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Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]6 <title>The LLVM Target-Independent Code Generator</title>
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Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]19</head>
20<body>
21
22<div class="doc_title">
23 The LLVM Target-Independent Code Generator
24</div>
25
26<ol>
27 <li><a href="#introduction">Introduction</a>
28 <ul>
29 <li><a href="#required">Required components in the code generator</a></li>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]30 <li><a href="#high-level-design">The high-level design of the code
31 generator</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]32 <li><a href="#tablegen">Using TableGen for target description</a></li>
33 </ul>
34 </li>
35 <li><a href="#targetdesc">Target description classes</a>
36 <ul>
37 <li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
38 <li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]39 <li><a href="#targetlowering">The <tt>TargetLowering</tt> class</a></li>
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]40 <li><a href="#targetregisterinfo">The <tt>TargetRegisterInfo</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]41 <li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
42 <li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]43 <li><a href="#targetsubtarget">The <tt>TargetSubtarget</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]44 <li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
45 </ul>
46 </li>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]47 <li><a href="#codegendesc">The "Machine" Code Generator classes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]48 <ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]49 <li><a href="#machineinstr">The <tt>MachineInstr</tt> class</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]50 <li><a href="#machinebasicblock">The <tt>MachineBasicBlock</tt>
51 class</a></li>
52 <li><a href="#machinefunction">The <tt>MachineFunction</tt> class</a></li>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]53 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]54 </li>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]55 <li><a href="#mc">The "MC" Layer</a>
56 <ul>
57 <li><a href="#mcstreamer">The <tt>MCStreamer</tt> API</a></li>
58 <li><a href="#mccontext">The <tt>MCContext</tt> class</a>
59 <li><a href="#mcsymbol">The <tt>MCSymbol</tt> class</a></li>
60 <li><a href="#mcsection">The <tt>MCSection</tt> class</a></li>
61 <li><a href="#mcinst">The <tt>MCInst</tt> class</a></li>
62 </ul>
63 </li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]64 <li><a href="#codegenalgs">Target-independent code generation algorithms</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]65 <ul>
66 <li><a href="#instselect">Instruction Selection</a>
67 <ul>
68 <li><a href="#selectiondag_intro">Introduction to SelectionDAGs</a></li>
69 <li><a href="#selectiondag_process">SelectionDAG Code Generation
70 Process</a></li>
71 <li><a href="#selectiondag_build">Initial SelectionDAG
72 Construction</a></li>
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]73 <li><a href="#selectiondag_legalize_types">SelectionDAG LegalizeTypes Phase</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]74 <li><a href="#selectiondag_legalize">SelectionDAG Legalize Phase</a></li>
75 <li><a href="#selectiondag_optimize">SelectionDAG Optimization
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]76 Phase: the DAG Combiner</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]77 <li><a href="#selectiondag_select">SelectionDAG Select Phase</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]78 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]79 Phase</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]80 <li><a href="#selectiondag_future">Future directions for the
81 SelectionDAG</a></li>
82 </ul></li>
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]83 <li><a href="#liveintervals">Live Intervals</a>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]84 <ul>
85 <li><a href="#livevariable_analysis">Live Variable Analysis</a></li>
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]86 <li><a href="#liveintervals_analysis">Live Intervals Analysis</a></li>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]87 </ul></li>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]88 <li><a href="#regalloc">Register Allocation</a>
89 <ul>
90 <li><a href="#regAlloc_represent">How registers are represented in
91 LLVM</a></li>
92 <li><a href="#regAlloc_howTo">Mapping virtual registers to physical
93 registers</a></li>
94 <li><a href="#regAlloc_twoAddr">Handling two address instructions</a></li>
95 <li><a href="#regAlloc_ssaDecon">The SSA deconstruction phase</a></li>
96 <li><a href="#regAlloc_fold">Instruction folding</a></li>
97 <li><a href="#regAlloc_builtIn">Built in register allocators</a></li>
98 </ul></li>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]99 <li><a href="#codeemit">Code Emission</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]100 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]101 </li>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]102 <li><a href="#nativeassembler">Implementing a Native Assembler</a></li>
103
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]104 <li><a href="#targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]105 <ul>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]106 <li><a href="#targetfeatures">Target Feature Matrix</a></li>
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]107 <li><a href="#tailcallopt">Tail call optimization</a></li>
Evan Chengdc444e92010-03-08 21:05:02 +0000[diff] [blame]108 <li><a href="#sibcallopt">Sibling call optimization</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]109 <li><a href="#x86">The X86 backend</a></li>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]110 <li><a href="#ppc">The PowerPC backend</a>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]111 <ul>
112 <li><a href="#ppc_abi">LLVM PowerPC ABI</a></li>
113 <li><a href="#ppc_frame">Frame Layout</a></li>
114 <li><a href="#ppc_prolog">Prolog/Epilog</a></li>
115 <li><a href="#ppc_dynamic">Dynamic Allocation</a></li>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]116 </ul></li>
117 </ul></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]118
119</ol>
120
121<div class="doc_author">
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]122 <p>Written by the LLVM Team.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]123</div>
124
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]125<div class="doc_warning">
126 <p>Warning: This is a work in progress.</p>
127</div>
128
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]129<!-- *********************************************************************** -->
130<div class="doc_section">
131 <a name="introduction">Introduction</a>
132</div>
133<!-- *********************************************************************** -->
134
135<div class="doc_text">
136
137<p>The LLVM target-independent code generator is a framework that provides a
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]138 suite of reusable components for translating the LLVM internal representation
139 to the machine code for a specified target&mdash;either in assembly form
140 (suitable for a static compiler) or in binary machine code format (usable for
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]141 a JIT compiler). The LLVM target-independent code generator consists of six
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]142 main components:</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]143
144<ol>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]145 <li><a href="#targetdesc">Abstract target description</a> interfaces which
146 capture important properties about various aspects of the machine,
147 independently of how they will be used. These interfaces are defined in
148 <tt>include/llvm/Target/</tt>.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]149
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]150 <li>Classes used to represent the <a href="#codegendesc">code being
151 generated</a> for a target. These classes are intended to be abstract
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]152 enough to represent the machine code for <i>any</i> target machine. These
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]153 classes are defined in <tt>include/llvm/CodeGen/</tt>. At this level,
154 concepts like "constant pool entries" and "jump tables" are explicitly
155 exposed.</li>
156
157 <li>Classes and algorithms used to represent code as the object file level,
158 the <a href="#mc">MC Layer</a>. These classes represent assembly level
159 constructs like labels, sections, and instructions. At this level,
160 concepts like "constant pool entries" and "jump tables" don't exist.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]161
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]162 <li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
163 various phases of native code generation (register allocation, scheduling,
164 stack frame representation, etc). This code lives
165 in <tt>lib/CodeGen/</tt>.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]166
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]167 <li><a href="#targetimpls">Implementations of the abstract target description
168 interfaces</a> for particular targets. These machine descriptions make
169 use of the components provided by LLVM, and can optionally provide custom
170 target-specific passes, to build complete code generators for a specific
171 target. Target descriptions live in <tt>lib/Target/</tt>.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]172
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]173 <li><a href="#jit">The target-independent JIT components</a>. The LLVM JIT is
174 completely target independent (it uses the <tt>TargetJITInfo</tt>
175 structure to interface for target-specific issues. The code for the
176 target-independent JIT lives in <tt>lib/ExecutionEngine/JIT</tt>.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]177</ol>
178
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]179<p>Depending on which part of the code generator you are interested in working
180 on, different pieces of this will be useful to you. In any case, you should
181 be familiar with the <a href="#targetdesc">target description</a>
182 and <a href="#codegendesc">machine code representation</a> classes. If you
183 want to add a backend for a new target, you will need
184 to <a href="#targetimpls">implement the target description</a> classes for
185 your new target and understand the <a href="LangRef.html">LLVM code
186 representation</a>. If you are interested in implementing a
187 new <a href="#codegenalgs">code generation algorithm</a>, it should only
188 depend on the target-description and machine code representation classes,
189 ensuring that it is portable.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]190
191</div>
192
193<!-- ======================================================================= -->
194<div class="doc_subsection">
195 <a name="required">Required components in the code generator</a>
196</div>
197
198<div class="doc_text">
199
200<p>The two pieces of the LLVM code generator are the high-level interface to the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]201 code generator and the set of reusable components that can be used to build
202 target-specific backends. The two most important interfaces
203 (<a href="#targetmachine"><tt>TargetMachine</tt></a>
204 and <a href="#targetdata"><tt>TargetData</tt></a>) are the only ones that are
205 required to be defined for a backend to fit into the LLVM system, but the
206 others must be defined if the reusable code generator components are going to
207 be used.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]208
209<p>This design has two important implications. The first is that LLVM can
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]210 support completely non-traditional code generation targets. For example, the
211 C backend does not require register allocation, instruction selection, or any
212 of the other standard components provided by the system. As such, it only
213 implements these two interfaces, and does its own thing. Another example of
214 a code generator like this is a (purely hypothetical) backend that converts
215 LLVM to the GCC RTL form and uses GCC to emit machine code for a target.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]216
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]217<p>This design also implies that it is possible to design and implement
218 radically different code generators in the LLVM system that do not make use
219 of any of the built-in components. Doing so is not recommended at all, but
220 could be required for radically different targets that do not fit into the
221 LLVM machine description model: FPGAs for example.</p>
Chris Lattner900bf8c2004-06-02 07:06:06 +0000[diff] [blame]222
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]223</div>
224
225<!-- ======================================================================= -->
226<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]227 <a name="high-level-design">The high-level design of the code generator</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]228</div>
229
230<div class="doc_text">
231
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]232<p>The LLVM target-independent code generator is designed to support efficient
233 and quality code generation for standard register-based microprocessors.
234 Code generation in this model is divided into the following stages:</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]235
236<ol>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]237 <li><b><a href="#instselect">Instruction Selection</a></b> &mdash; This phase
238 determines an efficient way to express the input LLVM code in the target
239 instruction set. This stage produces the initial code for the program in
240 the target instruction set, then makes use of virtual registers in SSA
241 form and physical registers that represent any required register
242 assignments due to target constraints or calling conventions. This step
243 turns the LLVM code into a DAG of target instructions.</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]244
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]245 <li><b><a href="#selectiondag_sched">Scheduling and Formation</a></b> &mdash;
246 This phase takes the DAG of target instructions produced by the
247 instruction selection phase, determines an ordering of the instructions,
248 then emits the instructions
249 as <tt><a href="#machineinstr">MachineInstr</a></tt>s with that ordering.
250 Note that we describe this in the <a href="#instselect">instruction
251 selection section</a> because it operates on
252 a <a href="#selectiondag_intro">SelectionDAG</a>.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]253
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]254 <li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> &mdash;
255 This optional stage consists of a series of machine-code optimizations
256 that operate on the SSA-form produced by the instruction selector.
257 Optimizations like modulo-scheduling or peephole optimization work
258 here.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]259
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]260 <li><b><a href="#regalloc">Register Allocation</a></b> &mdash; The target code
261 is transformed from an infinite virtual register file in SSA form to the
262 concrete register file used by the target. This phase introduces spill
263 code and eliminates all virtual register references from the program.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]264
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]265 <li><b><a href="#proepicode">Prolog/Epilog Code Insertion</a></b> &mdash; Once
266 the machine code has been generated for the function and the amount of
267 stack space required is known (used for LLVM alloca's and spill slots),
268 the prolog and epilog code for the function can be inserted and "abstract
269 stack location references" can be eliminated. This stage is responsible
270 for implementing optimizations like frame-pointer elimination and stack
271 packing.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]272
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]273 <li><b><a href="#latemco">Late Machine Code Optimizations</a></b> &mdash;
274 Optimizations that operate on "final" machine code can go here, such as
275 spill code scheduling and peephole optimizations.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]276
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]277 <li><b><a href="#codeemit">Code Emission</a></b> &mdash; The final stage
278 actually puts out the code for the current function, either in the target
279 assembler format or in machine code.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]280</ol>
281
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]282<p>The code generator is based on the assumption that the instruction selector
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]283 will use an optimal pattern matching selector to create high-quality
284 sequences of native instructions. Alternative code generator designs based
285 on pattern expansion and aggressive iterative peephole optimization are much
286 slower. This design permits efficient compilation (important for JIT
287 environments) and aggressive optimization (used when generating code offline)
288 by allowing components of varying levels of sophistication to be used for any
289 step of compilation.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]290
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]291<p>In addition to these stages, target implementations can insert arbitrary
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]292 target-specific passes into the flow. For example, the X86 target uses a
293 special pass to handle the 80x87 floating point stack architecture. Other
294 targets with unusual requirements can be supported with custom passes as
295 needed.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]296
297</div>
298
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]299<!-- ======================================================================= -->
300<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]301 <a name="tablegen">Using TableGen for target description</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]302</div>
303
304<div class="doc_text">
305
Chris Lattner5489e932004-06-01 18:35:00 +0000[diff] [blame]306<p>The target description classes require a detailed description of the target
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]307 architecture. These target descriptions often have a large amount of common
308 information (e.g., an <tt>add</tt> instruction is almost identical to a
309 <tt>sub</tt> instruction). In order to allow the maximum amount of
310 commonality to be factored out, the LLVM code generator uses
311 the <a href="TableGenFundamentals.html">TableGen</a> tool to describe big
312 chunks of the target machine, which allows the use of domain-specific and
313 target-specific abstractions to reduce the amount of repetition.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]314
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]315<p>As LLVM continues to be developed and refined, we plan to move more and more
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]316 of the target description to the <tt>.td</tt> form. Doing so gives us a
317 number of advantages. The most important is that it makes it easier to port
318 LLVM because it reduces the amount of C++ code that has to be written, and
319 the surface area of the code generator that needs to be understood before
320 someone can get something working. Second, it makes it easier to change
321 things. In particular, if tables and other things are all emitted
322 by <tt>tblgen</tt>, we only need a change in one place (<tt>tblgen</tt>) to
323 update all of the targets to a new interface.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]324
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]325</div>
326
327<!-- *********************************************************************** -->
328<div class="doc_section">
329 <a name="targetdesc">Target description classes</a>
330</div>
331<!-- *********************************************************************** -->
332
333<div class="doc_text">
334
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]335<p>The LLVM target description classes (located in the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]336 <tt>include/llvm/Target</tt> directory) provide an abstract description of
337 the target machine independent of any particular client. These classes are
338 designed to capture the <i>abstract</i> properties of the target (such as the
339 instructions and registers it has), and do not incorporate any particular
340 pieces of code generation algorithms.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]341
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]342<p>All of the target description classes (except the
343 <tt><a href="#targetdata">TargetData</a></tt> class) are designed to be
344 subclassed by the concrete target implementation, and have virtual methods
345 implemented. To get to these implementations, the
346 <tt><a href="#targetmachine">TargetMachine</a></tt> class provides accessors
347 that should be implemented by the target.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]348
349</div>
350
351<!-- ======================================================================= -->
352<div class="doc_subsection">
353 <a name="targetmachine">The <tt>TargetMachine</tt> class</a>
354</div>
355
356<div class="doc_text">
357
358<p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]359 access the target-specific implementations of the various target description
360 classes via the <tt>get*Info</tt> methods (<tt>getInstrInfo</tt>,
361 <tt>getRegisterInfo</tt>, <tt>getFrameInfo</tt>, etc.). This class is
362 designed to be specialized by a concrete target implementation
363 (e.g., <tt>X86TargetMachine</tt>) which implements the various virtual
364 methods. The only required target description class is
365 the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the code
366 generator components are to be used, the other interfaces should be
367 implemented as well.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]368
369</div>
370
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]371<!-- ======================================================================= -->
372<div class="doc_subsection">
373 <a name="targetdata">The <tt>TargetData</tt> class</a>
374</div>
375
376<div class="doc_text">
377
378<p>The <tt>TargetData</tt> class is the only required target description class,
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]379 and it is the only class that is not extensible (you cannot derived a new
380 class from it). <tt>TargetData</tt> specifies information about how the
381 target lays out memory for structures, the alignment requirements for various
382 data types, the size of pointers in the target, and whether the target is
383 little-endian or big-endian.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]384
385</div>
386
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]387<!-- ======================================================================= -->
388<div class="doc_subsection">
389 <a name="targetlowering">The <tt>TargetLowering</tt> class</a>
390</div>
391
392<div class="doc_text">
393
394<p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]395 selectors primarily to describe how LLVM code should be lowered to
396 SelectionDAG operations. Among other things, this class indicates:</p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]397
398<ul>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]399 <li>an initial register class to use for various <tt>ValueType</tt>s,</li>
400
401 <li>which operations are natively supported by the target machine,</li>
402
403 <li>the return type of <tt>setcc</tt> operations,</li>
404
405 <li>the type to use for shift amounts, and</li>
406
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]407 <li>various high-level characteristics, like whether it is profitable to turn
408 division by a constant into a multiplication sequence</li>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]409</ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]410
411</div>
412
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]413<!-- ======================================================================= -->
414<div class="doc_subsection">
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]415 <a name="targetregisterinfo">The <tt>TargetRegisterInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]416</div>
417
418<div class="doc_text">
419
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]420<p>The <tt>TargetRegisterInfo</tt> class is used to describe the register file
421 of the target and any interactions between the registers.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]422
423<p>Registers in the code generator are represented in the code generator by
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]424 unsigned integers. Physical registers (those that actually exist in the
425 target description) are unique small numbers, and virtual registers are
426 generally large. Note that register #0 is reserved as a flag value.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]427
428<p>Each register in the processor description has an associated
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]429 <tt>TargetRegisterDesc</tt> entry, which provides a textual name for the
430 register (used for assembly output and debugging dumps) and a set of aliases
431 (used to indicate whether one register overlaps with another).</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]432
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]433<p>In addition to the per-register description, the <tt>TargetRegisterInfo</tt>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]434 class exposes a set of processor specific register classes (instances of the
435 <tt>TargetRegisterClass</tt> class). Each register class contains sets of
436 registers that have the same properties (for example, they are all 32-bit
437 integer registers). Each SSA virtual register created by the instruction
438 selector has an associated register class. When the register allocator runs,
439 it replaces virtual registers with a physical register in the set.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]440
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]441<p>The target-specific implementations of these classes is auto-generated from
442 a <a href="TableGenFundamentals.html">TableGen</a> description of the
443 register file.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]444
445</div>
446
447<!-- ======================================================================= -->
448<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]449 <a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]450</div>
451
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]452<div class="doc_text">
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]453
454<p>The <tt>TargetInstrInfo</tt> class is used to describe the machine
455 instructions supported by the target. It is essentially an array of
456 <tt>TargetInstrDescriptor</tt> objects, each of which describes one
457 instruction the target supports. Descriptors define things like the mnemonic
458 for the opcode, the number of operands, the list of implicit register uses
459 and defs, whether the instruction has certain target-independent properties
460 (accesses memory, is commutable, etc), and holds any target-specific
461 flags.</p>
462
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]463</div>
464
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]465<!-- ======================================================================= -->
466<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]467 <a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]468</div>
469
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]470<div class="doc_text">
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]471
472<p>The <tt>TargetFrameInfo</tt> class is used to provide information about the
473 stack frame layout of the target. It holds the direction of stack growth, the
474 known stack alignment on entry to each function, and the offset to the local
475 area. The offset to the local area is the offset from the stack pointer on
476 function entry to the first location where function data (local variables,
477 spill locations) can be stored.</p>
478
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]479</div>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]480
481<!-- ======================================================================= -->
482<div class="doc_subsection">
483 <a name="targetsubtarget">The <tt>TargetSubtarget</tt> class</a>
484</div>
485
486<div class="doc_text">
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]487
488<p>The <tt>TargetSubtarget</tt> class is used to provide information about the
489 specific chip set being targeted. A sub-target informs code generation of
490 which instructions are supported, instruction latencies and instruction
491 execution itinerary; i.e., which processing units are used, in what order,
492 and for how long.</p>
493
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]494</div>
495
496
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]497<!-- ======================================================================= -->
498<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]499 <a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]500</div>
501
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]502<div class="doc_text">
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]503
504<p>The <tt>TargetJITInfo</tt> class exposes an abstract interface used by the
505 Just-In-Time code generator to perform target-specific activities, such as
506 emitting stubs. If a <tt>TargetMachine</tt> supports JIT code generation, it
507 should provide one of these objects through the <tt>getJITInfo</tt>
508 method.</p>
509
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]510</div>
511
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]512<!-- *********************************************************************** -->
513<div class="doc_section">
514 <a name="codegendesc">Machine code description classes</a>
515</div>
516<!-- *********************************************************************** -->
517
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]518<div class="doc_text">
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]519
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]520<p>At the high-level, LLVM code is translated to a machine specific
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]521 representation formed out of
522 <a href="#machinefunction"><tt>MachineFunction</tt></a>,
523 <a href="#machinebasicblock"><tt>MachineBasicBlock</tt></a>,
524 and <a href="#machineinstr"><tt>MachineInstr</tt></a> instances (defined
525 in <tt>include/llvm/CodeGen</tt>). This representation is completely target
526 agnostic, representing instructions in their most abstract form: an opcode
527 and a series of operands. This representation is designed to support both an
528 SSA representation for machine code, as well as a register allocated, non-SSA
529 form.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]530
531</div>
532
533<!-- ======================================================================= -->
534<div class="doc_subsection">
535 <a name="machineinstr">The <tt>MachineInstr</tt> class</a>
536</div>
537
538<div class="doc_text">
539
540<p>Target machine instructions are represented as instances of the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]541 <tt>MachineInstr</tt> class. This class is an extremely abstract way of
542 representing machine instructions. In particular, it only keeps track of an
543 opcode number and a set of operands.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]544
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]545<p>The opcode number is a simple unsigned integer that only has meaning to a
546 specific backend. All of the instructions for a target should be defined in
547 the <tt>*InstrInfo.td</tt> file for the target. The opcode enum values are
548 auto-generated from this description. The <tt>MachineInstr</tt> class does
549 not have any information about how to interpret the instruction (i.e., what
550 the semantics of the instruction are); for that you must refer to the
551 <tt><a href="#targetinstrinfo">TargetInstrInfo</a></tt> class.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]552
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]553<p>The operands of a machine instruction can be of several different types: a
554 register reference, a constant integer, a basic block reference, etc. In
555 addition, a machine operand should be marked as a def or a use of the value
556 (though only registers are allowed to be defs).</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]557
558<p>By convention, the LLVM code generator orders instruction operands so that
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]559 all register definitions come before the register uses, even on architectures
560 that are normally printed in other orders. For example, the SPARC add
561 instruction: "<tt>add %i1, %i2, %i3</tt>" adds the "%i1", and "%i2" registers
562 and stores the result into the "%i3" register. In the LLVM code generator,
563 the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the
564 destination first.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]565
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]566<p>Keeping destination (definition) operands at the beginning of the operand
567 list has several advantages. In particular, the debugging printer will print
568 the instruction like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]569
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]570<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]571<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]572%r3 = add %i1, %i2
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]573</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]574</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]575
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]576<p>Also if the first operand is a def, it is easier to <a href="#buildmi">create
577 instructions</a> whose only def is the first operand.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]578
579</div>
580
581<!-- _______________________________________________________________________ -->
582<div class="doc_subsubsection">
583 <a name="buildmi">Using the <tt>MachineInstrBuilder.h</tt> functions</a>
584</div>
585
586<div class="doc_text">
587
588<p>Machine instructions are created by using the <tt>BuildMI</tt> functions,
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]589 located in the <tt>include/llvm/CodeGen/MachineInstrBuilder.h</tt> file. The
590 <tt>BuildMI</tt> functions make it easy to build arbitrary machine
591 instructions. Usage of the <tt>BuildMI</tt> functions look like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]592
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]593<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]594<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]595// Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
596// instruction. The '1' specifies how many operands will be added.
597MachineInstr *MI = BuildMI(X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]598
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]599// Create the same instr, but insert it at the end of a basic block.
600MachineBasicBlock &amp;MBB = ...
601BuildMI(MBB, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]602
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]603// Create the same instr, but insert it before a specified iterator point.
604MachineBasicBlock::iterator MBBI = ...
605BuildMI(MBB, MBBI, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]606
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]607// Create a 'cmp Reg, 0' instruction, no destination reg.
608MI = BuildMI(X86::CMP32ri, 2).addReg(Reg).addImm(0);
609// Create an 'sahf' instruction which takes no operands and stores nothing.
610MI = BuildMI(X86::SAHF, 0);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]611
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]612// Create a self looping branch instruction.
613BuildMI(MBB, X86::JNE, 1).addMBB(&amp;MBB);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]614</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]615</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]616
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]617<p>The key thing to remember with the <tt>BuildMI</tt> functions is that you
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]618 have to specify the number of operands that the machine instruction will
619 take. This allows for efficient memory allocation. You also need to specify
620 if operands default to be uses of values, not definitions. If you need to
621 add a definition operand (other than the optional destination register), you
622 must explicitly mark it as such:</p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]623
624<div class="doc_code">
625<pre>
Bill Wendling587daed2009-05-13 21:33:08 +0000[diff] [blame]626MI.addReg(Reg, RegState::Define);
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]627</pre>
628</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]629
630</div>
631
632<!-- _______________________________________________________________________ -->
633<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]634 <a name="fixedregs">Fixed (preassigned) registers</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]635</div>
636
637<div class="doc_text">
638
639<p>One important issue that the code generator needs to be aware of is the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]640 presence of fixed registers. In particular, there are often places in the
641 instruction stream where the register allocator <em>must</em> arrange for a
642 particular value to be in a particular register. This can occur due to
643 limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
644 with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like
645 calling conventions. In any case, the instruction selector should emit code
646 that copies a virtual register into or out of a physical register when
647 needed.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]648
649<p>For example, consider this simple LLVM example:</p>
650
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]651<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]652<pre>
Matthijs Kooijman61399af2008-06-04 15:46:35 +0000[diff] [blame]653define i32 @test(i32 %X, i32 %Y) {
654 %Z = udiv i32 %X, %Y
655 ret i32 %Z
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]656}
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]657</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]658</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]659
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]660<p>The X86 instruction selector produces this machine code for the <tt>div</tt>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]661 and <tt>ret</tt> (use "<tt>llc X.bc -march=x86 -print-machineinstrs</tt>" to
662 get this):</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]663
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]664<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]665<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]666;; Start of div
667%EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
668%reg1027 = sar %reg1024, 31
669%EDX = mov %reg1027 ;; Sign extend X into EDX
670idiv %reg1025 ;; Divide by Y (in reg1025)
671%reg1026 = mov %EAX ;; Read the result (Z) out of EAX
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]672
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]673;; Start of ret
674%EAX = mov %reg1026 ;; 32-bit return value goes in EAX
675ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]676</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]677</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]678
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]679<p>By the end of code generation, the register allocator has coalesced the
680 registers and deleted the resultant identity moves producing the following
681 code:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]682
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]683<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]684<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]685;; X is in EAX, Y is in ECX
686mov %EAX, %EDX
687sar %EDX, 31
688idiv %ECX
689ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]690</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]691</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]692
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]693<p>This approach is extremely general (if it can handle the X86 architecture, it
694 can handle anything!) and allows all of the target specific knowledge about
695 the instruction stream to be isolated in the instruction selector. Note that
696 physical registers should have a short lifetime for good code generation, and
697 all physical registers are assumed dead on entry to and exit from basic
698 blocks (before register allocation). Thus, if you need a value to be live
699 across basic block boundaries, it <em>must</em> live in a virtual
700 register.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]701
702</div>
703
704<!-- _______________________________________________________________________ -->
705<div class="doc_subsubsection">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]706 <a name="ssa">Machine code in SSA form</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]707</div>
708
709<div class="doc_text">
710
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]711<p><tt>MachineInstr</tt>'s are initially selected in SSA-form, and are
712 maintained in SSA-form until register allocation happens. For the most part,
713 this is trivially simple since LLVM is already in SSA form; LLVM PHI nodes
714 become machine code PHI nodes, and virtual registers are only allowed to have
715 a single definition.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]716
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]717<p>After register allocation, machine code is no longer in SSA-form because
718 there are no virtual registers left in the code.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]719
720</div>
721
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]722<!-- ======================================================================= -->
723<div class="doc_subsection">
724 <a name="machinebasicblock">The <tt>MachineBasicBlock</tt> class</a>
725</div>
726
727<div class="doc_text">
728
729<p>The <tt>MachineBasicBlock</tt> class contains a list of machine instructions
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]730 (<tt><a href="#machineinstr">MachineInstr</a></tt> instances). It roughly
731 corresponds to the LLVM code input to the instruction selector, but there can
732 be a one-to-many mapping (i.e. one LLVM basic block can map to multiple
733 machine basic blocks). The <tt>MachineBasicBlock</tt> class has a
734 "<tt>getBasicBlock</tt>" method, which returns the LLVM basic block that it
735 comes from.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]736
737</div>
738
739<!-- ======================================================================= -->
740<div class="doc_subsection">
741 <a name="machinefunction">The <tt>MachineFunction</tt> class</a>
742</div>
743
744<div class="doc_text">
745
746<p>The <tt>MachineFunction</tt> class contains a list of machine basic blocks
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]747 (<tt><a href="#machinebasicblock">MachineBasicBlock</a></tt> instances). It
748 corresponds one-to-one with the LLVM function input to the instruction
749 selector. In addition to a list of basic blocks,
750 the <tt>MachineFunction</tt> contains a a <tt>MachineConstantPool</tt>,
751 a <tt>MachineFrameInfo</tt>, a <tt>MachineFunctionInfo</tt>, and a
752 <tt>MachineRegisterInfo</tt>. See
753 <tt>include/llvm/CodeGen/MachineFunction.h</tt> for more information.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]754
755</div>
756
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]757
758<!-- *********************************************************************** -->
759<div class="doc_section">
760 <a name="mc">The "MC" Layer</a>
761</div>
762<!-- *********************************************************************** -->
763
764<div class="doc_text">
765
766<p>
767The MC Layer is used to represent and process code at the raw machine code
768level, devoid of "high level" information like "constant pools", "jump tables",
769"global variables" or anything like that. At this level, LLVM handles things
770like label names, machine instructions, and sections in the object file. The
771code in this layer is used for a number of important purposes: the tail end of
772the code generator uses it to write a .s or .o file, and it is also used by the
773llvm-mc tool to implement standalone machine codeassemblers and disassemblers.
774</p>
775
776<p>
777This section describes some of the important classes. There are also a number
778of important subsystems that interact at this layer, they are described later
779in this manual.
780</p>
781
782</div>
783
784
785<!-- ======================================================================= -->
786<div class="doc_subsection">
787 <a name="mcstreamer">The <tt>MCStreamer</tt> API</a>
788</div>
789
790<div class="doc_text">
791
792<p>
793MCStreamer is best thought of as an assembler API. It is an abstract API which
794is <em>implemented</em> in different ways (e.g. to output a .s file, output an
795ELF .o file, etc) but whose API correspond directly to what you see in a .s
796file. MCStreamer has one method per directive, such as EmitLabel,
797EmitSymbolAttribute, SwitchSection, EmitValue (for .byte, .word), etc, which
798directly correspond to assembly level directives. It also has an
799EmitInstruction method, which is used to output an MCInst to the streamer.
800</p>
801
802<p>
803This API is most important for two clients: the llvm-mc stand-alone assembler is
804effectively a parser that parses a line, then invokes a method on MCStreamer. In
805the code generator, the <a href="#codeemit">Code Emission</a> phase of the code
806generator lowers higher level LLVM IR and Machine* constructs down to the MC
807layer, emitting directives through MCStreamer.</p>
808
809<p>
810On the implementation side of MCStreamer, there are two major implementations:
811one for writing out a .s file (MCAsmStreamer), and one for writing out a .o
812file (MCObjectStreamer). MCAsmStreamer is a straight-forward implementation
813that prints out a directive for each method (e.g. EmitValue -&gt; .byte), but
814MCObjectStreamer implements a full assembler.
815</p>
816
817</div>
818
819<!-- ======================================================================= -->
820<div class="doc_subsection">
821 <a name="mccontext">The <tt>MCContext</tt> class</a>
822</div>
823
824<div class="doc_text">
825
826<p>
827The MCContext class is the owner of a variety of uniqued data structures at the
828MC layer, including symbols, sections, etc. As such, this is the class that you
829interact with to create symbols and sections. This class can not be subclassed.
830</p>
831
832</div>
833
834<!-- ======================================================================= -->
835<div class="doc_subsection">
836 <a name="mcsymbol">The <tt>MCSymbol</tt> class</a>
837</div>
838
839<div class="doc_text">
840
841<p>
842The MCSymbol class represents a symbol (aka label) in the assembly file. There
843are two interesting kinds of symbols: assembler temporary symbols, and normal
844symbols. Assembler temporary symbols are used and processed by the assembler
845but are discarded when the object file is produced. The distinction is usually
846represented by adding a prefix to the label, for example "L" labels are
847assembler temporary labels in MachO.
848</p>
849
850<p>MCSymbols are created by MCContext and uniqued there. This means that
851MCSymbols can be compared for pointer equivalence to find out if they are the
852same symbol. Note that pointer inequality does not guarantee the labels will
853end up at different addresses though. It's perfectly legal to output something
854like this to the .s file:<p>
855
856<pre>
857 foo:
858 bar:
859 .byte 4
860</pre>
861
862<p>In this case, both the foo and bar symbols will have the same address.</p>
863
864</div>
865
866<!-- ======================================================================= -->
867<div class="doc_subsection">
868 <a name="mcsection">The <tt>MCSection</tt> class</a>
869</div>
870
871<div class="doc_text">
872
873<p>
874The MCSection class represents an object-file specific section. It is subclassed
875by object file specific implementations (e.g. <tt>MCSectionMachO</tt>,
876<tt>MCSectionCOFF</tt>, <tt>MCSectionELF</tt>) and these are created and uniqued
877by MCContext. The MCStreamer has a notion of the current section, which can be
878changed with the SwitchToSection method (which corresponds to a ".section"
879directive in a .s file).
880</p>
881
882</div>
883
884<!-- ======================================================================= -->
885<div class="doc_subsection">
Benjamin Kramer943beeb2010-10-30 21:07:28 +0000[diff] [blame]886 <a name="mcinst">The <tt>MCInst</tt> class</a>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]887</div>
888
889<div class="doc_text">
890
891<p>
892The MCInst class is a target-independent representation of an instruction. It
893is a simple class (much more so than <a href="#machineinstr">MachineInstr</a>)
894that holds a target-specific opcode and a vector of MCOperands. MCOperand, in
895turn, is a simple discriminated union of three cases: 1) a simple immediate,
8962) a target register ID, 3) a symbolic expression (e.g. "Lfoo-Lbar+42") as an
897MCExpr.
898</p>
899
900<p>MCInst is the common currency used to represent machine instructions at the
901MC layer. It is the type used by the instruction encoder, the instruction
902printer, and the type generated by the assembly parser and disassembler.
903</p>
904
905</div>
906
907
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]908<!-- *********************************************************************** -->
909<div class="doc_section">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]910 <a name="codegenalgs">Target-independent code generation algorithms</a>
911</div>
912<!-- *********************************************************************** -->
913
914<div class="doc_text">
915
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]916<p>This section documents the phases described in the
917 <a href="#high-level-design">high-level design of the code generator</a>.
918 It explains how they work and some of the rationale behind their design.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]919
920</div>
921
922<!-- ======================================================================= -->
923<div class="doc_subsection">
924 <a name="instselect">Instruction Selection</a>
925</div>
926
927<div class="doc_text">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]928
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]929<p>Instruction Selection is the process of translating LLVM code presented to
930 the code generator into target-specific machine instructions. There are
931 several well-known ways to do this in the literature. LLVM uses a
932 SelectionDAG based instruction selector.</p>
933
934<p>Portions of the DAG instruction selector are generated from the target
935 description (<tt>*.td</tt>) files. Our goal is for the entire instruction
936 selector to be generated from these <tt>.td</tt> files, though currently
937 there are still things that require custom C++ code.</p>
938
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]939</div>
940
941<!-- _______________________________________________________________________ -->
942<div class="doc_subsubsection">
943 <a name="selectiondag_intro">Introduction to SelectionDAGs</a>
944</div>
945
946<div class="doc_text">
947
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]948<p>The SelectionDAG provides an abstraction for code representation in a way
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]949 that is amenable to instruction selection using automatic techniques
950 (e.g. dynamic-programming based optimal pattern matching selectors). It is
951 also well-suited to other phases of code generation; in particular,
952 instruction scheduling (SelectionDAG's are very close to scheduling DAGs
953 post-selection). Additionally, the SelectionDAG provides a host
954 representation where a large variety of very-low-level (but
955 target-independent) <a href="#selectiondag_optimize">optimizations</a> may be
956 performed; ones which require extensive information about the instructions
957 efficiently supported by the target.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]958
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]959<p>The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]960 <tt>SDNode</tt> class. The primary payload of the <tt>SDNode</tt> is its
961 operation code (Opcode) that indicates what operation the node performs and
962 the operands to the operation. The various operation node types are
963 described at the top of the <tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt>
964 file.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]965
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]966<p>Although most operations define a single value, each node in the graph may
967 define multiple values. For example, a combined div/rem operation will
968 define both the dividend and the remainder. Many other situations require
969 multiple values as well. Each node also has some number of operands, which
970 are edges to the node defining the used value. Because nodes may define
971 multiple values, edges are represented by instances of the <tt>SDValue</tt>
972 class, which is a <tt>&lt;SDNode, unsigned&gt;</tt> pair, indicating the node
973 and result value being used, respectively. Each value produced by
974 an <tt>SDNode</tt> has an associated <tt>MVT</tt> (Machine Value Type)
975 indicating what the type of the value is.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]976
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]977<p>SelectionDAGs contain two different kinds of values: those that represent
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]978 data flow and those that represent control flow dependencies. Data values
979 are simple edges with an integer or floating point value type. Control edges
980 are represented as "chain" edges which are of type <tt>MVT::Other</tt>.
981 These edges provide an ordering between nodes that have side effects (such as
982 loads, stores, calls, returns, etc). All nodes that have side effects should
983 take a token chain as input and produce a new one as output. By convention,
984 token chain inputs are always operand #0, and chain results are always the
985 last value produced by an operation.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]986
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]987<p>A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]988 always a marker node with an Opcode of <tt>ISD::EntryToken</tt>. The Root
989 node is the final side-effecting node in the token chain. For example, in a
990 single basic block function it would be the return node.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]991
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]992<p>One important concept for SelectionDAGs is the notion of a "legal" vs.
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]993 "illegal" DAG. A legal DAG for a target is one that only uses supported
994 operations and supported types. On a 32-bit PowerPC, for example, a DAG with
995 a value of type i1, i8, i16, or i64 would be illegal, as would a DAG that
996 uses a SREM or UREM operation. The
997 <a href="#selectinodag_legalize_types">legalize types</a> and
998 <a href="#selectiondag_legalize">legalize operations</a> phases are
999 responsible for turning an illegal DAG into a legal DAG.</p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1000
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1001</div>
1002
1003<!-- _______________________________________________________________________ -->
1004<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1005 <a name="selectiondag_process">SelectionDAG Instruction Selection Process</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1006</div>
1007
1008<div class="doc_text">
1009
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1010<p>SelectionDAG-based instruction selection consists of the following steps:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1011
1012<ol>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1013 <li><a href="#selectiondag_build">Build initial DAG</a> &mdash; This stage
1014 performs a simple translation from the input LLVM code to an illegal
1015 SelectionDAG.</li>
1016
1017 <li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> &mdash; This
1018 stage performs simple optimizations on the SelectionDAG to simplify it,
1019 and recognize meta instructions (like rotates
1020 and <tt>div</tt>/<tt>rem</tt> pairs) for targets that support these meta
1021 operations. This makes the resultant code more efficient and
1022 the <a href="#selectiondag_select">select instructions from DAG</a> phase
1023 (below) simpler.</li>
1024
1025 <li><a href="#selectiondag_legalize_types">Legalize SelectionDAG Types</a>
1026 &mdash; This stage transforms SelectionDAG nodes to eliminate any types
1027 that are unsupported on the target.</li>
1028
1029 <li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> &mdash; The
1030 SelectionDAG optimizer is run to clean up redundancies exposed by type
1031 legalization.</li>
1032
1033 <li><a href="#selectiondag_legalize">Legalize SelectionDAG Types</a> &mdash;
1034 This stage transforms SelectionDAG nodes to eliminate any types that are
1035 unsupported on the target.</li>
1036
1037 <li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> &mdash; The
1038 SelectionDAG optimizer is run to eliminate inefficiencies introduced by
1039 operation legalization.</li>
1040
1041 <li><a href="#selectiondag_select">Select instructions from DAG</a> &mdash;
1042 Finally, the target instruction selector matches the DAG operations to
1043 target instructions. This process translates the target-independent input
1044 DAG into another DAG of target instructions.</li>
1045
1046 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation</a>
1047 &mdash; The last phase assigns a linear order to the instructions in the
1048 target-instruction DAG and emits them into the MachineFunction being
1049 compiled. This step uses traditional prepass scheduling techniques.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1050</ol>
1051
1052<p>After all of these steps are complete, the SelectionDAG is destroyed and the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1053 rest of the code generation passes are run.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1054
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1055<p>One great way to visualize what is going on here is to take advantage of a
1056 few LLC command line options. The following options pop up a window
1057 displaying the SelectionDAG at specific times (if you only get errors printed
1058 to the console while using this, you probably
1059 <a href="ProgrammersManual.html#ViewGraph">need to configure your system</a>
1060 to add support for it).</p>
Dan Gohman8c9c55f2008-09-10 22:23:41 +0000[diff] [blame]1061
1062<ul>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1063 <li><tt>-view-dag-combine1-dags</tt> displays the DAG after being built,
1064 before the first optimization pass.</li>
1065
1066 <li><tt>-view-legalize-dags</tt> displays the DAG before Legalization.</li>
1067
1068 <li><tt>-view-dag-combine2-dags</tt> displays the DAG before the second
1069 optimization pass.</li>
1070
1071 <li><tt>-view-isel-dags</tt> displays the DAG before the Select phase.</li>
1072
1073 <li><tt>-view-sched-dags</tt> displays the DAG before Scheduling.</li>
Dan Gohman8c9c55f2008-09-10 22:23:41 +0000[diff] [blame]1074</ul>
1075
1076<p>The <tt>-view-sunit-dags</tt> displays the Scheduler's dependency graph.
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1077 This graph is based on the final SelectionDAG, with nodes that must be
1078 scheduled together bundled into a single scheduling-unit node, and with
1079 immediate operands and other nodes that aren't relevant for scheduling
1080 omitted.</p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1081
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1082</div>
1083
1084<!-- _______________________________________________________________________ -->
1085<div class="doc_subsubsection">
1086 <a name="selectiondag_build">Initial SelectionDAG Construction</a>
1087</div>
1088
1089<div class="doc_text">
1090
Bill Wendling16448772006-08-28 03:04:05 +0000[diff] [blame]1091<p>The initial SelectionDAG is na&iuml;vely peephole expanded from the LLVM
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1092 input by the <tt>SelectionDAGLowering</tt> class in the
1093 <tt>lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp</tt> file. The intent of
1094 this pass is to expose as much low-level, target-specific details to the
1095 SelectionDAG as possible. This pass is mostly hard-coded (e.g. an
1096 LLVM <tt>add</tt> turns into an <tt>SDNode add</tt> while a
1097 <tt>getelementptr</tt> is expanded into the obvious arithmetic). This pass
1098 requires target-specific hooks to lower calls, returns, varargs, etc. For
1099 these features, the <tt><a href="#targetlowering">TargetLowering</a></tt>
1100 interface is used.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1101
1102</div>
1103
1104<!-- _______________________________________________________________________ -->
1105<div class="doc_subsubsection">
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1106 <a name="selectiondag_legalize_types">SelectionDAG LegalizeTypes Phase</a>
1107</div>
1108
1109<div class="doc_text">
1110
1111<p>The Legalize phase is in charge of converting a DAG to only use the types
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1112 that are natively supported by the target.</p>
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1113
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1114<p>There are two main ways of converting values of unsupported scalar types to
1115 values of supported types: converting small types to larger types
1116 ("promoting"), and breaking up large integer types into smaller ones
1117 ("expanding"). For example, a target might require that all f32 values are
1118 promoted to f64 and that all i1/i8/i16 values are promoted to i32. The same
1119 target might require that all i64 values be expanded into pairs of i32
1120 values. These changes can insert sign and zero extensions as needed to make
1121 sure that the final code has the same behavior as the input.</p>
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1122
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1123<p>There are two main ways of converting values of unsupported vector types to
1124 value of supported types: splitting vector types, multiple times if
1125 necessary, until a legal type is found, and extending vector types by adding
1126 elements to the end to round them out to legal types ("widening"). If a
1127 vector gets split all the way down to single-element parts with no supported
1128 vector type being found, the elements are converted to scalars
1129 ("scalarizing").</p>
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1130
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1131<p>A target implementation tells the legalizer which types are supported (and
1132 which register class to use for them) by calling the
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1133 <tt>addRegisterClass</tt> method in its TargetLowering constructor.</p>
1134
1135</div>
1136
1137<!-- _______________________________________________________________________ -->
1138<div class="doc_subsubsection">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1139 <a name="selectiondag_legalize">SelectionDAG Legalize Phase</a>
1140</div>
1141
1142<div class="doc_text">
1143
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1144<p>The Legalize phase is in charge of converting a DAG to only use the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1145 operations that are natively supported by the target.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1146
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1147<p>Targets often have weird constraints, such as not supporting every operation
1148 on every supported datatype (e.g. X86 does not support byte conditional moves
1149 and PowerPC does not support sign-extending loads from a 16-bit memory
1150 location). Legalize takes care of this by open-coding another sequence of
1151 operations to emulate the operation ("expansion"), by promoting one type to a
1152 larger type that supports the operation ("promotion"), or by using a
1153 target-specific hook to implement the legalization ("custom").</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1154
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1155<p>A target implementation tells the legalizer which operations are not
1156 supported (and which of the above three actions to take) by calling the
1157 <tt>setOperationAction</tt> method in its <tt>TargetLowering</tt>
1158 constructor.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1159
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1160<p>Prior to the existence of the Legalize passes, we required that every target
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1161 <a href="#selectiondag_optimize">selector</a> supported and handled every
1162 operator and type even if they are not natively supported. The introduction
1163 of the Legalize phases allows all of the canonicalization patterns to be
1164 shared across targets, and makes it very easy to optimize the canonicalized
1165 code because it is still in the form of a DAG.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1166
1167</div>
1168
1169<!-- _______________________________________________________________________ -->
1170<div class="doc_subsubsection">
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1171 <a name="selectiondag_optimize">SelectionDAG Optimization Phase: the DAG
1172 Combiner</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1173</div>
1174
1175<div class="doc_text">
1176
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1177<p>The SelectionDAG optimization phase is run multiple times for code
1178 generation, immediately after the DAG is built and once after each
1179 legalization. The first run of the pass allows the initial code to be
1180 cleaned up (e.g. performing optimizations that depend on knowing that the
1181 operators have restricted type inputs). Subsequent runs of the pass clean up
1182 the messy code generated by the Legalize passes, which allows Legalize to be
1183 very simple (it can focus on making code legal instead of focusing on
1184 generating <em>good</em> and legal code).</p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1185
1186<p>One important class of optimizations performed is optimizing inserted sign
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1187 and zero extension instructions. We currently use ad-hoc techniques, but
1188 could move to more rigorous techniques in the future. Here are some good
1189 papers on the subject:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1190
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1191<p>"<a href="http://www.eecs.harvard.edu/~nr/pubs/widen-abstract.html">Widening
1192 integer arithmetic</a>"<br>
1193 Kevin Redwine and Norman Ramsey<br>
1194 International Conference on Compiler Construction (CC) 2004</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1195
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1196<p>"<a href="http://portal.acm.org/citation.cfm?doid=512529.512552">Effective
1197 sign extension elimination</a>"<br>
1198 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
1199 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
1200 and Implementation.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1201
1202</div>
1203
1204<!-- _______________________________________________________________________ -->
1205<div class="doc_subsubsection">
1206 <a name="selectiondag_select">SelectionDAG Select Phase</a>
1207</div>
1208
1209<div class="doc_text">
1210
1211<p>The Select phase is the bulk of the target-specific code for instruction
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1212 selection. This phase takes a legal SelectionDAG as input, pattern matches
1213 the instructions supported by the target to this DAG, and produces a new DAG
1214 of target code. For example, consider the following LLVM fragment:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1215
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1216<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1217<pre>
Dan Gohmana9445e12010-03-02 01:11:08 +0000[diff] [blame]1218%t1 = fadd float %W, %X
1219%t2 = fmul float %t1, %Y
1220%t3 = fadd float %t2, %Z
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1221</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1222</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1223
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1224<p>This LLVM code corresponds to a SelectionDAG that looks basically like
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1225 this:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1226
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1227<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1228<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1229(fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1230</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1231</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1232
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1233<p>If a target supports floating point multiply-and-add (FMA) operations, one of
1234 the adds can be merged with the multiply. On the PowerPC, for example, the
1235 output of the instruction selector might look like this DAG:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1236
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1237<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1238<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1239(FMADDS (FADDS W, X), Y, Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1240</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1241</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1242
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1243<p>The <tt>FMADDS</tt> instruction is a ternary instruction that multiplies its
1244first two operands and adds the third (as single-precision floating-point
1245numbers). The <tt>FADDS</tt> instruction is a simple binary single-precision
1246add instruction. To perform this pattern match, the PowerPC backend includes
1247the following instruction definitions:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1248
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1249<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1250<pre>
1251def FMADDS : AForm_1&lt;59, 29,
1252 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1253 "fmadds $FRT, $FRA, $FRC, $FRB",
1254 [<b>(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1255 F4RC:$FRB))</b>]&gt;;
1256def FADDS : AForm_2&lt;59, 21,
1257 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1258 "fadds $FRT, $FRA, $FRB",
1259 [<b>(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))</b>]&gt;;
1260</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1261</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1262
1263<p>The portion of the instruction definition in bold indicates the pattern used
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1264 to match the instruction. The DAG operators
1265 (like <tt>fmul</tt>/<tt>fadd</tt>) are defined in
Dan Gohman6a4824c2010-03-25 00:03:04 +0000[diff] [blame]1266 the <tt>include/llvm/Target/TargetSelectionDAG.td</tt> file. "
1267 <tt>F4RC</tt>" is the register class of the input and result values.</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1268
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1269<p>The TableGen DAG instruction selector generator reads the instruction
1270 patterns in the <tt>.td</tt> file and automatically builds parts of the
1271 pattern matching code for your target. It has the following strengths:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1272
1273<ul>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1274 <li>At compiler-compiler time, it analyzes your instruction patterns and tells
1275 you if your patterns make sense or not.</li>
1276
1277 <li>It can handle arbitrary constraints on operands for the pattern match. In
1278 particular, it is straight-forward to say things like "match any immediate
1279 that is a 13-bit sign-extended value". For examples, see the
1280 <tt>immSExt16</tt> and related <tt>tblgen</tt> classes in the PowerPC
1281 backend.</li>
1282
1283 <li>It knows several important identities for the patterns defined. For
1284 example, it knows that addition is commutative, so it allows the
1285 <tt>FMADDS</tt> pattern above to match "<tt>(fadd X, (fmul Y, Z))</tt>" as
1286 well as "<tt>(fadd (fmul X, Y), Z)</tt>", without the target author having
1287 to specially handle this case.</li>
1288
1289 <li>It has a full-featured type-inferencing system. In particular, you should
1290 rarely have to explicitly tell the system what type parts of your patterns
1291 are. In the <tt>FMADDS</tt> case above, we didn't have to tell
1292 <tt>tblgen</tt> that all of the nodes in the pattern are of type 'f32'.
1293 It was able to infer and propagate this knowledge from the fact that
1294 <tt>F4RC</tt> has type 'f32'.</li>
1295
1296 <li>Targets can define their own (and rely on built-in) "pattern fragments".
1297 Pattern fragments are chunks of reusable patterns that get inlined into
1298 your patterns during compiler-compiler time. For example, the integer
1299 "<tt>(not x)</tt>" operation is actually defined as a pattern fragment
1300 that expands as "<tt>(xor x, -1)</tt>", since the SelectionDAG does not
1301 have a native '<tt>not</tt>' operation. Targets can define their own
1302 short-hand fragments as they see fit. See the definition of
1303 '<tt>not</tt>' and '<tt>ineg</tt>' for examples.</li>
1304
1305 <li>In addition to instructions, targets can specify arbitrary patterns that
1306 map to one or more instructions using the 'Pat' class. For example, the
1307 PowerPC has no way to load an arbitrary integer immediate into a register
1308 in one instruction. To tell tblgen how to do this, it defines:
1309 <br>
1310 <br>
1311<div class="doc_code">
1312<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1313// Arbitrary immediate support. Implement in terms of LIS/ORI.
1314def : Pat&lt;(i32 imm:$imm),
1315 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))&gt;;
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1316</pre>
1317</div>
1318 <br>
1319 If none of the single-instruction patterns for loading an immediate into a
1320 register match, this will be used. This rule says "match an arbitrary i32
1321 immediate, turning it into an <tt>ORI</tt> ('or a 16-bit immediate') and
1322 an <tt>LIS</tt> ('load 16-bit immediate, where the immediate is shifted to
1323 the left 16 bits') instruction". To make this work, the
1324 <tt>LO16</tt>/<tt>HI16</tt> node transformations are used to manipulate
1325 the input immediate (in this case, take the high or low 16-bits of the
1326 immediate).</li>
1327
1328 <li>While the system does automate a lot, it still allows you to write custom
1329 C++ code to match special cases if there is something that is hard to
1330 express.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1331</ul>
1332
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1333<p>While it has many strengths, the system currently has some limitations,
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1334 primarily because it is a work in progress and is not yet finished:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1335
1336<ul>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1337 <li>Overall, there is no way to define or match SelectionDAG nodes that define
Dan Gohmane370c802009-04-22 15:55:31 +0000[diff] [blame]1338 multiple values (e.g. <tt>SMUL_LOHI</tt>, <tt>LOAD</tt>, <tt>CALL</tt>,
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1339 etc). This is the biggest reason that you currently still <em>have
1340 to</em> write custom C++ code for your instruction selector.</li>
1341
1342 <li>There is no great way to support matching complex addressing modes yet.
1343 In the future, we will extend pattern fragments to allow them to define
1344 multiple values (e.g. the four operands of the <a href="#x86_memory">X86
1345 addressing mode</a>, which are currently matched with custom C++ code).
1346 In addition, we'll extend fragments so that a fragment can match multiple
1347 different patterns.</li>
1348
1349 <li>We don't automatically infer flags like isStore/isLoad yet.</li>
1350
1351 <li>We don't automatically generate the set of supported registers and
1352 operations for the <a href="#selectiondag_legalize">Legalizer</a>
1353 yet.</li>
1354
1355 <li>We don't have a way of tying in custom legalized nodes yet.</li>
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1356</ul>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1357
1358<p>Despite these limitations, the instruction selector generator is still quite
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1359 useful for most of the binary and logical operations in typical instruction
1360 sets. If you run into any problems or can't figure out how to do something,
1361 please let Chris know!</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1362
1363</div>
1364
1365<!-- _______________________________________________________________________ -->
1366<div class="doc_subsubsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1367 <a name="selectiondag_sched">SelectionDAG Scheduling and Formation Phase</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1368</div>
1369
1370<div class="doc_text">
1371
1372<p>The scheduling phase takes the DAG of target instructions from the selection
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1373 phase and assigns an order. The scheduler can pick an order depending on
1374 various constraints of the machines (i.e. order for minimal register pressure
1375 or try to cover instruction latencies). Once an order is established, the
1376 DAG is converted to a list
1377 of <tt><a href="#machineinstr">MachineInstr</a></tt>s and the SelectionDAG is
1378 destroyed.</p>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1379
Jeff Cohen0b81cda2005-10-24 16:54:55 +0000[diff] [blame]1380<p>Note that this phase is logically separate from the instruction selection
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1381 phase, but is tied to it closely in the code because it operates on
1382 SelectionDAGs.</p>
Chris Lattnerc38959f2005-10-17 03:09:31 +0000[diff] [blame]1383
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1384</div>
1385
1386<!-- _______________________________________________________________________ -->
1387<div class="doc_subsubsection">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1388 <a name="selectiondag_future">Future directions for the SelectionDAG</a>
1389</div>
1390
1391<div class="doc_text">
1392
1393<ol>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1394 <li>Optional function-at-a-time selection.</li>
1395
1396 <li>Auto-generate entire selector from <tt>.td</tt> file.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1397</ol>
1398
1399</div>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1400
1401<!-- ======================================================================= -->
1402<div class="doc_subsection">
1403 <a name="ssamco">SSA-based Machine Code Optimizations</a>
1404</div>
1405<div class="doc_text"><p>To Be Written</p></div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1406
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1407<!-- ======================================================================= -->
1408<div class="doc_subsection">
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1409 <a name="liveintervals">Live Intervals</a>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1410</div>
1411
1412<div class="doc_text">
1413
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1414<p>Live Intervals are the ranges (intervals) where a variable is <i>live</i>.
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1415 They are used by some <a href="#regalloc">register allocator</a> passes to
1416 determine if two or more virtual registers which require the same physical
1417 register are live at the same point in the program (i.e., they conflict).
1418 When this situation occurs, one virtual register must be <i>spilled</i>.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1419
1420</div>
1421
1422<!-- _______________________________________________________________________ -->
1423<div class="doc_subsubsection">
1424 <a name="livevariable_analysis">Live Variable Analysis</a>
1425</div>
1426
1427<div class="doc_text">
1428
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1429<p>The first step in determining the live intervals of variables is to calculate
1430 the set of registers that are immediately dead after the instruction (i.e.,
1431 the instruction calculates the value, but it is never used) and the set of
1432 registers that are used by the instruction, but are never used after the
1433 instruction (i.e., they are killed). Live variable information is computed
1434 for each <i>virtual</i> register and <i>register allocatable</i> physical
1435 register in the function. This is done in a very efficient manner because it
1436 uses SSA to sparsely compute lifetime information for virtual registers
1437 (which are in SSA form) and only has to track physical registers within a
1438 block. Before register allocation, LLVM can assume that physical registers
1439 are only live within a single basic block. This allows it to do a single,
1440 local analysis to resolve physical register lifetimes within each basic
1441 block. If a physical register is not register allocatable (e.g., a stack
1442 pointer or condition codes), it is not tracked.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1443
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1444<p>Physical registers may be live in to or out of a function. Live in values are
1445 typically arguments in registers. Live out values are typically return values
1446 in registers. Live in values are marked as such, and are given a dummy
1447 "defining" instruction during live intervals analysis. If the last basic
1448 block of a function is a <tt>return</tt>, then it's marked as using all live
1449 out values in the function.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1450
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1451<p><tt>PHI</tt> nodes need to be handled specially, because the calculation of
1452 the live variable information from a depth first traversal of the CFG of the
1453 function won't guarantee that a virtual register used by the <tt>PHI</tt>
1454 node is defined before it's used. When a <tt>PHI</tt> node is encountered,
1455 only the definition is handled, because the uses will be handled in other
1456 basic blocks.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1457
1458<p>For each <tt>PHI</tt> node of the current basic block, we simulate an
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1459 assignment at the end of the current basic block and traverse the successor
1460 basic blocks. If a successor basic block has a <tt>PHI</tt> node and one of
1461 the <tt>PHI</tt> node's operands is coming from the current basic block, then
1462 the variable is marked as <i>alive</i> within the current basic block and all
1463 of its predecessor basic blocks, until the basic block with the defining
1464 instruction is encountered.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1465
1466</div>
1467
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1468<!-- _______________________________________________________________________ -->
1469<div class="doc_subsubsection">
1470 <a name="liveintervals_analysis">Live Intervals Analysis</a>
1471</div>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1472
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1473<div class="doc_text">
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1474
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1475<p>We now have the information available to perform the live intervals analysis
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1476 and build the live intervals themselves. We start off by numbering the basic
1477 blocks and machine instructions. We then handle the "live-in" values. These
1478 are in physical registers, so the physical register is assumed to be killed
1479 by the end of the basic block. Live intervals for virtual registers are
1480 computed for some ordering of the machine instructions <tt>[1, N]</tt>. A
1481 live interval is an interval <tt>[i, j)</tt>, where <tt>1 &lt;= i &lt;= j
1482 &lt; N</tt>, for which a variable is live.</p>
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1483
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1484<p><i><b>More to come...</b></i></p>
1485
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1486</div>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1487
1488<!-- ======================================================================= -->
1489<div class="doc_subsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1490 <a name="regalloc">Register Allocation</a>
1491</div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1492
1493<div class="doc_text">
1494
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1495<p>The <i>Register Allocation problem</i> consists in mapping a program
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1496 <i>P<sub>v</sub></i>, that can use an unbounded number of virtual registers,
1497 to a program <i>P<sub>p</sub></i> that contains a finite (possibly small)
1498 number of physical registers. Each target architecture has a different number
1499 of physical registers. If the number of physical registers is not enough to
1500 accommodate all the virtual registers, some of them will have to be mapped
1501 into memory. These virtuals are called <i>spilled virtuals</i>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1502
1503</div>
1504
1505<!-- _______________________________________________________________________ -->
1506
1507<div class="doc_subsubsection">
1508 <a name="regAlloc_represent">How registers are represented in LLVM</a>
1509</div>
1510
1511<div class="doc_text">
1512
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1513<p>In LLVM, physical registers are denoted by integer numbers that normally
1514 range from 1 to 1023. To see how this numbering is defined for a particular
1515 architecture, you can read the <tt>GenRegisterNames.inc</tt> file for that
1516 architecture. For instance, by
1517 inspecting <tt>lib/Target/X86/X86GenRegisterNames.inc</tt> we see that the
1518 32-bit register <tt>EAX</tt> is denoted by 15, and the MMX register
1519 <tt>MM0</tt> is mapped to 48.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1520
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1521<p>Some architectures contain registers that share the same physical location. A
1522 notable example is the X86 platform. For instance, in the X86 architecture,
1523 the registers <tt>EAX</tt>, <tt>AX</tt> and <tt>AL</tt> share the first eight
1524 bits. These physical registers are marked as <i>aliased</i> in LLVM. Given a
1525 particular architecture, you can check which registers are aliased by
1526 inspecting its <tt>RegisterInfo.td</tt> file. Moreover, the method
1527 <tt>TargetRegisterInfo::getAliasSet(p_reg)</tt> returns an array containing
1528 all the physical registers aliased to the register <tt>p_reg</tt>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1529
1530<p>Physical registers, in LLVM, are grouped in <i>Register Classes</i>.
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1531 Elements in the same register class are functionally equivalent, and can be
1532 interchangeably used. Each virtual register can only be mapped to physical
1533 registers of a particular class. For instance, in the X86 architecture, some
1534 virtuals can only be allocated to 8 bit registers. A register class is
1535 described by <tt>TargetRegisterClass</tt> objects. To discover if a virtual
1536 register is compatible with a given physical, this code can be used:</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1537
1538<div class="doc_code">
1539<pre>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]1540bool RegMapping_Fer::compatible_class(MachineFunction &amp;mf,
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1541 unsigned v_reg,
1542 unsigned p_reg) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1543 assert(TargetRegisterInfo::isPhysicalRegister(p_reg) &amp;&amp;
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1544 "Target register must be physical");
Chris Lattner534bcfb2007-12-31 04:16:08 +0000[diff] [blame]1545 const TargetRegisterClass *trc = mf.getRegInfo().getRegClass(v_reg);
1546 return trc-&gt;contains(p_reg);
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1547}
1548</pre>
1549</div>
1550
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1551<p>Sometimes, mostly for debugging purposes, it is useful to change the number
1552 of physical registers available in the target architecture. This must be done
1553 statically, inside the <tt>TargetRegsterInfo.td</tt> file. Just <tt>grep</tt>
1554 for <tt>RegisterClass</tt>, the last parameter of which is a list of
1555 registers. Just commenting some out is one simple way to avoid them being
1556 used. A more polite way is to explicitly exclude some registers from
Dan Gohmand2cb3d22009-07-24 00:30:09 +0000[diff] [blame]1557 the <i>allocation order</i>. See the definition of the <tt>GR8</tt> register
1558 class in <tt>lib/Target/X86/X86RegisterInfo.td</tt> for an example of this.
1559 </p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1560
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1561<p>Virtual registers are also denoted by integer numbers. Contrary to physical
1562 registers, different virtual registers never share the same number. The
1563 smallest virtual register is normally assigned the number 1024. This may
1564 change, so, in order to know which is the first virtual register, you should
1565 access <tt>TargetRegisterInfo::FirstVirtualRegister</tt>. Any register whose
1566 number is greater than or equal
1567 to <tt>TargetRegisterInfo::FirstVirtualRegister</tt> is considered a virtual
1568 register. Whereas physical registers are statically defined in
1569 a <tt>TargetRegisterInfo.td</tt> file and cannot be created by the
1570 application developer, that is not the case with virtual registers. In order
1571 to create new virtual registers, use the
1572 method <tt>MachineRegisterInfo::createVirtualRegister()</tt>. This method
1573 will return a virtual register with the highest code.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1574
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1575<p>Before register allocation, the operands of an instruction are mostly virtual
1576 registers, although physical registers may also be used. In order to check if
1577 a given machine operand is a register, use the boolean
1578 function <tt>MachineOperand::isRegister()</tt>. To obtain the integer code of
1579 a register, use <tt>MachineOperand::getReg()</tt>. An instruction may define
1580 or use a register. For instance, <tt>ADD reg:1026 := reg:1025 reg:1024</tt>
1581 defines the registers 1024, and uses registers 1025 and 1026. Given a
1582 register operand, the method <tt>MachineOperand::isUse()</tt> informs if that
1583 register is being used by the instruction. The
1584 method <tt>MachineOperand::isDef()</tt> informs if that registers is being
1585 defined.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1586
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1587<p>We will call physical registers present in the LLVM bitcode before register
1588 allocation <i>pre-colored registers</i>. Pre-colored registers are used in
1589 many different situations, for instance, to pass parameters of functions
1590 calls, and to store results of particular instructions. There are two types
1591 of pre-colored registers: the ones <i>implicitly</i> defined, and
1592 those <i>explicitly</i> defined. Explicitly defined registers are normal
1593 operands, and can be accessed
1594 with <tt>MachineInstr::getOperand(int)::getReg()</tt>. In order to check
1595 which registers are implicitly defined by an instruction, use
1596 the <tt>TargetInstrInfo::get(opcode)::ImplicitDefs</tt>,
1597 where <tt>opcode</tt> is the opcode of the target instruction. One important
1598 difference between explicit and implicit physical registers is that the
1599 latter are defined statically for each instruction, whereas the former may
1600 vary depending on the program being compiled. For example, an instruction
1601 that represents a function call will always implicitly define or use the same
1602 set of physical registers. To read the registers implicitly used by an
1603 instruction,
1604 use <tt>TargetInstrInfo::get(opcode)::ImplicitUses</tt>. Pre-colored
1605 registers impose constraints on any register allocation algorithm. The
Bob Wilson04738682010-04-09 18:39:54 +0000[diff] [blame]1606 register allocator must make sure that none of them are overwritten by
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1607 the values of virtual registers while still alive.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1608
1609</div>
1610
1611<!-- _______________________________________________________________________ -->
1612
1613<div class="doc_subsubsection">
1614 <a name="regAlloc_howTo">Mapping virtual registers to physical registers</a>
1615</div>
1616
1617<div class="doc_text">
1618
1619<p>There are two ways to map virtual registers to physical registers (or to
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1620 memory slots). The first way, that we will call <i>direct mapping</i>, is
1621 based on the use of methods of the classes <tt>TargetRegisterInfo</tt>,
1622 and <tt>MachineOperand</tt>. The second way, that we will call <i>indirect
1623 mapping</i>, relies on the <tt>VirtRegMap</tt> class in order to insert loads
1624 and stores sending and getting values to and from memory.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1625
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1626<p>The direct mapping provides more flexibility to the developer of the register
1627 allocator; however, it is more error prone, and demands more implementation
1628 work. Basically, the programmer will have to specify where load and store
1629 instructions should be inserted in the target function being compiled in
1630 order to get and store values in memory. To assign a physical register to a
1631 virtual register present in a given operand,
1632 use <tt>MachineOperand::setReg(p_reg)</tt>. To insert a store instruction,
Jakob Stoklund Olesen297907f2010-08-31 22:01:07 +0000[diff] [blame]1633 use <tt>TargetInstrInfo::storeRegToStackSlot(...)</tt>, and to insert a
1634 load instruction, use <tt>TargetInstrInfo::loadRegFromStackSlot</tt>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1635
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1636<p>The indirect mapping shields the application developer from the complexities
1637 of inserting load and store instructions. In order to map a virtual register
1638 to a physical one, use <tt>VirtRegMap::assignVirt2Phys(vreg, preg)</tt>. In
1639 order to map a certain virtual register to memory,
1640 use <tt>VirtRegMap::assignVirt2StackSlot(vreg)</tt>. This method will return
1641 the stack slot where <tt>vreg</tt>'s value will be located. If it is
1642 necessary to map another virtual register to the same stack slot,
1643 use <tt>VirtRegMap::assignVirt2StackSlot(vreg, stack_location)</tt>. One
1644 important point to consider when using the indirect mapping, is that even if
1645 a virtual register is mapped to memory, it still needs to be mapped to a
1646 physical register. This physical register is the location where the virtual
1647 register is supposed to be found before being stored or after being
1648 reloaded.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1649
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1650<p>If the indirect strategy is used, after all the virtual registers have been
1651 mapped to physical registers or stack slots, it is necessary to use a spiller
1652 object to place load and store instructions in the code. Every virtual that
1653 has been mapped to a stack slot will be stored to memory after been defined
1654 and will be loaded before being used. The implementation of the spiller tries
1655 to recycle load/store instructions, avoiding unnecessary instructions. For an
1656 example of how to invoke the spiller,
1657 see <tt>RegAllocLinearScan::runOnMachineFunction</tt>
1658 in <tt>lib/CodeGen/RegAllocLinearScan.cpp</tt>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1659
1660</div>
1661
1662<!-- _______________________________________________________________________ -->
1663<div class="doc_subsubsection">
1664 <a name="regAlloc_twoAddr">Handling two address instructions</a>
1665</div>
1666
1667<div class="doc_text">
1668
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1669<p>With very rare exceptions (e.g., function calls), the LLVM machine code
1670 instructions are three address instructions. That is, each instruction is
1671 expected to define at most one register, and to use at most two registers.
1672 However, some architectures use two address instructions. In this case, the
1673 defined register is also one of the used register. For instance, an
1674 instruction such as <tt>ADD %EAX, %EBX</tt>, in X86 is actually equivalent
1675 to <tt>%EAX = %EAX + %EBX</tt>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1676
1677<p>In order to produce correct code, LLVM must convert three address
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1678 instructions that represent two address instructions into true two address
1679 instructions. LLVM provides the pass <tt>TwoAddressInstructionPass</tt> for
1680 this specific purpose. It must be run before register allocation takes
1681 place. After its execution, the resulting code may no longer be in SSA
1682 form. This happens, for instance, in situations where an instruction such
1683 as <tt>%a = ADD %b %c</tt> is converted to two instructions such as:</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1684
1685<div class="doc_code">
1686<pre>
1687%a = MOVE %b
Dan Gohman03e58572008-06-13 17:55:57 +0000[diff] [blame]1688%a = ADD %a %c
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1689</pre>
1690</div>
1691
1692<p>Notice that, internally, the second instruction is represented as
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1693 <tt>ADD %a[def/use] %c</tt>. I.e., the register operand <tt>%a</tt> is both
1694 used and defined by the instruction.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1695
1696</div>
1697
1698<!-- _______________________________________________________________________ -->
1699<div class="doc_subsubsection">
1700 <a name="regAlloc_ssaDecon">The SSA deconstruction phase</a>
1701</div>
1702
1703<div class="doc_text">
1704
1705<p>An important transformation that happens during register allocation is called
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1706 the <i>SSA Deconstruction Phase</i>. The SSA form simplifies many analyses
1707 that are performed on the control flow graph of programs. However,
1708 traditional instruction sets do not implement PHI instructions. Thus, in
1709 order to generate executable code, compilers must replace PHI instructions
1710 with other instructions that preserve their semantics.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1711
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1712<p>There are many ways in which PHI instructions can safely be removed from the
1713 target code. The most traditional PHI deconstruction algorithm replaces PHI
1714 instructions with copy instructions. That is the strategy adopted by
1715 LLVM. The SSA deconstruction algorithm is implemented
1716 in <tt>lib/CodeGen/PHIElimination.cpp</tt>. In order to invoke this pass, the
1717 identifier <tt>PHIEliminationID</tt> must be marked as required in the code
1718 of the register allocator.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1719
1720</div>
1721
1722<!-- _______________________________________________________________________ -->
1723<div class="doc_subsubsection">
1724 <a name="regAlloc_fold">Instruction folding</a>
1725</div>
1726
1727<div class="doc_text">
1728
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1729<p><i>Instruction folding</i> is an optimization performed during register
1730 allocation that removes unnecessary copy instructions. For instance, a
1731 sequence of instructions such as:</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1732
1733<div class="doc_code">
1734<pre>
1735%EBX = LOAD %mem_address
1736%EAX = COPY %EBX
1737</pre>
1738</div>
1739
Dan Gohmana7ab2bf2008-11-24 16:35:31 +0000[diff] [blame]1740<p>can be safely substituted by the single instruction:</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1741
1742<div class="doc_code">
1743<pre>
1744%EAX = LOAD %mem_address
1745</pre>
1746</div>
1747
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1748<p>Instructions can be folded with
1749 the <tt>TargetRegisterInfo::foldMemoryOperand(...)</tt> method. Care must be
1750 taken when folding instructions; a folded instruction can be quite different
1751 from the original
1752 instruction. See <tt>LiveIntervals::addIntervalsForSpills</tt>
1753 in <tt>lib/CodeGen/LiveIntervalAnalysis.cpp</tt> for an example of its
1754 use.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1755
1756</div>
1757
1758<!-- _______________________________________________________________________ -->
1759
1760<div class="doc_subsubsection">
1761 <a name="regAlloc_builtIn">Built in register allocators</a>
1762</div>
1763
1764<div class="doc_text">
1765
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1766<p>The LLVM infrastructure provides the application developer with three
1767 different register allocators:</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1768
1769<ul>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1770 <li><i>Linear Scan</i> &mdash; <i>The default allocator</i>. This is the
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1771 well-know linear scan register allocator. Whereas the
1772 <i>Simple</i> and <i>Local</i> algorithms use a direct mapping
1773 implementation technique, the <i>Linear Scan</i> implementation
1774 uses a spiller in order to place load and stores.</li>
Jakob Stoklund Olesen8a3eab92010-06-15 21:58:33 +0000[diff] [blame]1775
1776 <li><i>Fast</i> &mdash; This register allocator is the default for debug
1777 builds. It allocates registers on a basic block level, attempting to keep
1778 values in registers and reusing registers as appropriate.</li>
1779
1780 <li><i>PBQP</i> &mdash; A Partitioned Boolean Quadratic Programming (PBQP)
1781 based register allocator. This allocator works by constructing a PBQP
1782 problem representing the register allocation problem under consideration,
1783 solving this using a PBQP solver, and mapping the solution back to a
1784 register assignment.</li>
1785
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1786</ul>
1787
1788<p>The type of register allocator used in <tt>llc</tt> can be chosen with the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1789 command line option <tt>-regalloc=...</tt>:</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1790
1791<div class="doc_code">
1792<pre>
Dan Gohman0cabaa52009-08-25 15:54:01 +0000[diff] [blame]1793$ llc -regalloc=linearscan file.bc -o ln.s;
Jakob Stoklund Olesen8a3eab92010-06-15 21:58:33 +0000[diff] [blame]1794$ llc -regalloc=fast file.bc -o fa.s;
1795$ llc -regalloc=pbqp file.bc -o pbqp.s;
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1796</pre>
1797</div>
1798
1799</div>
1800
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1801<!-- ======================================================================= -->
1802<div class="doc_subsection">
1803 <a name="proepicode">Prolog/Epilog Code Insertion</a>
1804</div>
1805<div class="doc_text"><p>To Be Written</p></div>
1806<!-- ======================================================================= -->
1807<div class="doc_subsection">
1808 <a name="latemco">Late Machine Code Optimizations</a>
1809</div>
1810<div class="doc_text"><p>To Be Written</p></div>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]1811
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1812<!-- ======================================================================= -->
1813<div class="doc_subsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1814 <a name="codeemit">Code Emission</a>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1815</div>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]1816
1817<div class="doc_text">
1818
1819<p>The code emission step of code generation is responsible for lowering from
1820the code generator abstractions (like <a
1821href="#machinefunction">MachineFunction</a>, <a
1822href="#machineinstr">MachineInstr</a>, etc) down
1823to the abstractions used by the MC layer (<a href="#mcinst">MCInst</a>,
1824<a href="#mcstreamer">MCStreamer</a>, etc). This is
1825done with a combination of several different classes: the (misnamed)
1826target-independent AsmPrinter class, target-specific subclasses of AsmPrinter
1827(such as SparcAsmPrinter), and the TargetLoweringObjectFile class.</p>
1828
1829<p>Since the MC layer works at the level of abstraction of object files, it
1830doesn't have a notion of functions, global variables etc. Instead, it thinks
1831about labels, directives, and instructions. A key class used at this time is
1832the MCStreamer class. This is an abstract API that is implemented in different
1833ways (e.g. to output a .s file, output an ELF .o file, etc) that is effectively
1834an "assembler API". MCStreamer has one method per directive, such as EmitLabel,
1835EmitSymbolAttribute, SwitchSection, etc, which directly correspond to assembly
1836level directives.
1837</p>
1838
1839<p>If you are interested in implementing a code generator for a target, there
1840are three important things that you have to implement for your target:</p>
1841
1842<ol>
1843<li>First, you need a subclass of AsmPrinter for your target. This class
1844implements the general lowering process converting MachineFunction's into MC
1845label constructs. The AsmPrinter base class provides a number of useful methods
1846and routines, and also allows you to override the lowering process in some
1847important ways. You should get much of the lowering for free if you are
1848implementing an ELF, COFF, or MachO target, because the TargetLoweringObjectFile
1849class implements much of the common logic.</li>
1850
1851<li>Second, you need to implement an instruction printer for your target. The
1852instruction printer takes an <a href="#mcinst">MCInst</a> and renders it to a
1853raw_ostream as text. Most of this is automatically generated from the .td file
1854(when you specify something like "<tt>add $dst, $src1, $src2</tt>" in the
1855instructions), but you need to implement routines to print operands.</li>
1856
1857<li>Third, you need to implement code that lowers a <a
1858href="#machineinstr">MachineInstr</a> to an MCInst, usually implemented in
1859"&lt;target&gt;MCInstLower.cpp". This lowering process is often target
1860specific, and is responsible for turning jump table entries, constant pool
1861indices, global variable addresses, etc into MCLabels as appropriate. This
1862translation layer is also responsible for expanding pseudo ops used by the code
1863generator into the actual machine instructions they correspond to. The MCInsts
1864that are generated by this are fed into the instruction printer or the encoder.
1865</li>
1866
1867</ol>
1868
1869<p>Finally, at your choosing, you can also implement an subclass of
1870MCCodeEmitter which lowers MCInst's into machine code bytes and relocations.
1871This is important if you want to support direct .o file emission, or would like
1872to implement an assembler for your target.</p>
1873
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1874</div>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]1875
1876
Chris Lattner22481f22010-09-21 04:03:39 +0000[diff] [blame]1877<!-- *********************************************************************** -->
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]1878<div class="doc_section">
1879 <a name="nativeassembler">Implementing a Native Assembler</a>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1880</div>
Chris Lattner22481f22010-09-21 04:03:39 +0000[diff] [blame]1881<!-- *********************************************************************** -->
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1882
1883<div class="doc_text">
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]1884
Chris Lattner22481f22010-09-21 04:03:39 +0000[diff] [blame]1885<p>Though you're probably reading this because you want to write or maintain a
1886compiler backend, LLVM also fully supports building a native assemblers too.
1887We've tried hard to automate the generation of the assembler from the .td files
1888(in particular the instruction syntax and encodings), which means that a large
1889part of the manual and repetitive data entry can be factored and shared with the
1890compiler.</p>
1891
Chris Lattner674c1dc2010-10-30 17:36:36 +0000[diff] [blame]1892</div>
Chris Lattner22481f22010-09-21 04:03:39 +0000[diff] [blame]1893
Chris Lattner674c1dc2010-10-30 17:36:36 +0000[diff] [blame]1894<!-- ======================================================================= -->
1895<div class="doc_subsection" id="na_instparsing">Instruction Parsing</div>
1896
1897<div class="doc_text"><p>To Be Written</p></div>
1898
1899
1900<!-- ======================================================================= -->
1901<div class="doc_subsection" id="na_instaliases">
1902 Instruction Alias Processing
1903</div>
1904
1905<div class="doc_text">
1906<p>Once the instruction is parsed, it enters the MatchInstructionImpl function.
1907The MatchInstructionImpl function performs alias processing and then does
1908actual matching.</p>
1909
Chris Lattner693173f2010-10-30 19:23:13 +0000[diff] [blame]1910<p>Alias processing is the phase that canonicalizes different lexical forms of
Chris Lattner674c1dc2010-10-30 17:36:36 +0000[diff] [blame]1911the same instructions down to one representation. There are several different
1912kinds of alias that are possible to implement and they are listed below in the
1913order that they are processed (which is in order from simplest/weakest to most
1914complex/powerful). Generally you want to use the first alias mechanism that
1915meets the needs of your instruction, because it will allow a more concise
1916description.</p>
1917
Chris Lattner50e59722010-10-30 20:21:00 +0000[diff] [blame]1918</div>
1919
Chris Lattner674c1dc2010-10-30 17:36:36 +0000[diff] [blame]1920<!-- _______________________________________________________________________ -->
1921<div class="doc_subsubsection">Mnemonic Aliases</div>
1922
1923<div class="doc_text">
1924
Chris Lattner8cf8bcc2010-10-30 19:47:49 +0000[diff] [blame]1925<p>The first phase of alias processing is simple instruction mnemonic
Chris Lattner674c1dc2010-10-30 17:36:36 +0000[diff] [blame]1926remapping for classes of instructions which are allowed with two different
Chris Lattner693173f2010-10-30 19:23:13 +0000[diff] [blame]1927mnemonics. This phase is a simple and unconditionally remapping from one input
Chris Lattner674c1dc2010-10-30 17:36:36 +0000[diff] [blame]1928mnemonic to one output mnemonic. It isn't possible for this form of alias to
1929look at the operands at all, so the remapping must apply for all forms of a
1930given mnemonic. Mnemonic aliases are defined simply, for example X86 has:
1931</p>
1932
1933<div class="doc_code">
1934<pre>
1935def : MnemonicAlias&lt;"cbw", "cbtw"&gt;;
1936def : MnemonicAlias&lt;"smovq", "movsq"&gt;;
1937def : MnemonicAlias&lt;"fldcww", "fldcw"&gt;;
1938def : MnemonicAlias&lt;"fucompi", "fucomip"&gt;;
1939def : MnemonicAlias&lt;"ud2a", "ud2"&gt;;
1940</pre>
1941</div>
1942
1943<p>... and many others. With a MnemonicAlias definition, the mnemonic is
Chris Lattner693173f2010-10-30 19:23:13 +0000[diff] [blame]1944remapped simply and directly. Though MnemonicAlias's can't look at any aspect
1945of the instruction (such as the operands) they can depend on global modes (the
1946same ones supported by the matcher), through a Requires clause:</p>
1947
1948<div class="doc_code">
1949<pre>
1950def : MnemonicAlias&lt;"pushf", "pushfq"&gt;, Requires&lt;[In64BitMode]&gt;;
1951def : MnemonicAlias&lt;"pushf", "pushfl"&gt;, Requires&lt;[In32BitMode]&gt;;
1952</pre>
1953</div>
1954
1955<p>In this example, the mnemonic gets mapped into different a new one depending
1956on the current instruction set.</p>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]1957
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1958</div>
1959
Chris Lattnerc7a03fb2010-11-06 08:30:26 +0000[diff] [blame]1960<!-- _______________________________________________________________________ -->
1961<div class="doc_subsubsection">Instruction Aliases</div>
1962
1963<div class="doc_text">
1964
1965<p>The most general phase of alias processing occurs while matching is
1966happening: it provides new forms for the matcher to match along with a specific
1967instruction to generate. An instruction alias has two parts: the string to
1968match and the instruction to generate. For example:
1969</p>
1970
1971<div class="doc_code">
1972<pre>
1973def : InstAlias&lt;"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8 :$src)&gt;;
1974def : InstAlias&lt;"movsx $src, $dst", (MOVSX16rm8W GR16:$dst, i8mem:$src)&gt;;
1975def : InstAlias&lt;"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8 :$src)&gt;;
1976def : InstAlias&lt;"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16 :$src)&gt;;
1977def : InstAlias&lt;"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8 :$src)&gt;;
1978def : InstAlias&lt;"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16 :$src)&gt;;
1979def : InstAlias&lt;"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32 :$src)&gt;;
1980</pre>
1981</div>
1982
1983<p>This shows a powerful example of the instruction aliases, matching the
1984same mnemonic in multiple different ways depending on what operands are present
1985in the assembly. The result of instruction aliases can include operands in a
1986different order than the destination instruction, and can use an input
1987multiple times, for example:</p>
1988
1989<div class="doc_code">
1990<pre>
1991def : InstAlias&lt;"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)&gt;;
1992def : InstAlias&lt;"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)&gt;;
1993def : InstAlias&lt;"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)&gt;;
1994def : InstAlias&lt;"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)&gt;;
1995</pre>
1996</div>
1997
1998<p>This example also shows that tied operands are only listed once. In the X86
1999backend, XOR8rr has two input GR8's and one output GR8 (where an input is tied
2000to the output). InstAliases take a flattened operand list without duplicates
Chris Lattner90fd7972010-11-06 19:57:21 +0000[diff] [blame]2001for tied operands. The result of an instruction alias can also use immediates
2002and fixed physical registers which are added as simple immediate operands in the
2003result, for example:</p>
Chris Lattner98c870f2010-11-06 19:25:43 +0000[diff] [blame]2004
2005<div class="doc_code">
2006<pre>
Chris Lattner90fd7972010-11-06 19:57:21 +0000[diff] [blame]2007// Fixed Immediate operand.
Chris Lattner98c870f2010-11-06 19:25:43 +0000[diff] [blame]2008def : InstAlias&lt;"aad", (AAD8i8 10)&gt;;
Chris Lattner90fd7972010-11-06 19:57:21 +0000[diff] [blame]2009
2010// Fixed register operand.
2011def : InstAlias&lt;"fcomi", (COM_FIr ST1)&gt;;
2012
2013// Simple alias.
2014def : InstAlias&lt;"fcomi $reg", (COM_FIr RST:$reg)&gt;;
Chris Lattner98c870f2010-11-06 19:25:43 +0000[diff] [blame]2015</pre>
2016</div>
2017
Chris Lattnerc7a03fb2010-11-06 08:30:26 +0000[diff] [blame]2018
2019<p>Instruction aliases can also have a Requires clause to make them
2020subtarget specific.</p>
2021
2022</div>
2023
2024
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]2025
Chris Lattner22481f22010-09-21 04:03:39 +0000[diff] [blame]2026<!-- ======================================================================= -->
Chris Lattner674c1dc2010-10-30 17:36:36 +0000[diff] [blame]2027<div class="doc_subsection" id="na_matching">Instruction Matching</div>
2028
Chris Lattner22481f22010-09-21 04:03:39 +0000[diff] [blame]2029<div class="doc_text"><p>To Be Written</p></div>
2030
2031
2032
2033
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]2034<!-- *********************************************************************** -->
2035<div class="doc_section">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]2036 <a name="targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2037</div>
2038<!-- *********************************************************************** -->
2039
2040<div class="doc_text">
2041
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2042<p>This section of the document explains features or design decisions that are
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2043 specific to the code generator for a particular target. First we start
2044 with a table that summarizes what features are supported by each target.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2045
2046</div>
2047
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]2048<!-- ======================================================================= -->
2049<div class="doc_subsection">
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2050 <a name="targetfeatures">Target Feature Matrix</a>
2051</div>
2052
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2053<div class="doc_text">
2054
2055<p>Note that this table does not include the C backend or Cpp backends, since
2056they do not use the target independent code generator infrastructure. It also
2057doesn't list features that are not supported fully by any target yet. It
2058considers a feature to be supported if at least one subtarget supports it. A
2059feature being supported means that it is useful and works for most cases, it
2060does not indicate that there are zero known bugs in the implementation. Here
2061is the key:</p>
2062
2063
2064<table border="1" cellspacing="0">
2065 <tr>
2066 <th>Unknown</th>
2067 <th>No support</th>
2068 <th>Partial Support</th>
2069 <th>Complete Support</th>
2070 </tr>
2071 <tr>
2072 <td class="unknown"></td>
2073 <td class="no"></td>
2074 <td class="partial"></td>
2075 <td class="yes"></td>
2076 </tr>
2077</table>
2078
2079<p>Here is the table:</p>
2080
2081<table width="689" border="1" cellspacing="0">
2082<tr><td></td>
Benjamin Kramer943beeb2010-10-30 21:07:28 +0000[diff] [blame]2083<td colspan="13" align="center" style="background-color:#ffc">Target</td>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2084</tr>
2085 <tr>
2086 <th>Feature</th>
2087 <th>ARM</th>
2088 <th>Alpha</th>
2089 <th>Blackfin</th>
2090 <th>CellSPU</th>
2091 <th>MBlaze</th>
2092 <th>MSP430</th>
2093 <th>Mips</th>
2094 <th>PTX</th>
2095 <th>PowerPC</th>
2096 <th>Sparc</th>
2097 <th>SystemZ</th>
2098 <th>X86</th>
2099 <th>XCore</th>
2100 </tr>
2101
2102<tr>
2103 <td><a href="#feat_reliable">is generally reliable</a></td>
2104 <td class="yes"></td> <!-- ARM -->
2105 <td class="unknown"></td> <!-- Alpha -->
Jakob Stoklund Olesen4e136122010-10-24 20:04:05 +0000[diff] [blame]2106 <td class="no"></td> <!-- Blackfin -->
Kalle Raiskila94cc4fe2010-10-25 08:57:30 +0000[diff] [blame]2107 <td class="no"></td> <!-- CellSPU -->
Wesley Peckc6a45242010-10-24 18:50:12 +0000[diff] [blame]2108 <td class="no"></td> <!-- MBlaze -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2109 <td class="unknown"></td> <!-- MSP430 -->
2110 <td class="unknown"></td> <!-- Mips -->
2111 <td class="no"></td> <!-- PTX -->
2112 <td class="yes"></td> <!-- PowerPC -->
2113 <td class="yes"></td> <!-- Sparc -->
2114 <td class="unknown"></td> <!-- SystemZ -->
2115 <td class="yes"></td> <!-- X86 -->
2116 <td class="unknown"></td> <!-- XCore -->
2117</tr>
2118
2119<tr>
2120 <td><a href="#feat_asmparser">assembly parser</a></td>
2121 <td class="no"></td> <!-- ARM -->
2122 <td class="no"></td> <!-- Alpha -->
2123 <td class="no"></td> <!-- Blackfin -->
2124 <td class="no"></td> <!-- CellSPU -->
2125 <td class="no"></td> <!-- MBlaze -->
2126 <td class="no"></td> <!-- MSP430 -->
2127 <td class="no"></td> <!-- Mips -->
2128 <td class="no"></td> <!-- PTX -->
2129 <td class="no"></td> <!-- PowerPC -->
2130 <td class="no"></td> <!-- Sparc -->
2131 <td class="no"></td> <!-- SystemZ -->
2132 <td class="yes"></td> <!-- X86 -->
2133 <td class="no"></td> <!-- XCore -->
2134</tr>
2135
2136<tr>
2137 <td><a href="#feat_disassembler">disassembler</a></td>
2138 <td class="yes"></td> <!-- ARM -->
2139 <td class="no"></td> <!-- Alpha -->
2140 <td class="no"></td> <!-- Blackfin -->
2141 <td class="no"></td> <!-- CellSPU -->
2142 <td class="no"></td> <!-- MBlaze -->
2143 <td class="no"></td> <!-- MSP430 -->
2144 <td class="no"></td> <!-- Mips -->
2145 <td class="no"></td> <!-- PTX -->
2146 <td class="no"></td> <!-- PowerPC -->
2147 <td class="no"></td> <!-- Sparc -->
2148 <td class="no"></td> <!-- SystemZ -->
2149 <td class="yes"></td> <!-- X86 -->
2150 <td class="no"></td> <!-- XCore -->
2151</tr>
2152
2153<tr>
2154 <td><a href="#feat_inlineasm">inline asm</a></td>
2155 <td class="yes"></td> <!-- ARM -->
2156 <td class="unknown"></td> <!-- Alpha -->
Jakob Stoklund Olesen4e136122010-10-24 20:04:05 +0000[diff] [blame]2157 <td class="yes"></td> <!-- Blackfin -->
Kalle Raiskila94cc4fe2010-10-25 08:57:30 +0000[diff] [blame]2158 <td class="no"></td> <!-- CellSPU -->
Wesley Peckc6a45242010-10-24 18:50:12 +0000[diff] [blame]2159 <td class="no"></td> <!-- MBlaze -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2160 <td class="unknown"></td> <!-- MSP430 -->
2161 <td class="unknown"></td> <!-- Mips -->
2162 <td class="unknown"></td> <!-- PTX -->
2163 <td class="yes"></td> <!-- PowerPC -->
2164 <td class="unknown"></td> <!-- Sparc -->
2165 <td class="unknown"></td> <!-- SystemZ -->
2166 <td class="yes"><a href="#feat_inlineasm_x86">*</a></td> <!-- X86 -->
2167 <td class="unknown"></td> <!-- XCore -->
2168</tr>
2169
2170<tr>
2171 <td><a href="#feat_jit">jit</a></td>
2172 <td class="partial"><a href="#feat_jit_arm">*</a></td> <!-- ARM -->
Chris Lattnerac3031a2010-11-14 18:25:50 +0000[diff] [blame]2173 <td class="no"></td> <!-- Alpha -->
Jakob Stoklund Olesen4e136122010-10-24 20:04:05 +0000[diff] [blame]2174 <td class="no"></td> <!-- Blackfin -->
Kalle Raiskila94cc4fe2010-10-25 08:57:30 +0000[diff] [blame]2175 <td class="no"></td> <!-- CellSPU -->
Wesley Peckc6a45242010-10-24 18:50:12 +0000[diff] [blame]2176 <td class="no"></td> <!-- MBlaze -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2177 <td class="unknown"></td> <!-- MSP430 -->
2178 <td class="unknown"></td> <!-- Mips -->
2179 <td class="unknown"></td> <!-- PTX -->
2180 <td class="yes"></td> <!-- PowerPC -->
2181 <td class="unknown"></td> <!-- Sparc -->
2182 <td class="unknown"></td> <!-- SystemZ -->
2183 <td class="yes"></td> <!-- X86 -->
2184 <td class="unknown"></td> <!-- XCore -->
2185</tr>
2186
2187<tr>
2188 <td><a href="#feat_objectwrite">.o&nbsp;file writing</a></td>
2189 <td class="no"></td> <!-- ARM -->
2190 <td class="no"></td> <!-- Alpha -->
2191 <td class="no"></td> <!-- Blackfin -->
2192 <td class="no"></td> <!-- CellSPU -->
2193 <td class="no"></td> <!-- MBlaze -->
2194 <td class="no"></td> <!-- MSP430 -->
2195 <td class="no"></td> <!-- Mips -->
2196 <td class="no"></td> <!-- PTX -->
2197 <td class="no"></td> <!-- PowerPC -->
2198 <td class="no"></td> <!-- Sparc -->
2199 <td class="no"></td> <!-- SystemZ -->
2200 <td class="yes"></td> <!-- X86 -->
2201 <td class="no"></td> <!-- XCore -->
2202</tr>
2203
2204<tr>
2205 <td><a href="#feat_tailcall">tail calls</a></td>
2206 <td class="yes"></td> <!-- ARM -->
2207 <td class="unknown"></td> <!-- Alpha -->
Jakob Stoklund Olesen4e136122010-10-24 20:04:05 +0000[diff] [blame]2208 <td class="no"></td> <!-- Blackfin -->
Kalle Raiskila94cc4fe2010-10-25 08:57:30 +0000[diff] [blame]2209 <td class="no"></td> <!-- CellSPU -->
Wesley Peckc6a45242010-10-24 18:50:12 +0000[diff] [blame]2210 <td class="no"></td> <!-- MBlaze -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2211 <td class="unknown"></td> <!-- MSP430 -->
2212 <td class="unknown"></td> <!-- Mips -->
2213 <td class="unknown"></td> <!-- PTX -->
2214 <td class="yes"></td> <!-- PowerPC -->
2215 <td class="unknown"></td> <!-- Sparc -->
2216 <td class="unknown"></td> <!-- SystemZ -->
2217 <td class="yes"></td> <!-- X86 -->
2218 <td class="unknown"></td> <!-- XCore -->
2219</tr>
2220
2221
2222</table>
2223
2224</div>
2225
2226<!-- _______________________________________________________________________ -->
2227<div class="doc_subsubsection" id="feat_reliable">Is Generally Reliable</div>
2228
2229<div class="doc_text">
2230<p>This box indicates whether the target is considered to be production quality.
2231This indicates that the target has been used as a static compiler to
2232compile large amounts of code by a variety of different people and is in
2233continuous use.</p>
2234</div>
2235
2236<!-- _______________________________________________________________________ -->
2237<div class="doc_subsubsection" id="feat_asmparser">Assembly Parser</div>
2238
2239<div class="doc_text">
2240<p>This box indicates whether the target supports parsing target specific .s
2241files by implementing the MCAsmParser interface. This is required for llvm-mc
2242to be able to act as a native assembler and is required for inline assembly
2243support in the native .o file writer.</p>
2244
2245</div>
2246
2247
2248<!-- _______________________________________________________________________ -->
2249<div class="doc_subsubsection" id="feat_disassembler">Disassembler</div>
2250
2251<div class="doc_text">
2252<p>This box indicates whether the target supports the MCDisassembler API for
2253disassembling machine opcode bytes into MCInst's.</p>
2254
2255</div>
2256
2257<!-- _______________________________________________________________________ -->
2258<div class="doc_subsubsection" id="feat_inlineasm">Inline Asm</div>
2259
2260<div class="doc_text">
2261<p>This box indicates whether the target supports most popular inline assembly
2262constraints and modifiers.</p>
2263
2264<p id="feat_inlineasm_x86">X86 lacks reliable support for inline assembly
2265constraints relating to the X86 floating point stack.</p>
2266
2267</div>
2268
2269<!-- _______________________________________________________________________ -->
2270<div class="doc_subsubsection" id="feat_jit">JIT Support</div>
2271
2272<div class="doc_text">
2273<p>This box indicates whether the target supports the JIT compiler through
2274the ExecutionEngine interface.</p>
2275
Chris Lattner6fb99552010-10-24 16:24:22 +0000[diff] [blame]2276<p id="feat_jit_arm">The ARM backend has basic support for integer code
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2277in ARM codegen mode, but lacks NEON and full Thumb support.</p>
2278
2279</div>
2280
2281<!-- _______________________________________________________________________ -->
2282<div class="doc_subsubsection" id="feat_objectwrite">.o File Writing</div>
2283
2284<div class="doc_text">
2285
2286<p>This box indicates whether the target supports writing .o files (e.g. MachO,
2287ELF, and/or COFF) files directly from the target. Note that the target also
2288must include an assembly parser and general inline assembly support for full
2289inline assembly support in the .o writer.</p>
2290
Chris Lattner219ddf52010-10-28 02:22:02 +0000[diff] [blame]2291<p>Targets that don't support this feature can obviously still write out .o
2292files, they just rely on having an external assembler to translate from a .s
2293file to a .o file (as is the case for many C compilers).</p>
2294
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2295</div>
2296
2297<!-- _______________________________________________________________________ -->
2298<div class="doc_subsubsection" id="feat_tailcall">Tail Calls</div>
2299
2300<div class="doc_text">
2301
2302<p>This box indicates whether the target supports guaranteed tail calls. These
2303are calls marked "<a href="LangRef.html#i_call">tail</a>" and use the fastcc
2304calling convention. Please see the <a href="#tailcallopt">tail call section
2305more more details</a>.</p>
2306
2307</div>
2308
2309
2310
2311
2312<!-- ======================================================================= -->
2313<div class="doc_subsection">
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]2314 <a name="tailcallopt">Tail call optimization</a>
2315</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2316
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]2317<div class="doc_text">
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]2318
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2319<p>Tail call optimization, callee reusing the stack of the caller, is currently
2320 supported on x86/x86-64 and PowerPC. It is performed if:</p>
2321
2322<ul>
Chris Lattner29689432010-03-11 00:22:57 +0000[diff] [blame]2323 <li>Caller and callee have the calling convention <tt>fastcc</tt> or
2324 <tt>cc 10</tt> (GHC call convention).</li>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2325
2326 <li>The call is a tail call - in tail position (ret immediately follows call
2327 and ret uses value of call or is void).</li>
2328
2329 <li>Option <tt>-tailcallopt</tt> is enabled.</li>
2330
2331 <li>Platform specific constraints are met.</li>
2332</ul>
2333
2334<p>x86/x86-64 constraints:</p>
2335
2336<ul>
2337 <li>No variable argument lists are used.</li>
2338
2339 <li>On x86-64 when generating GOT/PIC code only module-local calls (visibility
2340 = hidden or protected) are supported.</li>
2341</ul>
2342
2343<p>PowerPC constraints:</p>
2344
2345<ul>
2346 <li>No variable argument lists are used.</li>
2347
2348 <li>No byval parameters are used.</li>
2349
2350 <li>On ppc32/64 GOT/PIC only module-local calls (visibility = hidden or protected) are supported.</li>
2351</ul>
2352
2353<p>Example:</p>
2354
2355<p>Call as <tt>llc -tailcallopt test.ll</tt>.</p>
2356
2357<div class="doc_code">
2358<pre>
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]2359declare fastcc i32 @tailcallee(i32 inreg %a1, i32 inreg %a2, i32 %a3, i32 %a4)
2360
2361define fastcc i32 @tailcaller(i32 %in1, i32 %in2) {
2362 %l1 = add i32 %in1, %in2
2363 %tmp = tail call fastcc i32 @tailcallee(i32 %in1 inreg, i32 %in2 inreg, i32 %in1, i32 %l1)
2364 ret i32 %tmp
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2365}
2366</pre>
2367</div>
2368
2369<p>Implications of <tt>-tailcallopt</tt>:</p>
2370
2371<p>To support tail call optimization in situations where the callee has more
2372 arguments than the caller a 'callee pops arguments' convention is used. This
2373 currently causes each <tt>fastcc</tt> call that is not tail call optimized
2374 (because one or more of above constraints are not met) to be followed by a
2375 readjustment of the stack. So performance might be worse in such cases.</p>
2376
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]2377</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2378<!-- ======================================================================= -->
2379<div class="doc_subsection">
Evan Chengdc444e92010-03-08 21:05:02 +0000[diff] [blame]2380 <a name="sibcallopt">Sibling call optimization</a>
2381</div>
2382
2383<div class="doc_text">
2384
2385<p>Sibling call optimization is a restricted form of tail call optimization.
2386 Unlike tail call optimization described in the previous section, it can be
2387 performed automatically on any tail calls when <tt>-tailcallopt</tt> option
2388 is not specified.</p>
2389
2390<p>Sibling call optimization is currently performed on x86/x86-64 when the
2391 following constraints are met:</p>
2392
2393<ul>
2394 <li>Caller and callee have the same calling convention. It can be either
2395 <tt>c</tt> or <tt>fastcc</tt>.
2396
2397 <li>The call is a tail call - in tail position (ret immediately follows call
2398 and ret uses value of call or is void).</li>
2399
2400 <li>Caller and callee have matching return type or the callee result is not
2401 used.
2402
2403 <li>If any of the callee arguments are being passed in stack, they must be
2404 available in caller's own incoming argument stack and the frame offsets
2405 must be the same.
2406</ul>
2407
2408<p>Example:</p>
2409<div class="doc_code">
2410<pre>
2411declare i32 @bar(i32, i32)
2412
2413define i32 @foo(i32 %a, i32 %b, i32 %c) {
2414entry:
2415 %0 = tail call i32 @bar(i32 %a, i32 %b)
2416 ret i32 %0
2417}
2418</pre>
2419</div>
2420
2421</div>
2422<!-- ======================================================================= -->
2423<div class="doc_subsection">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2424 <a name="x86">The X86 backend</a>
2425</div>
2426
2427<div class="doc_text">
2428
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]2429<p>The X86 code generator lives in the <tt>lib/Target/X86</tt> directory. This
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2430 code generator is capable of targeting a variety of x86-32 and x86-64
2431 processors, and includes support for ISA extensions such as MMX and SSE.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2432
2433</div>
2434
2435<!-- _______________________________________________________________________ -->
2436<div class="doc_subsubsection">
Nate Begeman34509842009-01-26 02:54:45 +0000[diff] [blame]2437 <a name="x86_tt">X86 Target Triples supported</a>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]2438</div>
2439
2440<div class="doc_text">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]2441
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2442<p>The following are the known target triples that are supported by the X86
2443 backend. This is not an exhaustive list, and it would be useful to add those
2444 that people test.</p>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]2445
2446<ul>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2447 <li><b>i686-pc-linux-gnu</b> &mdash; Linux</li>
2448
2449 <li><b>i386-unknown-freebsd5.3</b> &mdash; FreeBSD 5.3</li>
2450
2451 <li><b>i686-pc-cygwin</b> &mdash; Cygwin on Win32</li>
2452
2453 <li><b>i686-pc-mingw32</b> &mdash; MingW on Win32</li>
2454
2455 <li><b>i386-pc-mingw32msvc</b> &mdash; MingW crosscompiler on Linux</li>
2456
2457 <li><b>i686-apple-darwin*</b> &mdash; Apple Darwin on X86</li>
Torok Edwinc457b652009-06-15 12:17:44 +0000[diff] [blame]2458
2459 <li><b>x86_64-unknown-linux-gnu</b> &mdash; Linux</li>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]2460</ul>
2461
2462</div>
2463
2464<!-- _______________________________________________________________________ -->
2465<div class="doc_subsubsection">
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]2466 <a name="x86_cc">X86 Calling Conventions supported</a>
2467</div>
2468
2469
2470<div class="doc_text">
2471
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]2472<p>The following target-specific calling conventions are known to backend:</p>
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]2473
2474<ul>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2475 <li><b>x86_StdCall</b> &mdash; stdcall calling convention seen on Microsoft
2476 Windows platform (CC ID = 64).</li>
2477
2478 <li><b>x86_FastCall</b> &mdash; fastcall calling convention seen on Microsoft
2479 Windows platform (CC ID = 65).</li>
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]2480</ul>
2481
2482</div>
2483
2484<!-- _______________________________________________________________________ -->
2485<div class="doc_subsubsection">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2486 <a name="x86_memory">Representing X86 addressing modes in MachineInstrs</a>
2487</div>
2488
2489<div class="doc_text">
2490
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]2491<p>The x86 has a very flexible way of accessing memory. It is capable of
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2492 forming memory addresses of the following expression directly in integer
2493 instructions (which use ModR/M addressing):</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2494
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]2495<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2496<pre>
Chris Lattnerb91227d2009-10-10 21:30:55 +0000[diff] [blame]2497SegmentReg: Base + [1,2,4,8] * IndexReg + Disp32
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2498</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]2499</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2500
Chris Lattnerb91227d2009-10-10 21:30:55 +0000[diff] [blame]2501<p>In order to represent this, LLVM tracks no less than 5 operands for each
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2502 memory operand of this form. This means that the "load" form of
2503 '<tt>mov</tt>' has the following <tt>MachineOperand</tt>s in this order:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2504
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2505<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2506<pre>
Chris Lattnerb91227d2009-10-10 21:30:55 +0000[diff] [blame]2507Index: 0 | 1 2 3 4 5
2508Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement Segment
2509OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm PhysReg
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2510</pre>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2511</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2512
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2513<p>Stores, and all other instructions, treat the four memory operands in the
Chris Lattnerb91227d2009-10-10 21:30:55 +0000[diff] [blame]2514 same way and in the same order. If the segment register is unspecified
2515 (regno = 0), then no segment override is generated. "Lea" operations do not
2516 have a segment register specified, so they only have 4 operands for their
2517 memory reference.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2518
2519</div>
2520
2521<!-- _______________________________________________________________________ -->
2522<div class="doc_subsubsection">
Nate Begeman34509842009-01-26 02:54:45 +0000[diff] [blame]2523 <a name="x86_memory">X86 address spaces supported</a>
2524</div>
2525
2526<div class="doc_text">
2527
Dan Gohmand26795a2009-05-05 20:48:47 +0000[diff] [blame]2528<p>x86 has an experimental feature which provides
2529 the ability to perform loads and stores to different address spaces
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2530 via the x86 segment registers. A segment override prefix byte on an
2531 instruction causes the instruction's memory access to go to the specified
2532 segment. LLVM address space 0 is the default address space, which includes
2533 the stack, and any unqualified memory accesses in a program. Address spaces
2534 1-255 are currently reserved for user-defined code. The GS-segment is
Chris Lattner1777d0c2009-05-05 18:52:19 +0000[diff] [blame]2535 represented by address space 256, while the FS-segment is represented by
2536 address space 257. Other x86 segments have yet to be allocated address space
2537 numbers.</p>
Nate Begeman34509842009-01-26 02:54:45 +0000[diff] [blame]2538
Dan Gohmand26795a2009-05-05 20:48:47 +0000[diff] [blame]2539<p>While these address spaces may seem similar to TLS via the
2540 <tt>thread_local</tt> keyword, and often use the same underlying hardware,
2541 there are some fundamental differences.</p>
2542
2543<p>The <tt>thread_local</tt> keyword applies to global variables and
2544 specifies that they are to be allocated in thread-local memory. There are
2545 no type qualifiers involved, and these variables can be pointed to with
2546 normal pointers and accessed with normal loads and stores.
2547 The <tt>thread_local</tt> keyword is target-independent at the LLVM IR
2548 level (though LLVM doesn't yet have implementations of it for some
2549 configurations).<p>
2550
2551<p>Special address spaces, in contrast, apply to static types. Every
2552 load and store has a particular address space in its address operand type,
2553 and this is what determines which address space is accessed.
2554 LLVM ignores these special address space qualifiers on global variables,
2555 and does not provide a way to directly allocate storage in them.
2556 At the LLVM IR level, the behavior of these special address spaces depends
2557 in part on the underlying OS or runtime environment, and they are specific
2558 to x86 (and LLVM doesn't yet handle them correctly in some cases).</p>
2559
2560<p>Some operating systems and runtime environments use (or may in the future
2561 use) the FS/GS-segment registers for various low-level purposes, so care
2562 should be taken when considering them.</p>
Nate Begeman34509842009-01-26 02:54:45 +0000[diff] [blame]2563
2564</div>
2565
2566<!-- _______________________________________________________________________ -->
2567<div class="doc_subsubsection">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2568 <a name="x86_names">Instruction naming</a>
2569</div>
2570
2571<div class="doc_text">
2572
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]2573<p>An instruction name consists of the base name, a default operand size, and a
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2574 a character per operand with an optional special size. For example:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2575
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2576<div class="doc_code">
2577<pre>
2578ADD8rr -&gt; add, 8-bit register, 8-bit register
2579IMUL16rmi -&gt; imul, 16-bit register, 16-bit memory, 16-bit immediate
2580IMUL16rmi8 -&gt; imul, 16-bit register, 16-bit memory, 8-bit immediate
2581MOVSX32rm16 -&gt; movsx, 32-bit register, 16-bit memory
2582</pre>
2583</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2584
2585</div>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]2586
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2587<!-- ======================================================================= -->
2588<div class="doc_subsection">
2589 <a name="ppc">The PowerPC backend</a>
2590</div>
2591
2592<div class="doc_text">
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2593
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2594<p>The PowerPC code generator lives in the lib/Target/PowerPC directory. The
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2595 code generation is retargetable to several variations or <i>subtargets</i> of
2596 the PowerPC ISA; including ppc32, ppc64 and altivec.</p>
2597
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2598</div>
2599
2600<!-- _______________________________________________________________________ -->
2601<div class="doc_subsubsection">
2602 <a name="ppc_abi">LLVM PowerPC ABI</a>
2603</div>
2604
2605<div class="doc_text">
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2606
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2607<p>LLVM follows the AIX PowerPC ABI, with two deviations. LLVM uses a PC
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2608 relative (PIC) or static addressing for accessing global values, so no TOC
2609 (r2) is used. Second, r31 is used as a frame pointer to allow dynamic growth
2610 of a stack frame. LLVM takes advantage of having no TOC to provide space to
2611 save the frame pointer in the PowerPC linkage area of the caller frame.
2612 Other details of PowerPC ABI can be found at <a href=
2613 "http://developer.apple.com/documentation/DeveloperTools/Conceptual/LowLevelABI/Articles/32bitPowerPC.html"
2614 >PowerPC ABI.</a> Note: This link describes the 32 bit ABI. The 64 bit ABI
2615 is similar except space for GPRs are 8 bytes wide (not 4) and r13 is reserved
2616 for system use.</p>
2617
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2618</div>
2619
2620<!-- _______________________________________________________________________ -->
2621<div class="doc_subsubsection">
2622 <a name="ppc_frame">Frame Layout</a>
2623</div>
2624
2625<div class="doc_text">
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2626
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2627<p>The size of a PowerPC frame is usually fixed for the duration of a
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2628 function's invocation. Since the frame is fixed size, all references
2629 into the frame can be accessed via fixed offsets from the stack pointer. The
2630 exception to this is when dynamic alloca or variable sized arrays are
2631 present, then a base pointer (r31) is used as a proxy for the stack pointer
2632 and stack pointer is free to grow or shrink. A base pointer is also used if
2633 llvm-gcc is not passed the -fomit-frame-pointer flag. The stack pointer is
2634 always aligned to 16 bytes, so that space allocated for altivec vectors will
2635 be properly aligned.</p>
2636
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]2637<p>An invocation frame is laid out as follows (low memory at top);</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2638
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2639<table class="layout">
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2640 <tr>
2641 <td>Linkage<br><br></td>
2642 </tr>
2643 <tr>
2644 <td>Parameter area<br><br></td>
2645 </tr>
2646 <tr>
2647 <td>Dynamic area<br><br></td>
2648 </tr>
2649 <tr>
2650 <td>Locals area<br><br></td>
2651 </tr>
2652 <tr>
2653 <td>Saved registers area<br><br></td>
2654 </tr>
2655 <tr style="border-style: none hidden none hidden;">
2656 <td><br></td>
2657 </tr>
2658 <tr>
2659 <td>Previous Frame<br><br></td>
2660 </tr>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2661</table>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2662
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2663<p>The <i>linkage</i> area is used by a callee to save special registers prior
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2664 to allocating its own frame. Only three entries are relevant to LLVM. The
2665 first entry is the previous stack pointer (sp), aka link. This allows
2666 probing tools like gdb or exception handlers to quickly scan the frames in
2667 the stack. A function epilog can also use the link to pop the frame from the
2668 stack. The third entry in the linkage area is used to save the return
2669 address from the lr register. Finally, as mentioned above, the last entry is
2670 used to save the previous frame pointer (r31.) The entries in the linkage
2671 area are the size of a GPR, thus the linkage area is 24 bytes long in 32 bit
2672 mode and 48 bytes in 64 bit mode.</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2673
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2674<p>32 bit linkage area</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2675
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2676<table class="layout">
2677 <tr>
2678 <td>0</td>
2679 <td>Saved SP (r1)</td>
2680 </tr>
2681 <tr>
2682 <td>4</td>
2683 <td>Saved CR</td>
2684 </tr>
2685 <tr>
2686 <td>8</td>
2687 <td>Saved LR</td>
2688 </tr>
2689 <tr>
2690 <td>12</td>
2691 <td>Reserved</td>
2692 </tr>
2693 <tr>
2694 <td>16</td>
2695 <td>Reserved</td>
2696 </tr>
2697 <tr>
2698 <td>20</td>
2699 <td>Saved FP (r31)</td>
2700 </tr>
2701</table>
2702
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2703<p>64 bit linkage area</p>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2704
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2705<table class="layout">
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2706 <tr>
2707 <td>0</td>
2708 <td>Saved SP (r1)</td>
2709 </tr>
2710 <tr>
2711 <td>8</td>
2712 <td>Saved CR</td>
2713 </tr>
2714 <tr>
2715 <td>16</td>
2716 <td>Saved LR</td>
2717 </tr>
2718 <tr>
2719 <td>24</td>
2720 <td>Reserved</td>
2721 </tr>
2722 <tr>
2723 <td>32</td>
2724 <td>Reserved</td>
2725 </tr>
2726 <tr>
2727 <td>40</td>
2728 <td>Saved FP (r31)</td>
2729 </tr>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2730</table>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2731
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2732<p>The <i>parameter area</i> is used to store arguments being passed to a callee
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2733 function. Following the PowerPC ABI, the first few arguments are actually
2734 passed in registers, with the space in the parameter area unused. However,
2735 if there are not enough registers or the callee is a thunk or vararg
2736 function, these register arguments can be spilled into the parameter area.
2737 Thus, the parameter area must be large enough to store all the parameters for
2738 the largest call sequence made by the caller. The size must also be
2739 minimally large enough to spill registers r3-r10. This allows callees blind
2740 to the call signature, such as thunks and vararg functions, enough space to
2741 cache the argument registers. Therefore, the parameter area is minimally 32
2742 bytes (64 bytes in 64 bit mode.) Also note that since the parameter area is
2743 a fixed offset from the top of the frame, that a callee can access its spilt
2744 arguments using fixed offsets from the stack pointer (or base pointer.)</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2745
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2746<p>Combining the information about the linkage, parameter areas and alignment. A
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2747 stack frame is minimally 64 bytes in 32 bit mode and 128 bytes in 64 bit
2748 mode.</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2749
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2750<p>The <i>dynamic area</i> starts out as size zero. If a function uses dynamic
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2751 alloca then space is added to the stack, the linkage and parameter areas are
2752 shifted to top of stack, and the new space is available immediately below the
2753 linkage and parameter areas. The cost of shifting the linkage and parameter
2754 areas is minor since only the link value needs to be copied. The link value
2755 can be easily fetched by adding the original frame size to the base pointer.
2756 Note that allocations in the dynamic space need to observe 16 byte
2757 alignment.</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2758
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2759<p>The <i>locals area</i> is where the llvm compiler reserves space for local
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2760 variables.</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2761
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2762<p>The <i>saved registers area</i> is where the llvm compiler spills callee
2763 saved registers on entry to the callee.</p>
2764
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2765</div>
2766
2767<!-- _______________________________________________________________________ -->
2768<div class="doc_subsubsection">
2769 <a name="ppc_prolog">Prolog/Epilog</a>
2770</div>
2771
2772<div class="doc_text">
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2773
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2774<p>The llvm prolog and epilog are the same as described in the PowerPC ABI, with
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2775 the following exceptions. Callee saved registers are spilled after the frame
2776 is created. This allows the llvm epilog/prolog support to be common with
2777 other targets. The base pointer callee saved register r31 is saved in the
2778 TOC slot of linkage area. This simplifies allocation of space for the base
2779 pointer and makes it convenient to locate programatically and during
2780 debugging.</p>
2781
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2782</div>
2783
2784<!-- _______________________________________________________________________ -->
2785<div class="doc_subsubsection">
2786 <a name="ppc_dynamic">Dynamic Allocation</a>
2787</div>
2788
2789<div class="doc_text">
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2790
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]2791<p><i>TODO - More to come.</i></p>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2792
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]2793</div>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2794
2795
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]2796<!-- *********************************************************************** -->
2797<hr>
2798<address>
2799 <a href="http://jigsaw.w3.org/css-validator/check/referer"><img
Misha Brukman44408702008-12-11 17:34:48 +0000[diff] [blame]2800 src="http://jigsaw.w3.org/css-validator/images/vcss-blue" alt="Valid CSS"></a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]2801 <a href="http://validator.w3.org/check/referer"><img
Misha Brukmanf00ddb02008-12-11 18:23:24 +0000[diff] [blame]2802 src="http://www.w3.org/Icons/valid-html401-blue" alt="Valid HTML 4.01"></a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]2803
2804 <a href="mailto:sabre@nondot.org">Chris Lattner</a><br>
Reid Spencer05fe4b02006-03-14 05:39:39 +0000[diff] [blame]2805 <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]2806 Last modified: $Date$
2807</address>
2808
2809</body>
2810</html>