Jia Liu | 31d157a | 2012-02-18 12:03:15 +0000 | [diff] [blame] | 1 | //===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===// |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 2 | // |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
Chris Lattner | 4ee451d | 2007-12-29 20:36:04 +0000 | [diff] [blame] | 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 7 | // |
John Criswell | 856ba76 | 2003-10-21 15:17:13 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 9 | // |
| 10 | // This file describes the X86 instruction set, defining the instructions, and |
| 11 | // properties of the instructions which are needed for code generation, machine |
| 12 | // code emission, and analysis. |
| 13 | // |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 16 | //===----------------------------------------------------------------------===// |
| 17 | // X86 specific DAG Nodes. |
| 18 | // |
| 19 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 20 | def SDTIntShiftDOp: SDTypeProfile<1, 3, |
| 21 | [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, |
| 22 | SDTCisInt<0>, SDTCisInt<3>]>; |
| 23 | |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 24 | def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 25 | |
Stuart Hastings | 865f093 | 2011-06-03 23:53:54 +0000 | [diff] [blame] | 26 | def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; |
| 27 | def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; |
| 28 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 29 | def SDTX86Cmov : SDTypeProfile<1, 4, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 30 | [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, |
| 31 | SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 32 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 33 | // Unary and binary operator instructions that set EFLAGS as a side-effect. |
Chris Lattner | 74c8d67 | 2010-03-24 00:47:47 +0000 | [diff] [blame] | 34 | def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, |
| 35 | [SDTCisInt<0>, SDTCisVT<1, i32>]>; |
| 36 | |
Chris Lattner | 1aec4d7 | 2010-03-24 00:49:29 +0000 | [diff] [blame] | 37 | def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, |
| 38 | [SDTCisSameAs<0, 2>, |
| 39 | SDTCisSameAs<0, 3>, |
| 40 | SDTCisInt<0>, SDTCisVT<1, i32>]>; |
Chris Lattner | 5b85654 | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 41 | |
NAKAMURA Takumi | e5fffe9 | 2011-01-26 02:03:37 +0000 | [diff] [blame] | 42 | // SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS |
Chris Lattner | 5b85654 | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 43 | def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, |
| 44 | [SDTCisSameAs<0, 2>, |
| 45 | SDTCisSameAs<0, 3>, |
| 46 | SDTCisInt<0>, |
| 47 | SDTCisVT<1, i32>, |
| 48 | SDTCisVT<4, i32>]>; |
Chris Lattner | b20e0b1 | 2010-12-05 07:30:36 +0000 | [diff] [blame] | 49 | // RES1, RES2, FLAGS = op LHS, RHS |
| 50 | def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2, |
| 51 | [SDTCisSameAs<0, 1>, |
| 52 | SDTCisSameAs<0, 2>, |
| 53 | SDTCisSameAs<0, 3>, |
| 54 | SDTCisInt<0>, SDTCisVT<1, i32>]>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 55 | def SDTX86BrCond : SDTypeProfile<0, 3, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 56 | [SDTCisVT<0, OtherVT>, |
| 57 | SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 58 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 59 | def SDTX86SetCC : SDTypeProfile<1, 2, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 60 | [SDTCisVT<0, i8>, |
| 61 | SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; |
Evan Cheng | 2e489c4 | 2009-12-16 00:53:11 +0000 | [diff] [blame] | 62 | def SDTX86SetCC_C : SDTypeProfile<1, 2, |
| 63 | [SDTCisInt<0>, |
| 64 | SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; |
Evan Cheng | d5781fc | 2005-12-21 20:21:51 +0000 | [diff] [blame] | 65 | |
Benjamin Kramer | 17c836c | 2012-04-27 12:07:43 +0000 | [diff] [blame] | 66 | def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>; |
| 67 | |
Benjamin Kramer | b9bee04 | 2012-07-12 09:31:43 +0000 | [diff] [blame] | 68 | def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>; |
| 69 | |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 70 | def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 71 | SDTCisVT<2, i8>]>; |
Eli Friedman | 43f51ae | 2011-08-26 21:21:21 +0000 | [diff] [blame] | 72 | def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 73 | |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 74 | def SDTX86atomicBinary : SDTypeProfile<2, 3, [SDTCisInt<0>, SDTCisInt<1>, |
| 75 | SDTCisPtrTy<2>, SDTCisInt<3>,SDTCisInt<4>]>; |
Chris Lattner | 447ff68 | 2008-03-11 03:23:40 +0000 | [diff] [blame] | 76 | def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>; |
Evan Cheng | 898101c | 2005-12-19 23:12:38 +0000 | [diff] [blame] | 77 | |
Sean Callanan | 1c97ceb | 2009-06-23 23:25:37 +0000 | [diff] [blame] | 78 | def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; |
| 79 | def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, |
| 80 | SDTCisVT<1, i32>]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 81 | |
Dan Gohman | d35121a | 2008-05-29 19:57:41 +0000 | [diff] [blame] | 82 | def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 83 | |
Dan Gohman | d6708ea | 2009-08-15 01:38:56 +0000 | [diff] [blame] | 84 | def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, |
| 85 | SDTCisVT<1, iPTR>, |
| 86 | SDTCisVT<2, iPTR>]>; |
| 87 | |
Dan Gohman | 320afb8 | 2010-10-12 18:00:49 +0000 | [diff] [blame] | 88 | def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>, |
| 89 | SDTCisPtrTy<1>, |
| 90 | SDTCisVT<2, i32>, |
| 91 | SDTCisVT<3, i8>, |
| 92 | SDTCisVT<4, i32>]>; |
| 93 | |
Chris Lattner | ed52c8f | 2010-03-28 07:38:39 +0000 | [diff] [blame] | 94 | def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; |
| 95 | |
Anton Korobeynikov | 043f3c2 | 2010-03-06 19:32:29 +0000 | [diff] [blame] | 96 | def SDTX86Void : SDTypeProfile<0, 0, []>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 97 | |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 98 | def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; |
| 99 | |
Rafael Espindola | 2ee3db3 | 2009-04-17 14:35:58 +0000 | [diff] [blame] | 100 | def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 101 | |
Hans Wennborg | f0234fc | 2012-06-01 16:27:21 +0000 | [diff] [blame] | 102 | def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; |
| 103 | |
Eric Christopher | d8c0536 | 2010-12-09 06:25:53 +0000 | [diff] [blame] | 104 | def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>; |
Eric Christopher | 30ef0e5 | 2010-06-03 04:07:48 +0000 | [diff] [blame] | 105 | |
Rafael Espindola | d07b7ec | 2011-08-30 19:43:21 +0000 | [diff] [blame] | 106 | def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; |
| 107 | |
Michael J. Spencer | 1a2d061 | 2012-02-24 19:01:22 +0000 | [diff] [blame] | 108 | def SDT_X86WIN_FTOL : SDTypeProfile<0, 1, [SDTCisFP<0>]>; |
| 109 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 110 | def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; |
| 111 | |
Arnold Schwaighofer | c85e171 | 2007-10-11 19:40:01 +0000 | [diff] [blame] | 112 | def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; |
| 113 | |
Eric Christopher | 9a9d275 | 2010-07-22 02:48:34 +0000 | [diff] [blame] | 114 | def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>; |
Eric Christopher | 9a9d275 | 2010-07-22 02:48:34 +0000 | [diff] [blame] | 115 | |
| 116 | def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER, |
Jakob Stoklund Olesen | cfe8a96 | 2012-08-24 00:31:10 +0000 | [diff] [blame] | 117 | [SDNPHasChain,SDNPSideEffect]>; |
Eric Christopher | 9a9d275 | 2010-07-22 02:48:34 +0000 | [diff] [blame] | 118 | def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER, |
| 119 | [SDNPHasChain]>; |
| 120 | def X86SFence : SDNode<"X86ISD::SFENCE", SDT_X86MEMBARRIER, |
| 121 | [SDNPHasChain]>; |
| 122 | def X86LFence : SDNode<"X86ISD::LFENCE", SDT_X86MEMBARRIER, |
| 123 | [SDNPHasChain]>; |
| 124 | |
| 125 | |
Chris Lattner | d486d77 | 2010-03-28 05:07:17 +0000 | [diff] [blame] | 126 | def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>; |
| 127 | def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 128 | def X86shld : SDNode<"X86ISD::SHLD", SDTIntShiftDOp>; |
| 129 | def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 130 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 131 | def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 132 | def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; |
| 133 | |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 134 | def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 135 | def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 136 | [SDNPHasChain]>; |
Evan Cheng | e5f6204 | 2007-09-29 00:00:36 +0000 | [diff] [blame] | 137 | def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; |
Evan Cheng | 2e489c4 | 2009-12-16 00:53:11 +0000 | [diff] [blame] | 138 | def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 139 | |
Benjamin Kramer | 17c836c | 2012-04-27 12:07:43 +0000 | [diff] [blame] | 140 | def X86sahf : SDNode<"X86ISD::SAHF", SDTX86sahf>; |
| 141 | |
Benjamin Kramer | feae00a | 2012-07-12 18:14:57 +0000 | [diff] [blame] | 142 | def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand, |
| 143 | [SDNPHasChain, SDNPSideEffect]>; |
Benjamin Kramer | b9bee04 | 2012-07-12 09:31:43 +0000 | [diff] [blame] | 144 | |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 145 | def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, |
Chris Lattner | 036609b | 2010-12-23 18:28:41 +0000 | [diff] [blame] | 146 | [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, |
Chris Lattner | 8864155 | 2010-09-22 00:34:38 +0000 | [diff] [blame] | 147 | SDNPMayLoad, SDNPMemOperand]>; |
Eli Friedman | 43f51ae | 2011-08-26 21:21:21 +0000 | [diff] [blame] | 148 | def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair, |
Chris Lattner | 036609b | 2010-12-23 18:28:41 +0000 | [diff] [blame] | 149 | [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, |
Chris Lattner | 8864155 | 2010-09-22 00:34:38 +0000 | [diff] [blame] | 150 | SDNPMayLoad, SDNPMemOperand]>; |
Eli Friedman | 43f51ae | 2011-08-26 21:21:21 +0000 | [diff] [blame] | 151 | def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair, |
| 152 | [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, |
| 153 | SDNPMayLoad, SDNPMemOperand]>; |
| 154 | |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 155 | def X86AtomAdd64 : SDNode<"X86ISD::ATOMADD64_DAG", SDTX86atomicBinary, |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 156 | [SDNPHasChain, SDNPMayStore, |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 157 | SDNPMayLoad, SDNPMemOperand]>; |
| 158 | def X86AtomSub64 : SDNode<"X86ISD::ATOMSUB64_DAG", SDTX86atomicBinary, |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 159 | [SDNPHasChain, SDNPMayStore, |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 160 | SDNPMayLoad, SDNPMemOperand]>; |
| 161 | def X86AtomOr64 : SDNode<"X86ISD::ATOMOR64_DAG", SDTX86atomicBinary, |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 162 | [SDNPHasChain, SDNPMayStore, |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 163 | SDNPMayLoad, SDNPMemOperand]>; |
| 164 | def X86AtomXor64 : SDNode<"X86ISD::ATOMXOR64_DAG", SDTX86atomicBinary, |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 165 | [SDNPHasChain, SDNPMayStore, |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 166 | SDNPMayLoad, SDNPMemOperand]>; |
| 167 | def X86AtomAnd64 : SDNode<"X86ISD::ATOMAND64_DAG", SDTX86atomicBinary, |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 168 | [SDNPHasChain, SDNPMayStore, |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 169 | SDNPMayLoad, SDNPMemOperand]>; |
| 170 | def X86AtomNand64 : SDNode<"X86ISD::ATOMNAND64_DAG", SDTX86atomicBinary, |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 171 | [SDNPHasChain, SDNPMayStore, |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 172 | SDNPMayLoad, SDNPMemOperand]>; |
Dale Johannesen | 880ae36 | 2008-10-03 22:25:52 +0000 | [diff] [blame] | 173 | def X86AtomSwap64 : SDNode<"X86ISD::ATOMSWAP64_DAG", SDTX86atomicBinary, |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 174 | [SDNPHasChain, SDNPMayStore, |
Dale Johannesen | 880ae36 | 2008-10-03 22:25:52 +0000 | [diff] [blame] | 175 | SDNPMayLoad, SDNPMemOperand]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 176 | def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, |
Chris Lattner | 036609b | 2010-12-23 18:28:41 +0000 | [diff] [blame] | 177 | [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 178 | |
Dan Gohman | d6708ea | 2009-08-15 01:38:56 +0000 | [diff] [blame] | 179 | def X86vastart_save_xmm_regs : |
| 180 | SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", |
| 181 | SDT_X86VASTART_SAVE_XMM_REGS, |
Chris Lattner | e8cabf3 | 2010-03-19 05:07:09 +0000 | [diff] [blame] | 182 | [SDNPHasChain, SDNPVariadic]>; |
Dan Gohman | 320afb8 | 2010-10-12 18:00:49 +0000 | [diff] [blame] | 183 | def X86vaarg64 : |
| 184 | SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64, |
| 185 | [SDNPHasChain, SDNPMayLoad, SDNPMayStore, |
| 186 | SDNPMemOperand]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 187 | def X86callseq_start : |
| 188 | SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, |
Chris Lattner | 036609b | 2010-12-23 18:28:41 +0000 | [diff] [blame] | 189 | [SDNPHasChain, SDNPOutGlue]>; |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 190 | def X86callseq_end : |
| 191 | SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, |
Chris Lattner | 036609b | 2010-12-23 18:28:41 +0000 | [diff] [blame] | 192 | [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; |
Evan Cheng | b077b84 | 2005-12-21 02:39:21 +0000 | [diff] [blame] | 193 | |
Evan Cheng | e341316 | 2006-01-09 18:33:28 +0000 | [diff] [blame] | 194 | def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, |
Chris Lattner | 036609b | 2010-12-23 18:28:41 +0000 | [diff] [blame] | 195 | [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, |
Chris Lattner | e8cabf3 | 2010-03-19 05:07:09 +0000 | [diff] [blame] | 196 | SDNPVariadic]>; |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 197 | |
Chris Lattner | ed52c8f | 2010-03-28 07:38:39 +0000 | [diff] [blame] | 198 | def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, |
Chris Lattner | 036609b | 2010-12-23 18:28:41 +0000 | [diff] [blame] | 199 | [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>; |
Chris Lattner | ed52c8f | 2010-03-28 07:38:39 +0000 | [diff] [blame] | 200 | def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, |
Chris Lattner | 036609b | 2010-12-23 18:28:41 +0000 | [diff] [blame] | 201 | [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, |
Chris Lattner | 9b37aaf | 2008-01-10 05:12:37 +0000 | [diff] [blame] | 202 | SDNPMayLoad]>; |
Evan Cheng | 67f92a7 | 2006-01-11 22:15:48 +0000 | [diff] [blame] | 203 | |
Anton Korobeynikov | 043f3c2 | 2010-03-06 19:32:29 +0000 | [diff] [blame] | 204 | def X86rdtsc : SDNode<"X86ISD::RDTSC_DAG", SDTX86Void, |
Chris Lattner | 036609b | 2010-12-23 18:28:41 +0000 | [diff] [blame] | 205 | [SDNPHasChain, SDNPOutGlue, SDNPSideEffect]>; |
Evan Cheng | d90eb7f | 2006-01-05 00:27:02 +0000 | [diff] [blame] | 206 | |
Evan Cheng | 0085a28 | 2006-11-30 21:55:46 +0000 | [diff] [blame] | 207 | def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; |
| 208 | def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; |
Evan Cheng | 71fb834 | 2006-02-25 10:02:21 +0000 | [diff] [blame] | 209 | |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 210 | def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, |
Chris Lattner | 036609b | 2010-12-23 18:28:41 +0000 | [diff] [blame] | 211 | [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 212 | |
Hans Wennborg | f0234fc | 2012-06-01 16:27:21 +0000 | [diff] [blame] | 213 | def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR, |
| 214 | [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; |
| 215 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 216 | def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, |
| 217 | [SDNPHasChain]>; |
| 218 | |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 219 | def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, |
Chris Lattner | 036609b | 2010-12-23 18:28:41 +0000 | [diff] [blame] | 220 | [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; |
Lauro Ramos Venancio | b3a0417 | 2007-04-20 21:38:10 +0000 | [diff] [blame] | 221 | |
Dan Gohman | 43ffe67 | 2010-01-04 20:51:05 +0000 | [diff] [blame] | 222 | def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 223 | [SDNPCommutative]>; |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 224 | def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; |
Dan Gohman | 43ffe67 | 2010-01-04 20:51:05 +0000 | [diff] [blame] | 225 | def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 226 | [SDNPCommutative]>; |
Chris Lattner | b20e0b1 | 2010-12-05 07:30:36 +0000 | [diff] [blame] | 227 | def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 228 | [SDNPCommutative]>; |
Chris Lattner | 5b85654 | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 229 | def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>; |
| 230 | def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>; |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 231 | |
Dan Gohman | 076aee3 | 2009-03-04 19:44:21 +0000 | [diff] [blame] | 232 | def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>; |
| 233 | def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>; |
Dan Gohman | 43ffe67 | 2010-01-04 20:51:05 +0000 | [diff] [blame] | 234 | def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 235 | [SDNPCommutative]>; |
Dan Gohman | 43ffe67 | 2010-01-04 20:51:05 +0000 | [diff] [blame] | 236 | def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 237 | [SDNPCommutative]>; |
Dan Gohman | 43ffe67 | 2010-01-04 20:51:05 +0000 | [diff] [blame] | 238 | def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, |
Dan Gohman | 4361bbf | 2010-01-05 00:44:20 +0000 | [diff] [blame] | 239 | [SDNPCommutative]>; |
Craig Topper | 54a1117 | 2011-10-14 07:06:56 +0000 | [diff] [blame] | 240 | def X86andn_flag : SDNode<"X86ISD::ANDN", SDTBinaryArithWithFlags>; |
Bill Wendling | ab55ebd | 2008-12-12 00:56:36 +0000 | [diff] [blame] | 241 | |
Craig Topper | b4c9457 | 2011-10-21 06:55:01 +0000 | [diff] [blame] | 242 | def X86blsi_flag : SDNode<"X86ISD::BLSI", SDTUnaryArithWithFlags>; |
| 243 | def X86blsmsk_flag : SDNode<"X86ISD::BLSMSK", SDTUnaryArithWithFlags>; |
| 244 | def X86blsr_flag : SDNode<"X86ISD::BLSR", SDTUnaryArithWithFlags>; |
| 245 | |
Evan Cheng | 73f24c9 | 2009-03-30 21:36:47 +0000 | [diff] [blame] | 246 | def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; |
| 247 | |
Michael J. Spencer | e9c253e | 2010-10-21 01:41:01 +0000 | [diff] [blame] | 248 | def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDTX86Void, |
Chris Lattner | 036609b | 2010-12-23 18:28:41 +0000 | [diff] [blame] | 249 | [SDNPHasChain, SDNPInGlue, SDNPOutGlue]>; |
Michael J. Spencer | e9c253e | 2010-10-21 01:41:01 +0000 | [diff] [blame] | 250 | |
Rafael Espindola | d07b7ec | 2011-08-30 19:43:21 +0000 | [diff] [blame] | 251 | def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, |
| 252 | [SDNPHasChain]>; |
| 253 | |
Eric Christopher | 30ef0e5 | 2010-06-03 04:07:48 +0000 | [diff] [blame] | 254 | def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, |
Chris Lattner | 036609b | 2010-12-23 18:28:41 +0000 | [diff] [blame] | 255 | [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; |
Anton Korobeynikov | 043f3c2 | 2010-03-06 19:32:29 +0000 | [diff] [blame] | 256 | |
Michael J. Spencer | 1a2d061 | 2012-02-24 19:01:22 +0000 | [diff] [blame] | 257 | def X86WinFTOL : SDNode<"X86ISD::WIN_FTOL", SDT_X86WIN_FTOL, |
| 258 | [SDNPHasChain, SDNPOutGlue]>; |
| 259 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 260 | //===----------------------------------------------------------------------===// |
| 261 | // X86 Operand Definitions. |
| 262 | // |
| 263 | |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 264 | // A version of ptr_rc which excludes SP, ESP, and RSP. This is used for |
| 265 | // the index operand of an address, to conform to x86 encoding restrictions. |
| 266 | def ptr_rc_nosp : PointerLikeRegClass<1>; |
Chris Lattner | 7680e73 | 2009-06-20 19:34:09 +0000 | [diff] [blame] | 267 | |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 268 | // *mem - Operand definitions for the funky X86 addressing mode operands. |
| 269 | // |
Devang Patel | c59d9df | 2012-01-12 01:51:42 +0000 | [diff] [blame] | 270 | def X86MemAsmOperand : AsmOperandClass { |
| 271 | let Name = "Mem"; let PredicateMethod = "isMem"; |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 272 | } |
Devang Patel | c59d9df | 2012-01-12 01:51:42 +0000 | [diff] [blame] | 273 | def X86Mem8AsmOperand : AsmOperandClass { |
| 274 | let Name = "Mem8"; let PredicateMethod = "isMem8"; |
| 275 | } |
| 276 | def X86Mem16AsmOperand : AsmOperandClass { |
| 277 | let Name = "Mem16"; let PredicateMethod = "isMem16"; |
| 278 | } |
| 279 | def X86Mem32AsmOperand : AsmOperandClass { |
| 280 | let Name = "Mem32"; let PredicateMethod = "isMem32"; |
| 281 | } |
| 282 | def X86Mem64AsmOperand : AsmOperandClass { |
| 283 | let Name = "Mem64"; let PredicateMethod = "isMem64"; |
| 284 | } |
| 285 | def X86Mem80AsmOperand : AsmOperandClass { |
| 286 | let Name = "Mem80"; let PredicateMethod = "isMem80"; |
| 287 | } |
| 288 | def X86Mem128AsmOperand : AsmOperandClass { |
| 289 | let Name = "Mem128"; let PredicateMethod = "isMem128"; |
| 290 | } |
| 291 | def X86Mem256AsmOperand : AsmOperandClass { |
| 292 | let Name = "Mem256"; let PredicateMethod = "isMem256"; |
| 293 | } |
| 294 | |
Craig Topper | 75dc33a | 2012-07-18 04:11:12 +0000 | [diff] [blame] | 295 | // Gather mem operands |
| 296 | def X86MemVX32Operand : AsmOperandClass { |
| 297 | let Name = "MemVX32"; let PredicateMethod = "isMemVX32"; |
| 298 | } |
| 299 | def X86MemVY32Operand : AsmOperandClass { |
| 300 | let Name = "MemVY32"; let PredicateMethod = "isMemVY32"; |
| 301 | } |
| 302 | def X86MemVX64Operand : AsmOperandClass { |
| 303 | let Name = "MemVX64"; let PredicateMethod = "isMemVX64"; |
| 304 | } |
| 305 | def X86MemVY64Operand : AsmOperandClass { |
| 306 | let Name = "MemVY64"; let PredicateMethod = "isMemVY64"; |
| 307 | } |
| 308 | |
Daniel Dunbar | c26ae5a | 2010-05-06 22:39:14 +0000 | [diff] [blame] | 309 | def X86AbsMemAsmOperand : AsmOperandClass { |
| 310 | let Name = "AbsMem"; |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 311 | let SuperClasses = [X86MemAsmOperand]; |
Daniel Dunbar | c26ae5a | 2010-05-06 22:39:14 +0000 | [diff] [blame] | 312 | } |
Evan Cheng | af78ef5 | 2006-05-17 21:21:41 +0000 | [diff] [blame] | 313 | class X86MemOperand<string printMethod> : Operand<iPTR> { |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 314 | let PrintMethod = printMethod; |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 315 | let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 316 | let ParserMatchClass = X86MemAsmOperand; |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 317 | } |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 318 | |
Benjamin Kramer | 3be41b7 | 2011-07-14 21:47:22 +0000 | [diff] [blame] | 319 | let OperandType = "OPERAND_MEMORY" in { |
Sean Callanan | 9947bbb | 2009-09-03 00:04:47 +0000 | [diff] [blame] | 320 | def opaque32mem : X86MemOperand<"printopaquemem">; |
| 321 | def opaque48mem : X86MemOperand<"printopaquemem">; |
| 322 | def opaque80mem : X86MemOperand<"printopaquemem">; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 323 | def opaque512mem : X86MemOperand<"printopaquemem">; |
| 324 | |
Devang Patel | c59d9df | 2012-01-12 01:51:42 +0000 | [diff] [blame] | 325 | def i8mem : X86MemOperand<"printi8mem"> { |
| 326 | let ParserMatchClass = X86Mem8AsmOperand; } |
| 327 | def i16mem : X86MemOperand<"printi16mem"> { |
| 328 | let ParserMatchClass = X86Mem16AsmOperand; } |
| 329 | def i32mem : X86MemOperand<"printi32mem"> { |
| 330 | let ParserMatchClass = X86Mem32AsmOperand; } |
| 331 | def i64mem : X86MemOperand<"printi64mem"> { |
| 332 | let ParserMatchClass = X86Mem64AsmOperand; } |
| 333 | def i128mem : X86MemOperand<"printi128mem"> { |
| 334 | let ParserMatchClass = X86Mem128AsmOperand; } |
| 335 | def i256mem : X86MemOperand<"printi256mem"> { |
| 336 | let ParserMatchClass = X86Mem256AsmOperand; } |
| 337 | def f32mem : X86MemOperand<"printf32mem"> { |
| 338 | let ParserMatchClass = X86Mem32AsmOperand; } |
| 339 | def f64mem : X86MemOperand<"printf64mem"> { |
| 340 | let ParserMatchClass = X86Mem64AsmOperand; } |
| 341 | def f80mem : X86MemOperand<"printf80mem"> { |
| 342 | let ParserMatchClass = X86Mem80AsmOperand; } |
| 343 | def f128mem : X86MemOperand<"printf128mem"> { |
| 344 | let ParserMatchClass = X86Mem128AsmOperand; } |
| 345 | def f256mem : X86MemOperand<"printf256mem">{ |
| 346 | let ParserMatchClass = X86Mem256AsmOperand; } |
Craig Topper | 75dc33a | 2012-07-18 04:11:12 +0000 | [diff] [blame] | 347 | |
| 348 | // Gather mem operands |
| 349 | def vx32mem : X86MemOperand<"printi32mem">{ |
Manman Ren | 1f7a1b6 | 2012-06-26 19:47:59 +0000 | [diff] [blame] | 350 | let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm); |
Craig Topper | 75dc33a | 2012-07-18 04:11:12 +0000 | [diff] [blame] | 351 | let ParserMatchClass = X86MemVX32Operand; } |
| 352 | def vy32mem : X86MemOperand<"printi32mem">{ |
Manman Ren | 1f7a1b6 | 2012-06-26 19:47:59 +0000 | [diff] [blame] | 353 | let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm); |
Craig Topper | 75dc33a | 2012-07-18 04:11:12 +0000 | [diff] [blame] | 354 | let ParserMatchClass = X86MemVY32Operand; } |
| 355 | def vx64mem : X86MemOperand<"printi64mem">{ |
| 356 | let MIOperandInfo = (ops ptr_rc, i8imm, VR128, i32imm, i8imm); |
| 357 | let ParserMatchClass = X86MemVX64Operand; } |
| 358 | def vy64mem : X86MemOperand<"printi64mem">{ |
| 359 | let MIOperandInfo = (ops ptr_rc, i8imm, VR256, i32imm, i8imm); |
| 360 | let ParserMatchClass = X86MemVY64Operand; } |
Benjamin Kramer | 3be41b7 | 2011-07-14 21:47:22 +0000 | [diff] [blame] | 361 | } |
Nate Begeman | 391c5d2 | 2005-11-30 18:54:35 +0000 | [diff] [blame] | 362 | |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 363 | // A version of i8mem for use on x86-64 that uses GR64_NOREX instead of |
| 364 | // plain GR64, so that it doesn't potentially require a REX prefix. |
| 365 | def i8mem_NOREX : Operand<i64> { |
| 366 | let PrintMethod = "printi8mem"; |
Dan Gohman | a4714e0 | 2009-07-30 01:56:29 +0000 | [diff] [blame] | 367 | let MIOperandInfo = (ops GR64_NOREX, i8imm, GR64_NOREX_NOSP, i32imm, i8imm); |
Devang Patel | 2f8af1d | 2012-01-17 21:48:03 +0000 | [diff] [blame] | 368 | let ParserMatchClass = X86Mem8AsmOperand; |
Benjamin Kramer | 3be41b7 | 2011-07-14 21:47:22 +0000 | [diff] [blame] | 369 | let OperandType = "OPERAND_MEMORY"; |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 370 | } |
| 371 | |
NAKAMURA Takumi | 7754f85 | 2011-01-26 02:04:09 +0000 | [diff] [blame] | 372 | // GPRs available for tailcall. |
Jakob Stoklund Olesen | cf661a0 | 2012-05-09 01:50:09 +0000 | [diff] [blame] | 373 | // It represents GR32_TC, GR64_TC or GR64_TCW64. |
NAKAMURA Takumi | 7754f85 | 2011-01-26 02:04:09 +0000 | [diff] [blame] | 374 | def ptr_rc_tailcall : PointerLikeRegClass<2>; |
| 375 | |
Evan Cheng | f48ef03 | 2010-03-14 03:48:46 +0000 | [diff] [blame] | 376 | // Special i32mem for addresses of load folding tail calls. These are not |
| 377 | // allowed to use callee-saved registers since they must be scheduled |
| 378 | // after callee-saved register are popped. |
| 379 | def i32mem_TC : Operand<i32> { |
| 380 | let PrintMethod = "printi32mem"; |
Jakob Stoklund Olesen | cf661a0 | 2012-05-09 01:50:09 +0000 | [diff] [blame] | 381 | let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall, |
| 382 | i32imm, i8imm); |
Devang Patel | 2f8af1d | 2012-01-17 21:48:03 +0000 | [diff] [blame] | 383 | let ParserMatchClass = X86Mem32AsmOperand; |
Benjamin Kramer | 3be41b7 | 2011-07-14 21:47:22 +0000 | [diff] [blame] | 384 | let OperandType = "OPERAND_MEMORY"; |
Evan Cheng | f48ef03 | 2010-03-14 03:48:46 +0000 | [diff] [blame] | 385 | } |
| 386 | |
Chris Lattner | 41efbfa | 2010-10-05 06:37:31 +0000 | [diff] [blame] | 387 | // Special i64mem for addresses of load folding tail calls. These are not |
| 388 | // allowed to use callee-saved registers since they must be scheduled |
| 389 | // after callee-saved register are popped. |
| 390 | def i64mem_TC : Operand<i64> { |
| 391 | let PrintMethod = "printi64mem"; |
NAKAMURA Takumi | 7754f85 | 2011-01-26 02:04:09 +0000 | [diff] [blame] | 392 | let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, |
| 393 | ptr_rc_tailcall, i32imm, i8imm); |
Devang Patel | 2f8af1d | 2012-01-17 21:48:03 +0000 | [diff] [blame] | 394 | let ParserMatchClass = X86Mem64AsmOperand; |
Benjamin Kramer | 3be41b7 | 2011-07-14 21:47:22 +0000 | [diff] [blame] | 395 | let OperandType = "OPERAND_MEMORY"; |
Chris Lattner | 41efbfa | 2010-10-05 06:37:31 +0000 | [diff] [blame] | 396 | } |
Evan Cheng | 25ab690 | 2006-09-08 06:48:29 +0000 | [diff] [blame] | 397 | |
Benjamin Kramer | 3be41b7 | 2011-07-14 21:47:22 +0000 | [diff] [blame] | 398 | let OperandType = "OPERAND_PCREL", |
| 399 | ParserMatchClass = X86AbsMemAsmOperand, |
Daniel Dunbar | b834f5d | 2010-01-30 01:02:48 +0000 | [diff] [blame] | 400 | PrintMethod = "print_pcrel_imm" in { |
Daniel Dunbar | 728e5eb | 2010-01-30 00:24:12 +0000 | [diff] [blame] | 401 | def i32imm_pcrel : Operand<i32>; |
Chris Lattner | 9fc0522 | 2010-07-07 22:27:31 +0000 | [diff] [blame] | 402 | def i16imm_pcrel : Operand<i16>; |
Daniel Dunbar | 728e5eb | 2010-01-30 00:24:12 +0000 | [diff] [blame] | 403 | |
| 404 | def offset8 : Operand<i64>; |
| 405 | def offset16 : Operand<i64>; |
| 406 | def offset32 : Operand<i64>; |
| 407 | def offset64 : Operand<i64>; |
| 408 | |
| 409 | // Branch targets have OtherVT type and print as pc-relative values. |
| 410 | def brtarget : Operand<OtherVT>; |
| 411 | def brtarget8 : Operand<OtherVT>; |
| 412 | |
| 413 | } |
| 414 | |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 415 | def SSECC : Operand<i8> { |
| 416 | let PrintMethod = "printSSECC"; |
Benjamin Kramer | 3be41b7 | 2011-07-14 21:47:22 +0000 | [diff] [blame] | 417 | let OperandType = "OPERAND_IMMEDIATE"; |
Nate Begeman | 16b04f3 | 2005-07-15 00:38:55 +0000 | [diff] [blame] | 418 | } |
Chris Lattner | 66fa1dc | 2004-08-11 02:25:00 +0000 | [diff] [blame] | 419 | |
Craig Topper | 769bbfd | 2012-04-03 05:20:24 +0000 | [diff] [blame] | 420 | def AVXCC : Operand<i8> { |
| 421 | let PrintMethod = "printSSECC"; |
| 422 | let OperandType = "OPERAND_IMMEDIATE"; |
| 423 | } |
| 424 | |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 425 | class ImmSExtAsmOperandClass : AsmOperandClass { |
Daniel Dunbar | 54ddf3d | 2010-05-22 21:02:29 +0000 | [diff] [blame] | 426 | let SuperClasses = [ImmAsmOperand]; |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 427 | let RenderMethod = "addImmOperands"; |
Daniel Dunbar | 1fe591d | 2010-05-20 20:20:39 +0000 | [diff] [blame] | 428 | } |
| 429 | |
Kevin Enderby | c37d4bb | 2011-07-27 23:01:50 +0000 | [diff] [blame] | 430 | class ImmZExtAsmOperandClass : AsmOperandClass { |
| 431 | let SuperClasses = [ImmAsmOperand]; |
| 432 | let RenderMethod = "addImmOperands"; |
| 433 | } |
| 434 | |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 435 | // Sign-extended immediate classes. We don't need to define the full lattice |
| 436 | // here because there is no instruction with an ambiguity between ImmSExti64i32 |
| 437 | // and ImmSExti32i8. |
| 438 | // |
| 439 | // The strange ranges come from the fact that the assembler always works with |
| 440 | // 64-bit immediates, but for a 16-bit target value we want to accept both "-1" |
| 441 | // (which will be a -1ULL), and "0xFF" (-1 in 16-bits). |
| 442 | |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 443 | // [0, 0x7FFFFFFF] | |
| 444 | // [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 445 | def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { |
| 446 | let Name = "ImmSExti64i32"; |
| 447 | } |
| 448 | |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 449 | // [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | |
| 450 | // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 451 | def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { |
| 452 | let Name = "ImmSExti16i8"; |
| 453 | let SuperClasses = [ImmSExti64i32AsmOperand]; |
| 454 | } |
| 455 | |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 456 | // [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | |
| 457 | // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 458 | def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { |
| 459 | let Name = "ImmSExti32i8"; |
| 460 | } |
| 461 | |
Kevin Enderby | c37d4bb | 2011-07-27 23:01:50 +0000 | [diff] [blame] | 462 | // [0, 0x000000FF] |
| 463 | def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass { |
| 464 | let Name = "ImmZExtu32u8"; |
| 465 | } |
| 466 | |
| 467 | |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 468 | // [0, 0x0000007F] | |
| 469 | // [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 470 | def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { |
| 471 | let Name = "ImmSExti64i8"; |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 472 | let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, |
| 473 | ImmSExti64i32AsmOperand]; |
Daniel Dunbar | 338825c | 2009-08-10 18:41:10 +0000 | [diff] [blame] | 474 | } |
| 475 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 476 | // A couple of more descriptive operand definitions. |
| 477 | // 16-bits but only 8 bits are significant. |
Daniel Dunbar | 5fe6338 | 2009-08-09 07:20:21 +0000 | [diff] [blame] | 478 | def i16i8imm : Operand<i16> { |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 479 | let ParserMatchClass = ImmSExti16i8AsmOperand; |
Benjamin Kramer | 3be41b7 | 2011-07-14 21:47:22 +0000 | [diff] [blame] | 480 | let OperandType = "OPERAND_IMMEDIATE"; |
Daniel Dunbar | 5fe6338 | 2009-08-09 07:20:21 +0000 | [diff] [blame] | 481 | } |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 482 | // 32-bits but only 8 bits are significant. |
Daniel Dunbar | 5fe6338 | 2009-08-09 07:20:21 +0000 | [diff] [blame] | 483 | def i32i8imm : Operand<i32> { |
Daniel Dunbar | 62e4c67 | 2010-05-22 21:02:33 +0000 | [diff] [blame] | 484 | let ParserMatchClass = ImmSExti32i8AsmOperand; |
Benjamin Kramer | 3be41b7 | 2011-07-14 21:47:22 +0000 | [diff] [blame] | 485 | let OperandType = "OPERAND_IMMEDIATE"; |
Daniel Dunbar | 5fe6338 | 2009-08-09 07:20:21 +0000 | [diff] [blame] | 486 | } |
Kevin Enderby | c37d4bb | 2011-07-27 23:01:50 +0000 | [diff] [blame] | 487 | // 32-bits but only 8 bits are significant, and those 8 bits are unsigned. |
| 488 | def u32u8imm : Operand<i32> { |
| 489 | let ParserMatchClass = ImmZExtu32u8AsmOperand; |
| 490 | let OperandType = "OPERAND_IMMEDIATE"; |
| 491 | } |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 492 | |
Chris Lattner | 41efbfa | 2010-10-05 06:37:31 +0000 | [diff] [blame] | 493 | // 64-bits but only 32 bits are significant. |
| 494 | def i64i32imm : Operand<i64> { |
| 495 | let ParserMatchClass = ImmSExti64i32AsmOperand; |
Benjamin Kramer | 3be41b7 | 2011-07-14 21:47:22 +0000 | [diff] [blame] | 496 | let OperandType = "OPERAND_IMMEDIATE"; |
Chris Lattner | 41efbfa | 2010-10-05 06:37:31 +0000 | [diff] [blame] | 497 | } |
| 498 | |
| 499 | // 64-bits but only 32 bits are significant, and those bits are treated as being |
| 500 | // pc relative. |
| 501 | def i64i32imm_pcrel : Operand<i64> { |
| 502 | let PrintMethod = "print_pcrel_imm"; |
| 503 | let ParserMatchClass = X86AbsMemAsmOperand; |
Benjamin Kramer | 3c1fece | 2011-08-22 22:55:32 +0000 | [diff] [blame] | 504 | let OperandType = "OPERAND_PCREL"; |
Chris Lattner | 41efbfa | 2010-10-05 06:37:31 +0000 | [diff] [blame] | 505 | } |
| 506 | |
| 507 | // 64-bits but only 8 bits are significant. |
| 508 | def i64i8imm : Operand<i64> { |
| 509 | let ParserMatchClass = ImmSExti64i8AsmOperand; |
Benjamin Kramer | 3c1fece | 2011-08-22 22:55:32 +0000 | [diff] [blame] | 510 | let OperandType = "OPERAND_IMMEDIATE"; |
Chris Lattner | 41efbfa | 2010-10-05 06:37:31 +0000 | [diff] [blame] | 511 | } |
| 512 | |
| 513 | def lea64_32mem : Operand<i32> { |
| 514 | let PrintMethod = "printi32mem"; |
| 515 | let AsmOperandLowerMethod = "lower_lea64_32mem"; |
| 516 | let MIOperandInfo = (ops GR32, i8imm, GR32_NOSP, i32imm, i8imm); |
| 517 | let ParserMatchClass = X86MemAsmOperand; |
| 518 | } |
| 519 | |
| 520 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 521 | //===----------------------------------------------------------------------===// |
| 522 | // X86 Complex Pattern Definitions. |
| 523 | // |
| 524 | |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 525 | // Define X86 specific addressing mode. |
Chris Lattner | b86faa1 | 2010-09-21 22:07:31 +0000 | [diff] [blame] | 526 | def addr : ComplexPattern<iPTR, 5, "SelectAddr", [], [SDNPWantParent]>; |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 527 | def lea32addr : ComplexPattern<i32, 5, "SelectLEAAddr", |
Dan Gohman | a98634b | 2009-08-02 16:09:17 +0000 | [diff] [blame] | 528 | [add, sub, mul, X86mul_imm, shl, or, frameindex], |
| 529 | []>; |
Chris Lattner | 599b531 | 2010-07-08 23:46:44 +0000 | [diff] [blame] | 530 | def tls32addr : ComplexPattern<i32, 5, "SelectTLSADDRAddr", |
Chris Lattner | 5c0b16d | 2009-06-20 20:38:48 +0000 | [diff] [blame] | 531 | [tglobaltlsaddr], []>; |
Evan Cheng | ec693f7 | 2005-12-08 02:01:35 +0000 | [diff] [blame] | 532 | |
Hans Wennborg | f0234fc | 2012-06-01 16:27:21 +0000 | [diff] [blame] | 533 | def tls32baseaddr : ComplexPattern<i32, 5, "SelectTLSADDRAddr", |
| 534 | [tglobaltlsaddr], []>; |
| 535 | |
Chris Lattner | 41efbfa | 2010-10-05 06:37:31 +0000 | [diff] [blame] | 536 | def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr", |
| 537 | [add, sub, mul, X86mul_imm, shl, or, frameindex, |
| 538 | X86WrapperRIP], []>; |
| 539 | |
| 540 | def tls64addr : ComplexPattern<i64, 5, "SelectTLSADDRAddr", |
| 541 | [tglobaltlsaddr], []>; |
| 542 | |
Hans Wennborg | f0234fc | 2012-06-01 16:27:21 +0000 | [diff] [blame] | 543 | def tls64baseaddr : ComplexPattern<i64, 5, "SelectTLSADDRAddr", |
| 544 | [tglobaltlsaddr], []>; |
| 545 | |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 546 | //===----------------------------------------------------------------------===// |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 547 | // X86 Instruction Predicate Definitions. |
Chris Lattner | 314a113 | 2010-03-14 18:31:44 +0000 | [diff] [blame] | 548 | def HasCMov : Predicate<"Subtarget->hasCMov()">; |
| 549 | def NoCMov : Predicate<"!Subtarget->hasCMov()">; |
Nate Begeman | 5812b10 | 2010-12-03 22:29:15 +0000 | [diff] [blame] | 550 | |
Nate Begeman | 2ea8ee7 | 2010-12-10 00:26:57 +0000 | [diff] [blame] | 551 | def HasMMX : Predicate<"Subtarget->hasMMX()">; |
Chris Lattner | 548abfc | 2010-10-03 18:08:05 +0000 | [diff] [blame] | 552 | def Has3DNow : Predicate<"Subtarget->has3DNow()">; |
| 553 | def Has3DNowA : Predicate<"Subtarget->has3DNowA()">; |
Nate Begeman | 2ea8ee7 | 2010-12-10 00:26:57 +0000 | [diff] [blame] | 554 | def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; |
| 555 | def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; |
| 556 | def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; |
| 557 | def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; |
| 558 | def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; |
| 559 | def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; |
| 560 | def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">; |
David Greene | 343dadb | 2009-06-26 22:46:54 +0000 | [diff] [blame] | 561 | def HasAVX : Predicate<"Subtarget->hasAVX()">; |
Craig Topper | e7b0550 | 2011-10-30 19:57:21 +0000 | [diff] [blame] | 562 | def HasAVX2 : Predicate<"Subtarget->hasAVX2()">; |
Craig Topper | 3a1683f | 2012-08-27 06:08:57 +0000 | [diff] [blame^] | 563 | def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">; |
Nate Begeman | 2ea8ee7 | 2010-12-10 00:26:57 +0000 | [diff] [blame] | 564 | |
Craig Topper | c48b301 | 2011-10-11 07:13:09 +0000 | [diff] [blame] | 565 | def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">; |
Nate Begeman | 2ea8ee7 | 2010-12-10 00:26:57 +0000 | [diff] [blame] | 566 | def HasAES : Predicate<"Subtarget->hasAES()">; |
Benjamin Kramer | c8e340d | 2012-05-31 14:34:17 +0000 | [diff] [blame] | 567 | def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">; |
Craig Topper | a15f9d5 | 2012-06-03 18:58:46 +0000 | [diff] [blame] | 568 | def HasFMA : Predicate<"Subtarget->hasFMA()">; |
David Greene | 343dadb | 2009-06-26 22:46:54 +0000 | [diff] [blame] | 569 | def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; |
Jan Sjödin | 37e7ecf | 2011-12-12 19:37:49 +0000 | [diff] [blame] | 570 | def HasXOP : Predicate<"Subtarget->hasXOP()">; |
Craig Topper | 581fe82 | 2011-10-03 17:28:23 +0000 | [diff] [blame] | 571 | def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">; |
| 572 | def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">; |
Craig Topper | da39404 | 2011-10-09 07:31:39 +0000 | [diff] [blame] | 573 | def HasF16C : Predicate<"Subtarget->hasF16C()">; |
Craig Topper | e7b0550 | 2011-10-30 19:57:21 +0000 | [diff] [blame] | 574 | def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">; |
Craig Topper | 37f2167 | 2011-10-11 06:44:02 +0000 | [diff] [blame] | 575 | def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">; |
Craig Topper | 909652f | 2011-10-14 03:21:46 +0000 | [diff] [blame] | 576 | def HasBMI : Predicate<"Subtarget->hasBMI()">; |
Craig Topper | b53fa8b | 2011-10-16 07:55:05 +0000 | [diff] [blame] | 577 | def HasBMI2 : Predicate<"Subtarget->hasBMI2()">; |
Craig Topper | c6d5995 | 2012-01-10 06:30:56 +0000 | [diff] [blame] | 578 | def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; |
| 579 | def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; |
Eli Friedman | 43f51ae | 2011-08-26 21:21:21 +0000 | [diff] [blame] | 580 | def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">; |
Evan Cheng | ebdeeab | 2011-07-08 01:53:10 +0000 | [diff] [blame] | 581 | def In32BitMode : Predicate<"!Subtarget->is64Bit()">, |
| 582 | AssemblerPredicate<"!Mode64Bit">; |
| 583 | def In64BitMode : Predicate<"Subtarget->is64Bit()">, |
| 584 | AssemblerPredicate<"Mode64Bit">; |
Anton Korobeynikov | cf6b739 | 2009-08-03 08:12:53 +0000 | [diff] [blame] | 585 | def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; |
David Meyer | 928698b | 2011-10-18 05:29:23 +0000 | [diff] [blame] | 586 | def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; |
| 587 | def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; |
Anton Korobeynikov | d7697d0 | 2009-08-06 11:23:24 +0000 | [diff] [blame] | 588 | def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; |
| 589 | def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; |
| 590 | def FarData : Predicate<"TM.getCodeModel() != CodeModel::Small &&" |
Anton Korobeynikov | 186fa1d | 2009-08-06 09:11:19 +0000 | [diff] [blame] | 591 | "TM.getCodeModel() != CodeModel::Kernel">; |
Anton Korobeynikov | d7697d0 | 2009-08-06 11:23:24 +0000 | [diff] [blame] | 592 | def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" |
| 593 | "TM.getCodeModel() == CodeModel::Kernel">; |
Evan Cheng | 28b51439 | 2006-12-05 19:50:18 +0000 | [diff] [blame] | 594 | def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">; |
Evan Cheng | cb0f06e | 2010-03-25 00:10:31 +0000 | [diff] [blame] | 595 | def IsNotPIC : Predicate<"TM.getRelocationModel() != Reloc::PIC_">; |
Evan Cheng | b1f4981 | 2009-12-22 17:47:23 +0000 | [diff] [blame] | 596 | def OptForSize : Predicate<"OptForSize">; |
Evan Cheng | b7a75a5 | 2008-09-26 23:41:32 +0000 | [diff] [blame] | 597 | def OptForSpeed : Predicate<"!OptForSize">; |
Evan Cheng | ccb6976 | 2009-01-02 05:35:45 +0000 | [diff] [blame] | 598 | def FastBTMem : Predicate<"!Subtarget->isBTMemSlow()">; |
Evan Cheng | d7f666a | 2009-05-20 04:53:57 +0000 | [diff] [blame] | 599 | def CallImmAddr : Predicate<"Subtarget->IsLegalToCallImmediateAddr(TM)">; |
Evan Cheng | bbc8ddb | 2005-12-20 22:59:51 +0000 | [diff] [blame] | 600 | |
| 601 | //===----------------------------------------------------------------------===// |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 602 | // X86 Instruction Format Definitions. |
Evan Cheng | aed7c72 | 2005-12-17 01:24:02 +0000 | [diff] [blame] | 603 | // |
| 604 | |
Evan Cheng | c64a1a9 | 2007-07-31 08:04:03 +0000 | [diff] [blame] | 605 | include "X86InstrFormats.td" |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 606 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 607 | //===----------------------------------------------------------------------===// |
Chris Lattner | 5437906 | 2011-04-17 21:38:24 +0000 | [diff] [blame] | 608 | // Pattern fragments. |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 609 | // |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 610 | |
| 611 | // X86 specific condition code. These correspond to CondCode in |
Nate Begeman | 9a22530 | 2007-05-06 04:00:55 +0000 | [diff] [blame] | 612 | // X86InstrInfo.h. They must be kept in synch. |
Dan Gohman | 653456c | 2009-01-07 00:15:08 +0000 | [diff] [blame] | 613 | def X86_COND_A : PatLeaf<(i8 0)>; // alt. COND_NBE |
| 614 | def X86_COND_AE : PatLeaf<(i8 1)>; // alt. COND_NC |
| 615 | def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C |
| 616 | def X86_COND_BE : PatLeaf<(i8 3)>; // alt. COND_NA |
| 617 | def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z |
| 618 | def X86_COND_G : PatLeaf<(i8 5)>; // alt. COND_NLE |
| 619 | def X86_COND_GE : PatLeaf<(i8 6)>; // alt. COND_NL |
| 620 | def X86_COND_L : PatLeaf<(i8 7)>; // alt. COND_NGE |
| 621 | def X86_COND_LE : PatLeaf<(i8 8)>; // alt. COND_NG |
| 622 | def X86_COND_NE : PatLeaf<(i8 9)>; // alt. COND_NZ |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 623 | def X86_COND_NO : PatLeaf<(i8 10)>; |
Dan Gohman | 653456c | 2009-01-07 00:15:08 +0000 | [diff] [blame] | 624 | def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 625 | def X86_COND_NS : PatLeaf<(i8 12)>; |
Dan Gohman | 653456c | 2009-01-07 00:15:08 +0000 | [diff] [blame] | 626 | def X86_COND_O : PatLeaf<(i8 13)>; |
| 627 | def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE |
| 628 | def X86_COND_S : PatLeaf<(i8 15)>; |
Evan Cheng | d9558e0 | 2006-01-06 00:43:03 +0000 | [diff] [blame] | 629 | |
Chris Lattner | 202a7a1 | 2011-04-18 06:36:55 +0000 | [diff] [blame] | 630 | let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs. |
Nick Lewycky | 52a8399 | 2011-04-20 03:19:42 +0000 | [diff] [blame] | 631 | def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>; |
| 632 | def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>; |
| 633 | def i64immSExt8 : ImmLeaf<i64, [{ return Imm == (int8_t)Imm; }]>; |
Chris Lattner | 202a7a1 | 2011-04-18 06:36:55 +0000 | [diff] [blame] | 634 | } |
| 635 | |
Chris Lattner | 5662bc9 | 2011-04-17 22:12:55 +0000 | [diff] [blame] | 636 | def i64immSExt32 : ImmLeaf<i64, [{ return Imm == (int32_t)Imm; }]>; |
Chris Lattner | 7ed1391 | 2011-04-17 22:05:17 +0000 | [diff] [blame] | 637 | |
| 638 | |
Chris Lattner | 5662bc9 | 2011-04-17 22:12:55 +0000 | [diff] [blame] | 639 | // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit |
| 640 | // unsigned field. |
| 641 | def i64immZExt32 : ImmLeaf<i64, [{ return (uint64_t)Imm == (uint32_t)Imm; }]>; |
Chris Lattner | 7ed1391 | 2011-04-17 22:05:17 +0000 | [diff] [blame] | 642 | |
Chris Lattner | 5662bc9 | 2011-04-17 22:12:55 +0000 | [diff] [blame] | 643 | def i64immZExt32SExt8 : ImmLeaf<i64, [{ |
| 644 | return (uint64_t)Imm == (uint32_t)Imm && (int32_t)Imm == (int8_t)Imm; |
Rafael Espindola | dba81cf | 2010-10-13 13:31:20 +0000 | [diff] [blame] | 645 | }]>; |
| 646 | |
Evan Cheng | 605c415 | 2005-12-13 01:57:51 +0000 | [diff] [blame] | 647 | // Helper fragments for loads. |
Evan Cheng | b656443 | 2008-05-13 18:59:59 +0000 | [diff] [blame] | 648 | // It's always safe to treat a anyext i16 load as a i32 load if the i16 is |
| 649 | // known to be 32-bit aligned or better. Ditto for i8 to i16. |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 650 | def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 651 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 652 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 653 | if (ExtType == ISD::NON_EXTLOAD) |
| 654 | return true; |
| 655 | if (ExtType == ISD::EXTLOAD) |
| 656 | return LD->getAlignment() >= 2 && !LD->isVolatile(); |
Evan Cheng | fa7fd33 | 2008-05-13 00:54:02 +0000 | [diff] [blame] | 657 | return false; |
| 658 | }]>; |
| 659 | |
Chris Lattner | f85eff7 | 2010-03-03 01:52:59 +0000 | [diff] [blame] | 660 | def loadi16_anyext : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)),[{ |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 661 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Evan Cheng | ca57f78 | 2008-09-24 23:27:55 +0000 | [diff] [blame] | 662 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 663 | if (ExtType == ISD::EXTLOAD) |
| 664 | return LD->getAlignment() >= 2 && !LD->isVolatile(); |
| 665 | return false; |
| 666 | }]>; |
| 667 | |
Dan Gohman | 3358629 | 2008-10-15 06:50:19 +0000 | [diff] [blame] | 668 | def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 669 | LoadSDNode *LD = cast<LoadSDNode>(N); |
Dan Gohman | 67ca6be | 2008-08-20 15:24:22 +0000 | [diff] [blame] | 670 | ISD::LoadExtType ExtType = LD->getExtensionType(); |
| 671 | if (ExtType == ISD::NON_EXTLOAD) |
| 672 | return true; |
| 673 | if (ExtType == ISD::EXTLOAD) |
| 674 | return LD->getAlignment() >= 4 && !LD->isVolatile(); |
Evan Cheng | fa7fd33 | 2008-05-13 00:54:02 +0000 | [diff] [blame] | 675 | return false; |
| 676 | }]>; |
| 677 | |
Chris Lattner | b86faa1 | 2010-09-21 22:07:31 +0000 | [diff] [blame] | 678 | def loadi8 : PatFrag<(ops node:$ptr), (i8 (load node:$ptr))>; |
| 679 | def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; |
| 680 | def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; |
| 681 | def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; |
| 682 | def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 683 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 684 | def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; |
| 685 | def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; |
| 686 | def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; |
Chris Lattner | 41efbfa | 2010-10-05 06:37:31 +0000 | [diff] [blame] | 687 | def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; |
| 688 | def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; |
| 689 | def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 690 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 691 | def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; |
| 692 | def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; |
| 693 | def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; |
| 694 | def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; |
| 695 | def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; |
| 696 | def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; |
Chris Lattner | 41efbfa | 2010-10-05 06:37:31 +0000 | [diff] [blame] | 697 | def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; |
| 698 | def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; |
| 699 | def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; |
| 700 | def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; |
Evan Cheng | 7a7e837 | 2005-12-14 02:22:27 +0000 | [diff] [blame] | 701 | |
Evan Cheng | 466685d | 2006-10-09 20:57:25 +0000 | [diff] [blame] | 702 | def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; |
| 703 | def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; |
| 704 | def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; |
| 705 | def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; |
| 706 | def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; |
| 707 | def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; |
Chris Lattner | 41efbfa | 2010-10-05 06:37:31 +0000 | [diff] [blame] | 708 | def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; |
| 709 | def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; |
| 710 | def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; |
| 711 | def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; |
Evan Cheng | 747a90d | 2006-02-21 02:24:38 +0000 | [diff] [blame] | 712 | |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 713 | |
| 714 | // An 'and' node with a single use. |
| 715 | def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ |
Evan Cheng | 07b7ea1 | 2008-03-04 00:40:35 +0000 | [diff] [blame] | 716 | return N->hasOneUse(); |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 717 | }]>; |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 718 | // An 'srl' node with a single use. |
| 719 | def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{ |
| 720 | return N->hasOneUse(); |
| 721 | }]>; |
| 722 | // An 'trunc' node with a single use. |
| 723 | def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ |
| 724 | return N->hasOneUse(); |
| 725 | }]>; |
Chris Lattner | ce2bcc8 | 2008-02-19 17:37:35 +0000 | [diff] [blame] | 726 | |
Chris Lattner | f124d5e | 2005-11-18 01:04:42 +0000 | [diff] [blame] | 727 | //===----------------------------------------------------------------------===// |
Chris Lattner | 434c7cb | 2010-10-05 05:32:15 +0000 | [diff] [blame] | 728 | // Instruction list. |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 729 | // |
| 730 | |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 731 | // Nop |
Sean Callanan | 74e5210 | 2009-07-23 23:39:34 +0000 | [diff] [blame] | 732 | let neverHasSideEffects = 1 in { |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 733 | def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 734 | def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 735 | "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize; |
Sean Callanan | 74e5210 | 2009-07-23 23:39:34 +0000 | [diff] [blame] | 736 | def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 737 | "nop{l}\t$zero", [], IIC_NOP>, TB; |
Sean Callanan | 74e5210 | 2009-07-23 23:39:34 +0000 | [diff] [blame] | 738 | } |
Evan Cheng | 4a46080 | 2006-01-11 00:33:36 +0000 | [diff] [blame] | 739 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 740 | |
Sean Callanan | 8d70854 | 2009-09-16 02:57:13 +0000 | [diff] [blame] | 741 | // Constructing a stack frame. |
Chris Lattner | 40cc3f8 | 2010-09-17 18:02:29 +0000 | [diff] [blame] | 742 | def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 743 | "enter\t$len, $lvl", [], IIC_ENTER>; |
Sean Callanan | 8d70854 | 2009-09-16 02:57:13 +0000 | [diff] [blame] | 744 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 745 | let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, neverHasSideEffects=1 in |
Chris Lattner | 30bf2d8 | 2004-08-10 20:17:41 +0000 | [diff] [blame] | 746 | def LEAVE : I<0xC9, RawFrm, |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 747 | (outs), (ins), "leave", [], IIC_LEAVE>, |
| 748 | Requires<[In32BitMode]>; |
Evan Cheng | 071a279 | 2007-09-11 19:55:27 +0000 | [diff] [blame] | 749 | |
Chris Lattner | 5673e1d | 2010-10-05 06:41:40 +0000 | [diff] [blame] | 750 | let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, neverHasSideEffects = 1 in |
| 751 | def LEAVE64 : I<0xC9, RawFrm, |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 752 | (outs), (ins), "leave", [], IIC_LEAVE>, |
| 753 | Requires<[In64BitMode]>; |
Chris Lattner | 5673e1d | 2010-10-05 06:41:40 +0000 | [diff] [blame] | 754 | |
Chris Lattner | 87be16a | 2010-10-05 06:04:14 +0000 | [diff] [blame] | 755 | //===----------------------------------------------------------------------===// |
Chris Lattner | 5673e1d | 2010-10-05 06:41:40 +0000 | [diff] [blame] | 756 | // Miscellaneous Instructions. |
Chris Lattner | 87be16a | 2010-10-05 06:04:14 +0000 | [diff] [blame] | 757 | // |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 758 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 759 | let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in { |
Sean Callanan | 1f24e01 | 2009-09-10 18:29:13 +0000 | [diff] [blame] | 760 | let mayLoad = 1 in { |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 761 | def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [], |
| 762 | IIC_POP_REG16>, OpSize; |
| 763 | def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [], |
| 764 | IIC_POP_REG>; |
| 765 | def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [], |
| 766 | IIC_POP_REG>, OpSize; |
| 767 | def POP16rmm: I<0x8F, MRM0m, (outs i16mem:$dst), (ins), "pop{w}\t$dst", [], |
| 768 | IIC_POP_MEM>, OpSize; |
| 769 | def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [], |
| 770 | IIC_POP_REG>; |
| 771 | def POP32rmm: I<0x8F, MRM0m, (outs i32mem:$dst), (ins), "pop{l}\t$dst", [], |
| 772 | IIC_POP_MEM>; |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 773 | |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 774 | def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, OpSize; |
| 775 | def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>, |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 776 | Requires<[In32BitMode]>; |
Sean Callanan | 1f24e01 | 2009-09-10 18:29:13 +0000 | [diff] [blame] | 777 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 778 | |
Sean Callanan | 1f24e01 | 2009-09-10 18:29:13 +0000 | [diff] [blame] | 779 | let mayStore = 1 in { |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 780 | def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[], |
| 781 | IIC_PUSH_REG>, OpSize; |
| 782 | def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[], |
| 783 | IIC_PUSH_REG>; |
| 784 | def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[], |
| 785 | IIC_PUSH_REG>, OpSize; |
| 786 | def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[], |
| 787 | IIC_PUSH_MEM>, |
Sean Callanan | 1f24e01 | 2009-09-10 18:29:13 +0000 | [diff] [blame] | 788 | OpSize; |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 789 | def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[], |
| 790 | IIC_PUSH_REG>; |
| 791 | def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[], |
| 792 | IIC_PUSH_MEM>; |
Anton Korobeynikov | 57fc00d | 2007-04-17 09:20:00 +0000 | [diff] [blame] | 793 | |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 794 | def PUSHi8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 795 | "push{l}\t$imm", [], IIC_PUSH_IMM>; |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 796 | def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 797 | "push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize; |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 798 | def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 799 | "push{l}\t$imm", [], IIC_PUSH_IMM>; |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 800 | |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 801 | def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>, |
| 802 | OpSize; |
| 803 | def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>, |
Dan Gohman | e5e4ff9 | 2010-05-20 16:16:00 +0000 | [diff] [blame] | 804 | Requires<[In32BitMode]>; |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 805 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 806 | } |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 807 | } |
| 808 | |
| 809 | let Defs = [RSP], Uses = [RSP], neverHasSideEffects=1 in { |
| 810 | let mayLoad = 1 in { |
| 811 | def POP64r : I<0x58, AddRegFrm, |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 812 | (outs GR64:$reg), (ins), "pop{q}\t$reg", [], IIC_POP_REG>; |
| 813 | def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", [], |
| 814 | IIC_POP_REG>; |
| 815 | def POP64rmm: I<0x8F, MRM0m, (outs i64mem:$dst), (ins), "pop{q}\t$dst", [], |
| 816 | IIC_POP_MEM>; |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 817 | } |
| 818 | let mayStore = 1 in { |
| 819 | def PUSH64r : I<0x50, AddRegFrm, |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 820 | (outs), (ins GR64:$reg), "push{q}\t$reg", [], IIC_PUSH_REG>; |
| 821 | def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", [], |
| 822 | IIC_PUSH_REG>; |
| 823 | def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", [], |
| 824 | IIC_PUSH_MEM>; |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 825 | } |
| 826 | } |
| 827 | |
| 828 | let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1 in { |
Kevin Enderby | d521f2d | 2011-07-06 17:23:46 +0000 | [diff] [blame] | 829 | def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 830 | "push{q}\t$imm", [], IIC_PUSH_IMM>; |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 831 | def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 832 | "push{q}\t$imm", [], IIC_PUSH_IMM>; |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 833 | def PUSH64i32 : Ii32<0x68, RawFrm, (outs), (ins i64i32imm:$imm), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 834 | "push{q}\t$imm", [], IIC_PUSH_IMM>; |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 835 | } |
| 836 | |
| 837 | let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, neverHasSideEffects=1 in |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 838 | def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", [], IIC_POP_FD>, |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 839 | Requires<[In64BitMode]>; |
| 840 | let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, neverHasSideEffects=1 in |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 841 | def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>, |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 842 | Requires<[In64BitMode]>; |
| 843 | |
| 844 | |
Evan Cheng | 2f245ba | 2007-09-26 01:29:06 +0000 | [diff] [blame] | 845 | |
Nico Weber | 50b9efc | 2010-06-23 20:00:58 +0000 | [diff] [blame] | 846 | let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], |
| 847 | mayLoad=1, neverHasSideEffects=1 in { |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 848 | def POPA32 : I<0x61, RawFrm, (outs), (ins), "popa{l}", [], IIC_POP_A>, |
Nico Weber | 50b9efc | 2010-06-23 20:00:58 +0000 | [diff] [blame] | 849 | Requires<[In32BitMode]>; |
| 850 | } |
| 851 | let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], |
| 852 | mayStore=1, neverHasSideEffects=1 in { |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 853 | def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pusha{l}", [], IIC_PUSH_A>, |
Nico Weber | 50b9efc | 2010-06-23 20:00:58 +0000 | [diff] [blame] | 854 | Requires<[In32BitMode]>; |
| 855 | } |
| 856 | |
Chris Lattner | 8917cd3 | 2010-10-05 06:52:26 +0000 | [diff] [blame] | 857 | let Constraints = "$src = $dst" in { // GR32 = bswap GR32 |
| 858 | def BSWAP32r : I<0xC8, AddRegFrm, |
| 859 | (outs GR32:$dst), (ins GR32:$src), |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 860 | "bswap{l}\t$dst", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 861 | [(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, TB; |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 862 | |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 863 | def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 864 | "bswap{q}\t$dst", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 865 | [(set GR64:$dst, (bswap GR64:$src))], IIC_BSWAP>, TB; |
Chris Lattner | 8917cd3 | 2010-10-05 06:52:26 +0000 | [diff] [blame] | 866 | } // Constraints = "$src = $dst" |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 867 | |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 868 | // Bit scan instructions. |
| 869 | let Defs = [EFLAGS] in { |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 870 | def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 871 | "bsf{w}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 872 | [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))], |
| 873 | IIC_BSF>, TB, OpSize; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 874 | def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 875 | "bsf{w}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 876 | [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))], |
| 877 | IIC_BSF>, TB, OpSize; |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 878 | def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 879 | "bsf{l}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 880 | [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))], IIC_BSF>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 881 | def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 882 | "bsf{l}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 883 | [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))], |
| 884 | IIC_BSF>, TB; |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 885 | def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), |
| 886 | "bsf{q}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 887 | [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))], |
| 888 | IIC_BSF>, TB; |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 889 | def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), |
| 890 | "bsf{q}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 891 | [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))], |
| 892 | IIC_BSF>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 893 | |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 894 | def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 895 | "bsr{w}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 896 | [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))], IIC_BSR>, |
| 897 | TB, OpSize; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 898 | def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 899 | "bsr{w}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 900 | [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))], |
| 901 | IIC_BSR>, TB, |
Kevin Enderby | 9ac7282 | 2010-04-28 23:20:40 +0000 | [diff] [blame] | 902 | OpSize; |
Evan Cheng | fd9e473 | 2007-12-14 18:49:43 +0000 | [diff] [blame] | 903 | def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 904 | "bsr{l}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 905 | [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))], IIC_BSR>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 906 | def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
Dan Gohman | 1a8001e | 2007-12-14 15:10:00 +0000 | [diff] [blame] | 907 | "bsr{l}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 908 | [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))], |
| 909 | IIC_BSR>, TB; |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 910 | def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), |
| 911 | "bsr{q}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 912 | [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], IIC_BSR>, TB; |
Chris Lattner | d8cc272 | 2010-10-05 06:47:35 +0000 | [diff] [blame] | 913 | def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), |
| 914 | "bsr{q}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 915 | [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))], |
| 916 | IIC_BSR>, TB; |
Evan Cheng | 18efe26 | 2007-12-14 02:13:44 +0000 | [diff] [blame] | 917 | } // Defs = [EFLAGS] |
| 918 | |
Chris Lattner | 915e5e5 | 2004-02-12 17:53:22 +0000 | [diff] [blame] | 919 | |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 920 | // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI |
| 921 | let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in { |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 922 | def MOVSB : I<0xA4, RawFrm, (outs), (ins), "movsb", [], IIC_MOVS>; |
| 923 | def MOVSW : I<0xA5, RawFrm, (outs), (ins), "movsw", [], IIC_MOVS>, OpSize; |
| 924 | def MOVSD : I<0xA5, RawFrm, (outs), (ins), "movs{l|d}", [], IIC_MOVS>; |
| 925 | def MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "movsq", [], IIC_MOVS>; |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 926 | } |
| 927 | |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 928 | // These uses the DF flag in the EFLAGS register to inc or dec EDI and ESI |
| 929 | let Defs = [EDI], Uses = [AL,EDI,EFLAGS] in |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 930 | def STOSB : I<0xAA, RawFrm, (outs), (ins), "stosb", [], IIC_STOS>; |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 931 | let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 932 | def STOSW : I<0xAB, RawFrm, (outs), (ins), "stosw", [], IIC_STOS>, OpSize; |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 933 | let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 934 | def STOSD : I<0xAB, RawFrm, (outs), (ins), "stos{l|d}", [], IIC_STOS>; |
Chris Lattner | d3f033d | 2010-10-05 06:27:48 +0000 | [diff] [blame] | 935 | let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 936 | def STOSQ : RI<0xAB, RawFrm, (outs), (ins), "stosq", [], IIC_STOS>; |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 937 | |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 938 | def SCAS8 : I<0xAE, RawFrm, (outs), (ins), "scasb", [], IIC_SCAS>; |
| 939 | def SCAS16 : I<0xAF, RawFrm, (outs), (ins), "scasw", [], IIC_SCAS>, OpSize; |
| 940 | def SCAS32 : I<0xAF, RawFrm, (outs), (ins), "scas{l|d}", [], IIC_SCAS>; |
| 941 | def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", [], IIC_SCAS>; |
Sean Callanan | a82e465 | 2009-09-12 00:37:19 +0000 | [diff] [blame] | 942 | |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 943 | def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmpsb", [], IIC_CMPS>; |
| 944 | def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmpsw", [], IIC_CMPS>, OpSize; |
| 945 | def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l|d}", [], IIC_CMPS>; |
| 946 | def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", [], IIC_CMPS>; |
Sean Callanan | 6f8f462 | 2009-09-12 02:25:20 +0000 | [diff] [blame] | 947 | |
Chris Lattner | 02552de | 2009-08-11 16:58:39 +0000 | [diff] [blame] | 948 | |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 949 | //===----------------------------------------------------------------------===// |
Chris Lattner | 434c7cb | 2010-10-05 05:32:15 +0000 | [diff] [blame] | 950 | // Move Instructions. |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 951 | // |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 952 | |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 953 | let neverHasSideEffects = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 954 | def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 955 | "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 956 | def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 957 | "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 958 | def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 959 | "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 960 | def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 961 | "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 962 | } |
Evan Cheng | 359e937 | 2008-06-18 08:13:07 +0000 | [diff] [blame] | 963 | let isReMaterializable = 1, isAsCheapAsAMove = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 964 | def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 965 | "mov{b}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 966 | [(set GR8:$dst, imm:$src)], IIC_MOV>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 967 | def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 968 | "mov{w}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 969 | [(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 970 | def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 971 | "mov{l}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 972 | [(set GR32:$dst, imm:$src)], IIC_MOV>; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 973 | def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src), |
| 974 | "movabs{q}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 975 | [(set GR64:$dst, imm:$src)], IIC_MOV>; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 976 | def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), |
| 977 | "mov{q}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 978 | [(set GR64:$dst, i64immSExt32:$src)], IIC_MOV>; |
Dan Gohman | d45eddd | 2007-06-26 00:48:07 +0000 | [diff] [blame] | 979 | } |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 980 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 981 | def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 982 | "mov{b}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 983 | [(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 984 | def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 985 | "mov{w}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 986 | [(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 987 | def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 988 | "mov{l}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 989 | [(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 990 | def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), |
| 991 | "mov{q}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 992 | [(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>; |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 993 | |
Chris Lattner | b5505d0 | 2010-05-13 00:02:47 +0000 | [diff] [blame] | 994 | /// moffs8, moffs16 and moffs32 versions of moves. The immediate is a |
| 995 | /// 32-bit offset from the PC. These are only valid in x86-32 mode. |
Chris Lattner | 2745f6e | 2010-05-12 22:48:24 +0000 | [diff] [blame] | 996 | def MOV8o8a : Ii32 <0xA0, RawFrm, (outs), (ins offset8:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 997 | "mov{b}\t{$src, %al|AL, $src}", [], IIC_MOV_MEM>, |
Daniel Dunbar | 6c2c9a2 | 2010-07-19 06:14:44 +0000 | [diff] [blame] | 998 | Requires<[In32BitMode]>; |
Chris Lattner | 2745f6e | 2010-05-12 22:48:24 +0000 | [diff] [blame] | 999 | def MOV16o16a : Ii32 <0xA1, RawFrm, (outs), (ins offset16:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1000 | "mov{w}\t{$src, %ax|AL, $src}", [], IIC_MOV_MEM>, OpSize, |
Daniel Dunbar | 6c2c9a2 | 2010-07-19 06:14:44 +0000 | [diff] [blame] | 1001 | Requires<[In32BitMode]>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1002 | def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1003 | "mov{l}\t{$src, %eax|EAX, $src}", [], IIC_MOV_MEM>, |
Daniel Dunbar | 6c2c9a2 | 2010-07-19 06:14:44 +0000 | [diff] [blame] | 1004 | Requires<[In32BitMode]>; |
Chris Lattner | 2745f6e | 2010-05-12 22:48:24 +0000 | [diff] [blame] | 1005 | def MOV8ao8 : Ii32 <0xA2, RawFrm, (outs offset8:$dst), (ins), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1006 | "mov{b}\t{%al, $dst|$dst, AL}", [], IIC_MOV_MEM>, |
Daniel Dunbar | 6c2c9a2 | 2010-07-19 06:14:44 +0000 | [diff] [blame] | 1007 | Requires<[In32BitMode]>; |
Chris Lattner | 2745f6e | 2010-05-12 22:48:24 +0000 | [diff] [blame] | 1008 | def MOV16ao16 : Ii32 <0xA3, RawFrm, (outs offset16:$dst), (ins), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1009 | "mov{w}\t{%ax, $dst|$dst, AL}", [], IIC_MOV_MEM>, OpSize, |
Daniel Dunbar | 6c2c9a2 | 2010-07-19 06:14:44 +0000 | [diff] [blame] | 1010 | Requires<[In32BitMode]>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1011 | def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1012 | "mov{l}\t{%eax, $dst|$dst, EAX}", [], IIC_MOV_MEM>, |
Daniel Dunbar | 6c2c9a2 | 2010-07-19 06:14:44 +0000 | [diff] [blame] | 1013 | Requires<[In32BitMode]>; |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 1014 | |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1015 | // FIXME: These definitions are utterly broken |
| 1016 | // Just leave them commented out for now because they're useless outside |
| 1017 | // of the large code model, and most compilers won't generate the instructions |
| 1018 | // in question. |
| 1019 | /* |
| 1020 | def MOV64o8a : RIi8<0xA0, RawFrm, (outs), (ins offset8:$src), |
Craig Topper | 82f131a | 2011-10-02 21:08:12 +0000 | [diff] [blame] | 1021 | "mov{q}\t{$src, %rax|RAX, $src}", []>; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1022 | def MOV64o64a : RIi32<0xA1, RawFrm, (outs), (ins offset64:$src), |
Craig Topper | 82f131a | 2011-10-02 21:08:12 +0000 | [diff] [blame] | 1023 | "mov{q}\t{$src, %rax|RAX, $src}", []>; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1024 | def MOV64ao8 : RIi8<0xA2, RawFrm, (outs offset8:$dst), (ins), |
Craig Topper | 82f131a | 2011-10-02 21:08:12 +0000 | [diff] [blame] | 1025 | "mov{q}\t{%rax, $dst|$dst, RAX}", []>; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1026 | def MOV64ao64 : RIi32<0xA3, RawFrm, (outs offset64:$dst), (ins), |
Craig Topper | 82f131a | 2011-10-02 21:08:12 +0000 | [diff] [blame] | 1027 | "mov{q}\t{%rax, $dst|$dst, RAX}", []>; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1028 | */ |
| 1029 | |
Sean Callanan | 38fee0e | 2009-09-15 18:47:29 +0000 | [diff] [blame] | 1030 | |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 1031 | let isCodeGenOnly = 1 in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1032 | def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1033 | "mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1034 | def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1035 | "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1036 | def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1037 | "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1038 | def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1039 | "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>; |
Daniel Dunbar | dcbab9c | 2010-05-26 22:21:28 +0000 | [diff] [blame] | 1040 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1041 | |
Dan Gohman | bc9d98b | 2010-02-27 23:47:46 +0000 | [diff] [blame] | 1042 | let canFoldAsLoad = 1, isReMaterializable = 1 in { |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1043 | def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1044 | "mov{b}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1045 | [(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1046 | def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1047 | "mov{w}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1048 | [(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1049 | def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1050 | "mov{l}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1051 | [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1052 | def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), |
| 1053 | "mov{q}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1054 | [(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>; |
Evan Cheng | 2f39426 | 2007-08-30 05:49:43 +0000 | [diff] [blame] | 1055 | } |
Chris Lattner | 1cca5e3 | 2003-08-03 21:54:21 +0000 | [diff] [blame] | 1056 | |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1057 | def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1058 | "mov{b}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1059 | [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1060 | def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1061 | "mov{w}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1062 | [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize; |
Evan Cheng | 64d80e3 | 2007-07-19 01:14:50 +0000 | [diff] [blame] | 1063 | def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), |
Dan Gohman | b1576f5 | 2007-07-31 20:11:57 +0000 | [diff] [blame] | 1064 | "mov{l}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1065 | [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1066 | def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), |
| 1067 | "mov{q}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1068 | [(store GR64:$src, addr:$dst)], IIC_MOV_MEM>; |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 1069 | |
Dan Gohman | 4af325d | 2009-04-27 16:41:36 +0000 | [diff] [blame] | 1070 | // Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so |
| 1071 | // that they can be used for copying and storing h registers, which can't be |
| 1072 | // encoded when a REX prefix is present. |
Daniel Dunbar | cf246b7 | 2010-07-19 06:14:49 +0000 | [diff] [blame] | 1073 | let isCodeGenOnly = 1 in { |
Dan Gohman | 6d9305c | 2009-04-15 00:04:23 +0000 | [diff] [blame] | 1074 | let neverHasSideEffects = 1 in |
Dan Gohman | df7dfc7 | 2009-04-15 19:48:57 +0000 | [diff] [blame] | 1075 | def MOV8rr_NOREX : I<0x88, MRMDestReg, |
| 1076 | (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1077 | "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], IIC_MOV>; |
Evan Cheng | 8c14740 | 2009-04-30 00:58:57 +0000 | [diff] [blame] | 1078 | let mayStore = 1 in |
Dan Gohman | 6d9305c | 2009-04-15 00:04:23 +0000 | [diff] [blame] | 1079 | def MOV8mr_NOREX : I<0x88, MRMDestMem, |
| 1080 | (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1081 | "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], |
| 1082 | IIC_MOV_MEM>; |
Jakob Stoklund Olesen | ccbe603 | 2011-10-14 01:00:49 +0000 | [diff] [blame] | 1083 | let mayLoad = 1, neverHasSideEffects = 1, |
Dan Gohman | bc9d98b | 2010-02-27 23:47:46 +0000 | [diff] [blame] | 1084 | canFoldAsLoad = 1, isReMaterializable = 1 in |
Dan Gohman | 4af325d | 2009-04-27 16:41:36 +0000 | [diff] [blame] | 1085 | def MOV8rm_NOREX : I<0x8A, MRMSrcMem, |
| 1086 | (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1087 | "mov{b}\t{$src, $dst|$dst, $src} # NOREX", [], |
| 1088 | IIC_MOV_MEM>; |
Daniel Dunbar | cf246b7 | 2010-07-19 06:14:49 +0000 | [diff] [blame] | 1089 | } |
Dan Gohman | 21e3dfb | 2009-04-13 16:09:41 +0000 | [diff] [blame] | 1090 | |
Evan Cheng | 0488db9 | 2007-09-25 01:57:46 +0000 | [diff] [blame] | 1091 | |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1092 | // Condition code ops, incl. set if equal/not equal/... |
Benjamin Kramer | 17c836c | 2012-04-27 12:07:43 +0000 | [diff] [blame] | 1093 | let Defs = [EFLAGS], Uses = [AH] in |
| 1094 | def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1095 | [(set EFLAGS, (X86sahf AH))], IIC_AHF>; |
Chris Lattner | ba7e756 | 2008-01-10 07:59:24 +0000 | [diff] [blame] | 1096 | let Defs = [AH], Uses = [EFLAGS], neverHasSideEffects = 1 in |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1097 | def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [], |
| 1098 | IIC_AHF>; // AH = flags |
Alkis Evlogimenos | 5ab29b5 | 2004-02-28 22:02:05 +0000 | [diff] [blame] | 1099 | |
Sean Callanan | a09caa5 | 2009-09-02 00:55:49 +0000 | [diff] [blame] | 1100 | |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1101 | //===----------------------------------------------------------------------===// |
| 1102 | // Bit tests instructions: BT, BTS, BTR, BTC. |
Daniel Dunbar | 1e8ee89 | 2010-03-09 22:50:40 +0000 | [diff] [blame] | 1103 | |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 1104 | let Defs = [EFLAGS] in { |
Dan Gohman | 0c89b7e | 2009-01-13 20:32:45 +0000 | [diff] [blame] | 1105 | def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 1106 | "bt{w}\t{$src2, $src1|$src1, $src2}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1107 | [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>, |
| 1108 | OpSize, TB; |
Dan Gohman | 0c89b7e | 2009-01-13 20:32:45 +0000 | [diff] [blame] | 1109 | def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 1110 | "bt{l}\t{$src2, $src1|$src1, $src2}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1111 | [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>, TB; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1112 | def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), |
| 1113 | "bt{q}\t{$src2, $src1|$src1, $src2}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1114 | [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB; |
Dan Gohman | f31408d | 2009-01-13 23:23:30 +0000 | [diff] [blame] | 1115 | |
| 1116 | // Unlike with the register+register form, the memory+register form of the |
| 1117 | // bt instruction does not ignore the high bits of the index. From ISel's |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1118 | // perspective, this is pretty bizarre. Make these instructions disassembly |
| 1119 | // only for now. |
| 1120 | |
| 1121 | def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 1122 | "bt{w}\t{$src2, $src1|$src1, $src2}", |
Dan Gohman | f31408d | 2009-01-13 23:23:30 +0000 | [diff] [blame] | 1123 | // [(X86bt (loadi16 addr:$src1), GR16:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1124 | // (implicit EFLAGS)] |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1125 | [], IIC_BT_MR |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1126 | >, OpSize, TB, Requires<[FastBTMem]>; |
| 1127 | def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 1128 | "bt{l}\t{$src2, $src1|$src1, $src2}", |
Dan Gohman | f31408d | 2009-01-13 23:23:30 +0000 | [diff] [blame] | 1129 | // [(X86bt (loadi32 addr:$src1), GR32:$src2), |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1130 | // (implicit EFLAGS)] |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1131 | [], IIC_BT_MR |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1132 | >, TB, Requires<[FastBTMem]>; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1133 | def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), |
| 1134 | "bt{q}\t{$src2, $src1|$src1, $src2}", |
| 1135 | // [(X86bt (loadi64 addr:$src1), GR64:$src2), |
| 1136 | // (implicit EFLAGS)] |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1137 | [], IIC_BT_MR |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1138 | >, TB; |
Dan Gohman | 4afe15b | 2009-01-13 20:33:23 +0000 | [diff] [blame] | 1139 | |
| 1140 | def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2), |
| 1141 | "bt{w}\t{$src2, $src1|$src1, $src2}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1142 | [(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))], |
| 1143 | IIC_BT_RI>, OpSize, TB; |
Dan Gohman | 4afe15b | 2009-01-13 20:33:23 +0000 | [diff] [blame] | 1144 | def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2), |
| 1145 | "bt{l}\t{$src2, $src1|$src1, $src2}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1146 | [(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))], |
| 1147 | IIC_BT_RI>, TB; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1148 | def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2), |
| 1149 | "bt{q}\t{$src2, $src1|$src1, $src2}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1150 | [(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))], |
| 1151 | IIC_BT_RI>, TB; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1152 | |
Dan Gohman | 4afe15b | 2009-01-13 20:33:23 +0000 | [diff] [blame] | 1153 | // Note that these instructions don't need FastBTMem because that |
| 1154 | // only applies when the other operand is in a register. When it's |
| 1155 | // an immediate, bt is still fast. |
| 1156 | def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2), |
| 1157 | "bt{w}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 1158 | [(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2)) |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1159 | ], IIC_BT_MI>, OpSize, TB; |
Dan Gohman | 4afe15b | 2009-01-13 20:33:23 +0000 | [diff] [blame] | 1160 | def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2), |
| 1161 | "bt{l}\t{$src2, $src1|$src1, $src2}", |
Chris Lattner | e3486a4 | 2010-03-19 00:01:11 +0000 | [diff] [blame] | 1162 | [(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2)) |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1163 | ], IIC_BT_MI>, TB; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1164 | def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2), |
| 1165 | "bt{q}\t{$src2, $src1|$src1, $src2}", |
| 1166 | [(set EFLAGS, (X86bt (loadi64 addr:$src1), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1167 | i64immSExt8:$src2))], IIC_BT_MI>, TB; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1168 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1169 | |
| 1170 | def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1171 | "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, |
| 1172 | OpSize, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1173 | def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1174 | "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1175 | def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1176 | "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1177 | def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1178 | "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, |
| 1179 | OpSize, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1180 | def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1181 | "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1182 | def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1183 | "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1184 | def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1185 | "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, |
| 1186 | OpSize, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1187 | def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1188 | "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1189 | def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1190 | "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1191 | def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1192 | "btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, |
| 1193 | OpSize, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1194 | def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1195 | "btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1196 | def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1197 | "btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1198 | |
| 1199 | def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1200 | "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, |
| 1201 | OpSize, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1202 | def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1203 | "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1204 | def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), |
| 1205 | "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1206 | def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1207 | "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, |
| 1208 | OpSize, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1209 | def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1210 | "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1211 | def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1212 | "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1213 | def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1214 | "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, |
| 1215 | OpSize, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1216 | def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1217 | "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1218 | def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1219 | "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1220 | def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1221 | "btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, |
| 1222 | OpSize, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1223 | def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1224 | "btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1225 | def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1226 | "btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1227 | |
| 1228 | def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1229 | "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, |
| 1230 | OpSize, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1231 | def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1232 | "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1233 | def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1234 | "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1235 | def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1236 | "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, |
| 1237 | OpSize, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1238 | def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1239 | "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1240 | def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1241 | "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1242 | def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1243 | "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, |
| 1244 | OpSize, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1245 | def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1246 | "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1247 | def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1248 | "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1249 | def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1250 | "bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, |
| 1251 | OpSize, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1252 | def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1253 | "bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; |
Chris Lattner | 748a2fe | 2010-10-05 20:49:15 +0000 | [diff] [blame] | 1254 | def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1255 | "bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB; |
Dan Gohman | c7a37d4 | 2008-12-23 22:45:23 +0000 | [diff] [blame] | 1256 | } // Defs = [EFLAGS] |
| 1257 | |
Anton Korobeynikov | 2365f51 | 2007-07-14 14:06:15 +0000 | [diff] [blame] | 1258 | |
| 1259 | //===----------------------------------------------------------------------===// |
Andrew Lenharth | ab0b949 | 2008-02-21 06:45:13 +0000 | [diff] [blame] | 1260 | // Atomic support |
| 1261 | // |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 1262 | |
Eric Christopher | 9a9d275 | 2010-07-22 02:48:34 +0000 | [diff] [blame] | 1263 | |
Evan Cheng | bb6939d | 2008-04-19 01:20:30 +0000 | [diff] [blame] | 1264 | // Atomic swap. These are just normal xchg instructions. But since a memory |
| 1265 | // operand is referenced, the atomicity is ensured. |
Dan Gohman | 165660e | 2008-08-06 15:52:50 +0000 | [diff] [blame] | 1266 | let Constraints = "$val = $dst" in { |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 1267 | def XCHG8rm : I<0x86, MRMSrcMem, (outs GR8:$dst), (ins GR8:$val, i8mem:$ptr), |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 1268 | "xchg{b}\t{$val, $ptr|$ptr, $val}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1269 | [(set GR8:$dst, (atomic_swap_8 addr:$ptr, GR8:$val))], |
| 1270 | IIC_XCHG_MEM>; |
Chris Lattner | 5bde734 | 2010-11-06 08:20:59 +0000 | [diff] [blame] | 1271 | def XCHG16rm : I<0x87, MRMSrcMem, (outs GR16:$dst),(ins GR16:$val, i16mem:$ptr), |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 1272 | "xchg{w}\t{$val, $ptr|$ptr, $val}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1273 | [(set GR16:$dst, (atomic_swap_16 addr:$ptr, GR16:$val))], |
| 1274 | IIC_XCHG_MEM>, |
Evan Cheng | bb6939d | 2008-04-19 01:20:30 +0000 | [diff] [blame] | 1275 | OpSize; |
Chris Lattner | 5bde734 | 2010-11-06 08:20:59 +0000 | [diff] [blame] | 1276 | def XCHG32rm : I<0x87, MRMSrcMem, (outs GR32:$dst),(ins GR32:$val, i32mem:$ptr), |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 1277 | "xchg{l}\t{$val, $ptr|$ptr, $val}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1278 | [(set GR32:$dst, (atomic_swap_32 addr:$ptr, GR32:$val))], |
| 1279 | IIC_XCHG_MEM>; |
Chris Lattner | 5bde734 | 2010-11-06 08:20:59 +0000 | [diff] [blame] | 1280 | def XCHG64rm : RI<0x87, MRMSrcMem, (outs GR64:$dst),(ins GR64:$val,i64mem:$ptr), |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 1281 | "xchg{q}\t{$val, $ptr|$ptr, $val}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1282 | [(set GR64:$dst, (atomic_swap_64 addr:$ptr, GR64:$val))], |
| 1283 | IIC_XCHG_MEM>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1284 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1285 | def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1286 | "xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 1287 | def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1288 | "xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, OpSize; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 1289 | def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1290 | "xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 1291 | def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1292 | "xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>; |
Evan Cheng | bb6939d | 2008-04-19 01:20:30 +0000 | [diff] [blame] | 1293 | } |
| 1294 | |
Craig Topper | 25f6dfd | 2011-10-07 05:35:38 +0000 | [diff] [blame] | 1295 | def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1296 | "xchg{w}\t{$src, %ax|AX, $src}", [], IIC_XCHG_REG>, OpSize; |
Craig Topper | 25f6dfd | 2011-10-07 05:35:38 +0000 | [diff] [blame] | 1297 | def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1298 | "xchg{l}\t{$src, %eax|EAX, $src}", [], IIC_XCHG_REG>, |
| 1299 | Requires<[In32BitMode]>; |
Craig Topper | 25f6dfd | 2011-10-07 05:35:38 +0000 | [diff] [blame] | 1300 | // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding. |
| 1301 | // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP. |
| 1302 | def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1303 | "xchg{l}\t{$src, %eax|EAX, $src}", [], IIC_XCHG_REG>, |
| 1304 | Requires<[In64BitMode]>; |
Craig Topper | 25f6dfd | 2011-10-07 05:35:38 +0000 | [diff] [blame] | 1305 | def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1306 | "xchg{q}\t{$src, %rax|RAX, $src}", [], IIC_XCHG_REG>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1307 | |
Andrew Lenharth | 26ed869 | 2008-03-01 21:52:34 +0000 | [diff] [blame] | 1308 | |
Andrew Lenharth | ea7da50 | 2008-03-01 13:37:02 +0000 | [diff] [blame] | 1309 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1310 | def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1311 | "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1312 | def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1313 | "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB, |
| 1314 | OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1315 | def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1316 | "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 1317 | def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1318 | "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1319 | |
Dan Gohman | 7f357ec | 2010-05-14 16:34:55 +0000 | [diff] [blame] | 1320 | let mayLoad = 1, mayStore = 1 in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1321 | def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1322 | "xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1323 | def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1324 | "xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB, |
| 1325 | OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1326 | def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1327 | "xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 1328 | def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1329 | "xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 1330 | |
Dan Gohman | 7f357ec | 2010-05-14 16:34:55 +0000 | [diff] [blame] | 1331 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1332 | |
| 1333 | def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1334 | "cmpxchg{b}\t{$src, $dst|$dst, $src}", [], |
| 1335 | IIC_CMPXCHG_REG8>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1336 | def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1337 | "cmpxchg{w}\t{$src, $dst|$dst, $src}", [], |
| 1338 | IIC_CMPXCHG_REG>, TB, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1339 | def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1340 | "cmpxchg{l}\t{$src, $dst|$dst, $src}", [], |
| 1341 | IIC_CMPXCHG_REG>, TB; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 1342 | def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1343 | "cmpxchg{q}\t{$src, $dst|$dst, $src}", [], |
| 1344 | IIC_CMPXCHG_REG>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1345 | |
Dan Gohman | 7f357ec | 2010-05-14 16:34:55 +0000 | [diff] [blame] | 1346 | let mayLoad = 1, mayStore = 1 in { |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1347 | def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1348 | "cmpxchg{b}\t{$src, $dst|$dst, $src}", [], |
| 1349 | IIC_CMPXCHG_MEM8>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1350 | def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1351 | "cmpxchg{w}\t{$src, $dst|$dst, $src}", [], |
| 1352 | IIC_CMPXCHG_MEM>, TB, OpSize; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1353 | def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1354 | "cmpxchg{l}\t{$src, $dst|$dst, $src}", [], |
| 1355 | IIC_CMPXCHG_MEM>, TB; |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 1356 | def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1357 | "cmpxchg{q}\t{$src, $dst|$dst, $src}", [], |
| 1358 | IIC_CMPXCHG_MEM>, TB; |
Dan Gohman | 7f357ec | 2010-05-14 16:34:55 +0000 | [diff] [blame] | 1359 | } |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1360 | |
Evan Cheng | b093bd0 | 2010-01-08 01:29:19 +0000 | [diff] [blame] | 1361 | let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1362 | def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1363 | "cmpxchg8b\t$dst", [], IIC_CMPXCHG_8B>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1364 | |
Chris Lattner | 010496c | 2010-10-05 06:22:35 +0000 | [diff] [blame] | 1365 | let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in |
| 1366 | def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1367 | "cmpxchg16b\t$dst", [], IIC_CMPXCHG_16B>, |
| 1368 | TB, Requires<[HasCmpxchg16b]>; |
Evan Cheng | 37b7387 | 2009-07-30 08:33:02 +0000 | [diff] [blame] | 1369 | |
Evan Cheng | 37b7387 | 2009-07-30 08:33:02 +0000 | [diff] [blame] | 1370 | |
Dale Johannesen | 48c1bc2 | 2008-10-02 18:53:47 +0000 | [diff] [blame] | 1371 | |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 1372 | // Lock instruction prefix |
| 1373 | def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>; |
| 1374 | |
Rafael Espindola | beb6898 | 2010-11-23 11:23:24 +0000 | [diff] [blame] | 1375 | // Rex64 instruction prefix |
| 1376 | def REX64_PREFIX : I<0x48, RawFrm, (outs), (ins), "rex64", []>; |
| 1377 | |
Rafael Espindola | bfd2d26 | 2010-11-27 20:29:45 +0000 | [diff] [blame] | 1378 | // Data16 instruction prefix |
| 1379 | def DATA16_PREFIX : I<0x66, RawFrm, (outs), (ins), "data16", []>; |
| 1380 | |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 1381 | // Repeat string operation instruction prefixes |
| 1382 | // These uses the DF flag in the EFLAGS register to inc or dec ECX |
| 1383 | let Defs = [ECX], Uses = [ECX,EFLAGS] in { |
| 1384 | // Repeat (used with INS, OUTS, MOVS, LODS and STOS) |
| 1385 | def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>; |
| 1386 | // Repeat while not equal (used with CMPS and SCAS) |
| 1387 | def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>; |
| 1388 | } |
| 1389 | |
Kevin Enderby | 12ce0de | 2010-02-03 21:04:42 +0000 | [diff] [blame] | 1390 | |
Sean Callanan | 9a86f10 | 2009-09-16 22:59:28 +0000 | [diff] [blame] | 1391 | // String manipulation instructions |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1392 | def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", [], IIC_LODS>; |
| 1393 | def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", [], IIC_LODS>, OpSize; |
| 1394 | def LODSD : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", [], IIC_LODS>; |
| 1395 | def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", [], IIC_LODS>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1396 | |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1397 | def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", [], IIC_OUTS>; |
| 1398 | def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", [], IIC_OUTS>, OpSize; |
| 1399 | def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", [], IIC_OUTS>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1400 | |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1401 | |
| 1402 | // Flag instructions |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1403 | def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", [], IIC_CLC>; |
| 1404 | def STC : I<0xF9, RawFrm, (outs), (ins), "stc", [], IIC_STC>; |
| 1405 | def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", [], IIC_CLI>; |
| 1406 | def STI : I<0xFB, RawFrm, (outs), (ins), "sti", [], IIC_STI>; |
| 1407 | def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", [], IIC_CLD>; |
| 1408 | def STD : I<0xFD, RawFrm, (outs), (ins), "std", [], IIC_STD>; |
| 1409 | def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", [], IIC_CMC>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1410 | |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1411 | def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", [], IIC_CLTS>, TB; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1412 | |
| 1413 | // Table lookup instructions |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1414 | def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", [], IIC_XLAT>; |
Sean Callanan | 108934c | 2009-12-18 00:01:26 +0000 | [diff] [blame] | 1415 | |
Kevin Enderby | 7aef62f | 2010-10-18 17:04:36 +0000 | [diff] [blame] | 1416 | // ASCII Adjust After Addition |
| 1417 | // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1418 | def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", [], IIC_AAA>, |
| 1419 | Requires<[In32BitMode]>; |
Evan Cheng | 510e478 | 2006-01-09 23:10:28 +0000 | [diff] [blame] | 1420 | |
Kevin Enderby | 7aef62f | 2010-10-18 17:04:36 +0000 | [diff] [blame] | 1421 | // ASCII Adjust AX Before Division |
| 1422 | // sets AL, AH and EFLAGS and uses AL and AH |
| 1423 | def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1424 | "aad\t$src", [], IIC_AAD>, Requires<[In32BitMode]>; |
Kevin Enderby | 7aef62f | 2010-10-18 17:04:36 +0000 | [diff] [blame] | 1425 | |
| 1426 | // ASCII Adjust AX After Multiply |
| 1427 | // sets AL, AH and EFLAGS and uses AL |
| 1428 | def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1429 | "aam\t$src", [], IIC_AAM>, Requires<[In32BitMode]>; |
Kevin Enderby | 7aef62f | 2010-10-18 17:04:36 +0000 | [diff] [blame] | 1430 | |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 1431 | // ASCII Adjust AL After Subtraction - sets |
Kevin Enderby | 7aef62f | 2010-10-18 17:04:36 +0000 | [diff] [blame] | 1432 | // sets AL, AH and CF and AF of EFLAGS and uses AL and AF of EFLAGS |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1433 | def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", [], IIC_AAS>, |
| 1434 | Requires<[In32BitMode]>; |
Kevin Enderby | 7aef62f | 2010-10-18 17:04:36 +0000 | [diff] [blame] | 1435 | |
| 1436 | // Decimal Adjust AL after Addition |
| 1437 | // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1438 | def DAA : I<0x27, RawFrm, (outs), (ins), "daa", [], IIC_DAA>, |
| 1439 | Requires<[In32BitMode]>; |
Kevin Enderby | 7aef62f | 2010-10-18 17:04:36 +0000 | [diff] [blame] | 1440 | |
| 1441 | // Decimal Adjust AL after Subtraction |
| 1442 | // sets AL, CF and AF of EFLAGS and uses AL, CF and AF of EFLAGS |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1443 | def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>, |
| 1444 | Requires<[In32BitMode]>; |
Kevin Enderby | 7aef62f | 2010-10-18 17:04:36 +0000 | [diff] [blame] | 1445 | |
| 1446 | // Check Array Index Against Bounds |
| 1447 | def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1448 | "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize, |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 1449 | Requires<[In32BitMode]>; |
Kevin Enderby | 7aef62f | 2010-10-18 17:04:36 +0000 | [diff] [blame] | 1450 | def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1451 | "bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, |
Michael J. Spencer | 6e56b18 | 2010-10-20 23:40:27 +0000 | [diff] [blame] | 1452 | Requires<[In32BitMode]>; |
Kevin Enderby | 7aef62f | 2010-10-18 17:04:36 +0000 | [diff] [blame] | 1453 | |
| 1454 | // Adjust RPL Field of Segment Selector |
| 1455 | def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$src), (ins GR16:$dst), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1456 | "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_REG>, |
| 1457 | Requires<[In32BitMode]>; |
Kevin Enderby | 7aef62f | 2010-10-18 17:04:36 +0000 | [diff] [blame] | 1458 | def ARPL16mr : I<0x63, MRMSrcMem, (outs GR16:$src), (ins i16mem:$dst), |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1459 | "arpl\t{$src, $dst|$dst, $src}", [], IIC_ARPL_MEM>, |
| 1460 | Requires<[In32BitMode]>; |
Dan Gohman | e220c4b | 2009-09-18 19:59:53 +0000 | [diff] [blame] | 1461 | |
Bill Wendling | d350e02 | 2008-12-12 21:15:41 +0000 | [diff] [blame] | 1462 | //===----------------------------------------------------------------------===// |
Craig Topper | 581fe82 | 2011-10-03 17:28:23 +0000 | [diff] [blame] | 1463 | // MOVBE Instructions |
| 1464 | // |
| 1465 | let Predicates = [HasMOVBE] in { |
| 1466 | def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
Benjamin Kramer | a86a586 | 2011-10-10 18:34:56 +0000 | [diff] [blame] | 1467 | "movbe{w}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1468 | [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>, |
| 1469 | OpSize, T8; |
Craig Topper | 581fe82 | 2011-10-03 17:28:23 +0000 | [diff] [blame] | 1470 | def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
Benjamin Kramer | a86a586 | 2011-10-10 18:34:56 +0000 | [diff] [blame] | 1471 | "movbe{l}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1472 | [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>, |
| 1473 | T8; |
Craig Topper | 581fe82 | 2011-10-03 17:28:23 +0000 | [diff] [blame] | 1474 | def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), |
Benjamin Kramer | a86a586 | 2011-10-10 18:34:56 +0000 | [diff] [blame] | 1475 | "movbe{q}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1476 | [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>, |
| 1477 | T8; |
Craig Topper | 581fe82 | 2011-10-03 17:28:23 +0000 | [diff] [blame] | 1478 | def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), |
Benjamin Kramer | a86a586 | 2011-10-10 18:34:56 +0000 | [diff] [blame] | 1479 | "movbe{w}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1480 | [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>, |
| 1481 | OpSize, T8; |
Craig Topper | 581fe82 | 2011-10-03 17:28:23 +0000 | [diff] [blame] | 1482 | def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), |
Benjamin Kramer | a86a586 | 2011-10-10 18:34:56 +0000 | [diff] [blame] | 1483 | "movbe{l}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1484 | [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>, |
| 1485 | T8; |
Craig Topper | 581fe82 | 2011-10-03 17:28:23 +0000 | [diff] [blame] | 1486 | def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), |
Benjamin Kramer | a86a586 | 2011-10-10 18:34:56 +0000 | [diff] [blame] | 1487 | "movbe{q}\t{$src, $dst|$dst, $src}", |
Preston Gurd | deaa3f3 | 2012-05-10 21:58:35 +0000 | [diff] [blame] | 1488 | [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>, |
| 1489 | T8; |
Craig Topper | 581fe82 | 2011-10-03 17:28:23 +0000 | [diff] [blame] | 1490 | } |
| 1491 | |
| 1492 | //===----------------------------------------------------------------------===// |
| 1493 | // RDRAND Instruction |
| 1494 | // |
| 1495 | let Predicates = [HasRDRAND], Defs = [EFLAGS] in { |
| 1496 | def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins), |
Benjamin Kramer | b9bee04 | 2012-07-12 09:31:43 +0000 | [diff] [blame] | 1497 | "rdrand{w}\t$dst", |
| 1498 | [(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize, TB; |
Craig Topper | 581fe82 | 2011-10-03 17:28:23 +0000 | [diff] [blame] | 1499 | def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins), |
Benjamin Kramer | b9bee04 | 2012-07-12 09:31:43 +0000 | [diff] [blame] | 1500 | "rdrand{l}\t$dst", |
| 1501 | [(set GR32:$dst, EFLAGS, (X86rdrand))]>, TB; |
Craig Topper | 581fe82 | 2011-10-03 17:28:23 +0000 | [diff] [blame] | 1502 | def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins), |
Benjamin Kramer | b9bee04 | 2012-07-12 09:31:43 +0000 | [diff] [blame] | 1503 | "rdrand{q}\t$dst", |
| 1504 | [(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB; |
Craig Topper | 581fe82 | 2011-10-03 17:28:23 +0000 | [diff] [blame] | 1505 | } |
| 1506 | |
| 1507 | //===----------------------------------------------------------------------===// |
Craig Topper | 37f2167 | 2011-10-11 06:44:02 +0000 | [diff] [blame] | 1508 | // LZCNT Instruction |
| 1509 | // |
| 1510 | let Predicates = [HasLZCNT], Defs = [EFLAGS] in { |
| 1511 | def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
| 1512 | "lzcnt{w}\t{$src, $dst|$dst, $src}", |
Craig Topper | d501c71 | 2011-10-13 06:18:52 +0000 | [diff] [blame] | 1513 | [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS, |
| 1514 | OpSize; |
Craig Topper | 37f2167 | 2011-10-11 06:44:02 +0000 | [diff] [blame] | 1515 | def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
| 1516 | "lzcnt{w}\t{$src, $dst|$dst, $src}", |
Craig Topper | d501c71 | 2011-10-13 06:18:52 +0000 | [diff] [blame] | 1517 | [(set GR16:$dst, (ctlz (loadi16 addr:$src))), |
| 1518 | (implicit EFLAGS)]>, XS, OpSize; |
Craig Topper | 37f2167 | 2011-10-11 06:44:02 +0000 | [diff] [blame] | 1519 | |
| 1520 | def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
| 1521 | "lzcnt{l}\t{$src, $dst|$dst, $src}", |
Craig Topper | d501c71 | 2011-10-13 06:18:52 +0000 | [diff] [blame] | 1522 | [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS; |
Craig Topper | 37f2167 | 2011-10-11 06:44:02 +0000 | [diff] [blame] | 1523 | def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
| 1524 | "lzcnt{l}\t{$src, $dst|$dst, $src}", |
Craig Topper | d501c71 | 2011-10-13 06:18:52 +0000 | [diff] [blame] | 1525 | [(set GR32:$dst, (ctlz (loadi32 addr:$src))), |
| 1526 | (implicit EFLAGS)]>, XS; |
Craig Topper | 37f2167 | 2011-10-11 06:44:02 +0000 | [diff] [blame] | 1527 | |
| 1528 | def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), |
| 1529 | "lzcnt{q}\t{$src, $dst|$dst, $src}", |
Craig Topper | d501c71 | 2011-10-13 06:18:52 +0000 | [diff] [blame] | 1530 | [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>, |
| 1531 | XS; |
Craig Topper | 37f2167 | 2011-10-11 06:44:02 +0000 | [diff] [blame] | 1532 | def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), |
| 1533 | "lzcnt{q}\t{$src, $dst|$dst, $src}", |
Craig Topper | d501c71 | 2011-10-13 06:18:52 +0000 | [diff] [blame] | 1534 | [(set GR64:$dst, (ctlz (loadi64 addr:$src))), |
| 1535 | (implicit EFLAGS)]>, XS; |
Craig Topper | 37f2167 | 2011-10-11 06:44:02 +0000 | [diff] [blame] | 1536 | } |
| 1537 | |
| 1538 | //===----------------------------------------------------------------------===// |
Craig Topper | 566f233 | 2011-10-15 20:46:47 +0000 | [diff] [blame] | 1539 | // BMI Instructions |
Craig Topper | 909652f | 2011-10-14 03:21:46 +0000 | [diff] [blame] | 1540 | // |
| 1541 | let Predicates = [HasBMI], Defs = [EFLAGS] in { |
| 1542 | def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), |
| 1543 | "tzcnt{w}\t{$src, $dst|$dst, $src}", |
| 1544 | [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS, |
| 1545 | OpSize; |
| 1546 | def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), |
| 1547 | "tzcnt{w}\t{$src, $dst|$dst, $src}", |
| 1548 | [(set GR16:$dst, (cttz (loadi16 addr:$src))), |
| 1549 | (implicit EFLAGS)]>, XS, OpSize; |
| 1550 | |
| 1551 | def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), |
| 1552 | "tzcnt{l}\t{$src, $dst|$dst, $src}", |
| 1553 | [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS; |
| 1554 | def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), |
| 1555 | "tzcnt{l}\t{$src, $dst|$dst, $src}", |
| 1556 | [(set GR32:$dst, (cttz (loadi32 addr:$src))), |
| 1557 | (implicit EFLAGS)]>, XS; |
| 1558 | |
| 1559 | def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), |
| 1560 | "tzcnt{q}\t{$src, $dst|$dst, $src}", |
| 1561 | [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>, |
| 1562 | XS; |
| 1563 | def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), |
| 1564 | "tzcnt{q}\t{$src, $dst|$dst, $src}", |
| 1565 | [(set GR64:$dst, (cttz (loadi64 addr:$src))), |
| 1566 | (implicit EFLAGS)]>, XS; |
| 1567 | } |
| 1568 | |
Craig Topper | 566f233 | 2011-10-15 20:46:47 +0000 | [diff] [blame] | 1569 | multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM, |
Craig Topper | b4c9457 | 2011-10-21 06:55:01 +0000 | [diff] [blame] | 1570 | RegisterClass RC, X86MemOperand x86memop, SDNode OpNode, |
| 1571 | PatFrag ld_frag> { |
Craig Topper | 566f233 | 2011-10-15 20:46:47 +0000 | [diff] [blame] | 1572 | def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src), |
Craig Topper | 717cdb0 | 2011-10-19 07:48:35 +0000 | [diff] [blame] | 1573 | !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), |
Craig Topper | b4c9457 | 2011-10-21 06:55:01 +0000 | [diff] [blame] | 1574 | [(set RC:$dst, EFLAGS, (OpNode RC:$src))]>, T8, VEX_4V; |
Craig Topper | 566f233 | 2011-10-15 20:46:47 +0000 | [diff] [blame] | 1575 | def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src), |
Craig Topper | 717cdb0 | 2011-10-19 07:48:35 +0000 | [diff] [blame] | 1576 | !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), |
Craig Topper | b4c9457 | 2011-10-21 06:55:01 +0000 | [diff] [blame] | 1577 | [(set RC:$dst, EFLAGS, (OpNode (ld_frag addr:$src)))]>, |
Craig Topper | 717cdb0 | 2011-10-19 07:48:35 +0000 | [diff] [blame] | 1578 | T8, VEX_4V; |
Craig Topper | 566f233 | 2011-10-15 20:46:47 +0000 | [diff] [blame] | 1579 | } |
| 1580 | |
| 1581 | let Predicates = [HasBMI], Defs = [EFLAGS] in { |
Craig Topper | 717cdb0 | 2011-10-19 07:48:35 +0000 | [diff] [blame] | 1582 | defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem, |
Craig Topper | b4c9457 | 2011-10-21 06:55:01 +0000 | [diff] [blame] | 1583 | X86blsr_flag, loadi32>; |
Craig Topper | 717cdb0 | 2011-10-19 07:48:35 +0000 | [diff] [blame] | 1584 | defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem, |
Craig Topper | b4c9457 | 2011-10-21 06:55:01 +0000 | [diff] [blame] | 1585 | X86blsr_flag, loadi64>, VEX_W; |
Craig Topper | 717cdb0 | 2011-10-19 07:48:35 +0000 | [diff] [blame] | 1586 | defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem, |
Craig Topper | b4c9457 | 2011-10-21 06:55:01 +0000 | [diff] [blame] | 1587 | X86blsmsk_flag, loadi32>; |
Craig Topper | 717cdb0 | 2011-10-19 07:48:35 +0000 | [diff] [blame] | 1588 | defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem, |
Craig Topper | b4c9457 | 2011-10-21 06:55:01 +0000 | [diff] [blame] | 1589 | X86blsmsk_flag, loadi64>, VEX_W; |
Craig Topper | 717cdb0 | 2011-10-19 07:48:35 +0000 | [diff] [blame] | 1590 | defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem, |
Craig Topper | b4c9457 | 2011-10-21 06:55:01 +0000 | [diff] [blame] | 1591 | X86blsi_flag, loadi32>; |
Craig Topper | 717cdb0 | 2011-10-19 07:48:35 +0000 | [diff] [blame] | 1592 | defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem, |
Craig Topper | b4c9457 | 2011-10-21 06:55:01 +0000 | [diff] [blame] | 1593 | X86blsi_flag, loadi64>, VEX_W; |
Craig Topper | 1773084 | 2011-10-16 03:51:13 +0000 | [diff] [blame] | 1594 | } |
| 1595 | |
Craig Topper | b53fa8b | 2011-10-16 07:55:05 +0000 | [diff] [blame] | 1596 | multiclass bmi_bextr_bzhi<bits<8> opc, string mnemonic, RegisterClass RC, |
Craig Topper | 717cdb0 | 2011-10-19 07:48:35 +0000 | [diff] [blame] | 1597 | X86MemOperand x86memop, Intrinsic Int, |
| 1598 | PatFrag ld_frag> { |
Craig Topper | b53fa8b | 2011-10-16 07:55:05 +0000 | [diff] [blame] | 1599 | def rr : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), |
Craig Topper | 1773084 | 2011-10-16 03:51:13 +0000 | [diff] [blame] | 1600 | !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), |
Craig Topper | 717cdb0 | 2011-10-19 07:48:35 +0000 | [diff] [blame] | 1601 | [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>, |
| 1602 | T8, VEX_4VOp3; |
Craig Topper | b53fa8b | 2011-10-16 07:55:05 +0000 | [diff] [blame] | 1603 | def rm : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), |
Craig Topper | 1773084 | 2011-10-16 03:51:13 +0000 | [diff] [blame] | 1604 | !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), |
Craig Topper | 717cdb0 | 2011-10-19 07:48:35 +0000 | [diff] [blame] | 1605 | [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)), |
| 1606 | (implicit EFLAGS)]>, T8, VEX_4VOp3; |
Craig Topper | 1773084 | 2011-10-16 03:51:13 +0000 | [diff] [blame] | 1607 | } |
| 1608 | |
| 1609 | let Predicates = [HasBMI], Defs = [EFLAGS] in { |
Craig Topper | 717cdb0 | 2011-10-19 07:48:35 +0000 | [diff] [blame] | 1610 | defm BEXTR32 : bmi_bextr_bzhi<0xF7, "bextr{l}", GR32, i32mem, |
| 1611 | int_x86_bmi_bextr_32, loadi32>; |
| 1612 | defm BEXTR64 : bmi_bextr_bzhi<0xF7, "bextr{q}", GR64, i64mem, |
| 1613 | int_x86_bmi_bextr_64, loadi64>, VEX_W; |
Craig Topper | b53fa8b | 2011-10-16 07:55:05 +0000 | [diff] [blame] | 1614 | } |
| 1615 | |
| 1616 | let Predicates = [HasBMI2], Defs = [EFLAGS] in { |
Craig Topper | 717cdb0 | 2011-10-19 07:48:35 +0000 | [diff] [blame] | 1617 | defm BZHI32 : bmi_bextr_bzhi<0xF5, "bzhi{l}", GR32, i32mem, |
| 1618 | int_x86_bmi_bzhi_32, loadi32>; |
| 1619 | defm BZHI64 : bmi_bextr_bzhi<0xF5, "bzhi{q}", GR64, i64mem, |
| 1620 | int_x86_bmi_bzhi_64, loadi64>, VEX_W; |
Craig Topper | 566f233 | 2011-10-15 20:46:47 +0000 | [diff] [blame] | 1621 | } |
| 1622 | |
Craig Topper | 717cdb0 | 2011-10-19 07:48:35 +0000 | [diff] [blame] | 1623 | multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC, |
| 1624 | X86MemOperand x86memop, Intrinsic Int, |
| 1625 | PatFrag ld_frag> { |
Craig Topper | ee62e4f | 2011-10-16 16:50:08 +0000 | [diff] [blame] | 1626 | def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), |
| 1627 | !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), |
Craig Topper | 717cdb0 | 2011-10-19 07:48:35 +0000 | [diff] [blame] | 1628 | [(set RC:$dst, (Int RC:$src1, RC:$src2))]>, |
| 1629 | VEX_4V; |
Craig Topper | ee62e4f | 2011-10-16 16:50:08 +0000 | [diff] [blame] | 1630 | def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), |
| 1631 | !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), |
Craig Topper | 717cdb0 | 2011-10-19 07:48:35 +0000 | [diff] [blame] | 1632 | [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V; |
Craig Topper | ee62e4f | 2011-10-16 16:50:08 +0000 | [diff] [blame] | 1633 | } |
| 1634 | |
| 1635 | let Predicates = [HasBMI2] in { |
Craig Topper | 717cdb0 | 2011-10-19 07:48:35 +0000 | [diff] [blame] | 1636 | defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem, |
| 1637 | int_x86_bmi_pdep_32, loadi32>, T8XD; |
| 1638 | defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem, |
| 1639 | int_x86_bmi_pdep_64, loadi64>, T8XD, VEX_W; |
| 1640 | defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem, |
| 1641 | int_x86_bmi_pext_32, loadi32>, T8XS; |
| 1642 | defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem, |
| 1643 | int_x86_bmi_pext_64, loadi64>, T8XS, VEX_W; |
Craig Topper | ee62e4f | 2011-10-16 16:50:08 +0000 | [diff] [blame] | 1644 | } |
| 1645 | |
Craig Topper | 909652f | 2011-10-14 03:21:46 +0000 | [diff] [blame] | 1646 | //===----------------------------------------------------------------------===// |
Chris Lattner | 434c7cb | 2010-10-05 05:32:15 +0000 | [diff] [blame] | 1647 | // Subsystems. |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 1648 | //===----------------------------------------------------------------------===// |
| 1649 | |
Chris Lattner | 6367cfc | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 1650 | include "X86InstrArithmetic.td" |
Chris Lattner | 35649fc | 2010-10-05 06:33:16 +0000 | [diff] [blame] | 1651 | include "X86InstrCMovSetCC.td" |
Chris Lattner | 8917cd3 | 2010-10-05 06:52:26 +0000 | [diff] [blame] | 1652 | include "X86InstrExtension.td" |
Chris Lattner | 87be16a | 2010-10-05 06:04:14 +0000 | [diff] [blame] | 1653 | include "X86InstrControl.td" |
Chris Lattner | 5f58e84 | 2010-10-05 07:00:12 +0000 | [diff] [blame] | 1654 | include "X86InstrShiftRotate.td" |
Chris Lattner | 87be16a | 2010-10-05 06:04:14 +0000 | [diff] [blame] | 1655 | |
Chris Lattner | 6367cfc | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 1656 | // X87 Floating Point Stack. |
| 1657 | include "X86InstrFPStack.td" |
| 1658 | |
David Greene | 51898d7 | 2010-02-09 23:52:19 +0000 | [diff] [blame] | 1659 | // SIMD support (SSE, MMX and AVX) |
David Greene | 51898d7 | 2010-02-09 23:52:19 +0000 | [diff] [blame] | 1660 | include "X86InstrFragmentsSIMD.td" |
| 1661 | |
Bruno Cardoso Lopes | 6b7e916 | 2010-07-23 00:54:35 +0000 | [diff] [blame] | 1662 | // FMA - Fused Multiply-Add support (requires FMA) |
Bruno Cardoso Lopes | 6b7e916 | 2010-07-23 00:54:35 +0000 | [diff] [blame] | 1663 | include "X86InstrFMA.td" |
| 1664 | |
Jan Sjödin | 37e7ecf | 2011-12-12 19:37:49 +0000 | [diff] [blame] | 1665 | // XOP |
| 1666 | include "X86InstrXOP.td" |
| 1667 | |
Chris Lattner | 434c7cb | 2010-10-05 05:32:15 +0000 | [diff] [blame] | 1668 | // SSE, MMX and 3DNow! vector support. |
Evan Cheng | 4e4c71e | 2006-02-21 20:00:20 +0000 | [diff] [blame] | 1669 | include "X86InstrSSE.td" |
Evan Cheng | 80f5404 | 2008-04-25 18:19:54 +0000 | [diff] [blame] | 1670 | include "X86InstrMMX.td" |
Chris Lattner | 7330d97 | 2010-10-02 23:06:23 +0000 | [diff] [blame] | 1671 | include "X86Instr3DNow.td" |
| 1672 | |
Chris Lattner | d071b83 | 2010-10-05 06:06:53 +0000 | [diff] [blame] | 1673 | include "X86InstrVMX.td" |
Craig Topper | 9e3d0b3 | 2012-02-18 08:19:49 +0000 | [diff] [blame] | 1674 | include "X86InstrSVM.td" |
Chris Lattner | d071b83 | 2010-10-05 06:06:53 +0000 | [diff] [blame] | 1675 | |
Chris Lattner | 434c7cb | 2010-10-05 05:32:15 +0000 | [diff] [blame] | 1676 | // System instructions. |
| 1677 | include "X86InstrSystem.td" |
Chris Lattner | 87be16a | 2010-10-05 06:04:14 +0000 | [diff] [blame] | 1678 | |
| 1679 | // Compiler Pseudo Instructions and Pat Patterns |
| 1680 | include "X86InstrCompiler.td" |
| 1681 | |
Chris Lattner | 674c1dc | 2010-10-30 17:36:36 +0000 | [diff] [blame] | 1682 | //===----------------------------------------------------------------------===// |
Chris Lattner | efd8dad | 2010-11-01 23:07:52 +0000 | [diff] [blame] | 1683 | // Assembler Mnemonic Aliases |
Chris Lattner | 674c1dc | 2010-10-30 17:36:36 +0000 | [diff] [blame] | 1684 | //===----------------------------------------------------------------------===// |
| 1685 | |
Chris Lattner | 99f5352 | 2010-11-01 21:06:34 +0000 | [diff] [blame] | 1686 | def : MnemonicAlias<"call", "calll">, Requires<[In32BitMode]>; |
| 1687 | def : MnemonicAlias<"call", "callq">, Requires<[In64BitMode]>; |
| 1688 | |
Chris Lattner | 674c1dc | 2010-10-30 17:36:36 +0000 | [diff] [blame] | 1689 | def : MnemonicAlias<"cbw", "cbtw">; |
Benjamin Kramer | 9d399b1 | 2011-11-24 12:02:46 +0000 | [diff] [blame] | 1690 | def : MnemonicAlias<"cwde", "cwtl">; |
Chris Lattner | 674c1dc | 2010-10-30 17:36:36 +0000 | [diff] [blame] | 1691 | def : MnemonicAlias<"cwd", "cwtd">; |
| 1692 | def : MnemonicAlias<"cdq", "cltd">; |
Chris Lattner | 674c1dc | 2010-10-30 17:36:36 +0000 | [diff] [blame] | 1693 | def : MnemonicAlias<"cdqe", "cltq">; |
Benjamin Kramer | 9d399b1 | 2011-11-24 12:02:46 +0000 | [diff] [blame] | 1694 | def : MnemonicAlias<"cqo", "cqto">; |
Chris Lattner | 8b260a7 | 2010-10-30 18:07:17 +0000 | [diff] [blame] | 1695 | |
Chris Lattner | 269f10b | 2010-11-12 18:54:56 +0000 | [diff] [blame] | 1696 | // lret maps to lretl, it is not ambiguous with lretq. |
| 1697 | def : MnemonicAlias<"lret", "lretl">; |
| 1698 | |
Joerg Sonnenberger | 97755a0 | 2011-02-17 23:36:39 +0000 | [diff] [blame] | 1699 | def : MnemonicAlias<"leavel", "leave">, Requires<[In32BitMode]>; |
| 1700 | def : MnemonicAlias<"leaveq", "leave">, Requires<[In64BitMode]>; |
| 1701 | |
Joerg Sonnenberger | d86f482 | 2011-02-22 00:43:07 +0000 | [diff] [blame] | 1702 | def : MnemonicAlias<"loopz", "loope">; |
| 1703 | def : MnemonicAlias<"loopnz", "loopne">; |
| 1704 | |
Chris Lattner | 693173f | 2010-10-30 19:23:13 +0000 | [diff] [blame] | 1705 | def : MnemonicAlias<"pop", "popl">, Requires<[In32BitMode]>; |
| 1706 | def : MnemonicAlias<"pop", "popq">, Requires<[In64BitMode]>; |
| 1707 | def : MnemonicAlias<"popf", "popfl">, Requires<[In32BitMode]>; |
| 1708 | def : MnemonicAlias<"popf", "popfq">, Requires<[In64BitMode]>; |
Chris Lattner | 8b260a7 | 2010-10-30 18:07:17 +0000 | [diff] [blame] | 1709 | def : MnemonicAlias<"popfd", "popfl">; |
| 1710 | |
Chris Lattner | a33b93f | 2010-10-31 18:43:46 +0000 | [diff] [blame] | 1711 | // FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in |
| 1712 | // all modes. However: "push (addr)" and "push $42" should default to |
| 1713 | // pushl/pushq depending on the current mode. Similar for "pop %bx" |
Chris Lattner | 693173f | 2010-10-30 19:23:13 +0000 | [diff] [blame] | 1714 | def : MnemonicAlias<"push", "pushl">, Requires<[In32BitMode]>; |
| 1715 | def : MnemonicAlias<"push", "pushq">, Requires<[In64BitMode]>; |
| 1716 | def : MnemonicAlias<"pushf", "pushfl">, Requires<[In32BitMode]>; |
| 1717 | def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>; |
| 1718 | def : MnemonicAlias<"pushfd", "pushfl">; |
| 1719 | |
Chris Lattner | 6f96b08 | 2010-10-30 18:17:33 +0000 | [diff] [blame] | 1720 | def : MnemonicAlias<"repe", "rep">; |
| 1721 | def : MnemonicAlias<"repz", "rep">; |
| 1722 | def : MnemonicAlias<"repnz", "repne">; |
| 1723 | |
Chris Lattner | 693173f | 2010-10-30 19:23:13 +0000 | [diff] [blame] | 1724 | def : MnemonicAlias<"retl", "ret">, Requires<[In32BitMode]>; |
| 1725 | def : MnemonicAlias<"retq", "ret">, Requires<[In64BitMode]>; |
| 1726 | |
Chris Lattner | a17a9a0 | 2010-10-30 18:14:54 +0000 | [diff] [blame] | 1727 | def : MnemonicAlias<"salb", "shlb">; |
| 1728 | def : MnemonicAlias<"salw", "shlw">; |
| 1729 | def : MnemonicAlias<"sall", "shll">; |
| 1730 | def : MnemonicAlias<"salq", "shlq">; |
| 1731 | |
Chris Lattner | 674c1dc | 2010-10-30 17:36:36 +0000 | [diff] [blame] | 1732 | def : MnemonicAlias<"smovb", "movsb">; |
| 1733 | def : MnemonicAlias<"smovw", "movsw">; |
| 1734 | def : MnemonicAlias<"smovl", "movsl">; |
| 1735 | def : MnemonicAlias<"smovq", "movsq">; |
| 1736 | |
Chris Lattner | 674c1dc | 2010-10-30 17:36:36 +0000 | [diff] [blame] | 1737 | def : MnemonicAlias<"ud2a", "ud2">; |
| 1738 | def : MnemonicAlias<"verrw", "verr">; |
| 1739 | |
Chris Lattner | 99f5352 | 2010-11-01 21:06:34 +0000 | [diff] [blame] | 1740 | // System instruction aliases. |
| 1741 | def : MnemonicAlias<"iret", "iretl">; |
| 1742 | def : MnemonicAlias<"sysret", "sysretl">; |
Kevin Enderby | 55c4127 | 2011-10-27 17:40:41 +0000 | [diff] [blame] | 1743 | def : MnemonicAlias<"sysexit", "sysexitl">; |
Chris Lattner | 99f5352 | 2010-11-01 21:06:34 +0000 | [diff] [blame] | 1744 | |
| 1745 | def : MnemonicAlias<"lgdtl", "lgdt">, Requires<[In32BitMode]>; |
| 1746 | def : MnemonicAlias<"lgdtq", "lgdt">, Requires<[In64BitMode]>; |
| 1747 | def : MnemonicAlias<"lidtl", "lidt">, Requires<[In32BitMode]>; |
| 1748 | def : MnemonicAlias<"lidtq", "lidt">, Requires<[In64BitMode]>; |
| 1749 | def : MnemonicAlias<"sgdtl", "sgdt">, Requires<[In32BitMode]>; |
| 1750 | def : MnemonicAlias<"sgdtq", "sgdt">, Requires<[In64BitMode]>; |
| 1751 | def : MnemonicAlias<"sidtl", "sidt">, Requires<[In32BitMode]>; |
| 1752 | def : MnemonicAlias<"sidtq", "sidt">, Requires<[In64BitMode]>; |
| 1753 | |
Chris Lattner | 674c1dc | 2010-10-30 17:36:36 +0000 | [diff] [blame] | 1754 | |
Chris Lattner | 8b260a7 | 2010-10-30 18:07:17 +0000 | [diff] [blame] | 1755 | // Floating point stack aliases. |
| 1756 | def : MnemonicAlias<"fcmovz", "fcmove">; |
| 1757 | def : MnemonicAlias<"fcmova", "fcmovnbe">; |
| 1758 | def : MnemonicAlias<"fcmovnae", "fcmovb">; |
| 1759 | def : MnemonicAlias<"fcmovna", "fcmovbe">; |
| 1760 | def : MnemonicAlias<"fcmovae", "fcmovnb">; |
Chris Lattner | db28788 | 2010-11-06 21:37:06 +0000 | [diff] [blame] | 1761 | def : MnemonicAlias<"fcomip", "fcompi">; |
Chris Lattner | 8b260a7 | 2010-10-30 18:07:17 +0000 | [diff] [blame] | 1762 | def : MnemonicAlias<"fildq", "fildll">; |
Chad Rosier | 77834e7 | 2012-02-27 19:43:12 +0000 | [diff] [blame] | 1763 | def : MnemonicAlias<"fistpq", "fistpll">; |
| 1764 | def : MnemonicAlias<"fisttpq", "fisttpll">; |
Chris Lattner | 8b260a7 | 2010-10-30 18:07:17 +0000 | [diff] [blame] | 1765 | def : MnemonicAlias<"fldcww", "fldcw">; |
| 1766 | def : MnemonicAlias<"fnstcww", "fnstcw">; |
| 1767 | def : MnemonicAlias<"fnstsww", "fnstsw">; |
Chris Lattner | db28788 | 2010-11-06 21:37:06 +0000 | [diff] [blame] | 1768 | def : MnemonicAlias<"fucomip", "fucompi">; |
Chris Lattner | 8b260a7 | 2010-10-30 18:07:17 +0000 | [diff] [blame] | 1769 | def : MnemonicAlias<"fwait", "wait">; |
| 1770 | |
| 1771 | |
Chris Lattner | 8cb441c | 2010-10-30 17:56:50 +0000 | [diff] [blame] | 1772 | class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond> |
| 1773 | : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix), |
| 1774 | !strconcat(Prefix, NewCond, Suffix)>; |
Chris Lattner | b69fc28 | 2010-10-30 17:51:45 +0000 | [diff] [blame] | 1775 | |
| 1776 | /// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of |
| 1777 | /// MnemonicAlias's that canonicalize the condition code in a mnemonic, for |
| 1778 | /// example "setz" -> "sete". |
Chris Lattner | 8cb441c | 2010-10-30 17:56:50 +0000 | [diff] [blame] | 1779 | multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix> { |
| 1780 | def C : CondCodeAlias<Prefix, Suffix, "c", "b">; // setc -> setb |
| 1781 | def Z : CondCodeAlias<Prefix, Suffix, "z" , "e">; // setz -> sete |
| 1782 | def NA : CondCodeAlias<Prefix, Suffix, "na", "be">; // setna -> setbe |
| 1783 | def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae">; // setnb -> setae |
| 1784 | def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae">; // setnc -> setae |
| 1785 | def NG : CondCodeAlias<Prefix, Suffix, "ng", "le">; // setng -> setle |
| 1786 | def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge">; // setnl -> setge |
| 1787 | def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne">; // setnz -> setne |
| 1788 | def PE : CondCodeAlias<Prefix, Suffix, "pe", "p">; // setpe -> setp |
| 1789 | def PO : CondCodeAlias<Prefix, Suffix, "po", "np">; // setpo -> setnp |
Chris Lattner | b69fc28 | 2010-10-30 17:51:45 +0000 | [diff] [blame] | 1790 | |
Chris Lattner | 8cb441c | 2010-10-30 17:56:50 +0000 | [diff] [blame] | 1791 | def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b">; // setnae -> setb |
| 1792 | def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a">; // setnbe -> seta |
| 1793 | def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l">; // setnge -> setl |
| 1794 | def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g">; // setnle -> setg |
Chris Lattner | b69fc28 | 2010-10-30 17:51:45 +0000 | [diff] [blame] | 1795 | } |
| 1796 | |
| 1797 | // Aliases for set<CC> |
Chris Lattner | 8cb441c | 2010-10-30 17:56:50 +0000 | [diff] [blame] | 1798 | defm : IntegerCondCodeMnemonicAlias<"set", "">; |
Chris Lattner | b69fc28 | 2010-10-30 17:51:45 +0000 | [diff] [blame] | 1799 | // Aliases for j<CC> |
Chris Lattner | 8cb441c | 2010-10-30 17:56:50 +0000 | [diff] [blame] | 1800 | defm : IntegerCondCodeMnemonicAlias<"j", "">; |
| 1801 | // Aliases for cmov<CC>{w,l,q} |
| 1802 | defm : IntegerCondCodeMnemonicAlias<"cmov", "w">; |
| 1803 | defm : IntegerCondCodeMnemonicAlias<"cmov", "l">; |
| 1804 | defm : IntegerCondCodeMnemonicAlias<"cmov", "q">; |
Chris Lattner | 674c1dc | 2010-10-30 17:36:36 +0000 | [diff] [blame] | 1805 | |
Chris Lattner | efd8dad | 2010-11-01 23:07:52 +0000 | [diff] [blame] | 1806 | |
| 1807 | //===----------------------------------------------------------------------===// |
| 1808 | // Assembler Instruction Aliases |
| 1809 | //===----------------------------------------------------------------------===// |
| 1810 | |
Chris Lattner | 98c870f | 2010-11-06 19:25:43 +0000 | [diff] [blame] | 1811 | // aad/aam default to base 10 if no operand is specified. |
| 1812 | def : InstAlias<"aad", (AAD8i8 10)>; |
| 1813 | def : InstAlias<"aam", (AAM8i8 10)>; |
| 1814 | |
Chris Lattner | 824a907 | 2011-02-19 21:06:36 +0000 | [diff] [blame] | 1815 | // Disambiguate the mem/imm form of bt-without-a-suffix as btl. |
| 1816 | def : InstAlias<"bt $imm, $mem", (BT32mi8 i32mem:$mem, i32i8imm:$imm)>; |
| 1817 | |
Chris Lattner | 4140985 | 2010-11-06 07:31:43 +0000 | [diff] [blame] | 1818 | // clr aliases. |
| 1819 | def : InstAlias<"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)>; |
| 1820 | def : InstAlias<"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)>; |
| 1821 | def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)>; |
| 1822 | def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)>; |
| 1823 | |
Chris Lattner | 689cf3c | 2010-11-06 22:41:18 +0000 | [diff] [blame] | 1824 | // div and idiv aliases for explicit A register. |
| 1825 | def : InstAlias<"divb $src, %al", (DIV8r GR8 :$src)>; |
| 1826 | def : InstAlias<"divw $src, %ax", (DIV16r GR16:$src)>; |
| 1827 | def : InstAlias<"divl $src, %eax", (DIV32r GR32:$src)>; |
| 1828 | def : InstAlias<"divq $src, %rax", (DIV64r GR64:$src)>; |
| 1829 | def : InstAlias<"divb $src, %al", (DIV8m i8mem :$src)>; |
| 1830 | def : InstAlias<"divw $src, %ax", (DIV16m i16mem:$src)>; |
| 1831 | def : InstAlias<"divl $src, %eax", (DIV32m i32mem:$src)>; |
| 1832 | def : InstAlias<"divq $src, %rax", (DIV64m i64mem:$src)>; |
| 1833 | def : InstAlias<"idivb $src, %al", (IDIV8r GR8 :$src)>; |
| 1834 | def : InstAlias<"idivw $src, %ax", (IDIV16r GR16:$src)>; |
| 1835 | def : InstAlias<"idivl $src, %eax", (IDIV32r GR32:$src)>; |
| 1836 | def : InstAlias<"idivq $src, %rax", (IDIV64r GR64:$src)>; |
| 1837 | def : InstAlias<"idivb $src, %al", (IDIV8m i8mem :$src)>; |
| 1838 | def : InstAlias<"idivw $src, %ax", (IDIV16m i16mem:$src)>; |
| 1839 | def : InstAlias<"idivl $src, %eax", (IDIV32m i32mem:$src)>; |
| 1840 | def : InstAlias<"idivq $src, %rax", (IDIV64m i64mem:$src)>; |
| 1841 | |
| 1842 | |
| 1843 | |
Chris Lattner | 3af0e7d | 2010-11-06 20:47:38 +0000 | [diff] [blame] | 1844 | // Various unary fpstack operations default to operating on on ST1. |
| 1845 | // For example, "fxch" -> "fxch %st(1)" |
Bill Wendling | c6df988 | 2011-04-14 01:11:51 +0000 | [diff] [blame] | 1846 | def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>; |
Chris Lattner | 3af0e7d | 2010-11-06 20:47:38 +0000 | [diff] [blame] | 1847 | def : InstAlias<"fsubp", (SUBR_FPrST0 ST1)>; |
| 1848 | def : InstAlias<"fsubrp", (SUB_FPrST0 ST1)>; |
| 1849 | def : InstAlias<"fmulp", (MUL_FPrST0 ST1)>; |
| 1850 | def : InstAlias<"fdivp", (DIVR_FPrST0 ST1)>; |
| 1851 | def : InstAlias<"fdivrp", (DIV_FPrST0 ST1)>; |
| 1852 | def : InstAlias<"fxch", (XCH_F ST1)>; |
| 1853 | def : InstAlias<"fcomi", (COM_FIr ST1)>; |
Chris Lattner | db28788 | 2010-11-06 21:37:06 +0000 | [diff] [blame] | 1854 | def : InstAlias<"fcompi", (COM_FIPr ST1)>; |
Chris Lattner | 3af0e7d | 2010-11-06 20:47:38 +0000 | [diff] [blame] | 1855 | def : InstAlias<"fucom", (UCOM_Fr ST1)>; |
| 1856 | def : InstAlias<"fucomp", (UCOM_FPr ST1)>; |
| 1857 | def : InstAlias<"fucomi", (UCOM_FIr ST1)>; |
Chris Lattner | db28788 | 2010-11-06 21:37:06 +0000 | [diff] [blame] | 1858 | def : InstAlias<"fucompi", (UCOM_FIPr ST1)>; |
Chris Lattner | 3af0e7d | 2010-11-06 20:47:38 +0000 | [diff] [blame] | 1859 | |
| 1860 | // Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. |
| 1861 | // For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate |
| 1862 | // instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with |
| 1863 | // gas. |
Bill Wendling | c6df988 | 2011-04-14 01:11:51 +0000 | [diff] [blame] | 1864 | multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> { |
| 1865 | def : InstAlias<!strconcat(Mnemonic, " $op, %st(0)"), |
| 1866 | (Inst RST:$op), EmitAlias>; |
| 1867 | def : InstAlias<!strconcat(Mnemonic, " %st(0), %st(0)"), |
| 1868 | (Inst ST0), EmitAlias>; |
Chris Lattner | 3af0e7d | 2010-11-06 20:47:38 +0000 | [diff] [blame] | 1869 | } |
| 1870 | |
| 1871 | defm : FpUnaryAlias<"fadd", ADD_FST0r>; |
Bill Wendling | c6df988 | 2011-04-14 01:11:51 +0000 | [diff] [blame] | 1872 | defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>; |
Chris Lattner | 3af0e7d | 2010-11-06 20:47:38 +0000 | [diff] [blame] | 1873 | defm : FpUnaryAlias<"fsub", SUB_FST0r>; |
| 1874 | defm : FpUnaryAlias<"fsubp", SUBR_FPrST0>; |
| 1875 | defm : FpUnaryAlias<"fsubr", SUBR_FST0r>; |
| 1876 | defm : FpUnaryAlias<"fsubrp", SUB_FPrST0>; |
| 1877 | defm : FpUnaryAlias<"fmul", MUL_FST0r>; |
| 1878 | defm : FpUnaryAlias<"fmulp", MUL_FPrST0>; |
| 1879 | defm : FpUnaryAlias<"fdiv", DIV_FST0r>; |
| 1880 | defm : FpUnaryAlias<"fdivp", DIVR_FPrST0>; |
| 1881 | defm : FpUnaryAlias<"fdivr", DIVR_FST0r>; |
| 1882 | defm : FpUnaryAlias<"fdivrp", DIV_FPrST0>; |
Bill Wendling | c6df988 | 2011-04-14 01:11:51 +0000 | [diff] [blame] | 1883 | defm : FpUnaryAlias<"fcomi", COM_FIr, 0>; |
| 1884 | defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>; |
Chris Lattner | db28788 | 2010-11-06 21:37:06 +0000 | [diff] [blame] | 1885 | defm : FpUnaryAlias<"fcompi", COM_FIPr>; |
| 1886 | defm : FpUnaryAlias<"fucompi", UCOM_FIPr>; |
Chris Lattner | 235705b | 2010-11-06 20:55:09 +0000 | [diff] [blame] | 1887 | |
Chris Lattner | 3af0e7d | 2010-11-06 20:47:38 +0000 | [diff] [blame] | 1888 | |
| 1889 | // Handle "f{mulp,addp} st(0), $op" the same as "f{mulp,addp} $op", since they |
Nick Lewycky | c00210c | 2010-12-30 22:10:49 +0000 | [diff] [blame] | 1890 | // commute. We also allow fdiv[r]p/fsubrp even though they don't commute, |
| 1891 | // solely because gas supports it. |
Bill Wendling | c6df988 | 2011-04-14 01:11:51 +0000 | [diff] [blame] | 1892 | def : InstAlias<"faddp %st(0), $op", (ADD_FPrST0 RST:$op), 0>; |
Chris Lattner | 3af0e7d | 2010-11-06 20:47:38 +0000 | [diff] [blame] | 1893 | def : InstAlias<"fmulp %st(0), $op", (MUL_FPrST0 RST:$op)>; |
Chris Lattner | 92f920c | 2011-05-22 22:31:57 +0000 | [diff] [blame] | 1894 | def : InstAlias<"fsubp %st(0), $op", (SUBR_FPrST0 RST:$op)>; |
Chris Lattner | 3af0e7d | 2010-11-06 20:47:38 +0000 | [diff] [blame] | 1895 | def : InstAlias<"fsubrp %st(0), $op", (SUB_FPrST0 RST:$op)>; |
Nick Lewycky | c00210c | 2010-12-30 22:10:49 +0000 | [diff] [blame] | 1896 | def : InstAlias<"fdivp %st(0), $op", (DIVR_FPrST0 RST:$op)>; |
Chris Lattner | 3af0e7d | 2010-11-06 20:47:38 +0000 | [diff] [blame] | 1897 | def : InstAlias<"fdivrp %st(0), $op", (DIV_FPrST0 RST:$op)>; |
Chris Lattner | 90fd797 | 2010-11-06 19:57:21 +0000 | [diff] [blame] | 1898 | |
Nick Lewycky | c00210c | 2010-12-30 22:10:49 +0000 | [diff] [blame] | 1899 | // We accept "fnstsw %eax" even though it only writes %ax. |
Benjamin Kramer | 17c836c | 2012-04-27 12:07:43 +0000 | [diff] [blame] | 1900 | def : InstAlias<"fnstsw %eax", (FNSTSW16r)>; |
| 1901 | def : InstAlias<"fnstsw %al" , (FNSTSW16r)>; |
| 1902 | def : InstAlias<"fnstsw" , (FNSTSW16r)>; |
Chris Lattner | dea546b | 2010-11-06 18:58:32 +0000 | [diff] [blame] | 1903 | |
Chris Lattner | 8caa290 | 2010-11-06 07:48:45 +0000 | [diff] [blame] | 1904 | // lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but |
| 1905 | // this is compatible with what GAS does. |
| 1906 | def : InstAlias<"lcall $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; |
| 1907 | def : InstAlias<"ljmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; |
| 1908 | def : InstAlias<"lcall *$dst", (FARCALL32m opaque48mem:$dst)>; |
| 1909 | def : InstAlias<"ljmp *$dst", (FARJMP32m opaque48mem:$dst)>; |
| 1910 | |
Chris Lattner | 9c1dbc6 | 2010-11-06 18:44:26 +0000 | [diff] [blame] | 1911 | // "imul <imm>, B" is an alias for "imul <imm>, B, B". |
| 1912 | def : InstAlias<"imulw $imm, $r", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm)>; |
| 1913 | def : InstAlias<"imulw $imm, $r", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm)>; |
| 1914 | def : InstAlias<"imull $imm, $r", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm)>; |
| 1915 | def : InstAlias<"imull $imm, $r", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm)>; |
| 1916 | def : InstAlias<"imulq $imm, $r",(IMUL64rri32 GR64:$r, GR64:$r,i64i32imm:$imm)>; |
| 1917 | def : InstAlias<"imulq $imm, $r", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm)>; |
| 1918 | |
Chris Lattner | 7e925cc | 2010-11-06 18:52:40 +0000 | [diff] [blame] | 1919 | // inb %dx -> inb %al, %dx |
| 1920 | def : InstAlias<"inb %dx", (IN8rr)>; |
| 1921 | def : InstAlias<"inw %dx", (IN16rr)>; |
| 1922 | def : InstAlias<"inl %dx", (IN32rr)>; |
| 1923 | def : InstAlias<"inb $port", (IN8ri i8imm:$port)>; |
Chris Lattner | dea546b | 2010-11-06 18:58:32 +0000 | [diff] [blame] | 1924 | def : InstAlias<"inw $port", (IN16ri i8imm:$port)>; |
Chris Lattner | 7e925cc | 2010-11-06 18:52:40 +0000 | [diff] [blame] | 1925 | def : InstAlias<"inl $port", (IN32ri i8imm:$port)>; |
| 1926 | |
Chris Lattner | 9c1dbc6 | 2010-11-06 18:44:26 +0000 | [diff] [blame] | 1927 | |
Chris Lattner | 8caa290 | 2010-11-06 07:48:45 +0000 | [diff] [blame] | 1928 | // jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp |
| 1929 | def : InstAlias<"call $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; |
| 1930 | def : InstAlias<"jmp $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; |
| 1931 | def : InstAlias<"callw $seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>; |
| 1932 | def : InstAlias<"jmpw $seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>; |
| 1933 | def : InstAlias<"calll $seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>; |
| 1934 | def : InstAlias<"jmpl $seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>; |
| 1935 | |
Chris Lattner | 04a75ab | 2010-11-06 22:35:34 +0000 | [diff] [blame] | 1936 | // Force mov without a suffix with a segment and mem to prefer the 'l' form of |
| 1937 | // the move. All segment/mem forms are equivalent, this has the shortest |
| 1938 | // encoding. |
| 1939 | def : InstAlias<"mov $mem, $seg", (MOV32sm SEGMENT_REG:$seg, i32mem:$mem)>; |
| 1940 | def : InstAlias<"mov $seg, $mem", (MOV32ms i32mem:$mem, SEGMENT_REG:$seg)>; |
Chris Lattner | 8caa290 | 2010-11-06 07:48:45 +0000 | [diff] [blame] | 1941 | |
Chris Lattner | 9c1dbc6 | 2010-11-06 18:44:26 +0000 | [diff] [blame] | 1942 | // Match 'movq <largeimm>, <reg>' as an alias for movabsq. |
| 1943 | def : InstAlias<"movq $imm, $reg", (MOV64ri GR64:$reg, i64imm:$imm)>; |
| 1944 | |
Chris Lattner | cbf5d74 | 2010-11-21 08:18:57 +0000 | [diff] [blame] | 1945 | // Match 'movq GR64, MMX' as an alias for movd. |
Bill Wendling | eef965f | 2011-04-13 23:36:21 +0000 | [diff] [blame] | 1946 | def : InstAlias<"movq $src, $dst", |
Bill Wendling | c6df988 | 2011-04-14 01:11:51 +0000 | [diff] [blame] | 1947 | (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; |
Bill Wendling | eef965f | 2011-04-13 23:36:21 +0000 | [diff] [blame] | 1948 | def : InstAlias<"movq $src, $dst", |
Bill Wendling | c6df988 | 2011-04-14 01:11:51 +0000 | [diff] [blame] | 1949 | (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; |
Chris Lattner | cbf5d74 | 2010-11-21 08:18:57 +0000 | [diff] [blame] | 1950 | |
Chris Lattner | 8caa290 | 2010-11-06 07:48:45 +0000 | [diff] [blame] | 1951 | // movsd with no operands (as opposed to the SSE scalar move of a double) is an |
| 1952 | // alias for movsl. (as in rep; movsd) |
| 1953 | def : InstAlias<"movsd", (MOVSD)>; |
| 1954 | |
Chris Lattner | efd8dad | 2010-11-01 23:07:52 +0000 | [diff] [blame] | 1955 | // movsx aliases |
Stuart Hastings | 0e29ed0 | 2011-05-20 19:04:40 +0000 | [diff] [blame] | 1956 | def : InstAlias<"movsx $src, $dst", (MOVSX16rr8 GR16:$dst, GR8:$src), 0>; |
| 1957 | def : InstAlias<"movsx $src, $dst", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0>; |
Bill Wendling | d336de3 | 2011-04-14 01:46:37 +0000 | [diff] [blame] | 1958 | def : InstAlias<"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8:$src), 0>; |
| 1959 | def : InstAlias<"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16:$src), 0>; |
| 1960 | def : InstAlias<"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8:$src), 0>; |
| 1961 | def : InstAlias<"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16:$src), 0>; |
| 1962 | def : InstAlias<"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32:$src), 0>; |
Chris Lattner | efd8dad | 2010-11-01 23:07:52 +0000 | [diff] [blame] | 1963 | |
| 1964 | // movzx aliases |
Stuart Hastings | 0e29ed0 | 2011-05-20 19:04:40 +0000 | [diff] [blame] | 1965 | def : InstAlias<"movzx $src, $dst", (MOVZX16rr8 GR16:$dst, GR8:$src), 0>; |
| 1966 | def : InstAlias<"movzx $src, $dst", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0>; |
Bill Wendling | d336de3 | 2011-04-14 01:46:37 +0000 | [diff] [blame] | 1967 | def : InstAlias<"movzx $src, $dst", (MOVZX32rr8 GR32:$dst, GR8:$src), 0>; |
| 1968 | def : InstAlias<"movzx $src, $dst", (MOVZX32rr16 GR32:$dst, GR16:$src), 0>; |
| 1969 | def : InstAlias<"movzx $src, $dst", (MOVZX64rr8_Q GR64:$dst, GR8:$src), 0>; |
| 1970 | def : InstAlias<"movzx $src, $dst", (MOVZX64rr16_Q GR64:$dst, GR16:$src), 0>; |
Chris Lattner | efd8dad | 2010-11-01 23:07:52 +0000 | [diff] [blame] | 1971 | // Note: No GR32->GR64 movzx form. |
| 1972 | |
Chris Lattner | 7e925cc | 2010-11-06 18:52:40 +0000 | [diff] [blame] | 1973 | // outb %dx -> outb %al, %dx |
| 1974 | def : InstAlias<"outb %dx", (OUT8rr)>; |
| 1975 | def : InstAlias<"outw %dx", (OUT16rr)>; |
| 1976 | def : InstAlias<"outl %dx", (OUT32rr)>; |
| 1977 | def : InstAlias<"outb $port", (OUT8ir i8imm:$port)>; |
| 1978 | def : InstAlias<"outw $port", (OUT16ir i8imm:$port)>; |
| 1979 | def : InstAlias<"outl $port", (OUT32ir i8imm:$port)>; |
| 1980 | |
Chris Lattner | 9c1dbc6 | 2010-11-06 18:44:26 +0000 | [diff] [blame] | 1981 | // 'sldt <mem>' can be encoded with either sldtw or sldtq with the same |
| 1982 | // effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity |
| 1983 | // errors, since its encoding is the most compact. |
| 1984 | def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem)>; |
| 1985 | |
Eli Friedman | ec93b6d | 2012-03-05 04:31:54 +0000 | [diff] [blame] | 1986 | // shld/shrd op,op -> shld op, op, CL |
Eli Friedman | 54427e5 | 2012-03-06 19:58:46 +0000 | [diff] [blame] | 1987 | def : InstAlias<"shldw $r2, $r1", (SHLD16rrCL GR16:$r1, GR16:$r2)>; |
| 1988 | def : InstAlias<"shldl $r2, $r1", (SHLD32rrCL GR32:$r1, GR32:$r2)>; |
| 1989 | def : InstAlias<"shldq $r2, $r1", (SHLD64rrCL GR64:$r1, GR64:$r2)>; |
| 1990 | def : InstAlias<"shrdw $r2, $r1", (SHRD16rrCL GR16:$r1, GR16:$r2)>; |
| 1991 | def : InstAlias<"shrdl $r2, $r1", (SHRD32rrCL GR32:$r1, GR32:$r2)>; |
| 1992 | def : InstAlias<"shrdq $r2, $r1", (SHRD64rrCL GR64:$r1, GR64:$r2)>; |
Chris Lattner | d5b2f1a | 2010-11-06 22:25:39 +0000 | [diff] [blame] | 1993 | |
Eli Friedman | 54427e5 | 2012-03-06 19:58:46 +0000 | [diff] [blame] | 1994 | def : InstAlias<"shldw $reg, $mem", (SHLD16mrCL i16mem:$mem, GR16:$reg)>; |
| 1995 | def : InstAlias<"shldl $reg, $mem", (SHLD32mrCL i32mem:$mem, GR32:$reg)>; |
| 1996 | def : InstAlias<"shldq $reg, $mem", (SHLD64mrCL i64mem:$mem, GR64:$reg)>; |
| 1997 | def : InstAlias<"shrdw $reg, $mem", (SHRD16mrCL i16mem:$mem, GR16:$reg)>; |
| 1998 | def : InstAlias<"shrdl $reg, $mem", (SHRD32mrCL i32mem:$mem, GR32:$reg)>; |
| 1999 | def : InstAlias<"shrdq $reg, $mem", (SHRD64mrCL i64mem:$mem, GR64:$reg)>; |
Chris Lattner | d5b2f1a | 2010-11-06 22:25:39 +0000 | [diff] [blame] | 2000 | |
| 2001 | /* FIXME: This is disabled because the asm matcher is currently incapable of |
| 2002 | * matching a fixed immediate like $1. |
Chris Lattner | 1767151 | 2010-11-06 22:05:43 +0000 | [diff] [blame] | 2003 | // "shl X, $1" is an alias for "shl X". |
| 2004 | multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> { |
Chris Lattner | 8c24b0c | 2010-11-06 21:23:40 +0000 | [diff] [blame] | 2005 | def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), |
| 2006 | (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>; |
| 2007 | def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), |
| 2008 | (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>; |
| 2009 | def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), |
| 2010 | (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>; |
| 2011 | def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), |
| 2012 | (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>; |
| 2013 | def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), |
| 2014 | (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>; |
| 2015 | def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), |
| 2016 | (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>; |
| 2017 | def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), |
| 2018 | (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>; |
| 2019 | def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), |
| 2020 | (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>; |
| 2021 | } |
| 2022 | |
Chris Lattner | 1767151 | 2010-11-06 22:05:43 +0000 | [diff] [blame] | 2023 | defm : ShiftRotateByOneAlias<"rcl", "RCL">; |
| 2024 | defm : ShiftRotateByOneAlias<"rcr", "RCR">; |
| 2025 | defm : ShiftRotateByOneAlias<"rol", "ROL">; |
| 2026 | defm : ShiftRotateByOneAlias<"ror", "ROR">; |
Chris Lattner | d5b2f1a | 2010-11-06 22:25:39 +0000 | [diff] [blame] | 2027 | FIXME */ |
Chris Lattner | 8c24b0c | 2010-11-06 21:23:40 +0000 | [diff] [blame] | 2028 | |
Chris Lattner | 5bde734 | 2010-11-06 08:20:59 +0000 | [diff] [blame] | 2029 | // test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms. |
| 2030 | def : InstAlias<"testb $val, $mem", (TEST8rm GR8 :$val, i8mem :$mem)>; |
| 2031 | def : InstAlias<"testw $val, $mem", (TEST16rm GR16:$val, i16mem:$mem)>; |
| 2032 | def : InstAlias<"testl $val, $mem", (TEST32rm GR32:$val, i32mem:$mem)>; |
| 2033 | def : InstAlias<"testq $val, $mem", (TEST64rm GR64:$val, i64mem:$mem)>; |
| 2034 | |
| 2035 | // xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms. |
| 2036 | def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>; |
| 2037 | def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>; |
| 2038 | def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>; |
| 2039 | def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>; |
Craig Topper | 7ea16b0 | 2011-10-06 06:44:41 +0000 | [diff] [blame] | 2040 | |
| 2041 | // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms. |
Craig Topper | 25f6dfd | 2011-10-07 05:35:38 +0000 | [diff] [blame] | 2042 | def : InstAlias<"xchgw %ax, $src", (XCHG16ar GR16:$src)>; |
| 2043 | def : InstAlias<"xchgl %eax, $src", (XCHG32ar GR32:$src)>, Requires<[In32BitMode]>; |
| 2044 | def : InstAlias<"xchgl %eax, $src", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>; |
| 2045 | def : InstAlias<"xchgq %rax, $src", (XCHG64ar GR64:$src)>; |