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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / 45b5f88938f59c495209512b545f289bf2cca90a / . / lib / Target / ARM / ARMISelLowering.h
blob: b46abda94b679cb9e3aa08c9892442e1bb508ba4 [file] [log] [blame]
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef ARMISELLOWERING_H
16#define ARMISELLOWERING_H
17
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]18#include "ARMSubtarget.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]19#include "llvm/Target/TargetLowering.h"
Evan Cheng31446872010-07-23 22:39:59 +0000[diff] [blame]20#include "llvm/Target/TargetRegisterInfo.h"
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]21#include "llvm/CodeGen/FastISel.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]22#include "llvm/CodeGen/SelectionDAG.h"
Bob Wilson1f595bb2009-04-17 19:07:39 +0000[diff] [blame]23#include "llvm/CodeGen/CallingConvLower.h"
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]24#include <vector>
25
26namespace llvm {
27 class ARMConstantPoolValue;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]28
29 namespace ARMISD {
30 // ARM Specific DAG Nodes
31 enum NodeType {
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]32 // Start the numbering where the builtin ops and target ops leave off.
Dan Gohman0ba2bcf2008-09-23 18:42:32 +0000[diff] [blame]33 FIRST_NUMBER = ISD::BUILTIN_OP_END,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]34
35 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
36 // TargetExternalSymbol, and TargetGlobalAddress.
Evan Cheng53519f02011-01-21 18:55:51 +0000[diff] [blame]37 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in
38 // DYN mode.
Evan Cheng5de5d4b2011-01-17 08:03:18 +0000[diff] [blame]39 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
40 // PIC mode.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]41 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]42
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]43 CALL, // Function call.
Evan Cheng277f0742007-06-19 21:05:09 +0000[diff] [blame]44 CALL_PRED, // Function call that's predicable.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]45 CALL_NOLINK, // Function call with branch not branch-and-link.
46 tCALL, // Thumb function call.
47 BRCOND, // Conditional branch.
48 BR_JT, // Jumptable branch.
Evan Cheng5657c012009-07-29 02:18:14 +0000[diff] [blame]49 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]50 RET_FLAG, // Return with a flag operand.
51
52 PIC_ADD, // Add with a PC operand and a PIC label.
53
54 CMP, // ARM compare instructions.
David Goodwinc0309b42009-06-29 15:33:01 +0000[diff] [blame]55 CMPZ, // ARM compare that sets only Z flag.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]56 CMPFP, // ARM VFP compare instruction, sets FPSCR.
57 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
58 FMSTAT, // ARM fmstat instruction.
Evan Chengc892aeb2012-02-23 01:19:06 +0000[diff] [blame]59
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]60 CMOV, // ARM conditional move instructions.
Evan Chengc892aeb2012-02-23 01:19:06 +0000[diff] [blame]61 CAND, // ARM conditional and instructions.
62 COR, // ARM conditional or instructions.
63 CXOR, // ARM conditional xor instructions.
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]64
Evan Cheng218977b2010-07-13 19:27:42 +0000[diff] [blame]65 BCC_i64,
66
Jim Grosbach3482c802010-01-18 19:58:49 +0000[diff] [blame]67 RBIT, // ARM bitreverse instruction
68
Bob Wilson76a312b2010-03-19 22:51:32 +0000[diff] [blame]69 FTOSI, // FP to sint within a FP register.
70 FTOUI, // FP to uint within a FP register.
71 SITOF, // sint to FP within a FP register.
72 UITOF, // uint to FP within a FP register.
73
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]74 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
75 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
76 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]77
Evan Cheng342e3162011-08-30 01:34:54 +0000[diff] [blame]78 ADDC, // Add with carry
79 ADDE, // Add using carry
80 SUBC, // Sub with carry
81 SUBE, // Sub using carry
82
Jim Grosbache5165492009-11-09 00:11:35 +0000[diff] [blame]83 VMOVRRD, // double to two gprs.
84 VMOVDRR, // Two gprs to double.
Lauro Ramos Venancio64f4fa52007-04-27 13:54:47 +0000[diff] [blame]85
Jim Grosbache4ad3872010-10-19 23:27:08 +0000[diff] [blame]86 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
87 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
Jim Grosbach0e0da732009-05-12 23:59:14 +0000[diff] [blame]88
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]89 TC_RETURN, // Tail call return pseudo.
90
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]91 THREAD_POINTER,
92
Evan Cheng86198642009-08-07 00:34:42 +0000[diff] [blame]93 DYN_ALLOC, // Dynamic allocation on the stack.
94
Bob Wilsonf74a4292010-10-30 00:54:37 +0000[diff] [blame]95 MEMBARRIER, // Memory barrier (DMB)
96 MEMBARRIER_MCR, // Memory barrier (MCR)
Evan Chengdfed19f2010-11-03 06:34:55 +0000[diff] [blame]97
98 PRELOAD, // Preload
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]99
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]100 VCEQ, // Vector compare equal.
Owen Andersonc24cb352010-11-08 23:21:22 +0000[diff] [blame]101 VCEQZ, // Vector compare equal to zero.
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]102 VCGE, // Vector compare greater than or equal.
Owen Andersonc24cb352010-11-08 23:21:22 +0000[diff] [blame]103 VCGEZ, // Vector compare greater than or equal to zero.
104 VCLEZ, // Vector compare less than or equal to zero.
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]105 VCGEU, // Vector compare unsigned greater than or equal.
106 VCGT, // Vector compare greater than.
Owen Andersonc24cb352010-11-08 23:21:22 +0000[diff] [blame]107 VCGTZ, // Vector compare greater than zero.
108 VCLTZ, // Vector compare less than zero.
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]109 VCGTU, // Vector compare unsigned greater than.
110 VTST, // Vector test bits.
111
112 // Vector shift by immediate:
113 VSHL, // ...left
114 VSHRs, // ...right (signed)
115 VSHRu, // ...right (unsigned)
116 VSHLLs, // ...left long (signed)
117 VSHLLu, // ...left long (unsigned)
118 VSHLLi, // ...left long (with maximum shift count)
119 VSHRN, // ...right narrow
120
121 // Vector rounding shift by immediate:
122 VRSHRs, // ...right (signed)
123 VRSHRu, // ...right (unsigned)
124 VRSHRN, // ...right narrow
125
126 // Vector saturating shift by immediate:
127 VQSHLs, // ...left (signed)
128 VQSHLu, // ...left (unsigned)
129 VQSHLsu, // ...left (signed to unsigned)
130 VQSHRNs, // ...right narrow (signed)
131 VQSHRNu, // ...right narrow (unsigned)
132 VQSHRNsu, // ...right narrow (signed to unsigned)
133
134 // Vector saturating rounding shift by immediate:
135 VQRSHRNs, // ...right narrow (signed)
136 VQRSHRNu, // ...right narrow (unsigned)
137 VQRSHRNsu, // ...right narrow (signed to unsigned)
138
139 // Vector shift and insert:
140 VSLI, // ...left
141 VSRI, // ...right
142
143 // Vector get lane (VMOV scalar to ARM core register)
144 // (These are used for 8- and 16-bit element types only.)
145 VGETLANEu, // zero-extend vector extract element
146 VGETLANEs, // sign-extend vector extract element
147
Bob Wilson7e3f0d22010-07-14 06:31:50 +0000[diff] [blame]148 // Vector move immediate and move negated immediate:
Bob Wilsoncba270d2010-07-13 21:16:48 +0000[diff] [blame]149 VMOVIMM,
Bob Wilson7e3f0d22010-07-14 06:31:50 +0000[diff] [blame]150 VMVNIMM,
151
Evan Chengeaa192a2011-11-15 02:12:34 +0000[diff] [blame]152 // Vector move f32 immediate:
153 VMOVFPIMM,
154
Bob Wilson7e3f0d22010-07-14 06:31:50 +0000[diff] [blame]155 // Vector duplicate:
Bob Wilsonc1d287b2009-08-14 05:13:08 +0000[diff] [blame]156 VDUP,
Bob Wilson0ce37102009-08-14 05:08:32 +0000[diff] [blame]157 VDUPLANE,
Bob Wilsona599bff2009-08-04 00:36:16 +0000[diff] [blame]158
Bob Wilsond8e17572009-08-12 22:31:50 +0000[diff] [blame]159 // Vector shuffles:
Bob Wilsonde95c1b82009-08-19 17:03:43 +0000[diff] [blame]160 VEXT, // extract
Bob Wilsond8e17572009-08-12 22:31:50 +0000[diff] [blame]161 VREV64, // reverse elements within 64-bit doublewords
162 VREV32, // reverse elements within 32-bit words
Anton Korobeynikov1c8e5812009-08-21 12:41:24 +0000[diff] [blame]163 VREV16, // reverse elements within 16-bit halfwords
Bob Wilsonc692cb72009-08-21 20:54:19 +0000[diff] [blame]164 VZIP, // zip (interleave)
165 VUZP, // unzip (deinterleave)
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000[diff] [blame]166 VTRN, // transpose
Bill Wendling69a05a72011-03-14 23:02:38 +0000[diff] [blame]167 VTBL1, // 1-register shuffle with mask
168 VTBL2, // 2-register shuffle with mask
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000[diff] [blame]169
Bob Wilsond0b69cf2010-09-01 23:50:19 +0000[diff] [blame]170 // Vector multiply long:
171 VMULLs, // ...signed
172 VMULLu, // ...unsigned
173
Bob Wilson40cbe7d2010-06-04 00:04:02 +0000[diff] [blame]174 // Operands of the standard BUILD_VECTOR node are not legalized, which
175 // is fine if BUILD_VECTORs are always lowered to shuffles or other
176 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
177 // operands need to be legalized. Define an ARM-specific version of
178 // BUILD_VECTOR for this purpose.
179 BUILD_VECTOR,
180
Bob Wilson9f6c4c12010-02-18 06:05:53 +0000[diff] [blame]181 // Floating-point max and min:
182 FMAX,
Jim Grosbach469bbdb2010-07-16 23:05:05 +0000[diff] [blame]183 FMIN,
184
185 // Bit-field insert
Owen Andersond9668172010-11-03 22:44:51 +0000[diff] [blame]186 BFI,
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]187
Owen Andersond9668172010-11-03 22:44:51 +0000[diff] [blame]188 // Vector OR with immediate
Owen Anderson080c0922010-11-05 19:27:46 +0000[diff] [blame]189 VORRIMM,
190 // Vector AND with NOT of immediate
Bob Wilsonb1dfa7a2010-11-28 06:51:26 +0000[diff] [blame]191 VBICIMM,
192
Cameron Zwarichc0e6d782011-03-30 23:01:21 +0000[diff] [blame]193 // Vector bitwise select
194 VBSL,
195
Bob Wilsonb1dfa7a2010-11-28 06:51:26 +0000[diff] [blame]196 // Vector load N-element structure to all lanes:
197 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
198 VLD3DUP,
Bob Wilson1c3ef902011-02-07 17:43:21 +0000[diff] [blame]199 VLD4DUP,
200
201 // NEON loads with post-increment base updates:
202 VLD1_UPD,
203 VLD2_UPD,
204 VLD3_UPD,
205 VLD4_UPD,
206 VLD2LN_UPD,
207 VLD3LN_UPD,
208 VLD4LN_UPD,
209 VLD2DUP_UPD,
210 VLD3DUP_UPD,
211 VLD4DUP_UPD,
212
213 // NEON stores with post-increment base updates:
214 VST1_UPD,
215 VST2_UPD,
216 VST3_UPD,
217 VST4_UPD,
218 VST2LN_UPD,
219 VST3LN_UPD,
Eli Friedman2bdffe42011-08-31 00:31:29 +0000[diff] [blame]220 VST4LN_UPD,
221
222 // 64-bit atomic ops (value split into two registers)
223 ATOMADD64_DAG,
224 ATOMSUB64_DAG,
225 ATOMOR64_DAG,
226 ATOMXOR64_DAG,
227 ATOMAND64_DAG,
228 ATOMNAND64_DAG,
229 ATOMSWAP64_DAG,
230 ATOMCMPXCHG64_DAG
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]231 };
232 }
233
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]234 /// Define some predicates that are used for node matching.
235 namespace ARM {
Jim Grosbach469bbdb2010-07-16 23:05:05 +0000[diff] [blame]236 bool isBitFieldInvertedMask(unsigned v);
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]237 }
238
Bob Wilson261f2a22009-05-20 16:30:25 +0000[diff] [blame]239 //===--------------------------------------------------------------------===//
Dale Johannesen80dae192007-03-20 00:30:56 +0000[diff] [blame]240 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]241
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]242 class ARMTargetLowering : public TargetLowering {
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]243 public:
Dan Gohman61e729e2007-08-02 21:21:54 +0000[diff] [blame]244 explicit ARMTargetLowering(TargetMachine &TM);
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]245
Jim Grosbache1102ca2010-07-19 17:20:38 +0000[diff] [blame]246 virtual unsigned getJumpTableEncoding(void) const;
247
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]248 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
Duncan Sands1607f052008-12-01 11:39:25 +0000[diff] [blame]249
250 /// ReplaceNodeResults - Replace the results of node with an illegal result
251 /// type with new values built out of custom code.
252 ///
253 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]254 SelectionDAG &DAG) const;
Duncan Sands1607f052008-12-01 11:39:25 +0000[diff] [blame]255
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]256 virtual const char *getTargetNodeName(unsigned Opcode) const;
257
Duncan Sands28b77e92011-09-06 19:07:46 +0000[diff] [blame]258 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
259 virtual EVT getSetCCResultType(EVT VT) const;
260
Dan Gohmanaf1d8ca2010-05-01 00:01:06 +0000[diff] [blame]261 virtual MachineBasicBlock *
262 EmitInstrWithCustomInserter(MachineInstr *MI,
263 MachineBasicBlock *MBB) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]264
Evan Cheng37fefc22011-08-30 19:09:48 +0000[diff] [blame]265 virtual void
266 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
267
Evan Chenge721f5c2011-07-13 00:42:17 +0000[diff] [blame]268 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
Evan Cheng31959b12011-02-02 01:06:55 +0000[diff] [blame]269 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
270
271 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
272
Bill Wendlingaf566342009-08-15 21:21:19 +0000[diff] [blame]273 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
274 /// unaligned memory accesses. of the specified type.
Bill Wendlingaf566342009-08-15 21:21:19 +0000[diff] [blame]275 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
276
Lang Hames1a1d1fc2011-11-02 22:52:45 +0000[diff] [blame]277 virtual EVT getOptimalMemOpType(uint64_t Size,
278 unsigned DstAlign, unsigned SrcAlign,
Lang Hamesa1e78882011-11-02 23:37:04 +0000[diff] [blame]279 bool IsZeroVal,
Lang Hames1a1d1fc2011-11-02 22:52:45 +0000[diff] [blame]280 bool MemcpyStrSrc,
281 MachineFunction &MF) const;
282
Chris Lattnerc9addb72007-03-30 23:15:24 +0000[diff] [blame]283 /// isLegalAddressingMode - Return true if the addressing mode represented
284 /// by AM is legal for this target, for a load/store of the specified type.
Chris Lattnerdb125cf2011-07-18 04:54:35 +0000[diff] [blame]285 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
Evan Chenge6c835f2009-08-14 20:09:37 +0000[diff] [blame]286 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]287
Evan Cheng77e47512009-11-11 19:05:52 +0000[diff] [blame]288 /// isLegalICmpImmediate - Return true if the specified immediate is legal
Jim Grosbach18f30e62010-06-02 21:53:11 +0000[diff] [blame]289 /// icmp immediate, that is the target has icmp instructions which can
290 /// compare a register against the immediate without having to materialize
291 /// the immediate into a register.
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]292 virtual bool isLegalICmpImmediate(int64_t Imm) const;
Evan Cheng77e47512009-11-11 19:05:52 +0000[diff] [blame]293
Dan Gohmancca82142011-05-03 00:46:49 +0000[diff] [blame]294 /// isLegalAddImmediate - Return true if the specified immediate is legal
295 /// add immediate, that is the target has add instructions which can
296 /// add a register and the immediate without having to materialize
297 /// the immediate into a register.
298 virtual bool isLegalAddImmediate(int64_t Imm) const;
299
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]300 /// getPreIndexedAddressParts - returns true by value, base pointer and
301 /// offset pointer and addressing mode by reference if the node's address
302 /// can be legally represented as pre-indexed load / store address.
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]303 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
304 SDValue &Offset,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]305 ISD::MemIndexedMode &AM,
Dan Gohman73e09142009-01-15 16:29:45 +0000[diff] [blame]306 SelectionDAG &DAG) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]307
308 /// getPostIndexedAddressParts - returns true by value, base pointer and
309 /// offset pointer and addressing mode by reference if this node can be
310 /// combined with a load / store to form a post-indexed load / store.
311 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]312 SDValue &Base, SDValue &Offset,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]313 ISD::MemIndexedMode &AM,
Dan Gohman73e09142009-01-15 16:29:45 +0000[diff] [blame]314 SelectionDAG &DAG) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]315
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]316 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
Dan Gohman977a76f2008-02-13 22:28:48 +0000[diff] [blame]317 const APInt &Mask,
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]318 APInt &KnownZero,
Dan Gohmanfd29e0e2008-02-13 00:35:47 +0000[diff] [blame]319 APInt &KnownOne,
Dan Gohmanea859be2007-06-22 14:59:07 +0000[diff] [blame]320 const SelectionDAG &DAG,
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]321 unsigned Depth) const;
Bill Wendlingaf566342009-08-15 21:21:19 +0000[diff] [blame]322
323
Evan Cheng55d42002011-01-08 01:24:27 +0000[diff] [blame]324 virtual bool ExpandInlineAsm(CallInst *CI) const;
325
Chris Lattner4234f572007-03-25 02:14:49 +0000[diff] [blame]326 ConstraintType getConstraintType(const std::string &Constraint) const;
John Thompson44ab89e2010-10-29 17:29:13 +0000[diff] [blame]327
328 /// Examine constraint string and operand type and determine a weight value.
329 /// The operand object must already have been set up with the operand type.
330 ConstraintWeight getSingleConstraintMatchWeight(
331 AsmOperandInfo &info, const char *constraint) const;
332
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]333 std::pair<unsigned, const TargetRegisterClass*>
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]334 getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]335 EVT VT) const;
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]336
Bob Wilsonbf6396b2009-04-01 17:58:54 +0000[diff] [blame]337 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
338 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
339 /// true it means one of the asm constraint of the inline asm instruction
340 /// being processed is 'm'.
341 virtual void LowerAsmOperandForConstraint(SDValue Op,
Eric Christopher100c8332011-06-02 23:16:42 +0000[diff] [blame]342 std::string &Constraint,
Bob Wilsonbf6396b2009-04-01 17:58:54 +0000[diff] [blame]343 std::vector<SDValue> &Ops,
344 SelectionDAG &DAG) const;
Jim Grosbach6aa71972009-05-13 22:32:43 +0000[diff] [blame]345
Dan Gohman419e4f92010-05-11 16:21:03 +0000[diff] [blame]346 const ARMSubtarget* getSubtarget() const {
Dan Gohman707e0182008-04-12 04:36:06 +0000[diff] [blame]347 return Subtarget;
Rafael Espindolaf1ba1ca2007-11-05 23:12:20 +0000[diff] [blame]348 }
349
Evan Cheng06b666c2010-05-15 02:18:07 +0000[diff] [blame]350 /// getRegClassFor - Return the register class that should be used for the
351 /// specified value type.
Craig Topper44d23822012-02-22 05:59:10 +0000[diff] [blame]352 virtual const TargetRegisterClass *getRegClassFor(EVT VT) const;
Evan Cheng06b666c2010-05-15 02:18:07 +0000[diff] [blame]353
Anton Korobeynikovcec36f42010-07-24 21:52:08 +0000[diff] [blame]354 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
355 /// be used for loads / stores from the global.
356 virtual unsigned getMaximalGlobalOffset() const;
357
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]358 /// createFastISel - This method returns a target specific FastISel object,
359 /// or null if the target does not support "fast" ISel.
360 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
361
Evan Cheng1cc39842010-05-20 23:26:43 +0000[diff] [blame]362 Sched::Preference getSchedulingPreference(SDNode *N) const;
363
Anton Korobeynikovd0ac2342009-08-21 12:40:07 +0000[diff] [blame]364 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
Anton Korobeynikov48e19352009-09-23 19:04:09 +0000[diff] [blame]365 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
Evan Cheng39382422009-10-28 01:44:26 +0000[diff] [blame]366
367 /// isFPImmLegal - Returns true if the target can instruction select the
368 /// specified FP immediate natively. If false, the legalizer will
369 /// materialize the FP immediate as a load from a constant pool.
370 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
371
Bob Wilson65ffec42010-09-21 17:56:22 +0000[diff] [blame]372 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
373 const CallInst &I,
374 unsigned Intrinsic) const;
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]375 protected:
Evan Cheng4f6b4672010-07-21 06:09:07 +0000[diff] [blame]376 std::pair<const TargetRegisterClass*, uint8_t>
377 findRepresentativeClass(EVT VT) const;
Evan Chengd70f57b2010-07-19 22:15:08 +0000[diff] [blame]378
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]379 private:
380 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
381 /// make the right decision when generating code for different targets.
382 const ARMSubtarget *Subtarget;
383
Evan Cheng31446872010-07-23 22:39:59 +0000[diff] [blame]384 const TargetRegisterInfo *RegInfo;
385
Evan Cheng3ef1c872010-09-10 01:29:16 +0000[diff] [blame]386 const InstrItineraryData *Itins;
387
Bob Wilsond2559bf2009-07-13 18:11:36 +0000[diff] [blame]388 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]389 ///
390 unsigned ARMPCLabelIndex;
391
Owen Andersone50ed302009-08-10 22:56:29 +0000[diff] [blame]392 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
393 void addDRTypeForNEON(EVT VT);
394 void addQRTypeForNEON(EVT VT);
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]395
396 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]397 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]398 SDValue Chain, SDValue &Arg,
399 RegsToPassVector &RegsToPass,
400 CCValAssign &VA, CCValAssign &NextVA,
401 SDValue &StackPtr,
402 SmallVector<SDValue, 8> &MemOpChains,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]403 ISD::ArgFlagsTy Flags) const;
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]404 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]405 SDValue &Root, SelectionDAG &DAG,
406 DebugLoc dl) const;
Bob Wilson5bafff32009-06-22 23:27:02 +0000[diff] [blame]407
Jim Grosbach18f30e62010-06-02 21:53:11 +0000[diff] [blame]408 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
409 bool isVarArg) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]410 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
411 DebugLoc dl, SelectionDAG &DAG,
412 const CCValAssign &VA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]413 ISD::ArgFlagsTy Flags) const;
Jim Grosbach23ff7cf2010-05-26 20:22:18 +0000[diff] [blame]414 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5eb19512010-05-22 01:06:18 +0000[diff] [blame]415 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbacha87ded22010-02-08 23:22:00 +0000[diff] [blame]416 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]417 const ARMSubtarget *Subtarget) const;
418 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
419 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
420 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
421 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]422 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]423 SelectionDAG &DAG) const;
Dan Gohman475871a2008-07-27 21:46:04 +0000[diff] [blame]424 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]425 SelectionDAG &DAG) const;
426 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
427 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
Bill Wendlingde2b1512010-08-11 08:43:16 +0000[diff] [blame]428 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]429 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
430 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng515fe3a2010-07-08 02:08:50 +0000[diff] [blame]431 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng2457f2c2010-05-22 01:47:14 +0000[diff] [blame]432 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]433 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]434 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
435 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
Nate Begemand1fb5832010-08-03 21:31:55 +0000[diff] [blame]436 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
Lang Hames45b5f882012-03-15 18:49:02 +0000[diff] [blame^]437 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
438 const ARMSubtarget *ST) const;
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]439 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
Bob Wilson11a1dff2011-01-07 21:37:30 +0000[diff] [blame]440 const ARMSubtarget *ST) const;
441
442 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
Rafael Espindola7b73a5d2007-10-19 14:35:17 +0000[diff] [blame]443
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]444 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]445 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]446 const SmallVectorImpl<ISD::InputArg> &Ins,
447 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]448 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]449
450 virtual SDValue
451 LowerFormalArguments(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]452 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]453 const SmallVectorImpl<ISD::InputArg> &Ins,
454 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]455 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]456
Stuart Hastingsc7315872011-04-20 16:47:52 +0000[diff] [blame]457 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
458 DebugLoc dl, SDValue &Chain, unsigned ArgOffset)
459 const;
460
461 void computeRegArea(CCState &CCInfo, MachineFunction &MF,
462 unsigned &VARegSize, unsigned &VARegSaveSize) const;
463
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]464 virtual SDValue
Evan Cheng022d9e12010-02-02 23:55:14 +0000[diff] [blame]465 LowerCall(SDValue Chain, SDValue Callee,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]466 CallingConv::ID CallConv, bool isVarArg,
Evan Cheng4bfcd4a2012-02-28 18:51:51 +0000[diff] [blame]467 bool doesNotRet, bool &isTailCall,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]468 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]469 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]470 const SmallVectorImpl<ISD::InputArg> &Ins,
471 DebugLoc dl, SelectionDAG &DAG,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]472 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]473
Stuart Hastingsf222e592011-02-28 17:17:53 +0000[diff] [blame]474 /// HandleByVal - Target-specific cleanup for ByVal support.
Stuart Hastingsc7315872011-04-20 16:47:52 +0000[diff] [blame]475 virtual void HandleByVal(CCState *, unsigned &) const;
Stuart Hastingsf222e592011-02-28 17:17:53 +0000[diff] [blame]476
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]477 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
478 /// for tail call optimization. Targets which want to do tail call
479 /// optimization should implement this function.
480 bool IsEligibleForTailCallOptimization(SDValue Callee,
481 CallingConv::ID CalleeCC,
482 bool isVarArg,
483 bool isCalleeStructRet,
484 bool isCallerStructRet,
485 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]486 const SmallVectorImpl<SDValue> &OutVals,
Dale Johannesen51e28e62010-06-03 21:09:53 +0000[diff] [blame]487 const SmallVectorImpl<ISD::InputArg> &Ins,
488 SelectionDAG& DAG) const;
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]489 virtual SDValue
490 LowerReturn(SDValue Chain,
Sandeep Patel65c3c8f2009-09-02 08:44:58 +0000[diff] [blame]491 CallingConv::ID CallConv, bool isVarArg,
Dan Gohman98ca4f22009-08-05 01:29:28 +0000[diff] [blame]492 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanc9403652010-07-07 15:54:55 +0000[diff] [blame]493 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohmand858e902010-04-17 15:26:15 +0000[diff] [blame]494 DebugLoc dl, SelectionDAG &DAG) const;
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]495
Evan Cheng3d2125c2010-11-30 23:55:39 +0000[diff] [blame]496 virtual bool isUsedByReturnOnly(SDNode *N) const;
497
Evan Cheng485fafc2011-03-21 01:19:09 +0000[diff] [blame]498 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
499
Evan Cheng06b53c02009-11-12 07:13:11 +0000[diff] [blame]500 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
Evan Cheng218977b2010-07-13 19:27:42 +0000[diff] [blame]501 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
502 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
503 SelectionDAG &DAG, DebugLoc dl) const;
Bob Wilson79f56c92011-03-08 01:17:20 +0000[diff] [blame]504 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
Evan Cheng218977b2010-07-13 19:27:42 +0000[diff] [blame]505
506 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5278eb82009-12-11 01:42:04 +0000[diff] [blame]507
Jim Grosbache801dc42009-12-12 01:40:06 +0000[diff] [blame]508 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
509 MachineBasicBlock *BB,
510 unsigned Size) const;
511 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
512 MachineBasicBlock *BB,
513 unsigned Size,
514 unsigned BinOpcode) const;
Eli Friedman2bdffe42011-08-31 00:31:29 +0000[diff] [blame]515 MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI,
516 MachineBasicBlock *BB,
517 unsigned Op1,
518 unsigned Op2,
Eli Friedman4d3f3292011-08-31 17:52:22 +0000[diff] [blame]519 bool NeedsCarry = false,
520 bool IsCmpxchg = false) const;
Jim Grosbachf7da8822011-04-26 19:44:18 +0000[diff] [blame]521 MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI,
522 MachineBasicBlock *BB,
523 unsigned Size,
524 bool signExtend,
525 ARMCC::CondCodes Cond) const;
Jim Grosbach5278eb82009-12-11 01:42:04 +0000[diff] [blame]526
Bill Wendlinge29fa1d2011-10-06 22:18:16 +0000[diff] [blame]527 void SetupEntryBlockForSjLj(MachineInstr *MI,
528 MachineBasicBlock *MBB,
529 MachineBasicBlock *DispatchBB, int FI) const;
530
Bill Wendlingf7e4aef2011-10-03 21:25:38 +0000[diff] [blame]531 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI,
532 MachineBasicBlock *MBB) const;
533
Andrew Trick1c3af772011-04-23 03:55:32 +0000[diff] [blame]534 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]535 };
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]536
Owen Anderson36fa3ea2010-11-05 21:57:54 +0000[diff] [blame]537 enum NEONModImmType {
538 VMOVModImm,
539 VMVNModImm,
540 OtherModImm
541 };
Andrew Trick5adfba22011-04-23 03:24:11 +0000[diff] [blame]542
543
Eric Christopherab695882010-07-21 22:26:11 +0000[diff] [blame]544 namespace ARM {
545 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
546 }
Evan Chenga8e29892007-01-19 07:51:42 +0000[diff] [blame]547}
548
549#endif // ARMISELLOWERING_H