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Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Chris Lattner8c4d88d2004-09-30 01:54:45 +000019#define DEBUG_TYPE "spiller"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000022#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000023#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/SSARegMap.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000025#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000026#include "llvm/Target/TargetInstrInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000027#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000029#include "llvm/Support/Compiler.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000030#include "llvm/ADT/Statistic.h"
31#include "llvm/ADT/STLExtras.h"
Chris Lattner27f29162004-10-26 15:35:58 +000032#include <algorithm>
Chris Lattner2c2c6c62006-01-22 23:41:00 +000033#include <iostream>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000034using namespace llvm;
35
36namespace {
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000037 static Statistic<> NumSpills("spiller", "Number of register spills");
38 static Statistic<> NumStores("spiller", "Number of stores added");
39 static Statistic<> NumLoads ("spiller", "Number of loads added");
40 static Statistic<> NumReused("spiller", "Number of values reused");
41 static Statistic<> NumDSE ("spiller", "Number of dead stores elided");
42 static Statistic<> NumDCE ("spiller", "Number of copies elided");
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000043
Chris Lattner8c4d88d2004-09-30 01:54:45 +000044 enum SpillerName { simple, local };
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +000045
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000046 static cl::opt<SpillerName>
Chris Lattner8c4d88d2004-09-30 01:54:45 +000047 SpillerOpt("spiller",
Chris Lattner7fb64342004-10-01 19:04:51 +000048 cl::desc("Spiller to use: (default: local)"),
Chris Lattner8c4d88d2004-09-30 01:54:45 +000049 cl::Prefix,
50 cl::values(clEnumVal(simple, " simple spiller"),
51 clEnumVal(local, " local spiller"),
52 clEnumValEnd),
Chris Lattner7fb64342004-10-01 19:04:51 +000053 cl::init(local));
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000054}
55
Chris Lattner8c4d88d2004-09-30 01:54:45 +000056//===----------------------------------------------------------------------===//
57// VirtRegMap implementation
58//===----------------------------------------------------------------------===//
59
Chris Lattner29268692006-09-05 02:12:02 +000060VirtRegMap::VirtRegMap(MachineFunction &mf)
61 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
62 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT) {
63 grow();
64}
65
Chris Lattner8c4d88d2004-09-30 01:54:45 +000066void VirtRegMap::grow() {
Chris Lattner7f690e62004-09-30 02:15:18 +000067 Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg());
68 Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg());
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000069}
70
Chris Lattner8c4d88d2004-09-30 01:54:45 +000071int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
72 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000073 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000074 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000075 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
76 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
77 RC->getAlignment());
78 Virt2StackSlotMap[virtReg] = frameIndex;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000079 ++NumSpills;
80 return frameIndex;
81}
82
83void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
84 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000085 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000086 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000087 Virt2StackSlotMap[virtReg] = frameIndex;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +000088}
89
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000090void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
Chris Lattner35f27052006-05-01 21:16:03 +000091 unsigned OpNo, MachineInstr *NewMI) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000092 // Move previous memory references folded to new instruction.
93 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +000094 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000095 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
96 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +000097 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +000098 }
Chris Lattnerdbea9732004-09-30 16:35:08 +000099
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000100 ModRef MRInfo;
Chris Lattner29268692006-09-05 02:12:02 +0000101 if (OpNo < 2 && TII.isTwoAddrInstr(OldMI->getOpcode())) {
102 // Folded a two-address operand.
103 MRInfo = isModRef;
104 } else if (OldMI->getOperand(OpNo).isDef()) {
105 MRInfo = isMod;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000106 } else {
Chris Lattner29268692006-09-05 02:12:02 +0000107 MRInfo = isRef;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000108 }
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000109
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000110 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000111 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000112}
113
Chris Lattner7f690e62004-09-30 02:15:18 +0000114void VirtRegMap::print(std::ostream &OS) const {
115 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000116
Chris Lattner7f690e62004-09-30 02:15:18 +0000117 OS << "********** REGISTER MAP **********\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000118 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000119 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
120 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
121 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
Misha Brukmanedf128a2005-04-21 22:36:52 +0000122
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000123 }
124
125 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000126 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
127 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
128 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
129 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000130}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000131
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000132void VirtRegMap::dump() const { print(std::cerr); }
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000133
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000134
135//===----------------------------------------------------------------------===//
136// Simple Spiller Implementation
137//===----------------------------------------------------------------------===//
138
139Spiller::~Spiller() {}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000140
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000141namespace {
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000142 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
Chris Lattner35f27052006-05-01 21:16:03 +0000143 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000144 };
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000145}
146
Chris Lattner35f27052006-05-01 21:16:03 +0000147bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000148 DEBUG(std::cerr << "********** REWRITE MACHINE CODE **********\n");
149 DEBUG(std::cerr << "********** Function: "
150 << MF.getFunction()->getName() << '\n');
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000151 const TargetMachine &TM = MF.getTarget();
152 const MRegisterInfo &MRI = *TM.getRegisterInfo();
153 bool *PhysRegsUsed = MF.getUsedPhysregs();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000154
Chris Lattner4ea1b822004-09-30 02:33:48 +0000155 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
156 // each vreg once (in the case where a spilled vreg is used by multiple
157 // operands). This is always smaller than the number of operands to the
158 // current machine instr, so it should be small.
159 std::vector<unsigned> LoadedRegs;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000160
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000161 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
162 MBBI != E; ++MBBI) {
163 DEBUG(std::cerr << MBBI->getBasicBlock()->getName() << ":\n");
164 MachineBasicBlock &MBB = *MBBI;
165 for (MachineBasicBlock::iterator MII = MBB.begin(),
166 E = MBB.end(); MII != E; ++MII) {
167 MachineInstr &MI = *MII;
168 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000169 MachineOperand &MO = MI.getOperand(i);
Chris Lattner886dd912005-04-04 21:35:34 +0000170 if (MO.isRegister() && MO.getReg())
171 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
172 unsigned VirtReg = MO.getReg();
173 unsigned PhysReg = VRM.getPhys(VirtReg);
174 if (VRM.hasStackSlot(VirtReg)) {
175 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000176 const TargetRegisterClass* RC =
177 MF.getSSARegMap()->getRegClass(VirtReg);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000178
Chris Lattner886dd912005-04-04 21:35:34 +0000179 if (MO.isUse() &&
180 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
181 == LoadedRegs.end()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000182 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000183 LoadedRegs.push_back(VirtReg);
184 ++NumLoads;
185 DEBUG(std::cerr << '\t' << *prior(MII));
186 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000187
Chris Lattner886dd912005-04-04 21:35:34 +0000188 if (MO.isDef()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000189 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000190 ++NumStores;
191 }
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000192 }
Chris Lattner886dd912005-04-04 21:35:34 +0000193 PhysRegsUsed[PhysReg] = true;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000194 MI.getOperand(i).setReg(PhysReg);
Chris Lattner886dd912005-04-04 21:35:34 +0000195 } else {
196 PhysRegsUsed[MO.getReg()] = true;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000197 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000198 }
Chris Lattner886dd912005-04-04 21:35:34 +0000199
Chris Lattner477e4552004-09-30 16:10:45 +0000200 DEBUG(std::cerr << '\t' << MI);
Chris Lattner4ea1b822004-09-30 02:33:48 +0000201 LoadedRegs.clear();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000202 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000203 }
204 return true;
205}
206
207//===----------------------------------------------------------------------===//
208// Local Spiller Implementation
209//===----------------------------------------------------------------------===//
210
211namespace {
Chris Lattner7fb64342004-10-01 19:04:51 +0000212 /// LocalSpiller - This spiller does a simple pass over the machine basic
213 /// block to attempt to keep spills in registers as much as possible for
214 /// blocks that have low register pressure (the vreg may be spilled due to
215 /// register pressure in other blocks).
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000216 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000217 const MRegisterInfo *MRI;
Chris Lattner7fb64342004-10-01 19:04:51 +0000218 const TargetInstrInfo *TII;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000219 public:
Chris Lattner35f27052006-05-01 21:16:03 +0000220 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000221 MRI = MF.getTarget().getRegisterInfo();
222 TII = MF.getTarget().getInstrInfo();
223 DEBUG(std::cerr << "\n**** Local spiller rewriting function '"
224 << MF.getFunction()->getName() << "':\n");
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000225
Chris Lattner7fb64342004-10-01 19:04:51 +0000226 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
227 MBB != E; ++MBB)
228 RewriteMBB(*MBB, VRM);
229 return true;
230 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000231 private:
Chris Lattner35f27052006-05-01 21:16:03 +0000232 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM);
Chris Lattner7fb64342004-10-01 19:04:51 +0000233 void ClobberPhysReg(unsigned PR, std::map<int, unsigned> &SpillSlots,
Chris Lattner07cf1412006-02-03 00:36:31 +0000234 std::multimap<unsigned, int> &PhysRegs);
Chris Lattner7fb64342004-10-01 19:04:51 +0000235 void ClobberPhysRegOnly(unsigned PR, std::map<int, unsigned> &SpillSlots,
Chris Lattner07cf1412006-02-03 00:36:31 +0000236 std::multimap<unsigned, int> &PhysRegs);
237 void ModifyStackSlot(int Slot, std::map<int, unsigned> &SpillSlots,
238 std::multimap<unsigned, int> &PhysRegs);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000239 };
240}
241
Chris Lattner66cf80f2006-02-03 23:13:58 +0000242/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
243/// top down, keep track of which spills slots are available in each register.
Chris Lattner593c9582006-02-03 23:28:46 +0000244///
245/// Note that not all physregs are created equal here. In particular, some
246/// physregs are reloads that we are allowed to clobber or ignore at any time.
247/// Other physregs are values that the register allocated program is using that
248/// we cannot CHANGE, but we can read if we like. We keep track of this on a
249/// per-stack-slot basis as the low bit in the value of the SpillSlotsAvailable
250/// entries. The predicate 'canClobberPhysReg()' checks this bit and
251/// addAvailable sets it if.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000252namespace {
253class VISIBILITY_HIDDEN AvailableSpills {
Chris Lattner66cf80f2006-02-03 23:13:58 +0000254 const MRegisterInfo *MRI;
255 const TargetInstrInfo *TII;
256
257 // SpillSlotsAvailable - This map keeps track of all of the spilled virtual
258 // register values that are still available, due to being loaded or stored to,
259 // but not invalidated yet.
260 std::map<int, unsigned> SpillSlotsAvailable;
261
262 // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating
263 // which stack slot values are currently held by a physreg. This is used to
264 // invalidate entries in SpillSlotsAvailable when a physreg is modified.
265 std::multimap<unsigned, int> PhysRegsAvailable;
266
267 void ClobberPhysRegOnly(unsigned PhysReg);
268public:
269 AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
270 : MRI(mri), TII(tii) {
271 }
272
273 /// getSpillSlotPhysReg - If the specified stack slot is available in a
274 /// physical register, return that PhysReg, otherwise return 0.
275 unsigned getSpillSlotPhysReg(int Slot) const {
276 std::map<int, unsigned>::const_iterator I = SpillSlotsAvailable.find(Slot);
277 if (I != SpillSlotsAvailable.end())
Chris Lattner593c9582006-02-03 23:28:46 +0000278 return I->second >> 1; // Remove the CanClobber bit.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000279 return 0;
280 }
Chris Lattner540fec62006-02-25 01:51:33 +0000281
282 const MRegisterInfo *getRegInfo() const { return MRI; }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000283
284 /// addAvailable - Mark that the specified stack slot is available in the
Chris Lattner593c9582006-02-03 23:28:46 +0000285 /// specified physreg. If CanClobber is true, the physreg can be modified at
286 /// any time without changing the semantics of the program.
287 void addAvailable(int Slot, unsigned Reg, bool CanClobber = true) {
Chris Lattner86662492006-02-03 23:50:46 +0000288 // If this stack slot is thought to be available in some other physreg,
289 // remove its record.
290 ModifyStackSlot(Slot);
291
Chris Lattner66cf80f2006-02-03 23:13:58 +0000292 PhysRegsAvailable.insert(std::make_pair(Reg, Slot));
Jeff Cohen003cecb2006-02-04 03:27:39 +0000293 SpillSlotsAvailable[Slot] = (Reg << 1) | (unsigned)CanClobber;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000294
295 DEBUG(std::cerr << "Remembering SS#" << Slot << " in physreg "
296 << MRI->getName(Reg) << "\n");
297 }
298
Chris Lattner593c9582006-02-03 23:28:46 +0000299 /// canClobberPhysReg - Return true if the spiller is allowed to change the
300 /// value of the specified stackslot register if it desires. The specified
301 /// stack slot must be available in a physreg for this query to make sense.
302 bool canClobberPhysReg(int Slot) const {
303 assert(SpillSlotsAvailable.count(Slot) && "Slot not available!");
304 return SpillSlotsAvailable.find(Slot)->second & 1;
305 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000306
307 /// ClobberPhysReg - This is called when the specified physreg changes
308 /// value. We use this to invalidate any info about stuff we thing lives in
309 /// it and any of its aliases.
310 void ClobberPhysReg(unsigned PhysReg);
311
312 /// ModifyStackSlot - This method is called when the value in a stack slot
313 /// changes. This removes information about which register the previous value
314 /// for this slot lives in (as the previous value is dead now).
315 void ModifyStackSlot(int Slot);
316};
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000317}
Chris Lattner66cf80f2006-02-03 23:13:58 +0000318
319/// ClobberPhysRegOnly - This is called when the specified physreg changes
320/// value. We use this to invalidate any info about stuff we thing lives in it.
321void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
322 std::multimap<unsigned, int>::iterator I =
323 PhysRegsAvailable.lower_bound(PhysReg);
Chris Lattner07cf1412006-02-03 00:36:31 +0000324 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000325 int Slot = I->second;
Chris Lattner07cf1412006-02-03 00:36:31 +0000326 PhysRegsAvailable.erase(I++);
Chris Lattner593c9582006-02-03 23:28:46 +0000327 assert((SpillSlotsAvailable[Slot] >> 1) == PhysReg &&
Chris Lattner66cf80f2006-02-03 23:13:58 +0000328 "Bidirectional map mismatch!");
329 SpillSlotsAvailable.erase(Slot);
Chris Lattner7fb64342004-10-01 19:04:51 +0000330 DEBUG(std::cerr << "PhysReg " << MRI->getName(PhysReg)
Chris Lattner07cf1412006-02-03 00:36:31 +0000331 << " clobbered, invalidating SS#" << Slot << "\n");
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000332 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000333}
334
Chris Lattner66cf80f2006-02-03 23:13:58 +0000335/// ClobberPhysReg - This is called when the specified physreg changes
336/// value. We use this to invalidate any info about stuff we thing lives in
337/// it and any of its aliases.
338void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000339 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
Chris Lattner66cf80f2006-02-03 23:13:58 +0000340 ClobberPhysRegOnly(*AS);
341 ClobberPhysRegOnly(PhysReg);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000342}
343
Chris Lattner07cf1412006-02-03 00:36:31 +0000344/// ModifyStackSlot - This method is called when the value in a stack slot
345/// changes. This removes information about which register the previous value
346/// for this slot lives in (as the previous value is dead now).
Chris Lattner66cf80f2006-02-03 23:13:58 +0000347void AvailableSpills::ModifyStackSlot(int Slot) {
348 std::map<int, unsigned>::iterator It = SpillSlotsAvailable.find(Slot);
349 if (It == SpillSlotsAvailable.end()) return;
Chris Lattner593c9582006-02-03 23:28:46 +0000350 unsigned Reg = It->second >> 1;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000351 SpillSlotsAvailable.erase(It);
Chris Lattner07cf1412006-02-03 00:36:31 +0000352
353 // This register may hold the value of multiple stack slots, only remove this
354 // stack slot from the set of values the register contains.
355 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
356 for (; ; ++I) {
357 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
358 "Map inverse broken!");
359 if (I->second == Slot) break;
360 }
361 PhysRegsAvailable.erase(I);
362}
363
364
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000365
Chris Lattner7fb64342004-10-01 19:04:51 +0000366// ReusedOp - For each reused operand, we keep track of a bit of information, in
367// case we need to rollback upon processing a new operand. See comments below.
368namespace {
369 struct ReusedOp {
370 // The MachineInstr operand that reused an available value.
371 unsigned Operand;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000372
Chris Lattner7fb64342004-10-01 19:04:51 +0000373 // StackSlot - The spill slot of the value being reused.
374 unsigned StackSlot;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000375
Chris Lattner7fb64342004-10-01 19:04:51 +0000376 // PhysRegReused - The physical register the value was available in.
377 unsigned PhysRegReused;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000378
Chris Lattner7fb64342004-10-01 19:04:51 +0000379 // AssignedPhysReg - The physreg that was assigned for use by the reload.
380 unsigned AssignedPhysReg;
Chris Lattner8a61a752005-10-06 17:19:06 +0000381
382 // VirtReg - The virtual register itself.
383 unsigned VirtReg;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000384
Chris Lattner8a61a752005-10-06 17:19:06 +0000385 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
386 unsigned vreg)
387 : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr),
388 VirtReg(vreg) {}
Chris Lattner7fb64342004-10-01 19:04:51 +0000389 };
Chris Lattner540fec62006-02-25 01:51:33 +0000390
391 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
392 /// is reused instead of reloaded.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000393 class VISIBILITY_HIDDEN ReuseInfo {
Chris Lattner540fec62006-02-25 01:51:33 +0000394 MachineInstr &MI;
395 std::vector<ReusedOp> Reuses;
396 public:
397 ReuseInfo(MachineInstr &mi) : MI(mi) {}
398
399 bool hasReuses() const {
400 return !Reuses.empty();
401 }
402
403 /// addReuse - If we choose to reuse a virtual register that is already
404 /// available instead of reloading it, remember that we did so.
405 void addReuse(unsigned OpNo, unsigned StackSlot,
406 unsigned PhysRegReused, unsigned AssignedPhysReg,
407 unsigned VirtReg) {
408 // If the reload is to the assigned register anyway, no undo will be
409 // required.
410 if (PhysRegReused == AssignedPhysReg) return;
411
412 // Otherwise, remember this.
413 Reuses.push_back(ReusedOp(OpNo, StackSlot, PhysRegReused,
414 AssignedPhysReg, VirtReg));
415 }
416
417 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
418 /// is some other operand that is using the specified register, either pick
419 /// a new register to use, or evict the previous reload and use this reg.
420 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
421 AvailableSpills &Spills,
422 std::map<int, MachineInstr*> &MaybeDeadStores) {
423 if (Reuses.empty()) return PhysReg; // This is most often empty.
424
425 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
426 ReusedOp &Op = Reuses[ro];
427 // If we find some other reuse that was supposed to use this register
428 // exactly for its reload, we can change this reload to use ITS reload
429 // register.
430 if (Op.PhysRegReused == PhysReg) {
431 // Yup, use the reload register that we didn't use before.
Chris Lattner47cb7172006-02-25 02:03:40 +0000432 unsigned NewReg = Op.AssignedPhysReg;
433
434 // Remove the record for the previous reuse. We know it can never be
435 // invalidated now.
436 Reuses.erase(Reuses.begin()+ro);
437 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores);
Chris Lattner540fec62006-02-25 01:51:33 +0000438 } else {
439 // Otherwise, we might also have a problem if a previously reused
440 // value aliases the new register. If so, codegen the previous reload
441 // and use this one.
442 unsigned PRRU = Op.PhysRegReused;
443 const MRegisterInfo *MRI = Spills.getRegInfo();
444 if (MRI->areAliases(PRRU, PhysReg)) {
445 // Okay, we found out that an alias of a reused register
446 // was used. This isn't good because it means we have
447 // to undo a previous reuse.
448 MachineBasicBlock *MBB = MI->getParent();
449 const TargetRegisterClass *AliasRC =
Chris Lattner28bad082006-02-25 02:17:31 +0000450 MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
451
452 // Copy Op out of the vector and remove it, we're going to insert an
453 // explicit load for it.
454 ReusedOp NewOp = Op;
455 Reuses.erase(Reuses.begin()+ro);
456
457 // Ok, we're going to try to reload the assigned physreg into the
458 // slot that we were supposed to in the first place. However, that
459 // register could hold a reuse. Check to see if it conflicts or
460 // would prefer us to use a different register.
461 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
462 MI, Spills, MaybeDeadStores);
463
464 MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
465 NewOp.StackSlot, AliasRC);
466 Spills.ClobberPhysReg(NewPhysReg);
467 Spills.ClobberPhysReg(NewOp.PhysRegReused);
Chris Lattner540fec62006-02-25 01:51:33 +0000468
469 // Any stores to this stack slot are not dead anymore.
Chris Lattner28bad082006-02-25 02:17:31 +0000470 MaybeDeadStores.erase(NewOp.StackSlot);
Chris Lattner540fec62006-02-25 01:51:33 +0000471
Chris Lattnere53f4a02006-05-04 17:52:23 +0000472 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000473
Chris Lattner28bad082006-02-25 02:17:31 +0000474 Spills.addAvailable(NewOp.StackSlot, NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000475 ++NumLoads;
476 DEBUG(MachineBasicBlock::iterator MII = MI;
477 std::cerr << '\t' << *prior(MII));
478
479 DEBUG(std::cerr << "Reuse undone!\n");
Chris Lattner540fec62006-02-25 01:51:33 +0000480 --NumReused;
Chris Lattner28bad082006-02-25 02:17:31 +0000481
482 // Finally, PhysReg is now available, go ahead and use it.
Chris Lattner540fec62006-02-25 01:51:33 +0000483 return PhysReg;
484 }
485 }
486 }
487 return PhysReg;
488 }
489 };
Chris Lattner7fb64342004-10-01 19:04:51 +0000490}
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000491
Chris Lattner7fb64342004-10-01 19:04:51 +0000492
493/// rewriteMBB - Keep track of which spills are available even after the
494/// register allocator is done with them. If possible, avoid reloading vregs.
Chris Lattner35f27052006-05-01 21:16:03 +0000495void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000496
Chris Lattner7fb64342004-10-01 19:04:51 +0000497 DEBUG(std::cerr << MBB.getBasicBlock()->getName() << ":\n");
498
Chris Lattner66cf80f2006-02-03 23:13:58 +0000499 // Spills - Keep track of which spilled values are available in physregs so
500 // that we can choose to reuse the physregs instead of emitting reloads.
501 AvailableSpills Spills(MRI, TII);
502
Chris Lattner52b25db2004-10-01 19:47:12 +0000503 // MaybeDeadStores - When we need to write a value back into a stack slot,
504 // keep track of the inserted store. If the stack slot value is never read
505 // (because the value was used from some available register, for example), and
506 // subsequently stored to, the original store is dead. This map keeps track
507 // of inserted stores that are not used. If we see a subsequent store to the
508 // same stack slot, the original store is deleted.
509 std::map<int, MachineInstr*> MaybeDeadStores;
510
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000511 bool *PhysRegsUsed = MBB.getParent()->getUsedPhysregs();
512
Chris Lattner7fb64342004-10-01 19:04:51 +0000513 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
514 MII != E; ) {
515 MachineInstr &MI = *MII;
516 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
517
Chris Lattner540fec62006-02-25 01:51:33 +0000518 /// ReusedOperands - Keep track of operand reuse in case we need to undo
519 /// reuse.
520 ReuseInfo ReusedOperands(MI);
521
Chris Lattner7fb64342004-10-01 19:04:51 +0000522 // Process all of the spilled uses and all non spilled reg references.
523 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
524 MachineOperand &MO = MI.getOperand(i);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000525 if (!MO.isRegister() || MO.getReg() == 0)
526 continue; // Ignore non-register operands.
527
528 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
529 // Ignore physregs for spilling, but remember that it is used by this
530 // function.
Chris Lattner886dd912005-04-04 21:35:34 +0000531 PhysRegsUsed[MO.getReg()] = true;
Chris Lattner50ea01e2005-09-09 20:29:51 +0000532 continue;
533 }
534
535 assert(MRegisterInfo::isVirtualRegister(MO.getReg()) &&
536 "Not a virtual or a physical register?");
537
538 unsigned VirtReg = MO.getReg();
539 if (!VRM.hasStackSlot(VirtReg)) {
540 // This virtual register was assigned a physreg!
541 unsigned Phys = VRM.getPhys(VirtReg);
542 PhysRegsUsed[Phys] = true;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000543 MI.getOperand(i).setReg(Phys);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000544 continue;
545 }
546
547 // This virtual register is now known to be a spilled value.
548 if (!MO.isUse())
549 continue; // Handle defs in the loop below (handle use&def here though)
Chris Lattner7fb64342004-10-01 19:04:51 +0000550
Chris Lattner50ea01e2005-09-09 20:29:51 +0000551 int StackSlot = VRM.getStackSlot(VirtReg);
552 unsigned PhysReg;
Chris Lattner7fb64342004-10-01 19:04:51 +0000553
Chris Lattner50ea01e2005-09-09 20:29:51 +0000554 // Check to see if this stack slot is available.
Chris Lattneraddc55a2006-04-28 01:46:50 +0000555 if ((PhysReg = Spills.getSpillSlotPhysReg(StackSlot))) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000556
Chris Lattner29268692006-09-05 02:12:02 +0000557 // This spilled operand might be part of a two-address operand. If this
558 // is the case, then changing it will necessarily require changing the
559 // def part of the instruction as well. However, in some cases, we
560 // aren't allowed to modify the reused register. If none of these cases
561 // apply, reuse it.
562 bool CanReuse = true;
563 if (i == 1 && MI.getOperand(0).isReg() &&
564 MI.getOperand(0).getReg() == VirtReg &&
565 TII->isTwoAddrInstr(MI.getOpcode())) {
566 // Okay, we have a two address operand. We can reuse this physreg as
567 // long as we are allowed to clobber the value.
568 CanReuse = Spills.canClobberPhysReg(StackSlot);
569 }
570
571 if (CanReuse) {
Chris Lattneraddc55a2006-04-28 01:46:50 +0000572 // If this stack slot value is already available, reuse it!
573 DEBUG(std::cerr << "Reusing SS#" << StackSlot << " from physreg "
574 << MRI->getName(PhysReg) << " for vreg"
575 << VirtReg <<" instead of reloading into physreg "
576 << MRI->getName(VRM.getPhys(VirtReg)) << "\n");
Chris Lattnere53f4a02006-05-04 17:52:23 +0000577 MI.getOperand(i).setReg(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000578
579 // The only technical detail we have is that we don't know that
580 // PhysReg won't be clobbered by a reloaded stack slot that occurs
581 // later in the instruction. In particular, consider 'op V1, V2'.
582 // If V1 is available in physreg R0, we would choose to reuse it
583 // here, instead of reloading it into the register the allocator
584 // indicated (say R1). However, V2 might have to be reloaded
585 // later, and it might indicate that it needs to live in R0. When
586 // this occurs, we need to have information available that
587 // indicates it is safe to use R1 for the reload instead of R0.
588 //
589 // To further complicate matters, we might conflict with an alias,
590 // or R0 and R1 might not be compatible with each other. In this
591 // case, we actually insert a reload for V1 in R1, ensuring that
592 // we can get at R0 or its alias.
593 ReusedOperands.addReuse(i, StackSlot, PhysReg,
594 VRM.getPhys(VirtReg), VirtReg);
595 ++NumReused;
596 continue;
597 }
598
599 // Otherwise we have a situation where we have a two-address instruction
600 // whose mod/ref operand needs to be reloaded. This reload is already
601 // available in some register "PhysReg", but if we used PhysReg as the
602 // operand to our 2-addr instruction, the instruction would modify
603 // PhysReg. This isn't cool if something later uses PhysReg and expects
604 // to get its initial value.
Chris Lattner50ea01e2005-09-09 20:29:51 +0000605 //
Chris Lattneraddc55a2006-04-28 01:46:50 +0000606 // To avoid this problem, and to avoid doing a load right after a store,
607 // we emit a copy from PhysReg into the designated register for this
608 // operand.
609 unsigned DesignatedReg = VRM.getPhys(VirtReg);
610 assert(DesignatedReg && "Must map virtreg to physreg!");
611
612 // Note that, if we reused a register for a previous operand, the
613 // register we want to reload into might not actually be
614 // available. If this occurs, use the register indicated by the
615 // reuser.
616 if (ReusedOperands.hasReuses())
617 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
618 Spills, MaybeDeadStores);
619
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000620 // If the mapped designated register is actually the physreg we have
621 // incoming, we don't need to inserted a dead copy.
622 if (DesignatedReg == PhysReg) {
623 // If this stack slot value is already available, reuse it!
624 DEBUG(std::cerr << "Reusing SS#" << StackSlot << " from physreg "
625 << MRI->getName(PhysReg) << " for vreg"
626 << VirtReg
627 << " instead of reloading into same physreg.\n");
Chris Lattnere53f4a02006-05-04 17:52:23 +0000628 MI.getOperand(i).setReg(PhysReg);
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000629 ++NumReused;
630 continue;
631 }
632
Chris Lattneraddc55a2006-04-28 01:46:50 +0000633 const TargetRegisterClass* RC =
634 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
635
636 PhysRegsUsed[DesignatedReg] = true;
637 MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC);
638
639 // This invalidates DesignatedReg.
640 Spills.ClobberPhysReg(DesignatedReg);
641
642 Spills.addAvailable(StackSlot, DesignatedReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000643 MI.getOperand(i).setReg(DesignatedReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000644 DEBUG(std::cerr << '\t' << *prior(MII));
Chris Lattner50ea01e2005-09-09 20:29:51 +0000645 ++NumReused;
646 continue;
647 }
648
649 // Otherwise, reload it and remember that we have it.
650 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner172c3622006-01-04 06:47:48 +0000651 assert(PhysReg && "Must map virtreg to physreg!");
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000652 const TargetRegisterClass* RC =
653 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000654
Chris Lattner50ea01e2005-09-09 20:29:51 +0000655 // Note that, if we reused a register for a previous operand, the
656 // register we want to reload into might not actually be
657 // available. If this occurs, use the register indicated by the
658 // reuser.
Chris Lattner540fec62006-02-25 01:51:33 +0000659 if (ReusedOperands.hasReuses())
660 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
661 Spills, MaybeDeadStores);
662
Chris Lattner50ea01e2005-09-09 20:29:51 +0000663 PhysRegsUsed[PhysReg] = true;
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000664 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000665 // This invalidates PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000666 Spills.ClobberPhysReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000667
668 // Any stores to this stack slot are not dead anymore.
669 MaybeDeadStores.erase(StackSlot);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000670 Spills.addAvailable(StackSlot, PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000671 ++NumLoads;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000672 MI.getOperand(i).setReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000673 DEBUG(std::cerr << '\t' << *prior(MII));
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000674 }
675
Chris Lattner7fb64342004-10-01 19:04:51 +0000676 // Loop over all of the implicit defs, clearing them from our available
677 // sets.
Jim Laskeycd4317e2006-07-21 21:15:20 +0000678 const unsigned *ImpDef = TII->getImplicitDefs(MI.getOpcode());
679 if (ImpDef) {
680 for ( ; *ImpDef; ++ImpDef) {
681 PhysRegsUsed[*ImpDef] = true;
682 Spills.ClobberPhysReg(*ImpDef);
683 }
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000684 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000685
Chris Lattner7fb64342004-10-01 19:04:51 +0000686 DEBUG(std::cerr << '\t' << MI);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000687
Chris Lattner7fb64342004-10-01 19:04:51 +0000688 // If we have folded references to memory operands, make sure we clear all
689 // physical registers that may contain the value of the spilled virtual
690 // register
Chris Lattner8f1d6402005-01-14 15:54:24 +0000691 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
692 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000693 DEBUG(std::cerr << "Folded vreg: " << I->second.first << " MR: "
694 << I->second.second);
695 unsigned VirtReg = I->second.first;
696 VirtRegMap::ModRef MR = I->second.second;
Chris Lattnercea86882005-09-19 06:56:21 +0000697 if (!VRM.hasStackSlot(VirtReg)) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000698 DEBUG(std::cerr << ": No stack slot!\n");
Chris Lattnercea86882005-09-19 06:56:21 +0000699 continue;
700 }
701 int SS = VRM.getStackSlot(VirtReg);
702 DEBUG(std::cerr << " - StackSlot: " << SS << "\n");
703
704 // If this folded instruction is just a use, check to see if it's a
705 // straight load from the virt reg slot.
706 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
707 int FrameIdx;
Chris Lattner40839602006-02-02 20:12:32 +0000708 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
Chris Lattner6ec36262006-10-12 17:45:38 +0000709 if (FrameIdx == SS) {
710 // If this spill slot is available, turn it into a copy (or nothing)
711 // instead of leaving it as a load!
712 if (unsigned InReg = Spills.getSpillSlotPhysReg(SS)) {
713 DEBUG(std::cerr << "Promoted Load To Copy: " << MI);
714 MachineFunction &MF = *MBB.getParent();
715 if (DestReg != InReg) {
716 MRI->copyRegToReg(MBB, &MI, DestReg, InReg,
717 MF.getSSARegMap()->getRegClass(VirtReg));
718 // Revisit the copy so we make sure to notice the effects of the
719 // operation on the destreg (either needing to RA it if it's
720 // virtual or needing to clobber any values if it's physical).
721 NextMII = &MI;
722 --NextMII; // backtrack to the copy.
723 }
724 VRM.RemoveFromFoldedVirtMap(&MI);
725 MBB.erase(&MI);
726 goto ProcessNextInst;
Chris Lattnercea86882005-09-19 06:56:21 +0000727 }
Chris Lattnercea86882005-09-19 06:56:21 +0000728 }
729 }
730 }
731
732 // If this reference is not a use, any previous store is now dead.
733 // Otherwise, the store to this stack slot is not dead anymore.
734 std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS);
735 if (MDSI != MaybeDeadStores.end()) {
736 if (MR & VirtRegMap::isRef) // Previous store is not dead.
737 MaybeDeadStores.erase(MDSI);
738 else {
739 // If we get here, the store is dead, nuke it now.
Chris Lattner35f27052006-05-01 21:16:03 +0000740 assert(VirtRegMap::isMod && "Can't be modref!");
741 DEBUG(std::cerr << "Removed dead store:\t" << *MDSI->second);
742 MBB.erase(MDSI->second);
Chris Lattner229924a2006-05-01 22:03:24 +0000743 VRM.RemoveFromFoldedVirtMap(MDSI->second);
Chris Lattner35f27052006-05-01 21:16:03 +0000744 MaybeDeadStores.erase(MDSI);
745 ++NumDSE;
Chris Lattnercea86882005-09-19 06:56:21 +0000746 }
747 }
748
749 // If the spill slot value is available, and this is a new definition of
750 // the value, the value is not available anymore.
751 if (MR & VirtRegMap::isMod) {
Chris Lattner07cf1412006-02-03 00:36:31 +0000752 // Notice that the value in this stack slot has been modified.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000753 Spills.ModifyStackSlot(SS);
Chris Lattnercd816392006-02-02 23:29:36 +0000754
755 // If this is *just* a mod of the value, check to see if this is just a
756 // store to the spill slot (i.e. the spill got merged into the copy). If
757 // so, realize that the vreg is available now, and add the store to the
758 // MaybeDeadStore info.
759 int StackSlot;
760 if (!(MR & VirtRegMap::isRef)) {
761 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
762 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
763 "Src hasn't been allocated yet?");
Chris Lattner07cf1412006-02-03 00:36:31 +0000764 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
Chris Lattnercd816392006-02-02 23:29:36 +0000765 // this as a potentially dead store in case there is a subsequent
766 // store into the stack slot without a read from it.
767 MaybeDeadStores[StackSlot] = &MI;
768
Chris Lattnercd816392006-02-02 23:29:36 +0000769 // If the stack slot value was previously available in some other
770 // register, change it now. Otherwise, make the register available,
771 // in PhysReg.
Chris Lattner593c9582006-02-03 23:28:46 +0000772 Spills.addAvailable(StackSlot, SrcReg, false /*don't clobber*/);
Chris Lattnercd816392006-02-02 23:29:36 +0000773 }
774 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000775 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000776 }
777
Chris Lattner7fb64342004-10-01 19:04:51 +0000778 // Process all of the spilled defs.
779 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
780 MachineOperand &MO = MI.getOperand(i);
781 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
782 unsigned VirtReg = MO.getReg();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000783
Chris Lattner7fb64342004-10-01 19:04:51 +0000784 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
Chris Lattner29268692006-09-05 02:12:02 +0000785 // Check to see if this is a noop copy. If so, eliminate the
786 // instruction before considering the dest reg to be changed.
787 unsigned Src, Dst;
788 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
789 ++NumDCE;
790 DEBUG(std::cerr << "Removing now-noop copy: " << MI);
791 MBB.erase(&MI);
792 VRM.RemoveFromFoldedVirtMap(&MI);
793 goto ProcessNextInst;
Chris Lattner7fb64342004-10-01 19:04:51 +0000794 }
Chris Lattner6ec36262006-10-12 17:45:38 +0000795
796 // If it's not a no-op copy, it clobbers the value in the destreg.
Chris Lattner29268692006-09-05 02:12:02 +0000797 Spills.ClobberPhysReg(VirtReg);
Chris Lattner6ec36262006-10-12 17:45:38 +0000798
799 // Check to see if this instruction is a load from a stack slot into
800 // a register. If so, this provides the stack slot value in the reg.
801 int FrameIdx;
802 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
803 assert(DestReg == VirtReg && "Unknown load situation!");
804
805 // Otherwise, if it wasn't available, remember that it is now!
806 Spills.addAvailable(FrameIdx, DestReg);
807 goto ProcessNextInst;
808 }
809
Chris Lattner29268692006-09-05 02:12:02 +0000810 continue;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000811 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000812
Chris Lattner84e752a2006-02-03 03:06:49 +0000813 // The only vregs left are stack slot definitions.
814 int StackSlot = VRM.getStackSlot(VirtReg);
815 const TargetRegisterClass *RC =
816 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000817
Chris Lattner29268692006-09-05 02:12:02 +0000818 // If this def is part of a two-address operand, make sure to execute
819 // the store from the correct physical register.
820 unsigned PhysReg;
821 if (i == 0 && TII->isTwoAddrInstr(MI.getOpcode()))
822 PhysReg = MI.getOperand(1).getReg();
Chris Lattner84e752a2006-02-03 03:06:49 +0000823 else
Chris Lattner29268692006-09-05 02:12:02 +0000824 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000825
Chris Lattner84e752a2006-02-03 03:06:49 +0000826 PhysRegsUsed[PhysReg] = true;
827 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
828 DEBUG(std::cerr << "Store:\t" << *next(MII));
Chris Lattnere53f4a02006-05-04 17:52:23 +0000829 MI.getOperand(i).setReg(PhysReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000830
Chris Lattner109afed2006-02-03 03:16:14 +0000831 // Check to see if this is a noop copy. If so, eliminate the
832 // instruction before considering the dest reg to be changed.
833 {
834 unsigned Src, Dst;
835 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
836 ++NumDCE;
837 DEBUG(std::cerr << "Removing now-noop copy: " << MI);
838 MBB.erase(&MI);
Chris Lattner229924a2006-05-01 22:03:24 +0000839 VRM.RemoveFromFoldedVirtMap(&MI);
Chris Lattner109afed2006-02-03 03:16:14 +0000840 goto ProcessNextInst;
841 }
842 }
843
Chris Lattner84e752a2006-02-03 03:06:49 +0000844 // If there is a dead store to this stack slot, nuke it now.
845 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
846 if (LastStore) {
Chris Lattner35f27052006-05-01 21:16:03 +0000847 DEBUG(std::cerr << "Removed dead store:\t" << *LastStore);
Chris Lattner84e752a2006-02-03 03:06:49 +0000848 ++NumDSE;
849 MBB.erase(LastStore);
Chris Lattner229924a2006-05-01 22:03:24 +0000850 VRM.RemoveFromFoldedVirtMap(LastStore);
Chris Lattner7fb64342004-10-01 19:04:51 +0000851 }
Chris Lattner84e752a2006-02-03 03:06:49 +0000852 LastStore = next(MII);
853
854 // If the stack slot value was previously available in some other
855 // register, change it now. Otherwise, make the register available,
856 // in PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000857 Spills.ModifyStackSlot(StackSlot);
858 Spills.ClobberPhysReg(PhysReg);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000859 Spills.addAvailable(StackSlot, PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +0000860 ++NumStores;
Chris Lattner7fb64342004-10-01 19:04:51 +0000861 }
862 }
Chris Lattnercea86882005-09-19 06:56:21 +0000863 ProcessNextInst:
Chris Lattner7fb64342004-10-01 19:04:51 +0000864 MII = NextMII;
865 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000866}
867
Chris Lattnerf7da2c72006-08-24 22:43:55 +0000868
869
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000870llvm::Spiller* llvm::createSpiller() {
871 switch (SpillerOpt) {
872 default: assert(0 && "Unreachable!");
873 case local:
874 return new LocalSpiller();
875 case simple:
876 return new SimpleSpiller();
877 }
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000878}