Gitiles
Code Review Sign In
gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / af53a87052f41664ff5962731d0b64e3b51a5501 / . / docs / CodeGenerator.html
blob: 42721b6a35f941f8bd51850c14a86cfbc394bcff [file] [log] [blame]
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]1<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN"
2 "http://www.w3.org/TR/html4/strict.dtd">
3<html>
4<head>
5 <title>The LLVM Target-Independent Code Generator</title>
6 <link rel="stylesheet" href="llvm.css" type="text/css">
7</head>
8<body>
9
10<div class="doc_title">
11 The LLVM Target-Independent Code Generator
12</div>
13
14<ol>
15 <li><a href="#introduction">Introduction</a>
16 <ul>
17 <li><a href="#required">Required components in the code generator</a></li>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]18 <li><a href="#high-level-design">The high-level design of the code
19 generator</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]20 <li><a href="#tablegen">Using TableGen for target description</a></li>
21 </ul>
22 </li>
23 <li><a href="#targetdesc">Target description classes</a>
24 <ul>
25 <li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
26 <li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]27 <li><a href="#targetlowering">The <tt>TargetLowering</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]28 <li><a href="#mregisterinfo">The <tt>MRegisterInfo</tt> class</a></li>
29 <li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
30 <li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]31 <li><a href="#targetsubtarget">The <tt>TargetSubtarget</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]32 <li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
33 </ul>
34 </li>
35 <li><a href="#codegendesc">Machine code description classes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]36 <ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]37 <li><a href="#machineinstr">The <tt>MachineInstr</tt> class</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]38 <li><a href="#machinebasicblock">The <tt>MachineBasicBlock</tt>
39 class</a></li>
40 <li><a href="#machinefunction">The <tt>MachineFunction</tt> class</a></li>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]41 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]42 </li>
43 <li><a href="#codegenalgs">Target-independent code generation algorithms</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]44 <ul>
45 <li><a href="#instselect">Instruction Selection</a>
46 <ul>
47 <li><a href="#selectiondag_intro">Introduction to SelectionDAGs</a></li>
48 <li><a href="#selectiondag_process">SelectionDAG Code Generation
49 Process</a></li>
50 <li><a href="#selectiondag_build">Initial SelectionDAG
51 Construction</a></li>
52 <li><a href="#selectiondag_legalize">SelectionDAG Legalize Phase</a></li>
53 <li><a href="#selectiondag_optimize">SelectionDAG Optimization
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]54 Phase: the DAG Combiner</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]55 <li><a href="#selectiondag_select">SelectionDAG Select Phase</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]56 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]57 Phase</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]58 <li><a href="#selectiondag_future">Future directions for the
59 SelectionDAG</a></li>
60 </ul></li>
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]61 <li><a href="#liveintervals">Live Intervals</a>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]62 <ul>
63 <li><a href="#livevariable_analysis">Live Variable Analysis</a></li>
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]64 <li><a href="#liveintervals_analysis">Live Intervals Analysis</a></li>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]65 </ul></li>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]66 <li><a href="#regalloc">Register Allocation</a>
67 <ul>
68 <li><a href="#regAlloc_represent">How registers are represented in
69 LLVM</a></li>
70 <li><a href="#regAlloc_howTo">Mapping virtual registers to physical
71 registers</a></li>
72 <li><a href="#regAlloc_twoAddr">Handling two address instructions</a></li>
73 <li><a href="#regAlloc_ssaDecon">The SSA deconstruction phase</a></li>
74 <li><a href="#regAlloc_fold">Instruction folding</a></li>
75 <li><a href="#regAlloc_builtIn">Built in register allocators</a></li>
76 </ul></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]77 <li><a href="#codeemit">Code Emission</a>
78 <ul>
79 <li><a href="#codeemit_asm">Generating Assembly Code</a></li>
80 <li><a href="#codeemit_bin">Generating Binary Machine Code</a></li>
81 </ul></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]82 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]83 </li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]84 <li><a href="#targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]85 <ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]86 <li><a href="#x86">The X86 backend</a></li>
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]87 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]88 </li>
89
90</ol>
91
92<div class="doc_author">
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]93 <p>Written by <a href="mailto:sabre@nondot.org">Chris Lattner</a>,
94 <a href="mailto:isanbard@gmail.com">Bill Wendling</a>, and
95 <a href="mailto:pronesto@gmail.com">Fernando Magno Quintao
96 Pereira</a></p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]97</div>
98
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]99<div class="doc_warning">
100 <p>Warning: This is a work in progress.</p>
101</div>
102
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]103<!-- *********************************************************************** -->
104<div class="doc_section">
105 <a name="introduction">Introduction</a>
106</div>
107<!-- *********************************************************************** -->
108
109<div class="doc_text">
110
111<p>The LLVM target-independent code generator is a framework that provides a
112suite of reusable components for translating the LLVM internal representation to
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]113the machine code for a specified target&mdash;either in assembly form (suitable
114for a static compiler) or in binary machine code format (usable for a JIT
115compiler). The LLVM target-independent code generator consists of five main
116components:</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]117
118<ol>
119<li><a href="#targetdesc">Abstract target description</a> interfaces which
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]120capture important properties about various aspects of the machine, independently
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]121of how they will be used. These interfaces are defined in
122<tt>include/llvm/Target/</tt>.</li>
123
124<li>Classes used to represent the <a href="#codegendesc">machine code</a> being
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]125generated for a target. These classes are intended to be abstract enough to
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]126represent the machine code for <i>any</i> target machine. These classes are
127defined in <tt>include/llvm/CodeGen/</tt>.</li>
128
129<li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
130various phases of native code generation (register allocation, scheduling, stack
131frame representation, etc). This code lives in <tt>lib/CodeGen/</tt>.</li>
132
133<li><a href="#targetimpls">Implementations of the abstract target description
134interfaces</a> for particular targets. These machine descriptions make use of
135the components provided by LLVM, and can optionally provide custom
136target-specific passes, to build complete code generators for a specific target.
137Target descriptions live in <tt>lib/Target/</tt>.</li>
138
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]139<li><a href="#jit">The target-independent JIT components</a>. The LLVM JIT is
140completely target independent (it uses the <tt>TargetJITInfo</tt> structure to
141interface for target-specific issues. The code for the target-independent
142JIT lives in <tt>lib/ExecutionEngine/JIT</tt>.</li>
143
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]144</ol>
145
146<p>
147Depending on which part of the code generator you are interested in working on,
148different pieces of this will be useful to you. In any case, you should be
149familiar with the <a href="#targetdesc">target description</a> and <a
150href="#codegendesc">machine code representation</a> classes. If you want to add
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]151a backend for a new target, you will need to <a href="#targetimpls">implement the
152target description</a> classes for your new target and understand the <a
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]153href="LangRef.html">LLVM code representation</a>. If you are interested in
154implementing a new <a href="#codegenalgs">code generation algorithm</a>, it
155should only depend on the target-description and machine code representation
156classes, ensuring that it is portable.
157</p>
158
159</div>
160
161<!-- ======================================================================= -->
162<div class="doc_subsection">
163 <a name="required">Required components in the code generator</a>
164</div>
165
166<div class="doc_text">
167
168<p>The two pieces of the LLVM code generator are the high-level interface to the
169code generator and the set of reusable components that can be used to build
170target-specific backends. The two most important interfaces (<a
171href="#targetmachine"><tt>TargetMachine</tt></a> and <a
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]172href="#targetdata"><tt>TargetData</tt></a>) are the only ones that are
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]173required to be defined for a backend to fit into the LLVM system, but the others
174must be defined if the reusable code generator components are going to be
175used.</p>
176
177<p>This design has two important implications. The first is that LLVM can
178support completely non-traditional code generation targets. For example, the C
179backend does not require register allocation, instruction selection, or any of
180the other standard components provided by the system. As such, it only
181implements these two interfaces, and does its own thing. Another example of a
182code generator like this is a (purely hypothetical) backend that converts LLVM
183to the GCC RTL form and uses GCC to emit machine code for a target.</p>
184
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]185<p>This design also implies that it is possible to design and
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]186implement radically different code generators in the LLVM system that do not
187make use of any of the built-in components. Doing so is not recommended at all,
188but could be required for radically different targets that do not fit into the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]189LLVM machine description model: FPGAs for example.</p>
Chris Lattner900bf8c2004-06-02 07:06:06 +0000[diff] [blame]190
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]191</div>
192
193<!-- ======================================================================= -->
194<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]195 <a name="high-level-design">The high-level design of the code generator</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]196</div>
197
198<div class="doc_text">
199
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]200<p>The LLVM target-independent code generator is designed to support efficient and
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]201quality code generation for standard register-based microprocessors. Code
202generation in this model is divided into the following stages:</p>
203
204<ol>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]205<li><b><a href="#instselect">Instruction Selection</a></b> - This phase
206determines an efficient way to express the input LLVM code in the target
207instruction set.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]208This stage produces the initial code for the program in the target instruction
209set, then makes use of virtual registers in SSA form and physical registers that
210represent any required register assignments due to target constraints or calling
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]211conventions. This step turns the LLVM code into a DAG of target
212instructions.</li>
213
214<li><b><a href="#selectiondag_sched">Scheduling and Formation</a></b> - This
215phase takes the DAG of target instructions produced by the instruction selection
216phase, determines an ordering of the instructions, then emits the instructions
Chris Lattnerc38959f2005-10-17 03:09:31 +0000[diff] [blame]217as <tt><a href="#machineinstr">MachineInstr</a></tt>s with that ordering. Note
218that we describe this in the <a href="#instselect">instruction selection
219section</a> because it operates on a <a
220href="#selectiondag_intro">SelectionDAG</a>.
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]221</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]222
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]223<li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> - This
224optional stage consists of a series of machine-code optimizations that
225operate on the SSA-form produced by the instruction selector. Optimizations
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]226like modulo-scheduling or peephole optimization work here.
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]227</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]228
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]229<li><b><a href="#regalloc">Register Allocation</a></b> - The
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]230target code is transformed from an infinite virtual register file in SSA form
231to the concrete register file used by the target. This phase introduces spill
232code and eliminates all virtual register references from the program.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]233
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]234<li><b><a href="#proepicode">Prolog/Epilog Code Insertion</a></b> - Once the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]235machine code has been generated for the function and the amount of stack space
236required is known (used for LLVM alloca's and spill slots), the prolog and
237epilog code for the function can be inserted and "abstract stack location
238references" can be eliminated. This stage is responsible for implementing
239optimizations like frame-pointer elimination and stack packing.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]240
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]241<li><b><a href="#latemco">Late Machine Code Optimizations</a></b> - Optimizations
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]242that operate on "final" machine code can go here, such as spill code scheduling
243and peephole optimizations.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]244
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]245<li><b><a href="#codeemit">Code Emission</a></b> - The final stage actually
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]246puts out the code for the current function, either in the target assembler
247format or in machine code.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]248
249</ol>
250
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]251<p>The code generator is based on the assumption that the instruction selector
252will use an optimal pattern matching selector to create high-quality sequences of
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]253native instructions. Alternative code generator designs based on pattern
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]254expansion and aggressive iterative peephole optimization are much slower. This
255design permits efficient compilation (important for JIT environments) and
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]256aggressive optimization (used when generating code offline) by allowing
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]257components of varying levels of sophistication to be used for any step of
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]258compilation.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]259
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]260<p>In addition to these stages, target implementations can insert arbitrary
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]261target-specific passes into the flow. For example, the X86 target uses a
262special pass to handle the 80x87 floating point stack architecture. Other
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]263targets with unusual requirements can be supported with custom passes as
264needed.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]265
266</div>
267
268
269<!-- ======================================================================= -->
270<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]271 <a name="tablegen">Using TableGen for target description</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]272</div>
273
274<div class="doc_text">
275
Chris Lattner5489e932004-06-01 18:35:00 +0000[diff] [blame]276<p>The target description classes require a detailed description of the target
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]277architecture. These target descriptions often have a large amount of common
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]278information (e.g., an <tt>add</tt> instruction is almost identical to a
279<tt>sub</tt> instruction).
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]280In order to allow the maximum amount of commonality to be factored out, the LLVM
281code generator uses the <a href="TableGenFundamentals.html">TableGen</a> tool to
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]282describe big chunks of the target machine, which allows the use of
283domain-specific and target-specific abstractions to reduce the amount of
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]284repetition.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]285
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]286<p>As LLVM continues to be developed and refined, we plan to move more and more
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]287of the target description to the <tt>.td</tt> form. Doing so gives us a
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]288number of advantages. The most important is that it makes it easier to port
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]289LLVM because it reduces the amount of C++ code that has to be written, and the
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]290surface area of the code generator that needs to be understood before someone
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]291can get something working. Second, it makes it easier to change things. In
292particular, if tables and other things are all emitted by <tt>tblgen</tt>, we
293only need a change in one place (<tt>tblgen</tt>) to update all of the targets
294to a new interface.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]295
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]296</div>
297
298<!-- *********************************************************************** -->
299<div class="doc_section">
300 <a name="targetdesc">Target description classes</a>
301</div>
302<!-- *********************************************************************** -->
303
304<div class="doc_text">
305
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]306<p>The LLVM target description classes (located in the
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]307<tt>include/llvm/Target</tt> directory) provide an abstract description of the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]308target machine independent of any particular client. These classes are
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]309designed to capture the <i>abstract</i> properties of the target (such as the
310instructions and registers it has), and do not incorporate any particular pieces
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]311of code generation algorithms.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]312
313<p>All of the target description classes (except the <tt><a
314href="#targetdata">TargetData</a></tt> class) are designed to be subclassed by
315the concrete target implementation, and have virtual methods implemented. To
Reid Spencerbdbcb8a2004-06-05 14:39:24 +0000[diff] [blame]316get to these implementations, the <tt><a
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]317href="#targetmachine">TargetMachine</a></tt> class provides accessors that
318should be implemented by the target.</p>
319
320</div>
321
322<!-- ======================================================================= -->
323<div class="doc_subsection">
324 <a name="targetmachine">The <tt>TargetMachine</tt> class</a>
325</div>
326
327<div class="doc_text">
328
329<p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
330access the target-specific implementations of the various target description
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]331classes via the <tt>get*Info</tt> methods (<tt>getInstrInfo</tt>,
332<tt>getRegisterInfo</tt>, <tt>getFrameInfo</tt>, etc.). This class is
333designed to be specialized by
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]334a concrete target implementation (e.g., <tt>X86TargetMachine</tt>) which
335implements the various virtual methods. The only required target description
336class is the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the
337code generator components are to be used, the other interfaces should be
338implemented as well.</p>
339
340</div>
341
342
343<!-- ======================================================================= -->
344<div class="doc_subsection">
345 <a name="targetdata">The <tt>TargetData</tt> class</a>
346</div>
347
348<div class="doc_text">
349
350<p>The <tt>TargetData</tt> class is the only required target description class,
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]351and it is the only class that is not extensible (you cannot derived a new
352class from it). <tt>TargetData</tt> specifies information about how the target
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]353lays out memory for structures, the alignment requirements for various data
354types, the size of pointers in the target, and whether the target is
355little-endian or big-endian.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]356
357</div>
358
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]359<!-- ======================================================================= -->
360<div class="doc_subsection">
361 <a name="targetlowering">The <tt>TargetLowering</tt> class</a>
362</div>
363
364<div class="doc_text">
365
366<p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
367selectors primarily to describe how LLVM code should be lowered to SelectionDAG
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]368operations. Among other things, this class indicates:</p>
369
370<ul>
371 <li>an initial register class to use for various <tt>ValueType</tt>s</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]372 <li>which operations are natively supported by the target machine</li>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]373 <li>the return type of <tt>setcc</tt> operations</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]374 <li>the type to use for shift amounts</li>
375 <li>various high-level characteristics, like whether it is profitable to turn
376 division by a constant into a multiplication sequence</li>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]377</ol>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]378
379</div>
380
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]381<!-- ======================================================================= -->
382<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]383 <a name="mregisterinfo">The <tt>MRegisterInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]384</div>
385
386<div class="doc_text">
387
388<p>The <tt>MRegisterInfo</tt> class (which will eventually be renamed to
389<tt>TargetRegisterInfo</tt>) is used to describe the register file of the
390target and any interactions between the registers.</p>
391
392<p>Registers in the code generator are represented in the code generator by
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]393unsigned integers. Physical registers (those that actually exist in the target
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]394description) are unique small numbers, and virtual registers are generally
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]395large. Note that register #0 is reserved as a flag value.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]396
397<p>Each register in the processor description has an associated
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]398<tt>TargetRegisterDesc</tt> entry, which provides a textual name for the
399register (used for assembly output and debugging dumps) and a set of aliases
400(used to indicate whether one register overlaps with another).
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]401</p>
402
403<p>In addition to the per-register description, the <tt>MRegisterInfo</tt> class
404exposes a set of processor specific register classes (instances of the
405<tt>TargetRegisterClass</tt> class). Each register class contains sets of
406registers that have the same properties (for example, they are all 32-bit
407integer registers). Each SSA virtual register created by the instruction
408selector has an associated register class. When the register allocator runs, it
409replaces virtual registers with a physical register in the set.</p>
410
411<p>
412The target-specific implementations of these classes is auto-generated from a <a
413href="TableGenFundamentals.html">TableGen</a> description of the register file.
414</p>
415
416</div>
417
418<!-- ======================================================================= -->
419<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]420 <a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]421</div>
422
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]423<div class="doc_text">
424 <p>The <tt>TargetInstrInfo</tt> class is used to describe the machine
425 instructions supported by the target. It is essentially an array of
426 <tt>TargetInstrDescriptor</tt> objects, each of which describes one
427 instruction the target supports. Descriptors define things like the mnemonic
Chris Lattnera3079782005-07-19 03:37:48 +0000[diff] [blame]428 for the opcode, the number of operands, the list of implicit register uses
429 and defs, whether the instruction has certain target-independent properties
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]430 (accesses memory, is commutable, etc), and holds any target-specific
431 flags.</p>
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]432</div>
433
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]434<!-- ======================================================================= -->
435<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]436 <a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]437</div>
438
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]439<div class="doc_text">
440 <p>The <tt>TargetFrameInfo</tt> class is used to provide information about the
441 stack frame layout of the target. It holds the direction of stack growth,
442 the known stack alignment on entry to each function, and the offset to the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]443 local area. The offset to the local area is the offset from the stack
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]444 pointer on function entry to the first location where function data (local
445 variables, spill locations) can be stored.</p>
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]446</div>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]447
448<!-- ======================================================================= -->
449<div class="doc_subsection">
450 <a name="targetsubtarget">The <tt>TargetSubtarget</tt> class</a>
451</div>
452
453<div class="doc_text">
Jim Laskey82d61a12005-10-17 12:19:10 +0000[diff] [blame]454 <p>The <tt>TargetSubtarget</tt> class is used to provide information about the
455 specific chip set being targeted. A sub-target informs code generation of
456 which instructions are supported, instruction latencies and instruction
457 execution itinerary; i.e., which processing units are used, in what order, and
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]458 for how long.</p>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]459</div>
460
461
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]462<!-- ======================================================================= -->
463<div class="doc_subsection">
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]464 <a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]465</div>
466
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]467<div class="doc_text">
468 <p>The <tt>TargetJITInfo</tt> class exposes an abstract interface used by the
469 Just-In-Time code generator to perform target-specific activities, such as
470 emitting stubs. If a <tt>TargetMachine</tt> supports JIT code generation, it
471 should provide one of these objects through the <tt>getJITInfo</tt>
472 method.</p>
473</div>
474
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]475<!-- *********************************************************************** -->
476<div class="doc_section">
477 <a name="codegendesc">Machine code description classes</a>
478</div>
479<!-- *********************************************************************** -->
480
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]481<div class="doc_text">
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]482
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]483<p>At the high-level, LLVM code is translated to a machine specific
484representation formed out of
485<a href="#machinefunction"><tt>MachineFunction</tt></a>,
486<a href="#machinebasicblock"><tt>MachineBasicBlock</tt></a>, and <a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]487href="#machineinstr"><tt>MachineInstr</tt></a> instances
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]488(defined in <tt>include/llvm/CodeGen</tt>). This representation is completely
489target agnostic, representing instructions in their most abstract form: an
490opcode and a series of operands. This representation is designed to support
491both an SSA representation for machine code, as well as a register allocated,
492non-SSA form.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]493
494</div>
495
496<!-- ======================================================================= -->
497<div class="doc_subsection">
498 <a name="machineinstr">The <tt>MachineInstr</tt> class</a>
499</div>
500
501<div class="doc_text">
502
503<p>Target machine instructions are represented as instances of the
504<tt>MachineInstr</tt> class. This class is an extremely abstract way of
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]505representing machine instructions. In particular, it only keeps track of
506an opcode number and a set of operands.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]507
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]508<p>The opcode number is a simple unsigned integer that only has meaning to a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]509specific backend. All of the instructions for a target should be defined in
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]510the <tt>*InstrInfo.td</tt> file for the target. The opcode enum values
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]511are auto-generated from this description. The <tt>MachineInstr</tt> class does
512not have any information about how to interpret the instruction (i.e., what the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]513semantics of the instruction are); for that you must refer to the
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]514<tt><a href="#targetinstrinfo">TargetInstrInfo</a></tt> class.</p>
515
516<p>The operands of a machine instruction can be of several different types:
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]517a register reference, a constant integer, a basic block reference, etc. In
518addition, a machine operand should be marked as a def or a use of the value
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]519(though only registers are allowed to be defs).</p>
520
521<p>By convention, the LLVM code generator orders instruction operands so that
522all register definitions come before the register uses, even on architectures
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]523that are normally printed in other orders. For example, the SPARC add
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]524instruction: "<tt>add %i1, %i2, %i3</tt>" adds the "%i1", and "%i2" registers
525and stores the result into the "%i3" register. In the LLVM code generator,
526the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the destination
527first.</p>
528
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]529<p>Keeping destination (definition) operands at the beginning of the operand
530list has several advantages. In particular, the debugging printer will print
531the instruction like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]532
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]533<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]534<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]535%r3 = add %i1, %i2
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]536</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]537</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]538
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]539<p>Also if the first operand is a def, it is easier to <a
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]540href="#buildmi">create instructions</a> whose only def is the first
541operand.</p>
542
543</div>
544
545<!-- _______________________________________________________________________ -->
546<div class="doc_subsubsection">
547 <a name="buildmi">Using the <tt>MachineInstrBuilder.h</tt> functions</a>
548</div>
549
550<div class="doc_text">
551
552<p>Machine instructions are created by using the <tt>BuildMI</tt> functions,
553located in the <tt>include/llvm/CodeGen/MachineInstrBuilder.h</tt> file. The
554<tt>BuildMI</tt> functions make it easy to build arbitrary machine
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]555instructions. Usage of the <tt>BuildMI</tt> functions look like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]556
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]557<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]558<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]559// Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
560// instruction. The '1' specifies how many operands will be added.
561MachineInstr *MI = BuildMI(X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]562
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]563// Create the same instr, but insert it at the end of a basic block.
564MachineBasicBlock &amp;MBB = ...
565BuildMI(MBB, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]566
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]567// Create the same instr, but insert it before a specified iterator point.
568MachineBasicBlock::iterator MBBI = ...
569BuildMI(MBB, MBBI, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]570
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]571// Create a 'cmp Reg, 0' instruction, no destination reg.
572MI = BuildMI(X86::CMP32ri, 2).addReg(Reg).addImm(0);
573// Create an 'sahf' instruction which takes no operands and stores nothing.
574MI = BuildMI(X86::SAHF, 0);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]575
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]576// Create a self looping branch instruction.
577BuildMI(MBB, X86::JNE, 1).addMBB(&amp;MBB);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]578</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]579</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]580
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]581<p>The key thing to remember with the <tt>BuildMI</tt> functions is that you
582have to specify the number of operands that the machine instruction will take.
583This allows for efficient memory allocation. You also need to specify if
584operands default to be uses of values, not definitions. If you need to add a
585definition operand (other than the optional destination register), you must
586explicitly mark it as such:</p>
587
588<div class="doc_code">
589<pre>
590MI.addReg(Reg, MachineOperand::Def);
591</pre>
592</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]593
594</div>
595
596<!-- _______________________________________________________________________ -->
597<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]598 <a name="fixedregs">Fixed (preassigned) registers</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]599</div>
600
601<div class="doc_text">
602
603<p>One important issue that the code generator needs to be aware of is the
604presence of fixed registers. In particular, there are often places in the
605instruction stream where the register allocator <em>must</em> arrange for a
606particular value to be in a particular register. This can occur due to
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]607limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]608with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like calling
609conventions. In any case, the instruction selector should emit code that
610copies a virtual register into or out of a physical register when needed.</p>
611
612<p>For example, consider this simple LLVM example:</p>
613
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]614<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]615<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]616int %test(int %X, int %Y) {
617 %Z = div int %X, %Y
618 ret int %Z
619}
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]620</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]621</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]622
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]623<p>The X86 instruction selector produces this machine code for the <tt>div</tt>
624and <tt>ret</tt> (use
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]625"<tt>llc X.bc -march=x86 -print-machineinstrs</tt>" to get this):</p>
626
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]627<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]628<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]629;; Start of div
630%EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
631%reg1027 = sar %reg1024, 31
632%EDX = mov %reg1027 ;; Sign extend X into EDX
633idiv %reg1025 ;; Divide by Y (in reg1025)
634%reg1026 = mov %EAX ;; Read the result (Z) out of EAX
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]635
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]636;; Start of ret
637%EAX = mov %reg1026 ;; 32-bit return value goes in EAX
638ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]639</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]640</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]641
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]642<p>By the end of code generation, the register allocator has coalesced
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]643the registers and deleted the resultant identity moves producing the
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]644following code:</p>
645
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]646<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]647<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]648;; X is in EAX, Y is in ECX
649mov %EAX, %EDX
650sar %EDX, 31
651idiv %ECX
652ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]653</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]654</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]655
656<p>This approach is extremely general (if it can handle the X86 architecture,
657it can handle anything!) and allows all of the target specific
658knowledge about the instruction stream to be isolated in the instruction
659selector. Note that physical registers should have a short lifetime for good
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]660code generation, and all physical registers are assumed dead on entry to and
661exit from basic blocks (before register allocation). Thus, if you need a value
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]662to be live across basic block boundaries, it <em>must</em> live in a virtual
663register.</p>
664
665</div>
666
667<!-- _______________________________________________________________________ -->
668<div class="doc_subsubsection">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]669 <a name="ssa">Machine code in SSA form</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]670</div>
671
672<div class="doc_text">
673
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]674<p><tt>MachineInstr</tt>'s are initially selected in SSA-form, and
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]675are maintained in SSA-form until register allocation happens. For the most
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]676part, this is trivially simple since LLVM is already in SSA form; LLVM PHI nodes
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]677become machine code PHI nodes, and virtual registers are only allowed to have a
678single definition.</p>
679
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]680<p>After register allocation, machine code is no longer in SSA-form because there
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]681are no virtual registers left in the code.</p>
682
683</div>
684
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]685<!-- ======================================================================= -->
686<div class="doc_subsection">
687 <a name="machinebasicblock">The <tt>MachineBasicBlock</tt> class</a>
688</div>
689
690<div class="doc_text">
691
692<p>The <tt>MachineBasicBlock</tt> class contains a list of machine instructions
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]693(<tt><a href="#machineinstr">MachineInstr</a></tt> instances). It roughly
694corresponds to the LLVM code input to the instruction selector, but there can be
695a one-to-many mapping (i.e. one LLVM basic block can map to multiple machine
696basic blocks). The <tt>MachineBasicBlock</tt> class has a
697"<tt>getBasicBlock</tt>" method, which returns the LLVM basic block that it
698comes from.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]699
700</div>
701
702<!-- ======================================================================= -->
703<div class="doc_subsection">
704 <a name="machinefunction">The <tt>MachineFunction</tt> class</a>
705</div>
706
707<div class="doc_text">
708
709<p>The <tt>MachineFunction</tt> class contains a list of machine basic blocks
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]710(<tt><a href="#machinebasicblock">MachineBasicBlock</a></tt> instances). It
711corresponds one-to-one with the LLVM function input to the instruction selector.
712In addition to a list of basic blocks, the <tt>MachineFunction</tt> contains a
713a <tt>MachineConstantPool</tt>, a <tt>MachineFrameInfo</tt>, a
714<tt>MachineFunctionInfo</tt>, a <tt>SSARegMap</tt>, and a set of live in and
715live out registers for the function. See
716<tt>include/llvm/CodeGen/MachineFunction.h</tt> for more information.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]717
718</div>
719
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]720<!-- *********************************************************************** -->
721<div class="doc_section">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]722 <a name="codegenalgs">Target-independent code generation algorithms</a>
723</div>
724<!-- *********************************************************************** -->
725
726<div class="doc_text">
727
728<p>This section documents the phases described in the <a
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]729href="#high-level-design">high-level design of the code generator</a>. It
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]730explains how they work and some of the rationale behind their design.</p>
731
732</div>
733
734<!-- ======================================================================= -->
735<div class="doc_subsection">
736 <a name="instselect">Instruction Selection</a>
737</div>
738
739<div class="doc_text">
740<p>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]741Instruction Selection is the process of translating LLVM code presented to the
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]742code generator into target-specific machine instructions. There are several
743well-known ways to do this in the literature. In LLVM there are two main forms:
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]744the SelectionDAG based instruction selector framework and an old-style 'simple'
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]745instruction selector, which effectively peephole selects each LLVM instruction
746into a series of machine instructions. We recommend that all targets use the
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]747SelectionDAG infrastructure.
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]748</p>
749
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]750<p>Portions of the DAG instruction selector are generated from the target
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]751description (<tt>*.td</tt>) files. Our goal is for the entire instruction
752selector to be generated from these <tt>.td</tt> files.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]753</div>
754
755<!-- _______________________________________________________________________ -->
756<div class="doc_subsubsection">
757 <a name="selectiondag_intro">Introduction to SelectionDAGs</a>
758</div>
759
760<div class="doc_text">
761
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]762<p>The SelectionDAG provides an abstraction for code representation in a way
763that is amenable to instruction selection using automatic techniques
764(e.g. dynamic-programming based optimal pattern matching selectors). It is also
765well-suited to other phases of code generation; in particular,
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]766instruction scheduling (SelectionDAG's are very close to scheduling DAGs
767post-selection). Additionally, the SelectionDAG provides a host representation
768where a large variety of very-low-level (but target-independent)
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]769<a href="#selectiondag_optimize">optimizations</a> may be
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]770performed; ones which require extensive information about the instructions
771efficiently supported by the target.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]772
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]773<p>The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]774<tt>SDNode</tt> class. The primary payload of the <tt>SDNode</tt> is its
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]775operation code (Opcode) that indicates what operation the node performs and
776the operands to the operation.
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]777The various operation node types are described at the top of the
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]778<tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt> file.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]779
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]780<p>Although most operations define a single value, each node in the graph may
781define multiple values. For example, a combined div/rem operation will define
782both the dividend and the remainder. Many other situations require multiple
783values as well. Each node also has some number of operands, which are edges
784to the node defining the used value. Because nodes may define multiple values,
785edges are represented by instances of the <tt>SDOperand</tt> class, which is
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]786a <tt>&lt;SDNode, unsigned&gt;</tt> pair, indicating the node and result
787value being used, respectively. Each value produced by an <tt>SDNode</tt> has
788an associated <tt>MVT::ValueType</tt> indicating what type the value is.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]789
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]790<p>SelectionDAGs contain two different kinds of values: those that represent
791data flow and those that represent control flow dependencies. Data values are
792simple edges with an integer or floating point value type. Control edges are
793represented as "chain" edges which are of type <tt>MVT::Other</tt>. These edges
794provide an ordering between nodes that have side effects (such as
795loads, stores, calls, returns, etc). All nodes that have side effects should
796take a token chain as input and produce a new one as output. By convention,
797token chain inputs are always operand #0, and chain results are always the last
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]798value produced by an operation.</p>
799
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]800<p>A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is
801always a marker node with an Opcode of <tt>ISD::EntryToken</tt>. The Root node
802is the final side-effecting node in the token chain. For example, in a single
803basic block function it would be the return node.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]804
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]805<p>One important concept for SelectionDAGs is the notion of a "legal" vs.
806"illegal" DAG. A legal DAG for a target is one that only uses supported
807operations and supported types. On a 32-bit PowerPC, for example, a DAG with
808a value of type i1, i8, i16, or i64 would be illegal, as would a DAG that uses a
809SREM or UREM operation. The
810<a href="#selectiondag_legalize">legalize</a> phase is responsible for turning
811an illegal DAG into a legal DAG.</p>
812
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]813</div>
814
815<!-- _______________________________________________________________________ -->
816<div class="doc_subsubsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]817 <a name="selectiondag_process">SelectionDAG Instruction Selection Process</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]818</div>
819
820<div class="doc_text">
821
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]822<p>SelectionDAG-based instruction selection consists of the following steps:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]823
824<ol>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]825<li><a href="#selectiondag_build">Build initial DAG</a> - This stage
826 performs a simple translation from the input LLVM code to an illegal
827 SelectionDAG.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]828<li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> - This stage
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]829 performs simple optimizations on the SelectionDAG to simplify it, and
830 recognize meta instructions (like rotates and <tt>div</tt>/<tt>rem</tt>
831 pairs) for targets that support these meta operations. This makes the
832 resultant code more efficient and the <a href="#selectiondag_select">select
833 instructions from DAG</a> phase (below) simpler.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]834<li><a href="#selectiondag_legalize">Legalize SelectionDAG</a> - This stage
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]835 converts the illegal SelectionDAG to a legal SelectionDAG by eliminating
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]836 unsupported operations and data types.</li>
837<li><a href="#selectiondag_optimize">Optimize SelectionDAG (#2)</a> - This
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]838 second run of the SelectionDAG optimizes the newly legalized DAG to
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]839 eliminate inefficiencies introduced by legalization.</li>
840<li><a href="#selectiondag_select">Select instructions from DAG</a> - Finally,
841 the target instruction selector matches the DAG operations to target
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]842 instructions. This process translates the target-independent input DAG into
843 another DAG of target instructions.</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]844<li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]845 - The last phase assigns a linear order to the instructions in the
846 target-instruction DAG and emits them into the MachineFunction being
847 compiled. This step uses traditional prepass scheduling techniques.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]848</ol>
849
850<p>After all of these steps are complete, the SelectionDAG is destroyed and the
851rest of the code generation passes are run.</p>
852
Chris Lattnerdf921f02005-10-17 01:40:33 +0000[diff] [blame]853<p>One great way to visualize what is going on here is to take advantage of a
854few LLC command line options. In particular, the <tt>-view-isel-dags</tt>
855option pops up a window with the SelectionDAG input to the Select phase for all
856of the code compiled (if you only get errors printed to the console while using
857this, you probably <a href="ProgrammersManual.html#ViewGraph">need to configure
858your system</a> to add support for it). The <tt>-view-sched-dags</tt> option
859views the SelectionDAG output from the Select phase and input to the Scheduler
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]860phase.</p>
861
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]862</div>
863
864<!-- _______________________________________________________________________ -->
865<div class="doc_subsubsection">
866 <a name="selectiondag_build">Initial SelectionDAG Construction</a>
867</div>
868
869<div class="doc_text">
870
Bill Wendling16448772006-08-28 03:04:05 +0000[diff] [blame]871<p>The initial SelectionDAG is na&iuml;vely peephole expanded from the LLVM
872input by the <tt>SelectionDAGLowering</tt> class in the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]873<tt>lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp</tt> file. The intent of this
874pass is to expose as much low-level, target-specific details to the SelectionDAG
875as possible. This pass is mostly hard-coded (e.g. an LLVM <tt>add</tt> turns
876into an <tt>SDNode add</tt> while a <tt>geteelementptr</tt> is expanded into the
877obvious arithmetic). This pass requires target-specific hooks to lower calls,
878returns, varargs, etc. For these features, the
879<tt><a href="#targetlowering">TargetLowering</a></tt> interface is used.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]880
881</div>
882
883<!-- _______________________________________________________________________ -->
884<div class="doc_subsubsection">
885 <a name="selectiondag_legalize">SelectionDAG Legalize Phase</a>
886</div>
887
888<div class="doc_text">
889
890<p>The Legalize phase is in charge of converting a DAG to only use the types and
891operations that are natively supported by the target. This involves two major
892tasks:</p>
893
894<ol>
895<li><p>Convert values of unsupported types to values of supported types.</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]896 <p>There are two main ways of doing this: converting small types to
897 larger types ("promoting"), and breaking up large integer types
898 into smaller ones ("expanding"). For example, a target might require
899 that all f32 values are promoted to f64 and that all i1/i8/i16 values
900 are promoted to i32. The same target might require that all i64 values
901 be expanded into i32 values. These changes can insert sign and zero
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]902 extensions as needed to make sure that the final code has the same
903 behavior as the input.</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]904 <p>A target implementation tells the legalizer which types are supported
905 (and which register class to use for them) by calling the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]906 <tt>addRegisterClass</tt> method in its TargetLowering constructor.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]907</li>
908
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]909<li><p>Eliminate operations that are not supported by the target.</p>
910 <p>Targets often have weird constraints, such as not supporting every
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]911 operation on every supported datatype (e.g. X86 does not support byte
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]912 conditional moves and PowerPC does not support sign-extending loads from
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]913 a 16-bit memory location). Legalize takes care of this by open-coding
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]914 another sequence of operations to emulate the operation ("expansion"), by
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]915 promoting one type to a larger type that supports the operation
916 ("promotion"), or by using a target-specific hook to implement the
917 legalization ("custom").</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]918 <p>A target implementation tells the legalizer which operations are not
919 supported (and which of the above three actions to take) by calling the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]920 <tt>setOperationAction</tt> method in its <tt>TargetLowering</tt>
921 constructor.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]922</li>
923</ol>
924
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]925<p>Prior to the existance of the Legalize pass, we required that every target
926<a href="#selectiondag_optimize">selector</a> supported and handled every
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]927operator and type even if they are not natively supported. The introduction of
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]928the Legalize phase allows all of the cannonicalization patterns to be shared
929across targets, and makes it very easy to optimize the cannonicalized code
930because it is still in the form of a DAG.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]931
932</div>
933
934<!-- _______________________________________________________________________ -->
935<div class="doc_subsubsection">
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]936 <a name="selectiondag_optimize">SelectionDAG Optimization Phase: the DAG
937 Combiner</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]938</div>
939
940<div class="doc_text">
941
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]942<p>The SelectionDAG optimization phase is run twice for code generation: once
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]943immediately after the DAG is built and once after legalization. The first run
944of the pass allows the initial code to be cleaned up (e.g. performing
945optimizations that depend on knowing that the operators have restricted type
946inputs). The second run of the pass cleans up the messy code generated by the
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]947Legalize pass, which allows Legalize to be very simple (it can focus on making
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]948code legal instead of focusing on generating <em>good</em> and legal code).</p>
949
950<p>One important class of optimizations performed is optimizing inserted sign
951and zero extension instructions. We currently use ad-hoc techniques, but could
952move to more rigorous techniques in the future. Here are some good papers on
953the subject:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]954
955<p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]956 "<a href="http://www.eecs.harvard.edu/~nr/pubs/widen-abstract.html">Widening
957 integer arithmetic</a>"<br>
958 Kevin Redwine and Norman Ramsey<br>
959 International Conference on Compiler Construction (CC) 2004
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]960</p>
961
962
963<p>
964 "<a href="http://portal.acm.org/citation.cfm?doid=512529.512552">Effective
965 sign extension elimination</a>"<br>
966 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
967 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
968 and Implementation.
969</p>
970
971</div>
972
973<!-- _______________________________________________________________________ -->
974<div class="doc_subsubsection">
975 <a name="selectiondag_select">SelectionDAG Select Phase</a>
976</div>
977
978<div class="doc_text">
979
980<p>The Select phase is the bulk of the target-specific code for instruction
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]981selection. This phase takes a legal SelectionDAG as input, pattern matches the
982instructions supported by the target to this DAG, and produces a new DAG of
983target code. For example, consider the following LLVM fragment:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]984
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]985<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]986<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]987%t1 = add float %W, %X
988%t2 = mul float %t1, %Y
989%t3 = add float %t2, %Z
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]990</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]991</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]992
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]993<p>This LLVM code corresponds to a SelectionDAG that looks basically like
994this:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]995
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]996<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]997<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]998(fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]999</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1000</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1001
Chris Lattnera1ff9312005-10-17 15:19:24 +0000[diff] [blame]1002<p>If a target supports floating point multiply-and-add (FMA) operations, one
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1003of the adds can be merged with the multiply. On the PowerPC, for example, the
1004output of the instruction selector might look like this DAG:</p>
1005
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1006<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1007<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1008(FMADDS (FADDS W, X), Y, Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1009</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1010</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1011
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1012<p>The <tt>FMADDS</tt> instruction is a ternary instruction that multiplies its
1013first two operands and adds the third (as single-precision floating-point
1014numbers). The <tt>FADDS</tt> instruction is a simple binary single-precision
1015add instruction. To perform this pattern match, the PowerPC backend includes
1016the following instruction definitions:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1017
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1018<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1019<pre>
1020def FMADDS : AForm_1&lt;59, 29,
1021 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1022 "fmadds $FRT, $FRA, $FRC, $FRB",
1023 [<b>(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1024 F4RC:$FRB))</b>]&gt;;
1025def FADDS : AForm_2&lt;59, 21,
1026 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1027 "fadds $FRT, $FRA, $FRB",
1028 [<b>(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))</b>]&gt;;
1029</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1030</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1031
1032<p>The portion of the instruction definition in bold indicates the pattern used
1033to match the instruction. The DAG operators (like <tt>fmul</tt>/<tt>fadd</tt>)
1034are defined in the <tt>lib/Target/TargetSelectionDAG.td</tt> file.
1035"<tt>F4RC</tt>" is the register class of the input and result values.<p>
1036
1037<p>The TableGen DAG instruction selector generator reads the instruction
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1038patterns in the <tt>.td</tt> file and automatically builds parts of the pattern
1039matching code for your target. It has the following strengths:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1040
1041<ul>
1042<li>At compiler-compiler time, it analyzes your instruction patterns and tells
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1043 you if your patterns make sense or not.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1044<li>It can handle arbitrary constraints on operands for the pattern match. In
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1045 particular, it is straight-forward to say things like "match any immediate
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1046 that is a 13-bit sign-extended value". For examples, see the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1047 <tt>immSExt16</tt> and related <tt>tblgen</tt> classes in the PowerPC
1048 backend.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1049<li>It knows several important identities for the patterns defined. For
1050 example, it knows that addition is commutative, so it allows the
1051 <tt>FMADDS</tt> pattern above to match "<tt>(fadd X, (fmul Y, Z))</tt>" as
1052 well as "<tt>(fadd (fmul X, Y), Z)</tt>", without the target author having
1053 to specially handle this case.</li>
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1054<li>It has a full-featured type-inferencing system. In particular, you should
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1055 rarely have to explicitly tell the system what type parts of your patterns
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1056 are. In the <tt>FMADDS</tt> case above, we didn't have to tell
1057 <tt>tblgen</tt> that all of the nodes in the pattern are of type 'f32'. It
1058 was able to infer and propagate this knowledge from the fact that
1059 <tt>F4RC</tt> has type 'f32'.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1060<li>Targets can define their own (and rely on built-in) "pattern fragments".
1061 Pattern fragments are chunks of reusable patterns that get inlined into your
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1062 patterns during compiler-compiler time. For example, the integer
1063 "<tt>(not x)</tt>" operation is actually defined as a pattern fragment that
1064 expands as "<tt>(xor x, -1)</tt>", since the SelectionDAG does not have a
1065 native '<tt>not</tt>' operation. Targets can define their own short-hand
1066 fragments as they see fit. See the definition of '<tt>not</tt>' and
1067 '<tt>ineg</tt>' for examples.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1068<li>In addition to instructions, targets can specify arbitrary patterns that
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1069 map to one or more instructions using the 'Pat' class. For example,
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1070 the PowerPC has no way to load an arbitrary integer immediate into a
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1071 register in one instruction. To tell tblgen how to do this, it defines:
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1072 <br>
1073 <br>
1074 <div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1075 <pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1076// Arbitrary immediate support. Implement in terms of LIS/ORI.
1077def : Pat&lt;(i32 imm:$imm),
1078 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))&gt;;
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1079 </pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1080 </div>
1081 <br>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1082 If none of the single-instruction patterns for loading an immediate into a
1083 register match, this will be used. This rule says "match an arbitrary i32
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1084 immediate, turning it into an <tt>ORI</tt> ('or a 16-bit immediate') and an
1085 <tt>LIS</tt> ('load 16-bit immediate, where the immediate is shifted to the
1086 left 16 bits') instruction". To make this work, the
1087 <tt>LO16</tt>/<tt>HI16</tt> node transformations are used to manipulate the
1088 input immediate (in this case, take the high or low 16-bits of the
1089 immediate).</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1090<li>While the system does automate a lot, it still allows you to write custom
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1091 C++ code to match special cases if there is something that is hard to
1092 express.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1093</ul>
1094
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1095<p>While it has many strengths, the system currently has some limitations,
1096primarily because it is a work in progress and is not yet finished:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1097
1098<ul>
1099<li>Overall, there is no way to define or match SelectionDAG nodes that define
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1100 multiple values (e.g. <tt>ADD_PARTS</tt>, <tt>LOAD</tt>, <tt>CALL</tt>,
1101 etc). This is the biggest reason that you currently still <em>have to</em>
1102 write custom C++ code for your instruction selector.</li>
1103<li>There is no great way to support matching complex addressing modes yet. In
1104 the future, we will extend pattern fragments to allow them to define
1105 multiple values (e.g. the four operands of the <a href="#x86_memory">X86
1106 addressing mode</a>). In addition, we'll extend fragments so that a
1107 fragment can match multiple different patterns.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1108<li>We don't automatically infer flags like isStore/isLoad yet.</li>
1109<li>We don't automatically generate the set of supported registers and
1110 operations for the <a href="#"selectiondag_legalize>Legalizer</a> yet.</li>
1111<li>We don't have a way of tying in custom legalized nodes yet.</li>
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1112</ul>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1113
1114<p>Despite these limitations, the instruction selector generator is still quite
1115useful for most of the binary and logical operations in typical instruction
1116sets. If you run into any problems or can't figure out how to do something,
1117please let Chris know!</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1118
1119</div>
1120
1121<!-- _______________________________________________________________________ -->
1122<div class="doc_subsubsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1123 <a name="selectiondag_sched">SelectionDAG Scheduling and Formation Phase</a>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1124</div>
1125
1126<div class="doc_text">
1127
1128<p>The scheduling phase takes the DAG of target instructions from the selection
1129phase and assigns an order. The scheduler can pick an order depending on
1130various constraints of the machines (i.e. order for minimal register pressure or
1131try to cover instruction latencies). Once an order is established, the DAG is
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1132converted to a list of <tt><a href="#machineinstr">MachineInstr</a></tt>s and
1133the SelectionDAG is destroyed.</p>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1134
Jeff Cohen0b81cda2005-10-24 16:54:55 +0000[diff] [blame]1135<p>Note that this phase is logically separate from the instruction selection
Chris Lattnerc38959f2005-10-17 03:09:31 +0000[diff] [blame]1136phase, but is tied to it closely in the code because it operates on
1137SelectionDAGs.</p>
1138
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1139</div>
1140
1141<!-- _______________________________________________________________________ -->
1142<div class="doc_subsubsection">
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1143 <a name="selectiondag_future">Future directions for the SelectionDAG</a>
1144</div>
1145
1146<div class="doc_text">
1147
1148<ol>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1149<li>Optional function-at-a-time selection.</li>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1150<li>Auto-generate entire selector from <tt>.td</tt> file.</li>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1151</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1152</ol>
1153
1154</div>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1155
1156<!-- ======================================================================= -->
1157<div class="doc_subsection">
1158 <a name="ssamco">SSA-based Machine Code Optimizations</a>
1159</div>
1160<div class="doc_text"><p>To Be Written</p></div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1161
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1162<!-- ======================================================================= -->
1163<div class="doc_subsection">
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1164 <a name="liveintervals">Live Intervals</a>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1165</div>
1166
1167<div class="doc_text">
1168
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1169<p>Live Intervals are the ranges (intervals) where a variable is <i>live</i>.
1170They are used by some <a href="#regalloc">register allocator</a> passes to
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1171determine if two or more virtual registers which require the same physical
Bill Wendling41b32522006-09-07 08:39:35 +0000[diff] [blame]1172register are live at the same point in the program (i.e., they conflict). When
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1173this situation occurs, one virtual register must be <i>spilled</i>.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1174
1175</div>
1176
1177<!-- _______________________________________________________________________ -->
1178<div class="doc_subsubsection">
1179 <a name="livevariable_analysis">Live Variable Analysis</a>
1180</div>
1181
1182<div class="doc_text">
1183
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1184<p>The first step in determining the live intervals of variables is to
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1185calculate the set of registers that are immediately dead after the
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1186instruction (i.e., the instruction calculates the value, but it is
1187never used) and the set of registers that are used by the instruction,
1188but are never used after the instruction (i.e., they are killed). Live
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1189variable information is computed for each <i>virtual</i> register and
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1190<i>register allocatable</i> physical register in the function. This
1191is done in a very efficient manner because it uses SSA to sparsely
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1192compute lifetime information for virtual registers (which are in SSA
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1193form) and only has to track physical registers within a block. Before
1194register allocation, LLVM can assume that physical registers are only
1195live within a single basic block. This allows it to do a single,
1196local analysis to resolve physical register lifetimes within each
1197basic block. If a physical register is not register allocatable (e.g.,
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1198a stack pointer or condition codes), it is not tracked.</p>
1199
1200<p>Physical registers may be live in to or out of a function. Live in values
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1201are typically arguments in registers. Live out values are typically return
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1202values in registers. Live in values are marked as such, and are given a dummy
Bill Wendlingbd0d7b52006-09-07 08:36:28 +0000[diff] [blame]1203"defining" instruction during live intervals analysis. If the last basic block
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1204of a function is a <tt>return</tt>, then it's marked as using all live out
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1205values in the function.</p>
1206
1207<p><tt>PHI</tt> nodes need to be handled specially, because the calculation
1208of the live variable information from a depth first traversal of the CFG of
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1209the function won't guarantee that a virtual register used by the <tt>PHI</tt>
1210node is defined before it's used. When a <tt>PHI</tt> node is encounted, only
1211the definition is handled, because the uses will be handled in other basic
1212blocks.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1213
1214<p>For each <tt>PHI</tt> node of the current basic block, we simulate an
1215assignment at the end of the current basic block and traverse the successor
1216basic blocks. If a successor basic block has a <tt>PHI</tt> node and one of
1217the <tt>PHI</tt> node's operands is coming from the current basic block,
1218then the variable is marked as <i>alive</i> within the current basic block
1219and all of its predecessor basic blocks, until the basic block with the
1220defining instruction is encountered.</p>
1221
1222</div>
1223
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1224<!-- _______________________________________________________________________ -->
1225<div class="doc_subsubsection">
1226 <a name="liveintervals_analysis">Live Intervals Analysis</a>
1227</div>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1228
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1229<div class="doc_text">
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1230
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1231<p>We now have the information available to perform the live intervals analysis
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1232and build the live intervals themselves. We start off by numbering the basic
1233blocks and machine instructions. We then handle the "live-in" values. These
1234are in physical registers, so the physical register is assumed to be killed by
1235the end of the basic block. Live intervals for virtual registers are computed
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1236for some ordering of the machine instructions <tt>[1, N]</tt>. A live interval
1237is an interval <tt>[i, j)</tt>, where <tt>1 <= i <= j < N</tt>, for which a
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1238variable is live.</p>
1239
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1240<p><i><b>More to come...</b></i></p>
1241
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1242</ol>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1243
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1244</div>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1245
1246<!-- ======================================================================= -->
1247<div class="doc_subsection">
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1248 <a name="regalloc">Register Allocation</a>
1249</div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1250
1251<div class="doc_text">
1252
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1253<p>The <i>Register Allocation problem</i> consists in mapping a program
1254<i>P<sub>v</sub></i>, that can use an unbounded number of virtual
1255registers, to a program <i>P<sub>p</sub></i> that contains a finite
1256(possibly small) number of physical registers. Each target architecture has
1257a different number of physical registers. If the number of physical
1258registers is not enough to accommodate all the virtual registers, some of
1259them will have to be mapped into memory. These virtuals are called
1260<i>spilled virtuals</i>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1261
1262</div>
1263
1264<!-- _______________________________________________________________________ -->
1265
1266<div class="doc_subsubsection">
1267 <a name="regAlloc_represent">How registers are represented in LLVM</a>
1268</div>
1269
1270<div class="doc_text">
1271
1272<p>In LLVM, physical registers are denoted by integer numbers that
1273normally range from 1 to 1023. To see how this numbering is defined
1274for a particular architecture, you can read the
1275<tt>GenRegisterNames.inc</tt> file for that architecture. For
1276instance, by inspecting
1277<tt>lib/Target/X86/X86GenRegisterNames.inc</tt> we see that the 32-bit
1278register <tt>EAX</tt> is denoted by 15, and the MMX register
1279<tt>MM0</tt> is mapped to 48.</p>
1280
1281<p>Some architectures contain registers that share the same physical
1282location. A notable example is the X86 platform. For instance, in the
1283X86 architecture, the registers <tt>EAX</tt>, <tt>AX</tt> and
1284<tt>AL</tt> share the first eight bits. These physical registers are
1285marked as <i>aliased</i> in LLVM. Given a particular architecture, you
1286can check which registers are aliased by inspecting its
1287<tt>RegisterInfo.td</tt> file. Moreover, the method
1288<tt>MRegisterInfo::getAliasSet(p_reg)</tt> returns an array containing
1289all the physical registers aliased to the register <tt>p_reg</tt>.</p>
1290
1291<p>Physical registers, in LLVM, are grouped in <i>Register Classes</i>.
1292Elements in the same register class are functionally equivalent, and can
1293be interchangeably used. Each virtual register can only be mapped to
1294physical registers of a particular class. For instance, in the X86
1295architecture, some virtuals can only be allocated to 8 bit registers.
1296A register class is described by <tt>TargetRegisterClass</tt> objects.
1297To discover if a virtual register is compatible with a given physical,
1298this code can be used:
1299</p>
1300
1301<div class="doc_code">
1302<pre>
1303bool RegMapping_Fer::compatible_class(MachineFunction &mf,
1304 unsigned v_reg,
1305 unsigned p_reg) {
1306 assert(MRegisterInfo::isPhysicalRegister(p_reg) &&
1307 "Target register must be physical");
1308 const TargetRegisterClass *trc = mf.getSSARegMap()->getRegClass(v_reg);
1309 return trc->contains(p_reg);
1310}
1311</pre>
1312</div>
1313
1314<p>Sometimes, mostly for debugging purposes, it is useful to change
1315the number of physical registers available in the target
1316architecture. This must be done statically, inside the
1317<tt>TargetRegsterInfo.td</tt> file. Just <tt>grep</tt> for
1318<tt>RegisterClass</tt>, the last parameter of which is a list of
1319registers. Just commenting some out is one simple way to avoid them
1320being used. A more polite way is to explicitly exclude some registers
1321from the <i>allocation order</i>. See the definition of the
1322<tt>GR</tt> register class in
1323<tt>lib/Target/IA64/IA64RegisterInfo.td</tt> for an example of this
1324(e.g., <tt>numReservedRegs</tt> registers are hidden.)</p>
1325
1326<p>Virtual registers are also denoted by integer numbers. Contrary to
1327physical registers, different virtual registers never share the same
1328number. The smallest virtual register is normally assigned the number
13291024. This may change, so, in order to know which is the first virtual
1330register, you should access
1331<tt>MRegisterInfo::FirstVirtualRegister</tt>. Any register whose
1332number is greater than or equal to
1333<tt>MRegisterInfo::FirstVirtualRegister</tt> is considered a virtual
1334register. Whereas physical registers are statically defined in a
1335<tt>TargetRegisterInfo.td</tt> file and cannot be created by the
1336application developer, that is not the case with virtual registers.
1337In order to create new virtual registers, use the method
1338<tt>SSARegMap::createVirtualRegister()</tt>. This method will return a
1339virtual register with the highest code.
1340</p>
1341
1342<p>Before register allocation, the operands of an instruction are
1343mostly virtual registers, although physical registers may also be
1344used. In order to check if a given machine operand is a register, use
1345the boolean function <tt>MachineOperand::isRegister()</tt>. To obtain
1346the integer code of a register, use
1347<tt>MachineOperand::getReg()</tt>. An instruction may define or use a
1348register. For instance, <tt>ADD reg:1026 := reg:1025 reg:1024</tt>
1349defines the registers 1024, and uses registers 1025 and 1026. Given a
1350register operand, the method <tt>MachineOperand::isUse()</tt> informs
1351if that register is being used by the instruction. The method
1352<tt>MachineOperand::isDef()</tt> informs if that registers is being
1353defined.</p>
1354
1355<p>We will call physical registers present in the LLVM bytecode before
1356register allocation <i>pre-colored registers</i>. Pre-colored
1357registers are used in many different situations, for instance, to pass
1358parameters of functions calls, and to store results of particular
1359instructions. There are two types of pre-colored registers: the ones
1360<i>implicitly</i> defined, and those <i>explicitly</i>
1361defined. Explicitly defined registers are normal operands, and can be
1362accessed with <tt>MachineInstr::getOperand(int)::getReg()</tt>. In
1363order to check which registers are implicitly defined by an
1364instruction, use the
1365<tt>TargetInstrInfo::get(opcode)::ImplicitDefs</tt>, where
1366<tt>opcode</tt> is the opcode of the target instruction. One important
1367difference between explicit and implicit physical registers is that
1368the latter are defined statically for each instruction, whereas the
1369former may vary depending on the program being compiled. For example,
1370an instruction that represents a function call will always implicitly
1371define or use the same set of physical registers. To read the
1372registers implicitly used by an instruction, use
1373<tt>TargetInstrInfo::get(opcode)::ImplicitUses</tt>. Pre-colored
1374registers impose constraints on any register allocation algorithm. The
1375register allocator must make sure that none of them is been
1376overwritten by the values of virtual registers while still alive.</p>
1377
1378</div>
1379
1380<!-- _______________________________________________________________________ -->
1381
1382<div class="doc_subsubsection">
1383 <a name="regAlloc_howTo">Mapping virtual registers to physical registers</a>
1384</div>
1385
1386<div class="doc_text">
1387
1388<p>There are two ways to map virtual registers to physical registers (or to
1389memory slots). The first way, that we will call <i>direct mapping</i>,
1390is based on the use of methods of the classes <tt>MRegisterInfo</tt>,
1391and <tt>MachineOperand</tt>. The second way, that we will call
1392<i>indirect mapping</i>, relies on the <tt>VirtRegMap</tt> class in
1393order to insert loads and stores sending and getting values to and from
1394memory.</p>
1395
1396<p>The direct mapping provides more flexibility to the developer of
1397the register allocator; however, it is more error prone, and demands
1398more implementation work. Basically, the programmer will have to
1399specify where load and store instructions should be inserted in the
1400target function being compiled in order to get and store values in
1401memory. To assign a physical register to a virtual register present in
1402a given operand, use <tt>MachineOperand::setReg(p_reg)</tt>. To insert
1403a store instruction, use
1404<tt>MRegisterInfo::storeRegToStackSlot(...)</tt>, and to insert a load
1405instruction, use <tt>MRegisterInfo::loadRegFromStackSlot</tt>.</p>
1406
1407<p>The indirect mapping shields the application developer from the
1408complexities of inserting load and store instructions. In order to map
1409a virtual register to a physical one, use
1410<tt>VirtRegMap::assignVirt2Phys(vreg, preg)</tt>. In order to map a
1411certain virtual register to memory, use
1412<tt>VirtRegMap::assignVirt2StackSlot(vreg)</tt>. This method will
1413return the stack slot where <tt>vreg</tt>'s value will be located. If
1414it is necessary to map another virtual register to the same stack
1415slot, use <tt>VirtRegMap::assignVirt2StackSlot(vreg,
1416stack_location)</tt>. One important point to consider when using the
1417indirect mapping, is that even if a virtual register is mapped to
1418memory, it still needs to be mapped to a physical register. This
1419physical register is the location where the virtual register is
1420supposed to be found before being stored or after being reloaded.</p>
1421
1422<p>If the indirect strategy is used, after all the virtual registers
1423have been mapped to physical registers or stack slots, it is necessary
1424to use a spiller object to place load and store instructions in the
1425code. Every virtual that has been mapped to a stack slot will be
1426stored to memory after been defined and will be loaded before being
1427used. The implementation of the spiller tries to recycle load/store
1428instructions, avoiding unnecessary instructions. For an example of how
1429to invoke the spiller, see
1430<tt>RegAllocLinearScan::runOnMachineFunction</tt> in
1431<tt>lib/CodeGen/RegAllocLinearScan.cpp</tt>.</p>
1432
1433</div>
1434
1435<!-- _______________________________________________________________________ -->
1436<div class="doc_subsubsection">
1437 <a name="regAlloc_twoAddr">Handling two address instructions</a>
1438</div>
1439
1440<div class="doc_text">
1441
1442<p>With very rare exceptions (e.g., function calls), the LLVM machine
1443code instructions are three address instructions. That is, each
1444instruction is expected to define at most one register, and to use at
1445most two registers. However, some architectures use two address
1446instructions. In this case, the defined register is also one of the
1447used register. For instance, an instruction such as <tt>ADD %EAX,
1448%EBX</tt>, in X86 is actually equivalent to <tt>%EAX = %EAX +
1449%EBX</tt>.</p>
1450
1451<p>In order to produce correct code, LLVM must convert three address
1452instructions that represent two address instructions into true two
1453address instructions. LLVM provides the pass
1454<tt>TwoAddressInstructionPass</tt> for this specific purpose. It must
1455be run before register allocation takes place. After its execution,
1456the resulting code may no longer be in SSA form. This happens, for
1457instance, in situations where an instruction such as <tt>%a = ADD %b
1458%c</tt> is converted to two instructions such as:</p>
1459
1460<div class="doc_code">
1461<pre>
1462%a = MOVE %b
1463%a = ADD %a %b
1464</pre>
1465</div>
1466
1467<p>Notice that, internally, the second instruction is represented as
1468<tt>ADD %a[def/use] %b</tt>. I.e., the register operand <tt>%a</tt> is
1469both used and defined by the instruction.</p>
1470
1471</div>
1472
1473<!-- _______________________________________________________________________ -->
1474<div class="doc_subsubsection">
1475 <a name="regAlloc_ssaDecon">The SSA deconstruction phase</a>
1476</div>
1477
1478<div class="doc_text">
1479
1480<p>An important transformation that happens during register allocation is called
1481the <i>SSA Deconstruction Phase</i>. The SSA form simplifies many
1482analyses that are performed on the control flow graph of
1483programs. However, traditional instruction sets do not implement
1484PHI instructions. Thus, in order to generate executable code, compilers
1485must replace PHI instructions with other instructions that preserve their
1486semantics.</p>
1487
1488<p>There are many ways in which PHI instructions can safely be removed
1489from the target code. The most traditional PHI deconstruction
1490algorithm replaces PHI instructions with copy instructions. That is
1491the strategy adopted by LLVM. The SSA deconstruction algorithm is
1492implemented in n<tt>lib/CodeGen/>PHIElimination.cpp</tt>. In order to
1493invoke this pass, the identifier <tt>PHIEliminationID</tt> must be
1494marked as required in the code of the register allocator.</p>
1495
1496</div>
1497
1498<!-- _______________________________________________________________________ -->
1499<div class="doc_subsubsection">
1500 <a name="regAlloc_fold">Instruction folding</a>
1501</div>
1502
1503<div class="doc_text">
1504
1505<p><i>Instruction folding</i> is an optimization performed during
1506register allocation that removes unnecessary copy instructions. For
1507instance, a sequence of instructions such as:</p>
1508
1509<div class="doc_code">
1510<pre>
1511%EBX = LOAD %mem_address
1512%EAX = COPY %EBX
1513</pre>
1514</div>
1515
1516<p>can be safely substituted by the single instruction:
1517
1518<div class="doc_code">
1519<pre>
1520%EAX = LOAD %mem_address
1521</pre>
1522</div>
1523
1524<p>Instructions can be folded with the
1525<tt>MRegisterInfo::foldMemoryOperand(...)</tt> method. Care must be
1526taken when folding instructions; a folded instruction can be quite
1527different from the original instruction. See
1528<tt>LiveIntervals::addIntervalsForSpills</tt> in
1529<tt>lib/CodeGen/LiveIntervalAnalysis.cpp</tt> for an example of its use.</p>
1530
1531</div>
1532
1533<!-- _______________________________________________________________________ -->
1534
1535<div class="doc_subsubsection">
1536 <a name="regAlloc_builtIn">Built in register allocators</a>
1537</div>
1538
1539<div class="doc_text">
1540
1541<p>The LLVM infrastructure provides the application developer with
1542three different register allocators:</p>
1543
1544<ul>
1545 <li><i>Simple</i> - This is a very simple implementation that does
1546 not keep values in registers across instructions. This register
1547 allocator immediately spills every value right after it is
1548 computed, and reloads all used operands from memory to temporary
1549 registers before each instruction.</li>
1550 <li><i>Local</i> - This register allocator is an improvement on the
1551 <i>Simple</i> implementation. It allocates registers on a basic
1552 block level, attempting to keep values in registers and reusing
1553 registers as appropriate.</li>
1554 <li><i>Linear Scan</i> - <i>The default allocator</i>. This is the
1555 well-know linear scan register allocator. Whereas the
1556 <i>Simple</i> and <i>Local</i> algorithms use a direct mapping
1557 implementation technique, the <i>Linear Scan</i> implementation
1558 uses a spiller in order to place load and stores.</li>
1559</ul>
1560
1561<p>The type of register allocator used in <tt>llc</tt> can be chosen with the
1562command line option <tt>-regalloc=...</tt>:</p>
1563
1564<div class="doc_code">
1565<pre>
1566$ llc -f -regalloc=simple file.bc -o sp.s;
1567$ llc -f -regalloc=local file.bc -o lc.s;
1568$ llc -f -regalloc=linearscan file.bc -o ln.s;
1569</pre>
1570</div>
1571
1572</div>
1573
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1574<!-- ======================================================================= -->
1575<div class="doc_subsection">
1576 <a name="proepicode">Prolog/Epilog Code Insertion</a>
1577</div>
1578<div class="doc_text"><p>To Be Written</p></div>
1579<!-- ======================================================================= -->
1580<div class="doc_subsection">
1581 <a name="latemco">Late Machine Code Optimizations</a>
1582</div>
1583<div class="doc_text"><p>To Be Written</p></div>
1584<!-- ======================================================================= -->
1585<div class="doc_subsection">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1586 <a name="codeemit">Code Emission</a>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1587</div>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1588<div class="doc_text"><p>To Be Written</p></div>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1589<!-- _______________________________________________________________________ -->
1590<div class="doc_subsubsection">
1591 <a name="codeemit_asm">Generating Assembly Code</a>
1592</div>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1593<div class="doc_text"><p>To Be Written</p></div>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1594<!-- _______________________________________________________________________ -->
1595<div class="doc_subsubsection">
1596 <a name="codeemit_bin">Generating Binary Machine Code</a>
1597</div>
1598
1599<div class="doc_text">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1600 <p>For the JIT or <tt>.o</tt> file writer</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1601</div>
1602
1603
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1604<!-- *********************************************************************** -->
1605<div class="doc_section">
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1606 <a name="targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1607</div>
1608<!-- *********************************************************************** -->
1609
1610<div class="doc_text">
1611
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1612<p>This section of the document explains features or design decisions that
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1613are specific to the code generator for a particular target.</p>
1614
1615</div>
1616
1617
1618<!-- ======================================================================= -->
1619<div class="doc_subsection">
1620 <a name="x86">The X86 backend</a>
1621</div>
1622
1623<div class="doc_text">
1624
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1625<p>The X86 code generator lives in the <tt>lib/Target/X86</tt> directory. This
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1626code generator currently targets a generic P6-like processor. As such, it
1627produces a few P6-and-above instructions (like conditional moves), but it does
1628not make use of newer features like MMX or SSE. In the future, the X86 backend
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1629will have sub-target support added for specific processor families and
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1630implementations.</p>
1631
1632</div>
1633
1634<!-- _______________________________________________________________________ -->
1635<div class="doc_subsubsection">
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1636 <a name="x86_tt">X86 Target Triples Supported</a>
1637</div>
1638
1639<div class="doc_text">
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1640
1641<p>The following are the known target triples that are supported by the X86
1642backend. This is not an exhaustive list, and it would be useful to add those
1643that people test.</p>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1644
1645<ul>
1646<li><b>i686-pc-linux-gnu</b> - Linux</li>
1647<li><b>i386-unknown-freebsd5.3</b> - FreeBSD 5.3</li>
1648<li><b>i686-pc-cygwin</b> - Cygwin on Win32</li>
1649<li><b>i686-pc-mingw32</b> - MingW on Win32</li>
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]1650<li><b>i386-pc-mingw32msvc</b> - MingW crosscompiler on Linux</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1651<li><b>i686-apple-darwin*</b> - Apple Darwin on X86</li>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]1652</ul>
1653
1654</div>
1655
1656<!-- _______________________________________________________________________ -->
1657<div class="doc_subsubsection">
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]1658 <a name="x86_cc">X86 Calling Conventions supported</a>
1659</div>
1660
1661
1662<div class="doc_text">
1663
1664<p>The folowing target-specific calling conventions are known to backend:</p>
1665
1666<ul>
1667<li><b>x86_StdCall</b> - stdcall calling convention seen on Microsoft Windows
1668platform (CC ID = 64).</li>
1669<li><b>x86_FastCall</b> - fastcall calling convention seen on Microsoft Windows
1670platform (CC ID = 65).</li>
1671</ul>
1672
1673</div>
1674
1675<!-- _______________________________________________________________________ -->
1676<div class="doc_subsubsection">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1677 <a name="x86_memory">Representing X86 addressing modes in MachineInstrs</a>
1678</div>
1679
1680<div class="doc_text">
1681
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1682<p>The x86 has a very flexible way of accessing memory. It is capable of
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1683forming memory addresses of the following expression directly in integer
1684instructions (which use ModR/M addressing):</p>
1685
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1686<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1687<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1688Base + [1,2,4,8] * IndexReg + Disp32
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1689</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1690</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1691
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]1692<p>In order to represent this, LLVM tracks no less than 4 operands for each
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1693memory operand of this form. This means that the "load" form of '<tt>mov</tt>'
1694has the following <tt>MachineOperand</tt>s in this order:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1695
1696<pre>
1697Index: 0 | 1 2 3 4
1698Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement
1699OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm
1700</pre>
1701
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1702<p>Stores, and all other instructions, treat the four memory operands in the
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1703same way and in the same order.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1704
1705</div>
1706
1707<!-- _______________________________________________________________________ -->
1708<div class="doc_subsubsection">
1709 <a name="x86_names">Instruction naming</a>
1710</div>
1711
1712<div class="doc_text">
1713
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1714<p>An instruction name consists of the base name, a default operand size, and a
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1715a character per operand with an optional special size. For example:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]1716
1717<p>
1718<tt>ADD8rr</tt> -&gt; add, 8-bit register, 8-bit register<br>
1719<tt>IMUL16rmi</tt> -&gt; imul, 16-bit register, 16-bit memory, 16-bit immediate<br>
1720<tt>IMUL16rmi8</tt> -&gt; imul, 16-bit register, 16-bit memory, 8-bit immediate<br>
1721<tt>MOVSX32rm16</tt> -&gt; movsx, 32-bit register, 16-bit memory
1722</p>
1723
1724</div>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]1725
1726<!-- *********************************************************************** -->
1727<hr>
1728<address>
1729 <a href="http://jigsaw.w3.org/css-validator/check/referer"><img
1730 src="http://jigsaw.w3.org/css-validator/images/vcss" alt="Valid CSS!"></a>
1731 <a href="http://validator.w3.org/check/referer"><img
1732 src="http://www.w3.org/Icons/valid-html401" alt="Valid HTML 4.01!" /></a>
1733
1734 <a href="mailto:sabre@nondot.org">Chris Lattner</a><br>
Reid Spencer05fe4b02006-03-14 05:39:39 +0000[diff] [blame]1735 <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]1736 Last modified: $Date$
1737</address>
1738
1739</body>
1740</html>