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Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]6 <title>The LLVM Target-Independent Code Generator</title>
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21
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]22<h1>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]23 The LLVM Target-Independent Code Generator
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]24</h1>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]25
26<ol>
27 <li><a href="#introduction">Introduction</a>
28 <ul>
29 <li><a href="#required">Required components in the code generator</a></li>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]30 <li><a href="#high-level-design">The high-level design of the code
31 generator</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]32 <li><a href="#tablegen">Using TableGen for target description</a></li>
33 </ul>
34 </li>
35 <li><a href="#targetdesc">Target description classes</a>
36 <ul>
37 <li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
38 <li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]39 <li><a href="#targetlowering">The <tt>TargetLowering</tt> class</a></li>
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]40 <li><a href="#targetregisterinfo">The <tt>TargetRegisterInfo</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]41 <li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
42 <li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]43 <li><a href="#targetsubtarget">The <tt>TargetSubtarget</tt> class</a></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]44 <li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
45 </ul>
46 </li>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]47 <li><a href="#codegendesc">The "Machine" Code Generator classes</a>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]48 <ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]49 <li><a href="#machineinstr">The <tt>MachineInstr</tt> class</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]50 <li><a href="#machinebasicblock">The <tt>MachineBasicBlock</tt>
51 class</a></li>
52 <li><a href="#machinefunction">The <tt>MachineFunction</tt> class</a></li>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]53 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]54 </li>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]55 <li><a href="#mc">The "MC" Layer</a>
56 <ul>
57 <li><a href="#mcstreamer">The <tt>MCStreamer</tt> API</a></li>
58 <li><a href="#mccontext">The <tt>MCContext</tt> class</a>
59 <li><a href="#mcsymbol">The <tt>MCSymbol</tt> class</a></li>
60 <li><a href="#mcsection">The <tt>MCSection</tt> class</a></li>
61 <li><a href="#mcinst">The <tt>MCInst</tt> class</a></li>
62 </ul>
63 </li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]64 <li><a href="#codegenalgs">Target-independent code generation algorithms</a>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]65 <ul>
66 <li><a href="#instselect">Instruction Selection</a>
67 <ul>
68 <li><a href="#selectiondag_intro">Introduction to SelectionDAGs</a></li>
69 <li><a href="#selectiondag_process">SelectionDAG Code Generation
70 Process</a></li>
71 <li><a href="#selectiondag_build">Initial SelectionDAG
72 Construction</a></li>
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]73 <li><a href="#selectiondag_legalize_types">SelectionDAG LegalizeTypes Phase</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]74 <li><a href="#selectiondag_legalize">SelectionDAG Legalize Phase</a></li>
75 <li><a href="#selectiondag_optimize">SelectionDAG Optimization
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]76 Phase: the DAG Combiner</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]77 <li><a href="#selectiondag_select">SelectionDAG Select Phase</a></li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]78 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]79 Phase</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]80 <li><a href="#selectiondag_future">Future directions for the
81 SelectionDAG</a></li>
82 </ul></li>
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]83 <li><a href="#liveintervals">Live Intervals</a>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]84 <ul>
85 <li><a href="#livevariable_analysis">Live Variable Analysis</a></li>
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]86 <li><a href="#liveintervals_analysis">Live Intervals Analysis</a></li>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]87 </ul></li>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]88 <li><a href="#regalloc">Register Allocation</a>
89 <ul>
90 <li><a href="#regAlloc_represent">How registers are represented in
91 LLVM</a></li>
92 <li><a href="#regAlloc_howTo">Mapping virtual registers to physical
93 registers</a></li>
94 <li><a href="#regAlloc_twoAddr">Handling two address instructions</a></li>
95 <li><a href="#regAlloc_ssaDecon">The SSA deconstruction phase</a></li>
96 <li><a href="#regAlloc_fold">Instruction folding</a></li>
97 <li><a href="#regAlloc_builtIn">Built in register allocators</a></li>
98 </ul></li>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]99 <li><a href="#codeemit">Code Emission</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]100 </ul>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]101 </li>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]102 <li><a href="#nativeassembler">Implementing a Native Assembler</a></li>
103
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]104 <li><a href="#targetimpls">Target-specific Implementation Notes</a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]105 <ul>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]106 <li><a href="#targetfeatures">Target Feature Matrix</a></li>
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]107 <li><a href="#tailcallopt">Tail call optimization</a></li>
Evan Chengdc444e92010-03-08 21:05:02 +0000[diff] [blame]108 <li><a href="#sibcallopt">Sibling call optimization</a></li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]109 <li><a href="#x86">The X86 backend</a></li>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]110 <li><a href="#ppc">The PowerPC backend</a>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]111 <ul>
112 <li><a href="#ppc_abi">LLVM PowerPC ABI</a></li>
113 <li><a href="#ppc_frame">Frame Layout</a></li>
114 <li><a href="#ppc_prolog">Prolog/Epilog</a></li>
115 <li><a href="#ppc_dynamic">Dynamic Allocation</a></li>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]116 </ul></li>
Justin Holewinskidceb0022011-08-11 17:34:16 +0000[diff] [blame]117 <li><a href="#ptx">The PTX backend</a></li>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]118 </ul></li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]119
120</ol>
121
122<div class="doc_author">
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]123 <p>Written by the LLVM Team.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]124</div>
125
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]126<div class="doc_warning">
127 <p>Warning: This is a work in progress.</p>
128</div>
129
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]130<!-- *********************************************************************** -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]131<h2>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]132 <a name="introduction">Introduction</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]133</h2>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]134<!-- *********************************************************************** -->
135
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]136<div>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]137
138<p>The LLVM target-independent code generator is a framework that provides a
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]139 suite of reusable components for translating the LLVM internal representation
140 to the machine code for a specified target&mdash;either in assembly form
141 (suitable for a static compiler) or in binary machine code format (usable for
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]142 a JIT compiler). The LLVM target-independent code generator consists of six
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]143 main components:</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]144
145<ol>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]146 <li><a href="#targetdesc">Abstract target description</a> interfaces which
147 capture important properties about various aspects of the machine,
148 independently of how they will be used. These interfaces are defined in
149 <tt>include/llvm/Target/</tt>.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]150
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]151 <li>Classes used to represent the <a href="#codegendesc">code being
152 generated</a> for a target. These classes are intended to be abstract
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]153 enough to represent the machine code for <i>any</i> target machine. These
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]154 classes are defined in <tt>include/llvm/CodeGen/</tt>. At this level,
155 concepts like "constant pool entries" and "jump tables" are explicitly
156 exposed.</li>
157
158 <li>Classes and algorithms used to represent code as the object file level,
159 the <a href="#mc">MC Layer</a>. These classes represent assembly level
160 constructs like labels, sections, and instructions. At this level,
161 concepts like "constant pool entries" and "jump tables" don't exist.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]162
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]163 <li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
164 various phases of native code generation (register allocation, scheduling,
165 stack frame representation, etc). This code lives
166 in <tt>lib/CodeGen/</tt>.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]167
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]168 <li><a href="#targetimpls">Implementations of the abstract target description
169 interfaces</a> for particular targets. These machine descriptions make
170 use of the components provided by LLVM, and can optionally provide custom
171 target-specific passes, to build complete code generators for a specific
172 target. Target descriptions live in <tt>lib/Target/</tt>.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]173
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]174 <li><a href="#jit">The target-independent JIT components</a>. The LLVM JIT is
175 completely target independent (it uses the <tt>TargetJITInfo</tt>
176 structure to interface for target-specific issues. The code for the
177 target-independent JIT lives in <tt>lib/ExecutionEngine/JIT</tt>.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]178</ol>
179
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]180<p>Depending on which part of the code generator you are interested in working
181 on, different pieces of this will be useful to you. In any case, you should
182 be familiar with the <a href="#targetdesc">target description</a>
183 and <a href="#codegendesc">machine code representation</a> classes. If you
184 want to add a backend for a new target, you will need
185 to <a href="#targetimpls">implement the target description</a> classes for
186 your new target and understand the <a href="LangRef.html">LLVM code
187 representation</a>. If you are interested in implementing a
188 new <a href="#codegenalgs">code generation algorithm</a>, it should only
189 depend on the target-description and machine code representation classes,
190 ensuring that it is portable.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]191
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]192<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]193<h3>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]194 <a name="required">Required components in the code generator</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]195</h3>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]196
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]197<div>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]198
199<p>The two pieces of the LLVM code generator are the high-level interface to the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]200 code generator and the set of reusable components that can be used to build
201 target-specific backends. The two most important interfaces
202 (<a href="#targetmachine"><tt>TargetMachine</tt></a>
203 and <a href="#targetdata"><tt>TargetData</tt></a>) are the only ones that are
204 required to be defined for a backend to fit into the LLVM system, but the
205 others must be defined if the reusable code generator components are going to
206 be used.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]207
208<p>This design has two important implications. The first is that LLVM can
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]209 support completely non-traditional code generation targets. For example, the
210 C backend does not require register allocation, instruction selection, or any
211 of the other standard components provided by the system. As such, it only
212 implements these two interfaces, and does its own thing. Another example of
213 a code generator like this is a (purely hypothetical) backend that converts
214 LLVM to the GCC RTL form and uses GCC to emit machine code for a target.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]215
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]216<p>This design also implies that it is possible to design and implement
217 radically different code generators in the LLVM system that do not make use
218 of any of the built-in components. Doing so is not recommended at all, but
219 could be required for radically different targets that do not fit into the
220 LLVM machine description model: FPGAs for example.</p>
Chris Lattner900bf8c2004-06-02 07:06:06 +0000[diff] [blame]221
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]222</div>
223
224<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]225<h3>
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]226 <a name="high-level-design">The high-level design of the code generator</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]227</h3>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]228
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]229<div>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]230
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]231<p>The LLVM target-independent code generator is designed to support efficient
232 and quality code generation for standard register-based microprocessors.
233 Code generation in this model is divided into the following stages:</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]234
235<ol>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]236 <li><b><a href="#instselect">Instruction Selection</a></b> &mdash; This phase
237 determines an efficient way to express the input LLVM code in the target
238 instruction set. This stage produces the initial code for the program in
239 the target instruction set, then makes use of virtual registers in SSA
240 form and physical registers that represent any required register
241 assignments due to target constraints or calling conventions. This step
242 turns the LLVM code into a DAG of target instructions.</li>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]243
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]244 <li><b><a href="#selectiondag_sched">Scheduling and Formation</a></b> &mdash;
245 This phase takes the DAG of target instructions produced by the
246 instruction selection phase, determines an ordering of the instructions,
247 then emits the instructions
248 as <tt><a href="#machineinstr">MachineInstr</a></tt>s with that ordering.
249 Note that we describe this in the <a href="#instselect">instruction
250 selection section</a> because it operates on
251 a <a href="#selectiondag_intro">SelectionDAG</a>.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]252
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]253 <li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> &mdash;
254 This optional stage consists of a series of machine-code optimizations
255 that operate on the SSA-form produced by the instruction selector.
256 Optimizations like modulo-scheduling or peephole optimization work
257 here.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]258
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]259 <li><b><a href="#regalloc">Register Allocation</a></b> &mdash; The target code
260 is transformed from an infinite virtual register file in SSA form to the
261 concrete register file used by the target. This phase introduces spill
262 code and eliminates all virtual register references from the program.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]263
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]264 <li><b><a href="#proepicode">Prolog/Epilog Code Insertion</a></b> &mdash; Once
265 the machine code has been generated for the function and the amount of
266 stack space required is known (used for LLVM alloca's and spill slots),
267 the prolog and epilog code for the function can be inserted and "abstract
268 stack location references" can be eliminated. This stage is responsible
269 for implementing optimizations like frame-pointer elimination and stack
270 packing.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]271
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]272 <li><b><a href="#latemco">Late Machine Code Optimizations</a></b> &mdash;
273 Optimizations that operate on "final" machine code can go here, such as
274 spill code scheduling and peephole optimizations.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]275
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]276 <li><b><a href="#codeemit">Code Emission</a></b> &mdash; The final stage
277 actually puts out the code for the current function, either in the target
278 assembler format or in machine code.</li>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]279</ol>
280
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]281<p>The code generator is based on the assumption that the instruction selector
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]282 will use an optimal pattern matching selector to create high-quality
283 sequences of native instructions. Alternative code generator designs based
284 on pattern expansion and aggressive iterative peephole optimization are much
285 slower. This design permits efficient compilation (important for JIT
286 environments) and aggressive optimization (used when generating code offline)
287 by allowing components of varying levels of sophistication to be used for any
288 step of compilation.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]289
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]290<p>In addition to these stages, target implementations can insert arbitrary
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]291 target-specific passes into the flow. For example, the X86 target uses a
292 special pass to handle the 80x87 floating point stack architecture. Other
293 targets with unusual requirements can be supported with custom passes as
294 needed.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]295
296</div>
297
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]298<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]299<h3>
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]300 <a name="tablegen">Using TableGen for target description</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]301</h3>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]302
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]303<div>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]304
Chris Lattner5489e932004-06-01 18:35:00 +0000[diff] [blame]305<p>The target description classes require a detailed description of the target
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]306 architecture. These target descriptions often have a large amount of common
307 information (e.g., an <tt>add</tt> instruction is almost identical to a
308 <tt>sub</tt> instruction). In order to allow the maximum amount of
309 commonality to be factored out, the LLVM code generator uses
310 the <a href="TableGenFundamentals.html">TableGen</a> tool to describe big
311 chunks of the target machine, which allows the use of domain-specific and
312 target-specific abstractions to reduce the amount of repetition.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]313
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]314<p>As LLVM continues to be developed and refined, we plan to move more and more
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]315 of the target description to the <tt>.td</tt> form. Doing so gives us a
316 number of advantages. The most important is that it makes it easier to port
317 LLVM because it reduces the amount of C++ code that has to be written, and
318 the surface area of the code generator that needs to be understood before
319 someone can get something working. Second, it makes it easier to change
320 things. In particular, if tables and other things are all emitted
321 by <tt>tblgen</tt>, we only need a change in one place (<tt>tblgen</tt>) to
322 update all of the targets to a new interface.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]323
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]324</div>
325
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]326</div>
327
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]328<!-- *********************************************************************** -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]329<h2>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]330 <a name="targetdesc">Target description classes</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]331</h2>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]332<!-- *********************************************************************** -->
333
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]334<div>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]335
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]336<p>The LLVM target description classes (located in the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]337 <tt>include/llvm/Target</tt> directory) provide an abstract description of
338 the target machine independent of any particular client. These classes are
339 designed to capture the <i>abstract</i> properties of the target (such as the
340 instructions and registers it has), and do not incorporate any particular
341 pieces of code generation algorithms.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]342
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]343<p>All of the target description classes (except the
344 <tt><a href="#targetdata">TargetData</a></tt> class) are designed to be
345 subclassed by the concrete target implementation, and have virtual methods
346 implemented. To get to these implementations, the
347 <tt><a href="#targetmachine">TargetMachine</a></tt> class provides accessors
348 that should be implemented by the target.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]349
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]350<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]351<h3>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]352 <a name="targetmachine">The <tt>TargetMachine</tt> class</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]353</h3>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]354
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]355<div>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]356
357<p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]358 access the target-specific implementations of the various target description
359 classes via the <tt>get*Info</tt> methods (<tt>getInstrInfo</tt>,
360 <tt>getRegisterInfo</tt>, <tt>getFrameInfo</tt>, etc.). This class is
361 designed to be specialized by a concrete target implementation
362 (e.g., <tt>X86TargetMachine</tt>) which implements the various virtual
363 methods. The only required target description class is
364 the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the code
365 generator components are to be used, the other interfaces should be
366 implemented as well.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]367
368</div>
369
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]370<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]371<h3>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]372 <a name="targetdata">The <tt>TargetData</tt> class</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]373</h3>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]374
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]375<div>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]376
377<p>The <tt>TargetData</tt> class is the only required target description class,
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]378 and it is the only class that is not extensible (you cannot derived a new
379 class from it). <tt>TargetData</tt> specifies information about how the
380 target lays out memory for structures, the alignment requirements for various
381 data types, the size of pointers in the target, and whether the target is
382 little-endian or big-endian.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]383
384</div>
385
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]386<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]387<h3>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]388 <a name="targetlowering">The <tt>TargetLowering</tt> class</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]389</h3>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]390
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]391<div>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]392
393<p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]394 selectors primarily to describe how LLVM code should be lowered to
395 SelectionDAG operations. Among other things, this class indicates:</p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]396
397<ul>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]398 <li>an initial register class to use for various <tt>ValueType</tt>s,</li>
399
400 <li>which operations are natively supported by the target machine,</li>
401
402 <li>the return type of <tt>setcc</tt> operations,</li>
403
404 <li>the type to use for shift amounts, and</li>
405
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]406 <li>various high-level characteristics, like whether it is profitable to turn
407 division by a constant into a multiplication sequence</li>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]408</ul>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]409
410</div>
411
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]412<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]413<h3>
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]414 <a name="targetregisterinfo">The <tt>TargetRegisterInfo</tt> class</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]415</h3>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]416
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]417<div>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]418
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]419<p>The <tt>TargetRegisterInfo</tt> class is used to describe the register file
420 of the target and any interactions between the registers.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]421
422<p>Registers in the code generator are represented in the code generator by
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]423 unsigned integers. Physical registers (those that actually exist in the
424 target description) are unique small numbers, and virtual registers are
425 generally large. Note that register #0 is reserved as a flag value.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]426
427<p>Each register in the processor description has an associated
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]428 <tt>TargetRegisterDesc</tt> entry, which provides a textual name for the
429 register (used for assembly output and debugging dumps) and a set of aliases
430 (used to indicate whether one register overlaps with another).</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]431
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]432<p>In addition to the per-register description, the <tt>TargetRegisterInfo</tt>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]433 class exposes a set of processor specific register classes (instances of the
434 <tt>TargetRegisterClass</tt> class). Each register class contains sets of
435 registers that have the same properties (for example, they are all 32-bit
436 integer registers). Each SSA virtual register created by the instruction
437 selector has an associated register class. When the register allocator runs,
438 it replaces virtual registers with a physical register in the set.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]439
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]440<p>The target-specific implementations of these classes is auto-generated from
441 a <a href="TableGenFundamentals.html">TableGen</a> description of the
442 register file.</p>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]443
444</div>
445
446<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]447<h3>
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]448 <a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]449</h3>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]450
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]451<div>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]452
453<p>The <tt>TargetInstrInfo</tt> class is used to describe the machine
454 instructions supported by the target. It is essentially an array of
455 <tt>TargetInstrDescriptor</tt> objects, each of which describes one
456 instruction the target supports. Descriptors define things like the mnemonic
457 for the opcode, the number of operands, the list of implicit register uses
458 and defs, whether the instruction has certain target-independent properties
459 (accesses memory, is commutable, etc), and holds any target-specific
460 flags.</p>
461
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]462</div>
463
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]464<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]465<h3>
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]466 <a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]467</h3>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]468
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]469<div>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]470
471<p>The <tt>TargetFrameInfo</tt> class is used to provide information about the
472 stack frame layout of the target. It holds the direction of stack growth, the
473 known stack alignment on entry to each function, and the offset to the local
474 area. The offset to the local area is the offset from the stack pointer on
475 function entry to the first location where function data (local variables,
476 spill locations) can be stored.</p>
477
Reid Spencer627cd002005-07-19 01:36:35 +0000[diff] [blame]478</div>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]479
480<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]481<h3>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]482 <a name="targetsubtarget">The <tt>TargetSubtarget</tt> class</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]483</h3>
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]484
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]485<div>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]486
487<p>The <tt>TargetSubtarget</tt> class is used to provide information about the
488 specific chip set being targeted. A sub-target informs code generation of
489 which instructions are supported, instruction latencies and instruction
490 execution itinerary; i.e., which processing units are used, in what order,
491 and for how long.</p>
492
Chris Lattner47adebb2005-10-16 17:06:07 +0000[diff] [blame]493</div>
494
495
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]496<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]497<h3>
Chris Lattner10d68002004-06-01 17:18:11 +0000[diff] [blame]498 <a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]499</h3>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]500
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]501<div>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]502
503<p>The <tt>TargetJITInfo</tt> class exposes an abstract interface used by the
504 Just-In-Time code generator to perform target-specific activities, such as
505 emitting stubs. If a <tt>TargetMachine</tt> supports JIT code generation, it
506 should provide one of these objects through the <tt>getJITInfo</tt>
507 method.</p>
508
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]509</div>
510
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]511</div>
512
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]513<!-- *********************************************************************** -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]514<h2>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]515 <a name="codegendesc">Machine code description classes</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]516</h2>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]517<!-- *********************************************************************** -->
518
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]519<div>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]520
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]521<p>At the high-level, LLVM code is translated to a machine specific
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]522 representation formed out of
523 <a href="#machinefunction"><tt>MachineFunction</tt></a>,
524 <a href="#machinebasicblock"><tt>MachineBasicBlock</tt></a>,
525 and <a href="#machineinstr"><tt>MachineInstr</tt></a> instances (defined
526 in <tt>include/llvm/CodeGen</tt>). This representation is completely target
527 agnostic, representing instructions in their most abstract form: an opcode
528 and a series of operands. This representation is designed to support both an
529 SSA representation for machine code, as well as a register allocated, non-SSA
530 form.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]531
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]532<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]533<h3>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]534 <a name="machineinstr">The <tt>MachineInstr</tt> class</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]535</h3>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]536
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]537<div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]538
539<p>Target machine instructions are represented as instances of the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]540 <tt>MachineInstr</tt> class. This class is an extremely abstract way of
541 representing machine instructions. In particular, it only keeps track of an
542 opcode number and a set of operands.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]543
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]544<p>The opcode number is a simple unsigned integer that only has meaning to a
545 specific backend. All of the instructions for a target should be defined in
546 the <tt>*InstrInfo.td</tt> file for the target. The opcode enum values are
547 auto-generated from this description. The <tt>MachineInstr</tt> class does
548 not have any information about how to interpret the instruction (i.e., what
549 the semantics of the instruction are); for that you must refer to the
550 <tt><a href="#targetinstrinfo">TargetInstrInfo</a></tt> class.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]551
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]552<p>The operands of a machine instruction can be of several different types: a
553 register reference, a constant integer, a basic block reference, etc. In
554 addition, a machine operand should be marked as a def or a use of the value
555 (though only registers are allowed to be defs).</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]556
557<p>By convention, the LLVM code generator orders instruction operands so that
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]558 all register definitions come before the register uses, even on architectures
559 that are normally printed in other orders. For example, the SPARC add
560 instruction: "<tt>add %i1, %i2, %i3</tt>" adds the "%i1", and "%i2" registers
561 and stores the result into the "%i3" register. In the LLVM code generator,
562 the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the
563 destination first.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]564
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]565<p>Keeping destination (definition) operands at the beginning of the operand
566 list has several advantages. In particular, the debugging printer will print
567 the instruction like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]568
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]569<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]570<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]571%r3 = add %i1, %i2
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]572</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]573</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]574
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]575<p>Also if the first operand is a def, it is easier to <a href="#buildmi">create
576 instructions</a> whose only def is the first operand.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]577
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]578<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]579<h4>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]580 <a name="buildmi">Using the <tt>MachineInstrBuilder.h</tt> functions</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]581</h4>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]582
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]583<div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]584
585<p>Machine instructions are created by using the <tt>BuildMI</tt> functions,
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]586 located in the <tt>include/llvm/CodeGen/MachineInstrBuilder.h</tt> file. The
587 <tt>BuildMI</tt> functions make it easy to build arbitrary machine
588 instructions. Usage of the <tt>BuildMI</tt> functions look like this:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]589
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]590<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]591<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]592// Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
593// instruction. The '1' specifies how many operands will be added.
594MachineInstr *MI = BuildMI(X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]595
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]596// Create the same instr, but insert it at the end of a basic block.
597MachineBasicBlock &amp;MBB = ...
598BuildMI(MBB, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]599
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]600// Create the same instr, but insert it before a specified iterator point.
601MachineBasicBlock::iterator MBBI = ...
602BuildMI(MBB, MBBI, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]603
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]604// Create a 'cmp Reg, 0' instruction, no destination reg.
605MI = BuildMI(X86::CMP32ri, 2).addReg(Reg).addImm(0);
606// Create an 'sahf' instruction which takes no operands and stores nothing.
607MI = BuildMI(X86::SAHF, 0);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]608
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]609// Create a self looping branch instruction.
610BuildMI(MBB, X86::JNE, 1).addMBB(&amp;MBB);
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]611</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]612</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]613
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]614<p>The key thing to remember with the <tt>BuildMI</tt> functions is that you
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]615 have to specify the number of operands that the machine instruction will
616 take. This allows for efficient memory allocation. You also need to specify
617 if operands default to be uses of values, not definitions. If you need to
618 add a definition operand (other than the optional destination register), you
619 must explicitly mark it as such:</p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]620
621<div class="doc_code">
622<pre>
Bill Wendling587daed2009-05-13 21:33:08 +0000[diff] [blame]623MI.addReg(Reg, RegState::Define);
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]624</pre>
625</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]626
627</div>
628
629<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]630<h4>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]631 <a name="fixedregs">Fixed (preassigned) registers</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]632</h4>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]633
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]634<div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]635
636<p>One important issue that the code generator needs to be aware of is the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]637 presence of fixed registers. In particular, there are often places in the
638 instruction stream where the register allocator <em>must</em> arrange for a
639 particular value to be in a particular register. This can occur due to
640 limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
641 with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like
642 calling conventions. In any case, the instruction selector should emit code
643 that copies a virtual register into or out of a physical register when
644 needed.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]645
646<p>For example, consider this simple LLVM example:</p>
647
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]648<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]649<pre>
Matthijs Kooijman61399af2008-06-04 15:46:35 +0000[diff] [blame]650define i32 @test(i32 %X, i32 %Y) {
651 %Z = udiv i32 %X, %Y
652 ret i32 %Z
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]653}
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]654</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]655</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]656
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]657<p>The X86 instruction selector produces this machine code for the <tt>div</tt>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]658 and <tt>ret</tt> (use "<tt>llc X.bc -march=x86 -print-machineinstrs</tt>" to
659 get this):</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]660
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]661<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]662<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]663;; Start of div
664%EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
665%reg1027 = sar %reg1024, 31
666%EDX = mov %reg1027 ;; Sign extend X into EDX
667idiv %reg1025 ;; Divide by Y (in reg1025)
668%reg1026 = mov %EAX ;; Read the result (Z) out of EAX
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]669
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]670;; Start of ret
671%EAX = mov %reg1026 ;; 32-bit return value goes in EAX
672ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]673</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]674</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]675
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]676<p>By the end of code generation, the register allocator has coalesced the
677 registers and deleted the resultant identity moves producing the following
678 code:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]679
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]680<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]681<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]682;; X is in EAX, Y is in ECX
683mov %EAX, %EDX
684sar %EDX, 31
685idiv %ECX
686ret
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]687</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]688</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]689
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]690<p>This approach is extremely general (if it can handle the X86 architecture, it
691 can handle anything!) and allows all of the target specific knowledge about
692 the instruction stream to be isolated in the instruction selector. Note that
693 physical registers should have a short lifetime for good code generation, and
694 all physical registers are assumed dead on entry to and exit from basic
695 blocks (before register allocation). Thus, if you need a value to be live
696 across basic block boundaries, it <em>must</em> live in a virtual
697 register.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]698
699</div>
700
701<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]702<h4>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]703 <a name="ssa">Machine code in SSA form</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]704</h4>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]705
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]706<div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]707
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]708<p><tt>MachineInstr</tt>'s are initially selected in SSA-form, and are
709 maintained in SSA-form until register allocation happens. For the most part,
710 this is trivially simple since LLVM is already in SSA form; LLVM PHI nodes
711 become machine code PHI nodes, and virtual registers are only allowed to have
712 a single definition.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]713
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]714<p>After register allocation, machine code is no longer in SSA-form because
715 there are no virtual registers left in the code.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]716
717</div>
718
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]719</div>
720
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]721<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]722<h3>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]723 <a name="machinebasicblock">The <tt>MachineBasicBlock</tt> class</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]724</h3>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]725
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]726<div>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]727
728<p>The <tt>MachineBasicBlock</tt> class contains a list of machine instructions
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]729 (<tt><a href="#machineinstr">MachineInstr</a></tt> instances). It roughly
730 corresponds to the LLVM code input to the instruction selector, but there can
731 be a one-to-many mapping (i.e. one LLVM basic block can map to multiple
732 machine basic blocks). The <tt>MachineBasicBlock</tt> class has a
733 "<tt>getBasicBlock</tt>" method, which returns the LLVM basic block that it
734 comes from.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]735
736</div>
737
738<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]739<h3>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]740 <a name="machinefunction">The <tt>MachineFunction</tt> class</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]741</h3>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]742
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]743<div>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]744
745<p>The <tt>MachineFunction</tt> class contains a list of machine basic blocks
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]746 (<tt><a href="#machinebasicblock">MachineBasicBlock</a></tt> instances). It
747 corresponds one-to-one with the LLVM function input to the instruction
748 selector. In addition to a list of basic blocks,
749 the <tt>MachineFunction</tt> contains a a <tt>MachineConstantPool</tt>,
750 a <tt>MachineFrameInfo</tt>, a <tt>MachineFunctionInfo</tt>, and a
751 <tt>MachineRegisterInfo</tt>. See
752 <tt>include/llvm/CodeGen/MachineFunction.h</tt> for more information.</p>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]753
754</div>
755
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]756</div>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]757
758<!-- *********************************************************************** -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]759<h2>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]760 <a name="mc">The "MC" Layer</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]761</h2>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]762<!-- *********************************************************************** -->
763
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]764<div>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]765
766<p>
767The MC Layer is used to represent and process code at the raw machine code
768level, devoid of "high level" information like "constant pools", "jump tables",
769"global variables" or anything like that. At this level, LLVM handles things
770like label names, machine instructions, and sections in the object file. The
771code in this layer is used for a number of important purposes: the tail end of
772the code generator uses it to write a .s or .o file, and it is also used by the
Jay Foadd61895a2011-04-13 13:03:56 +0000[diff] [blame]773llvm-mc tool to implement standalone machine code assemblers and disassemblers.
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]774</p>
775
776<p>
777This section describes some of the important classes. There are also a number
778of important subsystems that interact at this layer, they are described later
779in this manual.
780</p>
781
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]782<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]783<h3>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]784 <a name="mcstreamer">The <tt>MCStreamer</tt> API</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]785</h3>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]786
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]787<div>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]788
789<p>
790MCStreamer is best thought of as an assembler API. It is an abstract API which
791is <em>implemented</em> in different ways (e.g. to output a .s file, output an
792ELF .o file, etc) but whose API correspond directly to what you see in a .s
793file. MCStreamer has one method per directive, such as EmitLabel,
794EmitSymbolAttribute, SwitchSection, EmitValue (for .byte, .word), etc, which
795directly correspond to assembly level directives. It also has an
796EmitInstruction method, which is used to output an MCInst to the streamer.
797</p>
798
799<p>
800This API is most important for two clients: the llvm-mc stand-alone assembler is
801effectively a parser that parses a line, then invokes a method on MCStreamer. In
802the code generator, the <a href="#codeemit">Code Emission</a> phase of the code
803generator lowers higher level LLVM IR and Machine* constructs down to the MC
804layer, emitting directives through MCStreamer.</p>
805
806<p>
807On the implementation side of MCStreamer, there are two major implementations:
808one for writing out a .s file (MCAsmStreamer), and one for writing out a .o
809file (MCObjectStreamer). MCAsmStreamer is a straight-forward implementation
810that prints out a directive for each method (e.g. EmitValue -&gt; .byte), but
811MCObjectStreamer implements a full assembler.
812</p>
813
814</div>
815
816<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]817<h3>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]818 <a name="mccontext">The <tt>MCContext</tt> class</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]819</h3>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]820
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]821<div>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]822
823<p>
824The MCContext class is the owner of a variety of uniqued data structures at the
825MC layer, including symbols, sections, etc. As such, this is the class that you
826interact with to create symbols and sections. This class can not be subclassed.
827</p>
828
829</div>
830
831<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]832<h3>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]833 <a name="mcsymbol">The <tt>MCSymbol</tt> class</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]834</h3>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]835
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]836<div>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]837
838<p>
839The MCSymbol class represents a symbol (aka label) in the assembly file. There
840are two interesting kinds of symbols: assembler temporary symbols, and normal
841symbols. Assembler temporary symbols are used and processed by the assembler
842but are discarded when the object file is produced. The distinction is usually
843represented by adding a prefix to the label, for example "L" labels are
844assembler temporary labels in MachO.
845</p>
846
847<p>MCSymbols are created by MCContext and uniqued there. This means that
848MCSymbols can be compared for pointer equivalence to find out if they are the
849same symbol. Note that pointer inequality does not guarantee the labels will
850end up at different addresses though. It's perfectly legal to output something
851like this to the .s file:<p>
852
853<pre>
854 foo:
855 bar:
856 .byte 4
857</pre>
858
859<p>In this case, both the foo and bar symbols will have the same address.</p>
860
861</div>
862
863<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]864<h3>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]865 <a name="mcsection">The <tt>MCSection</tt> class</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]866</h3>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]867
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]868<div>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]869
870<p>
871The MCSection class represents an object-file specific section. It is subclassed
872by object file specific implementations (e.g. <tt>MCSectionMachO</tt>,
873<tt>MCSectionCOFF</tt>, <tt>MCSectionELF</tt>) and these are created and uniqued
874by MCContext. The MCStreamer has a notion of the current section, which can be
875changed with the SwitchToSection method (which corresponds to a ".section"
876directive in a .s file).
877</p>
878
879</div>
880
881<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]882<h3>
Benjamin Kramer943beeb2010-10-30 21:07:28 +0000[diff] [blame]883 <a name="mcinst">The <tt>MCInst</tt> class</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]884</h3>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]885
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]886<div>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]887
888<p>
889The MCInst class is a target-independent representation of an instruction. It
890is a simple class (much more so than <a href="#machineinstr">MachineInstr</a>)
891that holds a target-specific opcode and a vector of MCOperands. MCOperand, in
892turn, is a simple discriminated union of three cases: 1) a simple immediate,
8932) a target register ID, 3) a symbolic expression (e.g. "Lfoo-Lbar+42") as an
894MCExpr.
895</p>
896
897<p>MCInst is the common currency used to represent machine instructions at the
898MC layer. It is the type used by the instruction encoder, the instruction
899printer, and the type generated by the assembly parser and disassembler.
900</p>
901
902</div>
903
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]904</div>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]905
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]906<!-- *********************************************************************** -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]907<h2>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]908 <a name="codegenalgs">Target-independent code generation algorithms</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]909</h2>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]910<!-- *********************************************************************** -->
911
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]912<div>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]913
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]914<p>This section documents the phases described in the
915 <a href="#high-level-design">high-level design of the code generator</a>.
916 It explains how they work and some of the rationale behind their design.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]917
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]918<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]919<h3>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]920 <a name="instselect">Instruction Selection</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]921</h3>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]922
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]923<div>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]924
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]925<p>Instruction Selection is the process of translating LLVM code presented to
926 the code generator into target-specific machine instructions. There are
927 several well-known ways to do this in the literature. LLVM uses a
928 SelectionDAG based instruction selector.</p>
929
930<p>Portions of the DAG instruction selector are generated from the target
931 description (<tt>*.td</tt>) files. Our goal is for the entire instruction
932 selector to be generated from these <tt>.td</tt> files, though currently
933 there are still things that require custom C++ code.</p>
934
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]935<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]936<h4>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]937 <a name="selectiondag_intro">Introduction to SelectionDAGs</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]938</h4>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]939
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]940<div>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]941
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]942<p>The SelectionDAG provides an abstraction for code representation in a way
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]943 that is amenable to instruction selection using automatic techniques
944 (e.g. dynamic-programming based optimal pattern matching selectors). It is
945 also well-suited to other phases of code generation; in particular,
946 instruction scheduling (SelectionDAG's are very close to scheduling DAGs
947 post-selection). Additionally, the SelectionDAG provides a host
948 representation where a large variety of very-low-level (but
949 target-independent) <a href="#selectiondag_optimize">optimizations</a> may be
950 performed; ones which require extensive information about the instructions
951 efficiently supported by the target.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]952
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]953<p>The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]954 <tt>SDNode</tt> class. The primary payload of the <tt>SDNode</tt> is its
955 operation code (Opcode) that indicates what operation the node performs and
956 the operands to the operation. The various operation node types are
957 described at the top of the <tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt>
958 file.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]959
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]960<p>Although most operations define a single value, each node in the graph may
961 define multiple values. For example, a combined div/rem operation will
962 define both the dividend and the remainder. Many other situations require
963 multiple values as well. Each node also has some number of operands, which
964 are edges to the node defining the used value. Because nodes may define
965 multiple values, edges are represented by instances of the <tt>SDValue</tt>
966 class, which is a <tt>&lt;SDNode, unsigned&gt;</tt> pair, indicating the node
967 and result value being used, respectively. Each value produced by
968 an <tt>SDNode</tt> has an associated <tt>MVT</tt> (Machine Value Type)
969 indicating what the type of the value is.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]970
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]971<p>SelectionDAGs contain two different kinds of values: those that represent
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]972 data flow and those that represent control flow dependencies. Data values
973 are simple edges with an integer or floating point value type. Control edges
974 are represented as "chain" edges which are of type <tt>MVT::Other</tt>.
975 These edges provide an ordering between nodes that have side effects (such as
976 loads, stores, calls, returns, etc). All nodes that have side effects should
977 take a token chain as input and produce a new one as output. By convention,
978 token chain inputs are always operand #0, and chain results are always the
979 last value produced by an operation.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]980
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]981<p>A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]982 always a marker node with an Opcode of <tt>ISD::EntryToken</tt>. The Root
983 node is the final side-effecting node in the token chain. For example, in a
984 single basic block function it would be the return node.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]985
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]986<p>One important concept for SelectionDAGs is the notion of a "legal" vs.
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]987 "illegal" DAG. A legal DAG for a target is one that only uses supported
988 operations and supported types. On a 32-bit PowerPC, for example, a DAG with
989 a value of type i1, i8, i16, or i64 would be illegal, as would a DAG that
990 uses a SREM or UREM operation. The
991 <a href="#selectinodag_legalize_types">legalize types</a> and
992 <a href="#selectiondag_legalize">legalize operations</a> phases are
993 responsible for turning an illegal DAG into a legal DAG.</p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]994
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]995</div>
996
997<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]998<h4>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]999 <a name="selectiondag_process">SelectionDAG Instruction Selection Process</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1000</h4>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1001
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1002<div>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1003
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1004<p>SelectionDAG-based instruction selection consists of the following steps:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1005
1006<ol>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1007 <li><a href="#selectiondag_build">Build initial DAG</a> &mdash; This stage
1008 performs a simple translation from the input LLVM code to an illegal
1009 SelectionDAG.</li>
1010
1011 <li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> &mdash; This
1012 stage performs simple optimizations on the SelectionDAG to simplify it,
1013 and recognize meta instructions (like rotates
1014 and <tt>div</tt>/<tt>rem</tt> pairs) for targets that support these meta
1015 operations. This makes the resultant code more efficient and
1016 the <a href="#selectiondag_select">select instructions from DAG</a> phase
1017 (below) simpler.</li>
1018
1019 <li><a href="#selectiondag_legalize_types">Legalize SelectionDAG Types</a>
1020 &mdash; This stage transforms SelectionDAG nodes to eliminate any types
1021 that are unsupported on the target.</li>
1022
1023 <li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> &mdash; The
1024 SelectionDAG optimizer is run to clean up redundancies exposed by type
1025 legalization.</li>
1026
Chris Lattner71388632010-12-12 02:42:57 +0000[diff] [blame]1027 <li><a href="#selectiondag_legalize">Legalize SelectionDAG Ops</a> &mdash;
Chris Lattner4c247f62010-12-13 00:17:12 +0000[diff] [blame]1028 This stage transforms SelectionDAG nodes to eliminate any operations
1029 that are unsupported on the target.</li>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1030
1031 <li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> &mdash; The
1032 SelectionDAG optimizer is run to eliminate inefficiencies introduced by
1033 operation legalization.</li>
1034
1035 <li><a href="#selectiondag_select">Select instructions from DAG</a> &mdash;
1036 Finally, the target instruction selector matches the DAG operations to
1037 target instructions. This process translates the target-independent input
1038 DAG into another DAG of target instructions.</li>
1039
1040 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation</a>
1041 &mdash; The last phase assigns a linear order to the instructions in the
1042 target-instruction DAG and emits them into the MachineFunction being
1043 compiled. This step uses traditional prepass scheduling techniques.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1044</ol>
1045
1046<p>After all of these steps are complete, the SelectionDAG is destroyed and the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1047 rest of the code generation passes are run.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1048
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1049<p>One great way to visualize what is going on here is to take advantage of a
1050 few LLC command line options. The following options pop up a window
1051 displaying the SelectionDAG at specific times (if you only get errors printed
1052 to the console while using this, you probably
1053 <a href="ProgrammersManual.html#ViewGraph">need to configure your system</a>
1054 to add support for it).</p>
Dan Gohman8c9c55f2008-09-10 22:23:41 +0000[diff] [blame]1055
1056<ul>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1057 <li><tt>-view-dag-combine1-dags</tt> displays the DAG after being built,
1058 before the first optimization pass.</li>
1059
1060 <li><tt>-view-legalize-dags</tt> displays the DAG before Legalization.</li>
1061
1062 <li><tt>-view-dag-combine2-dags</tt> displays the DAG before the second
1063 optimization pass.</li>
1064
1065 <li><tt>-view-isel-dags</tt> displays the DAG before the Select phase.</li>
1066
1067 <li><tt>-view-sched-dags</tt> displays the DAG before Scheduling.</li>
Dan Gohman8c9c55f2008-09-10 22:23:41 +0000[diff] [blame]1068</ul>
1069
1070<p>The <tt>-view-sunit-dags</tt> displays the Scheduler's dependency graph.
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1071 This graph is based on the final SelectionDAG, with nodes that must be
1072 scheduled together bundled into a single scheduling-unit node, and with
1073 immediate operands and other nodes that aren't relevant for scheduling
1074 omitted.</p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1075
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1076</div>
1077
1078<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1079<h4>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1080 <a name="selectiondag_build">Initial SelectionDAG Construction</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1081</h4>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1082
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1083<div>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1084
Bill Wendling16448772006-08-28 03:04:05 +0000[diff] [blame]1085<p>The initial SelectionDAG is na&iuml;vely peephole expanded from the LLVM
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1086 input by the <tt>SelectionDAGLowering</tt> class in the
1087 <tt>lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp</tt> file. The intent of
1088 this pass is to expose as much low-level, target-specific details to the
1089 SelectionDAG as possible. This pass is mostly hard-coded (e.g. an
1090 LLVM <tt>add</tt> turns into an <tt>SDNode add</tt> while a
1091 <tt>getelementptr</tt> is expanded into the obvious arithmetic). This pass
1092 requires target-specific hooks to lower calls, returns, varargs, etc. For
1093 these features, the <tt><a href="#targetlowering">TargetLowering</a></tt>
1094 interface is used.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1095
1096</div>
1097
1098<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1099<h4>
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1100 <a name="selectiondag_legalize_types">SelectionDAG LegalizeTypes Phase</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1101</h4>
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1102
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1103<div>
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1104
1105<p>The Legalize phase is in charge of converting a DAG to only use the types
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1106 that are natively supported by the target.</p>
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1107
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1108<p>There are two main ways of converting values of unsupported scalar types to
1109 values of supported types: converting small types to larger types
1110 ("promoting"), and breaking up large integer types into smaller ones
1111 ("expanding"). For example, a target might require that all f32 values are
1112 promoted to f64 and that all i1/i8/i16 values are promoted to i32. The same
1113 target might require that all i64 values be expanded into pairs of i32
1114 values. These changes can insert sign and zero extensions as needed to make
1115 sure that the final code has the same behavior as the input.</p>
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1116
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1117<p>There are two main ways of converting values of unsupported vector types to
1118 value of supported types: splitting vector types, multiple times if
1119 necessary, until a legal type is found, and extending vector types by adding
1120 elements to the end to round them out to legal types ("widening"). If a
1121 vector gets split all the way down to single-element parts with no supported
1122 vector type being found, the elements are converted to scalars
1123 ("scalarizing").</p>
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1124
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1125<p>A target implementation tells the legalizer which types are supported (and
1126 which register class to use for them) by calling the
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1127 <tt>addRegisterClass</tt> method in its TargetLowering constructor.</p>
1128
1129</div>
1130
1131<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1132<h4>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1133 <a name="selectiondag_legalize">SelectionDAG Legalize Phase</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1134</h4>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1135
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1136<div>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1137
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1138<p>The Legalize phase is in charge of converting a DAG to only use the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1139 operations that are natively supported by the target.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1140
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1141<p>Targets often have weird constraints, such as not supporting every operation
1142 on every supported datatype (e.g. X86 does not support byte conditional moves
1143 and PowerPC does not support sign-extending loads from a 16-bit memory
1144 location). Legalize takes care of this by open-coding another sequence of
1145 operations to emulate the operation ("expansion"), by promoting one type to a
1146 larger type that supports the operation ("promotion"), or by using a
1147 target-specific hook to implement the legalization ("custom").</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1148
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1149<p>A target implementation tells the legalizer which operations are not
1150 supported (and which of the above three actions to take) by calling the
1151 <tt>setOperationAction</tt> method in its <tt>TargetLowering</tt>
1152 constructor.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1153
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]1154<p>Prior to the existence of the Legalize passes, we required that every target
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1155 <a href="#selectiondag_optimize">selector</a> supported and handled every
1156 operator and type even if they are not natively supported. The introduction
1157 of the Legalize phases allows all of the canonicalization patterns to be
1158 shared across targets, and makes it very easy to optimize the canonicalized
1159 code because it is still in the form of a DAG.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1160
1161</div>
1162
1163<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1164<h4>
1165 <a name="selectiondag_optimize">
1166 SelectionDAG Optimization Phase: the DAG Combiner
1167 </a>
1168</h4>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1169
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1170<div>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1171
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1172<p>The SelectionDAG optimization phase is run multiple times for code
1173 generation, immediately after the DAG is built and once after each
1174 legalization. The first run of the pass allows the initial code to be
1175 cleaned up (e.g. performing optimizations that depend on knowing that the
1176 operators have restricted type inputs). Subsequent runs of the pass clean up
1177 the messy code generated by the Legalize passes, which allows Legalize to be
1178 very simple (it can focus on making code legal instead of focusing on
1179 generating <em>good</em> and legal code).</p>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1180
1181<p>One important class of optimizations performed is optimizing inserted sign
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1182 and zero extension instructions. We currently use ad-hoc techniques, but
1183 could move to more rigorous techniques in the future. Here are some good
1184 papers on the subject:</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1185
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1186<p>"<a href="http://www.eecs.harvard.edu/~nr/pubs/widen-abstract.html">Widening
1187 integer arithmetic</a>"<br>
1188 Kevin Redwine and Norman Ramsey<br>
1189 International Conference on Compiler Construction (CC) 2004</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1190
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1191<p>"<a href="http://portal.acm.org/citation.cfm?doid=512529.512552">Effective
1192 sign extension elimination</a>"<br>
1193 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
1194 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
1195 and Implementation.</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1196
1197</div>
1198
1199<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1200<h4>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1201 <a name="selectiondag_select">SelectionDAG Select Phase</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1202</h4>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1203
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1204<div>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1205
1206<p>The Select phase is the bulk of the target-specific code for instruction
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1207 selection. This phase takes a legal SelectionDAG as input, pattern matches
1208 the instructions supported by the target to this DAG, and produces a new DAG
1209 of target code. For example, consider the following LLVM fragment:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1210
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1211<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1212<pre>
Dan Gohmana9445e12010-03-02 01:11:08 +0000[diff] [blame]1213%t1 = fadd float %W, %X
1214%t2 = fmul float %t1, %Y
1215%t3 = fadd float %t2, %Z
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1216</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1217</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1218
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1219<p>This LLVM code corresponds to a SelectionDAG that looks basically like
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1220 this:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1221
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1222<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1223<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1224(fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1225</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1226</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1227
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1228<p>If a target supports floating point multiply-and-add (FMA) operations, one of
1229 the adds can be merged with the multiply. On the PowerPC, for example, the
1230 output of the instruction selector might look like this DAG:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1231
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1232<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1233<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1234(FMADDS (FADDS W, X), Y, Z)
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1235</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1236</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1237
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1238<p>The <tt>FMADDS</tt> instruction is a ternary instruction that multiplies its
1239first two operands and adds the third (as single-precision floating-point
1240numbers). The <tt>FADDS</tt> instruction is a simple binary single-precision
1241add instruction. To perform this pattern match, the PowerPC backend includes
1242the following instruction definitions:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1243
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1244<div class="doc_code">
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1245<pre>
1246def FMADDS : AForm_1&lt;59, 29,
1247 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1248 "fmadds $FRT, $FRA, $FRC, $FRB",
1249 [<b>(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1250 F4RC:$FRB))</b>]&gt;;
1251def FADDS : AForm_2&lt;59, 21,
1252 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1253 "fadds $FRT, $FRA, $FRB",
1254 [<b>(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))</b>]&gt;;
1255</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1256</div>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1257
1258<p>The portion of the instruction definition in bold indicates the pattern used
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1259 to match the instruction. The DAG operators
1260 (like <tt>fmul</tt>/<tt>fadd</tt>) are defined in
Dan Gohman6a4824c2010-03-25 00:03:04 +0000[diff] [blame]1261 the <tt>include/llvm/Target/TargetSelectionDAG.td</tt> file. "
1262 <tt>F4RC</tt>" is the register class of the input and result values.</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1263
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1264<p>The TableGen DAG instruction selector generator reads the instruction
1265 patterns in the <tt>.td</tt> file and automatically builds parts of the
1266 pattern matching code for your target. It has the following strengths:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1267
1268<ul>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1269 <li>At compiler-compiler time, it analyzes your instruction patterns and tells
1270 you if your patterns make sense or not.</li>
1271
1272 <li>It can handle arbitrary constraints on operands for the pattern match. In
1273 particular, it is straight-forward to say things like "match any immediate
1274 that is a 13-bit sign-extended value". For examples, see the
1275 <tt>immSExt16</tt> and related <tt>tblgen</tt> classes in the PowerPC
1276 backend.</li>
1277
1278 <li>It knows several important identities for the patterns defined. For
1279 example, it knows that addition is commutative, so it allows the
1280 <tt>FMADDS</tt> pattern above to match "<tt>(fadd X, (fmul Y, Z))</tt>" as
1281 well as "<tt>(fadd (fmul X, Y), Z)</tt>", without the target author having
1282 to specially handle this case.</li>
1283
1284 <li>It has a full-featured type-inferencing system. In particular, you should
1285 rarely have to explicitly tell the system what type parts of your patterns
1286 are. In the <tt>FMADDS</tt> case above, we didn't have to tell
1287 <tt>tblgen</tt> that all of the nodes in the pattern are of type 'f32'.
1288 It was able to infer and propagate this knowledge from the fact that
1289 <tt>F4RC</tt> has type 'f32'.</li>
1290
1291 <li>Targets can define their own (and rely on built-in) "pattern fragments".
1292 Pattern fragments are chunks of reusable patterns that get inlined into
1293 your patterns during compiler-compiler time. For example, the integer
1294 "<tt>(not x)</tt>" operation is actually defined as a pattern fragment
1295 that expands as "<tt>(xor x, -1)</tt>", since the SelectionDAG does not
1296 have a native '<tt>not</tt>' operation. Targets can define their own
1297 short-hand fragments as they see fit. See the definition of
1298 '<tt>not</tt>' and '<tt>ineg</tt>' for examples.</li>
1299
1300 <li>In addition to instructions, targets can specify arbitrary patterns that
1301 map to one or more instructions using the 'Pat' class. For example, the
1302 PowerPC has no way to load an arbitrary integer immediate into a register
1303 in one instruction. To tell tblgen how to do this, it defines:
1304 <br>
1305 <br>
1306<div class="doc_code">
1307<pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1308// Arbitrary immediate support. Implement in terms of LIS/ORI.
1309def : Pat&lt;(i32 imm:$imm),
1310 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))&gt;;
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1311</pre>
1312</div>
1313 <br>
1314 If none of the single-instruction patterns for loading an immediate into a
1315 register match, this will be used. This rule says "match an arbitrary i32
1316 immediate, turning it into an <tt>ORI</tt> ('or a 16-bit immediate') and
1317 an <tt>LIS</tt> ('load 16-bit immediate, where the immediate is shifted to
1318 the left 16 bits') instruction". To make this work, the
1319 <tt>LO16</tt>/<tt>HI16</tt> node transformations are used to manipulate
1320 the input immediate (in this case, take the high or low 16-bits of the
1321 immediate).</li>
1322
1323 <li>While the system does automate a lot, it still allows you to write custom
1324 C++ code to match special cases if there is something that is hard to
1325 express.</li>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1326</ul>
1327
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]1328<p>While it has many strengths, the system currently has some limitations,
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1329 primarily because it is a work in progress and is not yet finished:</p>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1330
1331<ul>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1332 <li>Overall, there is no way to define or match SelectionDAG nodes that define
Dan Gohmane370c802009-04-22 15:55:31 +0000[diff] [blame]1333 multiple values (e.g. <tt>SMUL_LOHI</tt>, <tt>LOAD</tt>, <tt>CALL</tt>,
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1334 etc). This is the biggest reason that you currently still <em>have
1335 to</em> write custom C++ code for your instruction selector.</li>
1336
1337 <li>There is no great way to support matching complex addressing modes yet.
1338 In the future, we will extend pattern fragments to allow them to define
1339 multiple values (e.g. the four operands of the <a href="#x86_memory">X86
1340 addressing mode</a>, which are currently matched with custom C++ code).
1341 In addition, we'll extend fragments so that a fragment can match multiple
1342 different patterns.</li>
1343
1344 <li>We don't automatically infer flags like isStore/isLoad yet.</li>
1345
1346 <li>We don't automatically generate the set of supported registers and
1347 operations for the <a href="#selectiondag_legalize">Legalizer</a>
1348 yet.</li>
1349
1350 <li>We don't have a way of tying in custom legalized nodes yet.</li>
Chris Lattner7d6915c2005-10-17 04:18:41 +0000[diff] [blame]1351</ul>
Chris Lattner7a025c82005-10-16 20:02:19 +0000[diff] [blame]1352
1353<p>Despite these limitations, the instruction selector generator is still quite
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1354 useful for most of the binary and logical operations in typical instruction
1355 sets. If you run into any problems or can't figure out how to do something,
1356 please let Chris know!</p>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1357
1358</div>
1359
1360<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1361<h4>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1362 <a name="selectiondag_sched">SelectionDAG Scheduling and Formation Phase</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1363</h4>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1364
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1365<div>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1366
1367<p>The scheduling phase takes the DAG of target instructions from the selection
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1368 phase and assigns an order. The scheduler can pick an order depending on
1369 various constraints of the machines (i.e. order for minimal register pressure
1370 or try to cover instruction latencies). Once an order is established, the
1371 DAG is converted to a list
1372 of <tt><a href="#machineinstr">MachineInstr</a></tt>s and the SelectionDAG is
1373 destroyed.</p>
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1374
Jeff Cohen0b81cda2005-10-24 16:54:55 +0000[diff] [blame]1375<p>Note that this phase is logically separate from the instruction selection
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1376 phase, but is tied to it closely in the code because it operates on
1377 SelectionDAGs.</p>
Chris Lattnerc38959f2005-10-17 03:09:31 +0000[diff] [blame]1378
Chris Lattnere35d3bb2005-10-16 00:36:38 +0000[diff] [blame]1379</div>
1380
1381<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1382<h4>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1383 <a name="selectiondag_future">Future directions for the SelectionDAG</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1384</h4>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1385
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1386<div>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1387
1388<ol>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1389 <li>Optional function-at-a-time selection.</li>
1390
1391 <li>Auto-generate entire selector from <tt>.td</tt> file.</li>
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]1392</ol>
1393
1394</div>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1395
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1396</div>
1397
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1398<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1399<h3>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1400 <a name="ssamco">SSA-based Machine Code Optimizations</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1401</h3>
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1402<div><p>To Be Written</p></div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1403
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1404<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1405<h3>
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1406 <a name="liveintervals">Live Intervals</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1407</h3>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1408
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1409<div>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1410
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1411<p>Live Intervals are the ranges (intervals) where a variable is <i>live</i>.
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1412 They are used by some <a href="#regalloc">register allocator</a> passes to
1413 determine if two or more virtual registers which require the same physical
1414 register are live at the same point in the program (i.e., they conflict).
1415 When this situation occurs, one virtual register must be <i>spilled</i>.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1416
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1417<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1418<h4>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1419 <a name="livevariable_analysis">Live Variable Analysis</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1420</h4>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1421
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1422<div>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1423
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1424<p>The first step in determining the live intervals of variables is to calculate
1425 the set of registers that are immediately dead after the instruction (i.e.,
1426 the instruction calculates the value, but it is never used) and the set of
1427 registers that are used by the instruction, but are never used after the
1428 instruction (i.e., they are killed). Live variable information is computed
1429 for each <i>virtual</i> register and <i>register allocatable</i> physical
1430 register in the function. This is done in a very efficient manner because it
1431 uses SSA to sparsely compute lifetime information for virtual registers
1432 (which are in SSA form) and only has to track physical registers within a
1433 block. Before register allocation, LLVM can assume that physical registers
1434 are only live within a single basic block. This allows it to do a single,
1435 local analysis to resolve physical register lifetimes within each basic
1436 block. If a physical register is not register allocatable (e.g., a stack
1437 pointer or condition codes), it is not tracked.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1438
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1439<p>Physical registers may be live in to or out of a function. Live in values are
1440 typically arguments in registers. Live out values are typically return values
1441 in registers. Live in values are marked as such, and are given a dummy
1442 "defining" instruction during live intervals analysis. If the last basic
1443 block of a function is a <tt>return</tt>, then it's marked as using all live
1444 out values in the function.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1445
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1446<p><tt>PHI</tt> nodes need to be handled specially, because the calculation of
1447 the live variable information from a depth first traversal of the CFG of the
1448 function won't guarantee that a virtual register used by the <tt>PHI</tt>
1449 node is defined before it's used. When a <tt>PHI</tt> node is encountered,
1450 only the definition is handled, because the uses will be handled in other
1451 basic blocks.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1452
1453<p>For each <tt>PHI</tt> node of the current basic block, we simulate an
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1454 assignment at the end of the current basic block and traverse the successor
1455 basic blocks. If a successor basic block has a <tt>PHI</tt> node and one of
1456 the <tt>PHI</tt> node's operands is coming from the current basic block, then
1457 the variable is marked as <i>alive</i> within the current basic block and all
1458 of its predecessor basic blocks, until the basic block with the defining
1459 instruction is encountered.</p>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1460
1461</div>
1462
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1463<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1464<h4>
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1465 <a name="liveintervals_analysis">Live Intervals Analysis</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1466</h4>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1467
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1468<div>
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1469
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1470<p>We now have the information available to perform the live intervals analysis
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1471 and build the live intervals themselves. We start off by numbering the basic
1472 blocks and machine instructions. We then handle the "live-in" values. These
1473 are in physical registers, so the physical register is assumed to be killed
1474 by the end of the basic block. Live intervals for virtual registers are
1475 computed for some ordering of the machine instructions <tt>[1, N]</tt>. A
1476 live interval is an interval <tt>[i, j)</tt>, where <tt>1 &lt;= i &lt;= j
1477 &lt; N</tt>, for which a variable is live.</p>
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1478
Bill Wendling82e2eea2006-10-11 18:00:22 +0000[diff] [blame]1479<p><i><b>More to come...</b></i></p>
1480
Bill Wendling3fc488d2006-09-06 18:42:41 +0000[diff] [blame]1481</div>
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1482
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1483</div>
1484
Bill Wendling2f87a882006-09-04 23:35:52 +0000[diff] [blame]1485<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1486<h3>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1487 <a name="regalloc">Register Allocation</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1488</h3>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1489
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1490<div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1491
Bill Wendling3cd5ca62006-10-11 06:30:10 +0000[diff] [blame]1492<p>The <i>Register Allocation problem</i> consists in mapping a program
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1493 <i>P<sub>v</sub></i>, that can use an unbounded number of virtual registers,
1494 to a program <i>P<sub>p</sub></i> that contains a finite (possibly small)
1495 number of physical registers. Each target architecture has a different number
1496 of physical registers. If the number of physical registers is not enough to
1497 accommodate all the virtual registers, some of them will have to be mapped
1498 into memory. These virtuals are called <i>spilled virtuals</i>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1499
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1500<!-- _______________________________________________________________________ -->
1501
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1502<h4>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1503 <a name="regAlloc_represent">How registers are represented in LLVM</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1504</h4>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1505
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1506<div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1507
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1508<p>In LLVM, physical registers are denoted by integer numbers that normally
1509 range from 1 to 1023. To see how this numbering is defined for a particular
1510 architecture, you can read the <tt>GenRegisterNames.inc</tt> file for that
1511 architecture. For instance, by
1512 inspecting <tt>lib/Target/X86/X86GenRegisterNames.inc</tt> we see that the
1513 32-bit register <tt>EAX</tt> is denoted by 15, and the MMX register
1514 <tt>MM0</tt> is mapped to 48.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1515
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1516<p>Some architectures contain registers that share the same physical location. A
1517 notable example is the X86 platform. For instance, in the X86 architecture,
1518 the registers <tt>EAX</tt>, <tt>AX</tt> and <tt>AL</tt> share the first eight
1519 bits. These physical registers are marked as <i>aliased</i> in LLVM. Given a
1520 particular architecture, you can check which registers are aliased by
1521 inspecting its <tt>RegisterInfo.td</tt> file. Moreover, the method
1522 <tt>TargetRegisterInfo::getAliasSet(p_reg)</tt> returns an array containing
1523 all the physical registers aliased to the register <tt>p_reg</tt>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1524
1525<p>Physical registers, in LLVM, are grouped in <i>Register Classes</i>.
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1526 Elements in the same register class are functionally equivalent, and can be
1527 interchangeably used. Each virtual register can only be mapped to physical
1528 registers of a particular class. For instance, in the X86 architecture, some
1529 virtuals can only be allocated to 8 bit registers. A register class is
1530 described by <tt>TargetRegisterClass</tt> objects. To discover if a virtual
1531 register is compatible with a given physical, this code can be used:</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1532
1533<div class="doc_code">
1534<pre>
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]1535bool RegMapping_Fer::compatible_class(MachineFunction &amp;mf,
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1536 unsigned v_reg,
1537 unsigned p_reg) {
Dan Gohman6f0d0242008-02-10 18:45:23 +0000[diff] [blame]1538 assert(TargetRegisterInfo::isPhysicalRegister(p_reg) &amp;&amp;
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1539 "Target register must be physical");
Chris Lattner534bcfb2007-12-31 04:16:08 +0000[diff] [blame]1540 const TargetRegisterClass *trc = mf.getRegInfo().getRegClass(v_reg);
1541 return trc-&gt;contains(p_reg);
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1542}
1543</pre>
1544</div>
1545
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1546<p>Sometimes, mostly for debugging purposes, it is useful to change the number
1547 of physical registers available in the target architecture. This must be done
1548 statically, inside the <tt>TargetRegsterInfo.td</tt> file. Just <tt>grep</tt>
1549 for <tt>RegisterClass</tt>, the last parameter of which is a list of
1550 registers. Just commenting some out is one simple way to avoid them being
1551 used. A more polite way is to explicitly exclude some registers from
Dan Gohmand2cb3d22009-07-24 00:30:09 +0000[diff] [blame]1552 the <i>allocation order</i>. See the definition of the <tt>GR8</tt> register
1553 class in <tt>lib/Target/X86/X86RegisterInfo.td</tt> for an example of this.
1554 </p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1555
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1556<p>Virtual registers are also denoted by integer numbers. Contrary to physical
Jakob Stoklund Olesen3ca21022011-01-08 23:10:59 +0000[diff] [blame]1557 registers, different virtual registers never share the same number. Whereas
1558 physical registers are statically defined in a <tt>TargetRegisterInfo.td</tt>
1559 file and cannot be created by the application developer, that is not the case
1560 with virtual registers. In order to create new virtual registers, use the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1561 method <tt>MachineRegisterInfo::createVirtualRegister()</tt>. This method
Jakob Stoklund Olesen3ca21022011-01-08 23:10:59 +0000[diff] [blame]1562 will return a new virtual register. Use an <tt>IndexedMap&lt;Foo,
1563 VirtReg2IndexFunctor&gt;</tt> to hold information per virtual register. If you
1564 need to enumerate all virtual registers, use the function
1565 <tt>TargetRegisterInfo::index2VirtReg()</tt> to find the virtual register
1566 numbers:</p>
1567
1568<div class="doc_code">
1569<pre>
1570 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1571 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(i);
1572 stuff(VirtReg);
1573 }
1574</pre>
1575</div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1576
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1577<p>Before register allocation, the operands of an instruction are mostly virtual
1578 registers, although physical registers may also be used. In order to check if
1579 a given machine operand is a register, use the boolean
1580 function <tt>MachineOperand::isRegister()</tt>. To obtain the integer code of
1581 a register, use <tt>MachineOperand::getReg()</tt>. An instruction may define
1582 or use a register. For instance, <tt>ADD reg:1026 := reg:1025 reg:1024</tt>
1583 defines the registers 1024, and uses registers 1025 and 1026. Given a
1584 register operand, the method <tt>MachineOperand::isUse()</tt> informs if that
1585 register is being used by the instruction. The
1586 method <tt>MachineOperand::isDef()</tt> informs if that registers is being
1587 defined.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1588
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1589<p>We will call physical registers present in the LLVM bitcode before register
1590 allocation <i>pre-colored registers</i>. Pre-colored registers are used in
1591 many different situations, for instance, to pass parameters of functions
1592 calls, and to store results of particular instructions. There are two types
1593 of pre-colored registers: the ones <i>implicitly</i> defined, and
1594 those <i>explicitly</i> defined. Explicitly defined registers are normal
1595 operands, and can be accessed
1596 with <tt>MachineInstr::getOperand(int)::getReg()</tt>. In order to check
1597 which registers are implicitly defined by an instruction, use
1598 the <tt>TargetInstrInfo::get(opcode)::ImplicitDefs</tt>,
1599 where <tt>opcode</tt> is the opcode of the target instruction. One important
1600 difference between explicit and implicit physical registers is that the
1601 latter are defined statically for each instruction, whereas the former may
1602 vary depending on the program being compiled. For example, an instruction
1603 that represents a function call will always implicitly define or use the same
1604 set of physical registers. To read the registers implicitly used by an
1605 instruction,
1606 use <tt>TargetInstrInfo::get(opcode)::ImplicitUses</tt>. Pre-colored
1607 registers impose constraints on any register allocation algorithm. The
Bob Wilson04738682010-04-09 18:39:54 +0000[diff] [blame]1608 register allocator must make sure that none of them are overwritten by
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1609 the values of virtual registers while still alive.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1610
1611</div>
1612
1613<!-- _______________________________________________________________________ -->
1614
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1615<h4>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1616 <a name="regAlloc_howTo">Mapping virtual registers to physical registers</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1617</h4>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1618
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1619<div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1620
1621<p>There are two ways to map virtual registers to physical registers (or to
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1622 memory slots). The first way, that we will call <i>direct mapping</i>, is
1623 based on the use of methods of the classes <tt>TargetRegisterInfo</tt>,
1624 and <tt>MachineOperand</tt>. The second way, that we will call <i>indirect
1625 mapping</i>, relies on the <tt>VirtRegMap</tt> class in order to insert loads
1626 and stores sending and getting values to and from memory.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1627
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1628<p>The direct mapping provides more flexibility to the developer of the register
1629 allocator; however, it is more error prone, and demands more implementation
1630 work. Basically, the programmer will have to specify where load and store
1631 instructions should be inserted in the target function being compiled in
1632 order to get and store values in memory. To assign a physical register to a
1633 virtual register present in a given operand,
1634 use <tt>MachineOperand::setReg(p_reg)</tt>. To insert a store instruction,
Jakob Stoklund Olesen297907f2010-08-31 22:01:07 +0000[diff] [blame]1635 use <tt>TargetInstrInfo::storeRegToStackSlot(...)</tt>, and to insert a
1636 load instruction, use <tt>TargetInstrInfo::loadRegFromStackSlot</tt>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1637
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1638<p>The indirect mapping shields the application developer from the complexities
1639 of inserting load and store instructions. In order to map a virtual register
1640 to a physical one, use <tt>VirtRegMap::assignVirt2Phys(vreg, preg)</tt>. In
1641 order to map a certain virtual register to memory,
1642 use <tt>VirtRegMap::assignVirt2StackSlot(vreg)</tt>. This method will return
1643 the stack slot where <tt>vreg</tt>'s value will be located. If it is
1644 necessary to map another virtual register to the same stack slot,
1645 use <tt>VirtRegMap::assignVirt2StackSlot(vreg, stack_location)</tt>. One
1646 important point to consider when using the indirect mapping, is that even if
1647 a virtual register is mapped to memory, it still needs to be mapped to a
1648 physical register. This physical register is the location where the virtual
1649 register is supposed to be found before being stored or after being
1650 reloaded.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1651
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1652<p>If the indirect strategy is used, after all the virtual registers have been
1653 mapped to physical registers or stack slots, it is necessary to use a spiller
1654 object to place load and store instructions in the code. Every virtual that
1655 has been mapped to a stack slot will be stored to memory after been defined
1656 and will be loaded before being used. The implementation of the spiller tries
1657 to recycle load/store instructions, avoiding unnecessary instructions. For an
1658 example of how to invoke the spiller,
1659 see <tt>RegAllocLinearScan::runOnMachineFunction</tt>
1660 in <tt>lib/CodeGen/RegAllocLinearScan.cpp</tt>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1661
1662</div>
1663
1664<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1665<h4>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1666 <a name="regAlloc_twoAddr">Handling two address instructions</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1667</h4>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1668
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1669<div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1670
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1671<p>With very rare exceptions (e.g., function calls), the LLVM machine code
1672 instructions are three address instructions. That is, each instruction is
1673 expected to define at most one register, and to use at most two registers.
1674 However, some architectures use two address instructions. In this case, the
1675 defined register is also one of the used register. For instance, an
1676 instruction such as <tt>ADD %EAX, %EBX</tt>, in X86 is actually equivalent
1677 to <tt>%EAX = %EAX + %EBX</tt>.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1678
1679<p>In order to produce correct code, LLVM must convert three address
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1680 instructions that represent two address instructions into true two address
1681 instructions. LLVM provides the pass <tt>TwoAddressInstructionPass</tt> for
1682 this specific purpose. It must be run before register allocation takes
1683 place. After its execution, the resulting code may no longer be in SSA
1684 form. This happens, for instance, in situations where an instruction such
1685 as <tt>%a = ADD %b %c</tt> is converted to two instructions such as:</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1686
1687<div class="doc_code">
1688<pre>
1689%a = MOVE %b
Dan Gohman03e58572008-06-13 17:55:57 +0000[diff] [blame]1690%a = ADD %a %c
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1691</pre>
1692</div>
1693
1694<p>Notice that, internally, the second instruction is represented as
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1695 <tt>ADD %a[def/use] %c</tt>. I.e., the register operand <tt>%a</tt> is both
1696 used and defined by the instruction.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1697
1698</div>
1699
1700<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1701<h4>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1702 <a name="regAlloc_ssaDecon">The SSA deconstruction phase</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1703</h4>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1704
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1705<div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1706
1707<p>An important transformation that happens during register allocation is called
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1708 the <i>SSA Deconstruction Phase</i>. The SSA form simplifies many analyses
1709 that are performed on the control flow graph of programs. However,
1710 traditional instruction sets do not implement PHI instructions. Thus, in
1711 order to generate executable code, compilers must replace PHI instructions
1712 with other instructions that preserve their semantics.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1713
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1714<p>There are many ways in which PHI instructions can safely be removed from the
1715 target code. The most traditional PHI deconstruction algorithm replaces PHI
1716 instructions with copy instructions. That is the strategy adopted by
1717 LLVM. The SSA deconstruction algorithm is implemented
1718 in <tt>lib/CodeGen/PHIElimination.cpp</tt>. In order to invoke this pass, the
1719 identifier <tt>PHIEliminationID</tt> must be marked as required in the code
1720 of the register allocator.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1721
1722</div>
1723
1724<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1725<h4>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1726 <a name="regAlloc_fold">Instruction folding</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1727</h4>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1728
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1729<div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1730
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1731<p><i>Instruction folding</i> is an optimization performed during register
1732 allocation that removes unnecessary copy instructions. For instance, a
1733 sequence of instructions such as:</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1734
1735<div class="doc_code">
1736<pre>
1737%EBX = LOAD %mem_address
1738%EAX = COPY %EBX
1739</pre>
1740</div>
1741
Dan Gohmana7ab2bf2008-11-24 16:35:31 +0000[diff] [blame]1742<p>can be safely substituted by the single instruction:</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1743
1744<div class="doc_code">
1745<pre>
1746%EAX = LOAD %mem_address
1747</pre>
1748</div>
1749
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1750<p>Instructions can be folded with
1751 the <tt>TargetRegisterInfo::foldMemoryOperand(...)</tt> method. Care must be
1752 taken when folding instructions; a folded instruction can be quite different
1753 from the original
1754 instruction. See <tt>LiveIntervals::addIntervalsForSpills</tt>
1755 in <tt>lib/CodeGen/LiveIntervalAnalysis.cpp</tt> for an example of its
1756 use.</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1757
1758</div>
1759
1760<!-- _______________________________________________________________________ -->
1761
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1762<h4>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1763 <a name="regAlloc_builtIn">Built in register allocators</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1764</h4>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1765
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1766<div>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1767
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1768<p>The LLVM infrastructure provides the application developer with three
1769 different register allocators:</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1770
1771<ul>
Jakob Stoklund Olesen8a3eab92010-06-15 21:58:33 +0000[diff] [blame]1772 <li><i>Fast</i> &mdash; This register allocator is the default for debug
1773 builds. It allocates registers on a basic block level, attempting to keep
1774 values in registers and reusing registers as appropriate.</li>
1775
Andrew Trick5acaeb52011-07-26 18:31:49 +0000[diff] [blame]1776 <li><i>Basic</i> &mdash; This is an incremental approach to register
1777 allocation. Live ranges are assigned to registers one at a time in
1778 an order that is driven by heuristics. Since code can be rewritten
1779 on-the-fly during allocation, this framework allows interesting
1780 allocators to be developed as extensions. It is not itself a
1781 production register allocator but is a potentially useful
1782 stand-alone mode for triaging bugs and as a performance baseline.
1783
1784 <li><i>Greedy</i> &mdash; <i>The default allocator</i>. This is a
1785 highly tuned implementation of the <i>Basic</i> allocator that
1786 incorporates global live range splitting. This allocator works hard
1787 to minimize the cost of spill code.
1788
Jakob Stoklund Olesen8a3eab92010-06-15 21:58:33 +0000[diff] [blame]1789 <li><i>PBQP</i> &mdash; A Partitioned Boolean Quadratic Programming (PBQP)
1790 based register allocator. This allocator works by constructing a PBQP
1791 problem representing the register allocation problem under consideration,
1792 solving this using a PBQP solver, and mapping the solution back to a
1793 register assignment.</li>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1794</ul>
1795
1796<p>The type of register allocator used in <tt>llc</tt> can be chosen with the
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]1797 command line option <tt>-regalloc=...</tt>:</p>
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1798
1799<div class="doc_code">
1800<pre>
Dan Gohman0cabaa52009-08-25 15:54:01 +0000[diff] [blame]1801$ llc -regalloc=linearscan file.bc -o ln.s;
Jakob Stoklund Olesen8a3eab92010-06-15 21:58:33 +0000[diff] [blame]1802$ llc -regalloc=fast file.bc -o fa.s;
1803$ llc -regalloc=pbqp file.bc -o pbqp.s;
Bill Wendlinga396ee82006-09-01 21:46:00 +0000[diff] [blame]1804</pre>
1805</div>
1806
1807</div>
1808
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1809</div>
1810
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1811<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1812<h3>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1813 <a name="proepicode">Prolog/Epilog Code Insertion</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1814</h3>
Bill Wendling66bc5c62011-07-25 20:19:48 +0000[diff] [blame]1815
NAKAMURA Takumi4b2e07a2011-10-31 13:04:26 +0000[diff] [blame]1816<div>
1817
Bill Wendling66bc5c62011-07-25 20:19:48 +0000[diff] [blame]1818<!-- _______________________________________________________________________ -->
1819<h4>
1820 <a name="compact_unwind">Compact Unwind</a>
1821</h4>
1822
1823<div>
1824
Bill Wendling75471d62011-07-26 07:58:09 +0000[diff] [blame]1825<p>Throwing an exception requires <em>unwinding</em> out of a function. The
1826 information on how to unwind a given function is traditionally expressed in
1827 DWARF unwind (a.k.a. frame) info. But that format was originally developed
1828 for debuggers to backtrace, and each Frame Description Entry (FDE) requires
1829 ~20-30 bytes per function. There is also the cost of mapping from an address
1830 in a function to the corresponding FDE at runtime. An alternative unwind
1831 encoding is called <em>compact unwind</em> and requires just 4-bytes per
1832 function.</p>
Bill Wendling66bc5c62011-07-25 20:19:48 +0000[diff] [blame]1833
1834<p>The compact unwind encoding is a 32-bit value, which is encoded in an
1835 architecture-specific way. It specifies which registers to restore and from
Roman Divacky4d7ce322011-08-01 20:38:27 +0000[diff] [blame]1836 where, and how to unwind out of the function. When the linker creates a final
Bill Wendling66bc5c62011-07-25 20:19:48 +0000[diff] [blame]1837 linked image, it will create a <code>__TEXT,__unwind_info</code>
1838 section. This section is a small and fast way for the runtime to access
1839 unwind info for any given function. If we emit compact unwind info for the
1840 function, that compact unwind info will be encoded in
1841 the <code>__TEXT,__unwind_info</code> section. If we emit DWARF unwind info,
1842 the <code>__TEXT,__unwind_info</code> section will contain the offset of the
1843 FDE in the <code>__TEXT,__eh_frame</code> section in the final linked
1844 image.</p>
1845
1846<p>For X86, there are three modes for the compact unwind encoding:</p>
1847
Bill Wendling75471d62011-07-26 07:58:09 +0000[diff] [blame]1848<dl>
Bill Wendling66bc5c62011-07-25 20:19:48 +0000[diff] [blame]1849 <dt><i>Function with a Frame Pointer (<code>EBP</code> or <code>RBP</code>)</i></dt>
1850 <dd><p><code>EBP/RBP</code>-based frame, where <code>EBP/RBP</code> is pushed
1851 onto the stack immediately after the return address,
1852 then <code>ESP/RSP</code> is moved to <code>EBP/RBP</code>. Thus to
1853 unwind, <code>ESP/RSP</code> is restored with the
1854 current <code>EBP/RBP</code> value, then <code>EBP/RBP</code> is restored
1855 by popping the stack, and the return is done by popping the stack once
1856 more into the PC. All non-volatile registers that need to be restored must
1857 have been saved in a small range on the stack that
1858 starts <code>EBP-4</code> to <code>EBP-1020</code> (<code>RBP-8</code>
Bill Wendling75471d62011-07-26 07:58:09 +0000[diff] [blame]1859 to <code>RBP-1020</code>). The offset (divided by 4 in 32-bit mode and 8
1860 in 64-bit mode) is encoded in bits 16-23 (mask: <code>0x00FF0000</code>).
1861 The registers saved are encoded in bits 0-14
1862 (mask: <code>0x00007FFF</code>) as five 3-bit entries from the following
1863 table:</p>
Bill Wendling66bc5c62011-07-25 20:19:48 +0000[diff] [blame]1864<table border="1" cellspacing="0">
1865 <tr>
1866 <th>Compact Number</th>
1867 <th>i386 Register</th>
1868 <th>x86-64 Regiser</th>
1869 </tr>
1870 <tr>
1871 <td>1</td>
1872 <td><code>EBX</code></td>
1873 <td><code>RBX</code></td>
1874 </tr>
1875 <tr>
1876 <td>2</td>
1877 <td><code>ECX</code></td>
1878 <td><code>R12</code></td>
1879 </tr>
1880 <tr>
1881 <td>3</td>
1882 <td><code>EDX</code></td>
1883 <td><code>R13</code></td>
1884 </tr>
1885 <tr>
1886 <td>4</td>
1887 <td><code>EDI</code></td>
1888 <td><code>R14</code></td>
1889 </tr>
1890 <tr>
1891 <td>5</td>
1892 <td><code>ESI</code></td>
1893 <td><code>R15</code></td>
1894 </tr>
1895 <tr>
1896 <td>6</td>
1897 <td><code>EBP</code></td>
1898 <td><code>RBP</code></td>
1899 </tr>
1900</table>
1901
1902</dd>
1903
Bill Wendling3ef750d2011-07-25 20:25:03 +0000[diff] [blame]1904 <dt><i>Frameless with a Small Constant Stack Size (<code>EBP</code>
1905 or <code>RBP</code> is not used as a frame pointer)</i></dt>
Bill Wendling66bc5c62011-07-25 20:19:48 +0000[diff] [blame]1906 <dd><p>To return, a constant (encoded in the compact unwind encoding) is added
1907 to the <code>ESP/RSP</code>. Then the return is done by popping the stack
1908 into the PC. All non-volatile registers that need to be restored must have
1909 been saved on the stack immediately after the return address. The stack
Bill Wendling75471d62011-07-26 07:58:09 +0000[diff] [blame]1910 size (divided by 4 in 32-bit mode and 8 in 64-bit mode) is encoded in bits
1911 16-23 (mask: <code>0x00FF0000</code>). There is a maximum stack size of
1912 1024 bytes in 32-bit mode and 2048 in 64-bit mode. The number of registers
1913 saved is encoded in bits 9-12 (mask: <code>0x00001C00</code>). Bits 0-9
1914 (mask: <code>0x000003FF</code>) contain which registers were saved and
1915 their order. (See
1916 the <code>encodeCompactUnwindRegistersWithoutFrame()</code> function
1917 in <code>lib/Target/X86FrameLowering.cpp</code> for the encoding
Bill Wendling66bc5c62011-07-25 20:19:48 +0000[diff] [blame]1918 algorithm.)</p></dd>
1919
Bill Wendling3ef750d2011-07-25 20:25:03 +0000[diff] [blame]1920 <dt><i>Frameless with a Large Constant Stack Size (<code>EBP</code>
1921 or <code>RBP</code> is not used as a frame pointer)</i></dt>
Bill Wendling66bc5c62011-07-25 20:19:48 +0000[diff] [blame]1922 <dd><p>This case is like the "Frameless with a Small Constant Stack Size"
Bill Wendling3ef750d2011-07-25 20:25:03 +0000[diff] [blame]1923 case, but the stack size is too large to encode in the compact unwind
Bill Wendling66bc5c62011-07-25 20:19:48 +0000[diff] [blame]1924 encoding. Instead it requires that the function contains "<code>subl
1925 $nnnnnn, %esp</code>" in its prolog. The compact encoding contains the
Bill Wendling3ef750d2011-07-25 20:25:03 +0000[diff] [blame]1926 offset to the <code>$nnnnnn</code> value in the function in bits 9-12
Bill Wendling66bc5c62011-07-25 20:19:48 +0000[diff] [blame]1927 (mask: <code>0x00001C00</code>).</p></dd>
Bill Wendling75471d62011-07-26 07:58:09 +0000[diff] [blame]1928</dl>
Bill Wendling66bc5c62011-07-25 20:19:48 +0000[diff] [blame]1929
1930</div>
1931
NAKAMURA Takumi4b2e07a2011-10-31 13:04:26 +0000[diff] [blame]1932</div>
1933
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1934<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1935<h3>
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1936 <a name="latemco">Late Machine Code Optimizations</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1937</h3>
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1938<div><p>To Be Written</p></div>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]1939
Reid Spencerad1f0cd2005-04-24 20:56:18 +0000[diff] [blame]1940<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1941<h3>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]1942 <a name="codeemit">Code Emission</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]1943</h3>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]1944
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]1945<div>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]1946
1947<p>The code emission step of code generation is responsible for lowering from
1948the code generator abstractions (like <a
1949href="#machinefunction">MachineFunction</a>, <a
1950href="#machineinstr">MachineInstr</a>, etc) down
1951to the abstractions used by the MC layer (<a href="#mcinst">MCInst</a>,
1952<a href="#mcstreamer">MCStreamer</a>, etc). This is
1953done with a combination of several different classes: the (misnamed)
1954target-independent AsmPrinter class, target-specific subclasses of AsmPrinter
1955(such as SparcAsmPrinter), and the TargetLoweringObjectFile class.</p>
1956
1957<p>Since the MC layer works at the level of abstraction of object files, it
1958doesn't have a notion of functions, global variables etc. Instead, it thinks
1959about labels, directives, and instructions. A key class used at this time is
1960the MCStreamer class. This is an abstract API that is implemented in different
1961ways (e.g. to output a .s file, output an ELF .o file, etc) that is effectively
1962an "assembler API". MCStreamer has one method per directive, such as EmitLabel,
1963EmitSymbolAttribute, SwitchSection, etc, which directly correspond to assembly
1964level directives.
1965</p>
1966
1967<p>If you are interested in implementing a code generator for a target, there
1968are three important things that you have to implement for your target:</p>
1969
1970<ol>
1971<li>First, you need a subclass of AsmPrinter for your target. This class
1972implements the general lowering process converting MachineFunction's into MC
1973label constructs. The AsmPrinter base class provides a number of useful methods
1974and routines, and also allows you to override the lowering process in some
1975important ways. You should get much of the lowering for free if you are
1976implementing an ELF, COFF, or MachO target, because the TargetLoweringObjectFile
1977class implements much of the common logic.</li>
1978
1979<li>Second, you need to implement an instruction printer for your target. The
1980instruction printer takes an <a href="#mcinst">MCInst</a> and renders it to a
1981raw_ostream as text. Most of this is automatically generated from the .td file
1982(when you specify something like "<tt>add $dst, $src1, $src2</tt>" in the
1983instructions), but you need to implement routines to print operands.</li>
1984
1985<li>Third, you need to implement code that lowers a <a
1986href="#machineinstr">MachineInstr</a> to an MCInst, usually implemented in
1987"&lt;target&gt;MCInstLower.cpp". This lowering process is often target
1988specific, and is responsible for turning jump table entries, constant pool
1989indices, global variable addresses, etc into MCLabels as appropriate. This
1990translation layer is also responsible for expanding pseudo ops used by the code
1991generator into the actual machine instructions they correspond to. The MCInsts
1992that are generated by this are fed into the instruction printer or the encoder.
1993</li>
1994
1995</ol>
1996
1997<p>Finally, at your choosing, you can also implement an subclass of
1998MCCodeEmitter which lowers MCInst's into machine code bytes and relocations.
1999This is important if you want to support direct .o file emission, or would like
2000to implement an assembler for your target.</p>
2001
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]2002</div>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]2003
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2004</div>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]2005
Chris Lattner22481f22010-09-21 04:03:39 +0000[diff] [blame]2006<!-- *********************************************************************** -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2007<h2>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]2008 <a name="nativeassembler">Implementing a Native Assembler</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2009</h2>
Chris Lattner22481f22010-09-21 04:03:39 +0000[diff] [blame]2010<!-- *********************************************************************** -->
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]2011
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2012<div>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]2013
Chris Lattner22481f22010-09-21 04:03:39 +0000[diff] [blame]2014<p>Though you're probably reading this because you want to write or maintain a
2015compiler backend, LLVM also fully supports building a native assemblers too.
2016We've tried hard to automate the generation of the assembler from the .td files
2017(in particular the instruction syntax and encodings), which means that a large
2018part of the manual and repetitive data entry can be factored and shared with the
2019compiler.</p>
2020
Chris Lattner674c1dc2010-10-30 17:36:36 +0000[diff] [blame]2021<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2022<h3 id="na_instparsing">Instruction Parsing</h3>
Chris Lattner674c1dc2010-10-30 17:36:36 +0000[diff] [blame]2023
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2024<div><p>To Be Written</p></div>
Chris Lattner674c1dc2010-10-30 17:36:36 +0000[diff] [blame]2025
2026
2027<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2028<h3 id="na_instaliases">
Chris Lattner674c1dc2010-10-30 17:36:36 +0000[diff] [blame]2029 Instruction Alias Processing
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2030</h3>
Chris Lattner674c1dc2010-10-30 17:36:36 +0000[diff] [blame]2031
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2032<div>
Chris Lattner674c1dc2010-10-30 17:36:36 +0000[diff] [blame]2033<p>Once the instruction is parsed, it enters the MatchInstructionImpl function.
2034The MatchInstructionImpl function performs alias processing and then does
2035actual matching.</p>
2036
Chris Lattner693173f2010-10-30 19:23:13 +0000[diff] [blame]2037<p>Alias processing is the phase that canonicalizes different lexical forms of
Chris Lattner674c1dc2010-10-30 17:36:36 +0000[diff] [blame]2038the same instructions down to one representation. There are several different
2039kinds of alias that are possible to implement and they are listed below in the
2040order that they are processed (which is in order from simplest/weakest to most
2041complex/powerful). Generally you want to use the first alias mechanism that
2042meets the needs of your instruction, because it will allow a more concise
2043description.</p>
2044
2045<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2046<h4>Mnemonic Aliases</h4>
Chris Lattner674c1dc2010-10-30 17:36:36 +0000[diff] [blame]2047
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2048<div>
Chris Lattner674c1dc2010-10-30 17:36:36 +0000[diff] [blame]2049
Chris Lattner8cf8bcc2010-10-30 19:47:49 +0000[diff] [blame]2050<p>The first phase of alias processing is simple instruction mnemonic
Chris Lattner674c1dc2010-10-30 17:36:36 +0000[diff] [blame]2051remapping for classes of instructions which are allowed with two different
Chris Lattner693173f2010-10-30 19:23:13 +0000[diff] [blame]2052mnemonics. This phase is a simple and unconditionally remapping from one input
Chris Lattner674c1dc2010-10-30 17:36:36 +0000[diff] [blame]2053mnemonic to one output mnemonic. It isn't possible for this form of alias to
2054look at the operands at all, so the remapping must apply for all forms of a
2055given mnemonic. Mnemonic aliases are defined simply, for example X86 has:
2056</p>
2057
2058<div class="doc_code">
2059<pre>
2060def : MnemonicAlias&lt;"cbw", "cbtw"&gt;;
2061def : MnemonicAlias&lt;"smovq", "movsq"&gt;;
2062def : MnemonicAlias&lt;"fldcww", "fldcw"&gt;;
2063def : MnemonicAlias&lt;"fucompi", "fucomip"&gt;;
2064def : MnemonicAlias&lt;"ud2a", "ud2"&gt;;
2065</pre>
2066</div>
2067
2068<p>... and many others. With a MnemonicAlias definition, the mnemonic is
Chris Lattner693173f2010-10-30 19:23:13 +0000[diff] [blame]2069remapped simply and directly. Though MnemonicAlias's can't look at any aspect
2070of the instruction (such as the operands) they can depend on global modes (the
2071same ones supported by the matcher), through a Requires clause:</p>
2072
2073<div class="doc_code">
2074<pre>
2075def : MnemonicAlias&lt;"pushf", "pushfq"&gt;, Requires&lt;[In64BitMode]&gt;;
2076def : MnemonicAlias&lt;"pushf", "pushfl"&gt;, Requires&lt;[In32BitMode]&gt;;
2077</pre>
2078</div>
2079
2080<p>In this example, the mnemonic gets mapped into different a new one depending
2081on the current instruction set.</p>
Chris Lattnere1b83452010-09-11 23:02:10 +0000[diff] [blame]2082
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]2083</div>
2084
Chris Lattnerc7a03fb2010-11-06 08:30:26 +0000[diff] [blame]2085<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2086<h4>Instruction Aliases</h4>
Chris Lattnerc7a03fb2010-11-06 08:30:26 +0000[diff] [blame]2087
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2088<div>
Chris Lattnerc7a03fb2010-11-06 08:30:26 +0000[diff] [blame]2089
2090<p>The most general phase of alias processing occurs while matching is
2091happening: it provides new forms for the matcher to match along with a specific
2092instruction to generate. An instruction alias has two parts: the string to
2093match and the instruction to generate. For example:
2094</p>
2095
2096<div class="doc_code">
2097<pre>
2098def : InstAlias&lt;"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8 :$src)&gt;;
2099def : InstAlias&lt;"movsx $src, $dst", (MOVSX16rm8W GR16:$dst, i8mem:$src)&gt;;
2100def : InstAlias&lt;"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8 :$src)&gt;;
2101def : InstAlias&lt;"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16 :$src)&gt;;
2102def : InstAlias&lt;"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8 :$src)&gt;;
2103def : InstAlias&lt;"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16 :$src)&gt;;
2104def : InstAlias&lt;"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32 :$src)&gt;;
2105</pre>
2106</div>
2107
2108<p>This shows a powerful example of the instruction aliases, matching the
2109same mnemonic in multiple different ways depending on what operands are present
2110in the assembly. The result of instruction aliases can include operands in a
2111different order than the destination instruction, and can use an input
2112multiple times, for example:</p>
2113
2114<div class="doc_code">
2115<pre>
2116def : InstAlias&lt;"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)&gt;;
2117def : InstAlias&lt;"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)&gt;;
2118def : InstAlias&lt;"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)&gt;;
2119def : InstAlias&lt;"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)&gt;;
2120</pre>
2121</div>
2122
2123<p>This example also shows that tied operands are only listed once. In the X86
2124backend, XOR8rr has two input GR8's and one output GR8 (where an input is tied
2125to the output). InstAliases take a flattened operand list without duplicates
Chris Lattner90fd7972010-11-06 19:57:21 +0000[diff] [blame]2126for tied operands. The result of an instruction alias can also use immediates
2127and fixed physical registers which are added as simple immediate operands in the
2128result, for example:</p>
Chris Lattner98c870f2010-11-06 19:25:43 +0000[diff] [blame]2129
2130<div class="doc_code">
2131<pre>
Chris Lattner90fd7972010-11-06 19:57:21 +0000[diff] [blame]2132// Fixed Immediate operand.
Chris Lattner98c870f2010-11-06 19:25:43 +0000[diff] [blame]2133def : InstAlias&lt;"aad", (AAD8i8 10)&gt;;
Chris Lattner90fd7972010-11-06 19:57:21 +0000[diff] [blame]2134
2135// Fixed register operand.
2136def : InstAlias&lt;"fcomi", (COM_FIr ST1)&gt;;
2137
2138// Simple alias.
2139def : InstAlias&lt;"fcomi $reg", (COM_FIr RST:$reg)&gt;;
Chris Lattner98c870f2010-11-06 19:25:43 +0000[diff] [blame]2140</pre>
2141</div>
2142
Chris Lattnerc7a03fb2010-11-06 08:30:26 +0000[diff] [blame]2143
2144<p>Instruction aliases can also have a Requires clause to make them
2145subtarget specific.</p>
2146
Bill Wendling3f58a512011-05-04 23:40:14 +0000[diff] [blame]2147<p>If the back-end supports it, the instruction printer can automatically emit
2148 the alias rather than what's being aliased. It typically leads to better,
2149 more readable code. If it's better to print out what's being aliased, then
2150 pass a '0' as the third parameter to the InstAlias definition.</p>
2151
Chris Lattnerc7a03fb2010-11-06 08:30:26 +0000[diff] [blame]2152</div>
2153
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2154</div>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]2155
Chris Lattner22481f22010-09-21 04:03:39 +0000[diff] [blame]2156<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2157<h3 id="na_matching">Instruction Matching</h3>
Chris Lattner674c1dc2010-10-30 17:36:36 +0000[diff] [blame]2158
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2159<div><p>To Be Written</p></div>
Chris Lattner22481f22010-09-21 04:03:39 +0000[diff] [blame]2160
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2161</div>
Chris Lattner22481f22010-09-21 04:03:39 +0000[diff] [blame]2162
Chris Lattneraa5bcb52005-01-28 17:22:53 +0000[diff] [blame]2163<!-- *********************************************************************** -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2164<h2>
Chris Lattner32e89f22005-10-16 18:31:08 +0000[diff] [blame]2165 <a name="targetimpls">Target-specific Implementation Notes</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2166</h2>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2167<!-- *********************************************************************** -->
2168
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2169<div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2170
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2171<p>This section of the document explains features or design decisions that are
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2172 specific to the code generator for a particular target. First we start
2173 with a table that summarizes what features are supported by each target.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2174
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]2175<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2176<h3>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2177 <a name="targetfeatures">Target Feature Matrix</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2178</h3>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2179
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2180<div>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2181
2182<p>Note that this table does not include the C backend or Cpp backends, since
2183they do not use the target independent code generator infrastructure. It also
2184doesn't list features that are not supported fully by any target yet. It
2185considers a feature to be supported if at least one subtarget supports it. A
2186feature being supported means that it is useful and works for most cases, it
2187does not indicate that there are zero known bugs in the implementation. Here
2188is the key:</p>
2189
2190
2191<table border="1" cellspacing="0">
2192 <tr>
2193 <th>Unknown</th>
2194 <th>No support</th>
2195 <th>Partial Support</th>
2196 <th>Complete Support</th>
2197 </tr>
2198 <tr>
2199 <td class="unknown"></td>
2200 <td class="no"></td>
2201 <td class="partial"></td>
2202 <td class="yes"></td>
2203 </tr>
2204</table>
2205
2206<p>Here is the table:</p>
2207
2208<table width="689" border="1" cellspacing="0">
2209<tr><td></td>
Benjamin Kramer943beeb2010-10-30 21:07:28 +0000[diff] [blame]2210<td colspan="13" align="center" style="background-color:#ffc">Target</td>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2211</tr>
2212 <tr>
2213 <th>Feature</th>
2214 <th>ARM</th>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2215 <th>CellSPU</th>
2216 <th>MBlaze</th>
2217 <th>MSP430</th>
2218 <th>Mips</th>
2219 <th>PTX</th>
2220 <th>PowerPC</th>
2221 <th>Sparc</th>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2222 <th>X86</th>
2223 <th>XCore</th>
2224 </tr>
2225
2226<tr>
2227 <td><a href="#feat_reliable">is generally reliable</a></td>
2228 <td class="yes"></td> <!-- ARM -->
Kalle Raiskila94cc4fe2010-10-25 08:57:30 +0000[diff] [blame]2229 <td class="no"></td> <!-- CellSPU -->
Wesley Peckc6a45242010-10-24 18:50:12 +0000[diff] [blame]2230 <td class="no"></td> <!-- MBlaze -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2231 <td class="unknown"></td> <!-- MSP430 -->
Bruno Cardoso Lopes9d9c4ad2011-10-25 20:09:31 +0000[diff] [blame]2232 <td class="yes"></td> <!-- Mips -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2233 <td class="no"></td> <!-- PTX -->
2234 <td class="yes"></td> <!-- PowerPC -->
2235 <td class="yes"></td> <!-- Sparc -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2236 <td class="yes"></td> <!-- X86 -->
2237 <td class="unknown"></td> <!-- XCore -->
2238</tr>
2239
2240<tr>
2241 <td><a href="#feat_asmparser">assembly parser</a></td>
2242 <td class="no"></td> <!-- ARM -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2243 <td class="no"></td> <!-- CellSPU -->
Wesley Peckd5fe3ef2010-12-20 21:54:50 +0000[diff] [blame]2244 <td class="yes"></td> <!-- MBlaze -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2245 <td class="no"></td> <!-- MSP430 -->
2246 <td class="no"></td> <!-- Mips -->
2247 <td class="no"></td> <!-- PTX -->
2248 <td class="no"></td> <!-- PowerPC -->
2249 <td class="no"></td> <!-- Sparc -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2250 <td class="yes"></td> <!-- X86 -->
2251 <td class="no"></td> <!-- XCore -->
2252</tr>
2253
2254<tr>
2255 <td><a href="#feat_disassembler">disassembler</a></td>
2256 <td class="yes"></td> <!-- ARM -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2257 <td class="no"></td> <!-- CellSPU -->
Wesley Peckd5fe3ef2010-12-20 21:54:50 +0000[diff] [blame]2258 <td class="yes"></td> <!-- MBlaze -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2259 <td class="no"></td> <!-- MSP430 -->
2260 <td class="no"></td> <!-- Mips -->
2261 <td class="no"></td> <!-- PTX -->
2262 <td class="no"></td> <!-- PowerPC -->
2263 <td class="no"></td> <!-- Sparc -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2264 <td class="yes"></td> <!-- X86 -->
2265 <td class="no"></td> <!-- XCore -->
2266</tr>
2267
2268<tr>
2269 <td><a href="#feat_inlineasm">inline asm</a></td>
2270 <td class="yes"></td> <!-- ARM -->
Kalle Raiskila94cc4fe2010-10-25 08:57:30 +0000[diff] [blame]2271 <td class="no"></td> <!-- CellSPU -->
Wesley Peckd5fe3ef2010-12-20 21:54:50 +0000[diff] [blame]2272 <td class="yes"></td> <!-- MBlaze -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2273 <td class="unknown"></td> <!-- MSP430 -->
Bruno Cardoso Lopes48461f62010-12-19 22:41:43 +0000[diff] [blame]2274 <td class="no"></td> <!-- Mips -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2275 <td class="unknown"></td> <!-- PTX -->
2276 <td class="yes"></td> <!-- PowerPC -->
2277 <td class="unknown"></td> <!-- Sparc -->
Jakob Stoklund Olesenf22e6722011-09-19 18:15:46 +0000[diff] [blame]2278 <td class="yes"></td> <!-- X86 -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2279 <td class="unknown"></td> <!-- XCore -->
2280</tr>
2281
2282<tr>
2283 <td><a href="#feat_jit">jit</a></td>
2284 <td class="partial"><a href="#feat_jit_arm">*</a></td> <!-- ARM -->
Kalle Raiskila94cc4fe2010-10-25 08:57:30 +0000[diff] [blame]2285 <td class="no"></td> <!-- CellSPU -->
Wesley Peckc6a45242010-10-24 18:50:12 +0000[diff] [blame]2286 <td class="no"></td> <!-- MBlaze -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2287 <td class="unknown"></td> <!-- MSP430 -->
Bruno Cardoso Lopes9d9c4ad2011-10-25 20:09:31 +0000[diff] [blame]2288 <td class="yes"></td> <!-- Mips -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2289 <td class="unknown"></td> <!-- PTX -->
2290 <td class="yes"></td> <!-- PowerPC -->
2291 <td class="unknown"></td> <!-- Sparc -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2292 <td class="yes"></td> <!-- X86 -->
2293 <td class="unknown"></td> <!-- XCore -->
2294</tr>
2295
2296<tr>
2297 <td><a href="#feat_objectwrite">.o&nbsp;file writing</a></td>
2298 <td class="no"></td> <!-- ARM -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2299 <td class="no"></td> <!-- CellSPU -->
Wesley Peckd5fe3ef2010-12-20 21:54:50 +0000[diff] [blame]2300 <td class="yes"></td> <!-- MBlaze -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2301 <td class="no"></td> <!-- MSP430 -->
2302 <td class="no"></td> <!-- Mips -->
2303 <td class="no"></td> <!-- PTX -->
2304 <td class="no"></td> <!-- PowerPC -->
2305 <td class="no"></td> <!-- Sparc -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2306 <td class="yes"></td> <!-- X86 -->
2307 <td class="no"></td> <!-- XCore -->
2308</tr>
2309
2310<tr>
2311 <td><a href="#feat_tailcall">tail calls</a></td>
2312 <td class="yes"></td> <!-- ARM -->
Kalle Raiskila94cc4fe2010-10-25 08:57:30 +0000[diff] [blame]2313 <td class="no"></td> <!-- CellSPU -->
Wesley Peckc6a45242010-10-24 18:50:12 +0000[diff] [blame]2314 <td class="no"></td> <!-- MBlaze -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2315 <td class="unknown"></td> <!-- MSP430 -->
Bruno Cardoso Lopes48461f62010-12-19 22:41:43 +0000[diff] [blame]2316 <td class="no"></td> <!-- Mips -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2317 <td class="unknown"></td> <!-- PTX -->
2318 <td class="yes"></td> <!-- PowerPC -->
2319 <td class="unknown"></td> <!-- Sparc -->
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2320 <td class="yes"></td> <!-- X86 -->
2321 <td class="unknown"></td> <!-- XCore -->
2322</tr>
2323
Rafael Espindola70d2b172011-11-27 22:05:46 +0000[diff] [blame]2324<tr>
2325 <td><a href="#feat_segstacks">segmented stacks</a></td>
2326 <td class="no"></td> <!-- ARM -->
2327 <td class="no"></td> <!-- CellSPU -->
2328 <td class="no"></td> <!-- MBlaze -->
2329 <td class="no"></td> <!-- MSP430 -->
2330 <td class="no"></td> <!-- Mips -->
2331 <td class="no"></td> <!-- PTX -->
2332 <td class="no"></td> <!-- PowerPC -->
2333 <td class="no"></td> <!-- Sparc -->
2334 <td class="partial"><a href="#feat_segstacks_x86">*</a></td> <!-- X86 -->
2335 <td class="no"></td> <!-- XCore -->
2336</tr>
2337
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2338
2339</table>
2340
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2341<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2342<h4 id="feat_reliable">Is Generally Reliable</h4>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2343
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2344<div>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2345<p>This box indicates whether the target is considered to be production quality.
2346This indicates that the target has been used as a static compiler to
2347compile large amounts of code by a variety of different people and is in
2348continuous use.</p>
2349</div>
2350
2351<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2352<h4 id="feat_asmparser">Assembly Parser</h4>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2353
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2354<div>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2355<p>This box indicates whether the target supports parsing target specific .s
2356files by implementing the MCAsmParser interface. This is required for llvm-mc
2357to be able to act as a native assembler and is required for inline assembly
2358support in the native .o file writer.</p>
2359
2360</div>
2361
2362
2363<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2364<h4 id="feat_disassembler">Disassembler</h4>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2365
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2366<div>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2367<p>This box indicates whether the target supports the MCDisassembler API for
2368disassembling machine opcode bytes into MCInst's.</p>
2369
2370</div>
2371
2372<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2373<h4 id="feat_inlineasm">Inline Asm</h4>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2374
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2375<div>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2376<p>This box indicates whether the target supports most popular inline assembly
2377constraints and modifiers.</p>
2378
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2379</div>
2380
2381<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2382<h4 id="feat_jit">JIT Support</h4>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2383
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2384<div>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2385<p>This box indicates whether the target supports the JIT compiler through
2386the ExecutionEngine interface.</p>
2387
Chris Lattner6fb99552010-10-24 16:24:22 +0000[diff] [blame]2388<p id="feat_jit_arm">The ARM backend has basic support for integer code
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2389in ARM codegen mode, but lacks NEON and full Thumb support.</p>
2390
2391</div>
2392
2393<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2394<h4 id="feat_objectwrite">.o File Writing</h4>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2395
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2396<div>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2397
2398<p>This box indicates whether the target supports writing .o files (e.g. MachO,
2399ELF, and/or COFF) files directly from the target. Note that the target also
2400must include an assembly parser and general inline assembly support for full
2401inline assembly support in the .o writer.</p>
2402
Chris Lattner219ddf52010-10-28 02:22:02 +0000[diff] [blame]2403<p>Targets that don't support this feature can obviously still write out .o
2404files, they just rely on having an external assembler to translate from a .s
2405file to a .o file (as is the case for many C compilers).</p>
2406
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2407</div>
2408
2409<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2410<h4 id="feat_tailcall">Tail Calls</h4>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2411
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2412<div>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2413
2414<p>This box indicates whether the target supports guaranteed tail calls. These
2415are calls marked "<a href="LangRef.html#i_call">tail</a>" and use the fastcc
2416calling convention. Please see the <a href="#tailcallopt">tail call section
2417more more details</a>.</p>
2418
2419</div>
2420
Rafael Espindola70d2b172011-11-27 22:05:46 +0000[diff] [blame]2421<!-- _______________________________________________________________________ -->
2422<h4 id="feat_segstacks">Segmented Stacks</h4>
2423
2424<div>
2425
2426<p>This box indicates whether the target supports segmented stacks. This
2427replaces the traditional large C stack with many linked segments. It
2428is compatible with the <a href="http://gcc.gnu.org/wiki/SplitStacks">gcc
2429implementation</a> used by the Go front end.</p>
2430
Rafael Espindola30c5fa22011-11-28 17:06:58 +0000[diff] [blame]2431<p id="feat_segstacks_x86">Basic support exists on the X86 backend. Currently
2432vararg doesn't work and the object files are not marked the way the gold
Rafael Espindoladda8c6f2011-11-29 19:38:09 +0000[diff] [blame^]2433linker expects, but simple Go programs can be built by dragonegg.</p>
Rafael Espindola70d2b172011-11-27 22:05:46 +0000[diff] [blame]2434
2435</div>
2436
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2437</div>
Chris Lattner68de6022010-10-24 16:18:00 +0000[diff] [blame]2438
2439<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2440<h3>
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]2441 <a name="tailcallopt">Tail call optimization</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2442</h3>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2443
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2444<div>
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]2445
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2446<p>Tail call optimization, callee reusing the stack of the caller, is currently
2447 supported on x86/x86-64 and PowerPC. It is performed if:</p>
2448
2449<ul>
Chris Lattner29689432010-03-11 00:22:57 +0000[diff] [blame]2450 <li>Caller and callee have the calling convention <tt>fastcc</tt> or
2451 <tt>cc 10</tt> (GHC call convention).</li>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2452
2453 <li>The call is a tail call - in tail position (ret immediately follows call
2454 and ret uses value of call or is void).</li>
2455
2456 <li>Option <tt>-tailcallopt</tt> is enabled.</li>
2457
2458 <li>Platform specific constraints are met.</li>
2459</ul>
2460
2461<p>x86/x86-64 constraints:</p>
2462
2463<ul>
2464 <li>No variable argument lists are used.</li>
2465
2466 <li>On x86-64 when generating GOT/PIC code only module-local calls (visibility
2467 = hidden or protected) are supported.</li>
2468</ul>
2469
2470<p>PowerPC constraints:</p>
2471
2472<ul>
2473 <li>No variable argument lists are used.</li>
2474
2475 <li>No byval parameters are used.</li>
2476
2477 <li>On ppc32/64 GOT/PIC only module-local calls (visibility = hidden or protected) are supported.</li>
2478</ul>
2479
2480<p>Example:</p>
2481
2482<p>Call as <tt>llc -tailcallopt test.ll</tt>.</p>
2483
2484<div class="doc_code">
2485<pre>
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]2486declare fastcc i32 @tailcallee(i32 inreg %a1, i32 inreg %a2, i32 %a3, i32 %a4)
2487
2488define fastcc i32 @tailcaller(i32 %in1, i32 %in2) {
2489 %l1 = add i32 %in1, %in2
2490 %tmp = tail call fastcc i32 @tailcallee(i32 %in1 inreg, i32 %in2 inreg, i32 %in1, i32 %l1)
2491 ret i32 %tmp
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2492}
2493</pre>
2494</div>
2495
2496<p>Implications of <tt>-tailcallopt</tt>:</p>
2497
2498<p>To support tail call optimization in situations where the callee has more
2499 arguments than the caller a 'callee pops arguments' convention is used. This
2500 currently causes each <tt>fastcc</tt> call that is not tail call optimized
2501 (because one or more of above constraints are not met) to be followed by a
2502 readjustment of the stack. So performance might be worse in such cases.</p>
2503
Arnold Schwaighofer9097d142008-05-14 09:17:12 +0000[diff] [blame]2504</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2505<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2506<h3>
Evan Chengdc444e92010-03-08 21:05:02 +0000[diff] [blame]2507 <a name="sibcallopt">Sibling call optimization</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2508</h3>
Evan Chengdc444e92010-03-08 21:05:02 +0000[diff] [blame]2509
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2510<div>
Evan Chengdc444e92010-03-08 21:05:02 +0000[diff] [blame]2511
2512<p>Sibling call optimization is a restricted form of tail call optimization.
2513 Unlike tail call optimization described in the previous section, it can be
2514 performed automatically on any tail calls when <tt>-tailcallopt</tt> option
2515 is not specified.</p>
2516
2517<p>Sibling call optimization is currently performed on x86/x86-64 when the
2518 following constraints are met:</p>
2519
2520<ul>
2521 <li>Caller and callee have the same calling convention. It can be either
2522 <tt>c</tt> or <tt>fastcc</tt>.
2523
2524 <li>The call is a tail call - in tail position (ret immediately follows call
2525 and ret uses value of call or is void).</li>
2526
2527 <li>Caller and callee have matching return type or the callee result is not
2528 used.
2529
2530 <li>If any of the callee arguments are being passed in stack, they must be
2531 available in caller's own incoming argument stack and the frame offsets
2532 must be the same.
2533</ul>
2534
2535<p>Example:</p>
2536<div class="doc_code">
2537<pre>
2538declare i32 @bar(i32, i32)
2539
2540define i32 @foo(i32 %a, i32 %b, i32 %c) {
2541entry:
2542 %0 = tail call i32 @bar(i32 %a, i32 %b)
2543 ret i32 %0
2544}
2545</pre>
2546</div>
2547
2548</div>
2549<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2550<h3>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2551 <a name="x86">The X86 backend</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2552</h3>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2553
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2554<div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2555
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]2556<p>The X86 code generator lives in the <tt>lib/Target/X86</tt> directory. This
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2557 code generator is capable of targeting a variety of x86-32 and x86-64
2558 processors, and includes support for ISA extensions such as MMX and SSE.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2559
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2560<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2561<h4>
Nate Begeman34509842009-01-26 02:54:45 +0000[diff] [blame]2562 <a name="x86_tt">X86 Target Triples supported</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2563</h4>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]2564
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2565<div>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]2566
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2567<p>The following are the known target triples that are supported by the X86
2568 backend. This is not an exhaustive list, and it would be useful to add those
2569 that people test.</p>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]2570
2571<ul>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2572 <li><b>i686-pc-linux-gnu</b> &mdash; Linux</li>
2573
2574 <li><b>i386-unknown-freebsd5.3</b> &mdash; FreeBSD 5.3</li>
2575
2576 <li><b>i686-pc-cygwin</b> &mdash; Cygwin on Win32</li>
2577
2578 <li><b>i686-pc-mingw32</b> &mdash; MingW on Win32</li>
2579
2580 <li><b>i386-pc-mingw32msvc</b> &mdash; MingW crosscompiler on Linux</li>
2581
2582 <li><b>i686-apple-darwin*</b> &mdash; Apple Darwin on X86</li>
Torok Edwinc457b652009-06-15 12:17:44 +0000[diff] [blame]2583
2584 <li><b>x86_64-unknown-linux-gnu</b> &mdash; Linux</li>
Chris Lattner9b988be2005-07-12 00:20:49 +0000[diff] [blame]2585</ul>
2586
2587</div>
2588
2589<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2590<h4>
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]2591 <a name="x86_cc">X86 Calling Conventions supported</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2592</h4>
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]2593
2594
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2595<div>
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]2596
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]2597<p>The following target-specific calling conventions are known to backend:</p>
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]2598
2599<ul>
Chris Lattner01ebd562011-05-22 22:28:47 +0000[diff] [blame]2600<li><b>x86_StdCall</b> &mdash; stdcall calling convention seen on Microsoft
2601 Windows platform (CC ID = 64).</li>
2602<li><b>x86_FastCall</b> &mdash; fastcall calling convention seen on Microsoft
2603 Windows platform (CC ID = 65).</li>
2604<li><b>x86_ThisCall</b> &mdash; Similar to X86_StdCall. Passes first argument
2605 in ECX, others via stack. Callee is responsible for stack cleaning. This
2606 convention is used by MSVC by default for methods in its ABI
2607 (CC ID = 70).</li>
Anton Korobeynikovbcb97702006-09-17 20:25:45 +0000[diff] [blame]2608</ul>
2609
2610</div>
2611
2612<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2613<h4>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2614 <a name="x86_memory">Representing X86 addressing modes in MachineInstrs</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2615</h4>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2616
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2617<div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2618
Misha Brukman600df452005-02-17 22:22:24 +0000[diff] [blame]2619<p>The x86 has a very flexible way of accessing memory. It is capable of
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2620 forming memory addresses of the following expression directly in integer
2621 instructions (which use ModR/M addressing):</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2622
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]2623<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2624<pre>
Chris Lattnerb91227d2009-10-10 21:30:55 +0000[diff] [blame]2625SegmentReg: Base + [1,2,4,8] * IndexReg + Disp32
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2626</pre>
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]2627</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2628
Chris Lattnerb91227d2009-10-10 21:30:55 +0000[diff] [blame]2629<p>In order to represent this, LLVM tracks no less than 5 operands for each
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2630 memory operand of this form. This means that the "load" form of
2631 '<tt>mov</tt>' has the following <tt>MachineOperand</tt>s in this order:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2632
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2633<div class="doc_code">
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2634<pre>
Chris Lattnerb91227d2009-10-10 21:30:55 +0000[diff] [blame]2635Index: 0 | 1 2 3 4 5
2636Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement Segment
2637OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm PhysReg
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2638</pre>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2639</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2640
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2641<p>Stores, and all other instructions, treat the four memory operands in the
Chris Lattnerb91227d2009-10-10 21:30:55 +0000[diff] [blame]2642 same way and in the same order. If the segment register is unspecified
2643 (regno = 0), then no segment override is generated. "Lea" operations do not
2644 have a segment register specified, so they only have 4 operands for their
2645 memory reference.</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2646
2647</div>
2648
2649<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2650<h4>
Nate Begeman34509842009-01-26 02:54:45 +0000[diff] [blame]2651 <a name="x86_memory">X86 address spaces supported</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2652</h4>
Nate Begeman34509842009-01-26 02:54:45 +0000[diff] [blame]2653
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2654<div>
Nate Begeman34509842009-01-26 02:54:45 +0000[diff] [blame]2655
Jay Foadcb88ec32011-04-06 07:55:30 +0000[diff] [blame]2656<p>x86 has a feature which provides
Dan Gohmand26795a2009-05-05 20:48:47 +0000[diff] [blame]2657 the ability to perform loads and stores to different address spaces
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2658 via the x86 segment registers. A segment override prefix byte on an
2659 instruction causes the instruction's memory access to go to the specified
2660 segment. LLVM address space 0 is the default address space, which includes
2661 the stack, and any unqualified memory accesses in a program. Address spaces
2662 1-255 are currently reserved for user-defined code. The GS-segment is
Chris Lattner1777d0c2009-05-05 18:52:19 +0000[diff] [blame]2663 represented by address space 256, while the FS-segment is represented by
2664 address space 257. Other x86 segments have yet to be allocated address space
2665 numbers.</p>
Nate Begeman34509842009-01-26 02:54:45 +0000[diff] [blame]2666
Dan Gohmand26795a2009-05-05 20:48:47 +0000[diff] [blame]2667<p>While these address spaces may seem similar to TLS via the
2668 <tt>thread_local</tt> keyword, and often use the same underlying hardware,
2669 there are some fundamental differences.</p>
2670
2671<p>The <tt>thread_local</tt> keyword applies to global variables and
2672 specifies that they are to be allocated in thread-local memory. There are
2673 no type qualifiers involved, and these variables can be pointed to with
2674 normal pointers and accessed with normal loads and stores.
2675 The <tt>thread_local</tt> keyword is target-independent at the LLVM IR
2676 level (though LLVM doesn't yet have implementations of it for some
2677 configurations).<p>
2678
2679<p>Special address spaces, in contrast, apply to static types. Every
2680 load and store has a particular address space in its address operand type,
2681 and this is what determines which address space is accessed.
2682 LLVM ignores these special address space qualifiers on global variables,
2683 and does not provide a way to directly allocate storage in them.
2684 At the LLVM IR level, the behavior of these special address spaces depends
2685 in part on the underlying OS or runtime environment, and they are specific
2686 to x86 (and LLVM doesn't yet handle them correctly in some cases).</p>
2687
2688<p>Some operating systems and runtime environments use (or may in the future
2689 use) the FS/GS-segment registers for various low-level purposes, so care
2690 should be taken when considering them.</p>
Nate Begeman34509842009-01-26 02:54:45 +0000[diff] [blame]2691
2692</div>
2693
2694<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2695<h4>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2696 <a name="x86_names">Instruction naming</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2697</h4>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2698
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2699<div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2700
Bill Wendling91e10c42006-08-28 02:26:32 +0000[diff] [blame]2701<p>An instruction name consists of the base name, a default operand size, and a
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2702 a character per operand with an optional special size. For example:</p>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2703
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2704<div class="doc_code">
2705<pre>
2706ADD8rr -&gt; add, 8-bit register, 8-bit register
2707IMUL16rmi -&gt; imul, 16-bit register, 16-bit memory, 16-bit immediate
2708IMUL16rmi8 -&gt; imul, 16-bit register, 16-bit memory, 8-bit immediate
2709MOVSX32rm16 -&gt; movsx, 32-bit register, 16-bit memory
2710</pre>
2711</div>
Chris Lattnerec94f802004-06-04 00:16:02 +0000[diff] [blame]2712
2713</div>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]2714
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2715</div>
2716
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2717<!-- ======================================================================= -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2718<h3>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2719 <a name="ppc">The PowerPC backend</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2720</h3>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2721
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2722<div>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2723
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2724<p>The PowerPC code generator lives in the lib/Target/PowerPC directory. The
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2725 code generation is retargetable to several variations or <i>subtargets</i> of
2726 the PowerPC ISA; including ppc32, ppc64 and altivec.</p>
2727
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2728<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2729<h4>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2730 <a name="ppc_abi">LLVM PowerPC ABI</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2731</h4>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2732
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2733<div>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2734
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2735<p>LLVM follows the AIX PowerPC ABI, with two deviations. LLVM uses a PC
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2736 relative (PIC) or static addressing for accessing global values, so no TOC
2737 (r2) is used. Second, r31 is used as a frame pointer to allow dynamic growth
2738 of a stack frame. LLVM takes advantage of having no TOC to provide space to
2739 save the frame pointer in the PowerPC linkage area of the caller frame.
2740 Other details of PowerPC ABI can be found at <a href=
2741 "http://developer.apple.com/documentation/DeveloperTools/Conceptual/LowLevelABI/Articles/32bitPowerPC.html"
2742 >PowerPC ABI.</a> Note: This link describes the 32 bit ABI. The 64 bit ABI
2743 is similar except space for GPRs are 8 bytes wide (not 4) and r13 is reserved
2744 for system use.</p>
2745
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2746</div>
2747
2748<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2749<h4>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2750 <a name="ppc_frame">Frame Layout</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2751</h4>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2752
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2753<div>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2754
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2755<p>The size of a PowerPC frame is usually fixed for the duration of a
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2756 function's invocation. Since the frame is fixed size, all references
2757 into the frame can be accessed via fixed offsets from the stack pointer. The
2758 exception to this is when dynamic alloca or variable sized arrays are
2759 present, then a base pointer (r31) is used as a proxy for the stack pointer
2760 and stack pointer is free to grow or shrink. A base pointer is also used if
2761 llvm-gcc is not passed the -fomit-frame-pointer flag. The stack pointer is
2762 always aligned to 16 bytes, so that space allocated for altivec vectors will
2763 be properly aligned.</p>
2764
Dan Gohman641b2792008-11-24 16:27:17 +0000[diff] [blame]2765<p>An invocation frame is laid out as follows (low memory at top);</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2766
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2767<table class="layout">
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2768 <tr>
2769 <td>Linkage<br><br></td>
2770 </tr>
2771 <tr>
2772 <td>Parameter area<br><br></td>
2773 </tr>
2774 <tr>
2775 <td>Dynamic area<br><br></td>
2776 </tr>
2777 <tr>
2778 <td>Locals area<br><br></td>
2779 </tr>
2780 <tr>
2781 <td>Saved registers area<br><br></td>
2782 </tr>
2783 <tr style="border-style: none hidden none hidden;">
2784 <td><br></td>
2785 </tr>
2786 <tr>
2787 <td>Previous Frame<br><br></td>
2788 </tr>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2789</table>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2790
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2791<p>The <i>linkage</i> area is used by a callee to save special registers prior
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2792 to allocating its own frame. Only three entries are relevant to LLVM. The
2793 first entry is the previous stack pointer (sp), aka link. This allows
2794 probing tools like gdb or exception handlers to quickly scan the frames in
2795 the stack. A function epilog can also use the link to pop the frame from the
2796 stack. The third entry in the linkage area is used to save the return
2797 address from the lr register. Finally, as mentioned above, the last entry is
2798 used to save the previous frame pointer (r31.) The entries in the linkage
2799 area are the size of a GPR, thus the linkage area is 24 bytes long in 32 bit
2800 mode and 48 bytes in 64 bit mode.</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2801
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2802<p>32 bit linkage area</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2803
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2804<table class="layout">
2805 <tr>
2806 <td>0</td>
2807 <td>Saved SP (r1)</td>
2808 </tr>
2809 <tr>
2810 <td>4</td>
2811 <td>Saved CR</td>
2812 </tr>
2813 <tr>
2814 <td>8</td>
2815 <td>Saved LR</td>
2816 </tr>
2817 <tr>
2818 <td>12</td>
2819 <td>Reserved</td>
2820 </tr>
2821 <tr>
2822 <td>16</td>
2823 <td>Reserved</td>
2824 </tr>
2825 <tr>
2826 <td>20</td>
2827 <td>Saved FP (r31)</td>
2828 </tr>
2829</table>
2830
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2831<p>64 bit linkage area</p>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2832
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2833<table class="layout">
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2834 <tr>
2835 <td>0</td>
2836 <td>Saved SP (r1)</td>
2837 </tr>
2838 <tr>
2839 <td>8</td>
2840 <td>Saved CR</td>
2841 </tr>
2842 <tr>
2843 <td>16</td>
2844 <td>Saved LR</td>
2845 </tr>
2846 <tr>
2847 <td>24</td>
2848 <td>Reserved</td>
2849 </tr>
2850 <tr>
2851 <td>32</td>
2852 <td>Reserved</td>
2853 </tr>
2854 <tr>
2855 <td>40</td>
2856 <td>Saved FP (r31)</td>
2857 </tr>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2858</table>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2859
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2860<p>The <i>parameter area</i> is used to store arguments being passed to a callee
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2861 function. Following the PowerPC ABI, the first few arguments are actually
2862 passed in registers, with the space in the parameter area unused. However,
2863 if there are not enough registers or the callee is a thunk or vararg
2864 function, these register arguments can be spilled into the parameter area.
2865 Thus, the parameter area must be large enough to store all the parameters for
2866 the largest call sequence made by the caller. The size must also be
2867 minimally large enough to spill registers r3-r10. This allows callees blind
2868 to the call signature, such as thunks and vararg functions, enough space to
2869 cache the argument registers. Therefore, the parameter area is minimally 32
2870 bytes (64 bytes in 64 bit mode.) Also note that since the parameter area is
2871 a fixed offset from the top of the frame, that a callee can access its spilt
2872 arguments using fixed offsets from the stack pointer (or base pointer.)</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2873
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2874<p>Combining the information about the linkage, parameter areas and alignment. A
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2875 stack frame is minimally 64 bytes in 32 bit mode and 128 bytes in 64 bit
2876 mode.</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2877
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2878<p>The <i>dynamic area</i> starts out as size zero. If a function uses dynamic
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2879 alloca then space is added to the stack, the linkage and parameter areas are
2880 shifted to top of stack, and the new space is available immediately below the
2881 linkage and parameter areas. The cost of shifting the linkage and parameter
2882 areas is minor since only the link value needs to be copied. The link value
2883 can be easily fetched by adding the original frame size to the base pointer.
2884 Note that allocations in the dynamic space need to observe 16 byte
2885 alignment.</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2886
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2887<p>The <i>locals area</i> is where the llvm compiler reserves space for local
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2888 variables.</p>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2889
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2890<p>The <i>saved registers area</i> is where the llvm compiler spills callee
2891 saved registers on entry to the callee.</p>
2892
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2893</div>
2894
2895<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2896<h4>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2897 <a name="ppc_prolog">Prolog/Epilog</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2898</h4>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2899
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2900<div>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2901
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2902<p>The llvm prolog and epilog are the same as described in the PowerPC ABI, with
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2903 the following exceptions. Callee saved registers are spilled after the frame
2904 is created. This allows the llvm epilog/prolog support to be common with
2905 other targets. The base pointer callee saved register r31 is saved in the
2906 TOC slot of linkage area. This simplifies allocation of space for the base
2907 pointer and makes it convenient to locate programatically and during
2908 debugging.</p>
2909
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2910</div>
2911
2912<!-- _______________________________________________________________________ -->
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2913<h4>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2914 <a name="ppc_dynamic">Dynamic Allocation</a>
NAKAMURA Takumi05d02652011-04-18 23:59:50 +0000[diff] [blame]2915</h4>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2916
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2917<div>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2918
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]2919<p><i>TODO - More to come.</i></p>
Bill Wendling80118802009-04-15 02:12:37 +0000[diff] [blame]2920
Jim Laskeyb744c252006-12-15 10:40:48 +0000[diff] [blame]2921</div>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2922
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2923</div>
2924
Justin Holewinskidceb0022011-08-11 17:34:16 +0000[diff] [blame]2925<!-- ======================================================================= -->
2926<h3>
2927 <a name="ptx">The PTX backend</a>
2928</h3>
2929
2930<div>
2931
2932<p>The PTX code generator lives in the lib/Target/PTX directory. It is
2933 currently a work-in-progress, but already supports most of the code
2934 generation functionality needed to generate correct PTX kernels for
2935 CUDA devices.</p>
2936
2937<p>The code generator can target PTX 2.0+, and shader model 1.0+. The
2938 PTX ISA Reference Manual is used as the primary source of ISA
2939 information, though an effort is made to make the output of the code
2940 generator match the output of the NVidia nvcc compiler, whenever
2941 possible.</p>
2942
2943<p>Code Generator Options:</p>
2944<table border="1" cellspacing="0">
2945 <tr>
2946 <th>Option</th>
2947 <th>Description</th>
2948 </tr>
2949 <tr>
2950 <td><code>double</code></td>
2951 <td align="left">If enabled, the map_f64_to_f32 directive is
2952 disabled in the PTX output, allowing native double-precision
2953 arithmetic</td>
2954 </tr>
2955 <tr>
2956 <td><code>no-fma</code></td>
2957 <td align="left">Disable generation of Fused-Multiply Add
2958 instructions, which may be beneficial for some devices</td>
2959 </tr>
2960 <tr>
2961 <td><code>smxy / computexy</code></td>
2962 <td align="left">Set shader model/compute capability to x.y,
2963 e.g. sm20 or compute13</td>
2964 </tr>
2965</table>
2966
2967<p>Working:</p>
2968<ul>
2969 <li>Arithmetic instruction selection (including combo FMA)</li>
2970 <li>Bitwise instruction selection</li>
2971 <li>Control-flow instruction selection</li>
2972 <li>Function calls (only on SM 2.0+ and no return arguments)</li>
2973 <li>Addresses spaces (0 = global, 1 = constant, 2 = local, 4 =
2974 shared)</li>
2975 <li>Thread synchronization (bar.sync)</li>
2976 <li>Special register reads ([N]TID, [N]CTAID, PMx, CLOCK, etc.)</li>
2977</ul>
2978
2979<p>In Progress:</p>
2980<ul>
2981 <li>Robust call instruction selection</li>
2982 <li>Stack frame allocation</li>
2983 <li>Device-specific instruction scheduling optimizations</li>
2984</ul>
2985
2986
2987</div>
2988
NAKAMURA Takumif5af6ad2011-04-23 00:30:22 +0000[diff] [blame]2989</div>
Jim Laskey762b6cb2006-12-14 17:19:50 +0000[diff] [blame]2990
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]2991<!-- *********************************************************************** -->
2992<hr>
2993<address>
2994 <a href="http://jigsaw.w3.org/css-validator/check/referer"><img
Misha Brukman44408702008-12-11 17:34:48 +0000[diff] [blame]2995 src="http://jigsaw.w3.org/css-validator/images/vcss-blue" alt="Valid CSS"></a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]2996 <a href="http://validator.w3.org/check/referer"><img
Misha Brukmanf00ddb02008-12-11 18:23:24 +0000[diff] [blame]2997 src="http://www.w3.org/Icons/valid-html401-blue" alt="Valid HTML 4.01"></a>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]2998
2999 <a href="mailto:sabre@nondot.org">Chris Lattner</a><br>
NAKAMURA Takumib9a33632011-04-09 02:13:37 +0000[diff] [blame]3000 <a href="http://llvm.org/">The LLVM Compiler Infrastructure</a><br>
Chris Lattnerce52b7e2004-06-01 06:48:00 +0000[diff] [blame]3001 Last modified: $Date$
3002</address>
3003
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