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Eugene Yasman6382ee02013-01-16 13:00:56 +02001/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
Deepa Dinamani7d6c8972011-12-14 15:16:56 -08002 *
3 * Redistribution and use in source and binary forms, with or without
Deepa Dinamani1e094942012-10-30 15:49:02 -07004 * modification, are permitted provided that the following conditions are
5 * met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above
9 * copyright notice, this list of conditions and the following
10 * disclaimer in the documentation and/or other materials provided
11 * with the distribution.
12 * * Neither the name of The Linux Foundation nor the names of its
13 * contributors may be used to endorse or promote products derived
14 * from this software without specific prior written permission.
Deepa Dinamani7d6c8972011-12-14 15:16:56 -080015 *
Deepa Dinamani1e094942012-10-30 15:49:02 -070016 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Deepa Dinamani7d6c8972011-12-14 15:16:56 -080027 */
28
29#include <debug.h>
30#include <platform/iomap.h>
Channagoud Kadabib14d6d02013-05-15 10:48:59 -070031#include <platform/irqs.h>
Channagoud Kadabi744c8902013-04-02 11:54:53 -070032#include <platform/gpio.h>
Deepa Dinamani7d6c8972011-12-14 15:16:56 -080033#include <reg.h>
34#include <target.h>
35#include <platform.h>
Pavel Nedev03511492013-03-08 19:05:32 -080036#include <dload_util.h>
Deepa Dinamani26e93262012-05-21 17:35:14 -070037#include <uart_dm.h>
Amol Jadi29f95032012-06-22 12:52:54 -070038#include <mmc.h>
Deepa Dinamanic2a9b362012-02-23 15:15:54 -080039#include <spmi.h>
Neeti Desai465491e2012-07-31 12:53:35 -070040#include <board.h>
41#include <smem.h>
42#include <baseband.h>
Deepa Dinamani9a612932012-08-14 16:15:03 -070043#include <dev/keys.h>
44#include <pm8x41.h>
Deepa Dinamanib9a57202012-12-20 18:05:11 -080045#include <crypto5_wrapper.h>
Eugene Yasmana0d18122013-02-26 13:23:05 +020046#include <hsusb.h>
47#include <clock.h>
sundarajan srinivasana098d832013-03-07 12:19:30 -080048#include <partition_parser.h>
49#include <scm.h>
50#include <platform/clock.h>
Channagoud Kadabic1fdc8d2013-04-05 11:29:23 -070051#include <platform/gpio.h>
Channagoud Kadabif84830c2013-04-19 14:35:47 -070052#include <stdlib.h>
Deepa Dinamanib9a57202012-12-20 18:05:11 -080053
54extern bool target_use_signed_kernel(void);
Channagoud Kadabi744c8902013-04-02 11:54:53 -070055static void set_sdc_power_ctrl();
Deepa Dinamani7d6c8972011-12-14 15:16:56 -080056
57static unsigned int target_id;
Deepa Dinamani07f15712013-03-08 17:02:13 -080058static uint32_t pmic_ver;
Deepa Dinamani7d6c8972011-12-14 15:16:56 -080059
Channagoud Kadabic1fdc8d2013-04-05 11:29:23 -070060#if MMC_SDHCI_SUPPORT
61struct mmc_device *dev;
62#endif
63
Deepa Dinamanic2a9b362012-02-23 15:15:54 -080064#define PMIC_ARB_CHANNEL_NUM 0
65#define PMIC_ARB_OWNER_ID 0
66
Deepa Dinamani1e094942012-10-30 15:49:02 -070067#define WDOG_DEBUG_DISABLE_BIT 17
Deepa Dinamani7d6c8972011-12-14 15:16:56 -080068
Channagoud Kadabi974391e2013-10-02 17:32:11 -070069#define CE1_INSTANCE 1
70#define CE2_INSTANCE 2
Deepa Dinamanib9a57202012-12-20 18:05:11 -080071#define CE_EE 1
72#define CE_FIFO_SIZE 64
73#define CE_READ_PIPE 3
74#define CE_WRITE_PIPE 2
Deepa Dinamani809c4282013-07-09 14:06:02 -070075#define CE_READ_PIPE_LOCK_GRP 0
76#define CE_WRITE_PIPE_LOCK_GRP 0
Deepa Dinamanib9a57202012-12-20 18:05:11 -080077#define CE_ARRAY_SIZE 20
78
sundarajan srinivasana098d832013-03-07 12:19:30 -080079#ifdef SSD_ENABLE
80#define SSD_CE_INSTANCE_1 1
81#define SSD_PARTITION_SIZE 8192
82#endif
83
Sundarajan Srinivasand00f31d2013-07-19 12:09:15 -070084#define FASTBOOT_MODE 0x77665500
85
Channagoud Kadabic48b3e92013-06-23 16:19:10 -070086#define BOARD_SOC_VERSION1(soc_rev) (soc_rev >= 0x10000 && soc_rev < 0x20000)
87
Channagoud Kadabic1fdc8d2013-04-05 11:29:23 -070088#if MMC_SDHCI_SUPPORT
89static uint32_t mmc_sdhci_base[] =
90 { MSM_SDC1_SDHCI_BASE, MSM_SDC2_SDHCI_BASE, MSM_SDC3_SDHCI_BASE, MSM_SDC4_SDHCI_BASE };
91#endif
92
Deepa Dinamanica5ad852012-05-07 18:19:47 -070093static uint32_t mmc_sdc_base[] =
94 { MSM_SDC1_BASE, MSM_SDC2_BASE, MSM_SDC3_BASE, MSM_SDC4_BASE };
95
Channagoud Kadabib14d6d02013-05-15 10:48:59 -070096static uint32_t mmc_sdc_pwrctl_irq[] =
97 { SDCC1_PWRCTL_IRQ, SDCC2_PWRCTL_IRQ, SDCC3_PWRCTL_IRQ, SDCC4_PWRCTL_IRQ };
98
Deepa Dinamani7d6c8972011-12-14 15:16:56 -080099void target_early_init(void)
100{
Deepa Dinamanib073ba22012-08-10 11:06:41 -0700101#if WITH_DEBUG_UART
Neeti Desaiac011272012-08-29 18:24:54 -0700102 uart_dm_init(1, 0, BLSP1_UART1_BASE);
Deepa Dinamanib073ba22012-08-10 11:06:41 -0700103#endif
Deepa Dinamani7d6c8972011-12-14 15:16:56 -0800104}
105
Deepa Dinamani9a612932012-08-14 16:15:03 -0700106/* Return 1 if vol_up pressed */
107static int target_volume_up()
108{
109 uint8_t status = 0;
110 struct pm8x41_gpio gpio;
111
112 /* CDP vol_up seems to be always grounded. So gpio status is read as 0,
113 * whether key is pressed or not.
114 * Ignore volume_up key on CDP for now.
115 */
116 if (board_hardware_id() == HW_PLATFORM_SURF)
117 return 0;
118
119 /* Configure the GPIO */
120 gpio.direction = PM_GPIO_DIR_IN;
121 gpio.function = 0;
122 gpio.pull = PM_GPIO_PULL_UP_30;
Eugene Yasman6382ee02013-01-16 13:00:56 +0200123 gpio.vin_sel = 2;
Deepa Dinamani9a612932012-08-14 16:15:03 -0700124
125 pm8x41_gpio_config(5, &gpio);
126
Channagoud Kadabi4d7b5302013-08-07 16:34:08 -0700127 /* Wait for the pmic gpio config to take effect */
128 thread_sleep(1);
129
Deepa Dinamani9a612932012-08-14 16:15:03 -0700130 /* Get status of P_GPIO_5 */
131 pm8x41_gpio_get(5, &status);
132
133 return !status; /* active low */
134}
135
136/* Return 1 if vol_down pressed */
Deepa Dinamani66a87962013-02-04 10:39:30 -0800137uint32_t target_volume_down()
Deepa Dinamani9a612932012-08-14 16:15:03 -0700138{
Deepa Dinamani66a87962013-02-04 10:39:30 -0800139 /* Volume down button is tied in with RESIN on MSM8974. */
Channagoud Kadabi0de103c2013-09-26 10:44:57 -0700140 if (platform_is_8974() && (pmic_ver == PM8X41_VERSION_V2))
Channagoud Kadabi84dcd912013-07-03 15:33:15 -0700141 return pm8x41_v2_resin_status();
Deepa Dinamani13bfc852013-02-05 17:56:47 -0800142 else
143 return pm8x41_resin_status();
Deepa Dinamani9a612932012-08-14 16:15:03 -0700144}
145
146static void target_keystatus()
147{
148 keys_init();
149
150 if(target_volume_down())
151 keys_post_event(KEY_VOLUMEDOWN, 1);
152
153 if(target_volume_up())
154 keys_post_event(KEY_VOLUMEUP, 1);
155}
156
Deepa Dinamanib9a57202012-12-20 18:05:11 -0800157/* Set up params for h/w CE. */
158void target_crypto_init_params()
159{
160 struct crypto_init_params ce_params;
161
162 /* Set up base addresses and instance. */
Channagoud Kadabi974391e2013-10-02 17:32:11 -0700163 if (platform_is_8x62())
164 {
165 ce_params.crypto_instance = CE1_INSTANCE;
166 ce_params.crypto_base = MSM_CE1_BASE;
167 ce_params.bam_base = MSM_CE1_BAM_BASE;
168 }
169 else
170 {
171 ce_params.crypto_instance = CE2_INSTANCE;
172 ce_params.crypto_base = MSM_CE2_BASE;
173 ce_params.bam_base = MSM_CE2_BAM_BASE;
174 }
Deepa Dinamanib9a57202012-12-20 18:05:11 -0800175
176 /* Set up BAM config. */
Deepa Dinamani809c4282013-07-09 14:06:02 -0700177 ce_params.bam_ee = CE_EE;
178 ce_params.pipes.read_pipe = CE_READ_PIPE;
179 ce_params.pipes.write_pipe = CE_WRITE_PIPE;
180 ce_params.pipes.read_pipe_grp = CE_READ_PIPE_LOCK_GRP;
181 ce_params.pipes.write_pipe_grp = CE_WRITE_PIPE_LOCK_GRP;
Deepa Dinamanib9a57202012-12-20 18:05:11 -0800182
183 /* Assign buffer sizes. */
184 ce_params.num_ce = CE_ARRAY_SIZE;
185 ce_params.read_fifo_size = CE_FIFO_SIZE;
186 ce_params.write_fifo_size = CE_FIFO_SIZE;
187
Deepa Dinamanie505d3d2013-05-14 16:55:38 -0700188 /* BAM is initialized by TZ for this platform.
189 * Do not do it again as the initialization address space
190 * is locked.
191 */
192 ce_params.do_bam_init = 0;
193
Deepa Dinamanib9a57202012-12-20 18:05:11 -0800194 crypto_init_params(&ce_params);
195}
196
197crypto_engine_type board_ce_type(void)
198{
199 return CRYPTO_ENGINE_TYPE_HW;
200}
201
Channagoud Kadabic1fdc8d2013-04-05 11:29:23 -0700202#if MMC_SDHCI_SUPPORT
Channagoud Kadabib14d6d02013-05-15 10:48:59 -0700203static void target_mmc_sdhci_init()
Channagoud Kadabic1fdc8d2013-04-05 11:29:23 -0700204{
Channagoud Kadabib14d6d02013-05-15 10:48:59 -0700205 struct mmc_config_data config = {0};
Channagoud Kadabic1fdc8d2013-04-05 11:29:23 -0700206 uint32_t soc_ver = 0;
207
Channagoud Kadabic1fdc8d2013-04-05 11:29:23 -0700208 soc_ver = board_soc_version();
209
210 /*
211 * 8974 v1 fluid devices, have a hardware bug
212 * which limits the bus width to 4 bit.
213 */
214 switch(board_hardware_id())
215 {
216 case HW_PLATFORM_FLUID:
Channagoud Kadabi0de103c2013-09-26 10:44:57 -0700217 if (platform_is_8974() && BOARD_SOC_VERSION1(soc_ver))
Channagoud Kadabic1fdc8d2013-04-05 11:29:23 -0700218 config.bus_width = DATA_BUS_WIDTH_4BIT;
Channagoud Kadabic48b3e92013-06-23 16:19:10 -0700219 else
220 config.bus_width = DATA_BUS_WIDTH_8BIT;
Channagoud Kadabic1fdc8d2013-04-05 11:29:23 -0700221 break;
222 default:
223 config.bus_width = DATA_BUS_WIDTH_8BIT;
224 };
225
Channagoud Kadabic1fdc8d2013-04-05 11:29:23 -0700226 /* Trying Slot 1*/
227 config.slot = 1;
Channagoud Kadabibdac7092013-08-20 15:28:07 -0700228 /*
229 * For 8974 AC & 8x62 platforms the software clock
230 * plan recommends to use the following frequencies:
231 * 200 MHz --> 192 MHZ
232 * 400 MHZ --> 384 MHZ
233 * only for emmc slot
234 */
235 if (platform_is_8974ac() || platform_is_8x62())
236 config.max_clk_rate = MMC_CLK_192MHZ;
237 else
238 config.max_clk_rate = MMC_CLK_200MHZ;
Channagoud Kadabib14d6d02013-05-15 10:48:59 -0700239 config.sdhc_base = mmc_sdhci_base[config.slot - 1];
240 config.pwrctl_base = mmc_sdc_base[config.slot - 1];
241 config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
Channagoud Kadabic1fdc8d2013-04-05 11:29:23 -0700242
243 if (!(dev = mmc_init(&config))) {
244 /* Trying Slot 2 next */
245 config.slot = 2;
Channagoud Kadabibdac7092013-08-20 15:28:07 -0700246 config.max_clk_rate = MMC_CLK_200MHZ;
Channagoud Kadabib14d6d02013-05-15 10:48:59 -0700247 config.sdhc_base = mmc_sdhci_base[config.slot - 1];
248 config.pwrctl_base = mmc_sdc_base[config.slot - 1];
249 config.pwr_irq = mmc_sdc_pwrctl_irq[config.slot - 1];
250
Channagoud Kadabic1fdc8d2013-04-05 11:29:23 -0700251 if (!(dev = mmc_init(&config))) {
252 dprintf(CRITICAL, "mmc init failed!");
253 ASSERT(0);
254 }
255 }
Channagoud Kadabief5332f2013-05-16 15:23:43 -0700256
257 /*
258 * MMC initialization is complete, read the partition table info
259 */
260 if (partition_read_table()) {
261 dprintf(CRITICAL, "Error reading the partition table info\n");
262 ASSERT(0);
263 }
Channagoud Kadabic1fdc8d2013-04-05 11:29:23 -0700264}
265
Channagoud Kadabi6faaf702013-09-10 15:00:51 -0700266void *target_mmc_device()
Channagoud Kadabic1fdc8d2013-04-05 11:29:23 -0700267{
Channagoud Kadabi6faaf702013-09-10 15:00:51 -0700268 return (void *) dev;
Channagoud Kadabic1fdc8d2013-04-05 11:29:23 -0700269}
Channagoud Kadabib14d6d02013-05-15 10:48:59 -0700270
Channagoud Kadabic1fdc8d2013-04-05 11:29:23 -0700271#else
Channagoud Kadabib14d6d02013-05-15 10:48:59 -0700272static void target_mmc_mci_init()
Deepa Dinamani7d6c8972011-12-14 15:16:56 -0800273{
Deepa Dinamanica5ad852012-05-07 18:19:47 -0700274 uint32_t base_addr;
275 uint8_t slot;
Deepa Dinamani7d6c8972011-12-14 15:16:56 -0800276
Channagoud Kadabic1fdc8d2013-04-05 11:29:23 -0700277 /* Trying Slot 1 */
278 slot = 1;
279 base_addr = mmc_sdc_base[slot - 1];
280
281 if (mmc_boot_main(slot, base_addr))
282 {
283 /* Trying Slot 2 next */
284 slot = 2;
285 base_addr = mmc_sdc_base[slot - 1];
286 if (mmc_boot_main(slot, base_addr)) {
287 dprintf(CRITICAL, "mmc init failed!");
288 ASSERT(0);
289 }
290 }
291}
292
293/*
294 * Function to set the capabilities for the host
295 */
296void target_mmc_caps(struct mmc_host *host)
297{
298 uint32_t soc_ver = 0;
299
300 soc_ver = board_soc_version();
301
302 /*
303 * 8974 v1 fluid devices, have a hardware bug
304 * which limits the bus width to 4 bit.
305 */
306 switch(board_hardware_id())
307 {
308 case HW_PLATFORM_FLUID:
Channagoud Kadabi0de103c2013-09-26 10:44:57 -0700309 if (platform_is_8974() && BOARD_SOC_VERSION1(soc_ver))
Channagoud Kadabic1fdc8d2013-04-05 11:29:23 -0700310 host->caps.bus_width = MMC_BOOT_BUS_WIDTH_4_BIT;
Channagoud Kadabic48b3e92013-06-23 16:19:10 -0700311 else
312 host->caps.bus_width = MMC_BOOT_BUS_WIDTH_8_BIT;
Channagoud Kadabic1fdc8d2013-04-05 11:29:23 -0700313 break;
314 default:
315 host->caps.bus_width = MMC_BOOT_BUS_WIDTH_8_BIT;
316 };
317
318 host->caps.ddr_mode = 1;
319 host->caps.hs200_mode = 1;
320 host->caps.hs_clk_rate = MMC_CLK_96MHZ;
321}
322#endif
323
324
325void target_init(void)
326{
Deepa Dinamani7d6c8972011-12-14 15:16:56 -0800327 dprintf(INFO, "target_init()\n");
328
Deepa Dinamanic2a9b362012-02-23 15:15:54 -0800329 spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
Deepa Dinamani7d6c8972011-12-14 15:16:56 -0800330
Deepa Dinamani07f15712013-03-08 17:02:13 -0800331 /* Save PM8941 version info. */
332 pmic_ver = pm8x41_get_pmic_rev();
333
Deepa Dinamani9a612932012-08-14 16:15:03 -0700334 target_keystatus();
335
Deepa Dinamanib9a57202012-12-20 18:05:11 -0800336 if (target_use_signed_kernel())
337 target_crypto_init_params();
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800338 /* Display splash screen if enabled */
339#if DISPLAY_SPLASH_SCREEN
Channagoud Kadabi8a9c6a22013-02-05 14:43:48 -0800340 dprintf(INFO, "Display Init: Start\n");
Channagoud Kadabia178a502013-09-26 10:59:47 -0700341 if (!platform_is_8x62())
Channagoud Kadabi20e0dd12013-08-06 12:30:51 -0700342 {
343 display_init();
344 }
Channagoud Kadabi8a9c6a22013-02-05 14:43:48 -0800345 dprintf(INFO, "Display Init: Done\n");
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800346#endif
Deepa Dinamanib9a57202012-12-20 18:05:11 -0800347
Channagoud Kadabi744c8902013-04-02 11:54:53 -0700348 /*
349 * Set drive strength & pull ctrl for
350 * emmc
351 */
352 set_sdc_power_ctrl();
353
Channagoud Kadabic1fdc8d2013-04-05 11:29:23 -0700354#if MMC_SDHCI_SUPPORT
355 target_mmc_sdhci_init();
356#else
357 target_mmc_mci_init();
358#endif
Deepa Dinamani7d6c8972011-12-14 15:16:56 -0800359}
360
361unsigned board_machtype(void)
362{
363 return target_id;
364}
365
366/* Do any target specific intialization needed before entering fastboot mode */
sundarajan srinivasana098d832013-03-07 12:19:30 -0800367#ifdef SSD_ENABLE
sundarajan srinivasana098d832013-03-07 12:19:30 -0800368static void ssd_load_keystore_from_emmc()
369{
370 uint64_t ptn = 0;
371 int index = -1;
372 uint32_t size = SSD_PARTITION_SIZE;
373 int ret = -1;
374
Channagoud Kadabif84830c2013-04-19 14:35:47 -0700375 uint32_t *buffer = (uint32_t *)memalign(CACHE_LINE,
376 ROUNDUP(SSD_PARTITION_SIZE, CACHE_LINE));
377
378 if (!buffer) {
379 dprintf(CRITICAL, "Error Allocating memory for SSD buffer\n");
380 ASSERT(0);
381 }
382
sundarajan srinivasana098d832013-03-07 12:19:30 -0800383 index = partition_get_index("ssd");
384
385 ptn = partition_get_offset(index);
386 if(ptn == 0){
387 dprintf(CRITICAL,"ERROR: ssd parition not found");
388 return;
389 }
390
391 if(mmc_read(ptn, buffer, size)){
392 dprintf(CRITICAL,"ERROR:Cannot read data\n");
393 return;
394 }
395
396 ret = scm_protect_keystore((uint32_t *)&buffer[0],size);
397 if(ret != 0)
398 dprintf(CRITICAL,"ERROR: scm_protect_keystore Failed");
Channagoud Kadabif84830c2013-04-19 14:35:47 -0700399
400 free(buffer);
sundarajan srinivasana098d832013-03-07 12:19:30 -0800401}
402#endif
403
Deepa Dinamani7d6c8972011-12-14 15:16:56 -0800404void target_fastboot_init(void)
405{
Deepa Dinamani9a612932012-08-14 16:15:03 -0700406 /* Set the BOOT_DONE flag in PM8921 */
Channagoud Kadabia178a502013-09-26 10:59:47 -0700407 if (!platform_is_8x62())
408 pm8x41_set_boot_done();
sundarajan srinivasana098d832013-03-07 12:19:30 -0800409
410#ifdef SSD_ENABLE
411 clock_ce_enable(SSD_CE_INSTANCE_1);
412 ssd_load_keystore_from_emmc();
413#endif
Deepa Dinamani7d6c8972011-12-14 15:16:56 -0800414}
Neeti Desai465491e2012-07-31 12:53:35 -0700415
416/* Detect the target type */
417void target_detect(struct board_data *board)
418{
419 board->target = LINUX_MACHTYPE_UNKNOWN;
420}
421
422/* Detect the modem type */
423void target_baseband_detect(struct board_data *board)
424{
Channagoud Kadabif1d44422013-02-21 22:59:35 -0800425 uint32_t platform;
Channagoud Kadabif1d44422013-02-21 22:59:35 -0800426
427 platform = board->platform;
Channagoud Kadabif1d44422013-02-21 22:59:35 -0800428
429 switch(platform) {
430 case MSM8974:
Deepa Dinamani713a76f2013-05-03 13:17:24 -0700431 case MSM8274:
432 case MSM8674:
Deepa Dinamanicaf9e772013-06-14 12:39:41 -0700433 case MSM8274AA:
434 case MSM8274AB:
435 case MSM8274AC:
436 case MSM8674AA:
437 case MSM8674AB:
438 case MSM8674AC:
439 case MSM8974AA:
440 case MSM8974AB:
441 case MSM8974AC:
Channagoud Kadabia178a502013-09-26 10:59:47 -0700442 case MSM8262:
443 case MSM8962:
Neeti Desai465491e2012-07-31 12:53:35 -0700444 board->baseband = BASEBAND_MSM;
Channagoud Kadabif1d44422013-02-21 22:59:35 -0800445 break;
446 case APQ8074:
Deepa Dinamanicaf9e772013-06-14 12:39:41 -0700447 case APQ8074AA:
448 case APQ8074AB:
449 case APQ8074AC:
Channagoud Kadabia178a502013-09-26 10:59:47 -0700450 case APQ8062:
Channagoud Kadabif1d44422013-02-21 22:59:35 -0800451 board->baseband = BASEBAND_APQ;
452 break;
453 default:
454 dprintf(CRITICAL, "Platform type: %u is not supported\n",platform);
455 ASSERT(0);
456 };
Neeti Desai465491e2012-07-31 12:53:35 -0700457}
Deepa Dinamani9a612932012-08-14 16:15:03 -0700458
Deepa Dinamani927a6b62013-03-28 17:05:32 -0700459unsigned target_baseband()
460{
461 return board_baseband();
462}
463
Deepa Dinamani9a612932012-08-14 16:15:03 -0700464void target_serialno(unsigned char *buf)
465{
466 unsigned int serialno;
467 if (target_is_emmc_boot()) {
468 serialno = mmc_get_psn();
469 snprintf((char *)buf, 13, "%x", serialno);
470 }
471}
Amol Jadi6639d452012-08-16 14:51:19 -0700472
473unsigned check_reboot_mode(void)
474{
475 uint32_t restart_reason = 0;
Channagoud Kadabi8c8587f2013-02-08 12:46:09 -0800476 uint32_t soc_ver = 0;
477 uint32_t restart_reason_addr;
478
479 soc_ver = board_soc_version();
480
Channagoud Kadabi0de103c2013-09-26 10:44:57 -0700481 if (platform_is_8974() && BOARD_SOC_VERSION1(soc_ver))
Channagoud Kadabi8c8587f2013-02-08 12:46:09 -0800482 restart_reason_addr = RESTART_REASON_ADDR;
Channagoud Kadabic48b3e92013-06-23 16:19:10 -0700483 else
484 restart_reason_addr = RESTART_REASON_ADDR_V2;
Amol Jadi6639d452012-08-16 14:51:19 -0700485
486 /* Read reboot reason and scrub it */
Channagoud Kadabi8c8587f2013-02-08 12:46:09 -0800487 restart_reason = readl(restart_reason_addr);
488 writel(0x00, restart_reason_addr);
Amol Jadi6639d452012-08-16 14:51:19 -0700489
490 return restart_reason;
491}
Neeti Desai120b55d2012-08-20 17:15:56 -0700492
493void reboot_device(unsigned reboot_reason)
494{
Channagoud Kadabi8c8587f2013-02-08 12:46:09 -0800495 uint32_t soc_ver = 0;
Sundarajan Srinivasand00f31d2013-07-19 12:09:15 -0700496 uint8_t reset_type = 0;
Channagoud Kadabi8c8587f2013-02-08 12:46:09 -0800497
498 soc_ver = board_soc_version();
499
Neeti Desai120b55d2012-08-20 17:15:56 -0700500 /* Write the reboot reason */
Channagoud Kadabi0de103c2013-09-26 10:44:57 -0700501 if (platform_is_8974() && BOARD_SOC_VERSION1(soc_ver))
Channagoud Kadabi8c8587f2013-02-08 12:46:09 -0800502 writel(reboot_reason, RESTART_REASON_ADDR);
Channagoud Kadabic48b3e92013-06-23 16:19:10 -0700503 else
504 writel(reboot_reason, RESTART_REASON_ADDR_V2);
Neeti Desai120b55d2012-08-20 17:15:56 -0700505
Sundarajan Srinivasand00f31d2013-07-19 12:09:15 -0700506 if(reboot_reason == FASTBOOT_MODE)
507 reset_type = PON_PSHOLD_WARM_RESET;
508 else
509 reset_type = PON_PSHOLD_HARD_RESET;
510
Neeti Desai120b55d2012-08-20 17:15:56 -0700511 /* Configure PMIC for warm reset */
Channagoud Kadabi0de103c2013-09-26 10:44:57 -0700512 if (platform_is_8974() && (pmic_ver == PM8X41_VERSION_V2))
Sundarajan Srinivasand00f31d2013-07-19 12:09:15 -0700513 pm8x41_v2_reset_configure(reset_type);
Deepa Dinamani07f15712013-03-08 17:02:13 -0800514 else
Sundarajan Srinivasand00f31d2013-07-19 12:09:15 -0700515 pm8x41_reset_configure(reset_type);
Neeti Desai120b55d2012-08-20 17:15:56 -0700516
Deepa Dinamani1e094942012-10-30 15:49:02 -0700517 /* Disable Watchdog Debug.
518 * Required becuase of a H/W bug which causes the system to
519 * reset partially even for non watchdog resets.
520 */
521 writel(readl(GCC_WDOG_DEBUG) & ~(1 << WDOG_DEBUG_DISABLE_BIT), GCC_WDOG_DEBUG);
522
Deepa Dinamanie0808e52012-11-26 15:22:46 -0800523 dsb();
524
525 /* Wait until the write takes effect. */
526 while(readl(GCC_WDOG_DEBUG) & (1 << WDOG_DEBUG_DISABLE_BIT));
527
Neeti Desai120b55d2012-08-20 17:15:56 -0700528 /* Drop PS_HOLD for MSM */
529 writel(0x00, MPM2_MPM_PS_HOLD);
530
531 mdelay(5000);
532
533 dprintf(CRITICAL, "Rebooting failed\n");
534}
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800535
Pavel Nedeva4c9d3a2013-05-15 14:42:34 +0300536int set_download_mode(enum dload_mode mode)
Pavel Nedev03511492013-03-08 19:05:32 -0800537{
Pavel Nedeva4c9d3a2013-05-15 14:42:34 +0300538 dload_util_write_cookie(mode == NORMAL_DLOAD ?
539 DLOAD_MODE_ADDR_V2 : EMERGENCY_DLOAD_MODE_ADDR_V2, mode);
Pavel Nedev03511492013-03-08 19:05:32 -0800540
541 return 0;
542}
543
Channagoud Kadabi6d215b92013-06-23 16:47:07 -0700544/* Check if MSM needs VBUS mimic for USB */
545static int target_needs_vbus_mimic()
546{
Channagoud Kadabi0de103c2013-09-26 10:44:57 -0700547 if (platform_is_8974())
Channagoud Kadabi6d215b92013-06-23 16:47:07 -0700548 return 0;
549
550 return 1;
551}
552
Eugene Yasmana0d18122013-02-26 13:23:05 +0200553/* Do target specific usb initialization */
554void target_usb_init(void)
555{
Channagoud Kadabi6d215b92013-06-23 16:47:07 -0700556 uint32_t val;
557
Eugene Yasmana0d18122013-02-26 13:23:05 +0200558 /* Enable secondary USB PHY on DragonBoard8074 */
559 if (board_hardware_id() == HW_PLATFORM_DRAGON) {
560 /* Route ChipIDea to use secondary USB HS port2 */
561 writel_relaxed(1, USB2_PHY_SEL);
562
563 /* Enable access to secondary PHY by clamping the low
564 * voltage interface between DVDD of the PHY and Vddcx
565 * (set bit16 (USB2_PHY_HS2_DIG_CLAMP_N_2) = 1) */
566 writel_relaxed(readl_relaxed(USB_OTG_HS_PHY_SEC_CTRL)
567 | 0x00010000, USB_OTG_HS_PHY_SEC_CTRL);
568
569 /* Perform power-on-reset of the PHY.
570 * Delay values are arbitrary */
571 writel_relaxed(readl_relaxed(USB_OTG_HS_PHY_CTRL)|1,
572 USB_OTG_HS_PHY_CTRL);
573 thread_sleep(10);
574 writel_relaxed(readl_relaxed(USB_OTG_HS_PHY_CTRL) & 0xFFFFFFFE,
575 USB_OTG_HS_PHY_CTRL);
576 thread_sleep(10);
577
578 /* Enable HSUSB PHY port for ULPI interface,
579 * then configure related parameters within the PHY */
580 writel_relaxed(((readl_relaxed(USB_PORTSC) & 0xC0000000)
581 | 0x8c000004), USB_PORTSC);
582 }
Channagoud Kadabi6d215b92013-06-23 16:47:07 -0700583
584 if (target_needs_vbus_mimic())
585 {
586 /* Select and enable external configuration with USB PHY */
587 ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_SET);
588
589 /* Enable sess_vld */
590 val = readl(USB_GENCONFIG_2) | GEN2_SESS_VLD_CTRL_EN;
591 writel(val, USB_GENCONFIG_2);
592
593 /* Enable external vbus configuration in the LINK */
594 val = readl(USB_USBCMD);
595 val |= SESS_VLD_CTRL;
596 writel(val, USB_USBCMD);
597 }
Eugene Yasmana0d18122013-02-26 13:23:05 +0200598}
599
Casey Piper74f8e5c2013-09-05 15:00:30 -0700600uint8_t target_panel_auto_detect_enabled()
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800601{
Siddhartha Agrawal17a6b832013-02-17 18:36:25 -0800602 switch(board_hardware_id())
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800603 {
Siddhartha Agrawal17a6b832013-02-17 18:36:25 -0800604 case HW_PLATFORM_SURF:
605 case HW_PLATFORM_MTP:
606 case HW_PLATFORM_FLUID:
Siddhartha Agrawal17a6b832013-02-17 18:36:25 -0800607 return 1;
608 break;
609 default:
Siddhartha Agrawal17a6b832013-02-17 18:36:25 -0800610 return 0;
Casey Piper74f8e5c2013-09-05 15:00:30 -0700611 break;
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800612 }
Casey Piper74f8e5c2013-09-05 15:00:30 -0700613 return 0;
614}
615
616static uint8_t splash_override;
617/* Returns 1 if target supports continuous splash screen. */
618int target_cont_splash_screen()
619{
620 uint8_t splash_screen = 0;
621 if(!splash_override) {
622 switch(board_hardware_id())
623 {
624 case HW_PLATFORM_SURF:
625 case HW_PLATFORM_MTP:
626 case HW_PLATFORM_FLUID:
627 case HW_PLATFORM_DRAGON:
628 case HW_PLATFORM_LIQUID:
629 dprintf(SPEW, "Target_cont_splash=1\n");
630 splash_screen = 1;
631 break;
632 default:
633 dprintf(SPEW, "Target_cont_splash=0\n");
634 splash_screen = 0;
635 }
636 }
637 return splash_screen;
638}
639
640void target_force_cont_splash_disable(uint8_t override)
641{
642 splash_override = override;
Siddhartha Agrawal7ac6d512013-01-22 18:39:50 -0800643}
sundarajan srinivasanb5db0a92013-02-12 19:19:27 -0800644
645unsigned target_pause_for_battery_charge(void)
646{
647 uint8_t pon_reason = pm8x41_get_pon_reason();
648
649 /* This function will always return 0 to facilitate
650 * automated testing/reboot with usb connected.
651 * uncomment if this feature is needed */
652 /* if ((pon_reason == USB_CHG) || (pon_reason == DC_CHG))
653 return 1;*/
654
655 return 0;
656}
sundarajan srinivasana098d832013-03-07 12:19:30 -0800657
Channagoud Kadabi9faa45b2013-06-18 18:33:02 -0700658void target_uninit(void)
sundarajan srinivasana098d832013-03-07 12:19:30 -0800659{
Channagoud Kadabi9faa45b2013-06-18 18:33:02 -0700660#if MMC_SDHCI_SUPPORT
661 mmc_put_card_to_sleep(dev);
662#else
663 mmc_put_card_to_sleep();
664#endif
sundarajan srinivasana098d832013-03-07 12:19:30 -0800665#ifdef SSD_ENABLE
666 clock_ce_disable(SSD_CE_INSTANCE_1);
667#endif
668}
Deepa Dinamani65df9822013-03-08 13:38:34 -0800669
670void shutdown_device()
671{
672 dprintf(CRITICAL, "Going down for shutdown.\n");
673
674 /* Configure PMIC for shutdown. */
Channagoud Kadabi0de103c2013-09-26 10:44:57 -0700675 if (platform_is_8974() && (pmic_ver == PM8X41_VERSION_V2))
Deepa Dinamani65df9822013-03-08 13:38:34 -0800676 pm8x41_v2_reset_configure(PON_PSHOLD_SHUTDOWN);
677 else
678 pm8x41_reset_configure(PON_PSHOLD_SHUTDOWN);
679
680 /* Drop PS_HOLD for MSM */
681 writel(0x00, MPM2_MPM_PS_HOLD);
682
683 mdelay(5000);
684
685 dprintf(CRITICAL, "Shutdown failed\n");
Channagoud Kadabi744c8902013-04-02 11:54:53 -0700686}
687
688static void set_sdc_power_ctrl()
689{
Channagoud Kadabi224d8322013-09-27 14:25:22 -0700690 uint8_t tlmm_hdrv_clk = 0;
691 uint32_t platform_id = 0;
692
693 platform_id = board_platform_id();
694
695 switch(platform_id)
696 {
697 case MSM8274AA:
698 case MSM8274AB:
699 case MSM8674AA:
700 case MSM8674AB:
701 case MSM8974AA:
702 case MSM8974AB:
703 if (board_hardware_id() == HW_PLATFORM_MTP)
704 tlmm_hdrv_clk = TLMM_CUR_VAL_10MA;
705 else
706 tlmm_hdrv_clk = TLMM_CUR_VAL_16MA;
707 break;
708 default:
709 tlmm_hdrv_clk = TLMM_CUR_VAL_16MA;
710 };
711
Channagoud Kadabi744c8902013-04-02 11:54:53 -0700712 /* Drive strength configs for sdc pins */
713 struct tlmm_cfgs sdc1_hdrv_cfg[] =
714 {
Channagoud Kadabi224d8322013-09-27 14:25:22 -0700715 { SDC1_CLK_HDRV_CTL_OFF, tlmm_hdrv_clk, TLMM_HDRV_MASK },
Channagoud Kadabi744c8902013-04-02 11:54:53 -0700716 { SDC1_CMD_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
717 { SDC1_DATA_HDRV_CTL_OFF, TLMM_CUR_VAL_10MA, TLMM_HDRV_MASK },
718 };
719
720 /* Pull configs for sdc pins */
721 struct tlmm_cfgs sdc1_pull_cfg[] =
722 {
723 { SDC1_CLK_PULL_CTL_OFF, TLMM_NO_PULL, TLMM_PULL_MASK },
724 { SDC1_CMD_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
725 { SDC1_DATA_PULL_CTL_OFF, TLMM_PULL_UP, TLMM_PULL_MASK },
726 };
727
Channagoud Kadabi389cab22013-08-20 15:29:15 -0700728 struct tlmm_cfgs sdc1_rclk_cfg[] =
729 {
730 { SDC1_RCLK_PULL_CTL_OFF, TLMM_PULL_DOWN, TLMM_PULL_MASK },
731 };
732
Channagoud Kadabi744c8902013-04-02 11:54:53 -0700733 /* Set the drive strength & pull control values */
734 tlmm_set_hdrive_ctrl(sdc1_hdrv_cfg, ARRAY_SIZE(sdc1_hdrv_cfg));
735 tlmm_set_pull_ctrl(sdc1_pull_cfg, ARRAY_SIZE(sdc1_pull_cfg));
Channagoud Kadabi389cab22013-08-20 15:29:15 -0700736
737 /* RCLK is supported only with 8974 pro, set rclk to pull down
738 * only for 8974 pro targets
739 */
740 if (!platform_is_8974())
741 tlmm_set_pull_ctrl(sdc1_rclk_cfg, ARRAY_SIZE(sdc1_rclk_cfg));
Channagoud Kadabi744c8902013-04-02 11:54:53 -0700742}
Stanimir Varbanovf64a0292013-04-29 11:58:27 +0300743
744int emmc_recovery_init(void)
745{
746 return _emmc_recovery_init();
747}
Channagoud Kadabi6d215b92013-06-23 16:47:07 -0700748
749void target_usb_stop(void)
750{
751 uint32_t platform = board_platform_id();
752
753 /* Disable VBUS mimicing in the controller. */
754 if (target_needs_vbus_mimic())
755 ulpi_write(ULPI_MISC_A_VBUSVLDEXTSEL | ULPI_MISC_A_VBUSVLDEXT, ULPI_MISC_A_CLEAR);
756}
Amol Jadi4c3229f2013-10-07 14:38:06 -0700757
758/* identify the usb controller to be used for the target */
759const char * target_usb_controller()
760{
761 switch(board_platform_id())
762 {
763 /* use dwc controller for PRO chips (with some exceptions) */
764 case MSM8974AA:
765 case MSM8974AB:
766 case MSM8974AC:
767 /* exceptions based on hardware id */
768 if (board_hardware_id() != HW_PLATFORM_DRAGON)
769 return "dwc";
770 /* fall through to default "ci" for anything that did'nt select "dwc" */
771 default:
772 return "ci";
773 }
774}
Amol Jadi28864bb2013-10-11 14:12:59 -0700775
776/* UTMI MUX configuration to connect PHY to SNPS controller:
777 * Configure primary HS phy mux to use UTMI interface
778 * (connected to usb30 controller).
779 */
780static void tcsr_hs_phy_mux_configure(void)
781{
782 uint32_t reg;
783
784 reg = readl(USB2_PHY_SEL);
785
786 writel(reg | 0x1, USB2_PHY_SEL);
787}
788
789/* configure hs phy mux if using dwc controller */
790void target_usb_phy_mux_configure(void)
791{
792 if(!strcmp(target_usb_controller(), "dwc"))
793 {
794 tcsr_hs_phy_mux_configure();
795 }
796}