Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved. |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 12 | * * Neither the name of The Linux Foundation nor the names of its |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #include <reg.h> |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 31 | #include <endian.h> |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 32 | #include <mipi_dsi.h> |
| 33 | #include <dev/fbcon.h> |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 34 | #include <stdlib.h> |
Greg Grisco | 1073a5e | 2011-07-28 18:59:18 -0700 | [diff] [blame] | 35 | #include <string.h> |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 36 | #include <debug.h> |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 37 | #include <target/display.h> |
Veera Sundaram Sankaran | 602d95a | 2014-12-09 17:55:04 -0800 | [diff] [blame] | 38 | #include <mdp5.h> |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 39 | #include <platform/iomap.h> |
| 40 | #include <platform/clock.h> |
Greg Grisco | 1073a5e | 2011-07-28 18:59:18 -0700 | [diff] [blame] | 41 | #include <platform/timer.h> |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 42 | #include <err.h> |
| 43 | #include <msm_panel.h> |
Matthew Qin | 81933ce | 2015-02-03 17:58:52 +0800 | [diff] [blame] | 44 | #include <arch/ops.h> |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 45 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 46 | extern int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg, |
| 47 | unsigned short num_of_lanes); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 48 | extern void mdp_shutdown(void); |
| 49 | extern void mdp_start_dma(void); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 50 | |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 51 | #if (DISPLAY_TYPE_MDSS == 0) |
| 52 | #define MIPI_DSI0_BASE MIPI_DSI_BASE |
| 53 | #define MIPI_DSI1_BASE MIPI_DSI_BASE |
| 54 | #endif |
| 55 | |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 56 | struct fbcon_config mipi_fb_cfg = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 57 | .height = 0, |
| 58 | .width = 0, |
| 59 | .stride = 0, |
| 60 | .format = 0, |
| 61 | .bpp = 0, |
| 62 | .update_start = NULL, |
| 63 | .update_done = NULL, |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 64 | }; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 65 | |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 66 | static char read_id_a1h_cmd[4] = { 0xA1, 0x00, 0x06, 0xA0 }; /* DTYPE_DCS_READ */ |
| 67 | static struct mipi_dsi_cmd read_ddb_start_cmd = |
| 68 | {sizeof(read_id_a1h_cmd), read_id_a1h_cmd, 0x00}; |
| 69 | |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 70 | void secure_writel(uint32_t, uint32_t); |
| 71 | uint32_t secure_readl(uint32_t); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 72 | |
Shivaraj Shetty | 6460403 | 2013-11-14 16:44:10 +0530 | [diff] [blame] | 73 | static uint32_t response_value = 0; |
| 74 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 75 | static uint32_t mdss_dsi_read_panel_signature(struct mipi_panel_info *mipi) |
Shivaraj Shetty | 6460403 | 2013-11-14 16:44:10 +0530 | [diff] [blame] | 76 | { |
| 77 | uint32_t rec_buf[1]; |
| 78 | uint32_t *lp = rec_buf, data; |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 79 | uint32_t ret = response_value; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 80 | uint32_t panel_signature = mipi->signature; |
Shivaraj Shetty | 6460403 | 2013-11-14 16:44:10 +0530 | [diff] [blame] | 81 | |
| 82 | #if (DISPLAY_TYPE_MDSS == 1) |
| 83 | if (ret && ret != panel_signature) |
| 84 | goto exit_read_signature; |
| 85 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 86 | ret = mdss_dsi_cmds_tx(mipi, &read_ddb_start_cmd, 1, 0); |
Shivaraj Shetty | 6460403 | 2013-11-14 16:44:10 +0530 | [diff] [blame] | 87 | if (ret) |
| 88 | goto exit_read_signature; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 89 | if (!mdss_dsi_cmds_rx(mipi, &lp, 1, 1)) |
Shivaraj Shetty | 6460403 | 2013-11-14 16:44:10 +0530 | [diff] [blame] | 90 | goto exit_read_signature; |
| 91 | |
| 92 | data = ntohl(*lp); |
| 93 | data = data >> 8; |
| 94 | response_value = data; |
| 95 | if (response_value != panel_signature) |
| 96 | ret = response_value; |
| 97 | |
| 98 | exit_read_signature: |
| 99 | /* Keep the non detectable panel at the end and set panel signature 0xFFFF */ |
Vineet Bajaj | c0d150d | 2014-11-07 17:04:44 +0530 | [diff] [blame] | 100 | if ((panel_signature == 0) || (panel_signature == 0xFFFF)) |
Shivaraj Shetty | 6460403 | 2013-11-14 16:44:10 +0530 | [diff] [blame] | 101 | ret = 0; |
| 102 | #endif |
| 103 | return ret; |
| 104 | } |
| 105 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 106 | static int mdss_dsi_cmd_dma_trigger_for_panel(char dual_dsi, |
| 107 | uint32_t ctl_base, uint32_t sctl_base) |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 108 | { |
| 109 | uint32_t ReadValue; |
| 110 | uint32_t count = 0; |
| 111 | int status = 0; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 112 | uint32_t base = dual_dsi ? sctl_base : ctl_base; |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 113 | |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 114 | #if (DISPLAY_TYPE_MDSS == 1) |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 115 | writel(0x03030303, ctl_base + INT_CTRL); |
| 116 | writel(0x1, ctl_base + CMD_MODE_DMA_SW_TRIGGER); |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 117 | dsb(); |
| 118 | |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 119 | if (dual_dsi) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 120 | writel(0x03030303, sctl_base + INT_CTRL); |
| 121 | writel(0x1, sctl_base + CMD_MODE_DMA_SW_TRIGGER); |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 122 | dsb(); |
| 123 | } |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 124 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 125 | ReadValue = readl(base + INT_CTRL) & 0x00000001; |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 126 | while (ReadValue != 0x00000001) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 127 | ReadValue = readl(base + INT_CTRL) & 0x00000001; |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 128 | count++; |
| 129 | if (count > 0xffff) { |
| 130 | status = FAIL; |
| 131 | dprintf(CRITICAL, |
| 132 | "Panel CMD: command mode dma test failed\n"); |
| 133 | return status; |
| 134 | } |
| 135 | } |
| 136 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 137 | writel((readl(base + INT_CTRL) | 0x01000001), base + INT_CTRL); |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 138 | dprintf(SPEW, "Panel CMD: command mode dma tested successfully\n"); |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 139 | #endif |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 140 | return status; |
| 141 | } |
| 142 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 143 | static int mdss_dsi_wait4_video_done(uint32_t ctl_base) |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 144 | { |
| 145 | unsigned long read; |
| 146 | unsigned long count = 0; |
| 147 | int status = 0; |
| 148 | |
Padmanabhan Komanduru | 66459a9 | 2014-11-04 00:05:08 +0530 | [diff] [blame] | 149 | /* If video mode is not enabled, return here */ |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 150 | if ((readl(ctl_base + CTRL) & BIT(1)) == 0) |
Padmanabhan Komanduru | 66459a9 | 2014-11-04 00:05:08 +0530 | [diff] [blame] | 151 | return 0; |
| 152 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 153 | read = readl(ctl_base + INT_CTRL); |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 154 | /* Enable VIDEO MODE DONE MASK and clear the interrupt */ |
| 155 | read = read | DSI_VIDEO_MODE_DONE_MASK | DSI_VIDEO_MODE_DONE_AK; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 156 | writel(read, ctl_base + INT_CTRL); |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 157 | dsb(); |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 158 | do { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 159 | read = readl(ctl_base + INT_CTRL) & |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 160 | DSI_VIDEO_MODE_DONE_STAT; |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 161 | count++; |
| 162 | if (count > 0xffff) { |
| 163 | status = FAIL; |
| 164 | dprintf(CRITICAL, |
| 165 | "Panel CMD: Did not recieve video mode done interrupt\n"); |
| 166 | return status; |
| 167 | } |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 168 | } while (!read); |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 169 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 170 | writel((readl(ctl_base + INT_CTRL) | 0x01000001), ctl_base + INT_CTRL); |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 171 | dprintf(SPEW, "Panel wait_4_video_done: Recieved video mode done ack\n"); |
Padmanabhan Komanduru | 66459a9 | 2014-11-04 00:05:08 +0530 | [diff] [blame] | 172 | |
| 173 | /* Skip BLLP 4ms */ |
| 174 | mdelay(4); |
| 175 | |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 176 | return status; |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 177 | } |
| 178 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 179 | int mdss_dsi_cmds_tx(struct mipi_panel_info *mipi, |
| 180 | struct mipi_dsi_cmd *cmds, int count, char dual_dsi) |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 181 | { |
| 182 | int ret = 0; |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 183 | #if (DISPLAY_TYPE_MDSS == 1) |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 184 | struct mipi_dsi_cmd *cm; |
| 185 | int i = 0; |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 186 | uint8_t pload[256]; |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 187 | uint32_t off; |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 188 | uint32_t size; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 189 | uint32_t ctl_base, sctl_base; |
| 190 | |
| 191 | /* if dest controller is not specified, default to DSI0 */ |
| 192 | if (!mipi) { |
| 193 | ctl_base = MIPI_DSI0_BASE; |
| 194 | sctl_base = MIPI_DSI1_BASE; |
| 195 | } else { |
| 196 | ctl_base = mipi->ctl_base; |
| 197 | sctl_base = mipi->sctl_base; |
| 198 | } |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 199 | |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 200 | /* Align pload at 8 byte boundary */ |
| 201 | off = (uint32_t) pload; |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 202 | off &= 0x07; |
| 203 | if (off) |
| 204 | off = 8 - off; |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 205 | off += (uint32_t) pload; |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 206 | |
| 207 | cm = cmds; |
| 208 | for (i = 0; i < count; i++) { |
Padmanabhan Komanduru | 66459a9 | 2014-11-04 00:05:08 +0530 | [diff] [blame] | 209 | /* Wait for VIDEO_MODE_DONE */ |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 210 | ret = mdss_dsi_wait4_video_done(ctl_base); |
Padmanabhan Komanduru | 66459a9 | 2014-11-04 00:05:08 +0530 | [diff] [blame] | 211 | if (ret) |
| 212 | goto wait4video_error; |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 213 | |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 214 | /* The payload size has to be a multiple of 4 */ |
| 215 | size = cm->size; |
| 216 | size &= 0x03; |
| 217 | if (size) |
| 218 | size = 4 - size; |
| 219 | size += cm->size; |
| 220 | memcpy((uint8_t *)off, (cm->payload), size); |
Matthew Qin | 81933ce | 2015-02-03 17:58:52 +0800 | [diff] [blame] | 221 | arch_clean_invalidate_cache_range((addr_t)(off), size); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 222 | writel(off, ctl_base + DMA_CMD_OFFSET); |
| 223 | writel(size, ctl_base + DMA_CMD_LENGTH); |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 224 | if (dual_dsi) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 225 | writel(off, sctl_base + DMA_CMD_OFFSET); |
| 226 | writel(size, sctl_base + DMA_CMD_LENGTH); |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 227 | } |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 228 | dsb(); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 229 | ret += mdss_dsi_cmd_dma_trigger_for_panel(dual_dsi, ctl_base, |
| 230 | sctl_base); |
Dhaval Patel | 607a624 | 2013-10-29 12:37:24 -0700 | [diff] [blame] | 231 | if (cm->wait) |
| 232 | mdelay(cm->wait); |
| 233 | else |
| 234 | udelay(80); |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 235 | cm++; |
| 236 | } |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 237 | wait4video_error: |
Padmanabhan Komanduru | 66459a9 | 2014-11-04 00:05:08 +0530 | [diff] [blame] | 238 | #endif |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 239 | return ret; |
| 240 | } |
| 241 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 242 | int mdss_dsi_cmds_rx(struct mipi_panel_info *mipi, uint32_t **rp, int rp_len, |
| 243 | int rdbk_len) |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 244 | { |
| 245 | uint32_t *lp, data; |
Veera Sundaram Sankaran | db0b2bf | 2014-12-16 18:09:27 -0800 | [diff] [blame] | 246 | uint32_t *dp; |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 247 | int i, off; |
| 248 | int rlen, res; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 249 | uint32_t ctl_base; |
| 250 | |
| 251 | /* if dest controller is not specified, default to DSI0 */ |
| 252 | if (!mipi) |
| 253 | ctl_base = MIPI_DSI0_BASE; |
| 254 | else |
| 255 | ctl_base = mipi->ctl_base; |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 256 | |
| 257 | if (rdbk_len > rp_len) { |
| 258 | return 0; |
| 259 | } |
| 260 | |
| 261 | if (rdbk_len <= 2) |
| 262 | rlen = 4; /* short read */ |
| 263 | else |
| 264 | rlen = MIPI_DSI_MRPS + 6; /* 4 bytes header + 2 bytes crc */ |
| 265 | |
| 266 | if (rlen > MIPI_DSI_REG_LEN) { |
| 267 | return 0; |
| 268 | } |
| 269 | |
| 270 | res = rlen & 0x03; |
| 271 | |
| 272 | rlen += res; /* 4 byte align */ |
| 273 | lp = *rp; |
| 274 | |
| 275 | rlen += 3; |
| 276 | rlen >>= 2; |
| 277 | |
| 278 | if (rlen > 4) |
| 279 | rlen = 4; /* 4 x 32 bits registers only */ |
| 280 | |
Shivaraj Shetty | 3c77da6 | 2013-12-09 15:58:16 +0530 | [diff] [blame] | 281 | off = RDBK_DATA0; |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 282 | off += ((rlen - 1) * 4); |
| 283 | |
| 284 | for (i = 0; i < rlen; i++) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 285 | data = readl(ctl_base + off); |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 286 | *lp = ntohl(data); /* to network byte order */ |
| 287 | lp++; |
| 288 | |
| 289 | off -= 4; |
| 290 | } |
| 291 | |
| 292 | if (rdbk_len > 2) { |
| 293 | /*First 4 bytes + paded bytes will be header next len bytes would be payload */ |
| 294 | for (i = 0; i < rdbk_len; i++) { |
| 295 | dp = *rp; |
| 296 | dp[i] = dp[(res + i) >> 2]; |
| 297 | } |
| 298 | } |
| 299 | return rdbk_len; |
| 300 | } |
| 301 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 302 | static int mdss_dsi_cmd_bta_sw_trigger(uint32_t ctl_base) |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 303 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 304 | uint32_t data; |
| 305 | int cnt = 0; |
| 306 | int err = 0; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 307 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 308 | writel(0x01, ctl_base + 0x094); /* trigger */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 309 | while (cnt < 10000) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 310 | data = readl(ctl_base + 0x0004); /*DSI_STATUS */ |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 311 | if ((data & 0x0010) == 0) |
| 312 | break; |
| 313 | cnt++; |
| 314 | } |
| 315 | if (cnt == 10000) |
| 316 | err = 1; |
| 317 | return err; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 318 | } |
| 319 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 320 | int mdss_dsi_host_init(struct mipi_panel_info *mipi, uint32_t |
Dhaval Patel | 9207dec | 2014-04-16 10:45:32 -0700 | [diff] [blame] | 321 | dual_dsi, uint32_t broadcast) |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 322 | { |
| 323 | uint8_t DMA_STREAM1 = 0; // for mdp display processor path |
| 324 | uint8_t EMBED_MODE1 = 1; // from frame buffer |
| 325 | uint8_t POWER_MODE2 = 1; // from frame buffer |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 326 | uint8_t PACK_TYPE1 = 0; // long packet |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 327 | uint8_t VC1 = 0; |
| 328 | uint8_t DT1 = 0; // non embedded mode |
| 329 | uint8_t WC1 = 0; // for non embedded mode only |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 330 | uint8_t DLNx_EN; |
Siddhartha Agrawal | 2679a82 | 2013-05-31 19:15:12 -0700 | [diff] [blame] | 331 | uint8_t lane_swap = 0; |
Siddhartha Agrawal | b6c861f | 2013-05-31 19:36:44 -0700 | [diff] [blame] | 332 | uint32_t timing_ctl = 0; |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 333 | uint32_t lane_swap_dsi1 = 0; |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 334 | uint32_t ctrl_mode = 0x105; //Default is command mode to send cmds. |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 335 | |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 336 | #if (DISPLAY_TYPE_MDSS == 1) |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 337 | switch (mipi->num_of_lanes) { |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 338 | default: |
| 339 | case 1: |
| 340 | DLNx_EN = 1; // 1 lane |
| 341 | break; |
| 342 | case 2: |
| 343 | DLNx_EN = 3; // 2 lane |
| 344 | break; |
| 345 | case 3: |
| 346 | DLNx_EN = 7; // 3 lane |
| 347 | break; |
| 348 | case 4: |
| 349 | DLNx_EN = 0x0F; /* 4 lanes */ |
| 350 | break; |
| 351 | } |
| 352 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 353 | lane_swap = mipi->lane_swap; |
| 354 | timing_ctl = ((mipi->t_clk_post << 8) | mipi->t_clk_pre); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 355 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 356 | if (mipi->cmds_post_tg) { |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 357 | /* |
| 358 | * Need to send pixel data before sending the ON commands |
| 359 | * so need to configure controller to VIDEO MODE. |
| 360 | */ |
| 361 | ctrl_mode = 0x103; |
| 362 | } |
| 363 | |
Dhaval Patel | 9207dec | 2014-04-16 10:45:32 -0700 | [diff] [blame] | 364 | if (dual_dsi) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 365 | writel(0x0001, mipi->sctl_base + SOFT_RESET); |
| 366 | writel(0x0000, mipi->sctl_base + SOFT_RESET); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 367 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 368 | /* Turn on all DSI Clks */ |
| 369 | writel((0 << 16) | 0x3f, mipi->sctl_base + CLK_CTRL); |
| 370 | writel(DMA_STREAM1 << 8 | 0x04, mipi->sctl_base + TRIG_CTRL); |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 371 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 372 | writel(0 << 30 | DLNx_EN << 4 | ctrl_mode, mipi->sctl_base + CTRL); |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 373 | writel(broadcast << 31 | EMBED_MODE1 << 28 | POWER_MODE2 << 26 |
| 374 | | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1, |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 375 | mipi->sctl_base + COMMAND_MODE_DMA_CTRL); |
Siddhartha Agrawal | 2679a82 | 2013-05-31 19:15:12 -0700 | [diff] [blame] | 376 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 377 | /* for 8939 hw dsi1 has Lane_map as 3210 */ |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 378 | if (readl(mipi->ctl_base) == DSI_HW_REV_103_1) |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 379 | lane_swap_dsi1 = 0x7; |
| 380 | else |
| 381 | lane_swap_dsi1 = lane_swap; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 382 | writel(lane_swap_dsi1, mipi->sctl_base + LANE_SWAP_CTL); |
| 383 | writel(timing_ctl, mipi->sctl_base + TIMING_CTL); |
Ray Zhang | 8da5e5d | 2015-01-21 10:14:09 +0800 | [diff] [blame] | 384 | |
| 385 | if (mipi->force_clk_lane_hs) { |
| 386 | uint32_t tmp; |
| 387 | |
| 388 | tmp = readl(mipi->sctl_base + LANE_CTL); |
| 389 | tmp |= BIT(28); |
| 390 | writel(tmp, mipi->sctl_base + LANE_CTL); |
| 391 | } |
Sandeep Panda | d9cc3a9 | 2015-05-25 15:19:38 +0530 | [diff] [blame] | 392 | |
| 393 | if ((mipi->mode == DSI_CMD_MODE) && |
| 394 | (readl(mipi->sctl_base) >= DSI_HW_REV_103)) { |
| 395 | uint32_t tmp; |
| 396 | tmp = readl(mipi->sctl_base + 0x01b8); |
| 397 | tmp |= BIT(16); /* enable burst mode */ |
| 398 | writel(tmp, mipi->sctl_base + 0x01b8); |
| 399 | } |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 400 | } |
| 401 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 402 | writel(0x0001, mipi->ctl_base + SOFT_RESET); |
| 403 | writel(0x0000, mipi->ctl_base + SOFT_RESET); |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 404 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 405 | /* Turn on all DSI Clks */ |
| 406 | writel((0 << 16) | 0x3f, mipi->ctl_base + CLK_CTRL); |
| 407 | writel(DMA_STREAM1 << 8 | 0x04, mipi->ctl_base + TRIG_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 408 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 409 | writel(0 << 30 | DLNx_EN << 4 | ctrl_mode, mipi->ctl_base + CTRL); |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 410 | writel(broadcast << 31 | EMBED_MODE1 << 28 | POWER_MODE2 << 26 |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 411 | | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1, |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 412 | mipi->ctl_base + COMMAND_MODE_DMA_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 413 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 414 | writel(lane_swap, mipi->ctl_base + LANE_SWAP_CTL); |
| 415 | writel(timing_ctl, mipi->ctl_base + TIMING_CTL); |
Ray Zhang | 8da5e5d | 2015-01-21 10:14:09 +0800 | [diff] [blame] | 416 | |
| 417 | if (mipi->force_clk_lane_hs) { |
| 418 | uint32_t tmp; |
| 419 | |
| 420 | tmp = readl(mipi->ctl_base + LANE_CTL); |
| 421 | tmp |= BIT(28); |
| 422 | writel(tmp, mipi->ctl_base + LANE_CTL); |
| 423 | } |
Huaibin Yang | 952dce3 | 2015-02-19 18:01:27 -0800 | [diff] [blame] | 424 | |
Sandeep Panda | d9cc3a9 | 2015-05-25 15:19:38 +0530 | [diff] [blame] | 425 | if ((mipi->mode == DSI_CMD_MODE) && |
| 426 | (readl(mipi->ctl_base) >= DSI_HW_REV_103)) { |
| 427 | uint32_t tmp; |
| 428 | tmp = readl(mipi->ctl_base + 0x01b8); |
| 429 | tmp |= BIT(16); /* enable burst mode */ |
| 430 | writel(tmp, mipi->ctl_base + 0x01b8); |
| 431 | } |
| 432 | |
Huaibin Yang | 952dce3 | 2015-02-19 18:01:27 -0800 | [diff] [blame] | 433 | if ((mipi->mode == DSI_VIDEO_MODE) && mipi->tx_eot_append) |
| 434 | writel(0x1, mipi->ctl_base + EOT_PACKET_CTRL); |
| 435 | |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 436 | #endif |
Siddhartha Agrawal | 2679a82 | 2013-05-31 19:15:12 -0700 | [diff] [blame] | 437 | |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 438 | return 0; |
| 439 | } |
| 440 | |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 441 | void mdss_dsi_panel_shutdown(struct msm_panel_info *pinfo) |
| 442 | { |
| 443 | #if (DISPLAY_TYPE_MDSS == 1) |
| 444 | unsigned long read_val = 0; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 445 | uint32_t ctl_base = pinfo->mipi.ctl_base; |
| 446 | uint32_t sctl_base = pinfo->mipi.sctl_base; |
| 447 | |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 448 | if (pinfo->mipi.panel_off_cmds) { |
| 449 | /* |
| 450 | * Once MDP TG is disabled, reset of DSI controller is |
| 451 | * needed before we send panel OFF commands. |
| 452 | */ |
| 453 | if (pinfo->type == MIPI_VIDEO_PANEL) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 454 | read_val = readl(ctl_base + CTRL); |
| 455 | writel((read_val & ~BIT(0)), ctl_base + CTRL); |
| 456 | writel(0x0001, ctl_base + SOFT_RESET); |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 457 | dsb(); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 458 | writel(0x0000, ctl_base + SOFT_RESET); |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 459 | dsb(); |
| 460 | /* Enable cmd mode only */ |
| 461 | writel(((read_val & ~BIT(1)) | BIT(2)), |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 462 | ctl_base + CTRL); |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 463 | } |
| 464 | |
| 465 | if (pinfo->mipi.broadcast) { |
| 466 | if (pinfo->type == MIPI_VIDEO_PANEL) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 467 | read_val = readl(sctl_base + CTRL); |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 468 | writel((read_val & ~BIT(0)), |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 469 | sctl_base + CTRL); |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 470 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 471 | writel(0x0001, sctl_base + SOFT_RESET); |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 472 | dsb(); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 473 | writel(0x0000, sctl_base + SOFT_RESET); |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 474 | dsb(); |
| 475 | |
| 476 | writel(((read_val & ~BIT(1)) | BIT(2)), |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 477 | sctl_base + CTRL); |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 478 | } |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 479 | } |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 480 | mdss_dsi_cmds_tx(&pinfo->mipi, pinfo->mipi.panel_off_cmds, |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 481 | pinfo->mipi.num_of_panel_off_cmds, |
| 482 | pinfo->mipi.broadcast); |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 483 | } |
| 484 | #endif |
| 485 | } |
| 486 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 487 | int mdss_dsi_panel_initialize(struct mipi_panel_info *mipi, uint32_t |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 488 | broadcast) |
| 489 | { |
| 490 | int status = 0; |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 491 | uint32_t ctrl_mode = 0; |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 492 | |
| 493 | #if (DISPLAY_TYPE_MDSS == 1) |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 494 | if (!mipi->panel_on_cmds) |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 495 | goto end; |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 496 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 497 | ctrl_mode = readl(mipi->ctl_base + CTRL); |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 498 | |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 499 | /* Enable command mode before sending the commands. */ |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 500 | writel(ctrl_mode | 0x04, mipi->ctl_base + CTRL); |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 501 | if (broadcast) |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 502 | writel(ctrl_mode | 0x04, mipi->sctl_base + CTRL); |
| 503 | status = mdss_dsi_cmds_tx(mipi, mipi->panel_on_cmds, |
| 504 | mipi->num_of_panel_on_cmds, broadcast); |
| 505 | writel(ctrl_mode, mipi->ctl_base + CTRL); |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 506 | if (broadcast) |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 507 | writel(ctrl_mode, mipi->sctl_base + CTRL); |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 508 | |
| 509 | if (!broadcast && !status && target_panel_auto_detect_enabled()) |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 510 | status = mdss_dsi_read_panel_signature(mipi); |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 511 | |
| 512 | end: |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 513 | #endif |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 514 | return status; |
| 515 | } |
| 516 | |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 517 | int mdss_dsi_video_mode_config(struct msm_panel_info *pinfo, |
| 518 | uint16_t disp_width, |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 519 | uint16_t disp_height, |
| 520 | uint16_t img_width, |
| 521 | uint16_t img_height, |
| 522 | uint16_t hsync_porch0_fp, |
| 523 | uint16_t hsync_porch0_bp, |
| 524 | uint16_t vsync_porch0_fp, |
| 525 | uint16_t vsync_porch0_bp, |
| 526 | uint16_t hsync_width, |
| 527 | uint16_t vsync_width, |
| 528 | uint16_t dst_format, |
| 529 | uint16_t traffic_mode, |
| 530 | uint8_t lane_en, |
Padmanabhan Komanduru | e320987 | 2015-01-12 16:33:16 +0530 | [diff] [blame] | 531 | uint8_t pulse_mode_hsa_he, |
| 532 | uint32_t low_pwr_stop_mode, |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 533 | uint8_t eof_bllp_pwr, |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 534 | uint8_t interleav, |
| 535 | uint32_t ctl_base) |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 536 | { |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 537 | int status = 0; |
| 538 | |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 539 | #if (DISPLAY_TYPE_MDSS == 1) |
Padmanabhan Komanduru | 684b58f | 2015-02-11 16:22:51 +0530 | [diff] [blame] | 540 | int last_line_interleave_en = 0; |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 541 | struct dsc_desc *dsc = NULL; |
| 542 | |
| 543 | if (pinfo->compression_mode == COMPRESSION_DSC) |
| 544 | dsc = &pinfo->dsc; |
Padmanabhan Komanduru | 684b58f | 2015-02-11 16:22:51 +0530 | [diff] [blame] | 545 | |
| 546 | /*Check if EOF_BLLP_PWR_MODE bit is set*/ |
| 547 | if(eof_bllp_pwr & 0x8) |
| 548 | last_line_interleave_en = 1; |
| 549 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 550 | writel(0x00000000, ctl_base + CLK_CTRL); |
| 551 | writel(0x00000002, ctl_base + CLK_CTRL); |
| 552 | writel(0x00000006, ctl_base + CLK_CTRL); |
| 553 | writel(0x0000000e, ctl_base + CLK_CTRL); |
| 554 | writel(0x0000001e, ctl_base + CLK_CTRL); |
| 555 | writel(0x0000023f, ctl_base + CLK_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 556 | |
Padmanabhan Komanduru | 2f8e0bc | 2014-11-27 18:25:36 +0530 | [diff] [blame] | 557 | writel(0x03f03fe0, ctl_base + ERR_INT_MASK0); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 558 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 559 | writel(0x02020202, ctl_base + INT_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 560 | |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 561 | /* For 8916/8939, enable DSI timing double buffering */ |
Kuogee Hsieh | 861e25d | 2014-10-29 16:50:15 -0700 | [diff] [blame] | 562 | if (readl(ctl_base) >= DSI_HW_REV_103 && |
Shivaraj Shetty | 41d2d48 | 2014-11-04 16:07:32 +0530 | [diff] [blame] | 563 | mdp_get_revision() != MDP_REV_305) |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 564 | writel(0x1, ctl_base + TIMING_DB_MODE); |
| 565 | |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 566 | writel(((disp_width + hsync_porch0_bp) << 16) | hsync_porch0_bp, |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 567 | ctl_base + VIDEO_MODE_ACTIVE_H); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 568 | |
| 569 | writel(((disp_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp), |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 570 | ctl_base + VIDEO_MODE_ACTIVE_V); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 571 | |
Terence Hampson | 7385f6a | 2013-08-16 15:31:25 -0400 | [diff] [blame] | 572 | if (mdp_get_revision() >= MDP_REV_41 || |
Shivaraj Shetty | f9e10c4 | 2014-09-17 04:21:15 +0530 | [diff] [blame] | 573 | mdp_get_revision() == MDP_REV_304 || |
| 574 | mdp_get_revision() == MDP_REV_305) { |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 575 | writel(((disp_height + vsync_porch0_fp |
| 576 | + vsync_porch0_bp - 1) << 16) |
| 577 | | (disp_width + hsync_porch0_fp |
| 578 | + hsync_porch0_bp - 1), |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 579 | ctl_base + VIDEO_MODE_TOTAL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 580 | } else { |
| 581 | writel(((disp_height + vsync_porch0_fp |
| 582 | + vsync_porch0_bp) << 16) |
| 583 | | (disp_width + hsync_porch0_fp |
| 584 | + hsync_porch0_bp), |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 585 | ctl_base + VIDEO_MODE_TOTAL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 586 | } |
| 587 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 588 | writel((hsync_width << 16) | 0, ctl_base + VIDEO_MODE_HSYNC); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 589 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 590 | writel(0 << 16 | 0, ctl_base + VIDEO_MODE_VSYNC); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 591 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 592 | writel(vsync_width << 16 | 0, ctl_base + VIDEO_MODE_VSYNC_VPOS); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 593 | |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 594 | /* For 8916/8939, flush the DSI timing registers */ |
Kuogee Hsieh | 861e25d | 2014-10-29 16:50:15 -0700 | [diff] [blame] | 595 | if (readl(ctl_base) >= DSI_HW_REV_103 && |
Shivaraj Shetty | 41d2d48 | 2014-11-04 16:07:32 +0530 | [diff] [blame] | 596 | mdp_get_revision() != MDP_REV_305) |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 597 | writel(0x1, ctl_base + TIMING_FLUSH); |
| 598 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 599 | writel(0x0, ctl_base + EOT_PACKET_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 600 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 601 | writel(0x00000100, ctl_base + MISR_VIDEO_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 602 | |
Shivaraj Shetty | 41d2d48 | 2014-11-04 16:07:32 +0530 | [diff] [blame] | 603 | if (mdp_get_revision() >= MDP_REV_41 || mdp_get_revision() == MDP_REV_305) { |
Padmanabhan Komanduru | 684b58f | 2015-02-11 16:22:51 +0530 | [diff] [blame] | 604 | writel(last_line_interleave_en << 31 | pulse_mode_hsa_he << 28 | |
| 605 | low_pwr_stop_mode << 16 | eof_bllp_pwr << 12 | |
| 606 | traffic_mode << 8 | dst_format << 4 | 0x0, |
| 607 | ctl_base + VIDEO_MODE_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 608 | } else { |
| 609 | writel(1 << 28 | 1 << 24 | 1 << 20 | low_pwr_stop_mode << 16 | |
| 610 | eof_bllp_pwr << 12 | traffic_mode << 8 |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 611 | | dst_format << 4 | 0x0, ctl_base + VIDEO_MODE_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 612 | } |
| 613 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 614 | writel(0x3fd08, ctl_base + HS_TIMER_CTRL); |
| 615 | writel(0x00010100, ctl_base + MISR_VIDEO_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 616 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 617 | writel(0x00010100, ctl_base + INT_CTRL); |
| 618 | writel(0x02010202, ctl_base + INT_CTRL); |
| 619 | writel(0x02030303, ctl_base + INT_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 620 | |
| 621 | writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 622 | | 0x103, ctl_base + CTRL); |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 623 | if (dsc) { |
| 624 | if (dsc->dsi_dsc_config) |
| 625 | dsc->dsi_dsc_config(pinfo->mipi.ctl_base, DSI_VIDEO_MODE, dsc); |
| 626 | } |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 627 | #endif |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 628 | |
| 629 | return status; |
| 630 | } |
| 631 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 632 | int mdss_dsi_config(struct msm_fb_panel_data *panel) |
| 633 | { |
| 634 | int ret = NO_ERROR; |
| 635 | struct msm_panel_info *pinfo; |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 636 | struct mipi_panel_info *mipi; |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 637 | struct dsc_desc *dsc = NULL; |
| 638 | struct mipi_dsi_cmd cmd; |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 639 | |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 640 | #if (DISPLAY_TYPE_MDSS == 1) |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 641 | if (!panel) |
| 642 | return ERR_INVALID_ARGS; |
| 643 | |
| 644 | pinfo = &(panel->panel_info); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 645 | mipi = &(pinfo->mipi); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 646 | |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 647 | |
| 648 | if (pinfo->compression_mode == COMPRESSION_DSC) { |
| 649 | dsc = &pinfo->dsc; |
| 650 | if (dsc) { |
| 651 | if (dsc->dsc2buf) |
| 652 | dsc->dsc2buf(pinfo); |
| 653 | } |
| 654 | } |
| 655 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 656 | dprintf(SPEW, "ctl_base=0x%08x, phy_base=0x%08x\n", mipi->ctl_base, |
| 657 | mipi->phy_base); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 658 | |
Jeevan Shriram | 0137932 | 2015-01-07 17:41:26 -0800 | [diff] [blame] | 659 | mdss_dsi_phy_init(mipi); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 660 | |
| 661 | ret = mdss_dsi_host_init(mipi, mipi->dual_dsi, |
| 662 | mipi->broadcast); |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 663 | if (ret) { |
| 664 | dprintf(CRITICAL, "dsi host init error\n"); |
| 665 | goto error; |
| 666 | } |
| 667 | |
Aravind Venkateswaran | 51e5755 | 2014-12-09 13:23:19 -0800 | [diff] [blame] | 668 | mdss_dsi_phy_contention_detection(mipi, mipi->phy_base); |
| 669 | if (mipi->dual_dsi) |
| 670 | mdss_dsi_phy_contention_detection(mipi, mipi->sphy_base); |
Xiaoming Zhou | 03fd48b | 2014-07-31 15:24:41 -0400 | [diff] [blame] | 671 | |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 672 | if (panel->pre_init_func) { |
| 673 | ret = panel->pre_init_func(); |
| 674 | if (ret) { |
| 675 | dprintf(CRITICAL, "pre_init_func error\n"); |
| 676 | goto error; |
| 677 | } |
| 678 | } |
| 679 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 680 | if (!mipi->cmds_post_tg) { |
| 681 | ret = mdss_dsi_panel_initialize(mipi, mipi->broadcast); |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 682 | if (ret) { |
| 683 | dprintf(CRITICAL, "dsi panel init error\n"); |
| 684 | goto error; |
| 685 | } |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 686 | } |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 687 | |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 688 | if (dsc) { |
| 689 | cmd.size = DCS_HDR_LEN + DSC_PPS_LEN; |
| 690 | cmd.payload = dsc->pps_buf; |
| 691 | cmd.wait = 0x10; |
| 692 | mdss_dsi_cmds_tx(mipi, &cmd, 1, mipi->broadcast); |
| 693 | } |
| 694 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 695 | if (pinfo->rotate && panel->rotate) |
| 696 | pinfo->rotate(); |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 697 | #endif |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 698 | |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 699 | error: |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 700 | return ret; |
| 701 | } |
| 702 | |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 703 | int mdss_dsi_post_on(struct msm_fb_panel_data *panel) |
| 704 | { |
| 705 | int ret = 0; |
| 706 | struct msm_panel_info *pinfo = &(panel->panel_info); |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 707 | |
| 708 | if (pinfo->mipi.cmds_post_tg) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 709 | ret = mdss_dsi_panel_initialize(&pinfo->mipi, pinfo->mipi.broadcast); |
Siddhartha Agrawal | 007ea9e | 2014-10-14 15:02:48 -0700 | [diff] [blame] | 710 | if (ret) { |
| 711 | dprintf(CRITICAL, "dsi panel init error\n"); |
| 712 | } |
| 713 | } |
| 714 | return ret; |
| 715 | } |
| 716 | |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 717 | int mdss_dsi_cmd_mode_config(struct msm_panel_info *pinfo, |
| 718 | uint16_t disp_width, |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 719 | uint16_t disp_height, |
| 720 | uint16_t img_width, |
| 721 | uint16_t img_height, |
| 722 | uint16_t dst_format, |
Xiaoming Zhou | 8d534dd | 2013-07-29 15:49:19 -0400 | [diff] [blame] | 723 | uint8_t ystride, |
| 724 | uint8_t lane_en, |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 725 | uint8_t interleav, |
| 726 | uint32_t ctl_base) |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 727 | { |
Xiaoming Zhou | 8d534dd | 2013-07-29 15:49:19 -0400 | [diff] [blame] | 728 | uint16_t dst_fmt = 0; |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 729 | struct dsc_desc *dsc = NULL; |
| 730 | unsigned int data; |
Xiaoming Zhou | 8d534dd | 2013-07-29 15:49:19 -0400 | [diff] [blame] | 731 | |
| 732 | switch (dst_format) { |
| 733 | case DSI_VIDEO_DST_FORMAT_RGB565: |
| 734 | dst_fmt = DSI_CMD_DST_FORMAT_RGB565; |
| 735 | break; |
| 736 | case DSI_VIDEO_DST_FORMAT_RGB666: |
| 737 | case DSI_VIDEO_DST_FORMAT_RGB666_LOOSE: |
| 738 | dst_fmt = DSI_CMD_DST_FORMAT_RGB666; |
| 739 | break; |
| 740 | case DSI_VIDEO_DST_FORMAT_RGB888: |
| 741 | dst_fmt = DSI_CMD_DST_FORMAT_RGB888; |
| 742 | break; |
| 743 | default: |
| 744 | dprintf(CRITICAL, "unsupported dst format\n"); |
| 745 | return ERROR; |
| 746 | } |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 747 | |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 748 | #if (DISPLAY_TYPE_MDSS == 1) |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 749 | writel(0x00000000, ctl_base + CLK_CTRL); |
| 750 | writel(0x00000000, ctl_base + CLK_CTRL); |
| 751 | writel(0x00000000, ctl_base + CLK_CTRL); |
| 752 | writel(0x00000000, ctl_base + CLK_CTRL); |
| 753 | writel(0x00000002, ctl_base + CLK_CTRL); |
| 754 | writel(0x00000006, ctl_base + CLK_CTRL); |
| 755 | writel(0x0000000e, ctl_base + CLK_CTRL); |
| 756 | writel(0x0000001e, ctl_base + CLK_CTRL); |
| 757 | writel(0x0000023f, ctl_base + CLK_CTRL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 758 | |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 759 | writel(0, ctl_base + CTRL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 760 | |
Padmanabhan Komanduru | 2f8e0bc | 2014-11-27 18:25:36 +0530 | [diff] [blame] | 761 | writel(0x03f03fe0, ctl_base + ERR_INT_MASK0); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 762 | |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 763 | writel(0x02020202, ctl_base + INT_CTRL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 764 | |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 765 | writel(dst_fmt, ctl_base + COMMAND_MODE_MDP_CTRL); |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 766 | |
| 767 | if (pinfo->compression_mode == COMPRESSION_DSC) |
| 768 | dsc = &pinfo->dsc; |
| 769 | |
| 770 | if (dsc) { |
| 771 | data = dsc->bytes_per_pkt; |
| 772 | if (pinfo->mipi.insert_dcs_cmd) |
| 773 | data++; |
| 774 | data <<= 16; |
| 775 | data |= 0x039; |
| 776 | writel(data, ctl_base + COMMAND_MODE_MDP_STREAM0_CTRL); |
| 777 | writel(data, ctl_base + COMMAND_MODE_MDP_STREAM1_CTRL); |
| 778 | data = dsc->pic_height << 16; |
| 779 | data |= dsc->pclk_per_line; |
| 780 | writel(data, ctl_base + COMMAND_MODE_MDP_STREAM0_TOTAL); |
| 781 | writel(data, ctl_base + COMMAND_MODE_MDP_STREAM1_TOTAL); |
| 782 | |
| 783 | if (dsc->dsi_dsc_config) |
Kuogee Hsieh | 6a8802f | 2015-09-01 09:11:40 -0700 | [diff] [blame] | 784 | dsc->dsi_dsc_config(pinfo->mipi.ctl_base, DSI_CMD_MODE, dsc); |
Kuogee Hsieh | d58c809 | 2015-07-07 10:31:34 -0700 | [diff] [blame] | 785 | } else { |
| 786 | |
| 787 | writel((img_width * ystride + 1) << 16 | 0x0039, |
| 788 | ctl_base + COMMAND_MODE_MDP_STREAM0_CTRL); |
| 789 | writel((img_width * ystride + 1) << 16 | 0x0039, |
| 790 | ctl_base + COMMAND_MODE_MDP_STREAM1_CTRL); |
| 791 | writel(img_height << 16 | img_width, |
| 792 | ctl_base + COMMAND_MODE_MDP_STREAM0_TOTAL); |
| 793 | writel(img_height << 16 | img_width, |
| 794 | ctl_base + COMMAND_MODE_MDP_STREAM1_TOTAL); |
| 795 | } |
| 796 | |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 797 | writel(0x13c2c, ctl_base + COMMAND_MODE_MDP_DCS_CMD_CTRL); |
Xiaoming Zhou | 8d534dd | 2013-07-29 15:49:19 -0400 | [diff] [blame] | 798 | writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 | 0x105, |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 799 | ctl_base + CTRL); |
Padmanabhan Komanduru | 7860be5 | 2014-03-18 19:07:36 +0530 | [diff] [blame] | 800 | writel(0x14000000, ctl_base + COMMAND_MODE_DMA_CTRL); |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 801 | writel(0x10000000, ctl_base + MISR_CMD_CTRL); |
Xiaoming Zhou | a046933 | 2014-03-04 18:34:24 -0500 | [diff] [blame] | 802 | writel(0x1, ctl_base + EOT_PACKET_CTRL); |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 803 | #endif |
Xiaoming Zhou | 8d534dd | 2013-07-29 15:49:19 -0400 | [diff] [blame] | 804 | return 0; |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 805 | } |
| 806 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 807 | int mipi_dsi_on(struct msm_panel_info *pinfo) |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 808 | { |
| 809 | int ret = NO_ERROR; |
| 810 | unsigned long ReadValue; |
| 811 | unsigned long count = 0; |
| 812 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 813 | ReadValue = readl(pinfo->mipi.ctl_base + INT_CTRL) & 0x00010000; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 814 | |
| 815 | mdelay(10); |
| 816 | |
| 817 | while (ReadValue != 0x00010000) { |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 818 | ReadValue = readl(pinfo->mipi.ctl_base + INT_CTRL) & 0x00010000; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 819 | count++; |
| 820 | if (count > 0xffff) { |
| 821 | dprintf(CRITICAL, "Video lane test failed\n"); |
| 822 | return ERROR; |
| 823 | } |
| 824 | } |
| 825 | |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 826 | dprintf(INFO, "Video lane tested successfully\n"); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 827 | return ret; |
| 828 | } |
| 829 | |
Siddhartha Agrawal | 24d81b5 | 2013-07-01 11:13:32 -0700 | [diff] [blame] | 830 | int mipi_dsi_off(struct msm_panel_info *pinfo) |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 831 | { |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 832 | if(!target_cont_splash_screen()) |
| 833 | { |
Padmanabhan Komanduru | f8986be | 2014-11-04 15:57:19 +0530 | [diff] [blame] | 834 | mdss_dsi_panel_shutdown(pinfo); |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 835 | writel(0, pinfo->mipi.ctl_base + CLK_CTRL); |
| 836 | writel(0x1F1, pinfo->mipi.ctl_base + CTRL); |
Siddhartha Agrawal | e0033a1 | 2013-02-23 15:37:42 -0800 | [diff] [blame] | 837 | } |
| 838 | |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 839 | writel(0x1115501, pinfo->mipi.ctl_base + INT_CTRL); |
feifanz | 87f1985 | 2015-09-25 11:54:26 +0800 | [diff] [blame] | 840 | if (pinfo->mipi.dual_dsi) |
Aravind Venkateswaran | fec354c | 2014-12-04 18:10:14 -0800 | [diff] [blame] | 841 | writel(0x1115501, pinfo->mipi.sctl_base + INT_CTRL); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 842 | |
| 843 | return NO_ERROR; |
| 844 | } |
Channagoud Kadabi | 10189fd | 2012-05-25 13:33:39 +0530 | [diff] [blame] | 845 | |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 846 | #if (DISPLAY_TYPE_MDSS == 0) |
| 847 | static int dsi_cmd_dma_trigger_for_panel() |
| 848 | { |
| 849 | unsigned long ReadValue; |
| 850 | unsigned long count = 0; |
| 851 | int status = 0; |
| 852 | |
| 853 | writel(0x03030303, DSI_INT_CTRL); |
| 854 | writel(0x1, DSI_CMD_MODE_DMA_SW_TRIGGER); |
| 855 | dsb(); |
| 856 | ReadValue = readl(DSI_INT_CTRL) & 0x00000001; |
| 857 | while (ReadValue != 0x00000001) { |
| 858 | ReadValue = readl(DSI_INT_CTRL) & 0x00000001; |
| 859 | count++; |
| 860 | if (count > 0xffff) { |
| 861 | status = FAIL; |
| 862 | dprintf(CRITICAL, |
| 863 | "Panel CMD: command mode dma test failed\n"); |
| 864 | return status; |
| 865 | } |
| 866 | } |
| 867 | |
| 868 | writel((readl(DSI_INT_CTRL) | 0x01000001), DSI_INT_CTRL); |
| 869 | dprintf(SPEW, "Panel CMD: command mode dma tested successfully\n"); |
| 870 | return status; |
| 871 | } |
| 872 | |
| 873 | int mipi_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count) |
| 874 | { |
| 875 | int ret = 0; |
| 876 | struct mipi_dsi_cmd *cm; |
| 877 | int i = 0; |
| 878 | char pload[256]; |
| 879 | uint32_t off; |
| 880 | |
| 881 | /* Align pload at 8 byte boundry */ |
| 882 | off = pload; |
| 883 | off &= 0x07; |
| 884 | if (off) |
| 885 | off = 8 - off; |
| 886 | off += pload; |
| 887 | |
| 888 | cm = cmds; |
| 889 | for (i = 0; i < count; i++) { |
| 890 | /* Wait for VIDEO_MODE_DONE */ |
| 891 | ret = mdss_dsi_wait4_video_done(); |
| 892 | if (ret) |
| 893 | goto mipi_cmds_error; |
| 894 | |
| 895 | memcpy((void *)off, (cm->payload), cm->size); |
Matthew Qin | 81933ce | 2015-02-03 17:58:52 +0800 | [diff] [blame] | 896 | arch_clean_invalidate_cache_range((addr_t)(off), size); |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 897 | writel(off, DSI_DMA_CMD_OFFSET); |
| 898 | writel(cm->size, DSI_DMA_CMD_LENGTH); // reg 0x48 for this build |
| 899 | dsb(); |
| 900 | ret += dsi_cmd_dma_trigger_for_panel(); |
| 901 | dsb(); |
| 902 | if (cm->wait) |
| 903 | mdelay(cm->wait); |
| 904 | else |
| 905 | udelay(80); |
| 906 | cm++; |
| 907 | } |
| 908 | mipi_cmds_error: |
| 909 | return ret; |
| 910 | } |
| 911 | |
| 912 | /* |
| 913 | * mipi_dsi_cmd_rx: can receive at most 16 bytes |
| 914 | * per transaction since it only have 4 32bits reigsters |
| 915 | * to hold data. |
| 916 | * therefore Maximum Return Packet Size need to be set to 16. |
| 917 | * any return data more than MRPS need to be break down |
| 918 | * to multiple transactions. |
| 919 | */ |
| 920 | int mipi_dsi_cmds_rx(char **rp, int len) |
| 921 | { |
| 922 | uint32_t *lp, data; |
| 923 | char *dp; |
| 924 | int i, off, cnt; |
| 925 | int rlen, res; |
| 926 | |
| 927 | if (len <= 2) |
| 928 | rlen = 4; /* short read */ |
| 929 | else |
| 930 | rlen = MIPI_DSI_MRPS + 6; /* 4 bytes header + 2 bytes crc */ |
| 931 | |
| 932 | if (rlen > MIPI_DSI_REG_LEN) { |
| 933 | return 0; |
| 934 | } |
| 935 | |
| 936 | res = rlen & 0x03; |
| 937 | |
| 938 | rlen += res; /* 4 byte align */ |
| 939 | lp = (uint32_t *) (*rp); |
| 940 | |
| 941 | cnt = rlen; |
| 942 | cnt += 3; |
| 943 | cnt >>= 2; |
| 944 | |
| 945 | if (cnt > 4) |
| 946 | cnt = 4; /* 4 x 32 bits registers only */ |
| 947 | |
| 948 | off = 0x068; /* DSI_RDBK_DATA0 */ |
| 949 | off += ((cnt - 1) * 4); |
| 950 | |
| 951 | for (i = 0; i < cnt; i++) { |
| 952 | data = (uint32_t) readl(MIPI_DSI_BASE + off); |
| 953 | *lp++ = ntohl(data); /* to network byte order */ |
| 954 | off -= 4; |
| 955 | } |
| 956 | |
| 957 | if (len > 2) { |
| 958 | /*First 4 bytes + paded bytes will be header next len bytes would be payload */ |
| 959 | for (i = 0; i < len; i++) { |
| 960 | dp = *rp; |
| 961 | dp[i] = dp[4 + res + i]; |
| 962 | } |
| 963 | } |
| 964 | |
| 965 | return len; |
| 966 | } |
| 967 | |
| 968 | static int mipi_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo) |
| 969 | { |
| 970 | uint8_t DMA_STREAM1 = 0; // for mdp display processor path |
| 971 | uint8_t EMBED_MODE1 = 1; // from frame buffer |
| 972 | uint8_t POWER_MODE2 = 1; // from frame buffer |
| 973 | uint8_t PACK_TYPE1; // long packet |
| 974 | uint8_t VC1 = 0; |
| 975 | uint8_t DT1 = 0; // non embedded mode |
| 976 | uint8_t WC1 = 0; // for non embedded mode only |
| 977 | int status = 0; |
| 978 | uint8_t DLNx_EN; |
| 979 | |
| 980 | switch (pinfo->num_of_lanes) { |
| 981 | default: |
| 982 | case 1: |
| 983 | DLNx_EN = 1; // 1 lane |
| 984 | break; |
| 985 | case 2: |
| 986 | DLNx_EN = 3; // 2 lane |
| 987 | break; |
| 988 | case 3: |
| 989 | DLNx_EN = 7; // 3 lane |
| 990 | break; |
| 991 | case 4: |
| 992 | DLNx_EN = 0x0F; /* 4 lanes */ |
| 993 | break; |
| 994 | } |
| 995 | |
| 996 | PACK_TYPE1 = pinfo->pack; |
| 997 | |
| 998 | writel(0x0001, DSI_SOFT_RESET); |
| 999 | writel(0x0000, DSI_SOFT_RESET); |
| 1000 | |
| 1001 | writel((0 << 16) | 0x3f, DSI_CLK_CTRL); /* Turn on all DSI Clks */ |
| 1002 | writel(DMA_STREAM1 << 8 | 0x04, DSI_TRIG_CTRL); // reg 0x80 dma trigger: sw |
| 1003 | // trigger 0x4; dma stream1 |
| 1004 | |
| 1005 | writel(0 << 30 | DLNx_EN << 4 | 0x105, DSI_CTRL); // reg 0x00 for this |
| 1006 | // build |
| 1007 | writel(EMBED_MODE1 << 28 | POWER_MODE2 << 26 |
| 1008 | | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1, |
| 1009 | DSI_COMMAND_MODE_DMA_CTRL); |
| 1010 | |
| 1011 | if (pinfo->panel_on_cmds) |
| 1012 | status = mipi_dsi_cmds_tx(pinfo->panel_on_cmds, |
| 1013 | pinfo->num_of_panel_on_cmds); |
| 1014 | |
| 1015 | return status; |
| 1016 | } |
| 1017 | #endif |
| 1018 | |
| 1019 | void mipi_dsi_shutdown(void) |
| 1020 | { |
| 1021 | #if (DISPLAY_TYPE_MDSS == 0) |
| 1022 | if(!target_cont_splash_screen()) |
| 1023 | { |
| 1024 | mdp_shutdown(); |
| 1025 | writel(0x01010101, DSI_INT_CTRL); |
| 1026 | writel(0x13FF3BFF, DSI_ERR_INT_MASK0); |
| 1027 | |
| 1028 | writel(0, DSI_CLK_CTRL); |
| 1029 | writel(0, DSI_CTRL); |
| 1030 | writel(0, DSIPHY_PLL_CTRL(0)); |
| 1031 | } |
| 1032 | else |
| 1033 | { |
| 1034 | /* To keep the splash screen displayed till kernel driver takes |
| 1035 | control, do not turn off the video mode engine and clocks. |
| 1036 | Only disabling the MIPI DSI IRQs */ |
| 1037 | writel(0x01010101, DSI_INT_CTRL); |
| 1038 | writel(0x13FF3BFF, DSI_ERR_INT_MASK0); |
| 1039 | } |
| 1040 | #endif |
| 1041 | } |
| 1042 | |
Channagoud Kadabi | 10189fd | 2012-05-25 13:33:39 +0530 | [diff] [blame] | 1043 | int mipi_cmd_trigger() |
| 1044 | { |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 1045 | #if (DISPLAY_TYPE_MDSS == 0) |
Channagoud Kadabi | 10189fd | 2012-05-25 13:33:39 +0530 | [diff] [blame] | 1046 | writel(0x1, DSI_CMD_MODE_MDP_SW_TRIGGER); |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 1047 | #endif |
Channagoud Kadabi | 10189fd | 2012-05-25 13:33:39 +0530 | [diff] [blame] | 1048 | return NO_ERROR; |
| 1049 | } |
Aravind Venkateswaran | ce4dd7f | 2014-12-04 16:54:26 -0800 | [diff] [blame] | 1050 | |
| 1051 | int mipi_config(struct msm_fb_panel_data *panel) |
| 1052 | { |
| 1053 | int ret = NO_ERROR; |
| 1054 | #if (DISPLAY_TYPE_MDSS == 0) |
| 1055 | struct msm_panel_info *pinfo; |
| 1056 | struct mipi_dsi_panel_config mipi_pinfo; |
| 1057 | |
| 1058 | if (!panel) |
| 1059 | return ERR_INVALID_ARGS; |
| 1060 | |
| 1061 | pinfo = &(panel->panel_info); |
| 1062 | mipi_pinfo.mode = pinfo->mipi.mode; |
| 1063 | mipi_pinfo.num_of_lanes = pinfo->mipi.num_of_lanes; |
| 1064 | mipi_pinfo.dsi_phy_config = pinfo->mipi.dsi_phy_db; |
| 1065 | mipi_pinfo.panel_on_cmds = pinfo->mipi.panel_on_cmds; |
| 1066 | mipi_pinfo.num_of_panel_on_cmds = pinfo->mipi.num_of_panel_on_cmds; |
| 1067 | mipi_pinfo.lane_swap = pinfo->mipi.lane_swap; |
| 1068 | mipi_pinfo.pack = 1; |
| 1069 | |
| 1070 | /* Enable MMSS_AHB_ARB_MATER_PORT_E for |
| 1071 | arbiter master0 and master 1 request */ |
| 1072 | #if (!DISPLAY_MIPI_PANEL_RENESAS && !DISPLAY_TYPE_DSI6G && !DISPLAY_TYPE_8610) |
| 1073 | writel(0x00001800, MMSS_SFPB_GPREG); |
| 1074 | #endif |
| 1075 | |
| 1076 | mipi_dsi_phy_init(&mipi_pinfo); |
| 1077 | |
| 1078 | ret += mipi_dsi_panel_initialize(&mipi_pinfo); |
| 1079 | |
| 1080 | if (pinfo->rotate && panel->rotate) |
| 1081 | pinfo->rotate(); |
| 1082 | #endif |
| 1083 | return ret; |
| 1084 | } |