Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved. |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 2 | * |
| 3 | * Redistribution and use in source and binary forms, with or without |
| 4 | * modification, are permitted provided that the following conditions are |
| 5 | * met: |
| 6 | * * Redistributions of source code must retain the above copyright |
| 7 | * notice, this list of conditions and the following disclaimer. |
| 8 | * * Redistributions in binary form must reproduce the above |
| 9 | * copyright notice, this list of conditions and the following |
| 10 | * disclaimer in the documentation and/or other materials provided |
| 11 | * with the distribution. |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 12 | * * Neither the name of The Linux Foundation nor the names of its |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 13 | * contributors may be used to endorse or promote products derived |
| 14 | * from this software without specific prior written permission. |
| 15 | * |
| 16 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED |
| 17 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| 18 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT |
| 19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS |
| 20 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 21 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 22 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR |
| 23 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, |
| 24 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE |
| 25 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN |
| 26 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #include <reg.h> |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 31 | #include <endian.h> |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 32 | #include <mipi_dsi.h> |
| 33 | #include <dev/fbcon.h> |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 34 | #include <stdlib.h> |
Greg Grisco | 1073a5e | 2011-07-28 18:59:18 -0700 | [diff] [blame] | 35 | #include <string.h> |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 36 | #include <debug.h> |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 37 | #include <target/display.h> |
| 38 | #include <platform/iomap.h> |
| 39 | #include <platform/clock.h> |
Greg Grisco | 1073a5e | 2011-07-28 18:59:18 -0700 | [diff] [blame] | 40 | #include <platform/timer.h> |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 41 | #include <err.h> |
| 42 | #include <msm_panel.h> |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 43 | |
| 44 | extern void mdp_disable(void); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 45 | extern int mipi_dsi_cmd_config(struct fbcon_config mipi_fb_cfg, |
| 46 | unsigned short num_of_lanes); |
Kinson Chik | fe93103 | 2011-07-21 10:01:34 -0700 | [diff] [blame] | 47 | extern void mdp_shutdown(void); |
| 48 | extern void mdp_start_dma(void); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 49 | |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 50 | #if (DISPLAY_TYPE_MDSS == 0) |
| 51 | #define MIPI_DSI0_BASE MIPI_DSI_BASE |
| 52 | #define MIPI_DSI1_BASE MIPI_DSI_BASE |
| 53 | #endif |
| 54 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 55 | static struct fbcon_config mipi_fb_cfg = { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 56 | .height = 0, |
| 57 | .width = 0, |
| 58 | .stride = 0, |
| 59 | .format = 0, |
| 60 | .bpp = 0, |
| 61 | .update_start = NULL, |
| 62 | .update_done = NULL, |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 63 | }; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 64 | |
| 65 | static int cmd_mode_status = 0; |
Greg Grisco | d625055 | 2011-06-29 14:40:23 -0700 | [diff] [blame] | 66 | void secure_writel(uint32_t, uint32_t); |
| 67 | uint32_t secure_readl(uint32_t); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 68 | |
Shivaraj Shetty | 6460403 | 2013-11-14 16:44:10 +0530 | [diff] [blame] | 69 | static uint32_t response_value = 0; |
| 70 | |
| 71 | uint32_t mdss_dsi_read_panel_signature(uint32_t panel_signature) |
| 72 | { |
| 73 | uint32_t rec_buf[1]; |
| 74 | uint32_t *lp = rec_buf, data; |
| 75 | int ret = response_value; |
| 76 | |
| 77 | #if (DISPLAY_TYPE_MDSS == 1) |
| 78 | if (ret && ret != panel_signature) |
| 79 | goto exit_read_signature; |
| 80 | |
| 81 | ret = mipi_dsi_cmds_tx(&read_ddb_start_cmd, 1); |
| 82 | if (ret) |
| 83 | goto exit_read_signature; |
| 84 | if (!mdss_dsi_cmds_rx(&lp, 1, 1)) |
| 85 | goto exit_read_signature; |
| 86 | |
| 87 | data = ntohl(*lp); |
| 88 | data = data >> 8; |
| 89 | response_value = data; |
| 90 | if (response_value != panel_signature) |
| 91 | ret = response_value; |
| 92 | |
| 93 | exit_read_signature: |
| 94 | /* Keep the non detectable panel at the end and set panel signature 0xFFFF */ |
| 95 | if (panel_signature == 0xFFFF) |
| 96 | ret = 0; |
| 97 | #endif |
| 98 | return ret; |
| 99 | } |
| 100 | |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 101 | int mdss_dual_dsi_cmd_dma_trigger_for_panel() |
| 102 | { |
| 103 | uint32_t ReadValue; |
| 104 | uint32_t count = 0; |
| 105 | int status = 0; |
| 106 | |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 107 | #if (DISPLAY_TYPE_MDSS == 1) |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 108 | writel(0x03030303, MIPI_DSI0_BASE + INT_CTRL); |
| 109 | writel(0x1, MIPI_DSI0_BASE + CMD_MODE_DMA_SW_TRIGGER); |
| 110 | dsb(); |
| 111 | |
| 112 | writel(0x03030303, MIPI_DSI1_BASE + INT_CTRL); |
| 113 | writel(0x1, MIPI_DSI1_BASE + CMD_MODE_DMA_SW_TRIGGER); |
| 114 | dsb(); |
| 115 | |
| 116 | ReadValue = readl(MIPI_DSI1_BASE + INT_CTRL) & 0x00000001; |
| 117 | while (ReadValue != 0x00000001) { |
| 118 | ReadValue = readl(MIPI_DSI1_BASE + INT_CTRL) & 0x00000001; |
| 119 | count++; |
| 120 | if (count > 0xffff) { |
| 121 | status = FAIL; |
| 122 | dprintf(CRITICAL, |
| 123 | "Panel CMD: command mode dma test failed\n"); |
| 124 | return status; |
| 125 | } |
| 126 | } |
| 127 | |
| 128 | writel((readl(MIPI_DSI1_BASE + INT_CTRL) | 0x01000001), |
| 129 | MIPI_DSI1_BASE + INT_CTRL); |
| 130 | dprintf(SPEW, "Panel CMD: command mode dma tested successfully\n"); |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 131 | #endif |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 132 | return status; |
| 133 | } |
| 134 | |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 135 | int dsi_cmd_dma_trigger_for_panel() |
| 136 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 137 | unsigned long ReadValue; |
| 138 | unsigned long count = 0; |
| 139 | int status = 0; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 140 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 141 | writel(0x03030303, DSI_INT_CTRL); |
| 142 | writel(0x1, DSI_CMD_MODE_DMA_SW_TRIGGER); |
| 143 | dsb(); |
| 144 | ReadValue = readl(DSI_INT_CTRL) & 0x00000001; |
| 145 | while (ReadValue != 0x00000001) { |
| 146 | ReadValue = readl(DSI_INT_CTRL) & 0x00000001; |
| 147 | count++; |
| 148 | if (count > 0xffff) { |
| 149 | status = FAIL; |
| 150 | dprintf(CRITICAL, |
| 151 | "Panel CMD: command mode dma test failed\n"); |
| 152 | return status; |
| 153 | } |
| 154 | } |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 155 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 156 | writel((readl(DSI_INT_CTRL) | 0x01000001), DSI_INT_CTRL); |
| 157 | dprintf(SPEW, "Panel CMD: command mode dma tested successfully\n"); |
| 158 | return status; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 159 | } |
| 160 | |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 161 | int mdss_dual_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count) |
| 162 | { |
| 163 | int ret = 0; |
| 164 | struct mipi_dsi_cmd *cm; |
| 165 | int i = 0; |
| 166 | char pload[256]; |
| 167 | uint32_t off; |
| 168 | |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 169 | #if (DISPLAY_TYPE_MDSS == 1) |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 170 | /* Align pload at 8 byte boundry */ |
| 171 | off = pload; |
| 172 | off &= 0x07; |
| 173 | if (off) |
| 174 | off = 8 - off; |
| 175 | off += pload; |
| 176 | |
| 177 | cm = cmds; |
| 178 | for (i = 0; i < count; i++) { |
| 179 | memcpy((void *)off, (cm->payload), cm->size); |
| 180 | writel(off, MIPI_DSI0_BASE + DMA_CMD_OFFSET); |
| 181 | writel(cm->size, MIPI_DSI0_BASE + DMA_CMD_LENGTH); // reg 0x48 for this build |
| 182 | writel(off, MIPI_DSI1_BASE + DMA_CMD_OFFSET); |
| 183 | writel(cm->size, MIPI_DSI1_BASE + DMA_CMD_LENGTH); // reg 0x48 for this build |
| 184 | dsb(); |
| 185 | ret += mdss_dual_dsi_cmd_dma_trigger_for_panel(); |
Dhaval Patel | 607a624 | 2013-10-29 12:37:24 -0700 | [diff] [blame] | 186 | if (cm->wait) |
| 187 | mdelay(cm->wait); |
| 188 | else |
| 189 | udelay(80); |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 190 | cm++; |
| 191 | } |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 192 | #endif |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 193 | return ret; |
| 194 | } |
| 195 | |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 196 | int mdss_dsi_cmds_rx(uint32_t **rp, int rp_len, int rdbk_len) |
| 197 | { |
| 198 | uint32_t *lp, data; |
| 199 | char *dp; |
| 200 | int i, off; |
| 201 | int rlen, res; |
| 202 | |
| 203 | if (rdbk_len > rp_len) { |
| 204 | return 0; |
| 205 | } |
| 206 | |
| 207 | if (rdbk_len <= 2) |
| 208 | rlen = 4; /* short read */ |
| 209 | else |
| 210 | rlen = MIPI_DSI_MRPS + 6; /* 4 bytes header + 2 bytes crc */ |
| 211 | |
| 212 | if (rlen > MIPI_DSI_REG_LEN) { |
| 213 | return 0; |
| 214 | } |
| 215 | |
| 216 | res = rlen & 0x03; |
| 217 | |
| 218 | rlen += res; /* 4 byte align */ |
| 219 | lp = *rp; |
| 220 | |
| 221 | rlen += 3; |
| 222 | rlen >>= 2; |
| 223 | |
| 224 | if (rlen > 4) |
| 225 | rlen = 4; /* 4 x 32 bits registers only */ |
| 226 | |
Shivaraj Shetty | 3c77da6 | 2013-12-09 15:58:16 +0530 | [diff] [blame] | 227 | off = RDBK_DATA0; |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 228 | off += ((rlen - 1) * 4); |
| 229 | |
| 230 | for (i = 0; i < rlen; i++) { |
| 231 | data = readl(MIPI_DSI_BASE + off); |
| 232 | *lp = ntohl(data); /* to network byte order */ |
| 233 | lp++; |
| 234 | |
| 235 | off -= 4; |
| 236 | } |
| 237 | |
| 238 | if (rdbk_len > 2) { |
| 239 | /*First 4 bytes + paded bytes will be header next len bytes would be payload */ |
| 240 | for (i = 0; i < rdbk_len; i++) { |
| 241 | dp = *rp; |
| 242 | dp[i] = dp[(res + i) >> 2]; |
| 243 | } |
| 244 | } |
| 245 | return rdbk_len; |
| 246 | } |
| 247 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 248 | int mipi_dsi_cmds_tx(struct mipi_dsi_cmd *cmds, int count) |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 249 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 250 | int ret = 0; |
| 251 | struct mipi_dsi_cmd *cm; |
| 252 | int i = 0; |
| 253 | char pload[256]; |
| 254 | uint32_t off; |
Deepa Dinamani | a080a40 | 2011-11-05 18:59:26 -0700 | [diff] [blame] | 255 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 256 | /* Align pload at 8 byte boundry */ |
| 257 | off = pload; |
| 258 | off &= 0x07; |
| 259 | if (off) |
| 260 | off = 8 - off; |
| 261 | off += pload; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 262 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 263 | cm = cmds; |
| 264 | for (i = 0; i < count; i++) { |
| 265 | memcpy((void *)off, (cm->payload), cm->size); |
| 266 | writel(off, DSI_DMA_CMD_OFFSET); |
| 267 | writel(cm->size, DSI_DMA_CMD_LENGTH); // reg 0x48 for this build |
| 268 | dsb(); |
| 269 | ret += dsi_cmd_dma_trigger_for_panel(); |
Sangani Suryanarayana Raju | 769f9ac | 2013-04-30 19:05:06 +0530 | [diff] [blame] | 270 | dsb(); |
| 271 | if (cm->wait) |
| 272 | mdelay(cm->wait); |
| 273 | else |
| 274 | udelay(80); |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 275 | cm++; |
| 276 | } |
| 277 | return ret; |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 278 | } |
| 279 | |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 280 | /* |
| 281 | * mipi_dsi_cmd_rx: can receive at most 16 bytes |
| 282 | * per transaction since it only have 4 32bits reigsters |
| 283 | * to hold data. |
| 284 | * therefore Maximum Return Packet Size need to be set to 16. |
| 285 | * any return data more than MRPS need to be break down |
| 286 | * to multiple transactions. |
| 287 | */ |
| 288 | int mipi_dsi_cmds_rx(char **rp, int len) |
| 289 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 290 | uint32_t *lp, data; |
| 291 | char *dp; |
| 292 | int i, off, cnt; |
| 293 | int rlen, res; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 294 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 295 | if (len <= 2) |
| 296 | rlen = 4; /* short read */ |
| 297 | else |
| 298 | rlen = MIPI_DSI_MRPS + 6; /* 4 bytes header + 2 bytes crc */ |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 299 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 300 | if (rlen > MIPI_DSI_REG_LEN) { |
| 301 | return 0; |
| 302 | } |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 303 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 304 | res = rlen & 0x03; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 305 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 306 | rlen += res; /* 4 byte align */ |
| 307 | lp = (uint32_t *) (*rp); |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 308 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 309 | cnt = rlen; |
| 310 | cnt += 3; |
| 311 | cnt >>= 2; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 312 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 313 | if (cnt > 4) |
| 314 | cnt = 4; /* 4 x 32 bits registers only */ |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 315 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 316 | off = 0x068; /* DSI_RDBK_DATA0 */ |
| 317 | off += ((cnt - 1) * 4); |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 318 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 319 | for (i = 0; i < cnt; i++) { |
| 320 | data = (uint32_t) readl(MIPI_DSI_BASE + off); |
| 321 | *lp++ = ntohl(data); /* to network byte order */ |
| 322 | off -= 4; |
| 323 | } |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 324 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 325 | if (len > 2) { |
| 326 | /*First 4 bytes + paded bytes will be header next len bytes would be payload */ |
| 327 | for (i = 0; i < len; i++) { |
| 328 | dp = *rp; |
| 329 | dp[i] = dp[4 + res + i]; |
| 330 | } |
| 331 | } |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 332 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 333 | return len; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 334 | } |
| 335 | |
| 336 | static int mipi_dsi_cmd_bta_sw_trigger(void) |
| 337 | { |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 338 | uint32_t data; |
| 339 | int cnt = 0; |
| 340 | int err = 0; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 341 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 342 | writel(0x01, MIPI_DSI_BASE + 0x094); /* trigger */ |
| 343 | while (cnt < 10000) { |
| 344 | data = readl(MIPI_DSI_BASE + 0x0004); /*DSI_STATUS */ |
| 345 | if ((data & 0x0010) == 0) |
| 346 | break; |
| 347 | cnt++; |
| 348 | } |
| 349 | if (cnt == 10000) |
| 350 | err = 1; |
| 351 | return err; |
Shashank Mittal | cbd271d | 2011-01-14 15:18:33 -0800 | [diff] [blame] | 352 | } |
| 353 | |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 354 | int mdss_dsi_host_init(struct mipi_dsi_panel_config *pinfo, uint32_t |
Dhaval Patel | 9207dec | 2014-04-16 10:45:32 -0700 | [diff] [blame] | 355 | dual_dsi, uint32_t broadcast) |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 356 | { |
| 357 | uint8_t DMA_STREAM1 = 0; // for mdp display processor path |
| 358 | uint8_t EMBED_MODE1 = 1; // from frame buffer |
| 359 | uint8_t POWER_MODE2 = 1; // from frame buffer |
| 360 | uint8_t PACK_TYPE1; // long packet |
| 361 | uint8_t VC1 = 0; |
| 362 | uint8_t DT1 = 0; // non embedded mode |
| 363 | uint8_t WC1 = 0; // for non embedded mode only |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 364 | uint8_t DLNx_EN; |
Siddhartha Agrawal | 2679a82 | 2013-05-31 19:15:12 -0700 | [diff] [blame] | 365 | uint8_t lane_swap = 0; |
Siddhartha Agrawal | b6c861f | 2013-05-31 19:36:44 -0700 | [diff] [blame] | 366 | uint32_t timing_ctl = 0; |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 367 | uint32_t lane_swap_dsi1 = 0; |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 368 | |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 369 | #if (DISPLAY_TYPE_MDSS == 1) |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 370 | switch (pinfo->num_of_lanes) { |
| 371 | default: |
| 372 | case 1: |
| 373 | DLNx_EN = 1; // 1 lane |
| 374 | break; |
| 375 | case 2: |
| 376 | DLNx_EN = 3; // 2 lane |
| 377 | break; |
| 378 | case 3: |
| 379 | DLNx_EN = 7; // 3 lane |
| 380 | break; |
| 381 | case 4: |
| 382 | DLNx_EN = 0x0F; /* 4 lanes */ |
| 383 | break; |
| 384 | } |
| 385 | |
| 386 | PACK_TYPE1 = pinfo->pack; |
Siddhartha Agrawal | 2679a82 | 2013-05-31 19:15:12 -0700 | [diff] [blame] | 387 | lane_swap = pinfo->lane_swap; |
Siddhartha Agrawal | b6c861f | 2013-05-31 19:36:44 -0700 | [diff] [blame] | 388 | timing_ctl = ((pinfo->t_clk_post << 8) | pinfo->t_clk_pre); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 389 | |
Dhaval Patel | 9207dec | 2014-04-16 10:45:32 -0700 | [diff] [blame] | 390 | if (dual_dsi) { |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 391 | writel(0x0001, MIPI_DSI1_BASE + SOFT_RESET); |
| 392 | writel(0x0000, MIPI_DSI1_BASE + SOFT_RESET); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 393 | |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 394 | writel((0 << 16) | 0x3f, MIPI_DSI1_BASE + CLK_CTRL); /* Turn on all DSI Clks */ |
| 395 | writel(DMA_STREAM1 << 8 | 0x04, MIPI_DSI1_BASE + TRIG_CTRL); // reg 0x80 dma trigger: sw |
| 396 | // trigger 0x4; dma stream1 |
| 397 | |
| 398 | writel(0 << 30 | DLNx_EN << 4 | 0x105, MIPI_DSI1_BASE + CTRL); // reg 0x00 for this |
| 399 | // build |
| 400 | writel(broadcast << 31 | EMBED_MODE1 << 28 | POWER_MODE2 << 26 |
| 401 | | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1, |
| 402 | MIPI_DSI1_BASE + COMMAND_MODE_DMA_CTRL); |
Siddhartha Agrawal | 2679a82 | 2013-05-31 19:15:12 -0700 | [diff] [blame] | 403 | |
Vineet Bajaj | 2f08a36 | 2014-07-24 20:50:42 +0530 | [diff] [blame] | 404 | if (readl(MIPI_DSI_BASE) == DSI_HW_REV_103_1) /*for 8939 hw dsi1 has Lane_map as 3210*/ |
| 405 | lane_swap_dsi1 = 0x7; |
| 406 | else |
| 407 | lane_swap_dsi1 = lane_swap; |
| 408 | writel(lane_swap_dsi1, MIPI_DSI1_BASE + LANE_SWAP_CTL); |
Siddhartha Agrawal | b6c861f | 2013-05-31 19:36:44 -0700 | [diff] [blame] | 409 | writel(timing_ctl, MIPI_DSI1_BASE + TIMING_CTL); |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 410 | } |
| 411 | |
| 412 | writel(0x0001, MIPI_DSI0_BASE + SOFT_RESET); |
| 413 | writel(0x0000, MIPI_DSI0_BASE + SOFT_RESET); |
| 414 | |
| 415 | writel((0 << 16) | 0x3f, MIPI_DSI0_BASE + CLK_CTRL); /* Turn on all DSI Clks */ |
| 416 | writel(DMA_STREAM1 << 8 | 0x04, MIPI_DSI0_BASE + TRIG_CTRL); // reg 0x80 dma trigger: sw |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 417 | // trigger 0x4; dma stream1 |
| 418 | |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 419 | writel(0 << 30 | DLNx_EN << 4 | 0x105, MIPI_DSI0_BASE + CTRL); // reg 0x00 for this |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 420 | // build |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 421 | writel(broadcast << 31 | EMBED_MODE1 << 28 | POWER_MODE2 << 26 |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 422 | | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1, |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 423 | MIPI_DSI0_BASE + COMMAND_MODE_DMA_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 424 | |
Siddhartha Agrawal | 2679a82 | 2013-05-31 19:15:12 -0700 | [diff] [blame] | 425 | writel(lane_swap, MIPI_DSI0_BASE + LANE_SWAP_CTL); |
Siddhartha Agrawal | b6c861f | 2013-05-31 19:36:44 -0700 | [diff] [blame] | 426 | writel(timing_ctl, MIPI_DSI0_BASE + TIMING_CTL); |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 427 | #endif |
Siddhartha Agrawal | 2679a82 | 2013-05-31 19:15:12 -0700 | [diff] [blame] | 428 | |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 429 | return 0; |
| 430 | } |
| 431 | |
| 432 | int mdss_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo, uint32_t |
| 433 | broadcast) |
| 434 | { |
| 435 | int status = 0; |
| 436 | |
| 437 | #if (DISPLAY_TYPE_MDSS == 1) |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 438 | if (pinfo->panel_cmds) { |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 439 | |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 440 | if (broadcast) { |
| 441 | status = mdss_dual_dsi_cmds_tx(pinfo->panel_cmds, |
| 442 | pinfo->num_of_panel_cmds); |
| 443 | |
| 444 | } else { |
| 445 | status = mipi_dsi_cmds_tx(pinfo->panel_cmds, |
| 446 | pinfo->num_of_panel_cmds); |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 447 | if (!status && target_panel_auto_detect_enabled()) |
| 448 | status = |
Shivaraj Shetty | 6460403 | 2013-11-14 16:44:10 +0530 | [diff] [blame] | 449 | mdss_dsi_read_panel_signature(pinfo->signature); |
Siddhartha Agrawal | 980b5ee | 2013-05-30 12:17:50 -0700 | [diff] [blame] | 450 | } |
| 451 | } |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 452 | #endif |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 453 | return status; |
| 454 | } |
| 455 | |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 456 | int mipi_dsi_panel_initialize(struct mipi_dsi_panel_config *pinfo) |
| 457 | { |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 458 | uint8_t DMA_STREAM1 = 0; // for mdp display processor path |
| 459 | uint8_t EMBED_MODE1 = 1; // from frame buffer |
| 460 | uint8_t POWER_MODE2 = 1; // from frame buffer |
| 461 | uint8_t PACK_TYPE1; // long packet |
| 462 | uint8_t VC1 = 0; |
| 463 | uint8_t DT1 = 0; // non embedded mode |
| 464 | uint8_t WC1 = 0; // for non embedded mode only |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 465 | int status = 0; |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 466 | uint8_t DLNx_EN; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 467 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 468 | switch (pinfo->num_of_lanes) { |
| 469 | default: |
| 470 | case 1: |
| 471 | DLNx_EN = 1; // 1 lane |
| 472 | break; |
| 473 | case 2: |
| 474 | DLNx_EN = 3; // 2 lane |
| 475 | break; |
| 476 | case 3: |
| 477 | DLNx_EN = 7; // 3 lane |
| 478 | break; |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 479 | case 4: |
| 480 | DLNx_EN = 0x0F; /* 4 lanes */ |
| 481 | break; |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 482 | } |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 483 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 484 | PACK_TYPE1 = pinfo->pack; |
| 485 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 486 | writel(0x0001, DSI_SOFT_RESET); |
| 487 | writel(0x0000, DSI_SOFT_RESET); |
Chandan Uddaraju | fe93e82 | 2010-11-21 20:44:47 -0800 | [diff] [blame] | 488 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 489 | writel((0 << 16) | 0x3f, DSI_CLK_CTRL); /* Turn on all DSI Clks */ |
| 490 | writel(DMA_STREAM1 << 8 | 0x04, DSI_TRIG_CTRL); // reg 0x80 dma trigger: sw |
| 491 | // trigger 0x4; dma stream1 |
Kinson Chik | e5c9343 | 2011-06-17 09:10:29 -0700 | [diff] [blame] | 492 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 493 | writel(0 << 30 | DLNx_EN << 4 | 0x105, DSI_CTRL); // reg 0x00 for this |
| 494 | // build |
| 495 | writel(EMBED_MODE1 << 28 | POWER_MODE2 << 26 |
| 496 | | PACK_TYPE1 << 24 | VC1 << 22 | DT1 << 16 | WC1, |
| 497 | DSI_COMMAND_MODE_DMA_CTRL); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 498 | |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 499 | if (pinfo->panel_cmds) |
| 500 | status = mipi_dsi_cmds_tx(pinfo->panel_cmds, |
| 501 | pinfo->num_of_panel_cmds); |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 502 | |
Ajay Dudani | b01e506 | 2011-12-03 23:23:42 -0800 | [diff] [blame] | 503 | return status; |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 504 | } |
| 505 | |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 506 | void mipi_dsi_shutdown(void) |
| 507 | { |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 508 | if(!target_cont_splash_screen()) |
| 509 | { |
| 510 | mdp_shutdown(); |
| 511 | writel(0x01010101, DSI_INT_CTRL); |
| 512 | writel(0x13FF3BFF, DSI_ERR_INT_MASK0); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 513 | |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 514 | writel(0, DSI_CLK_CTRL); |
| 515 | writel(0, DSI_CTRL); |
| 516 | writel(0, DSIPHY_PLL_CTRL(0)); |
| 517 | } |
| 518 | else |
| 519 | { |
Chandan Uddaraju | 4877d37 | 2011-07-21 12:51:51 -0700 | [diff] [blame] | 520 | /* To keep the splash screen displayed till kernel driver takes |
| 521 | control, do not turn off the video mode engine and clocks. |
| 522 | Only disabling the MIPI DSI IRQs */ |
| 523 | writel(0x01010101, DSI_INT_CTRL); |
| 524 | writel(0x13FF3BFF, DSI_ERR_INT_MASK0); |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 525 | } |
Chandan Uddaraju | 78ae675 | 2010-10-19 12:57:10 -0700 | [diff] [blame] | 526 | } |
| 527 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 528 | int mipi_config(struct msm_fb_panel_data *panel) |
| 529 | { |
| 530 | int ret = NO_ERROR; |
| 531 | struct msm_panel_info *pinfo; |
| 532 | struct mipi_dsi_panel_config mipi_pinfo; |
| 533 | |
| 534 | if (!panel) |
| 535 | return ERR_INVALID_ARGS; |
| 536 | |
| 537 | pinfo = &(panel->panel_info); |
| 538 | mipi_pinfo.mode = pinfo->mipi.mode; |
| 539 | mipi_pinfo.num_of_lanes = pinfo->mipi.num_of_lanes; |
| 540 | mipi_pinfo.dsi_phy_config = pinfo->mipi.dsi_phy_db; |
| 541 | mipi_pinfo.panel_cmds = pinfo->mipi.panel_cmds; |
| 542 | mipi_pinfo.num_of_panel_cmds = pinfo->mipi.num_of_panel_cmds; |
Channagoud Kadabi | 539ef72 | 2012-03-29 16:02:50 +0530 | [diff] [blame] | 543 | mipi_pinfo.lane_swap = pinfo->mipi.lane_swap; |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 544 | mipi_pinfo.pack = 1; |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 545 | |
| 546 | /* Enable MMSS_AHB_ARB_MATER_PORT_E for |
| 547 | arbiter master0 and master 1 request */ |
Terence Hampson | f49ff4e | 2013-06-18 15:11:31 -0400 | [diff] [blame] | 548 | #if (!DISPLAY_MIPI_PANEL_RENESAS && !DISPLAY_TYPE_DSI6G && !DISPLAY_TYPE_8610) |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 549 | writel(0x00001800, MMSS_SFPB_GPREG); |
| 550 | #endif |
| 551 | |
| 552 | mipi_dsi_phy_init(&mipi_pinfo); |
| 553 | |
| 554 | ret += mipi_dsi_panel_initialize(&mipi_pinfo); |
| 555 | |
Channagoud Kadabi | 01c9182 | 2012-06-06 15:53:30 +0530 | [diff] [blame] | 556 | if (pinfo->rotate && panel->rotate) |
| 557 | pinfo->rotate(); |
| 558 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 559 | return ret; |
| 560 | } |
| 561 | |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 562 | int mdss_dsi_video_mode_config(uint16_t disp_width, |
| 563 | uint16_t disp_height, |
| 564 | uint16_t img_width, |
| 565 | uint16_t img_height, |
| 566 | uint16_t hsync_porch0_fp, |
| 567 | uint16_t hsync_porch0_bp, |
| 568 | uint16_t vsync_porch0_fp, |
| 569 | uint16_t vsync_porch0_bp, |
| 570 | uint16_t hsync_width, |
| 571 | uint16_t vsync_width, |
| 572 | uint16_t dst_format, |
| 573 | uint16_t traffic_mode, |
| 574 | uint8_t lane_en, |
| 575 | uint16_t low_pwr_stop_mode, |
| 576 | uint8_t eof_bllp_pwr, |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 577 | uint8_t interleav, |
| 578 | uint32_t ctl_base) |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 579 | { |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 580 | int status = 0; |
| 581 | |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 582 | #if (DISPLAY_TYPE_MDSS == 1) |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 583 | /* disable mdp first */ |
| 584 | mdp_disable(); |
| 585 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 586 | writel(0x00000000, ctl_base + CLK_CTRL); |
| 587 | writel(0x00000002, ctl_base + CLK_CTRL); |
| 588 | writel(0x00000006, ctl_base + CLK_CTRL); |
| 589 | writel(0x0000000e, ctl_base + CLK_CTRL); |
| 590 | writel(0x0000001e, ctl_base + CLK_CTRL); |
| 591 | writel(0x0000023f, ctl_base + CLK_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 592 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 593 | writel(0, ctl_base + CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 594 | |
Padmanabhan Komanduru | 7860be5 | 2014-03-18 19:07:36 +0530 | [diff] [blame] | 595 | writel(0x13ff3fe0, ctl_base + ERR_INT_MASK0); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 596 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 597 | writel(0x02020202, ctl_base + INT_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 598 | |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 599 | /* For 8916/8939, enable DSI timing double buffering */ |
| 600 | if (readl(ctl_base) == DSI_HW_REV_103_1) |
| 601 | writel(0x1, ctl_base + TIMING_DB_MODE); |
| 602 | |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 603 | writel(((disp_width + hsync_porch0_bp) << 16) | hsync_porch0_bp, |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 604 | ctl_base + VIDEO_MODE_ACTIVE_H); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 605 | |
| 606 | writel(((disp_height + vsync_porch0_bp) << 16) | (vsync_porch0_bp), |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 607 | ctl_base + VIDEO_MODE_ACTIVE_V); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 608 | |
Terence Hampson | 7385f6a | 2013-08-16 15:31:25 -0400 | [diff] [blame] | 609 | if (mdp_get_revision() >= MDP_REV_41 || |
| 610 | mdp_get_revision() == MDP_REV_304) { |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 611 | writel(((disp_height + vsync_porch0_fp |
| 612 | + vsync_porch0_bp - 1) << 16) |
| 613 | | (disp_width + hsync_porch0_fp |
| 614 | + hsync_porch0_bp - 1), |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 615 | ctl_base + VIDEO_MODE_TOTAL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 616 | } else { |
| 617 | writel(((disp_height + vsync_porch0_fp |
| 618 | + vsync_porch0_bp) << 16) |
| 619 | | (disp_width + hsync_porch0_fp |
| 620 | + hsync_porch0_bp), |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 621 | ctl_base + VIDEO_MODE_TOTAL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 622 | } |
| 623 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 624 | writel((hsync_width << 16) | 0, ctl_base + VIDEO_MODE_HSYNC); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 625 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 626 | writel(0 << 16 | 0, ctl_base + VIDEO_MODE_VSYNC); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 627 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 628 | writel(vsync_width << 16 | 0, ctl_base + VIDEO_MODE_VSYNC_VPOS); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 629 | |
Padmanabhan Komanduru | daebf6b | 2014-08-20 20:39:40 +0530 | [diff] [blame] | 630 | /* For 8916/8939, flush the DSI timing registers */ |
| 631 | if (readl(ctl_base) == DSI_HW_REV_103_1) |
| 632 | writel(0x1, ctl_base + TIMING_FLUSH); |
| 633 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 634 | writel(0x0, ctl_base + EOT_PACKET_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 635 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 636 | writel(0x00000100, ctl_base + MISR_VIDEO_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 637 | |
| 638 | if (mdp_get_revision() >= MDP_REV_41) { |
| 639 | writel(low_pwr_stop_mode << 16 | |
| 640 | eof_bllp_pwr << 12 | traffic_mode << 8 |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 641 | | dst_format << 4 | 0x0, ctl_base + VIDEO_MODE_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 642 | } else { |
| 643 | writel(1 << 28 | 1 << 24 | 1 << 20 | low_pwr_stop_mode << 16 | |
| 644 | eof_bllp_pwr << 12 | traffic_mode << 8 |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 645 | | dst_format << 4 | 0x0, ctl_base + VIDEO_MODE_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 646 | } |
| 647 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 648 | writel(0x3fd08, ctl_base + HS_TIMER_CTRL); |
| 649 | writel(0x00010100, ctl_base + MISR_VIDEO_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 650 | |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 651 | writel(0x00010100, ctl_base + INT_CTRL); |
| 652 | writel(0x02010202, ctl_base + INT_CTRL); |
| 653 | writel(0x02030303, ctl_base + INT_CTRL); |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 654 | |
| 655 | writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 |
Siddhartha Agrawal | 6e76004 | 2013-05-30 21:10:18 -0700 | [diff] [blame] | 656 | | 0x103, ctl_base + CTRL); |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 657 | #endif |
Siddhartha Agrawal | 06bb82f | 2013-05-24 12:32:33 -0700 | [diff] [blame] | 658 | |
| 659 | return status; |
| 660 | } |
| 661 | |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 662 | int mdss_dsi_config(struct msm_fb_panel_data *panel) |
| 663 | { |
| 664 | int ret = NO_ERROR; |
| 665 | struct msm_panel_info *pinfo; |
| 666 | struct mipi_dsi_panel_config mipi_pinfo; |
| 667 | |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 668 | #if (DISPLAY_TYPE_MDSS == 1) |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 669 | if (!panel) |
| 670 | return ERR_INVALID_ARGS; |
| 671 | |
| 672 | pinfo = &(panel->panel_info); |
| 673 | mipi_pinfo.mode = pinfo->mipi.mode; |
| 674 | mipi_pinfo.num_of_lanes = pinfo->mipi.num_of_lanes; |
| 675 | mipi_pinfo.mdss_dsi_phy_config = pinfo->mipi.mdss_dsi_phy_db; |
| 676 | mipi_pinfo.panel_cmds = pinfo->mipi.panel_cmds; |
| 677 | mipi_pinfo.num_of_panel_cmds = pinfo->mipi.num_of_panel_cmds; |
| 678 | mipi_pinfo.lane_swap = pinfo->mipi.lane_swap; |
| 679 | mipi_pinfo.pack = 0; |
Siddhartha Agrawal | b6c861f | 2013-05-31 19:36:44 -0700 | [diff] [blame] | 680 | mipi_pinfo.t_clk_pre = pinfo->mipi.t_clk_pre; |
| 681 | mipi_pinfo.t_clk_post = pinfo->mipi.t_clk_post; |
Casey Piper | 8403675 | 2013-09-05 14:56:37 -0700 | [diff] [blame] | 682 | mipi_pinfo.signature = pinfo->mipi.signature; |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 683 | |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 684 | mdss_dsi_phy_init(&mipi_pinfo, MIPI_DSI0_BASE, DSI0_PHY_BASE); |
Siddhartha Agrawal | 1b2ed84 | 2013-05-29 18:02:28 -0700 | [diff] [blame] | 685 | if (pinfo->mipi.dual_dsi) |
Padmanabhan Komanduru | cdc651e | 2014-03-25 20:25:55 +0530 | [diff] [blame] | 686 | mdss_dsi_phy_init(&mipi_pinfo, MIPI_DSI1_BASE, DSI1_PHY_BASE); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 687 | |
Dhaval Patel | 9207dec | 2014-04-16 10:45:32 -0700 | [diff] [blame] | 688 | ret = mdss_dsi_host_init(&mipi_pinfo, pinfo->mipi.dual_dsi, |
| 689 | pinfo->mipi.broadcast); |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 690 | if (ret) { |
| 691 | dprintf(CRITICAL, "dsi host init error\n"); |
| 692 | goto error; |
| 693 | } |
| 694 | |
Xiaoming Zhou | 03fd48b | 2014-07-31 15:24:41 -0400 | [diff] [blame] | 695 | mdss_dsi_phy_contention_detection(&mipi_pinfo, DSI0_PHY_BASE); |
| 696 | |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 697 | if (panel->pre_init_func) { |
| 698 | ret = panel->pre_init_func(); |
| 699 | if (ret) { |
| 700 | dprintf(CRITICAL, "pre_init_func error\n"); |
| 701 | goto error; |
| 702 | } |
| 703 | } |
| 704 | |
| 705 | ret = mdss_dsi_panel_initialize(&mipi_pinfo, pinfo->mipi.broadcast); |
| 706 | if (ret) { |
| 707 | dprintf(CRITICAL, "dsi panel init error\n"); |
| 708 | goto error; |
| 709 | } |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 710 | |
| 711 | if (pinfo->rotate && panel->rotate) |
| 712 | pinfo->rotate(); |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 713 | #endif |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 714 | |
Ray Zhang | 4c7e37f | 2013-12-03 17:04:55 +0800 | [diff] [blame] | 715 | error: |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 716 | return ret; |
| 717 | } |
| 718 | |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 719 | int mdss_dsi_cmd_mode_config(uint16_t disp_width, |
| 720 | uint16_t disp_height, |
| 721 | uint16_t img_width, |
| 722 | uint16_t img_height, |
| 723 | uint16_t dst_format, |
Xiaoming Zhou | 8d534dd | 2013-07-29 15:49:19 -0400 | [diff] [blame] | 724 | uint8_t ystride, |
| 725 | uint8_t lane_en, |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 726 | uint8_t interleav, |
| 727 | uint32_t ctl_base) |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 728 | { |
Xiaoming Zhou | 8d534dd | 2013-07-29 15:49:19 -0400 | [diff] [blame] | 729 | uint16_t dst_fmt = 0; |
| 730 | |
| 731 | switch (dst_format) { |
| 732 | case DSI_VIDEO_DST_FORMAT_RGB565: |
| 733 | dst_fmt = DSI_CMD_DST_FORMAT_RGB565; |
| 734 | break; |
| 735 | case DSI_VIDEO_DST_FORMAT_RGB666: |
| 736 | case DSI_VIDEO_DST_FORMAT_RGB666_LOOSE: |
| 737 | dst_fmt = DSI_CMD_DST_FORMAT_RGB666; |
| 738 | break; |
| 739 | case DSI_VIDEO_DST_FORMAT_RGB888: |
| 740 | dst_fmt = DSI_CMD_DST_FORMAT_RGB888; |
| 741 | break; |
| 742 | default: |
| 743 | dprintf(CRITICAL, "unsupported dst format\n"); |
| 744 | return ERROR; |
| 745 | } |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 746 | |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 747 | #if (DISPLAY_TYPE_MDSS == 1) |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 748 | writel(0x00000000, ctl_base + CLK_CTRL); |
| 749 | writel(0x00000000, ctl_base + CLK_CTRL); |
| 750 | writel(0x00000000, ctl_base + CLK_CTRL); |
| 751 | writel(0x00000000, ctl_base + CLK_CTRL); |
| 752 | writel(0x00000002, ctl_base + CLK_CTRL); |
| 753 | writel(0x00000006, ctl_base + CLK_CTRL); |
| 754 | writel(0x0000000e, ctl_base + CLK_CTRL); |
| 755 | writel(0x0000001e, ctl_base + CLK_CTRL); |
| 756 | writel(0x0000023f, ctl_base + CLK_CTRL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 757 | |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 758 | writel(0, ctl_base + CTRL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 759 | |
Padmanabhan Komanduru | 7860be5 | 2014-03-18 19:07:36 +0530 | [diff] [blame] | 760 | writel(0x13ff3fe0, ctl_base + ERR_INT_MASK0); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 761 | |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 762 | writel(0x02020202, ctl_base + INT_CTRL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 763 | |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 764 | writel(dst_fmt, ctl_base + COMMAND_MODE_MDP_CTRL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 765 | writel((img_width * ystride + 1) << 16 | 0x0039, |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 766 | ctl_base + COMMAND_MODE_MDP_STREAM0_CTRL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 767 | writel((img_width * ystride + 1) << 16 | 0x0039, |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 768 | ctl_base + COMMAND_MODE_MDP_STREAM1_CTRL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 769 | writel(img_height << 16 | img_width, |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 770 | ctl_base + COMMAND_MODE_MDP_STREAM0_TOTAL); |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 771 | writel(img_height << 16 | img_width, |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 772 | ctl_base + COMMAND_MODE_MDP_STREAM1_TOTAL); |
| 773 | writel(0x13c2c, ctl_base + COMMAND_MODE_MDP_DCS_CMD_CTRL); |
Xiaoming Zhou | 8d534dd | 2013-07-29 15:49:19 -0400 | [diff] [blame] | 774 | writel(interleav << 30 | 0 << 24 | 0 << 20 | lane_en << 4 | 0x105, |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 775 | ctl_base + CTRL); |
Padmanabhan Komanduru | 7860be5 | 2014-03-18 19:07:36 +0530 | [diff] [blame] | 776 | writel(0x14000000, ctl_base + COMMAND_MODE_DMA_CTRL); |
Dhaval Patel | 5b22fe7 | 2014-01-02 16:28:38 -0800 | [diff] [blame] | 777 | writel(0x10000000, ctl_base + MISR_CMD_CTRL); |
Xiaoming Zhou | a046933 | 2014-03-04 18:34:24 -0500 | [diff] [blame] | 778 | writel(0x1, ctl_base + EOT_PACKET_CTRL); |
Terence Hampson | cc3345c | 2013-06-27 15:30:10 -0400 | [diff] [blame] | 779 | #endif |
Xiaoming Zhou | 8d534dd | 2013-07-29 15:49:19 -0400 | [diff] [blame] | 780 | return 0; |
Siddhartha Agrawal | 7317e48 | 2013-04-21 16:16:57 -0700 | [diff] [blame] | 781 | } |
| 782 | |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 783 | int mipi_dsi_on() |
| 784 | { |
| 785 | int ret = NO_ERROR; |
| 786 | unsigned long ReadValue; |
| 787 | unsigned long count = 0; |
| 788 | |
| 789 | ReadValue = readl(DSI_INT_CTRL) & 0x00010000; |
| 790 | |
| 791 | mdelay(10); |
| 792 | |
| 793 | while (ReadValue != 0x00010000) { |
| 794 | ReadValue = readl(DSI_INT_CTRL) & 0x00010000; |
| 795 | count++; |
| 796 | if (count > 0xffff) { |
| 797 | dprintf(CRITICAL, "Video lane test failed\n"); |
| 798 | return ERROR; |
| 799 | } |
| 800 | } |
| 801 | |
Amir Samuelov | 2d4ba16 | 2012-07-22 11:53:14 +0300 | [diff] [blame] | 802 | dprintf(INFO, "Video lane tested successfully\n"); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 803 | return ret; |
| 804 | } |
| 805 | |
Siddhartha Agrawal | 24d81b5 | 2013-07-01 11:13:32 -0700 | [diff] [blame] | 806 | int mipi_dsi_off(struct msm_panel_info *pinfo) |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 807 | { |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 808 | if(!target_cont_splash_screen()) |
| 809 | { |
| 810 | writel(0, DSI_CLK_CTRL); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 811 | writel(0x1F1, DSI_CTRL); |
Siddhartha Agrawal | 3e694ea | 2013-01-23 17:01:31 -0800 | [diff] [blame] | 812 | mdelay(10); |
| 813 | writel(0x0001, DSI_SOFT_RESET); |
| 814 | writel(0x0000, DSI_SOFT_RESET); |
Amol Jadi | 6834f1a | 2012-06-29 14:42:59 -0700 | [diff] [blame] | 815 | writel(0, DSI_CTRL); |
Siddhartha Agrawal | e0033a1 | 2013-02-23 15:37:42 -0800 | [diff] [blame] | 816 | } |
| 817 | |
Dhaval Patel | ddde45a | 2014-08-13 19:07:59 -0700 | [diff] [blame] | 818 | writel(0x1115501, MIPI_DSI0_BASE + INT_CTRL); |
Siddhartha Agrawal | 24d81b5 | 2013-07-01 11:13:32 -0700 | [diff] [blame] | 819 | if (pinfo->mipi.broadcast) |
Dhaval Patel | ddde45a | 2014-08-13 19:07:59 -0700 | [diff] [blame] | 820 | writel(0x1115501, MIPI_DSI1_BASE + INT_CTRL); |
Shashank Mittal | 4bfb2e3 | 2012-04-16 10:56:27 -0700 | [diff] [blame] | 821 | |
| 822 | return NO_ERROR; |
| 823 | } |
Channagoud Kadabi | 10189fd | 2012-05-25 13:33:39 +0530 | [diff] [blame] | 824 | |
| 825 | int mipi_cmd_trigger() |
| 826 | { |
| 827 | writel(0x1, DSI_CMD_MODE_MDP_SW_TRIGGER); |
| 828 | |
| 829 | return NO_ERROR; |
| 830 | } |