Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2010 Daniel Vetter |
Ben Widawsky | c4ac524 | 2014-02-19 22:05:47 -0800 | [diff] [blame] | 3 | * Copyright © 2011-2014 Intel Corporation |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice (including the next |
| 13 | * paragraph) shall be included in all copies or substantial portions of the |
| 14 | * Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 22 | * IN THE SOFTWARE. |
| 23 | * |
| 24 | */ |
| 25 | |
Daniel Vetter | 0e46ce2 | 2014-01-08 16:10:27 +0100 | [diff] [blame] | 26 | #include <linux/seq_file.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 27 | #include <drm/drmP.h> |
| 28 | #include <drm/i915_drm.h> |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 29 | #include "i915_drv.h" |
Yu Zhang | 5dda8fa | 2015-02-10 19:05:48 +0800 | [diff] [blame] | 30 | #include "i915_vgpu.h" |
Daniel Vetter | 76aaf22 | 2010-11-05 22:23:30 +0100 | [diff] [blame] | 31 | #include "i915_trace.h" |
| 32 | #include "intel_drv.h" |
| 33 | |
Tvrtko Ursulin | 45f8f69 | 2014-12-10 17:27:59 +0000 | [diff] [blame] | 34 | /** |
| 35 | * DOC: Global GTT views |
| 36 | * |
| 37 | * Background and previous state |
| 38 | * |
| 39 | * Historically objects could exists (be bound) in global GTT space only as |
| 40 | * singular instances with a view representing all of the object's backing pages |
| 41 | * in a linear fashion. This view will be called a normal view. |
| 42 | * |
| 43 | * To support multiple views of the same object, where the number of mapped |
| 44 | * pages is not equal to the backing store, or where the layout of the pages |
| 45 | * is not linear, concept of a GGTT view was added. |
| 46 | * |
| 47 | * One example of an alternative view is a stereo display driven by a single |
| 48 | * image. In this case we would have a framebuffer looking like this |
| 49 | * (2x2 pages): |
| 50 | * |
| 51 | * 12 |
| 52 | * 34 |
| 53 | * |
| 54 | * Above would represent a normal GGTT view as normally mapped for GPU or CPU |
| 55 | * rendering. In contrast, fed to the display engine would be an alternative |
| 56 | * view which could look something like this: |
| 57 | * |
| 58 | * 1212 |
| 59 | * 3434 |
| 60 | * |
| 61 | * In this example both the size and layout of pages in the alternative view is |
| 62 | * different from the normal view. |
| 63 | * |
| 64 | * Implementation and usage |
| 65 | * |
| 66 | * GGTT views are implemented using VMAs and are distinguished via enum |
| 67 | * i915_ggtt_view_type and struct i915_ggtt_view. |
| 68 | * |
| 69 | * A new flavour of core GEM functions which work with GGTT bound objects were |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 70 | * added with the _ggtt_ infix, and sometimes with _view postfix to avoid |
| 71 | * renaming in large amounts of code. They take the struct i915_ggtt_view |
| 72 | * parameter encapsulating all metadata required to implement a view. |
Tvrtko Ursulin | 45f8f69 | 2014-12-10 17:27:59 +0000 | [diff] [blame] | 73 | * |
| 74 | * As a helper for callers which are only interested in the normal view, |
| 75 | * globally const i915_ggtt_view_normal singleton instance exists. All old core |
| 76 | * GEM API functions, the ones not taking the view parameter, are operating on, |
| 77 | * or with the normal GGTT view. |
| 78 | * |
| 79 | * Code wanting to add or use a new GGTT view needs to: |
| 80 | * |
| 81 | * 1. Add a new enum with a suitable name. |
| 82 | * 2. Extend the metadata in the i915_ggtt_view structure if required. |
| 83 | * 3. Add support to i915_get_vma_pages(). |
| 84 | * |
| 85 | * New views are required to build a scatter-gather table from within the |
| 86 | * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and |
| 87 | * exists for the lifetime of an VMA. |
| 88 | * |
| 89 | * Core API is designed to have copy semantics which means that passed in |
| 90 | * struct i915_ggtt_view does not need to be persistent (left around after |
| 91 | * calling the core API functions). |
| 92 | * |
| 93 | */ |
| 94 | |
Daniel Vetter | 70b9f6f | 2015-04-14 17:35:27 +0200 | [diff] [blame] | 95 | static int |
| 96 | i915_get_ggtt_vma_pages(struct i915_vma *vma); |
| 97 | |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 98 | const struct i915_ggtt_view i915_ggtt_view_normal; |
Joonas Lahtinen | 9abc464 | 2015-03-27 13:09:22 +0200 | [diff] [blame] | 99 | const struct i915_ggtt_view i915_ggtt_view_rotated = { |
| 100 | .type = I915_GGTT_VIEW_ROTATED |
| 101 | }; |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 102 | |
Daniel Vetter | cfa7c86 | 2014-04-29 11:53:58 +0200 | [diff] [blame] | 103 | static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) |
| 104 | { |
Chris Wilson | 1893a71 | 2014-09-19 11:56:27 +0100 | [diff] [blame] | 105 | bool has_aliasing_ppgtt; |
| 106 | bool has_full_ppgtt; |
| 107 | |
| 108 | has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6; |
| 109 | has_full_ppgtt = INTEL_INFO(dev)->gen >= 7; |
Chris Wilson | 1893a71 | 2014-09-19 11:56:27 +0100 | [diff] [blame] | 110 | |
Yu Zhang | 71ba2d6 | 2015-02-10 19:05:54 +0800 | [diff] [blame] | 111 | if (intel_vgpu_active(dev)) |
| 112 | has_full_ppgtt = false; /* emulation is too hard */ |
| 113 | |
Damien Lespiau | 70ee45e | 2014-11-14 15:05:59 +0000 | [diff] [blame] | 114 | /* |
| 115 | * We don't allow disabling PPGTT for gen9+ as it's a requirement for |
| 116 | * execlists, the sole mechanism available to submit work. |
| 117 | */ |
| 118 | if (INTEL_INFO(dev)->gen < 9 && |
| 119 | (enable_ppgtt == 0 || !has_aliasing_ppgtt)) |
Daniel Vetter | cfa7c86 | 2014-04-29 11:53:58 +0200 | [diff] [blame] | 120 | return 0; |
| 121 | |
| 122 | if (enable_ppgtt == 1) |
| 123 | return 1; |
| 124 | |
Chris Wilson | 1893a71 | 2014-09-19 11:56:27 +0100 | [diff] [blame] | 125 | if (enable_ppgtt == 2 && has_full_ppgtt) |
Daniel Vetter | cfa7c86 | 2014-04-29 11:53:58 +0200 | [diff] [blame] | 126 | return 2; |
| 127 | |
Daniel Vetter | 93a25a9 | 2014-03-06 09:40:43 +0100 | [diff] [blame] | 128 | #ifdef CONFIG_INTEL_IOMMU |
| 129 | /* Disable ppgtt on SNB if VT-d is on. */ |
| 130 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { |
| 131 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); |
Daniel Vetter | cfa7c86 | 2014-04-29 11:53:58 +0200 | [diff] [blame] | 132 | return 0; |
Daniel Vetter | 93a25a9 | 2014-03-06 09:40:43 +0100 | [diff] [blame] | 133 | } |
| 134 | #endif |
| 135 | |
Jesse Barnes | 62942ed | 2014-06-13 09:28:33 -0700 | [diff] [blame] | 136 | /* Early VLV doesn't have this */ |
Ville Syrjälä | ca2aed6c | 2014-06-28 02:03:56 +0300 | [diff] [blame] | 137 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
| 138 | dev->pdev->revision < 0xb) { |
Jesse Barnes | 62942ed | 2014-06-13 09:28:33 -0700 | [diff] [blame] | 139 | DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); |
| 140 | return 0; |
| 141 | } |
| 142 | |
Michel Thierry | 2f82bbd | 2014-12-15 14:58:00 +0000 | [diff] [blame] | 143 | if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists) |
| 144 | return 2; |
| 145 | else |
| 146 | return has_aliasing_ppgtt ? 1 : 0; |
Daniel Vetter | 93a25a9 | 2014-03-06 09:40:43 +0100 | [diff] [blame] | 147 | } |
| 148 | |
Daniel Vetter | 70b9f6f | 2015-04-14 17:35:27 +0200 | [diff] [blame] | 149 | static int ppgtt_bind_vma(struct i915_vma *vma, |
| 150 | enum i915_cache_level cache_level, |
| 151 | u32 unused) |
Daniel Vetter | 4755265 | 2015-04-14 17:35:24 +0200 | [diff] [blame] | 152 | { |
| 153 | u32 pte_flags = 0; |
| 154 | |
| 155 | /* Currently applicable only to VLV */ |
| 156 | if (vma->obj->gt_ro) |
| 157 | pte_flags |= PTE_READ_ONLY; |
| 158 | |
| 159 | vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, |
| 160 | cache_level, pte_flags); |
Daniel Vetter | 70b9f6f | 2015-04-14 17:35:27 +0200 | [diff] [blame] | 161 | |
| 162 | return 0; |
Daniel Vetter | 4755265 | 2015-04-14 17:35:24 +0200 | [diff] [blame] | 163 | } |
| 164 | |
| 165 | static void ppgtt_unbind_vma(struct i915_vma *vma) |
| 166 | { |
| 167 | vma->vm->clear_range(vma->vm, |
| 168 | vma->node.start, |
| 169 | vma->obj->base.size, |
| 170 | true); |
| 171 | } |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 172 | |
Daniel Vetter | 2c642b0 | 2015-04-14 17:35:26 +0200 | [diff] [blame] | 173 | static gen8_pte_t gen8_pte_encode(dma_addr_t addr, |
| 174 | enum i915_cache_level level, |
| 175 | bool valid) |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 176 | { |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 177 | gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 178 | pte |= addr; |
Ben Widawsky | 63c42e5 | 2014-04-18 18:04:27 -0300 | [diff] [blame] | 179 | |
| 180 | switch (level) { |
| 181 | case I915_CACHE_NONE: |
Ben Widawsky | fbe5d36 | 2013-11-04 19:56:49 -0800 | [diff] [blame] | 182 | pte |= PPAT_UNCACHED_INDEX; |
Ben Widawsky | 63c42e5 | 2014-04-18 18:04:27 -0300 | [diff] [blame] | 183 | break; |
| 184 | case I915_CACHE_WT: |
| 185 | pte |= PPAT_DISPLAY_ELLC_INDEX; |
| 186 | break; |
| 187 | default: |
| 188 | pte |= PPAT_CACHED_INDEX; |
| 189 | break; |
| 190 | } |
| 191 | |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 192 | return pte; |
| 193 | } |
| 194 | |
Mika Kuoppala | fe36f55 | 2015-06-25 18:35:16 +0300 | [diff] [blame] | 195 | static gen8_pde_t gen8_pde_encode(const dma_addr_t addr, |
| 196 | const enum i915_cache_level level) |
Ben Widawsky | b1fe667 | 2013-11-04 21:20:14 -0800 | [diff] [blame] | 197 | { |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 198 | gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; |
Ben Widawsky | b1fe667 | 2013-11-04 21:20:14 -0800 | [diff] [blame] | 199 | pde |= addr; |
| 200 | if (level != I915_CACHE_NONE) |
| 201 | pde |= PPAT_CACHED_PDE_INDEX; |
| 202 | else |
| 203 | pde |= PPAT_UNCACHED_INDEX; |
| 204 | return pde; |
| 205 | } |
| 206 | |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 207 | static gen6_pte_t snb_pte_encode(dma_addr_t addr, |
| 208 | enum i915_cache_level level, |
| 209 | bool valid, u32 unused) |
Ben Widawsky | 54d1252 | 2012-09-24 16:44:32 -0700 | [diff] [blame] | 210 | { |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 211 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
Ben Widawsky | 54d1252 | 2012-09-24 16:44:32 -0700 | [diff] [blame] | 212 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
Ben Widawsky | e7210c3 | 2012-10-19 09:33:22 -0700 | [diff] [blame] | 213 | |
| 214 | switch (level) { |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 215 | case I915_CACHE_L3_LLC: |
| 216 | case I915_CACHE_LLC: |
| 217 | pte |= GEN6_PTE_CACHE_LLC; |
| 218 | break; |
| 219 | case I915_CACHE_NONE: |
| 220 | pte |= GEN6_PTE_UNCACHED; |
| 221 | break; |
| 222 | default: |
Daniel Vetter | 5f77eeb | 2014-12-08 16:40:10 +0100 | [diff] [blame] | 223 | MISSING_CASE(level); |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 224 | } |
| 225 | |
| 226 | return pte; |
| 227 | } |
| 228 | |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 229 | static gen6_pte_t ivb_pte_encode(dma_addr_t addr, |
| 230 | enum i915_cache_level level, |
| 231 | bool valid, u32 unused) |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 232 | { |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 233 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 234 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
| 235 | |
| 236 | switch (level) { |
| 237 | case I915_CACHE_L3_LLC: |
| 238 | pte |= GEN7_PTE_CACHE_L3_LLC; |
Ben Widawsky | e7210c3 | 2012-10-19 09:33:22 -0700 | [diff] [blame] | 239 | break; |
| 240 | case I915_CACHE_LLC: |
| 241 | pte |= GEN6_PTE_CACHE_LLC; |
| 242 | break; |
| 243 | case I915_CACHE_NONE: |
Kenneth Graunke | 9119708 | 2013-04-22 00:53:51 -0700 | [diff] [blame] | 244 | pte |= GEN6_PTE_UNCACHED; |
Ben Widawsky | e7210c3 | 2012-10-19 09:33:22 -0700 | [diff] [blame] | 245 | break; |
| 246 | default: |
Daniel Vetter | 5f77eeb | 2014-12-08 16:40:10 +0100 | [diff] [blame] | 247 | MISSING_CASE(level); |
Ben Widawsky | e7210c3 | 2012-10-19 09:33:22 -0700 | [diff] [blame] | 248 | } |
| 249 | |
Ben Widawsky | 54d1252 | 2012-09-24 16:44:32 -0700 | [diff] [blame] | 250 | return pte; |
| 251 | } |
| 252 | |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 253 | static gen6_pte_t byt_pte_encode(dma_addr_t addr, |
| 254 | enum i915_cache_level level, |
| 255 | bool valid, u32 flags) |
Kenneth Graunke | 93c34e7 | 2013-04-22 00:53:50 -0700 | [diff] [blame] | 256 | { |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 257 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
Kenneth Graunke | 93c34e7 | 2013-04-22 00:53:50 -0700 | [diff] [blame] | 258 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
| 259 | |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 260 | if (!(flags & PTE_READ_ONLY)) |
| 261 | pte |= BYT_PTE_WRITEABLE; |
Kenneth Graunke | 93c34e7 | 2013-04-22 00:53:50 -0700 | [diff] [blame] | 262 | |
| 263 | if (level != I915_CACHE_NONE) |
| 264 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; |
| 265 | |
| 266 | return pte; |
| 267 | } |
| 268 | |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 269 | static gen6_pte_t hsw_pte_encode(dma_addr_t addr, |
| 270 | enum i915_cache_level level, |
| 271 | bool valid, u32 unused) |
Kenneth Graunke | 9119708 | 2013-04-22 00:53:51 -0700 | [diff] [blame] | 272 | { |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 273 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
Ben Widawsky | 0d8ff15 | 2013-07-04 11:02:03 -0700 | [diff] [blame] | 274 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
Kenneth Graunke | 9119708 | 2013-04-22 00:53:51 -0700 | [diff] [blame] | 275 | |
| 276 | if (level != I915_CACHE_NONE) |
Ben Widawsky | 87a6b68 | 2013-08-04 23:47:29 -0700 | [diff] [blame] | 277 | pte |= HSW_WB_LLC_AGE3; |
Kenneth Graunke | 9119708 | 2013-04-22 00:53:51 -0700 | [diff] [blame] | 278 | |
| 279 | return pte; |
| 280 | } |
| 281 | |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 282 | static gen6_pte_t iris_pte_encode(dma_addr_t addr, |
| 283 | enum i915_cache_level level, |
| 284 | bool valid, u32 unused) |
Ben Widawsky | 4d15c14 | 2013-07-04 11:02:06 -0700 | [diff] [blame] | 285 | { |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 286 | gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; |
Ben Widawsky | 4d15c14 | 2013-07-04 11:02:06 -0700 | [diff] [blame] | 287 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
| 288 | |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 289 | switch (level) { |
| 290 | case I915_CACHE_NONE: |
| 291 | break; |
| 292 | case I915_CACHE_WT: |
Chris Wilson | c51e970 | 2013-11-22 10:37:53 +0000 | [diff] [blame] | 293 | pte |= HSW_WT_ELLC_LLC_AGE3; |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 294 | break; |
| 295 | default: |
Chris Wilson | c51e970 | 2013-11-22 10:37:53 +0000 | [diff] [blame] | 296 | pte |= HSW_WB_ELLC_LLC_AGE3; |
Chris Wilson | 651d794 | 2013-08-08 14:41:10 +0100 | [diff] [blame] | 297 | break; |
| 298 | } |
Ben Widawsky | 4d15c14 | 2013-07-04 11:02:06 -0700 | [diff] [blame] | 299 | |
| 300 | return pte; |
| 301 | } |
| 302 | |
Mika Kuoppala | c114f76 | 2015-06-25 18:35:13 +0300 | [diff] [blame] | 303 | static int __setup_page_dma(struct drm_device *dev, |
| 304 | struct i915_page_dma *p, gfp_t flags) |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 305 | { |
| 306 | struct device *device = &dev->pdev->dev; |
| 307 | |
Mika Kuoppala | c114f76 | 2015-06-25 18:35:13 +0300 | [diff] [blame] | 308 | p->page = alloc_page(flags); |
Mika Kuoppala | 44159dd | 2015-06-25 18:35:07 +0300 | [diff] [blame] | 309 | if (!p->page) |
Michel Thierry | 1266cdb | 2015-03-24 17:06:33 +0000 | [diff] [blame] | 310 | return -ENOMEM; |
| 311 | |
Mika Kuoppala | 44159dd | 2015-06-25 18:35:07 +0300 | [diff] [blame] | 312 | p->daddr = dma_map_page(device, |
| 313 | p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL); |
| 314 | |
| 315 | if (dma_mapping_error(device, p->daddr)) { |
| 316 | __free_page(p->page); |
| 317 | return -EINVAL; |
| 318 | } |
| 319 | |
Michel Thierry | 1266cdb | 2015-03-24 17:06:33 +0000 | [diff] [blame] | 320 | return 0; |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 321 | } |
| 322 | |
Mika Kuoppala | c114f76 | 2015-06-25 18:35:13 +0300 | [diff] [blame] | 323 | static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p) |
| 324 | { |
| 325 | return __setup_page_dma(dev, p, GFP_KERNEL); |
| 326 | } |
| 327 | |
Mika Kuoppala | 44159dd | 2015-06-25 18:35:07 +0300 | [diff] [blame] | 328 | static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p) |
| 329 | { |
| 330 | if (WARN_ON(!p->page)) |
| 331 | return; |
| 332 | |
| 333 | dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL); |
| 334 | __free_page(p->page); |
| 335 | memset(p, 0, sizeof(*p)); |
| 336 | } |
| 337 | |
Mika Kuoppala | d1c54ac | 2015-06-25 18:35:11 +0300 | [diff] [blame] | 338 | static void *kmap_page_dma(struct i915_page_dma *p) |
Mika Kuoppala | 73eeea5 | 2015-06-25 18:35:10 +0300 | [diff] [blame] | 339 | { |
Mika Kuoppala | d1c54ac | 2015-06-25 18:35:11 +0300 | [diff] [blame] | 340 | return kmap_atomic(p->page); |
| 341 | } |
Mika Kuoppala | 73eeea5 | 2015-06-25 18:35:10 +0300 | [diff] [blame] | 342 | |
Mika Kuoppala | d1c54ac | 2015-06-25 18:35:11 +0300 | [diff] [blame] | 343 | /* We use the flushing unmap only with ppgtt structures: |
| 344 | * page directories, page tables and scratch pages. |
| 345 | */ |
| 346 | static void kunmap_page_dma(struct drm_device *dev, void *vaddr) |
| 347 | { |
Mika Kuoppala | 73eeea5 | 2015-06-25 18:35:10 +0300 | [diff] [blame] | 348 | /* There are only few exceptions for gen >=6. chv and bxt. |
| 349 | * And we are not sure about the latter so play safe for now. |
| 350 | */ |
| 351 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) |
| 352 | drm_clflush_virt_range(vaddr, PAGE_SIZE); |
| 353 | |
| 354 | kunmap_atomic(vaddr); |
| 355 | } |
| 356 | |
Mika Kuoppala | 567047b | 2015-06-25 18:35:12 +0300 | [diff] [blame] | 357 | #define kmap_px(px) kmap_page_dma(px_base(px)) |
Mika Kuoppala | d1c54ac | 2015-06-25 18:35:11 +0300 | [diff] [blame] | 358 | #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr)) |
| 359 | |
Mika Kuoppala | 567047b | 2015-06-25 18:35:12 +0300 | [diff] [blame] | 360 | #define setup_px(dev, px) setup_page_dma((dev), px_base(px)) |
| 361 | #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px)) |
| 362 | #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v)) |
| 363 | #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v)) |
| 364 | |
Mika Kuoppala | d1c54ac | 2015-06-25 18:35:11 +0300 | [diff] [blame] | 365 | static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p, |
| 366 | const uint64_t val) |
| 367 | { |
| 368 | int i; |
| 369 | uint64_t * const vaddr = kmap_page_dma(p); |
| 370 | |
| 371 | for (i = 0; i < 512; i++) |
| 372 | vaddr[i] = val; |
| 373 | |
| 374 | kunmap_page_dma(dev, vaddr); |
| 375 | } |
| 376 | |
Mika Kuoppala | 73eeea5 | 2015-06-25 18:35:10 +0300 | [diff] [blame] | 377 | static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p, |
| 378 | const uint32_t val32) |
| 379 | { |
| 380 | uint64_t v = val32; |
| 381 | |
| 382 | v = v << 32 | val32; |
| 383 | |
| 384 | fill_page_dma(dev, p, v); |
| 385 | } |
| 386 | |
Mika Kuoppala | 8a1ebd7 | 2015-05-22 20:04:59 +0300 | [diff] [blame] | 387 | static struct i915_page_table *alloc_pt(struct drm_device *dev) |
Ben Widawsky | 06fda60 | 2015-02-24 16:22:36 +0000 | [diff] [blame] | 388 | { |
Michel Thierry | ec565b3 | 2015-04-08 12:13:23 +0100 | [diff] [blame] | 389 | struct i915_page_table *pt; |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 390 | const size_t count = INTEL_INFO(dev)->gen >= 8 ? |
| 391 | GEN8_PTES : GEN6_PTES; |
| 392 | int ret = -ENOMEM; |
Ben Widawsky | 06fda60 | 2015-02-24 16:22:36 +0000 | [diff] [blame] | 393 | |
| 394 | pt = kzalloc(sizeof(*pt), GFP_KERNEL); |
| 395 | if (!pt) |
| 396 | return ERR_PTR(-ENOMEM); |
| 397 | |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 398 | pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes), |
| 399 | GFP_KERNEL); |
| 400 | |
| 401 | if (!pt->used_ptes) |
| 402 | goto fail_bitmap; |
| 403 | |
Mika Kuoppala | 567047b | 2015-06-25 18:35:12 +0300 | [diff] [blame] | 404 | ret = setup_px(dev, pt); |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 405 | if (ret) |
Mika Kuoppala | 44159dd | 2015-06-25 18:35:07 +0300 | [diff] [blame] | 406 | goto fail_page_m; |
Ben Widawsky | 06fda60 | 2015-02-24 16:22:36 +0000 | [diff] [blame] | 407 | |
| 408 | return pt; |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 409 | |
Mika Kuoppala | 44159dd | 2015-06-25 18:35:07 +0300 | [diff] [blame] | 410 | fail_page_m: |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 411 | kfree(pt->used_ptes); |
| 412 | fail_bitmap: |
| 413 | kfree(pt); |
| 414 | |
| 415 | return ERR_PTR(ret); |
Ben Widawsky | 06fda60 | 2015-02-24 16:22:36 +0000 | [diff] [blame] | 416 | } |
| 417 | |
Mika Kuoppala | 2e906be | 2015-06-30 18:16:37 +0300 | [diff] [blame^] | 418 | static void free_pt(struct drm_device *dev, struct i915_page_table *pt) |
Ben Widawsky | 06fda60 | 2015-02-24 16:22:36 +0000 | [diff] [blame] | 419 | { |
Mika Kuoppala | 2e906be | 2015-06-30 18:16:37 +0300 | [diff] [blame^] | 420 | cleanup_px(dev, pt); |
| 421 | kfree(pt->used_ptes); |
| 422 | kfree(pt); |
| 423 | } |
| 424 | |
| 425 | static void gen8_initialize_pt(struct i915_address_space *vm, |
| 426 | struct i915_page_table *pt) |
| 427 | { |
| 428 | gen8_pte_t scratch_pte; |
| 429 | |
| 430 | scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page), |
| 431 | I915_CACHE_LLC, true); |
| 432 | |
| 433 | fill_px(vm->dev, pt, scratch_pte); |
| 434 | } |
| 435 | |
| 436 | static void gen6_initialize_pt(struct i915_address_space *vm, |
| 437 | struct i915_page_table *pt) |
| 438 | { |
| 439 | gen6_pte_t scratch_pte; |
| 440 | |
| 441 | WARN_ON(px_dma(vm->scratch_page) == 0); |
| 442 | |
| 443 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), |
| 444 | I915_CACHE_LLC, true, 0); |
| 445 | |
| 446 | fill32_px(vm->dev, pt, scratch_pte); |
Ben Widawsky | 06fda60 | 2015-02-24 16:22:36 +0000 | [diff] [blame] | 447 | } |
| 448 | |
Mika Kuoppala | 8a1ebd7 | 2015-05-22 20:04:59 +0300 | [diff] [blame] | 449 | static struct i915_page_directory *alloc_pd(struct drm_device *dev) |
Ben Widawsky | 06fda60 | 2015-02-24 16:22:36 +0000 | [diff] [blame] | 450 | { |
Michel Thierry | ec565b3 | 2015-04-08 12:13:23 +0100 | [diff] [blame] | 451 | struct i915_page_directory *pd; |
Michel Thierry | 33c8819 | 2015-04-08 12:13:33 +0100 | [diff] [blame] | 452 | int ret = -ENOMEM; |
Ben Widawsky | 06fda60 | 2015-02-24 16:22:36 +0000 | [diff] [blame] | 453 | |
| 454 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); |
| 455 | if (!pd) |
| 456 | return ERR_PTR(-ENOMEM); |
| 457 | |
Michel Thierry | 33c8819 | 2015-04-08 12:13:33 +0100 | [diff] [blame] | 458 | pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES), |
| 459 | sizeof(*pd->used_pdes), GFP_KERNEL); |
| 460 | if (!pd->used_pdes) |
Mika Kuoppala | a08e111 | 2015-06-25 18:35:08 +0300 | [diff] [blame] | 461 | goto fail_bitmap; |
Michel Thierry | 33c8819 | 2015-04-08 12:13:33 +0100 | [diff] [blame] | 462 | |
Mika Kuoppala | 567047b | 2015-06-25 18:35:12 +0300 | [diff] [blame] | 463 | ret = setup_px(dev, pd); |
Michel Thierry | 33c8819 | 2015-04-08 12:13:33 +0100 | [diff] [blame] | 464 | if (ret) |
Mika Kuoppala | a08e111 | 2015-06-25 18:35:08 +0300 | [diff] [blame] | 465 | goto fail_page_m; |
Michel Thierry | e5815a2 | 2015-04-08 12:13:32 +0100 | [diff] [blame] | 466 | |
Ben Widawsky | 06fda60 | 2015-02-24 16:22:36 +0000 | [diff] [blame] | 467 | return pd; |
Michel Thierry | 33c8819 | 2015-04-08 12:13:33 +0100 | [diff] [blame] | 468 | |
Mika Kuoppala | a08e111 | 2015-06-25 18:35:08 +0300 | [diff] [blame] | 469 | fail_page_m: |
Michel Thierry | 33c8819 | 2015-04-08 12:13:33 +0100 | [diff] [blame] | 470 | kfree(pd->used_pdes); |
Mika Kuoppala | a08e111 | 2015-06-25 18:35:08 +0300 | [diff] [blame] | 471 | fail_bitmap: |
Michel Thierry | 33c8819 | 2015-04-08 12:13:33 +0100 | [diff] [blame] | 472 | kfree(pd); |
| 473 | |
| 474 | return ERR_PTR(ret); |
Ben Widawsky | 06fda60 | 2015-02-24 16:22:36 +0000 | [diff] [blame] | 475 | } |
| 476 | |
Mika Kuoppala | 2e906be | 2015-06-30 18:16:37 +0300 | [diff] [blame^] | 477 | static void free_pd(struct drm_device *dev, struct i915_page_directory *pd) |
| 478 | { |
| 479 | if (px_page(pd)) { |
| 480 | cleanup_px(dev, pd); |
| 481 | kfree(pd->used_pdes); |
| 482 | kfree(pd); |
| 483 | } |
| 484 | } |
| 485 | |
| 486 | static void gen8_initialize_pd(struct i915_address_space *vm, |
| 487 | struct i915_page_directory *pd) |
| 488 | { |
| 489 | gen8_pde_t scratch_pde; |
| 490 | |
| 491 | scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC); |
| 492 | |
| 493 | fill_px(vm->dev, pd, scratch_pde); |
| 494 | } |
| 495 | |
| 496 | static int alloc_scratch_page(struct i915_address_space *vm) |
| 497 | { |
| 498 | struct i915_page_scratch *sp; |
| 499 | int ret; |
| 500 | |
| 501 | WARN_ON(vm->scratch_page); |
| 502 | |
| 503 | sp = kzalloc(sizeof(*sp), GFP_KERNEL); |
| 504 | if (sp == NULL) |
| 505 | return -ENOMEM; |
| 506 | |
| 507 | ret = __setup_page_dma(vm->dev, px_base(sp), GFP_DMA32 | __GFP_ZERO); |
| 508 | if (ret) { |
| 509 | kfree(sp); |
| 510 | return ret; |
| 511 | } |
| 512 | |
| 513 | set_pages_uc(px_page(sp), 1); |
| 514 | |
| 515 | vm->scratch_page = sp; |
| 516 | |
| 517 | return 0; |
| 518 | } |
| 519 | |
| 520 | static void free_scratch_page(struct i915_address_space *vm) |
| 521 | { |
| 522 | struct i915_page_scratch *sp = vm->scratch_page; |
| 523 | |
| 524 | set_pages_wb(px_page(sp), 1); |
| 525 | |
| 526 | cleanup_px(vm->dev, sp); |
| 527 | kfree(sp); |
| 528 | |
| 529 | vm->scratch_page = NULL; |
| 530 | } |
| 531 | |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 532 | /* Broadwell Page Directory Pointer Descriptors */ |
John Harrison | e85b26d | 2015-05-29 17:43:56 +0100 | [diff] [blame] | 533 | static int gen8_write_pdp(struct drm_i915_gem_request *req, |
Michel Thierry | 7cb6d7a | 2015-04-08 12:13:29 +0100 | [diff] [blame] | 534 | unsigned entry, |
| 535 | dma_addr_t addr) |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 536 | { |
John Harrison | e85b26d | 2015-05-29 17:43:56 +0100 | [diff] [blame] | 537 | struct intel_engine_cs *ring = req->ring; |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 538 | int ret; |
| 539 | |
| 540 | BUG_ON(entry >= 4); |
| 541 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 542 | ret = intel_ring_begin(req, 6); |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 543 | if (ret) |
| 544 | return ret; |
| 545 | |
| 546 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 547 | intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); |
Michel Thierry | 7cb6d7a | 2015-04-08 12:13:29 +0100 | [diff] [blame] | 548 | intel_ring_emit(ring, upper_32_bits(addr)); |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 549 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
| 550 | intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); |
Michel Thierry | 7cb6d7a | 2015-04-08 12:13:29 +0100 | [diff] [blame] | 551 | intel_ring_emit(ring, lower_32_bits(addr)); |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 552 | intel_ring_advance(ring); |
| 553 | |
| 554 | return 0; |
| 555 | } |
| 556 | |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 557 | static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, |
John Harrison | e85b26d | 2015-05-29 17:43:56 +0100 | [diff] [blame] | 558 | struct drm_i915_gem_request *req) |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 559 | { |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 560 | int i, ret; |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 561 | |
Michel Thierry | 7cb6d7a | 2015-04-08 12:13:29 +0100 | [diff] [blame] | 562 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
Mika Kuoppala | d852c7b | 2015-06-25 18:35:06 +0300 | [diff] [blame] | 563 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
| 564 | |
John Harrison | e85b26d | 2015-05-29 17:43:56 +0100 | [diff] [blame] | 565 | ret = gen8_write_pdp(req, i, pd_daddr); |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 566 | if (ret) |
| 567 | return ret; |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 568 | } |
Ben Widawsky | d595bd4 | 2013-11-25 09:54:32 -0800 | [diff] [blame] | 569 | |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 570 | return 0; |
Ben Widawsky | 94e409c | 2013-11-04 22:29:36 -0800 | [diff] [blame] | 571 | } |
| 572 | |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 573 | static void gen8_ppgtt_clear_range(struct i915_address_space *vm, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 574 | uint64_t start, |
| 575 | uint64_t length, |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 576 | bool use_scratch) |
| 577 | { |
| 578 | struct i915_hw_ppgtt *ppgtt = |
| 579 | container_of(vm, struct i915_hw_ppgtt, base); |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 580 | gen8_pte_t *pt_vaddr, scratch_pte; |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 581 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
| 582 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; |
| 583 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 584 | unsigned num_entries = length >> PAGE_SHIFT; |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 585 | unsigned last_pte, i; |
| 586 | |
Mika Kuoppala | c114f76 | 2015-06-25 18:35:13 +0300 | [diff] [blame] | 587 | scratch_pte = gen8_pte_encode(px_dma(ppgtt->base.scratch_page), |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 588 | I915_CACHE_LLC, use_scratch); |
| 589 | |
| 590 | while (num_entries) { |
Michel Thierry | ec565b3 | 2015-04-08 12:13:23 +0100 | [diff] [blame] | 591 | struct i915_page_directory *pd; |
| 592 | struct i915_page_table *pt; |
Ben Widawsky | 06fda60 | 2015-02-24 16:22:36 +0000 | [diff] [blame] | 593 | |
| 594 | if (WARN_ON(!ppgtt->pdp.page_directory[pdpe])) |
| 595 | continue; |
| 596 | |
| 597 | pd = ppgtt->pdp.page_directory[pdpe]; |
| 598 | |
| 599 | if (WARN_ON(!pd->page_table[pde])) |
| 600 | continue; |
| 601 | |
| 602 | pt = pd->page_table[pde]; |
| 603 | |
Mika Kuoppala | 567047b | 2015-06-25 18:35:12 +0300 | [diff] [blame] | 604 | if (WARN_ON(!px_page(pt))) |
Ben Widawsky | 06fda60 | 2015-02-24 16:22:36 +0000 | [diff] [blame] | 605 | continue; |
| 606 | |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 607 | last_pte = pte + num_entries; |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 608 | if (last_pte > GEN8_PTES) |
| 609 | last_pte = GEN8_PTES; |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 610 | |
Mika Kuoppala | d1c54ac | 2015-06-25 18:35:11 +0300 | [diff] [blame] | 611 | pt_vaddr = kmap_px(pt); |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 612 | |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 613 | for (i = pte; i < last_pte; i++) { |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 614 | pt_vaddr[i] = scratch_pte; |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 615 | num_entries--; |
| 616 | } |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 617 | |
Mika Kuoppala | d1c54ac | 2015-06-25 18:35:11 +0300 | [diff] [blame] | 618 | kunmap_px(ppgtt, pt); |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 619 | |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 620 | pte = 0; |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 621 | if (++pde == I915_PDES) { |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 622 | pdpe++; |
| 623 | pde = 0; |
| 624 | } |
Ben Widawsky | 459108b | 2013-11-02 21:07:23 -0700 | [diff] [blame] | 625 | } |
| 626 | } |
| 627 | |
Ben Widawsky | 9df15b4 | 2013-11-02 21:07:24 -0700 | [diff] [blame] | 628 | static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, |
| 629 | struct sg_table *pages, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 630 | uint64_t start, |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 631 | enum i915_cache_level cache_level, u32 unused) |
Ben Widawsky | 9df15b4 | 2013-11-02 21:07:24 -0700 | [diff] [blame] | 632 | { |
| 633 | struct i915_hw_ppgtt *ppgtt = |
| 634 | container_of(vm, struct i915_hw_ppgtt, base); |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 635 | gen8_pte_t *pt_vaddr; |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 636 | unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; |
| 637 | unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; |
| 638 | unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; |
Ben Widawsky | 9df15b4 | 2013-11-02 21:07:24 -0700 | [diff] [blame] | 639 | struct sg_page_iter sg_iter; |
| 640 | |
Chris Wilson | 6f1cc99 | 2013-12-31 15:50:31 +0000 | [diff] [blame] | 641 | pt_vaddr = NULL; |
Ben Widawsky | 9df15b4 | 2013-11-02 21:07:24 -0700 | [diff] [blame] | 642 | |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 643 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
Ben Widawsky | 7664360 | 2015-01-22 17:01:24 +0000 | [diff] [blame] | 644 | if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES)) |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 645 | break; |
| 646 | |
Ben Widawsky | d7b3de9 | 2015-02-24 16:22:34 +0000 | [diff] [blame] | 647 | if (pt_vaddr == NULL) { |
Michel Thierry | ec565b3 | 2015-04-08 12:13:23 +0100 | [diff] [blame] | 648 | struct i915_page_directory *pd = ppgtt->pdp.page_directory[pdpe]; |
| 649 | struct i915_page_table *pt = pd->page_table[pde]; |
Mika Kuoppala | d1c54ac | 2015-06-25 18:35:11 +0300 | [diff] [blame] | 650 | pt_vaddr = kmap_px(pt); |
Ben Widawsky | d7b3de9 | 2015-02-24 16:22:34 +0000 | [diff] [blame] | 651 | } |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 652 | |
| 653 | pt_vaddr[pte] = |
Chris Wilson | 6f1cc99 | 2013-12-31 15:50:31 +0000 | [diff] [blame] | 654 | gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), |
| 655 | cache_level, true); |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 656 | if (++pte == GEN8_PTES) { |
Mika Kuoppala | d1c54ac | 2015-06-25 18:35:11 +0300 | [diff] [blame] | 657 | kunmap_px(ppgtt, pt_vaddr); |
Chris Wilson | 6f1cc99 | 2013-12-31 15:50:31 +0000 | [diff] [blame] | 658 | pt_vaddr = NULL; |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 659 | if (++pde == I915_PDES) { |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 660 | pdpe++; |
| 661 | pde = 0; |
| 662 | } |
| 663 | pte = 0; |
Ben Widawsky | 9df15b4 | 2013-11-02 21:07:24 -0700 | [diff] [blame] | 664 | } |
| 665 | } |
Mika Kuoppala | d1c54ac | 2015-06-25 18:35:11 +0300 | [diff] [blame] | 666 | |
| 667 | if (pt_vaddr) |
| 668 | kunmap_px(ppgtt, pt_vaddr); |
Ben Widawsky | 9df15b4 | 2013-11-02 21:07:24 -0700 | [diff] [blame] | 669 | } |
| 670 | |
Michel Thierry | f37c050 | 2015-06-10 17:46:39 +0100 | [diff] [blame] | 671 | static void gen8_free_page_tables(struct drm_device *dev, |
| 672 | struct i915_page_directory *pd) |
Ben Widawsky | b45a671 | 2014-02-12 14:28:44 -0800 | [diff] [blame] | 673 | { |
| 674 | int i; |
| 675 | |
Mika Kuoppala | 567047b | 2015-06-25 18:35:12 +0300 | [diff] [blame] | 676 | if (!px_page(pd)) |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 677 | return; |
Ben Widawsky | b45a671 | 2014-02-12 14:28:44 -0800 | [diff] [blame] | 678 | |
Michel Thierry | 33c8819 | 2015-04-08 12:13:33 +0100 | [diff] [blame] | 679 | for_each_set_bit(i, pd->used_pdes, I915_PDES) { |
Ben Widawsky | 06fda60 | 2015-02-24 16:22:36 +0000 | [diff] [blame] | 680 | if (WARN_ON(!pd->page_table[i])) |
| 681 | continue; |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 682 | |
Mika Kuoppala | a08e111 | 2015-06-25 18:35:08 +0300 | [diff] [blame] | 683 | free_pt(dev, pd->page_table[i]); |
Ben Widawsky | 06fda60 | 2015-02-24 16:22:36 +0000 | [diff] [blame] | 684 | pd->page_table[i] = NULL; |
| 685 | } |
Ben Widawsky | d7b3de9 | 2015-02-24 16:22:34 +0000 | [diff] [blame] | 686 | } |
| 687 | |
Daniel Vetter | 061dd49 | 2015-04-14 17:35:13 +0200 | [diff] [blame] | 688 | static void gen8_ppgtt_cleanup(struct i915_address_space *vm) |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 689 | { |
Daniel Vetter | 061dd49 | 2015-04-14 17:35:13 +0200 | [diff] [blame] | 690 | struct i915_hw_ppgtt *ppgtt = |
| 691 | container_of(vm, struct i915_hw_ppgtt, base); |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 692 | int i; |
| 693 | |
Michel Thierry | 33c8819 | 2015-04-08 12:13:33 +0100 | [diff] [blame] | 694 | for_each_set_bit(i, ppgtt->pdp.used_pdpes, GEN8_LEGACY_PDPES) { |
Ben Widawsky | 06fda60 | 2015-02-24 16:22:36 +0000 | [diff] [blame] | 695 | if (WARN_ON(!ppgtt->pdp.page_directory[i])) |
| 696 | continue; |
| 697 | |
Michel Thierry | f37c050 | 2015-06-10 17:46:39 +0100 | [diff] [blame] | 698 | gen8_free_page_tables(ppgtt->base.dev, |
| 699 | ppgtt->pdp.page_directory[i]); |
Mika Kuoppala | a08e111 | 2015-06-25 18:35:08 +0300 | [diff] [blame] | 700 | free_pd(ppgtt->base.dev, ppgtt->pdp.page_directory[i]); |
Ben Widawsky | 7ad47cf | 2014-02-20 11:51:21 -0800 | [diff] [blame] | 701 | } |
Michel Thierry | 69876be | 2015-04-08 12:13:27 +0100 | [diff] [blame] | 702 | |
Mika Kuoppala | 79ab937 | 2015-06-25 18:35:17 +0300 | [diff] [blame] | 703 | free_pd(vm->dev, vm->scratch_pd); |
| 704 | free_pt(vm->dev, vm->scratch_pt); |
Ben Widawsky | b45a671 | 2014-02-12 14:28:44 -0800 | [diff] [blame] | 705 | } |
| 706 | |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 707 | /** |
| 708 | * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range. |
| 709 | * @ppgtt: Master ppgtt structure. |
| 710 | * @pd: Page directory for this address range. |
| 711 | * @start: Starting virtual address to begin allocations. |
| 712 | * @length Size of the allocations. |
| 713 | * @new_pts: Bitmap set by function with new allocations. Likely used by the |
| 714 | * caller to free on error. |
| 715 | * |
| 716 | * Allocate the required number of page tables. Extremely similar to |
| 717 | * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by |
| 718 | * the page directory boundary (instead of the page directory pointer). That |
| 719 | * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is |
| 720 | * possible, and likely that the caller will need to use multiple calls of this |
| 721 | * function to achieve the appropriate allocation. |
| 722 | * |
| 723 | * Return: 0 if success; negative error code otherwise. |
| 724 | */ |
Michel Thierry | e5815a2 | 2015-04-08 12:13:32 +0100 | [diff] [blame] | 725 | static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt *ppgtt, |
| 726 | struct i915_page_directory *pd, |
Michel Thierry | 5441f0c | 2015-04-08 12:13:28 +0100 | [diff] [blame] | 727 | uint64_t start, |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 728 | uint64_t length, |
| 729 | unsigned long *new_pts) |
Ben Widawsky | d7b3de9 | 2015-02-24 16:22:34 +0000 | [diff] [blame] | 730 | { |
Michel Thierry | e5815a2 | 2015-04-08 12:13:32 +0100 | [diff] [blame] | 731 | struct drm_device *dev = ppgtt->base.dev; |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 732 | struct i915_page_table *pt; |
Michel Thierry | 5441f0c | 2015-04-08 12:13:28 +0100 | [diff] [blame] | 733 | uint64_t temp; |
| 734 | uint32_t pde; |
Ben Widawsky | d7b3de9 | 2015-02-24 16:22:34 +0000 | [diff] [blame] | 735 | |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 736 | gen8_for_each_pde(pt, pd, start, length, temp, pde) { |
| 737 | /* Don't reallocate page tables */ |
| 738 | if (pt) { |
| 739 | /* Scratch is never allocated this way */ |
Mika Kuoppala | 79ab937 | 2015-06-25 18:35:17 +0300 | [diff] [blame] | 740 | WARN_ON(pt == ppgtt->base.scratch_pt); |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 741 | continue; |
| 742 | } |
| 743 | |
Mika Kuoppala | 8a1ebd7 | 2015-05-22 20:04:59 +0300 | [diff] [blame] | 744 | pt = alloc_pt(dev); |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 745 | if (IS_ERR(pt)) |
Ben Widawsky | 06fda60 | 2015-02-24 16:22:36 +0000 | [diff] [blame] | 746 | goto unwind_out; |
Michel Thierry | 5441f0c | 2015-04-08 12:13:28 +0100 | [diff] [blame] | 747 | |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 748 | gen8_initialize_pt(&ppgtt->base, pt); |
| 749 | pd->page_table[pde] = pt; |
Mika Kuoppala | 966082c | 2015-06-25 18:35:19 +0300 | [diff] [blame] | 750 | __set_bit(pde, new_pts); |
Ben Widawsky | d7b3de9 | 2015-02-24 16:22:34 +0000 | [diff] [blame] | 751 | } |
| 752 | |
| 753 | return 0; |
| 754 | |
| 755 | unwind_out: |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 756 | for_each_set_bit(pde, new_pts, I915_PDES) |
Mika Kuoppala | a08e111 | 2015-06-25 18:35:08 +0300 | [diff] [blame] | 757 | free_pt(dev, pd->page_table[pde]); |
Ben Widawsky | d7b3de9 | 2015-02-24 16:22:34 +0000 | [diff] [blame] | 758 | |
| 759 | return -ENOMEM; |
| 760 | } |
| 761 | |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 762 | /** |
| 763 | * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range. |
| 764 | * @ppgtt: Master ppgtt structure. |
| 765 | * @pdp: Page directory pointer for this address range. |
| 766 | * @start: Starting virtual address to begin allocations. |
| 767 | * @length Size of the allocations. |
| 768 | * @new_pds Bitmap set by function with new allocations. Likely used by the |
| 769 | * caller to free on error. |
| 770 | * |
| 771 | * Allocate the required number of page directories starting at the pde index of |
| 772 | * @start, and ending at the pde index @start + @length. This function will skip |
| 773 | * over already allocated page directories within the range, and only allocate |
| 774 | * new ones, setting the appropriate pointer within the pdp as well as the |
| 775 | * correct position in the bitmap @new_pds. |
| 776 | * |
| 777 | * The function will only allocate the pages within the range for a give page |
| 778 | * directory pointer. In other words, if @start + @length straddles a virtually |
| 779 | * addressed PDP boundary (512GB for 4k pages), there will be more allocations |
| 780 | * required by the caller, This is not currently possible, and the BUG in the |
| 781 | * code will prevent it. |
| 782 | * |
| 783 | * Return: 0 if success; negative error code otherwise. |
| 784 | */ |
Michel Thierry | c488dbb | 2015-04-08 12:13:31 +0100 | [diff] [blame] | 785 | static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt, |
| 786 | struct i915_page_directory_pointer *pdp, |
Michel Thierry | 69876be | 2015-04-08 12:13:27 +0100 | [diff] [blame] | 787 | uint64_t start, |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 788 | uint64_t length, |
| 789 | unsigned long *new_pds) |
Ben Widawsky | bf2b4ed | 2014-02-19 22:05:43 -0800 | [diff] [blame] | 790 | { |
Michel Thierry | e5815a2 | 2015-04-08 12:13:32 +0100 | [diff] [blame] | 791 | struct drm_device *dev = ppgtt->base.dev; |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 792 | struct i915_page_directory *pd; |
Michel Thierry | 69876be | 2015-04-08 12:13:27 +0100 | [diff] [blame] | 793 | uint64_t temp; |
| 794 | uint32_t pdpe; |
Ben Widawsky | bf2b4ed | 2014-02-19 22:05:43 -0800 | [diff] [blame] | 795 | |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 796 | WARN_ON(!bitmap_empty(new_pds, GEN8_LEGACY_PDPES)); |
| 797 | |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 798 | gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) { |
| 799 | if (pd) |
| 800 | continue; |
Michel Thierry | 33c8819 | 2015-04-08 12:13:33 +0100 | [diff] [blame] | 801 | |
Mika Kuoppala | 8a1ebd7 | 2015-05-22 20:04:59 +0300 | [diff] [blame] | 802 | pd = alloc_pd(dev); |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 803 | if (IS_ERR(pd)) |
Ben Widawsky | d7b3de9 | 2015-02-24 16:22:34 +0000 | [diff] [blame] | 804 | goto unwind_out; |
Michel Thierry | 69876be | 2015-04-08 12:13:27 +0100 | [diff] [blame] | 805 | |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 806 | gen8_initialize_pd(&ppgtt->base, pd); |
| 807 | pdp->page_directory[pdpe] = pd; |
Mika Kuoppala | 966082c | 2015-06-25 18:35:19 +0300 | [diff] [blame] | 808 | __set_bit(pdpe, new_pds); |
Ben Widawsky | d7b3de9 | 2015-02-24 16:22:34 +0000 | [diff] [blame] | 809 | } |
| 810 | |
Ben Widawsky | bf2b4ed | 2014-02-19 22:05:43 -0800 | [diff] [blame] | 811 | return 0; |
Ben Widawsky | d7b3de9 | 2015-02-24 16:22:34 +0000 | [diff] [blame] | 812 | |
| 813 | unwind_out: |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 814 | for_each_set_bit(pdpe, new_pds, GEN8_LEGACY_PDPES) |
Mika Kuoppala | a08e111 | 2015-06-25 18:35:08 +0300 | [diff] [blame] | 815 | free_pd(dev, pdp->page_directory[pdpe]); |
Ben Widawsky | d7b3de9 | 2015-02-24 16:22:34 +0000 | [diff] [blame] | 816 | |
| 817 | return -ENOMEM; |
Ben Widawsky | bf2b4ed | 2014-02-19 22:05:43 -0800 | [diff] [blame] | 818 | } |
| 819 | |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 820 | static void |
| 821 | free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts) |
| 822 | { |
| 823 | int i; |
| 824 | |
| 825 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) |
| 826 | kfree(new_pts[i]); |
| 827 | kfree(new_pts); |
| 828 | kfree(new_pds); |
| 829 | } |
| 830 | |
| 831 | /* Fills in the page directory bitmap, and the array of page tables bitmap. Both |
| 832 | * of these are based on the number of PDPEs in the system. |
| 833 | */ |
| 834 | static |
| 835 | int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds, |
| 836 | unsigned long ***new_pts) |
| 837 | { |
| 838 | int i; |
| 839 | unsigned long *pds; |
| 840 | unsigned long **pts; |
| 841 | |
| 842 | pds = kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES), sizeof(unsigned long), GFP_KERNEL); |
| 843 | if (!pds) |
| 844 | return -ENOMEM; |
| 845 | |
| 846 | pts = kcalloc(GEN8_LEGACY_PDPES, sizeof(unsigned long *), GFP_KERNEL); |
| 847 | if (!pts) { |
| 848 | kfree(pds); |
| 849 | return -ENOMEM; |
| 850 | } |
| 851 | |
| 852 | for (i = 0; i < GEN8_LEGACY_PDPES; i++) { |
| 853 | pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES), |
| 854 | sizeof(unsigned long), GFP_KERNEL); |
| 855 | if (!pts[i]) |
| 856 | goto err_out; |
| 857 | } |
| 858 | |
| 859 | *new_pds = pds; |
| 860 | *new_pts = pts; |
| 861 | |
| 862 | return 0; |
| 863 | |
| 864 | err_out: |
| 865 | free_gen8_temp_bitmaps(pds, pts); |
| 866 | return -ENOMEM; |
| 867 | } |
| 868 | |
Mika Kuoppala | 5b7e4c9c | 2015-06-25 18:35:03 +0300 | [diff] [blame] | 869 | /* PDE TLBs are a pain to invalidate on GEN8+. When we modify |
| 870 | * the page table structures, we mark them dirty so that |
| 871 | * context switching/execlist queuing code takes extra steps |
| 872 | * to ensure that tlbs are flushed. |
| 873 | */ |
| 874 | static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) |
| 875 | { |
| 876 | ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask; |
| 877 | } |
| 878 | |
Michel Thierry | e5815a2 | 2015-04-08 12:13:32 +0100 | [diff] [blame] | 879 | static int gen8_alloc_va_range(struct i915_address_space *vm, |
| 880 | uint64_t start, |
| 881 | uint64_t length) |
Ben Widawsky | bf2b4ed | 2014-02-19 22:05:43 -0800 | [diff] [blame] | 882 | { |
Michel Thierry | e5815a2 | 2015-04-08 12:13:32 +0100 | [diff] [blame] | 883 | struct i915_hw_ppgtt *ppgtt = |
| 884 | container_of(vm, struct i915_hw_ppgtt, base); |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 885 | unsigned long *new_page_dirs, **new_page_tables; |
Michel Thierry | 5441f0c | 2015-04-08 12:13:28 +0100 | [diff] [blame] | 886 | struct i915_page_directory *pd; |
Michel Thierry | 33c8819 | 2015-04-08 12:13:33 +0100 | [diff] [blame] | 887 | const uint64_t orig_start = start; |
| 888 | const uint64_t orig_length = length; |
Michel Thierry | 5441f0c | 2015-04-08 12:13:28 +0100 | [diff] [blame] | 889 | uint64_t temp; |
| 890 | uint32_t pdpe; |
Ben Widawsky | bf2b4ed | 2014-02-19 22:05:43 -0800 | [diff] [blame] | 891 | int ret; |
| 892 | |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 893 | /* Wrap is never okay since we can only represent 48b, and we don't |
| 894 | * actually use the other side of the canonical address space. |
| 895 | */ |
| 896 | if (WARN_ON(start + length < start)) |
Mika Kuoppala | a05d80e | 2015-06-25 18:35:04 +0300 | [diff] [blame] | 897 | return -ENODEV; |
| 898 | |
| 899 | if (WARN_ON(start + length > ppgtt->base.total)) |
| 900 | return -ENODEV; |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 901 | |
| 902 | ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables); |
Ben Widawsky | bf2b4ed | 2014-02-19 22:05:43 -0800 | [diff] [blame] | 903 | if (ret) |
| 904 | return ret; |
| 905 | |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 906 | /* Do the allocations first so we can easily bail out */ |
| 907 | ret = gen8_ppgtt_alloc_page_directories(ppgtt, &ppgtt->pdp, start, length, |
| 908 | new_page_dirs); |
| 909 | if (ret) { |
| 910 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
| 911 | return ret; |
| 912 | } |
| 913 | |
| 914 | /* For every page directory referenced, allocate page tables */ |
Michel Thierry | 5441f0c | 2015-04-08 12:13:28 +0100 | [diff] [blame] | 915 | gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) { |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 916 | ret = gen8_ppgtt_alloc_pagetabs(ppgtt, pd, start, length, |
| 917 | new_page_tables[pdpe]); |
Michel Thierry | 5441f0c | 2015-04-08 12:13:28 +0100 | [diff] [blame] | 918 | if (ret) |
| 919 | goto err_out; |
Michel Thierry | 5441f0c | 2015-04-08 12:13:28 +0100 | [diff] [blame] | 920 | } |
| 921 | |
Michel Thierry | 33c8819 | 2015-04-08 12:13:33 +0100 | [diff] [blame] | 922 | start = orig_start; |
| 923 | length = orig_length; |
| 924 | |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 925 | /* Allocations have completed successfully, so set the bitmaps, and do |
| 926 | * the mappings. */ |
Michel Thierry | 33c8819 | 2015-04-08 12:13:33 +0100 | [diff] [blame] | 927 | gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) { |
Mika Kuoppala | d1c54ac | 2015-06-25 18:35:11 +0300 | [diff] [blame] | 928 | gen8_pde_t *const page_directory = kmap_px(pd); |
Michel Thierry | 33c8819 | 2015-04-08 12:13:33 +0100 | [diff] [blame] | 929 | struct i915_page_table *pt; |
| 930 | uint64_t pd_len = gen8_clamp_pd(start, length); |
| 931 | uint64_t pd_start = start; |
| 932 | uint32_t pde; |
| 933 | |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 934 | /* Every pd should be allocated, we just did that above. */ |
| 935 | WARN_ON(!pd); |
| 936 | |
| 937 | gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) { |
| 938 | /* Same reasoning as pd */ |
| 939 | WARN_ON(!pt); |
| 940 | WARN_ON(!pd_len); |
| 941 | WARN_ON(!gen8_pte_count(pd_start, pd_len)); |
| 942 | |
| 943 | /* Set our used ptes within the page table */ |
| 944 | bitmap_set(pt->used_ptes, |
| 945 | gen8_pte_index(pd_start), |
| 946 | gen8_pte_count(pd_start, pd_len)); |
| 947 | |
| 948 | /* Our pde is now pointing to the pagetable, pt */ |
Mika Kuoppala | 966082c | 2015-06-25 18:35:19 +0300 | [diff] [blame] | 949 | __set_bit(pde, pd->used_pdes); |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 950 | |
| 951 | /* Map the PDE to the page table */ |
Mika Kuoppala | fe36f55 | 2015-06-25 18:35:16 +0300 | [diff] [blame] | 952 | page_directory[pde] = gen8_pde_encode(px_dma(pt), |
| 953 | I915_CACHE_LLC); |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 954 | |
| 955 | /* NB: We haven't yet mapped ptes to pages. At this |
| 956 | * point we're still relying on insert_entries() */ |
Michel Thierry | 33c8819 | 2015-04-08 12:13:33 +0100 | [diff] [blame] | 957 | } |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 958 | |
Mika Kuoppala | d1c54ac | 2015-06-25 18:35:11 +0300 | [diff] [blame] | 959 | kunmap_px(ppgtt, page_directory); |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 960 | |
Mika Kuoppala | 966082c | 2015-06-25 18:35:19 +0300 | [diff] [blame] | 961 | __set_bit(pdpe, ppgtt->pdp.used_pdpes); |
Michel Thierry | 33c8819 | 2015-04-08 12:13:33 +0100 | [diff] [blame] | 962 | } |
| 963 | |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 964 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
Mika Kuoppala | 5b7e4c9c | 2015-06-25 18:35:03 +0300 | [diff] [blame] | 965 | mark_tlbs_dirty(ppgtt); |
Ben Widawsky | d7b3de9 | 2015-02-24 16:22:34 +0000 | [diff] [blame] | 966 | return 0; |
| 967 | |
| 968 | err_out: |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 969 | while (pdpe--) { |
| 970 | for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES) |
Mika Kuoppala | a08e111 | 2015-06-25 18:35:08 +0300 | [diff] [blame] | 971 | free_pt(vm->dev, ppgtt->pdp.page_directory[pdpe]->page_table[temp]); |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 972 | } |
| 973 | |
| 974 | for_each_set_bit(pdpe, new_page_dirs, GEN8_LEGACY_PDPES) |
Mika Kuoppala | a08e111 | 2015-06-25 18:35:08 +0300 | [diff] [blame] | 975 | free_pd(vm->dev, ppgtt->pdp.page_directory[pdpe]); |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 976 | |
| 977 | free_gen8_temp_bitmaps(new_page_dirs, new_page_tables); |
Mika Kuoppala | 5b7e4c9c | 2015-06-25 18:35:03 +0300 | [diff] [blame] | 978 | mark_tlbs_dirty(ppgtt); |
Ben Widawsky | bf2b4ed | 2014-02-19 22:05:43 -0800 | [diff] [blame] | 979 | return ret; |
| 980 | } |
| 981 | |
Daniel Vetter | eb0b44a | 2015-03-18 14:47:59 +0100 | [diff] [blame] | 982 | /* |
Ben Widawsky | f3a964b | 2014-02-19 22:05:42 -0800 | [diff] [blame] | 983 | * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers |
| 984 | * with a net effect resembling a 2-level page table in normal x86 terms. Each |
| 985 | * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address |
| 986 | * space. |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 987 | * |
Ben Widawsky | f3a964b | 2014-02-19 22:05:42 -0800 | [diff] [blame] | 988 | */ |
Daniel Vetter | 5c5f645 | 2015-04-14 17:35:14 +0200 | [diff] [blame] | 989 | static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
Ben Widawsky | 37aca44 | 2013-11-04 20:47:32 -0800 | [diff] [blame] | 990 | { |
Mika Kuoppala | 79ab937 | 2015-06-25 18:35:17 +0300 | [diff] [blame] | 991 | ppgtt->base.scratch_pt = alloc_pt(ppgtt->base.dev); |
| 992 | if (IS_ERR(ppgtt->base.scratch_pt)) |
| 993 | return PTR_ERR(ppgtt->base.scratch_pt); |
Michel Thierry | 69876be | 2015-04-08 12:13:27 +0100 | [diff] [blame] | 994 | |
Mika Kuoppala | 79ab937 | 2015-06-25 18:35:17 +0300 | [diff] [blame] | 995 | ppgtt->base.scratch_pd = alloc_pd(ppgtt->base.dev); |
| 996 | if (IS_ERR(ppgtt->base.scratch_pd)) |
| 997 | return PTR_ERR(ppgtt->base.scratch_pd); |
Michel Thierry | 7cb6d7a | 2015-04-08 12:13:29 +0100 | [diff] [blame] | 998 | |
Mika Kuoppala | 79ab937 | 2015-06-25 18:35:17 +0300 | [diff] [blame] | 999 | gen8_initialize_pt(&ppgtt->base, ppgtt->base.scratch_pt); |
| 1000 | gen8_initialize_pd(&ppgtt->base, ppgtt->base.scratch_pd); |
Michel Thierry | 69876be | 2015-04-08 12:13:27 +0100 | [diff] [blame] | 1001 | |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 1002 | ppgtt->base.start = 0; |
Daniel Vetter | 5c5f645 | 2015-04-14 17:35:14 +0200 | [diff] [blame] | 1003 | ppgtt->base.total = 1ULL << 32; |
Michel Thierry | 501fd70 | 2015-05-29 14:15:05 +0100 | [diff] [blame] | 1004 | if (IS_ENABLED(CONFIG_X86_32)) |
| 1005 | /* While we have a proliferation of size_t variables |
| 1006 | * we cannot represent the full ppgtt size on 32bit, |
| 1007 | * so limit it to the same size as the GGTT (currently |
| 1008 | * 2GiB). |
| 1009 | */ |
| 1010 | ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total; |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 1011 | ppgtt->base.cleanup = gen8_ppgtt_cleanup; |
Daniel Vetter | 5c5f645 | 2015-04-14 17:35:14 +0200 | [diff] [blame] | 1012 | ppgtt->base.allocate_va_range = gen8_alloc_va_range; |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 1013 | ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; |
Daniel Vetter | c7e16f2 | 2015-04-14 17:35:11 +0200 | [diff] [blame] | 1014 | ppgtt->base.clear_range = gen8_ppgtt_clear_range; |
Daniel Vetter | 777dc5b | 2015-04-14 17:35:12 +0200 | [diff] [blame] | 1015 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
| 1016 | ppgtt->base.bind_vma = ppgtt_bind_vma; |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 1017 | |
| 1018 | ppgtt->switch_mm = gen8_mm_switch; |
| 1019 | |
| 1020 | return 0; |
| 1021 | } |
| 1022 | |
Ben Widawsky | 87d60b6 | 2013-12-06 14:11:29 -0800 | [diff] [blame] | 1023 | static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) |
| 1024 | { |
Ben Widawsky | 87d60b6 | 2013-12-06 14:11:29 -0800 | [diff] [blame] | 1025 | struct i915_address_space *vm = &ppgtt->base; |
Michel Thierry | 09942c6 | 2015-04-08 12:13:30 +0100 | [diff] [blame] | 1026 | struct i915_page_table *unused; |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 1027 | gen6_pte_t scratch_pte; |
Ben Widawsky | 87d60b6 | 2013-12-06 14:11:29 -0800 | [diff] [blame] | 1028 | uint32_t pd_entry; |
Michel Thierry | 09942c6 | 2015-04-08 12:13:30 +0100 | [diff] [blame] | 1029 | uint32_t pte, pde, temp; |
| 1030 | uint32_t start = ppgtt->base.start, length = ppgtt->base.total; |
Ben Widawsky | 87d60b6 | 2013-12-06 14:11:29 -0800 | [diff] [blame] | 1031 | |
Mika Kuoppala | 79ab937 | 2015-06-25 18:35:17 +0300 | [diff] [blame] | 1032 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), |
| 1033 | I915_CACHE_LLC, true, 0); |
Ben Widawsky | 87d60b6 | 2013-12-06 14:11:29 -0800 | [diff] [blame] | 1034 | |
Michel Thierry | 09942c6 | 2015-04-08 12:13:30 +0100 | [diff] [blame] | 1035 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) { |
Ben Widawsky | 87d60b6 | 2013-12-06 14:11:29 -0800 | [diff] [blame] | 1036 | u32 expected; |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 1037 | gen6_pte_t *pt_vaddr; |
Mika Kuoppala | 567047b | 2015-06-25 18:35:12 +0300 | [diff] [blame] | 1038 | const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]); |
Michel Thierry | 09942c6 | 2015-04-08 12:13:30 +0100 | [diff] [blame] | 1039 | pd_entry = readl(ppgtt->pd_addr + pde); |
Ben Widawsky | 87d60b6 | 2013-12-06 14:11:29 -0800 | [diff] [blame] | 1040 | expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); |
| 1041 | |
| 1042 | if (pd_entry != expected) |
| 1043 | seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", |
| 1044 | pde, |
| 1045 | pd_entry, |
| 1046 | expected); |
| 1047 | seq_printf(m, "\tPDE: %x\n", pd_entry); |
| 1048 | |
Mika Kuoppala | d1c54ac | 2015-06-25 18:35:11 +0300 | [diff] [blame] | 1049 | pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]); |
| 1050 | |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 1051 | for (pte = 0; pte < GEN6_PTES; pte+=4) { |
Ben Widawsky | 87d60b6 | 2013-12-06 14:11:29 -0800 | [diff] [blame] | 1052 | unsigned long va = |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 1053 | (pde * PAGE_SIZE * GEN6_PTES) + |
Ben Widawsky | 87d60b6 | 2013-12-06 14:11:29 -0800 | [diff] [blame] | 1054 | (pte * PAGE_SIZE); |
| 1055 | int i; |
| 1056 | bool found = false; |
| 1057 | for (i = 0; i < 4; i++) |
| 1058 | if (pt_vaddr[pte + i] != scratch_pte) |
| 1059 | found = true; |
| 1060 | if (!found) |
| 1061 | continue; |
| 1062 | |
| 1063 | seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); |
| 1064 | for (i = 0; i < 4; i++) { |
| 1065 | if (pt_vaddr[pte + i] != scratch_pte) |
| 1066 | seq_printf(m, " %08x", pt_vaddr[pte + i]); |
| 1067 | else |
| 1068 | seq_puts(m, " SCRATCH "); |
| 1069 | } |
| 1070 | seq_puts(m, "\n"); |
| 1071 | } |
Mika Kuoppala | d1c54ac | 2015-06-25 18:35:11 +0300 | [diff] [blame] | 1072 | kunmap_px(ppgtt, pt_vaddr); |
Ben Widawsky | 87d60b6 | 2013-12-06 14:11:29 -0800 | [diff] [blame] | 1073 | } |
| 1074 | } |
| 1075 | |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 1076 | /* Write pde (index) from the page directory @pd to the page table @pt */ |
Michel Thierry | ec565b3 | 2015-04-08 12:13:23 +0100 | [diff] [blame] | 1077 | static void gen6_write_pde(struct i915_page_directory *pd, |
| 1078 | const int pde, struct i915_page_table *pt) |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 1079 | { |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 1080 | /* Caller needs to make sure the write completes if necessary */ |
| 1081 | struct i915_hw_ppgtt *ppgtt = |
| 1082 | container_of(pd, struct i915_hw_ppgtt, pd); |
| 1083 | u32 pd_entry; |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 1084 | |
Mika Kuoppala | 567047b | 2015-06-25 18:35:12 +0300 | [diff] [blame] | 1085 | pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt)); |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 1086 | pd_entry |= GEN6_PDE_VALID; |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 1087 | |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 1088 | writel(pd_entry, ppgtt->pd_addr + pde); |
| 1089 | } |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 1090 | |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 1091 | /* Write all the page tables found in the ppgtt structure to incrementing page |
| 1092 | * directories. */ |
| 1093 | static void gen6_write_page_range(struct drm_i915_private *dev_priv, |
Michel Thierry | ec565b3 | 2015-04-08 12:13:23 +0100 | [diff] [blame] | 1094 | struct i915_page_directory *pd, |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 1095 | uint32_t start, uint32_t length) |
| 1096 | { |
Michel Thierry | ec565b3 | 2015-04-08 12:13:23 +0100 | [diff] [blame] | 1097 | struct i915_page_table *pt; |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 1098 | uint32_t pde, temp; |
| 1099 | |
| 1100 | gen6_for_each_pde(pt, pd, start, length, temp, pde) |
| 1101 | gen6_write_pde(pd, pde, pt); |
| 1102 | |
| 1103 | /* Make sure write is complete before other code can use this page |
| 1104 | * table. Also require for WC mapped PTEs */ |
| 1105 | readl(dev_priv->gtt.gsm); |
Ben Widawsky | 3e30254 | 2013-04-23 23:15:32 -0700 | [diff] [blame] | 1106 | } |
| 1107 | |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 1108 | static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) |
Ben Widawsky | 3e30254 | 2013-04-23 23:15:32 -0700 | [diff] [blame] | 1109 | { |
Mika Kuoppala | 44159dd | 2015-06-25 18:35:07 +0300 | [diff] [blame] | 1110 | BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f); |
Ben Widawsky | 3e30254 | 2013-04-23 23:15:32 -0700 | [diff] [blame] | 1111 | |
Mika Kuoppala | 44159dd | 2015-06-25 18:35:07 +0300 | [diff] [blame] | 1112 | return (ppgtt->pd.base.ggtt_offset / 64) << 16; |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 1113 | } |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 1114 | |
Ben Widawsky | 90252e5 | 2013-12-06 14:11:12 -0800 | [diff] [blame] | 1115 | static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, |
John Harrison | e85b26d | 2015-05-29 17:43:56 +0100 | [diff] [blame] | 1116 | struct drm_i915_gem_request *req) |
Ben Widawsky | 90252e5 | 2013-12-06 14:11:12 -0800 | [diff] [blame] | 1117 | { |
John Harrison | e85b26d | 2015-05-29 17:43:56 +0100 | [diff] [blame] | 1118 | struct intel_engine_cs *ring = req->ring; |
Ben Widawsky | 90252e5 | 2013-12-06 14:11:12 -0800 | [diff] [blame] | 1119 | int ret; |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 1120 | |
Ben Widawsky | 90252e5 | 2013-12-06 14:11:12 -0800 | [diff] [blame] | 1121 | /* NB: TLBs must be flushed and invalidated before a switch */ |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 1122 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
Ben Widawsky | 90252e5 | 2013-12-06 14:11:12 -0800 | [diff] [blame] | 1123 | if (ret) |
| 1124 | return ret; |
| 1125 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1126 | ret = intel_ring_begin(req, 6); |
Ben Widawsky | 90252e5 | 2013-12-06 14:11:12 -0800 | [diff] [blame] | 1127 | if (ret) |
| 1128 | return ret; |
| 1129 | |
| 1130 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
| 1131 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); |
| 1132 | intel_ring_emit(ring, PP_DIR_DCLV_2G); |
| 1133 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); |
| 1134 | intel_ring_emit(ring, get_pd_offset(ppgtt)); |
| 1135 | intel_ring_emit(ring, MI_NOOP); |
| 1136 | intel_ring_advance(ring); |
| 1137 | |
| 1138 | return 0; |
| 1139 | } |
| 1140 | |
Yu Zhang | 71ba2d6 | 2015-02-10 19:05:54 +0800 | [diff] [blame] | 1141 | static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt, |
John Harrison | e85b26d | 2015-05-29 17:43:56 +0100 | [diff] [blame] | 1142 | struct drm_i915_gem_request *req) |
Yu Zhang | 71ba2d6 | 2015-02-10 19:05:54 +0800 | [diff] [blame] | 1143 | { |
John Harrison | e85b26d | 2015-05-29 17:43:56 +0100 | [diff] [blame] | 1144 | struct intel_engine_cs *ring = req->ring; |
Yu Zhang | 71ba2d6 | 2015-02-10 19:05:54 +0800 | [diff] [blame] | 1145 | struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev); |
| 1146 | |
| 1147 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
| 1148 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); |
| 1149 | return 0; |
| 1150 | } |
| 1151 | |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 1152 | static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, |
John Harrison | e85b26d | 2015-05-29 17:43:56 +0100 | [diff] [blame] | 1153 | struct drm_i915_gem_request *req) |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 1154 | { |
John Harrison | e85b26d | 2015-05-29 17:43:56 +0100 | [diff] [blame] | 1155 | struct intel_engine_cs *ring = req->ring; |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 1156 | int ret; |
| 1157 | |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 1158 | /* NB: TLBs must be flushed and invalidated before a switch */ |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 1159 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 1160 | if (ret) |
| 1161 | return ret; |
| 1162 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 1163 | ret = intel_ring_begin(req, 6); |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 1164 | if (ret) |
| 1165 | return ret; |
| 1166 | |
| 1167 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); |
| 1168 | intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); |
| 1169 | intel_ring_emit(ring, PP_DIR_DCLV_2G); |
| 1170 | intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); |
| 1171 | intel_ring_emit(ring, get_pd_offset(ppgtt)); |
| 1172 | intel_ring_emit(ring, MI_NOOP); |
| 1173 | intel_ring_advance(ring); |
| 1174 | |
Ben Widawsky | 90252e5 | 2013-12-06 14:11:12 -0800 | [diff] [blame] | 1175 | /* XXX: RCS is the only one to auto invalidate the TLBs? */ |
| 1176 | if (ring->id != RCS) { |
John Harrison | a84c3ae | 2015-05-29 17:43:57 +0100 | [diff] [blame] | 1177 | ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
Ben Widawsky | 90252e5 | 2013-12-06 14:11:12 -0800 | [diff] [blame] | 1178 | if (ret) |
| 1179 | return ret; |
| 1180 | } |
| 1181 | |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 1182 | return 0; |
| 1183 | } |
| 1184 | |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 1185 | static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, |
John Harrison | e85b26d | 2015-05-29 17:43:56 +0100 | [diff] [blame] | 1186 | struct drm_i915_gem_request *req) |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 1187 | { |
John Harrison | e85b26d | 2015-05-29 17:43:56 +0100 | [diff] [blame] | 1188 | struct intel_engine_cs *ring = req->ring; |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 1189 | struct drm_device *dev = ppgtt->base.dev; |
| 1190 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1191 | |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 1192 | |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 1193 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); |
| 1194 | I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); |
| 1195 | |
| 1196 | POSTING_READ(RING_PP_DIR_DCLV(ring)); |
| 1197 | |
| 1198 | return 0; |
| 1199 | } |
| 1200 | |
Daniel Vetter | 82460d9 | 2014-08-06 20:19:53 +0200 | [diff] [blame] | 1201 | static void gen8_ppgtt_enable(struct drm_device *dev) |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 1202 | { |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 1203 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1204 | struct intel_engine_cs *ring; |
Daniel Vetter | 82460d9 | 2014-08-06 20:19:53 +0200 | [diff] [blame] | 1205 | int j; |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 1206 | |
| 1207 | for_each_ring(ring, dev_priv, j) { |
| 1208 | I915_WRITE(RING_MODE_GEN7(ring), |
| 1209 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 1210 | } |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 1211 | } |
| 1212 | |
Daniel Vetter | 82460d9 | 2014-08-06 20:19:53 +0200 | [diff] [blame] | 1213 | static void gen7_ppgtt_enable(struct drm_device *dev) |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 1214 | { |
Jani Nikula | 50227e1 | 2014-03-31 14:27:21 +0300 | [diff] [blame] | 1215 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1216 | struct intel_engine_cs *ring; |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 1217 | uint32_t ecochk, ecobits; |
| 1218 | int i; |
| 1219 | |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 1220 | ecobits = I915_READ(GAC_ECO_BITS); |
| 1221 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); |
| 1222 | |
| 1223 | ecochk = I915_READ(GAM_ECOCHK); |
| 1224 | if (IS_HASWELL(dev)) { |
| 1225 | ecochk |= ECOCHK_PPGTT_WB_HSW; |
| 1226 | } else { |
| 1227 | ecochk |= ECOCHK_PPGTT_LLC_IVB; |
| 1228 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; |
| 1229 | } |
| 1230 | I915_WRITE(GAM_ECOCHK, ecochk); |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 1231 | |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 1232 | for_each_ring(ring, dev_priv, i) { |
Ben Widawsky | eeb9488 | 2013-12-06 14:11:10 -0800 | [diff] [blame] | 1233 | /* GFX_MODE is per-ring on gen7+ */ |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 1234 | I915_WRITE(RING_MODE_GEN7(ring), |
| 1235 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 1236 | } |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 1237 | } |
| 1238 | |
Daniel Vetter | 82460d9 | 2014-08-06 20:19:53 +0200 | [diff] [blame] | 1239 | static void gen6_ppgtt_enable(struct drm_device *dev) |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 1240 | { |
Jani Nikula | 50227e1 | 2014-03-31 14:27:21 +0300 | [diff] [blame] | 1241 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 1242 | uint32_t ecochk, gab_ctl, ecobits; |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 1243 | |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 1244 | ecobits = I915_READ(GAC_ECO_BITS); |
| 1245 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | |
| 1246 | ECOBITS_PPGTT_CACHE64B); |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 1247 | |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 1248 | gab_ctl = I915_READ(GAB_CTL); |
| 1249 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 1250 | |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 1251 | ecochk = I915_READ(GAM_ECOCHK); |
| 1252 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 1253 | |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 1254 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
Ben Widawsky | 6197349 | 2013-04-08 18:43:54 -0700 | [diff] [blame] | 1255 | } |
| 1256 | |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1257 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1258 | static void gen6_ppgtt_clear_range(struct i915_address_space *vm, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1259 | uint64_t start, |
| 1260 | uint64_t length, |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1261 | bool use_scratch) |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1262 | { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1263 | struct i915_hw_ppgtt *ppgtt = |
| 1264 | container_of(vm, struct i915_hw_ppgtt, base); |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 1265 | gen6_pte_t *pt_vaddr, scratch_pte; |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1266 | unsigned first_entry = start >> PAGE_SHIFT; |
| 1267 | unsigned num_entries = length >> PAGE_SHIFT; |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 1268 | unsigned act_pt = first_entry / GEN6_PTES; |
| 1269 | unsigned first_pte = first_entry % GEN6_PTES; |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 1270 | unsigned last_pte, i; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1271 | |
Mika Kuoppala | c114f76 | 2015-06-25 18:35:13 +0300 | [diff] [blame] | 1272 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), |
| 1273 | I915_CACHE_LLC, true, 0); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1274 | |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 1275 | while (num_entries) { |
| 1276 | last_pte = first_pte + num_entries; |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 1277 | if (last_pte > GEN6_PTES) |
| 1278 | last_pte = GEN6_PTES; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1279 | |
Mika Kuoppala | d1c54ac | 2015-06-25 18:35:11 +0300 | [diff] [blame] | 1280 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 1281 | |
| 1282 | for (i = first_pte; i < last_pte; i++) |
| 1283 | pt_vaddr[i] = scratch_pte; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1284 | |
Mika Kuoppala | d1c54ac | 2015-06-25 18:35:11 +0300 | [diff] [blame] | 1285 | kunmap_px(ppgtt, pt_vaddr); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1286 | |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 1287 | num_entries -= last_pte - first_pte; |
| 1288 | first_pte = 0; |
Daniel Vetter | a15326a | 2013-03-19 23:48:39 +0100 | [diff] [blame] | 1289 | act_pt++; |
Daniel Vetter | 7bddb01 | 2012-02-09 17:15:47 +0100 | [diff] [blame] | 1290 | } |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1291 | } |
| 1292 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1293 | static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, |
Daniel Vetter | def886c | 2013-01-24 14:44:56 -0800 | [diff] [blame] | 1294 | struct sg_table *pages, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1295 | uint64_t start, |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 1296 | enum i915_cache_level cache_level, u32 flags) |
Daniel Vetter | def886c | 2013-01-24 14:44:56 -0800 | [diff] [blame] | 1297 | { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1298 | struct i915_hw_ppgtt *ppgtt = |
| 1299 | container_of(vm, struct i915_hw_ppgtt, base); |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 1300 | gen6_pte_t *pt_vaddr; |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1301 | unsigned first_entry = start >> PAGE_SHIFT; |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 1302 | unsigned act_pt = first_entry / GEN6_PTES; |
| 1303 | unsigned act_pte = first_entry % GEN6_PTES; |
Imre Deak | 6e995e2 | 2013-02-18 19:28:04 +0200 | [diff] [blame] | 1304 | struct sg_page_iter sg_iter; |
Daniel Vetter | def886c | 2013-01-24 14:44:56 -0800 | [diff] [blame] | 1305 | |
Chris Wilson | cc79714 | 2013-12-31 15:50:30 +0000 | [diff] [blame] | 1306 | pt_vaddr = NULL; |
Imre Deak | 6e995e2 | 2013-02-18 19:28:04 +0200 | [diff] [blame] | 1307 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
Chris Wilson | cc79714 | 2013-12-31 15:50:30 +0000 | [diff] [blame] | 1308 | if (pt_vaddr == NULL) |
Mika Kuoppala | d1c54ac | 2015-06-25 18:35:11 +0300 | [diff] [blame] | 1309 | pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]); |
Daniel Vetter | def886c | 2013-01-24 14:44:56 -0800 | [diff] [blame] | 1310 | |
Chris Wilson | cc79714 | 2013-12-31 15:50:30 +0000 | [diff] [blame] | 1311 | pt_vaddr[act_pte] = |
| 1312 | vm->pte_encode(sg_page_iter_dma_address(&sg_iter), |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 1313 | cache_level, true, flags); |
| 1314 | |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 1315 | if (++act_pte == GEN6_PTES) { |
Mika Kuoppala | d1c54ac | 2015-06-25 18:35:11 +0300 | [diff] [blame] | 1316 | kunmap_px(ppgtt, pt_vaddr); |
Chris Wilson | cc79714 | 2013-12-31 15:50:30 +0000 | [diff] [blame] | 1317 | pt_vaddr = NULL; |
Daniel Vetter | a15326a | 2013-03-19 23:48:39 +0100 | [diff] [blame] | 1318 | act_pt++; |
Imre Deak | 6e995e2 | 2013-02-18 19:28:04 +0200 | [diff] [blame] | 1319 | act_pte = 0; |
Daniel Vetter | def886c | 2013-01-24 14:44:56 -0800 | [diff] [blame] | 1320 | } |
Daniel Vetter | def886c | 2013-01-24 14:44:56 -0800 | [diff] [blame] | 1321 | } |
Chris Wilson | cc79714 | 2013-12-31 15:50:30 +0000 | [diff] [blame] | 1322 | if (pt_vaddr) |
Mika Kuoppala | d1c54ac | 2015-06-25 18:35:11 +0300 | [diff] [blame] | 1323 | kunmap_px(ppgtt, pt_vaddr); |
Daniel Vetter | def886c | 2013-01-24 14:44:56 -0800 | [diff] [blame] | 1324 | } |
| 1325 | |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 1326 | static int gen6_alloc_va_range(struct i915_address_space *vm, |
Mika Kuoppala | a05d80e | 2015-06-25 18:35:04 +0300 | [diff] [blame] | 1327 | uint64_t start_in, uint64_t length_in) |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 1328 | { |
Michel Thierry | 4933d51 | 2015-03-24 15:46:22 +0000 | [diff] [blame] | 1329 | DECLARE_BITMAP(new_page_tables, I915_PDES); |
| 1330 | struct drm_device *dev = vm->dev; |
| 1331 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 1332 | struct i915_hw_ppgtt *ppgtt = |
| 1333 | container_of(vm, struct i915_hw_ppgtt, base); |
Michel Thierry | ec565b3 | 2015-04-08 12:13:23 +0100 | [diff] [blame] | 1334 | struct i915_page_table *pt; |
Mika Kuoppala | a05d80e | 2015-06-25 18:35:04 +0300 | [diff] [blame] | 1335 | uint32_t start, length, start_save, length_save; |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 1336 | uint32_t pde, temp; |
Michel Thierry | 4933d51 | 2015-03-24 15:46:22 +0000 | [diff] [blame] | 1337 | int ret; |
| 1338 | |
Mika Kuoppala | a05d80e | 2015-06-25 18:35:04 +0300 | [diff] [blame] | 1339 | if (WARN_ON(start_in + length_in > ppgtt->base.total)) |
| 1340 | return -ENODEV; |
| 1341 | |
| 1342 | start = start_save = start_in; |
| 1343 | length = length_save = length_in; |
Michel Thierry | 4933d51 | 2015-03-24 15:46:22 +0000 | [diff] [blame] | 1344 | |
| 1345 | bitmap_zero(new_page_tables, I915_PDES); |
| 1346 | |
| 1347 | /* The allocation is done in two stages so that we can bail out with |
| 1348 | * minimal amount of pain. The first stage finds new page tables that |
| 1349 | * need allocation. The second stage marks use ptes within the page |
| 1350 | * tables. |
| 1351 | */ |
| 1352 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { |
Mika Kuoppala | 79ab937 | 2015-06-25 18:35:17 +0300 | [diff] [blame] | 1353 | if (pt != vm->scratch_pt) { |
Michel Thierry | 4933d51 | 2015-03-24 15:46:22 +0000 | [diff] [blame] | 1354 | WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES)); |
| 1355 | continue; |
| 1356 | } |
| 1357 | |
| 1358 | /* We've already allocated a page table */ |
| 1359 | WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES)); |
| 1360 | |
Mika Kuoppala | 8a1ebd7 | 2015-05-22 20:04:59 +0300 | [diff] [blame] | 1361 | pt = alloc_pt(dev); |
Michel Thierry | 4933d51 | 2015-03-24 15:46:22 +0000 | [diff] [blame] | 1362 | if (IS_ERR(pt)) { |
| 1363 | ret = PTR_ERR(pt); |
| 1364 | goto unwind_out; |
| 1365 | } |
| 1366 | |
| 1367 | gen6_initialize_pt(vm, pt); |
| 1368 | |
| 1369 | ppgtt->pd.page_table[pde] = pt; |
Mika Kuoppala | 966082c | 2015-06-25 18:35:19 +0300 | [diff] [blame] | 1370 | __set_bit(pde, new_page_tables); |
Michel Thierry | 72744cb | 2015-03-24 15:46:23 +0000 | [diff] [blame] | 1371 | trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT); |
Michel Thierry | 4933d51 | 2015-03-24 15:46:22 +0000 | [diff] [blame] | 1372 | } |
| 1373 | |
| 1374 | start = start_save; |
| 1375 | length = length_save; |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 1376 | |
| 1377 | gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { |
| 1378 | DECLARE_BITMAP(tmp_bitmap, GEN6_PTES); |
| 1379 | |
| 1380 | bitmap_zero(tmp_bitmap, GEN6_PTES); |
| 1381 | bitmap_set(tmp_bitmap, gen6_pte_index(start), |
| 1382 | gen6_pte_count(start, length)); |
| 1383 | |
Mika Kuoppala | 966082c | 2015-06-25 18:35:19 +0300 | [diff] [blame] | 1384 | if (__test_and_clear_bit(pde, new_page_tables)) |
Michel Thierry | 4933d51 | 2015-03-24 15:46:22 +0000 | [diff] [blame] | 1385 | gen6_write_pde(&ppgtt->pd, pde, pt); |
| 1386 | |
Michel Thierry | 72744cb | 2015-03-24 15:46:23 +0000 | [diff] [blame] | 1387 | trace_i915_page_table_entry_map(vm, pde, pt, |
| 1388 | gen6_pte_index(start), |
| 1389 | gen6_pte_count(start, length), |
| 1390 | GEN6_PTES); |
Michel Thierry | 4933d51 | 2015-03-24 15:46:22 +0000 | [diff] [blame] | 1391 | bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes, |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 1392 | GEN6_PTES); |
| 1393 | } |
| 1394 | |
Michel Thierry | 4933d51 | 2015-03-24 15:46:22 +0000 | [diff] [blame] | 1395 | WARN_ON(!bitmap_empty(new_page_tables, I915_PDES)); |
| 1396 | |
| 1397 | /* Make sure write is complete before other code can use this page |
| 1398 | * table. Also require for WC mapped PTEs */ |
| 1399 | readl(dev_priv->gtt.gsm); |
| 1400 | |
Ben Widawsky | 563222a | 2015-03-19 12:53:28 +0000 | [diff] [blame] | 1401 | mark_tlbs_dirty(ppgtt); |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 1402 | return 0; |
Michel Thierry | 4933d51 | 2015-03-24 15:46:22 +0000 | [diff] [blame] | 1403 | |
| 1404 | unwind_out: |
| 1405 | for_each_set_bit(pde, new_page_tables, I915_PDES) { |
Michel Thierry | ec565b3 | 2015-04-08 12:13:23 +0100 | [diff] [blame] | 1406 | struct i915_page_table *pt = ppgtt->pd.page_table[pde]; |
Michel Thierry | 4933d51 | 2015-03-24 15:46:22 +0000 | [diff] [blame] | 1407 | |
Mika Kuoppala | 79ab937 | 2015-06-25 18:35:17 +0300 | [diff] [blame] | 1408 | ppgtt->pd.page_table[pde] = vm->scratch_pt; |
Mika Kuoppala | a08e111 | 2015-06-25 18:35:08 +0300 | [diff] [blame] | 1409 | free_pt(vm->dev, pt); |
Michel Thierry | 4933d51 | 2015-03-24 15:46:22 +0000 | [diff] [blame] | 1410 | } |
| 1411 | |
| 1412 | mark_tlbs_dirty(ppgtt); |
| 1413 | return ret; |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 1414 | } |
| 1415 | |
Daniel Vetter | 061dd49 | 2015-04-14 17:35:13 +0200 | [diff] [blame] | 1416 | static void gen6_ppgtt_cleanup(struct i915_address_space *vm) |
Ben Widawsky | a00d825 | 2014-02-19 22:05:48 -0800 | [diff] [blame] | 1417 | { |
Daniel Vetter | 061dd49 | 2015-04-14 17:35:13 +0200 | [diff] [blame] | 1418 | struct i915_hw_ppgtt *ppgtt = |
| 1419 | container_of(vm, struct i915_hw_ppgtt, base); |
Michel Thierry | 09942c6 | 2015-04-08 12:13:30 +0100 | [diff] [blame] | 1420 | struct i915_page_table *pt; |
| 1421 | uint32_t pde; |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 1422 | |
Daniel Vetter | 061dd49 | 2015-04-14 17:35:13 +0200 | [diff] [blame] | 1423 | drm_mm_remove_node(&ppgtt->node); |
| 1424 | |
Michel Thierry | 09942c6 | 2015-04-08 12:13:30 +0100 | [diff] [blame] | 1425 | gen6_for_all_pdes(pt, ppgtt, pde) { |
Mika Kuoppala | 79ab937 | 2015-06-25 18:35:17 +0300 | [diff] [blame] | 1426 | if (pt != vm->scratch_pt) |
Mika Kuoppala | a08e111 | 2015-06-25 18:35:08 +0300 | [diff] [blame] | 1427 | free_pt(ppgtt->base.dev, pt); |
Michel Thierry | 4933d51 | 2015-03-24 15:46:22 +0000 | [diff] [blame] | 1428 | } |
| 1429 | |
Mika Kuoppala | 79ab937 | 2015-06-25 18:35:17 +0300 | [diff] [blame] | 1430 | free_pt(vm->dev, vm->scratch_pt); |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 1431 | } |
| 1432 | |
Ben Widawsky | b146520 | 2014-02-19 22:05:49 -0800 | [diff] [blame] | 1433 | static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 1434 | { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1435 | struct drm_device *dev = ppgtt->base.dev; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1436 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | e3cc199 | 2013-12-06 14:11:08 -0800 | [diff] [blame] | 1437 | bool retried = false; |
Ben Widawsky | b146520 | 2014-02-19 22:05:49 -0800 | [diff] [blame] | 1438 | int ret; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1439 | |
Ben Widawsky | c8d4c0d | 2013-12-06 14:11:07 -0800 | [diff] [blame] | 1440 | /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The |
| 1441 | * allocator works in address space sizes, so it's multiplied by page |
| 1442 | * size. We allocate at the top of the GTT to avoid fragmentation. |
| 1443 | */ |
| 1444 | BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); |
Mika Kuoppala | 79ab937 | 2015-06-25 18:35:17 +0300 | [diff] [blame] | 1445 | ppgtt->base.scratch_pt = alloc_pt(ppgtt->base.dev); |
| 1446 | if (IS_ERR(ppgtt->base.scratch_pt)) |
| 1447 | return PTR_ERR(ppgtt->base.scratch_pt); |
Michel Thierry | 4933d51 | 2015-03-24 15:46:22 +0000 | [diff] [blame] | 1448 | |
Mika Kuoppala | 79ab937 | 2015-06-25 18:35:17 +0300 | [diff] [blame] | 1449 | gen6_initialize_pt(&ppgtt->base, ppgtt->base.scratch_pt); |
Michel Thierry | 4933d51 | 2015-03-24 15:46:22 +0000 | [diff] [blame] | 1450 | |
Ben Widawsky | e3cc199 | 2013-12-06 14:11:08 -0800 | [diff] [blame] | 1451 | alloc: |
Ben Widawsky | c8d4c0d | 2013-12-06 14:11:07 -0800 | [diff] [blame] | 1452 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, |
| 1453 | &ppgtt->node, GEN6_PD_SIZE, |
| 1454 | GEN6_PD_ALIGN, 0, |
| 1455 | 0, dev_priv->gtt.base.total, |
Ben Widawsky | 3e8b5ae | 2014-05-06 22:21:30 -0700 | [diff] [blame] | 1456 | DRM_MM_TOPDOWN); |
Ben Widawsky | e3cc199 | 2013-12-06 14:11:08 -0800 | [diff] [blame] | 1457 | if (ret == -ENOSPC && !retried) { |
| 1458 | ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, |
| 1459 | GEN6_PD_SIZE, GEN6_PD_ALIGN, |
Chris Wilson | d23db88 | 2014-05-23 08:48:08 +0200 | [diff] [blame] | 1460 | I915_CACHE_NONE, |
| 1461 | 0, dev_priv->gtt.base.total, |
| 1462 | 0); |
Ben Widawsky | e3cc199 | 2013-12-06 14:11:08 -0800 | [diff] [blame] | 1463 | if (ret) |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 1464 | goto err_out; |
Ben Widawsky | e3cc199 | 2013-12-06 14:11:08 -0800 | [diff] [blame] | 1465 | |
| 1466 | retried = true; |
| 1467 | goto alloc; |
| 1468 | } |
Ben Widawsky | c8d4c0d | 2013-12-06 14:11:07 -0800 | [diff] [blame] | 1469 | |
Ben Widawsky | c8c2662 | 2015-01-22 17:01:25 +0000 | [diff] [blame] | 1470 | if (ret) |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 1471 | goto err_out; |
| 1472 | |
Ben Widawsky | c8c2662 | 2015-01-22 17:01:25 +0000 | [diff] [blame] | 1473 | |
Ben Widawsky | c8d4c0d | 2013-12-06 14:11:07 -0800 | [diff] [blame] | 1474 | if (ppgtt->node.start < dev_priv->gtt.mappable_end) |
| 1475 | DRM_DEBUG("Forced to use aperture for PDEs\n"); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1476 | |
Ben Widawsky | c8c2662 | 2015-01-22 17:01:25 +0000 | [diff] [blame] | 1477 | return 0; |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 1478 | |
| 1479 | err_out: |
Mika Kuoppala | 79ab937 | 2015-06-25 18:35:17 +0300 | [diff] [blame] | 1480 | free_pt(ppgtt->base.dev, ppgtt->base.scratch_pt); |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 1481 | return ret; |
Ben Widawsky | b146520 | 2014-02-19 22:05:49 -0800 | [diff] [blame] | 1482 | } |
| 1483 | |
Ben Widawsky | b146520 | 2014-02-19 22:05:49 -0800 | [diff] [blame] | 1484 | static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) |
| 1485 | { |
kbuild test robot | 2f2cf68 | 2015-03-27 19:26:35 +0800 | [diff] [blame] | 1486 | return gen6_ppgtt_allocate_page_directories(ppgtt); |
Ben Widawsky | b146520 | 2014-02-19 22:05:49 -0800 | [diff] [blame] | 1487 | } |
| 1488 | |
Michel Thierry | 4933d51 | 2015-03-24 15:46:22 +0000 | [diff] [blame] | 1489 | static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, |
| 1490 | uint64_t start, uint64_t length) |
| 1491 | { |
Michel Thierry | ec565b3 | 2015-04-08 12:13:23 +0100 | [diff] [blame] | 1492 | struct i915_page_table *unused; |
Michel Thierry | 4933d51 | 2015-03-24 15:46:22 +0000 | [diff] [blame] | 1493 | uint32_t pde, temp; |
| 1494 | |
| 1495 | gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) |
Mika Kuoppala | 79ab937 | 2015-06-25 18:35:17 +0300 | [diff] [blame] | 1496 | ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt; |
Michel Thierry | 4933d51 | 2015-03-24 15:46:22 +0000 | [diff] [blame] | 1497 | } |
| 1498 | |
Daniel Vetter | 5c5f645 | 2015-04-14 17:35:14 +0200 | [diff] [blame] | 1499 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) |
Ben Widawsky | b146520 | 2014-02-19 22:05:49 -0800 | [diff] [blame] | 1500 | { |
| 1501 | struct drm_device *dev = ppgtt->base.dev; |
| 1502 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1503 | int ret; |
| 1504 | |
| 1505 | ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 1506 | if (IS_GEN6(dev)) { |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 1507 | ppgtt->switch_mm = gen6_mm_switch; |
Ben Widawsky | 90252e5 | 2013-12-06 14:11:12 -0800 | [diff] [blame] | 1508 | } else if (IS_HASWELL(dev)) { |
Ben Widawsky | 90252e5 | 2013-12-06 14:11:12 -0800 | [diff] [blame] | 1509 | ppgtt->switch_mm = hsw_mm_switch; |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 1510 | } else if (IS_GEN7(dev)) { |
Ben Widawsky | 48a1038 | 2013-12-06 14:11:11 -0800 | [diff] [blame] | 1511 | ppgtt->switch_mm = gen7_mm_switch; |
| 1512 | } else |
Ben Widawsky | b4a74e3 | 2013-12-06 14:11:09 -0800 | [diff] [blame] | 1513 | BUG(); |
Ben Widawsky | b146520 | 2014-02-19 22:05:49 -0800 | [diff] [blame] | 1514 | |
Yu Zhang | 71ba2d6 | 2015-02-10 19:05:54 +0800 | [diff] [blame] | 1515 | if (intel_vgpu_active(dev)) |
| 1516 | ppgtt->switch_mm = vgpu_mm_switch; |
| 1517 | |
Ben Widawsky | b146520 | 2014-02-19 22:05:49 -0800 | [diff] [blame] | 1518 | ret = gen6_ppgtt_alloc(ppgtt); |
| 1519 | if (ret) |
| 1520 | return ret; |
| 1521 | |
Daniel Vetter | 5c5f645 | 2015-04-14 17:35:14 +0200 | [diff] [blame] | 1522 | ppgtt->base.allocate_va_range = gen6_alloc_va_range; |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1523 | ppgtt->base.clear_range = gen6_ppgtt_clear_range; |
| 1524 | ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; |
Daniel Vetter | 777dc5b | 2015-04-14 17:35:12 +0200 | [diff] [blame] | 1525 | ppgtt->base.unbind_vma = ppgtt_unbind_vma; |
| 1526 | ppgtt->base.bind_vma = ppgtt_bind_vma; |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1527 | ppgtt->base.cleanup = gen6_ppgtt_cleanup; |
Ben Widawsky | 686e1f6f | 2013-11-25 09:54:34 -0800 | [diff] [blame] | 1528 | ppgtt->base.start = 0; |
Michel Thierry | 09942c6 | 2015-04-08 12:13:30 +0100 | [diff] [blame] | 1529 | ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE; |
Ben Widawsky | b146520 | 2014-02-19 22:05:49 -0800 | [diff] [blame] | 1530 | ppgtt->debug_dump = gen6_dump_ppgtt; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1531 | |
Mika Kuoppala | 44159dd | 2015-06-25 18:35:07 +0300 | [diff] [blame] | 1532 | ppgtt->pd.base.ggtt_offset = |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 1533 | ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1534 | |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 1535 | ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm + |
Mika Kuoppala | 44159dd | 2015-06-25 18:35:07 +0300 | [diff] [blame] | 1536 | ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t); |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 1537 | |
Daniel Vetter | 5c5f645 | 2015-04-14 17:35:14 +0200 | [diff] [blame] | 1538 | gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1539 | |
Ben Widawsky | 678d96f | 2015-03-16 16:00:56 +0000 | [diff] [blame] | 1540 | gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); |
| 1541 | |
Thierry Reding | 440fd52 | 2015-01-23 09:05:06 +0100 | [diff] [blame] | 1542 | DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", |
Ben Widawsky | c8d4c0d | 2013-12-06 14:11:07 -0800 | [diff] [blame] | 1543 | ppgtt->node.size >> 20, |
| 1544 | ppgtt->node.start / PAGE_SIZE); |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1545 | |
Daniel Vetter | fa76da3 | 2014-08-06 20:19:54 +0200 | [diff] [blame] | 1546 | DRM_DEBUG("Adding PPGTT at offset %x\n", |
Mika Kuoppala | 44159dd | 2015-06-25 18:35:07 +0300 | [diff] [blame] | 1547 | ppgtt->pd.base.ggtt_offset << 10); |
Daniel Vetter | fa76da3 | 2014-08-06 20:19:54 +0200 | [diff] [blame] | 1548 | |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1549 | return 0; |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 1550 | } |
| 1551 | |
Daniel Vetter | 5c5f645 | 2015-04-14 17:35:14 +0200 | [diff] [blame] | 1552 | static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 1553 | { |
| 1554 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 1555 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1556 | ppgtt->base.dev = dev; |
Mika Kuoppala | c114f76 | 2015-06-25 18:35:13 +0300 | [diff] [blame] | 1557 | ppgtt->base.scratch_page = dev_priv->gtt.base.scratch_page; |
Daniel Vetter | 3440d26 | 2013-01-24 13:49:56 -0800 | [diff] [blame] | 1558 | |
Ben Widawsky | 3ed124b | 2013-04-08 18:43:53 -0700 | [diff] [blame] | 1559 | if (INTEL_INFO(dev)->gen < 8) |
Daniel Vetter | 5c5f645 | 2015-04-14 17:35:14 +0200 | [diff] [blame] | 1560 | return gen6_ppgtt_init(ppgtt); |
Ben Widawsky | 3ed124b | 2013-04-08 18:43:53 -0700 | [diff] [blame] | 1561 | else |
Michel Thierry | d7b2633 | 2015-04-08 12:13:34 +0100 | [diff] [blame] | 1562 | return gen8_ppgtt_init(ppgtt); |
Daniel Vetter | fa76da3 | 2014-08-06 20:19:54 +0200 | [diff] [blame] | 1563 | } |
Mika Kuoppala | c114f76 | 2015-06-25 18:35:13 +0300 | [diff] [blame] | 1564 | |
Daniel Vetter | fa76da3 | 2014-08-06 20:19:54 +0200 | [diff] [blame] | 1565 | int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) |
| 1566 | { |
| 1567 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1568 | int ret = 0; |
Ben Widawsky | 3ed124b | 2013-04-08 18:43:53 -0700 | [diff] [blame] | 1569 | |
Daniel Vetter | 5c5f645 | 2015-04-14 17:35:14 +0200 | [diff] [blame] | 1570 | ret = __hw_ppgtt_init(dev, ppgtt); |
Daniel Vetter | fa76da3 | 2014-08-06 20:19:54 +0200 | [diff] [blame] | 1571 | if (ret == 0) { |
Ben Widawsky | c7c48df | 2013-12-06 14:11:15 -0800 | [diff] [blame] | 1572 | kref_init(&ppgtt->ref); |
Ben Widawsky | 93bd864 | 2013-07-16 16:50:06 -0700 | [diff] [blame] | 1573 | drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, |
| 1574 | ppgtt->base.total); |
Ben Widawsky | 7e0d96b | 2013-12-06 14:11:26 -0800 | [diff] [blame] | 1575 | i915_init_vm(dev_priv, &ppgtt->base); |
Ben Widawsky | 93bd864 | 2013-07-16 16:50:06 -0700 | [diff] [blame] | 1576 | } |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1577 | |
| 1578 | return ret; |
| 1579 | } |
| 1580 | |
Daniel Vetter | 82460d9 | 2014-08-06 20:19:53 +0200 | [diff] [blame] | 1581 | int i915_ppgtt_init_hw(struct drm_device *dev) |
| 1582 | { |
Thomas Daniel | 671b5013 | 2014-08-20 16:24:50 +0100 | [diff] [blame] | 1583 | /* In the case of execlists, PPGTT is enabled by the context descriptor |
| 1584 | * and the PDPs are contained within the context itself. We don't |
| 1585 | * need to do anything here. */ |
| 1586 | if (i915.enable_execlists) |
| 1587 | return 0; |
| 1588 | |
Daniel Vetter | 82460d9 | 2014-08-06 20:19:53 +0200 | [diff] [blame] | 1589 | if (!USES_PPGTT(dev)) |
| 1590 | return 0; |
| 1591 | |
| 1592 | if (IS_GEN6(dev)) |
| 1593 | gen6_ppgtt_enable(dev); |
| 1594 | else if (IS_GEN7(dev)) |
| 1595 | gen7_ppgtt_enable(dev); |
| 1596 | else if (INTEL_INFO(dev)->gen >= 8) |
| 1597 | gen8_ppgtt_enable(dev); |
| 1598 | else |
Daniel Vetter | 5f77eeb | 2014-12-08 16:40:10 +0100 | [diff] [blame] | 1599 | MISSING_CASE(INTEL_INFO(dev)->gen); |
Daniel Vetter | 82460d9 | 2014-08-06 20:19:53 +0200 | [diff] [blame] | 1600 | |
John Harrison | 4ad2fd8 | 2015-06-18 13:11:20 +0100 | [diff] [blame] | 1601 | return 0; |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1602 | } |
John Harrison | 4ad2fd8 | 2015-06-18 13:11:20 +0100 | [diff] [blame] | 1603 | |
John Harrison | b3dd6b9 | 2015-05-29 17:43:40 +0100 | [diff] [blame] | 1604 | int i915_ppgtt_init_ring(struct drm_i915_gem_request *req) |
John Harrison | 4ad2fd8 | 2015-06-18 13:11:20 +0100 | [diff] [blame] | 1605 | { |
John Harrison | b3dd6b9 | 2015-05-29 17:43:40 +0100 | [diff] [blame] | 1606 | struct drm_i915_private *dev_priv = req->ring->dev->dev_private; |
John Harrison | 4ad2fd8 | 2015-06-18 13:11:20 +0100 | [diff] [blame] | 1607 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 1608 | |
| 1609 | if (i915.enable_execlists) |
| 1610 | return 0; |
| 1611 | |
| 1612 | if (!ppgtt) |
| 1613 | return 0; |
| 1614 | |
John Harrison | e85b26d | 2015-05-29 17:43:56 +0100 | [diff] [blame] | 1615 | return ppgtt->switch_mm(ppgtt, req); |
John Harrison | 4ad2fd8 | 2015-06-18 13:11:20 +0100 | [diff] [blame] | 1616 | } |
| 1617 | |
Daniel Vetter | 4d88470 | 2014-08-06 15:04:47 +0200 | [diff] [blame] | 1618 | struct i915_hw_ppgtt * |
| 1619 | i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) |
| 1620 | { |
| 1621 | struct i915_hw_ppgtt *ppgtt; |
| 1622 | int ret; |
| 1623 | |
| 1624 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); |
| 1625 | if (!ppgtt) |
| 1626 | return ERR_PTR(-ENOMEM); |
| 1627 | |
| 1628 | ret = i915_ppgtt_init(dev, ppgtt); |
| 1629 | if (ret) { |
| 1630 | kfree(ppgtt); |
| 1631 | return ERR_PTR(ret); |
| 1632 | } |
| 1633 | |
| 1634 | ppgtt->file_priv = fpriv; |
| 1635 | |
Daniele Ceraolo Spurio | 198c974 | 2014-11-10 13:44:31 +0000 | [diff] [blame] | 1636 | trace_i915_ppgtt_create(&ppgtt->base); |
| 1637 | |
Daniel Vetter | 4d88470 | 2014-08-06 15:04:47 +0200 | [diff] [blame] | 1638 | return ppgtt; |
| 1639 | } |
| 1640 | |
Daniel Vetter | ee960be | 2014-08-06 15:04:45 +0200 | [diff] [blame] | 1641 | void i915_ppgtt_release(struct kref *kref) |
| 1642 | { |
| 1643 | struct i915_hw_ppgtt *ppgtt = |
| 1644 | container_of(kref, struct i915_hw_ppgtt, ref); |
| 1645 | |
Daniele Ceraolo Spurio | 198c974 | 2014-11-10 13:44:31 +0000 | [diff] [blame] | 1646 | trace_i915_ppgtt_release(&ppgtt->base); |
| 1647 | |
Daniel Vetter | ee960be | 2014-08-06 15:04:45 +0200 | [diff] [blame] | 1648 | /* vmas should already be unbound */ |
| 1649 | WARN_ON(!list_empty(&ppgtt->base.active_list)); |
| 1650 | WARN_ON(!list_empty(&ppgtt->base.inactive_list)); |
| 1651 | |
Daniel Vetter | 19dd120 | 2014-08-06 15:04:55 +0200 | [diff] [blame] | 1652 | list_del(&ppgtt->base.global_link); |
| 1653 | drm_mm_takedown(&ppgtt->base.mm); |
| 1654 | |
Daniel Vetter | ee960be | 2014-08-06 15:04:45 +0200 | [diff] [blame] | 1655 | ppgtt->base.cleanup(&ppgtt->base); |
| 1656 | kfree(ppgtt); |
| 1657 | } |
Daniel Vetter | 1d2a314 | 2012-02-09 17:15:46 +0100 | [diff] [blame] | 1658 | |
Ben Widawsky | a81cc00 | 2013-01-18 12:30:31 -0800 | [diff] [blame] | 1659 | extern int intel_iommu_gfx_mapped; |
| 1660 | /* Certain Gen5 chipsets require require idling the GPU before |
| 1661 | * unmapping anything from the GTT when VT-d is enabled. |
| 1662 | */ |
Daniel Vetter | 2c642b0 | 2015-04-14 17:35:26 +0200 | [diff] [blame] | 1663 | static bool needs_idle_maps(struct drm_device *dev) |
Ben Widawsky | a81cc00 | 2013-01-18 12:30:31 -0800 | [diff] [blame] | 1664 | { |
| 1665 | #ifdef CONFIG_INTEL_IOMMU |
| 1666 | /* Query intel_iommu to see if we need the workaround. Presumably that |
| 1667 | * was loaded first. |
| 1668 | */ |
| 1669 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) |
| 1670 | return true; |
| 1671 | #endif |
| 1672 | return false; |
| 1673 | } |
| 1674 | |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 1675 | static bool do_idling(struct drm_i915_private *dev_priv) |
| 1676 | { |
| 1677 | bool ret = dev_priv->mm.interruptible; |
| 1678 | |
Ben Widawsky | a81cc00 | 2013-01-18 12:30:31 -0800 | [diff] [blame] | 1679 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 1680 | dev_priv->mm.interruptible = false; |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 1681 | if (i915_gpu_idle(dev_priv->dev)) { |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 1682 | DRM_ERROR("Couldn't idle GPU\n"); |
| 1683 | /* Wait a bit, in hopes it avoids the hang */ |
| 1684 | udelay(10); |
| 1685 | } |
| 1686 | } |
| 1687 | |
| 1688 | return ret; |
| 1689 | } |
| 1690 | |
| 1691 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) |
| 1692 | { |
Ben Widawsky | a81cc00 | 2013-01-18 12:30:31 -0800 | [diff] [blame] | 1693 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 1694 | dev_priv->mm.interruptible = interruptible; |
| 1695 | } |
| 1696 | |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1697 | void i915_check_and_clear_faults(struct drm_device *dev) |
| 1698 | { |
| 1699 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 1700 | struct intel_engine_cs *ring; |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1701 | int i; |
| 1702 | |
| 1703 | if (INTEL_INFO(dev)->gen < 6) |
| 1704 | return; |
| 1705 | |
| 1706 | for_each_ring(ring, dev_priv, i) { |
| 1707 | u32 fault_reg; |
| 1708 | fault_reg = I915_READ(RING_FAULT_REG(ring)); |
| 1709 | if (fault_reg & RING_FAULT_VALID) { |
| 1710 | DRM_DEBUG_DRIVER("Unexpected fault\n" |
Paulo Zanoni | 59a5d29 | 2014-10-30 15:52:45 -0200 | [diff] [blame] | 1711 | "\tAddr: 0x%08lx\n" |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1712 | "\tAddress space: %s\n" |
| 1713 | "\tSource ID: %d\n" |
| 1714 | "\tType: %d\n", |
| 1715 | fault_reg & PAGE_MASK, |
| 1716 | fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", |
| 1717 | RING_FAULT_SRCID(fault_reg), |
| 1718 | RING_FAULT_FAULT_TYPE(fault_reg)); |
| 1719 | I915_WRITE(RING_FAULT_REG(ring), |
| 1720 | fault_reg & ~RING_FAULT_VALID); |
| 1721 | } |
| 1722 | } |
| 1723 | POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); |
| 1724 | } |
| 1725 | |
Chris Wilson | 91e5649 | 2014-09-25 10:13:12 +0100 | [diff] [blame] | 1726 | static void i915_ggtt_flush(struct drm_i915_private *dev_priv) |
| 1727 | { |
| 1728 | if (INTEL_INFO(dev_priv->dev)->gen < 6) { |
| 1729 | intel_gtt_chipset_flush(); |
| 1730 | } else { |
| 1731 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); |
| 1732 | POSTING_READ(GFX_FLSH_CNTL_GEN6); |
| 1733 | } |
| 1734 | } |
| 1735 | |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1736 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev) |
| 1737 | { |
| 1738 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1739 | |
| 1740 | /* Don't bother messing with faults pre GEN6 as we have little |
| 1741 | * documentation supporting that it's a good idea. |
| 1742 | */ |
| 1743 | if (INTEL_INFO(dev)->gen < 6) |
| 1744 | return; |
| 1745 | |
| 1746 | i915_check_and_clear_faults(dev); |
| 1747 | |
| 1748 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1749 | dev_priv->gtt.base.start, |
| 1750 | dev_priv->gtt.base.total, |
Daniel Vetter | e568af1 | 2014-03-26 20:08:20 +0100 | [diff] [blame] | 1751 | true); |
Chris Wilson | 91e5649 | 2014-09-25 10:13:12 +0100 | [diff] [blame] | 1752 | |
| 1753 | i915_ggtt_flush(dev_priv); |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1754 | } |
| 1755 | |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 1756 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 1757 | { |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1758 | if (obj->has_dma_mapping) |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 1759 | return 0; |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 1760 | |
| 1761 | if (!dma_map_sg(&obj->base.dev->pdev->dev, |
| 1762 | obj->pages->sgl, obj->pages->nents, |
| 1763 | PCI_DMA_BIDIRECTIONAL)) |
| 1764 | return -ENOSPC; |
| 1765 | |
| 1766 | return 0; |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 1767 | } |
| 1768 | |
Daniel Vetter | 2c642b0 | 2015-04-14 17:35:26 +0200 | [diff] [blame] | 1769 | static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 1770 | { |
| 1771 | #ifdef writeq |
| 1772 | writeq(pte, addr); |
| 1773 | #else |
| 1774 | iowrite32((u32)pte, addr); |
| 1775 | iowrite32(pte >> 32, addr + 4); |
| 1776 | #endif |
| 1777 | } |
| 1778 | |
| 1779 | static void gen8_ggtt_insert_entries(struct i915_address_space *vm, |
| 1780 | struct sg_table *st, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1781 | uint64_t start, |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 1782 | enum i915_cache_level level, u32 unused) |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 1783 | { |
| 1784 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1785 | unsigned first_entry = start >> PAGE_SHIFT; |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 1786 | gen8_pte_t __iomem *gtt_entries = |
| 1787 | (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 1788 | int i = 0; |
| 1789 | struct sg_page_iter sg_iter; |
Pavel Machek | 57007df | 2014-07-28 13:20:58 +0200 | [diff] [blame] | 1790 | dma_addr_t addr = 0; /* shut up gcc */ |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 1791 | |
| 1792 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
| 1793 | addr = sg_dma_address(sg_iter.sg) + |
| 1794 | (sg_iter.sg_pgoffset << PAGE_SHIFT); |
| 1795 | gen8_set_pte(>t_entries[i], |
| 1796 | gen8_pte_encode(addr, level, true)); |
| 1797 | i++; |
| 1798 | } |
| 1799 | |
| 1800 | /* |
| 1801 | * XXX: This serves as a posting read to make sure that the PTE has |
| 1802 | * actually been updated. There is some concern that even though |
| 1803 | * registers and PTEs are within the same BAR that they are potentially |
| 1804 | * of NUMA access patterns. Therefore, even with the way we assume |
| 1805 | * hardware should work, we must keep this posting read for paranoia. |
| 1806 | */ |
| 1807 | if (i != 0) |
| 1808 | WARN_ON(readq(>t_entries[i-1]) |
| 1809 | != gen8_pte_encode(addr, level, true)); |
| 1810 | |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 1811 | /* This next bit makes the above posting read even more important. We |
| 1812 | * want to flush the TLBs only after we're certain all the PTE updates |
| 1813 | * have finished. |
| 1814 | */ |
| 1815 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); |
| 1816 | POSTING_READ(GFX_FLSH_CNTL_GEN6); |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 1817 | } |
| 1818 | |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1819 | /* |
| 1820 | * Binds an object into the global gtt with the specified cache level. The object |
| 1821 | * will be accessible to the GPU via commands whose operands reference offsets |
| 1822 | * within the global GTT as well as accessible by the GPU through the GMADR |
| 1823 | * mapped BAR (dev_priv->mm.gtt->gtt). |
| 1824 | */ |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1825 | static void gen6_ggtt_insert_entries(struct i915_address_space *vm, |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1826 | struct sg_table *st, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1827 | uint64_t start, |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 1828 | enum i915_cache_level level, u32 flags) |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1829 | { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1830 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1831 | unsigned first_entry = start >> PAGE_SHIFT; |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 1832 | gen6_pte_t __iomem *gtt_entries = |
| 1833 | (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; |
Imre Deak | 6e995e2 | 2013-02-18 19:28:04 +0200 | [diff] [blame] | 1834 | int i = 0; |
| 1835 | struct sg_page_iter sg_iter; |
Pavel Machek | 57007df | 2014-07-28 13:20:58 +0200 | [diff] [blame] | 1836 | dma_addr_t addr = 0; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1837 | |
Imre Deak | 6e995e2 | 2013-02-18 19:28:04 +0200 | [diff] [blame] | 1838 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
Imre Deak | 2db76d7 | 2013-03-26 15:14:18 +0200 | [diff] [blame] | 1839 | addr = sg_page_iter_dma_address(&sg_iter); |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 1840 | iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]); |
Imre Deak | 6e995e2 | 2013-02-18 19:28:04 +0200 | [diff] [blame] | 1841 | i++; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1842 | } |
| 1843 | |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1844 | /* XXX: This serves as a posting read to make sure that the PTE has |
| 1845 | * actually been updated. There is some concern that even though |
| 1846 | * registers and PTEs are within the same BAR that they are potentially |
| 1847 | * of NUMA access patterns. Therefore, even with the way we assume |
| 1848 | * hardware should work, we must keep this posting read for paranoia. |
| 1849 | */ |
Pavel Machek | 57007df | 2014-07-28 13:20:58 +0200 | [diff] [blame] | 1850 | if (i != 0) { |
| 1851 | unsigned long gtt = readl(>t_entries[i-1]); |
| 1852 | WARN_ON(gtt != vm->pte_encode(addr, level, true, flags)); |
| 1853 | } |
Ben Widawsky | 0f9b91c | 2012-11-04 09:21:30 -0800 | [diff] [blame] | 1854 | |
| 1855 | /* This next bit makes the above posting read even more important. We |
| 1856 | * want to flush the TLBs only after we're certain all the PTE updates |
| 1857 | * have finished. |
| 1858 | */ |
| 1859 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); |
| 1860 | POSTING_READ(GFX_FLSH_CNTL_GEN6); |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1861 | } |
| 1862 | |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 1863 | static void gen8_ggtt_clear_range(struct i915_address_space *vm, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1864 | uint64_t start, |
| 1865 | uint64_t length, |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 1866 | bool use_scratch) |
| 1867 | { |
| 1868 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1869 | unsigned first_entry = start >> PAGE_SHIFT; |
| 1870 | unsigned num_entries = length >> PAGE_SHIFT; |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 1871 | gen8_pte_t scratch_pte, __iomem *gtt_base = |
| 1872 | (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 1873 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
| 1874 | int i; |
| 1875 | |
| 1876 | if (WARN(num_entries > max_entries, |
| 1877 | "First entry = %d; Num entries = %d (max=%d)\n", |
| 1878 | first_entry, num_entries, max_entries)) |
| 1879 | num_entries = max_entries; |
| 1880 | |
Mika Kuoppala | c114f76 | 2015-06-25 18:35:13 +0300 | [diff] [blame] | 1881 | scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page), |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 1882 | I915_CACHE_LLC, |
| 1883 | use_scratch); |
| 1884 | for (i = 0; i < num_entries; i++) |
| 1885 | gen8_set_pte(>t_base[i], scratch_pte); |
| 1886 | readl(gtt_base); |
| 1887 | } |
| 1888 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1889 | static void gen6_ggtt_clear_range(struct i915_address_space *vm, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1890 | uint64_t start, |
| 1891 | uint64_t length, |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1892 | bool use_scratch) |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1893 | { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1894 | struct drm_i915_private *dev_priv = vm->dev->dev_private; |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1895 | unsigned first_entry = start >> PAGE_SHIFT; |
| 1896 | unsigned num_entries = length >> PAGE_SHIFT; |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 1897 | gen6_pte_t scratch_pte, __iomem *gtt_base = |
| 1898 | (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; |
Ben Widawsky | a54c0c2 | 2013-01-24 14:45:00 -0800 | [diff] [blame] | 1899 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1900 | int i; |
| 1901 | |
| 1902 | if (WARN(num_entries > max_entries, |
| 1903 | "First entry = %d; Num entries = %d (max=%d)\n", |
| 1904 | first_entry, num_entries, max_entries)) |
| 1905 | num_entries = max_entries; |
| 1906 | |
Mika Kuoppala | c114f76 | 2015-06-25 18:35:13 +0300 | [diff] [blame] | 1907 | scratch_pte = vm->pte_encode(px_dma(vm->scratch_page), |
| 1908 | I915_CACHE_LLC, use_scratch, 0); |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1909 | |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1910 | for (i = 0; i < num_entries; i++) |
| 1911 | iowrite32(scratch_pte, >t_base[i]); |
| 1912 | readl(gtt_base); |
| 1913 | } |
| 1914 | |
Daniel Vetter | d369d2d | 2015-04-14 17:35:25 +0200 | [diff] [blame] | 1915 | static void i915_ggtt_insert_entries(struct i915_address_space *vm, |
| 1916 | struct sg_table *pages, |
| 1917 | uint64_t start, |
| 1918 | enum i915_cache_level cache_level, u32 unused) |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1919 | { |
| 1920 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? |
| 1921 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; |
| 1922 | |
Daniel Vetter | d369d2d | 2015-04-14 17:35:25 +0200 | [diff] [blame] | 1923 | intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags); |
Daniel Vetter | 0875546 | 2015-04-20 09:04:05 -0700 | [diff] [blame] | 1924 | |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1925 | } |
| 1926 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 1927 | static void i915_ggtt_clear_range(struct i915_address_space *vm, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1928 | uint64_t start, |
| 1929 | uint64_t length, |
Ben Widawsky | 828c790 | 2013-10-16 09:21:30 -0700 | [diff] [blame] | 1930 | bool unused) |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1931 | { |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1932 | unsigned first_entry = start >> PAGE_SHIFT; |
| 1933 | unsigned num_entries = length >> PAGE_SHIFT; |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1934 | intel_gtt_clear_range(first_entry, num_entries); |
| 1935 | } |
| 1936 | |
Daniel Vetter | 70b9f6f | 2015-04-14 17:35:27 +0200 | [diff] [blame] | 1937 | static int ggtt_bind_vma(struct i915_vma *vma, |
| 1938 | enum i915_cache_level cache_level, |
| 1939 | u32 flags) |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 1940 | { |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1941 | struct drm_device *dev = vma->vm->dev; |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1942 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1943 | struct drm_i915_gem_object *obj = vma->obj; |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 1944 | struct sg_table *pages = obj->pages; |
Daniel Vetter | f329f5f | 2015-04-14 17:35:15 +0200 | [diff] [blame] | 1945 | u32 pte_flags = 0; |
Daniel Vetter | 70b9f6f | 2015-04-14 17:35:27 +0200 | [diff] [blame] | 1946 | int ret; |
| 1947 | |
| 1948 | ret = i915_get_ggtt_vma_pages(vma); |
| 1949 | if (ret) |
| 1950 | return ret; |
| 1951 | pages = vma->ggtt_view.pages; |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 1952 | |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 1953 | /* Currently applicable only to VLV */ |
| 1954 | if (obj->gt_ro) |
Daniel Vetter | f329f5f | 2015-04-14 17:35:15 +0200 | [diff] [blame] | 1955 | pte_flags |= PTE_READ_ONLY; |
Akash Goel | 24f3a8c | 2014-06-17 10:59:42 +0530 | [diff] [blame] | 1956 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 1957 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1958 | if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { |
Daniel Vetter | 0875546 | 2015-04-20 09:04:05 -0700 | [diff] [blame] | 1959 | vma->vm->insert_entries(vma->vm, pages, |
| 1960 | vma->node.start, |
| 1961 | cache_level, pte_flags); |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1962 | } |
Daniel Vetter | 74898d7 | 2012-02-15 23:50:22 +0100 | [diff] [blame] | 1963 | |
Daniel Vetter | 0875546 | 2015-04-20 09:04:05 -0700 | [diff] [blame] | 1964 | if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) { |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1965 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 1966 | appgtt->base.insert_entries(&appgtt->base, pages, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1967 | vma->node.start, |
Daniel Vetter | f329f5f | 2015-04-14 17:35:15 +0200 | [diff] [blame] | 1968 | cache_level, pte_flags); |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1969 | } |
Daniel Vetter | 70b9f6f | 2015-04-14 17:35:27 +0200 | [diff] [blame] | 1970 | |
| 1971 | return 0; |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1972 | } |
| 1973 | |
| 1974 | static void ggtt_unbind_vma(struct i915_vma *vma) |
| 1975 | { |
| 1976 | struct drm_device *dev = vma->vm->dev; |
| 1977 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1978 | struct drm_i915_gem_object *obj = vma->obj; |
Joonas Lahtinen | 06615ee | 2015-04-24 15:09:03 +0300 | [diff] [blame] | 1979 | const uint64_t size = min_t(uint64_t, |
| 1980 | obj->base.size, |
| 1981 | vma->node.size); |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1982 | |
Tvrtko Ursulin | aff4376 | 2014-10-24 12:42:33 +0100 | [diff] [blame] | 1983 | if (vma->bound & GLOBAL_BIND) { |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1984 | vma->vm->clear_range(vma->vm, |
| 1985 | vma->node.start, |
Joonas Lahtinen | 06615ee | 2015-04-24 15:09:03 +0300 | [diff] [blame] | 1986 | size, |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1987 | true); |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1988 | } |
| 1989 | |
Daniel Vetter | 0875546 | 2015-04-20 09:04:05 -0700 | [diff] [blame] | 1990 | if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) { |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1991 | struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; |
Joonas Lahtinen | 06615ee | 2015-04-24 15:09:03 +0300 | [diff] [blame] | 1992 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1993 | appgtt->base.clear_range(&appgtt->base, |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 1994 | vma->node.start, |
Joonas Lahtinen | 06615ee | 2015-04-24 15:09:03 +0300 | [diff] [blame] | 1995 | size, |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1996 | true); |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 1997 | } |
Daniel Vetter | 7416390 | 2012-02-15 23:50:21 +0100 | [diff] [blame] | 1998 | } |
| 1999 | |
| 2000 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) |
| 2001 | { |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 2002 | struct drm_device *dev = obj->base.dev; |
| 2003 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2004 | bool interruptible; |
| 2005 | |
| 2006 | interruptible = do_idling(dev_priv); |
| 2007 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 2008 | if (!obj->has_dma_mapping) |
| 2009 | dma_unmap_sg(&dev->pdev->dev, |
| 2010 | obj->pages->sgl, obj->pages->nents, |
| 2011 | PCI_DMA_BIDIRECTIONAL); |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 2012 | |
| 2013 | undo_idling(dev_priv, interruptible); |
Daniel Vetter | 7c2e6fd | 2010-11-06 10:10:47 +0100 | [diff] [blame] | 2014 | } |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 2015 | |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 2016 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
| 2017 | unsigned long color, |
Thierry Reding | 440fd52 | 2015-01-23 09:05:06 +0100 | [diff] [blame] | 2018 | u64 *start, |
| 2019 | u64 *end) |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 2020 | { |
| 2021 | if (node->color != color) |
| 2022 | *start += 4096; |
| 2023 | |
| 2024 | if (!list_empty(&node->node_list)) { |
| 2025 | node = list_entry(node->node_list.next, |
| 2026 | struct drm_mm_node, |
| 2027 | node_list); |
| 2028 | if (node->allocated && node->color != color) |
| 2029 | *end -= 4096; |
| 2030 | } |
| 2031 | } |
Ben Widawsky | fbe5d36 | 2013-11-04 19:56:49 -0800 | [diff] [blame] | 2032 | |
Daniel Vetter | f548c0e | 2014-11-19 21:40:13 +0100 | [diff] [blame] | 2033 | static int i915_gem_setup_global_gtt(struct drm_device *dev, |
| 2034 | unsigned long start, |
| 2035 | unsigned long mappable_end, |
| 2036 | unsigned long end) |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 2037 | { |
Ben Widawsky | e78891c | 2013-01-25 16:41:04 -0800 | [diff] [blame] | 2038 | /* Let GEM Manage all of the aperture. |
| 2039 | * |
| 2040 | * However, leave one page at the end still bound to the scratch page. |
| 2041 | * There are a number of places where the hardware apparently prefetches |
| 2042 | * past the end of the object, and we've seen multiple hangs with the |
| 2043 | * GPU head pointer stuck in a batchbuffer bound at the last page of the |
| 2044 | * aperture. One page should be enough to keep any prefetching inside |
| 2045 | * of the aperture. |
| 2046 | */ |
Ben Widawsky | 40d74980 | 2013-07-31 16:59:59 -0700 | [diff] [blame] | 2047 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2048 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 2049 | struct drm_mm_node *entry; |
| 2050 | struct drm_i915_gem_object *obj; |
| 2051 | unsigned long hole_start, hole_end; |
Daniel Vetter | fa76da3 | 2014-08-06 20:19:54 +0200 | [diff] [blame] | 2052 | int ret; |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 2053 | |
Ben Widawsky | 35451cb | 2013-01-17 12:45:13 -0800 | [diff] [blame] | 2054 | BUG_ON(mappable_end > end); |
| 2055 | |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 2056 | /* Subtract the guard page ... */ |
Ben Widawsky | 40d74980 | 2013-07-31 16:59:59 -0700 | [diff] [blame] | 2057 | drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); |
Yu Zhang | 5dda8fa | 2015-02-10 19:05:48 +0800 | [diff] [blame] | 2058 | |
| 2059 | dev_priv->gtt.base.start = start; |
| 2060 | dev_priv->gtt.base.total = end - start; |
| 2061 | |
| 2062 | if (intel_vgpu_active(dev)) { |
| 2063 | ret = intel_vgt_balloon(dev); |
| 2064 | if (ret) |
| 2065 | return ret; |
| 2066 | } |
| 2067 | |
Chris Wilson | 42d6ab4 | 2012-07-26 11:49:32 +0100 | [diff] [blame] | 2068 | if (!HAS_LLC(dev)) |
Ben Widawsky | 93bd864 | 2013-07-16 16:50:06 -0700 | [diff] [blame] | 2069 | dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 2070 | |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 2071 | /* Mark any preallocated objects as occupied */ |
Ben Widawsky | 35c20a6 | 2013-05-31 11:28:48 -0700 | [diff] [blame] | 2072 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
Ben Widawsky | 40d74980 | 2013-07-31 16:59:59 -0700 | [diff] [blame] | 2073 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); |
Daniel Vetter | fa76da3 | 2014-08-06 20:19:54 +0200 | [diff] [blame] | 2074 | |
Ben Widawsky | edd41a8 | 2013-07-05 14:41:05 -0700 | [diff] [blame] | 2075 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 2076 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 2077 | |
Ben Widawsky | c6cfb32 | 2013-07-05 14:41:06 -0700 | [diff] [blame] | 2078 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); |
Ben Widawsky | 40d74980 | 2013-07-31 16:59:59 -0700 | [diff] [blame] | 2079 | ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); |
Daniel Vetter | 6c5566a | 2014-08-06 15:04:50 +0200 | [diff] [blame] | 2080 | if (ret) { |
| 2081 | DRM_DEBUG_KMS("Reservation failed: %i\n", ret); |
| 2082 | return ret; |
| 2083 | } |
Tvrtko Ursulin | aff4376 | 2014-10-24 12:42:33 +0100 | [diff] [blame] | 2084 | vma->bound |= GLOBAL_BIND; |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 2085 | } |
| 2086 | |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 2087 | /* Clear any non-preallocated blocks */ |
Ben Widawsky | 40d74980 | 2013-07-31 16:59:59 -0700 | [diff] [blame] | 2088 | drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 2089 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", |
| 2090 | hole_start, hole_end); |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 2091 | ggtt_vm->clear_range(ggtt_vm, hole_start, |
| 2092 | hole_end - hole_start, true); |
Chris Wilson | ed2f345 | 2012-11-15 11:32:19 +0000 | [diff] [blame] | 2093 | } |
| 2094 | |
| 2095 | /* And finally clear the reserved guard page */ |
Ben Widawsky | 782f149 | 2014-02-20 11:50:33 -0800 | [diff] [blame] | 2096 | ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); |
Daniel Vetter | 6c5566a | 2014-08-06 15:04:50 +0200 | [diff] [blame] | 2097 | |
Daniel Vetter | fa76da3 | 2014-08-06 20:19:54 +0200 | [diff] [blame] | 2098 | if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) { |
| 2099 | struct i915_hw_ppgtt *ppgtt; |
| 2100 | |
| 2101 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); |
| 2102 | if (!ppgtt) |
| 2103 | return -ENOMEM; |
| 2104 | |
Daniel Vetter | 5c5f645 | 2015-04-14 17:35:14 +0200 | [diff] [blame] | 2105 | ret = __hw_ppgtt_init(dev, ppgtt); |
Michel Thierry | 4933d51 | 2015-03-24 15:46:22 +0000 | [diff] [blame] | 2106 | if (ret) { |
Daniel Vetter | 061dd49 | 2015-04-14 17:35:13 +0200 | [diff] [blame] | 2107 | ppgtt->base.cleanup(&ppgtt->base); |
Michel Thierry | 4933d51 | 2015-03-24 15:46:22 +0000 | [diff] [blame] | 2108 | kfree(ppgtt); |
Daniel Vetter | fa76da3 | 2014-08-06 20:19:54 +0200 | [diff] [blame] | 2109 | return ret; |
Michel Thierry | 4933d51 | 2015-03-24 15:46:22 +0000 | [diff] [blame] | 2110 | } |
Daniel Vetter | fa76da3 | 2014-08-06 20:19:54 +0200 | [diff] [blame] | 2111 | |
Daniel Vetter | 5c5f645 | 2015-04-14 17:35:14 +0200 | [diff] [blame] | 2112 | if (ppgtt->base.allocate_va_range) |
| 2113 | ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0, |
| 2114 | ppgtt->base.total); |
| 2115 | if (ret) { |
| 2116 | ppgtt->base.cleanup(&ppgtt->base); |
| 2117 | kfree(ppgtt); |
| 2118 | return ret; |
| 2119 | } |
| 2120 | |
| 2121 | ppgtt->base.clear_range(&ppgtt->base, |
| 2122 | ppgtt->base.start, |
| 2123 | ppgtt->base.total, |
| 2124 | true); |
| 2125 | |
Daniel Vetter | fa76da3 | 2014-08-06 20:19:54 +0200 | [diff] [blame] | 2126 | dev_priv->mm.aliasing_ppgtt = ppgtt; |
| 2127 | } |
| 2128 | |
Daniel Vetter | 6c5566a | 2014-08-06 15:04:50 +0200 | [diff] [blame] | 2129 | return 0; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2130 | } |
| 2131 | |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 2132 | void i915_gem_init_global_gtt(struct drm_device *dev) |
| 2133 | { |
| 2134 | struct drm_i915_private *dev_priv = dev->dev_private; |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 2135 | u64 gtt_size, mappable_size; |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 2136 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2137 | gtt_size = dev_priv->gtt.base.total; |
Ben Widawsky | 93d1879 | 2013-01-17 12:45:17 -0800 | [diff] [blame] | 2138 | mappable_size = dev_priv->gtt.mappable_end; |
Ben Widawsky | d7e5008 | 2012-12-18 10:31:25 -0800 | [diff] [blame] | 2139 | |
Ben Widawsky | e78891c | 2013-01-25 16:41:04 -0800 | [diff] [blame] | 2140 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2141 | } |
| 2142 | |
Daniel Vetter | 90d0a0e | 2014-08-06 15:04:56 +0200 | [diff] [blame] | 2143 | void i915_global_gtt_cleanup(struct drm_device *dev) |
| 2144 | { |
| 2145 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2146 | struct i915_address_space *vm = &dev_priv->gtt.base; |
| 2147 | |
Daniel Vetter | 70e3254 | 2014-08-06 15:04:57 +0200 | [diff] [blame] | 2148 | if (dev_priv->mm.aliasing_ppgtt) { |
| 2149 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 2150 | |
| 2151 | ppgtt->base.cleanup(&ppgtt->base); |
| 2152 | } |
| 2153 | |
Daniel Vetter | 90d0a0e | 2014-08-06 15:04:56 +0200 | [diff] [blame] | 2154 | if (drm_mm_initialized(&vm->mm)) { |
Yu Zhang | 5dda8fa | 2015-02-10 19:05:48 +0800 | [diff] [blame] | 2155 | if (intel_vgpu_active(dev)) |
| 2156 | intel_vgt_deballoon(); |
| 2157 | |
Daniel Vetter | 90d0a0e | 2014-08-06 15:04:56 +0200 | [diff] [blame] | 2158 | drm_mm_takedown(&vm->mm); |
| 2159 | list_del(&vm->global_link); |
| 2160 | } |
| 2161 | |
| 2162 | vm->cleanup(vm); |
| 2163 | } |
Daniel Vetter | 70e3254 | 2014-08-06 15:04:57 +0200 | [diff] [blame] | 2164 | |
Daniel Vetter | 2c642b0 | 2015-04-14 17:35:26 +0200 | [diff] [blame] | 2165 | static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2166 | { |
| 2167 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; |
| 2168 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; |
| 2169 | return snb_gmch_ctl << 20; |
| 2170 | } |
| 2171 | |
Daniel Vetter | 2c642b0 | 2015-04-14 17:35:26 +0200 | [diff] [blame] | 2172 | static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) |
Ben Widawsky | 9459d25 | 2013-11-03 16:53:55 -0800 | [diff] [blame] | 2173 | { |
| 2174 | bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; |
| 2175 | bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; |
| 2176 | if (bdw_gmch_ctl) |
| 2177 | bdw_gmch_ctl = 1 << bdw_gmch_ctl; |
Ben Widawsky | 562d55d | 2014-05-27 16:53:08 -0700 | [diff] [blame] | 2178 | |
| 2179 | #ifdef CONFIG_X86_32 |
| 2180 | /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ |
| 2181 | if (bdw_gmch_ctl > 4) |
| 2182 | bdw_gmch_ctl = 4; |
| 2183 | #endif |
| 2184 | |
Ben Widawsky | 9459d25 | 2013-11-03 16:53:55 -0800 | [diff] [blame] | 2185 | return bdw_gmch_ctl << 20; |
| 2186 | } |
| 2187 | |
Daniel Vetter | 2c642b0 | 2015-04-14 17:35:26 +0200 | [diff] [blame] | 2188 | static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) |
Damien Lespiau | d7f25f2 | 2014-05-08 22:19:40 +0300 | [diff] [blame] | 2189 | { |
| 2190 | gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; |
| 2191 | gmch_ctrl &= SNB_GMCH_GGMS_MASK; |
| 2192 | |
| 2193 | if (gmch_ctrl) |
| 2194 | return 1 << (20 + gmch_ctrl); |
| 2195 | |
| 2196 | return 0; |
| 2197 | } |
| 2198 | |
Daniel Vetter | 2c642b0 | 2015-04-14 17:35:26 +0200 | [diff] [blame] | 2199 | static size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2200 | { |
| 2201 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; |
| 2202 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; |
| 2203 | return snb_gmch_ctl << 25; /* 32 MB units */ |
| 2204 | } |
| 2205 | |
Daniel Vetter | 2c642b0 | 2015-04-14 17:35:26 +0200 | [diff] [blame] | 2206 | static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) |
Ben Widawsky | 9459d25 | 2013-11-03 16:53:55 -0800 | [diff] [blame] | 2207 | { |
| 2208 | bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; |
| 2209 | bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; |
| 2210 | return bdw_gmch_ctl << 25; /* 32 MB units */ |
| 2211 | } |
| 2212 | |
Damien Lespiau | d7f25f2 | 2014-05-08 22:19:40 +0300 | [diff] [blame] | 2213 | static size_t chv_get_stolen_size(u16 gmch_ctrl) |
| 2214 | { |
| 2215 | gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; |
| 2216 | gmch_ctrl &= SNB_GMCH_GMS_MASK; |
| 2217 | |
| 2218 | /* |
| 2219 | * 0x0 to 0x10: 32MB increments starting at 0MB |
| 2220 | * 0x11 to 0x16: 4MB increments starting at 8MB |
| 2221 | * 0x17 to 0x1d: 4MB increments start at 36MB |
| 2222 | */ |
| 2223 | if (gmch_ctrl < 0x11) |
| 2224 | return gmch_ctrl << 25; |
| 2225 | else if (gmch_ctrl < 0x17) |
| 2226 | return (gmch_ctrl - 0x11 + 2) << 22; |
| 2227 | else |
| 2228 | return (gmch_ctrl - 0x17 + 9) << 22; |
| 2229 | } |
| 2230 | |
Damien Lespiau | 6637501 | 2014-01-09 18:02:46 +0000 | [diff] [blame] | 2231 | static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) |
| 2232 | { |
| 2233 | gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; |
| 2234 | gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; |
| 2235 | |
| 2236 | if (gen9_gmch_ctl < 0xf0) |
| 2237 | return gen9_gmch_ctl << 25; /* 32 MB units */ |
| 2238 | else |
| 2239 | /* 4MB increments starting at 0xf0 for 4MB */ |
| 2240 | return (gen9_gmch_ctl - 0xf0 + 1) << 22; |
| 2241 | } |
| 2242 | |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2243 | static int ggtt_probe_common(struct drm_device *dev, |
| 2244 | size_t gtt_size) |
| 2245 | { |
| 2246 | struct drm_i915_private *dev_priv = dev->dev_private; |
Bjorn Helgaas | 21c3460 | 2013-12-21 10:52:52 -0700 | [diff] [blame] | 2247 | phys_addr_t gtt_phys_addr; |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2248 | int ret; |
| 2249 | |
| 2250 | /* For Modern GENs the PTEs and register space are split in the BAR */ |
Bjorn Helgaas | 21c3460 | 2013-12-21 10:52:52 -0700 | [diff] [blame] | 2251 | gtt_phys_addr = pci_resource_start(dev->pdev, 0) + |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2252 | (pci_resource_len(dev->pdev, 0) / 2); |
| 2253 | |
Imre Deak | 2a073f89 | 2015-03-27 13:07:33 +0200 | [diff] [blame] | 2254 | /* |
| 2255 | * On BXT writes larger than 64 bit to the GTT pagetable range will be |
| 2256 | * dropped. For WC mappings in general we have 64 byte burst writes |
| 2257 | * when the WC buffer is flushed, so we can't use it, but have to |
| 2258 | * resort to an uncached mapping. The WC issue is easily caught by the |
| 2259 | * readback check when writing GTT PTE entries. |
| 2260 | */ |
| 2261 | if (IS_BROXTON(dev)) |
| 2262 | dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size); |
| 2263 | else |
| 2264 | dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2265 | if (!dev_priv->gtt.gsm) { |
| 2266 | DRM_ERROR("Failed to map the gtt page table\n"); |
| 2267 | return -ENOMEM; |
| 2268 | } |
| 2269 | |
Mika Kuoppala | c114f76 | 2015-06-25 18:35:13 +0300 | [diff] [blame] | 2270 | ret = alloc_scratch_page(&dev_priv->gtt.base); |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2271 | if (ret) { |
| 2272 | DRM_ERROR("Scratch setup failed\n"); |
| 2273 | /* iounmap will also get called at remove, but meh */ |
| 2274 | iounmap(dev_priv->gtt.gsm); |
| 2275 | } |
| 2276 | |
| 2277 | return ret; |
| 2278 | } |
| 2279 | |
Ben Widawsky | fbe5d36 | 2013-11-04 19:56:49 -0800 | [diff] [blame] | 2280 | /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability |
| 2281 | * bits. When using advanced contexts each context stores its own PAT, but |
| 2282 | * writing this data shouldn't be harmful even in those cases. */ |
Ville Syrjälä | ee0ce47 | 2014-04-09 13:28:01 +0300 | [diff] [blame] | 2283 | static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) |
Ben Widawsky | fbe5d36 | 2013-11-04 19:56:49 -0800 | [diff] [blame] | 2284 | { |
Ben Widawsky | fbe5d36 | 2013-11-04 19:56:49 -0800 | [diff] [blame] | 2285 | uint64_t pat; |
| 2286 | |
| 2287 | pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ |
| 2288 | GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ |
| 2289 | GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ |
| 2290 | GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ |
| 2291 | GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | |
| 2292 | GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | |
| 2293 | GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | |
| 2294 | GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); |
| 2295 | |
Rodrigo Vivi | d6a8b72 | 2014-11-05 16:56:36 -0800 | [diff] [blame] | 2296 | if (!USES_PPGTT(dev_priv->dev)) |
| 2297 | /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, |
| 2298 | * so RTL will always use the value corresponding to |
| 2299 | * pat_sel = 000". |
| 2300 | * So let's disable cache for GGTT to avoid screen corruptions. |
| 2301 | * MOCS still can be used though. |
| 2302 | * - System agent ggtt writes (i.e. cpu gtt mmaps) already work |
| 2303 | * before this patch, i.e. the same uncached + snooping access |
| 2304 | * like on gen6/7 seems to be in effect. |
| 2305 | * - So this just fixes blitter/render access. Again it looks |
| 2306 | * like it's not just uncached access, but uncached + snooping. |
| 2307 | * So we can still hold onto all our assumptions wrt cpu |
| 2308 | * clflushing on LLC machines. |
| 2309 | */ |
| 2310 | pat = GEN8_PPAT(0, GEN8_PPAT_UC); |
| 2311 | |
Ben Widawsky | fbe5d36 | 2013-11-04 19:56:49 -0800 | [diff] [blame] | 2312 | /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b |
| 2313 | * write would work. */ |
| 2314 | I915_WRITE(GEN8_PRIVATE_PAT, pat); |
| 2315 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); |
| 2316 | } |
| 2317 | |
Ville Syrjälä | ee0ce47 | 2014-04-09 13:28:01 +0300 | [diff] [blame] | 2318 | static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) |
| 2319 | { |
| 2320 | uint64_t pat; |
| 2321 | |
| 2322 | /* |
| 2323 | * Map WB on BDW to snooped on CHV. |
| 2324 | * |
| 2325 | * Only the snoop bit has meaning for CHV, the rest is |
| 2326 | * ignored. |
| 2327 | * |
Ville Syrjälä | cf3d262 | 2014-11-14 21:02:44 +0200 | [diff] [blame] | 2328 | * The hardware will never snoop for certain types of accesses: |
| 2329 | * - CPU GTT (GMADR->GGTT->no snoop->memory) |
| 2330 | * - PPGTT page tables |
| 2331 | * - some other special cycles |
| 2332 | * |
| 2333 | * As with BDW, we also need to consider the following for GT accesses: |
| 2334 | * "For GGTT, there is NO pat_sel[2:0] from the entry, |
| 2335 | * so RTL will always use the value corresponding to |
| 2336 | * pat_sel = 000". |
| 2337 | * Which means we must set the snoop bit in PAT entry 0 |
| 2338 | * in order to keep the global status page working. |
Ville Syrjälä | ee0ce47 | 2014-04-09 13:28:01 +0300 | [diff] [blame] | 2339 | */ |
| 2340 | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | |
| 2341 | GEN8_PPAT(1, 0) | |
| 2342 | GEN8_PPAT(2, 0) | |
| 2343 | GEN8_PPAT(3, 0) | |
| 2344 | GEN8_PPAT(4, CHV_PPAT_SNOOP) | |
| 2345 | GEN8_PPAT(5, CHV_PPAT_SNOOP) | |
| 2346 | GEN8_PPAT(6, CHV_PPAT_SNOOP) | |
| 2347 | GEN8_PPAT(7, CHV_PPAT_SNOOP); |
| 2348 | |
| 2349 | I915_WRITE(GEN8_PRIVATE_PAT, pat); |
| 2350 | I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); |
| 2351 | } |
| 2352 | |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2353 | static int gen8_gmch_probe(struct drm_device *dev, |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 2354 | u64 *gtt_total, |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2355 | size_t *stolen, |
| 2356 | phys_addr_t *mappable_base, |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 2357 | u64 *mappable_end) |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2358 | { |
| 2359 | struct drm_i915_private *dev_priv = dev->dev_private; |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 2360 | u64 gtt_size; |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2361 | u16 snb_gmch_ctl; |
| 2362 | int ret; |
| 2363 | |
| 2364 | /* TODO: We're not aware of mappable constraints on gen8 yet */ |
| 2365 | *mappable_base = pci_resource_start(dev->pdev, 2); |
| 2366 | *mappable_end = pci_resource_len(dev->pdev, 2); |
| 2367 | |
| 2368 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) |
| 2369 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); |
| 2370 | |
| 2371 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
| 2372 | |
Damien Lespiau | 6637501 | 2014-01-09 18:02:46 +0000 | [diff] [blame] | 2373 | if (INTEL_INFO(dev)->gen >= 9) { |
| 2374 | *stolen = gen9_get_stolen_size(snb_gmch_ctl); |
| 2375 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); |
| 2376 | } else if (IS_CHERRYVIEW(dev)) { |
Damien Lespiau | d7f25f2 | 2014-05-08 22:19:40 +0300 | [diff] [blame] | 2377 | *stolen = chv_get_stolen_size(snb_gmch_ctl); |
| 2378 | gtt_size = chv_get_total_gtt_size(snb_gmch_ctl); |
| 2379 | } else { |
| 2380 | *stolen = gen8_get_stolen_size(snb_gmch_ctl); |
| 2381 | gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); |
| 2382 | } |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2383 | |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 2384 | *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT; |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2385 | |
Sumit Singh | 5a4e33a | 2015-03-17 11:39:31 +0200 | [diff] [blame] | 2386 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) |
Ville Syrjälä | ee0ce47 | 2014-04-09 13:28:01 +0300 | [diff] [blame] | 2387 | chv_setup_private_ppat(dev_priv); |
| 2388 | else |
| 2389 | bdw_setup_private_ppat(dev_priv); |
Ben Widawsky | fbe5d36 | 2013-11-04 19:56:49 -0800 | [diff] [blame] | 2390 | |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2391 | ret = ggtt_probe_common(dev, gtt_size); |
| 2392 | |
Ben Widawsky | 94ec8f6 | 2013-11-02 21:07:18 -0700 | [diff] [blame] | 2393 | dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; |
| 2394 | dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; |
Daniel Vetter | 777dc5b | 2015-04-14 17:35:12 +0200 | [diff] [blame] | 2395 | dev_priv->gtt.base.bind_vma = ggtt_bind_vma; |
| 2396 | dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2397 | |
| 2398 | return ret; |
| 2399 | } |
| 2400 | |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2401 | static int gen6_gmch_probe(struct drm_device *dev, |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 2402 | u64 *gtt_total, |
Ben Widawsky | 41907dd | 2013-02-08 11:32:47 -0800 | [diff] [blame] | 2403 | size_t *stolen, |
| 2404 | phys_addr_t *mappable_base, |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 2405 | u64 *mappable_end) |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2406 | { |
| 2407 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2408 | unsigned int gtt_size; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2409 | u16 snb_gmch_ctl; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2410 | int ret; |
| 2411 | |
Ben Widawsky | 41907dd | 2013-02-08 11:32:47 -0800 | [diff] [blame] | 2412 | *mappable_base = pci_resource_start(dev->pdev, 2); |
| 2413 | *mappable_end = pci_resource_len(dev->pdev, 2); |
| 2414 | |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2415 | /* 64/512MB is the current min/max we actually know of, but this is just |
| 2416 | * a coarse sanity check. |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2417 | */ |
Ben Widawsky | 41907dd | 2013-02-08 11:32:47 -0800 | [diff] [blame] | 2418 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 2419 | DRM_ERROR("Unknown GMADR size (%llx)\n", |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2420 | dev_priv->gtt.mappable_end); |
| 2421 | return -ENXIO; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2422 | } |
| 2423 | |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2424 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
| 2425 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2426 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2427 | |
Ben Widawsky | c4ae25e | 2013-05-01 11:00:34 -0700 | [diff] [blame] | 2428 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2429 | |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2430 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
Michel Thierry | 07749ef | 2015-03-16 16:00:54 +0000 | [diff] [blame] | 2431 | *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT; |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2432 | |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2433 | ret = ggtt_probe_common(dev, gtt_size); |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2434 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2435 | dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; |
| 2436 | dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; |
Daniel Vetter | 777dc5b | 2015-04-14 17:35:12 +0200 | [diff] [blame] | 2437 | dev_priv->gtt.base.bind_vma = ggtt_bind_vma; |
| 2438 | dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2439 | |
| 2440 | return ret; |
| 2441 | } |
| 2442 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2443 | static void gen6_gmch_remove(struct i915_address_space *vm) |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2444 | { |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2445 | |
| 2446 | struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); |
Ben Widawsky | 5ed1678 | 2013-11-25 09:54:43 -0800 | [diff] [blame] | 2447 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2448 | iounmap(gtt->gsm); |
Mika Kuoppala | c114f76 | 2015-06-25 18:35:13 +0300 | [diff] [blame] | 2449 | free_scratch_page(vm); |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2450 | } |
| 2451 | |
| 2452 | static int i915_gmch_probe(struct drm_device *dev, |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 2453 | u64 *gtt_total, |
Ben Widawsky | 41907dd | 2013-02-08 11:32:47 -0800 | [diff] [blame] | 2454 | size_t *stolen, |
| 2455 | phys_addr_t *mappable_base, |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 2456 | u64 *mappable_end) |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2457 | { |
| 2458 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2459 | int ret; |
| 2460 | |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2461 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
| 2462 | if (!ret) { |
| 2463 | DRM_ERROR("failed to set up gmch\n"); |
| 2464 | return -EIO; |
| 2465 | } |
| 2466 | |
Ben Widawsky | 41907dd | 2013-02-08 11:32:47 -0800 | [diff] [blame] | 2467 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2468 | |
| 2469 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); |
Daniel Vetter | d369d2d | 2015-04-14 17:35:25 +0200 | [diff] [blame] | 2470 | dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries; |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2471 | dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; |
Daniel Vetter | d369d2d | 2015-04-14 17:35:25 +0200 | [diff] [blame] | 2472 | dev_priv->gtt.base.bind_vma = ggtt_bind_vma; |
| 2473 | dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma; |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2474 | |
Chris Wilson | c0a7f81 | 2013-12-30 12:16:15 +0000 | [diff] [blame] | 2475 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
| 2476 | DRM_INFO("applying Ironlake quirks for intel_iommu\n"); |
| 2477 | |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2478 | return 0; |
| 2479 | } |
| 2480 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2481 | static void i915_gmch_remove(struct i915_address_space *vm) |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2482 | { |
| 2483 | intel_gmch_remove(); |
| 2484 | } |
| 2485 | |
| 2486 | int i915_gem_gtt_init(struct drm_device *dev) |
| 2487 | { |
| 2488 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2489 | struct i915_gtt *gtt = &dev_priv->gtt; |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2490 | int ret; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2491 | |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2492 | if (INTEL_INFO(dev)->gen <= 5) { |
Ben Widawsky | b2f21b4 | 2013-06-27 16:30:20 -0700 | [diff] [blame] | 2493 | gtt->gtt_probe = i915_gmch_probe; |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2494 | gtt->base.cleanup = i915_gmch_remove; |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2495 | } else if (INTEL_INFO(dev)->gen < 8) { |
Ben Widawsky | b2f21b4 | 2013-06-27 16:30:20 -0700 | [diff] [blame] | 2496 | gtt->gtt_probe = gen6_gmch_probe; |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2497 | gtt->base.cleanup = gen6_gmch_remove; |
Ben Widawsky | 4d15c14 | 2013-07-04 11:02:06 -0700 | [diff] [blame] | 2498 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2499 | gtt->base.pte_encode = iris_pte_encode; |
Ben Widawsky | 4d15c14 | 2013-07-04 11:02:06 -0700 | [diff] [blame] | 2500 | else if (IS_HASWELL(dev)) |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2501 | gtt->base.pte_encode = hsw_pte_encode; |
Ben Widawsky | b2f21b4 | 2013-06-27 16:30:20 -0700 | [diff] [blame] | 2502 | else if (IS_VALLEYVIEW(dev)) |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2503 | gtt->base.pte_encode = byt_pte_encode; |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 2504 | else if (INTEL_INFO(dev)->gen >= 7) |
| 2505 | gtt->base.pte_encode = ivb_pte_encode; |
Ben Widawsky | b2f21b4 | 2013-06-27 16:30:20 -0700 | [diff] [blame] | 2506 | else |
Chris Wilson | 350ec88 | 2013-08-06 13:17:02 +0100 | [diff] [blame] | 2507 | gtt->base.pte_encode = snb_pte_encode; |
Ben Widawsky | 6334013 | 2013-11-04 19:32:22 -0800 | [diff] [blame] | 2508 | } else { |
| 2509 | dev_priv->gtt.gtt_probe = gen8_gmch_probe; |
| 2510 | dev_priv->gtt.base.cleanup = gen6_gmch_remove; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2511 | } |
| 2512 | |
Mika Kuoppala | c114f76 | 2015-06-25 18:35:13 +0300 | [diff] [blame] | 2513 | gtt->base.dev = dev; |
| 2514 | |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2515 | ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, |
Ben Widawsky | b2f21b4 | 2013-06-27 16:30:20 -0700 | [diff] [blame] | 2516 | >t->mappable_base, >t->mappable_end); |
Ben Widawsky | a54c0c2 | 2013-01-24 14:45:00 -0800 | [diff] [blame] | 2517 | if (ret) |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2518 | return ret; |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2519 | |
Ben Widawsky | baa09f5 | 2013-01-24 13:49:57 -0800 | [diff] [blame] | 2520 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 2521 | DRM_INFO("Memory usable by graphics device = %lluM\n", |
Ben Widawsky | 853ba5d | 2013-07-16 16:50:05 -0700 | [diff] [blame] | 2522 | gtt->base.total >> 20); |
Mika Kuoppala | c44ef60 | 2015-06-25 18:35:05 +0300 | [diff] [blame] | 2523 | DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20); |
Ben Widawsky | b2f21b4 | 2013-06-27 16:30:20 -0700 | [diff] [blame] | 2524 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); |
Daniel Vetter | 5db6c73 | 2014-03-31 16:23:04 +0200 | [diff] [blame] | 2525 | #ifdef CONFIG_INTEL_IOMMU |
| 2526 | if (intel_iommu_gfx_mapped) |
| 2527 | DRM_INFO("VT-d active for gfx access\n"); |
| 2528 | #endif |
Daniel Vetter | cfa7c86 | 2014-04-29 11:53:58 +0200 | [diff] [blame] | 2529 | /* |
| 2530 | * i915.enable_ppgtt is read-only, so do an early pass to validate the |
| 2531 | * user's requested state against the hardware/driver capabilities. We |
| 2532 | * do this now so that we can print out any log messages once rather |
| 2533 | * than every time we check intel_enable_ppgtt(). |
| 2534 | */ |
| 2535 | i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); |
| 2536 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); |
Daniel Vetter | 7faf1ab | 2013-01-24 14:44:55 -0800 | [diff] [blame] | 2537 | |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 2538 | return 0; |
Daniel Vetter | 644ec02 | 2012-03-26 09:45:40 +0200 | [diff] [blame] | 2539 | } |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 2540 | |
Daniel Vetter | fa42331 | 2015-04-14 17:35:23 +0200 | [diff] [blame] | 2541 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
| 2542 | { |
| 2543 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2544 | struct drm_i915_gem_object *obj; |
| 2545 | struct i915_address_space *vm; |
| 2546 | |
| 2547 | i915_check_and_clear_faults(dev); |
| 2548 | |
| 2549 | /* First fill our portion of the GTT with scratch pages */ |
| 2550 | dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, |
| 2551 | dev_priv->gtt.base.start, |
| 2552 | dev_priv->gtt.base.total, |
| 2553 | true); |
| 2554 | |
| 2555 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
| 2556 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, |
| 2557 | &dev_priv->gtt.base); |
| 2558 | if (!vma) |
| 2559 | continue; |
| 2560 | |
| 2561 | i915_gem_clflush_object(obj, obj->pin_display); |
| 2562 | WARN_ON(i915_vma_bind(vma, obj->cache_level, PIN_UPDATE)); |
| 2563 | } |
| 2564 | |
| 2565 | |
| 2566 | if (INTEL_INFO(dev)->gen >= 8) { |
| 2567 | if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) |
| 2568 | chv_setup_private_ppat(dev_priv); |
| 2569 | else |
| 2570 | bdw_setup_private_ppat(dev_priv); |
| 2571 | |
| 2572 | return; |
| 2573 | } |
| 2574 | |
| 2575 | if (USES_PPGTT(dev)) { |
| 2576 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
| 2577 | /* TODO: Perhaps it shouldn't be gen6 specific */ |
| 2578 | |
| 2579 | struct i915_hw_ppgtt *ppgtt = |
| 2580 | container_of(vm, struct i915_hw_ppgtt, |
| 2581 | base); |
| 2582 | |
| 2583 | if (i915_is_ggtt(vm)) |
| 2584 | ppgtt = dev_priv->mm.aliasing_ppgtt; |
| 2585 | |
| 2586 | gen6_write_page_range(dev_priv, &ppgtt->pd, |
| 2587 | 0, ppgtt->base.total); |
| 2588 | } |
| 2589 | } |
| 2590 | |
| 2591 | i915_ggtt_flush(dev_priv); |
| 2592 | } |
| 2593 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 2594 | static struct i915_vma * |
| 2595 | __i915_gem_vma_create(struct drm_i915_gem_object *obj, |
| 2596 | struct i915_address_space *vm, |
| 2597 | const struct i915_ggtt_view *ggtt_view) |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 2598 | { |
Dan Carpenter | dabde5c | 2015-03-18 11:21:58 +0300 | [diff] [blame] | 2599 | struct i915_vma *vma; |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 2600 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 2601 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
| 2602 | return ERR_PTR(-EINVAL); |
Chris Wilson | e20d2ab | 2015-04-07 16:20:58 +0100 | [diff] [blame] | 2603 | |
| 2604 | vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL); |
Dan Carpenter | dabde5c | 2015-03-18 11:21:58 +0300 | [diff] [blame] | 2605 | if (vma == NULL) |
| 2606 | return ERR_PTR(-ENOMEM); |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 2607 | |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 2608 | INIT_LIST_HEAD(&vma->vma_link); |
| 2609 | INIT_LIST_HEAD(&vma->mm_list); |
| 2610 | INIT_LIST_HEAD(&vma->exec_list); |
| 2611 | vma->vm = vm; |
| 2612 | vma->obj = obj; |
| 2613 | |
Daniel Vetter | 777dc5b | 2015-04-14 17:35:12 +0200 | [diff] [blame] | 2614 | if (i915_is_ggtt(vm)) |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 2615 | vma->ggtt_view = *ggtt_view; |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 2616 | |
Tvrtko Ursulin | f763566 | 2014-12-03 14:59:24 +0000 | [diff] [blame] | 2617 | list_add_tail(&vma->vma_link, &obj->vma_list); |
| 2618 | if (!i915_is_ggtt(vm)) |
Michel Thierry | e07f055 | 2014-08-19 15:49:41 +0100 | [diff] [blame] | 2619 | i915_ppgtt_get(i915_vm_to_ppgtt(vm)); |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 2620 | |
| 2621 | return vma; |
| 2622 | } |
| 2623 | |
| 2624 | struct i915_vma * |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 2625 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, |
| 2626 | struct i915_address_space *vm) |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 2627 | { |
| 2628 | struct i915_vma *vma; |
| 2629 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 2630 | vma = i915_gem_obj_to_vma(obj, vm); |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 2631 | if (!vma) |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 2632 | vma = __i915_gem_vma_create(obj, vm, |
| 2633 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL); |
Ben Widawsky | 6f65e29 | 2013-12-06 14:10:56 -0800 | [diff] [blame] | 2634 | |
| 2635 | return vma; |
| 2636 | } |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 2637 | |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 2638 | struct i915_vma * |
| 2639 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, |
| 2640 | const struct i915_ggtt_view *view) |
| 2641 | { |
| 2642 | struct i915_address_space *ggtt = i915_obj_to_ggtt(obj); |
| 2643 | struct i915_vma *vma; |
| 2644 | |
| 2645 | if (WARN_ON(!view)) |
| 2646 | return ERR_PTR(-EINVAL); |
| 2647 | |
| 2648 | vma = i915_gem_obj_to_ggtt_view(obj, view); |
| 2649 | |
| 2650 | if (IS_ERR(vma)) |
| 2651 | return vma; |
| 2652 | |
| 2653 | if (!vma) |
| 2654 | vma = __i915_gem_vma_create(obj, ggtt, view); |
| 2655 | |
| 2656 | return vma; |
| 2657 | |
| 2658 | } |
| 2659 | |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 2660 | static void |
| 2661 | rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height, |
| 2662 | struct sg_table *st) |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 2663 | { |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 2664 | unsigned int column, row; |
| 2665 | unsigned int src_idx; |
| 2666 | struct scatterlist *sg = st->sgl; |
| 2667 | |
| 2668 | st->nents = 0; |
| 2669 | |
| 2670 | for (column = 0; column < width; column++) { |
| 2671 | src_idx = width * (height - 1) + column; |
| 2672 | for (row = 0; row < height; row++) { |
| 2673 | st->nents++; |
| 2674 | /* We don't need the pages, but need to initialize |
| 2675 | * the entries so the sg list can be happily traversed. |
| 2676 | * The only thing we need are DMA addresses. |
| 2677 | */ |
| 2678 | sg_set_page(sg, NULL, PAGE_SIZE, 0); |
| 2679 | sg_dma_address(sg) = in[src_idx]; |
| 2680 | sg_dma_len(sg) = PAGE_SIZE; |
| 2681 | sg = sg_next(sg); |
| 2682 | src_idx -= width; |
| 2683 | } |
| 2684 | } |
| 2685 | } |
| 2686 | |
| 2687 | static struct sg_table * |
| 2688 | intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view, |
| 2689 | struct drm_i915_gem_object *obj) |
| 2690 | { |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 2691 | struct intel_rotation_info *rot_info = &ggtt_view->rotation_info; |
Tvrtko Ursulin | 84fe03f | 2015-06-23 14:26:46 +0100 | [diff] [blame] | 2692 | unsigned int size_pages = rot_info->size >> PAGE_SHIFT; |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 2693 | struct sg_page_iter sg_iter; |
| 2694 | unsigned long i; |
| 2695 | dma_addr_t *page_addr_list; |
| 2696 | struct sg_table *st; |
Tvrtko Ursulin | 1d00dad | 2015-03-25 10:15:26 +0000 | [diff] [blame] | 2697 | int ret = -ENOMEM; |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 2698 | |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 2699 | /* Allocate a temporary list of source pages for random access. */ |
Tvrtko Ursulin | 84fe03f | 2015-06-23 14:26:46 +0100 | [diff] [blame] | 2700 | page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE, |
| 2701 | sizeof(dma_addr_t)); |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 2702 | if (!page_addr_list) |
| 2703 | return ERR_PTR(ret); |
| 2704 | |
| 2705 | /* Allocate target SG list. */ |
| 2706 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
| 2707 | if (!st) |
| 2708 | goto err_st_alloc; |
| 2709 | |
Tvrtko Ursulin | 84fe03f | 2015-06-23 14:26:46 +0100 | [diff] [blame] | 2710 | ret = sg_alloc_table(st, size_pages, GFP_KERNEL); |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 2711 | if (ret) |
| 2712 | goto err_sg_alloc; |
| 2713 | |
| 2714 | /* Populate source page list from the object. */ |
| 2715 | i = 0; |
| 2716 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
| 2717 | page_addr_list[i] = sg_page_iter_dma_address(&sg_iter); |
| 2718 | i++; |
| 2719 | } |
| 2720 | |
| 2721 | /* Rotate the pages. */ |
Tvrtko Ursulin | 84fe03f | 2015-06-23 14:26:46 +0100 | [diff] [blame] | 2722 | rotate_pages(page_addr_list, |
| 2723 | rot_info->width_pages, rot_info->height_pages, |
| 2724 | st); |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 2725 | |
| 2726 | DRM_DEBUG_KMS( |
Tvrtko Ursulin | 84fe03f | 2015-06-23 14:26:46 +0100 | [diff] [blame] | 2727 | "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n", |
Tvrtko Ursulin | c9f8fd2 | 2015-06-24 09:55:20 +0100 | [diff] [blame] | 2728 | obj->base.size, rot_info->pitch, rot_info->height, |
Tvrtko Ursulin | 84fe03f | 2015-06-23 14:26:46 +0100 | [diff] [blame] | 2729 | rot_info->pixel_format, rot_info->width_pages, |
| 2730 | rot_info->height_pages, size_pages); |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 2731 | |
| 2732 | drm_free_large(page_addr_list); |
| 2733 | |
| 2734 | return st; |
| 2735 | |
| 2736 | err_sg_alloc: |
| 2737 | kfree(st); |
| 2738 | err_st_alloc: |
| 2739 | drm_free_large(page_addr_list); |
| 2740 | |
| 2741 | DRM_DEBUG_KMS( |
Tvrtko Ursulin | 84fe03f | 2015-06-23 14:26:46 +0100 | [diff] [blame] | 2742 | "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n", |
Tvrtko Ursulin | c9f8fd2 | 2015-06-24 09:55:20 +0100 | [diff] [blame] | 2743 | obj->base.size, ret, rot_info->pitch, rot_info->height, |
Tvrtko Ursulin | 84fe03f | 2015-06-23 14:26:46 +0100 | [diff] [blame] | 2744 | rot_info->pixel_format, rot_info->width_pages, |
| 2745 | rot_info->height_pages, size_pages); |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 2746 | return ERR_PTR(ret); |
| 2747 | } |
| 2748 | |
Joonas Lahtinen | 8bd7ef1 | 2015-05-06 14:35:38 +0300 | [diff] [blame] | 2749 | static struct sg_table * |
| 2750 | intel_partial_pages(const struct i915_ggtt_view *view, |
| 2751 | struct drm_i915_gem_object *obj) |
| 2752 | { |
| 2753 | struct sg_table *st; |
| 2754 | struct scatterlist *sg; |
| 2755 | struct sg_page_iter obj_sg_iter; |
| 2756 | int ret = -ENOMEM; |
| 2757 | |
| 2758 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
| 2759 | if (!st) |
| 2760 | goto err_st_alloc; |
| 2761 | |
| 2762 | ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL); |
| 2763 | if (ret) |
| 2764 | goto err_sg_alloc; |
| 2765 | |
| 2766 | sg = st->sgl; |
| 2767 | st->nents = 0; |
| 2768 | for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents, |
| 2769 | view->params.partial.offset) |
| 2770 | { |
| 2771 | if (st->nents >= view->params.partial.size) |
| 2772 | break; |
| 2773 | |
| 2774 | sg_set_page(sg, NULL, PAGE_SIZE, 0); |
| 2775 | sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter); |
| 2776 | sg_dma_len(sg) = PAGE_SIZE; |
| 2777 | |
| 2778 | sg = sg_next(sg); |
| 2779 | st->nents++; |
| 2780 | } |
| 2781 | |
| 2782 | return st; |
| 2783 | |
| 2784 | err_sg_alloc: |
| 2785 | kfree(st); |
| 2786 | err_st_alloc: |
| 2787 | return ERR_PTR(ret); |
| 2788 | } |
| 2789 | |
Daniel Vetter | 70b9f6f | 2015-04-14 17:35:27 +0200 | [diff] [blame] | 2790 | static int |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 2791 | i915_get_ggtt_vma_pages(struct i915_vma *vma) |
| 2792 | { |
| 2793 | int ret = 0; |
| 2794 | |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 2795 | if (vma->ggtt_view.pages) |
| 2796 | return 0; |
| 2797 | |
| 2798 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) |
| 2799 | vma->ggtt_view.pages = vma->obj->pages; |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 2800 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) |
| 2801 | vma->ggtt_view.pages = |
| 2802 | intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj); |
Joonas Lahtinen | 8bd7ef1 | 2015-05-06 14:35:38 +0300 | [diff] [blame] | 2803 | else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL) |
| 2804 | vma->ggtt_view.pages = |
| 2805 | intel_partial_pages(&vma->ggtt_view, vma->obj); |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 2806 | else |
| 2807 | WARN_ONCE(1, "GGTT view %u not implemented!\n", |
| 2808 | vma->ggtt_view.type); |
| 2809 | |
| 2810 | if (!vma->ggtt_view.pages) { |
Joonas Lahtinen | ec7adb6 | 2015-03-16 14:11:13 +0200 | [diff] [blame] | 2811 | DRM_ERROR("Failed to get pages for GGTT view type %u!\n", |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 2812 | vma->ggtt_view.type); |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 2813 | ret = -EINVAL; |
| 2814 | } else if (IS_ERR(vma->ggtt_view.pages)) { |
| 2815 | ret = PTR_ERR(vma->ggtt_view.pages); |
| 2816 | vma->ggtt_view.pages = NULL; |
| 2817 | DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", |
| 2818 | vma->ggtt_view.type, ret); |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 2819 | } |
| 2820 | |
Tvrtko Ursulin | 50470bb | 2015-03-23 11:10:36 +0000 | [diff] [blame] | 2821 | return ret; |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 2822 | } |
| 2823 | |
| 2824 | /** |
| 2825 | * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space. |
| 2826 | * @vma: VMA to map |
| 2827 | * @cache_level: mapping cache level |
| 2828 | * @flags: flags like global or local mapping |
| 2829 | * |
| 2830 | * DMA addresses are taken from the scatter-gather table of this object (or of |
| 2831 | * this VMA in case of non-default GGTT views) and PTE entries set up. |
| 2832 | * Note that DMA addresses are also the only part of the SG table we care about. |
| 2833 | */ |
| 2834 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, |
| 2835 | u32 flags) |
| 2836 | { |
Mika Kuoppala | 75d04a3 | 2015-04-28 17:56:17 +0300 | [diff] [blame] | 2837 | int ret; |
| 2838 | u32 bind_flags; |
Mika Kuoppala | 1d335d1 | 2015-04-10 15:54:58 +0300 | [diff] [blame] | 2839 | |
Mika Kuoppala | 75d04a3 | 2015-04-28 17:56:17 +0300 | [diff] [blame] | 2840 | if (WARN_ON(flags == 0)) |
| 2841 | return -EINVAL; |
Mika Kuoppala | 1d335d1 | 2015-04-10 15:54:58 +0300 | [diff] [blame] | 2842 | |
Mika Kuoppala | 75d04a3 | 2015-04-28 17:56:17 +0300 | [diff] [blame] | 2843 | bind_flags = 0; |
Daniel Vetter | 0875546 | 2015-04-20 09:04:05 -0700 | [diff] [blame] | 2844 | if (flags & PIN_GLOBAL) |
| 2845 | bind_flags |= GLOBAL_BIND; |
| 2846 | if (flags & PIN_USER) |
| 2847 | bind_flags |= LOCAL_BIND; |
| 2848 | |
| 2849 | if (flags & PIN_UPDATE) |
| 2850 | bind_flags |= vma->bound; |
| 2851 | else |
| 2852 | bind_flags &= ~vma->bound; |
| 2853 | |
Mika Kuoppala | 75d04a3 | 2015-04-28 17:56:17 +0300 | [diff] [blame] | 2854 | if (bind_flags == 0) |
| 2855 | return 0; |
| 2856 | |
| 2857 | if (vma->bound == 0 && vma->vm->allocate_va_range) { |
| 2858 | trace_i915_va_alloc(vma->vm, |
| 2859 | vma->node.start, |
| 2860 | vma->node.size, |
| 2861 | VM_TO_TRACE_NAME(vma->vm)); |
| 2862 | |
Mika Kuoppala | b2dd451 | 2015-06-25 18:35:15 +0300 | [diff] [blame] | 2863 | /* XXX: i915_vma_pin() will fix this +- hack */ |
| 2864 | vma->pin_count++; |
Mika Kuoppala | 75d04a3 | 2015-04-28 17:56:17 +0300 | [diff] [blame] | 2865 | ret = vma->vm->allocate_va_range(vma->vm, |
| 2866 | vma->node.start, |
| 2867 | vma->node.size); |
Mika Kuoppala | b2dd451 | 2015-06-25 18:35:15 +0300 | [diff] [blame] | 2868 | vma->pin_count--; |
Mika Kuoppala | 75d04a3 | 2015-04-28 17:56:17 +0300 | [diff] [blame] | 2869 | if (ret) |
| 2870 | return ret; |
| 2871 | } |
| 2872 | |
| 2873 | ret = vma->vm->bind_vma(vma, cache_level, bind_flags); |
Daniel Vetter | 70b9f6f | 2015-04-14 17:35:27 +0200 | [diff] [blame] | 2874 | if (ret) |
| 2875 | return ret; |
Daniel Vetter | 0875546 | 2015-04-20 09:04:05 -0700 | [diff] [blame] | 2876 | |
| 2877 | vma->bound |= bind_flags; |
Tvrtko Ursulin | fe14d5f | 2014-12-10 17:27:58 +0000 | [diff] [blame] | 2878 | |
| 2879 | return 0; |
| 2880 | } |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 2881 | |
| 2882 | /** |
| 2883 | * i915_ggtt_view_size - Get the size of a GGTT view. |
| 2884 | * @obj: Object the view is of. |
| 2885 | * @view: The view in question. |
| 2886 | * |
| 2887 | * @return The size of the GGTT view in bytes. |
| 2888 | */ |
| 2889 | size_t |
| 2890 | i915_ggtt_view_size(struct drm_i915_gem_object *obj, |
| 2891 | const struct i915_ggtt_view *view) |
| 2892 | { |
Tvrtko Ursulin | 9e759ff | 2015-06-23 12:57:43 +0100 | [diff] [blame] | 2893 | if (view->type == I915_GGTT_VIEW_NORMAL) { |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 2894 | return obj->base.size; |
Tvrtko Ursulin | 9e759ff | 2015-06-23 12:57:43 +0100 | [diff] [blame] | 2895 | } else if (view->type == I915_GGTT_VIEW_ROTATED) { |
| 2896 | return view->rotation_info.size; |
Joonas Lahtinen | 8bd7ef1 | 2015-05-06 14:35:38 +0300 | [diff] [blame] | 2897 | } else if (view->type == I915_GGTT_VIEW_PARTIAL) { |
| 2898 | return view->params.partial.size << PAGE_SHIFT; |
Joonas Lahtinen | 91e6711 | 2015-05-06 14:33:58 +0300 | [diff] [blame] | 2899 | } else { |
| 2900 | WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type); |
| 2901 | return obj->base.size; |
| 2902 | } |
| 2903 | } |