Blame - drivers/irqchip/Kconfig - kernel/msm-4.19

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Thomas Petazzoni	f6e916b	2012-11-20 23:00:52 +0100	[diff] [blame]	1	config IRQCHIP
				2	def_bool y
				3	depends on OF_IRQ
				4
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	5	config ARM_GIC
				6	bool
				7	select IRQ_DOMAIN
Yingjoe Chen	9a1091e	2014-11-25 16:04:19 +0800	[diff] [blame]	8	select IRQ_DOMAIN_HIERARCHY
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	9	select MULTI_IRQ_HANDLER
				10
Jon Hunter	9c8eddd	2016-06-07 16:12:34 +0100	[diff] [blame]	11	config ARM_GIC_PM
				12	bool
				13	depends on PM
				14	select ARM_GIC
				15	select PM_CLK
				16
Linus Walleij	a27d21e	2015-12-18 10:44:53 +0100	[diff] [blame]	17	config ARM_GIC_MAX_NR
				18	int
				19	default 2 if ARCH_REALVIEW
				20	default 1
				21
Suravee Suthikulpanit	853a33c	2014-11-25 18:47:22 +0000	[diff] [blame]	22	config ARM_GIC_V2M
				23	bool
Arnd Bergmann	3ee8036	2016-06-15 15:47:33 -0500	[diff] [blame]	24	depends on PCI
				25	select ARM_GIC
				26	select PCI_MSI
Suravee Suthikulpanit	853a33c	2014-11-25 18:47:22 +0000	[diff] [blame]	27
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	28	config GIC_NON_BANKED
				29	bool
				30
Marc Zyngier	021f653	2014-06-30 16:01:31 +0100	[diff] [blame]	31	config ARM_GIC_V3
				32	bool
				33	select IRQ_DOMAIN
				34	select MULTI_IRQ_HANDLER
Marc Zyngier	443acc4	2014-11-24 14:35:09 +0000	[diff] [blame]	35	select IRQ_DOMAIN_HIERARCHY
Marc Zyngier	e3825ba	2016-04-11 09:57:54 +0100	[diff] [blame]	36	select PARTITION_PERCPU
Marc Zyngier	021f653	2014-06-30 16:01:31 +0100	[diff] [blame]	37
Marc Zyngier	1981272	2014-11-24 14:35:19 +0000	[diff] [blame]	38	config ARM_GIC_V3_ITS
				39	bool
Arnd Bergmann	3ee8036	2016-06-15 15:47:33 -0500	[diff] [blame]	40	depends on PCI
				41	depends on PCI_MSI
Uwe Kleine-König	292ec08	2013-06-26 09:18:48 +0200	[diff] [blame]	42
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	43	config ARM_NVIC
				44	bool
				45	select IRQ_DOMAIN
Stefan Agner	2d9f59f	2015-05-16 11:44:16 +0200	[diff] [blame]	46	select IRQ_DOMAIN_HIERARCHY
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	47	select GENERIC_IRQ_CHIP
				48
				49	config ARM_VIC
				50	bool
				51	select IRQ_DOMAIN
				52	select MULTI_IRQ_HANDLER
				53
				54	config ARM_VIC_NR
				55	int
				56	default 4 if ARCH_S5PV210
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	57	default 2
				58	depends on ARM_VIC
				59	help
				60	The maximum number of VICs available in the system, for
				61	power management.
				62
Thomas Petazzoni	fed6d33	2016-02-10 15:46:56 +0100	[diff] [blame]	63	config ARMADA_370_XP_IRQ
				64	bool
Thomas Petazzoni	fed6d33	2016-02-10 15:46:56 +0100	[diff] [blame]	65	select GENERIC_IRQ_CHIP
Arnd Bergmann	3ee8036	2016-06-15 15:47:33 -0500	[diff] [blame]	66	select PCI_MSI if PCI
Thomas Petazzoni	fed6d33	2016-02-10 15:46:56 +0100	[diff] [blame]	67
Antoine Tenart	e6b78f2	2016-02-19 16:22:44 +0100	[diff] [blame]	68	config ALPINE_MSI
				69	bool
Arnd Bergmann	3ee8036	2016-06-15 15:47:33 -0500	[diff] [blame]	70	depends on PCI
				71	select PCI_MSI
Antoine Tenart	e6b78f2	2016-02-19 16:22:44 +0100	[diff] [blame]	72	select GENERIC_IRQ_CHIP
Antoine Tenart	e6b78f2	2016-02-19 16:22:44 +0100	[diff] [blame]	73
Boris BREZILLON	b1479eb	2014-07-10 19:14:18 +0200	[diff] [blame]	74	config ATMEL_AIC_IRQ
				75	bool
				76	select GENERIC_IRQ_CHIP
				77	select IRQ_DOMAIN
				78	select MULTI_IRQ_HANDLER
				79	select SPARSE_IRQ
				80
				81	config ATMEL_AIC5_IRQ
				82	bool
				83	select GENERIC_IRQ_CHIP
				84	select IRQ_DOMAIN
				85	select MULTI_IRQ_HANDLER
				86	select SPARSE_IRQ
				87
Ralf Baechle	0509cfd	2015-07-08 14:46:08 +0200	[diff] [blame]	88	config I8259
				89	bool
				90	select IRQ_DOMAIN
				91
Simon Arlott	c7c42ec	2015-11-22 14:30:14 +0000	[diff] [blame]	92	config BCM6345_L1_IRQ
				93	bool
				94	select GENERIC_IRQ_CHIP
				95	select IRQ_DOMAIN
				96
Kevin Cernekee	5f7f031	2014-12-25 09:49:06 -0800	[diff] [blame]	97	config BCM7038_L1_IRQ
				98	bool
				99	select GENERIC_IRQ_CHIP
				100	select IRQ_DOMAIN
				101
Kevin Cernekee	a4fcbb8	2014-11-06 22:44:27 -0800	[diff] [blame]	102	config BCM7120_L2_IRQ
				103	bool
				104	select GENERIC_IRQ_CHIP
				105	select IRQ_DOMAIN
				106
Florian Fainelli	7f646e9	2014-05-23 17:40:53 -0700	[diff] [blame]	107	config BRCMSTB_L2_IRQ
				108	bool
Florian Fainelli	7f646e9	2014-05-23 17:40:53 -0700	[diff] [blame]	109	select GENERIC_IRQ_CHIP
				110	select IRQ_DOMAIN
				111
Sebastian Hesselbarth	350d71b9	2013-09-09 14:01:20 +0200	[diff] [blame]	112	config DW_APB_ICTL
				113	bool
Jisheng Zhang	e158849	2014-10-22 20:59:10 +0800	[diff] [blame]	114	select GENERIC_IRQ_CHIP
Sebastian Hesselbarth	350d71b9	2013-09-09 14:01:20 +0200	[diff] [blame]	115	select IRQ_DOMAIN
				116
MaJun	9a7c4ab	2016-03-23 17:06:33 +0800	[diff] [blame]	117	config HISILICON_IRQ_MBIGEN
				118	bool
				119	select ARM_GIC_V3
				120	select ARM_GIC_V3_ITS
MaJun	9a7c4ab	2016-03-23 17:06:33 +0800	[diff] [blame]	121
James Hogan	b6ef916	2013-04-22 15:43:50 +0100	[diff] [blame]	122	config IMGPDC_IRQ
				123	bool
				124	select GENERIC_IRQ_CHIP
				125	select IRQ_DOMAIN
				126
Ralf Baechle	67e38cf	2015-05-26 18:20:06 +0200	[diff] [blame]	127	config IRQ_MIPS_CPU
				128	bool
				129	select GENERIC_IRQ_CHIP
				130	select IRQ_DOMAIN
				131
Alexander Shiyan	afc98d9	2014-02-02 12:07:46 +0400	[diff] [blame]	132	config CLPS711X_IRQCHIP
				133	bool
				134	depends on ARCH_CLPS711X
				135	select IRQ_DOMAIN
				136	select MULTI_IRQ_HANDLER
				137	select SPARSE_IRQ
				138	default y
				139
Stefan Kristiansson	4db8e6d	2014-05-26 23:31:42 +0300	[diff] [blame]	140	config OR1K_PIC
				141	bool
				142	select IRQ_DOMAIN
				143
Felipe Balbi	8598066	2014-09-15 16:15:02 -0500	[diff] [blame]	144	config OMAP_IRQCHIP
				145	bool
				146	select GENERIC_IRQ_CHIP
				147	select IRQ_DOMAIN
				148
Sebastian Hesselbarth	9dbd90f	2013-06-06 18:27:09 +0200	[diff] [blame]	149	config ORION_IRQCHIP
				150	bool
				151	select IRQ_DOMAIN
				152	select MULTI_IRQ_HANDLER
				153
Cristian Birsan	aaa8666	2016-01-13 18:15:35 -0700	[diff] [blame]	154	config PIC32_EVIC
				155	bool
				156	select GENERIC_IRQ_CHIP
				157	select IRQ_DOMAIN
				158
Magnus Damm	4435804	2013-02-18 23:28:34 +0900	[diff] [blame]	159	config RENESAS_INTC_IRQPIN
				160	bool
				161	select IRQ_DOMAIN
				162
Magnus Damm	fbc83b7	2013-02-27 17:15:01 +0900	[diff] [blame]	163	config RENESAS_IRQC
				164	bool
Magnus Damm	99c221d	2015-09-28 18:42:37 +0900	[diff] [blame]	165	select GENERIC_IRQ_CHIP
Magnus Damm	fbc83b7	2013-02-27 17:15:01 +0900	[diff] [blame]	166	select IRQ_DOMAIN
				167
Lee Jones	0708848	2015-02-18 15:13:58 +0000	[diff] [blame]	168	config ST_IRQCHIP
				169	bool
				170	select REGMAP
				171	select MFD_SYSCON
				172	help
				173	Enables SysCfg Controlled IRQs on STi based platforms.
				174
Mans Rullgard	4bba668	2016-01-20 18:07:17 +0000	[diff] [blame]	175	config TANGO_IRQ
				176	bool
				177	select IRQ_DOMAIN
				178	select GENERIC_IRQ_CHIP
				179
Christian Ruppert	b06eb01	2013-06-25 18:29:57 +0200	[diff] [blame]	180	config TB10X_IRQC
				181	bool
				182	select IRQ_DOMAIN
				183	select GENERIC_IRQ_CHIP
				184
Damien Riegel	d01f863	2015-12-21 15:11:23 -0500	[diff] [blame]	185	config TS4800_IRQ
				186	tristate "TS-4800 IRQ controller"
				187	select IRQ_DOMAIN
Richard Weinberger	0df337c	2016-01-25 23:24:17 +0100	[diff] [blame]	188	depends on HAS_IOMEM
Jean Delvare	d2b383d	2016-02-09 11:19:20 +0100	[diff] [blame]	189	depends on SOC_IMX51 \|\| COMPILE_TEST
Damien Riegel	d01f863	2015-12-21 15:11:23 -0500	[diff] [blame]	190	help
				191	Support for the TS-4800 FPGA IRQ controller
				192
Linus Walleij	2389d50	2012-10-31 22:04:31 +0100	[diff] [blame]	193	config VERSATILE_FPGA_IRQ
				194	bool
				195	select IRQ_DOMAIN
				196
				197	config VERSATILE_FPGA_IRQ_NR
				198	int
				199	default 4
				200	depends on VERSATILE_FPGA_IRQ
Max Filippov	26a8e96	2013-12-01 12:04:57 +0400	[diff] [blame]	201
				202	config XTENSA_MX
				203	bool
				204	select IRQ_DOMAIN
Sricharan R	96ca848	2013-12-03 15:57:23 +0530	[diff] [blame]	205
				206	config IRQ_CROSSBAR
				207	bool
				208	help
Masanari Iida	f54619f	2014-09-18 12:09:42 +0900	[diff] [blame]	209	Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R	96ca848	2013-12-03 15:57:23 +0530	[diff] [blame]	210	The primary irqchip invokes the crossbar's callback which inturn allocates
				211	a free irq and configures the IP. Thus the peripheral interrupts are
				212	routed to one of the free irqchip interrupt lines.
Grygorii Strashko	89323f8	2014-07-23 17:40:30 +0300	[diff] [blame]	213
				214	config KEYSTONE_IRQ
				215	tristate "Keystone 2 IRQ controller IP"
				216	depends on ARCH_KEYSTONE
				217	help
				218	Support for Texas Instruments Keystone 2 IRQ controller IP which
				219	is part of the Keystone 2 IPC mechanism
Andrew Bresticker	8a19b8f	2014-09-18 14:47:19 -0700	[diff] [blame]	220
				221	config MIPS_GIC
				222	bool
Qais Yousef	bb11cff	2015-12-08 13:20:28 +0000	[diff] [blame]	223	select GENERIC_IRQ_IPI
Qais Yousef	2af70a9	2015-12-08 13:20:23 +0000	[diff] [blame]	224	select IRQ_DOMAIN_HIERARCHY
Andrew Bresticker	8a19b8f	2014-09-18 14:47:19 -0700	[diff] [blame]	225	select MIPS_CM
Yoshinori Sato	8a76448	2015-05-10 02:30:47 +0900	[diff] [blame]	226
Paul Burton	44e08e7	2015-05-24 16:11:31 +0100	[diff] [blame]	227	config INGENIC_IRQ
				228	bool
				229	depends on MACH_INGENIC
				230	default y
Linus Torvalds	78c10e5	2015-06-27 12:44:34 -0700	[diff] [blame]	231
Yoshinori Sato	8a76448	2015-05-10 02:30:47 +0900	[diff] [blame]	232	config RENESAS_H8300H_INTC
				233	bool
				234	select IRQ_DOMAIN
				235
				236	config RENESAS_H8S_INTC
				237	bool
Linus Torvalds	78c10e5	2015-06-27 12:44:34 -0700	[diff] [blame]	238	select IRQ_DOMAIN
Shenwei Wang	e324c4d	2015-08-24 14:04:15 -0500	[diff] [blame]	239
				240	config IMX_GPCV2
				241	bool
				242	select IRQ_DOMAIN
				243	help
				244	Enables the wakeup IRQs for IMX platforms with GPCv2 block
Oleksij Rempel	7e4ac67	2015-10-12 21:15:34 +0200	[diff] [blame]	245
				246	config IRQ_MXS
				247	def_bool y if MACH_ASM9260 \|\| ARCH_MXS
				248	select IRQ_DOMAIN
				249	select STMP_DEVICE
Thomas Petazzoni	c27f29b	2016-02-19 14:34:43 +0100	[diff] [blame]	250
				251	config MVEBU_ODMI
				252	bool
Marc Zyngier	9e2c986	2016-04-11 09:57:53 +0100	[diff] [blame]	253
Minghuan Lian	b8f3ebe	2016-03-23 19:08:20 +0800	[diff] [blame]	254	config LS_SCFG_MSI
				255	def_bool y if SOC_LS1021A \|\| ARCH_LAYERSCAPE
				256	depends on PCI && PCI_MSI
Minghuan Lian	b8f3ebe	2016-03-23 19:08:20 +0800	[diff] [blame]	257
Marc Zyngier	9e2c986	2016-04-11 09:57:53 +0100	[diff] [blame]	258	config PARTITION_PERCPU
				259	bool
Linus Torvalds	0efacbb	2016-05-19 09:46:18 -0700	[diff] [blame]	260
Noam Camus	44df427c	2015-10-29 00:26:22 +0200	[diff] [blame]	261	config EZNPS_GIC
				262	bool "NPS400 Global Interrupt Manager (GIM)"
Arnd Bergmann	ffd565e	2016-05-12 23:03:35 +0200	[diff] [blame]	263	depends on ARC \|\| (COMPILE_TEST && !64BIT)
Noam Camus	44df427c	2015-10-29 00:26:22 +0200	[diff] [blame]	264	select IRQ_DOMAIN
				265	help
				266	Support the EZchip NPS400 global interrupt controller