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gerrit-public.fairphone.software / kernel / msm-4.19 / 7af8884a175b56851ece09e47c74948c3160c07c / . / arch / arm / boot / dts / am33xx.dtsi
blob: c87bf4b8acf2423e99228abc3bbcac58f13fac92 [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard6a8a6b62013-06-03 16:12:25 +0200[diff] [blame]12#include <dt-bindings/pinctrl/am33xx.h>
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]13
Florian Vaussardeb33ef662013-06-03 16:12:22 +0200[diff] [blame]14#include "skeleton.dtsi"
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]15
16/ {
17 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]18 interrupt-parent = <&intc>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]19
20 aliases {
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]21 serial0 = &uart0;
22 serial1 = &uart1;
23 serial2 = &uart2;
24 serial3 = &uart3;
25 serial4 = &uart4;
26 serial5 = &uart5;
AnilKumar Ch7a57ee82012-11-14 23:38:24 +0530[diff] [blame]27 d_can0 = &dcan0;
28 d_can1 = &dcan1;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]29 usb0 = &usb0;
30 usb1 = &usb1;
31 phy0 = &usb0_phy;
32 phy1 = &usb1_phy;
Dan Murphy81700562013-10-02 12:58:33 -0500[diff] [blame]33 ethernet0 = &cpsw_emac0;
34 ethernet1 = &cpsw_emac1;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]35 };
36
37 cpus {
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]38 #address-cells = <1>;
39 #size-cells = <0>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]40 cpu@0 {
41 compatible = "arm,cortex-a8";
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]42 device_type = "cpu";
43 reg = <0>;
AnilKumar Chefeedcf22012-08-31 15:07:20 +0530[diff] [blame]44
45 /*
46 * To consider voltage drop between PMIC and SoC,
47 * tolerance value is reduced to 2% from 4% and
48 * voltage value is increased as a precaution.
49 */
50 operating-points = <
51 /* kHz uV */
52 720000 1285000
53 600000 1225000
54 500000 1125000
55 275000 1125000
56 >;
57 voltage-tolerance = <2>; /* 2 percentage */
58 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]59 };
60 };
61
Alexandre Belloni6797cdb2013-08-03 20:00:54 +0200[diff] [blame]62 pmu {
63 compatible = "arm,cortex-a8-pmu";
64 interrupts = <3>;
65 };
66
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]67 /*
68 * The soc node represents the soc top level view. It is uses for IPs
69 * that are not memory mapped in the MPU view or for the MPU itself.
70 */
71 soc {
72 compatible = "ti,omap-infra";
73 mpu {
74 compatible = "ti,omap3-mpu";
75 ti,hwmods = "mpu";
76 };
77 };
78
AnilKumar Chb552dfc2012-09-20 02:49:26 +0530[diff] [blame]79 am33xx_pinmux: pinmux@44e10800 {
80 compatible = "pinctrl-single";
81 reg = <0x44e10800 0x0238>;
82 #address-cells = <1>;
83 #size-cells = <0>;
84 pinctrl-single,register-width = <32>;
85 pinctrl-single,function-mask = <0x7f>;
86 };
87
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]88 /*
89 * XXX: Use a flat representation of the AM33XX interconnect.
90 * The real AM33XX interconnect network is quite complex.Since
91 * that will not bring real advantage to represent that in DT
92 * for the moment, just use a fake OCP bus entry to represent
93 * the whole bus hierarchy.
94 */
95 ocp {
96 compatible = "simple-bus";
97 #address-cells = <1>;
98 #size-cells = <1>;
99 ranges;
100 ti,hwmods = "l3_main";
101
102 intc: interrupt-controller@48200000 {
103 compatible = "ti,omap2-intc";
104 interrupt-controller;
105 #interrupt-cells = <1>;
106 ti,intc-size = <128>;
107 reg = <0x48200000 0x1000>;
108 };
109
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]110 edma: edma@49000000 {
111 compatible = "ti,edma3";
112 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
113 reg = <0x49000000 0x10000>,
114 <0x44e10f90 0x10>;
115 interrupts = <12 13 14>;
116 #dma-cells = <1>;
117 dma-channels = <64>;
118 ti,edma-regions = <4>;
119 ti,edma-slots = <256>;
120 };
121
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]122 gpio0: gpio@44e07000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]123 compatible = "ti,omap4-gpio";
124 ti,hwmods = "gpio1";
125 gpio-controller;
126 #gpio-cells = <2>;
127 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]128 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]129 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]130 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]131 };
132
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]133 gpio1: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]134 compatible = "ti,omap4-gpio";
135 ti,hwmods = "gpio2";
136 gpio-controller;
137 #gpio-cells = <2>;
138 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]139 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]140 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]141 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]142 };
143
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]144 gpio2: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]145 compatible = "ti,omap4-gpio";
146 ti,hwmods = "gpio3";
147 gpio-controller;
148 #gpio-cells = <2>;
149 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]150 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]151 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]152 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]153 };
154
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]155 gpio3: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]156 compatible = "ti,omap4-gpio";
157 ti,hwmods = "gpio4";
158 gpio-controller;
159 #gpio-cells = <2>;
160 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]161 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]162 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]163 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]164 };
165
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]166 uart0: serial@44e09000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]167 compatible = "ti,omap3-uart";
168 ti,hwmods = "uart1";
169 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]170 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]171 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]172 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]173 };
174
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]175 uart1: serial@48022000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]176 compatible = "ti,omap3-uart";
177 ti,hwmods = "uart2";
178 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]179 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]180 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]181 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]182 };
183
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]184 uart2: serial@48024000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]185 compatible = "ti,omap3-uart";
186 ti,hwmods = "uart3";
187 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]188 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]189 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]190 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]191 };
192
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]193 uart3: serial@481a6000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]194 compatible = "ti,omap3-uart";
195 ti,hwmods = "uart4";
196 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]197 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]198 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]199 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]200 };
201
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]202 uart4: serial@481a8000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]203 compatible = "ti,omap3-uart";
204 ti,hwmods = "uart5";
205 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]206 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]207 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]208 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]209 };
210
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]211 uart5: serial@481aa000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]212 compatible = "ti,omap3-uart";
213 ti,hwmods = "uart6";
214 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]215 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]216 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]217 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]218 };
219
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]220 i2c0: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]221 compatible = "ti,omap4-i2c";
222 #address-cells = <1>;
223 #size-cells = <0>;
224 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]225 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]226 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]227 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]228 };
229
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]230 i2c1: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]231 compatible = "ti,omap4-i2c";
232 #address-cells = <1>;
233 #size-cells = <0>;
234 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]235 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]236 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]237 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]238 };
239
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]240 i2c2: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]241 compatible = "ti,omap4-i2c";
242 #address-cells = <1>;
243 #size-cells = <0>;
244 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]245 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]246 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]247 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]248 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]249
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]250 mmc1: mmc@48060000 {
251 compatible = "ti,omap4-hsmmc";
252 ti,hwmods = "mmc1";
253 ti,dual-volt;
254 ti,needs-special-reset;
255 ti,needs-special-hs-handling;
256 dmas = <&edma 24
257 &edma 25>;
258 dma-names = "tx", "rx";
259 interrupts = <64>;
260 interrupt-parent = <&intc>;
261 reg = <0x48060000 0x1000>;
262 status = "disabled";
263 };
264
265 mmc2: mmc@481d8000 {
266 compatible = "ti,omap4-hsmmc";
267 ti,hwmods = "mmc2";
268 ti,needs-special-reset;
269 dmas = <&edma 2
270 &edma 3>;
271 dma-names = "tx", "rx";
272 interrupts = <28>;
273 interrupt-parent = <&intc>;
274 reg = <0x481d8000 0x1000>;
275 status = "disabled";
276 };
277
278 mmc3: mmc@47810000 {
279 compatible = "ti,omap4-hsmmc";
280 ti,hwmods = "mmc3";
281 ti,needs-special-reset;
282 interrupts = <29>;
283 interrupt-parent = <&intc>;
284 reg = <0x47810000 0x1000>;
285 status = "disabled";
286 };
287
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]288 wdt2: wdt@44e35000 {
289 compatible = "ti,omap3-wdt";
290 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]291 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]292 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]293 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]294
295 dcan0: d_can@481cc000 {
296 compatible = "bosch,d_can";
297 ti,hwmods = "d_can0";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]298 reg = <0x481cc000 0x2000
299 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]300 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]301 status = "disabled";
302 };
303
304 dcan1: d_can@481d0000 {
305 compatible = "bosch,d_can";
306 ti,hwmods = "d_can1";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]307 reg = <0x481d0000 0x2000
308 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]309 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]310 status = "disabled";
311 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]312
313 timer1: timer@44e31000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]314 compatible = "ti,am335x-timer-1ms";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]315 reg = <0x44e31000 0x400>;
316 interrupts = <67>;
317 ti,hwmods = "timer1";
318 ti,timer-alwon;
319 };
320
321 timer2: timer@48040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]322 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]323 reg = <0x48040000 0x400>;
324 interrupts = <68>;
325 ti,hwmods = "timer2";
326 };
327
328 timer3: timer@48042000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]329 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]330 reg = <0x48042000 0x400>;
331 interrupts = <69>;
332 ti,hwmods = "timer3";
333 };
334
335 timer4: timer@48044000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]336 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]337 reg = <0x48044000 0x400>;
338 interrupts = <92>;
339 ti,hwmods = "timer4";
340 ti,timer-pwm;
341 };
342
343 timer5: timer@48046000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]344 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]345 reg = <0x48046000 0x400>;
346 interrupts = <93>;
347 ti,hwmods = "timer5";
348 ti,timer-pwm;
349 };
350
351 timer6: timer@48048000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]352 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]353 reg = <0x48048000 0x400>;
354 interrupts = <94>;
355 ti,hwmods = "timer6";
356 ti,timer-pwm;
357 };
358
359 timer7: timer@4804a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]360 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]361 reg = <0x4804a000 0x400>;
362 interrupts = <95>;
363 ti,hwmods = "timer7";
364 ti,timer-pwm;
365 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]366
367 rtc@44e3e000 {
368 compatible = "ti,da830-rtc";
369 reg = <0x44e3e000 0x1000>;
370 interrupts = <75
371 76>;
372 ti,hwmods = "rtc";
373 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]374
375 spi0: spi@48030000 {
376 compatible = "ti,omap4-mcspi";
377 #address-cells = <1>;
378 #size-cells = <0>;
379 reg = <0x48030000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]380 interrupts = <65>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]381 ti,spi-num-cs = <2>;
382 ti,hwmods = "spi0";
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]383 dmas = <&edma 16
384 &edma 17
385 &edma 18
386 &edma 19>;
387 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]388 status = "disabled";
389 };
390
391 spi1: spi@481a0000 {
392 compatible = "ti,omap4-mcspi";
393 #address-cells = <1>;
394 #size-cells = <0>;
395 reg = <0x481a0000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]396 interrupts = <125>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]397 ti,spi-num-cs = <2>;
398 ti,hwmods = "spi1";
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]399 dmas = <&edma 42
400 &edma 43
401 &edma 44
402 &edma 45>;
403 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]404 status = "disabled";
405 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]406
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]407 usb: usb@47400000 {
408 compatible = "ti,am33xx-usb";
409 reg = <0x47400000 0x1000>;
410 ranges;
411 #address-cells = <1>;
412 #size-cells = <1>;
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]413 ti,hwmods = "usb_otg_hs";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]414 status = "disabled";
415
416 ctrl_mod: control@44e10000 {
417 compatible = "ti,am335x-usb-ctrl-module";
418 reg = <0x44e10620 0x10
419 0x44e10648 0x4>;
420 reg-names = "phy_ctrl", "wakeup";
421 status = "disabled";
422 };
423
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]424 usb0_phy: usb-phy@47401300 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]425 compatible = "ti,am335x-usb-phy";
426 reg = <0x47401300 0x100>;
427 reg-names = "phy";
428 status = "disabled";
429 ti,ctrl_mod = <&ctrl_mod>;
430 };
431
432 usb0: usb@47401000 {
433 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]434 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]435 reg = <0x47401400 0x400
436 0x47401000 0x200>;
437 reg-names = "mc", "control";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]438
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]439 interrupts = <18>;
440 interrupt-names = "mc";
441 dr_mode = "otg";
442 mentor,multipoint = <1>;
443 mentor,num-eps = <16>;
444 mentor,ram-bits = <12>;
445 mentor,power = <500>;
446 phys = <&usb0_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]447
448 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
449 &cppi41dma 2 0 &cppi41dma 3 0
450 &cppi41dma 4 0 &cppi41dma 5 0
451 &cppi41dma 6 0 &cppi41dma 7 0
452 &cppi41dma 8 0 &cppi41dma 9 0
453 &cppi41dma 10 0 &cppi41dma 11 0
454 &cppi41dma 12 0 &cppi41dma 13 0
455 &cppi41dma 14 0 &cppi41dma 0 1
456 &cppi41dma 1 1 &cppi41dma 2 1
457 &cppi41dma 3 1 &cppi41dma 4 1
458 &cppi41dma 5 1 &cppi41dma 6 1
459 &cppi41dma 7 1 &cppi41dma 8 1
460 &cppi41dma 9 1 &cppi41dma 10 1
461 &cppi41dma 11 1 &cppi41dma 12 1
462 &cppi41dma 13 1 &cppi41dma 14 1>;
463 dma-names =
464 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
465 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
466 "rx14", "rx15",
467 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
468 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
469 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]470 };
471
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]472 usb1_phy: usb-phy@47401b00 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]473 compatible = "ti,am335x-usb-phy";
474 reg = <0x47401b00 0x100>;
475 reg-names = "phy";
476 status = "disabled";
477 ti,ctrl_mod = <&ctrl_mod>;
478 };
479
480 usb1: usb@47401800 {
481 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]482 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]483 reg = <0x47401c00 0x400
484 0x47401800 0x200>;
485 reg-names = "mc", "control";
486 interrupts = <19>;
487 interrupt-names = "mc";
488 dr_mode = "otg";
489 mentor,multipoint = <1>;
490 mentor,num-eps = <16>;
491 mentor,ram-bits = <12>;
492 mentor,power = <500>;
493 phys = <&usb1_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]494
495 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
496 &cppi41dma 17 0 &cppi41dma 18 0
497 &cppi41dma 19 0 &cppi41dma 20 0
498 &cppi41dma 21 0 &cppi41dma 22 0
499 &cppi41dma 23 0 &cppi41dma 24 0
500 &cppi41dma 25 0 &cppi41dma 26 0
501 &cppi41dma 27 0 &cppi41dma 28 0
502 &cppi41dma 29 0 &cppi41dma 15 1
503 &cppi41dma 16 1 &cppi41dma 17 1
504 &cppi41dma 18 1 &cppi41dma 19 1
505 &cppi41dma 20 1 &cppi41dma 21 1
506 &cppi41dma 22 1 &cppi41dma 23 1
507 &cppi41dma 24 1 &cppi41dma 25 1
508 &cppi41dma 26 1 &cppi41dma 27 1
509 &cppi41dma 28 1 &cppi41dma 29 1>;
510 dma-names =
511 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
512 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
513 "rx14", "rx15",
514 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
515 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
516 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]517 };
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]518
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]519 cppi41dma: dma-controller@07402000 {
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]520 compatible = "ti,am3359-cppi41";
521 reg = <0x47400000 0x1000
522 0x47402000 0x1000
523 0x47403000 0x1000
524 0x47404000 0x4000>;
Sebastian Andrzej Siewior3b6394b2013-08-20 18:35:45 +0200[diff] [blame]525 reg-names = "glue", "controller", "scheduler", "queuemgr";
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]526 interrupts = <17>;
527 interrupt-names = "glue";
528 #dma-cells = <2>;
529 #dma-channels = <30>;
530 #dma-requests = <256>;
531 status = "disabled";
532 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]533 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]534
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]535 epwmss0: epwmss@48300000 {
536 compatible = "ti,am33xx-pwmss";
537 reg = <0x48300000 0x10>;
538 ti,hwmods = "epwmss0";
539 #address-cells = <1>;
540 #size-cells = <1>;
541 status = "disabled";
542 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
543 0x48300180 0x48300180 0x80 /* EQEP */
544 0x48300200 0x48300200 0x80>; /* EHRPWM */
545
546 ecap0: ecap@48300100 {
547 compatible = "ti,am33xx-ecap";
548 #pwm-cells = <3>;
549 reg = <0x48300100 0x80>;
550 ti,hwmods = "ecap0";
551 status = "disabled";
552 };
553
554 ehrpwm0: ehrpwm@48300200 {
555 compatible = "ti,am33xx-ehrpwm";
556 #pwm-cells = <3>;
557 reg = <0x48300200 0x80>;
558 ti,hwmods = "ehrpwm0";
559 status = "disabled";
560 };
561 };
562
563 epwmss1: epwmss@48302000 {
564 compatible = "ti,am33xx-pwmss";
565 reg = <0x48302000 0x10>;
566 ti,hwmods = "epwmss1";
567 #address-cells = <1>;
568 #size-cells = <1>;
569 status = "disabled";
570 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
571 0x48302180 0x48302180 0x80 /* EQEP */
572 0x48302200 0x48302200 0x80>; /* EHRPWM */
573
574 ecap1: ecap@48302100 {
575 compatible = "ti,am33xx-ecap";
576 #pwm-cells = <3>;
577 reg = <0x48302100 0x80>;
578 ti,hwmods = "ecap1";
579 status = "disabled";
580 };
581
582 ehrpwm1: ehrpwm@48302200 {
583 compatible = "ti,am33xx-ehrpwm";
584 #pwm-cells = <3>;
585 reg = <0x48302200 0x80>;
586 ti,hwmods = "ehrpwm1";
587 status = "disabled";
588 };
589 };
590
591 epwmss2: epwmss@48304000 {
592 compatible = "ti,am33xx-pwmss";
593 reg = <0x48304000 0x10>;
594 ti,hwmods = "epwmss2";
595 #address-cells = <1>;
596 #size-cells = <1>;
597 status = "disabled";
598 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
599 0x48304180 0x48304180 0x80 /* EQEP */
600 0x48304200 0x48304200 0x80>; /* EHRPWM */
601
602 ecap2: ecap@48304100 {
603 compatible = "ti,am33xx-ecap";
604 #pwm-cells = <3>;
605 reg = <0x48304100 0x80>;
606 ti,hwmods = "ecap2";
607 status = "disabled";
608 };
609
610 ehrpwm2: ehrpwm@48304200 {
611 compatible = "ti,am33xx-ehrpwm";
612 #pwm-cells = <3>;
613 reg = <0x48304200 0x80>;
614 ti,hwmods = "ehrpwm2";
615 status = "disabled";
616 };
617 };
618
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]619 mac: ethernet@4a100000 {
620 compatible = "ti,cpsw";
621 ti,hwmods = "cpgmac0";
622 cpdma_channels = <8>;
623 ale_entries = <1024>;
624 bd_ram_size = <0x2000>;
625 no_bd_ram = <0>;
626 rx_descs = <64>;
627 mac_control = <0x20>;
628 slaves = <2>;
Mugunthan V Ne86ac132013-03-11 23:16:35 +0000[diff] [blame]629 active_slave = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]630 cpts_clock_mult = <0x80000000>;
631 cpts_clock_shift = <29>;
632 reg = <0x4a100000 0x800
633 0x4a101200 0x100>;
634 #address-cells = <1>;
635 #size-cells = <1>;
636 interrupt-parent = <&intc>;
637 /*
638 * c0_rx_thresh_pend
639 * c0_rx_pend
640 * c0_tx_pend
641 * c0_misc_pend
642 */
643 interrupts = <40 41 42 43>;
644 ranges;
645
646 davinci_mdio: mdio@4a101000 {
647 compatible = "ti,davinci_mdio";
648 #address-cells = <1>;
649 #size-cells = <0>;
650 ti,hwmods = "davinci_mdio";
651 bus_freq = <1000000>;
652 reg = <0x4a101000 0x100>;
653 };
654
655 cpsw_emac0: slave@4a100200 {
656 /* Filled in by U-Boot */
657 mac-address = [ 00 00 00 00 00 00 ];
658 };
659
660 cpsw_emac1: slave@4a100300 {
661 /* Filled in by U-Boot */
662 mac-address = [ 00 00 00 00 00 00 ];
663 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]664 };
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]665
666 ocmcram: ocmcram@40300000 {
667 compatible = "ti,am3352-ocmcram";
668 reg = <0x40300000 0x10000>;
669 ti,hwmods = "ocmcram";
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]670 };
671
672 wkup_m3: wkup_m3@44d00000 {
673 compatible = "ti,am3353-wkup-m3";
674 reg = <0x44d00000 0x4000 /* M3 UMEM */
675 0x44d80000 0x2000>; /* M3 DMEM */
676 ti,hwmods = "wkup_m3";
677 };
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]678
Philip, Avinash15e82462013-05-31 13:19:03 +0530[diff] [blame]679 elm: elm@48080000 {
680 compatible = "ti,am3352-elm";
681 reg = <0x48080000 0x2000>;
682 interrupts = <4>;
683 ti,hwmods = "elm";
684 status = "disabled";
685 };
686
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]687 tscadc: tscadc@44e0d000 {
688 compatible = "ti,am3359-tscadc";
689 reg = <0x44e0d000 0x1000>;
690 interrupt-parent = <&intc>;
691 interrupts = <16>;
692 ti,hwmods = "adc_tsc";
693 status = "disabled";
694
695 tsc {
696 compatible = "ti,am3359-tsc";
697 };
698 am335x_adc: adc {
699 #io-channel-cells = <1>;
700 compatible = "ti,am3359-adc";
701 };
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]702 };
703
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]704 gpmc: gpmc@50000000 {
705 compatible = "ti,am3352-gpmc";
706 ti,hwmods = "gpmc";
707 reg = <0x50000000 0x2000>;
708 interrupts = <100>;
Lars Poeschel00dddca2013-05-28 10:24:57 +0200[diff] [blame]709 gpmc,num-cs = <7>;
710 gpmc,num-waitpins = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]711 #address-cells = <2>;
712 #size-cells = <1>;
713 status = "disabled";
714 };
Mark A. Greerf8302e12013-08-23 14:12:35 -0700[diff] [blame]715
716 sham: sham@53100000 {
717 compatible = "ti,omap4-sham";
718 ti,hwmods = "sham";
719 reg = <0x53100000 0x200>;
720 interrupts = <109>;
721 dmas = <&edma 36>;
722 dma-names = "rx";
723 };
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]724
725 aes: aes@53500000 {
726 compatible = "ti,omap4-aes";
727 ti,hwmods = "aes";
728 reg = <0x53500000 0xa0>;
Joel Fernandes7af88842013-07-17 19:07:52 -0500[diff] [blame^]729 interrupts = <103>;
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]730 dmas = <&edma 6>,
731 <&edma 5>;
732 dma-names = "tx", "rx";
733 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]734 };
735};