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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * PCI Bus Services, see include/linux/pci.h for further explanation.
3 *
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
6 *
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */
9
10#include <linux/kernel.h>
11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/pci.h>
David Brownell075c1772007-04-26 00:12:06 -070014#include <linux/pm.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090015#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070016#include <linux/module.h>
17#include <linux/spinlock.h>
Tim Schmielau4e57b682005-10-30 15:03:48 -080018#include <linux/string.h>
vignesh babu229f5af2007-08-13 18:23:14 +053019#include <linux/log2.h>
Shaohua Li7d715a62008-02-25 09:46:41 +080020#include <linux/pci-aspm.h>
Stephen Rothwellc300bd2fb2008-07-10 02:16:44 +020021#include <linux/pm_wakeup.h>
Sheng Yang8dd7f802008-10-21 17:38:25 +080022#include <linux/interrupt.h>
Yuji Shimada32a9a6822009-03-16 17:13:39 +090023#include <linux/device.h>
Rafael J. Wysockib67ea762010-02-17 23:44:09 +010024#include <linux/pm_runtime.h>
Alex Williamson608c3882013-08-08 14:09:43 -060025#include <linux/pci_hotplug.h>
Bjorn Helgaas284f5f92012-04-30 15:21:02 -060026#include <asm-generic/pci-bridge.h>
Yuji Shimada32a9a6822009-03-16 17:13:39 +090027#include <asm/setup.h>
Greg KHbc56b9e2005-04-08 14:53:31 +090028#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
Alan Stern00240c32009-04-27 13:33:16 -040030const char *pci_power_names[] = {
31 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
32};
33EXPORT_SYMBOL_GPL(pci_power_names);
34
Rafael J. Wysocki93177a72010-01-02 22:57:24 +010035int isa_dma_bridge_buggy;
36EXPORT_SYMBOL(isa_dma_bridge_buggy);
37
38int pci_pci_problems;
39EXPORT_SYMBOL(pci_pci_problems);
40
Rafael J. Wysocki1ae861e2009-12-31 12:15:54 +010041unsigned int pci_pm_d3_delay;
42
Matthew Garrettdf17e622010-10-04 14:22:29 -040043static void pci_pme_list_scan(struct work_struct *work);
44
45static LIST_HEAD(pci_pme_list);
46static DEFINE_MUTEX(pci_pme_list_mutex);
47static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
48
49struct pci_pme_device {
50 struct list_head list;
51 struct pci_dev *dev;
52};
53
54#define PME_TIMEOUT 1000 /* How long between PME checks */
55
Rafael J. Wysocki1ae861e2009-12-31 12:15:54 +010056static void pci_dev_d3_sleep(struct pci_dev *dev)
57{
58 unsigned int delay = dev->d3_delay;
59
60 if (delay < pci_pm_d3_delay)
61 delay = pci_pm_d3_delay;
62
63 msleep(delay);
64}
Linus Torvalds1da177e2005-04-16 15:20:36 -070065
Jeff Garzik32a2eea2007-10-11 16:57:27 -040066#ifdef CONFIG_PCI_DOMAINS
67int pci_domains_supported = 1;
68#endif
69
Atsushi Nemoto4516a612007-02-05 16:36:06 -080070#define DEFAULT_CARDBUS_IO_SIZE (256)
71#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
72/* pci=cbmemsize=nnM,cbiosize=nn can override this */
73unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
74unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
75
Eric W. Biederman28760482009-09-09 14:09:24 -070076#define DEFAULT_HOTPLUG_IO_SIZE (256)
77#define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
78/* pci=hpmemsize=nnM,hpiosize=nn can override this */
79unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
80unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
81
Jon Mason5f39e672011-10-03 09:50:20 -050082enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
Jon Masonb03e7492011-07-20 15:20:54 -050083
Jesse Barnesac1aa472009-10-26 13:20:44 -070084/*
85 * The default CLS is used if arch didn't set CLS explicitly and not
86 * all pci devices agree on the same value. Arch can override either
87 * the dfl or actual value as it sees fit. Don't forget this is
88 * measured in 32-bit words, not bytes.
89 */
Bill Pemberton15856ad2012-11-21 15:35:00 -050090u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
Jesse Barnesac1aa472009-10-26 13:20:44 -070091u8 pci_cache_line_size;
92
Myron Stowe96c55902011-10-28 15:48:38 -060093/*
94 * If we set up a device for bus mastering, we need to check the latency
95 * timer as certain BIOSes forget to set it properly.
96 */
97unsigned int pcibios_max_latency = 255;
98
Rafael J. Wysocki6748dcc2012-03-01 00:06:33 +010099/* If set, the PCIe ARI capability will not be used. */
100static bool pcie_ari_disabled;
101
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102/**
103 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
104 * @bus: pointer to PCI bus structure to search
105 *
106 * Given a PCI bus, returns the highest PCI bus number present in the set
107 * including the given PCI bus and its list of child PCI buses.
108 */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800109unsigned char pci_bus_max_busnr(struct pci_bus* bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110{
111 struct list_head *tmp;
112 unsigned char max, n;
113
Yinghai Lub918c622012-05-17 18:51:11 -0700114 max = bus->busn_res.end;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700115 list_for_each(tmp, &bus->children) {
116 n = pci_bus_max_busnr(pci_bus_b(tmp));
117 if(n > max)
118 max = n;
119 }
120 return max;
121}
Kristen Accardib82db5c2006-01-17 16:56:56 -0800122EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123
Andrew Morton1684f5d2008-12-01 14:30:30 -0800124#ifdef CONFIG_HAS_IOMEM
125void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
126{
127 /*
128 * Make sure the BAR is actually a memory resource, not an IO resource
129 */
130 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
131 WARN_ON(1);
132 return NULL;
133 }
134 return ioremap_nocache(pci_resource_start(pdev, bar),
135 pci_resource_len(pdev, bar));
136}
137EXPORT_SYMBOL_GPL(pci_ioremap_bar);
138#endif
139
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100140#define PCI_FIND_CAP_TTL 48
141
142static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
143 u8 pos, int cap, int *ttl)
Roland Dreier24a4e372005-10-28 17:35:34 -0700144{
145 u8 id;
Roland Dreier24a4e372005-10-28 17:35:34 -0700146
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100147 while ((*ttl)--) {
Roland Dreier24a4e372005-10-28 17:35:34 -0700148 pci_bus_read_config_byte(bus, devfn, pos, &pos);
149 if (pos < 0x40)
150 break;
151 pos &= ~3;
152 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
153 &id);
154 if (id == 0xff)
155 break;
156 if (id == cap)
157 return pos;
158 pos += PCI_CAP_LIST_NEXT;
159 }
160 return 0;
161}
162
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100163static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
164 u8 pos, int cap)
165{
166 int ttl = PCI_FIND_CAP_TTL;
167
168 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
169}
170
Roland Dreier24a4e372005-10-28 17:35:34 -0700171int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
172{
173 return __pci_find_next_cap(dev->bus, dev->devfn,
174 pos + PCI_CAP_LIST_NEXT, cap);
175}
176EXPORT_SYMBOL_GPL(pci_find_next_capability);
177
Michael Ellermand3bac112006-11-22 18:26:16 +1100178static int __pci_bus_find_cap_start(struct pci_bus *bus,
179 unsigned int devfn, u8 hdr_type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180{
181 u16 status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700182
183 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
184 if (!(status & PCI_STATUS_CAP_LIST))
185 return 0;
186
187 switch (hdr_type) {
188 case PCI_HEADER_TYPE_NORMAL:
189 case PCI_HEADER_TYPE_BRIDGE:
Michael Ellermand3bac112006-11-22 18:26:16 +1100190 return PCI_CAPABILITY_LIST;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191 case PCI_HEADER_TYPE_CARDBUS:
Michael Ellermand3bac112006-11-22 18:26:16 +1100192 return PCI_CB_CAPABILITY_LIST;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700193 default:
194 return 0;
195 }
Michael Ellermand3bac112006-11-22 18:26:16 +1100196
197 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700198}
199
200/**
201 * pci_find_capability - query for devices' capabilities
202 * @dev: PCI device to query
203 * @cap: capability code
204 *
205 * Tell if a device supports a given PCI capability.
206 * Returns the address of the requested capability structure within the
207 * device's PCI configuration space or 0 in case the device does not
208 * support it. Possible values for @cap:
209 *
210 * %PCI_CAP_ID_PM Power Management
211 * %PCI_CAP_ID_AGP Accelerated Graphics Port
212 * %PCI_CAP_ID_VPD Vital Product Data
213 * %PCI_CAP_ID_SLOTID Slot Identification
214 * %PCI_CAP_ID_MSI Message Signalled Interrupts
215 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
216 * %PCI_CAP_ID_PCIX PCI-X
217 * %PCI_CAP_ID_EXP PCI Express
218 */
219int pci_find_capability(struct pci_dev *dev, int cap)
220{
Michael Ellermand3bac112006-11-22 18:26:16 +1100221 int pos;
222
223 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
224 if (pos)
225 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
226
227 return pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700228}
229
230/**
231 * pci_bus_find_capability - query for devices' capabilities
232 * @bus: the PCI bus to query
233 * @devfn: PCI device to query
234 * @cap: capability code
235 *
236 * Like pci_find_capability() but works for pci devices that do not have a
237 * pci_dev structure set up yet.
238 *
239 * Returns the address of the requested capability structure within the
240 * device's PCI configuration space or 0 in case the device does not
241 * support it.
242 */
243int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
244{
Michael Ellermand3bac112006-11-22 18:26:16 +1100245 int pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700246 u8 hdr_type;
247
248 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
249
Michael Ellermand3bac112006-11-22 18:26:16 +1100250 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
251 if (pos)
252 pos = __pci_find_next_cap(bus, devfn, pos, cap);
253
254 return pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700255}
256
257/**
Bjorn Helgaas44a9a362012-07-13 14:24:59 -0600258 * pci_find_next_ext_capability - Find an extended capability
259 * @dev: PCI device to query
260 * @start: address at which to start looking (0 to start at beginning of list)
261 * @cap: capability code
262 *
263 * Returns the address of the next matching extended capability structure
264 * within the device's PCI configuration space or 0 if the device does
265 * not support it. Some capabilities can occur several times, e.g., the
266 * vendor-specific capability, and this provides a way to find them all.
267 */
268int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
269{
270 u32 header;
271 int ttl;
272 int pos = PCI_CFG_SPACE_SIZE;
273
274 /* minimum 8 bytes per capability */
275 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
276
277 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
278 return 0;
279
280 if (start)
281 pos = start;
282
283 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
284 return 0;
285
286 /*
287 * If we have no capabilities, this is indicated by cap ID,
288 * cap version and next pointer all being 0.
289 */
290 if (header == 0)
291 return 0;
292
293 while (ttl-- > 0) {
294 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
295 return pos;
296
297 pos = PCI_EXT_CAP_NEXT(header);
298 if (pos < PCI_CFG_SPACE_SIZE)
299 break;
300
301 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
302 break;
303 }
304
305 return 0;
306}
307EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
308
309/**
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310 * pci_find_ext_capability - Find an extended capability
311 * @dev: PCI device to query
312 * @cap: capability code
313 *
314 * Returns the address of the requested extended capability structure
315 * within the device's PCI configuration space or 0 if the device does
316 * not support it. Possible values for @cap:
317 *
318 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
319 * %PCI_EXT_CAP_ID_VC Virtual Channel
320 * %PCI_EXT_CAP_ID_DSN Device Serial Number
321 * %PCI_EXT_CAP_ID_PWR Power Budgeting
322 */
323int pci_find_ext_capability(struct pci_dev *dev, int cap)
324{
Bjorn Helgaas44a9a362012-07-13 14:24:59 -0600325 return pci_find_next_ext_capability(dev, 0, cap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700326}
Brice Goglin3a720d72006-05-23 06:10:01 -0400327EXPORT_SYMBOL_GPL(pci_find_ext_capability);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700328
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100329static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
330{
331 int rc, ttl = PCI_FIND_CAP_TTL;
332 u8 cap, mask;
333
334 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
335 mask = HT_3BIT_CAP_MASK;
336 else
337 mask = HT_5BIT_CAP_MASK;
338
339 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
340 PCI_CAP_ID_HT, &ttl);
341 while (pos) {
342 rc = pci_read_config_byte(dev, pos + 3, &cap);
343 if (rc != PCIBIOS_SUCCESSFUL)
344 return 0;
345
346 if ((cap & mask) == ht_cap)
347 return pos;
348
Brice Goglin47a4d5b2007-01-10 23:15:29 -0800349 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
350 pos + PCI_CAP_LIST_NEXT,
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100351 PCI_CAP_ID_HT, &ttl);
352 }
353
354 return 0;
355}
356/**
357 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
358 * @dev: PCI device to query
359 * @pos: Position from which to continue searching
360 * @ht_cap: Hypertransport capability code
361 *
362 * To be used in conjunction with pci_find_ht_capability() to search for
363 * all capabilities matching @ht_cap. @pos should always be a value returned
364 * from pci_find_ht_capability().
365 *
366 * NB. To be 100% safe against broken PCI devices, the caller should take
367 * steps to avoid an infinite loop.
368 */
369int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
370{
371 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
372}
373EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
374
375/**
376 * pci_find_ht_capability - query a device's Hypertransport capabilities
377 * @dev: PCI device to query
378 * @ht_cap: Hypertransport capability code
379 *
380 * Tell if a device supports a given Hypertransport capability.
381 * Returns an address within the device's PCI configuration space
382 * or 0 in case the device does not support the request capability.
383 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
384 * which has a Hypertransport capability matching @ht_cap.
385 */
386int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
387{
388 int pos;
389
390 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
391 if (pos)
392 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
393
394 return pos;
395}
396EXPORT_SYMBOL_GPL(pci_find_ht_capability);
397
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398/**
399 * pci_find_parent_resource - return resource region of parent bus of given region
400 * @dev: PCI device structure contains resources to be searched
401 * @res: child resource record for which parent is sought
402 *
403 * For given resource region of given device, return the resource
404 * region of parent bus the given region is contained in or where
405 * it should be allocated from.
406 */
407struct resource *
408pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
409{
410 const struct pci_bus *bus = dev->bus;
411 int i;
Bjorn Helgaas89a74ec2010-02-23 10:24:31 -0700412 struct resource *best = NULL, *r;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413
Bjorn Helgaas89a74ec2010-02-23 10:24:31 -0700414 pci_bus_for_each_resource(bus, r, i) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700415 if (!r)
416 continue;
417 if (res->start && !(res->start >= r->start && res->end <= r->end))
418 continue; /* Not contained */
419 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
420 continue; /* Wrong type */
421 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
422 return r; /* Exact match */
Linus Torvalds8c8def22009-11-09 12:04:32 -0800423 /* We can't insert a non-prefetch resource inside a prefetchable parent .. */
424 if (r->flags & IORESOURCE_PREFETCH)
425 continue;
426 /* .. but we can put a prefetchable resource inside a non-prefetchable one */
427 if (!best)
428 best = r;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700429 }
430 return best;
431}
432
433/**
John W. Linville064b53db2005-07-27 10:19:44 -0400434 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
435 * @dev: PCI device to have its BARs restored
436 *
437 * Restore the BAR values for a given device, so as to make it
438 * accessible by its driver.
439 */
Adrian Bunkad6685992007-10-27 03:06:22 +0200440static void
John W. Linville064b53db2005-07-27 10:19:44 -0400441pci_restore_bars(struct pci_dev *dev)
442{
Yu Zhaobc5f5a82008-11-22 02:40:00 +0800443 int i;
John W. Linville064b53db2005-07-27 10:19:44 -0400444
Yu Zhaobc5f5a82008-11-22 02:40:00 +0800445 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
Yu Zhao14add802008-11-22 02:38:52 +0800446 pci_update_resource(dev, i);
John W. Linville064b53db2005-07-27 10:19:44 -0400447}
448
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200449static struct pci_platform_pm_ops *pci_platform_pm;
450
451int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
452{
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +0200453 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
Rafael J. Wysockid2e5f0c2012-12-23 00:02:44 +0100454 || !ops->sleep_wake)
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200455 return -EINVAL;
456 pci_platform_pm = ops;
457 return 0;
458}
459
460static inline bool platform_pci_power_manageable(struct pci_dev *dev)
461{
462 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
463}
464
465static inline int platform_pci_set_power_state(struct pci_dev *dev,
466 pci_power_t t)
467{
468 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
469}
470
471static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
472{
473 return pci_platform_pm ?
474 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
475}
Randy Dunlap8f7020d2005-10-23 11:57:38 -0700476
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +0200477static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
478{
479 return pci_platform_pm ?
480 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
481}
482
Rafael J. Wysockib67ea762010-02-17 23:44:09 +0100483static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
484{
485 return pci_platform_pm ?
486 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
487}
488
John W. Linville064b53db2005-07-27 10:19:44 -0400489/**
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200490 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
491 * given PCI device
492 * @dev: PCI device to handle.
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200493 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700494 *
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200495 * RETURN VALUE:
496 * -EINVAL if the requested state is invalid.
497 * -EIO if device does not support PCI PM or its PM capabilities register has a
498 * wrong version, or device doesn't support the requested state.
499 * 0 if device already is in the requested state.
500 * 0 if device's power state has been successfully changed.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700501 */
Rafael J. Wysockif00a20e2009-03-16 22:40:08 +0100502static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700503{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200504 u16 pmcsr;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200505 bool need_restore = false;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700506
Rafael J. Wysocki4a865902009-03-16 22:40:36 +0100507 /* Check if we're already there */
508 if (dev->current_state == state)
509 return 0;
510
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200511 if (!dev->pm_cap)
Andrew Lunncca03de2007-07-09 11:55:58 -0700512 return -EIO;
513
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200514 if (state < PCI_D0 || state > PCI_D3hot)
515 return -EINVAL;
516
Linus Torvalds1da177e2005-04-16 15:20:36 -0700517 /* Validate current state:
518 * Can enter D0 from any state, but if we can only go deeper
519 * to sleep if we're already in a low power state
520 */
Rafael J. Wysocki4a865902009-03-16 22:40:36 +0100521 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200522 && dev->current_state > state) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600523 dev_err(&dev->dev, "invalid power transition "
524 "(from state %d to %d)\n", dev->current_state, state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700525 return -EINVAL;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200526 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700527
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528 /* check if this device supports the desired state */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200529 if ((state == PCI_D1 && !dev->d1_support)
530 || (state == PCI_D2 && !dev->d2_support))
Daniel Ritz3fe9d192005-08-17 15:32:19 -0700531 return -EIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700532
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200533 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
John W. Linville064b53db2005-07-27 10:19:44 -0400534
John W. Linville32a36582005-09-14 09:52:42 -0400535 /* If we're (effectively) in D3, force entire word to 0.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700536 * This doesn't affect PME_Status, disables PME_En, and
537 * sets PowerState to 0.
538 */
John W. Linville32a36582005-09-14 09:52:42 -0400539 switch (dev->current_state) {
John W. Linvilled3535fb2005-09-28 17:50:51 -0400540 case PCI_D0:
541 case PCI_D1:
542 case PCI_D2:
543 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
544 pmcsr |= state;
545 break;
Rafael J. Wysockif62795f2009-05-18 22:51:12 +0200546 case PCI_D3hot:
547 case PCI_D3cold:
John W. Linville32a36582005-09-14 09:52:42 -0400548 case PCI_UNKNOWN: /* Boot-up */
549 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
Rafael J. Wysockif00a20e2009-03-16 22:40:08 +0100550 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200551 need_restore = true;
John W. Linville32a36582005-09-14 09:52:42 -0400552 /* Fall-through: force to D0 */
John W. Linville32a36582005-09-14 09:52:42 -0400553 default:
John W. Linvilled3535fb2005-09-28 17:50:51 -0400554 pmcsr = 0;
John W. Linville32a36582005-09-14 09:52:42 -0400555 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700556 }
557
558 /* enter specified state */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200559 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700560
561 /* Mandatory power management transition delays */
562 /* see PCI PM 1.1 5.6.1 table 18 */
563 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
Rafael J. Wysocki1ae861e2009-12-31 12:15:54 +0100564 pci_dev_d3_sleep(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565 else if (state == PCI_D2 || dev->current_state == PCI_D2)
Rafael J. Wysockiaa8c6c92009-01-16 21:54:43 +0100566 udelay(PCI_PM_D2_DELAY);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700567
Rafael J. Wysockie13cdbd2009-10-05 00:48:40 +0200568 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
569 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
570 if (dev->current_state != state && printk_ratelimit())
571 dev_info(&dev->dev, "Refused to change power state, "
572 "currently in D%d\n", dev->current_state);
John W. Linville064b53db2005-07-27 10:19:44 -0400573
Huang Ying448bd852012-06-23 10:23:51 +0800574 /*
575 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
John W. Linville064b53db2005-07-27 10:19:44 -0400576 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
577 * from D3hot to D0 _may_ perform an internal reset, thereby
578 * going to "D0 Uninitialized" rather than "D0 Initialized".
579 * For example, at least some versions of the 3c905B and the
580 * 3c556B exhibit this behaviour.
581 *
582 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
583 * devices in a D3hot state at boot. Consequently, we need to
584 * restore at least the BARs so that the device will be
585 * accessible to its driver.
586 */
587 if (need_restore)
588 pci_restore_bars(dev);
589
Rafael J. Wysockif00a20e2009-03-16 22:40:08 +0100590 if (dev->bus->self)
Shaohua Li7d715a62008-02-25 09:46:41 +0800591 pcie_aspm_pm_state_change(dev->bus->self);
592
Linus Torvalds1da177e2005-04-16 15:20:36 -0700593 return 0;
594}
595
596/**
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200597 * pci_update_current_state - Read PCI power state of given device from its
598 * PCI PM registers and cache it
599 * @dev: PCI device to handle.
Rafael J. Wysockif06fc0b2008-12-27 16:30:52 +0100600 * @state: State to cache in case the device doesn't have the PM capability
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200601 */
Rafael J. Wysocki734104292009-01-07 13:07:15 +0100602void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200603{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200604 if (dev->pm_cap) {
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200605 u16 pmcsr;
606
Huang Ying448bd852012-06-23 10:23:51 +0800607 /*
608 * Configuration space is not accessible for device in
609 * D3cold, so just keep or set D3cold for safety
610 */
611 if (dev->current_state == PCI_D3cold)
612 return;
613 if (state == PCI_D3cold) {
614 dev->current_state = PCI_D3cold;
615 return;
616 }
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200617 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200618 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
Rafael J. Wysockif06fc0b2008-12-27 16:30:52 +0100619 } else {
620 dev->current_state = state;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200621 }
622}
623
624/**
Rafael J. Wysockidb288c92012-07-05 15:20:00 -0600625 * pci_power_up - Put the given device into D0 forcibly
626 * @dev: PCI device to power up
627 */
628void pci_power_up(struct pci_dev *dev)
629{
630 if (platform_pci_power_manageable(dev))
631 platform_pci_set_power_state(dev, PCI_D0);
632
633 pci_raw_set_power_state(dev, PCI_D0);
634 pci_update_current_state(dev, PCI_D0);
635}
636
637/**
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100638 * pci_platform_power_transition - Use platform to change device power state
639 * @dev: PCI device to handle.
640 * @state: State to put the device into.
641 */
642static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
643{
644 int error;
645
646 if (platform_pci_power_manageable(dev)) {
647 error = platform_pci_set_power_state(dev, state);
648 if (!error)
649 pci_update_current_state(dev, state);
Rafael J. Wysocki769ba722013-04-12 13:58:17 +0000650 } else
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100651 error = -ENODEV;
Rafael J. Wysocki769ba722013-04-12 13:58:17 +0000652
653 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
654 dev->current_state = PCI_D0;
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100655
656 return error;
657}
658
659/**
660 * __pci_start_power_transition - Start power transition of a PCI device
661 * @dev: PCI device to handle.
662 * @state: State to put the device into.
663 */
664static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
665{
Huang Ying448bd852012-06-23 10:23:51 +0800666 if (state == PCI_D0) {
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100667 pci_platform_power_transition(dev, PCI_D0);
Huang Ying448bd852012-06-23 10:23:51 +0800668 /*
669 * Mandatory power management transition delays, see
670 * PCI Express Base Specification Revision 2.0 Section
671 * 6.6.1: Conventional Reset. Do not delay for
672 * devices powered on/off by corresponding bridge,
673 * because have already delayed for the bridge.
674 */
675 if (dev->runtime_d3cold) {
676 msleep(dev->d3cold_delay);
677 /*
678 * When powering on a bridge from D3cold, the
679 * whole hierarchy may be powered on into
680 * D0uninitialized state, resume them to give
681 * them a chance to suspend again
682 */
683 pci_wakeup_bus(dev->subordinate);
684 }
685 }
686}
687
688/**
689 * __pci_dev_set_current_state - Set current state of a PCI device
690 * @dev: Device to handle
691 * @data: pointer to state to be set
692 */
693static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
694{
695 pci_power_t state = *(pci_power_t *)data;
696
697 dev->current_state = state;
698 return 0;
699}
700
701/**
702 * __pci_bus_set_current_state - Walk given bus and set current state of devices
703 * @bus: Top bus of the subtree to walk.
704 * @state: state to be set
705 */
706static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
707{
708 if (bus)
709 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100710}
711
712/**
713 * __pci_complete_power_transition - Complete power transition of a PCI device
714 * @dev: PCI device to handle.
715 * @state: State to put the device into.
716 *
717 * This function should not be called directly by device drivers.
718 */
719int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
720{
Huang Ying448bd852012-06-23 10:23:51 +0800721 int ret;
722
Rafael J. Wysockidb288c92012-07-05 15:20:00 -0600723 if (state <= PCI_D0)
Huang Ying448bd852012-06-23 10:23:51 +0800724 return -EINVAL;
725 ret = pci_platform_power_transition(dev, state);
726 /* Power off the bridge may power off the whole hierarchy */
727 if (!ret && state == PCI_D3cold)
728 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
729 return ret;
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100730}
731EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
732
733/**
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200734 * pci_set_power_state - Set the power state of a PCI device
735 * @dev: PCI device to handle.
736 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
737 *
Nick Andrew877d0312009-01-26 11:06:57 +0100738 * Transition a device to a new power state, using the platform firmware and/or
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200739 * the device's PCI PM registers.
740 *
741 * RETURN VALUE:
742 * -EINVAL if the requested state is invalid.
743 * -EIO if device does not support PCI PM or its PM capabilities register has a
744 * wrong version, or device doesn't support the requested state.
745 * 0 if device already is in the requested state.
746 * 0 if device's power state has been successfully changed.
747 */
748int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
749{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200750 int error;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200751
752 /* bound the state we're entering */
Huang Ying448bd852012-06-23 10:23:51 +0800753 if (state > PCI_D3cold)
754 state = PCI_D3cold;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200755 else if (state < PCI_D0)
756 state = PCI_D0;
757 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
758 /*
759 * If the device or the parent bridge do not support PCI PM,
760 * ignore the request if we're doing anything other than putting
761 * it into D0 (which would only happen on boot).
762 */
763 return 0;
764
Rafael J. Wysockidb288c92012-07-05 15:20:00 -0600765 /* Check if we're already there */
766 if (dev->current_state == state)
767 return 0;
768
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100769 __pci_start_power_transition(dev, state);
770
Alan Cox979b1792008-07-24 17:18:38 +0100771 /* This device is quirked not to be put into D3, so
772 don't put it in D3 */
Huang Ying448bd852012-06-23 10:23:51 +0800773 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
Alan Cox979b1792008-07-24 17:18:38 +0100774 return 0;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200775
Huang Ying448bd852012-06-23 10:23:51 +0800776 /*
777 * To put device in D3cold, we put device into D3hot in native
778 * way, then put device into D3cold with platform ops
779 */
780 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
781 PCI_D3hot : state);
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200782
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100783 if (!__pci_complete_power_transition(dev, state))
784 error = 0;
Naga Chumbalkar1a680b72011-03-21 03:29:08 +0000785 /*
786 * When aspm_policy is "powersave" this call ensures
787 * that ASPM is configured.
788 */
789 if (!error && dev->bus->self)
790 pcie_aspm_powersave_config_link(dev->bus->self);
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200791
792 return error;
793}
794
795/**
Linus Torvalds1da177e2005-04-16 15:20:36 -0700796 * pci_choose_state - Choose the power state of a PCI device
797 * @dev: PCI device to be suspended
798 * @state: target sleep state for the whole system. This is the value
799 * that is passed to suspend() function.
800 *
801 * Returns PCI power state suitable for given device and given system
802 * message.
803 */
804
805pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
806{
Shaohua Liab826ca2007-07-20 10:03:22 +0800807 pci_power_t ret;
David Shaohua Li0f644742005-03-19 00:15:48 -0500808
Yijing Wang728cdb72013-06-18 16:22:14 +0800809 if (!dev->pm_cap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700810 return PCI_D0;
811
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200812 ret = platform_pci_choose_state(dev);
813 if (ret != PCI_POWER_ERROR)
814 return ret;
Pavel Machekca078ba2005-09-03 15:56:57 -0700815
816 switch (state.event) {
817 case PM_EVENT_ON:
818 return PCI_D0;
819 case PM_EVENT_FREEZE:
David Brownellb887d2e2006-08-14 23:11:05 -0700820 case PM_EVENT_PRETHAW:
821 /* REVISIT both freeze and pre-thaw "should" use D0 */
Pavel Machekca078ba2005-09-03 15:56:57 -0700822 case PM_EVENT_SUSPEND:
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +0100823 case PM_EVENT_HIBERNATE:
Pavel Machekca078ba2005-09-03 15:56:57 -0700824 return PCI_D3hot;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700825 default:
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600826 dev_info(&dev->dev, "unrecognized suspend event %d\n",
827 state.event);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700828 BUG();
829 }
830 return PCI_D0;
831}
832
833EXPORT_SYMBOL(pci_choose_state);
834
Yu Zhao89858512009-02-16 02:55:47 +0800835#define PCI_EXP_SAVE_REGS 7
836
Yu Zhao1b6b8ce2009-04-09 14:57:39 +0800837
Yinghai Lu34a48762012-02-11 00:18:41 -0800838static struct pci_cap_saved_state *pci_find_saved_cap(
839 struct pci_dev *pci_dev, char cap)
840{
841 struct pci_cap_saved_state *tmp;
Yinghai Lu34a48762012-02-11 00:18:41 -0800842
Sasha Levinb67bfe02013-02-27 17:06:00 -0800843 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
Yinghai Lu34a48762012-02-11 00:18:41 -0800844 if (tmp->cap.cap_nr == cap)
845 return tmp;
846 }
847 return NULL;
848}
849
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300850static int pci_save_pcie_state(struct pci_dev *dev)
851{
Jiang Liu59875ae2012-07-24 17:20:06 +0800852 int i = 0;
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300853 struct pci_cap_saved_state *save_state;
854 u16 *cap;
855
Jiang Liu59875ae2012-07-24 17:20:06 +0800856 if (!pci_is_pcie(dev))
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300857 return 0;
858
Eric W. Biederman9f355752007-03-08 13:06:13 -0700859 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300860 if (!save_state) {
Harvey Harrisone496b612009-01-07 16:22:37 -0800861 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300862 return -ENOMEM;
863 }
Jiang Liu59875ae2012-07-24 17:20:06 +0800864
Alex Williamson24a4742f2011-05-10 10:02:11 -0600865 cap = (u16 *)&save_state->cap.data[0];
Jiang Liu59875ae2012-07-24 17:20:06 +0800866 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
867 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
868 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
869 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
870 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
871 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
872 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300873
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300874 return 0;
875}
876
877static void pci_restore_pcie_state(struct pci_dev *dev)
878{
Jiang Liu59875ae2012-07-24 17:20:06 +0800879 int i = 0;
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300880 struct pci_cap_saved_state *save_state;
881 u16 *cap;
882
883 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
Jiang Liu59875ae2012-07-24 17:20:06 +0800884 if (!save_state)
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300885 return;
Jiang Liu59875ae2012-07-24 17:20:06 +0800886
Alex Williamson24a4742f2011-05-10 10:02:11 -0600887 cap = (u16 *)&save_state->cap.data[0];
Jiang Liu59875ae2012-07-24 17:20:06 +0800888 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
889 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
890 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
891 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
892 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
893 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
894 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300895}
896
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800897
898static int pci_save_pcix_state(struct pci_dev *dev)
899{
Rafael J. Wysocki63f48982008-12-07 22:02:58 +0100900 int pos;
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800901 struct pci_cap_saved_state *save_state;
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800902
903 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
904 if (pos <= 0)
905 return 0;
906
Shaohua Lif34303d2007-12-18 09:56:47 +0800907 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800908 if (!save_state) {
Harvey Harrisone496b612009-01-07 16:22:37 -0800909 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800910 return -ENOMEM;
911 }
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800912
Alex Williamson24a4742f2011-05-10 10:02:11 -0600913 pci_read_config_word(dev, pos + PCI_X_CMD,
914 (u16 *)save_state->cap.data);
Rafael J. Wysocki63f48982008-12-07 22:02:58 +0100915
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800916 return 0;
917}
918
919static void pci_restore_pcix_state(struct pci_dev *dev)
920{
921 int i = 0, pos;
922 struct pci_cap_saved_state *save_state;
923 u16 *cap;
924
925 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
926 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
927 if (!save_state || pos <= 0)
928 return;
Alex Williamson24a4742f2011-05-10 10:02:11 -0600929 cap = (u16 *)&save_state->cap.data[0];
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800930
931 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800932}
933
934
Linus Torvalds1da177e2005-04-16 15:20:36 -0700935/**
936 * pci_save_state - save the PCI configuration space of a device before suspending
937 * @dev: - PCI device that we're dealing with
Linus Torvalds1da177e2005-04-16 15:20:36 -0700938 */
939int
940pci_save_state(struct pci_dev *dev)
941{
942 int i;
943 /* XXX: 100% dword access ok here? */
944 for (i = 0; i < 16; i++)
Kleber Sacilotto de Souza9e0b5b22009-11-25 00:55:51 -0200945 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
Rafael J. Wysockiaa8c6c92009-01-16 21:54:43 +0100946 dev->state_saved = true;
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +0300947 if ((i = pci_save_pcie_state(dev)) != 0)
948 return i;
Stephen Hemmingercc692a52006-11-08 16:17:15 -0800949 if ((i = pci_save_pcix_state(dev)) != 0)
950 return i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700951 return 0;
952}
953
Rafael J. Wysockiebfc5b82012-04-15 21:40:40 +0200954static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
955 u32 saved_val, int retry)
956{
957 u32 val;
958
959 pci_read_config_dword(pdev, offset, &val);
960 if (val == saved_val)
961 return;
962
963 for (;;) {
964 dev_dbg(&pdev->dev, "restoring config space at offset "
965 "%#x (was %#x, writing %#x)\n", offset, val, saved_val);
966 pci_write_config_dword(pdev, offset, saved_val);
967 if (retry-- <= 0)
968 return;
969
970 pci_read_config_dword(pdev, offset, &val);
971 if (val == saved_val)
972 return;
973
974 mdelay(1);
975 }
976}
977
Rafael J. Wysockia6cb9ee2012-04-16 23:07:50 +0200978static void pci_restore_config_space_range(struct pci_dev *pdev,
979 int start, int end, int retry)
Rafael J. Wysockiebfc5b82012-04-15 21:40:40 +0200980{
981 int index;
982
983 for (index = end; index >= start; index--)
984 pci_restore_config_dword(pdev, 4 * index,
985 pdev->saved_config_space[index],
986 retry);
987}
988
Rafael J. Wysockia6cb9ee2012-04-16 23:07:50 +0200989static void pci_restore_config_space(struct pci_dev *pdev)
990{
991 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
992 pci_restore_config_space_range(pdev, 10, 15, 0);
993 /* Restore BARs before the command register. */
994 pci_restore_config_space_range(pdev, 4, 9, 10);
995 pci_restore_config_space_range(pdev, 0, 3, 0);
996 } else {
997 pci_restore_config_space_range(pdev, 0, 15, 0);
998 }
999}
1000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001001/**
1002 * pci_restore_state - Restore the saved state of a PCI device
1003 * @dev: - PCI device that we're dealing with
Linus Torvalds1da177e2005-04-16 15:20:36 -07001004 */
Jon Mason1d3c16a2010-11-30 17:43:26 -06001005void pci_restore_state(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001006{
Alek Duc82f63e2009-08-08 08:46:19 +08001007 if (!dev->state_saved)
Jon Mason1d3c16a2010-11-30 17:43:26 -06001008 return;
Rafael J. Wysocki4b77b0a2009-09-09 23:49:59 +02001009
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +03001010 /* PCI Express register must be restored first */
1011 pci_restore_pcie_state(dev);
Hao, Xudong1900ca12011-12-17 21:24:40 +08001012 pci_restore_ats_state(dev);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +03001013
Rafael J. Wysockia6cb9ee2012-04-16 23:07:50 +02001014 pci_restore_config_space(dev);
Rafael J. Wysockiebfc5b82012-04-15 21:40:40 +02001015
Stephen Hemmingercc692a52006-11-08 16:17:15 -08001016 pci_restore_pcix_state(dev);
Shaohua Li41017f02006-02-08 17:11:38 +08001017 pci_restore_msi_state(dev);
Yu Zhao8c5cdb62009-03-20 11:25:12 +08001018 pci_restore_iov_state(dev);
Michael Ellerman8fed4b62007-01-25 19:34:08 +11001019
Rafael J. Wysocki4b77b0a2009-09-09 23:49:59 +02001020 dev->state_saved = false;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001021}
1022
Alex Williamsonffbdd3f2011-05-10 10:02:27 -06001023struct pci_saved_state {
1024 u32 config_space[16];
1025 struct pci_cap_saved_data cap[0];
1026};
1027
1028/**
1029 * pci_store_saved_state - Allocate and return an opaque struct containing
1030 * the device saved state.
1031 * @dev: PCI device that we're dealing with
1032 *
1033 * Rerturn NULL if no state or error.
1034 */
1035struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1036{
1037 struct pci_saved_state *state;
1038 struct pci_cap_saved_state *tmp;
1039 struct pci_cap_saved_data *cap;
Alex Williamsonffbdd3f2011-05-10 10:02:27 -06001040 size_t size;
1041
1042 if (!dev->state_saved)
1043 return NULL;
1044
1045 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1046
Sasha Levinb67bfe02013-02-27 17:06:00 -08001047 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
Alex Williamsonffbdd3f2011-05-10 10:02:27 -06001048 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1049
1050 state = kzalloc(size, GFP_KERNEL);
1051 if (!state)
1052 return NULL;
1053
1054 memcpy(state->config_space, dev->saved_config_space,
1055 sizeof(state->config_space));
1056
1057 cap = state->cap;
Sasha Levinb67bfe02013-02-27 17:06:00 -08001058 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
Alex Williamsonffbdd3f2011-05-10 10:02:27 -06001059 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1060 memcpy(cap, &tmp->cap, len);
1061 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1062 }
1063 /* Empty cap_save terminates list */
1064
1065 return state;
1066}
1067EXPORT_SYMBOL_GPL(pci_store_saved_state);
1068
1069/**
1070 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1071 * @dev: PCI device that we're dealing with
1072 * @state: Saved state returned from pci_store_saved_state()
1073 */
1074int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
1075{
1076 struct pci_cap_saved_data *cap;
1077
1078 dev->state_saved = false;
1079
1080 if (!state)
1081 return 0;
1082
1083 memcpy(dev->saved_config_space, state->config_space,
1084 sizeof(state->config_space));
1085
1086 cap = state->cap;
1087 while (cap->size) {
1088 struct pci_cap_saved_state *tmp;
1089
1090 tmp = pci_find_saved_cap(dev, cap->cap_nr);
1091 if (!tmp || tmp->cap.size != cap->size)
1092 return -EINVAL;
1093
1094 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1095 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1096 sizeof(struct pci_cap_saved_data) + cap->size);
1097 }
1098
1099 dev->state_saved = true;
1100 return 0;
1101}
1102EXPORT_SYMBOL_GPL(pci_load_saved_state);
1103
1104/**
1105 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1106 * and free the memory allocated for it.
1107 * @dev: PCI device that we're dealing with
1108 * @state: Pointer to saved state returned from pci_store_saved_state()
1109 */
1110int pci_load_and_free_saved_state(struct pci_dev *dev,
1111 struct pci_saved_state **state)
1112{
1113 int ret = pci_load_saved_state(dev, *state);
1114 kfree(*state);
1115 *state = NULL;
1116 return ret;
1117}
1118EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1119
Hidetoshi Seto38cc1302006-12-18 10:30:00 +09001120static int do_pci_enable_device(struct pci_dev *dev, int bars)
1121{
1122 int err;
1123
1124 err = pci_set_power_state(dev, PCI_D0);
1125 if (err < 0 && err != -EIO)
1126 return err;
1127 err = pcibios_enable_device(dev, bars);
1128 if (err < 0)
1129 return err;
1130 pci_fixup_device(pci_fixup_enable, dev);
1131
1132 return 0;
1133}
1134
1135/**
Tejun Heo0b62e132007-07-27 14:43:35 +09001136 * pci_reenable_device - Resume abandoned device
Hidetoshi Seto38cc1302006-12-18 10:30:00 +09001137 * @dev: PCI device to be resumed
1138 *
1139 * Note this function is a backend of pci_default_resume and is not supposed
1140 * to be called by normal code, write proper resume handler and use it instead.
1141 */
Tejun Heo0b62e132007-07-27 14:43:35 +09001142int pci_reenable_device(struct pci_dev *dev)
Hidetoshi Seto38cc1302006-12-18 10:30:00 +09001143{
Yuji Shimada296ccb02009-04-03 16:41:46 +09001144 if (pci_is_enabled(dev))
Hidetoshi Seto38cc1302006-12-18 10:30:00 +09001145 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1146 return 0;
1147}
1148
Yinghai Lu928bea92013-07-22 14:37:17 -07001149static void pci_enable_bridge(struct pci_dev *dev)
1150{
1151 int retval;
1152
1153 if (!dev)
1154 return;
1155
1156 pci_enable_bridge(dev->bus->self);
1157
1158 if (pci_is_enabled(dev))
1159 return;
1160 retval = pci_enable_device(dev);
1161 if (retval)
1162 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1163 retval);
1164 pci_set_master(dev);
1165}
1166
Bjorn Helgaasb4b4fbb2013-01-04 12:12:55 -07001167static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001168{
1169 int err;
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +11001170 int i, bars = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001171
Jesse Barnes97c145f2010-11-05 15:16:36 -04001172 /*
1173 * Power state could be unknown at this point, either due to a fresh
1174 * boot or a device removal call. So get the current power state
1175 * so that things like MSI message writing will behave as expected
1176 * (e.g. if the device really is in D0 at enable time).
1177 */
1178 if (dev->pm_cap) {
1179 u16 pmcsr;
1180 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1181 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1182 }
1183
Bjorn Helgaascc7ba392013-02-11 16:47:01 -07001184 if (atomic_inc_return(&dev->enable_cnt) > 1)
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +09001185 return 0; /* already enabled */
1186
Yinghai Lu928bea92013-07-22 14:37:17 -07001187 pci_enable_bridge(dev->bus->self);
1188
Yinghai Lu497f16f2011-12-17 18:33:37 -08001189 /* only skip sriov related */
1190 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1191 if (dev->resource[i].flags & flags)
1192 bars |= (1 << i);
1193 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +11001194 if (dev->resource[i].flags & flags)
1195 bars |= (1 << i);
1196
Hidetoshi Seto38cc1302006-12-18 10:30:00 +09001197 err = do_pci_enable_device(dev, bars);
Greg Kroah-Hartman95a62962005-07-28 11:37:33 -07001198 if (err < 0)
Hidetoshi Seto38cc1302006-12-18 10:30:00 +09001199 atomic_dec(&dev->enable_cnt);
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +09001200 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001201}
1202
1203/**
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +11001204 * pci_enable_device_io - Initialize a device for use with IO space
1205 * @dev: PCI device to be initialized
1206 *
1207 * Initialize device before it's used by a driver. Ask low-level code
1208 * to enable I/O resources. Wake up the device if it was suspended.
1209 * Beware, this function can fail.
1210 */
1211int pci_enable_device_io(struct pci_dev *dev)
1212{
Bjorn Helgaasb4b4fbb2013-01-04 12:12:55 -07001213 return pci_enable_device_flags(dev, IORESOURCE_IO);
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +11001214}
1215
1216/**
1217 * pci_enable_device_mem - Initialize a device for use with Memory space
1218 * @dev: PCI device to be initialized
1219 *
1220 * Initialize device before it's used by a driver. Ask low-level code
1221 * to enable Memory resources. Wake up the device if it was suspended.
1222 * Beware, this function can fail.
1223 */
1224int pci_enable_device_mem(struct pci_dev *dev)
1225{
Bjorn Helgaasb4b4fbb2013-01-04 12:12:55 -07001226 return pci_enable_device_flags(dev, IORESOURCE_MEM);
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +11001227}
1228
Linus Torvalds1da177e2005-04-16 15:20:36 -07001229/**
1230 * pci_enable_device - Initialize device before it's used by a driver.
1231 * @dev: PCI device to be initialized
1232 *
1233 * Initialize device before it's used by a driver. Ask low-level code
1234 * to enable I/O and memory. Wake up the device if it was suspended.
1235 * Beware, this function can fail.
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -08001236 *
1237 * Note we don't actually enable the device many times if we call
1238 * this function repeatedly (we just increment the count).
Linus Torvalds1da177e2005-04-16 15:20:36 -07001239 */
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -08001240int pci_enable_device(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001241{
Bjorn Helgaasb4b4fbb2013-01-04 12:12:55 -07001242 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001243}
1244
Tejun Heo9ac78492007-01-20 16:00:26 +09001245/*
1246 * Managed PCI resources. This manages device on/off, intx/msi/msix
1247 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1248 * there's no need to track it separately. pci_devres is initialized
1249 * when a device is enabled using managed PCI device enable interface.
1250 */
1251struct pci_devres {
Tejun Heo7f375f32007-02-25 04:36:01 -08001252 unsigned int enabled:1;
1253 unsigned int pinned:1;
Tejun Heo9ac78492007-01-20 16:00:26 +09001254 unsigned int orig_intx:1;
1255 unsigned int restore_intx:1;
1256 u32 region_mask;
1257};
1258
1259static void pcim_release(struct device *gendev, void *res)
1260{
1261 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1262 struct pci_devres *this = res;
1263 int i;
1264
1265 if (dev->msi_enabled)
1266 pci_disable_msi(dev);
1267 if (dev->msix_enabled)
1268 pci_disable_msix(dev);
1269
1270 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1271 if (this->region_mask & (1 << i))
1272 pci_release_region(dev, i);
1273
1274 if (this->restore_intx)
1275 pci_intx(dev, this->orig_intx);
1276
Tejun Heo7f375f32007-02-25 04:36:01 -08001277 if (this->enabled && !this->pinned)
Tejun Heo9ac78492007-01-20 16:00:26 +09001278 pci_disable_device(dev);
1279}
1280
1281static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1282{
1283 struct pci_devres *dr, *new_dr;
1284
1285 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1286 if (dr)
1287 return dr;
1288
1289 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1290 if (!new_dr)
1291 return NULL;
1292 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1293}
1294
1295static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1296{
1297 if (pci_is_managed(pdev))
1298 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1299 return NULL;
1300}
1301
1302/**
1303 * pcim_enable_device - Managed pci_enable_device()
1304 * @pdev: PCI device to be initialized
1305 *
1306 * Managed pci_enable_device().
1307 */
1308int pcim_enable_device(struct pci_dev *pdev)
1309{
1310 struct pci_devres *dr;
1311 int rc;
1312
1313 dr = get_pci_dr(pdev);
1314 if (unlikely(!dr))
1315 return -ENOMEM;
Tejun Heob95d58e2008-01-30 18:20:04 +09001316 if (dr->enabled)
1317 return 0;
Tejun Heo9ac78492007-01-20 16:00:26 +09001318
1319 rc = pci_enable_device(pdev);
1320 if (!rc) {
1321 pdev->is_managed = 1;
Tejun Heo7f375f32007-02-25 04:36:01 -08001322 dr->enabled = 1;
Tejun Heo9ac78492007-01-20 16:00:26 +09001323 }
1324 return rc;
1325}
1326
1327/**
1328 * pcim_pin_device - Pin managed PCI device
1329 * @pdev: PCI device to pin
1330 *
1331 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1332 * driver detach. @pdev must have been enabled with
1333 * pcim_enable_device().
1334 */
1335void pcim_pin_device(struct pci_dev *pdev)
1336{
1337 struct pci_devres *dr;
1338
1339 dr = find_pci_dr(pdev);
Tejun Heo7f375f32007-02-25 04:36:01 -08001340 WARN_ON(!dr || !dr->enabled);
Tejun Heo9ac78492007-01-20 16:00:26 +09001341 if (dr)
Tejun Heo7f375f32007-02-25 04:36:01 -08001342 dr->pinned = 1;
Tejun Heo9ac78492007-01-20 16:00:26 +09001343}
1344
Matthew Garretteca0d462012-12-05 14:33:27 -07001345/*
1346 * pcibios_add_device - provide arch specific hooks when adding device dev
1347 * @dev: the PCI device being added
1348 *
1349 * Permits the platform to provide architecture specific functionality when
1350 * devices are added. This is the default implementation. Architecture
1351 * implementations can override this.
1352 */
1353int __weak pcibios_add_device (struct pci_dev *dev)
1354{
1355 return 0;
1356}
1357
Linus Torvalds1da177e2005-04-16 15:20:36 -07001358/**
Sebastian Ott6ae32c52013-06-04 19:18:14 +02001359 * pcibios_release_device - provide arch specific hooks when releasing device dev
1360 * @dev: the PCI device being released
1361 *
1362 * Permits the platform to provide architecture specific functionality when
1363 * devices are released. This is the default implementation. Architecture
1364 * implementations can override this.
1365 */
1366void __weak pcibios_release_device(struct pci_dev *dev) {}
1367
1368/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07001369 * pcibios_disable_device - disable arch specific PCI resources for device dev
1370 * @dev: the PCI device to disable
1371 *
1372 * Disables architecture specific PCI resources for the device. This
1373 * is the default implementation. Architecture implementations can
1374 * override this.
1375 */
Bjorn Helgaasd6d88c82012-06-19 06:54:49 -06001376void __weak pcibios_disable_device (struct pci_dev *dev) {}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001377
Rafael J. Wysockifa58d302009-01-07 13:03:42 +01001378static void do_pci_disable_device(struct pci_dev *dev)
1379{
1380 u16 pci_command;
1381
1382 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1383 if (pci_command & PCI_COMMAND_MASTER) {
1384 pci_command &= ~PCI_COMMAND_MASTER;
1385 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1386 }
1387
1388 pcibios_disable_device(dev);
1389}
1390
1391/**
1392 * pci_disable_enabled_device - Disable device without updating enable_cnt
1393 * @dev: PCI device to disable
1394 *
1395 * NOTE: This function is a backend of PCI power management routines and is
1396 * not supposed to be called drivers.
1397 */
1398void pci_disable_enabled_device(struct pci_dev *dev)
1399{
Yuji Shimada296ccb02009-04-03 16:41:46 +09001400 if (pci_is_enabled(dev))
Rafael J. Wysockifa58d302009-01-07 13:03:42 +01001401 do_pci_disable_device(dev);
1402}
1403
Linus Torvalds1da177e2005-04-16 15:20:36 -07001404/**
1405 * pci_disable_device - Disable PCI device after use
1406 * @dev: PCI device to be disabled
1407 *
1408 * Signal to the system that the PCI device is not in use by the system
1409 * anymore. This only involves disabling PCI bus-mastering, if active.
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -08001410 *
1411 * Note we don't actually disable the device until all callers of
Roman Fietzeee6583f2010-05-18 14:45:47 +02001412 * pci_enable_device() have called pci_disable_device().
Linus Torvalds1da177e2005-04-16 15:20:36 -07001413 */
1414void
1415pci_disable_device(struct pci_dev *dev)
1416{
Tejun Heo9ac78492007-01-20 16:00:26 +09001417 struct pci_devres *dr;
Shaohua Li99dc8042006-05-26 10:58:27 +08001418
Tejun Heo9ac78492007-01-20 16:00:26 +09001419 dr = find_pci_dr(dev);
1420 if (dr)
Tejun Heo7f375f32007-02-25 04:36:01 -08001421 dr->enabled = 0;
Tejun Heo9ac78492007-01-20 16:00:26 +09001422
Konstantin Khlebnikovfd6dcea2013-02-04 15:56:01 +04001423 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1424 "disabling already-disabled device");
1425
Bjorn Helgaascc7ba392013-02-11 16:47:01 -07001426 if (atomic_dec_return(&dev->enable_cnt) != 0)
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -08001427 return;
1428
Rafael J. Wysockifa58d302009-01-07 13:03:42 +01001429 do_pci_disable_device(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001430
Rafael J. Wysockifa58d302009-01-07 13:03:42 +01001431 dev->is_busmaster = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001432}
1433
1434/**
Brian Kingf7bdd122007-04-06 16:39:36 -05001435 * pcibios_set_pcie_reset_state - set reset state for device dev
Stefan Assmann45e829e2009-12-03 06:49:24 -05001436 * @dev: the PCIe device reset
Brian Kingf7bdd122007-04-06 16:39:36 -05001437 * @state: Reset state to enter into
1438 *
1439 *
Stefan Assmann45e829e2009-12-03 06:49:24 -05001440 * Sets the PCIe reset state for the device. This is the default
Brian Kingf7bdd122007-04-06 16:39:36 -05001441 * implementation. Architecture implementations can override this.
1442 */
Bjorn Helgaasd6d88c82012-06-19 06:54:49 -06001443int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1444 enum pcie_reset_state state)
Brian Kingf7bdd122007-04-06 16:39:36 -05001445{
1446 return -EINVAL;
1447}
1448
1449/**
1450 * pci_set_pcie_reset_state - set reset state for device dev
Stefan Assmann45e829e2009-12-03 06:49:24 -05001451 * @dev: the PCIe device reset
Brian Kingf7bdd122007-04-06 16:39:36 -05001452 * @state: Reset state to enter into
1453 *
1454 *
1455 * Sets the PCI reset state for the device.
1456 */
1457int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1458{
1459 return pcibios_set_pcie_reset_state(dev, state);
1460}
1461
1462/**
Rafael J. Wysocki58ff4632010-02-17 23:36:58 +01001463 * pci_check_pme_status - Check if given device has generated PME.
1464 * @dev: Device to check.
1465 *
1466 * Check the PME status of the device and if set, clear it and clear PME enable
1467 * (if set). Return 'true' if PME status and PME enable were both set or
1468 * 'false' otherwise.
1469 */
1470bool pci_check_pme_status(struct pci_dev *dev)
1471{
1472 int pmcsr_pos;
1473 u16 pmcsr;
1474 bool ret = false;
1475
1476 if (!dev->pm_cap)
1477 return false;
1478
1479 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1480 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1481 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1482 return false;
1483
1484 /* Clear PME status. */
1485 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1486 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1487 /* Disable PME to avoid interrupt flood. */
1488 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1489 ret = true;
1490 }
1491
1492 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1493
1494 return ret;
1495}
1496
1497/**
Rafael J. Wysockib67ea762010-02-17 23:44:09 +01001498 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1499 * @dev: Device to handle.
Rafael J. Wysocki379021d2011-10-03 23:16:33 +02001500 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
Rafael J. Wysockib67ea762010-02-17 23:44:09 +01001501 *
1502 * Check if @dev has generated PME and queue a resume request for it in that
1503 * case.
1504 */
Rafael J. Wysocki379021d2011-10-03 23:16:33 +02001505static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
Rafael J. Wysockib67ea762010-02-17 23:44:09 +01001506{
Rafael J. Wysocki379021d2011-10-03 23:16:33 +02001507 if (pme_poll_reset && dev->pme_poll)
1508 dev->pme_poll = false;
1509
Rafael J. Wysockic125e962010-07-05 22:43:53 +02001510 if (pci_check_pme_status(dev)) {
Rafael J. Wysockic125e962010-07-05 22:43:53 +02001511 pci_wakeup_event(dev);
Rafael J. Wysocki0f953bf2010-12-29 13:22:08 +01001512 pm_request_resume(&dev->dev);
Rafael J. Wysockic125e962010-07-05 22:43:53 +02001513 }
Rafael J. Wysockib67ea762010-02-17 23:44:09 +01001514 return 0;
1515}
1516
1517/**
1518 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1519 * @bus: Top bus of the subtree to walk.
1520 */
1521void pci_pme_wakeup_bus(struct pci_bus *bus)
1522{
1523 if (bus)
Rafael J. Wysocki379021d2011-10-03 23:16:33 +02001524 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
Rafael J. Wysockib67ea762010-02-17 23:44:09 +01001525}
1526
1527/**
Huang Ying448bd852012-06-23 10:23:51 +08001528 * pci_wakeup - Wake up a PCI device
Randy Dunlapceaf5b52012-08-18 17:37:53 -07001529 * @pci_dev: Device to handle.
Huang Ying448bd852012-06-23 10:23:51 +08001530 * @ign: ignored parameter
1531 */
1532static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
1533{
1534 pci_wakeup_event(pci_dev);
1535 pm_request_resume(&pci_dev->dev);
1536 return 0;
1537}
1538
1539/**
1540 * pci_wakeup_bus - Walk given bus and wake up devices on it
1541 * @bus: Top bus of the subtree to walk.
1542 */
1543void pci_wakeup_bus(struct pci_bus *bus)
1544{
1545 if (bus)
1546 pci_walk_bus(bus, pci_wakeup, NULL);
1547}
1548
1549/**
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001550 * pci_pme_capable - check the capability of PCI device to generate PME#
1551 * @dev: PCI device to handle.
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001552 * @state: PCI state from which device will issue PME#.
1553 */
Rafael J. Wysockie5899e12008-07-19 14:39:24 +02001554bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001555{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001556 if (!dev->pm_cap)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001557 return false;
1558
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001559 return !!(dev->pme_support & (1 << state));
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001560}
1561
Matthew Garrettdf17e622010-10-04 14:22:29 -04001562static void pci_pme_list_scan(struct work_struct *work)
1563{
Rafael J. Wysocki379021d2011-10-03 23:16:33 +02001564 struct pci_pme_device *pme_dev, *n;
Matthew Garrettdf17e622010-10-04 14:22:29 -04001565
1566 mutex_lock(&pci_pme_list_mutex);
1567 if (!list_empty(&pci_pme_list)) {
Rafael J. Wysocki379021d2011-10-03 23:16:33 +02001568 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1569 if (pme_dev->dev->pme_poll) {
Zheng Yan71a83bd2012-06-23 10:23:49 +08001570 struct pci_dev *bridge;
1571
1572 bridge = pme_dev->dev->bus->self;
1573 /*
1574 * If bridge is in low power state, the
1575 * configuration space of subordinate devices
1576 * may be not accessible
1577 */
1578 if (bridge && bridge->current_state != PCI_D0)
1579 continue;
Rafael J. Wysocki379021d2011-10-03 23:16:33 +02001580 pci_pme_wakeup(pme_dev->dev, NULL);
1581 } else {
1582 list_del(&pme_dev->list);
1583 kfree(pme_dev);
1584 }
1585 }
1586 if (!list_empty(&pci_pme_list))
1587 schedule_delayed_work(&pci_pme_work,
1588 msecs_to_jiffies(PME_TIMEOUT));
Matthew Garrettdf17e622010-10-04 14:22:29 -04001589 }
1590 mutex_unlock(&pci_pme_list_mutex);
1591}
1592
1593/**
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001594 * pci_pme_active - enable or disable PCI device's PME# function
1595 * @dev: PCI device to handle.
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001596 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1597 *
1598 * The caller must verify that the device is capable of generating PME# before
1599 * calling this function with @enable equal to 'true'.
1600 */
Rafael J. Wysocki5a6c9b62008-08-08 00:14:24 +02001601void pci_pme_active(struct pci_dev *dev, bool enable)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001602{
1603 u16 pmcsr;
1604
Rafael J. Wysockiffaddbe2013-04-10 10:32:51 +00001605 if (!dev->pme_support)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001606 return;
1607
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001608 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001609 /* Clear PME_Status by writing 1 to it and enable PME# */
1610 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1611 if (!enable)
1612 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1613
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001614 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001615
Huang Ying6e965e02012-10-26 13:07:51 +08001616 /*
1617 * PCI (as opposed to PCIe) PME requires that the device have
1618 * its PME# line hooked up correctly. Not all hardware vendors
1619 * do this, so the PME never gets delivered and the device
1620 * remains asleep. The easiest way around this is to
1621 * periodically walk the list of suspended devices and check
1622 * whether any have their PME flag set. The assumption is that
1623 * we'll wake up often enough anyway that this won't be a huge
1624 * hit, and the power savings from the devices will still be a
1625 * win.
1626 *
1627 * Although PCIe uses in-band PME message instead of PME# line
1628 * to report PME, PME does not work for some PCIe devices in
1629 * reality. For example, there are devices that set their PME
1630 * status bits, but don't really bother to send a PME message;
1631 * there are PCI Express Root Ports that don't bother to
1632 * trigger interrupts when they receive PME messages from the
1633 * devices below. So PME poll is used for PCIe devices too.
1634 */
Matthew Garrettdf17e622010-10-04 14:22:29 -04001635
Rafael J. Wysocki379021d2011-10-03 23:16:33 +02001636 if (dev->pme_poll) {
Matthew Garrettdf17e622010-10-04 14:22:29 -04001637 struct pci_pme_device *pme_dev;
1638 if (enable) {
1639 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1640 GFP_KERNEL);
1641 if (!pme_dev)
1642 goto out;
1643 pme_dev->dev = dev;
1644 mutex_lock(&pci_pme_list_mutex);
1645 list_add(&pme_dev->list, &pci_pme_list);
1646 if (list_is_singular(&pci_pme_list))
1647 schedule_delayed_work(&pci_pme_work,
1648 msecs_to_jiffies(PME_TIMEOUT));
1649 mutex_unlock(&pci_pme_list_mutex);
1650 } else {
1651 mutex_lock(&pci_pme_list_mutex);
1652 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1653 if (pme_dev->dev == dev) {
1654 list_del(&pme_dev->list);
1655 kfree(pme_dev);
1656 break;
1657 }
1658 }
1659 mutex_unlock(&pci_pme_list_mutex);
1660 }
1661 }
1662
1663out:
Vincent Palatin85b85822011-12-05 11:51:18 -08001664 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001665}
1666
1667/**
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001668 * __pci_enable_wake - enable PCI device as wakeup event source
David Brownell075c1772007-04-26 00:12:06 -07001669 * @dev: PCI device affected
1670 * @state: PCI state from which device will issue wakeup events
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001671 * @runtime: True if the events are to be generated at run time
David Brownell075c1772007-04-26 00:12:06 -07001672 * @enable: True to enable event generation; false to disable
Linus Torvalds1da177e2005-04-16 15:20:36 -07001673 *
David Brownell075c1772007-04-26 00:12:06 -07001674 * This enables the device as a wakeup event source, or disables it.
1675 * When such events involves platform-specific hooks, those hooks are
1676 * called automatically by this routine.
1677 *
1678 * Devices with legacy power management (no standard PCI PM capabilities)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001679 * always require such platform hooks.
David Brownell075c1772007-04-26 00:12:06 -07001680 *
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001681 * RETURN VALUE:
1682 * 0 is returned on success
1683 * -EINVAL is returned if device is not supposed to wake up the system
1684 * Error code depending on the platform is returned if both the platform and
1685 * the native mechanism fail to enable the generation of wake-up events
Linus Torvalds1da177e2005-04-16 15:20:36 -07001686 */
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001687int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1688 bool runtime, bool enable)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001689{
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001690 int ret = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001691
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001692 if (enable && !runtime && !device_may_wakeup(&dev->dev))
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001693 return -EINVAL;
1694
Rafael J. Wysockie80bb092009-09-08 23:14:49 +02001695 /* Don't do the same thing twice in a row for one device. */
1696 if (!!enable == !!dev->wakeup_prepared)
1697 return 0;
1698
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001699 /*
1700 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1701 * Anderson we should be doing PME# wake enable followed by ACPI wake
1702 * enable. To disable wake-up we call the platform first, for symmetry.
David Brownell075c1772007-04-26 00:12:06 -07001703 */
1704
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001705 if (enable) {
1706 int error;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001707
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001708 if (pci_pme_capable(dev, state))
1709 pci_pme_active(dev, true);
1710 else
1711 ret = 1;
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001712 error = runtime ? platform_pci_run_wake(dev, true) :
1713 platform_pci_sleep_wake(dev, true);
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001714 if (ret)
1715 ret = error;
Rafael J. Wysockie80bb092009-09-08 23:14:49 +02001716 if (!ret)
1717 dev->wakeup_prepared = true;
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001718 } else {
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001719 if (runtime)
1720 platform_pci_run_wake(dev, false);
1721 else
1722 platform_pci_sleep_wake(dev, false);
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001723 pci_pme_active(dev, false);
Rafael J. Wysockie80bb092009-09-08 23:14:49 +02001724 dev->wakeup_prepared = false;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001725 }
1726
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001727 return ret;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001728}
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001729EXPORT_SYMBOL(__pci_enable_wake);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001730
1731/**
Rafael J. Wysocki0235c4f2008-08-18 21:38:00 +02001732 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1733 * @dev: PCI device to prepare
1734 * @enable: True to enable wake-up event generation; false to disable
1735 *
1736 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1737 * and this function allows them to set that up cleanly - pci_enable_wake()
1738 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1739 * ordering constraints.
1740 *
1741 * This function only returns error code if the device is not capable of
1742 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1743 * enable wake-up power for it.
1744 */
1745int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1746{
1747 return pci_pme_capable(dev, PCI_D3cold) ?
1748 pci_enable_wake(dev, PCI_D3cold, enable) :
1749 pci_enable_wake(dev, PCI_D3hot, enable);
1750}
1751
1752/**
Jesse Barnes37139072008-07-28 11:49:26 -07001753 * pci_target_state - find an appropriate low power state for a given PCI dev
1754 * @dev: PCI device
1755 *
1756 * Use underlying platform code to find a supported low power state for @dev.
1757 * If the platform can't manage @dev, return the deepest state from which it
1758 * can generate wake events, based on any available PME info.
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001759 */
Rafael J. Wysockie5899e12008-07-19 14:39:24 +02001760pci_power_t pci_target_state(struct pci_dev *dev)
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001761{
1762 pci_power_t target_state = PCI_D3hot;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001763
1764 if (platform_pci_power_manageable(dev)) {
1765 /*
1766 * Call the platform to choose the target state of the device
1767 * and enable wake-up from this state if supported.
1768 */
1769 pci_power_t state = platform_pci_choose_state(dev);
1770
1771 switch (state) {
1772 case PCI_POWER_ERROR:
1773 case PCI_UNKNOWN:
1774 break;
1775 case PCI_D1:
1776 case PCI_D2:
1777 if (pci_no_d1d2(dev))
1778 break;
1779 default:
1780 target_state = state;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001781 }
Rafael J. Wysockid2abdf62009-06-14 21:25:02 +02001782 } else if (!dev->pm_cap) {
1783 target_state = PCI_D0;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001784 } else if (device_may_wakeup(&dev->dev)) {
1785 /*
1786 * Find the deepest state from which the device can generate
1787 * wake-up events, make it the target state and enable device
1788 * to generate PME#.
1789 */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001790 if (dev->pme_support) {
1791 while (target_state
1792 && !(dev->pme_support & (1 << target_state)))
1793 target_state--;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001794 }
1795 }
1796
Rafael J. Wysockie5899e12008-07-19 14:39:24 +02001797 return target_state;
1798}
1799
1800/**
1801 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1802 * @dev: Device to handle.
1803 *
1804 * Choose the power state appropriate for the device depending on whether
1805 * it can wake up the system and/or is power manageable by the platform
1806 * (PCI_D3hot is the default) and put the device into that state.
1807 */
1808int pci_prepare_to_sleep(struct pci_dev *dev)
1809{
1810 pci_power_t target_state = pci_target_state(dev);
1811 int error;
1812
1813 if (target_state == PCI_POWER_ERROR)
1814 return -EIO;
1815
Huang Ying448bd852012-06-23 10:23:51 +08001816 /* D3cold during system suspend/hibernate is not supported */
1817 if (target_state > PCI_D3hot)
1818 target_state = PCI_D3hot;
1819
Rafael J. Wysocki8efb8c72009-03-30 21:46:27 +02001820 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
Rafael J. Wysockic157dfa2008-07-13 22:45:06 +02001821
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001822 error = pci_set_power_state(dev, target_state);
1823
1824 if (error)
1825 pci_enable_wake(dev, target_state, false);
1826
1827 return error;
1828}
1829
1830/**
Randy Dunlap443bd1c2008-07-21 09:27:18 -07001831 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001832 * @dev: Device to handle.
1833 *
Thomas Weber88393162010-03-16 11:47:56 +01001834 * Disable device's system wake-up capability and put it into D0.
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001835 */
1836int pci_back_from_sleep(struct pci_dev *dev)
1837{
1838 pci_enable_wake(dev, PCI_D0, false);
1839 return pci_set_power_state(dev, PCI_D0);
1840}
1841
1842/**
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001843 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1844 * @dev: PCI device being suspended.
1845 *
1846 * Prepare @dev to generate wake-up events at run time and put it into a low
1847 * power state.
1848 */
1849int pci_finish_runtime_suspend(struct pci_dev *dev)
1850{
1851 pci_power_t target_state = pci_target_state(dev);
1852 int error;
1853
1854 if (target_state == PCI_POWER_ERROR)
1855 return -EIO;
1856
Huang Ying448bd852012-06-23 10:23:51 +08001857 dev->runtime_d3cold = target_state == PCI_D3cold;
1858
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001859 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1860
1861 error = pci_set_power_state(dev, target_state);
1862
Huang Ying448bd852012-06-23 10:23:51 +08001863 if (error) {
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001864 __pci_enable_wake(dev, target_state, true, false);
Huang Ying448bd852012-06-23 10:23:51 +08001865 dev->runtime_d3cold = false;
1866 }
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001867
1868 return error;
1869}
1870
1871/**
Rafael J. Wysockib67ea762010-02-17 23:44:09 +01001872 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1873 * @dev: Device to check.
1874 *
1875 * Return true if the device itself is cabable of generating wake-up events
1876 * (through the platform or using the native PCIe PME) or if the device supports
1877 * PME and one of its upstream bridges can generate wake-up events.
1878 */
1879bool pci_dev_run_wake(struct pci_dev *dev)
1880{
1881 struct pci_bus *bus = dev->bus;
1882
1883 if (device_run_wake(&dev->dev))
1884 return true;
1885
1886 if (!dev->pme_support)
1887 return false;
1888
1889 while (bus->parent) {
1890 struct pci_dev *bridge = bus->self;
1891
1892 if (device_run_wake(&bridge->dev))
1893 return true;
1894
1895 bus = bus->parent;
1896 }
1897
1898 /* We have reached the root bus. */
1899 if (bus->bridge)
1900 return device_run_wake(bus->bridge);
1901
1902 return false;
1903}
1904EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1905
Huang Yingb3c32c42012-10-25 09:36:03 +08001906void pci_config_pm_runtime_get(struct pci_dev *pdev)
1907{
1908 struct device *dev = &pdev->dev;
1909 struct device *parent = dev->parent;
1910
1911 if (parent)
1912 pm_runtime_get_sync(parent);
1913 pm_runtime_get_noresume(dev);
1914 /*
1915 * pdev->current_state is set to PCI_D3cold during suspending,
1916 * so wait until suspending completes
1917 */
1918 pm_runtime_barrier(dev);
1919 /*
1920 * Only need to resume devices in D3cold, because config
1921 * registers are still accessible for devices suspended but
1922 * not in D3cold.
1923 */
1924 if (pdev->current_state == PCI_D3cold)
1925 pm_runtime_resume(dev);
1926}
1927
1928void pci_config_pm_runtime_put(struct pci_dev *pdev)
1929{
1930 struct device *dev = &pdev->dev;
1931 struct device *parent = dev->parent;
1932
1933 pm_runtime_put(dev);
1934 if (parent)
1935 pm_runtime_put_sync(parent);
1936}
1937
Rafael J. Wysockib67ea762010-02-17 23:44:09 +01001938/**
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001939 * pci_pm_init - Initialize PM functions of given PCI device
1940 * @dev: PCI device to handle.
1941 */
1942void pci_pm_init(struct pci_dev *dev)
1943{
1944 int pm;
1945 u16 pmc;
David Brownell075c1772007-04-26 00:12:06 -07001946
Rafael J. Wysockibb910a72010-02-27 21:37:37 +01001947 pm_runtime_forbid(&dev->dev);
Huang Ying967577b2012-11-20 16:08:22 +08001948 pm_runtime_set_active(&dev->dev);
1949 pm_runtime_enable(&dev->dev);
Rafael J. Wysockia1e4d722010-02-08 19:16:33 +01001950 device_enable_async_suspend(&dev->dev);
Rafael J. Wysockie80bb092009-09-08 23:14:49 +02001951 dev->wakeup_prepared = false;
Rafael J. Wysockibb910a72010-02-27 21:37:37 +01001952
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001953 dev->pm_cap = 0;
Rafael J. Wysockiffaddbe2013-04-10 10:32:51 +00001954 dev->pme_support = 0;
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001955
Linus Torvalds1da177e2005-04-16 15:20:36 -07001956 /* find PCI PM capability in list */
1957 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
David Brownell075c1772007-04-26 00:12:06 -07001958 if (!pm)
Linus Torvalds50246dd2009-01-16 08:14:51 -08001959 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001960 /* Check device's ability to generate PME# */
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001961 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001962
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001963 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1964 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1965 pmc & PCI_PM_CAP_VER_MASK);
Linus Torvalds50246dd2009-01-16 08:14:51 -08001966 return;
David Brownell075c1772007-04-26 00:12:06 -07001967 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001968
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001969 dev->pm_cap = pm;
Rafael J. Wysocki1ae861e2009-12-31 12:15:54 +01001970 dev->d3_delay = PCI_PM_D3_WAIT;
Huang Ying448bd852012-06-23 10:23:51 +08001971 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
Huang Ying4f9c1392012-08-08 09:07:38 +08001972 dev->d3cold_allowed = true;
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001973
1974 dev->d1_support = false;
1975 dev->d2_support = false;
1976 if (!pci_no_d1d2(dev)) {
Bjorn Helgaasc9ed77e2008-08-22 09:37:02 -06001977 if (pmc & PCI_PM_CAP_D1)
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001978 dev->d1_support = true;
Bjorn Helgaasc9ed77e2008-08-22 09:37:02 -06001979 if (pmc & PCI_PM_CAP_D2)
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001980 dev->d2_support = true;
Bjorn Helgaasc9ed77e2008-08-22 09:37:02 -06001981
1982 if (dev->d1_support || dev->d2_support)
1983 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
Jesse Barnesec84f122008-09-23 11:43:34 -07001984 dev->d1_support ? " D1" : "",
1985 dev->d2_support ? " D2" : "");
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001986 }
1987
1988 pmc &= PCI_PM_CAP_PME_MASK;
1989 if (pmc) {
Bjorn Helgaas10c3d712009-11-04 10:32:42 -07001990 dev_printk(KERN_DEBUG, &dev->dev,
1991 "PME# supported from%s%s%s%s%s\n",
Bjorn Helgaasc9ed77e2008-08-22 09:37:02 -06001992 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1993 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1994 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1995 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1996 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001997 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
Rafael J. Wysocki379021d2011-10-03 23:16:33 +02001998 dev->pme_poll = true;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001999 /*
2000 * Make device's PM flags reflect the wake-up capability, but
2001 * let the user space enable it to wake up the system as needed.
2002 */
2003 device_set_wakeup_capable(&dev->dev, true);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02002004 /* Disable the PME# generation functionality */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02002005 pci_pme_active(dev, false);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02002006 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002007}
2008
Yinghai Lu34a48762012-02-11 00:18:41 -08002009static void pci_add_saved_cap(struct pci_dev *pci_dev,
2010 struct pci_cap_saved_state *new_cap)
2011{
2012 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2013}
2014
Jesse Barneseb9c39d2008-12-17 12:10:05 -08002015/**
Yijing Wangce1be102013-08-01 21:05:27 +08002016 * pci_add_cap_save_buffer - allocate buffer for saving given capability registers
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01002017 * @dev: the PCI device
2018 * @cap: the capability to allocate the buffer for
2019 * @size: requested size of the buffer
2020 */
2021static int pci_add_cap_save_buffer(
2022 struct pci_dev *dev, char cap, unsigned int size)
2023{
2024 int pos;
2025 struct pci_cap_saved_state *save_state;
2026
2027 pos = pci_find_capability(dev, cap);
2028 if (pos <= 0)
2029 return 0;
2030
2031 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2032 if (!save_state)
2033 return -ENOMEM;
2034
Alex Williamson24a4742f2011-05-10 10:02:11 -06002035 save_state->cap.cap_nr = cap;
2036 save_state->cap.size = size;
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01002037 pci_add_saved_cap(dev, save_state);
2038
2039 return 0;
2040}
2041
2042/**
2043 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2044 * @dev: the PCI device
2045 */
2046void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2047{
2048 int error;
2049
Yu Zhao89858512009-02-16 02:55:47 +08002050 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2051 PCI_EXP_SAVE_REGS * sizeof(u16));
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01002052 if (error)
2053 dev_err(&dev->dev,
2054 "unable to preallocate PCI Express save buffer\n");
2055
2056 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2057 if (error)
2058 dev_err(&dev->dev,
2059 "unable to preallocate PCI-X save buffer\n");
2060}
2061
Yinghai Luf7968412012-02-11 00:18:30 -08002062void pci_free_cap_save_buffers(struct pci_dev *dev)
2063{
2064 struct pci_cap_saved_state *tmp;
Sasha Levinb67bfe02013-02-27 17:06:00 -08002065 struct hlist_node *n;
Yinghai Luf7968412012-02-11 00:18:30 -08002066
Sasha Levinb67bfe02013-02-27 17:06:00 -08002067 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
Yinghai Luf7968412012-02-11 00:18:30 -08002068 kfree(tmp);
2069}
2070
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01002071/**
Yijing Wang31ab2472013-01-15 11:12:17 +08002072 * pci_configure_ari - enable or disable ARI forwarding
Yu Zhao58c3a722008-10-14 14:02:53 +08002073 * @dev: the PCI device
Yijing Wangb0cc6022013-01-15 11:12:16 +08002074 *
2075 * If @dev and its upstream bridge both support ARI, enable ARI in the
2076 * bridge. Otherwise, disable ARI in the bridge.
Yu Zhao58c3a722008-10-14 14:02:53 +08002077 */
Yijing Wang31ab2472013-01-15 11:12:17 +08002078void pci_configure_ari(struct pci_dev *dev)
Yu Zhao58c3a722008-10-14 14:02:53 +08002079{
Yu Zhao58c3a722008-10-14 14:02:53 +08002080 u32 cap;
Zhao, Yu81135872008-10-23 13:15:39 +08002081 struct pci_dev *bridge;
Yu Zhao58c3a722008-10-14 14:02:53 +08002082
Rafael J. Wysocki6748dcc2012-03-01 00:06:33 +01002083 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
Yu Zhao58c3a722008-10-14 14:02:53 +08002084 return;
2085
Zhao, Yu81135872008-10-23 13:15:39 +08002086 bridge = dev->bus->self;
Myron Stowecb97ae32012-06-01 15:16:31 -06002087 if (!bridge)
Zhao, Yu81135872008-10-23 13:15:39 +08002088 return;
2089
Jiang Liu59875ae2012-07-24 17:20:06 +08002090 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
Yu Zhao58c3a722008-10-14 14:02:53 +08002091 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2092 return;
2093
Yijing Wangb0cc6022013-01-15 11:12:16 +08002094 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2095 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2096 PCI_EXP_DEVCTL2_ARI);
2097 bridge->ari_enabled = 1;
2098 } else {
2099 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2100 PCI_EXP_DEVCTL2_ARI);
2101 bridge->ari_enabled = 0;
2102 }
Yu Zhao58c3a722008-10-14 14:02:53 +08002103}
2104
Jesse Barnesb48d4422010-10-19 13:07:57 -07002105/**
Myron Stowec463b8c2012-06-01 15:16:37 -06002106 * pci_enable_ido - enable ID-based Ordering on a device
Jesse Barnesb48d4422010-10-19 13:07:57 -07002107 * @dev: the PCI device
2108 * @type: which types of IDO to enable
2109 *
2110 * Enable ID-based ordering on @dev. @type can contain the bits
2111 * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
2112 * which types of transactions are allowed to be re-ordered.
2113 */
2114void pci_enable_ido(struct pci_dev *dev, unsigned long type)
2115{
Jiang Liu59875ae2012-07-24 17:20:06 +08002116 u16 ctrl = 0;
Jesse Barnesb48d4422010-10-19 13:07:57 -07002117
Jesse Barnesb48d4422010-10-19 13:07:57 -07002118 if (type & PCI_EXP_IDO_REQUEST)
Bjorn Helgaasd2ab1fa2013-08-27 11:11:10 -06002119 ctrl |= PCI_EXP_DEVCTL2_IDO_REQ_EN;
Jesse Barnesb48d4422010-10-19 13:07:57 -07002120 if (type & PCI_EXP_IDO_COMPLETION)
Bjorn Helgaasd2ab1fa2013-08-27 11:11:10 -06002121 ctrl |= PCI_EXP_DEVCTL2_IDO_CMP_EN;
Jiang Liu59875ae2012-07-24 17:20:06 +08002122 if (ctrl)
2123 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, ctrl);
Jesse Barnesb48d4422010-10-19 13:07:57 -07002124}
2125EXPORT_SYMBOL(pci_enable_ido);
2126
2127/**
2128 * pci_disable_ido - disable ID-based ordering on a device
2129 * @dev: the PCI device
2130 * @type: which types of IDO to disable
2131 */
2132void pci_disable_ido(struct pci_dev *dev, unsigned long type)
2133{
Jiang Liu59875ae2012-07-24 17:20:06 +08002134 u16 ctrl = 0;
Jesse Barnesb48d4422010-10-19 13:07:57 -07002135
Jesse Barnesb48d4422010-10-19 13:07:57 -07002136 if (type & PCI_EXP_IDO_REQUEST)
Bjorn Helgaasd2ab1fa2013-08-27 11:11:10 -06002137 ctrl |= PCI_EXP_DEVCTL2_IDO_REQ_EN;
Jesse Barnesb48d4422010-10-19 13:07:57 -07002138 if (type & PCI_EXP_IDO_COMPLETION)
Bjorn Helgaasd2ab1fa2013-08-27 11:11:10 -06002139 ctrl |= PCI_EXP_DEVCTL2_IDO_CMP_EN;
Jiang Liu59875ae2012-07-24 17:20:06 +08002140 if (ctrl)
2141 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2, ctrl);
Jesse Barnesb48d4422010-10-19 13:07:57 -07002142}
2143EXPORT_SYMBOL(pci_disable_ido);
2144
Jesse Barnes48a92a82011-01-10 12:46:36 -08002145/**
2146 * pci_enable_obff - enable optimized buffer flush/fill
2147 * @dev: PCI device
2148 * @type: type of signaling to use
2149 *
2150 * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
2151 * signaling if possible, falling back to message signaling only if
2152 * WAKE# isn't supported. @type should indicate whether the PCIe link
2153 * be brought out of L0s or L1 to send the message. It should be either
2154 * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
2155 *
2156 * If your device can benefit from receiving all messages, even at the
2157 * power cost of bringing the link back up from a low power state, use
2158 * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
2159 * preferred type).
2160 *
2161 * RETURNS:
2162 * Zero on success, appropriate error number on failure.
2163 */
2164int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
2165{
Jesse Barnes48a92a82011-01-10 12:46:36 -08002166 u32 cap;
2167 u16 ctrl;
2168 int ret;
2169
Jiang Liu59875ae2012-07-24 17:20:06 +08002170 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
Bjorn Helgaasd2ab1fa2013-08-27 11:11:10 -06002171 if (!(cap & PCI_EXP_DEVCAP2_OBFF_MASK))
Jesse Barnes48a92a82011-01-10 12:46:36 -08002172 return -ENOTSUPP; /* no OBFF support at all */
2173
2174 /* Make sure the topology supports OBFF as well */
Bjorn Helgaas82915502012-06-19 07:35:34 -06002175 if (dev->bus->self) {
Jesse Barnes48a92a82011-01-10 12:46:36 -08002176 ret = pci_enable_obff(dev->bus->self, type);
2177 if (ret)
2178 return ret;
2179 }
2180
Jiang Liu59875ae2012-07-24 17:20:06 +08002181 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &ctrl);
Bjorn Helgaasd2ab1fa2013-08-27 11:11:10 -06002182 if (cap & PCI_EXP_DEVCAP2_OBFF_WAKE)
2183 ctrl |= PCI_EXP_DEVCTL2_OBFF_WAKE_EN;
Jesse Barnes48a92a82011-01-10 12:46:36 -08002184 else {
2185 switch (type) {
2186 case PCI_EXP_OBFF_SIGNAL_L0:
Bjorn Helgaasd2ab1fa2013-08-27 11:11:10 -06002187 if (!(ctrl & PCI_EXP_DEVCTL2_OBFF_WAKE_EN))
2188 ctrl |= PCI_EXP_DEVCTL2_OBFF_MSGA_EN;
Jesse Barnes48a92a82011-01-10 12:46:36 -08002189 break;
2190 case PCI_EXP_OBFF_SIGNAL_ALWAYS:
Bjorn Helgaasd2ab1fa2013-08-27 11:11:10 -06002191 ctrl &= ~PCI_EXP_DEVCTL2_OBFF_WAKE_EN;
2192 ctrl |= PCI_EXP_DEVCTL2_OBFF_MSGB_EN;
Jesse Barnes48a92a82011-01-10 12:46:36 -08002193 break;
2194 default:
2195 WARN(1, "bad OBFF signal type\n");
2196 return -ENOTSUPP;
2197 }
2198 }
Jiang Liu59875ae2012-07-24 17:20:06 +08002199 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, ctrl);
Jesse Barnes48a92a82011-01-10 12:46:36 -08002200
2201 return 0;
2202}
2203EXPORT_SYMBOL(pci_enable_obff);
2204
2205/**
2206 * pci_disable_obff - disable optimized buffer flush/fill
2207 * @dev: PCI device
2208 *
2209 * Disable OBFF on @dev.
2210 */
2211void pci_disable_obff(struct pci_dev *dev)
2212{
Bjorn Helgaasd2ab1fa2013-08-27 11:11:10 -06002213 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2,
2214 PCI_EXP_DEVCTL2_OBFF_WAKE_EN);
Jesse Barnes48a92a82011-01-10 12:46:36 -08002215}
2216EXPORT_SYMBOL(pci_disable_obff);
2217
Jesse Barnes51c2e0a2011-01-14 08:53:04 -08002218/**
2219 * pci_ltr_supported - check whether a device supports LTR
2220 * @dev: PCI device
2221 *
2222 * RETURNS:
2223 * True if @dev supports latency tolerance reporting, false otherwise.
2224 */
Myron Stowec32823f2012-06-01 15:16:25 -06002225static bool pci_ltr_supported(struct pci_dev *dev)
Jesse Barnes51c2e0a2011-01-14 08:53:04 -08002226{
Jesse Barnes51c2e0a2011-01-14 08:53:04 -08002227 u32 cap;
2228
Jiang Liu59875ae2012-07-24 17:20:06 +08002229 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
Jesse Barnes51c2e0a2011-01-14 08:53:04 -08002230
2231 return cap & PCI_EXP_DEVCAP2_LTR;
2232}
Jesse Barnes51c2e0a2011-01-14 08:53:04 -08002233
2234/**
2235 * pci_enable_ltr - enable latency tolerance reporting
2236 * @dev: PCI device
2237 *
2238 * Enable LTR on @dev if possible, which means enabling it first on
2239 * upstream ports.
2240 *
2241 * RETURNS:
2242 * Zero on success, errno on failure.
2243 */
2244int pci_enable_ltr(struct pci_dev *dev)
2245{
Jesse Barnes51c2e0a2011-01-14 08:53:04 -08002246 int ret;
2247
Jesse Barnes51c2e0a2011-01-14 08:53:04 -08002248 /* Only primary function can enable/disable LTR */
2249 if (PCI_FUNC(dev->devfn) != 0)
2250 return -EINVAL;
2251
Jiang Liu59875ae2012-07-24 17:20:06 +08002252 if (!pci_ltr_supported(dev))
2253 return -ENOTSUPP;
2254
Jesse Barnes51c2e0a2011-01-14 08:53:04 -08002255 /* Enable upstream ports first */
Bjorn Helgaas82915502012-06-19 07:35:34 -06002256 if (dev->bus->self) {
Jesse Barnes51c2e0a2011-01-14 08:53:04 -08002257 ret = pci_enable_ltr(dev->bus->self);
2258 if (ret)
2259 return ret;
2260 }
2261
Bjorn Helgaasd2ab1fa2013-08-27 11:11:10 -06002262 return pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
2263 PCI_EXP_DEVCTL2_LTR_EN);
Jesse Barnes51c2e0a2011-01-14 08:53:04 -08002264}
2265EXPORT_SYMBOL(pci_enable_ltr);
2266
2267/**
2268 * pci_disable_ltr - disable latency tolerance reporting
2269 * @dev: PCI device
2270 */
2271void pci_disable_ltr(struct pci_dev *dev)
2272{
Jesse Barnes51c2e0a2011-01-14 08:53:04 -08002273 /* Only primary function can enable/disable LTR */
2274 if (PCI_FUNC(dev->devfn) != 0)
2275 return;
2276
Jiang Liu59875ae2012-07-24 17:20:06 +08002277 if (!pci_ltr_supported(dev))
2278 return;
2279
Bjorn Helgaasd2ab1fa2013-08-27 11:11:10 -06002280 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL2,
2281 PCI_EXP_DEVCTL2_LTR_EN);
Jesse Barnes51c2e0a2011-01-14 08:53:04 -08002282}
2283EXPORT_SYMBOL(pci_disable_ltr);
2284
2285static int __pci_ltr_scale(int *val)
2286{
2287 int scale = 0;
2288
2289 while (*val > 1023) {
2290 *val = (*val + 31) / 32;
2291 scale++;
2292 }
2293 return scale;
2294}
2295
2296/**
2297 * pci_set_ltr - set LTR latency values
2298 * @dev: PCI device
2299 * @snoop_lat_ns: snoop latency in nanoseconds
2300 * @nosnoop_lat_ns: nosnoop latency in nanoseconds
2301 *
2302 * Figure out the scale and set the LTR values accordingly.
2303 */
2304int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
2305{
2306 int pos, ret, snoop_scale, nosnoop_scale;
2307 u16 val;
2308
2309 if (!pci_ltr_supported(dev))
2310 return -ENOTSUPP;
2311
2312 snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
2313 nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
2314
2315 if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
2316 nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
2317 return -EINVAL;
2318
2319 if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
2320 (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
2321 return -EINVAL;
2322
2323 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
2324 if (!pos)
2325 return -ENOTSUPP;
2326
2327 val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
2328 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
2329 if (ret != 4)
2330 return -EIO;
2331
2332 val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
2333 ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
2334 if (ret != 4)
2335 return -EIO;
2336
2337 return 0;
2338}
2339EXPORT_SYMBOL(pci_set_ltr);
2340
Chris Wright5d990b62009-12-04 12:15:21 -08002341static int pci_acs_enable;
2342
2343/**
2344 * pci_request_acs - ask for ACS to be enabled if supported
2345 */
2346void pci_request_acs(void)
2347{
2348 pci_acs_enable = 1;
2349}
2350
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07002351/**
Allen Kayae21ee62009-10-07 10:27:17 -07002352 * pci_enable_acs - enable ACS if hardware support it
2353 * @dev: the PCI device
2354 */
2355void pci_enable_acs(struct pci_dev *dev)
2356{
2357 int pos;
2358 u16 cap;
2359 u16 ctrl;
2360
Chris Wright5d990b62009-12-04 12:15:21 -08002361 if (!pci_acs_enable)
2362 return;
2363
Allen Kayae21ee62009-10-07 10:27:17 -07002364 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2365 if (!pos)
2366 return;
2367
2368 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2369 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2370
2371 /* Source Validation */
2372 ctrl |= (cap & PCI_ACS_SV);
2373
2374 /* P2P Request Redirect */
2375 ctrl |= (cap & PCI_ACS_RR);
2376
2377 /* P2P Completion Redirect */
2378 ctrl |= (cap & PCI_ACS_CR);
2379
2380 /* Upstream Forwarding */
2381 ctrl |= (cap & PCI_ACS_UF);
2382
2383 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2384}
2385
Alex Williamson0a671192013-06-27 16:39:48 -06002386static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2387{
2388 int pos;
Alex Williamson83db7e02013-06-27 16:39:54 -06002389 u16 cap, ctrl;
Alex Williamson0a671192013-06-27 16:39:48 -06002390
2391 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2392 if (!pos)
2393 return false;
2394
Alex Williamson83db7e02013-06-27 16:39:54 -06002395 /*
2396 * Except for egress control, capabilities are either required
2397 * or only required if controllable. Features missing from the
2398 * capability field can therefore be assumed as hard-wired enabled.
2399 */
2400 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2401 acs_flags &= (cap | PCI_ACS_EC);
2402
Alex Williamson0a671192013-06-27 16:39:48 -06002403 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2404 return (ctrl & acs_flags) == acs_flags;
2405}
2406
Allen Kayae21ee62009-10-07 10:27:17 -07002407/**
Alex Williamsonad805752012-06-11 05:27:07 +00002408 * pci_acs_enabled - test ACS against required flags for a given device
2409 * @pdev: device to test
2410 * @acs_flags: required PCI ACS flags
2411 *
2412 * Return true if the device supports the provided flags. Automatically
2413 * filters out flags that are not implemented on multifunction devices.
Alex Williamson0a671192013-06-27 16:39:48 -06002414 *
2415 * Note that this interface checks the effective ACS capabilities of the
2416 * device rather than the actual capabilities. For instance, most single
2417 * function endpoints are not required to support ACS because they have no
2418 * opportunity for peer-to-peer access. We therefore return 'true'
2419 * regardless of whether the device exposes an ACS capability. This makes
2420 * it much easier for callers of this function to ignore the actual type
2421 * or topology of the device when testing ACS support.
Alex Williamsonad805752012-06-11 05:27:07 +00002422 */
2423bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2424{
Alex Williamson0a671192013-06-27 16:39:48 -06002425 int ret;
Alex Williamsonad805752012-06-11 05:27:07 +00002426
2427 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2428 if (ret >= 0)
2429 return ret > 0;
2430
Alex Williamson0a671192013-06-27 16:39:48 -06002431 /*
2432 * Conventional PCI and PCI-X devices never support ACS, either
2433 * effectively or actually. The shared bus topology implies that
2434 * any device on the bus can receive or snoop DMA.
2435 */
Alex Williamsonad805752012-06-11 05:27:07 +00002436 if (!pci_is_pcie(pdev))
2437 return false;
2438
Alex Williamson0a671192013-06-27 16:39:48 -06002439 switch (pci_pcie_type(pdev)) {
2440 /*
2441 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2442 * but since their primary inteface is PCI/X, we conservatively
2443 * handle them as we would a non-PCIe device.
2444 */
2445 case PCI_EXP_TYPE_PCIE_BRIDGE:
2446 /*
2447 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2448 * applicable... must never implement an ACS Extended Capability...".
2449 * This seems arbitrary, but we take a conservative interpretation
2450 * of this statement.
2451 */
2452 case PCI_EXP_TYPE_PCI_BRIDGE:
2453 case PCI_EXP_TYPE_RC_EC:
2454 return false;
2455 /*
2456 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2457 * implement ACS in order to indicate their peer-to-peer capabilities,
2458 * regardless of whether they are single- or multi-function devices.
2459 */
2460 case PCI_EXP_TYPE_DOWNSTREAM:
2461 case PCI_EXP_TYPE_ROOT_PORT:
2462 return pci_acs_flags_enabled(pdev, acs_flags);
2463 /*
2464 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2465 * implemented by the remaining PCIe types to indicate peer-to-peer
2466 * capabilities, but only when they are part of a multifunciton
2467 * device. The footnote for section 6.12 indicates the specific
2468 * PCIe types included here.
2469 */
2470 case PCI_EXP_TYPE_ENDPOINT:
2471 case PCI_EXP_TYPE_UPSTREAM:
2472 case PCI_EXP_TYPE_LEG_END:
2473 case PCI_EXP_TYPE_RC_END:
2474 if (!pdev->multifunction)
2475 break;
2476
Alex Williamson0a671192013-06-27 16:39:48 -06002477 return pci_acs_flags_enabled(pdev, acs_flags);
Alex Williamsonad805752012-06-11 05:27:07 +00002478 }
2479
Alex Williamson0a671192013-06-27 16:39:48 -06002480 /*
2481 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilties are applicable
2482 * to single function devices with the exception of downstream ports.
2483 */
Alex Williamsonad805752012-06-11 05:27:07 +00002484 return true;
2485}
2486
2487/**
2488 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2489 * @start: starting downstream device
2490 * @end: ending upstream device or NULL to search to the root bus
2491 * @acs_flags: required flags
2492 *
2493 * Walk up a device tree from start to end testing PCI ACS support. If
2494 * any step along the way does not support the required flags, return false.
2495 */
2496bool pci_acs_path_enabled(struct pci_dev *start,
2497 struct pci_dev *end, u16 acs_flags)
2498{
2499 struct pci_dev *pdev, *parent = start;
2500
2501 do {
2502 pdev = parent;
2503
2504 if (!pci_acs_enabled(pdev, acs_flags))
2505 return false;
2506
2507 if (pci_is_root_bus(pdev->bus))
2508 return (end == NULL);
2509
2510 parent = pdev->bus->self;
2511 } while (pdev != end);
2512
2513 return true;
2514}
2515
2516/**
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07002517 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2518 * @dev: the PCI device
Wang Sheng-Huibb5c2de2013-05-28 11:17:41 +08002519 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07002520 *
2521 * Perform INTx swizzling for a device behind one level of bridge. This is
2522 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
Matthew Wilcox46b952a2009-07-01 14:24:30 -07002523 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2524 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2525 * the PCI Express Base Specification, Revision 2.1)
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07002526 */
John Crispin3df425f2012-04-12 17:33:07 +02002527u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07002528{
Matthew Wilcox46b952a2009-07-01 14:24:30 -07002529 int slot;
2530
2531 if (pci_ari_enabled(dev->bus))
2532 slot = 0;
2533 else
2534 slot = PCI_SLOT(dev->devfn);
2535
2536 return (((pin - 1) + slot) % 4) + 1;
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07002537}
2538
Linus Torvalds1da177e2005-04-16 15:20:36 -07002539int
2540pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2541{
2542 u8 pin;
2543
Kristen Accardi514d2072005-11-02 16:24:39 -08002544 pin = dev->pin;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002545 if (!pin)
2546 return -1;
Bjorn Helgaas878f2e52008-12-09 16:11:46 -07002547
Kenji Kaneshige8784fd42009-05-26 16:07:33 +09002548 while (!pci_is_root_bus(dev->bus)) {
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07002549 pin = pci_swizzle_interrupt_pin(dev, pin);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002550 dev = dev->bus->self;
2551 }
2552 *bridge = dev;
2553 return pin;
2554}
2555
2556/**
Bjorn Helgaas68feac82008-12-16 21:36:55 -07002557 * pci_common_swizzle - swizzle INTx all the way to root bridge
2558 * @dev: the PCI device
2559 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2560 *
2561 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2562 * bridges all the way up to a PCI root bus.
2563 */
2564u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2565{
2566 u8 pin = *pinp;
2567
Kenji Kaneshige1eb39482009-05-26 16:08:36 +09002568 while (!pci_is_root_bus(dev->bus)) {
Bjorn Helgaas68feac82008-12-16 21:36:55 -07002569 pin = pci_swizzle_interrupt_pin(dev, pin);
2570 dev = dev->bus->self;
2571 }
2572 *pinp = pin;
2573 return PCI_SLOT(dev->devfn);
2574}
2575
2576/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07002577 * pci_release_region - Release a PCI bar
2578 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2579 * @bar: BAR to release
2580 *
2581 * Releases the PCI I/O and memory resources previously reserved by a
2582 * successful call to pci_request_region. Call this function only
2583 * after all use of the PCI regions has ceased.
2584 */
2585void pci_release_region(struct pci_dev *pdev, int bar)
2586{
Tejun Heo9ac78492007-01-20 16:00:26 +09002587 struct pci_devres *dr;
2588
Linus Torvalds1da177e2005-04-16 15:20:36 -07002589 if (pci_resource_len(pdev, bar) == 0)
2590 return;
2591 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2592 release_region(pci_resource_start(pdev, bar),
2593 pci_resource_len(pdev, bar));
2594 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2595 release_mem_region(pci_resource_start(pdev, bar),
2596 pci_resource_len(pdev, bar));
Tejun Heo9ac78492007-01-20 16:00:26 +09002597
2598 dr = find_pci_dr(pdev);
2599 if (dr)
2600 dr->region_mask &= ~(1 << bar);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002601}
2602
2603/**
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08002604 * __pci_request_region - Reserved PCI I/O and memory resource
Linus Torvalds1da177e2005-04-16 15:20:36 -07002605 * @pdev: PCI device whose resources are to be reserved
2606 * @bar: BAR to be reserved
2607 * @res_name: Name to be associated with resource.
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08002608 * @exclusive: whether the region access is exclusive or not
Linus Torvalds1da177e2005-04-16 15:20:36 -07002609 *
2610 * Mark the PCI region associated with PCI device @pdev BR @bar as
2611 * being reserved by owner @res_name. Do not access any
2612 * address inside the PCI regions unless this call returns
2613 * successfully.
2614 *
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08002615 * If @exclusive is set, then the region is marked so that userspace
2616 * is explicitly not allowed to map the resource via /dev/mem or
2617 * sysfs MMIO access.
2618 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07002619 * Returns 0 on success, or %EBUSY on error. A warning
2620 * message is also printed on failure.
2621 */
Arjan van de Vene8de1482008-10-22 19:55:31 -07002622static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2623 int exclusive)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002624{
Tejun Heo9ac78492007-01-20 16:00:26 +09002625 struct pci_devres *dr;
2626
Linus Torvalds1da177e2005-04-16 15:20:36 -07002627 if (pci_resource_len(pdev, bar) == 0)
2628 return 0;
2629
2630 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2631 if (!request_region(pci_resource_start(pdev, bar),
2632 pci_resource_len(pdev, bar), res_name))
2633 goto err_out;
2634 }
2635 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
Arjan van de Vene8de1482008-10-22 19:55:31 -07002636 if (!__request_mem_region(pci_resource_start(pdev, bar),
2637 pci_resource_len(pdev, bar), res_name,
2638 exclusive))
Linus Torvalds1da177e2005-04-16 15:20:36 -07002639 goto err_out;
2640 }
Tejun Heo9ac78492007-01-20 16:00:26 +09002641
2642 dr = find_pci_dr(pdev);
2643 if (dr)
2644 dr->region_mask |= 1 << bar;
2645
Linus Torvalds1da177e2005-04-16 15:20:36 -07002646 return 0;
2647
2648err_out:
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -06002649 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
Benjamin Herrenschmidt096e6f62008-10-20 15:07:37 +11002650 &pdev->resource[bar]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002651 return -EBUSY;
2652}
2653
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09002654/**
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08002655 * pci_request_region - Reserve PCI I/O and memory resource
Arjan van de Vene8de1482008-10-22 19:55:31 -07002656 * @pdev: PCI device whose resources are to be reserved
2657 * @bar: BAR to be reserved
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08002658 * @res_name: Name to be associated with resource
Arjan van de Vene8de1482008-10-22 19:55:31 -07002659 *
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08002660 * Mark the PCI region associated with PCI device @pdev BAR @bar as
Arjan van de Vene8de1482008-10-22 19:55:31 -07002661 * being reserved by owner @res_name. Do not access any
2662 * address inside the PCI regions unless this call returns
2663 * successfully.
2664 *
2665 * Returns 0 on success, or %EBUSY on error. A warning
2666 * message is also printed on failure.
2667 */
2668int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2669{
2670 return __pci_request_region(pdev, bar, res_name, 0);
2671}
2672
2673/**
2674 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2675 * @pdev: PCI device whose resources are to be reserved
2676 * @bar: BAR to be reserved
2677 * @res_name: Name to be associated with resource.
2678 *
2679 * Mark the PCI region associated with PCI device @pdev BR @bar as
2680 * being reserved by owner @res_name. Do not access any
2681 * address inside the PCI regions unless this call returns
2682 * successfully.
2683 *
2684 * Returns 0 on success, or %EBUSY on error. A warning
2685 * message is also printed on failure.
2686 *
2687 * The key difference that _exclusive makes it that userspace is
2688 * explicitly not allowed to map the resource via /dev/mem or
2689 * sysfs.
2690 */
2691int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2692{
2693 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2694}
2695/**
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09002696 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2697 * @pdev: PCI device whose resources were previously reserved
2698 * @bars: Bitmask of BARs to be released
2699 *
2700 * Release selected PCI I/O and memory resources previously reserved.
2701 * Call this function only after all use of the PCI regions has ceased.
2702 */
2703void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2704{
2705 int i;
2706
2707 for (i = 0; i < 6; i++)
2708 if (bars & (1 << i))
2709 pci_release_region(pdev, i);
2710}
2711
Bjorn Helgaas9738abe2013-04-12 11:20:03 -06002712static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
Arjan van de Vene8de1482008-10-22 19:55:31 -07002713 const char *res_name, int excl)
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09002714{
2715 int i;
2716
2717 for (i = 0; i < 6; i++)
2718 if (bars & (1 << i))
Arjan van de Vene8de1482008-10-22 19:55:31 -07002719 if (__pci_request_region(pdev, i, res_name, excl))
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09002720 goto err_out;
2721 return 0;
2722
2723err_out:
2724 while(--i >= 0)
2725 if (bars & (1 << i))
2726 pci_release_region(pdev, i);
2727
2728 return -EBUSY;
2729}
Linus Torvalds1da177e2005-04-16 15:20:36 -07002730
Arjan van de Vene8de1482008-10-22 19:55:31 -07002731
2732/**
2733 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2734 * @pdev: PCI device whose resources are to be reserved
2735 * @bars: Bitmask of BARs to be requested
2736 * @res_name: Name to be associated with resource
2737 */
2738int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2739 const char *res_name)
2740{
2741 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2742}
2743
2744int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2745 int bars, const char *res_name)
2746{
2747 return __pci_request_selected_regions(pdev, bars, res_name,
2748 IORESOURCE_EXCLUSIVE);
2749}
2750
Linus Torvalds1da177e2005-04-16 15:20:36 -07002751/**
2752 * pci_release_regions - Release reserved PCI I/O and memory resources
2753 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2754 *
2755 * Releases all PCI I/O and memory resources previously reserved by a
2756 * successful call to pci_request_regions. Call this function only
2757 * after all use of the PCI regions has ceased.
2758 */
2759
2760void pci_release_regions(struct pci_dev *pdev)
2761{
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09002762 pci_release_selected_regions(pdev, (1 << 6) - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002763}
2764
2765/**
2766 * pci_request_regions - Reserved PCI I/O and memory resources
2767 * @pdev: PCI device whose resources are to be reserved
2768 * @res_name: Name to be associated with resource.
2769 *
2770 * Mark all PCI regions associated with PCI device @pdev as
2771 * being reserved by owner @res_name. Do not access any
2772 * address inside the PCI regions unless this call returns
2773 * successfully.
2774 *
2775 * Returns 0 on success, or %EBUSY on error. A warning
2776 * message is also printed on failure.
2777 */
Jeff Garzik3c990e92006-03-04 21:52:42 -05002778int pci_request_regions(struct pci_dev *pdev, const char *res_name)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002779{
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09002780 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002781}
2782
2783/**
Arjan van de Vene8de1482008-10-22 19:55:31 -07002784 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2785 * @pdev: PCI device whose resources are to be reserved
2786 * @res_name: Name to be associated with resource.
2787 *
2788 * Mark all PCI regions associated with PCI device @pdev as
2789 * being reserved by owner @res_name. Do not access any
2790 * address inside the PCI regions unless this call returns
2791 * successfully.
2792 *
2793 * pci_request_regions_exclusive() will mark the region so that
2794 * /dev/mem and the sysfs MMIO access will not be allowed.
2795 *
2796 * Returns 0 on success, or %EBUSY on error. A warning
2797 * message is also printed on failure.
2798 */
2799int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2800{
2801 return pci_request_selected_regions_exclusive(pdev,
2802 ((1 << 6) - 1), res_name);
2803}
2804
Ben Hutchings6a479072008-12-23 03:08:29 +00002805static void __pci_set_master(struct pci_dev *dev, bool enable)
2806{
2807 u16 old_cmd, cmd;
2808
2809 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2810 if (enable)
2811 cmd = old_cmd | PCI_COMMAND_MASTER;
2812 else
2813 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2814 if (cmd != old_cmd) {
2815 dev_dbg(&dev->dev, "%s bus mastering\n",
2816 enable ? "enabling" : "disabling");
2817 pci_write_config_word(dev, PCI_COMMAND, cmd);
2818 }
2819 dev->is_busmaster = enable;
2820}
Arjan van de Vene8de1482008-10-22 19:55:31 -07002821
2822/**
Myron Stowe2b6f2c32012-06-25 21:30:57 -06002823 * pcibios_setup - process "pci=" kernel boot arguments
2824 * @str: string used to pass in "pci=" kernel boot arguments
2825 *
2826 * Process kernel boot arguments. This is the default implementation.
2827 * Architecture specific implementations can override this as necessary.
2828 */
2829char * __weak __init pcibios_setup(char *str)
2830{
2831 return str;
2832}
2833
2834/**
Myron Stowe96c55902011-10-28 15:48:38 -06002835 * pcibios_set_master - enable PCI bus-mastering for device dev
2836 * @dev: the PCI device to enable
2837 *
2838 * Enables PCI bus-mastering for the device. This is the default
2839 * implementation. Architecture specific implementations can override
2840 * this if necessary.
2841 */
2842void __weak pcibios_set_master(struct pci_dev *dev)
2843{
2844 u8 lat;
2845
Myron Stowef6766782011-10-28 15:49:20 -06002846 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2847 if (pci_is_pcie(dev))
2848 return;
2849
Myron Stowe96c55902011-10-28 15:48:38 -06002850 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
2851 if (lat < 16)
2852 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
2853 else if (lat > pcibios_max_latency)
2854 lat = pcibios_max_latency;
2855 else
2856 return;
2857 dev_printk(KERN_DEBUG, &dev->dev, "setting latency timer to %d\n", lat);
2858 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
2859}
2860
2861/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07002862 * pci_set_master - enables bus-mastering for device dev
2863 * @dev: the PCI device to enable
2864 *
2865 * Enables bus-mastering on the device and calls pcibios_set_master()
2866 * to do the needed arch specific settings.
2867 */
Ben Hutchings6a479072008-12-23 03:08:29 +00002868void pci_set_master(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002869{
Ben Hutchings6a479072008-12-23 03:08:29 +00002870 __pci_set_master(dev, true);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002871 pcibios_set_master(dev);
2872}
2873
Ben Hutchings6a479072008-12-23 03:08:29 +00002874/**
2875 * pci_clear_master - disables bus-mastering for device dev
2876 * @dev: the PCI device to disable
2877 */
2878void pci_clear_master(struct pci_dev *dev)
2879{
2880 __pci_set_master(dev, false);
2881}
2882
Linus Torvalds1da177e2005-04-16 15:20:36 -07002883/**
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06002884 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2885 * @dev: the PCI device for which MWI is to be enabled
Linus Torvalds1da177e2005-04-16 15:20:36 -07002886 *
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06002887 * Helper function for pci_set_mwi.
2888 * Originally copied from drivers/net/acenic.c.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002889 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2890 *
2891 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2892 */
Tejun Heo15ea76d2009-09-22 17:34:48 +09002893int pci_set_cacheline_size(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002894{
2895 u8 cacheline_size;
2896
2897 if (!pci_cache_line_size)
Tejun Heo15ea76d2009-09-22 17:34:48 +09002898 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002899
2900 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2901 equal to or multiple of the right value. */
2902 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2903 if (cacheline_size >= pci_cache_line_size &&
2904 (cacheline_size % pci_cache_line_size) == 0)
2905 return 0;
2906
2907 /* Write the correct value. */
2908 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2909 /* Read it back. */
2910 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2911 if (cacheline_size == pci_cache_line_size)
2912 return 0;
2913
Bjorn Helgaas80ccba12008-06-13 10:52:11 -06002914 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2915 "supported\n", pci_cache_line_size << 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002916
2917 return -EINVAL;
2918}
Tejun Heo15ea76d2009-09-22 17:34:48 +09002919EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2920
2921#ifdef PCI_DISABLE_MWI
2922int pci_set_mwi(struct pci_dev *dev)
2923{
2924 return 0;
2925}
2926
2927int pci_try_set_mwi(struct pci_dev *dev)
2928{
2929 return 0;
2930}
2931
2932void pci_clear_mwi(struct pci_dev *dev)
2933{
2934}
2935
2936#else
Linus Torvalds1da177e2005-04-16 15:20:36 -07002937
2938/**
2939 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2940 * @dev: the PCI device for which MWI is enabled
2941 *
Randy Dunlap694625c2007-07-09 11:55:54 -07002942 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002943 *
2944 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2945 */
2946int
2947pci_set_mwi(struct pci_dev *dev)
2948{
2949 int rc;
2950 u16 cmd;
2951
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06002952 rc = pci_set_cacheline_size(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002953 if (rc)
2954 return rc;
2955
2956 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2957 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -06002958 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002959 cmd |= PCI_COMMAND_INVALIDATE;
2960 pci_write_config_word(dev, PCI_COMMAND, cmd);
2961 }
2962
2963 return 0;
2964}
2965
2966/**
Randy Dunlap694625c2007-07-09 11:55:54 -07002967 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2968 * @dev: the PCI device for which MWI is enabled
2969 *
2970 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2971 * Callers are not required to check the return value.
2972 *
2973 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2974 */
2975int pci_try_set_mwi(struct pci_dev *dev)
2976{
2977 int rc = pci_set_mwi(dev);
2978 return rc;
2979}
2980
2981/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07002982 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2983 * @dev: the PCI device to disable
2984 *
2985 * Disables PCI Memory-Write-Invalidate transaction on the device
2986 */
2987void
2988pci_clear_mwi(struct pci_dev *dev)
2989{
2990 u16 cmd;
2991
2992 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2993 if (cmd & PCI_COMMAND_INVALIDATE) {
2994 cmd &= ~PCI_COMMAND_INVALIDATE;
2995 pci_write_config_word(dev, PCI_COMMAND, cmd);
2996 }
2997}
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06002998#endif /* ! PCI_DISABLE_MWI */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002999
Brett M Russa04ce0f2005-08-15 15:23:41 -04003000/**
3001 * pci_intx - enables/disables PCI INTx for device dev
Randy Dunlap8f7020d2005-10-23 11:57:38 -07003002 * @pdev: the PCI device to operate on
3003 * @enable: boolean: whether to enable or disable PCI INTx
Brett M Russa04ce0f2005-08-15 15:23:41 -04003004 *
3005 * Enables/disables PCI INTx for device dev
3006 */
3007void
3008pci_intx(struct pci_dev *pdev, int enable)
3009{
3010 u16 pci_command, new;
3011
3012 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
3013
3014 if (enable) {
3015 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
3016 } else {
3017 new = pci_command | PCI_COMMAND_INTX_DISABLE;
3018 }
3019
3020 if (new != pci_command) {
Tejun Heo9ac78492007-01-20 16:00:26 +09003021 struct pci_devres *dr;
3022
Brett M Russ2fd9d742005-09-09 10:02:22 -07003023 pci_write_config_word(pdev, PCI_COMMAND, new);
Tejun Heo9ac78492007-01-20 16:00:26 +09003024
3025 dr = find_pci_dr(pdev);
3026 if (dr && !dr->restore_intx) {
3027 dr->restore_intx = 1;
3028 dr->orig_intx = !enable;
3029 }
Brett M Russa04ce0f2005-08-15 15:23:41 -04003030 }
3031}
3032
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08003033/**
Jan Kiszkaa2e27782011-11-04 09:46:00 +01003034 * pci_intx_mask_supported - probe for INTx masking support
Randy Dunlap6e9292c2012-01-21 11:02:35 -08003035 * @dev: the PCI device to operate on
Jan Kiszkaa2e27782011-11-04 09:46:00 +01003036 *
3037 * Check if the device dev support INTx masking via the config space
3038 * command word.
3039 */
3040bool pci_intx_mask_supported(struct pci_dev *dev)
3041{
3042 bool mask_supported = false;
3043 u16 orig, new;
3044
Bjorn Helgaasfbebb9f2012-06-16 14:40:22 -06003045 if (dev->broken_intx_masking)
3046 return false;
3047
Jan Kiszkaa2e27782011-11-04 09:46:00 +01003048 pci_cfg_access_lock(dev);
3049
3050 pci_read_config_word(dev, PCI_COMMAND, &orig);
3051 pci_write_config_word(dev, PCI_COMMAND,
3052 orig ^ PCI_COMMAND_INTX_DISABLE);
3053 pci_read_config_word(dev, PCI_COMMAND, &new);
3054
3055 /*
3056 * There's no way to protect against hardware bugs or detect them
3057 * reliably, but as long as we know what the value should be, let's
3058 * go ahead and check it.
3059 */
3060 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
3061 dev_err(&dev->dev, "Command register changed from "
3062 "0x%x to 0x%x: driver or hardware bug?\n", orig, new);
3063 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
3064 mask_supported = true;
3065 pci_write_config_word(dev, PCI_COMMAND, orig);
3066 }
3067
3068 pci_cfg_access_unlock(dev);
3069 return mask_supported;
3070}
3071EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
3072
3073static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3074{
3075 struct pci_bus *bus = dev->bus;
3076 bool mask_updated = true;
3077 u32 cmd_status_dword;
3078 u16 origcmd, newcmd;
3079 unsigned long flags;
3080 bool irq_pending;
3081
3082 /*
3083 * We do a single dword read to retrieve both command and status.
3084 * Document assumptions that make this possible.
3085 */
3086 BUILD_BUG_ON(PCI_COMMAND % 4);
3087 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3088
3089 raw_spin_lock_irqsave(&pci_lock, flags);
3090
3091 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3092
3093 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3094
3095 /*
3096 * Check interrupt status register to see whether our device
3097 * triggered the interrupt (when masking) or the next IRQ is
3098 * already pending (when unmasking).
3099 */
3100 if (mask != irq_pending) {
3101 mask_updated = false;
3102 goto done;
3103 }
3104
3105 origcmd = cmd_status_dword;
3106 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3107 if (mask)
3108 newcmd |= PCI_COMMAND_INTX_DISABLE;
3109 if (newcmd != origcmd)
3110 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3111
3112done:
3113 raw_spin_unlock_irqrestore(&pci_lock, flags);
3114
3115 return mask_updated;
3116}
3117
3118/**
3119 * pci_check_and_mask_intx - mask INTx on pending interrupt
Randy Dunlap6e9292c2012-01-21 11:02:35 -08003120 * @dev: the PCI device to operate on
Jan Kiszkaa2e27782011-11-04 09:46:00 +01003121 *
3122 * Check if the device dev has its INTx line asserted, mask it and
3123 * return true in that case. False is returned if not interrupt was
3124 * pending.
3125 */
3126bool pci_check_and_mask_intx(struct pci_dev *dev)
3127{
3128 return pci_check_and_set_intx_mask(dev, true);
3129}
3130EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3131
3132/**
3133 * pci_check_and_mask_intx - unmask INTx of no interrupt is pending
Randy Dunlap6e9292c2012-01-21 11:02:35 -08003134 * @dev: the PCI device to operate on
Jan Kiszkaa2e27782011-11-04 09:46:00 +01003135 *
3136 * Check if the device dev has its INTx line asserted, unmask it if not
3137 * and return true. False is returned and the mask remains active if
3138 * there was still an interrupt pending.
3139 */
3140bool pci_check_and_unmask_intx(struct pci_dev *dev)
3141{
3142 return pci_check_and_set_intx_mask(dev, false);
3143}
3144EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3145
3146/**
Bjorn Helgaasda27f4b2013-08-22 14:45:21 -06003147 * pci_msi_off - disables any MSI or MSI-X capabilities
Randy Dunlap8d7d86e2007-03-16 19:55:52 -07003148 * @dev: the PCI device to operate on
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08003149 *
Bjorn Helgaasda27f4b2013-08-22 14:45:21 -06003150 * If you want to use MSI, see pci_enable_msi() and friends.
3151 * This is a lower-level primitive that allows us to disable
3152 * MSI operation at the device level.
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08003153 */
3154void pci_msi_off(struct pci_dev *dev)
3155{
3156 int pos;
3157 u16 control;
3158
Bjorn Helgaasda27f4b2013-08-22 14:45:21 -06003159 /*
3160 * This looks like it could go in msi.c, but we need it even when
3161 * CONFIG_PCI_MSI=n. For the same reason, we can't use
3162 * dev->msi_cap or dev->msix_cap here.
3163 */
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08003164 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
3165 if (pos) {
3166 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
3167 control &= ~PCI_MSI_FLAGS_ENABLE;
3168 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
3169 }
3170 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
3171 if (pos) {
3172 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
3173 control &= ~PCI_MSIX_FLAGS_ENABLE;
3174 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
3175 }
3176}
Michael S. Tsirkinb03214d2010-06-23 22:49:06 -06003177EXPORT_SYMBOL_GPL(pci_msi_off);
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08003178
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08003179int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
3180{
3181 return dma_set_max_seg_size(&dev->dev, size);
3182}
3183EXPORT_SYMBOL(pci_set_dma_max_seg_size);
FUJITA Tomonori4d57cdf2008-02-04 22:27:55 -08003184
FUJITA Tomonori59fc67d2008-02-04 22:28:14 -08003185int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
3186{
3187 return dma_set_seg_boundary(&dev->dev, mask);
3188}
3189EXPORT_SYMBOL(pci_set_dma_seg_boundary);
FUJITA Tomonori59fc67d2008-02-04 22:28:14 -08003190
Casey Leedom3775a202013-08-06 15:48:36 +05303191/**
3192 * pci_wait_for_pending_transaction - waits for pending transaction
3193 * @dev: the PCI device to operate on
3194 *
3195 * Return 0 if transaction is pending 1 otherwise.
3196 */
3197int pci_wait_for_pending_transaction(struct pci_dev *dev)
Sheng Yang8dd7f802008-10-21 17:38:25 +08003198{
Yu Zhao8c1c6992009-06-13 15:52:13 +08003199 int i;
Jiang Liu59875ae2012-07-24 17:20:06 +08003200 u16 status;
Sheng Yang8dd7f802008-10-21 17:38:25 +08003201
Sheng Yang8dd7f802008-10-21 17:38:25 +08003202 /* Wait for Transaction Pending bit clean */
Yu Zhao8c1c6992009-06-13 15:52:13 +08003203 for (i = 0; i < 4; i++) {
3204 if (i)
3205 msleep((1 << (i - 1)) * 100);
Sheng Yang5fe5db02009-02-09 14:53:47 +08003206
Jiang Liu59875ae2012-07-24 17:20:06 +08003207 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
Yu Zhao8c1c6992009-06-13 15:52:13 +08003208 if (!(status & PCI_EXP_DEVSTA_TRPND))
Casey Leedom3775a202013-08-06 15:48:36 +05303209 return 1;
Yu Zhao8c1c6992009-06-13 15:52:13 +08003210 }
Sheng Yang8dd7f802008-10-21 17:38:25 +08003211
Casey Leedom3775a202013-08-06 15:48:36 +05303212 return 0;
3213}
3214EXPORT_SYMBOL(pci_wait_for_pending_transaction);
Sheng Yang5fe5db02009-02-09 14:53:47 +08003215
Casey Leedom3775a202013-08-06 15:48:36 +05303216static int pcie_flr(struct pci_dev *dev, int probe)
3217{
3218 u32 cap;
3219
3220 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3221 if (!(cap & PCI_EXP_DEVCAP_FLR))
3222 return -ENOTTY;
3223
3224 if (probe)
3225 return 0;
3226
3227 if (!pci_wait_for_pending_transaction(dev))
3228 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3229
Jiang Liu59875ae2012-07-24 17:20:06 +08003230 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
Shmulik Ravid04b55c42009-12-03 22:27:51 +02003231
Yu Zhao8c1c6992009-06-13 15:52:13 +08003232 msleep(100);
Sheng Yang8dd7f802008-10-21 17:38:25 +08003233
Sheng Yang8dd7f802008-10-21 17:38:25 +08003234 return 0;
3235}
Sheng Yangd91cdc72008-11-11 17:17:47 +08003236
Yu Zhao8c1c6992009-06-13 15:52:13 +08003237static int pci_af_flr(struct pci_dev *dev, int probe)
Sheng Yang1ca88792008-11-11 17:17:48 +08003238{
Yu Zhao8c1c6992009-06-13 15:52:13 +08003239 int i;
3240 int pos;
Sheng Yang1ca88792008-11-11 17:17:48 +08003241 u8 cap;
Yu Zhao8c1c6992009-06-13 15:52:13 +08003242 u8 status;
Sheng Yang1ca88792008-11-11 17:17:48 +08003243
Yu Zhao8c1c6992009-06-13 15:52:13 +08003244 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3245 if (!pos)
Sheng Yang1ca88792008-11-11 17:17:48 +08003246 return -ENOTTY;
Yu Zhao8c1c6992009-06-13 15:52:13 +08003247
3248 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
Sheng Yang1ca88792008-11-11 17:17:48 +08003249 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3250 return -ENOTTY;
3251
3252 if (probe)
3253 return 0;
3254
Sheng Yang1ca88792008-11-11 17:17:48 +08003255 /* Wait for Transaction Pending bit clean */
Yu Zhao8c1c6992009-06-13 15:52:13 +08003256 for (i = 0; i < 4; i++) {
3257 if (i)
3258 msleep((1 << (i - 1)) * 100);
Sheng Yang5fe5db02009-02-09 14:53:47 +08003259
Yu Zhao8c1c6992009-06-13 15:52:13 +08003260 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
3261 if (!(status & PCI_AF_STATUS_TP))
3262 goto clear;
3263 }
3264
3265 dev_err(&dev->dev, "transaction is not cleared; "
3266 "proceeding with reset anyway\n");
3267
3268clear:
3269 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
Sheng Yang1ca88792008-11-11 17:17:48 +08003270 msleep(100);
Sheng Yang5fe5db02009-02-09 14:53:47 +08003271
Sheng Yang1ca88792008-11-11 17:17:48 +08003272 return 0;
3273}
3274
Rafael J. Wysocki83d74e02011-03-05 21:48:44 +01003275/**
3276 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3277 * @dev: Device to reset.
3278 * @probe: If set, only check if the device can be reset this way.
3279 *
3280 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3281 * unset, it will be reinitialized internally when going from PCI_D3hot to
3282 * PCI_D0. If that's the case and the device is not in a low-power state
3283 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3284 *
3285 * NOTE: This causes the caller to sleep for twice the device power transition
3286 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3287 * by devault (i.e. unless the @dev's d3_delay field has a different value).
3288 * Moreover, only devices in D0 can be reset by this function.
3289 */
Yu Zhaof85876b2009-06-13 15:52:14 +08003290static int pci_pm_reset(struct pci_dev *dev, int probe)
Sheng Yangd91cdc72008-11-11 17:17:47 +08003291{
Yu Zhaof85876b2009-06-13 15:52:14 +08003292 u16 csr;
Sheng Yangd91cdc72008-11-11 17:17:47 +08003293
Yu Zhaof85876b2009-06-13 15:52:14 +08003294 if (!dev->pm_cap)
3295 return -ENOTTY;
Sheng Yangd91cdc72008-11-11 17:17:47 +08003296
Yu Zhaof85876b2009-06-13 15:52:14 +08003297 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3298 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3299 return -ENOTTY;
Sheng Yang1ca88792008-11-11 17:17:48 +08003300
Yu Zhaof85876b2009-06-13 15:52:14 +08003301 if (probe)
3302 return 0;
3303
3304 if (dev->current_state != PCI_D0)
3305 return -EINVAL;
3306
3307 csr &= ~PCI_PM_CTRL_STATE_MASK;
3308 csr |= PCI_D3hot;
3309 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
Rafael J. Wysocki1ae861e2009-12-31 12:15:54 +01003310 pci_dev_d3_sleep(dev);
Yu Zhaof85876b2009-06-13 15:52:14 +08003311
3312 csr &= ~PCI_PM_CTRL_STATE_MASK;
3313 csr |= PCI_D0;
3314 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
Rafael J. Wysocki1ae861e2009-12-31 12:15:54 +01003315 pci_dev_d3_sleep(dev);
Yu Zhaof85876b2009-06-13 15:52:14 +08003316
3317 return 0;
3318}
3319
Alex Williamson64e86742013-08-08 14:09:24 -06003320/**
3321 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3322 * @dev: Bridge device
3323 *
3324 * Use the bridge control register to assert reset on the secondary bus.
3325 * Devices on the secondary bus are left in power-on state.
3326 */
3327void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
Yu Zhaoc12ff1d2009-06-13 15:52:15 +08003328{
3329 u16 ctrl;
Alex Williamson64e86742013-08-08 14:09:24 -06003330
3331 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3332 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3333 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
Alex Williamsonde0c5482013-08-08 14:10:13 -06003334 /*
3335 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3336 * this to 2ms to ensure that we meet the minium requirement.
3337 */
3338 msleep(2);
Alex Williamson64e86742013-08-08 14:09:24 -06003339
3340 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3341 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
Alex Williamsonde0c5482013-08-08 14:10:13 -06003342
3343 /*
3344 * Trhfa for conventional PCI is 2^25 clock cycles.
3345 * Assuming a minimum 33MHz clock this results in a 1s
3346 * delay before we can consider subordinate devices to
3347 * be re-initialized. PCIe has some ways to shorten this,
3348 * but we don't make use of them yet.
3349 */
3350 ssleep(1);
Alex Williamson64e86742013-08-08 14:09:24 -06003351}
3352EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3353
3354static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3355{
Yu Zhaoc12ff1d2009-06-13 15:52:15 +08003356 struct pci_dev *pdev;
3357
Yu Zhao654b75e2009-06-26 14:04:46 +08003358 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
Yu Zhaoc12ff1d2009-06-13 15:52:15 +08003359 return -ENOTTY;
3360
3361 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3362 if (pdev != dev)
3363 return -ENOTTY;
3364
3365 if (probe)
3366 return 0;
3367
Alex Williamson64e86742013-08-08 14:09:24 -06003368 pci_reset_bridge_secondary_bus(dev->bus->self);
Yu Zhaoc12ff1d2009-06-13 15:52:15 +08003369
3370 return 0;
3371}
3372
Alex Williamson608c3882013-08-08 14:09:43 -06003373static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
3374{
3375 int rc = -ENOTTY;
3376
3377 if (!hotplug || !try_module_get(hotplug->ops->owner))
3378 return rc;
3379
3380 if (hotplug->ops->reset_slot)
3381 rc = hotplug->ops->reset_slot(hotplug, probe);
3382
3383 module_put(hotplug->ops->owner);
3384
3385 return rc;
3386}
3387
3388static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
3389{
3390 struct pci_dev *pdev;
3391
3392 if (dev->subordinate || !dev->slot)
3393 return -ENOTTY;
3394
3395 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3396 if (pdev != dev && pdev->slot == dev->slot)
3397 return -ENOTTY;
3398
3399 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
3400}
3401
Konrad Rzeszutek Wilk977f8572012-04-24 13:15:18 -06003402static int __pci_dev_reset(struct pci_dev *dev, int probe)
Sheng Yang8dd7f802008-10-21 17:38:25 +08003403{
Yu Zhao8c1c6992009-06-13 15:52:13 +08003404 int rc;
Sheng Yang8dd7f802008-10-21 17:38:25 +08003405
Yu Zhao8c1c6992009-06-13 15:52:13 +08003406 might_sleep();
Sheng Yang8dd7f802008-10-21 17:38:25 +08003407
Dexuan Cuib9c3b262009-12-07 13:03:21 +08003408 rc = pci_dev_specific_reset(dev, probe);
3409 if (rc != -ENOTTY)
3410 goto done;
3411
Yu Zhao8c1c6992009-06-13 15:52:13 +08003412 rc = pcie_flr(dev, probe);
3413 if (rc != -ENOTTY)
3414 goto done;
3415
3416 rc = pci_af_flr(dev, probe);
Yu Zhaof85876b2009-06-13 15:52:14 +08003417 if (rc != -ENOTTY)
3418 goto done;
3419
3420 rc = pci_pm_reset(dev, probe);
Yu Zhaoc12ff1d2009-06-13 15:52:15 +08003421 if (rc != -ENOTTY)
3422 goto done;
3423
Alex Williamson608c3882013-08-08 14:09:43 -06003424 rc = pci_dev_reset_slot_function(dev, probe);
3425 if (rc != -ENOTTY)
3426 goto done;
3427
Yu Zhaoc12ff1d2009-06-13 15:52:15 +08003428 rc = pci_parent_bus_reset(dev, probe);
Yu Zhao8c1c6992009-06-13 15:52:13 +08003429done:
Konrad Rzeszutek Wilk977f8572012-04-24 13:15:18 -06003430 return rc;
3431}
3432
Alex Williamson77cb9852013-08-08 14:09:49 -06003433static void pci_dev_lock(struct pci_dev *dev)
3434{
3435 pci_cfg_access_lock(dev);
3436 /* block PM suspend, driver probe, etc. */
3437 device_lock(&dev->dev);
3438}
3439
3440static void pci_dev_unlock(struct pci_dev *dev)
3441{
3442 device_unlock(&dev->dev);
3443 pci_cfg_access_unlock(dev);
3444}
3445
3446static void pci_dev_save_and_disable(struct pci_dev *dev)
3447{
Alex Williamsona6cbaad2013-08-08 14:10:02 -06003448 /*
3449 * Wake-up device prior to save. PM registers default to D0 after
3450 * reset and a simple register restore doesn't reliably return
3451 * to a non-D0 state anyway.
3452 */
3453 pci_set_power_state(dev, PCI_D0);
3454
Alex Williamson77cb9852013-08-08 14:09:49 -06003455 pci_save_state(dev);
3456 /*
3457 * Disable the device by clearing the Command register, except for
3458 * INTx-disable which is set. This not only disables MMIO and I/O port
3459 * BARs, but also prevents the device from being Bus Master, preventing
3460 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
3461 * compliant devices, INTx-disable prevents legacy interrupts.
3462 */
3463 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3464}
3465
3466static void pci_dev_restore(struct pci_dev *dev)
3467{
3468 pci_restore_state(dev);
3469}
3470
Konrad Rzeszutek Wilk977f8572012-04-24 13:15:18 -06003471static int pci_dev_reset(struct pci_dev *dev, int probe)
3472{
3473 int rc;
3474
Alex Williamson77cb9852013-08-08 14:09:49 -06003475 if (!probe)
3476 pci_dev_lock(dev);
Konrad Rzeszutek Wilk977f8572012-04-24 13:15:18 -06003477
3478 rc = __pci_dev_reset(dev, probe);
3479
Alex Williamson77cb9852013-08-08 14:09:49 -06003480 if (!probe)
3481 pci_dev_unlock(dev);
3482
Yu Zhao8c1c6992009-06-13 15:52:13 +08003483 return rc;
Sheng Yang8dd7f802008-10-21 17:38:25 +08003484}
Sheng Yang8dd7f802008-10-21 17:38:25 +08003485/**
Yu Zhao8c1c6992009-06-13 15:52:13 +08003486 * __pci_reset_function - reset a PCI device function
3487 * @dev: PCI device to reset
Sheng Yang8dd7f802008-10-21 17:38:25 +08003488 *
3489 * Some devices allow an individual function to be reset without affecting
3490 * other functions in the same device. The PCI device must be responsive
3491 * to PCI config space in order to use this function.
3492 *
3493 * The device function is presumed to be unused when this function is called.
3494 * Resetting the device will make the contents of PCI configuration space
3495 * random, so any caller of this must be prepared to reinitialise the
3496 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3497 * etc.
3498 *
Yu Zhao8c1c6992009-06-13 15:52:13 +08003499 * Returns 0 if the device function was successfully reset or negative if the
Sheng Yang8dd7f802008-10-21 17:38:25 +08003500 * device doesn't support resetting a single function.
3501 */
Yu Zhao8c1c6992009-06-13 15:52:13 +08003502int __pci_reset_function(struct pci_dev *dev)
Sheng Yang8dd7f802008-10-21 17:38:25 +08003503{
Yu Zhao8c1c6992009-06-13 15:52:13 +08003504 return pci_dev_reset(dev, 0);
Sheng Yang8dd7f802008-10-21 17:38:25 +08003505}
Yu Zhao8c1c6992009-06-13 15:52:13 +08003506EXPORT_SYMBOL_GPL(__pci_reset_function);
Sheng Yang8dd7f802008-10-21 17:38:25 +08003507
3508/**
Konrad Rzeszutek Wilk6fbf9e72012-01-12 12:06:46 -05003509 * __pci_reset_function_locked - reset a PCI device function while holding
3510 * the @dev mutex lock.
3511 * @dev: PCI device to reset
3512 *
3513 * Some devices allow an individual function to be reset without affecting
3514 * other functions in the same device. The PCI device must be responsive
3515 * to PCI config space in order to use this function.
3516 *
3517 * The device function is presumed to be unused and the caller is holding
3518 * the device mutex lock when this function is called.
3519 * Resetting the device will make the contents of PCI configuration space
3520 * random, so any caller of this must be prepared to reinitialise the
3521 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3522 * etc.
3523 *
3524 * Returns 0 if the device function was successfully reset or negative if the
3525 * device doesn't support resetting a single function.
3526 */
3527int __pci_reset_function_locked(struct pci_dev *dev)
3528{
Konrad Rzeszutek Wilk977f8572012-04-24 13:15:18 -06003529 return __pci_dev_reset(dev, 0);
Konrad Rzeszutek Wilk6fbf9e72012-01-12 12:06:46 -05003530}
3531EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3532
3533/**
Michael S. Tsirkin711d5772009-07-27 23:37:48 +03003534 * pci_probe_reset_function - check whether the device can be safely reset
3535 * @dev: PCI device to reset
3536 *
3537 * Some devices allow an individual function to be reset without affecting
3538 * other functions in the same device. The PCI device must be responsive
3539 * to PCI config space in order to use this function.
3540 *
3541 * Returns 0 if the device function can be reset or negative if the
3542 * device doesn't support resetting a single function.
3543 */
3544int pci_probe_reset_function(struct pci_dev *dev)
3545{
3546 return pci_dev_reset(dev, 1);
3547}
3548
3549/**
Yu Zhao8c1c6992009-06-13 15:52:13 +08003550 * pci_reset_function - quiesce and reset a PCI device function
3551 * @dev: PCI device to reset
Sheng Yang8dd7f802008-10-21 17:38:25 +08003552 *
3553 * Some devices allow an individual function to be reset without affecting
3554 * other functions in the same device. The PCI device must be responsive
3555 * to PCI config space in order to use this function.
3556 *
3557 * This function does not just reset the PCI portion of a device, but
3558 * clears all the state associated with the device. This function differs
Yu Zhao8c1c6992009-06-13 15:52:13 +08003559 * from __pci_reset_function in that it saves and restores device state
Sheng Yang8dd7f802008-10-21 17:38:25 +08003560 * over the reset.
3561 *
Yu Zhao8c1c6992009-06-13 15:52:13 +08003562 * Returns 0 if the device function was successfully reset or negative if the
Sheng Yang8dd7f802008-10-21 17:38:25 +08003563 * device doesn't support resetting a single function.
3564 */
3565int pci_reset_function(struct pci_dev *dev)
3566{
Yu Zhao8c1c6992009-06-13 15:52:13 +08003567 int rc;
Sheng Yang8dd7f802008-10-21 17:38:25 +08003568
Yu Zhao8c1c6992009-06-13 15:52:13 +08003569 rc = pci_dev_reset(dev, 1);
3570 if (rc)
3571 return rc;
Sheng Yang8dd7f802008-10-21 17:38:25 +08003572
Alex Williamson77cb9852013-08-08 14:09:49 -06003573 pci_dev_save_and_disable(dev);
Sheng Yang8dd7f802008-10-21 17:38:25 +08003574
Yu Zhao8c1c6992009-06-13 15:52:13 +08003575 rc = pci_dev_reset(dev, 0);
Sheng Yang8dd7f802008-10-21 17:38:25 +08003576
Alex Williamson77cb9852013-08-08 14:09:49 -06003577 pci_dev_restore(dev);
Sheng Yang8dd7f802008-10-21 17:38:25 +08003578
Yu Zhao8c1c6992009-06-13 15:52:13 +08003579 return rc;
Sheng Yang8dd7f802008-10-21 17:38:25 +08003580}
3581EXPORT_SYMBOL_GPL(pci_reset_function);
3582
Alex Williamson090a3c52013-08-08 14:09:55 -06003583/* Lock devices from the top of the tree down */
3584static void pci_bus_lock(struct pci_bus *bus)
3585{
3586 struct pci_dev *dev;
3587
3588 list_for_each_entry(dev, &bus->devices, bus_list) {
3589 pci_dev_lock(dev);
3590 if (dev->subordinate)
3591 pci_bus_lock(dev->subordinate);
3592 }
3593}
3594
3595/* Unlock devices from the bottom of the tree up */
3596static void pci_bus_unlock(struct pci_bus *bus)
3597{
3598 struct pci_dev *dev;
3599
3600 list_for_each_entry(dev, &bus->devices, bus_list) {
3601 if (dev->subordinate)
3602 pci_bus_unlock(dev->subordinate);
3603 pci_dev_unlock(dev);
3604 }
3605}
3606
3607/* Lock devices from the top of the tree down */
3608static void pci_slot_lock(struct pci_slot *slot)
3609{
3610 struct pci_dev *dev;
3611
3612 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3613 if (!dev->slot || dev->slot != slot)
3614 continue;
3615 pci_dev_lock(dev);
3616 if (dev->subordinate)
3617 pci_bus_lock(dev->subordinate);
3618 }
3619}
3620
3621/* Unlock devices from the bottom of the tree up */
3622static void pci_slot_unlock(struct pci_slot *slot)
3623{
3624 struct pci_dev *dev;
3625
3626 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3627 if (!dev->slot || dev->slot != slot)
3628 continue;
3629 if (dev->subordinate)
3630 pci_bus_unlock(dev->subordinate);
3631 pci_dev_unlock(dev);
3632 }
3633}
3634
3635/* Save and disable devices from the top of the tree down */
3636static void pci_bus_save_and_disable(struct pci_bus *bus)
3637{
3638 struct pci_dev *dev;
3639
3640 list_for_each_entry(dev, &bus->devices, bus_list) {
3641 pci_dev_save_and_disable(dev);
3642 if (dev->subordinate)
3643 pci_bus_save_and_disable(dev->subordinate);
3644 }
3645}
3646
3647/*
3648 * Restore devices from top of the tree down - parent bridges need to be
3649 * restored before we can get to subordinate devices.
3650 */
3651static void pci_bus_restore(struct pci_bus *bus)
3652{
3653 struct pci_dev *dev;
3654
3655 list_for_each_entry(dev, &bus->devices, bus_list) {
3656 pci_dev_restore(dev);
3657 if (dev->subordinate)
3658 pci_bus_restore(dev->subordinate);
3659 }
3660}
3661
3662/* Save and disable devices from the top of the tree down */
3663static void pci_slot_save_and_disable(struct pci_slot *slot)
3664{
3665 struct pci_dev *dev;
3666
3667 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3668 if (!dev->slot || dev->slot != slot)
3669 continue;
3670 pci_dev_save_and_disable(dev);
3671 if (dev->subordinate)
3672 pci_bus_save_and_disable(dev->subordinate);
3673 }
3674}
3675
3676/*
3677 * Restore devices from top of the tree down - parent bridges need to be
3678 * restored before we can get to subordinate devices.
3679 */
3680static void pci_slot_restore(struct pci_slot *slot)
3681{
3682 struct pci_dev *dev;
3683
3684 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3685 if (!dev->slot || dev->slot != slot)
3686 continue;
3687 pci_dev_restore(dev);
3688 if (dev->subordinate)
3689 pci_bus_restore(dev->subordinate);
3690 }
3691}
3692
3693static int pci_slot_reset(struct pci_slot *slot, int probe)
3694{
3695 int rc;
3696
3697 if (!slot)
3698 return -ENOTTY;
3699
3700 if (!probe)
3701 pci_slot_lock(slot);
3702
3703 might_sleep();
3704
3705 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
3706
3707 if (!probe)
3708 pci_slot_unlock(slot);
3709
3710 return rc;
3711}
3712
3713/**
Alex Williamson9a3d2b92013-08-14 14:06:05 -06003714 * pci_probe_reset_slot - probe whether a PCI slot can be reset
3715 * @slot: PCI slot to probe
3716 *
3717 * Return 0 if slot can be reset, negative if a slot reset is not supported.
3718 */
3719int pci_probe_reset_slot(struct pci_slot *slot)
3720{
3721 return pci_slot_reset(slot, 1);
3722}
3723EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
3724
3725/**
Alex Williamson090a3c52013-08-08 14:09:55 -06003726 * pci_reset_slot - reset a PCI slot
3727 * @slot: PCI slot to reset
3728 *
3729 * A PCI bus may host multiple slots, each slot may support a reset mechanism
3730 * independent of other slots. For instance, some slots may support slot power
3731 * control. In the case of a 1:1 bus to slot architecture, this function may
3732 * wrap the bus reset to avoid spurious slot related events such as hotplug.
3733 * Generally a slot reset should be attempted before a bus reset. All of the
3734 * function of the slot and any subordinate buses behind the slot are reset
3735 * through this function. PCI config space of all devices in the slot and
3736 * behind the slot is saved before and restored after reset.
3737 *
3738 * Return 0 on success, non-zero on error.
3739 */
3740int pci_reset_slot(struct pci_slot *slot)
3741{
3742 int rc;
3743
3744 rc = pci_slot_reset(slot, 1);
3745 if (rc)
3746 return rc;
3747
3748 pci_slot_save_and_disable(slot);
3749
3750 rc = pci_slot_reset(slot, 0);
3751
3752 pci_slot_restore(slot);
3753
3754 return rc;
3755}
3756EXPORT_SYMBOL_GPL(pci_reset_slot);
3757
3758static int pci_bus_reset(struct pci_bus *bus, int probe)
3759{
3760 if (!bus->self)
3761 return -ENOTTY;
3762
3763 if (probe)
3764 return 0;
3765
3766 pci_bus_lock(bus);
3767
3768 might_sleep();
3769
3770 pci_reset_bridge_secondary_bus(bus->self);
3771
3772 pci_bus_unlock(bus);
3773
3774 return 0;
3775}
3776
3777/**
Alex Williamson9a3d2b92013-08-14 14:06:05 -06003778 * pci_probe_reset_bus - probe whether a PCI bus can be reset
3779 * @bus: PCI bus to probe
3780 *
3781 * Return 0 if bus can be reset, negative if a bus reset is not supported.
3782 */
3783int pci_probe_reset_bus(struct pci_bus *bus)
3784{
3785 return pci_bus_reset(bus, 1);
3786}
3787EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
3788
3789/**
Alex Williamson090a3c52013-08-08 14:09:55 -06003790 * pci_reset_bus - reset a PCI bus
3791 * @bus: top level PCI bus to reset
3792 *
3793 * Do a bus reset on the given bus and any subordinate buses, saving
3794 * and restoring state of all devices.
3795 *
3796 * Return 0 on success, non-zero on error.
3797 */
3798int pci_reset_bus(struct pci_bus *bus)
3799{
3800 int rc;
3801
3802 rc = pci_bus_reset(bus, 1);
3803 if (rc)
3804 return rc;
3805
3806 pci_bus_save_and_disable(bus);
3807
3808 rc = pci_bus_reset(bus, 0);
3809
3810 pci_bus_restore(bus);
3811
3812 return rc;
3813}
3814EXPORT_SYMBOL_GPL(pci_reset_bus);
3815
Sheng Yang8dd7f802008-10-21 17:38:25 +08003816/**
Peter Orubad556ad42007-05-15 13:59:13 +02003817 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3818 * @dev: PCI device to query
3819 *
3820 * Returns mmrbc: maximum designed memory read count in bytes
3821 * or appropriate error value.
3822 */
3823int pcix_get_max_mmrbc(struct pci_dev *dev)
3824{
Dean Nelson7c9e2b12010-03-09 22:26:55 -05003825 int cap;
Peter Orubad556ad42007-05-15 13:59:13 +02003826 u32 stat;
3827
3828 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3829 if (!cap)
3830 return -EINVAL;
3831
Dean Nelson7c9e2b12010-03-09 22:26:55 -05003832 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
Peter Orubad556ad42007-05-15 13:59:13 +02003833 return -EINVAL;
3834
Dean Nelson25daeb52010-03-09 22:26:40 -05003835 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
Peter Orubad556ad42007-05-15 13:59:13 +02003836}
3837EXPORT_SYMBOL(pcix_get_max_mmrbc);
3838
3839/**
3840 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3841 * @dev: PCI device to query
3842 *
3843 * Returns mmrbc: maximum memory read count in bytes
3844 * or appropriate error value.
3845 */
3846int pcix_get_mmrbc(struct pci_dev *dev)
3847{
Dean Nelson7c9e2b12010-03-09 22:26:55 -05003848 int cap;
Dean Nelsonbdc2bda2010-03-09 22:26:48 -05003849 u16 cmd;
Peter Orubad556ad42007-05-15 13:59:13 +02003850
3851 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3852 if (!cap)
3853 return -EINVAL;
3854
Dean Nelson7c9e2b12010-03-09 22:26:55 -05003855 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3856 return -EINVAL;
Peter Orubad556ad42007-05-15 13:59:13 +02003857
Dean Nelson7c9e2b12010-03-09 22:26:55 -05003858 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
Peter Orubad556ad42007-05-15 13:59:13 +02003859}
3860EXPORT_SYMBOL(pcix_get_mmrbc);
3861
3862/**
3863 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3864 * @dev: PCI device to query
3865 * @mmrbc: maximum memory read count in bytes
3866 * valid values are 512, 1024, 2048, 4096
3867 *
3868 * If possible sets maximum memory read byte count, some bridges have erratas
3869 * that prevent this.
3870 */
3871int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3872{
Dean Nelson7c9e2b12010-03-09 22:26:55 -05003873 int cap;
Dean Nelsonbdc2bda2010-03-09 22:26:48 -05003874 u32 stat, v, o;
3875 u16 cmd;
Peter Orubad556ad42007-05-15 13:59:13 +02003876
vignesh babu229f5af2007-08-13 18:23:14 +05303877 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
Dean Nelson7c9e2b12010-03-09 22:26:55 -05003878 return -EINVAL;
Peter Orubad556ad42007-05-15 13:59:13 +02003879
3880 v = ffs(mmrbc) - 10;
3881
3882 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3883 if (!cap)
Dean Nelson7c9e2b12010-03-09 22:26:55 -05003884 return -EINVAL;
Peter Orubad556ad42007-05-15 13:59:13 +02003885
Dean Nelson7c9e2b12010-03-09 22:26:55 -05003886 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3887 return -EINVAL;
Peter Orubad556ad42007-05-15 13:59:13 +02003888
3889 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3890 return -E2BIG;
3891
Dean Nelson7c9e2b12010-03-09 22:26:55 -05003892 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3893 return -EINVAL;
Peter Orubad556ad42007-05-15 13:59:13 +02003894
3895 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3896 if (o != v) {
Bjorn Helgaas809a3bf2012-06-20 16:41:16 -06003897 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
Peter Orubad556ad42007-05-15 13:59:13 +02003898 return -EIO;
3899
3900 cmd &= ~PCI_X_CMD_MAX_READ;
3901 cmd |= v << 2;
Dean Nelson7c9e2b12010-03-09 22:26:55 -05003902 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3903 return -EIO;
Peter Orubad556ad42007-05-15 13:59:13 +02003904 }
Dean Nelson7c9e2b12010-03-09 22:26:55 -05003905 return 0;
Peter Orubad556ad42007-05-15 13:59:13 +02003906}
3907EXPORT_SYMBOL(pcix_set_mmrbc);
3908
3909/**
3910 * pcie_get_readrq - get PCI Express read request size
3911 * @dev: PCI device to query
3912 *
3913 * Returns maximum memory read request in bytes
3914 * or appropriate error value.
3915 */
3916int pcie_get_readrq(struct pci_dev *dev)
3917{
Peter Orubad556ad42007-05-15 13:59:13 +02003918 u16 ctl;
3919
Jiang Liu59875ae2012-07-24 17:20:06 +08003920 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
Peter Orubad556ad42007-05-15 13:59:13 +02003921
Jiang Liu59875ae2012-07-24 17:20:06 +08003922 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
Peter Orubad556ad42007-05-15 13:59:13 +02003923}
3924EXPORT_SYMBOL(pcie_get_readrq);
3925
3926/**
3927 * pcie_set_readrq - set PCI Express maximum memory read request
3928 * @dev: PCI device to query
Randy Dunlap42e61f42007-07-23 21:42:11 -07003929 * @rq: maximum memory read count in bytes
Peter Orubad556ad42007-05-15 13:59:13 +02003930 * valid values are 128, 256, 512, 1024, 2048, 4096
3931 *
Jon Masonc9b378c2011-06-28 18:26:25 -05003932 * If possible sets maximum memory read request in bytes
Peter Orubad556ad42007-05-15 13:59:13 +02003933 */
3934int pcie_set_readrq(struct pci_dev *dev, int rq)
3935{
Jiang Liu59875ae2012-07-24 17:20:06 +08003936 u16 v;
Peter Orubad556ad42007-05-15 13:59:13 +02003937
vignesh babu229f5af2007-08-13 18:23:14 +05303938 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
Jiang Liu59875ae2012-07-24 17:20:06 +08003939 return -EINVAL;
Peter Orubad556ad42007-05-15 13:59:13 +02003940
Benjamin Herrenschmidta1c473a2011-10-14 14:56:15 -05003941 /*
3942 * If using the "performance" PCIe config, we clamp the
3943 * read rq size to the max packet size to prevent the
3944 * host bridge generating requests larger than we can
3945 * cope with
3946 */
3947 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
3948 int mps = pcie_get_mps(dev);
3949
Benjamin Herrenschmidta1c473a2011-10-14 14:56:15 -05003950 if (mps < rq)
3951 rq = mps;
3952 }
3953
3954 v = (ffs(rq) - 8) << 12;
Peter Orubad556ad42007-05-15 13:59:13 +02003955
Jiang Liu59875ae2012-07-24 17:20:06 +08003956 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3957 PCI_EXP_DEVCTL_READRQ, v);
Peter Orubad556ad42007-05-15 13:59:13 +02003958}
3959EXPORT_SYMBOL(pcie_set_readrq);
3960
3961/**
Jon Masonb03e7492011-07-20 15:20:54 -05003962 * pcie_get_mps - get PCI Express maximum payload size
3963 * @dev: PCI device to query
3964 *
3965 * Returns maximum payload size in bytes
Jon Masonb03e7492011-07-20 15:20:54 -05003966 */
3967int pcie_get_mps(struct pci_dev *dev)
3968{
Jon Masonb03e7492011-07-20 15:20:54 -05003969 u16 ctl;
3970
Jiang Liu59875ae2012-07-24 17:20:06 +08003971 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
Jon Masonb03e7492011-07-20 15:20:54 -05003972
Jiang Liu59875ae2012-07-24 17:20:06 +08003973 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
Jon Masonb03e7492011-07-20 15:20:54 -05003974}
3975
3976/**
3977 * pcie_set_mps - set PCI Express maximum payload size
3978 * @dev: PCI device to query
Randy Dunlap47c08f32011-08-20 11:49:43 -07003979 * @mps: maximum payload size in bytes
Jon Masonb03e7492011-07-20 15:20:54 -05003980 * valid values are 128, 256, 512, 1024, 2048, 4096
3981 *
3982 * If possible sets maximum payload size
3983 */
3984int pcie_set_mps(struct pci_dev *dev, int mps)
3985{
Jiang Liu59875ae2012-07-24 17:20:06 +08003986 u16 v;
Jon Masonb03e7492011-07-20 15:20:54 -05003987
3988 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
Jiang Liu59875ae2012-07-24 17:20:06 +08003989 return -EINVAL;
Jon Masonb03e7492011-07-20 15:20:54 -05003990
3991 v = ffs(mps) - 8;
3992 if (v > dev->pcie_mpss)
Jiang Liu59875ae2012-07-24 17:20:06 +08003993 return -EINVAL;
Jon Masonb03e7492011-07-20 15:20:54 -05003994 v <<= 5;
3995
Jiang Liu59875ae2012-07-24 17:20:06 +08003996 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3997 PCI_EXP_DEVCTL_PAYLOAD, v);
Jon Masonb03e7492011-07-20 15:20:54 -05003998}
3999
4000/**
Jacob Keller81377c82013-07-31 06:53:26 +00004001 * pcie_get_minimum_link - determine minimum link settings of a PCI device
4002 * @dev: PCI device to query
4003 * @speed: storage for minimum speed
4004 * @width: storage for minimum width
4005 *
4006 * This function will walk up the PCI device chain and determine the minimum
4007 * link width and speed of the device.
4008 */
4009int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
4010 enum pcie_link_width *width)
4011{
4012 int ret;
4013
4014 *speed = PCI_SPEED_UNKNOWN;
4015 *width = PCIE_LNK_WIDTH_UNKNOWN;
4016
4017 while (dev) {
4018 u16 lnksta;
4019 enum pci_bus_speed next_speed;
4020 enum pcie_link_width next_width;
4021
4022 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
4023 if (ret)
4024 return ret;
4025
4026 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
4027 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
4028 PCI_EXP_LNKSTA_NLW_SHIFT;
4029
4030 if (next_speed < *speed)
4031 *speed = next_speed;
4032
4033 if (next_width < *width)
4034 *width = next_width;
4035
4036 dev = dev->bus->self;
4037 }
4038
4039 return 0;
4040}
4041EXPORT_SYMBOL(pcie_get_minimum_link);
4042
4043/**
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09004044 * pci_select_bars - Make BAR mask from the type of resource
Randy Dunlapf95d8822007-02-10 14:41:56 -08004045 * @dev: the PCI device for which BAR mask is made
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09004046 * @flags: resource type mask to be selected
4047 *
4048 * This helper routine makes bar mask from the type of resource.
4049 */
4050int pci_select_bars(struct pci_dev *dev, unsigned long flags)
4051{
4052 int i, bars = 0;
4053 for (i = 0; i < PCI_NUM_RESOURCES; i++)
4054 if (pci_resource_flags(dev, i) & flags)
4055 bars |= (1 << i);
4056 return bars;
4057}
4058
Yu Zhao613e7ed2008-11-22 02:41:27 +08004059/**
4060 * pci_resource_bar - get position of the BAR associated with a resource
4061 * @dev: the PCI device
4062 * @resno: the resource number
4063 * @type: the BAR type to be filled in
4064 *
4065 * Returns BAR position in config space, or 0 if the BAR is invalid.
4066 */
4067int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
4068{
Yu Zhaod1b054d2009-03-20 11:25:11 +08004069 int reg;
4070
Yu Zhao613e7ed2008-11-22 02:41:27 +08004071 if (resno < PCI_ROM_RESOURCE) {
4072 *type = pci_bar_unknown;
4073 return PCI_BASE_ADDRESS_0 + 4 * resno;
4074 } else if (resno == PCI_ROM_RESOURCE) {
4075 *type = pci_bar_mem32;
4076 return dev->rom_base_reg;
Yu Zhaod1b054d2009-03-20 11:25:11 +08004077 } else if (resno < PCI_BRIDGE_RESOURCES) {
4078 /* device specific resource */
4079 reg = pci_iov_resource_bar(dev, resno, type);
4080 if (reg)
4081 return reg;
Yu Zhao613e7ed2008-11-22 02:41:27 +08004082 }
4083
Bjorn Helgaas865df572009-11-04 10:32:57 -07004084 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
Yu Zhao613e7ed2008-11-22 02:41:27 +08004085 return 0;
4086}
4087
Mike Travis95a8b6e2010-02-02 14:38:13 -08004088/* Some architectures require additional programming to enable VGA */
4089static arch_set_vga_state_t arch_set_vga_state;
4090
4091void __init pci_register_set_vga_state(arch_set_vga_state_t func)
4092{
4093 arch_set_vga_state = func; /* NULL disables */
4094}
4095
4096static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
Dave Airlie7ad35cf2011-05-25 14:00:49 +10004097 unsigned int command_bits, u32 flags)
Mike Travis95a8b6e2010-02-02 14:38:13 -08004098{
4099 if (arch_set_vga_state)
4100 return arch_set_vga_state(dev, decode, command_bits,
Dave Airlie7ad35cf2011-05-25 14:00:49 +10004101 flags);
Mike Travis95a8b6e2010-02-02 14:38:13 -08004102 return 0;
4103}
4104
Benjamin Herrenschmidtdeb2d2e2009-08-11 15:52:06 +10004105/**
4106 * pci_set_vga_state - set VGA decode state on device and parents if requested
Randy Dunlap19eea632009-09-17 15:28:22 -07004107 * @dev: the PCI device
4108 * @decode: true = enable decoding, false = disable decoding
4109 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
Randy Dunlap3f37d622011-05-25 19:21:25 -07004110 * @flags: traverse ancestors and change bridges
Dave Airlie3448a192010-06-01 15:32:24 +10004111 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
Benjamin Herrenschmidtdeb2d2e2009-08-11 15:52:06 +10004112 */
4113int pci_set_vga_state(struct pci_dev *dev, bool decode,
Dave Airlie3448a192010-06-01 15:32:24 +10004114 unsigned int command_bits, u32 flags)
Benjamin Herrenschmidtdeb2d2e2009-08-11 15:52:06 +10004115{
4116 struct pci_bus *bus;
4117 struct pci_dev *bridge;
4118 u16 cmd;
Mike Travis95a8b6e2010-02-02 14:38:13 -08004119 int rc;
Benjamin Herrenschmidtdeb2d2e2009-08-11 15:52:06 +10004120
Dave Airlie3448a192010-06-01 15:32:24 +10004121 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
Benjamin Herrenschmidtdeb2d2e2009-08-11 15:52:06 +10004122
Mike Travis95a8b6e2010-02-02 14:38:13 -08004123 /* ARCH specific VGA enables */
Dave Airlie3448a192010-06-01 15:32:24 +10004124 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
Mike Travis95a8b6e2010-02-02 14:38:13 -08004125 if (rc)
4126 return rc;
4127
Dave Airlie3448a192010-06-01 15:32:24 +10004128 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
4129 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4130 if (decode == true)
4131 cmd |= command_bits;
4132 else
4133 cmd &= ~command_bits;
4134 pci_write_config_word(dev, PCI_COMMAND, cmd);
4135 }
Benjamin Herrenschmidtdeb2d2e2009-08-11 15:52:06 +10004136
Dave Airlie3448a192010-06-01 15:32:24 +10004137 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
Benjamin Herrenschmidtdeb2d2e2009-08-11 15:52:06 +10004138 return 0;
4139
4140 bus = dev->bus;
4141 while (bus) {
4142 bridge = bus->self;
4143 if (bridge) {
4144 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
4145 &cmd);
4146 if (decode == true)
4147 cmd |= PCI_BRIDGE_CTL_VGA;
4148 else
4149 cmd &= ~PCI_BRIDGE_CTL_VGA;
4150 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
4151 cmd);
4152 }
4153 bus = bus->parent;
4154 }
4155 return 0;
4156}
4157
Yuji Shimada32a9a6822009-03-16 17:13:39 +09004158#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
4159static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
Thomas Gleixnere9d1e492009-11-06 22:41:23 +00004160static DEFINE_SPINLOCK(resource_alignment_lock);
Yuji Shimada32a9a6822009-03-16 17:13:39 +09004161
4162/**
4163 * pci_specified_resource_alignment - get resource alignment specified by user.
4164 * @dev: the PCI device to get
4165 *
4166 * RETURNS: Resource alignment if it is specified.
4167 * Zero if it is not specified.
4168 */
Bjorn Helgaas9738abe2013-04-12 11:20:03 -06004169static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
Yuji Shimada32a9a6822009-03-16 17:13:39 +09004170{
4171 int seg, bus, slot, func, align_order, count;
4172 resource_size_t align = 0;
4173 char *p;
4174
4175 spin_lock(&resource_alignment_lock);
4176 p = resource_alignment_param;
4177 while (*p) {
4178 count = 0;
4179 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
4180 p[count] == '@') {
4181 p += count + 1;
4182 } else {
4183 align_order = -1;
4184 }
4185 if (sscanf(p, "%x:%x:%x.%x%n",
4186 &seg, &bus, &slot, &func, &count) != 4) {
4187 seg = 0;
4188 if (sscanf(p, "%x:%x.%x%n",
4189 &bus, &slot, &func, &count) != 3) {
4190 /* Invalid format */
4191 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
4192 p);
4193 break;
4194 }
4195 }
4196 p += count;
4197 if (seg == pci_domain_nr(dev->bus) &&
4198 bus == dev->bus->number &&
4199 slot == PCI_SLOT(dev->devfn) &&
4200 func == PCI_FUNC(dev->devfn)) {
4201 if (align_order == -1) {
4202 align = PAGE_SIZE;
4203 } else {
4204 align = 1 << align_order;
4205 }
4206 /* Found */
4207 break;
4208 }
4209 if (*p != ';' && *p != ',') {
4210 /* End of param or invalid format */
4211 break;
4212 }
4213 p++;
4214 }
4215 spin_unlock(&resource_alignment_lock);
4216 return align;
4217}
4218
Yinghai Lu2069ecf2012-02-15 21:40:31 -08004219/*
4220 * This function disables memory decoding and releases memory resources
4221 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
4222 * It also rounds up size to specified alignment.
4223 * Later on, the kernel will assign page-aligned memory resource back
4224 * to the device.
4225 */
4226void pci_reassigndev_resource_alignment(struct pci_dev *dev)
4227{
4228 int i;
4229 struct resource *r;
4230 resource_size_t align, size;
4231 u16 command;
4232
Yinghai Lu10c463a2012-03-18 22:46:26 -07004233 /* check if specified PCI is target device to reassign */
4234 align = pci_specified_resource_alignment(dev);
4235 if (!align)
Yinghai Lu2069ecf2012-02-15 21:40:31 -08004236 return;
4237
4238 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
4239 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
4240 dev_warn(&dev->dev,
4241 "Can't reassign resources to host bridge.\n");
4242 return;
4243 }
4244
4245 dev_info(&dev->dev,
4246 "Disabling memory decoding and releasing memory resources.\n");
4247 pci_read_config_word(dev, PCI_COMMAND, &command);
4248 command &= ~PCI_COMMAND_MEMORY;
4249 pci_write_config_word(dev, PCI_COMMAND, command);
4250
Yinghai Lu2069ecf2012-02-15 21:40:31 -08004251 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
4252 r = &dev->resource[i];
4253 if (!(r->flags & IORESOURCE_MEM))
4254 continue;
4255 size = resource_size(r);
4256 if (size < align) {
4257 size = align;
4258 dev_info(&dev->dev,
4259 "Rounding up size of resource #%d to %#llx.\n",
4260 i, (unsigned long long)size);
4261 }
4262 r->end = size - 1;
4263 r->start = 0;
4264 }
4265 /* Need to disable bridge's resource window,
4266 * to enable the kernel to reassign new resource
4267 * window later on.
4268 */
4269 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4270 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
4271 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
4272 r = &dev->resource[i];
4273 if (!(r->flags & IORESOURCE_MEM))
4274 continue;
4275 r->end = resource_size(r) - 1;
4276 r->start = 0;
4277 }
4278 pci_disable_bridge_window(dev);
4279 }
4280}
4281
Bjorn Helgaas9738abe2013-04-12 11:20:03 -06004282static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
Yuji Shimada32a9a6822009-03-16 17:13:39 +09004283{
4284 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
4285 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
4286 spin_lock(&resource_alignment_lock);
4287 strncpy(resource_alignment_param, buf, count);
4288 resource_alignment_param[count] = '\0';
4289 spin_unlock(&resource_alignment_lock);
4290 return count;
4291}
4292
Bjorn Helgaas9738abe2013-04-12 11:20:03 -06004293static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
Yuji Shimada32a9a6822009-03-16 17:13:39 +09004294{
4295 size_t count;
4296 spin_lock(&resource_alignment_lock);
4297 count = snprintf(buf, size, "%s", resource_alignment_param);
4298 spin_unlock(&resource_alignment_lock);
4299 return count;
4300}
4301
4302static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
4303{
4304 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
4305}
4306
4307static ssize_t pci_resource_alignment_store(struct bus_type *bus,
4308 const char *buf, size_t count)
4309{
4310 return pci_set_resource_alignment_param(buf, count);
4311}
4312
4313BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
4314 pci_resource_alignment_store);
4315
4316static int __init pci_resource_alignment_sysfs_init(void)
4317{
4318 return bus_create_file(&pci_bus_type,
4319 &bus_attr_resource_alignment);
4320}
4321
4322late_initcall(pci_resource_alignment_sysfs_init);
4323
Bill Pemberton15856ad2012-11-21 15:35:00 -05004324static void pci_no_domains(void)
Jeff Garzik32a2eea2007-10-11 16:57:27 -04004325{
4326#ifdef CONFIG_PCI_DOMAINS
4327 pci_domains_supported = 0;
4328#endif
4329}
4330
Andrew Patterson0ef5f8f2008-11-10 15:30:50 -07004331/**
Taku Izumi642c92d2012-10-30 15:26:18 +09004332 * pci_ext_cfg_avail - can we access extended PCI config space?
Andrew Patterson0ef5f8f2008-11-10 15:30:50 -07004333 *
4334 * Returns 1 if we can access PCI extended config space (offsets
4335 * greater than 0xff). This is the default implementation. Architecture
4336 * implementations can override this.
4337 */
Taku Izumi642c92d2012-10-30 15:26:18 +09004338int __weak pci_ext_cfg_avail(void)
Andrew Patterson0ef5f8f2008-11-10 15:30:50 -07004339{
4340 return 1;
4341}
4342
Benjamin Herrenschmidt2d1c8612009-12-09 17:52:13 +11004343void __weak pci_fixup_cardbus(struct pci_bus *bus)
4344{
4345}
4346EXPORT_SYMBOL(pci_fixup_cardbus);
4347
Al Viroad04d312008-11-22 17:37:14 +00004348static int __init pci_setup(char *str)
Linus Torvalds1da177e2005-04-16 15:20:36 -07004349{
4350 while (str) {
4351 char *k = strchr(str, ',');
4352 if (k)
4353 *k++ = 0;
4354 if (*str && (str = pcibios_setup(str)) && *str) {
Matthew Wilcox309e57d2006-03-05 22:33:34 -07004355 if (!strcmp(str, "nomsi")) {
4356 pci_no_msi();
Randy Dunlap7f785762007-10-05 13:17:58 -07004357 } else if (!strcmp(str, "noaer")) {
4358 pci_no_aer();
Yinghai Lub55438f2012-02-23 19:23:30 -08004359 } else if (!strncmp(str, "realloc=", 8)) {
4360 pci_realloc_get_opt(str + 8);
Ram Paif483d392011-07-07 11:19:10 -07004361 } else if (!strncmp(str, "realloc", 7)) {
Yinghai Lub55438f2012-02-23 19:23:30 -08004362 pci_realloc_get_opt("on");
Jeff Garzik32a2eea2007-10-11 16:57:27 -04004363 } else if (!strcmp(str, "nodomains")) {
4364 pci_no_domains();
Rafael J. Wysocki6748dcc2012-03-01 00:06:33 +01004365 } else if (!strncmp(str, "noari", 5)) {
4366 pcie_ari_disabled = true;
Atsushi Nemoto4516a612007-02-05 16:36:06 -08004367 } else if (!strncmp(str, "cbiosize=", 9)) {
4368 pci_cardbus_io_size = memparse(str + 9, &str);
4369 } else if (!strncmp(str, "cbmemsize=", 10)) {
4370 pci_cardbus_mem_size = memparse(str + 10, &str);
Yuji Shimada32a9a6822009-03-16 17:13:39 +09004371 } else if (!strncmp(str, "resource_alignment=", 19)) {
4372 pci_set_resource_alignment_param(str + 19,
4373 strlen(str + 19));
Andrew Patterson43c16402009-04-22 16:52:09 -06004374 } else if (!strncmp(str, "ecrc=", 5)) {
4375 pcie_ecrc_get_policy(str + 5);
Eric W. Biederman28760482009-09-09 14:09:24 -07004376 } else if (!strncmp(str, "hpiosize=", 9)) {
4377 pci_hotplug_io_size = memparse(str + 9, &str);
4378 } else if (!strncmp(str, "hpmemsize=", 10)) {
4379 pci_hotplug_mem_size = memparse(str + 10, &str);
Jon Mason5f39e672011-10-03 09:50:20 -05004380 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
4381 pcie_bus_config = PCIE_BUS_TUNE_OFF;
Jon Masonb03e7492011-07-20 15:20:54 -05004382 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
4383 pcie_bus_config = PCIE_BUS_SAFE;
4384 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
4385 pcie_bus_config = PCIE_BUS_PERFORMANCE;
Jon Mason5f39e672011-10-03 09:50:20 -05004386 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
4387 pcie_bus_config = PCIE_BUS_PEER2PEER;
Bjorn Helgaas284f5f92012-04-30 15:21:02 -06004388 } else if (!strncmp(str, "pcie_scan_all", 13)) {
4389 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
Matthew Wilcox309e57d2006-03-05 22:33:34 -07004390 } else {
4391 printk(KERN_ERR "PCI: Unknown option `%s'\n",
4392 str);
4393 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07004394 }
4395 str = k;
4396 }
Andi Kleen0637a702006-09-26 10:52:41 +02004397 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07004398}
Andi Kleen0637a702006-09-26 10:52:41 +02004399early_param("pci", pci_setup);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004400
Tejun Heo0b62e132007-07-27 14:43:35 +09004401EXPORT_SYMBOL(pci_reenable_device);
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +11004402EXPORT_SYMBOL(pci_enable_device_io);
4403EXPORT_SYMBOL(pci_enable_device_mem);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004404EXPORT_SYMBOL(pci_enable_device);
Tejun Heo9ac78492007-01-20 16:00:26 +09004405EXPORT_SYMBOL(pcim_enable_device);
4406EXPORT_SYMBOL(pcim_pin_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004407EXPORT_SYMBOL(pci_disable_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004408EXPORT_SYMBOL(pci_find_capability);
4409EXPORT_SYMBOL(pci_bus_find_capability);
4410EXPORT_SYMBOL(pci_release_regions);
4411EXPORT_SYMBOL(pci_request_regions);
Arjan van de Vene8de1482008-10-22 19:55:31 -07004412EXPORT_SYMBOL(pci_request_regions_exclusive);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004413EXPORT_SYMBOL(pci_release_region);
4414EXPORT_SYMBOL(pci_request_region);
Arjan van de Vene8de1482008-10-22 19:55:31 -07004415EXPORT_SYMBOL(pci_request_region_exclusive);
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09004416EXPORT_SYMBOL(pci_release_selected_regions);
4417EXPORT_SYMBOL(pci_request_selected_regions);
Arjan van de Vene8de1482008-10-22 19:55:31 -07004418EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004419EXPORT_SYMBOL(pci_set_master);
Ben Hutchings6a479072008-12-23 03:08:29 +00004420EXPORT_SYMBOL(pci_clear_master);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004421EXPORT_SYMBOL(pci_set_mwi);
Randy Dunlap694625c2007-07-09 11:55:54 -07004422EXPORT_SYMBOL(pci_try_set_mwi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004423EXPORT_SYMBOL(pci_clear_mwi);
Brett M Russa04ce0f2005-08-15 15:23:41 -04004424EXPORT_SYMBOL_GPL(pci_intx);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004425EXPORT_SYMBOL(pci_assign_resource);
4426EXPORT_SYMBOL(pci_find_parent_resource);
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09004427EXPORT_SYMBOL(pci_select_bars);
Linus Torvalds1da177e2005-04-16 15:20:36 -07004428
4429EXPORT_SYMBOL(pci_set_power_state);
4430EXPORT_SYMBOL(pci_save_state);
4431EXPORT_SYMBOL(pci_restore_state);
Rafael J. Wysockie5899e12008-07-19 14:39:24 +02004432EXPORT_SYMBOL(pci_pme_capable);
Rafael J. Wysocki5a6c9b62008-08-08 00:14:24 +02004433EXPORT_SYMBOL(pci_pme_active);
Rafael J. Wysocki0235c4f2008-08-18 21:38:00 +02004434EXPORT_SYMBOL(pci_wake_from_d3);
Rafael J. Wysockie5899e12008-07-19 14:39:24 +02004435EXPORT_SYMBOL(pci_target_state);
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02004436EXPORT_SYMBOL(pci_prepare_to_sleep);
4437EXPORT_SYMBOL(pci_back_from_sleep);
Brian Kingf7bdd122007-04-06 16:39:36 -05004438EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);