Blame - drivers/irqchip/Kconfig - kernel/msm-4.19

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Thomas Petazzoni	f6e916b	2012-11-20 23:00:52 +0100	[diff] [blame]	1	config IRQCHIP
				2	def_bool y
				3	depends on OF_IRQ
				4
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	5	config ARM_GIC
				6	bool
				7	select IRQ_DOMAIN
Yingjoe Chen	9a1091e	2014-11-25 16:04:19 +0800	[diff] [blame]	8	select IRQ_DOMAIN_HIERARCHY
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	9	select MULTI_IRQ_HANDLER
				10
Jon Hunter	9c8eddd	2016-06-07 16:12:34 +0100	[diff] [blame]	11	config ARM_GIC_PM
				12	bool
				13	depends on PM
				14	select ARM_GIC
				15	select PM_CLK
				16
Linus Walleij	a27d21e	2015-12-18 10:44:53 +0100	[diff] [blame]	17	config ARM_GIC_MAX_NR
				18	int
				19	default 2 if ARCH_REALVIEW
				20	default 1
				21
Suravee Suthikulpanit	853a33c	2014-11-25 18:47:22 +0000	[diff] [blame]	22	config ARM_GIC_V2M
				23	bool
Arnd Bergmann	3ee8036	2016-06-15 15:47:33 -0500	[diff] [blame]	24	depends on PCI
				25	select ARM_GIC
				26	select PCI_MSI
Suravee Suthikulpanit	853a33c	2014-11-25 18:47:22 +0000	[diff] [blame]	27
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	28	config GIC_NON_BANKED
				29	bool
				30
Marc Zyngier	021f653	2014-06-30 16:01:31 +0100	[diff] [blame]	31	config ARM_GIC_V3
				32	bool
				33	select IRQ_DOMAIN
				34	select MULTI_IRQ_HANDLER
Marc Zyngier	443acc4	2014-11-24 14:35:09 +0000	[diff] [blame]	35	select IRQ_DOMAIN_HIERARCHY
Marc Zyngier	e3825ba	2016-04-11 09:57:54 +0100	[diff] [blame]	36	select PARTITION_PERCPU
Marc Zyngier	021f653	2014-06-30 16:01:31 +0100	[diff] [blame]	37
Marc Zyngier	1981272	2014-11-24 14:35:19 +0000	[diff] [blame]	38	config ARM_GIC_V3_ITS
				39	bool
Arnd Bergmann	3ee8036	2016-06-15 15:47:33 -0500	[diff] [blame]	40	depends on PCI
				41	depends on PCI_MSI
Tomasz Nowicki	3f010cf	2016-09-12 20:32:25 +0200	[diff] [blame]	42	select ACPI_IORT if ACPI
Uwe Kleine-König	292ec08	2013-06-26 09:18:48 +0200	[diff] [blame]	43
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	44	config ARM_NVIC
				45	bool
				46	select IRQ_DOMAIN
Stefan Agner	2d9f59f	2015-05-16 11:44:16 +0200	[diff] [blame]	47	select IRQ_DOMAIN_HIERARCHY
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	48	select GENERIC_IRQ_CHIP
				49
				50	config ARM_VIC
				51	bool
				52	select IRQ_DOMAIN
				53	select MULTI_IRQ_HANDLER
				54
				55	config ARM_VIC_NR
				56	int
				57	default 4 if ARCH_S5PV210
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	58	default 2
				59	depends on ARM_VIC
				60	help
				61	The maximum number of VICs available in the system, for
				62	power management.
				63
Thomas Petazzoni	fed6d33	2016-02-10 15:46:56 +0100	[diff] [blame]	64	config ARMADA_370_XP_IRQ
				65	bool
Thomas Petazzoni	fed6d33	2016-02-10 15:46:56 +0100	[diff] [blame]	66	select GENERIC_IRQ_CHIP
Arnd Bergmann	3ee8036	2016-06-15 15:47:33 -0500	[diff] [blame]	67	select PCI_MSI if PCI
Thomas Petazzoni	fed6d33	2016-02-10 15:46:56 +0100	[diff] [blame]	68
Antoine Tenart	e6b78f2	2016-02-19 16:22:44 +0100	[diff] [blame]	69	config ALPINE_MSI
				70	bool
Arnd Bergmann	3ee8036	2016-06-15 15:47:33 -0500	[diff] [blame]	71	depends on PCI
				72	select PCI_MSI
Antoine Tenart	e6b78f2	2016-02-19 16:22:44 +0100	[diff] [blame]	73	select GENERIC_IRQ_CHIP
Antoine Tenart	e6b78f2	2016-02-19 16:22:44 +0100	[diff] [blame]	74
Boris BREZILLON	b1479eb	2014-07-10 19:14:18 +0200	[diff] [blame]	75	config ATMEL_AIC_IRQ
				76	bool
				77	select GENERIC_IRQ_CHIP
				78	select IRQ_DOMAIN
				79	select MULTI_IRQ_HANDLER
				80	select SPARSE_IRQ
				81
				82	config ATMEL_AIC5_IRQ
				83	bool
				84	select GENERIC_IRQ_CHIP
				85	select IRQ_DOMAIN
				86	select MULTI_IRQ_HANDLER
				87	select SPARSE_IRQ
				88
Ralf Baechle	0509cfd	2015-07-08 14:46:08 +0200	[diff] [blame]	89	config I8259
				90	bool
				91	select IRQ_DOMAIN
				92
Simon Arlott	c7c42ec	2015-11-22 14:30:14 +0000	[diff] [blame]	93	config BCM6345_L1_IRQ
				94	bool
				95	select GENERIC_IRQ_CHIP
				96	select IRQ_DOMAIN
				97
Kevin Cernekee	5f7f031	2014-12-25 09:49:06 -0800	[diff] [blame]	98	config BCM7038_L1_IRQ
				99	bool
				100	select GENERIC_IRQ_CHIP
				101	select IRQ_DOMAIN
				102
Kevin Cernekee	a4fcbb8	2014-11-06 22:44:27 -0800	[diff] [blame]	103	config BCM7120_L2_IRQ
				104	bool
				105	select GENERIC_IRQ_CHIP
				106	select IRQ_DOMAIN
				107
Florian Fainelli	7f646e9	2014-05-23 17:40:53 -0700	[diff] [blame]	108	config BRCMSTB_L2_IRQ
				109	bool
Florian Fainelli	7f646e9	2014-05-23 17:40:53 -0700	[diff] [blame]	110	select GENERIC_IRQ_CHIP
				111	select IRQ_DOMAIN
				112
Sebastian Hesselbarth	350d71b9	2013-09-09 14:01:20 +0200	[diff] [blame]	113	config DW_APB_ICTL
				114	bool
Jisheng Zhang	e158849	2014-10-22 20:59:10 +0800	[diff] [blame]	115	select GENERIC_IRQ_CHIP
Sebastian Hesselbarth	350d71b9	2013-09-09 14:01:20 +0200	[diff] [blame]	116	select IRQ_DOMAIN
				117
Linus Walleij	6ee532e	2017-03-18 17:53:24 +0100	[diff] [blame]	118	config FARADAY_FTINTC010
				119	bool
				120	select IRQ_DOMAIN
				121	select MULTI_IRQ_HANDLER
				122	select SPARSE_IRQ
				123
MaJun	9a7c4ab	2016-03-23 17:06:33 +0800	[diff] [blame]	124	config HISILICON_IRQ_MBIGEN
				125	bool
				126	select ARM_GIC_V3
				127	select ARM_GIC_V3_ITS
MaJun	9a7c4ab	2016-03-23 17:06:33 +0800	[diff] [blame]	128
James Hogan	b6ef916	2013-04-22 15:43:50 +0100	[diff] [blame]	129	config IMGPDC_IRQ
				130	bool
				131	select GENERIC_IRQ_CHIP
				132	select IRQ_DOMAIN
				133
Ralf Baechle	67e38cf	2015-05-26 18:20:06 +0200	[diff] [blame]	134	config IRQ_MIPS_CPU
				135	bool
				136	select GENERIC_IRQ_CHIP
Paul Burton	3838a54	2017-03-30 12:06:11 -0700	[diff] [blame]	137	select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
Ralf Baechle	67e38cf	2015-05-26 18:20:06 +0200	[diff] [blame]	138	select IRQ_DOMAIN
Paul Burton	3838a54	2017-03-30 12:06:11 -0700	[diff] [blame]	139	select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
Ralf Baechle	67e38cf	2015-05-26 18:20:06 +0200	[diff] [blame]	140
Alexander Shiyan	afc98d9	2014-02-02 12:07:46 +0400	[diff] [blame]	141	config CLPS711X_IRQCHIP
				142	bool
				143	depends on ARCH_CLPS711X
				144	select IRQ_DOMAIN
				145	select MULTI_IRQ_HANDLER
				146	select SPARSE_IRQ
				147	default y
				148
Stefan Kristiansson	4db8e6d	2014-05-26 23:31:42 +0300	[diff] [blame]	149	config OR1K_PIC
				150	bool
				151	select IRQ_DOMAIN
				152
Felipe Balbi	8598066	2014-09-15 16:15:02 -0500	[diff] [blame]	153	config OMAP_IRQCHIP
				154	bool
				155	select GENERIC_IRQ_CHIP
				156	select IRQ_DOMAIN
				157
Sebastian Hesselbarth	9dbd90f	2013-06-06 18:27:09 +0200	[diff] [blame]	158	config ORION_IRQCHIP
				159	bool
				160	select IRQ_DOMAIN
				161	select MULTI_IRQ_HANDLER
				162
Cristian Birsan	aaa8666	2016-01-13 18:15:35 -0700	[diff] [blame]	163	config PIC32_EVIC
				164	bool
				165	select GENERIC_IRQ_CHIP
				166	select IRQ_DOMAIN
				167
Rich Felker	981b58f	2016-08-04 04:30:37 +0000	[diff] [blame]	168	config JCORE_AIC
Rich Felker	3602ffd	2016-10-19 17:53:52 +0000	[diff] [blame]	169	bool "J-Core integrated AIC" if COMPILE_TEST
				170	depends on OF
Rich Felker	981b58f	2016-08-04 04:30:37 +0000	[diff] [blame]	171	select IRQ_DOMAIN
				172	help
				173	Support for the J-Core integrated AIC.
				174
Magnus Damm	4435804	2013-02-18 23:28:34 +0900	[diff] [blame]	175	config RENESAS_INTC_IRQPIN
				176	bool
				177	select IRQ_DOMAIN
				178
Magnus Damm	fbc83b7	2013-02-27 17:15:01 +0900	[diff] [blame]	179	config RENESAS_IRQC
				180	bool
Magnus Damm	99c221d	2015-09-28 18:42:37 +0900	[diff] [blame]	181	select GENERIC_IRQ_CHIP
Magnus Damm	fbc83b7	2013-02-27 17:15:01 +0900	[diff] [blame]	182	select IRQ_DOMAIN
				183
Lee Jones	0708848	2015-02-18 15:13:58 +0000	[diff] [blame]	184	config ST_IRQCHIP
				185	bool
				186	select REGMAP
				187	select MFD_SYSCON
				188	help
				189	Enables SysCfg Controlled IRQs on STi based platforms.
				190
Mans Rullgard	4bba668	2016-01-20 18:07:17 +0000	[diff] [blame]	191	config TANGO_IRQ
				192	bool
				193	select IRQ_DOMAIN
				194	select GENERIC_IRQ_CHIP
				195
Christian Ruppert	b06eb01	2013-06-25 18:29:57 +0200	[diff] [blame]	196	config TB10X_IRQC
				197	bool
				198	select IRQ_DOMAIN
				199	select GENERIC_IRQ_CHIP
				200
Damien Riegel	d01f863	2015-12-21 15:11:23 -0500	[diff] [blame]	201	config TS4800_IRQ
				202	tristate "TS-4800 IRQ controller"
				203	select IRQ_DOMAIN
Richard Weinberger	0df337c	2016-01-25 23:24:17 +0100	[diff] [blame]	204	depends on HAS_IOMEM
Jean Delvare	d2b383d	2016-02-09 11:19:20 +0100	[diff] [blame]	205	depends on SOC_IMX51 \|\| COMPILE_TEST
Damien Riegel	d01f863	2015-12-21 15:11:23 -0500	[diff] [blame]	206	help
				207	Support for the TS-4800 FPGA IRQ controller
				208
Linus Walleij	2389d50	2012-10-31 22:04:31 +0100	[diff] [blame]	209	config VERSATILE_FPGA_IRQ
				210	bool
				211	select IRQ_DOMAIN
				212
				213	config VERSATILE_FPGA_IRQ_NR
				214	int
				215	default 4
				216	depends on VERSATILE_FPGA_IRQ
Max Filippov	26a8e96	2013-12-01 12:04:57 +0400	[diff] [blame]	217
				218	config XTENSA_MX
				219	bool
				220	select IRQ_DOMAIN
Sricharan R	96ca848	2013-12-03 15:57:23 +0530	[diff] [blame]	221
Zubair Lutfullah Kakakhel	0547dc7	2016-11-14 12:13:45 +0000	[diff] [blame]	222	config XILINX_INTC
				223	bool
				224	select IRQ_DOMAIN
				225
Sricharan R	96ca848	2013-12-03 15:57:23 +0530	[diff] [blame]	226	config IRQ_CROSSBAR
				227	bool
				228	help
Masanari Iida	f54619f	2014-09-18 12:09:42 +0900	[diff] [blame]	229	Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R	96ca848	2013-12-03 15:57:23 +0530	[diff] [blame]	230	The primary irqchip invokes the crossbar's callback which inturn allocates
				231	a free irq and configures the IP. Thus the peripheral interrupts are
				232	routed to one of the free irqchip interrupt lines.
Grygorii Strashko	89323f8	2014-07-23 17:40:30 +0300	[diff] [blame]	233
				234	config KEYSTONE_IRQ
				235	tristate "Keystone 2 IRQ controller IP"
				236	depends on ARCH_KEYSTONE
				237	help
				238	Support for Texas Instruments Keystone 2 IRQ controller IP which
				239	is part of the Keystone 2 IPC mechanism
Andrew Bresticker	8a19b8f	2014-09-18 14:47:19 -0700	[diff] [blame]	240
				241	config MIPS_GIC
				242	bool
Qais Yousef	bb11cff	2015-12-08 13:20:28 +0000	[diff] [blame]	243	select GENERIC_IRQ_IPI
Qais Yousef	2af70a9	2015-12-08 13:20:23 +0000	[diff] [blame]	244	select IRQ_DOMAIN_HIERARCHY
Andrew Bresticker	8a19b8f	2014-09-18 14:47:19 -0700	[diff] [blame]	245	select MIPS_CM
Yoshinori Sato	8a76448	2015-05-10 02:30:47 +0900	[diff] [blame]	246
Paul Burton	44e08e7	2015-05-24 16:11:31 +0100	[diff] [blame]	247	config INGENIC_IRQ
				248	bool
				249	depends on MACH_INGENIC
				250	default y
Linus Torvalds	78c10e5	2015-06-27 12:44:34 -0700	[diff] [blame]	251
Yoshinori Sato	8a76448	2015-05-10 02:30:47 +0900	[diff] [blame]	252	config RENESAS_H8300H_INTC
				253	bool
				254	select IRQ_DOMAIN
				255
				256	config RENESAS_H8S_INTC
				257	bool
Linus Torvalds	78c10e5	2015-06-27 12:44:34 -0700	[diff] [blame]	258	select IRQ_DOMAIN
Shenwei Wang	e324c4d	2015-08-24 14:04:15 -0500	[diff] [blame]	259
				260	config IMX_GPCV2
				261	bool
				262	select IRQ_DOMAIN
				263	help
				264	Enables the wakeup IRQs for IMX platforms with GPCv2 block
Oleksij Rempel	7e4ac67	2015-10-12 21:15:34 +0200	[diff] [blame]	265
				266	config IRQ_MXS
				267	def_bool y if MACH_ASM9260 \|\| ARCH_MXS
				268	select IRQ_DOMAIN
				269	select STMP_DEVICE
Thomas Petazzoni	c27f29b	2016-02-19 14:34:43 +0100	[diff] [blame]	270
Thomas Petazzoni	a68a63c	2017-06-21 15:29:14 +0200	[diff] [blame]	271	config MVEBU_GICP
				272	bool
				273
Thomas Petazzoni	e0de91a	2017-06-21 15:29:15 +0200	[diff] [blame^]	274	config MVEBU_ICU
				275	bool
				276
Thomas Petazzoni	c27f29b	2016-02-19 14:34:43 +0100	[diff] [blame]	277	config MVEBU_ODMI
				278	bool
Arnd Bergmann	fa23b9d	2017-03-14 13:54:12 +0100	[diff] [blame]	279	select GENERIC_MSI_IRQ_DOMAIN
Marc Zyngier	9e2c986	2016-04-11 09:57:53 +0100	[diff] [blame]	280
Thomas Petazzoni	a109893	2016-08-05 16:55:19 +0200	[diff] [blame]	281	config MVEBU_PIC
				282	bool
				283
Minghuan Lian	b8f3ebe	2016-03-23 19:08:20 +0800	[diff] [blame]	284	config LS_SCFG_MSI
				285	def_bool y if SOC_LS1021A \|\| ARCH_LAYERSCAPE
				286	depends on PCI && PCI_MSI
Minghuan Lian	b8f3ebe	2016-03-23 19:08:20 +0800	[diff] [blame]	287
Marc Zyngier	9e2c986	2016-04-11 09:57:53 +0100	[diff] [blame]	288	config PARTITION_PERCPU
				289	bool
Linus Torvalds	0efacbb	2016-05-19 09:46:18 -0700	[diff] [blame]	290
Noam Camus	44df427c	2015-10-29 00:26:22 +0200	[diff] [blame]	291	config EZNPS_GIC
				292	bool "NPS400 Global Interrupt Manager (GIM)"
Arnd Bergmann	ffd565e	2016-05-12 23:03:35 +0200	[diff] [blame]	293	depends on ARC \|\| (COMPILE_TEST && !64BIT)
Noam Camus	44df427c	2015-10-29 00:26:22 +0200	[diff] [blame]	294	select IRQ_DOMAIN
				295	help
				296	Support the EZchip NPS400 global interrupt controller
Alexandre TORGUE	e0720416	2016-09-20 18:00:57 +0200	[diff] [blame]	297
				298	config STM32_EXTI
				299	bool
				300	select IRQ_DOMAIN
Agustin Vega-Frias	f20cc9b	2017-02-02 18:23:59 -0500	[diff] [blame]	301
				302	config QCOM_IRQ_COMBINER
				303	bool "QCOM IRQ combiner support"
				304	depends on ARCH_QCOM && ACPI
				305	select IRQ_DOMAIN
				306	select IRQ_DOMAIN_HIERARCHY
				307	help
				308	Say yes here to add support for the IRQ combiner devices embedded
				309	in Qualcomm Technologies chips.