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Xiubo Li43550822013-12-17 11:24:38 +08001/*
2 * Freescale ALSA SoC Digital Audio Interface (SAI) driver.
3 *
4 * Copyright 2012-2013 Freescale Semiconductor, Inc.
5 *
6 * This program is free software, you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation, either version 2 of the License, or(at your
9 * option) any later version.
10 *
11 */
12
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/dmaengine.h>
16#include <linux/module.h>
17#include <linux/of_address.h>
Xiubo Li78957fc2014-02-08 14:38:28 +080018#include <linux/regmap.h>
Xiubo Li43550822013-12-17 11:24:38 +080019#include <linux/slab.h>
20#include <sound/core.h>
21#include <sound/dmaengine_pcm.h>
22#include <sound/pcm_params.h>
23
24#include "fsl_sai.h"
Nicolin Chenc7540642014-04-01 19:34:09 +080025#include "imx-pcm.h"
Xiubo Li43550822013-12-17 11:24:38 +080026
Nicolin Chene2681a12014-03-27 19:06:59 +080027#define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
28 FSL_SAI_CSR_FEIE)
29
30static irqreturn_t fsl_sai_isr(int irq, void *devid)
31{
32 struct fsl_sai *sai = (struct fsl_sai *)devid;
33 struct device *dev = &sai->pdev->dev;
Nicolin Chen413312a2014-03-28 19:39:25 +080034 u32 flags, xcsr, mask;
35 bool irq_none = true;
Nicolin Chene2681a12014-03-27 19:06:59 +080036
Nicolin Chen413312a2014-03-28 19:39:25 +080037 /*
38 * Both IRQ status bits and IRQ mask bits are in the xCSR but
39 * different shifts. And we here create a mask only for those
40 * IRQs that we activated.
41 */
Nicolin Chene2681a12014-03-27 19:06:59 +080042 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
43
44 /* Tx IRQ */
45 regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
Nicolin Chen413312a2014-03-28 19:39:25 +080046 flags = xcsr & mask;
Nicolin Chene2681a12014-03-27 19:06:59 +080047
Nicolin Chen413312a2014-03-28 19:39:25 +080048 if (flags)
49 irq_none = false;
50 else
51 goto irq_rx;
52
53 if (flags & FSL_SAI_CSR_WSF)
Nicolin Chene2681a12014-03-27 19:06:59 +080054 dev_dbg(dev, "isr: Start of Tx word detected\n");
55
Nicolin Chen413312a2014-03-28 19:39:25 +080056 if (flags & FSL_SAI_CSR_SEF)
Nicolin Chene2681a12014-03-27 19:06:59 +080057 dev_warn(dev, "isr: Tx Frame sync error detected\n");
58
Nicolin Chen413312a2014-03-28 19:39:25 +080059 if (flags & FSL_SAI_CSR_FEF) {
Nicolin Chene2681a12014-03-27 19:06:59 +080060 dev_warn(dev, "isr: Transmit underrun detected\n");
61 /* FIFO reset for safety */
62 xcsr |= FSL_SAI_CSR_FR;
63 }
64
Nicolin Chen413312a2014-03-28 19:39:25 +080065 if (flags & FSL_SAI_CSR_FWF)
Nicolin Chene2681a12014-03-27 19:06:59 +080066 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
67
Nicolin Chen413312a2014-03-28 19:39:25 +080068 if (flags & FSL_SAI_CSR_FRF)
Nicolin Chene2681a12014-03-27 19:06:59 +080069 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
70
Nicolin Chen413312a2014-03-28 19:39:25 +080071 flags &= FSL_SAI_CSR_xF_W_MASK;
72 xcsr &= ~FSL_SAI_CSR_xF_MASK;
Nicolin Chene2681a12014-03-27 19:06:59 +080073
Nicolin Chen413312a2014-03-28 19:39:25 +080074 if (flags)
75 regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr);
76
77irq_rx:
Nicolin Chene2681a12014-03-27 19:06:59 +080078 /* Rx IRQ */
79 regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr);
Nicolin Chen413312a2014-03-28 19:39:25 +080080 flags = xcsr & mask;
Nicolin Chene2681a12014-03-27 19:06:59 +080081
Nicolin Chen413312a2014-03-28 19:39:25 +080082 if (flags)
83 irq_none = false;
84 else
85 goto out;
86
87 if (flags & FSL_SAI_CSR_WSF)
Nicolin Chene2681a12014-03-27 19:06:59 +080088 dev_dbg(dev, "isr: Start of Rx word detected\n");
89
Nicolin Chen413312a2014-03-28 19:39:25 +080090 if (flags & FSL_SAI_CSR_SEF)
Nicolin Chene2681a12014-03-27 19:06:59 +080091 dev_warn(dev, "isr: Rx Frame sync error detected\n");
92
Nicolin Chen413312a2014-03-28 19:39:25 +080093 if (flags & FSL_SAI_CSR_FEF) {
Nicolin Chene2681a12014-03-27 19:06:59 +080094 dev_warn(dev, "isr: Receive overflow detected\n");
95 /* FIFO reset for safety */
96 xcsr |= FSL_SAI_CSR_FR;
97 }
98
Nicolin Chen413312a2014-03-28 19:39:25 +080099 if (flags & FSL_SAI_CSR_FWF)
Nicolin Chene2681a12014-03-27 19:06:59 +0800100 dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
101
Nicolin Chen413312a2014-03-28 19:39:25 +0800102 if (flags & FSL_SAI_CSR_FRF)
Nicolin Chene2681a12014-03-27 19:06:59 +0800103 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
104
Nicolin Chen413312a2014-03-28 19:39:25 +0800105 flags &= FSL_SAI_CSR_xF_W_MASK;
106 xcsr &= ~FSL_SAI_CSR_xF_MASK;
Nicolin Chene2681a12014-03-27 19:06:59 +0800107
Nicolin Chen413312a2014-03-28 19:39:25 +0800108 if (flags)
Nicolin Chen4800f882014-07-17 21:21:38 +0800109 regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr);
Nicolin Chen413312a2014-03-28 19:39:25 +0800110
111out:
112 if (irq_none)
113 return IRQ_NONE;
114 else
115 return IRQ_HANDLED;
Nicolin Chene2681a12014-03-27 19:06:59 +0800116}
117
Xiubo Li43550822013-12-17 11:24:38 +0800118static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
119 int clk_id, unsigned int freq, int fsl_dir)
120{
Xiubo Li43550822013-12-17 11:24:38 +0800121 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
Nicolin Chen2a266f82014-04-11 18:30:09 +0800122 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
123 u32 val_cr2 = 0;
Xiubo Li633ff8f2014-01-08 16:13:05 +0800124
Xiubo Li43550822013-12-17 11:24:38 +0800125 switch (clk_id) {
126 case FSL_SAI_CLK_BUS:
Xiubo Li43550822013-12-17 11:24:38 +0800127 val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
128 break;
129 case FSL_SAI_CLK_MAST1:
Xiubo Li43550822013-12-17 11:24:38 +0800130 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
131 break;
132 case FSL_SAI_CLK_MAST2:
Xiubo Li43550822013-12-17 11:24:38 +0800133 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
134 break;
135 case FSL_SAI_CLK_MAST3:
Xiubo Li43550822013-12-17 11:24:38 +0800136 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
137 break;
138 default:
139 return -EINVAL;
140 }
Xiubo Li633ff8f2014-01-08 16:13:05 +0800141
Nicolin Chen2a266f82014-04-11 18:30:09 +0800142 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
143 FSL_SAI_CR2_MSEL_MASK, val_cr2);
Xiubo Li43550822013-12-17 11:24:38 +0800144
145 return 0;
146}
147
148static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
149 int clk_id, unsigned int freq, int dir)
150{
Nicolin Chen4e3a99f2013-12-20 16:41:05 +0800151 int ret;
Xiubo Li43550822013-12-17 11:24:38 +0800152
153 if (dir == SND_SOC_CLOCK_IN)
154 return 0;
155
Xiubo Li43550822013-12-17 11:24:38 +0800156 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
157 FSL_FMT_TRANSMITTER);
158 if (ret) {
Nicolin Chen190af122013-12-20 16:41:04 +0800159 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
Xiubo Li78957fc2014-02-08 14:38:28 +0800160 return ret;
Xiubo Li43550822013-12-17 11:24:38 +0800161 }
162
163 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
164 FSL_FMT_RECEIVER);
Xiubo Li78957fc2014-02-08 14:38:28 +0800165 if (ret)
Nicolin Chen190af122013-12-20 16:41:04 +0800166 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
Xiubo Li43550822013-12-17 11:24:38 +0800167
Nicolin Chen1fb2d9d2013-12-20 16:41:00 +0800168 return ret;
Xiubo Li43550822013-12-17 11:24:38 +0800169}
170
171static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
172 unsigned int fmt, int fsl_dir)
173{
Xiubo Li43550822013-12-17 11:24:38 +0800174 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
Nicolin Chen2a266f82014-04-11 18:30:09 +0800175 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
176 u32 val_cr2 = 0, val_cr4 = 0;
Xiubo Li43550822013-12-17 11:24:38 +0800177
Nicolin Chen2a266f82014-04-11 18:30:09 +0800178 if (!sai->big_endian_data)
Xiubo Li72aa62b2013-12-31 15:33:22 +0800179 val_cr4 |= FSL_SAI_CR4_MF;
Xiubo Li43550822013-12-17 11:24:38 +0800180
Xiubo Li13cde092014-02-25 17:54:51 +0800181 /* DAI mode */
Xiubo Li43550822013-12-17 11:24:38 +0800182 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
183 case SND_SOC_DAIFMT_I2S:
Xiubo Lia3f7dcc2014-02-27 08:45:01 +0800184 /*
185 * Frame low, 1clk before data, one word length for frame sync,
186 * frame sync starts one serial clock cycle earlier,
187 * that is, together with the last bit of the previous
188 * data word.
189 */
Nicolin Chenef33bc32014-04-04 15:09:47 +0800190 val_cr2 |= FSL_SAI_CR2_BCP;
Xiubo Li13cde092014-02-25 17:54:51 +0800191 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
Xiubo Li43550822013-12-17 11:24:38 +0800192 break;
Xiubo Li13cde092014-02-25 17:54:51 +0800193 case SND_SOC_DAIFMT_LEFT_J:
Xiubo Lia3f7dcc2014-02-27 08:45:01 +0800194 /*
195 * Frame high, one word length for frame sync,
196 * frame sync asserts with the first bit of the frame.
197 */
Nicolin Chenef33bc32014-04-04 15:09:47 +0800198 val_cr2 |= FSL_SAI_CR2_BCP;
Xiubo Li13cde092014-02-25 17:54:51 +0800199 break;
Xiubo Lia3f7dcc2014-02-27 08:45:01 +0800200 case SND_SOC_DAIFMT_DSP_A:
201 /*
202 * Frame high, 1clk before data, one bit for frame sync,
203 * frame sync starts one serial clock cycle earlier,
204 * that is, together with the last bit of the previous
205 * data word.
206 */
Nicolin Chenef33bc32014-04-04 15:09:47 +0800207 val_cr2 |= FSL_SAI_CR2_BCP;
Xiubo Lia3f7dcc2014-02-27 08:45:01 +0800208 val_cr4 |= FSL_SAI_CR4_FSE;
209 sai->is_dsp_mode = true;
210 break;
211 case SND_SOC_DAIFMT_DSP_B:
212 /*
213 * Frame high, one bit for frame sync,
214 * frame sync asserts with the first bit of the frame.
215 */
Nicolin Chenef33bc32014-04-04 15:09:47 +0800216 val_cr2 |= FSL_SAI_CR2_BCP;
Xiubo Lia3f7dcc2014-02-27 08:45:01 +0800217 sai->is_dsp_mode = true;
218 break;
Xiubo Li13cde092014-02-25 17:54:51 +0800219 case SND_SOC_DAIFMT_RIGHT_J:
220 /* To be done */
Xiubo Li43550822013-12-17 11:24:38 +0800221 default:
222 return -EINVAL;
223 }
224
Xiubo Li13cde092014-02-25 17:54:51 +0800225 /* DAI clock inversion */
Xiubo Li43550822013-12-17 11:24:38 +0800226 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
227 case SND_SOC_DAIFMT_IB_IF:
Xiubo Li13cde092014-02-25 17:54:51 +0800228 /* Invert both clocks */
229 val_cr2 ^= FSL_SAI_CR2_BCP;
230 val_cr4 ^= FSL_SAI_CR4_FSP;
Xiubo Li43550822013-12-17 11:24:38 +0800231 break;
232 case SND_SOC_DAIFMT_IB_NF:
Xiubo Li13cde092014-02-25 17:54:51 +0800233 /* Invert bit clock */
234 val_cr2 ^= FSL_SAI_CR2_BCP;
Xiubo Li43550822013-12-17 11:24:38 +0800235 break;
236 case SND_SOC_DAIFMT_NB_IF:
Xiubo Li13cde092014-02-25 17:54:51 +0800237 /* Invert frame clock */
238 val_cr4 ^= FSL_SAI_CR4_FSP;
Xiubo Li43550822013-12-17 11:24:38 +0800239 break;
240 case SND_SOC_DAIFMT_NB_NF:
Xiubo Li13cde092014-02-25 17:54:51 +0800241 /* Nothing to do for both normal cases */
Xiubo Li43550822013-12-17 11:24:38 +0800242 break;
243 default:
244 return -EINVAL;
245 }
246
Xiubo Li13cde092014-02-25 17:54:51 +0800247 /* DAI clock master masks */
Xiubo Li43550822013-12-17 11:24:38 +0800248 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
249 case SND_SOC_DAIFMT_CBS_CFS:
250 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
251 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
252 break;
253 case SND_SOC_DAIFMT_CBM_CFM:
Xiubo Li43550822013-12-17 11:24:38 +0800254 break;
Xiubo Li13cde092014-02-25 17:54:51 +0800255 case SND_SOC_DAIFMT_CBS_CFM:
256 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
Xiubo Li13cde092014-02-25 17:54:51 +0800257 break;
258 case SND_SOC_DAIFMT_CBM_CFS:
Xiubo Li13cde092014-02-25 17:54:51 +0800259 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
260 break;
Xiubo Li43550822013-12-17 11:24:38 +0800261 default:
262 return -EINVAL;
263 }
264
Nicolin Chen2a266f82014-04-11 18:30:09 +0800265 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
266 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
267 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
268 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
269 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
Xiubo Li43550822013-12-17 11:24:38 +0800270
271 return 0;
272}
273
274static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
275{
Nicolin Chen4e3a99f2013-12-20 16:41:05 +0800276 int ret;
Xiubo Li43550822013-12-17 11:24:38 +0800277
Xiubo Li43550822013-12-17 11:24:38 +0800278 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
279 if (ret) {
Nicolin Chen190af122013-12-20 16:41:04 +0800280 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
Xiubo Li78957fc2014-02-08 14:38:28 +0800281 return ret;
Xiubo Li43550822013-12-17 11:24:38 +0800282 }
283
284 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
Xiubo Li78957fc2014-02-08 14:38:28 +0800285 if (ret)
Nicolin Chen190af122013-12-20 16:41:04 +0800286 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
Xiubo Li43550822013-12-17 11:24:38 +0800287
Nicolin Chen1fb2d9d2013-12-20 16:41:00 +0800288 return ret;
Xiubo Li43550822013-12-17 11:24:38 +0800289}
290
291static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
292 struct snd_pcm_hw_params *params,
293 struct snd_soc_dai *cpu_dai)
294{
Nicolin Chen4e3a99f2013-12-20 16:41:05 +0800295 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
Nicolin Chen2a266f82014-04-11 18:30:09 +0800296 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
Xiubo Li43550822013-12-17 11:24:38 +0800297 unsigned int channels = params_channels(params);
Nicolin Chen1d700302013-12-20 16:41:01 +0800298 u32 word_width = snd_pcm_format_width(params_format(params));
Nicolin Chen2a266f82014-04-11 18:30:09 +0800299 u32 val_cr4 = 0, val_cr5 = 0;
Xiubo Li43550822013-12-17 11:24:38 +0800300
Xiubo Lia3f7dcc2014-02-27 08:45:01 +0800301 if (!sai->is_dsp_mode)
302 val_cr4 |= FSL_SAI_CR4_SYWD(word_width);
303
Xiubo Li43550822013-12-17 11:24:38 +0800304 val_cr5 |= FSL_SAI_CR5_WNW(word_width);
305 val_cr5 |= FSL_SAI_CR5_W0W(word_width);
306
307 if (sai->big_endian_data)
Xiubo Li43550822013-12-17 11:24:38 +0800308 val_cr5 |= FSL_SAI_CR5_FBT(0);
Xiubo Li72aa62b2013-12-31 15:33:22 +0800309 else
310 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
Xiubo Li43550822013-12-17 11:24:38 +0800311
312 val_cr4 |= FSL_SAI_CR4_FRSZ(channels);
Xiubo Li43550822013-12-17 11:24:38 +0800313
Nicolin Chen2a266f82014-04-11 18:30:09 +0800314 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
315 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
316 val_cr4);
317 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx),
318 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
319 FSL_SAI_CR5_FBT_MASK, val_cr5);
320 regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
Xiubo Li43550822013-12-17 11:24:38 +0800321
322 return 0;
323}
324
325static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
326 struct snd_soc_dai *cpu_dai)
327{
328 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
Nicolin Chene6b39842014-04-01 11:17:06 +0800329 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
Nicolin Chenc44b56a2014-07-23 19:23:39 +0800330 u32 xcsr, count = 100;
Xiubo Li496a39d2013-12-31 15:33:21 +0800331
Xiubo Lia3f7dcc2014-02-27 08:45:01 +0800332 /*
333 * The transmitter bit clock and frame sync are to be
334 * used by both the transmitter and receiver.
335 */
Xiubo Li78957fc2014-02-08 14:38:28 +0800336 regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC,
337 ~FSL_SAI_CR2_SYNC);
338 regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
339 FSL_SAI_CR2_SYNC);
Xiubo Li496a39d2013-12-31 15:33:21 +0800340
Xiubo Lia3f7dcc2014-02-27 08:45:01 +0800341 /*
342 * It is recommended that the transmitter is the last enabled
343 * and the first disabled.
344 */
Xiubo Li43550822013-12-17 11:24:38 +0800345 switch (cmd) {
346 case SNDRV_PCM_TRIGGER_START:
347 case SNDRV_PCM_TRIGGER_RESUME:
348 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
Nicolin Chena3fdc672014-07-23 19:23:40 +0800349 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
350 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
351
Nicolin Chenf4075a82014-07-23 19:23:38 +0800352 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
353 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
354 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
355 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
Xiubo Lie5d0fa92013-12-25 12:40:04 +0800356
Nicolin Chene6b39842014-04-01 11:17:06 +0800357 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
Nicolin Chen8abba5d2014-04-01 11:17:07 +0800358 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
Xiubo Li43550822013-12-17 11:24:38 +0800359 break;
Xiubo Li43550822013-12-17 11:24:38 +0800360 case SNDRV_PCM_TRIGGER_STOP:
361 case SNDRV_PCM_TRIGGER_SUSPEND:
362 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
Nicolin Chene6b39842014-04-01 11:17:06 +0800363 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
364 FSL_SAI_CSR_FRDE, 0);
Nicolin Chen8abba5d2014-04-01 11:17:07 +0800365 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
366 FSL_SAI_CSR_xIE_MASK, 0);
Xiubo Lie5d0fa92013-12-25 12:40:04 +0800367
Nicolin Chenf84526c2014-04-11 22:10:00 +0800368 /* Check if the opposite FRDE is also disabled */
Nicolin Chenf4075a82014-07-23 19:23:38 +0800369 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr);
370 if (!(xcsr & FSL_SAI_CSR_FRDE)) {
Nicolin Cheneff952b2014-07-17 21:21:37 +0800371 /* Disable both directions and reset their FIFOs */
Nicolin Chene6b39842014-04-01 11:17:06 +0800372 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
Nicolin Chenc44b56a2014-07-23 19:23:39 +0800373 FSL_SAI_CSR_TERE, 0);
Nicolin Chene6b39842014-04-01 11:17:06 +0800374 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
Nicolin Chenc44b56a2014-07-23 19:23:39 +0800375 FSL_SAI_CSR_TERE, 0);
376
377 /* TERE will remain set till the end of current frame */
378 do {
379 udelay(10);
380 regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr);
381 } while (--count && xcsr & FSL_SAI_CSR_TERE);
382
383 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
384 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
385 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
386 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
Nicolin Chene6b39842014-04-01 11:17:06 +0800387 }
Xiubo Li43550822013-12-17 11:24:38 +0800388 break;
389 default:
390 return -EINVAL;
391 }
392
393 return 0;
394}
395
396static int fsl_sai_startup(struct snd_pcm_substream *substream,
397 struct snd_soc_dai *cpu_dai)
398{
Xiubo Li43550822013-12-17 11:24:38 +0800399 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
Nicolin Chen2a266f82014-04-11 18:30:09 +0800400 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
Nicolin Chenca3e35c2014-04-10 23:26:15 +0800401 struct device *dev = &sai->pdev->dev;
Nicolin Chenca3e35c2014-04-10 23:26:15 +0800402 int ret;
403
404 ret = clk_prepare_enable(sai->bus_clk);
405 if (ret) {
406 dev_err(dev, "failed to enable bus clock: %d\n", ret);
407 return ret;
408 }
Xiubo Li43550822013-12-17 11:24:38 +0800409
Nicolin Chen2a266f82014-04-11 18:30:09 +0800410 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE,
Xiubo Li78957fc2014-02-08 14:38:28 +0800411 FSL_SAI_CR3_TRCE);
412
413 return 0;
Xiubo Li43550822013-12-17 11:24:38 +0800414}
415
416static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
417 struct snd_soc_dai *cpu_dai)
418{
419 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
Nicolin Chen2a266f82014-04-11 18:30:09 +0800420 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
Xiubo Li43550822013-12-17 11:24:38 +0800421
Nicolin Chen2a266f82014-04-11 18:30:09 +0800422 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0);
Nicolin Chenca3e35c2014-04-10 23:26:15 +0800423
424 clk_disable_unprepare(sai->bus_clk);
Xiubo Li43550822013-12-17 11:24:38 +0800425}
426
427static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
428 .set_sysclk = fsl_sai_set_dai_sysclk,
429 .set_fmt = fsl_sai_set_dai_fmt,
430 .hw_params = fsl_sai_hw_params,
431 .trigger = fsl_sai_trigger,
432 .startup = fsl_sai_startup,
433 .shutdown = fsl_sai_shutdown,
434};
435
436static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
437{
438 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
Xiubo Lie6dc12d2013-12-25 11:20:14 +0800439
Nicolin Chen8abba5d2014-04-01 11:17:07 +0800440 regmap_update_bits(sai->regmap, FSL_SAI_TCSR, 0xffffffff, 0x0);
441 regmap_update_bits(sai->regmap, FSL_SAI_RCSR, 0xffffffff, 0x0);
Xiubo Li78957fc2014-02-08 14:38:28 +0800442 regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
443 FSL_SAI_MAXBURST_TX * 2);
444 regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,
445 FSL_SAI_MAXBURST_RX - 1);
Xiubo Li43550822013-12-17 11:24:38 +0800446
Xiubo Lidd9f4062013-12-20 12:35:33 +0800447 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
448 &sai->dma_params_rx);
Xiubo Li43550822013-12-17 11:24:38 +0800449
450 snd_soc_dai_set_drvdata(cpu_dai, sai);
451
452 return 0;
453}
454
Xiubo Li43550822013-12-17 11:24:38 +0800455static struct snd_soc_dai_driver fsl_sai_dai = {
456 .probe = fsl_sai_dai_probe,
Xiubo Li43550822013-12-17 11:24:38 +0800457 .playback = {
Nicolin Chen20d5b762014-07-30 11:10:27 +0800458 .stream_name = "CPU-Playback",
Xiubo Li43550822013-12-17 11:24:38 +0800459 .channels_min = 1,
460 .channels_max = 2,
461 .rates = SNDRV_PCM_RATE_8000_96000,
462 .formats = FSL_SAI_FORMATS,
463 },
464 .capture = {
Nicolin Chen20d5b762014-07-30 11:10:27 +0800465 .stream_name = "CPU-Capture",
Xiubo Li43550822013-12-17 11:24:38 +0800466 .channels_min = 1,
467 .channels_max = 2,
468 .rates = SNDRV_PCM_RATE_8000_96000,
469 .formats = FSL_SAI_FORMATS,
470 },
471 .ops = &fsl_sai_pcm_dai_ops,
472};
473
474static const struct snd_soc_component_driver fsl_component = {
475 .name = "fsl-sai",
476};
477
Xiubo Li78957fc2014-02-08 14:38:28 +0800478static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
479{
480 switch (reg) {
481 case FSL_SAI_TCSR:
482 case FSL_SAI_TCR1:
483 case FSL_SAI_TCR2:
484 case FSL_SAI_TCR3:
485 case FSL_SAI_TCR4:
486 case FSL_SAI_TCR5:
487 case FSL_SAI_TFR:
488 case FSL_SAI_TMR:
489 case FSL_SAI_RCSR:
490 case FSL_SAI_RCR1:
491 case FSL_SAI_RCR2:
492 case FSL_SAI_RCR3:
493 case FSL_SAI_RCR4:
494 case FSL_SAI_RCR5:
495 case FSL_SAI_RDR:
496 case FSL_SAI_RFR:
497 case FSL_SAI_RMR:
498 return true;
499 default:
500 return false;
501 }
502}
503
504static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
505{
506 switch (reg) {
507 case FSL_SAI_TFR:
508 case FSL_SAI_RFR:
509 case FSL_SAI_TDR:
510 case FSL_SAI_RDR:
511 return true;
512 default:
513 return false;
514 }
515
516}
517
518static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
519{
520 switch (reg) {
521 case FSL_SAI_TCSR:
522 case FSL_SAI_TCR1:
523 case FSL_SAI_TCR2:
524 case FSL_SAI_TCR3:
525 case FSL_SAI_TCR4:
526 case FSL_SAI_TCR5:
527 case FSL_SAI_TDR:
528 case FSL_SAI_TMR:
529 case FSL_SAI_RCSR:
530 case FSL_SAI_RCR1:
531 case FSL_SAI_RCR2:
532 case FSL_SAI_RCR3:
533 case FSL_SAI_RCR4:
534 case FSL_SAI_RCR5:
535 case FSL_SAI_RMR:
536 return true;
537 default:
538 return false;
539 }
540}
541
Xiubo Li014fd222014-08-25 11:31:02 +0800542static const struct regmap_config fsl_sai_regmap_config = {
Xiubo Li78957fc2014-02-08 14:38:28 +0800543 .reg_bits = 32,
544 .reg_stride = 4,
545 .val_bits = 32,
546
547 .max_register = FSL_SAI_RMR,
548 .readable_reg = fsl_sai_readable_reg,
549 .volatile_reg = fsl_sai_volatile_reg,
550 .writeable_reg = fsl_sai_writeable_reg,
551};
552
Xiubo Li43550822013-12-17 11:24:38 +0800553static int fsl_sai_probe(struct platform_device *pdev)
554{
Nicolin Chen4e3a99f2013-12-20 16:41:05 +0800555 struct device_node *np = pdev->dev.of_node;
Xiubo Li43550822013-12-17 11:24:38 +0800556 struct fsl_sai *sai;
557 struct resource *res;
Xiubo Li78957fc2014-02-08 14:38:28 +0800558 void __iomem *base;
Nicolin Chenca3e35c2014-04-10 23:26:15 +0800559 char tmp[8];
560 int irq, ret, i;
Xiubo Li43550822013-12-17 11:24:38 +0800561
562 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
563 if (!sai)
564 return -ENOMEM;
565
Nicolin Chene2681a12014-03-27 19:06:59 +0800566 sai->pdev = pdev;
567
Nicolin Chenc7540642014-04-01 19:34:09 +0800568 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai"))
569 sai->sai_on_imx = true;
570
Xiubo Li78957fc2014-02-08 14:38:28 +0800571 sai->big_endian_data = of_property_read_bool(np, "big-endian-data");
572
573 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
574 base = devm_ioremap_resource(&pdev->dev, res);
575 if (IS_ERR(base))
576 return PTR_ERR(base);
577
578 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
Nicolin Chenca3e35c2014-04-10 23:26:15 +0800579 "bus", base, &fsl_sai_regmap_config);
580
581 /* Compatible with old DTB cases */
582 if (IS_ERR(sai->regmap))
583 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
584 "sai", base, &fsl_sai_regmap_config);
Xiubo Li78957fc2014-02-08 14:38:28 +0800585 if (IS_ERR(sai->regmap)) {
586 dev_err(&pdev->dev, "regmap init failed\n");
587 return PTR_ERR(sai->regmap);
Xiubo Li43550822013-12-17 11:24:38 +0800588 }
589
Nicolin Chenca3e35c2014-04-10 23:26:15 +0800590 /* No error out for old DTB cases but only mark the clock NULL */
591 sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
592 if (IS_ERR(sai->bus_clk)) {
593 dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
594 PTR_ERR(sai->bus_clk));
595 sai->bus_clk = NULL;
596 }
597
598 for (i = 0; i < FSL_SAI_MCLK_MAX; i++) {
599 sprintf(tmp, "mclk%d", i + 1);
600 sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
601 if (IS_ERR(sai->mclk_clk[i])) {
602 dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
603 i + 1, PTR_ERR(sai->mclk_clk[i]));
604 sai->mclk_clk[i] = NULL;
605 }
606 }
607
Nicolin Chene2681a12014-03-27 19:06:59 +0800608 irq = platform_get_irq(pdev, 0);
609 if (irq < 0) {
610 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
611 return irq;
612 }
613
614 ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai);
615 if (ret) {
616 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
617 return ret;
618 }
619
Xiubo Li43550822013-12-17 11:24:38 +0800620 sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
621 sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
622 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
623 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
624
Xiubo Li43550822013-12-17 11:24:38 +0800625 platform_set_drvdata(pdev, sai);
626
627 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
628 &fsl_sai_dai, 1);
629 if (ret)
630 return ret;
631
Nicolin Chenc7540642014-04-01 19:34:09 +0800632 if (sai->sai_on_imx)
633 return imx_pcm_dma_init(pdev);
634 else
635 return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL,
636 SND_DMAENGINE_PCM_FLAG_NO_RESIDUE);
Xiubo Li43550822013-12-17 11:24:38 +0800637}
638
639static const struct of_device_id fsl_sai_ids[] = {
640 { .compatible = "fsl,vf610-sai", },
Nicolin Chenc7540642014-04-01 19:34:09 +0800641 { .compatible = "fsl,imx6sx-sai", },
Xiubo Li43550822013-12-17 11:24:38 +0800642 { /* sentinel */ }
643};
644
645static struct platform_driver fsl_sai_driver = {
646 .probe = fsl_sai_probe,
Xiubo Li43550822013-12-17 11:24:38 +0800647 .driver = {
648 .name = "fsl-sai",
649 .owner = THIS_MODULE,
650 .of_match_table = fsl_sai_ids,
651 },
652};
653module_platform_driver(fsl_sai_driver);
654
655MODULE_DESCRIPTION("Freescale Soc SAI Interface");
656MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
657MODULE_ALIAS("platform:fsl-sai");
658MODULE_LICENSE("GPL");