blob: 8d115db1e6510044dfe10fc0e87e949f517fca43 [file] [log] [blame]
Stephen Boyddd15ab82011-11-08 10:34:05 -08001/*
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -08002 *
3 * Copyright (C) 2007 Google, Inc.
Kumar Gala3f8e8ce2014-01-29 16:17:30 -06004 * Copyright (c) 2009-2012,2014, The Linux Foundation. All rights reserved.
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -08005 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
Stephen Boyd4a184072011-11-08 10:34:04 -080017#include <linux/clocksource.h>
18#include <linux/clockchips.h>
Stephen Boyd4d70c592013-02-15 17:31:31 -080019#include <linux/cpu.h>
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080020#include <linux/init.h>
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080021#include <linux/interrupt.h>
22#include <linux/irq.h>
Russell Kingfced80c2008-09-06 12:10:45 +010023#include <linux/io.h>
Stephen Boyd6e332162012-09-05 12:28:53 -070024#include <linux/of.h>
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
Stephen Boyd38ff87f2013-06-01 23:39:40 -070027#include <linux/sched_clock.h>
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080028
Stephen Boyd013be5a2014-05-13 16:01:00 -070029#include <asm/delay.h>
30
Stephen Boyde25e3d12013-03-14 20:31:39 -070031#define TIMER_MATCH_VAL 0x0000
32#define TIMER_COUNT_VAL 0x0004
33#define TIMER_ENABLE 0x0008
34#define TIMER_ENABLE_CLR_ON_MATCH_EN BIT(1)
35#define TIMER_ENABLE_EN BIT(0)
36#define TIMER_CLEAR 0x000C
37#define DGT_CLK_CTL 0x10
38#define DGT_CLK_CTL_DIV_4 0x3
39#define TIMER_STS_GPT0_CLR_PEND BIT(10)
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080040
41#define GPT_HZ 32768
Jeff Ohlstein672039f2010-10-05 15:23:57 -070042
Stephen Boyd2081a6b2011-11-08 10:34:08 -080043#define MSM_DGT_SHIFT 5
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080044
Stephen Boyd2a00c102011-11-08 10:34:07 -080045static void __iomem *event_base;
Stephen Boyde25e3d12013-03-14 20:31:39 -070046static void __iomem *sts_base;
Stephen Boyda850c3f2011-11-08 10:34:06 -080047
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080048static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
49{
Stephen Boyd4d70c592013-02-15 17:31:31 -080050 struct clock_event_device *evt = dev_id;
Stephen Boyda850c3f2011-11-08 10:34:06 -080051 /* Stop the timer tick */
52 if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
Stephen Boyd2a00c102011-11-08 10:34:07 -080053 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
Stephen Boyda850c3f2011-11-08 10:34:06 -080054 ctrl &= ~TIMER_ENABLE_EN;
Stephen Boyd2a00c102011-11-08 10:34:07 -080055 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
Stephen Boyda850c3f2011-11-08 10:34:06 -080056 }
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080057 evt->event_handler(evt);
58 return IRQ_HANDLED;
59}
60
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080061static int msm_timer_set_next_event(unsigned long cycles,
62 struct clock_event_device *evt)
63{
Stephen Boyd2a00c102011-11-08 10:34:07 -080064 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080065
Stephen Boyd4080d2d2013-03-14 20:31:37 -070066 ctrl &= ~TIMER_ENABLE_EN;
67 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
68
69 writel_relaxed(ctrl, event_base + TIMER_CLEAR);
Stephen Boyd2a00c102011-11-08 10:34:07 -080070 writel_relaxed(cycles, event_base + TIMER_MATCH_VAL);
Stephen Boyde25e3d12013-03-14 20:31:39 -070071
72 if (sts_base)
73 while (readl_relaxed(sts_base) & TIMER_STS_GPT0_CLR_PEND)
74 cpu_relax();
75
Stephen Boyd2a00c102011-11-08 10:34:07 -080076 writel_relaxed(ctrl | TIMER_ENABLE_EN, event_base + TIMER_ENABLE);
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080077 return 0;
78}
79
80static void msm_timer_set_mode(enum clock_event_mode mode,
81 struct clock_event_device *evt)
82{
Stephen Boyda850c3f2011-11-08 10:34:06 -080083 u32 ctrl;
84
Stephen Boyd2a00c102011-11-08 10:34:07 -080085 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
Stephen Boyda850c3f2011-11-08 10:34:06 -080086 ctrl &= ~(TIMER_ENABLE_EN | TIMER_ENABLE_CLR_ON_MATCH_EN);
Jeff Ohlstein94790ec2010-12-02 12:05:12 -080087
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080088 switch (mode) {
89 case CLOCK_EVT_MODE_RESUME:
90 case CLOCK_EVT_MODE_PERIODIC:
91 break;
92 case CLOCK_EVT_MODE_ONESHOT:
Stephen Boyda850c3f2011-11-08 10:34:06 -080093 /* Timer is enabled in set_next_event */
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080094 break;
95 case CLOCK_EVT_MODE_UNUSED:
96 case CLOCK_EVT_MODE_SHUTDOWN:
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -080097 break;
98 }
Stephen Boyd2a00c102011-11-08 10:34:07 -080099 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -0800100}
101
Stephen Boyd4d70c592013-02-15 17:31:31 -0800102static struct clock_event_device __percpu *msm_evt;
Stephen Boyd2a00c102011-11-08 10:34:07 -0800103
104static void __iomem *source_base;
105
Stephen Boydf8e56c42012-02-22 01:39:37 +0000106static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
Stephen Boyd2a00c102011-11-08 10:34:07 -0800107{
Stephen Boyd2081a6b2011-11-08 10:34:08 -0800108 return readl_relaxed(source_base + TIMER_COUNT_VAL);
109}
110
Stephen Boyd2a00c102011-11-08 10:34:07 -0800111static struct clocksource msm_clocksource = {
112 .name = "dg_timer",
113 .rating = 300,
114 .read = msm_read_timer_count,
Stephen Boyd2081a6b2011-11-08 10:34:08 -0800115 .mask = CLOCKSOURCE_MASK(32),
Stephen Boyd2a00c102011-11-08 10:34:07 -0800116 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -0800117};
118
Stephen Boyd4d70c592013-02-15 17:31:31 -0800119static int msm_timer_irq;
120static int msm_timer_has_ppi;
121
Paul Gortmaker8bd26e32013-06-17 15:43:14 -0400122static int msm_local_timer_setup(struct clock_event_device *evt)
Marc Zyngier5ca709c2012-01-10 19:44:19 +0000123{
Stephen Boyd4d70c592013-02-15 17:31:31 -0800124 int cpu = smp_processor_id();
125 int err;
Marc Zyngier5ca709c2012-01-10 19:44:19 +0000126
Stephen Boyd4d70c592013-02-15 17:31:31 -0800127 evt->irq = msm_timer_irq;
128 evt->name = "msm_timer";
129 evt->features = CLOCK_EVT_FEAT_ONESHOT;
130 evt->rating = 200;
Marc Zyngier5ca709c2012-01-10 19:44:19 +0000131 evt->set_mode = msm_timer_set_mode;
132 evt->set_next_event = msm_timer_set_next_event;
Stephen Boyd4d70c592013-02-15 17:31:31 -0800133 evt->cpumask = cpumask_of(cpu);
Marc Zyngier5ca709c2012-01-10 19:44:19 +0000134
Stephen Boyd4d70c592013-02-15 17:31:31 -0800135 clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
136
137 if (msm_timer_has_ppi) {
138 enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
139 } else {
140 err = request_irq(evt->irq, msm_timer_interrupt,
141 IRQF_TIMER | IRQF_NOBALANCING |
142 IRQF_TRIGGER_RISING, "gp_timer", evt);
143 if (err)
144 pr_err("request_irq failed\n");
145 }
146
Marc Zyngier5ca709c2012-01-10 19:44:19 +0000147 return 0;
148}
149
150static void msm_local_timer_stop(struct clock_event_device *evt)
151{
152 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
153 disable_percpu_irq(evt->irq);
154}
155
Olof Johansson47dcd352013-07-23 14:51:34 -0700156static int msm_timer_cpu_notify(struct notifier_block *self,
Stephen Boyd4d70c592013-02-15 17:31:31 -0800157 unsigned long action, void *hcpu)
158{
159 /*
160 * Grab cpu pointer in each case to avoid spurious
161 * preemptible warnings
162 */
163 switch (action & ~CPU_TASKS_FROZEN) {
164 case CPU_STARTING:
165 msm_local_timer_setup(this_cpu_ptr(msm_evt));
166 break;
167 case CPU_DYING:
168 msm_local_timer_stop(this_cpu_ptr(msm_evt));
169 break;
170 }
171
172 return NOTIFY_OK;
173}
174
Olof Johansson47dcd352013-07-23 14:51:34 -0700175static struct notifier_block msm_timer_cpu_nb = {
Stephen Boyd4d70c592013-02-15 17:31:31 -0800176 .notifier_call = msm_timer_cpu_notify,
Marc Zyngier5ca709c2012-01-10 19:44:19 +0000177};
Marc Zyngier5ca709c2012-01-10 19:44:19 +0000178
Stephen Boyd6aa16a22013-11-15 15:26:16 -0800179static u64 notrace msm_sched_clock_read(void)
Stephen Boydf8e56c42012-02-22 01:39:37 +0000180{
181 return msm_clocksource.read(&msm_clocksource);
182}
183
Stephen Boyd013be5a2014-05-13 16:01:00 -0700184static unsigned long msm_read_current_timer(void)
185{
186 return msm_clocksource.read(&msm_clocksource);
187}
188
189static struct delay_timer msm_delay_timer = {
190 .read_current_timer = msm_read_current_timer,
191};
192
Stephen Boyd4312a7e2012-09-05 12:28:52 -0700193static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
194 bool percpu)
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -0800195{
Stephen Boyd2a00c102011-11-08 10:34:07 -0800196 struct clocksource *cs = &msm_clocksource;
Stephen Boyd4d70c592013-02-15 17:31:31 -0800197 int res = 0;
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -0800198
Stephen Boyd4d70c592013-02-15 17:31:31 -0800199 msm_timer_irq = irq;
200 msm_timer_has_ppi = percpu;
David Brown8c27e6f2011-01-07 10:20:49 -0800201
Stephen Boyd4d70c592013-02-15 17:31:31 -0800202 msm_evt = alloc_percpu(struct clock_event_device);
203 if (!msm_evt) {
204 pr_err("memory allocation failed for clockevents\n");
205 goto err;
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -0800206 }
Stephen Boyddd15ab82011-11-08 10:34:05 -0800207
Stephen Boyd4d70c592013-02-15 17:31:31 -0800208 if (percpu)
209 res = request_percpu_irq(irq, msm_timer_interrupt,
210 "gp_timer", msm_evt);
211
212 if (res) {
213 pr_err("request_percpu_irq failed\n");
214 } else {
215 res = register_cpu_notifier(&msm_timer_cpu_nb);
216 if (res) {
217 free_percpu_irq(irq, msm_evt);
218 goto err;
219 }
220
221 /* Immediately configure the timer on the boot CPU */
222 msm_local_timer_setup(__this_cpu_ptr(msm_evt));
223 }
224
Stephen Boyddd15ab82011-11-08 10:34:05 -0800225err:
Stephen Boyd2a00c102011-11-08 10:34:07 -0800226 writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
Stephen Boyd2081a6b2011-11-08 10:34:08 -0800227 res = clocksource_register_hz(cs, dgt_hz);
Stephen Boyddd15ab82011-11-08 10:34:05 -0800228 if (res)
Stephen Boyd2a00c102011-11-08 10:34:07 -0800229 pr_err("clocksource_register failed\n");
Stephen Boyd6aa16a22013-11-15 15:26:16 -0800230 sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
Stephen Boyd013be5a2014-05-13 16:01:00 -0700231 msm_delay_timer.freq = dgt_hz;
232 register_current_timer_delay(&msm_delay_timer);
Arve Hjønnevåg3e4ea372007-11-26 04:11:58 -0800233}
234
Kumar Gala7d6d45f2014-01-29 17:01:37 -0600235#ifdef CONFIG_ARCH_QCOM
Stephen Boydc6025202013-07-24 13:54:30 -0700236static void __init msm_dt_timer_init(struct device_node *np)
Stephen Boyd6e332162012-09-05 12:28:53 -0700237{
Stephen Boyd6e332162012-09-05 12:28:53 -0700238 u32 freq;
239 int irq;
240 struct resource res;
241 u32 percpu_offset;
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700242 void __iomem *base;
243 void __iomem *cpu0_base;
Stephen Boyd6e332162012-09-05 12:28:53 -0700244
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700245 base = of_iomap(np, 0);
246 if (!base) {
Stephen Boyd6e332162012-09-05 12:28:53 -0700247 pr_err("Failed to map event base\n");
248 return;
249 }
250
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700251 /* We use GPT0 for the clockevent */
252 irq = irq_of_parse_and_map(np, 1);
Stephen Boyd6e332162012-09-05 12:28:53 -0700253 if (irq <= 0) {
254 pr_err("Can't get irq\n");
255 return;
256 }
Stephen Boyd6e332162012-09-05 12:28:53 -0700257
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700258 /* We use CPU0's DGT for the clocksource */
Stephen Boyd6e332162012-09-05 12:28:53 -0700259 if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
260 percpu_offset = 0;
261
262 if (of_address_to_resource(np, 0, &res)) {
263 pr_err("Failed to parse DGT resource\n");
264 return;
265 }
266
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700267 cpu0_base = ioremap(res.start + percpu_offset, resource_size(&res));
268 if (!cpu0_base) {
Stephen Boyd6e332162012-09-05 12:28:53 -0700269 pr_err("Failed to map source base\n");
270 return;
271 }
272
Stephen Boyd6e332162012-09-05 12:28:53 -0700273 if (of_property_read_u32(np, "clock-frequency", &freq)) {
274 pr_err("Unknown frequency\n");
275 return;
276 }
Stephen Boyd6e332162012-09-05 12:28:53 -0700277
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700278 event_base = base + 0x4;
Stephen Boyde25e3d12013-03-14 20:31:39 -0700279 sts_base = base + 0x88;
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700280 source_base = cpu0_base + 0x24;
281 freq /= 4;
282 writel_relaxed(DGT_CLK_CTL_DIV_4, source_base + DGT_CLK_CTL);
283
Stephen Boyd6e332162012-09-05 12:28:53 -0700284 msm_timer_init(freq, 32, irq, !!percpu_offset);
285}
Stephen Boydc6025202013-07-24 13:54:30 -0700286CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
287CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
Kumar Gala7d6d45f2014-01-29 17:01:37 -0600288#else
Stephen Boyd6e332162012-09-05 12:28:53 -0700289
Stephen Boyde25e3d12013-03-14 20:31:39 -0700290static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
291 u32 sts)
Stephen Boyd4312a7e2012-09-05 12:28:52 -0700292{
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700293 void __iomem *base;
294
295 base = ioremap(addr, SZ_256);
296 if (!base) {
297 pr_err("Failed to map timer base\n");
298 return -ENOMEM;
Stephen Boyd4312a7e2012-09-05 12:28:52 -0700299 }
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700300 event_base = base + event;
301 source_base = base + source;
Stephen Boyde25e3d12013-03-14 20:31:39 -0700302 if (sts)
303 sts_base = base + sts;
Stephen Boydeebdb0c2013-03-14 20:31:38 -0700304
Stephen Boyd4312a7e2012-09-05 12:28:52 -0700305 return 0;
306}
307
Kumar Gala7d6d45f2014-01-29 17:01:37 -0600308static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
309{
310 /*
311 * Shift timer count down by a constant due to unreliable lower bits
312 * on some targets.
313 */
314 return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
315}
316
Stephen Warren6bb27d72012-11-08 12:40:59 -0700317void __init msm7x01_timer_init(void)
Stephen Boyd4312a7e2012-09-05 12:28:52 -0700318{
319 struct clocksource *cs = &msm_clocksource;
320
Stephen Boyde25e3d12013-03-14 20:31:39 -0700321 if (msm_timer_map(0xc0100000, 0x0, 0x10, 0x0))
Stephen Boyd4312a7e2012-09-05 12:28:52 -0700322 return;
323 cs->read = msm_read_timer_count_shift;
324 cs->mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT));
325 /* 600 KHz */
326 msm_timer_init(19200000 >> MSM_DGT_SHIFT, 32 - MSM_DGT_SHIFT, 7,
327 false);
328}
329
Stephen Warren6bb27d72012-11-08 12:40:59 -0700330void __init msm7x30_timer_init(void)
Stephen Boyd4312a7e2012-09-05 12:28:52 -0700331{
Stephen Boyde25e3d12013-03-14 20:31:39 -0700332 if (msm_timer_map(0xc0100000, 0x4, 0x24, 0x80))
Stephen Boyd4312a7e2012-09-05 12:28:52 -0700333 return;
334 msm_timer_init(24576000 / 4, 32, 1, false);
335}
336
Stephen Warren6bb27d72012-11-08 12:40:59 -0700337void __init qsd8x50_timer_init(void)
Stephen Boyd4312a7e2012-09-05 12:28:52 -0700338{
Stephen Boyde25e3d12013-03-14 20:31:39 -0700339 if (msm_timer_map(0xAC100000, 0x0, 0x10, 0x34))
Stephen Boyd4312a7e2012-09-05 12:28:52 -0700340 return;
341 msm_timer_init(19200000 / 4, 32, 7, false);
342}
Kumar Gala7d6d45f2014-01-29 17:01:37 -0600343#endif