Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1 | /* |
Pierre Ossman | 70f1048 | 2007-07-11 20:04:50 +0200 | [diff] [blame] | 2 | * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3 | * |
Pierre Ossman | b69c905 | 2008-03-08 23:44:25 +0100 | [diff] [blame] | 4 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
Pierre Ossman | 643f720 | 2006-09-30 23:27:52 -0700 | [diff] [blame] | 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or (at |
| 9 | * your option) any later version. |
Pierre Ossman | 84c46a5 | 2007-12-02 19:58:16 +0100 | [diff] [blame] | 10 | * |
| 11 | * Thanks to the following companies for their support: |
| 12 | * |
| 13 | * - JMicron (hardware and technical support) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 14 | */ |
| 15 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 16 | #include <linux/delay.h> |
| 17 | #include <linux/highmem.h> |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 18 | #include <linux/io.h> |
Paul Gortmaker | 88b4767 | 2011-07-03 15:15:51 -0400 | [diff] [blame] | 19 | #include <linux/module.h> |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 20 | #include <linux/dma-mapping.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 21 | #include <linux/slab.h> |
Ralf Baechle | 1176360 | 2007-10-23 20:42:11 +0200 | [diff] [blame] | 22 | #include <linux/scatterlist.h> |
Marek Szyprowski | 9bea3c8 | 2010-08-10 18:01:59 -0700 | [diff] [blame] | 23 | #include <linux/regulator/consumer.h> |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 24 | #include <linux/pm_runtime.h> |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 25 | |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 26 | #include <linux/leds.h> |
| 27 | |
Aries Lee | 22113ef | 2010-12-15 08:14:24 +0100 | [diff] [blame] | 28 | #include <linux/mmc/mmc.h> |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 29 | #include <linux/mmc/host.h> |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 30 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 31 | #include "sdhci.h" |
| 32 | |
| 33 | #define DRIVER_NAME "sdhci" |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 34 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 35 | #define DBG(f, x...) \ |
Russell King | c656317 | 2006-03-29 09:30:20 +0100 | [diff] [blame] | 36 | pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 37 | |
Pierre Ossman | f913431 | 2008-12-21 17:01:48 +0100 | [diff] [blame] | 38 | #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \ |
| 39 | defined(CONFIG_MMC_SDHCI_MODULE)) |
| 40 | #define SDHCI_USE_LEDS_CLASS |
| 41 | #endif |
| 42 | |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 43 | #define MAX_TUNING_LOOP 40 |
| 44 | |
Pierre Ossman | df673b2 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 45 | static unsigned int debug_quirks = 0; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 46 | static unsigned int debug_quirks2; |
Pierre Ossman | 6743527 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 47 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 48 | static void sdhci_finish_data(struct sdhci_host *); |
| 49 | |
| 50 | static void sdhci_send_command(struct sdhci_host *, struct mmc_command *); |
| 51 | static void sdhci_finish_command(struct sdhci_host *); |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 52 | static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 53 | static void sdhci_tuning_timer(unsigned long data); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 54 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 55 | #ifdef CONFIG_PM_RUNTIME |
| 56 | static int sdhci_runtime_pm_get(struct sdhci_host *host); |
| 57 | static int sdhci_runtime_pm_put(struct sdhci_host *host); |
| 58 | #else |
| 59 | static inline int sdhci_runtime_pm_get(struct sdhci_host *host) |
| 60 | { |
| 61 | return 0; |
| 62 | } |
| 63 | static inline int sdhci_runtime_pm_put(struct sdhci_host *host) |
| 64 | { |
| 65 | return 0; |
| 66 | } |
| 67 | #endif |
| 68 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 69 | static void sdhci_dumpregs(struct sdhci_host *host) |
| 70 | { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 71 | pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", |
Philip Rakity | 412ab65 | 2010-09-22 15:25:13 -0700 | [diff] [blame] | 72 | mmc_hostname(host->mmc)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 73 | |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 74 | pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 75 | sdhci_readl(host, SDHCI_DMA_ADDRESS), |
| 76 | sdhci_readw(host, SDHCI_HOST_VERSION)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 77 | pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 78 | sdhci_readw(host, SDHCI_BLOCK_SIZE), |
| 79 | sdhci_readw(host, SDHCI_BLOCK_COUNT)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 80 | pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 81 | sdhci_readl(host, SDHCI_ARGUMENT), |
| 82 | sdhci_readw(host, SDHCI_TRANSFER_MODE)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 83 | pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 84 | sdhci_readl(host, SDHCI_PRESENT_STATE), |
| 85 | sdhci_readb(host, SDHCI_HOST_CONTROL)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 86 | pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 87 | sdhci_readb(host, SDHCI_POWER_CONTROL), |
| 88 | sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 89 | pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 90 | sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), |
| 91 | sdhci_readw(host, SDHCI_CLOCK_CONTROL)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 92 | pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 93 | sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), |
| 94 | sdhci_readl(host, SDHCI_INT_STATUS)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 95 | pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 96 | sdhci_readl(host, SDHCI_INT_ENABLE), |
| 97 | sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 98 | pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 99 | sdhci_readw(host, SDHCI_ACMD12_ERR), |
| 100 | sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 101 | pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 102 | sdhci_readl(host, SDHCI_CAPABILITIES), |
Philip Rakity | e8120ad | 2010-11-30 00:55:23 -0500 | [diff] [blame] | 103 | sdhci_readl(host, SDHCI_CAPABILITIES_1)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 104 | pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", |
Philip Rakity | e8120ad | 2010-11-30 00:55:23 -0500 | [diff] [blame] | 105 | sdhci_readw(host, SDHCI_COMMAND), |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 106 | sdhci_readl(host, SDHCI_MAX_CURRENT)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 107 | pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n", |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 108 | sdhci_readw(host, SDHCI_HOST_CONTROL2)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 109 | |
Ben Dooks | be3f4ae | 2009-06-08 23:33:52 +0100 | [diff] [blame] | 110 | if (host->flags & SDHCI_USE_ADMA) |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 111 | pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", |
Ben Dooks | be3f4ae | 2009-06-08 23:33:52 +0100 | [diff] [blame] | 112 | readl(host->ioaddr + SDHCI_ADMA_ERROR), |
| 113 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); |
| 114 | |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 115 | pr_debug(DRIVER_NAME ": ===========================================\n"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 116 | } |
| 117 | |
| 118 | /*****************************************************************************\ |
| 119 | * * |
| 120 | * Low level functions * |
| 121 | * * |
| 122 | \*****************************************************************************/ |
| 123 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 124 | static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) |
| 125 | { |
| 126 | u32 ier; |
| 127 | |
| 128 | ier = sdhci_readl(host, SDHCI_INT_ENABLE); |
| 129 | ier &= ~clear; |
| 130 | ier |= set; |
| 131 | sdhci_writel(host, ier, SDHCI_INT_ENABLE); |
| 132 | sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); |
| 133 | } |
| 134 | |
| 135 | static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs) |
| 136 | { |
| 137 | sdhci_clear_set_irqs(host, 0, irqs); |
| 138 | } |
| 139 | |
| 140 | static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs) |
| 141 | { |
| 142 | sdhci_clear_set_irqs(host, irqs, 0); |
| 143 | } |
| 144 | |
| 145 | static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) |
| 146 | { |
Shawn Guo | d25928d | 2011-06-21 22:41:48 +0800 | [diff] [blame] | 147 | u32 present, irqs; |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 148 | |
Adrian Hunter | c79396c | 2011-12-27 15:48:42 +0200 | [diff] [blame] | 149 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || |
Daniel Drake | 87b87a3 | 2012-04-10 00:14:20 +0100 | [diff] [blame] | 150 | (host->mmc->caps & MMC_CAP_NONREMOVABLE)) |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 151 | return; |
| 152 | |
Shawn Guo | d25928d | 2011-06-21 22:41:48 +0800 | [diff] [blame] | 153 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & |
| 154 | SDHCI_CARD_PRESENT; |
| 155 | irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT; |
| 156 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 157 | if (enable) |
| 158 | sdhci_unmask_irqs(host, irqs); |
| 159 | else |
| 160 | sdhci_mask_irqs(host, irqs); |
| 161 | } |
| 162 | |
| 163 | static void sdhci_enable_card_detection(struct sdhci_host *host) |
| 164 | { |
| 165 | sdhci_set_card_detection(host, true); |
| 166 | } |
| 167 | |
| 168 | static void sdhci_disable_card_detection(struct sdhci_host *host) |
| 169 | { |
| 170 | sdhci_set_card_detection(host, false); |
| 171 | } |
| 172 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 173 | static void sdhci_reset(struct sdhci_host *host, u8 mask) |
| 174 | { |
Pierre Ossman | e16514d8 | 2006-06-30 02:22:24 -0700 | [diff] [blame] | 175 | unsigned long timeout; |
Anton Vorontsov | 063a9db | 2009-03-17 00:14:02 +0300 | [diff] [blame] | 176 | u32 uninitialized_var(ier); |
Pierre Ossman | e16514d8 | 2006-06-30 02:22:24 -0700 | [diff] [blame] | 177 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 178 | if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 179 | if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & |
Pierre Ossman | 8a4da14 | 2006-10-04 02:15:40 -0700 | [diff] [blame] | 180 | SDHCI_CARD_PRESENT)) |
| 181 | return; |
| 182 | } |
| 183 | |
Anton Vorontsov | 063a9db | 2009-03-17 00:14:02 +0300 | [diff] [blame] | 184 | if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) |
| 185 | ier = sdhci_readl(host, SDHCI_INT_ENABLE); |
| 186 | |
Philip Rakity | 393c1a3 | 2011-01-21 11:26:40 -0800 | [diff] [blame] | 187 | if (host->ops->platform_reset_enter) |
| 188 | host->ops->platform_reset_enter(host, mask); |
| 189 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 190 | sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 191 | |
Pierre Ossman | e16514d8 | 2006-06-30 02:22:24 -0700 | [diff] [blame] | 192 | if (mask & SDHCI_RESET_ALL) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 193 | host->clock = 0; |
| 194 | |
Pierre Ossman | e16514d8 | 2006-06-30 02:22:24 -0700 | [diff] [blame] | 195 | /* Wait max 100 ms */ |
| 196 | timeout = 100; |
| 197 | |
| 198 | /* hw clears the bit when it's done */ |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 199 | while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { |
Pierre Ossman | e16514d8 | 2006-06-30 02:22:24 -0700 | [diff] [blame] | 200 | if (timeout == 0) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 201 | pr_err("%s: Reset 0x%x never completed.\n", |
Pierre Ossman | e16514d8 | 2006-06-30 02:22:24 -0700 | [diff] [blame] | 202 | mmc_hostname(host->mmc), (int)mask); |
| 203 | sdhci_dumpregs(host); |
| 204 | return; |
| 205 | } |
| 206 | timeout--; |
| 207 | mdelay(1); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 208 | } |
Anton Vorontsov | 063a9db | 2009-03-17 00:14:02 +0300 | [diff] [blame] | 209 | |
Philip Rakity | 393c1a3 | 2011-01-21 11:26:40 -0800 | [diff] [blame] | 210 | if (host->ops->platform_reset_exit) |
| 211 | host->ops->platform_reset_exit(host, mask); |
| 212 | |
Anton Vorontsov | 063a9db | 2009-03-17 00:14:02 +0300 | [diff] [blame] | 213 | if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET) |
| 214 | sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier); |
Shaohui Xie | 3abc1e80 | 2011-12-29 16:33:00 +0800 | [diff] [blame] | 215 | |
| 216 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
| 217 | if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL)) |
| 218 | host->ops->enable_dma(host); |
| 219 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 220 | } |
| 221 | |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 222 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); |
| 223 | |
| 224 | static void sdhci_init(struct sdhci_host *host, int soft) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 225 | { |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 226 | if (soft) |
| 227 | sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); |
| 228 | else |
| 229 | sdhci_reset(host, SDHCI_RESET_ALL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 230 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 231 | sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, |
| 232 | SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | |
Pierre Ossman | 3192a28 | 2006-06-30 02:22:26 -0700 | [diff] [blame] | 233 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | |
| 234 | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | |
Anton Vorontsov | 6aa943a | 2009-03-17 00:13:50 +0300 | [diff] [blame] | 235 | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE); |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 236 | |
| 237 | if (soft) { |
| 238 | /* force clock reconfiguration */ |
| 239 | host->clock = 0; |
| 240 | sdhci_set_ios(host->mmc, &host->mmc->ios); |
| 241 | } |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 242 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 243 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 244 | static void sdhci_reinit(struct sdhci_host *host) |
| 245 | { |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 246 | sdhci_init(host, 0); |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 247 | sdhci_enable_card_detection(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 248 | } |
| 249 | |
| 250 | static void sdhci_activate_led(struct sdhci_host *host) |
| 251 | { |
| 252 | u8 ctrl; |
| 253 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 254 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 255 | ctrl |= SDHCI_CTRL_LED; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 256 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 257 | } |
| 258 | |
| 259 | static void sdhci_deactivate_led(struct sdhci_host *host) |
| 260 | { |
| 261 | u8 ctrl; |
| 262 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 263 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 264 | ctrl &= ~SDHCI_CTRL_LED; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 265 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 266 | } |
| 267 | |
Pierre Ossman | f913431 | 2008-12-21 17:01:48 +0100 | [diff] [blame] | 268 | #ifdef SDHCI_USE_LEDS_CLASS |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 269 | static void sdhci_led_control(struct led_classdev *led, |
| 270 | enum led_brightness brightness) |
| 271 | { |
| 272 | struct sdhci_host *host = container_of(led, struct sdhci_host, led); |
| 273 | unsigned long flags; |
| 274 | |
| 275 | spin_lock_irqsave(&host->lock, flags); |
| 276 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 277 | if (host->runtime_suspended) |
| 278 | goto out; |
| 279 | |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 280 | if (brightness == LED_OFF) |
| 281 | sdhci_deactivate_led(host); |
| 282 | else |
| 283 | sdhci_activate_led(host); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 284 | out: |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 285 | spin_unlock_irqrestore(&host->lock, flags); |
| 286 | } |
| 287 | #endif |
| 288 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 289 | /*****************************************************************************\ |
| 290 | * * |
| 291 | * Core functions * |
| 292 | * * |
| 293 | \*****************************************************************************/ |
| 294 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 295 | static void sdhci_read_block_pio(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 296 | { |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 297 | unsigned long flags; |
| 298 | size_t blksize, len, chunk; |
Steven Noonan | 7244b85 | 2008-10-01 01:50:25 -0700 | [diff] [blame] | 299 | u32 uninitialized_var(scratch); |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 300 | u8 *buf; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 301 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 302 | DBG("PIO reading\n"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 303 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 304 | blksize = host->data->blksz; |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 305 | chunk = 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 306 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 307 | local_irq_save(flags); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 308 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 309 | while (blksize) { |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 310 | if (!sg_miter_next(&host->sg_miter)) |
| 311 | BUG(); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 312 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 313 | len = min(host->sg_miter.length, blksize); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 314 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 315 | blksize -= len; |
| 316 | host->sg_miter.consumed = len; |
Alex Dubov | 14d836e | 2007-04-13 19:04:38 +0200 | [diff] [blame] | 317 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 318 | buf = host->sg_miter.addr; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 319 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 320 | while (len) { |
| 321 | if (chunk == 0) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 322 | scratch = sdhci_readl(host, SDHCI_BUFFER); |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 323 | chunk = 4; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 324 | } |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 325 | |
| 326 | *buf = scratch & 0xFF; |
| 327 | |
| 328 | buf++; |
| 329 | scratch >>= 8; |
| 330 | chunk--; |
| 331 | len--; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 332 | } |
| 333 | } |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 334 | |
| 335 | sg_miter_stop(&host->sg_miter); |
| 336 | |
| 337 | local_irq_restore(flags); |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 338 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 339 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 340 | static void sdhci_write_block_pio(struct sdhci_host *host) |
| 341 | { |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 342 | unsigned long flags; |
| 343 | size_t blksize, len, chunk; |
| 344 | u32 scratch; |
| 345 | u8 *buf; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 346 | |
| 347 | DBG("PIO writing\n"); |
| 348 | |
| 349 | blksize = host->data->blksz; |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 350 | chunk = 0; |
| 351 | scratch = 0; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 352 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 353 | local_irq_save(flags); |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 354 | |
| 355 | while (blksize) { |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 356 | if (!sg_miter_next(&host->sg_miter)) |
| 357 | BUG(); |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 358 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 359 | len = min(host->sg_miter.length, blksize); |
Alex Dubov | 14d836e | 2007-04-13 19:04:38 +0200 | [diff] [blame] | 360 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 361 | blksize -= len; |
| 362 | host->sg_miter.consumed = len; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 363 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 364 | buf = host->sg_miter.addr; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 365 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 366 | while (len) { |
| 367 | scratch |= (u32)*buf << (chunk * 8); |
| 368 | |
| 369 | buf++; |
| 370 | chunk++; |
| 371 | len--; |
| 372 | |
| 373 | if ((chunk == 4) || ((len == 0) && (blksize == 0))) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 374 | sdhci_writel(host, scratch, SDHCI_BUFFER); |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 375 | chunk = 0; |
| 376 | scratch = 0; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 377 | } |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 378 | } |
| 379 | } |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 380 | |
| 381 | sg_miter_stop(&host->sg_miter); |
| 382 | |
| 383 | local_irq_restore(flags); |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 384 | } |
| 385 | |
| 386 | static void sdhci_transfer_pio(struct sdhci_host *host) |
| 387 | { |
| 388 | u32 mask; |
| 389 | |
| 390 | BUG_ON(!host->data); |
| 391 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 392 | if (host->blocks == 0) |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 393 | return; |
| 394 | |
| 395 | if (host->data->flags & MMC_DATA_READ) |
| 396 | mask = SDHCI_DATA_AVAILABLE; |
| 397 | else |
| 398 | mask = SDHCI_SPACE_AVAILABLE; |
| 399 | |
Pierre Ossman | 4a3cba3 | 2008-07-29 00:11:16 +0200 | [diff] [blame] | 400 | /* |
| 401 | * Some controllers (JMicron JMB38x) mess up the buffer bits |
| 402 | * for transfers < 4 bytes. As long as it is just one block, |
| 403 | * we can ignore the bits. |
| 404 | */ |
| 405 | if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && |
| 406 | (host->data->blocks == 1)) |
| 407 | mask = ~0; |
| 408 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 409 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
Anton Vorontsov | 3e3bf20 | 2009-03-17 00:14:00 +0300 | [diff] [blame] | 410 | if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) |
| 411 | udelay(100); |
| 412 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 413 | if (host->data->flags & MMC_DATA_READ) |
| 414 | sdhci_read_block_pio(host); |
| 415 | else |
| 416 | sdhci_write_block_pio(host); |
| 417 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 418 | host->blocks--; |
| 419 | if (host->blocks == 0) |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 420 | break; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 421 | } |
| 422 | |
| 423 | DBG("PIO transfer complete.\n"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 424 | } |
| 425 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 426 | static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) |
| 427 | { |
| 428 | local_irq_save(*flags); |
Cong Wang | 482fce9 | 2011-11-27 13:27:00 +0800 | [diff] [blame] | 429 | return kmap_atomic(sg_page(sg)) + sg->offset; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 430 | } |
| 431 | |
| 432 | static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) |
| 433 | { |
Cong Wang | 482fce9 | 2011-11-27 13:27:00 +0800 | [diff] [blame] | 434 | kunmap_atomic(buffer); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 435 | local_irq_restore(*flags); |
| 436 | } |
| 437 | |
Ben Dooks | 118cd17 | 2010-03-05 13:43:26 -0800 | [diff] [blame] | 438 | static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd) |
| 439 | { |
Ben Dooks | 9e506f3 | 2010-03-05 13:43:29 -0800 | [diff] [blame] | 440 | __le32 *dataddr = (__le32 __force *)(desc + 4); |
| 441 | __le16 *cmdlen = (__le16 __force *)desc; |
Ben Dooks | 118cd17 | 2010-03-05 13:43:26 -0800 | [diff] [blame] | 442 | |
Ben Dooks | 9e506f3 | 2010-03-05 13:43:29 -0800 | [diff] [blame] | 443 | /* SDHCI specification says ADMA descriptors should be 4 byte |
| 444 | * aligned, so using 16 or 32bit operations should be safe. */ |
Ben Dooks | 118cd17 | 2010-03-05 13:43:26 -0800 | [diff] [blame] | 445 | |
Ben Dooks | 9e506f3 | 2010-03-05 13:43:29 -0800 | [diff] [blame] | 446 | cmdlen[0] = cpu_to_le16(cmd); |
| 447 | cmdlen[1] = cpu_to_le16(len); |
| 448 | |
| 449 | dataddr[0] = cpu_to_le32(addr); |
Ben Dooks | 118cd17 | 2010-03-05 13:43:26 -0800 | [diff] [blame] | 450 | } |
| 451 | |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 452 | static int sdhci_adma_table_pre(struct sdhci_host *host, |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 453 | struct mmc_data *data) |
| 454 | { |
| 455 | int direction; |
| 456 | |
| 457 | u8 *desc; |
| 458 | u8 *align; |
| 459 | dma_addr_t addr; |
| 460 | dma_addr_t align_addr; |
| 461 | int len, offset; |
| 462 | |
| 463 | struct scatterlist *sg; |
| 464 | int i; |
| 465 | char *buffer; |
| 466 | unsigned long flags; |
| 467 | |
| 468 | /* |
| 469 | * The spec does not specify endianness of descriptor table. |
| 470 | * We currently guess that it is LE. |
| 471 | */ |
| 472 | |
| 473 | if (data->flags & MMC_DATA_READ) |
| 474 | direction = DMA_FROM_DEVICE; |
| 475 | else |
| 476 | direction = DMA_TO_DEVICE; |
| 477 | |
| 478 | /* |
| 479 | * The ADMA descriptor table is mapped further down as we |
| 480 | * need to fill it with data first. |
| 481 | */ |
| 482 | |
| 483 | host->align_addr = dma_map_single(mmc_dev(host->mmc), |
| 484 | host->align_buffer, 128 * 4, direction); |
FUJITA Tomonori | 8d8bb39 | 2008-07-25 19:44:49 -0700 | [diff] [blame] | 485 | if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr)) |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 486 | goto fail; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 487 | BUG_ON(host->align_addr & 0x3); |
| 488 | |
| 489 | host->sg_count = dma_map_sg(mmc_dev(host->mmc), |
| 490 | data->sg, data->sg_len, direction); |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 491 | if (host->sg_count == 0) |
| 492 | goto unmap_align; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 493 | |
| 494 | desc = host->adma_desc; |
| 495 | align = host->align_buffer; |
| 496 | |
| 497 | align_addr = host->align_addr; |
| 498 | |
| 499 | for_each_sg(data->sg, sg, host->sg_count, i) { |
| 500 | addr = sg_dma_address(sg); |
| 501 | len = sg_dma_len(sg); |
| 502 | |
| 503 | /* |
| 504 | * The SDHCI specification states that ADMA |
| 505 | * addresses must be 32-bit aligned. If they |
| 506 | * aren't, then we use a bounce buffer for |
| 507 | * the (up to three) bytes that screw up the |
| 508 | * alignment. |
| 509 | */ |
| 510 | offset = (4 - (addr & 0x3)) & 0x3; |
| 511 | if (offset) { |
| 512 | if (data->flags & MMC_DATA_WRITE) { |
| 513 | buffer = sdhci_kmap_atomic(sg, &flags); |
Pierre Ossman | 6cefd05 | 2008-07-21 00:45:15 +0200 | [diff] [blame] | 514 | WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 515 | memcpy(align, buffer, offset); |
| 516 | sdhci_kunmap_atomic(buffer, &flags); |
| 517 | } |
| 518 | |
Ben Dooks | 118cd17 | 2010-03-05 13:43:26 -0800 | [diff] [blame] | 519 | /* tran, valid */ |
| 520 | sdhci_set_adma_desc(desc, align_addr, offset, 0x21); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 521 | |
| 522 | BUG_ON(offset > 65536); |
| 523 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 524 | align += 4; |
| 525 | align_addr += 4; |
| 526 | |
| 527 | desc += 8; |
| 528 | |
| 529 | addr += offset; |
| 530 | len -= offset; |
| 531 | } |
| 532 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 533 | BUG_ON(len > 65536); |
| 534 | |
Ben Dooks | 118cd17 | 2010-03-05 13:43:26 -0800 | [diff] [blame] | 535 | /* tran, valid */ |
| 536 | sdhci_set_adma_desc(desc, addr, len, 0x21); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 537 | desc += 8; |
| 538 | |
| 539 | /* |
| 540 | * If this triggers then we have a calculation bug |
| 541 | * somewhere. :/ |
| 542 | */ |
| 543 | WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4); |
| 544 | } |
| 545 | |
Thomas Abraham | 70764a9 | 2010-05-26 14:42:04 -0700 | [diff] [blame] | 546 | if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { |
| 547 | /* |
| 548 | * Mark the last descriptor as the terminating descriptor |
| 549 | */ |
| 550 | if (desc != host->adma_desc) { |
| 551 | desc -= 8; |
| 552 | desc[0] |= 0x2; /* end */ |
| 553 | } |
| 554 | } else { |
| 555 | /* |
| 556 | * Add a terminating entry. |
| 557 | */ |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 558 | |
Thomas Abraham | 70764a9 | 2010-05-26 14:42:04 -0700 | [diff] [blame] | 559 | /* nop, end, valid */ |
| 560 | sdhci_set_adma_desc(desc, 0, 0, 0x3); |
| 561 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 562 | |
| 563 | /* |
| 564 | * Resync align buffer as we might have changed it. |
| 565 | */ |
| 566 | if (data->flags & MMC_DATA_WRITE) { |
| 567 | dma_sync_single_for_device(mmc_dev(host->mmc), |
| 568 | host->align_addr, 128 * 4, direction); |
| 569 | } |
| 570 | |
| 571 | host->adma_addr = dma_map_single(mmc_dev(host->mmc), |
| 572 | host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE); |
Pierre Ossman | 980167b | 2008-07-29 00:53:20 +0200 | [diff] [blame] | 573 | if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr)) |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 574 | goto unmap_entries; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 575 | BUG_ON(host->adma_addr & 0x3); |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 576 | |
| 577 | return 0; |
| 578 | |
| 579 | unmap_entries: |
| 580 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, |
| 581 | data->sg_len, direction); |
| 582 | unmap_align: |
| 583 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, |
| 584 | 128 * 4, direction); |
| 585 | fail: |
| 586 | return -EINVAL; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 587 | } |
| 588 | |
| 589 | static void sdhci_adma_table_post(struct sdhci_host *host, |
| 590 | struct mmc_data *data) |
| 591 | { |
| 592 | int direction; |
| 593 | |
| 594 | struct scatterlist *sg; |
| 595 | int i, size; |
| 596 | u8 *align; |
| 597 | char *buffer; |
| 598 | unsigned long flags; |
| 599 | |
| 600 | if (data->flags & MMC_DATA_READ) |
| 601 | direction = DMA_FROM_DEVICE; |
| 602 | else |
| 603 | direction = DMA_TO_DEVICE; |
| 604 | |
| 605 | dma_unmap_single(mmc_dev(host->mmc), host->adma_addr, |
| 606 | (128 * 2 + 1) * 4, DMA_TO_DEVICE); |
| 607 | |
| 608 | dma_unmap_single(mmc_dev(host->mmc), host->align_addr, |
| 609 | 128 * 4, direction); |
| 610 | |
| 611 | if (data->flags & MMC_DATA_READ) { |
| 612 | dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, |
| 613 | data->sg_len, direction); |
| 614 | |
| 615 | align = host->align_buffer; |
| 616 | |
| 617 | for_each_sg(data->sg, sg, host->sg_count, i) { |
| 618 | if (sg_dma_address(sg) & 0x3) { |
| 619 | size = 4 - (sg_dma_address(sg) & 0x3); |
| 620 | |
| 621 | buffer = sdhci_kmap_atomic(sg, &flags); |
Pierre Ossman | 6cefd05 | 2008-07-21 00:45:15 +0200 | [diff] [blame] | 622 | WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3)); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 623 | memcpy(buffer, align, size); |
| 624 | sdhci_kunmap_atomic(buffer, &flags); |
| 625 | |
| 626 | align += 4; |
| 627 | } |
| 628 | } |
| 629 | } |
| 630 | |
| 631 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, |
| 632 | data->sg_len, direction); |
| 633 | } |
| 634 | |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 635 | static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 636 | { |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 637 | u8 count; |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 638 | struct mmc_data *data = cmd->data; |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 639 | unsigned target_timeout, current_timeout; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 640 | |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 641 | /* |
| 642 | * If the host controller provides us with an incorrect timeout |
| 643 | * value, just skip the check and use 0xE. The hardware may take |
| 644 | * longer to time out, but that's much better than having a too-short |
| 645 | * timeout value. |
| 646 | */ |
Pierre Ossman | 11a2f1b | 2009-06-21 20:59:33 +0200 | [diff] [blame] | 647 | if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 648 | return 0xE; |
Pierre Ossman | e538fbe | 2007-08-12 16:46:32 +0200 | [diff] [blame] | 649 | |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 650 | /* Unspecified timeout, assume max */ |
| 651 | if (!data && !cmd->cmd_timeout_ms) |
| 652 | return 0xE; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 653 | |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 654 | /* timeout in us */ |
| 655 | if (!data) |
| 656 | target_timeout = cmd->cmd_timeout_ms * 1000; |
Andy Shevchenko | 78a2ca2 | 2011-08-03 18:35:59 +0300 | [diff] [blame] | 657 | else { |
| 658 | target_timeout = data->timeout_ns / 1000; |
| 659 | if (host->clock) |
| 660 | target_timeout += data->timeout_clks / host->clock; |
| 661 | } |
Anton Vorontsov | 81b3980 | 2009-09-22 16:45:13 -0700 | [diff] [blame] | 662 | |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 663 | /* |
| 664 | * Figure out needed cycles. |
| 665 | * We do this in steps in order to fit inside a 32 bit int. |
| 666 | * The first step is the minimum timeout, which will have a |
| 667 | * minimum resolution of 6 bits: |
| 668 | * (1) 2^13*1000 > 2^22, |
| 669 | * (2) host->timeout_clk < 2^16 |
| 670 | * => |
| 671 | * (1) / (2) > 2^6 |
| 672 | */ |
| 673 | count = 0; |
| 674 | current_timeout = (1 << 13) * 1000 / host->timeout_clk; |
| 675 | while (current_timeout < target_timeout) { |
| 676 | count++; |
| 677 | current_timeout <<= 1; |
| 678 | if (count >= 0xF) |
| 679 | break; |
| 680 | } |
| 681 | |
| 682 | if (count >= 0xF) { |
Chris Ball | 09eeff5 | 2012-06-01 10:39:45 -0400 | [diff] [blame] | 683 | DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", |
| 684 | mmc_hostname(host->mmc), count, cmd->opcode); |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 685 | count = 0xE; |
| 686 | } |
| 687 | |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 688 | return count; |
| 689 | } |
| 690 | |
Anton Vorontsov | 6aa943a | 2009-03-17 00:13:50 +0300 | [diff] [blame] | 691 | static void sdhci_set_transfer_irqs(struct sdhci_host *host) |
| 692 | { |
| 693 | u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; |
| 694 | u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; |
| 695 | |
| 696 | if (host->flags & SDHCI_REQ_USE_DMA) |
| 697 | sdhci_clear_set_irqs(host, pio_irqs, dma_irqs); |
| 698 | else |
| 699 | sdhci_clear_set_irqs(host, dma_irqs, pio_irqs); |
| 700 | } |
| 701 | |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 702 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 703 | { |
| 704 | u8 count; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 705 | u8 ctrl; |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 706 | struct mmc_data *data = cmd->data; |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 707 | int ret; |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 708 | |
| 709 | WARN_ON(host->data); |
| 710 | |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 711 | if (data || (cmd->flags & MMC_RSP_BUSY)) { |
| 712 | count = sdhci_calc_timeout(host, cmd); |
| 713 | sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); |
| 714 | } |
| 715 | |
| 716 | if (!data) |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 717 | return; |
| 718 | |
| 719 | /* Sanity checks */ |
| 720 | BUG_ON(data->blksz * data->blocks > 524288); |
| 721 | BUG_ON(data->blksz > host->mmc->max_blk_size); |
| 722 | BUG_ON(data->blocks > 65535); |
| 723 | |
| 724 | host->data = data; |
| 725 | host->data_early = 0; |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 726 | host->data->bytes_xfered = 0; |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 727 | |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 728 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) |
Pierre Ossman | c9fddbc | 2007-12-02 19:52:11 +0100 | [diff] [blame] | 729 | host->flags |= SDHCI_REQ_USE_DMA; |
| 730 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 731 | /* |
| 732 | * FIXME: This doesn't account for merging when mapping the |
| 733 | * scatterlist. |
| 734 | */ |
| 735 | if (host->flags & SDHCI_REQ_USE_DMA) { |
| 736 | int broken, i; |
| 737 | struct scatterlist *sg; |
| 738 | |
| 739 | broken = 0; |
| 740 | if (host->flags & SDHCI_USE_ADMA) { |
| 741 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) |
| 742 | broken = 1; |
| 743 | } else { |
| 744 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) |
| 745 | broken = 1; |
| 746 | } |
| 747 | |
| 748 | if (unlikely(broken)) { |
| 749 | for_each_sg(data->sg, sg, data->sg_len, i) { |
| 750 | if (sg->length & 0x3) { |
| 751 | DBG("Reverting to PIO because of " |
| 752 | "transfer size (%d)\n", |
| 753 | sg->length); |
| 754 | host->flags &= ~SDHCI_REQ_USE_DMA; |
| 755 | break; |
| 756 | } |
| 757 | } |
| 758 | } |
Pierre Ossman | c9fddbc | 2007-12-02 19:52:11 +0100 | [diff] [blame] | 759 | } |
| 760 | |
| 761 | /* |
| 762 | * The assumption here being that alignment is the same after |
| 763 | * translation to device address space. |
| 764 | */ |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 765 | if (host->flags & SDHCI_REQ_USE_DMA) { |
| 766 | int broken, i; |
| 767 | struct scatterlist *sg; |
| 768 | |
| 769 | broken = 0; |
| 770 | if (host->flags & SDHCI_USE_ADMA) { |
| 771 | /* |
| 772 | * As we use 3 byte chunks to work around |
| 773 | * alignment problems, we need to check this |
| 774 | * quirk. |
| 775 | */ |
| 776 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) |
| 777 | broken = 1; |
| 778 | } else { |
| 779 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) |
| 780 | broken = 1; |
| 781 | } |
| 782 | |
| 783 | if (unlikely(broken)) { |
| 784 | for_each_sg(data->sg, sg, data->sg_len, i) { |
| 785 | if (sg->offset & 0x3) { |
| 786 | DBG("Reverting to PIO because of " |
| 787 | "bad alignment\n"); |
| 788 | host->flags &= ~SDHCI_REQ_USE_DMA; |
| 789 | break; |
| 790 | } |
| 791 | } |
| 792 | } |
| 793 | } |
| 794 | |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 795 | if (host->flags & SDHCI_REQ_USE_DMA) { |
| 796 | if (host->flags & SDHCI_USE_ADMA) { |
| 797 | ret = sdhci_adma_table_pre(host, data); |
| 798 | if (ret) { |
| 799 | /* |
| 800 | * This only happens when someone fed |
| 801 | * us an invalid request. |
| 802 | */ |
| 803 | WARN_ON(1); |
Pierre Ossman | ebd6d35 | 2008-07-29 00:45:51 +0200 | [diff] [blame] | 804 | host->flags &= ~SDHCI_REQ_USE_DMA; |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 805 | } else { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 806 | sdhci_writel(host, host->adma_addr, |
| 807 | SDHCI_ADMA_ADDRESS); |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 808 | } |
| 809 | } else { |
Tomas Winkler | c8b3e02 | 2008-07-05 19:52:04 +0300 | [diff] [blame] | 810 | int sg_cnt; |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 811 | |
Tomas Winkler | c8b3e02 | 2008-07-05 19:52:04 +0300 | [diff] [blame] | 812 | sg_cnt = dma_map_sg(mmc_dev(host->mmc), |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 813 | data->sg, data->sg_len, |
| 814 | (data->flags & MMC_DATA_READ) ? |
| 815 | DMA_FROM_DEVICE : |
| 816 | DMA_TO_DEVICE); |
Tomas Winkler | c8b3e02 | 2008-07-05 19:52:04 +0300 | [diff] [blame] | 817 | if (sg_cnt == 0) { |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 818 | /* |
| 819 | * This only happens when someone fed |
| 820 | * us an invalid request. |
| 821 | */ |
| 822 | WARN_ON(1); |
Pierre Ossman | ebd6d35 | 2008-07-29 00:45:51 +0200 | [diff] [blame] | 823 | host->flags &= ~SDHCI_REQ_USE_DMA; |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 824 | } else { |
Pierre Ossman | 719a61b | 2008-07-22 13:23:23 +0200 | [diff] [blame] | 825 | WARN_ON(sg_cnt != 1); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 826 | sdhci_writel(host, sg_dma_address(data->sg), |
| 827 | SDHCI_DMA_ADDRESS); |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 828 | } |
| 829 | } |
| 830 | } |
| 831 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 832 | /* |
| 833 | * Always adjust the DMA selection as some controllers |
| 834 | * (e.g. JMicron) can't do PIO properly when the selection |
| 835 | * is ADMA. |
| 836 | */ |
| 837 | if (host->version >= SDHCI_SPEC_200) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 838 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 839 | ctrl &= ~SDHCI_CTRL_DMA_MASK; |
| 840 | if ((host->flags & SDHCI_REQ_USE_DMA) && |
| 841 | (host->flags & SDHCI_USE_ADMA)) |
| 842 | ctrl |= SDHCI_CTRL_ADMA32; |
| 843 | else |
| 844 | ctrl |= SDHCI_CTRL_SDMA; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 845 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Pierre Ossman | c9fddbc | 2007-12-02 19:52:11 +0100 | [diff] [blame] | 846 | } |
| 847 | |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 848 | if (!(host->flags & SDHCI_REQ_USE_DMA)) { |
Sebastian Andrzej Siewior | da60a91 | 2009-06-18 09:33:32 +0200 | [diff] [blame] | 849 | int flags; |
| 850 | |
| 851 | flags = SG_MITER_ATOMIC; |
| 852 | if (host->data->flags & MMC_DATA_READ) |
| 853 | flags |= SG_MITER_TO_SG; |
| 854 | else |
| 855 | flags |= SG_MITER_FROM_SG; |
| 856 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 857 | host->blocks = data->blocks; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 858 | } |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 859 | |
Anton Vorontsov | 6aa943a | 2009-03-17 00:13:50 +0300 | [diff] [blame] | 860 | sdhci_set_transfer_irqs(host); |
| 861 | |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 862 | /* Set the DMA boundary value and block size */ |
| 863 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, |
| 864 | data->blksz), SDHCI_BLOCK_SIZE); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 865 | sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 866 | } |
| 867 | |
| 868 | static void sdhci_set_transfer_mode(struct sdhci_host *host, |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 869 | struct mmc_command *cmd) |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 870 | { |
| 871 | u16 mode; |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 872 | struct mmc_data *data = cmd->data; |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 873 | |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 874 | if (data == NULL) |
| 875 | return; |
| 876 | |
Pierre Ossman | e538fbe | 2007-08-12 16:46:32 +0200 | [diff] [blame] | 877 | WARN_ON(!host->data); |
| 878 | |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 879 | mode = SDHCI_TRNS_BLK_CNT_EN; |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 880 | if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { |
| 881 | mode |= SDHCI_TRNS_MULTI; |
| 882 | /* |
| 883 | * If we are sending CMD23, CMD12 never gets sent |
| 884 | * on successful completion (so no Auto-CMD12). |
| 885 | */ |
| 886 | if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) |
| 887 | mode |= SDHCI_TRNS_AUTO_CMD12; |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 888 | else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { |
| 889 | mode |= SDHCI_TRNS_AUTO_CMD23; |
| 890 | sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2); |
| 891 | } |
Jerry Huang | c4512f7 | 2010-08-10 18:01:59 -0700 | [diff] [blame] | 892 | } |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 893 | |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 894 | if (data->flags & MMC_DATA_READ) |
| 895 | mode |= SDHCI_TRNS_READ; |
Pierre Ossman | c9fddbc | 2007-12-02 19:52:11 +0100 | [diff] [blame] | 896 | if (host->flags & SDHCI_REQ_USE_DMA) |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 897 | mode |= SDHCI_TRNS_DMA; |
| 898 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 899 | sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 900 | } |
| 901 | |
| 902 | static void sdhci_finish_data(struct sdhci_host *host) |
| 903 | { |
| 904 | struct mmc_data *data; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 905 | |
| 906 | BUG_ON(!host->data); |
| 907 | |
| 908 | data = host->data; |
| 909 | host->data = NULL; |
| 910 | |
Pierre Ossman | c9fddbc | 2007-12-02 19:52:11 +0100 | [diff] [blame] | 911 | if (host->flags & SDHCI_REQ_USE_DMA) { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 912 | if (host->flags & SDHCI_USE_ADMA) |
| 913 | sdhci_adma_table_post(host, data); |
| 914 | else { |
| 915 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, |
| 916 | data->sg_len, (data->flags & MMC_DATA_READ) ? |
| 917 | DMA_FROM_DEVICE : DMA_TO_DEVICE); |
| 918 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 919 | } |
| 920 | |
| 921 | /* |
Pierre Ossman | c9b74c5 | 2008-04-18 20:41:49 +0200 | [diff] [blame] | 922 | * The specification states that the block count register must |
| 923 | * be updated, but it does not specify at what point in the |
| 924 | * data flow. That makes the register entirely useless to read |
| 925 | * back so we have to assume that nothing made it to the card |
| 926 | * in the event of an error. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 927 | */ |
Pierre Ossman | c9b74c5 | 2008-04-18 20:41:49 +0200 | [diff] [blame] | 928 | if (data->error) |
| 929 | data->bytes_xfered = 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 930 | else |
Pierre Ossman | c9b74c5 | 2008-04-18 20:41:49 +0200 | [diff] [blame] | 931 | data->bytes_xfered = data->blksz * data->blocks; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 932 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 933 | /* |
| 934 | * Need to send CMD12 if - |
| 935 | * a) open-ended multiblock transfer (no CMD23) |
| 936 | * b) error in multiblock transfer |
| 937 | */ |
| 938 | if (data->stop && |
| 939 | (data->error || |
| 940 | !host->mrq->sbc)) { |
| 941 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 942 | /* |
| 943 | * The controller needs a reset of internal state machines |
| 944 | * upon error conditions. |
| 945 | */ |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 946 | if (data->error) { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 947 | sdhci_reset(host, SDHCI_RESET_CMD); |
| 948 | sdhci_reset(host, SDHCI_RESET_DATA); |
| 949 | } |
| 950 | |
| 951 | sdhci_send_command(host, data->stop); |
| 952 | } else |
| 953 | tasklet_schedule(&host->finish_tasklet); |
| 954 | } |
| 955 | |
| 956 | static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) |
| 957 | { |
| 958 | int flags; |
Pierre Ossman | fd2208d | 2006-06-30 02:22:28 -0700 | [diff] [blame] | 959 | u32 mask; |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 960 | unsigned long timeout; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 961 | |
| 962 | WARN_ON(host->cmd); |
| 963 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 964 | /* Wait max 10 ms */ |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 965 | timeout = 10; |
Pierre Ossman | fd2208d | 2006-06-30 02:22:28 -0700 | [diff] [blame] | 966 | |
| 967 | mask = SDHCI_CMD_INHIBIT; |
| 968 | if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) |
| 969 | mask |= SDHCI_DATA_INHIBIT; |
| 970 | |
| 971 | /* We shouldn't wait for data inihibit for stop commands, even |
| 972 | though they might use busy signaling */ |
| 973 | if (host->mrq->data && (cmd == host->mrq->data->stop)) |
| 974 | mask &= ~SDHCI_DATA_INHIBIT; |
| 975 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 976 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 977 | if (timeout == 0) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 978 | pr_err("%s: Controller never released " |
Pierre Ossman | acf1da4 | 2007-02-09 08:29:19 +0100 | [diff] [blame] | 979 | "inhibit bit(s).\n", mmc_hostname(host->mmc)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 980 | sdhci_dumpregs(host); |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 981 | cmd->error = -EIO; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 982 | tasklet_schedule(&host->finish_tasklet); |
| 983 | return; |
| 984 | } |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 985 | timeout--; |
| 986 | mdelay(1); |
| 987 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 988 | |
| 989 | mod_timer(&host->timer, jiffies + 10 * HZ); |
| 990 | |
| 991 | host->cmd = cmd; |
| 992 | |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 993 | sdhci_prepare_data(host, cmd); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 994 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 995 | sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 996 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 997 | sdhci_set_transfer_mode(host, cmd); |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 998 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 999 | if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 1000 | pr_err("%s: Unsupported response type!\n", |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1001 | mmc_hostname(host->mmc)); |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 1002 | cmd->error = -EINVAL; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1003 | tasklet_schedule(&host->finish_tasklet); |
| 1004 | return; |
| 1005 | } |
| 1006 | |
| 1007 | if (!(cmd->flags & MMC_RSP_PRESENT)) |
| 1008 | flags = SDHCI_CMD_RESP_NONE; |
| 1009 | else if (cmd->flags & MMC_RSP_136) |
| 1010 | flags = SDHCI_CMD_RESP_LONG; |
| 1011 | else if (cmd->flags & MMC_RSP_BUSY) |
| 1012 | flags = SDHCI_CMD_RESP_SHORT_BUSY; |
| 1013 | else |
| 1014 | flags = SDHCI_CMD_RESP_SHORT; |
| 1015 | |
| 1016 | if (cmd->flags & MMC_RSP_CRC) |
| 1017 | flags |= SDHCI_CMD_CRC; |
| 1018 | if (cmd->flags & MMC_RSP_OPCODE) |
| 1019 | flags |= SDHCI_CMD_INDEX; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1020 | |
| 1021 | /* CMD19 is special in that the Data Present Select should be set */ |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1022 | if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || |
| 1023 | cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1024 | flags |= SDHCI_CMD_DATA; |
| 1025 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1026 | sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1027 | } |
| 1028 | |
| 1029 | static void sdhci_finish_command(struct sdhci_host *host) |
| 1030 | { |
| 1031 | int i; |
| 1032 | |
| 1033 | BUG_ON(host->cmd == NULL); |
| 1034 | |
| 1035 | if (host->cmd->flags & MMC_RSP_PRESENT) { |
| 1036 | if (host->cmd->flags & MMC_RSP_136) { |
| 1037 | /* CRC is stripped so we need to do some shifting. */ |
| 1038 | for (i = 0;i < 4;i++) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1039 | host->cmd->resp[i] = sdhci_readl(host, |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1040 | SDHCI_RESPONSE + (3-i)*4) << 8; |
| 1041 | if (i != 3) |
| 1042 | host->cmd->resp[i] |= |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1043 | sdhci_readb(host, |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1044 | SDHCI_RESPONSE + (3-i)*4-1); |
| 1045 | } |
| 1046 | } else { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1047 | host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1048 | } |
| 1049 | } |
| 1050 | |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 1051 | host->cmd->error = 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1052 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1053 | /* Finished CMD23, now send actual command. */ |
| 1054 | if (host->cmd == host->mrq->sbc) { |
| 1055 | host->cmd = NULL; |
| 1056 | sdhci_send_command(host, host->mrq->cmd); |
| 1057 | } else { |
Pierre Ossman | e538fbe | 2007-08-12 16:46:32 +0200 | [diff] [blame] | 1058 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1059 | /* Processed actual command. */ |
| 1060 | if (host->data && host->data_early) |
| 1061 | sdhci_finish_data(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1062 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1063 | if (!host->cmd->data) |
| 1064 | tasklet_schedule(&host->finish_tasklet); |
| 1065 | |
| 1066 | host->cmd = NULL; |
| 1067 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1068 | } |
| 1069 | |
| 1070 | static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) |
| 1071 | { |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1072 | int div = 0; /* Initialized for compiler warning */ |
Giuseppe CAVALLARO | df16219 | 2011-11-04 13:53:19 +0100 | [diff] [blame] | 1073 | int real_div = div, clk_mul = 1; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1074 | u16 clk = 0; |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1075 | unsigned long timeout; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1076 | |
Todd Poynor | 30832ab | 2011-12-27 15:48:46 +0200 | [diff] [blame] | 1077 | if (clock && clock == host->clock) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1078 | return; |
| 1079 | |
Giuseppe CAVALLARO | df16219 | 2011-11-04 13:53:19 +0100 | [diff] [blame] | 1080 | host->mmc->actual_clock = 0; |
| 1081 | |
Anton Vorontsov | 8114634 | 2009-03-17 00:13:59 +0300 | [diff] [blame] | 1082 | if (host->ops->set_clock) { |
| 1083 | host->ops->set_clock(host, clock); |
| 1084 | if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK) |
| 1085 | return; |
| 1086 | } |
| 1087 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1088 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1089 | |
| 1090 | if (clock == 0) |
| 1091 | goto out; |
| 1092 | |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1093 | if (host->version >= SDHCI_SPEC_300) { |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1094 | /* |
| 1095 | * Check if the Host Controller supports Programmable Clock |
| 1096 | * Mode. |
| 1097 | */ |
| 1098 | if (host->clk_mul) { |
| 1099 | u16 ctrl; |
| 1100 | |
| 1101 | /* |
| 1102 | * We need to figure out whether the Host Driver needs |
| 1103 | * to select Programmable Clock Mode, or the value can |
| 1104 | * be set automatically by the Host Controller based on |
| 1105 | * the Preset Value registers. |
| 1106 | */ |
| 1107 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1108 | if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { |
| 1109 | for (div = 1; div <= 1024; div++) { |
| 1110 | if (((host->max_clk * host->clk_mul) / |
| 1111 | div) <= clock) |
| 1112 | break; |
| 1113 | } |
| 1114 | /* |
| 1115 | * Set Programmable Clock Mode in the Clock |
| 1116 | * Control register. |
| 1117 | */ |
| 1118 | clk = SDHCI_PROG_CLOCK_MODE; |
Giuseppe CAVALLARO | df16219 | 2011-11-04 13:53:19 +0100 | [diff] [blame] | 1119 | real_div = div; |
| 1120 | clk_mul = host->clk_mul; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1121 | div--; |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1122 | } |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1123 | } else { |
| 1124 | /* Version 3.00 divisors must be a multiple of 2. */ |
| 1125 | if (host->max_clk <= clock) |
| 1126 | div = 1; |
| 1127 | else { |
| 1128 | for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; |
| 1129 | div += 2) { |
| 1130 | if ((host->max_clk / div) <= clock) |
| 1131 | break; |
| 1132 | } |
| 1133 | } |
Giuseppe CAVALLARO | df16219 | 2011-11-04 13:53:19 +0100 | [diff] [blame] | 1134 | real_div = div; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1135 | div >>= 1; |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1136 | } |
| 1137 | } else { |
| 1138 | /* Version 2.00 divisors must be a power of 2. */ |
Zhangfei Gao | 0397526 | 2010-09-20 15:15:18 -0400 | [diff] [blame] | 1139 | for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1140 | if ((host->max_clk / div) <= clock) |
| 1141 | break; |
| 1142 | } |
Giuseppe CAVALLARO | df16219 | 2011-11-04 13:53:19 +0100 | [diff] [blame] | 1143 | real_div = div; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1144 | div >>= 1; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1145 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1146 | |
Giuseppe CAVALLARO | df16219 | 2011-11-04 13:53:19 +0100 | [diff] [blame] | 1147 | if (real_div) |
| 1148 | host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div; |
| 1149 | |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1150 | clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1151 | clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) |
| 1152 | << SDHCI_DIVIDER_HI_SHIFT; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1153 | clk |= SDHCI_CLOCK_INT_EN; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1154 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1155 | |
Chris Ball | 27f6cb1 | 2009-09-22 16:45:31 -0700 | [diff] [blame] | 1156 | /* Wait max 20 ms */ |
| 1157 | timeout = 20; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1158 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1159 | & SDHCI_CLOCK_INT_STABLE)) { |
| 1160 | if (timeout == 0) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 1161 | pr_err("%s: Internal clock never " |
Pierre Ossman | acf1da4 | 2007-02-09 08:29:19 +0100 | [diff] [blame] | 1162 | "stabilised.\n", mmc_hostname(host->mmc)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1163 | sdhci_dumpregs(host); |
| 1164 | return; |
| 1165 | } |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1166 | timeout--; |
| 1167 | mdelay(1); |
| 1168 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1169 | |
| 1170 | clk |= SDHCI_CLOCK_CARD_EN; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1171 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1172 | |
| 1173 | out: |
| 1174 | host->clock = clock; |
| 1175 | } |
| 1176 | |
Adrian Hunter | ceb6143 | 2011-12-27 15:48:41 +0200 | [diff] [blame] | 1177 | static int sdhci_set_power(struct sdhci_host *host, unsigned short power) |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1178 | { |
Giuseppe Cavallaro | 8364248 | 2010-09-28 10:41:28 +0200 | [diff] [blame] | 1179 | u8 pwr = 0; |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1180 | |
Giuseppe Cavallaro | 8364248 | 2010-09-28 10:41:28 +0200 | [diff] [blame] | 1181 | if (power != (unsigned short)-1) { |
Pierre Ossman | ae62890 | 2009-05-03 20:45:03 +0200 | [diff] [blame] | 1182 | switch (1 << power) { |
| 1183 | case MMC_VDD_165_195: |
| 1184 | pwr = SDHCI_POWER_180; |
| 1185 | break; |
| 1186 | case MMC_VDD_29_30: |
| 1187 | case MMC_VDD_30_31: |
| 1188 | pwr = SDHCI_POWER_300; |
| 1189 | break; |
| 1190 | case MMC_VDD_32_33: |
| 1191 | case MMC_VDD_33_34: |
| 1192 | pwr = SDHCI_POWER_330; |
| 1193 | break; |
| 1194 | default: |
| 1195 | BUG(); |
| 1196 | } |
| 1197 | } |
| 1198 | |
| 1199 | if (host->pwr == pwr) |
Adrian Hunter | ceb6143 | 2011-12-27 15:48:41 +0200 | [diff] [blame] | 1200 | return -1; |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1201 | |
Pierre Ossman | ae62890 | 2009-05-03 20:45:03 +0200 | [diff] [blame] | 1202 | host->pwr = pwr; |
| 1203 | |
| 1204 | if (pwr == 0) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1205 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
Adrian Hunter | ceb6143 | 2011-12-27 15:48:41 +0200 | [diff] [blame] | 1206 | return 0; |
Darren Salt | 9e9dc5f | 2007-01-27 15:32:31 +0100 | [diff] [blame] | 1207 | } |
| 1208 | |
| 1209 | /* |
| 1210 | * Spec says that we should clear the power reg before setting |
| 1211 | * a new value. Some controllers don't seem to like this though. |
| 1212 | */ |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 1213 | if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1214 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1215 | |
Andres Salomon | e08c169 | 2008-07-04 10:00:03 -0700 | [diff] [blame] | 1216 | /* |
Andres Salomon | c71f651 | 2008-07-07 17:25:56 -0400 | [diff] [blame] | 1217 | * At least the Marvell CaFe chip gets confused if we set the voltage |
Andres Salomon | e08c169 | 2008-07-04 10:00:03 -0700 | [diff] [blame] | 1218 | * and set turn on power at the same time, so set the voltage first. |
| 1219 | */ |
Pierre Ossman | 11a2f1b | 2009-06-21 20:59:33 +0200 | [diff] [blame] | 1220 | if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) |
Pierre Ossman | ae62890 | 2009-05-03 20:45:03 +0200 | [diff] [blame] | 1221 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
| 1222 | |
| 1223 | pwr |= SDHCI_POWER_ON; |
Andres Salomon | e08c169 | 2008-07-04 10:00:03 -0700 | [diff] [blame] | 1224 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1225 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
Harald Welte | 557b069 | 2009-06-18 16:53:38 +0200 | [diff] [blame] | 1226 | |
| 1227 | /* |
| 1228 | * Some controllers need an extra 10ms delay of 10ms before they |
| 1229 | * can apply clock after applying power |
| 1230 | */ |
Pierre Ossman | 11a2f1b | 2009-06-21 20:59:33 +0200 | [diff] [blame] | 1231 | if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) |
Harald Welte | 557b069 | 2009-06-18 16:53:38 +0200 | [diff] [blame] | 1232 | mdelay(10); |
Adrian Hunter | ceb6143 | 2011-12-27 15:48:41 +0200 | [diff] [blame] | 1233 | |
| 1234 | return power; |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1235 | } |
| 1236 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1237 | /*****************************************************************************\ |
| 1238 | * * |
| 1239 | * MMC callbacks * |
| 1240 | * * |
| 1241 | \*****************************************************************************/ |
| 1242 | |
| 1243 | static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) |
| 1244 | { |
| 1245 | struct sdhci_host *host; |
Anton Vorontsov | 68d1fb7 | 2009-03-17 00:13:52 +0300 | [diff] [blame] | 1246 | bool present; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1247 | unsigned long flags; |
| 1248 | |
| 1249 | host = mmc_priv(mmc); |
| 1250 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1251 | sdhci_runtime_pm_get(host); |
| 1252 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1253 | spin_lock_irqsave(&host->lock, flags); |
| 1254 | |
| 1255 | WARN_ON(host->mrq != NULL); |
| 1256 | |
Pierre Ossman | f913431 | 2008-12-21 17:01:48 +0100 | [diff] [blame] | 1257 | #ifndef SDHCI_USE_LEDS_CLASS |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1258 | sdhci_activate_led(host); |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 1259 | #endif |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1260 | |
| 1261 | /* |
| 1262 | * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED |
| 1263 | * requests if Auto-CMD12 is enabled. |
| 1264 | */ |
| 1265 | if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) { |
Jerry Huang | c4512f7 | 2010-08-10 18:01:59 -0700 | [diff] [blame] | 1266 | if (mrq->stop) { |
| 1267 | mrq->data->stop = NULL; |
| 1268 | mrq->stop = NULL; |
| 1269 | } |
| 1270 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1271 | |
| 1272 | host->mrq = mrq; |
| 1273 | |
Anton Vorontsov | 68d1fb7 | 2009-03-17 00:13:52 +0300 | [diff] [blame] | 1274 | /* If polling, assume that the card is always present. */ |
| 1275 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) |
| 1276 | present = true; |
| 1277 | else |
| 1278 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & |
| 1279 | SDHCI_CARD_PRESENT; |
| 1280 | |
| 1281 | if (!present || host->flags & SDHCI_DEVICE_DEAD) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 1282 | host->mrq->cmd->error = -ENOMEDIUM; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1283 | tasklet_schedule(&host->finish_tasklet); |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 1284 | } else { |
| 1285 | u32 present_state; |
| 1286 | |
| 1287 | present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); |
| 1288 | /* |
| 1289 | * Check if the re-tuning timer has already expired and there |
| 1290 | * is no on-going data transfer. If so, we need to execute |
| 1291 | * tuning procedure before sending command. |
| 1292 | */ |
| 1293 | if ((host->flags & SDHCI_NEEDS_RETUNING) && |
| 1294 | !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) { |
| 1295 | spin_unlock_irqrestore(&host->lock, flags); |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1296 | sdhci_execute_tuning(mmc, mrq->cmd->opcode); |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 1297 | spin_lock_irqsave(&host->lock, flags); |
| 1298 | |
| 1299 | /* Restore original mmc_request structure */ |
| 1300 | host->mrq = mrq; |
| 1301 | } |
| 1302 | |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 1303 | if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1304 | sdhci_send_command(host, mrq->sbc); |
| 1305 | else |
| 1306 | sdhci_send_command(host, mrq->cmd); |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 1307 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1308 | |
Pierre Ossman | 5f25a66 | 2006-10-04 02:15:39 -0700 | [diff] [blame] | 1309 | mmiowb(); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1310 | spin_unlock_irqrestore(&host->lock, flags); |
| 1311 | } |
| 1312 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1313 | static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1314 | { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1315 | unsigned long flags; |
Adrian Hunter | ceb6143 | 2011-12-27 15:48:41 +0200 | [diff] [blame] | 1316 | int vdd_bit = -1; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1317 | u8 ctrl; |
| 1318 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1319 | spin_lock_irqsave(&host->lock, flags); |
| 1320 | |
Adrian Hunter | ceb6143 | 2011-12-27 15:48:41 +0200 | [diff] [blame] | 1321 | if (host->flags & SDHCI_DEVICE_DEAD) { |
| 1322 | spin_unlock_irqrestore(&host->lock, flags); |
| 1323 | if (host->vmmc && ios->power_mode == MMC_POWER_OFF) |
| 1324 | mmc_regulator_set_ocr(host->mmc, host->vmmc, 0); |
| 1325 | return; |
| 1326 | } |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 1327 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1328 | /* |
| 1329 | * Reset the chip on each power off. |
| 1330 | * Should clear out any weird states. |
| 1331 | */ |
| 1332 | if (ios->power_mode == MMC_POWER_OFF) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1333 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 1334 | sdhci_reinit(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1335 | } |
| 1336 | |
| 1337 | sdhci_set_clock(host, ios->clock); |
| 1338 | |
| 1339 | if (ios->power_mode == MMC_POWER_OFF) |
Adrian Hunter | ceb6143 | 2011-12-27 15:48:41 +0200 | [diff] [blame] | 1340 | vdd_bit = sdhci_set_power(host, -1); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1341 | else |
Adrian Hunter | ceb6143 | 2011-12-27 15:48:41 +0200 | [diff] [blame] | 1342 | vdd_bit = sdhci_set_power(host, ios->vdd); |
| 1343 | |
| 1344 | if (host->vmmc && vdd_bit != -1) { |
| 1345 | spin_unlock_irqrestore(&host->lock, flags); |
| 1346 | mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit); |
| 1347 | spin_lock_irqsave(&host->lock, flags); |
| 1348 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1349 | |
Philip Rakity | 643a81f | 2010-09-23 08:24:32 -0700 | [diff] [blame] | 1350 | if (host->ops->platform_send_init_74_clocks) |
| 1351 | host->ops->platform_send_init_74_clocks(host, ios->power_mode); |
| 1352 | |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 1353 | /* |
| 1354 | * If your platform has 8-bit width support but is not a v3 controller, |
| 1355 | * or if it requires special setup code, you should implement that in |
| 1356 | * platform_8bit_width(). |
| 1357 | */ |
| 1358 | if (host->ops->platform_8bit_width) |
| 1359 | host->ops->platform_8bit_width(host, ios->bus_width); |
| 1360 | else { |
| 1361 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
| 1362 | if (ios->bus_width == MMC_BUS_WIDTH_8) { |
| 1363 | ctrl &= ~SDHCI_CTRL_4BITBUS; |
| 1364 | if (host->version >= SDHCI_SPEC_300) |
| 1365 | ctrl |= SDHCI_CTRL_8BITBUS; |
| 1366 | } else { |
| 1367 | if (host->version >= SDHCI_SPEC_300) |
| 1368 | ctrl &= ~SDHCI_CTRL_8BITBUS; |
| 1369 | if (ios->bus_width == MMC_BUS_WIDTH_4) |
| 1370 | ctrl |= SDHCI_CTRL_4BITBUS; |
| 1371 | else |
| 1372 | ctrl &= ~SDHCI_CTRL_4BITBUS; |
| 1373 | } |
| 1374 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
| 1375 | } |
| 1376 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1377 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
Pierre Ossman | cd9277c | 2007-02-18 12:07:47 +0100 | [diff] [blame] | 1378 | |
Philip Rakity | 3ab9c8d | 2010-10-06 11:57:23 -0700 | [diff] [blame] | 1379 | if ((ios->timing == MMC_TIMING_SD_HS || |
| 1380 | ios->timing == MMC_TIMING_MMC_HS) |
| 1381 | && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) |
Pierre Ossman | cd9277c | 2007-02-18 12:07:47 +0100 | [diff] [blame] | 1382 | ctrl |= SDHCI_CTRL_HISPD; |
| 1383 | else |
| 1384 | ctrl &= ~SDHCI_CTRL_HISPD; |
| 1385 | |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1386 | if (host->version >= SDHCI_SPEC_300) { |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1387 | u16 clk, ctrl_2; |
| 1388 | unsigned int clock; |
| 1389 | |
| 1390 | /* In case of UHS-I modes, set High Speed Enable */ |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1391 | if ((ios->timing == MMC_TIMING_MMC_HS200) || |
| 1392 | (ios->timing == MMC_TIMING_UHS_SDR50) || |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1393 | (ios->timing == MMC_TIMING_UHS_SDR104) || |
| 1394 | (ios->timing == MMC_TIMING_UHS_DDR50) || |
Alexander Elbs | dd8df17 | 2012-01-03 23:26:53 -0500 | [diff] [blame] | 1395 | (ios->timing == MMC_TIMING_UHS_SDR25)) |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1396 | ctrl |= SDHCI_CTRL_HISPD; |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1397 | |
| 1398 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1399 | if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) { |
Arindam Nath | 758535c | 2011-05-05 12:19:00 +0530 | [diff] [blame] | 1400 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1401 | /* |
| 1402 | * We only need to set Driver Strength if the |
| 1403 | * preset value enable is not set. |
| 1404 | */ |
| 1405 | ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; |
| 1406 | if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) |
| 1407 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; |
| 1408 | else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) |
| 1409 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; |
| 1410 | |
| 1411 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); |
Arindam Nath | 758535c | 2011-05-05 12:19:00 +0530 | [diff] [blame] | 1412 | } else { |
| 1413 | /* |
| 1414 | * According to SDHC Spec v3.00, if the Preset Value |
| 1415 | * Enable in the Host Control 2 register is set, we |
| 1416 | * need to reset SD Clock Enable before changing High |
| 1417 | * Speed Enable to avoid generating clock gliches. |
| 1418 | */ |
Arindam Nath | 758535c | 2011-05-05 12:19:00 +0530 | [diff] [blame] | 1419 | |
| 1420 | /* Reset SD Clock Enable */ |
| 1421 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); |
| 1422 | clk &= ~SDHCI_CLOCK_CARD_EN; |
| 1423 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
| 1424 | |
| 1425 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
| 1426 | |
| 1427 | /* Re-enable SD Clock */ |
| 1428 | clock = host->clock; |
| 1429 | host->clock = 0; |
| 1430 | sdhci_set_clock(host, clock); |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1431 | } |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1432 | |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1433 | |
| 1434 | /* Reset SD Clock Enable */ |
| 1435 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); |
| 1436 | clk &= ~SDHCI_CLOCK_CARD_EN; |
| 1437 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
| 1438 | |
Philip Rakity | 6322cdd | 2011-05-13 11:17:15 +0530 | [diff] [blame] | 1439 | if (host->ops->set_uhs_signaling) |
| 1440 | host->ops->set_uhs_signaling(host, ios->timing); |
| 1441 | else { |
| 1442 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1443 | /* Select Bus Speed Mode for host */ |
| 1444 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1445 | if (ios->timing == MMC_TIMING_MMC_HS200) |
| 1446 | ctrl_2 |= SDHCI_CTRL_HS_SDR200; |
| 1447 | else if (ios->timing == MMC_TIMING_UHS_SDR12) |
Philip Rakity | 6322cdd | 2011-05-13 11:17:15 +0530 | [diff] [blame] | 1448 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; |
| 1449 | else if (ios->timing == MMC_TIMING_UHS_SDR25) |
| 1450 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; |
| 1451 | else if (ios->timing == MMC_TIMING_UHS_SDR50) |
| 1452 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50; |
| 1453 | else if (ios->timing == MMC_TIMING_UHS_SDR104) |
| 1454 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; |
| 1455 | else if (ios->timing == MMC_TIMING_UHS_DDR50) |
| 1456 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50; |
| 1457 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); |
| 1458 | } |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1459 | |
| 1460 | /* Re-enable SD Clock */ |
| 1461 | clock = host->clock; |
| 1462 | host->clock = 0; |
| 1463 | sdhci_set_clock(host, clock); |
Arindam Nath | 758535c | 2011-05-05 12:19:00 +0530 | [diff] [blame] | 1464 | } else |
| 1465 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1466 | |
Leandro Dorileo | b835226 | 2007-07-25 23:47:04 +0200 | [diff] [blame] | 1467 | /* |
| 1468 | * Some (ENE) controllers go apeshit on some ios operation, |
| 1469 | * signalling timeout and CRC errors even on CMD0. Resetting |
| 1470 | * it on each ios seems to solve the problem. |
| 1471 | */ |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 1472 | if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) |
Leandro Dorileo | b835226 | 2007-07-25 23:47:04 +0200 | [diff] [blame] | 1473 | sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); |
| 1474 | |
Pierre Ossman | 5f25a66 | 2006-10-04 02:15:39 -0700 | [diff] [blame] | 1475 | mmiowb(); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1476 | spin_unlock_irqrestore(&host->lock, flags); |
| 1477 | } |
| 1478 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1479 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
| 1480 | { |
| 1481 | struct sdhci_host *host = mmc_priv(mmc); |
| 1482 | |
| 1483 | sdhci_runtime_pm_get(host); |
| 1484 | sdhci_do_set_ios(host, ios); |
| 1485 | sdhci_runtime_pm_put(host); |
| 1486 | } |
| 1487 | |
| 1488 | static int sdhci_check_ro(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1489 | { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1490 | unsigned long flags; |
Wolfram Sang | 2dfb579 | 2010-10-15 12:21:01 +0200 | [diff] [blame] | 1491 | int is_readonly; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1492 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1493 | spin_lock_irqsave(&host->lock, flags); |
| 1494 | |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 1495 | if (host->flags & SDHCI_DEVICE_DEAD) |
Wolfram Sang | 2dfb579 | 2010-10-15 12:21:01 +0200 | [diff] [blame] | 1496 | is_readonly = 0; |
| 1497 | else if (host->ops->get_ro) |
| 1498 | is_readonly = host->ops->get_ro(host); |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 1499 | else |
Wolfram Sang | 2dfb579 | 2010-10-15 12:21:01 +0200 | [diff] [blame] | 1500 | is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) |
| 1501 | & SDHCI_WRITE_PROTECT); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1502 | |
| 1503 | spin_unlock_irqrestore(&host->lock, flags); |
| 1504 | |
Wolfram Sang | 2dfb579 | 2010-10-15 12:21:01 +0200 | [diff] [blame] | 1505 | /* This quirk needs to be replaced by a callback-function later */ |
| 1506 | return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? |
| 1507 | !is_readonly : is_readonly; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1508 | } |
| 1509 | |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1510 | #define SAMPLE_COUNT 5 |
| 1511 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1512 | static int sdhci_do_get_ro(struct sdhci_host *host) |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1513 | { |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1514 | int i, ro_count; |
| 1515 | |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1516 | if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1517 | return sdhci_check_ro(host); |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1518 | |
| 1519 | ro_count = 0; |
| 1520 | for (i = 0; i < SAMPLE_COUNT; i++) { |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1521 | if (sdhci_check_ro(host)) { |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1522 | if (++ro_count > SAMPLE_COUNT / 2) |
| 1523 | return 1; |
| 1524 | } |
| 1525 | msleep(30); |
| 1526 | } |
| 1527 | return 0; |
| 1528 | } |
| 1529 | |
Adrian Hunter | 20758b6 | 2011-08-29 16:42:12 +0300 | [diff] [blame] | 1530 | static void sdhci_hw_reset(struct mmc_host *mmc) |
| 1531 | { |
| 1532 | struct sdhci_host *host = mmc_priv(mmc); |
| 1533 | |
| 1534 | if (host->ops && host->ops->hw_reset) |
| 1535 | host->ops->hw_reset(host); |
| 1536 | } |
| 1537 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1538 | static int sdhci_get_ro(struct mmc_host *mmc) |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 1539 | { |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1540 | struct sdhci_host *host = mmc_priv(mmc); |
| 1541 | int ret; |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 1542 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1543 | sdhci_runtime_pm_get(host); |
| 1544 | ret = sdhci_do_get_ro(host); |
| 1545 | sdhci_runtime_pm_put(host); |
| 1546 | return ret; |
| 1547 | } |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 1548 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1549 | static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) |
| 1550 | { |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 1551 | if (host->flags & SDHCI_DEVICE_DEAD) |
| 1552 | goto out; |
| 1553 | |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 1554 | if (enable) |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1555 | host->flags |= SDHCI_SDIO_IRQ_ENABLED; |
| 1556 | else |
| 1557 | host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; |
| 1558 | |
| 1559 | /* SDIO IRQ will be enabled as appropriate in runtime resume */ |
| 1560 | if (host->runtime_suspended) |
| 1561 | goto out; |
| 1562 | |
| 1563 | if (enable) |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 1564 | sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT); |
| 1565 | else |
| 1566 | sdhci_mask_irqs(host, SDHCI_INT_CARD_INT); |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 1567 | out: |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 1568 | mmiowb(); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1569 | } |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 1570 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1571 | static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
| 1572 | { |
| 1573 | struct sdhci_host *host = mmc_priv(mmc); |
| 1574 | unsigned long flags; |
| 1575 | |
| 1576 | spin_lock_irqsave(&host->lock, flags); |
| 1577 | sdhci_enable_sdio_irq_nolock(host, enable); |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 1578 | spin_unlock_irqrestore(&host->lock, flags); |
| 1579 | } |
| 1580 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1581 | static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, |
| 1582 | struct mmc_ios *ios) |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 1583 | { |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 1584 | u8 pwr; |
| 1585 | u16 clk, ctrl; |
| 1586 | u32 present_state; |
| 1587 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 1588 | /* |
| 1589 | * Signal Voltage Switching is only applicable for Host Controllers |
| 1590 | * v3.00 and above. |
| 1591 | */ |
| 1592 | if (host->version < SDHCI_SPEC_300) |
| 1593 | return 0; |
| 1594 | |
| 1595 | /* |
| 1596 | * We first check whether the request is to set signalling voltage |
| 1597 | * to 3.3V. If so, we change the voltage to 3.3V and return quickly. |
| 1598 | */ |
| 1599 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1600 | if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { |
| 1601 | /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ |
| 1602 | ctrl &= ~SDHCI_CTRL_VDD_180; |
| 1603 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
| 1604 | |
| 1605 | /* Wait for 5ms */ |
| 1606 | usleep_range(5000, 5500); |
| 1607 | |
| 1608 | /* 3.3V regulator output should be stable within 5 ms */ |
| 1609 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1610 | if (!(ctrl & SDHCI_CTRL_VDD_180)) |
| 1611 | return 0; |
| 1612 | else { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 1613 | pr_info(DRIVER_NAME ": Switching to 3.3V " |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 1614 | "signalling voltage failed\n"); |
| 1615 | return -EIO; |
| 1616 | } |
| 1617 | } else if (!(ctrl & SDHCI_CTRL_VDD_180) && |
| 1618 | (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) { |
| 1619 | /* Stop SDCLK */ |
| 1620 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); |
| 1621 | clk &= ~SDHCI_CLOCK_CARD_EN; |
| 1622 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
| 1623 | |
| 1624 | /* Check whether DAT[3:0] is 0000 */ |
| 1625 | present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); |
| 1626 | if (!((present_state & SDHCI_DATA_LVL_MASK) >> |
| 1627 | SDHCI_DATA_LVL_SHIFT)) { |
| 1628 | /* |
| 1629 | * Enable 1.8V Signal Enable in the Host Control2 |
| 1630 | * register |
| 1631 | */ |
| 1632 | ctrl |= SDHCI_CTRL_VDD_180; |
| 1633 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
| 1634 | |
| 1635 | /* Wait for 5ms */ |
| 1636 | usleep_range(5000, 5500); |
| 1637 | |
| 1638 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1639 | if (ctrl & SDHCI_CTRL_VDD_180) { |
| 1640 | /* Provide SDCLK again and wait for 1ms*/ |
| 1641 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); |
| 1642 | clk |= SDHCI_CLOCK_CARD_EN; |
| 1643 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
| 1644 | usleep_range(1000, 1500); |
| 1645 | |
| 1646 | /* |
| 1647 | * If DAT[3:0] level is 1111b, then the card |
| 1648 | * was successfully switched to 1.8V signaling. |
| 1649 | */ |
| 1650 | present_state = sdhci_readl(host, |
| 1651 | SDHCI_PRESENT_STATE); |
| 1652 | if ((present_state & SDHCI_DATA_LVL_MASK) == |
| 1653 | SDHCI_DATA_LVL_MASK) |
| 1654 | return 0; |
| 1655 | } |
| 1656 | } |
| 1657 | |
| 1658 | /* |
| 1659 | * If we are here, that means the switch to 1.8V signaling |
| 1660 | * failed. We power cycle the card, and retry initialization |
| 1661 | * sequence by setting S18R to 0. |
| 1662 | */ |
| 1663 | pwr = sdhci_readb(host, SDHCI_POWER_CONTROL); |
| 1664 | pwr &= ~SDHCI_POWER_ON; |
| 1665 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
| 1666 | |
| 1667 | /* Wait for 1ms as per the spec */ |
| 1668 | usleep_range(1000, 1500); |
| 1669 | pwr |= SDHCI_POWER_ON; |
| 1670 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
| 1671 | |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 1672 | pr_info(DRIVER_NAME ": Switching to 1.8V signalling " |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 1673 | "voltage failed, retrying with S18R set to 0\n"); |
| 1674 | return -EAGAIN; |
| 1675 | } else |
| 1676 | /* No signal voltage switch required */ |
| 1677 | return 0; |
| 1678 | } |
| 1679 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1680 | static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, |
| 1681 | struct mmc_ios *ios) |
| 1682 | { |
| 1683 | struct sdhci_host *host = mmc_priv(mmc); |
| 1684 | int err; |
| 1685 | |
| 1686 | if (host->version < SDHCI_SPEC_300) |
| 1687 | return 0; |
| 1688 | sdhci_runtime_pm_get(host); |
| 1689 | err = sdhci_do_start_signal_voltage_switch(host, ios); |
| 1690 | sdhci_runtime_pm_put(host); |
| 1691 | return err; |
| 1692 | } |
| 1693 | |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1694 | static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1695 | { |
| 1696 | struct sdhci_host *host; |
| 1697 | u16 ctrl; |
| 1698 | u32 ier; |
| 1699 | int tuning_loop_counter = MAX_TUNING_LOOP; |
| 1700 | unsigned long timeout; |
| 1701 | int err = 0; |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1702 | bool requires_tuning_nonuhs = false; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1703 | |
| 1704 | host = mmc_priv(mmc); |
| 1705 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1706 | sdhci_runtime_pm_get(host); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1707 | disable_irq(host->irq); |
| 1708 | spin_lock(&host->lock); |
| 1709 | |
| 1710 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1711 | |
| 1712 | /* |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1713 | * The Host Controller needs tuning only in case of SDR104 mode |
| 1714 | * and for SDR50 mode when Use Tuning for SDR50 is set in the |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1715 | * Capabilities register. |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1716 | * If the Host Controller supports the HS200 mode then the |
| 1717 | * tuning function has to be executed. |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1718 | */ |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1719 | if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) && |
| 1720 | (host->flags & SDHCI_SDR50_NEEDS_TUNING || |
| 1721 | host->flags & SDHCI_HS200_NEEDS_TUNING)) |
| 1722 | requires_tuning_nonuhs = true; |
| 1723 | |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1724 | if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) || |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1725 | requires_tuning_nonuhs) |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1726 | ctrl |= SDHCI_CTRL_EXEC_TUNING; |
| 1727 | else { |
| 1728 | spin_unlock(&host->lock); |
| 1729 | enable_irq(host->irq); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1730 | sdhci_runtime_pm_put(host); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1731 | return 0; |
| 1732 | } |
| 1733 | |
| 1734 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
| 1735 | |
| 1736 | /* |
| 1737 | * As per the Host Controller spec v3.00, tuning command |
| 1738 | * generates Buffer Read Ready interrupt, so enable that. |
| 1739 | * |
| 1740 | * Note: The spec clearly says that when tuning sequence |
| 1741 | * is being performed, the controller does not generate |
| 1742 | * interrupts other than Buffer Read Ready interrupt. But |
| 1743 | * to make sure we don't hit a controller bug, we _only_ |
| 1744 | * enable Buffer Read Ready interrupt here. |
| 1745 | */ |
| 1746 | ier = sdhci_readl(host, SDHCI_INT_ENABLE); |
| 1747 | sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL); |
| 1748 | |
| 1749 | /* |
| 1750 | * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number |
| 1751 | * of loops reaches 40 times or a timeout of 150ms occurs. |
| 1752 | */ |
| 1753 | timeout = 150; |
| 1754 | do { |
| 1755 | struct mmc_command cmd = {0}; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1756 | struct mmc_request mrq = {NULL}; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1757 | |
| 1758 | if (!tuning_loop_counter && !timeout) |
| 1759 | break; |
| 1760 | |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1761 | cmd.opcode = opcode; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1762 | cmd.arg = 0; |
| 1763 | cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; |
| 1764 | cmd.retries = 0; |
| 1765 | cmd.data = NULL; |
| 1766 | cmd.error = 0; |
| 1767 | |
| 1768 | mrq.cmd = &cmd; |
| 1769 | host->mrq = &mrq; |
| 1770 | |
| 1771 | /* |
| 1772 | * In response to CMD19, the card sends 64 bytes of tuning |
| 1773 | * block to the Host Controller. So we set the block size |
| 1774 | * to 64 here. |
| 1775 | */ |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1776 | if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { |
| 1777 | if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) |
| 1778 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), |
| 1779 | SDHCI_BLOCK_SIZE); |
| 1780 | else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
| 1781 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), |
| 1782 | SDHCI_BLOCK_SIZE); |
| 1783 | } else { |
| 1784 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), |
| 1785 | SDHCI_BLOCK_SIZE); |
| 1786 | } |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1787 | |
| 1788 | /* |
| 1789 | * The tuning block is sent by the card to the host controller. |
| 1790 | * So we set the TRNS_READ bit in the Transfer Mode register. |
| 1791 | * This also takes care of setting DMA Enable and Multi Block |
| 1792 | * Select in the same register to 0. |
| 1793 | */ |
| 1794 | sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); |
| 1795 | |
| 1796 | sdhci_send_command(host, &cmd); |
| 1797 | |
| 1798 | host->cmd = NULL; |
| 1799 | host->mrq = NULL; |
| 1800 | |
| 1801 | spin_unlock(&host->lock); |
| 1802 | enable_irq(host->irq); |
| 1803 | |
| 1804 | /* Wait for Buffer Read Ready interrupt */ |
| 1805 | wait_event_interruptible_timeout(host->buf_ready_int, |
| 1806 | (host->tuning_done == 1), |
| 1807 | msecs_to_jiffies(50)); |
| 1808 | disable_irq(host->irq); |
| 1809 | spin_lock(&host->lock); |
| 1810 | |
| 1811 | if (!host->tuning_done) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 1812 | pr_info(DRIVER_NAME ": Timeout waiting for " |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1813 | "Buffer Read Ready interrupt during tuning " |
| 1814 | "procedure, falling back to fixed sampling " |
| 1815 | "clock\n"); |
| 1816 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1817 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; |
| 1818 | ctrl &= ~SDHCI_CTRL_EXEC_TUNING; |
| 1819 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
| 1820 | |
| 1821 | err = -EIO; |
| 1822 | goto out; |
| 1823 | } |
| 1824 | |
| 1825 | host->tuning_done = 0; |
| 1826 | |
| 1827 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1828 | tuning_loop_counter--; |
| 1829 | timeout--; |
| 1830 | mdelay(1); |
| 1831 | } while (ctrl & SDHCI_CTRL_EXEC_TUNING); |
| 1832 | |
| 1833 | /* |
| 1834 | * The Host Driver has exhausted the maximum number of loops allowed, |
| 1835 | * so use fixed sampling frequency. |
| 1836 | */ |
| 1837 | if (!tuning_loop_counter || !timeout) { |
| 1838 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; |
| 1839 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
| 1840 | } else { |
| 1841 | if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 1842 | pr_info(DRIVER_NAME ": Tuning procedure" |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1843 | " failed, falling back to fixed sampling" |
| 1844 | " clock\n"); |
| 1845 | err = -EIO; |
| 1846 | } |
| 1847 | } |
| 1848 | |
| 1849 | out: |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 1850 | /* |
| 1851 | * If this is the very first time we are here, we start the retuning |
| 1852 | * timer. Since only during the first time, SDHCI_NEEDS_RETUNING |
| 1853 | * flag won't be set, we check this condition before actually starting |
| 1854 | * the timer. |
| 1855 | */ |
| 1856 | if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count && |
| 1857 | (host->tuning_mode == SDHCI_TUNING_MODE_1)) { |
| 1858 | mod_timer(&host->tuning_timer, jiffies + |
| 1859 | host->tuning_count * HZ); |
| 1860 | /* Tuning mode 1 limits the maximum data length to 4MB */ |
| 1861 | mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size; |
| 1862 | } else { |
| 1863 | host->flags &= ~SDHCI_NEEDS_RETUNING; |
| 1864 | /* Reload the new initial value for timer */ |
| 1865 | if (host->tuning_mode == SDHCI_TUNING_MODE_1) |
| 1866 | mod_timer(&host->tuning_timer, jiffies + |
| 1867 | host->tuning_count * HZ); |
| 1868 | } |
| 1869 | |
| 1870 | /* |
| 1871 | * In case tuning fails, host controllers which support re-tuning can |
| 1872 | * try tuning again at a later time, when the re-tuning timer expires. |
| 1873 | * So for these controllers, we return 0. Since there might be other |
| 1874 | * controllers who do not have this capability, we return error for |
| 1875 | * them. |
| 1876 | */ |
| 1877 | if (err && host->tuning_count && |
| 1878 | host->tuning_mode == SDHCI_TUNING_MODE_1) |
| 1879 | err = 0; |
| 1880 | |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1881 | sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier); |
| 1882 | spin_unlock(&host->lock); |
| 1883 | enable_irq(host->irq); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1884 | sdhci_runtime_pm_put(host); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1885 | |
| 1886 | return err; |
| 1887 | } |
| 1888 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1889 | static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable) |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 1890 | { |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 1891 | u16 ctrl; |
| 1892 | unsigned long flags; |
| 1893 | |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 1894 | /* Host Controller v3.00 defines preset value registers */ |
| 1895 | if (host->version < SDHCI_SPEC_300) |
| 1896 | return; |
| 1897 | |
| 1898 | spin_lock_irqsave(&host->lock, flags); |
| 1899 | |
| 1900 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1901 | |
| 1902 | /* |
| 1903 | * We only enable or disable Preset Value if they are not already |
| 1904 | * enabled or disabled respectively. Otherwise, we bail out. |
| 1905 | */ |
| 1906 | if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { |
| 1907 | ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; |
| 1908 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1909 | host->flags |= SDHCI_PV_ENABLED; |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 1910 | } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) { |
| 1911 | ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; |
| 1912 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1913 | host->flags &= ~SDHCI_PV_ENABLED; |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 1914 | } |
| 1915 | |
| 1916 | spin_unlock_irqrestore(&host->lock, flags); |
| 1917 | } |
| 1918 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1919 | static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable) |
| 1920 | { |
| 1921 | struct sdhci_host *host = mmc_priv(mmc); |
| 1922 | |
| 1923 | sdhci_runtime_pm_get(host); |
| 1924 | sdhci_do_enable_preset_value(host, enable); |
| 1925 | sdhci_runtime_pm_put(host); |
| 1926 | } |
| 1927 | |
David Brownell | ab7aefd | 2006-11-12 17:55:30 -0800 | [diff] [blame] | 1928 | static const struct mmc_host_ops sdhci_ops = { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1929 | .request = sdhci_request, |
| 1930 | .set_ios = sdhci_set_ios, |
| 1931 | .get_ro = sdhci_get_ro, |
Adrian Hunter | 20758b6 | 2011-08-29 16:42:12 +0300 | [diff] [blame] | 1932 | .hw_reset = sdhci_hw_reset, |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 1933 | .enable_sdio_irq = sdhci_enable_sdio_irq, |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 1934 | .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1935 | .execute_tuning = sdhci_execute_tuning, |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 1936 | .enable_preset_value = sdhci_enable_preset_value, |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1937 | }; |
| 1938 | |
| 1939 | /*****************************************************************************\ |
| 1940 | * * |
| 1941 | * Tasklets * |
| 1942 | * * |
| 1943 | \*****************************************************************************/ |
| 1944 | |
| 1945 | static void sdhci_tasklet_card(unsigned long param) |
| 1946 | { |
| 1947 | struct sdhci_host *host; |
| 1948 | unsigned long flags; |
| 1949 | |
| 1950 | host = (struct sdhci_host*)param; |
| 1951 | |
| 1952 | spin_lock_irqsave(&host->lock, flags); |
| 1953 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1954 | /* Check host->mrq first in case we are runtime suspended */ |
| 1955 | if (host->mrq && |
| 1956 | !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 1957 | pr_err("%s: Card removed during transfer!\n", |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1958 | mmc_hostname(host->mmc)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 1959 | pr_err("%s: Resetting controller.\n", |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1960 | mmc_hostname(host->mmc)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1961 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1962 | sdhci_reset(host, SDHCI_RESET_CMD); |
| 1963 | sdhci_reset(host, SDHCI_RESET_DATA); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1964 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1965 | host->mrq->cmd->error = -ENOMEDIUM; |
| 1966 | tasklet_schedule(&host->finish_tasklet); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1967 | } |
| 1968 | |
| 1969 | spin_unlock_irqrestore(&host->lock, flags); |
| 1970 | |
Pierre Ossman | 04cf585 | 2008-08-18 22:18:14 +0200 | [diff] [blame] | 1971 | mmc_detect_change(host->mmc, msecs_to_jiffies(200)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1972 | } |
| 1973 | |
| 1974 | static void sdhci_tasklet_finish(unsigned long param) |
| 1975 | { |
| 1976 | struct sdhci_host *host; |
| 1977 | unsigned long flags; |
| 1978 | struct mmc_request *mrq; |
| 1979 | |
| 1980 | host = (struct sdhci_host*)param; |
| 1981 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1982 | spin_lock_irqsave(&host->lock, flags); |
| 1983 | |
Chris Ball | 0c9c99a | 2011-04-27 17:35:31 -0400 | [diff] [blame] | 1984 | /* |
| 1985 | * If this tasklet gets rescheduled while running, it will |
| 1986 | * be run again afterwards but without any active request. |
| 1987 | */ |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1988 | if (!host->mrq) { |
| 1989 | spin_unlock_irqrestore(&host->lock, flags); |
Chris Ball | 0c9c99a | 2011-04-27 17:35:31 -0400 | [diff] [blame] | 1990 | return; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1991 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1992 | |
| 1993 | del_timer(&host->timer); |
| 1994 | |
| 1995 | mrq = host->mrq; |
| 1996 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1997 | /* |
| 1998 | * The controller needs a reset of internal state machines |
| 1999 | * upon error conditions. |
| 2000 | */ |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 2001 | if (!(host->flags & SDHCI_DEVICE_DEAD) && |
Ben Dooks | b7b4d34 | 2011-04-27 14:24:19 +0100 | [diff] [blame] | 2002 | ((mrq->cmd && mrq->cmd->error) || |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 2003 | (mrq->data && (mrq->data->error || |
| 2004 | (mrq->data->stop && mrq->data->stop->error))) || |
| 2005 | (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { |
Pierre Ossman | 645289d | 2006-06-30 02:22:33 -0700 | [diff] [blame] | 2006 | |
| 2007 | /* Some controllers need this kick or reset won't work here */ |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2008 | if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) { |
Pierre Ossman | 645289d | 2006-06-30 02:22:33 -0700 | [diff] [blame] | 2009 | unsigned int clock; |
| 2010 | |
| 2011 | /* This is to force an update */ |
| 2012 | clock = host->clock; |
| 2013 | host->clock = 0; |
| 2014 | sdhci_set_clock(host, clock); |
| 2015 | } |
| 2016 | |
| 2017 | /* Spec says we should do both at the same time, but Ricoh |
| 2018 | controllers do not like that. */ |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2019 | sdhci_reset(host, SDHCI_RESET_CMD); |
| 2020 | sdhci_reset(host, SDHCI_RESET_DATA); |
| 2021 | } |
| 2022 | |
| 2023 | host->mrq = NULL; |
| 2024 | host->cmd = NULL; |
| 2025 | host->data = NULL; |
| 2026 | |
Pierre Ossman | f913431 | 2008-12-21 17:01:48 +0100 | [diff] [blame] | 2027 | #ifndef SDHCI_USE_LEDS_CLASS |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2028 | sdhci_deactivate_led(host); |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 2029 | #endif |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2030 | |
Pierre Ossman | 5f25a66 | 2006-10-04 02:15:39 -0700 | [diff] [blame] | 2031 | mmiowb(); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2032 | spin_unlock_irqrestore(&host->lock, flags); |
| 2033 | |
| 2034 | mmc_request_done(host->mmc, mrq); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2035 | sdhci_runtime_pm_put(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2036 | } |
| 2037 | |
| 2038 | static void sdhci_timeout_timer(unsigned long data) |
| 2039 | { |
| 2040 | struct sdhci_host *host; |
| 2041 | unsigned long flags; |
| 2042 | |
| 2043 | host = (struct sdhci_host*)data; |
| 2044 | |
| 2045 | spin_lock_irqsave(&host->lock, flags); |
| 2046 | |
| 2047 | if (host->mrq) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2048 | pr_err("%s: Timeout waiting for hardware " |
Pierre Ossman | acf1da4 | 2007-02-09 08:29:19 +0100 | [diff] [blame] | 2049 | "interrupt.\n", mmc_hostname(host->mmc)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2050 | sdhci_dumpregs(host); |
| 2051 | |
| 2052 | if (host->data) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 2053 | host->data->error = -ETIMEDOUT; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2054 | sdhci_finish_data(host); |
| 2055 | } else { |
| 2056 | if (host->cmd) |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 2057 | host->cmd->error = -ETIMEDOUT; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2058 | else |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 2059 | host->mrq->cmd->error = -ETIMEDOUT; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2060 | |
| 2061 | tasklet_schedule(&host->finish_tasklet); |
| 2062 | } |
| 2063 | } |
| 2064 | |
Pierre Ossman | 5f25a66 | 2006-10-04 02:15:39 -0700 | [diff] [blame] | 2065 | mmiowb(); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2066 | spin_unlock_irqrestore(&host->lock, flags); |
| 2067 | } |
| 2068 | |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 2069 | static void sdhci_tuning_timer(unsigned long data) |
| 2070 | { |
| 2071 | struct sdhci_host *host; |
| 2072 | unsigned long flags; |
| 2073 | |
| 2074 | host = (struct sdhci_host *)data; |
| 2075 | |
| 2076 | spin_lock_irqsave(&host->lock, flags); |
| 2077 | |
| 2078 | host->flags |= SDHCI_NEEDS_RETUNING; |
| 2079 | |
| 2080 | spin_unlock_irqrestore(&host->lock, flags); |
| 2081 | } |
| 2082 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2083 | /*****************************************************************************\ |
| 2084 | * * |
| 2085 | * Interrupt handling * |
| 2086 | * * |
| 2087 | \*****************************************************************************/ |
| 2088 | |
| 2089 | static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) |
| 2090 | { |
| 2091 | BUG_ON(intmask == 0); |
| 2092 | |
| 2093 | if (!host->cmd) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2094 | pr_err("%s: Got command interrupt 0x%08x even " |
Pierre Ossman | b67ac3f | 2007-08-12 17:29:47 +0200 | [diff] [blame] | 2095 | "though no command operation was in progress.\n", |
| 2096 | mmc_hostname(host->mmc), (unsigned)intmask); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2097 | sdhci_dumpregs(host); |
| 2098 | return; |
| 2099 | } |
| 2100 | |
Pierre Ossman | 43b58b3 | 2007-07-25 23:15:27 +0200 | [diff] [blame] | 2101 | if (intmask & SDHCI_INT_TIMEOUT) |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 2102 | host->cmd->error = -ETIMEDOUT; |
| 2103 | else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT | |
| 2104 | SDHCI_INT_INDEX)) |
| 2105 | host->cmd->error = -EILSEQ; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2106 | |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 2107 | if (host->cmd->error) { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2108 | tasklet_schedule(&host->finish_tasklet); |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 2109 | return; |
| 2110 | } |
| 2111 | |
| 2112 | /* |
| 2113 | * The host can send and interrupt when the busy state has |
| 2114 | * ended, allowing us to wait without wasting CPU cycles. |
| 2115 | * Unfortunately this is overloaded on the "data complete" |
| 2116 | * interrupt, so we need to take some care when handling |
| 2117 | * it. |
| 2118 | * |
| 2119 | * Note: The 1.0 specification is a bit ambiguous about this |
| 2120 | * feature so there might be some problems with older |
| 2121 | * controllers. |
| 2122 | */ |
| 2123 | if (host->cmd->flags & MMC_RSP_BUSY) { |
| 2124 | if (host->cmd->data) |
| 2125 | DBG("Cannot wait for busy signal when also " |
| 2126 | "doing a data transfer"); |
Ben Dooks | f945405 | 2009-02-20 20:33:08 +0300 | [diff] [blame] | 2127 | else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)) |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 2128 | return; |
Ben Dooks | f945405 | 2009-02-20 20:33:08 +0300 | [diff] [blame] | 2129 | |
| 2130 | /* The controller does not support the end-of-busy IRQ, |
| 2131 | * fall through and take the SDHCI_INT_RESPONSE */ |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 2132 | } |
| 2133 | |
| 2134 | if (intmask & SDHCI_INT_RESPONSE) |
Pierre Ossman | 43b58b3 | 2007-07-25 23:15:27 +0200 | [diff] [blame] | 2135 | sdhci_finish_command(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2136 | } |
| 2137 | |
George G. Davis | 0957c33 | 2010-02-18 12:32:12 -0500 | [diff] [blame] | 2138 | #ifdef CONFIG_MMC_DEBUG |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2139 | static void sdhci_show_adma_error(struct sdhci_host *host) |
| 2140 | { |
| 2141 | const char *name = mmc_hostname(host->mmc); |
| 2142 | u8 *desc = host->adma_desc; |
| 2143 | __le32 *dma; |
| 2144 | __le16 *len; |
| 2145 | u8 attr; |
| 2146 | |
| 2147 | sdhci_dumpregs(host); |
| 2148 | |
| 2149 | while (true) { |
| 2150 | dma = (__le32 *)(desc + 4); |
| 2151 | len = (__le16 *)(desc + 2); |
| 2152 | attr = *desc; |
| 2153 | |
| 2154 | DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", |
| 2155 | name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr); |
| 2156 | |
| 2157 | desc += 8; |
| 2158 | |
| 2159 | if (attr & 2) |
| 2160 | break; |
| 2161 | } |
| 2162 | } |
| 2163 | #else |
| 2164 | static void sdhci_show_adma_error(struct sdhci_host *host) { } |
| 2165 | #endif |
| 2166 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2167 | static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) |
| 2168 | { |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 2169 | u32 command; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2170 | BUG_ON(intmask == 0); |
| 2171 | |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2172 | /* CMD19 generates _only_ Buffer Read Ready interrupt */ |
| 2173 | if (intmask & SDHCI_INT_DATA_AVAIL) { |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 2174 | command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); |
| 2175 | if (command == MMC_SEND_TUNING_BLOCK || |
| 2176 | command == MMC_SEND_TUNING_BLOCK_HS200) { |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2177 | host->tuning_done = 1; |
| 2178 | wake_up(&host->buf_ready_int); |
| 2179 | return; |
| 2180 | } |
| 2181 | } |
| 2182 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2183 | if (!host->data) { |
| 2184 | /* |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 2185 | * The "data complete" interrupt is also used to |
| 2186 | * indicate that a busy state has ended. See comment |
| 2187 | * above in sdhci_cmd_irq(). |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2188 | */ |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 2189 | if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) { |
| 2190 | if (intmask & SDHCI_INT_DATA_END) { |
| 2191 | sdhci_finish_command(host); |
| 2192 | return; |
| 2193 | } |
| 2194 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2195 | |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2196 | pr_err("%s: Got data interrupt 0x%08x even " |
Pierre Ossman | b67ac3f | 2007-08-12 17:29:47 +0200 | [diff] [blame] | 2197 | "though no data operation was in progress.\n", |
| 2198 | mmc_hostname(host->mmc), (unsigned)intmask); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2199 | sdhci_dumpregs(host); |
| 2200 | |
| 2201 | return; |
| 2202 | } |
| 2203 | |
| 2204 | if (intmask & SDHCI_INT_DATA_TIMEOUT) |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 2205 | host->data->error = -ETIMEDOUT; |
Aries Lee | 22113ef | 2010-12-15 08:14:24 +0100 | [diff] [blame] | 2206 | else if (intmask & SDHCI_INT_DATA_END_BIT) |
| 2207 | host->data->error = -EILSEQ; |
| 2208 | else if ((intmask & SDHCI_INT_DATA_CRC) && |
| 2209 | SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) |
| 2210 | != MMC_BUS_TEST_R) |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 2211 | host->data->error = -EILSEQ; |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2212 | else if (intmask & SDHCI_INT_ADMA_ERROR) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2213 | pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2214 | sdhci_show_adma_error(host); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 2215 | host->data->error = -EIO; |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2216 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2217 | |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 2218 | if (host->data->error) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2219 | sdhci_finish_data(host); |
| 2220 | else { |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 2221 | if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2222 | sdhci_transfer_pio(host); |
| 2223 | |
Pierre Ossman | 6ba736a | 2007-05-13 22:39:23 +0200 | [diff] [blame] | 2224 | /* |
| 2225 | * We currently don't do anything fancy with DMA |
| 2226 | * boundaries, but as we can't disable the feature |
| 2227 | * we need to at least restart the transfer. |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 2228 | * |
| 2229 | * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) |
| 2230 | * should return a valid address to continue from, but as |
| 2231 | * some controllers are faulty, don't trust them. |
Pierre Ossman | 6ba736a | 2007-05-13 22:39:23 +0200 | [diff] [blame] | 2232 | */ |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 2233 | if (intmask & SDHCI_INT_DMA_END) { |
| 2234 | u32 dmastart, dmanow; |
| 2235 | dmastart = sg_dma_address(host->data->sg); |
| 2236 | dmanow = dmastart + host->data->bytes_xfered; |
| 2237 | /* |
| 2238 | * Force update to the next DMA block boundary. |
| 2239 | */ |
| 2240 | dmanow = (dmanow & |
| 2241 | ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + |
| 2242 | SDHCI_DEFAULT_BOUNDARY_SIZE; |
| 2243 | host->data->bytes_xfered = dmanow - dmastart; |
| 2244 | DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," |
| 2245 | " next 0x%08x\n", |
| 2246 | mmc_hostname(host->mmc), dmastart, |
| 2247 | host->data->bytes_xfered, dmanow); |
| 2248 | sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); |
| 2249 | } |
Pierre Ossman | 6ba736a | 2007-05-13 22:39:23 +0200 | [diff] [blame] | 2250 | |
Pierre Ossman | e538fbe | 2007-08-12 16:46:32 +0200 | [diff] [blame] | 2251 | if (intmask & SDHCI_INT_DATA_END) { |
| 2252 | if (host->cmd) { |
| 2253 | /* |
| 2254 | * Data managed to finish before the |
| 2255 | * command completed. Make sure we do |
| 2256 | * things in the proper order. |
| 2257 | */ |
| 2258 | host->data_early = 1; |
| 2259 | } else { |
| 2260 | sdhci_finish_data(host); |
| 2261 | } |
| 2262 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2263 | } |
| 2264 | } |
| 2265 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 2266 | static irqreturn_t sdhci_irq(int irq, void *dev_id) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2267 | { |
| 2268 | irqreturn_t result; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2269 | struct sdhci_host *host = dev_id; |
Alexander Stein | 6379b23 | 2012-03-14 09:52:10 +0100 | [diff] [blame] | 2270 | u32 intmask, unexpected = 0; |
| 2271 | int cardint = 0, max_loops = 16; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2272 | |
| 2273 | spin_lock(&host->lock); |
| 2274 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2275 | if (host->runtime_suspended) { |
| 2276 | spin_unlock(&host->lock); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2277 | pr_warning("%s: got irq while runtime suspended\n", |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2278 | mmc_hostname(host->mmc)); |
| 2279 | return IRQ_HANDLED; |
| 2280 | } |
| 2281 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 2282 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2283 | |
Mark Lord | 62df67a5 | 2007-03-06 13:30:13 +0100 | [diff] [blame] | 2284 | if (!intmask || intmask == 0xffffffff) { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2285 | result = IRQ_NONE; |
| 2286 | goto out; |
| 2287 | } |
| 2288 | |
Alexander Stein | 6379b23 | 2012-03-14 09:52:10 +0100 | [diff] [blame] | 2289 | again: |
Pierre Ossman | b69c905 | 2008-03-08 23:44:25 +0100 | [diff] [blame] | 2290 | DBG("*** %s got interrupt: 0x%08x\n", |
| 2291 | mmc_hostname(host->mmc), intmask); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2292 | |
Pierre Ossman | 3192a28 | 2006-06-30 02:22:26 -0700 | [diff] [blame] | 2293 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
Shawn Guo | d25928d | 2011-06-21 22:41:48 +0800 | [diff] [blame] | 2294 | u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & |
| 2295 | SDHCI_CARD_PRESENT; |
| 2296 | |
| 2297 | /* |
| 2298 | * There is a observation on i.mx esdhc. INSERT bit will be |
| 2299 | * immediately set again when it gets cleared, if a card is |
| 2300 | * inserted. We have to mask the irq to prevent interrupt |
| 2301 | * storm which will freeze the system. And the REMOVE gets |
| 2302 | * the same situation. |
| 2303 | * |
| 2304 | * More testing are needed here to ensure it works for other |
| 2305 | * platforms though. |
| 2306 | */ |
| 2307 | sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT : |
| 2308 | SDHCI_INT_CARD_REMOVE); |
| 2309 | sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE : |
| 2310 | SDHCI_INT_CARD_INSERT); |
| 2311 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 2312 | sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | |
Shawn Guo | d25928d | 2011-06-21 22:41:48 +0800 | [diff] [blame] | 2313 | SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); |
| 2314 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2315 | tasklet_schedule(&host->card_tasklet); |
Pierre Ossman | 3192a28 | 2006-06-30 02:22:26 -0700 | [diff] [blame] | 2316 | } |
| 2317 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2318 | if (intmask & SDHCI_INT_CMD_MASK) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 2319 | sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, |
| 2320 | SDHCI_INT_STATUS); |
Pierre Ossman | 3192a28 | 2006-06-30 02:22:26 -0700 | [diff] [blame] | 2321 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2322 | } |
| 2323 | |
| 2324 | if (intmask & SDHCI_INT_DATA_MASK) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 2325 | sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK, |
| 2326 | SDHCI_INT_STATUS); |
Pierre Ossman | 3192a28 | 2006-06-30 02:22:26 -0700 | [diff] [blame] | 2327 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2328 | } |
| 2329 | |
| 2330 | intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); |
| 2331 | |
Pierre Ossman | 964f9ce | 2007-07-20 18:20:36 +0200 | [diff] [blame] | 2332 | intmask &= ~SDHCI_INT_ERROR; |
| 2333 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2334 | if (intmask & SDHCI_INT_BUS_POWER) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2335 | pr_err("%s: Card is consuming too much power!\n", |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2336 | mmc_hostname(host->mmc)); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 2337 | sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2338 | } |
| 2339 | |
Rolf Eike Beer | 9d26a5d | 2007-06-26 13:31:16 +0200 | [diff] [blame] | 2340 | intmask &= ~SDHCI_INT_BUS_POWER; |
Pierre Ossman | 3192a28 | 2006-06-30 02:22:26 -0700 | [diff] [blame] | 2341 | |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 2342 | if (intmask & SDHCI_INT_CARD_INT) |
| 2343 | cardint = 1; |
| 2344 | |
| 2345 | intmask &= ~SDHCI_INT_CARD_INT; |
| 2346 | |
Pierre Ossman | 3192a28 | 2006-06-30 02:22:26 -0700 | [diff] [blame] | 2347 | if (intmask) { |
Alexander Stein | 6379b23 | 2012-03-14 09:52:10 +0100 | [diff] [blame] | 2348 | unexpected |= intmask; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 2349 | sdhci_writel(host, intmask, SDHCI_INT_STATUS); |
Pierre Ossman | 3192a28 | 2006-06-30 02:22:26 -0700 | [diff] [blame] | 2350 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2351 | |
| 2352 | result = IRQ_HANDLED; |
| 2353 | |
Alexander Stein | 6379b23 | 2012-03-14 09:52:10 +0100 | [diff] [blame] | 2354 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
| 2355 | if (intmask && --max_loops) |
| 2356 | goto again; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2357 | out: |
| 2358 | spin_unlock(&host->lock); |
| 2359 | |
Alexander Stein | 6379b23 | 2012-03-14 09:52:10 +0100 | [diff] [blame] | 2360 | if (unexpected) { |
| 2361 | pr_err("%s: Unexpected interrupt 0x%08x.\n", |
| 2362 | mmc_hostname(host->mmc), unexpected); |
| 2363 | sdhci_dumpregs(host); |
| 2364 | } |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 2365 | /* |
| 2366 | * We have to delay this as it calls back into the driver. |
| 2367 | */ |
| 2368 | if (cardint) |
| 2369 | mmc_signal_sdio_irq(host->mmc); |
| 2370 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2371 | return result; |
| 2372 | } |
| 2373 | |
| 2374 | /*****************************************************************************\ |
| 2375 | * * |
| 2376 | * Suspend/resume * |
| 2377 | * * |
| 2378 | \*****************************************************************************/ |
| 2379 | |
| 2380 | #ifdef CONFIG_PM |
| 2381 | |
Manuel Lauss | 29495aa | 2011-11-03 11:09:45 +0100 | [diff] [blame] | 2382 | int sdhci_suspend_host(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2383 | { |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2384 | int ret; |
Aaron Lu | 38a60ea | 2012-01-04 10:07:43 +0800 | [diff] [blame] | 2385 | bool has_tuning_timer; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2386 | |
Chris Ball | a1b13b4 | 2012-02-06 00:43:59 -0500 | [diff] [blame] | 2387 | if (host->ops->platform_suspend) |
| 2388 | host->ops->platform_suspend(host); |
| 2389 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 2390 | sdhci_disable_card_detection(host); |
| 2391 | |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 2392 | /* Disable tuning since we are suspending */ |
Aaron Lu | 38a60ea | 2012-01-04 10:07:43 +0800 | [diff] [blame] | 2393 | has_tuning_timer = host->version >= SDHCI_SPEC_300 && |
| 2394 | host->tuning_count && host->tuning_mode == SDHCI_TUNING_MODE_1; |
| 2395 | if (has_tuning_timer) { |
Aaron Lu | c6ced0d | 2011-12-28 11:11:12 +0800 | [diff] [blame] | 2396 | del_timer_sync(&host->tuning_timer); |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 2397 | host->flags &= ~SDHCI_NEEDS_RETUNING; |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 2398 | } |
| 2399 | |
Matt Fleming | 1a13f8f | 2010-05-26 14:42:08 -0700 | [diff] [blame] | 2400 | ret = mmc_suspend_host(host->mmc); |
Aaron Lu | 38a60ea | 2012-01-04 10:07:43 +0800 | [diff] [blame] | 2401 | if (ret) { |
| 2402 | if (has_tuning_timer) { |
| 2403 | host->flags |= SDHCI_NEEDS_RETUNING; |
| 2404 | mod_timer(&host->tuning_timer, jiffies + |
| 2405 | host->tuning_count * HZ); |
| 2406 | } |
| 2407 | |
| 2408 | sdhci_enable_card_detection(host); |
| 2409 | |
Pierre Ossman | df1c4b7 | 2007-01-30 07:55:15 +0100 | [diff] [blame] | 2410 | return ret; |
Aaron Lu | 38a60ea | 2012-01-04 10:07:43 +0800 | [diff] [blame] | 2411 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2412 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2413 | free_irq(host->irq, host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2414 | |
Marek Szyprowski | 9bea3c8 | 2010-08-10 18:01:59 -0700 | [diff] [blame] | 2415 | return ret; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2416 | } |
| 2417 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2418 | EXPORT_SYMBOL_GPL(sdhci_suspend_host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2419 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2420 | int sdhci_resume_host(struct sdhci_host *host) |
| 2421 | { |
| 2422 | int ret; |
| 2423 | |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2424 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2425 | if (host->ops->enable_dma) |
| 2426 | host->ops->enable_dma(host); |
| 2427 | } |
| 2428 | |
| 2429 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, |
| 2430 | mmc_hostname(host->mmc), host); |
| 2431 | if (ret) |
| 2432 | return ret; |
| 2433 | |
Adrian Hunter | 6308d29 | 2012-02-07 14:48:54 +0200 | [diff] [blame] | 2434 | if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && |
| 2435 | (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { |
| 2436 | /* Card keeps power but host controller does not */ |
| 2437 | sdhci_init(host, 0); |
| 2438 | host->pwr = 0; |
| 2439 | host->clock = 0; |
| 2440 | sdhci_do_set_ios(host, &host->mmc->ios); |
| 2441 | } else { |
| 2442 | sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); |
| 2443 | mmiowb(); |
| 2444 | } |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2445 | |
| 2446 | ret = mmc_resume_host(host->mmc); |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 2447 | sdhci_enable_card_detection(host); |
| 2448 | |
Chris Ball | a1b13b4 | 2012-02-06 00:43:59 -0500 | [diff] [blame] | 2449 | if (host->ops->platform_resume) |
| 2450 | host->ops->platform_resume(host); |
| 2451 | |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 2452 | /* Set the re-tuning expiration flag */ |
| 2453 | if ((host->version >= SDHCI_SPEC_300) && host->tuning_count && |
| 2454 | (host->tuning_mode == SDHCI_TUNING_MODE_1)) |
| 2455 | host->flags |= SDHCI_NEEDS_RETUNING; |
| 2456 | |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 2457 | return ret; |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2458 | } |
| 2459 | |
| 2460 | EXPORT_SYMBOL_GPL(sdhci_resume_host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2461 | |
Daniel Drake | 5f61970 | 2010-11-04 22:20:39 +0000 | [diff] [blame] | 2462 | void sdhci_enable_irq_wakeups(struct sdhci_host *host) |
| 2463 | { |
| 2464 | u8 val; |
| 2465 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); |
| 2466 | val |= SDHCI_WAKE_ON_INT; |
| 2467 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); |
| 2468 | } |
| 2469 | |
| 2470 | EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); |
| 2471 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2472 | #endif /* CONFIG_PM */ |
| 2473 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2474 | #ifdef CONFIG_PM_RUNTIME |
| 2475 | |
| 2476 | static int sdhci_runtime_pm_get(struct sdhci_host *host) |
| 2477 | { |
| 2478 | return pm_runtime_get_sync(host->mmc->parent); |
| 2479 | } |
| 2480 | |
| 2481 | static int sdhci_runtime_pm_put(struct sdhci_host *host) |
| 2482 | { |
| 2483 | pm_runtime_mark_last_busy(host->mmc->parent); |
| 2484 | return pm_runtime_put_autosuspend(host->mmc->parent); |
| 2485 | } |
| 2486 | |
| 2487 | int sdhci_runtime_suspend_host(struct sdhci_host *host) |
| 2488 | { |
| 2489 | unsigned long flags; |
| 2490 | int ret = 0; |
| 2491 | |
| 2492 | /* Disable tuning since we are suspending */ |
| 2493 | if (host->version >= SDHCI_SPEC_300 && |
| 2494 | host->tuning_mode == SDHCI_TUNING_MODE_1) { |
| 2495 | del_timer_sync(&host->tuning_timer); |
| 2496 | host->flags &= ~SDHCI_NEEDS_RETUNING; |
| 2497 | } |
| 2498 | |
| 2499 | spin_lock_irqsave(&host->lock, flags); |
| 2500 | sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); |
| 2501 | spin_unlock_irqrestore(&host->lock, flags); |
| 2502 | |
| 2503 | synchronize_irq(host->irq); |
| 2504 | |
| 2505 | spin_lock_irqsave(&host->lock, flags); |
| 2506 | host->runtime_suspended = true; |
| 2507 | spin_unlock_irqrestore(&host->lock, flags); |
| 2508 | |
| 2509 | return ret; |
| 2510 | } |
| 2511 | EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); |
| 2512 | |
| 2513 | int sdhci_runtime_resume_host(struct sdhci_host *host) |
| 2514 | { |
| 2515 | unsigned long flags; |
| 2516 | int ret = 0, host_flags = host->flags; |
| 2517 | |
| 2518 | if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
| 2519 | if (host->ops->enable_dma) |
| 2520 | host->ops->enable_dma(host); |
| 2521 | } |
| 2522 | |
| 2523 | sdhci_init(host, 0); |
| 2524 | |
| 2525 | /* Force clock and power re-program */ |
| 2526 | host->pwr = 0; |
| 2527 | host->clock = 0; |
| 2528 | sdhci_do_set_ios(host, &host->mmc->ios); |
| 2529 | |
| 2530 | sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios); |
| 2531 | if (host_flags & SDHCI_PV_ENABLED) |
| 2532 | sdhci_do_enable_preset_value(host, true); |
| 2533 | |
| 2534 | /* Set the re-tuning expiration flag */ |
| 2535 | if ((host->version >= SDHCI_SPEC_300) && host->tuning_count && |
| 2536 | (host->tuning_mode == SDHCI_TUNING_MODE_1)) |
| 2537 | host->flags |= SDHCI_NEEDS_RETUNING; |
| 2538 | |
| 2539 | spin_lock_irqsave(&host->lock, flags); |
| 2540 | |
| 2541 | host->runtime_suspended = false; |
| 2542 | |
| 2543 | /* Enable SDIO IRQ */ |
| 2544 | if ((host->flags & SDHCI_SDIO_IRQ_ENABLED)) |
| 2545 | sdhci_enable_sdio_irq_nolock(host, true); |
| 2546 | |
| 2547 | /* Enable Card Detection */ |
| 2548 | sdhci_enable_card_detection(host); |
| 2549 | |
| 2550 | spin_unlock_irqrestore(&host->lock, flags); |
| 2551 | |
| 2552 | return ret; |
| 2553 | } |
| 2554 | EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); |
| 2555 | |
| 2556 | #endif |
| 2557 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2558 | /*****************************************************************************\ |
| 2559 | * * |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2560 | * Device allocation/registration * |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2561 | * * |
| 2562 | \*****************************************************************************/ |
| 2563 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2564 | struct sdhci_host *sdhci_alloc_host(struct device *dev, |
| 2565 | size_t priv_size) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2566 | { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2567 | struct mmc_host *mmc; |
| 2568 | struct sdhci_host *host; |
| 2569 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2570 | WARN_ON(dev == NULL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2571 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2572 | mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2573 | if (!mmc) |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2574 | return ERR_PTR(-ENOMEM); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2575 | |
| 2576 | host = mmc_priv(mmc); |
| 2577 | host->mmc = mmc; |
| 2578 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2579 | return host; |
| 2580 | } |
Pierre Ossman | 8a4da14 | 2006-10-04 02:15:40 -0700 | [diff] [blame] | 2581 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2582 | EXPORT_SYMBOL_GPL(sdhci_alloc_host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2583 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2584 | int sdhci_add_host(struct sdhci_host *host) |
| 2585 | { |
| 2586 | struct mmc_host *mmc; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2587 | u32 caps[2]; |
| 2588 | u32 max_current_caps; |
| 2589 | unsigned int ocr_avail; |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2590 | int ret; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2591 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2592 | WARN_ON(host == NULL); |
| 2593 | if (host == NULL) |
| 2594 | return -EINVAL; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2595 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2596 | mmc = host->mmc; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2597 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2598 | if (debug_quirks) |
| 2599 | host->quirks = debug_quirks; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2600 | if (debug_quirks2) |
| 2601 | host->quirks2 = debug_quirks2; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2602 | |
Pierre Ossman | d96649e | 2006-06-30 02:22:30 -0700 | [diff] [blame] | 2603 | sdhci_reset(host, SDHCI_RESET_ALL); |
| 2604 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 2605 | host->version = sdhci_readw(host, SDHCI_HOST_VERSION); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 2606 | host->version = (host->version & SDHCI_SPEC_VER_MASK) |
| 2607 | >> SDHCI_SPEC_VER_SHIFT; |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 2608 | if (host->version > SDHCI_SPEC_300) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2609 | pr_err("%s: Unknown controller version (%d). " |
Pierre Ossman | b69c905 | 2008-03-08 23:44:25 +0100 | [diff] [blame] | 2610 | "You may experience problems.\n", mmc_hostname(mmc), |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 2611 | host->version); |
Pierre Ossman | 4a96550 | 2006-06-30 02:22:29 -0700 | [diff] [blame] | 2612 | } |
| 2613 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2614 | caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps : |
Maxim Levitsky | ccc92c2 | 2010-08-10 18:01:42 -0700 | [diff] [blame] | 2615 | sdhci_readl(host, SDHCI_CAPABILITIES); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2616 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2617 | caps[1] = (host->version >= SDHCI_SPEC_300) ? |
| 2618 | sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0; |
| 2619 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2620 | if (host->quirks & SDHCI_QUIRK_FORCE_DMA) |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2621 | host->flags |= SDHCI_USE_SDMA; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2622 | else if (!(caps[0] & SDHCI_CAN_DO_SDMA)) |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2623 | DBG("Controller doesn't have SDMA capability\n"); |
Pierre Ossman | 6743527 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 2624 | else |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2625 | host->flags |= SDHCI_USE_SDMA; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2626 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2627 | if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2628 | (host->flags & SDHCI_USE_SDMA)) { |
Rolf Eike Beer | cee687c | 2007-11-02 15:22:30 +0100 | [diff] [blame] | 2629 | DBG("Disabling DMA as it is marked broken\n"); |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2630 | host->flags &= ~SDHCI_USE_SDMA; |
Feng Tang | 7c168e3 | 2007-09-30 12:44:18 +0200 | [diff] [blame] | 2631 | } |
| 2632 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2633 | if ((host->version >= SDHCI_SPEC_200) && |
| 2634 | (caps[0] & SDHCI_CAN_DO_ADMA2)) |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2635 | host->flags |= SDHCI_USE_ADMA; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 2636 | |
| 2637 | if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && |
| 2638 | (host->flags & SDHCI_USE_ADMA)) { |
| 2639 | DBG("Disabling ADMA as it is marked broken\n"); |
| 2640 | host->flags &= ~SDHCI_USE_ADMA; |
| 2641 | } |
| 2642 | |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2643 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2644 | if (host->ops->enable_dma) { |
| 2645 | if (host->ops->enable_dma(host)) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2646 | pr_warning("%s: No suitable DMA " |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2647 | "available. Falling back to PIO.\n", |
| 2648 | mmc_hostname(mmc)); |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2649 | host->flags &= |
| 2650 | ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2651 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2652 | } |
| 2653 | } |
| 2654 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 2655 | if (host->flags & SDHCI_USE_ADMA) { |
| 2656 | /* |
| 2657 | * We need to allocate descriptors for all sg entries |
| 2658 | * (128) and potentially one alignment transfer for |
| 2659 | * each of those entries. |
| 2660 | */ |
| 2661 | host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL); |
| 2662 | host->align_buffer = kmalloc(128 * 4, GFP_KERNEL); |
| 2663 | if (!host->adma_desc || !host->align_buffer) { |
| 2664 | kfree(host->adma_desc); |
| 2665 | kfree(host->align_buffer); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2666 | pr_warning("%s: Unable to allocate ADMA " |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 2667 | "buffers. Falling back to standard DMA.\n", |
| 2668 | mmc_hostname(mmc)); |
| 2669 | host->flags &= ~SDHCI_USE_ADMA; |
| 2670 | } |
| 2671 | } |
| 2672 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 2673 | /* |
| 2674 | * If we use DMA, then it's up to the caller to set the DMA |
| 2675 | * mask, but PIO does not need the hw shim so we set a new |
| 2676 | * mask here in that case. |
| 2677 | */ |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2678 | if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 2679 | host->dma_mask = DMA_BIT_MASK(64); |
| 2680 | mmc_dev(host->mmc)->dma_mask = &host->dma_mask; |
| 2681 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2682 | |
Zhangfei Gao | c4687d5 | 2010-08-20 14:02:36 -0400 | [diff] [blame] | 2683 | if (host->version >= SDHCI_SPEC_300) |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2684 | host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK) |
Zhangfei Gao | c4687d5 | 2010-08-20 14:02:36 -0400 | [diff] [blame] | 2685 | >> SDHCI_CLOCK_BASE_SHIFT; |
| 2686 | else |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2687 | host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK) |
Zhangfei Gao | c4687d5 | 2010-08-20 14:02:36 -0400 | [diff] [blame] | 2688 | >> SDHCI_CLOCK_BASE_SHIFT; |
| 2689 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2690 | host->max_clk *= 1000000; |
Anton Vorontsov | f27f47e | 2010-05-26 14:41:53 -0700 | [diff] [blame] | 2691 | if (host->max_clk == 0 || host->quirks & |
| 2692 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { |
Ben Dooks | 4240ff0 | 2009-03-17 00:13:57 +0300 | [diff] [blame] | 2693 | if (!host->ops->get_max_clock) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2694 | pr_err("%s: Hardware doesn't specify base clock " |
Ben Dooks | 4240ff0 | 2009-03-17 00:13:57 +0300 | [diff] [blame] | 2695 | "frequency.\n", mmc_hostname(mmc)); |
| 2696 | return -ENODEV; |
| 2697 | } |
| 2698 | host->max_clk = host->ops->get_max_clock(host); |
| 2699 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2700 | |
| 2701 | /* |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 2702 | * In case of Host Controller v3.00, find out whether clock |
| 2703 | * multiplier is supported. |
| 2704 | */ |
| 2705 | host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >> |
| 2706 | SDHCI_CLOCK_MUL_SHIFT; |
| 2707 | |
| 2708 | /* |
| 2709 | * In case the value in Clock Multiplier is 0, then programmable |
| 2710 | * clock mode is not supported, otherwise the actual clock |
| 2711 | * multiplier is one more than the value of Clock Multiplier |
| 2712 | * in the Capabilities Register. |
| 2713 | */ |
| 2714 | if (host->clk_mul) |
| 2715 | host->clk_mul += 1; |
| 2716 | |
| 2717 | /* |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2718 | * Set host parameters. |
| 2719 | */ |
| 2720 | mmc->ops = &sdhci_ops; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 2721 | mmc->f_max = host->max_clk; |
Marek Szyprowski | ce5f036 | 2010-08-10 18:01:56 -0700 | [diff] [blame] | 2722 | if (host->ops->get_min_clock) |
Anton Vorontsov | a9e58f2 | 2009-07-29 15:04:16 -0700 | [diff] [blame] | 2723 | mmc->f_min = host->ops->get_min_clock(host); |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 2724 | else if (host->version >= SDHCI_SPEC_300) { |
| 2725 | if (host->clk_mul) { |
| 2726 | mmc->f_min = (host->max_clk * host->clk_mul) / 1024; |
| 2727 | mmc->f_max = host->max_clk * host->clk_mul; |
| 2728 | } else |
| 2729 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; |
| 2730 | } else |
Zhangfei Gao | 0397526 | 2010-09-20 15:15:18 -0400 | [diff] [blame] | 2731 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 2732 | |
Andy Shevchenko | 272308c | 2011-08-03 18:36:00 +0300 | [diff] [blame] | 2733 | host->timeout_clk = |
| 2734 | (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; |
| 2735 | if (host->timeout_clk == 0) { |
| 2736 | if (host->ops->get_timeout_clock) { |
| 2737 | host->timeout_clk = host->ops->get_timeout_clock(host); |
| 2738 | } else if (!(host->quirks & |
| 2739 | SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2740 | pr_err("%s: Hardware doesn't specify timeout clock " |
Andy Shevchenko | 272308c | 2011-08-03 18:36:00 +0300 | [diff] [blame] | 2741 | "frequency.\n", mmc_hostname(mmc)); |
| 2742 | return -ENODEV; |
| 2743 | } |
| 2744 | } |
| 2745 | if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT) |
| 2746 | host->timeout_clk *= 1000; |
| 2747 | |
| 2748 | if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) |
Andy Shevchenko | 65be3fe | 2011-08-03 18:36:01 +0300 | [diff] [blame] | 2749 | host->timeout_clk = mmc->f_max / 1000; |
Andy Shevchenko | 272308c | 2011-08-03 18:36:00 +0300 | [diff] [blame] | 2750 | |
Andy Shevchenko | 65be3fe | 2011-08-03 18:36:01 +0300 | [diff] [blame] | 2751 | mmc->max_discard_to = (1 << 27) / host->timeout_clk; |
Adrian Hunter | 58d1246 | 2011-06-28 17:16:03 +0300 | [diff] [blame] | 2752 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 2753 | mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; |
| 2754 | |
| 2755 | if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) |
| 2756 | host->flags |= SDHCI_AUTO_CMD12; |
Anton Vorontsov | 5fe23c7 | 2009-06-18 00:14:08 +0400 | [diff] [blame] | 2757 | |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 2758 | /* Auto-CMD23 stuff only works in ADMA or PIO. */ |
Andrei Warkentin | 4f3d3e9 | 2011-05-25 10:42:50 -0400 | [diff] [blame] | 2759 | if ((host->version >= SDHCI_SPEC_300) && |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 2760 | ((host->flags & SDHCI_USE_ADMA) || |
Andrei Warkentin | 4f3d3e9 | 2011-05-25 10:42:50 -0400 | [diff] [blame] | 2761 | !(host->flags & SDHCI_USE_SDMA))) { |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 2762 | host->flags |= SDHCI_AUTO_CMD23; |
| 2763 | DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); |
| 2764 | } else { |
| 2765 | DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); |
| 2766 | } |
| 2767 | |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 2768 | /* |
| 2769 | * A controller may support 8-bit width, but the board itself |
| 2770 | * might not have the pins brought out. Boards that support |
| 2771 | * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in |
| 2772 | * their platform code before calling sdhci_add_host(), and we |
| 2773 | * won't assume 8-bit width for hosts without that CAP. |
| 2774 | */ |
Anton Vorontsov | 5fe23c7 | 2009-06-18 00:14:08 +0400 | [diff] [blame] | 2775 | if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 2776 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2777 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2778 | if (caps[0] & SDHCI_CAN_DO_HISPD) |
Zhangfei Gao | a29e7e1 | 2010-08-16 21:15:32 -0400 | [diff] [blame] | 2779 | mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; |
Pierre Ossman | cd9277c | 2007-02-18 12:07:47 +0100 | [diff] [blame] | 2780 | |
Jaehoon Chung | 176d1ed | 2010-09-27 09:42:20 +0100 | [diff] [blame] | 2781 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && |
| 2782 | mmc_card_is_removable(mmc)) |
Anton Vorontsov | 68d1fb7 | 2009-03-17 00:13:52 +0300 | [diff] [blame] | 2783 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
| 2784 | |
Al Cooper | 4188bba | 2012-03-16 15:54:17 -0400 | [diff] [blame] | 2785 | /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ |
| 2786 | if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | |
| 2787 | SDHCI_SUPPORT_DDR50)) |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2788 | mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; |
| 2789 | |
| 2790 | /* SDR104 supports also implies SDR50 support */ |
| 2791 | if (caps[1] & SDHCI_SUPPORT_SDR104) |
| 2792 | mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; |
| 2793 | else if (caps[1] & SDHCI_SUPPORT_SDR50) |
| 2794 | mmc->caps |= MMC_CAP_UHS_SDR50; |
| 2795 | |
| 2796 | if (caps[1] & SDHCI_SUPPORT_DDR50) |
| 2797 | mmc->caps |= MMC_CAP_UHS_DDR50; |
| 2798 | |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 2799 | /* Does the host need tuning for SDR50? */ |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2800 | if (caps[1] & SDHCI_USE_SDR50_TUNING) |
| 2801 | host->flags |= SDHCI_SDR50_NEEDS_TUNING; |
| 2802 | |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 2803 | /* Does the host need tuning for HS200? */ |
| 2804 | if (mmc->caps2 & MMC_CAP2_HS200) |
| 2805 | host->flags |= SDHCI_HS200_NEEDS_TUNING; |
| 2806 | |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 2807 | /* Driver Type(s) (A, C, D) supported by the host */ |
| 2808 | if (caps[1] & SDHCI_DRIVER_TYPE_A) |
| 2809 | mmc->caps |= MMC_CAP_DRIVER_TYPE_A; |
| 2810 | if (caps[1] & SDHCI_DRIVER_TYPE_C) |
| 2811 | mmc->caps |= MMC_CAP_DRIVER_TYPE_C; |
| 2812 | if (caps[1] & SDHCI_DRIVER_TYPE_D) |
| 2813 | mmc->caps |= MMC_CAP_DRIVER_TYPE_D; |
| 2814 | |
Girish K S | bec8726 | 2011-10-13 12:04:16 +0530 | [diff] [blame] | 2815 | /* |
| 2816 | * If Power Off Notify capability is enabled by the host, |
| 2817 | * set notify to short power off notify timeout value. |
| 2818 | */ |
| 2819 | if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY) |
| 2820 | mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT; |
| 2821 | else |
| 2822 | mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE; |
| 2823 | |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 2824 | /* Initial value for re-tuning timer count */ |
| 2825 | host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >> |
| 2826 | SDHCI_RETUNING_TIMER_COUNT_SHIFT; |
| 2827 | |
| 2828 | /* |
| 2829 | * In case Re-tuning Timer is not disabled, the actual value of |
| 2830 | * re-tuning timer will be 2 ^ (n - 1). |
| 2831 | */ |
| 2832 | if (host->tuning_count) |
| 2833 | host->tuning_count = 1 << (host->tuning_count - 1); |
| 2834 | |
| 2835 | /* Re-tuning mode supported by the Host Controller */ |
| 2836 | host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >> |
| 2837 | SDHCI_RETUNING_MODE_SHIFT; |
| 2838 | |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 2839 | ocr_avail = 0; |
Philip Rakity | bad37e1 | 2012-05-27 18:36:44 -0700 | [diff] [blame] | 2840 | |
| 2841 | host->vmmc = regulator_get(mmc_dev(mmc), "vmmc"); |
| 2842 | if (IS_ERR(host->vmmc)) { |
| 2843 | pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc)); |
| 2844 | host->vmmc = NULL; |
| 2845 | } |
| 2846 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2847 | /* |
| 2848 | * According to SD Host Controller spec v3.00, if the Host System |
| 2849 | * can afford more than 150mA, Host Driver should set XPC to 1. Also |
| 2850 | * the value is meaningful only if Voltage Support in the Capabilities |
| 2851 | * register is set. The actual current value is 4 times the register |
| 2852 | * value. |
| 2853 | */ |
| 2854 | max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); |
Philip Rakity | bad37e1 | 2012-05-27 18:36:44 -0700 | [diff] [blame] | 2855 | if (!max_current_caps && host->vmmc) { |
| 2856 | u32 curr = regulator_get_current_limit(host->vmmc); |
| 2857 | if (curr > 0) { |
| 2858 | |
| 2859 | /* convert to SDHCI_MAX_CURRENT format */ |
| 2860 | curr = curr/1000; /* convert to mA */ |
| 2861 | curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; |
| 2862 | |
| 2863 | curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); |
| 2864 | max_current_caps = |
| 2865 | (curr << SDHCI_MAX_CURRENT_330_SHIFT) | |
| 2866 | (curr << SDHCI_MAX_CURRENT_300_SHIFT) | |
| 2867 | (curr << SDHCI_MAX_CURRENT_180_SHIFT); |
| 2868 | } |
| 2869 | } |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2870 | |
| 2871 | if (caps[0] & SDHCI_CAN_VDD_330) { |
| 2872 | int max_current_330; |
| 2873 | |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 2874 | ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2875 | |
| 2876 | max_current_330 = ((max_current_caps & |
| 2877 | SDHCI_MAX_CURRENT_330_MASK) >> |
| 2878 | SDHCI_MAX_CURRENT_330_SHIFT) * |
| 2879 | SDHCI_MAX_CURRENT_MULTIPLIER; |
| 2880 | |
| 2881 | if (max_current_330 > 150) |
| 2882 | mmc->caps |= MMC_CAP_SET_XPC_330; |
| 2883 | } |
| 2884 | if (caps[0] & SDHCI_CAN_VDD_300) { |
| 2885 | int max_current_300; |
| 2886 | |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 2887 | ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2888 | |
| 2889 | max_current_300 = ((max_current_caps & |
| 2890 | SDHCI_MAX_CURRENT_300_MASK) >> |
| 2891 | SDHCI_MAX_CURRENT_300_SHIFT) * |
| 2892 | SDHCI_MAX_CURRENT_MULTIPLIER; |
| 2893 | |
| 2894 | if (max_current_300 > 150) |
| 2895 | mmc->caps |= MMC_CAP_SET_XPC_300; |
| 2896 | } |
| 2897 | if (caps[0] & SDHCI_CAN_VDD_180) { |
| 2898 | int max_current_180; |
| 2899 | |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 2900 | ocr_avail |= MMC_VDD_165_195; |
| 2901 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2902 | max_current_180 = ((max_current_caps & |
| 2903 | SDHCI_MAX_CURRENT_180_MASK) >> |
| 2904 | SDHCI_MAX_CURRENT_180_SHIFT) * |
| 2905 | SDHCI_MAX_CURRENT_MULTIPLIER; |
| 2906 | |
| 2907 | if (max_current_180 > 150) |
| 2908 | mmc->caps |= MMC_CAP_SET_XPC_180; |
Arindam Nath | 5371c92 | 2011-05-05 12:19:02 +0530 | [diff] [blame] | 2909 | |
| 2910 | /* Maximum current capabilities of the host at 1.8V */ |
| 2911 | if (max_current_180 >= 800) |
| 2912 | mmc->caps |= MMC_CAP_MAX_CURRENT_800; |
| 2913 | else if (max_current_180 >= 600) |
| 2914 | mmc->caps |= MMC_CAP_MAX_CURRENT_600; |
| 2915 | else if (max_current_180 >= 400) |
| 2916 | mmc->caps |= MMC_CAP_MAX_CURRENT_400; |
Philip Rakity | 0aa6770 | 2012-05-27 18:36:33 -0700 | [diff] [blame^] | 2917 | else if (max_current_180 >= 200) |
Arindam Nath | 5371c92 | 2011-05-05 12:19:02 +0530 | [diff] [blame] | 2918 | mmc->caps |= MMC_CAP_MAX_CURRENT_200; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2919 | } |
| 2920 | |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 2921 | mmc->ocr_avail = ocr_avail; |
| 2922 | mmc->ocr_avail_sdio = ocr_avail; |
| 2923 | if (host->ocr_avail_sdio) |
| 2924 | mmc->ocr_avail_sdio &= host->ocr_avail_sdio; |
| 2925 | mmc->ocr_avail_sd = ocr_avail; |
| 2926 | if (host->ocr_avail_sd) |
| 2927 | mmc->ocr_avail_sd &= host->ocr_avail_sd; |
| 2928 | else /* normal SD controllers don't support 1.8V */ |
| 2929 | mmc->ocr_avail_sd &= ~MMC_VDD_165_195; |
| 2930 | mmc->ocr_avail_mmc = ocr_avail; |
| 2931 | if (host->ocr_avail_mmc) |
| 2932 | mmc->ocr_avail_mmc &= host->ocr_avail_mmc; |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 2933 | |
| 2934 | if (mmc->ocr_avail == 0) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2935 | pr_err("%s: Hardware doesn't report any " |
Pierre Ossman | b69c905 | 2008-03-08 23:44:25 +0100 | [diff] [blame] | 2936 | "support voltages.\n", mmc_hostname(mmc)); |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2937 | return -ENODEV; |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 2938 | } |
| 2939 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2940 | spin_lock_init(&host->lock); |
| 2941 | |
| 2942 | /* |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 2943 | * Maximum number of segments. Depends on if the hardware |
| 2944 | * can do scatter/gather or not. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2945 | */ |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 2946 | if (host->flags & SDHCI_USE_ADMA) |
Martin K. Petersen | a36274e | 2010-09-10 01:33:59 -0400 | [diff] [blame] | 2947 | mmc->max_segs = 128; |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2948 | else if (host->flags & SDHCI_USE_SDMA) |
Martin K. Petersen | a36274e | 2010-09-10 01:33:59 -0400 | [diff] [blame] | 2949 | mmc->max_segs = 1; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 2950 | else /* PIO */ |
Martin K. Petersen | a36274e | 2010-09-10 01:33:59 -0400 | [diff] [blame] | 2951 | mmc->max_segs = 128; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2952 | |
| 2953 | /* |
Pierre Ossman | bab7696 | 2006-07-02 16:51:35 +0100 | [diff] [blame] | 2954 | * Maximum number of sectors in one transfer. Limited by DMA boundary |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 2955 | * size (512KiB). |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2956 | */ |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 2957 | mmc->max_req_size = 524288; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2958 | |
| 2959 | /* |
| 2960 | * Maximum segment size. Could be one segment with the maximum number |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 2961 | * of bytes. When doing hardware scatter/gather, each entry cannot |
| 2962 | * be larger than 64 KiB though. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2963 | */ |
Olof Johansson | 30652aa | 2011-01-01 18:37:32 -0600 | [diff] [blame] | 2964 | if (host->flags & SDHCI_USE_ADMA) { |
| 2965 | if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) |
| 2966 | mmc->max_seg_size = 65535; |
| 2967 | else |
| 2968 | mmc->max_seg_size = 65536; |
| 2969 | } else { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 2970 | mmc->max_seg_size = mmc->max_req_size; |
Olof Johansson | 30652aa | 2011-01-01 18:37:32 -0600 | [diff] [blame] | 2971 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2972 | |
| 2973 | /* |
Pierre Ossman | fe4a3c7 | 2006-11-21 17:54:23 +0100 | [diff] [blame] | 2974 | * Maximum block size. This varies from controller to controller and |
| 2975 | * is specified in the capabilities register. |
| 2976 | */ |
Anton Vorontsov | 0633f65 | 2009-03-17 00:14:03 +0300 | [diff] [blame] | 2977 | if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { |
| 2978 | mmc->max_blk_size = 2; |
| 2979 | } else { |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 2980 | mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >> |
Anton Vorontsov | 0633f65 | 2009-03-17 00:14:03 +0300 | [diff] [blame] | 2981 | SDHCI_MAX_BLOCK_SHIFT; |
| 2982 | if (mmc->max_blk_size >= 3) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2983 | pr_warning("%s: Invalid maximum block size, " |
Anton Vorontsov | 0633f65 | 2009-03-17 00:14:03 +0300 | [diff] [blame] | 2984 | "assuming 512 bytes\n", mmc_hostname(mmc)); |
| 2985 | mmc->max_blk_size = 0; |
| 2986 | } |
| 2987 | } |
| 2988 | |
| 2989 | mmc->max_blk_size = 512 << mmc->max_blk_size; |
Pierre Ossman | fe4a3c7 | 2006-11-21 17:54:23 +0100 | [diff] [blame] | 2990 | |
| 2991 | /* |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 2992 | * Maximum block count. |
| 2993 | */ |
Ben Dooks | 1388eef | 2009-06-14 12:40:53 +0100 | [diff] [blame] | 2994 | mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 2995 | |
| 2996 | /* |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2997 | * Init tasklets. |
| 2998 | */ |
| 2999 | tasklet_init(&host->card_tasklet, |
| 3000 | sdhci_tasklet_card, (unsigned long)host); |
| 3001 | tasklet_init(&host->finish_tasklet, |
| 3002 | sdhci_tasklet_finish, (unsigned long)host); |
| 3003 | |
Al Viro | e4cad1b | 2006-10-10 22:47:07 +0100 | [diff] [blame] | 3004 | setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3005 | |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 3006 | if (host->version >= SDHCI_SPEC_300) { |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 3007 | init_waitqueue_head(&host->buf_ready_int); |
| 3008 | |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 3009 | /* Initialize re-tuning timer */ |
| 3010 | init_timer(&host->tuning_timer); |
| 3011 | host->tuning_timer.data = (unsigned long)host; |
| 3012 | host->tuning_timer.function = sdhci_tuning_timer; |
| 3013 | } |
| 3014 | |
Thomas Gleixner | dace145 | 2006-07-01 19:29:38 -0700 | [diff] [blame] | 3015 | ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, |
Pierre Ossman | b69c905 | 2008-03-08 23:44:25 +0100 | [diff] [blame] | 3016 | mmc_hostname(mmc), host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3017 | if (ret) |
Pierre Ossman | 8ef1a14 | 2006-06-30 02:22:21 -0700 | [diff] [blame] | 3018 | goto untasklet; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3019 | |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 3020 | sdhci_init(host, 0); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3021 | |
| 3022 | #ifdef CONFIG_MMC_DEBUG |
| 3023 | sdhci_dumpregs(host); |
| 3024 | #endif |
| 3025 | |
Pierre Ossman | f913431 | 2008-12-21 17:01:48 +0100 | [diff] [blame] | 3026 | #ifdef SDHCI_USE_LEDS_CLASS |
Helmut Schaa | 5dbace0 | 2009-02-14 16:22:39 +0100 | [diff] [blame] | 3027 | snprintf(host->led_name, sizeof(host->led_name), |
| 3028 | "%s::", mmc_hostname(mmc)); |
| 3029 | host->led.name = host->led_name; |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 3030 | host->led.brightness = LED_OFF; |
| 3031 | host->led.default_trigger = mmc_hostname(mmc); |
| 3032 | host->led.brightness_set = sdhci_led_control; |
| 3033 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3034 | ret = led_classdev_register(mmc_dev(mmc), &host->led); |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 3035 | if (ret) |
| 3036 | goto reset; |
| 3037 | #endif |
| 3038 | |
Pierre Ossman | 5f25a66 | 2006-10-04 02:15:39 -0700 | [diff] [blame] | 3039 | mmiowb(); |
| 3040 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3041 | mmc_add_host(mmc); |
| 3042 | |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 3043 | pr_info("%s: SDHCI controller on %s [%s] using %s\n", |
Kay Sievers | d1b2686 | 2008-11-08 21:37:46 +0100 | [diff] [blame] | 3044 | mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 3045 | (host->flags & SDHCI_USE_ADMA) ? "ADMA" : |
| 3046 | (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3047 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 3048 | sdhci_enable_card_detection(host); |
| 3049 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3050 | return 0; |
| 3051 | |
Pierre Ossman | f913431 | 2008-12-21 17:01:48 +0100 | [diff] [blame] | 3052 | #ifdef SDHCI_USE_LEDS_CLASS |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 3053 | reset: |
| 3054 | sdhci_reset(host, SDHCI_RESET_ALL); |
| 3055 | free_irq(host->irq, host); |
| 3056 | #endif |
Pierre Ossman | 8ef1a14 | 2006-06-30 02:22:21 -0700 | [diff] [blame] | 3057 | untasklet: |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3058 | tasklet_kill(&host->card_tasklet); |
| 3059 | tasklet_kill(&host->finish_tasklet); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3060 | |
| 3061 | return ret; |
| 3062 | } |
| 3063 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3064 | EXPORT_SYMBOL_GPL(sdhci_add_host); |
| 3065 | |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 3066 | void sdhci_remove_host(struct sdhci_host *host, int dead) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3067 | { |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 3068 | unsigned long flags; |
| 3069 | |
| 3070 | if (dead) { |
| 3071 | spin_lock_irqsave(&host->lock, flags); |
| 3072 | |
| 3073 | host->flags |= SDHCI_DEVICE_DEAD; |
| 3074 | |
| 3075 | if (host->mrq) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 3076 | pr_err("%s: Controller removed during " |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 3077 | " transfer!\n", mmc_hostname(host->mmc)); |
| 3078 | |
| 3079 | host->mrq->cmd->error = -ENOMEDIUM; |
| 3080 | tasklet_schedule(&host->finish_tasklet); |
| 3081 | } |
| 3082 | |
| 3083 | spin_unlock_irqrestore(&host->lock, flags); |
| 3084 | } |
| 3085 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 3086 | sdhci_disable_card_detection(host); |
| 3087 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3088 | mmc_remove_host(host->mmc); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3089 | |
Pierre Ossman | f913431 | 2008-12-21 17:01:48 +0100 | [diff] [blame] | 3090 | #ifdef SDHCI_USE_LEDS_CLASS |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 3091 | led_classdev_unregister(&host->led); |
| 3092 | #endif |
| 3093 | |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 3094 | if (!dead) |
| 3095 | sdhci_reset(host, SDHCI_RESET_ALL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3096 | |
| 3097 | free_irq(host->irq, host); |
| 3098 | |
| 3099 | del_timer_sync(&host->timer); |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 3100 | if (host->version >= SDHCI_SPEC_300) |
| 3101 | del_timer_sync(&host->tuning_timer); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3102 | |
| 3103 | tasklet_kill(&host->card_tasklet); |
| 3104 | tasklet_kill(&host->finish_tasklet); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3105 | |
Adrian Hunter | ceb6143 | 2011-12-27 15:48:41 +0200 | [diff] [blame] | 3106 | if (host->vmmc) |
Marek Szyprowski | 9bea3c8 | 2010-08-10 18:01:59 -0700 | [diff] [blame] | 3107 | regulator_put(host->vmmc); |
Marek Szyprowski | 9bea3c8 | 2010-08-10 18:01:59 -0700 | [diff] [blame] | 3108 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3109 | kfree(host->adma_desc); |
| 3110 | kfree(host->align_buffer); |
| 3111 | |
| 3112 | host->adma_desc = NULL; |
| 3113 | host->align_buffer = NULL; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3114 | } |
| 3115 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3116 | EXPORT_SYMBOL_GPL(sdhci_remove_host); |
| 3117 | |
| 3118 | void sdhci_free_host(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3119 | { |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3120 | mmc_free_host(host->mmc); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3121 | } |
| 3122 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3123 | EXPORT_SYMBOL_GPL(sdhci_free_host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3124 | |
| 3125 | /*****************************************************************************\ |
| 3126 | * * |
| 3127 | * Driver init/exit * |
| 3128 | * * |
| 3129 | \*****************************************************************************/ |
| 3130 | |
| 3131 | static int __init sdhci_drv_init(void) |
| 3132 | { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 3133 | pr_info(DRIVER_NAME |
Pierre Ossman | 52fbf9c | 2007-02-09 08:23:41 +0100 | [diff] [blame] | 3134 | ": Secure Digital Host Controller Interface driver\n"); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 3135 | pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3136 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3137 | return 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3138 | } |
| 3139 | |
| 3140 | static void __exit sdhci_drv_exit(void) |
| 3141 | { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3142 | } |
| 3143 | |
| 3144 | module_init(sdhci_drv_init); |
| 3145 | module_exit(sdhci_drv_exit); |
| 3146 | |
Pierre Ossman | df673b2 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 3147 | module_param(debug_quirks, uint, 0444); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3148 | module_param(debug_quirks2, uint, 0444); |
Pierre Ossman | 6743527 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 3149 | |
Pierre Ossman | 32710e8 | 2009-04-08 20:14:54 +0200 | [diff] [blame] | 3150 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3151 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3152 | MODULE_LICENSE("GPL"); |
Pierre Ossman | 6743527 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 3153 | |
Pierre Ossman | df673b2 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 3154 | MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3155 | MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); |