Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/cpuidle34xx.c |
| 3 | * |
| 4 | * OMAP3 CPU IDLE Routines |
| 5 | * |
| 6 | * Copyright (C) 2008 Texas Instruments, Inc. |
| 7 | * Rajendra Nayak <rnayak@ti.com> |
| 8 | * |
| 9 | * Copyright (C) 2007 Texas Instruments, Inc. |
| 10 | * Karthik Dasu <karthik-dp@ti.com> |
| 11 | * |
| 12 | * Copyright (C) 2006 Nokia Corporation |
| 13 | * Tony Lindgren <tony@atomide.com> |
| 14 | * |
| 15 | * Copyright (C) 2005 Texas Instruments, Inc. |
| 16 | * Richard Woodruff <r-woodruff2@ti.com> |
| 17 | * |
| 18 | * Based on pm.c for omap2 |
| 19 | * |
| 20 | * This program is free software; you can redistribute it and/or modify |
| 21 | * it under the terms of the GNU General Public License version 2 as |
| 22 | * published by the Free Software Foundation. |
| 23 | */ |
| 24 | |
Tero Kristo | cf22854 | 2009-03-20 15:21:02 +0200 | [diff] [blame] | 25 | #include <linux/sched.h> |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 26 | #include <linux/cpuidle.h> |
Kevin Hilman | 5698eb4 | 2011-11-07 15:58:40 -0800 | [diff] [blame] | 27 | #include <linux/export.h> |
Santosh Shilimkar | ff819da | 2011-09-03 22:38:27 +0530 | [diff] [blame] | 28 | #include <linux/cpu_pm.h> |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 29 | |
Paul Walmsley | 72e06d0 | 2010-12-21 21:05:16 -0700 | [diff] [blame] | 30 | #include "powerdomain.h" |
Paul Walmsley | 1540f214 | 2010-12-21 21:05:15 -0700 | [diff] [blame] | 31 | #include "clockdomain.h" |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 32 | |
Kevin Hilman | c98e223 | 2008-10-28 17:30:07 -0700 | [diff] [blame] | 33 | #include "pm.h" |
Paul Walmsley | 4814ced | 2010-10-08 11:40:20 -0600 | [diff] [blame] | 34 | #include "control.h" |
Santosh Shilimkar | ba8bb18 | 2011-12-05 09:46:24 +0100 | [diff] [blame] | 35 | #include "common.h" |
Kevin Hilman | c98e223 | 2008-10-28 17:30:07 -0700 | [diff] [blame] | 36 | |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 37 | /* Mach specific information to be recorded in the C-state driver_data */ |
| 38 | struct omap3_idle_statedata { |
Paul Walmsley | fd6b42a | 2013-01-26 00:58:12 -0700 | [diff] [blame] | 39 | u8 mpu_state; |
| 40 | u8 core_state; |
| 41 | u8 per_min_state; |
Paul Walmsley | 1cd9647 | 2013-01-26 00:58:13 -0700 | [diff] [blame] | 42 | u8 flags; |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 43 | }; |
Daniel Lezcano | 0c2487f | 2012-04-24 16:05:33 +0200 | [diff] [blame] | 44 | |
Paul Walmsley | 9db316b | 2012-12-15 01:39:19 -0700 | [diff] [blame] | 45 | static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd; |
| 46 | |
Paul Walmsley | fd6b42a | 2013-01-26 00:58:12 -0700 | [diff] [blame] | 47 | /* |
Paul Walmsley | 1cd9647 | 2013-01-26 00:58:13 -0700 | [diff] [blame] | 48 | * Possible flag bits for struct omap3_idle_statedata.flags: |
| 49 | * |
| 50 | * OMAP_CPUIDLE_CX_NO_CLKDM_IDLE: don't allow the MPU clockdomain to go |
| 51 | * inactive. This in turn prevents the MPU DPLL from entering autoidle |
| 52 | * mode, so wakeup latency is greatly reduced, at the cost of additional |
| 53 | * energy consumption. This also prevents the CORE clockdomain from |
| 54 | * entering idle. |
| 55 | */ |
| 56 | #define OMAP_CPUIDLE_CX_NO_CLKDM_IDLE BIT(0) |
| 57 | |
| 58 | /* |
Paul Walmsley | fd6b42a | 2013-01-26 00:58:12 -0700 | [diff] [blame] | 59 | * Prevent PER OFF if CORE is not in RETention or OFF as this would |
| 60 | * disable PER wakeups completely. |
| 61 | */ |
Daniel Lezcano | 97abc49 | 2012-04-24 16:05:37 +0200 | [diff] [blame] | 62 | static struct omap3_idle_statedata omap3_idle_data[] = { |
Daniel Lezcano | 88c377dd | 2012-04-24 16:05:34 +0200 | [diff] [blame] | 63 | { |
| 64 | .mpu_state = PWRDM_POWER_ON, |
| 65 | .core_state = PWRDM_POWER_ON, |
Paul Walmsley | fd6b42a | 2013-01-26 00:58:12 -0700 | [diff] [blame] | 66 | /* In C1 do not allow PER state lower than CORE state */ |
| 67 | .per_min_state = PWRDM_POWER_ON, |
Paul Walmsley | 1cd9647 | 2013-01-26 00:58:13 -0700 | [diff] [blame] | 68 | .flags = OMAP_CPUIDLE_CX_NO_CLKDM_IDLE, |
Daniel Lezcano | 88c377dd | 2012-04-24 16:05:34 +0200 | [diff] [blame] | 69 | }, |
| 70 | { |
| 71 | .mpu_state = PWRDM_POWER_ON, |
| 72 | .core_state = PWRDM_POWER_ON, |
Paul Walmsley | fd6b42a | 2013-01-26 00:58:12 -0700 | [diff] [blame] | 73 | .per_min_state = PWRDM_POWER_RET, |
Daniel Lezcano | 88c377dd | 2012-04-24 16:05:34 +0200 | [diff] [blame] | 74 | }, |
| 75 | { |
| 76 | .mpu_state = PWRDM_POWER_RET, |
| 77 | .core_state = PWRDM_POWER_ON, |
Paul Walmsley | fd6b42a | 2013-01-26 00:58:12 -0700 | [diff] [blame] | 78 | .per_min_state = PWRDM_POWER_RET, |
Daniel Lezcano | 88c377dd | 2012-04-24 16:05:34 +0200 | [diff] [blame] | 79 | }, |
| 80 | { |
| 81 | .mpu_state = PWRDM_POWER_OFF, |
| 82 | .core_state = PWRDM_POWER_ON, |
Paul Walmsley | fd6b42a | 2013-01-26 00:58:12 -0700 | [diff] [blame] | 83 | .per_min_state = PWRDM_POWER_RET, |
Daniel Lezcano | 88c377dd | 2012-04-24 16:05:34 +0200 | [diff] [blame] | 84 | }, |
| 85 | { |
| 86 | .mpu_state = PWRDM_POWER_RET, |
| 87 | .core_state = PWRDM_POWER_RET, |
Paul Walmsley | fd6b42a | 2013-01-26 00:58:12 -0700 | [diff] [blame] | 88 | .per_min_state = PWRDM_POWER_OFF, |
Daniel Lezcano | 88c377dd | 2012-04-24 16:05:34 +0200 | [diff] [blame] | 89 | }, |
| 90 | { |
| 91 | .mpu_state = PWRDM_POWER_OFF, |
| 92 | .core_state = PWRDM_POWER_RET, |
Paul Walmsley | fd6b42a | 2013-01-26 00:58:12 -0700 | [diff] [blame] | 93 | .per_min_state = PWRDM_POWER_OFF, |
Daniel Lezcano | 88c377dd | 2012-04-24 16:05:34 +0200 | [diff] [blame] | 94 | }, |
| 95 | { |
| 96 | .mpu_state = PWRDM_POWER_OFF, |
| 97 | .core_state = PWRDM_POWER_OFF, |
Paul Walmsley | fd6b42a | 2013-01-26 00:58:12 -0700 | [diff] [blame] | 98 | .per_min_state = PWRDM_POWER_OFF, |
Daniel Lezcano | 88c377dd | 2012-04-24 16:05:34 +0200 | [diff] [blame] | 99 | }, |
| 100 | }; |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 101 | |
Paul Walmsley | 9db316b | 2012-12-15 01:39:19 -0700 | [diff] [blame] | 102 | /* Private functions */ |
Kevin Hilman | bb4de3d | 2009-12-15 16:37:18 -0800 | [diff] [blame] | 103 | |
Robert Lee | 6da45dc | 2012-03-20 15:22:46 -0500 | [diff] [blame] | 104 | static int __omap3_enter_idle(struct cpuidle_device *dev, |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame] | 105 | struct cpuidle_driver *drv, |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 106 | int index) |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 107 | { |
Daniel Lezcano | 6622ac5 | 2012-04-24 16:05:35 +0200 | [diff] [blame] | 108 | struct omap3_idle_statedata *cx = &omap3_idle_data[index]; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 109 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 110 | local_fiq_disable(); |
| 111 | |
Tero Kristo | cf22854 | 2009-03-20 15:21:02 +0200 | [diff] [blame] | 112 | if (omap_irq_pending() || need_resched()) |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 113 | goto return_sleep_time; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 114 | |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 115 | /* Deny idle for C1 */ |
Paul Walmsley | 1cd9647 | 2013-01-26 00:58:13 -0700 | [diff] [blame] | 116 | if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE) { |
Jean Pihet | 05011f7 | 2012-06-01 17:11:08 +0200 | [diff] [blame] | 117 | clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]); |
Paul Walmsley | 1cd9647 | 2013-01-26 00:58:13 -0700 | [diff] [blame] | 118 | } else { |
| 119 | pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state); |
| 120 | pwrdm_set_next_pwrst(core_pd, cx->core_state); |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 121 | } |
| 122 | |
Santosh Shilimkar | ff819da | 2011-09-03 22:38:27 +0530 | [diff] [blame] | 123 | /* |
| 124 | * Call idle CPU PM enter notifier chain so that |
| 125 | * VFP context is saved. |
| 126 | */ |
Paul Walmsley | 1cd9647 | 2013-01-26 00:58:13 -0700 | [diff] [blame] | 127 | if (cx->mpu_state == PWRDM_POWER_OFF) |
Santosh Shilimkar | ff819da | 2011-09-03 22:38:27 +0530 | [diff] [blame] | 128 | cpu_pm_enter(); |
| 129 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 130 | /* Execute ARM wfi */ |
| 131 | omap_sram_idle(); |
| 132 | |
Santosh Shilimkar | ff819da | 2011-09-03 22:38:27 +0530 | [diff] [blame] | 133 | /* |
| 134 | * Call idle CPU PM enter notifier chain to restore |
| 135 | * VFP context. |
| 136 | */ |
Paul Walmsley | 1cd9647 | 2013-01-26 00:58:13 -0700 | [diff] [blame] | 137 | if (cx->mpu_state == PWRDM_POWER_OFF && |
| 138 | pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF) |
Santosh Shilimkar | ff819da | 2011-09-03 22:38:27 +0530 | [diff] [blame] | 139 | cpu_pm_exit(); |
| 140 | |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 141 | /* Re-allow idle for C1 */ |
Paul Walmsley | 1cd9647 | 2013-01-26 00:58:13 -0700 | [diff] [blame] | 142 | if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE) |
Jean Pihet | 05011f7 | 2012-06-01 17:11:08 +0200 | [diff] [blame] | 143 | clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]); |
Peter 'p2' De Schrijver | 06d8f06 | 2009-03-13 18:19:16 +0200 | [diff] [blame] | 144 | |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 145 | return_sleep_time: |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 146 | local_fiq_enable(); |
| 147 | |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 148 | return index; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 149 | } |
| 150 | |
| 151 | /** |
Robert Lee | 6da45dc | 2012-03-20 15:22:46 -0500 | [diff] [blame] | 152 | * omap3_enter_idle - Programs OMAP3 to enter the specified state |
| 153 | * @dev: cpuidle device |
| 154 | * @drv: cpuidle driver |
| 155 | * @index: the index of state to be entered |
| 156 | * |
| 157 | * Called from the CPUidle framework to program the device to the |
| 158 | * specified target state selected by the governor. |
| 159 | */ |
| 160 | static inline int omap3_enter_idle(struct cpuidle_device *dev, |
| 161 | struct cpuidle_driver *drv, |
| 162 | int index) |
| 163 | { |
| 164 | return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle); |
| 165 | } |
| 166 | |
| 167 | /** |
Jean Pihet | 0490891 | 2011-05-09 12:02:16 +0200 | [diff] [blame] | 168 | * next_valid_state - Find next valid C-state |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 169 | * @dev: cpuidle device |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame] | 170 | * @drv: cpuidle driver |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 171 | * @index: Index of currently selected c-state |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 172 | * |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 173 | * If the state corresponding to index is valid, index is returned back |
| 174 | * to the caller. Else, this function searches for a lower c-state which is |
| 175 | * still valid (as defined in omap3_power_states[]) and returns its index. |
Jean Pihet | 0490891 | 2011-05-09 12:02:16 +0200 | [diff] [blame] | 176 | * |
| 177 | * A state is valid if the 'valid' field is enabled and |
| 178 | * if it satisfies the enable_off_mode condition. |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 179 | */ |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 180 | static int next_valid_state(struct cpuidle_device *dev, |
Daniel Lezcano | e92a458 | 2012-04-24 16:05:36 +0200 | [diff] [blame] | 181 | struct cpuidle_driver *drv, int index) |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 182 | { |
Daniel Lezcano | 6622ac5 | 2012-04-24 16:05:35 +0200 | [diff] [blame] | 183 | struct omap3_idle_statedata *cx = &omap3_idle_data[index]; |
Jean Pihet | 0490891 | 2011-05-09 12:02:16 +0200 | [diff] [blame] | 184 | u32 mpu_deepest_state = PWRDM_POWER_RET; |
| 185 | u32 core_deepest_state = PWRDM_POWER_RET; |
Daniel Lezcano | e92a458 | 2012-04-24 16:05:36 +0200 | [diff] [blame] | 186 | int idx; |
Jean Pihet | 063a5d0 | 2012-06-01 17:11:06 +0200 | [diff] [blame] | 187 | int next_index = 0; /* C1 is the default value */ |
Jean Pihet | 0490891 | 2011-05-09 12:02:16 +0200 | [diff] [blame] | 188 | |
| 189 | if (enable_off_mode) { |
| 190 | mpu_deepest_state = PWRDM_POWER_OFF; |
| 191 | /* |
| 192 | * Erratum i583: valable for ES rev < Es1.2 on 3630. |
| 193 | * CORE OFF mode is not supported in a stable form, restrict |
| 194 | * instead the CORE state to RET. |
| 195 | */ |
| 196 | if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) |
| 197 | core_deepest_state = PWRDM_POWER_OFF; |
| 198 | } |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 199 | |
| 200 | /* Check if current state is valid */ |
Daniel Lezcano | f79b5d8 | 2012-04-24 16:05:32 +0200 | [diff] [blame] | 201 | if ((cx->mpu_state >= mpu_deepest_state) && |
Daniel Lezcano | e92a458 | 2012-04-24 16:05:36 +0200 | [diff] [blame] | 202 | (cx->core_state >= core_deepest_state)) |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 203 | return index; |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 204 | |
Daniel Lezcano | e92a458 | 2012-04-24 16:05:36 +0200 | [diff] [blame] | 205 | /* |
| 206 | * Drop to next valid state. |
| 207 | * Start search from the next (lower) state. |
| 208 | */ |
| 209 | for (idx = index - 1; idx >= 0; idx--) { |
Paul Walmsley | 1cd9647 | 2013-01-26 00:58:13 -0700 | [diff] [blame] | 210 | cx = &omap3_idle_data[idx]; |
Daniel Lezcano | e92a458 | 2012-04-24 16:05:36 +0200 | [diff] [blame] | 211 | if ((cx->mpu_state >= mpu_deepest_state) && |
| 212 | (cx->core_state >= core_deepest_state)) { |
| 213 | next_index = idx; |
| 214 | break; |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 215 | } |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 216 | } |
| 217 | |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 218 | return next_index; |
Sanjeev Premi | 6af83b3 | 2010-01-28 23:16:43 +0530 | [diff] [blame] | 219 | } |
| 220 | |
| 221 | /** |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 222 | * omap3_enter_idle_bm - Checks for any bus activity |
| 223 | * @dev: cpuidle device |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame] | 224 | * @drv: cpuidle driver |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 225 | * @index: array index of target state to be programmed |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 226 | * |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 227 | * This function checks for any pending activity and then programs |
| 228 | * the device to the specified or a safer state. |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 229 | */ |
| 230 | static int omap3_enter_idle_bm(struct cpuidle_device *dev, |
Jean Pihet | 13d65c8 | 2012-06-01 17:11:07 +0200 | [diff] [blame] | 231 | struct cpuidle_driver *drv, |
Deepthi Dharwar | e978aa7 | 2011-10-28 16:20:09 +0530 | [diff] [blame] | 232 | int index) |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 233 | { |
Paul Walmsley | fd6b42a | 2013-01-26 00:58:12 -0700 | [diff] [blame] | 234 | int new_state_idx, ret; |
| 235 | u8 per_next_state, per_saved_state; |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 236 | struct omap3_idle_statedata *cx; |
Kevin Hilman | 0f724ed | 2008-10-28 17:32:11 -0700 | [diff] [blame] | 237 | |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 238 | /* |
Jean Pihet | 13d65c8 | 2012-06-01 17:11:07 +0200 | [diff] [blame] | 239 | * Use only C1 if CAM is active. |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 240 | * CAM does not have wakeup capability in OMAP3. |
| 241 | */ |
Jean Pihet | 13d65c8 | 2012-06-01 17:11:07 +0200 | [diff] [blame] | 242 | if (pwrdm_read_pwrst(cam_pd) == PWRDM_POWER_ON) |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame] | 243 | new_state_idx = drv->safe_state_index; |
Jean Pihet | 13d65c8 | 2012-06-01 17:11:07 +0200 | [diff] [blame] | 244 | else |
| 245 | new_state_idx = next_valid_state(dev, drv, index); |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 246 | |
| 247 | /* |
Jean Pihet | c6cd91d | 2011-05-09 12:02:15 +0200 | [diff] [blame] | 248 | * FIXME: we currently manage device-specific idle states |
| 249 | * for PER and CORE in combination with CPU-specific |
| 250 | * idle states. This is wrong, and device-specific |
| 251 | * idle management needs to be separated out into |
| 252 | * its own code. |
| 253 | */ |
| 254 | |
Jean Pihet | 13d65c8 | 2012-06-01 17:11:07 +0200 | [diff] [blame] | 255 | /* Program PER state */ |
| 256 | cx = &omap3_idle_data[new_state_idx]; |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 257 | |
Paul Walmsley | fd6b42a | 2013-01-26 00:58:12 -0700 | [diff] [blame] | 258 | per_next_state = pwrdm_read_next_pwrst(per_pd); |
| 259 | per_saved_state = per_next_state; |
| 260 | if (per_next_state < cx->per_min_state) { |
| 261 | per_next_state = cx->per_min_state; |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 262 | pwrdm_set_next_pwrst(per_pd, per_next_state); |
Paul Walmsley | fd6b42a | 2013-01-26 00:58:12 -0700 | [diff] [blame] | 263 | } |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 264 | |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame] | 265 | ret = omap3_enter_idle(dev, drv, new_state_idx); |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 266 | |
| 267 | /* Restore original PER state if it was modified */ |
| 268 | if (per_next_state != per_saved_state) |
| 269 | pwrdm_set_next_pwrst(per_pd, per_saved_state); |
| 270 | |
| 271 | return ret; |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 272 | } |
| 273 | |
Paul Walmsley | 9db316b | 2012-12-15 01:39:19 -0700 | [diff] [blame] | 274 | static DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev); |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 275 | |
Paul Walmsley | 9db316b | 2012-12-15 01:39:19 -0700 | [diff] [blame] | 276 | static struct cpuidle_driver omap3_idle_driver = { |
Daniel Lezcano | 0d97558 | 2013-03-29 11:31:35 +0100 | [diff] [blame^] | 277 | .name = "omap3_idle", |
| 278 | .owner = THIS_MODULE, |
| 279 | .en_core_tk_irqen = 1, |
Daniel Lezcano | 200dd52 | 2012-04-24 16:05:30 +0200 | [diff] [blame] | 280 | .states = { |
| 281 | { |
Jean Pihet | 13d65c8 | 2012-06-01 17:11:07 +0200 | [diff] [blame] | 282 | .enter = omap3_enter_idle_bm, |
Daniel Lezcano | 200dd52 | 2012-04-24 16:05:30 +0200 | [diff] [blame] | 283 | .exit_latency = 2 + 2, |
| 284 | .target_residency = 5, |
| 285 | .flags = CPUIDLE_FLAG_TIME_VALID, |
| 286 | .name = "C1", |
| 287 | .desc = "MPU ON + CORE ON", |
| 288 | }, |
| 289 | { |
| 290 | .enter = omap3_enter_idle_bm, |
| 291 | .exit_latency = 10 + 10, |
| 292 | .target_residency = 30, |
| 293 | .flags = CPUIDLE_FLAG_TIME_VALID, |
| 294 | .name = "C2", |
| 295 | .desc = "MPU ON + CORE ON", |
| 296 | }, |
| 297 | { |
| 298 | .enter = omap3_enter_idle_bm, |
| 299 | .exit_latency = 50 + 50, |
| 300 | .target_residency = 300, |
| 301 | .flags = CPUIDLE_FLAG_TIME_VALID, |
| 302 | .name = "C3", |
| 303 | .desc = "MPU RET + CORE ON", |
| 304 | }, |
| 305 | { |
| 306 | .enter = omap3_enter_idle_bm, |
| 307 | .exit_latency = 1500 + 1800, |
| 308 | .target_residency = 4000, |
| 309 | .flags = CPUIDLE_FLAG_TIME_VALID, |
| 310 | .name = "C4", |
| 311 | .desc = "MPU OFF + CORE ON", |
| 312 | }, |
| 313 | { |
| 314 | .enter = omap3_enter_idle_bm, |
| 315 | .exit_latency = 2500 + 7500, |
| 316 | .target_residency = 12000, |
| 317 | .flags = CPUIDLE_FLAG_TIME_VALID, |
| 318 | .name = "C5", |
| 319 | .desc = "MPU RET + CORE RET", |
| 320 | }, |
| 321 | { |
| 322 | .enter = omap3_enter_idle_bm, |
| 323 | .exit_latency = 3000 + 8500, |
| 324 | .target_residency = 15000, |
| 325 | .flags = CPUIDLE_FLAG_TIME_VALID, |
| 326 | .name = "C6", |
| 327 | .desc = "MPU OFF + CORE RET", |
| 328 | }, |
| 329 | { |
| 330 | .enter = omap3_enter_idle_bm, |
| 331 | .exit_latency = 10000 + 30000, |
| 332 | .target_residency = 30000, |
| 333 | .flags = CPUIDLE_FLAG_TIME_VALID, |
| 334 | .name = "C7", |
| 335 | .desc = "MPU OFF + CORE OFF", |
| 336 | }, |
| 337 | }, |
Daniel Lezcano | 88c377dd | 2012-04-24 16:05:34 +0200 | [diff] [blame] | 338 | .state_count = ARRAY_SIZE(omap3_idle_data), |
Daniel Lezcano | 200dd52 | 2012-04-24 16:05:30 +0200 | [diff] [blame] | 339 | .safe_state_index = 0, |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 340 | }; |
| 341 | |
Paul Walmsley | 9db316b | 2012-12-15 01:39:19 -0700 | [diff] [blame] | 342 | /* Public functions */ |
| 343 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 344 | /** |
| 345 | * omap3_idle_init - Init routine for OMAP3 idle |
| 346 | * |
Jean Pihet | badc303 | 2011-05-09 12:02:14 +0200 | [diff] [blame] | 347 | * Registers the OMAP3 specific cpuidle driver to the cpuidle |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 348 | * framework with the valid set of states. |
| 349 | */ |
Kalle Jokiniemi | 0343371 | 2008-09-26 11:04:20 +0300 | [diff] [blame] | 350 | int __init omap3_idle_init(void) |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 351 | { |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 352 | struct cpuidle_device *dev; |
| 353 | |
| 354 | mpu_pd = pwrdm_lookup("mpu_pwrdm"); |
Rajendra Nayak | 20b0166 | 2008-10-08 17:31:22 +0530 | [diff] [blame] | 355 | core_pd = pwrdm_lookup("core_pwrdm"); |
Kevin Hilman | e7410cf | 2010-09-08 16:37:42 -0700 | [diff] [blame] | 356 | per_pd = pwrdm_lookup("per_pwrdm"); |
| 357 | cam_pd = pwrdm_lookup("cam_pwrdm"); |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 358 | |
Daniel Lezcano | daa37ce | 2012-05-04 19:18:40 +0200 | [diff] [blame] | 359 | if (!mpu_pd || !core_pd || !per_pd || !cam_pd) |
| 360 | return -ENODEV; |
| 361 | |
Daniel Lezcano | 6622ac5 | 2012-04-24 16:05:35 +0200 | [diff] [blame] | 362 | cpuidle_register_driver(&omap3_idle_driver); |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame] | 363 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 364 | dev = &per_cpu(omap3_idle_dev, smp_processor_id()); |
Daniel Lezcano | 6622ac5 | 2012-04-24 16:05:35 +0200 | [diff] [blame] | 365 | dev->cpu = 0; |
Deepthi Dharwar | 46bcfad | 2011-10-28 16:20:42 +0530 | [diff] [blame] | 366 | |
Rajendra Nayak | 99e6a4d | 2008-10-08 17:30:58 +0530 | [diff] [blame] | 367 | if (cpuidle_register_device(dev)) { |
| 368 | printk(KERN_ERR "%s: CPUidle register device failed\n", |
| 369 | __func__); |
| 370 | return -EIO; |
| 371 | } |
| 372 | |
| 373 | return 0; |
| 374 | } |