blob: 13ec35231383646a1fe5de17efd9b4aca5970248 [file] [log] [blame]
Channagoud Kadabi459f0112017-03-20 12:42:15 -07001/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include "sdm845.dtsi"
14
15/ {
16 model = "Qualcomm Technologies, Inc. SDM845 V2";
17 qcom,msm-id = <321 0x20000>;
18};
David Collins36050182017-04-26 11:41:22 -070019
Subhash Jadavani0842b272017-07-19 17:05:13 -070020&sdhc_2 {
Subhash Jadavani3497a962017-07-31 13:57:47 -070021 /delete-property/ qcom,sdr104-wa;
Subhash Jadavani0842b272017-07-19 17:05:13 -070022};
23
David Collinsf5764762017-07-20 16:42:42 -070024/delete-node/ &apc0_cpr;
25/delete-node/ &apc1_cpr;
26
27&soc {
28 /* CPR controller regulators */
29 apc0_cpr: cprh-ctrl@17dc0000 {
30 compatible = "qcom,cprh-sdm845-v2-kbss-regulator";
31 reg = <0x17dc0000 0x4000>,
32 <0x00784000 0x1000>,
33 <0x17840000 0x1000>;
34 reg-names = "cpr_ctrl", "fuse_base", "saw";
35 clocks = <&clock_gcc GCC_CPUSS_RBCPR_CLK>;
36 clock-names = "core_clk";
37 qcom,cpr-ctrl-name = "apc0";
38 qcom,cpr-controller-id = <0>;
39
40 qcom,cpr-sensor-time = <1000>;
41 qcom,cpr-loop-time = <5000000>;
42 qcom,cpr-idle-cycles = <15>;
43 qcom,cpr-up-down-delay-time = <3000>;
44 qcom,cpr-step-quot-init-min = <11>;
45 qcom,cpr-step-quot-init-max = <12>;
46 qcom,cpr-count-mode = <0>; /* All at once */
47 qcom,cpr-count-repeat = <20>;
48 qcom,cpr-down-error-step-limit = <1>;
49 qcom,cpr-up-error-step-limit = <1>;
50 qcom,cpr-corner-switch-delay-time = <1042>;
51 qcom,cpr-voltage-settling-time = <1760>;
52 qcom,cpr-reset-step-quot-loop-en;
53
54 qcom,voltage-step = <4000>;
55 qcom,voltage-base = <352000>;
56 qcom,cpr-saw-use-unit-mV;
57
58 qcom,saw-avs-ctrl = <0x101C031>;
59 qcom,saw-avs-limit = <0x3B803B8>;
60
61 qcom,cpr-enable;
62 qcom,cpr-hw-closed-loop;
63
64 qcom,cpr-panic-reg-addr-list =
65 <0x17dc3a84 0x17dc3a88 0x17840c18>;
66 qcom,cpr-panic-reg-name-list =
67 "APSS_SILVER_CPRH_STATUS_0",
68 "APSS_SILVER_CPRH_STATUS_1",
69 "SILVER_SAW4_PMIC_STS";
70
71 qcom,cpr-aging-ref-voltage = <952000>;
72 vdd-supply = <&pm8998_s13>;
73
74 thread@0 {
75 qcom,cpr-thread-id = <0>;
76 qcom,cpr-consecutive-up = <0>;
77 qcom,cpr-consecutive-down = <0>;
78 qcom,cpr-up-threshold = <2>;
79 qcom,cpr-down-threshold = <2>;
80
81 apc0_pwrcl_vreg: regulator {
82 regulator-name = "apc0_pwrcl_corner";
83 regulator-min-microvolt = <1>;
84 regulator-max-microvolt = <18>;
85
86 qcom,cpr-fuse-corners = <4>;
87 qcom,cpr-fuse-combos = <16>;
88 qcom,cpr-speed-bins = <2>;
89 qcom,cpr-speed-bin-corners = <18 18>;
90 qcom,cpr-corners = <18>;
91
92 qcom,cpr-corner-fmax-map = <6 12 15 18>;
93
94 qcom,cpr-voltage-ceiling =
95 <828000 828000 828000 828000 828000
96 828000 828000 828000 828000 828000
97 828000 828000 828000 828000 828000
David Collinsb7d8a0a2017-08-10 17:54:03 -070098 884000 1000000 1000000>;
David Collinsf5764762017-07-20 16:42:42 -070099
100 qcom,cpr-voltage-floor =
101 <568000 568000 568000 568000 568000
102 568000 568000 568000 568000 568000
103 568000 568000 568000 568000 568000
104 568000 568000 568000>;
105
106 qcom,cpr-floor-to-ceiling-max-range =
107 <32000 32000 32000 32000 32000
108 32000 32000 32000 32000 32000
109 32000 32000 32000 32000 32000
110 32000 40000 40000>;
111
112 qcom,corner-frequencies =
113 <300000000 403200000 480000000
114 576000000 652800000 748800000
115 825600000 902400000 979200000
116 1056000000 1132800000 1228800000
117 1324800000 1420800000 1516800000
118 1612800000 1689600000 1766400000>;
119
120 qcom,cpr-ro-scaling-factor =
121 <2594 2795 2576 2761 2469 2673 2198
122 2553 3188 3255 3191 2962 3055 2984
123 2043 2947>,
124 <2594 2795 2576 2761 2469 2673 2198
125 2553 3188 3255 3191 2962 3055 2984
126 2043 2947>,
127 <2259 2389 2387 2531 2294 2464 2218
128 2476 2525 2855 2817 2836 2740 2490
129 1950 2632>,
130 <2259 2389 2387 2531 2294 2464 2218
131 2476 2525 2855 2817 2836 2740 2490
132 1950 2632>;
133
134 qcom,cpr-open-loop-voltage-fuse-adjustment =
135 <100000 100000 100000 100000>;
136
137 qcom,cpr-closed-loop-voltage-fuse-adjustment =
138 <100000 100000 100000 100000>;
139
140 qcom,allow-voltage-interpolation;
141 qcom,allow-quotient-interpolation;
142 qcom,cpr-scaled-open-loop-voltage-as-ceiling;
143
144 qcom,cpr-aging-max-voltage-adjustment = <15000>;
145 qcom,cpr-aging-ref-corner = <18>;
146 qcom,cpr-aging-ro-scaling-factor = <1620>;
147 qcom,allow-aging-voltage-adjustment =
148 /* Speed bin 0 */
149 <0 1 1 1 1 1 1 1>,
150 /* Speed bin 1 */
151 <0 1 1 1 1 1 1 1>;
152 qcom,allow-aging-open-loop-voltage-adjustment =
153 <1>;
154 };
155 };
156
157 thread@1 {
158 qcom,cpr-thread-id = <1>;
159 qcom,cpr-consecutive-up = <0>;
160 qcom,cpr-consecutive-down = <0>;
161 qcom,cpr-up-threshold = <2>;
162 qcom,cpr-down-threshold = <2>;
163
164 apc0_l3_vreg: regulator {
165 regulator-name = "apc0_l3_corner";
166 regulator-min-microvolt = <1>;
David Collinsb7d8a0a2017-08-10 17:54:03 -0700167 regulator-max-microvolt = <15>;
David Collinsf5764762017-07-20 16:42:42 -0700168
169 qcom,cpr-fuse-corners = <4>;
170 qcom,cpr-fuse-combos = <16>;
171 qcom,cpr-speed-bins = <2>;
David Collinsb7d8a0a2017-08-10 17:54:03 -0700172 qcom,cpr-speed-bin-corners = <14 15>;
173 qcom,cpr-corners =
174 /* Speed bin 0 */
175 <14 14 14 14 14 14 14 14>,
176 /* Speed bin 1 */
177 <15 15 15 15 15 15 15 15>;
David Collinsf5764762017-07-20 16:42:42 -0700178
David Collinsb7d8a0a2017-08-10 17:54:03 -0700179 qcom,cpr-corner-fmax-map =
180 /* Speed bin 0 */
181 <4 8 11 14>,
182 /* Speed bin 1 */
183 <4 8 11 15>;
David Collinsf5764762017-07-20 16:42:42 -0700184
185 qcom,cpr-voltage-ceiling =
David Collinsb7d8a0a2017-08-10 17:54:03 -0700186 /* Speed bin 0 */
David Collinsf5764762017-07-20 16:42:42 -0700187 <828000 828000 828000 828000 828000
188 828000 828000 828000 828000 828000
David Collinsb7d8a0a2017-08-10 17:54:03 -0700189 828000 884000 884000 1000000>,
190 /* Speed bin 1 */
191 <828000 828000 828000 828000 828000
192 828000 828000 828000 828000 828000
193 828000 884000 884000 1000000
194 1000000>;
David Collinsf5764762017-07-20 16:42:42 -0700195
196 qcom,cpr-voltage-floor =
David Collinsb7d8a0a2017-08-10 17:54:03 -0700197 /* Speed bin 0 */
David Collinsf5764762017-07-20 16:42:42 -0700198 <568000 568000 568000 568000 568000
199 568000 568000 568000 568000 568000
David Collinsb7d8a0a2017-08-10 17:54:03 -0700200 568000 568000 568000 568000>,
201 /* Speed bin 1 */
202 <568000 568000 568000 568000 568000
203 568000 568000 568000 568000 568000
204 568000 568000 568000 568000
205 568000>;
David Collinsf5764762017-07-20 16:42:42 -0700206
207 qcom,cpr-floor-to-ceiling-max-range =
David Collinsb7d8a0a2017-08-10 17:54:03 -0700208 /* Speed bin 0 */
David Collinsf5764762017-07-20 16:42:42 -0700209 <32000 32000 32000 32000 32000
210 32000 32000 32000 32000 32000
David Collinsb7d8a0a2017-08-10 17:54:03 -0700211 32000 32000 32000 40000>,
212 /* Speed bin 1 */
213 <32000 32000 32000 32000 32000
214 32000 32000 32000 32000 32000
215 32000 32000 32000 40000 40000>;
David Collinsf5764762017-07-20 16:42:42 -0700216
217 qcom,corner-frequencies =
David Collinsb7d8a0a2017-08-10 17:54:03 -0700218 /* Speed bin 0 */
David Collinsf5764762017-07-20 16:42:42 -0700219 <300000000 403200000 480000000
220 576000000 652800000 748800000
221 844800000 940800000 1036800000
222 1132800000 1209600000 1305600000
David Collinsb7d8a0a2017-08-10 17:54:03 -0700223 1401600000 1478400000>,
224 /* Speed bin 1 */
225 <300000000 403200000 480000000
226 576000000 652800000 748800000
227 844800000 940800000 1036800000
228 1132800000 1209600000 1305600000
229 1401600000 1497600000 1593600000>;
David Collinsf5764762017-07-20 16:42:42 -0700230
231 qcom,cpr-ro-scaling-factor =
232 <2857 3056 2828 2952 2699 2796 2447
233 2631 2630 2579 2244 3343 3287 3137
234 3164 2656>,
235 <2857 3056 2828 2952 2699 2796 2447
236 2631 2630 2579 2244 3343 3287 3137
237 3164 2656>,
238 <2439 2577 2552 2667 2461 2577 2394
239 2536 2132 2307 2191 2903 2838 2912
240 2501 2095>,
241 <2439 2577 2552 2667 2461 2577 2394
242 2536 2132 2307 2191 2903 2838 2912
243 2501 2095>;
244
245 qcom,cpr-open-loop-voltage-fuse-adjustment =
246 <100000 100000 100000 100000>;
247
248 qcom,cpr-closed-loop-voltage-fuse-adjustment =
249 <100000 100000 100000 100000>;
250
251 qcom,allow-voltage-interpolation;
252 qcom,allow-quotient-interpolation;
253 qcom,cpr-scaled-open-loop-voltage-as-ceiling;
254
255 qcom,cpr-aging-max-voltage-adjustment = <15000>;
256 qcom,cpr-aging-ref-corner = <14>;
257 qcom,cpr-aging-ro-scaling-factor = <1620>;
258 qcom,allow-aging-voltage-adjustment =
259 /* Speed bin 0 */
260 <0 1 1 1 1 1 1 1>,
261 /* Speed bin 1 */
262 <0 1 1 1 1 1 1 1>;
263 qcom,allow-aging-open-loop-voltage-adjustment =
264 <1>;
265 };
266 };
267 };
268
269 apc1_cpr: cprh-ctrl@17db0000 {
270 compatible = "qcom,cprh-sdm845-v2-kbss-regulator";
271 reg = <0x17db0000 0x4000>,
272 <0x00784000 0x1000>,
273 <0x17830000 0x1000>;
274 reg-names = "cpr_ctrl", "fuse_base", "saw";
275 clocks = <&clock_gcc GCC_CPUSS_RBCPR_CLK>;
276 clock-names = "core_clk";
277 qcom,cpr-ctrl-name = "apc1";
278 qcom,cpr-controller-id = <1>;
279
280 qcom,cpr-sensor-time = <1000>;
281 qcom,cpr-loop-time = <5000000>;
282 qcom,cpr-idle-cycles = <15>;
283 qcom,cpr-up-down-delay-time = <3000>;
284 qcom,cpr-step-quot-init-min = <9>;
285 qcom,cpr-step-quot-init-max = <14>;
286 qcom,cpr-count-mode = <0>; /* All at once */
287 qcom,cpr-count-repeat = <20>;
288 qcom,cpr-down-error-step-limit = <1>;
289 qcom,cpr-up-error-step-limit = <1>;
290 qcom,cpr-corner-switch-delay-time = <1042>;
291 qcom,cpr-voltage-settling-time = <1760>;
292 qcom,cpr-reset-step-quot-loop-en;
293
294 qcom,apm-threshold-voltage = <800000>;
295 qcom,apm-crossover-voltage = <880000>;
296 qcom,mem-acc-threshold-voltage = <852000>;
297 qcom,mem-acc-crossover-voltage = <852000>;
298
299 qcom,voltage-step = <4000>;
300 qcom,voltage-base = <352000>;
301 qcom,cpr-saw-use-unit-mV;
302
303 qcom,saw-avs-ctrl = <0x101C031>;
304 qcom,saw-avs-limit = <0x4700470>;
305
306 qcom,cpr-enable;
307 qcom,cpr-hw-closed-loop;
308
309 qcom,cpr-panic-reg-addr-list =
310 <0x17db3a84 0x17830c18>;
311 qcom,cpr-panic-reg-name-list =
312 "APSS_GOLD_CPRH_STATUS_0", "GOLD_SAW4_PMIC_STS";
313
314 qcom,cpr-aging-ref-voltage = <1136000>;
315 vdd-supply = <&pm8998_s12>;
316
317 thread@0 {
318 qcom,cpr-thread-id = <0>;
319 qcom,cpr-consecutive-up = <0>;
320 qcom,cpr-consecutive-down = <0>;
321 qcom,cpr-up-threshold = <2>;
322 qcom,cpr-down-threshold = <2>;
323
324 apc1_perfcl_vreg: regulator {
325 regulator-name = "apc1_perfcl_corner";
326 regulator-min-microvolt = <1>;
327 regulator-max-microvolt = <33>;
328
329 qcom,cpr-fuse-corners = <5>;
330 qcom,cpr-fuse-combos = <16>;
331 qcom,cpr-speed-bins = <2>;
332 qcom,cpr-speed-bin-corners = <28 31>;
333 qcom,cpr-corners =
334 /* Speed bin 0 */
335 <28 28 28 28 28 28 28 28>,
336 /* Speed bin 1 */
337 <31 31 31 31 31 31 31 31>;
338
339 qcom,cpr-corner-fmax-map =
340 /* Speed bin 0 */
341 <7 14 22 27 28>,
342 /* Speed bin 1 */
343 <7 14 22 27 31>;
344
345 qcom,cpr-voltage-ceiling =
346 /* Speed bin 0 */
347 <828000 828000 828000 828000 828000
348 828000 828000 828000 828000 828000
349 828000 828000 828000 828000 828000
350 828000 828000 828000 884000 884000
351 884000 884000 1104000 1104000 1104000
352 1104000 1136000 1136000>,
353 /* Speed bin 1 */
354 <828000 828000 828000 828000 828000
355 828000 828000 828000 828000 828000
356 828000 828000 828000 828000 828000
357 828000 828000 828000 884000 884000
358 884000 884000 1104000 1104000 1104000
359 1104000 1136000 1136000 1136000 1136000
360 1136000>;
361
362 qcom,cpr-voltage-floor =
363 /* Speed bin 0 */
364 <568000 568000 568000 568000 568000
365 568000 568000 568000 568000 568000
366 568000 568000 568000 568000 568000
367 568000 568000 568000 568000 568000
368 568000 568000 568000 568000 568000
369 568000 568000 568000>,
370 /* Speed bin 1 */
371 <568000 568000 568000 568000 568000
372 568000 568000 568000 568000 568000
373 568000 568000 568000 568000 568000
374 568000 568000 568000 568000 568000
375 568000 568000 568000 568000 568000
376 568000 568000 568000 568000 568000
377 568000>;
378
379 qcom,cpr-floor-to-ceiling-max-range =
380 /* Speed bin 0 */
381 <32000 32000 32000 32000 32000
382 32000 32000 32000 32000 32000
383 32000 32000 32000 32000 32000
384 32000 32000 32000 32000 32000
385 32000 32000 32000 32000 32000
386 32000 32000 32000>,
387 /* Speed bin 1 */
388 <32000 32000 32000 32000 32000
389 32000 32000 32000 32000 32000
390 32000 32000 32000 32000 32000
391 32000 32000 32000 32000 32000
392 32000 32000 32000 32000 32000
393 32000 32000 40000 40000 40000
394 40000>;
395
396 qcom,corner-frequencies =
397 /* Speed bin 0 */
398 <300000000 403200000 480000000
399 576000000 652800000 748800000
400 825600000 902400000 979200000
401 1056000000 1132800000 1209600000
402 1286400000 1363200000 1459200000
403 1536000000 1612800000 1689600000
404 1766400000 1843200000 1920000000
405 1996800000 2092800000 2169600000
406 2246400000 2323200000 2400000000
407 2400000000>,
408 /* Speed bin 1 */
409 <300000000 403200000 480000000
410 576000000 652800000 748800000
411 825600000 902400000 979200000
412 1056000000 1132800000 1209600000
413 1286400000 1363200000 1459200000
414 1536000000 1612800000 1689600000
415 1766400000 1843200000 1920000000
416 1996800000 2092800000 2169600000
417 2246400000 2323200000 2400000000
418 2476800000 2553600000 2630400000
419 2707200000>;
420
421 qcom,cpr-ro-scaling-factor =
422 <2857 3056 2828 2952 2699 2796 2447
423 2631 2630 2579 2244 3343 3287 3137
424 3164 2656>,
425 <2857 3056 2828 2952 2699 2796 2447
426 2631 2630 2579 2244 3343 3287 3137
427 3164 2656>,
428 <2086 2208 2273 2408 2203 2327 2213
429 2340 1755 2039 2049 2474 2437 2618
430 2003 1675>,
431 <2086 2208 2273 2408 2203 2327 2213
432 2340 1755 2039 2049 2474 2437 2618
433 2003 1675>,
434 <2086 2208 2273 2408 2203 2327 2213
435 2340 1755 2039 2049 2474 2437 2618
436 2003 1675>;
437
438 qcom,cpr-open-loop-voltage-fuse-adjustment =
439 <100000 100000 100000 100000 100000>;
440
441 qcom,cpr-closed-loop-voltage-fuse-adjustment =
442 <100000 100000 100000 100000 100000>;
443
444 qcom,allow-voltage-interpolation;
445 qcom,allow-quotient-interpolation;
446 qcom,cpr-scaled-open-loop-voltage-as-ceiling;
447
448 qcom,cpr-aging-max-voltage-adjustment = <15000>;
449 qcom,cpr-aging-ref-corner = <27 31>;
450 qcom,cpr-aging-ro-scaling-factor = <1700>;
451 qcom,allow-aging-voltage-adjustment =
452 /* Speed bin 0 */
453 <0 1 1 1 1 1 1 1>,
454 /* Speed bin 1 */
455 <0 1 1 1 1 1 1 1>;
456 qcom,allow-aging-open-loop-voltage-adjustment =
457 <1>;
458 };
459 };
460 };
461};
462
463&clock_cpucc {
Deepak Katragaddaa442baa2017-07-11 12:27:06 -0700464 compatible = "qcom,clk-cpu-osm-v2";
465
David Collinsf5764762017-07-20 16:42:42 -0700466 vdd-l3-supply = <&apc0_l3_vreg>;
467 vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;
Deepak Katragaddaa442baa2017-07-11 12:27:06 -0700468 vdd-perfcl-supply = <&apc1_perfcl_vreg>;
469
470 qcom,l3-speedbin0-v0 =
471 < 300000000 0x000c000f 0x00002020 0x1 1 >,
472 < 403200000 0x500c0115 0x00002020 0x1 2 >,
473 < 480000000 0x50140219 0x00002020 0x1 3 >,
474 < 576000000 0x5014031e 0x00002020 0x1 4 >,
475 < 652800000 0x401c0422 0x00002020 0x1 5 >,
476 < 748800000 0x401c0527 0x00002020 0x1 6 >,
477 < 844800000 0x4024062c 0x00002323 0x2 7 >,
478 < 940800000 0x40240731 0x00002727 0x2 8 >,
479 < 1036800000 0x40240836 0x00002b2b 0x2 9 >,
480 < 1132800000 0x402c093b 0x00002f2f 0x2 10 >,
481 < 1209600000 0x402c0a3f 0x00003232 0x2 11 >,
482 < 1305600000 0x40340b44 0x00003636 0x2 12 >,
483 < 1401600000 0x40340c49 0x00003a3a 0x2 13 >,
484 < 1478400000 0x403c0d4d 0x00003e3e 0x2 14 >;
485
Deepak Katragadda288d2b52017-08-11 10:13:59 -0700486 qcom,l3-speedbin1-v0 =
487 < 300000000 0x000c000f 0x00002020 0x1 1 >,
488 < 403200000 0x500c0115 0x00002020 0x1 2 >,
489 < 480000000 0x50140219 0x00002020 0x1 3 >,
490 < 576000000 0x5014031e 0x00002020 0x1 4 >,
491 < 652800000 0x401c0422 0x00002020 0x1 5 >,
492 < 748800000 0x401c0527 0x00002020 0x1 6 >,
493 < 844800000 0x4024062c 0x00002323 0x2 7 >,
494 < 940800000 0x40240731 0x00002727 0x2 8 >,
495 < 1036800000 0x40240836 0x00002b2b 0x2 9 >,
496 < 1132800000 0x402c093b 0x00002f2f 0x2 10 >,
497 < 1209600000 0x402c0a3f 0x00003232 0x2 11 >,
498 < 1305600000 0x40340b44 0x00003636 0x2 12 >,
499 < 1401600000 0x40340c49 0x00003a3a 0x2 13 >,
500 < 1497600000 0x403c0d4e 0x00003e3e 0x2 14 >,
501 < 1593600000 0x403c0e53 0x00004242 0x2 15 >;
502
Deepak Katragaddaa442baa2017-07-11 12:27:06 -0700503 qcom,pwrcl-speedbin0-v0 =
504 < 300000000 0x000c000f 0x00002020 0x1 1 >,
505 < 403200000 0x500c0115 0x00002020 0x1 2 >,
506 < 480000000 0x50140219 0x00002020 0x1 3 >,
507 < 576000000 0x5014031e 0x00002020 0x1 4 >,
508 < 652800000 0x401c0422 0x00002020 0x1 5 >,
509 < 748800000 0x401c0527 0x00002020 0x1 6 >,
510 < 825600000 0x401c062b 0x00002222 0x1 7 >,
511 < 902400000 0x4024072f 0x00002626 0x1 8 >,
512 < 979200000 0x40240833 0x00002929 0x1 9 >,
513 < 1056000000 0x402c0937 0x00002c2c 0x2 10 >,
514 < 1132800000 0x402c0a3b 0x00002f2f 0x2 11 >,
515 < 1228800000 0x402c0b40 0x00003333 0x2 12 >,
516 < 1324800000 0x40340c45 0x00003737 0x2 13 >,
517 < 1420800000 0x40340d4a 0x00003b3b 0x2 14 >,
518 < 1516800000 0x403c0e4f 0x00003f3f 0x2 15 >,
519 < 1612800000 0x403c0f54 0x00004343 0x2 16 >,
520 < 1689600000 0x40441058 0x00004646 0x2 17 >,
521 < 1766400000 0x4044115c 0x00004a4a 0x2 18 >;
522
523 qcom,perfcl-speedbin0-v0 =
524 < 300000000 0x000c000f 0x00002020 0x1 1 >,
525 < 403200000 0x500c0115 0x00002020 0x1 2 >,
526 < 480000000 0x50140219 0x00002020 0x1 3 >,
527 < 576000000 0x5014031e 0x00002020 0x1 4 >,
528 < 652800000 0x401c0422 0x00002020 0x1 5 >,
529 < 748800000 0x401c0527 0x00002020 0x1 6 >,
530 < 825600000 0x401c062b 0x00002222 0x1 7 >,
531 < 902400000 0x4024072f 0x00002626 0x1 8 >,
532 < 979200000 0x40240833 0x00002929 0x1 9 >,
533 < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
534 < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
535 < 1209600000 0x402c0b3f 0x00003232 0x2 12 >,
536 < 1286400000 0x40340c43 0x00003636 0x2 13 >,
537 < 1363200000 0x40340d47 0x00003939 0x2 14 >,
538 < 1459200000 0x403c0e4c 0x00003d3d 0x2 15 >,
539 < 1536000000 0x403c0f50 0x00004040 0x2 16 >,
540 < 1612800000 0x403c1054 0x00004343 0x2 17 >,
541 < 1689600000 0x40441158 0x00004646 0x2 18 >,
542 < 1766400000 0x4044125c 0x00004a4a 0x2 19 >,
543 < 1843200000 0x40441360 0x00004d4d 0x2 20 >,
544 < 1920000000 0x404c1464 0x00005050 0x2 21 >,
545 < 1996800000 0x404c1568 0x00005353 0x2 22 >,
546 < 2092800000 0x4054166d 0x00005757 0x2 23 >,
547 < 2169600000 0x40541771 0x00005a5a 0x2 24 >,
548 < 2246400000 0x40541875 0x00005e5e 0x2 25 >,
549 < 2323200000 0x40541979 0x00006161 0x2 26 >,
550 < 2400000000 0x40541a7d 0x00006464 0x2 27 >;
551
552 qcom,perfcl-speedbin1-v0 =
553 < 300000000 0x000c000f 0x00002020 0x1 1 >,
554 < 403200000 0x500c0115 0x00002020 0x1 2 >,
555 < 480000000 0x50140219 0x00002020 0x1 3 >,
556 < 576000000 0x5014031e 0x00002020 0x1 4 >,
557 < 652800000 0x401c0422 0x00002020 0x1 5 >,
558 < 748800000 0x401c0527 0x00002020 0x1 6 >,
559 < 825600000 0x401c062b 0x00002222 0x1 7 >,
560 < 902400000 0x4024072f 0x00002626 0x1 8 >,
561 < 979200000 0x40240833 0x00002929 0x1 9 >,
562 < 1056000000 0x402c0937 0x00002c2c 0x1 10 >,
563 < 1132800000 0x402c0a3b 0x00002f2f 0x1 11 >,
564 < 1209600000 0x402c0b3f 0x00003232 0x2 12 >,
565 < 1286400000 0x40340c43 0x00003636 0x2 13 >,
566 < 1363200000 0x40340d47 0x00003939 0x2 14 >,
567 < 1459200000 0x403c0e4c 0x00003d3d 0x2 15 >,
568 < 1536000000 0x403c0f50 0x00004040 0x2 16 >,
569 < 1612800000 0x403c1054 0x00004343 0x2 17 >,
570 < 1689600000 0x40441158 0x00004646 0x2 18 >,
571 < 1766400000 0x4044125c 0x00004a4a 0x2 19 >,
572 < 1843200000 0x40441360 0x00004d4d 0x2 20 >,
573 < 1920000000 0x404c1464 0x00005050 0x2 21 >,
574 < 1996800000 0x404c1568 0x00005353 0x2 22 >,
575 < 2092800000 0x4054166d 0x00005757 0x2 23 >,
576 < 2169600000 0x40541771 0x00005a5a 0x2 24 >,
577 < 2246400000 0x40541875 0x00005e5e 0x2 25 >,
578 < 2323200000 0x40541979 0x00006161 0x2 26 >,
579 < 2400000000 0x40541a7d 0x00006464 0x2 27 >,
580 < 2476800000 0x40541b81 0x00006767 0x2 28 >,
581 < 2553600000 0x40541c85 0x00006a6a 0x2 29 >,
582 < 2630400000 0x40541d89 0x00006e6e 0x2 30 >,
583 < 2707200000 0x40541e8d 0x00007171 0x2 31 >;
Deepak Katragadda30d72dd2017-08-01 13:56:00 -0700584
585 qcom,l3-memacc-level-vc-bin0 = <8 13>;
Deepak Katragadda288d2b52017-08-11 10:13:59 -0700586 qcom,l3-memacc-level-vc-bin1 = <8 13>;
Deepak Katragadda30d72dd2017-08-01 13:56:00 -0700587
588 qcom,pwrcl-memacc-level-vc-bin0 = <12 16>;
589
590 qcom,perfcl-memacc-level-vc-bin0 = <14 22>;
591 qcom,perfcl-memacc-level-vc-bin1 = <14 22>;
David Collinsf5764762017-07-20 16:42:42 -0700592};
593
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700594&clock_gcc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700595 compatible = "qcom,gcc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700596};
597
598&clock_camcc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700599 compatible = "qcom,cam_cc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700600};
601
602&clock_dispcc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700603 compatible = "qcom,dispcc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700604};
605
Vicky Wallace1762ab32017-07-12 19:00:04 -0700606&clock_gpucc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700607 compatible = "qcom,gpucc-sdm845-v2", "syscon";
Vicky Wallace1762ab32017-07-12 19:00:04 -0700608};
609
610&clock_gfx {
611 compatible = "qcom,gfxcc-sdm845-v2";
612};
613
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700614&clock_videocc {
Deepak Katragadda3f120bb2017-08-09 14:49:49 -0700615 compatible = "qcom,video_cc-sdm845-v2", "syscon";
Deepak Katragaddada47ee92017-06-07 14:15:09 -0700616};
Praneeth Paladugu55381212017-07-05 15:02:44 -0700617
Deepak Katragadda0836d182017-07-27 14:23:02 -0700618&clock_aop {
619 compatible = "qcom,aop-qmp-clk-v2";
620};
621
Praneeth Paladugu55381212017-07-05 15:02:44 -0700622&msm_vidc {
623 qcom,allowed-clock-rates = <100000000 200000000 330000000
624 404000000 444000000 533000000>;
625};
Reut Zysman861fd6c2017-07-30 15:39:13 +0300626
David Collins113cc2772017-06-27 17:26:54 -0700627&refgen {
628 status = "ok";
629};
630
Reut Zysman861fd6c2017-07-30 15:39:13 +0300631&spss_utils {
632 qcom,spss-dev-firmware-name = "spss2d"; /* 8 chars max */
633 qcom,spss-test-firmware-name = "spss2t"; /* 8 chars max */
634 qcom,spss-prod-firmware-name = "spss2p"; /* 8 chars max */
635};
Narendra Muppalla4efd3442017-07-24 17:36:15 -0700636
637&mdss_mdp {
638 clock-max-rate = <0 0 0 0 430000000 19200000 0>;
639};