blob: 3d9438ce59aba9fa87a1e85b5c54e5e7b2fceb9a [file] [log] [blame]
dea31012005-04-17 16:05:31 -05001/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
James.Smart@Emulex.Comc44ce172005-06-25 10:34:39 -04003 * Fibre Channel Host Bus Adapters. *
James Smart92c13f22013-05-31 17:05:45 -04004 * Copyright (C) 2004-2013 Emulex. All rights reserved. *
James.Smart@Emulex.Comc44ce172005-06-25 10:34:39 -04005 * EMULEX and SLI are trademarks of Emulex. *
dea31012005-04-17 16:05:31 -05006 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
James.Smart@Emulex.Comc44ce172005-06-25 10:34:39 -04009 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
dea31012005-04-17 16:05:31 -050019 *******************************************************************/
20
dea31012005-04-17 16:05:31 -050021#define FDMI_DID 0xfffffaU
22#define NameServer_DID 0xfffffcU
23#define SCR_DID 0xfffffdU
24#define Fabric_DID 0xfffffeU
25#define Bcast_DID 0xffffffU
26#define Mask_DID 0xffffffU
27#define CT_DID_MASK 0xffff00U
28#define Fabric_DID_MASK 0xfff000U
29#define WELL_KNOWN_DID_MASK 0xfffff0U
30
31#define PT2PT_LocalID 1
32#define PT2PT_RemoteID 2
33
34#define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
35#define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
36#define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */
37#define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
38
39#define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
40 0 */
41
42#define FCELSSIZE 1024 /* maximum ELS transfer size */
43
44#define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
James Smarta4bc3372006-12-02 13:34:16 -050045#define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
dea31012005-04-17 16:05:31 -050046#define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
47#define LPFC_FCP_NEXT_RING 3
James Smart1ba981f2014-02-20 09:56:45 -050048#define LPFC_FCP_OAS_RING 3
dea31012005-04-17 16:05:31 -050049
50#define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
51#define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
James Smarta4bc3372006-12-02 13:34:16 -050052#define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
53#define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
dea31012005-04-17 16:05:31 -050054#define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
55#define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
56#define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
57#define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
58#define SLI2_IOCB_CMD_R3_ENTRIES 0
59#define SLI2_IOCB_RSP_R3_ENTRIES 0
60#define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
61#define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
62
James Smarted957682007-06-17 19:56:37 -050063#define SLI2_IOCB_CMD_SIZE 32
64#define SLI2_IOCB_RSP_SIZE 32
65#define SLI3_IOCB_CMD_SIZE 128
66#define SLI3_IOCB_RSP_SIZE 64
67
James Smart6d368e52011-05-24 11:44:12 -040068#define LPFC_UNREG_ALL_RPIS_VPORT 0xffff
69#define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff
James Smart92d7f7b2007-06-17 19:56:38 -050070
James Smartddcc50f2008-12-04 22:38:46 -050071/* vendor ID used in SCSI netlink calls */
72#define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
73
James Smart6b5151f2012-01-18 16:24:06 -050074#define FW_REV_STR_SIZE 32
dea31012005-04-17 16:05:31 -050075/* Common Transport structures and definitions */
76
77union CtRevisionId {
78 /* Structure is in Big Endian format */
79 struct {
80 uint32_t Revision:8;
81 uint32_t InId:24;
82 } bits;
83 uint32_t word;
84};
85
86union CtCommandResponse {
87 /* Structure is in Big Endian format */
88 struct {
89 uint32_t CmdRsp:16;
90 uint32_t Size:16;
91 } bits;
92 uint32_t word;
93};
94
James Smart92d7f7b2007-06-17 19:56:38 -050095#define FC4_FEATURE_INIT 0x2
96#define FC4_FEATURE_TARGET 0x1
97
dea31012005-04-17 16:05:31 -050098struct lpfc_sli_ct_request {
99 /* Structure is in Big Endian format */
100 union CtRevisionId RevisionId;
101 uint8_t FsType;
102 uint8_t FsSubType;
103 uint8_t Options;
104 uint8_t Rsrvd1;
105 union CtCommandResponse CommandResponse;
106 uint8_t Rsrvd2;
107 uint8_t ReasonCode;
108 uint8_t Explanation;
109 uint8_t VendorUnique;
110
111 union {
112 uint32_t PortID;
113 struct gid {
114 uint8_t PortType; /* for GID_PT requests */
115 uint8_t DomainScope;
116 uint8_t AreaScope;
117 uint8_t Fc4Type; /* for GID_FT requests */
118 } gid;
119 struct rft {
120 uint32_t PortId; /* For RFT_ID requests */
121
122#ifdef __BIG_ENDIAN_BITFIELD
123 uint32_t rsvd0:16;
124 uint32_t rsvd1:7;
125 uint32_t fcpReg:1; /* Type 8 */
126 uint32_t rsvd2:2;
127 uint32_t ipReg:1; /* Type 5 */
128 uint32_t rsvd3:5;
129#else /* __LITTLE_ENDIAN_BITFIELD */
130 uint32_t rsvd0:16;
131 uint32_t fcpReg:1; /* Type 8 */
132 uint32_t rsvd1:7;
133 uint32_t rsvd3:5;
134 uint32_t ipReg:1; /* Type 5 */
135 uint32_t rsvd2:2;
136#endif
137
138 uint32_t rsvd[7];
139 } rft;
140 struct rnn {
141 uint32_t PortId; /* For RNN_ID requests */
142 uint8_t wwnn[8];
143 } rnn;
144 struct rsnn { /* For RSNN_ID requests */
145 uint8_t wwnn[8];
146 uint8_t len;
147 uint8_t symbname[255];
148 } rsnn;
James Smart7ee5d432007-10-27 13:37:17 -0400149 struct da_id { /* For DA_ID requests */
150 uint32_t port_id;
151 } da_id;
James Smart92d7f7b2007-06-17 19:56:38 -0500152 struct rspn { /* For RSPN_ID requests */
153 uint32_t PortId;
154 uint8_t len;
155 uint8_t symbname[255];
156 } rspn;
157 struct gff {
158 uint32_t PortId;
159 } gff;
160 struct gff_acc {
161 uint8_t fbits[128];
162 } gff_acc;
James Smart51ef4c22007-08-02 11:10:31 -0400163#define FCP_TYPE_FEATURE_OFFSET 7
James Smart92d7f7b2007-06-17 19:56:38 -0500164 struct rff {
165 uint32_t PortId;
166 uint8_t reserved[2];
167 uint8_t fbits;
168 uint8_t type_code; /* type=8 for FCP */
169 } rff;
dea31012005-04-17 16:05:31 -0500170 } un;
171};
172
173#define SLI_CT_REVISION 1
James Smart92d7f7b2007-06-17 19:56:38 -0500174#define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
175 sizeof(struct gid))
176#define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
177 sizeof(struct gff))
178#define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
179 sizeof(struct rft))
180#define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
181 sizeof(struct rff))
182#define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
183 sizeof(struct rnn))
184#define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
185 sizeof(struct rsnn))
James Smart7ee5d432007-10-27 13:37:17 -0400186#define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
187 sizeof(struct da_id))
James Smart92d7f7b2007-06-17 19:56:38 -0500188#define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
189 sizeof(struct rspn))
dea31012005-04-17 16:05:31 -0500190
191/*
192 * FsType Definitions
193 */
194
195#define SLI_CT_MANAGEMENT_SERVICE 0xFA
196#define SLI_CT_TIME_SERVICE 0xFB
197#define SLI_CT_DIRECTORY_SERVICE 0xFC
198#define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
199
200/*
201 * Directory Service Subtypes
202 */
203
204#define SLI_CT_DIRECTORY_NAME_SERVER 0x02
205
206/*
207 * Response Codes
208 */
209
210#define SLI_CT_RESPONSE_FS_RJT 0x8001
211#define SLI_CT_RESPONSE_FS_ACC 0x8002
212
213/*
214 * Reason Codes
215 */
216
217#define SLI_CT_NO_ADDITIONAL_EXPL 0x0
218#define SLI_CT_INVALID_COMMAND 0x01
219#define SLI_CT_INVALID_VERSION 0x02
220#define SLI_CT_LOGICAL_ERROR 0x03
221#define SLI_CT_INVALID_IU_SIZE 0x04
222#define SLI_CT_LOGICAL_BUSY 0x05
223#define SLI_CT_PROTOCOL_ERROR 0x07
224#define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
225#define SLI_CT_REQ_NOT_SUPPORTED 0x0b
226#define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
227#define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
228#define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
229#define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
230#define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
231#define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
232#define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
233#define SLI_CT_VENDOR_UNIQUE 0xff
234
235/*
236 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
237 */
238
239#define SLI_CT_NO_PORT_ID 0x01
240#define SLI_CT_NO_PORT_NAME 0x02
241#define SLI_CT_NO_NODE_NAME 0x03
242#define SLI_CT_NO_CLASS_OF_SERVICE 0x04
243#define SLI_CT_NO_IP_ADDRESS 0x05
244#define SLI_CT_NO_IPA 0x06
245#define SLI_CT_NO_FC4_TYPES 0x07
246#define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
247#define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
248#define SLI_CT_NO_PORT_TYPE 0x0A
249#define SLI_CT_ACCESS_DENIED 0x10
250#define SLI_CT_INVALID_PORT_ID 0x11
251#define SLI_CT_DATABASE_EMPTY 0x12
252
253/*
254 * Name Server Command Codes
255 */
256
257#define SLI_CTNS_GA_NXT 0x0100
258#define SLI_CTNS_GPN_ID 0x0112
259#define SLI_CTNS_GNN_ID 0x0113
260#define SLI_CTNS_GCS_ID 0x0114
261#define SLI_CTNS_GFT_ID 0x0117
262#define SLI_CTNS_GSPN_ID 0x0118
263#define SLI_CTNS_GPT_ID 0x011A
James Smart92d7f7b2007-06-17 19:56:38 -0500264#define SLI_CTNS_GFF_ID 0x011F
dea31012005-04-17 16:05:31 -0500265#define SLI_CTNS_GID_PN 0x0121
266#define SLI_CTNS_GID_NN 0x0131
267#define SLI_CTNS_GIP_NN 0x0135
268#define SLI_CTNS_GIPA_NN 0x0136
269#define SLI_CTNS_GSNN_NN 0x0139
270#define SLI_CTNS_GNN_IP 0x0153
271#define SLI_CTNS_GIPA_IP 0x0156
272#define SLI_CTNS_GID_FT 0x0171
273#define SLI_CTNS_GID_PT 0x01A1
274#define SLI_CTNS_RPN_ID 0x0212
275#define SLI_CTNS_RNN_ID 0x0213
276#define SLI_CTNS_RCS_ID 0x0214
277#define SLI_CTNS_RFT_ID 0x0217
278#define SLI_CTNS_RSPN_ID 0x0218
279#define SLI_CTNS_RPT_ID 0x021A
James Smart92d7f7b2007-06-17 19:56:38 -0500280#define SLI_CTNS_RFF_ID 0x021F
dea31012005-04-17 16:05:31 -0500281#define SLI_CTNS_RIP_NN 0x0235
282#define SLI_CTNS_RIPA_NN 0x0236
283#define SLI_CTNS_RSNN_NN 0x0239
284#define SLI_CTNS_DA_ID 0x0300
285
286/*
287 * Port Types
288 */
289
290#define SLI_CTPT_N_PORT 0x01
291#define SLI_CTPT_NL_PORT 0x02
292#define SLI_CTPT_FNL_PORT 0x03
293#define SLI_CTPT_IP 0x04
294#define SLI_CTPT_FCP 0x08
295#define SLI_CTPT_NX_PORT 0x7F
296#define SLI_CTPT_F_PORT 0x81
297#define SLI_CTPT_FL_PORT 0x82
298#define SLI_CTPT_E_PORT 0x84
299
300#define SLI_CT_LAST_ENTRY 0x80000000
301
302/* Fibre Channel Service Parameter definitions */
303
304#define FC_PH_4_0 6 /* FC-PH version 4.0 */
305#define FC_PH_4_1 7 /* FC-PH version 4.1 */
306#define FC_PH_4_2 8 /* FC-PH version 4.2 */
307#define FC_PH_4_3 9 /* FC-PH version 4.3 */
308
309#define FC_PH_LOW 8 /* Lowest supported FC-PH version */
310#define FC_PH_HIGH 9 /* Highest supported FC-PH version */
311#define FC_PH3 0x20 /* FC-PH-3 version */
312
313#define FF_FRAME_SIZE 2048
314
315struct lpfc_name {
Andrew Vasquezf631b4b2005-08-31 15:23:12 -0700316 union {
317 struct {
dea31012005-04-17 16:05:31 -0500318#ifdef __BIG_ENDIAN_BITFIELD
Andrew Vasquezf631b4b2005-08-31 15:23:12 -0700319 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
James.Smart@Emulex.Com1de933f2005-11-28 11:41:15 -0500320 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
321 8:11 of IEEE ext */
dea31012005-04-17 16:05:31 -0500322#else /* __LITTLE_ENDIAN_BITFIELD */
James.Smart@Emulex.Com1de933f2005-11-28 11:41:15 -0500323 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
324 8:11 of IEEE ext */
Andrew Vasquezf631b4b2005-08-31 15:23:12 -0700325 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
dea31012005-04-17 16:05:31 -0500326#endif
327
328#define NAME_IEEE 0x1 /* IEEE name - nameType */
329#define NAME_IEEE_EXT 0x2 /* IEEE extended name */
330#define NAME_FC_TYPE 0x3 /* FC native name type */
331#define NAME_IP_TYPE 0x4 /* IP address */
332#define NAME_CCITT_TYPE 0xC
333#define NAME_CCITT_GR_TYPE 0xE
James.Smart@Emulex.Com1de933f2005-11-28 11:41:15 -0500334 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
335 extended Lsb */
Andrew Vasquezf631b4b2005-08-31 15:23:12 -0700336 uint8_t IEEE[6]; /* FC IEEE address */
Andrew Morton68ce1eb2005-09-21 09:46:54 -0700337 } s;
Andrew Vasquezf631b4b2005-08-31 15:23:12 -0700338 uint8_t wwn[8];
Andrew Morton68ce1eb2005-09-21 09:46:54 -0700339 } u;
dea31012005-04-17 16:05:31 -0500340};
341
342struct csp {
343 uint8_t fcphHigh; /* FC Word 0, byte 0 */
344 uint8_t fcphLow;
345 uint8_t bbCreditMsb;
346 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */
347
James Smart92494142011-02-16 12:39:44 -0500348/*
349 * Word 1 Bit 31 in common service parameter is overloaded.
350 * Word 1 Bit 31 in FLOGI request is multiple NPort request
351 * Word 1 Bit 31 in FLOGI response is clean address bit
352 */
353#define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
James Smartdf9e1b52011-12-13 13:22:17 -0500354/*
355 * Word 1 Bit 30 in common service parameter is overloaded.
356 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics
357 * Word 1 Bit 30 in PLOGI request is random offset
358 */
359#define virtual_fabric_support randomOffset /* Word 1, bit 30 */
dea31012005-04-17 16:05:31 -0500360#ifdef __BIG_ENDIAN_BITFIELD
James Smart92d7f7b2007-06-17 19:56:38 -0500361 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
362 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
363 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
dea31012005-04-17 16:05:31 -0500364 uint16_t fPort:1; /* FC Word 1, bit 28 */
365 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
366 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
367 uint16_t multicast:1; /* FC Word 1, bit 25 */
368 uint16_t broadcast:1; /* FC Word 1, bit 24 */
369
370 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
371 uint16_t simplex:1; /* FC Word 1, bit 22 */
372 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
373 uint16_t dhd:1; /* FC Word 1, bit 18 */
374 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
375 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
376#else /* __LITTLE_ENDIAN_BITFIELD */
377 uint16_t broadcast:1; /* FC Word 1, bit 24 */
378 uint16_t multicast:1; /* FC Word 1, bit 25 */
379 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
380 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
381 uint16_t fPort:1; /* FC Word 1, bit 28 */
James Smart92d7f7b2007-06-17 19:56:38 -0500382 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
dea31012005-04-17 16:05:31 -0500383 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
James Smart92d7f7b2007-06-17 19:56:38 -0500384 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
dea31012005-04-17 16:05:31 -0500385
386 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
387 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
388 uint16_t dhd:1; /* FC Word 1, bit 18 */
389 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
390 uint16_t simplex:1; /* FC Word 1, bit 22 */
391 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
392#endif
393
394 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
395 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
396 union {
397 struct {
398 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
399
400 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
401 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
402
403 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
404 } nPort;
405 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
406 } w2;
407
408 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
409};
410
411struct class_parms {
412#ifdef __BIG_ENDIAN_BITFIELD
413 uint8_t classValid:1; /* FC Word 0, bit 31 */
414 uint8_t intermix:1; /* FC Word 0, bit 30 */
415 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
416 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
417 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
418 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
419#else /* __LITTLE_ENDIAN_BITFIELD */
420 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
421 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
422 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
423 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
424 uint8_t intermix:1; /* FC Word 0, bit 30 */
425 uint8_t classValid:1; /* FC Word 0, bit 31 */
426
427#endif
428
429 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
430
431#ifdef __BIG_ENDIAN_BITFIELD
432 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
433 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
434 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
435 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
436 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
437#else /* __LITTLE_ENDIAN_BITFIELD */
438 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
439 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
440 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
441 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
442 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
443#endif
444
445 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
446
447#ifdef __BIG_ENDIAN_BITFIELD
448 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
449 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
450 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
451 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
452 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
453 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
454#else /* __LITTLE_ENDIAN_BITFIELD */
455 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
456 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
457 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
458 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
459 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
460 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
461#endif
462
463 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
464 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
465 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
466
467 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
468 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
469 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
470 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
471
472 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
473 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
474 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
475 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
476};
477
478struct serv_parm { /* Structure is in Big Endian format */
479 struct csp cmn;
480 struct lpfc_name portName;
481 struct lpfc_name nodeName;
482 struct class_parms cls1;
483 struct class_parms cls2;
484 struct class_parms cls3;
485 struct class_parms cls4;
486 uint8_t vendorVersion[16];
487};
488
489/*
James Smartda0436e2009-05-22 14:51:39 -0400490 * Virtual Fabric Tagging Header
491 */
492struct fc_vft_header {
493 uint32_t word0;
494#define fc_vft_hdr_r_ctl_SHIFT 24
495#define fc_vft_hdr_r_ctl_MASK 0xFF
496#define fc_vft_hdr_r_ctl_WORD word0
497#define fc_vft_hdr_ver_SHIFT 22
498#define fc_vft_hdr_ver_MASK 0x3
499#define fc_vft_hdr_ver_WORD word0
500#define fc_vft_hdr_type_SHIFT 18
501#define fc_vft_hdr_type_MASK 0xF
502#define fc_vft_hdr_type_WORD word0
503#define fc_vft_hdr_e_SHIFT 16
504#define fc_vft_hdr_e_MASK 0x1
505#define fc_vft_hdr_e_WORD word0
506#define fc_vft_hdr_priority_SHIFT 13
507#define fc_vft_hdr_priority_MASK 0x7
508#define fc_vft_hdr_priority_WORD word0
509#define fc_vft_hdr_vf_id_SHIFT 1
510#define fc_vft_hdr_vf_id_MASK 0xFFF
511#define fc_vft_hdr_vf_id_WORD word0
512 uint32_t word1;
513#define fc_vft_hdr_hopct_SHIFT 24
514#define fc_vft_hdr_hopct_MASK 0xFF
515#define fc_vft_hdr_hopct_WORD word1
516};
517
518/*
dea31012005-04-17 16:05:31 -0500519 * Extended Link Service LS_COMMAND codes (Payload Word 0)
520 */
521#ifdef __BIG_ENDIAN_BITFIELD
522#define ELS_CMD_MASK 0xffff0000
523#define ELS_RSP_MASK 0xff000000
524#define ELS_CMD_LS_RJT 0x01000000
525#define ELS_CMD_ACC 0x02000000
526#define ELS_CMD_PLOGI 0x03000000
527#define ELS_CMD_FLOGI 0x04000000
528#define ELS_CMD_LOGO 0x05000000
529#define ELS_CMD_ABTX 0x06000000
530#define ELS_CMD_RCS 0x07000000
531#define ELS_CMD_RES 0x08000000
532#define ELS_CMD_RSS 0x09000000
533#define ELS_CMD_RSI 0x0A000000
534#define ELS_CMD_ESTS 0x0B000000
535#define ELS_CMD_ESTC 0x0C000000
536#define ELS_CMD_ADVC 0x0D000000
537#define ELS_CMD_RTV 0x0E000000
538#define ELS_CMD_RLS 0x0F000000
539#define ELS_CMD_ECHO 0x10000000
540#define ELS_CMD_TEST 0x11000000
541#define ELS_CMD_RRQ 0x12000000
James Smart303f2f92013-01-03 15:43:11 -0500542#define ELS_CMD_REC 0x13000000
dea31012005-04-17 16:05:31 -0500543#define ELS_CMD_PRLI 0x20100014
544#define ELS_CMD_PRLO 0x21100014
James Smart82d9a2a2006-04-15 11:53:05 -0400545#define ELS_CMD_PRLO_ACC 0x02100014
dea31012005-04-17 16:05:31 -0500546#define ELS_CMD_PDISC 0x50000000
547#define ELS_CMD_FDISC 0x51000000
548#define ELS_CMD_ADISC 0x52000000
549#define ELS_CMD_FARP 0x54000000
550#define ELS_CMD_FARPR 0x55000000
Jamie Wellnitz7bb3b132006-02-28 19:25:15 -0500551#define ELS_CMD_RPS 0x56000000
552#define ELS_CMD_RPL 0x57000000
dea31012005-04-17 16:05:31 -0500553#define ELS_CMD_FAN 0x60000000
554#define ELS_CMD_RSCN 0x61040000
555#define ELS_CMD_SCR 0x62000000
556#define ELS_CMD_RNID 0x78000000
Jamie Wellnitz7bb3b132006-02-28 19:25:15 -0500557#define ELS_CMD_LIRR 0x7A000000
dea31012005-04-17 16:05:31 -0500558#else /* __LITTLE_ENDIAN_BITFIELD */
559#define ELS_CMD_MASK 0xffff
560#define ELS_RSP_MASK 0xff
561#define ELS_CMD_LS_RJT 0x01
562#define ELS_CMD_ACC 0x02
563#define ELS_CMD_PLOGI 0x03
564#define ELS_CMD_FLOGI 0x04
565#define ELS_CMD_LOGO 0x05
566#define ELS_CMD_ABTX 0x06
567#define ELS_CMD_RCS 0x07
568#define ELS_CMD_RES 0x08
569#define ELS_CMD_RSS 0x09
570#define ELS_CMD_RSI 0x0A
571#define ELS_CMD_ESTS 0x0B
572#define ELS_CMD_ESTC 0x0C
573#define ELS_CMD_ADVC 0x0D
574#define ELS_CMD_RTV 0x0E
575#define ELS_CMD_RLS 0x0F
576#define ELS_CMD_ECHO 0x10
577#define ELS_CMD_TEST 0x11
578#define ELS_CMD_RRQ 0x12
James Smart303f2f92013-01-03 15:43:11 -0500579#define ELS_CMD_REC 0x13
dea31012005-04-17 16:05:31 -0500580#define ELS_CMD_PRLI 0x14001020
581#define ELS_CMD_PRLO 0x14001021
James Smart82d9a2a2006-04-15 11:53:05 -0400582#define ELS_CMD_PRLO_ACC 0x14001002
dea31012005-04-17 16:05:31 -0500583#define ELS_CMD_PDISC 0x50
584#define ELS_CMD_FDISC 0x51
585#define ELS_CMD_ADISC 0x52
586#define ELS_CMD_FARP 0x54
587#define ELS_CMD_FARPR 0x55
Jamie Wellnitz7bb3b132006-02-28 19:25:15 -0500588#define ELS_CMD_RPS 0x56
589#define ELS_CMD_RPL 0x57
dea31012005-04-17 16:05:31 -0500590#define ELS_CMD_FAN 0x60
591#define ELS_CMD_RSCN 0x0461
592#define ELS_CMD_SCR 0x62
593#define ELS_CMD_RNID 0x78
Jamie Wellnitz7bb3b132006-02-28 19:25:15 -0500594#define ELS_CMD_LIRR 0x7A
dea31012005-04-17 16:05:31 -0500595#endif
596
597/*
598 * LS_RJT Payload Definition
599 */
600
601struct ls_rjt { /* Structure is in Big Endian format */
602 union {
603 uint32_t lsRjtError;
604 struct {
605 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
606
607 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
608 /* LS_RJT reason codes */
609#define LSRJT_INVALID_CMD 0x01
610#define LSRJT_LOGICAL_ERR 0x03
611#define LSRJT_LOGICAL_BSY 0x05
612#define LSRJT_PROTOCOL_ERR 0x07
613#define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
614#define LSRJT_CMD_UNSUPPORTED 0x0B
615#define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
616
617 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
618 /* LS_RJT reason explanation */
619#define LSEXP_NOTHING_MORE 0x00
620#define LSEXP_SPARM_OPTIONS 0x01
621#define LSEXP_SPARM_ICTL 0x03
622#define LSEXP_SPARM_RCTL 0x05
623#define LSEXP_SPARM_RCV_SIZE 0x07
624#define LSEXP_SPARM_CONCUR_SEQ 0x09
625#define LSEXP_SPARM_CREDIT 0x0B
626#define LSEXP_INVALID_PNAME 0x0D
627#define LSEXP_INVALID_NNAME 0x0E
628#define LSEXP_INVALID_CSP 0x0F
629#define LSEXP_INVALID_ASSOC_HDR 0x11
630#define LSEXP_ASSOC_HDR_REQ 0x13
631#define LSEXP_INVALID_O_SID 0x15
632#define LSEXP_INVALID_OX_RX 0x17
633#define LSEXP_CMD_IN_PROGRESS 0x19
James Smart7f5f3d02008-02-08 18:50:14 -0500634#define LSEXP_PORT_LOGIN_REQ 0x1E
dea31012005-04-17 16:05:31 -0500635#define LSEXP_INVALID_NPORT_ID 0x1F
636#define LSEXP_INVALID_SEQ_ID 0x21
637#define LSEXP_INVALID_XCHG 0x23
638#define LSEXP_INACTIVE_XCHG 0x25
639#define LSEXP_RQ_REQUIRED 0x27
640#define LSEXP_OUT_OF_RESOURCE 0x29
641#define LSEXP_CANT_GIVE_DATA 0x2A
642#define LSEXP_REQ_UNSUPPORTED 0x2C
643 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
644 } b;
645 } un;
646};
647
648/*
649 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
650 */
651
652typedef struct _LOGO { /* Structure is in Big Endian format */
653 union {
654 uint32_t nPortId32; /* Access nPortId as a word */
655 struct {
656 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
657 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
658 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
659 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
660 } b;
661 } un;
662 struct lpfc_name portName; /* N_port name field */
663} LOGO;
664
665/*
666 * FCP Login (PRLI Request / ACC) Payload Definition
667 */
668
669#define PRLX_PAGE_LEN 0x10
670#define TPRLO_PAGE_LEN 0x14
671
672typedef struct _PRLI { /* Structure is in Big Endian format */
673 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
674
675#define PRLI_FCP_TYPE 0x08
676 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
677
678#ifdef __BIG_ENDIAN_BITFIELD
679 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
680 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
681 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
682
683 /* ACC = imagePairEstablished */
684 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
685 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
686#else /* __LITTLE_ENDIAN_BITFIELD */
687 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
688 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
689 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
690 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
691 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
692 /* ACC = imagePairEstablished */
693#endif
694
695#define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
696#define PRLI_NO_RESOURCES 0x2
697#define PRLI_INIT_INCOMPLETE 0x3
698#define PRLI_NO_SUCH_PA 0x4
699#define PRLI_PREDEF_CONFIG 0x5
700#define PRLI_PARTIAL_SUCCESS 0x6
701#define PRLI_INVALID_PAGE_CNT 0x7
702 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
703
704 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
705
706 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
707
708 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
709 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
710
711#ifdef __BIG_ENDIAN_BITFIELD
712 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
713 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
714 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
715 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
716 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
717 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
718 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
719 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
720 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
721 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
722 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
723 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
724 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
725 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
726 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
727 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
728#else /* __LITTLE_ENDIAN_BITFIELD */
729 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
730 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
731 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
732 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
733 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
734 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
735 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
736 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
737 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
738 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
739 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
740 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
741 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
742 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
743 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
744 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
745#endif
746} PRLI;
747
748/*
749 * FCP Logout (PRLO Request / ACC) Payload Definition
750 */
751
752typedef struct _PRLO { /* Structure is in Big Endian format */
753 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
754
755#define PRLO_FCP_TYPE 0x08
756 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
757
758#ifdef __BIG_ENDIAN_BITFIELD
759 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
760 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
761 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
762 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
763#else /* __LITTLE_ENDIAN_BITFIELD */
764 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
765 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
766 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
767 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
768#endif
769
770#define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
771#define PRLO_NO_SUCH_IMAGE 0x4
772#define PRLO_INVALID_PAGE_CNT 0x7
773
774 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
775
776 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
777
778 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
779
780 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
781} PRLO;
782
783typedef struct _ADISC { /* Structure is in Big Endian format */
784 uint32_t hardAL_PA;
785 struct lpfc_name portName;
786 struct lpfc_name nodeName;
787 uint32_t DID;
788} ADISC;
789
790typedef struct _FARP { /* Structure is in Big Endian format */
791 uint32_t Mflags:8;
792 uint32_t Odid:24;
793#define FARP_NO_ACTION 0 /* FARP information enclosed, no
794 action */
795#define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
796#define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
797#define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
798#define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
799 supported */
800#define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
801 supported */
802 uint32_t Rflags:8;
803 uint32_t Rdid:24;
804#define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
805#define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
806 struct lpfc_name OportName;
807 struct lpfc_name OnodeName;
808 struct lpfc_name RportName;
809 struct lpfc_name RnodeName;
810 uint8_t Oipaddr[16];
811 uint8_t Ripaddr[16];
812} FARP;
813
814typedef struct _FAN { /* Structure is in Big Endian format */
815 uint32_t Fdid;
816 struct lpfc_name FportName;
817 struct lpfc_name FnodeName;
818} FAN;
819
820typedef struct _SCR { /* Structure is in Big Endian format */
821 uint8_t resvd1;
822 uint8_t resvd2;
823 uint8_t resvd3;
824 uint8_t Function;
825#define SCR_FUNC_FABRIC 0x01
826#define SCR_FUNC_NPORT 0x02
827#define SCR_FUNC_FULL 0x03
828#define SCR_CLEAR 0xff
829} SCR;
830
831typedef struct _RNID_TOP_DISC {
832 struct lpfc_name portName;
833 uint8_t resvd[8];
834 uint32_t unitType;
835#define RNID_HBA 0x7
836#define RNID_HOST 0xa
837#define RNID_DRIVER 0xd
838 uint32_t physPort;
839 uint32_t attachedNodes;
840 uint16_t ipVersion;
841#define RNID_IPV4 0x1
842#define RNID_IPV6 0x2
843 uint16_t UDPport;
844 uint8_t ipAddr[16];
845 uint16_t resvd1;
846 uint16_t flags;
847#define RNID_TD_SUPPORT 0x1
848#define RNID_LP_VALID 0x2
849} RNID_TOP_DISC;
850
851typedef struct _RNID { /* Structure is in Big Endian format */
852 uint8_t Format;
853#define RNID_TOPOLOGY_DISC 0xdf
854 uint8_t CommonLen;
855 uint8_t resvd1;
856 uint8_t SpecificLen;
857 struct lpfc_name portName;
858 struct lpfc_name nodeName;
859 union {
860 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
861 } un;
862} RNID;
863
James Smart311464e2007-08-02 11:10:37 -0400864typedef struct _RPS { /* Structure is in Big Endian format */
Jamie Wellnitz7bb3b132006-02-28 19:25:15 -0500865 union {
866 uint32_t portNum;
867 struct lpfc_name portName;
868 } un;
869} RPS;
870
871typedef struct _RPS_RSP { /* Structure is in Big Endian format */
872 uint16_t rsvd1;
873 uint16_t portStatus;
874 uint32_t linkFailureCnt;
875 uint32_t lossSyncCnt;
876 uint32_t lossSignalCnt;
877 uint32_t primSeqErrCnt;
878 uint32_t invalidXmitWord;
879 uint32_t crcCnt;
880} RPS_RSP;
881
James Smart12265f62010-10-22 11:05:53 -0400882struct RLS { /* Structure is in Big Endian format */
883 uint32_t rls;
884#define rls_rsvd_SHIFT 24
885#define rls_rsvd_MASK 0x000000ff
886#define rls_rsvd_WORD rls
887#define rls_did_SHIFT 0
888#define rls_did_MASK 0x00ffffff
889#define rls_did_WORD rls
890};
891
892struct RLS_RSP { /* Structure is in Big Endian format */
893 uint32_t linkFailureCnt;
894 uint32_t lossSyncCnt;
895 uint32_t lossSignalCnt;
896 uint32_t primSeqErrCnt;
897 uint32_t invalidXmitWord;
898 uint32_t crcCnt;
899};
900
James Smart19ca7602010-11-20 23:11:55 -0500901struct RRQ { /* Structure is in Big Endian format */
902 uint32_t rrq;
903#define rrq_rsvd_SHIFT 24
904#define rrq_rsvd_MASK 0x000000ff
905#define rrq_rsvd_WORD rrq
906#define rrq_did_SHIFT 0
907#define rrq_did_MASK 0x00ffffff
908#define rrq_did_WORD rrq
909 uint32_t rrq_exchg;
910#define rrq_oxid_SHIFT 16
911#define rrq_oxid_MASK 0xffff
912#define rrq_oxid_WORD rrq_exchg
913#define rrq_rxid_SHIFT 0
914#define rrq_rxid_MASK 0xffff
915#define rrq_rxid_WORD rrq_exchg
916};
917
James Smart912e3ac2011-05-24 11:42:11 -0400918#define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */
919#define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/
James Smart19ca7602010-11-20 23:11:55 -0500920
James Smart12265f62010-10-22 11:05:53 -0400921struct RTV_RSP { /* Structure is in Big Endian format */
922 uint32_t ratov;
923 uint32_t edtov;
924 uint32_t qtov;
925#define qtov_rsvd0_SHIFT 28
926#define qtov_rsvd0_MASK 0x0000000f
927#define qtov_rsvd0_WORD qtov /* reserved */
928#define qtov_edtovres_SHIFT 27
929#define qtov_edtovres_MASK 0x00000001
930#define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */
931#define qtov__rsvd1_SHIFT 19
932#define qtov_rsvd1_MASK 0x0000003f
933#define qtov_rsvd1_WORD qtov /* reserved */
934#define qtov_rttov_SHIFT 18
935#define qtov_rttov_MASK 0x00000001
936#define qtov_rttov_WORD qtov /* R_T_TOV value */
937#define qtov_rsvd2_SHIFT 0
938#define qtov_rsvd2_MASK 0x0003ffff
939#define qtov_rsvd2_WORD qtov /* reserved */
940};
941
942
James Smart311464e2007-08-02 11:10:37 -0400943typedef struct _RPL { /* Structure is in Big Endian format */
Jamie Wellnitz7bb3b132006-02-28 19:25:15 -0500944 uint32_t maxsize;
945 uint32_t index;
946} RPL;
947
948typedef struct _PORT_NUM_BLK {
949 uint32_t portNum;
950 uint32_t portID;
951 struct lpfc_name portName;
952} PORT_NUM_BLK;
953
James Smart311464e2007-08-02 11:10:37 -0400954typedef struct _RPL_RSP { /* Structure is in Big Endian format */
Jamie Wellnitz7bb3b132006-02-28 19:25:15 -0500955 uint32_t listLen;
956 uint32_t index;
957 PORT_NUM_BLK port_num_blk;
958} RPL_RSP;
dea31012005-04-17 16:05:31 -0500959
960/* This is used for RSCN command */
961typedef struct _D_ID { /* Structure is in Big Endian format */
962 union {
963 uint32_t word;
964 struct {
965#ifdef __BIG_ENDIAN_BITFIELD
966 uint8_t resv;
967 uint8_t domain;
968 uint8_t area;
969 uint8_t id;
970#else /* __LITTLE_ENDIAN_BITFIELD */
971 uint8_t id;
972 uint8_t area;
973 uint8_t domain;
974 uint8_t resv;
975#endif
976 } b;
977 } un;
978} D_ID;
979
James Smarteaf15d52008-12-04 22:39:29 -0500980#define RSCN_ADDRESS_FORMAT_PORT 0x0
981#define RSCN_ADDRESS_FORMAT_AREA 0x1
982#define RSCN_ADDRESS_FORMAT_DOMAIN 0x2
983#define RSCN_ADDRESS_FORMAT_FABRIC 0x3
984#define RSCN_ADDRESS_FORMAT_MASK 0x3
985
dea31012005-04-17 16:05:31 -0500986/*
987 * Structure to define all ELS Payload types
988 */
989
990typedef struct _ELS_PKT { /* Structure is in Big Endian format */
991 uint8_t elsCode; /* FC Word 0, bit 24:31 */
992 uint8_t elsByte1;
993 uint8_t elsByte2;
994 uint8_t elsByte3;
995 union {
996 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
997 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
998 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
999 PRLI prli; /* Payload for PRLI/ACC */
1000 PRLO prlo; /* Payload for PRLO/ACC */
1001 ADISC adisc; /* Payload for ADISC/ACC */
1002 FARP farp; /* Payload for FARP/ACC */
1003 FAN fan; /* Payload for FAN */
1004 SCR scr; /* Payload for SCR/ACC */
dea31012005-04-17 16:05:31 -05001005 RNID rnid; /* Payload for RNID */
1006 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
1007 } un;
1008} ELS_PKT;
1009
1010/*
1011 * FDMI
1012 * HBA MAnagement Operations Command Codes
1013 */
1014#define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
1015#define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
1016#define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
1017#define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
1018#define SLI_MGMT_RHBA 0x200 /* Register HBA */
Justin P. Mattock70f23fd2011-05-10 10:16:21 +02001019#define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */
dea31012005-04-17 16:05:31 -05001020#define SLI_MGMT_RPRT 0x210 /* Register Port */
1021#define SLI_MGMT_RPA 0x211 /* Register Port attributes */
1022#define SLI_MGMT_DHBA 0x300 /* De-register HBA */
1023#define SLI_MGMT_DPRT 0x310 /* De-register Port */
1024
1025/*
1026 * Management Service Subtypes
1027 */
1028#define SLI_CT_FDMI_Subtypes 0x10
1029
1030/*
1031 * HBA Management Service Reject Code
1032 */
1033#define REJECT_CODE 0x9 /* Unable to perform command request */
1034
1035/*
1036 * HBA Management Service Reject Reason Code
1037 * Please refer to the Reason Codes above
1038 */
1039
1040/*
1041 * HBA Attribute Types
1042 */
1043#define NODE_NAME 0x1
1044#define MANUFACTURER 0x2
1045#define SERIAL_NUMBER 0x3
1046#define MODEL 0x4
1047#define MODEL_DESCRIPTION 0x5
1048#define HARDWARE_VERSION 0x6
1049#define DRIVER_VERSION 0x7
1050#define OPTION_ROM_VERSION 0x8
1051#define FIRMWARE_VERSION 0x9
1052#define OS_NAME_VERSION 0xa
1053#define MAX_CT_PAYLOAD_LEN 0xb
1054
1055/*
1056 * Port Attrubute Types
1057 */
1058#define SUPPORTED_FC4_TYPES 0x1
1059#define SUPPORTED_SPEED 0x2
1060#define PORT_SPEED 0x3
1061#define MAX_FRAME_SIZE 0x4
1062#define OS_DEVICE_NAME 0x5
1063#define HOST_NAME 0x6
1064
1065union AttributesDef {
1066 /* Structure is in Big Endian format */
1067 struct {
1068 uint32_t AttrType:16;
1069 uint32_t AttrLen:16;
1070 } bits;
1071 uint32_t word;
1072};
1073
1074
1075/*
1076 * HBA Attribute Entry (8 - 260 bytes)
1077 */
1078typedef struct {
1079 union AttributesDef ad;
1080 union {
1081 uint32_t VendorSpecific;
1082 uint8_t Manufacturer[64];
1083 uint8_t SerialNumber[64];
1084 uint8_t Model[256];
1085 uint8_t ModelDescription[256];
1086 uint8_t HardwareVersion[256];
1087 uint8_t DriverVersion[256];
1088 uint8_t OptionROMVersion[256];
1089 uint8_t FirmwareVersion[256];
1090 struct lpfc_name NodeName;
1091 uint8_t SupportFC4Types[32];
1092 uint32_t SupportSpeed;
1093 uint32_t PortSpeed;
1094 uint32_t MaxFrameSize;
1095 uint8_t OsDeviceName[256];
1096 uint8_t OsNameVersion[256];
1097 uint32_t MaxCTPayloadLen;
1098 uint8_t HostName[256];
1099 } un;
1100} ATTRIBUTE_ENTRY;
1101
1102/*
1103 * HBA Attribute Block
1104 */
1105typedef struct {
1106 uint32_t EntryCnt; /* Number of HBA attribute entries */
1107 ATTRIBUTE_ENTRY Entry; /* Variable-length array */
1108} ATTRIBUTE_BLOCK;
1109
1110/*
1111 * Port Entry
1112 */
1113typedef struct {
1114 struct lpfc_name PortName;
1115} PORT_ENTRY;
1116
1117/*
1118 * HBA Identifier
1119 */
1120typedef struct {
1121 struct lpfc_name PortName;
1122} HBA_IDENTIFIER;
1123
1124/*
1125 * Registered Port List Format
1126 */
1127typedef struct {
1128 uint32_t EntryCnt;
1129 PORT_ENTRY pe; /* Variable-length array */
1130} REG_PORT_LIST;
1131
1132/*
1133 * Register HBA(RHBA)
1134 */
1135typedef struct {
1136 HBA_IDENTIFIER hi;
1137 REG_PORT_LIST rpl; /* variable-length array */
1138/* ATTRIBUTE_BLOCK ab; */
1139} REG_HBA;
1140
1141/*
1142 * Register HBA Attributes (RHAT)
1143 */
1144typedef struct {
1145 struct lpfc_name HBA_PortName;
1146 ATTRIBUTE_BLOCK ab;
1147} REG_HBA_ATTRIBUTE;
1148
1149/*
1150 * Register Port Attributes (RPA)
1151 */
1152typedef struct {
1153 struct lpfc_name PortName;
1154 ATTRIBUTE_BLOCK ab;
1155} REG_PORT_ATTRIBUTE;
1156
1157/*
1158 * Get Registered HBA List (GRHL) Accept Payload Format
1159 */
1160typedef struct {
1161 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */
1162 struct lpfc_name HBA_PortName; /* Variable-length array */
1163} GRHL_ACC_PAYLOAD;
1164
1165/*
1166 * Get Registered Port List (GRPL) Accept Payload Format
1167 */
1168typedef struct {
1169 uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */
1170 PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */
1171} GRPL_ACC_PAYLOAD;
1172
1173/*
1174 * Get Port Attributes (GPAT) Accept Payload Format
1175 */
1176
1177typedef struct {
1178 ATTRIBUTE_BLOCK pab;
1179} GPAT_ACC_PAYLOAD;
1180
1181
1182/*
1183 * Begin HBA configuration parameters.
1184 * The PCI configuration register BAR assignments are:
1185 * BAR0, offset 0x10 - SLIM base memory address
1186 * BAR1, offset 0x14 - SLIM base memory high address
1187 * BAR2, offset 0x18 - REGISTER base memory address
1188 * BAR3, offset 0x1c - REGISTER base memory high address
1189 * BAR4, offset 0x20 - BIU I/O registers
1190 * BAR5, offset 0x24 - REGISTER base io high address
1191 */
1192
1193/* Number of rings currently used and available. */
James Smart2a76a282012-08-03 12:35:54 -04001194#define MAX_SLI3_CONFIGURED_RINGS 3
1195#define MAX_SLI3_RINGS 4
dea31012005-04-17 16:05:31 -05001196
1197/* IOCB / Mailbox is owned by FireFly */
1198#define OWN_CHIP 1
1199
1200/* IOCB / Mailbox is owned by Host */
1201#define OWN_HOST 0
1202
1203/* Number of 4-byte words in an IOCB. */
1204#define IOCB_WORD_SZ 8
1205
dea31012005-04-17 16:05:31 -05001206/* network headers for Dfctl field */
1207#define FC_NET_HDR 0x20
1208
1209/* Start FireFly Register definitions */
1210#define PCI_VENDOR_ID_EMULEX 0x10df
1211#define PCI_DEVICE_ID_FIREFLY 0x1ae5
James Smart84774a42008-08-24 21:50:06 -04001212#define PCI_DEVICE_ID_PROTEUS_VF 0xe100
James Smart085c6472010-11-20 23:11:37 -05001213#define PCI_DEVICE_ID_BALIUS 0xe131
James Smart84774a42008-08-24 21:50:06 -04001214#define PCI_DEVICE_ID_PROTEUS_PF 0xe180
James Smart085c6472010-11-20 23:11:37 -05001215#define PCI_DEVICE_ID_LANCER_FC 0xe200
James Smartc0c11512011-05-24 11:41:34 -04001216#define PCI_DEVICE_ID_LANCER_FC_VF 0xe208
James Smart085c6472010-11-20 23:11:37 -05001217#define PCI_DEVICE_ID_LANCER_FCOE 0xe260
James Smartc0c11512011-05-24 11:41:34 -04001218#define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
James Smartb87eab32007-04-25 09:53:28 -04001219#define PCI_DEVICE_ID_SAT_SMB 0xf011
1220#define PCI_DEVICE_ID_SAT_MID 0xf015
dea31012005-04-17 16:05:31 -05001221#define PCI_DEVICE_ID_RFLY 0xf095
1222#define PCI_DEVICE_ID_PFLY 0xf098
James.Smart@Emulex.Come4adb202005-11-28 11:42:12 -05001223#define PCI_DEVICE_ID_LP101 0xf0a1
dea31012005-04-17 16:05:31 -05001224#define PCI_DEVICE_ID_TFLY 0xf0a5
James.Smart@Emulex.Come4adb202005-11-28 11:42:12 -05001225#define PCI_DEVICE_ID_BSMB 0xf0d1
1226#define PCI_DEVICE_ID_BMID 0xf0d5
1227#define PCI_DEVICE_ID_ZSMB 0xf0e1
1228#define PCI_DEVICE_ID_ZMID 0xf0e5
1229#define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1230#define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1231#define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
James Smartb87eab32007-04-25 09:53:28 -04001232#define PCI_DEVICE_ID_SAT 0xf100
1233#define PCI_DEVICE_ID_SAT_SCSP 0xf111
1234#define PCI_DEVICE_ID_SAT_DCSP 0xf112
James Smart085c6472010-11-20 23:11:37 -05001235#define PCI_DEVICE_ID_FALCON 0xf180
James.Smart@Emulex.Come4adb202005-11-28 11:42:12 -05001236#define PCI_DEVICE_ID_SUPERFLY 0xf700
1237#define PCI_DEVICE_ID_DRAGONFLY 0xf800
dea31012005-04-17 16:05:31 -05001238#define PCI_DEVICE_ID_CENTAUR 0xf900
1239#define PCI_DEVICE_ID_PEGASUS 0xf980
1240#define PCI_DEVICE_ID_THOR 0xfa00
1241#define PCI_DEVICE_ID_VIPER 0xfb00
James.Smart@Emulex.Come4adb202005-11-28 11:42:12 -05001242#define PCI_DEVICE_ID_LP10000S 0xfc00
1243#define PCI_DEVICE_ID_LP11000S 0xfc10
1244#define PCI_DEVICE_ID_LPE11000S 0xfc20
James Smartb87eab32007-04-25 09:53:28 -04001245#define PCI_DEVICE_ID_SAT_S 0xfc40
James Smart84774a42008-08-24 21:50:06 -04001246#define PCI_DEVICE_ID_PROTEUS_S 0xfc50
dea31012005-04-17 16:05:31 -05001247#define PCI_DEVICE_ID_HELIOS 0xfd00
James.Smart@Emulex.Come4adb202005-11-28 11:42:12 -05001248#define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1249#define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
dea31012005-04-17 16:05:31 -05001250#define PCI_DEVICE_ID_ZEPHYR 0xfe00
James Smart84774a42008-08-24 21:50:06 -04001251#define PCI_DEVICE_ID_HORNET 0xfe05
James.Smart@Emulex.Come4adb202005-11-28 11:42:12 -05001252#define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1253#define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
James Smartda0436e2009-05-22 14:51:39 -04001254#define PCI_VENDOR_ID_SERVERENGINE 0x19a2
1255#define PCI_DEVICE_ID_TIGERSHARK 0x0704
James Smarta747c9c2009-11-18 15:41:10 -05001256#define PCI_DEVICE_ID_TOMCAT 0x0714
James Smartf8cafd32012-08-03 12:42:51 -04001257#define PCI_DEVICE_ID_SKYHAWK 0x0724
1258#define PCI_DEVICE_ID_SKYHAWK_VF 0x072c
dea31012005-04-17 16:05:31 -05001259
1260#define JEDEC_ID_ADDRESS 0x0080001c
1261#define FIREFLY_JEDEC_ID 0x1ACC
1262#define SUPERFLY_JEDEC_ID 0x0020
1263#define DRAGONFLY_JEDEC_ID 0x0021
1264#define DRAGONFLY_V2_JEDEC_ID 0x0025
1265#define CENTAUR_2G_JEDEC_ID 0x0026
1266#define CENTAUR_1G_JEDEC_ID 0x0028
1267#define PEGASUS_ORION_JEDEC_ID 0x0036
1268#define PEGASUS_JEDEC_ID 0x0038
1269#define THOR_JEDEC_ID 0x0012
1270#define HELIOS_JEDEC_ID 0x0364
1271#define ZEPHYR_JEDEC_ID 0x0577
1272#define VIPER_JEDEC_ID 0x4838
James Smartb87eab32007-04-25 09:53:28 -04001273#define SATURN_JEDEC_ID 0x1004
James Smart84774a42008-08-24 21:50:06 -04001274#define HORNET_JDEC_ID 0x2057706D
dea31012005-04-17 16:05:31 -05001275
1276#define JEDEC_ID_MASK 0x0FFFF000
1277#define JEDEC_ID_SHIFT 12
1278#define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1279
1280typedef struct { /* FireFly BIU registers */
1281 uint32_t hostAtt; /* See definitions for Host Attention
1282 register */
1283 uint32_t chipAtt; /* See definitions for Chip Attention
1284 register */
1285 uint32_t hostStatus; /* See definitions for Host Status register */
1286 uint32_t hostControl; /* See definitions for Host Control register */
1287 uint32_t buiConfig; /* See definitions for BIU configuration
1288 register */
1289} FF_REGS;
1290
1291/* IO Register size in bytes */
1292#define FF_REG_AREA_SIZE 256
1293
1294/* Host Attention Register */
1295
1296#define HA_REG_OFFSET 0 /* Byte offset from register base address */
1297
1298#define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1299#define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1300#define HA_R0ATT 0x00000008 /* Bit 3 */
1301#define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1302#define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1303#define HA_R1ATT 0x00000080 /* Bit 7 */
1304#define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1305#define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1306#define HA_R2ATT 0x00000800 /* Bit 11 */
1307#define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1308#define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1309#define HA_R3ATT 0x00008000 /* Bit 15 */
1310#define HA_LATT 0x20000000 /* Bit 29 */
1311#define HA_MBATT 0x40000000 /* Bit 30 */
1312#define HA_ERATT 0x80000000 /* Bit 31 */
1313
1314#define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1315#define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1316#define HA_RXATT 0x00000008 /* Bit 3 */
1317#define HA_RXMASK 0x0000000f
1318
James Smart93996272008-08-24 21:50:30 -04001319#define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1320#define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1321#define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1322#define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1323
1324#define HA_R0_POS 3
1325#define HA_R1_POS 7
1326#define HA_R2_POS 11
1327#define HA_R3_POS 15
1328#define HA_LE_POS 29
1329#define HA_MB_POS 30
1330#define HA_ER_POS 31
dea31012005-04-17 16:05:31 -05001331/* Chip Attention Register */
1332
1333#define CA_REG_OFFSET 4 /* Byte offset from register base address */
1334
1335#define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1336#define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1337#define CA_R0ATT 0x00000008 /* Bit 3 */
1338#define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1339#define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1340#define CA_R1ATT 0x00000080 /* Bit 7 */
1341#define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1342#define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1343#define CA_R2ATT 0x00000800 /* Bit 11 */
1344#define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1345#define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1346#define CA_R3ATT 0x00008000 /* Bit 15 */
1347#define CA_MBATT 0x40000000 /* Bit 30 */
1348
1349/* Host Status Register */
1350
1351#define HS_REG_OFFSET 8 /* Byte offset from register base address */
1352
1353#define HS_MBRDY 0x00400000 /* Bit 22 */
1354#define HS_FFRDY 0x00800000 /* Bit 23 */
1355#define HS_FFER8 0x01000000 /* Bit 24 */
1356#define HS_FFER7 0x02000000 /* Bit 25 */
1357#define HS_FFER6 0x04000000 /* Bit 26 */
1358#define HS_FFER5 0x08000000 /* Bit 27 */
1359#define HS_FFER4 0x10000000 /* Bit 28 */
1360#define HS_FFER3 0x20000000 /* Bit 29 */
1361#define HS_FFER2 0x40000000 /* Bit 30 */
1362#define HS_FFER1 0x80000000 /* Bit 31 */
James Smart57127f12007-10-27 13:37:05 -04001363#define HS_CRIT_TEMP 0x00000100 /* Bit 8 */
1364#define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */
James Smart9940b972011-03-11 16:06:12 -05001365#define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */
dea31012005-04-17 16:05:31 -05001366/* Host Control Register */
1367
James Smart93996272008-08-24 21:50:30 -04001368#define HC_REG_OFFSET 12 /* Byte offset from register base address */
dea31012005-04-17 16:05:31 -05001369
1370#define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1371#define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1372#define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1373#define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1374#define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1375#define HC_INITHBI 0x02000000 /* Bit 25 */
1376#define HC_INITMB 0x04000000 /* Bit 26 */
1377#define HC_INITFF 0x08000000 /* Bit 27 */
1378#define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1379#define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1380
James Smart93996272008-08-24 21:50:30 -04001381/* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1382#define MSIX_DFLT_ID 0
1383#define MSIX_RNG0_ID 0
1384#define MSIX_RNG1_ID 1
1385#define MSIX_RNG2_ID 2
1386#define MSIX_RNG3_ID 3
1387
1388#define MSIX_LINK_ID 4
1389#define MSIX_MBOX_ID 5
1390
1391#define MSIX_SPARE0_ID 6
1392#define MSIX_SPARE1_ID 7
1393
dea31012005-04-17 16:05:31 -05001394/* Mailbox Commands */
1395#define MBX_SHUTDOWN 0x00 /* terminate testing */
1396#define MBX_LOAD_SM 0x01
1397#define MBX_READ_NV 0x02
1398#define MBX_WRITE_NV 0x03
1399#define MBX_RUN_BIU_DIAG 0x04
1400#define MBX_INIT_LINK 0x05
1401#define MBX_DOWN_LINK 0x06
1402#define MBX_CONFIG_LINK 0x07
1403#define MBX_CONFIG_RING 0x09
1404#define MBX_RESET_RING 0x0A
1405#define MBX_READ_CONFIG 0x0B
1406#define MBX_READ_RCONFIG 0x0C
1407#define MBX_READ_SPARM 0x0D
1408#define MBX_READ_STATUS 0x0E
1409#define MBX_READ_RPI 0x0F
1410#define MBX_READ_XRI 0x10
1411#define MBX_READ_REV 0x11
1412#define MBX_READ_LNK_STAT 0x12
1413#define MBX_REG_LOGIN 0x13
1414#define MBX_UNREG_LOGIN 0x14
dea31012005-04-17 16:05:31 -05001415#define MBX_CLEAR_LA 0x16
1416#define MBX_DUMP_MEMORY 0x17
1417#define MBX_DUMP_CONTEXT 0x18
1418#define MBX_RUN_DIAGS 0x19
1419#define MBX_RESTART 0x1A
1420#define MBX_UPDATE_CFG 0x1B
1421#define MBX_DOWN_LOAD 0x1C
1422#define MBX_DEL_LD_ENTRY 0x1D
1423#define MBX_RUN_PROGRAM 0x1E
1424#define MBX_SET_MASK 0x20
James Smart09372822008-01-11 01:52:54 -05001425#define MBX_SET_VARIABLE 0x21
dea31012005-04-17 16:05:31 -05001426#define MBX_UNREG_D_ID 0x23
Jamie Wellnitz41415862006-02-28 19:25:27 -05001427#define MBX_KILL_BOARD 0x24
dea31012005-04-17 16:05:31 -05001428#define MBX_CONFIG_FARP 0x25
Jamie Wellnitz41415862006-02-28 19:25:27 -05001429#define MBX_BEACON 0x2A
James Smart93996272008-08-24 21:50:30 -04001430#define MBX_CONFIG_MSI 0x30
James Smart858c9f62007-06-17 19:56:39 -05001431#define MBX_HEARTBEAT 0x31
James Smarta8adb832007-10-27 13:37:53 -04001432#define MBX_WRITE_VPARMS 0x32
1433#define MBX_ASYNCEVT_ENABLE 0x33
James Smart4fede782010-01-26 23:08:55 -05001434#define MBX_READ_EVENT_LOG_STATUS 0x37
1435#define MBX_READ_EVENT_LOG 0x38
1436#define MBX_WRITE_EVENT_LOG 0x39
dea31012005-04-17 16:05:31 -05001437
James Smart84774a42008-08-24 21:50:06 -04001438#define MBX_PORT_CAPABILITIES 0x3B
1439#define MBX_PORT_IOV_CONTROL 0x3C
1440
James Smarted957682007-06-17 19:56:37 -05001441#define MBX_CONFIG_HBQ 0x7C
dea31012005-04-17 16:05:31 -05001442#define MBX_LOAD_AREA 0x81
1443#define MBX_RUN_BIU_DIAG64 0x84
1444#define MBX_CONFIG_PORT 0x88
1445#define MBX_READ_SPARM64 0x8D
1446#define MBX_READ_RPI64 0x8F
1447#define MBX_REG_LOGIN64 0x93
James Smart76a95d72010-11-20 23:11:48 -05001448#define MBX_READ_TOPOLOGY 0x95
James Smart92d7f7b2007-06-17 19:56:38 -05001449#define MBX_REG_VPI 0x96
1450#define MBX_UNREG_VPI 0x97
dea31012005-04-17 16:05:31 -05001451
James Smart09372822008-01-11 01:52:54 -05001452#define MBX_WRITE_WWN 0x98
dea31012005-04-17 16:05:31 -05001453#define MBX_SET_DEBUG 0x99
1454#define MBX_LOAD_EXP_ROM 0x9C
James Smartda0436e2009-05-22 14:51:39 -04001455#define MBX_SLI4_CONFIG 0x9B
1456#define MBX_SLI4_REQ_FTRS 0x9D
1457#define MBX_MAX_CMDS 0x9E
1458#define MBX_RESUME_RPI 0x9E
dea31012005-04-17 16:05:31 -05001459#define MBX_SLI2_CMD_MASK 0x80
James Smartda0436e2009-05-22 14:51:39 -04001460#define MBX_REG_VFI 0x9F
1461#define MBX_REG_FCFI 0xA0
1462#define MBX_UNREG_VFI 0xA1
1463#define MBX_UNREG_FCFI 0xA2
1464#define MBX_INIT_VFI 0xA3
1465#define MBX_INIT_VPI 0xA4
James Smart940eb682012-08-03 12:37:08 -04001466#define MBX_ACCESS_VDATA 0xA5
dea31012005-04-17 16:05:31 -05001467
James Smartdcf2a4e2010-09-29 11:18:53 -04001468#define MBX_AUTH_PORT 0xF8
1469#define MBX_SECURITY_MGMT 0xF9
1470
dea31012005-04-17 16:05:31 -05001471/* IOCB Commands */
1472
1473#define CMD_RCV_SEQUENCE_CX 0x01
1474#define CMD_XMIT_SEQUENCE_CR 0x02
1475#define CMD_XMIT_SEQUENCE_CX 0x03
1476#define CMD_XMIT_BCAST_CN 0x04
1477#define CMD_XMIT_BCAST_CX 0x05
1478#define CMD_QUE_RING_BUF_CN 0x06
1479#define CMD_QUE_XRI_BUF_CX 0x07
1480#define CMD_IOCB_CONTINUE_CN 0x08
1481#define CMD_RET_XRI_BUF_CX 0x09
1482#define CMD_ELS_REQUEST_CR 0x0A
1483#define CMD_ELS_REQUEST_CX 0x0B
1484#define CMD_RCV_ELS_REQ_CX 0x0D
1485#define CMD_ABORT_XRI_CN 0x0E
1486#define CMD_ABORT_XRI_CX 0x0F
1487#define CMD_CLOSE_XRI_CN 0x10
1488#define CMD_CLOSE_XRI_CX 0x11
1489#define CMD_CREATE_XRI_CR 0x12
1490#define CMD_CREATE_XRI_CX 0x13
1491#define CMD_GET_RPI_CN 0x14
1492#define CMD_XMIT_ELS_RSP_CX 0x15
1493#define CMD_GET_RPI_CR 0x16
1494#define CMD_XRI_ABORTED_CX 0x17
1495#define CMD_FCP_IWRITE_CR 0x18
1496#define CMD_FCP_IWRITE_CX 0x19
1497#define CMD_FCP_IREAD_CR 0x1A
1498#define CMD_FCP_IREAD_CX 0x1B
1499#define CMD_FCP_ICMND_CR 0x1C
1500#define CMD_FCP_ICMND_CX 0x1D
James Smartf5603512006-12-02 13:35:43 -05001501#define CMD_FCP_TSEND_CX 0x1F
1502#define CMD_FCP_TRECEIVE_CX 0x21
1503#define CMD_FCP_TRSP_CX 0x23
1504#define CMD_FCP_AUTO_TRSP_CX 0x29
dea31012005-04-17 16:05:31 -05001505
1506#define CMD_ADAPTER_MSG 0x20
1507#define CMD_ADAPTER_DUMP 0x22
1508
1509/* SLI_2 IOCB Command Set */
1510
James Smart57127f12007-10-27 13:37:05 -04001511#define CMD_ASYNC_STATUS 0x7C
dea31012005-04-17 16:05:31 -05001512#define CMD_RCV_SEQUENCE64_CX 0x81
1513#define CMD_XMIT_SEQUENCE64_CR 0x82
1514#define CMD_XMIT_SEQUENCE64_CX 0x83
1515#define CMD_XMIT_BCAST64_CN 0x84
1516#define CMD_XMIT_BCAST64_CX 0x85
1517#define CMD_QUE_RING_BUF64_CN 0x86
1518#define CMD_QUE_XRI_BUF64_CX 0x87
1519#define CMD_IOCB_CONTINUE64_CN 0x88
1520#define CMD_RET_XRI_BUF64_CX 0x89
1521#define CMD_ELS_REQUEST64_CR 0x8A
1522#define CMD_ELS_REQUEST64_CX 0x8B
1523#define CMD_ABORT_MXRI64_CN 0x8C
1524#define CMD_RCV_ELS_REQ64_CX 0x8D
1525#define CMD_XMIT_ELS_RSP64_CX 0x95
James Smart6669f9b2009-10-02 15:16:45 -04001526#define CMD_XMIT_BLS_RSP64_CX 0x97
dea31012005-04-17 16:05:31 -05001527#define CMD_FCP_IWRITE64_CR 0x98
1528#define CMD_FCP_IWRITE64_CX 0x99
1529#define CMD_FCP_IREAD64_CR 0x9A
1530#define CMD_FCP_IREAD64_CX 0x9B
1531#define CMD_FCP_ICMND64_CR 0x9C
1532#define CMD_FCP_ICMND64_CX 0x9D
James Smartf5603512006-12-02 13:35:43 -05001533#define CMD_FCP_TSEND64_CX 0x9F
1534#define CMD_FCP_TRECEIVE64_CX 0xA1
1535#define CMD_FCP_TRSP64_CX 0xA3
dea31012005-04-17 16:05:31 -05001536
James Smart76bb24e2007-10-27 13:38:00 -04001537#define CMD_QUE_XRI64_CX 0xB3
James Smarted957682007-06-17 19:56:37 -05001538#define CMD_IOCB_RCV_SEQ64_CX 0xB5
1539#define CMD_IOCB_RCV_ELS64_CX 0xB7
James Smart3163f722008-02-08 18:50:25 -05001540#define CMD_IOCB_RET_XRI64_CX 0xB9
James Smarted957682007-06-17 19:56:37 -05001541#define CMD_IOCB_RCV_CONT64_CX 0xBB
1542
dea31012005-04-17 16:05:31 -05001543#define CMD_GEN_REQUEST64_CR 0xC2
1544#define CMD_GEN_REQUEST64_CX 0xC3
1545
James Smart3163f722008-02-08 18:50:25 -05001546/* Unhandled SLI-3 Commands */
1547#define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
1548#define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
1549#define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
1550#define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
1551#define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
1552#define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
1553#define CMD_IOCB_RET_HBQE64_CN 0xCA
1554#define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
1555#define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
1556#define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
1557#define CMD_IOCB_LOGENTRY_CN 0x94
1558#define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
1559
James Smart341af102010-01-26 23:07:37 -05001560/* Data Security SLI Commands */
1561#define DSSCMD_IWRITE64_CR 0xF8
1562#define DSSCMD_IWRITE64_CX 0xF9
1563#define DSSCMD_IREAD64_CR 0xFA
1564#define DSSCMD_IREAD64_CX 0xFB
James Smartda0436e2009-05-22 14:51:39 -04001565
James Smart341af102010-01-26 23:07:37 -05001566#define CMD_MAX_IOCB_CMD 0xFB
dea31012005-04-17 16:05:31 -05001567#define CMD_IOCB_MASK 0xff
1568
1569#define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1570 iocb */
1571#define LPFC_MAX_ADPTMSG 32 /* max msg data */
1572/*
1573 * Define Status
1574 */
1575#define MBX_SUCCESS 0
1576#define MBXERR_NUM_RINGS 1
1577#define MBXERR_NUM_IOCBS 2
1578#define MBXERR_IOCBS_EXCEEDED 3
1579#define MBXERR_BAD_RING_NUMBER 4
1580#define MBXERR_MASK_ENTRIES_RANGE 5
1581#define MBXERR_MASKS_EXCEEDED 6
1582#define MBXERR_BAD_PROFILE 7
1583#define MBXERR_BAD_DEF_CLASS 8
1584#define MBXERR_BAD_MAX_RESPONDER 9
1585#define MBXERR_BAD_MAX_ORIGINATOR 10
1586#define MBXERR_RPI_REGISTERED 11
1587#define MBXERR_RPI_FULL 12
1588#define MBXERR_NO_RESOURCES 13
1589#define MBXERR_BAD_RCV_LENGTH 14
1590#define MBXERR_DMA_ERROR 15
1591#define MBXERR_ERROR 16
James Smartda0436e2009-05-22 14:51:39 -04001592#define MBXERR_LINK_DOWN 0x33
James Smartdcf2a4e2010-09-29 11:18:53 -04001593#define MBXERR_SEC_NO_PERMISSION 0xF02
1594#define MBX_NOT_FINISHED 255
dea31012005-04-17 16:05:31 -05001595
1596#define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
1597#define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
1598
James Smart57127f12007-10-27 13:37:05 -04001599#define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
1600
dea31012005-04-17 16:05:31 -05001601/*
1602 * Begin Structure Definitions for Mailbox Commands
1603 */
1604
1605typedef struct {
1606#ifdef __BIG_ENDIAN_BITFIELD
1607 uint8_t tval;
1608 uint8_t tmask;
1609 uint8_t rval;
1610 uint8_t rmask;
1611#else /* __LITTLE_ENDIAN_BITFIELD */
1612 uint8_t rmask;
1613 uint8_t rval;
1614 uint8_t tmask;
1615 uint8_t tval;
1616#endif
1617} RR_REG;
1618
1619struct ulp_bde {
1620 uint32_t bdeAddress;
1621#ifdef __BIG_ENDIAN_BITFIELD
1622 uint32_t bdeReserved:4;
1623 uint32_t bdeAddrHigh:4;
1624 uint32_t bdeSize:24;
1625#else /* __LITTLE_ENDIAN_BITFIELD */
1626 uint32_t bdeSize:24;
1627 uint32_t bdeAddrHigh:4;
1628 uint32_t bdeReserved:4;
1629#endif
1630};
1631
dea31012005-04-17 16:05:31 -05001632typedef struct ULP_BDL { /* SLI-2 */
1633#ifdef __BIG_ENDIAN_BITFIELD
1634 uint32_t bdeFlags:8; /* BDL Flags */
1635 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1636#else /* __LITTLE_ENDIAN_BITFIELD */
1637 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1638 uint32_t bdeFlags:8; /* BDL Flags */
1639#endif
1640
1641 uint32_t addrLow; /* Address 0:31 */
1642 uint32_t addrHigh; /* Address 32:63 */
1643 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
1644} ULP_BDL;
1645
James Smart81301a92008-12-04 22:39:46 -05001646/*
1647 * BlockGuard Definitions
1648 */
1649
1650enum lpfc_protgrp_type {
1651 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */
1652 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */
1653 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */
1654 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */
1655};
1656
1657/* PDE Descriptors */
James Smart6c8eea52010-04-06 14:49:53 -04001658#define LPFC_PDE5_DESCRIPTOR 0x85
1659#define LPFC_PDE6_DESCRIPTOR 0x86
1660#define LPFC_PDE7_DESCRIPTOR 0x87
James Smart81301a92008-12-04 22:39:46 -05001661
James Smart6c8eea52010-04-06 14:49:53 -04001662/* BlockGuard Opcodes */
1663#define BG_OP_IN_NODIF_OUT_CRC 0x0
1664#define BG_OP_IN_CRC_OUT_NODIF 0x1
1665#define BG_OP_IN_NODIF_OUT_CSUM 0x2
1666#define BG_OP_IN_CSUM_OUT_NODIF 0x3
1667#define BG_OP_IN_CRC_OUT_CRC 0x4
1668#define BG_OP_IN_CSUM_OUT_CSUM 0x5
1669#define BG_OP_IN_CRC_OUT_CSUM 0x6
1670#define BG_OP_IN_CSUM_OUT_CRC 0x7
James Smarta6887e22013-04-17 20:18:07 -04001671#define BG_OP_RAW_MODE 0x8
James Smart6c8eea52010-04-06 14:49:53 -04001672
1673struct lpfc_pde5 {
1674 uint32_t word0;
1675#define pde5_type_SHIFT 24
1676#define pde5_type_MASK 0x000000ff
1677#define pde5_type_WORD word0
1678#define pde5_rsvd0_SHIFT 0
1679#define pde5_rsvd0_MASK 0x00ffffff
1680#define pde5_rsvd0_WORD word0
1681 uint32_t reftag; /* Reference Tag Value */
1682 uint32_t reftagtr; /* Reference Tag Translation Value */
James Smart81301a92008-12-04 22:39:46 -05001683};
1684
James Smart6c8eea52010-04-06 14:49:53 -04001685struct lpfc_pde6 {
1686 uint32_t word0;
1687#define pde6_type_SHIFT 24
1688#define pde6_type_MASK 0x000000ff
1689#define pde6_type_WORD word0
1690#define pde6_rsvd0_SHIFT 0
1691#define pde6_rsvd0_MASK 0x00ffffff
1692#define pde6_rsvd0_WORD word0
1693 uint32_t word1;
1694#define pde6_rsvd1_SHIFT 26
1695#define pde6_rsvd1_MASK 0x0000003f
1696#define pde6_rsvd1_WORD word1
1697#define pde6_na_SHIFT 25
1698#define pde6_na_MASK 0x00000001
1699#define pde6_na_WORD word1
1700#define pde6_rsvd2_SHIFT 16
1701#define pde6_rsvd2_MASK 0x000001FF
1702#define pde6_rsvd2_WORD word1
1703#define pde6_apptagtr_SHIFT 0
1704#define pde6_apptagtr_MASK 0x0000ffff
1705#define pde6_apptagtr_WORD word1
1706 uint32_t word2;
1707#define pde6_optx_SHIFT 28
1708#define pde6_optx_MASK 0x0000000f
1709#define pde6_optx_WORD word2
1710#define pde6_oprx_SHIFT 24
1711#define pde6_oprx_MASK 0x0000000f
1712#define pde6_oprx_WORD word2
1713#define pde6_nr_SHIFT 23
1714#define pde6_nr_MASK 0x00000001
1715#define pde6_nr_WORD word2
1716#define pde6_ce_SHIFT 22
1717#define pde6_ce_MASK 0x00000001
1718#define pde6_ce_WORD word2
1719#define pde6_re_SHIFT 21
1720#define pde6_re_MASK 0x00000001
1721#define pde6_re_WORD word2
1722#define pde6_ae_SHIFT 20
1723#define pde6_ae_MASK 0x00000001
1724#define pde6_ae_WORD word2
1725#define pde6_ai_SHIFT 19
1726#define pde6_ai_MASK 0x00000001
1727#define pde6_ai_WORD word2
1728#define pde6_bs_SHIFT 16
1729#define pde6_bs_MASK 0x00000007
1730#define pde6_bs_WORD word2
1731#define pde6_apptagval_SHIFT 0
1732#define pde6_apptagval_MASK 0x0000ffff
1733#define pde6_apptagval_WORD word2
James Smart81301a92008-12-04 22:39:46 -05001734};
1735
James Smart7f860592011-03-11 16:05:52 -05001736struct lpfc_pde7 {
1737 uint32_t word0;
1738#define pde7_type_SHIFT 24
1739#define pde7_type_MASK 0x000000ff
1740#define pde7_type_WORD word0
1741#define pde7_rsvd0_SHIFT 0
1742#define pde7_rsvd0_MASK 0x00ffffff
1743#define pde7_rsvd0_WORD word0
1744 uint32_t addrHigh;
1745 uint32_t addrLow;
1746};
James Smart81301a92008-12-04 22:39:46 -05001747
dea31012005-04-17 16:05:31 -05001748/* Structure for MB Command LOAD_SM and DOWN_LOAD */
1749
1750typedef struct {
1751#ifdef __BIG_ENDIAN_BITFIELD
1752 uint32_t rsvd2:25;
1753 uint32_t acknowledgment:1;
1754 uint32_t version:1;
1755 uint32_t erase_or_prog:1;
1756 uint32_t update_flash:1;
1757 uint32_t update_ram:1;
1758 uint32_t method:1;
1759 uint32_t load_cmplt:1;
1760#else /* __LITTLE_ENDIAN_BITFIELD */
1761 uint32_t load_cmplt:1;
1762 uint32_t method:1;
1763 uint32_t update_ram:1;
1764 uint32_t update_flash:1;
1765 uint32_t erase_or_prog:1;
1766 uint32_t version:1;
1767 uint32_t acknowledgment:1;
1768 uint32_t rsvd2:25;
1769#endif
1770
1771 uint32_t dl_to_adr_low;
1772 uint32_t dl_to_adr_high;
1773 uint32_t dl_len;
1774 union {
1775 uint32_t dl_from_mbx_offset;
1776 struct ulp_bde dl_from_bde;
1777 struct ulp_bde64 dl_from_bde64;
1778 } un;
1779
1780} LOAD_SM_VAR;
1781
1782/* Structure for MB Command READ_NVPARM (02) */
1783
1784typedef struct {
1785 uint32_t rsvd1[3]; /* Read as all one's */
1786 uint32_t rsvd2; /* Read as all zero's */
1787 uint32_t portname[2]; /* N_PORT name */
1788 uint32_t nodename[2]; /* NODE name */
1789
1790#ifdef __BIG_ENDIAN_BITFIELD
1791 uint32_t pref_DID:24;
1792 uint32_t hardAL_PA:8;
1793#else /* __LITTLE_ENDIAN_BITFIELD */
1794 uint32_t hardAL_PA:8;
1795 uint32_t pref_DID:24;
1796#endif
1797
1798 uint32_t rsvd3[21]; /* Read as all one's */
1799} READ_NV_VAR;
1800
1801/* Structure for MB Command WRITE_NVPARMS (03) */
1802
1803typedef struct {
1804 uint32_t rsvd1[3]; /* Must be all one's */
1805 uint32_t rsvd2; /* Must be all zero's */
1806 uint32_t portname[2]; /* N_PORT name */
1807 uint32_t nodename[2]; /* NODE name */
1808
1809#ifdef __BIG_ENDIAN_BITFIELD
1810 uint32_t pref_DID:24;
1811 uint32_t hardAL_PA:8;
1812#else /* __LITTLE_ENDIAN_BITFIELD */
1813 uint32_t hardAL_PA:8;
1814 uint32_t pref_DID:24;
1815#endif
1816
1817 uint32_t rsvd3[21]; /* Must be all one's */
1818} WRITE_NV_VAR;
1819
1820/* Structure for MB Command RUN_BIU_DIAG (04) */
1821/* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
1822
1823typedef struct {
1824 uint32_t rsvd1;
1825 union {
1826 struct {
1827 struct ulp_bde xmit_bde;
1828 struct ulp_bde rcv_bde;
1829 } s1;
1830 struct {
1831 struct ulp_bde64 xmit_bde64;
1832 struct ulp_bde64 rcv_bde64;
1833 } s2;
1834 } un;
1835} BIU_DIAG_VAR;
1836
James Smartc7495932010-04-06 15:05:28 -04001837/* Structure for MB command READ_EVENT_LOG (0x38) */
1838struct READ_EVENT_LOG_VAR {
1839 uint32_t word1;
1840#define lpfc_event_log_SHIFT 29
1841#define lpfc_event_log_MASK 0x00000001
1842#define lpfc_event_log_WORD word1
1843#define USE_MAILBOX_RESPONSE 1
1844 uint32_t offset;
1845 struct ulp_bde64 rcv_bde64;
1846};
1847
dea31012005-04-17 16:05:31 -05001848/* Structure for MB Command INIT_LINK (05) */
1849
1850typedef struct {
1851#ifdef __BIG_ENDIAN_BITFIELD
1852 uint32_t rsvd1:24;
1853 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1854#else /* __LITTLE_ENDIAN_BITFIELD */
1855 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1856 uint32_t rsvd1:24;
1857#endif
1858
1859#ifdef __BIG_ENDIAN_BITFIELD
1860 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1861 uint8_t rsvd2;
1862 uint16_t link_flags;
1863#else /* __LITTLE_ENDIAN_BITFIELD */
1864 uint16_t link_flags;
1865 uint8_t rsvd2;
1866 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1867#endif
1868
dea31012005-04-17 16:05:31 -05001869#define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
James Smart1b511972011-12-13 13:23:09 -05001870#define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
dea31012005-04-17 16:05:31 -05001871#define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
1872#define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
1873#define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
James Smart92d7f7b2007-06-17 19:56:38 -05001874#define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
dea31012005-04-17 16:05:31 -05001875#define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
1876
1877#define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
1878#define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
James Smart4b0b91d2006-04-15 11:53:00 -04001879#define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
dea31012005-04-17 16:05:31 -05001880
1881 uint32_t link_speed;
James Smart76a95d72010-11-20 23:11:48 -05001882#define LINK_SPEED_AUTO 0x0 /* Auto selection */
1883#define LINK_SPEED_1G 0x1 /* 1 Gigabaud */
1884#define LINK_SPEED_2G 0x2 /* 2 Gigabaud */
1885#define LINK_SPEED_4G 0x4 /* 4 Gigabaud */
1886#define LINK_SPEED_8G 0x8 /* 8 Gigabaud */
1887#define LINK_SPEED_10G 0x10 /* 10 Gigabaud */
1888#define LINK_SPEED_16G 0x11 /* 16 Gigabaud */
dea31012005-04-17 16:05:31 -05001889
1890} INIT_LINK_VAR;
1891
1892/* Structure for MB Command DOWN_LINK (06) */
1893
1894typedef struct {
1895 uint32_t rsvd1;
1896} DOWN_LINK_VAR;
1897
1898/* Structure for MB Command CONFIG_LINK (07) */
1899
1900typedef struct {
1901#ifdef __BIG_ENDIAN_BITFIELD
1902 uint32_t cr:1;
1903 uint32_t ci:1;
1904 uint32_t cr_delay:6;
1905 uint32_t cr_count:8;
1906 uint32_t rsvd1:8;
1907 uint32_t MaxBBC:8;
1908#else /* __LITTLE_ENDIAN_BITFIELD */
1909 uint32_t MaxBBC:8;
1910 uint32_t rsvd1:8;
1911 uint32_t cr_count:8;
1912 uint32_t cr_delay:6;
1913 uint32_t ci:1;
1914 uint32_t cr:1;
1915#endif
1916
1917 uint32_t myId;
1918 uint32_t rsvd2;
1919 uint32_t edtov;
1920 uint32_t arbtov;
1921 uint32_t ratov;
1922 uint32_t rttov;
1923 uint32_t altov;
1924 uint32_t crtov;
1925 uint32_t citov;
1926#ifdef __BIG_ENDIAN_BITFIELD
1927 uint32_t rrq_enable:1;
1928 uint32_t rrq_immed:1;
1929 uint32_t rsvd4:29;
1930 uint32_t ack0_enable:1;
1931#else /* __LITTLE_ENDIAN_BITFIELD */
1932 uint32_t ack0_enable:1;
1933 uint32_t rsvd4:29;
1934 uint32_t rrq_immed:1;
1935 uint32_t rrq_enable:1;
1936#endif
1937} CONFIG_LINK;
1938
1939/* Structure for MB Command PART_SLIM (08)
1940 * will be removed since SLI1 is no longer supported!
1941 */
1942typedef struct {
1943#ifdef __BIG_ENDIAN_BITFIELD
1944 uint16_t offCiocb;
1945 uint16_t numCiocb;
1946 uint16_t offRiocb;
1947 uint16_t numRiocb;
1948#else /* __LITTLE_ENDIAN_BITFIELD */
1949 uint16_t numCiocb;
1950 uint16_t offCiocb;
1951 uint16_t numRiocb;
1952 uint16_t offRiocb;
1953#endif
1954} RING_DEF;
1955
1956typedef struct {
1957#ifdef __BIG_ENDIAN_BITFIELD
1958 uint32_t unused1:24;
1959 uint32_t numRing:8;
1960#else /* __LITTLE_ENDIAN_BITFIELD */
1961 uint32_t numRing:8;
1962 uint32_t unused1:24;
1963#endif
1964
1965 RING_DEF ringdef[4];
1966 uint32_t hbainit;
1967} PART_SLIM_VAR;
1968
1969/* Structure for MB Command CONFIG_RING (09) */
1970
1971typedef struct {
1972#ifdef __BIG_ENDIAN_BITFIELD
1973 uint32_t unused2:6;
1974 uint32_t recvSeq:1;
1975 uint32_t recvNotify:1;
1976 uint32_t numMask:8;
1977 uint32_t profile:8;
1978 uint32_t unused1:4;
1979 uint32_t ring:4;
1980#else /* __LITTLE_ENDIAN_BITFIELD */
1981 uint32_t ring:4;
1982 uint32_t unused1:4;
1983 uint32_t profile:8;
1984 uint32_t numMask:8;
1985 uint32_t recvNotify:1;
1986 uint32_t recvSeq:1;
1987 uint32_t unused2:6;
1988#endif
1989
1990#ifdef __BIG_ENDIAN_BITFIELD
1991 uint16_t maxRespXchg;
1992 uint16_t maxOrigXchg;
1993#else /* __LITTLE_ENDIAN_BITFIELD */
1994 uint16_t maxOrigXchg;
1995 uint16_t maxRespXchg;
1996#endif
1997
1998 RR_REG rrRegs[6];
1999} CONFIG_RING_VAR;
2000
2001/* Structure for MB Command RESET_RING (10) */
2002
2003typedef struct {
2004 uint32_t ring_no;
2005} RESET_RING_VAR;
2006
2007/* Structure for MB Command READ_CONFIG (11) */
2008
2009typedef struct {
2010#ifdef __BIG_ENDIAN_BITFIELD
2011 uint32_t cr:1;
2012 uint32_t ci:1;
2013 uint32_t cr_delay:6;
2014 uint32_t cr_count:8;
2015 uint32_t InitBBC:8;
2016 uint32_t MaxBBC:8;
2017#else /* __LITTLE_ENDIAN_BITFIELD */
2018 uint32_t MaxBBC:8;
2019 uint32_t InitBBC:8;
2020 uint32_t cr_count:8;
2021 uint32_t cr_delay:6;
2022 uint32_t ci:1;
2023 uint32_t cr:1;
2024#endif
2025
2026#ifdef __BIG_ENDIAN_BITFIELD
2027 uint32_t topology:8;
2028 uint32_t myDid:24;
2029#else /* __LITTLE_ENDIAN_BITFIELD */
2030 uint32_t myDid:24;
2031 uint32_t topology:8;
2032#endif
2033
2034 /* Defines for topology (defined previously) */
2035#ifdef __BIG_ENDIAN_BITFIELD
2036 uint32_t AR:1;
2037 uint32_t IR:1;
2038 uint32_t rsvd1:29;
2039 uint32_t ack0:1;
2040#else /* __LITTLE_ENDIAN_BITFIELD */
2041 uint32_t ack0:1;
2042 uint32_t rsvd1:29;
2043 uint32_t IR:1;
2044 uint32_t AR:1;
2045#endif
2046
2047 uint32_t edtov;
2048 uint32_t arbtov;
2049 uint32_t ratov;
2050 uint32_t rttov;
2051 uint32_t altov;
2052 uint32_t lmt;
Jamie Wellnitz74b72a52006-02-28 22:33:04 -05002053#define LMT_RESERVED 0x000 /* Not used */
2054#define LMT_1Gb 0x004
2055#define LMT_2Gb 0x008
2056#define LMT_4Gb 0x040
2057#define LMT_8Gb 0x080
2058#define LMT_10Gb 0x100
James Smart76a95d72010-11-20 23:11:48 -05002059#define LMT_16Gb 0x200
dea31012005-04-17 16:05:31 -05002060 uint32_t rsvd2;
2061 uint32_t rsvd3;
2062 uint32_t max_xri;
2063 uint32_t max_iocb;
2064 uint32_t max_rpi;
2065 uint32_t avail_xri;
2066 uint32_t avail_iocb;
2067 uint32_t avail_rpi;
James Smart858c9f62007-06-17 19:56:39 -05002068 uint32_t max_vpi;
2069 uint32_t rsvd4;
2070 uint32_t rsvd5;
2071 uint32_t avail_vpi;
dea31012005-04-17 16:05:31 -05002072} READ_CONFIG_VAR;
2073
2074/* Structure for MB Command READ_RCONFIG (12) */
2075
2076typedef struct {
2077#ifdef __BIG_ENDIAN_BITFIELD
2078 uint32_t rsvd2:7;
2079 uint32_t recvNotify:1;
2080 uint32_t numMask:8;
2081 uint32_t profile:8;
2082 uint32_t rsvd1:4;
2083 uint32_t ring:4;
2084#else /* __LITTLE_ENDIAN_BITFIELD */
2085 uint32_t ring:4;
2086 uint32_t rsvd1:4;
2087 uint32_t profile:8;
2088 uint32_t numMask:8;
2089 uint32_t recvNotify:1;
2090 uint32_t rsvd2:7;
2091#endif
2092
2093#ifdef __BIG_ENDIAN_BITFIELD
2094 uint16_t maxResp;
2095 uint16_t maxOrig;
2096#else /* __LITTLE_ENDIAN_BITFIELD */
2097 uint16_t maxOrig;
2098 uint16_t maxResp;
2099#endif
2100
2101 RR_REG rrRegs[6];
2102
2103#ifdef __BIG_ENDIAN_BITFIELD
2104 uint16_t cmdRingOffset;
2105 uint16_t cmdEntryCnt;
2106 uint16_t rspRingOffset;
2107 uint16_t rspEntryCnt;
2108 uint16_t nextCmdOffset;
2109 uint16_t rsvd3;
2110 uint16_t nextRspOffset;
2111 uint16_t rsvd4;
2112#else /* __LITTLE_ENDIAN_BITFIELD */
2113 uint16_t cmdEntryCnt;
2114 uint16_t cmdRingOffset;
2115 uint16_t rspEntryCnt;
2116 uint16_t rspRingOffset;
2117 uint16_t rsvd3;
2118 uint16_t nextCmdOffset;
2119 uint16_t rsvd4;
2120 uint16_t nextRspOffset;
2121#endif
2122} READ_RCONF_VAR;
2123
2124/* Structure for MB Command READ_SPARM (13) */
2125/* Structure for MB Command READ_SPARM64 (0x8D) */
2126
2127typedef struct {
2128 uint32_t rsvd1;
2129 uint32_t rsvd2;
2130 union {
2131 struct ulp_bde sp; /* This BDE points to struct serv_parm
2132 structure */
2133 struct ulp_bde64 sp64;
2134 } un;
James Smarted957682007-06-17 19:56:37 -05002135#ifdef __BIG_ENDIAN_BITFIELD
2136 uint16_t rsvd3;
2137 uint16_t vpi;
2138#else /* __LITTLE_ENDIAN_BITFIELD */
2139 uint16_t vpi;
2140 uint16_t rsvd3;
2141#endif
dea31012005-04-17 16:05:31 -05002142} READ_SPARM_VAR;
2143
2144/* Structure for MB Command READ_STATUS (14) */
2145
2146typedef struct {
2147#ifdef __BIG_ENDIAN_BITFIELD
2148 uint32_t rsvd1:31;
2149 uint32_t clrCounters:1;
2150 uint16_t activeXriCnt;
2151 uint16_t activeRpiCnt;
2152#else /* __LITTLE_ENDIAN_BITFIELD */
2153 uint32_t clrCounters:1;
2154 uint32_t rsvd1:31;
2155 uint16_t activeRpiCnt;
2156 uint16_t activeXriCnt;
2157#endif
2158
2159 uint32_t xmitByteCnt;
2160 uint32_t rcvByteCnt;
2161 uint32_t xmitFrameCnt;
2162 uint32_t rcvFrameCnt;
2163 uint32_t xmitSeqCnt;
2164 uint32_t rcvSeqCnt;
2165 uint32_t totalOrigExchanges;
2166 uint32_t totalRespExchanges;
2167 uint32_t rcvPbsyCnt;
2168 uint32_t rcvFbsyCnt;
2169} READ_STATUS_VAR;
2170
2171/* Structure for MB Command READ_RPI (15) */
2172/* Structure for MB Command READ_RPI64 (0x8F) */
2173
2174typedef struct {
2175#ifdef __BIG_ENDIAN_BITFIELD
2176 uint16_t nextRpi;
2177 uint16_t reqRpi;
2178 uint32_t rsvd2:8;
2179 uint32_t DID:24;
2180#else /* __LITTLE_ENDIAN_BITFIELD */
2181 uint16_t reqRpi;
2182 uint16_t nextRpi;
2183 uint32_t DID:24;
2184 uint32_t rsvd2:8;
2185#endif
2186
2187 union {
2188 struct ulp_bde sp;
2189 struct ulp_bde64 sp64;
2190 } un;
2191
2192} READ_RPI_VAR;
2193
2194/* Structure for MB Command READ_XRI (16) */
2195
2196typedef struct {
2197#ifdef __BIG_ENDIAN_BITFIELD
2198 uint16_t nextXri;
2199 uint16_t reqXri;
2200 uint16_t rsvd1;
2201 uint16_t rpi;
2202 uint32_t rsvd2:8;
2203 uint32_t DID:24;
2204 uint32_t rsvd3:8;
2205 uint32_t SID:24;
2206 uint32_t rsvd4;
2207 uint8_t seqId;
2208 uint8_t rsvd5;
2209 uint16_t seqCount;
2210 uint16_t oxId;
2211 uint16_t rxId;
2212 uint32_t rsvd6:30;
2213 uint32_t si:1;
2214 uint32_t exchOrig:1;
2215#else /* __LITTLE_ENDIAN_BITFIELD */
2216 uint16_t reqXri;
2217 uint16_t nextXri;
2218 uint16_t rpi;
2219 uint16_t rsvd1;
2220 uint32_t DID:24;
2221 uint32_t rsvd2:8;
2222 uint32_t SID:24;
2223 uint32_t rsvd3:8;
2224 uint32_t rsvd4;
2225 uint16_t seqCount;
2226 uint8_t rsvd5;
2227 uint8_t seqId;
2228 uint16_t rxId;
2229 uint16_t oxId;
2230 uint32_t exchOrig:1;
2231 uint32_t si:1;
2232 uint32_t rsvd6:30;
2233#endif
2234} READ_XRI_VAR;
2235
2236/* Structure for MB Command READ_REV (17) */
2237
2238typedef struct {
2239#ifdef __BIG_ENDIAN_BITFIELD
2240 uint32_t cv:1;
2241 uint32_t rr:1;
James Smarted957682007-06-17 19:56:37 -05002242 uint32_t rsvd2:2;
2243 uint32_t v3req:1;
2244 uint32_t v3rsp:1;
2245 uint32_t rsvd1:25;
dea31012005-04-17 16:05:31 -05002246 uint32_t rv:1;
2247#else /* __LITTLE_ENDIAN_BITFIELD */
2248 uint32_t rv:1;
James Smarted957682007-06-17 19:56:37 -05002249 uint32_t rsvd1:25;
2250 uint32_t v3rsp:1;
2251 uint32_t v3req:1;
2252 uint32_t rsvd2:2;
dea31012005-04-17 16:05:31 -05002253 uint32_t rr:1;
2254 uint32_t cv:1;
2255#endif
2256
2257 uint32_t biuRev;
2258 uint32_t smRev;
2259 union {
2260 uint32_t smFwRev;
2261 struct {
2262#ifdef __BIG_ENDIAN_BITFIELD
2263 uint8_t ProgType;
2264 uint8_t ProgId;
2265 uint16_t ProgVer:4;
2266 uint16_t ProgRev:4;
2267 uint16_t ProgFixLvl:2;
2268 uint16_t ProgDistType:2;
2269 uint16_t DistCnt:4;
2270#else /* __LITTLE_ENDIAN_BITFIELD */
2271 uint16_t DistCnt:4;
2272 uint16_t ProgDistType:2;
2273 uint16_t ProgFixLvl:2;
2274 uint16_t ProgRev:4;
2275 uint16_t ProgVer:4;
2276 uint8_t ProgId;
2277 uint8_t ProgType;
2278#endif
2279
2280 } b;
2281 } un;
2282 uint32_t endecRev;
2283#ifdef __BIG_ENDIAN_BITFIELD
2284 uint8_t feaLevelHigh;
2285 uint8_t feaLevelLow;
2286 uint8_t fcphHigh;
2287 uint8_t fcphLow;
2288#else /* __LITTLE_ENDIAN_BITFIELD */
2289 uint8_t fcphLow;
2290 uint8_t fcphHigh;
2291 uint8_t feaLevelLow;
2292 uint8_t feaLevelHigh;
2293#endif
2294
2295 uint32_t postKernRev;
2296 uint32_t opFwRev;
2297 uint8_t opFwName[16];
2298 uint32_t sli1FwRev;
2299 uint8_t sli1FwName[16];
2300 uint32_t sli2FwRev;
2301 uint8_t sli2FwName[16];
James Smarted957682007-06-17 19:56:37 -05002302 uint32_t sli3Feat;
2303 uint32_t RandomData[6];
dea31012005-04-17 16:05:31 -05002304} READ_REV_VAR;
2305
2306/* Structure for MB Command READ_LINK_STAT (18) */
2307
2308typedef struct {
2309 uint32_t rsvd1;
2310 uint32_t linkFailureCnt;
2311 uint32_t lossSyncCnt;
2312
2313 uint32_t lossSignalCnt;
2314 uint32_t primSeqErrCnt;
2315 uint32_t invalidXmitWord;
2316 uint32_t crcCnt;
2317 uint32_t primSeqTimeout;
2318 uint32_t elasticOverrun;
2319 uint32_t arbTimeout;
2320} READ_LNK_VAR;
2321
2322/* Structure for MB Command REG_LOGIN (19) */
2323/* Structure for MB Command REG_LOGIN64 (0x93) */
2324
2325typedef struct {
2326#ifdef __BIG_ENDIAN_BITFIELD
2327 uint16_t rsvd1;
2328 uint16_t rpi;
2329 uint32_t rsvd2:8;
2330 uint32_t did:24;
2331#else /* __LITTLE_ENDIAN_BITFIELD */
2332 uint16_t rpi;
2333 uint16_t rsvd1;
2334 uint32_t did:24;
2335 uint32_t rsvd2:8;
2336#endif
2337
2338 union {
2339 struct ulp_bde sp;
2340 struct ulp_bde64 sp64;
2341 } un;
2342
James Smarted957682007-06-17 19:56:37 -05002343#ifdef __BIG_ENDIAN_BITFIELD
2344 uint16_t rsvd6;
2345 uint16_t vpi;
2346#else /* __LITTLE_ENDIAN_BITFIELD */
2347 uint16_t vpi;
2348 uint16_t rsvd6;
2349#endif
2350
dea31012005-04-17 16:05:31 -05002351} REG_LOGIN_VAR;
2352
2353/* Word 30 contents for REG_LOGIN */
2354typedef union {
2355 struct {
2356#ifdef __BIG_ENDIAN_BITFIELD
2357 uint16_t rsvd1:12;
2358 uint16_t wd30_class:4;
2359 uint16_t xri;
2360#else /* __LITTLE_ENDIAN_BITFIELD */
2361 uint16_t xri;
2362 uint16_t wd30_class:4;
2363 uint16_t rsvd1:12;
2364#endif
2365 } f;
2366 uint32_t word;
2367} REG_WD30;
2368
2369/* Structure for MB Command UNREG_LOGIN (20) */
2370
2371typedef struct {
2372#ifdef __BIG_ENDIAN_BITFIELD
2373 uint16_t rsvd1;
2374 uint16_t rpi;
James Smarted957682007-06-17 19:56:37 -05002375 uint32_t rsvd2;
2376 uint32_t rsvd3;
2377 uint32_t rsvd4;
2378 uint32_t rsvd5;
2379 uint16_t rsvd6;
2380 uint16_t vpi;
dea31012005-04-17 16:05:31 -05002381#else /* __LITTLE_ENDIAN_BITFIELD */
2382 uint16_t rpi;
2383 uint16_t rsvd1;
James Smarted957682007-06-17 19:56:37 -05002384 uint32_t rsvd2;
2385 uint32_t rsvd3;
2386 uint32_t rsvd4;
2387 uint32_t rsvd5;
2388 uint16_t vpi;
2389 uint16_t rsvd6;
dea31012005-04-17 16:05:31 -05002390#endif
2391} UNREG_LOGIN_VAR;
2392
James Smart92d7f7b2007-06-17 19:56:38 -05002393/* Structure for MB Command REG_VPI (0x96) */
2394typedef struct {
2395#ifdef __BIG_ENDIAN_BITFIELD
2396 uint32_t rsvd1;
James Smart38b92ef2010-08-04 16:11:39 -04002397 uint32_t rsvd2:7;
2398 uint32_t upd:1;
James Smart92d7f7b2007-06-17 19:56:38 -05002399 uint32_t sid:24;
James Smartc8685952009-11-18 15:39:16 -05002400 uint32_t wwn[2];
James Smart92d7f7b2007-06-17 19:56:38 -05002401 uint32_t rsvd5;
James Smartda0436e2009-05-22 14:51:39 -04002402 uint16_t vfi;
James Smart92d7f7b2007-06-17 19:56:38 -05002403 uint16_t vpi;
2404#else /* __LITTLE_ENDIAN */
2405 uint32_t rsvd1;
2406 uint32_t sid:24;
James Smart38b92ef2010-08-04 16:11:39 -04002407 uint32_t upd:1;
2408 uint32_t rsvd2:7;
James Smartc8685952009-11-18 15:39:16 -05002409 uint32_t wwn[2];
James Smart92d7f7b2007-06-17 19:56:38 -05002410 uint32_t rsvd5;
2411 uint16_t vpi;
James Smartda0436e2009-05-22 14:51:39 -04002412 uint16_t vfi;
James Smart92d7f7b2007-06-17 19:56:38 -05002413#endif
2414} REG_VPI_VAR;
2415
2416/* Structure for MB Command UNREG_VPI (0x97) */
2417typedef struct {
2418 uint32_t rsvd1;
James Smart6669f9b2009-10-02 15:16:45 -04002419#ifdef __BIG_ENDIAN_BITFIELD
2420 uint16_t rsvd2;
2421 uint16_t sli4_vpi;
2422#else /* __LITTLE_ENDIAN */
2423 uint16_t sli4_vpi;
2424 uint16_t rsvd2;
2425#endif
James Smart92d7f7b2007-06-17 19:56:38 -05002426 uint32_t rsvd3;
2427 uint32_t rsvd4;
2428 uint32_t rsvd5;
2429#ifdef __BIG_ENDIAN_BITFIELD
2430 uint16_t rsvd6;
2431 uint16_t vpi;
2432#else /* __LITTLE_ENDIAN */
2433 uint16_t vpi;
2434 uint16_t rsvd6;
2435#endif
2436} UNREG_VPI_VAR;
2437
dea31012005-04-17 16:05:31 -05002438/* Structure for MB Command UNREG_D_ID (0x23) */
2439
2440typedef struct {
2441 uint32_t did;
James Smarted957682007-06-17 19:56:37 -05002442 uint32_t rsvd2;
2443 uint32_t rsvd3;
2444 uint32_t rsvd4;
2445 uint32_t rsvd5;
2446#ifdef __BIG_ENDIAN_BITFIELD
2447 uint16_t rsvd6;
2448 uint16_t vpi;
2449#else
2450 uint16_t vpi;
2451 uint16_t rsvd6;
2452#endif
dea31012005-04-17 16:05:31 -05002453} UNREG_D_ID_VAR;
2454
James Smart76a95d72010-11-20 23:11:48 -05002455/* Structure for MB Command READ_TOPOLOGY (0x95) */
2456struct lpfc_mbx_read_top {
dea31012005-04-17 16:05:31 -05002457 uint32_t eventTag; /* Event tag */
James Smart76a95d72010-11-20 23:11:48 -05002458 uint32_t word2;
2459#define lpfc_mbx_read_top_fa_SHIFT 12
2460#define lpfc_mbx_read_top_fa_MASK 0x00000001
2461#define lpfc_mbx_read_top_fa_WORD word2
2462#define lpfc_mbx_read_top_mm_SHIFT 11
2463#define lpfc_mbx_read_top_mm_MASK 0x00000001
2464#define lpfc_mbx_read_top_mm_WORD word2
2465#define lpfc_mbx_read_top_pb_SHIFT 9
2466#define lpfc_mbx_read_top_pb_MASK 0X00000001
2467#define lpfc_mbx_read_top_pb_WORD word2
2468#define lpfc_mbx_read_top_il_SHIFT 8
2469#define lpfc_mbx_read_top_il_MASK 0x00000001
2470#define lpfc_mbx_read_top_il_WORD word2
2471#define lpfc_mbx_read_top_att_type_SHIFT 0
2472#define lpfc_mbx_read_top_att_type_MASK 0x000000FF
2473#define lpfc_mbx_read_top_att_type_WORD word2
2474#define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */
2475#define LPFC_ATT_LINK_UP 0x01 /* Link is up */
2476#define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */
2477 uint32_t word3;
2478#define lpfc_mbx_read_top_alpa_granted_SHIFT 24
2479#define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF
2480#define lpfc_mbx_read_top_alpa_granted_WORD word3
2481#define lpfc_mbx_read_top_lip_alps_SHIFT 16
2482#define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF
2483#define lpfc_mbx_read_top_lip_alps_WORD word3
2484#define lpfc_mbx_read_top_lip_type_SHIFT 8
2485#define lpfc_mbx_read_top_lip_type_MASK 0x000000FF
2486#define lpfc_mbx_read_top_lip_type_WORD word3
2487#define lpfc_mbx_read_top_topology_SHIFT 0
2488#define lpfc_mbx_read_top_topology_MASK 0x000000FF
2489#define lpfc_mbx_read_top_topology_WORD word3
2490#define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
2491#define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
2492#define LPFC_TOPOLOGY_MM 0x05 /* maint mode zephtr to menlo */
2493 /* store the LILP AL_PA position map into */
2494 struct ulp_bde64 lilpBde64;
2495#define LPFC_ALPA_MAP_SIZE 128
2496 uint32_t word7;
2497#define lpfc_mbx_read_top_ld_lu_SHIFT 31
2498#define lpfc_mbx_read_top_ld_lu_MASK 0x00000001
2499#define lpfc_mbx_read_top_ld_lu_WORD word7
2500#define lpfc_mbx_read_top_ld_tf_SHIFT 30
2501#define lpfc_mbx_read_top_ld_tf_MASK 0x00000001
2502#define lpfc_mbx_read_top_ld_tf_WORD word7
2503#define lpfc_mbx_read_top_ld_link_spd_SHIFT 8
2504#define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF
2505#define lpfc_mbx_read_top_ld_link_spd_WORD word7
2506#define lpfc_mbx_read_top_ld_nl_port_SHIFT 4
2507#define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F
2508#define lpfc_mbx_read_top_ld_nl_port_WORD word7
2509#define lpfc_mbx_read_top_ld_tx_SHIFT 2
2510#define lpfc_mbx_read_top_ld_tx_MASK 0x00000003
2511#define lpfc_mbx_read_top_ld_tx_WORD word7
2512#define lpfc_mbx_read_top_ld_rx_SHIFT 0
2513#define lpfc_mbx_read_top_ld_rx_MASK 0x00000003
2514#define lpfc_mbx_read_top_ld_rx_WORD word7
2515 uint32_t word8;
2516#define lpfc_mbx_read_top_lu_SHIFT 31
2517#define lpfc_mbx_read_top_lu_MASK 0x00000001
2518#define lpfc_mbx_read_top_lu_WORD word8
2519#define lpfc_mbx_read_top_tf_SHIFT 30
2520#define lpfc_mbx_read_top_tf_MASK 0x00000001
2521#define lpfc_mbx_read_top_tf_WORD word8
2522#define lpfc_mbx_read_top_link_spd_SHIFT 8
2523#define lpfc_mbx_read_top_link_spd_MASK 0x000000FF
2524#define lpfc_mbx_read_top_link_spd_WORD word8
2525#define lpfc_mbx_read_top_nl_port_SHIFT 4
2526#define lpfc_mbx_read_top_nl_port_MASK 0x0000000F
2527#define lpfc_mbx_read_top_nl_port_WORD word8
2528#define lpfc_mbx_read_top_tx_SHIFT 2
2529#define lpfc_mbx_read_top_tx_MASK 0x00000003
2530#define lpfc_mbx_read_top_tx_WORD word8
2531#define lpfc_mbx_read_top_rx_SHIFT 0
2532#define lpfc_mbx_read_top_rx_MASK 0x00000003
2533#define lpfc_mbx_read_top_rx_WORD word8
2534#define LPFC_LINK_SPEED_UNKNOWN 0x0
2535#define LPFC_LINK_SPEED_1GHZ 0x04
2536#define LPFC_LINK_SPEED_2GHZ 0x08
2537#define LPFC_LINK_SPEED_4GHZ 0x10
2538#define LPFC_LINK_SPEED_8GHZ 0x20
2539#define LPFC_LINK_SPEED_10GHZ 0x40
2540#define LPFC_LINK_SPEED_16GHZ 0x80
2541};
dea31012005-04-17 16:05:31 -05002542
2543/* Structure for MB Command CLEAR_LA (22) */
2544
2545typedef struct {
2546 uint32_t eventTag; /* Event tag */
2547 uint32_t rsvd1;
2548} CLEAR_LA_VAR;
2549
2550/* Structure for MB Command DUMP */
2551
2552typedef struct {
2553#ifdef __BIG_ENDIAN_BITFIELD
2554 uint32_t rsvd:25;
2555 uint32_t ra:1;
2556 uint32_t co:1;
2557 uint32_t cv:1;
2558 uint32_t type:4;
2559 uint32_t entry_index:16;
2560 uint32_t region_id:16;
2561#else /* __LITTLE_ENDIAN_BITFIELD */
2562 uint32_t type:4;
2563 uint32_t cv:1;
2564 uint32_t co:1;
2565 uint32_t ra:1;
2566 uint32_t rsvd:25;
2567 uint32_t region_id:16;
2568 uint32_t entry_index:16;
2569#endif
2570
James Smartda0436e2009-05-22 14:51:39 -04002571 uint32_t sli4_length;
dea31012005-04-17 16:05:31 -05002572 uint32_t word_cnt;
2573 uint32_t resp_offset;
2574} DUMP_VAR;
2575
2576#define DMP_MEM_REG 0x1
2577#define DMP_NV_PARAMS 0x2
James Smart3ef6d242012-01-18 16:23:48 -05002578#define DMP_LMSD 0x3 /* Link Module Serial Data */
2579#define DMP_WELL_KNOWN 0x4
dea31012005-04-17 16:05:31 -05002580
2581#define DMP_REGION_VPD 0xe
2582#define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
2583#define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
2584#define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
2585
James Smartda0436e2009-05-22 14:51:39 -04002586#define DMP_REGION_VPORT 0x16 /* VPort info region */
2587#define DMP_VPORT_REGION_SIZE 0x200
2588#define DMP_MBOX_OFFSET_WORD 0x5
2589
James Smart6c8eea52010-04-06 14:49:53 -04002590#define DMP_REGION_23 0x17 /* fcoe param and port state region */
2591#define DMP_RGN23_SIZE 0x400
James Smartda0436e2009-05-22 14:51:39 -04002592
James Smart97207482008-12-04 22:39:19 -05002593#define WAKE_UP_PARMS_REGION_ID 4
2594#define WAKE_UP_PARMS_WORD_SIZE 15
2595
James Smartda0436e2009-05-22 14:51:39 -04002596struct vport_rec {
2597 uint8_t wwpn[8];
2598 uint8_t wwnn[8];
2599};
2600
2601#define VPORT_INFO_SIG 0x32324752
2602#define VPORT_INFO_REV_MASK 0xff
2603#define VPORT_INFO_REV 0x1
2604#define MAX_STATIC_VPORT_COUNT 16
2605struct static_vport_info {
James Smart6c8eea52010-04-06 14:49:53 -04002606 uint32_t signature;
James Smartda0436e2009-05-22 14:51:39 -04002607 uint32_t rev;
James Smart6c8eea52010-04-06 14:49:53 -04002608 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT];
James Smartda0436e2009-05-22 14:51:39 -04002609 uint32_t resvd[66];
2610};
2611
James Smart97207482008-12-04 22:39:19 -05002612/* Option rom version structure */
2613struct prog_id {
2614#ifdef __BIG_ENDIAN_BITFIELD
2615 uint8_t type;
2616 uint8_t id;
2617 uint32_t ver:4; /* Major Version */
2618 uint32_t rev:4; /* Revision */
2619 uint32_t lev:2; /* Level */
2620 uint32_t dist:2; /* Dist Type */
2621 uint32_t num:4; /* number after dist type */
2622#else /* __LITTLE_ENDIAN_BITFIELD */
2623 uint32_t num:4; /* number after dist type */
2624 uint32_t dist:2; /* Dist Type */
2625 uint32_t lev:2; /* Level */
2626 uint32_t rev:4; /* Revision */
2627 uint32_t ver:4; /* Major Version */
2628 uint8_t id;
2629 uint8_t type;
2630#endif
2631};
2632
James Smartd7c255b2008-08-24 21:50:00 -04002633/* Structure for MB Command UPDATE_CFG (0x1B) */
2634
2635struct update_cfg_var {
2636#ifdef __BIG_ENDIAN_BITFIELD
2637 uint32_t rsvd2:16;
2638 uint32_t type:8;
2639 uint32_t rsvd:1;
2640 uint32_t ra:1;
2641 uint32_t co:1;
2642 uint32_t cv:1;
2643 uint32_t req:4;
2644 uint32_t entry_length:16;
2645 uint32_t region_id:16;
2646#else /* __LITTLE_ENDIAN_BITFIELD */
2647 uint32_t req:4;
2648 uint32_t cv:1;
2649 uint32_t co:1;
2650 uint32_t ra:1;
2651 uint32_t rsvd:1;
2652 uint32_t type:8;
2653 uint32_t rsvd2:16;
2654 uint32_t region_id:16;
2655 uint32_t entry_length:16;
2656#endif
2657
2658 uint32_t resp_info;
2659 uint32_t byte_cnt;
2660 uint32_t data_offset;
2661};
2662
James Smarted957682007-06-17 19:56:37 -05002663struct hbq_mask {
2664#ifdef __BIG_ENDIAN_BITFIELD
2665 uint8_t tmatch;
2666 uint8_t tmask;
2667 uint8_t rctlmatch;
2668 uint8_t rctlmask;
2669#else /* __LITTLE_ENDIAN */
2670 uint8_t rctlmask;
2671 uint8_t rctlmatch;
2672 uint8_t tmask;
2673 uint8_t tmatch;
2674#endif
2675};
2676
2677
2678/* Structure for MB Command CONFIG_HBQ (7c) */
2679
2680struct config_hbq_var {
2681#ifdef __BIG_ENDIAN_BITFIELD
2682 uint32_t rsvd1 :7;
2683 uint32_t recvNotify :1; /* Receive Notification */
2684 uint32_t numMask :8; /* # Mask Entries */
2685 uint32_t profile :8; /* Selection Profile */
2686 uint32_t rsvd2 :8;
2687#else /* __LITTLE_ENDIAN */
2688 uint32_t rsvd2 :8;
2689 uint32_t profile :8; /* Selection Profile */
2690 uint32_t numMask :8; /* # Mask Entries */
2691 uint32_t recvNotify :1; /* Receive Notification */
2692 uint32_t rsvd1 :7;
2693#endif
2694
2695#ifdef __BIG_ENDIAN_BITFIELD
2696 uint32_t hbqId :16;
2697 uint32_t rsvd3 :12;
2698 uint32_t ringMask :4;
2699#else /* __LITTLE_ENDIAN */
2700 uint32_t ringMask :4;
2701 uint32_t rsvd3 :12;
2702 uint32_t hbqId :16;
2703#endif
2704
2705#ifdef __BIG_ENDIAN_BITFIELD
2706 uint32_t entry_count :16;
2707 uint32_t rsvd4 :8;
2708 uint32_t headerLen :8;
2709#else /* __LITTLE_ENDIAN */
2710 uint32_t headerLen :8;
2711 uint32_t rsvd4 :8;
2712 uint32_t entry_count :16;
2713#endif
2714
2715 uint32_t hbqaddrLow;
2716 uint32_t hbqaddrHigh;
2717
2718#ifdef __BIG_ENDIAN_BITFIELD
2719 uint32_t rsvd5 :31;
2720 uint32_t logEntry :1;
2721#else /* __LITTLE_ENDIAN */
2722 uint32_t logEntry :1;
2723 uint32_t rsvd5 :31;
2724#endif
2725
2726 uint32_t rsvd6; /* w7 */
2727 uint32_t rsvd7; /* w8 */
2728 uint32_t rsvd8; /* w9 */
2729
2730 struct hbq_mask hbqMasks[6];
2731
2732
2733 union {
2734 uint32_t allprofiles[12];
2735
2736 struct {
2737 #ifdef __BIG_ENDIAN_BITFIELD
2738 uint32_t seqlenoff :16;
2739 uint32_t maxlen :16;
2740 #else /* __LITTLE_ENDIAN */
2741 uint32_t maxlen :16;
2742 uint32_t seqlenoff :16;
2743 #endif
2744 #ifdef __BIG_ENDIAN_BITFIELD
2745 uint32_t rsvd1 :28;
2746 uint32_t seqlenbcnt :4;
2747 #else /* __LITTLE_ENDIAN */
2748 uint32_t seqlenbcnt :4;
2749 uint32_t rsvd1 :28;
2750 #endif
2751 uint32_t rsvd[10];
2752 } profile2;
2753
2754 struct {
2755 #ifdef __BIG_ENDIAN_BITFIELD
2756 uint32_t seqlenoff :16;
2757 uint32_t maxlen :16;
2758 #else /* __LITTLE_ENDIAN */
2759 uint32_t maxlen :16;
2760 uint32_t seqlenoff :16;
2761 #endif
2762 #ifdef __BIG_ENDIAN_BITFIELD
2763 uint32_t cmdcodeoff :28;
2764 uint32_t rsvd1 :12;
2765 uint32_t seqlenbcnt :4;
2766 #else /* __LITTLE_ENDIAN */
2767 uint32_t seqlenbcnt :4;
2768 uint32_t rsvd1 :12;
2769 uint32_t cmdcodeoff :28;
2770 #endif
2771 uint32_t cmdmatch[8];
2772
2773 uint32_t rsvd[2];
2774 } profile3;
2775
2776 struct {
2777 #ifdef __BIG_ENDIAN_BITFIELD
2778 uint32_t seqlenoff :16;
2779 uint32_t maxlen :16;
2780 #else /* __LITTLE_ENDIAN */
2781 uint32_t maxlen :16;
2782 uint32_t seqlenoff :16;
2783 #endif
2784 #ifdef __BIG_ENDIAN_BITFIELD
2785 uint32_t cmdcodeoff :28;
2786 uint32_t rsvd1 :12;
2787 uint32_t seqlenbcnt :4;
2788 #else /* __LITTLE_ENDIAN */
2789 uint32_t seqlenbcnt :4;
2790 uint32_t rsvd1 :12;
2791 uint32_t cmdcodeoff :28;
2792 #endif
2793 uint32_t cmdmatch[8];
2794
2795 uint32_t rsvd[2];
2796 } profile5;
2797
2798 } profiles;
2799
2800};
2801
2802
dea31012005-04-17 16:05:31 -05002803
James Smart2e0fef82007-06-17 19:56:36 -05002804/* Structure for MB Command CONFIG_PORT (0x88) */
dea31012005-04-17 16:05:31 -05002805typedef struct {
James Smarted957682007-06-17 19:56:37 -05002806#ifdef __BIG_ENDIAN_BITFIELD
2807 uint32_t cBE : 1;
2808 uint32_t cET : 1;
2809 uint32_t cHpcb : 1;
2810 uint32_t cMA : 1;
2811 uint32_t sli_mode : 4;
2812 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2813 * config block */
2814#else /* __LITTLE_ENDIAN */
2815 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2816 * config block */
2817 uint32_t sli_mode : 4;
2818 uint32_t cMA : 1;
2819 uint32_t cHpcb : 1;
2820 uint32_t cET : 1;
2821 uint32_t cBE : 1;
2822#endif
2823
dea31012005-04-17 16:05:31 -05002824 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
2825 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
James Smart97207482008-12-04 22:39:19 -05002826 uint32_t hbainit[5];
2827#ifdef __BIG_ENDIAN_BITFIELD
2828 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
2829 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
2830#else /* __LITTLE_ENDIAN */
2831 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
2832 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
2833#endif
James Smarted957682007-06-17 19:56:37 -05002834
2835#ifdef __BIG_ENDIAN_BITFIELD
James Smartda0436e2009-05-22 14:51:39 -04002836 uint32_t rsvd1 : 19; /* Reserved */
2837 uint32_t cdss : 1; /* Configure Data Security SLI */
James Smartcb69f7d2011-12-13 13:21:57 -05002838 uint32_t casabt : 1; /* Configure async abts status notice */
2839 uint32_t rsvd2 : 2; /* Reserved */
James Smart81301a92008-12-04 22:39:46 -05002840 uint32_t cbg : 1; /* Configure BlockGuard */
2841 uint32_t cmv : 1; /* Configure Max VPIs */
James Smarted957682007-06-17 19:56:37 -05002842 uint32_t ccrp : 1; /* Config Command Ring Polling */
2843 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2844 uint32_t chbs : 1; /* Cofigure Host Backing store */
2845 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2846 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2847 uint32_t cmx : 1; /* Configure Max XRIs */
2848 uint32_t cmr : 1; /* Configure Max RPIs */
2849#else /* __LITTLE_ENDIAN */
2850 uint32_t cmr : 1; /* Configure Max RPIs */
2851 uint32_t cmx : 1; /* Configure Max XRIs */
2852 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2853 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2854 uint32_t chbs : 1; /* Cofigure Host Backing store */
2855 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2856 uint32_t ccrp : 1; /* Config Command Ring Polling */
2857 uint32_t cmv : 1; /* Configure Max VPIs */
James Smart81301a92008-12-04 22:39:46 -05002858 uint32_t cbg : 1; /* Configure BlockGuard */
James Smartcb69f7d2011-12-13 13:21:57 -05002859 uint32_t rsvd2 : 2; /* Reserved */
2860 uint32_t casabt : 1; /* Configure async abts status notice */
James Smartda0436e2009-05-22 14:51:39 -04002861 uint32_t cdss : 1; /* Configure Data Security SLI */
2862 uint32_t rsvd1 : 19; /* Reserved */
James Smarted957682007-06-17 19:56:37 -05002863#endif
2864#ifdef __BIG_ENDIAN_BITFIELD
James Smartda0436e2009-05-22 14:51:39 -04002865 uint32_t rsvd3 : 19; /* Reserved */
2866 uint32_t gdss : 1; /* Configure Data Security SLI */
James Smartcb69f7d2011-12-13 13:21:57 -05002867 uint32_t gasabt : 1; /* Grant async abts status notice */
2868 uint32_t rsvd4 : 2; /* Reserved */
James Smart81301a92008-12-04 22:39:46 -05002869 uint32_t gbg : 1; /* Grant BlockGuard */
James Smarted957682007-06-17 19:56:37 -05002870 uint32_t gmv : 1; /* Grant Max VPIs */
2871 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2872 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2873 uint32_t ghbs : 1; /* Grant Host Backing Store */
2874 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2875 uint32_t gerbm : 1; /* Grant ERBM Request */
2876 uint32_t gmx : 1; /* Grant Max XRIs */
2877 uint32_t gmr : 1; /* Grant Max RPIs */
2878#else /* __LITTLE_ENDIAN */
2879 uint32_t gmr : 1; /* Grant Max RPIs */
2880 uint32_t gmx : 1; /* Grant Max XRIs */
2881 uint32_t gerbm : 1; /* Grant ERBM Request */
2882 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2883 uint32_t ghbs : 1; /* Grant Host Backing Store */
2884 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2885 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2886 uint32_t gmv : 1; /* Grant Max VPIs */
James Smart81301a92008-12-04 22:39:46 -05002887 uint32_t gbg : 1; /* Grant BlockGuard */
James Smartcb69f7d2011-12-13 13:21:57 -05002888 uint32_t rsvd4 : 2; /* Reserved */
2889 uint32_t gasabt : 1; /* Grant async abts status notice */
James Smartda0436e2009-05-22 14:51:39 -04002890 uint32_t gdss : 1; /* Configure Data Security SLI */
2891 uint32_t rsvd3 : 19; /* Reserved */
James Smarted957682007-06-17 19:56:37 -05002892#endif
2893
2894#ifdef __BIG_ENDIAN_BITFIELD
2895 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2896 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2897#else /* __LITTLE_ENDIAN */
2898 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2899 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2900#endif
2901
2902#ifdef __BIG_ENDIAN_BITFIELD
2903 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
James Smartda0436e2009-05-22 14:51:39 -04002904 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
James Smarted957682007-06-17 19:56:37 -05002905#else /* __LITTLE_ENDIAN */
James Smartda0436e2009-05-22 14:51:39 -04002906 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
James Smarted957682007-06-17 19:56:37 -05002907 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
2908#endif
2909
James Smartda0436e2009-05-22 14:51:39 -04002910 uint32_t rsvd6; /* Reserved */
James Smarted957682007-06-17 19:56:37 -05002911
2912#ifdef __BIG_ENDIAN_BITFIELD
James Smartbc739052010-08-04 16:11:18 -04002913 uint32_t fips_rev : 3; /* FIPS Spec Revision */
2914 uint32_t fips_level : 4; /* FIPS Level */
2915 uint32_t sec_err : 9; /* security crypto error */
James Smarted957682007-06-17 19:56:37 -05002916 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
2917#else /* __LITTLE_ENDIAN */
2918 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
James Smartbc739052010-08-04 16:11:18 -04002919 uint32_t sec_err : 9; /* security crypto error */
2920 uint32_t fips_level : 4; /* FIPS Level */
2921 uint32_t fips_rev : 3; /* FIPS Spec Revision */
James Smarted957682007-06-17 19:56:37 -05002922#endif
2923
dea31012005-04-17 16:05:31 -05002924} CONFIG_PORT_VAR;
2925
James Smart93996272008-08-24 21:50:30 -04002926/* Structure for MB Command CONFIG_MSI (0x30) */
2927struct config_msi_var {
2928#ifdef __BIG_ENDIAN_BITFIELD
2929 uint32_t dfltMsgNum:8; /* Default message number */
2930 uint32_t rsvd1:11; /* Reserved */
2931 uint32_t NID:5; /* Number of secondary attention IDs */
2932 uint32_t rsvd2:5; /* Reserved */
2933 uint32_t dfltPresent:1; /* Default message number present */
2934 uint32_t addFlag:1; /* Add association flag */
2935 uint32_t reportFlag:1; /* Report association flag */
2936#else /* __LITTLE_ENDIAN_BITFIELD */
2937 uint32_t reportFlag:1; /* Report association flag */
2938 uint32_t addFlag:1; /* Add association flag */
2939 uint32_t dfltPresent:1; /* Default message number present */
2940 uint32_t rsvd2:5; /* Reserved */
2941 uint32_t NID:5; /* Number of secondary attention IDs */
2942 uint32_t rsvd1:11; /* Reserved */
2943 uint32_t dfltMsgNum:8; /* Default message number */
2944#endif
2945 uint32_t attentionConditions[2];
2946 uint8_t attentionId[16];
2947 uint8_t messageNumberByHA[64];
2948 uint8_t messageNumberByID[16];
2949 uint32_t autoClearHA[2];
2950#ifdef __BIG_ENDIAN_BITFIELD
2951 uint32_t rsvd3:16;
2952 uint32_t autoClearID:16;
2953#else /* __LITTLE_ENDIAN_BITFIELD */
2954 uint32_t autoClearID:16;
2955 uint32_t rsvd3:16;
2956#endif
2957 uint32_t rsvd4;
2958};
2959
dea31012005-04-17 16:05:31 -05002960/* SLI-2 Port Control Block */
2961
2962/* SLIM POINTER */
2963#define SLIMOFF 0x30 /* WORD */
2964
2965typedef struct _SLI2_RDSC {
2966 uint32_t cmdEntries;
2967 uint32_t cmdAddrLow;
2968 uint32_t cmdAddrHigh;
2969
2970 uint32_t rspEntries;
2971 uint32_t rspAddrLow;
2972 uint32_t rspAddrHigh;
2973} SLI2_RDSC;
2974
2975typedef struct _PCB {
2976#ifdef __BIG_ENDIAN_BITFIELD
2977 uint32_t type:8;
Phil Carmody497888c2011-07-14 15:07:13 +03002978#define TYPE_NATIVE_SLI2 0x01
dea31012005-04-17 16:05:31 -05002979 uint32_t feature:8;
Phil Carmody497888c2011-07-14 15:07:13 +03002980#define FEATURE_INITIAL_SLI2 0x01
dea31012005-04-17 16:05:31 -05002981 uint32_t rsvd:12;
2982 uint32_t maxRing:4;
2983#else /* __LITTLE_ENDIAN_BITFIELD */
2984 uint32_t maxRing:4;
2985 uint32_t rsvd:12;
2986 uint32_t feature:8;
Phil Carmody497888c2011-07-14 15:07:13 +03002987#define FEATURE_INITIAL_SLI2 0x01
dea31012005-04-17 16:05:31 -05002988 uint32_t type:8;
Phil Carmody497888c2011-07-14 15:07:13 +03002989#define TYPE_NATIVE_SLI2 0x01
dea31012005-04-17 16:05:31 -05002990#endif
2991
2992 uint32_t mailBoxSize;
2993 uint32_t mbAddrLow;
2994 uint32_t mbAddrHigh;
2995
2996 uint32_t hgpAddrLow;
2997 uint32_t hgpAddrHigh;
2998
2999 uint32_t pgpAddrLow;
3000 uint32_t pgpAddrHigh;
James Smart2a76a282012-08-03 12:35:54 -04003001 SLI2_RDSC rdsc[MAX_SLI3_RINGS];
dea31012005-04-17 16:05:31 -05003002} PCB_t;
3003
3004/* NEW_FEATURE */
3005typedef struct {
3006#ifdef __BIG_ENDIAN_BITFIELD
3007 uint32_t rsvd0:27;
3008 uint32_t discardFarp:1;
3009 uint32_t IPEnable:1;
3010 uint32_t nodeName:1;
3011 uint32_t portName:1;
3012 uint32_t filterEnable:1;
3013#else /* __LITTLE_ENDIAN_BITFIELD */
3014 uint32_t filterEnable:1;
3015 uint32_t portName:1;
3016 uint32_t nodeName:1;
3017 uint32_t IPEnable:1;
3018 uint32_t discardFarp:1;
3019 uint32_t rsvd:27;
3020#endif
3021
3022 uint8_t portname[8]; /* Used to be struct lpfc_name */
3023 uint8_t nodename[8];
3024 uint32_t rsvd1;
3025 uint32_t rsvd2;
3026 uint32_t rsvd3;
3027 uint32_t IPAddress;
3028} CONFIG_FARP_VAR;
3029
James Smart57127f12007-10-27 13:37:05 -04003030/* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
3031
3032typedef struct {
3033#ifdef __BIG_ENDIAN_BITFIELD
3034 uint32_t rsvd:30;
3035 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3036#else /* __LITTLE_ENDIAN */
3037 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3038 uint32_t rsvd:30;
3039#endif
3040} ASYNCEVT_ENABLE_VAR;
3041
dea31012005-04-17 16:05:31 -05003042/* Union of all Mailbox Command types */
3043#define MAILBOX_CMD_WSIZE 32
3044#define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
James Smart7a470272010-03-15 11:25:20 -04003045/* ext_wsize times 4 bytes should not be greater than max xmit size */
3046#define MAILBOX_EXT_WSIZE 512
3047#define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3048#define MAILBOX_HBA_EXT_OFFSET 0x100
3049/* max mbox xmit size is a page size for sysfs IO operations */
James Smartc0c11512011-05-24 11:41:34 -04003050#define MAILBOX_SYSFS_MAX 4096
dea31012005-04-17 16:05:31 -05003051
3052typedef union {
James Smarted957682007-06-17 19:56:37 -05003053 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
3054 * feature/max ring number
3055 */
3056 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
3057 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
3058 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
James Smart311464e2007-08-02 11:10:37 -04003059 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
3060 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
dea31012005-04-17 16:05:31 -05003061 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
James Smarted957682007-06-17 19:56:37 -05003062 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
3063 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
dea31012005-04-17 16:05:31 -05003064 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
3065 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
3066 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
3067 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
3068 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
3069 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
James Smarted957682007-06-17 19:56:37 -05003070 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
3071 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
3072 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
3073 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
dea31012005-04-17 16:05:31 -05003074 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
3075 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
dea31012005-04-17 16:05:31 -05003076 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
James Smarted957682007-06-17 19:56:37 -05003077 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
3078 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
3079 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
3080 * NEW_FEATURE
3081 */
3082 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
James Smartd7c255b2008-08-24 21:50:00 -04003083 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
James Smarted957682007-06-17 19:56:37 -05003084 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
James Smart76a95d72010-11-20 23:11:48 -05003085 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
James Smart92d7f7b2007-06-17 19:56:38 -05003086 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
3087 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
James Smart57127f12007-10-27 13:37:05 -04003088 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
James Smartc7495932010-04-06 15:05:28 -04003089 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38
3090 * (READ_EVENT_LOG)
3091 */
James Smart93996272008-08-24 21:50:30 -04003092 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */
dea31012005-04-17 16:05:31 -05003093} MAILVARIANTS;
3094
3095/*
3096 * SLI-2 specific structures
3097 */
3098
James.Smart@Emulex.Com4cc2da12005-06-25 10:34:00 -04003099struct lpfc_hgp {
3100 __le32 cmdPutInx;
3101 __le32 rspGetInx;
3102};
dea31012005-04-17 16:05:31 -05003103
James.Smart@Emulex.Com4cc2da12005-06-25 10:34:00 -04003104struct lpfc_pgp {
3105 __le32 cmdGetInx;
3106 __le32 rspPutInx;
3107};
dea31012005-04-17 16:05:31 -05003108
James Smarted957682007-06-17 19:56:37 -05003109struct sli2_desc {
dea31012005-04-17 16:05:31 -05003110 uint32_t unused1[16];
James Smart2a76a282012-08-03 12:35:54 -04003111 struct lpfc_hgp host[MAX_SLI3_RINGS];
3112 struct lpfc_pgp port[MAX_SLI3_RINGS];
James Smarted957682007-06-17 19:56:37 -05003113};
3114
3115struct sli3_desc {
James Smart2a76a282012-08-03 12:35:54 -04003116 struct lpfc_hgp host[MAX_SLI3_RINGS];
James Smarted957682007-06-17 19:56:37 -05003117 uint32_t reserved[8];
3118 uint32_t hbq_put[16];
3119};
3120
3121struct sli3_pgp {
James Smart2a76a282012-08-03 12:35:54 -04003122 struct lpfc_pgp port[MAX_SLI3_RINGS];
James Smarted957682007-06-17 19:56:37 -05003123 uint32_t hbq_get[16];
3124};
dea31012005-04-17 16:05:31 -05003125
James Smart34b02dc2008-08-24 21:49:55 -04003126union sli_var {
3127 struct sli2_desc s2;
3128 struct sli3_desc s3;
3129 struct sli3_pgp s3_pgp;
James Smart34b02dc2008-08-24 21:49:55 -04003130};
dea31012005-04-17 16:05:31 -05003131
3132typedef struct {
3133#ifdef __BIG_ENDIAN_BITFIELD
3134 uint16_t mbxStatus;
3135 uint8_t mbxCommand;
3136 uint8_t mbxReserved:6;
3137 uint8_t mbxHc:1;
3138 uint8_t mbxOwner:1; /* Low order bit first word */
3139#else /* __LITTLE_ENDIAN_BITFIELD */
3140 uint8_t mbxOwner:1; /* Low order bit first word */
3141 uint8_t mbxHc:1;
3142 uint8_t mbxReserved:6;
3143 uint8_t mbxCommand;
3144 uint16_t mbxStatus;
3145#endif
3146
3147 MAILVARIANTS un;
James Smart34b02dc2008-08-24 21:49:55 -04003148 union sli_var us;
dea31012005-04-17 16:05:31 -05003149} MAILBOX_t;
3150
3151/*
3152 * Begin Structure Definitions for IOCB Commands
3153 */
3154
3155typedef struct {
3156#ifdef __BIG_ENDIAN_BITFIELD
3157 uint8_t statAction;
3158 uint8_t statRsn;
3159 uint8_t statBaExp;
3160 uint8_t statLocalError;
3161#else /* __LITTLE_ENDIAN_BITFIELD */
3162 uint8_t statLocalError;
3163 uint8_t statBaExp;
3164 uint8_t statRsn;
3165 uint8_t statAction;
3166#endif
3167 /* statRsn P/F_RJT reason codes */
3168#define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
3169#define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
3170#define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
3171#define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
3172#define RJT_UNSUP_CLASS 0x05 /* Class not supported */
3173#define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
3174#define RJT_UNSUP_TYPE 0x07 /* Type not supported */
3175#define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
3176#define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
3177#define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
3178#define RJT_BAD_OXID 0x0B /* OX_ID invalid */
3179#define RJT_BAD_RXID 0x0C /* RX_ID invalid */
3180#define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
3181#define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
3182#define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
3183#define RJT_BAD_PARM 0x10 /* Param. field invalid */
3184#define RJT_XCHG_ERR 0x11 /* Exchange error */
3185#define RJT_PROT_ERR 0x12 /* Protocol error */
3186#define RJT_BAD_LENGTH 0x13 /* Invalid Length */
3187#define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3188#define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3189#define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
3190#define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
3191#define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
3192#define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
3193#define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
3194
3195#define IOERR_SUCCESS 0x00 /* statLocalError */
3196#define IOERR_MISSING_CONTINUE 0x01
3197#define IOERR_SEQUENCE_TIMEOUT 0x02
3198#define IOERR_INTERNAL_ERROR 0x03
3199#define IOERR_INVALID_RPI 0x04
3200#define IOERR_NO_XRI 0x05
3201#define IOERR_ILLEGAL_COMMAND 0x06
3202#define IOERR_XCHG_DROPPED 0x07
3203#define IOERR_ILLEGAL_FIELD 0x08
3204#define IOERR_BAD_CONTINUE 0x09
3205#define IOERR_TOO_MANY_BUFFERS 0x0A
3206#define IOERR_RCV_BUFFER_WAITING 0x0B
3207#define IOERR_NO_CONNECTION 0x0C
3208#define IOERR_TX_DMA_FAILED 0x0D
3209#define IOERR_RX_DMA_FAILED 0x0E
3210#define IOERR_ILLEGAL_FRAME 0x0F
3211#define IOERR_EXTRA_DATA 0x10
3212#define IOERR_NO_RESOURCES 0x11
3213#define IOERR_RESERVED 0x12
3214#define IOERR_ILLEGAL_LENGTH 0x13
3215#define IOERR_UNSUPPORTED_FEATURE 0x14
3216#define IOERR_ABORT_IN_PROGRESS 0x15
3217#define IOERR_ABORT_REQUESTED 0x16
3218#define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
3219#define IOERR_LOOP_OPEN_FAILURE 0x18
3220#define IOERR_RING_RESET 0x19
3221#define IOERR_LINK_DOWN 0x1A
3222#define IOERR_CORRUPTED_DATA 0x1B
3223#define IOERR_CORRUPTED_RPI 0x1C
3224#define IOERR_OUT_OF_ORDER_DATA 0x1D
3225#define IOERR_OUT_OF_ORDER_ACK 0x1E
3226#define IOERR_DUP_FRAME 0x1F
3227#define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
3228#define IOERR_BAD_HOST_ADDRESS 0x21
3229#define IOERR_RCV_HDRBUF_WAITING 0x22
3230#define IOERR_MISSING_HDR_BUFFER 0x23
3231#define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
3232#define IOERR_ABORTMULT_REQUESTED 0x25
3233#define IOERR_BUFFER_SHORTAGE 0x28
3234#define IOERR_DEFAULT 0x29
3235#define IOERR_CNT 0x2A
James Smartb92938b2010-06-07 15:24:12 -04003236#define IOERR_SLER_FAILURE 0x46
3237#define IOERR_SLER_CMD_RCV_FAILURE 0x47
3238#define IOERR_SLER_REC_RJT_ERR 0x48
3239#define IOERR_SLER_REC_SRR_RETRY_ERR 0x49
3240#define IOERR_SLER_SRR_RJT_ERR 0x4A
3241#define IOERR_SLER_RRQ_RJT_ERR 0x4C
3242#define IOERR_SLER_RRQ_RETRY_ERR 0x4D
3243#define IOERR_SLER_ABTS_ERR 0x4E
James Smartab56dc22011-02-16 12:39:57 -05003244#define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0
3245#define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1
3246#define IOERR_ELXSEC_CRYPTO_ERROR 0xF2
3247#define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3
dea31012005-04-17 16:05:31 -05003248#define IOERR_DRVR_MASK 0x100
3249#define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
3250#define IOERR_SLI_BRESET 0x102
3251#define IOERR_SLI_ABORTED 0x103
James Smarte3d2b802012-08-14 14:25:43 -04003252#define IOERR_PARAM_MASK 0x1ff
dea31012005-04-17 16:05:31 -05003253} PARM_ERR;
3254
3255typedef union {
3256 struct {
3257#ifdef __BIG_ENDIAN_BITFIELD
3258 uint8_t Rctl; /* R_CTL field */
3259 uint8_t Type; /* TYPE field */
3260 uint8_t Dfctl; /* DF_CTL field */
3261 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3262#else /* __LITTLE_ENDIAN_BITFIELD */
3263 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3264 uint8_t Dfctl; /* DF_CTL field */
3265 uint8_t Type; /* TYPE field */
3266 uint8_t Rctl; /* R_CTL field */
3267#endif
3268
3269#define BC 0x02 /* Broadcast Received - Fctl */
3270#define SI 0x04 /* Sequence Initiative */
3271#define LA 0x08 /* Ignore Link Attention state */
3272#define LS 0x80 /* Last Sequence */
3273 } hcsw;
3274 uint32_t reserved;
3275} WORD5;
3276
3277/* IOCB Command template for a generic response */
3278typedef struct {
3279 uint32_t reserved[4];
3280 PARM_ERR perr;
3281} GENERIC_RSP;
3282
3283/* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3284typedef struct {
3285 struct ulp_bde xrsqbde[2];
3286 uint32_t xrsqRo; /* Starting Relative Offset */
3287 WORD5 w5; /* Header control/status word */
3288} XR_SEQ_FIELDS;
3289
3290/* IOCB Command template for ELS_REQUEST */
3291typedef struct {
3292 struct ulp_bde elsReq;
3293 struct ulp_bde elsRsp;
3294
3295#ifdef __BIG_ENDIAN_BITFIELD
3296 uint32_t word4Rsvd:7;
3297 uint32_t fl:1;
3298 uint32_t myID:24;
3299 uint32_t word5Rsvd:8;
3300 uint32_t remoteID:24;
3301#else /* __LITTLE_ENDIAN_BITFIELD */
3302 uint32_t myID:24;
3303 uint32_t fl:1;
3304 uint32_t word4Rsvd:7;
3305 uint32_t remoteID:24;
3306 uint32_t word5Rsvd:8;
3307#endif
3308} ELS_REQUEST;
3309
3310/* IOCB Command template for RCV_ELS_REQ */
3311typedef struct {
3312 struct ulp_bde elsReq[2];
3313 uint32_t parmRo;
3314
3315#ifdef __BIG_ENDIAN_BITFIELD
3316 uint32_t word5Rsvd:8;
3317 uint32_t remoteID:24;
3318#else /* __LITTLE_ENDIAN_BITFIELD */
3319 uint32_t remoteID:24;
3320 uint32_t word5Rsvd:8;
3321#endif
3322} RCV_ELS_REQ;
3323
3324/* IOCB Command template for ABORT / CLOSE_XRI */
3325typedef struct {
3326 uint32_t rsvd[3];
3327 uint32_t abortType;
3328#define ABORT_TYPE_ABTX 0x00000000
3329#define ABORT_TYPE_ABTS 0x00000001
3330 uint32_t parm;
3331#ifdef __BIG_ENDIAN_BITFIELD
3332 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3333 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3334#else /* __LITTLE_ENDIAN_BITFIELD */
3335 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3336 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3337#endif
3338} AC_XRI;
3339
3340/* IOCB Command template for ABORT_MXRI64 */
3341typedef struct {
3342 uint32_t rsvd[3];
3343 uint32_t abortType;
3344 uint32_t parm;
3345 uint32_t iotag32;
3346} A_MXRI64;
3347
3348/* IOCB Command template for GET_RPI */
3349typedef struct {
3350 uint32_t rsvd[4];
3351 uint32_t parmRo;
3352#ifdef __BIG_ENDIAN_BITFIELD
3353 uint32_t word5Rsvd:8;
3354 uint32_t remoteID:24;
3355#else /* __LITTLE_ENDIAN_BITFIELD */
3356 uint32_t remoteID:24;
3357 uint32_t word5Rsvd:8;
3358#endif
3359} GET_RPI;
3360
3361/* IOCB Command template for all FCP Initiator commands */
3362typedef struct {
3363 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
3364 struct ulp_bde fcpi_rsp; /* Rcv buffer */
3365 uint32_t fcpi_parm;
3366 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3367} FCPI_FIELDS;
3368
3369/* IOCB Command template for all FCP Target commands */
3370typedef struct {
3371 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
3372 uint32_t fcpt_Offset;
3373 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3374} FCPT_FIELDS;
3375
3376/* SLI-2 IOCB structure definitions */
3377
3378/* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3379typedef struct {
3380 ULP_BDL bdl;
3381 uint32_t xrsqRo; /* Starting Relative Offset */
3382 WORD5 w5; /* Header control/status word */
3383} XMT_SEQ_FIELDS64;
3384
James Smart939723a2012-05-09 21:19:03 -04003385/* This word is remote ports D_ID for XMIT_ELS_RSP64 */
3386#define xmit_els_remoteID xrsqRo
3387
dea31012005-04-17 16:05:31 -05003388/* IOCB Command template for 64 bit RCV_SEQUENCE64 */
3389typedef struct {
3390 struct ulp_bde64 rcvBde;
3391 uint32_t rsvd1;
3392 uint32_t xrsqRo; /* Starting Relative Offset */
3393 WORD5 w5; /* Header control/status word */
3394} RCV_SEQ_FIELDS64;
3395
3396/* IOCB Command template for ELS_REQUEST64 */
3397typedef struct {
3398 ULP_BDL bdl;
3399#ifdef __BIG_ENDIAN_BITFIELD
3400 uint32_t word4Rsvd:7;
3401 uint32_t fl:1;
3402 uint32_t myID:24;
3403 uint32_t word5Rsvd:8;
3404 uint32_t remoteID:24;
3405#else /* __LITTLE_ENDIAN_BITFIELD */
3406 uint32_t myID:24;
3407 uint32_t fl:1;
3408 uint32_t word4Rsvd:7;
3409 uint32_t remoteID:24;
3410 uint32_t word5Rsvd:8;
3411#endif
3412} ELS_REQUEST64;
3413
3414/* IOCB Command template for GEN_REQUEST64 */
3415typedef struct {
3416 ULP_BDL bdl;
3417 uint32_t xrsqRo; /* Starting Relative Offset */
3418 WORD5 w5; /* Header control/status word */
3419} GEN_REQUEST64;
3420
3421/* IOCB Command template for RCV_ELS_REQ64 */
3422typedef struct {
3423 struct ulp_bde64 elsReq;
3424 uint32_t rcvd1;
3425 uint32_t parmRo;
3426
3427#ifdef __BIG_ENDIAN_BITFIELD
3428 uint32_t word5Rsvd:8;
3429 uint32_t remoteID:24;
3430#else /* __LITTLE_ENDIAN_BITFIELD */
3431 uint32_t remoteID:24;
3432 uint32_t word5Rsvd:8;
3433#endif
3434} RCV_ELS_REQ64;
3435
James Smart9c2face2008-01-11 01:53:18 -05003436/* IOCB Command template for RCV_SEQ64 */
3437struct rcv_seq64 {
3438 struct ulp_bde64 elsReq;
3439 uint32_t hbq_1;
3440 uint32_t parmRo;
3441#ifdef __BIG_ENDIAN_BITFIELD
3442 uint32_t rctl:8;
3443 uint32_t type:8;
3444 uint32_t dfctl:8;
3445 uint32_t ls:1;
3446 uint32_t fs:1;
3447 uint32_t rsvd2:3;
3448 uint32_t si:1;
3449 uint32_t bc:1;
3450 uint32_t rsvd3:1;
3451#else /* __LITTLE_ENDIAN_BITFIELD */
3452 uint32_t rsvd3:1;
3453 uint32_t bc:1;
3454 uint32_t si:1;
3455 uint32_t rsvd2:3;
3456 uint32_t fs:1;
3457 uint32_t ls:1;
3458 uint32_t dfctl:8;
3459 uint32_t type:8;
3460 uint32_t rctl:8;
3461#endif
3462};
3463
dea31012005-04-17 16:05:31 -05003464/* IOCB Command template for all 64 bit FCP Initiator commands */
3465typedef struct {
3466 ULP_BDL bdl;
3467 uint32_t fcpi_parm;
3468 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
3469} FCPI_FIELDS64;
3470
3471/* IOCB Command template for all 64 bit FCP Target commands */
3472typedef struct {
3473 ULP_BDL bdl;
3474 uint32_t fcpt_Offset;
3475 uint32_t fcpt_Length; /* transfer ready for IWRITE */
3476} FCPT_FIELDS64;
3477
James Smart57127f12007-10-27 13:37:05 -04003478/* IOCB Command template for Async Status iocb commands */
3479typedef struct {
3480 uint32_t rsvd[4];
3481 uint32_t param;
3482#ifdef __BIG_ENDIAN_BITFIELD
3483 uint16_t evt_code; /* High order bits word 5 */
3484 uint16_t sub_ctxt_tag; /* Low order bits word 5 */
3485#else /* __LITTLE_ENDIAN_BITFIELD */
3486 uint16_t sub_ctxt_tag; /* High order bits word 5 */
3487 uint16_t evt_code; /* Low order bits word 5 */
3488#endif
3489} ASYNCSTAT_FIELDS;
3490#define ASYNC_TEMP_WARN 0x100
3491#define ASYNC_TEMP_SAFE 0x101
James Smartcb69f7d2011-12-13 13:21:57 -05003492#define ASYNC_STATUS_CN 0x102
James Smart57127f12007-10-27 13:37:05 -04003493
James Smarted957682007-06-17 19:56:37 -05003494/* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
3495 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
3496
3497struct rcv_sli3 {
James Smarted957682007-06-17 19:56:37 -05003498#ifdef __BIG_ENDIAN_BITFIELD
James Smart7851fe22011-07-22 18:36:52 -04003499 uint16_t ox_id;
3500 uint16_t seq_cnt;
3501
James Smarted957682007-06-17 19:56:37 -05003502 uint16_t vpi;
3503 uint16_t word9Rsvd;
3504#else /* __LITTLE_ENDIAN */
James Smart7851fe22011-07-22 18:36:52 -04003505 uint16_t seq_cnt;
3506 uint16_t ox_id;
3507
James Smarted957682007-06-17 19:56:37 -05003508 uint16_t word9Rsvd;
3509 uint16_t vpi;
3510#endif
3511 uint32_t word10Rsvd;
3512 uint32_t acc_len; /* accumulated length */
3513 struct ulp_bde64 bde2;
3514};
3515
James Smart76bb24e2007-10-27 13:38:00 -04003516/* Structure used for a single HBQ entry */
3517struct lpfc_hbq_entry {
3518 struct ulp_bde64 bde;
3519 uint32_t buffer_tag;
3520};
James Smart92d7f7b2007-06-17 19:56:38 -05003521
James Smart76bb24e2007-10-27 13:38:00 -04003522/* IOCB Command template for QUE_XRI64_CX (0xB3) command */
3523typedef struct {
3524 struct lpfc_hbq_entry buff;
3525 uint32_t rsvd;
3526 uint32_t rsvd1;
3527} QUE_XRI64_CX_FIELDS;
3528
3529struct que_xri64cx_ext_fields {
3530 uint32_t iotag64_low;
3531 uint32_t iotag64_high;
3532 uint32_t ebde_count;
3533 uint32_t rsvd;
3534 struct lpfc_hbq_entry buff[5];
3535};
James Smart92d7f7b2007-06-17 19:56:38 -05003536
James Smart81301a92008-12-04 22:39:46 -05003537struct sli3_bg_fields {
3538 uint32_t filler[6]; /* word 8-13 in IOCB */
3539 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */
3540/* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
3541#define BGS_BIDIR_BG_PROF_MASK 0xff000000
3542#define BGS_BIDIR_BG_PROF_SHIFT 24
3543#define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000
3544#define BGS_BIDIR_ERR_COND_SHIFT 16
3545#define BGS_BG_PROFILE_MASK 0x0000ff00
3546#define BGS_BG_PROFILE_SHIFT 8
3547#define BGS_INVALID_PROF_MASK 0x00000020
3548#define BGS_INVALID_PROF_SHIFT 5
3549#define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010
3550#define BGS_UNINIT_DIF_BLOCK_SHIFT 4
3551#define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008
3552#define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
3553#define BGS_REFTAG_ERR_MASK 0x00000004
3554#define BGS_REFTAG_ERR_SHIFT 2
3555#define BGS_APPTAG_ERR_MASK 0x00000002
3556#define BGS_APPTAG_ERR_SHIFT 1
3557#define BGS_GUARD_ERR_MASK 0x00000001
3558#define BGS_GUARD_ERR_SHIFT 0
3559 uint32_t bgstat; /* word 15 - BlockGuard Status */
3560};
3561
3562static inline uint32_t
3563lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
3564{
James Smartbc739052010-08-04 16:11:18 -04003565 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
James Smart81301a92008-12-04 22:39:46 -05003566 BGS_BIDIR_BG_PROF_SHIFT;
3567}
3568
3569static inline uint32_t
3570lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
3571{
James Smartbc739052010-08-04 16:11:18 -04003572 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
James Smart81301a92008-12-04 22:39:46 -05003573 BGS_BIDIR_ERR_COND_SHIFT;
3574}
3575
3576static inline uint32_t
3577lpfc_bgs_get_bg_prof(uint32_t bgstat)
3578{
James Smartbc739052010-08-04 16:11:18 -04003579 return (bgstat & BGS_BG_PROFILE_MASK) >>
James Smart81301a92008-12-04 22:39:46 -05003580 BGS_BG_PROFILE_SHIFT;
3581}
3582
3583static inline uint32_t
3584lpfc_bgs_get_invalid_prof(uint32_t bgstat)
3585{
James Smartbc739052010-08-04 16:11:18 -04003586 return (bgstat & BGS_INVALID_PROF_MASK) >>
James Smart81301a92008-12-04 22:39:46 -05003587 BGS_INVALID_PROF_SHIFT;
3588}
3589
3590static inline uint32_t
3591lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
3592{
James Smartbc739052010-08-04 16:11:18 -04003593 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
James Smart81301a92008-12-04 22:39:46 -05003594 BGS_UNINIT_DIF_BLOCK_SHIFT;
3595}
3596
3597static inline uint32_t
3598lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
3599{
James Smartbc739052010-08-04 16:11:18 -04003600 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
James Smart81301a92008-12-04 22:39:46 -05003601 BGS_HI_WATER_MARK_PRESENT_SHIFT;
3602}
3603
3604static inline uint32_t
3605lpfc_bgs_get_reftag_err(uint32_t bgstat)
3606{
James Smartbc739052010-08-04 16:11:18 -04003607 return (bgstat & BGS_REFTAG_ERR_MASK) >>
James Smart81301a92008-12-04 22:39:46 -05003608 BGS_REFTAG_ERR_SHIFT;
3609}
3610
3611static inline uint32_t
3612lpfc_bgs_get_apptag_err(uint32_t bgstat)
3613{
James Smartbc739052010-08-04 16:11:18 -04003614 return (bgstat & BGS_APPTAG_ERR_MASK) >>
James Smart81301a92008-12-04 22:39:46 -05003615 BGS_APPTAG_ERR_SHIFT;
3616}
3617
3618static inline uint32_t
3619lpfc_bgs_get_guard_err(uint32_t bgstat)
3620{
James Smartbc739052010-08-04 16:11:18 -04003621 return (bgstat & BGS_GUARD_ERR_MASK) >>
James Smart81301a92008-12-04 22:39:46 -05003622 BGS_GUARD_ERR_SHIFT;
3623}
3624
James Smart34b02dc2008-08-24 21:49:55 -04003625#define LPFC_EXT_DATA_BDE_COUNT 3
3626struct fcp_irw_ext {
3627 uint32_t io_tag64_low;
3628 uint32_t io_tag64_high;
3629#ifdef __BIG_ENDIAN_BITFIELD
3630 uint8_t reserved1;
3631 uint8_t reserved2;
3632 uint8_t reserved3;
3633 uint8_t ebde_count;
3634#else /* __LITTLE_ENDIAN */
3635 uint8_t ebde_count;
3636 uint8_t reserved3;
3637 uint8_t reserved2;
3638 uint8_t reserved1;
3639#endif
3640 uint32_t reserved4;
3641 struct ulp_bde64 rbde; /* response bde */
3642 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
3643 uint8_t icd[32]; /* immediate command data (32 bytes) */
3644};
3645
dea31012005-04-17 16:05:31 -05003646typedef struct _IOCB { /* IOCB structure */
3647 union {
3648 GENERIC_RSP grsp; /* Generic response */
3649 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
3650 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
3651 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
3652 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
3653 A_MXRI64 amxri; /* abort multiple xri command overlay */
3654 GET_RPI getrpi; /* GET_RPI template */
3655 FCPI_FIELDS fcpi; /* FCP Initiator template */
3656 FCPT_FIELDS fcpt; /* FCP target template */
3657
3658 /* SLI-2 structures */
3659
James Smarted957682007-06-17 19:56:37 -05003660 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
3661 * bde_64s */
dea31012005-04-17 16:05:31 -05003662 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
3663 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
3664 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
3665 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
3666 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
3667 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
James Smart57127f12007-10-27 13:37:05 -04003668 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
James Smart76bb24e2007-10-27 13:38:00 -04003669 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
James Smart9c2face2008-01-11 01:53:18 -05003670 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */
James Smart546fc852011-03-11 16:06:29 -05003671 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */
dea31012005-04-17 16:05:31 -05003672 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
3673 } un;
3674 union {
3675 struct {
3676#ifdef __BIG_ENDIAN_BITFIELD
3677 uint16_t ulpContext; /* High order bits word 6 */
3678 uint16_t ulpIoTag; /* Low order bits word 6 */
3679#else /* __LITTLE_ENDIAN_BITFIELD */
3680 uint16_t ulpIoTag; /* Low order bits word 6 */
3681 uint16_t ulpContext; /* High order bits word 6 */
3682#endif
3683 } t1;
3684 struct {
3685#ifdef __BIG_ENDIAN_BITFIELD
3686 uint16_t ulpContext; /* High order bits word 6 */
3687 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3688 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3689#else /* __LITTLE_ENDIAN_BITFIELD */
3690 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3691 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3692 uint16_t ulpContext; /* High order bits word 6 */
3693#endif
3694 } t2;
3695 } un1;
3696#define ulpContext un1.t1.ulpContext
3697#define ulpIoTag un1.t1.ulpIoTag
3698#define ulpIoTag0 un1.t2.ulpIoTag0
3699
3700#ifdef __BIG_ENDIAN_BITFIELD
3701 uint32_t ulpTimeout:8;
3702 uint32_t ulpXS:1;
3703 uint32_t ulpFCP2Rcvy:1;
3704 uint32_t ulpPU:2;
3705 uint32_t ulpIr:1;
3706 uint32_t ulpClass:3;
3707 uint32_t ulpCommand:8;
3708 uint32_t ulpStatus:4;
3709 uint32_t ulpBdeCount:2;
3710 uint32_t ulpLe:1;
3711 uint32_t ulpOwner:1; /* Low order bit word 7 */
3712#else /* __LITTLE_ENDIAN_BITFIELD */
3713 uint32_t ulpOwner:1; /* Low order bit word 7 */
3714 uint32_t ulpLe:1;
3715 uint32_t ulpBdeCount:2;
3716 uint32_t ulpStatus:4;
3717 uint32_t ulpCommand:8;
3718 uint32_t ulpClass:3;
3719 uint32_t ulpIr:1;
3720 uint32_t ulpPU:2;
3721 uint32_t ulpFCP2Rcvy:1;
3722 uint32_t ulpXS:1;
3723 uint32_t ulpTimeout:8;
3724#endif
James Smart92d7f7b2007-06-17 19:56:38 -05003725
James Smarted957682007-06-17 19:56:37 -05003726 union {
3727 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
James Smart76bb24e2007-10-27 13:38:00 -04003728
3729 /* words 8-31 used for que_xri_cx iocb */
3730 struct que_xri64cx_ext_fields que_xri64cx_ext_words;
James Smart34b02dc2008-08-24 21:49:55 -04003731 struct fcp_irw_ext fcp_ext;
James Smarted957682007-06-17 19:56:37 -05003732 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
James Smart81301a92008-12-04 22:39:46 -05003733
3734 /* words 8-15 for BlockGuard */
3735 struct sli3_bg_fields sli3_bg;
James Smarted957682007-06-17 19:56:37 -05003736 } unsli3;
dea31012005-04-17 16:05:31 -05003737
James Smarted957682007-06-17 19:56:37 -05003738#define ulpCt_h ulpXS
3739#define ulpCt_l ulpFCP2Rcvy
3740
3741#define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
3742#define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
dea31012005-04-17 16:05:31 -05003743#define PARM_UNUSED 0 /* PU field (Word 4) not used */
3744#define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
3745#define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
James Smart92d7f7b2007-06-17 19:56:38 -05003746#define PARM_NPIV_DID 3
dea31012005-04-17 16:05:31 -05003747#define CLASS1 0 /* Class 1 */
3748#define CLASS2 1 /* Class 2 */
3749#define CLASS3 2 /* Class 3 */
3750#define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
3751
3752#define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
3753#define IOSTAT_FCP_RSP_ERROR 0x1
3754#define IOSTAT_REMOTE_STOP 0x2
3755#define IOSTAT_LOCAL_REJECT 0x3
3756#define IOSTAT_NPORT_RJT 0x4
3757#define IOSTAT_FABRIC_RJT 0x5
3758#define IOSTAT_NPORT_BSY 0x6
3759#define IOSTAT_FABRIC_BSY 0x7
3760#define IOSTAT_INTERMED_RSP 0x8
3761#define IOSTAT_LS_RJT 0x9
3762#define IOSTAT_BA_RJT 0xA
3763#define IOSTAT_RSVD1 0xB
3764#define IOSTAT_RSVD2 0xC
3765#define IOSTAT_RSVD3 0xD
3766#define IOSTAT_RSVD4 0xE
James Smart92d7f7b2007-06-17 19:56:38 -05003767#define IOSTAT_NEED_BUFFER 0xF
dea31012005-04-17 16:05:31 -05003768#define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
3769#define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
3770#define IOSTAT_CNT 0x11
3771
3772} IOCB_t;
3773
3774
3775#define SLI1_SLIM_SIZE (4 * 1024)
3776
3777/* Up to 498 IOCBs will fit into 16k
3778 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
3779 */
James Smarted957682007-06-17 19:56:37 -05003780#define SLI2_SLIM_SIZE (64 * 1024)
dea31012005-04-17 16:05:31 -05003781
3782/* Maximum IOCBs that will fit in SLI2 slim */
3783#define MAX_SLI2_IOCB 498
James Smarted957682007-06-17 19:56:37 -05003784#define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
James Smart7a470272010-03-15 11:25:20 -04003785 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
3786 sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
James Smarted957682007-06-17 19:56:37 -05003787
3788/* HBQ entries are 4 words each = 4k */
3789#define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
3790 lpfc_sli_hbq_count())
dea31012005-04-17 16:05:31 -05003791
3792struct lpfc_sli2_slim {
3793 MAILBOX_t mbx;
James Smart7a470272010-03-15 11:25:20 -04003794 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE];
dea31012005-04-17 16:05:31 -05003795 PCB_t pcb;
James Smarted957682007-06-17 19:56:37 -05003796 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
dea31012005-04-17 16:05:31 -05003797};
3798
James Smart2e0fef82007-06-17 19:56:36 -05003799/*
3800 * This function checks PCI device to allow special handling for LC HBAs.
3801 *
3802 * Parameters:
3803 * device : struct pci_dev 's device field
3804 *
3805 * return 1 => TRUE
3806 * 0 => FALSE
3807 */
dea31012005-04-17 16:05:31 -05003808static inline int
3809lpfc_is_LC_HBA(unsigned short device)
3810{
3811 if ((device == PCI_DEVICE_ID_TFLY) ||
3812 (device == PCI_DEVICE_ID_PFLY) ||
3813 (device == PCI_DEVICE_ID_LP101) ||
3814 (device == PCI_DEVICE_ID_BMID) ||
3815 (device == PCI_DEVICE_ID_BSMB) ||
3816 (device == PCI_DEVICE_ID_ZMID) ||
3817 (device == PCI_DEVICE_ID_ZSMB) ||
James Smart09372822008-01-11 01:52:54 -05003818 (device == PCI_DEVICE_ID_SAT_MID) ||
3819 (device == PCI_DEVICE_ID_SAT_SMB) ||
dea31012005-04-17 16:05:31 -05003820 (device == PCI_DEVICE_ID_RFLY))
3821 return 1;
3822 else
3823 return 0;
3824}
James Smart858c9f62007-06-17 19:56:39 -05003825
3826/*
3827 * Determine if an IOCB failed because of a link event or firmware reset.
3828 */
3829
3830static inline int
3831lpfc_error_lost_link(IOCB_t *iocbp)
3832{
3833 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
3834 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
3835 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
3836 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));
3837}
James Smart84774a42008-08-24 21:50:06 -04003838
3839#define MENLO_TRANSPORT_TYPE 0xfe
3840#define MENLO_CONTEXT 0
3841#define MENLO_PU 3
3842#define MENLO_TIMEOUT 30
3843#define SETVAR_MLOMNT 0x103107
3844#define SETVAR_MLORST 0x103007
James Smartda0436e2009-05-22 14:51:39 -04003845
3846#define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */