Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 6 | * copy of this software and associated documentation files (the "Software"), |
| 7 | * to deal in the Software without restriction, including without limitation |
| 8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 9 | * and/or sell copies of the Software, and to permit persons to whom the |
| 10 | * Software is furnished to do so, subject to the following conditions: |
| 11 | * |
| 12 | * The above copyright notice and this permission notice shall be included in |
| 13 | * all copies or substantial portions of the Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 21 | * OTHER DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: Dave Airlie |
| 24 | * Alex Deucher |
Jerome Glisse | 8d1c702 | 2012-07-17 17:17:16 -0400 | [diff] [blame] | 25 | * Jerome Glisse |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 26 | */ |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 27 | #include <drm/drmP.h> |
| 28 | #include <drm/radeon_drm.h> |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 29 | #include "radeon.h" |
| 30 | |
| 31 | #include "atom.h" |
| 32 | #include "atom-bits.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 33 | #include <drm/drm_dp_helper.h> |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 34 | |
Alex Deucher | f92a8b6 | 2009-11-23 18:40:40 -0500 | [diff] [blame] | 35 | /* move these to drm_dp_helper.c/h */ |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 36 | #define DP_LINK_CONFIGURATION_SIZE 9 |
Daniel Vetter | 1a644cd | 2012-10-18 15:32:40 +0200 | [diff] [blame] | 37 | #define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 38 | |
| 39 | static char *voltage_names[] = { |
| 40 | "0.4V", "0.6V", "0.8V", "1.2V" |
| 41 | }; |
| 42 | static char *pre_emph_names[] = { |
| 43 | "0dB", "3.5dB", "6dB", "9.5dB" |
| 44 | }; |
Alex Deucher | f92a8b6 | 2009-11-23 18:40:40 -0500 | [diff] [blame] | 45 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 46 | /***** radeon AUX functions *****/ |
Alex Deucher | 34be8c9 | 2013-07-18 11:13:53 -0400 | [diff] [blame] | 47 | |
| 48 | /* Atom needs data in little endian format |
| 49 | * so swap as appropriate when copying data to |
| 50 | * or from atom. Note that atom operates on |
| 51 | * dw units. |
| 52 | */ |
Alex Deucher | 4543eda | 2013-08-07 19:34:53 -0400 | [diff] [blame] | 53 | void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) |
Alex Deucher | 34be8c9 | 2013-07-18 11:13:53 -0400 | [diff] [blame] | 54 | { |
| 55 | #ifdef __BIG_ENDIAN |
| 56 | u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */ |
| 57 | u32 *dst32, *src32; |
| 58 | int i; |
| 59 | |
| 60 | memcpy(src_tmp, src, num_bytes); |
| 61 | src32 = (u32 *)src_tmp; |
| 62 | dst32 = (u32 *)dst_tmp; |
| 63 | if (to_le) { |
| 64 | for (i = 0; i < ((num_bytes + 3) / 4); i++) |
| 65 | dst32[i] = cpu_to_le32(src32[i]); |
| 66 | memcpy(dst, dst_tmp, num_bytes); |
| 67 | } else { |
| 68 | u8 dws = num_bytes & ~3; |
| 69 | for (i = 0; i < ((num_bytes + 3) / 4); i++) |
| 70 | dst32[i] = le32_to_cpu(src32[i]); |
| 71 | memcpy(dst, dst_tmp, dws); |
| 72 | if (num_bytes % 4) { |
| 73 | for (i = 0; i < (num_bytes % 4); i++) |
| 74 | dst[dws+i] = dst_tmp[dws+i]; |
| 75 | } |
| 76 | } |
| 77 | #else |
| 78 | memcpy(dst, src, num_bytes); |
| 79 | #endif |
| 80 | } |
| 81 | |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 82 | union aux_channel_transaction { |
| 83 | PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1; |
| 84 | PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2; |
| 85 | }; |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 86 | |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 87 | static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, |
| 88 | u8 *send, int send_bytes, |
| 89 | u8 *recv, int recv_size, |
| 90 | u8 delay, u8 *ack) |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 91 | { |
| 92 | struct drm_device *dev = chan->dev; |
| 93 | struct radeon_device *rdev = dev->dev_private; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 94 | union aux_channel_transaction args; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 95 | int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction); |
| 96 | unsigned char *base; |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 97 | int recv_bytes; |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 98 | |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 99 | memset(&args, 0, sizeof(args)); |
Alex Deucher | 1a66c95 | 2009-11-20 19:40:13 -0500 | [diff] [blame] | 100 | |
Alex Deucher | 97412a7 | 2012-03-20 17:18:06 -0400 | [diff] [blame] | 101 | base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1); |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 102 | |
Alex Deucher | 4543eda | 2013-08-07 19:34:53 -0400 | [diff] [blame] | 103 | radeon_atom_copy_swap(base, send, send_bytes, true); |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 104 | |
Alex Deucher | 34be8c9 | 2013-07-18 11:13:53 -0400 | [diff] [blame] | 105 | args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4)); |
| 106 | args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4)); |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 107 | args.v1.ucDataOutLen = 0; |
| 108 | args.v1.ucChannelID = chan->rec.i2c_id; |
| 109 | args.v1.ucDelay = delay / 10; |
| 110 | if (ASIC_IS_DCE4(rdev)) |
Alex Deucher | 8e36ed0 | 2010-05-18 19:26:47 -0400 | [diff] [blame] | 111 | args.v2.ucHPD_ID = chan->rec.hpd; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 112 | |
| 113 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 114 | |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 115 | *ack = args.v1.ucReplyStatus; |
| 116 | |
| 117 | /* timeout */ |
| 118 | if (args.v1.ucReplyStatus == 1) { |
| 119 | DRM_DEBUG_KMS("dp_aux_ch timeout\n"); |
| 120 | return -ETIMEDOUT; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 121 | } |
| 122 | |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 123 | /* flags not zero */ |
| 124 | if (args.v1.ucReplyStatus == 2) { |
| 125 | DRM_DEBUG_KMS("dp_aux_ch flags not zero\n"); |
| 126 | return -EBUSY; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 127 | } |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 128 | |
| 129 | /* error */ |
| 130 | if (args.v1.ucReplyStatus == 3) { |
| 131 | DRM_DEBUG_KMS("dp_aux_ch error\n"); |
| 132 | return -EIO; |
| 133 | } |
| 134 | |
| 135 | recv_bytes = args.v1.ucDataOutLen; |
| 136 | if (recv_bytes > recv_size) |
| 137 | recv_bytes = recv_size; |
| 138 | |
| 139 | if (recv && recv_size) |
Alex Deucher | 4543eda | 2013-08-07 19:34:53 -0400 | [diff] [blame] | 140 | radeon_atom_copy_swap(recv, base + 16, recv_bytes, false); |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 141 | |
| 142 | return recv_bytes; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 143 | } |
| 144 | |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 145 | static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, |
| 146 | u16 address, u8 *send, u8 send_bytes, u8 delay) |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 147 | { |
| 148 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 149 | int ret; |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 150 | u8 msg[20]; |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 151 | int msg_bytes = send_bytes + 4; |
| 152 | u8 ack; |
Alex Deucher | 6375bda | 2011-10-03 09:13:46 -0400 | [diff] [blame] | 153 | unsigned retry; |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 154 | |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 155 | if (send_bytes > 16) |
| 156 | return -1; |
| 157 | |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 158 | msg[0] = address; |
| 159 | msg[1] = address >> 8; |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 160 | msg[2] = DP_AUX_NATIVE_WRITE << 4; |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 161 | msg[3] = (msg_bytes << 4) | (send_bytes - 1); |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 162 | memcpy(&msg[4], send, send_bytes); |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 163 | |
Alex Deucher | 2138681 | 2014-01-14 10:29:59 -0500 | [diff] [blame] | 164 | for (retry = 0; retry < 7; retry++) { |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 165 | ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, |
| 166 | msg, msg_bytes, NULL, 0, delay, &ack); |
Alex Deucher | 4f33284 | 2011-10-04 17:23:15 -0400 | [diff] [blame] | 167 | if (ret == -EBUSY) |
| 168 | continue; |
| 169 | else if (ret < 0) |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 170 | return ret; |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 171 | ack >>= 4; |
| 172 | if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) |
Alex Deucher | 6375bda | 2011-10-03 09:13:46 -0400 | [diff] [blame] | 173 | return send_bytes; |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 174 | else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) |
Alex Deucher | ab9f51c | 2014-01-14 10:37:33 -0500 | [diff] [blame] | 175 | usleep_range(400, 500); |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 176 | else |
| 177 | return -EIO; |
| 178 | } |
| 179 | |
Alex Deucher | 6375bda | 2011-10-03 09:13:46 -0400 | [diff] [blame] | 180 | return -EIO; |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 181 | } |
| 182 | |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 183 | static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, |
| 184 | u16 address, u8 *recv, int recv_bytes, u8 delay) |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 185 | { |
| 186 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 187 | u8 msg[4]; |
| 188 | int msg_bytes = 4; |
| 189 | u8 ack; |
| 190 | int ret; |
Alex Deucher | 6375bda | 2011-10-03 09:13:46 -0400 | [diff] [blame] | 191 | unsigned retry; |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 192 | |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 193 | msg[0] = address; |
| 194 | msg[1] = address >> 8; |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 195 | msg[2] = DP_AUX_NATIVE_READ << 4; |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 196 | msg[3] = (msg_bytes << 4) | (recv_bytes - 1); |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 197 | |
Alex Deucher | 2138681 | 2014-01-14 10:29:59 -0500 | [diff] [blame] | 198 | for (retry = 0; retry < 7; retry++) { |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 199 | ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, |
| 200 | msg, msg_bytes, recv, recv_bytes, delay, &ack); |
Alex Deucher | 4f33284 | 2011-10-04 17:23:15 -0400 | [diff] [blame] | 201 | if (ret == -EBUSY) |
| 202 | continue; |
| 203 | else if (ret < 0) |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 204 | return ret; |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 205 | ack >>= 4; |
| 206 | if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 207 | return ret; |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 208 | else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER) |
Alex Deucher | ab9f51c | 2014-01-14 10:37:33 -0500 | [diff] [blame] | 209 | usleep_range(400, 500); |
Alex Deucher | 109bc10 | 2011-10-03 09:13:45 -0400 | [diff] [blame] | 210 | else if (ret == 0) |
| 211 | return -EPROTO; |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 212 | else |
| 213 | return -EIO; |
| 214 | } |
Alex Deucher | 6375bda | 2011-10-03 09:13:46 -0400 | [diff] [blame] | 215 | |
| 216 | return -EIO; |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 217 | } |
| 218 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 219 | static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector, |
| 220 | u16 reg, u8 val) |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 221 | { |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 222 | radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0); |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 223 | } |
| 224 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 225 | static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector, |
| 226 | u16 reg) |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 227 | { |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 228 | u8 val = 0; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 229 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 230 | radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0); |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 231 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 232 | return val; |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 233 | } |
| 234 | |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 235 | int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 236 | u8 write_byte, u8 *read_byte) |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 237 | { |
| 238 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
Alex Deucher | f3381df | 2014-03-17 23:48:14 -0400 | [diff] [blame] | 239 | struct radeon_i2c_chan *auxch = i2c_get_adapdata(adapter); |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 240 | u16 address = algo_data->address; |
| 241 | u8 msg[5]; |
| 242 | u8 reply[2]; |
| 243 | unsigned retry; |
| 244 | int msg_bytes; |
| 245 | int reply_bytes = 1; |
| 246 | int ret; |
| 247 | u8 ack; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 248 | |
| 249 | /* Set up the command byte */ |
| 250 | if (mode & MODE_I2C_READ) |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 251 | msg[2] = DP_AUX_I2C_READ << 4; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 252 | else |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 253 | msg[2] = DP_AUX_I2C_WRITE << 4; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 254 | |
| 255 | if (!(mode & MODE_I2C_STOP)) |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 256 | msg[2] |= DP_AUX_I2C_MOT << 4; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 257 | |
| 258 | msg[0] = address; |
| 259 | msg[1] = address >> 8; |
| 260 | |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 261 | switch (mode) { |
| 262 | case MODE_I2C_WRITE: |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 263 | msg_bytes = 5; |
| 264 | msg[3] = msg_bytes << 4; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 265 | msg[4] = write_byte; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 266 | break; |
| 267 | case MODE_I2C_READ: |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 268 | msg_bytes = 4; |
| 269 | msg[3] = msg_bytes << 4; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 270 | break; |
| 271 | default: |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 272 | msg_bytes = 4; |
| 273 | msg[3] = 3 << 4; |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 274 | break; |
| 275 | } |
| 276 | |
Alex Deucher | 2138681 | 2014-01-14 10:29:59 -0500 | [diff] [blame] | 277 | for (retry = 0; retry < 7; retry++) { |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 278 | ret = radeon_process_aux_ch(auxch, |
| 279 | msg, msg_bytes, reply, reply_bytes, 0, &ack); |
Alex Deucher | 4f33284 | 2011-10-04 17:23:15 -0400 | [diff] [blame] | 280 | if (ret == -EBUSY) |
| 281 | continue; |
| 282 | else if (ret < 0) { |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 283 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
| 284 | return ret; |
| 285 | } |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 286 | |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 287 | switch ((ack >> 4) & DP_AUX_NATIVE_REPLY_MASK) { |
| 288 | case DP_AUX_NATIVE_REPLY_ACK: |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 289 | /* I2C-over-AUX Reply field is only valid |
| 290 | * when paired with AUX ACK. |
| 291 | */ |
| 292 | break; |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 293 | case DP_AUX_NATIVE_REPLY_NACK: |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 294 | DRM_DEBUG_KMS("aux_ch native nack\n"); |
| 295 | return -EREMOTEIO; |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 296 | case DP_AUX_NATIVE_REPLY_DEFER: |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 297 | DRM_DEBUG_KMS("aux_ch native defer\n"); |
Alex Deucher | ab9f51c | 2014-01-14 10:37:33 -0500 | [diff] [blame] | 298 | usleep_range(500, 600); |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 299 | continue; |
| 300 | default: |
| 301 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack); |
| 302 | return -EREMOTEIO; |
| 303 | } |
| 304 | |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 305 | switch ((ack >> 4) & DP_AUX_I2C_REPLY_MASK) { |
| 306 | case DP_AUX_I2C_REPLY_ACK: |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 307 | if (mode == MODE_I2C_READ) |
| 308 | *read_byte = reply[0]; |
| 309 | return ret; |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 310 | case DP_AUX_I2C_REPLY_NACK: |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 311 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
| 312 | return -EREMOTEIO; |
Thierry Reding | 6b27f7f | 2013-12-16 17:01:29 +0100 | [diff] [blame] | 313 | case DP_AUX_I2C_REPLY_DEFER: |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 314 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
Alex Deucher | ab9f51c | 2014-01-14 10:37:33 -0500 | [diff] [blame] | 315 | usleep_range(400, 500); |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 316 | break; |
| 317 | default: |
| 318 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack); |
| 319 | return -EREMOTEIO; |
| 320 | } |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 321 | } |
Alex Deucher | 834b290 | 2011-05-20 04:34:24 -0400 | [diff] [blame] | 322 | |
Alex Deucher | 091264f | 2011-11-08 10:09:58 -0500 | [diff] [blame] | 323 | DRM_DEBUG_KMS("aux i2c too many retries, giving up\n"); |
Dave Airlie | 746c1aa | 2009-12-08 07:07:28 +1000 | [diff] [blame] | 324 | return -EREMOTEIO; |
| 325 | } |
Alex Deucher | 5801ead | 2009-11-24 13:32:59 -0500 | [diff] [blame] | 326 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 327 | /***** general DP utility functions *****/ |
| 328 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 329 | #define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 |
| 330 | #define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5 |
| 331 | |
| 332 | static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], |
| 333 | int lane_count, |
| 334 | u8 train_set[4]) |
| 335 | { |
| 336 | u8 v = 0; |
| 337 | u8 p = 0; |
| 338 | int lane; |
| 339 | |
| 340 | for (lane = 0; lane < lane_count; lane++) { |
Daniel Vetter | 0f037bd | 2012-10-18 10:15:27 +0200 | [diff] [blame] | 341 | u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
| 342 | u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 343 | |
| 344 | DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n", |
| 345 | lane, |
| 346 | voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
| 347 | pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); |
| 348 | |
| 349 | if (this_v > v) |
| 350 | v = this_v; |
| 351 | if (this_p > p) |
| 352 | p = this_p; |
| 353 | } |
| 354 | |
| 355 | if (v >= DP_VOLTAGE_MAX) |
| 356 | v |= DP_TRAIN_MAX_SWING_REACHED; |
| 357 | |
| 358 | if (p >= DP_PRE_EMPHASIS_MAX) |
| 359 | p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
| 360 | |
| 361 | DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n", |
| 362 | voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT], |
| 363 | pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); |
| 364 | |
| 365 | for (lane = 0; lane < 4; lane++) |
| 366 | train_set[lane] = v | p; |
| 367 | } |
| 368 | |
| 369 | /* convert bits per color to bits per pixel */ |
| 370 | /* get bpc from the EDID */ |
| 371 | static int convert_bpc_to_bpp(int bpc) |
| 372 | { |
| 373 | if (bpc == 0) |
| 374 | return 24; |
| 375 | else |
| 376 | return bpc * 3; |
| 377 | } |
| 378 | |
| 379 | /* get the max pix clock supported by the link rate and lane num */ |
| 380 | static int dp_get_max_dp_pix_clock(int link_rate, |
| 381 | int lane_num, |
| 382 | int bpp) |
| 383 | { |
| 384 | return (link_rate * lane_num * 8) / bpp; |
| 385 | } |
| 386 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 387 | /***** radeon specific DP functions *****/ |
| 388 | |
| 389 | /* First get the min lane# when low rate is used according to pixel clock |
| 390 | * (prefer low rate), second check max lane# supported by DP panel, |
| 391 | * if the max lane# < low rate lane# then use max lane# instead. |
| 392 | */ |
| 393 | static int radeon_dp_get_dp_lane_number(struct drm_connector *connector, |
| 394 | u8 dpcd[DP_DPCD_SIZE], |
| 395 | int pix_clock) |
| 396 | { |
Alex Deucher | eccea79 | 2012-03-26 15:12:54 -0400 | [diff] [blame] | 397 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
Daniel Vetter | 3b5c662 | 2012-10-18 10:15:31 +0200 | [diff] [blame] | 398 | int max_link_rate = drm_dp_max_link_rate(dpcd); |
Daniel Vetter | 397fe15 | 2012-10-22 22:56:43 +0200 | [diff] [blame] | 399 | int max_lane_num = drm_dp_max_lane_count(dpcd); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 400 | int lane_num; |
| 401 | int max_dp_pix_clock; |
| 402 | |
| 403 | for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) { |
| 404 | max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp); |
| 405 | if (pix_clock <= max_dp_pix_clock) |
| 406 | break; |
| 407 | } |
| 408 | |
| 409 | return lane_num; |
| 410 | } |
| 411 | |
| 412 | static int radeon_dp_get_dp_link_clock(struct drm_connector *connector, |
| 413 | u8 dpcd[DP_DPCD_SIZE], |
| 414 | int pix_clock) |
| 415 | { |
Alex Deucher | eccea79 | 2012-03-26 15:12:54 -0400 | [diff] [blame] | 416 | int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 417 | int lane_num, max_pix_clock; |
| 418 | |
Alex Deucher | fdca78c | 2011-10-25 11:54:52 -0400 | [diff] [blame] | 419 | if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) == |
| 420 | ENCODER_OBJECT_ID_NUTMEG) |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 421 | return 270000; |
| 422 | |
| 423 | lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock); |
| 424 | max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp); |
| 425 | if (pix_clock <= max_pix_clock) |
| 426 | return 162000; |
| 427 | max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp); |
| 428 | if (pix_clock <= max_pix_clock) |
| 429 | return 270000; |
| 430 | if (radeon_connector_is_dp12_capable(connector)) { |
| 431 | max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp); |
| 432 | if (pix_clock <= max_pix_clock) |
| 433 | return 540000; |
| 434 | } |
| 435 | |
Daniel Vetter | 3b5c662 | 2012-10-18 10:15:31 +0200 | [diff] [blame] | 436 | return drm_dp_max_link_rate(dpcd); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 437 | } |
| 438 | |
| 439 | static u8 radeon_dp_encoder_service(struct radeon_device *rdev, |
| 440 | int action, int dp_clock, |
| 441 | u8 ucconfig, u8 lane_num) |
| 442 | { |
| 443 | DP_ENCODER_SERVICE_PARAMETERS args; |
| 444 | int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); |
| 445 | |
| 446 | memset(&args, 0, sizeof(args)); |
| 447 | args.ucLinkClock = dp_clock / 10; |
| 448 | args.ucConfig = ucconfig; |
| 449 | args.ucAction = action; |
| 450 | args.ucLaneNum = lane_num; |
| 451 | args.ucStatus = 0; |
| 452 | |
| 453 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
| 454 | return args.ucStatus; |
| 455 | } |
| 456 | |
| 457 | u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector) |
| 458 | { |
| 459 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
| 460 | struct drm_device *dev = radeon_connector->base.dev; |
| 461 | struct radeon_device *rdev = dev->dev_private; |
| 462 | |
| 463 | return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0, |
| 464 | dig_connector->dp_i2c_bus->rec.i2c_id, 0); |
| 465 | } |
| 466 | |
Adam Jackson | 40c5d87 | 2012-05-14 16:05:48 -0400 | [diff] [blame] | 467 | static void radeon_dp_probe_oui(struct radeon_connector *radeon_connector) |
| 468 | { |
| 469 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
| 470 | u8 buf[3]; |
| 471 | |
| 472 | if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
| 473 | return; |
| 474 | |
| 475 | if (radeon_dp_aux_native_read(radeon_connector, DP_SINK_OUI, buf, 3, 0)) |
| 476 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
| 477 | buf[0], buf[1], buf[2]); |
| 478 | |
| 479 | if (radeon_dp_aux_native_read(radeon_connector, DP_BRANCH_OUI, buf, 3, 0)) |
| 480 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
| 481 | buf[0], buf[1], buf[2]); |
| 482 | } |
| 483 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 484 | bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector) |
| 485 | { |
| 486 | struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; |
Daniel Vetter | 1a644cd | 2012-10-18 15:32:40 +0200 | [diff] [blame] | 487 | u8 msg[DP_DPCD_SIZE]; |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 488 | int ret, i; |
| 489 | |
Daniel Vetter | 1a644cd | 2012-10-18 15:32:40 +0200 | [diff] [blame] | 490 | ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg, |
| 491 | DP_DPCD_SIZE, 0); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 492 | if (ret > 0) { |
Daniel Vetter | 1a644cd | 2012-10-18 15:32:40 +0200 | [diff] [blame] | 493 | memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 494 | DRM_DEBUG_KMS("DPCD: "); |
Daniel Vetter | 1a644cd | 2012-10-18 15:32:40 +0200 | [diff] [blame] | 495 | for (i = 0; i < DP_DPCD_SIZE; i++) |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 496 | DRM_DEBUG_KMS("%02x ", msg[i]); |
| 497 | DRM_DEBUG_KMS("\n"); |
Adam Jackson | 40c5d87 | 2012-05-14 16:05:48 -0400 | [diff] [blame] | 498 | |
| 499 | radeon_dp_probe_oui(radeon_connector); |
| 500 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 501 | return true; |
| 502 | } |
| 503 | dig_connector->dpcd[0] = 0; |
| 504 | return false; |
| 505 | } |
| 506 | |
Alex Deucher | 386d4d7 | 2012-01-20 15:01:29 -0500 | [diff] [blame] | 507 | int radeon_dp_get_panel_mode(struct drm_encoder *encoder, |
| 508 | struct drm_connector *connector) |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 509 | { |
| 510 | struct drm_device *dev = encoder->dev; |
| 511 | struct radeon_device *rdev = dev->dev_private; |
Alex Deucher | 00dfb8d | 2011-10-31 08:54:41 -0400 | [diff] [blame] | 512 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 513 | int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
Alex Deucher | 0ceb996 | 2012-08-27 17:48:18 -0400 | [diff] [blame] | 514 | u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector); |
| 515 | u8 tmp; |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 516 | |
| 517 | if (!ASIC_IS_DCE4(rdev)) |
Alex Deucher | 386d4d7 | 2012-01-20 15:01:29 -0500 | [diff] [blame] | 518 | return panel_mode; |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 519 | |
Alex Deucher | 0ceb996 | 2012-08-27 17:48:18 -0400 | [diff] [blame] | 520 | if (dp_bridge != ENCODER_OBJECT_ID_NONE) { |
| 521 | /* DP bridge chips */ |
| 522 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); |
| 523 | if (tmp & 1) |
| 524 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; |
| 525 | else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) || |
| 526 | (dp_bridge == ENCODER_OBJECT_ID_TRAVIS)) |
Alex Deucher | 304a484 | 2012-02-02 10:18:00 -0500 | [diff] [blame] | 527 | panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE; |
| 528 | else |
Alex Deucher | 0ceb996 | 2012-08-27 17:48:18 -0400 | [diff] [blame] | 529 | panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE; |
Alex Deucher | 304a484 | 2012-02-02 10:18:00 -0500 | [diff] [blame] | 530 | } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { |
Alex Deucher | 0ceb996 | 2012-08-27 17:48:18 -0400 | [diff] [blame] | 531 | /* eDP */ |
| 532 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP); |
Alex Deucher | 00dfb8d | 2011-10-31 08:54:41 -0400 | [diff] [blame] | 533 | if (tmp & 1) |
| 534 | panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE; |
| 535 | } |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 536 | |
Alex Deucher | 386d4d7 | 2012-01-20 15:01:29 -0500 | [diff] [blame] | 537 | return panel_mode; |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 538 | } |
| 539 | |
| 540 | void radeon_dp_set_link_config(struct drm_connector *connector, |
Laurent Pinchart | e811f5a | 2012-07-17 17:56:50 +0200 | [diff] [blame] | 541 | const struct drm_display_mode *mode) |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 542 | { |
| 543 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 544 | struct radeon_connector_atom_dig *dig_connector; |
| 545 | |
| 546 | if (!radeon_connector->con_priv) |
| 547 | return; |
| 548 | dig_connector = radeon_connector->con_priv; |
| 549 | |
| 550 | if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || |
| 551 | (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { |
| 552 | dig_connector->dp_clock = |
| 553 | radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); |
| 554 | dig_connector->dp_lane_count = |
| 555 | radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock); |
| 556 | } |
| 557 | } |
| 558 | |
| 559 | int radeon_dp_mode_valid_helper(struct drm_connector *connector, |
| 560 | struct drm_display_mode *mode) |
| 561 | { |
| 562 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 563 | struct radeon_connector_atom_dig *dig_connector; |
| 564 | int dp_clock; |
| 565 | |
| 566 | if (!radeon_connector->con_priv) |
| 567 | return MODE_CLOCK_HIGH; |
| 568 | dig_connector = radeon_connector->con_priv; |
| 569 | |
| 570 | dp_clock = |
| 571 | radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock); |
| 572 | |
| 573 | if ((dp_clock == 540000) && |
| 574 | (!radeon_connector_is_dp12_capable(connector))) |
| 575 | return MODE_CLOCK_HIGH; |
| 576 | |
| 577 | return MODE_OK; |
| 578 | } |
| 579 | |
| 580 | static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector, |
| 581 | u8 link_status[DP_LINK_STATUS_SIZE]) |
| 582 | { |
| 583 | int ret; |
| 584 | ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, |
| 585 | link_status, DP_LINK_STATUS_SIZE, 100); |
| 586 | if (ret <= 0) { |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 587 | return false; |
| 588 | } |
| 589 | |
Andy Shevchenko | 08fcd72 | 2013-08-02 14:09:24 +0300 | [diff] [blame] | 590 | DRM_DEBUG_KMS("link status %6ph\n", link_status); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 591 | return true; |
| 592 | } |
| 593 | |
Alex Deucher | d5811e8 | 2011-08-13 13:36:13 -0400 | [diff] [blame] | 594 | bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector) |
| 595 | { |
| 596 | u8 link_status[DP_LINK_STATUS_SIZE]; |
| 597 | struct radeon_connector_atom_dig *dig = radeon_connector->con_priv; |
| 598 | |
| 599 | if (!radeon_dp_get_link_status(radeon_connector, link_status)) |
| 600 | return false; |
Daniel Vetter | 1ffdff1 | 2012-10-18 10:15:24 +0200 | [diff] [blame] | 601 | if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count)) |
Alex Deucher | d5811e8 | 2011-08-13 13:36:13 -0400 | [diff] [blame] | 602 | return false; |
| 603 | return true; |
| 604 | } |
| 605 | |
Alex Deucher | 2953da1 | 2014-03-17 23:48:15 -0400 | [diff] [blame^] | 606 | void radeon_dp_set_rx_power_state(struct drm_connector *connector, |
| 607 | u8 power_state) |
| 608 | { |
| 609 | struct radeon_connector *radeon_connector = to_radeon_connector(connector); |
| 610 | struct radeon_connector_atom_dig *dig_connector; |
| 611 | |
| 612 | if (!radeon_connector->con_priv) |
| 613 | return; |
| 614 | |
| 615 | dig_connector = radeon_connector->con_priv; |
| 616 | |
| 617 | /* power up/down the sink */ |
| 618 | if (dig_connector->dpcd[0] >= 0x11) { |
| 619 | radeon_write_dpcd_reg(radeon_connector, |
| 620 | DP_SET_POWER, power_state); |
| 621 | usleep_range(1000, 2000); |
| 622 | } |
| 623 | } |
| 624 | |
| 625 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 626 | struct radeon_dp_link_train_info { |
| 627 | struct radeon_device *rdev; |
| 628 | struct drm_encoder *encoder; |
| 629 | struct drm_connector *connector; |
| 630 | struct radeon_connector *radeon_connector; |
| 631 | int enc_id; |
| 632 | int dp_clock; |
| 633 | int dp_lane_count; |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 634 | bool tp3_supported; |
Daniel Vetter | 1a644cd | 2012-10-18 15:32:40 +0200 | [diff] [blame] | 635 | u8 dpcd[DP_RECEIVER_CAP_SIZE]; |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 636 | u8 train_set[4]; |
| 637 | u8 link_status[DP_LINK_STATUS_SIZE]; |
| 638 | u8 tries; |
Jerome Glisse | 5a96a89 | 2011-07-25 11:57:43 -0400 | [diff] [blame] | 639 | bool use_dpencoder; |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 640 | }; |
| 641 | |
| 642 | static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) |
| 643 | { |
| 644 | /* set the initial vs/emph on the source */ |
| 645 | atombios_dig_transmitter_setup(dp_info->encoder, |
| 646 | ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, |
| 647 | 0, dp_info->train_set[0]); /* sets all lanes at once */ |
| 648 | |
| 649 | /* set the vs/emph on the sink */ |
| 650 | radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET, |
| 651 | dp_info->train_set, dp_info->dp_lane_count, 0); |
| 652 | } |
| 653 | |
| 654 | static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp) |
| 655 | { |
| 656 | int rtp = 0; |
| 657 | |
| 658 | /* set training pattern on the source */ |
Jerome Glisse | 5a96a89 | 2011-07-25 11:57:43 -0400 | [diff] [blame] | 659 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) { |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 660 | switch (tp) { |
| 661 | case DP_TRAINING_PATTERN_1: |
| 662 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; |
| 663 | break; |
| 664 | case DP_TRAINING_PATTERN_2: |
| 665 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; |
| 666 | break; |
| 667 | case DP_TRAINING_PATTERN_3: |
| 668 | rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; |
| 669 | break; |
| 670 | } |
| 671 | atombios_dig_encoder_setup(dp_info->encoder, rtp, 0); |
| 672 | } else { |
| 673 | switch (tp) { |
| 674 | case DP_TRAINING_PATTERN_1: |
| 675 | rtp = 0; |
| 676 | break; |
| 677 | case DP_TRAINING_PATTERN_2: |
| 678 | rtp = 1; |
| 679 | break; |
| 680 | } |
| 681 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL, |
| 682 | dp_info->dp_clock, dp_info->enc_id, rtp); |
| 683 | } |
| 684 | |
| 685 | /* enable training pattern on the sink */ |
| 686 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp); |
| 687 | } |
| 688 | |
| 689 | static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) |
| 690 | { |
Alex Deucher | 386d4d7 | 2012-01-20 15:01:29 -0500 | [diff] [blame] | 691 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(dp_info->encoder); |
| 692 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 693 | u8 tmp; |
| 694 | |
| 695 | /* power up the sink */ |
Alex Deucher | 2953da1 | 2014-03-17 23:48:15 -0400 | [diff] [blame^] | 696 | radeon_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 697 | |
| 698 | /* possibly enable downspread on the sink */ |
| 699 | if (dp_info->dpcd[3] & 0x1) |
| 700 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
| 701 | DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5); |
| 702 | else |
| 703 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
| 704 | DP_DOWNSPREAD_CTRL, 0); |
| 705 | |
Alex Deucher | 386d4d7 | 2012-01-20 15:01:29 -0500 | [diff] [blame] | 706 | if ((dp_info->connector->connector_type == DRM_MODE_CONNECTOR_eDP) && |
| 707 | (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)) { |
| 708 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_EDP_CONFIGURATION_SET, 1); |
| 709 | } |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 710 | |
| 711 | /* set the lane count on the sink */ |
| 712 | tmp = dp_info->dp_lane_count; |
Jani Nikula | 27f75dc6 | 2013-10-04 15:08:09 +0300 | [diff] [blame] | 713 | if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 714 | tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
| 715 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp); |
| 716 | |
| 717 | /* set the link rate on the sink */ |
Daniel Vetter | 3b5c662 | 2012-10-18 10:15:31 +0200 | [diff] [blame] | 718 | tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 719 | radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp); |
| 720 | |
| 721 | /* start training on the source */ |
Jerome Glisse | 5a96a89 | 2011-07-25 11:57:43 -0400 | [diff] [blame] | 722 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 723 | atombios_dig_encoder_setup(dp_info->encoder, |
| 724 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0); |
| 725 | else |
| 726 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START, |
| 727 | dp_info->dp_clock, dp_info->enc_id, 0); |
| 728 | |
| 729 | /* disable the training pattern on the sink */ |
| 730 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
| 731 | DP_TRAINING_PATTERN_SET, |
| 732 | DP_TRAINING_PATTERN_DISABLE); |
| 733 | |
| 734 | return 0; |
| 735 | } |
| 736 | |
| 737 | static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info) |
| 738 | { |
| 739 | udelay(400); |
| 740 | |
| 741 | /* disable the training pattern on the sink */ |
| 742 | radeon_write_dpcd_reg(dp_info->radeon_connector, |
| 743 | DP_TRAINING_PATTERN_SET, |
| 744 | DP_TRAINING_PATTERN_DISABLE); |
| 745 | |
| 746 | /* disable the training pattern on the source */ |
Jerome Glisse | 5a96a89 | 2011-07-25 11:57:43 -0400 | [diff] [blame] | 747 | if (ASIC_IS_DCE4(dp_info->rdev) || !dp_info->use_dpencoder) |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 748 | atombios_dig_encoder_setup(dp_info->encoder, |
| 749 | ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0); |
| 750 | else |
| 751 | radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE, |
| 752 | dp_info->dp_clock, dp_info->enc_id, 0); |
| 753 | |
| 754 | return 0; |
| 755 | } |
| 756 | |
| 757 | static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info) |
| 758 | { |
| 759 | bool clock_recovery; |
| 760 | u8 voltage; |
| 761 | int i; |
| 762 | |
| 763 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1); |
| 764 | memset(dp_info->train_set, 0, 4); |
| 765 | radeon_dp_update_vs_emph(dp_info); |
| 766 | |
| 767 | udelay(400); |
| 768 | |
| 769 | /* clock recovery loop */ |
| 770 | clock_recovery = false; |
| 771 | dp_info->tries = 0; |
| 772 | voltage = 0xff; |
| 773 | while (1) { |
Daniel Vetter | 1a644cd | 2012-10-18 15:32:40 +0200 | [diff] [blame] | 774 | drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 775 | |
Jerome Glisse | 8d1c702 | 2012-07-17 17:17:16 -0400 | [diff] [blame] | 776 | if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { |
| 777 | DRM_ERROR("displayport link status failed\n"); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 778 | break; |
Jerome Glisse | 8d1c702 | 2012-07-17 17:17:16 -0400 | [diff] [blame] | 779 | } |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 780 | |
Daniel Vetter | 0191627 | 2012-10-18 10:15:25 +0200 | [diff] [blame] | 781 | if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 782 | clock_recovery = true; |
| 783 | break; |
| 784 | } |
| 785 | |
| 786 | for (i = 0; i < dp_info->dp_lane_count; i++) { |
| 787 | if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
| 788 | break; |
| 789 | } |
| 790 | if (i == dp_info->dp_lane_count) { |
| 791 | DRM_ERROR("clock recovery reached max voltage\n"); |
| 792 | break; |
| 793 | } |
| 794 | |
| 795 | if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
| 796 | ++dp_info->tries; |
| 797 | if (dp_info->tries == 5) { |
| 798 | DRM_ERROR("clock recovery tried 5 times\n"); |
| 799 | break; |
| 800 | } |
| 801 | } else |
| 802 | dp_info->tries = 0; |
| 803 | |
| 804 | voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
| 805 | |
| 806 | /* Compute new train_set as requested by sink */ |
| 807 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
| 808 | |
| 809 | radeon_dp_update_vs_emph(dp_info); |
| 810 | } |
| 811 | if (!clock_recovery) { |
| 812 | DRM_ERROR("clock recovery failed\n"); |
| 813 | return -1; |
| 814 | } else { |
| 815 | DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n", |
| 816 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
| 817 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> |
| 818 | DP_TRAIN_PRE_EMPHASIS_SHIFT); |
| 819 | return 0; |
| 820 | } |
| 821 | } |
| 822 | |
| 823 | static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info) |
| 824 | { |
| 825 | bool channel_eq; |
| 826 | |
| 827 | if (dp_info->tp3_supported) |
| 828 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3); |
| 829 | else |
| 830 | radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2); |
| 831 | |
| 832 | /* channel equalization loop */ |
| 833 | dp_info->tries = 0; |
| 834 | channel_eq = false; |
| 835 | while (1) { |
Daniel Vetter | 1a644cd | 2012-10-18 15:32:40 +0200 | [diff] [blame] | 836 | drm_dp_link_train_channel_eq_delay(dp_info->dpcd); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 837 | |
Jerome Glisse | 8d1c702 | 2012-07-17 17:17:16 -0400 | [diff] [blame] | 838 | if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status)) { |
| 839 | DRM_ERROR("displayport link status failed\n"); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 840 | break; |
Jerome Glisse | 8d1c702 | 2012-07-17 17:17:16 -0400 | [diff] [blame] | 841 | } |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 842 | |
Daniel Vetter | 1ffdff1 | 2012-10-18 10:15:24 +0200 | [diff] [blame] | 843 | if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) { |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 844 | channel_eq = true; |
| 845 | break; |
| 846 | } |
| 847 | |
| 848 | /* Try 5 times */ |
| 849 | if (dp_info->tries > 5) { |
| 850 | DRM_ERROR("channel eq failed: 5 tries\n"); |
| 851 | break; |
| 852 | } |
| 853 | |
| 854 | /* Compute new train_set as requested by sink */ |
| 855 | dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); |
| 856 | |
| 857 | radeon_dp_update_vs_emph(dp_info); |
| 858 | dp_info->tries++; |
| 859 | } |
| 860 | |
| 861 | if (!channel_eq) { |
| 862 | DRM_ERROR("channel eq failed\n"); |
| 863 | return -1; |
| 864 | } else { |
| 865 | DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n", |
| 866 | dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK, |
| 867 | (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) |
| 868 | >> DP_TRAIN_PRE_EMPHASIS_SHIFT); |
| 869 | return 0; |
| 870 | } |
| 871 | } |
| 872 | |
| 873 | void radeon_dp_link_train(struct drm_encoder *encoder, |
| 874 | struct drm_connector *connector) |
| 875 | { |
| 876 | struct drm_device *dev = encoder->dev; |
| 877 | struct radeon_device *rdev = dev->dev_private; |
| 878 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
| 879 | struct radeon_encoder_atom_dig *dig; |
| 880 | struct radeon_connector *radeon_connector; |
| 881 | struct radeon_connector_atom_dig *dig_connector; |
| 882 | struct radeon_dp_link_train_info dp_info; |
Jerome Glisse | 5a96a89 | 2011-07-25 11:57:43 -0400 | [diff] [blame] | 883 | int index; |
| 884 | u8 tmp, frev, crev; |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 885 | |
| 886 | if (!radeon_encoder->enc_priv) |
| 887 | return; |
| 888 | dig = radeon_encoder->enc_priv; |
| 889 | |
| 890 | radeon_connector = to_radeon_connector(connector); |
| 891 | if (!radeon_connector->con_priv) |
| 892 | return; |
| 893 | dig_connector = radeon_connector->con_priv; |
| 894 | |
| 895 | if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) && |
| 896 | (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP)) |
| 897 | return; |
| 898 | |
Jerome Glisse | 5a96a89 | 2011-07-25 11:57:43 -0400 | [diff] [blame] | 899 | /* DPEncoderService newer than 1.1 can't program properly the |
| 900 | * training pattern. When facing such version use the |
| 901 | * DIGXEncoderControl (X== 1 | 2) |
| 902 | */ |
| 903 | dp_info.use_dpencoder = true; |
| 904 | index = GetIndexIntoMasterTable(COMMAND, DPEncoderService); |
| 905 | if (atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) { |
| 906 | if (crev > 1) { |
| 907 | dp_info.use_dpencoder = false; |
| 908 | } |
| 909 | } |
| 910 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 911 | dp_info.enc_id = 0; |
| 912 | if (dig->dig_encoder) |
| 913 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER; |
| 914 | else |
| 915 | dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER; |
| 916 | if (dig->linkb) |
| 917 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B; |
| 918 | else |
| 919 | dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A; |
| 920 | |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 921 | tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT); |
| 922 | if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED)) |
| 923 | dp_info.tp3_supported = true; |
| 924 | else |
| 925 | dp_info.tp3_supported = false; |
| 926 | |
Daniel Vetter | 1a644cd | 2012-10-18 15:32:40 +0200 | [diff] [blame] | 927 | memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE); |
Alex Deucher | 224d94b | 2011-05-20 04:34:28 -0400 | [diff] [blame] | 928 | dp_info.rdev = rdev; |
| 929 | dp_info.encoder = encoder; |
| 930 | dp_info.connector = connector; |
| 931 | dp_info.radeon_connector = radeon_connector; |
| 932 | dp_info.dp_lane_count = dig_connector->dp_lane_count; |
| 933 | dp_info.dp_clock = dig_connector->dp_clock; |
| 934 | |
| 935 | if (radeon_dp_link_train_init(&dp_info)) |
| 936 | goto done; |
| 937 | if (radeon_dp_link_train_cr(&dp_info)) |
| 938 | goto done; |
| 939 | if (radeon_dp_link_train_ce(&dp_info)) |
| 940 | goto done; |
| 941 | done: |
| 942 | if (radeon_dp_link_train_finish(&dp_info)) |
| 943 | return; |
| 944 | } |