Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1 | /* |
| 2 | * OMAP3 clock framework |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2007-2008 Nokia Corporation |
| 6 | * |
| 7 | * Written by Paul Walmsley |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 8 | * With many device clock fixes by Kevin Hilman and Jouni Högander |
| 9 | * DPLL bypass clock support added by Roman Tereshonkov |
| 10 | * |
| 11 | */ |
| 12 | |
| 13 | /* |
| 14 | * Virtual clocks are introduced as convenient tools. |
| 15 | * They are sources for other clocks and not supposed |
| 16 | * to be requested from drivers directly. |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 17 | */ |
| 18 | |
| 19 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H |
| 20 | #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H |
| 21 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 22 | #include <mach/control.h> |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 23 | |
| 24 | #include "clock.h" |
| 25 | #include "cm.h" |
| 26 | #include "cm-regbits-34xx.h" |
| 27 | #include "prm.h" |
| 28 | #include "prm-regbits-34xx.h" |
| 29 | |
| 30 | static void omap3_dpll_recalc(struct clk *clk); |
| 31 | static void omap3_clkoutx2_recalc(struct clk *clk); |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 32 | static void omap3_dpll_allow_idle(struct clk *clk); |
| 33 | static void omap3_dpll_deny_idle(struct clk *clk); |
| 34 | static u32 omap3_dpll_autoidle_read(struct clk *clk); |
Paul Walmsley | 16c90f0 | 2009-01-27 19:12:47 -0700 | [diff] [blame] | 35 | static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); |
| 36 | static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 37 | |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 38 | /* Maximum DPLL multiplier, divider values for OMAP3 */ |
| 39 | #define OMAP3_MAX_DPLL_MULT 2048 |
| 40 | #define OMAP3_MAX_DPLL_DIV 128 |
| 41 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 42 | /* |
| 43 | * DPLL1 supplies clock to the MPU. |
| 44 | * DPLL2 supplies clock to the IVA2. |
| 45 | * DPLL3 supplies CORE domain clocks. |
| 46 | * DPLL4 supplies peripheral clocks. |
| 47 | * DPLL5 supplies other peripheral clocks (USBHOST, USIM). |
| 48 | */ |
| 49 | |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 50 | /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ |
| 51 | #define DPLL_LOW_POWER_STOP 0x1 |
| 52 | #define DPLL_LOW_POWER_BYPASS 0x5 |
| 53 | #define DPLL_LOCKED 0x7 |
| 54 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 55 | /* PRM CLOCKS */ |
| 56 | |
| 57 | /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ |
| 58 | static struct clk omap_32k_fck = { |
| 59 | .name = "omap_32k_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 60 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 61 | .rate = 32768, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 62 | .flags = RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 63 | }; |
| 64 | |
| 65 | static struct clk secure_32k_fck = { |
| 66 | .name = "secure_32k_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 67 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 68 | .rate = 32768, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 69 | .flags = RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 70 | }; |
| 71 | |
| 72 | /* Virtual source clocks for osc_sys_ck */ |
| 73 | static struct clk virt_12m_ck = { |
| 74 | .name = "virt_12m_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 75 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 76 | .rate = 12000000, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 77 | .flags = RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 78 | }; |
| 79 | |
| 80 | static struct clk virt_13m_ck = { |
| 81 | .name = "virt_13m_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 82 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 83 | .rate = 13000000, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 84 | .flags = RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 85 | }; |
| 86 | |
| 87 | static struct clk virt_16_8m_ck = { |
| 88 | .name = "virt_16_8m_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 89 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 90 | .rate = 16800000, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 91 | .flags = RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 92 | }; |
| 93 | |
| 94 | static struct clk virt_19_2m_ck = { |
| 95 | .name = "virt_19_2m_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 96 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 97 | .rate = 19200000, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 98 | .flags = RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 99 | }; |
| 100 | |
| 101 | static struct clk virt_26m_ck = { |
| 102 | .name = "virt_26m_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 103 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 104 | .rate = 26000000, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 105 | .flags = RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 106 | }; |
| 107 | |
| 108 | static struct clk virt_38_4m_ck = { |
| 109 | .name = "virt_38_4m_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 110 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 111 | .rate = 38400000, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 112 | .flags = RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 113 | }; |
| 114 | |
| 115 | static const struct clksel_rate osc_sys_12m_rates[] = { |
| 116 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 117 | { .div = 0 } |
| 118 | }; |
| 119 | |
| 120 | static const struct clksel_rate osc_sys_13m_rates[] = { |
| 121 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 122 | { .div = 0 } |
| 123 | }; |
| 124 | |
| 125 | static const struct clksel_rate osc_sys_16_8m_rates[] = { |
| 126 | { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE }, |
| 127 | { .div = 0 } |
| 128 | }; |
| 129 | |
| 130 | static const struct clksel_rate osc_sys_19_2m_rates[] = { |
| 131 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 132 | { .div = 0 } |
| 133 | }; |
| 134 | |
| 135 | static const struct clksel_rate osc_sys_26m_rates[] = { |
| 136 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 137 | { .div = 0 } |
| 138 | }; |
| 139 | |
| 140 | static const struct clksel_rate osc_sys_38_4m_rates[] = { |
| 141 | { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 142 | { .div = 0 } |
| 143 | }; |
| 144 | |
| 145 | static const struct clksel osc_sys_clksel[] = { |
| 146 | { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates }, |
| 147 | { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates }, |
| 148 | { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates }, |
| 149 | { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates }, |
| 150 | { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates }, |
| 151 | { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates }, |
| 152 | { .parent = NULL }, |
| 153 | }; |
| 154 | |
| 155 | /* Oscillator clock */ |
| 156 | /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ |
| 157 | static struct clk osc_sys_ck = { |
| 158 | .name = "osc_sys_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 159 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 160 | .init = &omap2_init_clksel_parent, |
| 161 | .clksel_reg = OMAP3430_PRM_CLKSEL, |
| 162 | .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, |
| 163 | .clksel = osc_sys_clksel, |
| 164 | /* REVISIT: deal with autoextclkmode? */ |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 165 | .flags = RATE_FIXED | RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 166 | .recalc = &omap2_clksel_recalc, |
| 167 | }; |
| 168 | |
| 169 | static const struct clksel_rate div2_rates[] = { |
| 170 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 171 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, |
| 172 | { .div = 0 } |
| 173 | }; |
| 174 | |
| 175 | static const struct clksel sys_clksel[] = { |
| 176 | { .parent = &osc_sys_ck, .rates = div2_rates }, |
| 177 | { .parent = NULL } |
| 178 | }; |
| 179 | |
| 180 | /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */ |
| 181 | /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ |
| 182 | static struct clk sys_ck = { |
| 183 | .name = "sys_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 184 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 185 | .parent = &osc_sys_ck, |
| 186 | .init = &omap2_init_clksel_parent, |
| 187 | .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, |
| 188 | .clksel_mask = OMAP_SYSCLKDIV_MASK, |
| 189 | .clksel = sys_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 190 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 191 | .recalc = &omap2_clksel_recalc, |
| 192 | }; |
| 193 | |
| 194 | static struct clk sys_altclk = { |
| 195 | .name = "sys_altclk", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 196 | .ops = &clkops_null, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 197 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 198 | }; |
| 199 | |
| 200 | /* Optional external clock input for some McBSPs */ |
| 201 | static struct clk mcbsp_clks = { |
| 202 | .name = "mcbsp_clks", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 203 | .ops = &clkops_null, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 204 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 205 | }; |
| 206 | |
| 207 | /* PRM EXTERNAL CLOCK OUTPUT */ |
| 208 | |
| 209 | static struct clk sys_clkout1 = { |
| 210 | .name = "sys_clkout1", |
Russell King | c1168dc | 2008-11-04 21:24:00 +0000 | [diff] [blame] | 211 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 212 | .parent = &osc_sys_ck, |
| 213 | .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, |
| 214 | .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 215 | .recalc = &followparent_recalc, |
| 216 | }; |
| 217 | |
| 218 | /* DPLLS */ |
| 219 | |
| 220 | /* CM CLOCKS */ |
| 221 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 222 | static const struct clksel_rate dpll_bypass_rates[] = { |
| 223 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 224 | { .div = 0 } |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 225 | }; |
| 226 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 227 | static const struct clksel_rate dpll_locked_rates[] = { |
| 228 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 229 | { .div = 0 } |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 230 | }; |
| 231 | |
| 232 | static const struct clksel_rate div16_dpll_rates[] = { |
| 233 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 234 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, |
| 235 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, |
| 236 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, |
| 237 | { .div = 5, .val = 5, .flags = RATE_IN_343X }, |
| 238 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, |
| 239 | { .div = 7, .val = 7, .flags = RATE_IN_343X }, |
| 240 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, |
| 241 | { .div = 9, .val = 9, .flags = RATE_IN_343X }, |
| 242 | { .div = 10, .val = 10, .flags = RATE_IN_343X }, |
| 243 | { .div = 11, .val = 11, .flags = RATE_IN_343X }, |
| 244 | { .div = 12, .val = 12, .flags = RATE_IN_343X }, |
| 245 | { .div = 13, .val = 13, .flags = RATE_IN_343X }, |
| 246 | { .div = 14, .val = 14, .flags = RATE_IN_343X }, |
| 247 | { .div = 15, .val = 15, .flags = RATE_IN_343X }, |
| 248 | { .div = 16, .val = 16, .flags = RATE_IN_343X }, |
| 249 | { .div = 0 } |
| 250 | }; |
| 251 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 252 | /* DPLL1 */ |
| 253 | /* MPU clock source */ |
| 254 | /* Type: DPLL */ |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 255 | static struct dpll_data dpll1_dd = { |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 256 | .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 257 | .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, |
| 258 | .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, |
Paul Walmsley | 16c90f0 | 2009-01-27 19:12:47 -0700 | [diff] [blame] | 259 | .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 260 | .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), |
| 261 | .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 262 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 263 | .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, |
| 264 | .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, |
| 265 | .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 266 | .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), |
| 267 | .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, |
| 268 | .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), |
| 269 | .idlest_bit = OMAP3430_ST_MPU_CLK_SHIFT, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 270 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 271 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 272 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 273 | }; |
| 274 | |
| 275 | static struct clk dpll1_ck = { |
| 276 | .name = "dpll1_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 277 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 278 | .parent = &sys_ck, |
| 279 | .dpll_data = &dpll1_dd, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 280 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 281 | .round_rate = &omap2_dpll_round_rate, |
Paul Walmsley | 16c90f0 | 2009-01-27 19:12:47 -0700 | [diff] [blame] | 282 | .set_rate = &omap3_noncore_dpll_set_rate, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 283 | .clkdm_name = "dpll1_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 284 | .recalc = &omap3_dpll_recalc, |
| 285 | }; |
| 286 | |
| 287 | /* |
| 288 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the |
| 289 | * DPLL isn't bypassed. |
| 290 | */ |
| 291 | static struct clk dpll1_x2_ck = { |
| 292 | .name = "dpll1_x2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 293 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 294 | .parent = &dpll1_ck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 295 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 296 | .clkdm_name = "dpll1_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 297 | .recalc = &omap3_clkoutx2_recalc, |
| 298 | }; |
| 299 | |
| 300 | /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */ |
| 301 | static const struct clksel div16_dpll1_x2m2_clksel[] = { |
| 302 | { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates }, |
| 303 | { .parent = NULL } |
| 304 | }; |
| 305 | |
| 306 | /* |
| 307 | * Does not exist in the TRM - needed to separate the M2 divider from |
| 308 | * bypass selection in mpu_ck |
| 309 | */ |
| 310 | static struct clk dpll1_x2m2_ck = { |
| 311 | .name = "dpll1_x2m2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 312 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 313 | .parent = &dpll1_x2_ck, |
| 314 | .init = &omap2_init_clksel_parent, |
| 315 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), |
| 316 | .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, |
| 317 | .clksel = div16_dpll1_x2m2_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 318 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 319 | .clkdm_name = "dpll1_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 320 | .recalc = &omap2_clksel_recalc, |
| 321 | }; |
| 322 | |
| 323 | /* DPLL2 */ |
| 324 | /* IVA2 clock source */ |
| 325 | /* Type: DPLL */ |
| 326 | |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 327 | static struct dpll_data dpll2_dd = { |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 328 | .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 329 | .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, |
| 330 | .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, |
Paul Walmsley | 16c90f0 | 2009-01-27 19:12:47 -0700 | [diff] [blame] | 331 | .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 332 | .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), |
| 333 | .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 334 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | |
| 335 | (1 << DPLL_LOW_POWER_BYPASS), |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 336 | .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, |
| 337 | .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, |
| 338 | .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 339 | .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), |
| 340 | .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, |
| 341 | .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 342 | .idlest_bit = OMAP3430_ST_IVA2_CLK_SHIFT, |
| 343 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 344 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 345 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 346 | }; |
| 347 | |
| 348 | static struct clk dpll2_ck = { |
| 349 | .name = "dpll2_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 350 | .ops = &clkops_noncore_dpll_ops, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 351 | .parent = &sys_ck, |
| 352 | .dpll_data = &dpll2_dd, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 353 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 354 | .round_rate = &omap2_dpll_round_rate, |
Paul Walmsley | 16c90f0 | 2009-01-27 19:12:47 -0700 | [diff] [blame] | 355 | .set_rate = &omap3_noncore_dpll_set_rate, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 356 | .clkdm_name = "dpll2_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 357 | .recalc = &omap3_dpll_recalc, |
| 358 | }; |
| 359 | |
| 360 | static const struct clksel div16_dpll2_m2x2_clksel[] = { |
| 361 | { .parent = &dpll2_ck, .rates = div16_dpll_rates }, |
| 362 | { .parent = NULL } |
| 363 | }; |
| 364 | |
| 365 | /* |
| 366 | * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT |
| 367 | * or CLKOUTX2. CLKOUT seems most plausible. |
| 368 | */ |
| 369 | static struct clk dpll2_m2_ck = { |
| 370 | .name = "dpll2_m2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 371 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 372 | .parent = &dpll2_ck, |
| 373 | .init = &omap2_init_clksel_parent, |
| 374 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, |
| 375 | OMAP3430_CM_CLKSEL2_PLL), |
| 376 | .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, |
| 377 | .clksel = div16_dpll2_m2x2_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 378 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 379 | .clkdm_name = "dpll2_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 380 | .recalc = &omap2_clksel_recalc, |
| 381 | }; |
| 382 | |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 383 | /* |
| 384 | * DPLL3 |
| 385 | * Source clock for all interfaces and for some device fclks |
| 386 | * REVISIT: Also supports fast relock bypass - not included below |
| 387 | */ |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 388 | static struct dpll_data dpll3_dd = { |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 389 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 390 | .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, |
| 391 | .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, |
Paul Walmsley | 16c90f0 | 2009-01-27 19:12:47 -0700 | [diff] [blame] | 392 | .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 393 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 394 | .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, |
| 395 | .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, |
| 396 | .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, |
| 397 | .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 398 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), |
| 399 | .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 400 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 401 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 402 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 403 | }; |
| 404 | |
| 405 | static struct clk dpll3_ck = { |
| 406 | .name = "dpll3_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 407 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 408 | .parent = &sys_ck, |
| 409 | .dpll_data = &dpll3_dd, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 410 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 411 | .round_rate = &omap2_dpll_round_rate, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 412 | .clkdm_name = "dpll3_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 413 | .recalc = &omap3_dpll_recalc, |
| 414 | }; |
| 415 | |
| 416 | /* |
| 417 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the |
| 418 | * DPLL isn't bypassed |
| 419 | */ |
| 420 | static struct clk dpll3_x2_ck = { |
| 421 | .name = "dpll3_x2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 422 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 423 | .parent = &dpll3_ck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 424 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 425 | .clkdm_name = "dpll3_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 426 | .recalc = &omap3_clkoutx2_recalc, |
| 427 | }; |
| 428 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 429 | static const struct clksel_rate div31_dpll3_rates[] = { |
| 430 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 431 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, |
| 432 | { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 }, |
| 433 | { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 }, |
| 434 | { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 }, |
| 435 | { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 }, |
| 436 | { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 }, |
| 437 | { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 }, |
| 438 | { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 }, |
| 439 | { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 }, |
| 440 | { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 }, |
| 441 | { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 }, |
| 442 | { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 }, |
| 443 | { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 }, |
| 444 | { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 }, |
| 445 | { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 }, |
| 446 | { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 }, |
| 447 | { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 }, |
| 448 | { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 }, |
| 449 | { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 }, |
| 450 | { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 }, |
| 451 | { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 }, |
| 452 | { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 }, |
| 453 | { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 }, |
| 454 | { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 }, |
| 455 | { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 }, |
| 456 | { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 }, |
| 457 | { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 }, |
| 458 | { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 }, |
| 459 | { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 }, |
| 460 | { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 }, |
| 461 | { .div = 0 }, |
| 462 | }; |
| 463 | |
| 464 | static const struct clksel div31_dpll3m2_clksel[] = { |
| 465 | { .parent = &dpll3_ck, .rates = div31_dpll3_rates }, |
| 466 | { .parent = NULL } |
| 467 | }; |
| 468 | |
| 469 | /* |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 470 | * DPLL3 output M2 |
| 471 | * REVISIT: This DPLL output divider must be changed in SRAM, so until |
| 472 | * that code is ready, this should remain a 'read-only' clksel clock. |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 473 | */ |
| 474 | static struct clk dpll3_m2_ck = { |
| 475 | .name = "dpll3_m2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 476 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 477 | .parent = &dpll3_ck, |
| 478 | .init = &omap2_init_clksel_parent, |
| 479 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 480 | .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, |
| 481 | .clksel = div31_dpll3m2_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 482 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 483 | .clkdm_name = "dpll3_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 484 | .recalc = &omap2_clksel_recalc, |
| 485 | }; |
| 486 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 487 | static const struct clksel core_ck_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 488 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 489 | { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates }, |
| 490 | { .parent = NULL } |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 491 | }; |
| 492 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 493 | static struct clk core_ck = { |
| 494 | .name = "core_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 495 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 496 | .init = &omap2_init_clksel_parent, |
| 497 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 498 | .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 499 | .clksel = core_ck_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 500 | .flags = RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 501 | .recalc = &omap2_clksel_recalc, |
| 502 | }; |
| 503 | |
| 504 | static const struct clksel dpll3_m2x2_ck_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 505 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 506 | { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates }, |
| 507 | { .parent = NULL } |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 508 | }; |
| 509 | |
| 510 | static struct clk dpll3_m2x2_ck = { |
| 511 | .name = "dpll3_m2x2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 512 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 513 | .init = &omap2_init_clksel_parent, |
| 514 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 515 | .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 516 | .clksel = dpll3_m2x2_ck_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 517 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 518 | .clkdm_name = "dpll3_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 519 | .recalc = &omap2_clksel_recalc, |
| 520 | }; |
| 521 | |
| 522 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 523 | static const struct clksel div16_dpll3_clksel[] = { |
| 524 | { .parent = &dpll3_ck, .rates = div16_dpll_rates }, |
| 525 | { .parent = NULL } |
| 526 | }; |
| 527 | |
| 528 | /* This virtual clock is the source for dpll3_m3x2_ck */ |
| 529 | static struct clk dpll3_m3_ck = { |
| 530 | .name = "dpll3_m3_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 531 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 532 | .parent = &dpll3_ck, |
| 533 | .init = &omap2_init_clksel_parent, |
| 534 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 535 | .clksel_mask = OMAP3430_DIV_DPLL3_MASK, |
| 536 | .clksel = div16_dpll3_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 537 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 538 | .clkdm_name = "dpll3_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 539 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 540 | }; |
| 541 | |
| 542 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 543 | static struct clk dpll3_m3x2_ck = { |
| 544 | .name = "dpll3_m3x2_ck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 545 | .ops = &clkops_omap2_dflt_wait, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 546 | .parent = &dpll3_m3_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 547 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 548 | .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 549 | .flags = RATE_PROPAGATES | INVERT_ENABLE, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 550 | .clkdm_name = "dpll3_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 551 | .recalc = &omap3_clkoutx2_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 552 | }; |
| 553 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 554 | static const struct clksel emu_core_alwon_ck_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 555 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 556 | { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates }, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 557 | { .parent = NULL } |
| 558 | }; |
| 559 | |
| 560 | static struct clk emu_core_alwon_ck = { |
| 561 | .name = "emu_core_alwon_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 562 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 563 | .parent = &dpll3_m3x2_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 564 | .init = &omap2_init_clksel_parent, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 565 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 566 | .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 567 | .clksel = emu_core_alwon_ck_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 568 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 569 | .clkdm_name = "dpll3_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 570 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 571 | }; |
| 572 | |
| 573 | /* DPLL4 */ |
| 574 | /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ |
| 575 | /* Type: DPLL */ |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 576 | static struct dpll_data dpll4_dd = { |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 577 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), |
| 578 | .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, |
| 579 | .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, |
Paul Walmsley | 16c90f0 | 2009-01-27 19:12:47 -0700 | [diff] [blame] | 580 | .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 581 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 582 | .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 583 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 584 | .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, |
| 585 | .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, |
| 586 | .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 587 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), |
| 588 | .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, |
| 589 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
| 590 | .idlest_bit = OMAP3430_ST_PERIPH_CLK_SHIFT, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 591 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 592 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 593 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 594 | }; |
| 595 | |
| 596 | static struct clk dpll4_ck = { |
| 597 | .name = "dpll4_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 598 | .ops = &clkops_noncore_dpll_ops, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 599 | .parent = &sys_ck, |
| 600 | .dpll_data = &dpll4_dd, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 601 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 602 | .round_rate = &omap2_dpll_round_rate, |
Paul Walmsley | 16c90f0 | 2009-01-27 19:12:47 -0700 | [diff] [blame] | 603 | .set_rate = &omap3_dpll4_set_rate, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 604 | .clkdm_name = "dpll4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 605 | .recalc = &omap3_dpll_recalc, |
| 606 | }; |
| 607 | |
| 608 | /* |
| 609 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 610 | * DPLL isn't bypassed -- |
| 611 | * XXX does this serve any downstream clocks? |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 612 | */ |
| 613 | static struct clk dpll4_x2_ck = { |
| 614 | .name = "dpll4_x2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 615 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 616 | .parent = &dpll4_ck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 617 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 618 | .clkdm_name = "dpll4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 619 | .recalc = &omap3_clkoutx2_recalc, |
| 620 | }; |
| 621 | |
| 622 | static const struct clksel div16_dpll4_clksel[] = { |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 623 | { .parent = &dpll4_ck, .rates = div16_dpll_rates }, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 624 | { .parent = NULL } |
| 625 | }; |
| 626 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 627 | /* This virtual clock is the source for dpll4_m2x2_ck */ |
| 628 | static struct clk dpll4_m2_ck = { |
| 629 | .name = "dpll4_m2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 630 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 631 | .parent = &dpll4_ck, |
| 632 | .init = &omap2_init_clksel_parent, |
| 633 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), |
| 634 | .clksel_mask = OMAP3430_DIV_96M_MASK, |
| 635 | .clksel = div16_dpll4_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 636 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 637 | .clkdm_name = "dpll4_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 638 | .recalc = &omap2_clksel_recalc, |
| 639 | }; |
| 640 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 641 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 642 | static struct clk dpll4_m2x2_ck = { |
| 643 | .name = "dpll4_m2x2_ck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 644 | .ops = &clkops_omap2_dflt_wait, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 645 | .parent = &dpll4_m2_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 646 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 647 | .enable_bit = OMAP3430_PWRDN_96M_SHIFT, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 648 | .flags = RATE_PROPAGATES | INVERT_ENABLE, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 649 | .clkdm_name = "dpll4_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 650 | .recalc = &omap3_clkoutx2_recalc, |
| 651 | }; |
| 652 | |
| 653 | static const struct clksel omap_96m_alwon_fck_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 654 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 655 | { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, |
| 656 | { .parent = NULL } |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 657 | }; |
| 658 | |
Paul Walmsley | 9cfd985 | 2009-01-27 19:13:02 -0700 | [diff] [blame] | 659 | /* |
| 660 | * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as |
| 661 | * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM: |
| 662 | * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and |
| 663 | * CM_96K_(F)CLK. |
| 664 | */ |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 665 | static struct clk omap_96m_alwon_fck = { |
| 666 | .name = "omap_96m_alwon_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 667 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 668 | .parent = &dpll4_m2x2_ck, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 669 | .init = &omap2_init_clksel_parent, |
| 670 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 671 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 672 | .clksel = omap_96m_alwon_fck_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 673 | .flags = RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 674 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 675 | }; |
| 676 | |
Paul Walmsley | 9cfd985 | 2009-01-27 19:13:02 -0700 | [diff] [blame] | 677 | static struct clk cm_96m_fck = { |
| 678 | .name = "cm_96m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 679 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 680 | .parent = &omap_96m_alwon_fck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 681 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 682 | .recalc = &followparent_recalc, |
| 683 | }; |
| 684 | |
Paul Walmsley | 9cfd985 | 2009-01-27 19:13:02 -0700 | [diff] [blame] | 685 | static const struct clksel_rate omap_96m_dpll_rates[] = { |
| 686 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 687 | { .div = 0 } |
| 688 | }; |
| 689 | |
| 690 | static const struct clksel_rate omap_96m_sys_rates[] = { |
| 691 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 692 | { .div = 0 } |
| 693 | }; |
| 694 | |
| 695 | static const struct clksel omap_96m_fck_clksel[] = { |
| 696 | { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates }, |
| 697 | { .parent = &sys_ck, .rates = omap_96m_sys_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 698 | { .parent = NULL } |
| 699 | }; |
| 700 | |
Paul Walmsley | 9cfd985 | 2009-01-27 19:13:02 -0700 | [diff] [blame] | 701 | static struct clk omap_96m_fck = { |
| 702 | .name = "omap_96m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 703 | .ops = &clkops_null, |
Paul Walmsley | 9cfd985 | 2009-01-27 19:13:02 -0700 | [diff] [blame] | 704 | .parent = &sys_ck, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 705 | .init = &omap2_init_clksel_parent, |
Paul Walmsley | 9cfd985 | 2009-01-27 19:13:02 -0700 | [diff] [blame] | 706 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 707 | .clksel_mask = OMAP3430_SOURCE_96M_MASK, |
| 708 | .clksel = omap_96m_fck_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 709 | .flags = RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 710 | .recalc = &omap2_clksel_recalc, |
| 711 | }; |
| 712 | |
| 713 | /* This virtual clock is the source for dpll4_m3x2_ck */ |
| 714 | static struct clk dpll4_m3_ck = { |
| 715 | .name = "dpll4_m3_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 716 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 717 | .parent = &dpll4_ck, |
| 718 | .init = &omap2_init_clksel_parent, |
| 719 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), |
| 720 | .clksel_mask = OMAP3430_CLKSEL_TV_MASK, |
| 721 | .clksel = div16_dpll4_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 722 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 723 | .clkdm_name = "dpll4_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 724 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 725 | }; |
| 726 | |
| 727 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 728 | static struct clk dpll4_m3x2_ck = { |
| 729 | .name = "dpll4_m3x2_ck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 730 | .ops = &clkops_omap2_dflt_wait, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 731 | .parent = &dpll4_m3_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 732 | .init = &omap2_init_clksel_parent, |
| 733 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 734 | .enable_bit = OMAP3430_PWRDN_TV_SHIFT, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 735 | .flags = RATE_PROPAGATES | INVERT_ENABLE, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 736 | .clkdm_name = "dpll4_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 737 | .recalc = &omap3_clkoutx2_recalc, |
| 738 | }; |
| 739 | |
| 740 | static const struct clksel virt_omap_54m_fck_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 741 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 742 | { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates }, |
| 743 | { .parent = NULL } |
| 744 | }; |
| 745 | |
| 746 | static struct clk virt_omap_54m_fck = { |
| 747 | .name = "virt_omap_54m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 748 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 749 | .parent = &dpll4_m3x2_ck, |
| 750 | .init = &omap2_init_clksel_parent, |
| 751 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 752 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 753 | .clksel = virt_omap_54m_fck_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 754 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 755 | .recalc = &omap2_clksel_recalc, |
| 756 | }; |
| 757 | |
| 758 | static const struct clksel_rate omap_54m_d4m3x2_rates[] = { |
| 759 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 760 | { .div = 0 } |
| 761 | }; |
| 762 | |
| 763 | static const struct clksel_rate omap_54m_alt_rates[] = { |
| 764 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 765 | { .div = 0 } |
| 766 | }; |
| 767 | |
| 768 | static const struct clksel omap_54m_clksel[] = { |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 769 | { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates }, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 770 | { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, |
| 771 | { .parent = NULL } |
| 772 | }; |
| 773 | |
| 774 | static struct clk omap_54m_fck = { |
| 775 | .name = "omap_54m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 776 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 777 | .init = &omap2_init_clksel_parent, |
| 778 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
Paul Walmsley | 9cfd985 | 2009-01-27 19:13:02 -0700 | [diff] [blame] | 779 | .clksel_mask = OMAP3430_SOURCE_54M_MASK, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 780 | .clksel = omap_54m_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 781 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 782 | .recalc = &omap2_clksel_recalc, |
| 783 | }; |
| 784 | |
Paul Walmsley | 9cfd985 | 2009-01-27 19:13:02 -0700 | [diff] [blame] | 785 | static const struct clksel_rate omap_48m_cm96m_rates[] = { |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 786 | { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 787 | { .div = 0 } |
| 788 | }; |
| 789 | |
| 790 | static const struct clksel_rate omap_48m_alt_rates[] = { |
| 791 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 792 | { .div = 0 } |
| 793 | }; |
| 794 | |
| 795 | static const struct clksel omap_48m_clksel[] = { |
Paul Walmsley | 9cfd985 | 2009-01-27 19:13:02 -0700 | [diff] [blame] | 796 | { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates }, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 797 | { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, |
| 798 | { .parent = NULL } |
| 799 | }; |
| 800 | |
| 801 | static struct clk omap_48m_fck = { |
| 802 | .name = "omap_48m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 803 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 804 | .init = &omap2_init_clksel_parent, |
| 805 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
Paul Walmsley | 9cfd985 | 2009-01-27 19:13:02 -0700 | [diff] [blame] | 806 | .clksel_mask = OMAP3430_SOURCE_48M_MASK, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 807 | .clksel = omap_48m_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 808 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 809 | .recalc = &omap2_clksel_recalc, |
| 810 | }; |
| 811 | |
| 812 | static struct clk omap_12m_fck = { |
| 813 | .name = "omap_12m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 814 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 815 | .parent = &omap_48m_fck, |
| 816 | .fixed_div = 4, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 817 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 818 | .recalc = &omap2_fixed_divisor_recalc, |
| 819 | }; |
| 820 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 821 | /* This virstual clock is the source for dpll4_m4x2_ck */ |
| 822 | static struct clk dpll4_m4_ck = { |
| 823 | .name = "dpll4_m4_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 824 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 825 | .parent = &dpll4_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 826 | .init = &omap2_init_clksel_parent, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 827 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), |
| 828 | .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, |
| 829 | .clksel = div16_dpll4_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 830 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 831 | .clkdm_name = "dpll4_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 832 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | ae8578c | 2009-01-27 19:13:12 -0700 | [diff] [blame] | 833 | .set_rate = &omap2_clksel_set_rate, |
| 834 | .round_rate = &omap2_clksel_round_rate, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 835 | }; |
| 836 | |
| 837 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 838 | static struct clk dpll4_m4x2_ck = { |
| 839 | .name = "dpll4_m4x2_ck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 840 | .ops = &clkops_omap2_dflt_wait, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 841 | .parent = &dpll4_m4_ck, |
| 842 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 843 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 844 | .flags = RATE_PROPAGATES | INVERT_ENABLE, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 845 | .clkdm_name = "dpll4_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 846 | .recalc = &omap3_clkoutx2_recalc, |
| 847 | }; |
| 848 | |
| 849 | /* This virtual clock is the source for dpll4_m5x2_ck */ |
| 850 | static struct clk dpll4_m5_ck = { |
| 851 | .name = "dpll4_m5_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 852 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 853 | .parent = &dpll4_ck, |
| 854 | .init = &omap2_init_clksel_parent, |
| 855 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), |
| 856 | .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, |
| 857 | .clksel = div16_dpll4_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 858 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 859 | .clkdm_name = "dpll4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 860 | .recalc = &omap2_clksel_recalc, |
| 861 | }; |
| 862 | |
| 863 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 864 | static struct clk dpll4_m5x2_ck = { |
| 865 | .name = "dpll4_m5x2_ck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 866 | .ops = &clkops_omap2_dflt_wait, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 867 | .parent = &dpll4_m5_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 868 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 869 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 870 | .flags = RATE_PROPAGATES | INVERT_ENABLE, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 871 | .clkdm_name = "dpll4_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 872 | .recalc = &omap3_clkoutx2_recalc, |
| 873 | }; |
| 874 | |
| 875 | /* This virtual clock is the source for dpll4_m6x2_ck */ |
| 876 | static struct clk dpll4_m6_ck = { |
| 877 | .name = "dpll4_m6_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 878 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 879 | .parent = &dpll4_ck, |
| 880 | .init = &omap2_init_clksel_parent, |
| 881 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 882 | .clksel_mask = OMAP3430_DIV_DPLL4_MASK, |
| 883 | .clksel = div16_dpll4_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 884 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 885 | .clkdm_name = "dpll4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 886 | .recalc = &omap2_clksel_recalc, |
| 887 | }; |
| 888 | |
| 889 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 890 | static struct clk dpll4_m6x2_ck = { |
| 891 | .name = "dpll4_m6x2_ck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 892 | .ops = &clkops_omap2_dflt_wait, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 893 | .parent = &dpll4_m6_ck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 894 | .init = &omap2_init_clksel_parent, |
| 895 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 896 | .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 897 | .flags = RATE_PROPAGATES | INVERT_ENABLE, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 898 | .clkdm_name = "dpll4_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 899 | .recalc = &omap3_clkoutx2_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 900 | }; |
| 901 | |
| 902 | static struct clk emu_per_alwon_ck = { |
| 903 | .name = "emu_per_alwon_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 904 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 905 | .parent = &dpll4_m6x2_ck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 906 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 907 | .clkdm_name = "dpll4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 908 | .recalc = &followparent_recalc, |
| 909 | }; |
| 910 | |
| 911 | /* DPLL5 */ |
| 912 | /* Supplies 120MHz clock, USIM source clock */ |
| 913 | /* Type: DPLL */ |
| 914 | /* 3430ES2 only */ |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 915 | static struct dpll_data dpll5_dd = { |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 916 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), |
| 917 | .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, |
| 918 | .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, |
Paul Walmsley | 16c90f0 | 2009-01-27 19:12:47 -0700 | [diff] [blame] | 919 | .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 920 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), |
| 921 | .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 922 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 923 | .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, |
| 924 | .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, |
| 925 | .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 926 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), |
| 927 | .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, |
| 928 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), |
| 929 | .idlest_bit = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 930 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 931 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 932 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 933 | }; |
| 934 | |
| 935 | static struct clk dpll5_ck = { |
| 936 | .name = "dpll5_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 937 | .ops = &clkops_noncore_dpll_ops, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 938 | .parent = &sys_ck, |
| 939 | .dpll_data = &dpll5_dd, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 940 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 88b8ba9 | 2008-07-03 12:24:46 +0300 | [diff] [blame] | 941 | .round_rate = &omap2_dpll_round_rate, |
Paul Walmsley | 16c90f0 | 2009-01-27 19:12:47 -0700 | [diff] [blame] | 942 | .set_rate = &omap3_noncore_dpll_set_rate, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 943 | .clkdm_name = "dpll5_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 944 | .recalc = &omap3_dpll_recalc, |
| 945 | }; |
| 946 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 947 | static const struct clksel div16_dpll5_clksel[] = { |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 948 | { .parent = &dpll5_ck, .rates = div16_dpll_rates }, |
| 949 | { .parent = NULL } |
| 950 | }; |
| 951 | |
| 952 | static struct clk dpll5_m2_ck = { |
| 953 | .name = "dpll5_m2_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 954 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 955 | .parent = &dpll5_ck, |
| 956 | .init = &omap2_init_clksel_parent, |
| 957 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), |
| 958 | .clksel_mask = OMAP3430ES2_DIV_120M_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 959 | .clksel = div16_dpll5_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 960 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 46e0ccf | 2009-01-27 19:44:18 -0700 | [diff] [blame^] | 961 | .clkdm_name = "dpll5_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 962 | .recalc = &omap2_clksel_recalc, |
| 963 | }; |
| 964 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 965 | static const struct clksel omap_120m_fck_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 966 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 967 | { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates }, |
| 968 | { .parent = NULL } |
| 969 | }; |
| 970 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 971 | static struct clk omap_120m_fck = { |
| 972 | .name = "omap_120m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 973 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 974 | .parent = &dpll5_m2_ck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 975 | .init = &omap2_init_clksel_parent, |
| 976 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), |
| 977 | .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, |
| 978 | .clksel = omap_120m_fck_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 979 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 980 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 981 | }; |
| 982 | |
| 983 | /* CM EXTERNAL CLOCK OUTPUTS */ |
| 984 | |
| 985 | static const struct clksel_rate clkout2_src_core_rates[] = { |
| 986 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 987 | { .div = 0 } |
| 988 | }; |
| 989 | |
| 990 | static const struct clksel_rate clkout2_src_sys_rates[] = { |
| 991 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 992 | { .div = 0 } |
| 993 | }; |
| 994 | |
| 995 | static const struct clksel_rate clkout2_src_96m_rates[] = { |
| 996 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 997 | { .div = 0 } |
| 998 | }; |
| 999 | |
| 1000 | static const struct clksel_rate clkout2_src_54m_rates[] = { |
| 1001 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 1002 | { .div = 0 } |
| 1003 | }; |
| 1004 | |
| 1005 | static const struct clksel clkout2_src_clksel[] = { |
Paul Walmsley | 9cfd985 | 2009-01-27 19:13:02 -0700 | [diff] [blame] | 1006 | { .parent = &core_ck, .rates = clkout2_src_core_rates }, |
| 1007 | { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, |
| 1008 | { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates }, |
| 1009 | { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1010 | { .parent = NULL } |
| 1011 | }; |
| 1012 | |
| 1013 | static struct clk clkout2_src_ck = { |
| 1014 | .name = "clkout2_src_ck", |
Russell King | c1168dc | 2008-11-04 21:24:00 +0000 | [diff] [blame] | 1015 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1016 | .init = &omap2_init_clksel_parent, |
| 1017 | .enable_reg = OMAP3430_CM_CLKOUT_CTRL, |
| 1018 | .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, |
| 1019 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, |
| 1020 | .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, |
| 1021 | .clksel = clkout2_src_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1022 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 15b52bc | 2008-05-07 19:19:07 -0600 | [diff] [blame] | 1023 | .clkdm_name = "core_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1024 | .recalc = &omap2_clksel_recalc, |
| 1025 | }; |
| 1026 | |
| 1027 | static const struct clksel_rate sys_clkout2_rates[] = { |
| 1028 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 1029 | { .div = 2, .val = 1, .flags = RATE_IN_343X }, |
| 1030 | { .div = 4, .val = 2, .flags = RATE_IN_343X }, |
| 1031 | { .div = 8, .val = 3, .flags = RATE_IN_343X }, |
| 1032 | { .div = 16, .val = 4, .flags = RATE_IN_343X }, |
| 1033 | { .div = 0 }, |
| 1034 | }; |
| 1035 | |
| 1036 | static const struct clksel sys_clkout2_clksel[] = { |
| 1037 | { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates }, |
| 1038 | { .parent = NULL }, |
| 1039 | }; |
| 1040 | |
| 1041 | static struct clk sys_clkout2 = { |
| 1042 | .name = "sys_clkout2", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1043 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1044 | .init = &omap2_init_clksel_parent, |
| 1045 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, |
| 1046 | .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, |
| 1047 | .clksel = sys_clkout2_clksel, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1048 | .recalc = &omap2_clksel_recalc, |
| 1049 | }; |
| 1050 | |
| 1051 | /* CM OUTPUT CLOCKS */ |
| 1052 | |
| 1053 | static struct clk corex2_fck = { |
| 1054 | .name = "corex2_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1055 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1056 | .parent = &dpll3_m2x2_ck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1057 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1058 | .recalc = &followparent_recalc, |
| 1059 | }; |
| 1060 | |
| 1061 | /* DPLL power domain clock controls */ |
| 1062 | |
| 1063 | static const struct clksel div2_core_clksel[] = { |
| 1064 | { .parent = &core_ck, .rates = div2_rates }, |
| 1065 | { .parent = NULL } |
| 1066 | }; |
| 1067 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1068 | /* |
| 1069 | * REVISIT: Are these in DPLL power domain or CM power domain? docs |
| 1070 | * may be inconsistent here? |
| 1071 | */ |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1072 | static struct clk dpll1_fck = { |
| 1073 | .name = "dpll1_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1074 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1075 | .parent = &core_ck, |
| 1076 | .init = &omap2_init_clksel_parent, |
| 1077 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 1078 | .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, |
| 1079 | .clksel = div2_core_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1080 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1081 | .recalc = &omap2_clksel_recalc, |
| 1082 | }; |
| 1083 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1084 | /* |
| 1085 | * MPU clksel: |
| 1086 | * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck |
| 1087 | * derives from the high-frequency bypass clock originating from DPLL3, |
| 1088 | * called 'dpll1_fck' |
| 1089 | */ |
| 1090 | static const struct clksel mpu_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1091 | { .parent = &dpll1_fck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1092 | { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates }, |
| 1093 | { .parent = NULL } |
| 1094 | }; |
| 1095 | |
| 1096 | static struct clk mpu_ck = { |
| 1097 | .name = "mpu_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1098 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1099 | .parent = &dpll1_x2m2_ck, |
| 1100 | .init = &omap2_init_clksel_parent, |
| 1101 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), |
| 1102 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, |
| 1103 | .clksel = mpu_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1104 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1105 | .clkdm_name = "mpu_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1106 | .recalc = &omap2_clksel_recalc, |
| 1107 | }; |
| 1108 | |
| 1109 | /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ |
| 1110 | static const struct clksel_rate arm_fck_rates[] = { |
| 1111 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 1112 | { .div = 2, .val = 1, .flags = RATE_IN_343X }, |
| 1113 | { .div = 0 }, |
| 1114 | }; |
| 1115 | |
| 1116 | static const struct clksel arm_fck_clksel[] = { |
| 1117 | { .parent = &mpu_ck, .rates = arm_fck_rates }, |
| 1118 | { .parent = NULL } |
| 1119 | }; |
| 1120 | |
| 1121 | static struct clk arm_fck = { |
| 1122 | .name = "arm_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1123 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1124 | .parent = &mpu_ck, |
| 1125 | .init = &omap2_init_clksel_parent, |
| 1126 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), |
| 1127 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, |
| 1128 | .clksel = arm_fck_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1129 | .flags = RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1130 | .recalc = &omap2_clksel_recalc, |
| 1131 | }; |
| 1132 | |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1133 | /* XXX What about neon_clkdm ? */ |
| 1134 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1135 | /* |
| 1136 | * REVISIT: This clock is never specifically defined in the 3430 TRM, |
| 1137 | * although it is referenced - so this is a guess |
| 1138 | */ |
| 1139 | static struct clk emu_mpu_alwon_ck = { |
| 1140 | .name = "emu_mpu_alwon_ck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1141 | .ops = &clkops_null, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1142 | .parent = &mpu_ck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1143 | .flags = RATE_PROPAGATES, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1144 | .recalc = &followparent_recalc, |
| 1145 | }; |
| 1146 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1147 | static struct clk dpll2_fck = { |
| 1148 | .name = "dpll2_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1149 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1150 | .parent = &core_ck, |
| 1151 | .init = &omap2_init_clksel_parent, |
| 1152 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 1153 | .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, |
| 1154 | .clksel = div2_core_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1155 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1156 | .recalc = &omap2_clksel_recalc, |
| 1157 | }; |
| 1158 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1159 | /* |
| 1160 | * IVA2 clksel: |
| 1161 | * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck |
| 1162 | * derives from the high-frequency bypass clock originating from DPLL3, |
| 1163 | * called 'dpll2_fck' |
| 1164 | */ |
| 1165 | |
| 1166 | static const struct clksel iva2_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1167 | { .parent = &dpll2_fck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1168 | { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates }, |
| 1169 | { .parent = NULL } |
| 1170 | }; |
| 1171 | |
| 1172 | static struct clk iva2_ck = { |
| 1173 | .name = "iva2_ck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1174 | .ops = &clkops_omap2_dflt_wait, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1175 | .parent = &dpll2_m2_ck, |
| 1176 | .init = &omap2_init_clksel_parent, |
Hiroshi DOYU | 31c203d | 2008-04-01 10:11:22 +0300 | [diff] [blame] | 1177 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), |
| 1178 | .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1179 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, |
| 1180 | OMAP3430_CM_IDLEST_PLL), |
| 1181 | .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK, |
| 1182 | .clksel = iva2_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1183 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1184 | .clkdm_name = "iva2_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1185 | .recalc = &omap2_clksel_recalc, |
| 1186 | }; |
| 1187 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1188 | /* Common interface clocks */ |
| 1189 | |
| 1190 | static struct clk l3_ick = { |
| 1191 | .name = "l3_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1192 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1193 | .parent = &core_ck, |
| 1194 | .init = &omap2_init_clksel_parent, |
| 1195 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1196 | .clksel_mask = OMAP3430_CLKSEL_L3_MASK, |
| 1197 | .clksel = div2_core_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1198 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1199 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1200 | .recalc = &omap2_clksel_recalc, |
| 1201 | }; |
| 1202 | |
| 1203 | static const struct clksel div2_l3_clksel[] = { |
| 1204 | { .parent = &l3_ick, .rates = div2_rates }, |
| 1205 | { .parent = NULL } |
| 1206 | }; |
| 1207 | |
| 1208 | static struct clk l4_ick = { |
| 1209 | .name = "l4_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1210 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1211 | .parent = &l3_ick, |
| 1212 | .init = &omap2_init_clksel_parent, |
| 1213 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1214 | .clksel_mask = OMAP3430_CLKSEL_L4_MASK, |
| 1215 | .clksel = div2_l3_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1216 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1217 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1218 | .recalc = &omap2_clksel_recalc, |
| 1219 | |
| 1220 | }; |
| 1221 | |
| 1222 | static const struct clksel div2_l4_clksel[] = { |
| 1223 | { .parent = &l4_ick, .rates = div2_rates }, |
| 1224 | { .parent = NULL } |
| 1225 | }; |
| 1226 | |
| 1227 | static struct clk rm_ick = { |
| 1228 | .name = "rm_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1229 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1230 | .parent = &l4_ick, |
| 1231 | .init = &omap2_init_clksel_parent, |
| 1232 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), |
| 1233 | .clksel_mask = OMAP3430_CLKSEL_RM_MASK, |
| 1234 | .clksel = div2_l4_clksel, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1235 | .recalc = &omap2_clksel_recalc, |
| 1236 | }; |
| 1237 | |
| 1238 | /* GFX power domain */ |
| 1239 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 1240 | /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */ |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1241 | |
| 1242 | static const struct clksel gfx_l3_clksel[] = { |
| 1243 | { .parent = &l3_ick, .rates = gfx_l3_rates }, |
| 1244 | { .parent = NULL } |
| 1245 | }; |
| 1246 | |
Högander Jouni | 5955902 | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1247 | /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ |
| 1248 | static struct clk gfx_l3_ck = { |
| 1249 | .name = "gfx_l3_ck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1250 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1251 | .parent = &l3_ick, |
| 1252 | .init = &omap2_init_clksel_parent, |
| 1253 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), |
| 1254 | .enable_bit = OMAP_EN_GFX_SHIFT, |
Högander Jouni | 5955902 | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1255 | .recalc = &followparent_recalc, |
| 1256 | }; |
| 1257 | |
| 1258 | static struct clk gfx_l3_fck = { |
| 1259 | .name = "gfx_l3_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1260 | .ops = &clkops_null, |
Högander Jouni | 5955902 | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1261 | .parent = &gfx_l3_ck, |
| 1262 | .init = &omap2_init_clksel_parent, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1263 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), |
| 1264 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, |
| 1265 | .clksel = gfx_l3_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1266 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1267 | .clkdm_name = "gfx_3430es1_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1268 | .recalc = &omap2_clksel_recalc, |
| 1269 | }; |
| 1270 | |
| 1271 | static struct clk gfx_l3_ick = { |
| 1272 | .name = "gfx_l3_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1273 | .ops = &clkops_null, |
Högander Jouni | 5955902 | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1274 | .parent = &gfx_l3_ck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1275 | .clkdm_name = "gfx_3430es1_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1276 | .recalc = &followparent_recalc, |
| 1277 | }; |
| 1278 | |
| 1279 | static struct clk gfx_cg1_ck = { |
| 1280 | .name = "gfx_cg1_ck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1281 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1282 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1283 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1284 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 1285 | .enable_bit = OMAP3430ES1_EN_2D_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1286 | .clkdm_name = "gfx_3430es1_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1287 | .recalc = &followparent_recalc, |
| 1288 | }; |
| 1289 | |
| 1290 | static struct clk gfx_cg2_ck = { |
| 1291 | .name = "gfx_cg2_ck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1292 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1293 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1294 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1295 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 1296 | .enable_bit = OMAP3430ES1_EN_3D_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1297 | .clkdm_name = "gfx_3430es1_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1298 | .recalc = &followparent_recalc, |
| 1299 | }; |
| 1300 | |
| 1301 | /* SGX power domain - 3430ES2 only */ |
| 1302 | |
| 1303 | static const struct clksel_rate sgx_core_rates[] = { |
| 1304 | { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 1305 | { .div = 4, .val = 1, .flags = RATE_IN_343X }, |
| 1306 | { .div = 6, .val = 2, .flags = RATE_IN_343X }, |
| 1307 | { .div = 0 }, |
| 1308 | }; |
| 1309 | |
| 1310 | static const struct clksel_rate sgx_96m_rates[] = { |
| 1311 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 1312 | { .div = 0 }, |
| 1313 | }; |
| 1314 | |
| 1315 | static const struct clksel sgx_clksel[] = { |
| 1316 | { .parent = &core_ck, .rates = sgx_core_rates }, |
| 1317 | { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, |
| 1318 | { .parent = NULL }, |
| 1319 | }; |
| 1320 | |
| 1321 | static struct clk sgx_fck = { |
| 1322 | .name = "sgx_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1323 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1324 | .init = &omap2_init_clksel_parent, |
| 1325 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), |
Daniel Stone | 712d7c8 | 2009-01-27 19:13:05 -0700 | [diff] [blame] | 1326 | .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1327 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), |
| 1328 | .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, |
| 1329 | .clksel = sgx_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1330 | .clkdm_name = "sgx_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1331 | .recalc = &omap2_clksel_recalc, |
| 1332 | }; |
| 1333 | |
| 1334 | static struct clk sgx_ick = { |
| 1335 | .name = "sgx_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1336 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1337 | .parent = &l3_ick, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1338 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1339 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), |
Daniel Stone | 712d7c8 | 2009-01-27 19:13:05 -0700 | [diff] [blame] | 1340 | .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1341 | .clkdm_name = "sgx_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1342 | .recalc = &followparent_recalc, |
| 1343 | }; |
| 1344 | |
| 1345 | /* CORE power domain */ |
| 1346 | |
| 1347 | static struct clk d2d_26m_fck = { |
| 1348 | .name = "d2d_26m_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1349 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1350 | .parent = &sys_ck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1351 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1352 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1353 | .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1354 | .clkdm_name = "d2d_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1355 | .recalc = &followparent_recalc, |
| 1356 | }; |
| 1357 | |
| 1358 | static const struct clksel omap343x_gpt_clksel[] = { |
| 1359 | { .parent = &omap_32k_fck, .rates = gpt_32k_rates }, |
| 1360 | { .parent = &sys_ck, .rates = gpt_sys_rates }, |
| 1361 | { .parent = NULL} |
| 1362 | }; |
| 1363 | |
| 1364 | static struct clk gpt10_fck = { |
| 1365 | .name = "gpt10_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1366 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1367 | .parent = &sys_ck, |
| 1368 | .init = &omap2_init_clksel_parent, |
| 1369 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1370 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, |
| 1371 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1372 | .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, |
| 1373 | .clksel = omap343x_gpt_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1374 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1375 | .recalc = &omap2_clksel_recalc, |
| 1376 | }; |
| 1377 | |
| 1378 | static struct clk gpt11_fck = { |
| 1379 | .name = "gpt11_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1380 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1381 | .parent = &sys_ck, |
| 1382 | .init = &omap2_init_clksel_parent, |
| 1383 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1384 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, |
| 1385 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1386 | .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, |
| 1387 | .clksel = omap343x_gpt_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1388 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1389 | .recalc = &omap2_clksel_recalc, |
| 1390 | }; |
| 1391 | |
| 1392 | static struct clk cpefuse_fck = { |
| 1393 | .name = "cpefuse_fck", |
Russell King | c1168dc | 2008-11-04 21:24:00 +0000 | [diff] [blame] | 1394 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1395 | .parent = &sys_ck, |
| 1396 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
| 1397 | .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1398 | .recalc = &followparent_recalc, |
| 1399 | }; |
| 1400 | |
| 1401 | static struct clk ts_fck = { |
| 1402 | .name = "ts_fck", |
Russell King | c1168dc | 2008-11-04 21:24:00 +0000 | [diff] [blame] | 1403 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1404 | .parent = &omap_32k_fck, |
| 1405 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
| 1406 | .enable_bit = OMAP3430ES2_EN_TS_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1407 | .recalc = &followparent_recalc, |
| 1408 | }; |
| 1409 | |
| 1410 | static struct clk usbtll_fck = { |
| 1411 | .name = "usbtll_fck", |
Russell King | c1168dc | 2008-11-04 21:24:00 +0000 | [diff] [blame] | 1412 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1413 | .parent = &omap_120m_fck, |
| 1414 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
| 1415 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1416 | .recalc = &followparent_recalc, |
| 1417 | }; |
| 1418 | |
| 1419 | /* CORE 96M FCLK-derived clocks */ |
| 1420 | |
| 1421 | static struct clk core_96m_fck = { |
| 1422 | .name = "core_96m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1423 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1424 | .parent = &omap_96m_fck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1425 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1426 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1427 | .recalc = &followparent_recalc, |
| 1428 | }; |
| 1429 | |
| 1430 | static struct clk mmchs3_fck = { |
| 1431 | .name = "mmchs_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1432 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | d887466 | 2008-12-10 17:37:16 -0800 | [diff] [blame] | 1433 | .id = 2, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1434 | .parent = &core_96m_fck, |
| 1435 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1436 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1437 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1438 | .recalc = &followparent_recalc, |
| 1439 | }; |
| 1440 | |
| 1441 | static struct clk mmchs2_fck = { |
| 1442 | .name = "mmchs_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1443 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | d887466 | 2008-12-10 17:37:16 -0800 | [diff] [blame] | 1444 | .id = 1, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1445 | .parent = &core_96m_fck, |
| 1446 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1447 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1448 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1449 | .recalc = &followparent_recalc, |
| 1450 | }; |
| 1451 | |
| 1452 | static struct clk mspro_fck = { |
| 1453 | .name = "mspro_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1454 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1455 | .parent = &core_96m_fck, |
| 1456 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1457 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1458 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1459 | .recalc = &followparent_recalc, |
| 1460 | }; |
| 1461 | |
| 1462 | static struct clk mmchs1_fck = { |
| 1463 | .name = "mmchs_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1464 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1465 | .parent = &core_96m_fck, |
| 1466 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1467 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1468 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1469 | .recalc = &followparent_recalc, |
| 1470 | }; |
| 1471 | |
| 1472 | static struct clk i2c3_fck = { |
| 1473 | .name = "i2c_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1474 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1475 | .id = 3, |
| 1476 | .parent = &core_96m_fck, |
| 1477 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1478 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1479 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1480 | .recalc = &followparent_recalc, |
| 1481 | }; |
| 1482 | |
| 1483 | static struct clk i2c2_fck = { |
| 1484 | .name = "i2c_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1485 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1486 | .id = 2, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1487 | .parent = &core_96m_fck, |
| 1488 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1489 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1490 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1491 | .recalc = &followparent_recalc, |
| 1492 | }; |
| 1493 | |
| 1494 | static struct clk i2c1_fck = { |
| 1495 | .name = "i2c_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1496 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1497 | .id = 1, |
| 1498 | .parent = &core_96m_fck, |
| 1499 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1500 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1501 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1502 | .recalc = &followparent_recalc, |
| 1503 | }; |
| 1504 | |
| 1505 | /* |
| 1506 | * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck; |
| 1507 | * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. |
| 1508 | */ |
| 1509 | static const struct clksel_rate common_mcbsp_96m_rates[] = { |
| 1510 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 1511 | { .div = 0 } |
| 1512 | }; |
| 1513 | |
| 1514 | static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { |
| 1515 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 1516 | { .div = 0 } |
| 1517 | }; |
| 1518 | |
| 1519 | static const struct clksel mcbsp_15_clksel[] = { |
| 1520 | { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, |
| 1521 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, |
| 1522 | { .parent = NULL } |
| 1523 | }; |
| 1524 | |
| 1525 | static struct clk mcbsp5_fck = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1526 | .name = "mcbsp_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1527 | .ops = &clkops_omap2_dflt_wait, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1528 | .id = 5, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1529 | .init = &omap2_init_clksel_parent, |
| 1530 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1531 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, |
| 1532 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), |
| 1533 | .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, |
| 1534 | .clksel = mcbsp_15_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1535 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1536 | .recalc = &omap2_clksel_recalc, |
| 1537 | }; |
| 1538 | |
| 1539 | static struct clk mcbsp1_fck = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1540 | .name = "mcbsp_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1541 | .ops = &clkops_omap2_dflt_wait, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1542 | .id = 1, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1543 | .init = &omap2_init_clksel_parent, |
| 1544 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1545 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, |
| 1546 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), |
| 1547 | .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, |
| 1548 | .clksel = mcbsp_15_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1549 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1550 | .recalc = &omap2_clksel_recalc, |
| 1551 | }; |
| 1552 | |
| 1553 | /* CORE_48M_FCK-derived clocks */ |
| 1554 | |
| 1555 | static struct clk core_48m_fck = { |
| 1556 | .name = "core_48m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1557 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1558 | .parent = &omap_48m_fck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1559 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1560 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1561 | .recalc = &followparent_recalc, |
| 1562 | }; |
| 1563 | |
| 1564 | static struct clk mcspi4_fck = { |
| 1565 | .name = "mcspi_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1566 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1567 | .id = 4, |
| 1568 | .parent = &core_48m_fck, |
| 1569 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1570 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1571 | .recalc = &followparent_recalc, |
| 1572 | }; |
| 1573 | |
| 1574 | static struct clk mcspi3_fck = { |
| 1575 | .name = "mcspi_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1576 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1577 | .id = 3, |
| 1578 | .parent = &core_48m_fck, |
| 1579 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1580 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1581 | .recalc = &followparent_recalc, |
| 1582 | }; |
| 1583 | |
| 1584 | static struct clk mcspi2_fck = { |
| 1585 | .name = "mcspi_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1586 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1587 | .id = 2, |
| 1588 | .parent = &core_48m_fck, |
| 1589 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1590 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1591 | .recalc = &followparent_recalc, |
| 1592 | }; |
| 1593 | |
| 1594 | static struct clk mcspi1_fck = { |
| 1595 | .name = "mcspi_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1596 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1597 | .id = 1, |
| 1598 | .parent = &core_48m_fck, |
| 1599 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1600 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1601 | .recalc = &followparent_recalc, |
| 1602 | }; |
| 1603 | |
| 1604 | static struct clk uart2_fck = { |
| 1605 | .name = "uart2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1606 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1607 | .parent = &core_48m_fck, |
| 1608 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1609 | .enable_bit = OMAP3430_EN_UART2_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1610 | .recalc = &followparent_recalc, |
| 1611 | }; |
| 1612 | |
| 1613 | static struct clk uart1_fck = { |
| 1614 | .name = "uart1_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1615 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1616 | .parent = &core_48m_fck, |
| 1617 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1618 | .enable_bit = OMAP3430_EN_UART1_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1619 | .recalc = &followparent_recalc, |
| 1620 | }; |
| 1621 | |
| 1622 | static struct clk fshostusb_fck = { |
| 1623 | .name = "fshostusb_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1624 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1625 | .parent = &core_48m_fck, |
| 1626 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1627 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1628 | .recalc = &followparent_recalc, |
| 1629 | }; |
| 1630 | |
| 1631 | /* CORE_12M_FCK based clocks */ |
| 1632 | |
| 1633 | static struct clk core_12m_fck = { |
| 1634 | .name = "core_12m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1635 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1636 | .parent = &omap_12m_fck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1637 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1638 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1639 | .recalc = &followparent_recalc, |
| 1640 | }; |
| 1641 | |
| 1642 | static struct clk hdq_fck = { |
| 1643 | .name = "hdq_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1644 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1645 | .parent = &core_12m_fck, |
| 1646 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1647 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1648 | .recalc = &followparent_recalc, |
| 1649 | }; |
| 1650 | |
| 1651 | /* DPLL3-derived clock */ |
| 1652 | |
| 1653 | static const struct clksel_rate ssi_ssr_corex2_rates[] = { |
| 1654 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 1655 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, |
| 1656 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, |
| 1657 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, |
| 1658 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, |
| 1659 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, |
| 1660 | { .div = 0 } |
| 1661 | }; |
| 1662 | |
| 1663 | static const struct clksel ssi_ssr_clksel[] = { |
| 1664 | { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates }, |
| 1665 | { .parent = NULL } |
| 1666 | }; |
| 1667 | |
| 1668 | static struct clk ssi_ssr_fck = { |
| 1669 | .name = "ssi_ssr_fck", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 1670 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1671 | .init = &omap2_init_clksel_parent, |
| 1672 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1673 | .enable_bit = OMAP3430_EN_SSI_SHIFT, |
| 1674 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1675 | .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, |
| 1676 | .clksel = ssi_ssr_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1677 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1678 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1679 | .recalc = &omap2_clksel_recalc, |
| 1680 | }; |
| 1681 | |
| 1682 | static struct clk ssi_sst_fck = { |
| 1683 | .name = "ssi_sst_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1684 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1685 | .parent = &ssi_ssr_fck, |
| 1686 | .fixed_div = 2, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1687 | .recalc = &omap2_fixed_divisor_recalc, |
| 1688 | }; |
| 1689 | |
| 1690 | |
| 1691 | |
| 1692 | /* CORE_L3_ICK based clocks */ |
| 1693 | |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1694 | /* |
| 1695 | * XXX must add clk_enable/clk_disable for these if standard code won't |
| 1696 | * handle it |
| 1697 | */ |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1698 | static struct clk core_l3_ick = { |
| 1699 | .name = "core_l3_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1700 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1701 | .parent = &l3_ick, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1702 | .init = &omap2_init_clk_clkdm, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1703 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1704 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1705 | .recalc = &followparent_recalc, |
| 1706 | }; |
| 1707 | |
| 1708 | static struct clk hsotgusb_ick = { |
| 1709 | .name = "hsotgusb_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1710 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1711 | .parent = &core_l3_ick, |
| 1712 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1713 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1714 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1715 | .recalc = &followparent_recalc, |
| 1716 | }; |
| 1717 | |
| 1718 | static struct clk sdrc_ick = { |
| 1719 | .name = "sdrc_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1720 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1721 | .parent = &core_l3_ick, |
| 1722 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1723 | .enable_bit = OMAP3430_EN_SDRC_SHIFT, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1724 | .flags = ENABLE_ON_INIT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1725 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1726 | .recalc = &followparent_recalc, |
| 1727 | }; |
| 1728 | |
| 1729 | static struct clk gpmc_fck = { |
| 1730 | .name = "gpmc_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1731 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1732 | .parent = &core_l3_ick, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1733 | .flags = ENABLE_ON_INIT, /* huh? */ |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1734 | .clkdm_name = "core_l3_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1735 | .recalc = &followparent_recalc, |
| 1736 | }; |
| 1737 | |
| 1738 | /* SECURITY_L3_ICK based clocks */ |
| 1739 | |
| 1740 | static struct clk security_l3_ick = { |
| 1741 | .name = "security_l3_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1742 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1743 | .parent = &l3_ick, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1744 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1745 | .recalc = &followparent_recalc, |
| 1746 | }; |
| 1747 | |
| 1748 | static struct clk pka_ick = { |
| 1749 | .name = "pka_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1750 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1751 | .parent = &security_l3_ick, |
| 1752 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1753 | .enable_bit = OMAP3430_EN_PKA_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1754 | .recalc = &followparent_recalc, |
| 1755 | }; |
| 1756 | |
| 1757 | /* CORE_L4_ICK based clocks */ |
| 1758 | |
| 1759 | static struct clk core_l4_ick = { |
| 1760 | .name = "core_l4_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 1761 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1762 | .parent = &l4_ick, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1763 | .init = &omap2_init_clk_clkdm, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 1764 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1765 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1766 | .recalc = &followparent_recalc, |
| 1767 | }; |
| 1768 | |
| 1769 | static struct clk usbtll_ick = { |
| 1770 | .name = "usbtll_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1771 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1772 | .parent = &core_l4_ick, |
| 1773 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), |
| 1774 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1775 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1776 | .recalc = &followparent_recalc, |
| 1777 | }; |
| 1778 | |
| 1779 | static struct clk mmchs3_ick = { |
| 1780 | .name = "mmchs_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1781 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | d887466 | 2008-12-10 17:37:16 -0800 | [diff] [blame] | 1782 | .id = 2, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1783 | .parent = &core_l4_ick, |
| 1784 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1785 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1786 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1787 | .recalc = &followparent_recalc, |
| 1788 | }; |
| 1789 | |
| 1790 | /* Intersystem Communication Registers - chassis mode only */ |
| 1791 | static struct clk icr_ick = { |
| 1792 | .name = "icr_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1793 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1794 | .parent = &core_l4_ick, |
| 1795 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1796 | .enable_bit = OMAP3430_EN_ICR_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1797 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1798 | .recalc = &followparent_recalc, |
| 1799 | }; |
| 1800 | |
| 1801 | static struct clk aes2_ick = { |
| 1802 | .name = "aes2_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1803 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1804 | .parent = &core_l4_ick, |
| 1805 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1806 | .enable_bit = OMAP3430_EN_AES2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1807 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1808 | .recalc = &followparent_recalc, |
| 1809 | }; |
| 1810 | |
| 1811 | static struct clk sha12_ick = { |
| 1812 | .name = "sha12_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1813 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1814 | .parent = &core_l4_ick, |
| 1815 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1816 | .enable_bit = OMAP3430_EN_SHA12_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1817 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1818 | .recalc = &followparent_recalc, |
| 1819 | }; |
| 1820 | |
| 1821 | static struct clk des2_ick = { |
| 1822 | .name = "des2_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1823 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1824 | .parent = &core_l4_ick, |
| 1825 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1826 | .enable_bit = OMAP3430_EN_DES2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1827 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1828 | .recalc = &followparent_recalc, |
| 1829 | }; |
| 1830 | |
| 1831 | static struct clk mmchs2_ick = { |
| 1832 | .name = "mmchs_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1833 | .ops = &clkops_omap2_dflt_wait, |
Tony Lindgren | d887466 | 2008-12-10 17:37:16 -0800 | [diff] [blame] | 1834 | .id = 1, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1835 | .parent = &core_l4_ick, |
| 1836 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1837 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1838 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1839 | .recalc = &followparent_recalc, |
| 1840 | }; |
| 1841 | |
| 1842 | static struct clk mmchs1_ick = { |
| 1843 | .name = "mmchs_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1844 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1845 | .parent = &core_l4_ick, |
| 1846 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1847 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1848 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1849 | .recalc = &followparent_recalc, |
| 1850 | }; |
| 1851 | |
| 1852 | static struct clk mspro_ick = { |
| 1853 | .name = "mspro_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1854 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1855 | .parent = &core_l4_ick, |
| 1856 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1857 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1858 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1859 | .recalc = &followparent_recalc, |
| 1860 | }; |
| 1861 | |
| 1862 | static struct clk hdq_ick = { |
| 1863 | .name = "hdq_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1864 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1865 | .parent = &core_l4_ick, |
| 1866 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1867 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1868 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1869 | .recalc = &followparent_recalc, |
| 1870 | }; |
| 1871 | |
| 1872 | static struct clk mcspi4_ick = { |
| 1873 | .name = "mcspi_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1874 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1875 | .id = 4, |
| 1876 | .parent = &core_l4_ick, |
| 1877 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1878 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1879 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1880 | .recalc = &followparent_recalc, |
| 1881 | }; |
| 1882 | |
| 1883 | static struct clk mcspi3_ick = { |
| 1884 | .name = "mcspi_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1885 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1886 | .id = 3, |
| 1887 | .parent = &core_l4_ick, |
| 1888 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1889 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1890 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1891 | .recalc = &followparent_recalc, |
| 1892 | }; |
| 1893 | |
| 1894 | static struct clk mcspi2_ick = { |
| 1895 | .name = "mcspi_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1896 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1897 | .id = 2, |
| 1898 | .parent = &core_l4_ick, |
| 1899 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1900 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1901 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1902 | .recalc = &followparent_recalc, |
| 1903 | }; |
| 1904 | |
| 1905 | static struct clk mcspi1_ick = { |
| 1906 | .name = "mcspi_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1907 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1908 | .id = 1, |
| 1909 | .parent = &core_l4_ick, |
| 1910 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1911 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1912 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1913 | .recalc = &followparent_recalc, |
| 1914 | }; |
| 1915 | |
| 1916 | static struct clk i2c3_ick = { |
| 1917 | .name = "i2c_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1918 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1919 | .id = 3, |
| 1920 | .parent = &core_l4_ick, |
| 1921 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1922 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1923 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1924 | .recalc = &followparent_recalc, |
| 1925 | }; |
| 1926 | |
| 1927 | static struct clk i2c2_ick = { |
| 1928 | .name = "i2c_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1929 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1930 | .id = 2, |
| 1931 | .parent = &core_l4_ick, |
| 1932 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1933 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1934 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1935 | .recalc = &followparent_recalc, |
| 1936 | }; |
| 1937 | |
| 1938 | static struct clk i2c1_ick = { |
| 1939 | .name = "i2c_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1940 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1941 | .id = 1, |
| 1942 | .parent = &core_l4_ick, |
| 1943 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1944 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1945 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1946 | .recalc = &followparent_recalc, |
| 1947 | }; |
| 1948 | |
| 1949 | static struct clk uart2_ick = { |
| 1950 | .name = "uart2_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1951 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1952 | .parent = &core_l4_ick, |
| 1953 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1954 | .enable_bit = OMAP3430_EN_UART2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1955 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1956 | .recalc = &followparent_recalc, |
| 1957 | }; |
| 1958 | |
| 1959 | static struct clk uart1_ick = { |
| 1960 | .name = "uart1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1961 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1962 | .parent = &core_l4_ick, |
| 1963 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1964 | .enable_bit = OMAP3430_EN_UART1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1965 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1966 | .recalc = &followparent_recalc, |
| 1967 | }; |
| 1968 | |
| 1969 | static struct clk gpt11_ick = { |
| 1970 | .name = "gpt11_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1971 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1972 | .parent = &core_l4_ick, |
| 1973 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1974 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1975 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1976 | .recalc = &followparent_recalc, |
| 1977 | }; |
| 1978 | |
| 1979 | static struct clk gpt10_ick = { |
| 1980 | .name = "gpt10_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1981 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1982 | .parent = &core_l4_ick, |
| 1983 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1984 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1985 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1986 | .recalc = &followparent_recalc, |
| 1987 | }; |
| 1988 | |
| 1989 | static struct clk mcbsp5_ick = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1990 | .name = "mcbsp_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 1991 | .ops = &clkops_omap2_dflt_wait, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 1992 | .id = 5, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1993 | .parent = &core_l4_ick, |
| 1994 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1995 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 1996 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 1997 | .recalc = &followparent_recalc, |
| 1998 | }; |
| 1999 | |
| 2000 | static struct clk mcbsp1_ick = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2001 | .name = "mcbsp_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2002 | .ops = &clkops_omap2_dflt_wait, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2003 | .id = 1, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2004 | .parent = &core_l4_ick, |
| 2005 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2006 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2007 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2008 | .recalc = &followparent_recalc, |
| 2009 | }; |
| 2010 | |
| 2011 | static struct clk fac_ick = { |
| 2012 | .name = "fac_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2013 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2014 | .parent = &core_l4_ick, |
| 2015 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2016 | .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2017 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2018 | .recalc = &followparent_recalc, |
| 2019 | }; |
| 2020 | |
| 2021 | static struct clk mailboxes_ick = { |
| 2022 | .name = "mailboxes_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2023 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2024 | .parent = &core_l4_ick, |
| 2025 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2026 | .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2027 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2028 | .recalc = &followparent_recalc, |
| 2029 | }; |
| 2030 | |
| 2031 | static struct clk omapctrl_ick = { |
| 2032 | .name = "omapctrl_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2033 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2034 | .parent = &core_l4_ick, |
| 2035 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2036 | .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2037 | .flags = ENABLE_ON_INIT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2038 | .recalc = &followparent_recalc, |
| 2039 | }; |
| 2040 | |
| 2041 | /* SSI_L4_ICK based clocks */ |
| 2042 | |
| 2043 | static struct clk ssi_l4_ick = { |
| 2044 | .name = "ssi_l4_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 2045 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2046 | .parent = &l4_ick, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2047 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2048 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2049 | .recalc = &followparent_recalc, |
| 2050 | }; |
| 2051 | |
| 2052 | static struct clk ssi_ick = { |
| 2053 | .name = "ssi_ick", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 2054 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2055 | .parent = &ssi_l4_ick, |
| 2056 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2057 | .enable_bit = OMAP3430_EN_SSI_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2058 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2059 | .recalc = &followparent_recalc, |
| 2060 | }; |
| 2061 | |
| 2062 | /* REVISIT: Technically the TRM claims that this is CORE_CLK based, |
| 2063 | * but l4_ick makes more sense to me */ |
| 2064 | |
| 2065 | static const struct clksel usb_l4_clksel[] = { |
| 2066 | { .parent = &l4_ick, .rates = div2_rates }, |
| 2067 | { .parent = NULL }, |
| 2068 | }; |
| 2069 | |
| 2070 | static struct clk usb_l4_ick = { |
| 2071 | .name = "usb_l4_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2072 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2073 | .parent = &l4_ick, |
| 2074 | .init = &omap2_init_clksel_parent, |
| 2075 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2076 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, |
| 2077 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 2078 | .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, |
| 2079 | .clksel = usb_l4_clksel, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2080 | .recalc = &omap2_clksel_recalc, |
| 2081 | }; |
| 2082 | |
| 2083 | /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */ |
| 2084 | |
| 2085 | /* SECURITY_L4_ICK2 based clocks */ |
| 2086 | |
| 2087 | static struct clk security_l4_ick2 = { |
| 2088 | .name = "security_l4_ick2", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 2089 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2090 | .parent = &l4_ick, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2091 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2092 | .recalc = &followparent_recalc, |
| 2093 | }; |
| 2094 | |
| 2095 | static struct clk aes1_ick = { |
| 2096 | .name = "aes1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2097 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2098 | .parent = &security_l4_ick2, |
| 2099 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2100 | .enable_bit = OMAP3430_EN_AES1_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2101 | .recalc = &followparent_recalc, |
| 2102 | }; |
| 2103 | |
| 2104 | static struct clk rng_ick = { |
| 2105 | .name = "rng_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2106 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2107 | .parent = &security_l4_ick2, |
| 2108 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2109 | .enable_bit = OMAP3430_EN_RNG_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2110 | .recalc = &followparent_recalc, |
| 2111 | }; |
| 2112 | |
| 2113 | static struct clk sha11_ick = { |
| 2114 | .name = "sha11_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2115 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2116 | .parent = &security_l4_ick2, |
| 2117 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2118 | .enable_bit = OMAP3430_EN_SHA11_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2119 | .recalc = &followparent_recalc, |
| 2120 | }; |
| 2121 | |
| 2122 | static struct clk des1_ick = { |
| 2123 | .name = "des1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2124 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2125 | .parent = &security_l4_ick2, |
| 2126 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2127 | .enable_bit = OMAP3430_EN_DES1_SHIFT, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2128 | .recalc = &followparent_recalc, |
| 2129 | }; |
| 2130 | |
| 2131 | /* DSS */ |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2132 | static const struct clksel dss1_alwon_fck_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2133 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2134 | { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates }, |
| 2135 | { .parent = NULL } |
| 2136 | }; |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2137 | |
| 2138 | static struct clk dss1_alwon_fck = { |
| 2139 | .name = "dss1_alwon_fck", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 2140 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2141 | .parent = &dpll4_m4x2_ck, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2142 | .init = &omap2_init_clksel_parent, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2143 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2144 | .enable_bit = OMAP3430_EN_DSS1_SHIFT, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2145 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 2146 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2147 | .clksel = dss1_alwon_fck_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2148 | .clkdm_name = "dss_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2149 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2150 | }; |
| 2151 | |
| 2152 | static struct clk dss_tv_fck = { |
| 2153 | .name = "dss_tv_fck", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 2154 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2155 | .parent = &omap_54m_fck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2156 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2157 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2158 | .enable_bit = OMAP3430_EN_TV_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2159 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2160 | .recalc = &followparent_recalc, |
| 2161 | }; |
| 2162 | |
| 2163 | static struct clk dss_96m_fck = { |
| 2164 | .name = "dss_96m_fck", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 2165 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2166 | .parent = &omap_96m_fck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2167 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2168 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2169 | .enable_bit = OMAP3430_EN_TV_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2170 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2171 | .recalc = &followparent_recalc, |
| 2172 | }; |
| 2173 | |
| 2174 | static struct clk dss2_alwon_fck = { |
| 2175 | .name = "dss2_alwon_fck", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 2176 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2177 | .parent = &sys_ck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2178 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2179 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2180 | .enable_bit = OMAP3430_EN_DSS2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2181 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2182 | .recalc = &followparent_recalc, |
| 2183 | }; |
| 2184 | |
| 2185 | static struct clk dss_ick = { |
| 2186 | /* Handles both L3 and L4 clocks */ |
| 2187 | .name = "dss_ick", |
Russell King | bc51da4 | 2008-11-04 18:59:32 +0000 | [diff] [blame] | 2188 | .ops = &clkops_omap2_dflt, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2189 | .parent = &l4_ick, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2190 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2191 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), |
| 2192 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2193 | .clkdm_name = "dss_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2194 | .recalc = &followparent_recalc, |
| 2195 | }; |
| 2196 | |
| 2197 | /* CAM */ |
| 2198 | |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2199 | static const struct clksel cam_mclk_clksel[] = { |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2200 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2201 | { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates }, |
| 2202 | { .parent = NULL } |
| 2203 | }; |
| 2204 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2205 | static struct clk cam_mclk = { |
| 2206 | .name = "cam_mclk", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2207 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2208 | .parent = &dpll4_m5x2_ck, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2209 | .init = &omap2_init_clksel_parent, |
| 2210 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
Paul Walmsley | 542313c | 2008-07-03 12:24:45 +0300 | [diff] [blame] | 2211 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2212 | .clksel = cam_mclk_clksel, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2213 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), |
| 2214 | .enable_bit = OMAP3430_EN_CAM_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2215 | .clkdm_name = "cam_clkdm", |
Roman Tereshonkov | 3760d31 | 2008-03-13 21:35:09 +0200 | [diff] [blame] | 2216 | .recalc = &omap2_clksel_recalc, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2217 | }; |
| 2218 | |
Högander Jouni | 5955902 | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2219 | static struct clk cam_ick = { |
| 2220 | /* Handles both L3 and L4 clocks */ |
| 2221 | .name = "cam_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2222 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2223 | .parent = &l4_ick, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2224 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2225 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), |
| 2226 | .enable_bit = OMAP3430_EN_CAM_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2227 | .clkdm_name = "cam_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2228 | .recalc = &followparent_recalc, |
| 2229 | }; |
| 2230 | |
Sergio Aguirre | 6c8fe0b | 2009-01-27 19:13:09 -0700 | [diff] [blame] | 2231 | static struct clk csi2_96m_fck = { |
| 2232 | .name = "csi2_96m_fck", |
| 2233 | .ops = &clkops_omap2_dflt_wait, |
| 2234 | .parent = &core_96m_fck, |
| 2235 | .init = &omap2_init_clk_clkdm, |
| 2236 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), |
| 2237 | .enable_bit = OMAP3430_EN_CSI2_SHIFT, |
| 2238 | .clkdm_name = "cam_clkdm", |
| 2239 | .recalc = &followparent_recalc, |
| 2240 | }; |
| 2241 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2242 | /* USBHOST - 3430ES2 only */ |
| 2243 | |
| 2244 | static struct clk usbhost_120m_fck = { |
| 2245 | .name = "usbhost_120m_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2246 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2247 | .parent = &omap_120m_fck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2248 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2249 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), |
| 2250 | .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2251 | .clkdm_name = "usbhost_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2252 | .recalc = &followparent_recalc, |
| 2253 | }; |
| 2254 | |
| 2255 | static struct clk usbhost_48m_fck = { |
| 2256 | .name = "usbhost_48m_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2257 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2258 | .parent = &omap_48m_fck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2259 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2260 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), |
| 2261 | .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2262 | .clkdm_name = "usbhost_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2263 | .recalc = &followparent_recalc, |
| 2264 | }; |
| 2265 | |
Högander Jouni | 5955902 | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2266 | static struct clk usbhost_ick = { |
| 2267 | /* Handles both L3 and L4 clocks */ |
| 2268 | .name = "usbhost_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2269 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2270 | .parent = &l4_ick, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2271 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2272 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), |
| 2273 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2274 | .clkdm_name = "usbhost_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2275 | .recalc = &followparent_recalc, |
| 2276 | }; |
| 2277 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2278 | /* WKUP */ |
| 2279 | |
| 2280 | static const struct clksel_rate usim_96m_rates[] = { |
| 2281 | { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2282 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, |
| 2283 | { .div = 8, .val = 5, .flags = RATE_IN_343X }, |
| 2284 | { .div = 10, .val = 6, .flags = RATE_IN_343X }, |
| 2285 | { .div = 0 }, |
| 2286 | }; |
| 2287 | |
| 2288 | static const struct clksel_rate usim_120m_rates[] = { |
| 2289 | { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2290 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, |
| 2291 | { .div = 16, .val = 9, .flags = RATE_IN_343X }, |
| 2292 | { .div = 20, .val = 10, .flags = RATE_IN_343X }, |
| 2293 | { .div = 0 }, |
| 2294 | }; |
| 2295 | |
| 2296 | static const struct clksel usim_clksel[] = { |
| 2297 | { .parent = &omap_96m_fck, .rates = usim_96m_rates }, |
| 2298 | { .parent = &omap_120m_fck, .rates = usim_120m_rates }, |
| 2299 | { .parent = &sys_ck, .rates = div2_rates }, |
| 2300 | { .parent = NULL }, |
| 2301 | }; |
| 2302 | |
| 2303 | /* 3430ES2 only */ |
| 2304 | static struct clk usim_fck = { |
| 2305 | .name = "usim_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2306 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2307 | .init = &omap2_init_clksel_parent, |
| 2308 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2309 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, |
| 2310 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), |
| 2311 | .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, |
| 2312 | .clksel = usim_clksel, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2313 | .recalc = &omap2_clksel_recalc, |
| 2314 | }; |
| 2315 | |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2316 | /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2317 | static struct clk gpt1_fck = { |
| 2318 | .name = "gpt1_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2319 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2320 | .init = &omap2_init_clksel_parent, |
| 2321 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2322 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, |
| 2323 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), |
| 2324 | .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, |
| 2325 | .clksel = omap343x_gpt_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2326 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2327 | .recalc = &omap2_clksel_recalc, |
| 2328 | }; |
| 2329 | |
| 2330 | static struct clk wkup_32k_fck = { |
| 2331 | .name = "wkup_32k_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2332 | .ops = &clkops_null, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2333 | .init = &omap2_init_clk_clkdm, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2334 | .parent = &omap_32k_fck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2335 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2336 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2337 | .recalc = &followparent_recalc, |
| 2338 | }; |
| 2339 | |
Jouni Hogander | 89db948 | 2008-12-10 17:35:24 -0800 | [diff] [blame] | 2340 | static struct clk gpio1_dbck = { |
| 2341 | .name = "gpio1_dbck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2342 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2343 | .parent = &wkup_32k_fck, |
| 2344 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2345 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2346 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2347 | .recalc = &followparent_recalc, |
| 2348 | }; |
| 2349 | |
| 2350 | static struct clk wdt2_fck = { |
| 2351 | .name = "wdt2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2352 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2353 | .parent = &wkup_32k_fck, |
| 2354 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2355 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2356 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2357 | .recalc = &followparent_recalc, |
| 2358 | }; |
| 2359 | |
| 2360 | static struct clk wkup_l4_ick = { |
| 2361 | .name = "wkup_l4_ick", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2362 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2363 | .parent = &sys_ck, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2364 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2365 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2366 | .recalc = &followparent_recalc, |
| 2367 | }; |
| 2368 | |
| 2369 | /* 3430ES2 only */ |
| 2370 | /* Never specifically named in the TRM, so we have to infer a likely name */ |
| 2371 | static struct clk usim_ick = { |
| 2372 | .name = "usim_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2373 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2374 | .parent = &wkup_l4_ick, |
| 2375 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2376 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2377 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2378 | .recalc = &followparent_recalc, |
| 2379 | }; |
| 2380 | |
| 2381 | static struct clk wdt2_ick = { |
| 2382 | .name = "wdt2_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2383 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2384 | .parent = &wkup_l4_ick, |
| 2385 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2386 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2387 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2388 | .recalc = &followparent_recalc, |
| 2389 | }; |
| 2390 | |
| 2391 | static struct clk wdt1_ick = { |
| 2392 | .name = "wdt1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2393 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2394 | .parent = &wkup_l4_ick, |
| 2395 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2396 | .enable_bit = OMAP3430_EN_WDT1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2397 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2398 | .recalc = &followparent_recalc, |
| 2399 | }; |
| 2400 | |
| 2401 | static struct clk gpio1_ick = { |
| 2402 | .name = "gpio1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2403 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2404 | .parent = &wkup_l4_ick, |
| 2405 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2406 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2407 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2408 | .recalc = &followparent_recalc, |
| 2409 | }; |
| 2410 | |
| 2411 | static struct clk omap_32ksync_ick = { |
| 2412 | .name = "omap_32ksync_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2413 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2414 | .parent = &wkup_l4_ick, |
| 2415 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2416 | .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2417 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2418 | .recalc = &followparent_recalc, |
| 2419 | }; |
| 2420 | |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2421 | /* XXX This clock no longer exists in 3430 TRM rev F */ |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2422 | static struct clk gpt12_ick = { |
| 2423 | .name = "gpt12_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2424 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2425 | .parent = &wkup_l4_ick, |
| 2426 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2427 | .enable_bit = OMAP3430_EN_GPT12_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2428 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2429 | .recalc = &followparent_recalc, |
| 2430 | }; |
| 2431 | |
| 2432 | static struct clk gpt1_ick = { |
| 2433 | .name = "gpt1_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2434 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2435 | .parent = &wkup_l4_ick, |
| 2436 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2437 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2438 | .clkdm_name = "wkup_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2439 | .recalc = &followparent_recalc, |
| 2440 | }; |
| 2441 | |
| 2442 | |
| 2443 | |
| 2444 | /* PER clock domain */ |
| 2445 | |
| 2446 | static struct clk per_96m_fck = { |
| 2447 | .name = "per_96m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 2448 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2449 | .parent = &omap_96m_alwon_fck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2450 | .init = &omap2_init_clk_clkdm, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2451 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2452 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2453 | .recalc = &followparent_recalc, |
| 2454 | }; |
| 2455 | |
| 2456 | static struct clk per_48m_fck = { |
| 2457 | .name = "per_48m_fck", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 2458 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2459 | .parent = &omap_48m_fck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2460 | .init = &omap2_init_clk_clkdm, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2461 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2462 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2463 | .recalc = &followparent_recalc, |
| 2464 | }; |
| 2465 | |
| 2466 | static struct clk uart3_fck = { |
| 2467 | .name = "uart3_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2468 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2469 | .parent = &per_48m_fck, |
| 2470 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2471 | .enable_bit = OMAP3430_EN_UART3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2472 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2473 | .recalc = &followparent_recalc, |
| 2474 | }; |
| 2475 | |
| 2476 | static struct clk gpt2_fck = { |
| 2477 | .name = "gpt2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2478 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2479 | .init = &omap2_init_clksel_parent, |
| 2480 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2481 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, |
| 2482 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2483 | .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, |
| 2484 | .clksel = omap343x_gpt_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2485 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2486 | .recalc = &omap2_clksel_recalc, |
| 2487 | }; |
| 2488 | |
| 2489 | static struct clk gpt3_fck = { |
| 2490 | .name = "gpt3_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2491 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2492 | .init = &omap2_init_clksel_parent, |
| 2493 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2494 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, |
| 2495 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2496 | .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, |
| 2497 | .clksel = omap343x_gpt_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2498 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2499 | .recalc = &omap2_clksel_recalc, |
| 2500 | }; |
| 2501 | |
| 2502 | static struct clk gpt4_fck = { |
| 2503 | .name = "gpt4_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2504 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2505 | .init = &omap2_init_clksel_parent, |
| 2506 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2507 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, |
| 2508 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2509 | .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, |
| 2510 | .clksel = omap343x_gpt_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2511 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2512 | .recalc = &omap2_clksel_recalc, |
| 2513 | }; |
| 2514 | |
| 2515 | static struct clk gpt5_fck = { |
| 2516 | .name = "gpt5_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2517 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2518 | .init = &omap2_init_clksel_parent, |
| 2519 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2520 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, |
| 2521 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2522 | .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, |
| 2523 | .clksel = omap343x_gpt_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2524 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2525 | .recalc = &omap2_clksel_recalc, |
| 2526 | }; |
| 2527 | |
| 2528 | static struct clk gpt6_fck = { |
| 2529 | .name = "gpt6_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2530 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2531 | .init = &omap2_init_clksel_parent, |
| 2532 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2533 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, |
| 2534 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2535 | .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, |
| 2536 | .clksel = omap343x_gpt_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2537 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2538 | .recalc = &omap2_clksel_recalc, |
| 2539 | }; |
| 2540 | |
| 2541 | static struct clk gpt7_fck = { |
| 2542 | .name = "gpt7_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2543 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2544 | .init = &omap2_init_clksel_parent, |
| 2545 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2546 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, |
| 2547 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2548 | .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, |
| 2549 | .clksel = omap343x_gpt_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2550 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2551 | .recalc = &omap2_clksel_recalc, |
| 2552 | }; |
| 2553 | |
| 2554 | static struct clk gpt8_fck = { |
| 2555 | .name = "gpt8_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2556 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2557 | .init = &omap2_init_clksel_parent, |
| 2558 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2559 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, |
| 2560 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2561 | .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, |
| 2562 | .clksel = omap343x_gpt_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2563 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2564 | .recalc = &omap2_clksel_recalc, |
| 2565 | }; |
| 2566 | |
| 2567 | static struct clk gpt9_fck = { |
| 2568 | .name = "gpt9_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2569 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2570 | .init = &omap2_init_clksel_parent, |
| 2571 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2572 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, |
| 2573 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2574 | .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, |
| 2575 | .clksel = omap343x_gpt_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2576 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2577 | .recalc = &omap2_clksel_recalc, |
| 2578 | }; |
| 2579 | |
| 2580 | static struct clk per_32k_alwon_fck = { |
| 2581 | .name = "per_32k_alwon_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2582 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2583 | .parent = &omap_32k_fck, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2584 | .clkdm_name = "per_clkdm", |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2585 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2586 | .recalc = &followparent_recalc, |
| 2587 | }; |
| 2588 | |
Jouni Hogander | 89db948 | 2008-12-10 17:35:24 -0800 | [diff] [blame] | 2589 | static struct clk gpio6_dbck = { |
| 2590 | .name = "gpio6_dbck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2591 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2592 | .parent = &per_32k_alwon_fck, |
| 2593 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
Jouni Högander | c3aa044a | 2008-03-28 14:57:50 +0200 | [diff] [blame] | 2594 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2595 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2596 | .recalc = &followparent_recalc, |
| 2597 | }; |
| 2598 | |
Jouni Hogander | 89db948 | 2008-12-10 17:35:24 -0800 | [diff] [blame] | 2599 | static struct clk gpio5_dbck = { |
| 2600 | .name = "gpio5_dbck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2601 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2602 | .parent = &per_32k_alwon_fck, |
| 2603 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
Jouni Högander | c3aa044a | 2008-03-28 14:57:50 +0200 | [diff] [blame] | 2604 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2605 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2606 | .recalc = &followparent_recalc, |
| 2607 | }; |
| 2608 | |
Jouni Hogander | 89db948 | 2008-12-10 17:35:24 -0800 | [diff] [blame] | 2609 | static struct clk gpio4_dbck = { |
| 2610 | .name = "gpio4_dbck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2611 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2612 | .parent = &per_32k_alwon_fck, |
| 2613 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
Jouni Högander | c3aa044a | 2008-03-28 14:57:50 +0200 | [diff] [blame] | 2614 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2615 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2616 | .recalc = &followparent_recalc, |
| 2617 | }; |
| 2618 | |
Jouni Hogander | 89db948 | 2008-12-10 17:35:24 -0800 | [diff] [blame] | 2619 | static struct clk gpio3_dbck = { |
| 2620 | .name = "gpio3_dbck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2621 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2622 | .parent = &per_32k_alwon_fck, |
| 2623 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
Jouni Högander | c3aa044a | 2008-03-28 14:57:50 +0200 | [diff] [blame] | 2624 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2625 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2626 | .recalc = &followparent_recalc, |
| 2627 | }; |
| 2628 | |
Jouni Hogander | 89db948 | 2008-12-10 17:35:24 -0800 | [diff] [blame] | 2629 | static struct clk gpio2_dbck = { |
| 2630 | .name = "gpio2_dbck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2631 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2632 | .parent = &per_32k_alwon_fck, |
| 2633 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
Jouni Högander | c3aa044a | 2008-03-28 14:57:50 +0200 | [diff] [blame] | 2634 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2635 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2636 | .recalc = &followparent_recalc, |
| 2637 | }; |
| 2638 | |
| 2639 | static struct clk wdt3_fck = { |
| 2640 | .name = "wdt3_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2641 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2642 | .parent = &per_32k_alwon_fck, |
| 2643 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2644 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2645 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2646 | .recalc = &followparent_recalc, |
| 2647 | }; |
| 2648 | |
| 2649 | static struct clk per_l4_ick = { |
| 2650 | .name = "per_l4_ick", |
Russell King | 5713718 | 2008-11-04 16:48:35 +0000 | [diff] [blame] | 2651 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2652 | .parent = &l4_ick, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2653 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2654 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2655 | .recalc = &followparent_recalc, |
| 2656 | }; |
| 2657 | |
| 2658 | static struct clk gpio6_ick = { |
| 2659 | .name = "gpio6_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2660 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2661 | .parent = &per_l4_ick, |
| 2662 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2663 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2664 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2665 | .recalc = &followparent_recalc, |
| 2666 | }; |
| 2667 | |
| 2668 | static struct clk gpio5_ick = { |
| 2669 | .name = "gpio5_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2670 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2671 | .parent = &per_l4_ick, |
| 2672 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2673 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2674 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2675 | .recalc = &followparent_recalc, |
| 2676 | }; |
| 2677 | |
| 2678 | static struct clk gpio4_ick = { |
| 2679 | .name = "gpio4_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2680 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2681 | .parent = &per_l4_ick, |
| 2682 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2683 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2684 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2685 | .recalc = &followparent_recalc, |
| 2686 | }; |
| 2687 | |
| 2688 | static struct clk gpio3_ick = { |
| 2689 | .name = "gpio3_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2690 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2691 | .parent = &per_l4_ick, |
| 2692 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2693 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2694 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2695 | .recalc = &followparent_recalc, |
| 2696 | }; |
| 2697 | |
| 2698 | static struct clk gpio2_ick = { |
| 2699 | .name = "gpio2_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2700 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2701 | .parent = &per_l4_ick, |
| 2702 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2703 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2704 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2705 | .recalc = &followparent_recalc, |
| 2706 | }; |
| 2707 | |
| 2708 | static struct clk wdt3_ick = { |
| 2709 | .name = "wdt3_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2710 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2711 | .parent = &per_l4_ick, |
| 2712 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2713 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2714 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2715 | .recalc = &followparent_recalc, |
| 2716 | }; |
| 2717 | |
| 2718 | static struct clk uart3_ick = { |
| 2719 | .name = "uart3_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2720 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2721 | .parent = &per_l4_ick, |
| 2722 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2723 | .enable_bit = OMAP3430_EN_UART3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2724 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2725 | .recalc = &followparent_recalc, |
| 2726 | }; |
| 2727 | |
| 2728 | static struct clk gpt9_ick = { |
| 2729 | .name = "gpt9_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2730 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2731 | .parent = &per_l4_ick, |
| 2732 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2733 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2734 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2735 | .recalc = &followparent_recalc, |
| 2736 | }; |
| 2737 | |
| 2738 | static struct clk gpt8_ick = { |
| 2739 | .name = "gpt8_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2740 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2741 | .parent = &per_l4_ick, |
| 2742 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2743 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2744 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2745 | .recalc = &followparent_recalc, |
| 2746 | }; |
| 2747 | |
| 2748 | static struct clk gpt7_ick = { |
| 2749 | .name = "gpt7_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2750 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2751 | .parent = &per_l4_ick, |
| 2752 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2753 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2754 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2755 | .recalc = &followparent_recalc, |
| 2756 | }; |
| 2757 | |
| 2758 | static struct clk gpt6_ick = { |
| 2759 | .name = "gpt6_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2760 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2761 | .parent = &per_l4_ick, |
| 2762 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2763 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2764 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2765 | .recalc = &followparent_recalc, |
| 2766 | }; |
| 2767 | |
| 2768 | static struct clk gpt5_ick = { |
| 2769 | .name = "gpt5_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2770 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2771 | .parent = &per_l4_ick, |
| 2772 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2773 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2774 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2775 | .recalc = &followparent_recalc, |
| 2776 | }; |
| 2777 | |
| 2778 | static struct clk gpt4_ick = { |
| 2779 | .name = "gpt4_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2780 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2781 | .parent = &per_l4_ick, |
| 2782 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2783 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2784 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2785 | .recalc = &followparent_recalc, |
| 2786 | }; |
| 2787 | |
| 2788 | static struct clk gpt3_ick = { |
| 2789 | .name = "gpt3_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2790 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2791 | .parent = &per_l4_ick, |
| 2792 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2793 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2794 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2795 | .recalc = &followparent_recalc, |
| 2796 | }; |
| 2797 | |
| 2798 | static struct clk gpt2_ick = { |
| 2799 | .name = "gpt2_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2800 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2801 | .parent = &per_l4_ick, |
| 2802 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2803 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2804 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2805 | .recalc = &followparent_recalc, |
| 2806 | }; |
| 2807 | |
| 2808 | static struct clk mcbsp2_ick = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2809 | .name = "mcbsp_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2810 | .ops = &clkops_omap2_dflt_wait, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2811 | .id = 2, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2812 | .parent = &per_l4_ick, |
| 2813 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2814 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2815 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2816 | .recalc = &followparent_recalc, |
| 2817 | }; |
| 2818 | |
| 2819 | static struct clk mcbsp3_ick = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2820 | .name = "mcbsp_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2821 | .ops = &clkops_omap2_dflt_wait, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2822 | .id = 3, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2823 | .parent = &per_l4_ick, |
| 2824 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2825 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2826 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2827 | .recalc = &followparent_recalc, |
| 2828 | }; |
| 2829 | |
| 2830 | static struct clk mcbsp4_ick = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2831 | .name = "mcbsp_ick", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2832 | .ops = &clkops_omap2_dflt_wait, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2833 | .id = 4, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2834 | .parent = &per_l4_ick, |
| 2835 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2836 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2837 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2838 | .recalc = &followparent_recalc, |
| 2839 | }; |
| 2840 | |
| 2841 | static const struct clksel mcbsp_234_clksel[] = { |
Paul Walmsley | 9cfd985 | 2009-01-27 19:13:02 -0700 | [diff] [blame] | 2842 | { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, |
| 2843 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2844 | { .parent = NULL } |
| 2845 | }; |
| 2846 | |
| 2847 | static struct clk mcbsp2_fck = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2848 | .name = "mcbsp_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2849 | .ops = &clkops_omap2_dflt_wait, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2850 | .id = 2, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2851 | .init = &omap2_init_clksel_parent, |
| 2852 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2853 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, |
| 2854 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), |
| 2855 | .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, |
| 2856 | .clksel = mcbsp_234_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2857 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2858 | .recalc = &omap2_clksel_recalc, |
| 2859 | }; |
| 2860 | |
| 2861 | static struct clk mcbsp3_fck = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2862 | .name = "mcbsp_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2863 | .ops = &clkops_omap2_dflt_wait, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2864 | .id = 3, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2865 | .init = &omap2_init_clksel_parent, |
| 2866 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2867 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, |
| 2868 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), |
| 2869 | .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, |
| 2870 | .clksel = mcbsp_234_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2871 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2872 | .recalc = &omap2_clksel_recalc, |
| 2873 | }; |
| 2874 | |
| 2875 | static struct clk mcbsp4_fck = { |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2876 | .name = "mcbsp_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 2877 | .ops = &clkops_omap2_dflt_wait, |
Eduardo Valentin | 78673bc | 2008-07-03 12:24:40 +0300 | [diff] [blame] | 2878 | .id = 4, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2879 | .init = &omap2_init_clksel_parent, |
| 2880 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2881 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, |
| 2882 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), |
| 2883 | .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, |
| 2884 | .clksel = mcbsp_234_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2885 | .clkdm_name = "per_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2886 | .recalc = &omap2_clksel_recalc, |
| 2887 | }; |
| 2888 | |
| 2889 | /* EMU clocks */ |
| 2890 | |
| 2891 | /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ |
| 2892 | |
| 2893 | static const struct clksel_rate emu_src_sys_rates[] = { |
| 2894 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2895 | { .div = 0 }, |
| 2896 | }; |
| 2897 | |
| 2898 | static const struct clksel_rate emu_src_core_rates[] = { |
| 2899 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2900 | { .div = 0 }, |
| 2901 | }; |
| 2902 | |
| 2903 | static const struct clksel_rate emu_src_per_rates[] = { |
| 2904 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2905 | { .div = 0 }, |
| 2906 | }; |
| 2907 | |
| 2908 | static const struct clksel_rate emu_src_mpu_rates[] = { |
| 2909 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2910 | { .div = 0 }, |
| 2911 | }; |
| 2912 | |
| 2913 | static const struct clksel emu_src_clksel[] = { |
| 2914 | { .parent = &sys_ck, .rates = emu_src_sys_rates }, |
| 2915 | { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates }, |
| 2916 | { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates }, |
| 2917 | { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates }, |
| 2918 | { .parent = NULL }, |
| 2919 | }; |
| 2920 | |
| 2921 | /* |
| 2922 | * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only |
| 2923 | * to switch the source of some of the EMU clocks. |
| 2924 | * XXX Are there CLKEN bits for these EMU clks? |
| 2925 | */ |
| 2926 | static struct clk emu_src_ck = { |
| 2927 | .name = "emu_src_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2928 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2929 | .init = &omap2_init_clksel_parent, |
| 2930 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2931 | .clksel_mask = OMAP3430_MUX_CTRL_MASK, |
| 2932 | .clksel = emu_src_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2933 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2934 | .clkdm_name = "emu_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2935 | .recalc = &omap2_clksel_recalc, |
| 2936 | }; |
| 2937 | |
| 2938 | static const struct clksel_rate pclk_emu_rates[] = { |
| 2939 | { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2940 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, |
| 2941 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, |
| 2942 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, |
| 2943 | { .div = 0 }, |
| 2944 | }; |
| 2945 | |
| 2946 | static const struct clksel pclk_emu_clksel[] = { |
| 2947 | { .parent = &emu_src_ck, .rates = pclk_emu_rates }, |
| 2948 | { .parent = NULL }, |
| 2949 | }; |
| 2950 | |
| 2951 | static struct clk pclk_fck = { |
| 2952 | .name = "pclk_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2953 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2954 | .init = &omap2_init_clksel_parent, |
| 2955 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2956 | .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, |
| 2957 | .clksel = pclk_emu_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2958 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2959 | .clkdm_name = "emu_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2960 | .recalc = &omap2_clksel_recalc, |
| 2961 | }; |
| 2962 | |
| 2963 | static const struct clksel_rate pclkx2_emu_rates[] = { |
| 2964 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 2965 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, |
| 2966 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, |
| 2967 | { .div = 0 }, |
| 2968 | }; |
| 2969 | |
| 2970 | static const struct clksel pclkx2_emu_clksel[] = { |
| 2971 | { .parent = &emu_src_ck, .rates = pclkx2_emu_rates }, |
| 2972 | { .parent = NULL }, |
| 2973 | }; |
| 2974 | |
| 2975 | static struct clk pclkx2_fck = { |
| 2976 | .name = "pclkx2_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2977 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2978 | .init = &omap2_init_clksel_parent, |
| 2979 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2980 | .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, |
| 2981 | .clksel = pclkx2_emu_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2982 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 2983 | .clkdm_name = "emu_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2984 | .recalc = &omap2_clksel_recalc, |
| 2985 | }; |
| 2986 | |
| 2987 | static const struct clksel atclk_emu_clksel[] = { |
| 2988 | { .parent = &emu_src_ck, .rates = div2_rates }, |
| 2989 | { .parent = NULL }, |
| 2990 | }; |
| 2991 | |
| 2992 | static struct clk atclk_fck = { |
| 2993 | .name = "atclk_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 2994 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 2995 | .init = &omap2_init_clksel_parent, |
| 2996 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2997 | .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, |
| 2998 | .clksel = atclk_emu_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 2999 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 3000 | .clkdm_name = "emu_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3001 | .recalc = &omap2_clksel_recalc, |
| 3002 | }; |
| 3003 | |
| 3004 | static struct clk traceclk_src_fck = { |
| 3005 | .name = "traceclk_src_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 3006 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3007 | .init = &omap2_init_clksel_parent, |
| 3008 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 3009 | .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, |
| 3010 | .clksel = emu_src_clksel, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 3011 | .flags = RATE_PROPAGATES, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 3012 | .clkdm_name = "emu_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3013 | .recalc = &omap2_clksel_recalc, |
| 3014 | }; |
| 3015 | |
| 3016 | static const struct clksel_rate traceclk_rates[] = { |
| 3017 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 3018 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, |
| 3019 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, |
| 3020 | { .div = 0 }, |
| 3021 | }; |
| 3022 | |
| 3023 | static const struct clksel traceclk_clksel[] = { |
| 3024 | { .parent = &traceclk_src_fck, .rates = traceclk_rates }, |
| 3025 | { .parent = NULL }, |
| 3026 | }; |
| 3027 | |
| 3028 | static struct clk traceclk_fck = { |
| 3029 | .name = "traceclk_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 3030 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3031 | .init = &omap2_init_clksel_parent, |
| 3032 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 3033 | .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, |
| 3034 | .clksel = traceclk_clksel, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 3035 | .clkdm_name = "emu_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3036 | .recalc = &omap2_clksel_recalc, |
| 3037 | }; |
| 3038 | |
| 3039 | /* SR clocks */ |
| 3040 | |
| 3041 | /* SmartReflex fclk (VDD1) */ |
| 3042 | static struct clk sr1_fck = { |
| 3043 | .name = "sr1_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 3044 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3045 | .parent = &sys_ck, |
| 3046 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 3047 | .enable_bit = OMAP3430_EN_SR1_SHIFT, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 3048 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3049 | .recalc = &followparent_recalc, |
| 3050 | }; |
| 3051 | |
| 3052 | /* SmartReflex fclk (VDD2) */ |
| 3053 | static struct clk sr2_fck = { |
| 3054 | .name = "sr2_fck", |
Russell King | b36ee72 | 2008-11-04 17:59:52 +0000 | [diff] [blame] | 3055 | .ops = &clkops_omap2_dflt_wait, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3056 | .parent = &sys_ck, |
| 3057 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 3058 | .enable_bit = OMAP3430_EN_SR2_SHIFT, |
Russell King | 44dc9d0 | 2009-01-19 15:51:11 +0000 | [diff] [blame] | 3059 | .flags = RATE_PROPAGATES, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3060 | .recalc = &followparent_recalc, |
| 3061 | }; |
| 3062 | |
| 3063 | static struct clk sr_l4_ick = { |
| 3064 | .name = "sr_l4_ick", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 3065 | .ops = &clkops_null, /* RMK: missing? */ |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3066 | .parent = &l4_ick, |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 3067 | .clkdm_name = "core_l4_clkdm", |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3068 | .recalc = &followparent_recalc, |
| 3069 | }; |
| 3070 | |
| 3071 | /* SECURE_32K_FCK clocks */ |
| 3072 | |
Paul Walmsley | 333943b | 2008-08-19 11:08:45 +0300 | [diff] [blame] | 3073 | /* XXX This clock no longer exists in 3430 TRM rev F */ |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3074 | static struct clk gpt12_fck = { |
| 3075 | .name = "gpt12_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 3076 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3077 | .parent = &secure_32k_fck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3078 | .recalc = &followparent_recalc, |
| 3079 | }; |
| 3080 | |
| 3081 | static struct clk wdt1_fck = { |
| 3082 | .name = "wdt1_fck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame] | 3083 | .ops = &clkops_null, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3084 | .parent = &secure_32k_fck, |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3085 | .recalc = &followparent_recalc, |
| 3086 | }; |
| 3087 | |
Paul Walmsley | b045d08 | 2008-03-18 11:24:28 +0200 | [diff] [blame] | 3088 | #endif |