Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Intel IO-APIC support for multi-Pentium hosts. |
| 3 | * |
Ingo Molnar | 8f47e16 | 2009-01-31 02:03:42 +0100 | [diff] [blame] | 4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * |
| 6 | * Many thanks to Stig Venaas for trying out countless experimental |
| 7 | * patches and reporting/debugging problems patiently! |
| 8 | * |
| 9 | * (c) 1999, Multiple IO-APIC support, developed by |
| 10 | * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and |
| 11 | * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, |
| 12 | * further tested and cleaned up by Zach Brown <zab@redhat.com> |
| 13 | * and Ingo Molnar <mingo@redhat.com> |
| 14 | * |
| 15 | * Fixes |
| 16 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs; |
| 17 | * thanks to Eric Gilmore |
| 18 | * and Rolf G. Tews |
| 19 | * for testing these extensively |
| 20 | * Paul Diefenbaugh : Added full ACPI support |
| 21 | */ |
| 22 | |
| 23 | #include <linux/mm.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 24 | #include <linux/interrupt.h> |
| 25 | #include <linux/init.h> |
| 26 | #include <linux/delay.h> |
| 27 | #include <linux/sched.h> |
Yinghai Lu | d4057bd | 2008-08-19 20:50:38 -0700 | [diff] [blame] | 28 | #include <linux/pci.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | #include <linux/mc146818rtc.h> |
| 30 | #include <linux/compiler.h> |
| 31 | #include <linux/acpi.h> |
Alexey Dobriyan | 129f694 | 2005-06-23 00:08:33 -0700 | [diff] [blame] | 32 | #include <linux/module.h> |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 33 | #include <linux/syscore_ops.h> |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 34 | #include <linux/msi.h> |
Eric W. Biederman | 95d7788 | 2006-10-04 02:17:01 -0700 | [diff] [blame] | 35 | #include <linux/htirq.h> |
Nigel Cunningham | 7dfb710 | 2006-12-06 20:34:23 -0800 | [diff] [blame] | 36 | #include <linux/freezer.h> |
Eric W. Biederman | f26d6a2 | 2007-05-02 19:27:19 +0200 | [diff] [blame] | 37 | #include <linux/kthread.h> |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 38 | #include <linux/jiffies.h> /* time_after() */ |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 39 | #include <linux/slab.h> |
Yinghai Lu | d4057bd | 2008-08-19 20:50:38 -0700 | [diff] [blame] | 40 | #include <linux/bootmem.h> |
| 41 | #include <linux/dmar.h> |
venkatesh.pallipadi@intel.com | 58ac1e7 | 2008-09-05 18:02:17 -0700 | [diff] [blame] | 42 | #include <linux/hpet.h> |
Ashok Raj | 54d5d42 | 2005-09-06 15:16:15 -0700 | [diff] [blame] | 43 | |
Yinghai Lu | d4057bd | 2008-08-19 20:50:38 -0700 | [diff] [blame] | 44 | #include <asm/idle.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 45 | #include <asm/io.h> |
| 46 | #include <asm/smp.h> |
Jaswinder Singh Rajput | 6d652ea | 2009-01-07 21:38:59 +0530 | [diff] [blame] | 47 | #include <asm/cpu.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 48 | #include <asm/desc.h> |
Yinghai Lu | d4057bd | 2008-08-19 20:50:38 -0700 | [diff] [blame] | 49 | #include <asm/proto.h> |
| 50 | #include <asm/acpi.h> |
| 51 | #include <asm/dma.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 52 | #include <asm/timer.h> |
Ingo Molnar | 306e440 | 2005-06-30 02:58:55 -0700 | [diff] [blame] | 53 | #include <asm/i8259.h> |
Eric W. Biederman | 2d3fcc1 | 2006-10-04 02:16:43 -0700 | [diff] [blame] | 54 | #include <asm/msidef.h> |
Eric W. Biederman | 8b955b0 | 2006-10-04 02:16:55 -0700 | [diff] [blame] | 55 | #include <asm/hypertransport.h> |
Yinghai Lu | a4dbc34 | 2008-07-25 02:14:28 -0700 | [diff] [blame] | 56 | #include <asm/setup.h> |
Suresh Siddha | 8a8f422 | 2012-03-30 11:47:08 -0700 | [diff] [blame] | 57 | #include <asm/irq_remapping.h> |
venkatesh.pallipadi@intel.com | 58ac1e7 | 2008-09-05 18:02:17 -0700 | [diff] [blame] | 58 | #include <asm/hpet.h> |
Jaswinder Singh Rajput | 2c1b284 | 2009-04-11 00:03:10 +0530 | [diff] [blame] | 59 | #include <asm/hw_irq.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 60 | |
Ingo Molnar | 7b6aa33 | 2009-02-17 13:58:15 +0100 | [diff] [blame] | 61 | #include <asm/apic.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 62 | |
Maciej W. Rozycki | 32f71af | 2008-07-21 00:52:49 +0100 | [diff] [blame] | 63 | #define __apicdebuginit(type) static type __init |
Jeremy Fitzhardinge | 136d249 | 2012-03-21 22:58:08 -0400 | [diff] [blame] | 64 | |
Cyrill Gorcunov | 2977fb3 | 2009-08-01 11:47:59 +0400 | [diff] [blame] | 65 | #define for_each_irq_pin(entry, head) \ |
| 66 | for (entry = head; entry; entry = entry->next) |
Maciej W. Rozycki | 32f71af | 2008-07-21 00:52:49 +0100 | [diff] [blame] | 67 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 68 | /* |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 69 | * Is the SiS APIC rmw bug present ? |
| 70 | * -1 = don't know, 0 = no, 1 = yes |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 71 | */ |
| 72 | int sis_apic_bug = -1; |
| 73 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 74 | static DEFINE_RAW_SPINLOCK(ioapic_lock); |
| 75 | static DEFINE_RAW_SPINLOCK(vector_lock); |
Yinghai Lu | efa2559 | 2008-08-19 20:50:36 -0700 | [diff] [blame] | 76 | |
Suresh Siddha | b69c6c3 | 2011-05-18 16:31:35 -0700 | [diff] [blame] | 77 | static struct ioapic { |
| 78 | /* |
| 79 | * # of IRQ routing registers |
| 80 | */ |
| 81 | int nr_registers; |
Suresh Siddha | 57a6f74 | 2011-05-18 16:31:36 -0700 | [diff] [blame] | 82 | /* |
| 83 | * Saved state during suspend/resume, or while enabling intr-remap. |
| 84 | */ |
| 85 | struct IO_APIC_route_entry *saved_registers; |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 86 | /* I/O APIC config */ |
| 87 | struct mpc_ioapic mp_config; |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 88 | /* IO APIC gsi routing info */ |
| 89 | struct mp_ioapic_gsi gsi_config; |
Suresh Siddha | 8f18c97 | 2011-05-18 16:31:39 -0700 | [diff] [blame] | 90 | DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); |
Suresh Siddha | b69c6c3 | 2011-05-18 16:31:35 -0700 | [diff] [blame] | 91 | } ioapics[MAX_IO_APICS]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 93 | #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 94 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 95 | int mpc_ioapic_id(int ioapic_idx) |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 96 | { |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 97 | return ioapics[ioapic_idx].mp_config.apicid; |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 98 | } |
| 99 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 100 | unsigned int mpc_ioapic_addr(int ioapic_idx) |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 101 | { |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 102 | return ioapics[ioapic_idx].mp_config.apicaddr; |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 103 | } |
| 104 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 105 | struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx) |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 106 | { |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 107 | return &ioapics[ioapic_idx].gsi_config; |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 108 | } |
Alexey Starikovskiy | 9f640cc | 2008-04-04 23:41:13 +0400 | [diff] [blame] | 109 | |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 110 | int nr_ioapics; |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 111 | |
Eric W. Biederman | a4384df | 2010-06-08 11:44:32 -0700 | [diff] [blame] | 112 | /* The one past the highest gsi number used */ |
| 113 | u32 gsi_top; |
Eric W. Biederman | 5777372 | 2010-03-30 01:07:10 -0700 | [diff] [blame] | 114 | |
Alexey Starikovskiy | 584f734 | 2008-04-04 23:41:32 +0400 | [diff] [blame] | 115 | /* MP IRQ source entries */ |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 116 | struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; |
Alexey Starikovskiy | 584f734 | 2008-04-04 23:41:32 +0400 | [diff] [blame] | 117 | |
| 118 | /* # of MP IRQ source entries */ |
| 119 | int mp_irq_entries; |
| 120 | |
Thomas Gleixner | bc07844 | 2009-08-29 18:09:57 +0200 | [diff] [blame] | 121 | /* GSI interrupts */ |
| 122 | static int nr_irqs_gsi = NR_IRQS_LEGACY; |
| 123 | |
Paul Gortmaker | bb8187d | 2012-05-17 19:06:13 -0400 | [diff] [blame] | 124 | #ifdef CONFIG_EISA |
Alexey Starikovskiy | 8732fc4 | 2008-05-19 19:47:16 +0400 | [diff] [blame] | 125 | int mp_bus_id_to_type[MAX_MP_BUSSES]; |
| 126 | #endif |
| 127 | |
| 128 | DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); |
| 129 | |
Yinghai Lu | efa2559 | 2008-08-19 20:50:36 -0700 | [diff] [blame] | 130 | int skip_ioapic_setup; |
| 131 | |
Henrik Kretzschmar | 7167d08 | 2011-02-22 15:38:05 +0100 | [diff] [blame] | 132 | /** |
| 133 | * disable_ioapic_support() - disables ioapic support at runtime |
| 134 | */ |
| 135 | void disable_ioapic_support(void) |
Ingo Molnar | 65a4e57 | 2009-01-31 03:36:17 +0100 | [diff] [blame] | 136 | { |
| 137 | #ifdef CONFIG_PCI |
| 138 | noioapicquirk = 1; |
| 139 | noioapicreroute = -1; |
| 140 | #endif |
| 141 | skip_ioapic_setup = 1; |
| 142 | } |
| 143 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 144 | static int __init parse_noapic(char *str) |
Yinghai Lu | efa2559 | 2008-08-19 20:50:36 -0700 | [diff] [blame] | 145 | { |
| 146 | /* disable IO-APIC */ |
Henrik Kretzschmar | 7167d08 | 2011-02-22 15:38:05 +0100 | [diff] [blame] | 147 | disable_ioapic_support(); |
Yinghai Lu | efa2559 | 2008-08-19 20:50:36 -0700 | [diff] [blame] | 148 | return 0; |
| 149 | } |
| 150 | early_param("noapic", parse_noapic); |
Chuck Ebbert | 66759a0 | 2005-09-12 18:49:25 +0200 | [diff] [blame] | 151 | |
Sebastian Andrzej Siewior | 2044359 | 2011-04-27 16:30:52 +0200 | [diff] [blame] | 152 | static int io_apic_setup_irq_pin(unsigned int irq, int node, |
| 153 | struct io_apic_irq_attr *attr); |
Thomas Gleixner | 710dcda | 2011-02-23 17:47:41 +0100 | [diff] [blame] | 154 | |
Feng Tang | 2d8009b | 2010-11-19 11:33:35 +0800 | [diff] [blame] | 155 | /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ |
| 156 | void mp_save_irq(struct mpc_intsrc *m) |
| 157 | { |
| 158 | int i; |
| 159 | |
| 160 | apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," |
| 161 | " IRQ %02x, APIC ID %x, APIC INT %02x\n", |
| 162 | m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, |
| 163 | m->srcbusirq, m->dstapic, m->dstirq); |
| 164 | |
| 165 | for (i = 0; i < mp_irq_entries; i++) { |
Feng Tang | 0e3fa13 | 2010-12-08 15:18:57 +0800 | [diff] [blame] | 166 | if (!memcmp(&mp_irqs[i], m, sizeof(*m))) |
Feng Tang | 2d8009b | 2010-11-19 11:33:35 +0800 | [diff] [blame] | 167 | return; |
| 168 | } |
| 169 | |
Feng Tang | 0e3fa13 | 2010-12-08 15:18:57 +0800 | [diff] [blame] | 170 | memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m)); |
Feng Tang | 2d8009b | 2010-11-19 11:33:35 +0800 | [diff] [blame] | 171 | if (++mp_irq_entries == MAX_IRQ_SOURCES) |
| 172 | panic("Max # of irq sources exceeded!!\n"); |
| 173 | } |
| 174 | |
Yinghai Lu | 0f978f4 | 2008-08-19 20:50:26 -0700 | [diff] [blame] | 175 | struct irq_pin_list { |
| 176 | int apic, pin; |
| 177 | struct irq_pin_list *next; |
| 178 | }; |
Yinghai Lu | 301e619 | 2008-08-19 20:50:02 -0700 | [diff] [blame] | 179 | |
Thomas Gleixner | 7e49552 | 2010-09-28 23:31:50 +0200 | [diff] [blame] | 180 | static struct irq_pin_list *alloc_irq_pin_list(int node) |
Yinghai Lu | 0f978f4 | 2008-08-19 20:50:26 -0700 | [diff] [blame] | 181 | { |
Thomas Gleixner | 2ee3906 | 2010-10-06 16:28:51 +0200 | [diff] [blame] | 182 | return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node); |
Yinghai Lu | 0f978f4 | 2008-08-19 20:50:26 -0700 | [diff] [blame] | 183 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 184 | |
Feng Tang | 2d8009b | 2010-11-19 11:33:35 +0800 | [diff] [blame] | 185 | |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 186 | /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ |
Suresh Siddha | 9794339 | 2010-01-19 12:20:54 -0800 | [diff] [blame] | 187 | static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 188 | |
Yinghai Lu | 13a0c3c | 2008-12-26 02:05:47 -0800 | [diff] [blame] | 189 | int __init arch_early_irq_init(void) |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 190 | { |
| 191 | struct irq_cfg *cfg; |
Thomas Gleixner | 60c6994 | 2010-09-28 17:28:38 +0200 | [diff] [blame] | 192 | int count, node, i; |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 193 | |
Jacob Pan | bb84ac2 | 2011-11-10 13:42:21 +0000 | [diff] [blame] | 194 | if (!legacy_pic->nr_legacy_irqs) |
Jacob Pan | 1f91233 | 2010-02-05 04:06:56 -0800 | [diff] [blame] | 195 | io_apic_irqs = ~0UL; |
Jacob Pan | 1f91233 | 2010-02-05 04:06:56 -0800 | [diff] [blame] | 196 | |
Suresh Siddha | 4c79185 | 2011-05-18 16:31:32 -0700 | [diff] [blame] | 197 | for (i = 0; i < nr_ioapics; i++) { |
Suresh Siddha | 57a6f74 | 2011-05-18 16:31:36 -0700 | [diff] [blame] | 198 | ioapics[i].saved_registers = |
Suresh Siddha | 4c79185 | 2011-05-18 16:31:32 -0700 | [diff] [blame] | 199 | kzalloc(sizeof(struct IO_APIC_route_entry) * |
Suresh Siddha | b69c6c3 | 2011-05-18 16:31:35 -0700 | [diff] [blame] | 200 | ioapics[i].nr_registers, GFP_KERNEL); |
Suresh Siddha | 57a6f74 | 2011-05-18 16:31:36 -0700 | [diff] [blame] | 201 | if (!ioapics[i].saved_registers) |
Suresh Siddha | 4c79185 | 2011-05-18 16:31:32 -0700 | [diff] [blame] | 202 | pr_err("IOAPIC %d: suspend/resume impossible!\n", i); |
| 203 | } |
| 204 | |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 205 | cfg = irq_cfgx; |
| 206 | count = ARRAY_SIZE(irq_cfgx); |
Robert Richter | f6e9456c | 2010-07-21 19:03:58 +0200 | [diff] [blame] | 207 | node = cpu_to_node(0); |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 208 | |
Thomas Gleixner | fbc6bff | 2010-09-28 20:34:53 +0200 | [diff] [blame] | 209 | /* Make sure the legacy interrupts are marked in the bitmap */ |
| 210 | irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs); |
| 211 | |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 212 | for (i = 0; i < count; i++) { |
Thomas Gleixner | 2c77865 | 2011-03-12 12:20:43 +0100 | [diff] [blame] | 213 | irq_set_chip_data(i, &cfg[i]); |
Thomas Gleixner | 2ee3906 | 2010-10-06 16:28:51 +0200 | [diff] [blame] | 214 | zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node); |
| 215 | zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node); |
Suresh Siddha | 9794339 | 2010-01-19 12:20:54 -0800 | [diff] [blame] | 216 | /* |
| 217 | * For legacy IRQ's, start with assigning irq0 to irq15 to |
Suresh Siddha | 29c574c | 2012-11-26 14:49:36 -0800 | [diff] [blame] | 218 | * IRQ0_VECTOR to IRQ15_VECTOR for all cpu's. |
Suresh Siddha | 9794339 | 2010-01-19 12:20:54 -0800 | [diff] [blame] | 219 | */ |
H. Peter Anvin | 54b5617 | 2010-02-22 16:25:18 -0800 | [diff] [blame] | 220 | if (i < legacy_pic->nr_legacy_irqs) { |
Suresh Siddha | 9794339 | 2010-01-19 12:20:54 -0800 | [diff] [blame] | 221 | cfg[i].vector = IRQ0_VECTOR + i; |
Suresh Siddha | 29c574c | 2012-11-26 14:49:36 -0800 | [diff] [blame] | 222 | cpumask_setall(cfg[i].domain); |
Suresh Siddha | 9794339 | 2010-01-19 12:20:54 -0800 | [diff] [blame] | 223 | } |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 224 | } |
Yinghai Lu | 13a0c3c | 2008-12-26 02:05:47 -0800 | [diff] [blame] | 225 | |
| 226 | return 0; |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 227 | } |
| 228 | |
Thomas Gleixner | 48b2650 | 2010-09-30 11:43:08 +0200 | [diff] [blame] | 229 | static struct irq_cfg *irq_cfg(unsigned int irq) |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 230 | { |
Thomas Gleixner | 2c77865 | 2011-03-12 12:20:43 +0100 | [diff] [blame] | 231 | return irq_get_chip_data(irq); |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 232 | } |
| 233 | |
Thomas Gleixner | f981a3d | 2010-10-08 10:44:21 +0200 | [diff] [blame] | 234 | static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 235 | { |
| 236 | struct irq_cfg *cfg; |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 237 | |
Thomas Gleixner | 2ee3906 | 2010-10-06 16:28:51 +0200 | [diff] [blame] | 238 | cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node); |
Thomas Gleixner | 6e2fff5 | 2010-10-06 22:07:03 +0200 | [diff] [blame] | 239 | if (!cfg) |
| 240 | return NULL; |
Thomas Gleixner | 2ee3906 | 2010-10-06 16:28:51 +0200 | [diff] [blame] | 241 | if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node)) |
Thomas Gleixner | 6e2fff5 | 2010-10-06 22:07:03 +0200 | [diff] [blame] | 242 | goto out_cfg; |
Thomas Gleixner | 2ee3906 | 2010-10-06 16:28:51 +0200 | [diff] [blame] | 243 | if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node)) |
Thomas Gleixner | 6e2fff5 | 2010-10-06 22:07:03 +0200 | [diff] [blame] | 244 | goto out_domain; |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 245 | return cfg; |
Thomas Gleixner | 6e2fff5 | 2010-10-06 22:07:03 +0200 | [diff] [blame] | 246 | out_domain: |
| 247 | free_cpumask_var(cfg->domain); |
| 248 | out_cfg: |
| 249 | kfree(cfg); |
| 250 | return NULL; |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 251 | } |
| 252 | |
Thomas Gleixner | f981a3d | 2010-10-08 10:44:21 +0200 | [diff] [blame] | 253 | static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) |
Thomas Gleixner | 08c33db | 2010-10-06 22:14:21 +0200 | [diff] [blame] | 254 | { |
Thomas Gleixner | fbc6bff | 2010-09-28 20:34:53 +0200 | [diff] [blame] | 255 | if (!cfg) |
| 256 | return; |
Thomas Gleixner | 2c77865 | 2011-03-12 12:20:43 +0100 | [diff] [blame] | 257 | irq_set_chip_data(at, NULL); |
Thomas Gleixner | 08c33db | 2010-10-06 22:14:21 +0200 | [diff] [blame] | 258 | free_cpumask_var(cfg->domain); |
| 259 | free_cpumask_var(cfg->old_domain); |
| 260 | kfree(cfg); |
| 261 | } |
| 262 | |
Thomas Gleixner | 08c33db | 2010-10-06 22:14:21 +0200 | [diff] [blame] | 263 | static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node) |
| 264 | { |
| 265 | int res = irq_alloc_desc_at(at, node); |
| 266 | struct irq_cfg *cfg; |
| 267 | |
| 268 | if (res < 0) { |
| 269 | if (res != -EEXIST) |
| 270 | return NULL; |
Thomas Gleixner | 2c77865 | 2011-03-12 12:20:43 +0100 | [diff] [blame] | 271 | cfg = irq_get_chip_data(at); |
Thomas Gleixner | 08c33db | 2010-10-06 22:14:21 +0200 | [diff] [blame] | 272 | if (cfg) |
| 273 | return cfg; |
| 274 | } |
| 275 | |
Thomas Gleixner | f981a3d | 2010-10-08 10:44:21 +0200 | [diff] [blame] | 276 | cfg = alloc_irq_cfg(at, node); |
Thomas Gleixner | 08c33db | 2010-10-06 22:14:21 +0200 | [diff] [blame] | 277 | if (cfg) |
Thomas Gleixner | 2c77865 | 2011-03-12 12:20:43 +0100 | [diff] [blame] | 278 | irq_set_chip_data(at, cfg); |
Thomas Gleixner | 08c33db | 2010-10-06 22:14:21 +0200 | [diff] [blame] | 279 | else |
| 280 | irq_free_desc(at); |
| 281 | return cfg; |
| 282 | } |
| 283 | |
Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 284 | static int alloc_irqs_from(unsigned int from, unsigned int count, int node) |
Thomas Gleixner | 08c33db | 2010-10-06 22:14:21 +0200 | [diff] [blame] | 285 | { |
Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 286 | return irq_alloc_descs_from(from, count, node); |
Thomas Gleixner | 08c33db | 2010-10-06 22:14:21 +0200 | [diff] [blame] | 287 | } |
| 288 | |
| 289 | static void free_irq_at(unsigned int at, struct irq_cfg *cfg) |
| 290 | { |
Thomas Gleixner | f981a3d | 2010-10-08 10:44:21 +0200 | [diff] [blame] | 291 | free_irq_cfg(at, cfg); |
Thomas Gleixner | 08c33db | 2010-10-06 22:14:21 +0200 | [diff] [blame] | 292 | irq_free_desc(at); |
| 293 | } |
| 294 | |
Jeremy Fitzhardinge | 136d249 | 2012-03-21 22:58:08 -0400 | [diff] [blame] | 295 | |
Linus Torvalds | 130fe05 | 2006-11-01 09:11:00 -0800 | [diff] [blame] | 296 | struct io_apic { |
| 297 | unsigned int index; |
| 298 | unsigned int unused[3]; |
| 299 | unsigned int data; |
Suresh Siddha | 0280f7c | 2009-03-16 17:05:01 -0700 | [diff] [blame] | 300 | unsigned int unused2[11]; |
| 301 | unsigned int eoi; |
Linus Torvalds | 130fe05 | 2006-11-01 09:11:00 -0800 | [diff] [blame] | 302 | }; |
| 303 | |
| 304 | static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) |
| 305 | { |
| 306 | return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 307 | + (mpc_ioapic_addr(idx) & ~PAGE_MASK); |
Linus Torvalds | 130fe05 | 2006-11-01 09:11:00 -0800 | [diff] [blame] | 308 | } |
| 309 | |
Joerg Roedel | da16532 | 2012-09-26 12:44:50 +0200 | [diff] [blame] | 310 | void io_apic_eoi(unsigned int apic, unsigned int vector) |
Suresh Siddha | 0280f7c | 2009-03-16 17:05:01 -0700 | [diff] [blame] | 311 | { |
| 312 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
| 313 | writel(vector, &io_apic->eoi); |
| 314 | } |
| 315 | |
Konrad Rzeszutek Wilk | 4a8e2a3 | 2012-03-28 12:37:36 -0400 | [diff] [blame] | 316 | unsigned int native_io_apic_read(unsigned int apic, unsigned int reg) |
Linus Torvalds | 130fe05 | 2006-11-01 09:11:00 -0800 | [diff] [blame] | 317 | { |
| 318 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
| 319 | writel(reg, &io_apic->index); |
| 320 | return readl(&io_apic->data); |
| 321 | } |
| 322 | |
Konrad Rzeszutek Wilk | 4a8e2a3 | 2012-03-28 12:37:36 -0400 | [diff] [blame] | 323 | void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) |
Linus Torvalds | 130fe05 | 2006-11-01 09:11:00 -0800 | [diff] [blame] | 324 | { |
| 325 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
Jeremy Fitzhardinge | 136d249 | 2012-03-21 22:58:08 -0400 | [diff] [blame] | 326 | |
Linus Torvalds | 130fe05 | 2006-11-01 09:11:00 -0800 | [diff] [blame] | 327 | writel(reg, &io_apic->index); |
| 328 | writel(value, &io_apic->data); |
| 329 | } |
| 330 | |
| 331 | /* |
| 332 | * Re-write a value: to be used for read-modify-write |
| 333 | * cycles where the read already set up the index register. |
| 334 | * |
| 335 | * Older SiS APIC requires we rewrite the index register |
| 336 | */ |
Konrad Rzeszutek Wilk | 4a8e2a3 | 2012-03-28 12:37:36 -0400 | [diff] [blame] | 337 | void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) |
Linus Torvalds | 130fe05 | 2006-11-01 09:11:00 -0800 | [diff] [blame] | 338 | { |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 339 | struct io_apic __iomem *io_apic = io_apic_base(apic); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 340 | |
| 341 | if (sis_apic_bug) |
| 342 | writel(reg, &io_apic->index); |
Linus Torvalds | 130fe05 | 2006-11-01 09:11:00 -0800 | [diff] [blame] | 343 | writel(value, &io_apic->data); |
| 344 | } |
| 345 | |
Andi Kleen | cf4c6a2 | 2006-09-26 10:52:30 +0200 | [diff] [blame] | 346 | union entry_union { |
| 347 | struct { u32 w1, w2; }; |
| 348 | struct IO_APIC_route_entry entry; |
| 349 | }; |
| 350 | |
Suresh Siddha | e57253a | 2011-08-25 12:01:12 -0700 | [diff] [blame] | 351 | static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) |
| 352 | { |
| 353 | union entry_union eu; |
| 354 | |
| 355 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); |
| 356 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); |
Jeremy Fitzhardinge | 136d249 | 2012-03-21 22:58:08 -0400 | [diff] [blame] | 357 | |
Suresh Siddha | e57253a | 2011-08-25 12:01:12 -0700 | [diff] [blame] | 358 | return eu.entry; |
| 359 | } |
| 360 | |
Andi Kleen | cf4c6a2 | 2006-09-26 10:52:30 +0200 | [diff] [blame] | 361 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) |
| 362 | { |
| 363 | union entry_union eu; |
| 364 | unsigned long flags; |
Jeremy Fitzhardinge | 136d249 | 2012-03-21 22:58:08 -0400 | [diff] [blame] | 365 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 366 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Suresh Siddha | e57253a | 2011-08-25 12:01:12 -0700 | [diff] [blame] | 367 | eu.entry = __ioapic_read_entry(apic, pin); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 368 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Jeremy Fitzhardinge | 136d249 | 2012-03-21 22:58:08 -0400 | [diff] [blame] | 369 | |
Andi Kleen | cf4c6a2 | 2006-09-26 10:52:30 +0200 | [diff] [blame] | 370 | return eu.entry; |
| 371 | } |
| 372 | |
Linus Torvalds | f9dadfa | 2006-11-01 10:05:35 -0800 | [diff] [blame] | 373 | /* |
| 374 | * When we write a new IO APIC routing entry, we need to write the high |
| 375 | * word first! If the mask bit in the low word is clear, we will enable |
| 376 | * the interrupt, and we need to make sure the entry is fully populated |
| 377 | * before that happens. |
| 378 | */ |
Jeremy Fitzhardinge | 136d249 | 2012-03-21 22:58:08 -0400 | [diff] [blame] | 379 | static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
Andi Kleen | d15512f | 2006-12-07 02:14:07 +0100 | [diff] [blame] | 380 | { |
Figo.zhang | 50a8d4d | 2009-06-17 22:25:20 +0800 | [diff] [blame] | 381 | union entry_union eu = {{0, 0}}; |
| 382 | |
Andi Kleen | d15512f | 2006-12-07 02:14:07 +0100 | [diff] [blame] | 383 | eu.entry = e; |
| 384 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
| 385 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
| 386 | } |
| 387 | |
Thomas Gleixner | 1a8ce7f | 2010-10-04 21:08:56 +0200 | [diff] [blame] | 388 | static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) |
Andi Kleen | cf4c6a2 | 2006-09-26 10:52:30 +0200 | [diff] [blame] | 389 | { |
| 390 | unsigned long flags; |
Jeremy Fitzhardinge | 136d249 | 2012-03-21 22:58:08 -0400 | [diff] [blame] | 391 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 392 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Andi Kleen | d15512f | 2006-12-07 02:14:07 +0100 | [diff] [blame] | 393 | __ioapic_write_entry(apic, pin, e); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 394 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Linus Torvalds | f9dadfa | 2006-11-01 10:05:35 -0800 | [diff] [blame] | 395 | } |
| 396 | |
| 397 | /* |
| 398 | * When we mask an IO APIC routing entry, we need to write the low |
| 399 | * word first, in order to set the mask bit before we change the |
| 400 | * high bits! |
| 401 | */ |
| 402 | static void ioapic_mask_entry(int apic, int pin) |
| 403 | { |
| 404 | unsigned long flags; |
| 405 | union entry_union eu = { .entry.mask = 1 }; |
| 406 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 407 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Andi Kleen | cf4c6a2 | 2006-09-26 10:52:30 +0200 | [diff] [blame] | 408 | io_apic_write(apic, 0x10 + 2*pin, eu.w1); |
| 409 | io_apic_write(apic, 0x11 + 2*pin, eu.w2); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 410 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Andi Kleen | cf4c6a2 | 2006-09-26 10:52:30 +0200 | [diff] [blame] | 411 | } |
| 412 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 413 | /* |
| 414 | * The common case is 1:1 IRQ<->pin mappings. Sometimes there are |
| 415 | * shared ISA-space IRQs, so we have to support them. We are super |
| 416 | * fast in the common case, and fast for shared ISA-space IRQs. |
| 417 | */ |
Jeremy Fitzhardinge | 136d249 | 2012-03-21 22:58:08 -0400 | [diff] [blame] | 418 | static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 419 | { |
Cyrill Gorcunov | 2977fb3 | 2009-08-01 11:47:59 +0400 | [diff] [blame] | 420 | struct irq_pin_list **last, *entry; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 421 | |
Cyrill Gorcunov | 2977fb3 | 2009-08-01 11:47:59 +0400 | [diff] [blame] | 422 | /* don't allow duplicates */ |
| 423 | last = &cfg->irq_2_pin; |
| 424 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
Yinghai Lu | 0f978f4 | 2008-08-19 20:50:26 -0700 | [diff] [blame] | 425 | if (entry->apic == apic && entry->pin == pin) |
Cyrill Gorcunov | f3d1915 | 2009-08-06 00:09:31 +0400 | [diff] [blame] | 426 | return 0; |
Cyrill Gorcunov | 2977fb3 | 2009-08-01 11:47:59 +0400 | [diff] [blame] | 427 | last = &entry->next; |
Yinghai Lu | 0f978f4 | 2008-08-19 20:50:26 -0700 | [diff] [blame] | 428 | } |
| 429 | |
Thomas Gleixner | 7e49552 | 2010-09-28 23:31:50 +0200 | [diff] [blame] | 430 | entry = alloc_irq_pin_list(node); |
Cyrill Gorcunov | a7428cd | 2009-08-01 11:48:00 +0400 | [diff] [blame] | 431 | if (!entry) { |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 432 | pr_err("can not alloc irq_pin_list (%d,%d,%d)\n", |
| 433 | node, apic, pin); |
Cyrill Gorcunov | f3d1915 | 2009-08-06 00:09:31 +0400 | [diff] [blame] | 434 | return -ENOMEM; |
Cyrill Gorcunov | a7428cd | 2009-08-01 11:48:00 +0400 | [diff] [blame] | 435 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 436 | entry->apic = apic; |
| 437 | entry->pin = pin; |
Jeremy Fitzhardinge | 875e68e | 2009-06-08 03:24:11 -0700 | [diff] [blame] | 438 | |
Cyrill Gorcunov | 2977fb3 | 2009-08-01 11:47:59 +0400 | [diff] [blame] | 439 | *last = entry; |
Cyrill Gorcunov | f3d1915 | 2009-08-06 00:09:31 +0400 | [diff] [blame] | 440 | return 0; |
| 441 | } |
| 442 | |
| 443 | static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) |
| 444 | { |
Thomas Gleixner | 7e49552 | 2010-09-28 23:31:50 +0200 | [diff] [blame] | 445 | if (__add_pin_to_irq_node(cfg, node, apic, pin)) |
Cyrill Gorcunov | f3d1915 | 2009-08-06 00:09:31 +0400 | [diff] [blame] | 446 | panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 447 | } |
| 448 | |
| 449 | /* |
| 450 | * Reroute an IRQ to a different pin. |
| 451 | */ |
Yinghai Lu | 85ac16d | 2009-04-27 18:00:38 -0700 | [diff] [blame] | 452 | static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, |
Jeremy Fitzhardinge | 4eea6ff | 2009-06-08 03:32:15 -0700 | [diff] [blame] | 453 | int oldapic, int oldpin, |
| 454 | int newapic, int newpin) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 455 | { |
Jeremy Fitzhardinge | 535b642 | 2009-06-08 03:29:26 -0700 | [diff] [blame] | 456 | struct irq_pin_list *entry; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 457 | |
Cyrill Gorcunov | 2977fb3 | 2009-08-01 11:47:59 +0400 | [diff] [blame] | 458 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 459 | if (entry->apic == oldapic && entry->pin == oldpin) { |
| 460 | entry->apic = newapic; |
| 461 | entry->pin = newpin; |
Yinghai Lu | 0f978f4 | 2008-08-19 20:50:26 -0700 | [diff] [blame] | 462 | /* every one is different, right? */ |
Jeremy Fitzhardinge | 4eea6ff | 2009-06-08 03:32:15 -0700 | [diff] [blame] | 463 | return; |
Yinghai Lu | 0f978f4 | 2008-08-19 20:50:26 -0700 | [diff] [blame] | 464 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 465 | } |
Yinghai Lu | 0f978f4 | 2008-08-19 20:50:26 -0700 | [diff] [blame] | 466 | |
Jeremy Fitzhardinge | 4eea6ff | 2009-06-08 03:32:15 -0700 | [diff] [blame] | 467 | /* old apic/pin didn't exist, so just add new ones */ |
| 468 | add_pin_to_irq_node(cfg, node, newapic, newpin); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 469 | } |
| 470 | |
Suresh Siddha | c29d9db | 2009-12-01 15:31:16 -0800 | [diff] [blame] | 471 | static void __io_apic_modify_irq(struct irq_pin_list *entry, |
| 472 | int mask_and, int mask_or, |
| 473 | void (*final)(struct irq_pin_list *entry)) |
| 474 | { |
| 475 | unsigned int reg, pin; |
| 476 | |
| 477 | pin = entry->pin; |
| 478 | reg = io_apic_read(entry->apic, 0x10 + pin * 2); |
| 479 | reg &= mask_and; |
| 480 | reg |= mask_or; |
| 481 | io_apic_modify(entry->apic, 0x10 + pin * 2, reg); |
| 482 | if (final) |
| 483 | final(entry); |
| 484 | } |
| 485 | |
Jeremy Fitzhardinge | 2f210de | 2009-06-08 02:55:22 -0700 | [diff] [blame] | 486 | static void io_apic_modify_irq(struct irq_cfg *cfg, |
| 487 | int mask_and, int mask_or, |
| 488 | void (*final)(struct irq_pin_list *entry)) |
Cyrill Gorcunov | 87783be | 2008-09-10 22:19:50 +0400 | [diff] [blame] | 489 | { |
Cyrill Gorcunov | 87783be | 2008-09-10 22:19:50 +0400 | [diff] [blame] | 490 | struct irq_pin_list *entry; |
| 491 | |
Suresh Siddha | c29d9db | 2009-12-01 15:31:16 -0800 | [diff] [blame] | 492 | for_each_irq_pin(entry, cfg->irq_2_pin) |
| 493 | __io_apic_modify_irq(entry, mask_and, mask_or, final); |
| 494 | } |
| 495 | |
Jaswinder Singh Rajput | 7f3e632 | 2008-12-29 20:34:35 +0530 | [diff] [blame] | 496 | static void io_apic_sync(struct irq_pin_list *entry) |
Yinghai Lu | 4e738e2 | 2008-08-19 20:50:47 -0700 | [diff] [blame] | 497 | { |
Cyrill Gorcunov | 87783be | 2008-09-10 22:19:50 +0400 | [diff] [blame] | 498 | /* |
| 499 | * Synchronize the IO-APIC and the CPU by doing |
| 500 | * a dummy read from the IO-APIC |
| 501 | */ |
| 502 | struct io_apic __iomem *io_apic; |
Jeremy Fitzhardinge | 136d249 | 2012-03-21 22:58:08 -0400 | [diff] [blame] | 503 | |
Cyrill Gorcunov | 87783be | 2008-09-10 22:19:50 +0400 | [diff] [blame] | 504 | io_apic = io_apic_base(entry->apic); |
Yinghai Lu | 4e738e2 | 2008-08-19 20:50:47 -0700 | [diff] [blame] | 505 | readl(&io_apic->data); |
| 506 | } |
| 507 | |
Thomas Gleixner | dd5f15e | 2010-09-28 15:18:35 +0200 | [diff] [blame] | 508 | static void mask_ioapic(struct irq_cfg *cfg) |
Cyrill Gorcunov | 87783be | 2008-09-10 22:19:50 +0400 | [diff] [blame] | 509 | { |
Thomas Gleixner | dd5f15e | 2010-09-28 15:18:35 +0200 | [diff] [blame] | 510 | unsigned long flags; |
| 511 | |
| 512 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Yinghai Lu | 3145e94 | 2008-12-05 18:58:34 -0800 | [diff] [blame] | 513 | io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 514 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 515 | } |
| 516 | |
Thomas Gleixner | 90297c5 | 2010-09-28 16:03:54 +0200 | [diff] [blame] | 517 | static void mask_ioapic_irq(struct irq_data *data) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 518 | { |
Thomas Gleixner | 90297c5 | 2010-09-28 16:03:54 +0200 | [diff] [blame] | 519 | mask_ioapic(data->chip_data); |
Thomas Gleixner | dd5f15e | 2010-09-28 15:18:35 +0200 | [diff] [blame] | 520 | } |
| 521 | |
| 522 | static void __unmask_ioapic(struct irq_cfg *cfg) |
| 523 | { |
| 524 | io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); |
| 525 | } |
| 526 | |
| 527 | static void unmask_ioapic(struct irq_cfg *cfg) |
| 528 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 529 | unsigned long flags; |
| 530 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 531 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Thomas Gleixner | dd5f15e | 2010-09-28 15:18:35 +0200 | [diff] [blame] | 532 | __unmask_ioapic(cfg); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 533 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 534 | } |
| 535 | |
Thomas Gleixner | 90297c5 | 2010-09-28 16:03:54 +0200 | [diff] [blame] | 536 | static void unmask_ioapic_irq(struct irq_data *data) |
Yinghai Lu | 3145e94 | 2008-12-05 18:58:34 -0800 | [diff] [blame] | 537 | { |
Thomas Gleixner | 90297c5 | 2010-09-28 16:03:54 +0200 | [diff] [blame] | 538 | unmask_ioapic(data->chip_data); |
Yinghai Lu | 3145e94 | 2008-12-05 18:58:34 -0800 | [diff] [blame] | 539 | } |
| 540 | |
Suresh Siddha | c020570 | 2011-08-25 12:01:13 -0700 | [diff] [blame] | 541 | /* |
| 542 | * IO-APIC versions below 0x20 don't support EOI register. |
| 543 | * For the record, here is the information about various versions: |
| 544 | * 0Xh 82489DX |
| 545 | * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant |
| 546 | * 2Xh I/O(x)APIC which is PCI 2.2 Compliant |
| 547 | * 30h-FFh Reserved |
| 548 | * |
| 549 | * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic |
| 550 | * version as 0x2. This is an error with documentation and these ICH chips |
| 551 | * use io-apic's of version 0x20. |
| 552 | * |
| 553 | * For IO-APIC's with EOI register, we use that to do an explicit EOI. |
| 554 | * Otherwise, we simulate the EOI message manually by changing the trigger |
| 555 | * mode to edge and then back to level, with RTE being masked during this. |
| 556 | */ |
Joerg Roedel | da16532 | 2012-09-26 12:44:50 +0200 | [diff] [blame] | 557 | void native_eoi_ioapic_pin(int apic, int pin, int vector) |
Suresh Siddha | c020570 | 2011-08-25 12:01:13 -0700 | [diff] [blame] | 558 | { |
| 559 | if (mpc_ioapic_ver(apic) >= 0x20) { |
Joerg Roedel | da16532 | 2012-09-26 12:44:50 +0200 | [diff] [blame] | 560 | io_apic_eoi(apic, vector); |
Suresh Siddha | c020570 | 2011-08-25 12:01:13 -0700 | [diff] [blame] | 561 | } else { |
| 562 | struct IO_APIC_route_entry entry, entry1; |
| 563 | |
| 564 | entry = entry1 = __ioapic_read_entry(apic, pin); |
| 565 | |
| 566 | /* |
| 567 | * Mask the entry and change the trigger mode to edge. |
| 568 | */ |
| 569 | entry1.mask = 1; |
| 570 | entry1.trigger = IOAPIC_EDGE; |
| 571 | |
| 572 | __ioapic_write_entry(apic, pin, entry1); |
| 573 | |
| 574 | /* |
| 575 | * Restore the previous level triggered entry. |
| 576 | */ |
| 577 | __ioapic_write_entry(apic, pin, entry); |
| 578 | } |
| 579 | } |
| 580 | |
Joerg Roedel | 9b1b0e4 | 2012-09-26 12:44:45 +0200 | [diff] [blame] | 581 | void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) |
Suresh Siddha | c020570 | 2011-08-25 12:01:13 -0700 | [diff] [blame] | 582 | { |
| 583 | struct irq_pin_list *entry; |
| 584 | unsigned long flags; |
| 585 | |
| 586 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
| 587 | for_each_irq_pin(entry, cfg->irq_2_pin) |
Joerg Roedel | da16532 | 2012-09-26 12:44:50 +0200 | [diff] [blame] | 588 | x86_io_apic_ops.eoi_ioapic_pin(entry->apic, entry->pin, |
| 589 | cfg->vector); |
Suresh Siddha | c020570 | 2011-08-25 12:01:13 -0700 | [diff] [blame] | 590 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
| 591 | } |
| 592 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 593 | static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) |
| 594 | { |
| 595 | struct IO_APIC_route_entry entry; |
Paolo Ciarrocchi | 3606244 | 2008-06-08 13:07:18 +0200 | [diff] [blame] | 596 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 597 | /* Check delivery_mode to be sure we're not clearing an SMI pin */ |
Andi Kleen | cf4c6a2 | 2006-09-26 10:52:30 +0200 | [diff] [blame] | 598 | entry = ioapic_read_entry(apic, pin); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 599 | if (entry.delivery_mode == dest_SMI) |
| 600 | return; |
Suresh Siddha | 1e75b31 | 2011-08-25 12:01:11 -0700 | [diff] [blame] | 601 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 602 | /* |
Suresh Siddha | 1e75b31 | 2011-08-25 12:01:11 -0700 | [diff] [blame] | 603 | * Make sure the entry is masked and re-read the contents to check |
| 604 | * if it is a level triggered pin and if the remote-IRR is set. |
| 605 | */ |
| 606 | if (!entry.mask) { |
| 607 | entry.mask = 1; |
| 608 | ioapic_write_entry(apic, pin, entry); |
| 609 | entry = ioapic_read_entry(apic, pin); |
| 610 | } |
| 611 | |
| 612 | if (entry.irr) { |
Suresh Siddha | c020570 | 2011-08-25 12:01:13 -0700 | [diff] [blame] | 613 | unsigned long flags; |
| 614 | |
Suresh Siddha | 1e75b31 | 2011-08-25 12:01:11 -0700 | [diff] [blame] | 615 | /* |
| 616 | * Make sure the trigger mode is set to level. Explicit EOI |
| 617 | * doesn't clear the remote-IRR if the trigger mode is not |
| 618 | * set to level. |
| 619 | */ |
| 620 | if (!entry.trigger) { |
| 621 | entry.trigger = IOAPIC_LEVEL; |
| 622 | ioapic_write_entry(apic, pin, entry); |
| 623 | } |
| 624 | |
Suresh Siddha | c020570 | 2011-08-25 12:01:13 -0700 | [diff] [blame] | 625 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Joerg Roedel | da16532 | 2012-09-26 12:44:50 +0200 | [diff] [blame] | 626 | x86_io_apic_ops.eoi_ioapic_pin(apic, pin, entry.vector); |
Suresh Siddha | c020570 | 2011-08-25 12:01:13 -0700 | [diff] [blame] | 627 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Suresh Siddha | 1e75b31 | 2011-08-25 12:01:11 -0700 | [diff] [blame] | 628 | } |
| 629 | |
| 630 | /* |
| 631 | * Clear the rest of the bits in the IO-APIC RTE except for the mask |
| 632 | * bit. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 633 | */ |
Linus Torvalds | f9dadfa | 2006-11-01 10:05:35 -0800 | [diff] [blame] | 634 | ioapic_mask_entry(apic, pin); |
Suresh Siddha | 1e75b31 | 2011-08-25 12:01:11 -0700 | [diff] [blame] | 635 | entry = ioapic_read_entry(apic, pin); |
| 636 | if (entry.irr) |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 637 | pr_err("Unable to reset IRR for apic: %d, pin :%d\n", |
Suresh Siddha | 1e75b31 | 2011-08-25 12:01:11 -0700 | [diff] [blame] | 638 | mpc_ioapic_id(apic), pin); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 639 | } |
| 640 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 641 | static void clear_IO_APIC (void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 642 | { |
| 643 | int apic, pin; |
| 644 | |
| 645 | for (apic = 0; apic < nr_ioapics; apic++) |
Suresh Siddha | b69c6c3 | 2011-05-18 16:31:35 -0700 | [diff] [blame] | 646 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 647 | clear_IO_APIC_pin(apic, pin); |
| 648 | } |
| 649 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 650 | #ifdef CONFIG_X86_32 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 651 | /* |
| 652 | * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to |
| 653 | * specific CPU-side IRQs. |
| 654 | */ |
| 655 | |
| 656 | #define MAX_PIRQS 8 |
Yinghai Lu | 3bd25d0 | 2009-02-15 02:54:03 -0800 | [diff] [blame] | 657 | static int pirq_entries[MAX_PIRQS] = { |
| 658 | [0 ... MAX_PIRQS - 1] = -1 |
| 659 | }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 660 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 661 | static int __init ioapic_pirq_setup(char *str) |
| 662 | { |
| 663 | int i, max; |
| 664 | int ints[MAX_PIRQS+1]; |
| 665 | |
| 666 | get_options(str, ARRAY_SIZE(ints), ints); |
| 667 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 668 | apic_printk(APIC_VERBOSE, KERN_INFO |
| 669 | "PIRQ redirection, working around broken MP-BIOS.\n"); |
| 670 | max = MAX_PIRQS; |
| 671 | if (ints[0] < MAX_PIRQS) |
| 672 | max = ints[0]; |
| 673 | |
| 674 | for (i = 0; i < max; i++) { |
| 675 | apic_printk(APIC_VERBOSE, KERN_DEBUG |
| 676 | "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); |
| 677 | /* |
| 678 | * PIRQs are mapped upside down, usually. |
| 679 | */ |
| 680 | pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; |
| 681 | } |
| 682 | return 1; |
| 683 | } |
| 684 | |
| 685 | __setup("pirq=", ioapic_pirq_setup); |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 686 | #endif /* CONFIG_X86_32 */ |
| 687 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 688 | /* |
Suresh Siddha | 05c3dc2 | 2009-03-16 17:05:03 -0700 | [diff] [blame] | 689 | * Saves all the IO-APIC RTE's |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 690 | */ |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 691 | int save_ioapic_entries(void) |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 692 | { |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 693 | int apic, pin; |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 694 | int err = 0; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 695 | |
| 696 | for (apic = 0; apic < nr_ioapics; apic++) { |
Suresh Siddha | 57a6f74 | 2011-05-18 16:31:36 -0700 | [diff] [blame] | 697 | if (!ioapics[apic].saved_registers) { |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 698 | err = -ENOMEM; |
| 699 | continue; |
| 700 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 701 | |
Suresh Siddha | b69c6c3 | 2011-05-18 16:31:35 -0700 | [diff] [blame] | 702 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) |
Suresh Siddha | 57a6f74 | 2011-05-18 16:31:36 -0700 | [diff] [blame] | 703 | ioapics[apic].saved_registers[pin] = |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 704 | ioapic_read_entry(apic, pin); |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 705 | } |
Cyrill Gorcunov | 5ffa4eb | 2008-09-18 23:37:57 +0400 | [diff] [blame] | 706 | |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 707 | return err; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 708 | } |
| 709 | |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 710 | /* |
| 711 | * Mask all IO APIC entries. |
| 712 | */ |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 713 | void mask_ioapic_entries(void) |
Suresh Siddha | 05c3dc2 | 2009-03-16 17:05:03 -0700 | [diff] [blame] | 714 | { |
| 715 | int apic, pin; |
| 716 | |
| 717 | for (apic = 0; apic < nr_ioapics; apic++) { |
Suresh Siddha | 2f344d2 | 2011-05-24 10:45:31 -0700 | [diff] [blame] | 718 | if (!ioapics[apic].saved_registers) |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 719 | continue; |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 720 | |
Suresh Siddha | b69c6c3 | 2011-05-18 16:31:35 -0700 | [diff] [blame] | 721 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { |
Suresh Siddha | 05c3dc2 | 2009-03-16 17:05:03 -0700 | [diff] [blame] | 722 | struct IO_APIC_route_entry entry; |
| 723 | |
Suresh Siddha | 57a6f74 | 2011-05-18 16:31:36 -0700 | [diff] [blame] | 724 | entry = ioapics[apic].saved_registers[pin]; |
Suresh Siddha | 05c3dc2 | 2009-03-16 17:05:03 -0700 | [diff] [blame] | 725 | if (!entry.mask) { |
| 726 | entry.mask = 1; |
| 727 | ioapic_write_entry(apic, pin, entry); |
| 728 | } |
| 729 | } |
| 730 | } |
| 731 | } |
| 732 | |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 733 | /* |
Suresh Siddha | 57a6f74 | 2011-05-18 16:31:36 -0700 | [diff] [blame] | 734 | * Restore IO APIC entries which was saved in the ioapic structure. |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 735 | */ |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 736 | int restore_ioapic_entries(void) |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 737 | { |
| 738 | int apic, pin; |
| 739 | |
Cyrill Gorcunov | 5ffa4eb | 2008-09-18 23:37:57 +0400 | [diff] [blame] | 740 | for (apic = 0; apic < nr_ioapics; apic++) { |
Suresh Siddha | 2f344d2 | 2011-05-24 10:45:31 -0700 | [diff] [blame] | 741 | if (!ioapics[apic].saved_registers) |
Suresh Siddha | 31dce14 | 2011-05-18 16:31:33 -0700 | [diff] [blame] | 742 | continue; |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 743 | |
Suresh Siddha | b69c6c3 | 2011-05-18 16:31:35 -0700 | [diff] [blame] | 744 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 745 | ioapic_write_entry(apic, pin, |
Suresh Siddha | 57a6f74 | 2011-05-18 16:31:36 -0700 | [diff] [blame] | 746 | ioapics[apic].saved_registers[pin]); |
Cyrill Gorcunov | 5ffa4eb | 2008-09-18 23:37:57 +0400 | [diff] [blame] | 747 | } |
Fenghua Yu | b24696b | 2009-03-27 14:22:44 -0700 | [diff] [blame] | 748 | return 0; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 749 | } |
| 750 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 751 | /* |
| 752 | * Find the IRQ entry number of a certain pin. |
| 753 | */ |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 754 | static int find_irq_entry(int ioapic_idx, int pin, int type) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 755 | { |
| 756 | int i; |
| 757 | |
| 758 | for (i = 0; i < mp_irq_entries; i++) |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 759 | if (mp_irqs[i].irqtype == type && |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 760 | (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) || |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 761 | mp_irqs[i].dstapic == MP_APIC_ALL) && |
| 762 | mp_irqs[i].dstirq == pin) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 763 | return i; |
| 764 | |
| 765 | return -1; |
| 766 | } |
| 767 | |
| 768 | /* |
| 769 | * Find the pin to which IRQ[irq] (ISA) is connected |
| 770 | */ |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 771 | static int __init find_isa_irq_pin(int irq, int type) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 772 | { |
| 773 | int i; |
| 774 | |
| 775 | for (i = 0; i < mp_irq_entries; i++) { |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 776 | int lbus = mp_irqs[i].srcbus; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 777 | |
Alexey Starikovskiy | d27e2b8 | 2008-03-20 14:54:18 +0300 | [diff] [blame] | 778 | if (test_bit(lbus, mp_bus_not_pci) && |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 779 | (mp_irqs[i].irqtype == type) && |
| 780 | (mp_irqs[i].srcbusirq == irq)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 781 | |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 782 | return mp_irqs[i].dstirq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 783 | } |
| 784 | return -1; |
| 785 | } |
| 786 | |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 787 | static int __init find_isa_irq_apic(int irq, int type) |
| 788 | { |
| 789 | int i; |
| 790 | |
| 791 | for (i = 0; i < mp_irq_entries; i++) { |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 792 | int lbus = mp_irqs[i].srcbus; |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 793 | |
Alexey Starikovskiy | 73b2961 | 2008-03-20 14:54:24 +0300 | [diff] [blame] | 794 | if (test_bit(lbus, mp_bus_not_pci) && |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 795 | (mp_irqs[i].irqtype == type) && |
| 796 | (mp_irqs[i].srcbusirq == irq)) |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 797 | break; |
| 798 | } |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 799 | |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 800 | if (i < mp_irq_entries) { |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 801 | int ioapic_idx; |
| 802 | |
| 803 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) |
| 804 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic) |
| 805 | return ioapic_idx; |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 806 | } |
| 807 | |
| 808 | return -1; |
| 809 | } |
| 810 | |
Paul Gortmaker | bb8187d | 2012-05-17 19:06:13 -0400 | [diff] [blame] | 811 | #ifdef CONFIG_EISA |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 812 | /* |
| 813 | * EISA Edge/Level control register, ELCR |
| 814 | */ |
| 815 | static int EISA_ELCR(unsigned int irq) |
| 816 | { |
Jacob Pan | b81bb37 | 2009-11-09 11:27:04 -0800 | [diff] [blame] | 817 | if (irq < legacy_pic->nr_legacy_irqs) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 818 | unsigned int port = 0x4d0 + (irq >> 3); |
| 819 | return (inb(port) >> (irq & 7)) & 1; |
| 820 | } |
| 821 | apic_printk(APIC_VERBOSE, KERN_INFO |
| 822 | "Broken MPtable reports ISA irq %d\n", irq); |
| 823 | return 0; |
| 824 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 825 | |
Alexey Starikovskiy | c0a282c | 2008-03-20 14:55:02 +0300 | [diff] [blame] | 826 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 827 | |
Alexey Starikovskiy | 6728801 | 2008-03-20 14:54:36 +0300 | [diff] [blame] | 828 | /* ISA interrupts are always polarity zero edge triggered, |
| 829 | * when listed as conforming in the MP table. */ |
| 830 | |
| 831 | #define default_ISA_trigger(idx) (0) |
| 832 | #define default_ISA_polarity(idx) (0) |
| 833 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 834 | /* EISA interrupts are always polarity zero and can be edge or level |
| 835 | * trigger depending on the ELCR value. If an interrupt is listed as |
| 836 | * EISA conforming in the MP table, that means its trigger type must |
| 837 | * be read in from the ELCR */ |
| 838 | |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 839 | #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) |
Alexey Starikovskiy | 6728801 | 2008-03-20 14:54:36 +0300 | [diff] [blame] | 840 | #define default_EISA_polarity(idx) default_ISA_polarity(idx) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 841 | |
| 842 | /* PCI interrupts are always polarity one level triggered, |
| 843 | * when listed as conforming in the MP table. */ |
| 844 | |
| 845 | #define default_PCI_trigger(idx) (1) |
| 846 | #define default_PCI_polarity(idx) (1) |
| 847 | |
Thomas Gleixner | b77cf6a | 2011-02-23 17:33:53 +0100 | [diff] [blame] | 848 | static int irq_polarity(int idx) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 849 | { |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 850 | int bus = mp_irqs[idx].srcbus; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 851 | int polarity; |
| 852 | |
| 853 | /* |
| 854 | * Determine IRQ line polarity (high active or low active): |
| 855 | */ |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 856 | switch (mp_irqs[idx].irqflag & 3) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 857 | { |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 858 | case 0: /* conforms, ie. bus-type dependent polarity */ |
| 859 | if (test_bit(bus, mp_bus_not_pci)) |
| 860 | polarity = default_ISA_polarity(idx); |
| 861 | else |
| 862 | polarity = default_PCI_polarity(idx); |
| 863 | break; |
| 864 | case 1: /* high active */ |
| 865 | { |
| 866 | polarity = 0; |
| 867 | break; |
| 868 | } |
| 869 | case 2: /* reserved */ |
| 870 | { |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 871 | pr_warn("broken BIOS!!\n"); |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 872 | polarity = 1; |
| 873 | break; |
| 874 | } |
| 875 | case 3: /* low active */ |
| 876 | { |
| 877 | polarity = 1; |
| 878 | break; |
| 879 | } |
| 880 | default: /* invalid */ |
| 881 | { |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 882 | pr_warn("broken BIOS!!\n"); |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 883 | polarity = 1; |
| 884 | break; |
| 885 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 886 | } |
| 887 | return polarity; |
| 888 | } |
| 889 | |
Thomas Gleixner | b77cf6a | 2011-02-23 17:33:53 +0100 | [diff] [blame] | 890 | static int irq_trigger(int idx) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 891 | { |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 892 | int bus = mp_irqs[idx].srcbus; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 893 | int trigger; |
| 894 | |
| 895 | /* |
| 896 | * Determine IRQ trigger mode (edge or level sensitive): |
| 897 | */ |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 898 | switch ((mp_irqs[idx].irqflag>>2) & 3) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 899 | { |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 900 | case 0: /* conforms, ie. bus-type dependent */ |
| 901 | if (test_bit(bus, mp_bus_not_pci)) |
| 902 | trigger = default_ISA_trigger(idx); |
| 903 | else |
| 904 | trigger = default_PCI_trigger(idx); |
Paul Gortmaker | bb8187d | 2012-05-17 19:06:13 -0400 | [diff] [blame] | 905 | #ifdef CONFIG_EISA |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 906 | switch (mp_bus_id_to_type[bus]) { |
| 907 | case MP_BUS_ISA: /* ISA pin */ |
| 908 | { |
| 909 | /* set before the switch */ |
| 910 | break; |
| 911 | } |
| 912 | case MP_BUS_EISA: /* EISA pin */ |
| 913 | { |
| 914 | trigger = default_EISA_trigger(idx); |
| 915 | break; |
| 916 | } |
| 917 | case MP_BUS_PCI: /* PCI pin */ |
| 918 | { |
| 919 | /* set before the switch */ |
| 920 | break; |
| 921 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 922 | default: |
| 923 | { |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 924 | pr_warn("broken BIOS!!\n"); |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 925 | trigger = 1; |
| 926 | break; |
| 927 | } |
| 928 | } |
| 929 | #endif |
| 930 | break; |
| 931 | case 1: /* edge */ |
Paolo Ciarrocchi | 3606244 | 2008-06-08 13:07:18 +0200 | [diff] [blame] | 932 | { |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 933 | trigger = 0; |
Paolo Ciarrocchi | 3606244 | 2008-06-08 13:07:18 +0200 | [diff] [blame] | 934 | break; |
| 935 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 936 | case 2: /* reserved */ |
Paolo Ciarrocchi | 3606244 | 2008-06-08 13:07:18 +0200 | [diff] [blame] | 937 | { |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 938 | pr_warn("broken BIOS!!\n"); |
Paolo Ciarrocchi | 3606244 | 2008-06-08 13:07:18 +0200 | [diff] [blame] | 939 | trigger = 1; |
| 940 | break; |
| 941 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 942 | case 3: /* level */ |
| 943 | { |
| 944 | trigger = 1; |
| 945 | break; |
| 946 | } |
| 947 | default: /* invalid */ |
| 948 | { |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 949 | pr_warn("broken BIOS!!\n"); |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 950 | trigger = 0; |
| 951 | break; |
| 952 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 953 | } |
| 954 | return trigger; |
| 955 | } |
| 956 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 957 | static int pin_2_irq(int idx, int apic, int pin) |
| 958 | { |
Eric W. Biederman | d464207 | 2010-03-30 01:07:13 -0700 | [diff] [blame] | 959 | int irq; |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 960 | int bus = mp_irqs[idx].srcbus; |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 961 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 962 | |
| 963 | /* |
| 964 | * Debugging check, we are in big trouble if this message pops up! |
| 965 | */ |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 966 | if (mp_irqs[idx].dstirq != pin) |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 967 | pr_err("broken BIOS or MPTABLE parser, ayiee!!\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 968 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 969 | if (test_bit(bus, mp_bus_not_pci)) { |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 970 | irq = mp_irqs[idx].srcbusirq; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 971 | } else { |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 972 | u32 gsi = gsi_cfg->gsi_base + pin; |
Eric W. Biederman | 988856e | 2010-03-30 01:07:15 -0700 | [diff] [blame] | 973 | |
| 974 | if (gsi >= NR_IRQS_LEGACY) |
| 975 | irq = gsi; |
| 976 | else |
Eric W. Biederman | a4384df | 2010-06-08 11:44:32 -0700 | [diff] [blame] | 977 | irq = gsi_top + gsi; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 978 | } |
| 979 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 980 | #ifdef CONFIG_X86_32 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 981 | /* |
| 982 | * PCI IRQ command line redirection. Yes, limits are hardcoded. |
| 983 | */ |
| 984 | if ((pin >= 16) && (pin <= 23)) { |
| 985 | if (pirq_entries[pin-16] != -1) { |
| 986 | if (!pirq_entries[pin-16]) { |
| 987 | apic_printk(APIC_VERBOSE, KERN_DEBUG |
| 988 | "disabling PIRQ%d\n", pin-16); |
| 989 | } else { |
| 990 | irq = pirq_entries[pin-16]; |
| 991 | apic_printk(APIC_VERBOSE, KERN_DEBUG |
| 992 | "using PIRQ%d -> IRQ %d\n", |
| 993 | pin-16, irq); |
| 994 | } |
| 995 | } |
| 996 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 997 | #endif |
| 998 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 999 | return irq; |
| 1000 | } |
| 1001 | |
Yinghai Lu | e20c06f | 2009-05-06 10:08:22 -0700 | [diff] [blame] | 1002 | /* |
| 1003 | * Find a specific PCI IRQ entry. |
| 1004 | * Not an __init, possibly needed by modules |
| 1005 | */ |
| 1006 | int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, |
Yinghai Lu | e519807 | 2009-05-15 13:05:16 -0700 | [diff] [blame] | 1007 | struct io_apic_irq_attr *irq_attr) |
Yinghai Lu | e20c06f | 2009-05-06 10:08:22 -0700 | [diff] [blame] | 1008 | { |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1009 | int ioapic_idx, i, best_guess = -1; |
Yinghai Lu | e20c06f | 2009-05-06 10:08:22 -0700 | [diff] [blame] | 1010 | |
| 1011 | apic_printk(APIC_DEBUG, |
| 1012 | "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", |
| 1013 | bus, slot, pin); |
| 1014 | if (test_bit(bus, mp_bus_not_pci)) { |
| 1015 | apic_printk(APIC_VERBOSE, |
| 1016 | "PCI BIOS passed nonexistent PCI bus %d!\n", bus); |
| 1017 | return -1; |
| 1018 | } |
| 1019 | for (i = 0; i < mp_irq_entries; i++) { |
| 1020 | int lbus = mp_irqs[i].srcbus; |
| 1021 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1022 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) |
| 1023 | if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic || |
Yinghai Lu | e20c06f | 2009-05-06 10:08:22 -0700 | [diff] [blame] | 1024 | mp_irqs[i].dstapic == MP_APIC_ALL) |
| 1025 | break; |
| 1026 | |
| 1027 | if (!test_bit(lbus, mp_bus_not_pci) && |
| 1028 | !mp_irqs[i].irqtype && |
| 1029 | (bus == lbus) && |
| 1030 | (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1031 | int irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq); |
Yinghai Lu | e20c06f | 2009-05-06 10:08:22 -0700 | [diff] [blame] | 1032 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1033 | if (!(ioapic_idx || IO_APIC_IRQ(irq))) |
Yinghai Lu | e20c06f | 2009-05-06 10:08:22 -0700 | [diff] [blame] | 1034 | continue; |
| 1035 | |
| 1036 | if (pin == (mp_irqs[i].srcbusirq & 3)) { |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1037 | set_io_apic_irq_attr(irq_attr, ioapic_idx, |
Yinghai Lu | e519807 | 2009-05-15 13:05:16 -0700 | [diff] [blame] | 1038 | mp_irqs[i].dstirq, |
| 1039 | irq_trigger(i), |
| 1040 | irq_polarity(i)); |
Yinghai Lu | e20c06f | 2009-05-06 10:08:22 -0700 | [diff] [blame] | 1041 | return irq; |
| 1042 | } |
| 1043 | /* |
| 1044 | * Use the first all-but-pin matching entry as a |
| 1045 | * best-guess fuzzy result for broken mptables. |
| 1046 | */ |
| 1047 | if (best_guess < 0) { |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1048 | set_io_apic_irq_attr(irq_attr, ioapic_idx, |
Yinghai Lu | e519807 | 2009-05-15 13:05:16 -0700 | [diff] [blame] | 1049 | mp_irqs[i].dstirq, |
| 1050 | irq_trigger(i), |
| 1051 | irq_polarity(i)); |
Yinghai Lu | e20c06f | 2009-05-06 10:08:22 -0700 | [diff] [blame] | 1052 | best_guess = irq; |
| 1053 | } |
| 1054 | } |
| 1055 | } |
| 1056 | return best_guess; |
| 1057 | } |
| 1058 | EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); |
| 1059 | |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1060 | void lock_vector_lock(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1061 | { |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1062 | /* Used to the online set of cpus does not change |
| 1063 | * during assign_irq_vector. |
| 1064 | */ |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 1065 | raw_spin_lock(&vector_lock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1066 | } |
| 1067 | |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1068 | void unlock_vector_lock(void) |
Eric W. Biederman | ace80ab | 2006-10-04 02:16:47 -0700 | [diff] [blame] | 1069 | { |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 1070 | raw_spin_unlock(&vector_lock); |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1071 | } |
| 1072 | |
Mike Travis | e798673 | 2008-12-16 17:33:52 -0800 | [diff] [blame] | 1073 | static int |
| 1074 | __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1075 | { |
Yinghai Lu | 047c8fd | 2008-08-19 20:50:41 -0700 | [diff] [blame] | 1076 | /* |
| 1077 | * NOTE! The local APIC isn't very good at handling |
| 1078 | * multiple interrupts at the same interrupt level. |
| 1079 | * As the interrupt level is determined by taking the |
| 1080 | * vector number and shifting that right by 4, we |
| 1081 | * want to spread these out a bit so that they don't |
| 1082 | * all fall in the same interrupt level. |
| 1083 | * |
| 1084 | * Also, we've got to be careful not to trash gate |
| 1085 | * 0x80, because int 0x80 is hm, kind of importantish. ;) |
| 1086 | */ |
Suresh Siddha | 6579b47 | 2010-01-13 16:19:11 -0800 | [diff] [blame] | 1087 | static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; |
Alexander Gordeev | 1bccd58 | 2012-06-07 15:15:15 +0200 | [diff] [blame] | 1088 | static int current_offset = VECTOR_OFFSET_START % 16; |
Mike Travis | 22f65d3 | 2008-12-16 17:33:56 -0800 | [diff] [blame] | 1089 | int cpu, err; |
| 1090 | cpumask_var_t tmp_mask; |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1091 | |
Suresh Siddha | 23359a8 | 2009-10-26 14:24:33 -0800 | [diff] [blame] | 1092 | if (cfg->move_in_progress) |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1093 | return -EBUSY; |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1094 | |
Mike Travis | 22f65d3 | 2008-12-16 17:33:56 -0800 | [diff] [blame] | 1095 | if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) |
| 1096 | return -ENOMEM; |
Yinghai Lu | 3145e94 | 2008-12-05 18:58:34 -0800 | [diff] [blame] | 1097 | |
Mike Travis | e798673 | 2008-12-16 17:33:52 -0800 | [diff] [blame] | 1098 | /* Only try and allocate irqs on cpus that are present */ |
Mike Travis | 22f65d3 | 2008-12-16 17:33:56 -0800 | [diff] [blame] | 1099 | err = -ENOSPC; |
Suresh Siddha | b39f25a | 2012-06-25 13:38:27 -0700 | [diff] [blame] | 1100 | cpumask_clear(cfg->old_domain); |
| 1101 | cpu = cpumask_first_and(mask, cpu_online_mask); |
| 1102 | while (cpu < nr_cpu_ids) { |
Suresh Siddha | 1ac322d | 2012-06-25 13:38:28 -0700 | [diff] [blame] | 1103 | int new_cpu, vector, offset; |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1104 | |
Suresh Siddha | 1ac322d | 2012-06-25 13:38:28 -0700 | [diff] [blame] | 1105 | apic->vector_allocation_domain(cpu, tmp_mask, mask); |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1106 | |
Suresh Siddha | 332afa6 | 2012-05-21 16:58:01 -0700 | [diff] [blame] | 1107 | if (cpumask_subset(tmp_mask, cfg->domain)) { |
Suresh Siddha | 1ac322d | 2012-06-25 13:38:28 -0700 | [diff] [blame] | 1108 | err = 0; |
| 1109 | if (cpumask_equal(tmp_mask, cfg->domain)) |
| 1110 | break; |
| 1111 | /* |
| 1112 | * New cpumask using the vector is a proper subset of |
| 1113 | * the current in use mask. So cleanup the vector |
| 1114 | * allocation for the members that are not used anymore. |
| 1115 | */ |
| 1116 | cpumask_andnot(cfg->old_domain, cfg->domain, tmp_mask); |
Suresh Siddha | 29c574c | 2012-11-26 14:49:36 -0800 | [diff] [blame] | 1117 | cfg->move_in_progress = |
| 1118 | cpumask_intersects(cfg->old_domain, cpu_online_mask); |
Suresh Siddha | 1ac322d | 2012-06-25 13:38:28 -0700 | [diff] [blame] | 1119 | cpumask_and(cfg->domain, cfg->domain, tmp_mask); |
| 1120 | break; |
Suresh Siddha | 332afa6 | 2012-05-21 16:58:01 -0700 | [diff] [blame] | 1121 | } |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1122 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1123 | vector = current_vector; |
| 1124 | offset = current_offset; |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1125 | next: |
Alexander Gordeev | 1bccd58 | 2012-06-07 15:15:15 +0200 | [diff] [blame] | 1126 | vector += 16; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1127 | if (vector >= first_system_vector) { |
Alexander Gordeev | 1bccd58 | 2012-06-07 15:15:15 +0200 | [diff] [blame] | 1128 | offset = (offset + 1) % 16; |
Suresh Siddha | 6579b47 | 2010-01-13 16:19:11 -0800 | [diff] [blame] | 1129 | vector = FIRST_EXTERNAL_VECTOR + offset; |
Yinghai Lu | 7a959cf | 2008-08-19 20:50:32 -0700 | [diff] [blame] | 1130 | } |
Alexander Gordeev | 8637e38 | 2012-06-07 15:15:44 +0200 | [diff] [blame] | 1131 | |
| 1132 | if (unlikely(current_vector == vector)) { |
Suresh Siddha | b39f25a | 2012-06-25 13:38:27 -0700 | [diff] [blame] | 1133 | cpumask_or(cfg->old_domain, cfg->old_domain, tmp_mask); |
| 1134 | cpumask_andnot(tmp_mask, mask, cfg->old_domain); |
| 1135 | cpu = cpumask_first_and(tmp_mask, cpu_online_mask); |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1136 | continue; |
Alexander Gordeev | 8637e38 | 2012-06-07 15:15:44 +0200 | [diff] [blame] | 1137 | } |
Yinghai Lu | b77b881 | 2008-12-19 15:23:44 -0800 | [diff] [blame] | 1138 | |
| 1139 | if (test_bit(vector, used_vectors)) |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1140 | goto next; |
Yinghai Lu | b77b881 | 2008-12-19 15:23:44 -0800 | [diff] [blame] | 1141 | |
Prarit Bhargava | 9345005 | 2014-01-05 11:10:52 -0500 | [diff] [blame] | 1142 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) { |
| 1143 | if (per_cpu(vector_irq, new_cpu)[vector] > VECTOR_UNDEFINED) |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1144 | goto next; |
Prarit Bhargava | 9345005 | 2014-01-05 11:10:52 -0500 | [diff] [blame] | 1145 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1146 | /* Found one! */ |
| 1147 | current_vector = vector; |
| 1148 | current_offset = offset; |
Suresh Siddha | 1ac322d | 2012-06-25 13:38:28 -0700 | [diff] [blame] | 1149 | if (cfg->vector) { |
Mike Travis | 22f65d3 | 2008-12-16 17:33:56 -0800 | [diff] [blame] | 1150 | cpumask_copy(cfg->old_domain, cfg->domain); |
Suresh Siddha | 29c574c | 2012-11-26 14:49:36 -0800 | [diff] [blame] | 1151 | cfg->move_in_progress = |
| 1152 | cpumask_intersects(cfg->old_domain, cpu_online_mask); |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1153 | } |
Mike Travis | 22f65d3 | 2008-12-16 17:33:56 -0800 | [diff] [blame] | 1154 | for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1155 | per_cpu(vector_irq, new_cpu)[vector] = irq; |
| 1156 | cfg->vector = vector; |
Mike Travis | 22f65d3 | 2008-12-16 17:33:56 -0800 | [diff] [blame] | 1157 | cpumask_copy(cfg->domain, tmp_mask); |
| 1158 | err = 0; |
| 1159 | break; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1160 | } |
Mike Travis | 22f65d3 | 2008-12-16 17:33:56 -0800 | [diff] [blame] | 1161 | free_cpumask_var(tmp_mask); |
| 1162 | return err; |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1163 | } |
| 1164 | |
Dimitri Sivanich | 9338ad6 | 2009-10-13 15:32:36 -0500 | [diff] [blame] | 1165 | int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1166 | { |
| 1167 | int err; |
Eric W. Biederman | ace80ab | 2006-10-04 02:16:47 -0700 | [diff] [blame] | 1168 | unsigned long flags; |
Eric W. Biederman | ace80ab | 2006-10-04 02:16:47 -0700 | [diff] [blame] | 1169 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 1170 | raw_spin_lock_irqsave(&vector_lock, flags); |
Yinghai Lu | 3145e94 | 2008-12-05 18:58:34 -0800 | [diff] [blame] | 1171 | err = __assign_irq_vector(irq, cfg, mask); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 1172 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1173 | return err; |
| 1174 | } |
| 1175 | |
Yinghai Lu | 3145e94 | 2008-12-05 18:58:34 -0800 | [diff] [blame] | 1176 | static void __clear_irq_vector(int irq, struct irq_cfg *cfg) |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1177 | { |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1178 | int cpu, vector; |
| 1179 | |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1180 | BUG_ON(!cfg->vector); |
| 1181 | |
| 1182 | vector = cfg->vector; |
Tomoki Sekiyama | 1d44b30 | 2012-07-26 19:47:32 +0900 | [diff] [blame] | 1183 | for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) |
Prarit Bhargava | 9345005 | 2014-01-05 11:10:52 -0500 | [diff] [blame] | 1184 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1185 | |
| 1186 | cfg->vector = 0; |
Mike Travis | 22f65d3 | 2008-12-16 17:33:56 -0800 | [diff] [blame] | 1187 | cpumask_clear(cfg->domain); |
Matthew Wilcox | 0ca4b6b | 2008-11-20 14:09:33 -0700 | [diff] [blame] | 1188 | |
| 1189 | if (likely(!cfg->move_in_progress)) |
| 1190 | return; |
Tomoki Sekiyama | 1d44b30 | 2012-07-26 19:47:32 +0900 | [diff] [blame] | 1191 | for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { |
Prarit Bhargava | 9345005 | 2014-01-05 11:10:52 -0500 | [diff] [blame] | 1192 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { |
Matthew Wilcox | 0ca4b6b | 2008-11-20 14:09:33 -0700 | [diff] [blame] | 1193 | if (per_cpu(vector_irq, cpu)[vector] != irq) |
| 1194 | continue; |
Prarit Bhargava | 9345005 | 2014-01-05 11:10:52 -0500 | [diff] [blame] | 1195 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; |
Matthew Wilcox | 0ca4b6b | 2008-11-20 14:09:33 -0700 | [diff] [blame] | 1196 | break; |
| 1197 | } |
| 1198 | } |
| 1199 | cfg->move_in_progress = 0; |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1200 | } |
| 1201 | |
| 1202 | void __setup_vector_irq(int cpu) |
| 1203 | { |
| 1204 | /* Initialize vector_irq on a new cpu */ |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1205 | int irq, vector; |
| 1206 | struct irq_cfg *cfg; |
| 1207 | |
Suresh Siddha | 9d133e5 | 2010-01-29 11:42:21 -0800 | [diff] [blame] | 1208 | /* |
| 1209 | * vector_lock will make sure that we don't run into irq vector |
| 1210 | * assignments that might be happening on another cpu in parallel, |
| 1211 | * while we setup our initial vector to irq mappings. |
| 1212 | */ |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 1213 | raw_spin_lock(&vector_lock); |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1214 | /* Mark the inuse vectors */ |
Thomas Gleixner | ad9f433 | 2010-09-30 11:26:43 +0200 | [diff] [blame] | 1215 | for_each_active_irq(irq) { |
Thomas Gleixner | 2c77865 | 2011-03-12 12:20:43 +0100 | [diff] [blame] | 1216 | cfg = irq_get_chip_data(irq); |
Thomas Gleixner | ad9f433 | 2010-09-30 11:26:43 +0200 | [diff] [blame] | 1217 | if (!cfg) |
| 1218 | continue; |
Suresh Siddha | 36e9e1e | 2010-03-15 14:33:06 -0800 | [diff] [blame] | 1219 | |
Mike Travis | 22f65d3 | 2008-12-16 17:33:56 -0800 | [diff] [blame] | 1220 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1221 | continue; |
| 1222 | vector = cfg->vector; |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1223 | per_cpu(vector_irq, cpu)[vector] = irq; |
| 1224 | } |
| 1225 | /* Mark the free vectors */ |
| 1226 | for (vector = 0; vector < NR_VECTORS; ++vector) { |
| 1227 | irq = per_cpu(vector_irq, cpu)[vector]; |
Prarit Bhargava | 9345005 | 2014-01-05 11:10:52 -0500 | [diff] [blame] | 1228 | if (irq <= VECTOR_UNDEFINED) |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1229 | continue; |
| 1230 | |
| 1231 | cfg = irq_cfg(irq); |
Mike Travis | 22f65d3 | 2008-12-16 17:33:56 -0800 | [diff] [blame] | 1232 | if (!cpumask_test_cpu(cpu, cfg->domain)) |
Prarit Bhargava | 9345005 | 2014-01-05 11:10:52 -0500 | [diff] [blame] | 1233 | per_cpu(vector_irq, cpu)[vector] = VECTOR_UNDEFINED; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1234 | } |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 1235 | raw_spin_unlock(&vector_lock); |
Eric W. Biederman | ace80ab | 2006-10-04 02:16:47 -0700 | [diff] [blame] | 1236 | } |
Glauber Costa | 3fde690 | 2008-05-28 20:34:19 -0700 | [diff] [blame] | 1237 | |
Ingo Molnar | f5b9ed7 | 2006-10-04 02:16:26 -0700 | [diff] [blame] | 1238 | static struct irq_chip ioapic_chip; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1239 | |
Yinghai Lu | 047c8fd | 2008-08-19 20:50:41 -0700 | [diff] [blame] | 1240 | #ifdef CONFIG_X86_32 |
Yinghai Lu | 1d02519 | 2008-08-19 20:50:34 -0700 | [diff] [blame] | 1241 | static inline int IO_APIC_irq_trigger(int irq) |
| 1242 | { |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 1243 | int apic, idx, pin; |
Yinghai Lu | 1d02519 | 2008-08-19 20:50:34 -0700 | [diff] [blame] | 1244 | |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 1245 | for (apic = 0; apic < nr_ioapics; apic++) { |
Suresh Siddha | b69c6c3 | 2011-05-18 16:31:35 -0700 | [diff] [blame] | 1246 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 1247 | idx = find_irq_entry(apic, pin, mp_INT); |
| 1248 | if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) |
| 1249 | return irq_trigger(idx); |
| 1250 | } |
| 1251 | } |
| 1252 | /* |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1253 | * nonexistent IRQs are edge default |
| 1254 | */ |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 1255 | return 0; |
Yinghai Lu | 1d02519 | 2008-08-19 20:50:34 -0700 | [diff] [blame] | 1256 | } |
Yinghai Lu | 047c8fd | 2008-08-19 20:50:41 -0700 | [diff] [blame] | 1257 | #else |
| 1258 | static inline int IO_APIC_irq_trigger(int irq) |
| 1259 | { |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1260 | return 1; |
Yinghai Lu | 047c8fd | 2008-08-19 20:50:41 -0700 | [diff] [blame] | 1261 | } |
| 1262 | #endif |
Yinghai Lu | 1d02519 | 2008-08-19 20:50:34 -0700 | [diff] [blame] | 1263 | |
Thomas Gleixner | 1a0e62a | 2011-03-12 13:47:18 +0100 | [diff] [blame] | 1264 | static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg, |
| 1265 | unsigned long trigger) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1266 | { |
Thomas Gleixner | c60eaf2 | 2011-03-11 13:17:16 +0100 | [diff] [blame] | 1267 | struct irq_chip *chip = &ioapic_chip; |
| 1268 | irq_flow_handler_t hdl; |
| 1269 | bool fasteoi; |
Yinghai Lu | 199751d | 2008-08-19 20:50:27 -0700 | [diff] [blame] | 1270 | |
Jan Beulich | 6ebcc00 | 2006-06-26 13:56:46 +0200 | [diff] [blame] | 1271 | if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || |
Thomas Gleixner | c60eaf2 | 2011-03-11 13:17:16 +0100 | [diff] [blame] | 1272 | trigger == IOAPIC_LEVEL) { |
Thomas Gleixner | 60c6994 | 2010-09-28 17:28:38 +0200 | [diff] [blame] | 1273 | irq_set_status_flags(irq, IRQ_LEVEL); |
Thomas Gleixner | c60eaf2 | 2011-03-11 13:17:16 +0100 | [diff] [blame] | 1274 | fasteoi = true; |
| 1275 | } else { |
Thomas Gleixner | 60c6994 | 2010-09-28 17:28:38 +0200 | [diff] [blame] | 1276 | irq_clear_status_flags(irq, IRQ_LEVEL); |
Thomas Gleixner | c60eaf2 | 2011-03-11 13:17:16 +0100 | [diff] [blame] | 1277 | fasteoi = false; |
| 1278 | } |
Yinghai Lu | 047c8fd | 2008-08-19 20:50:41 -0700 | [diff] [blame] | 1279 | |
Joerg Roedel | 2976fd8 | 2012-09-26 12:44:48 +0200 | [diff] [blame] | 1280 | if (setup_remapped_irq(irq, cfg, chip)) |
Thomas Gleixner | c60eaf2 | 2011-03-11 13:17:16 +0100 | [diff] [blame] | 1281 | fasteoi = trigger != 0; |
Suresh Siddha | 29b61be | 2009-03-16 17:05:02 -0700 | [diff] [blame] | 1282 | |
Thomas Gleixner | c60eaf2 | 2011-03-11 13:17:16 +0100 | [diff] [blame] | 1283 | hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq; |
| 1284 | irq_set_chip_and_handler_name(irq, chip, hdl, |
| 1285 | fasteoi ? "fasteoi" : "edge"); |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1286 | } |
| 1287 | |
Joerg Roedel | a6a25dd | 2012-09-26 12:44:40 +0200 | [diff] [blame] | 1288 | int native_setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry, |
| 1289 | unsigned int destination, int vector, |
| 1290 | struct io_apic_irq_attr *attr) |
Yinghai Lu | c5b4712 | 2011-10-12 00:33:15 -0700 | [diff] [blame] | 1291 | { |
Yinghai Lu | c5b4712 | 2011-10-12 00:33:15 -0700 | [diff] [blame] | 1292 | memset(entry, 0, sizeof(*entry)); |
| 1293 | |
| 1294 | entry->delivery_mode = apic->irq_delivery_mode; |
| 1295 | entry->dest_mode = apic->irq_dest_mode; |
| 1296 | entry->dest = destination; |
| 1297 | entry->vector = vector; |
| 1298 | entry->mask = 0; /* enable IRQ */ |
| 1299 | entry->trigger = attr->trigger; |
| 1300 | entry->polarity = attr->polarity; |
| 1301 | |
| 1302 | /* |
| 1303 | * Mask level triggered irqs. |
| 1304 | * Use IRQ_DELAYED_DISABLE for edge triggered irqs. |
| 1305 | */ |
| 1306 | if (attr->trigger) |
| 1307 | entry->mask = 1; |
| 1308 | |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1309 | return 0; |
| 1310 | } |
| 1311 | |
Yinghai Lu | e4aff81 | 2011-10-12 00:33:05 -0700 | [diff] [blame] | 1312 | static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg, |
| 1313 | struct io_apic_irq_attr *attr) |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1314 | { |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1315 | struct IO_APIC_route_entry entry; |
Mike Travis | 22f65d3 | 2008-12-16 17:33:56 -0800 | [diff] [blame] | 1316 | unsigned int dest; |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1317 | |
| 1318 | if (!IO_APIC_IRQ(irq)) |
| 1319 | return; |
Suresh Siddha | 69c89ef | 2010-01-29 11:42:20 -0800 | [diff] [blame] | 1320 | |
Ingo Molnar | fe402e1 | 2009-01-28 04:32:51 +0100 | [diff] [blame] | 1321 | if (assign_irq_vector(irq, cfg, apic->target_cpus())) |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1322 | return; |
| 1323 | |
Alexander Gordeev | ff16432 | 2012-06-07 15:15:59 +0200 | [diff] [blame] | 1324 | if (apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus(), |
| 1325 | &dest)) { |
| 1326 | pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n", |
| 1327 | mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); |
| 1328 | __clear_irq_vector(irq, cfg); |
| 1329 | |
| 1330 | return; |
| 1331 | } |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1332 | |
| 1333 | apic_printk(APIC_VERBOSE,KERN_DEBUG |
| 1334 | "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " |
Naga Chumbalkar | 7fece83 | 2011-07-08 18:46:42 +0000 | [diff] [blame] | 1335 | "IRQ %d Mode:%i Active:%i Dest:%d)\n", |
Yinghai Lu | e4aff81 | 2011-10-12 00:33:05 -0700 | [diff] [blame] | 1336 | attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin, |
| 1337 | cfg->vector, irq, attr->trigger, attr->polarity, dest); |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1338 | |
Joerg Roedel | a6a25dd | 2012-09-26 12:44:40 +0200 | [diff] [blame] | 1339 | if (x86_io_apic_ops.setup_entry(irq, &entry, dest, cfg->vector, attr)) { |
| 1340 | pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n", |
Yinghai Lu | c5b4712 | 2011-10-12 00:33:15 -0700 | [diff] [blame] | 1341 | mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); |
Yinghai Lu | 3145e94 | 2008-12-05 18:58:34 -0800 | [diff] [blame] | 1342 | __clear_irq_vector(irq, cfg); |
Yinghai Lu | c5b4712 | 2011-10-12 00:33:15 -0700 | [diff] [blame] | 1343 | |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1344 | return; |
| 1345 | } |
| 1346 | |
Yinghai Lu | e4aff81 | 2011-10-12 00:33:05 -0700 | [diff] [blame] | 1347 | ioapic_register_intr(irq, cfg, attr->trigger); |
Jacob Pan | b81bb37 | 2009-11-09 11:27:04 -0800 | [diff] [blame] | 1348 | if (irq < legacy_pic->nr_legacy_irqs) |
Thomas Gleixner | 4305df9 | 2010-09-28 15:01:33 +0200 | [diff] [blame] | 1349 | legacy_pic->mask(irq); |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 1350 | |
Yinghai Lu | e4aff81 | 2011-10-12 00:33:05 -0700 | [diff] [blame] | 1351 | ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1352 | } |
| 1353 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1354 | static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin) |
Thomas Gleixner | c8d6b8f | 2011-02-23 14:29:34 +0100 | [diff] [blame] | 1355 | { |
| 1356 | if (idx != -1) |
| 1357 | return false; |
| 1358 | |
| 1359 | apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n", |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1360 | mpc_ioapic_id(ioapic_idx), pin); |
Thomas Gleixner | c8d6b8f | 2011-02-23 14:29:34 +0100 | [diff] [blame] | 1361 | return true; |
| 1362 | } |
| 1363 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1364 | static void __init __io_apic_setup_irqs(unsigned int ioapic_idx) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1365 | { |
Thomas Gleixner | ed972cc | 2011-02-23 14:31:36 +0100 | [diff] [blame] | 1366 | int idx, node = cpu_to_node(0); |
Thomas Gleixner | 2d57e37 | 2011-02-23 14:40:35 +0100 | [diff] [blame] | 1367 | struct io_apic_irq_attr attr; |
Thomas Gleixner | ed972cc | 2011-02-23 14:31:36 +0100 | [diff] [blame] | 1368 | unsigned int pin, irq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1369 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1370 | for (pin = 0; pin < ioapics[ioapic_idx].nr_registers; pin++) { |
| 1371 | idx = find_irq_entry(ioapic_idx, pin, mp_INT); |
| 1372 | if (io_apic_pin_not_connected(idx, ioapic_idx, pin)) |
Yinghai Lu | b9c61b70 | 2009-05-06 10:10:06 -0700 | [diff] [blame] | 1373 | continue; |
Yinghai Lu | b9c61b70 | 2009-05-06 10:10:06 -0700 | [diff] [blame] | 1374 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1375 | irq = pin_2_irq(idx, ioapic_idx, pin); |
Yinghai Lu | b9c61b70 | 2009-05-06 10:10:06 -0700 | [diff] [blame] | 1376 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1377 | if ((ioapic_idx > 0) && (irq > 16)) |
Eric W. Biederman | fad5399 | 2010-02-28 01:06:34 -0800 | [diff] [blame] | 1378 | continue; |
| 1379 | |
Yinghai Lu | b9c61b70 | 2009-05-06 10:10:06 -0700 | [diff] [blame] | 1380 | /* |
| 1381 | * Skip the timer IRQ if there's a quirk handler |
| 1382 | * installed and if it returns 1: |
| 1383 | */ |
| 1384 | if (apic->multi_timer_check && |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1385 | apic->multi_timer_check(ioapic_idx, irq)) |
Yinghai Lu | b9c61b70 | 2009-05-06 10:10:06 -0700 | [diff] [blame] | 1386 | continue; |
| 1387 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1388 | set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx), |
Thomas Gleixner | 2d57e37 | 2011-02-23 14:40:35 +0100 | [diff] [blame] | 1389 | irq_polarity(idx)); |
Thomas Gleixner | fbc6bff | 2010-09-28 20:34:53 +0200 | [diff] [blame] | 1390 | |
Thomas Gleixner | 2d57e37 | 2011-02-23 14:40:35 +0100 | [diff] [blame] | 1391 | io_apic_setup_irq_pin(irq, node, &attr); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1392 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1393 | } |
| 1394 | |
Thomas Gleixner | ed972cc | 2011-02-23 14:31:36 +0100 | [diff] [blame] | 1395 | static void __init setup_IO_APIC_irqs(void) |
| 1396 | { |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1397 | unsigned int ioapic_idx; |
Thomas Gleixner | ed972cc | 2011-02-23 14:31:36 +0100 | [diff] [blame] | 1398 | |
| 1399 | apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); |
| 1400 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1401 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) |
| 1402 | __io_apic_setup_irqs(ioapic_idx); |
Thomas Gleixner | ed972cc | 2011-02-23 14:31:36 +0100 | [diff] [blame] | 1403 | } |
| 1404 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1405 | /* |
Yinghai Lu | 18dce6b | 2010-02-10 01:20:05 -0800 | [diff] [blame] | 1406 | * for the gsit that is not in first ioapic |
| 1407 | * but could not use acpi_register_gsi() |
| 1408 | * like some special sci in IBM x3330 |
| 1409 | */ |
| 1410 | void setup_IO_APIC_irq_extra(u32 gsi) |
| 1411 | { |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1412 | int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0); |
Thomas Gleixner | da1ad9d | 2011-02-23 14:52:16 +0100 | [diff] [blame] | 1413 | struct io_apic_irq_attr attr; |
Yinghai Lu | 18dce6b | 2010-02-10 01:20:05 -0800 | [diff] [blame] | 1414 | |
| 1415 | /* |
| 1416 | * Convert 'gsi' to 'ioapic.pin'. |
| 1417 | */ |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1418 | ioapic_idx = mp_find_ioapic(gsi); |
| 1419 | if (ioapic_idx < 0) |
Yinghai Lu | 18dce6b | 2010-02-10 01:20:05 -0800 | [diff] [blame] | 1420 | return; |
| 1421 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1422 | pin = mp_find_ioapic_pin(ioapic_idx, gsi); |
| 1423 | idx = find_irq_entry(ioapic_idx, pin, mp_INT); |
Yinghai Lu | 18dce6b | 2010-02-10 01:20:05 -0800 | [diff] [blame] | 1424 | if (idx == -1) |
| 1425 | return; |
| 1426 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1427 | irq = pin_2_irq(idx, ioapic_idx, pin); |
Yinghai Lu | fe6dab4 | 2010-10-08 22:44:02 -0700 | [diff] [blame] | 1428 | |
| 1429 | /* Only handle the non legacy irqs on secondary ioapics */ |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1430 | if (ioapic_idx == 0 || irq < NR_IRQS_LEGACY) |
Yinghai Lu | 18dce6b | 2010-02-10 01:20:05 -0800 | [diff] [blame] | 1431 | return; |
Yinghai Lu | fe6dab4 | 2010-10-08 22:44:02 -0700 | [diff] [blame] | 1432 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1433 | set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx), |
Thomas Gleixner | da1ad9d | 2011-02-23 14:52:16 +0100 | [diff] [blame] | 1434 | irq_polarity(idx)); |
| 1435 | |
Thomas Gleixner | 710dcda | 2011-02-23 17:47:41 +0100 | [diff] [blame] | 1436 | io_apic_setup_irq_pin_once(irq, node, &attr); |
Yinghai Lu | 18dce6b | 2010-02-10 01:20:05 -0800 | [diff] [blame] | 1437 | } |
| 1438 | |
| 1439 | /* |
Maciej W. Rozycki | f7633ce | 2008-05-27 21:19:34 +0100 | [diff] [blame] | 1440 | * Set up the timer pin, possibly with the 8259A-master behind. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1441 | */ |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1442 | static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx, |
Alexander Gordeev | 49d0c7a | 2012-06-05 13:23:15 +0200 | [diff] [blame] | 1443 | unsigned int pin, int vector) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1444 | { |
| 1445 | struct IO_APIC_route_entry entry; |
Alexander Gordeev | ff16432 | 2012-06-07 15:15:59 +0200 | [diff] [blame] | 1446 | unsigned int dest; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1447 | |
Paolo Ciarrocchi | 3606244 | 2008-06-08 13:07:18 +0200 | [diff] [blame] | 1448 | memset(&entry, 0, sizeof(entry)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1449 | |
| 1450 | /* |
| 1451 | * We use logical delivery to get the timer IRQ |
| 1452 | * to the first CPU. |
| 1453 | */ |
Alexander Gordeev | a5a3915 | 2012-06-14 09:49:35 +0200 | [diff] [blame] | 1454 | if (unlikely(apic->cpu_mask_to_apicid_and(apic->target_cpus(), |
| 1455 | apic->target_cpus(), &dest))) |
Alexander Gordeev | ff16432 | 2012-06-07 15:15:59 +0200 | [diff] [blame] | 1456 | dest = BAD_APICID; |
| 1457 | |
Ingo Molnar | 9b5bc8d | 2009-01-28 04:09:58 +0100 | [diff] [blame] | 1458 | entry.dest_mode = apic->irq_dest_mode; |
Yinghai Lu | f72dcca | 2009-02-08 16:18:03 -0800 | [diff] [blame] | 1459 | entry.mask = 0; /* don't mask IRQ for edge */ |
Alexander Gordeev | ff16432 | 2012-06-07 15:15:59 +0200 | [diff] [blame] | 1460 | entry.dest = dest; |
Ingo Molnar | 9b5bc8d | 2009-01-28 04:09:58 +0100 | [diff] [blame] | 1461 | entry.delivery_mode = apic->irq_delivery_mode; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1462 | entry.polarity = 0; |
| 1463 | entry.trigger = 0; |
| 1464 | entry.vector = vector; |
| 1465 | |
| 1466 | /* |
| 1467 | * The timer IRQ doesn't have to know that behind the |
Maciej W. Rozycki | f7633ce | 2008-05-27 21:19:34 +0100 | [diff] [blame] | 1468 | * scene we may have a 8259A-master in AEOI mode ... |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1469 | */ |
Thomas Gleixner | 2c77865 | 2011-03-12 12:20:43 +0100 | [diff] [blame] | 1470 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
| 1471 | "edge"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1472 | |
| 1473 | /* |
| 1474 | * Add it to the IO-APIC irq-routing table: |
| 1475 | */ |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1476 | ioapic_write_entry(ioapic_idx, pin, entry); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1477 | } |
| 1478 | |
Joerg Roedel | afcc8a4 | 2012-09-26 12:44:36 +0200 | [diff] [blame] | 1479 | void native_io_apic_print_entries(unsigned int apic, unsigned int nr_entries) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1480 | { |
Yinghai Lu | cda417d | 2011-10-12 00:33:39 -0700 | [diff] [blame] | 1481 | int i; |
Joerg Roedel | afcc8a4 | 2012-09-26 12:44:36 +0200 | [diff] [blame] | 1482 | |
| 1483 | pr_debug(" NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:\n"); |
| 1484 | |
| 1485 | for (i = 0; i <= nr_entries; i++) { |
| 1486 | struct IO_APIC_route_entry entry; |
| 1487 | |
| 1488 | entry = ioapic_read_entry(apic, i); |
| 1489 | |
| 1490 | pr_debug(" %02x %02X ", i, entry.dest); |
| 1491 | pr_cont("%1d %1d %1d %1d %1d " |
| 1492 | "%1d %1d %02X\n", |
| 1493 | entry.mask, |
| 1494 | entry.trigger, |
| 1495 | entry.irr, |
| 1496 | entry.polarity, |
| 1497 | entry.delivery_status, |
| 1498 | entry.dest_mode, |
| 1499 | entry.delivery_mode, |
| 1500 | entry.vector); |
| 1501 | } |
| 1502 | } |
| 1503 | |
| 1504 | void intel_ir_io_apic_print_entries(unsigned int apic, |
| 1505 | unsigned int nr_entries) |
| 1506 | { |
| 1507 | int i; |
| 1508 | |
| 1509 | pr_debug(" NR Indx Fmt Mask Trig IRR Pol Stat Indx2 Zero Vect:\n"); |
| 1510 | |
| 1511 | for (i = 0; i <= nr_entries; i++) { |
| 1512 | struct IR_IO_APIC_route_entry *ir_entry; |
| 1513 | struct IO_APIC_route_entry entry; |
| 1514 | |
| 1515 | entry = ioapic_read_entry(apic, i); |
| 1516 | |
| 1517 | ir_entry = (struct IR_IO_APIC_route_entry *)&entry; |
| 1518 | |
| 1519 | pr_debug(" %02x %04X ", i, ir_entry->index); |
| 1520 | pr_cont("%1d %1d %1d %1d %1d " |
| 1521 | "%1d %1d %X %02X\n", |
| 1522 | ir_entry->format, |
| 1523 | ir_entry->mask, |
| 1524 | ir_entry->trigger, |
| 1525 | ir_entry->irr, |
| 1526 | ir_entry->polarity, |
| 1527 | ir_entry->delivery_status, |
| 1528 | ir_entry->index2, |
| 1529 | ir_entry->zero, |
| 1530 | ir_entry->vector); |
| 1531 | } |
| 1532 | } |
| 1533 | |
Yoshihiro YUNOMAE | 1740545 | 2013-08-20 16:01:07 +0900 | [diff] [blame] | 1534 | void ioapic_zap_locks(void) |
| 1535 | { |
| 1536 | raw_spin_lock_init(&ioapic_lock); |
| 1537 | } |
| 1538 | |
Joerg Roedel | afcc8a4 | 2012-09-26 12:44:36 +0200 | [diff] [blame] | 1539 | __apicdebuginit(void) print_IO_APIC(int ioapic_idx) |
| 1540 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1541 | union IO_APIC_reg_00 reg_00; |
| 1542 | union IO_APIC_reg_01 reg_01; |
| 1543 | union IO_APIC_reg_02 reg_02; |
| 1544 | union IO_APIC_reg_03 reg_03; |
| 1545 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1546 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 1547 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1548 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
| 1549 | reg_01.raw = io_apic_read(ioapic_idx, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1550 | if (reg_01.bits.version >= 0x10) |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1551 | reg_02.raw = io_apic_read(ioapic_idx, 2); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 1552 | if (reg_01.bits.version >= 0x20) |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1553 | reg_03.raw = io_apic_read(ioapic_idx, 3); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 1554 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1555 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1556 | printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1557 | printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); |
| 1558 | printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); |
| 1559 | printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); |
| 1560 | printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1561 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1562 | printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); |
Naga Chumbalkar | bd6a46e | 2011-07-08 18:46:36 +0000 | [diff] [blame] | 1563 | printk(KERN_DEBUG "....... : max redirection entries: %02X\n", |
| 1564 | reg_01.bits.entries); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1565 | |
| 1566 | printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); |
Naga Chumbalkar | bd6a46e | 2011-07-08 18:46:36 +0000 | [diff] [blame] | 1567 | printk(KERN_DEBUG "....... : IO APIC version: %02X\n", |
| 1568 | reg_01.bits.version); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1569 | |
| 1570 | /* |
| 1571 | * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, |
| 1572 | * but the value of reg_02 is read as the previous read register |
| 1573 | * value, so ignore it if reg_02 == reg_01. |
| 1574 | */ |
| 1575 | if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { |
| 1576 | printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); |
| 1577 | printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1578 | } |
| 1579 | |
| 1580 | /* |
| 1581 | * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 |
| 1582 | * or reg_03, but the value of reg_0[23] is read as the previous read |
| 1583 | * register value, so ignore it if reg_03 == reg_0[12]. |
| 1584 | */ |
| 1585 | if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && |
| 1586 | reg_03.raw != reg_01.raw) { |
| 1587 | printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); |
| 1588 | printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1589 | } |
| 1590 | |
| 1591 | printk(KERN_DEBUG ".... IRQ redirection table:\n"); |
| 1592 | |
Joerg Roedel | afcc8a4 | 2012-09-26 12:44:36 +0200 | [diff] [blame] | 1593 | x86_io_apic_ops.print_entries(ioapic_idx, reg_01.bits.entries); |
Yinghai Lu | cda417d | 2011-10-12 00:33:39 -0700 | [diff] [blame] | 1594 | } |
| 1595 | |
| 1596 | __apicdebuginit(void) print_IO_APICs(void) |
| 1597 | { |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1598 | int ioapic_idx; |
Yinghai Lu | cda417d | 2011-10-12 00:33:39 -0700 | [diff] [blame] | 1599 | struct irq_cfg *cfg; |
| 1600 | unsigned int irq; |
Mathias Nyman | 6fd36ba | 2011-11-10 13:45:24 +0000 | [diff] [blame] | 1601 | struct irq_chip *chip; |
Yinghai Lu | cda417d | 2011-10-12 00:33:39 -0700 | [diff] [blame] | 1602 | |
| 1603 | printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1604 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) |
Yinghai Lu | cda417d | 2011-10-12 00:33:39 -0700 | [diff] [blame] | 1605 | printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1606 | mpc_ioapic_id(ioapic_idx), |
| 1607 | ioapics[ioapic_idx].nr_registers); |
Yinghai Lu | cda417d | 2011-10-12 00:33:39 -0700 | [diff] [blame] | 1608 | |
| 1609 | /* |
| 1610 | * We are a bit conservative about what we expect. We have to |
| 1611 | * know about every hardware change ASAP. |
| 1612 | */ |
| 1613 | printk(KERN_INFO "testing the IO APIC.......................\n"); |
| 1614 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1615 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) |
| 1616 | print_IO_APIC(ioapic_idx); |
Naga Chumbalkar | 42f0efc | 2011-07-12 21:17:35 +0000 | [diff] [blame] | 1617 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1618 | printk(KERN_DEBUG "IRQ to pin mappings:\n"); |
Thomas Gleixner | ad9f433 | 2010-09-30 11:26:43 +0200 | [diff] [blame] | 1619 | for_each_active_irq(irq) { |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 1620 | struct irq_pin_list *entry; |
| 1621 | |
Mathias Nyman | 6fd36ba | 2011-11-10 13:45:24 +0000 | [diff] [blame] | 1622 | chip = irq_get_chip(irq); |
| 1623 | if (chip != &ioapic_chip) |
| 1624 | continue; |
| 1625 | |
Thomas Gleixner | 2c77865 | 2011-03-12 12:20:43 +0100 | [diff] [blame] | 1626 | cfg = irq_get_chip_data(irq); |
Daniel Kiper | 05e4076 | 2010-08-20 00:46:16 +0200 | [diff] [blame] | 1627 | if (!cfg) |
| 1628 | continue; |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 1629 | entry = cfg->irq_2_pin; |
Yinghai Lu | 0f978f4 | 2008-08-19 20:50:26 -0700 | [diff] [blame] | 1630 | if (!entry) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1631 | continue; |
Yinghai Lu | 8f09cd2 | 2008-08-19 20:50:51 -0700 | [diff] [blame] | 1632 | printk(KERN_DEBUG "IRQ%d ", irq); |
Cyrill Gorcunov | 2977fb3 | 2009-08-01 11:47:59 +0400 | [diff] [blame] | 1633 | for_each_irq_pin(entry, cfg->irq_2_pin) |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 1634 | pr_cont("-> %d:%d", entry->apic, entry->pin); |
| 1635 | pr_cont("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1636 | } |
| 1637 | |
| 1638 | printk(KERN_INFO ".................................... done.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1639 | } |
| 1640 | |
Ingo Molnar | 251e1e4 | 2009-07-02 08:54:01 +0200 | [diff] [blame] | 1641 | __apicdebuginit(void) print_APIC_field(int base) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1642 | { |
Ingo Molnar | 251e1e4 | 2009-07-02 08:54:01 +0200 | [diff] [blame] | 1643 | int i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1644 | |
Ingo Molnar | 251e1e4 | 2009-07-02 08:54:01 +0200 | [diff] [blame] | 1645 | printk(KERN_DEBUG); |
| 1646 | |
| 1647 | for (i = 0; i < 8; i++) |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 1648 | pr_cont("%08x", apic_read(base + i*0x10)); |
Ingo Molnar | 251e1e4 | 2009-07-02 08:54:01 +0200 | [diff] [blame] | 1649 | |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 1650 | pr_cont("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1651 | } |
| 1652 | |
Maciej W. Rozycki | 32f71af | 2008-07-21 00:52:49 +0100 | [diff] [blame] | 1653 | __apicdebuginit(void) print_local_APIC(void *dummy) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1654 | { |
Andreas Herrmann | 97a5271 | 2009-05-08 18:23:50 +0200 | [diff] [blame] | 1655 | unsigned int i, v, ver, maxlvt; |
Hiroshi Shimamoto | 7ab6af7 | 2008-07-30 17:36:48 -0700 | [diff] [blame] | 1656 | u64 icr; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1657 | |
Ingo Molnar | 251e1e4 | 2009-07-02 08:54:01 +0200 | [diff] [blame] | 1658 | printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1659 | smp_processor_id(), hard_smp_processor_id()); |
Andreas Herrmann | 6682311 | 2008-06-05 16:35:10 +0200 | [diff] [blame] | 1660 | v = apic_read(APIC_ID); |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1661 | printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1662 | v = apic_read(APIC_LVR); |
| 1663 | printk(KERN_INFO "... APIC VERSION: %08x\n", v); |
| 1664 | ver = GET_APIC_VERSION(v); |
Thomas Gleixner | e05d723 | 2007-02-16 01:27:58 -0800 | [diff] [blame] | 1665 | maxlvt = lapic_get_maxlvt(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1666 | |
| 1667 | v = apic_read(APIC_TASKPRI); |
| 1668 | printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); |
| 1669 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1670 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
Yinghai Lu | a11b5ab | 2008-09-03 16:58:31 -0700 | [diff] [blame] | 1671 | if (!APIC_XAPIC(ver)) { |
| 1672 | v = apic_read(APIC_ARBPRI); |
| 1673 | printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, |
| 1674 | v & APIC_ARBPRI_MASK); |
| 1675 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1676 | v = apic_read(APIC_PROCPRI); |
| 1677 | printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); |
| 1678 | } |
| 1679 | |
Yinghai Lu | a11b5ab | 2008-09-03 16:58:31 -0700 | [diff] [blame] | 1680 | /* |
| 1681 | * Remote read supported only in the 82489DX and local APIC for |
| 1682 | * Pentium processors. |
| 1683 | */ |
| 1684 | if (!APIC_INTEGRATED(ver) || maxlvt == 3) { |
| 1685 | v = apic_read(APIC_RRR); |
| 1686 | printk(KERN_DEBUG "... APIC RRR: %08x\n", v); |
| 1687 | } |
| 1688 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1689 | v = apic_read(APIC_LDR); |
| 1690 | printk(KERN_DEBUG "... APIC LDR: %08x\n", v); |
Yinghai Lu | a11b5ab | 2008-09-03 16:58:31 -0700 | [diff] [blame] | 1691 | if (!x2apic_enabled()) { |
| 1692 | v = apic_read(APIC_DFR); |
| 1693 | printk(KERN_DEBUG "... APIC DFR: %08x\n", v); |
| 1694 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1695 | v = apic_read(APIC_SPIV); |
| 1696 | printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); |
| 1697 | |
| 1698 | printk(KERN_DEBUG "... APIC ISR field:\n"); |
Ingo Molnar | 251e1e4 | 2009-07-02 08:54:01 +0200 | [diff] [blame] | 1699 | print_APIC_field(APIC_ISR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1700 | printk(KERN_DEBUG "... APIC TMR field:\n"); |
Ingo Molnar | 251e1e4 | 2009-07-02 08:54:01 +0200 | [diff] [blame] | 1701 | print_APIC_field(APIC_TMR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1702 | printk(KERN_DEBUG "... APIC IRR field:\n"); |
Ingo Molnar | 251e1e4 | 2009-07-02 08:54:01 +0200 | [diff] [blame] | 1703 | print_APIC_field(APIC_IRR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1704 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1705 | if (APIC_INTEGRATED(ver)) { /* !82489DX */ |
| 1706 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1707 | apic_write(APIC_ESR, 0); |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1708 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1709 | v = apic_read(APIC_ESR); |
| 1710 | printk(KERN_DEBUG "... APIC ESR: %08x\n", v); |
| 1711 | } |
| 1712 | |
Hiroshi Shimamoto | 7ab6af7 | 2008-07-30 17:36:48 -0700 | [diff] [blame] | 1713 | icr = apic_icr_read(); |
Ingo Molnar | 0c425ce | 2008-08-18 13:04:26 +0200 | [diff] [blame] | 1714 | printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); |
| 1715 | printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1716 | |
| 1717 | v = apic_read(APIC_LVTT); |
| 1718 | printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); |
| 1719 | |
| 1720 | if (maxlvt > 3) { /* PC is LVT#4. */ |
| 1721 | v = apic_read(APIC_LVTPC); |
| 1722 | printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); |
| 1723 | } |
| 1724 | v = apic_read(APIC_LVT0); |
| 1725 | printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); |
| 1726 | v = apic_read(APIC_LVT1); |
| 1727 | printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); |
| 1728 | |
| 1729 | if (maxlvt > 2) { /* ERR is LVT#3. */ |
| 1730 | v = apic_read(APIC_LVTERR); |
| 1731 | printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); |
| 1732 | } |
| 1733 | |
| 1734 | v = apic_read(APIC_TMICT); |
| 1735 | printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); |
| 1736 | v = apic_read(APIC_TMCCT); |
| 1737 | printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); |
| 1738 | v = apic_read(APIC_TDCR); |
| 1739 | printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); |
Andreas Herrmann | 97a5271 | 2009-05-08 18:23:50 +0200 | [diff] [blame] | 1740 | |
| 1741 | if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { |
| 1742 | v = apic_read(APIC_EFEAT); |
| 1743 | maxlvt = (v >> 16) & 0xff; |
| 1744 | printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); |
| 1745 | v = apic_read(APIC_ECTRL); |
| 1746 | printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); |
| 1747 | for (i = 0; i < maxlvt; i++) { |
| 1748 | v = apic_read(APIC_EILVTn(i)); |
| 1749 | printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); |
| 1750 | } |
| 1751 | } |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 1752 | pr_cont("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1753 | } |
| 1754 | |
Cyrill Gorcunov | 2626eb2 | 2009-10-14 00:07:05 +0400 | [diff] [blame] | 1755 | __apicdebuginit(void) print_local_APICs(int maxcpu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1756 | { |
Yinghai Lu | ffd5aae | 2008-08-19 20:50:50 -0700 | [diff] [blame] | 1757 | int cpu; |
| 1758 | |
Cyrill Gorcunov | 2626eb2 | 2009-10-14 00:07:05 +0400 | [diff] [blame] | 1759 | if (!maxcpu) |
| 1760 | return; |
| 1761 | |
Yinghai Lu | ffd5aae | 2008-08-19 20:50:50 -0700 | [diff] [blame] | 1762 | preempt_disable(); |
Cyrill Gorcunov | 2626eb2 | 2009-10-14 00:07:05 +0400 | [diff] [blame] | 1763 | for_each_online_cpu(cpu) { |
| 1764 | if (cpu >= maxcpu) |
| 1765 | break; |
Yinghai Lu | ffd5aae | 2008-08-19 20:50:50 -0700 | [diff] [blame] | 1766 | smp_call_function_single(cpu, print_local_APIC, NULL, 1); |
Cyrill Gorcunov | 2626eb2 | 2009-10-14 00:07:05 +0400 | [diff] [blame] | 1767 | } |
Yinghai Lu | ffd5aae | 2008-08-19 20:50:50 -0700 | [diff] [blame] | 1768 | preempt_enable(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1769 | } |
| 1770 | |
Maciej W. Rozycki | 32f71af | 2008-07-21 00:52:49 +0100 | [diff] [blame] | 1771 | __apicdebuginit(void) print_PIC(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1772 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1773 | unsigned int v; |
| 1774 | unsigned long flags; |
| 1775 | |
Jacob Pan | b81bb37 | 2009-11-09 11:27:04 -0800 | [diff] [blame] | 1776 | if (!legacy_pic->nr_legacy_irqs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1777 | return; |
| 1778 | |
| 1779 | printk(KERN_DEBUG "\nprinting PIC contents\n"); |
| 1780 | |
Thomas Gleixner | 5619c28 | 2009-07-25 18:35:11 +0200 | [diff] [blame] | 1781 | raw_spin_lock_irqsave(&i8259A_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1782 | |
| 1783 | v = inb(0xa1) << 8 | inb(0x21); |
| 1784 | printk(KERN_DEBUG "... PIC IMR: %04x\n", v); |
| 1785 | |
| 1786 | v = inb(0xa0) << 8 | inb(0x20); |
| 1787 | printk(KERN_DEBUG "... PIC IRR: %04x\n", v); |
| 1788 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1789 | outb(0x0b,0xa0); |
| 1790 | outb(0x0b,0x20); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1791 | v = inb(0xa0) << 8 | inb(0x20); |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1792 | outb(0x0a,0xa0); |
| 1793 | outb(0x0a,0x20); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1794 | |
Thomas Gleixner | 5619c28 | 2009-07-25 18:35:11 +0200 | [diff] [blame] | 1795 | raw_spin_unlock_irqrestore(&i8259A_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1796 | |
| 1797 | printk(KERN_DEBUG "... PIC ISR: %04x\n", v); |
| 1798 | |
| 1799 | v = inb(0x4d1) << 8 | inb(0x4d0); |
| 1800 | printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); |
| 1801 | } |
| 1802 | |
Cyrill Gorcunov | 2626eb2 | 2009-10-14 00:07:05 +0400 | [diff] [blame] | 1803 | static int __initdata show_lapic = 1; |
| 1804 | static __init int setup_show_lapic(char *arg) |
Maciej W. Rozycki | 32f71af | 2008-07-21 00:52:49 +0100 | [diff] [blame] | 1805 | { |
Cyrill Gorcunov | 2626eb2 | 2009-10-14 00:07:05 +0400 | [diff] [blame] | 1806 | int num = -1; |
| 1807 | |
| 1808 | if (strcmp(arg, "all") == 0) { |
| 1809 | show_lapic = CONFIG_NR_CPUS; |
| 1810 | } else { |
| 1811 | get_option(&arg, &num); |
| 1812 | if (num >= 0) |
| 1813 | show_lapic = num; |
| 1814 | } |
| 1815 | |
| 1816 | return 1; |
| 1817 | } |
| 1818 | __setup("show_lapic=", setup_show_lapic); |
| 1819 | |
| 1820 | __apicdebuginit(int) print_ICs(void) |
| 1821 | { |
| 1822 | if (apic_verbosity == APIC_QUIET) |
| 1823 | return 0; |
| 1824 | |
Maciej W. Rozycki | 32f71af | 2008-07-21 00:52:49 +0100 | [diff] [blame] | 1825 | print_PIC(); |
Yinghai Lu | 4797f6b | 2009-05-02 10:40:57 -0700 | [diff] [blame] | 1826 | |
| 1827 | /* don't print out if apic is not there */ |
Cyrill Gorcunov | 8312136 | 2009-09-15 11:12:30 +0400 | [diff] [blame] | 1828 | if (!cpu_has_apic && !apic_from_smp_config()) |
Yinghai Lu | 4797f6b | 2009-05-02 10:40:57 -0700 | [diff] [blame] | 1829 | return 0; |
| 1830 | |
Cyrill Gorcunov | 2626eb2 | 2009-10-14 00:07:05 +0400 | [diff] [blame] | 1831 | print_local_APICs(show_lapic); |
Yinghai Lu | cda417d | 2011-10-12 00:33:39 -0700 | [diff] [blame] | 1832 | print_IO_APICs(); |
Maciej W. Rozycki | 32f71af | 2008-07-21 00:52:49 +0100 | [diff] [blame] | 1833 | |
| 1834 | return 0; |
| 1835 | } |
| 1836 | |
Naga Chumbalkar | ded1f6a | 2011-07-08 08:36:34 +0000 | [diff] [blame] | 1837 | late_initcall(print_ICs); |
Maciej W. Rozycki | 32f71af | 2008-07-21 00:52:49 +0100 | [diff] [blame] | 1838 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1839 | |
Yinghai Lu | efa2559 | 2008-08-19 20:50:36 -0700 | [diff] [blame] | 1840 | /* Where if anywhere is the i8259 connect in external int mode */ |
| 1841 | static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; |
| 1842 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1843 | void __init enable_IO_APIC(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1844 | { |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 1845 | int i8259_apic, i8259_pin; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1846 | int apic; |
Thomas Gleixner | bc07844 | 2009-08-29 18:09:57 +0200 | [diff] [blame] | 1847 | |
Jacob Pan | b81bb37 | 2009-11-09 11:27:04 -0800 | [diff] [blame] | 1848 | if (!legacy_pic->nr_legacy_irqs) |
Thomas Gleixner | bc07844 | 2009-08-29 18:09:57 +0200 | [diff] [blame] | 1849 | return; |
| 1850 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1851 | for(apic = 0; apic < nr_ioapics; apic++) { |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 1852 | int pin; |
| 1853 | /* See if any of the pins is in ExtINT mode */ |
Suresh Siddha | b69c6c3 | 2011-05-18 16:31:35 -0700 | [diff] [blame] | 1854 | for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 1855 | struct IO_APIC_route_entry entry; |
Andi Kleen | cf4c6a2 | 2006-09-26 10:52:30 +0200 | [diff] [blame] | 1856 | entry = ioapic_read_entry(apic, pin); |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 1857 | |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 1858 | /* If the interrupt line is enabled and in ExtInt mode |
| 1859 | * I have found the pin where the i8259 is connected. |
| 1860 | */ |
| 1861 | if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { |
| 1862 | ioapic_i8259.apic = apic; |
| 1863 | ioapic_i8259.pin = pin; |
| 1864 | goto found_i8259; |
| 1865 | } |
| 1866 | } |
| 1867 | } |
| 1868 | found_i8259: |
| 1869 | /* Look to see what if the MP table has reported the ExtINT */ |
| 1870 | /* If we could not find the appropriate pin by looking at the ioapic |
| 1871 | * the i8259 probably is not connected the ioapic but give the |
| 1872 | * mptable a chance anyway. |
| 1873 | */ |
| 1874 | i8259_pin = find_isa_irq_pin(0, mp_ExtINT); |
| 1875 | i8259_apic = find_isa_irq_apic(0, mp_ExtINT); |
| 1876 | /* Trust the MP table if nothing is setup in the hardware */ |
| 1877 | if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { |
| 1878 | printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); |
| 1879 | ioapic_i8259.pin = i8259_pin; |
| 1880 | ioapic_i8259.apic = i8259_apic; |
| 1881 | } |
| 1882 | /* Complain if the MP table and the hardware disagree */ |
| 1883 | if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && |
| 1884 | (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) |
| 1885 | { |
| 1886 | printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1887 | } |
| 1888 | |
| 1889 | /* |
| 1890 | * Do not trust the IO-APIC being empty at bootup |
| 1891 | */ |
| 1892 | clear_IO_APIC(); |
| 1893 | } |
| 1894 | |
Joerg Roedel | 1c4248c | 2012-09-26 12:44:35 +0200 | [diff] [blame] | 1895 | void native_disable_io_apic(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1896 | { |
| 1897 | /* |
Karsten Wiese | 0b968d2 | 2005-09-09 12:59:04 +0200 | [diff] [blame] | 1898 | * If the i8259 is routed through an IOAPIC |
Eric W. Biederman | 650927e | 2005-06-25 14:57:44 -0700 | [diff] [blame] | 1899 | * Put that IOAPIC in virtual wire mode |
Karsten Wiese | 0b968d2 | 2005-09-09 12:59:04 +0200 | [diff] [blame] | 1900 | * so legacy interrupts can be delivered. |
Eric W. Biederman | 650927e | 2005-06-25 14:57:44 -0700 | [diff] [blame] | 1901 | */ |
Joerg Roedel | 1c4248c | 2012-09-26 12:44:35 +0200 | [diff] [blame] | 1902 | if (ioapic_i8259.pin != -1) { |
Eric W. Biederman | 650927e | 2005-06-25 14:57:44 -0700 | [diff] [blame] | 1903 | struct IO_APIC_route_entry entry; |
Eric W. Biederman | 650927e | 2005-06-25 14:57:44 -0700 | [diff] [blame] | 1904 | |
| 1905 | memset(&entry, 0, sizeof(entry)); |
| 1906 | entry.mask = 0; /* Enabled */ |
| 1907 | entry.trigger = 0; /* Edge */ |
| 1908 | entry.irr = 0; |
| 1909 | entry.polarity = 0; /* High */ |
| 1910 | entry.delivery_status = 0; |
| 1911 | entry.dest_mode = 0; /* Physical */ |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 1912 | entry.delivery_mode = dest_ExtINT; /* ExtInt */ |
Eric W. Biederman | 650927e | 2005-06-25 14:57:44 -0700 | [diff] [blame] | 1913 | entry.vector = 0; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1914 | entry.dest = read_apic_id(); |
Eric W. Biederman | 650927e | 2005-06-25 14:57:44 -0700 | [diff] [blame] | 1915 | |
| 1916 | /* |
| 1917 | * Add it to the IO-APIC irq-routing table: |
| 1918 | */ |
Andi Kleen | cf4c6a2 | 2006-09-26 10:52:30 +0200 | [diff] [blame] | 1919 | ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); |
Eric W. Biederman | 650927e | 2005-06-25 14:57:44 -0700 | [diff] [blame] | 1920 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1921 | |
Cyrill Gorcunov | 8312136 | 2009-09-15 11:12:30 +0400 | [diff] [blame] | 1922 | if (cpu_has_apic || apic_from_smp_config()) |
Joerg Roedel | 1c4248c | 2012-09-26 12:44:35 +0200 | [diff] [blame] | 1923 | disconnect_bsp_APIC(ioapic_i8259.pin != -1); |
| 1924 | |
| 1925 | } |
| 1926 | |
| 1927 | /* |
| 1928 | * Not an __init, needed by the reboot code |
| 1929 | */ |
| 1930 | void disable_IO_APIC(void) |
| 1931 | { |
| 1932 | /* |
| 1933 | * Clear the IO-APIC before rebooting: |
| 1934 | */ |
| 1935 | clear_IO_APIC(); |
| 1936 | |
| 1937 | if (!legacy_pic->nr_legacy_irqs) |
| 1938 | return; |
| 1939 | |
| 1940 | x86_io_apic_ops.disable(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1941 | } |
| 1942 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 1943 | #ifdef CONFIG_X86_32 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1944 | /* |
| 1945 | * function to set the IO-APIC physical IDs based on the |
| 1946 | * values stored in the MPC table. |
| 1947 | * |
| 1948 | * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 |
| 1949 | */ |
Sebastian Andrzej Siewior | a38c538 | 2010-11-26 17:50:20 +0100 | [diff] [blame] | 1950 | void __init setup_ioapic_ids_from_mpc_nocheck(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1951 | { |
| 1952 | union IO_APIC_reg_00 reg_00; |
| 1953 | physid_mask_t phys_id_present_map; |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1954 | int ioapic_idx; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1955 | int i; |
| 1956 | unsigned char old_id; |
| 1957 | unsigned long flags; |
| 1958 | |
Natalie Protasevich | ca05fea | 2005-06-23 00:08:22 -0700 | [diff] [blame] | 1959 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1960 | * This is broken; anything with a real cpu count has to |
| 1961 | * circumvent this idiocy regardless. |
| 1962 | */ |
Cyrill Gorcunov | 7abc075 | 2009-11-10 01:06:59 +0300 | [diff] [blame] | 1963 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1964 | |
| 1965 | /* |
| 1966 | * Set the IOAPIC ID to the value stored in the MPC table. |
| 1967 | */ |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1968 | for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1969 | /* Read the register 0 value */ |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 1970 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1971 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 1972 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Paolo Ciarrocchi | 3606244 | 2008-06-08 13:07:18 +0200 | [diff] [blame] | 1973 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1974 | old_id = mpc_ioapic_id(ioapic_idx); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1975 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1976 | if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1977 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1978 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1979 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
| 1980 | reg_00.bits.ID); |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1981 | ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1982 | } |
| 1983 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1984 | /* |
| 1985 | * Sanity check, is the ID really free? Every APIC in a |
| 1986 | * system must have a unique ID or we get lots of nice |
| 1987 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
| 1988 | */ |
Cyrill Gorcunov | 7abc075 | 2009-11-10 01:06:59 +0300 | [diff] [blame] | 1989 | if (apic->check_apicid_used(&phys_id_present_map, |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1990 | mpc_ioapic_id(ioapic_idx))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1991 | printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 1992 | ioapic_idx, mpc_ioapic_id(ioapic_idx)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1993 | for (i = 0; i < get_physical_broadcast(); i++) |
| 1994 | if (!physid_isset(i, phys_id_present_map)) |
| 1995 | break; |
| 1996 | if (i >= get_physical_broadcast()) |
| 1997 | panic("Max APIC ID exceeded!\n"); |
| 1998 | printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", |
| 1999 | i); |
| 2000 | physid_set(i, phys_id_present_map); |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 2001 | ioapics[ioapic_idx].mp_config.apicid = i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2002 | } else { |
| 2003 | physid_mask_t tmp; |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 2004 | apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx), |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 2005 | &tmp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2006 | apic_printk(APIC_VERBOSE, "Setting %d in the " |
| 2007 | "phys_id_present_map\n", |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 2008 | mpc_ioapic_id(ioapic_idx)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2009 | physids_or(phys_id_present_map, phys_id_present_map, tmp); |
| 2010 | } |
| 2011 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2012 | /* |
| 2013 | * We need to adjust the IRQ routing table |
| 2014 | * if the ID changed. |
| 2015 | */ |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 2016 | if (old_id != mpc_ioapic_id(ioapic_idx)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2017 | for (i = 0; i < mp_irq_entries; i++) |
Jaswinder Singh Rajput | c2c2174 | 2009-01-12 17:47:22 +0530 | [diff] [blame] | 2018 | if (mp_irqs[i].dstapic == old_id) |
| 2019 | mp_irqs[i].dstapic |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 2020 | = mpc_ioapic_id(ioapic_idx); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2021 | |
| 2022 | /* |
Yinghai Lu | 60d79fd | 2010-12-07 00:59:49 -0800 | [diff] [blame] | 2023 | * Update the ID register according to the right value |
| 2024 | * from the MPC table if they are different. |
Paolo Ciarrocchi | 3606244 | 2008-06-08 13:07:18 +0200 | [diff] [blame] | 2025 | */ |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 2026 | if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID) |
Yinghai Lu | 60d79fd | 2010-12-07 00:59:49 -0800 | [diff] [blame] | 2027 | continue; |
| 2028 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2029 | apic_printk(APIC_VERBOSE, KERN_INFO |
| 2030 | "...changing IO-APIC physical APIC ID to %d ...", |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 2031 | mpc_ioapic_id(ioapic_idx)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2032 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 2033 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 2034 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 2035 | io_apic_write(ioapic_idx, 0, reg_00.raw); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 2036 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2037 | |
| 2038 | /* |
| 2039 | * Sanity check |
| 2040 | */ |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 2041 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 2042 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 2043 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 2044 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 2045 | pr_cont("could not set ID!\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2046 | else |
| 2047 | apic_printk(APIC_VERBOSE, " ok.\n"); |
| 2048 | } |
| 2049 | } |
Sebastian Andrzej Siewior | a38c538 | 2010-11-26 17:50:20 +0100 | [diff] [blame] | 2050 | |
| 2051 | void __init setup_ioapic_ids_from_mpc(void) |
| 2052 | { |
| 2053 | |
| 2054 | if (acpi_ioapic) |
| 2055 | return; |
| 2056 | /* |
| 2057 | * Don't check I/O APIC IDs for xAPIC systems. They have |
| 2058 | * no meaning without the serial APIC bus. |
| 2059 | */ |
| 2060 | if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
| 2061 | || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) |
| 2062 | return; |
| 2063 | setup_ioapic_ids_from_mpc_nocheck(); |
| 2064 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2065 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2066 | |
Zachary Amsden | 7ce0bcf | 2007-02-13 13:26:21 +0100 | [diff] [blame] | 2067 | int no_timer_check __initdata; |
Zachary Amsden | 8542b20 | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 2068 | |
| 2069 | static int __init notimercheck(char *s) |
| 2070 | { |
| 2071 | no_timer_check = 1; |
| 2072 | return 1; |
| 2073 | } |
| 2074 | __setup("no_timer_check", notimercheck); |
| 2075 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2076 | /* |
| 2077 | * There is a nasty bug in some older SMP boards, their mptable lies |
| 2078 | * about the timer IRQ. We do the following to work around the situation: |
| 2079 | * |
| 2080 | * - timer IRQ defaults to IO-APIC IRQ |
| 2081 | * - if this function detects that timer IRQs are defunct, then we fall |
| 2082 | * back to ISA timer IRQs |
| 2083 | */ |
Adrian Bunk | f0a7a5c | 2007-07-21 17:10:29 +0200 | [diff] [blame] | 2084 | static int __init timer_irq_works(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2085 | { |
| 2086 | unsigned long t1 = jiffies; |
Ingo Molnar | 4aae070 | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 2087 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2088 | |
Zachary Amsden | 8542b20 | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 2089 | if (no_timer_check) |
| 2090 | return 1; |
| 2091 | |
Ingo Molnar | 4aae070 | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 2092 | local_save_flags(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2093 | local_irq_enable(); |
| 2094 | /* Let ten ticks pass... */ |
| 2095 | mdelay((10 * 1000) / HZ); |
Ingo Molnar | 4aae070 | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 2096 | local_irq_restore(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2097 | |
| 2098 | /* |
| 2099 | * Expect a few ticks at least, to be sure some possible |
| 2100 | * glue logic does not lock up after one or two first |
| 2101 | * ticks in a non-ExtINT mode. Also the local APIC |
| 2102 | * might have cached one ExtINT interrupt. Finally, at |
| 2103 | * least one tick may be lost due to delays. |
| 2104 | */ |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2105 | |
| 2106 | /* jiffies wrap? */ |
Julia Lawall | 1d16b53 | 2008-01-30 13:32:19 +0100 | [diff] [blame] | 2107 | if (time_after(jiffies, t1 + 4)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2108 | return 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2109 | return 0; |
| 2110 | } |
| 2111 | |
| 2112 | /* |
| 2113 | * In the SMP+IOAPIC case it might happen that there are an unspecified |
| 2114 | * number of pending IRQ events unhandled. These cases are very rare, |
| 2115 | * so we 'resend' these IRQs via IPIs, to the same CPU. It's much |
| 2116 | * better to do it this way as thus we do not have to be aware of |
| 2117 | * 'pending' interrupts in the IRQ path, except at this point. |
| 2118 | */ |
| 2119 | /* |
| 2120 | * Edge triggered needs to resend any interrupt |
| 2121 | * that was delayed but this is now handled in the device |
| 2122 | * independent code. |
| 2123 | */ |
| 2124 | |
| 2125 | /* |
| 2126 | * Starting up a edge-triggered IO-APIC interrupt is |
| 2127 | * nasty - we need to make sure that we get the edge. |
| 2128 | * If it is already asserted for some reason, we need |
| 2129 | * return 1 to indicate that is was pending. |
| 2130 | * |
| 2131 | * This is not complete - we should be able to fake |
| 2132 | * an edge even if it isn't on the 8259A... |
| 2133 | */ |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2134 | |
Thomas Gleixner | 61a38ce | 2010-09-28 16:00:34 +0200 | [diff] [blame] | 2135 | static unsigned int startup_ioapic_irq(struct irq_data *data) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2136 | { |
Thomas Gleixner | 61a38ce | 2010-09-28 16:00:34 +0200 | [diff] [blame] | 2137 | int was_pending = 0, irq = data->irq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2138 | unsigned long flags; |
| 2139 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 2140 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Jacob Pan | b81bb37 | 2009-11-09 11:27:04 -0800 | [diff] [blame] | 2141 | if (irq < legacy_pic->nr_legacy_irqs) { |
Thomas Gleixner | 4305df9 | 2010-09-28 15:01:33 +0200 | [diff] [blame] | 2142 | legacy_pic->mask(irq); |
Jacob Pan | b81bb37 | 2009-11-09 11:27:04 -0800 | [diff] [blame] | 2143 | if (legacy_pic->irq_pending(irq)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2144 | was_pending = 1; |
| 2145 | } |
Thomas Gleixner | 61a38ce | 2010-09-28 16:00:34 +0200 | [diff] [blame] | 2146 | __unmask_ioapic(data->chip_data); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 2147 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2148 | |
| 2149 | return was_pending; |
| 2150 | } |
| 2151 | |
Thomas Gleixner | 90297c5 | 2010-09-28 16:03:54 +0200 | [diff] [blame] | 2152 | static int ioapic_retrigger_irq(struct irq_data *data) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2153 | { |
Thomas Gleixner | 90297c5 | 2010-09-28 16:03:54 +0200 | [diff] [blame] | 2154 | struct irq_cfg *cfg = data->chip_data; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2155 | unsigned long flags; |
Fenghua Yu | 8d966a0 | 2012-11-13 11:32:49 -0800 | [diff] [blame] | 2156 | int cpu; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2157 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 2158 | raw_spin_lock_irqsave(&vector_lock, flags); |
Fenghua Yu | 8d966a0 | 2012-11-13 11:32:49 -0800 | [diff] [blame] | 2159 | cpu = cpumask_first_and(cfg->domain, cpu_online_mask); |
| 2160 | apic->send_IPI_mask(cpumask_of(cpu), cfg->vector); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 2161 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
Ingo Molnar | c0ad90a | 2006-06-29 02:24:44 -0700 | [diff] [blame] | 2162 | |
| 2163 | return 1; |
| 2164 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2165 | |
| 2166 | /* |
| 2167 | * Level and edge triggered IO-APIC interrupts need different handling, |
| 2168 | * so we use two separate IRQ descriptors. Edge triggered IRQs can be |
| 2169 | * handled with the level-triggered descriptor, but that one has slightly |
| 2170 | * more overhead. Level-triggered interrupts cannot be handled with the |
| 2171 | * edge-triggered handler, without risking IRQ storms and other ugly |
| 2172 | * races. |
| 2173 | */ |
Ingo Molnar | c0ad90a | 2006-06-29 02:24:44 -0700 | [diff] [blame] | 2174 | |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2175 | #ifdef CONFIG_SMP |
Dimitri Sivanich | 9338ad6 | 2009-10-13 15:32:36 -0500 | [diff] [blame] | 2176 | void send_cleanup_vector(struct irq_cfg *cfg) |
Gary Hade | e85abf8 | 2009-04-08 14:07:25 -0700 | [diff] [blame] | 2177 | { |
| 2178 | cpumask_var_t cleanup_mask; |
| 2179 | |
| 2180 | if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { |
| 2181 | unsigned int i; |
Gary Hade | e85abf8 | 2009-04-08 14:07:25 -0700 | [diff] [blame] | 2182 | for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) |
| 2183 | apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); |
| 2184 | } else { |
| 2185 | cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); |
Gary Hade | e85abf8 | 2009-04-08 14:07:25 -0700 | [diff] [blame] | 2186 | apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); |
| 2187 | free_cpumask_var(cleanup_mask); |
| 2188 | } |
| 2189 | cfg->move_in_progress = 0; |
| 2190 | } |
| 2191 | |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2192 | asmlinkage void smp_irq_move_cleanup_interrupt(void) |
| 2193 | { |
| 2194 | unsigned vector, me; |
Hiroshi Shimamoto | 8f2466f | 2008-12-08 19:19:07 -0800 | [diff] [blame] | 2195 | |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2196 | ack_APIC_irq(); |
| 2197 | irq_enter(); |
Frederic Weisbecker | 98ad1cc | 2011-10-07 18:22:09 +0200 | [diff] [blame] | 2198 | exit_idle(); |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2199 | |
| 2200 | me = smp_processor_id(); |
| 2201 | for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { |
Prarit Bhargava | c7a730f | 2014-01-13 08:40:20 -0500 | [diff] [blame] | 2202 | int irq; |
Suresh Siddha | 68a8ca5 | 2009-03-16 17:05:04 -0700 | [diff] [blame] | 2203 | unsigned int irr; |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2204 | struct irq_desc *desc; |
| 2205 | struct irq_cfg *cfg; |
Tejun Heo | 0a3aee0 | 2010-12-18 16:28:55 +0100 | [diff] [blame] | 2206 | irq = __this_cpu_read(vector_irq[vector]); |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2207 | |
Prarit Bhargava | 9345005 | 2014-01-05 11:10:52 -0500 | [diff] [blame] | 2208 | if (irq <= VECTOR_UNDEFINED) |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 2209 | continue; |
| 2210 | |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2211 | desc = irq_to_desc(irq); |
| 2212 | if (!desc) |
| 2213 | continue; |
| 2214 | |
| 2215 | cfg = irq_cfg(irq); |
Dimitri Sivanich | 94777fc | 2012-10-16 07:50:21 -0500 | [diff] [blame] | 2216 | if (!cfg) |
| 2217 | continue; |
| 2218 | |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 2219 | raw_spin_lock(&desc->lock); |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2220 | |
Suresh Siddha | 7f41c2e | 2010-01-06 10:56:31 -0800 | [diff] [blame] | 2221 | /* |
| 2222 | * Check if the irq migration is in progress. If so, we |
| 2223 | * haven't received the cleanup request yet for this irq. |
| 2224 | */ |
| 2225 | if (cfg->move_in_progress) |
| 2226 | goto unlock; |
| 2227 | |
Mike Travis | 22f65d3 | 2008-12-16 17:33:56 -0800 | [diff] [blame] | 2228 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2229 | goto unlock; |
| 2230 | |
Suresh Siddha | 68a8ca5 | 2009-03-16 17:05:04 -0700 | [diff] [blame] | 2231 | irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); |
| 2232 | /* |
| 2233 | * Check if the vector that needs to be cleanedup is |
| 2234 | * registered at the cpu's IRR. If so, then this is not |
| 2235 | * the best time to clean it up. Lets clean it up in the |
| 2236 | * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR |
| 2237 | * to myself. |
| 2238 | */ |
| 2239 | if (irr & (1 << (vector % 32))) { |
| 2240 | apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); |
| 2241 | goto unlock; |
| 2242 | } |
Tejun Heo | 0a3aee0 | 2010-12-18 16:28:55 +0100 | [diff] [blame] | 2243 | __this_cpu_write(vector_irq[vector], -1); |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2244 | unlock: |
Thomas Gleixner | 239007b | 2009-11-17 16:46:45 +0100 | [diff] [blame] | 2245 | raw_spin_unlock(&desc->lock); |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2246 | } |
| 2247 | |
| 2248 | irq_exit(); |
| 2249 | } |
| 2250 | |
Thomas Gleixner | dd5f15e | 2010-09-28 15:18:35 +0200 | [diff] [blame] | 2251 | static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2252 | { |
Suresh Siddha | a5e74b8 | 2009-10-26 14:24:34 -0800 | [diff] [blame] | 2253 | unsigned me; |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2254 | |
Yinghai Lu | fcef591 | 2009-04-27 17:58:23 -0700 | [diff] [blame] | 2255 | if (likely(!cfg->move_in_progress)) |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2256 | return; |
| 2257 | |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2258 | me = smp_processor_id(); |
Yinghai Lu | 10b888d | 2009-01-31 14:50:07 -0800 | [diff] [blame] | 2259 | |
Yinghai Lu | fcef591 | 2009-04-27 17:58:23 -0700 | [diff] [blame] | 2260 | if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) |
Mike Travis | 22f65d3 | 2008-12-16 17:33:56 -0800 | [diff] [blame] | 2261 | send_cleanup_vector(cfg); |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2262 | } |
Suresh Siddha | a5e74b8 | 2009-10-26 14:24:34 -0800 | [diff] [blame] | 2263 | |
Thomas Gleixner | dd5f15e | 2010-09-28 15:18:35 +0200 | [diff] [blame] | 2264 | static void irq_complete_move(struct irq_cfg *cfg) |
Suresh Siddha | a5e74b8 | 2009-10-26 14:24:34 -0800 | [diff] [blame] | 2265 | { |
Thomas Gleixner | dd5f15e | 2010-09-28 15:18:35 +0200 | [diff] [blame] | 2266 | __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); |
Suresh Siddha | a5e74b8 | 2009-10-26 14:24:34 -0800 | [diff] [blame] | 2267 | } |
| 2268 | |
| 2269 | void irq_force_complete_move(int irq) |
| 2270 | { |
Thomas Gleixner | 2c77865 | 2011-03-12 12:20:43 +0100 | [diff] [blame] | 2271 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
Suresh Siddha | a5e74b8 | 2009-10-26 14:24:34 -0800 | [diff] [blame] | 2272 | |
Prarit Bhargava | bbd391a | 2010-04-27 11:24:42 -0400 | [diff] [blame] | 2273 | if (!cfg) |
| 2274 | return; |
| 2275 | |
Thomas Gleixner | dd5f15e | 2010-09-28 15:18:35 +0200 | [diff] [blame] | 2276 | __irq_complete_move(cfg, cfg->vector); |
Suresh Siddha | a5e74b8 | 2009-10-26 14:24:34 -0800 | [diff] [blame] | 2277 | } |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2278 | #else |
Thomas Gleixner | dd5f15e | 2010-09-28 15:18:35 +0200 | [diff] [blame] | 2279 | static inline void irq_complete_move(struct irq_cfg *cfg) { } |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2280 | #endif |
Yinghai Lu | 3145e94 | 2008-12-05 18:58:34 -0800 | [diff] [blame] | 2281 | |
Suresh Siddha | 7eb9ae0 | 2012-06-14 18:28:49 -0700 | [diff] [blame] | 2282 | static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) |
| 2283 | { |
| 2284 | int apic, pin; |
| 2285 | struct irq_pin_list *entry; |
| 2286 | u8 vector = cfg->vector; |
| 2287 | |
| 2288 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
| 2289 | unsigned int reg; |
| 2290 | |
| 2291 | apic = entry->apic; |
| 2292 | pin = entry->pin; |
Joerg Roedel | 9f9d39e | 2012-09-26 12:44:46 +0200 | [diff] [blame] | 2293 | |
| 2294 | io_apic_write(apic, 0x11 + pin*2, dest); |
Suresh Siddha | 7eb9ae0 | 2012-06-14 18:28:49 -0700 | [diff] [blame] | 2295 | reg = io_apic_read(apic, 0x10 + pin*2); |
| 2296 | reg &= ~IO_APIC_REDIR_VECTOR_MASK; |
| 2297 | reg |= vector; |
| 2298 | io_apic_modify(apic, 0x10 + pin*2, reg); |
| 2299 | } |
| 2300 | } |
| 2301 | |
| 2302 | /* |
| 2303 | * Either sets data->affinity to a valid value, and returns |
| 2304 | * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and |
| 2305 | * leaves data->affinity untouched. |
| 2306 | */ |
| 2307 | int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, |
| 2308 | unsigned int *dest_id) |
| 2309 | { |
| 2310 | struct irq_cfg *cfg = data->chip_data; |
| 2311 | unsigned int irq = data->irq; |
| 2312 | int err; |
| 2313 | |
| 2314 | if (!config_enabled(CONFIG_SMP)) |
| 2315 | return -1; |
| 2316 | |
| 2317 | if (!cpumask_intersects(mask, cpu_online_mask)) |
| 2318 | return -EINVAL; |
| 2319 | |
| 2320 | err = assign_irq_vector(irq, cfg, mask); |
| 2321 | if (err) |
| 2322 | return err; |
| 2323 | |
| 2324 | err = apic->cpu_mask_to_apicid_and(mask, cfg->domain, dest_id); |
| 2325 | if (err) { |
| 2326 | if (assign_irq_vector(irq, cfg, data->affinity)) |
| 2327 | pr_err("Failed to recover vector for irq %d\n", irq); |
| 2328 | return err; |
| 2329 | } |
| 2330 | |
| 2331 | cpumask_copy(data->affinity, mask); |
| 2332 | |
| 2333 | return 0; |
| 2334 | } |
| 2335 | |
Joerg Roedel | 373dd7a | 2012-09-26 12:44:39 +0200 | [diff] [blame] | 2336 | |
| 2337 | int native_ioapic_set_affinity(struct irq_data *data, |
| 2338 | const struct cpumask *mask, |
| 2339 | bool force) |
Suresh Siddha | 7eb9ae0 | 2012-06-14 18:28:49 -0700 | [diff] [blame] | 2340 | { |
| 2341 | unsigned int dest, irq = data->irq; |
| 2342 | unsigned long flags; |
| 2343 | int ret; |
| 2344 | |
| 2345 | if (!config_enabled(CONFIG_SMP)) |
| 2346 | return -1; |
| 2347 | |
| 2348 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
| 2349 | ret = __ioapic_set_affinity(data, mask, &dest); |
| 2350 | if (!ret) { |
| 2351 | /* Only the high 8 bits are valid. */ |
| 2352 | dest = SET_APIC_LOGICAL_ID(dest); |
| 2353 | __target_IO_APIC_irq(irq, dest, data->chip_data); |
| 2354 | ret = IRQ_SET_MASK_OK_NOCOPY; |
| 2355 | } |
| 2356 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
| 2357 | return ret; |
| 2358 | } |
| 2359 | |
Thomas Gleixner | 90297c5 | 2010-09-28 16:03:54 +0200 | [diff] [blame] | 2360 | static void ack_apic_edge(struct irq_data *data) |
Yinghai Lu | 1d02519 | 2008-08-19 20:50:34 -0700 | [diff] [blame] | 2361 | { |
Thomas Gleixner | 90297c5 | 2010-09-28 16:03:54 +0200 | [diff] [blame] | 2362 | irq_complete_move(data->chip_data); |
Thomas Gleixner | 0822111 | 2011-02-04 18:56:11 +0100 | [diff] [blame] | 2363 | irq_move_irq(data); |
Yinghai Lu | 1d02519 | 2008-08-19 20:50:34 -0700 | [diff] [blame] | 2364 | ack_APIC_irq(); |
| 2365 | } |
| 2366 | |
Yinghai Lu | 3eb2cce | 2008-08-19 20:50:48 -0700 | [diff] [blame] | 2367 | atomic_t irq_mis_count; |
Yinghai Lu | 3eb2cce | 2008-08-19 20:50:48 -0700 | [diff] [blame] | 2368 | |
Alexander Gordeev | 4da7072 | 2012-03-20 15:19:36 +0100 | [diff] [blame] | 2369 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
Márton Németh | d1ecad6 | 2012-05-08 00:24:20 -0700 | [diff] [blame] | 2370 | static bool io_apic_level_ack_pending(struct irq_cfg *cfg) |
| 2371 | { |
| 2372 | struct irq_pin_list *entry; |
| 2373 | unsigned long flags; |
| 2374 | |
| 2375 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
| 2376 | for_each_irq_pin(entry, cfg->irq_2_pin) { |
| 2377 | unsigned int reg; |
| 2378 | int pin; |
| 2379 | |
| 2380 | pin = entry->pin; |
| 2381 | reg = io_apic_read(entry->apic, 0x10 + pin*2); |
| 2382 | /* Is the remote IRR bit set? */ |
| 2383 | if (reg & IO_APIC_REDIR_REMOTE_IRR) { |
| 2384 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
| 2385 | return true; |
| 2386 | } |
| 2387 | } |
| 2388 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
| 2389 | |
| 2390 | return false; |
| 2391 | } |
| 2392 | |
Alexander Gordeev | 4da7072 | 2012-03-20 15:19:36 +0100 | [diff] [blame] | 2393 | static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg) |
| 2394 | { |
| 2395 | /* If we are moving the irq we need to mask it */ |
| 2396 | if (unlikely(irqd_is_setaffinity_pending(data))) { |
| 2397 | mask_ioapic(cfg); |
| 2398 | return true; |
| 2399 | } |
| 2400 | return false; |
| 2401 | } |
| 2402 | |
| 2403 | static inline void ioapic_irqd_unmask(struct irq_data *data, |
| 2404 | struct irq_cfg *cfg, bool masked) |
| 2405 | { |
| 2406 | if (unlikely(masked)) { |
| 2407 | /* Only migrate the irq if the ack has been received. |
| 2408 | * |
| 2409 | * On rare occasions the broadcast level triggered ack gets |
| 2410 | * delayed going to ioapics, and if we reprogram the |
| 2411 | * vector while Remote IRR is still set the irq will never |
| 2412 | * fire again. |
| 2413 | * |
| 2414 | * To prevent this scenario we read the Remote IRR bit |
| 2415 | * of the ioapic. This has two effects. |
| 2416 | * - On any sane system the read of the ioapic will |
| 2417 | * flush writes (and acks) going to the ioapic from |
| 2418 | * this cpu. |
| 2419 | * - We get to see if the ACK has actually been delivered. |
| 2420 | * |
| 2421 | * Based on failed experiments of reprogramming the |
| 2422 | * ioapic entry from outside of irq context starting |
| 2423 | * with masking the ioapic entry and then polling until |
| 2424 | * Remote IRR was clear before reprogramming the |
| 2425 | * ioapic I don't trust the Remote IRR bit to be |
| 2426 | * completey accurate. |
| 2427 | * |
| 2428 | * However there appears to be no other way to plug |
| 2429 | * this race, so if the Remote IRR bit is not |
| 2430 | * accurate and is causing problems then it is a hardware bug |
| 2431 | * and you can go talk to the chipset vendor about it. |
| 2432 | */ |
| 2433 | if (!io_apic_level_ack_pending(cfg)) |
| 2434 | irq_move_masked_irq(data); |
| 2435 | unmask_ioapic(cfg); |
| 2436 | } |
| 2437 | } |
| 2438 | #else |
| 2439 | static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg) |
| 2440 | { |
| 2441 | return false; |
| 2442 | } |
| 2443 | static inline void ioapic_irqd_unmask(struct irq_data *data, |
| 2444 | struct irq_cfg *cfg, bool masked) |
| 2445 | { |
| 2446 | } |
| 2447 | #endif |
| 2448 | |
Thomas Gleixner | 90297c5 | 2010-09-28 16:03:54 +0200 | [diff] [blame] | 2449 | static void ack_apic_level(struct irq_data *data) |
Yinghai Lu | 047c8fd | 2008-08-19 20:50:41 -0700 | [diff] [blame] | 2450 | { |
Thomas Gleixner | 90297c5 | 2010-09-28 16:03:54 +0200 | [diff] [blame] | 2451 | struct irq_cfg *cfg = data->chip_data; |
Alexander Gordeev | 4da7072 | 2012-03-20 15:19:36 +0100 | [diff] [blame] | 2452 | int i, irq = data->irq; |
Yinghai Lu | 3eb2cce | 2008-08-19 20:50:48 -0700 | [diff] [blame] | 2453 | unsigned long v; |
Alexander Gordeev | 4da7072 | 2012-03-20 15:19:36 +0100 | [diff] [blame] | 2454 | bool masked; |
Yinghai Lu | 047c8fd | 2008-08-19 20:50:41 -0700 | [diff] [blame] | 2455 | |
Thomas Gleixner | dd5f15e | 2010-09-28 15:18:35 +0200 | [diff] [blame] | 2456 | irq_complete_move(cfg); |
Alexander Gordeev | 4da7072 | 2012-03-20 15:19:36 +0100 | [diff] [blame] | 2457 | masked = ioapic_irqd_mask(data, cfg); |
Yinghai Lu | 047c8fd | 2008-08-19 20:50:41 -0700 | [diff] [blame] | 2458 | |
Yinghai Lu | 3eb2cce | 2008-08-19 20:50:48 -0700 | [diff] [blame] | 2459 | /* |
Jeremy Fitzhardinge | 916a0fe | 2009-06-08 03:00:22 -0700 | [diff] [blame] | 2460 | * It appears there is an erratum which affects at least version 0x11 |
| 2461 | * of I/O APIC (that's the 82093AA and cores integrated into various |
| 2462 | * chipsets). Under certain conditions a level-triggered interrupt is |
| 2463 | * erroneously delivered as edge-triggered one but the respective IRR |
| 2464 | * bit gets set nevertheless. As a result the I/O unit expects an EOI |
| 2465 | * message but it will never arrive and further interrupts are blocked |
| 2466 | * from the source. The exact reason is so far unknown, but the |
| 2467 | * phenomenon was observed when two consecutive interrupt requests |
| 2468 | * from a given source get delivered to the same CPU and the source is |
| 2469 | * temporarily disabled in between. |
| 2470 | * |
| 2471 | * A workaround is to simulate an EOI message manually. We achieve it |
| 2472 | * by setting the trigger mode to edge and then to level when the edge |
| 2473 | * trigger mode gets detected in the TMR of a local APIC for a |
| 2474 | * level-triggered interrupt. We mask the source for the time of the |
| 2475 | * operation to prevent an edge-triggered interrupt escaping meanwhile. |
| 2476 | * The idea is from Manfred Spraul. --macro |
Suresh Siddha | 1c83995 | 2009-12-01 15:31:17 -0800 | [diff] [blame] | 2477 | * |
| 2478 | * Also in the case when cpu goes offline, fixup_irqs() will forward |
| 2479 | * any unhandled interrupt on the offlined cpu to the new cpu |
| 2480 | * destination that is handling the corresponding interrupt. This |
| 2481 | * interrupt forwarding is done via IPI's. Hence, in this case also |
| 2482 | * level-triggered io-apic interrupt will be seen as an edge |
| 2483 | * interrupt in the IRR. And we can't rely on the cpu's EOI |
| 2484 | * to be broadcasted to the IO-APIC's which will clear the remoteIRR |
| 2485 | * corresponding to the level-triggered interrupt. Hence on IO-APIC's |
| 2486 | * supporting EOI register, we do an explicit EOI to clear the |
| 2487 | * remote IRR and on IO-APIC's which don't have an EOI register, |
| 2488 | * we use the above logic (mask+edge followed by unmask+level) from |
| 2489 | * Manfred Spraul to clear the remote IRR. |
Jeremy Fitzhardinge | 916a0fe | 2009-06-08 03:00:22 -0700 | [diff] [blame] | 2490 | */ |
Yinghai Lu | 3145e94 | 2008-12-05 18:58:34 -0800 | [diff] [blame] | 2491 | i = cfg->vector; |
Yinghai Lu | 3eb2cce | 2008-08-19 20:50:48 -0700 | [diff] [blame] | 2492 | v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); |
Yinghai Lu | 3eb2cce | 2008-08-19 20:50:48 -0700 | [diff] [blame] | 2493 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2494 | /* |
| 2495 | * We must acknowledge the irq before we move it or the acknowledge will |
| 2496 | * not propagate properly. |
| 2497 | */ |
| 2498 | ack_APIC_irq(); |
Yinghai Lu | 047c8fd | 2008-08-19 20:50:41 -0700 | [diff] [blame] | 2499 | |
Suresh Siddha | 1c83995 | 2009-12-01 15:31:17 -0800 | [diff] [blame] | 2500 | /* |
| 2501 | * Tail end of clearing remote IRR bit (either by delivering the EOI |
| 2502 | * message via io-apic EOI register write or simulating it using |
| 2503 | * mask+edge followed by unnask+level logic) manually when the |
| 2504 | * level triggered interrupt is seen as the edge triggered interrupt |
| 2505 | * at the cpu. |
| 2506 | */ |
Maciej W. Rozycki | ca64c47 | 2009-12-01 15:31:15 -0800 | [diff] [blame] | 2507 | if (!(v & (1 << (i & 0x1f)))) { |
| 2508 | atomic_inc(&irq_mis_count); |
| 2509 | |
Thomas Gleixner | dd5f15e | 2010-09-28 15:18:35 +0200 | [diff] [blame] | 2510 | eoi_ioapic_irq(irq, cfg); |
Maciej W. Rozycki | ca64c47 | 2009-12-01 15:31:15 -0800 | [diff] [blame] | 2511 | } |
| 2512 | |
Alexander Gordeev | 4da7072 | 2012-03-20 15:19:36 +0100 | [diff] [blame] | 2513 | ioapic_irqd_unmask(data, cfg, masked); |
Yinghai Lu | 3eb2cce | 2008-08-19 20:50:48 -0700 | [diff] [blame] | 2514 | } |
Yinghai Lu | 1d02519 | 2008-08-19 20:50:34 -0700 | [diff] [blame] | 2515 | |
Ingo Molnar | f5b9ed7 | 2006-10-04 02:16:26 -0700 | [diff] [blame] | 2516 | static struct irq_chip ioapic_chip __read_mostly = { |
Thomas Gleixner | f7e909e | 2010-10-08 21:40:23 +0200 | [diff] [blame] | 2517 | .name = "IO-APIC", |
| 2518 | .irq_startup = startup_ioapic_irq, |
| 2519 | .irq_mask = mask_ioapic_irq, |
| 2520 | .irq_unmask = unmask_ioapic_irq, |
| 2521 | .irq_ack = ack_apic_edge, |
| 2522 | .irq_eoi = ack_apic_level, |
Joerg Roedel | 373dd7a | 2012-09-26 12:44:39 +0200 | [diff] [blame] | 2523 | .irq_set_affinity = native_ioapic_set_affinity, |
Thomas Gleixner | f7e909e | 2010-10-08 21:40:23 +0200 | [diff] [blame] | 2524 | .irq_retrigger = ioapic_retrigger_irq, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2525 | }; |
| 2526 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2527 | static inline void init_IO_APIC_traps(void) |
| 2528 | { |
Yinghai Lu | da51a82 | 2008-08-19 20:50:25 -0700 | [diff] [blame] | 2529 | struct irq_cfg *cfg; |
Thomas Gleixner | ad9f433 | 2010-09-30 11:26:43 +0200 | [diff] [blame] | 2530 | unsigned int irq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2531 | |
| 2532 | /* |
| 2533 | * NOTE! The local APIC isn't very good at handling |
| 2534 | * multiple interrupts at the same interrupt level. |
| 2535 | * As the interrupt level is determined by taking the |
| 2536 | * vector number and shifting that right by 4, we |
| 2537 | * want to spread these out a bit so that they don't |
| 2538 | * all fall in the same interrupt level. |
| 2539 | * |
| 2540 | * Also, we've got to be careful not to trash gate |
| 2541 | * 0x80, because int 0x80 is hm, kind of importantish. ;) |
| 2542 | */ |
Thomas Gleixner | ad9f433 | 2010-09-30 11:26:43 +0200 | [diff] [blame] | 2543 | for_each_active_irq(irq) { |
Thomas Gleixner | 2c77865 | 2011-03-12 12:20:43 +0100 | [diff] [blame] | 2544 | cfg = irq_get_chip_data(irq); |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 2545 | if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2546 | /* |
| 2547 | * Hmm.. We don't have an entry for this, |
| 2548 | * so default to an old-fashioned 8259 |
| 2549 | * interrupt if we can.. |
| 2550 | */ |
Jacob Pan | b81bb37 | 2009-11-09 11:27:04 -0800 | [diff] [blame] | 2551 | if (irq < legacy_pic->nr_legacy_irqs) |
| 2552 | legacy_pic->make_irq(irq); |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 2553 | else |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2554 | /* Strange. Oh, well.. */ |
Thomas Gleixner | 2c77865 | 2011-03-12 12:20:43 +0100 | [diff] [blame] | 2555 | irq_set_chip(irq, &no_irq_chip); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2556 | } |
| 2557 | } |
| 2558 | } |
| 2559 | |
Ingo Molnar | f5b9ed7 | 2006-10-04 02:16:26 -0700 | [diff] [blame] | 2560 | /* |
| 2561 | * The local APIC irq-chip implementation: |
| 2562 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2563 | |
Thomas Gleixner | 90297c5 | 2010-09-28 16:03:54 +0200 | [diff] [blame] | 2564 | static void mask_lapic_irq(struct irq_data *data) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2565 | { |
| 2566 | unsigned long v; |
| 2567 | |
| 2568 | v = apic_read(APIC_LVT0); |
Maciej W. Rozycki | 593f4a7 | 2008-07-16 19:15:30 +0100 | [diff] [blame] | 2569 | apic_write(APIC_LVT0, v | APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2570 | } |
| 2571 | |
Thomas Gleixner | 90297c5 | 2010-09-28 16:03:54 +0200 | [diff] [blame] | 2572 | static void unmask_lapic_irq(struct irq_data *data) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2573 | { |
Ingo Molnar | f5b9ed7 | 2006-10-04 02:16:26 -0700 | [diff] [blame] | 2574 | unsigned long v; |
| 2575 | |
| 2576 | v = apic_read(APIC_LVT0); |
Maciej W. Rozycki | 593f4a7 | 2008-07-16 19:15:30 +0100 | [diff] [blame] | 2577 | apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2578 | } |
| 2579 | |
Thomas Gleixner | 90297c5 | 2010-09-28 16:03:54 +0200 | [diff] [blame] | 2580 | static void ack_lapic_irq(struct irq_data *data) |
Yinghai Lu | 1d02519 | 2008-08-19 20:50:34 -0700 | [diff] [blame] | 2581 | { |
| 2582 | ack_APIC_irq(); |
| 2583 | } |
| 2584 | |
Ingo Molnar | f5b9ed7 | 2006-10-04 02:16:26 -0700 | [diff] [blame] | 2585 | static struct irq_chip lapic_chip __read_mostly = { |
Maciej W. Rozycki | 9a1c619 | 2008-05-27 21:19:09 +0100 | [diff] [blame] | 2586 | .name = "local-APIC", |
Thomas Gleixner | 90297c5 | 2010-09-28 16:03:54 +0200 | [diff] [blame] | 2587 | .irq_mask = mask_lapic_irq, |
| 2588 | .irq_unmask = unmask_lapic_irq, |
| 2589 | .irq_ack = ack_lapic_irq, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2590 | }; |
| 2591 | |
Thomas Gleixner | 60c6994 | 2010-09-28 17:28:38 +0200 | [diff] [blame] | 2592 | static void lapic_register_intr(int irq) |
Maciej W. Rozycki | c88ac1d | 2008-07-11 19:35:17 +0100 | [diff] [blame] | 2593 | { |
Thomas Gleixner | 60c6994 | 2010-09-28 17:28:38 +0200 | [diff] [blame] | 2594 | irq_clear_status_flags(irq, IRQ_LEVEL); |
Thomas Gleixner | 2c77865 | 2011-03-12 12:20:43 +0100 | [diff] [blame] | 2595 | irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, |
Maciej W. Rozycki | c88ac1d | 2008-07-11 19:35:17 +0100 | [diff] [blame] | 2596 | "edge"); |
Maciej W. Rozycki | c88ac1d | 2008-07-11 19:35:17 +0100 | [diff] [blame] | 2597 | } |
| 2598 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2599 | /* |
| 2600 | * This looks a bit hackish but it's about the only one way of sending |
| 2601 | * a few INTA cycles to 8259As and any associated glue logic. ICR does |
| 2602 | * not support the ExtINT mode, unfortunately. We need to send these |
| 2603 | * cycles as some i82489DX-based boards have glue logic that keeps the |
| 2604 | * 8259A interrupt line asserted until INTA. --macro |
| 2605 | */ |
Jacek Luczak | 28acf28 | 2008-04-12 17:41:12 +0200 | [diff] [blame] | 2606 | static inline void __init unlock_ExtINT_logic(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2607 | { |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 2608 | int apic, pin, i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2609 | struct IO_APIC_route_entry entry0, entry1; |
| 2610 | unsigned char save_control, save_freq_select; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2611 | |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 2612 | pin = find_isa_irq_pin(8, mp_INT); |
Adrian Bunk | 956fb53 | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2613 | if (pin == -1) { |
| 2614 | WARN_ON_ONCE(1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2615 | return; |
Adrian Bunk | 956fb53 | 2006-12-07 02:14:11 +0100 | [diff] [blame] | 2616 | } |
| 2617 | apic = find_isa_irq_apic(8, mp_INT); |
| 2618 | if (apic == -1) { |
| 2619 | WARN_ON_ONCE(1); |
| 2620 | return; |
| 2621 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2622 | |
Andi Kleen | cf4c6a2 | 2006-09-26 10:52:30 +0200 | [diff] [blame] | 2623 | entry0 = ioapic_read_entry(apic, pin); |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 2624 | clear_IO_APIC_pin(apic, pin); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2625 | |
| 2626 | memset(&entry1, 0, sizeof(entry1)); |
| 2627 | |
| 2628 | entry1.dest_mode = 0; /* physical delivery */ |
| 2629 | entry1.mask = 0; /* unmask IRQ now */ |
Yinghai Lu | d83e94a | 2008-08-19 20:50:33 -0700 | [diff] [blame] | 2630 | entry1.dest = hard_smp_processor_id(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2631 | entry1.delivery_mode = dest_ExtINT; |
| 2632 | entry1.polarity = entry0.polarity; |
| 2633 | entry1.trigger = 0; |
| 2634 | entry1.vector = 0; |
| 2635 | |
Andi Kleen | cf4c6a2 | 2006-09-26 10:52:30 +0200 | [diff] [blame] | 2636 | ioapic_write_entry(apic, pin, entry1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2637 | |
| 2638 | save_control = CMOS_READ(RTC_CONTROL); |
| 2639 | save_freq_select = CMOS_READ(RTC_FREQ_SELECT); |
| 2640 | CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, |
| 2641 | RTC_FREQ_SELECT); |
| 2642 | CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); |
| 2643 | |
| 2644 | i = 100; |
| 2645 | while (i-- > 0) { |
| 2646 | mdelay(10); |
| 2647 | if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) |
| 2648 | i -= 10; |
| 2649 | } |
| 2650 | |
| 2651 | CMOS_WRITE(save_control, RTC_CONTROL); |
| 2652 | CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 2653 | clear_IO_APIC_pin(apic, pin); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2654 | |
Andi Kleen | cf4c6a2 | 2006-09-26 10:52:30 +0200 | [diff] [blame] | 2655 | ioapic_write_entry(apic, pin, entry0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2656 | } |
| 2657 | |
Yinghai Lu | efa2559 | 2008-08-19 20:50:36 -0700 | [diff] [blame] | 2658 | static int disable_timer_pin_1 __initdata; |
Yinghai Lu | 047c8fd | 2008-08-19 20:50:41 -0700 | [diff] [blame] | 2659 | /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2660 | static int __init disable_timer_pin_setup(char *arg) |
Yinghai Lu | efa2559 | 2008-08-19 20:50:36 -0700 | [diff] [blame] | 2661 | { |
| 2662 | disable_timer_pin_1 = 1; |
| 2663 | return 0; |
| 2664 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2665 | early_param("disable_timer_pin_1", disable_timer_pin_setup); |
Yinghai Lu | efa2559 | 2008-08-19 20:50:36 -0700 | [diff] [blame] | 2666 | |
| 2667 | int timer_through_8259 __initdata; |
| 2668 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2669 | /* |
| 2670 | * This code may look a bit paranoid, but it's supposed to cooperate with |
| 2671 | * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ |
| 2672 | * is so screwy. Thanks to Brian Perkins for testing/hacking this beast |
| 2673 | * fanatically on his truly buggy board. |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2674 | * |
| 2675 | * FIXME: really need to revamp this for all platforms. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2676 | */ |
Zachary Amsden | 8542b20 | 2006-12-07 02:14:09 +0100 | [diff] [blame] | 2677 | static inline void __init check_timer(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2678 | { |
Thomas Gleixner | 2c77865 | 2011-03-12 12:20:43 +0100 | [diff] [blame] | 2679 | struct irq_cfg *cfg = irq_get_chip_data(0); |
Robert Richter | f6e9456c | 2010-07-21 19:03:58 +0200 | [diff] [blame] | 2680 | int node = cpu_to_node(0); |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 2681 | int apic1, pin1, apic2, pin2; |
Ingo Molnar | 4aae070 | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 2682 | unsigned long flags; |
Yinghai Lu | 047c8fd | 2008-08-19 20:50:41 -0700 | [diff] [blame] | 2683 | int no_pin1 = 0; |
Ingo Molnar | 4aae070 | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 2684 | |
| 2685 | local_irq_save(flags); |
Maciej W. Rozycki | d4d25de | 2007-11-26 20:42:19 +0100 | [diff] [blame] | 2686 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2687 | /* |
| 2688 | * get/set the timer IRQ vector: |
| 2689 | */ |
Thomas Gleixner | 4305df9 | 2010-09-28 15:01:33 +0200 | [diff] [blame] | 2690 | legacy_pic->mask(0); |
Ingo Molnar | fe402e1 | 2009-01-28 04:32:51 +0100 | [diff] [blame] | 2691 | assign_irq_vector(0, cfg, apic->target_cpus()); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2692 | |
| 2693 | /* |
Maciej W. Rozycki | d11d579 | 2008-05-21 22:09:11 +0100 | [diff] [blame] | 2694 | * As IRQ0 is to be enabled in the 8259A, the virtual |
| 2695 | * wire has to be disabled in the local APIC. Also |
| 2696 | * timer interrupts need to be acknowledged manually in |
| 2697 | * the 8259A for the i82489DX when using the NMI |
| 2698 | * watchdog as that APIC treats NMIs as level-triggered. |
| 2699 | * The AEOI mode will finish them in the 8259A |
| 2700 | * automatically. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2701 | */ |
Maciej W. Rozycki | 593f4a7 | 2008-07-16 19:15:30 +0100 | [diff] [blame] | 2702 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); |
Jacob Pan | b81bb37 | 2009-11-09 11:27:04 -0800 | [diff] [blame] | 2703 | legacy_pic->init(1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2704 | |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 2705 | pin1 = find_isa_irq_pin(0, mp_INT); |
| 2706 | apic1 = find_isa_irq_apic(0, mp_INT); |
| 2707 | pin2 = ioapic_i8259.pin; |
| 2708 | apic2 = ioapic_i8259.apic; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2709 | |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2710 | apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " |
| 2711 | "apic1=%d pin1=%d apic2=%d pin2=%d\n", |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2712 | cfg->vector, apic1, pin1, apic2, pin2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2713 | |
Maciej W. Rozycki | 691874f | 2008-05-27 21:19:51 +0100 | [diff] [blame] | 2714 | /* |
| 2715 | * Some BIOS writers are clueless and report the ExtINTA |
| 2716 | * I/O APIC input from the cascaded 8259A as the timer |
| 2717 | * interrupt input. So just in case, if only one pin |
| 2718 | * was found above, try it both directly and through the |
| 2719 | * 8259A. |
| 2720 | */ |
| 2721 | if (pin1 == -1) { |
Joerg Roedel | 6a9f5de | 2012-09-26 12:44:41 +0200 | [diff] [blame] | 2722 | panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC"); |
Maciej W. Rozycki | 691874f | 2008-05-27 21:19:51 +0100 | [diff] [blame] | 2723 | pin1 = pin2; |
| 2724 | apic1 = apic2; |
| 2725 | no_pin1 = 1; |
| 2726 | } else if (pin2 == -1) { |
| 2727 | pin2 = pin1; |
| 2728 | apic2 = apic1; |
| 2729 | } |
| 2730 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2731 | if (pin1 != -1) { |
| 2732 | /* |
| 2733 | * Ok, does IRQ0 through the IOAPIC work? |
| 2734 | */ |
Maciej W. Rozycki | 691874f | 2008-05-27 21:19:51 +0100 | [diff] [blame] | 2735 | if (no_pin1) { |
Yinghai Lu | 85ac16d | 2009-04-27 18:00:38 -0700 | [diff] [blame] | 2736 | add_pin_to_irq_node(cfg, node, apic1, pin1); |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2737 | setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); |
Yinghai Lu | f72dcca | 2009-02-08 16:18:03 -0800 | [diff] [blame] | 2738 | } else { |
Thomas Gleixner | 60c6994 | 2010-09-28 17:28:38 +0200 | [diff] [blame] | 2739 | /* for edge trigger, setup_ioapic_irq already |
Yinghai Lu | f72dcca | 2009-02-08 16:18:03 -0800 | [diff] [blame] | 2740 | * leave it unmasked. |
| 2741 | * so only need to unmask if it is level-trigger |
| 2742 | * do we really have level trigger timer? |
| 2743 | */ |
| 2744 | int idx; |
| 2745 | idx = find_irq_entry(apic1, pin1, mp_INT); |
| 2746 | if (idx != -1 && irq_trigger(idx)) |
Thomas Gleixner | dd5f15e | 2010-09-28 15:18:35 +0200 | [diff] [blame] | 2747 | unmask_ioapic(cfg); |
Maciej W. Rozycki | 691874f | 2008-05-27 21:19:51 +0100 | [diff] [blame] | 2748 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2749 | if (timer_irq_works()) { |
Chuck Ebbert | 66759a0 | 2005-09-12 18:49:25 +0200 | [diff] [blame] | 2750 | if (disable_timer_pin_1 > 0) |
| 2751 | clear_IO_APIC_pin(0, pin1); |
Ingo Molnar | 4aae070 | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 2752 | goto out; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2753 | } |
Joerg Roedel | 6a9f5de | 2012-09-26 12:44:41 +0200 | [diff] [blame] | 2754 | panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC"); |
Yinghai Lu | f72dcca | 2009-02-08 16:18:03 -0800 | [diff] [blame] | 2755 | local_irq_disable(); |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 2756 | clear_IO_APIC_pin(apic1, pin1); |
Maciej W. Rozycki | 691874f | 2008-05-27 21:19:51 +0100 | [diff] [blame] | 2757 | if (!no_pin1) |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2758 | apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " |
| 2759 | "8254 timer not connected to IO-APIC\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2760 | |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2761 | apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " |
| 2762 | "(IRQ0) through the 8259A ...\n"); |
| 2763 | apic_printk(APIC_QUIET, KERN_INFO |
| 2764 | "..... (found apic %d pin %d) ...\n", apic2, pin2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2765 | /* |
| 2766 | * legacy devices should be connected to IO APIC #0 |
| 2767 | */ |
Yinghai Lu | 85ac16d | 2009-04-27 18:00:38 -0700 | [diff] [blame] | 2768 | replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2769 | setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); |
Thomas Gleixner | 4305df9 | 2010-09-28 15:01:33 +0200 | [diff] [blame] | 2770 | legacy_pic->unmask(0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2771 | if (timer_irq_works()) { |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2772 | apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); |
Maciej W. Rozycki | 35542c5 | 2008-05-21 22:10:22 +0100 | [diff] [blame] | 2773 | timer_through_8259 = 1; |
Ingo Molnar | 4aae070 | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 2774 | goto out; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2775 | } |
| 2776 | /* |
| 2777 | * Cleanup, just in case ... |
| 2778 | */ |
Yinghai Lu | f72dcca | 2009-02-08 16:18:03 -0800 | [diff] [blame] | 2779 | local_irq_disable(); |
Thomas Gleixner | 4305df9 | 2010-09-28 15:01:33 +0200 | [diff] [blame] | 2780 | legacy_pic->mask(0); |
Eric W. Biederman | fcfd636 | 2005-10-30 14:59:39 -0800 | [diff] [blame] | 2781 | clear_IO_APIC_pin(apic2, pin2); |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2782 | apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2783 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2784 | |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2785 | apic_printk(APIC_QUIET, KERN_INFO |
| 2786 | "...trying to set up timer as Virtual Wire IRQ...\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2787 | |
Thomas Gleixner | 60c6994 | 2010-09-28 17:28:38 +0200 | [diff] [blame] | 2788 | lapic_register_intr(0); |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2789 | apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ |
Thomas Gleixner | 4305df9 | 2010-09-28 15:01:33 +0200 | [diff] [blame] | 2790 | legacy_pic->unmask(0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2791 | |
| 2792 | if (timer_irq_works()) { |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2793 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
Ingo Molnar | 4aae070 | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 2794 | goto out; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2795 | } |
Yinghai Lu | f72dcca | 2009-02-08 16:18:03 -0800 | [diff] [blame] | 2796 | local_irq_disable(); |
Thomas Gleixner | 4305df9 | 2010-09-28 15:01:33 +0200 | [diff] [blame] | 2797 | legacy_pic->mask(0); |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 2798 | apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2799 | apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2800 | |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2801 | apic_printk(APIC_QUIET, KERN_INFO |
| 2802 | "...trying to set up timer as ExtINT IRQ...\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2803 | |
Jacob Pan | b81bb37 | 2009-11-09 11:27:04 -0800 | [diff] [blame] | 2804 | legacy_pic->init(0); |
| 2805 | legacy_pic->make_irq(0); |
Maciej W. Rozycki | 593f4a7 | 2008-07-16 19:15:30 +0100 | [diff] [blame] | 2806 | apic_write(APIC_LVT0, APIC_DM_EXTINT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2807 | |
| 2808 | unlock_ExtINT_logic(); |
| 2809 | |
| 2810 | if (timer_irq_works()) { |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2811 | apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); |
Ingo Molnar | 4aae070 | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 2812 | goto out; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2813 | } |
Yinghai Lu | f72dcca | 2009-02-08 16:18:03 -0800 | [diff] [blame] | 2814 | local_irq_disable(); |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2815 | apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); |
Yinghai Lu | fb209bd | 2011-12-21 17:45:17 -0800 | [diff] [blame] | 2816 | if (x2apic_preenabled) |
| 2817 | apic_printk(APIC_QUIET, KERN_INFO |
| 2818 | "Perhaps problem with the pre-enabled x2apic mode\n" |
| 2819 | "Try booting with x2apic and interrupt-remapping disabled in the bios.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2820 | panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " |
Maciej W. Rozycki | 49a66a0b | 2008-07-14 19:08:13 +0100 | [diff] [blame] | 2821 | "report. Then try booting with the 'noapic' option.\n"); |
Ingo Molnar | 4aae070 | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 2822 | out: |
| 2823 | local_irq_restore(flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2824 | } |
| 2825 | |
| 2826 | /* |
Maciej W. Rozycki | af17478 | 2008-07-11 19:35:23 +0100 | [diff] [blame] | 2827 | * Traditionally ISA IRQ2 is the cascade IRQ, and is not available |
| 2828 | * to devices. However there may be an I/O APIC pin available for |
| 2829 | * this interrupt regardless. The pin may be left unconnected, but |
| 2830 | * typically it will be reused as an ExtINT cascade interrupt for |
| 2831 | * the master 8259A. In the MPS case such a pin will normally be |
| 2832 | * reported as an ExtINT interrupt in the MP table. With ACPI |
| 2833 | * there is no provision for ExtINT interrupts, and in the absence |
| 2834 | * of an override it would be treated as an ordinary ISA I/O APIC |
| 2835 | * interrupt, that is edge-triggered and unmasked by default. We |
| 2836 | * used to do this, but it caused problems on some systems because |
| 2837 | * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using |
| 2838 | * the same ExtINT cascade interrupt to drive the local APIC of the |
| 2839 | * bootstrap processor. Therefore we refrain from routing IRQ2 to |
| 2840 | * the I/O APIC in all cases now. No actual device should request |
| 2841 | * it anyway. --macro |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2842 | */ |
Thomas Gleixner | bc07844 | 2009-08-29 18:09:57 +0200 | [diff] [blame] | 2843 | #define PIC_IRQS (1UL << PIC_CASCADE_IR) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2844 | |
| 2845 | void __init setup_IO_APIC(void) |
| 2846 | { |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2847 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2848 | /* |
| 2849 | * calling enable_IO_APIC() is moved to setup_local_APIC for BP |
| 2850 | */ |
Jacob Pan | b81bb37 | 2009-11-09 11:27:04 -0800 | [diff] [blame] | 2851 | io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2852 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2853 | apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 2854 | /* |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2855 | * Set up IO-APIC IRQ routing. |
| 2856 | */ |
Thomas Gleixner | de93410 | 2009-08-20 09:27:29 +0200 | [diff] [blame] | 2857 | x86_init.mpparse.setup_ioapic_ids(); |
| 2858 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2859 | sync_Arb_IDs(); |
| 2860 | setup_IO_APIC_irqs(); |
| 2861 | init_IO_APIC_traps(); |
Jacob Pan | b81bb37 | 2009-11-09 11:27:04 -0800 | [diff] [blame] | 2862 | if (legacy_pic->nr_legacy_irqs) |
Thomas Gleixner | bc07844 | 2009-08-29 18:09:57 +0200 | [diff] [blame] | 2863 | check_timer(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2864 | } |
| 2865 | |
| 2866 | /* |
Lucas De Marchi | 0d2eb44 | 2011-03-17 16:24:16 -0300 | [diff] [blame] | 2867 | * Called after all the initialization is done. If we didn't find any |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2868 | * APIC bugs then we can allow the modify fast path |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2869 | */ |
Paolo Ciarrocchi | 3606244 | 2008-06-08 13:07:18 +0200 | [diff] [blame] | 2870 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2871 | static int __init io_apic_bug_finalize(void) |
| 2872 | { |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 2873 | if (sis_apic_bug == -1) |
| 2874 | sis_apic_bug = 0; |
| 2875 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2876 | } |
| 2877 | |
| 2878 | late_initcall(io_apic_bug_finalize); |
| 2879 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 2880 | static void resume_ioapic_id(int ioapic_idx) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2881 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2882 | unsigned long flags; |
| 2883 | union IO_APIC_reg_00 reg_00; |
Paolo Ciarrocchi | 3606244 | 2008-06-08 13:07:18 +0200 | [diff] [blame] | 2884 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 2885 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 2886 | reg_00.raw = io_apic_read(ioapic_idx, 0); |
| 2887 | if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) { |
| 2888 | reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); |
| 2889 | io_apic_write(ioapic_idx, 0, reg_00.raw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2890 | } |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 2891 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2892 | } |
| 2893 | |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2894 | static void ioapic_resume(void) |
| 2895 | { |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 2896 | int ioapic_idx; |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2897 | |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 2898 | for (ioapic_idx = nr_ioapics - 1; ioapic_idx >= 0; ioapic_idx--) |
| 2899 | resume_ioapic_id(ioapic_idx); |
Suresh Siddha | 15bac20 | 2011-05-18 16:31:34 -0700 | [diff] [blame] | 2900 | |
| 2901 | restore_ioapic_entries(); |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2902 | } |
| 2903 | |
| 2904 | static struct syscore_ops ioapic_syscore_ops = { |
Suresh Siddha | 15bac20 | 2011-05-18 16:31:34 -0700 | [diff] [blame] | 2905 | .suspend = save_ioapic_entries, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2906 | .resume = ioapic_resume, |
| 2907 | }; |
| 2908 | |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2909 | static int __init ioapic_init_ops(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2910 | { |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2911 | register_syscore_ops(&ioapic_syscore_ops); |
| 2912 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2913 | return 0; |
| 2914 | } |
| 2915 | |
Rafael J. Wysocki | f3c6ea1 | 2011-03-23 22:15:54 +0100 | [diff] [blame] | 2916 | device_initcall(ioapic_init_ops); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2917 | |
Eric W. Biederman | 3fc471e | 2006-10-04 02:16:39 -0700 | [diff] [blame] | 2918 | /* |
Eric W. Biederman | 95d7788 | 2006-10-04 02:17:01 -0700 | [diff] [blame] | 2919 | * Dynamic irq allocate and deallocation |
Eric W. Biederman | 3fc471e | 2006-10-04 02:16:39 -0700 | [diff] [blame] | 2920 | */ |
Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 2921 | unsigned int __create_irqs(unsigned int from, unsigned int count, int node) |
Eric W. Biederman | 3fc471e | 2006-10-04 02:16:39 -0700 | [diff] [blame] | 2922 | { |
Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 2923 | struct irq_cfg **cfg; |
Eric W. Biederman | 3fc471e | 2006-10-04 02:16:39 -0700 | [diff] [blame] | 2924 | unsigned long flags; |
Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 2925 | int irq, i; |
Yinghai Lu | 199751d | 2008-08-19 20:50:27 -0700 | [diff] [blame] | 2926 | |
Thomas Gleixner | fbc6bff | 2010-09-28 20:34:53 +0200 | [diff] [blame] | 2927 | if (from < nr_irqs_gsi) |
| 2928 | from = nr_irqs_gsi; |
| 2929 | |
Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 2930 | cfg = kzalloc_node(count * sizeof(cfg[0]), GFP_KERNEL, node); |
| 2931 | if (!cfg) |
| 2932 | return 0; |
| 2933 | |
| 2934 | irq = alloc_irqs_from(from, count, node); |
Thomas Gleixner | fbc6bff | 2010-09-28 20:34:53 +0200 | [diff] [blame] | 2935 | if (irq < 0) |
Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 2936 | goto out_cfgs; |
| 2937 | |
| 2938 | for (i = 0; i < count; i++) { |
| 2939 | cfg[i] = alloc_irq_cfg(irq + i, node); |
| 2940 | if (!cfg[i]) |
| 2941 | goto out_irqs; |
Thomas Gleixner | fbc6bff | 2010-09-28 20:34:53 +0200 | [diff] [blame] | 2942 | } |
Yinghai Lu | abcaa2b | 2009-02-08 16:18:03 -0800 | [diff] [blame] | 2943 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 2944 | raw_spin_lock_irqsave(&vector_lock, flags); |
Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 2945 | for (i = 0; i < count; i++) |
| 2946 | if (__assign_irq_vector(irq + i, cfg[i], apic->target_cpus())) |
| 2947 | goto out_vecs; |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 2948 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
Eric W. Biederman | 3fc471e | 2006-10-04 02:16:39 -0700 | [diff] [blame] | 2949 | |
Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 2950 | for (i = 0; i < count; i++) { |
| 2951 | irq_set_chip_data(irq + i, cfg[i]); |
| 2952 | irq_clear_status_flags(irq + i, IRQ_NOREQUEST); |
Thomas Gleixner | fbc6bff | 2010-09-28 20:34:53 +0200 | [diff] [blame] | 2953 | } |
Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 2954 | |
| 2955 | kfree(cfg); |
| 2956 | return irq; |
| 2957 | |
| 2958 | out_vecs: |
| 2959 | for (i--; i >= 0; i--) |
| 2960 | __clear_irq_vector(irq + i, cfg[i]); |
| 2961 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
| 2962 | out_irqs: |
| 2963 | for (i = 0; i < count; i++) |
| 2964 | free_irq_at(irq + i, cfg[i]); |
| 2965 | out_cfgs: |
| 2966 | kfree(cfg); |
| 2967 | return 0; |
| 2968 | } |
| 2969 | |
| 2970 | unsigned int create_irq_nr(unsigned int from, int node) |
| 2971 | { |
| 2972 | return __create_irqs(from, 1, node); |
Eric W. Biederman | 3fc471e | 2006-10-04 02:16:39 -0700 | [diff] [blame] | 2973 | } |
| 2974 | |
Yinghai Lu | 199751d | 2008-08-19 20:50:27 -0700 | [diff] [blame] | 2975 | int create_irq(void) |
| 2976 | { |
Robert Richter | f6e9456c | 2010-07-21 19:03:58 +0200 | [diff] [blame] | 2977 | int node = cpu_to_node(0); |
Yinghai Lu | be5d535 | 2008-12-05 18:58:33 -0800 | [diff] [blame] | 2978 | unsigned int irq_want; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2979 | int irq; |
| 2980 | |
Yinghai Lu | be5d535 | 2008-12-05 18:58:33 -0800 | [diff] [blame] | 2981 | irq_want = nr_irqs_gsi; |
Yinghai Lu | d047f53a | 2009-04-27 18:02:23 -0700 | [diff] [blame] | 2982 | irq = create_irq_nr(irq_want, node); |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 2983 | |
| 2984 | if (irq == 0) |
| 2985 | irq = -1; |
| 2986 | |
| 2987 | return irq; |
Yinghai Lu | 199751d | 2008-08-19 20:50:27 -0700 | [diff] [blame] | 2988 | } |
| 2989 | |
Eric W. Biederman | 3fc471e | 2006-10-04 02:16:39 -0700 | [diff] [blame] | 2990 | void destroy_irq(unsigned int irq) |
| 2991 | { |
Thomas Gleixner | 2c77865 | 2011-03-12 12:20:43 +0100 | [diff] [blame] | 2992 | struct irq_cfg *cfg = irq_get_chip_data(irq); |
Eric W. Biederman | 3fc471e | 2006-10-04 02:16:39 -0700 | [diff] [blame] | 2993 | unsigned long flags; |
Eric W. Biederman | 3fc471e | 2006-10-04 02:16:39 -0700 | [diff] [blame] | 2994 | |
Thomas Gleixner | fbc6bff | 2010-09-28 20:34:53 +0200 | [diff] [blame] | 2995 | irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE); |
Eric W. Biederman | 3fc471e | 2006-10-04 02:16:39 -0700 | [diff] [blame] | 2996 | |
Joerg Roedel | 11b4a1c | 2012-09-26 12:44:47 +0200 | [diff] [blame] | 2997 | free_remapped_irq(irq); |
| 2998 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 2999 | raw_spin_lock_irqsave(&vector_lock, flags); |
Thomas Gleixner | fbc6bff | 2010-09-28 20:34:53 +0200 | [diff] [blame] | 3000 | __clear_irq_vector(irq, cfg); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 3001 | raw_spin_unlock_irqrestore(&vector_lock, flags); |
Thomas Gleixner | fbc6bff | 2010-09-28 20:34:53 +0200 | [diff] [blame] | 3002 | free_irq_at(irq, cfg); |
Eric W. Biederman | 3fc471e | 2006-10-04 02:16:39 -0700 | [diff] [blame] | 3003 | } |
Eric W. Biederman | 3fc471e | 2006-10-04 02:16:39 -0700 | [diff] [blame] | 3004 | |
Joerg Roedel | 5afba62 | 2012-09-26 12:44:38 +0200 | [diff] [blame] | 3005 | void destroy_irqs(unsigned int irq, unsigned int count) |
Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 3006 | { |
| 3007 | unsigned int i; |
| 3008 | |
| 3009 | for (i = 0; i < count; i++) |
| 3010 | destroy_irq(irq + i); |
| 3011 | } |
| 3012 | |
Eric W. Biederman | 2d3fcc1 | 2006-10-04 02:16:43 -0700 | [diff] [blame] | 3013 | /* |
Simon Arlott | 27b46d7 | 2007-10-20 01:13:56 +0200 | [diff] [blame] | 3014 | * MSI message composition |
Eric W. Biederman | 2d3fcc1 | 2006-10-04 02:16:43 -0700 | [diff] [blame] | 3015 | */ |
Joerg Roedel | 7601384 | 2012-09-26 12:44:49 +0200 | [diff] [blame] | 3016 | void native_compose_msi_msg(struct pci_dev *pdev, |
| 3017 | unsigned int irq, unsigned int dest, |
| 3018 | struct msi_msg *msg, u8 hpet_id) |
| 3019 | { |
| 3020 | struct irq_cfg *cfg = irq_cfg(irq); |
| 3021 | |
| 3022 | msg->address_hi = MSI_ADDR_BASE_HI; |
| 3023 | |
| 3024 | if (x2apic_enabled()) |
| 3025 | msg->address_hi |= MSI_ADDR_EXT_DEST_ID(dest); |
| 3026 | |
| 3027 | msg->address_lo = |
| 3028 | MSI_ADDR_BASE_LO | |
| 3029 | ((apic->irq_dest_mode == 0) ? |
| 3030 | MSI_ADDR_DEST_MODE_PHYSICAL: |
| 3031 | MSI_ADDR_DEST_MODE_LOGICAL) | |
| 3032 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
| 3033 | MSI_ADDR_REDIRECTION_CPU: |
| 3034 | MSI_ADDR_REDIRECTION_LOWPRI) | |
| 3035 | MSI_ADDR_DEST_ID(dest); |
| 3036 | |
| 3037 | msg->data = |
| 3038 | MSI_DATA_TRIGGER_EDGE | |
| 3039 | MSI_DATA_LEVEL_ASSERT | |
| 3040 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
| 3041 | MSI_DATA_DELIVERY_FIXED: |
| 3042 | MSI_DATA_DELIVERY_LOWPRI) | |
| 3043 | MSI_DATA_VECTOR(cfg->vector); |
| 3044 | } |
| 3045 | |
Eric W. Biederman | 2d3fcc1 | 2006-10-04 02:16:43 -0700 | [diff] [blame] | 3046 | #ifdef CONFIG_PCI_MSI |
Suresh Siddha | c8bc6f3 | 2009-08-04 12:07:09 -0700 | [diff] [blame] | 3047 | static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, |
| 3048 | struct msi_msg *msg, u8 hpet_id) |
Eric W. Biederman | 2d3fcc1 | 2006-10-04 02:16:43 -0700 | [diff] [blame] | 3049 | { |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 3050 | struct irq_cfg *cfg; |
| 3051 | int err; |
Eric W. Biederman | 2d3fcc1 | 2006-10-04 02:16:43 -0700 | [diff] [blame] | 3052 | unsigned dest; |
| 3053 | |
Jan Beulich | f118263 | 2009-01-14 12:27:35 +0000 | [diff] [blame] | 3054 | if (disable_apic) |
| 3055 | return -ENXIO; |
| 3056 | |
Yinghai Lu | 3145e94 | 2008-12-05 18:58:34 -0800 | [diff] [blame] | 3057 | cfg = irq_cfg(irq); |
Ingo Molnar | fe402e1 | 2009-01-28 04:32:51 +0100 | [diff] [blame] | 3058 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 3059 | if (err) |
| 3060 | return err; |
Eric W. Biederman | 2d3fcc1 | 2006-10-04 02:16:43 -0700 | [diff] [blame] | 3061 | |
Alexander Gordeev | ff16432 | 2012-06-07 15:15:59 +0200 | [diff] [blame] | 3062 | err = apic->cpu_mask_to_apicid_and(cfg->domain, |
| 3063 | apic->target_cpus(), &dest); |
| 3064 | if (err) |
| 3065 | return err; |
Eric W. Biederman | 2d3fcc1 | 2006-10-04 02:16:43 -0700 | [diff] [blame] | 3066 | |
Joerg Roedel | 7601384 | 2012-09-26 12:44:49 +0200 | [diff] [blame] | 3067 | x86_msi.compose_msi_msg(pdev, irq, dest, msg, hpet_id); |
Joerg Roedel | 5e2b930 | 2012-03-30 11:47:05 -0700 | [diff] [blame] | 3068 | |
Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 3069 | return 0; |
Eric W. Biederman | 2d3fcc1 | 2006-10-04 02:16:43 -0700 | [diff] [blame] | 3070 | } |
| 3071 | |
Thomas Gleixner | 5346b2a | 2010-10-08 21:49:03 +0200 | [diff] [blame] | 3072 | static int |
| 3073 | msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 3074 | { |
Thomas Gleixner | 5346b2a | 2010-10-08 21:49:03 +0200 | [diff] [blame] | 3075 | struct irq_cfg *cfg = data->chip_data; |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 3076 | struct msi_msg msg; |
| 3077 | unsigned int dest; |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 3078 | |
Thomas Gleixner | 5346b2a | 2010-10-08 21:49:03 +0200 | [diff] [blame] | 3079 | if (__ioapic_set_affinity(data, mask, &dest)) |
Yinghai Lu | d5dedd4 | 2009-04-27 17:59:21 -0700 | [diff] [blame] | 3080 | return -1; |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 3081 | |
Thomas Gleixner | 5346b2a | 2010-10-08 21:49:03 +0200 | [diff] [blame] | 3082 | __get_cached_msi_msg(data->msi_desc, &msg); |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 3083 | |
| 3084 | msg.data &= ~MSI_DATA_VECTOR_MASK; |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 3085 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 3086 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
| 3087 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); |
| 3088 | |
Thomas Gleixner | 5346b2a | 2010-10-08 21:49:03 +0200 | [diff] [blame] | 3089 | __write_msi_msg(data->msi_desc, &msg); |
Yinghai Lu | d5dedd4 | 2009-04-27 17:59:21 -0700 | [diff] [blame] | 3090 | |
Jiang Liu | f841d79 | 2012-03-30 23:11:35 +0800 | [diff] [blame] | 3091 | return IRQ_SET_MASK_OK_NOCOPY; |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 3092 | } |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 3093 | |
| 3094 | /* |
| 3095 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, |
| 3096 | * which implement the MSI or MSI-X Capability Structure. |
| 3097 | */ |
| 3098 | static struct irq_chip msi_chip = { |
Thomas Gleixner | 5346b2a | 2010-10-08 21:49:03 +0200 | [diff] [blame] | 3099 | .name = "PCI-MSI", |
| 3100 | .irq_unmask = unmask_msi_irq, |
| 3101 | .irq_mask = mask_msi_irq, |
| 3102 | .irq_ack = ack_apic_edge, |
Thomas Gleixner | 5346b2a | 2010-10-08 21:49:03 +0200 | [diff] [blame] | 3103 | .irq_set_affinity = msi_set_affinity, |
Thomas Gleixner | 5346b2a | 2010-10-08 21:49:03 +0200 | [diff] [blame] | 3104 | .irq_retrigger = ioapic_retrigger_irq, |
Eric W. Biederman | 3b7d192 | 2006-10-04 02:16:59 -0700 | [diff] [blame] | 3105 | }; |
| 3106 | |
Joerg Roedel | 5afba62 | 2012-09-26 12:44:38 +0200 | [diff] [blame] | 3107 | int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, |
| 3108 | unsigned int irq_base, unsigned int irq_offset) |
Yinghai Lu | 1d02519 | 2008-08-19 20:50:34 -0700 | [diff] [blame] | 3109 | { |
Thomas Gleixner | c60eaf2 | 2011-03-11 13:17:16 +0100 | [diff] [blame] | 3110 | struct irq_chip *chip = &msi_chip; |
Yinghai Lu | 1d02519 | 2008-08-19 20:50:34 -0700 | [diff] [blame] | 3111 | struct msi_msg msg; |
Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 3112 | unsigned int irq = irq_base + irq_offset; |
Thomas Gleixner | 60c6994 | 2010-09-28 17:28:38 +0200 | [diff] [blame] | 3113 | int ret; |
Yinghai Lu | 1d02519 | 2008-08-19 20:50:34 -0700 | [diff] [blame] | 3114 | |
Suresh Siddha | c8bc6f3 | 2009-08-04 12:07:09 -0700 | [diff] [blame] | 3115 | ret = msi_compose_msg(dev, irq, &msg, -1); |
Yinghai Lu | 1d02519 | 2008-08-19 20:50:34 -0700 | [diff] [blame] | 3116 | if (ret < 0) |
| 3117 | return ret; |
| 3118 | |
Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 3119 | irq_set_msi_desc_off(irq_base, irq_offset, msidesc); |
| 3120 | |
| 3121 | /* |
| 3122 | * MSI-X message is written per-IRQ, the offset is always 0. |
| 3123 | * MSI message denotes a contiguous group of IRQs, written for 0th IRQ. |
| 3124 | */ |
| 3125 | if (!irq_offset) |
| 3126 | write_msi_msg(irq, &msg); |
Yinghai Lu | 1d02519 | 2008-08-19 20:50:34 -0700 | [diff] [blame] | 3127 | |
Joerg Roedel | 2976fd8 | 2012-09-26 12:44:48 +0200 | [diff] [blame] | 3128 | setup_remapped_irq(irq, irq_get_chip_data(irq), chip); |
Thomas Gleixner | c60eaf2 | 2011-03-11 13:17:16 +0100 | [diff] [blame] | 3129 | |
| 3130 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); |
Yinghai Lu | 1d02519 | 2008-08-19 20:50:34 -0700 | [diff] [blame] | 3131 | |
Yinghai Lu | c81bba4 | 2008-09-25 11:53:11 -0700 | [diff] [blame] | 3132 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); |
| 3133 | |
Yinghai Lu | 1d02519 | 2008-08-19 20:50:34 -0700 | [diff] [blame] | 3134 | return 0; |
| 3135 | } |
| 3136 | |
Joerg Roedel | 5afba62 | 2012-09-26 12:44:38 +0200 | [diff] [blame] | 3137 | int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
Yinghai Lu | 047c8fd | 2008-08-19 20:50:41 -0700 | [diff] [blame] | 3138 | { |
Thomas Gleixner | 60c6994 | 2010-09-28 17:28:38 +0200 | [diff] [blame] | 3139 | unsigned int irq, irq_want; |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 3140 | struct msi_desc *msidesc; |
Joerg Roedel | 5afba62 | 2012-09-26 12:44:38 +0200 | [diff] [blame] | 3141 | int node, ret; |
| 3142 | |
| 3143 | /* Multiple MSI vectors only supported with interrupt remapping */ |
| 3144 | if (type == PCI_CAP_ID_MSI && nvec > 1) |
| 3145 | return 1; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3146 | |
Yinghai Lu | d047f53a | 2009-04-27 18:02:23 -0700 | [diff] [blame] | 3147 | node = dev_to_node(&dev->dev); |
Yinghai Lu | be5d535 | 2008-12-05 18:58:33 -0800 | [diff] [blame] | 3148 | irq_want = nr_irqs_gsi; |
Yinghai Lu | 0b8f1ef | 2008-12-05 18:58:31 -0800 | [diff] [blame] | 3149 | list_for_each_entry(msidesc, &dev->msi_list, list) { |
Yinghai Lu | d047f53a | 2009-04-27 18:02:23 -0700 | [diff] [blame] | 3150 | irq = create_irq_nr(irq_want, node); |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3151 | if (irq == 0) |
Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 3152 | return -ENOSPC; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3153 | |
Joerg Roedel | 5afba62 | 2012-09-26 12:44:38 +0200 | [diff] [blame] | 3154 | irq_want = irq + 1; |
| 3155 | |
Alexander Gordeev | 51906e7 | 2012-11-19 16:01:29 +0100 | [diff] [blame] | 3156 | ret = setup_msi_irq(dev, msidesc, irq, 0); |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3157 | if (ret < 0) |
| 3158 | goto error; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3159 | } |
| 3160 | return 0; |
Yinghai Lu | 047c8fd | 2008-08-19 20:50:41 -0700 | [diff] [blame] | 3161 | |
| 3162 | error: |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3163 | destroy_irq(irq); |
| 3164 | return ret; |
Yinghai Lu | 047c8fd | 2008-08-19 20:50:41 -0700 | [diff] [blame] | 3165 | } |
| 3166 | |
Stefano Stabellini | 294ee6f | 2010-10-06 16:12:28 -0400 | [diff] [blame] | 3167 | void native_teardown_msi_irq(unsigned int irq) |
Eric W. Biederman | 2d3fcc1 | 2006-10-04 02:16:43 -0700 | [diff] [blame] | 3168 | { |
Eric W. Biederman | f7feaca | 2007-01-28 12:56:37 -0700 | [diff] [blame] | 3169 | destroy_irq(irq); |
Eric W. Biederman | 2d3fcc1 | 2006-10-04 02:16:43 -0700 | [diff] [blame] | 3170 | } |
| 3171 | |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 3172 | #ifdef CONFIG_DMAR_TABLE |
Thomas Gleixner | fe52b2d | 2010-10-08 22:19:29 +0200 | [diff] [blame] | 3173 | static int |
| 3174 | dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, |
| 3175 | bool force) |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3176 | { |
Thomas Gleixner | fe52b2d | 2010-10-08 22:19:29 +0200 | [diff] [blame] | 3177 | struct irq_cfg *cfg = data->chip_data; |
| 3178 | unsigned int dest, irq = data->irq; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3179 | struct msi_msg msg; |
Eric W. Biederman | 2d3fcc1 | 2006-10-04 02:16:43 -0700 | [diff] [blame] | 3180 | |
Thomas Gleixner | fe52b2d | 2010-10-08 22:19:29 +0200 | [diff] [blame] | 3181 | if (__ioapic_set_affinity(data, mask, &dest)) |
Yinghai Lu | d5dedd4 | 2009-04-27 17:59:21 -0700 | [diff] [blame] | 3182 | return -1; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3183 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3184 | dmar_msi_read(irq, &msg); |
| 3185 | |
| 3186 | msg.data &= ~MSI_DATA_VECTOR_MASK; |
| 3187 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
| 3188 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
| 3189 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); |
Kenji Kaneshige | 086e8ce | 2010-12-01 09:40:32 -0800 | [diff] [blame] | 3190 | msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest); |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3191 | |
| 3192 | dmar_msi_write(irq, &msg); |
Yinghai Lu | d5dedd4 | 2009-04-27 17:59:21 -0700 | [diff] [blame] | 3193 | |
Jiang Liu | f841d79 | 2012-03-30 23:11:35 +0800 | [diff] [blame] | 3194 | return IRQ_SET_MASK_OK_NOCOPY; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3195 | } |
Yinghai Lu | 3145e94 | 2008-12-05 18:58:34 -0800 | [diff] [blame] | 3196 | |
Jaswinder Singh Rajput | 8f7007a | 2009-06-10 12:41:01 -0700 | [diff] [blame] | 3197 | static struct irq_chip dmar_msi_type = { |
Thomas Gleixner | fe52b2d | 2010-10-08 22:19:29 +0200 | [diff] [blame] | 3198 | .name = "DMAR_MSI", |
| 3199 | .irq_unmask = dmar_msi_unmask, |
| 3200 | .irq_mask = dmar_msi_mask, |
| 3201 | .irq_ack = ack_apic_edge, |
Thomas Gleixner | fe52b2d | 2010-10-08 22:19:29 +0200 | [diff] [blame] | 3202 | .irq_set_affinity = dmar_msi_set_affinity, |
Thomas Gleixner | fe52b2d | 2010-10-08 22:19:29 +0200 | [diff] [blame] | 3203 | .irq_retrigger = ioapic_retrigger_irq, |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3204 | }; |
| 3205 | |
| 3206 | int arch_setup_dmar_msi(unsigned int irq) |
| 3207 | { |
| 3208 | int ret; |
| 3209 | struct msi_msg msg; |
| 3210 | |
Suresh Siddha | c8bc6f3 | 2009-08-04 12:07:09 -0700 | [diff] [blame] | 3211 | ret = msi_compose_msg(NULL, irq, &msg, -1); |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3212 | if (ret < 0) |
| 3213 | return ret; |
| 3214 | dmar_msi_write(irq, &msg); |
Thomas Gleixner | 2c77865 | 2011-03-12 12:20:43 +0100 | [diff] [blame] | 3215 | irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, |
| 3216 | "edge"); |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3217 | return 0; |
| 3218 | } |
| 3219 | #endif |
| 3220 | |
venkatesh.pallipadi@intel.com | 58ac1e7 | 2008-09-05 18:02:17 -0700 | [diff] [blame] | 3221 | #ifdef CONFIG_HPET_TIMER |
| 3222 | |
Thomas Gleixner | d0fbca8 | 2010-09-28 16:18:39 +0200 | [diff] [blame] | 3223 | static int hpet_msi_set_affinity(struct irq_data *data, |
| 3224 | const struct cpumask *mask, bool force) |
venkatesh.pallipadi@intel.com | 58ac1e7 | 2008-09-05 18:02:17 -0700 | [diff] [blame] | 3225 | { |
Thomas Gleixner | d0fbca8 | 2010-09-28 16:18:39 +0200 | [diff] [blame] | 3226 | struct irq_cfg *cfg = data->chip_data; |
venkatesh.pallipadi@intel.com | 58ac1e7 | 2008-09-05 18:02:17 -0700 | [diff] [blame] | 3227 | struct msi_msg msg; |
| 3228 | unsigned int dest; |
venkatesh.pallipadi@intel.com | 58ac1e7 | 2008-09-05 18:02:17 -0700 | [diff] [blame] | 3229 | |
Thomas Gleixner | 0e09ddf | 2010-10-08 22:21:26 +0200 | [diff] [blame] | 3230 | if (__ioapic_set_affinity(data, mask, &dest)) |
Yinghai Lu | d5dedd4 | 2009-04-27 17:59:21 -0700 | [diff] [blame] | 3231 | return -1; |
venkatesh.pallipadi@intel.com | 58ac1e7 | 2008-09-05 18:02:17 -0700 | [diff] [blame] | 3232 | |
Thomas Gleixner | d0fbca8 | 2010-09-28 16:18:39 +0200 | [diff] [blame] | 3233 | hpet_msi_read(data->handler_data, &msg); |
venkatesh.pallipadi@intel.com | 58ac1e7 | 2008-09-05 18:02:17 -0700 | [diff] [blame] | 3234 | |
| 3235 | msg.data &= ~MSI_DATA_VECTOR_MASK; |
| 3236 | msg.data |= MSI_DATA_VECTOR(cfg->vector); |
| 3237 | msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; |
| 3238 | msg.address_lo |= MSI_ADDR_DEST_ID(dest); |
| 3239 | |
Thomas Gleixner | d0fbca8 | 2010-09-28 16:18:39 +0200 | [diff] [blame] | 3240 | hpet_msi_write(data->handler_data, &msg); |
Yinghai Lu | d5dedd4 | 2009-04-27 17:59:21 -0700 | [diff] [blame] | 3241 | |
Jiang Liu | f841d79 | 2012-03-30 23:11:35 +0800 | [diff] [blame] | 3242 | return IRQ_SET_MASK_OK_NOCOPY; |
venkatesh.pallipadi@intel.com | 58ac1e7 | 2008-09-05 18:02:17 -0700 | [diff] [blame] | 3243 | } |
Yinghai Lu | 3145e94 | 2008-12-05 18:58:34 -0800 | [diff] [blame] | 3244 | |
Dmitri Vorobiev | 1cc1852 | 2009-03-22 19:11:09 +0200 | [diff] [blame] | 3245 | static struct irq_chip hpet_msi_type = { |
venkatesh.pallipadi@intel.com | 58ac1e7 | 2008-09-05 18:02:17 -0700 | [diff] [blame] | 3246 | .name = "HPET_MSI", |
Thomas Gleixner | d0fbca8 | 2010-09-28 16:18:39 +0200 | [diff] [blame] | 3247 | .irq_unmask = hpet_msi_unmask, |
| 3248 | .irq_mask = hpet_msi_mask, |
Thomas Gleixner | 90297c5 | 2010-09-28 16:03:54 +0200 | [diff] [blame] | 3249 | .irq_ack = ack_apic_edge, |
Thomas Gleixner | d0fbca8 | 2010-09-28 16:18:39 +0200 | [diff] [blame] | 3250 | .irq_set_affinity = hpet_msi_set_affinity, |
Thomas Gleixner | 90297c5 | 2010-09-28 16:03:54 +0200 | [diff] [blame] | 3251 | .irq_retrigger = ioapic_retrigger_irq, |
venkatesh.pallipadi@intel.com | 58ac1e7 | 2008-09-05 18:02:17 -0700 | [diff] [blame] | 3252 | }; |
| 3253 | |
Joerg Roedel | 71054d8 | 2012-09-26 12:44:37 +0200 | [diff] [blame] | 3254 | int default_setup_hpet_msi(unsigned int irq, unsigned int id) |
venkatesh.pallipadi@intel.com | 58ac1e7 | 2008-09-05 18:02:17 -0700 | [diff] [blame] | 3255 | { |
Thomas Gleixner | c60eaf2 | 2011-03-11 13:17:16 +0100 | [diff] [blame] | 3256 | struct irq_chip *chip = &hpet_msi_type; |
venkatesh.pallipadi@intel.com | 58ac1e7 | 2008-09-05 18:02:17 -0700 | [diff] [blame] | 3257 | struct msi_msg msg; |
Thomas Gleixner | d0fbca8 | 2010-09-28 16:18:39 +0200 | [diff] [blame] | 3258 | int ret; |
venkatesh.pallipadi@intel.com | 58ac1e7 | 2008-09-05 18:02:17 -0700 | [diff] [blame] | 3259 | |
Suresh Siddha | c8bc6f3 | 2009-08-04 12:07:09 -0700 | [diff] [blame] | 3260 | ret = msi_compose_msg(NULL, irq, &msg, id); |
venkatesh.pallipadi@intel.com | 58ac1e7 | 2008-09-05 18:02:17 -0700 | [diff] [blame] | 3261 | if (ret < 0) |
| 3262 | return ret; |
| 3263 | |
Thomas Gleixner | 2c77865 | 2011-03-12 12:20:43 +0100 | [diff] [blame] | 3264 | hpet_msi_write(irq_get_handler_data(irq), &msg); |
Thomas Gleixner | 60c6994 | 2010-09-28 17:28:38 +0200 | [diff] [blame] | 3265 | irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); |
Joerg Roedel | 2976fd8 | 2012-09-26 12:44:48 +0200 | [diff] [blame] | 3266 | setup_remapped_irq(irq, irq_get_chip_data(irq), chip); |
Yinghai Lu | c81bba4 | 2008-09-25 11:53:11 -0700 | [diff] [blame] | 3267 | |
Thomas Gleixner | c60eaf2 | 2011-03-11 13:17:16 +0100 | [diff] [blame] | 3268 | irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); |
venkatesh.pallipadi@intel.com | 58ac1e7 | 2008-09-05 18:02:17 -0700 | [diff] [blame] | 3269 | return 0; |
| 3270 | } |
| 3271 | #endif |
| 3272 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3273 | #endif /* CONFIG_PCI_MSI */ |
Eric W. Biederman | 8b955b0 | 2006-10-04 02:16:55 -0700 | [diff] [blame] | 3274 | /* |
| 3275 | * Hypertransport interrupt support |
| 3276 | */ |
| 3277 | #ifdef CONFIG_HT_IRQ |
| 3278 | |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 3279 | static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) |
Eric W. Biederman | 8b955b0 | 2006-10-04 02:16:55 -0700 | [diff] [blame] | 3280 | { |
Eric W. Biederman | ec68307 | 2006-11-08 17:44:57 -0800 | [diff] [blame] | 3281 | struct ht_irq_msg msg; |
| 3282 | fetch_ht_irq_msg(irq, &msg); |
Eric W. Biederman | 8b955b0 | 2006-10-04 02:16:55 -0700 | [diff] [blame] | 3283 | |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 3284 | msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); |
Eric W. Biederman | ec68307 | 2006-11-08 17:44:57 -0800 | [diff] [blame] | 3285 | msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); |
Eric W. Biederman | 8b955b0 | 2006-10-04 02:16:55 -0700 | [diff] [blame] | 3286 | |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 3287 | msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); |
Eric W. Biederman | ec68307 | 2006-11-08 17:44:57 -0800 | [diff] [blame] | 3288 | msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); |
Eric W. Biederman | 8b955b0 | 2006-10-04 02:16:55 -0700 | [diff] [blame] | 3289 | |
Eric W. Biederman | ec68307 | 2006-11-08 17:44:57 -0800 | [diff] [blame] | 3290 | write_ht_irq_msg(irq, &msg); |
Eric W. Biederman | 8b955b0 | 2006-10-04 02:16:55 -0700 | [diff] [blame] | 3291 | } |
| 3292 | |
Thomas Gleixner | be5b7bf | 2010-10-08 22:31:46 +0200 | [diff] [blame] | 3293 | static int |
| 3294 | ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) |
Eric W. Biederman | 8b955b0 | 2006-10-04 02:16:55 -0700 | [diff] [blame] | 3295 | { |
Thomas Gleixner | be5b7bf | 2010-10-08 22:31:46 +0200 | [diff] [blame] | 3296 | struct irq_cfg *cfg = data->chip_data; |
Eric W. Biederman | 8b955b0 | 2006-10-04 02:16:55 -0700 | [diff] [blame] | 3297 | unsigned int dest; |
Eric W. Biederman | 8b955b0 | 2006-10-04 02:16:55 -0700 | [diff] [blame] | 3298 | |
Thomas Gleixner | be5b7bf | 2010-10-08 22:31:46 +0200 | [diff] [blame] | 3299 | if (__ioapic_set_affinity(data, mask, &dest)) |
Yinghai Lu | d5dedd4 | 2009-04-27 17:59:21 -0700 | [diff] [blame] | 3300 | return -1; |
Eric W. Biederman | 8b955b0 | 2006-10-04 02:16:55 -0700 | [diff] [blame] | 3301 | |
Thomas Gleixner | be5b7bf | 2010-10-08 22:31:46 +0200 | [diff] [blame] | 3302 | target_ht_irq(data->irq, dest, cfg->vector); |
Jiang Liu | f841d79 | 2012-03-30 23:11:35 +0800 | [diff] [blame] | 3303 | return IRQ_SET_MASK_OK_NOCOPY; |
Eric W. Biederman | 8b955b0 | 2006-10-04 02:16:55 -0700 | [diff] [blame] | 3304 | } |
Yinghai Lu | 3145e94 | 2008-12-05 18:58:34 -0800 | [diff] [blame] | 3305 | |
Aneesh Kumar K.V | c37e108 | 2006-10-11 01:20:43 -0700 | [diff] [blame] | 3306 | static struct irq_chip ht_irq_chip = { |
Thomas Gleixner | be5b7bf | 2010-10-08 22:31:46 +0200 | [diff] [blame] | 3307 | .name = "PCI-HT", |
| 3308 | .irq_mask = mask_ht_irq, |
| 3309 | .irq_unmask = unmask_ht_irq, |
| 3310 | .irq_ack = ack_apic_edge, |
Thomas Gleixner | be5b7bf | 2010-10-08 22:31:46 +0200 | [diff] [blame] | 3311 | .irq_set_affinity = ht_set_affinity, |
Thomas Gleixner | be5b7bf | 2010-10-08 22:31:46 +0200 | [diff] [blame] | 3312 | .irq_retrigger = ioapic_retrigger_irq, |
Eric W. Biederman | 8b955b0 | 2006-10-04 02:16:55 -0700 | [diff] [blame] | 3313 | }; |
| 3314 | |
| 3315 | int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) |
| 3316 | { |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 3317 | struct irq_cfg *cfg; |
Alexander Gordeev | ff16432 | 2012-06-07 15:15:59 +0200 | [diff] [blame] | 3318 | struct ht_irq_msg msg; |
| 3319 | unsigned dest; |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 3320 | int err; |
Eric W. Biederman | 8b955b0 | 2006-10-04 02:16:55 -0700 | [diff] [blame] | 3321 | |
Jan Beulich | f118263 | 2009-01-14 12:27:35 +0000 | [diff] [blame] | 3322 | if (disable_apic) |
| 3323 | return -ENXIO; |
| 3324 | |
Yinghai Lu | 3145e94 | 2008-12-05 18:58:34 -0800 | [diff] [blame] | 3325 | cfg = irq_cfg(irq); |
Ingo Molnar | fe402e1 | 2009-01-28 04:32:51 +0100 | [diff] [blame] | 3326 | err = assign_irq_vector(irq, cfg, apic->target_cpus()); |
Alexander Gordeev | ff16432 | 2012-06-07 15:15:59 +0200 | [diff] [blame] | 3327 | if (err) |
| 3328 | return err; |
Eric W. Biederman | 8b955b0 | 2006-10-04 02:16:55 -0700 | [diff] [blame] | 3329 | |
Alexander Gordeev | ff16432 | 2012-06-07 15:15:59 +0200 | [diff] [blame] | 3330 | err = apic->cpu_mask_to_apicid_and(cfg->domain, |
| 3331 | apic->target_cpus(), &dest); |
| 3332 | if (err) |
| 3333 | return err; |
Eric W. Biederman | 8b955b0 | 2006-10-04 02:16:55 -0700 | [diff] [blame] | 3334 | |
Alexander Gordeev | ff16432 | 2012-06-07 15:15:59 +0200 | [diff] [blame] | 3335 | msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); |
Eric W. Biederman | 8b955b0 | 2006-10-04 02:16:55 -0700 | [diff] [blame] | 3336 | |
Alexander Gordeev | ff16432 | 2012-06-07 15:15:59 +0200 | [diff] [blame] | 3337 | msg.address_lo = |
| 3338 | HT_IRQ_LOW_BASE | |
| 3339 | HT_IRQ_LOW_DEST_ID(dest) | |
| 3340 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
| 3341 | ((apic->irq_dest_mode == 0) ? |
| 3342 | HT_IRQ_LOW_DM_PHYSICAL : |
| 3343 | HT_IRQ_LOW_DM_LOGICAL) | |
| 3344 | HT_IRQ_LOW_RQEOI_EDGE | |
| 3345 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
| 3346 | HT_IRQ_LOW_MT_FIXED : |
| 3347 | HT_IRQ_LOW_MT_ARBITRATED) | |
| 3348 | HT_IRQ_LOW_IRQ_MASKED; |
Eric W. Biederman | 8b955b0 | 2006-10-04 02:16:55 -0700 | [diff] [blame] | 3349 | |
Alexander Gordeev | ff16432 | 2012-06-07 15:15:59 +0200 | [diff] [blame] | 3350 | write_ht_irq_msg(irq, &msg); |
Eric W. Biederman | 8b955b0 | 2006-10-04 02:16:55 -0700 | [diff] [blame] | 3351 | |
Alexander Gordeev | ff16432 | 2012-06-07 15:15:59 +0200 | [diff] [blame] | 3352 | irq_set_chip_and_handler_name(irq, &ht_irq_chip, |
| 3353 | handle_edge_irq, "edge"); |
Yinghai Lu | c81bba4 | 2008-09-25 11:53:11 -0700 | [diff] [blame] | 3354 | |
Alexander Gordeev | ff16432 | 2012-06-07 15:15:59 +0200 | [diff] [blame] | 3355 | dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); |
| 3356 | |
| 3357 | return 0; |
Eric W. Biederman | 8b955b0 | 2006-10-04 02:16:55 -0700 | [diff] [blame] | 3358 | } |
| 3359 | #endif /* CONFIG_HT_IRQ */ |
| 3360 | |
Sebastian Andrzej Siewior | 2044359 | 2011-04-27 16:30:52 +0200 | [diff] [blame] | 3361 | static int |
Thomas Gleixner | ff973d0 | 2011-02-23 13:00:56 +0100 | [diff] [blame] | 3362 | io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr) |
| 3363 | { |
| 3364 | struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node); |
| 3365 | int ret; |
| 3366 | |
| 3367 | if (!cfg) |
| 3368 | return -EINVAL; |
| 3369 | ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin); |
| 3370 | if (!ret) |
Yinghai Lu | e4aff81 | 2011-10-12 00:33:05 -0700 | [diff] [blame] | 3371 | setup_ioapic_irq(irq, cfg, attr); |
Thomas Gleixner | ff973d0 | 2011-02-23 13:00:56 +0100 | [diff] [blame] | 3372 | return ret; |
| 3373 | } |
| 3374 | |
Sebastian Andrzej Siewior | 2044359 | 2011-04-27 16:30:52 +0200 | [diff] [blame] | 3375 | int io_apic_setup_irq_pin_once(unsigned int irq, int node, |
| 3376 | struct io_apic_irq_attr *attr) |
Thomas Gleixner | 710dcda | 2011-02-23 17:47:41 +0100 | [diff] [blame] | 3377 | { |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 3378 | unsigned int ioapic_idx = attr->ioapic, pin = attr->ioapic_pin; |
Thomas Gleixner | 710dcda | 2011-02-23 17:47:41 +0100 | [diff] [blame] | 3379 | int ret; |
Liu Ping Fan | 25aa295 | 2013-08-23 16:58:47 +0800 | [diff] [blame] | 3380 | struct IO_APIC_route_entry orig_entry; |
Thomas Gleixner | 710dcda | 2011-02-23 17:47:41 +0100 | [diff] [blame] | 3381 | |
| 3382 | /* Avoid redundant programming */ |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 3383 | if (test_bit(pin, ioapics[ioapic_idx].pin_programmed)) { |
Liu Ping Fan | 25aa295 | 2013-08-23 16:58:47 +0800 | [diff] [blame] | 3384 | pr_debug("Pin %d-%d already programmed\n", mpc_ioapic_id(ioapic_idx), pin); |
| 3385 | orig_entry = ioapic_read_entry(attr->ioapic, pin); |
| 3386 | if (attr->trigger == orig_entry.trigger && attr->polarity == orig_entry.polarity) |
| 3387 | return 0; |
| 3388 | return -EBUSY; |
Thomas Gleixner | 710dcda | 2011-02-23 17:47:41 +0100 | [diff] [blame] | 3389 | } |
| 3390 | ret = io_apic_setup_irq_pin(irq, node, attr); |
| 3391 | if (!ret) |
Yinghai Lu | 6f50d45 | 2011-10-12 00:33:48 -0700 | [diff] [blame] | 3392 | set_bit(pin, ioapics[ioapic_idx].pin_programmed); |
Thomas Gleixner | 710dcda | 2011-02-23 17:47:41 +0100 | [diff] [blame] | 3393 | return ret; |
| 3394 | } |
| 3395 | |
Thomas Gleixner | 41098ff | 2011-02-23 16:08:03 +0100 | [diff] [blame] | 3396 | static int __init io_apic_get_redir_entries(int ioapic) |
Yinghai Lu | 9d6a4d0 | 2008-08-19 20:50:52 -0700 | [diff] [blame] | 3397 | { |
| 3398 | union IO_APIC_reg_01 reg_01; |
| 3399 | unsigned long flags; |
| 3400 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 3401 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Yinghai Lu | 9d6a4d0 | 2008-08-19 20:50:52 -0700 | [diff] [blame] | 3402 | reg_01.raw = io_apic_read(ioapic, 1); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 3403 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Yinghai Lu | 9d6a4d0 | 2008-08-19 20:50:52 -0700 | [diff] [blame] | 3404 | |
Eric W. Biederman | 4b6b19a | 2010-03-30 01:07:08 -0700 | [diff] [blame] | 3405 | /* The register returns the maximum index redir index |
| 3406 | * supported, which is one less than the total number of redir |
| 3407 | * entries. |
| 3408 | */ |
| 3409 | return reg_01.bits.entries + 1; |
Yinghai Lu | 9d6a4d0 | 2008-08-19 20:50:52 -0700 | [diff] [blame] | 3410 | } |
| 3411 | |
Thomas Gleixner | 23f9b26 | 2010-10-15 15:38:50 -0700 | [diff] [blame] | 3412 | static void __init probe_nr_irqs_gsi(void) |
Yinghai Lu | 9d6a4d0 | 2008-08-19 20:50:52 -0700 | [diff] [blame] | 3413 | { |
Eric W. Biederman | 4afc51a | 2010-03-30 01:07:14 -0700 | [diff] [blame] | 3414 | int nr; |
Yinghai Lu | be5d535 | 2008-12-05 18:58:33 -0800 | [diff] [blame] | 3415 | |
Eric W. Biederman | a4384df | 2010-06-08 11:44:32 -0700 | [diff] [blame] | 3416 | nr = gsi_top + NR_IRQS_LEGACY; |
Eric W. Biederman | 4afc51a | 2010-03-30 01:07:14 -0700 | [diff] [blame] | 3417 | if (nr > nr_irqs_gsi) |
Yinghai Lu | be5d535 | 2008-12-05 18:58:33 -0800 | [diff] [blame] | 3418 | nr_irqs_gsi = nr; |
Yinghai Lu | cc6c500 | 2009-02-08 16:18:03 -0800 | [diff] [blame] | 3419 | |
| 3420 | printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); |
Yinghai Lu | 9d6a4d0 | 2008-08-19 20:50:52 -0700 | [diff] [blame] | 3421 | } |
| 3422 | |
Jeremy Fitzhardinge | 7b586d7 | 2009-02-12 17:22:49 -0800 | [diff] [blame] | 3423 | int get_nr_irqs_gsi(void) |
| 3424 | { |
| 3425 | return nr_irqs_gsi; |
| 3426 | } |
| 3427 | |
Thomas Gleixner | 62a08ae | 2014-04-24 09:50:53 +0200 | [diff] [blame^] | 3428 | unsigned int arch_dynirq_lower_bound(unsigned int from) |
| 3429 | { |
| 3430 | return from < nr_irqs_gsi ? nr_irqs_gsi : from; |
| 3431 | } |
| 3432 | |
Yinghai Lu | 4a046d1 | 2009-01-12 17:39:24 -0800 | [diff] [blame] | 3433 | int __init arch_probe_nr_irqs(void) |
| 3434 | { |
| 3435 | int nr; |
| 3436 | |
Yinghai Lu | f1ee554 | 2009-02-08 16:18:03 -0800 | [diff] [blame] | 3437 | if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) |
| 3438 | nr_irqs = NR_VECTORS * nr_cpu_ids; |
Yinghai Lu | 4a046d1 | 2009-01-12 17:39:24 -0800 | [diff] [blame] | 3439 | |
Yinghai Lu | f1ee554 | 2009-02-08 16:18:03 -0800 | [diff] [blame] | 3440 | nr = nr_irqs_gsi + 8 * nr_cpu_ids; |
| 3441 | #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) |
| 3442 | /* |
| 3443 | * for MSI and HT dyn irq |
| 3444 | */ |
| 3445 | nr += nr_irqs_gsi * 16; |
| 3446 | #endif |
| 3447 | if (nr < nr_irqs) |
Yinghai Lu | 4a046d1 | 2009-01-12 17:39:24 -0800 | [diff] [blame] | 3448 | nr_irqs = nr; |
| 3449 | |
Thomas Gleixner | b683de2 | 2010-09-27 20:55:03 +0200 | [diff] [blame] | 3450 | return NR_IRQS_LEGACY; |
Yinghai Lu | 4a046d1 | 2009-01-12 17:39:24 -0800 | [diff] [blame] | 3451 | } |
Yinghai Lu | 4a046d1 | 2009-01-12 17:39:24 -0800 | [diff] [blame] | 3452 | |
Thomas Gleixner | 710dcda | 2011-02-23 17:47:41 +0100 | [diff] [blame] | 3453 | int io_apic_set_pci_routing(struct device *dev, int irq, |
| 3454 | struct io_apic_irq_attr *irq_attr) |
Yinghai Lu | 5ef2183 | 2009-05-06 10:08:50 -0700 | [diff] [blame] | 3455 | { |
Yinghai Lu | 5ef2183 | 2009-05-06 10:08:50 -0700 | [diff] [blame] | 3456 | int node; |
| 3457 | |
| 3458 | if (!IO_APIC_IRQ(irq)) { |
| 3459 | apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", |
Thomas Gleixner | e0799c0 | 2011-02-23 14:10:54 +0100 | [diff] [blame] | 3460 | irq_attr->ioapic); |
Yinghai Lu | 5ef2183 | 2009-05-06 10:08:50 -0700 | [diff] [blame] | 3461 | return -EINVAL; |
| 3462 | } |
| 3463 | |
Thomas Gleixner | e0799c0 | 2011-02-23 14:10:54 +0100 | [diff] [blame] | 3464 | node = dev ? dev_to_node(dev) : cpu_to_node(0); |
Yinghai Lu | 5ef2183 | 2009-05-06 10:08:50 -0700 | [diff] [blame] | 3465 | |
Thomas Gleixner | 710dcda | 2011-02-23 17:47:41 +0100 | [diff] [blame] | 3466 | return io_apic_setup_irq_pin_once(irq, node, irq_attr); |
Yinghai Lu | 5ef2183 | 2009-05-06 10:08:50 -0700 | [diff] [blame] | 3467 | } |
| 3468 | |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 3469 | #ifdef CONFIG_X86_32 |
Thomas Gleixner | 41098ff | 2011-02-23 16:08:03 +0100 | [diff] [blame] | 3470 | static int __init io_apic_get_unique_id(int ioapic, int apic_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3471 | { |
| 3472 | union IO_APIC_reg_00 reg_00; |
| 3473 | static physid_mask_t apic_id_map = PHYSID_MASK_NONE; |
| 3474 | physid_mask_t tmp; |
| 3475 | unsigned long flags; |
| 3476 | int i = 0; |
| 3477 | |
| 3478 | /* |
Paolo Ciarrocchi | 3606244 | 2008-06-08 13:07:18 +0200 | [diff] [blame] | 3479 | * The P4 platform supports up to 256 APIC IDs on two separate APIC |
| 3480 | * buses (one for LAPICs, one for IOAPICs), where predecessors only |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3481 | * supports up to 16 on one shared APIC bus. |
Paolo Ciarrocchi | 3606244 | 2008-06-08 13:07:18 +0200 | [diff] [blame] | 3482 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3483 | * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full |
| 3484 | * advantage of new APIC bus architecture. |
| 3485 | */ |
| 3486 | |
| 3487 | if (physids_empty(apic_id_map)) |
Cyrill Gorcunov | 7abc075 | 2009-11-10 01:06:59 +0300 | [diff] [blame] | 3488 | apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3489 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 3490 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3491 | reg_00.raw = io_apic_read(ioapic, 0); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 3492 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3493 | |
| 3494 | if (apic_id >= get_physical_broadcast()) { |
| 3495 | printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " |
| 3496 | "%d\n", ioapic, apic_id, reg_00.bits.ID); |
| 3497 | apic_id = reg_00.bits.ID; |
| 3498 | } |
| 3499 | |
| 3500 | /* |
Paolo Ciarrocchi | 3606244 | 2008-06-08 13:07:18 +0200 | [diff] [blame] | 3501 | * Every APIC in a system must have a unique ID or we get lots of nice |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3502 | * 'stuck on smp_invalidate_needed IPI wait' messages. |
| 3503 | */ |
Cyrill Gorcunov | 7abc075 | 2009-11-10 01:06:59 +0300 | [diff] [blame] | 3504 | if (apic->check_apicid_used(&apic_id_map, apic_id)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3505 | |
| 3506 | for (i = 0; i < get_physical_broadcast(); i++) { |
Cyrill Gorcunov | 7abc075 | 2009-11-10 01:06:59 +0300 | [diff] [blame] | 3507 | if (!apic->check_apicid_used(&apic_id_map, i)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3508 | break; |
| 3509 | } |
| 3510 | |
| 3511 | if (i == get_physical_broadcast()) |
| 3512 | panic("Max apic_id exceeded!\n"); |
| 3513 | |
| 3514 | printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " |
| 3515 | "trying %d\n", ioapic, apic_id, i); |
| 3516 | |
| 3517 | apic_id = i; |
Paolo Ciarrocchi | 3606244 | 2008-06-08 13:07:18 +0200 | [diff] [blame] | 3518 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3519 | |
Cyrill Gorcunov | 7abc075 | 2009-11-10 01:06:59 +0300 | [diff] [blame] | 3520 | apic->apicid_to_cpu_present(apic_id, &tmp); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3521 | physids_or(apic_id_map, apic_id_map, tmp); |
| 3522 | |
| 3523 | if (reg_00.bits.ID != apic_id) { |
| 3524 | reg_00.bits.ID = apic_id; |
| 3525 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 3526 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3527 | io_apic_write(ioapic, 0, reg_00.raw); |
| 3528 | reg_00.raw = io_apic_read(ioapic, 0); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 3529 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3530 | |
| 3531 | /* Sanity check */ |
Andreas Deresch | 6070f9e | 2006-02-26 04:18:34 +0100 | [diff] [blame] | 3532 | if (reg_00.bits.ID != apic_id) { |
Joe Perches | c767a54 | 2012-05-21 19:50:07 -0700 | [diff] [blame] | 3533 | pr_err("IOAPIC[%d]: Unable to change apic_id!\n", |
| 3534 | ioapic); |
Andreas Deresch | 6070f9e | 2006-02-26 04:18:34 +0100 | [diff] [blame] | 3535 | return -1; |
| 3536 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3537 | } |
| 3538 | |
| 3539 | apic_printk(APIC_VERBOSE, KERN_INFO |
| 3540 | "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); |
| 3541 | |
| 3542 | return apic_id; |
| 3543 | } |
Thomas Gleixner | 41098ff | 2011-02-23 16:08:03 +0100 | [diff] [blame] | 3544 | |
| 3545 | static u8 __init io_apic_unique_id(u8 id) |
| 3546 | { |
| 3547 | if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && |
| 3548 | !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) |
| 3549 | return io_apic_get_unique_id(nr_ioapics, id); |
| 3550 | else |
| 3551 | return id; |
| 3552 | } |
| 3553 | #else |
| 3554 | static u8 __init io_apic_unique_id(u8 id) |
| 3555 | { |
| 3556 | int i; |
| 3557 | DECLARE_BITMAP(used, 256); |
| 3558 | |
| 3559 | bitmap_zero(used, 256); |
| 3560 | for (i = 0; i < nr_ioapics; i++) { |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 3561 | __set_bit(mpc_ioapic_id(i), used); |
Thomas Gleixner | 41098ff | 2011-02-23 16:08:03 +0100 | [diff] [blame] | 3562 | } |
| 3563 | if (!test_bit(id, used)) |
| 3564 | return id; |
| 3565 | return find_first_zero_bit(used, 256); |
| 3566 | } |
Naga Chumbalkar | 58f892e | 2009-05-26 21:48:07 +0000 | [diff] [blame] | 3567 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3568 | |
Thomas Gleixner | 41098ff | 2011-02-23 16:08:03 +0100 | [diff] [blame] | 3569 | static int __init io_apic_get_version(int ioapic) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3570 | { |
| 3571 | union IO_APIC_reg_01 reg_01; |
| 3572 | unsigned long flags; |
| 3573 | |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 3574 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3575 | reg_01.raw = io_apic_read(ioapic, 1); |
Thomas Gleixner | dade771 | 2009-07-25 18:39:36 +0200 | [diff] [blame] | 3576 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3577 | |
| 3578 | return reg_01.bits.version; |
| 3579 | } |
| 3580 | |
Eric W. Biederman | 9a0a91b | 2010-03-30 01:07:03 -0700 | [diff] [blame] | 3581 | int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) |
Shaohua Li | 61fd47e | 2007-11-17 01:05:28 -0500 | [diff] [blame] | 3582 | { |
Eric W. Biederman | 9a0a91b | 2010-03-30 01:07:03 -0700 | [diff] [blame] | 3583 | int ioapic, pin, idx; |
Shaohua Li | 61fd47e | 2007-11-17 01:05:28 -0500 | [diff] [blame] | 3584 | |
| 3585 | if (skip_ioapic_setup) |
| 3586 | return -1; |
| 3587 | |
Eric W. Biederman | 9a0a91b | 2010-03-30 01:07:03 -0700 | [diff] [blame] | 3588 | ioapic = mp_find_ioapic(gsi); |
| 3589 | if (ioapic < 0) |
Shaohua Li | 61fd47e | 2007-11-17 01:05:28 -0500 | [diff] [blame] | 3590 | return -1; |
| 3591 | |
Eric W. Biederman | 9a0a91b | 2010-03-30 01:07:03 -0700 | [diff] [blame] | 3592 | pin = mp_find_ioapic_pin(ioapic, gsi); |
| 3593 | if (pin < 0) |
| 3594 | return -1; |
| 3595 | |
| 3596 | idx = find_irq_entry(ioapic, pin, mp_INT); |
| 3597 | if (idx < 0) |
| 3598 | return -1; |
| 3599 | |
| 3600 | *trigger = irq_trigger(idx); |
| 3601 | *polarity = irq_polarity(idx); |
Shaohua Li | 61fd47e | 2007-11-17 01:05:28 -0500 | [diff] [blame] | 3602 | return 0; |
| 3603 | } |
| 3604 | |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 3605 | /* |
| 3606 | * This function currently is only a helper for the i386 smp boot process where |
| 3607 | * we need to reprogram the ioredtbls to cater for the cpus which have come online |
Ingo Molnar | fe402e1 | 2009-01-28 04:32:51 +0100 | [diff] [blame] | 3608 | * so mask in all cases should simply be apic->target_cpus() |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 3609 | */ |
| 3610 | #ifdef CONFIG_SMP |
| 3611 | void __init setup_ioapic_dest(void) |
| 3612 | { |
Eric W. Biederman | fad5399 | 2010-02-28 01:06:34 -0800 | [diff] [blame] | 3613 | int pin, ioapic, irq, irq_entry; |
Mike Travis | 22f65d3 | 2008-12-16 17:33:56 -0800 | [diff] [blame] | 3614 | const struct cpumask *mask; |
Thomas Gleixner | 5451ddc | 2011-02-05 15:35:51 +0100 | [diff] [blame] | 3615 | struct irq_data *idata; |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 3616 | |
| 3617 | if (skip_ioapic_setup == 1) |
| 3618 | return; |
| 3619 | |
Eric W. Biederman | fad5399 | 2010-02-28 01:06:34 -0800 | [diff] [blame] | 3620 | for (ioapic = 0; ioapic < nr_ioapics; ioapic++) |
Suresh Siddha | b69c6c3 | 2011-05-18 16:31:35 -0700 | [diff] [blame] | 3621 | for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) { |
Yinghai Lu | b9c61b70 | 2009-05-06 10:10:06 -0700 | [diff] [blame] | 3622 | irq_entry = find_irq_entry(ioapic, pin, mp_INT); |
| 3623 | if (irq_entry == -1) |
| 3624 | continue; |
| 3625 | irq = pin_2_irq(irq_entry, ioapic, pin); |
| 3626 | |
Eric W. Biederman | fad5399 | 2010-02-28 01:06:34 -0800 | [diff] [blame] | 3627 | if ((ioapic > 0) && (irq > 16)) |
| 3628 | continue; |
| 3629 | |
Thomas Gleixner | 5451ddc | 2011-02-05 15:35:51 +0100 | [diff] [blame] | 3630 | idata = irq_get_irq_data(irq); |
Yinghai Lu | b9c61b70 | 2009-05-06 10:10:06 -0700 | [diff] [blame] | 3631 | |
| 3632 | /* |
| 3633 | * Honour affinities which have been set in early boot |
| 3634 | */ |
Thomas Gleixner | 5451ddc | 2011-02-05 15:35:51 +0100 | [diff] [blame] | 3635 | if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata)) |
| 3636 | mask = idata->affinity; |
Yinghai Lu | b9c61b70 | 2009-05-06 10:10:06 -0700 | [diff] [blame] | 3637 | else |
| 3638 | mask = apic->target_cpus(); |
| 3639 | |
Joerg Roedel | 373dd7a | 2012-09-26 12:44:39 +0200 | [diff] [blame] | 3640 | x86_io_apic_ops.set_affinity(idata, mask, false); |
Yinghai Lu | b9c61b70 | 2009-05-06 10:10:06 -0700 | [diff] [blame] | 3641 | } |
| 3642 | |
Yinghai Lu | 497c9a1 | 2008-08-19 20:50:28 -0700 | [diff] [blame] | 3643 | } |
| 3644 | #endif |
| 3645 | |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3646 | #define IOAPIC_RESOURCE_NAME_SIZE 11 |
| 3647 | |
| 3648 | static struct resource *ioapic_resources; |
| 3649 | |
Cyrill Gorcunov | ffc4383 | 2009-08-24 21:53:39 +0400 | [diff] [blame] | 3650 | static struct resource * __init ioapic_setup_resources(int nr_ioapics) |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3651 | { |
| 3652 | unsigned long n; |
| 3653 | struct resource *res; |
| 3654 | char *mem; |
| 3655 | int i; |
| 3656 | |
| 3657 | if (nr_ioapics <= 0) |
| 3658 | return NULL; |
| 3659 | |
| 3660 | n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); |
| 3661 | n *= nr_ioapics; |
| 3662 | |
| 3663 | mem = alloc_bootmem(n); |
| 3664 | res = (void *)mem; |
| 3665 | |
Cyrill Gorcunov | ffc4383 | 2009-08-24 21:53:39 +0400 | [diff] [blame] | 3666 | mem += sizeof(struct resource) * nr_ioapics; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3667 | |
Cyrill Gorcunov | ffc4383 | 2009-08-24 21:53:39 +0400 | [diff] [blame] | 3668 | for (i = 0; i < nr_ioapics; i++) { |
| 3669 | res[i].name = mem; |
| 3670 | res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; |
Cyrill Gorcunov | 4343fe1 | 2009-11-08 18:54:31 +0300 | [diff] [blame] | 3671 | snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); |
Cyrill Gorcunov | ffc4383 | 2009-08-24 21:53:39 +0400 | [diff] [blame] | 3672 | mem += IOAPIC_RESOURCE_NAME_SIZE; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3673 | } |
| 3674 | |
| 3675 | ioapic_resources = res; |
| 3676 | |
| 3677 | return res; |
| 3678 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3679 | |
Konrad Rzeszutek Wilk | 4a8e2a3 | 2012-03-28 12:37:36 -0400 | [diff] [blame] | 3680 | void __init native_io_apic_init_mappings(void) |
Jeremy Fitzhardinge | 136d249 | 2012-03-21 22:58:08 -0400 | [diff] [blame] | 3681 | { |
Yinghai Lu | f3294a3 | 2008-06-27 01:41:56 -0700 | [diff] [blame] | 3682 | unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3683 | struct resource *ioapic_res; |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 3684 | int i; |
Yinghai Lu | f3294a3 | 2008-06-27 01:41:56 -0700 | [diff] [blame] | 3685 | |
Cyrill Gorcunov | ffc4383 | 2009-08-24 21:53:39 +0400 | [diff] [blame] | 3686 | ioapic_res = ioapic_setup_resources(nr_ioapics); |
Yinghai Lu | f3294a3 | 2008-06-27 01:41:56 -0700 | [diff] [blame] | 3687 | for (i = 0; i < nr_ioapics; i++) { |
| 3688 | if (smp_found_config) { |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 3689 | ioapic_phys = mpc_ioapic_addr(i); |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3690 | #ifdef CONFIG_X86_32 |
Thomas Gleixner | d6c88a5 | 2008-10-15 15:27:23 +0200 | [diff] [blame] | 3691 | if (!ioapic_phys) { |
| 3692 | printk(KERN_ERR |
| 3693 | "WARNING: bogus zero IO-APIC " |
| 3694 | "address found in MPTABLE, " |
| 3695 | "disabling IO/APIC support!\n"); |
| 3696 | smp_found_config = 0; |
| 3697 | skip_ioapic_setup = 1; |
| 3698 | goto fake_ioapic_page; |
| 3699 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3700 | #endif |
Yinghai Lu | f3294a3 | 2008-06-27 01:41:56 -0700 | [diff] [blame] | 3701 | } else { |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3702 | #ifdef CONFIG_X86_32 |
Yinghai Lu | f3294a3 | 2008-06-27 01:41:56 -0700 | [diff] [blame] | 3703 | fake_ioapic_page: |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3704 | #endif |
Cyrill Gorcunov | e79c65a | 2009-11-16 18:14:26 +0300 | [diff] [blame] | 3705 | ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); |
Yinghai Lu | f3294a3 | 2008-06-27 01:41:56 -0700 | [diff] [blame] | 3706 | ioapic_phys = __pa(ioapic_phys); |
| 3707 | } |
| 3708 | set_fixmap_nocache(idx, ioapic_phys); |
Cyrill Gorcunov | e79c65a | 2009-11-16 18:14:26 +0300 | [diff] [blame] | 3709 | apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", |
| 3710 | __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), |
| 3711 | ioapic_phys); |
Yinghai Lu | f3294a3 | 2008-06-27 01:41:56 -0700 | [diff] [blame] | 3712 | idx++; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3713 | |
Cyrill Gorcunov | ffc4383 | 2009-08-24 21:53:39 +0400 | [diff] [blame] | 3714 | ioapic_res->start = ioapic_phys; |
Cyrill Gorcunov | e79c65a | 2009-11-16 18:14:26 +0300 | [diff] [blame] | 3715 | ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; |
Cyrill Gorcunov | ffc4383 | 2009-08-24 21:53:39 +0400 | [diff] [blame] | 3716 | ioapic_res++; |
Yinghai Lu | f3294a3 | 2008-06-27 01:41:56 -0700 | [diff] [blame] | 3717 | } |
Thomas Gleixner | 23f9b26 | 2010-10-15 15:38:50 -0700 | [diff] [blame] | 3718 | |
| 3719 | probe_nr_irqs_gsi(); |
Yinghai Lu | f3294a3 | 2008-06-27 01:41:56 -0700 | [diff] [blame] | 3720 | } |
| 3721 | |
Yinghai Lu | 857fdc5 | 2009-07-10 09:36:20 -0700 | [diff] [blame] | 3722 | void __init ioapic_insert_resources(void) |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3723 | { |
| 3724 | int i; |
| 3725 | struct resource *r = ioapic_resources; |
| 3726 | |
| 3727 | if (!r) { |
Yinghai Lu | 857fdc5 | 2009-07-10 09:36:20 -0700 | [diff] [blame] | 3728 | if (nr_ioapics > 0) |
Bartlomiej Zolnierkiewicz | 04c93ce | 2009-03-20 21:02:55 +0100 | [diff] [blame] | 3729 | printk(KERN_ERR |
| 3730 | "IO APIC resources couldn't be allocated.\n"); |
Yinghai Lu | 857fdc5 | 2009-07-10 09:36:20 -0700 | [diff] [blame] | 3731 | return; |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3732 | } |
| 3733 | |
| 3734 | for (i = 0; i < nr_ioapics; i++) { |
| 3735 | insert_resource(&iomem_resource, r); |
| 3736 | r++; |
| 3737 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3738 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3739 | |
Eric W. Biederman | eddb0c5 | 2010-03-30 01:07:09 -0700 | [diff] [blame] | 3740 | int mp_find_ioapic(u32 gsi) |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 3741 | { |
| 3742 | int i = 0; |
| 3743 | |
Paul Bolle | 678301e | 2011-02-14 22:52:38 +0100 | [diff] [blame] | 3744 | if (nr_ioapics == 0) |
| 3745 | return -1; |
| 3746 | |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 3747 | /* Find the IOAPIC that manages this GSI. */ |
| 3748 | for (i = 0; i < nr_ioapics; i++) { |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 3749 | struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i); |
| 3750 | if ((gsi >= gsi_cfg->gsi_base) |
| 3751 | && (gsi <= gsi_cfg->gsi_end)) |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 3752 | return i; |
| 3753 | } |
| 3754 | |
| 3755 | printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); |
| 3756 | return -1; |
| 3757 | } |
| 3758 | |
Eric W. Biederman | eddb0c5 | 2010-03-30 01:07:09 -0700 | [diff] [blame] | 3759 | int mp_find_ioapic_pin(int ioapic, u32 gsi) |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 3760 | { |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 3761 | struct mp_ioapic_gsi *gsi_cfg; |
| 3762 | |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 3763 | if (WARN_ON(ioapic == -1)) |
| 3764 | return -1; |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 3765 | |
| 3766 | gsi_cfg = mp_ioapic_gsi_routing(ioapic); |
| 3767 | if (WARN_ON(gsi > gsi_cfg->gsi_end)) |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 3768 | return -1; |
| 3769 | |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 3770 | return gsi - gsi_cfg->gsi_base; |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 3771 | } |
| 3772 | |
Thomas Gleixner | 41098ff | 2011-02-23 16:08:03 +0100 | [diff] [blame] | 3773 | static __init int bad_ioapic(unsigned long address) |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 3774 | { |
| 3775 | if (nr_ioapics >= MAX_IO_APICS) { |
Suresh Siddha | 73d63d0 | 2012-03-12 11:36:33 -0700 | [diff] [blame] | 3776 | pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n", |
| 3777 | MAX_IO_APICS, nr_ioapics); |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 3778 | return 1; |
| 3779 | } |
| 3780 | if (!address) { |
Suresh Siddha | 73d63d0 | 2012-03-12 11:36:33 -0700 | [diff] [blame] | 3781 | pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n"); |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 3782 | return 1; |
| 3783 | } |
Ingo Molnar | 54168ed | 2008-08-20 09:07:45 +0200 | [diff] [blame] | 3784 | return 0; |
| 3785 | } |
| 3786 | |
Suresh Siddha | 73d63d0 | 2012-03-12 11:36:33 -0700 | [diff] [blame] | 3787 | static __init int bad_ioapic_register(int idx) |
| 3788 | { |
| 3789 | union IO_APIC_reg_00 reg_00; |
| 3790 | union IO_APIC_reg_01 reg_01; |
| 3791 | union IO_APIC_reg_02 reg_02; |
| 3792 | |
| 3793 | reg_00.raw = io_apic_read(idx, 0); |
| 3794 | reg_01.raw = io_apic_read(idx, 1); |
| 3795 | reg_02.raw = io_apic_read(idx, 2); |
| 3796 | |
| 3797 | if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) { |
| 3798 | pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n", |
| 3799 | mpc_ioapic_addr(idx)); |
| 3800 | return 1; |
| 3801 | } |
| 3802 | |
| 3803 | return 0; |
| 3804 | } |
| 3805 | |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 3806 | void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) |
| 3807 | { |
| 3808 | int idx = 0; |
Eric W. Biederman | 7716a5c | 2010-03-30 01:07:12 -0700 | [diff] [blame] | 3809 | int entries; |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 3810 | struct mp_ioapic_gsi *gsi_cfg; |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 3811 | |
| 3812 | if (bad_ioapic(address)) |
| 3813 | return; |
| 3814 | |
| 3815 | idx = nr_ioapics; |
| 3816 | |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 3817 | ioapics[idx].mp_config.type = MP_IOAPIC; |
| 3818 | ioapics[idx].mp_config.flags = MPC_APIC_USABLE; |
| 3819 | ioapics[idx].mp_config.apicaddr = address; |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 3820 | |
| 3821 | set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); |
Suresh Siddha | 73d63d0 | 2012-03-12 11:36:33 -0700 | [diff] [blame] | 3822 | |
| 3823 | if (bad_ioapic_register(idx)) { |
| 3824 | clear_fixmap(FIX_IO_APIC_BASE_0 + idx); |
| 3825 | return; |
| 3826 | } |
| 3827 | |
Suresh Siddha | d537143 | 2011-05-18 16:31:37 -0700 | [diff] [blame] | 3828 | ioapics[idx].mp_config.apicid = io_apic_unique_id(id); |
| 3829 | ioapics[idx].mp_config.apicver = io_apic_get_version(idx); |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 3830 | |
| 3831 | /* |
| 3832 | * Build basic GSI lookup table to facilitate gsi->io_apic lookups |
| 3833 | * and to prevent reprogramming of IOAPIC pins (PCI GSIs). |
| 3834 | */ |
Eric W. Biederman | 7716a5c | 2010-03-30 01:07:12 -0700 | [diff] [blame] | 3835 | entries = io_apic_get_redir_entries(idx); |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 3836 | gsi_cfg = mp_ioapic_gsi_routing(idx); |
| 3837 | gsi_cfg->gsi_base = gsi_base; |
| 3838 | gsi_cfg->gsi_end = gsi_base + entries - 1; |
Eric W. Biederman | 7716a5c | 2010-03-30 01:07:12 -0700 | [diff] [blame] | 3839 | |
| 3840 | /* |
| 3841 | * The number of IO-APIC IRQ registers (== #pins): |
| 3842 | */ |
Suresh Siddha | b69c6c3 | 2011-05-18 16:31:35 -0700 | [diff] [blame] | 3843 | ioapics[idx].nr_registers = entries; |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 3844 | |
Suresh Siddha | c040aae | 2011-05-18 16:31:38 -0700 | [diff] [blame] | 3845 | if (gsi_cfg->gsi_end >= gsi_top) |
| 3846 | gsi_top = gsi_cfg->gsi_end + 1; |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 3847 | |
Suresh Siddha | 73d63d0 | 2012-03-12 11:36:33 -0700 | [diff] [blame] | 3848 | pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n", |
| 3849 | idx, mpc_ioapic_id(idx), |
| 3850 | mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), |
| 3851 | gsi_cfg->gsi_base, gsi_cfg->gsi_end); |
Feng Tang | 2a4ab64 | 2009-07-07 23:01:15 -0400 | [diff] [blame] | 3852 | |
| 3853 | nr_ioapics++; |
| 3854 | } |
Jacob Pan | 05ddafb | 2009-09-23 07:20:23 -0700 | [diff] [blame] | 3855 | |
| 3856 | /* Enable IOAPIC early just for system timer */ |
| 3857 | void __init pre_init_apic_IRQ0(void) |
| 3858 | { |
Thomas Gleixner | f880ec7 | 2011-02-23 13:07:54 +0100 | [diff] [blame] | 3859 | struct io_apic_irq_attr attr = { 0, 0, 0, 0 }; |
Jacob Pan | 05ddafb | 2009-09-23 07:20:23 -0700 | [diff] [blame] | 3860 | |
| 3861 | printk(KERN_INFO "Early APIC setup for system timer0\n"); |
| 3862 | #ifndef CONFIG_SMP |
Yinghai Lu | cb2ded3 | 2011-01-04 16:38:52 -0800 | [diff] [blame] | 3863 | physid_set_mask_of_physid(boot_cpu_physical_apicid, |
| 3864 | &phys_cpu_present_map); |
Jacob Pan | 05ddafb | 2009-09-23 07:20:23 -0700 | [diff] [blame] | 3865 | #endif |
Jacob Pan | 05ddafb | 2009-09-23 07:20:23 -0700 | [diff] [blame] | 3866 | setup_local_APIC(); |
| 3867 | |
Thomas Gleixner | f880ec7 | 2011-02-23 13:07:54 +0100 | [diff] [blame] | 3868 | io_apic_setup_irq_pin(0, 0, &attr); |
Thomas Gleixner | 2c77865 | 2011-03-12 12:20:43 +0100 | [diff] [blame] | 3869 | irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, |
| 3870 | "edge"); |
Jacob Pan | 05ddafb | 2009-09-23 07:20:23 -0700 | [diff] [blame] | 3871 | } |