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gerrit-public.fairphone.software / kernel / msm-4.9 / 665a535ab9a076736c0a68a692852bb7b6840ecd / . / arch / arm64 / boot / dts / qcom / sdm670-sde-display.dtsi
blob: 27b27d01a20198381aa63af7c6c6bae9890e9952 [file] [log] [blame]
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]1/* Copyright (c) 2017, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include "dsi-panel-sim-video.dtsi"
14#include "dsi-panel-sim-cmd.dtsi"
15#include "dsi-panel-sim-dsc375-cmd.dtsi"
16#include "dsi-panel-sim-dualmipi-video.dtsi"
17#include "dsi-panel-sim-dualmipi-cmd.dtsi"
18#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi"
19#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi"
20#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi"
21#include "dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi"
22#include "dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi"
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]23#include "dsi-panel-nt35597-dualmipi-wqxga-video.dtsi"
24#include "dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi"
25#include "dsi-panel-nt35695b-truly-fhd-video.dtsi"
26#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi"
27#include "dsi-panel-rm67195-amoled-fhd-cmd.dtsi"
Yuan Zhao3e1868e2017-09-25 16:47:29 +0800[diff] [blame]28#include "dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi"
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]29#include <dt-bindings/clock/mdss-10nm-pll-clk.h>
30
31&soc {
32 dsi_panel_pwr_supply: dsi_panel_pwr_supply {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 qcom,panel-supply-entry@0 {
37 reg = <0>;
38 qcom,supply-name = "vddio";
39 qcom,supply-min-voltage = <1800000>;
40 qcom,supply-max-voltage = <1800000>;
41 qcom,supply-enable-load = <62000>;
42 qcom,supply-disable-load = <80>;
43 qcom,supply-post-on-sleep = <20>;
44 };
45
46 qcom,panel-supply-entry@1 {
47 reg = <1>;
48 qcom,supply-name = "lab";
49 qcom,supply-min-voltage = <4600000>;
50 qcom,supply-max-voltage = <6000000>;
51 qcom,supply-enable-load = <100000>;
52 qcom,supply-disable-load = <100>;
53 };
54
55 qcom,panel-supply-entry@2 {
56 reg = <2>;
57 qcom,supply-name = "ibb";
58 qcom,supply-min-voltage = <4600000>;
59 qcom,supply-max-voltage = <6000000>;
60 qcom,supply-enable-load = <100000>;
61 qcom,supply-disable-load = <100>;
62 qcom,supply-post-on-sleep = <20>;
63 };
64 };
65
66 dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
67 #address-cells = <1>;
68 #size-cells = <0>;
69
70 qcom,panel-supply-entry@0 {
71 reg = <0>;
72 qcom,supply-name = "vddio";
73 qcom,supply-min-voltage = <1800000>;
74 qcom,supply-max-voltage = <1800000>;
75 qcom,supply-enable-load = <62000>;
76 qcom,supply-disable-load = <80>;
77 qcom,supply-post-on-sleep = <20>;
78 };
79 };
80
81 dsi_panel_pwr_supply_vdd_no_labibb: dsi_panel_pwr_supply_vdd_no_labibb {
82 #address-cells = <1>;
83 #size-cells = <0>;
84
85 qcom,panel-supply-entry@0 {
86 reg = <0>;
87 qcom,supply-name = "vddio";
88 qcom,supply-min-voltage = <1800000>;
89 qcom,supply-max-voltage = <1800000>;
90 qcom,supply-enable-load = <62000>;
91 qcom,supply-disable-load = <80>;
92 qcom,supply-post-on-sleep = <20>;
93 };
94
95 qcom,panel-supply-entry@1 {
96 reg = <1>;
97 qcom,supply-name = "vdd";
98 qcom,supply-min-voltage = <3000000>;
99 qcom,supply-max-voltage = <3000000>;
100 qcom,supply-enable-load = <857000>;
101 qcom,supply-disable-load = <0>;
102 qcom,supply-post-on-sleep = <0>;
103 };
104 };
105
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]106 dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled {
107 #address-cells = <1>;
108 #size-cells = <0>;
109
110 qcom,panel-supply-entry@0 {
111 reg = <0>;
Vishnuvardhan Prodduturid5fb0802017-11-08 14:49:31 +0530[diff] [blame]112 qcom,supply-name = "vddio";
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]113 qcom,supply-min-voltage = <1800000>;
Vishnuvardhan Prodduturid5fb0802017-11-08 14:49:31 +0530[diff] [blame]114 qcom,supply-max-voltage = <1800000>;
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]115 qcom,supply-enable-load = <32000>;
116 qcom,supply-disable-load = <80>;
117 };
118
119 qcom,panel-supply-entry@1 {
120 reg = <1>;
121 qcom,supply-name = "vdda-3p3";
122 qcom,supply-min-voltage = <3300000>;
123 qcom,supply-max-voltage = <3300000>;
124 qcom,supply-enable-load = <13200>;
125 qcom,supply-disable-load = <80>;
126 };
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]127 };
128
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]129 dsi_dual_nt35597_truly_video_display: qcom,dsi-display@0 {
130 compatible = "qcom,dsi-display";
131 label = "dsi_dual_nt35597_truly_video_display";
132 qcom,display-type = "primary";
133
134 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
135 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
136 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
137 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
138 clock-names = "src_byte_clk", "src_pixel_clk";
139
140 pinctrl-names = "panel_active", "panel_suspend";
141 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
142 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
143 qcom,platform-reset-gpio = <&tlmm 75 0>;
144 qcom,panel-mode-gpio = <&tlmm 76 0>;
145
146 qcom,dsi-panel = <&dsi_dual_nt35597_truly_video>;
147 vddio-supply = <&pm660_l11>;
148 lab-supply = <&lcdb_ldo_vreg>;
149 ibb-supply = <&lcdb_ncp_vreg>;
150 };
151
152 dsi_dual_nt35597_truly_cmd_display: qcom,dsi-display@1 {
153 compatible = "qcom,dsi-display";
154 label = "dsi_dual_nt35597_truly_cmd_display";
155 qcom,display-type = "primary";
156
157 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
158 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
159 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
160 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
161 clock-names = "src_byte_clk", "src_pixel_clk";
162
163 pinctrl-names = "panel_active", "panel_suspend";
164 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
165 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
166 qcom,platform-te-gpio = <&tlmm 10 0>;
167 qcom,platform-reset-gpio = <&tlmm 75 0>;
168 qcom,panel-mode-gpio = <&tlmm 76 0>;
169
170 qcom,dsi-panel = <&dsi_dual_nt35597_truly_cmd>;
171 vddio-supply = <&pm660_l11>;
172 lab-supply = <&lcdb_ldo_vreg>;
173 ibb-supply = <&lcdb_ncp_vreg>;
174 };
175
176 dsi_nt35597_truly_dsc_cmd_display: qcom,dsi-display@2 {
177 compatible = "qcom,dsi-display";
178 label = "dsi_nt35597_truly_dsc_cmd_display";
179 qcom,display-type = "primary";
180
181 qcom,dsi-ctrl = <&mdss_dsi1>;
182 qcom,dsi-phy = <&mdss_dsi_phy1>;
183 clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
184 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;
185 clock-names = "src_byte_clk", "src_pixel_clk";
186
187 pinctrl-names = "panel_active", "panel_suspend";
188 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
189 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
190 qcom,platform-te-gpio = <&tlmm 10 0>;
191 qcom,platform-reset-gpio = <&tlmm 75 0>;
192 qcom,panel-mode-gpio = <&tlmm 76 0>;
193
194 qcom,dsi-panel = <&dsi_nt35597_truly_dsc_cmd>;
195 vddio-supply = <&pm660_l11>;
196 lab-supply = <&lcdb_ldo_vreg>;
197 ibb-supply = <&lcdb_ncp_vreg>;
198 };
199
200 dsi_nt35597_truly_dsc_video_display: qcom,dsi-display@3 {
201 compatible = "qcom,dsi-display";
202 label = "dsi_nt35597_truly_dsc_video_display";
203 qcom,display-type = "primary";
204
205 qcom,dsi-ctrl = <&mdss_dsi1>;
206 qcom,dsi-phy = <&mdss_dsi_phy1>;
207 clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
208 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;
209 clock-names = "src_byte_clk", "src_pixel_clk";
210
211 pinctrl-names = "panel_active", "panel_suspend";
212 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
213 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
214 qcom,platform-te-gpio = <&tlmm 10 0>;
215 qcom,platform-reset-gpio = <&tlmm 75 0>;
216 qcom,panel-mode-gpio = <&tlmm 76 0>;
217
218 qcom,dsi-panel = <&dsi_nt35597_truly_dsc_video>;
219 vddio-supply = <&pm660_l11>;
220 lab-supply = <&lcdb_ldo_vreg>;
221 ibb-supply = <&lcdb_ncp_vreg>;
222 };
223
224 dsi_sim_vid_display: qcom,dsi-display@4 {
225 compatible = "qcom,dsi-display";
226 label = "dsi_sim_vid_display";
227 qcom,display-type = "primary";
228
229 qcom,dsi-ctrl = <&mdss_dsi0>;
230 qcom,dsi-phy = <&mdss_dsi_phy0>;
231 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
232 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
233 clock-names = "src_byte_clk", "src_pixel_clk";
234
235 pinctrl-names = "panel_active", "panel_suspend";
236 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
237 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
238
239 qcom,dsi-panel = <&dsi_sim_vid>;
240 };
241
242 dsi_dual_sim_vid_display: qcom,dsi-display@5 {
243 compatible = "qcom,dsi-display";
244 label = "dsi_dual_sim_vid_display";
245 qcom,display-type = "primary";
246
247 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
248 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
249 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
250 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
251 clock-names = "src_byte_clk", "src_pixel_clk";
252
253 pinctrl-names = "panel_active", "panel_suspend";
254 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
255 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
256
257 qcom,dsi-panel = <&dsi_dual_sim_vid>;
258 };
259
260 dsi_sim_cmd_display: qcom,dsi-display@6 {
261 compatible = "qcom,dsi-display";
262 label = "dsi_sim_cmd_display";
263 qcom,display-type = "primary";
264
265 qcom,dsi-ctrl = <&mdss_dsi0>;
266 qcom,dsi-phy = <&mdss_dsi_phy0>;
267 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
268 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
269 clock-names = "src_byte_clk", "src_pixel_clk";
270
271 pinctrl-names = "panel_active", "panel_suspend";
272 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
273 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
274
275 qcom,dsi-panel = <&dsi_sim_cmd>;
276 };
277
278 dsi_dual_sim_cmd_display: qcom,dsi-display@7 {
279 compatible = "qcom,dsi-display";
280 label = "dsi_dual_sim_cmd_display";
281 qcom,display-type = "primary";
282
283 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
284 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
285 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
286 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
287 clock-names = "src_byte_clk", "src_pixel_clk";
288
289 pinctrl-names = "panel_active", "panel_suspend";
290 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
291 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
292
293 qcom,dsi-panel = <&dsi_dual_sim_cmd>;
294 };
295
296 dsi_sim_dsc_375_cmd_display: qcom,dsi-display@8 {
297 compatible = "qcom,dsi-display";
298 label = "dsi_sim_dsc_375_cmd_display";
299 qcom,display-type = "primary";
300
301 qcom,dsi-ctrl = <&mdss_dsi0>;
302 qcom,dsi-phy = <&mdss_dsi_phy0>;
303 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
304 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
305 clock-names = "src_byte_clk", "src_pixel_clk";
306
307 pinctrl-names = "panel_active", "panel_suspend";
308 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
309 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
310
311 qcom,dsi-panel = <&dsi_sim_dsc_375_cmd>;
312 };
313
314 dsi_dual_sim_dsc_375_cmd_display: qcom,dsi-display@9 {
315 compatible = "qcom,dsi-display";
316 label = "dsi_dual_sim_dsc_375_cmd_display";
317 qcom,display-type = "primary";
318
319 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
320 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
321 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
322 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
323 clock-names = "src_byte_clk", "src_pixel_clk";
324
325 pinctrl-names = "panel_active", "panel_suspend";
326 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
327 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
328
329 qcom,dsi-panel = <&dsi_dual_sim_dsc_375_cmd>;
330 };
331
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]332 dsi_dual_nt35597_video_display: qcom,dsi-display@10 {
333 compatible = "qcom,dsi-display";
334 label = "dsi_dual_nt35597_video_display";
335 qcom,display-type = "primary";
336
337 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
338 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
339 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
340 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
341 clock-names = "src_byte_clk", "src_pixel_clk";
342
343 pinctrl-names = "panel_active", "panel_suspend";
344 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
345 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
346 qcom,platform-reset-gpio = <&tlmm 75 0>;
347 qcom,panel-mode-gpio = <&tlmm 76 0>;
348
349 qcom,dsi-panel = <&dsi_dual_nt35597_video>;
350 vddio-supply = <&pm660_l11>;
351 lab-supply = <&lcdb_ldo_vreg>;
352 ibb-supply = <&lcdb_ncp_vreg>;
353 };
354
355 dsi_dual_nt35597_cmd_display: qcom,dsi-display@11 {
356 compatible = "qcom,dsi-display";
357 label = "dsi_dual_nt35597_cmd_display";
358 qcom,display-type = "primary";
359
360 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
361 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
362 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
363 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
364 clock-names = "src_byte_clk", "src_pixel_clk";
365
366 pinctrl-names = "panel_active", "panel_suspend";
367 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
368 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
369 qcom,platform-reset-gpio = <&tlmm 75 0>;
370 qcom,panel-mode-gpio = <&tlmm 76 0>;
371
372 qcom,dsi-panel = <&dsi_dual_nt35597_cmd>;
373 vddio-supply = <&pm660_l11>;
374 lab-supply = <&lcdb_ldo_vreg>;
375 ibb-supply = <&lcdb_ncp_vreg>;
376 };
377
378 dsi_rm67195_amoled_fhd_cmd_display: qcom,dsi-display@12 {
379 compatible = "qcom,dsi-display";
380 label = "dsi_rm67195_amoled_fhd_cmd_display";
381 qcom,display-type = "primary";
382
383 qcom,dsi-ctrl = <&mdss_dsi0>;
384 qcom,dsi-phy = <&mdss_dsi_phy0>;
385 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
386 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
387 clock-names = "src_byte_clk", "src_pixel_clk";
388
389 pinctrl-names = "panel_active", "panel_suspend";
390 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
391 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
392 qcom,platform-te-gpio = <&tlmm 10 0>;
393 qcom,platform-reset-gpio = <&tlmm 75 0>;
394
395 qcom,dsi-panel = <&dsi_rm67195_amoled_fhd_cmd>;
396 vddio-supply = <&pm660_l11>;
Vishnuvardhan Prodduturid5fb0802017-11-08 14:49:31 +0530[diff] [blame]397 vdda-3p3-supply = <&pm660l_l6>;
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]398 };
399
400 dsi_nt35695b_truly_fhd_video_display: qcom,dsi-display@13 {
401 compatible = "qcom,dsi-display";
402 label = "dsi_nt35695b_truly_fhd_video_display";
403 qcom,display-type = "primary";
404
405 qcom,dsi-ctrl = <&mdss_dsi0>;
406 qcom,dsi-phy = <&mdss_dsi_phy0>;
407 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
408 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
409 clock-names = "src_byte_clk", "src_pixel_clk";
410
411 pinctrl-names = "panel_active", "panel_suspend";
412 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
413 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
414 qcom,platform-reset-gpio = <&tlmm 75 0>;
415
416 qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_video>;
417 vddio-supply = <&pm660_l11>;
418 lab-supply = <&lcdb_ldo_vreg>;
419 ibb-supply = <&lcdb_ncp_vreg>;
420 };
421
422 dsi_nt35695b_truly_fhd_cmd_display: qcom,dsi-display@14 {
423 compatible = "qcom,dsi-display";
424 label = "dsi_nt35695b_truly_fhd_cmd_display";
425 qcom,display-type = "primary";
426
427 qcom,dsi-ctrl = <&mdss_dsi0>;
428 qcom,dsi-phy = <&mdss_dsi_phy0>;
429 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
430 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
431 clock-names = "src_byte_clk", "src_pixel_clk";
432
433 pinctrl-names = "panel_active", "panel_suspend";
434 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
435 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
436 qcom,platform-te-gpio = <&tlmm 10 0>;
437 qcom,platform-reset-gpio = <&tlmm 75 0>;
438
439 qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_cmd>;
440 vddio-supply = <&pm660_l11>;
441 lab-supply = <&lcdb_ldo_vreg>;
442 ibb-supply = <&lcdb_ncp_vreg>;
443 };
444
Yuan Zhao3e1868e2017-09-25 16:47:29 +0800[diff] [blame]445 dsi_dual_nt36850_truly_cmd_display: qcom,dsi-display@15 {
446 compatible = "qcom,dsi-display";
447 label = "dsi_dual_nt36850_truly_cmd_display";
448 qcom,display-type = "primary";
449
450 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
451 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
452 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
453 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
454 clock-names = "src_byte_clk", "src_pixel_clk";
455
456 pinctrl-names = "panel_active", "panel_suspend";
457 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
458 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
459 qcom,platform-te-gpio = <&tlmm 10 0>;
460 qcom,platform-reset-gpio = <&tlmm 75 0>;
461
462 qcom,dsi-panel = <&dsi_dual_nt36850_truly_cmd>;
463 vddio-supply = <&pm660_l11>;
464 lab-supply = <&lcdb_ldo_vreg>;
465 ibb-supply = <&lcdb_ncp_vreg>;
466 };
467
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]468 sde_wb: qcom,wb-display@0 {
469 compatible = "qcom,wb-display";
470 cell-index = <0>;
471 label = "wb_display";
472 };
473
474 ext_disp: qcom,msm-ext-disp {
475 compatible = "qcom,msm-ext-disp";
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]476
477 ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
478 compatible = "qcom,msm-ext-disp-audio-codec-rx";
479 };
480 };
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]481};
482
483&sde_dp {
Padmanabhan Komanduruf3838e42017-10-20 12:50:47 +0530[diff] [blame]484 qcom,dp-usbpd-detection = <&pm660_pdphy>;
485 qcom,ext-disp = <&ext_disp>;
486
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]487 pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
488 pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>;
489 pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>;
490 qcom,aux-en-gpio = <&tlmm 50 0>;
491 qcom,aux-sel-gpio = <&tlmm 40 0>;
492 qcom,usbplug-cc-gpio = <&tlmm 38 0>;
493};
494
495&mdss_mdp {
Padmanabhan Komandurud03f38f2017-10-10 15:34:41 +0530[diff] [blame]496 connectors = <&sde_rscc &sde_wb &sde_dp>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]497};
498
499&dsi_dual_nt35597_truly_video {
500 qcom,mdss-dsi-t-clk-post = <0x0D>;
501 qcom,mdss-dsi-t-clk-pre = <0x2D>;
Raviteja Tamatam52a580f2017-10-31 11:29:06 +0530[diff] [blame]502 qcom,mdss-dsi-min-refresh-rate = <53>;
503 qcom,mdss-dsi-max-refresh-rate = <60>;
504 qcom,mdss-dsi-pan-enable-dynamic-fps;
505 qcom,mdss-dsi-pan-fps-update =
506 "dfps_immediate_porch_mode_vfp";
Sandeep Panda8d29a7a2017-11-13 10:30:54 +0530[diff] [blame]507 qcom,esd-check-enabled;
508 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
509 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
510 qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
511 qcom,mdss-dsi-panel-status-value = <0x9c>;
512 qcom,mdss-dsi-panel-on-check-value = <0x9c>;
513 qcom,mdss-dsi-panel-status-read-length = <1>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]514 qcom,mdss-dsi-display-timings {
515 timing@0{
516 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
517 07 05 03 04 00];
518 qcom,display-topology = <2 0 2>,
519 <1 0 2>;
520 qcom,default-topology-index = <0>;
521 };
522 };
523};
524
525&dsi_dual_nt35597_truly_cmd {
526 qcom,mdss-dsi-t-clk-post = <0x0D>;
527 qcom,mdss-dsi-t-clk-pre = <0x2D>;
Sandeep Panda5d8d7242017-11-01 12:15:33 +0530[diff] [blame]528 qcom,ulps-enabled;
Sandeep Panda8d29a7a2017-11-13 10:30:54 +0530[diff] [blame]529 qcom,esd-check-enabled;
530 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
531 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
532 qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
533 qcom,mdss-dsi-panel-status-value = <0x9c>;
534 qcom,mdss-dsi-panel-on-check-value = <0x9c>;
535 qcom,mdss-dsi-panel-status-read-length = <1>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]536 qcom,mdss-dsi-display-timings {
537 timing@0{
538 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
539 07 05 03 04 00];
540 qcom,display-topology = <2 0 2>,
541 <1 0 2>;
542 qcom,default-topology-index = <0>;
Sandeep Pandae34dcd72017-11-23 18:33:00 +0530[diff] [blame]543 qcom,partial-update-enabled = "single_roi";
544 qcom,panel-roi-alignment = <720 128 720 128 1440 128>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]545 };
546 };
547};
548
549&dsi_nt35597_truly_dsc_cmd {
550 qcom,mdss-dsi-t-clk-post = <0x0b>;
551 qcom,mdss-dsi-t-clk-pre = <0x23>;
Sandeep Panda5d8d7242017-11-01 12:15:33 +0530[diff] [blame]552 qcom,ulps-enabled;
Sandeep Panda8d29a7a2017-11-13 10:30:54 +0530[diff] [blame]553 qcom,esd-check-enabled;
554 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
555 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
556 qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
557 qcom,mdss-dsi-panel-status-value = <0x9c>;
558 qcom,mdss-dsi-panel-on-check-value = <0x9c>;
559 qcom,mdss-dsi-panel-status-read-length = <1>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]560 qcom,mdss-dsi-display-timings {
561 timing@0{
562 qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
563 05 03 03 04 00];
564 qcom,display-topology = <1 1 1>,
565 <2 2 1>, /* dsc merge */
566 <2 1 1>; /* 3d mux */
567 qcom,default-topology-index = <1>;
568 };
569 };
570};
571
572&dsi_nt35597_truly_dsc_video {
573 qcom,mdss-dsi-t-clk-post = <0x0b>;
574 qcom,mdss-dsi-t-clk-pre = <0x23>;
Raviteja Tamatam52a580f2017-10-31 11:29:06 +0530[diff] [blame]575 qcom,mdss-dsi-min-refresh-rate = <53>;
576 qcom,mdss-dsi-max-refresh-rate = <60>;
577 qcom,mdss-dsi-pan-enable-dynamic-fps;
578 qcom,mdss-dsi-pan-fps-update =
579 "dfps_immediate_porch_mode_vfp";
Sandeep Panda8d29a7a2017-11-13 10:30:54 +0530[diff] [blame]580 qcom,esd-check-enabled;
581 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
582 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
583 qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
584 qcom,mdss-dsi-panel-status-value = <0x9c>;
585 qcom,mdss-dsi-panel-on-check-value = <0x9c>;
586 qcom,mdss-dsi-panel-status-read-length = <1>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]587 qcom,mdss-dsi-display-timings {
588 timing@0{
589 qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
590 04 03 03 04 00];
591 qcom,display-topology = <1 1 1>,
592 <2 2 1>, /* dsc merge */
593 <2 1 1>; /* 3d mux */
594 qcom,default-topology-index = <1>;
595 };
596 };
597};
598
599&dsi_sim_vid {
600 qcom,mdss-dsi-t-clk-post = <0x0d>;
601 qcom,mdss-dsi-t-clk-pre = <0x2d>;
602 qcom,mdss-dsi-display-timings {
603 timing@0{
604 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
605 07 05 03 04 00];
606 qcom,display-topology = <1 0 1>,
607 <2 0 1>;
608 qcom,default-topology-index = <0>;
609 };
610 };
611};
612
613&dsi_dual_sim_vid {
614 qcom,mdss-dsi-t-clk-post = <0x0d>;
615 qcom,mdss-dsi-t-clk-pre = <0x2d>;
616 qcom,mdss-dsi-display-timings {
617 timing@0{
618 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
619 07 05 03 04 00];
620 qcom,display-topology = <2 0 2>,
621 <1 0 2>;
622 qcom,default-topology-index = <0>;
623 };
624 };
625};
626
627&dsi_sim_cmd {
Sandeep Panda665a5352017-12-22 16:08:48 +0530[diff] [blame^]628 qcom,mdss-dsi-t-clk-post = <0x0c>;
629 qcom,mdss-dsi-t-clk-pre = <0x29>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]630 qcom,mdss-dsi-display-timings {
631 timing@0{
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]632 qcom,display-topology = <1 0 1>,
Sandeep Panda665a5352017-12-22 16:08:48 +0530[diff] [blame^]633 <2 2 1>;
634 qcom,default-topology-index = <1>;
635 qcom,panel-roi-alignment = <720 40 720 40 720 40>;
636 qcom,partial-update-enabled = "single_roi";
637 qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 22 20 07
638 07 04 03 04 00];
639 };
640 timing@1{
641 qcom,display-topology = <1 0 1>,
642 <2 2 1>;
643 qcom,default-topology-index = <1>;
644 qcom,panel-roi-alignment = <540 40 540 40 540 40>;
645 qcom,partial-update-enabled = "single_roi";
646 qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 22 20 07
647 07 04 03 04 00];
648 };
649 timing@2{
650 qcom,display-topology = <1 0 1>,
651 <2 2 1>;
652 qcom,default-topology-index = <1>;
653 qcom,panel-roi-alignment = <360 40 360 40 360 40>;
654 qcom,partial-update-enabled = "single_roi";
655 qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 22 20 07
656 07 04 03 04 00];
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]657 };
658 };
659};
660
661&dsi_dual_sim_cmd {
662 qcom,mdss-dsi-t-clk-post = <0x0d>;
663 qcom,mdss-dsi-t-clk-pre = <0x2d>;
664 qcom,mdss-dsi-display-timings {
665 timing@0{
666 qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09
667 09 06 03 04 00];
668 qcom,display-topology = <2 0 2>;
669 qcom,default-topology-index = <0>;
670 };
671 timing@1{
672 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
673 07 05 03 04 00];
674 qcom,display-topology = <2 0 2>,
675 <1 0 2>;
676 qcom,default-topology-index = <0>;
677 };
678 timing@2{
679 qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06
680 06 04 03 04 00];
681 qcom,display-topology = <2 0 2>;
682 qcom,default-topology-index = <0>;
683 };
684 };
685};
686
687&dsi_sim_dsc_375_cmd {
688 qcom,mdss-dsi-t-clk-post = <0x0d>;
689 qcom,mdss-dsi-t-clk-pre = <0x2d>;
690 qcom,mdss-dsi-display-timings {
691 timing@0 { /* 1080p */
692 qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07
693 07 04 03 04 00];
694 qcom,display-topology = <1 1 1>;
695 qcom,default-topology-index = <0>;
696 };
697 timing@1 { /* qhd */
698 qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
699 05 03 03 04 00];
700 qcom,display-topology = <1 1 1>,
701 <2 2 1>, /* dsc merge */
702 <2 1 1>; /* 3d mux */
703 qcom,default-topology-index = <0>;
704 };
705 };
706};
707
708&dsi_dual_sim_dsc_375_cmd {
709 qcom,mdss-dsi-t-clk-post = <0x0d>;
710 qcom,mdss-dsi-t-clk-pre = <0x2d>;
711 qcom,mdss-dsi-display-timings {
712 timing@0 { /* qhd */
713 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
714 07 05 03 04 00];
715 qcom,display-topology = <2 2 2>;
716 qcom,default-topology-index = <0>;
717 };
718 timing@1 { /* 4k */
719 qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06
720 06 04 03 04 00];
721 qcom,display-topology = <2 2 2>;
722 qcom,default-topology-index = <0>;
723 };
724 };
725};
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]726
727&dsi_dual_nt35597_video {
728 qcom,mdss-dsi-t-clk-post = <0x0d>;
729 qcom,mdss-dsi-t-clk-pre = <0x2d>;
730 qcom,mdss-dsi-display-timings {
731 timing@0 {
732 qcom,mdss-dsi-panel-timings = [00 1c 08 07 23 22 07 07
733 05 03 04 00];
734 qcom,display-topology = <2 0 2>,
735 <1 0 2>;
736 qcom,default-topology-index = <0>;
737 };
738 };
739};
740
741&dsi_dual_nt35597_cmd {
742 qcom,mdss-dsi-t-clk-post = <0x0d>;
743 qcom,mdss-dsi-t-clk-pre = <0x2d>;
Sandeep Panda5d8d7242017-11-01 12:15:33 +0530[diff] [blame]744 qcom,ulps-enabled;
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]745 qcom,mdss-dsi-display-timings {
746 timing@0 {
747 qcom,mdss-dsi-panel-timings = [00 1c 08 07 23 22 07 07
748 05 03 04 00];
749 qcom,display-topology = <2 0 2>,
750 <1 0 2>;
751 qcom,default-topology-index = <0>;
Sandeep Pandae34dcd72017-11-23 18:33:00 +0530[diff] [blame]752 qcom,partial-update-enabled = "single_roi";
753 qcom,panel-roi-alignment = <720 128 720 128 1440 128>;
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]754 };
755 };
756};
757
758&dsi_rm67195_amoled_fhd_cmd {
759 qcom,mdss-dsi-t-clk-post = <0x07>;
760 qcom,mdss-dsi-t-clk-pre = <0x1c>;
761 qcom,mdss-dsi-display-timings {
762 timing@0 {
763 qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c
764 05 07 05 03 04 00];
765 qcom,display-topology = <1 0 1>;
766 qcom,default-topology-index = <0>;
767 };
768 };
769};
770
771&dsi_nt35695b_truly_fhd_video {
772 qcom,mdss-dsi-t-clk-post = <0x07>;
773 qcom,mdss-dsi-t-clk-pre = <0x1c>;
Raviteja Tamatamd5ca1b82017-11-30 13:23:54 +0530[diff] [blame]774 qcom,mdss-dsi-min-refresh-rate = <48>;
775 qcom,mdss-dsi-max-refresh-rate = <60>;
776 qcom,mdss-dsi-pan-enable-dynamic-fps;
777 qcom,mdss-dsi-pan-fps-update =
778 "dfps_immediate_porch_mode_vfp";
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]779 qcom,mdss-dsi-display-timings {
780 timing@0 {
781 qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c
782 05 07 05 03 04 00];
783 qcom,display-topology = <1 0 1>;
784 qcom,default-topology-index = <0>;
785 };
786 };
787};
788
789&dsi_nt35695b_truly_fhd_cmd {
790 qcom,mdss-dsi-t-clk-post = <0x07>;
791 qcom,mdss-dsi-t-clk-pre = <0x1c>;
Sandeep Panda5d8d7242017-11-01 12:15:33 +0530[diff] [blame]792 qcom,ulps-enabled;
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]793 qcom,mdss-dsi-display-timings {
794 timing@0 {
795 qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c
796 05 07 05 03 04 00];
797 qcom,display-topology = <1 0 1>;
798 qcom,default-topology-index = <0>;
799 };
800 };
801};
Yuan Zhao3e1868e2017-09-25 16:47:29 +0800[diff] [blame]802
803&dsi_dual_nt36850_truly_cmd {
804 qcom,mdss-dsi-t-clk-post = <0x0E>;
805 qcom,mdss-dsi-t-clk-pre = <0x30>;
806 qcom,mdss-dsi-display-timings {
807 timing@0{
808 qcom,mdss-dsi-panel-phy-timings = [00 1f 08 08 24 23 08
809 08 05 03 04 00];
810 qcom,display-topology = <2 0 2>,
811 <1 0 2>;
812 qcom,default-topology-index = <0>;
813 };
814 };
815};