Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 1 | /* |
| 2 | * SuperH Timer Support - MTU2 |
| 3 | * |
| 4 | * Copyright (C) 2009 Magnus Damm |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 18 | */ |
| 19 | |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/spinlock.h> |
| 23 | #include <linux/interrupt.h> |
| 24 | #include <linux/ioport.h> |
| 25 | #include <linux/delay.h> |
| 26 | #include <linux/io.h> |
| 27 | #include <linux/clk.h> |
| 28 | #include <linux/irq.h> |
| 29 | #include <linux/err.h> |
| 30 | #include <linux/clockchips.h> |
Paul Mundt | 46a12f7 | 2009-05-03 17:57:17 +0900 | [diff] [blame] | 31 | #include <linux/sh_timer.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 32 | #include <linux/slab.h> |
Paul Gortmaker | 7deeab5 | 2011-07-03 13:36:22 -0400 | [diff] [blame] | 33 | #include <linux/module.h> |
Rafael J. Wysocki | 57d1337 | 2012-03-13 22:40:14 +0100 | [diff] [blame] | 34 | #include <linux/pm_domain.h> |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 35 | #include <linux/pm_runtime.h> |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 36 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 37 | struct sh_mtu2_device; |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 38 | |
| 39 | struct sh_mtu2_channel { |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 40 | struct sh_mtu2_device *mtu; |
Laurent Pinchart | d2b9317 | 2014-03-04 14:17:26 +0100 | [diff] [blame] | 41 | unsigned int index; |
Laurent Pinchart | da90a1c | 2014-03-04 14:04:24 +0100 | [diff] [blame] | 42 | |
| 43 | void __iomem *base; |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 44 | int irq; |
Laurent Pinchart | da90a1c | 2014-03-04 14:04:24 +0100 | [diff] [blame] | 45 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 46 | struct clock_event_device ced; |
| 47 | }; |
| 48 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 49 | struct sh_mtu2_device { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 50 | struct platform_device *pdev; |
| 51 | |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 52 | void __iomem *mapbase; |
| 53 | struct clk *clk; |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 54 | |
Laurent Pinchart | c54ccb4 | 2014-03-04 14:23:00 +0100 | [diff] [blame] | 55 | struct sh_mtu2_channel *channels; |
| 56 | unsigned int num_channels; |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 57 | |
| 58 | bool legacy; |
| 59 | bool has_clockevent; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 60 | }; |
| 61 | |
Paul Mundt | 50393a9 | 2012-05-25 13:38:54 +0900 | [diff] [blame] | 62 | static DEFINE_RAW_SPINLOCK(sh_mtu2_lock); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 63 | |
| 64 | #define TSTR -1 /* shared register */ |
| 65 | #define TCR 0 /* channel register */ |
| 66 | #define TMDR 1 /* channel register */ |
| 67 | #define TIOR 2 /* channel register */ |
| 68 | #define TIER 3 /* channel register */ |
| 69 | #define TSR 4 /* channel register */ |
| 70 | #define TCNT 5 /* channel register */ |
| 71 | #define TGR 6 /* channel register */ |
| 72 | |
Laurent Pinchart | f992c24 | 2014-03-04 15:16:25 +0100 | [diff] [blame] | 73 | #define TCR_CCLR_NONE (0 << 5) |
| 74 | #define TCR_CCLR_TGRA (1 << 5) |
| 75 | #define TCR_CCLR_TGRB (2 << 5) |
| 76 | #define TCR_CCLR_SYNC (3 << 5) |
| 77 | #define TCR_CCLR_TGRC (5 << 5) |
| 78 | #define TCR_CCLR_TGRD (6 << 5) |
| 79 | #define TCR_CCLR_MASK (7 << 5) |
| 80 | #define TCR_CKEG_RISING (0 << 3) |
| 81 | #define TCR_CKEG_FALLING (1 << 3) |
| 82 | #define TCR_CKEG_BOTH (2 << 3) |
| 83 | #define TCR_CKEG_MASK (3 << 3) |
| 84 | /* Values 4 to 7 are channel-dependent */ |
| 85 | #define TCR_TPSC_P1 (0 << 0) |
| 86 | #define TCR_TPSC_P4 (1 << 0) |
| 87 | #define TCR_TPSC_P16 (2 << 0) |
| 88 | #define TCR_TPSC_P64 (3 << 0) |
| 89 | #define TCR_TPSC_CH0_TCLKA (4 << 0) |
| 90 | #define TCR_TPSC_CH0_TCLKB (5 << 0) |
| 91 | #define TCR_TPSC_CH0_TCLKC (6 << 0) |
| 92 | #define TCR_TPSC_CH0_TCLKD (7 << 0) |
| 93 | #define TCR_TPSC_CH1_TCLKA (4 << 0) |
| 94 | #define TCR_TPSC_CH1_TCLKB (5 << 0) |
| 95 | #define TCR_TPSC_CH1_P256 (6 << 0) |
| 96 | #define TCR_TPSC_CH1_TCNT2 (7 << 0) |
| 97 | #define TCR_TPSC_CH2_TCLKA (4 << 0) |
| 98 | #define TCR_TPSC_CH2_TCLKB (5 << 0) |
| 99 | #define TCR_TPSC_CH2_TCLKC (6 << 0) |
| 100 | #define TCR_TPSC_CH2_P1024 (7 << 0) |
| 101 | #define TCR_TPSC_CH34_P256 (4 << 0) |
| 102 | #define TCR_TPSC_CH34_P1024 (5 << 0) |
| 103 | #define TCR_TPSC_CH34_TCLKA (6 << 0) |
| 104 | #define TCR_TPSC_CH34_TCLKB (7 << 0) |
| 105 | #define TCR_TPSC_MASK (7 << 0) |
| 106 | |
| 107 | #define TMDR_BFE (1 << 6) |
| 108 | #define TMDR_BFB (1 << 5) |
| 109 | #define TMDR_BFA (1 << 4) |
| 110 | #define TMDR_MD_NORMAL (0 << 0) |
| 111 | #define TMDR_MD_PWM_1 (2 << 0) |
| 112 | #define TMDR_MD_PWM_2 (3 << 0) |
| 113 | #define TMDR_MD_PHASE_1 (4 << 0) |
| 114 | #define TMDR_MD_PHASE_2 (5 << 0) |
| 115 | #define TMDR_MD_PHASE_3 (6 << 0) |
| 116 | #define TMDR_MD_PHASE_4 (7 << 0) |
| 117 | #define TMDR_MD_PWM_SYNC (8 << 0) |
| 118 | #define TMDR_MD_PWM_COMP_CREST (13 << 0) |
| 119 | #define TMDR_MD_PWM_COMP_TROUGH (14 << 0) |
| 120 | #define TMDR_MD_PWM_COMP_BOTH (15 << 0) |
| 121 | #define TMDR_MD_MASK (15 << 0) |
| 122 | |
| 123 | #define TIOC_IOCH(n) ((n) << 4) |
| 124 | #define TIOC_IOCL(n) ((n) << 0) |
| 125 | #define TIOR_OC_RETAIN (0 << 0) |
| 126 | #define TIOR_OC_0_CLEAR (1 << 0) |
| 127 | #define TIOR_OC_0_SET (2 << 0) |
| 128 | #define TIOR_OC_0_TOGGLE (3 << 0) |
| 129 | #define TIOR_OC_1_CLEAR (5 << 0) |
| 130 | #define TIOR_OC_1_SET (6 << 0) |
| 131 | #define TIOR_OC_1_TOGGLE (7 << 0) |
| 132 | #define TIOR_IC_RISING (8 << 0) |
| 133 | #define TIOR_IC_FALLING (9 << 0) |
| 134 | #define TIOR_IC_BOTH (10 << 0) |
| 135 | #define TIOR_IC_TCNT (12 << 0) |
| 136 | #define TIOR_MASK (15 << 0) |
| 137 | |
| 138 | #define TIER_TTGE (1 << 7) |
| 139 | #define TIER_TTGE2 (1 << 6) |
| 140 | #define TIER_TCIEU (1 << 5) |
| 141 | #define TIER_TCIEV (1 << 4) |
| 142 | #define TIER_TGIED (1 << 3) |
| 143 | #define TIER_TGIEC (1 << 2) |
| 144 | #define TIER_TGIEB (1 << 1) |
| 145 | #define TIER_TGIEA (1 << 0) |
| 146 | |
| 147 | #define TSR_TCFD (1 << 7) |
| 148 | #define TSR_TCFU (1 << 5) |
| 149 | #define TSR_TCFV (1 << 4) |
| 150 | #define TSR_TGFD (1 << 3) |
| 151 | #define TSR_TGFC (1 << 2) |
| 152 | #define TSR_TGFB (1 << 1) |
| 153 | #define TSR_TGFA (1 << 0) |
| 154 | |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 155 | static unsigned long mtu2_reg_offs[] = { |
| 156 | [TCR] = 0, |
| 157 | [TMDR] = 1, |
| 158 | [TIOR] = 2, |
| 159 | [TIER] = 4, |
| 160 | [TSR] = 5, |
| 161 | [TCNT] = 6, |
| 162 | [TGR] = 8, |
| 163 | }; |
| 164 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 165 | static inline unsigned long sh_mtu2_read(struct sh_mtu2_channel *ch, int reg_nr) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 166 | { |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 167 | unsigned long offs; |
| 168 | |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 169 | if (reg_nr == TSTR) { |
| 170 | if (ch->mtu->legacy) |
| 171 | return ioread8(ch->mtu->mapbase); |
| 172 | else |
| 173 | return ioread8(ch->mtu->mapbase + 0x280); |
| 174 | } |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 175 | |
| 176 | offs = mtu2_reg_offs[reg_nr]; |
| 177 | |
| 178 | if ((reg_nr == TCNT) || (reg_nr == TGR)) |
Laurent Pinchart | da90a1c | 2014-03-04 14:04:24 +0100 | [diff] [blame] | 179 | return ioread16(ch->base + offs); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 180 | else |
Laurent Pinchart | da90a1c | 2014-03-04 14:04:24 +0100 | [diff] [blame] | 181 | return ioread8(ch->base + offs); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 182 | } |
| 183 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 184 | static inline void sh_mtu2_write(struct sh_mtu2_channel *ch, int reg_nr, |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 185 | unsigned long value) |
| 186 | { |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 187 | unsigned long offs; |
| 188 | |
| 189 | if (reg_nr == TSTR) { |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 190 | if (ch->mtu->legacy) |
| 191 | return iowrite8(value, ch->mtu->mapbase); |
| 192 | else |
| 193 | return iowrite8(value, ch->mtu->mapbase + 0x280); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 194 | } |
| 195 | |
| 196 | offs = mtu2_reg_offs[reg_nr]; |
| 197 | |
| 198 | if ((reg_nr == TCNT) || (reg_nr == TGR)) |
Laurent Pinchart | da90a1c | 2014-03-04 14:04:24 +0100 | [diff] [blame] | 199 | iowrite16(value, ch->base + offs); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 200 | else |
Laurent Pinchart | da90a1c | 2014-03-04 14:04:24 +0100 | [diff] [blame] | 201 | iowrite8(value, ch->base + offs); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 202 | } |
| 203 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 204 | static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 205 | { |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 206 | unsigned long flags, value; |
| 207 | |
| 208 | /* start stop register shared by multiple timer channels */ |
Paul Mundt | 50393a9 | 2012-05-25 13:38:54 +0900 | [diff] [blame] | 209 | raw_spin_lock_irqsave(&sh_mtu2_lock, flags); |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 210 | value = sh_mtu2_read(ch, TSTR); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 211 | |
| 212 | if (start) |
Laurent Pinchart | d2b9317 | 2014-03-04 14:17:26 +0100 | [diff] [blame] | 213 | value |= 1 << ch->index; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 214 | else |
Laurent Pinchart | d2b9317 | 2014-03-04 14:17:26 +0100 | [diff] [blame] | 215 | value &= ~(1 << ch->index); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 216 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 217 | sh_mtu2_write(ch, TSTR, value); |
Paul Mundt | 50393a9 | 2012-05-25 13:38:54 +0900 | [diff] [blame] | 218 | raw_spin_unlock_irqrestore(&sh_mtu2_lock, flags); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 219 | } |
| 220 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 221 | static int sh_mtu2_enable(struct sh_mtu2_channel *ch) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 222 | { |
Laurent Pinchart | f92d62f5 | 2014-03-04 12:59:54 +0100 | [diff] [blame] | 223 | unsigned long periodic; |
| 224 | unsigned long rate; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 225 | int ret; |
| 226 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 227 | pm_runtime_get_sync(&ch->mtu->pdev->dev); |
| 228 | dev_pm_syscore_device(&ch->mtu->pdev->dev, true); |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 229 | |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 230 | /* enable clock */ |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 231 | ret = clk_enable(ch->mtu->clk); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 232 | if (ret) { |
Laurent Pinchart | d2b9317 | 2014-03-04 14:17:26 +0100 | [diff] [blame] | 233 | dev_err(&ch->mtu->pdev->dev, "ch%u: cannot enable clock\n", |
| 234 | ch->index); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 235 | return ret; |
| 236 | } |
| 237 | |
| 238 | /* make sure channel is disabled */ |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 239 | sh_mtu2_start_stop_ch(ch, 0); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 240 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 241 | rate = clk_get_rate(ch->mtu->clk) / 64; |
Laurent Pinchart | f92d62f5 | 2014-03-04 12:59:54 +0100 | [diff] [blame] | 242 | periodic = (rate + HZ/2) / HZ; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 243 | |
Laurent Pinchart | f992c24 | 2014-03-04 15:16:25 +0100 | [diff] [blame] | 244 | /* |
| 245 | * "Periodic Counter Operation" |
| 246 | * Clear on TGRA compare match, divide clock by 64. |
| 247 | */ |
| 248 | sh_mtu2_write(ch, TCR, TCR_CCLR_TGRA | TCR_TPSC_P64); |
| 249 | sh_mtu2_write(ch, TIOR, TIOC_IOCH(TIOR_OC_0_CLEAR) | |
| 250 | TIOC_IOCL(TIOR_OC_0_CLEAR)); |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 251 | sh_mtu2_write(ch, TGR, periodic); |
| 252 | sh_mtu2_write(ch, TCNT, 0); |
Laurent Pinchart | f992c24 | 2014-03-04 15:16:25 +0100 | [diff] [blame] | 253 | sh_mtu2_write(ch, TMDR, TMDR_MD_NORMAL); |
| 254 | sh_mtu2_write(ch, TIER, TIER_TGIEA); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 255 | |
| 256 | /* enable channel */ |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 257 | sh_mtu2_start_stop_ch(ch, 1); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 258 | |
| 259 | return 0; |
| 260 | } |
| 261 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 262 | static void sh_mtu2_disable(struct sh_mtu2_channel *ch) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 263 | { |
| 264 | /* disable channel */ |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 265 | sh_mtu2_start_stop_ch(ch, 0); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 266 | |
| 267 | /* stop clock */ |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 268 | clk_disable(ch->mtu->clk); |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 269 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 270 | dev_pm_syscore_device(&ch->mtu->pdev->dev, false); |
| 271 | pm_runtime_put(&ch->mtu->pdev->dev); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 272 | } |
| 273 | |
| 274 | static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id) |
| 275 | { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 276 | struct sh_mtu2_channel *ch = dev_id; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 277 | |
| 278 | /* acknowledge interrupt */ |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 279 | sh_mtu2_read(ch, TSR); |
Laurent Pinchart | f992c24 | 2014-03-04 15:16:25 +0100 | [diff] [blame] | 280 | sh_mtu2_write(ch, TSR, ~TSR_TGFA); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 281 | |
| 282 | /* notify clockevent layer */ |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 283 | ch->ced.event_handler(&ch->ced); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 284 | return IRQ_HANDLED; |
| 285 | } |
| 286 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 287 | static struct sh_mtu2_channel *ced_to_sh_mtu2(struct clock_event_device *ced) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 288 | { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 289 | return container_of(ced, struct sh_mtu2_channel, ced); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 290 | } |
| 291 | |
| 292 | static void sh_mtu2_clock_event_mode(enum clock_event_mode mode, |
| 293 | struct clock_event_device *ced) |
| 294 | { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 295 | struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 296 | int disabled = 0; |
| 297 | |
| 298 | /* deal with old setting first */ |
| 299 | switch (ced->mode) { |
| 300 | case CLOCK_EVT_MODE_PERIODIC: |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 301 | sh_mtu2_disable(ch); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 302 | disabled = 1; |
| 303 | break; |
| 304 | default: |
| 305 | break; |
| 306 | } |
| 307 | |
| 308 | switch (mode) { |
| 309 | case CLOCK_EVT_MODE_PERIODIC: |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 310 | dev_info(&ch->mtu->pdev->dev, |
Laurent Pinchart | d2b9317 | 2014-03-04 14:17:26 +0100 | [diff] [blame] | 311 | "ch%u: used for periodic clock events\n", ch->index); |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 312 | sh_mtu2_enable(ch); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 313 | break; |
| 314 | case CLOCK_EVT_MODE_UNUSED: |
| 315 | if (!disabled) |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 316 | sh_mtu2_disable(ch); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 317 | break; |
| 318 | case CLOCK_EVT_MODE_SHUTDOWN: |
| 319 | default: |
| 320 | break; |
| 321 | } |
| 322 | } |
| 323 | |
Rafael J. Wysocki | cc7ad45 | 2012-08-06 01:43:41 +0200 | [diff] [blame] | 324 | static void sh_mtu2_clock_event_suspend(struct clock_event_device *ced) |
| 325 | { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 326 | pm_genpd_syscore_poweroff(&ced_to_sh_mtu2(ced)->mtu->pdev->dev); |
Rafael J. Wysocki | cc7ad45 | 2012-08-06 01:43:41 +0200 | [diff] [blame] | 327 | } |
| 328 | |
| 329 | static void sh_mtu2_clock_event_resume(struct clock_event_device *ced) |
| 330 | { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 331 | pm_genpd_syscore_poweron(&ced_to_sh_mtu2(ced)->mtu->pdev->dev); |
Rafael J. Wysocki | cc7ad45 | 2012-08-06 01:43:41 +0200 | [diff] [blame] | 332 | } |
| 333 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 334 | static void sh_mtu2_register_clockevent(struct sh_mtu2_channel *ch, |
Laurent Pinchart | 207e21a | 2014-03-04 15:19:41 +0100 | [diff] [blame] | 335 | const char *name) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 336 | { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 337 | struct clock_event_device *ced = &ch->ced; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 338 | int ret; |
| 339 | |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 340 | ced->name = name; |
| 341 | ced->features = CLOCK_EVT_FEAT_PERIODIC; |
Laurent Pinchart | 207e21a | 2014-03-04 15:19:41 +0100 | [diff] [blame] | 342 | ced->rating = 200; |
Laurent Pinchart | 3cc9504 | 2014-03-04 15:22:19 +0100 | [diff] [blame] | 343 | ced->cpumask = cpu_possible_mask; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 344 | ced->set_mode = sh_mtu2_clock_event_mode; |
Rafael J. Wysocki | cc7ad45 | 2012-08-06 01:43:41 +0200 | [diff] [blame] | 345 | ced->suspend = sh_mtu2_clock_event_suspend; |
| 346 | ced->resume = sh_mtu2_clock_event_resume; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 347 | |
Laurent Pinchart | d2b9317 | 2014-03-04 14:17:26 +0100 | [diff] [blame] | 348 | dev_info(&ch->mtu->pdev->dev, "ch%u: used for clock events\n", |
| 349 | ch->index); |
Paul Mundt | da64c2a | 2010-02-25 16:37:46 +0900 | [diff] [blame] | 350 | clockevents_register_device(ced); |
| 351 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 352 | ret = request_irq(ch->irq, sh_mtu2_interrupt, |
Laurent Pinchart | 276bee0 | 2014-02-17 11:27:49 +0100 | [diff] [blame] | 353 | IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 354 | dev_name(&ch->mtu->pdev->dev), ch); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 355 | if (ret) { |
Laurent Pinchart | d2b9317 | 2014-03-04 14:17:26 +0100 | [diff] [blame] | 356 | dev_err(&ch->mtu->pdev->dev, "ch%u: failed to request irq %d\n", |
| 357 | ch->index, ch->irq); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 358 | return; |
| 359 | } |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 360 | } |
| 361 | |
Laurent Pinchart | aa83804 | 2014-03-04 13:57:14 +0100 | [diff] [blame] | 362 | static int sh_mtu2_register(struct sh_mtu2_channel *ch, const char *name, |
Laurent Pinchart | 207e21a | 2014-03-04 15:19:41 +0100 | [diff] [blame] | 363 | bool clockevent) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 364 | { |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 365 | if (clockevent) { |
| 366 | ch->mtu->has_clockevent = true; |
Laurent Pinchart | 207e21a | 2014-03-04 15:19:41 +0100 | [diff] [blame] | 367 | sh_mtu2_register_clockevent(ch, name); |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 368 | } |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 369 | |
| 370 | return 0; |
| 371 | } |
| 372 | |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 373 | static int sh_mtu2_setup_channel(struct sh_mtu2_channel *ch, unsigned int index, |
Laurent Pinchart | 2e1a532 | 2014-03-04 13:11:23 +0100 | [diff] [blame] | 374 | struct sh_mtu2_device *mtu) |
| 375 | { |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 376 | static const unsigned int channel_offsets[] = { |
| 377 | 0x300, 0x380, 0x000, |
| 378 | }; |
| 379 | bool clockevent; |
Laurent Pinchart | 2e1a532 | 2014-03-04 13:11:23 +0100 | [diff] [blame] | 380 | |
Laurent Pinchart | 2e1a532 | 2014-03-04 13:11:23 +0100 | [diff] [blame] | 381 | ch->mtu = mtu; |
| 382 | |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 383 | if (mtu->legacy) { |
| 384 | struct sh_timer_config *cfg = mtu->pdev->dev.platform_data; |
| 385 | |
| 386 | clockevent = cfg->clockevent_rating != 0; |
| 387 | |
| 388 | ch->irq = platform_get_irq(mtu->pdev, 0); |
| 389 | ch->base = mtu->mapbase - cfg->channel_offset; |
| 390 | ch->index = cfg->timer_bit; |
| 391 | } else { |
| 392 | char name[6]; |
| 393 | |
| 394 | clockevent = true; |
| 395 | |
| 396 | sprintf(name, "tgi%ua", index); |
| 397 | ch->irq = platform_get_irq_byname(mtu->pdev, name); |
| 398 | ch->base = mtu->mapbase + channel_offsets[index]; |
| 399 | ch->index = index; |
| 400 | } |
| 401 | |
Laurent Pinchart | 2e1a532 | 2014-03-04 13:11:23 +0100 | [diff] [blame] | 402 | if (ch->irq < 0) { |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 403 | /* Skip channels with no declared interrupt. */ |
| 404 | if (!mtu->legacy) |
| 405 | return 0; |
| 406 | |
Laurent Pinchart | d2b9317 | 2014-03-04 14:17:26 +0100 | [diff] [blame] | 407 | dev_err(&mtu->pdev->dev, "ch%u: failed to get irq\n", |
| 408 | ch->index); |
Laurent Pinchart | 2e1a532 | 2014-03-04 13:11:23 +0100 | [diff] [blame] | 409 | return ch->irq; |
| 410 | } |
| 411 | |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 412 | return sh_mtu2_register(ch, dev_name(&mtu->pdev->dev), clockevent); |
| 413 | } |
| 414 | |
| 415 | static int sh_mtu2_map_memory(struct sh_mtu2_device *mtu) |
| 416 | { |
| 417 | struct resource *res; |
| 418 | |
| 419 | res = platform_get_resource(mtu->pdev, IORESOURCE_MEM, 0); |
| 420 | if (!res) { |
| 421 | dev_err(&mtu->pdev->dev, "failed to get I/O memory\n"); |
| 422 | return -ENXIO; |
| 423 | } |
| 424 | |
| 425 | mtu->mapbase = ioremap_nocache(res->start, resource_size(res)); |
| 426 | if (mtu->mapbase == NULL) |
| 427 | return -ENXIO; |
| 428 | |
| 429 | /* |
| 430 | * In legacy platform device configuration (with one device per channel) |
| 431 | * the resource points to the channel base address. |
| 432 | */ |
| 433 | if (mtu->legacy) { |
| 434 | struct sh_timer_config *cfg = mtu->pdev->dev.platform_data; |
| 435 | mtu->mapbase += cfg->channel_offset; |
| 436 | } |
| 437 | |
| 438 | return 0; |
| 439 | } |
| 440 | |
| 441 | static void sh_mtu2_unmap_memory(struct sh_mtu2_device *mtu) |
| 442 | { |
| 443 | if (mtu->legacy) { |
| 444 | struct sh_timer_config *cfg = mtu->pdev->dev.platform_data; |
| 445 | mtu->mapbase -= cfg->channel_offset; |
| 446 | } |
| 447 | |
| 448 | iounmap(mtu->mapbase); |
Laurent Pinchart | 2e1a532 | 2014-03-04 13:11:23 +0100 | [diff] [blame] | 449 | } |
| 450 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 451 | static int sh_mtu2_setup(struct sh_mtu2_device *mtu, |
| 452 | struct platform_device *pdev) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 453 | { |
Paul Mundt | 46a12f7 | 2009-05-03 17:57:17 +0900 | [diff] [blame] | 454 | struct sh_timer_config *cfg = pdev->dev.platform_data; |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 455 | const struct platform_device_id *id = pdev->id_entry; |
| 456 | unsigned int i; |
Laurent Pinchart | 276bee0 | 2014-02-17 11:27:49 +0100 | [diff] [blame] | 457 | int ret; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 458 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 459 | mtu->pdev = pdev; |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 460 | mtu->legacy = id->driver_data; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 461 | |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 462 | if (mtu->legacy && !cfg) { |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 463 | dev_err(&mtu->pdev->dev, "missing platform data\n"); |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 464 | return -ENXIO; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 465 | } |
| 466 | |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 467 | /* Get hold of clock. */ |
Laurent Pinchart | 6dc9693 | 2014-03-04 18:09:15 +0100 | [diff] [blame^] | 468 | mtu->clk = clk_get(&mtu->pdev->dev, mtu->legacy ? "mtu2_fck" : "fck"); |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 469 | if (IS_ERR(mtu->clk)) { |
| 470 | dev_err(&mtu->pdev->dev, "cannot get clock\n"); |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 471 | return PTR_ERR(mtu->clk); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 472 | } |
| 473 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 474 | ret = clk_prepare(mtu->clk); |
Laurent Pinchart | a4a5fc3 | 2013-11-08 11:07:59 +0100 | [diff] [blame] | 475 | if (ret < 0) |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 476 | goto err_clk_put; |
Laurent Pinchart | a4a5fc3 | 2013-11-08 11:07:59 +0100 | [diff] [blame] | 477 | |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 478 | /* Map the memory resource. */ |
| 479 | ret = sh_mtu2_map_memory(mtu); |
| 480 | if (ret < 0) { |
| 481 | dev_err(&mtu->pdev->dev, "failed to remap I/O memory\n"); |
| 482 | goto err_clk_unprepare; |
Laurent Pinchart | c54ccb4 | 2014-03-04 14:23:00 +0100 | [diff] [blame] | 483 | } |
| 484 | |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 485 | /* Allocate and setup the channels. */ |
| 486 | if (mtu->legacy) |
| 487 | mtu->num_channels = 1; |
| 488 | else |
| 489 | mtu->num_channels = 3; |
Laurent Pinchart | c54ccb4 | 2014-03-04 14:23:00 +0100 | [diff] [blame] | 490 | |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 491 | mtu->channels = kzalloc(sizeof(*mtu->channels) * mtu->num_channels, |
| 492 | GFP_KERNEL); |
| 493 | if (mtu->channels == NULL) { |
| 494 | ret = -ENOMEM; |
| 495 | goto err_unmap; |
| 496 | } |
Laurent Pinchart | c54ccb4 | 2014-03-04 14:23:00 +0100 | [diff] [blame] | 497 | |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 498 | if (mtu->legacy) { |
| 499 | ret = sh_mtu2_setup_channel(&mtu->channels[0], 0, mtu); |
| 500 | if (ret < 0) |
| 501 | goto err_unmap; |
| 502 | } else { |
| 503 | for (i = 0; i < mtu->num_channels; ++i) { |
| 504 | ret = sh_mtu2_setup_channel(&mtu->channels[i], i, mtu); |
| 505 | if (ret < 0) |
| 506 | goto err_unmap; |
| 507 | } |
| 508 | } |
| 509 | |
| 510 | platform_set_drvdata(pdev, mtu); |
Laurent Pinchart | a4a5fc3 | 2013-11-08 11:07:59 +0100 | [diff] [blame] | 511 | |
Laurent Pinchart | bd75493 | 2013-11-08 11:07:59 +0100 | [diff] [blame] | 512 | return 0; |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 513 | |
| 514 | err_unmap: |
Laurent Pinchart | c54ccb4 | 2014-03-04 14:23:00 +0100 | [diff] [blame] | 515 | kfree(mtu->channels); |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 516 | sh_mtu2_unmap_memory(mtu); |
| 517 | err_clk_unprepare: |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 518 | clk_unprepare(mtu->clk); |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 519 | err_clk_put: |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 520 | clk_put(mtu->clk); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 521 | return ret; |
| 522 | } |
| 523 | |
Greg Kroah-Hartman | 1850514 | 2012-12-21 15:11:38 -0800 | [diff] [blame] | 524 | static int sh_mtu2_probe(struct platform_device *pdev) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 525 | { |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 526 | struct sh_mtu2_device *mtu = platform_get_drvdata(pdev); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 527 | int ret; |
| 528 | |
Rafael J. Wysocki | cc7ad45 | 2012-08-06 01:43:41 +0200 | [diff] [blame] | 529 | if (!is_early_platform_device(pdev)) { |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 530 | pm_runtime_set_active(&pdev->dev); |
| 531 | pm_runtime_enable(&pdev->dev); |
Rafael J. Wysocki | cc7ad45 | 2012-08-06 01:43:41 +0200 | [diff] [blame] | 532 | } |
Rafael J. Wysocki | 57d1337 | 2012-03-13 22:40:14 +0100 | [diff] [blame] | 533 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 534 | if (mtu) { |
Paul Mundt | 214a607 | 2010-03-10 16:26:25 +0900 | [diff] [blame] | 535 | dev_info(&pdev->dev, "kept as earlytimer\n"); |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 536 | goto out; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 537 | } |
| 538 | |
Laurent Pinchart | 810c651 | 2014-03-04 14:10:55 +0100 | [diff] [blame] | 539 | mtu = kzalloc(sizeof(*mtu), GFP_KERNEL); |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 540 | if (mtu == NULL) { |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 541 | dev_err(&pdev->dev, "failed to allocate driver data\n"); |
| 542 | return -ENOMEM; |
| 543 | } |
| 544 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 545 | ret = sh_mtu2_setup(mtu, pdev); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 546 | if (ret) { |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 547 | kfree(mtu); |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 548 | pm_runtime_idle(&pdev->dev); |
| 549 | return ret; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 550 | } |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 551 | if (is_early_platform_device(pdev)) |
| 552 | return 0; |
| 553 | |
| 554 | out: |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 555 | if (mtu->has_clockevent) |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 556 | pm_runtime_irq_safe(&pdev->dev); |
| 557 | else |
| 558 | pm_runtime_idle(&pdev->dev); |
| 559 | |
| 560 | return 0; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 561 | } |
| 562 | |
Greg Kroah-Hartman | 1850514 | 2012-12-21 15:11:38 -0800 | [diff] [blame] | 563 | static int sh_mtu2_remove(struct platform_device *pdev) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 564 | { |
| 565 | return -EBUSY; /* cannot unregister clockevent */ |
| 566 | } |
| 567 | |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 568 | static const struct platform_device_id sh_mtu2_id_table[] = { |
| 569 | { "sh_mtu2", 1 }, |
| 570 | { "sh-mtu2", 0 }, |
| 571 | { }, |
| 572 | }; |
| 573 | MODULE_DEVICE_TABLE(platform, sh_mtu2_id_table); |
| 574 | |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 575 | static struct platform_driver sh_mtu2_device_driver = { |
| 576 | .probe = sh_mtu2_probe, |
Greg Kroah-Hartman | 1850514 | 2012-12-21 15:11:38 -0800 | [diff] [blame] | 577 | .remove = sh_mtu2_remove, |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 578 | .driver = { |
| 579 | .name = "sh_mtu2", |
Laurent Pinchart | faf3f4f | 2014-03-04 18:05:45 +0100 | [diff] [blame] | 580 | }, |
| 581 | .id_table = sh_mtu2_id_table, |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 582 | }; |
| 583 | |
| 584 | static int __init sh_mtu2_init(void) |
| 585 | { |
| 586 | return platform_driver_register(&sh_mtu2_device_driver); |
| 587 | } |
| 588 | |
| 589 | static void __exit sh_mtu2_exit(void) |
| 590 | { |
| 591 | platform_driver_unregister(&sh_mtu2_device_driver); |
| 592 | } |
| 593 | |
| 594 | early_platform_init("earlytimer", &sh_mtu2_device_driver); |
Simon Horman | 342896a | 2013-03-05 15:40:42 +0900 | [diff] [blame] | 595 | subsys_initcall(sh_mtu2_init); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 596 | module_exit(sh_mtu2_exit); |
| 597 | |
| 598 | MODULE_AUTHOR("Magnus Damm"); |
| 599 | MODULE_DESCRIPTION("SuperH MTU2 Timer Driver"); |
| 600 | MODULE_LICENSE("GPL v2"); |