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Magnus Dammd5ed4c22009-04-30 07:02:49 +00001/*
2 * SuperH Timer Support - MTU2
3 *
4 * Copyright (C) 2009 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27#include <linux/clk.h>
28#include <linux/irq.h>
29#include <linux/err.h>
30#include <linux/clockchips.h>
Paul Mundt46a12f72009-05-03 17:57:17 +090031#include <linux/sh_timer.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Paul Gortmaker7deeab52011-07-03 13:36:22 -040033#include <linux/module.h>
Rafael J. Wysocki57d13372012-03-13 22:40:14 +010034#include <linux/pm_domain.h>
Rafael J. Wysocki3cb6f102012-08-13 14:00:16 +020035#include <linux/pm_runtime.h>
Magnus Dammd5ed4c22009-04-30 07:02:49 +000036
Laurent Pinchart7dad72d2014-03-04 13:04:48 +010037struct sh_mtu2_device;
Laurent Pinchart42752cc2014-03-04 12:58:30 +010038
39struct sh_mtu2_channel {
Laurent Pinchart7dad72d2014-03-04 13:04:48 +010040 struct sh_mtu2_device *mtu;
Laurent Pinchartd2b93172014-03-04 14:17:26 +010041 unsigned int index;
Laurent Pinchartda90a1c2014-03-04 14:04:24 +010042
43 void __iomem *base;
Laurent Pinchart42752cc2014-03-04 12:58:30 +010044 int irq;
Laurent Pinchartda90a1c2014-03-04 14:04:24 +010045
Laurent Pinchart42752cc2014-03-04 12:58:30 +010046 struct clock_event_device ced;
47};
48
Laurent Pinchart7dad72d2014-03-04 13:04:48 +010049struct sh_mtu2_device {
Laurent Pinchart42752cc2014-03-04 12:58:30 +010050 struct platform_device *pdev;
51
Magnus Dammd5ed4c22009-04-30 07:02:49 +000052 void __iomem *mapbase;
53 struct clk *clk;
Laurent Pinchart42752cc2014-03-04 12:58:30 +010054
Laurent Pinchartc54ccb42014-03-04 14:23:00 +010055 struct sh_mtu2_channel *channels;
56 unsigned int num_channels;
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +010057
58 bool legacy;
59 bool has_clockevent;
Magnus Dammd5ed4c22009-04-30 07:02:49 +000060};
61
Paul Mundt50393a92012-05-25 13:38:54 +090062static DEFINE_RAW_SPINLOCK(sh_mtu2_lock);
Magnus Dammd5ed4c22009-04-30 07:02:49 +000063
64#define TSTR -1 /* shared register */
65#define TCR 0 /* channel register */
66#define TMDR 1 /* channel register */
67#define TIOR 2 /* channel register */
68#define TIER 3 /* channel register */
69#define TSR 4 /* channel register */
70#define TCNT 5 /* channel register */
71#define TGR 6 /* channel register */
72
Laurent Pinchartf992c242014-03-04 15:16:25 +010073#define TCR_CCLR_NONE (0 << 5)
74#define TCR_CCLR_TGRA (1 << 5)
75#define TCR_CCLR_TGRB (2 << 5)
76#define TCR_CCLR_SYNC (3 << 5)
77#define TCR_CCLR_TGRC (5 << 5)
78#define TCR_CCLR_TGRD (6 << 5)
79#define TCR_CCLR_MASK (7 << 5)
80#define TCR_CKEG_RISING (0 << 3)
81#define TCR_CKEG_FALLING (1 << 3)
82#define TCR_CKEG_BOTH (2 << 3)
83#define TCR_CKEG_MASK (3 << 3)
84/* Values 4 to 7 are channel-dependent */
85#define TCR_TPSC_P1 (0 << 0)
86#define TCR_TPSC_P4 (1 << 0)
87#define TCR_TPSC_P16 (2 << 0)
88#define TCR_TPSC_P64 (3 << 0)
89#define TCR_TPSC_CH0_TCLKA (4 << 0)
90#define TCR_TPSC_CH0_TCLKB (5 << 0)
91#define TCR_TPSC_CH0_TCLKC (6 << 0)
92#define TCR_TPSC_CH0_TCLKD (7 << 0)
93#define TCR_TPSC_CH1_TCLKA (4 << 0)
94#define TCR_TPSC_CH1_TCLKB (5 << 0)
95#define TCR_TPSC_CH1_P256 (6 << 0)
96#define TCR_TPSC_CH1_TCNT2 (7 << 0)
97#define TCR_TPSC_CH2_TCLKA (4 << 0)
98#define TCR_TPSC_CH2_TCLKB (5 << 0)
99#define TCR_TPSC_CH2_TCLKC (6 << 0)
100#define TCR_TPSC_CH2_P1024 (7 << 0)
101#define TCR_TPSC_CH34_P256 (4 << 0)
102#define TCR_TPSC_CH34_P1024 (5 << 0)
103#define TCR_TPSC_CH34_TCLKA (6 << 0)
104#define TCR_TPSC_CH34_TCLKB (7 << 0)
105#define TCR_TPSC_MASK (7 << 0)
106
107#define TMDR_BFE (1 << 6)
108#define TMDR_BFB (1 << 5)
109#define TMDR_BFA (1 << 4)
110#define TMDR_MD_NORMAL (0 << 0)
111#define TMDR_MD_PWM_1 (2 << 0)
112#define TMDR_MD_PWM_2 (3 << 0)
113#define TMDR_MD_PHASE_1 (4 << 0)
114#define TMDR_MD_PHASE_2 (5 << 0)
115#define TMDR_MD_PHASE_3 (6 << 0)
116#define TMDR_MD_PHASE_4 (7 << 0)
117#define TMDR_MD_PWM_SYNC (8 << 0)
118#define TMDR_MD_PWM_COMP_CREST (13 << 0)
119#define TMDR_MD_PWM_COMP_TROUGH (14 << 0)
120#define TMDR_MD_PWM_COMP_BOTH (15 << 0)
121#define TMDR_MD_MASK (15 << 0)
122
123#define TIOC_IOCH(n) ((n) << 4)
124#define TIOC_IOCL(n) ((n) << 0)
125#define TIOR_OC_RETAIN (0 << 0)
126#define TIOR_OC_0_CLEAR (1 << 0)
127#define TIOR_OC_0_SET (2 << 0)
128#define TIOR_OC_0_TOGGLE (3 << 0)
129#define TIOR_OC_1_CLEAR (5 << 0)
130#define TIOR_OC_1_SET (6 << 0)
131#define TIOR_OC_1_TOGGLE (7 << 0)
132#define TIOR_IC_RISING (8 << 0)
133#define TIOR_IC_FALLING (9 << 0)
134#define TIOR_IC_BOTH (10 << 0)
135#define TIOR_IC_TCNT (12 << 0)
136#define TIOR_MASK (15 << 0)
137
138#define TIER_TTGE (1 << 7)
139#define TIER_TTGE2 (1 << 6)
140#define TIER_TCIEU (1 << 5)
141#define TIER_TCIEV (1 << 4)
142#define TIER_TGIED (1 << 3)
143#define TIER_TGIEC (1 << 2)
144#define TIER_TGIEB (1 << 1)
145#define TIER_TGIEA (1 << 0)
146
147#define TSR_TCFD (1 << 7)
148#define TSR_TCFU (1 << 5)
149#define TSR_TCFV (1 << 4)
150#define TSR_TGFD (1 << 3)
151#define TSR_TGFC (1 << 2)
152#define TSR_TGFB (1 << 1)
153#define TSR_TGFA (1 << 0)
154
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000155static unsigned long mtu2_reg_offs[] = {
156 [TCR] = 0,
157 [TMDR] = 1,
158 [TIOR] = 2,
159 [TIER] = 4,
160 [TSR] = 5,
161 [TCNT] = 6,
162 [TGR] = 8,
163};
164
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100165static inline unsigned long sh_mtu2_read(struct sh_mtu2_channel *ch, int reg_nr)
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000166{
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000167 unsigned long offs;
168
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100169 if (reg_nr == TSTR) {
170 if (ch->mtu->legacy)
171 return ioread8(ch->mtu->mapbase);
172 else
173 return ioread8(ch->mtu->mapbase + 0x280);
174 }
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000175
176 offs = mtu2_reg_offs[reg_nr];
177
178 if ((reg_nr == TCNT) || (reg_nr == TGR))
Laurent Pinchartda90a1c2014-03-04 14:04:24 +0100179 return ioread16(ch->base + offs);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000180 else
Laurent Pinchartda90a1c2014-03-04 14:04:24 +0100181 return ioread8(ch->base + offs);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000182}
183
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100184static inline void sh_mtu2_write(struct sh_mtu2_channel *ch, int reg_nr,
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000185 unsigned long value)
186{
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000187 unsigned long offs;
188
189 if (reg_nr == TSTR) {
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100190 if (ch->mtu->legacy)
191 return iowrite8(value, ch->mtu->mapbase);
192 else
193 return iowrite8(value, ch->mtu->mapbase + 0x280);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000194 }
195
196 offs = mtu2_reg_offs[reg_nr];
197
198 if ((reg_nr == TCNT) || (reg_nr == TGR))
Laurent Pinchartda90a1c2014-03-04 14:04:24 +0100199 iowrite16(value, ch->base + offs);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000200 else
Laurent Pinchartda90a1c2014-03-04 14:04:24 +0100201 iowrite8(value, ch->base + offs);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000202}
203
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100204static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start)
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000205{
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000206 unsigned long flags, value;
207
208 /* start stop register shared by multiple timer channels */
Paul Mundt50393a92012-05-25 13:38:54 +0900209 raw_spin_lock_irqsave(&sh_mtu2_lock, flags);
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100210 value = sh_mtu2_read(ch, TSTR);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000211
212 if (start)
Laurent Pinchartd2b93172014-03-04 14:17:26 +0100213 value |= 1 << ch->index;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000214 else
Laurent Pinchartd2b93172014-03-04 14:17:26 +0100215 value &= ~(1 << ch->index);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000216
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100217 sh_mtu2_write(ch, TSTR, value);
Paul Mundt50393a92012-05-25 13:38:54 +0900218 raw_spin_unlock_irqrestore(&sh_mtu2_lock, flags);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000219}
220
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100221static int sh_mtu2_enable(struct sh_mtu2_channel *ch)
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000222{
Laurent Pinchartf92d62f52014-03-04 12:59:54 +0100223 unsigned long periodic;
224 unsigned long rate;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000225 int ret;
226
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100227 pm_runtime_get_sync(&ch->mtu->pdev->dev);
228 dev_pm_syscore_device(&ch->mtu->pdev->dev, true);
Rafael J. Wysocki3cb6f102012-08-13 14:00:16 +0200229
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000230 /* enable clock */
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100231 ret = clk_enable(ch->mtu->clk);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000232 if (ret) {
Laurent Pinchartd2b93172014-03-04 14:17:26 +0100233 dev_err(&ch->mtu->pdev->dev, "ch%u: cannot enable clock\n",
234 ch->index);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000235 return ret;
236 }
237
238 /* make sure channel is disabled */
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100239 sh_mtu2_start_stop_ch(ch, 0);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000240
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100241 rate = clk_get_rate(ch->mtu->clk) / 64;
Laurent Pinchartf92d62f52014-03-04 12:59:54 +0100242 periodic = (rate + HZ/2) / HZ;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000243
Laurent Pinchartf992c242014-03-04 15:16:25 +0100244 /*
245 * "Periodic Counter Operation"
246 * Clear on TGRA compare match, divide clock by 64.
247 */
248 sh_mtu2_write(ch, TCR, TCR_CCLR_TGRA | TCR_TPSC_P64);
249 sh_mtu2_write(ch, TIOR, TIOC_IOCH(TIOR_OC_0_CLEAR) |
250 TIOC_IOCL(TIOR_OC_0_CLEAR));
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100251 sh_mtu2_write(ch, TGR, periodic);
252 sh_mtu2_write(ch, TCNT, 0);
Laurent Pinchartf992c242014-03-04 15:16:25 +0100253 sh_mtu2_write(ch, TMDR, TMDR_MD_NORMAL);
254 sh_mtu2_write(ch, TIER, TIER_TGIEA);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000255
256 /* enable channel */
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100257 sh_mtu2_start_stop_ch(ch, 1);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000258
259 return 0;
260}
261
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100262static void sh_mtu2_disable(struct sh_mtu2_channel *ch)
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000263{
264 /* disable channel */
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100265 sh_mtu2_start_stop_ch(ch, 0);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000266
267 /* stop clock */
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100268 clk_disable(ch->mtu->clk);
Rafael J. Wysocki3cb6f102012-08-13 14:00:16 +0200269
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100270 dev_pm_syscore_device(&ch->mtu->pdev->dev, false);
271 pm_runtime_put(&ch->mtu->pdev->dev);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000272}
273
274static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
275{
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100276 struct sh_mtu2_channel *ch = dev_id;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000277
278 /* acknowledge interrupt */
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100279 sh_mtu2_read(ch, TSR);
Laurent Pinchartf992c242014-03-04 15:16:25 +0100280 sh_mtu2_write(ch, TSR, ~TSR_TGFA);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000281
282 /* notify clockevent layer */
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100283 ch->ced.event_handler(&ch->ced);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000284 return IRQ_HANDLED;
285}
286
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100287static struct sh_mtu2_channel *ced_to_sh_mtu2(struct clock_event_device *ced)
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000288{
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100289 return container_of(ced, struct sh_mtu2_channel, ced);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000290}
291
292static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
293 struct clock_event_device *ced)
294{
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100295 struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000296 int disabled = 0;
297
298 /* deal with old setting first */
299 switch (ced->mode) {
300 case CLOCK_EVT_MODE_PERIODIC:
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100301 sh_mtu2_disable(ch);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000302 disabled = 1;
303 break;
304 default:
305 break;
306 }
307
308 switch (mode) {
309 case CLOCK_EVT_MODE_PERIODIC:
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100310 dev_info(&ch->mtu->pdev->dev,
Laurent Pinchartd2b93172014-03-04 14:17:26 +0100311 "ch%u: used for periodic clock events\n", ch->index);
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100312 sh_mtu2_enable(ch);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000313 break;
314 case CLOCK_EVT_MODE_UNUSED:
315 if (!disabled)
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100316 sh_mtu2_disable(ch);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000317 break;
318 case CLOCK_EVT_MODE_SHUTDOWN:
319 default:
320 break;
321 }
322}
323
Rafael J. Wysockicc7ad452012-08-06 01:43:41 +0200324static void sh_mtu2_clock_event_suspend(struct clock_event_device *ced)
325{
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100326 pm_genpd_syscore_poweroff(&ced_to_sh_mtu2(ced)->mtu->pdev->dev);
Rafael J. Wysockicc7ad452012-08-06 01:43:41 +0200327}
328
329static void sh_mtu2_clock_event_resume(struct clock_event_device *ced)
330{
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100331 pm_genpd_syscore_poweron(&ced_to_sh_mtu2(ced)->mtu->pdev->dev);
Rafael J. Wysockicc7ad452012-08-06 01:43:41 +0200332}
333
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100334static void sh_mtu2_register_clockevent(struct sh_mtu2_channel *ch,
Laurent Pinchart207e21a2014-03-04 15:19:41 +0100335 const char *name)
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000336{
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100337 struct clock_event_device *ced = &ch->ced;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000338 int ret;
339
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000340 ced->name = name;
341 ced->features = CLOCK_EVT_FEAT_PERIODIC;
Laurent Pinchart207e21a2014-03-04 15:19:41 +0100342 ced->rating = 200;
Laurent Pinchart3cc95042014-03-04 15:22:19 +0100343 ced->cpumask = cpu_possible_mask;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000344 ced->set_mode = sh_mtu2_clock_event_mode;
Rafael J. Wysockicc7ad452012-08-06 01:43:41 +0200345 ced->suspend = sh_mtu2_clock_event_suspend;
346 ced->resume = sh_mtu2_clock_event_resume;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000347
Laurent Pinchartd2b93172014-03-04 14:17:26 +0100348 dev_info(&ch->mtu->pdev->dev, "ch%u: used for clock events\n",
349 ch->index);
Paul Mundtda64c2a2010-02-25 16:37:46 +0900350 clockevents_register_device(ced);
351
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100352 ret = request_irq(ch->irq, sh_mtu2_interrupt,
Laurent Pinchart276bee02014-02-17 11:27:49 +0100353 IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING,
Laurent Pinchart42752cc2014-03-04 12:58:30 +0100354 dev_name(&ch->mtu->pdev->dev), ch);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000355 if (ret) {
Laurent Pinchartd2b93172014-03-04 14:17:26 +0100356 dev_err(&ch->mtu->pdev->dev, "ch%u: failed to request irq %d\n",
357 ch->index, ch->irq);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000358 return;
359 }
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000360}
361
Laurent Pinchartaa838042014-03-04 13:57:14 +0100362static int sh_mtu2_register(struct sh_mtu2_channel *ch, const char *name,
Laurent Pinchart207e21a2014-03-04 15:19:41 +0100363 bool clockevent)
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000364{
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100365 if (clockevent) {
366 ch->mtu->has_clockevent = true;
Laurent Pinchart207e21a2014-03-04 15:19:41 +0100367 sh_mtu2_register_clockevent(ch, name);
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100368 }
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000369
370 return 0;
371}
372
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100373static int sh_mtu2_setup_channel(struct sh_mtu2_channel *ch, unsigned int index,
Laurent Pinchart2e1a5322014-03-04 13:11:23 +0100374 struct sh_mtu2_device *mtu)
375{
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100376 static const unsigned int channel_offsets[] = {
377 0x300, 0x380, 0x000,
378 };
379 bool clockevent;
Laurent Pinchart2e1a5322014-03-04 13:11:23 +0100380
Laurent Pinchart2e1a5322014-03-04 13:11:23 +0100381 ch->mtu = mtu;
382
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100383 if (mtu->legacy) {
384 struct sh_timer_config *cfg = mtu->pdev->dev.platform_data;
385
386 clockevent = cfg->clockevent_rating != 0;
387
388 ch->irq = platform_get_irq(mtu->pdev, 0);
389 ch->base = mtu->mapbase - cfg->channel_offset;
390 ch->index = cfg->timer_bit;
391 } else {
392 char name[6];
393
394 clockevent = true;
395
396 sprintf(name, "tgi%ua", index);
397 ch->irq = platform_get_irq_byname(mtu->pdev, name);
398 ch->base = mtu->mapbase + channel_offsets[index];
399 ch->index = index;
400 }
401
Laurent Pinchart2e1a5322014-03-04 13:11:23 +0100402 if (ch->irq < 0) {
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100403 /* Skip channels with no declared interrupt. */
404 if (!mtu->legacy)
405 return 0;
406
Laurent Pinchartd2b93172014-03-04 14:17:26 +0100407 dev_err(&mtu->pdev->dev, "ch%u: failed to get irq\n",
408 ch->index);
Laurent Pinchart2e1a5322014-03-04 13:11:23 +0100409 return ch->irq;
410 }
411
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100412 return sh_mtu2_register(ch, dev_name(&mtu->pdev->dev), clockevent);
413}
414
415static int sh_mtu2_map_memory(struct sh_mtu2_device *mtu)
416{
417 struct resource *res;
418
419 res = platform_get_resource(mtu->pdev, IORESOURCE_MEM, 0);
420 if (!res) {
421 dev_err(&mtu->pdev->dev, "failed to get I/O memory\n");
422 return -ENXIO;
423 }
424
425 mtu->mapbase = ioremap_nocache(res->start, resource_size(res));
426 if (mtu->mapbase == NULL)
427 return -ENXIO;
428
429 /*
430 * In legacy platform device configuration (with one device per channel)
431 * the resource points to the channel base address.
432 */
433 if (mtu->legacy) {
434 struct sh_timer_config *cfg = mtu->pdev->dev.platform_data;
435 mtu->mapbase += cfg->channel_offset;
436 }
437
438 return 0;
439}
440
441static void sh_mtu2_unmap_memory(struct sh_mtu2_device *mtu)
442{
443 if (mtu->legacy) {
444 struct sh_timer_config *cfg = mtu->pdev->dev.platform_data;
445 mtu->mapbase -= cfg->channel_offset;
446 }
447
448 iounmap(mtu->mapbase);
Laurent Pinchart2e1a5322014-03-04 13:11:23 +0100449}
450
Laurent Pinchart7dad72d2014-03-04 13:04:48 +0100451static int sh_mtu2_setup(struct sh_mtu2_device *mtu,
452 struct platform_device *pdev)
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000453{
Paul Mundt46a12f72009-05-03 17:57:17 +0900454 struct sh_timer_config *cfg = pdev->dev.platform_data;
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100455 const struct platform_device_id *id = pdev->id_entry;
456 unsigned int i;
Laurent Pinchart276bee02014-02-17 11:27:49 +0100457 int ret;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000458
Laurent Pinchart7dad72d2014-03-04 13:04:48 +0100459 mtu->pdev = pdev;
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100460 mtu->legacy = id->driver_data;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000461
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100462 if (mtu->legacy && !cfg) {
Laurent Pinchart7dad72d2014-03-04 13:04:48 +0100463 dev_err(&mtu->pdev->dev, "missing platform data\n");
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100464 return -ENXIO;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000465 }
466
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100467 /* Get hold of clock. */
Laurent Pinchart6dc96932014-03-04 18:09:15 +0100468 mtu->clk = clk_get(&mtu->pdev->dev, mtu->legacy ? "mtu2_fck" : "fck");
Laurent Pinchart7dad72d2014-03-04 13:04:48 +0100469 if (IS_ERR(mtu->clk)) {
470 dev_err(&mtu->pdev->dev, "cannot get clock\n");
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100471 return PTR_ERR(mtu->clk);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000472 }
473
Laurent Pinchart7dad72d2014-03-04 13:04:48 +0100474 ret = clk_prepare(mtu->clk);
Laurent Pincharta4a5fc32013-11-08 11:07:59 +0100475 if (ret < 0)
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100476 goto err_clk_put;
Laurent Pincharta4a5fc32013-11-08 11:07:59 +0100477
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100478 /* Map the memory resource. */
479 ret = sh_mtu2_map_memory(mtu);
480 if (ret < 0) {
481 dev_err(&mtu->pdev->dev, "failed to remap I/O memory\n");
482 goto err_clk_unprepare;
Laurent Pinchartc54ccb42014-03-04 14:23:00 +0100483 }
484
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100485 /* Allocate and setup the channels. */
486 if (mtu->legacy)
487 mtu->num_channels = 1;
488 else
489 mtu->num_channels = 3;
Laurent Pinchartc54ccb42014-03-04 14:23:00 +0100490
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100491 mtu->channels = kzalloc(sizeof(*mtu->channels) * mtu->num_channels,
492 GFP_KERNEL);
493 if (mtu->channels == NULL) {
494 ret = -ENOMEM;
495 goto err_unmap;
496 }
Laurent Pinchartc54ccb42014-03-04 14:23:00 +0100497
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100498 if (mtu->legacy) {
499 ret = sh_mtu2_setup_channel(&mtu->channels[0], 0, mtu);
500 if (ret < 0)
501 goto err_unmap;
502 } else {
503 for (i = 0; i < mtu->num_channels; ++i) {
504 ret = sh_mtu2_setup_channel(&mtu->channels[i], i, mtu);
505 if (ret < 0)
506 goto err_unmap;
507 }
508 }
509
510 platform_set_drvdata(pdev, mtu);
Laurent Pincharta4a5fc32013-11-08 11:07:59 +0100511
Laurent Pinchartbd754932013-11-08 11:07:59 +0100512 return 0;
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100513
514err_unmap:
Laurent Pinchartc54ccb42014-03-04 14:23:00 +0100515 kfree(mtu->channels);
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100516 sh_mtu2_unmap_memory(mtu);
517err_clk_unprepare:
Laurent Pinchart7dad72d2014-03-04 13:04:48 +0100518 clk_unprepare(mtu->clk);
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100519err_clk_put:
Laurent Pinchart7dad72d2014-03-04 13:04:48 +0100520 clk_put(mtu->clk);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000521 return ret;
522}
523
Greg Kroah-Hartman18505142012-12-21 15:11:38 -0800524static int sh_mtu2_probe(struct platform_device *pdev)
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000525{
Laurent Pinchart7dad72d2014-03-04 13:04:48 +0100526 struct sh_mtu2_device *mtu = platform_get_drvdata(pdev);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000527 int ret;
528
Rafael J. Wysockicc7ad452012-08-06 01:43:41 +0200529 if (!is_early_platform_device(pdev)) {
Rafael J. Wysocki3cb6f102012-08-13 14:00:16 +0200530 pm_runtime_set_active(&pdev->dev);
531 pm_runtime_enable(&pdev->dev);
Rafael J. Wysockicc7ad452012-08-06 01:43:41 +0200532 }
Rafael J. Wysocki57d13372012-03-13 22:40:14 +0100533
Laurent Pinchart7dad72d2014-03-04 13:04:48 +0100534 if (mtu) {
Paul Mundt214a6072010-03-10 16:26:25 +0900535 dev_info(&pdev->dev, "kept as earlytimer\n");
Rafael J. Wysocki3cb6f102012-08-13 14:00:16 +0200536 goto out;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000537 }
538
Laurent Pinchart810c6512014-03-04 14:10:55 +0100539 mtu = kzalloc(sizeof(*mtu), GFP_KERNEL);
Laurent Pinchart7dad72d2014-03-04 13:04:48 +0100540 if (mtu == NULL) {
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000541 dev_err(&pdev->dev, "failed to allocate driver data\n");
542 return -ENOMEM;
543 }
544
Laurent Pinchart7dad72d2014-03-04 13:04:48 +0100545 ret = sh_mtu2_setup(mtu, pdev);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000546 if (ret) {
Laurent Pinchart7dad72d2014-03-04 13:04:48 +0100547 kfree(mtu);
Rafael J. Wysocki3cb6f102012-08-13 14:00:16 +0200548 pm_runtime_idle(&pdev->dev);
549 return ret;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000550 }
Rafael J. Wysocki3cb6f102012-08-13 14:00:16 +0200551 if (is_early_platform_device(pdev))
552 return 0;
553
554 out:
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100555 if (mtu->has_clockevent)
Rafael J. Wysocki3cb6f102012-08-13 14:00:16 +0200556 pm_runtime_irq_safe(&pdev->dev);
557 else
558 pm_runtime_idle(&pdev->dev);
559
560 return 0;
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000561}
562
Greg Kroah-Hartman18505142012-12-21 15:11:38 -0800563static int sh_mtu2_remove(struct platform_device *pdev)
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000564{
565 return -EBUSY; /* cannot unregister clockevent */
566}
567
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100568static const struct platform_device_id sh_mtu2_id_table[] = {
569 { "sh_mtu2", 1 },
570 { "sh-mtu2", 0 },
571 { },
572};
573MODULE_DEVICE_TABLE(platform, sh_mtu2_id_table);
574
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000575static struct platform_driver sh_mtu2_device_driver = {
576 .probe = sh_mtu2_probe,
Greg Kroah-Hartman18505142012-12-21 15:11:38 -0800577 .remove = sh_mtu2_remove,
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000578 .driver = {
579 .name = "sh_mtu2",
Laurent Pinchartfaf3f4f2014-03-04 18:05:45 +0100580 },
581 .id_table = sh_mtu2_id_table,
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000582};
583
584static int __init sh_mtu2_init(void)
585{
586 return platform_driver_register(&sh_mtu2_device_driver);
587}
588
589static void __exit sh_mtu2_exit(void)
590{
591 platform_driver_unregister(&sh_mtu2_device_driver);
592}
593
594early_platform_init("earlytimer", &sh_mtu2_device_driver);
Simon Horman342896a2013-03-05 15:40:42 +0900595subsys_initcall(sh_mtu2_init);
Magnus Dammd5ed4c22009-04-30 07:02:49 +0000596module_exit(sh_mtu2_exit);
597
598MODULE_AUTHOR("Magnus Damm");
599MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
600MODULE_LICENSE("GPL v2");