blob: 284f6ab8fef7696f476900499041c94dd8f00112 [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
40#include <linux/netdevice.h>
41#include <linux/etherdevice.h>
42#include <linux/ethtool.h>
43#include <linux/slab.h>
44#include <linux/device.h>
45#include <linux/skbuff.h>
46#include <linux/if_vlan.h>
47#include <linux/if_bridge.h>
48#include <linux/workqueue.h>
49#include <linux/jiffies.h>
50#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010051#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020052#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020053#include <linux/dcbnl.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020054#include <net/switchdev.h>
55#include <generated/utsrelease.h>
56
57#include "spectrum.h"
58#include "core.h"
59#include "reg.h"
60#include "port.h"
61#include "trap.h"
62#include "txheader.h"
63
64static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
65static const char mlxsw_sp_driver_version[] = "1.0";
66
67/* tx_hdr_version
68 * Tx header version.
69 * Must be set to 1.
70 */
71MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
72
73/* tx_hdr_ctl
74 * Packet control type.
75 * 0 - Ethernet control (e.g. EMADs, LACP)
76 * 1 - Ethernet data
77 */
78MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
79
80/* tx_hdr_proto
81 * Packet protocol type. Must be set to 1 (Ethernet).
82 */
83MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
84
85/* tx_hdr_rx_is_router
86 * Packet is sent from the router. Valid for data packets only.
87 */
88MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
89
90/* tx_hdr_fid_valid
91 * Indicates if the 'fid' field is valid and should be used for
92 * forwarding lookup. Valid for data packets only.
93 */
94MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
95
96/* tx_hdr_swid
97 * Switch partition ID. Must be set to 0.
98 */
99MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
100
101/* tx_hdr_control_tclass
102 * Indicates if the packet should use the control TClass and not one
103 * of the data TClasses.
104 */
105MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
106
107/* tx_hdr_etclass
108 * Egress TClass to be used on the egress device on the egress port.
109 */
110MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
111
112/* tx_hdr_port_mid
113 * Destination local port for unicast packets.
114 * Destination multicast ID for multicast packets.
115 *
116 * Control packets are directed to a specific egress port, while data
117 * packets are transmitted through the CPU port (0) into the switch partition,
118 * where forwarding rules are applied.
119 */
120MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
121
122/* tx_hdr_fid
123 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
124 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
125 * Valid for data packets only.
126 */
127MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
128
129/* tx_hdr_type
130 * 0 - Data packets
131 * 6 - Control packets
132 */
133MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
134
135static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
136 const struct mlxsw_tx_info *tx_info)
137{
138 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
139
140 memset(txhdr, 0, MLXSW_TXHDR_LEN);
141
142 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
143 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
144 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
145 mlxsw_tx_hdr_swid_set(txhdr, 0);
146 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
147 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
148 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
149}
150
151static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
152{
153 char spad_pl[MLXSW_REG_SPAD_LEN];
154 int err;
155
156 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
157 if (err)
158 return err;
159 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
160 return 0;
161}
162
163static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
164 bool is_up)
165{
166 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
167 char paos_pl[MLXSW_REG_PAOS_LEN];
168
169 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
170 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
171 MLXSW_PORT_ADMIN_STATUS_DOWN);
172 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
173}
174
175static int mlxsw_sp_port_oper_status_get(struct mlxsw_sp_port *mlxsw_sp_port,
176 bool *p_is_up)
177{
178 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
179 char paos_pl[MLXSW_REG_PAOS_LEN];
180 u8 oper_status;
181 int err;
182
183 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port, 0);
184 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
185 if (err)
186 return err;
187 oper_status = mlxsw_reg_paos_oper_status_get(paos_pl);
188 *p_is_up = oper_status == MLXSW_PORT_ADMIN_STATUS_UP ? true : false;
189 return 0;
190}
191
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200192static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
193 unsigned char *addr)
194{
195 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
196 char ppad_pl[MLXSW_REG_PPAD_LEN];
197
198 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
199 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
200 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
201}
202
203static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
204{
205 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
206 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
207
208 ether_addr_copy(addr, mlxsw_sp->base_mac);
209 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
210 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
211}
212
213static int mlxsw_sp_port_stp_state_set(struct mlxsw_sp_port *mlxsw_sp_port,
214 u16 vid, enum mlxsw_reg_spms_state state)
215{
216 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
217 char *spms_pl;
218 int err;
219
220 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
221 if (!spms_pl)
222 return -ENOMEM;
223 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
224 mlxsw_reg_spms_vid_pack(spms_pl, vid, state);
225 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
226 kfree(spms_pl);
227 return err;
228}
229
230static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
231{
232 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
233 char pmtu_pl[MLXSW_REG_PMTU_LEN];
234 int max_mtu;
235 int err;
236
237 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
238 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
239 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
240 if (err)
241 return err;
242 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
243
244 if (mtu > max_mtu)
245 return -EINVAL;
246
247 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
248 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
249}
250
Ido Schimmelbe945352016-06-09 09:51:39 +0200251static int __mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, u8 local_port,
252 u8 swid)
253{
254 char pspa_pl[MLXSW_REG_PSPA_LEN];
255
256 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
257 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
258}
259
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200260static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
261{
262 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200263
Ido Schimmelbe945352016-06-09 09:51:39 +0200264 return __mlxsw_sp_port_swid_set(mlxsw_sp, mlxsw_sp_port->local_port,
265 swid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200266}
267
268static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
269 bool enable)
270{
271 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
272 char svpe_pl[MLXSW_REG_SVPE_LEN];
273
274 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
275 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
276}
277
278int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
279 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
280 u16 vid)
281{
282 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
283 char svfa_pl[MLXSW_REG_SVFA_LEN];
284
285 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
286 fid, vid);
287 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
288}
289
290static int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port,
291 u16 vid, bool learn_enable)
292{
293 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
294 char *spvmlr_pl;
295 int err;
296
297 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
298 if (!spvmlr_pl)
299 return -ENOMEM;
300 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
301 learn_enable);
302 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
303 kfree(spvmlr_pl);
304 return err;
305}
306
307static int
308mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
309{
310 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
311 char sspr_pl[MLXSW_REG_SSPR_LEN];
312
313 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
314 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
315}
316
Ido Schimmeld664b412016-06-09 09:51:40 +0200317static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
318 u8 local_port, u8 *p_module,
319 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200320{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200321 char pmlp_pl[MLXSW_REG_PMLP_LEN];
322 int err;
323
Ido Schimmel558c2d52016-02-26 17:32:29 +0100324 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200325 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
326 if (err)
327 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100328 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
329 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200330 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200331 return 0;
332}
333
Ido Schimmel18f1e702016-02-26 17:32:31 +0100334static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
335 u8 module, u8 width, u8 lane)
336{
337 char pmlp_pl[MLXSW_REG_PMLP_LEN];
338 int i;
339
340 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
341 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
342 for (i = 0; i < width; i++) {
343 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
344 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
345 }
346
347 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
348}
349
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100350static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
351{
352 char pmlp_pl[MLXSW_REG_PMLP_LEN];
353
354 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
355 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
356 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
357}
358
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200359static int mlxsw_sp_port_open(struct net_device *dev)
360{
361 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
362 int err;
363
364 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
365 if (err)
366 return err;
367 netif_start_queue(dev);
368 return 0;
369}
370
371static int mlxsw_sp_port_stop(struct net_device *dev)
372{
373 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
374
375 netif_stop_queue(dev);
376 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
377}
378
379static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
380 struct net_device *dev)
381{
382 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
383 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
384 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
385 const struct mlxsw_tx_info tx_info = {
386 .local_port = mlxsw_sp_port->local_port,
387 .is_emad = false,
388 };
389 u64 len;
390 int err;
391
Jiri Pirko307c2432016-04-08 19:11:22 +0200392 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200393 return NETDEV_TX_BUSY;
394
395 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
396 struct sk_buff *skb_orig = skb;
397
398 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
399 if (!skb) {
400 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
401 dev_kfree_skb_any(skb_orig);
402 return NETDEV_TX_OK;
403 }
404 }
405
406 if (eth_skb_pad(skb)) {
407 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
408 return NETDEV_TX_OK;
409 }
410
411 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +0200412 /* TX header is consumed by HW on the way so we shouldn't count its
413 * bytes as being sent.
414 */
415 len = skb->len - MLXSW_TXHDR_LEN;
416
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200417 /* Due to a race we might fail here because of a full queue. In that
418 * unlikely case we simply drop the packet.
419 */
Jiri Pirko307c2432016-04-08 19:11:22 +0200420 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200421
422 if (!err) {
423 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
424 u64_stats_update_begin(&pcpu_stats->syncp);
425 pcpu_stats->tx_packets++;
426 pcpu_stats->tx_bytes += len;
427 u64_stats_update_end(&pcpu_stats->syncp);
428 } else {
429 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
430 dev_kfree_skb_any(skb);
431 }
432 return NETDEV_TX_OK;
433}
434
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100435static void mlxsw_sp_set_rx_mode(struct net_device *dev)
436{
437}
438
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200439static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
440{
441 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
442 struct sockaddr *addr = p;
443 int err;
444
445 if (!is_valid_ether_addr(addr->sa_data))
446 return -EADDRNOTAVAIL;
447
448 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
449 if (err)
450 return err;
451 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
452 return 0;
453}
454
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200455static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int pg_index, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200456 bool pause_en, bool pfc_en, u16 delay)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200457{
458 u16 pg_size = 2 * MLXSW_SP_BYTES_TO_CELLS(mtu);
459
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200460 delay = pfc_en ? mlxsw_sp_pfc_delay_get(mtu, delay) :
461 MLXSW_SP_PAUSE_DELAY;
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200462
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200463 if (pause_en || pfc_en)
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200464 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, pg_index,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200465 pg_size + delay, pg_size);
466 else
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200467 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, pg_index, pg_size);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200468}
469
470int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200471 u8 *prio_tc, bool pause_en,
472 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +0200473{
474 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200475 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
476 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200477 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200478 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200479
480 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
481 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
482 if (err)
483 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200484
485 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
486 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200487 bool pfc = false;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200488
489 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
490 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200491 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200492 configure = true;
493 break;
494 }
495 }
496
497 if (!configure)
498 continue;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200499 mlxsw_sp_pg_buf_pack(pbmc_pl, i, mtu, pause_en, pfc, delay);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200500 }
501
Ido Schimmelff6551e2016-04-06 17:10:03 +0200502 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
503}
504
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200505static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200506 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200507{
508 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
509 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200510 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200511 u8 *prio_tc;
512
513 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200514 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200515
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200516 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +0200517 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +0200518}
519
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200520static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
521{
522 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200523 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200524 int err;
525
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200526 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200527 if (err)
528 return err;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200529 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
530 if (err)
531 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200532 dev->mtu = mtu;
533 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +0200534
535err_port_mtu_set:
Ido Schimmel9f7ec052016-04-06 17:10:14 +0200536 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +0200537 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200538}
539
540static struct rtnl_link_stats64 *
541mlxsw_sp_port_get_stats64(struct net_device *dev,
542 struct rtnl_link_stats64 *stats)
543{
544 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
545 struct mlxsw_sp_port_pcpu_stats *p;
546 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
547 u32 tx_dropped = 0;
548 unsigned int start;
549 int i;
550
551 for_each_possible_cpu(i) {
552 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
553 do {
554 start = u64_stats_fetch_begin_irq(&p->syncp);
555 rx_packets = p->rx_packets;
556 rx_bytes = p->rx_bytes;
557 tx_packets = p->tx_packets;
558 tx_bytes = p->tx_bytes;
559 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
560
561 stats->rx_packets += rx_packets;
562 stats->rx_bytes += rx_bytes;
563 stats->tx_packets += tx_packets;
564 stats->tx_bytes += tx_bytes;
565 /* tx_dropped is u32, updated without syncp protection. */
566 tx_dropped += p->tx_dropped;
567 }
568 stats->tx_dropped = tx_dropped;
569 return stats;
570}
571
572int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
573 u16 vid_end, bool is_member, bool untagged)
574{
575 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
576 char *spvm_pl;
577 int err;
578
579 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
580 if (!spvm_pl)
581 return -ENOMEM;
582
583 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
584 vid_end, is_member, untagged);
585 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
586 kfree(spvm_pl);
587 return err;
588}
589
590static int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
591{
592 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
593 u16 vid, last_visited_vid;
594 int err;
595
596 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
597 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
598 vid);
599 if (err) {
600 last_visited_vid = vid;
601 goto err_port_vid_to_fid_set;
602 }
603 }
604
605 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
606 if (err) {
607 last_visited_vid = VLAN_N_VID;
608 goto err_port_vid_to_fid_set;
609 }
610
611 return 0;
612
613err_port_vid_to_fid_set:
614 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
615 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
616 vid);
617 return err;
618}
619
620static int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
621{
622 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
623 u16 vid;
624 int err;
625
626 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
627 if (err)
628 return err;
629
630 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
631 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
632 vid, vid);
633 if (err)
634 return err;
635 }
636
637 return 0;
638}
639
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200640static struct mlxsw_sp_fid *
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100641mlxsw_sp_vfid_find(const struct mlxsw_sp *mlxsw_sp, u16 vid)
642{
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200643 struct mlxsw_sp_fid *f;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100644
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200645 list_for_each_entry(f, &mlxsw_sp->port_vfids.list, list) {
646 if (f->vid == vid)
647 return f;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100648 }
649
650 return NULL;
651}
652
653static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
654{
655 return find_first_zero_bit(mlxsw_sp->port_vfids.mapped,
656 MLXSW_SP_VFID_PORT_MAX);
657}
658
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200659static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create)
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100660{
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100661 char sfmr_pl[MLXSW_REG_SFMR_LEN];
662
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200663 mlxsw_reg_sfmr_pack(sfmr_pl, !create, fid, 0);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100664 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
665}
666
Ido Schimmel1c800752016-06-20 23:04:20 +0200667static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
668
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200669static struct mlxsw_sp_fid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
670 u16 vid)
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100671{
672 struct device *dev = mlxsw_sp->bus_info->dev;
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200673 struct mlxsw_sp_fid *f;
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200674 u16 vfid, fid;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100675 int err;
676
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200677 vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
678 if (vfid == MLXSW_SP_VFID_PORT_MAX) {
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100679 dev_err(dev, "No available vFIDs\n");
680 return ERR_PTR(-ERANGE);
681 }
682
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200683 fid = mlxsw_sp_vfid_to_fid(vfid);
684 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100685 if (err) {
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200686 dev_err(dev, "Failed to create FID=%d\n", fid);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100687 return ERR_PTR(err);
688 }
689
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200690 f = kzalloc(sizeof(*f), GFP_KERNEL);
691 if (!f)
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100692 goto err_allocate_vfid;
693
Ido Schimmel1c800752016-06-20 23:04:20 +0200694 f->leave = mlxsw_sp_vport_vfid_leave;
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200695 f->fid = fid;
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200696 f->vid = vid;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100697
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200698 list_add(&f->list, &mlxsw_sp->port_vfids.list);
699 set_bit(vfid, mlxsw_sp->port_vfids.mapped);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100700
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200701 return f;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100702
703err_allocate_vfid:
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200704 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100705 return ERR_PTR(-ENOMEM);
706}
707
708static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200709 struct mlxsw_sp_fid *f)
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100710{
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200711 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
Ido Schimmelc7e920b2016-06-20 23:04:09 +0200712
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200713 clear_bit(vfid, mlxsw_sp->port_vfids.mapped);
714 list_del(&f->list);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100715
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200716 mlxsw_sp_vfid_op(mlxsw_sp, f->fid, false);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100717
Ido Schimmeld0ec8752016-06-20 23:04:12 +0200718 kfree(f);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100719}
720
721static struct mlxsw_sp_port *
Ido Schimmel0355b592016-06-20 23:04:13 +0200722mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100723{
724 struct mlxsw_sp_port *mlxsw_sp_vport;
725
726 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
727 if (!mlxsw_sp_vport)
728 return NULL;
729
730 /* dev will be set correctly after the VLAN device is linked
731 * with the real device. In case of bridge SELF invocation, dev
732 * will remain as is.
733 */
734 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
735 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
736 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
737 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
Ido Schimmel272c4472015-12-15 16:03:47 +0100738 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
739 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel0355b592016-06-20 23:04:13 +0200740 mlxsw_sp_vport->vport.vid = vid;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100741
742 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
743
744 return mlxsw_sp_vport;
745}
746
747static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
748{
749 list_del(&mlxsw_sp_vport->vport.list);
750 kfree(mlxsw_sp_vport);
751}
752
Ido Schimmel9c4d4422016-06-20 23:04:10 +0200753static int mlxsw_sp_vport_fid_map(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
754 bool valid)
755{
756 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
757 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
758
759 return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport, mt, valid, fid,
760 vid);
761}
762
Ido Schimmel0355b592016-06-20 23:04:13 +0200763static int mlxsw_sp_vport_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport)
764{
765 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
766 struct mlxsw_sp_fid *f;
767 int err;
768
769 f = mlxsw_sp_vfid_find(mlxsw_sp_vport->mlxsw_sp, vid);
770 if (!f) {
771 f = mlxsw_sp_vfid_create(mlxsw_sp_vport->mlxsw_sp, vid);
772 if (IS_ERR(f))
773 return PTR_ERR(f);
774 }
775
776 if (!f->ref_count) {
777 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
778 if (err)
779 goto err_vport_flood_set;
780 }
781
782 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
783 if (err)
784 goto err_vport_fid_map;
785
Ido Schimmel41b996c2016-06-20 23:04:17 +0200786 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
Ido Schimmel0355b592016-06-20 23:04:13 +0200787 f->ref_count++;
788
789 return 0;
790
791err_vport_fid_map:
792 if (!f->ref_count)
793 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
794err_vport_flood_set:
795 if (!f->ref_count)
796 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
797 return err;
798}
799
800static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
801{
Ido Schimmel41b996c2016-06-20 23:04:17 +0200802 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
Ido Schimmel0355b592016-06-20 23:04:13 +0200803
Ido Schimmel41b996c2016-06-20 23:04:17 +0200804 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
Ido Schimmel0355b592016-06-20 23:04:13 +0200805
806 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
807
808 if (--f->ref_count == 0) {
809 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
810 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
811 }
812}
813
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200814int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
815 u16 vid)
816{
817 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100818 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel52697a92016-07-02 11:00:09 +0200819 bool untagged = vid == 1;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200820 int err;
821
822 /* VLAN 0 is added to HW filter when device goes up, but it is
823 * reserved in our case, so simply return.
824 */
825 if (!vid)
826 return 0;
827
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100828 if (mlxsw_sp_port_vport_find(mlxsw_sp_port, vid)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200829 netdev_warn(dev, "VID=%d already configured\n", vid);
830 return 0;
831 }
832
Ido Schimmel0355b592016-06-20 23:04:13 +0200833 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, vid);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100834 if (!mlxsw_sp_vport) {
835 netdev_err(dev, "Failed to create vPort for VID=%d\n", vid);
Ido Schimmel0355b592016-06-20 23:04:13 +0200836 return -ENOMEM;
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100837 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200838
839 /* When adding the first VLAN interface on a bridged port we need to
840 * transition all the active 802.1Q bridge VLANs to use explicit
841 * {Port, VID} to FID mappings and set the port's mode to Virtual mode.
842 */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100843 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200844 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
845 if (err) {
846 netdev_err(dev, "Failed to set to Virtual mode\n");
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100847 goto err_port_vp_mode_trans;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200848 }
849 }
850
Ido Schimmel0355b592016-06-20 23:04:13 +0200851 err = mlxsw_sp_vport_vfid_join(mlxsw_sp_vport);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200852 if (err) {
Ido Schimmel0355b592016-06-20 23:04:13 +0200853 netdev_err(dev, "Failed to join vFID\n");
854 goto err_vport_vfid_join;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200855 }
856
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100857 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200858 if (err) {
859 netdev_err(dev, "Failed to disable learning for VID=%d\n", vid);
860 goto err_port_vid_learning_set;
861 }
862
Ido Schimmel52697a92016-07-02 11:00:09 +0200863 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, untagged);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200864 if (err) {
865 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
866 vid);
867 goto err_port_add_vid;
868 }
869
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100870 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200871 MLXSW_REG_SPMS_STATE_FORWARDING);
872 if (err) {
873 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
874 goto err_port_stp_state_set;
875 }
876
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200877 return 0;
878
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200879err_port_stp_state_set:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100880 mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200881err_port_add_vid:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100882 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200883err_port_vid_learning_set:
Ido Schimmel0355b592016-06-20 23:04:13 +0200884 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
885err_vport_vfid_join:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100886 if (list_is_singular(&mlxsw_sp_port->vports_list))
887 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
888err_port_vp_mode_trans:
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100889 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200890 return err;
891}
892
Ido Schimmel32d863f2016-07-02 11:00:10 +0200893static int mlxsw_sp_port_kill_vid(struct net_device *dev,
894 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200895{
896 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100897 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel1c800752016-06-20 23:04:20 +0200898 struct mlxsw_sp_fid *f;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200899 int err;
900
901 /* VLAN 0 is removed from HW filter when device goes down, but
902 * it is reserved in our case, so simply return.
903 */
904 if (!vid)
905 return 0;
906
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100907 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
908 if (!mlxsw_sp_vport) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200909 netdev_warn(dev, "VID=%d does not exist\n", vid);
910 return 0;
911 }
912
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100913 err = mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200914 MLXSW_REG_SPMS_STATE_DISCARDING);
915 if (err) {
916 netdev_err(dev, "Failed to set STP state for VID=%d\n", vid);
917 return err;
918 }
919
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100920 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200921 if (err) {
922 netdev_err(dev, "Failed to set VLAN membership for VID=%d\n",
923 vid);
924 return err;
925 }
926
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100927 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200928 if (err) {
929 netdev_err(dev, "Failed to enable learning for VID=%d\n", vid);
930 return err;
931 }
932
Ido Schimmel1c800752016-06-20 23:04:20 +0200933 /* Drop FID reference. If this was the last reference the
934 * resources will be freed.
935 */
936 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
937 if (f && !WARN_ON(!f->leave))
938 f->leave(mlxsw_sp_vport);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200939
940 /* When removing the last VLAN interface on a bridged port we need to
941 * transition all active 802.1Q bridge VLANs to use VID to FID
942 * mappings and set port's mode to VLAN mode.
943 */
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100944 if (list_is_singular(&mlxsw_sp_port->vports_list)) {
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200945 err = mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
946 if (err) {
947 netdev_err(dev, "Failed to set to VLAN mode\n");
948 return err;
949 }
950 }
951
Ido Schimmel7f71eb42015-12-15 16:03:37 +0100952 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
953
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200954 return 0;
955}
956
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200957static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
958 size_t len)
959{
960 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmeld664b412016-06-09 09:51:40 +0200961 u8 module = mlxsw_sp_port->mapping.module;
962 u8 width = mlxsw_sp_port->mapping.width;
963 u8 lane = mlxsw_sp_port->mapping.lane;
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200964 int err;
965
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200966 if (!mlxsw_sp_port->split)
967 err = snprintf(name, len, "p%d", module + 1);
968 else
969 err = snprintf(name, len, "p%ds%d", module + 1,
970 lane / width);
971
972 if (err >= len)
973 return -EINVAL;
974
975 return 0;
976}
977
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200978static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
979 .ndo_open = mlxsw_sp_port_open,
980 .ndo_stop = mlxsw_sp_port_stop,
981 .ndo_start_xmit = mlxsw_sp_port_xmit,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +0100982 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200983 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
984 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
985 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
986 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
987 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
988 .ndo_fdb_add = switchdev_port_fdb_add,
989 .ndo_fdb_del = switchdev_port_fdb_del,
990 .ndo_fdb_dump = switchdev_port_fdb_dump,
991 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
992 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
993 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200994 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200995};
996
997static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
998 struct ethtool_drvinfo *drvinfo)
999{
1000 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1001 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1002
1003 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1004 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1005 sizeof(drvinfo->version));
1006 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1007 "%d.%d.%d",
1008 mlxsw_sp->bus_info->fw_rev.major,
1009 mlxsw_sp->bus_info->fw_rev.minor,
1010 mlxsw_sp->bus_info->fw_rev.subminor);
1011 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1012 sizeof(drvinfo->bus_info));
1013}
1014
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001015static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1016 struct ethtool_pauseparam *pause)
1017{
1018 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1019
1020 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1021 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1022}
1023
1024static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1025 struct ethtool_pauseparam *pause)
1026{
1027 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1028
1029 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1030 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1031 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1032
1033 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1034 pfcc_pl);
1035}
1036
1037static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1038 struct ethtool_pauseparam *pause)
1039{
1040 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1041 bool pause_en = pause->tx_pause || pause->rx_pause;
1042 int err;
1043
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001044 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1045 netdev_err(dev, "PFC already enabled on port\n");
1046 return -EINVAL;
1047 }
1048
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001049 if (pause->autoneg) {
1050 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1051 return -EINVAL;
1052 }
1053
1054 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1055 if (err) {
1056 netdev_err(dev, "Failed to configure port's headroom\n");
1057 return err;
1058 }
1059
1060 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1061 if (err) {
1062 netdev_err(dev, "Failed to set PAUSE parameters\n");
1063 goto err_port_pause_configure;
1064 }
1065
1066 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1067 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1068
1069 return 0;
1070
1071err_port_pause_configure:
1072 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1073 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1074 return err;
1075}
1076
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001077struct mlxsw_sp_port_hw_stats {
1078 char str[ETH_GSTRING_LEN];
1079 u64 (*getter)(char *payload);
1080};
1081
1082static const struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
1083 {
1084 .str = "a_frames_transmitted_ok",
1085 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1086 },
1087 {
1088 .str = "a_frames_received_ok",
1089 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1090 },
1091 {
1092 .str = "a_frame_check_sequence_errors",
1093 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1094 },
1095 {
1096 .str = "a_alignment_errors",
1097 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1098 },
1099 {
1100 .str = "a_octets_transmitted_ok",
1101 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1102 },
1103 {
1104 .str = "a_octets_received_ok",
1105 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1106 },
1107 {
1108 .str = "a_multicast_frames_xmitted_ok",
1109 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1110 },
1111 {
1112 .str = "a_broadcast_frames_xmitted_ok",
1113 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1114 },
1115 {
1116 .str = "a_multicast_frames_received_ok",
1117 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1118 },
1119 {
1120 .str = "a_broadcast_frames_received_ok",
1121 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1122 },
1123 {
1124 .str = "a_in_range_length_errors",
1125 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1126 },
1127 {
1128 .str = "a_out_of_range_length_field",
1129 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1130 },
1131 {
1132 .str = "a_frame_too_long_errors",
1133 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1134 },
1135 {
1136 .str = "a_symbol_error_during_carrier",
1137 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1138 },
1139 {
1140 .str = "a_mac_control_frames_transmitted",
1141 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1142 },
1143 {
1144 .str = "a_mac_control_frames_received",
1145 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1146 },
1147 {
1148 .str = "a_unsupported_opcodes_received",
1149 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1150 },
1151 {
1152 .str = "a_pause_mac_ctrl_frames_received",
1153 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1154 },
1155 {
1156 .str = "a_pause_mac_ctrl_frames_xmitted",
1157 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1158 },
1159};
1160
1161#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1162
1163static void mlxsw_sp_port_get_strings(struct net_device *dev,
1164 u32 stringset, u8 *data)
1165{
1166 u8 *p = data;
1167 int i;
1168
1169 switch (stringset) {
1170 case ETH_SS_STATS:
1171 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
1172 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
1173 ETH_GSTRING_LEN);
1174 p += ETH_GSTRING_LEN;
1175 }
1176 break;
1177 }
1178}
1179
Ido Schimmel3a66ee32015-11-27 13:45:55 +01001180static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
1181 enum ethtool_phys_id_state state)
1182{
1183 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1184 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1185 char mlcr_pl[MLXSW_REG_MLCR_LEN];
1186 bool active;
1187
1188 switch (state) {
1189 case ETHTOOL_ID_ACTIVE:
1190 active = true;
1191 break;
1192 case ETHTOOL_ID_INACTIVE:
1193 active = false;
1194 break;
1195 default:
1196 return -EOPNOTSUPP;
1197 }
1198
1199 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
1200 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
1201}
1202
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001203static void mlxsw_sp_port_get_stats(struct net_device *dev,
1204 struct ethtool_stats *stats, u64 *data)
1205{
1206 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1207 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1208 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1209 int i;
1210 int err;
1211
Ido Schimmel34dba0a2016-04-06 17:10:15 +02001212 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port,
1213 MLXSW_REG_PPCNT_IEEE_8023_CNT, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001214 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1215 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++)
1216 data[i] = !err ? mlxsw_sp_port_hw_stats[i].getter(ppcnt_pl) : 0;
1217}
1218
1219static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
1220{
1221 switch (sset) {
1222 case ETH_SS_STATS:
1223 return MLXSW_SP_PORT_HW_STATS_LEN;
1224 default:
1225 return -EOPNOTSUPP;
1226 }
1227}
1228
1229struct mlxsw_sp_port_link_mode {
1230 u32 mask;
1231 u32 supported;
1232 u32 advertised;
1233 u32 speed;
1234};
1235
1236static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
1237 {
1238 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
1239 .supported = SUPPORTED_100baseT_Full,
1240 .advertised = ADVERTISED_100baseT_Full,
1241 .speed = 100,
1242 },
1243 {
1244 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX,
1245 .speed = 100,
1246 },
1247 {
1248 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
1249 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
1250 .supported = SUPPORTED_1000baseKX_Full,
1251 .advertised = ADVERTISED_1000baseKX_Full,
1252 .speed = 1000,
1253 },
1254 {
1255 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
1256 .supported = SUPPORTED_10000baseT_Full,
1257 .advertised = ADVERTISED_10000baseT_Full,
1258 .speed = 10000,
1259 },
1260 {
1261 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
1262 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
1263 .supported = SUPPORTED_10000baseKX4_Full,
1264 .advertised = ADVERTISED_10000baseKX4_Full,
1265 .speed = 10000,
1266 },
1267 {
1268 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1269 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1270 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1271 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
1272 .supported = SUPPORTED_10000baseKR_Full,
1273 .advertised = ADVERTISED_10000baseKR_Full,
1274 .speed = 10000,
1275 },
1276 {
1277 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
1278 .supported = SUPPORTED_20000baseKR2_Full,
1279 .advertised = ADVERTISED_20000baseKR2_Full,
1280 .speed = 20000,
1281 },
1282 {
1283 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
1284 .supported = SUPPORTED_40000baseCR4_Full,
1285 .advertised = ADVERTISED_40000baseCR4_Full,
1286 .speed = 40000,
1287 },
1288 {
1289 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
1290 .supported = SUPPORTED_40000baseKR4_Full,
1291 .advertised = ADVERTISED_40000baseKR4_Full,
1292 .speed = 40000,
1293 },
1294 {
1295 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
1296 .supported = SUPPORTED_40000baseSR4_Full,
1297 .advertised = ADVERTISED_40000baseSR4_Full,
1298 .speed = 40000,
1299 },
1300 {
1301 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
1302 .supported = SUPPORTED_40000baseLR4_Full,
1303 .advertised = ADVERTISED_40000baseLR4_Full,
1304 .speed = 40000,
1305 },
1306 {
1307 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR |
1308 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR |
1309 MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
1310 .speed = 25000,
1311 },
1312 {
1313 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 |
1314 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 |
1315 MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
1316 .speed = 50000,
1317 },
1318 {
1319 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
1320 .supported = SUPPORTED_56000baseKR4_Full,
1321 .advertised = ADVERTISED_56000baseKR4_Full,
1322 .speed = 56000,
1323 },
1324 {
1325 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 |
1326 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1327 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1328 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
1329 .speed = 100000,
1330 },
1331};
1332
1333#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
1334
1335static u32 mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto)
1336{
1337 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1338 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1339 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1340 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1341 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1342 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1343 return SUPPORTED_FIBRE;
1344
1345 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1346 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1347 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1348 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
1349 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
1350 return SUPPORTED_Backplane;
1351 return 0;
1352}
1353
1354static u32 mlxsw_sp_from_ptys_supported_link(u32 ptys_eth_proto)
1355{
1356 u32 modes = 0;
1357 int i;
1358
1359 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1360 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1361 modes |= mlxsw_sp_port_link_mode[i].supported;
1362 }
1363 return modes;
1364}
1365
1366static u32 mlxsw_sp_from_ptys_advert_link(u32 ptys_eth_proto)
1367{
1368 u32 modes = 0;
1369 int i;
1370
1371 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1372 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
1373 modes |= mlxsw_sp_port_link_mode[i].advertised;
1374 }
1375 return modes;
1376}
1377
1378static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
1379 struct ethtool_cmd *cmd)
1380{
1381 u32 speed = SPEED_UNKNOWN;
1382 u8 duplex = DUPLEX_UNKNOWN;
1383 int i;
1384
1385 if (!carrier_ok)
1386 goto out;
1387
1388 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1389 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
1390 speed = mlxsw_sp_port_link_mode[i].speed;
1391 duplex = DUPLEX_FULL;
1392 break;
1393 }
1394 }
1395out:
1396 ethtool_cmd_speed_set(cmd, speed);
1397 cmd->duplex = duplex;
1398}
1399
1400static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
1401{
1402 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
1403 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
1404 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
1405 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
1406 return PORT_FIBRE;
1407
1408 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
1409 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
1410 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
1411 return PORT_DA;
1412
1413 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
1414 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
1415 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
1416 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
1417 return PORT_NONE;
1418
1419 return PORT_OTHER;
1420}
1421
1422static int mlxsw_sp_port_get_settings(struct net_device *dev,
1423 struct ethtool_cmd *cmd)
1424{
1425 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1426 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1427 char ptys_pl[MLXSW_REG_PTYS_LEN];
1428 u32 eth_proto_cap;
1429 u32 eth_proto_admin;
1430 u32 eth_proto_oper;
1431 int err;
1432
1433 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1434 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1435 if (err) {
1436 netdev_err(dev, "Failed to get proto");
1437 return err;
1438 }
1439 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap,
1440 &eth_proto_admin, &eth_proto_oper);
1441
1442 cmd->supported = mlxsw_sp_from_ptys_supported_port(eth_proto_cap) |
1443 mlxsw_sp_from_ptys_supported_link(eth_proto_cap) |
1444 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1445 cmd->advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_admin);
1446 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev),
1447 eth_proto_oper, cmd);
1448
1449 eth_proto_oper = eth_proto_oper ? eth_proto_oper : eth_proto_cap;
1450 cmd->port = mlxsw_sp_port_connector_port(eth_proto_oper);
1451 cmd->lp_advertising = mlxsw_sp_from_ptys_advert_link(eth_proto_oper);
1452
1453 cmd->transceiver = XCVR_INTERNAL;
1454 return 0;
1455}
1456
1457static u32 mlxsw_sp_to_ptys_advert_link(u32 advertising)
1458{
1459 u32 ptys_proto = 0;
1460 int i;
1461
1462 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1463 if (advertising & mlxsw_sp_port_link_mode[i].advertised)
1464 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1465 }
1466 return ptys_proto;
1467}
1468
1469static u32 mlxsw_sp_to_ptys_speed(u32 speed)
1470{
1471 u32 ptys_proto = 0;
1472 int i;
1473
1474 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1475 if (speed == mlxsw_sp_port_link_mode[i].speed)
1476 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1477 }
1478 return ptys_proto;
1479}
1480
Ido Schimmel18f1e702016-02-26 17:32:31 +01001481static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
1482{
1483 u32 ptys_proto = 0;
1484 int i;
1485
1486 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
1487 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
1488 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
1489 }
1490 return ptys_proto;
1491}
1492
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001493static int mlxsw_sp_port_set_settings(struct net_device *dev,
1494 struct ethtool_cmd *cmd)
1495{
1496 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1497 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1498 char ptys_pl[MLXSW_REG_PTYS_LEN];
1499 u32 speed;
1500 u32 eth_proto_new;
1501 u32 eth_proto_cap;
1502 u32 eth_proto_admin;
1503 bool is_up;
1504 int err;
1505
1506 speed = ethtool_cmd_speed(cmd);
1507
1508 eth_proto_new = cmd->autoneg == AUTONEG_ENABLE ?
1509 mlxsw_sp_to_ptys_advert_link(cmd->advertising) :
1510 mlxsw_sp_to_ptys_speed(speed);
1511
1512 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
1513 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1514 if (err) {
1515 netdev_err(dev, "Failed to get proto");
1516 return err;
1517 }
1518 mlxsw_reg_ptys_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin, NULL);
1519
1520 eth_proto_new = eth_proto_new & eth_proto_cap;
1521 if (!eth_proto_new) {
1522 netdev_err(dev, "Not supported proto admin requested");
1523 return -EINVAL;
1524 }
1525 if (eth_proto_new == eth_proto_admin)
1526 return 0;
1527
1528 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port, eth_proto_new);
1529 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1530 if (err) {
1531 netdev_err(dev, "Failed to set proto admin");
1532 return err;
1533 }
1534
1535 err = mlxsw_sp_port_oper_status_get(mlxsw_sp_port, &is_up);
1536 if (err) {
1537 netdev_err(dev, "Failed to get oper status");
1538 return err;
1539 }
1540 if (!is_up)
1541 return 0;
1542
1543 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1544 if (err) {
1545 netdev_err(dev, "Failed to set admin status");
1546 return err;
1547 }
1548
1549 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1550 if (err) {
1551 netdev_err(dev, "Failed to set admin status");
1552 return err;
1553 }
1554
1555 return 0;
1556}
1557
1558static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
1559 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
1560 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001561 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
1562 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001563 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01001564 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001565 .get_ethtool_stats = mlxsw_sp_port_get_stats,
1566 .get_sset_count = mlxsw_sp_port_get_sset_count,
1567 .get_settings = mlxsw_sp_port_get_settings,
1568 .set_settings = mlxsw_sp_port_set_settings,
1569};
1570
Ido Schimmel18f1e702016-02-26 17:32:31 +01001571static int
1572mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
1573{
1574 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1575 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
1576 char ptys_pl[MLXSW_REG_PTYS_LEN];
1577 u32 eth_proto_admin;
1578
1579 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
1580 mlxsw_reg_ptys_pack(ptys_pl, mlxsw_sp_port->local_port,
1581 eth_proto_admin);
1582 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
1583}
1584
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001585int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
1586 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
1587 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02001588{
1589 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1590 char qeec_pl[MLXSW_REG_QEEC_LEN];
1591
1592 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1593 next_index);
1594 mlxsw_reg_qeec_de_set(qeec_pl, true);
1595 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
1596 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
1597 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1598}
1599
Ido Schimmelcc7cf512016-04-06 17:10:11 +02001600int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
1601 enum mlxsw_reg_qeec_hr hr, u8 index,
1602 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02001603{
1604 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1605 char qeec_pl[MLXSW_REG_QEEC_LEN];
1606
1607 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
1608 next_index);
1609 mlxsw_reg_qeec_mase_set(qeec_pl, true);
1610 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
1611 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
1612}
1613
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001614int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
1615 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02001616{
1617 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1618 char qtct_pl[MLXSW_REG_QTCT_LEN];
1619
1620 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
1621 tclass);
1622 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
1623}
1624
1625static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
1626{
1627 int err, i;
1628
1629 /* Setup the elements hierarcy, so that each TC is linked to
1630 * one subgroup, which are all member in the same group.
1631 */
1632 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1633 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
1634 0);
1635 if (err)
1636 return err;
1637 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1638 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1639 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
1640 0, false, 0);
1641 if (err)
1642 return err;
1643 }
1644 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1645 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
1646 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
1647 false, 0);
1648 if (err)
1649 return err;
1650 }
1651
1652 /* Make sure the max shaper is disabled in all hierarcies that
1653 * support it.
1654 */
1655 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1656 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
1657 MLXSW_REG_QEEC_MAS_DIS);
1658 if (err)
1659 return err;
1660 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1661 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1662 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
1663 i, 0,
1664 MLXSW_REG_QEEC_MAS_DIS);
1665 if (err)
1666 return err;
1667 }
1668 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1669 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
1670 MLXSW_REG_QEEC_HIERARCY_TC,
1671 i, i,
1672 MLXSW_REG_QEEC_MAS_DIS);
1673 if (err)
1674 return err;
1675 }
1676
1677 /* Map all priorities to traffic class 0. */
1678 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1679 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
1680 if (err)
1681 return err;
1682 }
1683
1684 return 0;
1685}
1686
Ido Schimmelbe945352016-06-09 09:51:39 +02001687static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
Ido Schimmeld664b412016-06-09 09:51:40 +02001688 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001689{
1690 struct mlxsw_sp_port *mlxsw_sp_port;
1691 struct net_device *dev;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001692 size_t bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001693 int err;
1694
1695 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
1696 if (!dev)
1697 return -ENOMEM;
1698 mlxsw_sp_port = netdev_priv(dev);
1699 mlxsw_sp_port->dev = dev;
1700 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
1701 mlxsw_sp_port->local_port = local_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01001702 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02001703 mlxsw_sp_port->mapping.module = module;
1704 mlxsw_sp_port->mapping.width = width;
1705 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001706 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
1707 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
1708 if (!mlxsw_sp_port->active_vlans) {
1709 err = -ENOMEM;
1710 goto err_port_active_vlans_alloc;
1711 }
Elad Razfc1273a2016-01-06 13:01:11 +01001712 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
1713 if (!mlxsw_sp_port->untagged_vlans) {
1714 err = -ENOMEM;
1715 goto err_port_untagged_vlans_alloc;
1716 }
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001717 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001718
1719 mlxsw_sp_port->pcpu_stats =
1720 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
1721 if (!mlxsw_sp_port->pcpu_stats) {
1722 err = -ENOMEM;
1723 goto err_alloc_stats;
1724 }
1725
1726 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
1727 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
1728
1729 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
1730 if (err) {
1731 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
1732 mlxsw_sp_port->local_port);
1733 goto err_dev_addr_init;
1734 }
1735
1736 netif_carrier_off(dev);
1737
1738 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
1739 NETIF_F_HW_VLAN_CTAG_FILTER;
1740
1741 /* Each packet needs to have a Tx header (metadata) on top all other
1742 * headers.
1743 */
1744 dev->hard_header_len += MLXSW_TXHDR_LEN;
1745
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001746 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
1747 if (err) {
1748 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
1749 mlxsw_sp_port->local_port);
1750 goto err_port_system_port_mapping_set;
1751 }
1752
1753 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
1754 if (err) {
1755 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
1756 mlxsw_sp_port->local_port);
1757 goto err_port_swid_set;
1758 }
1759
Ido Schimmel18f1e702016-02-26 17:32:31 +01001760 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
1761 if (err) {
1762 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
1763 mlxsw_sp_port->local_port);
1764 goto err_port_speed_by_width_set;
1765 }
1766
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001767 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
1768 if (err) {
1769 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
1770 mlxsw_sp_port->local_port);
1771 goto err_port_mtu_set;
1772 }
1773
1774 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1775 if (err)
1776 goto err_port_admin_status_set;
1777
1778 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
1779 if (err) {
1780 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
1781 mlxsw_sp_port->local_port);
1782 goto err_port_buffers_init;
1783 }
1784
Ido Schimmel90183b92016-04-06 17:10:08 +02001785 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
1786 if (err) {
1787 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
1788 mlxsw_sp_port->local_port);
1789 goto err_port_ets_init;
1790 }
1791
Ido Schimmelf00817d2016-04-06 17:10:09 +02001792 /* ETS and buffers must be initialized before DCB. */
1793 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
1794 if (err) {
1795 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
1796 mlxsw_sp_port->local_port);
1797 goto err_port_dcb_init;
1798 }
1799
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001800 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
1801 err = register_netdev(dev);
1802 if (err) {
1803 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
1804 mlxsw_sp_port->local_port);
1805 goto err_register_netdev;
1806 }
1807
Jiri Pirko932762b2016-04-08 19:11:21 +02001808 err = mlxsw_core_port_init(mlxsw_sp->core, &mlxsw_sp_port->core_port,
1809 mlxsw_sp_port->local_port, dev,
1810 mlxsw_sp_port->split, module);
1811 if (err) {
1812 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
1813 mlxsw_sp_port->local_port);
1814 goto err_core_port_init;
1815 }
Jiri Pirkoc4745502016-02-26 17:32:26 +01001816
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001817 err = mlxsw_sp_port_vlan_init(mlxsw_sp_port);
1818 if (err)
1819 goto err_port_vlan_init;
1820
1821 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
1822 return 0;
1823
1824err_port_vlan_init:
Jiri Pirko932762b2016-04-08 19:11:21 +02001825 mlxsw_core_port_fini(&mlxsw_sp_port->core_port);
1826err_core_port_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001827 unregister_netdev(dev);
1828err_register_netdev:
Ido Schimmelf00817d2016-04-06 17:10:09 +02001829err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02001830err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001831err_port_buffers_init:
1832err_port_admin_status_set:
1833err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01001834err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001835err_port_swid_set:
1836err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001837err_dev_addr_init:
1838 free_percpu(mlxsw_sp_port->pcpu_stats);
1839err_alloc_stats:
Elad Razfc1273a2016-01-06 13:01:11 +01001840 kfree(mlxsw_sp_port->untagged_vlans);
1841err_port_untagged_vlans_alloc:
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001842 kfree(mlxsw_sp_port->active_vlans);
1843err_port_active_vlans_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001844 free_netdev(dev);
1845 return err;
1846}
1847
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001848static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
1849{
1850 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
1851
1852 if (!mlxsw_sp_port)
1853 return;
Ido Schimmela1333182016-02-26 17:32:30 +01001854 mlxsw_sp->ports[local_port] = NULL;
Jiri Pirko932762b2016-04-08 19:11:21 +02001855 mlxsw_core_port_fini(&mlxsw_sp_port->core_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001856 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmelf00817d2016-04-06 17:10:09 +02001857 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel32d863f2016-07-02 11:00:10 +02001858 mlxsw_sp_port_kill_vid(mlxsw_sp_port->dev, 0, 1);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001859 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01001860 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
1861 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001862 free_percpu(mlxsw_sp_port->pcpu_stats);
Elad Razfc1273a2016-01-06 13:01:11 +01001863 kfree(mlxsw_sp_port->untagged_vlans);
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01001864 kfree(mlxsw_sp_port->active_vlans);
Ido Schimmel32d863f2016-07-02 11:00:10 +02001865 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vports_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001866 free_netdev(mlxsw_sp_port->dev);
1867}
1868
1869static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
1870{
1871 int i;
1872
1873 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++)
1874 mlxsw_sp_port_remove(mlxsw_sp, i);
1875 kfree(mlxsw_sp->ports);
1876}
1877
1878static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
1879{
Ido Schimmeld664b412016-06-09 09:51:40 +02001880 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001881 size_t alloc_size;
1882 int i;
1883 int err;
1884
1885 alloc_size = sizeof(struct mlxsw_sp_port *) * MLXSW_PORT_MAX_PORTS;
1886 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
1887 if (!mlxsw_sp->ports)
1888 return -ENOMEM;
1889
1890 for (i = 1; i < MLXSW_PORT_MAX_PORTS; i++) {
Ido Schimmel558c2d52016-02-26 17:32:29 +01001891 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02001892 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01001893 if (err)
1894 goto err_port_module_info_get;
1895 if (!width)
1896 continue;
1897 mlxsw_sp->port_to_module[i] = module;
Ido Schimmeld664b412016-06-09 09:51:40 +02001898 err = mlxsw_sp_port_create(mlxsw_sp, i, false, module, width,
1899 lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001900 if (err)
1901 goto err_port_create;
1902 }
1903 return 0;
1904
1905err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01001906err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001907 for (i--; i >= 1; i--)
1908 mlxsw_sp_port_remove(mlxsw_sp, i);
1909 kfree(mlxsw_sp->ports);
1910 return err;
1911}
1912
Ido Schimmel18f1e702016-02-26 17:32:31 +01001913static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
1914{
1915 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
1916
1917 return local_port - offset;
1918}
1919
Ido Schimmelbe945352016-06-09 09:51:39 +02001920static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
1921 u8 module, unsigned int count)
1922{
1923 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
1924 int err, i;
1925
1926 for (i = 0; i < count; i++) {
1927 err = mlxsw_sp_port_module_map(mlxsw_sp, base_port + i, module,
1928 width, i * width);
1929 if (err)
1930 goto err_port_module_map;
1931 }
1932
1933 for (i = 0; i < count; i++) {
1934 err = __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i, 0);
1935 if (err)
1936 goto err_port_swid_set;
1937 }
1938
1939 for (i = 0; i < count; i++) {
1940 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02001941 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02001942 if (err)
1943 goto err_port_create;
1944 }
1945
1946 return 0;
1947
1948err_port_create:
1949 for (i--; i >= 0; i--)
1950 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
1951 i = count;
1952err_port_swid_set:
1953 for (i--; i >= 0; i--)
1954 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i,
1955 MLXSW_PORT_SWID_DISABLED_PORT);
1956 i = count;
1957err_port_module_map:
1958 for (i--; i >= 0; i--)
1959 mlxsw_sp_port_module_unmap(mlxsw_sp, base_port + i);
1960 return err;
1961}
1962
1963static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
1964 u8 base_port, unsigned int count)
1965{
1966 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
1967 int i;
1968
1969 /* Split by four means we need to re-create two ports, otherwise
1970 * only one.
1971 */
1972 count = count / 2;
1973
1974 for (i = 0; i < count; i++) {
1975 local_port = base_port + i * 2;
1976 module = mlxsw_sp->port_to_module[local_port];
1977
1978 mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
1979 0);
1980 }
1981
1982 for (i = 0; i < count; i++)
1983 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i * 2, 0);
1984
1985 for (i = 0; i < count; i++) {
1986 local_port = base_port + i * 2;
1987 module = mlxsw_sp->port_to_module[local_port];
1988
1989 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02001990 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02001991 }
1992}
1993
Jiri Pirkob2f10572016-04-08 19:11:23 +02001994static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
1995 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01001996{
Jiri Pirkob2f10572016-04-08 19:11:23 +02001997 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01001998 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01001999 u8 module, cur_width, base_port;
2000 int i;
2001 int err;
2002
2003 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2004 if (!mlxsw_sp_port) {
2005 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2006 local_port);
2007 return -EINVAL;
2008 }
2009
Ido Schimmeld664b412016-06-09 09:51:40 +02002010 module = mlxsw_sp_port->mapping.module;
2011 cur_width = mlxsw_sp_port->mapping.width;
2012
Ido Schimmel18f1e702016-02-26 17:32:31 +01002013 if (count != 2 && count != 4) {
2014 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
2015 return -EINVAL;
2016 }
2017
Ido Schimmel18f1e702016-02-26 17:32:31 +01002018 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
2019 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
2020 return -EINVAL;
2021 }
2022
2023 /* Make sure we have enough slave (even) ports for the split. */
2024 if (count == 2) {
2025 base_port = local_port;
2026 if (mlxsw_sp->ports[base_port + 1]) {
2027 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2028 return -EINVAL;
2029 }
2030 } else {
2031 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2032 if (mlxsw_sp->ports[base_port + 1] ||
2033 mlxsw_sp->ports[base_port + 3]) {
2034 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
2035 return -EINVAL;
2036 }
2037 }
2038
2039 for (i = 0; i < count; i++)
2040 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2041
Ido Schimmelbe945352016-06-09 09:51:39 +02002042 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
2043 if (err) {
2044 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
2045 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002046 }
2047
2048 return 0;
2049
Ido Schimmelbe945352016-06-09 09:51:39 +02002050err_port_split_create:
2051 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002052 return err;
2053}
2054
Jiri Pirkob2f10572016-04-08 19:11:23 +02002055static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01002056{
Jiri Pirkob2f10572016-04-08 19:11:23 +02002057 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002058 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02002059 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002060 unsigned int count;
2061 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002062
2063 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2064 if (!mlxsw_sp_port) {
2065 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
2066 local_port);
2067 return -EINVAL;
2068 }
2069
2070 if (!mlxsw_sp_port->split) {
2071 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
2072 return -EINVAL;
2073 }
2074
Ido Schimmeld664b412016-06-09 09:51:40 +02002075 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002076 count = cur_width == 1 ? 4 : 2;
2077
2078 base_port = mlxsw_sp_cluster_base_port_get(local_port);
2079
2080 /* Determine which ports to remove. */
2081 if (count == 2 && local_port >= base_port + 2)
2082 base_port = base_port + 2;
2083
2084 for (i = 0; i < count; i++)
2085 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
2086
Ido Schimmelbe945352016-06-09 09:51:39 +02002087 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002088
2089 return 0;
2090}
2091
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002092static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
2093 char *pude_pl, void *priv)
2094{
2095 struct mlxsw_sp *mlxsw_sp = priv;
2096 struct mlxsw_sp_port *mlxsw_sp_port;
2097 enum mlxsw_reg_pude_oper_status status;
2098 u8 local_port;
2099
2100 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
2101 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02002102 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002103 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002104
2105 status = mlxsw_reg_pude_oper_status_get(pude_pl);
2106 if (status == MLXSW_PORT_OPER_STATUS_UP) {
2107 netdev_info(mlxsw_sp_port->dev, "link up\n");
2108 netif_carrier_on(mlxsw_sp_port->dev);
2109 } else {
2110 netdev_info(mlxsw_sp_port->dev, "link down\n");
2111 netif_carrier_off(mlxsw_sp_port->dev);
2112 }
2113}
2114
2115static struct mlxsw_event_listener mlxsw_sp_pude_event = {
2116 .func = mlxsw_sp_pude_event_func,
2117 .trap_id = MLXSW_TRAP_ID_PUDE,
2118};
2119
2120static int mlxsw_sp_event_register(struct mlxsw_sp *mlxsw_sp,
2121 enum mlxsw_event_trap_id trap_id)
2122{
2123 struct mlxsw_event_listener *el;
2124 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2125 int err;
2126
2127 switch (trap_id) {
2128 case MLXSW_TRAP_ID_PUDE:
2129 el = &mlxsw_sp_pude_event;
2130 break;
2131 }
2132 err = mlxsw_core_event_listener_register(mlxsw_sp->core, el, mlxsw_sp);
2133 if (err)
2134 return err;
2135
2136 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_FORWARD, trap_id);
2137 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2138 if (err)
2139 goto err_event_trap_set;
2140
2141 return 0;
2142
2143err_event_trap_set:
2144 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2145 return err;
2146}
2147
2148static void mlxsw_sp_event_unregister(struct mlxsw_sp *mlxsw_sp,
2149 enum mlxsw_event_trap_id trap_id)
2150{
2151 struct mlxsw_event_listener *el;
2152
2153 switch (trap_id) {
2154 case MLXSW_TRAP_ID_PUDE:
2155 el = &mlxsw_sp_pude_event;
2156 break;
2157 }
2158 mlxsw_core_event_listener_unregister(mlxsw_sp->core, el, mlxsw_sp);
2159}
2160
2161static void mlxsw_sp_rx_listener_func(struct sk_buff *skb, u8 local_port,
2162 void *priv)
2163{
2164 struct mlxsw_sp *mlxsw_sp = priv;
2165 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2166 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
2167
2168 if (unlikely(!mlxsw_sp_port)) {
2169 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
2170 local_port);
2171 return;
2172 }
2173
2174 skb->dev = mlxsw_sp_port->dev;
2175
2176 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
2177 u64_stats_update_begin(&pcpu_stats->syncp);
2178 pcpu_stats->rx_packets++;
2179 pcpu_stats->rx_bytes += skb->len;
2180 u64_stats_update_end(&pcpu_stats->syncp);
2181
2182 skb->protocol = eth_type_trans(skb, skb->dev);
2183 netif_receive_skb(skb);
2184}
2185
2186static const struct mlxsw_rx_listener mlxsw_sp_rx_listener[] = {
2187 {
2188 .func = mlxsw_sp_rx_listener_func,
2189 .local_port = MLXSW_PORT_DONT_CARE,
2190 .trap_id = MLXSW_TRAP_ID_FDB_MC,
2191 },
2192 /* Traps for specific L2 packet types, not trapped as FDB MC */
2193 {
2194 .func = mlxsw_sp_rx_listener_func,
2195 .local_port = MLXSW_PORT_DONT_CARE,
2196 .trap_id = MLXSW_TRAP_ID_STP,
2197 },
2198 {
2199 .func = mlxsw_sp_rx_listener_func,
2200 .local_port = MLXSW_PORT_DONT_CARE,
2201 .trap_id = MLXSW_TRAP_ID_LACP,
2202 },
2203 {
2204 .func = mlxsw_sp_rx_listener_func,
2205 .local_port = MLXSW_PORT_DONT_CARE,
2206 .trap_id = MLXSW_TRAP_ID_EAPOL,
2207 },
2208 {
2209 .func = mlxsw_sp_rx_listener_func,
2210 .local_port = MLXSW_PORT_DONT_CARE,
2211 .trap_id = MLXSW_TRAP_ID_LLDP,
2212 },
2213 {
2214 .func = mlxsw_sp_rx_listener_func,
2215 .local_port = MLXSW_PORT_DONT_CARE,
2216 .trap_id = MLXSW_TRAP_ID_MMRP,
2217 },
2218 {
2219 .func = mlxsw_sp_rx_listener_func,
2220 .local_port = MLXSW_PORT_DONT_CARE,
2221 .trap_id = MLXSW_TRAP_ID_MVRP,
2222 },
2223 {
2224 .func = mlxsw_sp_rx_listener_func,
2225 .local_port = MLXSW_PORT_DONT_CARE,
2226 .trap_id = MLXSW_TRAP_ID_RPVST,
2227 },
2228 {
2229 .func = mlxsw_sp_rx_listener_func,
2230 .local_port = MLXSW_PORT_DONT_CARE,
2231 .trap_id = MLXSW_TRAP_ID_DHCP,
2232 },
2233 {
2234 .func = mlxsw_sp_rx_listener_func,
2235 .local_port = MLXSW_PORT_DONT_CARE,
2236 .trap_id = MLXSW_TRAP_ID_IGMP_QUERY,
2237 },
2238 {
2239 .func = mlxsw_sp_rx_listener_func,
2240 .local_port = MLXSW_PORT_DONT_CARE,
2241 .trap_id = MLXSW_TRAP_ID_IGMP_V1_REPORT,
2242 },
2243 {
2244 .func = mlxsw_sp_rx_listener_func,
2245 .local_port = MLXSW_PORT_DONT_CARE,
2246 .trap_id = MLXSW_TRAP_ID_IGMP_V2_REPORT,
2247 },
2248 {
2249 .func = mlxsw_sp_rx_listener_func,
2250 .local_port = MLXSW_PORT_DONT_CARE,
2251 .trap_id = MLXSW_TRAP_ID_IGMP_V2_LEAVE,
2252 },
2253 {
2254 .func = mlxsw_sp_rx_listener_func,
2255 .local_port = MLXSW_PORT_DONT_CARE,
2256 .trap_id = MLXSW_TRAP_ID_IGMP_V3_REPORT,
2257 },
Jiri Pirko7b27ce72016-07-02 11:00:20 +02002258 {
2259 .func = mlxsw_sp_rx_listener_func,
2260 .local_port = MLXSW_PORT_DONT_CARE,
2261 .trap_id = MLXSW_TRAP_ID_ARPBC,
2262 },
2263 {
2264 .func = mlxsw_sp_rx_listener_func,
2265 .local_port = MLXSW_PORT_DONT_CARE,
2266 .trap_id = MLXSW_TRAP_ID_ARPUC,
2267 },
2268 {
2269 .func = mlxsw_sp_rx_listener_func,
2270 .local_port = MLXSW_PORT_DONT_CARE,
2271 .trap_id = MLXSW_TRAP_ID_IP2ME,
2272 },
2273 {
2274 .func = mlxsw_sp_rx_listener_func,
2275 .local_port = MLXSW_PORT_DONT_CARE,
2276 .trap_id = MLXSW_TRAP_ID_RTR_INGRESS0,
2277 },
2278 {
2279 .func = mlxsw_sp_rx_listener_func,
2280 .local_port = MLXSW_PORT_DONT_CARE,
2281 .trap_id = MLXSW_TRAP_ID_HOST_MISS_IPV4,
2282 },
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002283};
2284
2285static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
2286{
2287 char htgt_pl[MLXSW_REG_HTGT_LEN];
2288 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2289 int i;
2290 int err;
2291
2292 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_RX);
2293 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2294 if (err)
2295 return err;
2296
2297 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_CTRL);
2298 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(htgt), htgt_pl);
2299 if (err)
2300 return err;
2301
2302 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
2303 err = mlxsw_core_rx_listener_register(mlxsw_sp->core,
2304 &mlxsw_sp_rx_listener[i],
2305 mlxsw_sp);
2306 if (err)
2307 goto err_rx_listener_register;
2308
2309 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
2310 mlxsw_sp_rx_listener[i].trap_id);
2311 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2312 if (err)
2313 goto err_rx_trap_set;
2314 }
2315 return 0;
2316
2317err_rx_trap_set:
2318 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2319 &mlxsw_sp_rx_listener[i],
2320 mlxsw_sp);
2321err_rx_listener_register:
2322 for (i--; i >= 0; i--) {
Ido Schimmel10f00aa2016-07-02 11:00:19 +02002323 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_DISCARD,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002324 mlxsw_sp_rx_listener[i].trap_id);
2325 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2326
2327 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2328 &mlxsw_sp_rx_listener[i],
2329 mlxsw_sp);
2330 }
2331 return err;
2332}
2333
2334static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
2335{
2336 char hpkt_pl[MLXSW_REG_HPKT_LEN];
2337 int i;
2338
2339 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_rx_listener); i++) {
Ido Schimmel10f00aa2016-07-02 11:00:19 +02002340 mlxsw_reg_hpkt_pack(hpkt_pl, MLXSW_REG_HPKT_ACTION_DISCARD,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002341 mlxsw_sp_rx_listener[i].trap_id);
2342 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(hpkt), hpkt_pl);
2343
2344 mlxsw_core_rx_listener_unregister(mlxsw_sp->core,
2345 &mlxsw_sp_rx_listener[i],
2346 mlxsw_sp);
2347 }
2348}
2349
2350static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
2351 enum mlxsw_reg_sfgc_type type,
2352 enum mlxsw_reg_sfgc_bridge_type bridge_type)
2353{
2354 enum mlxsw_flood_table_type table_type;
2355 enum mlxsw_sp_flood_table flood_table;
2356 char sfgc_pl[MLXSW_REG_SFGC_LEN];
2357
Ido Schimmel19ae6122015-12-15 16:03:39 +01002358 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002359 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
Ido Schimmel19ae6122015-12-15 16:03:39 +01002360 else
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002361 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
Ido Schimmel19ae6122015-12-15 16:03:39 +01002362
2363 if (type == MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST)
2364 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
2365 else
2366 flood_table = MLXSW_SP_FLOOD_TABLE_BM;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002367
2368 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
2369 flood_table);
2370 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
2371}
2372
2373static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
2374{
2375 int type, err;
2376
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002377 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
2378 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
2379 continue;
2380
2381 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2382 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
2383 if (err)
2384 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002385
2386 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
2387 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
2388 if (err)
2389 return err;
2390 }
2391
2392 return 0;
2393}
2394
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002395static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
2396{
2397 char slcr_pl[MLXSW_REG_SLCR_LEN];
2398
2399 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
2400 MLXSW_REG_SLCR_LAG_HASH_DMAC |
2401 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
2402 MLXSW_REG_SLCR_LAG_HASH_VLANID |
2403 MLXSW_REG_SLCR_LAG_HASH_SIP |
2404 MLXSW_REG_SLCR_LAG_HASH_DIP |
2405 MLXSW_REG_SLCR_LAG_HASH_SPORT |
2406 MLXSW_REG_SLCR_LAG_HASH_DPORT |
2407 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
2408 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
2409}
2410
Jiri Pirkob2f10572016-04-08 19:11:23 +02002411static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002412 const struct mlxsw_bus_info *mlxsw_bus_info)
2413{
Jiri Pirkob2f10572016-04-08 19:11:23 +02002414 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002415 int err;
2416
2417 mlxsw_sp->core = mlxsw_core;
2418 mlxsw_sp->bus_info = mlxsw_bus_info;
Ido Schimmel14d39462016-06-20 23:04:15 +02002419 INIT_LIST_HEAD(&mlxsw_sp->fids);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01002420 INIT_LIST_HEAD(&mlxsw_sp->port_vfids.list);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01002421 INIT_LIST_HEAD(&mlxsw_sp->br_vfids.list);
Elad Raz3a49b4f2016-01-10 21:06:28 +01002422 INIT_LIST_HEAD(&mlxsw_sp->br_mids.list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002423
2424 err = mlxsw_sp_base_mac_get(mlxsw_sp);
2425 if (err) {
2426 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
2427 return err;
2428 }
2429
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002430 err = mlxsw_sp_event_register(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
2431 if (err) {
2432 dev_err(mlxsw_sp->bus_info->dev, "Failed to register for PUDE events\n");
Ido Schimmelbbf2a472016-07-02 11:00:14 +02002433 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002434 }
2435
2436 err = mlxsw_sp_traps_init(mlxsw_sp);
2437 if (err) {
2438 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps for RX\n");
2439 goto err_rx_listener_register;
2440 }
2441
2442 err = mlxsw_sp_flood_init(mlxsw_sp);
2443 if (err) {
2444 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
2445 goto err_flood_init;
2446 }
2447
2448 err = mlxsw_sp_buffers_init(mlxsw_sp);
2449 if (err) {
2450 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
2451 goto err_buffers_init;
2452 }
2453
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002454 err = mlxsw_sp_lag_init(mlxsw_sp);
2455 if (err) {
2456 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
2457 goto err_lag_init;
2458 }
2459
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002460 err = mlxsw_sp_switchdev_init(mlxsw_sp);
2461 if (err) {
2462 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
2463 goto err_switchdev_init;
2464 }
2465
Ido Schimmel464dce12016-07-02 11:00:15 +02002466 err = mlxsw_sp_router_init(mlxsw_sp);
2467 if (err) {
2468 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
2469 goto err_router_init;
2470 }
2471
Ido Schimmelbbf2a472016-07-02 11:00:14 +02002472 err = mlxsw_sp_ports_create(mlxsw_sp);
2473 if (err) {
2474 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
2475 goto err_ports_create;
2476 }
2477
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002478 return 0;
2479
Ido Schimmelbbf2a472016-07-02 11:00:14 +02002480err_ports_create:
Ido Schimmel464dce12016-07-02 11:00:15 +02002481 mlxsw_sp_router_fini(mlxsw_sp);
2482err_router_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02002483 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002484err_switchdev_init:
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002485err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02002486 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002487err_buffers_init:
2488err_flood_init:
2489 mlxsw_sp_traps_fini(mlxsw_sp);
2490err_rx_listener_register:
2491 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002492 return err;
2493}
2494
Jiri Pirkob2f10572016-04-08 19:11:23 +02002495static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002496{
Jiri Pirkob2f10572016-04-08 19:11:23 +02002497 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmelfa3054f2016-07-02 11:00:16 +02002498 int i;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002499
Ido Schimmelbbf2a472016-07-02 11:00:14 +02002500 mlxsw_sp_ports_remove(mlxsw_sp);
Ido Schimmel464dce12016-07-02 11:00:15 +02002501 mlxsw_sp_router_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002502 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02002503 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002504 mlxsw_sp_traps_fini(mlxsw_sp);
2505 mlxsw_sp_event_unregister(mlxsw_sp, MLXSW_TRAP_ID_PUDE);
Ido Schimmel14d39462016-06-20 23:04:15 +02002506 WARN_ON(!list_empty(&mlxsw_sp->fids));
Ido Schimmelfa3054f2016-07-02 11:00:16 +02002507 for (i = 0; i < MLXSW_SP_RIF_MAX; i++)
2508 WARN_ON_ONCE(mlxsw_sp->rifs[i]);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002509}
2510
2511static struct mlxsw_config_profile mlxsw_sp_config_profile = {
2512 .used_max_vepa_channels = 1,
2513 .max_vepa_channels = 0,
2514 .used_max_lag = 1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002515 .max_lag = MLXSW_SP_LAG_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002516 .used_max_port_per_lag = 1,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002517 .max_port_per_lag = MLXSW_SP_PORT_PER_LAG_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002518 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01002519 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002520 .used_max_pgt = 1,
2521 .max_pgt = 0,
2522 .used_max_system_port = 1,
2523 .max_system_port = 64,
2524 .used_max_vlan_groups = 1,
2525 .max_vlan_groups = 127,
2526 .used_max_regions = 1,
2527 .max_regions = 400,
2528 .used_flood_tables = 1,
2529 .used_flood_mode = 1,
2530 .flood_mode = 3,
2531 .max_fid_offset_flood_tables = 2,
2532 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Ido Schimmel19ae6122015-12-15 16:03:39 +01002533 .max_fid_flood_tables = 2,
2534 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002535 .used_max_ib_mc = 1,
2536 .max_ib_mc = 0,
2537 .used_max_pkey = 1,
2538 .max_pkey = 0,
2539 .swid_config = {
2540 {
2541 .used_type = 1,
2542 .type = MLXSW_PORT_SWID_TYPE_ETH,
2543 }
2544 },
2545};
2546
2547static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko2d0ed392016-04-14 18:19:30 +02002548 .kind = MLXSW_DEVICE_KIND_SPECTRUM,
2549 .owner = THIS_MODULE,
2550 .priv_size = sizeof(struct mlxsw_sp),
2551 .init = mlxsw_sp_init,
2552 .fini = mlxsw_sp_fini,
2553 .port_split = mlxsw_sp_port_split,
2554 .port_unsplit = mlxsw_sp_port_unsplit,
2555 .sb_pool_get = mlxsw_sp_sb_pool_get,
2556 .sb_pool_set = mlxsw_sp_sb_pool_set,
2557 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
2558 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
2559 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
2560 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
2561 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
2562 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
2563 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
2564 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
2565 .txhdr_construct = mlxsw_sp_txhdr_construct,
2566 .txhdr_len = MLXSW_TXHDR_LEN,
2567 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002568};
2569
Jiri Pirko7ce856a2016-07-04 08:23:12 +02002570static bool mlxsw_sp_port_dev_check(const struct net_device *dev)
2571{
2572 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
2573}
2574
2575static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
2576{
2577 struct net_device *lower_dev;
2578 struct list_head *iter;
2579
2580 if (mlxsw_sp_port_dev_check(dev))
2581 return netdev_priv(dev);
2582
2583 netdev_for_each_all_lower_dev(dev, lower_dev, iter) {
2584 if (mlxsw_sp_port_dev_check(lower_dev))
2585 return netdev_priv(lower_dev);
2586 }
2587 return NULL;
2588}
2589
2590static struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
2591{
2592 struct mlxsw_sp_port *mlxsw_sp_port;
2593
2594 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
2595 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
2596}
2597
2598static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
2599{
2600 struct net_device *lower_dev;
2601 struct list_head *iter;
2602
2603 if (mlxsw_sp_port_dev_check(dev))
2604 return netdev_priv(dev);
2605
2606 netdev_for_each_all_lower_dev_rcu(dev, lower_dev, iter) {
2607 if (mlxsw_sp_port_dev_check(lower_dev))
2608 return netdev_priv(lower_dev);
2609 }
2610 return NULL;
2611}
2612
2613struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
2614{
2615 struct mlxsw_sp_port *mlxsw_sp_port;
2616
2617 rcu_read_lock();
2618 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
2619 if (mlxsw_sp_port)
2620 dev_hold(mlxsw_sp_port->dev);
2621 rcu_read_unlock();
2622 return mlxsw_sp_port;
2623}
2624
2625void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
2626{
2627 dev_put(mlxsw_sp_port->dev);
2628}
2629
Ido Schimmel6e095fd2016-07-04 08:23:13 +02002630static int mlxsw_sp_rif_edit(struct mlxsw_sp *mlxsw_sp, u16 rif,
2631 const char *mac, int mtu)
2632{
2633 char ritr_pl[MLXSW_REG_RITR_LEN];
2634 int err;
2635
2636 mlxsw_reg_ritr_rif_pack(ritr_pl, rif);
2637 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
2638 if (err)
2639 return err;
2640
2641 mlxsw_reg_ritr_mtu_set(ritr_pl, mtu);
2642 mlxsw_reg_ritr_if_mac_memcpy_to(ritr_pl, mac);
2643 mlxsw_reg_ritr_op_set(ritr_pl, MLXSW_REG_RITR_RIF_CREATE);
2644 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ritr), ritr_pl);
2645}
2646
2647static int mlxsw_sp_netdevice_router_port_event(struct net_device *dev)
2648{
2649 struct mlxsw_sp *mlxsw_sp;
2650 struct mlxsw_sp_rif *r;
2651 int err;
2652
2653 mlxsw_sp = mlxsw_sp_lower_get(dev);
2654 if (!mlxsw_sp)
2655 return 0;
2656
2657 r = mlxsw_sp_rif_find_by_dev(mlxsw_sp, dev);
2658 if (!r)
2659 return 0;
2660
2661 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, r->addr, r->f->fid, false);
2662 if (err)
2663 return err;
2664
2665 err = mlxsw_sp_rif_edit(mlxsw_sp, r->rif, dev->dev_addr, dev->mtu);
2666 if (err)
2667 goto err_rif_edit;
2668
2669 err = mlxsw_sp_rif_fdb_op(mlxsw_sp, dev->dev_addr, r->f->fid, true);
2670 if (err)
2671 goto err_rif_fdb_op;
2672
2673 ether_addr_copy(r->addr, dev->dev_addr);
2674 r->mtu = dev->mtu;
2675
2676 netdev_dbg(dev, "Updated RIF=%d\n", r->rif);
2677
2678 return 0;
2679
2680err_rif_fdb_op:
2681 mlxsw_sp_rif_edit(mlxsw_sp, r->rif, r->addr, r->mtu);
2682err_rif_edit:
2683 mlxsw_sp_rif_fdb_op(mlxsw_sp, r->addr, r->f->fid, true);
2684 return err;
2685}
2686
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02002687static bool mlxsw_sp_lag_port_fid_member(struct mlxsw_sp_port *lag_port,
2688 u16 fid)
2689{
2690 if (mlxsw_sp_fid_is_vfid(fid))
2691 return mlxsw_sp_port_vport_find_by_fid(lag_port, fid);
2692 else
2693 return test_bit(fid, lag_port->active_vlans);
2694}
2695
2696static bool mlxsw_sp_port_fdb_should_flush(struct mlxsw_sp_port *mlxsw_sp_port,
2697 u16 fid)
Ido Schimmel039c49a2016-01-27 15:20:18 +01002698{
2699 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02002700 u8 local_port = mlxsw_sp_port->local_port;
2701 u16 lag_id = mlxsw_sp_port->lag_id;
2702 int i, count = 0;
Ido Schimmel039c49a2016-01-27 15:20:18 +01002703
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02002704 if (!mlxsw_sp_port->lagged)
2705 return true;
Ido Schimmel039c49a2016-01-27 15:20:18 +01002706
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02002707 for (i = 0; i < MLXSW_SP_PORT_PER_LAG_MAX; i++) {
2708 struct mlxsw_sp_port *lag_port;
2709
2710 lag_port = mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i);
2711 if (!lag_port || lag_port->local_port == local_port)
2712 continue;
2713 if (mlxsw_sp_lag_port_fid_member(lag_port, fid))
2714 count++;
2715 }
2716
2717 return !count;
Ido Schimmel039c49a2016-01-27 15:20:18 +01002718}
2719
2720static int
2721mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2722 u16 fid)
2723{
2724 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2725 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2726
2727 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
2728 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2729 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
2730 mlxsw_sp_port->local_port);
2731
Ido Schimmel22305372016-06-20 23:04:21 +02002732 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using Port=%d, FID=%d\n",
2733 mlxsw_sp_port->local_port, fid);
2734
Ido Schimmel039c49a2016-01-27 15:20:18 +01002735 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2736}
2737
2738static int
Ido Schimmel039c49a2016-01-27 15:20:18 +01002739mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
2740 u16 fid)
2741{
2742 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2743 char sfdf_pl[MLXSW_REG_SFDF_LEN];
2744
2745 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
2746 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
2747 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
2748
Ido Schimmel22305372016-06-20 23:04:21 +02002749 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using LAG ID=%d, FID=%d\n",
2750 mlxsw_sp_port->lag_id, fid);
2751
Ido Schimmel039c49a2016-01-27 15:20:18 +01002752 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
2753}
2754
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02002755int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid)
Ido Schimmel039c49a2016-01-27 15:20:18 +01002756{
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02002757 if (!mlxsw_sp_port_fdb_should_flush(mlxsw_sp_port, fid))
2758 return 0;
Ido Schimmel039c49a2016-01-27 15:20:18 +01002759
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02002760 if (mlxsw_sp_port->lagged)
2761 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port,
Ido Schimmel039c49a2016-01-27 15:20:18 +01002762 fid);
2763 else
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02002764 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, fid);
Ido Schimmel039c49a2016-01-27 15:20:18 +01002765}
2766
Ido Schimmel7117a572016-06-20 23:04:06 +02002767static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
2768 struct net_device *br_dev)
2769{
2770 return !mlxsw_sp->master_bridge.dev ||
2771 mlxsw_sp->master_bridge.dev == br_dev;
2772}
2773
2774static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
2775 struct net_device *br_dev)
2776{
2777 mlxsw_sp->master_bridge.dev = br_dev;
2778 mlxsw_sp->master_bridge.ref_count++;
2779}
2780
2781static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp)
2782{
2783 if (--mlxsw_sp->master_bridge.ref_count == 0)
2784 mlxsw_sp->master_bridge.dev = NULL;
2785}
2786
2787static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port,
2788 struct net_device *br_dev)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002789{
2790 struct net_device *dev = mlxsw_sp_port->dev;
2791 int err;
2792
2793 /* When port is not bridged untagged packets are tagged with
2794 * PVID=VID=1, thereby creating an implicit VLAN interface in
2795 * the device. Remove it and let bridge code take care of its
2796 * own VLANs.
2797 */
2798 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01002799 if (err)
2800 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002801
Ido Schimmel7117a572016-06-20 23:04:06 +02002802 mlxsw_sp_master_bridge_inc(mlxsw_sp_port->mlxsw_sp, br_dev);
2803
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01002804 mlxsw_sp_port->learning = 1;
2805 mlxsw_sp_port->learning_sync = 1;
2806 mlxsw_sp_port->uc_flood = 1;
2807 mlxsw_sp_port->bridged = 1;
2808
2809 return 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002810}
2811
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02002812static void mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002813{
2814 struct net_device *dev = mlxsw_sp_port->dev;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01002815
Ido Schimmel28a01d22016-02-18 11:30:02 +01002816 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
2817
Ido Schimmel7117a572016-06-20 23:04:06 +02002818 mlxsw_sp_master_bridge_dec(mlxsw_sp_port->mlxsw_sp);
2819
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01002820 mlxsw_sp_port->learning = 0;
2821 mlxsw_sp_port->learning_sync = 0;
2822 mlxsw_sp_port->uc_flood = 0;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01002823 mlxsw_sp_port->bridged = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002824
2825 /* Add implicit VLAN interface in the device, so that untagged
2826 * packets will be classified to the default vFID.
2827 */
Ido Schimmel82e6db02016-06-20 23:04:04 +02002828 mlxsw_sp_port_add_vid(dev, 0, 1);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002829}
2830
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002831static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002832{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002833 char sldr_pl[MLXSW_REG_SLDR_LEN];
2834
2835 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
2836 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2837}
2838
2839static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
2840{
2841 char sldr_pl[MLXSW_REG_SLDR_LEN];
2842
2843 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
2844 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
2845}
2846
2847static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
2848 u16 lag_id, u8 port_index)
2849{
2850 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2851 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2852
2853 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
2854 lag_id, port_index);
2855 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2856}
2857
2858static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
2859 u16 lag_id)
2860{
2861 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2862 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2863
2864 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
2865 lag_id);
2866 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2867}
2868
2869static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
2870 u16 lag_id)
2871{
2872 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2873 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2874
2875 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
2876 lag_id);
2877 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2878}
2879
2880static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
2881 u16 lag_id)
2882{
2883 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2884 char slcor_pl[MLXSW_REG_SLCOR_LEN];
2885
2886 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
2887 lag_id);
2888 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
2889}
2890
2891static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2892 struct net_device *lag_dev,
2893 u16 *p_lag_id)
2894{
2895 struct mlxsw_sp_upper *lag;
2896 int free_lag_id = -1;
2897 int i;
2898
2899 for (i = 0; i < MLXSW_SP_LAG_MAX; i++) {
2900 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
2901 if (lag->ref_count) {
2902 if (lag->dev == lag_dev) {
2903 *p_lag_id = i;
2904 return 0;
2905 }
2906 } else if (free_lag_id < 0) {
2907 free_lag_id = i;
2908 }
2909 }
2910 if (free_lag_id < 0)
2911 return -EBUSY;
2912 *p_lag_id = free_lag_id;
2913 return 0;
2914}
2915
2916static bool
2917mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
2918 struct net_device *lag_dev,
2919 struct netdev_lag_upper_info *lag_upper_info)
2920{
2921 u16 lag_id;
2922
2923 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
2924 return false;
2925 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
2926 return false;
2927 return true;
2928}
2929
2930static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
2931 u16 lag_id, u8 *p_port_index)
2932{
2933 int i;
2934
2935 for (i = 0; i < MLXSW_SP_PORT_PER_LAG_MAX; i++) {
2936 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
2937 *p_port_index = i;
2938 return 0;
2939 }
2940 }
2941 return -EBUSY;
2942}
2943
Ido Schimmel86bf95b2016-07-02 11:00:11 +02002944static void
2945mlxsw_sp_port_pvid_vport_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
2946 u16 lag_id)
2947{
2948 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel11943ff2016-07-02 11:00:12 +02002949 struct mlxsw_sp_fid *f;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02002950
2951 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
2952 if (WARN_ON(!mlxsw_sp_vport))
2953 return;
2954
Ido Schimmel11943ff2016-07-02 11:00:12 +02002955 /* If vPort is assigned a RIF, then leave it since it's no
2956 * longer valid.
2957 */
2958 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
2959 if (f)
2960 f->leave(mlxsw_sp_vport);
2961
Ido Schimmel86bf95b2016-07-02 11:00:11 +02002962 mlxsw_sp_vport->lag_id = lag_id;
2963 mlxsw_sp_vport->lagged = 1;
2964}
2965
2966static void
2967mlxsw_sp_port_pvid_vport_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port)
2968{
2969 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel11943ff2016-07-02 11:00:12 +02002970 struct mlxsw_sp_fid *f;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02002971
2972 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
2973 if (WARN_ON(!mlxsw_sp_vport))
2974 return;
2975
Ido Schimmel11943ff2016-07-02 11:00:12 +02002976 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
2977 if (f)
2978 f->leave(mlxsw_sp_vport);
2979
Ido Schimmel86bf95b2016-07-02 11:00:11 +02002980 mlxsw_sp_vport->lagged = 0;
2981}
2982
Jiri Pirko0d65fc12015-12-03 12:12:28 +01002983static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
2984 struct net_device *lag_dev)
2985{
2986 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2987 struct mlxsw_sp_upper *lag;
2988 u16 lag_id;
2989 u8 port_index;
2990 int err;
2991
2992 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
2993 if (err)
2994 return err;
2995 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
2996 if (!lag->ref_count) {
2997 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
2998 if (err)
2999 return err;
3000 lag->dev = lag_dev;
3001 }
3002
3003 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
3004 if (err)
3005 return err;
3006 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
3007 if (err)
3008 goto err_col_port_add;
3009 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
3010 if (err)
3011 goto err_col_port_enable;
3012
3013 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
3014 mlxsw_sp_port->local_port);
3015 mlxsw_sp_port->lag_id = lag_id;
3016 mlxsw_sp_port->lagged = 1;
3017 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003018
3019 mlxsw_sp_port_pvid_vport_lag_join(mlxsw_sp_port, lag_id);
3020
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003021 return 0;
3022
Ido Schimmel51554db2016-05-06 22:18:39 +02003023err_col_port_enable:
3024 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003025err_col_port_add:
3026 if (!lag->ref_count)
3027 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003028 return err;
3029}
3030
Ido Schimmel82e6db02016-06-20 23:04:04 +02003031static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
3032 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003033{
3034 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003035 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02003036 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003037
3038 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02003039 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003040 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
3041 WARN_ON(lag->ref_count == 0);
3042
Ido Schimmel82e6db02016-06-20 23:04:04 +02003043 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
3044 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003045
Ido Schimmel4dc236c2016-01-27 15:20:16 +01003046 if (mlxsw_sp_port->bridged) {
3047 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003048 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01003049 }
3050
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003051 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02003052 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003053
3054 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
3055 mlxsw_sp_port->local_port);
3056 mlxsw_sp_port->lagged = 0;
3057 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003058
3059 mlxsw_sp_port_pvid_vport_lag_leave(mlxsw_sp_port);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003060}
3061
Jiri Pirko74581202015-12-03 12:12:30 +01003062static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
3063 u16 lag_id)
3064{
3065 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3066 char sldr_pl[MLXSW_REG_SLDR_LEN];
3067
3068 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
3069 mlxsw_sp_port->local_port);
3070 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3071}
3072
3073static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
3074 u16 lag_id)
3075{
3076 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3077 char sldr_pl[MLXSW_REG_SLDR_LEN];
3078
3079 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
3080 mlxsw_sp_port->local_port);
3081 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3082}
3083
3084static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
3085 bool lag_tx_enabled)
3086{
3087 if (lag_tx_enabled)
3088 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
3089 mlxsw_sp_port->lag_id);
3090 else
3091 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
3092 mlxsw_sp_port->lag_id);
3093}
3094
3095static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
3096 struct netdev_lag_lower_state_info *info)
3097{
3098 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
3099}
3100
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003101static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
3102 struct net_device *vlan_dev)
3103{
3104 struct mlxsw_sp_port *mlxsw_sp_vport;
3105 u16 vid = vlan_dev_vlan_id(vlan_dev);
3106
3107 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel423b9372016-06-20 23:04:03 +02003108 if (WARN_ON(!mlxsw_sp_vport))
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003109 return -EINVAL;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003110
3111 mlxsw_sp_vport->dev = vlan_dev;
3112
3113 return 0;
3114}
3115
Ido Schimmel82e6db02016-06-20 23:04:04 +02003116static void mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
3117 struct net_device *vlan_dev)
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003118{
3119 struct mlxsw_sp_port *mlxsw_sp_vport;
3120 u16 vid = vlan_dev_vlan_id(vlan_dev);
3121
3122 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel423b9372016-06-20 23:04:03 +02003123 if (WARN_ON(!mlxsw_sp_vport))
Ido Schimmel82e6db02016-06-20 23:04:04 +02003124 return;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003125
3126 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003127}
3128
Jiri Pirko74581202015-12-03 12:12:30 +01003129static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
3130 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003131{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003132 struct netdev_notifier_changeupper_info *info;
3133 struct mlxsw_sp_port *mlxsw_sp_port;
3134 struct net_device *upper_dev;
3135 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02003136 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003137
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003138 mlxsw_sp_port = netdev_priv(dev);
3139 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3140 info = ptr;
3141
3142 switch (event) {
3143 case NETDEV_PRECHANGEUPPER:
3144 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02003145 if (!is_vlan_dev(upper_dev) &&
3146 !netif_is_lag_master(upper_dev) &&
3147 !netif_is_bridge_master(upper_dev))
3148 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02003149 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003150 break;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003151 /* HW limitation forbids to put ports to multiple bridges. */
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003152 if (netif_is_bridge_master(upper_dev) &&
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003153 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02003154 return -EINVAL;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003155 if (netif_is_lag_master(upper_dev) &&
3156 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
3157 info->upper_info))
Ido Schimmel80bedf12016-06-20 23:03:59 +02003158 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02003159 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
3160 return -EINVAL;
3161 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
3162 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
3163 return -EINVAL;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003164 break;
3165 case NETDEV_CHANGEUPPER:
3166 upper_dev = info->upper_dev;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003167 if (is_vlan_dev(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02003168 if (info->linking)
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003169 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
3170 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02003171 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02003172 mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
3173 upper_dev);
Ido Schimmel9589a7b52015-12-15 16:03:43 +01003174 } else if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02003175 if (info->linking)
3176 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
3177 upper_dev);
3178 else
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003179 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003180 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02003181 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003182 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
3183 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02003184 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02003185 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
3186 upper_dev);
Ido Schimmel59fe9b32016-06-20 23:04:00 +02003187 } else {
3188 err = -EINVAL;
3189 WARN_ON(1);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003190 }
3191 break;
3192 }
3193
Ido Schimmel80bedf12016-06-20 23:03:59 +02003194 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003195}
3196
Jiri Pirko74581202015-12-03 12:12:30 +01003197static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
3198 unsigned long event, void *ptr)
3199{
3200 struct netdev_notifier_changelowerstate_info *info;
3201 struct mlxsw_sp_port *mlxsw_sp_port;
3202 int err;
3203
3204 mlxsw_sp_port = netdev_priv(dev);
3205 info = ptr;
3206
3207 switch (event) {
3208 case NETDEV_CHANGELOWERSTATE:
3209 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
3210 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
3211 info->lower_state_info);
3212 if (err)
3213 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
3214 }
3215 break;
3216 }
3217
Ido Schimmel80bedf12016-06-20 23:03:59 +02003218 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01003219}
3220
3221static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
3222 unsigned long event, void *ptr)
3223{
3224 switch (event) {
3225 case NETDEV_PRECHANGEUPPER:
3226 case NETDEV_CHANGEUPPER:
3227 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
3228 case NETDEV_CHANGELOWERSTATE:
3229 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
3230 }
3231
Ido Schimmel80bedf12016-06-20 23:03:59 +02003232 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01003233}
3234
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003235static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
3236 unsigned long event, void *ptr)
3237{
3238 struct net_device *dev;
3239 struct list_head *iter;
3240 int ret;
3241
3242 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3243 if (mlxsw_sp_port_dev_check(dev)) {
3244 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02003245 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003246 return ret;
3247 }
3248 }
3249
Ido Schimmel80bedf12016-06-20 23:03:59 +02003250 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003251}
3252
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003253static struct mlxsw_sp_fid *
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003254mlxsw_sp_br_vfid_find(const struct mlxsw_sp *mlxsw_sp,
3255 const struct net_device *br_dev)
3256{
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003257 struct mlxsw_sp_fid *f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003258
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003259 list_for_each_entry(f, &mlxsw_sp->br_vfids.list, list) {
3260 if (f->dev == br_dev)
3261 return f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003262 }
3263
3264 return NULL;
3265}
3266
3267static u16 mlxsw_sp_vfid_to_br_vfid(u16 vfid)
3268{
3269 return vfid - MLXSW_SP_VFID_PORT_MAX;
3270}
3271
3272static u16 mlxsw_sp_br_vfid_to_vfid(u16 br_vfid)
3273{
3274 return MLXSW_SP_VFID_PORT_MAX + br_vfid;
3275}
3276
3277static u16 mlxsw_sp_avail_br_vfid_get(const struct mlxsw_sp *mlxsw_sp)
3278{
3279 return find_first_zero_bit(mlxsw_sp->br_vfids.mapped,
3280 MLXSW_SP_VFID_BR_MAX);
3281}
3282
Ido Schimmel1c800752016-06-20 23:04:20 +02003283static void mlxsw_sp_vport_br_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
3284
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003285static struct mlxsw_sp_fid *mlxsw_sp_br_vfid_create(struct mlxsw_sp *mlxsw_sp,
3286 struct net_device *br_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003287{
3288 struct device *dev = mlxsw_sp->bus_info->dev;
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003289 struct mlxsw_sp_fid *f;
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003290 u16 vfid, fid;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003291 int err;
3292
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003293 vfid = mlxsw_sp_br_vfid_to_vfid(mlxsw_sp_avail_br_vfid_get(mlxsw_sp));
3294 if (vfid == MLXSW_SP_VFID_MAX) {
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003295 dev_err(dev, "No available vFIDs\n");
3296 return ERR_PTR(-ERANGE);
3297 }
3298
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003299 fid = mlxsw_sp_vfid_to_fid(vfid);
3300 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003301 if (err) {
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003302 dev_err(dev, "Failed to create FID=%d\n", fid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003303 return ERR_PTR(err);
3304 }
3305
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003306 f = kzalloc(sizeof(*f), GFP_KERNEL);
3307 if (!f)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003308 goto err_allocate_vfid;
3309
Ido Schimmel1c800752016-06-20 23:04:20 +02003310 f->leave = mlxsw_sp_vport_br_vfid_leave;
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003311 f->fid = fid;
3312 f->dev = br_dev;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003313
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003314 list_add(&f->list, &mlxsw_sp->br_vfids.list);
3315 set_bit(mlxsw_sp_vfid_to_br_vfid(vfid), mlxsw_sp->br_vfids.mapped);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003316
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003317 return f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003318
3319err_allocate_vfid:
Ido Schimmelc7e920b2016-06-20 23:04:09 +02003320 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003321 return ERR_PTR(-ENOMEM);
3322}
3323
3324static void mlxsw_sp_br_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003325 struct mlxsw_sp_fid *f)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003326{
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003327 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
3328 u16 br_vfid = mlxsw_sp_vfid_to_br_vfid(vfid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003329
3330 clear_bit(br_vfid, mlxsw_sp->br_vfids.mapped);
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003331 list_del(&f->list);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003332
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003333 mlxsw_sp_vfid_op(mlxsw_sp, f->fid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003334
Ido Schimmeld0ec8752016-06-20 23:04:12 +02003335 kfree(f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003336}
3337
Ido Schimmel0355b592016-06-20 23:04:13 +02003338static int mlxsw_sp_vport_br_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3339 struct net_device *br_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003340{
Ido Schimmel0355b592016-06-20 23:04:13 +02003341 struct mlxsw_sp_fid *f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003342 int err;
3343
Ido Schimmel0355b592016-06-20 23:04:13 +02003344 f = mlxsw_sp_br_vfid_find(mlxsw_sp_vport->mlxsw_sp, br_dev);
3345 if (!f) {
3346 f = mlxsw_sp_br_vfid_create(mlxsw_sp_vport->mlxsw_sp, br_dev);
3347 if (IS_ERR(f))
3348 return PTR_ERR(f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003349 }
3350
Ido Schimmel0355b592016-06-20 23:04:13 +02003351 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
3352 if (err)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003353 goto err_vport_flood_set;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003354
Ido Schimmel0355b592016-06-20 23:04:13 +02003355 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
3356 if (err)
3357 goto err_vport_fid_map;
Ido Schimmel6a9863a2016-02-15 13:19:54 +01003358
Ido Schimmel41b996c2016-06-20 23:04:17 +02003359 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
Ido Schimmel0355b592016-06-20 23:04:13 +02003360 f->ref_count++;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003361
Ido Schimmel22305372016-06-20 23:04:21 +02003362 netdev_dbg(mlxsw_sp_vport->dev, "Joined FID=%d\n", f->fid);
3363
Ido Schimmel0355b592016-06-20 23:04:13 +02003364 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003365
Ido Schimmel9c4d4422016-06-20 23:04:10 +02003366err_vport_fid_map:
Ido Schimmel0355b592016-06-20 23:04:13 +02003367 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
3368err_vport_flood_set:
3369 if (!f->ref_count)
3370 mlxsw_sp_br_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
3371 return err;
3372}
3373
3374static void mlxsw_sp_vport_br_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
3375{
Ido Schimmel41b996c2016-06-20 23:04:17 +02003376 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
Ido Schimmel0355b592016-06-20 23:04:13 +02003377
Ido Schimmel22305372016-06-20 23:04:21 +02003378 netdev_dbg(mlxsw_sp_vport->dev, "Left FID=%d\n", f->fid);
3379
Ido Schimmel0355b592016-06-20 23:04:13 +02003380 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
3381
3382 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
3383
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003384 mlxsw_sp_port_fdb_flush(mlxsw_sp_vport, f->fid);
3385
Ido Schimmel41b996c2016-06-20 23:04:17 +02003386 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
Ido Schimmel0355b592016-06-20 23:04:13 +02003387 if (--f->ref_count == 0)
3388 mlxsw_sp_br_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003389}
3390
3391static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
3392 struct net_device *br_dev)
3393{
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003394 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
3395 struct net_device *dev = mlxsw_sp_vport->dev;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003396 int err;
3397
Ido Schimmel0355b592016-06-20 23:04:13 +02003398 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003399
Ido Schimmel0355b592016-06-20 23:04:13 +02003400 err = mlxsw_sp_vport_br_vfid_join(mlxsw_sp_vport, br_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003401 if (err) {
Ido Schimmel0355b592016-06-20 23:04:13 +02003402 netdev_err(dev, "Failed to join vFID\n");
3403 goto err_vport_br_vfid_join;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003404 }
3405
3406 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
3407 if (err) {
3408 netdev_err(dev, "Failed to enable learning\n");
3409 goto err_port_vid_learning_set;
3410 }
3411
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003412 mlxsw_sp_vport->learning = 1;
3413 mlxsw_sp_vport->learning_sync = 1;
3414 mlxsw_sp_vport->uc_flood = 1;
3415 mlxsw_sp_vport->bridged = 1;
3416
3417 return 0;
3418
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003419err_port_vid_learning_set:
Ido Schimmel0355b592016-06-20 23:04:13 +02003420 mlxsw_sp_vport_br_vfid_leave(mlxsw_sp_vport);
3421err_vport_br_vfid_join:
3422 mlxsw_sp_vport_vfid_join(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003423 return err;
3424}
3425
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003426static void mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
Ido Schimmel0355b592016-06-20 23:04:13 +02003427{
3428 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
Ido Schimmel0355b592016-06-20 23:04:13 +02003429
3430 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
3431
3432 mlxsw_sp_vport_br_vfid_leave(mlxsw_sp_vport);
3433
3434 mlxsw_sp_vport_vfid_join(mlxsw_sp_vport);
3435
3436 mlxsw_sp_port_stp_state_set(mlxsw_sp_vport, vid,
3437 MLXSW_REG_SPMS_STATE_FORWARDING);
3438
Ido Schimmel0355b592016-06-20 23:04:13 +02003439 mlxsw_sp_vport->learning = 0;
3440 mlxsw_sp_vport->learning_sync = 0;
3441 mlxsw_sp_vport->uc_flood = 0;
3442 mlxsw_sp_vport->bridged = 0;
3443}
3444
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003445static bool
3446mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
3447 const struct net_device *br_dev)
3448{
3449 struct mlxsw_sp_port *mlxsw_sp_vport;
3450
3451 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
3452 vport.list) {
Ido Schimmel56918b62016-06-20 23:04:18 +02003453 struct net_device *dev = mlxsw_sp_vport_br_get(mlxsw_sp_vport);
3454
3455 if (dev && dev == br_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003456 return false;
3457 }
3458
3459 return true;
3460}
3461
3462static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
3463 unsigned long event, void *ptr,
3464 u16 vid)
3465{
3466 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3467 struct netdev_notifier_changeupper_info *info = ptr;
3468 struct mlxsw_sp_port *mlxsw_sp_vport;
3469 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02003470 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003471
3472 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
3473
3474 switch (event) {
3475 case NETDEV_PRECHANGEUPPER:
3476 upper_dev = info->upper_dev;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003477 if (!netif_is_bridge_master(upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02003478 return -EINVAL;
Ido Schimmelddbe9932016-06-20 23:04:02 +02003479 if (!info->linking)
3480 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003481 /* We can't have multiple VLAN interfaces configured on
3482 * the same port and being members in the same bridge.
3483 */
3484 if (!mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
3485 upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02003486 return -EINVAL;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003487 break;
3488 case NETDEV_CHANGEUPPER:
3489 upper_dev = info->upper_dev;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003490 if (info->linking) {
Ido Schimmel423b9372016-06-20 23:04:03 +02003491 if (WARN_ON(!mlxsw_sp_vport))
Ido Schimmel80bedf12016-06-20 23:03:59 +02003492 return -EINVAL;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003493 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
3494 upper_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003495 } else {
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003496 if (!mlxsw_sp_vport)
Ido Schimmel80bedf12016-06-20 23:03:59 +02003497 return 0;
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003498 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003499 }
3500 }
3501
Ido Schimmel80bedf12016-06-20 23:03:59 +02003502 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003503}
3504
Ido Schimmel272c4472015-12-15 16:03:47 +01003505static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
3506 unsigned long event, void *ptr,
3507 u16 vid)
3508{
3509 struct net_device *dev;
3510 struct list_head *iter;
3511 int ret;
3512
3513 netdev_for_each_lower_dev(lag_dev, dev, iter) {
3514 if (mlxsw_sp_port_dev_check(dev)) {
3515 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
3516 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02003517 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01003518 return ret;
3519 }
3520 }
3521
Ido Schimmel80bedf12016-06-20 23:03:59 +02003522 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01003523}
3524
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003525static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
3526 unsigned long event, void *ptr)
3527{
3528 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
3529 u16 vid = vlan_dev_vlan_id(vlan_dev);
3530
Ido Schimmel272c4472015-12-15 16:03:47 +01003531 if (mlxsw_sp_port_dev_check(real_dev))
3532 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
3533 vid);
3534 else if (netif_is_lag_master(real_dev))
3535 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
3536 vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003537
Ido Schimmel80bedf12016-06-20 23:03:59 +02003538 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01003539}
3540
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003541static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3542 unsigned long event, void *ptr)
3543{
3544 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02003545 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003546
Ido Schimmel6e095fd2016-07-04 08:23:13 +02003547 if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
3548 err = mlxsw_sp_netdevice_router_port_event(dev);
3549 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02003550 err = mlxsw_sp_netdevice_port_event(dev, event, ptr);
3551 else if (netif_is_lag_master(dev))
3552 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
3553 else if (is_vlan_dev(dev))
3554 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003555
Ido Schimmel80bedf12016-06-20 23:03:59 +02003556 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003557}
3558
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003559static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
3560 .notifier_call = mlxsw_sp_netdevice_event,
3561};
3562
3563static int __init mlxsw_sp_module_init(void)
3564{
3565 int err;
3566
3567 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3568 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
3569 if (err)
3570 goto err_core_driver_register;
3571 return 0;
3572
3573err_core_driver_register:
3574 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3575 return err;
3576}
3577
3578static void __exit mlxsw_sp_module_exit(void)
3579{
3580 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
3581 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
3582}
3583
3584module_init(mlxsw_sp_module_init);
3585module_exit(mlxsw_sp_module_exit);
3586
3587MODULE_LICENSE("Dual BSD/GPL");
3588MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
3589MODULE_DESCRIPTION("Mellanox Spectrum driver");
3590MODULE_MLXSW_DRIVER_ALIAS(MLXSW_DEVICE_KIND_SPECTRUM);