blob: 2209f75fdf05bf29114f0fb3ffedff89f55b43f3 [file] [log] [blame]
Zhang Wei173acc72008-03-01 07:42:48 -07001/*
2 * Freescale MPC85xx, MPC83xx DMA Engine support
3 *
Li Yange2c8e4252010-11-11 20:16:29 +08004 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
Zhang Wei173acc72008-03-01 07:42:48 -07005 *
6 * Author:
7 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007
8 * Ebony Zhu <ebony.zhu@freescale.com>, May 2007
9 *
10 * Description:
11 * DMA engine driver for Freescale MPC8540 DMA controller, which is
12 * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
Stefan Weilc2e07b32010-08-03 19:44:52 +020013 * The support for MPC8349 DMA controller is also added.
Zhang Wei173acc72008-03-01 07:42:48 -070014 *
Ira W. Snydera7aea372009-04-23 16:17:54 -070015 * This driver instructs the DMA controller to issue the PCI Read Multiple
16 * command for PCI read operations, instead of using the default PCI Read Line
17 * command. Please be aware that this setting may result in read pre-fetching
18 * on some platforms.
19 *
Zhang Wei173acc72008-03-01 07:42:48 -070020 * This is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 */
26
27#include <linux/init.h>
28#include <linux/module.h>
29#include <linux/pci.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Zhang Wei173acc72008-03-01 07:42:48 -070031#include <linux/interrupt.h>
32#include <linux/dmaengine.h>
33#include <linux/delay.h>
34#include <linux/dma-mapping.h>
35#include <linux/dmapool.h>
Rob Herring5af50732013-09-17 14:28:33 -050036#include <linux/of_address.h>
37#include <linux/of_irq.h>
Zhang Wei173acc72008-03-01 07:42:48 -070038#include <linux/of_platform.h>
Vinod Koul0a5642b2014-10-11 21:16:44 +053039#include <linux/fsldma.h>
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000040#include "dmaengine.h"
Zhang Wei173acc72008-03-01 07:42:48 -070041#include "fsldma.h"
42
Ira Snyderb1584712011-03-03 07:54:55 +000043#define chan_dbg(chan, fmt, arg...) \
44 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
45#define chan_err(chan, fmt, arg...) \
46 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
Ira Snyderc14330412010-09-30 11:46:45 +000047
Ira Snyderb1584712011-03-03 07:54:55 +000048static const char msg_ld_oom[] = "No free memory for link descriptor";
Zhang Wei173acc72008-03-01 07:42:48 -070049
Ira Snydere8bd84d2011-03-03 07:54:54 +000050/*
51 * Register Helpers
52 */
Zhang Wei173acc72008-03-01 07:42:48 -070053
Ira Snydera1c03312010-01-06 13:34:05 +000054static void set_sr(struct fsldma_chan *chan, u32 val)
Zhang Wei173acc72008-03-01 07:42:48 -070055{
Ira Snydera1c03312010-01-06 13:34:05 +000056 DMA_OUT(chan, &chan->regs->sr, val, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070057}
58
Ira Snydera1c03312010-01-06 13:34:05 +000059static u32 get_sr(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -070060{
Ira Snydera1c03312010-01-06 13:34:05 +000061 return DMA_IN(chan, &chan->regs->sr, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070062}
63
Hongbo Zhangccdce9a2014-04-18 16:17:45 +080064static void set_mr(struct fsldma_chan *chan, u32 val)
65{
66 DMA_OUT(chan, &chan->regs->mr, val, 32);
67}
68
69static u32 get_mr(struct fsldma_chan *chan)
70{
71 return DMA_IN(chan, &chan->regs->mr, 32);
72}
73
Ira Snydera1c03312010-01-06 13:34:05 +000074static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
Zhang Wei173acc72008-03-01 07:42:48 -070075{
Ira Snydera1c03312010-01-06 13:34:05 +000076 DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
Zhang Wei173acc72008-03-01 07:42:48 -070077}
78
Ira Snydera1c03312010-01-06 13:34:05 +000079static dma_addr_t get_cdar(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -070080{
Ira Snydera1c03312010-01-06 13:34:05 +000081 return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
Zhang Wei173acc72008-03-01 07:42:48 -070082}
83
Hongbo Zhangccdce9a2014-04-18 16:17:45 +080084static void set_bcr(struct fsldma_chan *chan, u32 val)
85{
86 DMA_OUT(chan, &chan->regs->bcr, val, 32);
87}
88
Ira Snydera1c03312010-01-06 13:34:05 +000089static u32 get_bcr(struct fsldma_chan *chan)
Zhang Weif79abb62008-03-18 18:45:00 -070090{
Ira Snydera1c03312010-01-06 13:34:05 +000091 return DMA_IN(chan, &chan->regs->bcr, 32);
Zhang Weif79abb62008-03-18 18:45:00 -070092}
93
Ira Snydere8bd84d2011-03-03 07:54:54 +000094/*
95 * Descriptor Helpers
96 */
97
Zhang Wei173acc72008-03-01 07:42:48 -070098static void set_desc_cnt(struct fsldma_chan *chan,
99 struct fsl_dma_ld_hw *hw, u32 count)
Zhang Wei173acc72008-03-01 07:42:48 -0700100{
Zhang Wei173acc72008-03-01 07:42:48 -0700101 hw->count = CPU_TO_DMA(chan, count, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700102}
103
Zhang Wei173acc72008-03-01 07:42:48 -0700104static void set_desc_src(struct fsldma_chan *chan,
Ira Snyder31f43062011-03-03 07:54:57 +0000105 struct fsl_dma_ld_hw *hw, dma_addr_t src)
Zhang Wei173acc72008-03-01 07:42:48 -0700106{
Zhang Wei173acc72008-03-01 07:42:48 -0700107 u64 snoop_bits;
Dan Williams900325a2009-03-02 15:33:46 -0700108
Zhang Wei173acc72008-03-01 07:42:48 -0700109 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
110 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
111 hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700112}
113
Zhang Wei173acc72008-03-01 07:42:48 -0700114static void set_desc_dst(struct fsldma_chan *chan,
Ira Snyder31f43062011-03-03 07:54:57 +0000115 struct fsl_dma_ld_hw *hw, dma_addr_t dst)
Zhang Wei173acc72008-03-01 07:42:48 -0700116{
117 u64 snoop_bits;
118
119 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
120 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
121 hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
122}
123
124static void set_desc_next(struct fsldma_chan *chan,
Ira Snyder31f43062011-03-03 07:54:57 +0000125 struct fsl_dma_ld_hw *hw, dma_addr_t next)
Zhang Wei173acc72008-03-01 07:42:48 -0700126{
127 u64 snoop_bits;
128
129 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
130 ? FSL_DMA_SNEN : 0;
131 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
132}
133
Ira Snyder31f43062011-03-03 07:54:57 +0000134static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
Zhang Wei173acc72008-03-01 07:42:48 -0700135{
Ira Snyder776c8942009-05-15 11:33:20 -0700136 u64 snoop_bits;
137
Ira Snydera1c03312010-01-06 13:34:05 +0000138 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
Ira Snyder776c8942009-05-15 11:33:20 -0700139 ? FSL_DMA_SNEN : 0;
140
Ira Snydera1c03312010-01-06 13:34:05 +0000141 desc->hw.next_ln_addr = CPU_TO_DMA(chan,
142 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
Ira Snyder776c8942009-05-15 11:33:20 -0700143 | snoop_bits, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700144}
145
Ira Snydere8bd84d2011-03-03 07:54:54 +0000146/*
147 * DMA Engine Hardware Control Helpers
148 */
Zhang Wei173acc72008-03-01 07:42:48 -0700149
Ira Snydere8bd84d2011-03-03 07:54:54 +0000150static void dma_init(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700151{
Ira Snydere8bd84d2011-03-03 07:54:54 +0000152 /* Reset the channel */
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800153 set_mr(chan, 0);
Zhang Wei173acc72008-03-01 07:42:48 -0700154
Ira Snydere8bd84d2011-03-03 07:54:54 +0000155 switch (chan->feature & FSL_DMA_IP_MASK) {
156 case FSL_DMA_IP_85XX:
157 /* Set the channel to below modes:
158 * EIE - Error interrupt enable
Ira Snydere8bd84d2011-03-03 07:54:54 +0000159 * EOLNIE - End of links interrupt enable
160 * BWC - Bandwidth sharing among channels
161 */
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800162 set_mr(chan, FSL_DMA_MR_BWC | FSL_DMA_MR_EIE
163 | FSL_DMA_MR_EOLNIE);
Ira Snydere8bd84d2011-03-03 07:54:54 +0000164 break;
165 case FSL_DMA_IP_83XX:
166 /* Set the channel to below modes:
167 * EOTIE - End-of-transfer interrupt enable
168 * PRC_RM - PCI read multiple
169 */
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800170 set_mr(chan, FSL_DMA_MR_EOTIE | FSL_DMA_MR_PRC_RM);
Ira Snydere8bd84d2011-03-03 07:54:54 +0000171 break;
172 }
Zhang Wei173acc72008-03-01 07:42:48 -0700173}
174
175static int dma_is_idle(struct fsldma_chan *chan)
176{
177 u32 sr = get_sr(chan);
178 return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
179}
180
Ira Snyderf04cd402011-03-03 07:54:58 +0000181/*
182 * Start the DMA controller
183 *
184 * Preconditions:
185 * - the CDAR register must point to the start descriptor
186 * - the MRn[CS] bit must be cleared
187 */
Zhang Wei173acc72008-03-01 07:42:48 -0700188static void dma_start(struct fsldma_chan *chan)
189{
190 u32 mode;
191
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800192 mode = get_mr(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700193
Ira Snyderf04cd402011-03-03 07:54:58 +0000194 if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800195 set_bcr(chan, 0);
Ira Snyderf04cd402011-03-03 07:54:58 +0000196 mode |= FSL_DMA_MR_EMP_EN;
197 } else {
198 mode &= ~FSL_DMA_MR_EMP_EN;
Zhang Wei173acc72008-03-01 07:42:48 -0700199 }
200
Ira Snyderf04cd402011-03-03 07:54:58 +0000201 if (chan->feature & FSL_DMA_CHAN_START_EXT) {
Zhang Wei173acc72008-03-01 07:42:48 -0700202 mode |= FSL_DMA_MR_EMS_EN;
Ira Snyderf04cd402011-03-03 07:54:58 +0000203 } else {
204 mode &= ~FSL_DMA_MR_EMS_EN;
Zhang Wei173acc72008-03-01 07:42:48 -0700205 mode |= FSL_DMA_MR_CS;
Ira Snyderf04cd402011-03-03 07:54:58 +0000206 }
Zhang Wei173acc72008-03-01 07:42:48 -0700207
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800208 set_mr(chan, mode);
Zhang Wei173acc72008-03-01 07:42:48 -0700209}
210
211static void dma_halt(struct fsldma_chan *chan)
212{
213 u32 mode;
214 int i;
215
Ira Snydera00ae342011-03-03 07:55:01 +0000216 /* read the mode register */
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800217 mode = get_mr(chan);
Ira Snydera00ae342011-03-03 07:55:01 +0000218
219 /*
220 * The 85xx controller supports channel abort, which will stop
221 * the current transfer. On 83xx, this bit is the transfer error
222 * mask bit, which should not be changed.
223 */
224 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
225 mode |= FSL_DMA_MR_CA;
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800226 set_mr(chan, mode);
Ira Snydera00ae342011-03-03 07:55:01 +0000227
228 mode &= ~FSL_DMA_MR_CA;
229 }
230
231 /* stop the DMA controller */
232 mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN);
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800233 set_mr(chan, mode);
Zhang Wei173acc72008-03-01 07:42:48 -0700234
Ira Snydera00ae342011-03-03 07:55:01 +0000235 /* wait for the DMA controller to become idle */
Zhang Wei173acc72008-03-01 07:42:48 -0700236 for (i = 0; i < 100; i++) {
237 if (dma_is_idle(chan))
238 return;
239
240 udelay(10);
241 }
242
243 if (!dma_is_idle(chan))
Ira Snyderb1584712011-03-03 07:54:55 +0000244 chan_err(chan, "DMA halt timeout!\n");
Zhang Wei173acc72008-03-01 07:42:48 -0700245}
246
Zhang Wei173acc72008-03-01 07:42:48 -0700247/**
248 * fsl_chan_set_src_loop_size - Set source address hold transfer size
Ira Snydera1c03312010-01-06 13:34:05 +0000249 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700250 * @size : Address loop size, 0 for disable loop
251 *
252 * The set source address hold transfer size. The source
253 * address hold or loop transfer size is when the DMA transfer
254 * data from source address (SA), if the loop size is 4, the DMA will
255 * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
256 * SA + 1 ... and so on.
257 */
Ira Snydera1c03312010-01-06 13:34:05 +0000258static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
Zhang Wei173acc72008-03-01 07:42:48 -0700259{
Ira Snyder272ca652010-01-06 13:33:59 +0000260 u32 mode;
261
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800262 mode = get_mr(chan);
Ira Snyder272ca652010-01-06 13:33:59 +0000263
Zhang Wei173acc72008-03-01 07:42:48 -0700264 switch (size) {
265 case 0:
Ira Snyder272ca652010-01-06 13:33:59 +0000266 mode &= ~FSL_DMA_MR_SAHE;
Zhang Wei173acc72008-03-01 07:42:48 -0700267 break;
268 case 1:
269 case 2:
270 case 4:
271 case 8:
Ira Snyder272ca652010-01-06 13:33:59 +0000272 mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
Zhang Wei173acc72008-03-01 07:42:48 -0700273 break;
274 }
Ira Snyder272ca652010-01-06 13:33:59 +0000275
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800276 set_mr(chan, mode);
Zhang Wei173acc72008-03-01 07:42:48 -0700277}
278
279/**
Ira Snyder738f5f72010-01-06 13:34:02 +0000280 * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
Ira Snydera1c03312010-01-06 13:34:05 +0000281 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700282 * @size : Address loop size, 0 for disable loop
283 *
284 * The set destination address hold transfer size. The destination
285 * address hold or loop transfer size is when the DMA transfer
286 * data to destination address (TA), if the loop size is 4, the DMA will
287 * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
288 * TA + 1 ... and so on.
289 */
Ira Snydera1c03312010-01-06 13:34:05 +0000290static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
Zhang Wei173acc72008-03-01 07:42:48 -0700291{
Ira Snyder272ca652010-01-06 13:33:59 +0000292 u32 mode;
293
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800294 mode = get_mr(chan);
Ira Snyder272ca652010-01-06 13:33:59 +0000295
Zhang Wei173acc72008-03-01 07:42:48 -0700296 switch (size) {
297 case 0:
Ira Snyder272ca652010-01-06 13:33:59 +0000298 mode &= ~FSL_DMA_MR_DAHE;
Zhang Wei173acc72008-03-01 07:42:48 -0700299 break;
300 case 1:
301 case 2:
302 case 4:
303 case 8:
Ira Snyder272ca652010-01-06 13:33:59 +0000304 mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
Zhang Wei173acc72008-03-01 07:42:48 -0700305 break;
306 }
Ira Snyder272ca652010-01-06 13:33:59 +0000307
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800308 set_mr(chan, mode);
Zhang Wei173acc72008-03-01 07:42:48 -0700309}
310
311/**
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700312 * fsl_chan_set_request_count - Set DMA Request Count for external control
Ira Snydera1c03312010-01-06 13:34:05 +0000313 * @chan : Freescale DMA channel
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700314 * @size : Number of bytes to transfer in a single request
315 *
316 * The Freescale DMA channel can be controlled by the external signal DREQ#.
317 * The DMA request count is how many bytes are allowed to transfer before
318 * pausing the channel, after which a new assertion of DREQ# resumes channel
319 * operation.
320 *
321 * A size of 0 disables external pause control. The maximum size is 1024.
322 */
Ira Snydera1c03312010-01-06 13:34:05 +0000323static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700324{
Ira Snyder272ca652010-01-06 13:33:59 +0000325 u32 mode;
326
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700327 BUG_ON(size > 1024);
Ira Snyder272ca652010-01-06 13:33:59 +0000328
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800329 mode = get_mr(chan);
Ira Snyder272ca652010-01-06 13:33:59 +0000330 mode |= (__ilog2(size) << 24) & 0x0f000000;
331
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800332 set_mr(chan, mode);
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700333}
334
335/**
Zhang Wei173acc72008-03-01 07:42:48 -0700336 * fsl_chan_toggle_ext_pause - Toggle channel external pause status
Ira Snydera1c03312010-01-06 13:34:05 +0000337 * @chan : Freescale DMA channel
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700338 * @enable : 0 is disabled, 1 is enabled.
Zhang Wei173acc72008-03-01 07:42:48 -0700339 *
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700340 * The Freescale DMA channel can be controlled by the external signal DREQ#.
341 * The DMA Request Count feature should be used in addition to this feature
342 * to set the number of bytes to transfer before pausing the channel.
Zhang Wei173acc72008-03-01 07:42:48 -0700343 */
Ira Snydera1c03312010-01-06 13:34:05 +0000344static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
Zhang Wei173acc72008-03-01 07:42:48 -0700345{
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700346 if (enable)
Ira Snydera1c03312010-01-06 13:34:05 +0000347 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700348 else
Ira Snydera1c03312010-01-06 13:34:05 +0000349 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700350}
351
352/**
353 * fsl_chan_toggle_ext_start - Toggle channel external start status
Ira Snydera1c03312010-01-06 13:34:05 +0000354 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700355 * @enable : 0 is disabled, 1 is enabled.
356 *
357 * If enable the external start, the channel can be started by an
358 * external DMA start pin. So the dma_start() does not start the
359 * transfer immediately. The DMA channel will wait for the
360 * control pin asserted.
361 */
Ira Snydera1c03312010-01-06 13:34:05 +0000362static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
Zhang Wei173acc72008-03-01 07:42:48 -0700363{
364 if (enable)
Ira Snydera1c03312010-01-06 13:34:05 +0000365 chan->feature |= FSL_DMA_CHAN_START_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700366 else
Ira Snydera1c03312010-01-06 13:34:05 +0000367 chan->feature &= ~FSL_DMA_CHAN_START_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700368}
369
Vinod Koul0a5642b2014-10-11 21:16:44 +0530370int fsl_dma_external_start(struct dma_chan *dchan, int enable)
371{
372 struct fsldma_chan *chan;
373
374 if (!dchan)
375 return -EINVAL;
376
377 chan = to_fsl_chan(dchan);
378
379 fsl_chan_toggle_ext_start(chan, enable);
380 return 0;
381}
382EXPORT_SYMBOL_GPL(fsl_dma_external_start);
383
Ira Snyder31f43062011-03-03 07:54:57 +0000384static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000385{
386 struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
387
388 if (list_empty(&chan->ld_pending))
389 goto out_splice;
390
391 /*
392 * Add the hardware descriptor to the chain of hardware descriptors
393 * that already exists in memory.
394 *
395 * This will un-set the EOL bit of the existing transaction, and the
396 * last link in this transaction will become the EOL descriptor.
397 */
398 set_desc_next(chan, &tail->hw, desc->async_tx.phys);
399
400 /*
401 * Add the software descriptor and all children to the list
402 * of pending transactions
403 */
404out_splice:
405 list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
406}
407
Zhang Wei173acc72008-03-01 07:42:48 -0700408static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
409{
Ira Snydera1c03312010-01-06 13:34:05 +0000410 struct fsldma_chan *chan = to_fsl_chan(tx->chan);
Dan Williamseda34232009-09-08 17:53:02 -0700411 struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
412 struct fsl_desc_sw *child;
Dan Williamsbbc76562013-12-09 11:16:00 -0800413 dma_cookie_t cookie = -EINVAL;
Zhang Wei173acc72008-03-01 07:42:48 -0700414
Hongbo Zhang2baff572014-05-21 16:03:01 +0800415 spin_lock_bh(&chan->desc_lock);
Zhang Wei173acc72008-03-01 07:42:48 -0700416
Hongbo Zhang14c6a332014-05-21 16:03:02 +0800417#ifdef CONFIG_PM
418 if (unlikely(chan->pm_state != RUNNING)) {
419 chan_dbg(chan, "cannot submit due to suspend\n");
420 spin_unlock_bh(&chan->desc_lock);
421 return -1;
422 }
423#endif
424
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000425 /*
426 * assign cookies to all of the software descriptors
427 * that make up this transaction
428 */
Dan Williamseda34232009-09-08 17:53:02 -0700429 list_for_each_entry(child, &desc->tx_list, node) {
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000430 cookie = dma_cookie_assign(&child->async_tx);
Ira Snyderbcfb7462009-05-15 14:27:16 -0700431 }
432
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000433 /* put this transaction onto the tail of the pending queue */
Ira Snydera1c03312010-01-06 13:34:05 +0000434 append_ld_queue(chan, desc);
Zhang Wei173acc72008-03-01 07:42:48 -0700435
Hongbo Zhang2baff572014-05-21 16:03:01 +0800436 spin_unlock_bh(&chan->desc_lock);
Zhang Wei173acc72008-03-01 07:42:48 -0700437
438 return cookie;
439}
440
441/**
Hongbo Zhang86d19a52014-04-18 16:17:47 +0800442 * fsl_dma_free_descriptor - Free descriptor from channel's DMA pool.
443 * @chan : Freescale DMA channel
444 * @desc: descriptor to be freed
445 */
446static void fsl_dma_free_descriptor(struct fsldma_chan *chan,
447 struct fsl_desc_sw *desc)
448{
449 list_del(&desc->node);
450 chan_dbg(chan, "LD %p free\n", desc);
451 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
452}
453
454/**
Zhang Wei173acc72008-03-01 07:42:48 -0700455 * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
Ira Snydera1c03312010-01-06 13:34:05 +0000456 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700457 *
458 * Return - The descriptor allocated. NULL for failed.
459 */
Ira Snyder31f43062011-03-03 07:54:57 +0000460static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700461{
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000462 struct fsl_desc_sw *desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700463 dma_addr_t pdesc;
Zhang Wei173acc72008-03-01 07:42:48 -0700464
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000465 desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
466 if (!desc) {
Ira Snyderb1584712011-03-03 07:54:55 +0000467 chan_dbg(chan, "out of memory for link descriptor\n");
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000468 return NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700469 }
470
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000471 memset(desc, 0, sizeof(*desc));
472 INIT_LIST_HEAD(&desc->tx_list);
473 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
474 desc->async_tx.tx_submit = fsl_dma_tx_submit;
475 desc->async_tx.phys = pdesc;
476
Ira Snyder0ab09c32011-03-03 07:54:56 +0000477 chan_dbg(chan, "LD %p allocated\n", desc);
Ira Snyder0ab09c32011-03-03 07:54:56 +0000478
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000479 return desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700480}
481
Zhang Wei173acc72008-03-01 07:42:48 -0700482/**
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800483 * fsldma_clean_completed_descriptor - free all descriptors which
484 * has been completed and acked
485 * @chan: Freescale DMA channel
486 *
487 * This function is used on all completed and acked descriptors.
488 * All descriptors should only be freed in this function.
489 */
490static void fsldma_clean_completed_descriptor(struct fsldma_chan *chan)
491{
492 struct fsl_desc_sw *desc, *_desc;
493
494 /* Run the callback for each descriptor, in order */
495 list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node)
496 if (async_tx_test_ack(&desc->async_tx))
497 fsl_dma_free_descriptor(chan, desc);
498}
499
500/**
501 * fsldma_run_tx_complete_actions - cleanup a single link descriptor
502 * @chan: Freescale DMA channel
503 * @desc: descriptor to cleanup and free
504 * @cookie: Freescale DMA transaction identifier
505 *
506 * This function is used on a descriptor which has been executed by the DMA
507 * controller. It will run any callbacks, submit any dependencies.
508 */
509static dma_cookie_t fsldma_run_tx_complete_actions(struct fsldma_chan *chan,
510 struct fsl_desc_sw *desc, dma_cookie_t cookie)
511{
512 struct dma_async_tx_descriptor *txd = &desc->async_tx;
513 dma_cookie_t ret = cookie;
514
515 BUG_ON(txd->cookie < 0);
516
517 if (txd->cookie > 0) {
518 ret = txd->cookie;
519
520 /* Run the link descriptor callback function */
521 if (txd->callback) {
522 chan_dbg(chan, "LD %p callback\n", desc);
523 txd->callback(txd->callback_param);
524 }
525 }
526
527 /* Run any dependencies */
528 dma_run_dependencies(txd);
529
530 return ret;
531}
532
533/**
534 * fsldma_clean_running_descriptor - move the completed descriptor from
535 * ld_running to ld_completed
536 * @chan: Freescale DMA channel
537 * @desc: the descriptor which is completed
538 *
539 * Free the descriptor directly if acked by async_tx api, or move it to
540 * queue ld_completed.
541 */
542static void fsldma_clean_running_descriptor(struct fsldma_chan *chan,
543 struct fsl_desc_sw *desc)
544{
545 /* Remove from the list of transactions */
546 list_del(&desc->node);
547
548 /*
549 * the client is allowed to attach dependent operations
550 * until 'ack' is set
551 */
552 if (!async_tx_test_ack(&desc->async_tx)) {
553 /*
554 * Move this descriptor to the list of descriptors which is
555 * completed, but still awaiting the 'ack' bit to be set.
556 */
557 list_add_tail(&desc->node, &chan->ld_completed);
558 return;
559 }
560
561 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
562}
563
564/**
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800565 * fsl_chan_xfer_ld_queue - transfer any pending transactions
566 * @chan : Freescale DMA channel
567 *
568 * HARDWARE STATE: idle
569 * LOCKING: must hold chan->desc_lock
570 */
571static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
572{
573 struct fsl_desc_sw *desc;
574
575 /*
576 * If the list of pending descriptors is empty, then we
577 * don't need to do any work at all
578 */
579 if (list_empty(&chan->ld_pending)) {
580 chan_dbg(chan, "no pending LDs\n");
581 return;
582 }
583
584 /*
585 * The DMA controller is not idle, which means that the interrupt
586 * handler will start any queued transactions when it runs after
587 * this transaction finishes
588 */
589 if (!chan->idle) {
590 chan_dbg(chan, "DMA controller still busy\n");
591 return;
592 }
593
594 /*
595 * If there are some link descriptors which have not been
596 * transferred, we need to start the controller
597 */
598
599 /*
600 * Move all elements from the queue of pending transactions
601 * onto the list of running transactions
602 */
603 chan_dbg(chan, "idle, starting controller\n");
604 desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
605 list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
606
607 /*
608 * The 85xx DMA controller doesn't clear the channel start bit
609 * automatically at the end of a transfer. Therefore we must clear
610 * it in software before starting the transfer.
611 */
612 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
613 u32 mode;
614
615 mode = get_mr(chan);
616 mode &= ~FSL_DMA_MR_CS;
617 set_mr(chan, mode);
618 }
619
620 /*
621 * Program the descriptor's address into the DMA controller,
622 * then start the DMA transaction
623 */
624 set_cdar(chan, desc->async_tx.phys);
625 get_cdar(chan);
626
627 dma_start(chan);
628 chan->idle = false;
629}
630
631/**
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800632 * fsldma_cleanup_descriptors - cleanup link descriptors which are completed
633 * and move them to ld_completed to free until flag 'ack' is set
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800634 * @chan: Freescale DMA channel
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800635 *
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800636 * This function is used on descriptors which have been executed by the DMA
637 * controller. It will run any callbacks, submit any dependencies, then
638 * free these descriptors if flag 'ack' is set.
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800639 */
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800640static void fsldma_cleanup_descriptors(struct fsldma_chan *chan)
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800641{
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800642 struct fsl_desc_sw *desc, *_desc;
643 dma_cookie_t cookie = 0;
644 dma_addr_t curr_phys = get_cdar(chan);
645 int seen_current = 0;
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800646
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800647 fsldma_clean_completed_descriptor(chan);
648
649 /* Run the callback for each descriptor, in order */
650 list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) {
651 /*
652 * do not advance past the current descriptor loaded into the
653 * hardware channel, subsequent descriptors are either in
654 * process or have not been submitted
655 */
656 if (seen_current)
657 break;
658
659 /*
660 * stop the search if we reach the current descriptor and the
661 * channel is busy
662 */
663 if (desc->async_tx.phys == curr_phys) {
664 seen_current = 1;
665 if (!dma_is_idle(chan))
666 break;
667 }
668
669 cookie = fsldma_run_tx_complete_actions(chan, desc, cookie);
670
671 fsldma_clean_running_descriptor(chan, desc);
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800672 }
673
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800674 /*
675 * Start any pending transactions automatically
676 *
677 * In the ideal case, we keep the DMA controller busy while we go
678 * ahead and free the descriptors below.
679 */
680 fsl_chan_xfer_ld_queue(chan);
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800681
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800682 if (cookie > 0)
683 chan->common.completed_cookie = cookie;
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800684}
685
686/**
Zhang Wei173acc72008-03-01 07:42:48 -0700687 * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
Ira Snydera1c03312010-01-06 13:34:05 +0000688 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700689 *
690 * This function will create a dma pool for descriptor allocation.
691 *
692 * Return - The number of descriptors allocated.
693 */
Ira Snydera1c03312010-01-06 13:34:05 +0000694static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700695{
Ira Snydera1c03312010-01-06 13:34:05 +0000696 struct fsldma_chan *chan = to_fsl_chan(dchan);
Timur Tabi77cd62e2008-09-26 17:00:11 -0700697
698 /* Has this channel already been allocated? */
Ira Snydera1c03312010-01-06 13:34:05 +0000699 if (chan->desc_pool)
Timur Tabi77cd62e2008-09-26 17:00:11 -0700700 return 1;
Zhang Wei173acc72008-03-01 07:42:48 -0700701
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000702 /*
703 * We need the descriptor to be aligned to 32bytes
Zhang Wei173acc72008-03-01 07:42:48 -0700704 * for meeting FSL DMA specification requirement.
705 */
Ira Snyderb1584712011-03-03 07:54:55 +0000706 chan->desc_pool = dma_pool_create(chan->name, chan->dev,
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000707 sizeof(struct fsl_desc_sw),
708 __alignof__(struct fsl_desc_sw), 0);
Ira Snydera1c03312010-01-06 13:34:05 +0000709 if (!chan->desc_pool) {
Ira Snyderb1584712011-03-03 07:54:55 +0000710 chan_err(chan, "unable to allocate descriptor pool\n");
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000711 return -ENOMEM;
Zhang Wei173acc72008-03-01 07:42:48 -0700712 }
713
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000714 /* there is at least one descriptor free to be allocated */
Zhang Wei173acc72008-03-01 07:42:48 -0700715 return 1;
716}
717
718/**
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000719 * fsldma_free_desc_list - Free all descriptors in a queue
720 * @chan: Freescae DMA channel
721 * @list: the list to free
722 *
723 * LOCKING: must hold chan->desc_lock
724 */
725static void fsldma_free_desc_list(struct fsldma_chan *chan,
726 struct list_head *list)
727{
728 struct fsl_desc_sw *desc, *_desc;
729
Hongbo Zhang86d19a52014-04-18 16:17:47 +0800730 list_for_each_entry_safe(desc, _desc, list, node)
731 fsl_dma_free_descriptor(chan, desc);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000732}
733
734static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
735 struct list_head *list)
736{
737 struct fsl_desc_sw *desc, *_desc;
738
Hongbo Zhang86d19a52014-04-18 16:17:47 +0800739 list_for_each_entry_safe_reverse(desc, _desc, list, node)
740 fsl_dma_free_descriptor(chan, desc);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000741}
742
743/**
Zhang Wei173acc72008-03-01 07:42:48 -0700744 * fsl_dma_free_chan_resources - Free all resources of the channel.
Ira Snydera1c03312010-01-06 13:34:05 +0000745 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700746 */
Ira Snydera1c03312010-01-06 13:34:05 +0000747static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700748{
Ira Snydera1c03312010-01-06 13:34:05 +0000749 struct fsldma_chan *chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700750
Ira Snyderb1584712011-03-03 07:54:55 +0000751 chan_dbg(chan, "free all channel resources\n");
Hongbo Zhang2baff572014-05-21 16:03:01 +0800752 spin_lock_bh(&chan->desc_lock);
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800753 fsldma_cleanup_descriptors(chan);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000754 fsldma_free_desc_list(chan, &chan->ld_pending);
755 fsldma_free_desc_list(chan, &chan->ld_running);
Hongbo Zhang43452fa2014-05-21 16:03:03 +0800756 fsldma_free_desc_list(chan, &chan->ld_completed);
Hongbo Zhang2baff572014-05-21 16:03:01 +0800757 spin_unlock_bh(&chan->desc_lock);
Timur Tabi77cd62e2008-09-26 17:00:11 -0700758
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000759 dma_pool_destroy(chan->desc_pool);
Ira Snydera1c03312010-01-06 13:34:05 +0000760 chan->desc_pool = NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700761}
762
Zhang Wei2187c262008-03-13 17:45:28 -0700763static struct dma_async_tx_descriptor *
Ira Snyder31f43062011-03-03 07:54:57 +0000764fsl_dma_prep_memcpy(struct dma_chan *dchan,
765 dma_addr_t dma_dst, dma_addr_t dma_src,
Zhang Wei173acc72008-03-01 07:42:48 -0700766 size_t len, unsigned long flags)
767{
Ira Snydera1c03312010-01-06 13:34:05 +0000768 struct fsldma_chan *chan;
Zhang Wei173acc72008-03-01 07:42:48 -0700769 struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
770 size_t copy;
Zhang Wei173acc72008-03-01 07:42:48 -0700771
Ira Snydera1c03312010-01-06 13:34:05 +0000772 if (!dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700773 return NULL;
774
775 if (!len)
776 return NULL;
777
Ira Snydera1c03312010-01-06 13:34:05 +0000778 chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700779
780 do {
781
782 /* Allocate the link descriptor from DMA pool */
Ira Snydera1c03312010-01-06 13:34:05 +0000783 new = fsl_dma_alloc_descriptor(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700784 if (!new) {
Ira Snyderb1584712011-03-03 07:54:55 +0000785 chan_err(chan, "%s\n", msg_ld_oom);
Ira Snyder2e077f82009-05-15 09:59:46 -0700786 goto fail;
Zhang Wei173acc72008-03-01 07:42:48 -0700787 }
Zhang Wei173acc72008-03-01 07:42:48 -0700788
Zhang Wei56822842008-03-13 10:45:27 -0700789 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
Zhang Wei173acc72008-03-01 07:42:48 -0700790
Ira Snydera1c03312010-01-06 13:34:05 +0000791 set_desc_cnt(chan, &new->hw, copy);
792 set_desc_src(chan, &new->hw, dma_src);
793 set_desc_dst(chan, &new->hw, dma_dst);
Zhang Wei173acc72008-03-01 07:42:48 -0700794
795 if (!first)
796 first = new;
797 else
Ira Snydera1c03312010-01-06 13:34:05 +0000798 set_desc_next(chan, &prev->hw, new->async_tx.phys);
Zhang Wei173acc72008-03-01 07:42:48 -0700799
800 new->async_tx.cookie = 0;
Dan Williams636bdea2008-04-17 20:17:26 -0700801 async_tx_ack(&new->async_tx);
Zhang Wei173acc72008-03-01 07:42:48 -0700802
803 prev = new;
804 len -= copy;
805 dma_src += copy;
Ira Snyder738f5f72010-01-06 13:34:02 +0000806 dma_dst += copy;
Zhang Wei173acc72008-03-01 07:42:48 -0700807
808 /* Insert the link descriptor to the LD ring */
Dan Williamseda34232009-09-08 17:53:02 -0700809 list_add_tail(&new->node, &first->tx_list);
Zhang Wei173acc72008-03-01 07:42:48 -0700810 } while (len);
811
Dan Williams636bdea2008-04-17 20:17:26 -0700812 new->async_tx.flags = flags; /* client is in control of this ack */
Zhang Wei173acc72008-03-01 07:42:48 -0700813 new->async_tx.cookie = -EBUSY;
814
Ira Snyder31f43062011-03-03 07:54:57 +0000815 /* Set End-of-link to the last link descriptor of new list */
Ira Snydera1c03312010-01-06 13:34:05 +0000816 set_ld_eol(chan, new);
Zhang Wei173acc72008-03-01 07:42:48 -0700817
Ira Snyder2e077f82009-05-15 09:59:46 -0700818 return &first->async_tx;
819
820fail:
821 if (!first)
822 return NULL;
823
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000824 fsldma_free_desc_list_reverse(chan, &first->tx_list);
Ira Snyder2e077f82009-05-15 09:59:46 -0700825 return NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700826}
827
Ira Snyderc14330412010-09-30 11:46:45 +0000828static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan,
829 struct scatterlist *dst_sg, unsigned int dst_nents,
830 struct scatterlist *src_sg, unsigned int src_nents,
831 unsigned long flags)
832{
833 struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
834 struct fsldma_chan *chan = to_fsl_chan(dchan);
835 size_t dst_avail, src_avail;
836 dma_addr_t dst, src;
837 size_t len;
838
839 /* basic sanity checks */
840 if (dst_nents == 0 || src_nents == 0)
841 return NULL;
842
843 if (dst_sg == NULL || src_sg == NULL)
844 return NULL;
845
846 /*
847 * TODO: should we check that both scatterlists have the same
848 * TODO: number of bytes in total? Is that really an error?
849 */
850
851 /* get prepared for the loop */
852 dst_avail = sg_dma_len(dst_sg);
853 src_avail = sg_dma_len(src_sg);
854
855 /* run until we are out of scatterlist entries */
856 while (true) {
857
858 /* create the largest transaction possible */
859 len = min_t(size_t, src_avail, dst_avail);
860 len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT);
861 if (len == 0)
862 goto fetch;
863
864 dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail;
865 src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail;
866
867 /* allocate and populate the descriptor */
868 new = fsl_dma_alloc_descriptor(chan);
869 if (!new) {
Ira Snyderb1584712011-03-03 07:54:55 +0000870 chan_err(chan, "%s\n", msg_ld_oom);
Ira Snyderc14330412010-09-30 11:46:45 +0000871 goto fail;
872 }
Ira Snyderc14330412010-09-30 11:46:45 +0000873
874 set_desc_cnt(chan, &new->hw, len);
875 set_desc_src(chan, &new->hw, src);
876 set_desc_dst(chan, &new->hw, dst);
877
878 if (!first)
879 first = new;
880 else
881 set_desc_next(chan, &prev->hw, new->async_tx.phys);
882
883 new->async_tx.cookie = 0;
884 async_tx_ack(&new->async_tx);
885 prev = new;
886
887 /* Insert the link descriptor to the LD ring */
888 list_add_tail(&new->node, &first->tx_list);
889
890 /* update metadata */
891 dst_avail -= len;
892 src_avail -= len;
893
894fetch:
895 /* fetch the next dst scatterlist entry */
896 if (dst_avail == 0) {
897
898 /* no more entries: we're done */
899 if (dst_nents == 0)
900 break;
901
902 /* fetch the next entry: if there are no more: done */
903 dst_sg = sg_next(dst_sg);
904 if (dst_sg == NULL)
905 break;
906
907 dst_nents--;
908 dst_avail = sg_dma_len(dst_sg);
909 }
910
911 /* fetch the next src scatterlist entry */
912 if (src_avail == 0) {
913
914 /* no more entries: we're done */
915 if (src_nents == 0)
916 break;
917
918 /* fetch the next entry: if there are no more: done */
919 src_sg = sg_next(src_sg);
920 if (src_sg == NULL)
921 break;
922
923 src_nents--;
924 src_avail = sg_dma_len(src_sg);
925 }
926 }
927
928 new->async_tx.flags = flags; /* client is in control of this ack */
929 new->async_tx.cookie = -EBUSY;
930
931 /* Set End-of-link to the last link descriptor of new list */
932 set_ld_eol(chan, new);
933
934 return &first->async_tx;
935
936fail:
937 if (!first)
938 return NULL;
939
940 fsldma_free_desc_list_reverse(chan, &first->tx_list);
941 return NULL;
942}
943
Maxime Ripardb7f75522014-11-17 14:42:24 +0100944static int fsl_dma_device_terminate_all(struct dma_chan *dchan)
Ira Snyderbbea0b62009-09-08 17:53:04 -0700945{
Ira Snydera1c03312010-01-06 13:34:05 +0000946 struct fsldma_chan *chan;
Linus Walleijc3635c72010-03-26 16:44:01 -0700947
Ira Snydera1c03312010-01-06 13:34:05 +0000948 if (!dchan)
Linus Walleijc3635c72010-03-26 16:44:01 -0700949 return -EINVAL;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700950
Ira Snydera1c03312010-01-06 13:34:05 +0000951 chan = to_fsl_chan(dchan);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700952
Maxime Ripardb7f75522014-11-17 14:42:24 +0100953 spin_lock_bh(&chan->desc_lock);
Ira Snyderf04cd402011-03-03 07:54:58 +0000954
Maxime Ripardb7f75522014-11-17 14:42:24 +0100955 /* Halt the DMA engine */
956 dma_halt(chan);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700957
Maxime Ripardb7f75522014-11-17 14:42:24 +0100958 /* Remove and free all of the descriptors in the LD queue */
959 fsldma_free_desc_list(chan, &chan->ld_pending);
960 fsldma_free_desc_list(chan, &chan->ld_running);
961 fsldma_free_desc_list(chan, &chan->ld_completed);
962 chan->idle = true;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700963
Maxime Ripardb7f75522014-11-17 14:42:24 +0100964 spin_unlock_bh(&chan->desc_lock);
Linus Walleijc3635c72010-03-26 16:44:01 -0700965 return 0;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700966}
967
Maxime Ripardb7f75522014-11-17 14:42:24 +0100968static int fsl_dma_device_config(struct dma_chan *dchan,
969 struct dma_slave_config *config)
970{
971 struct fsldma_chan *chan;
972 int size;
973
974 if (!dchan)
975 return -EINVAL;
976
977 chan = to_fsl_chan(dchan);
978
979 /* make sure the channel supports setting burst size */
980 if (!chan->set_request_count)
981 return -ENXIO;
982
983 /* we set the controller burst size depending on direction */
984 if (config->direction == DMA_MEM_TO_DEV)
985 size = config->dst_addr_width * config->dst_maxburst;
986 else
987 size = config->src_addr_width * config->src_maxburst;
988
989 chan->set_request_count(chan, size);
990 return 0;
991}
992
993
Ira Snyderbbea0b62009-09-08 17:53:04 -0700994/**
Zhang Wei173acc72008-03-01 07:42:48 -0700995 * fsl_dma_memcpy_issue_pending - Issue the DMA start command
Ira Snydera1c03312010-01-06 13:34:05 +0000996 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700997 */
Ira Snydera1c03312010-01-06 13:34:05 +0000998static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700999{
Ira Snydera1c03312010-01-06 13:34:05 +00001000 struct fsldma_chan *chan = to_fsl_chan(dchan);
Ira Snyderdc8d4092011-03-03 07:55:00 +00001001
Hongbo Zhang2baff572014-05-21 16:03:01 +08001002 spin_lock_bh(&chan->desc_lock);
Ira Snydera1c03312010-01-06 13:34:05 +00001003 fsl_chan_xfer_ld_queue(chan);
Hongbo Zhang2baff572014-05-21 16:03:01 +08001004 spin_unlock_bh(&chan->desc_lock);
Zhang Wei173acc72008-03-01 07:42:48 -07001005}
1006
Zhang Wei173acc72008-03-01 07:42:48 -07001007/**
Linus Walleij07934482010-03-26 16:50:49 -07001008 * fsl_tx_status - Determine the DMA status
Ira Snydera1c03312010-01-06 13:34:05 +00001009 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -07001010 */
Linus Walleij07934482010-03-26 16:50:49 -07001011static enum dma_status fsl_tx_status(struct dma_chan *dchan,
Zhang Wei173acc72008-03-01 07:42:48 -07001012 dma_cookie_t cookie,
Linus Walleij07934482010-03-26 16:50:49 -07001013 struct dma_tx_state *txstate)
Zhang Wei173acc72008-03-01 07:42:48 -07001014{
Hongbo Zhang43452fa2014-05-21 16:03:03 +08001015 struct fsldma_chan *chan = to_fsl_chan(dchan);
1016 enum dma_status ret;
1017
1018 ret = dma_cookie_status(dchan, cookie, txstate);
1019 if (ret == DMA_COMPLETE)
1020 return ret;
1021
1022 spin_lock_bh(&chan->desc_lock);
1023 fsldma_cleanup_descriptors(chan);
1024 spin_unlock_bh(&chan->desc_lock);
1025
Andy Shevchenko9b0b0bd2013-05-27 15:14:35 +03001026 return dma_cookie_status(dchan, cookie, txstate);
Zhang Wei173acc72008-03-01 07:42:48 -07001027}
1028
Ira Snyderd3f620b2010-01-06 13:34:04 +00001029/*----------------------------------------------------------------------------*/
1030/* Interrupt Handling */
1031/*----------------------------------------------------------------------------*/
1032
Ira Snydere7a29152010-01-06 13:34:03 +00001033static irqreturn_t fsldma_chan_irq(int irq, void *data)
Zhang Wei173acc72008-03-01 07:42:48 -07001034{
Ira Snydera1c03312010-01-06 13:34:05 +00001035 struct fsldma_chan *chan = data;
Ira Snydera1c03312010-01-06 13:34:05 +00001036 u32 stat;
Zhang Wei173acc72008-03-01 07:42:48 -07001037
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001038 /* save and clear the status register */
Ira Snydera1c03312010-01-06 13:34:05 +00001039 stat = get_sr(chan);
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001040 set_sr(chan, stat);
Ira Snyderb1584712011-03-03 07:54:55 +00001041 chan_dbg(chan, "irq: stat = 0x%x\n", stat);
Zhang Wei173acc72008-03-01 07:42:48 -07001042
Ira Snyderf04cd402011-03-03 07:54:58 +00001043 /* check that this was really our device */
Zhang Wei173acc72008-03-01 07:42:48 -07001044 stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
1045 if (!stat)
1046 return IRQ_NONE;
1047
1048 if (stat & FSL_DMA_SR_TE)
Ira Snyderb1584712011-03-03 07:54:55 +00001049 chan_err(chan, "Transfer Error!\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001050
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001051 /*
1052 * Programming Error
Zhang Weif79abb62008-03-18 18:45:00 -07001053 * The DMA_INTERRUPT async_tx is a NULL transfer, which will
Masanari Iidad73111c2012-08-04 23:37:53 +09001054 * trigger a PE interrupt.
Zhang Weif79abb62008-03-18 18:45:00 -07001055 */
1056 if (stat & FSL_DMA_SR_PE) {
Ira Snyderb1584712011-03-03 07:54:55 +00001057 chan_dbg(chan, "irq: Programming Error INT\n");
Zhang Weif79abb62008-03-18 18:45:00 -07001058 stat &= ~FSL_DMA_SR_PE;
Ira Snyderf04cd402011-03-03 07:54:58 +00001059 if (get_bcr(chan) != 0)
1060 chan_err(chan, "Programming Error!\n");
Zhang Wei1c629792008-04-17 20:17:25 -07001061 }
1062
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001063 /*
1064 * For MPC8349, EOCDI event need to update cookie
Zhang Wei1c629792008-04-17 20:17:25 -07001065 * and start the next transfer if it exist.
1066 */
1067 if (stat & FSL_DMA_SR_EOCDI) {
Ira Snyderb1584712011-03-03 07:54:55 +00001068 chan_dbg(chan, "irq: End-of-Chain link INT\n");
Zhang Wei1c629792008-04-17 20:17:25 -07001069 stat &= ~FSL_DMA_SR_EOCDI;
Zhang Wei173acc72008-03-01 07:42:48 -07001070 }
1071
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001072 /*
1073 * If it current transfer is the end-of-transfer,
Zhang Wei173acc72008-03-01 07:42:48 -07001074 * we should clear the Channel Start bit for
1075 * prepare next transfer.
1076 */
Zhang Wei1c629792008-04-17 20:17:25 -07001077 if (stat & FSL_DMA_SR_EOLNI) {
Ira Snyderb1584712011-03-03 07:54:55 +00001078 chan_dbg(chan, "irq: End-of-link INT\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001079 stat &= ~FSL_DMA_SR_EOLNI;
Zhang Wei173acc72008-03-01 07:42:48 -07001080 }
1081
Ira Snyderf04cd402011-03-03 07:54:58 +00001082 /* check that the DMA controller is really idle */
1083 if (!dma_is_idle(chan))
1084 chan_err(chan, "irq: controller not idle!\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001085
Ira Snyderf04cd402011-03-03 07:54:58 +00001086 /* check that we handled all of the bits */
1087 if (stat)
1088 chan_err(chan, "irq: unhandled sr 0x%08x\n", stat);
1089
1090 /*
1091 * Schedule the tasklet to handle all cleanup of the current
1092 * transaction. It will start a new transaction if there is
1093 * one pending.
1094 */
Ira Snydera1c03312010-01-06 13:34:05 +00001095 tasklet_schedule(&chan->tasklet);
Ira Snyderf04cd402011-03-03 07:54:58 +00001096 chan_dbg(chan, "irq: Exit\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001097 return IRQ_HANDLED;
1098}
1099
Zhang Wei173acc72008-03-01 07:42:48 -07001100static void dma_do_tasklet(unsigned long data)
1101{
Ira Snydera1c03312010-01-06 13:34:05 +00001102 struct fsldma_chan *chan = (struct fsldma_chan *)data;
Ira Snyderf04cd402011-03-03 07:54:58 +00001103
1104 chan_dbg(chan, "tasklet entry\n");
1105
Hongbo Zhang2baff572014-05-21 16:03:01 +08001106 spin_lock_bh(&chan->desc_lock);
Ira Snyderdc8d4092011-03-03 07:55:00 +00001107
Ira Snyderdc8d4092011-03-03 07:55:00 +00001108 /* the hardware is now idle and ready for more */
Ira Snyderf04cd402011-03-03 07:54:58 +00001109 chan->idle = true;
Ira Snyderdc8d4092011-03-03 07:55:00 +00001110
Hongbo Zhang43452fa2014-05-21 16:03:03 +08001111 /* Run all cleanup for descriptors which have been completed */
1112 fsldma_cleanup_descriptors(chan);
1113
Hongbo Zhang2baff572014-05-21 16:03:01 +08001114 spin_unlock_bh(&chan->desc_lock);
Ira Snyderf04cd402011-03-03 07:54:58 +00001115
Ira Snyderf04cd402011-03-03 07:54:58 +00001116 chan_dbg(chan, "tasklet exit\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001117}
1118
Ira Snyderd3f620b2010-01-06 13:34:04 +00001119static irqreturn_t fsldma_ctrl_irq(int irq, void *data)
1120{
1121 struct fsldma_device *fdev = data;
1122 struct fsldma_chan *chan;
1123 unsigned int handled = 0;
1124 u32 gsr, mask;
1125 int i;
1126
1127 gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs)
1128 : in_le32(fdev->regs);
1129 mask = 0xff000000;
1130 dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr);
1131
1132 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1133 chan = fdev->chan[i];
1134 if (!chan)
1135 continue;
1136
1137 if (gsr & mask) {
1138 dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
1139 fsldma_chan_irq(irq, chan);
1140 handled++;
1141 }
1142
1143 gsr &= ~mask;
1144 mask >>= 8;
1145 }
1146
1147 return IRQ_RETVAL(handled);
1148}
1149
1150static void fsldma_free_irqs(struct fsldma_device *fdev)
1151{
1152 struct fsldma_chan *chan;
1153 int i;
1154
1155 if (fdev->irq != NO_IRQ) {
1156 dev_dbg(fdev->dev, "free per-controller IRQ\n");
1157 free_irq(fdev->irq, fdev);
1158 return;
1159 }
1160
1161 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1162 chan = fdev->chan[i];
1163 if (chan && chan->irq != NO_IRQ) {
Ira Snyderb1584712011-03-03 07:54:55 +00001164 chan_dbg(chan, "free per-channel IRQ\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001165 free_irq(chan->irq, chan);
1166 }
1167 }
1168}
1169
1170static int fsldma_request_irqs(struct fsldma_device *fdev)
1171{
1172 struct fsldma_chan *chan;
1173 int ret;
1174 int i;
1175
1176 /* if we have a per-controller IRQ, use that */
1177 if (fdev->irq != NO_IRQ) {
1178 dev_dbg(fdev->dev, "request per-controller IRQ\n");
1179 ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED,
1180 "fsldma-controller", fdev);
1181 return ret;
1182 }
1183
1184 /* no per-controller IRQ, use the per-channel IRQs */
1185 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1186 chan = fdev->chan[i];
1187 if (!chan)
1188 continue;
1189
1190 if (chan->irq == NO_IRQ) {
Ira Snyderb1584712011-03-03 07:54:55 +00001191 chan_err(chan, "interrupts property missing in device tree\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001192 ret = -ENODEV;
1193 goto out_unwind;
1194 }
1195
Ira Snyderb1584712011-03-03 07:54:55 +00001196 chan_dbg(chan, "request per-channel IRQ\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001197 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
1198 "fsldma-chan", chan);
1199 if (ret) {
Ira Snyderb1584712011-03-03 07:54:55 +00001200 chan_err(chan, "unable to request per-channel IRQ\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001201 goto out_unwind;
1202 }
1203 }
1204
1205 return 0;
1206
1207out_unwind:
1208 for (/* none */; i >= 0; i--) {
1209 chan = fdev->chan[i];
1210 if (!chan)
1211 continue;
1212
1213 if (chan->irq == NO_IRQ)
1214 continue;
1215
1216 free_irq(chan->irq, chan);
1217 }
1218
1219 return ret;
1220}
1221
Ira Snydera4f56d42010-01-06 13:34:01 +00001222/*----------------------------------------------------------------------------*/
1223/* OpenFirmware Subsystem */
1224/*----------------------------------------------------------------------------*/
1225
Bill Pemberton463a1f82012-11-19 13:22:55 -05001226static int fsl_dma_chan_probe(struct fsldma_device *fdev,
Timur Tabi77cd62e2008-09-26 17:00:11 -07001227 struct device_node *node, u32 feature, const char *compatible)
Zhang Wei173acc72008-03-01 07:42:48 -07001228{
Ira Snydera1c03312010-01-06 13:34:05 +00001229 struct fsldma_chan *chan;
Ira Snyder4ce0e952010-01-06 13:34:00 +00001230 struct resource res;
Zhang Wei173acc72008-03-01 07:42:48 -07001231 int err;
1232
Zhang Wei173acc72008-03-01 07:42:48 -07001233 /* alloc channel */
Ira Snydera1c03312010-01-06 13:34:05 +00001234 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1235 if (!chan) {
Ira Snydere7a29152010-01-06 13:34:03 +00001236 dev_err(fdev->dev, "no free memory for DMA channels!\n");
1237 err = -ENOMEM;
1238 goto out_return;
Zhang Wei173acc72008-03-01 07:42:48 -07001239 }
1240
Ira Snydere7a29152010-01-06 13:34:03 +00001241 /* ioremap registers for use */
Ira Snydera1c03312010-01-06 13:34:05 +00001242 chan->regs = of_iomap(node, 0);
1243 if (!chan->regs) {
Ira Snydere7a29152010-01-06 13:34:03 +00001244 dev_err(fdev->dev, "unable to ioremap registers\n");
1245 err = -ENOMEM;
Ira Snydera1c03312010-01-06 13:34:05 +00001246 goto out_free_chan;
Ira Snydere7a29152010-01-06 13:34:03 +00001247 }
1248
Ira Snyder4ce0e952010-01-06 13:34:00 +00001249 err = of_address_to_resource(node, 0, &res);
Zhang Wei173acc72008-03-01 07:42:48 -07001250 if (err) {
Ira Snydere7a29152010-01-06 13:34:03 +00001251 dev_err(fdev->dev, "unable to find 'reg' property\n");
1252 goto out_iounmap_regs;
Zhang Wei173acc72008-03-01 07:42:48 -07001253 }
1254
Ira Snydera1c03312010-01-06 13:34:05 +00001255 chan->feature = feature;
Zhang Wei173acc72008-03-01 07:42:48 -07001256 if (!fdev->feature)
Ira Snydera1c03312010-01-06 13:34:05 +00001257 fdev->feature = chan->feature;
Zhang Wei173acc72008-03-01 07:42:48 -07001258
Ira Snydere7a29152010-01-06 13:34:03 +00001259 /*
1260 * If the DMA device's feature is different than the feature
1261 * of its channels, report the bug
Zhang Wei173acc72008-03-01 07:42:48 -07001262 */
Ira Snydera1c03312010-01-06 13:34:05 +00001263 WARN_ON(fdev->feature != chan->feature);
Zhang Wei173acc72008-03-01 07:42:48 -07001264
Ira Snydera1c03312010-01-06 13:34:05 +00001265 chan->dev = fdev->dev;
Hongbo Zhang8de7a7d2013-09-26 17:33:43 +08001266 chan->id = (res.start & 0xfff) < 0x300 ?
1267 ((res.start - 0x100) & 0xfff) >> 7 :
1268 ((res.start - 0x200) & 0xfff) >> 7;
Ira Snydera1c03312010-01-06 13:34:05 +00001269 if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
Ira Snydere7a29152010-01-06 13:34:03 +00001270 dev_err(fdev->dev, "too many channels for device\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001271 err = -EINVAL;
Ira Snydere7a29152010-01-06 13:34:03 +00001272 goto out_iounmap_regs;
Zhang Wei173acc72008-03-01 07:42:48 -07001273 }
Zhang Wei173acc72008-03-01 07:42:48 -07001274
Ira Snydera1c03312010-01-06 13:34:05 +00001275 fdev->chan[chan->id] = chan;
1276 tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
Ira Snyderb1584712011-03-03 07:54:55 +00001277 snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id);
Ira Snydere7a29152010-01-06 13:34:03 +00001278
1279 /* Initialize the channel */
Ira Snydera1c03312010-01-06 13:34:05 +00001280 dma_init(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001281
1282 /* Clear cdar registers */
Ira Snydera1c03312010-01-06 13:34:05 +00001283 set_cdar(chan, 0);
Zhang Wei173acc72008-03-01 07:42:48 -07001284
Ira Snydera1c03312010-01-06 13:34:05 +00001285 switch (chan->feature & FSL_DMA_IP_MASK) {
Zhang Wei173acc72008-03-01 07:42:48 -07001286 case FSL_DMA_IP_85XX:
Ira Snydera1c03312010-01-06 13:34:05 +00001287 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
Zhang Wei173acc72008-03-01 07:42:48 -07001288 case FSL_DMA_IP_83XX:
Ira Snydera1c03312010-01-06 13:34:05 +00001289 chan->toggle_ext_start = fsl_chan_toggle_ext_start;
1290 chan->set_src_loop_size = fsl_chan_set_src_loop_size;
1291 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
1292 chan->set_request_count = fsl_chan_set_request_count;
Zhang Wei173acc72008-03-01 07:42:48 -07001293 }
1294
Ira Snydera1c03312010-01-06 13:34:05 +00001295 spin_lock_init(&chan->desc_lock);
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001296 INIT_LIST_HEAD(&chan->ld_pending);
1297 INIT_LIST_HEAD(&chan->ld_running);
Hongbo Zhang43452fa2014-05-21 16:03:03 +08001298 INIT_LIST_HEAD(&chan->ld_completed);
Ira Snyderf04cd402011-03-03 07:54:58 +00001299 chan->idle = true;
Hongbo Zhang14c6a332014-05-21 16:03:02 +08001300#ifdef CONFIG_PM
1301 chan->pm_state = RUNNING;
1302#endif
Zhang Wei173acc72008-03-01 07:42:48 -07001303
Ira Snydera1c03312010-01-06 13:34:05 +00001304 chan->common.device = &fdev->common;
Russell King - ARM Linux8ac69542012-03-06 22:36:27 +00001305 dma_cookie_init(&chan->common);
Zhang Wei173acc72008-03-01 07:42:48 -07001306
Ira Snyderd3f620b2010-01-06 13:34:04 +00001307 /* find the IRQ line, if it exists in the device tree */
Ira Snydera1c03312010-01-06 13:34:05 +00001308 chan->irq = irq_of_parse_and_map(node, 0);
Ira Snyderd3f620b2010-01-06 13:34:04 +00001309
Zhang Wei173acc72008-03-01 07:42:48 -07001310 /* Add the channel to DMA device channel list */
Ira Snydera1c03312010-01-06 13:34:05 +00001311 list_add_tail(&chan->common.device_node, &fdev->common.channels);
Zhang Wei173acc72008-03-01 07:42:48 -07001312
Ira Snydera1c03312010-01-06 13:34:05 +00001313 dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
1314 chan->irq != NO_IRQ ? chan->irq : fdev->irq);
Zhang Wei173acc72008-03-01 07:42:48 -07001315
1316 return 0;
Li Yang51ee87f2008-05-29 23:25:45 -07001317
Ira Snydere7a29152010-01-06 13:34:03 +00001318out_iounmap_regs:
Ira Snydera1c03312010-01-06 13:34:05 +00001319 iounmap(chan->regs);
1320out_free_chan:
1321 kfree(chan);
Ira Snydere7a29152010-01-06 13:34:03 +00001322out_return:
Zhang Wei173acc72008-03-01 07:42:48 -07001323 return err;
1324}
1325
Ira Snydera1c03312010-01-06 13:34:05 +00001326static void fsl_dma_chan_remove(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -07001327{
Ira Snydera1c03312010-01-06 13:34:05 +00001328 irq_dispose_mapping(chan->irq);
1329 list_del(&chan->common.device_node);
1330 iounmap(chan->regs);
1331 kfree(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001332}
1333
Bill Pemberton463a1f82012-11-19 13:22:55 -05001334static int fsldma_of_probe(struct platform_device *op)
Zhang Wei173acc72008-03-01 07:42:48 -07001335{
Ira Snydera4f56d42010-01-06 13:34:01 +00001336 struct fsldma_device *fdev;
Timur Tabi77cd62e2008-09-26 17:00:11 -07001337 struct device_node *child;
Ira Snydere7a29152010-01-06 13:34:03 +00001338 int err;
Zhang Wei173acc72008-03-01 07:42:48 -07001339
Ira Snydera4f56d42010-01-06 13:34:01 +00001340 fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
Zhang Wei173acc72008-03-01 07:42:48 -07001341 if (!fdev) {
Ira Snydere7a29152010-01-06 13:34:03 +00001342 dev_err(&op->dev, "No enough memory for 'priv'\n");
1343 err = -ENOMEM;
1344 goto out_return;
Zhang Wei173acc72008-03-01 07:42:48 -07001345 }
Ira Snydere7a29152010-01-06 13:34:03 +00001346
1347 fdev->dev = &op->dev;
Zhang Wei173acc72008-03-01 07:42:48 -07001348 INIT_LIST_HEAD(&fdev->common.channels);
1349
Ira Snydere7a29152010-01-06 13:34:03 +00001350 /* ioremap the registers for use */
Grant Likely61c7a082010-04-13 16:12:29 -07001351 fdev->regs = of_iomap(op->dev.of_node, 0);
Ira Snydere7a29152010-01-06 13:34:03 +00001352 if (!fdev->regs) {
1353 dev_err(&op->dev, "unable to ioremap registers\n");
1354 err = -ENOMEM;
1355 goto out_free_fdev;
Zhang Wei173acc72008-03-01 07:42:48 -07001356 }
1357
Ira Snyderd3f620b2010-01-06 13:34:04 +00001358 /* map the channel IRQ if it exists, but don't hookup the handler yet */
Grant Likely61c7a082010-04-13 16:12:29 -07001359 fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0);
Ira Snyderd3f620b2010-01-06 13:34:04 +00001360
Zhang Wei173acc72008-03-01 07:42:48 -07001361 dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
Ira Snyderc14330412010-09-30 11:46:45 +00001362 dma_cap_set(DMA_SG, fdev->common.cap_mask);
Ira Snyderbbea0b62009-09-08 17:53:04 -07001363 dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
Zhang Wei173acc72008-03-01 07:42:48 -07001364 fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
1365 fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
Zhang Wei173acc72008-03-01 07:42:48 -07001366 fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
Ira Snyderc14330412010-09-30 11:46:45 +00001367 fdev->common.device_prep_dma_sg = fsl_dma_prep_sg;
Linus Walleij07934482010-03-26 16:50:49 -07001368 fdev->common.device_tx_status = fsl_tx_status;
Zhang Wei173acc72008-03-01 07:42:48 -07001369 fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
Maxime Ripardb7f75522014-11-17 14:42:24 +01001370 fdev->common.device_config = fsl_dma_device_config;
1371 fdev->common.device_terminate_all = fsl_dma_device_terminate_all;
Ira Snydere7a29152010-01-06 13:34:03 +00001372 fdev->common.dev = &op->dev;
Zhang Wei173acc72008-03-01 07:42:48 -07001373
Kevin Hao75dc1772015-01-08 18:38:16 +08001374 fdev->common.src_addr_widths = FSL_DMA_BUSWIDTHS;
1375 fdev->common.dst_addr_widths = FSL_DMA_BUSWIDTHS;
1376 fdev->common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1377 fdev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
1378
Li Yange2c8e4252010-11-11 20:16:29 +08001379 dma_set_mask(&(op->dev), DMA_BIT_MASK(36));
1380
Jingoo Handd3daca2013-05-24 10:10:13 +09001381 platform_set_drvdata(op, fdev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001382
Ira Snydere7a29152010-01-06 13:34:03 +00001383 /*
1384 * We cannot use of_platform_bus_probe() because there is no
1385 * of_platform_bus_remove(). Instead, we manually instantiate every DMA
Timur Tabi77cd62e2008-09-26 17:00:11 -07001386 * channel object.
1387 */
Grant Likely61c7a082010-04-13 16:12:29 -07001388 for_each_child_of_node(op->dev.of_node, child) {
Ira Snydere7a29152010-01-06 13:34:03 +00001389 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001390 fsl_dma_chan_probe(fdev, child,
1391 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
1392 "fsl,eloplus-dma-channel");
Ira Snydere7a29152010-01-06 13:34:03 +00001393 }
1394
1395 if (of_device_is_compatible(child, "fsl,elo-dma-channel")) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001396 fsl_dma_chan_probe(fdev, child,
1397 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
1398 "fsl,elo-dma-channel");
Ira Snydere7a29152010-01-06 13:34:03 +00001399 }
Timur Tabi77cd62e2008-09-26 17:00:11 -07001400 }
Zhang Wei173acc72008-03-01 07:42:48 -07001401
Ira Snyderd3f620b2010-01-06 13:34:04 +00001402 /*
1403 * Hookup the IRQ handler(s)
1404 *
1405 * If we have a per-controller interrupt, we prefer that to the
1406 * per-channel interrupts to reduce the number of shared interrupt
1407 * handlers on the same IRQ line
1408 */
1409 err = fsldma_request_irqs(fdev);
1410 if (err) {
1411 dev_err(fdev->dev, "unable to request IRQs\n");
1412 goto out_free_fdev;
1413 }
1414
Zhang Wei173acc72008-03-01 07:42:48 -07001415 dma_async_device_register(&fdev->common);
1416 return 0;
1417
Ira Snydere7a29152010-01-06 13:34:03 +00001418out_free_fdev:
Ira Snyderd3f620b2010-01-06 13:34:04 +00001419 irq_dispose_mapping(fdev->irq);
Zhang Wei173acc72008-03-01 07:42:48 -07001420 kfree(fdev);
Ira Snydere7a29152010-01-06 13:34:03 +00001421out_return:
Zhang Wei173acc72008-03-01 07:42:48 -07001422 return err;
1423}
1424
Grant Likely2dc11582010-08-06 09:25:50 -06001425static int fsldma_of_remove(struct platform_device *op)
Timur Tabi77cd62e2008-09-26 17:00:11 -07001426{
Ira Snydera4f56d42010-01-06 13:34:01 +00001427 struct fsldma_device *fdev;
Timur Tabi77cd62e2008-09-26 17:00:11 -07001428 unsigned int i;
1429
Jingoo Handd3daca2013-05-24 10:10:13 +09001430 fdev = platform_get_drvdata(op);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001431 dma_async_device_unregister(&fdev->common);
1432
Ira Snyderd3f620b2010-01-06 13:34:04 +00001433 fsldma_free_irqs(fdev);
1434
Ira Snydere7a29152010-01-06 13:34:03 +00001435 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001436 if (fdev->chan[i])
1437 fsl_dma_chan_remove(fdev->chan[i]);
Ira Snydere7a29152010-01-06 13:34:03 +00001438 }
Timur Tabi77cd62e2008-09-26 17:00:11 -07001439
Ira Snydere7a29152010-01-06 13:34:03 +00001440 iounmap(fdev->regs);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001441 kfree(fdev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001442
1443 return 0;
1444}
1445
Hongbo Zhang14c6a332014-05-21 16:03:02 +08001446#ifdef CONFIG_PM
1447static int fsldma_suspend_late(struct device *dev)
1448{
1449 struct platform_device *pdev = to_platform_device(dev);
1450 struct fsldma_device *fdev = platform_get_drvdata(pdev);
1451 struct fsldma_chan *chan;
1452 int i;
1453
1454 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1455 chan = fdev->chan[i];
1456 if (!chan)
1457 continue;
1458
1459 spin_lock_bh(&chan->desc_lock);
1460 if (unlikely(!chan->idle))
1461 goto out;
1462 chan->regs_save.mr = get_mr(chan);
1463 chan->pm_state = SUSPENDED;
1464 spin_unlock_bh(&chan->desc_lock);
1465 }
1466 return 0;
1467
1468out:
1469 for (; i >= 0; i--) {
1470 chan = fdev->chan[i];
1471 if (!chan)
1472 continue;
1473 chan->pm_state = RUNNING;
1474 spin_unlock_bh(&chan->desc_lock);
1475 }
1476 return -EBUSY;
1477}
1478
1479static int fsldma_resume_early(struct device *dev)
1480{
1481 struct platform_device *pdev = to_platform_device(dev);
1482 struct fsldma_device *fdev = platform_get_drvdata(pdev);
1483 struct fsldma_chan *chan;
1484 u32 mode;
1485 int i;
1486
1487 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1488 chan = fdev->chan[i];
1489 if (!chan)
1490 continue;
1491
1492 spin_lock_bh(&chan->desc_lock);
1493 mode = chan->regs_save.mr
1494 & ~FSL_DMA_MR_CS & ~FSL_DMA_MR_CC & ~FSL_DMA_MR_CA;
1495 set_mr(chan, mode);
1496 chan->pm_state = RUNNING;
1497 spin_unlock_bh(&chan->desc_lock);
1498 }
1499
1500 return 0;
1501}
1502
1503static const struct dev_pm_ops fsldma_pm_ops = {
1504 .suspend_late = fsldma_suspend_late,
1505 .resume_early = fsldma_resume_early,
1506};
1507#endif
1508
Márton Németh4b1cf1f2010-02-02 23:41:06 -07001509static const struct of_device_id fsldma_of_ids[] = {
Hongbo Zhang8de7a7d2013-09-26 17:33:43 +08001510 { .compatible = "fsl,elo3-dma", },
Kumar Gala049c9d42008-03-31 11:13:21 -05001511 { .compatible = "fsl,eloplus-dma", },
1512 { .compatible = "fsl,elo-dma", },
Zhang Wei173acc72008-03-01 07:42:48 -07001513 {}
1514};
Luis de Bethencourt7522c242015-09-16 22:57:17 +02001515MODULE_DEVICE_TABLE(of, fsldma_of_ids);
Zhang Wei173acc72008-03-01 07:42:48 -07001516
Ira W. Snyder8faa7cf2011-04-07 10:33:03 -07001517static struct platform_driver fsldma_of_driver = {
Grant Likely40182942010-04-13 16:13:02 -07001518 .driver = {
1519 .name = "fsl-elo-dma",
Grant Likely40182942010-04-13 16:13:02 -07001520 .of_match_table = fsldma_of_ids,
Hongbo Zhang14c6a332014-05-21 16:03:02 +08001521#ifdef CONFIG_PM
1522 .pm = &fsldma_pm_ops,
1523#endif
Grant Likely40182942010-04-13 16:13:02 -07001524 },
1525 .probe = fsldma_of_probe,
1526 .remove = fsldma_of_remove,
Zhang Wei173acc72008-03-01 07:42:48 -07001527};
1528
Ira Snydera4f56d42010-01-06 13:34:01 +00001529/*----------------------------------------------------------------------------*/
1530/* Module Init / Exit */
1531/*----------------------------------------------------------------------------*/
1532
1533static __init int fsldma_init(void)
Zhang Wei173acc72008-03-01 07:42:48 -07001534{
Hongbo Zhang8de7a7d2013-09-26 17:33:43 +08001535 pr_info("Freescale Elo series DMA driver\n");
Grant Likely00006122011-02-22 19:59:54 -07001536 return platform_driver_register(&fsldma_of_driver);
Zhang Wei173acc72008-03-01 07:42:48 -07001537}
1538
Ira Snydera4f56d42010-01-06 13:34:01 +00001539static void __exit fsldma_exit(void)
Timur Tabi77cd62e2008-09-26 17:00:11 -07001540{
Grant Likely00006122011-02-22 19:59:54 -07001541 platform_driver_unregister(&fsldma_of_driver);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001542}
1543
Ira Snydera4f56d42010-01-06 13:34:01 +00001544subsys_initcall(fsldma_init);
1545module_exit(fsldma_exit);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001546
Hongbo Zhang8de7a7d2013-09-26 17:33:43 +08001547MODULE_DESCRIPTION("Freescale Elo series DMA driver");
Timur Tabi77cd62e2008-09-26 17:00:11 -07001548MODULE_LICENSE("GPL");