Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1 | /* |
Tomoya MORINAGA | eca9dfa | 2011-10-28 09:38:50 +0900 | [diff] [blame] | 2 | *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 3 | * |
| 4 | *This program is free software; you can redistribute it and/or modify |
| 5 | *it under the terms of the GNU General Public License as published by |
| 6 | *the Free Software Foundation; version 2 of the License. |
| 7 | * |
| 8 | *This program is distributed in the hope that it will be useful, |
| 9 | *but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | *GNU General Public License for more details. |
| 12 | * |
| 13 | *You should have received a copy of the GNU General Public License |
| 14 | *along with this program; if not, write to the Free Software |
| 15 | *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. |
| 16 | */ |
Liang Li | 1f9db09 | 2013-01-19 17:52:11 +0800 | [diff] [blame] | 17 | #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
| 18 | #define SUPPORT_SYSRQ |
| 19 | #endif |
Uwe Kleine-König | 0e2adc0 | 2011-05-26 10:41:17 +0200 | [diff] [blame] | 20 | #include <linux/kernel.h> |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 21 | #include <linux/serial_reg.h> |
Andrew Morton | 023bc8e | 2011-05-24 17:13:44 -0700 | [diff] [blame] | 22 | #include <linux/slab.h> |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 23 | #include <linux/module.h> |
| 24 | #include <linux/pci.h> |
Liang Li | 1f9db09 | 2013-01-19 17:52:11 +0800 | [diff] [blame] | 25 | #include <linux/console.h> |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 26 | #include <linux/serial_core.h> |
Jiri Slaby | ee160a3 | 2011-09-01 16:20:57 +0200 | [diff] [blame] | 27 | #include <linux/tty.h> |
| 28 | #include <linux/tty_flip.h> |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 29 | #include <linux/interrupt.h> |
| 30 | #include <linux/io.h> |
Denis Turischev | 6ae705b | 2011-03-10 15:14:00 +0200 | [diff] [blame] | 31 | #include <linux/dmi.h> |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 32 | #include <linux/nmi.h> |
| 33 | #include <linux/delay.h> |
Zubair Lutfullah Kakakhel | 7789e5a | 2016-08-12 12:48:54 +0100 | [diff] [blame^] | 34 | #include <linux/of.h> |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 35 | |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 36 | #include <linux/debugfs.h> |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 37 | #include <linux/dmaengine.h> |
| 38 | #include <linux/pch_dma.h> |
| 39 | |
| 40 | enum { |
| 41 | PCH_UART_HANDLED_RX_INT_SHIFT, |
| 42 | PCH_UART_HANDLED_TX_INT_SHIFT, |
| 43 | PCH_UART_HANDLED_RX_ERR_INT_SHIFT, |
| 44 | PCH_UART_HANDLED_RX_TRG_INT_SHIFT, |
| 45 | PCH_UART_HANDLED_MS_INT_SHIFT, |
Tomoya MORINAGA | 04e2c2e | 2012-03-26 14:43:05 +0900 | [diff] [blame] | 46 | PCH_UART_HANDLED_LS_INT_SHIFT, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 47 | }; |
| 48 | |
| 49 | enum { |
| 50 | PCH_UART_8LINE, |
| 51 | PCH_UART_2LINE, |
| 52 | }; |
| 53 | |
| 54 | #define PCH_UART_DRIVER_DEVICE "ttyPCH" |
| 55 | |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 56 | /* Set the max number of UART port |
| 57 | * Intel EG20T PCH: 4 port |
Tomoya MORINAGA | eca9dfa | 2011-10-28 09:38:50 +0900 | [diff] [blame] | 58 | * LAPIS Semiconductor ML7213 IOH: 3 port |
| 59 | * LAPIS Semiconductor ML7223 IOH: 2 port |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 60 | */ |
| 61 | #define PCH_UART_NR 4 |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 62 | |
| 63 | #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1)) |
| 64 | #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1)) |
| 65 | #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\ |
| 66 | PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1)) |
| 67 | #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\ |
| 68 | PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) |
| 69 | #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) |
| 70 | |
Tomoya MORINAGA | 04e2c2e | 2012-03-26 14:43:05 +0900 | [diff] [blame] | 71 | #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1)) |
| 72 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 73 | #define PCH_UART_RBR 0x00 |
| 74 | #define PCH_UART_THR 0x00 |
| 75 | |
| 76 | #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\ |
| 77 | PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI) |
| 78 | #define PCH_UART_IER_ERBFI 0x00000001 |
| 79 | #define PCH_UART_IER_ETBEI 0x00000002 |
| 80 | #define PCH_UART_IER_ELSI 0x00000004 |
| 81 | #define PCH_UART_IER_EDSSI 0x00000008 |
| 82 | |
| 83 | #define PCH_UART_IIR_IP 0x00000001 |
| 84 | #define PCH_UART_IIR_IID 0x00000006 |
| 85 | #define PCH_UART_IIR_MSI 0x00000000 |
| 86 | #define PCH_UART_IIR_TRI 0x00000002 |
| 87 | #define PCH_UART_IIR_RRI 0x00000004 |
| 88 | #define PCH_UART_IIR_REI 0x00000006 |
| 89 | #define PCH_UART_IIR_TOI 0x00000008 |
| 90 | #define PCH_UART_IIR_FIFO256 0x00000020 |
| 91 | #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256 |
| 92 | #define PCH_UART_IIR_FE 0x000000C0 |
| 93 | |
| 94 | #define PCH_UART_FCR_FIFOE 0x00000001 |
| 95 | #define PCH_UART_FCR_RFR 0x00000002 |
| 96 | #define PCH_UART_FCR_TFR 0x00000004 |
| 97 | #define PCH_UART_FCR_DMS 0x00000008 |
| 98 | #define PCH_UART_FCR_FIFO256 0x00000020 |
| 99 | #define PCH_UART_FCR_RFTL 0x000000C0 |
| 100 | |
| 101 | #define PCH_UART_FCR_RFTL1 0x00000000 |
| 102 | #define PCH_UART_FCR_RFTL64 0x00000040 |
| 103 | #define PCH_UART_FCR_RFTL128 0x00000080 |
| 104 | #define PCH_UART_FCR_RFTL224 0x000000C0 |
| 105 | #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64 |
| 106 | #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128 |
| 107 | #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224 |
| 108 | #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64 |
| 109 | #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128 |
| 110 | #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224 |
| 111 | #define PCH_UART_FCR_RFTL_SHIFT 6 |
| 112 | |
| 113 | #define PCH_UART_LCR_WLS 0x00000003 |
| 114 | #define PCH_UART_LCR_STB 0x00000004 |
| 115 | #define PCH_UART_LCR_PEN 0x00000008 |
| 116 | #define PCH_UART_LCR_EPS 0x00000010 |
| 117 | #define PCH_UART_LCR_SP 0x00000020 |
| 118 | #define PCH_UART_LCR_SB 0x00000040 |
| 119 | #define PCH_UART_LCR_DLAB 0x00000080 |
| 120 | #define PCH_UART_LCR_NP 0x00000000 |
| 121 | #define PCH_UART_LCR_OP PCH_UART_LCR_PEN |
| 122 | #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS) |
| 123 | #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP) |
| 124 | #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\ |
| 125 | PCH_UART_LCR_SP) |
| 126 | |
| 127 | #define PCH_UART_LCR_5BIT 0x00000000 |
| 128 | #define PCH_UART_LCR_6BIT 0x00000001 |
| 129 | #define PCH_UART_LCR_7BIT 0x00000002 |
| 130 | #define PCH_UART_LCR_8BIT 0x00000003 |
| 131 | |
| 132 | #define PCH_UART_MCR_DTR 0x00000001 |
| 133 | #define PCH_UART_MCR_RTS 0x00000002 |
| 134 | #define PCH_UART_MCR_OUT 0x0000000C |
| 135 | #define PCH_UART_MCR_LOOP 0x00000010 |
| 136 | #define PCH_UART_MCR_AFE 0x00000020 |
| 137 | |
| 138 | #define PCH_UART_LSR_DR 0x00000001 |
| 139 | #define PCH_UART_LSR_ERR (1<<7) |
| 140 | |
| 141 | #define PCH_UART_MSR_DCTS 0x00000001 |
| 142 | #define PCH_UART_MSR_DDSR 0x00000002 |
| 143 | #define PCH_UART_MSR_TERI 0x00000004 |
| 144 | #define PCH_UART_MSR_DDCD 0x00000008 |
| 145 | #define PCH_UART_MSR_CTS 0x00000010 |
| 146 | #define PCH_UART_MSR_DSR 0x00000020 |
| 147 | #define PCH_UART_MSR_RI 0x00000040 |
| 148 | #define PCH_UART_MSR_DCD 0x00000080 |
| 149 | #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\ |
| 150 | PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD) |
| 151 | |
| 152 | #define PCH_UART_DLL 0x00 |
| 153 | #define PCH_UART_DLM 0x01 |
| 154 | |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 155 | #define PCH_UART_BRCSR 0x0E |
| 156 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 157 | #define PCH_UART_IID_RLS (PCH_UART_IIR_REI) |
| 158 | #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) |
| 159 | #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) |
| 160 | #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI) |
| 161 | #define PCH_UART_IID_MS (PCH_UART_IIR_MSI) |
| 162 | |
| 163 | #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP) |
| 164 | #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP) |
| 165 | #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP) |
| 166 | #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P) |
| 167 | #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P) |
| 168 | #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT) |
| 169 | #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT) |
| 170 | #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT) |
| 171 | #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT) |
| 172 | #define PCH_UART_HAL_STB1 0 |
| 173 | #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB) |
| 174 | |
| 175 | #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR) |
| 176 | #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR) |
| 177 | #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \ |
| 178 | PCH_UART_HAL_CLR_RX_FIFO) |
| 179 | |
| 180 | #define PCH_UART_HAL_DMA_MODE0 0 |
| 181 | #define PCH_UART_HAL_FIFO_DIS 0 |
| 182 | #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE) |
| 183 | #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \ |
| 184 | PCH_UART_FCR_FIFO256) |
| 185 | #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256) |
| 186 | #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1) |
| 187 | #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64) |
| 188 | #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128) |
| 189 | #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224) |
| 190 | #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16) |
| 191 | #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32) |
| 192 | #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56) |
| 193 | #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4) |
| 194 | #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8) |
| 195 | #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14) |
| 196 | #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64) |
| 197 | #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128) |
| 198 | #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224) |
| 199 | |
| 200 | #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI) |
| 201 | #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI) |
| 202 | #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI) |
| 203 | #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI) |
| 204 | #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK) |
| 205 | |
| 206 | #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR) |
| 207 | #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS) |
| 208 | #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT) |
| 209 | #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP) |
| 210 | #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE) |
| 211 | |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 212 | #define PCI_VENDOR_ID_ROHM 0x10DB |
| 213 | |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 214 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
| 215 | |
Darren Hart | 077175f | 2012-03-09 09:51:49 -0800 | [diff] [blame] | 216 | #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */ |
| 217 | #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */ |
| 218 | #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */ |
| 219 | #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */ |
Michael Brunner | 11bbd5b | 2012-03-23 11:06:37 +0100 | [diff] [blame] | 220 | #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */ |
Darren Hart | 29692d0 | 2013-06-25 18:53:22 -0700 | [diff] [blame] | 221 | #define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */ |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 222 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 223 | struct pch_uart_buffer { |
| 224 | unsigned char *buf; |
| 225 | int size; |
| 226 | }; |
| 227 | |
| 228 | struct eg20t_port { |
| 229 | struct uart_port port; |
| 230 | int port_type; |
| 231 | void __iomem *membase; |
| 232 | resource_size_t mapbase; |
| 233 | unsigned int iobase; |
| 234 | struct pci_dev *pdev; |
| 235 | int fifo_size; |
Darren Hart | e26439c | 2013-07-29 15:15:07 -0700 | [diff] [blame] | 236 | unsigned int uartclk; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 237 | int start_tx; |
| 238 | int start_rx; |
| 239 | int tx_empty; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 240 | int trigger; |
| 241 | int trigger_level; |
| 242 | struct pch_uart_buffer rxbuf; |
| 243 | unsigned int dmsr; |
| 244 | unsigned int fcr; |
Tomoya MORINAGA | 9af7155 | 2011-02-23 10:03:17 +0900 | [diff] [blame] | 245 | unsigned int mcr; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 246 | unsigned int use_dma; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 247 | struct dma_async_tx_descriptor *desc_tx; |
| 248 | struct dma_async_tx_descriptor *desc_rx; |
| 249 | struct pch_dma_slave param_tx; |
| 250 | struct pch_dma_slave param_rx; |
| 251 | struct dma_chan *chan_tx; |
| 252 | struct dma_chan *chan_rx; |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 253 | struct scatterlist *sg_tx_p; |
| 254 | int nent; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 255 | struct scatterlist sg_rx; |
| 256 | int tx_dma_use; |
| 257 | void *rx_buf_virt; |
| 258 | dma_addr_t rx_buf_dma; |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 259 | |
| 260 | struct dentry *debugfs; |
Alexander Stein | 50d16ca | 2014-03-25 14:05:08 +0100 | [diff] [blame] | 261 | #define IRQ_NAME_SIZE 17 |
| 262 | char irq_name[IRQ_NAME_SIZE]; |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 263 | |
| 264 | /* protect the eg20t_port private structure and io access to membase */ |
| 265 | spinlock_t lock; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 266 | }; |
| 267 | |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 268 | /** |
| 269 | * struct pch_uart_driver_data - private data structure for UART-DMA |
| 270 | * @port_type: The number of DMA channel |
| 271 | * @line_no: UART port line number (0, 1, 2...) |
| 272 | */ |
| 273 | struct pch_uart_driver_data { |
| 274 | int port_type; |
| 275 | int line_no; |
| 276 | }; |
| 277 | |
| 278 | enum pch_uart_num_t { |
| 279 | pch_et20t_uart0 = 0, |
| 280 | pch_et20t_uart1, |
| 281 | pch_et20t_uart2, |
| 282 | pch_et20t_uart3, |
| 283 | pch_ml7213_uart0, |
| 284 | pch_ml7213_uart1, |
| 285 | pch_ml7213_uart2, |
Tomoya MORINAGA | 177c2cb | 2011-05-09 17:25:20 +0900 | [diff] [blame] | 286 | pch_ml7223_uart0, |
| 287 | pch_ml7223_uart1, |
Tomoya MORINAGA | 8249f74 | 2011-10-28 09:38:49 +0900 | [diff] [blame] | 288 | pch_ml7831_uart0, |
| 289 | pch_ml7831_uart1, |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 290 | }; |
| 291 | |
| 292 | static struct pch_uart_driver_data drv_dat[] = { |
| 293 | [pch_et20t_uart0] = {PCH_UART_8LINE, 0}, |
| 294 | [pch_et20t_uart1] = {PCH_UART_2LINE, 1}, |
| 295 | [pch_et20t_uart2] = {PCH_UART_2LINE, 2}, |
| 296 | [pch_et20t_uart3] = {PCH_UART_2LINE, 3}, |
| 297 | [pch_ml7213_uart0] = {PCH_UART_8LINE, 0}, |
| 298 | [pch_ml7213_uart1] = {PCH_UART_2LINE, 1}, |
| 299 | [pch_ml7213_uart2] = {PCH_UART_2LINE, 2}, |
Tomoya MORINAGA | 177c2cb | 2011-05-09 17:25:20 +0900 | [diff] [blame] | 300 | [pch_ml7223_uart0] = {PCH_UART_8LINE, 0}, |
| 301 | [pch_ml7223_uart1] = {PCH_UART_2LINE, 1}, |
Tomoya MORINAGA | 8249f74 | 2011-10-28 09:38:49 +0900 | [diff] [blame] | 302 | [pch_ml7831_uart0] = {PCH_UART_8LINE, 0}, |
| 303 | [pch_ml7831_uart1] = {PCH_UART_2LINE, 1}, |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 304 | }; |
| 305 | |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 306 | #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE |
| 307 | static struct eg20t_port *pch_uart_ports[PCH_UART_NR]; |
| 308 | #endif |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 309 | static unsigned int default_baud = 9600; |
Darren Hart | 2a44feb | 2012-03-09 09:51:50 -0800 | [diff] [blame] | 310 | static unsigned int user_uartclk = 0; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 311 | static const int trigger_level_256[4] = { 1, 64, 128, 224 }; |
| 312 | static const int trigger_level_64[4] = { 1, 16, 32, 56 }; |
| 313 | static const int trigger_level_16[4] = { 1, 4, 8, 14 }; |
| 314 | static const int trigger_level_1[4] = { 1, 1, 1, 1 }; |
| 315 | |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 316 | #ifdef CONFIG_DEBUG_FS |
| 317 | |
| 318 | #define PCH_REGS_BUFSIZE 1024 |
Stephen Boyd | 234e340 | 2012-04-05 14:25:11 -0700 | [diff] [blame] | 319 | |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 320 | |
| 321 | static ssize_t port_show_regs(struct file *file, char __user *user_buf, |
| 322 | size_t count, loff_t *ppos) |
| 323 | { |
| 324 | struct eg20t_port *priv = file->private_data; |
| 325 | char *buf; |
| 326 | u32 len = 0; |
| 327 | ssize_t ret; |
| 328 | unsigned char lcr; |
| 329 | |
| 330 | buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL); |
| 331 | if (!buf) |
| 332 | return 0; |
| 333 | |
| 334 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 335 | "PCH EG20T port[%d] regs:\n", priv->port.line); |
| 336 | |
| 337 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 338 | "=================================\n"); |
| 339 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 340 | "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); |
| 341 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 342 | "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); |
| 343 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 344 | "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); |
| 345 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 346 | "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); |
| 347 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 348 | "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); |
| 349 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 350 | "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); |
| 351 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 352 | "BRCSR: \t0x%02x\n", |
| 353 | ioread8(priv->membase + PCH_UART_BRCSR)); |
| 354 | |
| 355 | lcr = ioread8(priv->membase + UART_LCR); |
| 356 | iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); |
| 357 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 358 | "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL)); |
| 359 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, |
| 360 | "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM)); |
| 361 | iowrite8(lcr, priv->membase + UART_LCR); |
| 362 | |
| 363 | if (len > PCH_REGS_BUFSIZE) |
| 364 | len = PCH_REGS_BUFSIZE; |
| 365 | |
| 366 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); |
| 367 | kfree(buf); |
| 368 | return ret; |
| 369 | } |
| 370 | |
| 371 | static const struct file_operations port_regs_ops = { |
| 372 | .owner = THIS_MODULE, |
Stephen Boyd | 234e340 | 2012-04-05 14:25:11 -0700 | [diff] [blame] | 373 | .open = simple_open, |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 374 | .read = port_show_regs, |
| 375 | .llseek = default_llseek, |
| 376 | }; |
| 377 | #endif /* CONFIG_DEBUG_FS */ |
| 378 | |
Darren Hart | 0a09ae9 | 2013-07-29 09:58:14 -0700 | [diff] [blame] | 379 | static struct dmi_system_id pch_uart_dmi_table[] = { |
Darren Hart | 4e32348 | 2013-07-12 17:58:05 -0700 | [diff] [blame] | 380 | { |
| 381 | .ident = "CM-iTC", |
| 382 | { |
| 383 | DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"), |
| 384 | }, |
| 385 | (void *)CMITC_UARTCLK, |
| 386 | }, |
| 387 | { |
| 388 | .ident = "FRI2", |
| 389 | { |
| 390 | DMI_MATCH(DMI_BIOS_VERSION, "FRI2"), |
| 391 | }, |
| 392 | (void *)FRI2_64_UARTCLK, |
| 393 | }, |
| 394 | { |
| 395 | .ident = "Fish River Island II", |
| 396 | { |
| 397 | DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"), |
| 398 | }, |
| 399 | (void *)FRI2_48_UARTCLK, |
| 400 | }, |
| 401 | { |
| 402 | .ident = "COMe-mTT", |
| 403 | { |
| 404 | DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"), |
| 405 | }, |
| 406 | (void *)NTC1_UARTCLK, |
| 407 | }, |
| 408 | { |
| 409 | .ident = "nanoETXexpress-TT", |
| 410 | { |
| 411 | DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"), |
| 412 | }, |
| 413 | (void *)NTC1_UARTCLK, |
| 414 | }, |
| 415 | { |
| 416 | .ident = "MinnowBoard", |
| 417 | { |
| 418 | DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"), |
| 419 | }, |
| 420 | (void *)MINNOW_UARTCLK, |
| 421 | }, |
| 422 | }; |
| 423 | |
Darren Hart | 077175f | 2012-03-09 09:51:49 -0800 | [diff] [blame] | 424 | /* Return UART clock, checking for board specific clocks. */ |
Darren Hart | e26439c | 2013-07-29 15:15:07 -0700 | [diff] [blame] | 425 | static unsigned int pch_uart_get_uartclk(void) |
Darren Hart | 077175f | 2012-03-09 09:51:49 -0800 | [diff] [blame] | 426 | { |
Darren Hart | 4e32348 | 2013-07-12 17:58:05 -0700 | [diff] [blame] | 427 | const struct dmi_system_id *d; |
Darren Hart | 077175f | 2012-03-09 09:51:49 -0800 | [diff] [blame] | 428 | |
Darren Hart | 2a44feb | 2012-03-09 09:51:50 -0800 | [diff] [blame] | 429 | if (user_uartclk) |
| 430 | return user_uartclk; |
| 431 | |
Darren Hart | 4e32348 | 2013-07-12 17:58:05 -0700 | [diff] [blame] | 432 | d = dmi_first_match(pch_uart_dmi_table); |
| 433 | if (d) |
Darren Hart | e26439c | 2013-07-29 15:15:07 -0700 | [diff] [blame] | 434 | return (unsigned long)d->driver_data; |
Darren Hart | 29692d0 | 2013-06-25 18:53:22 -0700 | [diff] [blame] | 435 | |
Darren Hart | 077175f | 2012-03-09 09:51:49 -0800 | [diff] [blame] | 436 | return DEFAULT_UARTCLK; |
| 437 | } |
| 438 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 439 | static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, |
| 440 | unsigned int flag) |
| 441 | { |
| 442 | u8 ier = ioread8(priv->membase + UART_IER); |
| 443 | ier |= flag & PCH_UART_IER_MASK; |
| 444 | iowrite8(ier, priv->membase + UART_IER); |
| 445 | } |
| 446 | |
| 447 | static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv, |
| 448 | unsigned int flag) |
| 449 | { |
| 450 | u8 ier = ioread8(priv->membase + UART_IER); |
| 451 | ier &= ~(flag & PCH_UART_IER_MASK); |
| 452 | iowrite8(ier, priv->membase + UART_IER); |
| 453 | } |
| 454 | |
Darren Hart | e26439c | 2013-07-29 15:15:07 -0700 | [diff] [blame] | 455 | static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 456 | unsigned int parity, unsigned int bits, |
| 457 | unsigned int stb) |
| 458 | { |
| 459 | unsigned int dll, dlm, lcr; |
| 460 | int div; |
| 461 | |
Darren Hart | a8a3ec9 | 2012-03-09 09:51:48 -0800 | [diff] [blame] | 462 | div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 463 | if (div < 0 || USHRT_MAX <= div) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 464 | dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 465 | return -EINVAL; |
| 466 | } |
| 467 | |
| 468 | dll = (unsigned int)div & 0x00FFU; |
| 469 | dlm = ((unsigned int)div >> 8) & 0x00FFU; |
| 470 | |
| 471 | if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 472 | dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 473 | return -EINVAL; |
| 474 | } |
| 475 | |
| 476 | if (bits & ~PCH_UART_LCR_WLS) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 477 | dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 478 | return -EINVAL; |
| 479 | } |
| 480 | |
| 481 | if (stb & ~PCH_UART_LCR_STB) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 482 | dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 483 | return -EINVAL; |
| 484 | } |
| 485 | |
| 486 | lcr = parity; |
| 487 | lcr |= bits; |
| 488 | lcr |= stb; |
| 489 | |
Darren Hart | e26439c | 2013-07-29 15:15:07 -0700 | [diff] [blame] | 490 | dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n", |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 491 | __func__, baud, div, lcr, jiffies); |
| 492 | iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); |
| 493 | iowrite8(dll, priv->membase + PCH_UART_DLL); |
| 494 | iowrite8(dlm, priv->membase + PCH_UART_DLM); |
| 495 | iowrite8(lcr, priv->membase + UART_LCR); |
| 496 | |
| 497 | return 0; |
| 498 | } |
| 499 | |
| 500 | static int pch_uart_hal_fifo_reset(struct eg20t_port *priv, |
| 501 | unsigned int flag) |
| 502 | { |
| 503 | if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 504 | dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", |
| 505 | __func__, flag); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 506 | return -EINVAL; |
| 507 | } |
| 508 | |
| 509 | iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); |
| 510 | iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, |
| 511 | priv->membase + UART_FCR); |
| 512 | iowrite8(priv->fcr, priv->membase + UART_FCR); |
| 513 | |
| 514 | return 0; |
| 515 | } |
| 516 | |
| 517 | static int pch_uart_hal_set_fifo(struct eg20t_port *priv, |
| 518 | unsigned int dmamode, |
| 519 | unsigned int fifo_size, unsigned int trigger) |
| 520 | { |
| 521 | u8 fcr; |
| 522 | |
| 523 | if (dmamode & ~PCH_UART_FCR_DMS) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 524 | dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", |
| 525 | __func__, dmamode); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 526 | return -EINVAL; |
| 527 | } |
| 528 | |
| 529 | if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 530 | dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", |
| 531 | __func__, fifo_size); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 532 | return -EINVAL; |
| 533 | } |
| 534 | |
| 535 | if (trigger & ~PCH_UART_FCR_RFTL) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 536 | dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", |
| 537 | __func__, trigger); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 538 | return -EINVAL; |
| 539 | } |
| 540 | |
| 541 | switch (priv->fifo_size) { |
| 542 | case 256: |
| 543 | priv->trigger_level = |
| 544 | trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT]; |
| 545 | break; |
| 546 | case 64: |
| 547 | priv->trigger_level = |
| 548 | trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT]; |
| 549 | break; |
| 550 | case 16: |
| 551 | priv->trigger_level = |
| 552 | trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT]; |
| 553 | break; |
| 554 | default: |
| 555 | priv->trigger_level = |
| 556 | trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT]; |
| 557 | break; |
| 558 | } |
| 559 | fcr = |
| 560 | dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR; |
| 561 | iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); |
| 562 | iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR, |
| 563 | priv->membase + UART_FCR); |
| 564 | iowrite8(fcr, priv->membase + UART_FCR); |
| 565 | priv->fcr = fcr; |
| 566 | |
| 567 | return 0; |
| 568 | } |
| 569 | |
| 570 | static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) |
| 571 | { |
Feng Tang | 30c6c6b | 2012-02-06 17:24:44 +0800 | [diff] [blame] | 572 | unsigned int msr = ioread8(priv->membase + UART_MSR); |
| 573 | priv->dmsr = msr & PCH_UART_MSR_DELTA; |
| 574 | return (u8)msr; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 575 | } |
| 576 | |
Tomoya MORINAGA | 1822076 | 2011-02-23 10:03:14 +0900 | [diff] [blame] | 577 | static void pch_uart_hal_write(struct eg20t_port *priv, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 578 | const unsigned char *buf, int tx_size) |
| 579 | { |
| 580 | int i; |
| 581 | unsigned int thr; |
| 582 | |
| 583 | for (i = 0; i < tx_size;) { |
| 584 | thr = buf[i++]; |
| 585 | iowrite8(thr, priv->membase + PCH_UART_THR); |
| 586 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 587 | } |
| 588 | |
| 589 | static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf, |
| 590 | int rx_size) |
| 591 | { |
| 592 | int i; |
| 593 | u8 rbr, lsr; |
Liang Li | 1f9db09 | 2013-01-19 17:52:11 +0800 | [diff] [blame] | 594 | struct uart_port *port = &priv->port; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 595 | |
| 596 | lsr = ioread8(priv->membase + UART_LSR); |
| 597 | for (i = 0, lsr = ioread8(priv->membase + UART_LSR); |
Liang Li | 1f9db09 | 2013-01-19 17:52:11 +0800 | [diff] [blame] | 598 | i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 599 | lsr = ioread8(priv->membase + UART_LSR)) { |
| 600 | rbr = ioread8(priv->membase + PCH_UART_RBR); |
Liang Li | 1f9db09 | 2013-01-19 17:52:11 +0800 | [diff] [blame] | 601 | |
| 602 | if (lsr & UART_LSR_BI) { |
| 603 | port->icount.brk++; |
| 604 | if (uart_handle_break(port)) |
| 605 | continue; |
| 606 | } |
Liang Li | e8c5b56 | 2013-01-24 12:31:27 +0800 | [diff] [blame] | 607 | #ifdef SUPPORT_SYSRQ |
Liang Li | 1f9db09 | 2013-01-19 17:52:11 +0800 | [diff] [blame] | 608 | if (port->sysrq) { |
| 609 | if (uart_handle_sysrq_char(port, rbr)) |
| 610 | continue; |
| 611 | } |
Liang Li | e8c5b56 | 2013-01-24 12:31:27 +0800 | [diff] [blame] | 612 | #endif |
Liang Li | 1f9db09 | 2013-01-19 17:52:11 +0800 | [diff] [blame] | 613 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 614 | buf[i++] = rbr; |
| 615 | } |
| 616 | return i; |
| 617 | } |
| 618 | |
Tomoya MORINAGA | 2a58364 | 2012-03-26 14:43:01 +0900 | [diff] [blame] | 619 | static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv) |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 620 | { |
Tomoya MORINAGA | 2a58364 | 2012-03-26 14:43:01 +0900 | [diff] [blame] | 621 | return ioread8(priv->membase + UART_IIR) &\ |
| 622 | (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 623 | } |
| 624 | |
| 625 | static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) |
| 626 | { |
| 627 | return ioread8(priv->membase + UART_LSR); |
| 628 | } |
| 629 | |
| 630 | static void pch_uart_hal_set_break(struct eg20t_port *priv, int on) |
| 631 | { |
| 632 | unsigned int lcr; |
| 633 | |
| 634 | lcr = ioread8(priv->membase + UART_LCR); |
| 635 | if (on) |
| 636 | lcr |= PCH_UART_LCR_SB; |
| 637 | else |
| 638 | lcr &= ~PCH_UART_LCR_SB; |
| 639 | |
| 640 | iowrite8(lcr, priv->membase + UART_LCR); |
| 641 | } |
| 642 | |
| 643 | static int push_rx(struct eg20t_port *priv, const unsigned char *buf, |
| 644 | int size) |
| 645 | { |
Jiri Slaby | 05c7cd3 | 2013-01-03 15:53:04 +0100 | [diff] [blame] | 646 | struct uart_port *port = &priv->port; |
| 647 | struct tty_port *tport = &port->state->port; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 648 | |
Jiri Slaby | 05c7cd3 | 2013-01-03 15:53:04 +0100 | [diff] [blame] | 649 | tty_insert_flip_string(tport, buf, size); |
Jiri Slaby | 2e124b4 | 2013-01-03 15:53:06 +0100 | [diff] [blame] | 650 | tty_flip_buffer_push(tport); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 651 | |
| 652 | return 0; |
| 653 | } |
| 654 | |
| 655 | static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf) |
| 656 | { |
Feng Tang | 30c6c6b | 2012-02-06 17:24:44 +0800 | [diff] [blame] | 657 | int ret = 0; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 658 | struct uart_port *port = &priv->port; |
| 659 | |
| 660 | if (port->x_char) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 661 | dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n", |
| 662 | __func__, port->x_char, jiffies); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 663 | buf[0] = port->x_char; |
| 664 | port->x_char = 0; |
| 665 | ret = 1; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 666 | } |
| 667 | |
| 668 | return ret; |
| 669 | } |
| 670 | |
| 671 | static int dma_push_rx(struct eg20t_port *priv, int size) |
| 672 | { |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 673 | int room; |
| 674 | struct uart_port *port = &priv->port; |
Jiri Slaby | 227434f | 2013-01-03 15:53:01 +0100 | [diff] [blame] | 675 | struct tty_port *tport = &port->state->port; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 676 | |
Jiri Slaby | 227434f | 2013-01-03 15:53:01 +0100 | [diff] [blame] | 677 | room = tty_buffer_request_room(tport, size); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 678 | |
| 679 | if (room < size) |
| 680 | dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", |
| 681 | size - room); |
| 682 | if (!room) |
Johan Hovold | 0b53861 | 2013-09-10 12:50:51 +0200 | [diff] [blame] | 683 | return 0; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 684 | |
Jiri Slaby | 05c7cd3 | 2013-01-03 15:53:04 +0100 | [diff] [blame] | 685 | tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 686 | |
| 687 | port->icount.rx += room; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 688 | |
| 689 | return room; |
| 690 | } |
| 691 | |
| 692 | static void pch_free_dma(struct uart_port *port) |
| 693 | { |
| 694 | struct eg20t_port *priv; |
| 695 | priv = container_of(port, struct eg20t_port, port); |
| 696 | |
| 697 | if (priv->chan_tx) { |
| 698 | dma_release_channel(priv->chan_tx); |
| 699 | priv->chan_tx = NULL; |
| 700 | } |
| 701 | if (priv->chan_rx) { |
| 702 | dma_release_channel(priv->chan_rx); |
| 703 | priv->chan_rx = NULL; |
| 704 | } |
Tomoya MORINAGA | ef4f9d4 | 2012-03-26 14:43:06 +0900 | [diff] [blame] | 705 | |
| 706 | if (priv->rx_buf_dma) { |
| 707 | dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt, |
| 708 | priv->rx_buf_dma); |
| 709 | priv->rx_buf_virt = NULL; |
| 710 | priv->rx_buf_dma = 0; |
| 711 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 712 | |
| 713 | return; |
| 714 | } |
| 715 | |
| 716 | static bool filter(struct dma_chan *chan, void *slave) |
| 717 | { |
| 718 | struct pch_dma_slave *param = slave; |
| 719 | |
| 720 | if ((chan->chan_id == param->chan_id) && (param->dma_dev == |
| 721 | chan->device->dev)) { |
| 722 | chan->private = param; |
| 723 | return true; |
| 724 | } else { |
| 725 | return false; |
| 726 | } |
| 727 | } |
| 728 | |
| 729 | static void pch_request_dma(struct uart_port *port) |
| 730 | { |
| 731 | dma_cap_mask_t mask; |
| 732 | struct dma_chan *chan; |
| 733 | struct pci_dev *dma_dev; |
| 734 | struct pch_dma_slave *param; |
| 735 | struct eg20t_port *priv = |
| 736 | container_of(port, struct eg20t_port, port); |
| 737 | dma_cap_zero(mask); |
| 738 | dma_cap_set(DMA_SLAVE, mask); |
| 739 | |
Andy Shevchenko | 8368d6a | 2014-07-30 18:59:52 +0300 | [diff] [blame] | 740 | /* Get DMA's dev information */ |
| 741 | dma_dev = pci_get_slot(priv->pdev->bus, |
| 742 | PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0)); |
| 743 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 744 | /* Set Tx DMA */ |
| 745 | param = &priv->param_tx; |
| 746 | param->dma_dev = &dma_dev->dev; |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 747 | param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */ |
| 748 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 749 | param->tx_reg = port->mapbase + UART_TX; |
| 750 | chan = dma_request_channel(mask, filter, param); |
| 751 | if (!chan) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 752 | dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", |
| 753 | __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 754 | return; |
| 755 | } |
| 756 | priv->chan_tx = chan; |
| 757 | |
| 758 | /* Set Rx DMA */ |
| 759 | param = &priv->param_rx; |
| 760 | param->dma_dev = &dma_dev->dev; |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 761 | param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */ |
| 762 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 763 | param->rx_reg = port->mapbase + UART_RX; |
| 764 | chan = dma_request_channel(mask, filter, param); |
| 765 | if (!chan) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 766 | dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", |
| 767 | __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 768 | dma_release_channel(priv->chan_tx); |
Tomoya MORINAGA | 90f04c2 | 2011-11-11 10:55:27 +0900 | [diff] [blame] | 769 | priv->chan_tx = NULL; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 770 | return; |
| 771 | } |
| 772 | |
| 773 | /* Get Consistent memory for DMA */ |
| 774 | priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, |
| 775 | &priv->rx_buf_dma, GFP_KERNEL); |
| 776 | priv->chan_rx = chan; |
| 777 | } |
| 778 | |
| 779 | static void pch_dma_rx_complete(void *arg) |
| 780 | { |
| 781 | struct eg20t_port *priv = arg; |
| 782 | struct uart_port *port = &priv->port; |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 783 | int count; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 784 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 785 | dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); |
| 786 | count = dma_push_rx(priv, priv->trigger_level); |
| 787 | if (count) |
Jiri Slaby | 2e124b4 | 2013-01-03 15:53:06 +0100 | [diff] [blame] | 788 | tty_flip_buffer_push(&port->state->port); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 789 | async_tx_ack(priv->desc_rx); |
Tomoya MORINAGA | ae213f3 | 2012-07-06 17:19:42 +0900 | [diff] [blame] | 790 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | |
| 791 | PCH_UART_HAL_RX_ERR_INT); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 792 | } |
| 793 | |
| 794 | static void pch_dma_tx_complete(void *arg) |
| 795 | { |
| 796 | struct eg20t_port *priv = arg; |
| 797 | struct uart_port *port = &priv->port; |
| 798 | struct circ_buf *xmit = &port->state->xmit; |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 799 | struct scatterlist *sg = priv->sg_tx_p; |
| 800 | int i; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 801 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 802 | for (i = 0; i < priv->nent; i++, sg++) { |
| 803 | xmit->tail += sg_dma_len(sg); |
| 804 | port->icount.tx += sg_dma_len(sg); |
| 805 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 806 | xmit->tail &= UART_XMIT_SIZE - 1; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 807 | async_tx_ack(priv->desc_tx); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 808 | dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 809 | priv->tx_dma_use = 0; |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 810 | priv->nent = 0; |
| 811 | kfree(priv->sg_tx_p); |
Tomoya MORINAGA | 60d1031 | 2011-02-23 10:03:18 +0900 | [diff] [blame] | 812 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 813 | } |
| 814 | |
Tomoya MORINAGA | 1822076 | 2011-02-23 10:03:14 +0900 | [diff] [blame] | 815 | static int pop_tx(struct eg20t_port *priv, int size) |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 816 | { |
| 817 | int count = 0; |
| 818 | struct uart_port *port = &priv->port; |
| 819 | struct circ_buf *xmit = &port->state->xmit; |
| 820 | |
| 821 | if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size) |
| 822 | goto pop_tx_end; |
| 823 | |
| 824 | do { |
| 825 | int cnt_to_end = |
| 826 | CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); |
| 827 | int sz = min(size - count, cnt_to_end); |
Tomoya MORINAGA | 1822076 | 2011-02-23 10:03:14 +0900 | [diff] [blame] | 828 | pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 829 | xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1); |
| 830 | count += sz; |
| 831 | } while (!uart_circ_empty(xmit) && count < size); |
| 832 | |
| 833 | pop_tx_end: |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 834 | dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n", |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 835 | count, size - count, jiffies); |
| 836 | |
| 837 | return count; |
| 838 | } |
| 839 | |
| 840 | static int handle_rx_to(struct eg20t_port *priv) |
| 841 | { |
| 842 | struct pch_uart_buffer *buf; |
| 843 | int rx_size; |
| 844 | int ret; |
| 845 | if (!priv->start_rx) { |
Tomoya MORINAGA | ae213f3 | 2012-07-06 17:19:42 +0900 | [diff] [blame] | 846 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | |
| 847 | PCH_UART_HAL_RX_ERR_INT); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 848 | return 0; |
| 849 | } |
| 850 | buf = &priv->rxbuf; |
| 851 | do { |
| 852 | rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); |
| 853 | ret = push_rx(priv, buf->buf, rx_size); |
| 854 | if (ret) |
| 855 | return 0; |
| 856 | } while (rx_size == buf->size); |
| 857 | |
| 858 | return PCH_UART_HANDLED_RX_INT; |
| 859 | } |
| 860 | |
| 861 | static int handle_rx(struct eg20t_port *priv) |
| 862 | { |
| 863 | return handle_rx_to(priv); |
| 864 | } |
| 865 | |
| 866 | static int dma_handle_rx(struct eg20t_port *priv) |
| 867 | { |
| 868 | struct uart_port *port = &priv->port; |
| 869 | struct dma_async_tx_descriptor *desc; |
| 870 | struct scatterlist *sg; |
| 871 | |
| 872 | priv = container_of(port, struct eg20t_port, port); |
| 873 | sg = &priv->sg_rx; |
| 874 | |
| 875 | sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ |
| 876 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 877 | sg_dma_len(sg) = priv->trigger_level; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 878 | |
| 879 | sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 880 | sg_dma_len(sg), (unsigned long)priv->rx_buf_virt & |
| 881 | ~PAGE_MASK); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 882 | |
| 883 | sg_dma_address(sg) = priv->rx_buf_dma; |
| 884 | |
Alexandre Bounine | 1605282 | 2012-03-08 16:11:18 -0500 | [diff] [blame] | 885 | desc = dmaengine_prep_slave_sg(priv->chan_rx, |
Vinod Koul | a485df4 | 2011-10-14 10:47:38 +0530 | [diff] [blame] | 886 | sg, 1, DMA_DEV_TO_MEM, |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 887 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
| 888 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 889 | if (!desc) |
| 890 | return 0; |
| 891 | |
| 892 | priv->desc_rx = desc; |
| 893 | desc->callback = pch_dma_rx_complete; |
| 894 | desc->callback_param = priv; |
| 895 | desc->tx_submit(desc); |
| 896 | dma_async_issue_pending(priv->chan_rx); |
| 897 | |
| 898 | return PCH_UART_HANDLED_RX_INT; |
| 899 | } |
| 900 | |
| 901 | static unsigned int handle_tx(struct eg20t_port *priv) |
| 902 | { |
| 903 | struct uart_port *port = &priv->port; |
| 904 | struct circ_buf *xmit = &port->state->xmit; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 905 | int fifo_size; |
| 906 | int tx_size; |
| 907 | int size; |
| 908 | int tx_empty; |
| 909 | |
| 910 | if (!priv->start_tx) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 911 | dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", |
| 912 | __func__, jiffies); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 913 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
| 914 | priv->tx_empty = 1; |
| 915 | return 0; |
| 916 | } |
| 917 | |
| 918 | fifo_size = max(priv->fifo_size, 1); |
| 919 | tx_empty = 1; |
| 920 | if (pop_tx_x(priv, xmit->buf)) { |
| 921 | pch_uart_hal_write(priv, xmit->buf, 1); |
| 922 | port->icount.tx++; |
| 923 | tx_empty = 0; |
| 924 | fifo_size--; |
| 925 | } |
| 926 | size = min(xmit->head - xmit->tail, fifo_size); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 927 | if (size < 0) |
| 928 | size = fifo_size; |
| 929 | |
Tomoya MORINAGA | 1822076 | 2011-02-23 10:03:14 +0900 | [diff] [blame] | 930 | tx_size = pop_tx(priv, size); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 931 | if (tx_size > 0) { |
Tomoya MORINAGA | 1822076 | 2011-02-23 10:03:14 +0900 | [diff] [blame] | 932 | port->icount.tx += tx_size; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 933 | tx_empty = 0; |
| 934 | } |
| 935 | |
| 936 | priv->tx_empty = tx_empty; |
| 937 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 938 | if (tx_empty) { |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 939 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 940 | uart_write_wakeup(port); |
| 941 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 942 | |
| 943 | return PCH_UART_HANDLED_TX_INT; |
| 944 | } |
| 945 | |
| 946 | static unsigned int dma_handle_tx(struct eg20t_port *priv) |
| 947 | { |
| 948 | struct uart_port *port = &priv->port; |
| 949 | struct circ_buf *xmit = &port->state->xmit; |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 950 | struct scatterlist *sg; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 951 | int nent; |
| 952 | int fifo_size; |
| 953 | int tx_empty; |
| 954 | struct dma_async_tx_descriptor *desc; |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 955 | int num; |
| 956 | int i; |
| 957 | int bytes; |
| 958 | int size; |
| 959 | int rem; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 960 | |
| 961 | if (!priv->start_tx) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 962 | dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", |
| 963 | __func__, jiffies); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 964 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
| 965 | priv->tx_empty = 1; |
| 966 | return 0; |
| 967 | } |
| 968 | |
Tomoya MORINAGA | 60d1031 | 2011-02-23 10:03:18 +0900 | [diff] [blame] | 969 | if (priv->tx_dma_use) { |
| 970 | dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n", |
| 971 | __func__, jiffies); |
| 972 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
| 973 | priv->tx_empty = 1; |
| 974 | return 0; |
| 975 | } |
| 976 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 977 | fifo_size = max(priv->fifo_size, 1); |
| 978 | tx_empty = 1; |
| 979 | if (pop_tx_x(priv, xmit->buf)) { |
| 980 | pch_uart_hal_write(priv, xmit->buf, 1); |
| 981 | port->icount.tx++; |
| 982 | tx_empty = 0; |
| 983 | fifo_size--; |
| 984 | } |
| 985 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 986 | bytes = min((int)CIRC_CNT(xmit->head, xmit->tail, |
| 987 | UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head, |
| 988 | xmit->tail, UART_XMIT_SIZE)); |
| 989 | if (!bytes) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 990 | dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 991 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
| 992 | uart_write_wakeup(port); |
| 993 | return 0; |
| 994 | } |
| 995 | |
| 996 | if (bytes > fifo_size) { |
| 997 | num = bytes / fifo_size + 1; |
| 998 | size = fifo_size; |
| 999 | rem = bytes % fifo_size; |
| 1000 | } else { |
| 1001 | num = 1; |
| 1002 | size = bytes; |
| 1003 | rem = bytes; |
| 1004 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1005 | |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1006 | dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", |
| 1007 | __func__, num, size, rem); |
| 1008 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1009 | priv->tx_dma_use = 1; |
| 1010 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1011 | priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); |
Fengguang Wu | a92098a | 2012-07-28 20:43:57 +0800 | [diff] [blame] | 1012 | if (!priv->sg_tx_p) { |
| 1013 | dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__); |
| 1014 | return 0; |
| 1015 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1016 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1017 | sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ |
| 1018 | sg = priv->sg_tx_p; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1019 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1020 | for (i = 0; i < num; i++, sg++) { |
| 1021 | if (i == (num - 1)) |
| 1022 | sg_set_page(sg, virt_to_page(xmit->buf), |
| 1023 | rem, fifo_size * i); |
| 1024 | else |
| 1025 | sg_set_page(sg, virt_to_page(xmit->buf), |
| 1026 | size, fifo_size * i); |
| 1027 | } |
| 1028 | |
| 1029 | sg = priv->sg_tx_p; |
| 1030 | nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1031 | if (!nent) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1032 | dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1033 | return 0; |
| 1034 | } |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1035 | priv->nent = nent; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1036 | |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1037 | for (i = 0; i < nent; i++, sg++) { |
| 1038 | sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) + |
| 1039 | fifo_size * i; |
| 1040 | sg_dma_address(sg) = (sg_dma_address(sg) & |
| 1041 | ~(UART_XMIT_SIZE - 1)) + sg->offset; |
| 1042 | if (i == (nent - 1)) |
| 1043 | sg_dma_len(sg) = rem; |
| 1044 | else |
| 1045 | sg_dma_len(sg) = size; |
| 1046 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1047 | |
Alexandre Bounine | 1605282 | 2012-03-08 16:11:18 -0500 | [diff] [blame] | 1048 | desc = dmaengine_prep_slave_sg(priv->chan_tx, |
Vinod Koul | a485df4 | 2011-10-14 10:47:38 +0530 | [diff] [blame] | 1049 | priv->sg_tx_p, nent, DMA_MEM_TO_DEV, |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1050 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1051 | if (!desc) { |
Geert Uytterhoeven | 493671a | 2014-07-11 18:13:26 +0200 | [diff] [blame] | 1052 | dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n", |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1053 | __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1054 | return 0; |
| 1055 | } |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1056 | dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1057 | priv->desc_tx = desc; |
| 1058 | desc->callback = pch_dma_tx_complete; |
| 1059 | desc->callback_param = priv; |
| 1060 | |
| 1061 | desc->tx_submit(desc); |
| 1062 | |
| 1063 | dma_async_issue_pending(priv->chan_tx); |
| 1064 | |
| 1065 | return PCH_UART_HANDLED_TX_INT; |
| 1066 | } |
| 1067 | |
| 1068 | static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr) |
| 1069 | { |
Liang Li | 384e301 | 2013-01-19 17:52:10 +0800 | [diff] [blame] | 1070 | struct uart_port *port = &priv->port; |
| 1071 | struct tty_struct *tty = tty_port_tty_get(&port->state->port); |
| 1072 | char *error_msg[5] = {}; |
| 1073 | int i = 0; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1074 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1075 | if (lsr & PCH_UART_LSR_ERR) |
Liang Li | 384e301 | 2013-01-19 17:52:10 +0800 | [diff] [blame] | 1076 | error_msg[i++] = "Error data in FIFO\n"; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1077 | |
Liang Li | 384e301 | 2013-01-19 17:52:10 +0800 | [diff] [blame] | 1078 | if (lsr & UART_LSR_FE) { |
| 1079 | port->icount.frame++; |
| 1080 | error_msg[i++] = " Framing Error\n"; |
| 1081 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1082 | |
Liang Li | 384e301 | 2013-01-19 17:52:10 +0800 | [diff] [blame] | 1083 | if (lsr & UART_LSR_PE) { |
| 1084 | port->icount.parity++; |
| 1085 | error_msg[i++] = " Parity Error\n"; |
| 1086 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1087 | |
Liang Li | 384e301 | 2013-01-19 17:52:10 +0800 | [diff] [blame] | 1088 | if (lsr & UART_LSR_OE) { |
| 1089 | port->icount.overrun++; |
| 1090 | error_msg[i++] = " Overrun Error\n"; |
| 1091 | } |
| 1092 | |
| 1093 | if (tty == NULL) { |
| 1094 | for (i = 0; error_msg[i] != NULL; i++) |
| 1095 | dev_err(&priv->pdev->dev, error_msg[i]); |
Johan Hovold | fc0919c | 2013-09-10 12:50:49 +0200 | [diff] [blame] | 1096 | } else { |
| 1097 | tty_kref_put(tty); |
Liang Li | 384e301 | 2013-01-19 17:52:10 +0800 | [diff] [blame] | 1098 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1099 | } |
| 1100 | |
| 1101 | static irqreturn_t pch_uart_interrupt(int irq, void *dev_id) |
| 1102 | { |
| 1103 | struct eg20t_port *priv = dev_id; |
| 1104 | unsigned int handled; |
| 1105 | u8 lsr; |
| 1106 | int ret = 0; |
Tomoya MORINAGA | 2a58364 | 2012-03-26 14:43:01 +0900 | [diff] [blame] | 1107 | unsigned char iid; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1108 | unsigned long flags; |
Tomoya MORINAGA | 5181fb3 | 2012-03-26 14:43:03 +0900 | [diff] [blame] | 1109 | int next = 1; |
| 1110 | u8 msr; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1111 | |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1112 | spin_lock_irqsave(&priv->lock, flags); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1113 | handled = 0; |
Tomoya MORINAGA | 5181fb3 | 2012-03-26 14:43:03 +0900 | [diff] [blame] | 1114 | while (next) { |
| 1115 | iid = pch_uart_hal_get_iid(priv); |
| 1116 | if (iid & PCH_UART_IIR_IP) /* No Interrupt */ |
| 1117 | break; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1118 | switch (iid) { |
| 1119 | case PCH_UART_IID_RLS: /* Receiver Line Status */ |
| 1120 | lsr = pch_uart_hal_get_line_status(priv); |
| 1121 | if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE | |
| 1122 | UART_LSR_PE | UART_LSR_OE)) { |
| 1123 | pch_uart_err_ir(priv, lsr); |
| 1124 | ret = PCH_UART_HANDLED_RX_ERR_INT; |
Tomoya MORINAGA | 04e2c2e | 2012-03-26 14:43:05 +0900 | [diff] [blame] | 1125 | } else { |
| 1126 | ret = PCH_UART_HANDLED_LS_INT; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1127 | } |
| 1128 | break; |
| 1129 | case PCH_UART_IID_RDR: /* Received Data Ready */ |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1130 | if (priv->use_dma) { |
| 1131 | pch_uart_hal_disable_interrupt(priv, |
Tomoya MORINAGA | ae213f3 | 2012-07-06 17:19:42 +0900 | [diff] [blame] | 1132 | PCH_UART_HAL_RX_INT | |
| 1133 | PCH_UART_HAL_RX_ERR_INT); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1134 | ret = dma_handle_rx(priv); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1135 | if (!ret) |
| 1136 | pch_uart_hal_enable_interrupt(priv, |
Tomoya MORINAGA | ae213f3 | 2012-07-06 17:19:42 +0900 | [diff] [blame] | 1137 | PCH_UART_HAL_RX_INT | |
| 1138 | PCH_UART_HAL_RX_ERR_INT); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1139 | } else { |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1140 | ret = handle_rx(priv); |
Tomoya MORINAGA | da3564e | 2011-02-23 10:03:12 +0900 | [diff] [blame] | 1141 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1142 | break; |
| 1143 | case PCH_UART_IID_RDR_TO: /* Received Data Ready |
| 1144 | (FIFO Timeout) */ |
| 1145 | ret = handle_rx_to(priv); |
| 1146 | break; |
| 1147 | case PCH_UART_IID_THRE: /* Transmitter Holding Register |
| 1148 | Empty */ |
| 1149 | if (priv->use_dma) |
| 1150 | ret = dma_handle_tx(priv); |
| 1151 | else |
| 1152 | ret = handle_tx(priv); |
| 1153 | break; |
| 1154 | case PCH_UART_IID_MS: /* Modem Status */ |
Tomoya MORINAGA | 5181fb3 | 2012-03-26 14:43:03 +0900 | [diff] [blame] | 1155 | msr = pch_uart_hal_get_modem(priv); |
| 1156 | next = 0; /* MS ir prioirty is the lowest. So, MS ir |
| 1157 | means final interrupt */ |
| 1158 | if ((msr & UART_MSR_ANY_DELTA) == 0) |
| 1159 | break; |
| 1160 | ret |= PCH_UART_HANDLED_MS_INT; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1161 | break; |
| 1162 | default: /* Never junp to this label */ |
Tomoya MORINAGA | b23954a3 | 2012-03-26 14:43:02 +0900 | [diff] [blame] | 1163 | dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__, |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1164 | iid, jiffies); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1165 | ret = -1; |
Tomoya MORINAGA | 5181fb3 | 2012-03-26 14:43:03 +0900 | [diff] [blame] | 1166 | next = 0; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1167 | break; |
| 1168 | } |
| 1169 | handled |= (unsigned int)ret; |
| 1170 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1171 | |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1172 | spin_unlock_irqrestore(&priv->lock, flags); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1173 | return IRQ_RETVAL(handled); |
| 1174 | } |
| 1175 | |
| 1176 | /* This function tests whether the transmitter fifo and shifter for the port |
| 1177 | described by 'port' is empty. */ |
| 1178 | static unsigned int pch_uart_tx_empty(struct uart_port *port) |
| 1179 | { |
| 1180 | struct eg20t_port *priv; |
Feng Tang | 30c6c6b | 2012-02-06 17:24:44 +0800 | [diff] [blame] | 1181 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1182 | priv = container_of(port, struct eg20t_port, port); |
| 1183 | if (priv->tx_empty) |
Feng Tang | 30c6c6b | 2012-02-06 17:24:44 +0800 | [diff] [blame] | 1184 | return TIOCSER_TEMT; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1185 | else |
Feng Tang | 30c6c6b | 2012-02-06 17:24:44 +0800 | [diff] [blame] | 1186 | return 0; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1187 | } |
| 1188 | |
| 1189 | /* Returns the current state of modem control inputs. */ |
| 1190 | static unsigned int pch_uart_get_mctrl(struct uart_port *port) |
| 1191 | { |
| 1192 | struct eg20t_port *priv; |
| 1193 | u8 modem; |
| 1194 | unsigned int ret = 0; |
| 1195 | |
| 1196 | priv = container_of(port, struct eg20t_port, port); |
| 1197 | modem = pch_uart_hal_get_modem(priv); |
| 1198 | |
| 1199 | if (modem & UART_MSR_DCD) |
| 1200 | ret |= TIOCM_CAR; |
| 1201 | |
| 1202 | if (modem & UART_MSR_RI) |
| 1203 | ret |= TIOCM_RNG; |
| 1204 | |
| 1205 | if (modem & UART_MSR_DSR) |
| 1206 | ret |= TIOCM_DSR; |
| 1207 | |
| 1208 | if (modem & UART_MSR_CTS) |
| 1209 | ret |= TIOCM_CTS; |
| 1210 | |
| 1211 | return ret; |
| 1212 | } |
| 1213 | |
| 1214 | static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
| 1215 | { |
| 1216 | u32 mcr = 0; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1217 | struct eg20t_port *priv = container_of(port, struct eg20t_port, port); |
| 1218 | |
| 1219 | if (mctrl & TIOCM_DTR) |
| 1220 | mcr |= UART_MCR_DTR; |
| 1221 | if (mctrl & TIOCM_RTS) |
| 1222 | mcr |= UART_MCR_RTS; |
| 1223 | if (mctrl & TIOCM_LOOP) |
| 1224 | mcr |= UART_MCR_LOOP; |
| 1225 | |
Tomoya MORINAGA | 9af7155 | 2011-02-23 10:03:17 +0900 | [diff] [blame] | 1226 | if (priv->mcr & UART_MCR_AFE) |
| 1227 | mcr |= UART_MCR_AFE; |
| 1228 | |
| 1229 | if (mctrl) |
| 1230 | iowrite8(mcr, priv->membase + UART_MCR); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1231 | } |
| 1232 | |
| 1233 | static void pch_uart_stop_tx(struct uart_port *port) |
| 1234 | { |
| 1235 | struct eg20t_port *priv; |
| 1236 | priv = container_of(port, struct eg20t_port, port); |
| 1237 | priv->start_tx = 0; |
| 1238 | priv->tx_dma_use = 0; |
| 1239 | } |
| 1240 | |
| 1241 | static void pch_uart_start_tx(struct uart_port *port) |
| 1242 | { |
| 1243 | struct eg20t_port *priv; |
| 1244 | |
| 1245 | priv = container_of(port, struct eg20t_port, port); |
| 1246 | |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1247 | if (priv->use_dma) { |
| 1248 | if (priv->tx_dma_use) { |
| 1249 | dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", |
| 1250 | __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1251 | return; |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1252 | } |
| 1253 | } |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1254 | |
| 1255 | priv->start_tx = 1; |
| 1256 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); |
| 1257 | } |
| 1258 | |
| 1259 | static void pch_uart_stop_rx(struct uart_port *port) |
| 1260 | { |
| 1261 | struct eg20t_port *priv; |
| 1262 | priv = container_of(port, struct eg20t_port, port); |
| 1263 | priv->start_rx = 0; |
Tomoya MORINAGA | ae213f3 | 2012-07-06 17:19:42 +0900 | [diff] [blame] | 1264 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | |
| 1265 | PCH_UART_HAL_RX_ERR_INT); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1266 | } |
| 1267 | |
| 1268 | /* Enable the modem status interrupts. */ |
| 1269 | static void pch_uart_enable_ms(struct uart_port *port) |
| 1270 | { |
| 1271 | struct eg20t_port *priv; |
| 1272 | priv = container_of(port, struct eg20t_port, port); |
| 1273 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT); |
| 1274 | } |
| 1275 | |
| 1276 | /* Control the transmission of a break signal. */ |
| 1277 | static void pch_uart_break_ctl(struct uart_port *port, int ctl) |
| 1278 | { |
| 1279 | struct eg20t_port *priv; |
| 1280 | unsigned long flags; |
| 1281 | |
| 1282 | priv = container_of(port, struct eg20t_port, port); |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1283 | spin_lock_irqsave(&priv->lock, flags); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1284 | pch_uart_hal_set_break(priv, ctl); |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1285 | spin_unlock_irqrestore(&priv->lock, flags); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1286 | } |
| 1287 | |
| 1288 | /* Grab any interrupt resources and initialise any low level driver state. */ |
| 1289 | static int pch_uart_startup(struct uart_port *port) |
| 1290 | { |
| 1291 | struct eg20t_port *priv; |
| 1292 | int ret; |
| 1293 | int fifo_size; |
| 1294 | int trigger_level; |
| 1295 | |
| 1296 | priv = container_of(port, struct eg20t_port, port); |
| 1297 | priv->tx_empty = 1; |
Tomoya MORINAGA | aac6c0b | 2011-02-23 10:03:16 +0900 | [diff] [blame] | 1298 | |
| 1299 | if (port->uartclk) |
Darren Hart | a8a3ec9 | 2012-03-09 09:51:48 -0800 | [diff] [blame] | 1300 | priv->uartclk = port->uartclk; |
Tomoya MORINAGA | aac6c0b | 2011-02-23 10:03:16 +0900 | [diff] [blame] | 1301 | else |
Darren Hart | a8a3ec9 | 2012-03-09 09:51:48 -0800 | [diff] [blame] | 1302 | port->uartclk = priv->uartclk; |
Tomoya MORINAGA | aac6c0b | 2011-02-23 10:03:16 +0900 | [diff] [blame] | 1303 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1304 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); |
| 1305 | ret = pch_uart_hal_set_line(priv, default_baud, |
| 1306 | PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT, |
| 1307 | PCH_UART_HAL_STB1); |
| 1308 | if (ret) |
| 1309 | return ret; |
| 1310 | |
| 1311 | switch (priv->fifo_size) { |
| 1312 | case 256: |
| 1313 | fifo_size = PCH_UART_HAL_FIFO256; |
| 1314 | break; |
| 1315 | case 64: |
| 1316 | fifo_size = PCH_UART_HAL_FIFO64; |
| 1317 | break; |
| 1318 | case 16: |
| 1319 | fifo_size = PCH_UART_HAL_FIFO16; |
Alan Cox | 669bd45 | 2012-07-02 18:51:38 +0100 | [diff] [blame] | 1320 | break; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1321 | case 1: |
| 1322 | default: |
| 1323 | fifo_size = PCH_UART_HAL_FIFO_DIS; |
| 1324 | break; |
| 1325 | } |
| 1326 | |
| 1327 | switch (priv->trigger) { |
| 1328 | case PCH_UART_HAL_TRIGGER1: |
| 1329 | trigger_level = 1; |
| 1330 | break; |
| 1331 | case PCH_UART_HAL_TRIGGER_L: |
| 1332 | trigger_level = priv->fifo_size / 4; |
| 1333 | break; |
| 1334 | case PCH_UART_HAL_TRIGGER_M: |
| 1335 | trigger_level = priv->fifo_size / 2; |
| 1336 | break; |
| 1337 | case PCH_UART_HAL_TRIGGER_H: |
| 1338 | default: |
| 1339 | trigger_level = priv->fifo_size - (priv->fifo_size / 8); |
| 1340 | break; |
| 1341 | } |
| 1342 | |
| 1343 | priv->trigger_level = trigger_level; |
| 1344 | ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, |
| 1345 | fifo_size, priv->trigger); |
| 1346 | if (ret < 0) |
| 1347 | return ret; |
| 1348 | |
| 1349 | ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, |
Alexander Stein | 50d16ca | 2014-03-25 14:05:08 +0100 | [diff] [blame] | 1350 | priv->irq_name, priv); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1351 | if (ret < 0) |
| 1352 | return ret; |
| 1353 | |
| 1354 | if (priv->use_dma) |
| 1355 | pch_request_dma(port); |
| 1356 | |
| 1357 | priv->start_rx = 1; |
Tomoya MORINAGA | ae213f3 | 2012-07-06 17:19:42 +0900 | [diff] [blame] | 1358 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | |
| 1359 | PCH_UART_HAL_RX_ERR_INT); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1360 | uart_update_timeout(port, CS8, default_baud); |
| 1361 | |
| 1362 | return 0; |
| 1363 | } |
| 1364 | |
| 1365 | static void pch_uart_shutdown(struct uart_port *port) |
| 1366 | { |
| 1367 | struct eg20t_port *priv; |
| 1368 | int ret; |
| 1369 | |
| 1370 | priv = container_of(port, struct eg20t_port, port); |
| 1371 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); |
| 1372 | pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO); |
| 1373 | ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, |
| 1374 | PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1); |
| 1375 | if (ret) |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1376 | dev_err(priv->port.dev, |
| 1377 | "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1378 | |
Tomoya MORINAGA | 90f04c2 | 2011-11-11 10:55:27 +0900 | [diff] [blame] | 1379 | pch_free_dma(port); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1380 | |
| 1381 | free_irq(priv->port.irq, priv); |
| 1382 | } |
| 1383 | |
| 1384 | /* Change the port parameters, including word length, parity, stop |
| 1385 | *bits. Update read_status_mask and ignore_status_mask to indicate |
| 1386 | *the types of events we are interested in receiving. */ |
| 1387 | static void pch_uart_set_termios(struct uart_port *port, |
| 1388 | struct ktermios *termios, struct ktermios *old) |
| 1389 | { |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1390 | int rtn; |
Darren Hart | e26439c | 2013-07-29 15:15:07 -0700 | [diff] [blame] | 1391 | unsigned int baud, parity, bits, stb; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1392 | struct eg20t_port *priv; |
| 1393 | unsigned long flags; |
| 1394 | |
| 1395 | priv = container_of(port, struct eg20t_port, port); |
| 1396 | switch (termios->c_cflag & CSIZE) { |
| 1397 | case CS5: |
| 1398 | bits = PCH_UART_HAL_5BIT; |
| 1399 | break; |
| 1400 | case CS6: |
| 1401 | bits = PCH_UART_HAL_6BIT; |
| 1402 | break; |
| 1403 | case CS7: |
| 1404 | bits = PCH_UART_HAL_7BIT; |
| 1405 | break; |
| 1406 | default: /* CS8 */ |
| 1407 | bits = PCH_UART_HAL_8BIT; |
| 1408 | break; |
| 1409 | } |
| 1410 | if (termios->c_cflag & CSTOPB) |
| 1411 | stb = PCH_UART_HAL_STB2; |
| 1412 | else |
| 1413 | stb = PCH_UART_HAL_STB1; |
| 1414 | |
| 1415 | if (termios->c_cflag & PARENB) { |
Tomoya MORINAGA | 2fc39ae | 2012-07-06 17:19:43 +0900 | [diff] [blame] | 1416 | if (termios->c_cflag & PARODD) |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1417 | parity = PCH_UART_HAL_PARITY_ODD; |
| 1418 | else |
| 1419 | parity = PCH_UART_HAL_PARITY_EVEN; |
| 1420 | |
Feng Tang | 30c6c6b | 2012-02-06 17:24:44 +0800 | [diff] [blame] | 1421 | } else |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1422 | parity = PCH_UART_HAL_PARITY_NONE; |
Tomoya MORINAGA | 9af7155 | 2011-02-23 10:03:17 +0900 | [diff] [blame] | 1423 | |
| 1424 | /* Only UART0 has auto hardware flow function */ |
| 1425 | if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) |
| 1426 | priv->mcr |= UART_MCR_AFE; |
| 1427 | else |
| 1428 | priv->mcr &= ~UART_MCR_AFE; |
| 1429 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1430 | termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ |
| 1431 | |
| 1432 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); |
| 1433 | |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1434 | spin_lock_irqsave(&priv->lock, flags); |
| 1435 | spin_lock(&port->lock); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1436 | |
| 1437 | uart_update_timeout(port, termios->c_cflag, baud); |
| 1438 | rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); |
| 1439 | if (rtn) |
| 1440 | goto out; |
| 1441 | |
Tomoya MORINAGA | a1d7cfe | 2011-10-27 15:45:18 +0900 | [diff] [blame] | 1442 | pch_uart_set_mctrl(&priv->port, priv->port.mctrl); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1443 | /* Don't rewrite B0 */ |
| 1444 | if (tty_termios_baud_rate(termios)) |
| 1445 | tty_termios_encode_baud_rate(termios, baud, baud); |
| 1446 | |
| 1447 | out: |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1448 | spin_unlock(&port->lock); |
| 1449 | spin_unlock_irqrestore(&priv->lock, flags); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1450 | } |
| 1451 | |
| 1452 | static const char *pch_uart_type(struct uart_port *port) |
| 1453 | { |
| 1454 | return KBUILD_MODNAME; |
| 1455 | } |
| 1456 | |
| 1457 | static void pch_uart_release_port(struct uart_port *port) |
| 1458 | { |
| 1459 | struct eg20t_port *priv; |
| 1460 | |
| 1461 | priv = container_of(port, struct eg20t_port, port); |
| 1462 | pci_iounmap(priv->pdev, priv->membase); |
| 1463 | pci_release_regions(priv->pdev); |
| 1464 | } |
| 1465 | |
| 1466 | static int pch_uart_request_port(struct uart_port *port) |
| 1467 | { |
| 1468 | struct eg20t_port *priv; |
| 1469 | int ret; |
| 1470 | void __iomem *membase; |
| 1471 | |
| 1472 | priv = container_of(port, struct eg20t_port, port); |
| 1473 | ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); |
| 1474 | if (ret < 0) |
| 1475 | return -EBUSY; |
| 1476 | |
| 1477 | membase = pci_iomap(priv->pdev, 1, 0); |
| 1478 | if (!membase) { |
| 1479 | pci_release_regions(priv->pdev); |
| 1480 | return -EBUSY; |
| 1481 | } |
| 1482 | priv->membase = port->membase = membase; |
| 1483 | |
| 1484 | return 0; |
| 1485 | } |
| 1486 | |
| 1487 | static void pch_uart_config_port(struct uart_port *port, int type) |
| 1488 | { |
| 1489 | struct eg20t_port *priv; |
| 1490 | |
| 1491 | priv = container_of(port, struct eg20t_port, port); |
| 1492 | if (type & UART_CONFIG_TYPE) { |
| 1493 | port->type = priv->port_type; |
| 1494 | pch_uart_request_port(port); |
| 1495 | } |
| 1496 | } |
| 1497 | |
| 1498 | static int pch_uart_verify_port(struct uart_port *port, |
| 1499 | struct serial_struct *serinfo) |
| 1500 | { |
| 1501 | struct eg20t_port *priv; |
| 1502 | |
| 1503 | priv = container_of(port, struct eg20t_port, port); |
| 1504 | if (serinfo->flags & UPF_LOW_LATENCY) { |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1505 | dev_info(priv->port.dev, |
| 1506 | "PCH UART : Use PIO Mode (without DMA)\n"); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1507 | priv->use_dma = 0; |
| 1508 | serinfo->flags &= ~UPF_LOW_LATENCY; |
| 1509 | } else { |
| 1510 | #ifndef CONFIG_PCH_DMA |
Tomoya MORINAGA | 23877fd | 2011-02-23 10:03:15 +0900 | [diff] [blame] | 1511 | dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", |
| 1512 | __func__); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1513 | return -EOPNOTSUPP; |
| 1514 | #endif |
Sebastian Andrzej Siewior | e41c098 | 2013-12-04 20:52:49 +0100 | [diff] [blame] | 1515 | if (!priv->use_dma) { |
Tomoya MORINAGA | af6d17c | 2012-04-12 10:47:50 +0900 | [diff] [blame] | 1516 | pch_request_dma(port); |
Sebastian Andrzej Siewior | e41c098 | 2013-12-04 20:52:49 +0100 | [diff] [blame] | 1517 | if (priv->chan_rx) |
| 1518 | priv->use_dma = 1; |
| 1519 | } |
| 1520 | dev_info(priv->port.dev, "PCH UART: %s\n", |
| 1521 | priv->use_dma ? |
| 1522 | "Use DMA Mode" : "No DMA"); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1523 | } |
| 1524 | |
| 1525 | return 0; |
| 1526 | } |
| 1527 | |
Luis Henriques | 09a5163 | 2013-08-14 23:18:37 +0100 | [diff] [blame] | 1528 | #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE) |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1529 | /* |
| 1530 | * Wait for transmitter & holding register to empty |
| 1531 | */ |
| 1532 | static void wait_for_xmitr(struct eg20t_port *up, int bits) |
| 1533 | { |
| 1534 | unsigned int status, tmout = 10000; |
| 1535 | |
| 1536 | /* Wait up to 10ms for the character(s) to be sent. */ |
| 1537 | for (;;) { |
| 1538 | status = ioread8(up->membase + UART_LSR); |
| 1539 | |
| 1540 | if ((status & bits) == bits) |
| 1541 | break; |
| 1542 | if (--tmout == 0) |
| 1543 | break; |
| 1544 | udelay(1); |
| 1545 | } |
| 1546 | |
| 1547 | /* Wait up to 1s for flow control if necessary */ |
| 1548 | if (up->port.flags & UPF_CONS_FLOW) { |
| 1549 | unsigned int tmout; |
| 1550 | for (tmout = 1000000; tmout; tmout--) { |
| 1551 | unsigned int msr = ioread8(up->membase + UART_MSR); |
| 1552 | if (msr & UART_MSR_CTS) |
| 1553 | break; |
| 1554 | udelay(1); |
| 1555 | touch_nmi_watchdog(); |
| 1556 | } |
| 1557 | } |
| 1558 | } |
Luis Henriques | 09a5163 | 2013-08-14 23:18:37 +0100 | [diff] [blame] | 1559 | #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */ |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1560 | |
Liang Li | ef44d28 | 2013-03-05 22:30:38 +0800 | [diff] [blame] | 1561 | #ifdef CONFIG_CONSOLE_POLL |
| 1562 | /* |
| 1563 | * Console polling routines for communicate via uart while |
| 1564 | * in an interrupt or debug context. |
| 1565 | */ |
| 1566 | static int pch_uart_get_poll_char(struct uart_port *port) |
| 1567 | { |
| 1568 | struct eg20t_port *priv = |
| 1569 | container_of(port, struct eg20t_port, port); |
| 1570 | u8 lsr = ioread8(priv->membase + UART_LSR); |
| 1571 | |
| 1572 | if (!(lsr & UART_LSR_DR)) |
| 1573 | return NO_POLL_CHAR; |
| 1574 | |
| 1575 | return ioread8(priv->membase + PCH_UART_RBR); |
| 1576 | } |
| 1577 | |
| 1578 | |
| 1579 | static void pch_uart_put_poll_char(struct uart_port *port, |
| 1580 | unsigned char c) |
| 1581 | { |
| 1582 | unsigned int ier; |
| 1583 | struct eg20t_port *priv = |
| 1584 | container_of(port, struct eg20t_port, port); |
| 1585 | |
| 1586 | /* |
| 1587 | * First save the IER then disable the interrupts |
| 1588 | */ |
| 1589 | ier = ioread8(priv->membase + UART_IER); |
| 1590 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); |
| 1591 | |
| 1592 | wait_for_xmitr(priv, UART_LSR_THRE); |
| 1593 | /* |
| 1594 | * Send the character out. |
Liang Li | ef44d28 | 2013-03-05 22:30:38 +0800 | [diff] [blame] | 1595 | */ |
| 1596 | iowrite8(c, priv->membase + PCH_UART_THR); |
Liang Li | ef44d28 | 2013-03-05 22:30:38 +0800 | [diff] [blame] | 1597 | |
| 1598 | /* |
| 1599 | * Finally, wait for transmitter to become empty |
| 1600 | * and restore the IER |
| 1601 | */ |
| 1602 | wait_for_xmitr(priv, BOTH_EMPTY); |
| 1603 | iowrite8(ier, priv->membase + UART_IER); |
| 1604 | } |
| 1605 | #endif /* CONFIG_CONSOLE_POLL */ |
| 1606 | |
| 1607 | static struct uart_ops pch_uart_ops = { |
| 1608 | .tx_empty = pch_uart_tx_empty, |
| 1609 | .set_mctrl = pch_uart_set_mctrl, |
| 1610 | .get_mctrl = pch_uart_get_mctrl, |
| 1611 | .stop_tx = pch_uart_stop_tx, |
| 1612 | .start_tx = pch_uart_start_tx, |
| 1613 | .stop_rx = pch_uart_stop_rx, |
| 1614 | .enable_ms = pch_uart_enable_ms, |
| 1615 | .break_ctl = pch_uart_break_ctl, |
| 1616 | .startup = pch_uart_startup, |
| 1617 | .shutdown = pch_uart_shutdown, |
| 1618 | .set_termios = pch_uart_set_termios, |
| 1619 | /* .pm = pch_uart_pm, Not supported yet */ |
Liang Li | ef44d28 | 2013-03-05 22:30:38 +0800 | [diff] [blame] | 1620 | .type = pch_uart_type, |
| 1621 | .release_port = pch_uart_release_port, |
| 1622 | .request_port = pch_uart_request_port, |
| 1623 | .config_port = pch_uart_config_port, |
| 1624 | .verify_port = pch_uart_verify_port, |
| 1625 | #ifdef CONFIG_CONSOLE_POLL |
| 1626 | .poll_get_char = pch_uart_get_poll_char, |
| 1627 | .poll_put_char = pch_uart_put_poll_char, |
| 1628 | #endif |
| 1629 | }; |
| 1630 | |
| 1631 | #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE |
| 1632 | |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1633 | static void pch_console_putchar(struct uart_port *port, int ch) |
| 1634 | { |
| 1635 | struct eg20t_port *priv = |
| 1636 | container_of(port, struct eg20t_port, port); |
| 1637 | |
| 1638 | wait_for_xmitr(priv, UART_LSR_THRE); |
| 1639 | iowrite8(ch, priv->membase + PCH_UART_THR); |
| 1640 | } |
| 1641 | |
| 1642 | /* |
| 1643 | * Print a string to the serial port trying not to disturb |
| 1644 | * any possible real use of the port... |
| 1645 | * |
| 1646 | * The console_lock must be held when we get here. |
| 1647 | */ |
| 1648 | static void |
| 1649 | pch_console_write(struct console *co, const char *s, unsigned int count) |
| 1650 | { |
| 1651 | struct eg20t_port *priv; |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1652 | unsigned long flags; |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1653 | int priv_locked = 1; |
| 1654 | int port_locked = 1; |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1655 | u8 ier; |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1656 | |
| 1657 | priv = pch_uart_ports[co->index]; |
| 1658 | |
| 1659 | touch_nmi_watchdog(); |
| 1660 | |
| 1661 | local_irq_save(flags); |
| 1662 | if (priv->port.sysrq) { |
Liang Li | 1f9db09 | 2013-01-19 17:52:11 +0800 | [diff] [blame] | 1663 | /* call to uart_handle_sysrq_char already took the priv lock */ |
| 1664 | priv_locked = 0; |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1665 | /* serial8250_handle_port() already took the port lock */ |
| 1666 | port_locked = 0; |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1667 | } else if (oops_in_progress) { |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1668 | priv_locked = spin_trylock(&priv->lock); |
| 1669 | port_locked = spin_trylock(&priv->port.lock); |
| 1670 | } else { |
| 1671 | spin_lock(&priv->lock); |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1672 | spin_lock(&priv->port.lock); |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1673 | } |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1674 | |
| 1675 | /* |
| 1676 | * First save the IER then disable the interrupts |
| 1677 | */ |
| 1678 | ier = ioread8(priv->membase + UART_IER); |
| 1679 | |
| 1680 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); |
| 1681 | |
| 1682 | uart_console_write(&priv->port, s, count, pch_console_putchar); |
| 1683 | |
| 1684 | /* |
| 1685 | * Finally, wait for transmitter to become empty |
| 1686 | * and restore the IER |
| 1687 | */ |
| 1688 | wait_for_xmitr(priv, BOTH_EMPTY); |
| 1689 | iowrite8(ier, priv->membase + UART_IER); |
| 1690 | |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1691 | if (port_locked) |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1692 | spin_unlock(&priv->port.lock); |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1693 | if (priv_locked) |
| 1694 | spin_unlock(&priv->lock); |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1695 | local_irq_restore(flags); |
| 1696 | } |
| 1697 | |
| 1698 | static int __init pch_console_setup(struct console *co, char *options) |
| 1699 | { |
| 1700 | struct uart_port *port; |
Darren Hart | 7ce9251 | 2012-03-09 09:51:51 -0800 | [diff] [blame] | 1701 | int baud = default_baud; |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1702 | int bits = 8; |
| 1703 | int parity = 'n'; |
| 1704 | int flow = 'n'; |
| 1705 | |
| 1706 | /* |
| 1707 | * Check whether an invalid uart number has been specified, and |
| 1708 | * if so, search for the first available port that does have |
| 1709 | * console support. |
| 1710 | */ |
| 1711 | if (co->index >= PCH_UART_NR) |
| 1712 | co->index = 0; |
| 1713 | port = &pch_uart_ports[co->index]->port; |
| 1714 | |
| 1715 | if (!port || (!port->iobase && !port->membase)) |
| 1716 | return -ENODEV; |
| 1717 | |
Darren Hart | 077175f | 2012-03-09 09:51:49 -0800 | [diff] [blame] | 1718 | port->uartclk = pch_uart_get_uartclk(); |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1719 | |
| 1720 | if (options) |
| 1721 | uart_parse_options(options, &baud, &parity, &bits, &flow); |
| 1722 | |
| 1723 | return uart_set_options(port, co, baud, parity, bits, flow); |
| 1724 | } |
| 1725 | |
| 1726 | static struct uart_driver pch_uart_driver; |
| 1727 | |
| 1728 | static struct console pch_console = { |
| 1729 | .name = PCH_UART_DRIVER_DEVICE, |
| 1730 | .write = pch_console_write, |
| 1731 | .device = uart_console_device, |
| 1732 | .setup = pch_console_setup, |
| 1733 | .flags = CON_PRINTBUFFER | CON_ANYTIME, |
| 1734 | .index = -1, |
| 1735 | .data = &pch_uart_driver, |
| 1736 | }; |
| 1737 | |
| 1738 | #define PCH_CONSOLE (&pch_console) |
| 1739 | #else |
| 1740 | #define PCH_CONSOLE NULL |
Liang Li | ef44d28 | 2013-03-05 22:30:38 +0800 | [diff] [blame] | 1741 | #endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */ |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1742 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1743 | static struct uart_driver pch_uart_driver = { |
| 1744 | .owner = THIS_MODULE, |
| 1745 | .driver_name = KBUILD_MODNAME, |
| 1746 | .dev_name = PCH_UART_DRIVER_DEVICE, |
| 1747 | .major = 0, |
| 1748 | .minor = 0, |
| 1749 | .nr = PCH_UART_NR, |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1750 | .cons = PCH_CONSOLE, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1751 | }; |
| 1752 | |
| 1753 | static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1754 | const struct pci_device_id *id) |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1755 | { |
| 1756 | struct eg20t_port *priv; |
| 1757 | int ret; |
| 1758 | unsigned int iobase; |
| 1759 | unsigned int mapbase; |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 1760 | unsigned char *rxbuf; |
Darren Hart | 077175f | 2012-03-09 09:51:49 -0800 | [diff] [blame] | 1761 | int fifosize; |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1762 | int port_type; |
| 1763 | struct pch_uart_driver_data *board; |
Jingoo Han | 6ec0656 | 2014-02-05 09:58:02 +0900 | [diff] [blame] | 1764 | #ifdef CONFIG_DEBUG_FS |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 1765 | char name[32]; /* for debugfs file name */ |
Jingoo Han | 6ec0656 | 2014-02-05 09:58:02 +0900 | [diff] [blame] | 1766 | #endif |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1767 | |
| 1768 | board = &drv_dat[id->driver_data]; |
| 1769 | port_type = board->port_type; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1770 | |
| 1771 | priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL); |
| 1772 | if (priv == NULL) |
| 1773 | goto init_port_alloc_err; |
| 1774 | |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 1775 | rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1776 | if (!rxbuf) |
| 1777 | goto init_port_free_txbuf; |
| 1778 | |
| 1779 | switch (port_type) { |
| 1780 | case PORT_UNKNOWN: |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1781 | fifosize = 256; /* EG20T/ML7213: UART0 */ |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1782 | break; |
| 1783 | case PORT_8250: |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1784 | fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1785 | break; |
| 1786 | default: |
| 1787 | dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); |
| 1788 | goto init_port_hal_free; |
| 1789 | } |
| 1790 | |
Alexander Stein | e463595 | 2011-07-04 08:58:31 +0200 | [diff] [blame] | 1791 | pci_enable_msi(pdev); |
Tomoya MORINAGA | 867c902 | 2012-04-02 14:36:22 +0900 | [diff] [blame] | 1792 | pci_set_master(pdev); |
Alexander Stein | e463595 | 2011-07-04 08:58:31 +0200 | [diff] [blame] | 1793 | |
Darren Hart | fe89def | 2012-06-19 14:00:18 -0700 | [diff] [blame] | 1794 | spin_lock_init(&priv->lock); |
| 1795 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1796 | iobase = pci_resource_start(pdev, 0); |
| 1797 | mapbase = pci_resource_start(pdev, 1); |
| 1798 | priv->mapbase = mapbase; |
| 1799 | priv->iobase = iobase; |
| 1800 | priv->pdev = pdev; |
| 1801 | priv->tx_empty = 1; |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 1802 | priv->rxbuf.buf = rxbuf; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1803 | priv->rxbuf.size = PAGE_SIZE; |
| 1804 | |
| 1805 | priv->fifo_size = fifosize; |
Darren Hart | 077175f | 2012-03-09 09:51:49 -0800 | [diff] [blame] | 1806 | priv->uartclk = pch_uart_get_uartclk(); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1807 | priv->port_type = PORT_MAX_8250 + port_type + 1; |
| 1808 | priv->port.dev = &pdev->dev; |
| 1809 | priv->port.iobase = iobase; |
| 1810 | priv->port.membase = NULL; |
| 1811 | priv->port.mapbase = mapbase; |
| 1812 | priv->port.irq = pdev->irq; |
| 1813 | priv->port.iotype = UPIO_PORT; |
| 1814 | priv->port.ops = &pch_uart_ops; |
| 1815 | priv->port.flags = UPF_BOOT_AUTOCONF; |
| 1816 | priv->port.fifosize = fifosize; |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1817 | priv->port.line = board->line_no; |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1818 | priv->trigger = PCH_UART_HAL_TRIGGER_M; |
| 1819 | |
Alexander Stein | 50d16ca | 2014-03-25 14:05:08 +0100 | [diff] [blame] | 1820 | snprintf(priv->irq_name, IRQ_NAME_SIZE, |
| 1821 | KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d", |
| 1822 | priv->port.line); |
| 1823 | |
Tomoya MORINAGA | 7e46132 | 2011-02-23 10:03:13 +0900 | [diff] [blame] | 1824 | spin_lock_init(&priv->port.lock); |
| 1825 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1826 | pci_set_drvdata(pdev, priv); |
Feng Tang | 6f56d0f | 2012-02-06 17:24:45 +0800 | [diff] [blame] | 1827 | priv->trigger_level = 1; |
| 1828 | priv->fcr = 0; |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1829 | |
Zubair Lutfullah Kakakhel | 7789e5a | 2016-08-12 12:48:54 +0100 | [diff] [blame^] | 1830 | if (pdev->dev.of_node) |
| 1831 | of_property_read_u32(pdev->dev.of_node, "clock-frequency" |
| 1832 | , &user_uartclk); |
| 1833 | |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1834 | #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE |
| 1835 | pch_uart_ports[board->line_no] = priv; |
| 1836 | #endif |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1837 | ret = uart_add_one_port(&pch_uart_driver, &priv->port); |
| 1838 | if (ret < 0) |
| 1839 | goto init_port_hal_free; |
| 1840 | |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 1841 | #ifdef CONFIG_DEBUG_FS |
| 1842 | snprintf(name, sizeof(name), "uart%d_regs", board->line_no); |
| 1843 | priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO, |
| 1844 | NULL, priv, &port_regs_ops); |
| 1845 | #endif |
| 1846 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1847 | return priv; |
| 1848 | |
| 1849 | init_port_hal_free: |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1850 | #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE |
| 1851 | pch_uart_ports[board->line_no] = NULL; |
| 1852 | #endif |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 1853 | free_page((unsigned long)rxbuf); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1854 | init_port_free_txbuf: |
| 1855 | kfree(priv); |
| 1856 | init_port_alloc_err: |
| 1857 | |
| 1858 | return NULL; |
| 1859 | } |
| 1860 | |
| 1861 | static void pch_uart_exit_port(struct eg20t_port *priv) |
| 1862 | { |
Feng Tang | d011411 | 2012-02-06 17:24:43 +0800 | [diff] [blame] | 1863 | |
| 1864 | #ifdef CONFIG_DEBUG_FS |
| 1865 | if (priv->debugfs) |
| 1866 | debugfs_remove(priv->debugfs); |
| 1867 | #endif |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1868 | uart_remove_one_port(&pch_uart_driver, &priv->port); |
Tomoya MORINAGA | 1c51899 | 2010-12-16 16:13:29 +0900 | [diff] [blame] | 1869 | free_page((unsigned long)priv->rxbuf.buf); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1870 | } |
| 1871 | |
| 1872 | static void pch_uart_pci_remove(struct pci_dev *pdev) |
| 1873 | { |
Feng Tang | 6f56d0f | 2012-02-06 17:24:45 +0800 | [diff] [blame] | 1874 | struct eg20t_port *priv = pci_get_drvdata(pdev); |
Alexander Stein | e463595 | 2011-07-04 08:58:31 +0200 | [diff] [blame] | 1875 | |
| 1876 | pci_disable_msi(pdev); |
Alexander Stein | e30f867 | 2011-11-15 15:04:07 -0800 | [diff] [blame] | 1877 | |
| 1878 | #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE |
| 1879 | pch_uart_ports[priv->port.line] = NULL; |
| 1880 | #endif |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1881 | pch_uart_exit_port(priv); |
| 1882 | pci_disable_device(pdev); |
| 1883 | kfree(priv); |
| 1884 | return; |
| 1885 | } |
| 1886 | #ifdef CONFIG_PM |
| 1887 | static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state) |
| 1888 | { |
| 1889 | struct eg20t_port *priv = pci_get_drvdata(pdev); |
| 1890 | |
| 1891 | uart_suspend_port(&pch_uart_driver, &priv->port); |
| 1892 | |
| 1893 | pci_save_state(pdev); |
| 1894 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
| 1895 | return 0; |
| 1896 | } |
| 1897 | |
| 1898 | static int pch_uart_pci_resume(struct pci_dev *pdev) |
| 1899 | { |
| 1900 | struct eg20t_port *priv = pci_get_drvdata(pdev); |
| 1901 | int ret; |
| 1902 | |
| 1903 | pci_set_power_state(pdev, PCI_D0); |
| 1904 | pci_restore_state(pdev); |
| 1905 | |
| 1906 | ret = pci_enable_device(pdev); |
| 1907 | if (ret) { |
| 1908 | dev_err(&pdev->dev, |
| 1909 | "%s-pci_enable_device failed(ret=%d) ", __func__, ret); |
| 1910 | return ret; |
| 1911 | } |
| 1912 | |
| 1913 | uart_resume_port(&pch_uart_driver, &priv->port); |
| 1914 | |
| 1915 | return 0; |
| 1916 | } |
| 1917 | #else |
| 1918 | #define pch_uart_pci_suspend NULL |
| 1919 | #define pch_uart_pci_resume NULL |
| 1920 | #endif |
| 1921 | |
Jingoo Han | 311df74 | 2013-12-03 08:26:37 +0900 | [diff] [blame] | 1922 | static const struct pci_device_id pch_uart_pci_id[] = { |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1923 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811), |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1924 | .driver_data = pch_et20t_uart0}, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1925 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812), |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1926 | .driver_data = pch_et20t_uart1}, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1927 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813), |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1928 | .driver_data = pch_et20t_uart2}, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1929 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814), |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1930 | .driver_data = pch_et20t_uart3}, |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1931 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027), |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1932 | .driver_data = pch_ml7213_uart0}, |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1933 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028), |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1934 | .driver_data = pch_ml7213_uart1}, |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1935 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029), |
Tomoya MORINAGA | fec38d1 | 2011-02-23 10:03:19 +0900 | [diff] [blame] | 1936 | .driver_data = pch_ml7213_uart2}, |
Tomoya MORINAGA | 177c2cb | 2011-05-09 17:25:20 +0900 | [diff] [blame] | 1937 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C), |
| 1938 | .driver_data = pch_ml7223_uart0}, |
| 1939 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D), |
| 1940 | .driver_data = pch_ml7223_uart1}, |
Tomoya MORINAGA | 8249f74 | 2011-10-28 09:38:49 +0900 | [diff] [blame] | 1941 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811), |
| 1942 | .driver_data = pch_ml7831_uart0}, |
| 1943 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812), |
| 1944 | .driver_data = pch_ml7831_uart1}, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1945 | {0,}, |
| 1946 | }; |
| 1947 | |
Bill Pemberton | 9671f09 | 2012-11-19 13:21:50 -0500 | [diff] [blame] | 1948 | static int pch_uart_pci_probe(struct pci_dev *pdev, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1949 | const struct pci_device_id *id) |
| 1950 | { |
| 1951 | int ret; |
| 1952 | struct eg20t_port *priv; |
| 1953 | |
| 1954 | ret = pci_enable_device(pdev); |
| 1955 | if (ret < 0) |
| 1956 | goto probe_error; |
| 1957 | |
Tomoya MORINAGA | 4564e1e | 2011-01-28 18:00:01 +0900 | [diff] [blame] | 1958 | priv = pch_uart_init_port(pdev, id); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1959 | if (!priv) { |
| 1960 | ret = -EBUSY; |
| 1961 | goto probe_disable_device; |
| 1962 | } |
| 1963 | pci_set_drvdata(pdev, priv); |
| 1964 | |
| 1965 | return ret; |
| 1966 | |
| 1967 | probe_disable_device: |
Alexander Stein | e463595 | 2011-07-04 08:58:31 +0200 | [diff] [blame] | 1968 | pci_disable_msi(pdev); |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1969 | pci_disable_device(pdev); |
| 1970 | probe_error: |
| 1971 | return ret; |
| 1972 | } |
| 1973 | |
| 1974 | static struct pci_driver pch_uart_pci_driver = { |
| 1975 | .name = "pch_uart", |
| 1976 | .id_table = pch_uart_pci_id, |
| 1977 | .probe = pch_uart_pci_probe, |
Bill Pemberton | 2d47b71 | 2012-11-19 13:21:34 -0500 | [diff] [blame] | 1978 | .remove = pch_uart_pci_remove, |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 1979 | .suspend = pch_uart_pci_suspend, |
| 1980 | .resume = pch_uart_pci_resume, |
| 1981 | }; |
| 1982 | |
| 1983 | static int __init pch_uart_module_init(void) |
| 1984 | { |
| 1985 | int ret; |
| 1986 | |
| 1987 | /* register as UART driver */ |
| 1988 | ret = uart_register_driver(&pch_uart_driver); |
| 1989 | if (ret < 0) |
| 1990 | return ret; |
| 1991 | |
| 1992 | /* register as PCI driver */ |
| 1993 | ret = pci_register_driver(&pch_uart_pci_driver); |
| 1994 | if (ret < 0) |
| 1995 | uart_unregister_driver(&pch_uart_driver); |
| 1996 | |
| 1997 | return ret; |
| 1998 | } |
| 1999 | module_init(pch_uart_module_init); |
| 2000 | |
| 2001 | static void __exit pch_uart_module_exit(void) |
| 2002 | { |
| 2003 | pci_unregister_driver(&pch_uart_pci_driver); |
| 2004 | uart_unregister_driver(&pch_uart_driver); |
| 2005 | } |
| 2006 | module_exit(pch_uart_module_exit); |
| 2007 | |
| 2008 | MODULE_LICENSE("GPL v2"); |
| 2009 | MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver"); |
Ben Hutchings | 52592da | 2013-09-01 19:26:37 +0100 | [diff] [blame] | 2010 | MODULE_DEVICE_TABLE(pci, pch_uart_pci_id); |
| 2011 | |
Tomoya MORINAGA | 3c6a483 | 2010-11-17 09:55:54 +0900 | [diff] [blame] | 2012 | module_param(default_baud, uint, S_IRUGO); |
Darren Hart | a46f553 | 2012-03-09 09:51:52 -0800 | [diff] [blame] | 2013 | MODULE_PARM_DESC(default_baud, |
| 2014 | "Default BAUD for initial driver state and console (default 9600)"); |
Darren Hart | 2a44feb | 2012-03-09 09:51:50 -0800 | [diff] [blame] | 2015 | module_param(user_uartclk, uint, S_IRUGO); |
Darren Hart | a46f553 | 2012-03-09 09:51:52 -0800 | [diff] [blame] | 2016 | MODULE_PARM_DESC(user_uartclk, |
| 2017 | "Override UART default or board specific UART clock"); |