Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1 | /* |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 2 | * Copyright © 2006-2014 Intel Corporation. |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, |
| 6 | * version 2, as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 11 | * more details. |
| 12 | * |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 13 | * Authors: David Woodhouse <dwmw2@infradead.org>, |
| 14 | * Ashok Raj <ashok.raj@intel.com>, |
| 15 | * Shaohua Li <shaohua.li@intel.com>, |
| 16 | * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>, |
| 17 | * Fenghua Yu <fenghua.yu@intel.com> |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/bitmap.h> |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 22 | #include <linux/debugfs.h> |
Paul Gortmaker | 54485c3 | 2011-10-29 10:26:25 -0400 | [diff] [blame] | 23 | #include <linux/export.h> |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 24 | #include <linux/slab.h> |
| 25 | #include <linux/irq.h> |
| 26 | #include <linux/interrupt.h> |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 27 | #include <linux/spinlock.h> |
| 28 | #include <linux/pci.h> |
| 29 | #include <linux/dmar.h> |
| 30 | #include <linux/dma-mapping.h> |
| 31 | #include <linux/mempool.h> |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 32 | #include <linux/memory.h> |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 33 | #include <linux/timer.h> |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 34 | #include <linux/iova.h> |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 35 | #include <linux/iommu.h> |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 36 | #include <linux/intel-iommu.h> |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 37 | #include <linux/syscore_ops.h> |
Shane Wang | 69575d3 | 2009-09-01 18:25:07 -0700 | [diff] [blame] | 38 | #include <linux/tboot.h> |
Stephen Rothwell | adb2fe0 | 2009-08-31 15:24:23 +1000 | [diff] [blame] | 39 | #include <linux/dmi.h> |
Joerg Roedel | 5cdede2 | 2011-04-04 15:55:18 +0200 | [diff] [blame] | 40 | #include <linux/pci-ats.h> |
Tejun Heo | 0ee332c | 2011-12-08 10:22:09 -0800 | [diff] [blame] | 41 | #include <linux/memblock.h> |
Akinobu Mita | 3674643 | 2014-06-04 16:06:51 -0700 | [diff] [blame] | 42 | #include <linux/dma-contiguous.h> |
Suresh Siddha | 8a8f422 | 2012-03-30 11:47:08 -0700 | [diff] [blame] | 43 | #include <asm/irq_remapping.h> |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 44 | #include <asm/cacheflush.h> |
FUJITA Tomonori | 46a7fa2 | 2008-07-11 10:23:42 +0900 | [diff] [blame] | 45 | #include <asm/iommu.h> |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 46 | |
Joerg Roedel | 078e1ee | 2012-09-26 12:44:43 +0200 | [diff] [blame] | 47 | #include "irq_remapping.h" |
| 48 | |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 49 | #define ROOT_SIZE VTD_PAGE_SIZE |
| 50 | #define CONTEXT_SIZE VTD_PAGE_SIZE |
| 51 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 52 | #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY) |
| 53 | #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA) |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 54 | #define IS_AZALIA(pdev) ((pdev)->vendor == 0x8086 && (pdev)->device == 0x3a3e) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 55 | |
| 56 | #define IOAPIC_RANGE_START (0xfee00000) |
| 57 | #define IOAPIC_RANGE_END (0xfeefffff) |
| 58 | #define IOVA_START_ADDR (0x1000) |
| 59 | |
| 60 | #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48 |
| 61 | |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 62 | #define MAX_AGAW_WIDTH 64 |
Jiang Liu | 5c645b3 | 2014-01-06 14:18:12 +0800 | [diff] [blame] | 63 | #define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT) |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 64 | |
David Woodhouse | 2ebe315 | 2009-09-19 07:34:04 -0700 | [diff] [blame] | 65 | #define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1) |
| 66 | #define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1) |
| 67 | |
| 68 | /* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR |
| 69 | to match. That way, we can use 'unsigned long' for PFNs with impunity. */ |
| 70 | #define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \ |
| 71 | __DOMAIN_MAX_PFN(gaw), (unsigned long)-1)) |
| 72 | #define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 73 | |
Mark McLoughlin | f27be03 | 2008-11-20 15:49:43 +0000 | [diff] [blame] | 74 | #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT) |
Yang Hongyang | 284901a | 2009-04-06 19:01:15 -0700 | [diff] [blame] | 75 | #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32)) |
Yang Hongyang | 6a35528 | 2009-04-06 19:01:13 -0700 | [diff] [blame] | 76 | #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64)) |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 77 | |
Andrew Morton | df08cdc | 2010-09-22 13:05:11 -0700 | [diff] [blame] | 78 | /* page table handling */ |
| 79 | #define LEVEL_STRIDE (9) |
| 80 | #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1) |
| 81 | |
Ohad Ben-Cohen | 6d1c56a | 2011-11-10 11:32:30 +0200 | [diff] [blame] | 82 | /* |
| 83 | * This bitmap is used to advertise the page sizes our hardware support |
| 84 | * to the IOMMU core, which will then use this information to split |
| 85 | * physically contiguous memory regions it is mapping into page sizes |
| 86 | * that we support. |
| 87 | * |
| 88 | * Traditionally the IOMMU core just handed us the mappings directly, |
| 89 | * after making sure the size is an order of a 4KiB page and that the |
| 90 | * mapping has natural alignment. |
| 91 | * |
| 92 | * To retain this behavior, we currently advertise that we support |
| 93 | * all page sizes that are an order of 4KiB. |
| 94 | * |
| 95 | * If at some point we'd like to utilize the IOMMU core's new behavior, |
| 96 | * we could change this to advertise the real page sizes we support. |
| 97 | */ |
| 98 | #define INTEL_IOMMU_PGSIZES (~0xFFFUL) |
| 99 | |
Andrew Morton | df08cdc | 2010-09-22 13:05:11 -0700 | [diff] [blame] | 100 | static inline int agaw_to_level(int agaw) |
| 101 | { |
| 102 | return agaw + 2; |
| 103 | } |
| 104 | |
| 105 | static inline int agaw_to_width(int agaw) |
| 106 | { |
Jiang Liu | 5c645b3 | 2014-01-06 14:18:12 +0800 | [diff] [blame] | 107 | return min_t(int, 30 + agaw * LEVEL_STRIDE, MAX_AGAW_WIDTH); |
Andrew Morton | df08cdc | 2010-09-22 13:05:11 -0700 | [diff] [blame] | 108 | } |
| 109 | |
| 110 | static inline int width_to_agaw(int width) |
| 111 | { |
Jiang Liu | 5c645b3 | 2014-01-06 14:18:12 +0800 | [diff] [blame] | 112 | return DIV_ROUND_UP(width - 30, LEVEL_STRIDE); |
Andrew Morton | df08cdc | 2010-09-22 13:05:11 -0700 | [diff] [blame] | 113 | } |
| 114 | |
| 115 | static inline unsigned int level_to_offset_bits(int level) |
| 116 | { |
| 117 | return (level - 1) * LEVEL_STRIDE; |
| 118 | } |
| 119 | |
| 120 | static inline int pfn_level_offset(unsigned long pfn, int level) |
| 121 | { |
| 122 | return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK; |
| 123 | } |
| 124 | |
| 125 | static inline unsigned long level_mask(int level) |
| 126 | { |
| 127 | return -1UL << level_to_offset_bits(level); |
| 128 | } |
| 129 | |
| 130 | static inline unsigned long level_size(int level) |
| 131 | { |
| 132 | return 1UL << level_to_offset_bits(level); |
| 133 | } |
| 134 | |
| 135 | static inline unsigned long align_to_level(unsigned long pfn, int level) |
| 136 | { |
| 137 | return (pfn + level_size(level) - 1) & level_mask(level); |
| 138 | } |
David Woodhouse | fd18de5 | 2009-05-10 23:57:41 +0100 | [diff] [blame] | 139 | |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 140 | static inline unsigned long lvl_to_nr_pages(unsigned int lvl) |
| 141 | { |
Jiang Liu | 5c645b3 | 2014-01-06 14:18:12 +0800 | [diff] [blame] | 142 | return 1 << min_t(int, (lvl - 1) * LEVEL_STRIDE, MAX_AGAW_PFN_WIDTH); |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 143 | } |
| 144 | |
David Woodhouse | dd4e831 | 2009-06-27 16:21:20 +0100 | [diff] [blame] | 145 | /* VT-d pages must always be _smaller_ than MM pages. Otherwise things |
| 146 | are never going to work. */ |
| 147 | static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn) |
| 148 | { |
| 149 | return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT); |
| 150 | } |
| 151 | |
| 152 | static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn) |
| 153 | { |
| 154 | return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT); |
| 155 | } |
| 156 | static inline unsigned long page_to_dma_pfn(struct page *pg) |
| 157 | { |
| 158 | return mm_to_dma_pfn(page_to_pfn(pg)); |
| 159 | } |
| 160 | static inline unsigned long virt_to_dma_pfn(void *p) |
| 161 | { |
| 162 | return page_to_dma_pfn(virt_to_page(p)); |
| 163 | } |
| 164 | |
Weidong Han | d9630fe | 2008-12-08 11:06:32 +0800 | [diff] [blame] | 165 | /* global iommu list, set NULL for ignored DMAR units */ |
| 166 | static struct intel_iommu **g_iommus; |
| 167 | |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 168 | static void __init check_tylersburg_isoch(void); |
David Woodhouse | 9af8814 | 2009-02-13 23:18:03 +0000 | [diff] [blame] | 169 | static int rwbf_quirk; |
| 170 | |
Mark McLoughlin | 46b08e1 | 2008-11-20 15:49:44 +0000 | [diff] [blame] | 171 | /* |
Joseph Cihula | b779260 | 2011-05-03 00:08:37 -0700 | [diff] [blame] | 172 | * set to 1 to panic kernel if can't successfully enable VT-d |
| 173 | * (used when kernel is launched w/ TXT) |
| 174 | */ |
| 175 | static int force_on = 0; |
| 176 | |
| 177 | /* |
Mark McLoughlin | 46b08e1 | 2008-11-20 15:49:44 +0000 | [diff] [blame] | 178 | * 0: Present |
| 179 | * 1-11: Reserved |
| 180 | * 12-63: Context Ptr (12 - (haw-1)) |
| 181 | * 64-127: Reserved |
| 182 | */ |
| 183 | struct root_entry { |
| 184 | u64 val; |
| 185 | u64 rsvd1; |
| 186 | }; |
| 187 | #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry)) |
| 188 | static inline bool root_present(struct root_entry *root) |
| 189 | { |
| 190 | return (root->val & 1); |
| 191 | } |
| 192 | static inline void set_root_present(struct root_entry *root) |
| 193 | { |
| 194 | root->val |= 1; |
| 195 | } |
| 196 | static inline void set_root_value(struct root_entry *root, unsigned long value) |
| 197 | { |
Li, Zhen-Hua | 1a2262f | 2014-11-05 15:30:19 +0800 | [diff] [blame] | 198 | root->val &= ~VTD_PAGE_MASK; |
Mark McLoughlin | 46b08e1 | 2008-11-20 15:49:44 +0000 | [diff] [blame] | 199 | root->val |= value & VTD_PAGE_MASK; |
| 200 | } |
| 201 | |
| 202 | static inline struct context_entry * |
| 203 | get_context_addr_from_root(struct root_entry *root) |
| 204 | { |
| 205 | return (struct context_entry *) |
| 206 | (root_present(root)?phys_to_virt( |
| 207 | root->val & VTD_PAGE_MASK) : |
| 208 | NULL); |
| 209 | } |
| 210 | |
Mark McLoughlin | 7a8fc25 | 2008-11-20 15:49:45 +0000 | [diff] [blame] | 211 | /* |
| 212 | * low 64 bits: |
| 213 | * 0: present |
| 214 | * 1: fault processing disable |
| 215 | * 2-3: translation type |
| 216 | * 12-63: address space root |
| 217 | * high 64 bits: |
| 218 | * 0-2: address width |
| 219 | * 3-6: aval |
| 220 | * 8-23: domain id |
| 221 | */ |
| 222 | struct context_entry { |
| 223 | u64 lo; |
| 224 | u64 hi; |
| 225 | }; |
Mark McLoughlin | 7a8fc25 | 2008-11-20 15:49:45 +0000 | [diff] [blame] | 226 | |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 227 | static inline bool context_present(struct context_entry *context) |
| 228 | { |
| 229 | return (context->lo & 1); |
| 230 | } |
| 231 | static inline void context_set_present(struct context_entry *context) |
| 232 | { |
| 233 | context->lo |= 1; |
| 234 | } |
| 235 | |
| 236 | static inline void context_set_fault_enable(struct context_entry *context) |
| 237 | { |
| 238 | context->lo &= (((u64)-1) << 2) | 1; |
| 239 | } |
| 240 | |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 241 | static inline void context_set_translation_type(struct context_entry *context, |
| 242 | unsigned long value) |
| 243 | { |
| 244 | context->lo &= (((u64)-1) << 4) | 3; |
| 245 | context->lo |= (value & 3) << 2; |
| 246 | } |
| 247 | |
| 248 | static inline void context_set_address_root(struct context_entry *context, |
| 249 | unsigned long value) |
| 250 | { |
Li, Zhen-Hua | 1a2262f | 2014-11-05 15:30:19 +0800 | [diff] [blame] | 251 | context->lo &= ~VTD_PAGE_MASK; |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 252 | context->lo |= value & VTD_PAGE_MASK; |
| 253 | } |
| 254 | |
| 255 | static inline void context_set_address_width(struct context_entry *context, |
| 256 | unsigned long value) |
| 257 | { |
| 258 | context->hi |= value & 7; |
| 259 | } |
| 260 | |
| 261 | static inline void context_set_domain_id(struct context_entry *context, |
| 262 | unsigned long value) |
| 263 | { |
| 264 | context->hi |= (value & ((1 << 16) - 1)) << 8; |
| 265 | } |
| 266 | |
| 267 | static inline void context_clear_entry(struct context_entry *context) |
| 268 | { |
| 269 | context->lo = 0; |
| 270 | context->hi = 0; |
| 271 | } |
Mark McLoughlin | 7a8fc25 | 2008-11-20 15:49:45 +0000 | [diff] [blame] | 272 | |
Mark McLoughlin | 622ba12 | 2008-11-20 15:49:46 +0000 | [diff] [blame] | 273 | /* |
| 274 | * 0: readable |
| 275 | * 1: writable |
| 276 | * 2-6: reserved |
| 277 | * 7: super page |
Sheng Yang | 9cf06697 | 2009-03-18 15:33:07 +0800 | [diff] [blame] | 278 | * 8-10: available |
| 279 | * 11: snoop behavior |
Mark McLoughlin | 622ba12 | 2008-11-20 15:49:46 +0000 | [diff] [blame] | 280 | * 12-63: Host physcial address |
| 281 | */ |
| 282 | struct dma_pte { |
| 283 | u64 val; |
| 284 | }; |
Mark McLoughlin | 622ba12 | 2008-11-20 15:49:46 +0000 | [diff] [blame] | 285 | |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 286 | static inline void dma_clear_pte(struct dma_pte *pte) |
| 287 | { |
| 288 | pte->val = 0; |
| 289 | } |
| 290 | |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 291 | static inline u64 dma_pte_addr(struct dma_pte *pte) |
| 292 | { |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 293 | #ifdef CONFIG_64BIT |
| 294 | return pte->val & VTD_PAGE_MASK; |
| 295 | #else |
| 296 | /* Must have a full atomic 64-bit read */ |
David Woodhouse | 1a8bd48 | 2010-08-10 01:38:53 +0100 | [diff] [blame] | 297 | return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK; |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 298 | #endif |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 299 | } |
| 300 | |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 301 | static inline bool dma_pte_present(struct dma_pte *pte) |
| 302 | { |
| 303 | return (pte->val & 3) != 0; |
| 304 | } |
Mark McLoughlin | 622ba12 | 2008-11-20 15:49:46 +0000 | [diff] [blame] | 305 | |
Allen Kay | 4399c8b | 2011-10-14 12:32:46 -0700 | [diff] [blame] | 306 | static inline bool dma_pte_superpage(struct dma_pte *pte) |
| 307 | { |
Joerg Roedel | c3c75eb | 2014-07-04 11:19:10 +0200 | [diff] [blame] | 308 | return (pte->val & DMA_PTE_LARGE_PAGE); |
Allen Kay | 4399c8b | 2011-10-14 12:32:46 -0700 | [diff] [blame] | 309 | } |
| 310 | |
David Woodhouse | 75e6bf9 | 2009-07-02 11:21:16 +0100 | [diff] [blame] | 311 | static inline int first_pte_in_page(struct dma_pte *pte) |
| 312 | { |
| 313 | return !((unsigned long)pte & ~VTD_PAGE_MASK); |
| 314 | } |
| 315 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 316 | /* |
| 317 | * This domain is a statically identity mapping domain. |
| 318 | * 1. This domain creats a static 1:1 mapping to all usable memory. |
| 319 | * 2. It maps to each iommu if successful. |
| 320 | * 3. Each iommu mapps to this domain if successful. |
| 321 | */ |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 322 | static struct dmar_domain *si_domain; |
| 323 | static int hw_pass_through = 1; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 324 | |
Weidong Han | 1ce28fe | 2008-12-08 16:35:39 +0800 | [diff] [blame] | 325 | /* domain represents a virtual machine, more than one devices |
| 326 | * across iommus may be owned in one domain, e.g. kvm guest. |
| 327 | */ |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 328 | #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 0) |
Weidong Han | 1ce28fe | 2008-12-08 16:35:39 +0800 | [diff] [blame] | 329 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 330 | /* si_domain contains mulitple devices */ |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 331 | #define DOMAIN_FLAG_STATIC_IDENTITY (1 << 1) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 332 | |
Mark McLoughlin | 99126f7 | 2008-11-20 15:49:47 +0000 | [diff] [blame] | 333 | struct dmar_domain { |
| 334 | int id; /* domain id */ |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 335 | int nid; /* node id */ |
Jiang Liu | 78d8e70 | 2014-11-09 22:47:57 +0800 | [diff] [blame^] | 336 | DECLARE_BITMAP(iommu_bmp, DMAR_UNITS_SUPPORTED); |
Mike Travis | 1b198bb | 2012-03-05 15:05:16 -0800 | [diff] [blame] | 337 | /* bitmap of iommus this domain uses*/ |
Mark McLoughlin | 99126f7 | 2008-11-20 15:49:47 +0000 | [diff] [blame] | 338 | |
| 339 | struct list_head devices; /* all devices' list */ |
| 340 | struct iova_domain iovad; /* iova's that belong to this domain */ |
| 341 | |
| 342 | struct dma_pte *pgd; /* virtual address */ |
Mark McLoughlin | 99126f7 | 2008-11-20 15:49:47 +0000 | [diff] [blame] | 343 | int gaw; /* max guest address width */ |
| 344 | |
| 345 | /* adjusted guest address width, 0 is level 2 30-bit */ |
| 346 | int agaw; |
| 347 | |
Weidong Han | 3b5410e | 2008-12-08 09:17:15 +0800 | [diff] [blame] | 348 | int flags; /* flags to find out type of domain */ |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 349 | |
| 350 | int iommu_coherency;/* indicate coherency of iommu access */ |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 351 | int iommu_snooping; /* indicate snooping control feature*/ |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 352 | int iommu_count; /* reference count of iommu */ |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 353 | int iommu_superpage;/* Level of superpages supported: |
| 354 | 0 == 4KiB (no superpages), 1 == 2MiB, |
| 355 | 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */ |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 356 | spinlock_t iommu_lock; /* protect iommu set in domain */ |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 357 | u64 max_addr; /* maximum mapped address */ |
Mark McLoughlin | 99126f7 | 2008-11-20 15:49:47 +0000 | [diff] [blame] | 358 | }; |
| 359 | |
Mark McLoughlin | a647dac | 2008-11-20 15:49:48 +0000 | [diff] [blame] | 360 | /* PCI domain-device relationship */ |
| 361 | struct device_domain_info { |
| 362 | struct list_head link; /* link to domain siblings */ |
| 363 | struct list_head global; /* link to global list */ |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 364 | u8 bus; /* PCI bus number */ |
Mark McLoughlin | a647dac | 2008-11-20 15:49:48 +0000 | [diff] [blame] | 365 | u8 devfn; /* PCI devfn number */ |
David Woodhouse | 0bcb3e2 | 2014-03-06 17:12:03 +0000 | [diff] [blame] | 366 | struct device *dev; /* it's NULL for PCIe-to-PCI bridge */ |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 367 | struct intel_iommu *iommu; /* IOMMU used by this device */ |
Mark McLoughlin | a647dac | 2008-11-20 15:49:48 +0000 | [diff] [blame] | 368 | struct dmar_domain *domain; /* pointer to domain */ |
| 369 | }; |
| 370 | |
Jiang Liu | b94e411 | 2014-02-19 14:07:25 +0800 | [diff] [blame] | 371 | struct dmar_rmrr_unit { |
| 372 | struct list_head list; /* list of rmrr units */ |
| 373 | struct acpi_dmar_header *hdr; /* ACPI header */ |
| 374 | u64 base_address; /* reserved base address*/ |
| 375 | u64 end_address; /* reserved end address */ |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 376 | struct dmar_dev_scope *devices; /* target devices */ |
Jiang Liu | b94e411 | 2014-02-19 14:07:25 +0800 | [diff] [blame] | 377 | int devices_cnt; /* target device count */ |
| 378 | }; |
| 379 | |
| 380 | struct dmar_atsr_unit { |
| 381 | struct list_head list; /* list of ATSR units */ |
| 382 | struct acpi_dmar_header *hdr; /* ACPI header */ |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 383 | struct dmar_dev_scope *devices; /* target devices */ |
Jiang Liu | b94e411 | 2014-02-19 14:07:25 +0800 | [diff] [blame] | 384 | int devices_cnt; /* target device count */ |
| 385 | u8 include_all:1; /* include all ports */ |
| 386 | }; |
| 387 | |
| 388 | static LIST_HEAD(dmar_atsr_units); |
| 389 | static LIST_HEAD(dmar_rmrr_units); |
| 390 | |
| 391 | #define for_each_rmrr_units(rmrr) \ |
| 392 | list_for_each_entry(rmrr, &dmar_rmrr_units, list) |
| 393 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 394 | static void flush_unmaps_timeout(unsigned long data); |
| 395 | |
Jiang Liu | b707cb0 | 2014-01-06 14:18:26 +0800 | [diff] [blame] | 396 | static DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 397 | |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 398 | #define HIGH_WATER_MARK 250 |
| 399 | struct deferred_flush_tables { |
| 400 | int next; |
| 401 | struct iova *iova[HIGH_WATER_MARK]; |
| 402 | struct dmar_domain *domain[HIGH_WATER_MARK]; |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 403 | struct page *freelist[HIGH_WATER_MARK]; |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 404 | }; |
| 405 | |
| 406 | static struct deferred_flush_tables *deferred_flush; |
| 407 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 408 | /* bitmap for indexing intel_iommus */ |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 409 | static int g_num_of_iommus; |
| 410 | |
| 411 | static DEFINE_SPINLOCK(async_umap_flush_lock); |
| 412 | static LIST_HEAD(unmaps_to_do); |
| 413 | |
| 414 | static int timer_on; |
| 415 | static long list_size; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 416 | |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 417 | static void domain_exit(struct dmar_domain *domain); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 418 | static void domain_remove_dev_info(struct dmar_domain *domain); |
Jiang Liu | b94e411 | 2014-02-19 14:07:25 +0800 | [diff] [blame] | 419 | static void domain_remove_one_dev_info(struct dmar_domain *domain, |
David Woodhouse | bf9c9ed | 2014-03-09 16:19:13 -0700 | [diff] [blame] | 420 | struct device *dev); |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 421 | static void iommu_detach_dependent_devices(struct intel_iommu *iommu, |
David Woodhouse | 0bcb3e2 | 2014-03-06 17:12:03 +0000 | [diff] [blame] | 422 | struct device *dev); |
Jiang Liu | 2a46ddf | 2014-07-11 14:19:30 +0800 | [diff] [blame] | 423 | static int domain_detach_iommu(struct dmar_domain *domain, |
| 424 | struct intel_iommu *iommu); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 425 | |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 426 | #ifdef CONFIG_INTEL_IOMMU_DEFAULT_ON |
Kyle McMartin | 0cd5c3c | 2009-02-04 14:29:19 -0800 | [diff] [blame] | 427 | int dmar_disabled = 0; |
| 428 | #else |
| 429 | int dmar_disabled = 1; |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 430 | #endif /*CONFIG_INTEL_IOMMU_DEFAULT_ON*/ |
Kyle McMartin | 0cd5c3c | 2009-02-04 14:29:19 -0800 | [diff] [blame] | 431 | |
Eugeni Dodonov | 8bc1f85 | 2011-11-23 16:42:14 -0200 | [diff] [blame] | 432 | int intel_iommu_enabled = 0; |
| 433 | EXPORT_SYMBOL_GPL(intel_iommu_enabled); |
| 434 | |
David Woodhouse | 2d9e667 | 2010-06-15 10:57:57 +0100 | [diff] [blame] | 435 | static int dmar_map_gfx = 1; |
Keshavamurthy, Anil S | 7d3b03c | 2007-10-21 16:41:53 -0700 | [diff] [blame] | 436 | static int dmar_forcedac; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 437 | static int intel_iommu_strict; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 438 | static int intel_iommu_superpage = 1; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 439 | |
David Woodhouse | c0771df | 2011-10-14 20:59:46 +0100 | [diff] [blame] | 440 | int intel_iommu_gfx_mapped; |
| 441 | EXPORT_SYMBOL_GPL(intel_iommu_gfx_mapped); |
| 442 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 443 | #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1)) |
| 444 | static DEFINE_SPINLOCK(device_domain_lock); |
| 445 | static LIST_HEAD(device_domain_list); |
| 446 | |
Thierry Reding | b22f643 | 2014-06-27 09:03:12 +0200 | [diff] [blame] | 447 | static const struct iommu_ops intel_iommu_ops; |
Joerg Roedel | a8bcbb0d | 2008-12-03 15:14:02 +0100 | [diff] [blame] | 448 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 449 | static int __init intel_iommu_setup(char *str) |
| 450 | { |
| 451 | if (!str) |
| 452 | return -EINVAL; |
| 453 | while (*str) { |
Kyle McMartin | 0cd5c3c | 2009-02-04 14:29:19 -0800 | [diff] [blame] | 454 | if (!strncmp(str, "on", 2)) { |
| 455 | dmar_disabled = 0; |
| 456 | printk(KERN_INFO "Intel-IOMMU: enabled\n"); |
| 457 | } else if (!strncmp(str, "off", 3)) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 458 | dmar_disabled = 1; |
Kyle McMartin | 0cd5c3c | 2009-02-04 14:29:19 -0800 | [diff] [blame] | 459 | printk(KERN_INFO "Intel-IOMMU: disabled\n"); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 460 | } else if (!strncmp(str, "igfx_off", 8)) { |
| 461 | dmar_map_gfx = 0; |
| 462 | printk(KERN_INFO |
| 463 | "Intel-IOMMU: disable GFX device mapping\n"); |
Keshavamurthy, Anil S | 7d3b03c | 2007-10-21 16:41:53 -0700 | [diff] [blame] | 464 | } else if (!strncmp(str, "forcedac", 8)) { |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 465 | printk(KERN_INFO |
Keshavamurthy, Anil S | 7d3b03c | 2007-10-21 16:41:53 -0700 | [diff] [blame] | 466 | "Intel-IOMMU: Forcing DAC for PCI devices\n"); |
| 467 | dmar_forcedac = 1; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 468 | } else if (!strncmp(str, "strict", 6)) { |
| 469 | printk(KERN_INFO |
| 470 | "Intel-IOMMU: disable batched IOTLB flush\n"); |
| 471 | intel_iommu_strict = 1; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 472 | } else if (!strncmp(str, "sp_off", 6)) { |
| 473 | printk(KERN_INFO |
| 474 | "Intel-IOMMU: disable supported super page\n"); |
| 475 | intel_iommu_superpage = 0; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 476 | } |
| 477 | |
| 478 | str += strcspn(str, ","); |
| 479 | while (*str == ',') |
| 480 | str++; |
| 481 | } |
| 482 | return 0; |
| 483 | } |
| 484 | __setup("intel_iommu=", intel_iommu_setup); |
| 485 | |
| 486 | static struct kmem_cache *iommu_domain_cache; |
| 487 | static struct kmem_cache *iommu_devinfo_cache; |
| 488 | static struct kmem_cache *iommu_iova_cache; |
| 489 | |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 490 | static inline void *alloc_pgtable_page(int node) |
Keshavamurthy, Anil S | eb3fa7c | 2007-10-21 16:41:52 -0700 | [diff] [blame] | 491 | { |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 492 | struct page *page; |
| 493 | void *vaddr = NULL; |
Keshavamurthy, Anil S | eb3fa7c | 2007-10-21 16:41:52 -0700 | [diff] [blame] | 494 | |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 495 | page = alloc_pages_node(node, GFP_ATOMIC | __GFP_ZERO, 0); |
| 496 | if (page) |
| 497 | vaddr = page_address(page); |
Keshavamurthy, Anil S | eb3fa7c | 2007-10-21 16:41:52 -0700 | [diff] [blame] | 498 | return vaddr; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 499 | } |
| 500 | |
| 501 | static inline void free_pgtable_page(void *vaddr) |
| 502 | { |
| 503 | free_page((unsigned long)vaddr); |
| 504 | } |
| 505 | |
| 506 | static inline void *alloc_domain_mem(void) |
| 507 | { |
KOSAKI Motohiro | 354bb65 | 2009-11-17 16:21:09 +0900 | [diff] [blame] | 508 | return kmem_cache_alloc(iommu_domain_cache, GFP_ATOMIC); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 509 | } |
| 510 | |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 511 | static void free_domain_mem(void *vaddr) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 512 | { |
| 513 | kmem_cache_free(iommu_domain_cache, vaddr); |
| 514 | } |
| 515 | |
| 516 | static inline void * alloc_devinfo_mem(void) |
| 517 | { |
KOSAKI Motohiro | 354bb65 | 2009-11-17 16:21:09 +0900 | [diff] [blame] | 518 | return kmem_cache_alloc(iommu_devinfo_cache, GFP_ATOMIC); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 519 | } |
| 520 | |
| 521 | static inline void free_devinfo_mem(void *vaddr) |
| 522 | { |
| 523 | kmem_cache_free(iommu_devinfo_cache, vaddr); |
| 524 | } |
| 525 | |
| 526 | struct iova *alloc_iova_mem(void) |
| 527 | { |
KOSAKI Motohiro | 354bb65 | 2009-11-17 16:21:09 +0900 | [diff] [blame] | 528 | return kmem_cache_alloc(iommu_iova_cache, GFP_ATOMIC); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 529 | } |
| 530 | |
| 531 | void free_iova_mem(struct iova *iova) |
| 532 | { |
| 533 | kmem_cache_free(iommu_iova_cache, iova); |
| 534 | } |
| 535 | |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 536 | static inline int domain_type_is_vm(struct dmar_domain *domain) |
| 537 | { |
| 538 | return domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE; |
| 539 | } |
| 540 | |
| 541 | static inline int domain_type_is_vm_or_si(struct dmar_domain *domain) |
| 542 | { |
| 543 | return domain->flags & (DOMAIN_FLAG_VIRTUAL_MACHINE | |
| 544 | DOMAIN_FLAG_STATIC_IDENTITY); |
| 545 | } |
Weidong Han | 1b57368 | 2008-12-08 15:34:06 +0800 | [diff] [blame] | 546 | |
Jiang Liu | 162d1b1 | 2014-07-11 14:19:35 +0800 | [diff] [blame] | 547 | static inline int domain_pfn_supported(struct dmar_domain *domain, |
| 548 | unsigned long pfn) |
| 549 | { |
| 550 | int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; |
| 551 | |
| 552 | return !(addr_width < BITS_PER_LONG && pfn >> addr_width); |
| 553 | } |
| 554 | |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 555 | static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw) |
Weidong Han | 1b57368 | 2008-12-08 15:34:06 +0800 | [diff] [blame] | 556 | { |
| 557 | unsigned long sagaw; |
| 558 | int agaw = -1; |
| 559 | |
| 560 | sagaw = cap_sagaw(iommu->cap); |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 561 | for (agaw = width_to_agaw(max_gaw); |
Weidong Han | 1b57368 | 2008-12-08 15:34:06 +0800 | [diff] [blame] | 562 | agaw >= 0; agaw--) { |
| 563 | if (test_bit(agaw, &sagaw)) |
| 564 | break; |
| 565 | } |
| 566 | |
| 567 | return agaw; |
| 568 | } |
| 569 | |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 570 | /* |
| 571 | * Calculate max SAGAW for each iommu. |
| 572 | */ |
| 573 | int iommu_calculate_max_sagaw(struct intel_iommu *iommu) |
| 574 | { |
| 575 | return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH); |
| 576 | } |
| 577 | |
| 578 | /* |
| 579 | * calculate agaw for each iommu. |
| 580 | * "SAGAW" may be different across iommus, use a default agaw, and |
| 581 | * get a supported less agaw for iommus that don't support the default agaw. |
| 582 | */ |
| 583 | int iommu_calculate_agaw(struct intel_iommu *iommu) |
| 584 | { |
| 585 | return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH); |
| 586 | } |
| 587 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 588 | /* This functionin only returns single iommu in a domain */ |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 589 | static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain) |
| 590 | { |
| 591 | int iommu_id; |
| 592 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 593 | /* si_domain and vm domain should not get here. */ |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 594 | BUG_ON(domain_type_is_vm_or_si(domain)); |
Mike Travis | 1b198bb | 2012-03-05 15:05:16 -0800 | [diff] [blame] | 595 | iommu_id = find_first_bit(domain->iommu_bmp, g_num_of_iommus); |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 596 | if (iommu_id < 0 || iommu_id >= g_num_of_iommus) |
| 597 | return NULL; |
| 598 | |
| 599 | return g_iommus[iommu_id]; |
| 600 | } |
| 601 | |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 602 | static void domain_update_iommu_coherency(struct dmar_domain *domain) |
| 603 | { |
David Woodhouse | d050196 | 2014-03-11 17:10:29 -0700 | [diff] [blame] | 604 | struct dmar_drhd_unit *drhd; |
| 605 | struct intel_iommu *iommu; |
| 606 | int i, found = 0; |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 607 | |
David Woodhouse | d050196 | 2014-03-11 17:10:29 -0700 | [diff] [blame] | 608 | domain->iommu_coherency = 1; |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 609 | |
Mike Travis | 1b198bb | 2012-03-05 15:05:16 -0800 | [diff] [blame] | 610 | for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus) { |
David Woodhouse | d050196 | 2014-03-11 17:10:29 -0700 | [diff] [blame] | 611 | found = 1; |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 612 | if (!ecap_coherent(g_iommus[i]->ecap)) { |
| 613 | domain->iommu_coherency = 0; |
| 614 | break; |
| 615 | } |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 616 | } |
David Woodhouse | d050196 | 2014-03-11 17:10:29 -0700 | [diff] [blame] | 617 | if (found) |
| 618 | return; |
| 619 | |
| 620 | /* No hardware attached; use lowest common denominator */ |
| 621 | rcu_read_lock(); |
| 622 | for_each_active_iommu(iommu, drhd) { |
| 623 | if (!ecap_coherent(iommu->ecap)) { |
| 624 | domain->iommu_coherency = 0; |
| 625 | break; |
| 626 | } |
| 627 | } |
| 628 | rcu_read_unlock(); |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 629 | } |
| 630 | |
Jiang Liu | 161f693 | 2014-07-11 14:19:37 +0800 | [diff] [blame] | 631 | static int domain_update_iommu_snooping(struct intel_iommu *skip) |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 632 | { |
Allen Kay | 8140a95 | 2011-10-14 12:32:17 -0700 | [diff] [blame] | 633 | struct dmar_drhd_unit *drhd; |
Jiang Liu | 161f693 | 2014-07-11 14:19:37 +0800 | [diff] [blame] | 634 | struct intel_iommu *iommu; |
| 635 | int ret = 1; |
| 636 | |
| 637 | rcu_read_lock(); |
| 638 | for_each_active_iommu(iommu, drhd) { |
| 639 | if (iommu != skip) { |
| 640 | if (!ecap_sc_support(iommu->ecap)) { |
| 641 | ret = 0; |
| 642 | break; |
| 643 | } |
| 644 | } |
| 645 | } |
| 646 | rcu_read_unlock(); |
| 647 | |
| 648 | return ret; |
| 649 | } |
| 650 | |
| 651 | static int domain_update_iommu_superpage(struct intel_iommu *skip) |
| 652 | { |
| 653 | struct dmar_drhd_unit *drhd; |
| 654 | struct intel_iommu *iommu; |
Allen Kay | 8140a95 | 2011-10-14 12:32:17 -0700 | [diff] [blame] | 655 | int mask = 0xf; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 656 | |
| 657 | if (!intel_iommu_superpage) { |
Jiang Liu | 161f693 | 2014-07-11 14:19:37 +0800 | [diff] [blame] | 658 | return 0; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 659 | } |
| 660 | |
Allen Kay | 8140a95 | 2011-10-14 12:32:17 -0700 | [diff] [blame] | 661 | /* set iommu_superpage to the smallest common denominator */ |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 662 | rcu_read_lock(); |
Allen Kay | 8140a95 | 2011-10-14 12:32:17 -0700 | [diff] [blame] | 663 | for_each_active_iommu(iommu, drhd) { |
Jiang Liu | 161f693 | 2014-07-11 14:19:37 +0800 | [diff] [blame] | 664 | if (iommu != skip) { |
| 665 | mask &= cap_super_page_val(iommu->cap); |
| 666 | if (!mask) |
| 667 | break; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 668 | } |
| 669 | } |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 670 | rcu_read_unlock(); |
| 671 | |
Jiang Liu | 161f693 | 2014-07-11 14:19:37 +0800 | [diff] [blame] | 672 | return fls(mask); |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 673 | } |
| 674 | |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 675 | /* Some capabilities may be different across iommus */ |
| 676 | static void domain_update_iommu_cap(struct dmar_domain *domain) |
| 677 | { |
| 678 | domain_update_iommu_coherency(domain); |
Jiang Liu | 161f693 | 2014-07-11 14:19:37 +0800 | [diff] [blame] | 679 | domain->iommu_snooping = domain_update_iommu_snooping(NULL); |
| 680 | domain->iommu_superpage = domain_update_iommu_superpage(NULL); |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 681 | } |
| 682 | |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 683 | static struct intel_iommu *device_to_iommu(struct device *dev, u8 *bus, u8 *devfn) |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 684 | { |
| 685 | struct dmar_drhd_unit *drhd = NULL; |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 686 | struct intel_iommu *iommu; |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 687 | struct device *tmp; |
| 688 | struct pci_dev *ptmp, *pdev = NULL; |
Yijing Wang | aa4d066 | 2014-05-26 20:14:06 +0800 | [diff] [blame] | 689 | u16 segment = 0; |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 690 | int i; |
| 691 | |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 692 | if (dev_is_pci(dev)) { |
| 693 | pdev = to_pci_dev(dev); |
| 694 | segment = pci_domain_nr(pdev->bus); |
| 695 | } else if (ACPI_COMPANION(dev)) |
| 696 | dev = &ACPI_COMPANION(dev)->dev; |
| 697 | |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 698 | rcu_read_lock(); |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 699 | for_each_active_iommu(iommu, drhd) { |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 700 | if (pdev && segment != drhd->segment) |
David Woodhouse | 276dbf99 | 2009-04-04 01:45:37 +0100 | [diff] [blame] | 701 | continue; |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 702 | |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 703 | for_each_active_dev_scope(drhd->devices, |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 704 | drhd->devices_cnt, i, tmp) { |
| 705 | if (tmp == dev) { |
| 706 | *bus = drhd->devices[i].bus; |
| 707 | *devfn = drhd->devices[i].devfn; |
| 708 | goto out; |
| 709 | } |
| 710 | |
| 711 | if (!pdev || !dev_is_pci(tmp)) |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 712 | continue; |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 713 | |
| 714 | ptmp = to_pci_dev(tmp); |
| 715 | if (ptmp->subordinate && |
| 716 | ptmp->subordinate->number <= pdev->bus->number && |
| 717 | ptmp->subordinate->busn_res.end >= pdev->bus->number) |
| 718 | goto got_pdev; |
David Woodhouse | 924b623 | 2009-04-04 00:39:25 +0100 | [diff] [blame] | 719 | } |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 720 | |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 721 | if (pdev && drhd->include_all) { |
| 722 | got_pdev: |
| 723 | *bus = pdev->bus->number; |
| 724 | *devfn = pdev->devfn; |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 725 | goto out; |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 726 | } |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 727 | } |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 728 | iommu = NULL; |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 729 | out: |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 730 | rcu_read_unlock(); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 731 | |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 732 | return iommu; |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 733 | } |
| 734 | |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 735 | static void domain_flush_cache(struct dmar_domain *domain, |
| 736 | void *addr, int size) |
| 737 | { |
| 738 | if (!domain->iommu_coherency) |
| 739 | clflush_cache_range(addr, size); |
| 740 | } |
| 741 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 742 | /* Gets context entry for a given bus and devfn */ |
| 743 | static struct context_entry * device_to_context_entry(struct intel_iommu *iommu, |
| 744 | u8 bus, u8 devfn) |
| 745 | { |
| 746 | struct root_entry *root; |
| 747 | struct context_entry *context; |
| 748 | unsigned long phy_addr; |
| 749 | unsigned long flags; |
| 750 | |
| 751 | spin_lock_irqsave(&iommu->lock, flags); |
| 752 | root = &iommu->root_entry[bus]; |
| 753 | context = get_context_addr_from_root(root); |
| 754 | if (!context) { |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 755 | context = (struct context_entry *) |
| 756 | alloc_pgtable_page(iommu->node); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 757 | if (!context) { |
| 758 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 759 | return NULL; |
| 760 | } |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 761 | __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 762 | phy_addr = virt_to_phys((void *)context); |
| 763 | set_root_value(root, phy_addr); |
| 764 | set_root_present(root); |
| 765 | __iommu_flush_cache(iommu, root, sizeof(*root)); |
| 766 | } |
| 767 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 768 | return &context[devfn]; |
| 769 | } |
| 770 | |
| 771 | static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn) |
| 772 | { |
| 773 | struct root_entry *root; |
| 774 | struct context_entry *context; |
| 775 | int ret; |
| 776 | unsigned long flags; |
| 777 | |
| 778 | spin_lock_irqsave(&iommu->lock, flags); |
| 779 | root = &iommu->root_entry[bus]; |
| 780 | context = get_context_addr_from_root(root); |
| 781 | if (!context) { |
| 782 | ret = 0; |
| 783 | goto out; |
| 784 | } |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 785 | ret = context_present(&context[devfn]); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 786 | out: |
| 787 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 788 | return ret; |
| 789 | } |
| 790 | |
| 791 | static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn) |
| 792 | { |
| 793 | struct root_entry *root; |
| 794 | struct context_entry *context; |
| 795 | unsigned long flags; |
| 796 | |
| 797 | spin_lock_irqsave(&iommu->lock, flags); |
| 798 | root = &iommu->root_entry[bus]; |
| 799 | context = get_context_addr_from_root(root); |
| 800 | if (context) { |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 801 | context_clear_entry(&context[devfn]); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 802 | __iommu_flush_cache(iommu, &context[devfn], \ |
| 803 | sizeof(*context)); |
| 804 | } |
| 805 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 806 | } |
| 807 | |
| 808 | static void free_context_table(struct intel_iommu *iommu) |
| 809 | { |
| 810 | struct root_entry *root; |
| 811 | int i; |
| 812 | unsigned long flags; |
| 813 | struct context_entry *context; |
| 814 | |
| 815 | spin_lock_irqsave(&iommu->lock, flags); |
| 816 | if (!iommu->root_entry) { |
| 817 | goto out; |
| 818 | } |
| 819 | for (i = 0; i < ROOT_ENTRY_NR; i++) { |
| 820 | root = &iommu->root_entry[i]; |
| 821 | context = get_context_addr_from_root(root); |
| 822 | if (context) |
| 823 | free_pgtable_page(context); |
| 824 | } |
| 825 | free_pgtable_page(iommu->root_entry); |
| 826 | iommu->root_entry = NULL; |
| 827 | out: |
| 828 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 829 | } |
| 830 | |
David Woodhouse | b026fd2 | 2009-06-28 10:37:25 +0100 | [diff] [blame] | 831 | static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain, |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 832 | unsigned long pfn, int *target_level) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 833 | { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 834 | struct dma_pte *parent, *pte = NULL; |
| 835 | int level = agaw_to_level(domain->agaw); |
Allen Kay | 4399c8b | 2011-10-14 12:32:46 -0700 | [diff] [blame] | 836 | int offset; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 837 | |
| 838 | BUG_ON(!domain->pgd); |
Julian Stecklina | f942360 | 2013-10-09 10:03:52 +0200 | [diff] [blame] | 839 | |
Jiang Liu | 162d1b1 | 2014-07-11 14:19:35 +0800 | [diff] [blame] | 840 | if (!domain_pfn_supported(domain, pfn)) |
Julian Stecklina | f942360 | 2013-10-09 10:03:52 +0200 | [diff] [blame] | 841 | /* Address beyond IOMMU's addressing capabilities. */ |
| 842 | return NULL; |
| 843 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 844 | parent = domain->pgd; |
| 845 | |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 846 | while (1) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 847 | void *tmp_page; |
| 848 | |
David Woodhouse | b026fd2 | 2009-06-28 10:37:25 +0100 | [diff] [blame] | 849 | offset = pfn_level_offset(pfn, level); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 850 | pte = &parent[offset]; |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 851 | if (!*target_level && (dma_pte_superpage(pte) || !dma_pte_present(pte))) |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 852 | break; |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 853 | if (level == *target_level) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 854 | break; |
| 855 | |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 856 | if (!dma_pte_present(pte)) { |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 857 | uint64_t pteval; |
| 858 | |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 859 | tmp_page = alloc_pgtable_page(domain->nid); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 860 | |
David Woodhouse | 206a73c1 | 2009-07-01 19:30:28 +0100 | [diff] [blame] | 861 | if (!tmp_page) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 862 | return NULL; |
David Woodhouse | 206a73c1 | 2009-07-01 19:30:28 +0100 | [diff] [blame] | 863 | |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 864 | domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE); |
Benjamin LaHaise | 64de5af | 2009-09-16 21:05:55 -0400 | [diff] [blame] | 865 | pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE; |
Yijing Wang | effad4b | 2014-05-26 20:13:47 +0800 | [diff] [blame] | 866 | if (cmpxchg64(&pte->val, 0ULL, pteval)) |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 867 | /* Someone else set it while we were thinking; use theirs. */ |
| 868 | free_pgtable_page(tmp_page); |
Yijing Wang | effad4b | 2014-05-26 20:13:47 +0800 | [diff] [blame] | 869 | else |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 870 | domain_flush_cache(domain, pte, sizeof(*pte)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 871 | } |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 872 | if (level == 1) |
| 873 | break; |
| 874 | |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 875 | parent = phys_to_virt(dma_pte_addr(pte)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 876 | level--; |
| 877 | } |
| 878 | |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 879 | if (!*target_level) |
| 880 | *target_level = level; |
| 881 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 882 | return pte; |
| 883 | } |
| 884 | |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 885 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 886 | /* return address's pte at specific level */ |
David Woodhouse | 90dcfb5 | 2009-06-27 17:14:59 +0100 | [diff] [blame] | 887 | static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain, |
| 888 | unsigned long pfn, |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 889 | int level, int *large_page) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 890 | { |
| 891 | struct dma_pte *parent, *pte = NULL; |
| 892 | int total = agaw_to_level(domain->agaw); |
| 893 | int offset; |
| 894 | |
| 895 | parent = domain->pgd; |
| 896 | while (level <= total) { |
David Woodhouse | 90dcfb5 | 2009-06-27 17:14:59 +0100 | [diff] [blame] | 897 | offset = pfn_level_offset(pfn, total); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 898 | pte = &parent[offset]; |
| 899 | if (level == total) |
| 900 | return pte; |
| 901 | |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 902 | if (!dma_pte_present(pte)) { |
| 903 | *large_page = total; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 904 | break; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 905 | } |
| 906 | |
Yijing Wang | e16922a | 2014-05-20 20:37:51 +0800 | [diff] [blame] | 907 | if (dma_pte_superpage(pte)) { |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 908 | *large_page = total; |
| 909 | return pte; |
| 910 | } |
| 911 | |
Mark McLoughlin | 19c239c | 2008-11-21 16:56:53 +0000 | [diff] [blame] | 912 | parent = phys_to_virt(dma_pte_addr(pte)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 913 | total--; |
| 914 | } |
| 915 | return NULL; |
| 916 | } |
| 917 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 918 | /* clear last level pte, a tlb flush should be followed */ |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 919 | static void dma_pte_clear_range(struct dmar_domain *domain, |
David Woodhouse | 595badf | 2009-06-27 22:09:11 +0100 | [diff] [blame] | 920 | unsigned long start_pfn, |
| 921 | unsigned long last_pfn) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 922 | { |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 923 | unsigned int large_page = 1; |
David Woodhouse | 310a5ab | 2009-06-28 18:52:20 +0100 | [diff] [blame] | 924 | struct dma_pte *first_pte, *pte; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 925 | |
Jiang Liu | 162d1b1 | 2014-07-11 14:19:35 +0800 | [diff] [blame] | 926 | BUG_ON(!domain_pfn_supported(domain, start_pfn)); |
| 927 | BUG_ON(!domain_pfn_supported(domain, last_pfn)); |
David Woodhouse | 59c3628 | 2009-09-19 07:36:28 -0700 | [diff] [blame] | 928 | BUG_ON(start_pfn > last_pfn); |
David Woodhouse | 66eae84 | 2009-06-27 19:00:32 +0100 | [diff] [blame] | 929 | |
David Woodhouse | 04b18e6 | 2009-06-27 19:15:01 +0100 | [diff] [blame] | 930 | /* we don't need lock here; nobody else touches the iova range */ |
David Woodhouse | 59c3628 | 2009-09-19 07:36:28 -0700 | [diff] [blame] | 931 | do { |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 932 | large_page = 1; |
| 933 | first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1, &large_page); |
David Woodhouse | 310a5ab | 2009-06-28 18:52:20 +0100 | [diff] [blame] | 934 | if (!pte) { |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 935 | start_pfn = align_to_level(start_pfn + 1, large_page + 1); |
David Woodhouse | 310a5ab | 2009-06-28 18:52:20 +0100 | [diff] [blame] | 936 | continue; |
| 937 | } |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 938 | do { |
David Woodhouse | 310a5ab | 2009-06-28 18:52:20 +0100 | [diff] [blame] | 939 | dma_clear_pte(pte); |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 940 | start_pfn += lvl_to_nr_pages(large_page); |
David Woodhouse | 310a5ab | 2009-06-28 18:52:20 +0100 | [diff] [blame] | 941 | pte++; |
David Woodhouse | 75e6bf9 | 2009-07-02 11:21:16 +0100 | [diff] [blame] | 942 | } while (start_pfn <= last_pfn && !first_pte_in_page(pte)); |
| 943 | |
David Woodhouse | 310a5ab | 2009-06-28 18:52:20 +0100 | [diff] [blame] | 944 | domain_flush_cache(domain, first_pte, |
| 945 | (void *)pte - (void *)first_pte); |
David Woodhouse | 59c3628 | 2009-09-19 07:36:28 -0700 | [diff] [blame] | 946 | |
| 947 | } while (start_pfn && start_pfn <= last_pfn); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 948 | } |
| 949 | |
Alex Williamson | 3269ee0 | 2013-06-15 10:27:19 -0600 | [diff] [blame] | 950 | static void dma_pte_free_level(struct dmar_domain *domain, int level, |
| 951 | struct dma_pte *pte, unsigned long pfn, |
| 952 | unsigned long start_pfn, unsigned long last_pfn) |
| 953 | { |
| 954 | pfn = max(start_pfn, pfn); |
| 955 | pte = &pte[pfn_level_offset(pfn, level)]; |
| 956 | |
| 957 | do { |
| 958 | unsigned long level_pfn; |
| 959 | struct dma_pte *level_pte; |
| 960 | |
| 961 | if (!dma_pte_present(pte) || dma_pte_superpage(pte)) |
| 962 | goto next; |
| 963 | |
| 964 | level_pfn = pfn & level_mask(level - 1); |
| 965 | level_pte = phys_to_virt(dma_pte_addr(pte)); |
| 966 | |
| 967 | if (level > 2) |
| 968 | dma_pte_free_level(domain, level - 1, level_pte, |
| 969 | level_pfn, start_pfn, last_pfn); |
| 970 | |
| 971 | /* If range covers entire pagetable, free it */ |
| 972 | if (!(start_pfn > level_pfn || |
Alex Williamson | 08336fd | 2014-01-21 15:48:18 -0800 | [diff] [blame] | 973 | last_pfn < level_pfn + level_size(level) - 1)) { |
Alex Williamson | 3269ee0 | 2013-06-15 10:27:19 -0600 | [diff] [blame] | 974 | dma_clear_pte(pte); |
| 975 | domain_flush_cache(domain, pte, sizeof(*pte)); |
| 976 | free_pgtable_page(level_pte); |
| 977 | } |
| 978 | next: |
| 979 | pfn += level_size(level); |
| 980 | } while (!first_pte_in_page(++pte) && pfn <= last_pfn); |
| 981 | } |
| 982 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 983 | /* free page table pages. last level pte should already be cleared */ |
| 984 | static void dma_pte_free_pagetable(struct dmar_domain *domain, |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 985 | unsigned long start_pfn, |
| 986 | unsigned long last_pfn) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 987 | { |
Jiang Liu | 162d1b1 | 2014-07-11 14:19:35 +0800 | [diff] [blame] | 988 | BUG_ON(!domain_pfn_supported(domain, start_pfn)); |
| 989 | BUG_ON(!domain_pfn_supported(domain, last_pfn)); |
David Woodhouse | 59c3628 | 2009-09-19 07:36:28 -0700 | [diff] [blame] | 990 | BUG_ON(start_pfn > last_pfn); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 991 | |
Jiang Liu | d41a4ad | 2014-07-11 14:19:34 +0800 | [diff] [blame] | 992 | dma_pte_clear_range(domain, start_pfn, last_pfn); |
| 993 | |
David Woodhouse | f3a0a52 | 2009-06-30 03:40:07 +0100 | [diff] [blame] | 994 | /* We don't need lock here; nobody else touches the iova range */ |
Alex Williamson | 3269ee0 | 2013-06-15 10:27:19 -0600 | [diff] [blame] | 995 | dma_pte_free_level(domain, agaw_to_level(domain->agaw), |
| 996 | domain->pgd, 0, start_pfn, last_pfn); |
David Woodhouse | 6660c63 | 2009-06-27 22:41:00 +0100 | [diff] [blame] | 997 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 998 | /* free pgd */ |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 999 | if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1000 | free_pgtable_page(domain->pgd); |
| 1001 | domain->pgd = NULL; |
| 1002 | } |
| 1003 | } |
| 1004 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1005 | /* When a page at a given level is being unlinked from its parent, we don't |
| 1006 | need to *modify* it at all. All we need to do is make a list of all the |
| 1007 | pages which can be freed just as soon as we've flushed the IOTLB and we |
| 1008 | know the hardware page-walk will no longer touch them. |
| 1009 | The 'pte' argument is the *parent* PTE, pointing to the page that is to |
| 1010 | be freed. */ |
| 1011 | static struct page *dma_pte_list_pagetables(struct dmar_domain *domain, |
| 1012 | int level, struct dma_pte *pte, |
| 1013 | struct page *freelist) |
| 1014 | { |
| 1015 | struct page *pg; |
| 1016 | |
| 1017 | pg = pfn_to_page(dma_pte_addr(pte) >> PAGE_SHIFT); |
| 1018 | pg->freelist = freelist; |
| 1019 | freelist = pg; |
| 1020 | |
| 1021 | if (level == 1) |
| 1022 | return freelist; |
| 1023 | |
Jiang Liu | adeb259 | 2014-04-09 10:20:39 +0800 | [diff] [blame] | 1024 | pte = page_address(pg); |
| 1025 | do { |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1026 | if (dma_pte_present(pte) && !dma_pte_superpage(pte)) |
| 1027 | freelist = dma_pte_list_pagetables(domain, level - 1, |
| 1028 | pte, freelist); |
Jiang Liu | adeb259 | 2014-04-09 10:20:39 +0800 | [diff] [blame] | 1029 | pte++; |
| 1030 | } while (!first_pte_in_page(pte)); |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1031 | |
| 1032 | return freelist; |
| 1033 | } |
| 1034 | |
| 1035 | static struct page *dma_pte_clear_level(struct dmar_domain *domain, int level, |
| 1036 | struct dma_pte *pte, unsigned long pfn, |
| 1037 | unsigned long start_pfn, |
| 1038 | unsigned long last_pfn, |
| 1039 | struct page *freelist) |
| 1040 | { |
| 1041 | struct dma_pte *first_pte = NULL, *last_pte = NULL; |
| 1042 | |
| 1043 | pfn = max(start_pfn, pfn); |
| 1044 | pte = &pte[pfn_level_offset(pfn, level)]; |
| 1045 | |
| 1046 | do { |
| 1047 | unsigned long level_pfn; |
| 1048 | |
| 1049 | if (!dma_pte_present(pte)) |
| 1050 | goto next; |
| 1051 | |
| 1052 | level_pfn = pfn & level_mask(level); |
| 1053 | |
| 1054 | /* If range covers entire pagetable, free it */ |
| 1055 | if (start_pfn <= level_pfn && |
| 1056 | last_pfn >= level_pfn + level_size(level) - 1) { |
| 1057 | /* These suborbinate page tables are going away entirely. Don't |
| 1058 | bother to clear them; we're just going to *free* them. */ |
| 1059 | if (level > 1 && !dma_pte_superpage(pte)) |
| 1060 | freelist = dma_pte_list_pagetables(domain, level - 1, pte, freelist); |
| 1061 | |
| 1062 | dma_clear_pte(pte); |
| 1063 | if (!first_pte) |
| 1064 | first_pte = pte; |
| 1065 | last_pte = pte; |
| 1066 | } else if (level > 1) { |
| 1067 | /* Recurse down into a level that isn't *entirely* obsolete */ |
| 1068 | freelist = dma_pte_clear_level(domain, level - 1, |
| 1069 | phys_to_virt(dma_pte_addr(pte)), |
| 1070 | level_pfn, start_pfn, last_pfn, |
| 1071 | freelist); |
| 1072 | } |
| 1073 | next: |
| 1074 | pfn += level_size(level); |
| 1075 | } while (!first_pte_in_page(++pte) && pfn <= last_pfn); |
| 1076 | |
| 1077 | if (first_pte) |
| 1078 | domain_flush_cache(domain, first_pte, |
| 1079 | (void *)++last_pte - (void *)first_pte); |
| 1080 | |
| 1081 | return freelist; |
| 1082 | } |
| 1083 | |
| 1084 | /* We can't just free the pages because the IOMMU may still be walking |
| 1085 | the page tables, and may have cached the intermediate levels. The |
| 1086 | pages can only be freed after the IOTLB flush has been done. */ |
| 1087 | struct page *domain_unmap(struct dmar_domain *domain, |
| 1088 | unsigned long start_pfn, |
| 1089 | unsigned long last_pfn) |
| 1090 | { |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1091 | struct page *freelist = NULL; |
| 1092 | |
Jiang Liu | 162d1b1 | 2014-07-11 14:19:35 +0800 | [diff] [blame] | 1093 | BUG_ON(!domain_pfn_supported(domain, start_pfn)); |
| 1094 | BUG_ON(!domain_pfn_supported(domain, last_pfn)); |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1095 | BUG_ON(start_pfn > last_pfn); |
| 1096 | |
| 1097 | /* we don't need lock here; nobody else touches the iova range */ |
| 1098 | freelist = dma_pte_clear_level(domain, agaw_to_level(domain->agaw), |
| 1099 | domain->pgd, 0, start_pfn, last_pfn, NULL); |
| 1100 | |
| 1101 | /* free pgd */ |
| 1102 | if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) { |
| 1103 | struct page *pgd_page = virt_to_page(domain->pgd); |
| 1104 | pgd_page->freelist = freelist; |
| 1105 | freelist = pgd_page; |
| 1106 | |
| 1107 | domain->pgd = NULL; |
| 1108 | } |
| 1109 | |
| 1110 | return freelist; |
| 1111 | } |
| 1112 | |
| 1113 | void dma_free_pagelist(struct page *freelist) |
| 1114 | { |
| 1115 | struct page *pg; |
| 1116 | |
| 1117 | while ((pg = freelist)) { |
| 1118 | freelist = pg->freelist; |
| 1119 | free_pgtable_page(page_address(pg)); |
| 1120 | } |
| 1121 | } |
| 1122 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1123 | /* iommu handling */ |
| 1124 | static int iommu_alloc_root_entry(struct intel_iommu *iommu) |
| 1125 | { |
| 1126 | struct root_entry *root; |
| 1127 | unsigned long flags; |
| 1128 | |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 1129 | root = (struct root_entry *)alloc_pgtable_page(iommu->node); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1130 | if (!root) |
| 1131 | return -ENOMEM; |
| 1132 | |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 1133 | __iommu_flush_cache(iommu, root, ROOT_SIZE); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1134 | |
| 1135 | spin_lock_irqsave(&iommu->lock, flags); |
| 1136 | iommu->root_entry = root; |
| 1137 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 1138 | |
| 1139 | return 0; |
| 1140 | } |
| 1141 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1142 | static void iommu_set_root_entry(struct intel_iommu *iommu) |
| 1143 | { |
| 1144 | void *addr; |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1145 | u32 sts; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1146 | unsigned long flag; |
| 1147 | |
| 1148 | addr = iommu->root_entry; |
| 1149 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1150 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1151 | dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr)); |
| 1152 | |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1153 | writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1154 | |
| 1155 | /* Make sure hardware complete it */ |
| 1156 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1157 | readl, (sts & DMA_GSTS_RTPS), sts); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1158 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1159 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1160 | } |
| 1161 | |
| 1162 | static void iommu_flush_write_buffer(struct intel_iommu *iommu) |
| 1163 | { |
| 1164 | u32 val; |
| 1165 | unsigned long flag; |
| 1166 | |
David Woodhouse | 9af8814 | 2009-02-13 23:18:03 +0000 | [diff] [blame] | 1167 | if (!rwbf_quirk && !cap_rwbf(iommu->cap)) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1168 | return; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1169 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1170 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
David Woodhouse | 462b60f | 2009-05-10 20:18:18 +0100 | [diff] [blame] | 1171 | writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1172 | |
| 1173 | /* Make sure hardware complete it */ |
| 1174 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1175 | readl, (!(val & DMA_GSTS_WBFS)), val); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1176 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1177 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1178 | } |
| 1179 | |
| 1180 | /* return value determine if we need a write buffer flush */ |
David Woodhouse | 4c25a2c | 2009-05-10 17:16:06 +0100 | [diff] [blame] | 1181 | static void __iommu_flush_context(struct intel_iommu *iommu, |
| 1182 | u16 did, u16 source_id, u8 function_mask, |
| 1183 | u64 type) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1184 | { |
| 1185 | u64 val = 0; |
| 1186 | unsigned long flag; |
| 1187 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1188 | switch (type) { |
| 1189 | case DMA_CCMD_GLOBAL_INVL: |
| 1190 | val = DMA_CCMD_GLOBAL_INVL; |
| 1191 | break; |
| 1192 | case DMA_CCMD_DOMAIN_INVL: |
| 1193 | val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did); |
| 1194 | break; |
| 1195 | case DMA_CCMD_DEVICE_INVL: |
| 1196 | val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did) |
| 1197 | | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask); |
| 1198 | break; |
| 1199 | default: |
| 1200 | BUG(); |
| 1201 | } |
| 1202 | val |= DMA_CCMD_ICC; |
| 1203 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1204 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1205 | dmar_writeq(iommu->reg + DMAR_CCMD_REG, val); |
| 1206 | |
| 1207 | /* Make sure hardware complete it */ |
| 1208 | IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG, |
| 1209 | dmar_readq, (!(val & DMA_CCMD_ICC)), val); |
| 1210 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1211 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1212 | } |
| 1213 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1214 | /* return value determine if we need a write buffer flush */ |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 1215 | static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did, |
| 1216 | u64 addr, unsigned int size_order, u64 type) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1217 | { |
| 1218 | int tlb_offset = ecap_iotlb_offset(iommu->ecap); |
| 1219 | u64 val = 0, val_iva = 0; |
| 1220 | unsigned long flag; |
| 1221 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1222 | switch (type) { |
| 1223 | case DMA_TLB_GLOBAL_FLUSH: |
| 1224 | /* global flush doesn't need set IVA_REG */ |
| 1225 | val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT; |
| 1226 | break; |
| 1227 | case DMA_TLB_DSI_FLUSH: |
| 1228 | val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); |
| 1229 | break; |
| 1230 | case DMA_TLB_PSI_FLUSH: |
| 1231 | val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did); |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1232 | /* IH bit is passed in as part of address */ |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1233 | val_iva = size_order | addr; |
| 1234 | break; |
| 1235 | default: |
| 1236 | BUG(); |
| 1237 | } |
| 1238 | /* Note: set drain read/write */ |
| 1239 | #if 0 |
| 1240 | /* |
| 1241 | * This is probably to be super secure.. Looks like we can |
| 1242 | * ignore it without any impact. |
| 1243 | */ |
| 1244 | if (cap_read_drain(iommu->cap)) |
| 1245 | val |= DMA_TLB_READ_DRAIN; |
| 1246 | #endif |
| 1247 | if (cap_write_drain(iommu->cap)) |
| 1248 | val |= DMA_TLB_WRITE_DRAIN; |
| 1249 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1250 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1251 | /* Note: Only uses first TLB reg currently */ |
| 1252 | if (val_iva) |
| 1253 | dmar_writeq(iommu->reg + tlb_offset, val_iva); |
| 1254 | dmar_writeq(iommu->reg + tlb_offset + 8, val); |
| 1255 | |
| 1256 | /* Make sure hardware complete it */ |
| 1257 | IOMMU_WAIT_OP(iommu, tlb_offset + 8, |
| 1258 | dmar_readq, (!(val & DMA_TLB_IVT)), val); |
| 1259 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1260 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1261 | |
| 1262 | /* check IOTLB invalidation granularity */ |
| 1263 | if (DMA_TLB_IAIG(val) == 0) |
| 1264 | printk(KERN_ERR"IOMMU: flush IOTLB failed\n"); |
| 1265 | if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type)) |
| 1266 | pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n", |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 1267 | (unsigned long long)DMA_TLB_IIRG(type), |
| 1268 | (unsigned long long)DMA_TLB_IAIG(val)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1269 | } |
| 1270 | |
David Woodhouse | 64ae892 | 2014-03-09 12:52:30 -0700 | [diff] [blame] | 1271 | static struct device_domain_info * |
| 1272 | iommu_support_dev_iotlb (struct dmar_domain *domain, struct intel_iommu *iommu, |
| 1273 | u8 bus, u8 devfn) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1274 | { |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1275 | int found = 0; |
| 1276 | unsigned long flags; |
| 1277 | struct device_domain_info *info; |
David Woodhouse | 0bcb3e2 | 2014-03-06 17:12:03 +0000 | [diff] [blame] | 1278 | struct pci_dev *pdev; |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1279 | |
| 1280 | if (!ecap_dev_iotlb_support(iommu->ecap)) |
| 1281 | return NULL; |
| 1282 | |
| 1283 | if (!iommu->qi) |
| 1284 | return NULL; |
| 1285 | |
| 1286 | spin_lock_irqsave(&device_domain_lock, flags); |
| 1287 | list_for_each_entry(info, &domain->devices, link) |
Jiang Liu | c3b497c | 2014-07-11 14:19:25 +0800 | [diff] [blame] | 1288 | if (info->iommu == iommu && info->bus == bus && |
| 1289 | info->devfn == devfn) { |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1290 | found = 1; |
| 1291 | break; |
| 1292 | } |
| 1293 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 1294 | |
David Woodhouse | 0bcb3e2 | 2014-03-06 17:12:03 +0000 | [diff] [blame] | 1295 | if (!found || !info->dev || !dev_is_pci(info->dev)) |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1296 | return NULL; |
| 1297 | |
David Woodhouse | 0bcb3e2 | 2014-03-06 17:12:03 +0000 | [diff] [blame] | 1298 | pdev = to_pci_dev(info->dev); |
| 1299 | |
| 1300 | if (!pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS)) |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1301 | return NULL; |
| 1302 | |
David Woodhouse | 0bcb3e2 | 2014-03-06 17:12:03 +0000 | [diff] [blame] | 1303 | if (!dmar_find_matched_atsr_unit(pdev)) |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1304 | return NULL; |
| 1305 | |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1306 | return info; |
| 1307 | } |
| 1308 | |
| 1309 | static void iommu_enable_dev_iotlb(struct device_domain_info *info) |
| 1310 | { |
David Woodhouse | 0bcb3e2 | 2014-03-06 17:12:03 +0000 | [diff] [blame] | 1311 | if (!info || !dev_is_pci(info->dev)) |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1312 | return; |
| 1313 | |
David Woodhouse | 0bcb3e2 | 2014-03-06 17:12:03 +0000 | [diff] [blame] | 1314 | pci_enable_ats(to_pci_dev(info->dev), VTD_PAGE_SHIFT); |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1315 | } |
| 1316 | |
| 1317 | static void iommu_disable_dev_iotlb(struct device_domain_info *info) |
| 1318 | { |
David Woodhouse | 0bcb3e2 | 2014-03-06 17:12:03 +0000 | [diff] [blame] | 1319 | if (!info->dev || !dev_is_pci(info->dev) || |
| 1320 | !pci_ats_enabled(to_pci_dev(info->dev))) |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1321 | return; |
| 1322 | |
David Woodhouse | 0bcb3e2 | 2014-03-06 17:12:03 +0000 | [diff] [blame] | 1323 | pci_disable_ats(to_pci_dev(info->dev)); |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1324 | } |
| 1325 | |
| 1326 | static void iommu_flush_dev_iotlb(struct dmar_domain *domain, |
| 1327 | u64 addr, unsigned mask) |
| 1328 | { |
| 1329 | u16 sid, qdep; |
| 1330 | unsigned long flags; |
| 1331 | struct device_domain_info *info; |
| 1332 | |
| 1333 | spin_lock_irqsave(&device_domain_lock, flags); |
| 1334 | list_for_each_entry(info, &domain->devices, link) { |
David Woodhouse | 0bcb3e2 | 2014-03-06 17:12:03 +0000 | [diff] [blame] | 1335 | struct pci_dev *pdev; |
| 1336 | if (!info->dev || !dev_is_pci(info->dev)) |
| 1337 | continue; |
| 1338 | |
| 1339 | pdev = to_pci_dev(info->dev); |
| 1340 | if (!pci_ats_enabled(pdev)) |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1341 | continue; |
| 1342 | |
| 1343 | sid = info->bus << 8 | info->devfn; |
David Woodhouse | 0bcb3e2 | 2014-03-06 17:12:03 +0000 | [diff] [blame] | 1344 | qdep = pci_ats_queue_depth(pdev); |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1345 | qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask); |
| 1346 | } |
| 1347 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 1348 | } |
| 1349 | |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 1350 | static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did, |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1351 | unsigned long pfn, unsigned int pages, int ih, int map) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1352 | { |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 1353 | unsigned int mask = ilog2(__roundup_pow_of_two(pages)); |
David Woodhouse | 03d6a24 | 2009-06-28 15:33:46 +0100 | [diff] [blame] | 1354 | uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1355 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1356 | BUG_ON(pages == 0); |
| 1357 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1358 | if (ih) |
| 1359 | ih = 1 << 6; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1360 | /* |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 1361 | * Fallback to domain selective flush if no PSI support or the size is |
| 1362 | * too big. |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1363 | * PSI requires page size to be 2 ^ x, and the base address is naturally |
| 1364 | * aligned to the size |
| 1365 | */ |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 1366 | if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap)) |
| 1367 | iommu->flush.flush_iotlb(iommu, did, 0, 0, |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 1368 | DMA_TLB_DSI_FLUSH); |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 1369 | else |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1370 | iommu->flush.flush_iotlb(iommu, did, addr | ih, mask, |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 1371 | DMA_TLB_PSI_FLUSH); |
Yu Zhao | bf92df3 | 2009-06-29 11:31:45 +0800 | [diff] [blame] | 1372 | |
| 1373 | /* |
Nadav Amit | 8265363 | 2010-04-01 13:24:40 +0300 | [diff] [blame] | 1374 | * In caching mode, changes of pages from non-present to present require |
| 1375 | * flush. However, device IOTLB doesn't need to be flushed in this case. |
Yu Zhao | bf92df3 | 2009-06-29 11:31:45 +0800 | [diff] [blame] | 1376 | */ |
Nadav Amit | 8265363 | 2010-04-01 13:24:40 +0300 | [diff] [blame] | 1377 | if (!cap_caching_mode(iommu->cap) || !map) |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1378 | iommu_flush_dev_iotlb(iommu->domains[did], addr, mask); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1379 | } |
| 1380 | |
mark gross | f8bab73 | 2008-02-08 04:18:38 -0800 | [diff] [blame] | 1381 | static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu) |
| 1382 | { |
| 1383 | u32 pmen; |
| 1384 | unsigned long flags; |
| 1385 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1386 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
mark gross | f8bab73 | 2008-02-08 04:18:38 -0800 | [diff] [blame] | 1387 | pmen = readl(iommu->reg + DMAR_PMEN_REG); |
| 1388 | pmen &= ~DMA_PMEN_EPM; |
| 1389 | writel(pmen, iommu->reg + DMAR_PMEN_REG); |
| 1390 | |
| 1391 | /* wait for the protected region status bit to clear */ |
| 1392 | IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG, |
| 1393 | readl, !(pmen & DMA_PMEN_PRS), pmen); |
| 1394 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1395 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
mark gross | f8bab73 | 2008-02-08 04:18:38 -0800 | [diff] [blame] | 1396 | } |
| 1397 | |
Jiang Liu | 2a41cce | 2014-07-11 14:19:33 +0800 | [diff] [blame] | 1398 | static void iommu_enable_translation(struct intel_iommu *iommu) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1399 | { |
| 1400 | u32 sts; |
| 1401 | unsigned long flags; |
| 1402 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1403 | raw_spin_lock_irqsave(&iommu->register_lock, flags); |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1404 | iommu->gcmd |= DMA_GCMD_TE; |
| 1405 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1406 | |
| 1407 | /* Make sure hardware complete it */ |
| 1408 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1409 | readl, (sts & DMA_GSTS_TES), sts); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1410 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1411 | raw_spin_unlock_irqrestore(&iommu->register_lock, flags); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1412 | } |
| 1413 | |
Jiang Liu | 2a41cce | 2014-07-11 14:19:33 +0800 | [diff] [blame] | 1414 | static void iommu_disable_translation(struct intel_iommu *iommu) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1415 | { |
| 1416 | u32 sts; |
| 1417 | unsigned long flag; |
| 1418 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1419 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1420 | iommu->gcmd &= ~DMA_GCMD_TE; |
| 1421 | writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); |
| 1422 | |
| 1423 | /* Make sure hardware complete it */ |
| 1424 | IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, |
David Woodhouse | c416daa | 2009-05-10 20:30:58 +0100 | [diff] [blame] | 1425 | readl, (!(sts & DMA_GSTS_TES)), sts); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1426 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 1427 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1428 | } |
| 1429 | |
Keshavamurthy, Anil S | 3460a6d | 2007-10-21 16:41:54 -0700 | [diff] [blame] | 1430 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1431 | static int iommu_init_domains(struct intel_iommu *iommu) |
| 1432 | { |
| 1433 | unsigned long ndomains; |
| 1434 | unsigned long nlongs; |
| 1435 | |
| 1436 | ndomains = cap_ndoms(iommu->cap); |
Jiang Liu | 852bdb0 | 2014-01-06 14:18:11 +0800 | [diff] [blame] | 1437 | pr_debug("IOMMU%d: Number of Domains supported <%ld>\n", |
| 1438 | iommu->seq_id, ndomains); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1439 | nlongs = BITS_TO_LONGS(ndomains); |
| 1440 | |
Donald Dutile | 94a91b5 | 2009-08-20 16:51:34 -0400 | [diff] [blame] | 1441 | spin_lock_init(&iommu->lock); |
| 1442 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1443 | /* TBD: there might be 64K domains, |
| 1444 | * consider other allocation for future chip |
| 1445 | */ |
| 1446 | iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL); |
| 1447 | if (!iommu->domain_ids) { |
Jiang Liu | 852bdb0 | 2014-01-06 14:18:11 +0800 | [diff] [blame] | 1448 | pr_err("IOMMU%d: allocating domain id array failed\n", |
| 1449 | iommu->seq_id); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1450 | return -ENOMEM; |
| 1451 | } |
| 1452 | iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *), |
| 1453 | GFP_KERNEL); |
| 1454 | if (!iommu->domains) { |
Jiang Liu | 852bdb0 | 2014-01-06 14:18:11 +0800 | [diff] [blame] | 1455 | pr_err("IOMMU%d: allocating domain array failed\n", |
| 1456 | iommu->seq_id); |
| 1457 | kfree(iommu->domain_ids); |
| 1458 | iommu->domain_ids = NULL; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1459 | return -ENOMEM; |
| 1460 | } |
| 1461 | |
| 1462 | /* |
| 1463 | * if Caching mode is set, then invalid translations are tagged |
| 1464 | * with domainid 0. Hence we need to pre-allocate it. |
| 1465 | */ |
| 1466 | if (cap_caching_mode(iommu->cap)) |
| 1467 | set_bit(0, iommu->domain_ids); |
| 1468 | return 0; |
| 1469 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1470 | |
Jiang Liu | a868e6b | 2014-01-06 14:18:20 +0800 | [diff] [blame] | 1471 | static void free_dmar_iommu(struct intel_iommu *iommu) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1472 | { |
| 1473 | struct dmar_domain *domain; |
Jiang Liu | 2a46ddf | 2014-07-11 14:19:30 +0800 | [diff] [blame] | 1474 | int i; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1475 | |
Donald Dutile | 94a91b5 | 2009-08-20 16:51:34 -0400 | [diff] [blame] | 1476 | if ((iommu->domains) && (iommu->domain_ids)) { |
Akinobu Mita | a45946a | 2010-03-11 14:04:08 -0800 | [diff] [blame] | 1477 | for_each_set_bit(i, iommu->domain_ids, cap_ndoms(iommu->cap)) { |
Jiang Liu | a4eaa86 | 2014-02-19 14:07:30 +0800 | [diff] [blame] | 1478 | /* |
| 1479 | * Domain id 0 is reserved for invalid translation |
| 1480 | * if hardware supports caching mode. |
| 1481 | */ |
| 1482 | if (cap_caching_mode(iommu->cap) && i == 0) |
| 1483 | continue; |
| 1484 | |
Donald Dutile | 94a91b5 | 2009-08-20 16:51:34 -0400 | [diff] [blame] | 1485 | domain = iommu->domains[i]; |
| 1486 | clear_bit(i, iommu->domain_ids); |
Jiang Liu | 129ad28 | 2014-07-11 14:19:31 +0800 | [diff] [blame] | 1487 | if (domain_detach_iommu(domain, iommu) == 0 && |
| 1488 | !domain_type_is_vm(domain)) |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 1489 | domain_exit(domain); |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 1490 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1491 | } |
| 1492 | |
| 1493 | if (iommu->gcmd & DMA_GCMD_TE) |
| 1494 | iommu_disable_translation(iommu); |
| 1495 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1496 | kfree(iommu->domains); |
| 1497 | kfree(iommu->domain_ids); |
Jiang Liu | a868e6b | 2014-01-06 14:18:20 +0800 | [diff] [blame] | 1498 | iommu->domains = NULL; |
| 1499 | iommu->domain_ids = NULL; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1500 | |
Weidong Han | d9630fe | 2008-12-08 11:06:32 +0800 | [diff] [blame] | 1501 | g_iommus[iommu->seq_id] = NULL; |
| 1502 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1503 | /* free context mapping */ |
| 1504 | free_context_table(iommu); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1505 | } |
| 1506 | |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 1507 | static struct dmar_domain *alloc_domain(int flags) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1508 | { |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 1509 | /* domain id for virtual machine, it won't be set in context */ |
| 1510 | static atomic_t vm_domid = ATOMIC_INIT(0); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1511 | struct dmar_domain *domain; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1512 | |
| 1513 | domain = alloc_domain_mem(); |
| 1514 | if (!domain) |
| 1515 | return NULL; |
| 1516 | |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 1517 | memset(domain, 0, sizeof(*domain)); |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 1518 | domain->nid = -1; |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 1519 | domain->flags = flags; |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 1520 | spin_lock_init(&domain->iommu_lock); |
| 1521 | INIT_LIST_HEAD(&domain->devices); |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 1522 | if (flags & DOMAIN_FLAG_VIRTUAL_MACHINE) |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 1523 | domain->id = atomic_inc_return(&vm_domid); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1524 | |
| 1525 | return domain; |
| 1526 | } |
| 1527 | |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 1528 | static int __iommu_attach_domain(struct dmar_domain *domain, |
| 1529 | struct intel_iommu *iommu) |
| 1530 | { |
| 1531 | int num; |
| 1532 | unsigned long ndomains; |
| 1533 | |
| 1534 | ndomains = cap_ndoms(iommu->cap); |
| 1535 | num = find_first_zero_bit(iommu->domain_ids, ndomains); |
| 1536 | if (num < ndomains) { |
| 1537 | set_bit(num, iommu->domain_ids); |
| 1538 | iommu->domains[num] = domain; |
| 1539 | } else { |
| 1540 | num = -ENOSPC; |
| 1541 | } |
| 1542 | |
| 1543 | return num; |
| 1544 | } |
| 1545 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1546 | static int iommu_attach_domain(struct dmar_domain *domain, |
| 1547 | struct intel_iommu *iommu) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1548 | { |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1549 | int num; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1550 | unsigned long flags; |
| 1551 | |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 1552 | spin_lock_irqsave(&iommu->lock, flags); |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 1553 | num = __iommu_attach_domain(domain, iommu); |
Jiang Liu | 44bde61 | 2014-07-11 14:19:29 +0800 | [diff] [blame] | 1554 | spin_unlock_irqrestore(&iommu->lock, flags); |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 1555 | if (num < 0) |
| 1556 | pr_err("IOMMU: no free domain ids\n"); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1557 | |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 1558 | return num; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1559 | } |
| 1560 | |
Jiang Liu | 44bde61 | 2014-07-11 14:19:29 +0800 | [diff] [blame] | 1561 | static int iommu_attach_vm_domain(struct dmar_domain *domain, |
| 1562 | struct intel_iommu *iommu) |
| 1563 | { |
| 1564 | int num; |
| 1565 | unsigned long ndomains; |
| 1566 | |
| 1567 | ndomains = cap_ndoms(iommu->cap); |
| 1568 | for_each_set_bit(num, iommu->domain_ids, ndomains) |
| 1569 | if (iommu->domains[num] == domain) |
| 1570 | return num; |
| 1571 | |
| 1572 | return __iommu_attach_domain(domain, iommu); |
| 1573 | } |
| 1574 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1575 | static void iommu_detach_domain(struct dmar_domain *domain, |
| 1576 | struct intel_iommu *iommu) |
| 1577 | { |
| 1578 | unsigned long flags; |
| 1579 | int num, ndomains; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1580 | |
| 1581 | spin_lock_irqsave(&iommu->lock, flags); |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 1582 | if (domain_type_is_vm_or_si(domain)) { |
| 1583 | ndomains = cap_ndoms(iommu->cap); |
| 1584 | for_each_set_bit(num, iommu->domain_ids, ndomains) { |
| 1585 | if (iommu->domains[num] == domain) { |
| 1586 | clear_bit(num, iommu->domain_ids); |
| 1587 | iommu->domains[num] = NULL; |
| 1588 | break; |
| 1589 | } |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1590 | } |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 1591 | } else { |
| 1592 | clear_bit(domain->id, iommu->domain_ids); |
| 1593 | iommu->domains[domain->id] = NULL; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1594 | } |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 1595 | spin_unlock_irqrestore(&iommu->lock, flags); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1596 | } |
| 1597 | |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 1598 | static void domain_attach_iommu(struct dmar_domain *domain, |
| 1599 | struct intel_iommu *iommu) |
| 1600 | { |
| 1601 | unsigned long flags; |
| 1602 | |
| 1603 | spin_lock_irqsave(&domain->iommu_lock, flags); |
| 1604 | if (!test_and_set_bit(iommu->seq_id, domain->iommu_bmp)) { |
| 1605 | domain->iommu_count++; |
| 1606 | if (domain->iommu_count == 1) |
| 1607 | domain->nid = iommu->node; |
| 1608 | domain_update_iommu_cap(domain); |
| 1609 | } |
| 1610 | spin_unlock_irqrestore(&domain->iommu_lock, flags); |
| 1611 | } |
| 1612 | |
| 1613 | static int domain_detach_iommu(struct dmar_domain *domain, |
| 1614 | struct intel_iommu *iommu) |
| 1615 | { |
| 1616 | unsigned long flags; |
| 1617 | int count = INT_MAX; |
| 1618 | |
| 1619 | spin_lock_irqsave(&domain->iommu_lock, flags); |
| 1620 | if (test_and_clear_bit(iommu->seq_id, domain->iommu_bmp)) { |
| 1621 | count = --domain->iommu_count; |
| 1622 | domain_update_iommu_cap(domain); |
| 1623 | } |
| 1624 | spin_unlock_irqrestore(&domain->iommu_lock, flags); |
| 1625 | |
| 1626 | return count; |
| 1627 | } |
| 1628 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1629 | static struct iova_domain reserved_iova_list; |
Mark Gross | 8a443df | 2008-03-04 14:59:31 -0800 | [diff] [blame] | 1630 | static struct lock_class_key reserved_rbtree_key; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1631 | |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 1632 | static int dmar_init_reserved_ranges(void) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1633 | { |
| 1634 | struct pci_dev *pdev = NULL; |
| 1635 | struct iova *iova; |
| 1636 | int i; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1637 | |
David Miller | f661197 | 2008-02-06 01:36:23 -0800 | [diff] [blame] | 1638 | init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1639 | |
Mark Gross | 8a443df | 2008-03-04 14:59:31 -0800 | [diff] [blame] | 1640 | lockdep_set_class(&reserved_iova_list.iova_rbtree_lock, |
| 1641 | &reserved_rbtree_key); |
| 1642 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1643 | /* IOAPIC ranges shouldn't be accessed by DMA */ |
| 1644 | iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START), |
| 1645 | IOVA_PFN(IOAPIC_RANGE_END)); |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 1646 | if (!iova) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1647 | printk(KERN_ERR "Reserve IOAPIC range failed\n"); |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 1648 | return -ENODEV; |
| 1649 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1650 | |
| 1651 | /* Reserve all PCI MMIO to avoid peer-to-peer access */ |
| 1652 | for_each_pci_dev(pdev) { |
| 1653 | struct resource *r; |
| 1654 | |
| 1655 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
| 1656 | r = &pdev->resource[i]; |
| 1657 | if (!r->flags || !(r->flags & IORESOURCE_MEM)) |
| 1658 | continue; |
David Woodhouse | 1a4a455 | 2009-06-28 16:00:42 +0100 | [diff] [blame] | 1659 | iova = reserve_iova(&reserved_iova_list, |
| 1660 | IOVA_PFN(r->start), |
| 1661 | IOVA_PFN(r->end)); |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 1662 | if (!iova) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1663 | printk(KERN_ERR "Reserve iova failed\n"); |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 1664 | return -ENODEV; |
| 1665 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1666 | } |
| 1667 | } |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 1668 | return 0; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1669 | } |
| 1670 | |
| 1671 | static void domain_reserve_special_ranges(struct dmar_domain *domain) |
| 1672 | { |
| 1673 | copy_reserved_iova(&reserved_iova_list, &domain->iovad); |
| 1674 | } |
| 1675 | |
| 1676 | static inline int guestwidth_to_adjustwidth(int gaw) |
| 1677 | { |
| 1678 | int agaw; |
| 1679 | int r = (gaw - 12) % 9; |
| 1680 | |
| 1681 | if (r == 0) |
| 1682 | agaw = gaw; |
| 1683 | else |
| 1684 | agaw = gaw + 9 - r; |
| 1685 | if (agaw > 64) |
| 1686 | agaw = 64; |
| 1687 | return agaw; |
| 1688 | } |
| 1689 | |
| 1690 | static int domain_init(struct dmar_domain *domain, int guest_width) |
| 1691 | { |
| 1692 | struct intel_iommu *iommu; |
| 1693 | int adjust_width, agaw; |
| 1694 | unsigned long sagaw; |
| 1695 | |
David Miller | f661197 | 2008-02-06 01:36:23 -0800 | [diff] [blame] | 1696 | init_iova_domain(&domain->iovad, DMA_32BIT_PFN); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1697 | domain_reserve_special_ranges(domain); |
| 1698 | |
| 1699 | /* calculate AGAW */ |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 1700 | iommu = domain_get_iommu(domain); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1701 | if (guest_width > cap_mgaw(iommu->cap)) |
| 1702 | guest_width = cap_mgaw(iommu->cap); |
| 1703 | domain->gaw = guest_width; |
| 1704 | adjust_width = guestwidth_to_adjustwidth(guest_width); |
| 1705 | agaw = width_to_agaw(adjust_width); |
| 1706 | sagaw = cap_sagaw(iommu->cap); |
| 1707 | if (!test_bit(agaw, &sagaw)) { |
| 1708 | /* hardware doesn't support it, choose a bigger one */ |
| 1709 | pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw); |
| 1710 | agaw = find_next_bit(&sagaw, 5, agaw); |
| 1711 | if (agaw >= 5) |
| 1712 | return -ENODEV; |
| 1713 | } |
| 1714 | domain->agaw = agaw; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1715 | |
Weidong Han | 8e604097 | 2008-12-08 15:49:06 +0800 | [diff] [blame] | 1716 | if (ecap_coherent(iommu->ecap)) |
| 1717 | domain->iommu_coherency = 1; |
| 1718 | else |
| 1719 | domain->iommu_coherency = 0; |
| 1720 | |
Sheng Yang | 58c610b | 2009-03-18 15:33:05 +0800 | [diff] [blame] | 1721 | if (ecap_sc_support(iommu->ecap)) |
| 1722 | domain->iommu_snooping = 1; |
| 1723 | else |
| 1724 | domain->iommu_snooping = 0; |
| 1725 | |
David Woodhouse | 214e39a | 2014-03-19 10:38:49 +0000 | [diff] [blame] | 1726 | if (intel_iommu_superpage) |
| 1727 | domain->iommu_superpage = fls(cap_super_page_val(iommu->cap)); |
| 1728 | else |
| 1729 | domain->iommu_superpage = 0; |
| 1730 | |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 1731 | domain->nid = iommu->node; |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 1732 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1733 | /* always allocate the top pgd */ |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 1734 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1735 | if (!domain->pgd) |
| 1736 | return -ENOMEM; |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 1737 | __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1738 | return 0; |
| 1739 | } |
| 1740 | |
| 1741 | static void domain_exit(struct dmar_domain *domain) |
| 1742 | { |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1743 | struct dmar_drhd_unit *drhd; |
| 1744 | struct intel_iommu *iommu; |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1745 | struct page *freelist = NULL; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1746 | |
| 1747 | /* Domain 0 is reserved, so dont process it */ |
| 1748 | if (!domain) |
| 1749 | return; |
| 1750 | |
Alex Williamson | 7b66835 | 2011-05-24 12:02:41 +0100 | [diff] [blame] | 1751 | /* Flush any lazy unmaps that may reference this domain */ |
| 1752 | if (!intel_iommu_strict) |
| 1753 | flush_unmaps_timeout(0); |
| 1754 | |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 1755 | /* remove associated devices */ |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1756 | domain_remove_dev_info(domain); |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 1757 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1758 | /* destroy iovas */ |
| 1759 | put_iova_domain(&domain->iovad); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1760 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1761 | freelist = domain_unmap(domain, 0, DOMAIN_MAX_PFN(domain->gaw)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1762 | |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 1763 | /* clear attached or cached domains */ |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 1764 | rcu_read_lock(); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1765 | for_each_active_iommu(iommu, drhd) |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 1766 | iommu_detach_domain(domain, iommu); |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 1767 | rcu_read_unlock(); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 1768 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 1769 | dma_free_pagelist(freelist); |
| 1770 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1771 | free_domain_mem(domain); |
| 1772 | } |
| 1773 | |
David Woodhouse | 64ae892 | 2014-03-09 12:52:30 -0700 | [diff] [blame] | 1774 | static int domain_context_mapping_one(struct dmar_domain *domain, |
| 1775 | struct intel_iommu *iommu, |
| 1776 | u8 bus, u8 devfn, int translation) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1777 | { |
| 1778 | struct context_entry *context; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1779 | unsigned long flags; |
Weidong Han | ea6606b | 2008-12-08 23:08:15 +0800 | [diff] [blame] | 1780 | struct dma_pte *pgd; |
Weidong Han | ea6606b | 2008-12-08 23:08:15 +0800 | [diff] [blame] | 1781 | int id; |
| 1782 | int agaw; |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1783 | struct device_domain_info *info = NULL; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1784 | |
| 1785 | pr_debug("Set context mapping for %02x:%02x.%d\n", |
| 1786 | bus, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1787 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1788 | BUG_ON(!domain->pgd); |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1789 | BUG_ON(translation != CONTEXT_TT_PASS_THROUGH && |
| 1790 | translation != CONTEXT_TT_MULTI_LEVEL); |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 1791 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1792 | context = device_to_context_entry(iommu, bus, devfn); |
| 1793 | if (!context) |
| 1794 | return -ENOMEM; |
| 1795 | spin_lock_irqsave(&iommu->lock, flags); |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 1796 | if (context_present(context)) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1797 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 1798 | return 0; |
| 1799 | } |
| 1800 | |
Weidong Han | ea6606b | 2008-12-08 23:08:15 +0800 | [diff] [blame] | 1801 | id = domain->id; |
| 1802 | pgd = domain->pgd; |
| 1803 | |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 1804 | if (domain_type_is_vm_or_si(domain)) { |
Jiang Liu | 44bde61 | 2014-07-11 14:19:29 +0800 | [diff] [blame] | 1805 | if (domain_type_is_vm(domain)) { |
| 1806 | id = iommu_attach_vm_domain(domain, iommu); |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 1807 | if (id < 0) { |
Weidong Han | ea6606b | 2008-12-08 23:08:15 +0800 | [diff] [blame] | 1808 | spin_unlock_irqrestore(&iommu->lock, flags); |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 1809 | pr_err("IOMMU: no free domain ids\n"); |
Weidong Han | ea6606b | 2008-12-08 23:08:15 +0800 | [diff] [blame] | 1810 | return -EFAULT; |
| 1811 | } |
Weidong Han | ea6606b | 2008-12-08 23:08:15 +0800 | [diff] [blame] | 1812 | } |
| 1813 | |
| 1814 | /* Skip top levels of page tables for |
| 1815 | * iommu which has less agaw than default. |
Chris Wright | 1672af1 | 2009-12-02 12:06:34 -0800 | [diff] [blame] | 1816 | * Unnecessary for PT mode. |
Weidong Han | ea6606b | 2008-12-08 23:08:15 +0800 | [diff] [blame] | 1817 | */ |
Chris Wright | 1672af1 | 2009-12-02 12:06:34 -0800 | [diff] [blame] | 1818 | if (translation != CONTEXT_TT_PASS_THROUGH) { |
| 1819 | for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) { |
| 1820 | pgd = phys_to_virt(dma_pte_addr(pgd)); |
| 1821 | if (!dma_pte_present(pgd)) { |
| 1822 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 1823 | return -ENOMEM; |
| 1824 | } |
Weidong Han | ea6606b | 2008-12-08 23:08:15 +0800 | [diff] [blame] | 1825 | } |
| 1826 | } |
| 1827 | } |
| 1828 | |
| 1829 | context_set_domain_id(context, id); |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1830 | |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1831 | if (translation != CONTEXT_TT_PASS_THROUGH) { |
David Woodhouse | 64ae892 | 2014-03-09 12:52:30 -0700 | [diff] [blame] | 1832 | info = iommu_support_dev_iotlb(domain, iommu, bus, devfn); |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1833 | translation = info ? CONTEXT_TT_DEV_IOTLB : |
| 1834 | CONTEXT_TT_MULTI_LEVEL; |
| 1835 | } |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1836 | /* |
| 1837 | * In pass through mode, AW must be programmed to indicate the largest |
| 1838 | * AGAW value supported by hardware. And ASR is ignored by hardware. |
| 1839 | */ |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1840 | if (unlikely(translation == CONTEXT_TT_PASS_THROUGH)) |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1841 | context_set_address_width(context, iommu->msagaw); |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1842 | else { |
| 1843 | context_set_address_root(context, virt_to_phys(pgd)); |
| 1844 | context_set_address_width(context, iommu->agaw); |
| 1845 | } |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1846 | |
| 1847 | context_set_translation_type(context, translation); |
Mark McLoughlin | c07e7d2 | 2008-11-21 16:54:46 +0000 | [diff] [blame] | 1848 | context_set_fault_enable(context); |
| 1849 | context_set_present(context); |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 1850 | domain_flush_cache(domain, context, sizeof(*context)); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1851 | |
David Woodhouse | 4c25a2c | 2009-05-10 17:16:06 +0100 | [diff] [blame] | 1852 | /* |
| 1853 | * It's a non-present to present mapping. If hardware doesn't cache |
| 1854 | * non-present entry we only need to flush the write-buffer. If the |
| 1855 | * _does_ cache non-present entries, then it does so in the special |
| 1856 | * domain #0, which we have to flush: |
| 1857 | */ |
| 1858 | if (cap_caching_mode(iommu->cap)) { |
| 1859 | iommu->flush.flush_context(iommu, 0, |
| 1860 | (((u16)bus) << 8) | devfn, |
| 1861 | DMA_CCMD_MASK_NOBIT, |
| 1862 | DMA_CCMD_DEVICE_INVL); |
Jiang Liu | 18fd779 | 2014-07-11 14:19:26 +0800 | [diff] [blame] | 1863 | iommu->flush.flush_iotlb(iommu, id, 0, 0, DMA_TLB_DSI_FLUSH); |
David Woodhouse | 4c25a2c | 2009-05-10 17:16:06 +0100 | [diff] [blame] | 1864 | } else { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1865 | iommu_flush_write_buffer(iommu); |
David Woodhouse | 4c25a2c | 2009-05-10 17:16:06 +0100 | [diff] [blame] | 1866 | } |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 1867 | iommu_enable_dev_iotlb(info); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1868 | spin_unlock_irqrestore(&iommu->lock, flags); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 1869 | |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 1870 | domain_attach_iommu(domain, iommu); |
| 1871 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1872 | return 0; |
| 1873 | } |
| 1874 | |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 1875 | struct domain_context_mapping_data { |
| 1876 | struct dmar_domain *domain; |
| 1877 | struct intel_iommu *iommu; |
| 1878 | int translation; |
| 1879 | }; |
| 1880 | |
| 1881 | static int domain_context_mapping_cb(struct pci_dev *pdev, |
| 1882 | u16 alias, void *opaque) |
| 1883 | { |
| 1884 | struct domain_context_mapping_data *data = opaque; |
| 1885 | |
| 1886 | return domain_context_mapping_one(data->domain, data->iommu, |
| 1887 | PCI_BUS_NUM(alias), alias & 0xff, |
| 1888 | data->translation); |
| 1889 | } |
| 1890 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1891 | static int |
David Woodhouse | e1f167f | 2014-03-09 15:24:46 -0700 | [diff] [blame] | 1892 | domain_context_mapping(struct dmar_domain *domain, struct device *dev, |
| 1893 | int translation) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1894 | { |
David Woodhouse | 64ae892 | 2014-03-09 12:52:30 -0700 | [diff] [blame] | 1895 | struct intel_iommu *iommu; |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 1896 | u8 bus, devfn; |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 1897 | struct domain_context_mapping_data data; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1898 | |
David Woodhouse | e1f167f | 2014-03-09 15:24:46 -0700 | [diff] [blame] | 1899 | iommu = device_to_iommu(dev, &bus, &devfn); |
David Woodhouse | 64ae892 | 2014-03-09 12:52:30 -0700 | [diff] [blame] | 1900 | if (!iommu) |
| 1901 | return -ENODEV; |
| 1902 | |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 1903 | if (!dev_is_pci(dev)) |
| 1904 | return domain_context_mapping_one(domain, iommu, bus, devfn, |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 1905 | translation); |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 1906 | |
| 1907 | data.domain = domain; |
| 1908 | data.iommu = iommu; |
| 1909 | data.translation = translation; |
| 1910 | |
| 1911 | return pci_for_each_dma_alias(to_pci_dev(dev), |
| 1912 | &domain_context_mapping_cb, &data); |
| 1913 | } |
| 1914 | |
| 1915 | static int domain_context_mapped_cb(struct pci_dev *pdev, |
| 1916 | u16 alias, void *opaque) |
| 1917 | { |
| 1918 | struct intel_iommu *iommu = opaque; |
| 1919 | |
| 1920 | return !device_context_mapped(iommu, PCI_BUS_NUM(alias), alias & 0xff); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1921 | } |
| 1922 | |
David Woodhouse | e1f167f | 2014-03-09 15:24:46 -0700 | [diff] [blame] | 1923 | static int domain_context_mapped(struct device *dev) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1924 | { |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 1925 | struct intel_iommu *iommu; |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 1926 | u8 bus, devfn; |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 1927 | |
David Woodhouse | e1f167f | 2014-03-09 15:24:46 -0700 | [diff] [blame] | 1928 | iommu = device_to_iommu(dev, &bus, &devfn); |
Weidong Han | 5331fe6 | 2008-12-08 23:00:00 +0800 | [diff] [blame] | 1929 | if (!iommu) |
| 1930 | return -ENODEV; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1931 | |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 1932 | if (!dev_is_pci(dev)) |
| 1933 | return device_context_mapped(iommu, bus, devfn); |
David Woodhouse | e1f167f | 2014-03-09 15:24:46 -0700 | [diff] [blame] | 1934 | |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 1935 | return !pci_for_each_dma_alias(to_pci_dev(dev), |
| 1936 | domain_context_mapped_cb, iommu); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 1937 | } |
| 1938 | |
Fenghua Yu | f532959 | 2009-08-04 15:09:37 -0700 | [diff] [blame] | 1939 | /* Returns a number of VTD pages, but aligned to MM page size */ |
| 1940 | static inline unsigned long aligned_nrpages(unsigned long host_addr, |
| 1941 | size_t size) |
| 1942 | { |
| 1943 | host_addr &= ~PAGE_MASK; |
| 1944 | return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT; |
| 1945 | } |
| 1946 | |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1947 | /* Return largest possible superpage level for a given mapping */ |
| 1948 | static inline int hardware_largepage_caps(struct dmar_domain *domain, |
| 1949 | unsigned long iov_pfn, |
| 1950 | unsigned long phy_pfn, |
| 1951 | unsigned long pages) |
| 1952 | { |
| 1953 | int support, level = 1; |
| 1954 | unsigned long pfnmerge; |
| 1955 | |
| 1956 | support = domain->iommu_superpage; |
| 1957 | |
| 1958 | /* To use a large page, the virtual *and* physical addresses |
| 1959 | must be aligned to 2MiB/1GiB/etc. Lower bits set in either |
| 1960 | of them will mean we have to use smaller pages. So just |
| 1961 | merge them and check both at once. */ |
| 1962 | pfnmerge = iov_pfn | phy_pfn; |
| 1963 | |
| 1964 | while (support && !(pfnmerge & ~VTD_STRIDE_MASK)) { |
| 1965 | pages >>= VTD_STRIDE_SHIFT; |
| 1966 | if (!pages) |
| 1967 | break; |
| 1968 | pfnmerge >>= VTD_STRIDE_SHIFT; |
| 1969 | level++; |
| 1970 | support--; |
| 1971 | } |
| 1972 | return level; |
| 1973 | } |
| 1974 | |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 1975 | static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
| 1976 | struct scatterlist *sg, unsigned long phys_pfn, |
| 1977 | unsigned long nr_pages, int prot) |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 1978 | { |
| 1979 | struct dma_pte *first_pte = NULL, *pte = NULL; |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 1980 | phys_addr_t uninitialized_var(pteval); |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 1981 | unsigned long sg_res; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1982 | unsigned int largepage_lvl = 0; |
| 1983 | unsigned long lvl_pages = 0; |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 1984 | |
Jiang Liu | 162d1b1 | 2014-07-11 14:19:35 +0800 | [diff] [blame] | 1985 | BUG_ON(!domain_pfn_supported(domain, iov_pfn + nr_pages - 1)); |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 1986 | |
| 1987 | if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0) |
| 1988 | return -EINVAL; |
| 1989 | |
| 1990 | prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP; |
| 1991 | |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 1992 | if (sg) |
| 1993 | sg_res = 0; |
| 1994 | else { |
| 1995 | sg_res = nr_pages + 1; |
| 1996 | pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot; |
| 1997 | } |
| 1998 | |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 1999 | while (nr_pages > 0) { |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 2000 | uint64_t tmp; |
| 2001 | |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2002 | if (!sg_res) { |
Fenghua Yu | f532959 | 2009-08-04 15:09:37 -0700 | [diff] [blame] | 2003 | sg_res = aligned_nrpages(sg->offset, sg->length); |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2004 | sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset; |
| 2005 | sg->dma_length = sg->length; |
| 2006 | pteval = page_to_phys(sg_page(sg)) | prot; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2007 | phys_pfn = pteval >> VTD_PAGE_SHIFT; |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2008 | } |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2009 | |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2010 | if (!pte) { |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2011 | largepage_lvl = hardware_largepage_caps(domain, iov_pfn, phys_pfn, sg_res); |
| 2012 | |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 2013 | first_pte = pte = pfn_to_dma_pte(domain, iov_pfn, &largepage_lvl); |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2014 | if (!pte) |
| 2015 | return -ENOMEM; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2016 | /* It is large page*/ |
Woodhouse, David | 6491d4d | 2012-12-19 13:25:35 +0000 | [diff] [blame] | 2017 | if (largepage_lvl > 1) { |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2018 | pteval |= DMA_PTE_LARGE_PAGE; |
Jiang Liu | d41a4ad | 2014-07-11 14:19:34 +0800 | [diff] [blame] | 2019 | lvl_pages = lvl_to_nr_pages(largepage_lvl); |
| 2020 | /* |
| 2021 | * Ensure that old small page tables are |
| 2022 | * removed to make room for superpage, |
| 2023 | * if they exist. |
| 2024 | */ |
Woodhouse, David | 6491d4d | 2012-12-19 13:25:35 +0000 | [diff] [blame] | 2025 | dma_pte_free_pagetable(domain, iov_pfn, |
Jiang Liu | d41a4ad | 2014-07-11 14:19:34 +0800 | [diff] [blame] | 2026 | iov_pfn + lvl_pages - 1); |
Woodhouse, David | 6491d4d | 2012-12-19 13:25:35 +0000 | [diff] [blame] | 2027 | } else { |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2028 | pteval &= ~(uint64_t)DMA_PTE_LARGE_PAGE; |
Woodhouse, David | 6491d4d | 2012-12-19 13:25:35 +0000 | [diff] [blame] | 2029 | } |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2030 | |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2031 | } |
| 2032 | /* We don't need lock here, nobody else |
| 2033 | * touches the iova range |
| 2034 | */ |
David Woodhouse | 7766a3f | 2009-07-01 20:27:03 +0100 | [diff] [blame] | 2035 | tmp = cmpxchg64_local(&pte->val, 0ULL, pteval); |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 2036 | if (tmp) { |
David Woodhouse | 1bf20f0 | 2009-06-29 22:06:43 +0100 | [diff] [blame] | 2037 | static int dumps = 5; |
David Woodhouse | c85994e | 2009-07-01 19:21:24 +0100 | [diff] [blame] | 2038 | printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n", |
| 2039 | iov_pfn, tmp, (unsigned long long)pteval); |
David Woodhouse | 1bf20f0 | 2009-06-29 22:06:43 +0100 | [diff] [blame] | 2040 | if (dumps) { |
| 2041 | dumps--; |
| 2042 | debug_dma_dump_mappings(NULL); |
| 2043 | } |
| 2044 | WARN_ON(1); |
| 2045 | } |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2046 | |
| 2047 | lvl_pages = lvl_to_nr_pages(largepage_lvl); |
| 2048 | |
| 2049 | BUG_ON(nr_pages < lvl_pages); |
| 2050 | BUG_ON(sg_res < lvl_pages); |
| 2051 | |
| 2052 | nr_pages -= lvl_pages; |
| 2053 | iov_pfn += lvl_pages; |
| 2054 | phys_pfn += lvl_pages; |
| 2055 | pteval += lvl_pages * VTD_PAGE_SIZE; |
| 2056 | sg_res -= lvl_pages; |
| 2057 | |
| 2058 | /* If the next PTE would be the first in a new page, then we |
| 2059 | need to flush the cache on the entries we've just written. |
| 2060 | And then we'll need to recalculate 'pte', so clear it and |
| 2061 | let it get set again in the if (!pte) block above. |
| 2062 | |
| 2063 | If we're done (!nr_pages) we need to flush the cache too. |
| 2064 | |
| 2065 | Also if we've been setting superpages, we may need to |
| 2066 | recalculate 'pte' and switch back to smaller pages for the |
| 2067 | end of the mapping, if the trailing size is not enough to |
| 2068 | use another superpage (i.e. sg_res < lvl_pages). */ |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2069 | pte++; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2070 | if (!nr_pages || first_pte_in_page(pte) || |
| 2071 | (largepage_lvl > 1 && sg_res < lvl_pages)) { |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2072 | domain_flush_cache(domain, first_pte, |
| 2073 | (void *)pte - (void *)first_pte); |
| 2074 | pte = NULL; |
| 2075 | } |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 2076 | |
| 2077 | if (!sg_res && nr_pages) |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 2078 | sg = sg_next(sg); |
| 2079 | } |
| 2080 | return 0; |
| 2081 | } |
| 2082 | |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 2083 | static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
| 2084 | struct scatterlist *sg, unsigned long nr_pages, |
| 2085 | int prot) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2086 | { |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 2087 | return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot); |
| 2088 | } |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 2089 | |
David Woodhouse | 9051aa0 | 2009-06-29 12:30:54 +0100 | [diff] [blame] | 2090 | static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn, |
| 2091 | unsigned long phys_pfn, unsigned long nr_pages, |
| 2092 | int prot) |
| 2093 | { |
| 2094 | return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2095 | } |
| 2096 | |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 2097 | static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2098 | { |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 2099 | if (!iommu) |
| 2100 | return; |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 2101 | |
| 2102 | clear_context_table(iommu, bus, devfn); |
| 2103 | iommu->flush.flush_context(iommu, 0, 0, 0, |
David Woodhouse | 4c25a2c | 2009-05-10 17:16:06 +0100 | [diff] [blame] | 2104 | DMA_CCMD_GLOBAL_INVL); |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 2105 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2106 | } |
| 2107 | |
David Woodhouse | 109b9b0 | 2012-05-25 17:43:02 +0100 | [diff] [blame] | 2108 | static inline void unlink_domain_info(struct device_domain_info *info) |
| 2109 | { |
| 2110 | assert_spin_locked(&device_domain_lock); |
| 2111 | list_del(&info->link); |
| 2112 | list_del(&info->global); |
| 2113 | if (info->dev) |
David Woodhouse | 0bcb3e2 | 2014-03-06 17:12:03 +0000 | [diff] [blame] | 2114 | info->dev->archdata.iommu = NULL; |
David Woodhouse | 109b9b0 | 2012-05-25 17:43:02 +0100 | [diff] [blame] | 2115 | } |
| 2116 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2117 | static void domain_remove_dev_info(struct dmar_domain *domain) |
| 2118 | { |
Yijing Wang | 3a74ca0 | 2014-05-20 20:37:47 +0800 | [diff] [blame] | 2119 | struct device_domain_info *info, *tmp; |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 2120 | unsigned long flags; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2121 | |
| 2122 | spin_lock_irqsave(&device_domain_lock, flags); |
Yijing Wang | 3a74ca0 | 2014-05-20 20:37:47 +0800 | [diff] [blame] | 2123 | list_for_each_entry_safe(info, tmp, &domain->devices, link) { |
David Woodhouse | 109b9b0 | 2012-05-25 17:43:02 +0100 | [diff] [blame] | 2124 | unlink_domain_info(info); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2125 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 2126 | |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 2127 | iommu_disable_dev_iotlb(info); |
David Woodhouse | 7c7faa1 | 2014-03-09 13:33:06 -0700 | [diff] [blame] | 2128 | iommu_detach_dev(info->iommu, info->bus, info->devfn); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2129 | |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 2130 | if (domain_type_is_vm(domain)) { |
David Woodhouse | 7c7faa1 | 2014-03-09 13:33:06 -0700 | [diff] [blame] | 2131 | iommu_detach_dependent_devices(info->iommu, info->dev); |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 2132 | domain_detach_iommu(domain, info->iommu); |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 2133 | } |
| 2134 | |
| 2135 | free_devinfo_mem(info); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2136 | spin_lock_irqsave(&device_domain_lock, flags); |
| 2137 | } |
| 2138 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 2139 | } |
| 2140 | |
| 2141 | /* |
| 2142 | * find_domain |
David Woodhouse | 1525a29 | 2014-03-06 16:19:30 +0000 | [diff] [blame] | 2143 | * Note: we use struct device->archdata.iommu stores the info |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2144 | */ |
David Woodhouse | 1525a29 | 2014-03-06 16:19:30 +0000 | [diff] [blame] | 2145 | static struct dmar_domain *find_domain(struct device *dev) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2146 | { |
| 2147 | struct device_domain_info *info; |
| 2148 | |
| 2149 | /* No lock here, assumes no domain exit in normal case */ |
David Woodhouse | 1525a29 | 2014-03-06 16:19:30 +0000 | [diff] [blame] | 2150 | info = dev->archdata.iommu; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2151 | if (info) |
| 2152 | return info->domain; |
| 2153 | return NULL; |
| 2154 | } |
| 2155 | |
David Woodhouse | 5a8f40e | 2014-03-09 13:31:18 -0700 | [diff] [blame] | 2156 | static inline struct device_domain_info * |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2157 | dmar_search_domain_by_dev_info(int segment, int bus, int devfn) |
| 2158 | { |
| 2159 | struct device_domain_info *info; |
| 2160 | |
| 2161 | list_for_each_entry(info, &device_domain_list, global) |
David Woodhouse | 41e80dca | 2014-03-09 13:55:54 -0700 | [diff] [blame] | 2162 | if (info->iommu->segment == segment && info->bus == bus && |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2163 | info->devfn == devfn) |
David Woodhouse | 5a8f40e | 2014-03-09 13:31:18 -0700 | [diff] [blame] | 2164 | return info; |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2165 | |
| 2166 | return NULL; |
| 2167 | } |
| 2168 | |
David Woodhouse | 5a8f40e | 2014-03-09 13:31:18 -0700 | [diff] [blame] | 2169 | static struct dmar_domain *dmar_insert_dev_info(struct intel_iommu *iommu, |
David Woodhouse | 41e80dca | 2014-03-09 13:55:54 -0700 | [diff] [blame] | 2170 | int bus, int devfn, |
David Woodhouse | b718cd3 | 2014-03-09 13:11:33 -0700 | [diff] [blame] | 2171 | struct device *dev, |
| 2172 | struct dmar_domain *domain) |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2173 | { |
David Woodhouse | 5a8f40e | 2014-03-09 13:31:18 -0700 | [diff] [blame] | 2174 | struct dmar_domain *found = NULL; |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2175 | struct device_domain_info *info; |
| 2176 | unsigned long flags; |
| 2177 | |
| 2178 | info = alloc_devinfo_mem(); |
| 2179 | if (!info) |
David Woodhouse | b718cd3 | 2014-03-09 13:11:33 -0700 | [diff] [blame] | 2180 | return NULL; |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2181 | |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2182 | info->bus = bus; |
| 2183 | info->devfn = devfn; |
| 2184 | info->dev = dev; |
| 2185 | info->domain = domain; |
David Woodhouse | 5a8f40e | 2014-03-09 13:31:18 -0700 | [diff] [blame] | 2186 | info->iommu = iommu; |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2187 | |
| 2188 | spin_lock_irqsave(&device_domain_lock, flags); |
| 2189 | if (dev) |
David Woodhouse | 0bcb3e2 | 2014-03-06 17:12:03 +0000 | [diff] [blame] | 2190 | found = find_domain(dev); |
David Woodhouse | 5a8f40e | 2014-03-09 13:31:18 -0700 | [diff] [blame] | 2191 | else { |
| 2192 | struct device_domain_info *info2; |
David Woodhouse | 41e80dca | 2014-03-09 13:55:54 -0700 | [diff] [blame] | 2193 | info2 = dmar_search_domain_by_dev_info(iommu->segment, bus, devfn); |
David Woodhouse | 5a8f40e | 2014-03-09 13:31:18 -0700 | [diff] [blame] | 2194 | if (info2) |
| 2195 | found = info2->domain; |
| 2196 | } |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2197 | if (found) { |
| 2198 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 2199 | free_devinfo_mem(info); |
David Woodhouse | b718cd3 | 2014-03-09 13:11:33 -0700 | [diff] [blame] | 2200 | /* Caller must free the original domain */ |
| 2201 | return found; |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2202 | } |
| 2203 | |
David Woodhouse | b718cd3 | 2014-03-09 13:11:33 -0700 | [diff] [blame] | 2204 | list_add(&info->link, &domain->devices); |
| 2205 | list_add(&info->global, &device_domain_list); |
| 2206 | if (dev) |
| 2207 | dev->archdata.iommu = info; |
| 2208 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 2209 | |
| 2210 | return domain; |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2211 | } |
| 2212 | |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2213 | static int get_last_alias(struct pci_dev *pdev, u16 alias, void *opaque) |
| 2214 | { |
| 2215 | *(u16 *)opaque = alias; |
| 2216 | return 0; |
| 2217 | } |
| 2218 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2219 | /* domain is initialized */ |
David Woodhouse | 146922e | 2014-03-09 15:44:17 -0700 | [diff] [blame] | 2220 | static struct dmar_domain *get_domain_for_dev(struct device *dev, int gaw) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2221 | { |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2222 | struct dmar_domain *domain, *tmp; |
| 2223 | struct intel_iommu *iommu; |
David Woodhouse | 5a8f40e | 2014-03-09 13:31:18 -0700 | [diff] [blame] | 2224 | struct device_domain_info *info; |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2225 | u16 dma_alias; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2226 | unsigned long flags; |
Yijing Wang | aa4d066 | 2014-05-26 20:14:06 +0800 | [diff] [blame] | 2227 | u8 bus, devfn; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2228 | |
David Woodhouse | 146922e | 2014-03-09 15:44:17 -0700 | [diff] [blame] | 2229 | domain = find_domain(dev); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2230 | if (domain) |
| 2231 | return domain; |
| 2232 | |
David Woodhouse | 146922e | 2014-03-09 15:44:17 -0700 | [diff] [blame] | 2233 | iommu = device_to_iommu(dev, &bus, &devfn); |
| 2234 | if (!iommu) |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2235 | return NULL; |
| 2236 | |
| 2237 | if (dev_is_pci(dev)) { |
| 2238 | struct pci_dev *pdev = to_pci_dev(dev); |
| 2239 | |
| 2240 | pci_for_each_dma_alias(pdev, get_last_alias, &dma_alias); |
| 2241 | |
| 2242 | spin_lock_irqsave(&device_domain_lock, flags); |
| 2243 | info = dmar_search_domain_by_dev_info(pci_domain_nr(pdev->bus), |
| 2244 | PCI_BUS_NUM(dma_alias), |
| 2245 | dma_alias & 0xff); |
| 2246 | if (info) { |
| 2247 | iommu = info->iommu; |
| 2248 | domain = info->domain; |
| 2249 | } |
| 2250 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 2251 | |
| 2252 | /* DMA alias already has a domain, uses it */ |
| 2253 | if (info) |
| 2254 | goto found_domain; |
| 2255 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2256 | |
David Woodhouse | 146922e | 2014-03-09 15:44:17 -0700 | [diff] [blame] | 2257 | /* Allocate and initialize new domain for the device */ |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 2258 | domain = alloc_domain(0); |
Jiang Liu | 745f258 | 2014-02-19 14:07:26 +0800 | [diff] [blame] | 2259 | if (!domain) |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2260 | return NULL; |
Jiang Liu | 44bde61 | 2014-07-11 14:19:29 +0800 | [diff] [blame] | 2261 | domain->id = iommu_attach_domain(domain, iommu); |
| 2262 | if (domain->id < 0) { |
Alex Williamson | 2fe9723d | 2011-03-04 14:52:30 -0700 | [diff] [blame] | 2263 | free_domain_mem(domain); |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2264 | return NULL; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2265 | } |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 2266 | domain_attach_iommu(domain, iommu); |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2267 | if (domain_init(domain, gaw)) { |
| 2268 | domain_exit(domain); |
| 2269 | return NULL; |
| 2270 | } |
| 2271 | |
| 2272 | /* register PCI DMA alias device */ |
| 2273 | if (dev_is_pci(dev)) { |
| 2274 | tmp = dmar_insert_dev_info(iommu, PCI_BUS_NUM(dma_alias), |
| 2275 | dma_alias & 0xff, NULL, domain); |
| 2276 | |
| 2277 | if (!tmp || tmp != domain) { |
| 2278 | domain_exit(domain); |
| 2279 | domain = tmp; |
| 2280 | } |
| 2281 | |
David Woodhouse | b718cd3 | 2014-03-09 13:11:33 -0700 | [diff] [blame] | 2282 | if (!domain) |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2283 | return NULL; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2284 | } |
| 2285 | |
| 2286 | found_domain: |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 2287 | tmp = dmar_insert_dev_info(iommu, bus, devfn, dev, domain); |
| 2288 | |
| 2289 | if (!tmp || tmp != domain) { |
| 2290 | domain_exit(domain); |
| 2291 | domain = tmp; |
| 2292 | } |
David Woodhouse | b718cd3 | 2014-03-09 13:11:33 -0700 | [diff] [blame] | 2293 | |
| 2294 | return domain; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2295 | } |
| 2296 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2297 | static int iommu_identity_mapping; |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 2298 | #define IDENTMAP_ALL 1 |
| 2299 | #define IDENTMAP_GFX 2 |
| 2300 | #define IDENTMAP_AZALIA 4 |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2301 | |
David Woodhouse | b213203 | 2009-06-26 18:50:28 +0100 | [diff] [blame] | 2302 | static int iommu_domain_identity_map(struct dmar_domain *domain, |
| 2303 | unsigned long long start, |
| 2304 | unsigned long long end) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2305 | { |
David Woodhouse | c5395d5 | 2009-06-28 16:35:56 +0100 | [diff] [blame] | 2306 | unsigned long first_vpfn = start >> VTD_PAGE_SHIFT; |
| 2307 | unsigned long last_vpfn = end >> VTD_PAGE_SHIFT; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2308 | |
David Woodhouse | c5395d5 | 2009-06-28 16:35:56 +0100 | [diff] [blame] | 2309 | if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn), |
| 2310 | dma_to_mm_pfn(last_vpfn))) { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2311 | printk(KERN_ERR "IOMMU: reserve iova failed\n"); |
David Woodhouse | b213203 | 2009-06-26 18:50:28 +0100 | [diff] [blame] | 2312 | return -ENOMEM; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2313 | } |
| 2314 | |
David Woodhouse | c5395d5 | 2009-06-28 16:35:56 +0100 | [diff] [blame] | 2315 | pr_debug("Mapping reserved region %llx-%llx for domain %d\n", |
| 2316 | start, end, domain->id); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2317 | /* |
| 2318 | * RMRR range might have overlap with physical memory range, |
| 2319 | * clear it first |
| 2320 | */ |
David Woodhouse | c5395d5 | 2009-06-28 16:35:56 +0100 | [diff] [blame] | 2321 | dma_pte_clear_range(domain, first_vpfn, last_vpfn); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2322 | |
David Woodhouse | c5395d5 | 2009-06-28 16:35:56 +0100 | [diff] [blame] | 2323 | return domain_pfn_mapping(domain, first_vpfn, first_vpfn, |
| 2324 | last_vpfn - first_vpfn + 1, |
David Woodhouse | 61df744 | 2009-06-28 11:55:58 +0100 | [diff] [blame] | 2325 | DMA_PTE_READ|DMA_PTE_WRITE); |
David Woodhouse | b213203 | 2009-06-26 18:50:28 +0100 | [diff] [blame] | 2326 | } |
| 2327 | |
David Woodhouse | 0b9d975 | 2014-03-09 15:48:15 -0700 | [diff] [blame] | 2328 | static int iommu_prepare_identity_map(struct device *dev, |
David Woodhouse | b213203 | 2009-06-26 18:50:28 +0100 | [diff] [blame] | 2329 | unsigned long long start, |
| 2330 | unsigned long long end) |
| 2331 | { |
| 2332 | struct dmar_domain *domain; |
| 2333 | int ret; |
| 2334 | |
David Woodhouse | 0b9d975 | 2014-03-09 15:48:15 -0700 | [diff] [blame] | 2335 | domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH); |
David Woodhouse | b213203 | 2009-06-26 18:50:28 +0100 | [diff] [blame] | 2336 | if (!domain) |
| 2337 | return -ENOMEM; |
| 2338 | |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2339 | /* For _hardware_ passthrough, don't bother. But for software |
| 2340 | passthrough, we do it anyway -- it may indicate a memory |
| 2341 | range which is reserved in E820, so which didn't get set |
| 2342 | up to start with in si_domain */ |
| 2343 | if (domain == si_domain && hw_pass_through) { |
| 2344 | printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n", |
David Woodhouse | 0b9d975 | 2014-03-09 15:48:15 -0700 | [diff] [blame] | 2345 | dev_name(dev), start, end); |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2346 | return 0; |
| 2347 | } |
| 2348 | |
| 2349 | printk(KERN_INFO |
| 2350 | "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n", |
David Woodhouse | 0b9d975 | 2014-03-09 15:48:15 -0700 | [diff] [blame] | 2351 | dev_name(dev), start, end); |
David Woodhouse | 2ff729f | 2009-08-26 14:25:41 +0100 | [diff] [blame] | 2352 | |
David Woodhouse | 5595b52 | 2009-12-02 09:21:55 +0000 | [diff] [blame] | 2353 | if (end < start) { |
| 2354 | WARN(1, "Your BIOS is broken; RMRR ends before it starts!\n" |
| 2355 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", |
| 2356 | dmi_get_system_info(DMI_BIOS_VENDOR), |
| 2357 | dmi_get_system_info(DMI_BIOS_VERSION), |
| 2358 | dmi_get_system_info(DMI_PRODUCT_VERSION)); |
| 2359 | ret = -EIO; |
| 2360 | goto error; |
| 2361 | } |
| 2362 | |
David Woodhouse | 2ff729f | 2009-08-26 14:25:41 +0100 | [diff] [blame] | 2363 | if (end >> agaw_to_width(domain->agaw)) { |
| 2364 | WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n" |
| 2365 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", |
| 2366 | agaw_to_width(domain->agaw), |
| 2367 | dmi_get_system_info(DMI_BIOS_VENDOR), |
| 2368 | dmi_get_system_info(DMI_BIOS_VERSION), |
| 2369 | dmi_get_system_info(DMI_PRODUCT_VERSION)); |
| 2370 | ret = -EIO; |
| 2371 | goto error; |
| 2372 | } |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2373 | |
David Woodhouse | b213203 | 2009-06-26 18:50:28 +0100 | [diff] [blame] | 2374 | ret = iommu_domain_identity_map(domain, start, end); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2375 | if (ret) |
| 2376 | goto error; |
| 2377 | |
| 2378 | /* context entry init */ |
David Woodhouse | 0b9d975 | 2014-03-09 15:48:15 -0700 | [diff] [blame] | 2379 | ret = domain_context_mapping(domain, dev, CONTEXT_TT_MULTI_LEVEL); |
David Woodhouse | b213203 | 2009-06-26 18:50:28 +0100 | [diff] [blame] | 2380 | if (ret) |
| 2381 | goto error; |
| 2382 | |
| 2383 | return 0; |
| 2384 | |
| 2385 | error: |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2386 | domain_exit(domain); |
| 2387 | return ret; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2388 | } |
| 2389 | |
| 2390 | static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr, |
David Woodhouse | 0b9d975 | 2014-03-09 15:48:15 -0700 | [diff] [blame] | 2391 | struct device *dev) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2392 | { |
David Woodhouse | 0b9d975 | 2014-03-09 15:48:15 -0700 | [diff] [blame] | 2393 | if (dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2394 | return 0; |
David Woodhouse | 0b9d975 | 2014-03-09 15:48:15 -0700 | [diff] [blame] | 2395 | return iommu_prepare_identity_map(dev, rmrr->base_address, |
| 2396 | rmrr->end_address); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2397 | } |
| 2398 | |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 2399 | #ifdef CONFIG_INTEL_IOMMU_FLOPPY_WA |
Keshavamurthy, Anil S | 49a0429 | 2007-10-21 16:41:57 -0700 | [diff] [blame] | 2400 | static inline void iommu_prepare_isa(void) |
| 2401 | { |
| 2402 | struct pci_dev *pdev; |
| 2403 | int ret; |
| 2404 | |
| 2405 | pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); |
| 2406 | if (!pdev) |
| 2407 | return; |
| 2408 | |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 2409 | printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n"); |
David Woodhouse | 0b9d975 | 2014-03-09 15:48:15 -0700 | [diff] [blame] | 2410 | ret = iommu_prepare_identity_map(&pdev->dev, 0, 16*1024*1024 - 1); |
Keshavamurthy, Anil S | 49a0429 | 2007-10-21 16:41:57 -0700 | [diff] [blame] | 2411 | |
| 2412 | if (ret) |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 2413 | printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; " |
| 2414 | "floppy might not work\n"); |
Keshavamurthy, Anil S | 49a0429 | 2007-10-21 16:41:57 -0700 | [diff] [blame] | 2415 | |
Yijing Wang | 9b27e82 | 2014-05-20 20:37:52 +0800 | [diff] [blame] | 2416 | pci_dev_put(pdev); |
Keshavamurthy, Anil S | 49a0429 | 2007-10-21 16:41:57 -0700 | [diff] [blame] | 2417 | } |
| 2418 | #else |
| 2419 | static inline void iommu_prepare_isa(void) |
| 2420 | { |
| 2421 | return; |
| 2422 | } |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 2423 | #endif /* !CONFIG_INTEL_IOMMU_FLPY_WA */ |
Keshavamurthy, Anil S | 49a0429 | 2007-10-21 16:41:57 -0700 | [diff] [blame] | 2424 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2425 | static int md_domain_init(struct dmar_domain *domain, int guest_width); |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 2426 | |
Matt Kraai | 071e137 | 2009-08-23 22:30:22 -0700 | [diff] [blame] | 2427 | static int __init si_domain_init(int hw) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2428 | { |
| 2429 | struct dmar_drhd_unit *drhd; |
| 2430 | struct intel_iommu *iommu; |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 2431 | int nid, ret = 0; |
Jiang Liu | 44bde61 | 2014-07-11 14:19:29 +0800 | [diff] [blame] | 2432 | bool first = true; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2433 | |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 2434 | si_domain = alloc_domain(DOMAIN_FLAG_STATIC_IDENTITY); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2435 | if (!si_domain) |
| 2436 | return -EFAULT; |
| 2437 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2438 | for_each_active_iommu(iommu, drhd) { |
| 2439 | ret = iommu_attach_domain(si_domain, iommu); |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 2440 | if (ret < 0) { |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2441 | domain_exit(si_domain); |
| 2442 | return -EFAULT; |
Jiang Liu | 44bde61 | 2014-07-11 14:19:29 +0800 | [diff] [blame] | 2443 | } else if (first) { |
| 2444 | si_domain->id = ret; |
| 2445 | first = false; |
| 2446 | } else if (si_domain->id != ret) { |
| 2447 | domain_exit(si_domain); |
| 2448 | return -EFAULT; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2449 | } |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 2450 | domain_attach_iommu(si_domain, iommu); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2451 | } |
| 2452 | |
| 2453 | if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { |
| 2454 | domain_exit(si_domain); |
| 2455 | return -EFAULT; |
| 2456 | } |
| 2457 | |
Jiang Liu | 9544c00 | 2014-01-06 14:18:13 +0800 | [diff] [blame] | 2458 | pr_debug("IOMMU: identity mapping domain is domain %d\n", |
| 2459 | si_domain->id); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2460 | |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2461 | if (hw) |
| 2462 | return 0; |
| 2463 | |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 2464 | for_each_online_node(nid) { |
Tejun Heo | d4bbf7e | 2011-11-28 09:46:22 -0800 | [diff] [blame] | 2465 | unsigned long start_pfn, end_pfn; |
| 2466 | int i; |
| 2467 | |
| 2468 | for_each_mem_pfn_range(i, nid, &start_pfn, &end_pfn, NULL) { |
| 2469 | ret = iommu_domain_identity_map(si_domain, |
| 2470 | PFN_PHYS(start_pfn), PFN_PHYS(end_pfn)); |
| 2471 | if (ret) |
| 2472 | return ret; |
| 2473 | } |
David Woodhouse | c7ab48d | 2009-06-26 19:10:36 +0100 | [diff] [blame] | 2474 | } |
| 2475 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2476 | return 0; |
| 2477 | } |
| 2478 | |
David Woodhouse | 9b22662 | 2014-03-09 14:03:28 -0700 | [diff] [blame] | 2479 | static int identity_mapping(struct device *dev) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2480 | { |
| 2481 | struct device_domain_info *info; |
| 2482 | |
| 2483 | if (likely(!iommu_identity_mapping)) |
| 2484 | return 0; |
| 2485 | |
David Woodhouse | 9b22662 | 2014-03-09 14:03:28 -0700 | [diff] [blame] | 2486 | info = dev->archdata.iommu; |
Mike Travis | cb452a4 | 2011-05-28 13:15:03 -0500 | [diff] [blame] | 2487 | if (info && info != DUMMY_DEVICE_DOMAIN_INFO) |
| 2488 | return (info->domain == si_domain); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2489 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2490 | return 0; |
| 2491 | } |
| 2492 | |
| 2493 | static int domain_add_dev_info(struct dmar_domain *domain, |
David Woodhouse | 5913c9b | 2014-03-09 16:27:31 -0700 | [diff] [blame] | 2494 | struct device *dev, int translation) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2495 | { |
David Woodhouse | 0ac7266 | 2014-03-09 13:19:22 -0700 | [diff] [blame] | 2496 | struct dmar_domain *ndomain; |
David Woodhouse | 5a8f40e | 2014-03-09 13:31:18 -0700 | [diff] [blame] | 2497 | struct intel_iommu *iommu; |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 2498 | u8 bus, devfn; |
David Woodhouse | 5fe60f4 | 2009-08-09 10:53:41 +0100 | [diff] [blame] | 2499 | int ret; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2500 | |
David Woodhouse | 5913c9b | 2014-03-09 16:27:31 -0700 | [diff] [blame] | 2501 | iommu = device_to_iommu(dev, &bus, &devfn); |
David Woodhouse | 5a8f40e | 2014-03-09 13:31:18 -0700 | [diff] [blame] | 2502 | if (!iommu) |
| 2503 | return -ENODEV; |
| 2504 | |
David Woodhouse | 5913c9b | 2014-03-09 16:27:31 -0700 | [diff] [blame] | 2505 | ndomain = dmar_insert_dev_info(iommu, bus, devfn, dev, domain); |
David Woodhouse | 0ac7266 | 2014-03-09 13:19:22 -0700 | [diff] [blame] | 2506 | if (ndomain != domain) |
| 2507 | return -EBUSY; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2508 | |
David Woodhouse | 5913c9b | 2014-03-09 16:27:31 -0700 | [diff] [blame] | 2509 | ret = domain_context_mapping(domain, dev, translation); |
David Woodhouse | e2ad23d | 2012-05-25 17:42:54 +0100 | [diff] [blame] | 2510 | if (ret) { |
David Woodhouse | 5913c9b | 2014-03-09 16:27:31 -0700 | [diff] [blame] | 2511 | domain_remove_one_dev_info(domain, dev); |
David Woodhouse | e2ad23d | 2012-05-25 17:42:54 +0100 | [diff] [blame] | 2512 | return ret; |
| 2513 | } |
| 2514 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2515 | return 0; |
| 2516 | } |
| 2517 | |
David Woodhouse | 0b9d975 | 2014-03-09 15:48:15 -0700 | [diff] [blame] | 2518 | static bool device_has_rmrr(struct device *dev) |
Tom Mingarelli | ea2447f | 2012-11-20 19:43:17 +0000 | [diff] [blame] | 2519 | { |
| 2520 | struct dmar_rmrr_unit *rmrr; |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 2521 | struct device *tmp; |
Tom Mingarelli | ea2447f | 2012-11-20 19:43:17 +0000 | [diff] [blame] | 2522 | int i; |
| 2523 | |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 2524 | rcu_read_lock(); |
Tom Mingarelli | ea2447f | 2012-11-20 19:43:17 +0000 | [diff] [blame] | 2525 | for_each_rmrr_units(rmrr) { |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 2526 | /* |
| 2527 | * Return TRUE if this RMRR contains the device that |
| 2528 | * is passed in. |
| 2529 | */ |
| 2530 | for_each_active_dev_scope(rmrr->devices, |
| 2531 | rmrr->devices_cnt, i, tmp) |
David Woodhouse | 0b9d975 | 2014-03-09 15:48:15 -0700 | [diff] [blame] | 2532 | if (tmp == dev) { |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 2533 | rcu_read_unlock(); |
Tom Mingarelli | ea2447f | 2012-11-20 19:43:17 +0000 | [diff] [blame] | 2534 | return true; |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 2535 | } |
Tom Mingarelli | ea2447f | 2012-11-20 19:43:17 +0000 | [diff] [blame] | 2536 | } |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 2537 | rcu_read_unlock(); |
Tom Mingarelli | ea2447f | 2012-11-20 19:43:17 +0000 | [diff] [blame] | 2538 | return false; |
| 2539 | } |
| 2540 | |
Alex Williamson | c875d2c | 2014-07-03 09:57:02 -0600 | [diff] [blame] | 2541 | /* |
| 2542 | * There are a couple cases where we need to restrict the functionality of |
| 2543 | * devices associated with RMRRs. The first is when evaluating a device for |
| 2544 | * identity mapping because problems exist when devices are moved in and out |
| 2545 | * of domains and their respective RMRR information is lost. This means that |
| 2546 | * a device with associated RMRRs will never be in a "passthrough" domain. |
| 2547 | * The second is use of the device through the IOMMU API. This interface |
| 2548 | * expects to have full control of the IOVA space for the device. We cannot |
| 2549 | * satisfy both the requirement that RMRR access is maintained and have an |
| 2550 | * unencumbered IOVA space. We also have no ability to quiesce the device's |
| 2551 | * use of the RMRR space or even inform the IOMMU API user of the restriction. |
| 2552 | * We therefore prevent devices associated with an RMRR from participating in |
| 2553 | * the IOMMU API, which eliminates them from device assignment. |
| 2554 | * |
| 2555 | * In both cases we assume that PCI USB devices with RMRRs have them largely |
| 2556 | * for historical reasons and that the RMRR space is not actively used post |
| 2557 | * boot. This exclusion may change if vendors begin to abuse it. |
| 2558 | */ |
| 2559 | static bool device_is_rmrr_locked(struct device *dev) |
| 2560 | { |
| 2561 | if (!device_has_rmrr(dev)) |
| 2562 | return false; |
| 2563 | |
| 2564 | if (dev_is_pci(dev)) { |
| 2565 | struct pci_dev *pdev = to_pci_dev(dev); |
| 2566 | |
| 2567 | if ((pdev->class >> 8) == PCI_CLASS_SERIAL_USB) |
| 2568 | return false; |
| 2569 | } |
| 2570 | |
| 2571 | return true; |
| 2572 | } |
| 2573 | |
David Woodhouse | 3bdb259 | 2014-03-09 16:03:08 -0700 | [diff] [blame] | 2574 | static int iommu_should_identity_map(struct device *dev, int startup) |
David Woodhouse | 6941af2 | 2009-07-04 18:24:27 +0100 | [diff] [blame] | 2575 | { |
Tom Mingarelli | ea2447f | 2012-11-20 19:43:17 +0000 | [diff] [blame] | 2576 | |
David Woodhouse | 3bdb259 | 2014-03-09 16:03:08 -0700 | [diff] [blame] | 2577 | if (dev_is_pci(dev)) { |
| 2578 | struct pci_dev *pdev = to_pci_dev(dev); |
Tom Mingarelli | ea2447f | 2012-11-20 19:43:17 +0000 | [diff] [blame] | 2579 | |
Alex Williamson | c875d2c | 2014-07-03 09:57:02 -0600 | [diff] [blame] | 2580 | if (device_is_rmrr_locked(dev)) |
David Woodhouse | 3bdb259 | 2014-03-09 16:03:08 -0700 | [diff] [blame] | 2581 | return 0; |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 2582 | |
David Woodhouse | 3bdb259 | 2014-03-09 16:03:08 -0700 | [diff] [blame] | 2583 | if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev)) |
| 2584 | return 1; |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 2585 | |
David Woodhouse | 3bdb259 | 2014-03-09 16:03:08 -0700 | [diff] [blame] | 2586 | if ((iommu_identity_mapping & IDENTMAP_GFX) && IS_GFX_DEVICE(pdev)) |
| 2587 | return 1; |
| 2588 | |
| 2589 | if (!(iommu_identity_mapping & IDENTMAP_ALL)) |
| 2590 | return 0; |
| 2591 | |
| 2592 | /* |
| 2593 | * We want to start off with all devices in the 1:1 domain, and |
| 2594 | * take them out later if we find they can't access all of memory. |
| 2595 | * |
| 2596 | * However, we can't do this for PCI devices behind bridges, |
| 2597 | * because all PCI devices behind the same bridge will end up |
| 2598 | * with the same source-id on their transactions. |
| 2599 | * |
| 2600 | * Practically speaking, we can't change things around for these |
| 2601 | * devices at run-time, because we can't be sure there'll be no |
| 2602 | * DMA transactions in flight for any of their siblings. |
| 2603 | * |
| 2604 | * So PCI devices (unless they're on the root bus) as well as |
| 2605 | * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of |
| 2606 | * the 1:1 domain, just in _case_ one of their siblings turns out |
| 2607 | * not to be able to map all of memory. |
| 2608 | */ |
| 2609 | if (!pci_is_pcie(pdev)) { |
| 2610 | if (!pci_is_root_bus(pdev->bus)) |
| 2611 | return 0; |
| 2612 | if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI) |
| 2613 | return 0; |
| 2614 | } else if (pci_pcie_type(pdev) == PCI_EXP_TYPE_PCI_BRIDGE) |
| 2615 | return 0; |
| 2616 | } else { |
| 2617 | if (device_has_rmrr(dev)) |
| 2618 | return 0; |
| 2619 | } |
David Woodhouse | 6941af2 | 2009-07-04 18:24:27 +0100 | [diff] [blame] | 2620 | |
David Woodhouse | 3dfc813 | 2009-07-04 19:11:08 +0100 | [diff] [blame] | 2621 | /* |
David Woodhouse | 3dfc813 | 2009-07-04 19:11:08 +0100 | [diff] [blame] | 2622 | * At boot time, we don't yet know if devices will be 64-bit capable. |
David Woodhouse | 3bdb259 | 2014-03-09 16:03:08 -0700 | [diff] [blame] | 2623 | * Assume that they will — if they turn out not to be, then we can |
David Woodhouse | 3dfc813 | 2009-07-04 19:11:08 +0100 | [diff] [blame] | 2624 | * take them out of the 1:1 domain later. |
| 2625 | */ |
Chris Wright | 8fcc537 | 2011-05-28 13:15:02 -0500 | [diff] [blame] | 2626 | if (!startup) { |
| 2627 | /* |
| 2628 | * If the device's dma_mask is less than the system's memory |
| 2629 | * size then this is not a candidate for identity mapping. |
| 2630 | */ |
David Woodhouse | 3bdb259 | 2014-03-09 16:03:08 -0700 | [diff] [blame] | 2631 | u64 dma_mask = *dev->dma_mask; |
Chris Wright | 8fcc537 | 2011-05-28 13:15:02 -0500 | [diff] [blame] | 2632 | |
David Woodhouse | 3bdb259 | 2014-03-09 16:03:08 -0700 | [diff] [blame] | 2633 | if (dev->coherent_dma_mask && |
| 2634 | dev->coherent_dma_mask < dma_mask) |
| 2635 | dma_mask = dev->coherent_dma_mask; |
Chris Wright | 8fcc537 | 2011-05-28 13:15:02 -0500 | [diff] [blame] | 2636 | |
David Woodhouse | 3bdb259 | 2014-03-09 16:03:08 -0700 | [diff] [blame] | 2637 | return dma_mask >= dma_get_required_mask(dev); |
Chris Wright | 8fcc537 | 2011-05-28 13:15:02 -0500 | [diff] [blame] | 2638 | } |
David Woodhouse | 6941af2 | 2009-07-04 18:24:27 +0100 | [diff] [blame] | 2639 | |
| 2640 | return 1; |
| 2641 | } |
| 2642 | |
David Woodhouse | cf04eee | 2014-03-21 16:49:04 +0000 | [diff] [blame] | 2643 | static int __init dev_prepare_static_identity_mapping(struct device *dev, int hw) |
| 2644 | { |
| 2645 | int ret; |
| 2646 | |
| 2647 | if (!iommu_should_identity_map(dev, 1)) |
| 2648 | return 0; |
| 2649 | |
| 2650 | ret = domain_add_dev_info(si_domain, dev, |
| 2651 | hw ? CONTEXT_TT_PASS_THROUGH : |
| 2652 | CONTEXT_TT_MULTI_LEVEL); |
| 2653 | if (!ret) |
| 2654 | pr_info("IOMMU: %s identity mapping for device %s\n", |
| 2655 | hw ? "hardware" : "software", dev_name(dev)); |
| 2656 | else if (ret == -ENODEV) |
| 2657 | /* device not associated with an iommu */ |
| 2658 | ret = 0; |
| 2659 | |
| 2660 | return ret; |
| 2661 | } |
| 2662 | |
| 2663 | |
Matt Kraai | 071e137 | 2009-08-23 22:30:22 -0700 | [diff] [blame] | 2664 | static int __init iommu_prepare_static_identity_mapping(int hw) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2665 | { |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2666 | struct pci_dev *pdev = NULL; |
David Woodhouse | cf04eee | 2014-03-21 16:49:04 +0000 | [diff] [blame] | 2667 | struct dmar_drhd_unit *drhd; |
| 2668 | struct intel_iommu *iommu; |
| 2669 | struct device *dev; |
| 2670 | int i; |
| 2671 | int ret = 0; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2672 | |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2673 | ret = si_domain_init(hw); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2674 | if (ret) |
| 2675 | return -EFAULT; |
| 2676 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2677 | for_each_pci_dev(pdev) { |
David Woodhouse | cf04eee | 2014-03-21 16:49:04 +0000 | [diff] [blame] | 2678 | ret = dev_prepare_static_identity_mapping(&pdev->dev, hw); |
| 2679 | if (ret) |
| 2680 | return ret; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2681 | } |
| 2682 | |
David Woodhouse | cf04eee | 2014-03-21 16:49:04 +0000 | [diff] [blame] | 2683 | for_each_active_iommu(iommu, drhd) |
| 2684 | for_each_active_dev_scope(drhd->devices, drhd->devices_cnt, i, dev) { |
| 2685 | struct acpi_device_physical_node *pn; |
| 2686 | struct acpi_device *adev; |
| 2687 | |
| 2688 | if (dev->bus != &acpi_bus_type) |
| 2689 | continue; |
| 2690 | |
| 2691 | adev= to_acpi_device(dev); |
| 2692 | mutex_lock(&adev->physical_node_lock); |
| 2693 | list_for_each_entry(pn, &adev->physical_node_list, node) { |
| 2694 | ret = dev_prepare_static_identity_mapping(pn->dev, hw); |
| 2695 | if (ret) |
| 2696 | break; |
| 2697 | } |
| 2698 | mutex_unlock(&adev->physical_node_lock); |
| 2699 | if (ret) |
| 2700 | return ret; |
| 2701 | } |
| 2702 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2703 | return 0; |
| 2704 | } |
| 2705 | |
Joseph Cihula | b779260 | 2011-05-03 00:08:37 -0700 | [diff] [blame] | 2706 | static int __init init_dmars(void) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2707 | { |
| 2708 | struct dmar_drhd_unit *drhd; |
| 2709 | struct dmar_rmrr_unit *rmrr; |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 2710 | struct device *dev; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2711 | struct intel_iommu *iommu; |
Suresh Siddha | 9d783ba | 2009-03-16 17:04:55 -0700 | [diff] [blame] | 2712 | int i, ret; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2713 | |
| 2714 | /* |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2715 | * for each drhd |
| 2716 | * allocate root |
| 2717 | * initialize and program root entry to not present |
| 2718 | * endfor |
| 2719 | */ |
| 2720 | for_each_drhd_unit(drhd) { |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2721 | /* |
| 2722 | * lock not needed as this is only incremented in the single |
| 2723 | * threaded kernel __init code path all other access are read |
| 2724 | * only |
| 2725 | */ |
Jiang Liu | 78d8e70 | 2014-11-09 22:47:57 +0800 | [diff] [blame^] | 2726 | if (g_num_of_iommus < DMAR_UNITS_SUPPORTED) { |
Mike Travis | 1b198bb | 2012-03-05 15:05:16 -0800 | [diff] [blame] | 2727 | g_num_of_iommus++; |
| 2728 | continue; |
| 2729 | } |
| 2730 | printk_once(KERN_ERR "intel-iommu: exceeded %d IOMMUs\n", |
Jiang Liu | 78d8e70 | 2014-11-09 22:47:57 +0800 | [diff] [blame^] | 2731 | DMAR_UNITS_SUPPORTED); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2732 | } |
| 2733 | |
Weidong Han | d9630fe | 2008-12-08 11:06:32 +0800 | [diff] [blame] | 2734 | g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *), |
| 2735 | GFP_KERNEL); |
| 2736 | if (!g_iommus) { |
| 2737 | printk(KERN_ERR "Allocating global iommu array failed\n"); |
| 2738 | ret = -ENOMEM; |
| 2739 | goto error; |
| 2740 | } |
| 2741 | |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 2742 | deferred_flush = kzalloc(g_num_of_iommus * |
| 2743 | sizeof(struct deferred_flush_tables), GFP_KERNEL); |
| 2744 | if (!deferred_flush) { |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2745 | ret = -ENOMEM; |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 2746 | goto free_g_iommus; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 2747 | } |
| 2748 | |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 2749 | for_each_active_iommu(iommu, drhd) { |
Weidong Han | d9630fe | 2008-12-08 11:06:32 +0800 | [diff] [blame] | 2750 | g_iommus[iommu->seq_id] = iommu; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2751 | |
Suresh Siddha | e61d98d | 2008-07-10 11:16:35 -0700 | [diff] [blame] | 2752 | ret = iommu_init_domains(iommu); |
| 2753 | if (ret) |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 2754 | goto free_iommu; |
Suresh Siddha | e61d98d | 2008-07-10 11:16:35 -0700 | [diff] [blame] | 2755 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2756 | /* |
| 2757 | * TBD: |
| 2758 | * we could share the same root & context tables |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 2759 | * among all IOMMU's. Need to Split it later. |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2760 | */ |
| 2761 | ret = iommu_alloc_root_entry(iommu); |
| 2762 | if (ret) { |
| 2763 | printk(KERN_ERR "IOMMU: allocate root entry failed\n"); |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 2764 | goto free_iommu; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2765 | } |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2766 | if (!ecap_pass_through(iommu->ecap)) |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2767 | hw_pass_through = 0; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2768 | } |
| 2769 | |
Suresh Siddha | 1531a6a | 2009-03-16 17:04:57 -0700 | [diff] [blame] | 2770 | /* |
| 2771 | * Start from the sane iommu hardware state. |
| 2772 | */ |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 2773 | for_each_active_iommu(iommu, drhd) { |
Suresh Siddha | 1531a6a | 2009-03-16 17:04:57 -0700 | [diff] [blame] | 2774 | /* |
| 2775 | * If the queued invalidation is already initialized by us |
| 2776 | * (for example, while enabling interrupt-remapping) then |
| 2777 | * we got the things already rolling from a sane state. |
| 2778 | */ |
| 2779 | if (iommu->qi) |
| 2780 | continue; |
| 2781 | |
| 2782 | /* |
| 2783 | * Clear any previous faults. |
| 2784 | */ |
| 2785 | dmar_fault(-1, iommu); |
| 2786 | /* |
| 2787 | * Disable queued invalidation if supported and already enabled |
| 2788 | * before OS handover. |
| 2789 | */ |
| 2790 | dmar_disable_qi(iommu); |
| 2791 | } |
| 2792 | |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 2793 | for_each_active_iommu(iommu, drhd) { |
Youquan Song | a77b67d | 2008-10-16 16:31:56 -0700 | [diff] [blame] | 2794 | if (dmar_enable_qi(iommu)) { |
| 2795 | /* |
| 2796 | * Queued Invalidate not enabled, use Register Based |
| 2797 | * Invalidate |
| 2798 | */ |
| 2799 | iommu->flush.flush_context = __iommu_flush_context; |
| 2800 | iommu->flush.flush_iotlb = __iommu_flush_iotlb; |
Yinghai Lu | 680a752 | 2010-04-08 19:58:23 +0100 | [diff] [blame] | 2801 | printk(KERN_INFO "IOMMU %d 0x%Lx: using Register based " |
FUJITA Tomonori | b4e0f9e | 2008-11-19 13:53:42 +0900 | [diff] [blame] | 2802 | "invalidation\n", |
Yinghai Lu | 680a752 | 2010-04-08 19:58:23 +0100 | [diff] [blame] | 2803 | iommu->seq_id, |
FUJITA Tomonori | b4e0f9e | 2008-11-19 13:53:42 +0900 | [diff] [blame] | 2804 | (unsigned long long)drhd->reg_base_addr); |
Youquan Song | a77b67d | 2008-10-16 16:31:56 -0700 | [diff] [blame] | 2805 | } else { |
| 2806 | iommu->flush.flush_context = qi_flush_context; |
| 2807 | iommu->flush.flush_iotlb = qi_flush_iotlb; |
Yinghai Lu | 680a752 | 2010-04-08 19:58:23 +0100 | [diff] [blame] | 2808 | printk(KERN_INFO "IOMMU %d 0x%Lx: using Queued " |
FUJITA Tomonori | b4e0f9e | 2008-11-19 13:53:42 +0900 | [diff] [blame] | 2809 | "invalidation\n", |
Yinghai Lu | 680a752 | 2010-04-08 19:58:23 +0100 | [diff] [blame] | 2810 | iommu->seq_id, |
FUJITA Tomonori | b4e0f9e | 2008-11-19 13:53:42 +0900 | [diff] [blame] | 2811 | (unsigned long long)drhd->reg_base_addr); |
Youquan Song | a77b67d | 2008-10-16 16:31:56 -0700 | [diff] [blame] | 2812 | } |
| 2813 | } |
| 2814 | |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2815 | if (iommu_pass_through) |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 2816 | iommu_identity_mapping |= IDENTMAP_ALL; |
| 2817 | |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 2818 | #ifdef CONFIG_INTEL_IOMMU_BROKEN_GFX_WA |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 2819 | iommu_identity_mapping |= IDENTMAP_GFX; |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2820 | #endif |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 2821 | |
| 2822 | check_tylersburg_isoch(); |
| 2823 | |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2824 | /* |
| 2825 | * If pass through is not set or not enabled, setup context entries for |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2826 | * identity mappings for rmrr, gfx, and isa and may fall back to static |
| 2827 | * identity mapping if iommu_identity_mapping is set. |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2828 | */ |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2829 | if (iommu_identity_mapping) { |
| 2830 | ret = iommu_prepare_static_identity_mapping(hw_pass_through); |
| 2831 | if (ret) { |
| 2832 | printk(KERN_CRIT "Failed to setup IOMMU pass-through\n"); |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 2833 | goto free_iommu; |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2834 | } |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 2835 | } |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2836 | /* |
| 2837 | * For each rmrr |
| 2838 | * for each dev attached to rmrr |
| 2839 | * do |
| 2840 | * locate drhd for dev, alloc domain for dev |
| 2841 | * allocate free domain |
| 2842 | * allocate page table entries for rmrr |
| 2843 | * if context not allocated for bus |
| 2844 | * allocate and init context |
| 2845 | * set present in root table for this bus |
| 2846 | * init context with domain, translation etc |
| 2847 | * endfor |
| 2848 | * endfor |
| 2849 | */ |
| 2850 | printk(KERN_INFO "IOMMU: Setting RMRR:\n"); |
| 2851 | for_each_rmrr_units(rmrr) { |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 2852 | /* some BIOS lists non-exist devices in DMAR table. */ |
| 2853 | for_each_active_dev_scope(rmrr->devices, rmrr->devices_cnt, |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 2854 | i, dev) { |
David Woodhouse | 0b9d975 | 2014-03-09 15:48:15 -0700 | [diff] [blame] | 2855 | ret = iommu_prepare_rmrr_dev(rmrr, dev); |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 2856 | if (ret) |
| 2857 | printk(KERN_ERR |
| 2858 | "IOMMU: mapping reserved region failed\n"); |
| 2859 | } |
| 2860 | } |
| 2861 | |
| 2862 | iommu_prepare_isa(); |
Keshavamurthy, Anil S | 49a0429 | 2007-10-21 16:41:57 -0700 | [diff] [blame] | 2863 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2864 | /* |
| 2865 | * for each drhd |
| 2866 | * enable fault log |
| 2867 | * global invalidate context cache |
| 2868 | * global invalidate iotlb |
| 2869 | * enable translation |
| 2870 | */ |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 2871 | for_each_iommu(iommu, drhd) { |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 2872 | if (drhd->ignored) { |
| 2873 | /* |
| 2874 | * we always have to disable PMRs or DMA may fail on |
| 2875 | * this device |
| 2876 | */ |
| 2877 | if (force_on) |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 2878 | iommu_disable_protect_mem_regions(iommu); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2879 | continue; |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 2880 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2881 | |
| 2882 | iommu_flush_write_buffer(iommu); |
| 2883 | |
Keshavamurthy, Anil S | 3460a6d | 2007-10-21 16:41:54 -0700 | [diff] [blame] | 2884 | ret = dmar_set_interrupt(iommu); |
| 2885 | if (ret) |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 2886 | goto free_iommu; |
Keshavamurthy, Anil S | 3460a6d | 2007-10-21 16:41:54 -0700 | [diff] [blame] | 2887 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2888 | iommu_set_root_entry(iommu); |
| 2889 | |
David Woodhouse | 4c25a2c | 2009-05-10 17:16:06 +0100 | [diff] [blame] | 2890 | iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL); |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 2891 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
Jiang Liu | 2a41cce | 2014-07-11 14:19:33 +0800 | [diff] [blame] | 2892 | iommu_enable_translation(iommu); |
David Woodhouse | b94996c | 2009-09-19 15:28:12 -0700 | [diff] [blame] | 2893 | iommu_disable_protect_mem_regions(iommu); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2894 | } |
| 2895 | |
| 2896 | return 0; |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 2897 | |
| 2898 | free_iommu: |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 2899 | for_each_active_iommu(iommu, drhd) |
Jiang Liu | a868e6b | 2014-01-06 14:18:20 +0800 | [diff] [blame] | 2900 | free_dmar_iommu(iommu); |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 2901 | kfree(deferred_flush); |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 2902 | free_g_iommus: |
Weidong Han | d9630fe | 2008-12-08 11:06:32 +0800 | [diff] [blame] | 2903 | kfree(g_iommus); |
Jiang Liu | 989d51f | 2014-02-19 14:07:21 +0800 | [diff] [blame] | 2904 | error: |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2905 | return ret; |
| 2906 | } |
| 2907 | |
David Woodhouse | 5a5e02a | 2009-07-04 09:35:44 +0100 | [diff] [blame] | 2908 | /* This takes a number of _MM_ pages, not VTD pages */ |
David Woodhouse | 875764d | 2009-06-28 21:20:51 +0100 | [diff] [blame] | 2909 | static struct iova *intel_alloc_iova(struct device *dev, |
| 2910 | struct dmar_domain *domain, |
| 2911 | unsigned long nrpages, uint64_t dma_mask) |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2912 | { |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2913 | struct iova *iova = NULL; |
| 2914 | |
David Woodhouse | 875764d | 2009-06-28 21:20:51 +0100 | [diff] [blame] | 2915 | /* Restrict dma_mask to the width that the iommu can handle */ |
| 2916 | dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask); |
| 2917 | |
| 2918 | if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) { |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2919 | /* |
| 2920 | * First try to allocate an io virtual address in |
Yang Hongyang | 284901a | 2009-04-06 19:01:15 -0700 | [diff] [blame] | 2921 | * DMA_BIT_MASK(32) and if that fails then try allocating |
Joe Perches | 3609801 | 2007-12-17 11:40:11 -0800 | [diff] [blame] | 2922 | * from higher range |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2923 | */ |
David Woodhouse | 875764d | 2009-06-28 21:20:51 +0100 | [diff] [blame] | 2924 | iova = alloc_iova(&domain->iovad, nrpages, |
| 2925 | IOVA_PFN(DMA_BIT_MASK(32)), 1); |
| 2926 | if (iova) |
| 2927 | return iova; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2928 | } |
David Woodhouse | 875764d | 2009-06-28 21:20:51 +0100 | [diff] [blame] | 2929 | iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1); |
| 2930 | if (unlikely(!iova)) { |
| 2931 | printk(KERN_ERR "Allocating %ld-page iova for %s failed", |
David Woodhouse | 207e359 | 2014-03-09 16:12:32 -0700 | [diff] [blame] | 2932 | nrpages, dev_name(dev)); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2933 | return NULL; |
| 2934 | } |
| 2935 | |
| 2936 | return iova; |
| 2937 | } |
| 2938 | |
David Woodhouse | d4b709f | 2014-03-09 16:07:40 -0700 | [diff] [blame] | 2939 | static struct dmar_domain *__get_valid_domain_for_dev(struct device *dev) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2940 | { |
| 2941 | struct dmar_domain *domain; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2942 | int ret; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2943 | |
David Woodhouse | d4b709f | 2014-03-09 16:07:40 -0700 | [diff] [blame] | 2944 | domain = get_domain_for_dev(dev, DEFAULT_DOMAIN_ADDRESS_WIDTH); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2945 | if (!domain) { |
David Woodhouse | d4b709f | 2014-03-09 16:07:40 -0700 | [diff] [blame] | 2946 | printk(KERN_ERR "Allocating domain for %s failed", |
| 2947 | dev_name(dev)); |
Al Viro | 4fe05bb | 2007-10-29 04:51:16 +0000 | [diff] [blame] | 2948 | return NULL; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2949 | } |
| 2950 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2951 | /* make sure context mapping is ok */ |
David Woodhouse | d4b709f | 2014-03-09 16:07:40 -0700 | [diff] [blame] | 2952 | if (unlikely(!domain_context_mapped(dev))) { |
| 2953 | ret = domain_context_mapping(domain, dev, CONTEXT_TT_MULTI_LEVEL); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2954 | if (ret) { |
David Woodhouse | d4b709f | 2014-03-09 16:07:40 -0700 | [diff] [blame] | 2955 | printk(KERN_ERR "Domain context map for %s failed", |
| 2956 | dev_name(dev)); |
Al Viro | 4fe05bb | 2007-10-29 04:51:16 +0000 | [diff] [blame] | 2957 | return NULL; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2958 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 2959 | } |
| 2960 | |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 2961 | return domain; |
| 2962 | } |
| 2963 | |
David Woodhouse | d4b709f | 2014-03-09 16:07:40 -0700 | [diff] [blame] | 2964 | static inline struct dmar_domain *get_valid_domain_for_dev(struct device *dev) |
David Woodhouse | 147202a | 2009-07-07 19:43:20 +0100 | [diff] [blame] | 2965 | { |
| 2966 | struct device_domain_info *info; |
| 2967 | |
| 2968 | /* No lock here, assumes no domain exit in normal case */ |
David Woodhouse | d4b709f | 2014-03-09 16:07:40 -0700 | [diff] [blame] | 2969 | info = dev->archdata.iommu; |
David Woodhouse | 147202a | 2009-07-07 19:43:20 +0100 | [diff] [blame] | 2970 | if (likely(info)) |
| 2971 | return info->domain; |
| 2972 | |
| 2973 | return __get_valid_domain_for_dev(dev); |
| 2974 | } |
| 2975 | |
David Woodhouse | 3d89194 | 2014-03-06 15:59:26 +0000 | [diff] [blame] | 2976 | static int iommu_dummy(struct device *dev) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2977 | { |
David Woodhouse | 3d89194 | 2014-03-06 15:59:26 +0000 | [diff] [blame] | 2978 | return dev->archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2979 | } |
| 2980 | |
David Woodhouse | ecb509e | 2014-03-09 16:29:55 -0700 | [diff] [blame] | 2981 | /* Check if the dev needs to go through non-identity map and unmap process.*/ |
David Woodhouse | 7367683 | 2009-07-04 14:08:36 +0100 | [diff] [blame] | 2982 | static int iommu_no_mapping(struct device *dev) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2983 | { |
| 2984 | int found; |
| 2985 | |
David Woodhouse | 3d89194 | 2014-03-06 15:59:26 +0000 | [diff] [blame] | 2986 | if (iommu_dummy(dev)) |
David Woodhouse | 1e4c64c | 2009-07-04 10:40:38 +0100 | [diff] [blame] | 2987 | return 1; |
| 2988 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2989 | if (!iommu_identity_mapping) |
David Woodhouse | 1e4c64c | 2009-07-04 10:40:38 +0100 | [diff] [blame] | 2990 | return 0; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2991 | |
David Woodhouse | 9b22662 | 2014-03-09 14:03:28 -0700 | [diff] [blame] | 2992 | found = identity_mapping(dev); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2993 | if (found) { |
David Woodhouse | ecb509e | 2014-03-09 16:29:55 -0700 | [diff] [blame] | 2994 | if (iommu_should_identity_map(dev, 0)) |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 2995 | return 1; |
| 2996 | else { |
| 2997 | /* |
| 2998 | * 32 bit DMA is removed from si_domain and fall back |
| 2999 | * to non-identity mapping. |
| 3000 | */ |
David Woodhouse | bf9c9ed | 2014-03-09 16:19:13 -0700 | [diff] [blame] | 3001 | domain_remove_one_dev_info(si_domain, dev); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3002 | printk(KERN_INFO "32bit %s uses non-identity mapping\n", |
David Woodhouse | ecb509e | 2014-03-09 16:29:55 -0700 | [diff] [blame] | 3003 | dev_name(dev)); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3004 | return 0; |
| 3005 | } |
| 3006 | } else { |
| 3007 | /* |
| 3008 | * In case of a detached 64 bit DMA device from vm, the device |
| 3009 | * is put into si_domain for identity mapping. |
| 3010 | */ |
David Woodhouse | ecb509e | 2014-03-09 16:29:55 -0700 | [diff] [blame] | 3011 | if (iommu_should_identity_map(dev, 0)) { |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3012 | int ret; |
David Woodhouse | 5913c9b | 2014-03-09 16:27:31 -0700 | [diff] [blame] | 3013 | ret = domain_add_dev_info(si_domain, dev, |
David Woodhouse | 5fe60f4 | 2009-08-09 10:53:41 +0100 | [diff] [blame] | 3014 | hw_pass_through ? |
| 3015 | CONTEXT_TT_PASS_THROUGH : |
| 3016 | CONTEXT_TT_MULTI_LEVEL); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3017 | if (!ret) { |
| 3018 | printk(KERN_INFO "64bit %s uses identity mapping\n", |
David Woodhouse | ecb509e | 2014-03-09 16:29:55 -0700 | [diff] [blame] | 3019 | dev_name(dev)); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3020 | return 1; |
| 3021 | } |
| 3022 | } |
| 3023 | } |
| 3024 | |
David Woodhouse | 1e4c64c | 2009-07-04 10:40:38 +0100 | [diff] [blame] | 3025 | return 0; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3026 | } |
| 3027 | |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3028 | static dma_addr_t __intel_map_single(struct device *dev, phys_addr_t paddr, |
FUJITA Tomonori | bb9e6d6 | 2008-10-15 16:08:28 +0900 | [diff] [blame] | 3029 | size_t size, int dir, u64 dma_mask) |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3030 | { |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3031 | struct dmar_domain *domain; |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 3032 | phys_addr_t start_paddr; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3033 | struct iova *iova; |
| 3034 | int prot = 0; |
Ingo Molnar | 6865f0d | 2008-04-22 11:09:04 +0200 | [diff] [blame] | 3035 | int ret; |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3036 | struct intel_iommu *iommu; |
Fenghua Yu | 33041ec | 2009-08-04 15:10:59 -0700 | [diff] [blame] | 3037 | unsigned long paddr_pfn = paddr >> PAGE_SHIFT; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3038 | |
| 3039 | BUG_ON(dir == DMA_NONE); |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3040 | |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3041 | if (iommu_no_mapping(dev)) |
Ingo Molnar | 6865f0d | 2008-04-22 11:09:04 +0200 | [diff] [blame] | 3042 | return paddr; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3043 | |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3044 | domain = get_valid_domain_for_dev(dev); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3045 | if (!domain) |
| 3046 | return 0; |
| 3047 | |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3048 | iommu = domain_get_iommu(domain); |
David Woodhouse | 88cb6a7 | 2009-06-28 15:03:06 +0100 | [diff] [blame] | 3049 | size = aligned_nrpages(paddr, size); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3050 | |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3051 | iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size), dma_mask); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3052 | if (!iova) |
| 3053 | goto error; |
| 3054 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3055 | /* |
| 3056 | * Check if DMAR supports zero-length reads on write only |
| 3057 | * mappings.. |
| 3058 | */ |
| 3059 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3060 | !cap_zlr(iommu->cap)) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3061 | prot |= DMA_PTE_READ; |
| 3062 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) |
| 3063 | prot |= DMA_PTE_WRITE; |
| 3064 | /* |
Ingo Molnar | 6865f0d | 2008-04-22 11:09:04 +0200 | [diff] [blame] | 3065 | * paddr - (paddr + size) might be partial page, we should map the whole |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3066 | * page. Note: if two part of one page are separately mapped, we |
Ingo Molnar | 6865f0d | 2008-04-22 11:09:04 +0200 | [diff] [blame] | 3067 | * might have two guest_addr mapping to the same host paddr, but this |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3068 | * is not a big problem |
| 3069 | */ |
David Woodhouse | 0ab36de | 2009-06-28 14:01:43 +0100 | [diff] [blame] | 3070 | ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo), |
Fenghua Yu | 33041ec | 2009-08-04 15:10:59 -0700 | [diff] [blame] | 3071 | mm_to_dma_pfn(paddr_pfn), size, prot); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3072 | if (ret) |
| 3073 | goto error; |
| 3074 | |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3075 | /* it's a non-present to present mapping. Only flush if caching mode */ |
| 3076 | if (cap_caching_mode(iommu->cap)) |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3077 | iommu_flush_iotlb_psi(iommu, domain->id, mm_to_dma_pfn(iova->pfn_lo), size, 0, 1); |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3078 | else |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3079 | iommu_flush_write_buffer(iommu); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3080 | |
David Woodhouse | 03d6a24 | 2009-06-28 15:33:46 +0100 | [diff] [blame] | 3081 | start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT; |
| 3082 | start_paddr += paddr & ~PAGE_MASK; |
| 3083 | return start_paddr; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3084 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3085 | error: |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3086 | if (iova) |
| 3087 | __free_iova(&domain->iovad, iova); |
David Woodhouse | 4cf2e75 | 2009-02-11 17:23:43 +0000 | [diff] [blame] | 3088 | printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n", |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3089 | dev_name(dev), size, (unsigned long long)paddr, dir); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3090 | return 0; |
| 3091 | } |
| 3092 | |
FUJITA Tomonori | ffbbef5 | 2009-01-05 23:47:26 +0900 | [diff] [blame] | 3093 | static dma_addr_t intel_map_page(struct device *dev, struct page *page, |
| 3094 | unsigned long offset, size_t size, |
| 3095 | enum dma_data_direction dir, |
| 3096 | struct dma_attrs *attrs) |
FUJITA Tomonori | bb9e6d6 | 2008-10-15 16:08:28 +0900 | [diff] [blame] | 3097 | { |
FUJITA Tomonori | ffbbef5 | 2009-01-05 23:47:26 +0900 | [diff] [blame] | 3098 | return __intel_map_single(dev, page_to_phys(page) + offset, size, |
David Woodhouse | 46333e3 | 2014-03-10 20:01:21 -0700 | [diff] [blame] | 3099 | dir, *dev->dma_mask); |
FUJITA Tomonori | bb9e6d6 | 2008-10-15 16:08:28 +0900 | [diff] [blame] | 3100 | } |
| 3101 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3102 | static void flush_unmaps(void) |
| 3103 | { |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 3104 | int i, j; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3105 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3106 | timer_on = 0; |
| 3107 | |
| 3108 | /* just flush them all */ |
| 3109 | for (i = 0; i < g_num_of_iommus; i++) { |
Weidong Han | a2bb845 | 2008-12-08 11:24:12 +0800 | [diff] [blame] | 3110 | struct intel_iommu *iommu = g_iommus[i]; |
| 3111 | if (!iommu) |
| 3112 | continue; |
Suresh Siddha | c42d9f3 | 2008-07-10 11:16:36 -0700 | [diff] [blame] | 3113 | |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 3114 | if (!deferred_flush[i].next) |
| 3115 | continue; |
| 3116 | |
Nadav Amit | 78d5f0f | 2010-04-08 23:00:41 +0300 | [diff] [blame] | 3117 | /* In caching mode, global flushes turn emulation expensive */ |
| 3118 | if (!cap_caching_mode(iommu->cap)) |
| 3119 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 3120 | DMA_TLB_GLOBAL_FLUSH); |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 3121 | for (j = 0; j < deferred_flush[i].next; j++) { |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 3122 | unsigned long mask; |
| 3123 | struct iova *iova = deferred_flush[i].iova[j]; |
Nadav Amit | 78d5f0f | 2010-04-08 23:00:41 +0300 | [diff] [blame] | 3124 | struct dmar_domain *domain = deferred_flush[i].domain[j]; |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 3125 | |
Nadav Amit | 78d5f0f | 2010-04-08 23:00:41 +0300 | [diff] [blame] | 3126 | /* On real hardware multiple invalidations are expensive */ |
| 3127 | if (cap_caching_mode(iommu->cap)) |
| 3128 | iommu_flush_iotlb_psi(iommu, domain->id, |
Jiang Liu | a156ef9 | 2014-07-11 14:19:36 +0800 | [diff] [blame] | 3129 | iova->pfn_lo, iova_size(iova), |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3130 | !deferred_flush[i].freelist[j], 0); |
Nadav Amit | 78d5f0f | 2010-04-08 23:00:41 +0300 | [diff] [blame] | 3131 | else { |
Jiang Liu | a156ef9 | 2014-07-11 14:19:36 +0800 | [diff] [blame] | 3132 | mask = ilog2(mm_to_dma_pfn(iova_size(iova))); |
Nadav Amit | 78d5f0f | 2010-04-08 23:00:41 +0300 | [diff] [blame] | 3133 | iommu_flush_dev_iotlb(deferred_flush[i].domain[j], |
| 3134 | (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask); |
| 3135 | } |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 3136 | __free_iova(&deferred_flush[i].domain[j]->iovad, iova); |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3137 | if (deferred_flush[i].freelist[j]) |
| 3138 | dma_free_pagelist(deferred_flush[i].freelist[j]); |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 3139 | } |
Yu Zhao | 9dd2fe8 | 2009-05-18 13:51:36 +0800 | [diff] [blame] | 3140 | deferred_flush[i].next = 0; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3141 | } |
| 3142 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3143 | list_size = 0; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3144 | } |
| 3145 | |
| 3146 | static void flush_unmaps_timeout(unsigned long data) |
| 3147 | { |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 3148 | unsigned long flags; |
| 3149 | |
| 3150 | spin_lock_irqsave(&async_umap_flush_lock, flags); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3151 | flush_unmaps(); |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 3152 | spin_unlock_irqrestore(&async_umap_flush_lock, flags); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3153 | } |
| 3154 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3155 | static void add_unmap(struct dmar_domain *dom, struct iova *iova, struct page *freelist) |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3156 | { |
| 3157 | unsigned long flags; |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 3158 | int next, iommu_id; |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3159 | struct intel_iommu *iommu; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3160 | |
| 3161 | spin_lock_irqsave(&async_umap_flush_lock, flags); |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 3162 | if (list_size == HIGH_WATER_MARK) |
| 3163 | flush_unmaps(); |
| 3164 | |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3165 | iommu = domain_get_iommu(dom); |
| 3166 | iommu_id = iommu->seq_id; |
Suresh Siddha | c42d9f3 | 2008-07-10 11:16:36 -0700 | [diff] [blame] | 3167 | |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 3168 | next = deferred_flush[iommu_id].next; |
| 3169 | deferred_flush[iommu_id].domain[next] = dom; |
| 3170 | deferred_flush[iommu_id].iova[next] = iova; |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3171 | deferred_flush[iommu_id].freelist[next] = freelist; |
mark gross | 80b20dd | 2008-04-18 13:53:58 -0700 | [diff] [blame] | 3172 | deferred_flush[iommu_id].next++; |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3173 | |
| 3174 | if (!timer_on) { |
| 3175 | mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10)); |
| 3176 | timer_on = 1; |
| 3177 | } |
| 3178 | list_size++; |
| 3179 | spin_unlock_irqrestore(&async_umap_flush_lock, flags); |
| 3180 | } |
| 3181 | |
Jiang Liu | d41a4ad | 2014-07-11 14:19:34 +0800 | [diff] [blame] | 3182 | static void intel_unmap(struct device *dev, dma_addr_t dev_addr) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3183 | { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3184 | struct dmar_domain *domain; |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 3185 | unsigned long start_pfn, last_pfn; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3186 | struct iova *iova; |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3187 | struct intel_iommu *iommu; |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3188 | struct page *freelist; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3189 | |
David Woodhouse | 7367683 | 2009-07-04 14:08:36 +0100 | [diff] [blame] | 3190 | if (iommu_no_mapping(dev)) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3191 | return; |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 3192 | |
David Woodhouse | 1525a29 | 2014-03-06 16:19:30 +0000 | [diff] [blame] | 3193 | domain = find_domain(dev); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3194 | BUG_ON(!domain); |
| 3195 | |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3196 | iommu = domain_get_iommu(domain); |
| 3197 | |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3198 | iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr)); |
David Woodhouse | 85b9827 | 2009-07-01 19:27:53 +0100 | [diff] [blame] | 3199 | if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n", |
| 3200 | (unsigned long long)dev_addr)) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3201 | return; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3202 | |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 3203 | start_pfn = mm_to_dma_pfn(iova->pfn_lo); |
| 3204 | last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3205 | |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 3206 | pr_debug("Device %s unmapping: pfn %lx-%lx\n", |
David Woodhouse | 207e359 | 2014-03-09 16:12:32 -0700 | [diff] [blame] | 3207 | dev_name(dev), start_pfn, last_pfn); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3208 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3209 | freelist = domain_unmap(domain, start_pfn, last_pfn); |
David Woodhouse | d794dc9 | 2009-06-28 00:27:49 +0100 | [diff] [blame] | 3210 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3211 | if (intel_iommu_strict) { |
David Woodhouse | 03d6a24 | 2009-06-28 15:33:46 +0100 | [diff] [blame] | 3212 | iommu_flush_iotlb_psi(iommu, domain->id, start_pfn, |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3213 | last_pfn - start_pfn + 1, !freelist, 0); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3214 | /* free iova */ |
| 3215 | __free_iova(&domain->iovad, iova); |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3216 | dma_free_pagelist(freelist); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3217 | } else { |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3218 | add_unmap(domain, iova, freelist); |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3219 | /* |
| 3220 | * queue up the release of the unmap to save the 1/6th of the |
| 3221 | * cpu used up by the iotlb flush operation... |
| 3222 | */ |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 3223 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3224 | } |
| 3225 | |
Jiang Liu | d41a4ad | 2014-07-11 14:19:34 +0800 | [diff] [blame] | 3226 | static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr, |
| 3227 | size_t size, enum dma_data_direction dir, |
| 3228 | struct dma_attrs *attrs) |
| 3229 | { |
| 3230 | intel_unmap(dev, dev_addr); |
| 3231 | } |
| 3232 | |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3233 | static void *intel_alloc_coherent(struct device *dev, size_t size, |
Andrzej Pietrasiewicz | baa676f | 2012-03-27 14:28:18 +0200 | [diff] [blame] | 3234 | dma_addr_t *dma_handle, gfp_t flags, |
| 3235 | struct dma_attrs *attrs) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3236 | { |
Akinobu Mita | 3674643 | 2014-06-04 16:06:51 -0700 | [diff] [blame] | 3237 | struct page *page = NULL; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3238 | int order; |
| 3239 | |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 3240 | size = PAGE_ALIGN(size); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3241 | order = get_order(size); |
Alex Williamson | e8bb910 | 2009-11-04 15:59:34 -0700 | [diff] [blame] | 3242 | |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3243 | if (!iommu_no_mapping(dev)) |
Alex Williamson | e8bb910 | 2009-11-04 15:59:34 -0700 | [diff] [blame] | 3244 | flags &= ~(GFP_DMA | GFP_DMA32); |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3245 | else if (dev->coherent_dma_mask < dma_get_required_mask(dev)) { |
| 3246 | if (dev->coherent_dma_mask < DMA_BIT_MASK(32)) |
Alex Williamson | e8bb910 | 2009-11-04 15:59:34 -0700 | [diff] [blame] | 3247 | flags |= GFP_DMA; |
| 3248 | else |
| 3249 | flags |= GFP_DMA32; |
| 3250 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3251 | |
Akinobu Mita | 3674643 | 2014-06-04 16:06:51 -0700 | [diff] [blame] | 3252 | if (flags & __GFP_WAIT) { |
| 3253 | unsigned int count = size >> PAGE_SHIFT; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3254 | |
Akinobu Mita | 3674643 | 2014-06-04 16:06:51 -0700 | [diff] [blame] | 3255 | page = dma_alloc_from_contiguous(dev, count, order); |
| 3256 | if (page && iommu_no_mapping(dev) && |
| 3257 | page_to_phys(page) + size > dev->coherent_dma_mask) { |
| 3258 | dma_release_from_contiguous(dev, page, count); |
| 3259 | page = NULL; |
| 3260 | } |
| 3261 | } |
| 3262 | |
| 3263 | if (!page) |
| 3264 | page = alloc_pages(flags, order); |
| 3265 | if (!page) |
| 3266 | return NULL; |
| 3267 | memset(page_address(page), 0, size); |
| 3268 | |
| 3269 | *dma_handle = __intel_map_single(dev, page_to_phys(page), size, |
FUJITA Tomonori | bb9e6d6 | 2008-10-15 16:08:28 +0900 | [diff] [blame] | 3270 | DMA_BIDIRECTIONAL, |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3271 | dev->coherent_dma_mask); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3272 | if (*dma_handle) |
Akinobu Mita | 3674643 | 2014-06-04 16:06:51 -0700 | [diff] [blame] | 3273 | return page_address(page); |
| 3274 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
| 3275 | __free_pages(page, order); |
| 3276 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3277 | return NULL; |
| 3278 | } |
| 3279 | |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3280 | static void intel_free_coherent(struct device *dev, size_t size, void *vaddr, |
Andrzej Pietrasiewicz | baa676f | 2012-03-27 14:28:18 +0200 | [diff] [blame] | 3281 | dma_addr_t dma_handle, struct dma_attrs *attrs) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3282 | { |
| 3283 | int order; |
Akinobu Mita | 3674643 | 2014-06-04 16:06:51 -0700 | [diff] [blame] | 3284 | struct page *page = virt_to_page(vaddr); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3285 | |
Fenghua Yu | 5b6985c | 2008-10-16 18:02:32 -0700 | [diff] [blame] | 3286 | size = PAGE_ALIGN(size); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3287 | order = get_order(size); |
| 3288 | |
Jiang Liu | d41a4ad | 2014-07-11 14:19:34 +0800 | [diff] [blame] | 3289 | intel_unmap(dev, dma_handle); |
Akinobu Mita | 3674643 | 2014-06-04 16:06:51 -0700 | [diff] [blame] | 3290 | if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT)) |
| 3291 | __free_pages(page, order); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3292 | } |
| 3293 | |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3294 | static void intel_unmap_sg(struct device *dev, struct scatterlist *sglist, |
FUJITA Tomonori | d7ab5c4 | 2009-01-28 21:53:18 +0900 | [diff] [blame] | 3295 | int nelems, enum dma_data_direction dir, |
| 3296 | struct dma_attrs *attrs) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3297 | { |
Jiang Liu | d41a4ad | 2014-07-11 14:19:34 +0800 | [diff] [blame] | 3298 | intel_unmap(dev, sglist[0].dma_address); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3299 | } |
| 3300 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3301 | static int intel_nontranslate_map_sg(struct device *hddev, |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 3302 | struct scatterlist *sglist, int nelems, int dir) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3303 | { |
| 3304 | int i; |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 3305 | struct scatterlist *sg; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3306 | |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 3307 | for_each_sg(sglist, sg, nelems, i) { |
FUJITA Tomonori | 12d4d40 | 2007-10-23 09:32:25 +0200 | [diff] [blame] | 3308 | BUG_ON(!sg_page(sg)); |
David Woodhouse | 4cf2e75 | 2009-02-11 17:23:43 +0000 | [diff] [blame] | 3309 | sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset; |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 3310 | sg->dma_length = sg->length; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3311 | } |
| 3312 | return nelems; |
| 3313 | } |
| 3314 | |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3315 | static int intel_map_sg(struct device *dev, struct scatterlist *sglist, int nelems, |
FUJITA Tomonori | d7ab5c4 | 2009-01-28 21:53:18 +0900 | [diff] [blame] | 3316 | enum dma_data_direction dir, struct dma_attrs *attrs) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3317 | { |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3318 | int i; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3319 | struct dmar_domain *domain; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3320 | size_t size = 0; |
| 3321 | int prot = 0; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3322 | struct iova *iova = NULL; |
| 3323 | int ret; |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 3324 | struct scatterlist *sg; |
David Woodhouse | b536d24 | 2009-06-28 14:49:31 +0100 | [diff] [blame] | 3325 | unsigned long start_vpfn; |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3326 | struct intel_iommu *iommu; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3327 | |
| 3328 | BUG_ON(dir == DMA_NONE); |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3329 | if (iommu_no_mapping(dev)) |
| 3330 | return intel_nontranslate_map_sg(dev, sglist, nelems, dir); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3331 | |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3332 | domain = get_valid_domain_for_dev(dev); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3333 | if (!domain) |
| 3334 | return 0; |
| 3335 | |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3336 | iommu = domain_get_iommu(domain); |
| 3337 | |
David Woodhouse | b536d24 | 2009-06-28 14:49:31 +0100 | [diff] [blame] | 3338 | for_each_sg(sglist, sg, nelems, i) |
David Woodhouse | 88cb6a7 | 2009-06-28 15:03:06 +0100 | [diff] [blame] | 3339 | size += aligned_nrpages(sg->offset, sg->length); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3340 | |
David Woodhouse | 5040a91 | 2014-03-09 16:14:00 -0700 | [diff] [blame] | 3341 | iova = intel_alloc_iova(dev, domain, dma_to_mm_pfn(size), |
| 3342 | *dev->dma_mask); |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3343 | if (!iova) { |
FUJITA Tomonori | c03ab37 | 2007-10-21 16:42:00 -0700 | [diff] [blame] | 3344 | sglist->dma_length = 0; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3345 | return 0; |
| 3346 | } |
| 3347 | |
| 3348 | /* |
| 3349 | * Check if DMAR supports zero-length reads on write only |
| 3350 | * mappings.. |
| 3351 | */ |
| 3352 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \ |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3353 | !cap_zlr(iommu->cap)) |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3354 | prot |= DMA_PTE_READ; |
| 3355 | if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL) |
| 3356 | prot |= DMA_PTE_WRITE; |
| 3357 | |
David Woodhouse | b536d24 | 2009-06-28 14:49:31 +0100 | [diff] [blame] | 3358 | start_vpfn = mm_to_dma_pfn(iova->pfn_lo); |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 3359 | |
Fenghua Yu | f532959 | 2009-08-04 15:09:37 -0700 | [diff] [blame] | 3360 | ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot); |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 3361 | if (unlikely(ret)) { |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 3362 | dma_pte_free_pagetable(domain, start_vpfn, |
| 3363 | start_vpfn + size - 1); |
David Woodhouse | e160549 | 2009-06-29 11:17:38 +0100 | [diff] [blame] | 3364 | __free_iova(&domain->iovad, iova); |
| 3365 | return 0; |
Keshavamurthy, Anil S | f76aec7 | 2007-10-21 16:41:58 -0700 | [diff] [blame] | 3366 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3367 | |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3368 | /* it's a non-present to present mapping. Only flush if caching mode */ |
| 3369 | if (cap_caching_mode(iommu->cap)) |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3370 | iommu_flush_iotlb_psi(iommu, domain->id, start_vpfn, size, 0, 1); |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3371 | else |
Weidong Han | 8c11e79 | 2008-12-08 15:29:22 +0800 | [diff] [blame] | 3372 | iommu_flush_write_buffer(iommu); |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3373 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3374 | return nelems; |
| 3375 | } |
| 3376 | |
FUJITA Tomonori | dfb805e | 2009-01-28 21:53:17 +0900 | [diff] [blame] | 3377 | static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr) |
| 3378 | { |
| 3379 | return !dma_addr; |
| 3380 | } |
| 3381 | |
FUJITA Tomonori | 160c1d8 | 2009-01-05 23:59:02 +0900 | [diff] [blame] | 3382 | struct dma_map_ops intel_dma_ops = { |
Andrzej Pietrasiewicz | baa676f | 2012-03-27 14:28:18 +0200 | [diff] [blame] | 3383 | .alloc = intel_alloc_coherent, |
| 3384 | .free = intel_free_coherent, |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3385 | .map_sg = intel_map_sg, |
| 3386 | .unmap_sg = intel_unmap_sg, |
FUJITA Tomonori | ffbbef5 | 2009-01-05 23:47:26 +0900 | [diff] [blame] | 3387 | .map_page = intel_map_page, |
| 3388 | .unmap_page = intel_unmap_page, |
FUJITA Tomonori | dfb805e | 2009-01-28 21:53:17 +0900 | [diff] [blame] | 3389 | .mapping_error = intel_mapping_error, |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3390 | }; |
| 3391 | |
| 3392 | static inline int iommu_domain_cache_init(void) |
| 3393 | { |
| 3394 | int ret = 0; |
| 3395 | |
| 3396 | iommu_domain_cache = kmem_cache_create("iommu_domain", |
| 3397 | sizeof(struct dmar_domain), |
| 3398 | 0, |
| 3399 | SLAB_HWCACHE_ALIGN, |
| 3400 | |
| 3401 | NULL); |
| 3402 | if (!iommu_domain_cache) { |
| 3403 | printk(KERN_ERR "Couldn't create iommu_domain cache\n"); |
| 3404 | ret = -ENOMEM; |
| 3405 | } |
| 3406 | |
| 3407 | return ret; |
| 3408 | } |
| 3409 | |
| 3410 | static inline int iommu_devinfo_cache_init(void) |
| 3411 | { |
| 3412 | int ret = 0; |
| 3413 | |
| 3414 | iommu_devinfo_cache = kmem_cache_create("iommu_devinfo", |
| 3415 | sizeof(struct device_domain_info), |
| 3416 | 0, |
| 3417 | SLAB_HWCACHE_ALIGN, |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3418 | NULL); |
| 3419 | if (!iommu_devinfo_cache) { |
| 3420 | printk(KERN_ERR "Couldn't create devinfo cache\n"); |
| 3421 | ret = -ENOMEM; |
| 3422 | } |
| 3423 | |
| 3424 | return ret; |
| 3425 | } |
| 3426 | |
| 3427 | static inline int iommu_iova_cache_init(void) |
| 3428 | { |
| 3429 | int ret = 0; |
| 3430 | |
| 3431 | iommu_iova_cache = kmem_cache_create("iommu_iova", |
| 3432 | sizeof(struct iova), |
| 3433 | 0, |
| 3434 | SLAB_HWCACHE_ALIGN, |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3435 | NULL); |
| 3436 | if (!iommu_iova_cache) { |
| 3437 | printk(KERN_ERR "Couldn't create iova cache\n"); |
| 3438 | ret = -ENOMEM; |
| 3439 | } |
| 3440 | |
| 3441 | return ret; |
| 3442 | } |
| 3443 | |
| 3444 | static int __init iommu_init_mempool(void) |
| 3445 | { |
| 3446 | int ret; |
| 3447 | ret = iommu_iova_cache_init(); |
| 3448 | if (ret) |
| 3449 | return ret; |
| 3450 | |
| 3451 | ret = iommu_domain_cache_init(); |
| 3452 | if (ret) |
| 3453 | goto domain_error; |
| 3454 | |
| 3455 | ret = iommu_devinfo_cache_init(); |
| 3456 | if (!ret) |
| 3457 | return ret; |
| 3458 | |
| 3459 | kmem_cache_destroy(iommu_domain_cache); |
| 3460 | domain_error: |
| 3461 | kmem_cache_destroy(iommu_iova_cache); |
| 3462 | |
| 3463 | return -ENOMEM; |
| 3464 | } |
| 3465 | |
| 3466 | static void __init iommu_exit_mempool(void) |
| 3467 | { |
| 3468 | kmem_cache_destroy(iommu_devinfo_cache); |
| 3469 | kmem_cache_destroy(iommu_domain_cache); |
| 3470 | kmem_cache_destroy(iommu_iova_cache); |
| 3471 | |
| 3472 | } |
| 3473 | |
Dan Williams | 556ab45 | 2010-07-23 15:47:56 -0700 | [diff] [blame] | 3474 | static void quirk_ioat_snb_local_iommu(struct pci_dev *pdev) |
| 3475 | { |
| 3476 | struct dmar_drhd_unit *drhd; |
| 3477 | u32 vtbar; |
| 3478 | int rc; |
| 3479 | |
| 3480 | /* We know that this device on this chipset has its own IOMMU. |
| 3481 | * If we find it under a different IOMMU, then the BIOS is lying |
| 3482 | * to us. Hope that the IOMMU for this device is actually |
| 3483 | * disabled, and it needs no translation... |
| 3484 | */ |
| 3485 | rc = pci_bus_read_config_dword(pdev->bus, PCI_DEVFN(0, 0), 0xb0, &vtbar); |
| 3486 | if (rc) { |
| 3487 | /* "can't" happen */ |
| 3488 | dev_info(&pdev->dev, "failed to run vt-d quirk\n"); |
| 3489 | return; |
| 3490 | } |
| 3491 | vtbar &= 0xffff0000; |
| 3492 | |
| 3493 | /* we know that the this iommu should be at offset 0xa000 from vtbar */ |
| 3494 | drhd = dmar_find_matched_drhd_unit(pdev); |
| 3495 | if (WARN_TAINT_ONCE(!drhd || drhd->reg_base_addr - vtbar != 0xa000, |
| 3496 | TAINT_FIRMWARE_WORKAROUND, |
| 3497 | "BIOS assigned incorrect VT-d unit for Intel(R) QuickData Technology device\n")) |
| 3498 | pdev->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; |
| 3499 | } |
| 3500 | DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IOAT_SNB, quirk_ioat_snb_local_iommu); |
| 3501 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3502 | static void __init init_no_remapping_devices(void) |
| 3503 | { |
| 3504 | struct dmar_drhd_unit *drhd; |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 3505 | struct device *dev; |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 3506 | int i; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3507 | |
| 3508 | for_each_drhd_unit(drhd) { |
| 3509 | if (!drhd->include_all) { |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 3510 | for_each_active_dev_scope(drhd->devices, |
| 3511 | drhd->devices_cnt, i, dev) |
| 3512 | break; |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 3513 | /* ignore DMAR unit if no devices exist */ |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3514 | if (i == drhd->devices_cnt) |
| 3515 | drhd->ignored = 1; |
| 3516 | } |
| 3517 | } |
| 3518 | |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 3519 | for_each_active_drhd_unit(drhd) { |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 3520 | if (drhd->include_all) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3521 | continue; |
| 3522 | |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 3523 | for_each_active_dev_scope(drhd->devices, |
| 3524 | drhd->devices_cnt, i, dev) |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 3525 | if (!dev_is_pci(dev) || !IS_GFX_DEVICE(to_pci_dev(dev))) |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3526 | break; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3527 | if (i < drhd->devices_cnt) |
| 3528 | continue; |
| 3529 | |
David Woodhouse | c0771df | 2011-10-14 20:59:46 +0100 | [diff] [blame] | 3530 | /* This IOMMU has *only* gfx devices. Either bypass it or |
| 3531 | set the gfx_mapped flag, as appropriate */ |
| 3532 | if (dmar_map_gfx) { |
| 3533 | intel_iommu_gfx_mapped = 1; |
| 3534 | } else { |
| 3535 | drhd->ignored = 1; |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 3536 | for_each_active_dev_scope(drhd->devices, |
| 3537 | drhd->devices_cnt, i, dev) |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 3538 | dev->archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 3539 | } |
| 3540 | } |
| 3541 | } |
| 3542 | |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3543 | #ifdef CONFIG_SUSPEND |
| 3544 | static int init_iommu_hw(void) |
| 3545 | { |
| 3546 | struct dmar_drhd_unit *drhd; |
| 3547 | struct intel_iommu *iommu = NULL; |
| 3548 | |
| 3549 | for_each_active_iommu(iommu, drhd) |
| 3550 | if (iommu->qi) |
| 3551 | dmar_reenable_qi(iommu); |
| 3552 | |
Joseph Cihula | b779260 | 2011-05-03 00:08:37 -0700 | [diff] [blame] | 3553 | for_each_iommu(iommu, drhd) { |
| 3554 | if (drhd->ignored) { |
| 3555 | /* |
| 3556 | * we always have to disable PMRs or DMA may fail on |
| 3557 | * this device |
| 3558 | */ |
| 3559 | if (force_on) |
| 3560 | iommu_disable_protect_mem_regions(iommu); |
| 3561 | continue; |
| 3562 | } |
| 3563 | |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3564 | iommu_flush_write_buffer(iommu); |
| 3565 | |
| 3566 | iommu_set_root_entry(iommu); |
| 3567 | |
| 3568 | iommu->flush.flush_context(iommu, 0, 0, 0, |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3569 | DMA_CCMD_GLOBAL_INVL); |
Jiang Liu | 2a41cce | 2014-07-11 14:19:33 +0800 | [diff] [blame] | 3570 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH); |
| 3571 | iommu_enable_translation(iommu); |
David Woodhouse | b94996c | 2009-09-19 15:28:12 -0700 | [diff] [blame] | 3572 | iommu_disable_protect_mem_regions(iommu); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3573 | } |
| 3574 | |
| 3575 | return 0; |
| 3576 | } |
| 3577 | |
| 3578 | static void iommu_flush_all(void) |
| 3579 | { |
| 3580 | struct dmar_drhd_unit *drhd; |
| 3581 | struct intel_iommu *iommu; |
| 3582 | |
| 3583 | for_each_active_iommu(iommu, drhd) { |
| 3584 | iommu->flush.flush_context(iommu, 0, 0, 0, |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3585 | DMA_CCMD_GLOBAL_INVL); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3586 | iommu->flush.flush_iotlb(iommu, 0, 0, 0, |
David Woodhouse | 1f0ef2a | 2009-05-10 19:58:49 +0100 | [diff] [blame] | 3587 | DMA_TLB_GLOBAL_FLUSH); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3588 | } |
| 3589 | } |
| 3590 | |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 3591 | static int iommu_suspend(void) |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3592 | { |
| 3593 | struct dmar_drhd_unit *drhd; |
| 3594 | struct intel_iommu *iommu = NULL; |
| 3595 | unsigned long flag; |
| 3596 | |
| 3597 | for_each_active_iommu(iommu, drhd) { |
| 3598 | iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS, |
| 3599 | GFP_ATOMIC); |
| 3600 | if (!iommu->iommu_state) |
| 3601 | goto nomem; |
| 3602 | } |
| 3603 | |
| 3604 | iommu_flush_all(); |
| 3605 | |
| 3606 | for_each_active_iommu(iommu, drhd) { |
| 3607 | iommu_disable_translation(iommu); |
| 3608 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 3609 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3610 | |
| 3611 | iommu->iommu_state[SR_DMAR_FECTL_REG] = |
| 3612 | readl(iommu->reg + DMAR_FECTL_REG); |
| 3613 | iommu->iommu_state[SR_DMAR_FEDATA_REG] = |
| 3614 | readl(iommu->reg + DMAR_FEDATA_REG); |
| 3615 | iommu->iommu_state[SR_DMAR_FEADDR_REG] = |
| 3616 | readl(iommu->reg + DMAR_FEADDR_REG); |
| 3617 | iommu->iommu_state[SR_DMAR_FEUADDR_REG] = |
| 3618 | readl(iommu->reg + DMAR_FEUADDR_REG); |
| 3619 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 3620 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3621 | } |
| 3622 | return 0; |
| 3623 | |
| 3624 | nomem: |
| 3625 | for_each_active_iommu(iommu, drhd) |
| 3626 | kfree(iommu->iommu_state); |
| 3627 | |
| 3628 | return -ENOMEM; |
| 3629 | } |
| 3630 | |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 3631 | static void iommu_resume(void) |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3632 | { |
| 3633 | struct dmar_drhd_unit *drhd; |
| 3634 | struct intel_iommu *iommu = NULL; |
| 3635 | unsigned long flag; |
| 3636 | |
| 3637 | if (init_iommu_hw()) { |
Joseph Cihula | b779260 | 2011-05-03 00:08:37 -0700 | [diff] [blame] | 3638 | if (force_on) |
| 3639 | panic("tboot: IOMMU setup failed, DMAR can not resume!\n"); |
| 3640 | else |
| 3641 | WARN(1, "IOMMU setup failed, DMAR can not resume!\n"); |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 3642 | return; |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3643 | } |
| 3644 | |
| 3645 | for_each_active_iommu(iommu, drhd) { |
| 3646 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 3647 | raw_spin_lock_irqsave(&iommu->register_lock, flag); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3648 | |
| 3649 | writel(iommu->iommu_state[SR_DMAR_FECTL_REG], |
| 3650 | iommu->reg + DMAR_FECTL_REG); |
| 3651 | writel(iommu->iommu_state[SR_DMAR_FEDATA_REG], |
| 3652 | iommu->reg + DMAR_FEDATA_REG); |
| 3653 | writel(iommu->iommu_state[SR_DMAR_FEADDR_REG], |
| 3654 | iommu->reg + DMAR_FEADDR_REG); |
| 3655 | writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG], |
| 3656 | iommu->reg + DMAR_FEUADDR_REG); |
| 3657 | |
Thomas Gleixner | 1f5b3c3 | 2011-07-19 16:19:51 +0200 | [diff] [blame] | 3658 | raw_spin_unlock_irqrestore(&iommu->register_lock, flag); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3659 | } |
| 3660 | |
| 3661 | for_each_active_iommu(iommu, drhd) |
| 3662 | kfree(iommu->iommu_state); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3663 | } |
| 3664 | |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 3665 | static struct syscore_ops iommu_syscore_ops = { |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3666 | .resume = iommu_resume, |
| 3667 | .suspend = iommu_suspend, |
| 3668 | }; |
| 3669 | |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 3670 | static void __init init_iommu_pm_ops(void) |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3671 | { |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 3672 | register_syscore_ops(&iommu_syscore_ops); |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3673 | } |
| 3674 | |
| 3675 | #else |
Rafael J. Wysocki | 99592ba | 2011-06-07 21:32:31 +0200 | [diff] [blame] | 3676 | static inline void init_iommu_pm_ops(void) {} |
Fenghua Yu | f59c7b6 | 2009-03-27 14:22:42 -0700 | [diff] [blame] | 3677 | #endif /* CONFIG_PM */ |
| 3678 | |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3679 | |
Jiang Liu | c2a0b53 | 2014-11-09 22:47:56 +0800 | [diff] [blame] | 3680 | int __init dmar_parse_one_rmrr(struct acpi_dmar_header *header, void *arg) |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3681 | { |
| 3682 | struct acpi_dmar_reserved_memory *rmrr; |
| 3683 | struct dmar_rmrr_unit *rmrru; |
| 3684 | |
| 3685 | rmrru = kzalloc(sizeof(*rmrru), GFP_KERNEL); |
| 3686 | if (!rmrru) |
| 3687 | return -ENOMEM; |
| 3688 | |
| 3689 | rmrru->hdr = header; |
| 3690 | rmrr = (struct acpi_dmar_reserved_memory *)header; |
| 3691 | rmrru->base_address = rmrr->base_address; |
| 3692 | rmrru->end_address = rmrr->end_address; |
Jiang Liu | 2e45528 | 2014-02-19 14:07:36 +0800 | [diff] [blame] | 3693 | rmrru->devices = dmar_alloc_dev_scope((void *)(rmrr + 1), |
| 3694 | ((void *)rmrr) + rmrr->header.length, |
| 3695 | &rmrru->devices_cnt); |
| 3696 | if (rmrru->devices_cnt && rmrru->devices == NULL) { |
| 3697 | kfree(rmrru); |
| 3698 | return -ENOMEM; |
| 3699 | } |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3700 | |
Jiang Liu | 2e45528 | 2014-02-19 14:07:36 +0800 | [diff] [blame] | 3701 | list_add(&rmrru->list, &dmar_rmrr_units); |
| 3702 | |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3703 | return 0; |
| 3704 | } |
| 3705 | |
Jiang Liu | c2a0b53 | 2014-11-09 22:47:56 +0800 | [diff] [blame] | 3706 | int __init dmar_parse_one_atsr(struct acpi_dmar_header *hdr, void *arg) |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3707 | { |
| 3708 | struct acpi_dmar_atsr *atsr; |
| 3709 | struct dmar_atsr_unit *atsru; |
| 3710 | |
| 3711 | atsr = container_of(hdr, struct acpi_dmar_atsr, header); |
| 3712 | atsru = kzalloc(sizeof(*atsru), GFP_KERNEL); |
| 3713 | if (!atsru) |
| 3714 | return -ENOMEM; |
| 3715 | |
| 3716 | atsru->hdr = hdr; |
| 3717 | atsru->include_all = atsr->flags & 0x1; |
Jiang Liu | 2e45528 | 2014-02-19 14:07:36 +0800 | [diff] [blame] | 3718 | if (!atsru->include_all) { |
| 3719 | atsru->devices = dmar_alloc_dev_scope((void *)(atsr + 1), |
| 3720 | (void *)atsr + atsr->header.length, |
| 3721 | &atsru->devices_cnt); |
| 3722 | if (atsru->devices_cnt && atsru->devices == NULL) { |
| 3723 | kfree(atsru); |
| 3724 | return -ENOMEM; |
| 3725 | } |
| 3726 | } |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3727 | |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 3728 | list_add_rcu(&atsru->list, &dmar_atsr_units); |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3729 | |
| 3730 | return 0; |
| 3731 | } |
| 3732 | |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 3733 | static void intel_iommu_free_atsr(struct dmar_atsr_unit *atsru) |
| 3734 | { |
| 3735 | dmar_free_dev_scope(&atsru->devices, &atsru->devices_cnt); |
| 3736 | kfree(atsru); |
| 3737 | } |
| 3738 | |
| 3739 | static void intel_iommu_free_dmars(void) |
| 3740 | { |
| 3741 | struct dmar_rmrr_unit *rmrru, *rmrr_n; |
| 3742 | struct dmar_atsr_unit *atsru, *atsr_n; |
| 3743 | |
| 3744 | list_for_each_entry_safe(rmrru, rmrr_n, &dmar_rmrr_units, list) { |
| 3745 | list_del(&rmrru->list); |
| 3746 | dmar_free_dev_scope(&rmrru->devices, &rmrru->devices_cnt); |
| 3747 | kfree(rmrru); |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3748 | } |
| 3749 | |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 3750 | list_for_each_entry_safe(atsru, atsr_n, &dmar_atsr_units, list) { |
| 3751 | list_del(&atsru->list); |
| 3752 | intel_iommu_free_atsr(atsru); |
| 3753 | } |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3754 | } |
| 3755 | |
| 3756 | int dmar_find_matched_atsr_unit(struct pci_dev *dev) |
| 3757 | { |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 3758 | int i, ret = 1; |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3759 | struct pci_bus *bus; |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 3760 | struct pci_dev *bridge = NULL; |
| 3761 | struct device *tmp; |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3762 | struct acpi_dmar_atsr *atsr; |
| 3763 | struct dmar_atsr_unit *atsru; |
| 3764 | |
| 3765 | dev = pci_physfn(dev); |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3766 | for (bus = dev->bus; bus; bus = bus->parent) { |
Jiang Liu | b5f82dd | 2014-02-19 14:07:31 +0800 | [diff] [blame] | 3767 | bridge = bus->self; |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3768 | if (!bridge || !pci_is_pcie(bridge) || |
Yijing Wang | 62f87c0 | 2012-07-24 17:20:03 +0800 | [diff] [blame] | 3769 | pci_pcie_type(bridge) == PCI_EXP_TYPE_PCI_BRIDGE) |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3770 | return 0; |
Jiang Liu | b5f82dd | 2014-02-19 14:07:31 +0800 | [diff] [blame] | 3771 | if (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3772 | break; |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3773 | } |
Jiang Liu | b5f82dd | 2014-02-19 14:07:31 +0800 | [diff] [blame] | 3774 | if (!bridge) |
| 3775 | return 0; |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3776 | |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 3777 | rcu_read_lock(); |
Jiang Liu | b5f82dd | 2014-02-19 14:07:31 +0800 | [diff] [blame] | 3778 | list_for_each_entry_rcu(atsru, &dmar_atsr_units, list) { |
| 3779 | atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header); |
| 3780 | if (atsr->segment != pci_domain_nr(dev->bus)) |
| 3781 | continue; |
| 3782 | |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 3783 | for_each_dev_scope(atsru->devices, atsru->devices_cnt, i, tmp) |
David Woodhouse | 832bd85 | 2014-03-07 15:08:36 +0000 | [diff] [blame] | 3784 | if (tmp == &bridge->dev) |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 3785 | goto out; |
Jiang Liu | b5f82dd | 2014-02-19 14:07:31 +0800 | [diff] [blame] | 3786 | |
| 3787 | if (atsru->include_all) |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 3788 | goto out; |
Jiang Liu | b5f82dd | 2014-02-19 14:07:31 +0800 | [diff] [blame] | 3789 | } |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 3790 | ret = 0; |
| 3791 | out: |
Jiang Liu | 0e24261 | 2014-02-19 14:07:34 +0800 | [diff] [blame] | 3792 | rcu_read_unlock(); |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3793 | |
Jiang Liu | b683b23 | 2014-02-19 14:07:32 +0800 | [diff] [blame] | 3794 | return ret; |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 3795 | } |
| 3796 | |
Jiang Liu | 59ce051 | 2014-02-19 14:07:35 +0800 | [diff] [blame] | 3797 | int dmar_iommu_notify_scope_dev(struct dmar_pci_notify_info *info) |
| 3798 | { |
| 3799 | int ret = 0; |
| 3800 | struct dmar_rmrr_unit *rmrru; |
| 3801 | struct dmar_atsr_unit *atsru; |
| 3802 | struct acpi_dmar_atsr *atsr; |
| 3803 | struct acpi_dmar_reserved_memory *rmrr; |
| 3804 | |
| 3805 | if (!intel_iommu_enabled && system_state != SYSTEM_BOOTING) |
| 3806 | return 0; |
| 3807 | |
| 3808 | list_for_each_entry(rmrru, &dmar_rmrr_units, list) { |
| 3809 | rmrr = container_of(rmrru->hdr, |
| 3810 | struct acpi_dmar_reserved_memory, header); |
| 3811 | if (info->event == BUS_NOTIFY_ADD_DEVICE) { |
| 3812 | ret = dmar_insert_dev_scope(info, (void *)(rmrr + 1), |
| 3813 | ((void *)rmrr) + rmrr->header.length, |
| 3814 | rmrr->segment, rmrru->devices, |
| 3815 | rmrru->devices_cnt); |
Jiang Liu | 27e2495 | 2014-06-20 15:08:06 +0800 | [diff] [blame] | 3816 | if(ret < 0) |
Jiang Liu | 59ce051 | 2014-02-19 14:07:35 +0800 | [diff] [blame] | 3817 | return ret; |
| 3818 | } else if (info->event == BUS_NOTIFY_DEL_DEVICE) { |
Jiang Liu | 27e2495 | 2014-06-20 15:08:06 +0800 | [diff] [blame] | 3819 | dmar_remove_dev_scope(info, rmrr->segment, |
| 3820 | rmrru->devices, rmrru->devices_cnt); |
Jiang Liu | 59ce051 | 2014-02-19 14:07:35 +0800 | [diff] [blame] | 3821 | } |
| 3822 | } |
| 3823 | |
| 3824 | list_for_each_entry(atsru, &dmar_atsr_units, list) { |
| 3825 | if (atsru->include_all) |
| 3826 | continue; |
| 3827 | |
| 3828 | atsr = container_of(atsru->hdr, struct acpi_dmar_atsr, header); |
| 3829 | if (info->event == BUS_NOTIFY_ADD_DEVICE) { |
| 3830 | ret = dmar_insert_dev_scope(info, (void *)(atsr + 1), |
| 3831 | (void *)atsr + atsr->header.length, |
| 3832 | atsr->segment, atsru->devices, |
| 3833 | atsru->devices_cnt); |
| 3834 | if (ret > 0) |
| 3835 | break; |
| 3836 | else if(ret < 0) |
| 3837 | return ret; |
| 3838 | } else if (info->event == BUS_NOTIFY_DEL_DEVICE) { |
| 3839 | if (dmar_remove_dev_scope(info, atsr->segment, |
| 3840 | atsru->devices, atsru->devices_cnt)) |
| 3841 | break; |
| 3842 | } |
| 3843 | } |
| 3844 | |
| 3845 | return 0; |
| 3846 | } |
| 3847 | |
Fenghua Yu | 99dcade | 2009-11-11 07:23:06 -0800 | [diff] [blame] | 3848 | /* |
| 3849 | * Here we only respond to action of unbound device from driver. |
| 3850 | * |
| 3851 | * Added device is not attached to its DMAR domain here yet. That will happen |
| 3852 | * when mapping the device to iova. |
| 3853 | */ |
| 3854 | static int device_notifier(struct notifier_block *nb, |
| 3855 | unsigned long action, void *data) |
| 3856 | { |
| 3857 | struct device *dev = data; |
Fenghua Yu | 99dcade | 2009-11-11 07:23:06 -0800 | [diff] [blame] | 3858 | struct dmar_domain *domain; |
| 3859 | |
David Woodhouse | 3d89194 | 2014-03-06 15:59:26 +0000 | [diff] [blame] | 3860 | if (iommu_dummy(dev)) |
David Woodhouse | 44cd613 | 2009-12-02 10:18:30 +0000 | [diff] [blame] | 3861 | return 0; |
| 3862 | |
Joerg Roedel | 1196c2f | 2014-09-30 13:02:03 +0200 | [diff] [blame] | 3863 | if (action != BUS_NOTIFY_REMOVED_DEVICE) |
Jiang Liu | 7e7dfab | 2014-02-19 14:07:23 +0800 | [diff] [blame] | 3864 | return 0; |
| 3865 | |
Joerg Roedel | e7f9fa5 | 2014-08-05 12:55:45 +0200 | [diff] [blame] | 3866 | /* |
| 3867 | * If the device is still attached to a device driver we can't |
| 3868 | * tear down the domain yet as DMA mappings may still be in use. |
| 3869 | * Wait for the BUS_NOTIFY_UNBOUND_DRIVER event to do that. |
| 3870 | */ |
| 3871 | if (action == BUS_NOTIFY_DEL_DEVICE && dev->driver != NULL) |
| 3872 | return 0; |
| 3873 | |
David Woodhouse | 1525a29 | 2014-03-06 16:19:30 +0000 | [diff] [blame] | 3874 | domain = find_domain(dev); |
Fenghua Yu | 99dcade | 2009-11-11 07:23:06 -0800 | [diff] [blame] | 3875 | if (!domain) |
| 3876 | return 0; |
| 3877 | |
Jiang Liu | 3a5670e | 2014-02-19 14:07:33 +0800 | [diff] [blame] | 3878 | down_read(&dmar_global_lock); |
David Woodhouse | bf9c9ed | 2014-03-09 16:19:13 -0700 | [diff] [blame] | 3879 | domain_remove_one_dev_info(domain, dev); |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 3880 | if (!domain_type_is_vm_or_si(domain) && list_empty(&domain->devices)) |
Jiang Liu | 7e7dfab | 2014-02-19 14:07:23 +0800 | [diff] [blame] | 3881 | domain_exit(domain); |
Jiang Liu | 3a5670e | 2014-02-19 14:07:33 +0800 | [diff] [blame] | 3882 | up_read(&dmar_global_lock); |
Alex Williamson | a97590e | 2011-03-04 14:52:16 -0700 | [diff] [blame] | 3883 | |
Fenghua Yu | 99dcade | 2009-11-11 07:23:06 -0800 | [diff] [blame] | 3884 | return 0; |
| 3885 | } |
| 3886 | |
| 3887 | static struct notifier_block device_nb = { |
| 3888 | .notifier_call = device_notifier, |
| 3889 | }; |
| 3890 | |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 3891 | static int intel_iommu_memory_notifier(struct notifier_block *nb, |
| 3892 | unsigned long val, void *v) |
| 3893 | { |
| 3894 | struct memory_notify *mhp = v; |
| 3895 | unsigned long long start, end; |
| 3896 | unsigned long start_vpfn, last_vpfn; |
| 3897 | |
| 3898 | switch (val) { |
| 3899 | case MEM_GOING_ONLINE: |
| 3900 | start = mhp->start_pfn << PAGE_SHIFT; |
| 3901 | end = ((mhp->start_pfn + mhp->nr_pages) << PAGE_SHIFT) - 1; |
| 3902 | if (iommu_domain_identity_map(si_domain, start, end)) { |
| 3903 | pr_warn("dmar: failed to build identity map for [%llx-%llx]\n", |
| 3904 | start, end); |
| 3905 | return NOTIFY_BAD; |
| 3906 | } |
| 3907 | break; |
| 3908 | |
| 3909 | case MEM_OFFLINE: |
| 3910 | case MEM_CANCEL_ONLINE: |
| 3911 | start_vpfn = mm_to_dma_pfn(mhp->start_pfn); |
| 3912 | last_vpfn = mm_to_dma_pfn(mhp->start_pfn + mhp->nr_pages - 1); |
| 3913 | while (start_vpfn <= last_vpfn) { |
| 3914 | struct iova *iova; |
| 3915 | struct dmar_drhd_unit *drhd; |
| 3916 | struct intel_iommu *iommu; |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3917 | struct page *freelist; |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 3918 | |
| 3919 | iova = find_iova(&si_domain->iovad, start_vpfn); |
| 3920 | if (iova == NULL) { |
| 3921 | pr_debug("dmar: failed get IOVA for PFN %lx\n", |
| 3922 | start_vpfn); |
| 3923 | break; |
| 3924 | } |
| 3925 | |
| 3926 | iova = split_and_remove_iova(&si_domain->iovad, iova, |
| 3927 | start_vpfn, last_vpfn); |
| 3928 | if (iova == NULL) { |
| 3929 | pr_warn("dmar: failed to split IOVA PFN [%lx-%lx]\n", |
| 3930 | start_vpfn, last_vpfn); |
| 3931 | return NOTIFY_BAD; |
| 3932 | } |
| 3933 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3934 | freelist = domain_unmap(si_domain, iova->pfn_lo, |
| 3935 | iova->pfn_hi); |
| 3936 | |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 3937 | rcu_read_lock(); |
| 3938 | for_each_active_iommu(iommu, drhd) |
| 3939 | iommu_flush_iotlb_psi(iommu, si_domain->id, |
Jiang Liu | a156ef9 | 2014-07-11 14:19:36 +0800 | [diff] [blame] | 3940 | iova->pfn_lo, iova_size(iova), |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3941 | !freelist, 0); |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 3942 | rcu_read_unlock(); |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 3943 | dma_free_pagelist(freelist); |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 3944 | |
| 3945 | start_vpfn = iova->pfn_hi + 1; |
| 3946 | free_iova_mem(iova); |
| 3947 | } |
| 3948 | break; |
| 3949 | } |
| 3950 | |
| 3951 | return NOTIFY_OK; |
| 3952 | } |
| 3953 | |
| 3954 | static struct notifier_block intel_iommu_memory_nb = { |
| 3955 | .notifier_call = intel_iommu_memory_notifier, |
| 3956 | .priority = 0 |
| 3957 | }; |
| 3958 | |
Alex Williamson | a5459cf | 2014-06-12 16:12:31 -0600 | [diff] [blame] | 3959 | |
| 3960 | static ssize_t intel_iommu_show_version(struct device *dev, |
| 3961 | struct device_attribute *attr, |
| 3962 | char *buf) |
| 3963 | { |
| 3964 | struct intel_iommu *iommu = dev_get_drvdata(dev); |
| 3965 | u32 ver = readl(iommu->reg + DMAR_VER_REG); |
| 3966 | return sprintf(buf, "%d:%d\n", |
| 3967 | DMAR_VER_MAJOR(ver), DMAR_VER_MINOR(ver)); |
| 3968 | } |
| 3969 | static DEVICE_ATTR(version, S_IRUGO, intel_iommu_show_version, NULL); |
| 3970 | |
| 3971 | static ssize_t intel_iommu_show_address(struct device *dev, |
| 3972 | struct device_attribute *attr, |
| 3973 | char *buf) |
| 3974 | { |
| 3975 | struct intel_iommu *iommu = dev_get_drvdata(dev); |
| 3976 | return sprintf(buf, "%llx\n", iommu->reg_phys); |
| 3977 | } |
| 3978 | static DEVICE_ATTR(address, S_IRUGO, intel_iommu_show_address, NULL); |
| 3979 | |
| 3980 | static ssize_t intel_iommu_show_cap(struct device *dev, |
| 3981 | struct device_attribute *attr, |
| 3982 | char *buf) |
| 3983 | { |
| 3984 | struct intel_iommu *iommu = dev_get_drvdata(dev); |
| 3985 | return sprintf(buf, "%llx\n", iommu->cap); |
| 3986 | } |
| 3987 | static DEVICE_ATTR(cap, S_IRUGO, intel_iommu_show_cap, NULL); |
| 3988 | |
| 3989 | static ssize_t intel_iommu_show_ecap(struct device *dev, |
| 3990 | struct device_attribute *attr, |
| 3991 | char *buf) |
| 3992 | { |
| 3993 | struct intel_iommu *iommu = dev_get_drvdata(dev); |
| 3994 | return sprintf(buf, "%llx\n", iommu->ecap); |
| 3995 | } |
| 3996 | static DEVICE_ATTR(ecap, S_IRUGO, intel_iommu_show_ecap, NULL); |
| 3997 | |
| 3998 | static struct attribute *intel_iommu_attrs[] = { |
| 3999 | &dev_attr_version.attr, |
| 4000 | &dev_attr_address.attr, |
| 4001 | &dev_attr_cap.attr, |
| 4002 | &dev_attr_ecap.attr, |
| 4003 | NULL, |
| 4004 | }; |
| 4005 | |
| 4006 | static struct attribute_group intel_iommu_group = { |
| 4007 | .name = "intel-iommu", |
| 4008 | .attrs = intel_iommu_attrs, |
| 4009 | }; |
| 4010 | |
| 4011 | const struct attribute_group *intel_iommu_groups[] = { |
| 4012 | &intel_iommu_group, |
| 4013 | NULL, |
| 4014 | }; |
| 4015 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 4016 | int __init intel_iommu_init(void) |
| 4017 | { |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 4018 | int ret = -ENODEV; |
Takao Indoh | 3a93c84 | 2013-04-23 17:35:03 +0900 | [diff] [blame] | 4019 | struct dmar_drhd_unit *drhd; |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 4020 | struct intel_iommu *iommu; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 4021 | |
Joseph Cihula | a59b50e | 2009-06-30 19:31:10 -0700 | [diff] [blame] | 4022 | /* VT-d is required for a TXT/tboot launch, so enforce that */ |
| 4023 | force_on = tboot_force_iommu(); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 4024 | |
Jiang Liu | 3a5670e | 2014-02-19 14:07:33 +0800 | [diff] [blame] | 4025 | if (iommu_init_mempool()) { |
| 4026 | if (force_on) |
| 4027 | panic("tboot: Failed to initialize iommu memory\n"); |
| 4028 | return -ENOMEM; |
| 4029 | } |
| 4030 | |
| 4031 | down_write(&dmar_global_lock); |
Joseph Cihula | a59b50e | 2009-06-30 19:31:10 -0700 | [diff] [blame] | 4032 | if (dmar_table_init()) { |
| 4033 | if (force_on) |
| 4034 | panic("tboot: Failed to initialize DMAR table\n"); |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 4035 | goto out_free_dmar; |
Joseph Cihula | a59b50e | 2009-06-30 19:31:10 -0700 | [diff] [blame] | 4036 | } |
| 4037 | |
Takao Indoh | 3a93c84 | 2013-04-23 17:35:03 +0900 | [diff] [blame] | 4038 | /* |
| 4039 | * Disable translation if already enabled prior to OS handover. |
| 4040 | */ |
Jiang Liu | 7c91977 | 2014-01-06 14:18:18 +0800 | [diff] [blame] | 4041 | for_each_active_iommu(iommu, drhd) |
Takao Indoh | 3a93c84 | 2013-04-23 17:35:03 +0900 | [diff] [blame] | 4042 | if (iommu->gcmd & DMA_GCMD_TE) |
| 4043 | iommu_disable_translation(iommu); |
Takao Indoh | 3a93c84 | 2013-04-23 17:35:03 +0900 | [diff] [blame] | 4044 | |
Suresh Siddha | c2c7286 | 2011-08-23 17:05:19 -0700 | [diff] [blame] | 4045 | if (dmar_dev_scope_init() < 0) { |
Joseph Cihula | a59b50e | 2009-06-30 19:31:10 -0700 | [diff] [blame] | 4046 | if (force_on) |
| 4047 | panic("tboot: Failed to initialize DMAR device scope\n"); |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 4048 | goto out_free_dmar; |
Joseph Cihula | a59b50e | 2009-06-30 19:31:10 -0700 | [diff] [blame] | 4049 | } |
Suresh Siddha | 1886e8a | 2008-07-10 11:16:37 -0700 | [diff] [blame] | 4050 | |
FUJITA Tomonori | 75f1cdf | 2009-11-10 19:46:20 +0900 | [diff] [blame] | 4051 | if (no_iommu || dmar_disabled) |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 4052 | goto out_free_dmar; |
Suresh Siddha | 2ae2101 | 2008-07-10 11:16:43 -0700 | [diff] [blame] | 4053 | |
Suresh Siddha | 318fe7d | 2011-08-23 17:05:20 -0700 | [diff] [blame] | 4054 | if (list_empty(&dmar_rmrr_units)) |
| 4055 | printk(KERN_INFO "DMAR: No RMRR found\n"); |
| 4056 | |
| 4057 | if (list_empty(&dmar_atsr_units)) |
| 4058 | printk(KERN_INFO "DMAR: No ATSR found\n"); |
| 4059 | |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 4060 | if (dmar_init_reserved_ranges()) { |
| 4061 | if (force_on) |
| 4062 | panic("tboot: Failed to reserve iommu ranges\n"); |
Jiang Liu | 3a5670e | 2014-02-19 14:07:33 +0800 | [diff] [blame] | 4063 | goto out_free_reserved_range; |
Joseph Cihula | 51a63e6 | 2011-03-21 11:04:24 -0700 | [diff] [blame] | 4064 | } |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 4065 | |
| 4066 | init_no_remapping_devices(); |
| 4067 | |
Joseph Cihula | b779260 | 2011-05-03 00:08:37 -0700 | [diff] [blame] | 4068 | ret = init_dmars(); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 4069 | if (ret) { |
Joseph Cihula | a59b50e | 2009-06-30 19:31:10 -0700 | [diff] [blame] | 4070 | if (force_on) |
| 4071 | panic("tboot: Failed to initialize DMARs\n"); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 4072 | printk(KERN_ERR "IOMMU: dmar init failed\n"); |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 4073 | goto out_free_reserved_range; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 4074 | } |
Jiang Liu | 3a5670e | 2014-02-19 14:07:33 +0800 | [diff] [blame] | 4075 | up_write(&dmar_global_lock); |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 4076 | printk(KERN_INFO |
| 4077 | "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n"); |
| 4078 | |
mark gross | 5e0d2a6 | 2008-03-04 15:22:08 -0800 | [diff] [blame] | 4079 | init_timer(&unmap_timer); |
FUJITA Tomonori | 75f1cdf | 2009-11-10 19:46:20 +0900 | [diff] [blame] | 4080 | #ifdef CONFIG_SWIOTLB |
| 4081 | swiotlb = 0; |
| 4082 | #endif |
David Woodhouse | 19943b0 | 2009-08-04 16:19:20 +0100 | [diff] [blame] | 4083 | dma_ops = &intel_dma_ops; |
Fenghua Yu | 4ed0d3e | 2009-04-24 17:30:20 -0700 | [diff] [blame] | 4084 | |
Rafael J. Wysocki | 134fac3 | 2011-03-23 22:16:14 +0100 | [diff] [blame] | 4085 | init_iommu_pm_ops(); |
Joerg Roedel | a8bcbb0d | 2008-12-03 15:14:02 +0100 | [diff] [blame] | 4086 | |
Alex Williamson | a5459cf | 2014-06-12 16:12:31 -0600 | [diff] [blame] | 4087 | for_each_active_iommu(iommu, drhd) |
| 4088 | iommu->iommu_dev = iommu_device_create(NULL, iommu, |
| 4089 | intel_iommu_groups, |
| 4090 | iommu->name); |
| 4091 | |
Joerg Roedel | 4236d97d | 2011-09-06 17:56:07 +0200 | [diff] [blame] | 4092 | bus_set_iommu(&pci_bus_type, &intel_iommu_ops); |
Fenghua Yu | 99dcade | 2009-11-11 07:23:06 -0800 | [diff] [blame] | 4093 | bus_register_notifier(&pci_bus_type, &device_nb); |
Jiang Liu | 75f0556 | 2014-02-19 14:07:37 +0800 | [diff] [blame] | 4094 | if (si_domain && !hw_pass_through) |
| 4095 | register_memory_notifier(&intel_iommu_memory_nb); |
Fenghua Yu | 99dcade | 2009-11-11 07:23:06 -0800 | [diff] [blame] | 4096 | |
Eugeni Dodonov | 8bc1f85 | 2011-11-23 16:42:14 -0200 | [diff] [blame] | 4097 | intel_iommu_enabled = 1; |
| 4098 | |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 4099 | return 0; |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 4100 | |
| 4101 | out_free_reserved_range: |
| 4102 | put_iova_domain(&reserved_iova_list); |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 4103 | out_free_dmar: |
| 4104 | intel_iommu_free_dmars(); |
Jiang Liu | 3a5670e | 2014-02-19 14:07:33 +0800 | [diff] [blame] | 4105 | up_write(&dmar_global_lock); |
| 4106 | iommu_exit_mempool(); |
Jiang Liu | 9bdc531 | 2014-01-06 14:18:27 +0800 | [diff] [blame] | 4107 | return ret; |
Keshavamurthy, Anil S | ba39592 | 2007-10-21 16:41:49 -0700 | [diff] [blame] | 4108 | } |
Keshavamurthy, Anil S | e820482 | 2007-10-21 16:41:55 -0700 | [diff] [blame] | 4109 | |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 4110 | static int iommu_detach_dev_cb(struct pci_dev *pdev, u16 alias, void *opaque) |
| 4111 | { |
| 4112 | struct intel_iommu *iommu = opaque; |
| 4113 | |
| 4114 | iommu_detach_dev(iommu, PCI_BUS_NUM(alias), alias & 0xff); |
| 4115 | return 0; |
| 4116 | } |
| 4117 | |
| 4118 | /* |
| 4119 | * NB - intel-iommu lacks any sort of reference counting for the users of |
| 4120 | * dependent devices. If multiple endpoints have intersecting dependent |
| 4121 | * devices, unbinding the driver from any one of them will possibly leave |
| 4122 | * the others unable to operate. |
| 4123 | */ |
Han, Weidong | 3199aa6 | 2009-02-26 17:31:12 +0800 | [diff] [blame] | 4124 | static void iommu_detach_dependent_devices(struct intel_iommu *iommu, |
David Woodhouse | 0bcb3e2 | 2014-03-06 17:12:03 +0000 | [diff] [blame] | 4125 | struct device *dev) |
Han, Weidong | 3199aa6 | 2009-02-26 17:31:12 +0800 | [diff] [blame] | 4126 | { |
David Woodhouse | 0bcb3e2 | 2014-03-06 17:12:03 +0000 | [diff] [blame] | 4127 | if (!iommu || !dev || !dev_is_pci(dev)) |
Han, Weidong | 3199aa6 | 2009-02-26 17:31:12 +0800 | [diff] [blame] | 4128 | return; |
| 4129 | |
Alex Williamson | 579305f | 2014-07-03 09:51:43 -0600 | [diff] [blame] | 4130 | pci_for_each_dma_alias(to_pci_dev(dev), &iommu_detach_dev_cb, iommu); |
Han, Weidong | 3199aa6 | 2009-02-26 17:31:12 +0800 | [diff] [blame] | 4131 | } |
| 4132 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 4133 | static void domain_remove_one_dev_info(struct dmar_domain *domain, |
David Woodhouse | bf9c9ed | 2014-03-09 16:19:13 -0700 | [diff] [blame] | 4134 | struct device *dev) |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4135 | { |
Yijing Wang | bca2b91 | 2013-10-31 17:26:04 +0800 | [diff] [blame] | 4136 | struct device_domain_info *info, *tmp; |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4137 | struct intel_iommu *iommu; |
| 4138 | unsigned long flags; |
| 4139 | int found = 0; |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 4140 | u8 bus, devfn; |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4141 | |
David Woodhouse | bf9c9ed | 2014-03-09 16:19:13 -0700 | [diff] [blame] | 4142 | iommu = device_to_iommu(dev, &bus, &devfn); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4143 | if (!iommu) |
| 4144 | return; |
| 4145 | |
| 4146 | spin_lock_irqsave(&device_domain_lock, flags); |
Yijing Wang | bca2b91 | 2013-10-31 17:26:04 +0800 | [diff] [blame] | 4147 | list_for_each_entry_safe(info, tmp, &domain->devices, link) { |
David Woodhouse | bf9c9ed | 2014-03-09 16:19:13 -0700 | [diff] [blame] | 4148 | if (info->iommu == iommu && info->bus == bus && |
| 4149 | info->devfn == devfn) { |
David Woodhouse | 109b9b0 | 2012-05-25 17:43:02 +0100 | [diff] [blame] | 4150 | unlink_domain_info(info); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4151 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 4152 | |
Yu Zhao | 93a23a7 | 2009-05-18 13:51:37 +0800 | [diff] [blame] | 4153 | iommu_disable_dev_iotlb(info); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4154 | iommu_detach_dev(iommu, info->bus, info->devfn); |
David Woodhouse | bf9c9ed | 2014-03-09 16:19:13 -0700 | [diff] [blame] | 4155 | iommu_detach_dependent_devices(iommu, dev); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4156 | free_devinfo_mem(info); |
| 4157 | |
| 4158 | spin_lock_irqsave(&device_domain_lock, flags); |
| 4159 | |
| 4160 | if (found) |
| 4161 | break; |
| 4162 | else |
| 4163 | continue; |
| 4164 | } |
| 4165 | |
| 4166 | /* if there is no other devices under the same iommu |
| 4167 | * owned by this domain, clear this iommu in iommu_bmp |
| 4168 | * update iommu count and coherency |
| 4169 | */ |
David Woodhouse | 8bbc441 | 2014-03-09 13:52:37 -0700 | [diff] [blame] | 4170 | if (info->iommu == iommu) |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4171 | found = 1; |
| 4172 | } |
| 4173 | |
Roland Dreier | 3e7abe2 | 2011-07-20 06:22:21 -0700 | [diff] [blame] | 4174 | spin_unlock_irqrestore(&device_domain_lock, flags); |
| 4175 | |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4176 | if (found == 0) { |
Jiang Liu | fb170fb | 2014-07-11 14:19:28 +0800 | [diff] [blame] | 4177 | domain_detach_iommu(domain, iommu); |
| 4178 | if (!domain_type_is_vm_or_si(domain)) |
| 4179 | iommu_detach_domain(domain, iommu); |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4180 | } |
Weidong Han | c7151a8 | 2008-12-08 22:51:37 +0800 | [diff] [blame] | 4181 | } |
| 4182 | |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 4183 | static int md_domain_init(struct dmar_domain *domain, int guest_width) |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 4184 | { |
| 4185 | int adjust_width; |
| 4186 | |
| 4187 | init_iova_domain(&domain->iovad, DMA_32BIT_PFN); |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 4188 | domain_reserve_special_ranges(domain); |
| 4189 | |
| 4190 | /* calculate AGAW */ |
| 4191 | domain->gaw = guest_width; |
| 4192 | adjust_width = guestwidth_to_adjustwidth(guest_width); |
| 4193 | domain->agaw = width_to_agaw(adjust_width); |
| 4194 | |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 4195 | domain->iommu_coherency = 0; |
Sheng Yang | c5b1525 | 2009-08-06 13:31:56 +0800 | [diff] [blame] | 4196 | domain->iommu_snooping = 0; |
Youquan Song | 6dd9a7c | 2011-05-25 19:13:49 +0100 | [diff] [blame] | 4197 | domain->iommu_superpage = 0; |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4198 | domain->max_addr = 0; |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 4199 | |
| 4200 | /* always allocate the top pgd */ |
Suresh Siddha | 4c923d4 | 2009-10-02 11:01:24 -0700 | [diff] [blame] | 4201 | domain->pgd = (struct dma_pte *)alloc_pgtable_page(domain->nid); |
Weidong Han | 5e98c4b | 2008-12-08 23:03:27 +0800 | [diff] [blame] | 4202 | if (!domain->pgd) |
| 4203 | return -ENOMEM; |
| 4204 | domain_flush_cache(domain, domain->pgd, PAGE_SIZE); |
| 4205 | return 0; |
| 4206 | } |
| 4207 | |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 4208 | static int intel_iommu_domain_init(struct iommu_domain *domain) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4209 | { |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 4210 | struct dmar_domain *dmar_domain; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4211 | |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 4212 | dmar_domain = alloc_domain(DOMAIN_FLAG_VIRTUAL_MACHINE); |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 4213 | if (!dmar_domain) { |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4214 | printk(KERN_ERR |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 4215 | "intel_iommu_domain_init: dmar_domain == NULL\n"); |
| 4216 | return -ENOMEM; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4217 | } |
Fenghua Yu | 2c2e2c3 | 2009-06-19 13:47:29 -0700 | [diff] [blame] | 4218 | if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) { |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4219 | printk(KERN_ERR |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 4220 | "intel_iommu_domain_init() failed\n"); |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 4221 | domain_exit(dmar_domain); |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 4222 | return -ENOMEM; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4223 | } |
Allen Kay | 8140a95 | 2011-10-14 12:32:17 -0700 | [diff] [blame] | 4224 | domain_update_iommu_cap(dmar_domain); |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 4225 | domain->priv = dmar_domain; |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4226 | |
Joerg Roedel | 8a0e715 | 2012-01-26 19:40:54 +0100 | [diff] [blame] | 4227 | domain->geometry.aperture_start = 0; |
| 4228 | domain->geometry.aperture_end = __DOMAIN_MAX_ADDR(dmar_domain->gaw); |
| 4229 | domain->geometry.force_aperture = true; |
| 4230 | |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 4231 | return 0; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4232 | } |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4233 | |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 4234 | static void intel_iommu_domain_destroy(struct iommu_domain *domain) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4235 | { |
Joerg Roedel | 5d45080 | 2008-12-03 14:52:32 +0100 | [diff] [blame] | 4236 | struct dmar_domain *dmar_domain = domain->priv; |
| 4237 | |
| 4238 | domain->priv = NULL; |
Jiang Liu | 92d03cc | 2014-02-19 14:07:28 +0800 | [diff] [blame] | 4239 | domain_exit(dmar_domain); |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4240 | } |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4241 | |
Joerg Roedel | 4c5478c | 2008-12-03 14:58:24 +0100 | [diff] [blame] | 4242 | static int intel_iommu_attach_device(struct iommu_domain *domain, |
| 4243 | struct device *dev) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4244 | { |
Joerg Roedel | 4c5478c | 2008-12-03 14:58:24 +0100 | [diff] [blame] | 4245 | struct dmar_domain *dmar_domain = domain->priv; |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4246 | struct intel_iommu *iommu; |
| 4247 | int addr_width; |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 4248 | u8 bus, devfn; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4249 | |
Alex Williamson | c875d2c | 2014-07-03 09:57:02 -0600 | [diff] [blame] | 4250 | if (device_is_rmrr_locked(dev)) { |
| 4251 | dev_warn(dev, "Device is ineligible for IOMMU domain attach due to platform RMRR requirement. Contact your platform vendor.\n"); |
| 4252 | return -EPERM; |
| 4253 | } |
| 4254 | |
David Woodhouse | 7207d8f | 2014-03-09 16:31:06 -0700 | [diff] [blame] | 4255 | /* normally dev is not mapped */ |
| 4256 | if (unlikely(domain_context_mapped(dev))) { |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4257 | struct dmar_domain *old_domain; |
| 4258 | |
David Woodhouse | 1525a29 | 2014-03-06 16:19:30 +0000 | [diff] [blame] | 4259 | old_domain = find_domain(dev); |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4260 | if (old_domain) { |
Jiang Liu | ab8dfe2 | 2014-07-11 14:19:27 +0800 | [diff] [blame] | 4261 | if (domain_type_is_vm_or_si(dmar_domain)) |
David Woodhouse | bf9c9ed | 2014-03-09 16:19:13 -0700 | [diff] [blame] | 4262 | domain_remove_one_dev_info(old_domain, dev); |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4263 | else |
| 4264 | domain_remove_dev_info(old_domain); |
| 4265 | } |
| 4266 | } |
| 4267 | |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 4268 | iommu = device_to_iommu(dev, &bus, &devfn); |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4269 | if (!iommu) |
| 4270 | return -ENODEV; |
| 4271 | |
| 4272 | /* check if this iommu agaw is sufficient for max mapped address */ |
| 4273 | addr_width = agaw_to_width(iommu->agaw); |
Tom Lyon | a99c47a | 2010-05-17 08:20:45 +0100 | [diff] [blame] | 4274 | if (addr_width > cap_mgaw(iommu->cap)) |
| 4275 | addr_width = cap_mgaw(iommu->cap); |
| 4276 | |
| 4277 | if (dmar_domain->max_addr > (1LL << addr_width)) { |
| 4278 | printk(KERN_ERR "%s: iommu width (%d) is not " |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4279 | "sufficient for the mapped address (%llx)\n", |
Tom Lyon | a99c47a | 2010-05-17 08:20:45 +0100 | [diff] [blame] | 4280 | __func__, addr_width, dmar_domain->max_addr); |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4281 | return -EFAULT; |
| 4282 | } |
Tom Lyon | a99c47a | 2010-05-17 08:20:45 +0100 | [diff] [blame] | 4283 | dmar_domain->gaw = addr_width; |
| 4284 | |
| 4285 | /* |
| 4286 | * Knock out extra levels of page tables if necessary |
| 4287 | */ |
| 4288 | while (iommu->agaw < dmar_domain->agaw) { |
| 4289 | struct dma_pte *pte; |
| 4290 | |
| 4291 | pte = dmar_domain->pgd; |
| 4292 | if (dma_pte_present(pte)) { |
Sheng Yang | 25cbff1 | 2010-06-12 19:21:42 +0800 | [diff] [blame] | 4293 | dmar_domain->pgd = (struct dma_pte *) |
| 4294 | phys_to_virt(dma_pte_addr(pte)); |
Jan Kiszka | 7a66101 | 2010-11-02 08:05:51 +0100 | [diff] [blame] | 4295 | free_pgtable_page(pte); |
Tom Lyon | a99c47a | 2010-05-17 08:20:45 +0100 | [diff] [blame] | 4296 | } |
| 4297 | dmar_domain->agaw--; |
| 4298 | } |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4299 | |
David Woodhouse | 5913c9b | 2014-03-09 16:27:31 -0700 | [diff] [blame] | 4300 | return domain_add_dev_info(dmar_domain, dev, CONTEXT_TT_MULTI_LEVEL); |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4301 | } |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4302 | |
Joerg Roedel | 4c5478c | 2008-12-03 14:58:24 +0100 | [diff] [blame] | 4303 | static void intel_iommu_detach_device(struct iommu_domain *domain, |
| 4304 | struct device *dev) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4305 | { |
Joerg Roedel | 4c5478c | 2008-12-03 14:58:24 +0100 | [diff] [blame] | 4306 | struct dmar_domain *dmar_domain = domain->priv; |
Joerg Roedel | 4c5478c | 2008-12-03 14:58:24 +0100 | [diff] [blame] | 4307 | |
David Woodhouse | bf9c9ed | 2014-03-09 16:19:13 -0700 | [diff] [blame] | 4308 | domain_remove_one_dev_info(dmar_domain, dev); |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4309 | } |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4310 | |
Joerg Roedel | b146a1c9f | 2010-01-20 17:17:37 +0100 | [diff] [blame] | 4311 | static int intel_iommu_map(struct iommu_domain *domain, |
| 4312 | unsigned long iova, phys_addr_t hpa, |
Ohad Ben-Cohen | 5009065 | 2011-11-10 11:32:25 +0200 | [diff] [blame] | 4313 | size_t size, int iommu_prot) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4314 | { |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 4315 | struct dmar_domain *dmar_domain = domain->priv; |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4316 | u64 max_addr; |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 4317 | int prot = 0; |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4318 | int ret; |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4319 | |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 4320 | if (iommu_prot & IOMMU_READ) |
| 4321 | prot |= DMA_PTE_READ; |
| 4322 | if (iommu_prot & IOMMU_WRITE) |
| 4323 | prot |= DMA_PTE_WRITE; |
Sheng Yang | 9cf06697 | 2009-03-18 15:33:07 +0800 | [diff] [blame] | 4324 | if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping) |
| 4325 | prot |= DMA_PTE_SNP; |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 4326 | |
David Woodhouse | 163cc52 | 2009-06-28 00:51:17 +0100 | [diff] [blame] | 4327 | max_addr = iova + size; |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 4328 | if (dmar_domain->max_addr < max_addr) { |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4329 | u64 end; |
| 4330 | |
| 4331 | /* check if minimum agaw is sufficient for mapped address */ |
Tom Lyon | 8954da1 | 2010-05-17 08:19:52 +0100 | [diff] [blame] | 4332 | end = __DOMAIN_MAX_ADDR(dmar_domain->gaw) + 1; |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4333 | if (end < max_addr) { |
Tom Lyon | 8954da1 | 2010-05-17 08:19:52 +0100 | [diff] [blame] | 4334 | printk(KERN_ERR "%s: iommu width (%d) is not " |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4335 | "sufficient for the mapped address (%llx)\n", |
Tom Lyon | 8954da1 | 2010-05-17 08:19:52 +0100 | [diff] [blame] | 4336 | __func__, dmar_domain->gaw, max_addr); |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4337 | return -EFAULT; |
| 4338 | } |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 4339 | dmar_domain->max_addr = max_addr; |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4340 | } |
David Woodhouse | ad05122 | 2009-06-28 14:22:28 +0100 | [diff] [blame] | 4341 | /* Round up size to next multiple of PAGE_SIZE, if it and |
| 4342 | the low bits of hpa would take us onto the next page */ |
David Woodhouse | 88cb6a7 | 2009-06-28 15:03:06 +0100 | [diff] [blame] | 4343 | size = aligned_nrpages(hpa, size); |
David Woodhouse | ad05122 | 2009-06-28 14:22:28 +0100 | [diff] [blame] | 4344 | ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT, |
| 4345 | hpa >> VTD_PAGE_SHIFT, size, prot); |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4346 | return ret; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4347 | } |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4348 | |
Ohad Ben-Cohen | 5009065 | 2011-11-10 11:32:25 +0200 | [diff] [blame] | 4349 | static size_t intel_iommu_unmap(struct iommu_domain *domain, |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 4350 | unsigned long iova, size_t size) |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4351 | { |
Joerg Roedel | dde57a2 | 2008-12-03 15:04:09 +0100 | [diff] [blame] | 4352 | struct dmar_domain *dmar_domain = domain->priv; |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 4353 | struct page *freelist = NULL; |
| 4354 | struct intel_iommu *iommu; |
| 4355 | unsigned long start_pfn, last_pfn; |
| 4356 | unsigned int npages; |
| 4357 | int iommu_id, num, ndomains, level = 0; |
Sheng Yang | 4b99d35 | 2009-07-08 11:52:52 +0100 | [diff] [blame] | 4358 | |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 4359 | /* Cope with horrid API which requires us to unmap more than the |
| 4360 | size argument if it happens to be a large-page mapping. */ |
| 4361 | if (!pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level)) |
| 4362 | BUG(); |
| 4363 | |
| 4364 | if (size < VTD_PAGE_SIZE << level_to_offset_bits(level)) |
| 4365 | size = VTD_PAGE_SIZE << level_to_offset_bits(level); |
| 4366 | |
David Woodhouse | ea8ea46 | 2014-03-05 17:09:32 +0000 | [diff] [blame] | 4367 | start_pfn = iova >> VTD_PAGE_SHIFT; |
| 4368 | last_pfn = (iova + size - 1) >> VTD_PAGE_SHIFT; |
| 4369 | |
| 4370 | freelist = domain_unmap(dmar_domain, start_pfn, last_pfn); |
| 4371 | |
| 4372 | npages = last_pfn - start_pfn + 1; |
| 4373 | |
| 4374 | for_each_set_bit(iommu_id, dmar_domain->iommu_bmp, g_num_of_iommus) { |
| 4375 | iommu = g_iommus[iommu_id]; |
| 4376 | |
| 4377 | /* |
| 4378 | * find bit position of dmar_domain |
| 4379 | */ |
| 4380 | ndomains = cap_ndoms(iommu->cap); |
| 4381 | for_each_set_bit(num, iommu->domain_ids, ndomains) { |
| 4382 | if (iommu->domains[num] == dmar_domain) |
| 4383 | iommu_flush_iotlb_psi(iommu, num, start_pfn, |
| 4384 | npages, !freelist, 0); |
| 4385 | } |
| 4386 | |
| 4387 | } |
| 4388 | |
| 4389 | dma_free_pagelist(freelist); |
Weidong Han | fe40f1e | 2008-12-08 23:10:23 +0800 | [diff] [blame] | 4390 | |
David Woodhouse | 163cc52 | 2009-06-28 00:51:17 +0100 | [diff] [blame] | 4391 | if (dmar_domain->max_addr == iova + size) |
| 4392 | dmar_domain->max_addr = iova; |
Joerg Roedel | b146a1c9f | 2010-01-20 17:17:37 +0100 | [diff] [blame] | 4393 | |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 4394 | return size; |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4395 | } |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4396 | |
Joerg Roedel | d14d657 | 2008-12-03 15:06:57 +0100 | [diff] [blame] | 4397 | static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain, |
Varun Sethi | bb5547ac | 2013-03-29 01:23:58 +0530 | [diff] [blame] | 4398 | dma_addr_t iova) |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4399 | { |
Joerg Roedel | d14d657 | 2008-12-03 15:06:57 +0100 | [diff] [blame] | 4400 | struct dmar_domain *dmar_domain = domain->priv; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4401 | struct dma_pte *pte; |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 4402 | int level = 0; |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4403 | u64 phys = 0; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4404 | |
David Woodhouse | 5cf0a76 | 2014-03-19 16:07:49 +0000 | [diff] [blame] | 4405 | pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT, &level); |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4406 | if (pte) |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4407 | phys = dma_pte_addr(pte); |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4408 | |
Weidong Han | faa3d6f | 2008-12-08 23:09:29 +0800 | [diff] [blame] | 4409 | return phys; |
Kay, Allen M | 3871794 | 2008-09-09 18:37:29 +0300 | [diff] [blame] | 4410 | } |
Joerg Roedel | a8bcbb0d | 2008-12-03 15:14:02 +0100 | [diff] [blame] | 4411 | |
Joerg Roedel | 5d587b8 | 2014-09-05 10:50:45 +0200 | [diff] [blame] | 4412 | static bool intel_iommu_capable(enum iommu_cap cap) |
Sheng Yang | dbb9fd8 | 2009-03-18 15:33:06 +0800 | [diff] [blame] | 4413 | { |
Sheng Yang | dbb9fd8 | 2009-03-18 15:33:06 +0800 | [diff] [blame] | 4414 | if (cap == IOMMU_CAP_CACHE_COHERENCY) |
Joerg Roedel | 5d587b8 | 2014-09-05 10:50:45 +0200 | [diff] [blame] | 4415 | return domain_update_iommu_snooping(NULL) == 1; |
Tom Lyon | 323f99c | 2010-07-02 16:56:14 -0400 | [diff] [blame] | 4416 | if (cap == IOMMU_CAP_INTR_REMAP) |
Joerg Roedel | 5d587b8 | 2014-09-05 10:50:45 +0200 | [diff] [blame] | 4417 | return irq_remapping_enabled == 1; |
Sheng Yang | dbb9fd8 | 2009-03-18 15:33:06 +0800 | [diff] [blame] | 4418 | |
Joerg Roedel | 5d587b8 | 2014-09-05 10:50:45 +0200 | [diff] [blame] | 4419 | return false; |
Sheng Yang | dbb9fd8 | 2009-03-18 15:33:06 +0800 | [diff] [blame] | 4420 | } |
| 4421 | |
Alex Williamson | abdfdde | 2012-05-30 14:19:19 -0600 | [diff] [blame] | 4422 | static int intel_iommu_add_device(struct device *dev) |
Alex Williamson | 70ae6f0 | 2011-10-21 15:56:11 -0400 | [diff] [blame] | 4423 | { |
Alex Williamson | a5459cf | 2014-06-12 16:12:31 -0600 | [diff] [blame] | 4424 | struct intel_iommu *iommu; |
Alex Williamson | abdfdde | 2012-05-30 14:19:19 -0600 | [diff] [blame] | 4425 | struct iommu_group *group; |
David Woodhouse | 156baca | 2014-03-09 14:00:57 -0700 | [diff] [blame] | 4426 | u8 bus, devfn; |
Alex Williamson | 70ae6f0 | 2011-10-21 15:56:11 -0400 | [diff] [blame] | 4427 | |
Alex Williamson | a5459cf | 2014-06-12 16:12:31 -0600 | [diff] [blame] | 4428 | iommu = device_to_iommu(dev, &bus, &devfn); |
| 4429 | if (!iommu) |
Alex Williamson | 70ae6f0 | 2011-10-21 15:56:11 -0400 | [diff] [blame] | 4430 | return -ENODEV; |
| 4431 | |
Alex Williamson | a5459cf | 2014-06-12 16:12:31 -0600 | [diff] [blame] | 4432 | iommu_device_link(iommu->iommu_dev, dev); |
Alex Williamson | abdfdde | 2012-05-30 14:19:19 -0600 | [diff] [blame] | 4433 | |
Alex Williamson | e17f9ff | 2014-07-03 09:51:37 -0600 | [diff] [blame] | 4434 | group = iommu_group_get_for_dev(dev); |
Alex Williamson | 783f157 | 2012-05-30 14:19:43 -0600 | [diff] [blame] | 4435 | |
Alex Williamson | e17f9ff | 2014-07-03 09:51:37 -0600 | [diff] [blame] | 4436 | if (IS_ERR(group)) |
| 4437 | return PTR_ERR(group); |
Alex Williamson | 70ae6f0 | 2011-10-21 15:56:11 -0400 | [diff] [blame] | 4438 | |
Alex Williamson | abdfdde | 2012-05-30 14:19:19 -0600 | [diff] [blame] | 4439 | iommu_group_put(group); |
Alex Williamson | e17f9ff | 2014-07-03 09:51:37 -0600 | [diff] [blame] | 4440 | return 0; |
Alex Williamson | abdfdde | 2012-05-30 14:19:19 -0600 | [diff] [blame] | 4441 | } |
| 4442 | |
| 4443 | static void intel_iommu_remove_device(struct device *dev) |
| 4444 | { |
Alex Williamson | a5459cf | 2014-06-12 16:12:31 -0600 | [diff] [blame] | 4445 | struct intel_iommu *iommu; |
| 4446 | u8 bus, devfn; |
| 4447 | |
| 4448 | iommu = device_to_iommu(dev, &bus, &devfn); |
| 4449 | if (!iommu) |
| 4450 | return; |
| 4451 | |
Alex Williamson | abdfdde | 2012-05-30 14:19:19 -0600 | [diff] [blame] | 4452 | iommu_group_remove_device(dev); |
Alex Williamson | a5459cf | 2014-06-12 16:12:31 -0600 | [diff] [blame] | 4453 | |
| 4454 | iommu_device_unlink(iommu->iommu_dev, dev); |
Alex Williamson | 70ae6f0 | 2011-10-21 15:56:11 -0400 | [diff] [blame] | 4455 | } |
| 4456 | |
Thierry Reding | b22f643 | 2014-06-27 09:03:12 +0200 | [diff] [blame] | 4457 | static const struct iommu_ops intel_iommu_ops = { |
Joerg Roedel | 5d587b8 | 2014-09-05 10:50:45 +0200 | [diff] [blame] | 4458 | .capable = intel_iommu_capable, |
Joerg Roedel | a8bcbb0d | 2008-12-03 15:14:02 +0100 | [diff] [blame] | 4459 | .domain_init = intel_iommu_domain_init, |
| 4460 | .domain_destroy = intel_iommu_domain_destroy, |
| 4461 | .attach_dev = intel_iommu_attach_device, |
| 4462 | .detach_dev = intel_iommu_detach_device, |
Joerg Roedel | b146a1c9f | 2010-01-20 17:17:37 +0100 | [diff] [blame] | 4463 | .map = intel_iommu_map, |
| 4464 | .unmap = intel_iommu_unmap, |
Joerg Roedel | a8bcbb0d | 2008-12-03 15:14:02 +0100 | [diff] [blame] | 4465 | .iova_to_phys = intel_iommu_iova_to_phys, |
Alex Williamson | abdfdde | 2012-05-30 14:19:19 -0600 | [diff] [blame] | 4466 | .add_device = intel_iommu_add_device, |
| 4467 | .remove_device = intel_iommu_remove_device, |
Ohad Ben-Cohen | 6d1c56a | 2011-11-10 11:32:30 +0200 | [diff] [blame] | 4468 | .pgsize_bitmap = INTEL_IOMMU_PGSIZES, |
Joerg Roedel | a8bcbb0d | 2008-12-03 15:14:02 +0100 | [diff] [blame] | 4469 | }; |
David Woodhouse | 9af8814 | 2009-02-13 23:18:03 +0000 | [diff] [blame] | 4470 | |
Daniel Vetter | 9452618 | 2013-01-20 23:50:13 +0100 | [diff] [blame] | 4471 | static void quirk_iommu_g4x_gfx(struct pci_dev *dev) |
| 4472 | { |
| 4473 | /* G4x/GM45 integrated gfx dmar support is totally busted. */ |
| 4474 | printk(KERN_INFO "DMAR: Disabling IOMMU for graphics on this chipset\n"); |
| 4475 | dmar_map_gfx = 0; |
| 4476 | } |
| 4477 | |
| 4478 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_g4x_gfx); |
| 4479 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_g4x_gfx); |
| 4480 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_g4x_gfx); |
| 4481 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_g4x_gfx); |
| 4482 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_g4x_gfx); |
| 4483 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_g4x_gfx); |
| 4484 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_g4x_gfx); |
| 4485 | |
Greg Kroah-Hartman | d34d651 | 2012-12-21 15:05:21 -0800 | [diff] [blame] | 4486 | static void quirk_iommu_rwbf(struct pci_dev *dev) |
David Woodhouse | 9af8814 | 2009-02-13 23:18:03 +0000 | [diff] [blame] | 4487 | { |
| 4488 | /* |
| 4489 | * Mobile 4 Series Chipset neglects to set RWBF capability, |
Daniel Vetter | 210561f | 2013-01-21 19:48:59 +0100 | [diff] [blame] | 4490 | * but needs it. Same seems to hold for the desktop versions. |
David Woodhouse | 9af8814 | 2009-02-13 23:18:03 +0000 | [diff] [blame] | 4491 | */ |
| 4492 | printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n"); |
| 4493 | rwbf_quirk = 1; |
| 4494 | } |
| 4495 | |
| 4496 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf); |
Daniel Vetter | 210561f | 2013-01-21 19:48:59 +0100 | [diff] [blame] | 4497 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_rwbf); |
| 4498 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e10, quirk_iommu_rwbf); |
| 4499 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e20, quirk_iommu_rwbf); |
| 4500 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e30, quirk_iommu_rwbf); |
| 4501 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e40, quirk_iommu_rwbf); |
| 4502 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e90, quirk_iommu_rwbf); |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 4503 | |
Adam Jackson | eecfd57 | 2010-08-25 21:17:34 +0100 | [diff] [blame] | 4504 | #define GGC 0x52 |
| 4505 | #define GGC_MEMORY_SIZE_MASK (0xf << 8) |
| 4506 | #define GGC_MEMORY_SIZE_NONE (0x0 << 8) |
| 4507 | #define GGC_MEMORY_SIZE_1M (0x1 << 8) |
| 4508 | #define GGC_MEMORY_SIZE_2M (0x3 << 8) |
| 4509 | #define GGC_MEMORY_VT_ENABLED (0x8 << 8) |
| 4510 | #define GGC_MEMORY_SIZE_2M_VT (0x9 << 8) |
| 4511 | #define GGC_MEMORY_SIZE_3M_VT (0xa << 8) |
| 4512 | #define GGC_MEMORY_SIZE_4M_VT (0xb << 8) |
| 4513 | |
Greg Kroah-Hartman | d34d651 | 2012-12-21 15:05:21 -0800 | [diff] [blame] | 4514 | static void quirk_calpella_no_shadow_gtt(struct pci_dev *dev) |
David Woodhouse | 9eecabc | 2010-09-21 22:28:23 +0100 | [diff] [blame] | 4515 | { |
| 4516 | unsigned short ggc; |
| 4517 | |
Adam Jackson | eecfd57 | 2010-08-25 21:17:34 +0100 | [diff] [blame] | 4518 | if (pci_read_config_word(dev, GGC, &ggc)) |
David Woodhouse | 9eecabc | 2010-09-21 22:28:23 +0100 | [diff] [blame] | 4519 | return; |
| 4520 | |
Adam Jackson | eecfd57 | 2010-08-25 21:17:34 +0100 | [diff] [blame] | 4521 | if (!(ggc & GGC_MEMORY_VT_ENABLED)) { |
David Woodhouse | 9eecabc | 2010-09-21 22:28:23 +0100 | [diff] [blame] | 4522 | printk(KERN_INFO "DMAR: BIOS has allocated no shadow GTT; disabling IOMMU for graphics\n"); |
| 4523 | dmar_map_gfx = 0; |
David Woodhouse | 6fbcfb3 | 2011-09-25 19:11:14 -0700 | [diff] [blame] | 4524 | } else if (dmar_map_gfx) { |
| 4525 | /* we have to ensure the gfx device is idle before we flush */ |
| 4526 | printk(KERN_INFO "DMAR: Disabling batched IOTLB flush on Ironlake\n"); |
| 4527 | intel_iommu_strict = 1; |
| 4528 | } |
David Woodhouse | 9eecabc | 2010-09-21 22:28:23 +0100 | [diff] [blame] | 4529 | } |
| 4530 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0040, quirk_calpella_no_shadow_gtt); |
| 4531 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0044, quirk_calpella_no_shadow_gtt); |
| 4532 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0062, quirk_calpella_no_shadow_gtt); |
| 4533 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x006a, quirk_calpella_no_shadow_gtt); |
| 4534 | |
David Woodhouse | e0fc7e0 | 2009-09-30 09:12:17 -0700 | [diff] [blame] | 4535 | /* On Tylersburg chipsets, some BIOSes have been known to enable the |
| 4536 | ISOCH DMAR unit for the Azalia sound device, but not give it any |
| 4537 | TLB entries, which causes it to deadlock. Check for that. We do |
| 4538 | this in a function called from init_dmars(), instead of in a PCI |
| 4539 | quirk, because we don't want to print the obnoxious "BIOS broken" |
| 4540 | message if VT-d is actually disabled. |
| 4541 | */ |
| 4542 | static void __init check_tylersburg_isoch(void) |
| 4543 | { |
| 4544 | struct pci_dev *pdev; |
| 4545 | uint32_t vtisochctrl; |
| 4546 | |
| 4547 | /* If there's no Azalia in the system anyway, forget it. */ |
| 4548 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x3a3e, NULL); |
| 4549 | if (!pdev) |
| 4550 | return; |
| 4551 | pci_dev_put(pdev); |
| 4552 | |
| 4553 | /* System Management Registers. Might be hidden, in which case |
| 4554 | we can't do the sanity check. But that's OK, because the |
| 4555 | known-broken BIOSes _don't_ actually hide it, so far. */ |
| 4556 | pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x342e, NULL); |
| 4557 | if (!pdev) |
| 4558 | return; |
| 4559 | |
| 4560 | if (pci_read_config_dword(pdev, 0x188, &vtisochctrl)) { |
| 4561 | pci_dev_put(pdev); |
| 4562 | return; |
| 4563 | } |
| 4564 | |
| 4565 | pci_dev_put(pdev); |
| 4566 | |
| 4567 | /* If Azalia DMA is routed to the non-isoch DMAR unit, fine. */ |
| 4568 | if (vtisochctrl & 1) |
| 4569 | return; |
| 4570 | |
| 4571 | /* Drop all bits other than the number of TLB entries */ |
| 4572 | vtisochctrl &= 0x1c; |
| 4573 | |
| 4574 | /* If we have the recommended number of TLB entries (16), fine. */ |
| 4575 | if (vtisochctrl == 0x10) |
| 4576 | return; |
| 4577 | |
| 4578 | /* Zero TLB entries? You get to ride the short bus to school. */ |
| 4579 | if (!vtisochctrl) { |
| 4580 | WARN(1, "Your BIOS is broken; DMA routed to ISOCH DMAR unit but no TLB space.\n" |
| 4581 | "BIOS vendor: %s; Ver: %s; Product Version: %s\n", |
| 4582 | dmi_get_system_info(DMI_BIOS_VENDOR), |
| 4583 | dmi_get_system_info(DMI_BIOS_VERSION), |
| 4584 | dmi_get_system_info(DMI_PRODUCT_VERSION)); |
| 4585 | iommu_identity_mapping |= IDENTMAP_AZALIA; |
| 4586 | return; |
| 4587 | } |
| 4588 | |
| 4589 | printk(KERN_WARNING "DMAR: Recommended TLB entries for ISOCH unit is 16; your BIOS set %d\n", |
| 4590 | vtisochctrl); |
| 4591 | } |