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Jeeja KPa40e6932015-07-09 15:20:08 +05301/*
2 * skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
3 *
4 * Copyright (C) 2014-2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
6 *
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
19 *
20 */
21
22#include <linux/pci.h>
23#include <linux/pm_runtime.h>
24#include <sound/pcm_params.h>
25#include <sound/soc.h>
26#include "skl.h"
Jeeja KPb663a8c2015-10-07 11:31:57 +010027#include "skl-topology.h"
Dharageswari.R721c3e32015-12-18 15:12:04 +053028#include "skl-sst-dsp.h"
29#include "skl-sst-ipc.h"
Jeeja KPa40e6932015-07-09 15:20:08 +053030
31#define HDA_MONO 1
32#define HDA_STEREO 2
Jeeja KP8f35bf32015-11-28 15:01:46 +053033#define HDA_QUAD 4
Jeeja KPa40e6932015-07-09 15:20:08 +053034
35static struct snd_pcm_hardware azx_pcm_hw = {
36 .info = (SNDRV_PCM_INFO_MMAP |
37 SNDRV_PCM_INFO_INTERLEAVED |
38 SNDRV_PCM_INFO_BLOCK_TRANSFER |
39 SNDRV_PCM_INFO_MMAP_VALID |
40 SNDRV_PCM_INFO_PAUSE |
Jeeja KP36379762015-12-18 15:12:09 +053041 SNDRV_PCM_INFO_RESUME |
Jeeja KPa40e6932015-07-09 15:20:08 +053042 SNDRV_PCM_INFO_SYNC_START |
43 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
44 SNDRV_PCM_INFO_HAS_LINK_ATIME |
45 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
Jeeja KP06b23d92015-11-23 22:26:26 +053046 .formats = SNDRV_PCM_FMTBIT_S16_LE |
47 SNDRV_PCM_FMTBIT_S32_LE |
48 SNDRV_PCM_FMTBIT_S24_LE,
49 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
50 SNDRV_PCM_RATE_8000,
51 .rate_min = 8000,
Jeeja KPa40e6932015-07-09 15:20:08 +053052 .rate_max = 48000,
Jeeja KP8f35bf32015-11-28 15:01:46 +053053 .channels_min = 1,
54 .channels_max = HDA_QUAD,
Jeeja KPa40e6932015-07-09 15:20:08 +053055 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
56 .period_bytes_min = 128,
57 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
58 .periods_min = 2,
59 .periods_max = AZX_MAX_FRAG,
60 .fifo_size = 0,
61};
62
63static inline
64struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
65{
66 return substream->runtime->private_data;
67}
68
69static struct hdac_ext_bus *get_bus_ctx(struct snd_pcm_substream *substream)
70{
71 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
72 struct hdac_stream *hstream = hdac_stream(stream);
73 struct hdac_bus *bus = hstream->bus;
74
75 return hbus_to_ebus(bus);
76}
77
78static int skl_substream_alloc_pages(struct hdac_ext_bus *ebus,
79 struct snd_pcm_substream *substream,
80 size_t size)
81{
82 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
83
84 hdac_stream(stream)->bufsize = 0;
85 hdac_stream(stream)->period_bytes = 0;
86 hdac_stream(stream)->format_val = 0;
87
88 return snd_pcm_lib_malloc_pages(substream, size);
89}
90
91static int skl_substream_free_pages(struct hdac_bus *bus,
92 struct snd_pcm_substream *substream)
93{
94 return snd_pcm_lib_free_pages(substream);
95}
96
97static void skl_set_pcm_constrains(struct hdac_ext_bus *ebus,
98 struct snd_pcm_runtime *runtime)
99{
100 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
101
102 /* avoid wrap-around with wall-clock */
103 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
104 20, 178000000);
105}
106
Jeeja KP05057002015-07-09 15:20:11 +0530107static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_ext_bus *ebus)
108{
109 if (ebus->ppcap)
110 return HDAC_EXT_STREAM_TYPE_HOST;
111 else
112 return HDAC_EXT_STREAM_TYPE_COUPLED;
113}
114
Jeeja KP4557c302015-12-03 23:30:00 +0530115/*
116 * check if the stream opened is marked as ignore_suspend by machine, if so
117 * then enable suspend_active refcount
118 *
119 * The count supend_active does not need lock as it is used in open/close
120 * and suspend context
121 */
122static void skl_set_suspend_active(struct snd_pcm_substream *substream,
123 struct snd_soc_dai *dai, bool enable)
124{
125 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
126 struct snd_soc_dapm_widget *w;
127 struct skl *skl = ebus_to_skl(ebus);
128
129 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
130 w = dai->playback_widget;
131 else
132 w = dai->capture_widget;
133
134 if (w->ignore_suspend && enable)
135 skl->supend_active++;
136 else if (w->ignore_suspend && !enable)
137 skl->supend_active--;
138}
139
Jeeja KPa40e6932015-07-09 15:20:08 +0530140static int skl_pcm_open(struct snd_pcm_substream *substream,
141 struct snd_soc_dai *dai)
142{
143 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
144 struct hdac_ext_stream *stream;
145 struct snd_pcm_runtime *runtime = substream->runtime;
146 struct skl_dma_params *dma_params;
Jeeja KPa40e6932015-07-09 15:20:08 +0530147
148 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
Jeeja KPa40e6932015-07-09 15:20:08 +0530149
150 stream = snd_hdac_ext_stream_assign(ebus, substream,
Jeeja KP05057002015-07-09 15:20:11 +0530151 skl_get_host_stream_type(ebus));
Jeeja KPa40e6932015-07-09 15:20:08 +0530152 if (stream == NULL)
153 return -EBUSY;
154
155 skl_set_pcm_constrains(ebus, runtime);
156
157 /*
158 * disable WALLCLOCK timestamps for capture streams
159 * until we figure out how to handle digital inputs
160 */
161 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
162 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
163 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
164 }
165
166 runtime->private_data = stream;
167
168 dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
169 if (!dma_params)
170 return -ENOMEM;
171
172 dma_params->stream_tag = hdac_stream(stream)->stream_tag;
173 snd_soc_dai_set_dma_data(dai, substream, dma_params);
174
175 dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
176 dma_params->stream_tag);
Jeeja KP4557c302015-12-03 23:30:00 +0530177 skl_set_suspend_active(substream, dai, true);
Jeeja KPa40e6932015-07-09 15:20:08 +0530178 snd_pcm_set_sync(substream);
179
180 return 0;
181}
182
183static int skl_get_format(struct snd_pcm_substream *substream,
184 struct snd_soc_dai *dai)
185{
186 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
187 struct skl_dma_params *dma_params;
Jeeja KP05057002015-07-09 15:20:11 +0530188 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
Jeeja KPa40e6932015-07-09 15:20:08 +0530189 int format_val = 0;
Jeeja KPa40e6932015-07-09 15:20:08 +0530190
Jeeja KP05057002015-07-09 15:20:11 +0530191 if (ebus->ppcap) {
192 struct snd_pcm_runtime *runtime = substream->runtime;
193
194 format_val = snd_hdac_calc_stream_format(runtime->rate,
195 runtime->channels,
196 runtime->format,
197 32, 0);
198 } else {
199 struct snd_soc_dai *codec_dai = rtd->codec_dai;
200
201 dma_params = snd_soc_dai_get_dma_data(codec_dai, substream);
202 if (dma_params)
203 format_val = dma_params->format;
204 }
Jeeja KPa40e6932015-07-09 15:20:08 +0530205
206 return format_val;
207}
208
Dharageswari.Rc115fa52016-02-05 12:19:07 +0530209static int skl_be_prepare(struct snd_pcm_substream *substream,
210 struct snd_soc_dai *dai)
211{
212 struct skl *skl = get_skl_ctx(dai->dev);
213 struct skl_sst *ctx = skl->skl_sst;
214 struct skl_module_cfg *mconfig;
215
Dharageswari.R1a13b1f2016-04-28 18:45:27 +0530216 if (dai->playback_widget->power || dai->capture_widget->power)
Dharageswari.Rc115fa52016-02-05 12:19:07 +0530217 return 0;
218
219 mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
220 if (mconfig == NULL)
221 return -EINVAL;
222
223 return skl_dsp_set_dma_control(ctx, mconfig);
224}
225
Jeeja KPa40e6932015-07-09 15:20:08 +0530226static int skl_pcm_prepare(struct snd_pcm_substream *substream,
227 struct snd_soc_dai *dai)
228{
229 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
230 unsigned int format_val;
231 int err;
232
233 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
Jeeja KPa40e6932015-07-09 15:20:08 +0530234
235 format_val = skl_get_format(substream, dai);
236 dev_dbg(dai->dev, "stream_tag=%d formatvalue=%d\n",
237 hdac_stream(stream)->stream_tag, format_val);
238 snd_hdac_stream_reset(hdac_stream(stream));
239
240 err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
241 if (err < 0)
242 return err;
243
244 err = snd_hdac_stream_setup(hdac_stream(stream));
245 if (err < 0)
246 return err;
247
248 hdac_stream(stream)->prepared = 1;
249
250 return err;
251}
252
253static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
254 struct snd_pcm_hw_params *params,
255 struct snd_soc_dai *dai)
256{
257 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
Jeeja KP05057002015-07-09 15:20:11 +0530258 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
Jeeja KPa40e6932015-07-09 15:20:08 +0530259 struct snd_pcm_runtime *runtime = substream->runtime;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100260 struct skl_pipe_params p_params = {0};
261 struct skl_module_cfg *m_cfg;
Jeeja KP05057002015-07-09 15:20:11 +0530262 int ret, dma_id;
Jeeja KPa40e6932015-07-09 15:20:08 +0530263
264 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
265 ret = skl_substream_alloc_pages(ebus, substream,
266 params_buffer_bytes(params));
267 if (ret < 0)
268 return ret;
269
270 dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
271 runtime->rate, runtime->channels, runtime->format);
272
Jeeja KP05057002015-07-09 15:20:11 +0530273 dma_id = hdac_stream(stream)->stream_tag - 1;
274 dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
275
Jeeja KPb663a8c2015-10-07 11:31:57 +0100276 p_params.s_fmt = snd_pcm_format_width(params_format(params));
277 p_params.ch = params_channels(params);
278 p_params.s_freq = params_rate(params);
279 p_params.host_dma_id = dma_id;
280 p_params.stream = substream->stream;
281
282 m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
283 if (m_cfg)
284 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
285
Jeeja KPa40e6932015-07-09 15:20:08 +0530286 return 0;
287}
288
289static void skl_pcm_close(struct snd_pcm_substream *substream,
290 struct snd_soc_dai *dai)
291{
292 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
Jeeja KP05057002015-07-09 15:20:11 +0530293 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
Jeeja KPa40e6932015-07-09 15:20:08 +0530294 struct skl_dma_params *dma_params = NULL;
Dharageswari.R721c3e32015-12-18 15:12:04 +0530295 struct skl *skl = ebus_to_skl(ebus);
Jeeja KPa40e6932015-07-09 15:20:08 +0530296
297 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
Jeeja KP05057002015-07-09 15:20:11 +0530298
299 snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(ebus));
Jeeja KPa40e6932015-07-09 15:20:08 +0530300
301 dma_params = snd_soc_dai_get_dma_data(dai, substream);
302 /*
303 * now we should set this to NULL as we are freeing by the
304 * dma_params
305 */
306 snd_soc_dai_set_dma_data(dai, substream, NULL);
Jeeja KP4557c302015-12-03 23:30:00 +0530307 skl_set_suspend_active(substream, dai, false);
Jeeja KPa40e6932015-07-09 15:20:08 +0530308
Dharageswari.R721c3e32015-12-18 15:12:04 +0530309 /*
310 * check if close is for "Reference Pin" and set back the
311 * CGCTL.MISCBDCGE if disabled by driver
312 */
313 if (!strncmp(dai->name, "Reference Pin", 13) &&
314 skl->skl_sst->miscbdcg_disabled) {
315 skl->skl_sst->enable_miscbdcge(dai->dev, true);
316 skl->skl_sst->miscbdcg_disabled = false;
317 }
318
Jeeja KPa40e6932015-07-09 15:20:08 +0530319 kfree(dma_params);
320}
321
322static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
323 struct snd_soc_dai *dai)
324{
325 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
326 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
327
328 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
329
330 snd_hdac_stream_cleanup(hdac_stream(stream));
331 hdac_stream(stream)->prepared = 0;
332
333 return skl_substream_free_pages(ebus_to_hbus(ebus), substream);
334}
335
Jeeja KPb663a8c2015-10-07 11:31:57 +0100336static int skl_be_hw_params(struct snd_pcm_substream *substream,
337 struct snd_pcm_hw_params *params,
338 struct snd_soc_dai *dai)
339{
340 struct skl_pipe_params p_params = {0};
341
342 p_params.s_fmt = snd_pcm_format_width(params_format(params));
343 p_params.ch = params_channels(params);
344 p_params.s_freq = params_rate(params);
345 p_params.stream = substream->stream;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100346
Jeeja KP4bd073f2015-10-27 09:22:45 +0900347 return skl_tplg_be_update_params(dai, &p_params);
Jeeja KPb663a8c2015-10-07 11:31:57 +0100348}
349
Jeeja KPd1730c32015-10-27 09:22:53 +0900350static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
351 int cmd)
352{
353 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
354 struct hdac_bus *bus = ebus_to_hbus(ebus);
355 struct hdac_ext_stream *stream;
356 int start;
357 unsigned long cookie;
358 struct hdac_stream *hstr;
359
360 stream = get_hdac_ext_stream(substream);
361 hstr = hdac_stream(stream);
362
363 if (!hstr->prepared)
364 return -EPIPE;
365
366 switch (cmd) {
367 case SNDRV_PCM_TRIGGER_START:
368 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
369 case SNDRV_PCM_TRIGGER_RESUME:
370 start = 1;
371 break;
372
373 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
374 case SNDRV_PCM_TRIGGER_SUSPEND:
375 case SNDRV_PCM_TRIGGER_STOP:
376 start = 0;
377 break;
378
379 default:
380 return -EINVAL;
381 }
382
383 spin_lock_irqsave(&bus->reg_lock, cookie);
384
385 if (start) {
386 snd_hdac_stream_start(hdac_stream(stream), true);
387 snd_hdac_stream_timecounter_init(hstr, 0);
388 } else {
389 snd_hdac_stream_stop(hdac_stream(stream));
390 }
391
392 spin_unlock_irqrestore(&bus->reg_lock, cookie);
393
394 return 0;
395}
396
Jeeja KPb663a8c2015-10-07 11:31:57 +0100397static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
398 struct snd_soc_dai *dai)
399{
400 struct skl *skl = get_skl_ctx(dai->dev);
401 struct skl_sst *ctx = skl->skl_sst;
402 struct skl_module_cfg *mconfig;
Jeeja KP7e3a17d2015-11-23 22:26:24 +0530403 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
404 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
Jeeja KP9a655db2016-04-28 18:45:28 +0530405 struct snd_soc_dapm_widget *w;
Jeeja KPd1730c32015-10-27 09:22:53 +0900406 int ret;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100407
408 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
409 if (!mconfig)
410 return -EIO;
411
Jeeja KP9a655db2016-04-28 18:45:28 +0530412 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
413 w = dai->playback_widget;
414 else
415 w = dai->capture_widget;
416
Jeeja KPb663a8c2015-10-07 11:31:57 +0100417 switch (cmd) {
Jeeja KP7e3a17d2015-11-23 22:26:24 +0530418 case SNDRV_PCM_TRIGGER_RESUME:
Jeeja KP9a655db2016-04-28 18:45:28 +0530419 if (!w->ignore_suspend) {
420 skl_pcm_prepare(substream, dai);
421 /*
422 * enable DMA Resume enable bit for the stream, set the
423 * dpib & lpib position to resume before starting the
424 * DMA
425 */
426 snd_hdac_ext_stream_drsm_enable(ebus, true,
427 hdac_stream(stream)->index);
428 snd_hdac_ext_stream_set_dpibr(ebus, stream,
429 stream->dpib);
430 snd_hdac_ext_stream_set_lpib(stream, stream->lpib);
431 }
Jeeja KP748a1d52015-12-18 15:12:07 +0530432
Jeeja KPd1730c32015-10-27 09:22:53 +0900433 case SNDRV_PCM_TRIGGER_START:
Jeeja KPb663a8c2015-10-07 11:31:57 +0100434 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
Jeeja KPd1730c32015-10-27 09:22:53 +0900435 /*
436 * Start HOST DMA and Start FE Pipe.This is to make sure that
437 * there are no underrun/overrun in the case when the FE
438 * pipeline is started but there is a delay in starting the
439 * DMA channel on the host.
440 */
Jeeja KP7e3a17d2015-11-23 22:26:24 +0530441 snd_hdac_ext_stream_decouple(ebus, stream, true);
Jeeja KPd1730c32015-10-27 09:22:53 +0900442 ret = skl_decoupled_trigger(substream, cmd);
443 if (ret < 0)
444 return ret;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100445 return skl_run_pipe(ctx, mconfig->pipe);
Jeeja KPd1730c32015-10-27 09:22:53 +0900446 break;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100447
448 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
449 case SNDRV_PCM_TRIGGER_SUSPEND:
Jeeja KPd1730c32015-10-27 09:22:53 +0900450 case SNDRV_PCM_TRIGGER_STOP:
451 /*
452 * Stop FE Pipe first and stop DMA. This is to make sure that
453 * there are no underrun/overrun in the case if there is a delay
454 * between the two operations.
455 */
456 ret = skl_stop_pipe(ctx, mconfig->pipe);
457 if (ret < 0)
458 return ret;
459
460 ret = skl_decoupled_trigger(substream, cmd);
Jeeja KP9a655db2016-04-28 18:45:28 +0530461 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) {
Jeeja KP748a1d52015-12-18 15:12:07 +0530462 /* save the dpib and lpib positions */
463 stream->dpib = readl(ebus->bus.remap_addr +
464 AZX_REG_VS_SDXDPIB_XBASE +
465 (AZX_REG_VS_SDXDPIB_XINTERVAL *
466 hdac_stream(stream)->index));
467
468 stream->lpib = snd_hdac_stream_get_pos_lpib(
469 hdac_stream(stream));
Jeeja KP7e3a17d2015-11-23 22:26:24 +0530470 snd_hdac_ext_stream_decouple(ebus, stream, false);
Jeeja KP748a1d52015-12-18 15:12:07 +0530471 }
Jeeja KPd1730c32015-10-27 09:22:53 +0900472 break;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100473
474 default:
Jeeja KPd1730c32015-10-27 09:22:53 +0900475 return -EINVAL;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100476 }
Jeeja KPd1730c32015-10-27 09:22:53 +0900477
478 return 0;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100479}
480
Jeeja KP05057002015-07-09 15:20:11 +0530481static int skl_link_hw_params(struct snd_pcm_substream *substream,
482 struct snd_pcm_hw_params *params,
483 struct snd_soc_dai *dai)
484{
485 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
486 struct hdac_ext_stream *link_dev;
487 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
Subhransu S. Prustyaceb5d22016-02-17 21:34:05 +0530488 struct hdac_ext_dma_params *dma_params;
Jeeja KP05057002015-07-09 15:20:11 +0530489 struct snd_soc_dai *codec_dai = rtd->codec_dai;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100490 struct skl_pipe_params p_params = {0};
Jeeja KP05057002015-07-09 15:20:11 +0530491
Jeeja KP05057002015-07-09 15:20:11 +0530492 link_dev = snd_hdac_ext_stream_assign(ebus, substream,
493 HDAC_EXT_STREAM_TYPE_LINK);
494 if (!link_dev)
495 return -EBUSY;
496
497 snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
498
499 /* set the stream tag in the codec dai dma params */
Subhransu S. Prustyaceb5d22016-02-17 21:34:05 +0530500 dma_params = snd_soc_dai_get_dma_data(codec_dai, substream);
Jeeja KP05057002015-07-09 15:20:11 +0530501 if (dma_params)
502 dma_params->stream_tag = hdac_stream(link_dev)->stream_tag;
Jeeja KPb663a8c2015-10-07 11:31:57 +0100503
504 p_params.s_fmt = snd_pcm_format_width(params_format(params));
505 p_params.ch = params_channels(params);
506 p_params.s_freq = params_rate(params);
507 p_params.stream = substream->stream;
508 p_params.link_dma_id = hdac_stream(link_dev)->stream_tag - 1;
509
Jeeja KP4bd073f2015-10-27 09:22:45 +0900510 return skl_tplg_be_update_params(dai, &p_params);
Jeeja KP05057002015-07-09 15:20:11 +0530511}
512
513static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
514 struct snd_soc_dai *dai)
515{
516 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
517 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
518 struct hdac_ext_stream *link_dev =
519 snd_soc_dai_get_dma_data(dai, substream);
520 unsigned int format_val = 0;
521 struct skl_dma_params *dma_params;
522 struct snd_soc_dai *codec_dai = rtd->codec_dai;
Jeeja KP05057002015-07-09 15:20:11 +0530523 struct hdac_ext_link *link;
524
Jeeja KP05057002015-07-09 15:20:11 +0530525 dma_params = (struct skl_dma_params *)
526 snd_soc_dai_get_dma_data(codec_dai, substream);
527 if (dma_params)
528 format_val = dma_params->format;
529 dev_dbg(dai->dev, "stream_tag=%d formatvalue=%d codec_dai_name=%s\n",
530 hdac_stream(link_dev)->stream_tag, format_val, codec_dai->name);
531
Jeeja KP05057002015-07-09 15:20:11 +0530532 link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name);
533 if (!link)
534 return -EINVAL;
535
Jeeja KP920982c2015-12-18 15:12:08 +0530536 snd_hdac_ext_bus_link_power_up(link);
537 snd_hdac_ext_link_stream_reset(link_dev);
538
539 snd_hdac_ext_link_stream_setup(link_dev, format_val);
540
Jeeja KP05057002015-07-09 15:20:11 +0530541 snd_hdac_ext_link_set_stream_id(link, hdac_stream(link_dev)->stream_tag);
542 link_dev->link_prepared = 1;
543
544 return 0;
545}
546
547static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
548 int cmd, struct snd_soc_dai *dai)
549{
550 struct hdac_ext_stream *link_dev =
551 snd_soc_dai_get_dma_data(dai, substream);
Jeeja KP920982c2015-12-18 15:12:08 +0530552 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
553 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
Jeeja KP05057002015-07-09 15:20:11 +0530554
555 dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
556 switch (cmd) {
Jeeja KP920982c2015-12-18 15:12:08 +0530557 case SNDRV_PCM_TRIGGER_RESUME:
558 skl_link_pcm_prepare(substream, dai);
Jeeja KP05057002015-07-09 15:20:11 +0530559 case SNDRV_PCM_TRIGGER_START:
560 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
Jeeja KP920982c2015-12-18 15:12:08 +0530561 snd_hdac_ext_stream_decouple(ebus, stream, true);
Jeeja KP05057002015-07-09 15:20:11 +0530562 snd_hdac_ext_link_stream_start(link_dev);
563 break;
564
565 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
566 case SNDRV_PCM_TRIGGER_SUSPEND:
567 case SNDRV_PCM_TRIGGER_STOP:
568 snd_hdac_ext_link_stream_clear(link_dev);
Jeeja KP920982c2015-12-18 15:12:08 +0530569 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
570 snd_hdac_ext_stream_decouple(ebus, stream, false);
Jeeja KP05057002015-07-09 15:20:11 +0530571 break;
572
573 default:
574 return -EINVAL;
575 }
576 return 0;
577}
578
579static int skl_link_hw_free(struct snd_pcm_substream *substream,
580 struct snd_soc_dai *dai)
581{
582 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
583 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
584 struct hdac_ext_stream *link_dev =
585 snd_soc_dai_get_dma_data(dai, substream);
586 struct hdac_ext_link *link;
587
588 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
589
590 link_dev->link_prepared = 0;
591
592 link = snd_hdac_ext_bus_get_link(ebus, rtd->codec->component.name);
593 if (!link)
594 return -EINVAL;
595
596 snd_hdac_ext_link_clear_stream_id(link, hdac_stream(link_dev)->stream_tag);
597 snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
598 return 0;
599}
600
Jeeja KPa40e6932015-07-09 15:20:08 +0530601static struct snd_soc_dai_ops skl_pcm_dai_ops = {
602 .startup = skl_pcm_open,
603 .shutdown = skl_pcm_close,
604 .prepare = skl_pcm_prepare,
605 .hw_params = skl_pcm_hw_params,
606 .hw_free = skl_pcm_hw_free,
Jeeja KPb663a8c2015-10-07 11:31:57 +0100607 .trigger = skl_pcm_trigger,
Jeeja KPa40e6932015-07-09 15:20:08 +0530608};
609
Jeeja KP05057002015-07-09 15:20:11 +0530610static struct snd_soc_dai_ops skl_dmic_dai_ops = {
Jeeja KPb663a8c2015-10-07 11:31:57 +0100611 .hw_params = skl_be_hw_params,
Jeeja KPb663a8c2015-10-07 11:31:57 +0100612};
613
614static struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
Jeeja KPb663a8c2015-10-07 11:31:57 +0100615 .hw_params = skl_be_hw_params,
Dharageswari.Rc115fa52016-02-05 12:19:07 +0530616 .prepare = skl_be_prepare,
Jeeja KP05057002015-07-09 15:20:11 +0530617};
618
619static struct snd_soc_dai_ops skl_link_dai_ops = {
Jeeja KP05057002015-07-09 15:20:11 +0530620 .prepare = skl_link_pcm_prepare,
621 .hw_params = skl_link_hw_params,
622 .hw_free = skl_link_hw_free,
623 .trigger = skl_link_pcm_trigger,
Jeeja KP05057002015-07-09 15:20:11 +0530624};
625
Jeeja KPa40e6932015-07-09 15:20:08 +0530626static struct snd_soc_dai_driver skl_platform_dai[] = {
627{
628 .name = "System Pin",
629 .ops = &skl_pcm_dai_ops,
630 .playback = {
631 .stream_name = "System Playback",
632 .channels_min = HDA_MONO,
633 .channels_max = HDA_STEREO,
634 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
635 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
636 },
637 .capture = {
638 .stream_name = "System Capture",
639 .channels_min = HDA_MONO,
640 .channels_max = HDA_STEREO,
641 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
642 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
643 },
644},
645{
Jeeja KP05057002015-07-09 15:20:11 +0530646 .name = "Reference Pin",
647 .ops = &skl_pcm_dai_ops,
648 .capture = {
649 .stream_name = "Reference Capture",
650 .channels_min = HDA_MONO,
Jeeja KP8f35bf32015-11-28 15:01:46 +0530651 .channels_max = HDA_QUAD,
Jeeja KP05057002015-07-09 15:20:11 +0530652 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
653 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
654 },
655},
656{
Jeeja KPa40e6932015-07-09 15:20:08 +0530657 .name = "Deepbuffer Pin",
658 .ops = &skl_pcm_dai_ops,
659 .playback = {
660 .stream_name = "Deepbuffer Playback",
661 .channels_min = HDA_STEREO,
662 .channels_max = HDA_STEREO,
663 .rates = SNDRV_PCM_RATE_48000,
664 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
665 },
666},
667{
668 .name = "LowLatency Pin",
669 .ops = &skl_pcm_dai_ops,
670 .playback = {
671 .stream_name = "Low Latency Playback",
672 .channels_min = HDA_STEREO,
673 .channels_max = HDA_STEREO,
674 .rates = SNDRV_PCM_RATE_48000,
675 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
676 },
677},
Jeeja KP8f35bf32015-11-28 15:01:46 +0530678{
679 .name = "DMIC Pin",
680 .ops = &skl_pcm_dai_ops,
681 .capture = {
682 .stream_name = "DMIC Capture",
683 .channels_min = HDA_MONO,
684 .channels_max = HDA_QUAD,
685 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
686 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
687 },
688},
Subhransu S. Prusty8cca87c2016-02-17 21:34:07 +0530689{
690 .name = "HDMI1 Pin",
691 .ops = &skl_pcm_dai_ops,
692 .playback = {
693 .stream_name = "HDMI1 Playback",
694 .channels_min = HDA_STEREO,
695 .channels_max = HDA_STEREO,
696 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
697 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
698 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
699 SNDRV_PCM_RATE_192000,
700 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
701 SNDRV_PCM_FMTBIT_S32_LE,
702 },
703},
704{
705 .name = "HDMI2 Pin",
706 .ops = &skl_pcm_dai_ops,
707 .playback = {
708 .stream_name = "HDMI2 Playback",
709 .channels_min = HDA_STEREO,
710 .channels_max = HDA_STEREO,
711 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
712 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
713 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
714 SNDRV_PCM_RATE_192000,
715 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
716 SNDRV_PCM_FMTBIT_S32_LE,
717 },
718},
719{
720 .name = "HDMI3 Pin",
721 .ops = &skl_pcm_dai_ops,
722 .playback = {
723 .stream_name = "HDMI3 Playback",
724 .channels_min = HDA_STEREO,
725 .channels_max = HDA_STEREO,
726 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
727 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
728 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
729 SNDRV_PCM_RATE_192000,
730 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
731 SNDRV_PCM_FMTBIT_S32_LE,
732 },
733},
Jeeja KP8f35bf32015-11-28 15:01:46 +0530734
Jeeja KP05057002015-07-09 15:20:11 +0530735/* BE CPU Dais */
736{
Jeeja KPb663a8c2015-10-07 11:31:57 +0100737 .name = "SSP0 Pin",
738 .ops = &skl_be_ssp_dai_ops,
739 .playback = {
740 .stream_name = "ssp0 Tx",
741 .channels_min = HDA_STEREO,
742 .channels_max = HDA_STEREO,
743 .rates = SNDRV_PCM_RATE_48000,
744 .formats = SNDRV_PCM_FMTBIT_S16_LE,
745 },
746 .capture = {
747 .stream_name = "ssp0 Rx",
748 .channels_min = HDA_STEREO,
749 .channels_max = HDA_STEREO,
750 .rates = SNDRV_PCM_RATE_48000,
751 .formats = SNDRV_PCM_FMTBIT_S16_LE,
752 },
753},
754{
Jeeja KPc80fd4d2015-11-05 22:53:06 +0530755 .name = "SSP1 Pin",
756 .ops = &skl_be_ssp_dai_ops,
757 .playback = {
758 .stream_name = "ssp1 Tx",
759 .channels_min = HDA_STEREO,
760 .channels_max = HDA_STEREO,
761 .rates = SNDRV_PCM_RATE_48000,
762 .formats = SNDRV_PCM_FMTBIT_S16_LE,
763 },
764 .capture = {
765 .stream_name = "ssp1 Rx",
766 .channels_min = HDA_STEREO,
767 .channels_max = HDA_STEREO,
768 .rates = SNDRV_PCM_RATE_48000,
769 .formats = SNDRV_PCM_FMTBIT_S16_LE,
770 },
771},
772{
Subhransu S. Prusty8cca87c2016-02-17 21:34:07 +0530773 .name = "iDisp1 Pin",
Jeeja KP05057002015-07-09 15:20:11 +0530774 .ops = &skl_link_dai_ops,
775 .playback = {
Subhransu S. Prusty8cca87c2016-02-17 21:34:07 +0530776 .stream_name = "iDisp1 Tx",
Jeeja KP05057002015-07-09 15:20:11 +0530777 .channels_min = HDA_STEREO,
778 .channels_max = HDA_STEREO,
779 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
Subhransu S. Prusty8cca87c2016-02-17 21:34:07 +0530780 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
781 SNDRV_PCM_FMTBIT_S24_LE,
782 },
783},
784{
785 .name = "iDisp2 Pin",
786 .ops = &skl_link_dai_ops,
787 .playback = {
788 .stream_name = "iDisp2 Tx",
789 .channels_min = HDA_STEREO,
790 .channels_max = HDA_STEREO,
791 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
792 SNDRV_PCM_RATE_48000,
793 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
794 SNDRV_PCM_FMTBIT_S24_LE,
795 },
796},
797{
798 .name = "iDisp3 Pin",
799 .ops = &skl_link_dai_ops,
800 .playback = {
801 .stream_name = "iDisp3 Tx",
802 .channels_min = HDA_STEREO,
803 .channels_max = HDA_STEREO,
804 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
805 SNDRV_PCM_RATE_48000,
806 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
807 SNDRV_PCM_FMTBIT_S24_LE,
Jeeja KP05057002015-07-09 15:20:11 +0530808 },
809},
810{
811 .name = "DMIC01 Pin",
812 .ops = &skl_dmic_dai_ops,
813 .capture = {
814 .stream_name = "DMIC01 Rx",
Jeeja KP8f35bf32015-11-28 15:01:46 +0530815 .channels_min = HDA_MONO,
816 .channels_max = HDA_QUAD,
Jeeja KP05057002015-07-09 15:20:11 +0530817 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
818 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
819 },
820},
821{
Jeeja KP05057002015-07-09 15:20:11 +0530822 .name = "HD-Codec Pin",
823 .ops = &skl_link_dai_ops,
824 .playback = {
825 .stream_name = "HD-Codec Tx",
826 .channels_min = HDA_STEREO,
827 .channels_max = HDA_STEREO,
828 .rates = SNDRV_PCM_RATE_48000,
829 .formats = SNDRV_PCM_FMTBIT_S16_LE,
830 },
831 .capture = {
832 .stream_name = "HD-Codec Rx",
833 .channels_min = HDA_STEREO,
834 .channels_max = HDA_STEREO,
835 .rates = SNDRV_PCM_RATE_48000,
836 .formats = SNDRV_PCM_FMTBIT_S16_LE,
837 },
838},
Jeeja KPa40e6932015-07-09 15:20:08 +0530839};
840
841static int skl_platform_open(struct snd_pcm_substream *substream)
842{
843 struct snd_pcm_runtime *runtime;
844 struct snd_soc_pcm_runtime *rtd = substream->private_data;
845 struct snd_soc_dai_link *dai_link = rtd->dai_link;
846
847 dev_dbg(rtd->cpu_dai->dev, "In %s:%s\n", __func__,
848 dai_link->cpu_dai_name);
849
850 runtime = substream->runtime;
851 snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
852
853 return 0;
854}
855
Jeeja KPb663a8c2015-10-07 11:31:57 +0100856static int skl_coupled_trigger(struct snd_pcm_substream *substream,
Jeeja KPa40e6932015-07-09 15:20:08 +0530857 int cmd)
858{
859 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
860 struct hdac_bus *bus = ebus_to_hbus(ebus);
861 struct hdac_ext_stream *stream;
862 struct snd_pcm_substream *s;
863 bool start;
864 int sbits = 0;
865 unsigned long cookie;
866 struct hdac_stream *hstr;
867
868 stream = get_hdac_ext_stream(substream);
869 hstr = hdac_stream(stream);
870
871 dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
872
873 if (!hstr->prepared)
874 return -EPIPE;
875
876 switch (cmd) {
877 case SNDRV_PCM_TRIGGER_START:
878 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
879 case SNDRV_PCM_TRIGGER_RESUME:
880 start = true;
881 break;
882
883 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
884 case SNDRV_PCM_TRIGGER_SUSPEND:
885 case SNDRV_PCM_TRIGGER_STOP:
886 start = false;
887 break;
888
889 default:
890 return -EINVAL;
891 }
892
893 snd_pcm_group_for_each_entry(s, substream) {
894 if (s->pcm->card != substream->pcm->card)
895 continue;
896 stream = get_hdac_ext_stream(s);
897 sbits |= 1 << hdac_stream(stream)->index;
898 snd_pcm_trigger_done(s, substream);
899 }
900
901 spin_lock_irqsave(&bus->reg_lock, cookie);
902
903 /* first, set SYNC bits of corresponding streams */
904 snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
905
906 snd_pcm_group_for_each_entry(s, substream) {
907 if (s->pcm->card != substream->pcm->card)
908 continue;
909 stream = get_hdac_ext_stream(s);
910 if (start)
911 snd_hdac_stream_start(hdac_stream(stream), true);
912 else
913 snd_hdac_stream_stop(hdac_stream(stream));
914 }
915 spin_unlock_irqrestore(&bus->reg_lock, cookie);
916
917 snd_hdac_stream_sync(hstr, start, sbits);
918
919 spin_lock_irqsave(&bus->reg_lock, cookie);
920
921 /* reset SYNC bits */
922 snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
923 if (start)
924 snd_hdac_stream_timecounter_init(hstr, sbits);
925 spin_unlock_irqrestore(&bus->reg_lock, cookie);
926
927 return 0;
928}
929
Jeeja KP05057002015-07-09 15:20:11 +0530930static int skl_platform_pcm_trigger(struct snd_pcm_substream *substream,
931 int cmd)
932{
933 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
934
Jeeja KPd1730c32015-10-27 09:22:53 +0900935 if (!ebus->ppcap)
Jeeja KPb663a8c2015-10-07 11:31:57 +0100936 return skl_coupled_trigger(substream, cmd);
Jeeja KPd1730c32015-10-27 09:22:53 +0900937
938 return 0;
Jeeja KP05057002015-07-09 15:20:11 +0530939}
940
Jeeja KPa40e6932015-07-09 15:20:08 +0530941/* calculate runtime delay from LPIB */
942static int skl_get_delay_from_lpib(struct hdac_ext_bus *ebus,
943 struct hdac_ext_stream *sstream,
944 unsigned int pos)
945{
946 struct hdac_bus *bus = ebus_to_hbus(ebus);
947 struct hdac_stream *hstream = hdac_stream(sstream);
948 struct snd_pcm_substream *substream = hstream->substream;
949 int stream = substream->stream;
950 unsigned int lpib_pos = snd_hdac_stream_get_pos_lpib(hstream);
951 int delay;
952
953 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
954 delay = pos - lpib_pos;
955 else
956 delay = lpib_pos - pos;
957
958 if (delay < 0) {
959 if (delay >= hstream->delay_negative_threshold)
960 delay = 0;
961 else
962 delay += hstream->bufsize;
963 }
Vinod Koul33420d62016-02-05 12:19:04 +0530964
965 if (hstream->bufsize == delay)
966 delay = 0;
Jeeja KPa40e6932015-07-09 15:20:08 +0530967
968 if (delay >= hstream->period_bytes) {
969 dev_info(bus->dev,
970 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n",
971 delay, hstream->period_bytes);
972 delay = 0;
973 }
974
975 return bytes_to_frames(substream->runtime, delay);
976}
977
978static unsigned int skl_get_position(struct hdac_ext_stream *hstream,
979 int codec_delay)
980{
981 struct hdac_stream *hstr = hdac_stream(hstream);
982 struct snd_pcm_substream *substream = hstr->substream;
Vinod Koulc7b2a442015-10-30 20:34:20 +0530983 struct hdac_ext_bus *ebus;
Jeeja KPa40e6932015-07-09 15:20:08 +0530984 unsigned int pos;
985 int delay;
986
987 /* use the position buffer as default */
988 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
989
990 if (pos >= hdac_stream(hstream)->bufsize)
991 pos = 0;
992
993 if (substream->runtime) {
Vinod Koulc7b2a442015-10-30 20:34:20 +0530994 ebus = get_bus_ctx(substream);
Jeeja KPa40e6932015-07-09 15:20:08 +0530995 delay = skl_get_delay_from_lpib(ebus, hstream, pos)
996 + codec_delay;
997 substream->runtime->delay += delay;
998 }
999
1000 return pos;
1001}
1002
1003static snd_pcm_uframes_t skl_platform_pcm_pointer
1004 (struct snd_pcm_substream *substream)
1005{
1006 struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
1007
1008 return bytes_to_frames(substream->runtime,
1009 skl_get_position(hstream, 0));
1010}
1011
1012static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
1013 u64 nsec)
1014{
1015 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
1016 struct snd_soc_dai *codec_dai = rtd->codec_dai;
1017 u64 codec_frames, codec_nsecs;
1018
1019 if (!codec_dai->driver->ops->delay)
1020 return nsec;
1021
1022 codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
1023 codec_nsecs = div_u64(codec_frames * 1000000000LL,
1024 substream->runtime->rate);
1025
1026 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1027 return nsec + codec_nsecs;
1028
1029 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1030}
1031
1032static int skl_get_time_info(struct snd_pcm_substream *substream,
1033 struct timespec *system_ts, struct timespec *audio_ts,
1034 struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
1035 struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
1036{
1037 struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
1038 struct hdac_stream *hstr = hdac_stream(sstream);
1039 u64 nsec;
1040
1041 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
1042 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
1043
1044 snd_pcm_gettime(substream->runtime, system_ts);
1045
1046 nsec = timecounter_read(&hstr->tc);
1047 nsec = div_u64(nsec, 3); /* can be optimized */
1048 if (audio_tstamp_config->report_delay)
1049 nsec = skl_adjust_codec_delay(substream, nsec);
1050
1051 *audio_ts = ns_to_timespec(nsec);
1052
1053 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
1054 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
1055 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
1056
1057 } else {
1058 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
1059 }
1060
1061 return 0;
1062}
1063
1064static struct snd_pcm_ops skl_platform_ops = {
1065 .open = skl_platform_open,
1066 .ioctl = snd_pcm_lib_ioctl,
1067 .trigger = skl_platform_pcm_trigger,
1068 .pointer = skl_platform_pcm_pointer,
1069 .get_time_info = skl_get_time_info,
1070 .mmap = snd_pcm_lib_default_mmap,
1071 .page = snd_pcm_sgbuf_ops_page,
1072};
1073
1074static void skl_pcm_free(struct snd_pcm *pcm)
1075{
1076 snd_pcm_lib_preallocate_free_for_all(pcm);
1077}
1078
1079#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
1080
1081static int skl_pcm_new(struct snd_soc_pcm_runtime *rtd)
1082{
1083 struct snd_soc_dai *dai = rtd->cpu_dai;
1084 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
1085 struct snd_pcm *pcm = rtd->pcm;
1086 unsigned int size;
1087 int retval = 0;
1088 struct skl *skl = ebus_to_skl(ebus);
1089
1090 if (dai->driver->playback.channels_min ||
1091 dai->driver->capture.channels_min) {
1092 /* buffer pre-allocation */
1093 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
1094 if (size > MAX_PREALLOC_SIZE)
1095 size = MAX_PREALLOC_SIZE;
1096 retval = snd_pcm_lib_preallocate_pages_for_all(pcm,
1097 SNDRV_DMA_TYPE_DEV_SG,
1098 snd_dma_pci_data(skl->pci),
1099 size, MAX_PREALLOC_SIZE);
1100 if (retval) {
1101 dev_err(dai->dev, "dma buffer allocationf fail\n");
1102 return retval;
1103 }
1104 }
1105
1106 return retval;
1107}
1108
Jeeja KPb663a8c2015-10-07 11:31:57 +01001109static int skl_platform_soc_probe(struct snd_soc_platform *platform)
1110{
1111 struct hdac_ext_bus *ebus = dev_get_drvdata(platform->dev);
1112
1113 if (ebus->ppcap)
1114 return skl_tplg_init(platform, ebus);
1115
1116 return 0;
1117}
Jeeja KPa40e6932015-07-09 15:20:08 +05301118static struct snd_soc_platform_driver skl_platform_drv = {
Jeeja KPb663a8c2015-10-07 11:31:57 +01001119 .probe = skl_platform_soc_probe,
Jeeja KPa40e6932015-07-09 15:20:08 +05301120 .ops = &skl_platform_ops,
1121 .pcm_new = skl_pcm_new,
1122 .pcm_free = skl_pcm_free,
1123};
1124
1125static const struct snd_soc_component_driver skl_component = {
1126 .name = "pcm",
1127};
1128
1129int skl_platform_register(struct device *dev)
1130{
1131 int ret;
Jeeja KPb663a8c2015-10-07 11:31:57 +01001132 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
1133 struct skl *skl = ebus_to_skl(ebus);
1134
1135 INIT_LIST_HEAD(&skl->ppl_list);
Jeeja KPa40e6932015-07-09 15:20:08 +05301136
1137 ret = snd_soc_register_platform(dev, &skl_platform_drv);
1138 if (ret) {
1139 dev_err(dev, "soc platform registration failed %d\n", ret);
1140 return ret;
1141 }
1142 ret = snd_soc_register_component(dev, &skl_component,
1143 skl_platform_dai,
1144 ARRAY_SIZE(skl_platform_dai));
1145 if (ret) {
1146 dev_err(dev, "soc component registration failed %d\n", ret);
1147 snd_soc_unregister_platform(dev);
1148 }
1149
1150 return ret;
1151
1152}
1153
1154int skl_platform_unregister(struct device *dev)
1155{
1156 snd_soc_unregister_component(dev);
1157 snd_soc_unregister_platform(dev);
1158 return 0;
1159}