blob: e0fec68aed2511220206960a1b0930cf65e696b8 [file] [log] [blame]
Zhang Wei173acc72008-03-01 07:42:48 -07001/*
2 * Freescale MPC85xx, MPC83xx DMA Engine support
3 *
Li Yange2c8e4252010-11-11 20:16:29 +08004 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
Zhang Wei173acc72008-03-01 07:42:48 -07005 *
6 * Author:
7 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007
8 * Ebony Zhu <ebony.zhu@freescale.com>, May 2007
9 *
10 * Description:
11 * DMA engine driver for Freescale MPC8540 DMA controller, which is
12 * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
Stefan Weilc2e07b32010-08-03 19:44:52 +020013 * The support for MPC8349 DMA controller is also added.
Zhang Wei173acc72008-03-01 07:42:48 -070014 *
Ira W. Snydera7aea372009-04-23 16:17:54 -070015 * This driver instructs the DMA controller to issue the PCI Read Multiple
16 * command for PCI read operations, instead of using the default PCI Read Line
17 * command. Please be aware that this setting may result in read pre-fetching
18 * on some platforms.
19 *
Zhang Wei173acc72008-03-01 07:42:48 -070020 * This is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 */
26
27#include <linux/init.h>
28#include <linux/module.h>
29#include <linux/pci.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Zhang Wei173acc72008-03-01 07:42:48 -070031#include <linux/interrupt.h>
32#include <linux/dmaengine.h>
33#include <linux/delay.h>
34#include <linux/dma-mapping.h>
35#include <linux/dmapool.h>
Rob Herring5af50732013-09-17 14:28:33 -050036#include <linux/of_address.h>
37#include <linux/of_irq.h>
Zhang Wei173acc72008-03-01 07:42:48 -070038#include <linux/of_platform.h>
39
Russell King - ARM Linuxd2ebfb32012-03-06 22:34:26 +000040#include "dmaengine.h"
Zhang Wei173acc72008-03-01 07:42:48 -070041#include "fsldma.h"
42
Ira Snyderb1584712011-03-03 07:54:55 +000043#define chan_dbg(chan, fmt, arg...) \
44 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
45#define chan_err(chan, fmt, arg...) \
46 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
Ira Snyderc14330412010-09-30 11:46:45 +000047
Ira Snyderb1584712011-03-03 07:54:55 +000048static const char msg_ld_oom[] = "No free memory for link descriptor";
Zhang Wei173acc72008-03-01 07:42:48 -070049
Ira Snydere8bd84d2011-03-03 07:54:54 +000050/*
51 * Register Helpers
52 */
Zhang Wei173acc72008-03-01 07:42:48 -070053
Ira Snydera1c03312010-01-06 13:34:05 +000054static void set_sr(struct fsldma_chan *chan, u32 val)
Zhang Wei173acc72008-03-01 07:42:48 -070055{
Ira Snydera1c03312010-01-06 13:34:05 +000056 DMA_OUT(chan, &chan->regs->sr, val, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070057}
58
Ira Snydera1c03312010-01-06 13:34:05 +000059static u32 get_sr(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -070060{
Ira Snydera1c03312010-01-06 13:34:05 +000061 return DMA_IN(chan, &chan->regs->sr, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070062}
63
Hongbo Zhangccdce9a2014-04-18 16:17:45 +080064static void set_mr(struct fsldma_chan *chan, u32 val)
65{
66 DMA_OUT(chan, &chan->regs->mr, val, 32);
67}
68
69static u32 get_mr(struct fsldma_chan *chan)
70{
71 return DMA_IN(chan, &chan->regs->mr, 32);
72}
73
Ira Snydera1c03312010-01-06 13:34:05 +000074static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
Zhang Wei173acc72008-03-01 07:42:48 -070075{
Ira Snydera1c03312010-01-06 13:34:05 +000076 DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
Zhang Wei173acc72008-03-01 07:42:48 -070077}
78
Ira Snydera1c03312010-01-06 13:34:05 +000079static dma_addr_t get_cdar(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -070080{
Ira Snydera1c03312010-01-06 13:34:05 +000081 return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
Zhang Wei173acc72008-03-01 07:42:48 -070082}
83
Hongbo Zhangccdce9a2014-04-18 16:17:45 +080084static void set_bcr(struct fsldma_chan *chan, u32 val)
85{
86 DMA_OUT(chan, &chan->regs->bcr, val, 32);
87}
88
Ira Snydera1c03312010-01-06 13:34:05 +000089static u32 get_bcr(struct fsldma_chan *chan)
Zhang Weif79abb62008-03-18 18:45:00 -070090{
Ira Snydera1c03312010-01-06 13:34:05 +000091 return DMA_IN(chan, &chan->regs->bcr, 32);
Zhang Weif79abb62008-03-18 18:45:00 -070092}
93
Ira Snydere8bd84d2011-03-03 07:54:54 +000094/*
95 * Descriptor Helpers
96 */
97
Zhang Wei173acc72008-03-01 07:42:48 -070098static void set_desc_cnt(struct fsldma_chan *chan,
99 struct fsl_dma_ld_hw *hw, u32 count)
Zhang Wei173acc72008-03-01 07:42:48 -0700100{
Zhang Wei173acc72008-03-01 07:42:48 -0700101 hw->count = CPU_TO_DMA(chan, count, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700102}
103
Zhang Wei173acc72008-03-01 07:42:48 -0700104static void set_desc_src(struct fsldma_chan *chan,
Ira Snyder31f43062011-03-03 07:54:57 +0000105 struct fsl_dma_ld_hw *hw, dma_addr_t src)
Zhang Wei173acc72008-03-01 07:42:48 -0700106{
Zhang Wei173acc72008-03-01 07:42:48 -0700107 u64 snoop_bits;
Dan Williams900325a2009-03-02 15:33:46 -0700108
Zhang Wei173acc72008-03-01 07:42:48 -0700109 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
110 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
111 hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700112}
113
Zhang Wei173acc72008-03-01 07:42:48 -0700114static void set_desc_dst(struct fsldma_chan *chan,
Ira Snyder31f43062011-03-03 07:54:57 +0000115 struct fsl_dma_ld_hw *hw, dma_addr_t dst)
Zhang Wei173acc72008-03-01 07:42:48 -0700116{
117 u64 snoop_bits;
118
119 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
120 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
121 hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
122}
123
124static void set_desc_next(struct fsldma_chan *chan,
Ira Snyder31f43062011-03-03 07:54:57 +0000125 struct fsl_dma_ld_hw *hw, dma_addr_t next)
Zhang Wei173acc72008-03-01 07:42:48 -0700126{
127 u64 snoop_bits;
128
129 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
130 ? FSL_DMA_SNEN : 0;
131 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
132}
133
Ira Snyder31f43062011-03-03 07:54:57 +0000134static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
Zhang Wei173acc72008-03-01 07:42:48 -0700135{
Ira Snyder776c8942009-05-15 11:33:20 -0700136 u64 snoop_bits;
137
Ira Snydera1c03312010-01-06 13:34:05 +0000138 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
Ira Snyder776c8942009-05-15 11:33:20 -0700139 ? FSL_DMA_SNEN : 0;
140
Ira Snydera1c03312010-01-06 13:34:05 +0000141 desc->hw.next_ln_addr = CPU_TO_DMA(chan,
142 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
Ira Snyder776c8942009-05-15 11:33:20 -0700143 | snoop_bits, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700144}
145
Ira Snydere8bd84d2011-03-03 07:54:54 +0000146/*
147 * DMA Engine Hardware Control Helpers
148 */
Zhang Wei173acc72008-03-01 07:42:48 -0700149
Ira Snydere8bd84d2011-03-03 07:54:54 +0000150static void dma_init(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700151{
Ira Snydere8bd84d2011-03-03 07:54:54 +0000152 /* Reset the channel */
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800153 set_mr(chan, 0);
Zhang Wei173acc72008-03-01 07:42:48 -0700154
Ira Snydere8bd84d2011-03-03 07:54:54 +0000155 switch (chan->feature & FSL_DMA_IP_MASK) {
156 case FSL_DMA_IP_85XX:
157 /* Set the channel to below modes:
158 * EIE - Error interrupt enable
Ira Snydere8bd84d2011-03-03 07:54:54 +0000159 * EOLNIE - End of links interrupt enable
160 * BWC - Bandwidth sharing among channels
161 */
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800162 set_mr(chan, FSL_DMA_MR_BWC | FSL_DMA_MR_EIE
163 | FSL_DMA_MR_EOLNIE);
Ira Snydere8bd84d2011-03-03 07:54:54 +0000164 break;
165 case FSL_DMA_IP_83XX:
166 /* Set the channel to below modes:
167 * EOTIE - End-of-transfer interrupt enable
168 * PRC_RM - PCI read multiple
169 */
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800170 set_mr(chan, FSL_DMA_MR_EOTIE | FSL_DMA_MR_PRC_RM);
Ira Snydere8bd84d2011-03-03 07:54:54 +0000171 break;
172 }
Zhang Wei173acc72008-03-01 07:42:48 -0700173}
174
175static int dma_is_idle(struct fsldma_chan *chan)
176{
177 u32 sr = get_sr(chan);
178 return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
179}
180
Ira Snyderf04cd402011-03-03 07:54:58 +0000181/*
182 * Start the DMA controller
183 *
184 * Preconditions:
185 * - the CDAR register must point to the start descriptor
186 * - the MRn[CS] bit must be cleared
187 */
Zhang Wei173acc72008-03-01 07:42:48 -0700188static void dma_start(struct fsldma_chan *chan)
189{
190 u32 mode;
191
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800192 mode = get_mr(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700193
Ira Snyderf04cd402011-03-03 07:54:58 +0000194 if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800195 set_bcr(chan, 0);
Ira Snyderf04cd402011-03-03 07:54:58 +0000196 mode |= FSL_DMA_MR_EMP_EN;
197 } else {
198 mode &= ~FSL_DMA_MR_EMP_EN;
Zhang Wei173acc72008-03-01 07:42:48 -0700199 }
200
Ira Snyderf04cd402011-03-03 07:54:58 +0000201 if (chan->feature & FSL_DMA_CHAN_START_EXT) {
Zhang Wei173acc72008-03-01 07:42:48 -0700202 mode |= FSL_DMA_MR_EMS_EN;
Ira Snyderf04cd402011-03-03 07:54:58 +0000203 } else {
204 mode &= ~FSL_DMA_MR_EMS_EN;
Zhang Wei173acc72008-03-01 07:42:48 -0700205 mode |= FSL_DMA_MR_CS;
Ira Snyderf04cd402011-03-03 07:54:58 +0000206 }
Zhang Wei173acc72008-03-01 07:42:48 -0700207
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800208 set_mr(chan, mode);
Zhang Wei173acc72008-03-01 07:42:48 -0700209}
210
211static void dma_halt(struct fsldma_chan *chan)
212{
213 u32 mode;
214 int i;
215
Ira Snydera00ae342011-03-03 07:55:01 +0000216 /* read the mode register */
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800217 mode = get_mr(chan);
Ira Snydera00ae342011-03-03 07:55:01 +0000218
219 /*
220 * The 85xx controller supports channel abort, which will stop
221 * the current transfer. On 83xx, this bit is the transfer error
222 * mask bit, which should not be changed.
223 */
224 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
225 mode |= FSL_DMA_MR_CA;
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800226 set_mr(chan, mode);
Ira Snydera00ae342011-03-03 07:55:01 +0000227
228 mode &= ~FSL_DMA_MR_CA;
229 }
230
231 /* stop the DMA controller */
232 mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN);
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800233 set_mr(chan, mode);
Zhang Wei173acc72008-03-01 07:42:48 -0700234
Ira Snydera00ae342011-03-03 07:55:01 +0000235 /* wait for the DMA controller to become idle */
Zhang Wei173acc72008-03-01 07:42:48 -0700236 for (i = 0; i < 100; i++) {
237 if (dma_is_idle(chan))
238 return;
239
240 udelay(10);
241 }
242
243 if (!dma_is_idle(chan))
Ira Snyderb1584712011-03-03 07:54:55 +0000244 chan_err(chan, "DMA halt timeout!\n");
Zhang Wei173acc72008-03-01 07:42:48 -0700245}
246
Zhang Wei173acc72008-03-01 07:42:48 -0700247/**
248 * fsl_chan_set_src_loop_size - Set source address hold transfer size
Ira Snydera1c03312010-01-06 13:34:05 +0000249 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700250 * @size : Address loop size, 0 for disable loop
251 *
252 * The set source address hold transfer size. The source
253 * address hold or loop transfer size is when the DMA transfer
254 * data from source address (SA), if the loop size is 4, the DMA will
255 * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
256 * SA + 1 ... and so on.
257 */
Ira Snydera1c03312010-01-06 13:34:05 +0000258static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
Zhang Wei173acc72008-03-01 07:42:48 -0700259{
Ira Snyder272ca652010-01-06 13:33:59 +0000260 u32 mode;
261
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800262 mode = get_mr(chan);
Ira Snyder272ca652010-01-06 13:33:59 +0000263
Zhang Wei173acc72008-03-01 07:42:48 -0700264 switch (size) {
265 case 0:
Ira Snyder272ca652010-01-06 13:33:59 +0000266 mode &= ~FSL_DMA_MR_SAHE;
Zhang Wei173acc72008-03-01 07:42:48 -0700267 break;
268 case 1:
269 case 2:
270 case 4:
271 case 8:
Ira Snyder272ca652010-01-06 13:33:59 +0000272 mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
Zhang Wei173acc72008-03-01 07:42:48 -0700273 break;
274 }
Ira Snyder272ca652010-01-06 13:33:59 +0000275
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800276 set_mr(chan, mode);
Zhang Wei173acc72008-03-01 07:42:48 -0700277}
278
279/**
Ira Snyder738f5f72010-01-06 13:34:02 +0000280 * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
Ira Snydera1c03312010-01-06 13:34:05 +0000281 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700282 * @size : Address loop size, 0 for disable loop
283 *
284 * The set destination address hold transfer size. The destination
285 * address hold or loop transfer size is when the DMA transfer
286 * data to destination address (TA), if the loop size is 4, the DMA will
287 * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
288 * TA + 1 ... and so on.
289 */
Ira Snydera1c03312010-01-06 13:34:05 +0000290static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
Zhang Wei173acc72008-03-01 07:42:48 -0700291{
Ira Snyder272ca652010-01-06 13:33:59 +0000292 u32 mode;
293
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800294 mode = get_mr(chan);
Ira Snyder272ca652010-01-06 13:33:59 +0000295
Zhang Wei173acc72008-03-01 07:42:48 -0700296 switch (size) {
297 case 0:
Ira Snyder272ca652010-01-06 13:33:59 +0000298 mode &= ~FSL_DMA_MR_DAHE;
Zhang Wei173acc72008-03-01 07:42:48 -0700299 break;
300 case 1:
301 case 2:
302 case 4:
303 case 8:
Ira Snyder272ca652010-01-06 13:33:59 +0000304 mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
Zhang Wei173acc72008-03-01 07:42:48 -0700305 break;
306 }
Ira Snyder272ca652010-01-06 13:33:59 +0000307
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800308 set_mr(chan, mode);
Zhang Wei173acc72008-03-01 07:42:48 -0700309}
310
311/**
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700312 * fsl_chan_set_request_count - Set DMA Request Count for external control
Ira Snydera1c03312010-01-06 13:34:05 +0000313 * @chan : Freescale DMA channel
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700314 * @size : Number of bytes to transfer in a single request
315 *
316 * The Freescale DMA channel can be controlled by the external signal DREQ#.
317 * The DMA request count is how many bytes are allowed to transfer before
318 * pausing the channel, after which a new assertion of DREQ# resumes channel
319 * operation.
320 *
321 * A size of 0 disables external pause control. The maximum size is 1024.
322 */
Ira Snydera1c03312010-01-06 13:34:05 +0000323static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700324{
Ira Snyder272ca652010-01-06 13:33:59 +0000325 u32 mode;
326
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700327 BUG_ON(size > 1024);
Ira Snyder272ca652010-01-06 13:33:59 +0000328
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800329 mode = get_mr(chan);
Ira Snyder272ca652010-01-06 13:33:59 +0000330 mode |= (__ilog2(size) << 24) & 0x0f000000;
331
Hongbo Zhangccdce9a2014-04-18 16:17:45 +0800332 set_mr(chan, mode);
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700333}
334
335/**
Zhang Wei173acc72008-03-01 07:42:48 -0700336 * fsl_chan_toggle_ext_pause - Toggle channel external pause status
Ira Snydera1c03312010-01-06 13:34:05 +0000337 * @chan : Freescale DMA channel
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700338 * @enable : 0 is disabled, 1 is enabled.
Zhang Wei173acc72008-03-01 07:42:48 -0700339 *
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700340 * The Freescale DMA channel can be controlled by the external signal DREQ#.
341 * The DMA Request Count feature should be used in addition to this feature
342 * to set the number of bytes to transfer before pausing the channel.
Zhang Wei173acc72008-03-01 07:42:48 -0700343 */
Ira Snydera1c03312010-01-06 13:34:05 +0000344static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
Zhang Wei173acc72008-03-01 07:42:48 -0700345{
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700346 if (enable)
Ira Snydera1c03312010-01-06 13:34:05 +0000347 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700348 else
Ira Snydera1c03312010-01-06 13:34:05 +0000349 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700350}
351
352/**
353 * fsl_chan_toggle_ext_start - Toggle channel external start status
Ira Snydera1c03312010-01-06 13:34:05 +0000354 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700355 * @enable : 0 is disabled, 1 is enabled.
356 *
357 * If enable the external start, the channel can be started by an
358 * external DMA start pin. So the dma_start() does not start the
359 * transfer immediately. The DMA channel will wait for the
360 * control pin asserted.
361 */
Ira Snydera1c03312010-01-06 13:34:05 +0000362static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
Zhang Wei173acc72008-03-01 07:42:48 -0700363{
364 if (enable)
Ira Snydera1c03312010-01-06 13:34:05 +0000365 chan->feature |= FSL_DMA_CHAN_START_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700366 else
Ira Snydera1c03312010-01-06 13:34:05 +0000367 chan->feature &= ~FSL_DMA_CHAN_START_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700368}
369
Ira Snyder31f43062011-03-03 07:54:57 +0000370static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000371{
372 struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
373
374 if (list_empty(&chan->ld_pending))
375 goto out_splice;
376
377 /*
378 * Add the hardware descriptor to the chain of hardware descriptors
379 * that already exists in memory.
380 *
381 * This will un-set the EOL bit of the existing transaction, and the
382 * last link in this transaction will become the EOL descriptor.
383 */
384 set_desc_next(chan, &tail->hw, desc->async_tx.phys);
385
386 /*
387 * Add the software descriptor and all children to the list
388 * of pending transactions
389 */
390out_splice:
391 list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
392}
393
Zhang Wei173acc72008-03-01 07:42:48 -0700394static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
395{
Ira Snydera1c03312010-01-06 13:34:05 +0000396 struct fsldma_chan *chan = to_fsl_chan(tx->chan);
Dan Williamseda34232009-09-08 17:53:02 -0700397 struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
398 struct fsl_desc_sw *child;
Zhang Wei173acc72008-03-01 07:42:48 -0700399 unsigned long flags;
Dan Williamsbbc76562013-12-09 11:16:00 -0800400 dma_cookie_t cookie = -EINVAL;
Zhang Wei173acc72008-03-01 07:42:48 -0700401
Ira Snydera1c03312010-01-06 13:34:05 +0000402 spin_lock_irqsave(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700403
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000404 /*
405 * assign cookies to all of the software descriptors
406 * that make up this transaction
407 */
Dan Williamseda34232009-09-08 17:53:02 -0700408 list_for_each_entry(child, &desc->tx_list, node) {
Russell King - ARM Linux884485e2012-03-06 22:34:46 +0000409 cookie = dma_cookie_assign(&child->async_tx);
Ira Snyderbcfb7462009-05-15 14:27:16 -0700410 }
411
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000412 /* put this transaction onto the tail of the pending queue */
Ira Snydera1c03312010-01-06 13:34:05 +0000413 append_ld_queue(chan, desc);
Zhang Wei173acc72008-03-01 07:42:48 -0700414
Ira Snydera1c03312010-01-06 13:34:05 +0000415 spin_unlock_irqrestore(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700416
417 return cookie;
418}
419
420/**
Hongbo Zhang86d19a52014-04-18 16:17:47 +0800421 * fsl_dma_free_descriptor - Free descriptor from channel's DMA pool.
422 * @chan : Freescale DMA channel
423 * @desc: descriptor to be freed
424 */
425static void fsl_dma_free_descriptor(struct fsldma_chan *chan,
426 struct fsl_desc_sw *desc)
427{
428 list_del(&desc->node);
429 chan_dbg(chan, "LD %p free\n", desc);
430 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
431}
432
433/**
Zhang Wei173acc72008-03-01 07:42:48 -0700434 * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
Ira Snydera1c03312010-01-06 13:34:05 +0000435 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700436 *
437 * Return - The descriptor allocated. NULL for failed.
438 */
Ira Snyder31f43062011-03-03 07:54:57 +0000439static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700440{
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000441 struct fsl_desc_sw *desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700442 dma_addr_t pdesc;
Zhang Wei173acc72008-03-01 07:42:48 -0700443
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000444 desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
445 if (!desc) {
Ira Snyderb1584712011-03-03 07:54:55 +0000446 chan_dbg(chan, "out of memory for link descriptor\n");
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000447 return NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700448 }
449
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000450 memset(desc, 0, sizeof(*desc));
451 INIT_LIST_HEAD(&desc->tx_list);
452 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
453 desc->async_tx.tx_submit = fsl_dma_tx_submit;
454 desc->async_tx.phys = pdesc;
455
Ira Snyder0ab09c32011-03-03 07:54:56 +0000456 chan_dbg(chan, "LD %p allocated\n", desc);
Ira Snyder0ab09c32011-03-03 07:54:56 +0000457
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000458 return desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700459}
460
Zhang Wei173acc72008-03-01 07:42:48 -0700461/**
Hongbo Zhang2a5ecb72014-04-18 16:17:48 +0800462 * fsl_chan_xfer_ld_queue - transfer any pending transactions
463 * @chan : Freescale DMA channel
464 *
465 * HARDWARE STATE: idle
466 * LOCKING: must hold chan->desc_lock
467 */
468static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
469{
470 struct fsl_desc_sw *desc;
471
472 /*
473 * If the list of pending descriptors is empty, then we
474 * don't need to do any work at all
475 */
476 if (list_empty(&chan->ld_pending)) {
477 chan_dbg(chan, "no pending LDs\n");
478 return;
479 }
480
481 /*
482 * The DMA controller is not idle, which means that the interrupt
483 * handler will start any queued transactions when it runs after
484 * this transaction finishes
485 */
486 if (!chan->idle) {
487 chan_dbg(chan, "DMA controller still busy\n");
488 return;
489 }
490
491 /*
492 * If there are some link descriptors which have not been
493 * transferred, we need to start the controller
494 */
495
496 /*
497 * Move all elements from the queue of pending transactions
498 * onto the list of running transactions
499 */
500 chan_dbg(chan, "idle, starting controller\n");
501 desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
502 list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
503
504 /*
505 * The 85xx DMA controller doesn't clear the channel start bit
506 * automatically at the end of a transfer. Therefore we must clear
507 * it in software before starting the transfer.
508 */
509 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
510 u32 mode;
511
512 mode = get_mr(chan);
513 mode &= ~FSL_DMA_MR_CS;
514 set_mr(chan, mode);
515 }
516
517 /*
518 * Program the descriptor's address into the DMA controller,
519 * then start the DMA transaction
520 */
521 set_cdar(chan, desc->async_tx.phys);
522 get_cdar(chan);
523
524 dma_start(chan);
525 chan->idle = false;
526}
527
528/**
529 * fsldma_cleanup_descriptor - cleanup and free a single link descriptor
530 * @chan: Freescale DMA channel
531 * @desc: descriptor to cleanup and free
532 *
533 * This function is used on a descriptor which has been executed by the DMA
534 * controller. It will run any callbacks, submit any dependencies, and then
535 * free the descriptor.
536 */
537static void fsldma_cleanup_descriptor(struct fsldma_chan *chan,
538 struct fsl_desc_sw *desc)
539{
540 struct dma_async_tx_descriptor *txd = &desc->async_tx;
541
542 /* Run the link descriptor callback function */
543 if (txd->callback) {
544 chan_dbg(chan, "LD %p callback\n", desc);
545 txd->callback(txd->callback_param);
546 }
547
548 /* Run any dependencies */
549 dma_run_dependencies(txd);
550
551 dma_descriptor_unmap(txd);
552 chan_dbg(chan, "LD %p free\n", desc);
553 dma_pool_free(chan->desc_pool, desc, txd->phys);
554}
555
556/**
Zhang Wei173acc72008-03-01 07:42:48 -0700557 * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
Ira Snydera1c03312010-01-06 13:34:05 +0000558 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700559 *
560 * This function will create a dma pool for descriptor allocation.
561 *
562 * Return - The number of descriptors allocated.
563 */
Ira Snydera1c03312010-01-06 13:34:05 +0000564static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700565{
Ira Snydera1c03312010-01-06 13:34:05 +0000566 struct fsldma_chan *chan = to_fsl_chan(dchan);
Timur Tabi77cd62e2008-09-26 17:00:11 -0700567
568 /* Has this channel already been allocated? */
Ira Snydera1c03312010-01-06 13:34:05 +0000569 if (chan->desc_pool)
Timur Tabi77cd62e2008-09-26 17:00:11 -0700570 return 1;
Zhang Wei173acc72008-03-01 07:42:48 -0700571
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000572 /*
573 * We need the descriptor to be aligned to 32bytes
Zhang Wei173acc72008-03-01 07:42:48 -0700574 * for meeting FSL DMA specification requirement.
575 */
Ira Snyderb1584712011-03-03 07:54:55 +0000576 chan->desc_pool = dma_pool_create(chan->name, chan->dev,
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000577 sizeof(struct fsl_desc_sw),
578 __alignof__(struct fsl_desc_sw), 0);
Ira Snydera1c03312010-01-06 13:34:05 +0000579 if (!chan->desc_pool) {
Ira Snyderb1584712011-03-03 07:54:55 +0000580 chan_err(chan, "unable to allocate descriptor pool\n");
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000581 return -ENOMEM;
Zhang Wei173acc72008-03-01 07:42:48 -0700582 }
583
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000584 /* there is at least one descriptor free to be allocated */
Zhang Wei173acc72008-03-01 07:42:48 -0700585 return 1;
586}
587
588/**
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000589 * fsldma_free_desc_list - Free all descriptors in a queue
590 * @chan: Freescae DMA channel
591 * @list: the list to free
592 *
593 * LOCKING: must hold chan->desc_lock
594 */
595static void fsldma_free_desc_list(struct fsldma_chan *chan,
596 struct list_head *list)
597{
598 struct fsl_desc_sw *desc, *_desc;
599
Hongbo Zhang86d19a52014-04-18 16:17:47 +0800600 list_for_each_entry_safe(desc, _desc, list, node)
601 fsl_dma_free_descriptor(chan, desc);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000602}
603
604static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
605 struct list_head *list)
606{
607 struct fsl_desc_sw *desc, *_desc;
608
Hongbo Zhang86d19a52014-04-18 16:17:47 +0800609 list_for_each_entry_safe_reverse(desc, _desc, list, node)
610 fsl_dma_free_descriptor(chan, desc);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000611}
612
613/**
Zhang Wei173acc72008-03-01 07:42:48 -0700614 * fsl_dma_free_chan_resources - Free all resources of the channel.
Ira Snydera1c03312010-01-06 13:34:05 +0000615 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700616 */
Ira Snydera1c03312010-01-06 13:34:05 +0000617static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700618{
Ira Snydera1c03312010-01-06 13:34:05 +0000619 struct fsldma_chan *chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700620 unsigned long flags;
621
Ira Snyderb1584712011-03-03 07:54:55 +0000622 chan_dbg(chan, "free all channel resources\n");
Ira Snydera1c03312010-01-06 13:34:05 +0000623 spin_lock_irqsave(&chan->desc_lock, flags);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000624 fsldma_free_desc_list(chan, &chan->ld_pending);
625 fsldma_free_desc_list(chan, &chan->ld_running);
Ira Snydera1c03312010-01-06 13:34:05 +0000626 spin_unlock_irqrestore(&chan->desc_lock, flags);
Timur Tabi77cd62e2008-09-26 17:00:11 -0700627
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000628 dma_pool_destroy(chan->desc_pool);
Ira Snydera1c03312010-01-06 13:34:05 +0000629 chan->desc_pool = NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700630}
631
Zhang Wei2187c262008-03-13 17:45:28 -0700632static struct dma_async_tx_descriptor *
Ira Snyder31f43062011-03-03 07:54:57 +0000633fsl_dma_prep_memcpy(struct dma_chan *dchan,
634 dma_addr_t dma_dst, dma_addr_t dma_src,
Zhang Wei173acc72008-03-01 07:42:48 -0700635 size_t len, unsigned long flags)
636{
Ira Snydera1c03312010-01-06 13:34:05 +0000637 struct fsldma_chan *chan;
Zhang Wei173acc72008-03-01 07:42:48 -0700638 struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
639 size_t copy;
Zhang Wei173acc72008-03-01 07:42:48 -0700640
Ira Snydera1c03312010-01-06 13:34:05 +0000641 if (!dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700642 return NULL;
643
644 if (!len)
645 return NULL;
646
Ira Snydera1c03312010-01-06 13:34:05 +0000647 chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700648
649 do {
650
651 /* Allocate the link descriptor from DMA pool */
Ira Snydera1c03312010-01-06 13:34:05 +0000652 new = fsl_dma_alloc_descriptor(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700653 if (!new) {
Ira Snyderb1584712011-03-03 07:54:55 +0000654 chan_err(chan, "%s\n", msg_ld_oom);
Ira Snyder2e077f82009-05-15 09:59:46 -0700655 goto fail;
Zhang Wei173acc72008-03-01 07:42:48 -0700656 }
Zhang Wei173acc72008-03-01 07:42:48 -0700657
Zhang Wei56822842008-03-13 10:45:27 -0700658 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
Zhang Wei173acc72008-03-01 07:42:48 -0700659
Ira Snydera1c03312010-01-06 13:34:05 +0000660 set_desc_cnt(chan, &new->hw, copy);
661 set_desc_src(chan, &new->hw, dma_src);
662 set_desc_dst(chan, &new->hw, dma_dst);
Zhang Wei173acc72008-03-01 07:42:48 -0700663
664 if (!first)
665 first = new;
666 else
Ira Snydera1c03312010-01-06 13:34:05 +0000667 set_desc_next(chan, &prev->hw, new->async_tx.phys);
Zhang Wei173acc72008-03-01 07:42:48 -0700668
669 new->async_tx.cookie = 0;
Dan Williams636bdea2008-04-17 20:17:26 -0700670 async_tx_ack(&new->async_tx);
Zhang Wei173acc72008-03-01 07:42:48 -0700671
672 prev = new;
673 len -= copy;
674 dma_src += copy;
Ira Snyder738f5f72010-01-06 13:34:02 +0000675 dma_dst += copy;
Zhang Wei173acc72008-03-01 07:42:48 -0700676
677 /* Insert the link descriptor to the LD ring */
Dan Williamseda34232009-09-08 17:53:02 -0700678 list_add_tail(&new->node, &first->tx_list);
Zhang Wei173acc72008-03-01 07:42:48 -0700679 } while (len);
680
Dan Williams636bdea2008-04-17 20:17:26 -0700681 new->async_tx.flags = flags; /* client is in control of this ack */
Zhang Wei173acc72008-03-01 07:42:48 -0700682 new->async_tx.cookie = -EBUSY;
683
Ira Snyder31f43062011-03-03 07:54:57 +0000684 /* Set End-of-link to the last link descriptor of new list */
Ira Snydera1c03312010-01-06 13:34:05 +0000685 set_ld_eol(chan, new);
Zhang Wei173acc72008-03-01 07:42:48 -0700686
Ira Snyder2e077f82009-05-15 09:59:46 -0700687 return &first->async_tx;
688
689fail:
690 if (!first)
691 return NULL;
692
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000693 fsldma_free_desc_list_reverse(chan, &first->tx_list);
Ira Snyder2e077f82009-05-15 09:59:46 -0700694 return NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700695}
696
Ira Snyderc14330412010-09-30 11:46:45 +0000697static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan,
698 struct scatterlist *dst_sg, unsigned int dst_nents,
699 struct scatterlist *src_sg, unsigned int src_nents,
700 unsigned long flags)
701{
702 struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
703 struct fsldma_chan *chan = to_fsl_chan(dchan);
704 size_t dst_avail, src_avail;
705 dma_addr_t dst, src;
706 size_t len;
707
708 /* basic sanity checks */
709 if (dst_nents == 0 || src_nents == 0)
710 return NULL;
711
712 if (dst_sg == NULL || src_sg == NULL)
713 return NULL;
714
715 /*
716 * TODO: should we check that both scatterlists have the same
717 * TODO: number of bytes in total? Is that really an error?
718 */
719
720 /* get prepared for the loop */
721 dst_avail = sg_dma_len(dst_sg);
722 src_avail = sg_dma_len(src_sg);
723
724 /* run until we are out of scatterlist entries */
725 while (true) {
726
727 /* create the largest transaction possible */
728 len = min_t(size_t, src_avail, dst_avail);
729 len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT);
730 if (len == 0)
731 goto fetch;
732
733 dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail;
734 src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail;
735
736 /* allocate and populate the descriptor */
737 new = fsl_dma_alloc_descriptor(chan);
738 if (!new) {
Ira Snyderb1584712011-03-03 07:54:55 +0000739 chan_err(chan, "%s\n", msg_ld_oom);
Ira Snyderc14330412010-09-30 11:46:45 +0000740 goto fail;
741 }
Ira Snyderc14330412010-09-30 11:46:45 +0000742
743 set_desc_cnt(chan, &new->hw, len);
744 set_desc_src(chan, &new->hw, src);
745 set_desc_dst(chan, &new->hw, dst);
746
747 if (!first)
748 first = new;
749 else
750 set_desc_next(chan, &prev->hw, new->async_tx.phys);
751
752 new->async_tx.cookie = 0;
753 async_tx_ack(&new->async_tx);
754 prev = new;
755
756 /* Insert the link descriptor to the LD ring */
757 list_add_tail(&new->node, &first->tx_list);
758
759 /* update metadata */
760 dst_avail -= len;
761 src_avail -= len;
762
763fetch:
764 /* fetch the next dst scatterlist entry */
765 if (dst_avail == 0) {
766
767 /* no more entries: we're done */
768 if (dst_nents == 0)
769 break;
770
771 /* fetch the next entry: if there are no more: done */
772 dst_sg = sg_next(dst_sg);
773 if (dst_sg == NULL)
774 break;
775
776 dst_nents--;
777 dst_avail = sg_dma_len(dst_sg);
778 }
779
780 /* fetch the next src scatterlist entry */
781 if (src_avail == 0) {
782
783 /* no more entries: we're done */
784 if (src_nents == 0)
785 break;
786
787 /* fetch the next entry: if there are no more: done */
788 src_sg = sg_next(src_sg);
789 if (src_sg == NULL)
790 break;
791
792 src_nents--;
793 src_avail = sg_dma_len(src_sg);
794 }
795 }
796
797 new->async_tx.flags = flags; /* client is in control of this ack */
798 new->async_tx.cookie = -EBUSY;
799
800 /* Set End-of-link to the last link descriptor of new list */
801 set_ld_eol(chan, new);
802
803 return &first->async_tx;
804
805fail:
806 if (!first)
807 return NULL;
808
809 fsldma_free_desc_list_reverse(chan, &first->tx_list);
810 return NULL;
811}
812
Zhang Wei173acc72008-03-01 07:42:48 -0700813/**
Ira Snyderbbea0b62009-09-08 17:53:04 -0700814 * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
815 * @chan: DMA channel
816 * @sgl: scatterlist to transfer to/from
817 * @sg_len: number of entries in @scatterlist
818 * @direction: DMA direction
819 * @flags: DMAEngine flags
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500820 * @context: transaction context (ignored)
Ira Snyderbbea0b62009-09-08 17:53:04 -0700821 *
822 * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the
823 * DMA_SLAVE API, this gets the device-specific information from the
824 * chan->private variable.
825 */
826static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
Ira Snydera1c03312010-01-06 13:34:05 +0000827 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
Alexandre Bounine185ecb52012-03-08 15:35:13 -0500828 enum dma_transfer_direction direction, unsigned long flags,
829 void *context)
Ira Snyderbbea0b62009-09-08 17:53:04 -0700830{
Ira Snyderbbea0b62009-09-08 17:53:04 -0700831 /*
Ira Snyder968f19a2010-09-30 11:46:46 +0000832 * This operation is not supported on the Freescale DMA controller
Ira Snyderbbea0b62009-09-08 17:53:04 -0700833 *
Ira Snyder968f19a2010-09-30 11:46:46 +0000834 * However, we need to provide the function pointer to allow the
835 * device_control() method to work.
Ira Snyderbbea0b62009-09-08 17:53:04 -0700836 */
Ira Snyderbbea0b62009-09-08 17:53:04 -0700837 return NULL;
838}
839
Linus Walleijc3635c72010-03-26 16:44:01 -0700840static int fsl_dma_device_control(struct dma_chan *dchan,
Linus Walleij05827632010-05-17 16:30:42 -0700841 enum dma_ctrl_cmd cmd, unsigned long arg)
Ira Snyderbbea0b62009-09-08 17:53:04 -0700842{
Ira Snyder968f19a2010-09-30 11:46:46 +0000843 struct dma_slave_config *config;
Ira Snydera1c03312010-01-06 13:34:05 +0000844 struct fsldma_chan *chan;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700845 unsigned long flags;
Ira Snyder968f19a2010-09-30 11:46:46 +0000846 int size;
Linus Walleijc3635c72010-03-26 16:44:01 -0700847
Ira Snydera1c03312010-01-06 13:34:05 +0000848 if (!dchan)
Linus Walleijc3635c72010-03-26 16:44:01 -0700849 return -EINVAL;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700850
Ira Snydera1c03312010-01-06 13:34:05 +0000851 chan = to_fsl_chan(dchan);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700852
Ira Snyder968f19a2010-09-30 11:46:46 +0000853 switch (cmd) {
854 case DMA_TERMINATE_ALL:
Ira Snyderf04cd402011-03-03 07:54:58 +0000855 spin_lock_irqsave(&chan->desc_lock, flags);
856
Ira Snyder968f19a2010-09-30 11:46:46 +0000857 /* Halt the DMA engine */
858 dma_halt(chan);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700859
Ira Snyder968f19a2010-09-30 11:46:46 +0000860 /* Remove and free all of the descriptors in the LD queue */
861 fsldma_free_desc_list(chan, &chan->ld_pending);
862 fsldma_free_desc_list(chan, &chan->ld_running);
Ira Snyderf04cd402011-03-03 07:54:58 +0000863 chan->idle = true;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700864
Ira Snyder968f19a2010-09-30 11:46:46 +0000865 spin_unlock_irqrestore(&chan->desc_lock, flags);
866 return 0;
867
868 case DMA_SLAVE_CONFIG:
869 config = (struct dma_slave_config *)arg;
870
871 /* make sure the channel supports setting burst size */
872 if (!chan->set_request_count)
873 return -ENXIO;
874
875 /* we set the controller burst size depending on direction */
Vinod Kouldb8196d2011-10-13 22:34:23 +0530876 if (config->direction == DMA_MEM_TO_DEV)
Ira Snyder968f19a2010-09-30 11:46:46 +0000877 size = config->dst_addr_width * config->dst_maxburst;
878 else
879 size = config->src_addr_width * config->src_maxburst;
880
881 chan->set_request_count(chan, size);
882 return 0;
883
884 case FSLDMA_EXTERNAL_START:
885
886 /* make sure the channel supports external start */
887 if (!chan->toggle_ext_start)
888 return -ENXIO;
889
890 chan->toggle_ext_start(chan, arg);
891 return 0;
892
893 default:
894 return -ENXIO;
895 }
Linus Walleijc3635c72010-03-26 16:44:01 -0700896
897 return 0;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700898}
899
900/**
Zhang Wei173acc72008-03-01 07:42:48 -0700901 * fsl_dma_memcpy_issue_pending - Issue the DMA start command
Ira Snydera1c03312010-01-06 13:34:05 +0000902 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700903 */
Ira Snydera1c03312010-01-06 13:34:05 +0000904static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700905{
Ira Snydera1c03312010-01-06 13:34:05 +0000906 struct fsldma_chan *chan = to_fsl_chan(dchan);
Ira Snyderdc8d4092011-03-03 07:55:00 +0000907 unsigned long flags;
908
909 spin_lock_irqsave(&chan->desc_lock, flags);
Ira Snydera1c03312010-01-06 13:34:05 +0000910 fsl_chan_xfer_ld_queue(chan);
Ira Snyderdc8d4092011-03-03 07:55:00 +0000911 spin_unlock_irqrestore(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700912}
913
Zhang Wei173acc72008-03-01 07:42:48 -0700914/**
Linus Walleij07934482010-03-26 16:50:49 -0700915 * fsl_tx_status - Determine the DMA status
Ira Snydera1c03312010-01-06 13:34:05 +0000916 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700917 */
Linus Walleij07934482010-03-26 16:50:49 -0700918static enum dma_status fsl_tx_status(struct dma_chan *dchan,
Zhang Wei173acc72008-03-01 07:42:48 -0700919 dma_cookie_t cookie,
Linus Walleij07934482010-03-26 16:50:49 -0700920 struct dma_tx_state *txstate)
Zhang Wei173acc72008-03-01 07:42:48 -0700921{
Andy Shevchenko9b0b0bd2013-05-27 15:14:35 +0300922 return dma_cookie_status(dchan, cookie, txstate);
Zhang Wei173acc72008-03-01 07:42:48 -0700923}
924
Ira Snyderd3f620b2010-01-06 13:34:04 +0000925/*----------------------------------------------------------------------------*/
926/* Interrupt Handling */
927/*----------------------------------------------------------------------------*/
928
Ira Snydere7a29152010-01-06 13:34:03 +0000929static irqreturn_t fsldma_chan_irq(int irq, void *data)
Zhang Wei173acc72008-03-01 07:42:48 -0700930{
Ira Snydera1c03312010-01-06 13:34:05 +0000931 struct fsldma_chan *chan = data;
Ira Snydera1c03312010-01-06 13:34:05 +0000932 u32 stat;
Zhang Wei173acc72008-03-01 07:42:48 -0700933
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000934 /* save and clear the status register */
Ira Snydera1c03312010-01-06 13:34:05 +0000935 stat = get_sr(chan);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000936 set_sr(chan, stat);
Ira Snyderb1584712011-03-03 07:54:55 +0000937 chan_dbg(chan, "irq: stat = 0x%x\n", stat);
Zhang Wei173acc72008-03-01 07:42:48 -0700938
Ira Snyderf04cd402011-03-03 07:54:58 +0000939 /* check that this was really our device */
Zhang Wei173acc72008-03-01 07:42:48 -0700940 stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
941 if (!stat)
942 return IRQ_NONE;
943
944 if (stat & FSL_DMA_SR_TE)
Ira Snyderb1584712011-03-03 07:54:55 +0000945 chan_err(chan, "Transfer Error!\n");
Zhang Wei173acc72008-03-01 07:42:48 -0700946
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000947 /*
948 * Programming Error
Zhang Weif79abb62008-03-18 18:45:00 -0700949 * The DMA_INTERRUPT async_tx is a NULL transfer, which will
Masanari Iidad73111c2012-08-04 23:37:53 +0900950 * trigger a PE interrupt.
Zhang Weif79abb62008-03-18 18:45:00 -0700951 */
952 if (stat & FSL_DMA_SR_PE) {
Ira Snyderb1584712011-03-03 07:54:55 +0000953 chan_dbg(chan, "irq: Programming Error INT\n");
Zhang Weif79abb62008-03-18 18:45:00 -0700954 stat &= ~FSL_DMA_SR_PE;
Ira Snyderf04cd402011-03-03 07:54:58 +0000955 if (get_bcr(chan) != 0)
956 chan_err(chan, "Programming Error!\n");
Zhang Wei1c629792008-04-17 20:17:25 -0700957 }
958
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000959 /*
960 * For MPC8349, EOCDI event need to update cookie
Zhang Wei1c629792008-04-17 20:17:25 -0700961 * and start the next transfer if it exist.
962 */
963 if (stat & FSL_DMA_SR_EOCDI) {
Ira Snyderb1584712011-03-03 07:54:55 +0000964 chan_dbg(chan, "irq: End-of-Chain link INT\n");
Zhang Wei1c629792008-04-17 20:17:25 -0700965 stat &= ~FSL_DMA_SR_EOCDI;
Zhang Wei173acc72008-03-01 07:42:48 -0700966 }
967
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000968 /*
969 * If it current transfer is the end-of-transfer,
Zhang Wei173acc72008-03-01 07:42:48 -0700970 * we should clear the Channel Start bit for
971 * prepare next transfer.
972 */
Zhang Wei1c629792008-04-17 20:17:25 -0700973 if (stat & FSL_DMA_SR_EOLNI) {
Ira Snyderb1584712011-03-03 07:54:55 +0000974 chan_dbg(chan, "irq: End-of-link INT\n");
Zhang Wei173acc72008-03-01 07:42:48 -0700975 stat &= ~FSL_DMA_SR_EOLNI;
Zhang Wei173acc72008-03-01 07:42:48 -0700976 }
977
Ira Snyderf04cd402011-03-03 07:54:58 +0000978 /* check that the DMA controller is really idle */
979 if (!dma_is_idle(chan))
980 chan_err(chan, "irq: controller not idle!\n");
Zhang Wei173acc72008-03-01 07:42:48 -0700981
Ira Snyderf04cd402011-03-03 07:54:58 +0000982 /* check that we handled all of the bits */
983 if (stat)
984 chan_err(chan, "irq: unhandled sr 0x%08x\n", stat);
985
986 /*
987 * Schedule the tasklet to handle all cleanup of the current
988 * transaction. It will start a new transaction if there is
989 * one pending.
990 */
Ira Snydera1c03312010-01-06 13:34:05 +0000991 tasklet_schedule(&chan->tasklet);
Ira Snyderf04cd402011-03-03 07:54:58 +0000992 chan_dbg(chan, "irq: Exit\n");
Zhang Wei173acc72008-03-01 07:42:48 -0700993 return IRQ_HANDLED;
994}
995
Zhang Wei173acc72008-03-01 07:42:48 -0700996static void dma_do_tasklet(unsigned long data)
997{
Ira Snydera1c03312010-01-06 13:34:05 +0000998 struct fsldma_chan *chan = (struct fsldma_chan *)data;
Ira Snyderdc8d4092011-03-03 07:55:00 +0000999 struct fsl_desc_sw *desc, *_desc;
1000 LIST_HEAD(ld_cleanup);
Ira Snyderf04cd402011-03-03 07:54:58 +00001001 unsigned long flags;
1002
1003 chan_dbg(chan, "tasklet entry\n");
1004
Ira Snyderf04cd402011-03-03 07:54:58 +00001005 spin_lock_irqsave(&chan->desc_lock, flags);
Ira Snyderdc8d4092011-03-03 07:55:00 +00001006
1007 /* update the cookie if we have some descriptors to cleanup */
1008 if (!list_empty(&chan->ld_running)) {
1009 dma_cookie_t cookie;
1010
1011 desc = to_fsl_desc(chan->ld_running.prev);
1012 cookie = desc->async_tx.cookie;
Russell King - ARM Linuxf7fbce02012-03-06 22:35:07 +00001013 dma_cookie_complete(&desc->async_tx);
Ira Snyderdc8d4092011-03-03 07:55:00 +00001014
Ira Snyderdc8d4092011-03-03 07:55:00 +00001015 chan_dbg(chan, "completed_cookie=%d\n", cookie);
1016 }
1017
1018 /*
1019 * move the descriptors to a temporary list so we can drop the lock
1020 * during the entire cleanup operation
1021 */
1022 list_splice_tail_init(&chan->ld_running, &ld_cleanup);
1023
1024 /* the hardware is now idle and ready for more */
Ira Snyderf04cd402011-03-03 07:54:58 +00001025 chan->idle = true;
Ira Snyderdc8d4092011-03-03 07:55:00 +00001026
1027 /*
1028 * Start any pending transactions automatically
1029 *
1030 * In the ideal case, we keep the DMA controller busy while we go
1031 * ahead and free the descriptors below.
1032 */
1033 fsl_chan_xfer_ld_queue(chan);
Ira Snyderf04cd402011-03-03 07:54:58 +00001034 spin_unlock_irqrestore(&chan->desc_lock, flags);
1035
Ira Snyderdc8d4092011-03-03 07:55:00 +00001036 /* Run the callback for each descriptor, in order */
1037 list_for_each_entry_safe(desc, _desc, &ld_cleanup, node) {
1038
1039 /* Remove from the list of transactions */
1040 list_del(&desc->node);
1041
1042 /* Run all cleanup for this descriptor */
1043 fsldma_cleanup_descriptor(chan, desc);
1044 }
1045
Ira Snyderf04cd402011-03-03 07:54:58 +00001046 chan_dbg(chan, "tasklet exit\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001047}
1048
Ira Snyderd3f620b2010-01-06 13:34:04 +00001049static irqreturn_t fsldma_ctrl_irq(int irq, void *data)
1050{
1051 struct fsldma_device *fdev = data;
1052 struct fsldma_chan *chan;
1053 unsigned int handled = 0;
1054 u32 gsr, mask;
1055 int i;
1056
1057 gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs)
1058 : in_le32(fdev->regs);
1059 mask = 0xff000000;
1060 dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr);
1061
1062 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1063 chan = fdev->chan[i];
1064 if (!chan)
1065 continue;
1066
1067 if (gsr & mask) {
1068 dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
1069 fsldma_chan_irq(irq, chan);
1070 handled++;
1071 }
1072
1073 gsr &= ~mask;
1074 mask >>= 8;
1075 }
1076
1077 return IRQ_RETVAL(handled);
1078}
1079
1080static void fsldma_free_irqs(struct fsldma_device *fdev)
1081{
1082 struct fsldma_chan *chan;
1083 int i;
1084
1085 if (fdev->irq != NO_IRQ) {
1086 dev_dbg(fdev->dev, "free per-controller IRQ\n");
1087 free_irq(fdev->irq, fdev);
1088 return;
1089 }
1090
1091 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1092 chan = fdev->chan[i];
1093 if (chan && chan->irq != NO_IRQ) {
Ira Snyderb1584712011-03-03 07:54:55 +00001094 chan_dbg(chan, "free per-channel IRQ\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001095 free_irq(chan->irq, chan);
1096 }
1097 }
1098}
1099
1100static int fsldma_request_irqs(struct fsldma_device *fdev)
1101{
1102 struct fsldma_chan *chan;
1103 int ret;
1104 int i;
1105
1106 /* if we have a per-controller IRQ, use that */
1107 if (fdev->irq != NO_IRQ) {
1108 dev_dbg(fdev->dev, "request per-controller IRQ\n");
1109 ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED,
1110 "fsldma-controller", fdev);
1111 return ret;
1112 }
1113
1114 /* no per-controller IRQ, use the per-channel IRQs */
1115 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1116 chan = fdev->chan[i];
1117 if (!chan)
1118 continue;
1119
1120 if (chan->irq == NO_IRQ) {
Ira Snyderb1584712011-03-03 07:54:55 +00001121 chan_err(chan, "interrupts property missing in device tree\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001122 ret = -ENODEV;
1123 goto out_unwind;
1124 }
1125
Ira Snyderb1584712011-03-03 07:54:55 +00001126 chan_dbg(chan, "request per-channel IRQ\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001127 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
1128 "fsldma-chan", chan);
1129 if (ret) {
Ira Snyderb1584712011-03-03 07:54:55 +00001130 chan_err(chan, "unable to request per-channel IRQ\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001131 goto out_unwind;
1132 }
1133 }
1134
1135 return 0;
1136
1137out_unwind:
1138 for (/* none */; i >= 0; i--) {
1139 chan = fdev->chan[i];
1140 if (!chan)
1141 continue;
1142
1143 if (chan->irq == NO_IRQ)
1144 continue;
1145
1146 free_irq(chan->irq, chan);
1147 }
1148
1149 return ret;
1150}
1151
Ira Snydera4f56d42010-01-06 13:34:01 +00001152/*----------------------------------------------------------------------------*/
1153/* OpenFirmware Subsystem */
1154/*----------------------------------------------------------------------------*/
1155
Bill Pemberton463a1f82012-11-19 13:22:55 -05001156static int fsl_dma_chan_probe(struct fsldma_device *fdev,
Timur Tabi77cd62e2008-09-26 17:00:11 -07001157 struct device_node *node, u32 feature, const char *compatible)
Zhang Wei173acc72008-03-01 07:42:48 -07001158{
Ira Snydera1c03312010-01-06 13:34:05 +00001159 struct fsldma_chan *chan;
Ira Snyder4ce0e952010-01-06 13:34:00 +00001160 struct resource res;
Zhang Wei173acc72008-03-01 07:42:48 -07001161 int err;
1162
Zhang Wei173acc72008-03-01 07:42:48 -07001163 /* alloc channel */
Ira Snydera1c03312010-01-06 13:34:05 +00001164 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1165 if (!chan) {
Ira Snydere7a29152010-01-06 13:34:03 +00001166 dev_err(fdev->dev, "no free memory for DMA channels!\n");
1167 err = -ENOMEM;
1168 goto out_return;
Zhang Wei173acc72008-03-01 07:42:48 -07001169 }
1170
Ira Snydere7a29152010-01-06 13:34:03 +00001171 /* ioremap registers for use */
Ira Snydera1c03312010-01-06 13:34:05 +00001172 chan->regs = of_iomap(node, 0);
1173 if (!chan->regs) {
Ira Snydere7a29152010-01-06 13:34:03 +00001174 dev_err(fdev->dev, "unable to ioremap registers\n");
1175 err = -ENOMEM;
Ira Snydera1c03312010-01-06 13:34:05 +00001176 goto out_free_chan;
Ira Snydere7a29152010-01-06 13:34:03 +00001177 }
1178
Ira Snyder4ce0e952010-01-06 13:34:00 +00001179 err = of_address_to_resource(node, 0, &res);
Zhang Wei173acc72008-03-01 07:42:48 -07001180 if (err) {
Ira Snydere7a29152010-01-06 13:34:03 +00001181 dev_err(fdev->dev, "unable to find 'reg' property\n");
1182 goto out_iounmap_regs;
Zhang Wei173acc72008-03-01 07:42:48 -07001183 }
1184
Ira Snydera1c03312010-01-06 13:34:05 +00001185 chan->feature = feature;
Zhang Wei173acc72008-03-01 07:42:48 -07001186 if (!fdev->feature)
Ira Snydera1c03312010-01-06 13:34:05 +00001187 fdev->feature = chan->feature;
Zhang Wei173acc72008-03-01 07:42:48 -07001188
Ira Snydere7a29152010-01-06 13:34:03 +00001189 /*
1190 * If the DMA device's feature is different than the feature
1191 * of its channels, report the bug
Zhang Wei173acc72008-03-01 07:42:48 -07001192 */
Ira Snydera1c03312010-01-06 13:34:05 +00001193 WARN_ON(fdev->feature != chan->feature);
Zhang Wei173acc72008-03-01 07:42:48 -07001194
Ira Snydera1c03312010-01-06 13:34:05 +00001195 chan->dev = fdev->dev;
Hongbo Zhang8de7a7d2013-09-26 17:33:43 +08001196 chan->id = (res.start & 0xfff) < 0x300 ?
1197 ((res.start - 0x100) & 0xfff) >> 7 :
1198 ((res.start - 0x200) & 0xfff) >> 7;
Ira Snydera1c03312010-01-06 13:34:05 +00001199 if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
Ira Snydere7a29152010-01-06 13:34:03 +00001200 dev_err(fdev->dev, "too many channels for device\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001201 err = -EINVAL;
Ira Snydere7a29152010-01-06 13:34:03 +00001202 goto out_iounmap_regs;
Zhang Wei173acc72008-03-01 07:42:48 -07001203 }
Zhang Wei173acc72008-03-01 07:42:48 -07001204
Ira Snydera1c03312010-01-06 13:34:05 +00001205 fdev->chan[chan->id] = chan;
1206 tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
Ira Snyderb1584712011-03-03 07:54:55 +00001207 snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id);
Ira Snydere7a29152010-01-06 13:34:03 +00001208
1209 /* Initialize the channel */
Ira Snydera1c03312010-01-06 13:34:05 +00001210 dma_init(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001211
1212 /* Clear cdar registers */
Ira Snydera1c03312010-01-06 13:34:05 +00001213 set_cdar(chan, 0);
Zhang Wei173acc72008-03-01 07:42:48 -07001214
Ira Snydera1c03312010-01-06 13:34:05 +00001215 switch (chan->feature & FSL_DMA_IP_MASK) {
Zhang Wei173acc72008-03-01 07:42:48 -07001216 case FSL_DMA_IP_85XX:
Ira Snydera1c03312010-01-06 13:34:05 +00001217 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
Zhang Wei173acc72008-03-01 07:42:48 -07001218 case FSL_DMA_IP_83XX:
Ira Snydera1c03312010-01-06 13:34:05 +00001219 chan->toggle_ext_start = fsl_chan_toggle_ext_start;
1220 chan->set_src_loop_size = fsl_chan_set_src_loop_size;
1221 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
1222 chan->set_request_count = fsl_chan_set_request_count;
Zhang Wei173acc72008-03-01 07:42:48 -07001223 }
1224
Ira Snydera1c03312010-01-06 13:34:05 +00001225 spin_lock_init(&chan->desc_lock);
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001226 INIT_LIST_HEAD(&chan->ld_pending);
1227 INIT_LIST_HEAD(&chan->ld_running);
Ira Snyderf04cd402011-03-03 07:54:58 +00001228 chan->idle = true;
Zhang Wei173acc72008-03-01 07:42:48 -07001229
Ira Snydera1c03312010-01-06 13:34:05 +00001230 chan->common.device = &fdev->common;
Russell King - ARM Linux8ac69542012-03-06 22:36:27 +00001231 dma_cookie_init(&chan->common);
Zhang Wei173acc72008-03-01 07:42:48 -07001232
Ira Snyderd3f620b2010-01-06 13:34:04 +00001233 /* find the IRQ line, if it exists in the device tree */
Ira Snydera1c03312010-01-06 13:34:05 +00001234 chan->irq = irq_of_parse_and_map(node, 0);
Ira Snyderd3f620b2010-01-06 13:34:04 +00001235
Zhang Wei173acc72008-03-01 07:42:48 -07001236 /* Add the channel to DMA device channel list */
Ira Snydera1c03312010-01-06 13:34:05 +00001237 list_add_tail(&chan->common.device_node, &fdev->common.channels);
Zhang Wei173acc72008-03-01 07:42:48 -07001238 fdev->common.chancnt++;
1239
Ira Snydera1c03312010-01-06 13:34:05 +00001240 dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
1241 chan->irq != NO_IRQ ? chan->irq : fdev->irq);
Zhang Wei173acc72008-03-01 07:42:48 -07001242
1243 return 0;
Li Yang51ee87f2008-05-29 23:25:45 -07001244
Ira Snydere7a29152010-01-06 13:34:03 +00001245out_iounmap_regs:
Ira Snydera1c03312010-01-06 13:34:05 +00001246 iounmap(chan->regs);
1247out_free_chan:
1248 kfree(chan);
Ira Snydere7a29152010-01-06 13:34:03 +00001249out_return:
Zhang Wei173acc72008-03-01 07:42:48 -07001250 return err;
1251}
1252
Ira Snydera1c03312010-01-06 13:34:05 +00001253static void fsl_dma_chan_remove(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -07001254{
Ira Snydera1c03312010-01-06 13:34:05 +00001255 irq_dispose_mapping(chan->irq);
1256 list_del(&chan->common.device_node);
1257 iounmap(chan->regs);
1258 kfree(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001259}
1260
Bill Pemberton463a1f82012-11-19 13:22:55 -05001261static int fsldma_of_probe(struct platform_device *op)
Zhang Wei173acc72008-03-01 07:42:48 -07001262{
Ira Snydera4f56d42010-01-06 13:34:01 +00001263 struct fsldma_device *fdev;
Timur Tabi77cd62e2008-09-26 17:00:11 -07001264 struct device_node *child;
Ira Snydere7a29152010-01-06 13:34:03 +00001265 int err;
Zhang Wei173acc72008-03-01 07:42:48 -07001266
Ira Snydera4f56d42010-01-06 13:34:01 +00001267 fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
Zhang Wei173acc72008-03-01 07:42:48 -07001268 if (!fdev) {
Ira Snydere7a29152010-01-06 13:34:03 +00001269 dev_err(&op->dev, "No enough memory for 'priv'\n");
1270 err = -ENOMEM;
1271 goto out_return;
Zhang Wei173acc72008-03-01 07:42:48 -07001272 }
Ira Snydere7a29152010-01-06 13:34:03 +00001273
1274 fdev->dev = &op->dev;
Zhang Wei173acc72008-03-01 07:42:48 -07001275 INIT_LIST_HEAD(&fdev->common.channels);
1276
Ira Snydere7a29152010-01-06 13:34:03 +00001277 /* ioremap the registers for use */
Grant Likely61c7a082010-04-13 16:12:29 -07001278 fdev->regs = of_iomap(op->dev.of_node, 0);
Ira Snydere7a29152010-01-06 13:34:03 +00001279 if (!fdev->regs) {
1280 dev_err(&op->dev, "unable to ioremap registers\n");
1281 err = -ENOMEM;
1282 goto out_free_fdev;
Zhang Wei173acc72008-03-01 07:42:48 -07001283 }
1284
Ira Snyderd3f620b2010-01-06 13:34:04 +00001285 /* map the channel IRQ if it exists, but don't hookup the handler yet */
Grant Likely61c7a082010-04-13 16:12:29 -07001286 fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0);
Ira Snyderd3f620b2010-01-06 13:34:04 +00001287
Zhang Wei173acc72008-03-01 07:42:48 -07001288 dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
Ira Snyderc14330412010-09-30 11:46:45 +00001289 dma_cap_set(DMA_SG, fdev->common.cap_mask);
Ira Snyderbbea0b62009-09-08 17:53:04 -07001290 dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
Zhang Wei173acc72008-03-01 07:42:48 -07001291 fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
1292 fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
Zhang Wei173acc72008-03-01 07:42:48 -07001293 fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
Ira Snyderc14330412010-09-30 11:46:45 +00001294 fdev->common.device_prep_dma_sg = fsl_dma_prep_sg;
Linus Walleij07934482010-03-26 16:50:49 -07001295 fdev->common.device_tx_status = fsl_tx_status;
Zhang Wei173acc72008-03-01 07:42:48 -07001296 fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
Ira Snyderbbea0b62009-09-08 17:53:04 -07001297 fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg;
Linus Walleijc3635c72010-03-26 16:44:01 -07001298 fdev->common.device_control = fsl_dma_device_control;
Ira Snydere7a29152010-01-06 13:34:03 +00001299 fdev->common.dev = &op->dev;
Zhang Wei173acc72008-03-01 07:42:48 -07001300
Li Yange2c8e4252010-11-11 20:16:29 +08001301 dma_set_mask(&(op->dev), DMA_BIT_MASK(36));
1302
Jingoo Handd3daca2013-05-24 10:10:13 +09001303 platform_set_drvdata(op, fdev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001304
Ira Snydere7a29152010-01-06 13:34:03 +00001305 /*
1306 * We cannot use of_platform_bus_probe() because there is no
1307 * of_platform_bus_remove(). Instead, we manually instantiate every DMA
Timur Tabi77cd62e2008-09-26 17:00:11 -07001308 * channel object.
1309 */
Grant Likely61c7a082010-04-13 16:12:29 -07001310 for_each_child_of_node(op->dev.of_node, child) {
Ira Snydere7a29152010-01-06 13:34:03 +00001311 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001312 fsl_dma_chan_probe(fdev, child,
1313 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
1314 "fsl,eloplus-dma-channel");
Ira Snydere7a29152010-01-06 13:34:03 +00001315 }
1316
1317 if (of_device_is_compatible(child, "fsl,elo-dma-channel")) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001318 fsl_dma_chan_probe(fdev, child,
1319 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
1320 "fsl,elo-dma-channel");
Ira Snydere7a29152010-01-06 13:34:03 +00001321 }
Timur Tabi77cd62e2008-09-26 17:00:11 -07001322 }
Zhang Wei173acc72008-03-01 07:42:48 -07001323
Ira Snyderd3f620b2010-01-06 13:34:04 +00001324 /*
1325 * Hookup the IRQ handler(s)
1326 *
1327 * If we have a per-controller interrupt, we prefer that to the
1328 * per-channel interrupts to reduce the number of shared interrupt
1329 * handlers on the same IRQ line
1330 */
1331 err = fsldma_request_irqs(fdev);
1332 if (err) {
1333 dev_err(fdev->dev, "unable to request IRQs\n");
1334 goto out_free_fdev;
1335 }
1336
Zhang Wei173acc72008-03-01 07:42:48 -07001337 dma_async_device_register(&fdev->common);
1338 return 0;
1339
Ira Snydere7a29152010-01-06 13:34:03 +00001340out_free_fdev:
Ira Snyderd3f620b2010-01-06 13:34:04 +00001341 irq_dispose_mapping(fdev->irq);
Zhang Wei173acc72008-03-01 07:42:48 -07001342 kfree(fdev);
Ira Snydere7a29152010-01-06 13:34:03 +00001343out_return:
Zhang Wei173acc72008-03-01 07:42:48 -07001344 return err;
1345}
1346
Grant Likely2dc11582010-08-06 09:25:50 -06001347static int fsldma_of_remove(struct platform_device *op)
Timur Tabi77cd62e2008-09-26 17:00:11 -07001348{
Ira Snydera4f56d42010-01-06 13:34:01 +00001349 struct fsldma_device *fdev;
Timur Tabi77cd62e2008-09-26 17:00:11 -07001350 unsigned int i;
1351
Jingoo Handd3daca2013-05-24 10:10:13 +09001352 fdev = platform_get_drvdata(op);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001353 dma_async_device_unregister(&fdev->common);
1354
Ira Snyderd3f620b2010-01-06 13:34:04 +00001355 fsldma_free_irqs(fdev);
1356
Ira Snydere7a29152010-01-06 13:34:03 +00001357 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001358 if (fdev->chan[i])
1359 fsl_dma_chan_remove(fdev->chan[i]);
Ira Snydere7a29152010-01-06 13:34:03 +00001360 }
Timur Tabi77cd62e2008-09-26 17:00:11 -07001361
Ira Snydere7a29152010-01-06 13:34:03 +00001362 iounmap(fdev->regs);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001363 kfree(fdev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001364
1365 return 0;
1366}
1367
Márton Németh4b1cf1f2010-02-02 23:41:06 -07001368static const struct of_device_id fsldma_of_ids[] = {
Hongbo Zhang8de7a7d2013-09-26 17:33:43 +08001369 { .compatible = "fsl,elo3-dma", },
Kumar Gala049c9d42008-03-31 11:13:21 -05001370 { .compatible = "fsl,eloplus-dma", },
1371 { .compatible = "fsl,elo-dma", },
Zhang Wei173acc72008-03-01 07:42:48 -07001372 {}
1373};
1374
Ira W. Snyder8faa7cf2011-04-07 10:33:03 -07001375static struct platform_driver fsldma_of_driver = {
Grant Likely40182942010-04-13 16:13:02 -07001376 .driver = {
1377 .name = "fsl-elo-dma",
1378 .owner = THIS_MODULE,
1379 .of_match_table = fsldma_of_ids,
1380 },
1381 .probe = fsldma_of_probe,
1382 .remove = fsldma_of_remove,
Zhang Wei173acc72008-03-01 07:42:48 -07001383};
1384
Ira Snydera4f56d42010-01-06 13:34:01 +00001385/*----------------------------------------------------------------------------*/
1386/* Module Init / Exit */
1387/*----------------------------------------------------------------------------*/
1388
1389static __init int fsldma_init(void)
Zhang Wei173acc72008-03-01 07:42:48 -07001390{
Hongbo Zhang8de7a7d2013-09-26 17:33:43 +08001391 pr_info("Freescale Elo series DMA driver\n");
Grant Likely00006122011-02-22 19:59:54 -07001392 return platform_driver_register(&fsldma_of_driver);
Zhang Wei173acc72008-03-01 07:42:48 -07001393}
1394
Ira Snydera4f56d42010-01-06 13:34:01 +00001395static void __exit fsldma_exit(void)
Timur Tabi77cd62e2008-09-26 17:00:11 -07001396{
Grant Likely00006122011-02-22 19:59:54 -07001397 platform_driver_unregister(&fsldma_of_driver);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001398}
1399
Ira Snydera4f56d42010-01-06 13:34:01 +00001400subsys_initcall(fsldma_init);
1401module_exit(fsldma_exit);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001402
Hongbo Zhang8de7a7d2013-09-26 17:33:43 +08001403MODULE_DESCRIPTION("Freescale Elo series DMA driver");
Timur Tabi77cd62e2008-09-26 17:00:11 -07001404MODULE_LICENSE("GPL");