Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> |
| 3 | * Copyright © 2006-2007 Intel Corporation |
| 4 | * Jesse Barnes <jesse.barnes@intel.com> |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the next |
| 14 | * paragraph) shall be included in all copies or substantial portions of the |
| 15 | * Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 23 | * DEALINGS IN THE SOFTWARE. |
| 24 | * |
| 25 | * Authors: |
| 26 | * Eric Anholt <eric@anholt.net> |
| 27 | */ |
| 28 | #include <linux/i2c.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 30 | #include <linux/delay.h> |
| 31 | #include "drmP.h" |
| 32 | #include "drm.h" |
| 33 | #include "drm_crtc.h" |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 34 | #include "drm_edid.h" |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 35 | #include "intel_drv.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include "i915_drm.h" |
| 37 | #include "i915_drv.h" |
| 38 | #include "intel_sdvo_regs.h" |
| 39 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 40 | #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) |
| 41 | #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) |
| 42 | #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) |
| 43 | #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0) |
| 44 | |
| 45 | #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ |
| 46 | SDVO_TV_MASK) |
| 47 | |
| 48 | #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) |
| 49 | #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 50 | #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 51 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 52 | |
Chris Wilson | 2e88e40 | 2010-08-07 11:01:27 +0100 | [diff] [blame] | 53 | static const char *tv_format_names[] = { |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 54 | "NTSC_M" , "NTSC_J" , "NTSC_443", |
| 55 | "PAL_B" , "PAL_D" , "PAL_G" , |
| 56 | "PAL_H" , "PAL_I" , "PAL_M" , |
| 57 | "PAL_N" , "PAL_NC" , "PAL_60" , |
| 58 | "SECAM_B" , "SECAM_D" , "SECAM_G" , |
| 59 | "SECAM_K" , "SECAM_K1", "SECAM_L" , |
| 60 | "SECAM_60" |
| 61 | }; |
| 62 | |
| 63 | #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) |
| 64 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 65 | struct intel_sdvo { |
| 66 | struct intel_encoder base; |
| 67 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 68 | struct i2c_adapter *i2c; |
Keith Packard | f9c10a9 | 2009-05-30 12:16:25 -0700 | [diff] [blame] | 69 | u8 slave_addr; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 70 | |
| 71 | /* Register for the SDVO device: SDVOB or SDVOC */ |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 72 | int sdvo_reg; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 73 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 74 | /* Active outputs controlled by this SDVO output */ |
| 75 | uint16_t controlled_output; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 76 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 77 | /* |
| 78 | * Capabilities of the SDVO device returned by |
| 79 | * i830_sdvo_get_capabilities() |
| 80 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 81 | struct intel_sdvo_caps caps; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 82 | |
| 83 | /* Pixel clock limitations reported by the SDVO device, in kHz */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 84 | int pixel_clock_min, pixel_clock_max; |
| 85 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 86 | /* |
| 87 | * For multiple function SDVO device, |
| 88 | * this is for current attached outputs. |
| 89 | */ |
| 90 | uint16_t attached_output; |
| 91 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 92 | /** |
| 93 | * This is set if we're going to treat the device as TV-out. |
| 94 | * |
| 95 | * While we have these nice friendly flags for output types that ought |
| 96 | * to decide this for us, the S-Video output on our HDMI+S-Video card |
| 97 | * shows up as RGB1 (VGA). |
| 98 | */ |
| 99 | bool is_tv; |
| 100 | |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 101 | /* This is for current tv format name */ |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 102 | int tv_format_index; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 103 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 104 | /** |
| 105 | * This is set if we treat the device as HDMI, instead of DVI. |
| 106 | */ |
| 107 | bool is_hdmi; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 108 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 109 | /** |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 110 | * This is set if we detect output of sdvo device as LVDS and |
| 111 | * have a valid fixed mode to use with the panel. |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 112 | */ |
| 113 | bool is_lvds; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 114 | |
| 115 | /** |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 116 | * This is sdvo fixed pannel mode pointer |
| 117 | */ |
| 118 | struct drm_display_mode *sdvo_lvds_fixed_mode; |
| 119 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 120 | /* |
| 121 | * supported encoding mode, used to determine whether HDMI is |
| 122 | * supported |
| 123 | */ |
| 124 | struct intel_sdvo_encode encode; |
| 125 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 126 | /* DDC bus used by this SDVO encoder */ |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 127 | uint8_t ddc_bus; |
| 128 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 129 | /* Input timings for adjusted_mode */ |
| 130 | struct intel_sdvo_dtd input_dtd; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 131 | }; |
| 132 | |
| 133 | struct intel_sdvo_connector { |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 134 | struct intel_connector base; |
| 135 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 136 | /* Mark the type of connector */ |
| 137 | uint16_t output_flag; |
| 138 | |
| 139 | /* This contains all current supported TV format */ |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 140 | u8 tv_format_supported[TV_FORMAT_NUM]; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 141 | int format_supported_num; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 142 | struct drm_property *tv_format; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 143 | |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 144 | /* add the property for the SDVO-TV */ |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 145 | struct drm_property *left; |
| 146 | struct drm_property *right; |
| 147 | struct drm_property *top; |
| 148 | struct drm_property *bottom; |
| 149 | struct drm_property *hpos; |
| 150 | struct drm_property *vpos; |
| 151 | struct drm_property *contrast; |
| 152 | struct drm_property *saturation; |
| 153 | struct drm_property *hue; |
| 154 | struct drm_property *sharpness; |
| 155 | struct drm_property *flicker_filter; |
| 156 | struct drm_property *flicker_filter_adaptive; |
| 157 | struct drm_property *flicker_filter_2d; |
| 158 | struct drm_property *tv_chroma_filter; |
| 159 | struct drm_property *tv_luma_filter; |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 160 | struct drm_property *dot_crawl; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 161 | |
| 162 | /* add the property for the SDVO-TV/LVDS */ |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 163 | struct drm_property *brightness; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 164 | |
| 165 | /* Add variable to record current setting for the above property */ |
| 166 | u32 left_margin, right_margin, top_margin, bottom_margin; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 167 | |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 168 | /* this is to get the range of margin.*/ |
| 169 | u32 max_hscan, max_vscan; |
| 170 | u32 max_hpos, cur_hpos; |
| 171 | u32 max_vpos, cur_vpos; |
| 172 | u32 cur_brightness, max_brightness; |
| 173 | u32 cur_contrast, max_contrast; |
| 174 | u32 cur_saturation, max_saturation; |
| 175 | u32 cur_hue, max_hue; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 176 | u32 cur_sharpness, max_sharpness; |
| 177 | u32 cur_flicker_filter, max_flicker_filter; |
| 178 | u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; |
| 179 | u32 cur_flicker_filter_2d, max_flicker_filter_2d; |
| 180 | u32 cur_tv_chroma_filter, max_tv_chroma_filter; |
| 181 | u32 cur_tv_luma_filter, max_tv_luma_filter; |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 182 | u32 cur_dot_crawl, max_dot_crawl; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 183 | }; |
| 184 | |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 185 | static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 186 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 187 | return container_of(encoder, struct intel_sdvo, base.base); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 188 | } |
| 189 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 190 | static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) |
| 191 | { |
| 192 | return container_of(intel_attached_encoder(connector), |
| 193 | struct intel_sdvo, base); |
| 194 | } |
| 195 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 196 | static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) |
| 197 | { |
| 198 | return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); |
| 199 | } |
| 200 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 201 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 202 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 203 | static bool |
| 204 | intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
| 205 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 206 | int type); |
| 207 | static bool |
| 208 | intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
| 209 | struct intel_sdvo_connector *intel_sdvo_connector); |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 210 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 211 | /** |
| 212 | * Writes the SDVOB or SDVOC with the given value, but always writes both |
| 213 | * SDVOB and SDVOC to work around apparent hardware issues (according to |
| 214 | * comments in the BIOS). |
| 215 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 216 | static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 217 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 218 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 219 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 220 | u32 bval = val, cval = val; |
| 221 | int i; |
| 222 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 223 | if (intel_sdvo->sdvo_reg == PCH_SDVOB) { |
| 224 | I915_WRITE(intel_sdvo->sdvo_reg, val); |
| 225 | I915_READ(intel_sdvo->sdvo_reg); |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 226 | return; |
| 227 | } |
| 228 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 229 | if (intel_sdvo->sdvo_reg == SDVOB) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 230 | cval = I915_READ(SDVOC); |
| 231 | } else { |
| 232 | bval = I915_READ(SDVOB); |
| 233 | } |
| 234 | /* |
| 235 | * Write the registers twice for luck. Sometimes, |
| 236 | * writing them only once doesn't appear to 'stick'. |
| 237 | * The BIOS does this too. Yay, magic |
| 238 | */ |
| 239 | for (i = 0; i < 2; i++) |
| 240 | { |
| 241 | I915_WRITE(SDVOB, bval); |
| 242 | I915_READ(SDVOB); |
| 243 | I915_WRITE(SDVOC, cval); |
| 244 | I915_READ(SDVOC); |
| 245 | } |
| 246 | } |
| 247 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 248 | static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 249 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 250 | u8 out_buf[2] = { addr, 0 }; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 251 | u8 buf[2]; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 252 | struct i2c_msg msgs[] = { |
| 253 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 254 | .addr = intel_sdvo->slave_addr >> 1, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 255 | .flags = 0, |
| 256 | .len = 1, |
| 257 | .buf = out_buf, |
| 258 | }, |
| 259 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 260 | .addr = intel_sdvo->slave_addr >> 1, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 261 | .flags = I2C_M_RD, |
| 262 | .len = 1, |
| 263 | .buf = buf, |
| 264 | } |
| 265 | }; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 266 | int ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 267 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 268 | if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 269 | { |
| 270 | *ch = buf[0]; |
| 271 | return true; |
| 272 | } |
| 273 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 274 | DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 275 | return false; |
| 276 | } |
| 277 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 278 | static bool intel_sdvo_write_byte(struct intel_sdvo *intel_sdvo, int addr, u8 ch) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 279 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 280 | u8 out_buf[2] = { addr, ch }; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 281 | struct i2c_msg msgs[] = { |
| 282 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 283 | .addr = intel_sdvo->slave_addr >> 1, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 284 | .flags = 0, |
| 285 | .len = 2, |
| 286 | .buf = out_buf, |
| 287 | } |
| 288 | }; |
| 289 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 290 | return i2c_transfer(intel_sdvo->i2c, msgs, 1) == 1; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 291 | } |
| 292 | |
| 293 | #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} |
| 294 | /** Mapping of command numbers to names, for debug output */ |
Tobias Klauser | 005568b | 2009-02-09 22:02:42 +0100 | [diff] [blame] | 295 | static const struct _sdvo_cmd_name { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 296 | u8 cmd; |
Chris Wilson | 2e88e40 | 2010-08-07 11:01:27 +0100 | [diff] [blame] | 297 | const char *name; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 298 | } sdvo_cmd_names[] = { |
| 299 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), |
| 300 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), |
| 301 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), |
| 302 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), |
| 303 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), |
| 304 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), |
| 305 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), |
| 306 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), |
| 307 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), |
| 308 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), |
| 309 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), |
| 310 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), |
| 311 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), |
| 312 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), |
| 313 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), |
| 314 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), |
| 315 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), |
| 316 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), |
| 317 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), |
| 318 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), |
| 319 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), |
| 320 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), |
| 321 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), |
| 322 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), |
| 323 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), |
| 324 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), |
| 325 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), |
| 326 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), |
| 327 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), |
| 328 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), |
| 329 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), |
| 330 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), |
| 331 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), |
| 332 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), |
| 333 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 334 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), |
| 335 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), |
| 336 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), |
| 337 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 338 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 339 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), |
| 340 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), |
| 341 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 342 | |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 343 | /* Add the op code for SDVO enhancements */ |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 344 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), |
| 345 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), |
| 346 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), |
| 347 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), |
| 348 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), |
| 349 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 350 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), |
| 351 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), |
| 352 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), |
| 353 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), |
| 354 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), |
| 355 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), |
| 356 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), |
| 357 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), |
| 358 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), |
| 359 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), |
| 360 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), |
| 361 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), |
| 362 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), |
| 363 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), |
| 364 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), |
| 365 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), |
| 366 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), |
| 367 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 368 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), |
| 369 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), |
| 370 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), |
| 371 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), |
| 372 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), |
| 373 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), |
| 374 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), |
| 375 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), |
| 376 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), |
| 377 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), |
| 378 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), |
| 379 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), |
| 380 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), |
| 381 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), |
| 382 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), |
| 383 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), |
| 384 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), |
| 385 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), |
| 386 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), |
| 387 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), |
| 388 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 389 | /* HDMI op code */ |
| 390 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), |
| 391 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), |
| 392 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), |
| 393 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), |
| 394 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), |
| 395 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), |
| 396 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), |
| 397 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), |
| 398 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), |
| 399 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), |
| 400 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), |
| 401 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), |
| 402 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), |
| 403 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), |
| 404 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), |
| 405 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), |
| 406 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), |
| 407 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), |
| 408 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), |
| 409 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 410 | }; |
| 411 | |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 412 | #define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 413 | #define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC") |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 414 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 415 | static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 416 | const void *args, int args_len) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 417 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 418 | int i; |
| 419 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 420 | DRM_DEBUG_KMS("%s: W: %02X ", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 421 | SDVO_NAME(intel_sdvo), cmd); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 422 | for (i = 0; i < args_len; i++) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 423 | DRM_LOG_KMS("%02X ", ((u8 *)args)[i]); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 424 | for (; i < 8; i++) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 425 | DRM_LOG_KMS(" "); |
Kulikov Vasiliy | 04ad327 | 2010-06-28 15:54:56 +0400 | [diff] [blame] | 426 | for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 427 | if (cmd == sdvo_cmd_names[i].cmd) { |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 428 | DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 429 | break; |
| 430 | } |
| 431 | } |
Kulikov Vasiliy | 04ad327 | 2010-06-28 15:54:56 +0400 | [diff] [blame] | 432 | if (i == ARRAY_SIZE(sdvo_cmd_names)) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 433 | DRM_LOG_KMS("(%02X)", cmd); |
| 434 | DRM_LOG_KMS("\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 435 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 436 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 437 | static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, |
| 438 | const void *args, int args_len) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 439 | { |
| 440 | int i; |
| 441 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 442 | intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 443 | |
| 444 | for (i = 0; i < args_len; i++) { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 445 | if (!intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0 - i, |
| 446 | ((u8*)args)[i])) |
| 447 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 448 | } |
| 449 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 450 | return intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_OPCODE, cmd); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 451 | } |
| 452 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 453 | static const char *cmd_status_names[] = { |
| 454 | "Power on", |
| 455 | "Success", |
| 456 | "Not supported", |
| 457 | "Invalid arg", |
| 458 | "Pending", |
| 459 | "Target not specified", |
| 460 | "Scaling not supported" |
| 461 | }; |
| 462 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 463 | static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, |
| 464 | void *response, int response_len) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 465 | { |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 466 | u8 retry = 5; |
| 467 | u8 status; |
Zhenyu Wang | 33b5296 | 2009-03-24 14:02:40 +0800 | [diff] [blame] | 468 | int i; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 469 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 470 | /* |
| 471 | * The documentation states that all commands will be |
| 472 | * processed within 15µs, and that we need only poll |
| 473 | * the status byte a maximum of 3 times in order for the |
| 474 | * command to be complete. |
| 475 | * |
| 476 | * Check 5 times in case the hardware failed to read the docs. |
| 477 | */ |
| 478 | do { |
| 479 | if (!intel_sdvo_read_byte(intel_sdvo, |
| 480 | SDVO_I2C_CMD_STATUS, |
| 481 | &status)) |
| 482 | return false; |
| 483 | } while (status == SDVO_CMD_STATUS_PENDING && --retry); |
| 484 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 485 | DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 486 | if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 487 | DRM_LOG_KMS("(%s)", cmd_status_names[status]); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 488 | else |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 489 | DRM_LOG_KMS("(??? %d)", status); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 490 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 491 | if (status != SDVO_CMD_STATUS_SUCCESS) |
| 492 | goto log_fail; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 493 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 494 | /* Read the command response */ |
| 495 | for (i = 0; i < response_len; i++) { |
| 496 | if (!intel_sdvo_read_byte(intel_sdvo, |
| 497 | SDVO_I2C_RETURN_0 + i, |
| 498 | &((u8 *)response)[i])) |
| 499 | goto log_fail; |
| 500 | DRM_LOG_KMS("%02X ", ((u8 *)response)[i]); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 501 | } |
| 502 | |
Chris Wilson | b5c616a | 2010-09-09 19:06:13 +0100 | [diff] [blame] | 503 | for (; i < 8; i++) |
| 504 | DRM_LOG_KMS(" "); |
| 505 | DRM_LOG_KMS("\n"); |
| 506 | |
| 507 | return true; |
| 508 | |
| 509 | log_fail: |
| 510 | DRM_LOG_KMS("\n"); |
| 511 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 512 | } |
| 513 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 514 | static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 515 | { |
| 516 | if (mode->clock >= 100000) |
| 517 | return 1; |
| 518 | else if (mode->clock >= 50000) |
| 519 | return 2; |
| 520 | else |
| 521 | return 4; |
| 522 | } |
| 523 | |
| 524 | /** |
Zhao Yakui | 6a304ca | 2010-01-08 10:58:19 +0800 | [diff] [blame] | 525 | * Try to read the response after issuie the DDC switch command. But it |
| 526 | * is noted that we must do the action of reading response and issuing DDC |
| 527 | * switch command in one I2C transaction. Otherwise when we try to start |
| 528 | * another I2C transaction after issuing the DDC bus switch, it will be |
| 529 | * switched to the internal SDVO register. |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 530 | */ |
Chris Wilson | 819f3fb | 2010-09-14 19:11:56 +0100 | [diff] [blame] | 531 | static int intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, |
| 532 | u8 target) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 533 | { |
Zhao Yakui | 6a304ca | 2010-01-08 10:58:19 +0800 | [diff] [blame] | 534 | u8 out_buf[2], cmd_buf[2], ret_value[2], ret; |
| 535 | struct i2c_msg msgs[] = { |
| 536 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 537 | .addr = intel_sdvo->slave_addr >> 1, |
Zhao Yakui | 6a304ca | 2010-01-08 10:58:19 +0800 | [diff] [blame] | 538 | .flags = 0, |
| 539 | .len = 2, |
| 540 | .buf = out_buf, |
| 541 | }, |
| 542 | /* the following two are to read the response */ |
| 543 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 544 | .addr = intel_sdvo->slave_addr >> 1, |
Zhao Yakui | 6a304ca | 2010-01-08 10:58:19 +0800 | [diff] [blame] | 545 | .flags = 0, |
| 546 | .len = 1, |
| 547 | .buf = cmd_buf, |
| 548 | }, |
| 549 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 550 | .addr = intel_sdvo->slave_addr >> 1, |
Zhao Yakui | 6a304ca | 2010-01-08 10:58:19 +0800 | [diff] [blame] | 551 | .flags = I2C_M_RD, |
| 552 | .len = 1, |
| 553 | .buf = ret_value, |
| 554 | }, |
| 555 | }; |
| 556 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 557 | intel_sdvo_debug_write(intel_sdvo, SDVO_CMD_SET_CONTROL_BUS_SWITCH, |
Chris Wilson | 819f3fb | 2010-09-14 19:11:56 +0100 | [diff] [blame] | 558 | &target, 1); |
Zhao Yakui | 6a304ca | 2010-01-08 10:58:19 +0800 | [diff] [blame] | 559 | /* write the DDC switch command argument */ |
Chris Wilson | 819f3fb | 2010-09-14 19:11:56 +0100 | [diff] [blame] | 560 | if (!intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0, target)) |
| 561 | return -EIO; |
Zhao Yakui | 6a304ca | 2010-01-08 10:58:19 +0800 | [diff] [blame] | 562 | |
| 563 | out_buf[0] = SDVO_I2C_OPCODE; |
| 564 | out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH; |
| 565 | cmd_buf[0] = SDVO_I2C_CMD_STATUS; |
| 566 | cmd_buf[1] = 0; |
| 567 | ret_value[0] = 0; |
| 568 | ret_value[1] = 0; |
| 569 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 570 | ret = i2c_transfer(intel_sdvo->i2c, msgs, 3); |
Chris Wilson | 819f3fb | 2010-09-14 19:11:56 +0100 | [diff] [blame] | 571 | if (ret < 0) |
| 572 | return ret; |
Zhao Yakui | 6a304ca | 2010-01-08 10:58:19 +0800 | [diff] [blame] | 573 | if (ret != 3) { |
| 574 | /* failure in I2C transfer */ |
| 575 | DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); |
Chris Wilson | 819f3fb | 2010-09-14 19:11:56 +0100 | [diff] [blame] | 576 | return -EIO; |
Zhao Yakui | 6a304ca | 2010-01-08 10:58:19 +0800 | [diff] [blame] | 577 | } |
| 578 | if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) { |
| 579 | DRM_DEBUG_KMS("DDC switch command returns response %d\n", |
Chris Wilson | 819f3fb | 2010-09-14 19:11:56 +0100 | [diff] [blame] | 580 | ret_value[0]); |
| 581 | return -EIO; |
Zhao Yakui | 6a304ca | 2010-01-08 10:58:19 +0800 | [diff] [blame] | 582 | } |
Chris Wilson | 819f3fb | 2010-09-14 19:11:56 +0100 | [diff] [blame] | 583 | |
| 584 | return 0; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 585 | } |
| 586 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 587 | static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) |
| 588 | { |
| 589 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) |
| 590 | return false; |
| 591 | |
| 592 | return intel_sdvo_read_response(intel_sdvo, NULL, 0); |
| 593 | } |
| 594 | |
| 595 | static bool |
| 596 | intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) |
| 597 | { |
| 598 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) |
| 599 | return false; |
| 600 | |
| 601 | return intel_sdvo_read_response(intel_sdvo, value, len); |
| 602 | } |
| 603 | |
| 604 | static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 605 | { |
| 606 | struct intel_sdvo_set_target_input_args targets = {0}; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 607 | return intel_sdvo_set_value(intel_sdvo, |
| 608 | SDVO_CMD_SET_TARGET_INPUT, |
| 609 | &targets, sizeof(targets)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 610 | } |
| 611 | |
| 612 | /** |
| 613 | * Return whether each input is trained. |
| 614 | * |
| 615 | * This function is making an assumption about the layout of the response, |
| 616 | * which should be checked against the docs. |
| 617 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 618 | static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 619 | { |
| 620 | struct intel_sdvo_get_trained_inputs_response response; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 621 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 622 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, |
| 623 | &response, sizeof(response))) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 624 | return false; |
| 625 | |
| 626 | *input_1 = response.input0_trained; |
| 627 | *input_2 = response.input1_trained; |
| 628 | return true; |
| 629 | } |
| 630 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 631 | static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 632 | u16 outputs) |
| 633 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 634 | return intel_sdvo_set_value(intel_sdvo, |
| 635 | SDVO_CMD_SET_ACTIVE_OUTPUTS, |
| 636 | &outputs, sizeof(outputs)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 637 | } |
| 638 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 639 | static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 640 | int mode) |
| 641 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 642 | u8 state = SDVO_ENCODER_STATE_ON; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 643 | |
| 644 | switch (mode) { |
| 645 | case DRM_MODE_DPMS_ON: |
| 646 | state = SDVO_ENCODER_STATE_ON; |
| 647 | break; |
| 648 | case DRM_MODE_DPMS_STANDBY: |
| 649 | state = SDVO_ENCODER_STATE_STANDBY; |
| 650 | break; |
| 651 | case DRM_MODE_DPMS_SUSPEND: |
| 652 | state = SDVO_ENCODER_STATE_SUSPEND; |
| 653 | break; |
| 654 | case DRM_MODE_DPMS_OFF: |
| 655 | state = SDVO_ENCODER_STATE_OFF; |
| 656 | break; |
| 657 | } |
| 658 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 659 | return intel_sdvo_set_value(intel_sdvo, |
| 660 | SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 661 | } |
| 662 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 663 | static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 664 | int *clock_min, |
| 665 | int *clock_max) |
| 666 | { |
| 667 | struct intel_sdvo_pixel_clock_range clocks; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 668 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 669 | if (!intel_sdvo_get_value(intel_sdvo, |
| 670 | SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, |
| 671 | &clocks, sizeof(clocks))) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 672 | return false; |
| 673 | |
| 674 | /* Convert the values from units of 10 kHz to kHz. */ |
| 675 | *clock_min = clocks.min * 10; |
| 676 | *clock_max = clocks.max * 10; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 677 | return true; |
| 678 | } |
| 679 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 680 | static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 681 | u16 outputs) |
| 682 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 683 | return intel_sdvo_set_value(intel_sdvo, |
| 684 | SDVO_CMD_SET_TARGET_OUTPUT, |
| 685 | &outputs, sizeof(outputs)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 686 | } |
| 687 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 688 | static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 689 | struct intel_sdvo_dtd *dtd) |
| 690 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 691 | return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && |
| 692 | intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 693 | } |
| 694 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 695 | static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 696 | struct intel_sdvo_dtd *dtd) |
| 697 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 698 | return intel_sdvo_set_timing(intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 699 | SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); |
| 700 | } |
| 701 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 702 | static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 703 | struct intel_sdvo_dtd *dtd) |
| 704 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 705 | return intel_sdvo_set_timing(intel_sdvo, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 706 | SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); |
| 707 | } |
| 708 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 709 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 710 | intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 711 | uint16_t clock, |
| 712 | uint16_t width, |
| 713 | uint16_t height) |
| 714 | { |
| 715 | struct intel_sdvo_preferred_input_timing_args args; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 716 | |
Zhenyu Wang | e642c6f | 2009-03-24 14:02:42 +0800 | [diff] [blame] | 717 | memset(&args, 0, sizeof(args)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 718 | args.clock = clock; |
| 719 | args.width = width; |
| 720 | args.height = height; |
Zhenyu Wang | e642c6f | 2009-03-24 14:02:42 +0800 | [diff] [blame] | 721 | args.interlace = 0; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 722 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 723 | if (intel_sdvo->is_lvds && |
| 724 | (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || |
| 725 | intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 726 | args.scaled = 1; |
| 727 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 728 | return intel_sdvo_set_value(intel_sdvo, |
| 729 | SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, |
| 730 | &args, sizeof(args)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 731 | } |
| 732 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 733 | static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 734 | struct intel_sdvo_dtd *dtd) |
| 735 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 736 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, |
| 737 | &dtd->part1, sizeof(dtd->part1)) && |
| 738 | intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, |
| 739 | &dtd->part2, sizeof(dtd->part2)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 740 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 741 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 742 | static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 743 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 744 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 745 | } |
| 746 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 747 | static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 748 | const struct drm_display_mode *mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 749 | { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 750 | uint16_t width, height; |
| 751 | uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; |
| 752 | uint16_t h_sync_offset, v_sync_offset; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 753 | |
| 754 | width = mode->crtc_hdisplay; |
| 755 | height = mode->crtc_vdisplay; |
| 756 | |
| 757 | /* do some mode translations */ |
| 758 | h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start; |
| 759 | h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; |
| 760 | |
| 761 | v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start; |
| 762 | v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; |
| 763 | |
| 764 | h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start; |
| 765 | v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start; |
| 766 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 767 | dtd->part1.clock = mode->clock / 10; |
| 768 | dtd->part1.h_active = width & 0xff; |
| 769 | dtd->part1.h_blank = h_blank_len & 0xff; |
| 770 | dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 771 | ((h_blank_len >> 8) & 0xf); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 772 | dtd->part1.v_active = height & 0xff; |
| 773 | dtd->part1.v_blank = v_blank_len & 0xff; |
| 774 | dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 775 | ((v_blank_len >> 8) & 0xf); |
| 776 | |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 777 | dtd->part2.h_sync_off = h_sync_offset & 0xff; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 778 | dtd->part2.h_sync_width = h_sync_len & 0xff; |
| 779 | dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 780 | (v_sync_len & 0xf); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 781 | dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 782 | ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | |
| 783 | ((v_sync_len & 0x30) >> 4); |
| 784 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 785 | dtd->part2.dtd_flags = 0x18; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 786 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 787 | dtd->part2.dtd_flags |= 0x2; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 788 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 789 | dtd->part2.dtd_flags |= 0x4; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 790 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 791 | dtd->part2.sdvo_flags = 0; |
| 792 | dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; |
| 793 | dtd->part2.reserved = 0; |
| 794 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 795 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 796 | static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 797 | const struct intel_sdvo_dtd *dtd) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 798 | { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 799 | mode->hdisplay = dtd->part1.h_active; |
| 800 | mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; |
| 801 | mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off; |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 802 | mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 803 | mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width; |
| 804 | mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; |
| 805 | mode->htotal = mode->hdisplay + dtd->part1.h_blank; |
| 806 | mode->htotal += (dtd->part1.h_high & 0xf) << 8; |
| 807 | |
| 808 | mode->vdisplay = dtd->part1.v_active; |
| 809 | mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; |
| 810 | mode->vsync_start = mode->vdisplay; |
| 811 | mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 812 | mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 813 | mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0; |
| 814 | mode->vsync_end = mode->vsync_start + |
| 815 | (dtd->part2.v_sync_off_width & 0xf); |
| 816 | mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; |
| 817 | mode->vtotal = mode->vdisplay + dtd->part1.v_blank; |
| 818 | mode->vtotal += (dtd->part1.v_high & 0xf) << 8; |
| 819 | |
| 820 | mode->clock = dtd->part1.clock * 10; |
| 821 | |
Zhenyu Wang | 171a9e9 | 2009-03-24 14:02:41 +0800 | [diff] [blame] | 822 | mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 823 | if (dtd->part2.dtd_flags & 0x2) |
| 824 | mode->flags |= DRM_MODE_FLAG_PHSYNC; |
| 825 | if (dtd->part2.dtd_flags & 0x4) |
| 826 | mode->flags |= DRM_MODE_FLAG_PVSYNC; |
| 827 | } |
| 828 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 829 | static bool intel_sdvo_get_supp_encode(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 830 | struct intel_sdvo_encode *encode) |
| 831 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 832 | if (intel_sdvo_get_value(intel_sdvo, |
| 833 | SDVO_CMD_GET_SUPP_ENCODE, |
| 834 | encode, sizeof(*encode))) |
| 835 | return true; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 836 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 837 | /* non-support means DVI */ |
| 838 | memset(encode, 0, sizeof(*encode)); |
| 839 | return false; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 840 | } |
| 841 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 842 | static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 843 | uint8_t mode) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 844 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 845 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 846 | } |
| 847 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 848 | static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 849 | uint8_t mode) |
| 850 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 851 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 852 | } |
| 853 | |
| 854 | #if 0 |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 855 | static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 856 | { |
| 857 | int i, j; |
| 858 | uint8_t set_buf_index[2]; |
| 859 | uint8_t av_split; |
| 860 | uint8_t buf_size; |
| 861 | uint8_t buf[48]; |
| 862 | uint8_t *pos; |
| 863 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 864 | intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 865 | |
| 866 | for (i = 0; i <= av_split; i++) { |
| 867 | set_buf_index[0] = i; set_buf_index[1] = 0; |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 868 | intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 869 | set_buf_index, 2); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 870 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); |
| 871 | intel_sdvo_read_response(encoder, &buf_size, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 872 | |
| 873 | pos = buf; |
| 874 | for (j = 0; j <= buf_size; j += 8) { |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 875 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 876 | NULL, 0); |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 877 | intel_sdvo_read_response(encoder, pos, 8); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 878 | pos += 8; |
| 879 | } |
| 880 | } |
| 881 | } |
| 882 | #endif |
| 883 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 884 | static bool intel_sdvo_set_hdmi_buf(struct intel_sdvo *intel_sdvo, |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 885 | int index, |
| 886 | uint8_t *data, int8_t size, uint8_t tx_rate) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 887 | { |
| 888 | uint8_t set_buf_index[2]; |
| 889 | |
| 890 | set_buf_index[0] = index; |
| 891 | set_buf_index[1] = 0; |
| 892 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 893 | if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_INDEX, |
| 894 | set_buf_index, 2)) |
| 895 | return false; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 896 | |
| 897 | for (; size > 0; size -= 8) { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 898 | if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_DATA, data, 8)) |
| 899 | return false; |
| 900 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 901 | data += 8; |
| 902 | } |
| 903 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 904 | return intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 905 | } |
| 906 | |
| 907 | static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size) |
| 908 | { |
| 909 | uint8_t csum = 0; |
| 910 | int i; |
| 911 | |
| 912 | for (i = 0; i < size; i++) |
| 913 | csum += data[i]; |
| 914 | |
| 915 | return 0x100 - csum; |
| 916 | } |
| 917 | |
| 918 | #define DIP_TYPE_AVI 0x82 |
| 919 | #define DIP_VERSION_AVI 0x2 |
| 920 | #define DIP_LEN_AVI 13 |
| 921 | |
| 922 | struct dip_infoframe { |
| 923 | uint8_t type; |
| 924 | uint8_t version; |
| 925 | uint8_t len; |
| 926 | uint8_t checksum; |
| 927 | union { |
| 928 | struct { |
| 929 | /* Packet Byte #1 */ |
| 930 | uint8_t S:2; |
| 931 | uint8_t B:2; |
| 932 | uint8_t A:1; |
| 933 | uint8_t Y:2; |
| 934 | uint8_t rsvd1:1; |
| 935 | /* Packet Byte #2 */ |
| 936 | uint8_t R:4; |
| 937 | uint8_t M:2; |
| 938 | uint8_t C:2; |
| 939 | /* Packet Byte #3 */ |
| 940 | uint8_t SC:2; |
| 941 | uint8_t Q:2; |
| 942 | uint8_t EC:3; |
| 943 | uint8_t ITC:1; |
| 944 | /* Packet Byte #4 */ |
| 945 | uint8_t VIC:7; |
| 946 | uint8_t rsvd2:1; |
| 947 | /* Packet Byte #5 */ |
| 948 | uint8_t PR:4; |
| 949 | uint8_t rsvd3:4; |
| 950 | /* Packet Byte #6~13 */ |
| 951 | uint16_t top_bar_end; |
| 952 | uint16_t bottom_bar_start; |
| 953 | uint16_t left_bar_end; |
| 954 | uint16_t right_bar_start; |
| 955 | } avi; |
| 956 | struct { |
| 957 | /* Packet Byte #1 */ |
| 958 | uint8_t channel_count:3; |
| 959 | uint8_t rsvd1:1; |
| 960 | uint8_t coding_type:4; |
| 961 | /* Packet Byte #2 */ |
| 962 | uint8_t sample_size:2; /* SS0, SS1 */ |
| 963 | uint8_t sample_frequency:3; |
| 964 | uint8_t rsvd2:3; |
| 965 | /* Packet Byte #3 */ |
| 966 | uint8_t coding_type_private:5; |
| 967 | uint8_t rsvd3:3; |
| 968 | /* Packet Byte #4 */ |
| 969 | uint8_t channel_allocation; |
| 970 | /* Packet Byte #5 */ |
| 971 | uint8_t rsvd4:3; |
| 972 | uint8_t level_shift:4; |
| 973 | uint8_t downmix_inhibit:1; |
| 974 | } audio; |
| 975 | uint8_t payload[28]; |
| 976 | } __attribute__ ((packed)) u; |
| 977 | } __attribute__((packed)); |
| 978 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 979 | static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 980 | struct drm_display_mode * mode) |
| 981 | { |
| 982 | struct dip_infoframe avi_if = { |
| 983 | .type = DIP_TYPE_AVI, |
| 984 | .version = DIP_VERSION_AVI, |
| 985 | .len = DIP_LEN_AVI, |
| 986 | }; |
| 987 | |
| 988 | avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if, |
| 989 | 4 + avi_if.len); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 990 | return intel_sdvo_set_hdmi_buf(intel_sdvo, 1, (uint8_t *)&avi_if, |
| 991 | 4 + avi_if.len, |
| 992 | SDVO_HBUF_TX_VSYNC); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 993 | } |
| 994 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 995 | static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 996 | { |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 997 | struct intel_sdvo_tv_format format; |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 998 | uint32_t format_map; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 999 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 1000 | format_map = 1 << intel_sdvo->tv_format_index; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1001 | memset(&format, 0, sizeof(format)); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1002 | memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1003 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1004 | BUILD_BUG_ON(sizeof(format) != 6); |
| 1005 | return intel_sdvo_set_value(intel_sdvo, |
| 1006 | SDVO_CMD_SET_TV_FORMAT, |
| 1007 | &format, sizeof(format)); |
| 1008 | } |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1009 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1010 | static bool |
| 1011 | intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, |
| 1012 | struct drm_display_mode *mode) |
| 1013 | { |
| 1014 | struct intel_sdvo_dtd output_dtd; |
| 1015 | |
| 1016 | if (!intel_sdvo_set_target_output(intel_sdvo, |
| 1017 | intel_sdvo->attached_output)) |
| 1018 | return false; |
| 1019 | |
| 1020 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); |
| 1021 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) |
| 1022 | return false; |
| 1023 | |
| 1024 | return true; |
| 1025 | } |
| 1026 | |
| 1027 | static bool |
| 1028 | intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo, |
| 1029 | struct drm_display_mode *mode, |
| 1030 | struct drm_display_mode *adjusted_mode) |
| 1031 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1032 | /* Reset the input timing to the screen. Assume always input 0. */ |
| 1033 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
| 1034 | return false; |
| 1035 | |
| 1036 | if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, |
| 1037 | mode->clock / 10, |
| 1038 | mode->hdisplay, |
| 1039 | mode->vdisplay)) |
| 1040 | return false; |
| 1041 | |
| 1042 | if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1043 | &intel_sdvo->input_dtd)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1044 | return false; |
| 1045 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1046 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1047 | |
| 1048 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1049 | return true; |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1050 | } |
| 1051 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1052 | static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, |
| 1053 | struct drm_display_mode *mode, |
| 1054 | struct drm_display_mode *adjusted_mode) |
| 1055 | { |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 1056 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1057 | int multiplier; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1058 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1059 | /* We need to construct preferred input timings based on our |
| 1060 | * output timings. To do that, we have to set the output |
| 1061 | * timings, even though this isn't really the right place in |
| 1062 | * the sequence to do it. Oh well. |
| 1063 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1064 | if (intel_sdvo->is_tv) { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1065 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1066 | return false; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1067 | |
Pavel Roskin | c74696b | 2010-09-02 14:46:34 -0400 | [diff] [blame] | 1068 | (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo, |
| 1069 | mode, |
| 1070 | adjusted_mode); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1071 | } else if (intel_sdvo->is_lvds) { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1072 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1073 | intel_sdvo->sdvo_lvds_fixed_mode)) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1074 | return false; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1075 | |
Pavel Roskin | c74696b | 2010-09-02 14:46:34 -0400 | [diff] [blame] | 1076 | (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo, |
| 1077 | mode, |
| 1078 | adjusted_mode); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1079 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1080 | |
| 1081 | /* Make the CRTC code factor in the SDVO pixel multiplier. The |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1082 | * SDVO device will factor out the multiplier during mode_set. |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1083 | */ |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1084 | multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode); |
| 1085 | intel_mode_set_pixel_multiplier(adjusted_mode, multiplier); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1086 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1087 | return true; |
| 1088 | } |
| 1089 | |
| 1090 | static void intel_sdvo_mode_set(struct drm_encoder *encoder, |
| 1091 | struct drm_display_mode *mode, |
| 1092 | struct drm_display_mode *adjusted_mode) |
| 1093 | { |
| 1094 | struct drm_device *dev = encoder->dev; |
| 1095 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1096 | struct drm_crtc *crtc = encoder->crtc; |
| 1097 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 1098 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1099 | u32 sdvox; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1100 | struct intel_sdvo_in_out_map in_out; |
| 1101 | struct intel_sdvo_dtd input_dtd; |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1102 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
| 1103 | int rate; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1104 | |
| 1105 | if (!mode) |
| 1106 | return; |
| 1107 | |
| 1108 | /* First, set the input mapping for the first input to our controlled |
| 1109 | * output. This is only correct if we're a single-input device, in |
| 1110 | * which case the first input is the output from the appropriate SDVO |
| 1111 | * channel on the motherboard. In a two-input device, the first input |
| 1112 | * will be SDVOB and the second SDVOC. |
| 1113 | */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1114 | in_out.in0 = intel_sdvo->attached_output; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1115 | in_out.in1 = 0; |
| 1116 | |
Pavel Roskin | c74696b | 2010-09-02 14:46:34 -0400 | [diff] [blame] | 1117 | intel_sdvo_set_value(intel_sdvo, |
| 1118 | SDVO_CMD_SET_IN_OUT_MAP, |
| 1119 | &in_out, sizeof(in_out)); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1120 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1121 | /* Set the output timings to the screen */ |
| 1122 | if (!intel_sdvo_set_target_output(intel_sdvo, |
| 1123 | intel_sdvo->attached_output)) |
| 1124 | return; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1125 | |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1126 | /* We have tried to get input timing in mode_fixup, and filled into |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1127 | * adjusted_mode. |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1128 | */ |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1129 | if (intel_sdvo->is_tv || intel_sdvo->is_lvds) { |
| 1130 | input_dtd = intel_sdvo->input_dtd; |
| 1131 | } else { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1132 | /* Set the output timing to the screen */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1133 | if (!intel_sdvo_set_target_output(intel_sdvo, |
| 1134 | intel_sdvo->attached_output)) |
| 1135 | return; |
| 1136 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1137 | intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); |
Pavel Roskin | c74696b | 2010-09-02 14:46:34 -0400 | [diff] [blame] | 1138 | (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1139 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1140 | |
| 1141 | /* Set the input timing to the screen. Assume always input 0. */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1142 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
| 1143 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1144 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1145 | if (intel_sdvo->is_hdmi && |
| 1146 | !intel_sdvo_set_avi_infoframe(intel_sdvo, mode)) |
| 1147 | return; |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1148 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1149 | if (intel_sdvo->is_tv && |
| 1150 | !intel_sdvo_set_tv_format(intel_sdvo)) |
| 1151 | return; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1152 | |
Pavel Roskin | c74696b | 2010-09-02 14:46:34 -0400 | [diff] [blame] | 1153 | (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1154 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1155 | switch (pixel_multiplier) { |
| 1156 | default: |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1157 | case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; |
| 1158 | case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; |
| 1159 | case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1160 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1161 | if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) |
| 1162 | return; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1163 | |
| 1164 | /* Set the SDVO control regs. */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame^] | 1165 | if (INTEL_INFO(dev)->gen >= 4) { |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1166 | sdvox = SDVO_BORDER_ENABLE; |
Adam Jackson | 81a14b4 | 2010-07-16 14:46:32 -0400 | [diff] [blame] | 1167 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 1168 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; |
| 1169 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 1170 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1171 | } else { |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1172 | sdvox = I915_READ(intel_sdvo->sdvo_reg); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1173 | switch (intel_sdvo->sdvo_reg) { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1174 | case SDVOB: |
| 1175 | sdvox &= SDVOB_PRESERVE_MASK; |
| 1176 | break; |
| 1177 | case SDVOC: |
| 1178 | sdvox &= SDVOC_PRESERVE_MASK; |
| 1179 | break; |
| 1180 | } |
| 1181 | sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; |
| 1182 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1183 | if (intel_crtc->pipe == 1) |
| 1184 | sdvox |= SDVO_PIPE_B_SELECT; |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1185 | if (intel_sdvo->is_hdmi) |
| 1186 | sdvox |= SDVO_AUDIO_ENABLE; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1187 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame^] | 1188 | if (INTEL_INFO(dev)->gen >= 4) { |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1189 | /* done in crtc_mode_set as the dpll_md reg must be written early */ |
| 1190 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
| 1191 | /* done in crtc_mode_set as it lives inside the dpll register */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1192 | } else { |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1193 | sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1194 | } |
| 1195 | |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1196 | if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1197 | sdvox |= SDVO_STALL_SELECT; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1198 | intel_sdvo_write_sdvox(intel_sdvo, sdvox); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1199 | } |
| 1200 | |
| 1201 | static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode) |
| 1202 | { |
| 1203 | struct drm_device *dev = encoder->dev; |
| 1204 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 1205 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1206 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1207 | u32 temp; |
| 1208 | |
| 1209 | if (mode != DRM_MODE_DPMS_ON) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1210 | intel_sdvo_set_active_outputs(intel_sdvo, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1211 | if (0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1212 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1213 | |
| 1214 | if (mode == DRM_MODE_DPMS_OFF) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1215 | temp = I915_READ(intel_sdvo->sdvo_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1216 | if ((temp & SDVO_ENABLE) != 0) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1217 | intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1218 | } |
| 1219 | } |
| 1220 | } else { |
| 1221 | bool input1, input2; |
| 1222 | int i; |
| 1223 | u8 status; |
| 1224 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1225 | temp = I915_READ(intel_sdvo->sdvo_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1226 | if ((temp & SDVO_ENABLE) == 0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1227 | intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1228 | for (i = 0; i < 2; i++) |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 1229 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1230 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1231 | status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1232 | /* Warn if the device reported failure to sync. |
| 1233 | * A lot of SDVO devices fail to notify of sync, but it's |
| 1234 | * a given it the status is a success, we succeeded. |
| 1235 | */ |
| 1236 | if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 1237 | DRM_DEBUG_KMS("First %s output reported failure to " |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1238 | "sync\n", SDVO_NAME(intel_sdvo)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1239 | } |
| 1240 | |
| 1241 | if (0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1242 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
| 1243 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1244 | } |
| 1245 | return; |
| 1246 | } |
| 1247 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1248 | static int intel_sdvo_mode_valid(struct drm_connector *connector, |
| 1249 | struct drm_display_mode *mode) |
| 1250 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1251 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1252 | |
| 1253 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 1254 | return MODE_NO_DBLESCAN; |
| 1255 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1256 | if (intel_sdvo->pixel_clock_min > mode->clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1257 | return MODE_CLOCK_LOW; |
| 1258 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1259 | if (intel_sdvo->pixel_clock_max < mode->clock) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1260 | return MODE_CLOCK_HIGH; |
| 1261 | |
Chris Wilson | 8545423 | 2010-08-08 14:28:23 +0100 | [diff] [blame] | 1262 | if (intel_sdvo->is_lvds) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1263 | if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1264 | return MODE_PANEL; |
| 1265 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1266 | if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1267 | return MODE_PANEL; |
| 1268 | } |
| 1269 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1270 | return MODE_OK; |
| 1271 | } |
| 1272 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1273 | static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1274 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1275 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DEVICE_CAPS, caps, sizeof(*caps)); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1276 | } |
| 1277 | |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1278 | /* No use! */ |
| 1279 | #if 0 |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1280 | struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB) |
| 1281 | { |
| 1282 | struct drm_connector *connector = NULL; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1283 | struct intel_sdvo *iout = NULL; |
| 1284 | struct intel_sdvo *sdvo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1285 | |
| 1286 | /* find the sdvo connector */ |
| 1287 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1288 | iout = to_intel_sdvo(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1289 | |
| 1290 | if (iout->type != INTEL_OUTPUT_SDVO) |
| 1291 | continue; |
| 1292 | |
| 1293 | sdvo = iout->dev_priv; |
| 1294 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1295 | if (sdvo->sdvo_reg == SDVOB && sdvoB) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1296 | return connector; |
| 1297 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 1298 | if (sdvo->sdvo_reg == SDVOC && !sdvoB) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1299 | return connector; |
| 1300 | |
| 1301 | } |
| 1302 | |
| 1303 | return NULL; |
| 1304 | } |
| 1305 | |
| 1306 | int intel_sdvo_supports_hotplug(struct drm_connector *connector) |
| 1307 | { |
| 1308 | u8 response[2]; |
| 1309 | u8 status; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1310 | struct intel_sdvo *intel_sdvo; |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 1311 | DRM_DEBUG_KMS("\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1312 | |
| 1313 | if (!connector) |
| 1314 | return 0; |
| 1315 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1316 | intel_sdvo = to_intel_sdvo(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1317 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1318 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, |
| 1319 | &response, 2) && response[0]; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1320 | } |
| 1321 | |
| 1322 | void intel_sdvo_set_hotplug(struct drm_connector *connector, int on) |
| 1323 | { |
| 1324 | u8 response[2]; |
| 1325 | u8 status; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1326 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1327 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1328 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); |
| 1329 | intel_sdvo_read_response(intel_sdvo, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1330 | |
| 1331 | if (on) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1332 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0); |
| 1333 | status = intel_sdvo_read_response(intel_sdvo, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1334 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1335 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1336 | } else { |
| 1337 | response[0] = 0; |
| 1338 | response[1] = 0; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1339 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1340 | } |
| 1341 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1342 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0); |
| 1343 | intel_sdvo_read_response(intel_sdvo, &response, 2); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1344 | } |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1345 | #endif |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1346 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1347 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1348 | intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1349 | { |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1350 | int caps = 0; |
| 1351 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1352 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1353 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) |
| 1354 | caps++; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1355 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1356 | (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)) |
| 1357 | caps++; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1358 | if (intel_sdvo->caps.output_flags & |
Roel Kluin | 19e1f88 | 2009-08-09 13:50:53 +0200 | [diff] [blame] | 1359 | (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1)) |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1360 | caps++; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1361 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1362 | (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1)) |
| 1363 | caps++; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1364 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1365 | (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1)) |
| 1366 | caps++; |
| 1367 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1368 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1369 | (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1)) |
| 1370 | caps++; |
| 1371 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1372 | if (intel_sdvo->caps.output_flags & |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1373 | (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)) |
| 1374 | caps++; |
| 1375 | |
| 1376 | return (caps > 1); |
| 1377 | } |
| 1378 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1379 | static struct edid * |
| 1380 | intel_sdvo_get_edid(struct drm_connector *connector, int ddc) |
| 1381 | { |
| 1382 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
| 1383 | int ret; |
| 1384 | |
| 1385 | ret = intel_sdvo_set_control_bus_switch(intel_sdvo, ddc); |
| 1386 | if (ret) |
| 1387 | return NULL; |
| 1388 | |
| 1389 | return drm_get_edid(connector, intel_sdvo->i2c); |
| 1390 | } |
| 1391 | |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1392 | static struct drm_connector * |
| 1393 | intel_find_analog_connector(struct drm_device *dev) |
| 1394 | { |
| 1395 | struct drm_connector *connector; |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1396 | struct intel_sdvo *encoder; |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1397 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1398 | list_for_each_entry(encoder, |
| 1399 | &dev->mode_config.encoder_list, |
| 1400 | base.base.head) { |
| 1401 | if (encoder->base.type == INTEL_OUTPUT_ANALOG) { |
| 1402 | list_for_each_entry(connector, |
| 1403 | &dev->mode_config.connector_list, |
| 1404 | head) { |
| 1405 | if (&encoder->base == |
| 1406 | intel_attached_encoder(connector)) |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1407 | return connector; |
| 1408 | } |
| 1409 | } |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1410 | } |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1411 | |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1412 | return NULL; |
| 1413 | } |
| 1414 | |
| 1415 | static int |
| 1416 | intel_analog_is_connected(struct drm_device *dev) |
| 1417 | { |
| 1418 | struct drm_connector *analog_connector; |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1419 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1420 | analog_connector = intel_find_analog_connector(dev); |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1421 | if (!analog_connector) |
| 1422 | return false; |
| 1423 | |
Chris Wilson | 930a9e2 | 2010-09-14 11:07:23 +0100 | [diff] [blame] | 1424 | if (analog_connector->funcs->detect(analog_connector, false) == |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1425 | connector_status_disconnected) |
| 1426 | return false; |
| 1427 | |
| 1428 | return true; |
| 1429 | } |
| 1430 | |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1431 | /* Mac mini hack -- use the same DDC as the analog connector */ |
| 1432 | static struct edid * |
| 1433 | intel_sdvo_get_analog_edid(struct drm_connector *connector) |
| 1434 | { |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1435 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1436 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1437 | if (!intel_analog_is_connected(connector->dev)) |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1438 | return NULL; |
| 1439 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1440 | return drm_get_edid(connector, &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter); |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1441 | } |
| 1442 | |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 1443 | enum drm_connector_status |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1444 | intel_sdvo_hdmi_sink_detect(struct drm_connector *connector) |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1445 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1446 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1447 | enum drm_connector_status status; |
| 1448 | struct edid *edid; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1449 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1450 | edid = intel_sdvo_get_edid(connector, intel_sdvo->ddc_bus); |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1451 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1452 | if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1453 | u8 ddc; |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1454 | |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1455 | /* |
| 1456 | * Don't use the 1 as the argument of DDC bus switch to get |
| 1457 | * the EDID. It is used for SDVO SPD ROM. |
| 1458 | */ |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1459 | for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1460 | edid = intel_sdvo_get_edid(connector, ddc); |
| 1461 | if (edid) { |
| 1462 | /* |
| 1463 | * If we found the EDID on the other bus, |
| 1464 | * assume that is the correct DDC bus. |
| 1465 | */ |
| 1466 | intel_sdvo->ddc_bus = ddc; |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1467 | break; |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1468 | } |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1469 | } |
Zhao Yakui | 7c3f0a2 | 2010-01-08 10:58:20 +0800 | [diff] [blame] | 1470 | } |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1471 | |
| 1472 | /* |
| 1473 | * When there is no edid and no monitor is connected with VGA |
| 1474 | * port, try to use the CRT ddc to read the EDID for DVI-connector. |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1475 | */ |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1476 | if (edid == NULL) |
| 1477 | edid = intel_sdvo_get_analog_edid(connector); |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1478 | |
Chris Wilson | 2f551c8 | 2010-09-15 10:42:50 +0100 | [diff] [blame] | 1479 | status = connector_status_unknown; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1480 | if (edid != NULL) { |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1481 | /* DDC bus is shared, match EDID to connector type */ |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1482 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
| 1483 | status = connector_status_connected; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1484 | intel_sdvo->is_hdmi = drm_detect_hdmi_monitor(edid); |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1485 | } |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1486 | connector->display_info.raw_edid = NULL; |
Chris Wilson | 9d1a903 | 2010-09-14 17:58:19 +0100 | [diff] [blame] | 1487 | kfree(edid); |
| 1488 | } |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1489 | |
ling.ma@intel.com | 2b8d33f7 | 2009-07-29 11:31:18 +0800 | [diff] [blame] | 1490 | return status; |
Ma Ling | 9dff6af | 2009-04-02 13:13:26 +0800 | [diff] [blame] | 1491 | } |
| 1492 | |
Chris Wilson | 7b334fc | 2010-09-09 23:51:02 +0100 | [diff] [blame] | 1493 | static enum drm_connector_status |
Chris Wilson | 930a9e2 | 2010-09-14 11:07:23 +0100 | [diff] [blame] | 1494 | intel_sdvo_detect(struct drm_connector *connector, bool force) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1495 | { |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1496 | uint16_t response; |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1497 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1498 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1499 | enum drm_connector_status ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1500 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1501 | if (!intel_sdvo_write_cmd(intel_sdvo, |
| 1502 | SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0)) |
| 1503 | return connector_status_unknown; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1504 | if (intel_sdvo->is_tv) { |
Zhao Yakui | d09c23d | 2009-11-06 15:39:56 +0800 | [diff] [blame] | 1505 | /* add 30ms delay when the output type is SDVO-TV */ |
| 1506 | mdelay(30); |
| 1507 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1508 | if (!intel_sdvo_read_response(intel_sdvo, &response, 2)) |
| 1509 | return connector_status_unknown; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1510 | |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 1511 | DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1512 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1513 | if (response == 0) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1514 | return connector_status_disconnected; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1515 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1516 | intel_sdvo->attached_output = response; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1517 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1518 | if ((intel_sdvo_connector->output_flag & response) == 0) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1519 | ret = connector_status_disconnected; |
Adam Jackson | 149c36a | 2010-04-29 14:05:18 -0400 | [diff] [blame] | 1520 | else if (response & SDVO_TMDS_MASK) |
| 1521 | ret = intel_sdvo_hdmi_sink_detect(connector); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1522 | else |
| 1523 | ret = connector_status_connected; |
| 1524 | |
| 1525 | /* May update encoder flag for like clock for SDVO TV, etc.*/ |
| 1526 | if (ret == connector_status_connected) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1527 | intel_sdvo->is_tv = false; |
| 1528 | intel_sdvo->is_lvds = false; |
| 1529 | intel_sdvo->base.needs_tv_clock = false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1530 | |
| 1531 | if (response & SDVO_TV_MASK) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1532 | intel_sdvo->is_tv = true; |
| 1533 | intel_sdvo->base.needs_tv_clock = true; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1534 | } |
| 1535 | if (response & SDVO_LVDS_MASK) |
Chris Wilson | 8545423 | 2010-08-08 14:28:23 +0100 | [diff] [blame] | 1536 | intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 1537 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 1538 | |
| 1539 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1540 | } |
| 1541 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1542 | static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1543 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1544 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1545 | struct edid *edid; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1546 | |
| 1547 | /* set the bus switch and get the modes */ |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1548 | edid = intel_sdvo_get_edid(connector, intel_sdvo->ddc_bus); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1549 | |
Keith Packard | 57cdaf9 | 2009-09-04 13:07:54 +0800 | [diff] [blame] | 1550 | /* |
| 1551 | * Mac mini hack. On this device, the DVI-I connector shares one DDC |
| 1552 | * link between analog and digital outputs. So, if the regular SDVO |
| 1553 | * DDC fails, check to see if the analog output is disconnected, in |
| 1554 | * which case we'll look there for the digital DDC data. |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1555 | */ |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1556 | if (edid == NULL) |
| 1557 | edid = intel_sdvo_get_analog_edid(connector); |
| 1558 | |
Chris Wilson | ff482d8 | 2010-09-15 10:40:38 +0100 | [diff] [blame] | 1559 | if (edid != NULL) { |
| 1560 | drm_mode_connector_update_edid_property(connector, edid); |
| 1561 | drm_add_edid_modes(connector, edid); |
| 1562 | connector->display_info.raw_edid = NULL; |
| 1563 | kfree(edid); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1564 | } |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1565 | } |
| 1566 | |
| 1567 | /* |
| 1568 | * Set of SDVO TV modes. |
| 1569 | * Note! This is in reply order (see loop in get_tv_modes). |
| 1570 | * XXX: all 60Hz refresh? |
| 1571 | */ |
| 1572 | struct drm_display_mode sdvo_tv_modes[] = { |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1573 | { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, |
| 1574 | 416, 0, 200, 201, 232, 233, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1575 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1576 | { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, |
| 1577 | 416, 0, 240, 241, 272, 273, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1578 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1579 | { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, |
| 1580 | 496, 0, 300, 301, 332, 333, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1581 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1582 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, |
| 1583 | 736, 0, 350, 351, 382, 383, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1584 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1585 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, |
| 1586 | 736, 0, 400, 401, 432, 433, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1587 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1588 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, |
| 1589 | 736, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1590 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1591 | { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, |
| 1592 | 800, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1593 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1594 | { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, |
| 1595 | 800, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1596 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1597 | { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, |
| 1598 | 816, 0, 350, 351, 382, 383, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1599 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1600 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, |
| 1601 | 816, 0, 400, 401, 432, 433, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1602 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1603 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, |
| 1604 | 816, 0, 480, 481, 512, 513, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1605 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1606 | { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, |
| 1607 | 816, 0, 540, 541, 572, 573, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1608 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1609 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, |
| 1610 | 816, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1611 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1612 | { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, |
| 1613 | 864, 0, 576, 577, 608, 609, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1614 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1615 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, |
| 1616 | 896, 0, 600, 601, 632, 633, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1617 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1618 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, |
| 1619 | 928, 0, 624, 625, 656, 657, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1620 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1621 | { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, |
| 1622 | 1016, 0, 766, 767, 798, 799, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1623 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1624 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, |
| 1625 | 1120, 0, 768, 769, 800, 801, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1626 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1627 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, |
| 1628 | 1376, 0, 1024, 1025, 1056, 1057, 0, |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1629 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
| 1630 | }; |
| 1631 | |
| 1632 | static void intel_sdvo_get_tv_modes(struct drm_connector *connector) |
| 1633 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1634 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1635 | struct intel_sdvo_sdtv_resolution_request tv_res; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1636 | uint32_t reply = 0, format_map = 0; |
| 1637 | int i; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1638 | |
| 1639 | /* Read the list of supported input resolutions for the selected TV |
| 1640 | * format. |
| 1641 | */ |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 1642 | format_map = 1 << intel_sdvo->tv_format_index; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1643 | memcpy(&tv_res, &format_map, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1644 | min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1645 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1646 | if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) |
| 1647 | return; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1648 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1649 | BUILD_BUG_ON(sizeof(tv_res) != 3); |
| 1650 | if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, |
| 1651 | &tv_res, sizeof(tv_res))) |
| 1652 | return; |
| 1653 | if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1654 | return; |
| 1655 | |
| 1656 | for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1657 | if (reply & (1 << i)) { |
| 1658 | struct drm_display_mode *nmode; |
| 1659 | nmode = drm_mode_duplicate(connector->dev, |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1660 | &sdvo_tv_modes[i]); |
Zhenyu Wang | 7026d4a | 2009-03-24 14:02:43 +0800 | [diff] [blame] | 1661 | if (nmode) |
| 1662 | drm_mode_probed_add(connector, nmode); |
| 1663 | } |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1664 | } |
| 1665 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1666 | static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) |
| 1667 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1668 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1669 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1670 | struct drm_display_mode *newmode; |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1671 | |
| 1672 | /* |
| 1673 | * Attempt to get the mode list from DDC. |
| 1674 | * Assume that the preferred modes are |
| 1675 | * arranged in priority order. |
| 1676 | */ |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 1677 | intel_ddc_get_modes(connector, intel_sdvo->i2c); |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1678 | if (list_empty(&connector->probed_modes) == false) |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1679 | goto end; |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1680 | |
| 1681 | /* Fetch modes from VBT */ |
| 1682 | if (dev_priv->sdvo_lvds_vbt_mode != NULL) { |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1683 | newmode = drm_mode_duplicate(connector->dev, |
| 1684 | dev_priv->sdvo_lvds_vbt_mode); |
| 1685 | if (newmode != NULL) { |
| 1686 | /* Guarantee the mode is preferred */ |
| 1687 | newmode->type = (DRM_MODE_TYPE_PREFERRED | |
| 1688 | DRM_MODE_TYPE_DRIVER); |
| 1689 | drm_mode_probed_add(connector, newmode); |
| 1690 | } |
| 1691 | } |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1692 | |
| 1693 | end: |
| 1694 | list_for_each_entry(newmode, &connector->probed_modes, head) { |
| 1695 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1696 | intel_sdvo->sdvo_lvds_fixed_mode = |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1697 | drm_mode_duplicate(connector->dev, newmode); |
Chris Wilson | 6c9547f | 2010-08-25 10:05:17 +0100 | [diff] [blame] | 1698 | |
| 1699 | drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode, |
| 1700 | 0); |
| 1701 | |
Chris Wilson | 8545423 | 2010-08-08 14:28:23 +0100 | [diff] [blame] | 1702 | intel_sdvo->is_lvds = true; |
ling.ma@intel.com | 12682a9 | 2009-06-30 11:35:35 +0800 | [diff] [blame] | 1703 | break; |
| 1704 | } |
| 1705 | } |
| 1706 | |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1707 | } |
| 1708 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1709 | static int intel_sdvo_get_modes(struct drm_connector *connector) |
| 1710 | { |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1711 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1712 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1713 | if (IS_TV(intel_sdvo_connector)) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1714 | intel_sdvo_get_tv_modes(connector); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1715 | else if (IS_LVDS(intel_sdvo_connector)) |
Ma Ling | 7086c87 | 2009-05-13 11:20:06 +0800 | [diff] [blame] | 1716 | intel_sdvo_get_lvds_modes(connector); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1717 | else |
| 1718 | intel_sdvo_get_ddc_modes(connector); |
| 1719 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1720 | return !list_empty(&connector->probed_modes); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1721 | } |
| 1722 | |
Chris Wilson | fcc8d67 | 2010-08-04 13:50:27 +0100 | [diff] [blame] | 1723 | static void |
| 1724 | intel_sdvo_destroy_enhance_property(struct drm_connector *connector) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1725 | { |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1726 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1727 | struct drm_device *dev = connector->dev; |
| 1728 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1729 | if (intel_sdvo_connector->left) |
| 1730 | drm_property_destroy(dev, intel_sdvo_connector->left); |
| 1731 | if (intel_sdvo_connector->right) |
| 1732 | drm_property_destroy(dev, intel_sdvo_connector->right); |
| 1733 | if (intel_sdvo_connector->top) |
| 1734 | drm_property_destroy(dev, intel_sdvo_connector->top); |
| 1735 | if (intel_sdvo_connector->bottom) |
| 1736 | drm_property_destroy(dev, intel_sdvo_connector->bottom); |
| 1737 | if (intel_sdvo_connector->hpos) |
| 1738 | drm_property_destroy(dev, intel_sdvo_connector->hpos); |
| 1739 | if (intel_sdvo_connector->vpos) |
| 1740 | drm_property_destroy(dev, intel_sdvo_connector->vpos); |
| 1741 | if (intel_sdvo_connector->saturation) |
| 1742 | drm_property_destroy(dev, intel_sdvo_connector->saturation); |
| 1743 | if (intel_sdvo_connector->contrast) |
| 1744 | drm_property_destroy(dev, intel_sdvo_connector->contrast); |
| 1745 | if (intel_sdvo_connector->hue) |
| 1746 | drm_property_destroy(dev, intel_sdvo_connector->hue); |
| 1747 | if (intel_sdvo_connector->sharpness) |
| 1748 | drm_property_destroy(dev, intel_sdvo_connector->sharpness); |
| 1749 | if (intel_sdvo_connector->flicker_filter) |
| 1750 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter); |
| 1751 | if (intel_sdvo_connector->flicker_filter_2d) |
| 1752 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d); |
| 1753 | if (intel_sdvo_connector->flicker_filter_adaptive) |
| 1754 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive); |
| 1755 | if (intel_sdvo_connector->tv_luma_filter) |
| 1756 | drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter); |
| 1757 | if (intel_sdvo_connector->tv_chroma_filter) |
| 1758 | drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter); |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 1759 | if (intel_sdvo_connector->dot_crawl) |
| 1760 | drm_property_destroy(dev, intel_sdvo_connector->dot_crawl); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1761 | if (intel_sdvo_connector->brightness) |
| 1762 | drm_property_destroy(dev, intel_sdvo_connector->brightness); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1763 | } |
| 1764 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1765 | static void intel_sdvo_destroy(struct drm_connector *connector) |
| 1766 | { |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1767 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1768 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1769 | if (intel_sdvo_connector->tv_format) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1770 | drm_property_destroy(connector->dev, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1771 | intel_sdvo_connector->tv_format); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1772 | |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1773 | intel_sdvo_destroy_enhance_property(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1774 | drm_sysfs_connector_remove(connector); |
| 1775 | drm_connector_cleanup(connector); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1776 | kfree(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1777 | } |
| 1778 | |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1779 | static int |
| 1780 | intel_sdvo_set_property(struct drm_connector *connector, |
| 1781 | struct drm_property *property, |
| 1782 | uint64_t val) |
| 1783 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1784 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1785 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1786 | uint16_t temp_value; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1787 | uint8_t cmd; |
| 1788 | int ret; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1789 | |
| 1790 | ret = drm_connector_property_set_value(connector, property, val); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1791 | if (ret) |
| 1792 | return ret; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1793 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1794 | #define CHECK_PROPERTY(name, NAME) \ |
| 1795 | if (intel_sdvo_connector->name == property) { \ |
| 1796 | if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ |
| 1797 | if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ |
| 1798 | cmd = SDVO_CMD_SET_##NAME; \ |
| 1799 | intel_sdvo_connector->cur_##name = temp_value; \ |
| 1800 | goto set_value; \ |
| 1801 | } |
| 1802 | |
| 1803 | if (property == intel_sdvo_connector->tv_format) { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1804 | if (val >= TV_FORMAT_NUM) |
| 1805 | return -EINVAL; |
| 1806 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 1807 | if (intel_sdvo->tv_format_index == |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1808 | intel_sdvo_connector->tv_format_supported[val]) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1809 | return 0; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1810 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 1811 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1812 | goto done; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1813 | } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1814 | temp_value = val; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1815 | if (intel_sdvo_connector->left == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1816 | drm_connector_property_set_value(connector, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1817 | intel_sdvo_connector->right, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1818 | if (intel_sdvo_connector->left_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1819 | return 0; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1820 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1821 | intel_sdvo_connector->left_margin = temp_value; |
| 1822 | intel_sdvo_connector->right_margin = temp_value; |
| 1823 | temp_value = intel_sdvo_connector->max_hscan - |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1824 | intel_sdvo_connector->left_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1825 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1826 | goto set_value; |
| 1827 | } else if (intel_sdvo_connector->right == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1828 | drm_connector_property_set_value(connector, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1829 | intel_sdvo_connector->left, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1830 | if (intel_sdvo_connector->right_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1831 | return 0; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1832 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1833 | intel_sdvo_connector->left_margin = temp_value; |
| 1834 | intel_sdvo_connector->right_margin = temp_value; |
| 1835 | temp_value = intel_sdvo_connector->max_hscan - |
| 1836 | intel_sdvo_connector->left_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1837 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1838 | goto set_value; |
| 1839 | } else if (intel_sdvo_connector->top == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1840 | drm_connector_property_set_value(connector, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1841 | intel_sdvo_connector->bottom, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1842 | if (intel_sdvo_connector->top_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1843 | return 0; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1844 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1845 | intel_sdvo_connector->top_margin = temp_value; |
| 1846 | intel_sdvo_connector->bottom_margin = temp_value; |
| 1847 | temp_value = intel_sdvo_connector->max_vscan - |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1848 | intel_sdvo_connector->top_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1849 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1850 | goto set_value; |
| 1851 | } else if (intel_sdvo_connector->bottom == property) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1852 | drm_connector_property_set_value(connector, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1853 | intel_sdvo_connector->top, val); |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1854 | if (intel_sdvo_connector->bottom_margin == temp_value) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1855 | return 0; |
| 1856 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 1857 | intel_sdvo_connector->top_margin = temp_value; |
| 1858 | intel_sdvo_connector->bottom_margin = temp_value; |
| 1859 | temp_value = intel_sdvo_connector->max_vscan - |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1860 | intel_sdvo_connector->top_margin; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1861 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1862 | goto set_value; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1863 | } |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1864 | CHECK_PROPERTY(hpos, HPOS) |
| 1865 | CHECK_PROPERTY(vpos, VPOS) |
| 1866 | CHECK_PROPERTY(saturation, SATURATION) |
| 1867 | CHECK_PROPERTY(contrast, CONTRAST) |
| 1868 | CHECK_PROPERTY(hue, HUE) |
| 1869 | CHECK_PROPERTY(brightness, BRIGHTNESS) |
| 1870 | CHECK_PROPERTY(sharpness, SHARPNESS) |
| 1871 | CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) |
| 1872 | CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) |
| 1873 | CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) |
| 1874 | CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) |
| 1875 | CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 1876 | CHECK_PROPERTY(dot_crawl, DOT_CRAWL) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 1877 | } |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1878 | |
| 1879 | return -EINVAL; /* unknown property */ |
| 1880 | |
| 1881 | set_value: |
| 1882 | if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) |
| 1883 | return -EIO; |
| 1884 | |
| 1885 | |
| 1886 | done: |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1887 | if (intel_sdvo->base.base.crtc) { |
| 1888 | struct drm_crtc *crtc = intel_sdvo->base.base.crtc; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1889 | drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1890 | crtc->y, crtc->fb); |
| 1891 | } |
| 1892 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1893 | return 0; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 1894 | #undef CHECK_PROPERTY |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1895 | } |
| 1896 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1897 | static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = { |
| 1898 | .dpms = intel_sdvo_dpms, |
| 1899 | .mode_fixup = intel_sdvo_mode_fixup, |
| 1900 | .prepare = intel_encoder_prepare, |
| 1901 | .mode_set = intel_sdvo_mode_set, |
| 1902 | .commit = intel_encoder_commit, |
| 1903 | }; |
| 1904 | |
| 1905 | static const struct drm_connector_funcs intel_sdvo_connector_funcs = { |
Keith Packard | c9fb15f | 2009-05-30 20:42:28 -0700 | [diff] [blame] | 1906 | .dpms = drm_helper_connector_dpms, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1907 | .detect = intel_sdvo_detect, |
| 1908 | .fill_modes = drm_helper_probe_single_connector_modes, |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 1909 | .set_property = intel_sdvo_set_property, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1910 | .destroy = intel_sdvo_destroy, |
| 1911 | }; |
| 1912 | |
| 1913 | static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { |
| 1914 | .get_modes = intel_sdvo_get_modes, |
| 1915 | .mode_valid = intel_sdvo_mode_valid, |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 1916 | .best_encoder = intel_best_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1917 | }; |
| 1918 | |
Hannes Eder | b358d0a | 2008-12-18 21:18:47 +0100 | [diff] [blame] | 1919 | static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1920 | { |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 1921 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1922 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1923 | if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1924 | drm_mode_destroy(encoder->dev, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1925 | intel_sdvo->sdvo_lvds_fixed_mode); |
Zhenyu Wang | d2a82a6 | 2010-03-29 21:22:55 +0800 | [diff] [blame] | 1926 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1927 | intel_encoder_destroy(encoder); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1928 | } |
| 1929 | |
| 1930 | static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { |
| 1931 | .destroy = intel_sdvo_enc_destroy, |
| 1932 | }; |
| 1933 | |
Chris Wilson | b66d842 | 2010-08-12 15:26:41 +0100 | [diff] [blame] | 1934 | static void |
| 1935 | intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) |
| 1936 | { |
| 1937 | uint16_t mask = 0; |
| 1938 | unsigned int num_bits; |
| 1939 | |
| 1940 | /* Make a mask of outputs less than or equal to our own priority in the |
| 1941 | * list. |
| 1942 | */ |
| 1943 | switch (sdvo->controlled_output) { |
| 1944 | case SDVO_OUTPUT_LVDS1: |
| 1945 | mask |= SDVO_OUTPUT_LVDS1; |
| 1946 | case SDVO_OUTPUT_LVDS0: |
| 1947 | mask |= SDVO_OUTPUT_LVDS0; |
| 1948 | case SDVO_OUTPUT_TMDS1: |
| 1949 | mask |= SDVO_OUTPUT_TMDS1; |
| 1950 | case SDVO_OUTPUT_TMDS0: |
| 1951 | mask |= SDVO_OUTPUT_TMDS0; |
| 1952 | case SDVO_OUTPUT_RGB1: |
| 1953 | mask |= SDVO_OUTPUT_RGB1; |
| 1954 | case SDVO_OUTPUT_RGB0: |
| 1955 | mask |= SDVO_OUTPUT_RGB0; |
| 1956 | break; |
| 1957 | } |
| 1958 | |
| 1959 | /* Count bits to find what number we are in the priority list. */ |
| 1960 | mask &= sdvo->caps.output_flags; |
| 1961 | num_bits = hweight16(mask); |
| 1962 | /* If more than 3 outputs, default to DDC bus 3 for now. */ |
| 1963 | if (num_bits > 3) |
| 1964 | num_bits = 3; |
| 1965 | |
| 1966 | /* Corresponds to SDVO_CONTROL_BUS_DDCx */ |
| 1967 | sdvo->ddc_bus = 1 << num_bits; |
| 1968 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1969 | |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1970 | /** |
| 1971 | * Choose the appropriate DDC bus for control bus switch command for this |
| 1972 | * SDVO output based on the controlled output. |
| 1973 | * |
| 1974 | * DDC bus number assignment is in a priority order of RGB outputs, then TMDS |
| 1975 | * outputs, then LVDS outputs. |
| 1976 | */ |
| 1977 | static void |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 1978 | intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1979 | struct intel_sdvo *sdvo, u32 reg) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1980 | { |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 1981 | struct sdvo_device_mapping *mapping; |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1982 | |
Adam Jackson | b108333 | 2010-04-23 16:07:40 -0400 | [diff] [blame] | 1983 | if (IS_SDVOB(reg)) |
| 1984 | mapping = &(dev_priv->sdvo_mappings[0]); |
| 1985 | else |
| 1986 | mapping = &(dev_priv->sdvo_mappings[1]); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1987 | |
Chris Wilson | b66d842 | 2010-08-12 15:26:41 +0100 | [diff] [blame] | 1988 | if (mapping->initialized) |
| 1989 | sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); |
| 1990 | else |
| 1991 | intel_sdvo_guess_ddc_bus(sdvo); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1992 | } |
| 1993 | |
| 1994 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1995 | intel_sdvo_get_digital_encoding_mode(struct intel_sdvo *intel_sdvo, int device) |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 1996 | { |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 1997 | return intel_sdvo_set_target_output(intel_sdvo, |
| 1998 | device == 0 ? SDVO_OUTPUT_TMDS0 : SDVO_OUTPUT_TMDS1) && |
| 1999 | intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, |
| 2000 | &intel_sdvo->is_hdmi, 1); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2001 | } |
| 2002 | |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2003 | static u8 |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 2004 | intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg) |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2005 | { |
| 2006 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2007 | struct sdvo_device_mapping *my_mapping, *other_mapping; |
| 2008 | |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 2009 | if (IS_SDVOB(sdvo_reg)) { |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2010 | my_mapping = &dev_priv->sdvo_mappings[0]; |
| 2011 | other_mapping = &dev_priv->sdvo_mappings[1]; |
| 2012 | } else { |
| 2013 | my_mapping = &dev_priv->sdvo_mappings[1]; |
| 2014 | other_mapping = &dev_priv->sdvo_mappings[0]; |
| 2015 | } |
| 2016 | |
| 2017 | /* If the BIOS described our SDVO device, take advantage of it. */ |
| 2018 | if (my_mapping->slave_addr) |
| 2019 | return my_mapping->slave_addr; |
| 2020 | |
| 2021 | /* If the BIOS only described a different SDVO device, use the |
| 2022 | * address that it isn't using. |
| 2023 | */ |
| 2024 | if (other_mapping->slave_addr) { |
| 2025 | if (other_mapping->slave_addr == 0x70) |
| 2026 | return 0x72; |
| 2027 | else |
| 2028 | return 0x70; |
| 2029 | } |
| 2030 | |
| 2031 | /* No SDVO device info is found for another DVO port, |
| 2032 | * so use mapping assumption we had before BIOS parsing. |
| 2033 | */ |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 2034 | if (IS_SDVOB(sdvo_reg)) |
yakui_zhao | 714605e | 2009-05-31 17:18:07 +0800 | [diff] [blame] | 2035 | return 0x70; |
| 2036 | else |
| 2037 | return 0x72; |
| 2038 | } |
| 2039 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2040 | static void |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2041 | intel_sdvo_connector_init(struct intel_sdvo_connector *connector, |
| 2042 | struct intel_sdvo *encoder) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2043 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2044 | drm_connector_init(encoder->base.base.dev, |
| 2045 | &connector->base.base, |
| 2046 | &intel_sdvo_connector_funcs, |
| 2047 | connector->base.base.connector_type); |
Zhao Yakui | 6070a4a | 2010-02-08 21:35:12 +0800 | [diff] [blame] | 2048 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2049 | drm_connector_helper_add(&connector->base.base, |
| 2050 | &intel_sdvo_connector_helper_funcs); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2051 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2052 | connector->base.base.interlace_allowed = 0; |
| 2053 | connector->base.base.doublescan_allowed = 0; |
| 2054 | connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2055 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2056 | intel_connector_attach_encoder(&connector->base, &encoder->base); |
| 2057 | drm_sysfs_connector_add(&connector->base.base); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2058 | } |
| 2059 | |
| 2060 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2061 | intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2062 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2063 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2064 | struct drm_connector *connector; |
| 2065 | struct intel_connector *intel_connector; |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2066 | struct intel_sdvo_connector *intel_sdvo_connector; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2067 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2068 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
| 2069 | if (!intel_sdvo_connector) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2070 | return false; |
| 2071 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2072 | if (device == 0) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2073 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2074 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2075 | } else if (device == 1) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2076 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2077 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2078 | } |
| 2079 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2080 | intel_connector = &intel_sdvo_connector->base; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2081 | connector = &intel_connector->base; |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 2082 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2083 | encoder->encoder_type = DRM_MODE_ENCODER_TMDS; |
| 2084 | connector->connector_type = DRM_MODE_CONNECTOR_DVID; |
| 2085 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2086 | if (intel_sdvo_get_supp_encode(intel_sdvo, &intel_sdvo->encode) |
| 2087 | && intel_sdvo_get_digital_encoding_mode(intel_sdvo, device) |
| 2088 | && intel_sdvo->is_hdmi) { |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2089 | /* enable hdmi encoding mode if supported */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2090 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); |
| 2091 | intel_sdvo_set_colorimetry(intel_sdvo, |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2092 | SDVO_COLORIMETRY_RGB256); |
| 2093 | connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; |
| 2094 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2095 | intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | |
| 2096 | (1 << INTEL_ANALOG_CLONE_BIT)); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2097 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2098 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2099 | |
| 2100 | return true; |
| 2101 | } |
| 2102 | |
| 2103 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2104 | intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2105 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2106 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
| 2107 | struct drm_connector *connector; |
| 2108 | struct intel_connector *intel_connector; |
| 2109 | struct intel_sdvo_connector *intel_sdvo_connector; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2110 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2111 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
| 2112 | if (!intel_sdvo_connector) |
| 2113 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2114 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2115 | intel_connector = &intel_sdvo_connector->base; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2116 | connector = &intel_connector->base; |
| 2117 | encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; |
| 2118 | connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2119 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2120 | intel_sdvo->controlled_output |= type; |
| 2121 | intel_sdvo_connector->output_flag = type; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2122 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2123 | intel_sdvo->is_tv = true; |
| 2124 | intel_sdvo->base.needs_tv_clock = true; |
| 2125 | intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2126 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2127 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2128 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2129 | if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2130 | goto err; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2131 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2132 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2133 | goto err; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2134 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2135 | return true; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2136 | |
| 2137 | err: |
Chris Wilson | fcc8d67 | 2010-08-04 13:50:27 +0100 | [diff] [blame] | 2138 | intel_sdvo_destroy_enhance_property(connector); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2139 | kfree(intel_sdvo_connector); |
| 2140 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2141 | } |
| 2142 | |
| 2143 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2144 | intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2145 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2146 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
| 2147 | struct drm_connector *connector; |
| 2148 | struct intel_connector *intel_connector; |
| 2149 | struct intel_sdvo_connector *intel_sdvo_connector; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2150 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2151 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
| 2152 | if (!intel_sdvo_connector) |
| 2153 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2154 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2155 | intel_connector = &intel_sdvo_connector->base; |
| 2156 | connector = &intel_connector->base; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2157 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
| 2158 | encoder->encoder_type = DRM_MODE_ENCODER_DAC; |
| 2159 | connector->connector_type = DRM_MODE_CONNECTOR_VGA; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2160 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2161 | if (device == 0) { |
| 2162 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; |
| 2163 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; |
| 2164 | } else if (device == 1) { |
| 2165 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; |
| 2166 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; |
| 2167 | } |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2168 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2169 | intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | |
| 2170 | (1 << INTEL_ANALOG_CLONE_BIT)); |
| 2171 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2172 | intel_sdvo_connector_init(intel_sdvo_connector, |
| 2173 | intel_sdvo); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2174 | return true; |
| 2175 | } |
| 2176 | |
| 2177 | static bool |
| 2178 | intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) |
| 2179 | { |
| 2180 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
| 2181 | struct drm_connector *connector; |
| 2182 | struct intel_connector *intel_connector; |
| 2183 | struct intel_sdvo_connector *intel_sdvo_connector; |
| 2184 | |
| 2185 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
| 2186 | if (!intel_sdvo_connector) |
| 2187 | return false; |
| 2188 | |
| 2189 | intel_connector = &intel_sdvo_connector->base; |
| 2190 | connector = &intel_connector->base; |
| 2191 | encoder->encoder_type = DRM_MODE_ENCODER_LVDS; |
| 2192 | connector->connector_type = DRM_MODE_CONNECTOR_LVDS; |
| 2193 | |
| 2194 | if (device == 0) { |
| 2195 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; |
| 2196 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; |
| 2197 | } else if (device == 1) { |
| 2198 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; |
| 2199 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; |
| 2200 | } |
| 2201 | |
| 2202 | intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2203 | (1 << INTEL_SDVO_LVDS_CLONE_BIT)); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2204 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2205 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2206 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2207 | goto err; |
| 2208 | |
| 2209 | return true; |
| 2210 | |
| 2211 | err: |
Chris Wilson | fcc8d67 | 2010-08-04 13:50:27 +0100 | [diff] [blame] | 2212 | intel_sdvo_destroy_enhance_property(connector); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2213 | kfree(intel_sdvo_connector); |
| 2214 | return false; |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2215 | } |
Zhao Yakui | 6070a4a | 2010-02-08 21:35:12 +0800 | [diff] [blame] | 2216 | |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2217 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2218 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2219 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2220 | intel_sdvo->is_tv = false; |
| 2221 | intel_sdvo->base.needs_tv_clock = false; |
| 2222 | intel_sdvo->is_lvds = false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2223 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2224 | /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2225 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2226 | if (flags & SDVO_OUTPUT_TMDS0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2227 | if (!intel_sdvo_dvi_init(intel_sdvo, 0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2228 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2229 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2230 | if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2231 | if (!intel_sdvo_dvi_init(intel_sdvo, 1)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2232 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2233 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2234 | /* TV has no XXX1 function block */ |
Zhenyu Wang | a1f4b7ff | 2010-03-29 23:16:13 +0800 | [diff] [blame] | 2235 | if (flags & SDVO_OUTPUT_SVID0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2236 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2237 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2238 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2239 | if (flags & SDVO_OUTPUT_CVBS0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2240 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2241 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2242 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2243 | if (flags & SDVO_OUTPUT_RGB0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2244 | if (!intel_sdvo_analog_init(intel_sdvo, 0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2245 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2246 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2247 | if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2248 | if (!intel_sdvo_analog_init(intel_sdvo, 1)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2249 | return false; |
Zhao Yakui | 2dd8738 | 2010-01-27 16:32:46 +0800 | [diff] [blame] | 2250 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2251 | if (flags & SDVO_OUTPUT_LVDS0) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2252 | if (!intel_sdvo_lvds_init(intel_sdvo, 0)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2253 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2254 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2255 | if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2256 | if (!intel_sdvo_lvds_init(intel_sdvo, 1)) |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2257 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2258 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2259 | if ((flags & SDVO_OUTPUT_MASK) == 0) { |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2260 | unsigned char bytes[2]; |
| 2261 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2262 | intel_sdvo->controlled_output = 0; |
| 2263 | memcpy(bytes, &intel_sdvo->caps.output_flags, 2); |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 2264 | DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2265 | SDVO_NAME(intel_sdvo), |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 2266 | bytes[0], bytes[1]); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2267 | return false; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2268 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2269 | intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1); |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2270 | |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2271 | return true; |
ling.ma@intel.com | fb7a46f | 2009-07-23 17:11:34 +0800 | [diff] [blame] | 2272 | } |
| 2273 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2274 | static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
| 2275 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 2276 | int type) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2277 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2278 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2279 | struct intel_sdvo_tv_format format; |
| 2280 | uint32_t format_map, i; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2281 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2282 | if (!intel_sdvo_set_target_output(intel_sdvo, type)) |
| 2283 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2284 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2285 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2286 | SDVO_CMD_GET_SUPPORTED_TV_FORMATS, |
| 2287 | &format, sizeof(format))) |
| 2288 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2289 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2290 | memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2291 | |
| 2292 | if (format_map == 0) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2293 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2294 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2295 | intel_sdvo_connector->format_supported_num = 0; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2296 | for (i = 0 ; i < TV_FORMAT_NUM; i++) |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 2297 | if (format_map & (1 << i)) |
| 2298 | intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2299 | |
| 2300 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2301 | intel_sdvo_connector->tv_format = |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2302 | drm_property_create(dev, DRM_MODE_PROP_ENUM, |
| 2303 | "mode", intel_sdvo_connector->format_supported_num); |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2304 | if (!intel_sdvo_connector->tv_format) |
Chris Wilson | fcc8d67 | 2010-08-04 13:50:27 +0100 | [diff] [blame] | 2305 | return false; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2306 | |
Chris Wilson | 615fb93 | 2010-08-04 13:50:24 +0100 | [diff] [blame] | 2307 | for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2308 | drm_property_add_enum( |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2309 | intel_sdvo_connector->tv_format, i, |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 2310 | i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2311 | |
Chris Wilson | 4003975 | 2010-08-04 13:50:26 +0100 | [diff] [blame] | 2312 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2313 | drm_connector_attach_property(&intel_sdvo_connector->base.base, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2314 | intel_sdvo_connector->tv_format, 0); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2315 | return true; |
Zhao Yakui | ce6feab | 2009-08-24 13:50:26 +0800 | [diff] [blame] | 2316 | |
| 2317 | } |
| 2318 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2319 | #define ENHANCEMENT(name, NAME) do { \ |
| 2320 | if (enhancements.name) { \ |
| 2321 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ |
| 2322 | !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ |
| 2323 | return false; \ |
| 2324 | intel_sdvo_connector->max_##name = data_value[0]; \ |
| 2325 | intel_sdvo_connector->cur_##name = response; \ |
| 2326 | intel_sdvo_connector->name = \ |
| 2327 | drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \ |
| 2328 | if (!intel_sdvo_connector->name) return false; \ |
| 2329 | intel_sdvo_connector->name->values[0] = 0; \ |
| 2330 | intel_sdvo_connector->name->values[1] = data_value[0]; \ |
| 2331 | drm_connector_attach_property(connector, \ |
| 2332 | intel_sdvo_connector->name, \ |
| 2333 | intel_sdvo_connector->cur_##name); \ |
| 2334 | DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ |
| 2335 | data_value[0], data_value[1], response); \ |
| 2336 | } \ |
| 2337 | } while(0) |
| 2338 | |
| 2339 | static bool |
| 2340 | intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, |
| 2341 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 2342 | struct intel_sdvo_enhancements_reply enhancements) |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2343 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2344 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2345 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2346 | uint16_t response, data_value[2]; |
| 2347 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2348 | /* when horizontal overscan is supported, Add the left/right property */ |
| 2349 | if (enhancements.overscan_h) { |
| 2350 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2351 | SDVO_CMD_GET_MAX_OVERSCAN_H, |
| 2352 | &data_value, 4)) |
| 2353 | return false; |
| 2354 | |
| 2355 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2356 | SDVO_CMD_GET_OVERSCAN_H, |
| 2357 | &response, 2)) |
| 2358 | return false; |
| 2359 | |
| 2360 | intel_sdvo_connector->max_hscan = data_value[0]; |
| 2361 | intel_sdvo_connector->left_margin = data_value[0] - response; |
| 2362 | intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; |
| 2363 | intel_sdvo_connector->left = |
| 2364 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2365 | "left_margin", 2); |
| 2366 | if (!intel_sdvo_connector->left) |
| 2367 | return false; |
| 2368 | |
| 2369 | intel_sdvo_connector->left->values[0] = 0; |
| 2370 | intel_sdvo_connector->left->values[1] = data_value[0]; |
| 2371 | drm_connector_attach_property(connector, |
| 2372 | intel_sdvo_connector->left, |
| 2373 | intel_sdvo_connector->left_margin); |
| 2374 | |
| 2375 | intel_sdvo_connector->right = |
| 2376 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2377 | "right_margin", 2); |
| 2378 | if (!intel_sdvo_connector->right) |
| 2379 | return false; |
| 2380 | |
| 2381 | intel_sdvo_connector->right->values[0] = 0; |
| 2382 | intel_sdvo_connector->right->values[1] = data_value[0]; |
| 2383 | drm_connector_attach_property(connector, |
| 2384 | intel_sdvo_connector->right, |
| 2385 | intel_sdvo_connector->right_margin); |
| 2386 | DRM_DEBUG_KMS("h_overscan: max %d, " |
| 2387 | "default %d, current %d\n", |
| 2388 | data_value[0], data_value[1], response); |
| 2389 | } |
| 2390 | |
| 2391 | if (enhancements.overscan_v) { |
| 2392 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2393 | SDVO_CMD_GET_MAX_OVERSCAN_V, |
| 2394 | &data_value, 4)) |
| 2395 | return false; |
| 2396 | |
| 2397 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2398 | SDVO_CMD_GET_OVERSCAN_V, |
| 2399 | &response, 2)) |
| 2400 | return false; |
| 2401 | |
| 2402 | intel_sdvo_connector->max_vscan = data_value[0]; |
| 2403 | intel_sdvo_connector->top_margin = data_value[0] - response; |
| 2404 | intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; |
| 2405 | intel_sdvo_connector->top = |
| 2406 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2407 | "top_margin", 2); |
| 2408 | if (!intel_sdvo_connector->top) |
| 2409 | return false; |
| 2410 | |
| 2411 | intel_sdvo_connector->top->values[0] = 0; |
| 2412 | intel_sdvo_connector->top->values[1] = data_value[0]; |
| 2413 | drm_connector_attach_property(connector, |
| 2414 | intel_sdvo_connector->top, |
| 2415 | intel_sdvo_connector->top_margin); |
| 2416 | |
| 2417 | intel_sdvo_connector->bottom = |
| 2418 | drm_property_create(dev, DRM_MODE_PROP_RANGE, |
| 2419 | "bottom_margin", 2); |
| 2420 | if (!intel_sdvo_connector->bottom) |
| 2421 | return false; |
| 2422 | |
| 2423 | intel_sdvo_connector->bottom->values[0] = 0; |
| 2424 | intel_sdvo_connector->bottom->values[1] = data_value[0]; |
| 2425 | drm_connector_attach_property(connector, |
| 2426 | intel_sdvo_connector->bottom, |
| 2427 | intel_sdvo_connector->bottom_margin); |
| 2428 | DRM_DEBUG_KMS("v_overscan: max %d, " |
| 2429 | "default %d, current %d\n", |
| 2430 | data_value[0], data_value[1], response); |
| 2431 | } |
| 2432 | |
| 2433 | ENHANCEMENT(hpos, HPOS); |
| 2434 | ENHANCEMENT(vpos, VPOS); |
| 2435 | ENHANCEMENT(saturation, SATURATION); |
| 2436 | ENHANCEMENT(contrast, CONTRAST); |
| 2437 | ENHANCEMENT(hue, HUE); |
| 2438 | ENHANCEMENT(sharpness, SHARPNESS); |
| 2439 | ENHANCEMENT(brightness, BRIGHTNESS); |
| 2440 | ENHANCEMENT(flicker_filter, FLICKER_FILTER); |
| 2441 | ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); |
| 2442 | ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); |
| 2443 | ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); |
| 2444 | ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); |
| 2445 | |
Chris Wilson | e044218 | 2010-08-04 13:50:29 +0100 | [diff] [blame] | 2446 | if (enhancements.dot_crawl) { |
| 2447 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) |
| 2448 | return false; |
| 2449 | |
| 2450 | intel_sdvo_connector->max_dot_crawl = 1; |
| 2451 | intel_sdvo_connector->cur_dot_crawl = response & 0x1; |
| 2452 | intel_sdvo_connector->dot_crawl = |
| 2453 | drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2); |
| 2454 | if (!intel_sdvo_connector->dot_crawl) |
| 2455 | return false; |
| 2456 | |
| 2457 | intel_sdvo_connector->dot_crawl->values[0] = 0; |
| 2458 | intel_sdvo_connector->dot_crawl->values[1] = 1; |
| 2459 | drm_connector_attach_property(connector, |
| 2460 | intel_sdvo_connector->dot_crawl, |
| 2461 | intel_sdvo_connector->cur_dot_crawl); |
| 2462 | DRM_DEBUG_KMS("dot crawl: current %d\n", response); |
| 2463 | } |
| 2464 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2465 | return true; |
| 2466 | } |
| 2467 | |
| 2468 | static bool |
| 2469 | intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, |
| 2470 | struct intel_sdvo_connector *intel_sdvo_connector, |
| 2471 | struct intel_sdvo_enhancements_reply enhancements) |
| 2472 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2473 | struct drm_device *dev = intel_sdvo->base.base.dev; |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2474 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
| 2475 | uint16_t response, data_value[2]; |
| 2476 | |
| 2477 | ENHANCEMENT(brightness, BRIGHTNESS); |
| 2478 | |
| 2479 | return true; |
| 2480 | } |
| 2481 | #undef ENHANCEMENT |
| 2482 | |
| 2483 | static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
| 2484 | struct intel_sdvo_connector *intel_sdvo_connector) |
| 2485 | { |
| 2486 | union { |
| 2487 | struct intel_sdvo_enhancements_reply reply; |
| 2488 | uint16_t response; |
| 2489 | } enhancements; |
| 2490 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2491 | if (!intel_sdvo_get_value(intel_sdvo, |
| 2492 | SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2493 | &enhancements, sizeof(enhancements))) |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2494 | return false; |
| 2495 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2496 | if (enhancements.response == 0) { |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2497 | DRM_DEBUG_KMS("No enhancement is supported\n"); |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2498 | return true; |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2499 | } |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2500 | |
Chris Wilson | c552170 | 2010-08-04 13:50:28 +0100 | [diff] [blame] | 2501 | if (IS_TV(intel_sdvo_connector)) |
| 2502 | return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
| 2503 | else if(IS_LVDS(intel_sdvo_connector)) |
| 2504 | return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
| 2505 | else |
| 2506 | return true; |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2507 | |
Zhao Yakui | b9219c5 | 2009-09-10 15:45:46 +0800 | [diff] [blame] | 2508 | } |
| 2509 | |
Eric Anholt | c751ce4 | 2010-03-25 11:48:48 -0700 | [diff] [blame] | 2510 | bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2511 | { |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2512 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2513 | struct intel_encoder *intel_encoder; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2514 | struct intel_sdvo *intel_sdvo; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2515 | int i; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2516 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2517 | intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL); |
| 2518 | if (!intel_sdvo) |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 2519 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2520 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2521 | intel_sdvo->sdvo_reg = sdvo_reg; |
Keith Packard | 308cd3a | 2009-06-14 11:56:18 -0700 | [diff] [blame] | 2522 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2523 | intel_encoder = &intel_sdvo->base; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2524 | intel_encoder->type = INTEL_OUTPUT_SDVO; |
Chris Wilson | 373a3cf | 2010-09-15 12:03:59 +0100 | [diff] [blame] | 2525 | /* encoder type will be decided later */ |
| 2526 | drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2527 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2528 | intel_sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2529 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2530 | intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2531 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2532 | /* Read the regs to test if we can talk to the device */ |
| 2533 | for (i = 0; i < 0x40; i++) { |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2534 | u8 byte; |
| 2535 | |
| 2536 | if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 2537 | DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n", |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 2538 | IS_SDVOB(sdvo_reg) ? 'B' : 'C'); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2539 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2540 | } |
| 2541 | } |
| 2542 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2543 | if (IS_SDVOB(sdvo_reg)) |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2544 | dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS; |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2545 | else |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 2546 | dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS; |
Ma Ling | 619ac3b | 2009-05-18 16:12:46 +0800 | [diff] [blame] | 2547 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2548 | drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs); |
Zhenyu Wang | 14571b4 | 2010-03-30 14:06:33 +0800 | [diff] [blame] | 2549 | |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 2550 | /* In default case sdvo lvds is false */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2551 | if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2552 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2553 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2554 | if (intel_sdvo_output_setup(intel_sdvo, |
| 2555 | intel_sdvo->caps.output_flags) != true) { |
Dave Airlie | 51c8b40 | 2009-08-20 13:38:04 +1000 | [diff] [blame] | 2556 | DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n", |
Zhao Yakui | 461ed3c | 2010-03-30 15:11:33 +0800 | [diff] [blame] | 2557 | IS_SDVOB(sdvo_reg) ? 'B' : 'C'); |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2558 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2559 | } |
| 2560 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2561 | intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); |
Jesse Barnes | e2f0ba9 | 2009-02-02 15:11:52 -0800 | [diff] [blame] | 2562 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2563 | /* Set the input timing to the screen. Assume always input 0. */ |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2564 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2565 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2566 | |
Chris Wilson | 32aad86 | 2010-08-04 13:50:25 +0100 | [diff] [blame] | 2567 | if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, |
| 2568 | &intel_sdvo->pixel_clock_min, |
| 2569 | &intel_sdvo->pixel_clock_max)) |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2570 | goto err; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2571 | |
Zhao Yakui | 8a4c47f | 2009-07-20 13:48:04 +0800 | [diff] [blame] | 2572 | DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 2573 | "clock range %dMHz - %dMHz, " |
| 2574 | "input 1: %c, input 2: %c, " |
| 2575 | "output 1: %c, output 2: %c\n", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2576 | SDVO_NAME(intel_sdvo), |
| 2577 | intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, |
| 2578 | intel_sdvo->caps.device_rev_id, |
| 2579 | intel_sdvo->pixel_clock_min / 1000, |
| 2580 | intel_sdvo->pixel_clock_max / 1000, |
| 2581 | (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', |
| 2582 | (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', |
yakui_zhao | 342dc38 | 2009-06-02 14:12:00 +0800 | [diff] [blame] | 2583 | /* check currently supported outputs */ |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2584 | intel_sdvo->caps.output_flags & |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2585 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2586 | intel_sdvo->caps.output_flags & |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2587 | (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 2588 | return true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2589 | |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 2590 | err: |
Chris Wilson | 373a3cf | 2010-09-15 12:03:59 +0100 | [diff] [blame] | 2591 | drm_encoder_cleanup(&intel_encoder->base); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2592 | kfree(intel_sdvo); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2593 | |
Eric Anholt | 7d57382 | 2009-01-02 13:33:00 -0800 | [diff] [blame] | 2594 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2595 | } |