Thomas Petazzoni | f6e916b | 2012-11-20 23:00:52 +0100 | [diff] [blame] | 1 | config IRQCHIP |
2 | def_bool y | ||||
3 | depends on OF_IRQ | ||||
4 | |||||
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 5 | config ARM_GIC |
6 | bool | ||||
7 | select IRQ_DOMAIN | ||||
Yingjoe Chen | 9a1091e | 2014-11-25 16:04:19 +0800 | [diff] [blame] | 8 | select IRQ_DOMAIN_HIERARCHY |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 9 | select MULTI_IRQ_HANDLER |
10 | |||||
Jon Hunter | 9c8eddd | 2016-06-07 16:12:34 +0100 | [diff] [blame] | 11 | config ARM_GIC_PM |
12 | bool | ||||
13 | depends on PM | ||||
14 | select ARM_GIC | ||||
15 | select PM_CLK | ||||
16 | |||||
Linus Walleij | a27d21e | 2015-12-18 10:44:53 +0100 | [diff] [blame] | 17 | config ARM_GIC_MAX_NR |
18 | int | ||||
19 | default 2 if ARCH_REALVIEW | ||||
20 | default 1 | ||||
21 | |||||
Suravee Suthikulpanit | 853a33c | 2014-11-25 18:47:22 +0000 | [diff] [blame] | 22 | config ARM_GIC_V2M |
23 | bool | ||||
Arnd Bergmann | 3ee8036 | 2016-06-15 15:47:33 -0500 | [diff] [blame] | 24 | depends on PCI |
25 | select ARM_GIC | ||||
26 | select PCI_MSI | ||||
Suravee Suthikulpanit | 853a33c | 2014-11-25 18:47:22 +0000 | [diff] [blame] | 27 | |
Rob Herring | 81243e4 | 2012-11-20 21:21:40 -0600 | [diff] [blame] | 28 | config GIC_NON_BANKED |
29 | bool | ||||
30 | |||||
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 31 | config ARM_GIC_V3 |
32 | bool | ||||
33 | select IRQ_DOMAIN | ||||
34 | select MULTI_IRQ_HANDLER | ||||
Marc Zyngier | 443acc4 | 2014-11-24 14:35:09 +0000 | [diff] [blame] | 35 | select IRQ_DOMAIN_HIERARCHY |
Marc Zyngier | e3825ba | 2016-04-11 09:57:54 +0100 | [diff] [blame] | 36 | select PARTITION_PERCPU |
Channagoud Kadabi | c6aa38d | 2016-09-13 11:37:40 -0700 | [diff] [blame] | 37 | select QCOM_SHOW_RESUME_IRQ |
Marc Zyngier | 021f653 | 2014-06-30 16:01:31 +0100 | [diff] [blame] | 38 | |
Marc Zyngier | 1981272 | 2014-11-24 14:35:19 +0000 | [diff] [blame] | 39 | config ARM_GIC_V3_ITS |
40 | bool | ||||
Arnd Bergmann | 3ee8036 | 2016-06-15 15:47:33 -0500 | [diff] [blame] | 41 | depends on PCI |
42 | depends on PCI_MSI | ||||
Tomasz Nowicki | 3f010cf | 2016-09-12 20:32:25 +0200 | [diff] [blame] | 43 | select ACPI_IORT if ACPI |
Uwe Kleine-König | 292ec08 | 2013-06-26 09:18:48 +0200 | [diff] [blame] | 44 | |
Channagoud Kadabi | fdb0664 | 2016-09-19 20:55:36 -0700 | [diff] [blame] | 45 | config ARM_GIC_V3_ACL |
46 | bool "GICv3 Access control" | ||||
47 | depends on ARM_GIC_V3 | ||||
48 | help | ||||
49 | Access to GIC ITS address space is controlled by EL2. | ||||
50 | Kernel has no permission to access GIC ITS address space. | ||||
51 | If you wish to enforce the Acces control then set this | ||||
52 | option to Y, if you are unsure please say N. | ||||
53 | |||||
Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 54 | config ARM_NVIC |
55 | bool | ||||
56 | select IRQ_DOMAIN | ||||
Stefan Agner | 2d9f59f | 2015-05-16 11:44:16 +0200 | [diff] [blame] | 57 | select IRQ_DOMAIN_HIERARCHY |
Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 58 | select GENERIC_IRQ_CHIP |
59 | |||||
60 | config ARM_VIC | ||||
61 | bool | ||||
62 | select IRQ_DOMAIN | ||||
63 | select MULTI_IRQ_HANDLER | ||||
64 | |||||
65 | config ARM_VIC_NR | ||||
66 | int | ||||
67 | default 4 if ARCH_S5PV210 | ||||
Rob Herring | 44430ec | 2012-10-27 17:25:26 -0500 | [diff] [blame] | 68 | default 2 |
69 | depends on ARM_VIC | ||||
70 | help | ||||
71 | The maximum number of VICs available in the system, for | ||||
72 | power management. | ||||
73 | |||||
Thomas Petazzoni | fed6d33 | 2016-02-10 15:46:56 +0100 | [diff] [blame] | 74 | config ARMADA_370_XP_IRQ |
75 | bool | ||||
Thomas Petazzoni | fed6d33 | 2016-02-10 15:46:56 +0100 | [diff] [blame] | 76 | select GENERIC_IRQ_CHIP |
Arnd Bergmann | 3ee8036 | 2016-06-15 15:47:33 -0500 | [diff] [blame] | 77 | select PCI_MSI if PCI |
Thomas Petazzoni | fed6d33 | 2016-02-10 15:46:56 +0100 | [diff] [blame] | 78 | |
Antoine Tenart | e6b78f2 | 2016-02-19 16:22:44 +0100 | [diff] [blame] | 79 | config ALPINE_MSI |
80 | bool | ||||
Arnd Bergmann | 3ee8036 | 2016-06-15 15:47:33 -0500 | [diff] [blame] | 81 | depends on PCI |
82 | select PCI_MSI | ||||
Antoine Tenart | e6b78f2 | 2016-02-19 16:22:44 +0100 | [diff] [blame] | 83 | select GENERIC_IRQ_CHIP |
Antoine Tenart | e6b78f2 | 2016-02-19 16:22:44 +0100 | [diff] [blame] | 84 | |
Boris BREZILLON | b1479eb | 2014-07-10 19:14:18 +0200 | [diff] [blame] | 85 | config ATMEL_AIC_IRQ |
86 | bool | ||||
87 | select GENERIC_IRQ_CHIP | ||||
88 | select IRQ_DOMAIN | ||||
89 | select MULTI_IRQ_HANDLER | ||||
90 | select SPARSE_IRQ | ||||
91 | |||||
92 | config ATMEL_AIC5_IRQ | ||||
93 | bool | ||||
94 | select GENERIC_IRQ_CHIP | ||||
95 | select IRQ_DOMAIN | ||||
96 | select MULTI_IRQ_HANDLER | ||||
97 | select SPARSE_IRQ | ||||
98 | |||||
Ralf Baechle | 0509cfd | 2015-07-08 14:46:08 +0200 | [diff] [blame] | 99 | config I8259 |
100 | bool | ||||
101 | select IRQ_DOMAIN | ||||
102 | |||||
Simon Arlott | c7c42ec | 2015-11-22 14:30:14 +0000 | [diff] [blame] | 103 | config BCM6345_L1_IRQ |
104 | bool | ||||
105 | select GENERIC_IRQ_CHIP | ||||
106 | select IRQ_DOMAIN | ||||
107 | |||||
Kevin Cernekee | 5f7f031 | 2014-12-25 09:49:06 -0800 | [diff] [blame] | 108 | config BCM7038_L1_IRQ |
109 | bool | ||||
110 | select GENERIC_IRQ_CHIP | ||||
111 | select IRQ_DOMAIN | ||||
112 | |||||
Kevin Cernekee | a4fcbb8 | 2014-11-06 22:44:27 -0800 | [diff] [blame] | 113 | config BCM7120_L2_IRQ |
114 | bool | ||||
115 | select GENERIC_IRQ_CHIP | ||||
116 | select IRQ_DOMAIN | ||||
117 | |||||
Florian Fainelli | 7f646e9 | 2014-05-23 17:40:53 -0700 | [diff] [blame] | 118 | config BRCMSTB_L2_IRQ |
119 | bool | ||||
Florian Fainelli | 7f646e9 | 2014-05-23 17:40:53 -0700 | [diff] [blame] | 120 | select GENERIC_IRQ_CHIP |
121 | select IRQ_DOMAIN | ||||
122 | |||||
Channagoud Kadabi | c6aa38d | 2016-09-13 11:37:40 -0700 | [diff] [blame] | 123 | config QCOM_SHOW_RESUME_IRQ |
124 | bool "Enable logging of interrupts that could have caused resume" | ||||
125 | depends on ARM_GIC | ||||
126 | default n | ||||
127 | help | ||||
128 | This option logs wake up interrupts that have triggered just before | ||||
129 | the resume loop unrolls. It helps to debug to know any unnecessary | ||||
130 | wake up interrupts that causes system to come out of low power modes. | ||||
131 | Say Y if you want to debug why the system resumed. | ||||
132 | |||||
Sebastian Hesselbarth | 350d71b9 | 2013-09-09 14:01:20 +0200 | [diff] [blame] | 133 | config DW_APB_ICTL |
134 | bool | ||||
Jisheng Zhang | e158849 | 2014-10-22 20:59:10 +0800 | [diff] [blame] | 135 | select GENERIC_IRQ_CHIP |
Sebastian Hesselbarth | 350d71b9 | 2013-09-09 14:01:20 +0200 | [diff] [blame] | 136 | select IRQ_DOMAIN |
137 | |||||
MaJun | 9a7c4ab | 2016-03-23 17:06:33 +0800 | [diff] [blame] | 138 | config HISILICON_IRQ_MBIGEN |
139 | bool | ||||
140 | select ARM_GIC_V3 | ||||
141 | select ARM_GIC_V3_ITS | ||||
MaJun | 9a7c4ab | 2016-03-23 17:06:33 +0800 | [diff] [blame] | 142 | |
James Hogan | b6ef916 | 2013-04-22 15:43:50 +0100 | [diff] [blame] | 143 | config IMGPDC_IRQ |
144 | bool | ||||
145 | select GENERIC_IRQ_CHIP | ||||
146 | select IRQ_DOMAIN | ||||
147 | |||||
Ralf Baechle | 67e38cf | 2015-05-26 18:20:06 +0200 | [diff] [blame] | 148 | config IRQ_MIPS_CPU |
149 | bool | ||||
150 | select GENERIC_IRQ_CHIP | ||||
151 | select IRQ_DOMAIN | ||||
152 | |||||
Alexander Shiyan | afc98d9 | 2014-02-02 12:07:46 +0400 | [diff] [blame] | 153 | config CLPS711X_IRQCHIP |
154 | bool | ||||
155 | depends on ARCH_CLPS711X | ||||
156 | select IRQ_DOMAIN | ||||
157 | select MULTI_IRQ_HANDLER | ||||
158 | select SPARSE_IRQ | ||||
159 | default y | ||||
160 | |||||
Stefan Kristiansson | 4db8e6d | 2014-05-26 23:31:42 +0300 | [diff] [blame] | 161 | config OR1K_PIC |
162 | bool | ||||
163 | select IRQ_DOMAIN | ||||
164 | |||||
Felipe Balbi | 8598066 | 2014-09-15 16:15:02 -0500 | [diff] [blame] | 165 | config OMAP_IRQCHIP |
166 | bool | ||||
167 | select GENERIC_IRQ_CHIP | ||||
168 | select IRQ_DOMAIN | ||||
169 | |||||
Sebastian Hesselbarth | 9dbd90f | 2013-06-06 18:27:09 +0200 | [diff] [blame] | 170 | config ORION_IRQCHIP |
171 | bool | ||||
172 | select IRQ_DOMAIN | ||||
173 | select MULTI_IRQ_HANDLER | ||||
174 | |||||
Cristian Birsan | aaa8666 | 2016-01-13 18:15:35 -0700 | [diff] [blame] | 175 | config PIC32_EVIC |
176 | bool | ||||
177 | select GENERIC_IRQ_CHIP | ||||
178 | select IRQ_DOMAIN | ||||
179 | |||||
Rich Felker | 981b58f | 2016-08-04 04:30:37 +0000 | [diff] [blame] | 180 | config JCORE_AIC |
Rich Felker | 3602ffd | 2016-10-19 17:53:52 +0000 | [diff] [blame] | 181 | bool "J-Core integrated AIC" if COMPILE_TEST |
182 | depends on OF | ||||
Rich Felker | 981b58f | 2016-08-04 04:30:37 +0000 | [diff] [blame] | 183 | select IRQ_DOMAIN |
184 | help | ||||
185 | Support for the J-Core integrated AIC. | ||||
186 | |||||
Magnus Damm | 4435804 | 2013-02-18 23:28:34 +0900 | [diff] [blame] | 187 | config RENESAS_INTC_IRQPIN |
188 | bool | ||||
189 | select IRQ_DOMAIN | ||||
190 | |||||
Magnus Damm | fbc83b7 | 2013-02-27 17:15:01 +0900 | [diff] [blame] | 191 | config RENESAS_IRQC |
192 | bool | ||||
Magnus Damm | 99c221d | 2015-09-28 18:42:37 +0900 | [diff] [blame] | 193 | select GENERIC_IRQ_CHIP |
Magnus Damm | fbc83b7 | 2013-02-27 17:15:01 +0900 | [diff] [blame] | 194 | select IRQ_DOMAIN |
195 | |||||
Lee Jones | 0708848 | 2015-02-18 15:13:58 +0000 | [diff] [blame] | 196 | config ST_IRQCHIP |
197 | bool | ||||
198 | select REGMAP | ||||
199 | select MFD_SYSCON | ||||
200 | help | ||||
201 | Enables SysCfg Controlled IRQs on STi based platforms. | ||||
202 | |||||
Mans Rullgard | 4bba668 | 2016-01-20 18:07:17 +0000 | [diff] [blame] | 203 | config TANGO_IRQ |
204 | bool | ||||
205 | select IRQ_DOMAIN | ||||
206 | select GENERIC_IRQ_CHIP | ||||
207 | |||||
Christian Ruppert | b06eb01 | 2013-06-25 18:29:57 +0200 | [diff] [blame] | 208 | config TB10X_IRQC |
209 | bool | ||||
210 | select IRQ_DOMAIN | ||||
211 | select GENERIC_IRQ_CHIP | ||||
212 | |||||
Damien Riegel | d01f863 | 2015-12-21 15:11:23 -0500 | [diff] [blame] | 213 | config TS4800_IRQ |
214 | tristate "TS-4800 IRQ controller" | ||||
215 | select IRQ_DOMAIN | ||||
Richard Weinberger | 0df337c | 2016-01-25 23:24:17 +0100 | [diff] [blame] | 216 | depends on HAS_IOMEM |
Jean Delvare | d2b383d | 2016-02-09 11:19:20 +0100 | [diff] [blame] | 217 | depends on SOC_IMX51 || COMPILE_TEST |
Damien Riegel | d01f863 | 2015-12-21 15:11:23 -0500 | [diff] [blame] | 218 | help |
219 | Support for the TS-4800 FPGA IRQ controller | ||||
220 | |||||
Linus Walleij | 2389d50 | 2012-10-31 22:04:31 +0100 | [diff] [blame] | 221 | config VERSATILE_FPGA_IRQ |
222 | bool | ||||
223 | select IRQ_DOMAIN | ||||
224 | |||||
225 | config VERSATILE_FPGA_IRQ_NR | ||||
226 | int | ||||
227 | default 4 | ||||
228 | depends on VERSATILE_FPGA_IRQ | ||||
Max Filippov | 26a8e96 | 2013-12-01 12:04:57 +0400 | [diff] [blame] | 229 | |
230 | config XTENSA_MX | ||||
231 | bool | ||||
232 | select IRQ_DOMAIN | ||||
Sricharan R | 96ca848 | 2013-12-03 15:57:23 +0530 | [diff] [blame] | 233 | |
234 | config IRQ_CROSSBAR | ||||
235 | bool | ||||
236 | help | ||||
Masanari Iida | f54619f | 2014-09-18 12:09:42 +0900 | [diff] [blame] | 237 | Support for a CROSSBAR ip that precedes the main interrupt controller. |
Sricharan R | 96ca848 | 2013-12-03 15:57:23 +0530 | [diff] [blame] | 238 | The primary irqchip invokes the crossbar's callback which inturn allocates |
239 | a free irq and configures the IP. Thus the peripheral interrupts are | ||||
240 | routed to one of the free irqchip interrupt lines. | ||||
Grygorii Strashko | 89323f8 | 2014-07-23 17:40:30 +0300 | [diff] [blame] | 241 | |
242 | config KEYSTONE_IRQ | ||||
243 | tristate "Keystone 2 IRQ controller IP" | ||||
244 | depends on ARCH_KEYSTONE | ||||
245 | help | ||||
246 | Support for Texas Instruments Keystone 2 IRQ controller IP which | ||||
247 | is part of the Keystone 2 IPC mechanism | ||||
Andrew Bresticker | 8a19b8f | 2014-09-18 14:47:19 -0700 | [diff] [blame] | 248 | |
249 | config MIPS_GIC | ||||
250 | bool | ||||
Qais Yousef | bb11cff | 2015-12-08 13:20:28 +0000 | [diff] [blame] | 251 | select GENERIC_IRQ_IPI |
Qais Yousef | 2af70a9 | 2015-12-08 13:20:23 +0000 | [diff] [blame] | 252 | select IRQ_DOMAIN_HIERARCHY |
Andrew Bresticker | 8a19b8f | 2014-09-18 14:47:19 -0700 | [diff] [blame] | 253 | select MIPS_CM |
Yoshinori Sato | 8a76448 | 2015-05-10 02:30:47 +0900 | [diff] [blame] | 254 | |
Paul Burton | 44e08e7 | 2015-05-24 16:11:31 +0100 | [diff] [blame] | 255 | config INGENIC_IRQ |
256 | bool | ||||
257 | depends on MACH_INGENIC | ||||
258 | default y | ||||
Linus Torvalds | 78c10e5 | 2015-06-27 12:44:34 -0700 | [diff] [blame] | 259 | |
Yoshinori Sato | 8a76448 | 2015-05-10 02:30:47 +0900 | [diff] [blame] | 260 | config RENESAS_H8300H_INTC |
261 | bool | ||||
262 | select IRQ_DOMAIN | ||||
263 | |||||
264 | config RENESAS_H8S_INTC | ||||
265 | bool | ||||
Linus Torvalds | 78c10e5 | 2015-06-27 12:44:34 -0700 | [diff] [blame] | 266 | select IRQ_DOMAIN |
Shenwei Wang | e324c4d | 2015-08-24 14:04:15 -0500 | [diff] [blame] | 267 | |
268 | config IMX_GPCV2 | ||||
269 | bool | ||||
270 | select IRQ_DOMAIN | ||||
271 | help | ||||
272 | Enables the wakeup IRQs for IMX platforms with GPCv2 block | ||||
Oleksij Rempel | 7e4ac67 | 2015-10-12 21:15:34 +0200 | [diff] [blame] | 273 | |
274 | config IRQ_MXS | ||||
275 | def_bool y if MACH_ASM9260 || ARCH_MXS | ||||
276 | select IRQ_DOMAIN | ||||
277 | select STMP_DEVICE | ||||
Thomas Petazzoni | c27f29b | 2016-02-19 14:34:43 +0100 | [diff] [blame] | 278 | |
279 | config MVEBU_ODMI | ||||
280 | bool | ||||
Arnd Bergmann | 889163d | 2017-03-14 13:54:12 +0100 | [diff] [blame] | 281 | select GENERIC_MSI_IRQ_DOMAIN |
Marc Zyngier | 9e2c986 | 2016-04-11 09:57:53 +0100 | [diff] [blame] | 282 | |
Thomas Petazzoni | a109893 | 2016-08-05 16:55:19 +0200 | [diff] [blame] | 283 | config MVEBU_PIC |
284 | bool | ||||
285 | |||||
Minghuan Lian | b8f3ebe | 2016-03-23 19:08:20 +0800 | [diff] [blame] | 286 | config LS_SCFG_MSI |
287 | def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE | ||||
288 | depends on PCI && PCI_MSI | ||||
Minghuan Lian | b8f3ebe | 2016-03-23 19:08:20 +0800 | [diff] [blame] | 289 | |
Marc Zyngier | 9e2c986 | 2016-04-11 09:57:53 +0100 | [diff] [blame] | 290 | config PARTITION_PERCPU |
291 | bool | ||||
Linus Torvalds | 0efacbb | 2016-05-19 09:46:18 -0700 | [diff] [blame] | 292 | |
Noam Camus | 44df427c | 2015-10-29 00:26:22 +0200 | [diff] [blame] | 293 | config EZNPS_GIC |
294 | bool "NPS400 Global Interrupt Manager (GIM)" | ||||
Arnd Bergmann | ffd565e | 2016-05-12 23:03:35 +0200 | [diff] [blame] | 295 | depends on ARC || (COMPILE_TEST && !64BIT) |
Noam Camus | 44df427c | 2015-10-29 00:26:22 +0200 | [diff] [blame] | 296 | select IRQ_DOMAIN |
297 | help | ||||
298 | Support the EZchip NPS400 global interrupt controller | ||||
Alexandre TORGUE | e0720416 | 2016-09-20 18:00:57 +0200 | [diff] [blame] | 299 | |
300 | config STM32_EXTI | ||||
301 | bool | ||||
302 | select IRQ_DOMAIN | ||||
Archana Sathyakumar | 741a37a | 2017-05-10 11:03:39 -0600 | [diff] [blame] | 303 | |
304 | source "drivers/irqchip/qcom/Kconfig" |