Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1 | #ifndef _INTEL_RINGBUFFER_H_ |
| 2 | #define _INTEL_RINGBUFFER_H_ |
| 3 | |
Brad Volkin | 44e895a | 2014-05-10 14:10:43 -0700 | [diff] [blame] | 4 | #include <linux/hashtable.h> |
Chris Wilson | 06fbca7 | 2015-04-07 16:20:36 +0100 | [diff] [blame] | 5 | #include "i915_gem_batch_pool.h" |
Brad Volkin | 44e895a | 2014-05-10 14:10:43 -0700 | [diff] [blame] | 6 | |
| 7 | #define I915_CMD_HASH_ORDER 9 |
| 8 | |
Oscar Mateo | 4712274 | 2014-07-24 17:04:28 +0100 | [diff] [blame] | 9 | /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill, |
| 10 | * but keeps the logic simple. Indeed, the whole purpose of this macro is just |
| 11 | * to give some inclination as to some of the magic values used in the various |
| 12 | * workarounds! |
| 13 | */ |
| 14 | #define CACHELINE_BYTES 64 |
Arun Siluvery | 17ee950 | 2015-06-19 19:07:01 +0100 | [diff] [blame] | 15 | #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t)) |
Oscar Mateo | 4712274 | 2014-07-24 17:04:28 +0100 | [diff] [blame] | 16 | |
Ville Syrjälä | 633cf8f | 2012-12-03 18:43:32 +0200 | [diff] [blame] | 17 | /* |
| 18 | * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use" |
| 19 | * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use" |
| 20 | * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use" |
| 21 | * |
| 22 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same |
| 23 | * cacheline, the Head Pointer must not be greater than the Tail |
| 24 | * Pointer." |
| 25 | */ |
| 26 | #define I915_RING_FREE_SPACE 64 |
| 27 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 28 | struct intel_hw_status_page { |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 29 | u32 *page_addr; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 30 | unsigned int gfx_addr; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 31 | struct drm_i915_gem_object *obj; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 32 | }; |
| 33 | |
Dave Gordon | bbdc070a | 2016-07-20 18:16:05 +0100 | [diff] [blame] | 34 | #define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base)) |
| 35 | #define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 36 | |
Dave Gordon | bbdc070a | 2016-07-20 18:16:05 +0100 | [diff] [blame] | 37 | #define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base)) |
| 38 | #define I915_WRITE_START(engine, val) I915_WRITE(RING_START((engine)->mmio_base), val) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 39 | |
Dave Gordon | bbdc070a | 2016-07-20 18:16:05 +0100 | [diff] [blame] | 40 | #define I915_READ_HEAD(engine) I915_READ(RING_HEAD((engine)->mmio_base)) |
| 41 | #define I915_WRITE_HEAD(engine, val) I915_WRITE(RING_HEAD((engine)->mmio_base), val) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 42 | |
Dave Gordon | bbdc070a | 2016-07-20 18:16:05 +0100 | [diff] [blame] | 43 | #define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base)) |
| 44 | #define I915_WRITE_CTL(engine, val) I915_WRITE(RING_CTL((engine)->mmio_base), val) |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 45 | |
Dave Gordon | bbdc070a | 2016-07-20 18:16:05 +0100 | [diff] [blame] | 46 | #define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base)) |
| 47 | #define I915_WRITE_IMR(engine, val) I915_WRITE(RING_IMR((engine)->mmio_base), val) |
Daniel Vetter | 870e86d | 2010-08-02 16:29:44 +0200 | [diff] [blame] | 48 | |
Dave Gordon | bbdc070a | 2016-07-20 18:16:05 +0100 | [diff] [blame] | 49 | #define I915_READ_MODE(engine) I915_READ(RING_MI_MODE((engine)->mmio_base)) |
| 50 | #define I915_WRITE_MODE(engine, val) I915_WRITE(RING_MI_MODE((engine)->mmio_base), val) |
Naresh Kumar Kachhi | e9fea57 | 2014-03-12 16:39:41 +0530 | [diff] [blame] | 51 | |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 52 | /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to |
| 53 | * do the writes, and that must have qw aligned offsets, simply pretend it's 8b. |
| 54 | */ |
Chris Wilson | 8c12672 | 2016-04-07 07:29:14 +0100 | [diff] [blame] | 55 | #define gen8_semaphore_seqno_size sizeof(uint64_t) |
| 56 | #define GEN8_SEMAPHORE_OFFSET(__from, __to) \ |
| 57 | (((__from) * I915_NUM_ENGINES + (__to)) * gen8_semaphore_seqno_size) |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 58 | #define GEN8_SIGNAL_OFFSET(__ring, to) \ |
| 59 | (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ |
Chris Wilson | 8c12672 | 2016-04-07 07:29:14 +0100 | [diff] [blame] | 60 | GEN8_SEMAPHORE_OFFSET((__ring)->id, (to))) |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 61 | #define GEN8_WAIT_OFFSET(__ring, from) \ |
| 62 | (i915_gem_obj_ggtt_offset(dev_priv->semaphore_obj) + \ |
Chris Wilson | 8c12672 | 2016-04-07 07:29:14 +0100 | [diff] [blame] | 63 | GEN8_SEMAPHORE_OFFSET(from, (__ring)->id)) |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 64 | |
Chris Wilson | 7e37f88 | 2016-08-02 22:50:21 +0100 | [diff] [blame] | 65 | enum intel_engine_hangcheck_action { |
Mika Kuoppala | da66146 | 2013-09-06 16:03:28 +0300 | [diff] [blame] | 66 | HANGCHECK_IDLE = 0, |
Jani Nikula | f2f4d82 | 2013-08-11 12:44:01 +0300 | [diff] [blame] | 67 | HANGCHECK_WAIT, |
| 68 | HANGCHECK_ACTIVE, |
| 69 | HANGCHECK_KICK, |
| 70 | HANGCHECK_HUNG, |
| 71 | }; |
Mika Kuoppala | ad8beae | 2013-06-12 12:35:32 +0300 | [diff] [blame] | 72 | |
Mika Kuoppala | b6b0fac | 2014-01-30 19:04:43 +0200 | [diff] [blame] | 73 | #define HANGCHECK_SCORE_RING_HUNG 31 |
| 74 | |
Chris Wilson | 7e37f88 | 2016-08-02 22:50:21 +0100 | [diff] [blame] | 75 | struct intel_engine_hangcheck { |
Chris Wilson | 5087744 | 2014-03-21 12:41:53 +0000 | [diff] [blame] | 76 | u64 acthd; |
Chris Wilson | aca34b6 | 2016-07-06 12:39:02 +0100 | [diff] [blame] | 77 | unsigned long user_interrupts; |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame] | 78 | u32 seqno; |
Mika Kuoppala | 05407ff | 2013-05-30 09:04:29 +0300 | [diff] [blame] | 79 | int score; |
Chris Wilson | 7e37f88 | 2016-08-02 22:50:21 +0100 | [diff] [blame] | 80 | enum intel_engine_hangcheck_action action; |
Chris Wilson | 4be1738 | 2014-06-06 10:22:29 +0100 | [diff] [blame] | 81 | int deadlock; |
Mika Kuoppala | 61642ff | 2015-12-01 17:56:12 +0200 | [diff] [blame] | 82 | u32 instdone[I915_NUM_INSTDONE_REG]; |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame] | 83 | }; |
| 84 | |
Chris Wilson | 7e37f88 | 2016-08-02 22:50:21 +0100 | [diff] [blame] | 85 | struct intel_ring { |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 86 | struct drm_i915_gem_object *obj; |
Chris Wilson | f2f0ed7 | 2016-07-20 13:31:56 +0100 | [diff] [blame] | 87 | void *vaddr; |
Tvrtko Ursulin | 0eb973d | 2016-01-15 15:10:28 +0000 | [diff] [blame] | 88 | struct i915_vma *vma; |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 89 | |
Tvrtko Ursulin | 4a570db | 2016-03-16 11:00:38 +0000 | [diff] [blame] | 90 | struct intel_engine_cs *engine; |
Chris Wilson | 608c1a5 | 2015-09-03 13:01:40 +0100 | [diff] [blame] | 91 | struct list_head link; |
Daniel Vetter | 0c7dd53 | 2014-08-11 16:17:44 +0200 | [diff] [blame] | 92 | |
Oscar Mateo | 8ee1497 | 2014-05-22 14:13:34 +0100 | [diff] [blame] | 93 | u32 head; |
| 94 | u32 tail; |
| 95 | int space; |
| 96 | int size; |
| 97 | int effective_size; |
| 98 | |
| 99 | /** We track the position of the requests in the ring buffer, and |
| 100 | * when each is retired we increment last_retired_head as the GPU |
| 101 | * must have finished processing the request and so we know we |
| 102 | * can advance the ringbuffer up to that position. |
| 103 | * |
| 104 | * last_retired_head is set to -1 after the value is consumed so |
| 105 | * we can detect new retirements. |
| 106 | */ |
| 107 | u32 last_retired_head; |
| 108 | }; |
| 109 | |
Chris Wilson | e2efd13 | 2016-05-24 14:53:34 +0100 | [diff] [blame] | 110 | struct i915_gem_context; |
Jordan Justen | 361b027 | 2016-03-06 23:30:27 -0800 | [diff] [blame] | 111 | struct drm_i915_reg_table; |
Nick Hoath | 2107637 | 2015-01-15 13:10:38 +0000 | [diff] [blame] | 112 | |
Arun Siluvery | 17ee950 | 2015-06-19 19:07:01 +0100 | [diff] [blame] | 113 | /* |
| 114 | * we use a single page to load ctx workarounds so all of these |
| 115 | * values are referred in terms of dwords |
| 116 | * |
| 117 | * struct i915_wa_ctx_bb: |
| 118 | * offset: specifies batch starting position, also helpful in case |
| 119 | * if we want to have multiple batches at different offsets based on |
| 120 | * some criteria. It is not a requirement at the moment but provides |
| 121 | * an option for future use. |
| 122 | * size: size of the batch in DWORDS |
| 123 | */ |
| 124 | struct i915_ctx_workarounds { |
| 125 | struct i915_wa_ctx_bb { |
| 126 | u32 offset; |
| 127 | u32 size; |
| 128 | } indirect_ctx, per_ctx; |
| 129 | struct drm_i915_gem_object *obj; |
| 130 | }; |
| 131 | |
Chris Wilson | c81d461 | 2016-07-01 17:23:25 +0100 | [diff] [blame] | 132 | struct drm_i915_gem_request; |
| 133 | |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 134 | struct intel_engine_cs { |
| 135 | struct drm_i915_private *i915; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 136 | const char *name; |
Tvrtko Ursulin | 117897f | 2016-03-16 11:00:40 +0000 | [diff] [blame] | 137 | enum intel_engine_id { |
Tvrtko Ursulin | de1add3 | 2016-01-15 15:12:50 +0000 | [diff] [blame] | 138 | RCS = 0, |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 139 | BCS, |
Tvrtko Ursulin | de1add3 | 2016-01-15 15:12:50 +0000 | [diff] [blame] | 140 | VCS, |
| 141 | VCS2, /* Keep instances of the same type engine together. */ |
| 142 | VECS |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 143 | } id; |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 144 | #define I915_NUM_ENGINES 5 |
Tvrtko Ursulin | de1add3 | 2016-01-15 15:12:50 +0000 | [diff] [blame] | 145 | #define _VCS(n) (VCS + (n)) |
Chris Wilson | 426960b | 2016-01-15 16:51:46 +0000 | [diff] [blame] | 146 | unsigned int exec_id; |
Chris Wilson | 215a7e3 | 2016-04-29 13:18:23 +0100 | [diff] [blame] | 147 | unsigned int hw_id; |
| 148 | unsigned int guc_id; /* XXX same as hw_id? */ |
Chris Wilson | 0476965 | 2016-07-20 09:21:11 +0100 | [diff] [blame] | 149 | u64 fence_context; |
Daniel Vetter | 333e9fe | 2010-08-02 16:24:01 +0200 | [diff] [blame] | 150 | u32 mmio_base; |
Dave Gordon | c2c7f24 | 2016-07-13 16:03:35 +0100 | [diff] [blame] | 151 | unsigned int irq_shift; |
Chris Wilson | 7e37f88 | 2016-08-02 22:50:21 +0100 | [diff] [blame] | 152 | struct intel_ring *buffer; |
Chris Wilson | 608c1a5 | 2015-09-03 13:01:40 +0100 | [diff] [blame] | 153 | struct list_head buffers; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 154 | |
Chris Wilson | 688e6c7 | 2016-07-01 17:23:15 +0100 | [diff] [blame] | 155 | /* Rather than have every client wait upon all user interrupts, |
| 156 | * with the herd waking after every interrupt and each doing the |
| 157 | * heavyweight seqno dance, we delegate the task (of being the |
| 158 | * bottom-half of the user interrupt) to the first client. After |
| 159 | * every interrupt, we wake up one client, who does the heavyweight |
| 160 | * coherent seqno read and either goes back to sleep (if incomplete), |
| 161 | * or wakes up all the completed clients in parallel, before then |
| 162 | * transferring the bottom-half status to the next client in the queue. |
| 163 | * |
| 164 | * Compared to walking the entire list of waiters in a single dedicated |
| 165 | * bottom-half, we reduce the latency of the first waiter by avoiding |
| 166 | * a context switch, but incur additional coherent seqno reads when |
| 167 | * following the chain of request breadcrumbs. Since it is most likely |
| 168 | * that we have a single client waiting on each seqno, then reducing |
| 169 | * the overhead of waking that client is much preferred. |
| 170 | */ |
| 171 | struct intel_breadcrumbs { |
Chris Wilson | aca34b6 | 2016-07-06 12:39:02 +0100 | [diff] [blame] | 172 | struct task_struct *irq_seqno_bh; /* bh for user interrupts */ |
| 173 | unsigned long irq_wakeups; |
| 174 | bool irq_posted; |
| 175 | |
Chris Wilson | 688e6c7 | 2016-07-01 17:23:15 +0100 | [diff] [blame] | 176 | spinlock_t lock; /* protects the lists of requests */ |
| 177 | struct rb_root waiters; /* sorted by retirement, priority */ |
Chris Wilson | c81d461 | 2016-07-01 17:23:25 +0100 | [diff] [blame] | 178 | struct rb_root signals; /* sorted by retirement */ |
Chris Wilson | 688e6c7 | 2016-07-01 17:23:15 +0100 | [diff] [blame] | 179 | struct intel_wait *first_wait; /* oldest waiter by retirement */ |
Chris Wilson | c81d461 | 2016-07-01 17:23:25 +0100 | [diff] [blame] | 180 | struct task_struct *signaler; /* used for fence signalling */ |
Chris Wilson | b385085 | 2016-07-01 17:23:26 +0100 | [diff] [blame] | 181 | struct drm_i915_gem_request *first_signal; |
Chris Wilson | 688e6c7 | 2016-07-01 17:23:15 +0100 | [diff] [blame] | 182 | struct timer_list fake_irq; /* used after a missed interrupt */ |
Chris Wilson | aca34b6 | 2016-07-06 12:39:02 +0100 | [diff] [blame] | 183 | |
| 184 | bool irq_enabled : 1; |
| 185 | bool rpm_wakelock : 1; |
Chris Wilson | 688e6c7 | 2016-07-01 17:23:15 +0100 | [diff] [blame] | 186 | } breadcrumbs; |
| 187 | |
Chris Wilson | 06fbca7 | 2015-04-07 16:20:36 +0100 | [diff] [blame] | 188 | /* |
| 189 | * A pool of objects to use as shadow copies of client batch buffers |
| 190 | * when the command parser is enabled. Prevents the client from |
| 191 | * modifying the batch contents after software parsing. |
| 192 | */ |
| 193 | struct i915_gem_batch_pool batch_pool; |
| 194 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 195 | struct intel_hw_status_page status_page; |
Arun Siluvery | 17ee950 | 2015-06-19 19:07:01 +0100 | [diff] [blame] | 196 | struct i915_ctx_workarounds wa_ctx; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 197 | |
Chris Wilson | 61ff75a | 2016-07-01 17:23:28 +0100 | [diff] [blame] | 198 | u32 irq_keep_mask; /* always keep these interrupts */ |
| 199 | u32 irq_enable_mask; /* bitmask to enable ring interrupt */ |
Dave Gordon | 38a0f2d | 2016-07-20 18:16:06 +0100 | [diff] [blame] | 200 | void (*irq_enable)(struct intel_engine_cs *engine); |
| 201 | void (*irq_disable)(struct intel_engine_cs *engine); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 202 | |
Dave Gordon | 38a0f2d | 2016-07-20 18:16:06 +0100 | [diff] [blame] | 203 | int (*init_hw)(struct intel_engine_cs *engine); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 204 | |
John Harrison | 8753181 | 2015-05-29 17:43:44 +0100 | [diff] [blame] | 205 | int (*init_context)(struct drm_i915_gem_request *req); |
Arun Siluvery | 86d7f23 | 2014-08-26 14:44:50 +0100 | [diff] [blame] | 206 | |
Chris Wilson | ddd66c5 | 2016-08-02 22:50:31 +0100 | [diff] [blame] | 207 | int (*emit_flush)(struct drm_i915_gem_request *request, |
| 208 | u32 mode); |
| 209 | #define EMIT_INVALIDATE BIT(0) |
| 210 | #define EMIT_FLUSH BIT(1) |
| 211 | #define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH) |
| 212 | int (*emit_bb_start)(struct drm_i915_gem_request *req, |
| 213 | u64 offset, u32 length, |
| 214 | unsigned int dispatch_flags); |
| 215 | #define I915_DISPATCH_SECURE BIT(0) |
| 216 | #define I915_DISPATCH_PINNED BIT(1) |
| 217 | #define I915_DISPATCH_RS BIT(2) |
| 218 | int (*emit_request)(struct drm_i915_gem_request *req); |
| 219 | void (*submit_request)(struct drm_i915_gem_request *req); |
Chris Wilson | b2eadbc | 2012-08-09 10:58:30 +0100 | [diff] [blame] | 220 | /* Some chipsets are not quite as coherent as advertised and need |
| 221 | * an expensive kick to force a true read of the up-to-date seqno. |
| 222 | * However, the up-to-date seqno is not always required and the last |
| 223 | * seen value is good enough. Note that the seqno will always be |
| 224 | * monotonic, even if not coherent. |
| 225 | */ |
Dave Gordon | 38a0f2d | 2016-07-20 18:16:06 +0100 | [diff] [blame] | 226 | void (*irq_seqno_barrier)(struct intel_engine_cs *engine); |
Dave Gordon | 38a0f2d | 2016-07-20 18:16:06 +0100 | [diff] [blame] | 227 | void (*cleanup)(struct intel_engine_cs *engine); |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 228 | |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 229 | /* GEN8 signal/wait table - never trust comments! |
| 230 | * signal to signal to signal to signal to signal to |
| 231 | * RCS VCS BCS VECS VCS2 |
| 232 | * -------------------------------------------------------------------- |
| 233 | * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) | |
| 234 | * |------------------------------------------------------------------- |
| 235 | * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) | |
| 236 | * |------------------------------------------------------------------- |
| 237 | * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) | |
| 238 | * |------------------------------------------------------------------- |
| 239 | * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) | |
| 240 | * |------------------------------------------------------------------- |
| 241 | * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) | |
| 242 | * |------------------------------------------------------------------- |
| 243 | * |
| 244 | * Generalization: |
| 245 | * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id) |
| 246 | * ie. transpose of g(x, y) |
| 247 | * |
| 248 | * sync from sync from sync from sync from sync from |
| 249 | * RCS VCS BCS VECS VCS2 |
| 250 | * -------------------------------------------------------------------- |
| 251 | * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) | |
| 252 | * |------------------------------------------------------------------- |
| 253 | * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) | |
| 254 | * |------------------------------------------------------------------- |
| 255 | * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) | |
| 256 | * |------------------------------------------------------------------- |
| 257 | * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) | |
| 258 | * |------------------------------------------------------------------- |
| 259 | * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) | |
| 260 | * |------------------------------------------------------------------- |
| 261 | * |
| 262 | * Generalization: |
| 263 | * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id) |
| 264 | * ie. transpose of f(x, y) |
| 265 | */ |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 266 | struct { |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 267 | u32 sync_seqno[I915_NUM_ENGINES-1]; |
Ben Widawsky | 78325f2 | 2014-04-29 14:52:29 -0700 | [diff] [blame] | 268 | |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 269 | union { |
| 270 | struct { |
| 271 | /* our mbox written by others */ |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 272 | u32 wait[I915_NUM_ENGINES]; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 273 | /* mboxes this ring signals to */ |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 274 | i915_reg_t signal[I915_NUM_ENGINES]; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 275 | } mbox; |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 276 | u64 signal_ggtt[I915_NUM_ENGINES]; |
Ben Widawsky | 3e78998 | 2014-06-30 09:53:37 -0700 | [diff] [blame] | 277 | }; |
Ben Widawsky | 78325f2 | 2014-04-29 14:52:29 -0700 | [diff] [blame] | 278 | |
| 279 | /* AKA wait() */ |
Chris Wilson | ad7bdb2 | 2016-08-02 22:50:40 +0100 | [diff] [blame^] | 280 | int (*sync_to)(struct drm_i915_gem_request *req, |
| 281 | struct drm_i915_gem_request *signal); |
| 282 | int (*signal)(struct drm_i915_gem_request *req); |
Ben Widawsky | ebc348b | 2014-04-29 14:52:28 -0700 | [diff] [blame] | 283 | } semaphore; |
Ben Widawsky | ad776f8 | 2013-05-28 19:22:18 -0700 | [diff] [blame] | 284 | |
Oscar Mateo | 4da46e1 | 2014-07-24 17:04:27 +0100 | [diff] [blame] | 285 | /* Execlists */ |
Tvrtko Ursulin | 27af5ee | 2016-04-04 12:11:56 +0100 | [diff] [blame] | 286 | struct tasklet_struct irq_tasklet; |
| 287 | spinlock_t execlist_lock; /* used inside tasklet, use spin_lock_bh */ |
Michel Thierry | acdd884 | 2014-07-24 17:04:38 +0100 | [diff] [blame] | 288 | struct list_head execlist_queue; |
Tvrtko Ursulin | 3756685 | 2016-04-12 14:37:31 +0100 | [diff] [blame] | 289 | unsigned int fw_domains; |
Tvrtko Ursulin | c6a2ac7 | 2016-02-26 16:58:32 +0000 | [diff] [blame] | 290 | unsigned int next_context_status_buffer; |
| 291 | unsigned int idle_lite_restore_wa; |
Tvrtko Ursulin | ca82580c | 2016-01-15 15:10:27 +0000 | [diff] [blame] | 292 | bool disable_lite_restore_wa; |
| 293 | u32 ctx_desc_template; |
Oscar Mateo | 4da46e1 | 2014-07-24 17:04:27 +0100 | [diff] [blame] | 294 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 295 | /** |
| 296 | * List of objects currently involved in rendering from the |
| 297 | * ringbuffer. |
| 298 | * |
| 299 | * Includes buffers having the contents of their GPU caches |
John Harrison | 97b2a6a | 2014-11-24 18:49:26 +0000 | [diff] [blame] | 300 | * flushed, not necessarily primitives. last_read_req |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 301 | * represents when the rendering involved will be completed. |
| 302 | * |
| 303 | * A reference is held on the buffer while on this list. |
| 304 | */ |
| 305 | struct list_head active_list; |
| 306 | |
| 307 | /** |
| 308 | * List of breadcrumbs associated with GPU requests currently |
| 309 | * outstanding. |
| 310 | */ |
| 311 | struct list_head request_list; |
| 312 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 313 | /** |
Tomas Elf | 94f7bbe | 2015-07-09 15:30:57 +0100 | [diff] [blame] | 314 | * Seqno of request most recently submitted to request_list. |
| 315 | * Used exclusively by hang checker to avoid grabbing lock while |
| 316 | * inspecting request list. |
| 317 | */ |
| 318 | u32 last_submitted_seqno; |
| 319 | |
Chris Wilson | e2efd13 | 2016-05-24 14:53:34 +0100 | [diff] [blame] | 320 | struct i915_gem_context *last_context; |
Ben Widawsky | 4052105 | 2012-06-04 14:42:43 -0700 | [diff] [blame] | 321 | |
Chris Wilson | 7e37f88 | 2016-08-02 22:50:21 +0100 | [diff] [blame] | 322 | struct intel_engine_hangcheck hangcheck; |
Mika Kuoppala | 92cab73 | 2013-05-24 17:16:07 +0300 | [diff] [blame] | 323 | |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 324 | struct { |
| 325 | struct drm_i915_gem_object *obj; |
| 326 | u32 gtt_offset; |
Chris Wilson | 0d1aaca | 2013-08-26 20:58:11 +0100 | [diff] [blame] | 327 | } scratch; |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 328 | |
Brad Volkin | 44e895a | 2014-05-10 14:10:43 -0700 | [diff] [blame] | 329 | bool needs_cmd_parser; |
| 330 | |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 331 | /* |
Brad Volkin | 44e895a | 2014-05-10 14:10:43 -0700 | [diff] [blame] | 332 | * Table of commands the command parser needs to know about |
Chris Wilson | 33a051a | 2016-07-27 09:07:26 +0100 | [diff] [blame] | 333 | * for this engine. |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 334 | */ |
Brad Volkin | 44e895a | 2014-05-10 14:10:43 -0700 | [diff] [blame] | 335 | DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER); |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 336 | |
| 337 | /* |
| 338 | * Table of registers allowed in commands that read/write registers. |
| 339 | */ |
Jordan Justen | 361b027 | 2016-03-06 23:30:27 -0800 | [diff] [blame] | 340 | const struct drm_i915_reg_table *reg_tables; |
| 341 | int reg_table_count; |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 342 | |
| 343 | /* |
| 344 | * Returns the bitmask for the length field of the specified command. |
| 345 | * Return 0 for an unrecognized/invalid command. |
| 346 | * |
Chris Wilson | 33a051a | 2016-07-27 09:07:26 +0100 | [diff] [blame] | 347 | * If the command parser finds an entry for a command in the engine's |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 348 | * cmd_tables, it gets the command's length based on the table entry. |
Chris Wilson | 33a051a | 2016-07-27 09:07:26 +0100 | [diff] [blame] | 349 | * If not, it calls this function to determine the per-engine length |
| 350 | * field encoding for the command (i.e. different opcode ranges use |
| 351 | * certain bits to encode the command length in the header). |
Brad Volkin | 351e3db | 2014-02-18 10:15:46 -0800 | [diff] [blame] | 352 | */ |
| 353 | u32 (*get_cmd_length_mask)(u32 cmd_header); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 354 | }; |
| 355 | |
Dave Gordon | b0366a5 | 2015-12-08 15:02:36 +0000 | [diff] [blame] | 356 | static inline bool |
Chris Wilson | 67d97da | 2016-07-04 08:08:31 +0100 | [diff] [blame] | 357 | intel_engine_initialized(const struct intel_engine_cs *engine) |
Dave Gordon | b0366a5 | 2015-12-08 15:02:36 +0000 | [diff] [blame] | 358 | { |
Chris Wilson | c033666 | 2016-05-06 15:40:21 +0100 | [diff] [blame] | 359 | return engine->i915 != NULL; |
Dave Gordon | b0366a5 | 2015-12-08 15:02:36 +0000 | [diff] [blame] | 360 | } |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 361 | |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 362 | static inline unsigned |
Chris Wilson | 67d97da | 2016-07-04 08:08:31 +0100 | [diff] [blame] | 363 | intel_engine_flag(const struct intel_engine_cs *engine) |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 364 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 365 | return 1 << engine->id; |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 366 | } |
| 367 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 368 | static inline u32 |
Chris Wilson | 7e37f88 | 2016-08-02 22:50:21 +0100 | [diff] [blame] | 369 | intel_engine_sync_index(struct intel_engine_cs *engine, |
| 370 | struct intel_engine_cs *other) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 371 | { |
| 372 | int idx; |
| 373 | |
| 374 | /* |
Rodrigo Vivi | ddd4dbc | 2014-06-30 09:51:11 -0700 | [diff] [blame] | 375 | * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2; |
| 376 | * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs; |
| 377 | * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs; |
| 378 | * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs; |
| 379 | * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 380 | */ |
| 381 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 382 | idx = (other - engine) - 1; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 383 | if (idx < 0) |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 384 | idx += I915_NUM_ENGINES; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 385 | |
| 386 | return idx; |
| 387 | } |
| 388 | |
Imre Deak | 319404d | 2015-08-14 18:35:27 +0300 | [diff] [blame] | 389 | static inline void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 390 | intel_flush_status_page(struct intel_engine_cs *engine, int reg) |
Imre Deak | 319404d | 2015-08-14 18:35:27 +0300 | [diff] [blame] | 391 | { |
Chris Wilson | 0d317ce | 2016-04-09 10:57:56 +0100 | [diff] [blame] | 392 | mb(); |
| 393 | clflush(&engine->status_page.page_addr[reg]); |
| 394 | mb(); |
Imre Deak | 319404d | 2015-08-14 18:35:27 +0300 | [diff] [blame] | 395 | } |
| 396 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 397 | static inline u32 |
Chris Wilson | 5dd8e50 | 2016-04-09 10:57:57 +0100 | [diff] [blame] | 398 | intel_read_status_page(struct intel_engine_cs *engine, int reg) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 399 | { |
Daniel Vetter | 4225d0f | 2012-04-26 23:28:16 +0200 | [diff] [blame] | 400 | /* Ensure that the compiler doesn't optimize away the load. */ |
Chris Wilson | 5dd8e50 | 2016-04-09 10:57:57 +0100 | [diff] [blame] | 401 | return READ_ONCE(engine->status_page.page_addr[reg]); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 402 | } |
| 403 | |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 404 | static inline void |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 405 | intel_write_status_page(struct intel_engine_cs *engine, |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 406 | int reg, u32 value) |
| 407 | { |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 408 | engine->status_page.page_addr[reg] = value; |
Mika Kuoppala | b70ec5b | 2012-12-19 11:13:05 +0200 | [diff] [blame] | 409 | } |
| 410 | |
Jani Nikula | e282891 | 2016-01-18 09:19:47 +0200 | [diff] [blame] | 411 | /* |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 412 | * Reads a dword out of the status page, which is written to from the command |
| 413 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or |
| 414 | * MI_STORE_DATA_IMM. |
| 415 | * |
| 416 | * The following dwords have a reserved meaning: |
| 417 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. |
| 418 | * 0x04: ring 0 head pointer |
| 419 | * 0x05: ring 1 head pointer (915-class) |
| 420 | * 0x06: ring 2 head pointer (915-class) |
| 421 | * 0x10-0x1b: Context status DWords (GM45) |
| 422 | * 0x1f: Last written status offset. (GM45) |
Thomas Daniel | b07da53 | 2015-02-18 11:48:21 +0000 | [diff] [blame] | 423 | * 0x20-0x2f: Reserved (Gen6+) |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 424 | * |
Thomas Daniel | b07da53 | 2015-02-18 11:48:21 +0000 | [diff] [blame] | 425 | * The area from dword 0x30 to 0x3ff is available for driver usage. |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 426 | */ |
Thomas Daniel | b07da53 | 2015-02-18 11:48:21 +0000 | [diff] [blame] | 427 | #define I915_GEM_HWS_INDEX 0x30 |
Chris Wilson | 7c17d37 | 2016-01-20 15:43:35 +0200 | [diff] [blame] | 428 | #define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
Thomas Daniel | b07da53 | 2015-02-18 11:48:21 +0000 | [diff] [blame] | 429 | #define I915_GEM_HWS_SCRATCH_INDEX 0x40 |
Jesse Barnes | 9a28977 | 2012-10-26 09:42:42 -0700 | [diff] [blame] | 430 | #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
Chris Wilson | 311bd68 | 2011-01-13 19:06:50 +0000 | [diff] [blame] | 431 | |
Chris Wilson | 7e37f88 | 2016-08-02 22:50:21 +0100 | [diff] [blame] | 432 | struct intel_ring * |
| 433 | intel_engine_create_ring(struct intel_engine_cs *engine, int size); |
Chris Wilson | aad29fb | 2016-08-02 22:50:23 +0100 | [diff] [blame] | 434 | int intel_ring_pin(struct intel_ring *ring); |
| 435 | void intel_ring_unpin(struct intel_ring *ring); |
Chris Wilson | 7e37f88 | 2016-08-02 22:50:21 +0100 | [diff] [blame] | 436 | void intel_ring_free(struct intel_ring *ring); |
Oscar Mateo | 84c2377 | 2014-07-24 17:04:15 +0100 | [diff] [blame] | 437 | |
Chris Wilson | 7e37f88 | 2016-08-02 22:50:21 +0100 | [diff] [blame] | 438 | void intel_engine_stop(struct intel_engine_cs *engine); |
| 439 | void intel_engine_cleanup(struct intel_engine_cs *engine); |
Ben Widawsky | 96f298a | 2011-03-19 18:14:27 -0700 | [diff] [blame] | 440 | |
John Harrison | 6689cb2 | 2015-03-19 12:30:08 +0000 | [diff] [blame] | 441 | int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request); |
| 442 | |
John Harrison | 5fb9de1 | 2015-05-29 17:44:07 +0100 | [diff] [blame] | 443 | int __must_check intel_ring_begin(struct drm_i915_gem_request *req, int n); |
John Harrison | bba09b1 | 2015-05-29 17:44:06 +0100 | [diff] [blame] | 444 | int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req); |
Chris Wilson | 406ea8d | 2016-07-20 13:31:55 +0100 | [diff] [blame] | 445 | |
Chris Wilson | 7e37f88 | 2016-08-02 22:50:21 +0100 | [diff] [blame] | 446 | static inline void intel_ring_emit(struct intel_ring *ring, u32 data) |
Chris Wilson | e898cd2 | 2010-08-04 15:18:14 +0100 | [diff] [blame] | 447 | { |
Chris Wilson | b5321f3 | 2016-08-02 22:50:18 +0100 | [diff] [blame] | 448 | *(uint32_t *)(ring->vaddr + ring->tail) = data; |
| 449 | ring->tail += 4; |
Chris Wilson | e898cd2 | 2010-08-04 15:18:14 +0100 | [diff] [blame] | 450 | } |
Chris Wilson | 406ea8d | 2016-07-20 13:31:55 +0100 | [diff] [blame] | 451 | |
Chris Wilson | 7e37f88 | 2016-08-02 22:50:21 +0100 | [diff] [blame] | 452 | static inline void intel_ring_emit_reg(struct intel_ring *ring, i915_reg_t reg) |
Ville Syrjälä | f92a916 | 2015-11-04 23:20:07 +0200 | [diff] [blame] | 453 | { |
Chris Wilson | b5321f3 | 2016-08-02 22:50:18 +0100 | [diff] [blame] | 454 | intel_ring_emit(ring, i915_mmio_reg_offset(reg)); |
Ville Syrjälä | f92a916 | 2015-11-04 23:20:07 +0200 | [diff] [blame] | 455 | } |
Chris Wilson | 406ea8d | 2016-07-20 13:31:55 +0100 | [diff] [blame] | 456 | |
Chris Wilson | 7e37f88 | 2016-08-02 22:50:21 +0100 | [diff] [blame] | 457 | static inline void intel_ring_advance(struct intel_ring *ring) |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 458 | { |
Chris Wilson | 8f94201 | 2016-08-02 22:50:30 +0100 | [diff] [blame] | 459 | /* Dummy function. |
| 460 | * |
| 461 | * This serves as a placeholder in the code so that the reader |
| 462 | * can compare against the preceding intel_ring_begin() and |
| 463 | * check that the number of dwords emitted matches the space |
| 464 | * reserved for the command packet (i.e. the value passed to |
| 465 | * intel_ring_begin()). |
Chris Wilson | c5efa1a | 2016-08-02 22:50:29 +0100 | [diff] [blame] | 466 | */ |
Chris Wilson | 8f94201 | 2016-08-02 22:50:30 +0100 | [diff] [blame] | 467 | } |
| 468 | |
| 469 | static inline u32 intel_ring_offset(struct intel_ring *ring, u32 value) |
| 470 | { |
| 471 | /* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */ |
| 472 | return value & (ring->size - 1); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 473 | } |
Chris Wilson | 406ea8d | 2016-07-20 13:31:55 +0100 | [diff] [blame] | 474 | |
Oscar Mateo | 82e104c | 2014-07-24 17:04:26 +0100 | [diff] [blame] | 475 | int __intel_ring_space(int head, int tail, int size); |
Chris Wilson | 32c04f1 | 2016-08-02 22:50:22 +0100 | [diff] [blame] | 476 | void intel_ring_update_space(struct intel_ring *ring); |
Chris Wilson | 0924673 | 2013-08-10 22:16:32 +0100 | [diff] [blame] | 477 | |
Tvrtko Ursulin | 666796d | 2016-03-16 11:00:39 +0000 | [diff] [blame] | 478 | int __must_check intel_engine_idle(struct intel_engine_cs *engine); |
Chris Wilson | 7e37f88 | 2016-08-02 22:50:21 +0100 | [diff] [blame] | 479 | void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 480 | |
Chris Wilson | 7d5ea80 | 2016-07-01 17:23:20 +0100 | [diff] [blame] | 481 | int intel_init_pipe_control(struct intel_engine_cs *engine, int size); |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 482 | void intel_fini_pipe_control(struct intel_engine_cs *engine); |
Oscar Mateo | 9b1136d | 2014-07-24 17:04:24 +0100 | [diff] [blame] | 483 | |
Tvrtko Ursulin | 019bf27 | 2016-07-13 16:03:41 +0100 | [diff] [blame] | 484 | void intel_engine_setup_common(struct intel_engine_cs *engine); |
| 485 | int intel_engine_init_common(struct intel_engine_cs *engine); |
| 486 | |
Tvrtko Ursulin | 8b3e2d3 | 2016-07-13 16:03:37 +0100 | [diff] [blame] | 487 | int intel_init_render_ring_buffer(struct intel_engine_cs *engine); |
| 488 | int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine); |
| 489 | int intel_init_bsd2_ring_buffer(struct intel_engine_cs *engine); |
| 490 | int intel_init_blt_ring_buffer(struct intel_engine_cs *engine); |
| 491 | int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 492 | |
Chris Wilson | 7e37f88 | 2016-08-02 22:50:21 +0100 | [diff] [blame] | 493 | u64 intel_engine_get_active_head(struct intel_engine_cs *engine); |
Chris Wilson | 1b7744e | 2016-07-01 17:23:17 +0100 | [diff] [blame] | 494 | static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine) |
| 495 | { |
| 496 | return intel_read_status_page(engine, I915_GEM_HWS_INDEX); |
| 497 | } |
Daniel Vetter | 79f321b | 2010-09-24 21:20:10 +0200 | [diff] [blame] | 498 | |
Tvrtko Ursulin | 0bc40be | 2016-03-16 11:00:37 +0000 | [diff] [blame] | 499 | int init_workarounds_ring(struct intel_engine_cs *engine); |
Michel Thierry | 771b9a5 | 2014-11-11 16:47:33 +0000 | [diff] [blame] | 500 | |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 501 | /* |
| 502 | * Arbitrary size for largest possible 'add request' sequence. The code paths |
| 503 | * are complex and variable. Empirical measurement shows that the worst case |
Chris Wilson | 596e5ef | 2016-04-29 09:07:04 +0100 | [diff] [blame] | 504 | * is BDW at 192 bytes (6 + 6 + 36 dwords), then ILK at 136 bytes. However, |
| 505 | * we need to allocate double the largest single packet within that emission |
| 506 | * to account for tail wraparound (so 6 + 6 + 72 dwords for BDW). |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 507 | */ |
Chris Wilson | 596e5ef | 2016-04-29 09:07:04 +0100 | [diff] [blame] | 508 | #define MIN_SPACE_FOR_ADD_REQUEST 336 |
John Harrison | 29b1b41 | 2015-06-18 13:10:09 +0100 | [diff] [blame] | 509 | |
Chris Wilson | a58c01a | 2016-04-29 13:18:21 +0100 | [diff] [blame] | 510 | static inline u32 intel_hws_seqno_address(struct intel_engine_cs *engine) |
| 511 | { |
| 512 | return engine->status_page.gfx_addr + I915_GEM_HWS_INDEX_ADDR; |
| 513 | } |
| 514 | |
Chris Wilson | 688e6c7 | 2016-07-01 17:23:15 +0100 | [diff] [blame] | 515 | /* intel_breadcrumbs.c -- user interrupt bottom-half for waiters */ |
| 516 | struct intel_wait { |
| 517 | struct rb_node node; |
| 518 | struct task_struct *tsk; |
| 519 | u32 seqno; |
| 520 | }; |
| 521 | |
Chris Wilson | b385085 | 2016-07-01 17:23:26 +0100 | [diff] [blame] | 522 | struct intel_signal_node { |
| 523 | struct rb_node node; |
| 524 | struct intel_wait wait; |
| 525 | }; |
| 526 | |
Chris Wilson | 688e6c7 | 2016-07-01 17:23:15 +0100 | [diff] [blame] | 527 | int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine); |
| 528 | |
| 529 | static inline void intel_wait_init(struct intel_wait *wait, u32 seqno) |
| 530 | { |
| 531 | wait->tsk = current; |
| 532 | wait->seqno = seqno; |
| 533 | } |
| 534 | |
| 535 | static inline bool intel_wait_complete(const struct intel_wait *wait) |
| 536 | { |
| 537 | return RB_EMPTY_NODE(&wait->node); |
| 538 | } |
| 539 | |
| 540 | bool intel_engine_add_wait(struct intel_engine_cs *engine, |
| 541 | struct intel_wait *wait); |
| 542 | void intel_engine_remove_wait(struct intel_engine_cs *engine, |
| 543 | struct intel_wait *wait); |
Chris Wilson | b385085 | 2016-07-01 17:23:26 +0100 | [diff] [blame] | 544 | void intel_engine_enable_signaling(struct drm_i915_gem_request *request); |
Chris Wilson | 688e6c7 | 2016-07-01 17:23:15 +0100 | [diff] [blame] | 545 | |
| 546 | static inline bool intel_engine_has_waiter(struct intel_engine_cs *engine) |
| 547 | { |
Chris Wilson | aca34b6 | 2016-07-06 12:39:02 +0100 | [diff] [blame] | 548 | return READ_ONCE(engine->breadcrumbs.irq_seqno_bh); |
Chris Wilson | 688e6c7 | 2016-07-01 17:23:15 +0100 | [diff] [blame] | 549 | } |
| 550 | |
| 551 | static inline bool intel_engine_wakeup(struct intel_engine_cs *engine) |
| 552 | { |
| 553 | bool wakeup = false; |
Chris Wilson | aca34b6 | 2016-07-06 12:39:02 +0100 | [diff] [blame] | 554 | struct task_struct *tsk = READ_ONCE(engine->breadcrumbs.irq_seqno_bh); |
Chris Wilson | 688e6c7 | 2016-07-01 17:23:15 +0100 | [diff] [blame] | 555 | /* Note that for this not to dangerously chase a dangling pointer, |
| 556 | * the caller is responsible for ensure that the task remain valid for |
| 557 | * wake_up_process() i.e. that the RCU grace period cannot expire. |
| 558 | * |
| 559 | * Also note that tsk is likely to be in !TASK_RUNNING state so an |
| 560 | * early test for tsk->state != TASK_RUNNING before wake_up_process() |
| 561 | * is unlikely to be beneficial. |
| 562 | */ |
| 563 | if (tsk) |
| 564 | wakeup = wake_up_process(tsk); |
| 565 | return wakeup; |
| 566 | } |
| 567 | |
| 568 | void intel_engine_enable_fake_irq(struct intel_engine_cs *engine); |
| 569 | void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine); |
| 570 | unsigned int intel_kick_waiters(struct drm_i915_private *i915); |
Chris Wilson | c81d461 | 2016-07-01 17:23:25 +0100 | [diff] [blame] | 571 | unsigned int intel_kick_signalers(struct drm_i915_private *i915); |
Chris Wilson | 688e6c7 | 2016-07-01 17:23:15 +0100 | [diff] [blame] | 572 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 573 | #endif /* _INTEL_RINGBUFFER_H_ */ |