Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Samsung SoC DP (Display Port) interface driver. |
| 3 | * |
| 4 | * Copyright (C) 2012 Samsung Electronics Co., Ltd. |
| 5 | * Author: Jingoo Han <jg1.han@samsung.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License as published by the |
| 9 | * Free Software Foundation; either version 2 of the License, or (at your |
| 10 | * option) any later version. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/platform_device.h> |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 15 | #include <linux/err.h> |
| 16 | #include <linux/clk.h> |
| 17 | #include <linux/io.h> |
| 18 | #include <linux/interrupt.h> |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 19 | #include <linux/of.h> |
Andrew Bresticker | b8b5247 | 2014-04-22 04:09:10 +0530 | [diff] [blame] | 20 | #include <linux/of_gpio.h> |
Ajay Kumar | 8018556 | 2015-01-20 22:08:46 +0530 | [diff] [blame] | 21 | #include <linux/of_graph.h> |
Andrew Bresticker | b8b5247 | 2014-04-22 04:09:10 +0530 | [diff] [blame] | 22 | #include <linux/gpio.h> |
Inki Dae | f37cd5e | 2014-05-09 14:25:20 +0900 | [diff] [blame] | 23 | #include <linux/component.h> |
Jingoo Han | 8114fab | 2013-10-16 21:58:16 +0530 | [diff] [blame] | 24 | #include <linux/phy/phy.h> |
Sean Paul | 1417f10 | 2014-01-30 16:19:23 -0500 | [diff] [blame] | 25 | #include <video/of_display_timing.h> |
| 26 | #include <video/of_videomode.h> |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 27 | |
Sean Paul | 1417f10 | 2014-01-30 16:19:23 -0500 | [diff] [blame] | 28 | #include <drm/drmP.h> |
Sean Paul | caa5d1e | 2014-01-30 16:19:30 -0500 | [diff] [blame] | 29 | #include <drm/drm_crtc.h> |
| 30 | #include <drm/drm_crtc_helper.h> |
Gustavo Padovan | 4ea9526 | 2015-06-01 12:04:44 -0300 | [diff] [blame] | 31 | #include <drm/drm_atomic_helper.h> |
Ajay Kumar | 5f1dcd8 | 2014-07-31 23:12:14 +0530 | [diff] [blame] | 32 | #include <drm/drm_panel.h> |
Sean Paul | 1417f10 | 2014-01-30 16:19:23 -0500 | [diff] [blame] | 33 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 34 | #include "exynos_dp_core.h" |
| 35 | |
Sean Paul | caa5d1e | 2014-01-30 16:19:30 -0500 | [diff] [blame] | 36 | #define ctx_from_connector(c) container_of(c, struct exynos_dp_device, \ |
| 37 | connector) |
| 38 | |
Krzysztof Kozlowski | 1c363c7 | 2015-04-07 22:28:50 +0900 | [diff] [blame] | 39 | static inline struct exynos_drm_crtc *dp_to_crtc(struct exynos_dp_device *dp) |
| 40 | { |
| 41 | return to_exynos_crtc(dp->encoder->crtc); |
| 42 | } |
| 43 | |
Andrzej Hajda | 63b3be3 | 2014-11-17 09:54:25 +0100 | [diff] [blame] | 44 | static inline struct exynos_dp_device * |
| 45 | display_to_dp(struct exynos_drm_display *d) |
| 46 | { |
| 47 | return container_of(d, struct exynos_dp_device, display); |
| 48 | } |
| 49 | |
Sean Paul | 1634ba2 | 2014-02-24 19:20:15 +0900 | [diff] [blame] | 50 | struct bridge_init { |
| 51 | struct i2c_client *client; |
| 52 | struct device_node *node; |
| 53 | }; |
| 54 | |
Ajay Kumar | 5f1dcd8 | 2014-07-31 23:12:14 +0530 | [diff] [blame] | 55 | static void exynos_dp_init_dp(struct exynos_dp_device *dp) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 56 | { |
| 57 | exynos_dp_reset(dp); |
| 58 | |
Jingoo Han | 24db03a | 2012-05-25 16:21:08 +0900 | [diff] [blame] | 59 | exynos_dp_swreset(dp); |
| 60 | |
Jingoo Han | 75435c7 | 2012-08-23 19:55:13 +0900 | [diff] [blame] | 61 | exynos_dp_init_analog_param(dp); |
| 62 | exynos_dp_init_interrupt(dp); |
| 63 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 64 | /* SW defined function Normal operation */ |
| 65 | exynos_dp_enable_sw_function(dp); |
| 66 | |
| 67 | exynos_dp_config_interrupt(dp); |
| 68 | exynos_dp_init_analog_func(dp); |
| 69 | |
| 70 | exynos_dp_init_hpd(dp); |
| 71 | exynos_dp_init_aux(dp); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 72 | } |
| 73 | |
| 74 | static int exynos_dp_detect_hpd(struct exynos_dp_device *dp) |
| 75 | { |
| 76 | int timeout_loop = 0; |
| 77 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 78 | while (exynos_dp_get_plug_in_status(dp) != 0) { |
| 79 | timeout_loop++; |
| 80 | if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { |
| 81 | dev_err(dp->dev, "failed to get hpd plug status\n"); |
| 82 | return -ETIMEDOUT; |
| 83 | } |
Jingoo Han | a2c81bc | 2012-07-18 18:50:59 +0900 | [diff] [blame] | 84 | usleep_range(10, 11); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 85 | } |
| 86 | |
| 87 | return 0; |
| 88 | } |
| 89 | |
| 90 | static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data) |
| 91 | { |
| 92 | int i; |
| 93 | unsigned char sum = 0; |
| 94 | |
| 95 | for (i = 0; i < EDID_BLOCK_LENGTH; i++) |
| 96 | sum = sum + edid_data[i]; |
| 97 | |
| 98 | return sum; |
| 99 | } |
| 100 | |
| 101 | static int exynos_dp_read_edid(struct exynos_dp_device *dp) |
| 102 | { |
| 103 | unsigned char edid[EDID_BLOCK_LENGTH * 2]; |
| 104 | unsigned int extend_block = 0; |
| 105 | unsigned char sum; |
| 106 | unsigned char test_vector; |
| 107 | int retval; |
| 108 | |
| 109 | /* |
| 110 | * EDID device address is 0x50. |
| 111 | * However, if necessary, you must have set upper address |
| 112 | * into E-EDID in I2C device, 0x30. |
| 113 | */ |
| 114 | |
| 115 | /* Read Extension Flag, Number of 128-byte EDID extension blocks */ |
Sean Paul | 99f5415 | 2012-11-01 02:13:00 +0000 | [diff] [blame] | 116 | retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR, |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 117 | EDID_EXTENSION_FLAG, |
| 118 | &extend_block); |
Sean Paul | 99f5415 | 2012-11-01 02:13:00 +0000 | [diff] [blame] | 119 | if (retval) |
| 120 | return retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 121 | |
| 122 | if (extend_block > 0) { |
| 123 | dev_dbg(dp->dev, "EDID data includes a single extension!\n"); |
| 124 | |
| 125 | /* Read EDID data */ |
| 126 | retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR, |
| 127 | EDID_HEADER_PATTERN, |
| 128 | EDID_BLOCK_LENGTH, |
| 129 | &edid[EDID_HEADER_PATTERN]); |
| 130 | if (retval != 0) { |
| 131 | dev_err(dp->dev, "EDID Read failed!\n"); |
| 132 | return -EIO; |
| 133 | } |
| 134 | sum = exynos_dp_calc_edid_check_sum(edid); |
| 135 | if (sum != 0) { |
| 136 | dev_err(dp->dev, "EDID bad checksum!\n"); |
| 137 | return -EIO; |
| 138 | } |
| 139 | |
| 140 | /* Read additional EDID data */ |
| 141 | retval = exynos_dp_read_bytes_from_i2c(dp, |
| 142 | I2C_EDID_DEVICE_ADDR, |
| 143 | EDID_BLOCK_LENGTH, |
| 144 | EDID_BLOCK_LENGTH, |
| 145 | &edid[EDID_BLOCK_LENGTH]); |
| 146 | if (retval != 0) { |
| 147 | dev_err(dp->dev, "EDID Read failed!\n"); |
| 148 | return -EIO; |
| 149 | } |
| 150 | sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]); |
| 151 | if (sum != 0) { |
| 152 | dev_err(dp->dev, "EDID bad checksum!\n"); |
| 153 | return -EIO; |
| 154 | } |
| 155 | |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 156 | exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST, |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 157 | &test_vector); |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 158 | if (test_vector & DP_TEST_LINK_EDID_READ) { |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 159 | exynos_dp_write_byte_to_dpcd(dp, |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 160 | DP_TEST_EDID_CHECKSUM, |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 161 | edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]); |
| 162 | exynos_dp_write_byte_to_dpcd(dp, |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 163 | DP_TEST_RESPONSE, |
| 164 | DP_TEST_EDID_CHECKSUM_WRITE); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 165 | } |
| 166 | } else { |
| 167 | dev_info(dp->dev, "EDID data does not include any extensions.\n"); |
| 168 | |
| 169 | /* Read EDID data */ |
| 170 | retval = exynos_dp_read_bytes_from_i2c(dp, |
| 171 | I2C_EDID_DEVICE_ADDR, |
| 172 | EDID_HEADER_PATTERN, |
| 173 | EDID_BLOCK_LENGTH, |
| 174 | &edid[EDID_HEADER_PATTERN]); |
| 175 | if (retval != 0) { |
| 176 | dev_err(dp->dev, "EDID Read failed!\n"); |
| 177 | return -EIO; |
| 178 | } |
| 179 | sum = exynos_dp_calc_edid_check_sum(edid); |
| 180 | if (sum != 0) { |
| 181 | dev_err(dp->dev, "EDID bad checksum!\n"); |
| 182 | return -EIO; |
| 183 | } |
| 184 | |
| 185 | exynos_dp_read_byte_from_dpcd(dp, |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 186 | DP_TEST_REQUEST, |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 187 | &test_vector); |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 188 | if (test_vector & DP_TEST_LINK_EDID_READ) { |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 189 | exynos_dp_write_byte_to_dpcd(dp, |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 190 | DP_TEST_EDID_CHECKSUM, |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 191 | edid[EDID_CHECKSUM]); |
| 192 | exynos_dp_write_byte_to_dpcd(dp, |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 193 | DP_TEST_RESPONSE, |
| 194 | DP_TEST_EDID_CHECKSUM_WRITE); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 195 | } |
| 196 | } |
| 197 | |
Krzysztof Kozlowski | b0f155a | 2015-05-14 09:03:06 +0900 | [diff] [blame] | 198 | dev_dbg(dp->dev, "EDID Read success!\n"); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 199 | return 0; |
| 200 | } |
| 201 | |
| 202 | static int exynos_dp_handle_edid(struct exynos_dp_device *dp) |
| 203 | { |
| 204 | u8 buf[12]; |
| 205 | int i; |
| 206 | int retval; |
| 207 | |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 208 | /* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */ |
| 209 | retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, |
Sean Paul | 99f5415 | 2012-11-01 02:13:00 +0000 | [diff] [blame] | 210 | 12, buf); |
| 211 | if (retval) |
| 212 | return retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 213 | |
| 214 | /* Read EDID */ |
| 215 | for (i = 0; i < 3; i++) { |
| 216 | retval = exynos_dp_read_edid(dp); |
Sean Paul | 99f5415 | 2012-11-01 02:13:00 +0000 | [diff] [blame] | 217 | if (!retval) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 218 | break; |
| 219 | } |
| 220 | |
| 221 | return retval; |
| 222 | } |
| 223 | |
| 224 | static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp, |
| 225 | bool enable) |
| 226 | { |
| 227 | u8 data; |
| 228 | |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 229 | exynos_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 230 | |
| 231 | if (enable) |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 232 | exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, |
| 233 | DP_LANE_COUNT_ENHANCED_FRAME_EN | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 234 | DPCD_LANE_COUNT_SET(data)); |
| 235 | else |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 236 | exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET, |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 237 | DPCD_LANE_COUNT_SET(data)); |
| 238 | } |
| 239 | |
| 240 | static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp) |
| 241 | { |
| 242 | u8 data; |
| 243 | int retval; |
| 244 | |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 245 | exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 246 | retval = DPCD_ENHANCED_FRAME_CAP(data); |
| 247 | |
| 248 | return retval; |
| 249 | } |
| 250 | |
| 251 | static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp) |
| 252 | { |
| 253 | u8 data; |
| 254 | |
| 255 | data = exynos_dp_is_enhanced_mode_available(dp); |
| 256 | exynos_dp_enable_rx_to_enhanced_mode(dp, data); |
| 257 | exynos_dp_enable_enhanced_mode(dp, data); |
| 258 | } |
| 259 | |
| 260 | static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp) |
| 261 | { |
| 262 | exynos_dp_set_training_pattern(dp, DP_NONE); |
| 263 | |
| 264 | exynos_dp_write_byte_to_dpcd(dp, |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 265 | DP_TRAINING_PATTERN_SET, |
| 266 | DP_TRAINING_PATTERN_DISABLE); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 267 | } |
| 268 | |
| 269 | static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp, |
| 270 | int pre_emphasis, int lane) |
| 271 | { |
| 272 | switch (lane) { |
| 273 | case 0: |
| 274 | exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis); |
| 275 | break; |
| 276 | case 1: |
| 277 | exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis); |
| 278 | break; |
| 279 | |
| 280 | case 2: |
| 281 | exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis); |
| 282 | break; |
| 283 | |
| 284 | case 3: |
| 285 | exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis); |
| 286 | break; |
| 287 | } |
| 288 | } |
| 289 | |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 290 | static int exynos_dp_link_start(struct exynos_dp_device *dp) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 291 | { |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 292 | u8 buf[4]; |
Sean Paul | 49ce41f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 293 | int lane, lane_count, pll_tries, retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 294 | |
| 295 | lane_count = dp->link_train.lane_count; |
| 296 | |
| 297 | dp->link_train.lt_state = CLOCK_RECOVERY; |
| 298 | dp->link_train.eq_loop = 0; |
| 299 | |
| 300 | for (lane = 0; lane < lane_count; lane++) |
| 301 | dp->link_train.cr_loop[lane] = 0; |
| 302 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 303 | /* Set link rate and count as you want to establish*/ |
| 304 | exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate); |
| 305 | exynos_dp_set_lane_count(dp, dp->link_train.lane_count); |
| 306 | |
| 307 | /* Setup RX configuration */ |
| 308 | buf[0] = dp->link_train.link_rate; |
| 309 | buf[1] = dp->link_train.lane_count; |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 310 | retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 311 | 2, buf); |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 312 | if (retval) |
| 313 | return retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 314 | |
| 315 | /* Set TX pre-emphasis to minimum */ |
| 316 | for (lane = 0; lane < lane_count; lane++) |
| 317 | exynos_dp_set_lane_lane_pre_emphasis(dp, |
| 318 | PRE_EMPHASIS_LEVEL_0, lane); |
| 319 | |
Sean Paul | 49ce41f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 320 | /* Wait for PLL lock */ |
| 321 | pll_tries = 0; |
| 322 | while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { |
| 323 | if (pll_tries == DP_TIMEOUT_LOOP_COUNT) { |
| 324 | dev_err(dp->dev, "Wait for PLL lock timed out\n"); |
| 325 | return -ETIMEDOUT; |
| 326 | } |
| 327 | |
| 328 | pll_tries++; |
| 329 | usleep_range(90, 120); |
| 330 | } |
| 331 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 332 | /* Set training pattern 1 */ |
| 333 | exynos_dp_set_training_pattern(dp, TRAINING_PTN1); |
| 334 | |
| 335 | /* Set RX training pattern */ |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 336 | retval = exynos_dp_write_byte_to_dpcd(dp, |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 337 | DP_TRAINING_PATTERN_SET, |
| 338 | DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1); |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 339 | if (retval) |
| 340 | return retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 341 | |
| 342 | for (lane = 0; lane < lane_count; lane++) |
Sonika Jindal | 0ded925 | 2014-08-08 16:23:42 +0530 | [diff] [blame] | 343 | buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 | |
| 344 | DP_TRAIN_VOLTAGE_SWING_LEVEL_0; |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 345 | |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 346 | retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 347 | lane_count, buf); |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 348 | |
| 349 | return retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 350 | } |
| 351 | |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 352 | static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 353 | { |
| 354 | int shift = (lane & 1) * 4; |
| 355 | u8 link_value = link_status[lane>>1]; |
| 356 | |
| 357 | return (link_value >> shift) & 0xf; |
| 358 | } |
| 359 | |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 360 | static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 361 | { |
| 362 | int lane; |
| 363 | u8 lane_status; |
| 364 | |
| 365 | for (lane = 0; lane < lane_count; lane++) { |
| 366 | lane_status = exynos_dp_get_lane_status(link_status, lane); |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 367 | if ((lane_status & DP_LANE_CR_DONE) == 0) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 368 | return -EINVAL; |
| 369 | } |
| 370 | return 0; |
| 371 | } |
| 372 | |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 373 | static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align, |
| 374 | int lane_count) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 375 | { |
| 376 | int lane; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 377 | u8 lane_status; |
| 378 | |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 379 | if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 380 | return -EINVAL; |
| 381 | |
| 382 | for (lane = 0; lane < lane_count; lane++) { |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 383 | lane_status = exynos_dp_get_lane_status(link_status, lane); |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 384 | lane_status &= DP_CHANNEL_EQ_BITS; |
| 385 | if (lane_status != DP_CHANNEL_EQ_BITS) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 386 | return -EINVAL; |
| 387 | } |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 388 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 389 | return 0; |
| 390 | } |
| 391 | |
| 392 | static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2], |
| 393 | int lane) |
| 394 | { |
| 395 | int shift = (lane & 1) * 4; |
| 396 | u8 link_value = adjust_request[lane>>1]; |
| 397 | |
| 398 | return (link_value >> shift) & 0x3; |
| 399 | } |
| 400 | |
| 401 | static unsigned char exynos_dp_get_adjust_request_pre_emphasis( |
| 402 | u8 adjust_request[2], |
| 403 | int lane) |
| 404 | { |
| 405 | int shift = (lane & 1) * 4; |
| 406 | u8 link_value = adjust_request[lane>>1]; |
| 407 | |
| 408 | return ((link_value >> shift) & 0xc) >> 2; |
| 409 | } |
| 410 | |
| 411 | static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp, |
| 412 | u8 training_lane_set, int lane) |
| 413 | { |
| 414 | switch (lane) { |
| 415 | case 0: |
| 416 | exynos_dp_set_lane0_link_training(dp, training_lane_set); |
| 417 | break; |
| 418 | case 1: |
| 419 | exynos_dp_set_lane1_link_training(dp, training_lane_set); |
| 420 | break; |
| 421 | |
| 422 | case 2: |
| 423 | exynos_dp_set_lane2_link_training(dp, training_lane_set); |
| 424 | break; |
| 425 | |
| 426 | case 3: |
| 427 | exynos_dp_set_lane3_link_training(dp, training_lane_set); |
| 428 | break; |
| 429 | } |
| 430 | } |
| 431 | |
| 432 | static unsigned int exynos_dp_get_lane_link_training( |
| 433 | struct exynos_dp_device *dp, |
| 434 | int lane) |
| 435 | { |
| 436 | u32 reg; |
| 437 | |
| 438 | switch (lane) { |
| 439 | case 0: |
| 440 | reg = exynos_dp_get_lane0_link_training(dp); |
| 441 | break; |
| 442 | case 1: |
| 443 | reg = exynos_dp_get_lane1_link_training(dp); |
| 444 | break; |
| 445 | case 2: |
| 446 | reg = exynos_dp_get_lane2_link_training(dp); |
| 447 | break; |
| 448 | case 3: |
| 449 | reg = exynos_dp_get_lane3_link_training(dp); |
| 450 | break; |
Jingoo Han | 64c43df | 2012-06-20 10:25:48 +0900 | [diff] [blame] | 451 | default: |
| 452 | WARN_ON(1); |
| 453 | return 0; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 454 | } |
| 455 | |
| 456 | return reg; |
| 457 | } |
| 458 | |
| 459 | static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp) |
| 460 | { |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 461 | exynos_dp_training_pattern_dis(dp); |
| 462 | exynos_dp_set_enhanced_mode(dp); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 463 | |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 464 | dp->link_train.lt_state = FAILED; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 465 | } |
| 466 | |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 467 | static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp, |
| 468 | u8 adjust_request[2]) |
| 469 | { |
| 470 | int lane, lane_count; |
| 471 | u8 voltage_swing, pre_emphasis, training_lane; |
| 472 | |
| 473 | lane_count = dp->link_train.lane_count; |
| 474 | for (lane = 0; lane < lane_count; lane++) { |
| 475 | voltage_swing = exynos_dp_get_adjust_request_voltage( |
| 476 | adjust_request, lane); |
| 477 | pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( |
| 478 | adjust_request, lane); |
| 479 | training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) | |
| 480 | DPCD_PRE_EMPHASIS_SET(pre_emphasis); |
| 481 | |
| 482 | if (voltage_swing == VOLTAGE_LEVEL_3) |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 483 | training_lane |= DP_TRAIN_MAX_SWING_REACHED; |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 484 | if (pre_emphasis == PRE_EMPHASIS_LEVEL_3) |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 485 | training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 486 | |
| 487 | dp->link_train.training_lane[lane] = training_lane; |
| 488 | } |
| 489 | } |
| 490 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 491 | static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) |
| 492 | { |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 493 | int lane, lane_count, retval; |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 494 | u8 voltage_swing, pre_emphasis, training_lane; |
| 495 | u8 link_status[2], adjust_request[2]; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 496 | |
Jingoo Han | a2c81bc | 2012-07-18 18:50:59 +0900 | [diff] [blame] | 497 | usleep_range(100, 101); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 498 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 499 | lane_count = dp->link_train.lane_count; |
| 500 | |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 501 | retval = exynos_dp_read_bytes_from_dpcd(dp, |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 502 | DP_LANE0_1_STATUS, 2, link_status); |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 503 | if (retval) |
| 504 | return retval; |
| 505 | |
| 506 | retval = exynos_dp_read_bytes_from_dpcd(dp, |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 507 | DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 508 | if (retval) |
| 509 | return retval; |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 510 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 511 | if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) { |
| 512 | /* set training pattern 2 for EQ */ |
| 513 | exynos_dp_set_training_pattern(dp, TRAINING_PTN2); |
| 514 | |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 515 | retval = exynos_dp_write_byte_to_dpcd(dp, |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 516 | DP_TRAINING_PATTERN_SET, |
| 517 | DP_LINK_SCRAMBLING_DISABLE | |
| 518 | DP_TRAINING_PATTERN_2); |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 519 | if (retval) |
| 520 | return retval; |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 521 | |
| 522 | dev_info(dp->dev, "Link Training Clock Recovery success\n"); |
| 523 | dp->link_train.lt_state = EQUALIZER_TRAINING; |
| 524 | } else { |
| 525 | for (lane = 0; lane < lane_count; lane++) { |
| 526 | training_lane = exynos_dp_get_lane_link_training( |
| 527 | dp, lane); |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 528 | voltage_swing = exynos_dp_get_adjust_request_voltage( |
| 529 | adjust_request, lane); |
| 530 | pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( |
| 531 | adjust_request, lane); |
| 532 | |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 533 | if (DPCD_VOLTAGE_SWING_GET(training_lane) == |
| 534 | voltage_swing && |
| 535 | DPCD_PRE_EMPHASIS_GET(training_lane) == |
| 536 | pre_emphasis) |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 537 | dp->link_train.cr_loop[lane]++; |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 538 | |
| 539 | if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP || |
| 540 | voltage_swing == VOLTAGE_LEVEL_3 || |
| 541 | pre_emphasis == PRE_EMPHASIS_LEVEL_3) { |
| 542 | dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n", |
| 543 | dp->link_train.cr_loop[lane], |
| 544 | voltage_swing, pre_emphasis); |
| 545 | exynos_dp_reduce_link_rate(dp); |
| 546 | return -EIO; |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 547 | } |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 548 | } |
| 549 | } |
| 550 | |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 551 | exynos_dp_get_adjust_training_lane(dp, adjust_request); |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 552 | |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 553 | for (lane = 0; lane < lane_count; lane++) |
| 554 | exynos_dp_set_lane_link_training(dp, |
| 555 | dp->link_train.training_lane[lane], lane); |
| 556 | |
| 557 | retval = exynos_dp_write_bytes_to_dpcd(dp, |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 558 | DP_TRAINING_LANE0_SET, lane_count, |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 559 | dp->link_train.training_lane); |
| 560 | if (retval) |
| 561 | return retval; |
| 562 | |
| 563 | return retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 564 | } |
| 565 | |
| 566 | static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp) |
| 567 | { |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 568 | int lane, lane_count, retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 569 | u32 reg; |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 570 | u8 link_align, link_status[2], adjust_request[2]; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 571 | |
Jingoo Han | a2c81bc | 2012-07-18 18:50:59 +0900 | [diff] [blame] | 572 | usleep_range(400, 401); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 573 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 574 | lane_count = dp->link_train.lane_count; |
| 575 | |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 576 | retval = exynos_dp_read_bytes_from_dpcd(dp, |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 577 | DP_LANE0_1_STATUS, 2, link_status); |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 578 | if (retval) |
| 579 | return retval; |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 580 | |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 581 | if (exynos_dp_clock_recovery_ok(link_status, lane_count)) { |
| 582 | exynos_dp_reduce_link_rate(dp); |
| 583 | return -EIO; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 584 | } |
| 585 | |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 586 | retval = exynos_dp_read_bytes_from_dpcd(dp, |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 587 | DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request); |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 588 | if (retval) |
| 589 | return retval; |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 590 | |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 591 | retval = exynos_dp_read_byte_from_dpcd(dp, |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 592 | DP_LANE_ALIGN_STATUS_UPDATED, &link_align); |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 593 | if (retval) |
| 594 | return retval; |
| 595 | |
| 596 | exynos_dp_get_adjust_training_lane(dp, adjust_request); |
| 597 | |
| 598 | if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) { |
| 599 | /* traing pattern Set to Normal */ |
| 600 | exynos_dp_training_pattern_dis(dp); |
| 601 | |
| 602 | dev_info(dp->dev, "Link Training success!\n"); |
| 603 | |
| 604 | exynos_dp_get_link_bandwidth(dp, ®); |
| 605 | dp->link_train.link_rate = reg; |
| 606 | dev_dbg(dp->dev, "final bandwidth = %.2x\n", |
| 607 | dp->link_train.link_rate); |
| 608 | |
| 609 | exynos_dp_get_lane_count(dp, ®); |
| 610 | dp->link_train.lane_count = reg; |
| 611 | dev_dbg(dp->dev, "final lane count = %.2x\n", |
| 612 | dp->link_train.lane_count); |
| 613 | |
| 614 | /* set enhanced mode if available */ |
| 615 | exynos_dp_set_enhanced_mode(dp); |
| 616 | dp->link_train.lt_state = FINISHED; |
| 617 | |
| 618 | return 0; |
| 619 | } |
| 620 | |
| 621 | /* not all locked */ |
| 622 | dp->link_train.eq_loop++; |
| 623 | |
| 624 | if (dp->link_train.eq_loop > MAX_EQ_LOOP) { |
| 625 | dev_err(dp->dev, "EQ Max loop\n"); |
| 626 | exynos_dp_reduce_link_rate(dp); |
| 627 | return -EIO; |
| 628 | } |
| 629 | |
| 630 | for (lane = 0; lane < lane_count; lane++) |
| 631 | exynos_dp_set_lane_link_training(dp, |
| 632 | dp->link_train.training_lane[lane], lane); |
| 633 | |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 634 | retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET, |
Sean Paul | fadec4b | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 635 | lane_count, dp->link_train.training_lane); |
| 636 | |
| 637 | return retval; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 638 | } |
| 639 | |
| 640 | static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp, |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 641 | u8 *bandwidth) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 642 | { |
| 643 | u8 data; |
| 644 | |
| 645 | /* |
| 646 | * For DP rev.1.1, Maximum link rate of Main Link lanes |
| 647 | * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps |
| 648 | */ |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 649 | exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 650 | *bandwidth = data; |
| 651 | } |
| 652 | |
| 653 | static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp, |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 654 | u8 *lane_count) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 655 | { |
| 656 | u8 data; |
| 657 | |
| 658 | /* |
| 659 | * For DP rev.1.1, Maximum number of Main Link lanes |
| 660 | * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes |
| 661 | */ |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 662 | exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 663 | *lane_count = DPCD_MAX_LANE_COUNT(data); |
| 664 | } |
| 665 | |
| 666 | static void exynos_dp_init_training(struct exynos_dp_device *dp, |
| 667 | enum link_lane_count_type max_lane, |
| 668 | enum link_rate_type max_rate) |
| 669 | { |
| 670 | /* |
| 671 | * MACRO_RST must be applied after the PLL_LOCK to avoid |
| 672 | * the DP inter pair skew issue for at least 10 us |
| 673 | */ |
| 674 | exynos_dp_reset_macro(dp); |
| 675 | |
| 676 | /* Initialize by reading RX's DPCD */ |
| 677 | exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate); |
| 678 | exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count); |
| 679 | |
| 680 | if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) && |
| 681 | (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) { |
| 682 | dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n", |
| 683 | dp->link_train.link_rate); |
| 684 | dp->link_train.link_rate = LINK_RATE_1_62GBPS; |
| 685 | } |
| 686 | |
| 687 | if (dp->link_train.lane_count == 0) { |
| 688 | dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n", |
| 689 | dp->link_train.lane_count); |
| 690 | dp->link_train.lane_count = (u8)LANE_COUNT1; |
| 691 | } |
| 692 | |
| 693 | /* Setup TX lane count & rate */ |
| 694 | if (dp->link_train.lane_count > max_lane) |
| 695 | dp->link_train.lane_count = max_lane; |
| 696 | if (dp->link_train.link_rate > max_rate) |
| 697 | dp->link_train.link_rate = max_rate; |
| 698 | |
| 699 | /* All DP analog module power up */ |
| 700 | exynos_dp_set_analog_power_down(dp, POWER_ALL, 0); |
| 701 | } |
| 702 | |
| 703 | static int exynos_dp_sw_link_training(struct exynos_dp_device *dp) |
| 704 | { |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 705 | int retval = 0, training_finished = 0; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 706 | |
| 707 | dp->link_train.lt_state = START; |
| 708 | |
| 709 | /* Process here */ |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 710 | while (!retval && !training_finished) { |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 711 | switch (dp->link_train.lt_state) { |
| 712 | case START: |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 713 | retval = exynos_dp_link_start(dp); |
| 714 | if (retval) |
| 715 | dev_err(dp->dev, "LT link start failed!\n"); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 716 | break; |
| 717 | case CLOCK_RECOVERY: |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 718 | retval = exynos_dp_process_clock_recovery(dp); |
| 719 | if (retval) |
| 720 | dev_err(dp->dev, "LT CR failed!\n"); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 721 | break; |
| 722 | case EQUALIZER_TRAINING: |
Jingoo Han | d5c0eed | 2012-07-19 13:52:59 +0900 | [diff] [blame] | 723 | retval = exynos_dp_process_equalizer_training(dp); |
| 724 | if (retval) |
| 725 | dev_err(dp->dev, "LT EQ failed!\n"); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 726 | break; |
| 727 | case FINISHED: |
| 728 | training_finished = 1; |
| 729 | break; |
| 730 | case FAILED: |
| 731 | return -EREMOTEIO; |
| 732 | } |
| 733 | } |
Sean Paul | ace2d7f | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 734 | if (retval) |
| 735 | dev_err(dp->dev, "eDP link training failed (%d)\n", retval); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 736 | |
| 737 | return retval; |
| 738 | } |
| 739 | |
| 740 | static int exynos_dp_set_link_train(struct exynos_dp_device *dp, |
| 741 | u32 count, |
| 742 | u32 bwtype) |
| 743 | { |
| 744 | int i; |
| 745 | int retval; |
| 746 | |
| 747 | for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) { |
| 748 | exynos_dp_init_training(dp, count, bwtype); |
| 749 | retval = exynos_dp_sw_link_training(dp); |
| 750 | if (retval == 0) |
| 751 | break; |
| 752 | |
Jingoo Han | a2c81bc | 2012-07-18 18:50:59 +0900 | [diff] [blame] | 753 | usleep_range(100, 110); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 754 | } |
| 755 | |
| 756 | return retval; |
| 757 | } |
| 758 | |
Ajay Kumar | 3fcb6eb | 2012-11-09 14:05:06 +0900 | [diff] [blame] | 759 | static int exynos_dp_config_video(struct exynos_dp_device *dp) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 760 | { |
| 761 | int retval = 0; |
| 762 | int timeout_loop = 0; |
| 763 | int done_count = 0; |
| 764 | |
Ajay Kumar | 3fcb6eb | 2012-11-09 14:05:06 +0900 | [diff] [blame] | 765 | exynos_dp_config_video_slave_mode(dp); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 766 | |
Ajay Kumar | 3fcb6eb | 2012-11-09 14:05:06 +0900 | [diff] [blame] | 767 | exynos_dp_set_video_color_format(dp); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 768 | |
| 769 | if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { |
| 770 | dev_err(dp->dev, "PLL is not locked yet.\n"); |
| 771 | return -EINVAL; |
| 772 | } |
| 773 | |
| 774 | for (;;) { |
| 775 | timeout_loop++; |
| 776 | if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0) |
| 777 | break; |
| 778 | if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { |
| 779 | dev_err(dp->dev, "Timeout of video streamclk ok\n"); |
| 780 | return -ETIMEDOUT; |
| 781 | } |
| 782 | |
Jingoo Han | a2c81bc | 2012-07-18 18:50:59 +0900 | [diff] [blame] | 783 | usleep_range(1, 2); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 784 | } |
| 785 | |
| 786 | /* Set to use the register calculated M/N video */ |
| 787 | exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0); |
| 788 | |
| 789 | /* For video bist, Video timing must be generated by register */ |
| 790 | exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE); |
| 791 | |
| 792 | /* Disable video mute */ |
| 793 | exynos_dp_enable_video_mute(dp, 0); |
| 794 | |
| 795 | /* Configure video slave mode */ |
| 796 | exynos_dp_enable_video_master(dp, 0); |
| 797 | |
| 798 | /* Enable video */ |
| 799 | exynos_dp_start_video(dp); |
| 800 | |
| 801 | timeout_loop = 0; |
| 802 | |
| 803 | for (;;) { |
| 804 | timeout_loop++; |
| 805 | if (exynos_dp_is_video_stream_on(dp) == 0) { |
| 806 | done_count++; |
| 807 | if (done_count > 10) |
| 808 | break; |
| 809 | } else if (done_count) { |
| 810 | done_count = 0; |
| 811 | } |
| 812 | if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { |
| 813 | dev_err(dp->dev, "Timeout of video streamclk ok\n"); |
| 814 | return -ETIMEDOUT; |
| 815 | } |
| 816 | |
Jingoo Han | a2c81bc | 2012-07-18 18:50:59 +0900 | [diff] [blame] | 817 | usleep_range(1000, 1001); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 818 | } |
| 819 | |
| 820 | if (retval != 0) |
| 821 | dev_err(dp->dev, "Video stream is not detected!\n"); |
| 822 | |
| 823 | return retval; |
| 824 | } |
| 825 | |
| 826 | static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable) |
| 827 | { |
| 828 | u8 data; |
| 829 | |
| 830 | if (enable) { |
| 831 | exynos_dp_enable_scrambling(dp); |
| 832 | |
| 833 | exynos_dp_read_byte_from_dpcd(dp, |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 834 | DP_TRAINING_PATTERN_SET, |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 835 | &data); |
| 836 | exynos_dp_write_byte_to_dpcd(dp, |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 837 | DP_TRAINING_PATTERN_SET, |
| 838 | (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE)); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 839 | } else { |
| 840 | exynos_dp_disable_scrambling(dp); |
| 841 | |
| 842 | exynos_dp_read_byte_from_dpcd(dp, |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 843 | DP_TRAINING_PATTERN_SET, |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 844 | &data); |
| 845 | exynos_dp_write_byte_to_dpcd(dp, |
Jingoo Han | 073ea2a | 2014-05-07 20:44:51 +0900 | [diff] [blame] | 846 | DP_TRAINING_PATTERN_SET, |
| 847 | (u8)(data | DP_LINK_SCRAMBLING_DISABLE)); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 848 | } |
| 849 | } |
| 850 | |
| 851 | static irqreturn_t exynos_dp_irq_handler(int irq, void *arg) |
| 852 | { |
| 853 | struct exynos_dp_device *dp = arg; |
| 854 | |
Sean Paul | c30ffb9 | 2012-11-01 19:13:46 +0900 | [diff] [blame] | 855 | enum dp_irq_type irq_type; |
| 856 | |
| 857 | irq_type = exynos_dp_get_irq_type(dp); |
| 858 | switch (irq_type) { |
| 859 | case DP_IRQ_TYPE_HP_CABLE_IN: |
| 860 | dev_dbg(dp->dev, "Received irq - cable in\n"); |
| 861 | schedule_work(&dp->hotplug_work); |
| 862 | exynos_dp_clear_hotplug_interrupts(dp); |
| 863 | break; |
| 864 | case DP_IRQ_TYPE_HP_CABLE_OUT: |
| 865 | dev_dbg(dp->dev, "Received irq - cable out\n"); |
| 866 | exynos_dp_clear_hotplug_interrupts(dp); |
| 867 | break; |
| 868 | case DP_IRQ_TYPE_HP_CHANGE: |
| 869 | /* |
| 870 | * We get these change notifications once in a while, but there |
| 871 | * is nothing we can do with them. Just ignore it for now and |
| 872 | * only handle cable changes. |
| 873 | */ |
| 874 | dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n"); |
| 875 | exynos_dp_clear_hotplug_interrupts(dp); |
| 876 | break; |
| 877 | default: |
| 878 | dev_err(dp->dev, "Received irq - unknown type!\n"); |
| 879 | break; |
| 880 | } |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 881 | return IRQ_HANDLED; |
| 882 | } |
| 883 | |
Sean Paul | 784fa9a | 2012-11-09 13:55:08 +0900 | [diff] [blame] | 884 | static void exynos_dp_hotplug(struct work_struct *work) |
| 885 | { |
| 886 | struct exynos_dp_device *dp; |
Sean Paul | 784fa9a | 2012-11-09 13:55:08 +0900 | [diff] [blame] | 887 | |
| 888 | dp = container_of(work, struct exynos_dp_device, hotplug_work); |
| 889 | |
Ajay Kumar | 4deabfa | 2014-07-31 23:12:13 +0530 | [diff] [blame] | 890 | if (dp->drm_dev) |
| 891 | drm_helper_hpd_irq_event(dp->drm_dev); |
| 892 | } |
| 893 | |
| 894 | static void exynos_dp_commit(struct exynos_drm_display *display) |
| 895 | { |
Andrzej Hajda | 63b3be3 | 2014-11-17 09:54:25 +0100 | [diff] [blame] | 896 | struct exynos_dp_device *dp = display_to_dp(display); |
Ajay Kumar | 4deabfa | 2014-07-31 23:12:13 +0530 | [diff] [blame] | 897 | int ret; |
| 898 | |
Ajay Kumar | 5f1dcd8 | 2014-07-31 23:12:14 +0530 | [diff] [blame] | 899 | /* Keep the panel disabled while we configure video */ |
| 900 | if (dp->panel) { |
| 901 | if (drm_panel_disable(dp->panel)) |
| 902 | DRM_ERROR("failed to disable the panel\n"); |
| 903 | } |
| 904 | |
Sean Paul | 784fa9a | 2012-11-09 13:55:08 +0900 | [diff] [blame] | 905 | ret = exynos_dp_detect_hpd(dp); |
| 906 | if (ret) { |
Sean Paul | c30ffb9 | 2012-11-01 19:13:46 +0900 | [diff] [blame] | 907 | /* Cable has been disconnected, we're done */ |
Sean Paul | 784fa9a | 2012-11-09 13:55:08 +0900 | [diff] [blame] | 908 | return; |
| 909 | } |
| 910 | |
| 911 | ret = exynos_dp_handle_edid(dp); |
| 912 | if (ret) { |
| 913 | dev_err(dp->dev, "unable to handle edid\n"); |
| 914 | return; |
| 915 | } |
| 916 | |
| 917 | ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count, |
| 918 | dp->video_info->link_rate); |
| 919 | if (ret) { |
| 920 | dev_err(dp->dev, "unable to do link train\n"); |
| 921 | return; |
| 922 | } |
| 923 | |
| 924 | exynos_dp_enable_scramble(dp, 1); |
| 925 | exynos_dp_enable_rx_to_enhanced_mode(dp, 1); |
| 926 | exynos_dp_enable_enhanced_mode(dp, 1); |
| 927 | |
| 928 | exynos_dp_set_lane_count(dp, dp->video_info->lane_count); |
| 929 | exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate); |
| 930 | |
| 931 | exynos_dp_init_video(dp); |
Ajay Kumar | 3fcb6eb | 2012-11-09 14:05:06 +0900 | [diff] [blame] | 932 | ret = exynos_dp_config_video(dp); |
Sean Paul | 784fa9a | 2012-11-09 13:55:08 +0900 | [diff] [blame] | 933 | if (ret) |
| 934 | dev_err(dp->dev, "unable to config video\n"); |
Ajay Kumar | 5f1dcd8 | 2014-07-31 23:12:14 +0530 | [diff] [blame] | 935 | |
| 936 | /* Safe to enable the panel now */ |
| 937 | if (dp->panel) { |
| 938 | if (drm_panel_enable(dp->panel)) |
| 939 | DRM_ERROR("failed to enable the panel\n"); |
| 940 | } |
Sean Paul | 784fa9a | 2012-11-09 13:55:08 +0900 | [diff] [blame] | 941 | } |
| 942 | |
Sean Paul | caa5d1e | 2014-01-30 16:19:30 -0500 | [diff] [blame] | 943 | static enum drm_connector_status exynos_dp_detect( |
| 944 | struct drm_connector *connector, bool force) |
Sean Paul | 1417f10 | 2014-01-30 16:19:23 -0500 | [diff] [blame] | 945 | { |
Sean Paul | caa5d1e | 2014-01-30 16:19:30 -0500 | [diff] [blame] | 946 | return connector_status_connected; |
Sean Paul | 1417f10 | 2014-01-30 16:19:23 -0500 | [diff] [blame] | 947 | } |
| 948 | |
Sean Paul | caa5d1e | 2014-01-30 16:19:30 -0500 | [diff] [blame] | 949 | static void exynos_dp_connector_destroy(struct drm_connector *connector) |
| 950 | { |
Andrzej Hajda | 7c61b1e | 2014-09-09 15:16:12 +0200 | [diff] [blame] | 951 | drm_connector_unregister(connector); |
| 952 | drm_connector_cleanup(connector); |
Sean Paul | caa5d1e | 2014-01-30 16:19:30 -0500 | [diff] [blame] | 953 | } |
| 954 | |
| 955 | static struct drm_connector_funcs exynos_dp_connector_funcs = { |
Gustavo Padovan | 63498e3 | 2015-06-01 12:04:53 -0300 | [diff] [blame] | 956 | .dpms = drm_atomic_helper_connector_dpms, |
Sean Paul | caa5d1e | 2014-01-30 16:19:30 -0500 | [diff] [blame] | 957 | .fill_modes = drm_helper_probe_single_connector_modes, |
| 958 | .detect = exynos_dp_detect, |
| 959 | .destroy = exynos_dp_connector_destroy, |
Gustavo Padovan | 4ea9526 | 2015-06-01 12:04:44 -0300 | [diff] [blame] | 960 | .reset = drm_atomic_helper_connector_reset, |
| 961 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
| 962 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
Sean Paul | caa5d1e | 2014-01-30 16:19:30 -0500 | [diff] [blame] | 963 | }; |
| 964 | |
| 965 | static int exynos_dp_get_modes(struct drm_connector *connector) |
| 966 | { |
| 967 | struct exynos_dp_device *dp = ctx_from_connector(connector); |
| 968 | struct drm_display_mode *mode; |
| 969 | |
Ajay Kumar | 5f1dcd8 | 2014-07-31 23:12:14 +0530 | [diff] [blame] | 970 | if (dp->panel) |
| 971 | return drm_panel_get_modes(dp->panel); |
| 972 | |
Sean Paul | caa5d1e | 2014-01-30 16:19:30 -0500 | [diff] [blame] | 973 | mode = drm_mode_create(connector->dev); |
| 974 | if (!mode) { |
| 975 | DRM_ERROR("failed to create a new display mode.\n"); |
| 976 | return 0; |
| 977 | } |
| 978 | |
Ajay Kumar | 5f1dcd8 | 2014-07-31 23:12:14 +0530 | [diff] [blame] | 979 | drm_display_mode_from_videomode(&dp->priv.vm, mode); |
| 980 | mode->width_mm = dp->priv.width_mm; |
| 981 | mode->height_mm = dp->priv.height_mm; |
Sean Paul | caa5d1e | 2014-01-30 16:19:30 -0500 | [diff] [blame] | 982 | connector->display_info.width_mm = mode->width_mm; |
| 983 | connector->display_info.height_mm = mode->height_mm; |
| 984 | |
| 985 | mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; |
| 986 | drm_mode_set_name(mode); |
| 987 | drm_mode_probed_add(connector, mode); |
| 988 | |
| 989 | return 1; |
| 990 | } |
| 991 | |
Sean Paul | caa5d1e | 2014-01-30 16:19:30 -0500 | [diff] [blame] | 992 | static struct drm_encoder *exynos_dp_best_encoder( |
| 993 | struct drm_connector *connector) |
| 994 | { |
| 995 | struct exynos_dp_device *dp = ctx_from_connector(connector); |
| 996 | |
| 997 | return dp->encoder; |
| 998 | } |
| 999 | |
| 1000 | static struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = { |
| 1001 | .get_modes = exynos_dp_get_modes, |
Sean Paul | caa5d1e | 2014-01-30 16:19:30 -0500 | [diff] [blame] | 1002 | .best_encoder = exynos_dp_best_encoder, |
| 1003 | }; |
| 1004 | |
Sean Paul | 1634ba2 | 2014-02-24 19:20:15 +0900 | [diff] [blame] | 1005 | /* returns the number of bridges attached */ |
Ajay Kumar | 8018556 | 2015-01-20 22:08:46 +0530 | [diff] [blame] | 1006 | static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp, |
Sean Paul | 1634ba2 | 2014-02-24 19:20:15 +0900 | [diff] [blame] | 1007 | struct drm_encoder *encoder) |
| 1008 | { |
Ajay Kumar | 8018556 | 2015-01-20 22:08:46 +0530 | [diff] [blame] | 1009 | int ret; |
| 1010 | |
| 1011 | encoder->bridge = dp->bridge; |
| 1012 | dp->bridge->encoder = encoder; |
| 1013 | ret = drm_bridge_attach(encoder->dev, dp->bridge); |
| 1014 | if (ret) { |
| 1015 | DRM_ERROR("Failed to attach bridge to drm\n"); |
| 1016 | return ret; |
| 1017 | } |
| 1018 | |
Sean Paul | 1634ba2 | 2014-02-24 19:20:15 +0900 | [diff] [blame] | 1019 | return 0; |
| 1020 | } |
| 1021 | |
Sean Paul | caa5d1e | 2014-01-30 16:19:30 -0500 | [diff] [blame] | 1022 | static int exynos_dp_create_connector(struct exynos_drm_display *display, |
| 1023 | struct drm_encoder *encoder) |
Sean Paul | 1417f10 | 2014-01-30 16:19:23 -0500 | [diff] [blame] | 1024 | { |
Andrzej Hajda | 63b3be3 | 2014-11-17 09:54:25 +0100 | [diff] [blame] | 1025 | struct exynos_dp_device *dp = display_to_dp(display); |
Sean Paul | caa5d1e | 2014-01-30 16:19:30 -0500 | [diff] [blame] | 1026 | struct drm_connector *connector = &dp->connector; |
| 1027 | int ret; |
| 1028 | |
| 1029 | dp->encoder = encoder; |
Sean Paul | 1634ba2 | 2014-02-24 19:20:15 +0900 | [diff] [blame] | 1030 | |
| 1031 | /* Pre-empt DP connector creation if there's a bridge */ |
Ajay Kumar | 8018556 | 2015-01-20 22:08:46 +0530 | [diff] [blame] | 1032 | if (dp->bridge) { |
| 1033 | ret = exynos_drm_attach_lcd_bridge(dp, encoder); |
| 1034 | if (!ret) |
| 1035 | return 0; |
| 1036 | } |
Sean Paul | 1634ba2 | 2014-02-24 19:20:15 +0900 | [diff] [blame] | 1037 | |
Sean Paul | caa5d1e | 2014-01-30 16:19:30 -0500 | [diff] [blame] | 1038 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 1039 | |
| 1040 | ret = drm_connector_init(dp->drm_dev, connector, |
| 1041 | &exynos_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP); |
| 1042 | if (ret) { |
| 1043 | DRM_ERROR("Failed to initialize connector with drm\n"); |
| 1044 | return ret; |
| 1045 | } |
| 1046 | |
| 1047 | drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs); |
Thomas Wood | 34ea3d3 | 2014-05-29 16:57:41 +0100 | [diff] [blame] | 1048 | drm_connector_register(connector); |
Sean Paul | caa5d1e | 2014-01-30 16:19:30 -0500 | [diff] [blame] | 1049 | drm_mode_connector_attach_encoder(connector, encoder); |
| 1050 | |
Ajay Kumar | 5f1dcd8 | 2014-07-31 23:12:14 +0530 | [diff] [blame] | 1051 | if (dp->panel) |
| 1052 | ret = drm_panel_attach(dp->panel, &dp->connector); |
| 1053 | |
| 1054 | return ret; |
Sean Paul | 1417f10 | 2014-01-30 16:19:23 -0500 | [diff] [blame] | 1055 | } |
| 1056 | |
Gustavo Padovan | b6595dc | 2015-08-10 21:37:04 -0300 | [diff] [blame] | 1057 | static void exynos_dp_enable(struct exynos_drm_display *display) |
Sean Paul | 12f5ad6 | 2014-01-30 16:19:25 -0500 | [diff] [blame] | 1058 | { |
Gustavo Padovan | b6595dc | 2015-08-10 21:37:04 -0300 | [diff] [blame] | 1059 | struct exynos_dp_device *dp = display_to_dp(display); |
Krzysztof Kozlowski | 48107d7 | 2015-05-07 09:04:44 +0900 | [diff] [blame] | 1060 | struct exynos_drm_crtc *crtc = dp_to_crtc(dp); |
| 1061 | |
Sean Paul | 12f5ad6 | 2014-01-30 16:19:25 -0500 | [diff] [blame] | 1062 | if (dp->dpms_mode == DRM_MODE_DPMS_ON) |
| 1063 | return; |
| 1064 | |
Ajay Kumar | 5f1dcd8 | 2014-07-31 23:12:14 +0530 | [diff] [blame] | 1065 | if (dp->panel) { |
| 1066 | if (drm_panel_prepare(dp->panel)) { |
| 1067 | DRM_ERROR("failed to setup the panel\n"); |
| 1068 | return; |
| 1069 | } |
| 1070 | } |
| 1071 | |
Krzysztof Kozlowski | 48107d7 | 2015-05-07 09:04:44 +0900 | [diff] [blame] | 1072 | if (crtc->ops->clock_enable) |
| 1073 | crtc->ops->clock_enable(dp_to_crtc(dp), true); |
Krzysztof Kozlowski | 1c363c7 | 2015-04-07 22:28:50 +0900 | [diff] [blame] | 1074 | |
Sean Paul | 12f5ad6 | 2014-01-30 16:19:25 -0500 | [diff] [blame] | 1075 | clk_prepare_enable(dp->clock); |
Gustavo Padovan | b6f3c36 | 2015-08-05 20:24:13 -0300 | [diff] [blame^] | 1076 | phy_power_on(dp->phy); |
Sean Paul | 12f5ad6 | 2014-01-30 16:19:25 -0500 | [diff] [blame] | 1077 | exynos_dp_init_dp(dp); |
| 1078 | enable_irq(dp->irq); |
Joonyoung Shim | 92dc7a0 | 2015-01-30 16:43:02 +0900 | [diff] [blame] | 1079 | exynos_dp_commit(&dp->display); |
Gustavo Padovan | b6595dc | 2015-08-10 21:37:04 -0300 | [diff] [blame] | 1080 | |
| 1081 | dp->dpms_mode = DRM_MODE_DPMS_ON; |
Sean Paul | 12f5ad6 | 2014-01-30 16:19:25 -0500 | [diff] [blame] | 1082 | } |
| 1083 | |
Gustavo Padovan | b6595dc | 2015-08-10 21:37:04 -0300 | [diff] [blame] | 1084 | static void exynos_dp_disable(struct exynos_drm_display *display) |
Sean Paul | 12f5ad6 | 2014-01-30 16:19:25 -0500 | [diff] [blame] | 1085 | { |
Gustavo Padovan | b6595dc | 2015-08-10 21:37:04 -0300 | [diff] [blame] | 1086 | struct exynos_dp_device *dp = display_to_dp(display); |
Krzysztof Kozlowski | 48107d7 | 2015-05-07 09:04:44 +0900 | [diff] [blame] | 1087 | struct exynos_drm_crtc *crtc = dp_to_crtc(dp); |
| 1088 | |
Sean Paul | 12f5ad6 | 2014-01-30 16:19:25 -0500 | [diff] [blame] | 1089 | if (dp->dpms_mode != DRM_MODE_DPMS_ON) |
| 1090 | return; |
| 1091 | |
Ajay Kumar | 5f1dcd8 | 2014-07-31 23:12:14 +0530 | [diff] [blame] | 1092 | if (dp->panel) { |
| 1093 | if (drm_panel_disable(dp->panel)) { |
| 1094 | DRM_ERROR("failed to disable the panel\n"); |
| 1095 | return; |
| 1096 | } |
| 1097 | } |
| 1098 | |
Sean Paul | 12f5ad6 | 2014-01-30 16:19:25 -0500 | [diff] [blame] | 1099 | disable_irq(dp->irq); |
| 1100 | flush_work(&dp->hotplug_work); |
Gustavo Padovan | b6f3c36 | 2015-08-05 20:24:13 -0300 | [diff] [blame^] | 1101 | phy_power_off(dp->phy); |
Sean Paul | 12f5ad6 | 2014-01-30 16:19:25 -0500 | [diff] [blame] | 1102 | clk_disable_unprepare(dp->clock); |
Ajay Kumar | 5f1dcd8 | 2014-07-31 23:12:14 +0530 | [diff] [blame] | 1103 | |
Krzysztof Kozlowski | 48107d7 | 2015-05-07 09:04:44 +0900 | [diff] [blame] | 1104 | if (crtc->ops->clock_enable) |
| 1105 | crtc->ops->clock_enable(dp_to_crtc(dp), false); |
Krzysztof Kozlowski | 1c363c7 | 2015-04-07 22:28:50 +0900 | [diff] [blame] | 1106 | |
Ajay Kumar | 5f1dcd8 | 2014-07-31 23:12:14 +0530 | [diff] [blame] | 1107 | if (dp->panel) { |
| 1108 | if (drm_panel_unprepare(dp->panel)) |
| 1109 | DRM_ERROR("failed to turnoff the panel\n"); |
| 1110 | } |
Sean Paul | 12f5ad6 | 2014-01-30 16:19:25 -0500 | [diff] [blame] | 1111 | |
Gustavo Padovan | b6595dc | 2015-08-10 21:37:04 -0300 | [diff] [blame] | 1112 | dp->dpms_mode = DRM_MODE_DPMS_OFF; |
Sean Paul | 12f5ad6 | 2014-01-30 16:19:25 -0500 | [diff] [blame] | 1113 | } |
| 1114 | |
Sean Paul | 1417f10 | 2014-01-30 16:19:23 -0500 | [diff] [blame] | 1115 | static struct exynos_drm_display_ops exynos_dp_display_ops = { |
Sean Paul | caa5d1e | 2014-01-30 16:19:30 -0500 | [diff] [blame] | 1116 | .create_connector = exynos_dp_create_connector, |
Gustavo Padovan | b6595dc | 2015-08-10 21:37:04 -0300 | [diff] [blame] | 1117 | .enable = exynos_dp_enable, |
| 1118 | .disable = exynos_dp_disable, |
Ajay Kumar | 4deabfa | 2014-07-31 23:12:13 +0530 | [diff] [blame] | 1119 | .commit = exynos_dp_commit, |
Sean Paul | 1417f10 | 2014-01-30 16:19:23 -0500 | [diff] [blame] | 1120 | }; |
| 1121 | |
Jingoo Han | f9b1e01 | 2013-10-16 21:58:15 +0530 | [diff] [blame] | 1122 | static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev) |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1123 | { |
| 1124 | struct device_node *dp_node = dev->of_node; |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1125 | struct video_info *dp_video_config; |
| 1126 | |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1127 | dp_video_config = devm_kzalloc(dev, |
| 1128 | sizeof(*dp_video_config), GFP_KERNEL); |
Jingoo Han | 7a5b6827 | 2014-04-17 19:08:14 +0900 | [diff] [blame] | 1129 | if (!dp_video_config) |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1130 | return ERR_PTR(-ENOMEM); |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1131 | |
| 1132 | dp_video_config->h_sync_polarity = |
| 1133 | of_property_read_bool(dp_node, "hsync-active-high"); |
| 1134 | |
| 1135 | dp_video_config->v_sync_polarity = |
| 1136 | of_property_read_bool(dp_node, "vsync-active-high"); |
| 1137 | |
| 1138 | dp_video_config->interlaced = |
| 1139 | of_property_read_bool(dp_node, "interlaced"); |
| 1140 | |
| 1141 | if (of_property_read_u32(dp_node, "samsung,color-space", |
| 1142 | &dp_video_config->color_space)) { |
| 1143 | dev_err(dev, "failed to get color-space\n"); |
| 1144 | return ERR_PTR(-EINVAL); |
| 1145 | } |
| 1146 | |
| 1147 | if (of_property_read_u32(dp_node, "samsung,dynamic-range", |
| 1148 | &dp_video_config->dynamic_range)) { |
| 1149 | dev_err(dev, "failed to get dynamic-range\n"); |
| 1150 | return ERR_PTR(-EINVAL); |
| 1151 | } |
| 1152 | |
| 1153 | if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff", |
| 1154 | &dp_video_config->ycbcr_coeff)) { |
| 1155 | dev_err(dev, "failed to get ycbcr-coeff\n"); |
| 1156 | return ERR_PTR(-EINVAL); |
| 1157 | } |
| 1158 | |
| 1159 | if (of_property_read_u32(dp_node, "samsung,color-depth", |
| 1160 | &dp_video_config->color_depth)) { |
| 1161 | dev_err(dev, "failed to get color-depth\n"); |
| 1162 | return ERR_PTR(-EINVAL); |
| 1163 | } |
| 1164 | |
| 1165 | if (of_property_read_u32(dp_node, "samsung,link-rate", |
| 1166 | &dp_video_config->link_rate)) { |
| 1167 | dev_err(dev, "failed to get link-rate\n"); |
| 1168 | return ERR_PTR(-EINVAL); |
| 1169 | } |
| 1170 | |
| 1171 | if (of_property_read_u32(dp_node, "samsung,lane-count", |
| 1172 | &dp_video_config->lane_count)) { |
| 1173 | dev_err(dev, "failed to get lane-count\n"); |
| 1174 | return ERR_PTR(-EINVAL); |
| 1175 | } |
| 1176 | |
Jingoo Han | f9b1e01 | 2013-10-16 21:58:15 +0530 | [diff] [blame] | 1177 | return dp_video_config; |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1178 | } |
| 1179 | |
Sean Paul | 1417f10 | 2014-01-30 16:19:23 -0500 | [diff] [blame] | 1180 | static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp) |
| 1181 | { |
| 1182 | int ret; |
| 1183 | |
Ajay Kumar | 5f1dcd8 | 2014-07-31 23:12:14 +0530 | [diff] [blame] | 1184 | ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm, |
Sean Paul | 1417f10 | 2014-01-30 16:19:23 -0500 | [diff] [blame] | 1185 | OF_USE_NATIVE_MODE); |
| 1186 | if (ret) { |
| 1187 | DRM_ERROR("failed: of_get_videomode() : %d\n", ret); |
| 1188 | return ret; |
| 1189 | } |
| 1190 | return 0; |
| 1191 | } |
| 1192 | |
Inki Dae | f37cd5e | 2014-05-09 14:25:20 +0900 | [diff] [blame] | 1193 | static int exynos_dp_bind(struct device *dev, struct device *master, void *data) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1194 | { |
Andrzej Hajda | 1df6e5f | 2014-11-17 09:54:24 +0100 | [diff] [blame] | 1195 | struct exynos_dp_device *dp = dev_get_drvdata(dev); |
Inki Dae | f37cd5e | 2014-05-09 14:25:20 +0900 | [diff] [blame] | 1196 | struct platform_device *pdev = to_platform_device(dev); |
| 1197 | struct drm_device *drm_dev = data; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1198 | struct resource *res; |
Andrew Bresticker | b8b5247 | 2014-04-22 04:09:10 +0530 | [diff] [blame] | 1199 | unsigned int irq_flags; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1200 | int ret = 0; |
| 1201 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1202 | dp->dev = &pdev->dev; |
Sean Paul | 12f5ad6 | 2014-01-30 16:19:25 -0500 | [diff] [blame] | 1203 | dp->dpms_mode = DRM_MODE_DPMS_OFF; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1204 | |
Jingoo Han | f9b1e01 | 2013-10-16 21:58:15 +0530 | [diff] [blame] | 1205 | dp->video_info = exynos_dp_dt_parse_pdata(&pdev->dev); |
| 1206 | if (IS_ERR(dp->video_info)) |
| 1207 | return PTR_ERR(dp->video_info); |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1208 | |
Vivek Gautam | b128aef | 2014-11-12 15:12:10 +0530 | [diff] [blame] | 1209 | dp->phy = devm_phy_get(dp->dev, "dp"); |
| 1210 | if (IS_ERR(dp->phy)) { |
| 1211 | dev_err(dp->dev, "no DP phy configured\n"); |
| 1212 | ret = PTR_ERR(dp->phy); |
| 1213 | if (ret) { |
| 1214 | /* |
| 1215 | * phy itself is not enabled, so we can move forward |
| 1216 | * assigning NULL to phy pointer. |
| 1217 | */ |
| 1218 | if (ret == -ENOSYS || ret == -ENODEV) |
| 1219 | dp->phy = NULL; |
| 1220 | else |
| 1221 | return ret; |
| 1222 | } |
| 1223 | } |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1224 | |
Ajay Kumar | 8018556 | 2015-01-20 22:08:46 +0530 | [diff] [blame] | 1225 | if (!dp->panel && !dp->bridge) { |
Ajay Kumar | 5f1dcd8 | 2014-07-31 23:12:14 +0530 | [diff] [blame] | 1226 | ret = exynos_dp_dt_parse_panel(dp); |
| 1227 | if (ret) |
| 1228 | return ret; |
| 1229 | } |
Sean Paul | 1417f10 | 2014-01-30 16:19:23 -0500 | [diff] [blame] | 1230 | |
Damien Cassou | d913f36 | 2012-08-01 18:20:39 +0200 | [diff] [blame] | 1231 | dp->clock = devm_clk_get(&pdev->dev, "dp"); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1232 | if (IS_ERR(dp->clock)) { |
| 1233 | dev_err(&pdev->dev, "failed to get clock\n"); |
Jingoo Han | 4d10ecf8 | 2012-05-25 16:20:45 +0900 | [diff] [blame] | 1234 | return PTR_ERR(dp->clock); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1235 | } |
| 1236 | |
Jingoo Han | 37414fb | 2012-10-04 15:45:14 +0900 | [diff] [blame] | 1237 | clk_prepare_enable(dp->clock); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1238 | |
| 1239 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1240 | |
Thierry Reding | bc3bad1 | 2013-01-21 11:09:23 +0100 | [diff] [blame] | 1241 | dp->reg_base = devm_ioremap_resource(&pdev->dev, res); |
| 1242 | if (IS_ERR(dp->reg_base)) |
| 1243 | return PTR_ERR(dp->reg_base); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1244 | |
Andrew Bresticker | b8b5247 | 2014-04-22 04:09:10 +0530 | [diff] [blame] | 1245 | dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0); |
| 1246 | |
| 1247 | if (gpio_is_valid(dp->hpd_gpio)) { |
| 1248 | /* |
| 1249 | * Set up the hotplug GPIO from the device tree as an interrupt. |
| 1250 | * Simply specifying a different interrupt in the device tree |
| 1251 | * doesn't work since we handle hotplug rather differently when |
| 1252 | * using a GPIO. We also need the actual GPIO specifier so |
| 1253 | * that we can get the current state of the GPIO. |
| 1254 | */ |
| 1255 | ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN, |
| 1256 | "hpd_gpio"); |
| 1257 | if (ret) { |
| 1258 | dev_err(&pdev->dev, "failed to get hpd gpio\n"); |
| 1259 | return ret; |
| 1260 | } |
| 1261 | dp->irq = gpio_to_irq(dp->hpd_gpio); |
| 1262 | irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING; |
| 1263 | } else { |
| 1264 | dp->hpd_gpio = -ENODEV; |
| 1265 | dp->irq = platform_get_irq(pdev, 0); |
| 1266 | irq_flags = 0; |
| 1267 | } |
| 1268 | |
Sean Paul | 1cefc1d | 2012-10-31 23:21:00 +0000 | [diff] [blame] | 1269 | if (dp->irq == -ENXIO) { |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1270 | dev_err(&pdev->dev, "failed to get irq\n"); |
Damien Cassou | d913f36 | 2012-08-01 18:20:39 +0200 | [diff] [blame] | 1271 | return -ENODEV; |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1272 | } |
| 1273 | |
Sean Paul | 784fa9a | 2012-11-09 13:55:08 +0900 | [diff] [blame] | 1274 | INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug); |
| 1275 | |
Gustavo Padovan | b6f3c36 | 2015-08-05 20:24:13 -0300 | [diff] [blame^] | 1276 | phy_power_on(dp->phy); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1277 | |
| 1278 | exynos_dp_init_dp(dp); |
| 1279 | |
Andrew Bresticker | b8b5247 | 2014-04-22 04:09:10 +0530 | [diff] [blame] | 1280 | ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler, |
| 1281 | irq_flags, "exynos-dp", dp); |
Ajay Kumar | 22ce19c | 2012-11-09 13:59:09 +0900 | [diff] [blame] | 1282 | if (ret) { |
| 1283 | dev_err(&pdev->dev, "failed to request irq\n"); |
| 1284 | return ret; |
| 1285 | } |
Sean Paul | 12f5ad6 | 2014-01-30 16:19:25 -0500 | [diff] [blame] | 1286 | disable_irq(dp->irq); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1287 | |
Inki Dae | f37cd5e | 2014-05-09 14:25:20 +0900 | [diff] [blame] | 1288 | dp->drm_dev = drm_dev; |
Sean Paul | 12f5ad6 | 2014-01-30 16:19:25 -0500 | [diff] [blame] | 1289 | |
Andrzej Hajda | 1df6e5f | 2014-11-17 09:54:24 +0100 | [diff] [blame] | 1290 | return exynos_drm_create_enc_conn(drm_dev, &dp->display); |
Inki Dae | f37cd5e | 2014-05-09 14:25:20 +0900 | [diff] [blame] | 1291 | } |
| 1292 | |
| 1293 | static void exynos_dp_unbind(struct device *dev, struct device *master, |
| 1294 | void *data) |
| 1295 | { |
Andrzej Hajda | 1df6e5f | 2014-11-17 09:54:24 +0100 | [diff] [blame] | 1296 | struct exynos_dp_device *dp = dev_get_drvdata(dev); |
Inki Dae | f37cd5e | 2014-05-09 14:25:20 +0900 | [diff] [blame] | 1297 | |
Gustavo Padovan | b6595dc | 2015-08-10 21:37:04 -0300 | [diff] [blame] | 1298 | exynos_dp_disable(&dp->display); |
Inki Dae | f37cd5e | 2014-05-09 14:25:20 +0900 | [diff] [blame] | 1299 | } |
| 1300 | |
| 1301 | static const struct component_ops exynos_dp_ops = { |
| 1302 | .bind = exynos_dp_bind, |
| 1303 | .unbind = exynos_dp_unbind, |
| 1304 | }; |
| 1305 | |
| 1306 | static int exynos_dp_probe(struct platform_device *pdev) |
| 1307 | { |
Ajay Kumar | 5f1dcd8 | 2014-07-31 23:12:14 +0530 | [diff] [blame] | 1308 | struct device *dev = &pdev->dev; |
Ajay Kumar | 8018556 | 2015-01-20 22:08:46 +0530 | [diff] [blame] | 1309 | struct device_node *panel_node, *bridge_node, *endpoint; |
Ajay Kumar | 5f1dcd8 | 2014-07-31 23:12:14 +0530 | [diff] [blame] | 1310 | struct exynos_dp_device *dp; |
Inki Dae | df5225b | 2014-05-29 18:28:02 +0900 | [diff] [blame] | 1311 | |
Ajay Kumar | 5f1dcd8 | 2014-07-31 23:12:14 +0530 | [diff] [blame] | 1312 | dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device), |
| 1313 | GFP_KERNEL); |
| 1314 | if (!dp) |
| 1315 | return -ENOMEM; |
| 1316 | |
Andrzej Hajda | 1df6e5f | 2014-11-17 09:54:24 +0100 | [diff] [blame] | 1317 | dp->display.type = EXYNOS_DISPLAY_TYPE_LCD; |
| 1318 | dp->display.ops = &exynos_dp_display_ops; |
| 1319 | platform_set_drvdata(pdev, dp); |
| 1320 | |
Ajay Kumar | 5f1dcd8 | 2014-07-31 23:12:14 +0530 | [diff] [blame] | 1321 | panel_node = of_parse_phandle(dev->of_node, "panel", 0); |
| 1322 | if (panel_node) { |
| 1323 | dp->panel = of_drm_find_panel(panel_node); |
| 1324 | of_node_put(panel_node); |
| 1325 | if (!dp->panel) |
| 1326 | return -EPROBE_DEFER; |
| 1327 | } |
| 1328 | |
Ajay Kumar | 8018556 | 2015-01-20 22:08:46 +0530 | [diff] [blame] | 1329 | endpoint = of_graph_get_next_endpoint(dev->of_node, NULL); |
| 1330 | if (endpoint) { |
| 1331 | bridge_node = of_graph_get_remote_port_parent(endpoint); |
| 1332 | if (bridge_node) { |
| 1333 | dp->bridge = of_drm_find_bridge(bridge_node); |
| 1334 | of_node_put(bridge_node); |
| 1335 | if (!dp->bridge) |
| 1336 | return -EPROBE_DEFER; |
| 1337 | } else |
| 1338 | return -EPROBE_DEFER; |
| 1339 | } |
| 1340 | |
Andrzej Hajda | 8665040 | 2015-06-11 23:23:37 +0900 | [diff] [blame] | 1341 | return component_add(&pdev->dev, &exynos_dp_ops); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1342 | } |
| 1343 | |
Greg Kroah-Hartman | 48c68c4 | 2012-12-21 13:07:39 -0800 | [diff] [blame] | 1344 | static int exynos_dp_remove(struct platform_device *pdev) |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1345 | { |
Inki Dae | df5225b | 2014-05-29 18:28:02 +0900 | [diff] [blame] | 1346 | component_del(&pdev->dev, &exynos_dp_ops); |
Inki Dae | df5225b | 2014-05-29 18:28:02 +0900 | [diff] [blame] | 1347 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1348 | return 0; |
| 1349 | } |
| 1350 | |
| 1351 | #ifdef CONFIG_PM_SLEEP |
| 1352 | static int exynos_dp_suspend(struct device *dev) |
| 1353 | { |
Andrzej Hajda | 1df6e5f | 2014-11-17 09:54:24 +0100 | [diff] [blame] | 1354 | struct exynos_dp_device *dp = dev_get_drvdata(dev); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1355 | |
Gustavo Padovan | b6595dc | 2015-08-10 21:37:04 -0300 | [diff] [blame] | 1356 | exynos_dp_disable(&dp->display); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1357 | return 0; |
| 1358 | } |
| 1359 | |
| 1360 | static int exynos_dp_resume(struct device *dev) |
| 1361 | { |
Andrzej Hajda | 1df6e5f | 2014-11-17 09:54:24 +0100 | [diff] [blame] | 1362 | struct exynos_dp_device *dp = dev_get_drvdata(dev); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1363 | |
Gustavo Padovan | b6595dc | 2015-08-10 21:37:04 -0300 | [diff] [blame] | 1364 | exynos_dp_enable(&dp->display); |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1365 | return 0; |
| 1366 | } |
| 1367 | #endif |
| 1368 | |
| 1369 | static const struct dev_pm_ops exynos_dp_pm_ops = { |
| 1370 | SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume) |
| 1371 | }; |
| 1372 | |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1373 | static const struct of_device_id exynos_dp_match[] = { |
| 1374 | { .compatible = "samsung,exynos5-dp" }, |
| 1375 | {}, |
| 1376 | }; |
Sjoerd Simons | bd024b8 | 2014-07-30 11:29:41 +0900 | [diff] [blame] | 1377 | MODULE_DEVICE_TABLE(of, exynos_dp_match); |
Ajay Kumar | c4e235c | 2012-10-13 05:48:00 +0900 | [diff] [blame] | 1378 | |
Sean Paul | 1417f10 | 2014-01-30 16:19:23 -0500 | [diff] [blame] | 1379 | struct platform_driver dp_driver = { |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1380 | .probe = exynos_dp_probe, |
Greg Kroah-Hartman | 48c68c4 | 2012-12-21 13:07:39 -0800 | [diff] [blame] | 1381 | .remove = exynos_dp_remove, |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1382 | .driver = { |
| 1383 | .name = "exynos-dp", |
| 1384 | .owner = THIS_MODULE, |
| 1385 | .pm = &exynos_dp_pm_ops, |
Jingoo Han | f9b1e01 | 2013-10-16 21:58:15 +0530 | [diff] [blame] | 1386 | .of_match_table = exynos_dp_match, |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1387 | }, |
| 1388 | }; |
| 1389 | |
Jingoo Han | e9474be | 2012-02-03 18:01:55 +0900 | [diff] [blame] | 1390 | MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>"); |
| 1391 | MODULE_DESCRIPTION("Samsung SoC DP Driver"); |
Jingoo Han | 8f589bb | 2014-06-03 21:46:11 +0900 | [diff] [blame] | 1392 | MODULE_LICENSE("GPL v2"); |