Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 1 | /* |
Sujith Manoharan | 5b68138 | 2011-05-17 13:36:18 +0530 | [diff] [blame] | 2 | * Copyright (c) 2010-2011 Atheros Communications Inc. |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
| 5 | * purpose with or without fee is hereby granted, provided that the above |
| 6 | * copyright notice and this permission notice appear in all copies. |
| 7 | * |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ |
| 16 | |
Paul Gortmaker | ee40fa0 | 2011-05-27 16:14:23 -0400 | [diff] [blame] | 17 | #include <linux/export.h> |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 18 | #include "hw.h" |
Felix Fietkau | da6f1d7 | 2010-04-15 17:38:31 -0400 | [diff] [blame] | 19 | #include "ar9003_phy.h" |
Helmut Schaa | 8569f59 | 2016-04-28 16:45:04 +0200 | [diff] [blame] | 20 | #include "ar9003_eeprom.h" |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 21 | |
Lorenzo Bianconi | 23f53dd3 | 2014-11-25 00:21:40 +0100 | [diff] [blame] | 22 | #define AR9300_OFDM_RATES 8 |
| 23 | #define AR9300_HT_SS_RATES 8 |
| 24 | #define AR9300_HT_DS_RATES 8 |
| 25 | #define AR9300_HT_TS_RATES 8 |
| 26 | |
| 27 | #define AR9300_11NA_OFDM_SHIFT 0 |
| 28 | #define AR9300_11NA_HT_SS_SHIFT 8 |
| 29 | #define AR9300_11NA_HT_DS_SHIFT 16 |
| 30 | #define AR9300_11NA_HT_TS_SHIFT 24 |
| 31 | |
| 32 | #define AR9300_11NG_OFDM_SHIFT 4 |
| 33 | #define AR9300_11NG_HT_SS_SHIFT 12 |
| 34 | #define AR9300_11NG_HT_DS_SHIFT 20 |
| 35 | #define AR9300_11NG_HT_TS_SHIFT 28 |
| 36 | |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 37 | static const int firstep_table[] = |
| 38 | /* level: 0 1 2 3 4 5 6 7 8 */ |
| 39 | { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */ |
| 40 | |
| 41 | static const int cycpwrThr1_table[] = |
| 42 | /* level: 0 1 2 3 4 5 6 7 8 */ |
| 43 | { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */ |
| 44 | |
| 45 | /* |
| 46 | * register values to turn OFDM weak signal detection OFF |
| 47 | */ |
| 48 | static const int m1ThreshLow_off = 127; |
| 49 | static const int m2ThreshLow_off = 127; |
| 50 | static const int m1Thresh_off = 127; |
| 51 | static const int m2Thresh_off = 127; |
| 52 | static const int m2CountThr_off = 31; |
| 53 | static const int m2CountThrLow_off = 63; |
| 54 | static const int m1ThreshLowExt_off = 127; |
| 55 | static const int m2ThreshLowExt_off = 127; |
| 56 | static const int m1ThreshExt_off = 127; |
| 57 | static const int m2ThreshExt_off = 127; |
| 58 | |
Lorenzo Bianconi | 23f53dd3 | 2014-11-25 00:21:40 +0100 | [diff] [blame] | 59 | static const u8 ofdm2pwr[] = { |
| 60 | ALL_TARGET_LEGACY_6_24, |
| 61 | ALL_TARGET_LEGACY_6_24, |
| 62 | ALL_TARGET_LEGACY_6_24, |
| 63 | ALL_TARGET_LEGACY_6_24, |
| 64 | ALL_TARGET_LEGACY_6_24, |
| 65 | ALL_TARGET_LEGACY_36, |
| 66 | ALL_TARGET_LEGACY_48, |
| 67 | ALL_TARGET_LEGACY_54 |
| 68 | }; |
| 69 | |
| 70 | static const u8 mcs2pwr_ht20[] = { |
| 71 | ALL_TARGET_HT20_0_8_16, |
| 72 | ALL_TARGET_HT20_1_3_9_11_17_19, |
| 73 | ALL_TARGET_HT20_1_3_9_11_17_19, |
| 74 | ALL_TARGET_HT20_1_3_9_11_17_19, |
| 75 | ALL_TARGET_HT20_4, |
| 76 | ALL_TARGET_HT20_5, |
| 77 | ALL_TARGET_HT20_6, |
| 78 | ALL_TARGET_HT20_7, |
| 79 | ALL_TARGET_HT20_0_8_16, |
| 80 | ALL_TARGET_HT20_1_3_9_11_17_19, |
| 81 | ALL_TARGET_HT20_1_3_9_11_17_19, |
| 82 | ALL_TARGET_HT20_1_3_9_11_17_19, |
| 83 | ALL_TARGET_HT20_12, |
| 84 | ALL_TARGET_HT20_13, |
| 85 | ALL_TARGET_HT20_14, |
| 86 | ALL_TARGET_HT20_15, |
| 87 | ALL_TARGET_HT20_0_8_16, |
| 88 | ALL_TARGET_HT20_1_3_9_11_17_19, |
| 89 | ALL_TARGET_HT20_1_3_9_11_17_19, |
| 90 | ALL_TARGET_HT20_1_3_9_11_17_19, |
| 91 | ALL_TARGET_HT20_20, |
| 92 | ALL_TARGET_HT20_21, |
| 93 | ALL_TARGET_HT20_22, |
| 94 | ALL_TARGET_HT20_23 |
| 95 | }; |
| 96 | |
| 97 | static const u8 mcs2pwr_ht40[] = { |
| 98 | ALL_TARGET_HT40_0_8_16, |
| 99 | ALL_TARGET_HT40_1_3_9_11_17_19, |
| 100 | ALL_TARGET_HT40_1_3_9_11_17_19, |
| 101 | ALL_TARGET_HT40_1_3_9_11_17_19, |
| 102 | ALL_TARGET_HT40_4, |
| 103 | ALL_TARGET_HT40_5, |
| 104 | ALL_TARGET_HT40_6, |
| 105 | ALL_TARGET_HT40_7, |
| 106 | ALL_TARGET_HT40_0_8_16, |
| 107 | ALL_TARGET_HT40_1_3_9_11_17_19, |
| 108 | ALL_TARGET_HT40_1_3_9_11_17_19, |
| 109 | ALL_TARGET_HT40_1_3_9_11_17_19, |
| 110 | ALL_TARGET_HT40_12, |
| 111 | ALL_TARGET_HT40_13, |
| 112 | ALL_TARGET_HT40_14, |
| 113 | ALL_TARGET_HT40_15, |
| 114 | ALL_TARGET_HT40_0_8_16, |
| 115 | ALL_TARGET_HT40_1_3_9_11_17_19, |
| 116 | ALL_TARGET_HT40_1_3_9_11_17_19, |
| 117 | ALL_TARGET_HT40_1_3_9_11_17_19, |
| 118 | ALL_TARGET_HT40_20, |
| 119 | ALL_TARGET_HT40_21, |
| 120 | ALL_TARGET_HT40_22, |
| 121 | ALL_TARGET_HT40_23, |
| 122 | }; |
| 123 | |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 124 | /** |
| 125 | * ar9003_hw_set_channel - set channel on single-chip device |
| 126 | * @ah: atheros hardware structure |
| 127 | * @chan: |
| 128 | * |
| 129 | * This is the function to change channel on single-chip devices, that is |
Mohammed Shafi Shajakhan | e4922f2 | 2012-01-07 21:06:02 +0530 | [diff] [blame] | 130 | * for AR9300 family of chipsets. |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 131 | * |
| 132 | * This function takes the channel value in MHz and sets |
| 133 | * hardware channel value. Assumes writes have been enabled to analog bus. |
| 134 | * |
| 135 | * Actual Expression, |
| 136 | * |
| 137 | * For 2GHz channel, |
| 138 | * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) |
| 139 | * (freq_ref = 40MHz) |
| 140 | * |
| 141 | * For 5GHz channel, |
| 142 | * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) |
| 143 | * (freq_ref = 40MHz/(24>>amodeRefSel)) |
| 144 | * |
| 145 | * For 5GHz channels which are 5MHz spaced, |
| 146 | * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) |
| 147 | * (freq_ref = 40MHz) |
| 148 | */ |
| 149 | static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) |
| 150 | { |
Felix Fietkau | f7abf0c | 2010-04-15 17:38:33 -0400 | [diff] [blame] | 151 | u16 bMode, fracMode = 0, aModeRefSel = 0; |
Sujith Manoharan | 1a26cda | 2013-01-08 20:57:53 +0530 | [diff] [blame] | 152 | u32 freq, chan_frac, div, channelSel = 0, reg32 = 0; |
Felix Fietkau | f7abf0c | 2010-04-15 17:38:33 -0400 | [diff] [blame] | 153 | struct chan_centers centers; |
| 154 | int loadSynthChannel; |
| 155 | |
| 156 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); |
| 157 | freq = centers.synth_center; |
| 158 | |
| 159 | if (freq < 4800) { /* 2 GHz, fractional mode */ |
Gabor Juhos | 5acb4b9 | 2011-06-21 11:23:34 +0200 | [diff] [blame] | 160 | if (AR_SREV_9330(ah)) { |
Gabor Juhos | 5acb4b9 | 2011-06-21 11:23:34 +0200 | [diff] [blame] | 161 | if (ah->is_clk_25mhz) |
| 162 | div = 75; |
| 163 | else |
| 164 | div = 120; |
| 165 | |
| 166 | channelSel = (freq * 4) / div; |
| 167 | chan_frac = (((freq * 4) % div) * 0x20000) / div; |
| 168 | channelSel = (channelSel << 17) | chan_frac; |
Sujith Manoharan | a4a2954 | 2012-09-10 09:20:03 +0530 | [diff] [blame] | 169 | } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) { |
Vasanthakumar Thiagarajan | 3dfd7f6 | 2011-04-11 16:39:40 +0530 | [diff] [blame] | 170 | /* |
Sujith Manoharan | 1a26cda | 2013-01-08 20:57:53 +0530 | [diff] [blame] | 171 | * freq_ref = 40 / (refdiva >> amoderefsel); |
| 172 | * where refdiva=1 and amoderefsel=0 |
Vasanthakumar Thiagarajan | 3dfd7f6 | 2011-04-11 16:39:40 +0530 | [diff] [blame] | 173 | * ndiv = ((chan_mhz * 4) / 3) / freq_ref; |
| 174 | * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000 |
| 175 | */ |
| 176 | channelSel = (freq * 4) / 120; |
| 177 | chan_frac = (((freq * 4) % 120) * 0x20000) / 120; |
| 178 | channelSel = (channelSel << 17) | chan_frac; |
Sujith Manoharan | 1a26cda | 2013-01-08 20:57:53 +0530 | [diff] [blame] | 179 | } else if (AR_SREV_9340(ah)) { |
Vasanthakumar Thiagarajan | 17869f4 | 2011-04-19 19:29:08 +0530 | [diff] [blame] | 180 | if (ah->is_clk_25mhz) { |
Vasanthakumar Thiagarajan | 17869f4 | 2011-04-19 19:29:08 +0530 | [diff] [blame] | 181 | channelSel = (freq * 2) / 75; |
| 182 | chan_frac = (((freq * 2) % 75) * 0x20000) / 75; |
| 183 | channelSel = (channelSel << 17) | chan_frac; |
Sujith Manoharan | 1a26cda | 2013-01-08 20:57:53 +0530 | [diff] [blame] | 184 | } else { |
Vasanthakumar Thiagarajan | 17869f4 | 2011-04-19 19:29:08 +0530 | [diff] [blame] | 185 | channelSel = CHANSEL_2G(freq) >> 1; |
Sujith Manoharan | 1a26cda | 2013-01-08 20:57:53 +0530 | [diff] [blame] | 186 | } |
Miaoqing Pan | ede6a5e | 2014-12-19 06:33:59 +0530 | [diff] [blame] | 187 | } else if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || |
| 188 | AR_SREV_9561(ah)) { |
Sujith Manoharan | 1a26cda | 2013-01-08 20:57:53 +0530 | [diff] [blame] | 189 | if (ah->is_clk_25mhz) |
| 190 | div = 75; |
| 191 | else |
| 192 | div = 120; |
| 193 | |
| 194 | channelSel = (freq * 4) / div; |
| 195 | chan_frac = (((freq * 4) % div) * 0x20000) / div; |
| 196 | channelSel = (channelSel << 17) | chan_frac; |
| 197 | } else { |
Vasanthakumar Thiagarajan | 85dd092 | 2010-12-06 04:27:45 -0800 | [diff] [blame] | 198 | channelSel = CHANSEL_2G(freq); |
Sujith Manoharan | 1a26cda | 2013-01-08 20:57:53 +0530 | [diff] [blame] | 199 | } |
Felix Fietkau | f7abf0c | 2010-04-15 17:38:33 -0400 | [diff] [blame] | 200 | /* Set to 2G mode */ |
| 201 | bMode = 1; |
| 202 | } else { |
Miaoqing Pan | ede6a5e | 2014-12-19 06:33:59 +0530 | [diff] [blame] | 203 | if ((AR_SREV_9340(ah) || AR_SREV_9550(ah) || |
| 204 | AR_SREV_9531(ah) || AR_SREV_9561(ah)) && |
Gabor Juhos | db4a3de | 2012-07-03 19:13:28 +0200 | [diff] [blame] | 205 | ah->is_clk_25mhz) { |
Felix Fietkau | 530275e | 2012-07-14 01:26:54 +0200 | [diff] [blame] | 206 | channelSel = freq / 75; |
| 207 | chan_frac = ((freq % 75) * 0x20000) / 75; |
Vasanthakumar Thiagarajan | 17869f4 | 2011-04-19 19:29:08 +0530 | [diff] [blame] | 208 | channelSel = (channelSel << 17) | chan_frac; |
| 209 | } else { |
| 210 | channelSel = CHANSEL_5G(freq); |
| 211 | /* Doubler is ON, so, divide channelSel by 2. */ |
| 212 | channelSel >>= 1; |
| 213 | } |
Felix Fietkau | f7abf0c | 2010-04-15 17:38:33 -0400 | [diff] [blame] | 214 | /* Set to 5G mode */ |
| 215 | bMode = 0; |
| 216 | } |
| 217 | |
| 218 | /* Enable fractional mode for all channels */ |
| 219 | fracMode = 1; |
| 220 | aModeRefSel = 0; |
| 221 | loadSynthChannel = 0; |
| 222 | |
| 223 | reg32 = (bMode << 29); |
| 224 | REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); |
| 225 | |
| 226 | /* Enable Long shift Select for Synthesizer */ |
| 227 | REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4, |
| 228 | AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1); |
| 229 | |
| 230 | /* Program Synth. setting */ |
| 231 | reg32 = (channelSel << 2) | (fracMode << 30) | |
| 232 | (aModeRefSel << 28) | (loadSynthChannel << 31); |
| 233 | REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); |
| 234 | |
| 235 | /* Toggle Load Synth channel bit */ |
| 236 | loadSynthChannel = 1; |
| 237 | reg32 = (channelSel << 2) | (fracMode << 30) | |
| 238 | (aModeRefSel << 28) | (loadSynthChannel << 31); |
| 239 | REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); |
| 240 | |
| 241 | ah->curchan = chan; |
Felix Fietkau | f7abf0c | 2010-04-15 17:38:33 -0400 | [diff] [blame] | 242 | |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 243 | return 0; |
| 244 | } |
| 245 | |
| 246 | /** |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 247 | * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 248 | * @ah: atheros hardware structure |
| 249 | * @chan: |
| 250 | * |
| 251 | * For single-chip solutions. Converts to baseband spur frequency given the |
| 252 | * input channel frequency and compute register settings below. |
| 253 | * |
| 254 | * Spur mitigation for MRC CCK |
| 255 | */ |
Luis R. Rodriguez | 1547da3 | 2010-04-15 17:39:15 -0400 | [diff] [blame] | 256 | static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah, |
| 257 | struct ath9k_channel *chan) |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 258 | { |
Joe Perches | 07b2fa5 | 2010-11-20 18:38:53 -0800 | [diff] [blame] | 259 | static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 }; |
Felix Fietkau | ca37555 | 2010-04-15 17:38:35 -0400 | [diff] [blame] | 260 | int cur_bb_spur, negative = 0, cck_spur_freq; |
| 261 | int i; |
Vasanthakumar Thiagarajan | d9a2545 | 2010-12-06 04:27:47 -0800 | [diff] [blame] | 262 | int range, max_spur_cnts, synth_freq; |
Rajkumar Manoharan | 4b5237c | 2012-06-21 20:34:00 +0530 | [diff] [blame] | 263 | u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan)); |
Felix Fietkau | ca37555 | 2010-04-15 17:38:35 -0400 | [diff] [blame] | 264 | |
| 265 | /* |
| 266 | * Need to verify range +/- 10 MHz in control channel, otherwise spur |
| 267 | * is out-of-band and can be ignored. |
| 268 | */ |
| 269 | |
Gabor Juhos | 8528f12 | 2012-07-03 19:13:24 +0200 | [diff] [blame] | 270 | if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || |
Miaoqing Pan | ede6a5e | 2014-12-19 06:33:59 +0530 | [diff] [blame] | 271 | AR_SREV_9550(ah) || AR_SREV_9561(ah)) { |
Vasanthakumar Thiagarajan | d9a2545 | 2010-12-06 04:27:47 -0800 | [diff] [blame] | 272 | if (spur_fbin_ptr[0] == 0) /* No spur */ |
| 273 | return; |
| 274 | max_spur_cnts = 5; |
| 275 | if (IS_CHAN_HT40(chan)) { |
| 276 | range = 19; |
| 277 | if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, |
| 278 | AR_PHY_GC_DYN2040_PRI_CH) == 0) |
| 279 | synth_freq = chan->channel + 10; |
| 280 | else |
| 281 | synth_freq = chan->channel - 10; |
| 282 | } else { |
| 283 | range = 10; |
| 284 | synth_freq = chan->channel; |
| 285 | } |
| 286 | } else { |
Rajkumar Manoharan | 38df2f0 | 2011-10-24 18:14:39 +0530 | [diff] [blame] | 287 | range = AR_SREV_9462(ah) ? 5 : 10; |
Vasanthakumar Thiagarajan | d9a2545 | 2010-12-06 04:27:47 -0800 | [diff] [blame] | 288 | max_spur_cnts = 4; |
| 289 | synth_freq = chan->channel; |
| 290 | } |
| 291 | |
| 292 | for (i = 0; i < max_spur_cnts; i++) { |
Rajkumar Manoharan | 38df2f0 | 2011-10-24 18:14:39 +0530 | [diff] [blame] | 293 | if (AR_SREV_9462(ah) && (i == 0 || i == 3)) |
| 294 | continue; |
Sujith Manoharan | d43d04a | 2012-09-10 09:20:20 +0530 | [diff] [blame] | 295 | |
Felix Fietkau | ca37555 | 2010-04-15 17:38:35 -0400 | [diff] [blame] | 296 | negative = 0; |
Gabor Juhos | 8528f12 | 2012-07-03 19:13:24 +0200 | [diff] [blame] | 297 | if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || |
Miaoqing Pan | ede6a5e | 2014-12-19 06:33:59 +0530 | [diff] [blame] | 298 | AR_SREV_9550(ah) || AR_SREV_9561(ah)) |
Gabor Juhos | 8edb254 | 2012-04-16 22:46:32 +0200 | [diff] [blame] | 299 | cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i], |
| 300 | IS_CHAN_2GHZ(chan)); |
Vasanthakumar Thiagarajan | d9a2545 | 2010-12-06 04:27:47 -0800 | [diff] [blame] | 301 | else |
Gabor Juhos | 8edb254 | 2012-04-16 22:46:32 +0200 | [diff] [blame] | 302 | cur_bb_spur = spur_freq[i]; |
Felix Fietkau | ca37555 | 2010-04-15 17:38:35 -0400 | [diff] [blame] | 303 | |
Gabor Juhos | 8edb254 | 2012-04-16 22:46:32 +0200 | [diff] [blame] | 304 | cur_bb_spur -= synth_freq; |
Felix Fietkau | ca37555 | 2010-04-15 17:38:35 -0400 | [diff] [blame] | 305 | if (cur_bb_spur < 0) { |
| 306 | negative = 1; |
| 307 | cur_bb_spur = -cur_bb_spur; |
| 308 | } |
Vasanthakumar Thiagarajan | d9a2545 | 2010-12-06 04:27:47 -0800 | [diff] [blame] | 309 | if (cur_bb_spur < range) { |
Felix Fietkau | ca37555 | 2010-04-15 17:38:35 -0400 | [diff] [blame] | 310 | cck_spur_freq = (int)((cur_bb_spur << 19) / 11); |
| 311 | |
| 312 | if (negative == 1) |
| 313 | cck_spur_freq = -cck_spur_freq; |
| 314 | |
| 315 | cck_spur_freq = cck_spur_freq & 0xfffff; |
| 316 | |
| 317 | REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, |
| 318 | AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7); |
| 319 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, |
| 320 | AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f); |
| 321 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, |
| 322 | AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, |
| 323 | 0x2); |
| 324 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, |
| 325 | AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, |
| 326 | 0x1); |
| 327 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, |
| 328 | AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, |
| 329 | cck_spur_freq); |
| 330 | |
| 331 | return; |
| 332 | } |
| 333 | } |
| 334 | |
| 335 | REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, |
| 336 | AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5); |
| 337 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, |
| 338 | AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0); |
| 339 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, |
| 340 | AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0); |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 341 | } |
| 342 | |
Luis R. Rodriguez | 1547da3 | 2010-04-15 17:39:15 -0400 | [diff] [blame] | 343 | /* Clean all spur register fields */ |
| 344 | static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah) |
| 345 | { |
| 346 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, |
| 347 | AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0); |
| 348 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, |
| 349 | AR_PHY_TIMING11_SPUR_FREQ_SD, 0); |
| 350 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, |
| 351 | AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0); |
| 352 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, |
| 353 | AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0); |
| 354 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, |
| 355 | AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0); |
| 356 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, |
| 357 | AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0); |
| 358 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, |
| 359 | AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0); |
| 360 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, |
| 361 | AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0); |
| 362 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, |
| 363 | AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0); |
| 364 | |
| 365 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, |
| 366 | AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0); |
| 367 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, |
| 368 | AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0); |
| 369 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, |
| 370 | AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0); |
| 371 | REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, |
| 372 | AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0); |
| 373 | REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, |
| 374 | AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0); |
| 375 | REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, |
| 376 | AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0); |
| 377 | REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, |
| 378 | AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0); |
| 379 | REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, |
| 380 | AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0); |
| 381 | REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, |
| 382 | AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0); |
| 383 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, |
| 384 | AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0); |
| 385 | } |
| 386 | |
| 387 | static void ar9003_hw_spur_ofdm(struct ath_hw *ah, |
| 388 | int freq_offset, |
| 389 | int spur_freq_sd, |
| 390 | int spur_delta_phase, |
Sujith Manoharan | d43d04a | 2012-09-10 09:20:20 +0530 | [diff] [blame] | 391 | int spur_subchannel_sd, |
| 392 | int range, |
| 393 | int synth_freq) |
Luis R. Rodriguez | 1547da3 | 2010-04-15 17:39:15 -0400 | [diff] [blame] | 394 | { |
| 395 | int mask_index = 0; |
| 396 | |
| 397 | /* OFDM Spur mitigation */ |
| 398 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, |
| 399 | AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1); |
| 400 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, |
| 401 | AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd); |
| 402 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, |
| 403 | AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase); |
| 404 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, |
| 405 | AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd); |
| 406 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, |
| 407 | AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1); |
Sujith Manoharan | d43d04a | 2012-09-10 09:20:20 +0530 | [diff] [blame] | 408 | |
| 409 | if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437)) |
| 410 | REG_RMW_FIELD(ah, AR_PHY_TIMING11, |
| 411 | AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1); |
| 412 | |
Luis R. Rodriguez | 1547da3 | 2010-04-15 17:39:15 -0400 | [diff] [blame] | 413 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, |
| 414 | AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1); |
| 415 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, |
| 416 | AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34); |
| 417 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, |
| 418 | AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1); |
| 419 | |
Felix Fietkau | 23dd9b2 | 2013-05-23 12:20:54 +0200 | [diff] [blame] | 420 | if (!AR_SREV_9340(ah) && |
| 421 | REG_READ_FIELD(ah, AR_PHY_MODE, |
Luis R. Rodriguez | 1547da3 | 2010-04-15 17:39:15 -0400 | [diff] [blame] | 422 | AR_PHY_MODE_DYNAMIC) == 0x1) |
| 423 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, |
| 424 | AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1); |
| 425 | |
| 426 | mask_index = (freq_offset << 4) / 5; |
| 427 | if (mask_index < 0) |
| 428 | mask_index = mask_index - 1; |
| 429 | |
| 430 | mask_index = mask_index & 0x7f; |
| 431 | |
| 432 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, |
| 433 | AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1); |
| 434 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, |
| 435 | AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1); |
| 436 | REG_RMW_FIELD(ah, AR_PHY_TIMING4, |
| 437 | AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1); |
| 438 | REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, |
| 439 | AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index); |
| 440 | REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, |
| 441 | AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index); |
| 442 | REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, |
| 443 | AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index); |
| 444 | REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, |
| 445 | AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc); |
| 446 | REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, |
| 447 | AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc); |
| 448 | REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A, |
| 449 | AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0); |
| 450 | REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, |
| 451 | AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff); |
| 452 | } |
| 453 | |
Sujith Manoharan | d43d04a | 2012-09-10 09:20:20 +0530 | [diff] [blame] | 454 | static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah, |
| 455 | int freq_offset) |
| 456 | { |
| 457 | int mask_index = 0; |
| 458 | |
| 459 | mask_index = (freq_offset << 4) / 5; |
| 460 | if (mask_index < 0) |
| 461 | mask_index = mask_index - 1; |
| 462 | |
| 463 | mask_index = mask_index & 0x7f; |
| 464 | |
| 465 | REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, |
| 466 | AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B, |
| 467 | mask_index); |
| 468 | |
| 469 | /* A == B */ |
| 470 | REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B, |
| 471 | AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, |
| 472 | mask_index); |
| 473 | |
| 474 | REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, |
| 475 | AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B, |
| 476 | mask_index); |
| 477 | REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK, |
| 478 | AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe); |
| 479 | REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK, |
| 480 | AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe); |
| 481 | |
| 482 | /* A == B */ |
| 483 | REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B, |
| 484 | AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0); |
| 485 | } |
| 486 | |
Luis R. Rodriguez | 1547da3 | 2010-04-15 17:39:15 -0400 | [diff] [blame] | 487 | static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah, |
| 488 | struct ath9k_channel *chan, |
Sujith Manoharan | d43d04a | 2012-09-10 09:20:20 +0530 | [diff] [blame] | 489 | int freq_offset, |
| 490 | int range, |
| 491 | int synth_freq) |
Luis R. Rodriguez | 1547da3 | 2010-04-15 17:39:15 -0400 | [diff] [blame] | 492 | { |
| 493 | int spur_freq_sd = 0; |
| 494 | int spur_subchannel_sd = 0; |
| 495 | int spur_delta_phase = 0; |
| 496 | |
| 497 | if (IS_CHAN_HT40(chan)) { |
| 498 | if (freq_offset < 0) { |
| 499 | if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, |
| 500 | AR_PHY_GC_DYN2040_PRI_CH) == 0x0) |
| 501 | spur_subchannel_sd = 1; |
| 502 | else |
| 503 | spur_subchannel_sd = 0; |
| 504 | |
Rajkumar Manoharan | 9d1ceac | 2012-05-01 09:12:24 +0530 | [diff] [blame] | 505 | spur_freq_sd = ((freq_offset + 10) << 9) / 11; |
Luis R. Rodriguez | 1547da3 | 2010-04-15 17:39:15 -0400 | [diff] [blame] | 506 | |
| 507 | } else { |
| 508 | if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, |
| 509 | AR_PHY_GC_DYN2040_PRI_CH) == 0x0) |
| 510 | spur_subchannel_sd = 0; |
| 511 | else |
| 512 | spur_subchannel_sd = 1; |
| 513 | |
Rajkumar Manoharan | 9d1ceac | 2012-05-01 09:12:24 +0530 | [diff] [blame] | 514 | spur_freq_sd = ((freq_offset - 10) << 9) / 11; |
Luis R. Rodriguez | 1547da3 | 2010-04-15 17:39:15 -0400 | [diff] [blame] | 515 | |
| 516 | } |
| 517 | |
| 518 | spur_delta_phase = (freq_offset << 17) / 5; |
| 519 | |
| 520 | } else { |
| 521 | spur_subchannel_sd = 0; |
| 522 | spur_freq_sd = (freq_offset << 9) /11; |
| 523 | spur_delta_phase = (freq_offset << 18) / 5; |
| 524 | } |
| 525 | |
| 526 | spur_freq_sd = spur_freq_sd & 0x3ff; |
| 527 | spur_delta_phase = spur_delta_phase & 0xfffff; |
| 528 | |
| 529 | ar9003_hw_spur_ofdm(ah, |
| 530 | freq_offset, |
| 531 | spur_freq_sd, |
| 532 | spur_delta_phase, |
Sujith Manoharan | d43d04a | 2012-09-10 09:20:20 +0530 | [diff] [blame] | 533 | spur_subchannel_sd, |
| 534 | range, synth_freq); |
Luis R. Rodriguez | 1547da3 | 2010-04-15 17:39:15 -0400 | [diff] [blame] | 535 | } |
| 536 | |
| 537 | /* Spur mitigation for OFDM */ |
| 538 | static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah, |
| 539 | struct ath9k_channel *chan) |
| 540 | { |
| 541 | int synth_freq; |
| 542 | int range = 10; |
| 543 | int freq_offset = 0; |
| 544 | int mode; |
| 545 | u8* spurChansPtr; |
| 546 | unsigned int i; |
| 547 | struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; |
| 548 | |
| 549 | if (IS_CHAN_5GHZ(chan)) { |
| 550 | spurChansPtr = &(eep->modalHeader5G.spurChans[0]); |
| 551 | mode = 0; |
| 552 | } |
| 553 | else { |
| 554 | spurChansPtr = &(eep->modalHeader2G.spurChans[0]); |
| 555 | mode = 1; |
| 556 | } |
| 557 | |
| 558 | if (spurChansPtr[0] == 0) |
| 559 | return; /* No spur in the mode */ |
| 560 | |
| 561 | if (IS_CHAN_HT40(chan)) { |
| 562 | range = 19; |
| 563 | if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, |
| 564 | AR_PHY_GC_DYN2040_PRI_CH) == 0x0) |
| 565 | synth_freq = chan->channel - 10; |
| 566 | else |
| 567 | synth_freq = chan->channel + 10; |
| 568 | } else { |
| 569 | range = 10; |
| 570 | synth_freq = chan->channel; |
| 571 | } |
| 572 | |
| 573 | ar9003_hw_spur_ofdm_clear(ah); |
| 574 | |
roel | 0f8e94d | 2011-04-10 21:09:50 +0200 | [diff] [blame] | 575 | for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) { |
Gabor Juhos | 8edb254 | 2012-04-16 22:46:32 +0200 | [diff] [blame] | 576 | freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode); |
| 577 | freq_offset -= synth_freq; |
Luis R. Rodriguez | 1547da3 | 2010-04-15 17:39:15 -0400 | [diff] [blame] | 578 | if (abs(freq_offset) < range) { |
Sujith Manoharan | d43d04a | 2012-09-10 09:20:20 +0530 | [diff] [blame] | 579 | ar9003_hw_spur_ofdm_work(ah, chan, freq_offset, |
| 580 | range, synth_freq); |
| 581 | |
| 582 | if (AR_SREV_9565(ah) && (i < 4)) { |
| 583 | freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1], |
| 584 | mode); |
| 585 | freq_offset -= synth_freq; |
| 586 | if (abs(freq_offset) < range) |
| 587 | ar9003_hw_spur_ofdm_9565(ah, freq_offset); |
| 588 | } |
| 589 | |
Luis R. Rodriguez | 1547da3 | 2010-04-15 17:39:15 -0400 | [diff] [blame] | 590 | break; |
| 591 | } |
| 592 | } |
| 593 | } |
| 594 | |
| 595 | static void ar9003_hw_spur_mitigate(struct ath_hw *ah, |
| 596 | struct ath9k_channel *chan) |
| 597 | { |
Sujith Manoharan | d43d04a | 2012-09-10 09:20:20 +0530 | [diff] [blame] | 598 | if (!AR_SREV_9565(ah)) |
| 599 | ar9003_hw_spur_mitigate_mrc_cck(ah, chan); |
Luis R. Rodriguez | 1547da3 | 2010-04-15 17:39:15 -0400 | [diff] [blame] | 600 | ar9003_hw_spur_mitigate_ofdm(ah, chan); |
| 601 | } |
| 602 | |
Felix Fietkau | 5fb9b1b | 2014-09-29 20:45:42 +0200 | [diff] [blame] | 603 | static u32 ar9003_hw_compute_pll_control_soc(struct ath_hw *ah, |
| 604 | struct ath9k_channel *chan) |
| 605 | { |
| 606 | u32 pll; |
| 607 | |
| 608 | pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV); |
| 609 | |
| 610 | if (chan && IS_CHAN_HALF_RATE(chan)) |
| 611 | pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL); |
| 612 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) |
| 613 | pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL); |
| 614 | |
| 615 | pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT); |
| 616 | |
| 617 | return pll; |
| 618 | } |
| 619 | |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 620 | static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah, |
| 621 | struct ath9k_channel *chan) |
| 622 | { |
Felix Fietkau | 317d332 | 2010-04-15 17:38:34 -0400 | [diff] [blame] | 623 | u32 pll; |
| 624 | |
| 625 | pll = SM(0x5, AR_RTC_9300_PLL_REFDIV); |
| 626 | |
| 627 | if (chan && IS_CHAN_HALF_RATE(chan)) |
| 628 | pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL); |
| 629 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) |
| 630 | pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL); |
| 631 | |
Felix Fietkau | 14bc110 | 2010-04-26 15:04:30 -0400 | [diff] [blame] | 632 | pll |= SM(0x2c, AR_RTC_9300_PLL_DIV); |
Felix Fietkau | 317d332 | 2010-04-15 17:38:34 -0400 | [diff] [blame] | 633 | |
| 634 | return pll; |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 635 | } |
| 636 | |
| 637 | static void ar9003_hw_set_channel_regs(struct ath_hw *ah, |
| 638 | struct ath9k_channel *chan) |
| 639 | { |
Luis R. Rodriguez | cffb5e4 | 2010-04-15 17:38:38 -0400 | [diff] [blame] | 640 | u32 phymode; |
| 641 | u32 enableDacFifo = 0; |
| 642 | |
| 643 | enableDacFifo = |
| 644 | (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO); |
| 645 | |
| 646 | /* Enable 11n HT, 20 MHz */ |
Miaoqing Pan | ede6a5e | 2014-12-19 06:33:59 +0530 | [diff] [blame] | 647 | phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SHORT_GI_40 | enableDacFifo; |
| 648 | |
| 649 | if (!AR_SREV_9561(ah)) |
| 650 | phymode |= AR_PHY_GC_SINGLE_HT_LTF1; |
Luis R. Rodriguez | cffb5e4 | 2010-04-15 17:38:38 -0400 | [diff] [blame] | 651 | |
| 652 | /* Configure baseband for dynamic 20/40 operation */ |
| 653 | if (IS_CHAN_HT40(chan)) { |
| 654 | phymode |= AR_PHY_GC_DYN2040_EN; |
| 655 | /* Configure control (primary) channel at +-10MHz */ |
Felix Fietkau | 8896934 | 2013-10-11 23:30:53 +0200 | [diff] [blame] | 656 | if (IS_CHAN_HT40PLUS(chan)) |
Luis R. Rodriguez | cffb5e4 | 2010-04-15 17:38:38 -0400 | [diff] [blame] | 657 | phymode |= AR_PHY_GC_DYN2040_PRI_CH; |
| 658 | |
| 659 | } |
| 660 | |
| 661 | /* make sure we preserve INI settings */ |
| 662 | phymode |= REG_READ(ah, AR_PHY_GEN_CTRL); |
| 663 | /* turn off Green Field detection for STA for now */ |
| 664 | phymode &= ~AR_PHY_GC_GF_DETECT_EN; |
| 665 | |
| 666 | REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode); |
| 667 | |
| 668 | /* Configure MAC for 20/40 operation */ |
Felix Fietkau | e4744ec | 2013-10-11 23:31:01 +0200 | [diff] [blame] | 669 | ath9k_hw_set11nmac2040(ah, chan); |
Luis R. Rodriguez | cffb5e4 | 2010-04-15 17:38:38 -0400 | [diff] [blame] | 670 | |
| 671 | /* global transmit timeout (25 TUs default)*/ |
| 672 | REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); |
| 673 | /* carrier sense timeout */ |
| 674 | REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 675 | } |
| 676 | |
| 677 | static void ar9003_hw_init_bb(struct ath_hw *ah, |
| 678 | struct ath9k_channel *chan) |
| 679 | { |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 680 | u32 synthDelay; |
| 681 | |
| 682 | /* |
| 683 | * Wait for the frequency synth to settle (synth goes on |
| 684 | * via AR_PHY_ACTIVE_EN). Read the phy active delay register. |
| 685 | * Value is in 100ns increments. |
| 686 | */ |
| 687 | synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 688 | |
| 689 | /* Activate the PHY (includes baseband activate + synthesizer on) */ |
| 690 | REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); |
Felix Fietkau | 7c5adc8 | 2012-04-19 21:18:26 +0200 | [diff] [blame] | 691 | ath9k_hw_synth_delay(ah, chan, synthDelay); |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 692 | } |
| 693 | |
Felix Fietkau | 4a8f199 | 2013-01-20 21:55:20 +0100 | [diff] [blame] | 694 | void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx) |
Luis R. Rodriguez | cffb5e4 | 2010-04-15 17:38:38 -0400 | [diff] [blame] | 695 | { |
Felix Fietkau | 24171dd | 2013-01-20 21:55:21 +0100 | [diff] [blame] | 696 | if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5) |
Luis R. Rodriguez | cffb5e4 | 2010-04-15 17:38:38 -0400 | [diff] [blame] | 697 | REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, |
| 698 | AR_PHY_SWAP_ALT_CHAIN); |
Felix Fietkau | 24171dd | 2013-01-20 21:55:21 +0100 | [diff] [blame] | 699 | |
| 700 | REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx); |
| 701 | REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx); |
Luis R. Rodriguez | cffb5e4 | 2010-04-15 17:38:38 -0400 | [diff] [blame] | 702 | |
Mohammed Shafi Shajakhan | ea066d5 | 2010-11-23 20:42:27 +0530 | [diff] [blame] | 703 | if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7)) |
Felix Fietkau | 24171dd | 2013-01-20 21:55:21 +0100 | [diff] [blame] | 704 | tx = 3; |
Mohammed Shafi Shajakhan | ea066d5 | 2010-11-23 20:42:27 +0530 | [diff] [blame] | 705 | |
Felix Fietkau | 24171dd | 2013-01-20 21:55:21 +0100 | [diff] [blame] | 706 | REG_WRITE(ah, AR_SELFGEN_MASK, tx); |
Luis R. Rodriguez | cffb5e4 | 2010-04-15 17:38:38 -0400 | [diff] [blame] | 707 | } |
| 708 | |
| 709 | /* |
| 710 | * Override INI values with chip specific configuration. |
| 711 | */ |
| 712 | static void ar9003_hw_override_ini(struct ath_hw *ah) |
| 713 | { |
| 714 | u32 val; |
| 715 | |
| 716 | /* |
| 717 | * Set the RX_ABORT and RX_DIS and clear it only after |
| 718 | * RXE is set for MAC. This prevents frames with |
| 719 | * corrupted descriptor status. |
| 720 | */ |
| 721 | REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); |
| 722 | |
| 723 | /* |
| 724 | * For AR9280 and above, there is a new feature that allows |
| 725 | * Multicast search based on both MAC Address and Key ID. By default, |
| 726 | * this feature is enabled. But since the driver is not using this |
| 727 | * feature, we switch it off; otherwise multicast search based on |
| 728 | * MAC addr only will fail. |
| 729 | */ |
| 730 | val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); |
Sujith Manoharan | 9ef4893 | 2013-09-11 11:40:58 +0530 | [diff] [blame] | 731 | val |= AR_AGG_WEP_ENABLE_FIX | |
| 732 | AR_AGG_WEP_ENABLE | |
| 733 | AR_PCU_MISC_MODE2_CFP_IGNORE; |
| 734 | REG_WRITE(ah, AR_PCU_MISC_MODE2, val); |
Felix Fietkau | bf3f204 | 2011-09-15 14:25:37 +0200 | [diff] [blame] | 735 | |
Sujith Manoharan | 4b03f16 | 2013-07-16 12:03:17 +0530 | [diff] [blame] | 736 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { |
| 737 | REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE, |
| 738 | AR_GLB_SWREG_DISCONT_EN_BT_WLAN); |
| 739 | |
| 740 | if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0, |
| 741 | AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL)) |
| 742 | ah->enabled_cals |= TX_IQ_CAL; |
| 743 | else |
| 744 | ah->enabled_cals &= ~TX_IQ_CAL; |
| 745 | |
Sujith Manoharan | 4b03f16 | 2013-07-16 12:03:17 +0530 | [diff] [blame] | 746 | } |
Sujith Manoharan | 34d9b68 | 2013-11-15 13:05:18 +0530 | [diff] [blame] | 747 | |
| 748 | if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) |
| 749 | ah->enabled_cals |= TX_CL_CAL; |
| 750 | else |
| 751 | ah->enabled_cals &= ~TX_CL_CAL; |
Miaoqing Pan | 4e6ce4d | 2014-11-06 10:52:23 +0530 | [diff] [blame] | 752 | |
Miaoqing Pan | ede6a5e | 2014-12-19 06:33:59 +0530 | [diff] [blame] | 753 | if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah) || |
| 754 | AR_SREV_9561(ah)) { |
Miaoqing Pan | 4e6ce4d | 2014-11-06 10:52:23 +0530 | [diff] [blame] | 755 | if (ah->is_clk_25mhz) { |
| 756 | REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); |
| 757 | REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); |
| 758 | REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); |
| 759 | } else { |
| 760 | REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1); |
| 761 | REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); |
| 762 | REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); |
| 763 | } |
| 764 | udelay(100); |
| 765 | } |
Luis R. Rodriguez | cffb5e4 | 2010-04-15 17:38:38 -0400 | [diff] [blame] | 766 | } |
| 767 | |
| 768 | static void ar9003_hw_prog_ini(struct ath_hw *ah, |
| 769 | struct ar5416IniArray *iniArr, |
| 770 | int column) |
| 771 | { |
| 772 | unsigned int i, regWrites = 0; |
| 773 | |
| 774 | /* New INI format: Array may be undefined (pre, core, post arrays) */ |
| 775 | if (!iniArr->ia_array) |
| 776 | return; |
| 777 | |
| 778 | /* |
| 779 | * New INI format: Pre, core, and post arrays for a given subsystem |
| 780 | * may be modal (> 2 columns) or non-modal (2 columns). Determine if |
| 781 | * the array is non-modal and force the column to 1. |
| 782 | */ |
| 783 | if (column >= iniArr->ia_columns) |
| 784 | column = 1; |
| 785 | |
| 786 | for (i = 0; i < iniArr->ia_rows; i++) { |
| 787 | u32 reg = INI_RA(iniArr, i, 0); |
| 788 | u32 val = INI_RA(iniArr, i, column); |
| 789 | |
Vasanthakumar Thiagarajan | 7e68b74 | 2010-12-15 07:30:47 -0800 | [diff] [blame] | 790 | REG_WRITE(ah, reg, val); |
Felix Fietkau | b2ccc50 | 2010-07-30 21:02:12 +0200 | [diff] [blame] | 791 | |
Luis R. Rodriguez | cffb5e4 | 2010-04-15 17:38:38 -0400 | [diff] [blame] | 792 | DO_DELAY(regWrites); |
| 793 | } |
| 794 | } |
| 795 | |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 796 | static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah, |
| 797 | struct ath9k_channel *chan) |
| 798 | { |
| 799 | int ret; |
| 800 | |
Felix Fietkau | 8896934 | 2013-10-11 23:30:53 +0200 | [diff] [blame] | 801 | if (IS_CHAN_2GHZ(chan)) { |
| 802 | if (IS_CHAN_HT40(chan)) |
| 803 | return 7; |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 804 | else |
Felix Fietkau | 8896934 | 2013-10-11 23:30:53 +0200 | [diff] [blame] | 805 | return 8; |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 806 | } |
| 807 | |
Felix Fietkau | 8896934 | 2013-10-11 23:30:53 +0200 | [diff] [blame] | 808 | if (chan->channel <= 5350) |
| 809 | ret = 1; |
| 810 | else if ((chan->channel > 5350) && (chan->channel <= 5600)) |
| 811 | ret = 3; |
| 812 | else |
| 813 | ret = 5; |
| 814 | |
| 815 | if (IS_CHAN_HT40(chan)) |
| 816 | ret++; |
| 817 | |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 818 | return ret; |
| 819 | } |
| 820 | |
Miaoqing Pan | ede6a5e | 2014-12-19 06:33:59 +0530 | [diff] [blame] | 821 | static int ar9561_hw_get_modes_txgain_index(struct ath_hw *ah, |
| 822 | struct ath9k_channel *chan) |
| 823 | { |
| 824 | if (IS_CHAN_2GHZ(chan)) { |
| 825 | if (IS_CHAN_HT40(chan)) |
| 826 | return 1; |
| 827 | else |
| 828 | return 2; |
| 829 | } |
| 830 | |
| 831 | return 0; |
| 832 | } |
| 833 | |
Sujith Manoharan | 6fcbe53 | 2013-11-14 15:26:06 +0530 | [diff] [blame] | 834 | static void ar9003_doubler_fix(struct ath_hw *ah) |
| 835 | { |
| 836 | if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) { |
| 837 | REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, |
| 838 | 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | |
| 839 | 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0); |
| 840 | REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, |
| 841 | 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | |
| 842 | 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0); |
| 843 | REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, |
| 844 | 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | |
| 845 | 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0); |
| 846 | |
| 847 | udelay(200); |
| 848 | |
| 849 | REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2, |
| 850 | AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK); |
| 851 | REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2, |
| 852 | AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK); |
| 853 | REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2, |
| 854 | AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK); |
| 855 | |
| 856 | udelay(1); |
| 857 | |
| 858 | REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2, |
| 859 | AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1); |
| 860 | REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2, |
| 861 | AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1); |
| 862 | REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2, |
| 863 | AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1); |
| 864 | |
| 865 | udelay(200); |
| 866 | |
| 867 | REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12, |
| 868 | AR_PHY_65NM_CH0_SYNTH12_VREFMUL3, 0xf); |
| 869 | |
| 870 | REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0, |
| 871 | 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | |
| 872 | 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S); |
| 873 | REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0, |
| 874 | 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | |
| 875 | 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S); |
| 876 | REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0, |
| 877 | 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | |
| 878 | 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S); |
| 879 | } |
| 880 | } |
| 881 | |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 882 | static int ar9003_hw_process_ini(struct ath_hw *ah, |
| 883 | struct ath9k_channel *chan) |
| 884 | { |
Luis R. Rodriguez | cffb5e4 | 2010-04-15 17:38:38 -0400 | [diff] [blame] | 885 | unsigned int regWrites = 0, i; |
Sujith Manoharan | 0ff2b5c | 2011-04-20 11:00:34 +0530 | [diff] [blame] | 886 | u32 modesIndex; |
Luis R. Rodriguez | cffb5e4 | 2010-04-15 17:38:38 -0400 | [diff] [blame] | 887 | |
Felix Fietkau | 8896934 | 2013-10-11 23:30:53 +0200 | [diff] [blame] | 888 | if (IS_CHAN_5GHZ(chan)) |
| 889 | modesIndex = IS_CHAN_HT40(chan) ? 2 : 1; |
| 890 | else |
| 891 | modesIndex = IS_CHAN_HT40(chan) ? 3 : 4; |
Luis R. Rodriguez | cffb5e4 | 2010-04-15 17:38:38 -0400 | [diff] [blame] | 892 | |
Sujith Manoharan | 51dbd0a | 2013-06-18 10:13:42 +0530 | [diff] [blame] | 893 | /* |
| 894 | * SOC, MAC, BB, RADIO initvals. |
| 895 | */ |
Luis R. Rodriguez | cffb5e4 | 2010-04-15 17:38:38 -0400 | [diff] [blame] | 896 | for (i = 0; i < ATH_INI_NUM_SPLIT; i++) { |
| 897 | ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex); |
| 898 | ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex); |
| 899 | ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex); |
| 900 | ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex); |
Sujith Manoharan | 2b5e54e | 2013-06-24 18:18:46 +0530 | [diff] [blame] | 901 | if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah)) |
Senthil Balasubramanian | 2577c6e | 2011-09-13 22:38:18 +0530 | [diff] [blame] | 902 | ar9003_hw_prog_ini(ah, |
| 903 | &ah->ini_radio_post_sys2ant, |
| 904 | modesIndex); |
Luis R. Rodriguez | cffb5e4 | 2010-04-15 17:38:38 -0400 | [diff] [blame] | 905 | } |
| 906 | |
Sujith Manoharan | 6fcbe53 | 2013-11-14 15:26:06 +0530 | [diff] [blame] | 907 | ar9003_doubler_fix(ah); |
| 908 | |
Sujith Manoharan | 51dbd0a | 2013-06-18 10:13:42 +0530 | [diff] [blame] | 909 | /* |
| 910 | * RXGAIN initvals. |
| 911 | */ |
Luis R. Rodriguez | cffb5e4 | 2010-04-15 17:38:38 -0400 | [diff] [blame] | 912 | REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites); |
Sujith Manoharan | 51dbd0a | 2013-06-18 10:13:42 +0530 | [diff] [blame] | 913 | |
Sujith Manoharan | 2b5e54e | 2013-06-24 18:18:46 +0530 | [diff] [blame] | 914 | if (AR_SREV_9462_20_OR_LATER(ah)) { |
Sujith Manoharan | 51dbd0a | 2013-06-18 10:13:42 +0530 | [diff] [blame] | 915 | /* |
Sujith Manoharan | c177fab | 2013-06-18 15:42:38 +0530 | [diff] [blame] | 916 | * CUS217 mix LNA mode. |
| 917 | */ |
| 918 | if (ar9003_hw_get_rx_gain_idx(ah) == 2) { |
| 919 | REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core, |
| 920 | 1, regWrites); |
| 921 | REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble, |
| 922 | modesIndex, regWrites); |
| 923 | } |
| 924 | |
| 925 | /* |
Sujith Manoharan | 51dbd0a | 2013-06-18 10:13:42 +0530 | [diff] [blame] | 926 | * 5G-XLNA |
| 927 | */ |
| 928 | if ((ar9003_hw_get_rx_gain_idx(ah) == 2) || |
| 929 | (ar9003_hw_get_rx_gain_idx(ah) == 3)) { |
Miaoqing Pan | 871d005 | 2015-09-29 13:24:36 +0800 | [diff] [blame] | 930 | REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna, |
Sujith Manoharan | 51dbd0a | 2013-06-18 10:13:42 +0530 | [diff] [blame] | 931 | modesIndex, regWrites); |
| 932 | } |
| 933 | } |
| 934 | |
Miaoqing Pan | ede6a5e | 2014-12-19 06:33:59 +0530 | [diff] [blame] | 935 | if (AR_SREV_9550(ah) || AR_SREV_9561(ah)) |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 936 | REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex, |
| 937 | regWrites); |
| 938 | |
Miaoqing Pan | cfa2b42 | 2015-09-29 13:24:37 +0800 | [diff] [blame] | 939 | if (AR_SREV_9561(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0)) |
| 940 | REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna, |
| 941 | modesIndex, regWrites); |
Sujith Manoharan | 51dbd0a | 2013-06-18 10:13:42 +0530 | [diff] [blame] | 942 | /* |
| 943 | * TXGAIN initvals. |
| 944 | */ |
Miaoqing Pan | ede6a5e | 2014-12-19 06:33:59 +0530 | [diff] [blame] | 945 | if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) { |
Sujith Manoharan | 2c32305 | 2013-12-31 08:12:02 +0530 | [diff] [blame] | 946 | int modes_txgain_index = 1; |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 947 | |
Sujith Manoharan | 2c32305 | 2013-12-31 08:12:02 +0530 | [diff] [blame] | 948 | if (AR_SREV_9550(ah)) |
| 949 | modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan); |
| 950 | |
Miaoqing Pan | ede6a5e | 2014-12-19 06:33:59 +0530 | [diff] [blame] | 951 | if (AR_SREV_9561(ah)) |
| 952 | modes_txgain_index = |
| 953 | ar9561_hw_get_modes_txgain_index(ah, chan); |
| 954 | |
Gabor Juhos | 8bc45c6 | 2012-07-03 19:13:23 +0200 | [diff] [blame] | 955 | if (modes_txgain_index < 0) |
| 956 | return -EINVAL; |
| 957 | |
| 958 | REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index, |
| 959 | regWrites); |
| 960 | } else { |
| 961 | REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); |
| 962 | } |
Luis R. Rodriguez | cffb5e4 | 2010-04-15 17:38:38 -0400 | [diff] [blame] | 963 | |
| 964 | /* |
| 965 | * For 5GHz channels requiring Fast Clock, apply |
| 966 | * different modal values. |
| 967 | */ |
Felix Fietkau | 6b42e8d | 2010-04-26 15:04:35 -0400 | [diff] [blame] | 968 | if (IS_CHAN_A_FAST_CLOCK(ah, chan)) |
Felix Fietkau | c7d36f9 | 2012-03-14 16:40:31 +0100 | [diff] [blame] | 969 | REG_WRITE_ARRAY(&ah->iniModesFastClock, |
Luis R. Rodriguez | cffb5e4 | 2010-04-15 17:38:38 -0400 | [diff] [blame] | 970 | modesIndex, regWrites); |
| 971 | |
Sujith Manoharan | 51dbd0a | 2013-06-18 10:13:42 +0530 | [diff] [blame] | 972 | /* |
| 973 | * Clock frequency initvals. |
| 974 | */ |
Felix Fietkau | c7d36f9 | 2012-03-14 16:40:31 +0100 | [diff] [blame] | 975 | REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites); |
Vasanthakumar Thiagarajan | d89baac | 2011-04-19 19:29:04 +0530 | [diff] [blame] | 976 | |
Sujith Manoharan | 51dbd0a | 2013-06-18 10:13:42 +0530 | [diff] [blame] | 977 | /* |
| 978 | * JAPAN regulatory. |
| 979 | */ |
Miaoqing Pan | 25c0f30 | 2016-02-18 17:20:02 +0800 | [diff] [blame] | 980 | if (chan->channel == 2484) { |
Sujith Manoharan | 57527f8 | 2012-11-13 11:33:53 +0530 | [diff] [blame] | 981 | ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); |
Felix Fietkau | 9951c4d | 2012-03-14 16:40:30 +0100 | [diff] [blame] | 982 | |
Miaoqing Pan | 25c0f30 | 2016-02-18 17:20:02 +0800 | [diff] [blame] | 983 | if (AR_SREV_9531(ah)) |
| 984 | REG_RMW_FIELD(ah, AR_PHY_FCAL_2_0, |
| 985 | AR_PHY_FLC_PWR_THRESH, 0); |
| 986 | } |
| 987 | |
Rajkumar Manoharan | 5f0c04e | 2011-10-13 11:00:35 +0530 | [diff] [blame] | 988 | ah->modes_index = modesIndex; |
Luis R. Rodriguez | cffb5e4 | 2010-04-15 17:38:38 -0400 | [diff] [blame] | 989 | ar9003_hw_override_ini(ah); |
| 990 | ar9003_hw_set_channel_regs(ah, chan); |
| 991 | ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); |
Gabor Juhos | 64ea57d | 2012-04-15 20:38:05 +0200 | [diff] [blame] | 992 | ath9k_hw_apply_txpower(ah, chan, false); |
Luis R. Rodriguez | cffb5e4 | 2010-04-15 17:38:38 -0400 | [diff] [blame] | 993 | |
| 994 | return 0; |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 995 | } |
| 996 | |
| 997 | static void ar9003_hw_set_rfmode(struct ath_hw *ah, |
| 998 | struct ath9k_channel *chan) |
| 999 | { |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1000 | u32 rfMode = 0; |
| 1001 | |
| 1002 | if (chan == NULL) |
| 1003 | return; |
| 1004 | |
Felix Fietkau | 1a5e632 | 2013-10-11 23:30:54 +0200 | [diff] [blame] | 1005 | if (IS_CHAN_2GHZ(chan)) |
| 1006 | rfMode |= AR_PHY_MODE_DYNAMIC; |
| 1007 | else |
| 1008 | rfMode |= AR_PHY_MODE_OFDM; |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1009 | |
Felix Fietkau | 6b42e8d | 2010-04-26 15:04:35 -0400 | [diff] [blame] | 1010 | if (IS_CHAN_A_FAST_CLOCK(ah, chan)) |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1011 | rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE); |
| 1012 | |
Helmut Schaa | 41842dc | 2016-04-29 15:06:34 +0200 | [diff] [blame] | 1013 | if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan)) |
Felix Fietkau | 3e61d3f | 2012-04-19 21:18:25 +0200 | [diff] [blame] | 1014 | REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, |
| 1015 | AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3); |
| 1016 | |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1017 | REG_WRITE(ah, AR_PHY_MODE, rfMode); |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 1018 | } |
| 1019 | |
| 1020 | static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah) |
| 1021 | { |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1022 | REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 1023 | } |
| 1024 | |
| 1025 | static void ar9003_hw_set_delta_slope(struct ath_hw *ah, |
| 1026 | struct ath9k_channel *chan) |
| 1027 | { |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1028 | u32 coef_scaled, ds_coef_exp, ds_coef_man; |
| 1029 | u32 clockMhzScaled = 0x64000000; |
| 1030 | struct chan_centers centers; |
| 1031 | |
| 1032 | /* |
| 1033 | * half and quarter rate can divide the scaled clock by 2 or 4 |
| 1034 | * scale for selected channel bandwidth |
| 1035 | */ |
| 1036 | if (IS_CHAN_HALF_RATE(chan)) |
| 1037 | clockMhzScaled = clockMhzScaled >> 1; |
| 1038 | else if (IS_CHAN_QUARTER_RATE(chan)) |
| 1039 | clockMhzScaled = clockMhzScaled >> 2; |
| 1040 | |
| 1041 | /* |
| 1042 | * ALGO -> coef = 1e8/fcarrier*fclock/40; |
| 1043 | * scaled coef to provide precision for this floating calculation |
| 1044 | */ |
| 1045 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); |
| 1046 | coef_scaled = clockMhzScaled / centers.synth_center; |
| 1047 | |
| 1048 | ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, |
| 1049 | &ds_coef_exp); |
| 1050 | |
| 1051 | REG_RMW_FIELD(ah, AR_PHY_TIMING3, |
| 1052 | AR_PHY_TIMING3_DSC_MAN, ds_coef_man); |
| 1053 | REG_RMW_FIELD(ah, AR_PHY_TIMING3, |
| 1054 | AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); |
| 1055 | |
| 1056 | /* |
| 1057 | * For Short GI, |
| 1058 | * scaled coeff is 9/10 that of normal coeff |
| 1059 | */ |
| 1060 | coef_scaled = (9 * coef_scaled) / 10; |
| 1061 | |
| 1062 | ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, |
| 1063 | &ds_coef_exp); |
| 1064 | |
| 1065 | /* for short gi */ |
| 1066 | REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, |
| 1067 | AR_PHY_SGI_DSC_MAN, ds_coef_man); |
| 1068 | REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, |
| 1069 | AR_PHY_SGI_DSC_EXP, ds_coef_exp); |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 1070 | } |
| 1071 | |
| 1072 | static bool ar9003_hw_rfbus_req(struct ath_hw *ah) |
| 1073 | { |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1074 | REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); |
| 1075 | return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, |
| 1076 | AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT); |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 1077 | } |
| 1078 | |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1079 | /* |
| 1080 | * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN). |
| 1081 | * Read the phy active delay register. Value is in 100ns increments. |
| 1082 | */ |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 1083 | static void ar9003_hw_rfbus_done(struct ath_hw *ah) |
| 1084 | { |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1085 | u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1086 | |
Felix Fietkau | 7c5adc8 | 2012-04-19 21:18:26 +0200 | [diff] [blame] | 1087 | ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1088 | |
| 1089 | REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 1090 | } |
| 1091 | |
Felix Fietkau | c16fcb4 | 2010-04-15 17:38:39 -0400 | [diff] [blame] | 1092 | static bool ar9003_hw_ani_control(struct ath_hw *ah, |
| 1093 | enum ath9k_ani_cmd cmd, int param) |
| 1094 | { |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1095 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1096 | struct ath9k_channel *chan = ah->curchan; |
Sujith Manoharan | c24bd36 | 2013-06-03 09:19:29 +0530 | [diff] [blame] | 1097 | struct ar5416AniState *aniState = &ah->ani; |
Sujith Manoharan | ff23e08 | 2013-06-04 15:41:33 +0530 | [diff] [blame] | 1098 | int m1ThreshLow, m2ThreshLow; |
| 1099 | int m1Thresh, m2Thresh; |
| 1100 | int m2CountThr, m2CountThrLow; |
| 1101 | int m1ThreshLowExt, m2ThreshLowExt; |
| 1102 | int m1ThreshExt, m2ThreshExt; |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1103 | s32 value, value2; |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1104 | |
| 1105 | switch (cmd & ah->ani_function) { |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1106 | case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{ |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1107 | /* |
| 1108 | * on == 1 means ofdm weak signal detection is ON |
| 1109 | * on == 1 is the default, for less noise immunity |
| 1110 | * |
| 1111 | * on == 0 means ofdm weak signal detection is OFF |
| 1112 | * on == 0 means more noise imm |
| 1113 | */ |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1114 | u32 on = param ? 1 : 0; |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1115 | |
Sujith Manoharan | ff23e08 | 2013-06-04 15:41:33 +0530 | [diff] [blame] | 1116 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) |
| 1117 | goto skip_ws_det; |
| 1118 | |
| 1119 | m1ThreshLow = on ? |
| 1120 | aniState->iniDef.m1ThreshLow : m1ThreshLow_off; |
| 1121 | m2ThreshLow = on ? |
| 1122 | aniState->iniDef.m2ThreshLow : m2ThreshLow_off; |
| 1123 | m1Thresh = on ? |
| 1124 | aniState->iniDef.m1Thresh : m1Thresh_off; |
| 1125 | m2Thresh = on ? |
| 1126 | aniState->iniDef.m2Thresh : m2Thresh_off; |
| 1127 | m2CountThr = on ? |
| 1128 | aniState->iniDef.m2CountThr : m2CountThr_off; |
| 1129 | m2CountThrLow = on ? |
| 1130 | aniState->iniDef.m2CountThrLow : m2CountThrLow_off; |
| 1131 | m1ThreshLowExt = on ? |
| 1132 | aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off; |
| 1133 | m2ThreshLowExt = on ? |
| 1134 | aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off; |
| 1135 | m1ThreshExt = on ? |
| 1136 | aniState->iniDef.m1ThreshExt : m1ThreshExt_off; |
| 1137 | m2ThreshExt = on ? |
| 1138 | aniState->iniDef.m2ThreshExt : m2ThreshExt_off; |
| 1139 | |
| 1140 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, |
| 1141 | AR_PHY_SFCORR_LOW_M1_THRESH_LOW, |
| 1142 | m1ThreshLow); |
| 1143 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, |
| 1144 | AR_PHY_SFCORR_LOW_M2_THRESH_LOW, |
| 1145 | m2ThreshLow); |
| 1146 | REG_RMW_FIELD(ah, AR_PHY_SFCORR, |
| 1147 | AR_PHY_SFCORR_M1_THRESH, |
| 1148 | m1Thresh); |
| 1149 | REG_RMW_FIELD(ah, AR_PHY_SFCORR, |
| 1150 | AR_PHY_SFCORR_M2_THRESH, |
| 1151 | m2Thresh); |
| 1152 | REG_RMW_FIELD(ah, AR_PHY_SFCORR, |
| 1153 | AR_PHY_SFCORR_M2COUNT_THR, |
| 1154 | m2CountThr); |
| 1155 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW, |
| 1156 | AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, |
| 1157 | m2CountThrLow); |
| 1158 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, |
| 1159 | AR_PHY_SFCORR_EXT_M1_THRESH_LOW, |
| 1160 | m1ThreshLowExt); |
| 1161 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, |
| 1162 | AR_PHY_SFCORR_EXT_M2_THRESH_LOW, |
| 1163 | m2ThreshLowExt); |
| 1164 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, |
| 1165 | AR_PHY_SFCORR_EXT_M1_THRESH, |
| 1166 | m1ThreshExt); |
| 1167 | REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT, |
| 1168 | AR_PHY_SFCORR_EXT_M2_THRESH, |
| 1169 | m2ThreshExt); |
| 1170 | skip_ws_det: |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1171 | if (on) |
| 1172 | REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, |
| 1173 | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); |
| 1174 | else |
| 1175 | REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW, |
| 1176 | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW); |
| 1177 | |
Felix Fietkau | 7067e70 | 2012-06-15 15:25:21 +0200 | [diff] [blame] | 1178 | if (on != aniState->ofdmWeakSigDetect) { |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 1179 | ath_dbg(common, ANI, |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1180 | "** ch %d: ofdm weak signal: %s=>%s\n", |
| 1181 | chan->channel, |
Felix Fietkau | 7067e70 | 2012-06-15 15:25:21 +0200 | [diff] [blame] | 1182 | aniState->ofdmWeakSigDetect ? |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1183 | "on" : "off", |
| 1184 | on ? "on" : "off"); |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1185 | if (on) |
| 1186 | ah->stats.ast_ani_ofdmon++; |
| 1187 | else |
| 1188 | ah->stats.ast_ani_ofdmoff++; |
Felix Fietkau | 7067e70 | 2012-06-15 15:25:21 +0200 | [diff] [blame] | 1189 | aniState->ofdmWeakSigDetect = on; |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1190 | } |
| 1191 | break; |
| 1192 | } |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1193 | case ATH9K_ANI_FIRSTEP_LEVEL:{ |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1194 | u32 level = param; |
| 1195 | |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1196 | if (level >= ARRAY_SIZE(firstep_table)) { |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 1197 | ath_dbg(common, ANI, |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1198 | "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n", |
| 1199 | level, ARRAY_SIZE(firstep_table)); |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1200 | return false; |
| 1201 | } |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1202 | |
| 1203 | /* |
| 1204 | * make register setting relative to default |
| 1205 | * from INI file & cap value |
| 1206 | */ |
| 1207 | value = firstep_table[level] - |
Felix Fietkau | 465dce6 | 2012-06-15 15:25:24 +0200 | [diff] [blame] | 1208 | firstep_table[ATH9K_ANI_FIRSTEP_LVL] + |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1209 | aniState->iniDef.firstep; |
| 1210 | if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN) |
| 1211 | value = ATH9K_SIG_FIRSTEP_SETTING_MIN; |
| 1212 | if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX) |
| 1213 | value = ATH9K_SIG_FIRSTEP_SETTING_MAX; |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1214 | REG_RMW_FIELD(ah, AR_PHY_FIND_SIG, |
| 1215 | AR_PHY_FIND_SIG_FIRSTEP, |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1216 | value); |
| 1217 | /* |
| 1218 | * we need to set first step low register too |
| 1219 | * make register setting relative to default |
| 1220 | * from INI file & cap value |
| 1221 | */ |
| 1222 | value2 = firstep_table[level] - |
Felix Fietkau | 465dce6 | 2012-06-15 15:25:24 +0200 | [diff] [blame] | 1223 | firstep_table[ATH9K_ANI_FIRSTEP_LVL] + |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1224 | aniState->iniDef.firstepLow; |
| 1225 | if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN) |
| 1226 | value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN; |
| 1227 | if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX) |
| 1228 | value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX; |
| 1229 | |
| 1230 | REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW, |
| 1231 | AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2); |
| 1232 | |
| 1233 | if (level != aniState->firstepLevel) { |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 1234 | ath_dbg(common, ANI, |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1235 | "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n", |
| 1236 | chan->channel, |
| 1237 | aniState->firstepLevel, |
| 1238 | level, |
Felix Fietkau | 465dce6 | 2012-06-15 15:25:24 +0200 | [diff] [blame] | 1239 | ATH9K_ANI_FIRSTEP_LVL, |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1240 | value, |
| 1241 | aniState->iniDef.firstep); |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 1242 | ath_dbg(common, ANI, |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1243 | "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n", |
| 1244 | chan->channel, |
| 1245 | aniState->firstepLevel, |
| 1246 | level, |
Felix Fietkau | 465dce6 | 2012-06-15 15:25:24 +0200 | [diff] [blame] | 1247 | ATH9K_ANI_FIRSTEP_LVL, |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1248 | value2, |
| 1249 | aniState->iniDef.firstepLow); |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1250 | if (level > aniState->firstepLevel) |
| 1251 | ah->stats.ast_ani_stepup++; |
| 1252 | else if (level < aniState->firstepLevel) |
| 1253 | ah->stats.ast_ani_stepdown++; |
| 1254 | aniState->firstepLevel = level; |
| 1255 | } |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1256 | break; |
| 1257 | } |
| 1258 | case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{ |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1259 | u32 level = param; |
| 1260 | |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1261 | if (level >= ARRAY_SIZE(cycpwrThr1_table)) { |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 1262 | ath_dbg(common, ANI, |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1263 | "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n", |
| 1264 | level, ARRAY_SIZE(cycpwrThr1_table)); |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1265 | return false; |
| 1266 | } |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1267 | /* |
| 1268 | * make register setting relative to default |
| 1269 | * from INI file & cap value |
| 1270 | */ |
| 1271 | value = cycpwrThr1_table[level] - |
Felix Fietkau | 465dce6 | 2012-06-15 15:25:24 +0200 | [diff] [blame] | 1272 | cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] + |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1273 | aniState->iniDef.cycpwrThr1; |
| 1274 | if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN) |
| 1275 | value = ATH9K_SIG_SPUR_IMM_SETTING_MIN; |
| 1276 | if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX) |
| 1277 | value = ATH9K_SIG_SPUR_IMM_SETTING_MAX; |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1278 | REG_RMW_FIELD(ah, AR_PHY_TIMING5, |
| 1279 | AR_PHY_TIMING5_CYCPWR_THR1, |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1280 | value); |
| 1281 | |
| 1282 | /* |
| 1283 | * set AR_PHY_EXT_CCA for extension channel |
| 1284 | * make register setting relative to default |
| 1285 | * from INI file & cap value |
| 1286 | */ |
| 1287 | value2 = cycpwrThr1_table[level] - |
Felix Fietkau | 465dce6 | 2012-06-15 15:25:24 +0200 | [diff] [blame] | 1288 | cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] + |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1289 | aniState->iniDef.cycpwrThr1Ext; |
| 1290 | if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN) |
| 1291 | value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN; |
| 1292 | if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX) |
| 1293 | value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX; |
| 1294 | REG_RMW_FIELD(ah, AR_PHY_EXT_CCA, |
| 1295 | AR_PHY_EXT_CYCPWR_THR1, value2); |
| 1296 | |
| 1297 | if (level != aniState->spurImmunityLevel) { |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 1298 | ath_dbg(common, ANI, |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1299 | "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n", |
| 1300 | chan->channel, |
| 1301 | aniState->spurImmunityLevel, |
| 1302 | level, |
Felix Fietkau | 465dce6 | 2012-06-15 15:25:24 +0200 | [diff] [blame] | 1303 | ATH9K_ANI_SPUR_IMMUNE_LVL, |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1304 | value, |
| 1305 | aniState->iniDef.cycpwrThr1); |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 1306 | ath_dbg(common, ANI, |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1307 | "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n", |
| 1308 | chan->channel, |
| 1309 | aniState->spurImmunityLevel, |
| 1310 | level, |
Felix Fietkau | 465dce6 | 2012-06-15 15:25:24 +0200 | [diff] [blame] | 1311 | ATH9K_ANI_SPUR_IMMUNE_LVL, |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1312 | value2, |
| 1313 | aniState->iniDef.cycpwrThr1Ext); |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1314 | if (level > aniState->spurImmunityLevel) |
| 1315 | ah->stats.ast_ani_spurup++; |
| 1316 | else if (level < aniState->spurImmunityLevel) |
| 1317 | ah->stats.ast_ani_spurdown++; |
| 1318 | aniState->spurImmunityLevel = level; |
| 1319 | } |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1320 | break; |
| 1321 | } |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1322 | case ATH9K_ANI_MRC_CCK:{ |
| 1323 | /* |
| 1324 | * is_on == 1 means MRC CCK ON (default, less noise imm) |
| 1325 | * is_on == 0 means MRC CCK is OFF (more noise imm) |
| 1326 | */ |
| 1327 | bool is_on = param ? 1 : 0; |
Felix Fietkau | a1c781b | 2013-08-13 12:33:28 +0200 | [diff] [blame] | 1328 | |
| 1329 | if (ah->caps.rx_chainmask == 1) |
| 1330 | break; |
| 1331 | |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1332 | REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, |
| 1333 | AR_PHY_MRC_CCK_ENABLE, is_on); |
| 1334 | REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL, |
| 1335 | AR_PHY_MRC_CCK_MUX_REG, is_on); |
Rajkumar Manoharan | 81b67fd6 | 2012-06-21 20:33:59 +0530 | [diff] [blame] | 1336 | if (is_on != aniState->mrcCCK) { |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 1337 | ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n", |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1338 | chan->channel, |
Rajkumar Manoharan | 81b67fd6 | 2012-06-21 20:33:59 +0530 | [diff] [blame] | 1339 | aniState->mrcCCK ? "on" : "off", |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1340 | is_on ? "on" : "off"); |
Bob Copeland | 1451a36 | 2016-02-28 20:07:56 -0500 | [diff] [blame] | 1341 | if (is_on) |
| 1342 | ah->stats.ast_ani_ccklow++; |
| 1343 | else |
| 1344 | ah->stats.ast_ani_cckhigh++; |
| 1345 | aniState->mrcCCK = is_on; |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1346 | } |
| 1347 | break; |
| 1348 | } |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1349 | default: |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 1350 | ath_dbg(common, ANI, "invalid cmd %u\n", cmd); |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1351 | return false; |
| 1352 | } |
| 1353 | |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 1354 | ath_dbg(common, ANI, |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1355 | "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n", |
| 1356 | aniState->spurImmunityLevel, |
Felix Fietkau | 7067e70 | 2012-06-15 15:25:21 +0200 | [diff] [blame] | 1357 | aniState->ofdmWeakSigDetect ? "on" : "off", |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1358 | aniState->firstepLevel, |
Rajkumar Manoharan | 81b67fd6 | 2012-06-21 20:33:59 +0530 | [diff] [blame] | 1359 | aniState->mrcCCK ? "on" : "off", |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1360 | aniState->listenTime, |
| 1361 | aniState->ofdmPhyErrCount, |
| 1362 | aniState->cckPhyErrCount); |
Luis R. Rodriguez | af914a9 | 2010-04-15 17:38:40 -0400 | [diff] [blame] | 1363 | return true; |
Felix Fietkau | c16fcb4 | 2010-04-15 17:38:39 -0400 | [diff] [blame] | 1364 | } |
| 1365 | |
Felix Fietkau | 641d992 | 2010-04-15 17:38:49 -0400 | [diff] [blame] | 1366 | static void ar9003_hw_do_getnf(struct ath_hw *ah, |
| 1367 | int16_t nfarray[NUM_NF_READINGS]) |
| 1368 | { |
Vasanthakumar Thiagarajan | b06af7a | 2011-03-01 08:59:36 -0800 | [diff] [blame] | 1369 | #define AR_PHY_CH_MINCCA_PWR 0x1FF00000 |
| 1370 | #define AR_PHY_CH_MINCCA_PWR_S 20 |
| 1371 | #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000 |
| 1372 | #define AR_PHY_CH_EXT_MINCCA_PWR_S 16 |
| 1373 | |
Felix Fietkau | 641d992 | 2010-04-15 17:38:49 -0400 | [diff] [blame] | 1374 | int16_t nf; |
Vasanthakumar Thiagarajan | b06af7a | 2011-03-01 08:59:36 -0800 | [diff] [blame] | 1375 | int i; |
Felix Fietkau | 641d992 | 2010-04-15 17:38:49 -0400 | [diff] [blame] | 1376 | |
Vasanthakumar Thiagarajan | b06af7a | 2011-03-01 08:59:36 -0800 | [diff] [blame] | 1377 | for (i = 0; i < AR9300_MAX_CHAINS; i++) { |
| 1378 | if (ah->rxchainmask & BIT(i)) { |
| 1379 | nf = MS(REG_READ(ah, ah->nf_regs[i]), |
| 1380 | AR_PHY_CH_MINCCA_PWR); |
| 1381 | nfarray[i] = sign_extend32(nf, 8); |
Felix Fietkau | 641d992 | 2010-04-15 17:38:49 -0400 | [diff] [blame] | 1382 | |
Vasanthakumar Thiagarajan | b06af7a | 2011-03-01 08:59:36 -0800 | [diff] [blame] | 1383 | if (IS_CHAN_HT40(ah->curchan)) { |
| 1384 | u8 ext_idx = AR9300_MAX_CHAINS + i; |
Felix Fietkau | 641d992 | 2010-04-15 17:38:49 -0400 | [diff] [blame] | 1385 | |
Vasanthakumar Thiagarajan | b06af7a | 2011-03-01 08:59:36 -0800 | [diff] [blame] | 1386 | nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]), |
| 1387 | AR_PHY_CH_EXT_MINCCA_PWR); |
| 1388 | nfarray[ext_idx] = sign_extend32(nf, 8); |
| 1389 | } |
| 1390 | } |
| 1391 | } |
Felix Fietkau | 641d992 | 2010-04-15 17:38:49 -0400 | [diff] [blame] | 1392 | } |
| 1393 | |
Felix Fietkau | f2552e2 | 2010-07-02 00:09:50 +0200 | [diff] [blame] | 1394 | static void ar9003_hw_set_nf_limits(struct ath_hw *ah) |
Felix Fietkau | 641d992 | 2010-04-15 17:38:49 -0400 | [diff] [blame] | 1395 | { |
Felix Fietkau | f2552e2 | 2010-07-02 00:09:50 +0200 | [diff] [blame] | 1396 | ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ; |
| 1397 | ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ; |
Sujith Manoharan | ae245cd | 2012-02-16 11:52:44 +0530 | [diff] [blame] | 1398 | ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ; |
Felix Fietkau | f2552e2 | 2010-07-02 00:09:50 +0200 | [diff] [blame] | 1399 | ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ; |
| 1400 | ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ; |
| 1401 | ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ; |
Sujith Manoharan | ae245cd | 2012-02-16 11:52:44 +0530 | [diff] [blame] | 1402 | |
| 1403 | if (AR_SREV_9330(ah)) |
| 1404 | ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ; |
| 1405 | |
Sujith Manoharan | a4a2954 | 2012-09-10 09:20:03 +0530 | [diff] [blame] | 1406 | if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { |
Sujith Manoharan | ae245cd | 2012-02-16 11:52:44 +0530 | [diff] [blame] | 1407 | ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ; |
| 1408 | ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ; |
| 1409 | ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ; |
| 1410 | ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ; |
| 1411 | } |
Felix Fietkau | 641d992 | 2010-04-15 17:38:49 -0400 | [diff] [blame] | 1412 | } |
| 1413 | |
Luis R. Rodriguez | df23aca | 2010-04-15 17:39:11 -0400 | [diff] [blame] | 1414 | /* |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1415 | * Initialize the ANI register values with default (ini) values. |
| 1416 | * This routine is called during a (full) hardware reset after |
| 1417 | * all the registers are initialised from the INI. |
| 1418 | */ |
| 1419 | static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah) |
| 1420 | { |
| 1421 | struct ar5416AniState *aniState; |
| 1422 | struct ath_common *common = ath9k_hw_common(ah); |
| 1423 | struct ath9k_channel *chan = ah->curchan; |
| 1424 | struct ath9k_ani_default *iniDef; |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1425 | u32 val; |
| 1426 | |
Sujith Manoharan | c24bd36 | 2013-06-03 09:19:29 +0530 | [diff] [blame] | 1427 | aniState = &ah->ani; |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1428 | iniDef = &aniState->iniDef; |
| 1429 | |
Felix Fietkau | 8896934 | 2013-10-11 23:30:53 +0200 | [diff] [blame] | 1430 | ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n", |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 1431 | ah->hw_version.macVersion, |
| 1432 | ah->hw_version.macRev, |
| 1433 | ah->opmode, |
Felix Fietkau | 8896934 | 2013-10-11 23:30:53 +0200 | [diff] [blame] | 1434 | chan->channel); |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1435 | |
| 1436 | val = REG_READ(ah, AR_PHY_SFCORR); |
| 1437 | iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); |
| 1438 | iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); |
| 1439 | iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); |
| 1440 | |
| 1441 | val = REG_READ(ah, AR_PHY_SFCORR_LOW); |
| 1442 | iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); |
| 1443 | iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); |
| 1444 | iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); |
| 1445 | |
| 1446 | val = REG_READ(ah, AR_PHY_SFCORR_EXT); |
| 1447 | iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); |
| 1448 | iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); |
| 1449 | iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); |
| 1450 | iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); |
| 1451 | iniDef->firstep = REG_READ_FIELD(ah, |
| 1452 | AR_PHY_FIND_SIG, |
| 1453 | AR_PHY_FIND_SIG_FIRSTEP); |
| 1454 | iniDef->firstepLow = REG_READ_FIELD(ah, |
| 1455 | AR_PHY_FIND_SIG_LOW, |
| 1456 | AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW); |
| 1457 | iniDef->cycpwrThr1 = REG_READ_FIELD(ah, |
| 1458 | AR_PHY_TIMING5, |
| 1459 | AR_PHY_TIMING5_CYCPWR_THR1); |
| 1460 | iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, |
| 1461 | AR_PHY_EXT_CCA, |
| 1462 | AR_PHY_EXT_CYCPWR_THR1); |
| 1463 | |
| 1464 | /* these levels just got reset to defaults by the INI */ |
Felix Fietkau | 465dce6 | 2012-06-15 15:25:24 +0200 | [diff] [blame] | 1465 | aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; |
| 1466 | aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL; |
Sujith Manoharan | 4f4395c | 2013-06-03 09:19:27 +0530 | [diff] [blame] | 1467 | aniState->ofdmWeakSigDetect = true; |
Rajkumar Manoharan | 81b67fd6 | 2012-06-21 20:33:59 +0530 | [diff] [blame] | 1468 | aniState->mrcCCK = true; |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1469 | } |
| 1470 | |
Felix Fietkau | 4e8c14e | 2010-11-11 03:18:38 +0100 | [diff] [blame] | 1471 | static void ar9003_hw_set_radar_params(struct ath_hw *ah, |
| 1472 | struct ath_hw_radar_conf *conf) |
| 1473 | { |
Sujith Manoharan | 4a878b9 | 2013-12-06 16:28:40 +0530 | [diff] [blame] | 1474 | unsigned int regWrites = 0; |
Lorenzo Bianconi | 992a36a | 2014-10-14 22:21:00 +0200 | [diff] [blame] | 1475 | u32 radar_0 = 0, radar_1; |
Felix Fietkau | 4e8c14e | 2010-11-11 03:18:38 +0100 | [diff] [blame] | 1476 | |
| 1477 | if (!conf) { |
| 1478 | REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA); |
| 1479 | return; |
| 1480 | } |
| 1481 | |
| 1482 | radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA; |
| 1483 | radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); |
| 1484 | radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); |
| 1485 | radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); |
| 1486 | radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); |
| 1487 | radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); |
| 1488 | |
Lorenzo Bianconi | 992a36a | 2014-10-14 22:21:00 +0200 | [diff] [blame] | 1489 | radar_1 = REG_READ(ah, AR_PHY_RADAR_1); |
| 1490 | radar_1 &= ~(AR_PHY_RADAR_1_MAXLEN | AR_PHY_RADAR_1_RELSTEP_THRESH | |
| 1491 | AR_PHY_RADAR_1_RELPWR_THRESH); |
Felix Fietkau | 4e8c14e | 2010-11-11 03:18:38 +0100 | [diff] [blame] | 1492 | radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI; |
| 1493 | radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK; |
| 1494 | radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); |
| 1495 | radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH); |
| 1496 | radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH); |
| 1497 | |
| 1498 | REG_WRITE(ah, AR_PHY_RADAR_0, radar_0); |
| 1499 | REG_WRITE(ah, AR_PHY_RADAR_1, radar_1); |
| 1500 | if (conf->ext_channel) |
| 1501 | REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); |
| 1502 | else |
| 1503 | REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); |
Sujith Manoharan | 4a878b9 | 2013-12-06 16:28:40 +0530 | [diff] [blame] | 1504 | |
| 1505 | if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) { |
| 1506 | REG_WRITE_ARRAY(&ah->ini_dfs, |
| 1507 | IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites); |
| 1508 | } |
Felix Fietkau | 4e8c14e | 2010-11-11 03:18:38 +0100 | [diff] [blame] | 1509 | } |
| 1510 | |
Felix Fietkau | c5d0855 | 2010-11-13 20:22:41 +0100 | [diff] [blame] | 1511 | static void ar9003_hw_set_radar_conf(struct ath_hw *ah) |
| 1512 | { |
| 1513 | struct ath_hw_radar_conf *conf = &ah->radar_conf; |
| 1514 | |
| 1515 | conf->fir_power = -28; |
| 1516 | conf->radar_rssi = 0; |
| 1517 | conf->pulse_height = 10; |
Lorenzo Bianconi | edad187 | 2014-10-28 12:37:16 +0100 | [diff] [blame] | 1518 | conf->pulse_rssi = 15; |
Felix Fietkau | c5d0855 | 2010-11-13 20:22:41 +0100 | [diff] [blame] | 1519 | conf->pulse_inband = 8; |
| 1520 | conf->pulse_maxlen = 255; |
| 1521 | conf->pulse_inband_step = 12; |
| 1522 | conf->radar_inband = 8; |
| 1523 | } |
| 1524 | |
Mohammed Shafi Shajakhan | 6bcbc06 | 2011-05-13 20:30:41 +0530 | [diff] [blame] | 1525 | static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah, |
Sujith Manoharan | 9aa49ea | 2012-09-11 10:46:38 +0530 | [diff] [blame] | 1526 | struct ath_hw_antcomb_conf *antconf) |
Mohammed Shafi Shajakhan | 6bcbc06 | 2011-05-13 20:30:41 +0530 | [diff] [blame] | 1527 | { |
| 1528 | u32 regval; |
| 1529 | |
| 1530 | regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); |
Sujith Manoharan | 9aa49ea | 2012-09-11 10:46:38 +0530 | [diff] [blame] | 1531 | antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >> |
| 1532 | AR_PHY_ANT_DIV_MAIN_LNACONF_S; |
| 1533 | antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >> |
| 1534 | AR_PHY_ANT_DIV_ALT_LNACONF_S; |
| 1535 | antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >> |
| 1536 | AR_PHY_ANT_FAST_DIV_BIAS_S; |
Gabor Juhos | cd0ed1b | 2011-06-21 11:23:44 +0200 | [diff] [blame] | 1537 | |
Gabor Juhos | c4cf2c5 | 2011-06-21 11:23:47 +0200 | [diff] [blame] | 1538 | if (AR_SREV_9330_11(ah)) { |
Sujith Manoharan | f96bd2a | 2013-09-02 13:59:03 +0530 | [diff] [blame] | 1539 | antconf->lna1_lna2_switch_delta = -1; |
Gabor Juhos | c4cf2c5 | 2011-06-21 11:23:47 +0200 | [diff] [blame] | 1540 | antconf->lna1_lna2_delta = -9; |
| 1541 | antconf->div_group = 1; |
| 1542 | } else if (AR_SREV_9485(ah)) { |
Sujith Manoharan | f96bd2a | 2013-09-02 13:59:03 +0530 | [diff] [blame] | 1543 | antconf->lna1_lna2_switch_delta = -1; |
Gabor Juhos | cd0ed1b | 2011-06-21 11:23:44 +0200 | [diff] [blame] | 1544 | antconf->lna1_lna2_delta = -9; |
| 1545 | antconf->div_group = 2; |
Sujith Manoharan | 5317c9c | 2012-09-16 08:06:08 +0530 | [diff] [blame] | 1546 | } else if (AR_SREV_9565(ah)) { |
Sujith Manoharan | f96bd2a | 2013-09-02 13:59:03 +0530 | [diff] [blame] | 1547 | antconf->lna1_lna2_switch_delta = 3; |
| 1548 | antconf->lna1_lna2_delta = -9; |
Sujith Manoharan | 5317c9c | 2012-09-16 08:06:08 +0530 | [diff] [blame] | 1549 | antconf->div_group = 3; |
Gabor Juhos | cd0ed1b | 2011-06-21 11:23:44 +0200 | [diff] [blame] | 1550 | } else { |
Sujith Manoharan | f96bd2a | 2013-09-02 13:59:03 +0530 | [diff] [blame] | 1551 | antconf->lna1_lna2_switch_delta = -1; |
Gabor Juhos | cd0ed1b | 2011-06-21 11:23:44 +0200 | [diff] [blame] | 1552 | antconf->lna1_lna2_delta = -3; |
| 1553 | antconf->div_group = 0; |
| 1554 | } |
Mohammed Shafi Shajakhan | 6bcbc06 | 2011-05-13 20:30:41 +0530 | [diff] [blame] | 1555 | } |
| 1556 | |
| 1557 | static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah, |
| 1558 | struct ath_hw_antcomb_conf *antconf) |
| 1559 | { |
| 1560 | u32 regval; |
| 1561 | |
| 1562 | regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); |
Sujith Manoharan | 9aa49ea | 2012-09-11 10:46:38 +0530 | [diff] [blame] | 1563 | regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF | |
| 1564 | AR_PHY_ANT_DIV_ALT_LNACONF | |
| 1565 | AR_PHY_ANT_FAST_DIV_BIAS | |
| 1566 | AR_PHY_ANT_DIV_MAIN_GAINTB | |
| 1567 | AR_PHY_ANT_DIV_ALT_GAINTB); |
| 1568 | regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S) |
| 1569 | & AR_PHY_ANT_DIV_MAIN_LNACONF); |
| 1570 | regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S) |
| 1571 | & AR_PHY_ANT_DIV_ALT_LNACONF); |
| 1572 | regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S) |
| 1573 | & AR_PHY_ANT_FAST_DIV_BIAS); |
| 1574 | regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S) |
| 1575 | & AR_PHY_ANT_DIV_MAIN_GAINTB); |
| 1576 | regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S) |
| 1577 | & AR_PHY_ANT_DIV_ALT_GAINTB); |
Mohammed Shafi Shajakhan | 6bcbc06 | 2011-05-13 20:30:41 +0530 | [diff] [blame] | 1578 | |
| 1579 | REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); |
| 1580 | } |
| 1581 | |
Sujith Manoharan | 36e8825 | 2013-08-06 12:44:15 +0530 | [diff] [blame] | 1582 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
| 1583 | |
Sujith Manoharan | d8d7744 | 2013-08-04 14:21:57 +0530 | [diff] [blame] | 1584 | static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable) |
Sujith Manoharan | 362cd03 | 2012-09-16 08:06:36 +0530 | [diff] [blame] | 1585 | { |
Sujith Manoharan | 8489381 | 2013-08-04 14:22:02 +0530 | [diff] [blame] | 1586 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Sujith Manoharan | 362cd03 | 2012-09-16 08:06:36 +0530 | [diff] [blame] | 1587 | u8 ant_div_ctl1; |
| 1588 | u32 regval; |
| 1589 | |
Sujith Manoharan | 8489381 | 2013-08-04 14:22:02 +0530 | [diff] [blame] | 1590 | if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah)) |
Sujith Manoharan | 362cd03 | 2012-09-16 08:06:36 +0530 | [diff] [blame] | 1591 | return; |
| 1592 | |
Sujith Manoharan | 8489381 | 2013-08-04 14:22:02 +0530 | [diff] [blame] | 1593 | if (AR_SREV_9485(ah)) { |
| 1594 | regval = ar9003_hw_ant_ctrl_common_2_get(ah, |
| 1595 | IS_CHAN_2GHZ(ah->curchan)); |
| 1596 | if (enable) { |
| 1597 | regval &= ~AR_SWITCH_TABLE_COM2_ALL; |
| 1598 | regval |= ah->config.ant_ctrl_comm2g_switch_enable; |
| 1599 | } |
| 1600 | REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, |
| 1601 | AR_SWITCH_TABLE_COM2_ALL, regval); |
| 1602 | } |
| 1603 | |
Sujith Manoharan | 362cd03 | 2012-09-16 08:06:36 +0530 | [diff] [blame] | 1604 | ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); |
| 1605 | |
Sujith Manoharan | 8489381 | 2013-08-04 14:22:02 +0530 | [diff] [blame] | 1606 | /* |
| 1607 | * Set MAIN/ALT LNA conf. |
| 1608 | * Set MAIN/ALT gain_tb. |
| 1609 | */ |
Sujith Manoharan | 362cd03 | 2012-09-16 08:06:36 +0530 | [diff] [blame] | 1610 | regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); |
| 1611 | regval &= (~AR_ANT_DIV_CTRL_ALL); |
| 1612 | regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S; |
Sujith Manoharan | 362cd03 | 2012-09-16 08:06:36 +0530 | [diff] [blame] | 1613 | REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); |
| 1614 | |
Sujith Manoharan | fb5a2dc | 2013-08-19 11:03:43 +0530 | [diff] [blame] | 1615 | if (AR_SREV_9485_11_OR_LATER(ah)) { |
Sujith Manoharan | 8489381 | 2013-08-04 14:22:02 +0530 | [diff] [blame] | 1616 | /* |
| 1617 | * Enable LNA diversity. |
| 1618 | */ |
Sujith Manoharan | 362cd03 | 2012-09-16 08:06:36 +0530 | [diff] [blame] | 1619 | regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); |
Sujith Manoharan | 8489381 | 2013-08-04 14:22:02 +0530 | [diff] [blame] | 1620 | regval &= ~AR_PHY_ANT_DIV_LNADIV; |
| 1621 | regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S; |
| 1622 | if (enable) |
| 1623 | regval |= AR_ANT_DIV_ENABLE; |
| 1624 | |
Sujith Manoharan | 362cd03 | 2012-09-16 08:06:36 +0530 | [diff] [blame] | 1625 | REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); |
Sujith Manoharan | 8489381 | 2013-08-04 14:22:02 +0530 | [diff] [blame] | 1626 | |
| 1627 | /* |
| 1628 | * Enable fast antenna diversity. |
| 1629 | */ |
| 1630 | regval = REG_READ(ah, AR_PHY_CCK_DETECT); |
| 1631 | regval &= ~AR_FAST_DIV_ENABLE; |
| 1632 | regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S; |
| 1633 | if (enable) |
| 1634 | regval |= AR_FAST_DIV_ENABLE; |
| 1635 | |
| 1636 | REG_WRITE(ah, AR_PHY_CCK_DETECT, regval); |
| 1637 | |
| 1638 | if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) { |
| 1639 | regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); |
| 1640 | regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF | |
| 1641 | AR_PHY_ANT_DIV_ALT_LNACONF | |
| 1642 | AR_PHY_ANT_DIV_ALT_GAINTB | |
| 1643 | AR_PHY_ANT_DIV_MAIN_GAINTB)); |
| 1644 | /* |
| 1645 | * Set MAIN to LNA1 and ALT to LNA2 at the |
| 1646 | * beginning. |
| 1647 | */ |
| 1648 | regval |= (ATH_ANT_DIV_COMB_LNA1 << |
| 1649 | AR_PHY_ANT_DIV_MAIN_LNACONF_S); |
| 1650 | regval |= (ATH_ANT_DIV_COMB_LNA2 << |
| 1651 | AR_PHY_ANT_DIV_ALT_LNACONF_S); |
| 1652 | REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); |
| 1653 | } |
| 1654 | } else if (AR_SREV_9565(ah)) { |
| 1655 | if (enable) { |
| 1656 | REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, |
Sujith Manoharan | c946868 | 2013-09-02 13:59:01 +0530 | [diff] [blame] | 1657 | AR_ANT_DIV_ENABLE); |
| 1658 | REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, |
Sujith Manoharan | 8489381 | 2013-08-04 14:22:02 +0530 | [diff] [blame] | 1659 | (1 << AR_PHY_ANT_SW_RX_PROT_S)); |
Sujith Manoharan | c946868 | 2013-09-02 13:59:01 +0530 | [diff] [blame] | 1660 | REG_SET_BIT(ah, AR_PHY_CCK_DETECT, |
| 1661 | AR_FAST_DIV_ENABLE); |
| 1662 | REG_SET_BIT(ah, AR_PHY_RESTART, |
| 1663 | AR_PHY_RESTART_ENABLE_DIV_M2FLAG); |
Sujith Manoharan | 8489381 | 2013-08-04 14:22:02 +0530 | [diff] [blame] | 1664 | REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, |
| 1665 | AR_BTCOEX_WL_LNADIV_FORCE_ON); |
| 1666 | } else { |
Sujith Manoharan | c946868 | 2013-09-02 13:59:01 +0530 | [diff] [blame] | 1667 | REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, |
| 1668 | AR_ANT_DIV_ENABLE); |
Sujith Manoharan | 8489381 | 2013-08-04 14:22:02 +0530 | [diff] [blame] | 1669 | REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, |
| 1670 | (1 << AR_PHY_ANT_SW_RX_PROT_S)); |
Sujith Manoharan | c946868 | 2013-09-02 13:59:01 +0530 | [diff] [blame] | 1671 | REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, |
| 1672 | AR_FAST_DIV_ENABLE); |
| 1673 | REG_CLR_BIT(ah, AR_PHY_RESTART, |
| 1674 | AR_PHY_RESTART_ENABLE_DIV_M2FLAG); |
Sujith Manoharan | 8489381 | 2013-08-04 14:22:02 +0530 | [diff] [blame] | 1675 | REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV, |
| 1676 | AR_BTCOEX_WL_LNADIV_FORCE_ON); |
| 1677 | |
| 1678 | regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); |
| 1679 | regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF | |
| 1680 | AR_PHY_ANT_DIV_ALT_LNACONF | |
| 1681 | AR_PHY_ANT_DIV_MAIN_GAINTB | |
| 1682 | AR_PHY_ANT_DIV_ALT_GAINTB); |
| 1683 | regval |= (ATH_ANT_DIV_COMB_LNA1 << |
| 1684 | AR_PHY_ANT_DIV_MAIN_LNACONF_S); |
| 1685 | regval |= (ATH_ANT_DIV_COMB_LNA2 << |
| 1686 | AR_PHY_ANT_DIV_ALT_LNACONF_S); |
| 1687 | REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval); |
| 1688 | } |
Sujith Manoharan | 362cd03 | 2012-09-16 08:06:36 +0530 | [diff] [blame] | 1689 | } |
| 1690 | } |
| 1691 | |
Sujith Manoharan | 36e8825 | 2013-08-06 12:44:15 +0530 | [diff] [blame] | 1692 | #endif |
| 1693 | |
Rajkumar Manoharan | 5f0c04e | 2011-10-13 11:00:35 +0530 | [diff] [blame] | 1694 | static int ar9003_hw_fast_chan_change(struct ath_hw *ah, |
| 1695 | struct ath9k_channel *chan, |
| 1696 | u8 *ini_reloaded) |
| 1697 | { |
| 1698 | unsigned int regWrites = 0; |
Rajkumar Manoharan | af2db44 | 2014-06-24 22:27:39 +0530 | [diff] [blame] | 1699 | u32 modesIndex, txgain_index; |
Rajkumar Manoharan | 5f0c04e | 2011-10-13 11:00:35 +0530 | [diff] [blame] | 1700 | |
Felix Fietkau | 8896934 | 2013-10-11 23:30:53 +0200 | [diff] [blame] | 1701 | if (IS_CHAN_5GHZ(chan)) |
| 1702 | modesIndex = IS_CHAN_HT40(chan) ? 2 : 1; |
| 1703 | else |
| 1704 | modesIndex = IS_CHAN_HT40(chan) ? 3 : 4; |
Rajkumar Manoharan | 5f0c04e | 2011-10-13 11:00:35 +0530 | [diff] [blame] | 1705 | |
Rajkumar Manoharan | af2db44 | 2014-06-24 22:27:39 +0530 | [diff] [blame] | 1706 | txgain_index = AR_SREV_9531(ah) ? 1 : modesIndex; |
| 1707 | |
Rajkumar Manoharan | 5f0c04e | 2011-10-13 11:00:35 +0530 | [diff] [blame] | 1708 | if (modesIndex == ah->modes_index) { |
| 1709 | *ini_reloaded = false; |
| 1710 | goto set_rfmode; |
| 1711 | } |
| 1712 | |
| 1713 | ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex); |
| 1714 | ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex); |
| 1715 | ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex); |
| 1716 | ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex); |
Sujith Manoharan | aaa53ee | 2012-09-10 09:19:54 +0530 | [diff] [blame] | 1717 | |
Sujith Manoharan | 2b5e54e | 2013-06-24 18:18:46 +0530 | [diff] [blame] | 1718 | if (AR_SREV_9462_20_OR_LATER(ah)) |
Sujith Manoharan | aaa53ee | 2012-09-10 09:19:54 +0530 | [diff] [blame] | 1719 | ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant, |
| 1720 | modesIndex); |
Rajkumar Manoharan | 5f0c04e | 2011-10-13 11:00:35 +0530 | [diff] [blame] | 1721 | |
Rajkumar Manoharan | af2db44 | 2014-06-24 22:27:39 +0530 | [diff] [blame] | 1722 | REG_WRITE_ARRAY(&ah->iniModesTxGain, txgain_index, regWrites); |
Rajkumar Manoharan | 5f0c04e | 2011-10-13 11:00:35 +0530 | [diff] [blame] | 1723 | |
Sujith Manoharan | 07a9bd2 | 2013-07-16 12:03:21 +0530 | [diff] [blame] | 1724 | if (AR_SREV_9462_20_OR_LATER(ah)) { |
| 1725 | /* |
| 1726 | * CUS217 mix LNA mode. |
| 1727 | */ |
| 1728 | if (ar9003_hw_get_rx_gain_idx(ah) == 2) { |
| 1729 | REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core, |
| 1730 | 1, regWrites); |
| 1731 | REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble, |
| 1732 | modesIndex, regWrites); |
| 1733 | } |
| 1734 | } |
| 1735 | |
Rajkumar Manoharan | 5f0c04e | 2011-10-13 11:00:35 +0530 | [diff] [blame] | 1736 | /* |
| 1737 | * For 5GHz channels requiring Fast Clock, apply |
| 1738 | * different modal values. |
| 1739 | */ |
| 1740 | if (IS_CHAN_A_FAST_CLOCK(ah, chan)) |
Felix Fietkau | c7d36f9 | 2012-03-14 16:40:31 +0100 | [diff] [blame] | 1741 | REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites); |
Rajkumar Manoharan | 5f0c04e | 2011-10-13 11:00:35 +0530 | [diff] [blame] | 1742 | |
Sujith Manoharan | aaa53ee | 2012-09-10 09:19:54 +0530 | [diff] [blame] | 1743 | if (AR_SREV_9565(ah)) |
| 1744 | REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites); |
| 1745 | |
Sujith Manoharan | 07a9bd2 | 2013-07-16 12:03:21 +0530 | [diff] [blame] | 1746 | /* |
| 1747 | * JAPAN regulatory. |
| 1748 | */ |
| 1749 | if (chan->channel == 2484) |
| 1750 | ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); |
Rajkumar Manoharan | 5f0c04e | 2011-10-13 11:00:35 +0530 | [diff] [blame] | 1751 | |
| 1752 | ah->modes_index = modesIndex; |
| 1753 | *ini_reloaded = true; |
| 1754 | |
| 1755 | set_rfmode: |
| 1756 | ar9003_hw_set_rfmode(ah, chan); |
| 1757 | return 0; |
| 1758 | } |
| 1759 | |
Simon Wunderlich | e93d083 | 2013-01-08 14:48:58 +0100 | [diff] [blame] | 1760 | static void ar9003_hw_spectral_scan_config(struct ath_hw *ah, |
| 1761 | struct ath_spec_scan *param) |
| 1762 | { |
| 1763 | u8 count; |
| 1764 | |
| 1765 | if (!param->enabled) { |
| 1766 | REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, |
| 1767 | AR_PHY_SPECTRAL_SCAN_ENABLE); |
| 1768 | return; |
| 1769 | } |
| 1770 | |
| 1771 | REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA); |
| 1772 | REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); |
| 1773 | |
| 1774 | /* on AR93xx and newer, count = 0 will make the the chip send |
| 1775 | * spectral samples endlessly. Check if this really was intended, |
| 1776 | * and fix otherwise. |
| 1777 | */ |
| 1778 | count = param->count; |
| 1779 | if (param->endless) |
| 1780 | count = 0; |
| 1781 | else if (param->count == 0) |
| 1782 | count = 1; |
| 1783 | |
| 1784 | if (param->short_repeat) |
| 1785 | REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, |
| 1786 | AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT); |
| 1787 | else |
| 1788 | REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN, |
| 1789 | AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT); |
| 1790 | |
| 1791 | REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, |
| 1792 | AR_PHY_SPECTRAL_SCAN_COUNT, count); |
| 1793 | REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, |
| 1794 | AR_PHY_SPECTRAL_SCAN_PERIOD, param->period); |
| 1795 | REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN, |
| 1796 | AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period); |
| 1797 | |
| 1798 | return; |
| 1799 | } |
| 1800 | |
| 1801 | static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah) |
| 1802 | { |
| 1803 | /* Activate spectral scan */ |
| 1804 | REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, |
| 1805 | AR_PHY_SPECTRAL_SCAN_ACTIVE); |
| 1806 | } |
| 1807 | |
| 1808 | static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah) |
| 1809 | { |
| 1810 | struct ath_common *common = ath9k_hw_common(ah); |
| 1811 | |
| 1812 | /* Poll for spectral scan complete */ |
| 1813 | if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN, |
| 1814 | AR_PHY_SPECTRAL_SCAN_ACTIVE, |
| 1815 | 0, AH_WAIT_TIMEOUT)) { |
| 1816 | ath_err(common, "spectral scan wait failed\n"); |
| 1817 | return; |
| 1818 | } |
| 1819 | } |
| 1820 | |
Luis R. Rodriguez | 89f927a | 2013-10-14 17:42:11 -0700 | [diff] [blame] | 1821 | static void ar9003_hw_tx99_start(struct ath_hw *ah, u32 qnum) |
| 1822 | { |
| 1823 | REG_SET_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR); |
| 1824 | REG_SET_BIT(ah, 0x9864, 0x7f000); |
| 1825 | REG_SET_BIT(ah, 0x9924, 0x7f00fe); |
| 1826 | REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); |
| 1827 | REG_WRITE(ah, AR_CR, AR_CR_RXD); |
| 1828 | REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); |
| 1829 | REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */ |
| 1830 | REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); |
| 1831 | REG_WRITE(ah, AR_TIME_OUT, 0x00000400); |
| 1832 | REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); |
| 1833 | REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ); |
| 1834 | } |
| 1835 | |
| 1836 | static void ar9003_hw_tx99_stop(struct ath_hw *ah) |
| 1837 | { |
| 1838 | REG_CLR_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR); |
| 1839 | REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS); |
| 1840 | } |
| 1841 | |
| 1842 | static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower) |
| 1843 | { |
Helmut Schaa | 8569f59 | 2016-04-28 16:45:04 +0200 | [diff] [blame] | 1844 | static u8 p_pwr_array[ar9300RateSize] = { 0 }; |
Luis R. Rodriguez | 89f927a | 2013-10-14 17:42:11 -0700 | [diff] [blame] | 1845 | unsigned int i; |
| 1846 | |
Helmut Schaa | b029171 | 2016-04-28 16:45:06 +0200 | [diff] [blame] | 1847 | txpower = txpower <= MAX_RATE_POWER ? txpower : MAX_RATE_POWER; |
| 1848 | for (i = 0; i < ar9300RateSize; i++) |
| 1849 | p_pwr_array[i] = txpower; |
Luis R. Rodriguez | 89f927a | 2013-10-14 17:42:11 -0700 | [diff] [blame] | 1850 | |
Helmut Schaa | 8569f59 | 2016-04-28 16:45:04 +0200 | [diff] [blame] | 1851 | ar9003_hw_tx_power_regwrite(ah, p_pwr_array); |
Luis R. Rodriguez | 89f927a | 2013-10-14 17:42:11 -0700 | [diff] [blame] | 1852 | } |
| 1853 | |
Lorenzo Bianconi | 23f53dd3 | 2014-11-25 00:21:40 +0100 | [diff] [blame] | 1854 | static void ar9003_hw_init_txpower_cck(struct ath_hw *ah, u8 *rate_array) |
| 1855 | { |
| 1856 | ah->tx_power[0] = rate_array[ALL_TARGET_LEGACY_1L_5L]; |
| 1857 | ah->tx_power[1] = rate_array[ALL_TARGET_LEGACY_1L_5L]; |
| 1858 | ah->tx_power[2] = min(rate_array[ALL_TARGET_LEGACY_1L_5L], |
| 1859 | rate_array[ALL_TARGET_LEGACY_5S]); |
| 1860 | ah->tx_power[3] = min(rate_array[ALL_TARGET_LEGACY_11L], |
| 1861 | rate_array[ALL_TARGET_LEGACY_11S]); |
| 1862 | } |
| 1863 | |
| 1864 | static void ar9003_hw_init_txpower_ofdm(struct ath_hw *ah, u8 *rate_array, |
| 1865 | int offset) |
| 1866 | { |
| 1867 | int i, j; |
| 1868 | |
| 1869 | for (i = offset; i < offset + AR9300_OFDM_RATES; i++) { |
| 1870 | /* OFDM rate to power table idx */ |
| 1871 | j = ofdm2pwr[i - offset]; |
| 1872 | ah->tx_power[i] = rate_array[j]; |
| 1873 | } |
| 1874 | } |
| 1875 | |
| 1876 | static void ar9003_hw_init_txpower_ht(struct ath_hw *ah, u8 *rate_array, |
| 1877 | int ss_offset, int ds_offset, |
| 1878 | int ts_offset, bool is_40) |
| 1879 | { |
| 1880 | int i, j, mcs_idx = 0; |
| 1881 | const u8 *mcs2pwr = (is_40) ? mcs2pwr_ht40 : mcs2pwr_ht20; |
| 1882 | |
| 1883 | for (i = ss_offset; i < ss_offset + AR9300_HT_SS_RATES; i++) { |
| 1884 | j = mcs2pwr[mcs_idx]; |
| 1885 | ah->tx_power[i] = rate_array[j]; |
| 1886 | mcs_idx++; |
| 1887 | } |
| 1888 | |
| 1889 | for (i = ds_offset; i < ds_offset + AR9300_HT_DS_RATES; i++) { |
| 1890 | j = mcs2pwr[mcs_idx]; |
| 1891 | ah->tx_power[i] = rate_array[j]; |
| 1892 | mcs_idx++; |
| 1893 | } |
| 1894 | |
| 1895 | for (i = ts_offset; i < ts_offset + AR9300_HT_TS_RATES; i++) { |
| 1896 | j = mcs2pwr[mcs_idx]; |
| 1897 | ah->tx_power[i] = rate_array[j]; |
| 1898 | mcs_idx++; |
| 1899 | } |
| 1900 | } |
| 1901 | |
| 1902 | static void ar9003_hw_init_txpower_stbc(struct ath_hw *ah, int ss_offset, |
| 1903 | int ds_offset, int ts_offset) |
| 1904 | { |
| 1905 | memcpy(&ah->tx_power_stbc[ss_offset], &ah->tx_power[ss_offset], |
| 1906 | AR9300_HT_SS_RATES); |
| 1907 | memcpy(&ah->tx_power_stbc[ds_offset], &ah->tx_power[ds_offset], |
| 1908 | AR9300_HT_DS_RATES); |
| 1909 | memcpy(&ah->tx_power_stbc[ts_offset], &ah->tx_power[ts_offset], |
| 1910 | AR9300_HT_TS_RATES); |
| 1911 | } |
| 1912 | |
| 1913 | void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array, |
| 1914 | struct ath9k_channel *chan) |
| 1915 | { |
| 1916 | if (IS_CHAN_5GHZ(chan)) { |
| 1917 | ar9003_hw_init_txpower_ofdm(ah, rate_array, |
| 1918 | AR9300_11NA_OFDM_SHIFT); |
| 1919 | if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) { |
| 1920 | ar9003_hw_init_txpower_ht(ah, rate_array, |
| 1921 | AR9300_11NA_HT_SS_SHIFT, |
| 1922 | AR9300_11NA_HT_DS_SHIFT, |
| 1923 | AR9300_11NA_HT_TS_SHIFT, |
| 1924 | IS_CHAN_HT40(chan)); |
| 1925 | ar9003_hw_init_txpower_stbc(ah, |
| 1926 | AR9300_11NA_HT_SS_SHIFT, |
| 1927 | AR9300_11NA_HT_DS_SHIFT, |
| 1928 | AR9300_11NA_HT_TS_SHIFT); |
| 1929 | } |
| 1930 | } else { |
| 1931 | ar9003_hw_init_txpower_cck(ah, rate_array); |
| 1932 | ar9003_hw_init_txpower_ofdm(ah, rate_array, |
| 1933 | AR9300_11NG_OFDM_SHIFT); |
| 1934 | if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) { |
| 1935 | ar9003_hw_init_txpower_ht(ah, rate_array, |
| 1936 | AR9300_11NG_HT_SS_SHIFT, |
| 1937 | AR9300_11NG_HT_DS_SHIFT, |
| 1938 | AR9300_11NG_HT_TS_SHIFT, |
| 1939 | IS_CHAN_HT40(chan)); |
| 1940 | ar9003_hw_init_txpower_stbc(ah, |
| 1941 | AR9300_11NG_HT_SS_SHIFT, |
| 1942 | AR9300_11NG_HT_DS_SHIFT, |
| 1943 | AR9300_11NG_HT_TS_SHIFT); |
| 1944 | } |
| 1945 | } |
| 1946 | } |
| 1947 | |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 1948 | void ar9003_hw_attach_phy_ops(struct ath_hw *ah) |
| 1949 | { |
| 1950 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); |
Mohammed Shafi Shajakhan | 6bcbc06 | 2011-05-13 20:30:41 +0530 | [diff] [blame] | 1951 | struct ath_hw_ops *ops = ath9k_hw_ops(ah); |
Joe Perches | 07b2fa5 | 2010-11-20 18:38:53 -0800 | [diff] [blame] | 1952 | static const u32 ar9300_cca_regs[6] = { |
Felix Fietkau | bbacee1 | 2010-07-11 15:44:42 +0200 | [diff] [blame] | 1953 | AR_PHY_CCA_0, |
| 1954 | AR_PHY_CCA_1, |
| 1955 | AR_PHY_CCA_2, |
| 1956 | AR_PHY_EXT_CCA, |
| 1957 | AR_PHY_EXT_CCA_1, |
| 1958 | AR_PHY_EXT_CCA_2, |
| 1959 | }; |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 1960 | |
| 1961 | priv_ops->rf_set_freq = ar9003_hw_set_channel; |
| 1962 | priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate; |
Felix Fietkau | 5fb9b1b | 2014-09-29 20:45:42 +0200 | [diff] [blame] | 1963 | |
Miaoqing Pan | ede6a5e | 2014-12-19 06:33:59 +0530 | [diff] [blame] | 1964 | if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || |
| 1965 | AR_SREV_9561(ah)) |
Felix Fietkau | 5fb9b1b | 2014-09-29 20:45:42 +0200 | [diff] [blame] | 1966 | priv_ops->compute_pll_control = ar9003_hw_compute_pll_control_soc; |
| 1967 | else |
| 1968 | priv_ops->compute_pll_control = ar9003_hw_compute_pll_control; |
| 1969 | |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 1970 | priv_ops->set_channel_regs = ar9003_hw_set_channel_regs; |
| 1971 | priv_ops->init_bb = ar9003_hw_init_bb; |
| 1972 | priv_ops->process_ini = ar9003_hw_process_ini; |
| 1973 | priv_ops->set_rfmode = ar9003_hw_set_rfmode; |
| 1974 | priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive; |
| 1975 | priv_ops->set_delta_slope = ar9003_hw_set_delta_slope; |
| 1976 | priv_ops->rfbus_req = ar9003_hw_rfbus_req; |
| 1977 | priv_ops->rfbus_done = ar9003_hw_rfbus_done; |
Felix Fietkau | c16fcb4 | 2010-04-15 17:38:39 -0400 | [diff] [blame] | 1978 | priv_ops->ani_control = ar9003_hw_ani_control; |
Felix Fietkau | 641d992 | 2010-04-15 17:38:49 -0400 | [diff] [blame] | 1979 | priv_ops->do_getnf = ar9003_hw_do_getnf; |
Luis R. Rodriguez | e36b27a | 2010-06-12 00:33:45 -0400 | [diff] [blame] | 1980 | priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs; |
Felix Fietkau | 4e8c14e | 2010-11-11 03:18:38 +0100 | [diff] [blame] | 1981 | priv_ops->set_radar_params = ar9003_hw_set_radar_params; |
Rajkumar Manoharan | 5f0c04e | 2011-10-13 11:00:35 +0530 | [diff] [blame] | 1982 | priv_ops->fast_chan_change = ar9003_hw_fast_chan_change; |
Felix Fietkau | f2552e2 | 2010-07-02 00:09:50 +0200 | [diff] [blame] | 1983 | |
Mohammed Shafi Shajakhan | 6bcbc06 | 2011-05-13 20:30:41 +0530 | [diff] [blame] | 1984 | ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get; |
| 1985 | ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set; |
Simon Wunderlich | e93d083 | 2013-01-08 14:48:58 +0100 | [diff] [blame] | 1986 | ops->spectral_scan_config = ar9003_hw_spectral_scan_config; |
| 1987 | ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger; |
| 1988 | ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait; |
Mohammed Shafi Shajakhan | 6bcbc06 | 2011-05-13 20:30:41 +0530 | [diff] [blame] | 1989 | |
Sujith Manoharan | 36e8825 | 2013-08-06 12:44:15 +0530 | [diff] [blame] | 1990 | #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT |
| 1991 | ops->set_bt_ant_diversity = ar9003_hw_set_bt_ant_diversity; |
| 1992 | #endif |
Luis R. Rodriguez | 89f927a | 2013-10-14 17:42:11 -0700 | [diff] [blame] | 1993 | ops->tx99_start = ar9003_hw_tx99_start; |
| 1994 | ops->tx99_stop = ar9003_hw_tx99_stop; |
| 1995 | ops->tx99_set_txpower = ar9003_hw_tx99_set_txpower; |
Sujith Manoharan | 36e8825 | 2013-08-06 12:44:15 +0530 | [diff] [blame] | 1996 | |
Felix Fietkau | f2552e2 | 2010-07-02 00:09:50 +0200 | [diff] [blame] | 1997 | ar9003_hw_set_nf_limits(ah); |
Felix Fietkau | c5d0855 | 2010-11-13 20:22:41 +0100 | [diff] [blame] | 1998 | ar9003_hw_set_radar_conf(ah); |
Felix Fietkau | bbacee1 | 2010-07-11 15:44:42 +0200 | [diff] [blame] | 1999 | memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs)); |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 2000 | } |
Luis R. Rodriguez | aea702b | 2010-05-13 13:33:43 -0400 | [diff] [blame] | 2001 | |
Sujith Manoharan | d88527d | 2013-12-24 10:44:23 +0530 | [diff] [blame] | 2002 | /* |
| 2003 | * Baseband Watchdog signatures: |
| 2004 | * |
| 2005 | * 0x04000539: BB hang when operating in HT40 DFS Channel. |
| 2006 | * Full chip reset is not required, but a recovery |
| 2007 | * mechanism is needed. |
| 2008 | * |
| 2009 | * 0x1300000a: Related to CAC deafness. |
| 2010 | * Chip reset is not required. |
| 2011 | * |
| 2012 | * 0x0400000a: Related to CAC deafness. |
| 2013 | * Full chip reset is required. |
| 2014 | * |
| 2015 | * 0x04000b09: RX state machine gets into an illegal state |
| 2016 | * when a packet with unsupported rate is received. |
| 2017 | * Full chip reset is required and PHY_RESTART has |
| 2018 | * to be disabled. |
| 2019 | * |
| 2020 | * 0x04000409: Packet stuck on receive. |
Miaoqing Pan | 3f6cc4e | 2016-01-18 09:33:48 +0800 | [diff] [blame] | 2021 | * Full chip reset is required for all chips except |
| 2022 | * AR9340, AR9531 and AR9561. |
Sujith Manoharan | d88527d | 2013-12-24 10:44:23 +0530 | [diff] [blame] | 2023 | */ |
| 2024 | |
| 2025 | /* |
| 2026 | * ar9003_hw_bb_watchdog_check(): Returns true if a chip reset is required. |
| 2027 | */ |
| 2028 | bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah) |
| 2029 | { |
| 2030 | u32 val; |
| 2031 | |
| 2032 | switch(ah->bb_watchdog_last_status) { |
| 2033 | case 0x04000539: |
| 2034 | val = REG_READ(ah, AR_PHY_RADAR_0); |
| 2035 | val &= (~AR_PHY_RADAR_0_FIRPWR); |
| 2036 | val |= SM(0x7f, AR_PHY_RADAR_0_FIRPWR); |
| 2037 | REG_WRITE(ah, AR_PHY_RADAR_0, val); |
| 2038 | udelay(1); |
| 2039 | val = REG_READ(ah, AR_PHY_RADAR_0); |
| 2040 | val &= ~AR_PHY_RADAR_0_FIRPWR; |
| 2041 | val |= SM(AR9300_DFS_FIRPWR, AR_PHY_RADAR_0_FIRPWR); |
| 2042 | REG_WRITE(ah, AR_PHY_RADAR_0, val); |
| 2043 | |
| 2044 | return false; |
| 2045 | case 0x1300000a: |
| 2046 | return false; |
| 2047 | case 0x0400000a: |
| 2048 | case 0x04000b09: |
| 2049 | return true; |
| 2050 | case 0x04000409: |
Miaoqing Pan | 3f6cc4e | 2016-01-18 09:33:48 +0800 | [diff] [blame] | 2051 | if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) |
Sujith Manoharan | d88527d | 2013-12-24 10:44:23 +0530 | [diff] [blame] | 2052 | return false; |
| 2053 | else |
| 2054 | return true; |
| 2055 | default: |
| 2056 | /* |
| 2057 | * For any other unknown signatures, do a |
| 2058 | * full chip reset. |
| 2059 | */ |
| 2060 | return true; |
| 2061 | } |
| 2062 | } |
| 2063 | EXPORT_SYMBOL(ar9003_hw_bb_watchdog_check); |
| 2064 | |
Luis R. Rodriguez | aea702b | 2010-05-13 13:33:43 -0400 | [diff] [blame] | 2065 | void ar9003_hw_bb_watchdog_config(struct ath_hw *ah) |
| 2066 | { |
| 2067 | struct ath_common *common = ath9k_hw_common(ah); |
| 2068 | u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms; |
| 2069 | u32 val, idle_count; |
| 2070 | |
| 2071 | if (!idle_tmo_ms) { |
| 2072 | /* disable IRQ, disable chip-reset for BB panic */ |
| 2073 | REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, |
| 2074 | REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & |
| 2075 | ~(AR_PHY_WATCHDOG_RST_ENABLE | |
| 2076 | AR_PHY_WATCHDOG_IRQ_ENABLE)); |
| 2077 | |
| 2078 | /* disable watchdog in non-IDLE mode, disable in IDLE mode */ |
| 2079 | REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, |
| 2080 | REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) & |
| 2081 | ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE | |
| 2082 | AR_PHY_WATCHDOG_IDLE_ENABLE)); |
| 2083 | |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 2084 | ath_dbg(common, RESET, "Disabled BB Watchdog\n"); |
Luis R. Rodriguez | aea702b | 2010-05-13 13:33:43 -0400 | [diff] [blame] | 2085 | return; |
| 2086 | } |
| 2087 | |
| 2088 | /* enable IRQ, disable chip-reset for BB watchdog */ |
| 2089 | val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK; |
| 2090 | REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2, |
| 2091 | (val | AR_PHY_WATCHDOG_IRQ_ENABLE) & |
| 2092 | ~AR_PHY_WATCHDOG_RST_ENABLE); |
| 2093 | |
| 2094 | /* bound limit to 10 secs */ |
| 2095 | if (idle_tmo_ms > 10000) |
| 2096 | idle_tmo_ms = 10000; |
| 2097 | |
| 2098 | /* |
| 2099 | * The time unit for watchdog event is 2^15 44/88MHz cycles. |
| 2100 | * |
| 2101 | * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick |
| 2102 | * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick |
| 2103 | * |
| 2104 | * Given we use fast clock now in 5 GHz, these time units should |
| 2105 | * be common for both 2 GHz and 5 GHz. |
| 2106 | */ |
| 2107 | idle_count = (100 * idle_tmo_ms) / 74; |
| 2108 | if (ah->curchan && IS_CHAN_HT40(ah->curchan)) |
| 2109 | idle_count = (100 * idle_tmo_ms) / 37; |
| 2110 | |
| 2111 | /* |
| 2112 | * enable watchdog in non-IDLE mode, disable in IDLE mode, |
| 2113 | * set idle time-out. |
| 2114 | */ |
| 2115 | REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1, |
| 2116 | AR_PHY_WATCHDOG_NON_IDLE_ENABLE | |
| 2117 | AR_PHY_WATCHDOG_IDLE_MASK | |
| 2118 | (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2))); |
| 2119 | |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 2120 | ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n", |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 2121 | idle_tmo_ms); |
Luis R. Rodriguez | aea702b | 2010-05-13 13:33:43 -0400 | [diff] [blame] | 2122 | } |
| 2123 | |
| 2124 | void ar9003_hw_bb_watchdog_read(struct ath_hw *ah) |
| 2125 | { |
| 2126 | /* |
| 2127 | * we want to avoid printing in ISR context so we save the |
| 2128 | * watchdog status to be printed later in bottom half context. |
| 2129 | */ |
| 2130 | ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS); |
| 2131 | |
| 2132 | /* |
| 2133 | * the watchdog timer should reset on status read but to be sure |
| 2134 | * sure we write 0 to the watchdog status bit. |
| 2135 | */ |
| 2136 | REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS, |
| 2137 | ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR); |
| 2138 | } |
| 2139 | |
| 2140 | void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah) |
| 2141 | { |
| 2142 | struct ath_common *common = ath9k_hw_common(ah); |
Felix Fietkau | 9dbebc7 | 2010-10-03 19:07:17 +0200 | [diff] [blame] | 2143 | u32 status; |
Luis R. Rodriguez | aea702b | 2010-05-13 13:33:43 -0400 | [diff] [blame] | 2144 | |
| 2145 | if (likely(!(common->debug_mask & ATH_DBG_RESET))) |
| 2146 | return; |
| 2147 | |
| 2148 | status = ah->bb_watchdog_last_status; |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 2149 | ath_dbg(common, RESET, |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 2150 | "\n==== BB update: BB status=0x%08x ====\n", status); |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 2151 | ath_dbg(common, RESET, |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 2152 | "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", |
| 2153 | MS(status, AR_PHY_WATCHDOG_INFO), |
| 2154 | MS(status, AR_PHY_WATCHDOG_DET_HANG), |
| 2155 | MS(status, AR_PHY_WATCHDOG_RADAR_SM), |
| 2156 | MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM), |
| 2157 | MS(status, AR_PHY_WATCHDOG_RX_CCK_SM), |
| 2158 | MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM), |
| 2159 | MS(status, AR_PHY_WATCHDOG_TX_CCK_SM), |
| 2160 | MS(status, AR_PHY_WATCHDOG_AGC_SM), |
| 2161 | MS(status, AR_PHY_WATCHDOG_SRCH_SM)); |
Luis R. Rodriguez | aea702b | 2010-05-13 13:33:43 -0400 | [diff] [blame] | 2162 | |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 2163 | ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 2164 | REG_READ(ah, AR_PHY_WATCHDOG_CTL_1), |
| 2165 | REG_READ(ah, AR_PHY_WATCHDOG_CTL_2)); |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 2166 | ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n", |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 2167 | REG_READ(ah, AR_PHY_GEN_CTRL)); |
Luis R. Rodriguez | aea702b | 2010-05-13 13:33:43 -0400 | [diff] [blame] | 2168 | |
Felix Fietkau | b5bfc56 | 2010-10-08 22:13:53 +0200 | [diff] [blame] | 2169 | #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles) |
| 2170 | if (common->cc_survey.cycles) |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 2171 | ath_dbg(common, RESET, |
Joe Perches | 226afe6 | 2010-12-02 19:12:37 -0800 | [diff] [blame] | 2172 | "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n", |
| 2173 | PCT(rx_busy), PCT(rx_frame), PCT(tx_frame)); |
Luis R. Rodriguez | aea702b | 2010-05-13 13:33:43 -0400 | [diff] [blame] | 2174 | |
Joe Perches | d2182b6 | 2011-12-15 14:55:53 -0800 | [diff] [blame] | 2175 | ath_dbg(common, RESET, "==== BB update: done ====\n\n"); |
Luis R. Rodriguez | aea702b | 2010-05-13 13:33:43 -0400 | [diff] [blame] | 2176 | } |
| 2177 | EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info); |
Rajkumar Manoharan | 51ac8cb | 2011-05-20 17:52:13 +0530 | [diff] [blame] | 2178 | |
| 2179 | void ar9003_hw_disable_phy_restart(struct ath_hw *ah) |
| 2180 | { |
Sujith Manoharan | a7abaf7 | 2013-12-24 10:44:21 +0530 | [diff] [blame] | 2181 | u8 result; |
Rajkumar Manoharan | 51ac8cb | 2011-05-20 17:52:13 +0530 | [diff] [blame] | 2182 | u32 val; |
| 2183 | |
| 2184 | /* While receiving unsupported rate frame rx state machine |
| 2185 | * gets into a state 0xb and if phy_restart happens in that |
| 2186 | * state, BB would go hang. If RXSM is in 0xb state after |
| 2187 | * first bb panic, ensure to disable the phy_restart. |
| 2188 | */ |
Sujith Manoharan | a7abaf7 | 2013-12-24 10:44:21 +0530 | [diff] [blame] | 2189 | result = MS(ah->bb_watchdog_last_status, AR_PHY_WATCHDOG_RX_OFDM_SM); |
Rajkumar Manoharan | 51ac8cb | 2011-05-20 17:52:13 +0530 | [diff] [blame] | 2190 | |
Sujith Manoharan | a7abaf7 | 2013-12-24 10:44:21 +0530 | [diff] [blame] | 2191 | if ((result == 0xb) || ah->bb_hang_rx_ofdm) { |
| 2192 | ah->bb_hang_rx_ofdm = true; |
| 2193 | val = REG_READ(ah, AR_PHY_RESTART); |
| 2194 | val &= ~AR_PHY_RESTART_ENA; |
| 2195 | REG_WRITE(ah, AR_PHY_RESTART, val); |
| 2196 | } |
Rajkumar Manoharan | 51ac8cb | 2011-05-20 17:52:13 +0530 | [diff] [blame] | 2197 | } |
| 2198 | EXPORT_SYMBOL(ar9003_hw_disable_phy_restart); |