Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | */ |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 3 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
| 5 | * All Rights Reserved. |
Dave Airlie | bc54fd1 | 2005-06-23 22:46:46 +1000 | [diff] [blame] | 6 | * |
| 7 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 8 | * copy of this software and associated documentation files (the |
| 9 | * "Software"), to deal in the Software without restriction, including |
| 10 | * without limitation the rights to use, copy, modify, merge, publish, |
| 11 | * distribute, sub license, and/or sell copies of the Software, and to |
| 12 | * permit persons to whom the Software is furnished to do so, subject to |
| 13 | * the following conditions: |
| 14 | * |
| 15 | * The above copyright notice and this permission notice (including the |
| 16 | * next paragraph) shall be included in all copies or substantial portions |
| 17 | * of the Software. |
| 18 | * |
| 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| 20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
| 22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
| 23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 26 | * |
Dave Airlie | 0d6aa60 | 2006-01-02 20:14:23 +1100 | [diff] [blame] | 27 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
| 29 | #include "drmP.h" |
| 30 | #include "drm.h" |
| 31 | #include "i915_drm.h" |
| 32 | #include "i915_drv.h" |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 33 | #include "intel_drv.h" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | #define MAX_NOPID ((u32)~0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 36 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 37 | /** |
| 38 | * Interrupts that are always left unmasked. |
| 39 | * |
| 40 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, |
| 41 | * we leave them always unmasked in IMR and then control enabling them through |
| 42 | * PIPESTAT alone. |
| 43 | */ |
| 44 | #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \ |
| 45 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ |
| 46 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) |
| 47 | |
| 48 | /** Interrupts that we mask and unmask at runtime. */ |
| 49 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT) |
| 50 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 51 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
| 52 | PIPE_VBLANK_INTERRUPT_STATUS) |
| 53 | |
| 54 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ |
| 55 | PIPE_VBLANK_INTERRUPT_ENABLE) |
| 56 | |
| 57 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ |
| 58 | DRM_I915_VBLANK_PIPE_B) |
| 59 | |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 60 | void |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 61 | igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 62 | { |
| 63 | if ((dev_priv->gt_irq_mask_reg & mask) != 0) { |
| 64 | dev_priv->gt_irq_mask_reg &= ~mask; |
| 65 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); |
| 66 | (void) I915_READ(GTIMR); |
| 67 | } |
| 68 | } |
| 69 | |
| 70 | static inline void |
| 71 | igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 72 | { |
| 73 | if ((dev_priv->gt_irq_mask_reg & mask) != mask) { |
| 74 | dev_priv->gt_irq_mask_reg |= mask; |
| 75 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); |
| 76 | (void) I915_READ(GTIMR); |
| 77 | } |
| 78 | } |
| 79 | |
| 80 | /* For display hotplug interrupt */ |
| 81 | void |
| 82 | igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 83 | { |
| 84 | if ((dev_priv->irq_mask_reg & mask) != 0) { |
| 85 | dev_priv->irq_mask_reg &= ~mask; |
| 86 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); |
| 87 | (void) I915_READ(DEIMR); |
| 88 | } |
| 89 | } |
| 90 | |
| 91 | static inline void |
| 92 | igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 93 | { |
| 94 | if ((dev_priv->irq_mask_reg & mask) != mask) { |
| 95 | dev_priv->irq_mask_reg |= mask; |
| 96 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); |
| 97 | (void) I915_READ(DEIMR); |
| 98 | } |
| 99 | } |
| 100 | |
| 101 | void |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 102 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 103 | { |
| 104 | if ((dev_priv->irq_mask_reg & mask) != 0) { |
| 105 | dev_priv->irq_mask_reg &= ~mask; |
| 106 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
| 107 | (void) I915_READ(IMR); |
| 108 | } |
| 109 | } |
| 110 | |
| 111 | static inline void |
| 112 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 113 | { |
| 114 | if ((dev_priv->irq_mask_reg & mask) != mask) { |
| 115 | dev_priv->irq_mask_reg |= mask; |
| 116 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
| 117 | (void) I915_READ(IMR); |
| 118 | } |
| 119 | } |
| 120 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 121 | static inline u32 |
| 122 | i915_pipestat(int pipe) |
| 123 | { |
| 124 | if (pipe == 0) |
| 125 | return PIPEASTAT; |
| 126 | if (pipe == 1) |
| 127 | return PIPEBSTAT; |
Andrew Morton | 9c84ba4 | 2008-12-01 13:14:08 -0800 | [diff] [blame] | 128 | BUG(); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 129 | } |
| 130 | |
| 131 | void |
| 132 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) |
| 133 | { |
| 134 | if ((dev_priv->pipestat[pipe] & mask) != mask) { |
| 135 | u32 reg = i915_pipestat(pipe); |
| 136 | |
| 137 | dev_priv->pipestat[pipe] |= mask; |
| 138 | /* Enable the interrupt, clear any pending status */ |
| 139 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); |
| 140 | (void) I915_READ(reg); |
| 141 | } |
| 142 | } |
| 143 | |
| 144 | void |
| 145 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) |
| 146 | { |
| 147 | if ((dev_priv->pipestat[pipe] & mask) != 0) { |
| 148 | u32 reg = i915_pipestat(pipe); |
| 149 | |
| 150 | dev_priv->pipestat[pipe] &= ~mask; |
| 151 | I915_WRITE(reg, dev_priv->pipestat[pipe]); |
| 152 | (void) I915_READ(reg); |
| 153 | } |
| 154 | } |
| 155 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 156 | /** |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 157 | * i915_pipe_enabled - check if a pipe is enabled |
| 158 | * @dev: DRM device |
| 159 | * @pipe: pipe to check |
| 160 | * |
| 161 | * Reading certain registers when the pipe is disabled can hang the chip. |
| 162 | * Use this routine to make sure the PLL is running and the pipe is active |
| 163 | * before reading such registers if unsure. |
| 164 | */ |
| 165 | static int |
| 166 | i915_pipe_enabled(struct drm_device *dev, int pipe) |
| 167 | { |
| 168 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 169 | unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF; |
| 170 | |
| 171 | if (I915_READ(pipeconf) & PIPEACONF_ENABLE) |
| 172 | return 1; |
| 173 | |
| 174 | return 0; |
| 175 | } |
| 176 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 177 | /* Called from drm generic code, passed a 'crtc', which |
| 178 | * we use as a pipe index |
| 179 | */ |
| 180 | u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 181 | { |
| 182 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 183 | unsigned long high_frame; |
| 184 | unsigned long low_frame; |
| 185 | u32 high1, high2, low, count; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 186 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 187 | high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; |
| 188 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; |
| 189 | |
| 190 | if (!i915_pipe_enabled(dev, pipe)) { |
| 191 | DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe); |
| 192 | return 0; |
| 193 | } |
| 194 | |
| 195 | /* |
| 196 | * High & low register fields aren't synchronized, so make sure |
| 197 | * we get a low value that's stable across two reads of the high |
| 198 | * register. |
| 199 | */ |
| 200 | do { |
| 201 | high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> |
| 202 | PIPE_FRAME_HIGH_SHIFT); |
| 203 | low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> |
| 204 | PIPE_FRAME_LOW_SHIFT); |
| 205 | high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> |
| 206 | PIPE_FRAME_HIGH_SHIFT); |
| 207 | } while (high1 != high2); |
| 208 | |
| 209 | count = (high1 << 8) | low; |
| 210 | |
| 211 | return count; |
| 212 | } |
| 213 | |
Jesse Barnes | 9880b7a | 2009-02-06 10:22:41 -0800 | [diff] [blame] | 214 | u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
| 215 | { |
| 216 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 217 | int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; |
| 218 | |
| 219 | if (!i915_pipe_enabled(dev, pipe)) { |
| 220 | DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe); |
| 221 | return 0; |
| 222 | } |
| 223 | |
| 224 | return I915_READ(reg); |
| 225 | } |
| 226 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 227 | /* |
| 228 | * Handle hotplug events outside the interrupt handler proper. |
| 229 | */ |
| 230 | static void i915_hotplug_work_func(struct work_struct *work) |
| 231 | { |
| 232 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
| 233 | hotplug_work); |
| 234 | struct drm_device *dev = dev_priv->dev; |
Keith Packard | c31c4ba | 2009-05-06 11:48:58 -0700 | [diff] [blame^] | 235 | struct drm_mode_config *mode_config = &dev->mode_config; |
| 236 | struct drm_connector *connector; |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 237 | |
Keith Packard | c31c4ba | 2009-05-06 11:48:58 -0700 | [diff] [blame^] | 238 | if (mode_config->num_connector) { |
| 239 | list_for_each_entry(connector, &mode_config->connector_list, head) { |
| 240 | struct intel_output *intel_output = to_intel_output(connector); |
| 241 | |
| 242 | if (intel_output->hot_plug) |
| 243 | (*intel_output->hot_plug) (intel_output); |
| 244 | } |
| 245 | } |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 246 | /* Just fire off a uevent and let userspace tell us what to do */ |
| 247 | drm_sysfs_hotplug_event(dev); |
| 248 | } |
| 249 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 250 | irqreturn_t igdng_irq_handler(struct drm_device *dev) |
| 251 | { |
| 252 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 253 | int ret = IRQ_NONE; |
| 254 | u32 de_iir, gt_iir; |
| 255 | u32 new_de_iir, new_gt_iir; |
| 256 | struct drm_i915_master_private *master_priv; |
| 257 | |
| 258 | de_iir = I915_READ(DEIIR); |
| 259 | gt_iir = I915_READ(GTIIR); |
| 260 | |
| 261 | for (;;) { |
| 262 | if (de_iir == 0 && gt_iir == 0) |
| 263 | break; |
| 264 | |
| 265 | ret = IRQ_HANDLED; |
| 266 | |
| 267 | I915_WRITE(DEIIR, de_iir); |
| 268 | new_de_iir = I915_READ(DEIIR); |
| 269 | I915_WRITE(GTIIR, gt_iir); |
| 270 | new_gt_iir = I915_READ(GTIIR); |
| 271 | |
| 272 | if (dev->primary->master) { |
| 273 | master_priv = dev->primary->master->driver_priv; |
| 274 | if (master_priv->sarea_priv) |
| 275 | master_priv->sarea_priv->last_dispatch = |
| 276 | READ_BREADCRUMB(dev_priv); |
| 277 | } |
| 278 | |
| 279 | if (gt_iir & GT_USER_INTERRUPT) { |
| 280 | dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev); |
| 281 | DRM_WAKEUP(&dev_priv->irq_queue); |
| 282 | } |
| 283 | |
| 284 | de_iir = new_de_iir; |
| 285 | gt_iir = new_gt_iir; |
| 286 | } |
| 287 | |
| 288 | return ret; |
| 289 | } |
| 290 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 291 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
| 292 | { |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 293 | struct drm_device *dev = (struct drm_device *) arg; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 294 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 295 | struct drm_i915_master_private *master_priv; |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 296 | u32 iir, new_iir; |
| 297 | u32 pipea_stats, pipeb_stats; |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 298 | u32 vblank_status; |
| 299 | u32 vblank_enable; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 300 | int vblank = 0; |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 301 | unsigned long irqflags; |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 302 | int irq_received; |
| 303 | int ret = IRQ_NONE; |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 304 | |
Eric Anholt | 630681d | 2008-10-06 15:14:12 -0700 | [diff] [blame] | 305 | atomic_inc(&dev_priv->irq_received); |
| 306 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 307 | if (IS_IGDNG(dev)) |
| 308 | return igdng_irq_handler(dev); |
| 309 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 310 | iir = I915_READ(IIR); |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 311 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 312 | if (IS_I965G(dev)) { |
| 313 | vblank_status = I915_START_VBLANK_INTERRUPT_STATUS; |
| 314 | vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE; |
| 315 | } else { |
| 316 | vblank_status = I915_VBLANK_INTERRUPT_STATUS; |
| 317 | vblank_enable = I915_VBLANK_INTERRUPT_ENABLE; |
| 318 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 319 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 320 | for (;;) { |
| 321 | irq_received = iir != 0; |
| 322 | |
| 323 | /* Can't rely on pipestat interrupt bit in iir as it might |
| 324 | * have been cleared after the pipestat interrupt was received. |
| 325 | * It doesn't set the bit in iir again, but it still produces |
| 326 | * interrupts (for non-MSI). |
| 327 | */ |
| 328 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
| 329 | pipea_stats = I915_READ(PIPEASTAT); |
| 330 | pipeb_stats = I915_READ(PIPEBSTAT); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 331 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 332 | /* |
| 333 | * Clear the PIPE(A|B)STAT regs before the IIR |
| 334 | */ |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 335 | if (pipea_stats & 0x8000ffff) { |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 336 | I915_WRITE(PIPEASTAT, pipea_stats); |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 337 | irq_received = 1; |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 338 | } |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 339 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 340 | if (pipeb_stats & 0x8000ffff) { |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 341 | I915_WRITE(PIPEBSTAT, pipeb_stats); |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 342 | irq_received = 1; |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 343 | } |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 344 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
| 345 | |
| 346 | if (!irq_received) |
| 347 | break; |
| 348 | |
| 349 | ret = IRQ_HANDLED; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 350 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 351 | /* Consume port. Then clear IIR or we'll miss events */ |
| 352 | if ((I915_HAS_HOTPLUG(dev)) && |
| 353 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { |
| 354 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); |
| 355 | |
| 356 | DRM_DEBUG("hotplug event received, stat 0x%08x\n", |
| 357 | hotplug_status); |
| 358 | if (hotplug_status & dev_priv->hotplug_supported_mask) |
| 359 | schedule_work(&dev_priv->hotplug_work); |
| 360 | |
| 361 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
| 362 | I915_READ(PORT_HOTPLUG_STAT); |
| 363 | } |
| 364 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 365 | I915_WRITE(IIR, iir); |
| 366 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 367 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 368 | if (dev->primary->master) { |
| 369 | master_priv = dev->primary->master->driver_priv; |
| 370 | if (master_priv->sarea_priv) |
| 371 | master_priv->sarea_priv->last_dispatch = |
| 372 | READ_BREADCRUMB(dev_priv); |
| 373 | } |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 374 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 375 | if (iir & I915_USER_INTERRUPT) { |
| 376 | dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev); |
| 377 | DRM_WAKEUP(&dev_priv->irq_queue); |
| 378 | } |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 379 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 380 | if (pipea_stats & vblank_status) { |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 381 | vblank++; |
| 382 | drm_handle_vblank(dev, 0); |
| 383 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 384 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 385 | if (pipeb_stats & vblank_status) { |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 386 | vblank++; |
| 387 | drm_handle_vblank(dev, 1); |
| 388 | } |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 389 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 390 | if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) || |
| 391 | (iir & I915_ASLE_INTERRUPT)) |
| 392 | opregion_asle_intr(dev); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 393 | |
Eric Anholt | cdfbc41 | 2008-11-04 15:50:30 -0800 | [diff] [blame] | 394 | /* With MSI, interrupts are only generated when iir |
| 395 | * transitions from zero to nonzero. If another bit got |
| 396 | * set while we were handling the existing iir bits, then |
| 397 | * we would never get another interrupt. |
| 398 | * |
| 399 | * This is fine on non-MSI as well, as if we hit this path |
| 400 | * we avoid exiting the interrupt handler only to generate |
| 401 | * another one. |
| 402 | * |
| 403 | * Note that for MSI this could cause a stray interrupt report |
| 404 | * if an interrupt landed in the time between writing IIR and |
| 405 | * the posting read. This should be rare enough to never |
| 406 | * trigger the 99% of 100,000 interrupts test for disabling |
| 407 | * stray interrupts. |
| 408 | */ |
| 409 | iir = new_iir; |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 410 | } |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 411 | |
Keith Packard | 05eff84 | 2008-11-19 14:03:05 -0800 | [diff] [blame] | 412 | return ret; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 413 | } |
| 414 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 415 | static int i915_emit_irq(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 416 | { |
| 417 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 418 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 419 | RING_LOCALS; |
| 420 | |
| 421 | i915_kernel_lost_context(dev); |
| 422 | |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 423 | DRM_DEBUG("\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 424 | |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 425 | dev_priv->counter++; |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 426 | if (dev_priv->counter > 0x7FFFFFFFUL) |
Kristian Høgsberg | c99b058 | 2008-08-20 11:20:13 -0400 | [diff] [blame] | 427 | dev_priv->counter = 1; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 428 | if (master_priv->sarea_priv) |
| 429 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 430 | |
Keith Packard | 0baf823 | 2008-11-08 11:44:14 +1000 | [diff] [blame] | 431 | BEGIN_LP_RING(4); |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 432 | OUT_RING(MI_STORE_DWORD_INDEX); |
Keith Packard | 0baf823 | 2008-11-08 11:44:14 +1000 | [diff] [blame] | 433 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 434 | OUT_RING(dev_priv->counter); |
Jesse Barnes | 585fb11 | 2008-07-29 11:54:06 -0700 | [diff] [blame] | 435 | OUT_RING(MI_USER_INTERRUPT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 436 | ADVANCE_LP_RING(); |
Dave Airlie | bc5f452 | 2007-11-05 12:50:58 +1000 | [diff] [blame] | 437 | |
Alan Hourihane | c29b669 | 2006-08-12 16:29:24 +1000 | [diff] [blame] | 438 | return dev_priv->counter; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 439 | } |
| 440 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 441 | void i915_user_irq_get(struct drm_device *dev) |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 442 | { |
| 443 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 444 | unsigned long irqflags; |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 445 | |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 446 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 447 | if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) { |
| 448 | if (IS_IGDNG(dev)) |
| 449 | igdng_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT); |
| 450 | else |
| 451 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); |
| 452 | } |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 453 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 454 | } |
| 455 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 456 | void i915_user_irq_put(struct drm_device *dev) |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 457 | { |
| 458 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 459 | unsigned long irqflags; |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 460 | |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 461 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 462 | BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0); |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 463 | if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) { |
| 464 | if (IS_IGDNG(dev)) |
| 465 | igdng_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT); |
| 466 | else |
| 467 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); |
| 468 | } |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 469 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 470 | } |
| 471 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 472 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 473 | { |
| 474 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 475 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 476 | int ret = 0; |
| 477 | |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 478 | DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 479 | READ_BREADCRUMB(dev_priv)); |
| 480 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 481 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 482 | if (master_priv->sarea_priv) |
| 483 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 484 | return 0; |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 485 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 486 | |
Dave Airlie | 7c1c287 | 2008-11-28 14:22:24 +1000 | [diff] [blame] | 487 | if (master_priv->sarea_priv) |
| 488 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 489 | |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 490 | i915_user_irq_get(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 491 | DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ, |
| 492 | READ_BREADCRUMB(dev_priv) >= irq_nr); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 493 | i915_user_irq_put(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 494 | |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 495 | if (ret == -EBUSY) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 496 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 497 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
| 498 | } |
| 499 | |
Dave Airlie | af6061a | 2008-05-07 12:15:39 +1000 | [diff] [blame] | 500 | return ret; |
| 501 | } |
| 502 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 503 | /* Needs the lock as it touches the ring. |
| 504 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 505 | int i915_irq_emit(struct drm_device *dev, void *data, |
| 506 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 507 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 508 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 509 | drm_i915_irq_emit_t *emit = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 510 | int result; |
| 511 | |
Eric Anholt | 07f4f8b | 2009-04-16 13:46:12 -0700 | [diff] [blame] | 512 | if (!dev_priv || !dev_priv->ring.virtual_start) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 513 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 514 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 515 | } |
Eric Anholt | 299eb93 | 2009-02-24 22:14:12 -0800 | [diff] [blame] | 516 | |
| 517 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); |
| 518 | |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 519 | mutex_lock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 520 | result = i915_emit_irq(dev); |
Eric Anholt | 546b097 | 2008-09-01 16:45:29 -0700 | [diff] [blame] | 521 | mutex_unlock(&dev->struct_mutex); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 522 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 523 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 524 | DRM_ERROR("copy_to_user\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 525 | return -EFAULT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 526 | } |
| 527 | |
| 528 | return 0; |
| 529 | } |
| 530 | |
| 531 | /* Doesn't need the hardware lock. |
| 532 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 533 | int i915_irq_wait(struct drm_device *dev, void *data, |
| 534 | struct drm_file *file_priv) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 535 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 536 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 537 | drm_i915_irq_wait_t *irqwait = data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 538 | |
| 539 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 540 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 541 | return -EINVAL; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 542 | } |
| 543 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 544 | return i915_wait_irq(dev, irqwait->irq_seq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 545 | } |
| 546 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 547 | /* Called from drm generic code, passed 'crtc' which |
| 548 | * we use as a pipe index |
| 549 | */ |
| 550 | int i915_enable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 551 | { |
| 552 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 553 | unsigned long irqflags; |
Jesse Barnes | 71e0ffa | 2009-01-08 10:42:15 -0800 | [diff] [blame] | 554 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; |
| 555 | u32 pipeconf; |
| 556 | |
| 557 | pipeconf = I915_READ(pipeconf_reg); |
| 558 | if (!(pipeconf & PIPEACONF_ENABLE)) |
| 559 | return -EINVAL; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 560 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 561 | if (IS_IGDNG(dev)) |
| 562 | return 0; |
| 563 | |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 564 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 565 | if (IS_I965G(dev)) |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 566 | i915_enable_pipestat(dev_priv, pipe, |
| 567 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 568 | else |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 569 | i915_enable_pipestat(dev_priv, pipe, |
| 570 | PIPE_VBLANK_INTERRUPT_ENABLE); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 571 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 572 | return 0; |
| 573 | } |
| 574 | |
Keith Packard | 42f52ef | 2008-10-18 19:39:29 -0700 | [diff] [blame] | 575 | /* Called from drm generic code, passed 'crtc' which |
| 576 | * we use as a pipe index |
| 577 | */ |
| 578 | void i915_disable_vblank(struct drm_device *dev, int pipe) |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 579 | { |
| 580 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 581 | unsigned long irqflags; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 582 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 583 | if (IS_IGDNG(dev)) |
| 584 | return; |
| 585 | |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 586 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 587 | i915_disable_pipestat(dev_priv, pipe, |
| 588 | PIPE_VBLANK_INTERRUPT_ENABLE | |
| 589 | PIPE_START_VBLANK_INTERRUPT_ENABLE); |
Keith Packard | e9d21d7 | 2008-10-16 11:31:38 -0700 | [diff] [blame] | 590 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 591 | } |
| 592 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 593 | void i915_enable_interrupt (struct drm_device *dev) |
| 594 | { |
| 595 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhenyu Wang | e170b03 | 2009-06-05 15:38:40 +0800 | [diff] [blame] | 596 | |
| 597 | if (!IS_IGDNG(dev)) |
| 598 | opregion_enable_asle(dev); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 599 | dev_priv->irq_enabled = 1; |
| 600 | } |
| 601 | |
| 602 | |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 603 | /* Set the vblank monitor pipe |
| 604 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 605 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
| 606 | struct drm_file *file_priv) |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 607 | { |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 608 | drm_i915_private_t *dev_priv = dev->dev_private; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 609 | |
| 610 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 611 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 612 | return -EINVAL; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 613 | } |
| 614 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | 5b51694 | 2006-10-25 00:08:23 +1000 | [diff] [blame] | 615 | return 0; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 616 | } |
| 617 | |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 618 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
| 619 | struct drm_file *file_priv) |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 620 | { |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 621 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 622 | drm_i915_vblank_pipe_t *pipe = data; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 623 | |
| 624 | if (!dev_priv) { |
Márton Németh | 3e684ea | 2008-01-24 15:58:57 +1000 | [diff] [blame] | 625 | DRM_ERROR("called with no initialization\n"); |
Eric Anholt | 20caafa | 2007-08-25 19:22:43 +1000 | [diff] [blame] | 626 | return -EINVAL; |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 627 | } |
| 628 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 629 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 630 | |
Dave Airlie | 702880f | 2006-06-24 17:07:34 +1000 | [diff] [blame] | 631 | return 0; |
| 632 | } |
| 633 | |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 634 | /** |
| 635 | * Schedule buffer swap at given vertical blank. |
| 636 | */ |
Eric Anholt | c153f45 | 2007-09-03 12:06:45 +1000 | [diff] [blame] | 637 | int i915_vblank_swap(struct drm_device *dev, void *data, |
| 638 | struct drm_file *file_priv) |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 639 | { |
Eric Anholt | bd95e0a | 2008-11-04 12:01:24 -0800 | [diff] [blame] | 640 | /* The delayed swap mechanism was fundamentally racy, and has been |
| 641 | * removed. The model was that the client requested a delayed flip/swap |
| 642 | * from the kernel, then waited for vblank before continuing to perform |
| 643 | * rendering. The problem was that the kernel might wake the client |
| 644 | * up before it dispatched the vblank swap (since the lock has to be |
| 645 | * held while touching the ringbuffer), in which case the client would |
| 646 | * clear and start the next frame before the swap occurred, and |
| 647 | * flicker would occur in addition to likely missing the vblank. |
| 648 | * |
| 649 | * In the absence of this ioctl, userland falls back to a correct path |
| 650 | * of waiting for a vblank, then dispatching the swap on its own. |
| 651 | * Context switching to userland and back is plenty fast enough for |
| 652 | * meeting the requirements of vblank swapping. |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 653 | */ |
Eric Anholt | bd95e0a | 2008-11-04 12:01:24 -0800 | [diff] [blame] | 654 | return -EINVAL; |
=?utf-8?q?Michel_D=C3=A4nzer?= | a6b54f3 | 2006-10-24 23:37:43 +1000 | [diff] [blame] | 655 | } |
| 656 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 657 | /* drm_dma.h hooks |
| 658 | */ |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 659 | static void igdng_irq_preinstall(struct drm_device *dev) |
| 660 | { |
| 661 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 662 | |
| 663 | I915_WRITE(HWSTAM, 0xeffe); |
| 664 | |
| 665 | /* XXX hotplug from PCH */ |
| 666 | |
| 667 | I915_WRITE(DEIMR, 0xffffffff); |
| 668 | I915_WRITE(DEIER, 0x0); |
| 669 | (void) I915_READ(DEIER); |
| 670 | |
| 671 | /* and GT */ |
| 672 | I915_WRITE(GTIMR, 0xffffffff); |
| 673 | I915_WRITE(GTIER, 0x0); |
| 674 | (void) I915_READ(GTIER); |
| 675 | } |
| 676 | |
| 677 | static int igdng_irq_postinstall(struct drm_device *dev) |
| 678 | { |
| 679 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 680 | /* enable kind of interrupts always enabled */ |
| 681 | u32 display_mask = DE_MASTER_IRQ_CONTROL /*| DE_PCH_EVENT */; |
| 682 | u32 render_mask = GT_USER_INTERRUPT; |
| 683 | |
| 684 | dev_priv->irq_mask_reg = ~display_mask; |
| 685 | dev_priv->de_irq_enable_reg = display_mask; |
| 686 | |
| 687 | /* should always can generate irq */ |
| 688 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
| 689 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); |
| 690 | I915_WRITE(DEIER, dev_priv->de_irq_enable_reg); |
| 691 | (void) I915_READ(DEIER); |
| 692 | |
| 693 | /* user interrupt should be enabled, but masked initial */ |
| 694 | dev_priv->gt_irq_mask_reg = 0xffffffff; |
| 695 | dev_priv->gt_irq_enable_reg = render_mask; |
| 696 | |
| 697 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 698 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); |
| 699 | I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); |
| 700 | (void) I915_READ(GTIER); |
| 701 | |
| 702 | return 0; |
| 703 | } |
| 704 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 705 | void i915_driver_irq_preinstall(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 706 | { |
| 707 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 708 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 709 | atomic_set(&dev_priv->irq_received, 0); |
| 710 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 711 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
| 712 | |
| 713 | if (IS_IGDNG(dev)) { |
| 714 | igdng_irq_preinstall(dev); |
| 715 | return; |
| 716 | } |
| 717 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 718 | if (I915_HAS_HOTPLUG(dev)) { |
| 719 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 720 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 721 | } |
| 722 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 723 | I915_WRITE(HWSTAM, 0xeffe); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 724 | I915_WRITE(PIPEASTAT, 0); |
| 725 | I915_WRITE(PIPEBSTAT, 0); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 726 | I915_WRITE(IMR, 0xffffffff); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 727 | I915_WRITE(IER, 0x0); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 728 | (void) I915_READ(IER); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 729 | } |
| 730 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 731 | int i915_driver_irq_postinstall(struct drm_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 732 | { |
| 733 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 734 | u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 735 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 736 | DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); |
| 737 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 738 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 739 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 740 | if (IS_IGDNG(dev)) |
| 741 | return igdng_irq_postinstall(dev); |
| 742 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 743 | /* Unmask the interrupts that we always want on. */ |
| 744 | dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 745 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 746 | dev_priv->pipestat[0] = 0; |
| 747 | dev_priv->pipestat[1] = 0; |
| 748 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 749 | if (I915_HAS_HOTPLUG(dev)) { |
| 750 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); |
| 751 | |
| 752 | /* Leave other bits alone */ |
| 753 | hotplug_en |= HOTPLUG_EN_MASK; |
| 754 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); |
| 755 | |
| 756 | dev_priv->hotplug_supported_mask = CRT_HOTPLUG_INT_STATUS | |
| 757 | TV_HOTPLUG_INT_STATUS | SDVOC_HOTPLUG_INT_STATUS | |
| 758 | SDVOB_HOTPLUG_INT_STATUS; |
| 759 | if (IS_G4X(dev)) { |
| 760 | dev_priv->hotplug_supported_mask |= |
| 761 | HDMIB_HOTPLUG_INT_STATUS | |
| 762 | HDMIC_HOTPLUG_INT_STATUS | |
| 763 | HDMID_HOTPLUG_INT_STATUS; |
| 764 | } |
| 765 | /* Enable in IER... */ |
| 766 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; |
| 767 | /* and unmask in IMR */ |
| 768 | i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT); |
| 769 | } |
| 770 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 771 | /* Disable pipe interrupt enables, clear pending pipe status */ |
| 772 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
| 773 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); |
| 774 | /* Clear pending interrupt status */ |
| 775 | I915_WRITE(IIR, I915_READ(IIR)); |
| 776 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 777 | I915_WRITE(IER, enable_mask); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 778 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 779 | (void) I915_READ(IER); |
| 780 | |
Matthew Garrett | 8ee1c3d | 2008-08-05 19:37:25 +0100 | [diff] [blame] | 781 | opregion_enable_asle(dev); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 782 | |
| 783 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 784 | } |
| 785 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 786 | static void igdng_irq_uninstall(struct drm_device *dev) |
| 787 | { |
| 788 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
| 789 | I915_WRITE(HWSTAM, 0xffffffff); |
| 790 | |
| 791 | I915_WRITE(DEIMR, 0xffffffff); |
| 792 | I915_WRITE(DEIER, 0x0); |
| 793 | I915_WRITE(DEIIR, I915_READ(DEIIR)); |
| 794 | |
| 795 | I915_WRITE(GTIMR, 0xffffffff); |
| 796 | I915_WRITE(GTIER, 0x0); |
| 797 | I915_WRITE(GTIIR, I915_READ(GTIIR)); |
| 798 | } |
| 799 | |
Dave Airlie | 84b1fd1 | 2007-07-11 15:53:27 +1000 | [diff] [blame] | 800 | void i915_driver_irq_uninstall(struct drm_device * dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 801 | { |
| 802 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
Dave Airlie | 91e3738 | 2006-02-18 15:17:04 +1100 | [diff] [blame] | 803 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 804 | if (!dev_priv) |
| 805 | return; |
| 806 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 807 | dev_priv->vblank_pipe = 0; |
| 808 | |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 809 | if (IS_IGDNG(dev)) { |
| 810 | igdng_irq_uninstall(dev); |
| 811 | return; |
| 812 | } |
| 813 | |
Jesse Barnes | 5ca5828 | 2009-03-31 14:11:15 -0700 | [diff] [blame] | 814 | if (I915_HAS_HOTPLUG(dev)) { |
| 815 | I915_WRITE(PORT_HOTPLUG_EN, 0); |
| 816 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
| 817 | } |
| 818 | |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 819 | I915_WRITE(HWSTAM, 0xffffffff); |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 820 | I915_WRITE(PIPEASTAT, 0); |
| 821 | I915_WRITE(PIPEBSTAT, 0); |
Jesse Barnes | 0a3e67a | 2008-09-30 12:14:26 -0700 | [diff] [blame] | 822 | I915_WRITE(IMR, 0xffffffff); |
Eric Anholt | ed4cb41 | 2008-07-29 12:10:39 -0700 | [diff] [blame] | 823 | I915_WRITE(IER, 0x0); |
Dave Airlie | 91e3738 | 2006-02-18 15:17:04 +1100 | [diff] [blame] | 824 | |
Keith Packard | 7c46358 | 2008-11-04 02:03:27 -0800 | [diff] [blame] | 825 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
| 826 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); |
| 827 | I915_WRITE(IIR, I915_READ(IIR)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 828 | } |