Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
Auke Kok | 0abb6eb | 2006-09-27 12:53:14 -0700 | [diff] [blame] | 3 | Intel PRO/1000 Linux driver |
| 4 | Copyright(c) 1999 - 2006 Intel Corporation. |
| 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | more details. |
Auke Kok | 0abb6eb | 2006-09-27 12:53:14 -0700 | [diff] [blame] | 14 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | You should have received a copy of the GNU General Public License along with |
Auke Kok | 0abb6eb | 2006-09-27 12:53:14 -0700 | [diff] [blame] | 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | Contact Information: |
| 23 | Linux NICS <linux.nics@intel.com> |
Auke Kok | 3d41e30 | 2006-04-14 19:05:31 -0700 | [diff] [blame] | 24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 26 | |
| 27 | *******************************************************************************/ |
| 28 | |
| 29 | /* e1000_hw.c |
| 30 | * Shared functions for accessing and configuring the MAC |
| 31 | */ |
| 32 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 33 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 34 | #include "e1000_hw.h" |
| 35 | |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 36 | static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask); |
| 37 | static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask); |
| 38 | static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data); |
| 39 | static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data); |
| 40 | static int32_t e1000_get_software_semaphore(struct e1000_hw *hw); |
| 41 | static void e1000_release_software_semaphore(struct e1000_hw *hw); |
| 42 | |
| 43 | static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw); |
| 44 | static int32_t e1000_check_downshift(struct e1000_hw *hw); |
| 45 | static int32_t e1000_check_polarity(struct e1000_hw *hw, e1000_rev_polarity *polarity); |
| 46 | static void e1000_clear_hw_cntrs(struct e1000_hw *hw); |
| 47 | static void e1000_clear_vfta(struct e1000_hw *hw); |
| 48 | static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw); |
| 49 | static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up); |
| 50 | static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw); |
| 51 | static int32_t e1000_detect_gig_phy(struct e1000_hw *hw); |
| 52 | static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank); |
| 53 | static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw); |
| 54 | static int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length); |
| 55 | static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw); |
| 56 | static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw); |
| 57 | static int32_t e1000_get_software_flag(struct e1000_hw *hw); |
| 58 | static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw); |
| 59 | static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout); |
| 60 | static int32_t e1000_id_led_init(struct e1000_hw *hw); |
| 61 | static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size); |
| 62 | static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw); |
| 63 | static void e1000_init_rx_addrs(struct e1000_hw *hw); |
Jeff Kirsher | 09ae3e8 | 2006-09-27 12:53:51 -0700 | [diff] [blame] | 64 | static void e1000_initialize_hardware_bits(struct e1000_hw *hw); |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 65 | static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw); |
| 66 | static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw); |
| 67 | static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw); |
| 68 | static int32_t e1000_mng_host_if_write(struct e1000_hw *hw, uint8_t *buffer, uint16_t length, uint16_t offset, uint8_t *sum); |
| 69 | static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr); |
| 70 | static int32_t e1000_mng_write_commit(struct e1000_hw *hw); |
| 71 | static int32_t e1000_phy_ife_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); |
| 72 | static int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); |
| 73 | static int32_t e1000_read_eeprom_eerd(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); |
| 74 | static int32_t e1000_write_eeprom_eewr(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); |
| 75 | static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd); |
| 76 | static int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info); |
| 77 | static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw); |
| 78 | static int32_t e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t *data); |
| 79 | static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte); |
| 80 | static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte); |
| 81 | static int32_t e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data); |
| 82 | static int32_t e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t *data); |
| 83 | static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data); |
| 84 | static int32_t e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); |
| 85 | static int32_t e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data); |
| 86 | static void e1000_release_software_flag(struct e1000_hw *hw); |
| 87 | static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active); |
| 88 | static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active); |
| 89 | static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop); |
| 90 | static void e1000_set_pci_express_master_disable(struct e1000_hw *hw); |
| 91 | static int32_t e1000_wait_autoneg(struct e1000_hw *hw); |
| 92 | static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 93 | static int32_t e1000_set_phy_type(struct e1000_hw *hw); |
| 94 | static void e1000_phy_init_script(struct e1000_hw *hw); |
| 95 | static int32_t e1000_setup_copper_link(struct e1000_hw *hw); |
| 96 | static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw); |
| 97 | static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw); |
| 98 | static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw); |
| 99 | static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw); |
| 100 | static void e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); |
| 101 | static void e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t *ctrl); |
| 102 | static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, |
| 103 | uint16_t count); |
| 104 | static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw); |
| 105 | static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw); |
| 106 | static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset, |
| 107 | uint16_t words, uint16_t *data); |
| 108 | static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw, |
| 109 | uint16_t offset, uint16_t words, |
| 110 | uint16_t *data); |
| 111 | static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw); |
| 112 | static void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t *eecd); |
| 113 | static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t *eecd); |
| 114 | static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, |
| 115 | uint16_t count); |
| 116 | static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, |
| 117 | uint16_t phy_data); |
| 118 | static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr, |
| 119 | uint16_t *phy_data); |
| 120 | static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count); |
| 121 | static int32_t e1000_acquire_eeprom(struct e1000_hw *hw); |
| 122 | static void e1000_release_eeprom(struct e1000_hw *hw); |
| 123 | static void e1000_standby_eeprom(struct e1000_hw *hw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 124 | static int32_t e1000_set_vco_speed(struct e1000_hw *hw); |
| 125 | static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw); |
| 126 | static int32_t e1000_set_phy_mode(struct e1000_hw *hw); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 127 | static int32_t e1000_host_if_read_cookie(struct e1000_hw *hw, uint8_t *buffer); |
| 128 | static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length); |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 129 | static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, |
| 130 | uint16_t duplex); |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 131 | static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 132 | |
| 133 | /* IGP cable length table */ |
| 134 | static const |
| 135 | uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] = |
| 136 | { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, |
| 137 | 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, |
| 138 | 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, |
| 139 | 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, |
| 140 | 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, |
| 141 | 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, |
| 142 | 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, |
| 143 | 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; |
| 144 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 145 | static const |
| 146 | uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] = |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 147 | { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, |
| 148 | 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, |
| 149 | 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, |
| 150 | 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, |
| 151 | 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, |
| 152 | 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, |
| 153 | 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124, |
| 154 | 104, 109, 114, 118, 121, 124}; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 155 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 156 | /****************************************************************************** |
| 157 | * Set the phy type member in the hw struct. |
| 158 | * |
| 159 | * hw - Struct containing variables accessed by shared code |
| 160 | *****************************************************************************/ |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 161 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 162 | e1000_set_phy_type(struct e1000_hw *hw) |
| 163 | { |
| 164 | DEBUGFUNC("e1000_set_phy_type"); |
| 165 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 166 | if (hw->mac_type == e1000_undefined) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 167 | return -E1000_ERR_PHY_TYPE; |
| 168 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 169 | switch (hw->phy_id) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 170 | case M88E1000_E_PHY_ID: |
| 171 | case M88E1000_I_PHY_ID: |
| 172 | case M88E1011_I_PHY_ID: |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 173 | case M88E1111_I_PHY_ID: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 174 | hw->phy_type = e1000_phy_m88; |
| 175 | break; |
| 176 | case IGP01E1000_I_PHY_ID: |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 177 | if (hw->mac_type == e1000_82541 || |
| 178 | hw->mac_type == e1000_82541_rev_2 || |
| 179 | hw->mac_type == e1000_82547 || |
| 180 | hw->mac_type == e1000_82547_rev_2) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 181 | hw->phy_type = e1000_phy_igp; |
| 182 | break; |
| 183 | } |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 184 | case IGP03E1000_E_PHY_ID: |
| 185 | hw->phy_type = e1000_phy_igp_3; |
| 186 | break; |
| 187 | case IFE_E_PHY_ID: |
| 188 | case IFE_PLUS_E_PHY_ID: |
| 189 | case IFE_C_E_PHY_ID: |
| 190 | hw->phy_type = e1000_phy_ife; |
| 191 | break; |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 192 | case GG82563_E_PHY_ID: |
| 193 | if (hw->mac_type == e1000_80003es2lan) { |
| 194 | hw->phy_type = e1000_phy_gg82563; |
| 195 | break; |
| 196 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 197 | /* Fall Through */ |
| 198 | default: |
| 199 | /* Should never have loaded on this device */ |
| 200 | hw->phy_type = e1000_phy_undefined; |
| 201 | return -E1000_ERR_PHY_TYPE; |
| 202 | } |
| 203 | |
| 204 | return E1000_SUCCESS; |
| 205 | } |
| 206 | |
| 207 | /****************************************************************************** |
| 208 | * IGP phy init script - initializes the GbE PHY |
| 209 | * |
| 210 | * hw - Struct containing variables accessed by shared code |
| 211 | *****************************************************************************/ |
| 212 | static void |
| 213 | e1000_phy_init_script(struct e1000_hw *hw) |
| 214 | { |
| 215 | uint32_t ret_val; |
| 216 | uint16_t phy_saved_data; |
| 217 | |
| 218 | DEBUGFUNC("e1000_phy_init_script"); |
| 219 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 220 | if (hw->phy_init_script) { |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 221 | msleep(20); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 222 | |
| 223 | /* Save off the current value of register 0x2F5B to be restored at |
| 224 | * the end of this routine. */ |
| 225 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); |
| 226 | |
| 227 | /* Disabled the PHY transmitter */ |
| 228 | e1000_write_phy_reg(hw, 0x2F5B, 0x0003); |
| 229 | |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 230 | msleep(20); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 231 | |
| 232 | e1000_write_phy_reg(hw,0x0000,0x0140); |
| 233 | |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 234 | msleep(5); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 235 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 236 | switch (hw->mac_type) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 237 | case e1000_82541: |
| 238 | case e1000_82547: |
| 239 | e1000_write_phy_reg(hw, 0x1F95, 0x0001); |
| 240 | |
| 241 | e1000_write_phy_reg(hw, 0x1F71, 0xBD21); |
| 242 | |
| 243 | e1000_write_phy_reg(hw, 0x1F79, 0x0018); |
| 244 | |
| 245 | e1000_write_phy_reg(hw, 0x1F30, 0x1600); |
| 246 | |
| 247 | e1000_write_phy_reg(hw, 0x1F31, 0x0014); |
| 248 | |
| 249 | e1000_write_phy_reg(hw, 0x1F32, 0x161C); |
| 250 | |
| 251 | e1000_write_phy_reg(hw, 0x1F94, 0x0003); |
| 252 | |
| 253 | e1000_write_phy_reg(hw, 0x1F96, 0x003F); |
| 254 | |
| 255 | e1000_write_phy_reg(hw, 0x2010, 0x0008); |
| 256 | break; |
| 257 | |
| 258 | case e1000_82541_rev_2: |
| 259 | case e1000_82547_rev_2: |
| 260 | e1000_write_phy_reg(hw, 0x1F73, 0x0099); |
| 261 | break; |
| 262 | default: |
| 263 | break; |
| 264 | } |
| 265 | |
| 266 | e1000_write_phy_reg(hw, 0x0000, 0x3300); |
| 267 | |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 268 | msleep(20); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 269 | |
| 270 | /* Now enable the transmitter */ |
| 271 | e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
| 272 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 273 | if (hw->mac_type == e1000_82547) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 274 | uint16_t fused, fine, coarse; |
| 275 | |
| 276 | /* Move to analog registers page */ |
| 277 | e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); |
| 278 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 279 | if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 280 | e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused); |
| 281 | |
| 282 | fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; |
| 283 | coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; |
| 284 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 285 | if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 286 | coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; |
| 287 | fine -= IGP01E1000_ANALOG_FUSE_FINE_1; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 288 | } else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 289 | fine -= IGP01E1000_ANALOG_FUSE_FINE_10; |
| 290 | |
| 291 | fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | |
| 292 | (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | |
| 293 | (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); |
| 294 | |
| 295 | e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused); |
| 296 | e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS, |
| 297 | IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); |
| 298 | } |
| 299 | } |
| 300 | } |
| 301 | } |
| 302 | |
| 303 | /****************************************************************************** |
| 304 | * Set the mac type member in the hw struct. |
| 305 | * |
| 306 | * hw - Struct containing variables accessed by shared code |
| 307 | *****************************************************************************/ |
| 308 | int32_t |
| 309 | e1000_set_mac_type(struct e1000_hw *hw) |
| 310 | { |
Jeff Garzik | bd2371e | 2006-12-15 10:31:40 -0500 | [diff] [blame] | 311 | DEBUGFUNC("e1000_set_mac_type"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 312 | |
Jeff Garzik | bd2371e | 2006-12-15 10:31:40 -0500 | [diff] [blame] | 313 | switch (hw->device_id) { |
| 314 | case E1000_DEV_ID_82542: |
| 315 | switch (hw->revision_id) { |
| 316 | case E1000_82542_2_0_REV_ID: |
| 317 | hw->mac_type = e1000_82542_rev2_0; |
| 318 | break; |
| 319 | case E1000_82542_2_1_REV_ID: |
| 320 | hw->mac_type = e1000_82542_rev2_1; |
| 321 | break; |
| 322 | default: |
| 323 | /* Invalid 82542 revision ID */ |
| 324 | return -E1000_ERR_MAC_TYPE; |
| 325 | } |
| 326 | break; |
| 327 | case E1000_DEV_ID_82543GC_FIBER: |
| 328 | case E1000_DEV_ID_82543GC_COPPER: |
| 329 | hw->mac_type = e1000_82543; |
| 330 | break; |
| 331 | case E1000_DEV_ID_82544EI_COPPER: |
| 332 | case E1000_DEV_ID_82544EI_FIBER: |
| 333 | case E1000_DEV_ID_82544GC_COPPER: |
| 334 | case E1000_DEV_ID_82544GC_LOM: |
| 335 | hw->mac_type = e1000_82544; |
| 336 | break; |
| 337 | case E1000_DEV_ID_82540EM: |
| 338 | case E1000_DEV_ID_82540EM_LOM: |
| 339 | case E1000_DEV_ID_82540EP: |
| 340 | case E1000_DEV_ID_82540EP_LOM: |
| 341 | case E1000_DEV_ID_82540EP_LP: |
| 342 | hw->mac_type = e1000_82540; |
| 343 | break; |
| 344 | case E1000_DEV_ID_82545EM_COPPER: |
| 345 | case E1000_DEV_ID_82545EM_FIBER: |
| 346 | hw->mac_type = e1000_82545; |
| 347 | break; |
| 348 | case E1000_DEV_ID_82545GM_COPPER: |
| 349 | case E1000_DEV_ID_82545GM_FIBER: |
| 350 | case E1000_DEV_ID_82545GM_SERDES: |
| 351 | hw->mac_type = e1000_82545_rev_3; |
| 352 | break; |
| 353 | case E1000_DEV_ID_82546EB_COPPER: |
| 354 | case E1000_DEV_ID_82546EB_FIBER: |
| 355 | case E1000_DEV_ID_82546EB_QUAD_COPPER: |
| 356 | hw->mac_type = e1000_82546; |
| 357 | break; |
| 358 | case E1000_DEV_ID_82546GB_COPPER: |
| 359 | case E1000_DEV_ID_82546GB_FIBER: |
| 360 | case E1000_DEV_ID_82546GB_SERDES: |
| 361 | case E1000_DEV_ID_82546GB_PCIE: |
| 362 | case E1000_DEV_ID_82546GB_QUAD_COPPER: |
| 363 | case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3: |
| 364 | hw->mac_type = e1000_82546_rev_3; |
| 365 | break; |
| 366 | case E1000_DEV_ID_82541EI: |
| 367 | case E1000_DEV_ID_82541EI_MOBILE: |
| 368 | case E1000_DEV_ID_82541ER_LOM: |
| 369 | hw->mac_type = e1000_82541; |
| 370 | break; |
| 371 | case E1000_DEV_ID_82541ER: |
| 372 | case E1000_DEV_ID_82541GI: |
| 373 | case E1000_DEV_ID_82541GI_LF: |
| 374 | case E1000_DEV_ID_82541GI_MOBILE: |
| 375 | hw->mac_type = e1000_82541_rev_2; |
| 376 | break; |
| 377 | case E1000_DEV_ID_82547EI: |
| 378 | case E1000_DEV_ID_82547EI_MOBILE: |
| 379 | hw->mac_type = e1000_82547; |
| 380 | break; |
| 381 | case E1000_DEV_ID_82547GI: |
| 382 | hw->mac_type = e1000_82547_rev_2; |
| 383 | break; |
| 384 | case E1000_DEV_ID_82571EB_COPPER: |
| 385 | case E1000_DEV_ID_82571EB_FIBER: |
| 386 | case E1000_DEV_ID_82571EB_SERDES: |
Auke Kok | ce57a02 | 2007-08-09 14:09:34 -0700 | [diff] [blame^] | 387 | case E1000_DEV_ID_82571EB_SERDES_DUAL: |
| 388 | case E1000_DEV_ID_82571EB_SERDES_QUAD: |
Jeff Garzik | bd2371e | 2006-12-15 10:31:40 -0500 | [diff] [blame] | 389 | case E1000_DEV_ID_82571EB_QUAD_COPPER: |
Auke Kok | ce57a02 | 2007-08-09 14:09:34 -0700 | [diff] [blame^] | 390 | case E1000_DEV_ID_82571EB_QUAD_FIBER: |
Jeff Garzik | bd2371e | 2006-12-15 10:31:40 -0500 | [diff] [blame] | 391 | case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE: |
| 392 | hw->mac_type = e1000_82571; |
| 393 | break; |
| 394 | case E1000_DEV_ID_82572EI_COPPER: |
| 395 | case E1000_DEV_ID_82572EI_FIBER: |
| 396 | case E1000_DEV_ID_82572EI_SERDES: |
| 397 | case E1000_DEV_ID_82572EI: |
| 398 | hw->mac_type = e1000_82572; |
| 399 | break; |
| 400 | case E1000_DEV_ID_82573E: |
| 401 | case E1000_DEV_ID_82573E_IAMT: |
| 402 | case E1000_DEV_ID_82573L: |
| 403 | hw->mac_type = e1000_82573; |
| 404 | break; |
| 405 | case E1000_DEV_ID_80003ES2LAN_COPPER_SPT: |
| 406 | case E1000_DEV_ID_80003ES2LAN_SERDES_SPT: |
| 407 | case E1000_DEV_ID_80003ES2LAN_COPPER_DPT: |
| 408 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: |
| 409 | hw->mac_type = e1000_80003es2lan; |
| 410 | break; |
| 411 | case E1000_DEV_ID_ICH8_IGP_M_AMT: |
| 412 | case E1000_DEV_ID_ICH8_IGP_AMT: |
| 413 | case E1000_DEV_ID_ICH8_IGP_C: |
| 414 | case E1000_DEV_ID_ICH8_IFE: |
| 415 | case E1000_DEV_ID_ICH8_IFE_GT: |
| 416 | case E1000_DEV_ID_ICH8_IFE_G: |
| 417 | case E1000_DEV_ID_ICH8_IGP_M: |
| 418 | hw->mac_type = e1000_ich8lan; |
| 419 | break; |
| 420 | default: |
| 421 | /* Should never have loaded on this device */ |
| 422 | return -E1000_ERR_MAC_TYPE; |
| 423 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 424 | |
Jeff Garzik | bd2371e | 2006-12-15 10:31:40 -0500 | [diff] [blame] | 425 | switch (hw->mac_type) { |
| 426 | case e1000_ich8lan: |
| 427 | hw->swfwhw_semaphore_present = TRUE; |
| 428 | hw->asf_firmware_present = TRUE; |
| 429 | break; |
| 430 | case e1000_80003es2lan: |
| 431 | hw->swfw_sync_present = TRUE; |
| 432 | /* fall through */ |
| 433 | case e1000_82571: |
| 434 | case e1000_82572: |
| 435 | case e1000_82573: |
| 436 | hw->eeprom_semaphore_present = TRUE; |
| 437 | /* fall through */ |
| 438 | case e1000_82541: |
| 439 | case e1000_82547: |
| 440 | case e1000_82541_rev_2: |
| 441 | case e1000_82547_rev_2: |
| 442 | hw->asf_firmware_present = TRUE; |
| 443 | break; |
| 444 | default: |
| 445 | break; |
| 446 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 447 | |
Jeff Garzik | 167fb28 | 2006-12-15 10:41:15 -0500 | [diff] [blame] | 448 | /* The 82543 chip does not count tx_carrier_errors properly in |
| 449 | * FD mode |
| 450 | */ |
| 451 | if (hw->mac_type == e1000_82543) |
| 452 | hw->bad_tx_carr_stats_fd = TRUE; |
| 453 | |
Jeff Garzik | 0fccd0e | 2006-12-15 10:56:10 -0500 | [diff] [blame] | 454 | /* capable of receiving management packets to the host */ |
| 455 | if (hw->mac_type >= e1000_82571) |
| 456 | hw->has_manc2h = TRUE; |
| 457 | |
Jeff Garzik | bb8e331 | 2006-12-15 11:06:17 -0500 | [diff] [blame] | 458 | /* In rare occasions, ESB2 systems would end up started without |
| 459 | * the RX unit being turned on. |
| 460 | */ |
| 461 | if (hw->mac_type == e1000_80003es2lan) |
| 462 | hw->rx_needs_kicking = TRUE; |
| 463 | |
Jeff Garzik | 15e376b | 2006-12-15 11:16:33 -0500 | [diff] [blame] | 464 | if (hw->mac_type > e1000_82544) |
| 465 | hw->has_smbus = TRUE; |
| 466 | |
Jeff Garzik | bd2371e | 2006-12-15 10:31:40 -0500 | [diff] [blame] | 467 | return E1000_SUCCESS; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 468 | } |
| 469 | |
| 470 | /***************************************************************************** |
| 471 | * Set media type and TBI compatibility. |
| 472 | * |
| 473 | * hw - Struct containing variables accessed by shared code |
| 474 | * **************************************************************************/ |
| 475 | void |
| 476 | e1000_set_media_type(struct e1000_hw *hw) |
| 477 | { |
| 478 | uint32_t status; |
| 479 | |
| 480 | DEBUGFUNC("e1000_set_media_type"); |
| 481 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 482 | if (hw->mac_type != e1000_82543) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 483 | /* tbi_compatibility is only valid on 82543 */ |
| 484 | hw->tbi_compatibility_en = FALSE; |
| 485 | } |
| 486 | |
| 487 | switch (hw->device_id) { |
| 488 | case E1000_DEV_ID_82545GM_SERDES: |
| 489 | case E1000_DEV_ID_82546GB_SERDES: |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 490 | case E1000_DEV_ID_82571EB_SERDES: |
Auke Kok | ce57a02 | 2007-08-09 14:09:34 -0700 | [diff] [blame^] | 491 | case E1000_DEV_ID_82571EB_SERDES_DUAL: |
| 492 | case E1000_DEV_ID_82571EB_SERDES_QUAD: |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 493 | case E1000_DEV_ID_82572EI_SERDES: |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 494 | case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 495 | hw->media_type = e1000_media_type_internal_serdes; |
| 496 | break; |
| 497 | default: |
Malli Chilakala | 3893d54 | 2005-06-17 17:44:49 -0700 | [diff] [blame] | 498 | switch (hw->mac_type) { |
| 499 | case e1000_82542_rev2_0: |
| 500 | case e1000_82542_rev2_1: |
| 501 | hw->media_type = e1000_media_type_fiber; |
| 502 | break; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 503 | case e1000_ich8lan: |
Malli Chilakala | 3893d54 | 2005-06-17 17:44:49 -0700 | [diff] [blame] | 504 | case e1000_82573: |
| 505 | /* The STATUS_TBIMODE bit is reserved or reused for the this |
| 506 | * device. |
| 507 | */ |
| 508 | hw->media_type = e1000_media_type_copper; |
| 509 | break; |
| 510 | default: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 511 | status = E1000_READ_REG(hw, STATUS); |
Malli Chilakala | 3893d54 | 2005-06-17 17:44:49 -0700 | [diff] [blame] | 512 | if (status & E1000_STATUS_TBIMODE) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 513 | hw->media_type = e1000_media_type_fiber; |
| 514 | /* tbi_compatibility not valid on fiber */ |
| 515 | hw->tbi_compatibility_en = FALSE; |
| 516 | } else { |
| 517 | hw->media_type = e1000_media_type_copper; |
| 518 | } |
Malli Chilakala | 3893d54 | 2005-06-17 17:44:49 -0700 | [diff] [blame] | 519 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 520 | } |
| 521 | } |
| 522 | } |
| 523 | |
| 524 | /****************************************************************************** |
| 525 | * Reset the transmit and receive units; mask and clear all interrupts. |
| 526 | * |
| 527 | * hw - Struct containing variables accessed by shared code |
| 528 | *****************************************************************************/ |
| 529 | int32_t |
| 530 | e1000_reset_hw(struct e1000_hw *hw) |
| 531 | { |
| 532 | uint32_t ctrl; |
| 533 | uint32_t ctrl_ext; |
| 534 | uint32_t icr; |
| 535 | uint32_t manc; |
| 536 | uint32_t led_ctrl; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 537 | uint32_t timeout; |
| 538 | uint32_t extcnf_ctrl; |
| 539 | int32_t ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 540 | |
| 541 | DEBUGFUNC("e1000_reset_hw"); |
| 542 | |
| 543 | /* For 82542 (rev 2.0), disable MWI before issuing a device reset */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 544 | if (hw->mac_type == e1000_82542_rev2_0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 545 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); |
| 546 | e1000_pci_clear_mwi(hw); |
| 547 | } |
| 548 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 549 | if (hw->bus_type == e1000_bus_type_pci_express) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 550 | /* Prevent the PCI-E bus from sticking if there is no TLP connection |
| 551 | * on the last TLP read/write transaction when MAC is reset. |
| 552 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 553 | if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 554 | DEBUGOUT("PCI-E Master disable polling has failed.\n"); |
| 555 | } |
| 556 | } |
| 557 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 558 | /* Clear interrupt mask to stop board from generating interrupts */ |
| 559 | DEBUGOUT("Masking off all interrupts\n"); |
| 560 | E1000_WRITE_REG(hw, IMC, 0xffffffff); |
| 561 | |
| 562 | /* Disable the Transmit and Receive units. Then delay to allow |
| 563 | * any pending transactions to complete before we hit the MAC with |
| 564 | * the global reset. |
| 565 | */ |
| 566 | E1000_WRITE_REG(hw, RCTL, 0); |
| 567 | E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP); |
| 568 | E1000_WRITE_FLUSH(hw); |
| 569 | |
| 570 | /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */ |
| 571 | hw->tbi_compatibility_on = FALSE; |
| 572 | |
| 573 | /* Delay to allow any outstanding PCI transactions to complete before |
| 574 | * resetting the device |
| 575 | */ |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 576 | msleep(10); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 577 | |
| 578 | ctrl = E1000_READ_REG(hw, CTRL); |
| 579 | |
| 580 | /* Must reset the PHY before resetting the MAC */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 581 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 582 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST)); |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 583 | msleep(5); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 584 | } |
| 585 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 586 | /* Must acquire the MDIO ownership before MAC reset. |
| 587 | * Ownership defaults to firmware after a reset. */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 588 | if (hw->mac_type == e1000_82573) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 589 | timeout = 10; |
| 590 | |
| 591 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); |
| 592 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; |
| 593 | |
| 594 | do { |
| 595 | E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); |
| 596 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); |
| 597 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 598 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 599 | break; |
| 600 | else |
| 601 | extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP; |
| 602 | |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 603 | msleep(2); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 604 | timeout--; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 605 | } while (timeout); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 606 | } |
| 607 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 608 | /* Workaround for ICH8 bit corruption issue in FIFO memory */ |
| 609 | if (hw->mac_type == e1000_ich8lan) { |
| 610 | /* Set Tx and Rx buffer allocation to 8k apiece. */ |
| 611 | E1000_WRITE_REG(hw, PBA, E1000_PBA_8K); |
| 612 | /* Set Packet Buffer Size to 16k. */ |
| 613 | E1000_WRITE_REG(hw, PBS, E1000_PBS_16K); |
| 614 | } |
| 615 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 616 | /* Issue a global reset to the MAC. This will reset the chip's |
| 617 | * transmit, receive, DMA, and link units. It will not effect |
| 618 | * the current PCI configuration. The global reset bit is self- |
| 619 | * clearing, and should clear within a microsecond. |
| 620 | */ |
| 621 | DEBUGOUT("Issuing a global reset to MAC\n"); |
| 622 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 623 | switch (hw->mac_type) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 624 | case e1000_82544: |
| 625 | case e1000_82540: |
| 626 | case e1000_82545: |
| 627 | case e1000_82546: |
| 628 | case e1000_82541: |
| 629 | case e1000_82541_rev_2: |
| 630 | /* These controllers can't ack the 64-bit write when issuing the |
| 631 | * reset, so use IO-mapping as a workaround to issue the reset */ |
| 632 | E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST)); |
| 633 | break; |
| 634 | case e1000_82545_rev_3: |
| 635 | case e1000_82546_rev_3: |
| 636 | /* Reset is performed on a shadow of the control register */ |
| 637 | E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST)); |
| 638 | break; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 639 | case e1000_ich8lan: |
| 640 | if (!hw->phy_reset_disable && |
| 641 | e1000_check_phy_reset_block(hw) == E1000_SUCCESS) { |
| 642 | /* e1000_ich8lan PHY HW reset requires MAC CORE reset |
| 643 | * at the same time to make sure the interface between |
| 644 | * MAC and the external PHY is reset. |
| 645 | */ |
| 646 | ctrl |= E1000_CTRL_PHY_RST; |
| 647 | } |
| 648 | |
| 649 | e1000_get_software_flag(hw); |
| 650 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 651 | msleep(5); |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 652 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 653 | default: |
| 654 | E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); |
| 655 | break; |
| 656 | } |
| 657 | |
| 658 | /* After MAC reset, force reload of EEPROM to restore power-on settings to |
| 659 | * device. Later controllers reload the EEPROM automatically, so just wait |
| 660 | * for reload to complete. |
| 661 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 662 | switch (hw->mac_type) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 663 | case e1000_82542_rev2_0: |
| 664 | case e1000_82542_rev2_1: |
| 665 | case e1000_82543: |
| 666 | case e1000_82544: |
| 667 | /* Wait for reset to complete */ |
| 668 | udelay(10); |
| 669 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
| 670 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
| 671 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
| 672 | E1000_WRITE_FLUSH(hw); |
| 673 | /* Wait for EEPROM reload */ |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 674 | msleep(2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 675 | break; |
| 676 | case e1000_82541: |
| 677 | case e1000_82541_rev_2: |
| 678 | case e1000_82547: |
| 679 | case e1000_82547_rev_2: |
| 680 | /* Wait for EEPROM reload */ |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 681 | msleep(20); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 682 | break; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 683 | case e1000_82573: |
Jeff Kirsher | fd80324 | 2005-12-13 00:06:22 -0500 | [diff] [blame] | 684 | if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { |
| 685 | udelay(10); |
| 686 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
| 687 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
| 688 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
| 689 | E1000_WRITE_FLUSH(hw); |
| 690 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 691 | /* fall through */ |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 692 | default: |
| 693 | /* Auto read done will delay 5ms or poll based on mac type */ |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 694 | ret_val = e1000_get_auto_rd_done(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 695 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 696 | return ret_val; |
| 697 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 698 | } |
| 699 | |
| 700 | /* Disable HW ARPs on ASF enabled adapters */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 701 | if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 702 | manc = E1000_READ_REG(hw, MANC); |
| 703 | manc &= ~(E1000_MANC_ARP_EN); |
| 704 | E1000_WRITE_REG(hw, MANC, manc); |
| 705 | } |
| 706 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 707 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 708 | e1000_phy_init_script(hw); |
| 709 | |
| 710 | /* Configure activity LED after PHY reset */ |
| 711 | led_ctrl = E1000_READ_REG(hw, LEDCTL); |
| 712 | led_ctrl &= IGP_ACTIVITY_LED_MASK; |
| 713 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
| 714 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); |
| 715 | } |
| 716 | |
| 717 | /* Clear interrupt mask to stop board from generating interrupts */ |
| 718 | DEBUGOUT("Masking off all interrupts\n"); |
| 719 | E1000_WRITE_REG(hw, IMC, 0xffffffff); |
| 720 | |
| 721 | /* Clear any pending interrupt events. */ |
| 722 | icr = E1000_READ_REG(hw, ICR); |
| 723 | |
| 724 | /* If MWI was previously enabled, reenable it. */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 725 | if (hw->mac_type == e1000_82542_rev2_0) { |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 726 | if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 727 | e1000_pci_set_mwi(hw); |
| 728 | } |
| 729 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 730 | if (hw->mac_type == e1000_ich8lan) { |
| 731 | uint32_t kab = E1000_READ_REG(hw, KABGTXD); |
| 732 | kab |= E1000_KABGTXD_BGSQLBIAS; |
| 733 | E1000_WRITE_REG(hw, KABGTXD, kab); |
| 734 | } |
| 735 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 736 | return E1000_SUCCESS; |
| 737 | } |
| 738 | |
| 739 | /****************************************************************************** |
Jeff Kirsher | 09ae3e8 | 2006-09-27 12:53:51 -0700 | [diff] [blame] | 740 | * |
| 741 | * Initialize a number of hardware-dependent bits |
| 742 | * |
| 743 | * hw: Struct containing variables accessed by shared code |
| 744 | * |
| 745 | * This function contains hardware limitation workarounds for PCI-E adapters |
| 746 | * |
| 747 | *****************************************************************************/ |
| 748 | static void |
| 749 | e1000_initialize_hardware_bits(struct e1000_hw *hw) |
| 750 | { |
| 751 | if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) { |
| 752 | /* Settings common to all PCI-express silicon */ |
| 753 | uint32_t reg_ctrl, reg_ctrl_ext; |
| 754 | uint32_t reg_tarc0, reg_tarc1; |
| 755 | uint32_t reg_tctl; |
| 756 | uint32_t reg_txdctl, reg_txdctl1; |
| 757 | |
| 758 | /* link autonegotiation/sync workarounds */ |
| 759 | reg_tarc0 = E1000_READ_REG(hw, TARC0); |
| 760 | reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); |
| 761 | |
| 762 | /* Enable not-done TX descriptor counting */ |
| 763 | reg_txdctl = E1000_READ_REG(hw, TXDCTL); |
| 764 | reg_txdctl |= E1000_TXDCTL_COUNT_DESC; |
| 765 | E1000_WRITE_REG(hw, TXDCTL, reg_txdctl); |
| 766 | reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1); |
| 767 | reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC; |
| 768 | E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1); |
| 769 | |
| 770 | switch (hw->mac_type) { |
| 771 | case e1000_82571: |
| 772 | case e1000_82572: |
| 773 | /* Clear PHY TX compatible mode bits */ |
| 774 | reg_tarc1 = E1000_READ_REG(hw, TARC1); |
| 775 | reg_tarc1 &= ~((1 << 30)|(1 << 29)); |
| 776 | |
| 777 | /* link autonegotiation/sync workarounds */ |
| 778 | reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23)); |
| 779 | |
| 780 | /* TX ring control fixes */ |
| 781 | reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24)); |
| 782 | |
| 783 | /* Multiple read bit is reversed polarity */ |
| 784 | reg_tctl = E1000_READ_REG(hw, TCTL); |
| 785 | if (reg_tctl & E1000_TCTL_MULR) |
| 786 | reg_tarc1 &= ~(1 << 28); |
| 787 | else |
| 788 | reg_tarc1 |= (1 << 28); |
| 789 | |
| 790 | E1000_WRITE_REG(hw, TARC1, reg_tarc1); |
| 791 | break; |
| 792 | case e1000_82573: |
| 793 | reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
| 794 | reg_ctrl_ext &= ~(1 << 23); |
| 795 | reg_ctrl_ext |= (1 << 22); |
| 796 | |
| 797 | /* TX byte count fix */ |
| 798 | reg_ctrl = E1000_READ_REG(hw, CTRL); |
| 799 | reg_ctrl &= ~(1 << 29); |
| 800 | |
| 801 | E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); |
| 802 | E1000_WRITE_REG(hw, CTRL, reg_ctrl); |
| 803 | break; |
| 804 | case e1000_80003es2lan: |
| 805 | /* improve small packet performace for fiber/serdes */ |
| 806 | if ((hw->media_type == e1000_media_type_fiber) || |
| 807 | (hw->media_type == e1000_media_type_internal_serdes)) { |
| 808 | reg_tarc0 &= ~(1 << 20); |
| 809 | } |
| 810 | |
| 811 | /* Multiple read bit is reversed polarity */ |
| 812 | reg_tctl = E1000_READ_REG(hw, TCTL); |
| 813 | reg_tarc1 = E1000_READ_REG(hw, TARC1); |
| 814 | if (reg_tctl & E1000_TCTL_MULR) |
| 815 | reg_tarc1 &= ~(1 << 28); |
| 816 | else |
| 817 | reg_tarc1 |= (1 << 28); |
| 818 | |
| 819 | E1000_WRITE_REG(hw, TARC1, reg_tarc1); |
| 820 | break; |
| 821 | case e1000_ich8lan: |
| 822 | /* Reduce concurrent DMA requests to 3 from 4 */ |
| 823 | if ((hw->revision_id < 3) || |
| 824 | ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && |
| 825 | (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) |
| 826 | reg_tarc0 |= ((1 << 29)|(1 << 28)); |
| 827 | |
| 828 | reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
| 829 | reg_ctrl_ext |= (1 << 22); |
| 830 | E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext); |
| 831 | |
| 832 | /* workaround TX hang with TSO=on */ |
| 833 | reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)); |
| 834 | |
| 835 | /* Multiple read bit is reversed polarity */ |
| 836 | reg_tctl = E1000_READ_REG(hw, TCTL); |
| 837 | reg_tarc1 = E1000_READ_REG(hw, TARC1); |
| 838 | if (reg_tctl & E1000_TCTL_MULR) |
| 839 | reg_tarc1 &= ~(1 << 28); |
| 840 | else |
| 841 | reg_tarc1 |= (1 << 28); |
| 842 | |
| 843 | /* workaround TX hang with TSO=on */ |
| 844 | reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24)); |
| 845 | |
| 846 | E1000_WRITE_REG(hw, TARC1, reg_tarc1); |
| 847 | break; |
| 848 | default: |
| 849 | break; |
| 850 | } |
| 851 | |
| 852 | E1000_WRITE_REG(hw, TARC0, reg_tarc0); |
| 853 | } |
| 854 | } |
| 855 | |
| 856 | /****************************************************************************** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 857 | * Performs basic configuration of the adapter. |
| 858 | * |
| 859 | * hw - Struct containing variables accessed by shared code |
| 860 | * |
| 861 | * Assumes that the controller has previously been reset and is in a |
| 862 | * post-reset uninitialized state. Initializes the receive address registers, |
| 863 | * multicast table, and VLAN filter table. Calls routines to setup link |
| 864 | * configuration and flow control settings. Clears all on-chip counters. Leaves |
| 865 | * the transmit and receive units disabled and uninitialized. |
| 866 | *****************************************************************************/ |
| 867 | int32_t |
| 868 | e1000_init_hw(struct e1000_hw *hw) |
| 869 | { |
| 870 | uint32_t ctrl; |
| 871 | uint32_t i; |
| 872 | int32_t ret_val; |
| 873 | uint16_t pcix_cmd_word; |
| 874 | uint16_t pcix_stat_hi_word; |
| 875 | uint16_t cmd_mmrbc; |
| 876 | uint16_t stat_mmrbc; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 877 | uint32_t mta_size; |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 878 | uint32_t reg_data; |
Jeff Kirsher | b7ee49d | 2006-01-12 16:51:21 -0800 | [diff] [blame] | 879 | uint32_t ctrl_ext; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 880 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 881 | DEBUGFUNC("e1000_init_hw"); |
| 882 | |
Jeff Kirsher | 7820d42 | 2006-08-16 13:39:00 -0700 | [diff] [blame] | 883 | /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ |
Jeff Kirsher | 09ae3e8 | 2006-09-27 12:53:51 -0700 | [diff] [blame] | 884 | if ((hw->mac_type == e1000_ich8lan) && |
| 885 | ((hw->revision_id < 3) || |
| 886 | ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && |
| 887 | (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { |
| 888 | reg_data = E1000_READ_REG(hw, STATUS); |
| 889 | reg_data &= ~0x80000000; |
| 890 | E1000_WRITE_REG(hw, STATUS, reg_data); |
Jeff Kirsher | 7820d42 | 2006-08-16 13:39:00 -0700 | [diff] [blame] | 891 | } |
| 892 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 893 | /* Initialize Identification LED */ |
| 894 | ret_val = e1000_id_led_init(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 895 | if (ret_val) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 896 | DEBUGOUT("Error Initializing Identification LED\n"); |
| 897 | return ret_val; |
| 898 | } |
| 899 | |
| 900 | /* Set the media type and TBI compatibility */ |
| 901 | e1000_set_media_type(hw); |
| 902 | |
Jeff Kirsher | 09ae3e8 | 2006-09-27 12:53:51 -0700 | [diff] [blame] | 903 | /* Must be called after e1000_set_media_type because media_type is used */ |
| 904 | e1000_initialize_hardware_bits(hw); |
| 905 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 906 | /* Disabling VLAN filtering. */ |
| 907 | DEBUGOUT("Initializing the IEEE VLAN\n"); |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 908 | /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */ |
| 909 | if (hw->mac_type != e1000_ich8lan) { |
| 910 | if (hw->mac_type < e1000_82545_rev_3) |
| 911 | E1000_WRITE_REG(hw, VET, 0); |
| 912 | e1000_clear_vfta(hw); |
| 913 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 914 | |
| 915 | /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 916 | if (hw->mac_type == e1000_82542_rev2_0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 917 | DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); |
| 918 | e1000_pci_clear_mwi(hw); |
| 919 | E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST); |
| 920 | E1000_WRITE_FLUSH(hw); |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 921 | msleep(5); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 922 | } |
| 923 | |
| 924 | /* Setup the receive address. This involves initializing all of the Receive |
| 925 | * Address Registers (RARs 0 - 15). |
| 926 | */ |
| 927 | e1000_init_rx_addrs(hw); |
| 928 | |
| 929 | /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 930 | if (hw->mac_type == e1000_82542_rev2_0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 931 | E1000_WRITE_REG(hw, RCTL, 0); |
| 932 | E1000_WRITE_FLUSH(hw); |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 933 | msleep(1); |
| 934 | if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 935 | e1000_pci_set_mwi(hw); |
| 936 | } |
| 937 | |
| 938 | /* Zero out the Multicast HASH table */ |
| 939 | DEBUGOUT("Zeroing the MTA\n"); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 940 | mta_size = E1000_MC_TBL_SIZE; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 941 | if (hw->mac_type == e1000_ich8lan) |
| 942 | mta_size = E1000_MC_TBL_SIZE_ICH8LAN; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 943 | for (i = 0; i < mta_size; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 944 | E1000_WRITE_REG_ARRAY(hw, MTA, i, 0); |
Auke Kok | 4ca213a | 2006-06-27 09:07:08 -0700 | [diff] [blame] | 945 | /* use write flush to prevent Memory Write Block (MWB) from |
| 946 | * occuring when accessing our register space */ |
| 947 | E1000_WRITE_FLUSH(hw); |
| 948 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 949 | |
| 950 | /* Set the PCI priority bit correctly in the CTRL register. This |
| 951 | * determines if the adapter gives priority to receives, or if it |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 952 | * gives equal priority to transmits and receives. Valid only on |
| 953 | * 82542 and 82543 silicon. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 954 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 955 | if (hw->dma_fairness && hw->mac_type <= e1000_82543) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 956 | ctrl = E1000_READ_REG(hw, CTRL); |
| 957 | E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR); |
| 958 | } |
| 959 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 960 | switch (hw->mac_type) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 961 | case e1000_82545_rev_3: |
| 962 | case e1000_82546_rev_3: |
| 963 | break; |
| 964 | default: |
| 965 | /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 966 | if (hw->bus_type == e1000_bus_type_pcix) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 967 | e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word); |
| 968 | e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, |
| 969 | &pcix_stat_hi_word); |
| 970 | cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >> |
| 971 | PCIX_COMMAND_MMRBC_SHIFT; |
| 972 | stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >> |
| 973 | PCIX_STATUS_HI_MMRBC_SHIFT; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 974 | if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 975 | stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 976 | if (cmd_mmrbc > stat_mmrbc) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 977 | pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK; |
| 978 | pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT; |
| 979 | e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, |
| 980 | &pcix_cmd_word); |
| 981 | } |
| 982 | } |
| 983 | break; |
| 984 | } |
| 985 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 986 | /* More time needed for PHY to initialize */ |
| 987 | if (hw->mac_type == e1000_ich8lan) |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 988 | msleep(15); |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 989 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 990 | /* Call a subroutine to configure the link and setup flow control. */ |
| 991 | ret_val = e1000_setup_link(hw); |
| 992 | |
| 993 | /* Set the transmit descriptor write-back policy */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 994 | if (hw->mac_type > e1000_82544) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 995 | ctrl = E1000_READ_REG(hw, TXDCTL); |
| 996 | ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; |
| 997 | E1000_WRITE_REG(hw, TXDCTL, ctrl); |
| 998 | } |
| 999 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1000 | if (hw->mac_type == e1000_82573) { |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 1001 | e1000_enable_tx_pkt_filtering(hw); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1002 | } |
| 1003 | |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 1004 | switch (hw->mac_type) { |
| 1005 | default: |
| 1006 | break; |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 1007 | case e1000_80003es2lan: |
| 1008 | /* Enable retransmit on late collisions */ |
| 1009 | reg_data = E1000_READ_REG(hw, TCTL); |
| 1010 | reg_data |= E1000_TCTL_RTLC; |
| 1011 | E1000_WRITE_REG(hw, TCTL, reg_data); |
| 1012 | |
| 1013 | /* Configure Gigabit Carry Extend Padding */ |
| 1014 | reg_data = E1000_READ_REG(hw, TCTL_EXT); |
| 1015 | reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; |
| 1016 | reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX; |
| 1017 | E1000_WRITE_REG(hw, TCTL_EXT, reg_data); |
| 1018 | |
| 1019 | /* Configure Transmit Inter-Packet Gap */ |
| 1020 | reg_data = E1000_READ_REG(hw, TIPG); |
| 1021 | reg_data &= ~E1000_TIPG_IPGT_MASK; |
| 1022 | reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; |
| 1023 | E1000_WRITE_REG(hw, TIPG, reg_data); |
| 1024 | |
| 1025 | reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001); |
| 1026 | reg_data &= ~0x00100000; |
| 1027 | E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data); |
| 1028 | /* Fall through */ |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 1029 | case e1000_82571: |
Mallikarjuna R Chilakala | a7990ba | 2005-10-04 07:08:19 -0400 | [diff] [blame] | 1030 | case e1000_82572: |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 1031 | case e1000_ich8lan: |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 1032 | ctrl = E1000_READ_REG(hw, TXDCTL1); |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 1033 | ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB; |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 1034 | E1000_WRITE_REG(hw, TXDCTL1, ctrl); |
| 1035 | break; |
| 1036 | } |
| 1037 | |
| 1038 | |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 1039 | if (hw->mac_type == e1000_82573) { |
| 1040 | uint32_t gcr = E1000_READ_REG(hw, GCR); |
| 1041 | gcr |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX; |
| 1042 | E1000_WRITE_REG(hw, GCR, gcr); |
| 1043 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1044 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1045 | /* Clear all of the statistics registers (clear on read). It is |
| 1046 | * important that we do this after we have tried to establish link |
| 1047 | * because the symbol error count will increment wildly if there |
| 1048 | * is no link. |
| 1049 | */ |
| 1050 | e1000_clear_hw_cntrs(hw); |
| 1051 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 1052 | /* ICH8 No-snoop bits are opposite polarity. |
| 1053 | * Set to snoop by default after reset. */ |
| 1054 | if (hw->mac_type == e1000_ich8lan) |
| 1055 | e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL); |
| 1056 | |
Jeff Kirsher | b7ee49d | 2006-01-12 16:51:21 -0800 | [diff] [blame] | 1057 | if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || |
| 1058 | hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { |
| 1059 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
| 1060 | /* Relaxed ordering must be disabled to avoid a parity |
| 1061 | * error crash in a PCI slot. */ |
| 1062 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS; |
| 1063 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
| 1064 | } |
| 1065 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1066 | return ret_val; |
| 1067 | } |
| 1068 | |
| 1069 | /****************************************************************************** |
| 1070 | * Adjust SERDES output amplitude based on EEPROM setting. |
| 1071 | * |
| 1072 | * hw - Struct containing variables accessed by shared code. |
| 1073 | *****************************************************************************/ |
| 1074 | static int32_t |
| 1075 | e1000_adjust_serdes_amplitude(struct e1000_hw *hw) |
| 1076 | { |
| 1077 | uint16_t eeprom_data; |
| 1078 | int32_t ret_val; |
| 1079 | |
| 1080 | DEBUGFUNC("e1000_adjust_serdes_amplitude"); |
| 1081 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1082 | if (hw->media_type != e1000_media_type_internal_serdes) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1083 | return E1000_SUCCESS; |
| 1084 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1085 | switch (hw->mac_type) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1086 | case e1000_82545_rev_3: |
| 1087 | case e1000_82546_rev_3: |
| 1088 | break; |
| 1089 | default: |
| 1090 | return E1000_SUCCESS; |
| 1091 | } |
| 1092 | |
| 1093 | ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data); |
| 1094 | if (ret_val) { |
| 1095 | return ret_val; |
| 1096 | } |
| 1097 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1098 | if (eeprom_data != EEPROM_RESERVED_WORD) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1099 | /* Adjust SERDES output amplitude only. */ |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 1100 | eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1101 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1102 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1103 | return ret_val; |
| 1104 | } |
| 1105 | |
| 1106 | return E1000_SUCCESS; |
| 1107 | } |
| 1108 | |
| 1109 | /****************************************************************************** |
| 1110 | * Configures flow control and link settings. |
| 1111 | * |
| 1112 | * hw - Struct containing variables accessed by shared code |
| 1113 | * |
| 1114 | * Determines which flow control settings to use. Calls the apropriate media- |
| 1115 | * specific link configuration function. Configures the flow control settings. |
| 1116 | * Assuming the adapter has a valid link partner, a valid link should be |
| 1117 | * established. Assumes the hardware has previously been reset and the |
| 1118 | * transmitter and receiver are not enabled. |
| 1119 | *****************************************************************************/ |
| 1120 | int32_t |
| 1121 | e1000_setup_link(struct e1000_hw *hw) |
| 1122 | { |
| 1123 | uint32_t ctrl_ext; |
| 1124 | int32_t ret_val; |
| 1125 | uint16_t eeprom_data; |
| 1126 | |
| 1127 | DEBUGFUNC("e1000_setup_link"); |
| 1128 | |
Jeff Kirsher | 526f995 | 2006-01-12 16:50:46 -0800 | [diff] [blame] | 1129 | /* In the case of the phy reset being blocked, we already have a link. |
| 1130 | * We do not have to set it up again. */ |
| 1131 | if (e1000_check_phy_reset_block(hw)) |
| 1132 | return E1000_SUCCESS; |
| 1133 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1134 | /* Read and store word 0x0F of the EEPROM. This word contains bits |
| 1135 | * that determine the hardware's default PAUSE (flow control) mode, |
| 1136 | * a bit that determines whether the HW defaults to enabling or |
| 1137 | * disabling auto-negotiation, and the direction of the |
| 1138 | * SW defined pins. If there is no SW over-ride of the flow |
| 1139 | * control setting, then the variable hw->fc will |
| 1140 | * be initialized based on a value in the EEPROM. |
| 1141 | */ |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 1142 | if (hw->fc == E1000_FC_DEFAULT) { |
Jeff Kirsher | fd80324 | 2005-12-13 00:06:22 -0500 | [diff] [blame] | 1143 | switch (hw->mac_type) { |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 1144 | case e1000_ich8lan: |
Jeff Kirsher | fd80324 | 2005-12-13 00:06:22 -0500 | [diff] [blame] | 1145 | case e1000_82573: |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 1146 | hw->fc = E1000_FC_FULL; |
Jeff Kirsher | fd80324 | 2005-12-13 00:06:22 -0500 | [diff] [blame] | 1147 | break; |
| 1148 | default: |
| 1149 | ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, |
| 1150 | 1, &eeprom_data); |
| 1151 | if (ret_val) { |
| 1152 | DEBUGOUT("EEPROM Read Error\n"); |
| 1153 | return -E1000_ERR_EEPROM; |
| 1154 | } |
| 1155 | if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0) |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 1156 | hw->fc = E1000_FC_NONE; |
Jeff Kirsher | fd80324 | 2005-12-13 00:06:22 -0500 | [diff] [blame] | 1157 | else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == |
| 1158 | EEPROM_WORD0F_ASM_DIR) |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 1159 | hw->fc = E1000_FC_TX_PAUSE; |
Jeff Kirsher | fd80324 | 2005-12-13 00:06:22 -0500 | [diff] [blame] | 1160 | else |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 1161 | hw->fc = E1000_FC_FULL; |
Jeff Kirsher | fd80324 | 2005-12-13 00:06:22 -0500 | [diff] [blame] | 1162 | break; |
| 1163 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1164 | } |
| 1165 | |
| 1166 | /* We want to save off the original Flow Control configuration just |
| 1167 | * in case we get disconnected and then reconnected into a different |
| 1168 | * hub or switch with different Flow Control capabilities. |
| 1169 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1170 | if (hw->mac_type == e1000_82542_rev2_0) |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 1171 | hw->fc &= (~E1000_FC_TX_PAUSE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1172 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1173 | if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 1174 | hw->fc &= (~E1000_FC_RX_PAUSE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1175 | |
| 1176 | hw->original_fc = hw->fc; |
| 1177 | |
| 1178 | DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc); |
| 1179 | |
| 1180 | /* Take the 4 bits from EEPROM word 0x0F that determine the initial |
| 1181 | * polarity value for the SW controlled pins, and setup the |
| 1182 | * Extended Device Control reg with that info. |
| 1183 | * This is needed because one of the SW controlled pins is used for |
| 1184 | * signal detection. So this should be done before e1000_setup_pcs_link() |
| 1185 | * or e1000_phy_setup() is called. |
| 1186 | */ |
Jeff Kirsher | 497fce5 | 2006-03-02 18:18:20 -0800 | [diff] [blame] | 1187 | if (hw->mac_type == e1000_82543) { |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1188 | ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, |
| 1189 | 1, &eeprom_data); |
| 1190 | if (ret_val) { |
| 1191 | DEBUGOUT("EEPROM Read Error\n"); |
| 1192 | return -E1000_ERR_EEPROM; |
| 1193 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1194 | ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << |
| 1195 | SWDPIO__EXT_SHIFT); |
| 1196 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
| 1197 | } |
| 1198 | |
| 1199 | /* Call the necessary subroutine to configure the link. */ |
| 1200 | ret_val = (hw->media_type == e1000_media_type_copper) ? |
| 1201 | e1000_setup_copper_link(hw) : |
| 1202 | e1000_setup_fiber_serdes_link(hw); |
| 1203 | |
| 1204 | /* Initialize the flow control address, type, and PAUSE timer |
| 1205 | * registers to their default values. This is done even if flow |
| 1206 | * control is disabled, because it does not hurt anything to |
| 1207 | * initialize these registers. |
| 1208 | */ |
| 1209 | DEBUGOUT("Initializing the Flow Control address, type and timer regs\n"); |
| 1210 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 1211 | /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */ |
| 1212 | if (hw->mac_type != e1000_ich8lan) { |
| 1213 | E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE); |
| 1214 | E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH); |
| 1215 | E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW); |
| 1216 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1217 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1218 | E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); |
| 1219 | |
| 1220 | /* Set the flow control receive threshold registers. Normally, |
| 1221 | * these registers will be set to a default threshold that may be |
| 1222 | * adjusted later by the driver's runtime code. However, if the |
| 1223 | * ability to transmit pause frames in not enabled, then these |
| 1224 | * registers will be set to 0. |
| 1225 | */ |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 1226 | if (!(hw->fc & E1000_FC_TX_PAUSE)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1227 | E1000_WRITE_REG(hw, FCRTL, 0); |
| 1228 | E1000_WRITE_REG(hw, FCRTH, 0); |
| 1229 | } else { |
| 1230 | /* We need to set up the Receive Threshold high and low water marks |
| 1231 | * as well as (optionally) enabling the transmission of XON frames. |
| 1232 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1233 | if (hw->fc_send_xon) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1234 | E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE)); |
| 1235 | E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); |
| 1236 | } else { |
| 1237 | E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); |
| 1238 | E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); |
| 1239 | } |
| 1240 | } |
| 1241 | return ret_val; |
| 1242 | } |
| 1243 | |
| 1244 | /****************************************************************************** |
| 1245 | * Sets up link for a fiber based or serdes based adapter |
| 1246 | * |
| 1247 | * hw - Struct containing variables accessed by shared code |
| 1248 | * |
| 1249 | * Manipulates Physical Coding Sublayer functions in order to configure |
| 1250 | * link. Assumes the hardware has been previously reset and the transmitter |
| 1251 | * and receiver are not enabled. |
| 1252 | *****************************************************************************/ |
| 1253 | static int32_t |
| 1254 | e1000_setup_fiber_serdes_link(struct e1000_hw *hw) |
| 1255 | { |
| 1256 | uint32_t ctrl; |
| 1257 | uint32_t status; |
| 1258 | uint32_t txcw = 0; |
| 1259 | uint32_t i; |
| 1260 | uint32_t signal = 0; |
| 1261 | int32_t ret_val; |
| 1262 | |
| 1263 | DEBUGFUNC("e1000_setup_fiber_serdes_link"); |
| 1264 | |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 1265 | /* On 82571 and 82572 Fiber connections, SerDes loopback mode persists |
| 1266 | * until explicitly turned off or a power cycle is performed. A read to |
| 1267 | * the register does not indicate its status. Therefore, we ensure |
| 1268 | * loopback mode is disabled during initialization. |
| 1269 | */ |
| 1270 | if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) |
| 1271 | E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK); |
| 1272 | |
Jeff Kirsher | 09ae3e8 | 2006-09-27 12:53:51 -0700 | [diff] [blame] | 1273 | /* On adapters with a MAC newer than 82544, SWDP 1 will be |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1274 | * set when the optics detect a signal. On older adapters, it will be |
| 1275 | * cleared when there is a signal. This applies to fiber media only. |
Jeff Kirsher | 09ae3e8 | 2006-09-27 12:53:51 -0700 | [diff] [blame] | 1276 | * If we're on serdes media, adjust the output amplitude to value |
| 1277 | * set in the EEPROM. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1278 | */ |
| 1279 | ctrl = E1000_READ_REG(hw, CTRL); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1280 | if (hw->media_type == e1000_media_type_fiber) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1281 | signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; |
| 1282 | |
| 1283 | ret_val = e1000_adjust_serdes_amplitude(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1284 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1285 | return ret_val; |
| 1286 | |
| 1287 | /* Take the link out of reset */ |
| 1288 | ctrl &= ~(E1000_CTRL_LRST); |
| 1289 | |
| 1290 | /* Adjust VCO speed to improve BER performance */ |
| 1291 | ret_val = e1000_set_vco_speed(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1292 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1293 | return ret_val; |
| 1294 | |
| 1295 | e1000_config_collision_dist(hw); |
| 1296 | |
| 1297 | /* Check for a software override of the flow control settings, and setup |
| 1298 | * the device accordingly. If auto-negotiation is enabled, then software |
| 1299 | * will have to set the "PAUSE" bits to the correct value in the Tranmsit |
| 1300 | * Config Word Register (TXCW) and re-start auto-negotiation. However, if |
| 1301 | * auto-negotiation is disabled, then software will have to manually |
| 1302 | * configure the two flow control enable bits in the CTRL register. |
| 1303 | * |
| 1304 | * The possible values of the "fc" parameter are: |
| 1305 | * 0: Flow control is completely disabled |
| 1306 | * 1: Rx flow control is enabled (we can receive pause frames, but |
| 1307 | * not send pause frames). |
| 1308 | * 2: Tx flow control is enabled (we can send pause frames but we do |
| 1309 | * not support receiving pause frames). |
| 1310 | * 3: Both Rx and TX flow control (symmetric) are enabled. |
| 1311 | */ |
| 1312 | switch (hw->fc) { |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 1313 | case E1000_FC_NONE: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1314 | /* Flow control is completely disabled by a software over-ride. */ |
| 1315 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); |
| 1316 | break; |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 1317 | case E1000_FC_RX_PAUSE: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1318 | /* RX Flow control is enabled and TX Flow control is disabled by a |
| 1319 | * software over-ride. Since there really isn't a way to advertise |
| 1320 | * that we are capable of RX Pause ONLY, we will advertise that we |
| 1321 | * support both symmetric and asymmetric RX PAUSE. Later, we will |
| 1322 | * disable the adapter's ability to send PAUSE frames. |
| 1323 | */ |
| 1324 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
| 1325 | break; |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 1326 | case E1000_FC_TX_PAUSE: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1327 | /* TX Flow control is enabled, and RX Flow control is disabled, by a |
| 1328 | * software over-ride. |
| 1329 | */ |
| 1330 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); |
| 1331 | break; |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 1332 | case E1000_FC_FULL: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1333 | /* Flow control (both RX and TX) is enabled by a software over-ride. */ |
| 1334 | txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); |
| 1335 | break; |
| 1336 | default: |
| 1337 | DEBUGOUT("Flow control param set incorrectly\n"); |
| 1338 | return -E1000_ERR_CONFIG; |
| 1339 | break; |
| 1340 | } |
| 1341 | |
| 1342 | /* Since auto-negotiation is enabled, take the link out of reset (the link |
| 1343 | * will be in reset, because we previously reset the chip). This will |
| 1344 | * restart auto-negotiation. If auto-neogtiation is successful then the |
| 1345 | * link-up status bit will be set and the flow control enable bits (RFCE |
| 1346 | * and TFCE) will be set according to their negotiated value. |
| 1347 | */ |
| 1348 | DEBUGOUT("Auto-negotiation enabled\n"); |
| 1349 | |
| 1350 | E1000_WRITE_REG(hw, TXCW, txcw); |
| 1351 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 1352 | E1000_WRITE_FLUSH(hw); |
| 1353 | |
| 1354 | hw->txcw = txcw; |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 1355 | msleep(1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1356 | |
| 1357 | /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" |
| 1358 | * indication in the Device Status Register. Time-out if a link isn't |
| 1359 | * seen in 500 milliseconds seconds (Auto-negotiation should complete in |
| 1360 | * less than 500 milliseconds even if the other end is doing it in SW). |
| 1361 | * For internal serdes, we just assume a signal is present, then poll. |
| 1362 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1363 | if (hw->media_type == e1000_media_type_internal_serdes || |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1364 | (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { |
| 1365 | DEBUGOUT("Looking for Link\n"); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1366 | for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) { |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 1367 | msleep(10); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1368 | status = E1000_READ_REG(hw, STATUS); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1369 | if (status & E1000_STATUS_LU) break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1370 | } |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1371 | if (i == (LINK_UP_TIMEOUT / 10)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1372 | DEBUGOUT("Never got a valid link from auto-neg!!!\n"); |
| 1373 | hw->autoneg_failed = 1; |
| 1374 | /* AutoNeg failed to achieve a link, so we'll call |
| 1375 | * e1000_check_for_link. This routine will force the link up if |
| 1376 | * we detect a signal. This will allow us to communicate with |
| 1377 | * non-autonegotiating link partners. |
| 1378 | */ |
| 1379 | ret_val = e1000_check_for_link(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1380 | if (ret_val) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1381 | DEBUGOUT("Error while checking for link\n"); |
| 1382 | return ret_val; |
| 1383 | } |
| 1384 | hw->autoneg_failed = 0; |
| 1385 | } else { |
| 1386 | hw->autoneg_failed = 0; |
| 1387 | DEBUGOUT("Valid Link Found\n"); |
| 1388 | } |
| 1389 | } else { |
| 1390 | DEBUGOUT("No Signal Detected\n"); |
| 1391 | } |
| 1392 | return E1000_SUCCESS; |
| 1393 | } |
| 1394 | |
| 1395 | /****************************************************************************** |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1396 | * Make sure we have a valid PHY and change PHY mode before link setup. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1397 | * |
| 1398 | * hw - Struct containing variables accessed by shared code |
| 1399 | ******************************************************************************/ |
| 1400 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1401 | e1000_copper_link_preconfig(struct e1000_hw *hw) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1402 | { |
| 1403 | uint32_t ctrl; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1404 | int32_t ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1405 | uint16_t phy_data; |
| 1406 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1407 | DEBUGFUNC("e1000_copper_link_preconfig"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1408 | |
| 1409 | ctrl = E1000_READ_REG(hw, CTRL); |
| 1410 | /* With 82543, we need to force speed and duplex on the MAC equal to what |
| 1411 | * the PHY speed and duplex configuration is. In addition, we need to |
| 1412 | * perform a hardware reset on the PHY to take it out of reset. |
| 1413 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1414 | if (hw->mac_type > e1000_82543) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1415 | ctrl |= E1000_CTRL_SLU; |
| 1416 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
| 1417 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 1418 | } else { |
| 1419 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU); |
| 1420 | E1000_WRITE_REG(hw, CTRL, ctrl); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1421 | ret_val = e1000_phy_hw_reset(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1422 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1423 | return ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1424 | } |
| 1425 | |
| 1426 | /* Make sure we have a valid PHY */ |
| 1427 | ret_val = e1000_detect_gig_phy(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1428 | if (ret_val) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1429 | DEBUGOUT("Error, did not detect valid phy.\n"); |
| 1430 | return ret_val; |
| 1431 | } |
| 1432 | DEBUGOUT1("Phy ID = %x \n", hw->phy_id); |
| 1433 | |
| 1434 | /* Set PHY to class A mode (if necessary) */ |
| 1435 | ret_val = e1000_set_phy_mode(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1436 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1437 | return ret_val; |
| 1438 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1439 | if ((hw->mac_type == e1000_82545_rev_3) || |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1440 | (hw->mac_type == e1000_82546_rev_3)) { |
| 1441 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
| 1442 | phy_data |= 0x00000008; |
| 1443 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
| 1444 | } |
| 1445 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1446 | if (hw->mac_type <= e1000_82543 || |
| 1447 | hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || |
| 1448 | hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1449 | hw->phy_reset_disable = FALSE; |
| 1450 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1451 | return E1000_SUCCESS; |
| 1452 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1453 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1454 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1455 | /******************************************************************** |
| 1456 | * Copper link setup for e1000_phy_igp series. |
| 1457 | * |
| 1458 | * hw - Struct containing variables accessed by shared code |
| 1459 | *********************************************************************/ |
| 1460 | static int32_t |
| 1461 | e1000_copper_link_igp_setup(struct e1000_hw *hw) |
| 1462 | { |
| 1463 | uint32_t led_ctrl; |
| 1464 | int32_t ret_val; |
| 1465 | uint16_t phy_data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1466 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1467 | DEBUGFUNC("e1000_copper_link_igp_setup"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1468 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1469 | if (hw->phy_reset_disable) |
| 1470 | return E1000_SUCCESS; |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 1471 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1472 | ret_val = e1000_phy_reset(hw); |
| 1473 | if (ret_val) { |
| 1474 | DEBUGOUT("Error Resetting the PHY\n"); |
| 1475 | return ret_val; |
| 1476 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1477 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1478 | /* Wait 15ms for MAC to configure PHY from eeprom settings */ |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 1479 | msleep(15); |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 1480 | if (hw->mac_type != e1000_ich8lan) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1481 | /* Configure activity LED after PHY reset */ |
| 1482 | led_ctrl = E1000_READ_REG(hw, LEDCTL); |
| 1483 | led_ctrl &= IGP_ACTIVITY_LED_MASK; |
| 1484 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
| 1485 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 1486 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1487 | |
Jeff Kirsher | c9c1b83 | 2006-08-16 13:38:54 -0700 | [diff] [blame] | 1488 | /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */ |
| 1489 | if (hw->phy_type == e1000_phy_igp) { |
| 1490 | /* disable lplu d3 during driver init */ |
| 1491 | ret_val = e1000_set_d3_lplu_state(hw, FALSE); |
| 1492 | if (ret_val) { |
| 1493 | DEBUGOUT("Error Disabling LPLU D3\n"); |
| 1494 | return ret_val; |
| 1495 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1496 | } |
| 1497 | |
| 1498 | /* disable lplu d0 during driver init */ |
| 1499 | ret_val = e1000_set_d0_lplu_state(hw, FALSE); |
| 1500 | if (ret_val) { |
| 1501 | DEBUGOUT("Error Disabling LPLU D0\n"); |
| 1502 | return ret_val; |
| 1503 | } |
| 1504 | /* Configure mdi-mdix settings */ |
| 1505 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
| 1506 | if (ret_val) |
| 1507 | return ret_val; |
| 1508 | |
| 1509 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
| 1510 | hw->dsp_config_state = e1000_dsp_config_disabled; |
| 1511 | /* Force MDI for earlier revs of the IGP PHY */ |
| 1512 | phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX | IGP01E1000_PSCR_FORCE_MDI_MDIX); |
| 1513 | hw->mdix = 1; |
| 1514 | |
| 1515 | } else { |
| 1516 | hw->dsp_config_state = e1000_dsp_config_enabled; |
| 1517 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
| 1518 | |
| 1519 | switch (hw->mdix) { |
| 1520 | case 1: |
| 1521 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
| 1522 | break; |
| 1523 | case 2: |
| 1524 | phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; |
| 1525 | break; |
| 1526 | case 0: |
| 1527 | default: |
| 1528 | phy_data |= IGP01E1000_PSCR_AUTO_MDIX; |
| 1529 | break; |
| 1530 | } |
| 1531 | } |
| 1532 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1533 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1534 | return ret_val; |
| 1535 | |
| 1536 | /* set auto-master slave resolution settings */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1537 | if (hw->autoneg) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1538 | e1000_ms_type phy_ms_setting = hw->master_slave; |
| 1539 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1540 | if (hw->ffe_config_state == e1000_ffe_config_active) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1541 | hw->ffe_config_state = e1000_ffe_config_enabled; |
| 1542 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1543 | if (hw->dsp_config_state == e1000_dsp_config_activated) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1544 | hw->dsp_config_state = e1000_dsp_config_enabled; |
| 1545 | |
| 1546 | /* when autonegotiation advertisment is only 1000Mbps then we |
| 1547 | * should disable SmartSpeed and enable Auto MasterSlave |
| 1548 | * resolution as hardware default. */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1549 | if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1550 | /* Disable SmartSpeed */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1551 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 1552 | &phy_data); |
| 1553 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1554 | return ret_val; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1555 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1556 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 1557 | phy_data); |
| 1558 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1559 | return ret_val; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1560 | /* Set auto Master/Slave resolution process */ |
| 1561 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1562 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1563 | return ret_val; |
| 1564 | phy_data &= ~CR_1000T_MS_ENABLE; |
| 1565 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1566 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1567 | return ret_val; |
| 1568 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1569 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1570 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1571 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1572 | return ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1573 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1574 | /* load defaults for future use */ |
| 1575 | hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? |
| 1576 | ((phy_data & CR_1000T_MS_VALUE) ? |
| 1577 | e1000_ms_force_master : |
| 1578 | e1000_ms_force_slave) : |
| 1579 | e1000_ms_auto; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1580 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1581 | switch (phy_ms_setting) { |
| 1582 | case e1000_ms_force_master: |
| 1583 | phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); |
| 1584 | break; |
| 1585 | case e1000_ms_force_slave: |
| 1586 | phy_data |= CR_1000T_MS_ENABLE; |
| 1587 | phy_data &= ~(CR_1000T_MS_VALUE); |
| 1588 | break; |
| 1589 | case e1000_ms_auto: |
| 1590 | phy_data &= ~CR_1000T_MS_ENABLE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1591 | default: |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1592 | break; |
| 1593 | } |
| 1594 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1595 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1596 | return ret_val; |
Malli Chilakala | 2b02893 | 2005-06-17 17:46:06 -0700 | [diff] [blame] | 1597 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1598 | |
Malli Chilakala | 2b02893 | 2005-06-17 17:46:06 -0700 | [diff] [blame] | 1599 | return E1000_SUCCESS; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1600 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1601 | |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 1602 | /******************************************************************** |
| 1603 | * Copper link setup for e1000_phy_gg82563 series. |
| 1604 | * |
| 1605 | * hw - Struct containing variables accessed by shared code |
| 1606 | *********************************************************************/ |
| 1607 | static int32_t |
| 1608 | e1000_copper_link_ggp_setup(struct e1000_hw *hw) |
| 1609 | { |
| 1610 | int32_t ret_val; |
| 1611 | uint16_t phy_data; |
| 1612 | uint32_t reg_data; |
| 1613 | |
| 1614 | DEBUGFUNC("e1000_copper_link_ggp_setup"); |
| 1615 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1616 | if (!hw->phy_reset_disable) { |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 1617 | |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 1618 | /* Enable CRS on TX for half-duplex operation. */ |
| 1619 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, |
| 1620 | &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1621 | if (ret_val) |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 1622 | return ret_val; |
| 1623 | |
| 1624 | phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; |
| 1625 | /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ |
| 1626 | phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ; |
| 1627 | |
| 1628 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, |
| 1629 | phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1630 | if (ret_val) |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 1631 | return ret_val; |
| 1632 | |
| 1633 | /* Options: |
| 1634 | * MDI/MDI-X = 0 (default) |
| 1635 | * 0 - Auto for all speeds |
| 1636 | * 1 - MDI mode |
| 1637 | * 2 - MDI-X mode |
| 1638 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) |
| 1639 | */ |
| 1640 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1641 | if (ret_val) |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 1642 | return ret_val; |
| 1643 | |
| 1644 | phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; |
| 1645 | |
| 1646 | switch (hw->mdix) { |
| 1647 | case 1: |
| 1648 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI; |
| 1649 | break; |
| 1650 | case 2: |
| 1651 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; |
| 1652 | break; |
| 1653 | case 0: |
| 1654 | default: |
| 1655 | phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; |
| 1656 | break; |
| 1657 | } |
| 1658 | |
| 1659 | /* Options: |
| 1660 | * disable_polarity_correction = 0 (default) |
| 1661 | * Automatic Correction for Reversed Cable Polarity |
| 1662 | * 0 - Disabled |
| 1663 | * 1 - Enabled |
| 1664 | */ |
| 1665 | phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1666 | if (hw->disable_polarity_correction == 1) |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 1667 | phy_data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; |
| 1668 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); |
| 1669 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1670 | if (ret_val) |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 1671 | return ret_val; |
| 1672 | |
| 1673 | /* SW Reset the PHY so all changes take effect */ |
| 1674 | ret_val = e1000_phy_reset(hw); |
| 1675 | if (ret_val) { |
| 1676 | DEBUGOUT("Error Resetting the PHY\n"); |
| 1677 | return ret_val; |
| 1678 | } |
| 1679 | } /* phy_reset_disable */ |
| 1680 | |
| 1681 | if (hw->mac_type == e1000_80003es2lan) { |
| 1682 | /* Bypass RX and TX FIFO's */ |
| 1683 | ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL, |
| 1684 | E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS | |
| 1685 | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS); |
| 1686 | if (ret_val) |
| 1687 | return ret_val; |
| 1688 | |
| 1689 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data); |
| 1690 | if (ret_val) |
| 1691 | return ret_val; |
| 1692 | |
| 1693 | phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; |
| 1694 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data); |
| 1695 | |
| 1696 | if (ret_val) |
| 1697 | return ret_val; |
| 1698 | |
| 1699 | reg_data = E1000_READ_REG(hw, CTRL_EXT); |
| 1700 | reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); |
| 1701 | E1000_WRITE_REG(hw, CTRL_EXT, reg_data); |
| 1702 | |
| 1703 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, |
| 1704 | &phy_data); |
| 1705 | if (ret_val) |
| 1706 | return ret_val; |
| 1707 | |
| 1708 | /* Do not init these registers when the HW is in IAMT mode, since the |
| 1709 | * firmware will have already initialized them. We only initialize |
| 1710 | * them if the HW is not in IAMT mode. |
| 1711 | */ |
| 1712 | if (e1000_check_mng_mode(hw) == FALSE) { |
| 1713 | /* Enable Electrical Idle on the PHY */ |
| 1714 | phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; |
| 1715 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, |
| 1716 | phy_data); |
| 1717 | if (ret_val) |
| 1718 | return ret_val; |
| 1719 | |
| 1720 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, |
| 1721 | &phy_data); |
| 1722 | if (ret_val) |
| 1723 | return ret_val; |
| 1724 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 1725 | phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 1726 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, |
| 1727 | phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1728 | |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 1729 | if (ret_val) |
| 1730 | return ret_val; |
| 1731 | } |
| 1732 | |
| 1733 | /* Workaround: Disable padding in Kumeran interface in the MAC |
| 1734 | * and in the PHY to avoid CRC errors. |
| 1735 | */ |
| 1736 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, |
| 1737 | &phy_data); |
| 1738 | if (ret_val) |
| 1739 | return ret_val; |
| 1740 | phy_data |= GG82563_ICR_DIS_PADDING; |
| 1741 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, |
| 1742 | phy_data); |
| 1743 | if (ret_val) |
| 1744 | return ret_val; |
| 1745 | } |
| 1746 | |
| 1747 | return E1000_SUCCESS; |
| 1748 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1749 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1750 | /******************************************************************** |
| 1751 | * Copper link setup for e1000_phy_m88 series. |
| 1752 | * |
| 1753 | * hw - Struct containing variables accessed by shared code |
| 1754 | *********************************************************************/ |
| 1755 | static int32_t |
| 1756 | e1000_copper_link_mgp_setup(struct e1000_hw *hw) |
| 1757 | { |
| 1758 | int32_t ret_val; |
| 1759 | uint16_t phy_data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1760 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1761 | DEBUGFUNC("e1000_copper_link_mgp_setup"); |
| 1762 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1763 | if (hw->phy_reset_disable) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1764 | return E1000_SUCCESS; |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 1765 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1766 | /* Enable CRS on TX. This must be set for half-duplex operation. */ |
| 1767 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1768 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1769 | return ret_val; |
| 1770 | |
| 1771 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
| 1772 | |
| 1773 | /* Options: |
| 1774 | * MDI/MDI-X = 0 (default) |
| 1775 | * 0 - Auto for all speeds |
| 1776 | * 1 - MDI mode |
| 1777 | * 2 - MDI-X mode |
| 1778 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) |
| 1779 | */ |
| 1780 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
| 1781 | |
| 1782 | switch (hw->mdix) { |
| 1783 | case 1: |
| 1784 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; |
| 1785 | break; |
| 1786 | case 2: |
| 1787 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; |
| 1788 | break; |
| 1789 | case 3: |
| 1790 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; |
| 1791 | break; |
| 1792 | case 0: |
| 1793 | default: |
| 1794 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; |
| 1795 | break; |
| 1796 | } |
| 1797 | |
| 1798 | /* Options: |
| 1799 | * disable_polarity_correction = 0 (default) |
| 1800 | * Automatic Correction for Reversed Cable Polarity |
| 1801 | * 0 - Disabled |
| 1802 | * 1 - Enabled |
| 1803 | */ |
| 1804 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1805 | if (hw->disable_polarity_correction == 1) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1806 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; |
Auke Kok | ee04022 | 2006-06-27 09:08:03 -0700 | [diff] [blame] | 1807 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
| 1808 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1809 | return ret_val; |
| 1810 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1811 | if (hw->phy_revision < M88E1011_I_REV_4) { |
Auke Kok | ee04022 | 2006-06-27 09:08:03 -0700 | [diff] [blame] | 1812 | /* Force TX_CLK in the Extended PHY Specific Control Register |
| 1813 | * to 25MHz clock. |
| 1814 | */ |
| 1815 | ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
| 1816 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1817 | return ret_val; |
Auke Kok | ee04022 | 2006-06-27 09:08:03 -0700 | [diff] [blame] | 1818 | |
| 1819 | phy_data |= M88E1000_EPSCR_TX_CLK_25; |
| 1820 | |
| 1821 | if ((hw->phy_revision == E1000_REVISION_2) && |
| 1822 | (hw->phy_id == M88E1111_I_PHY_ID)) { |
| 1823 | /* Vidalia Phy, set the downshift counter to 5x */ |
| 1824 | phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK); |
| 1825 | phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; |
| 1826 | ret_val = e1000_write_phy_reg(hw, |
| 1827 | M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
| 1828 | if (ret_val) |
| 1829 | return ret_val; |
| 1830 | } else { |
| 1831 | /* Configure Master and Slave downshift values */ |
| 1832 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | |
| 1833 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); |
| 1834 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | |
| 1835 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); |
| 1836 | ret_val = e1000_write_phy_reg(hw, |
| 1837 | M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
| 1838 | if (ret_val) |
| 1839 | return ret_val; |
| 1840 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1841 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1842 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1843 | /* SW Reset the PHY so all changes take effect */ |
| 1844 | ret_val = e1000_phy_reset(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1845 | if (ret_val) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1846 | DEBUGOUT("Error Resetting the PHY\n"); |
| 1847 | return ret_val; |
| 1848 | } |
| 1849 | |
| 1850 | return E1000_SUCCESS; |
| 1851 | } |
| 1852 | |
| 1853 | /******************************************************************** |
| 1854 | * Setup auto-negotiation and flow control advertisements, |
| 1855 | * and then perform auto-negotiation. |
| 1856 | * |
| 1857 | * hw - Struct containing variables accessed by shared code |
| 1858 | *********************************************************************/ |
| 1859 | static int32_t |
| 1860 | e1000_copper_link_autoneg(struct e1000_hw *hw) |
| 1861 | { |
| 1862 | int32_t ret_val; |
| 1863 | uint16_t phy_data; |
| 1864 | |
| 1865 | DEBUGFUNC("e1000_copper_link_autoneg"); |
| 1866 | |
| 1867 | /* Perform some bounds checking on the hw->autoneg_advertised |
| 1868 | * parameter. If this variable is zero, then set it to the default. |
| 1869 | */ |
| 1870 | hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; |
| 1871 | |
| 1872 | /* If autoneg_advertised is zero, we assume it was not defaulted |
| 1873 | * by the calling code so we set to advertise full capability. |
| 1874 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1875 | if (hw->autoneg_advertised == 0) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1876 | hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
| 1877 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 1878 | /* IFE phy only supports 10/100 */ |
| 1879 | if (hw->phy_type == e1000_phy_ife) |
| 1880 | hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; |
| 1881 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1882 | DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); |
| 1883 | ret_val = e1000_phy_setup_autoneg(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1884 | if (ret_val) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1885 | DEBUGOUT("Error Setting up Auto-Negotiation\n"); |
| 1886 | return ret_val; |
| 1887 | } |
| 1888 | DEBUGOUT("Restarting Auto-Neg\n"); |
| 1889 | |
| 1890 | /* Restart auto-negotiation by setting the Auto Neg Enable bit and |
| 1891 | * the Auto Neg Restart bit in the PHY control register. |
| 1892 | */ |
| 1893 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1894 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1895 | return ret_val; |
| 1896 | |
| 1897 | phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); |
| 1898 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1899 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1900 | return ret_val; |
| 1901 | |
| 1902 | /* Does the user want to wait for Auto-Neg to complete here, or |
| 1903 | * check at a later time (for example, callback routine). |
| 1904 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1905 | if (hw->wait_autoneg_complete) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1906 | ret_val = e1000_wait_autoneg(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1907 | if (ret_val) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1908 | DEBUGOUT("Error while waiting for autoneg to complete\n"); |
| 1909 | return ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1910 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1911 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1912 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1913 | hw->get_link_status = TRUE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1914 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1915 | return E1000_SUCCESS; |
| 1916 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1917 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1918 | /****************************************************************************** |
| 1919 | * Config the MAC and the PHY after link is up. |
| 1920 | * 1) Set up the MAC to the current PHY speed/duplex |
| 1921 | * if we are on 82543. If we |
| 1922 | * are on newer silicon, we only need to configure |
| 1923 | * collision distance in the Transmit Control Register. |
| 1924 | * 2) Set up flow control on the MAC to that established with |
| 1925 | * the link partner. |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 1926 | * 3) Config DSP to improve Gigabit link quality for some PHY revisions. |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1927 | * |
| 1928 | * hw - Struct containing variables accessed by shared code |
| 1929 | ******************************************************************************/ |
| 1930 | static int32_t |
| 1931 | e1000_copper_link_postconfig(struct e1000_hw *hw) |
| 1932 | { |
| 1933 | int32_t ret_val; |
| 1934 | DEBUGFUNC("e1000_copper_link_postconfig"); |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 1935 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1936 | if (hw->mac_type >= e1000_82544) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1937 | e1000_config_collision_dist(hw); |
| 1938 | } else { |
| 1939 | ret_val = e1000_config_mac_to_phy(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1940 | if (ret_val) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1941 | DEBUGOUT("Error configuring MAC to PHY settings\n"); |
| 1942 | return ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1943 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1944 | } |
| 1945 | ret_val = e1000_config_fc_after_link_up(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1946 | if (ret_val) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1947 | DEBUGOUT("Error Configuring Flow Control\n"); |
| 1948 | return ret_val; |
| 1949 | } |
| 1950 | |
| 1951 | /* Config DSP to improve Giga link quality */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1952 | if (hw->phy_type == e1000_phy_igp) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1953 | ret_val = e1000_config_dsp_after_link_change(hw, TRUE); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 1954 | if (ret_val) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1955 | DEBUGOUT("Error Configuring DSP after link up\n"); |
| 1956 | return ret_val; |
| 1957 | } |
| 1958 | } |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 1959 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1960 | return E1000_SUCCESS; |
| 1961 | } |
| 1962 | |
| 1963 | /****************************************************************************** |
| 1964 | * Detects which PHY is present and setup the speed and duplex |
| 1965 | * |
| 1966 | * hw - Struct containing variables accessed by shared code |
| 1967 | ******************************************************************************/ |
| 1968 | static int32_t |
| 1969 | e1000_setup_copper_link(struct e1000_hw *hw) |
| 1970 | { |
| 1971 | int32_t ret_val; |
| 1972 | uint16_t i; |
| 1973 | uint16_t phy_data; |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 1974 | uint16_t reg_data; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1975 | |
| 1976 | DEBUGFUNC("e1000_setup_copper_link"); |
| 1977 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 1978 | switch (hw->mac_type) { |
| 1979 | case e1000_80003es2lan: |
| 1980 | case e1000_ich8lan: |
| 1981 | /* Set the mac to wait the maximum time between each |
| 1982 | * iteration and increase the max iterations when |
| 1983 | * polling the phy; this fixes erroneous timeouts at 10Mbps. */ |
| 1984 | ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF); |
| 1985 | if (ret_val) |
| 1986 | return ret_val; |
| 1987 | ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), ®_data); |
| 1988 | if (ret_val) |
| 1989 | return ret_val; |
| 1990 | reg_data |= 0x3F; |
| 1991 | ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data); |
| 1992 | if (ret_val) |
| 1993 | return ret_val; |
| 1994 | default: |
| 1995 | break; |
| 1996 | } |
| 1997 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 1998 | /* Check if it is a valid PHY and set PHY mode if necessary. */ |
| 1999 | ret_val = e1000_copper_link_preconfig(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2000 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2001 | return ret_val; |
| 2002 | |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 2003 | switch (hw->mac_type) { |
| 2004 | case e1000_80003es2lan: |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 2005 | /* Kumeran registers are written-only */ |
| 2006 | reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT; |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 2007 | reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING; |
| 2008 | ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL, |
| 2009 | reg_data); |
| 2010 | if (ret_val) |
| 2011 | return ret_val; |
| 2012 | break; |
| 2013 | default: |
| 2014 | break; |
| 2015 | } |
| 2016 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2017 | if (hw->phy_type == e1000_phy_igp || |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 2018 | hw->phy_type == e1000_phy_igp_3 || |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2019 | hw->phy_type == e1000_phy_igp_2) { |
| 2020 | ret_val = e1000_copper_link_igp_setup(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2021 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2022 | return ret_val; |
| 2023 | } else if (hw->phy_type == e1000_phy_m88) { |
| 2024 | ret_val = e1000_copper_link_mgp_setup(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2025 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2026 | return ret_val; |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 2027 | } else if (hw->phy_type == e1000_phy_gg82563) { |
| 2028 | ret_val = e1000_copper_link_ggp_setup(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2029 | if (ret_val) |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 2030 | return ret_val; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2031 | } |
| 2032 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2033 | if (hw->autoneg) { |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 2034 | /* Setup autoneg and flow control advertisement |
| 2035 | * and perform autonegotiation */ |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2036 | ret_val = e1000_copper_link_autoneg(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2037 | if (ret_val) |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 2038 | return ret_val; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2039 | } else { |
| 2040 | /* PHY will be set to 10H, 10F, 100H,or 100F |
| 2041 | * depending on value from forced_speed_duplex. */ |
| 2042 | DEBUGOUT("Forcing speed and duplex\n"); |
| 2043 | ret_val = e1000_phy_force_speed_duplex(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2044 | if (ret_val) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2045 | DEBUGOUT("Error Forcing Speed and Duplex\n"); |
| 2046 | return ret_val; |
| 2047 | } |
| 2048 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2049 | |
| 2050 | /* Check link status. Wait up to 100 microseconds for link to become |
| 2051 | * valid. |
| 2052 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2053 | for (i = 0; i < 10; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2054 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2055 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2056 | return ret_val; |
| 2057 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2058 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2059 | return ret_val; |
| 2060 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2061 | if (phy_data & MII_SR_LINK_STATUS) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2062 | /* Config the MAC and PHY after link is up */ |
| 2063 | ret_val = e1000_copper_link_postconfig(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2064 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2065 | return ret_val; |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 2066 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2067 | DEBUGOUT("Valid link established!!!\n"); |
| 2068 | return E1000_SUCCESS; |
| 2069 | } |
| 2070 | udelay(10); |
| 2071 | } |
| 2072 | |
| 2073 | DEBUGOUT("Unable to establish link!!!\n"); |
| 2074 | return E1000_SUCCESS; |
| 2075 | } |
| 2076 | |
| 2077 | /****************************************************************************** |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 2078 | * Configure the MAC-to-PHY interface for 10/100Mbps |
| 2079 | * |
| 2080 | * hw - Struct containing variables accessed by shared code |
| 2081 | ******************************************************************************/ |
| 2082 | static int32_t |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 2083 | e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex) |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 2084 | { |
| 2085 | int32_t ret_val = E1000_SUCCESS; |
| 2086 | uint32_t tipg; |
| 2087 | uint16_t reg_data; |
| 2088 | |
| 2089 | DEBUGFUNC("e1000_configure_kmrn_for_10_100"); |
| 2090 | |
| 2091 | reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT; |
| 2092 | ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, |
| 2093 | reg_data); |
| 2094 | if (ret_val) |
| 2095 | return ret_val; |
| 2096 | |
| 2097 | /* Configure Transmit Inter-Packet Gap */ |
| 2098 | tipg = E1000_READ_REG(hw, TIPG); |
| 2099 | tipg &= ~E1000_TIPG_IPGT_MASK; |
| 2100 | tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100; |
| 2101 | E1000_WRITE_REG(hw, TIPG, tipg); |
| 2102 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 2103 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); |
| 2104 | |
| 2105 | if (ret_val) |
| 2106 | return ret_val; |
| 2107 | |
| 2108 | if (duplex == HALF_DUPLEX) |
| 2109 | reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; |
| 2110 | else |
| 2111 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; |
| 2112 | |
| 2113 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); |
| 2114 | |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 2115 | return ret_val; |
| 2116 | } |
| 2117 | |
| 2118 | static int32_t |
| 2119 | e1000_configure_kmrn_for_1000(struct e1000_hw *hw) |
| 2120 | { |
| 2121 | int32_t ret_val = E1000_SUCCESS; |
| 2122 | uint16_t reg_data; |
| 2123 | uint32_t tipg; |
| 2124 | |
| 2125 | DEBUGFUNC("e1000_configure_kmrn_for_1000"); |
| 2126 | |
| 2127 | reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT; |
| 2128 | ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL, |
| 2129 | reg_data); |
| 2130 | if (ret_val) |
| 2131 | return ret_val; |
| 2132 | |
| 2133 | /* Configure Transmit Inter-Packet Gap */ |
| 2134 | tipg = E1000_READ_REG(hw, TIPG); |
| 2135 | tipg &= ~E1000_TIPG_IPGT_MASK; |
| 2136 | tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000; |
| 2137 | E1000_WRITE_REG(hw, TIPG, tipg); |
| 2138 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 2139 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); |
| 2140 | |
| 2141 | if (ret_val) |
| 2142 | return ret_val; |
| 2143 | |
| 2144 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; |
| 2145 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); |
| 2146 | |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 2147 | return ret_val; |
| 2148 | } |
| 2149 | |
| 2150 | /****************************************************************************** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2151 | * Configures PHY autoneg and flow control advertisement settings |
| 2152 | * |
| 2153 | * hw - Struct containing variables accessed by shared code |
| 2154 | ******************************************************************************/ |
| 2155 | int32_t |
| 2156 | e1000_phy_setup_autoneg(struct e1000_hw *hw) |
| 2157 | { |
| 2158 | int32_t ret_val; |
| 2159 | uint16_t mii_autoneg_adv_reg; |
| 2160 | uint16_t mii_1000t_ctrl_reg; |
| 2161 | |
| 2162 | DEBUGFUNC("e1000_phy_setup_autoneg"); |
| 2163 | |
| 2164 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ |
| 2165 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2166 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2167 | return ret_val; |
| 2168 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 2169 | if (hw->phy_type != e1000_phy_ife) { |
| 2170 | /* Read the MII 1000Base-T Control Register (Address 9). */ |
| 2171 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg); |
| 2172 | if (ret_val) |
| 2173 | return ret_val; |
| 2174 | } else |
| 2175 | mii_1000t_ctrl_reg=0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2176 | |
| 2177 | /* Need to parse both autoneg_advertised and fc and set up |
| 2178 | * the appropriate PHY registers. First we will parse for |
| 2179 | * autoneg_advertised software override. Since we can advertise |
| 2180 | * a plethora of combinations, we need to check each bit |
| 2181 | * individually. |
| 2182 | */ |
| 2183 | |
| 2184 | /* First we clear all the 10/100 mb speed bits in the Auto-Neg |
| 2185 | * Advertisement Register (Address 4) and the 1000 mb speed bits in |
| 2186 | * the 1000Base-T Control Register (Address 9). |
| 2187 | */ |
| 2188 | mii_autoneg_adv_reg &= ~REG4_SPEED_MASK; |
| 2189 | mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK; |
| 2190 | |
| 2191 | DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised); |
| 2192 | |
| 2193 | /* Do we want to advertise 10 Mb Half Duplex? */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2194 | if (hw->autoneg_advertised & ADVERTISE_10_HALF) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2195 | DEBUGOUT("Advertise 10mb Half duplex\n"); |
| 2196 | mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; |
| 2197 | } |
| 2198 | |
| 2199 | /* Do we want to advertise 10 Mb Full Duplex? */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2200 | if (hw->autoneg_advertised & ADVERTISE_10_FULL) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2201 | DEBUGOUT("Advertise 10mb Full duplex\n"); |
| 2202 | mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; |
| 2203 | } |
| 2204 | |
| 2205 | /* Do we want to advertise 100 Mb Half Duplex? */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2206 | if (hw->autoneg_advertised & ADVERTISE_100_HALF) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2207 | DEBUGOUT("Advertise 100mb Half duplex\n"); |
| 2208 | mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; |
| 2209 | } |
| 2210 | |
| 2211 | /* Do we want to advertise 100 Mb Full Duplex? */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2212 | if (hw->autoneg_advertised & ADVERTISE_100_FULL) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2213 | DEBUGOUT("Advertise 100mb Full duplex\n"); |
| 2214 | mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; |
| 2215 | } |
| 2216 | |
| 2217 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2218 | if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2219 | DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n"); |
| 2220 | } |
| 2221 | |
| 2222 | /* Do we want to advertise 1000 Mb Full Duplex? */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2223 | if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2224 | DEBUGOUT("Advertise 1000mb Full duplex\n"); |
| 2225 | mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 2226 | if (hw->phy_type == e1000_phy_ife) { |
| 2227 | DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n"); |
| 2228 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2229 | } |
| 2230 | |
| 2231 | /* Check for a software override of the flow control settings, and |
| 2232 | * setup the PHY advertisement registers accordingly. If |
| 2233 | * auto-negotiation is enabled, then software will have to set the |
| 2234 | * "PAUSE" bits to the correct value in the Auto-Negotiation |
| 2235 | * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. |
| 2236 | * |
| 2237 | * The possible values of the "fc" parameter are: |
| 2238 | * 0: Flow control is completely disabled |
| 2239 | * 1: Rx flow control is enabled (we can receive pause frames |
| 2240 | * but not send pause frames). |
| 2241 | * 2: Tx flow control is enabled (we can send pause frames |
| 2242 | * but we do not support receiving pause frames). |
| 2243 | * 3: Both Rx and TX flow control (symmetric) are enabled. |
| 2244 | * other: No software override. The flow control configuration |
| 2245 | * in the EEPROM is used. |
| 2246 | */ |
| 2247 | switch (hw->fc) { |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 2248 | case E1000_FC_NONE: /* 0 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2249 | /* Flow control (RX & TX) is completely disabled by a |
| 2250 | * software over-ride. |
| 2251 | */ |
| 2252 | mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
| 2253 | break; |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 2254 | case E1000_FC_RX_PAUSE: /* 1 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2255 | /* RX Flow control is enabled, and TX Flow control is |
| 2256 | * disabled, by a software over-ride. |
| 2257 | */ |
| 2258 | /* Since there really isn't a way to advertise that we are |
| 2259 | * capable of RX Pause ONLY, we will advertise that we |
| 2260 | * support both symmetric and asymmetric RX PAUSE. Later |
| 2261 | * (in e1000_config_fc_after_link_up) we will disable the |
| 2262 | *hw's ability to send PAUSE frames. |
| 2263 | */ |
| 2264 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
| 2265 | break; |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 2266 | case E1000_FC_TX_PAUSE: /* 2 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2267 | /* TX Flow control is enabled, and RX Flow control is |
| 2268 | * disabled, by a software over-ride. |
| 2269 | */ |
| 2270 | mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; |
| 2271 | mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; |
| 2272 | break; |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 2273 | case E1000_FC_FULL: /* 3 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2274 | /* Flow control (both RX and TX) is enabled by a software |
| 2275 | * over-ride. |
| 2276 | */ |
| 2277 | mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); |
| 2278 | break; |
| 2279 | default: |
| 2280 | DEBUGOUT("Flow control param set incorrectly\n"); |
| 2281 | return -E1000_ERR_CONFIG; |
| 2282 | } |
| 2283 | |
| 2284 | ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2285 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2286 | return ret_val; |
| 2287 | |
| 2288 | DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
| 2289 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 2290 | if (hw->phy_type != e1000_phy_ife) { |
| 2291 | ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg); |
| 2292 | if (ret_val) |
| 2293 | return ret_val; |
| 2294 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2295 | |
| 2296 | return E1000_SUCCESS; |
| 2297 | } |
| 2298 | |
| 2299 | /****************************************************************************** |
| 2300 | * Force PHY speed and duplex settings to hw->forced_speed_duplex |
| 2301 | * |
| 2302 | * hw - Struct containing variables accessed by shared code |
| 2303 | ******************************************************************************/ |
| 2304 | static int32_t |
| 2305 | e1000_phy_force_speed_duplex(struct e1000_hw *hw) |
| 2306 | { |
| 2307 | uint32_t ctrl; |
| 2308 | int32_t ret_val; |
| 2309 | uint16_t mii_ctrl_reg; |
| 2310 | uint16_t mii_status_reg; |
| 2311 | uint16_t phy_data; |
| 2312 | uint16_t i; |
| 2313 | |
| 2314 | DEBUGFUNC("e1000_phy_force_speed_duplex"); |
| 2315 | |
| 2316 | /* Turn off Flow control if we are forcing speed and duplex. */ |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 2317 | hw->fc = E1000_FC_NONE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2318 | |
| 2319 | DEBUGOUT1("hw->fc = %d\n", hw->fc); |
| 2320 | |
| 2321 | /* Read the Device Control Register. */ |
| 2322 | ctrl = E1000_READ_REG(hw, CTRL); |
| 2323 | |
| 2324 | /* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */ |
| 2325 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
| 2326 | ctrl &= ~(DEVICE_SPEED_MASK); |
| 2327 | |
| 2328 | /* Clear the Auto Speed Detect Enable bit. */ |
| 2329 | ctrl &= ~E1000_CTRL_ASDE; |
| 2330 | |
| 2331 | /* Read the MII Control Register. */ |
| 2332 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2333 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2334 | return ret_val; |
| 2335 | |
| 2336 | /* We need to disable autoneg in order to force link and duplex. */ |
| 2337 | |
| 2338 | mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN; |
| 2339 | |
| 2340 | /* Are we forcing Full or Half Duplex? */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2341 | if (hw->forced_speed_duplex == e1000_100_full || |
| 2342 | hw->forced_speed_duplex == e1000_10_full) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2343 | /* We want to force full duplex so we SET the full duplex bits in the |
| 2344 | * Device and MII Control Registers. |
| 2345 | */ |
| 2346 | ctrl |= E1000_CTRL_FD; |
| 2347 | mii_ctrl_reg |= MII_CR_FULL_DUPLEX; |
| 2348 | DEBUGOUT("Full Duplex\n"); |
| 2349 | } else { |
| 2350 | /* We want to force half duplex so we CLEAR the full duplex bits in |
| 2351 | * the Device and MII Control Registers. |
| 2352 | */ |
| 2353 | ctrl &= ~E1000_CTRL_FD; |
| 2354 | mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX; |
| 2355 | DEBUGOUT("Half Duplex\n"); |
| 2356 | } |
| 2357 | |
| 2358 | /* Are we forcing 100Mbps??? */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2359 | if (hw->forced_speed_duplex == e1000_100_full || |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2360 | hw->forced_speed_duplex == e1000_100_half) { |
| 2361 | /* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */ |
| 2362 | ctrl |= E1000_CTRL_SPD_100; |
| 2363 | mii_ctrl_reg |= MII_CR_SPEED_100; |
| 2364 | mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10); |
| 2365 | DEBUGOUT("Forcing 100mb "); |
| 2366 | } else { |
| 2367 | /* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */ |
| 2368 | ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); |
| 2369 | mii_ctrl_reg |= MII_CR_SPEED_10; |
| 2370 | mii_ctrl_reg &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); |
| 2371 | DEBUGOUT("Forcing 10mb "); |
| 2372 | } |
| 2373 | |
| 2374 | e1000_config_collision_dist(hw); |
| 2375 | |
| 2376 | /* Write the configured values back to the Device Control Reg. */ |
| 2377 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 2378 | |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 2379 | if ((hw->phy_type == e1000_phy_m88) || |
| 2380 | (hw->phy_type == e1000_phy_gg82563)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2381 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2382 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2383 | return ret_val; |
| 2384 | |
| 2385 | /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI |
| 2386 | * forced whenever speed are duplex are forced. |
| 2387 | */ |
| 2388 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; |
| 2389 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2390 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2391 | return ret_val; |
| 2392 | |
| 2393 | DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data); |
| 2394 | |
| 2395 | /* Need to reset the PHY or these changes will be ignored */ |
| 2396 | mii_ctrl_reg |= MII_CR_RESET; |
Auke Kok | 90fb513 | 2006-11-01 08:47:30 -0800 | [diff] [blame] | 2397 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 2398 | /* Disable MDI-X support for 10/100 */ |
| 2399 | } else if (hw->phy_type == e1000_phy_ife) { |
| 2400 | ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); |
| 2401 | if (ret_val) |
| 2402 | return ret_val; |
| 2403 | |
| 2404 | phy_data &= ~IFE_PMC_AUTO_MDIX; |
| 2405 | phy_data &= ~IFE_PMC_FORCE_MDIX; |
| 2406 | |
| 2407 | ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data); |
| 2408 | if (ret_val) |
| 2409 | return ret_val; |
Auke Kok | 90fb513 | 2006-11-01 08:47:30 -0800 | [diff] [blame] | 2410 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2411 | } else { |
| 2412 | /* Clear Auto-Crossover to force MDI manually. IGP requires MDI |
| 2413 | * forced whenever speed or duplex are forced. |
| 2414 | */ |
| 2415 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2416 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2417 | return ret_val; |
| 2418 | |
| 2419 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; |
| 2420 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; |
| 2421 | |
| 2422 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2423 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2424 | return ret_val; |
| 2425 | } |
| 2426 | |
| 2427 | /* Write back the modified PHY MII control register. */ |
| 2428 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2429 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2430 | return ret_val; |
| 2431 | |
| 2432 | udelay(1); |
| 2433 | |
| 2434 | /* The wait_autoneg_complete flag may be a little misleading here. |
| 2435 | * Since we are forcing speed and duplex, Auto-Neg is not enabled. |
| 2436 | * But we do want to delay for a period while forcing only so we |
| 2437 | * don't generate false No Link messages. So we will wait here |
| 2438 | * only if the user has set wait_autoneg_complete to 1, which is |
| 2439 | * the default. |
| 2440 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2441 | if (hw->wait_autoneg_complete) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2442 | /* We will wait for autoneg to complete. */ |
| 2443 | DEBUGOUT("Waiting for forced speed/duplex link.\n"); |
| 2444 | mii_status_reg = 0; |
| 2445 | |
| 2446 | /* We will wait for autoneg to complete or 4.5 seconds to expire. */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2447 | for (i = PHY_FORCE_TIME; i > 0; i--) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2448 | /* Read the MII Status Register and wait for Auto-Neg Complete bit |
| 2449 | * to be set. |
| 2450 | */ |
| 2451 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2452 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2453 | return ret_val; |
| 2454 | |
| 2455 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2456 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2457 | return ret_val; |
| 2458 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2459 | if (mii_status_reg & MII_SR_LINK_STATUS) break; |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 2460 | msleep(100); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2461 | } |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2462 | if ((i == 0) && |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 2463 | ((hw->phy_type == e1000_phy_m88) || |
| 2464 | (hw->phy_type == e1000_phy_gg82563))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2465 | /* We didn't get link. Reset the DSP and wait again for link. */ |
| 2466 | ret_val = e1000_phy_reset_dsp(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2467 | if (ret_val) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2468 | DEBUGOUT("Error Resetting PHY DSP\n"); |
| 2469 | return ret_val; |
| 2470 | } |
| 2471 | } |
| 2472 | /* This loop will early-out if the link condition has been met. */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2473 | for (i = PHY_FORCE_TIME; i > 0; i--) { |
| 2474 | if (mii_status_reg & MII_SR_LINK_STATUS) break; |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 2475 | msleep(100); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2476 | /* Read the MII Status Register and wait for Auto-Neg Complete bit |
| 2477 | * to be set. |
| 2478 | */ |
| 2479 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2480 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2481 | return ret_val; |
| 2482 | |
| 2483 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2484 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2485 | return ret_val; |
| 2486 | } |
| 2487 | } |
| 2488 | |
| 2489 | if (hw->phy_type == e1000_phy_m88) { |
| 2490 | /* Because we reset the PHY above, we need to re-force TX_CLK in the |
| 2491 | * Extended PHY Specific Control Register to 25MHz clock. This value |
| 2492 | * defaults back to a 2.5MHz clock when the PHY is reset. |
| 2493 | */ |
| 2494 | ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2495 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2496 | return ret_val; |
| 2497 | |
| 2498 | phy_data |= M88E1000_EPSCR_TX_CLK_25; |
| 2499 | ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2500 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2501 | return ret_val; |
| 2502 | |
| 2503 | /* In addition, because of the s/w reset above, we need to enable CRS on |
| 2504 | * TX. This must be set for both full and half duplex operation. |
| 2505 | */ |
| 2506 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2507 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2508 | return ret_val; |
| 2509 | |
| 2510 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
| 2511 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2512 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2513 | return ret_val; |
| 2514 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2515 | if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && |
| 2516 | (!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full || |
| 2517 | hw->forced_speed_duplex == e1000_10_half)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2518 | ret_val = e1000_polarity_reversal_workaround(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2519 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2520 | return ret_val; |
| 2521 | } |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 2522 | } else if (hw->phy_type == e1000_phy_gg82563) { |
| 2523 | /* The TX_CLK of the Extended PHY Specific Control Register defaults |
| 2524 | * to 2.5MHz on a reset. We need to re-force it back to 25MHz, if |
| 2525 | * we're not in a forced 10/duplex configuration. */ |
| 2526 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data); |
| 2527 | if (ret_val) |
| 2528 | return ret_val; |
| 2529 | |
| 2530 | phy_data &= ~GG82563_MSCR_TX_CLK_MASK; |
| 2531 | if ((hw->forced_speed_duplex == e1000_10_full) || |
| 2532 | (hw->forced_speed_duplex == e1000_10_half)) |
| 2533 | phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ; |
| 2534 | else |
| 2535 | phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25MHZ; |
| 2536 | |
| 2537 | /* Also due to the reset, we need to enable CRS on Tx. */ |
| 2538 | phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; |
| 2539 | |
| 2540 | ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data); |
| 2541 | if (ret_val) |
| 2542 | return ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2543 | } |
| 2544 | return E1000_SUCCESS; |
| 2545 | } |
| 2546 | |
| 2547 | /****************************************************************************** |
| 2548 | * Sets the collision distance in the Transmit Control register |
| 2549 | * |
| 2550 | * hw - Struct containing variables accessed by shared code |
| 2551 | * |
| 2552 | * Link should have been established previously. Reads the speed and duplex |
| 2553 | * information from the Device Status register. |
| 2554 | ******************************************************************************/ |
| 2555 | void |
| 2556 | e1000_config_collision_dist(struct e1000_hw *hw) |
| 2557 | { |
Jeff Kirsher | 0fadb05 | 2006-01-12 16:51:05 -0800 | [diff] [blame] | 2558 | uint32_t tctl, coll_dist; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2559 | |
| 2560 | DEBUGFUNC("e1000_config_collision_dist"); |
| 2561 | |
Jeff Kirsher | 0fadb05 | 2006-01-12 16:51:05 -0800 | [diff] [blame] | 2562 | if (hw->mac_type < e1000_82543) |
| 2563 | coll_dist = E1000_COLLISION_DISTANCE_82542; |
| 2564 | else |
| 2565 | coll_dist = E1000_COLLISION_DISTANCE; |
| 2566 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2567 | tctl = E1000_READ_REG(hw, TCTL); |
| 2568 | |
| 2569 | tctl &= ~E1000_TCTL_COLD; |
Jeff Kirsher | 0fadb05 | 2006-01-12 16:51:05 -0800 | [diff] [blame] | 2570 | tctl |= coll_dist << E1000_COLD_SHIFT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2571 | |
| 2572 | E1000_WRITE_REG(hw, TCTL, tctl); |
| 2573 | E1000_WRITE_FLUSH(hw); |
| 2574 | } |
| 2575 | |
| 2576 | /****************************************************************************** |
| 2577 | * Sets MAC speed and duplex settings to reflect the those in the PHY |
| 2578 | * |
| 2579 | * hw - Struct containing variables accessed by shared code |
| 2580 | * mii_reg - data to write to the MII control register |
| 2581 | * |
| 2582 | * The contents of the PHY register containing the needed information need to |
| 2583 | * be passed in. |
| 2584 | ******************************************************************************/ |
| 2585 | static int32_t |
| 2586 | e1000_config_mac_to_phy(struct e1000_hw *hw) |
| 2587 | { |
| 2588 | uint32_t ctrl; |
| 2589 | int32_t ret_val; |
| 2590 | uint16_t phy_data; |
| 2591 | |
| 2592 | DEBUGFUNC("e1000_config_mac_to_phy"); |
| 2593 | |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 2594 | /* 82544 or newer MAC, Auto Speed Detection takes care of |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2595 | * MAC speed/duplex configuration.*/ |
| 2596 | if (hw->mac_type >= e1000_82544) |
| 2597 | return E1000_SUCCESS; |
| 2598 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2599 | /* Read the Device Control Register and set the bits to Force Speed |
| 2600 | * and Duplex. |
| 2601 | */ |
| 2602 | ctrl = E1000_READ_REG(hw, CTRL); |
| 2603 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); |
| 2604 | ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS); |
| 2605 | |
| 2606 | /* Set up duplex in the Device Control and Transmit Control |
| 2607 | * registers depending on negotiated values. |
| 2608 | */ |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2609 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2610 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2611 | return ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2612 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2613 | if (phy_data & M88E1000_PSSR_DPLX) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2614 | ctrl |= E1000_CTRL_FD; |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 2615 | else |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2616 | ctrl &= ~E1000_CTRL_FD; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2617 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2618 | e1000_config_collision_dist(hw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2619 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2620 | /* Set up speed in the Device Control register depending on |
| 2621 | * negotiated values. |
| 2622 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2623 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2624 | ctrl |= E1000_CTRL_SPD_1000; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2625 | else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 2626 | ctrl |= E1000_CTRL_SPD_100; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2627 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2628 | /* Write the configured values back to the Device Control Reg. */ |
| 2629 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 2630 | return E1000_SUCCESS; |
| 2631 | } |
| 2632 | |
| 2633 | /****************************************************************************** |
| 2634 | * Forces the MAC's flow control settings. |
| 2635 | * |
| 2636 | * hw - Struct containing variables accessed by shared code |
| 2637 | * |
| 2638 | * Sets the TFCE and RFCE bits in the device control register to reflect |
| 2639 | * the adapter settings. TFCE and RFCE need to be explicitly set by |
| 2640 | * software when a Copper PHY is used because autonegotiation is managed |
| 2641 | * by the PHY rather than the MAC. Software must also configure these |
| 2642 | * bits when link is forced on a fiber connection. |
| 2643 | *****************************************************************************/ |
| 2644 | int32_t |
| 2645 | e1000_force_mac_fc(struct e1000_hw *hw) |
| 2646 | { |
| 2647 | uint32_t ctrl; |
| 2648 | |
| 2649 | DEBUGFUNC("e1000_force_mac_fc"); |
| 2650 | |
| 2651 | /* Get the current configuration of the Device Control Register */ |
| 2652 | ctrl = E1000_READ_REG(hw, CTRL); |
| 2653 | |
| 2654 | /* Because we didn't get link via the internal auto-negotiation |
| 2655 | * mechanism (we either forced link or we got link via PHY |
| 2656 | * auto-neg), we have to manually enable/disable transmit an |
| 2657 | * receive flow control. |
| 2658 | * |
| 2659 | * The "Case" statement below enables/disable flow control |
| 2660 | * according to the "hw->fc" parameter. |
| 2661 | * |
| 2662 | * The possible values of the "fc" parameter are: |
| 2663 | * 0: Flow control is completely disabled |
| 2664 | * 1: Rx flow control is enabled (we can receive pause |
| 2665 | * frames but not send pause frames). |
| 2666 | * 2: Tx flow control is enabled (we can send pause frames |
| 2667 | * frames but we do not receive pause frames). |
| 2668 | * 3: Both Rx and TX flow control (symmetric) is enabled. |
| 2669 | * other: No other values should be possible at this point. |
| 2670 | */ |
| 2671 | |
| 2672 | switch (hw->fc) { |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 2673 | case E1000_FC_NONE: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2674 | ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); |
| 2675 | break; |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 2676 | case E1000_FC_RX_PAUSE: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2677 | ctrl &= (~E1000_CTRL_TFCE); |
| 2678 | ctrl |= E1000_CTRL_RFCE; |
| 2679 | break; |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 2680 | case E1000_FC_TX_PAUSE: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2681 | ctrl &= (~E1000_CTRL_RFCE); |
| 2682 | ctrl |= E1000_CTRL_TFCE; |
| 2683 | break; |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 2684 | case E1000_FC_FULL: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2685 | ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); |
| 2686 | break; |
| 2687 | default: |
| 2688 | DEBUGOUT("Flow control param set incorrectly\n"); |
| 2689 | return -E1000_ERR_CONFIG; |
| 2690 | } |
| 2691 | |
| 2692 | /* Disable TX Flow Control for 82542 (rev 2.0) */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2693 | if (hw->mac_type == e1000_82542_rev2_0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2694 | ctrl &= (~E1000_CTRL_TFCE); |
| 2695 | |
| 2696 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 2697 | return E1000_SUCCESS; |
| 2698 | } |
| 2699 | |
| 2700 | /****************************************************************************** |
| 2701 | * Configures flow control settings after link is established |
| 2702 | * |
| 2703 | * hw - Struct containing variables accessed by shared code |
| 2704 | * |
| 2705 | * Should be called immediately after a valid link has been established. |
| 2706 | * Forces MAC flow control settings if link was forced. When in MII/GMII mode |
| 2707 | * and autonegotiation is enabled, the MAC flow control settings will be set |
| 2708 | * based on the flow control negotiated by the PHY. In TBI mode, the TFCE |
| 2709 | * and RFCE bits will be automaticaly set to the negotiated flow control mode. |
| 2710 | *****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 2711 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2712 | e1000_config_fc_after_link_up(struct e1000_hw *hw) |
| 2713 | { |
| 2714 | int32_t ret_val; |
| 2715 | uint16_t mii_status_reg; |
| 2716 | uint16_t mii_nway_adv_reg; |
| 2717 | uint16_t mii_nway_lp_ability_reg; |
| 2718 | uint16_t speed; |
| 2719 | uint16_t duplex; |
| 2720 | |
| 2721 | DEBUGFUNC("e1000_config_fc_after_link_up"); |
| 2722 | |
| 2723 | /* Check for the case where we have fiber media and auto-neg failed |
| 2724 | * so we had to force link. In this case, we need to force the |
| 2725 | * configuration of the MAC to match the "fc" parameter. |
| 2726 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2727 | if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) || |
| 2728 | ((hw->media_type == e1000_media_type_internal_serdes) && |
| 2729 | (hw->autoneg_failed)) || |
| 2730 | ((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2731 | ret_val = e1000_force_mac_fc(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2732 | if (ret_val) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2733 | DEBUGOUT("Error forcing flow control settings\n"); |
| 2734 | return ret_val; |
| 2735 | } |
| 2736 | } |
| 2737 | |
| 2738 | /* Check for the case where we have copper media and auto-neg is |
| 2739 | * enabled. In this case, we need to check and see if Auto-Neg |
| 2740 | * has completed, and if so, how the PHY and link partner has |
| 2741 | * flow control configured. |
| 2742 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2743 | if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2744 | /* Read the MII Status Register and check to see if AutoNeg |
| 2745 | * has completed. We read this twice because this reg has |
| 2746 | * some "sticky" (latched) bits. |
| 2747 | */ |
| 2748 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2749 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2750 | return ret_val; |
| 2751 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2752 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2753 | return ret_val; |
| 2754 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2755 | if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2756 | /* The AutoNeg process has completed, so we now need to |
| 2757 | * read both the Auto Negotiation Advertisement Register |
| 2758 | * (Address 4) and the Auto_Negotiation Base Page Ability |
| 2759 | * Register (Address 5) to determine how flow control was |
| 2760 | * negotiated. |
| 2761 | */ |
| 2762 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, |
| 2763 | &mii_nway_adv_reg); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2764 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2765 | return ret_val; |
| 2766 | ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, |
| 2767 | &mii_nway_lp_ability_reg); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2768 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2769 | return ret_val; |
| 2770 | |
| 2771 | /* Two bits in the Auto Negotiation Advertisement Register |
| 2772 | * (Address 4) and two bits in the Auto Negotiation Base |
| 2773 | * Page Ability Register (Address 5) determine flow control |
| 2774 | * for both the PHY and the link partner. The following |
| 2775 | * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, |
| 2776 | * 1999, describes these PAUSE resolution bits and how flow |
| 2777 | * control is determined based upon these settings. |
| 2778 | * NOTE: DC = Don't Care |
| 2779 | * |
| 2780 | * LOCAL DEVICE | LINK PARTNER |
| 2781 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution |
| 2782 | *-------|---------|-------|---------|-------------------- |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 2783 | * 0 | 0 | DC | DC | E1000_FC_NONE |
| 2784 | * 0 | 1 | 0 | DC | E1000_FC_NONE |
| 2785 | * 0 | 1 | 1 | 0 | E1000_FC_NONE |
| 2786 | * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE |
| 2787 | * 1 | 0 | 0 | DC | E1000_FC_NONE |
| 2788 | * 1 | DC | 1 | DC | E1000_FC_FULL |
| 2789 | * 1 | 1 | 0 | 0 | E1000_FC_NONE |
| 2790 | * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2791 | * |
| 2792 | */ |
| 2793 | /* Are both PAUSE bits set to 1? If so, this implies |
| 2794 | * Symmetric Flow Control is enabled at both ends. The |
| 2795 | * ASM_DIR bits are irrelevant per the spec. |
| 2796 | * |
| 2797 | * For Symmetric Flow Control: |
| 2798 | * |
| 2799 | * LOCAL DEVICE | LINK PARTNER |
| 2800 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 2801 | *-------|---------|-------|---------|-------------------- |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 2802 | * 1 | DC | 1 | DC | E1000_FC_FULL |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2803 | * |
| 2804 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2805 | if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
| 2806 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2807 | /* Now we need to check if the user selected RX ONLY |
| 2808 | * of pause frames. In this case, we had to advertise |
| 2809 | * FULL flow control because we could not advertise RX |
| 2810 | * ONLY. Hence, we must now check to see if we need to |
| 2811 | * turn OFF the TRANSMISSION of PAUSE frames. |
| 2812 | */ |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 2813 | if (hw->original_fc == E1000_FC_FULL) { |
| 2814 | hw->fc = E1000_FC_FULL; |
Auke Kok | a42a507 | 2006-05-23 13:36:01 -0700 | [diff] [blame] | 2815 | DEBUGOUT("Flow Control = FULL.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2816 | } else { |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 2817 | hw->fc = E1000_FC_RX_PAUSE; |
Auke Kok | a42a507 | 2006-05-23 13:36:01 -0700 | [diff] [blame] | 2818 | DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2819 | } |
| 2820 | } |
| 2821 | /* For receiving PAUSE frames ONLY. |
| 2822 | * |
| 2823 | * LOCAL DEVICE | LINK PARTNER |
| 2824 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 2825 | *-------|---------|-------|---------|-------------------- |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 2826 | * 0 | 1 | 1 | 1 | E1000_FC_TX_PAUSE |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2827 | * |
| 2828 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2829 | else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && |
| 2830 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
| 2831 | (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
| 2832 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 2833 | hw->fc = E1000_FC_TX_PAUSE; |
Auke Kok | a42a507 | 2006-05-23 13:36:01 -0700 | [diff] [blame] | 2834 | DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2835 | } |
| 2836 | /* For transmitting PAUSE frames ONLY. |
| 2837 | * |
| 2838 | * LOCAL DEVICE | LINK PARTNER |
| 2839 | * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result |
| 2840 | *-------|---------|-------|---------|-------------------- |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 2841 | * 1 | 1 | 0 | 1 | E1000_FC_RX_PAUSE |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2842 | * |
| 2843 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2844 | else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && |
| 2845 | (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && |
| 2846 | !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && |
| 2847 | (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 2848 | hw->fc = E1000_FC_RX_PAUSE; |
Auke Kok | a42a507 | 2006-05-23 13:36:01 -0700 | [diff] [blame] | 2849 | DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2850 | } |
| 2851 | /* Per the IEEE spec, at this point flow control should be |
| 2852 | * disabled. However, we want to consider that we could |
| 2853 | * be connected to a legacy switch that doesn't advertise |
| 2854 | * desired flow control, but can be forced on the link |
| 2855 | * partner. So if we advertised no flow control, that is |
| 2856 | * what we will resolve to. If we advertised some kind of |
| 2857 | * receive capability (Rx Pause Only or Full Flow Control) |
| 2858 | * and the link partner advertised none, we will configure |
| 2859 | * ourselves to enable Rx Flow Control only. We can do |
| 2860 | * this safely for two reasons: If the link partner really |
| 2861 | * didn't want flow control enabled, and we enable Rx, no |
| 2862 | * harm done since we won't be receiving any PAUSE frames |
| 2863 | * anyway. If the intent on the link partner was to have |
| 2864 | * flow control enabled, then by us enabling RX only, we |
| 2865 | * can at least receive pause frames and process them. |
| 2866 | * This is a good idea because in most cases, since we are |
| 2867 | * predominantly a server NIC, more times than not we will |
| 2868 | * be asked to delay transmission of packets than asking |
| 2869 | * our link partner to pause transmission of frames. |
| 2870 | */ |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 2871 | else if ((hw->original_fc == E1000_FC_NONE || |
| 2872 | hw->original_fc == E1000_FC_TX_PAUSE) || |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2873 | hw->fc_strict_ieee) { |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 2874 | hw->fc = E1000_FC_NONE; |
Auke Kok | a42a507 | 2006-05-23 13:36:01 -0700 | [diff] [blame] | 2875 | DEBUGOUT("Flow Control = NONE.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2876 | } else { |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 2877 | hw->fc = E1000_FC_RX_PAUSE; |
Auke Kok | a42a507 | 2006-05-23 13:36:01 -0700 | [diff] [blame] | 2878 | DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2879 | } |
| 2880 | |
| 2881 | /* Now we need to do one last check... If we auto- |
| 2882 | * negotiated to HALF DUPLEX, flow control should not be |
| 2883 | * enabled per IEEE 802.3 spec. |
| 2884 | */ |
| 2885 | ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2886 | if (ret_val) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2887 | DEBUGOUT("Error getting link speed and duplex\n"); |
| 2888 | return ret_val; |
| 2889 | } |
| 2890 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2891 | if (duplex == HALF_DUPLEX) |
Jeff Kirsher | 11241b1 | 2006-09-27 12:53:28 -0700 | [diff] [blame] | 2892 | hw->fc = E1000_FC_NONE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2893 | |
| 2894 | /* Now we call a subroutine to actually force the MAC |
| 2895 | * controller to use the correct flow control settings. |
| 2896 | */ |
| 2897 | ret_val = e1000_force_mac_fc(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2898 | if (ret_val) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2899 | DEBUGOUT("Error forcing flow control settings\n"); |
| 2900 | return ret_val; |
| 2901 | } |
| 2902 | } else { |
Auke Kok | a42a507 | 2006-05-23 13:36:01 -0700 | [diff] [blame] | 2903 | DEBUGOUT("Copper PHY and Auto Neg has not completed.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2904 | } |
| 2905 | } |
| 2906 | return E1000_SUCCESS; |
| 2907 | } |
| 2908 | |
| 2909 | /****************************************************************************** |
| 2910 | * Checks to see if the link status of the hardware has changed. |
| 2911 | * |
| 2912 | * hw - Struct containing variables accessed by shared code |
| 2913 | * |
| 2914 | * Called by any function that needs to check the link status of the adapter. |
| 2915 | *****************************************************************************/ |
| 2916 | int32_t |
| 2917 | e1000_check_for_link(struct e1000_hw *hw) |
| 2918 | { |
| 2919 | uint32_t rxcw = 0; |
| 2920 | uint32_t ctrl; |
| 2921 | uint32_t status; |
| 2922 | uint32_t rctl; |
| 2923 | uint32_t icr; |
| 2924 | uint32_t signal = 0; |
| 2925 | int32_t ret_val; |
| 2926 | uint16_t phy_data; |
| 2927 | |
| 2928 | DEBUGFUNC("e1000_check_for_link"); |
| 2929 | |
| 2930 | ctrl = E1000_READ_REG(hw, CTRL); |
| 2931 | status = E1000_READ_REG(hw, STATUS); |
| 2932 | |
| 2933 | /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be |
| 2934 | * set when the optics detect a signal. On older adapters, it will be |
| 2935 | * cleared when there is a signal. This applies to fiber media only. |
| 2936 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2937 | if ((hw->media_type == e1000_media_type_fiber) || |
| 2938 | (hw->media_type == e1000_media_type_internal_serdes)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2939 | rxcw = E1000_READ_REG(hw, RXCW); |
| 2940 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2941 | if (hw->media_type == e1000_media_type_fiber) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2942 | signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2943 | if (status & E1000_STATUS_LU) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2944 | hw->get_link_status = FALSE; |
| 2945 | } |
| 2946 | } |
| 2947 | |
| 2948 | /* If we have a copper PHY then we only want to go out to the PHY |
| 2949 | * registers to see if Auto-Neg has completed and/or if our link |
| 2950 | * status has changed. The get_link_status flag will be set if we |
| 2951 | * receive a Link Status Change interrupt or we have Rx Sequence |
| 2952 | * Errors. |
| 2953 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2954 | if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2955 | /* First we want to see if the MII Status Register reports |
| 2956 | * link. If so, then we want to get the current speed/duplex |
| 2957 | * of the PHY. |
| 2958 | * Read the register twice since the link bit is sticky. |
| 2959 | */ |
| 2960 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2961 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2962 | return ret_val; |
| 2963 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2964 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2965 | return ret_val; |
| 2966 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2967 | if (phy_data & MII_SR_LINK_STATUS) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2968 | hw->get_link_status = FALSE; |
| 2969 | /* Check if there was DownShift, must be checked immediately after |
| 2970 | * link-up */ |
| 2971 | e1000_check_downshift(hw); |
| 2972 | |
| 2973 | /* If we are on 82544 or 82543 silicon and speed/duplex |
| 2974 | * are forced to 10H or 10F, then we will implement the polarity |
| 2975 | * reversal workaround. We disable interrupts first, and upon |
| 2976 | * returning, place the devices interrupt state to its previous |
| 2977 | * value except for the link status change interrupt which will |
| 2978 | * happen due to the execution of this workaround. |
| 2979 | */ |
| 2980 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 2981 | if ((hw->mac_type == e1000_82544 || hw->mac_type == e1000_82543) && |
| 2982 | (!hw->autoneg) && |
| 2983 | (hw->forced_speed_duplex == e1000_10_full || |
| 2984 | hw->forced_speed_duplex == e1000_10_half)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2985 | E1000_WRITE_REG(hw, IMC, 0xffffffff); |
| 2986 | ret_val = e1000_polarity_reversal_workaround(hw); |
| 2987 | icr = E1000_READ_REG(hw, ICR); |
| 2988 | E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC)); |
| 2989 | E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK); |
| 2990 | } |
| 2991 | |
| 2992 | } else { |
| 2993 | /* No link detected */ |
| 2994 | e1000_config_dsp_after_link_change(hw, FALSE); |
| 2995 | return 0; |
| 2996 | } |
| 2997 | |
| 2998 | /* If we are forcing speed/duplex, then we simply return since |
| 2999 | * we have already determined whether we have link or not. |
| 3000 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3001 | if (!hw->autoneg) return -E1000_ERR_CONFIG; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3002 | |
| 3003 | /* optimize the dsp settings for the igp phy */ |
| 3004 | e1000_config_dsp_after_link_change(hw, TRUE); |
| 3005 | |
| 3006 | /* We have a M88E1000 PHY and Auto-Neg is enabled. If we |
| 3007 | * have Si on board that is 82544 or newer, Auto |
| 3008 | * Speed Detection takes care of MAC speed/duplex |
| 3009 | * configuration. So we only need to configure Collision |
| 3010 | * Distance in the MAC. Otherwise, we need to force |
| 3011 | * speed/duplex on the MAC to the current PHY speed/duplex |
| 3012 | * settings. |
| 3013 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3014 | if (hw->mac_type >= e1000_82544) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3015 | e1000_config_collision_dist(hw); |
| 3016 | else { |
| 3017 | ret_val = e1000_config_mac_to_phy(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3018 | if (ret_val) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3019 | DEBUGOUT("Error configuring MAC to PHY settings\n"); |
| 3020 | return ret_val; |
| 3021 | } |
| 3022 | } |
| 3023 | |
| 3024 | /* Configure Flow Control now that Auto-Neg has completed. First, we |
| 3025 | * need to restore the desired flow control settings because we may |
| 3026 | * have had to re-autoneg with a different link partner. |
| 3027 | */ |
| 3028 | ret_val = e1000_config_fc_after_link_up(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3029 | if (ret_val) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3030 | DEBUGOUT("Error configuring flow control\n"); |
| 3031 | return ret_val; |
| 3032 | } |
| 3033 | |
| 3034 | /* At this point we know that we are on copper and we have |
| 3035 | * auto-negotiated link. These are conditions for checking the link |
| 3036 | * partner capability register. We use the link speed to determine if |
| 3037 | * TBI compatibility needs to be turned on or off. If the link is not |
| 3038 | * at gigabit speed, then TBI compatibility is not needed. If we are |
| 3039 | * at gigabit speed, we turn on TBI compatibility. |
| 3040 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3041 | if (hw->tbi_compatibility_en) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3042 | uint16_t speed, duplex; |
Auke Kok | 592600a | 2006-06-27 09:08:09 -0700 | [diff] [blame] | 3043 | ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); |
| 3044 | if (ret_val) { |
| 3045 | DEBUGOUT("Error getting link speed and duplex\n"); |
| 3046 | return ret_val; |
| 3047 | } |
| 3048 | if (speed != SPEED_1000) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3049 | /* If link speed is not set to gigabit speed, we do not need |
| 3050 | * to enable TBI compatibility. |
| 3051 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3052 | if (hw->tbi_compatibility_on) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3053 | /* If we previously were in the mode, turn it off. */ |
| 3054 | rctl = E1000_READ_REG(hw, RCTL); |
| 3055 | rctl &= ~E1000_RCTL_SBP; |
| 3056 | E1000_WRITE_REG(hw, RCTL, rctl); |
| 3057 | hw->tbi_compatibility_on = FALSE; |
| 3058 | } |
| 3059 | } else { |
| 3060 | /* If TBI compatibility is was previously off, turn it on. For |
| 3061 | * compatibility with a TBI link partner, we will store bad |
| 3062 | * packets. Some frames have an additional byte on the end and |
| 3063 | * will look like CRC errors to to the hardware. |
| 3064 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3065 | if (!hw->tbi_compatibility_on) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3066 | hw->tbi_compatibility_on = TRUE; |
| 3067 | rctl = E1000_READ_REG(hw, RCTL); |
| 3068 | rctl |= E1000_RCTL_SBP; |
| 3069 | E1000_WRITE_REG(hw, RCTL, rctl); |
| 3070 | } |
| 3071 | } |
| 3072 | } |
| 3073 | } |
| 3074 | /* If we don't have link (auto-negotiation failed or link partner cannot |
| 3075 | * auto-negotiate), the cable is plugged in (we have signal), and our |
| 3076 | * link partner is not trying to auto-negotiate with us (we are receiving |
| 3077 | * idles or data), we need to force link up. We also need to give |
| 3078 | * auto-negotiation time to complete, in case the cable was just plugged |
| 3079 | * in. The autoneg_failed flag does this. |
| 3080 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3081 | else if ((((hw->media_type == e1000_media_type_fiber) && |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3082 | ((ctrl & E1000_CTRL_SWDPIN1) == signal)) || |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3083 | (hw->media_type == e1000_media_type_internal_serdes)) && |
| 3084 | (!(status & E1000_STATUS_LU)) && |
| 3085 | (!(rxcw & E1000_RXCW_C))) { |
| 3086 | if (hw->autoneg_failed == 0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3087 | hw->autoneg_failed = 1; |
| 3088 | return 0; |
| 3089 | } |
Auke Kok | a42a507 | 2006-05-23 13:36:01 -0700 | [diff] [blame] | 3090 | DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3091 | |
| 3092 | /* Disable auto-negotiation in the TXCW register */ |
| 3093 | E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); |
| 3094 | |
| 3095 | /* Force link-up and also force full-duplex. */ |
| 3096 | ctrl = E1000_READ_REG(hw, CTRL); |
| 3097 | ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); |
| 3098 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 3099 | |
| 3100 | /* Configure Flow Control after forcing link up. */ |
| 3101 | ret_val = e1000_config_fc_after_link_up(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3102 | if (ret_val) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3103 | DEBUGOUT("Error configuring flow control\n"); |
| 3104 | return ret_val; |
| 3105 | } |
| 3106 | } |
| 3107 | /* If we are forcing link and we are receiving /C/ ordered sets, re-enable |
| 3108 | * auto-negotiation in the TXCW register and disable forced link in the |
| 3109 | * Device Control register in an attempt to auto-negotiate with our link |
| 3110 | * partner. |
| 3111 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3112 | else if (((hw->media_type == e1000_media_type_fiber) || |
| 3113 | (hw->media_type == e1000_media_type_internal_serdes)) && |
| 3114 | (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { |
Auke Kok | a42a507 | 2006-05-23 13:36:01 -0700 | [diff] [blame] | 3115 | DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3116 | E1000_WRITE_REG(hw, TXCW, hw->txcw); |
| 3117 | E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); |
| 3118 | |
| 3119 | hw->serdes_link_down = FALSE; |
| 3120 | } |
| 3121 | /* If we force link for non-auto-negotiation switch, check link status |
| 3122 | * based on MAC synchronization for internal serdes media type. |
| 3123 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3124 | else if ((hw->media_type == e1000_media_type_internal_serdes) && |
| 3125 | !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3126 | /* SYNCH bit and IV bit are sticky. */ |
| 3127 | udelay(10); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3128 | if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) { |
| 3129 | if (!(rxcw & E1000_RXCW_IV)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3130 | hw->serdes_link_down = FALSE; |
| 3131 | DEBUGOUT("SERDES: Link is up.\n"); |
| 3132 | } |
| 3133 | } else { |
| 3134 | hw->serdes_link_down = TRUE; |
| 3135 | DEBUGOUT("SERDES: Link is down.\n"); |
| 3136 | } |
| 3137 | } |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3138 | if ((hw->media_type == e1000_media_type_internal_serdes) && |
| 3139 | (E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3140 | hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS)); |
| 3141 | } |
| 3142 | return E1000_SUCCESS; |
| 3143 | } |
| 3144 | |
| 3145 | /****************************************************************************** |
| 3146 | * Detects the current speed and duplex settings of the hardware. |
| 3147 | * |
| 3148 | * hw - Struct containing variables accessed by shared code |
| 3149 | * speed - Speed of the connection |
| 3150 | * duplex - Duplex setting of the connection |
| 3151 | *****************************************************************************/ |
| 3152 | int32_t |
| 3153 | e1000_get_speed_and_duplex(struct e1000_hw *hw, |
| 3154 | uint16_t *speed, |
| 3155 | uint16_t *duplex) |
| 3156 | { |
| 3157 | uint32_t status; |
| 3158 | int32_t ret_val; |
| 3159 | uint16_t phy_data; |
| 3160 | |
| 3161 | DEBUGFUNC("e1000_get_speed_and_duplex"); |
| 3162 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3163 | if (hw->mac_type >= e1000_82543) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3164 | status = E1000_READ_REG(hw, STATUS); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3165 | if (status & E1000_STATUS_SPEED_1000) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3166 | *speed = SPEED_1000; |
| 3167 | DEBUGOUT("1000 Mbs, "); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3168 | } else if (status & E1000_STATUS_SPEED_100) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3169 | *speed = SPEED_100; |
| 3170 | DEBUGOUT("100 Mbs, "); |
| 3171 | } else { |
| 3172 | *speed = SPEED_10; |
| 3173 | DEBUGOUT("10 Mbs, "); |
| 3174 | } |
| 3175 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3176 | if (status & E1000_STATUS_FD) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3177 | *duplex = FULL_DUPLEX; |
Auke Kok | a42a507 | 2006-05-23 13:36:01 -0700 | [diff] [blame] | 3178 | DEBUGOUT("Full Duplex\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3179 | } else { |
| 3180 | *duplex = HALF_DUPLEX; |
Auke Kok | a42a507 | 2006-05-23 13:36:01 -0700 | [diff] [blame] | 3181 | DEBUGOUT(" Half Duplex\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3182 | } |
| 3183 | } else { |
Auke Kok | a42a507 | 2006-05-23 13:36:01 -0700 | [diff] [blame] | 3184 | DEBUGOUT("1000 Mbs, Full Duplex\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3185 | *speed = SPEED_1000; |
| 3186 | *duplex = FULL_DUPLEX; |
| 3187 | } |
| 3188 | |
| 3189 | /* IGP01 PHY may advertise full duplex operation after speed downgrade even |
| 3190 | * if it is operating at half duplex. Here we set the duplex settings to |
| 3191 | * match the duplex in the link partner's capabilities. |
| 3192 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3193 | if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3194 | ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3195 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3196 | return ret_val; |
| 3197 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3198 | if (!(phy_data & NWAY_ER_LP_NWAY_CAPS)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3199 | *duplex = HALF_DUPLEX; |
| 3200 | else { |
| 3201 | ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3202 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3203 | return ret_val; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3204 | if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) || |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3205 | (*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS))) |
| 3206 | *duplex = HALF_DUPLEX; |
| 3207 | } |
| 3208 | } |
| 3209 | |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 3210 | if ((hw->mac_type == e1000_80003es2lan) && |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3211 | (hw->media_type == e1000_media_type_copper)) { |
| 3212 | if (*speed == SPEED_1000) |
| 3213 | ret_val = e1000_configure_kmrn_for_1000(hw); |
| 3214 | else |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 3215 | ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex); |
| 3216 | if (ret_val) |
| 3217 | return ret_val; |
| 3218 | } |
| 3219 | |
| 3220 | if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) { |
| 3221 | ret_val = e1000_kumeran_lock_loss_workaround(hw); |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3222 | if (ret_val) |
| 3223 | return ret_val; |
| 3224 | } |
| 3225 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3226 | return E1000_SUCCESS; |
| 3227 | } |
| 3228 | |
| 3229 | /****************************************************************************** |
| 3230 | * Blocks until autoneg completes or times out (~4.5 seconds) |
| 3231 | * |
| 3232 | * hw - Struct containing variables accessed by shared code |
| 3233 | ******************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 3234 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3235 | e1000_wait_autoneg(struct e1000_hw *hw) |
| 3236 | { |
| 3237 | int32_t ret_val; |
| 3238 | uint16_t i; |
| 3239 | uint16_t phy_data; |
| 3240 | |
| 3241 | DEBUGFUNC("e1000_wait_autoneg"); |
| 3242 | DEBUGOUT("Waiting for Auto-Neg to complete.\n"); |
| 3243 | |
| 3244 | /* We will wait for autoneg to complete or 4.5 seconds to expire. */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3245 | for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3246 | /* Read the MII Status Register and wait for Auto-Neg |
| 3247 | * Complete bit to be set. |
| 3248 | */ |
| 3249 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3250 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3251 | return ret_val; |
| 3252 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3253 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3254 | return ret_val; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3255 | if (phy_data & MII_SR_AUTONEG_COMPLETE) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3256 | return E1000_SUCCESS; |
| 3257 | } |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 3258 | msleep(100); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3259 | } |
| 3260 | return E1000_SUCCESS; |
| 3261 | } |
| 3262 | |
| 3263 | /****************************************************************************** |
| 3264 | * Raises the Management Data Clock |
| 3265 | * |
| 3266 | * hw - Struct containing variables accessed by shared code |
| 3267 | * ctrl - Device control register's current value |
| 3268 | ******************************************************************************/ |
| 3269 | static void |
| 3270 | e1000_raise_mdi_clk(struct e1000_hw *hw, |
| 3271 | uint32_t *ctrl) |
| 3272 | { |
| 3273 | /* Raise the clock input to the Management Data Clock (by setting the MDC |
| 3274 | * bit), and then delay 10 microseconds. |
| 3275 | */ |
| 3276 | E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); |
| 3277 | E1000_WRITE_FLUSH(hw); |
| 3278 | udelay(10); |
| 3279 | } |
| 3280 | |
| 3281 | /****************************************************************************** |
| 3282 | * Lowers the Management Data Clock |
| 3283 | * |
| 3284 | * hw - Struct containing variables accessed by shared code |
| 3285 | * ctrl - Device control register's current value |
| 3286 | ******************************************************************************/ |
| 3287 | static void |
| 3288 | e1000_lower_mdi_clk(struct e1000_hw *hw, |
| 3289 | uint32_t *ctrl) |
| 3290 | { |
| 3291 | /* Lower the clock input to the Management Data Clock (by clearing the MDC |
| 3292 | * bit), and then delay 10 microseconds. |
| 3293 | */ |
| 3294 | E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); |
| 3295 | E1000_WRITE_FLUSH(hw); |
| 3296 | udelay(10); |
| 3297 | } |
| 3298 | |
| 3299 | /****************************************************************************** |
| 3300 | * Shifts data bits out to the PHY |
| 3301 | * |
| 3302 | * hw - Struct containing variables accessed by shared code |
| 3303 | * data - Data to send out to the PHY |
| 3304 | * count - Number of bits to shift out |
| 3305 | * |
| 3306 | * Bits are shifted out in MSB to LSB order. |
| 3307 | ******************************************************************************/ |
| 3308 | static void |
| 3309 | e1000_shift_out_mdi_bits(struct e1000_hw *hw, |
| 3310 | uint32_t data, |
| 3311 | uint16_t count) |
| 3312 | { |
| 3313 | uint32_t ctrl; |
| 3314 | uint32_t mask; |
| 3315 | |
| 3316 | /* We need to shift "count" number of bits out to the PHY. So, the value |
| 3317 | * in the "data" parameter will be shifted out to the PHY one bit at a |
| 3318 | * time. In order to do this, "data" must be broken down into bits. |
| 3319 | */ |
| 3320 | mask = 0x01; |
| 3321 | mask <<= (count - 1); |
| 3322 | |
| 3323 | ctrl = E1000_READ_REG(hw, CTRL); |
| 3324 | |
| 3325 | /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */ |
| 3326 | ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); |
| 3327 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3328 | while (mask) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3329 | /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and |
| 3330 | * then raising and lowering the Management Data Clock. A "0" is |
| 3331 | * shifted out to the PHY by setting the MDIO bit to "0" and then |
| 3332 | * raising and lowering the clock. |
| 3333 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3334 | if (data & mask) |
| 3335 | ctrl |= E1000_CTRL_MDIO; |
| 3336 | else |
| 3337 | ctrl &= ~E1000_CTRL_MDIO; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3338 | |
| 3339 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 3340 | E1000_WRITE_FLUSH(hw); |
| 3341 | |
| 3342 | udelay(10); |
| 3343 | |
| 3344 | e1000_raise_mdi_clk(hw, &ctrl); |
| 3345 | e1000_lower_mdi_clk(hw, &ctrl); |
| 3346 | |
| 3347 | mask = mask >> 1; |
| 3348 | } |
| 3349 | } |
| 3350 | |
| 3351 | /****************************************************************************** |
| 3352 | * Shifts data bits in from the PHY |
| 3353 | * |
| 3354 | * hw - Struct containing variables accessed by shared code |
| 3355 | * |
| 3356 | * Bits are shifted in in MSB to LSB order. |
| 3357 | ******************************************************************************/ |
| 3358 | static uint16_t |
| 3359 | e1000_shift_in_mdi_bits(struct e1000_hw *hw) |
| 3360 | { |
| 3361 | uint32_t ctrl; |
| 3362 | uint16_t data = 0; |
| 3363 | uint8_t i; |
| 3364 | |
| 3365 | /* In order to read a register from the PHY, we need to shift in a total |
| 3366 | * of 18 bits from the PHY. The first two bit (turnaround) times are used |
| 3367 | * to avoid contention on the MDIO pin when a read operation is performed. |
| 3368 | * These two bits are ignored by us and thrown away. Bits are "shifted in" |
| 3369 | * by raising the input to the Management Data Clock (setting the MDC bit), |
| 3370 | * and then reading the value of the MDIO bit. |
| 3371 | */ |
| 3372 | ctrl = E1000_READ_REG(hw, CTRL); |
| 3373 | |
| 3374 | /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */ |
| 3375 | ctrl &= ~E1000_CTRL_MDIO_DIR; |
| 3376 | ctrl &= ~E1000_CTRL_MDIO; |
| 3377 | |
| 3378 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 3379 | E1000_WRITE_FLUSH(hw); |
| 3380 | |
| 3381 | /* Raise and Lower the clock before reading in the data. This accounts for |
| 3382 | * the turnaround bits. The first clock occurred when we clocked out the |
| 3383 | * last bit of the Register Address. |
| 3384 | */ |
| 3385 | e1000_raise_mdi_clk(hw, &ctrl); |
| 3386 | e1000_lower_mdi_clk(hw, &ctrl); |
| 3387 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3388 | for (data = 0, i = 0; i < 16; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3389 | data = data << 1; |
| 3390 | e1000_raise_mdi_clk(hw, &ctrl); |
| 3391 | ctrl = E1000_READ_REG(hw, CTRL); |
| 3392 | /* Check to see if we shifted in a "1". */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3393 | if (ctrl & E1000_CTRL_MDIO) |
| 3394 | data |= 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3395 | e1000_lower_mdi_clk(hw, &ctrl); |
| 3396 | } |
| 3397 | |
| 3398 | e1000_raise_mdi_clk(hw, &ctrl); |
| 3399 | e1000_lower_mdi_clk(hw, &ctrl); |
| 3400 | |
| 3401 | return data; |
| 3402 | } |
| 3403 | |
Adrian Bunk | e4c780b | 2006-08-14 23:00:10 -0700 | [diff] [blame] | 3404 | static int32_t |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3405 | e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) |
| 3406 | { |
| 3407 | uint32_t swfw_sync = 0; |
| 3408 | uint32_t swmask = mask; |
| 3409 | uint32_t fwmask = mask << 16; |
| 3410 | int32_t timeout = 200; |
| 3411 | |
| 3412 | DEBUGFUNC("e1000_swfw_sync_acquire"); |
| 3413 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 3414 | if (hw->swfwhw_semaphore_present) |
| 3415 | return e1000_get_software_flag(hw); |
| 3416 | |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3417 | if (!hw->swfw_sync_present) |
| 3418 | return e1000_get_hw_eeprom_semaphore(hw); |
| 3419 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3420 | while (timeout) { |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3421 | if (e1000_get_hw_eeprom_semaphore(hw)) |
| 3422 | return -E1000_ERR_SWFW_SYNC; |
| 3423 | |
| 3424 | swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); |
| 3425 | if (!(swfw_sync & (fwmask | swmask))) { |
| 3426 | break; |
| 3427 | } |
| 3428 | |
| 3429 | /* firmware currently using resource (fwmask) */ |
| 3430 | /* or other software thread currently using resource (swmask) */ |
| 3431 | e1000_put_hw_eeprom_semaphore(hw); |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 3432 | mdelay(5); |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3433 | timeout--; |
| 3434 | } |
| 3435 | |
| 3436 | if (!timeout) { |
| 3437 | DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); |
| 3438 | return -E1000_ERR_SWFW_SYNC; |
| 3439 | } |
| 3440 | |
| 3441 | swfw_sync |= swmask; |
| 3442 | E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); |
| 3443 | |
| 3444 | e1000_put_hw_eeprom_semaphore(hw); |
| 3445 | return E1000_SUCCESS; |
| 3446 | } |
| 3447 | |
Adrian Bunk | e4c780b | 2006-08-14 23:00:10 -0700 | [diff] [blame] | 3448 | static void |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3449 | e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask) |
| 3450 | { |
| 3451 | uint32_t swfw_sync; |
| 3452 | uint32_t swmask = mask; |
| 3453 | |
| 3454 | DEBUGFUNC("e1000_swfw_sync_release"); |
| 3455 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 3456 | if (hw->swfwhw_semaphore_present) { |
| 3457 | e1000_release_software_flag(hw); |
| 3458 | return; |
| 3459 | } |
| 3460 | |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3461 | if (!hw->swfw_sync_present) { |
| 3462 | e1000_put_hw_eeprom_semaphore(hw); |
| 3463 | return; |
| 3464 | } |
| 3465 | |
| 3466 | /* if (e1000_get_hw_eeprom_semaphore(hw)) |
| 3467 | * return -E1000_ERR_SWFW_SYNC; */ |
| 3468 | while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS); |
| 3469 | /* empty */ |
| 3470 | |
| 3471 | swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); |
| 3472 | swfw_sync &= ~swmask; |
| 3473 | E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync); |
| 3474 | |
| 3475 | e1000_put_hw_eeprom_semaphore(hw); |
| 3476 | } |
| 3477 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3478 | /***************************************************************************** |
| 3479 | * Reads the value from a PHY register, if the value is on a specific non zero |
| 3480 | * page, sets the page first. |
| 3481 | * hw - Struct containing variables accessed by shared code |
| 3482 | * reg_addr - address of the PHY register to read |
| 3483 | ******************************************************************************/ |
| 3484 | int32_t |
| 3485 | e1000_read_phy_reg(struct e1000_hw *hw, |
| 3486 | uint32_t reg_addr, |
| 3487 | uint16_t *phy_data) |
| 3488 | { |
| 3489 | uint32_t ret_val; |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3490 | uint16_t swfw; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3491 | |
| 3492 | DEBUGFUNC("e1000_read_phy_reg"); |
| 3493 | |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3494 | if ((hw->mac_type == e1000_80003es2lan) && |
| 3495 | (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { |
| 3496 | swfw = E1000_SWFW_PHY1_SM; |
| 3497 | } else { |
| 3498 | swfw = E1000_SWFW_PHY0_SM; |
| 3499 | } |
| 3500 | if (e1000_swfw_sync_acquire(hw, swfw)) |
| 3501 | return -E1000_ERR_SWFW_SYNC; |
| 3502 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 3503 | if ((hw->phy_type == e1000_phy_igp || |
| 3504 | hw->phy_type == e1000_phy_igp_3 || |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3505 | hw->phy_type == e1000_phy_igp_2) && |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3506 | (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
| 3507 | ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, |
| 3508 | (uint16_t)reg_addr); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3509 | if (ret_val) { |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3510 | e1000_swfw_sync_release(hw, swfw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3511 | return ret_val; |
| 3512 | } |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3513 | } else if (hw->phy_type == e1000_phy_gg82563) { |
| 3514 | if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || |
| 3515 | (hw->mac_type == e1000_80003es2lan)) { |
| 3516 | /* Select Configuration Page */ |
| 3517 | if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { |
| 3518 | ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, |
| 3519 | (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); |
| 3520 | } else { |
| 3521 | /* Use Alternative Page Select register to access |
| 3522 | * registers 30 and 31 |
| 3523 | */ |
| 3524 | ret_val = e1000_write_phy_reg_ex(hw, |
| 3525 | GG82563_PHY_PAGE_SELECT_ALT, |
| 3526 | (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); |
| 3527 | } |
| 3528 | |
| 3529 | if (ret_val) { |
| 3530 | e1000_swfw_sync_release(hw, swfw); |
| 3531 | return ret_val; |
| 3532 | } |
| 3533 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3534 | } |
| 3535 | |
| 3536 | ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, |
| 3537 | phy_data); |
| 3538 | |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3539 | e1000_swfw_sync_release(hw, swfw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3540 | return ret_val; |
| 3541 | } |
| 3542 | |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 3543 | static int32_t |
| 3544 | e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3545 | uint16_t *phy_data) |
| 3546 | { |
| 3547 | uint32_t i; |
| 3548 | uint32_t mdic = 0; |
| 3549 | const uint32_t phy_addr = 1; |
| 3550 | |
| 3551 | DEBUGFUNC("e1000_read_phy_reg_ex"); |
| 3552 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3553 | if (reg_addr > MAX_PHY_REG_ADDRESS) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3554 | DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); |
| 3555 | return -E1000_ERR_PARAM; |
| 3556 | } |
| 3557 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3558 | if (hw->mac_type > e1000_82543) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3559 | /* Set up Op-code, Phy Address, and register address in the MDI |
| 3560 | * Control register. The MAC will take care of interfacing with the |
| 3561 | * PHY to retrieve the desired data. |
| 3562 | */ |
| 3563 | mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) | |
| 3564 | (phy_addr << E1000_MDIC_PHY_SHIFT) | |
| 3565 | (E1000_MDIC_OP_READ)); |
| 3566 | |
| 3567 | E1000_WRITE_REG(hw, MDIC, mdic); |
| 3568 | |
| 3569 | /* Poll the ready bit to see if the MDI read completed */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3570 | for (i = 0; i < 64; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3571 | udelay(50); |
| 3572 | mdic = E1000_READ_REG(hw, MDIC); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3573 | if (mdic & E1000_MDIC_READY) break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3574 | } |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3575 | if (!(mdic & E1000_MDIC_READY)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3576 | DEBUGOUT("MDI Read did not complete\n"); |
| 3577 | return -E1000_ERR_PHY; |
| 3578 | } |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3579 | if (mdic & E1000_MDIC_ERROR) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3580 | DEBUGOUT("MDI Error\n"); |
| 3581 | return -E1000_ERR_PHY; |
| 3582 | } |
| 3583 | *phy_data = (uint16_t) mdic; |
| 3584 | } else { |
| 3585 | /* We must first send a preamble through the MDIO pin to signal the |
| 3586 | * beginning of an MII instruction. This is done by sending 32 |
| 3587 | * consecutive "1" bits. |
| 3588 | */ |
| 3589 | e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); |
| 3590 | |
| 3591 | /* Now combine the next few fields that are required for a read |
| 3592 | * operation. We use this method instead of calling the |
| 3593 | * e1000_shift_out_mdi_bits routine five different times. The format of |
| 3594 | * a MII read instruction consists of a shift out of 14 bits and is |
| 3595 | * defined as follows: |
| 3596 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> |
| 3597 | * followed by a shift in of 18 bits. This first two bits shifted in |
| 3598 | * are TurnAround bits used to avoid contention on the MDIO pin when a |
| 3599 | * READ operation is performed. These two bits are thrown away |
| 3600 | * followed by a shift in of 16 bits which contains the desired data. |
| 3601 | */ |
| 3602 | mdic = ((reg_addr) | (phy_addr << 5) | |
| 3603 | (PHY_OP_READ << 10) | (PHY_SOF << 12)); |
| 3604 | |
| 3605 | e1000_shift_out_mdi_bits(hw, mdic, 14); |
| 3606 | |
| 3607 | /* Now that we've shifted out the read command to the MII, we need to |
| 3608 | * "shift in" the 16-bit value (18 total bits) of the requested PHY |
| 3609 | * register address. |
| 3610 | */ |
| 3611 | *phy_data = e1000_shift_in_mdi_bits(hw); |
| 3612 | } |
| 3613 | return E1000_SUCCESS; |
| 3614 | } |
| 3615 | |
| 3616 | /****************************************************************************** |
| 3617 | * Writes a value to a PHY register |
| 3618 | * |
| 3619 | * hw - Struct containing variables accessed by shared code |
| 3620 | * reg_addr - address of the PHY register to write |
| 3621 | * data - data to write to the PHY |
| 3622 | ******************************************************************************/ |
| 3623 | int32_t |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 3624 | e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3625 | uint16_t phy_data) |
| 3626 | { |
| 3627 | uint32_t ret_val; |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3628 | uint16_t swfw; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3629 | |
| 3630 | DEBUGFUNC("e1000_write_phy_reg"); |
| 3631 | |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3632 | if ((hw->mac_type == e1000_80003es2lan) && |
| 3633 | (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { |
| 3634 | swfw = E1000_SWFW_PHY1_SM; |
| 3635 | } else { |
| 3636 | swfw = E1000_SWFW_PHY0_SM; |
| 3637 | } |
| 3638 | if (e1000_swfw_sync_acquire(hw, swfw)) |
| 3639 | return -E1000_ERR_SWFW_SYNC; |
| 3640 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 3641 | if ((hw->phy_type == e1000_phy_igp || |
| 3642 | hw->phy_type == e1000_phy_igp_3 || |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3643 | hw->phy_type == e1000_phy_igp_2) && |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3644 | (reg_addr > MAX_PHY_MULTI_PAGE_REG)) { |
| 3645 | ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT, |
| 3646 | (uint16_t)reg_addr); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3647 | if (ret_val) { |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3648 | e1000_swfw_sync_release(hw, swfw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3649 | return ret_val; |
| 3650 | } |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3651 | } else if (hw->phy_type == e1000_phy_gg82563) { |
| 3652 | if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) || |
| 3653 | (hw->mac_type == e1000_80003es2lan)) { |
| 3654 | /* Select Configuration Page */ |
| 3655 | if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { |
| 3656 | ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT, |
| 3657 | (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); |
| 3658 | } else { |
| 3659 | /* Use Alternative Page Select register to access |
| 3660 | * registers 30 and 31 |
| 3661 | */ |
| 3662 | ret_val = e1000_write_phy_reg_ex(hw, |
| 3663 | GG82563_PHY_PAGE_SELECT_ALT, |
| 3664 | (uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT)); |
| 3665 | } |
| 3666 | |
| 3667 | if (ret_val) { |
| 3668 | e1000_swfw_sync_release(hw, swfw); |
| 3669 | return ret_val; |
| 3670 | } |
| 3671 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3672 | } |
| 3673 | |
| 3674 | ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr, |
| 3675 | phy_data); |
| 3676 | |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3677 | e1000_swfw_sync_release(hw, swfw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3678 | return ret_val; |
| 3679 | } |
| 3680 | |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 3681 | static int32_t |
| 3682 | e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, |
| 3683 | uint16_t phy_data) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3684 | { |
| 3685 | uint32_t i; |
| 3686 | uint32_t mdic = 0; |
| 3687 | const uint32_t phy_addr = 1; |
| 3688 | |
| 3689 | DEBUGFUNC("e1000_write_phy_reg_ex"); |
| 3690 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3691 | if (reg_addr > MAX_PHY_REG_ADDRESS) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3692 | DEBUGOUT1("PHY Address %d is out of range\n", reg_addr); |
| 3693 | return -E1000_ERR_PARAM; |
| 3694 | } |
| 3695 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3696 | if (hw->mac_type > e1000_82543) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3697 | /* Set up Op-code, Phy Address, register address, and data intended |
| 3698 | * for the PHY register in the MDI Control register. The MAC will take |
| 3699 | * care of interfacing with the PHY to send the desired data. |
| 3700 | */ |
| 3701 | mdic = (((uint32_t) phy_data) | |
| 3702 | (reg_addr << E1000_MDIC_REG_SHIFT) | |
| 3703 | (phy_addr << E1000_MDIC_PHY_SHIFT) | |
| 3704 | (E1000_MDIC_OP_WRITE)); |
| 3705 | |
| 3706 | E1000_WRITE_REG(hw, MDIC, mdic); |
| 3707 | |
| 3708 | /* Poll the ready bit to see if the MDI read completed */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3709 | for (i = 0; i < 641; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3710 | udelay(5); |
| 3711 | mdic = E1000_READ_REG(hw, MDIC); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3712 | if (mdic & E1000_MDIC_READY) break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3713 | } |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3714 | if (!(mdic & E1000_MDIC_READY)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3715 | DEBUGOUT("MDI Write did not complete\n"); |
| 3716 | return -E1000_ERR_PHY; |
| 3717 | } |
| 3718 | } else { |
| 3719 | /* We'll need to use the SW defined pins to shift the write command |
| 3720 | * out to the PHY. We first send a preamble to the PHY to signal the |
| 3721 | * beginning of the MII instruction. This is done by sending 32 |
| 3722 | * consecutive "1" bits. |
| 3723 | */ |
| 3724 | e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); |
| 3725 | |
| 3726 | /* Now combine the remaining required fields that will indicate a |
| 3727 | * write operation. We use this method instead of calling the |
| 3728 | * e1000_shift_out_mdi_bits routine for each field in the command. The |
| 3729 | * format of a MII write instruction is as follows: |
| 3730 | * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. |
| 3731 | */ |
| 3732 | mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) | |
| 3733 | (PHY_OP_WRITE << 12) | (PHY_SOF << 14)); |
| 3734 | mdic <<= 16; |
| 3735 | mdic |= (uint32_t) phy_data; |
| 3736 | |
| 3737 | e1000_shift_out_mdi_bits(hw, mdic, 32); |
| 3738 | } |
| 3739 | |
| 3740 | return E1000_SUCCESS; |
| 3741 | } |
| 3742 | |
Adrian Bunk | e4c780b | 2006-08-14 23:00:10 -0700 | [diff] [blame] | 3743 | static int32_t |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3744 | e1000_read_kmrn_reg(struct e1000_hw *hw, |
| 3745 | uint32_t reg_addr, |
| 3746 | uint16_t *data) |
| 3747 | { |
| 3748 | uint32_t reg_val; |
| 3749 | uint16_t swfw; |
| 3750 | DEBUGFUNC("e1000_read_kmrn_reg"); |
| 3751 | |
| 3752 | if ((hw->mac_type == e1000_80003es2lan) && |
| 3753 | (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { |
| 3754 | swfw = E1000_SWFW_PHY1_SM; |
| 3755 | } else { |
| 3756 | swfw = E1000_SWFW_PHY0_SM; |
| 3757 | } |
| 3758 | if (e1000_swfw_sync_acquire(hw, swfw)) |
| 3759 | return -E1000_ERR_SWFW_SYNC; |
| 3760 | |
| 3761 | /* Write register address */ |
| 3762 | reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & |
| 3763 | E1000_KUMCTRLSTA_OFFSET) | |
| 3764 | E1000_KUMCTRLSTA_REN; |
| 3765 | E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); |
| 3766 | udelay(2); |
| 3767 | |
| 3768 | /* Read the data returned */ |
| 3769 | reg_val = E1000_READ_REG(hw, KUMCTRLSTA); |
| 3770 | *data = (uint16_t)reg_val; |
| 3771 | |
| 3772 | e1000_swfw_sync_release(hw, swfw); |
| 3773 | return E1000_SUCCESS; |
| 3774 | } |
| 3775 | |
Adrian Bunk | e4c780b | 2006-08-14 23:00:10 -0700 | [diff] [blame] | 3776 | static int32_t |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3777 | e1000_write_kmrn_reg(struct e1000_hw *hw, |
| 3778 | uint32_t reg_addr, |
| 3779 | uint16_t data) |
| 3780 | { |
| 3781 | uint32_t reg_val; |
| 3782 | uint16_t swfw; |
| 3783 | DEBUGFUNC("e1000_write_kmrn_reg"); |
| 3784 | |
| 3785 | if ((hw->mac_type == e1000_80003es2lan) && |
| 3786 | (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { |
| 3787 | swfw = E1000_SWFW_PHY1_SM; |
| 3788 | } else { |
| 3789 | swfw = E1000_SWFW_PHY0_SM; |
| 3790 | } |
| 3791 | if (e1000_swfw_sync_acquire(hw, swfw)) |
| 3792 | return -E1000_ERR_SWFW_SYNC; |
| 3793 | |
| 3794 | reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) & |
| 3795 | E1000_KUMCTRLSTA_OFFSET) | data; |
| 3796 | E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val); |
| 3797 | udelay(2); |
| 3798 | |
| 3799 | e1000_swfw_sync_release(hw, swfw); |
| 3800 | return E1000_SUCCESS; |
| 3801 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3802 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3803 | /****************************************************************************** |
| 3804 | * Returns the PHY to the power-on reset state |
| 3805 | * |
| 3806 | * hw - Struct containing variables accessed by shared code |
| 3807 | ******************************************************************************/ |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3808 | int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3809 | e1000_phy_hw_reset(struct e1000_hw *hw) |
| 3810 | { |
| 3811 | uint32_t ctrl, ctrl_ext; |
| 3812 | uint32_t led_ctrl; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3813 | int32_t ret_val; |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3814 | uint16_t swfw; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3815 | |
| 3816 | DEBUGFUNC("e1000_phy_hw_reset"); |
| 3817 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3818 | /* In the case of the phy reset being blocked, it's not an error, we |
| 3819 | * simply return success without performing the reset. */ |
| 3820 | ret_val = e1000_check_phy_reset_block(hw); |
| 3821 | if (ret_val) |
| 3822 | return E1000_SUCCESS; |
| 3823 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3824 | DEBUGOUT("Resetting Phy...\n"); |
| 3825 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3826 | if (hw->mac_type > e1000_82543) { |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3827 | if ((hw->mac_type == e1000_80003es2lan) && |
| 3828 | (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { |
| 3829 | swfw = E1000_SWFW_PHY1_SM; |
| 3830 | } else { |
| 3831 | swfw = E1000_SWFW_PHY0_SM; |
| 3832 | } |
| 3833 | if (e1000_swfw_sync_acquire(hw, swfw)) { |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 3834 | DEBUGOUT("Unable to acquire swfw sync\n"); |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3835 | return -E1000_ERR_SWFW_SYNC; |
| 3836 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3837 | /* Read the device control register and assert the E1000_CTRL_PHY_RST |
| 3838 | * bit. Then, take it out of reset. |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 3839 | * For pre-e1000_82571 hardware, we delay for 10ms between the assert |
Jeff Kirsher | fd80324 | 2005-12-13 00:06:22 -0500 | [diff] [blame] | 3840 | * and deassert. For e1000_82571 hardware and later, we instead delay |
Jeff Kirsher | 0f15a8f | 2006-03-02 18:46:29 -0800 | [diff] [blame] | 3841 | * for 50us between and 10ms after the deassertion. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3842 | */ |
| 3843 | ctrl = E1000_READ_REG(hw, CTRL); |
| 3844 | E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); |
| 3845 | E1000_WRITE_FLUSH(hw); |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 3846 | |
| 3847 | if (hw->mac_type < e1000_82571) |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 3848 | msleep(10); |
Jeff Kirsher | b55ccb3 | 2006-01-12 16:50:30 -0800 | [diff] [blame] | 3849 | else |
| 3850 | udelay(100); |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 3851 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3852 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 3853 | E1000_WRITE_FLUSH(hw); |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 3854 | |
Jeff Kirsher | fd80324 | 2005-12-13 00:06:22 -0500 | [diff] [blame] | 3855 | if (hw->mac_type >= e1000_82571) |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 3856 | mdelay(10); |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 3857 | |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3858 | e1000_swfw_sync_release(hw, swfw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3859 | } else { |
| 3860 | /* Read the Extended Device Control Register, assert the PHY_RESET_DIR |
| 3861 | * bit to put the PHY into reset. Then, take it out of reset. |
| 3862 | */ |
| 3863 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
| 3864 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR; |
| 3865 | ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA; |
| 3866 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
| 3867 | E1000_WRITE_FLUSH(hw); |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 3868 | msleep(10); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3869 | ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA; |
| 3870 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
| 3871 | E1000_WRITE_FLUSH(hw); |
| 3872 | } |
| 3873 | udelay(150); |
| 3874 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3875 | if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3876 | /* Configure activity LED after PHY reset */ |
| 3877 | led_ctrl = E1000_READ_REG(hw, LEDCTL); |
| 3878 | led_ctrl &= IGP_ACTIVITY_LED_MASK; |
| 3879 | led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); |
| 3880 | E1000_WRITE_REG(hw, LEDCTL, led_ctrl); |
| 3881 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3882 | |
| 3883 | /* Wait for FW to finish PHY configuration. */ |
| 3884 | ret_val = e1000_get_phy_cfg_done(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3885 | if (ret_val != E1000_SUCCESS) |
| 3886 | return ret_val; |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 3887 | e1000_release_software_semaphore(hw); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3888 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3889 | if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3)) |
| 3890 | ret_val = e1000_init_lcd_from_nvm(hw); |
| 3891 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3892 | return ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3893 | } |
| 3894 | |
| 3895 | /****************************************************************************** |
| 3896 | * Resets the PHY |
| 3897 | * |
| 3898 | * hw - Struct containing variables accessed by shared code |
| 3899 | * |
Matt LaPlante | 0779bf2 | 2006-11-30 05:24:39 +0100 | [diff] [blame] | 3900 | * Sets bit 15 of the MII Control register |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3901 | ******************************************************************************/ |
| 3902 | int32_t |
| 3903 | e1000_phy_reset(struct e1000_hw *hw) |
| 3904 | { |
| 3905 | int32_t ret_val; |
| 3906 | uint16_t phy_data; |
| 3907 | |
| 3908 | DEBUGFUNC("e1000_phy_reset"); |
| 3909 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3910 | /* In the case of the phy reset being blocked, it's not an error, we |
| 3911 | * simply return success without performing the reset. */ |
| 3912 | ret_val = e1000_check_phy_reset_block(hw); |
| 3913 | if (ret_val) |
| 3914 | return E1000_SUCCESS; |
| 3915 | |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 3916 | switch (hw->phy_type) { |
| 3917 | case e1000_phy_igp: |
| 3918 | case e1000_phy_igp_2: |
| 3919 | case e1000_phy_igp_3: |
| 3920 | case e1000_phy_ife: |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3921 | ret_val = e1000_phy_hw_reset(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3922 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3923 | return ret_val; |
| 3924 | break; |
| 3925 | default: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3926 | ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3927 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3928 | return ret_val; |
| 3929 | |
| 3930 | phy_data |= MII_CR_RESET; |
| 3931 | ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3932 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3933 | return ret_val; |
| 3934 | |
| 3935 | udelay(1); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 3936 | break; |
| 3937 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3938 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 3939 | if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3940 | e1000_phy_init_script(hw); |
| 3941 | |
| 3942 | return E1000_SUCCESS; |
| 3943 | } |
| 3944 | |
| 3945 | /****************************************************************************** |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 3946 | * Work-around for 82566 power-down: on D3 entry- |
| 3947 | * 1) disable gigabit link |
| 3948 | * 2) write VR power-down enable |
| 3949 | * 3) read it back |
| 3950 | * if successful continue, else issue LCD reset and repeat |
| 3951 | * |
| 3952 | * hw - struct containing variables accessed by shared code |
| 3953 | ******************************************************************************/ |
| 3954 | void |
| 3955 | e1000_phy_powerdown_workaround(struct e1000_hw *hw) |
| 3956 | { |
| 3957 | int32_t reg; |
| 3958 | uint16_t phy_data; |
| 3959 | int32_t retry = 0; |
| 3960 | |
| 3961 | DEBUGFUNC("e1000_phy_powerdown_workaround"); |
| 3962 | |
| 3963 | if (hw->phy_type != e1000_phy_igp_3) |
| 3964 | return; |
| 3965 | |
| 3966 | do { |
| 3967 | /* Disable link */ |
| 3968 | reg = E1000_READ_REG(hw, PHY_CTRL); |
| 3969 | E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | |
| 3970 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); |
| 3971 | |
Jeff Kirsher | 070f6ff | 2006-11-01 08:47:44 -0800 | [diff] [blame] | 3972 | /* Write VR power-down enable - bits 9:8 should be 10b */ |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 3973 | e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); |
Jeff Kirsher | 070f6ff | 2006-11-01 08:47:44 -0800 | [diff] [blame] | 3974 | phy_data |= (1 << 9); |
| 3975 | phy_data &= ~(1 << 8); |
| 3976 | e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 3977 | |
| 3978 | /* Read it back and test */ |
| 3979 | e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data); |
Jeff Kirsher | 070f6ff | 2006-11-01 08:47:44 -0800 | [diff] [blame] | 3980 | if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) || retry) |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 3981 | break; |
| 3982 | |
| 3983 | /* Issue PHY reset and repeat at most one more time */ |
| 3984 | reg = E1000_READ_REG(hw, CTRL); |
| 3985 | E1000_WRITE_REG(hw, CTRL, reg | E1000_CTRL_PHY_RST); |
| 3986 | retry++; |
| 3987 | } while (retry); |
| 3988 | |
| 3989 | return; |
| 3990 | |
| 3991 | } |
| 3992 | |
| 3993 | /****************************************************************************** |
| 3994 | * Work-around for 82566 Kumeran PCS lock loss: |
| 3995 | * On link status change (i.e. PCI reset, speed change) and link is up and |
| 3996 | * speed is gigabit- |
| 3997 | * 0) if workaround is optionally disabled do nothing |
| 3998 | * 1) wait 1ms for Kumeran link to come up |
| 3999 | * 2) check Kumeran Diagnostic register PCS lock loss bit |
| 4000 | * 3) if not set the link is locked (all is good), otherwise... |
| 4001 | * 4) reset the PHY |
| 4002 | * 5) repeat up to 10 times |
| 4003 | * Note: this is only called for IGP3 copper when speed is 1gb. |
| 4004 | * |
| 4005 | * hw - struct containing variables accessed by shared code |
| 4006 | ******************************************************************************/ |
Adrian Bunk | e4c780b | 2006-08-14 23:00:10 -0700 | [diff] [blame] | 4007 | static int32_t |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 4008 | e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw) |
| 4009 | { |
| 4010 | int32_t ret_val; |
| 4011 | int32_t reg; |
| 4012 | int32_t cnt; |
| 4013 | uint16_t phy_data; |
| 4014 | |
| 4015 | if (hw->kmrn_lock_loss_workaround_disabled) |
| 4016 | return E1000_SUCCESS; |
| 4017 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4018 | /* Make sure link is up before proceeding. If not just return. |
| 4019 | * Attempting this while link is negotiating fouled up link |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 4020 | * stability */ |
| 4021 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
| 4022 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
| 4023 | |
| 4024 | if (phy_data & MII_SR_LINK_STATUS) { |
| 4025 | for (cnt = 0; cnt < 10; cnt++) { |
| 4026 | /* read once to clear */ |
| 4027 | ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); |
| 4028 | if (ret_val) |
| 4029 | return ret_val; |
| 4030 | /* and again to get new status */ |
| 4031 | ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data); |
| 4032 | if (ret_val) |
| 4033 | return ret_val; |
| 4034 | |
| 4035 | /* check for PCS lock */ |
| 4036 | if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) |
| 4037 | return E1000_SUCCESS; |
| 4038 | |
| 4039 | /* Issue PHY reset */ |
| 4040 | e1000_phy_hw_reset(hw); |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 4041 | mdelay(5); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 4042 | } |
| 4043 | /* Disable GigE link negotiation */ |
| 4044 | reg = E1000_READ_REG(hw, PHY_CTRL); |
| 4045 | E1000_WRITE_REG(hw, PHY_CTRL, reg | E1000_PHY_CTRL_GBE_DISABLE | |
| 4046 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); |
| 4047 | |
| 4048 | /* unable to acquire PCS lock */ |
| 4049 | return E1000_ERR_PHY; |
| 4050 | } |
| 4051 | |
| 4052 | return E1000_SUCCESS; |
| 4053 | } |
| 4054 | |
| 4055 | /****************************************************************************** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4056 | * Probes the expected PHY address for known PHY IDs |
| 4057 | * |
| 4058 | * hw - Struct containing variables accessed by shared code |
| 4059 | ******************************************************************************/ |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 4060 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4061 | e1000_detect_gig_phy(struct e1000_hw *hw) |
| 4062 | { |
| 4063 | int32_t phy_init_status, ret_val; |
| 4064 | uint16_t phy_id_high, phy_id_low; |
| 4065 | boolean_t match = FALSE; |
| 4066 | |
| 4067 | DEBUGFUNC("e1000_detect_gig_phy"); |
| 4068 | |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 4069 | if (hw->phy_id != 0) |
| 4070 | return E1000_SUCCESS; |
| 4071 | |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 4072 | /* The 82571 firmware may still be configuring the PHY. In this |
| 4073 | * case, we cannot access the PHY until the configuration is done. So |
| 4074 | * we explicitly set the PHY values. */ |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 4075 | if (hw->mac_type == e1000_82571 || |
| 4076 | hw->mac_type == e1000_82572) { |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 4077 | hw->phy_id = IGP01E1000_I_PHY_ID; |
| 4078 | hw->phy_type = e1000_phy_igp_2; |
| 4079 | return E1000_SUCCESS; |
| 4080 | } |
| 4081 | |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 4082 | /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work- |
| 4083 | * around that forces PHY page 0 to be set or the reads fail. The rest of |
| 4084 | * the code in this routine uses e1000_read_phy_reg to read the PHY ID. |
| 4085 | * So for ESB-2 we need to have this set so our reads won't fail. If the |
| 4086 | * attached PHY is not a e1000_phy_gg82563, the routines below will figure |
| 4087 | * this out as well. */ |
| 4088 | if (hw->mac_type == e1000_80003es2lan) |
| 4089 | hw->phy_type = e1000_phy_gg82563; |
| 4090 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4091 | /* Read the PHY ID Registers to identify which PHY is onboard. */ |
| 4092 | ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high); |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 4093 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4094 | return ret_val; |
| 4095 | |
| 4096 | hw->phy_id = (uint32_t) (phy_id_high << 16); |
| 4097 | udelay(20); |
| 4098 | ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4099 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4100 | return ret_val; |
| 4101 | |
| 4102 | hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); |
| 4103 | hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; |
| 4104 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4105 | switch (hw->mac_type) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4106 | case e1000_82543: |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4107 | if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4108 | break; |
| 4109 | case e1000_82544: |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4110 | if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4111 | break; |
| 4112 | case e1000_82540: |
| 4113 | case e1000_82545: |
| 4114 | case e1000_82545_rev_3: |
| 4115 | case e1000_82546: |
| 4116 | case e1000_82546_rev_3: |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4117 | if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4118 | break; |
| 4119 | case e1000_82541: |
| 4120 | case e1000_82541_rev_2: |
| 4121 | case e1000_82547: |
| 4122 | case e1000_82547_rev_2: |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4123 | if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4124 | break; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4125 | case e1000_82573: |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4126 | if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4127 | break; |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 4128 | case e1000_80003es2lan: |
| 4129 | if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE; |
| 4130 | break; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 4131 | case e1000_ich8lan: |
| 4132 | if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE; |
| 4133 | if (hw->phy_id == IFE_E_PHY_ID) match = TRUE; |
| 4134 | if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE; |
| 4135 | if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE; |
| 4136 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4137 | default: |
| 4138 | DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type); |
| 4139 | return -E1000_ERR_CONFIG; |
| 4140 | } |
| 4141 | phy_init_status = e1000_set_phy_type(hw); |
| 4142 | |
| 4143 | if ((match) && (phy_init_status == E1000_SUCCESS)) { |
| 4144 | DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id); |
| 4145 | return E1000_SUCCESS; |
| 4146 | } |
| 4147 | DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id); |
| 4148 | return -E1000_ERR_PHY; |
| 4149 | } |
| 4150 | |
| 4151 | /****************************************************************************** |
| 4152 | * Resets the PHY's DSP |
| 4153 | * |
| 4154 | * hw - Struct containing variables accessed by shared code |
| 4155 | ******************************************************************************/ |
| 4156 | static int32_t |
| 4157 | e1000_phy_reset_dsp(struct e1000_hw *hw) |
| 4158 | { |
| 4159 | int32_t ret_val; |
| 4160 | DEBUGFUNC("e1000_phy_reset_dsp"); |
| 4161 | |
| 4162 | do { |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 4163 | if (hw->phy_type != e1000_phy_gg82563) { |
| 4164 | ret_val = e1000_write_phy_reg(hw, 29, 0x001d); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4165 | if (ret_val) break; |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 4166 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4167 | ret_val = e1000_write_phy_reg(hw, 30, 0x00c1); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4168 | if (ret_val) break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4169 | ret_val = e1000_write_phy_reg(hw, 30, 0x0000); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4170 | if (ret_val) break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4171 | ret_val = E1000_SUCCESS; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4172 | } while (0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4173 | |
| 4174 | return ret_val; |
| 4175 | } |
| 4176 | |
| 4177 | /****************************************************************************** |
| 4178 | * Get PHY information from various PHY registers for igp PHY only. |
| 4179 | * |
| 4180 | * hw - Struct containing variables accessed by shared code |
| 4181 | * phy_info - PHY information structure |
| 4182 | ******************************************************************************/ |
Adrian Bunk | cff93eb | 2006-09-04 13:41:14 +0200 | [diff] [blame] | 4183 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4184 | e1000_phy_igp_get_info(struct e1000_hw *hw, |
| 4185 | struct e1000_phy_info *phy_info) |
| 4186 | { |
| 4187 | int32_t ret_val; |
Jeff Kirsher | 70c6f30 | 2006-09-27 12:53:31 -0700 | [diff] [blame] | 4188 | uint16_t phy_data, min_length, max_length, average; |
| 4189 | e1000_rev_polarity polarity; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4190 | |
| 4191 | DEBUGFUNC("e1000_phy_igp_get_info"); |
| 4192 | |
| 4193 | /* The downshift status is checked only once, after link is established, |
| 4194 | * and it stored in the hw->speed_downgraded parameter. */ |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4195 | phy_info->downshift = (e1000_downshift)hw->speed_downgraded; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4196 | |
| 4197 | /* IGP01E1000 does not need to support it. */ |
| 4198 | phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; |
| 4199 | |
| 4200 | /* IGP01E1000 always correct polarity reversal */ |
| 4201 | phy_info->polarity_correction = e1000_polarity_reversal_enabled; |
| 4202 | |
| 4203 | /* Check polarity status */ |
| 4204 | ret_val = e1000_check_polarity(hw, &polarity); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4205 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4206 | return ret_val; |
| 4207 | |
| 4208 | phy_info->cable_polarity = polarity; |
| 4209 | |
| 4210 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4211 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4212 | return ret_val; |
| 4213 | |
Jeff Kirsher | 70c6f30 | 2006-09-27 12:53:31 -0700 | [diff] [blame] | 4214 | phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >> |
| 4215 | IGP01E1000_PSSR_MDIX_SHIFT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4216 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4217 | if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4218 | IGP01E1000_PSSR_SPEED_1000MBPS) { |
| 4219 | /* Local/Remote Receiver Information are only valid at 1000 Mbps */ |
| 4220 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4221 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4222 | return ret_val; |
| 4223 | |
Jeff Kirsher | 70c6f30 | 2006-09-27 12:53:31 -0700 | [diff] [blame] | 4224 | phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> |
| 4225 | SR_1000T_LOCAL_RX_STATUS_SHIFT) ? |
| 4226 | e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
| 4227 | phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> |
| 4228 | SR_1000T_REMOTE_RX_STATUS_SHIFT) ? |
| 4229 | e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4230 | |
| 4231 | /* Get cable length */ |
| 4232 | ret_val = e1000_get_cable_length(hw, &min_length, &max_length); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4233 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4234 | return ret_val; |
| 4235 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4236 | /* Translate to old method */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4237 | average = (max_length + min_length) / 2; |
| 4238 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4239 | if (average <= e1000_igp_cable_length_50) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4240 | phy_info->cable_length = e1000_cable_length_50; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4241 | else if (average <= e1000_igp_cable_length_80) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4242 | phy_info->cable_length = e1000_cable_length_50_80; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4243 | else if (average <= e1000_igp_cable_length_110) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4244 | phy_info->cable_length = e1000_cable_length_80_110; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4245 | else if (average <= e1000_igp_cable_length_140) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4246 | phy_info->cable_length = e1000_cable_length_110_140; |
| 4247 | else |
| 4248 | phy_info->cable_length = e1000_cable_length_140; |
| 4249 | } |
| 4250 | |
| 4251 | return E1000_SUCCESS; |
| 4252 | } |
| 4253 | |
| 4254 | /****************************************************************************** |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 4255 | * Get PHY information from various PHY registers for ife PHY only. |
| 4256 | * |
| 4257 | * hw - Struct containing variables accessed by shared code |
| 4258 | * phy_info - PHY information structure |
| 4259 | ******************************************************************************/ |
Adrian Bunk | e4c780b | 2006-08-14 23:00:10 -0700 | [diff] [blame] | 4260 | static int32_t |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 4261 | e1000_phy_ife_get_info(struct e1000_hw *hw, |
| 4262 | struct e1000_phy_info *phy_info) |
| 4263 | { |
| 4264 | int32_t ret_val; |
Jeff Kirsher | 70c6f30 | 2006-09-27 12:53:31 -0700 | [diff] [blame] | 4265 | uint16_t phy_data; |
| 4266 | e1000_rev_polarity polarity; |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 4267 | |
| 4268 | DEBUGFUNC("e1000_phy_ife_get_info"); |
| 4269 | |
| 4270 | phy_info->downshift = (e1000_downshift)hw->speed_downgraded; |
| 4271 | phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal; |
| 4272 | |
| 4273 | ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data); |
| 4274 | if (ret_val) |
| 4275 | return ret_val; |
| 4276 | phy_info->polarity_correction = |
Jeff Kirsher | 70c6f30 | 2006-09-27 12:53:31 -0700 | [diff] [blame] | 4277 | ((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >> |
| 4278 | IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ? |
| 4279 | e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 4280 | |
| 4281 | if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) { |
| 4282 | ret_val = e1000_check_polarity(hw, &polarity); |
| 4283 | if (ret_val) |
| 4284 | return ret_val; |
| 4285 | } else { |
| 4286 | /* Polarity is forced. */ |
Jeff Kirsher | 70c6f30 | 2006-09-27 12:53:31 -0700 | [diff] [blame] | 4287 | polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >> |
| 4288 | IFE_PSC_FORCE_POLARITY_SHIFT) ? |
| 4289 | e1000_rev_polarity_reversed : e1000_rev_polarity_normal; |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 4290 | } |
| 4291 | phy_info->cable_polarity = polarity; |
| 4292 | |
| 4293 | ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data); |
| 4294 | if (ret_val) |
| 4295 | return ret_val; |
| 4296 | |
Jeff Kirsher | 70c6f30 | 2006-09-27 12:53:31 -0700 | [diff] [blame] | 4297 | phy_info->mdix_mode = (e1000_auto_x_mode) |
| 4298 | ((phy_data & (IFE_PMC_AUTO_MDIX | IFE_PMC_FORCE_MDIX)) >> |
| 4299 | IFE_PMC_MDIX_MODE_SHIFT); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 4300 | |
| 4301 | return E1000_SUCCESS; |
| 4302 | } |
| 4303 | |
| 4304 | /****************************************************************************** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4305 | * Get PHY information from various PHY registers fot m88 PHY only. |
| 4306 | * |
| 4307 | * hw - Struct containing variables accessed by shared code |
| 4308 | * phy_info - PHY information structure |
| 4309 | ******************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 4310 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4311 | e1000_phy_m88_get_info(struct e1000_hw *hw, |
| 4312 | struct e1000_phy_info *phy_info) |
| 4313 | { |
| 4314 | int32_t ret_val; |
Jeff Kirsher | 70c6f30 | 2006-09-27 12:53:31 -0700 | [diff] [blame] | 4315 | uint16_t phy_data; |
| 4316 | e1000_rev_polarity polarity; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4317 | |
| 4318 | DEBUGFUNC("e1000_phy_m88_get_info"); |
| 4319 | |
| 4320 | /* The downshift status is checked only once, after link is established, |
| 4321 | * and it stored in the hw->speed_downgraded parameter. */ |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4322 | phy_info->downshift = (e1000_downshift)hw->speed_downgraded; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4323 | |
| 4324 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4325 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4326 | return ret_val; |
| 4327 | |
| 4328 | phy_info->extended_10bt_distance = |
Jeff Kirsher | 70c6f30 | 2006-09-27 12:53:31 -0700 | [diff] [blame] | 4329 | ((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >> |
| 4330 | M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ? |
| 4331 | e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal; |
| 4332 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4333 | phy_info->polarity_correction = |
Jeff Kirsher | 70c6f30 | 2006-09-27 12:53:31 -0700 | [diff] [blame] | 4334 | ((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >> |
| 4335 | M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ? |
| 4336 | e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4337 | |
| 4338 | /* Check polarity status */ |
| 4339 | ret_val = e1000_check_polarity(hw, &polarity); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4340 | if (ret_val) |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 4341 | return ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4342 | phy_info->cable_polarity = polarity; |
| 4343 | |
| 4344 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4345 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4346 | return ret_val; |
| 4347 | |
Jeff Kirsher | 70c6f30 | 2006-09-27 12:53:31 -0700 | [diff] [blame] | 4348 | phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >> |
| 4349 | M88E1000_PSSR_MDIX_SHIFT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4350 | |
| 4351 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { |
| 4352 | /* Cable Length Estimation and Local/Remote Receiver Information |
| 4353 | * are only valid at 1000 Mbps. |
| 4354 | */ |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 4355 | if (hw->phy_type != e1000_phy_gg82563) { |
Jeff Kirsher | 70c6f30 | 2006-09-27 12:53:31 -0700 | [diff] [blame] | 4356 | phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 4357 | M88E1000_PSSR_CABLE_LENGTH_SHIFT); |
| 4358 | } else { |
| 4359 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, |
| 4360 | &phy_data); |
| 4361 | if (ret_val) |
| 4362 | return ret_val; |
| 4363 | |
Jeff Kirsher | 70c6f30 | 2006-09-27 12:53:31 -0700 | [diff] [blame] | 4364 | phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH); |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 4365 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4366 | |
| 4367 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4368 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4369 | return ret_val; |
| 4370 | |
Jeff Kirsher | 70c6f30 | 2006-09-27 12:53:31 -0700 | [diff] [blame] | 4371 | phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >> |
| 4372 | SR_1000T_LOCAL_RX_STATUS_SHIFT) ? |
| 4373 | e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
| 4374 | phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >> |
| 4375 | SR_1000T_REMOTE_RX_STATUS_SHIFT) ? |
| 4376 | e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4377 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4378 | } |
| 4379 | |
| 4380 | return E1000_SUCCESS; |
| 4381 | } |
| 4382 | |
| 4383 | /****************************************************************************** |
| 4384 | * Get PHY information from various PHY registers |
| 4385 | * |
| 4386 | * hw - Struct containing variables accessed by shared code |
| 4387 | * phy_info - PHY information structure |
| 4388 | ******************************************************************************/ |
| 4389 | int32_t |
| 4390 | e1000_phy_get_info(struct e1000_hw *hw, |
| 4391 | struct e1000_phy_info *phy_info) |
| 4392 | { |
| 4393 | int32_t ret_val; |
| 4394 | uint16_t phy_data; |
| 4395 | |
| 4396 | DEBUGFUNC("e1000_phy_get_info"); |
| 4397 | |
| 4398 | phy_info->cable_length = e1000_cable_length_undefined; |
| 4399 | phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined; |
| 4400 | phy_info->cable_polarity = e1000_rev_polarity_undefined; |
| 4401 | phy_info->downshift = e1000_downshift_undefined; |
| 4402 | phy_info->polarity_correction = e1000_polarity_reversal_undefined; |
| 4403 | phy_info->mdix_mode = e1000_auto_x_mode_undefined; |
| 4404 | phy_info->local_rx = e1000_1000t_rx_status_undefined; |
| 4405 | phy_info->remote_rx = e1000_1000t_rx_status_undefined; |
| 4406 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4407 | if (hw->media_type != e1000_media_type_copper) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4408 | DEBUGOUT("PHY info is only valid for copper media\n"); |
| 4409 | return -E1000_ERR_CONFIG; |
| 4410 | } |
| 4411 | |
| 4412 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4413 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4414 | return ret_val; |
| 4415 | |
| 4416 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4417 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4418 | return ret_val; |
| 4419 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4420 | if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4421 | DEBUGOUT("PHY info is only valid if link is up\n"); |
| 4422 | return -E1000_ERR_CONFIG; |
| 4423 | } |
| 4424 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 4425 | if (hw->phy_type == e1000_phy_igp || |
| 4426 | hw->phy_type == e1000_phy_igp_3 || |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4427 | hw->phy_type == e1000_phy_igp_2) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4428 | return e1000_phy_igp_get_info(hw, phy_info); |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 4429 | else if (hw->phy_type == e1000_phy_ife) |
| 4430 | return e1000_phy_ife_get_info(hw, phy_info); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4431 | else |
| 4432 | return e1000_phy_m88_get_info(hw, phy_info); |
| 4433 | } |
| 4434 | |
| 4435 | int32_t |
| 4436 | e1000_validate_mdi_setting(struct e1000_hw *hw) |
| 4437 | { |
| 4438 | DEBUGFUNC("e1000_validate_mdi_settings"); |
| 4439 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4440 | if (!hw->autoneg && (hw->mdix == 0 || hw->mdix == 3)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4441 | DEBUGOUT("Invalid MDI setting detected\n"); |
| 4442 | hw->mdix = 1; |
| 4443 | return -E1000_ERR_CONFIG; |
| 4444 | } |
| 4445 | return E1000_SUCCESS; |
| 4446 | } |
| 4447 | |
| 4448 | |
| 4449 | /****************************************************************************** |
| 4450 | * Sets up eeprom variables in the hw struct. Must be called after mac_type |
Jeff Kirsher | 0f15a8f | 2006-03-02 18:46:29 -0800 | [diff] [blame] | 4451 | * is configured. Additionally, if this is ICH8, the flash controller GbE |
| 4452 | * registers must be mapped, or this will crash. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4453 | * |
| 4454 | * hw - Struct containing variables accessed by shared code |
| 4455 | *****************************************************************************/ |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4456 | int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4457 | e1000_init_eeprom_params(struct e1000_hw *hw) |
| 4458 | { |
| 4459 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
| 4460 | uint32_t eecd = E1000_READ_REG(hw, EECD); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4461 | int32_t ret_val = E1000_SUCCESS; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4462 | uint16_t eeprom_size; |
| 4463 | |
| 4464 | DEBUGFUNC("e1000_init_eeprom_params"); |
| 4465 | |
| 4466 | switch (hw->mac_type) { |
| 4467 | case e1000_82542_rev2_0: |
| 4468 | case e1000_82542_rev2_1: |
| 4469 | case e1000_82543: |
| 4470 | case e1000_82544: |
| 4471 | eeprom->type = e1000_eeprom_microwire; |
| 4472 | eeprom->word_size = 64; |
| 4473 | eeprom->opcode_bits = 3; |
| 4474 | eeprom->address_bits = 6; |
| 4475 | eeprom->delay_usec = 50; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4476 | eeprom->use_eerd = FALSE; |
| 4477 | eeprom->use_eewr = FALSE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4478 | break; |
| 4479 | case e1000_82540: |
| 4480 | case e1000_82545: |
| 4481 | case e1000_82545_rev_3: |
| 4482 | case e1000_82546: |
| 4483 | case e1000_82546_rev_3: |
| 4484 | eeprom->type = e1000_eeprom_microwire; |
| 4485 | eeprom->opcode_bits = 3; |
| 4486 | eeprom->delay_usec = 50; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4487 | if (eecd & E1000_EECD_SIZE) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4488 | eeprom->word_size = 256; |
| 4489 | eeprom->address_bits = 8; |
| 4490 | } else { |
| 4491 | eeprom->word_size = 64; |
| 4492 | eeprom->address_bits = 6; |
| 4493 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4494 | eeprom->use_eerd = FALSE; |
| 4495 | eeprom->use_eewr = FALSE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4496 | break; |
| 4497 | case e1000_82541: |
| 4498 | case e1000_82541_rev_2: |
| 4499 | case e1000_82547: |
| 4500 | case e1000_82547_rev_2: |
| 4501 | if (eecd & E1000_EECD_TYPE) { |
| 4502 | eeprom->type = e1000_eeprom_spi; |
| 4503 | eeprom->opcode_bits = 8; |
| 4504 | eeprom->delay_usec = 1; |
| 4505 | if (eecd & E1000_EECD_ADDR_BITS) { |
| 4506 | eeprom->page_size = 32; |
| 4507 | eeprom->address_bits = 16; |
| 4508 | } else { |
| 4509 | eeprom->page_size = 8; |
| 4510 | eeprom->address_bits = 8; |
| 4511 | } |
| 4512 | } else { |
| 4513 | eeprom->type = e1000_eeprom_microwire; |
| 4514 | eeprom->opcode_bits = 3; |
| 4515 | eeprom->delay_usec = 50; |
| 4516 | if (eecd & E1000_EECD_ADDR_BITS) { |
| 4517 | eeprom->word_size = 256; |
| 4518 | eeprom->address_bits = 8; |
| 4519 | } else { |
| 4520 | eeprom->word_size = 64; |
| 4521 | eeprom->address_bits = 6; |
| 4522 | } |
| 4523 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4524 | eeprom->use_eerd = FALSE; |
| 4525 | eeprom->use_eewr = FALSE; |
| 4526 | break; |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 4527 | case e1000_82571: |
| 4528 | case e1000_82572: |
| 4529 | eeprom->type = e1000_eeprom_spi; |
| 4530 | eeprom->opcode_bits = 8; |
| 4531 | eeprom->delay_usec = 1; |
| 4532 | if (eecd & E1000_EECD_ADDR_BITS) { |
| 4533 | eeprom->page_size = 32; |
| 4534 | eeprom->address_bits = 16; |
| 4535 | } else { |
| 4536 | eeprom->page_size = 8; |
| 4537 | eeprom->address_bits = 8; |
| 4538 | } |
| 4539 | eeprom->use_eerd = FALSE; |
| 4540 | eeprom->use_eewr = FALSE; |
| 4541 | break; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4542 | case e1000_82573: |
| 4543 | eeprom->type = e1000_eeprom_spi; |
| 4544 | eeprom->opcode_bits = 8; |
| 4545 | eeprom->delay_usec = 1; |
| 4546 | if (eecd & E1000_EECD_ADDR_BITS) { |
| 4547 | eeprom->page_size = 32; |
| 4548 | eeprom->address_bits = 16; |
| 4549 | } else { |
| 4550 | eeprom->page_size = 8; |
| 4551 | eeprom->address_bits = 8; |
| 4552 | } |
| 4553 | eeprom->use_eerd = TRUE; |
| 4554 | eeprom->use_eewr = TRUE; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4555 | if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4556 | eeprom->type = e1000_eeprom_flash; |
| 4557 | eeprom->word_size = 2048; |
| 4558 | |
| 4559 | /* Ensure that the Autonomous FLASH update bit is cleared due to |
| 4560 | * Flash update issue on parts which use a FLASH for NVM. */ |
| 4561 | eecd &= ~E1000_EECD_AUPDEN; |
| 4562 | E1000_WRITE_REG(hw, EECD, eecd); |
| 4563 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4564 | break; |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 4565 | case e1000_80003es2lan: |
| 4566 | eeprom->type = e1000_eeprom_spi; |
| 4567 | eeprom->opcode_bits = 8; |
| 4568 | eeprom->delay_usec = 1; |
| 4569 | if (eecd & E1000_EECD_ADDR_BITS) { |
| 4570 | eeprom->page_size = 32; |
| 4571 | eeprom->address_bits = 16; |
| 4572 | } else { |
| 4573 | eeprom->page_size = 8; |
| 4574 | eeprom->address_bits = 8; |
| 4575 | } |
| 4576 | eeprom->use_eerd = TRUE; |
| 4577 | eeprom->use_eewr = FALSE; |
| 4578 | break; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 4579 | case e1000_ich8lan: |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 4580 | { |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 4581 | int32_t i = 0; |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 4582 | uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG); |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 4583 | |
| 4584 | eeprom->type = e1000_eeprom_ich8; |
| 4585 | eeprom->use_eerd = FALSE; |
| 4586 | eeprom->use_eewr = FALSE; |
| 4587 | eeprom->word_size = E1000_SHADOW_RAM_WORDS; |
| 4588 | |
| 4589 | /* Zero the shadow RAM structure. But don't load it from NVM |
| 4590 | * so as to save time for driver init */ |
| 4591 | if (hw->eeprom_shadow_ram != NULL) { |
| 4592 | for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { |
| 4593 | hw->eeprom_shadow_ram[i].modified = FALSE; |
| 4594 | hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; |
| 4595 | } |
| 4596 | } |
| 4597 | |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 4598 | hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) * |
| 4599 | ICH_FLASH_SECTOR_SIZE; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 4600 | |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 4601 | hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1; |
| 4602 | hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK); |
| 4603 | |
| 4604 | hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE; |
| 4605 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 4606 | hw->flash_bank_size /= 2 * sizeof(uint16_t); |
| 4607 | |
| 4608 | break; |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 4609 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4610 | default: |
| 4611 | break; |
| 4612 | } |
| 4613 | |
| 4614 | if (eeprom->type == e1000_eeprom_spi) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4615 | /* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to |
| 4616 | * 32KB (incremented by powers of 2). |
| 4617 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4618 | if (hw->mac_type <= e1000_82547_rev_2) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4619 | /* Set to default value for initial eeprom read. */ |
| 4620 | eeprom->word_size = 64; |
| 4621 | ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4622 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4623 | return ret_val; |
| 4624 | eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT; |
| 4625 | /* 256B eeprom size was not supported in earlier hardware, so we |
| 4626 | * bump eeprom_size up one to ensure that "1" (which maps to 256B) |
| 4627 | * is never the result used in the shifting logic below. */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4628 | if (eeprom_size) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4629 | eeprom_size++; |
| 4630 | } else { |
| 4631 | eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >> |
| 4632 | E1000_EECD_SIZE_EX_SHIFT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4633 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4634 | |
| 4635 | eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4636 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4637 | return ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4638 | } |
| 4639 | |
| 4640 | /****************************************************************************** |
| 4641 | * Raises the EEPROM's clock input. |
| 4642 | * |
| 4643 | * hw - Struct containing variables accessed by shared code |
| 4644 | * eecd - EECD's current value |
| 4645 | *****************************************************************************/ |
| 4646 | static void |
| 4647 | e1000_raise_ee_clk(struct e1000_hw *hw, |
| 4648 | uint32_t *eecd) |
| 4649 | { |
| 4650 | /* Raise the clock input to the EEPROM (by setting the SK bit), and then |
| 4651 | * wait <delay> microseconds. |
| 4652 | */ |
| 4653 | *eecd = *eecd | E1000_EECD_SK; |
| 4654 | E1000_WRITE_REG(hw, EECD, *eecd); |
| 4655 | E1000_WRITE_FLUSH(hw); |
| 4656 | udelay(hw->eeprom.delay_usec); |
| 4657 | } |
| 4658 | |
| 4659 | /****************************************************************************** |
| 4660 | * Lowers the EEPROM's clock input. |
| 4661 | * |
| 4662 | * hw - Struct containing variables accessed by shared code |
| 4663 | * eecd - EECD's current value |
| 4664 | *****************************************************************************/ |
| 4665 | static void |
| 4666 | e1000_lower_ee_clk(struct e1000_hw *hw, |
| 4667 | uint32_t *eecd) |
| 4668 | { |
| 4669 | /* Lower the clock input to the EEPROM (by clearing the SK bit), and then |
| 4670 | * wait 50 microseconds. |
| 4671 | */ |
| 4672 | *eecd = *eecd & ~E1000_EECD_SK; |
| 4673 | E1000_WRITE_REG(hw, EECD, *eecd); |
| 4674 | E1000_WRITE_FLUSH(hw); |
| 4675 | udelay(hw->eeprom.delay_usec); |
| 4676 | } |
| 4677 | |
| 4678 | /****************************************************************************** |
| 4679 | * Shift data bits out to the EEPROM. |
| 4680 | * |
| 4681 | * hw - Struct containing variables accessed by shared code |
| 4682 | * data - data to send to the EEPROM |
| 4683 | * count - number of bits to shift out |
| 4684 | *****************************************************************************/ |
| 4685 | static void |
| 4686 | e1000_shift_out_ee_bits(struct e1000_hw *hw, |
| 4687 | uint16_t data, |
| 4688 | uint16_t count) |
| 4689 | { |
| 4690 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
| 4691 | uint32_t eecd; |
| 4692 | uint32_t mask; |
| 4693 | |
| 4694 | /* We need to shift "count" bits out to the EEPROM. So, value in the |
| 4695 | * "data" parameter will be shifted out to the EEPROM one bit at a time. |
| 4696 | * In order to do this, "data" must be broken down into bits. |
| 4697 | */ |
| 4698 | mask = 0x01 << (count - 1); |
| 4699 | eecd = E1000_READ_REG(hw, EECD); |
| 4700 | if (eeprom->type == e1000_eeprom_microwire) { |
| 4701 | eecd &= ~E1000_EECD_DO; |
| 4702 | } else if (eeprom->type == e1000_eeprom_spi) { |
| 4703 | eecd |= E1000_EECD_DO; |
| 4704 | } |
| 4705 | do { |
| 4706 | /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1", |
| 4707 | * and then raising and then lowering the clock (the SK bit controls |
| 4708 | * the clock input to the EEPROM). A "0" is shifted out to the EEPROM |
| 4709 | * by setting "DI" to "0" and then raising and then lowering the clock. |
| 4710 | */ |
| 4711 | eecd &= ~E1000_EECD_DI; |
| 4712 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4713 | if (data & mask) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4714 | eecd |= E1000_EECD_DI; |
| 4715 | |
| 4716 | E1000_WRITE_REG(hw, EECD, eecd); |
| 4717 | E1000_WRITE_FLUSH(hw); |
| 4718 | |
| 4719 | udelay(eeprom->delay_usec); |
| 4720 | |
| 4721 | e1000_raise_ee_clk(hw, &eecd); |
| 4722 | e1000_lower_ee_clk(hw, &eecd); |
| 4723 | |
| 4724 | mask = mask >> 1; |
| 4725 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4726 | } while (mask); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4727 | |
| 4728 | /* We leave the "DI" bit set to "0" when we leave this routine. */ |
| 4729 | eecd &= ~E1000_EECD_DI; |
| 4730 | E1000_WRITE_REG(hw, EECD, eecd); |
| 4731 | } |
| 4732 | |
| 4733 | /****************************************************************************** |
| 4734 | * Shift data bits in from the EEPROM |
| 4735 | * |
| 4736 | * hw - Struct containing variables accessed by shared code |
| 4737 | *****************************************************************************/ |
| 4738 | static uint16_t |
| 4739 | e1000_shift_in_ee_bits(struct e1000_hw *hw, |
| 4740 | uint16_t count) |
| 4741 | { |
| 4742 | uint32_t eecd; |
| 4743 | uint32_t i; |
| 4744 | uint16_t data; |
| 4745 | |
| 4746 | /* In order to read a register from the EEPROM, we need to shift 'count' |
| 4747 | * bits in from the EEPROM. Bits are "shifted in" by raising the clock |
| 4748 | * input to the EEPROM (setting the SK bit), and then reading the value of |
| 4749 | * the "DO" bit. During this "shifting in" process the "DI" bit should |
| 4750 | * always be clear. |
| 4751 | */ |
| 4752 | |
| 4753 | eecd = E1000_READ_REG(hw, EECD); |
| 4754 | |
| 4755 | eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); |
| 4756 | data = 0; |
| 4757 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4758 | for (i = 0; i < count; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4759 | data = data << 1; |
| 4760 | e1000_raise_ee_clk(hw, &eecd); |
| 4761 | |
| 4762 | eecd = E1000_READ_REG(hw, EECD); |
| 4763 | |
| 4764 | eecd &= ~(E1000_EECD_DI); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4765 | if (eecd & E1000_EECD_DO) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4766 | data |= 1; |
| 4767 | |
| 4768 | e1000_lower_ee_clk(hw, &eecd); |
| 4769 | } |
| 4770 | |
| 4771 | return data; |
| 4772 | } |
| 4773 | |
| 4774 | /****************************************************************************** |
| 4775 | * Prepares EEPROM for access |
| 4776 | * |
| 4777 | * hw - Struct containing variables accessed by shared code |
| 4778 | * |
| 4779 | * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This |
| 4780 | * function should be called before issuing a command to the EEPROM. |
| 4781 | *****************************************************************************/ |
| 4782 | static int32_t |
| 4783 | e1000_acquire_eeprom(struct e1000_hw *hw) |
| 4784 | { |
| 4785 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
| 4786 | uint32_t eecd, i=0; |
| 4787 | |
| 4788 | DEBUGFUNC("e1000_acquire_eeprom"); |
| 4789 | |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 4790 | if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) |
| 4791 | return -E1000_ERR_SWFW_SYNC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4792 | eecd = E1000_READ_REG(hw, EECD); |
| 4793 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4794 | if (hw->mac_type != e1000_82573) { |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 4795 | /* Request EEPROM Access */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4796 | if (hw->mac_type > e1000_82544) { |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 4797 | eecd |= E1000_EECD_REQ; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4798 | E1000_WRITE_REG(hw, EECD, eecd); |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 4799 | eecd = E1000_READ_REG(hw, EECD); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4800 | while ((!(eecd & E1000_EECD_GNT)) && |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 4801 | (i < E1000_EEPROM_GRANT_ATTEMPTS)) { |
| 4802 | i++; |
| 4803 | udelay(5); |
| 4804 | eecd = E1000_READ_REG(hw, EECD); |
| 4805 | } |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4806 | if (!(eecd & E1000_EECD_GNT)) { |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 4807 | eecd &= ~E1000_EECD_REQ; |
| 4808 | E1000_WRITE_REG(hw, EECD, eecd); |
| 4809 | DEBUGOUT("Could not acquire EEPROM grant\n"); |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 4810 | e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 4811 | return -E1000_ERR_EEPROM; |
| 4812 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4813 | } |
| 4814 | } |
| 4815 | |
| 4816 | /* Setup EEPROM for Read/Write */ |
| 4817 | |
| 4818 | if (eeprom->type == e1000_eeprom_microwire) { |
| 4819 | /* Clear SK and DI */ |
| 4820 | eecd &= ~(E1000_EECD_DI | E1000_EECD_SK); |
| 4821 | E1000_WRITE_REG(hw, EECD, eecd); |
| 4822 | |
| 4823 | /* Set CS */ |
| 4824 | eecd |= E1000_EECD_CS; |
| 4825 | E1000_WRITE_REG(hw, EECD, eecd); |
| 4826 | } else if (eeprom->type == e1000_eeprom_spi) { |
| 4827 | /* Clear SK and CS */ |
| 4828 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
| 4829 | E1000_WRITE_REG(hw, EECD, eecd); |
| 4830 | udelay(1); |
| 4831 | } |
| 4832 | |
| 4833 | return E1000_SUCCESS; |
| 4834 | } |
| 4835 | |
| 4836 | /****************************************************************************** |
| 4837 | * Returns EEPROM to a "standby" state |
| 4838 | * |
| 4839 | * hw - Struct containing variables accessed by shared code |
| 4840 | *****************************************************************************/ |
| 4841 | static void |
| 4842 | e1000_standby_eeprom(struct e1000_hw *hw) |
| 4843 | { |
| 4844 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
| 4845 | uint32_t eecd; |
| 4846 | |
| 4847 | eecd = E1000_READ_REG(hw, EECD); |
| 4848 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4849 | if (eeprom->type == e1000_eeprom_microwire) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4850 | eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); |
| 4851 | E1000_WRITE_REG(hw, EECD, eecd); |
| 4852 | E1000_WRITE_FLUSH(hw); |
| 4853 | udelay(eeprom->delay_usec); |
| 4854 | |
| 4855 | /* Clock high */ |
| 4856 | eecd |= E1000_EECD_SK; |
| 4857 | E1000_WRITE_REG(hw, EECD, eecd); |
| 4858 | E1000_WRITE_FLUSH(hw); |
| 4859 | udelay(eeprom->delay_usec); |
| 4860 | |
| 4861 | /* Select EEPROM */ |
| 4862 | eecd |= E1000_EECD_CS; |
| 4863 | E1000_WRITE_REG(hw, EECD, eecd); |
| 4864 | E1000_WRITE_FLUSH(hw); |
| 4865 | udelay(eeprom->delay_usec); |
| 4866 | |
| 4867 | /* Clock low */ |
| 4868 | eecd &= ~E1000_EECD_SK; |
| 4869 | E1000_WRITE_REG(hw, EECD, eecd); |
| 4870 | E1000_WRITE_FLUSH(hw); |
| 4871 | udelay(eeprom->delay_usec); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4872 | } else if (eeprom->type == e1000_eeprom_spi) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4873 | /* Toggle CS to flush commands */ |
| 4874 | eecd |= E1000_EECD_CS; |
| 4875 | E1000_WRITE_REG(hw, EECD, eecd); |
| 4876 | E1000_WRITE_FLUSH(hw); |
| 4877 | udelay(eeprom->delay_usec); |
| 4878 | eecd &= ~E1000_EECD_CS; |
| 4879 | E1000_WRITE_REG(hw, EECD, eecd); |
| 4880 | E1000_WRITE_FLUSH(hw); |
| 4881 | udelay(eeprom->delay_usec); |
| 4882 | } |
| 4883 | } |
| 4884 | |
| 4885 | /****************************************************************************** |
| 4886 | * Terminates a command by inverting the EEPROM's chip select pin |
| 4887 | * |
| 4888 | * hw - Struct containing variables accessed by shared code |
| 4889 | *****************************************************************************/ |
| 4890 | static void |
| 4891 | e1000_release_eeprom(struct e1000_hw *hw) |
| 4892 | { |
| 4893 | uint32_t eecd; |
| 4894 | |
| 4895 | DEBUGFUNC("e1000_release_eeprom"); |
| 4896 | |
| 4897 | eecd = E1000_READ_REG(hw, EECD); |
| 4898 | |
| 4899 | if (hw->eeprom.type == e1000_eeprom_spi) { |
| 4900 | eecd |= E1000_EECD_CS; /* Pull CS high */ |
| 4901 | eecd &= ~E1000_EECD_SK; /* Lower SCK */ |
| 4902 | |
| 4903 | E1000_WRITE_REG(hw, EECD, eecd); |
| 4904 | |
| 4905 | udelay(hw->eeprom.delay_usec); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4906 | } else if (hw->eeprom.type == e1000_eeprom_microwire) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4907 | /* cleanup eeprom */ |
| 4908 | |
| 4909 | /* CS on Microwire is active-high */ |
| 4910 | eecd &= ~(E1000_EECD_CS | E1000_EECD_DI); |
| 4911 | |
| 4912 | E1000_WRITE_REG(hw, EECD, eecd); |
| 4913 | |
| 4914 | /* Rising edge of clock */ |
| 4915 | eecd |= E1000_EECD_SK; |
| 4916 | E1000_WRITE_REG(hw, EECD, eecd); |
| 4917 | E1000_WRITE_FLUSH(hw); |
| 4918 | udelay(hw->eeprom.delay_usec); |
| 4919 | |
| 4920 | /* Falling edge of clock */ |
| 4921 | eecd &= ~E1000_EECD_SK; |
| 4922 | E1000_WRITE_REG(hw, EECD, eecd); |
| 4923 | E1000_WRITE_FLUSH(hw); |
| 4924 | udelay(hw->eeprom.delay_usec); |
| 4925 | } |
| 4926 | |
| 4927 | /* Stop requesting EEPROM access */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4928 | if (hw->mac_type > e1000_82544) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4929 | eecd &= ~E1000_EECD_REQ; |
| 4930 | E1000_WRITE_REG(hw, EECD, eecd); |
| 4931 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4932 | |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 4933 | e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4934 | } |
| 4935 | |
| 4936 | /****************************************************************************** |
| 4937 | * Reads a 16 bit word from the EEPROM. |
| 4938 | * |
| 4939 | * hw - Struct containing variables accessed by shared code |
| 4940 | *****************************************************************************/ |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 4941 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4942 | e1000_spi_eeprom_ready(struct e1000_hw *hw) |
| 4943 | { |
| 4944 | uint16_t retry_count = 0; |
| 4945 | uint8_t spi_stat_reg; |
| 4946 | |
| 4947 | DEBUGFUNC("e1000_spi_eeprom_ready"); |
| 4948 | |
| 4949 | /* Read "Status Register" repeatedly until the LSB is cleared. The |
| 4950 | * EEPROM will signal that the command has been completed by clearing |
| 4951 | * bit 0 of the internal status register. If it's not cleared within |
| 4952 | * 5 milliseconds, then error out. |
| 4953 | */ |
| 4954 | retry_count = 0; |
| 4955 | do { |
| 4956 | e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI, |
| 4957 | hw->eeprom.opcode_bits); |
| 4958 | spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8); |
| 4959 | if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI)) |
| 4960 | break; |
| 4961 | |
| 4962 | udelay(5); |
| 4963 | retry_count += 5; |
| 4964 | |
| 4965 | e1000_standby_eeprom(hw); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4966 | } while (retry_count < EEPROM_MAX_RETRY_SPI); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4967 | |
| 4968 | /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and |
| 4969 | * only 0-5mSec on 5V devices) |
| 4970 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 4971 | if (retry_count >= EEPROM_MAX_RETRY_SPI) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4972 | DEBUGOUT("SPI EEPROM Status error\n"); |
| 4973 | return -E1000_ERR_EEPROM; |
| 4974 | } |
| 4975 | |
| 4976 | return E1000_SUCCESS; |
| 4977 | } |
| 4978 | |
| 4979 | /****************************************************************************** |
| 4980 | * Reads a 16 bit word from the EEPROM. |
| 4981 | * |
| 4982 | * hw - Struct containing variables accessed by shared code |
| 4983 | * offset - offset of word in the EEPROM to read |
| 4984 | * data - word read from the EEPROM |
| 4985 | * words - number of words to read |
| 4986 | *****************************************************************************/ |
| 4987 | int32_t |
| 4988 | e1000_read_eeprom(struct e1000_hw *hw, |
| 4989 | uint16_t offset, |
| 4990 | uint16_t words, |
| 4991 | uint16_t *data) |
| 4992 | { |
| 4993 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
| 4994 | uint32_t i = 0; |
| 4995 | |
| 4996 | DEBUGFUNC("e1000_read_eeprom"); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 4997 | |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 4998 | /* If eeprom is not yet detected, do so now */ |
| 4999 | if (eeprom->word_size == 0) |
| 5000 | e1000_init_eeprom_params(hw); |
| 5001 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5002 | /* A check for invalid values: offset too large, too many words, and not |
| 5003 | * enough words. |
| 5004 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5005 | if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5006 | (words == 0)) { |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 5007 | DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5008 | return -E1000_ERR_EEPROM; |
| 5009 | } |
| 5010 | |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 5011 | /* EEPROM's that don't use EERD to read require us to bit-bang the SPI |
| 5012 | * directly. In this case, we need to acquire the EEPROM so that |
| 5013 | * FW or other port software does not interrupt. |
| 5014 | */ |
Jeff Kirsher | 4d351858 | 2006-01-12 16:50:48 -0800 | [diff] [blame] | 5015 | if (e1000_is_onboard_nvm_eeprom(hw) == TRUE && |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5016 | hw->eeprom.use_eerd == FALSE) { |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 5017 | /* Prepare the EEPROM for bit-bang reading */ |
| 5018 | if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) |
| 5019 | return -E1000_ERR_EEPROM; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5020 | } |
| 5021 | |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 5022 | /* Eerd register EEPROM access requires no eeprom aquire/release */ |
| 5023 | if (eeprom->use_eerd == TRUE) |
| 5024 | return e1000_read_eeprom_eerd(hw, offset, words, data); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5025 | |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 5026 | /* ICH EEPROM access is done via the ICH flash controller */ |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5027 | if (eeprom->type == e1000_eeprom_ich8) |
| 5028 | return e1000_read_eeprom_ich8(hw, offset, words, data); |
| 5029 | |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 5030 | /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have |
| 5031 | * acquired the EEPROM at this point, so any returns should relase it */ |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5032 | if (eeprom->type == e1000_eeprom_spi) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5033 | uint16_t word_in; |
| 5034 | uint8_t read_opcode = EEPROM_READ_OPCODE_SPI; |
| 5035 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5036 | if (e1000_spi_eeprom_ready(hw)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5037 | e1000_release_eeprom(hw); |
| 5038 | return -E1000_ERR_EEPROM; |
| 5039 | } |
| 5040 | |
| 5041 | e1000_standby_eeprom(hw); |
| 5042 | |
| 5043 | /* Some SPI eeproms use the 8th address bit embedded in the opcode */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5044 | if ((eeprom->address_bits == 8) && (offset >= 128)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5045 | read_opcode |= EEPROM_A8_OPCODE_SPI; |
| 5046 | |
| 5047 | /* Send the READ command (opcode + addr) */ |
| 5048 | e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); |
| 5049 | e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits); |
| 5050 | |
| 5051 | /* Read the data. The address of the eeprom internally increments with |
| 5052 | * each byte (spi) being read, saving on the overhead of eeprom setup |
| 5053 | * and tear-down. The address counter will roll over if reading beyond |
| 5054 | * the size of the eeprom, thus allowing the entire memory to be read |
| 5055 | * starting from any offset. */ |
| 5056 | for (i = 0; i < words; i++) { |
| 5057 | word_in = e1000_shift_in_ee_bits(hw, 16); |
| 5058 | data[i] = (word_in >> 8) | (word_in << 8); |
| 5059 | } |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5060 | } else if (eeprom->type == e1000_eeprom_microwire) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5061 | for (i = 0; i < words; i++) { |
| 5062 | /* Send the READ command (opcode + addr) */ |
| 5063 | e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE, |
| 5064 | eeprom->opcode_bits); |
| 5065 | e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i), |
| 5066 | eeprom->address_bits); |
| 5067 | |
| 5068 | /* Read the data. For microwire, each word requires the overhead |
| 5069 | * of eeprom setup and tear-down. */ |
| 5070 | data[i] = e1000_shift_in_ee_bits(hw, 16); |
| 5071 | e1000_standby_eeprom(hw); |
| 5072 | } |
| 5073 | } |
| 5074 | |
| 5075 | /* End this read operation */ |
| 5076 | e1000_release_eeprom(hw); |
| 5077 | |
| 5078 | return E1000_SUCCESS; |
| 5079 | } |
| 5080 | |
| 5081 | /****************************************************************************** |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5082 | * Reads a 16 bit word from the EEPROM using the EERD register. |
| 5083 | * |
| 5084 | * hw - Struct containing variables accessed by shared code |
| 5085 | * offset - offset of word in the EEPROM to read |
| 5086 | * data - word read from the EEPROM |
| 5087 | * words - number of words to read |
| 5088 | *****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 5089 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5090 | e1000_read_eeprom_eerd(struct e1000_hw *hw, |
| 5091 | uint16_t offset, |
| 5092 | uint16_t words, |
| 5093 | uint16_t *data) |
| 5094 | { |
| 5095 | uint32_t i, eerd = 0; |
| 5096 | int32_t error = 0; |
| 5097 | |
| 5098 | for (i = 0; i < words; i++) { |
| 5099 | eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) + |
| 5100 | E1000_EEPROM_RW_REG_START; |
| 5101 | |
| 5102 | E1000_WRITE_REG(hw, EERD, eerd); |
| 5103 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ); |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 5104 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5105 | if (error) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5106 | break; |
| 5107 | } |
| 5108 | data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA); |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 5109 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5110 | } |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 5111 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5112 | return error; |
| 5113 | } |
| 5114 | |
| 5115 | /****************************************************************************** |
| 5116 | * Writes a 16 bit word from the EEPROM using the EEWR register. |
| 5117 | * |
| 5118 | * hw - Struct containing variables accessed by shared code |
| 5119 | * offset - offset of word in the EEPROM to read |
| 5120 | * data - word read from the EEPROM |
| 5121 | * words - number of words to read |
| 5122 | *****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 5123 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5124 | e1000_write_eeprom_eewr(struct e1000_hw *hw, |
| 5125 | uint16_t offset, |
| 5126 | uint16_t words, |
| 5127 | uint16_t *data) |
| 5128 | { |
| 5129 | uint32_t register_value = 0; |
| 5130 | uint32_t i = 0; |
| 5131 | int32_t error = 0; |
| 5132 | |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 5133 | if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM)) |
| 5134 | return -E1000_ERR_SWFW_SYNC; |
| 5135 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5136 | for (i = 0; i < words; i++) { |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 5137 | register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) | |
| 5138 | ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5139 | E1000_EEPROM_RW_REG_START; |
| 5140 | |
| 5141 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5142 | if (error) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5143 | break; |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 5144 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5145 | |
| 5146 | E1000_WRITE_REG(hw, EEWR, register_value); |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 5147 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5148 | error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE); |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 5149 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5150 | if (error) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5151 | break; |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 5152 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5153 | } |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 5154 | |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 5155 | e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5156 | return error; |
| 5157 | } |
| 5158 | |
| 5159 | /****************************************************************************** |
| 5160 | * Polls the status bit (bit 1) of the EERD to determine when the read is done. |
| 5161 | * |
| 5162 | * hw - Struct containing variables accessed by shared code |
| 5163 | *****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 5164 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5165 | e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd) |
| 5166 | { |
| 5167 | uint32_t attempts = 100000; |
| 5168 | uint32_t i, reg = 0; |
| 5169 | int32_t done = E1000_ERR_EEPROM; |
| 5170 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5171 | for (i = 0; i < attempts; i++) { |
| 5172 | if (eerd == E1000_EEPROM_POLL_READ) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5173 | reg = E1000_READ_REG(hw, EERD); |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 5174 | else |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5175 | reg = E1000_READ_REG(hw, EEWR); |
| 5176 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5177 | if (reg & E1000_EEPROM_RW_REG_DONE) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5178 | done = E1000_SUCCESS; |
| 5179 | break; |
| 5180 | } |
| 5181 | udelay(5); |
| 5182 | } |
| 5183 | |
| 5184 | return done; |
| 5185 | } |
| 5186 | |
| 5187 | /*************************************************************************** |
| 5188 | * Description: Determines if the onboard NVM is FLASH or EEPROM. |
| 5189 | * |
| 5190 | * hw - Struct containing variables accessed by shared code |
| 5191 | ****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 5192 | static boolean_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5193 | e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw) |
| 5194 | { |
| 5195 | uint32_t eecd = 0; |
| 5196 | |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 5197 | DEBUGFUNC("e1000_is_onboard_nvm_eeprom"); |
| 5198 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5199 | if (hw->mac_type == e1000_ich8lan) |
| 5200 | return FALSE; |
| 5201 | |
| 5202 | if (hw->mac_type == e1000_82573) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5203 | eecd = E1000_READ_REG(hw, EECD); |
| 5204 | |
| 5205 | /* Isolate bits 15 & 16 */ |
| 5206 | eecd = ((eecd >> 15) & 0x03); |
| 5207 | |
| 5208 | /* If both bits are set, device is Flash type */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5209 | if (eecd == 0x03) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5210 | return FALSE; |
| 5211 | } |
| 5212 | } |
| 5213 | return TRUE; |
| 5214 | } |
| 5215 | |
| 5216 | /****************************************************************************** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5217 | * Verifies that the EEPROM has a valid checksum |
| 5218 | * |
| 5219 | * hw - Struct containing variables accessed by shared code |
| 5220 | * |
| 5221 | * Reads the first 64 16 bit words of the EEPROM and sums the values read. |
| 5222 | * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is |
| 5223 | * valid. |
| 5224 | *****************************************************************************/ |
| 5225 | int32_t |
| 5226 | e1000_validate_eeprom_checksum(struct e1000_hw *hw) |
| 5227 | { |
| 5228 | uint16_t checksum = 0; |
| 5229 | uint16_t i, eeprom_data; |
| 5230 | |
| 5231 | DEBUGFUNC("e1000_validate_eeprom_checksum"); |
| 5232 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5233 | if ((hw->mac_type == e1000_82573) && |
| 5234 | (e1000_is_onboard_nvm_eeprom(hw) == FALSE)) { |
| 5235 | /* Check bit 4 of word 10h. If it is 0, firmware is done updating |
| 5236 | * 10h-12h. Checksum may need to be fixed. */ |
| 5237 | e1000_read_eeprom(hw, 0x10, 1, &eeprom_data); |
| 5238 | if ((eeprom_data & 0x10) == 0) { |
| 5239 | /* Read 0x23 and check bit 15. This bit is a 1 when the checksum |
| 5240 | * has already been fixed. If the checksum is still wrong and this |
| 5241 | * bit is a 1, we need to return bad checksum. Otherwise, we need |
| 5242 | * to set this bit to a 1 and update the checksum. */ |
| 5243 | e1000_read_eeprom(hw, 0x23, 1, &eeprom_data); |
| 5244 | if ((eeprom_data & 0x8000) == 0) { |
| 5245 | eeprom_data |= 0x8000; |
| 5246 | e1000_write_eeprom(hw, 0x23, 1, &eeprom_data); |
| 5247 | e1000_update_eeprom_checksum(hw); |
| 5248 | } |
| 5249 | } |
| 5250 | } |
| 5251 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5252 | if (hw->mac_type == e1000_ich8lan) { |
| 5253 | /* Drivers must allocate the shadow ram structure for the |
| 5254 | * EEPROM checksum to be updated. Otherwise, this bit as well |
| 5255 | * as the checksum must both be set correctly for this |
| 5256 | * validation to pass. |
| 5257 | */ |
| 5258 | e1000_read_eeprom(hw, 0x19, 1, &eeprom_data); |
| 5259 | if ((eeprom_data & 0x40) == 0) { |
| 5260 | eeprom_data |= 0x40; |
| 5261 | e1000_write_eeprom(hw, 0x19, 1, &eeprom_data); |
| 5262 | e1000_update_eeprom_checksum(hw); |
| 5263 | } |
| 5264 | } |
| 5265 | |
| 5266 | for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) { |
| 5267 | if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5268 | DEBUGOUT("EEPROM Read Error\n"); |
| 5269 | return -E1000_ERR_EEPROM; |
| 5270 | } |
| 5271 | checksum += eeprom_data; |
| 5272 | } |
| 5273 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5274 | if (checksum == (uint16_t) EEPROM_SUM) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5275 | return E1000_SUCCESS; |
| 5276 | else { |
| 5277 | DEBUGOUT("EEPROM Checksum Invalid\n"); |
| 5278 | return -E1000_ERR_EEPROM; |
| 5279 | } |
| 5280 | } |
| 5281 | |
| 5282 | /****************************************************************************** |
| 5283 | * Calculates the EEPROM checksum and writes it to the EEPROM |
| 5284 | * |
| 5285 | * hw - Struct containing variables accessed by shared code |
| 5286 | * |
| 5287 | * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA. |
| 5288 | * Writes the difference to word offset 63 of the EEPROM. |
| 5289 | *****************************************************************************/ |
| 5290 | int32_t |
| 5291 | e1000_update_eeprom_checksum(struct e1000_hw *hw) |
| 5292 | { |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5293 | uint32_t ctrl_ext; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5294 | uint16_t checksum = 0; |
| 5295 | uint16_t i, eeprom_data; |
| 5296 | |
| 5297 | DEBUGFUNC("e1000_update_eeprom_checksum"); |
| 5298 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5299 | for (i = 0; i < EEPROM_CHECKSUM_REG; i++) { |
| 5300 | if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5301 | DEBUGOUT("EEPROM Read Error\n"); |
| 5302 | return -E1000_ERR_EEPROM; |
| 5303 | } |
| 5304 | checksum += eeprom_data; |
| 5305 | } |
| 5306 | checksum = (uint16_t) EEPROM_SUM - checksum; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5307 | if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5308 | DEBUGOUT("EEPROM Write Error\n"); |
| 5309 | return -E1000_ERR_EEPROM; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5310 | } else if (hw->eeprom.type == e1000_eeprom_flash) { |
| 5311 | e1000_commit_shadow_ram(hw); |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5312 | } else if (hw->eeprom.type == e1000_eeprom_ich8) { |
| 5313 | e1000_commit_shadow_ram(hw); |
| 5314 | /* Reload the EEPROM, or else modifications will not appear |
| 5315 | * until after next adapter reset. */ |
| 5316 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
| 5317 | ctrl_ext |= E1000_CTRL_EXT_EE_RST; |
| 5318 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 5319 | msleep(10); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5320 | } |
| 5321 | return E1000_SUCCESS; |
| 5322 | } |
| 5323 | |
| 5324 | /****************************************************************************** |
| 5325 | * Parent function for writing words to the different EEPROM types. |
| 5326 | * |
| 5327 | * hw - Struct containing variables accessed by shared code |
| 5328 | * offset - offset within the EEPROM to be written to |
| 5329 | * words - number of words to write |
| 5330 | * data - 16 bit word to be written to the EEPROM |
| 5331 | * |
| 5332 | * If e1000_update_eeprom_checksum is not called after this function, the |
| 5333 | * EEPROM will most likely contain an invalid checksum. |
| 5334 | *****************************************************************************/ |
| 5335 | int32_t |
| 5336 | e1000_write_eeprom(struct e1000_hw *hw, |
| 5337 | uint16_t offset, |
| 5338 | uint16_t words, |
| 5339 | uint16_t *data) |
| 5340 | { |
| 5341 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
| 5342 | int32_t status = 0; |
| 5343 | |
| 5344 | DEBUGFUNC("e1000_write_eeprom"); |
| 5345 | |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 5346 | /* If eeprom is not yet detected, do so now */ |
| 5347 | if (eeprom->word_size == 0) |
| 5348 | e1000_init_eeprom_params(hw); |
| 5349 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5350 | /* A check for invalid values: offset too large, too many words, and not |
| 5351 | * enough words. |
| 5352 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5353 | if ((offset >= eeprom->word_size) || (words > eeprom->word_size - offset) || |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5354 | (words == 0)) { |
| 5355 | DEBUGOUT("\"words\" parameter out of bounds\n"); |
| 5356 | return -E1000_ERR_EEPROM; |
| 5357 | } |
| 5358 | |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 5359 | /* 82573 writes only through eewr */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5360 | if (eeprom->use_eewr == TRUE) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5361 | return e1000_write_eeprom_eewr(hw, offset, words, data); |
| 5362 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5363 | if (eeprom->type == e1000_eeprom_ich8) |
| 5364 | return e1000_write_eeprom_ich8(hw, offset, words, data); |
| 5365 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5366 | /* Prepare the EEPROM for writing */ |
| 5367 | if (e1000_acquire_eeprom(hw) != E1000_SUCCESS) |
| 5368 | return -E1000_ERR_EEPROM; |
| 5369 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5370 | if (eeprom->type == e1000_eeprom_microwire) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5371 | status = e1000_write_eeprom_microwire(hw, offset, words, data); |
| 5372 | } else { |
| 5373 | status = e1000_write_eeprom_spi(hw, offset, words, data); |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 5374 | msleep(10); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5375 | } |
| 5376 | |
| 5377 | /* Done with writing */ |
| 5378 | e1000_release_eeprom(hw); |
| 5379 | |
| 5380 | return status; |
| 5381 | } |
| 5382 | |
| 5383 | /****************************************************************************** |
| 5384 | * Writes a 16 bit word to a given offset in an SPI EEPROM. |
| 5385 | * |
| 5386 | * hw - Struct containing variables accessed by shared code |
| 5387 | * offset - offset within the EEPROM to be written to |
| 5388 | * words - number of words to write |
| 5389 | * data - pointer to array of 8 bit words to be written to the EEPROM |
| 5390 | * |
| 5391 | *****************************************************************************/ |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 5392 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5393 | e1000_write_eeprom_spi(struct e1000_hw *hw, |
| 5394 | uint16_t offset, |
| 5395 | uint16_t words, |
| 5396 | uint16_t *data) |
| 5397 | { |
| 5398 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
| 5399 | uint16_t widx = 0; |
| 5400 | |
| 5401 | DEBUGFUNC("e1000_write_eeprom_spi"); |
| 5402 | |
| 5403 | while (widx < words) { |
| 5404 | uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI; |
| 5405 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5406 | if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5407 | |
| 5408 | e1000_standby_eeprom(hw); |
| 5409 | |
| 5410 | /* Send the WRITE ENABLE command (8 bit opcode ) */ |
| 5411 | e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI, |
| 5412 | eeprom->opcode_bits); |
| 5413 | |
| 5414 | e1000_standby_eeprom(hw); |
| 5415 | |
| 5416 | /* Some SPI eeproms use the 8th address bit embedded in the opcode */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5417 | if ((eeprom->address_bits == 8) && (offset >= 128)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5418 | write_opcode |= EEPROM_A8_OPCODE_SPI; |
| 5419 | |
| 5420 | /* Send the Write command (8-bit opcode + addr) */ |
| 5421 | e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits); |
| 5422 | |
| 5423 | e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2), |
| 5424 | eeprom->address_bits); |
| 5425 | |
| 5426 | /* Send the data */ |
| 5427 | |
| 5428 | /* Loop to allow for up to whole page write (32 bytes) of eeprom */ |
| 5429 | while (widx < words) { |
| 5430 | uint16_t word_out = data[widx]; |
| 5431 | word_out = (word_out >> 8) | (word_out << 8); |
| 5432 | e1000_shift_out_ee_bits(hw, word_out, 16); |
| 5433 | widx++; |
| 5434 | |
| 5435 | /* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE |
| 5436 | * operation, while the smaller eeproms are capable of an 8-byte |
| 5437 | * PAGE WRITE operation. Break the inner loop to pass new address |
| 5438 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5439 | if ((((offset + widx)*2) % eeprom->page_size) == 0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5440 | e1000_standby_eeprom(hw); |
| 5441 | break; |
| 5442 | } |
| 5443 | } |
| 5444 | } |
| 5445 | |
| 5446 | return E1000_SUCCESS; |
| 5447 | } |
| 5448 | |
| 5449 | /****************************************************************************** |
| 5450 | * Writes a 16 bit word to a given offset in a Microwire EEPROM. |
| 5451 | * |
| 5452 | * hw - Struct containing variables accessed by shared code |
| 5453 | * offset - offset within the EEPROM to be written to |
| 5454 | * words - number of words to write |
| 5455 | * data - pointer to array of 16 bit words to be written to the EEPROM |
| 5456 | * |
| 5457 | *****************************************************************************/ |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 5458 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5459 | e1000_write_eeprom_microwire(struct e1000_hw *hw, |
| 5460 | uint16_t offset, |
| 5461 | uint16_t words, |
| 5462 | uint16_t *data) |
| 5463 | { |
| 5464 | struct e1000_eeprom_info *eeprom = &hw->eeprom; |
| 5465 | uint32_t eecd; |
| 5466 | uint16_t words_written = 0; |
| 5467 | uint16_t i = 0; |
| 5468 | |
| 5469 | DEBUGFUNC("e1000_write_eeprom_microwire"); |
| 5470 | |
| 5471 | /* Send the write enable command to the EEPROM (3-bit opcode plus |
| 5472 | * 6/8-bit dummy address beginning with 11). It's less work to include |
| 5473 | * the 11 of the dummy address as part of the opcode than it is to shift |
| 5474 | * it over the correct number of bits for the address. This puts the |
| 5475 | * EEPROM into write/erase mode. |
| 5476 | */ |
| 5477 | e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE, |
| 5478 | (uint16_t)(eeprom->opcode_bits + 2)); |
| 5479 | |
| 5480 | e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); |
| 5481 | |
| 5482 | /* Prepare the EEPROM */ |
| 5483 | e1000_standby_eeprom(hw); |
| 5484 | |
| 5485 | while (words_written < words) { |
| 5486 | /* Send the Write command (3-bit opcode + addr) */ |
| 5487 | e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE, |
| 5488 | eeprom->opcode_bits); |
| 5489 | |
| 5490 | e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written), |
| 5491 | eeprom->address_bits); |
| 5492 | |
| 5493 | /* Send the data */ |
| 5494 | e1000_shift_out_ee_bits(hw, data[words_written], 16); |
| 5495 | |
| 5496 | /* Toggle the CS line. This in effect tells the EEPROM to execute |
| 5497 | * the previous command. |
| 5498 | */ |
| 5499 | e1000_standby_eeprom(hw); |
| 5500 | |
| 5501 | /* Read DO repeatedly until it is high (equal to '1'). The EEPROM will |
| 5502 | * signal that the command has been completed by raising the DO signal. |
| 5503 | * If DO does not go high in 10 milliseconds, then error out. |
| 5504 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5505 | for (i = 0; i < 200; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5506 | eecd = E1000_READ_REG(hw, EECD); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5507 | if (eecd & E1000_EECD_DO) break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5508 | udelay(50); |
| 5509 | } |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5510 | if (i == 200) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5511 | DEBUGOUT("EEPROM Write did not complete\n"); |
| 5512 | return -E1000_ERR_EEPROM; |
| 5513 | } |
| 5514 | |
| 5515 | /* Recover from write */ |
| 5516 | e1000_standby_eeprom(hw); |
| 5517 | |
| 5518 | words_written++; |
| 5519 | } |
| 5520 | |
| 5521 | /* Send the write disable command to the EEPROM (3-bit opcode plus |
| 5522 | * 6/8-bit dummy address beginning with 10). It's less work to include |
| 5523 | * the 10 of the dummy address as part of the opcode than it is to shift |
| 5524 | * it over the correct number of bits for the address. This takes the |
| 5525 | * EEPROM out of write/erase mode. |
| 5526 | */ |
| 5527 | e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE, |
| 5528 | (uint16_t)(eeprom->opcode_bits + 2)); |
| 5529 | |
| 5530 | e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2)); |
| 5531 | |
| 5532 | return E1000_SUCCESS; |
| 5533 | } |
| 5534 | |
| 5535 | /****************************************************************************** |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5536 | * Flushes the cached eeprom to NVM. This is done by saving the modified values |
| 5537 | * in the eeprom cache and the non modified values in the currently active bank |
| 5538 | * to the new bank. |
| 5539 | * |
| 5540 | * hw - Struct containing variables accessed by shared code |
| 5541 | * offset - offset of word in the EEPROM to read |
| 5542 | * data - word read from the EEPROM |
| 5543 | * words - number of words to read |
| 5544 | *****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 5545 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5546 | e1000_commit_shadow_ram(struct e1000_hw *hw) |
| 5547 | { |
| 5548 | uint32_t attempts = 100000; |
| 5549 | uint32_t eecd = 0; |
| 5550 | uint32_t flop = 0; |
| 5551 | uint32_t i = 0; |
| 5552 | int32_t error = E1000_SUCCESS; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5553 | uint32_t old_bank_offset = 0; |
| 5554 | uint32_t new_bank_offset = 0; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5555 | uint8_t low_byte = 0; |
| 5556 | uint8_t high_byte = 0; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5557 | boolean_t sector_write_failed = FALSE; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5558 | |
| 5559 | if (hw->mac_type == e1000_82573) { |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5560 | /* The flop register will be used to determine if flash type is STM */ |
| 5561 | flop = E1000_READ_REG(hw, FLOP); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5562 | for (i=0; i < attempts; i++) { |
| 5563 | eecd = E1000_READ_REG(hw, EECD); |
| 5564 | if ((eecd & E1000_EECD_FLUPD) == 0) { |
| 5565 | break; |
| 5566 | } |
| 5567 | udelay(5); |
| 5568 | } |
| 5569 | |
| 5570 | if (i == attempts) { |
| 5571 | return -E1000_ERR_EEPROM; |
| 5572 | } |
| 5573 | |
Jesse Brandeburg | 96838a4 | 2006-01-18 13:01:39 -0800 | [diff] [blame] | 5574 | /* If STM opcode located in bits 15:8 of flop, reset firmware */ |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5575 | if ((flop & 0xFF00) == E1000_STM_OPCODE) { |
| 5576 | E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET); |
| 5577 | } |
| 5578 | |
| 5579 | /* Perform the flash update */ |
| 5580 | E1000_WRITE_REG(hw, EECD, eecd | E1000_EECD_FLUPD); |
| 5581 | |
Jesse Brandeburg | 96838a4 | 2006-01-18 13:01:39 -0800 | [diff] [blame] | 5582 | for (i=0; i < attempts; i++) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5583 | eecd = E1000_READ_REG(hw, EECD); |
| 5584 | if ((eecd & E1000_EECD_FLUPD) == 0) { |
| 5585 | break; |
| 5586 | } |
| 5587 | udelay(5); |
| 5588 | } |
| 5589 | |
| 5590 | if (i == attempts) { |
| 5591 | return -E1000_ERR_EEPROM; |
| 5592 | } |
| 5593 | } |
| 5594 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5595 | if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) { |
| 5596 | /* We're writing to the opposite bank so if we're on bank 1, |
| 5597 | * write to bank 0 etc. We also need to erase the segment that |
| 5598 | * is going to be written */ |
| 5599 | if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) { |
| 5600 | new_bank_offset = hw->flash_bank_size * 2; |
| 5601 | old_bank_offset = 0; |
| 5602 | e1000_erase_ich8_4k_segment(hw, 1); |
| 5603 | } else { |
| 5604 | old_bank_offset = hw->flash_bank_size * 2; |
| 5605 | new_bank_offset = 0; |
| 5606 | e1000_erase_ich8_4k_segment(hw, 0); |
| 5607 | } |
| 5608 | |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 5609 | sector_write_failed = FALSE; |
| 5610 | /* Loop for every byte in the shadow RAM, |
| 5611 | * which is in units of words. */ |
| 5612 | for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { |
| 5613 | /* Determine whether to write the value stored |
| 5614 | * in the other NVM bank or a modified value stored |
| 5615 | * in the shadow RAM */ |
| 5616 | if (hw->eeprom_shadow_ram[i].modified == TRUE) { |
| 5617 | low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word; |
| 5618 | udelay(100); |
| 5619 | error = e1000_verify_write_ich8_byte(hw, |
| 5620 | (i << 1) + new_bank_offset, low_byte); |
| 5621 | |
| 5622 | if (error != E1000_SUCCESS) |
| 5623 | sector_write_failed = TRUE; |
| 5624 | else { |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5625 | high_byte = |
| 5626 | (uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8); |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5627 | udelay(100); |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 5628 | } |
| 5629 | } else { |
| 5630 | e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset, |
| 5631 | &low_byte); |
| 5632 | udelay(100); |
| 5633 | error = e1000_verify_write_ich8_byte(hw, |
| 5634 | (i << 1) + new_bank_offset, low_byte); |
| 5635 | |
| 5636 | if (error != E1000_SUCCESS) |
| 5637 | sector_write_failed = TRUE; |
| 5638 | else { |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5639 | e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1, |
| 5640 | &high_byte); |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 5641 | udelay(100); |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5642 | } |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 5643 | } |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5644 | |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 5645 | /* If the write of the low byte was successful, go ahread and |
| 5646 | * write the high byte while checking to make sure that if it |
| 5647 | * is the signature byte, then it is handled properly */ |
| 5648 | if (sector_write_failed == FALSE) { |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5649 | /* If the word is 0x13, then make sure the signature bits |
| 5650 | * (15:14) are 11b until the commit has completed. |
| 5651 | * This will allow us to write 10b which indicates the |
| 5652 | * signature is valid. We want to do this after the write |
| 5653 | * has completed so that we don't mark the segment valid |
| 5654 | * while the write is still in progress */ |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 5655 | if (i == E1000_ICH_NVM_SIG_WORD) |
| 5656 | high_byte = E1000_ICH_NVM_SIG_MASK | high_byte; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5657 | |
| 5658 | error = e1000_verify_write_ich8_byte(hw, |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 5659 | (i << 1) + new_bank_offset + 1, high_byte); |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5660 | if (error != E1000_SUCCESS) |
| 5661 | sector_write_failed = TRUE; |
| 5662 | |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 5663 | } else { |
| 5664 | /* If the write failed then break from the loop and |
| 5665 | * return an error */ |
| 5666 | break; |
| 5667 | } |
| 5668 | } |
| 5669 | |
| 5670 | /* Don't bother writing the segment valid bits if sector |
| 5671 | * programming failed. */ |
| 5672 | if (sector_write_failed == FALSE) { |
| 5673 | /* Finally validate the new segment by setting bit 15:14 |
| 5674 | * to 10b in word 0x13 , this can be done without an |
| 5675 | * erase as well since these bits are 11 to start with |
| 5676 | * and we need to change bit 14 to 0b */ |
| 5677 | e1000_read_ich8_byte(hw, |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 5678 | E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 5679 | &high_byte); |
| 5680 | high_byte &= 0xBF; |
| 5681 | error = e1000_verify_write_ich8_byte(hw, |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 5682 | E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte); |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 5683 | /* And invalidate the previously valid segment by setting |
| 5684 | * its signature word (0x13) high_byte to 0b. This can be |
| 5685 | * done without an erase because flash erase sets all bits |
| 5686 | * to 1's. We can write 1's to 0's without an erase */ |
| 5687 | if (error == E1000_SUCCESS) { |
| 5688 | error = e1000_verify_write_ich8_byte(hw, |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 5689 | E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0); |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5690 | } |
| 5691 | |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 5692 | /* Clear the now not used entry in the cache */ |
| 5693 | for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) { |
| 5694 | hw->eeprom_shadow_ram[i].modified = FALSE; |
| 5695 | hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5696 | } |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 5697 | } |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5698 | } |
| 5699 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5700 | return error; |
| 5701 | } |
| 5702 | |
| 5703 | /****************************************************************************** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5704 | * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the |
| 5705 | * second function of dual function devices |
| 5706 | * |
| 5707 | * hw - Struct containing variables accessed by shared code |
| 5708 | *****************************************************************************/ |
| 5709 | int32_t |
| 5710 | e1000_read_mac_addr(struct e1000_hw * hw) |
| 5711 | { |
| 5712 | uint16_t offset; |
| 5713 | uint16_t eeprom_data, i; |
| 5714 | |
| 5715 | DEBUGFUNC("e1000_read_mac_addr"); |
| 5716 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5717 | for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5718 | offset = i >> 1; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5719 | if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5720 | DEBUGOUT("EEPROM Read Error\n"); |
| 5721 | return -E1000_ERR_EEPROM; |
| 5722 | } |
| 5723 | hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF); |
| 5724 | hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8); |
| 5725 | } |
Jesse Brandeburg | 96838a4 | 2006-01-18 13:01:39 -0800 | [diff] [blame] | 5726 | |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 5727 | switch (hw->mac_type) { |
| 5728 | default: |
| 5729 | break; |
| 5730 | case e1000_82546: |
| 5731 | case e1000_82546_rev_3: |
| 5732 | case e1000_82571: |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 5733 | case e1000_80003es2lan: |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5734 | if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5735 | hw->perm_mac_addr[5] ^= 0x01; |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 5736 | break; |
| 5737 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5738 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5739 | for (i = 0; i < NODE_ADDRESS_SIZE; i++) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5740 | hw->mac_addr[i] = hw->perm_mac_addr[i]; |
| 5741 | return E1000_SUCCESS; |
| 5742 | } |
| 5743 | |
| 5744 | /****************************************************************************** |
| 5745 | * Initializes receive address filters. |
| 5746 | * |
| 5747 | * hw - Struct containing variables accessed by shared code |
| 5748 | * |
| 5749 | * Places the MAC address in receive address register 0 and clears the rest |
| 5750 | * of the receive addresss registers. Clears the multicast table. Assumes |
| 5751 | * the receiver is in reset when the routine is called. |
| 5752 | *****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 5753 | static void |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5754 | e1000_init_rx_addrs(struct e1000_hw *hw) |
| 5755 | { |
| 5756 | uint32_t i; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5757 | uint32_t rar_num; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5758 | |
| 5759 | DEBUGFUNC("e1000_init_rx_addrs"); |
| 5760 | |
| 5761 | /* Setup the receive address. */ |
| 5762 | DEBUGOUT("Programming MAC Address into RAR[0]\n"); |
| 5763 | |
| 5764 | e1000_rar_set(hw, hw->mac_addr, 0); |
| 5765 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5766 | rar_num = E1000_RAR_ENTRIES; |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 5767 | |
| 5768 | /* Reserve a spot for the Locally Administered Address to work around |
| 5769 | * an 82571 issue in which a reset on one port will reload the MAC on |
| 5770 | * the other port. */ |
| 5771 | if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE)) |
| 5772 | rar_num -= 1; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5773 | if (hw->mac_type == e1000_ich8lan) |
| 5774 | rar_num = E1000_RAR_ENTRIES_ICH8LAN; |
| 5775 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5776 | /* Zero out the other 15 receive addresses. */ |
| 5777 | DEBUGOUT("Clearing RAR[1-15]\n"); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5778 | for (i = 1; i < rar_num; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5779 | E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0); |
Auke Kok | 4ca213a | 2006-06-27 09:07:08 -0700 | [diff] [blame] | 5780 | E1000_WRITE_FLUSH(hw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5781 | E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0); |
Auke Kok | 4ca213a | 2006-06-27 09:07:08 -0700 | [diff] [blame] | 5782 | E1000_WRITE_FLUSH(hw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5783 | } |
| 5784 | } |
| 5785 | |
| 5786 | /****************************************************************************** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5787 | * Hashes an address to determine its location in the multicast table |
| 5788 | * |
| 5789 | * hw - Struct containing variables accessed by shared code |
| 5790 | * mc_addr - the multicast address to hash |
| 5791 | *****************************************************************************/ |
| 5792 | uint32_t |
| 5793 | e1000_hash_mc_addr(struct e1000_hw *hw, |
| 5794 | uint8_t *mc_addr) |
| 5795 | { |
| 5796 | uint32_t hash_value = 0; |
| 5797 | |
| 5798 | /* The portion of the address that is used for the hash table is |
| 5799 | * determined by the mc_filter_type setting. |
| 5800 | */ |
| 5801 | switch (hw->mc_filter_type) { |
| 5802 | /* [0] [1] [2] [3] [4] [5] |
| 5803 | * 01 AA 00 12 34 56 |
| 5804 | * LSB MSB |
| 5805 | */ |
| 5806 | case 0: |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5807 | if (hw->mac_type == e1000_ich8lan) { |
| 5808 | /* [47:38] i.e. 0x158 for above example address */ |
| 5809 | hash_value = ((mc_addr[4] >> 6) | (((uint16_t) mc_addr[5]) << 2)); |
| 5810 | } else { |
| 5811 | /* [47:36] i.e. 0x563 for above example address */ |
| 5812 | hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); |
| 5813 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5814 | break; |
| 5815 | case 1: |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5816 | if (hw->mac_type == e1000_ich8lan) { |
| 5817 | /* [46:37] i.e. 0x2B1 for above example address */ |
| 5818 | hash_value = ((mc_addr[4] >> 5) | (((uint16_t) mc_addr[5]) << 3)); |
| 5819 | } else { |
| 5820 | /* [46:35] i.e. 0xAC6 for above example address */ |
| 5821 | hash_value = ((mc_addr[4] >> 3) | (((uint16_t) mc_addr[5]) << 5)); |
| 5822 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5823 | break; |
| 5824 | case 2: |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5825 | if (hw->mac_type == e1000_ich8lan) { |
| 5826 | /*[45:36] i.e. 0x163 for above example address */ |
| 5827 | hash_value = ((mc_addr[4] >> 4) | (((uint16_t) mc_addr[5]) << 4)); |
| 5828 | } else { |
| 5829 | /* [45:34] i.e. 0x5D8 for above example address */ |
| 5830 | hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); |
| 5831 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5832 | break; |
| 5833 | case 3: |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5834 | if (hw->mac_type == e1000_ich8lan) { |
| 5835 | /* [43:34] i.e. 0x18D for above example address */ |
| 5836 | hash_value = ((mc_addr[4] >> 2) | (((uint16_t) mc_addr[5]) << 6)); |
| 5837 | } else { |
| 5838 | /* [43:32] i.e. 0x634 for above example address */ |
| 5839 | hash_value = ((mc_addr[4]) | (((uint16_t) mc_addr[5]) << 8)); |
| 5840 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5841 | break; |
| 5842 | } |
| 5843 | |
| 5844 | hash_value &= 0xFFF; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5845 | if (hw->mac_type == e1000_ich8lan) |
| 5846 | hash_value &= 0x3FF; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5847 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5848 | return hash_value; |
| 5849 | } |
| 5850 | |
| 5851 | /****************************************************************************** |
| 5852 | * Sets the bit in the multicast table corresponding to the hash value. |
| 5853 | * |
| 5854 | * hw - Struct containing variables accessed by shared code |
| 5855 | * hash_value - Multicast address hash value |
| 5856 | *****************************************************************************/ |
| 5857 | void |
| 5858 | e1000_mta_set(struct e1000_hw *hw, |
| 5859 | uint32_t hash_value) |
| 5860 | { |
| 5861 | uint32_t hash_bit, hash_reg; |
| 5862 | uint32_t mta; |
| 5863 | uint32_t temp; |
| 5864 | |
| 5865 | /* The MTA is a register array of 128 32-bit registers. |
| 5866 | * It is treated like an array of 4096 bits. We want to set |
| 5867 | * bit BitArray[hash_value]. So we figure out what register |
| 5868 | * the bit is in, read it, OR in the new bit, then write |
| 5869 | * back the new value. The register is determined by the |
| 5870 | * upper 7 bits of the hash value and the bit within that |
| 5871 | * register are determined by the lower 5 bits of the value. |
| 5872 | */ |
| 5873 | hash_reg = (hash_value >> 5) & 0x7F; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5874 | if (hw->mac_type == e1000_ich8lan) |
| 5875 | hash_reg &= 0x1F; |
Auke Kok | 90fb513 | 2006-11-01 08:47:30 -0800 | [diff] [blame] | 5876 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5877 | hash_bit = hash_value & 0x1F; |
| 5878 | |
| 5879 | mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg); |
| 5880 | |
| 5881 | mta |= (1 << hash_bit); |
| 5882 | |
| 5883 | /* If we are on an 82544 and we are trying to write an odd offset |
| 5884 | * in the MTA, save off the previous entry before writing and |
| 5885 | * restore the old value after writing. |
| 5886 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 5887 | if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5888 | temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1)); |
| 5889 | E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); |
Auke Kok | 4ca213a | 2006-06-27 09:07:08 -0700 | [diff] [blame] | 5890 | E1000_WRITE_FLUSH(hw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5891 | E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp); |
Auke Kok | 4ca213a | 2006-06-27 09:07:08 -0700 | [diff] [blame] | 5892 | E1000_WRITE_FLUSH(hw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5893 | } else { |
| 5894 | E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta); |
Auke Kok | 4ca213a | 2006-06-27 09:07:08 -0700 | [diff] [blame] | 5895 | E1000_WRITE_FLUSH(hw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5896 | } |
| 5897 | } |
| 5898 | |
| 5899 | /****************************************************************************** |
| 5900 | * Puts an ethernet address into a receive address register. |
| 5901 | * |
| 5902 | * hw - Struct containing variables accessed by shared code |
| 5903 | * addr - Address to put into receive address register |
| 5904 | * index - Receive address register to write |
| 5905 | *****************************************************************************/ |
| 5906 | void |
| 5907 | e1000_rar_set(struct e1000_hw *hw, |
| 5908 | uint8_t *addr, |
| 5909 | uint32_t index) |
| 5910 | { |
| 5911 | uint32_t rar_low, rar_high; |
| 5912 | |
| 5913 | /* HW expects these in little endian so we reverse the byte order |
| 5914 | * from network order (big endian) to little endian |
| 5915 | */ |
| 5916 | rar_low = ((uint32_t) addr[0] | |
| 5917 | ((uint32_t) addr[1] << 8) | |
| 5918 | ((uint32_t) addr[2] << 16) | ((uint32_t) addr[3] << 24)); |
Jeff Kirsher | 8df06e5 | 2006-03-02 18:18:32 -0800 | [diff] [blame] | 5919 | rar_high = ((uint32_t) addr[4] | ((uint32_t) addr[5] << 8)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5920 | |
Jeff Kirsher | 8df06e5 | 2006-03-02 18:18:32 -0800 | [diff] [blame] | 5921 | /* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx |
| 5922 | * unit hang. |
| 5923 | * |
| 5924 | * Description: |
| 5925 | * If there are any Rx frames queued up or otherwise present in the HW |
| 5926 | * before RSS is enabled, and then we enable RSS, the HW Rx unit will |
| 5927 | * hang. To work around this issue, we have to disable receives and |
| 5928 | * flush out all Rx frames before we enable RSS. To do so, we modify we |
| 5929 | * redirect all Rx traffic to manageability and then reset the HW. |
| 5930 | * This flushes away Rx frames, and (since the redirections to |
| 5931 | * manageability persists across resets) keeps new ones from coming in |
| 5932 | * while we work. Then, we clear the Address Valid AV bit for all MAC |
| 5933 | * addresses and undo the re-direction to manageability. |
| 5934 | * Now, frames are coming in again, but the MAC won't accept them, so |
| 5935 | * far so good. We now proceed to initialize RSS (if necessary) and |
| 5936 | * configure the Rx unit. Last, we re-enable the AV bits and continue |
| 5937 | * on our merry way. |
| 5938 | */ |
| 5939 | switch (hw->mac_type) { |
| 5940 | case e1000_82571: |
| 5941 | case e1000_82572: |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 5942 | case e1000_80003es2lan: |
Jeff Kirsher | 8df06e5 | 2006-03-02 18:18:32 -0800 | [diff] [blame] | 5943 | if (hw->leave_av_bit_off == TRUE) |
| 5944 | break; |
| 5945 | default: |
| 5946 | /* Indicate to hardware the Address is Valid. */ |
| 5947 | rar_high |= E1000_RAH_AV; |
| 5948 | break; |
| 5949 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5950 | |
| 5951 | E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low); |
Auke Kok | 4ca213a | 2006-06-27 09:07:08 -0700 | [diff] [blame] | 5952 | E1000_WRITE_FLUSH(hw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5953 | E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high); |
Auke Kok | 4ca213a | 2006-06-27 09:07:08 -0700 | [diff] [blame] | 5954 | E1000_WRITE_FLUSH(hw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5955 | } |
| 5956 | |
| 5957 | /****************************************************************************** |
| 5958 | * Writes a value to the specified offset in the VLAN filter table. |
| 5959 | * |
| 5960 | * hw - Struct containing variables accessed by shared code |
| 5961 | * offset - Offset in VLAN filer table to write |
| 5962 | * value - Value to write into VLAN filter table |
| 5963 | *****************************************************************************/ |
| 5964 | void |
| 5965 | e1000_write_vfta(struct e1000_hw *hw, |
| 5966 | uint32_t offset, |
| 5967 | uint32_t value) |
| 5968 | { |
| 5969 | uint32_t temp; |
| 5970 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5971 | if (hw->mac_type == e1000_ich8lan) |
| 5972 | return; |
| 5973 | |
| 5974 | if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5975 | temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1)); |
| 5976 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); |
Auke Kok | 4ca213a | 2006-06-27 09:07:08 -0700 | [diff] [blame] | 5977 | E1000_WRITE_FLUSH(hw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5978 | E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp); |
Auke Kok | 4ca213a | 2006-06-27 09:07:08 -0700 | [diff] [blame] | 5979 | E1000_WRITE_FLUSH(hw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5980 | } else { |
| 5981 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value); |
Auke Kok | 4ca213a | 2006-06-27 09:07:08 -0700 | [diff] [blame] | 5982 | E1000_WRITE_FLUSH(hw); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5983 | } |
| 5984 | } |
| 5985 | |
| 5986 | /****************************************************************************** |
| 5987 | * Clears the VLAN filer table |
| 5988 | * |
| 5989 | * hw - Struct containing variables accessed by shared code |
| 5990 | *****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 5991 | static void |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5992 | e1000_clear_vfta(struct e1000_hw *hw) |
| 5993 | { |
| 5994 | uint32_t offset; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 5995 | uint32_t vfta_value = 0; |
| 5996 | uint32_t vfta_offset = 0; |
| 5997 | uint32_t vfta_bit_in_reg = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5998 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 5999 | if (hw->mac_type == e1000_ich8lan) |
| 6000 | return; |
| 6001 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6002 | if (hw->mac_type == e1000_82573) { |
| 6003 | if (hw->mng_cookie.vlan_id != 0) { |
| 6004 | /* The VFTA is a 4096b bit-field, each identifying a single VLAN |
| 6005 | * ID. The following operations determine which 32b entry |
| 6006 | * (i.e. offset) into the array we want to set the VLAN ID |
| 6007 | * (i.e. bit) of the manageability unit. */ |
| 6008 | vfta_offset = (hw->mng_cookie.vlan_id >> |
| 6009 | E1000_VFTA_ENTRY_SHIFT) & |
| 6010 | E1000_VFTA_ENTRY_MASK; |
| 6011 | vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id & |
| 6012 | E1000_VFTA_ENTRY_BIT_SHIFT_MASK); |
| 6013 | } |
| 6014 | } |
| 6015 | for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { |
| 6016 | /* If the offset we want to clear is the same offset of the |
| 6017 | * manageability VLAN ID, then clear all bits except that of the |
| 6018 | * manageability unit */ |
| 6019 | vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0; |
| 6020 | E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value); |
Auke Kok | 4ca213a | 2006-06-27 09:07:08 -0700 | [diff] [blame] | 6021 | E1000_WRITE_FLUSH(hw); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6022 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6023 | } |
| 6024 | |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 6025 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6026 | e1000_id_led_init(struct e1000_hw * hw) |
| 6027 | { |
| 6028 | uint32_t ledctl; |
| 6029 | const uint32_t ledctl_mask = 0x000000FF; |
| 6030 | const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON; |
| 6031 | const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF; |
| 6032 | uint16_t eeprom_data, i, temp; |
| 6033 | const uint16_t led_mask = 0x0F; |
| 6034 | |
| 6035 | DEBUGFUNC("e1000_id_led_init"); |
| 6036 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6037 | if (hw->mac_type < e1000_82540) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6038 | /* Nothing to do */ |
| 6039 | return E1000_SUCCESS; |
| 6040 | } |
| 6041 | |
| 6042 | ledctl = E1000_READ_REG(hw, LEDCTL); |
| 6043 | hw->ledctl_default = ledctl; |
| 6044 | hw->ledctl_mode1 = hw->ledctl_default; |
| 6045 | hw->ledctl_mode2 = hw->ledctl_default; |
| 6046 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6047 | if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6048 | DEBUGOUT("EEPROM Read Error\n"); |
| 6049 | return -E1000_ERR_EEPROM; |
| 6050 | } |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6051 | |
| 6052 | if ((hw->mac_type == e1000_82573) && |
| 6053 | (eeprom_data == ID_LED_RESERVED_82573)) |
| 6054 | eeprom_data = ID_LED_DEFAULT_82573; |
| 6055 | else if ((eeprom_data == ID_LED_RESERVED_0000) || |
| 6056 | (eeprom_data == ID_LED_RESERVED_FFFF)) { |
| 6057 | if (hw->mac_type == e1000_ich8lan) |
| 6058 | eeprom_data = ID_LED_DEFAULT_ICH8LAN; |
| 6059 | else |
| 6060 | eeprom_data = ID_LED_DEFAULT; |
| 6061 | } |
Auke Kok | 90fb513 | 2006-11-01 08:47:30 -0800 | [diff] [blame] | 6062 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6063 | for (i = 0; i < 4; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6064 | temp = (eeprom_data >> (i << 2)) & led_mask; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6065 | switch (temp) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6066 | case ID_LED_ON1_DEF2: |
| 6067 | case ID_LED_ON1_ON2: |
| 6068 | case ID_LED_ON1_OFF2: |
| 6069 | hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
| 6070 | hw->ledctl_mode1 |= ledctl_on << (i << 3); |
| 6071 | break; |
| 6072 | case ID_LED_OFF1_DEF2: |
| 6073 | case ID_LED_OFF1_ON2: |
| 6074 | case ID_LED_OFF1_OFF2: |
| 6075 | hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); |
| 6076 | hw->ledctl_mode1 |= ledctl_off << (i << 3); |
| 6077 | break; |
| 6078 | default: |
| 6079 | /* Do nothing */ |
| 6080 | break; |
| 6081 | } |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6082 | switch (temp) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6083 | case ID_LED_DEF1_ON2: |
| 6084 | case ID_LED_ON1_ON2: |
| 6085 | case ID_LED_OFF1_ON2: |
| 6086 | hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
| 6087 | hw->ledctl_mode2 |= ledctl_on << (i << 3); |
| 6088 | break; |
| 6089 | case ID_LED_DEF1_OFF2: |
| 6090 | case ID_LED_ON1_OFF2: |
| 6091 | case ID_LED_OFF1_OFF2: |
| 6092 | hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); |
| 6093 | hw->ledctl_mode2 |= ledctl_off << (i << 3); |
| 6094 | break; |
| 6095 | default: |
| 6096 | /* Do nothing */ |
| 6097 | break; |
| 6098 | } |
| 6099 | } |
| 6100 | return E1000_SUCCESS; |
| 6101 | } |
| 6102 | |
| 6103 | /****************************************************************************** |
| 6104 | * Prepares SW controlable LED for use and saves the current state of the LED. |
| 6105 | * |
| 6106 | * hw - Struct containing variables accessed by shared code |
| 6107 | *****************************************************************************/ |
| 6108 | int32_t |
| 6109 | e1000_setup_led(struct e1000_hw *hw) |
| 6110 | { |
| 6111 | uint32_t ledctl; |
| 6112 | int32_t ret_val = E1000_SUCCESS; |
| 6113 | |
| 6114 | DEBUGFUNC("e1000_setup_led"); |
| 6115 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6116 | switch (hw->mac_type) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6117 | case e1000_82542_rev2_0: |
| 6118 | case e1000_82542_rev2_1: |
| 6119 | case e1000_82543: |
| 6120 | case e1000_82544: |
| 6121 | /* No setup necessary */ |
| 6122 | break; |
| 6123 | case e1000_82541: |
| 6124 | case e1000_82547: |
| 6125 | case e1000_82541_rev_2: |
| 6126 | case e1000_82547_rev_2: |
| 6127 | /* Turn off PHY Smart Power Down (if enabled) */ |
| 6128 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, |
| 6129 | &hw->phy_spd_default); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6130 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6131 | return ret_val; |
| 6132 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, |
| 6133 | (uint16_t)(hw->phy_spd_default & |
| 6134 | ~IGP01E1000_GMII_SPD)); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6135 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6136 | return ret_val; |
| 6137 | /* Fall Through */ |
| 6138 | default: |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6139 | if (hw->media_type == e1000_media_type_fiber) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6140 | ledctl = E1000_READ_REG(hw, LEDCTL); |
| 6141 | /* Save current LEDCTL settings */ |
| 6142 | hw->ledctl_default = ledctl; |
| 6143 | /* Turn off LED0 */ |
| 6144 | ledctl &= ~(E1000_LEDCTL_LED0_IVRT | |
| 6145 | E1000_LEDCTL_LED0_BLINK | |
| 6146 | E1000_LEDCTL_LED0_MODE_MASK); |
| 6147 | ledctl |= (E1000_LEDCTL_MODE_LED_OFF << |
| 6148 | E1000_LEDCTL_LED0_MODE_SHIFT); |
| 6149 | E1000_WRITE_REG(hw, LEDCTL, ledctl); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6150 | } else if (hw->media_type == e1000_media_type_copper) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6151 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); |
| 6152 | break; |
| 6153 | } |
| 6154 | |
| 6155 | return E1000_SUCCESS; |
| 6156 | } |
| 6157 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6158 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6159 | /****************************************************************************** |
Auke Kok | f1b3a85 | 2006-06-27 09:07:56 -0700 | [diff] [blame] | 6160 | * Used on 82571 and later Si that has LED blink bits. |
| 6161 | * Callers must use their own timer and should have already called |
| 6162 | * e1000_id_led_init() |
| 6163 | * Call e1000_cleanup led() to stop blinking |
| 6164 | * |
| 6165 | * hw - Struct containing variables accessed by shared code |
| 6166 | *****************************************************************************/ |
| 6167 | int32_t |
| 6168 | e1000_blink_led_start(struct e1000_hw *hw) |
| 6169 | { |
| 6170 | int16_t i; |
| 6171 | uint32_t ledctl_blink = 0; |
| 6172 | |
| 6173 | DEBUGFUNC("e1000_id_led_blink_on"); |
| 6174 | |
| 6175 | if (hw->mac_type < e1000_82571) { |
| 6176 | /* Nothing to do */ |
| 6177 | return E1000_SUCCESS; |
| 6178 | } |
| 6179 | if (hw->media_type == e1000_media_type_fiber) { |
| 6180 | /* always blink LED0 for PCI-E fiber */ |
| 6181 | ledctl_blink = E1000_LEDCTL_LED0_BLINK | |
| 6182 | (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); |
| 6183 | } else { |
| 6184 | /* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */ |
| 6185 | ledctl_blink = hw->ledctl_mode2; |
| 6186 | for (i=0; i < 4; i++) |
| 6187 | if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) == |
| 6188 | E1000_LEDCTL_MODE_LED_ON) |
| 6189 | ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << (i * 8)); |
| 6190 | } |
| 6191 | |
| 6192 | E1000_WRITE_REG(hw, LEDCTL, ledctl_blink); |
| 6193 | |
| 6194 | return E1000_SUCCESS; |
| 6195 | } |
| 6196 | |
| 6197 | /****************************************************************************** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6198 | * Restores the saved state of the SW controlable LED. |
| 6199 | * |
| 6200 | * hw - Struct containing variables accessed by shared code |
| 6201 | *****************************************************************************/ |
| 6202 | int32_t |
| 6203 | e1000_cleanup_led(struct e1000_hw *hw) |
| 6204 | { |
| 6205 | int32_t ret_val = E1000_SUCCESS; |
| 6206 | |
| 6207 | DEBUGFUNC("e1000_cleanup_led"); |
| 6208 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6209 | switch (hw->mac_type) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6210 | case e1000_82542_rev2_0: |
| 6211 | case e1000_82542_rev2_1: |
| 6212 | case e1000_82543: |
| 6213 | case e1000_82544: |
| 6214 | /* No cleanup necessary */ |
| 6215 | break; |
| 6216 | case e1000_82541: |
| 6217 | case e1000_82547: |
| 6218 | case e1000_82541_rev_2: |
| 6219 | case e1000_82547_rev_2: |
| 6220 | /* Turn on PHY Smart Power Down (if previously enabled) */ |
| 6221 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, |
| 6222 | hw->phy_spd_default); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6223 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6224 | return ret_val; |
| 6225 | /* Fall Through */ |
| 6226 | default: |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6227 | if (hw->phy_type == e1000_phy_ife) { |
| 6228 | e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); |
| 6229 | break; |
| 6230 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6231 | /* Restore LEDCTL settings */ |
| 6232 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default); |
| 6233 | break; |
| 6234 | } |
| 6235 | |
| 6236 | return E1000_SUCCESS; |
| 6237 | } |
| 6238 | |
| 6239 | /****************************************************************************** |
| 6240 | * Turns on the software controllable LED |
| 6241 | * |
| 6242 | * hw - Struct containing variables accessed by shared code |
| 6243 | *****************************************************************************/ |
| 6244 | int32_t |
| 6245 | e1000_led_on(struct e1000_hw *hw) |
| 6246 | { |
| 6247 | uint32_t ctrl = E1000_READ_REG(hw, CTRL); |
| 6248 | |
| 6249 | DEBUGFUNC("e1000_led_on"); |
| 6250 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6251 | switch (hw->mac_type) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6252 | case e1000_82542_rev2_0: |
| 6253 | case e1000_82542_rev2_1: |
| 6254 | case e1000_82543: |
| 6255 | /* Set SW Defineable Pin 0 to turn on the LED */ |
| 6256 | ctrl |= E1000_CTRL_SWDPIN0; |
| 6257 | ctrl |= E1000_CTRL_SWDPIO0; |
| 6258 | break; |
| 6259 | case e1000_82544: |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6260 | if (hw->media_type == e1000_media_type_fiber) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6261 | /* Set SW Defineable Pin 0 to turn on the LED */ |
| 6262 | ctrl |= E1000_CTRL_SWDPIN0; |
| 6263 | ctrl |= E1000_CTRL_SWDPIO0; |
| 6264 | } else { |
| 6265 | /* Clear SW Defineable Pin 0 to turn on the LED */ |
| 6266 | ctrl &= ~E1000_CTRL_SWDPIN0; |
| 6267 | ctrl |= E1000_CTRL_SWDPIO0; |
| 6268 | } |
| 6269 | break; |
| 6270 | default: |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6271 | if (hw->media_type == e1000_media_type_fiber) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6272 | /* Clear SW Defineable Pin 0 to turn on the LED */ |
| 6273 | ctrl &= ~E1000_CTRL_SWDPIN0; |
| 6274 | ctrl |= E1000_CTRL_SWDPIO0; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6275 | } else if (hw->phy_type == e1000_phy_ife) { |
| 6276 | e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, |
| 6277 | (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); |
| 6278 | } else if (hw->media_type == e1000_media_type_copper) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6279 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2); |
| 6280 | return E1000_SUCCESS; |
| 6281 | } |
| 6282 | break; |
| 6283 | } |
| 6284 | |
| 6285 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 6286 | |
| 6287 | return E1000_SUCCESS; |
| 6288 | } |
| 6289 | |
| 6290 | /****************************************************************************** |
| 6291 | * Turns off the software controllable LED |
| 6292 | * |
| 6293 | * hw - Struct containing variables accessed by shared code |
| 6294 | *****************************************************************************/ |
| 6295 | int32_t |
| 6296 | e1000_led_off(struct e1000_hw *hw) |
| 6297 | { |
| 6298 | uint32_t ctrl = E1000_READ_REG(hw, CTRL); |
| 6299 | |
| 6300 | DEBUGFUNC("e1000_led_off"); |
| 6301 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6302 | switch (hw->mac_type) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6303 | case e1000_82542_rev2_0: |
| 6304 | case e1000_82542_rev2_1: |
| 6305 | case e1000_82543: |
| 6306 | /* Clear SW Defineable Pin 0 to turn off the LED */ |
| 6307 | ctrl &= ~E1000_CTRL_SWDPIN0; |
| 6308 | ctrl |= E1000_CTRL_SWDPIO0; |
| 6309 | break; |
| 6310 | case e1000_82544: |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6311 | if (hw->media_type == e1000_media_type_fiber) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6312 | /* Clear SW Defineable Pin 0 to turn off the LED */ |
| 6313 | ctrl &= ~E1000_CTRL_SWDPIN0; |
| 6314 | ctrl |= E1000_CTRL_SWDPIO0; |
| 6315 | } else { |
| 6316 | /* Set SW Defineable Pin 0 to turn off the LED */ |
| 6317 | ctrl |= E1000_CTRL_SWDPIN0; |
| 6318 | ctrl |= E1000_CTRL_SWDPIO0; |
| 6319 | } |
| 6320 | break; |
| 6321 | default: |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6322 | if (hw->media_type == e1000_media_type_fiber) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6323 | /* Set SW Defineable Pin 0 to turn off the LED */ |
| 6324 | ctrl |= E1000_CTRL_SWDPIN0; |
| 6325 | ctrl |= E1000_CTRL_SWDPIO0; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6326 | } else if (hw->phy_type == e1000_phy_ife) { |
| 6327 | e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, |
| 6328 | (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF)); |
| 6329 | } else if (hw->media_type == e1000_media_type_copper) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6330 | E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1); |
| 6331 | return E1000_SUCCESS; |
| 6332 | } |
| 6333 | break; |
| 6334 | } |
| 6335 | |
| 6336 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 6337 | |
| 6338 | return E1000_SUCCESS; |
| 6339 | } |
| 6340 | |
| 6341 | /****************************************************************************** |
| 6342 | * Clears all hardware statistics counters. |
| 6343 | * |
| 6344 | * hw - Struct containing variables accessed by shared code |
| 6345 | *****************************************************************************/ |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 6346 | static void |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6347 | e1000_clear_hw_cntrs(struct e1000_hw *hw) |
| 6348 | { |
| 6349 | volatile uint32_t temp; |
| 6350 | |
| 6351 | temp = E1000_READ_REG(hw, CRCERRS); |
| 6352 | temp = E1000_READ_REG(hw, SYMERRS); |
| 6353 | temp = E1000_READ_REG(hw, MPC); |
| 6354 | temp = E1000_READ_REG(hw, SCC); |
| 6355 | temp = E1000_READ_REG(hw, ECOL); |
| 6356 | temp = E1000_READ_REG(hw, MCC); |
| 6357 | temp = E1000_READ_REG(hw, LATECOL); |
| 6358 | temp = E1000_READ_REG(hw, COLC); |
| 6359 | temp = E1000_READ_REG(hw, DC); |
| 6360 | temp = E1000_READ_REG(hw, SEC); |
| 6361 | temp = E1000_READ_REG(hw, RLEC); |
| 6362 | temp = E1000_READ_REG(hw, XONRXC); |
| 6363 | temp = E1000_READ_REG(hw, XONTXC); |
| 6364 | temp = E1000_READ_REG(hw, XOFFRXC); |
| 6365 | temp = E1000_READ_REG(hw, XOFFTXC); |
| 6366 | temp = E1000_READ_REG(hw, FCRUC); |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6367 | |
| 6368 | if (hw->mac_type != e1000_ich8lan) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6369 | temp = E1000_READ_REG(hw, PRC64); |
| 6370 | temp = E1000_READ_REG(hw, PRC127); |
| 6371 | temp = E1000_READ_REG(hw, PRC255); |
| 6372 | temp = E1000_READ_REG(hw, PRC511); |
| 6373 | temp = E1000_READ_REG(hw, PRC1023); |
| 6374 | temp = E1000_READ_REG(hw, PRC1522); |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6375 | } |
| 6376 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6377 | temp = E1000_READ_REG(hw, GPRC); |
| 6378 | temp = E1000_READ_REG(hw, BPRC); |
| 6379 | temp = E1000_READ_REG(hw, MPRC); |
| 6380 | temp = E1000_READ_REG(hw, GPTC); |
| 6381 | temp = E1000_READ_REG(hw, GORCL); |
| 6382 | temp = E1000_READ_REG(hw, GORCH); |
| 6383 | temp = E1000_READ_REG(hw, GOTCL); |
| 6384 | temp = E1000_READ_REG(hw, GOTCH); |
| 6385 | temp = E1000_READ_REG(hw, RNBC); |
| 6386 | temp = E1000_READ_REG(hw, RUC); |
| 6387 | temp = E1000_READ_REG(hw, RFC); |
| 6388 | temp = E1000_READ_REG(hw, ROC); |
| 6389 | temp = E1000_READ_REG(hw, RJC); |
| 6390 | temp = E1000_READ_REG(hw, TORL); |
| 6391 | temp = E1000_READ_REG(hw, TORH); |
| 6392 | temp = E1000_READ_REG(hw, TOTL); |
| 6393 | temp = E1000_READ_REG(hw, TOTH); |
| 6394 | temp = E1000_READ_REG(hw, TPR); |
| 6395 | temp = E1000_READ_REG(hw, TPT); |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6396 | |
| 6397 | if (hw->mac_type != e1000_ich8lan) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6398 | temp = E1000_READ_REG(hw, PTC64); |
| 6399 | temp = E1000_READ_REG(hw, PTC127); |
| 6400 | temp = E1000_READ_REG(hw, PTC255); |
| 6401 | temp = E1000_READ_REG(hw, PTC511); |
| 6402 | temp = E1000_READ_REG(hw, PTC1023); |
| 6403 | temp = E1000_READ_REG(hw, PTC1522); |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6404 | } |
| 6405 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6406 | temp = E1000_READ_REG(hw, MPTC); |
| 6407 | temp = E1000_READ_REG(hw, BPTC); |
| 6408 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6409 | if (hw->mac_type < e1000_82543) return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6410 | |
| 6411 | temp = E1000_READ_REG(hw, ALGNERRC); |
| 6412 | temp = E1000_READ_REG(hw, RXERRC); |
| 6413 | temp = E1000_READ_REG(hw, TNCRS); |
| 6414 | temp = E1000_READ_REG(hw, CEXTERR); |
| 6415 | temp = E1000_READ_REG(hw, TSCTC); |
| 6416 | temp = E1000_READ_REG(hw, TSCTFC); |
| 6417 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6418 | if (hw->mac_type <= e1000_82544) return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6419 | |
| 6420 | temp = E1000_READ_REG(hw, MGTPRC); |
| 6421 | temp = E1000_READ_REG(hw, MGTPDC); |
| 6422 | temp = E1000_READ_REG(hw, MGTPTC); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6423 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6424 | if (hw->mac_type <= e1000_82547_rev_2) return; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6425 | |
| 6426 | temp = E1000_READ_REG(hw, IAC); |
| 6427 | temp = E1000_READ_REG(hw, ICRXOC); |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6428 | |
| 6429 | if (hw->mac_type == e1000_ich8lan) return; |
| 6430 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6431 | temp = E1000_READ_REG(hw, ICRXPTC); |
| 6432 | temp = E1000_READ_REG(hw, ICRXATC); |
| 6433 | temp = E1000_READ_REG(hw, ICTXPTC); |
| 6434 | temp = E1000_READ_REG(hw, ICTXATC); |
| 6435 | temp = E1000_READ_REG(hw, ICTXQEC); |
| 6436 | temp = E1000_READ_REG(hw, ICTXQMTC); |
| 6437 | temp = E1000_READ_REG(hw, ICRXDMTC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6438 | } |
| 6439 | |
| 6440 | /****************************************************************************** |
| 6441 | * Resets Adaptive IFS to its default state. |
| 6442 | * |
| 6443 | * hw - Struct containing variables accessed by shared code |
| 6444 | * |
| 6445 | * Call this after e1000_init_hw. You may override the IFS defaults by setting |
| 6446 | * hw->ifs_params_forced to TRUE. However, you must initialize hw-> |
| 6447 | * current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio |
| 6448 | * before calling this function. |
| 6449 | *****************************************************************************/ |
| 6450 | void |
| 6451 | e1000_reset_adaptive(struct e1000_hw *hw) |
| 6452 | { |
| 6453 | DEBUGFUNC("e1000_reset_adaptive"); |
| 6454 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6455 | if (hw->adaptive_ifs) { |
| 6456 | if (!hw->ifs_params_forced) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6457 | hw->current_ifs_val = 0; |
| 6458 | hw->ifs_min_val = IFS_MIN; |
| 6459 | hw->ifs_max_val = IFS_MAX; |
| 6460 | hw->ifs_step_size = IFS_STEP; |
| 6461 | hw->ifs_ratio = IFS_RATIO; |
| 6462 | } |
| 6463 | hw->in_ifs_mode = FALSE; |
| 6464 | E1000_WRITE_REG(hw, AIT, 0); |
| 6465 | } else { |
| 6466 | DEBUGOUT("Not in Adaptive IFS mode!\n"); |
| 6467 | } |
| 6468 | } |
| 6469 | |
| 6470 | /****************************************************************************** |
| 6471 | * Called during the callback/watchdog routine to update IFS value based on |
| 6472 | * the ratio of transmits to collisions. |
| 6473 | * |
| 6474 | * hw - Struct containing variables accessed by shared code |
| 6475 | * tx_packets - Number of transmits since last callback |
| 6476 | * total_collisions - Number of collisions since last callback |
| 6477 | *****************************************************************************/ |
| 6478 | void |
| 6479 | e1000_update_adaptive(struct e1000_hw *hw) |
| 6480 | { |
| 6481 | DEBUGFUNC("e1000_update_adaptive"); |
| 6482 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6483 | if (hw->adaptive_ifs) { |
| 6484 | if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) { |
| 6485 | if (hw->tx_packet_delta > MIN_NUM_XMITS) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6486 | hw->in_ifs_mode = TRUE; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6487 | if (hw->current_ifs_val < hw->ifs_max_val) { |
| 6488 | if (hw->current_ifs_val == 0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6489 | hw->current_ifs_val = hw->ifs_min_val; |
| 6490 | else |
| 6491 | hw->current_ifs_val += hw->ifs_step_size; |
| 6492 | E1000_WRITE_REG(hw, AIT, hw->current_ifs_val); |
| 6493 | } |
| 6494 | } |
| 6495 | } else { |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6496 | if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6497 | hw->current_ifs_val = 0; |
| 6498 | hw->in_ifs_mode = FALSE; |
| 6499 | E1000_WRITE_REG(hw, AIT, 0); |
| 6500 | } |
| 6501 | } |
| 6502 | } else { |
| 6503 | DEBUGOUT("Not in Adaptive IFS mode!\n"); |
| 6504 | } |
| 6505 | } |
| 6506 | |
| 6507 | /****************************************************************************** |
| 6508 | * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT |
| 6509 | * |
| 6510 | * hw - Struct containing variables accessed by shared code |
| 6511 | * frame_len - The length of the frame in question |
| 6512 | * mac_addr - The Ethernet destination address of the frame in question |
| 6513 | *****************************************************************************/ |
| 6514 | void |
| 6515 | e1000_tbi_adjust_stats(struct e1000_hw *hw, |
| 6516 | struct e1000_hw_stats *stats, |
| 6517 | uint32_t frame_len, |
| 6518 | uint8_t *mac_addr) |
| 6519 | { |
| 6520 | uint64_t carry_bit; |
| 6521 | |
| 6522 | /* First adjust the frame length. */ |
| 6523 | frame_len--; |
| 6524 | /* We need to adjust the statistics counters, since the hardware |
| 6525 | * counters overcount this packet as a CRC error and undercount |
| 6526 | * the packet as a good packet |
| 6527 | */ |
| 6528 | /* This packet should not be counted as a CRC error. */ |
| 6529 | stats->crcerrs--; |
| 6530 | /* This packet does count as a Good Packet Received. */ |
| 6531 | stats->gprc++; |
| 6532 | |
| 6533 | /* Adjust the Good Octets received counters */ |
| 6534 | carry_bit = 0x80000000 & stats->gorcl; |
| 6535 | stats->gorcl += frame_len; |
| 6536 | /* If the high bit of Gorcl (the low 32 bits of the Good Octets |
| 6537 | * Received Count) was one before the addition, |
| 6538 | * AND it is zero after, then we lost the carry out, |
| 6539 | * need to add one to Gorch (Good Octets Received Count High). |
| 6540 | * This could be simplified if all environments supported |
| 6541 | * 64-bit integers. |
| 6542 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6543 | if (carry_bit && ((stats->gorcl & 0x80000000) == 0)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6544 | stats->gorch++; |
| 6545 | /* Is this a broadcast or multicast? Check broadcast first, |
| 6546 | * since the test for a multicast frame will test positive on |
| 6547 | * a broadcast frame. |
| 6548 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6549 | if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6550 | /* Broadcast packet */ |
| 6551 | stats->bprc++; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6552 | else if (*mac_addr & 0x01) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6553 | /* Multicast packet */ |
| 6554 | stats->mprc++; |
| 6555 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6556 | if (frame_len == hw->max_frame_size) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6557 | /* In this case, the hardware has overcounted the number of |
| 6558 | * oversize frames. |
| 6559 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6560 | if (stats->roc > 0) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6561 | stats->roc--; |
| 6562 | } |
| 6563 | |
| 6564 | /* Adjust the bin counters when the extra byte put the frame in the |
| 6565 | * wrong bin. Remember that the frame_len was adjusted above. |
| 6566 | */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6567 | if (frame_len == 64) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6568 | stats->prc64++; |
| 6569 | stats->prc127--; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6570 | } else if (frame_len == 127) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6571 | stats->prc127++; |
| 6572 | stats->prc255--; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6573 | } else if (frame_len == 255) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6574 | stats->prc255++; |
| 6575 | stats->prc511--; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6576 | } else if (frame_len == 511) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6577 | stats->prc511++; |
| 6578 | stats->prc1023--; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6579 | } else if (frame_len == 1023) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6580 | stats->prc1023++; |
| 6581 | stats->prc1522--; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6582 | } else if (frame_len == 1522) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6583 | stats->prc1522++; |
| 6584 | } |
| 6585 | } |
| 6586 | |
| 6587 | /****************************************************************************** |
| 6588 | * Gets the current PCI bus type, speed, and width of the hardware |
| 6589 | * |
| 6590 | * hw - Struct containing variables accessed by shared code |
| 6591 | *****************************************************************************/ |
| 6592 | void |
| 6593 | e1000_get_bus_info(struct e1000_hw *hw) |
| 6594 | { |
Jeff Kirsher | caeccb6 | 2006-09-27 12:53:57 -0700 | [diff] [blame] | 6595 | int32_t ret_val; |
| 6596 | uint16_t pci_ex_link_status; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6597 | uint32_t status; |
| 6598 | |
| 6599 | switch (hw->mac_type) { |
| 6600 | case e1000_82542_rev2_0: |
| 6601 | case e1000_82542_rev2_1: |
Jeff Kirsher | c3813ae | 2006-12-15 10:37:32 +0100 | [diff] [blame] | 6602 | hw->bus_type = e1000_bus_type_pci; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6603 | hw->bus_speed = e1000_bus_speed_unknown; |
| 6604 | hw->bus_width = e1000_bus_width_unknown; |
| 6605 | break; |
Jeff Kirsher | caeccb6 | 2006-09-27 12:53:57 -0700 | [diff] [blame] | 6606 | case e1000_82571: |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 6607 | case e1000_82572: |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6608 | case e1000_82573: |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 6609 | case e1000_80003es2lan: |
Jeff Kirsher | fd80324 | 2005-12-13 00:06:22 -0500 | [diff] [blame] | 6610 | hw->bus_type = e1000_bus_type_pci_express; |
| 6611 | hw->bus_speed = e1000_bus_speed_2500; |
Jeff Kirsher | caeccb6 | 2006-09-27 12:53:57 -0700 | [diff] [blame] | 6612 | ret_val = e1000_read_pcie_cap_reg(hw, |
| 6613 | PCI_EX_LINK_STATUS, |
| 6614 | &pci_ex_link_status); |
| 6615 | if (ret_val) |
| 6616 | hw->bus_width = e1000_bus_width_unknown; |
| 6617 | else |
| 6618 | hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >> |
| 6619 | PCI_EX_LINK_WIDTH_SHIFT; |
| 6620 | break; |
| 6621 | case e1000_ich8lan: |
| 6622 | hw->bus_type = e1000_bus_type_pci_express; |
| 6623 | hw->bus_speed = e1000_bus_speed_2500; |
| 6624 | hw->bus_width = e1000_bus_width_pciex_1; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6625 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6626 | default: |
| 6627 | status = E1000_READ_REG(hw, STATUS); |
| 6628 | hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? |
| 6629 | e1000_bus_type_pcix : e1000_bus_type_pci; |
| 6630 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6631 | if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6632 | hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ? |
| 6633 | e1000_bus_speed_66 : e1000_bus_speed_120; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6634 | } else if (hw->bus_type == e1000_bus_type_pci) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6635 | hw->bus_speed = (status & E1000_STATUS_PCI66) ? |
| 6636 | e1000_bus_speed_66 : e1000_bus_speed_33; |
| 6637 | } else { |
| 6638 | switch (status & E1000_STATUS_PCIX_SPEED) { |
| 6639 | case E1000_STATUS_PCIX_SPEED_66: |
| 6640 | hw->bus_speed = e1000_bus_speed_66; |
| 6641 | break; |
| 6642 | case E1000_STATUS_PCIX_SPEED_100: |
| 6643 | hw->bus_speed = e1000_bus_speed_100; |
| 6644 | break; |
| 6645 | case E1000_STATUS_PCIX_SPEED_133: |
| 6646 | hw->bus_speed = e1000_bus_speed_133; |
| 6647 | break; |
| 6648 | default: |
| 6649 | hw->bus_speed = e1000_bus_speed_reserved; |
| 6650 | break; |
| 6651 | } |
| 6652 | } |
| 6653 | hw->bus_width = (status & E1000_STATUS_BUS64) ? |
| 6654 | e1000_bus_width_64 : e1000_bus_width_32; |
| 6655 | break; |
| 6656 | } |
| 6657 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6658 | |
| 6659 | /****************************************************************************** |
| 6660 | * Writes a value to one of the devices registers using port I/O (as opposed to |
| 6661 | * memory mapped I/O). Only 82544 and newer devices support port I/O. |
| 6662 | * |
| 6663 | * hw - Struct containing variables accessed by shared code |
| 6664 | * offset - offset to write to |
| 6665 | * value - value to write |
| 6666 | *****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 6667 | static void |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6668 | e1000_write_reg_io(struct e1000_hw *hw, |
| 6669 | uint32_t offset, |
| 6670 | uint32_t value) |
| 6671 | { |
| 6672 | unsigned long io_addr = hw->io_base; |
| 6673 | unsigned long io_data = hw->io_base + 4; |
| 6674 | |
| 6675 | e1000_io_write(hw, io_addr, offset); |
| 6676 | e1000_io_write(hw, io_data, value); |
| 6677 | } |
| 6678 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6679 | /****************************************************************************** |
| 6680 | * Estimates the cable length. |
| 6681 | * |
| 6682 | * hw - Struct containing variables accessed by shared code |
| 6683 | * min_length - The estimated minimum length |
| 6684 | * max_length - The estimated maximum length |
| 6685 | * |
| 6686 | * returns: - E1000_ERR_XXX |
| 6687 | * E1000_SUCCESS |
| 6688 | * |
| 6689 | * This function always returns a ranged length (minimum & maximum). |
| 6690 | * So for M88 phy's, this function interprets the one value returned from the |
| 6691 | * register to the minimum and maximum range. |
| 6692 | * For IGP phy's, the function calculates the range by the AGC registers. |
| 6693 | *****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 6694 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6695 | e1000_get_cable_length(struct e1000_hw *hw, |
| 6696 | uint16_t *min_length, |
| 6697 | uint16_t *max_length) |
| 6698 | { |
| 6699 | int32_t ret_val; |
| 6700 | uint16_t agc_value = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6701 | uint16_t i, phy_data; |
| 6702 | uint16_t cable_length; |
| 6703 | |
| 6704 | DEBUGFUNC("e1000_get_cable_length"); |
| 6705 | |
| 6706 | *min_length = *max_length = 0; |
| 6707 | |
| 6708 | /* Use old method for Phy older than IGP */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6709 | if (hw->phy_type == e1000_phy_m88) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6710 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6711 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
| 6712 | &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6713 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6714 | return ret_val; |
| 6715 | cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> |
| 6716 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; |
| 6717 | |
| 6718 | /* Convert the enum value to ranged values */ |
| 6719 | switch (cable_length) { |
| 6720 | case e1000_cable_length_50: |
| 6721 | *min_length = 0; |
| 6722 | *max_length = e1000_igp_cable_length_50; |
| 6723 | break; |
| 6724 | case e1000_cable_length_50_80: |
| 6725 | *min_length = e1000_igp_cable_length_50; |
| 6726 | *max_length = e1000_igp_cable_length_80; |
| 6727 | break; |
| 6728 | case e1000_cable_length_80_110: |
| 6729 | *min_length = e1000_igp_cable_length_80; |
| 6730 | *max_length = e1000_igp_cable_length_110; |
| 6731 | break; |
| 6732 | case e1000_cable_length_110_140: |
| 6733 | *min_length = e1000_igp_cable_length_110; |
| 6734 | *max_length = e1000_igp_cable_length_140; |
| 6735 | break; |
| 6736 | case e1000_cable_length_140: |
| 6737 | *min_length = e1000_igp_cable_length_140; |
| 6738 | *max_length = e1000_igp_cable_length_170; |
| 6739 | break; |
| 6740 | default: |
| 6741 | return -E1000_ERR_PHY; |
| 6742 | break; |
| 6743 | } |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 6744 | } else if (hw->phy_type == e1000_phy_gg82563) { |
| 6745 | ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, |
| 6746 | &phy_data); |
| 6747 | if (ret_val) |
| 6748 | return ret_val; |
| 6749 | cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH; |
| 6750 | |
| 6751 | switch (cable_length) { |
| 6752 | case e1000_gg_cable_length_60: |
| 6753 | *min_length = 0; |
| 6754 | *max_length = e1000_igp_cable_length_60; |
| 6755 | break; |
| 6756 | case e1000_gg_cable_length_60_115: |
| 6757 | *min_length = e1000_igp_cable_length_60; |
| 6758 | *max_length = e1000_igp_cable_length_115; |
| 6759 | break; |
| 6760 | case e1000_gg_cable_length_115_150: |
| 6761 | *min_length = e1000_igp_cable_length_115; |
| 6762 | *max_length = e1000_igp_cable_length_150; |
| 6763 | break; |
| 6764 | case e1000_gg_cable_length_150: |
| 6765 | *min_length = e1000_igp_cable_length_150; |
| 6766 | *max_length = e1000_igp_cable_length_180; |
| 6767 | break; |
| 6768 | default: |
| 6769 | return -E1000_ERR_PHY; |
| 6770 | break; |
| 6771 | } |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6772 | } else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */ |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6773 | uint16_t cur_agc_value; |
| 6774 | uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6775 | uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = |
| 6776 | {IGP01E1000_PHY_AGC_A, |
| 6777 | IGP01E1000_PHY_AGC_B, |
| 6778 | IGP01E1000_PHY_AGC_C, |
| 6779 | IGP01E1000_PHY_AGC_D}; |
| 6780 | /* Read the AGC registers for all channels */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6781 | for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6782 | |
| 6783 | ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6784 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6785 | return ret_val; |
| 6786 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6787 | cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6788 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6789 | /* Value bound check. */ |
| 6790 | if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || |
| 6791 | (cur_agc_value == 0)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6792 | return -E1000_ERR_PHY; |
| 6793 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6794 | agc_value += cur_agc_value; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6795 | |
| 6796 | /* Update minimal AGC value. */ |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6797 | if (min_agc_value > cur_agc_value) |
| 6798 | min_agc_value = cur_agc_value; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6799 | } |
| 6800 | |
| 6801 | /* Remove the minimal AGC result for length < 50m */ |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6802 | if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) { |
| 6803 | agc_value -= min_agc_value; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6804 | |
| 6805 | /* Get the average length of the remaining 3 channels */ |
| 6806 | agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); |
| 6807 | } else { |
| 6808 | /* Get the average length of all the 4 channels. */ |
| 6809 | agc_value /= IGP01E1000_PHY_CHANNEL_NUM; |
| 6810 | } |
| 6811 | |
| 6812 | /* Set the range of the calculated length. */ |
| 6813 | *min_length = ((e1000_igp_cable_length_table[agc_value] - |
| 6814 | IGP01E1000_AGC_RANGE) > 0) ? |
| 6815 | (e1000_igp_cable_length_table[agc_value] - |
| 6816 | IGP01E1000_AGC_RANGE) : 0; |
| 6817 | *max_length = e1000_igp_cable_length_table[agc_value] + |
| 6818 | IGP01E1000_AGC_RANGE; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6819 | } else if (hw->phy_type == e1000_phy_igp_2 || |
| 6820 | hw->phy_type == e1000_phy_igp_3) { |
| 6821 | uint16_t cur_agc_index, max_agc_index = 0; |
| 6822 | uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1; |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 6823 | uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = |
| 6824 | {IGP02E1000_PHY_AGC_A, |
| 6825 | IGP02E1000_PHY_AGC_B, |
| 6826 | IGP02E1000_PHY_AGC_C, |
| 6827 | IGP02E1000_PHY_AGC_D}; |
| 6828 | /* Read the AGC registers for all channels */ |
| 6829 | for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { |
| 6830 | ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data); |
| 6831 | if (ret_val) |
| 6832 | return ret_val; |
| 6833 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6834 | /* Getting bits 15:9, which represent the combination of course and |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 6835 | * fine gain values. The result is a number that can be put into |
| 6836 | * the lookup table to obtain the approximate cable length. */ |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6837 | cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & |
| 6838 | IGP02E1000_AGC_LENGTH_MASK; |
| 6839 | |
| 6840 | /* Array index bound check. */ |
| 6841 | if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) || |
| 6842 | (cur_agc_index == 0)) |
| 6843 | return -E1000_ERR_PHY; |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 6844 | |
| 6845 | /* Remove min & max AGC values from calculation. */ |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6846 | if (e1000_igp_2_cable_length_table[min_agc_index] > |
| 6847 | e1000_igp_2_cable_length_table[cur_agc_index]) |
| 6848 | min_agc_index = cur_agc_index; |
| 6849 | if (e1000_igp_2_cable_length_table[max_agc_index] < |
| 6850 | e1000_igp_2_cable_length_table[cur_agc_index]) |
| 6851 | max_agc_index = cur_agc_index; |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 6852 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6853 | agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 6854 | } |
| 6855 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6856 | agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + |
| 6857 | e1000_igp_2_cable_length_table[max_agc_index]); |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 6858 | agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); |
| 6859 | |
| 6860 | /* Calculate cable length with the error range of +/- 10 meters. */ |
| 6861 | *min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? |
| 6862 | (agc_value - IGP02E1000_AGC_RANGE) : 0; |
| 6863 | *max_length = agc_value + IGP02E1000_AGC_RANGE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6864 | } |
| 6865 | |
| 6866 | return E1000_SUCCESS; |
| 6867 | } |
| 6868 | |
| 6869 | /****************************************************************************** |
| 6870 | * Check the cable polarity |
| 6871 | * |
| 6872 | * hw - Struct containing variables accessed by shared code |
| 6873 | * polarity - output parameter : 0 - Polarity is not reversed |
| 6874 | * 1 - Polarity is reversed. |
| 6875 | * |
| 6876 | * returns: - E1000_ERR_XXX |
| 6877 | * E1000_SUCCESS |
| 6878 | * |
| 6879 | * For phy's older then IGP, this function simply reads the polarity bit in the |
| 6880 | * Phy Status register. For IGP phy's, this bit is valid only if link speed is |
| 6881 | * 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will |
| 6882 | * return 0. If the link speed is 1000 Mbps the polarity status is in the |
| 6883 | * IGP01E1000_PHY_PCS_INIT_REG. |
| 6884 | *****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 6885 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6886 | e1000_check_polarity(struct e1000_hw *hw, |
Jeff Kirsher | 70c6f30 | 2006-09-27 12:53:31 -0700 | [diff] [blame] | 6887 | e1000_rev_polarity *polarity) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6888 | { |
| 6889 | int32_t ret_val; |
| 6890 | uint16_t phy_data; |
| 6891 | |
| 6892 | DEBUGFUNC("e1000_check_polarity"); |
| 6893 | |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 6894 | if ((hw->phy_type == e1000_phy_m88) || |
| 6895 | (hw->phy_type == e1000_phy_gg82563)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6896 | /* return the Polarity bit in the Status register. */ |
| 6897 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
| 6898 | &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6899 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6900 | return ret_val; |
Jeff Kirsher | 70c6f30 | 2006-09-27 12:53:31 -0700 | [diff] [blame] | 6901 | *polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >> |
| 6902 | M88E1000_PSSR_REV_POLARITY_SHIFT) ? |
| 6903 | e1000_rev_polarity_reversed : e1000_rev_polarity_normal; |
| 6904 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6905 | } else if (hw->phy_type == e1000_phy_igp || |
| 6906 | hw->phy_type == e1000_phy_igp_3 || |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6907 | hw->phy_type == e1000_phy_igp_2) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6908 | /* Read the Status register to check the speed */ |
| 6909 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, |
| 6910 | &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6911 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6912 | return ret_val; |
| 6913 | |
| 6914 | /* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to |
| 6915 | * find the polarity status */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6916 | if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) == |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6917 | IGP01E1000_PSSR_SPEED_1000MBPS) { |
| 6918 | |
| 6919 | /* Read the GIG initialization PCS register (0x00B4) */ |
| 6920 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG, |
| 6921 | &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6922 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6923 | return ret_val; |
| 6924 | |
| 6925 | /* Check the polarity bits */ |
Jeff Kirsher | 70c6f30 | 2006-09-27 12:53:31 -0700 | [diff] [blame] | 6926 | *polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ? |
| 6927 | e1000_rev_polarity_reversed : e1000_rev_polarity_normal; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6928 | } else { |
| 6929 | /* For 10 Mbps, read the polarity bit in the status register. (for |
| 6930 | * 100 Mbps this bit is always 0) */ |
Jeff Kirsher | 70c6f30 | 2006-09-27 12:53:31 -0700 | [diff] [blame] | 6931 | *polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ? |
| 6932 | e1000_rev_polarity_reversed : e1000_rev_polarity_normal; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6933 | } |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6934 | } else if (hw->phy_type == e1000_phy_ife) { |
| 6935 | ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL, |
| 6936 | &phy_data); |
| 6937 | if (ret_val) |
| 6938 | return ret_val; |
Jeff Kirsher | 70c6f30 | 2006-09-27 12:53:31 -0700 | [diff] [blame] | 6939 | *polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >> |
| 6940 | IFE_PESC_POLARITY_REVERSED_SHIFT) ? |
| 6941 | e1000_rev_polarity_reversed : e1000_rev_polarity_normal; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6942 | } |
| 6943 | return E1000_SUCCESS; |
| 6944 | } |
| 6945 | |
| 6946 | /****************************************************************************** |
| 6947 | * Check if Downshift occured |
| 6948 | * |
| 6949 | * hw - Struct containing variables accessed by shared code |
| 6950 | * downshift - output parameter : 0 - No Downshift ocured. |
| 6951 | * 1 - Downshift ocured. |
| 6952 | * |
| 6953 | * returns: - E1000_ERR_XXX |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 6954 | * E1000_SUCCESS |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6955 | * |
| 6956 | * For phy's older then IGP, this function reads the Downshift bit in the Phy |
| 6957 | * Specific Status register. For IGP phy's, it reads the Downgrade bit in the |
| 6958 | * Link Health register. In IGP this bit is latched high, so the driver must |
| 6959 | * read it immediately after link is established. |
| 6960 | *****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 6961 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6962 | e1000_check_downshift(struct e1000_hw *hw) |
| 6963 | { |
| 6964 | int32_t ret_val; |
| 6965 | uint16_t phy_data; |
| 6966 | |
| 6967 | DEBUGFUNC("e1000_check_downshift"); |
| 6968 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6969 | if (hw->phy_type == e1000_phy_igp || |
| 6970 | hw->phy_type == e1000_phy_igp_3 || |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6971 | hw->phy_type == e1000_phy_igp_2) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6972 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH, |
| 6973 | &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6974 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6975 | return ret_val; |
| 6976 | |
| 6977 | hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0; |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 6978 | } else if ((hw->phy_type == e1000_phy_m88) || |
| 6979 | (hw->phy_type == e1000_phy_gg82563)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6980 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, |
| 6981 | &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 6982 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6983 | return ret_val; |
| 6984 | |
| 6985 | hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >> |
| 6986 | M88E1000_PSSR_DOWNSHIFT_SHIFT; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 6987 | } else if (hw->phy_type == e1000_phy_ife) { |
| 6988 | /* e1000_phy_ife supports 10/100 speed only */ |
| 6989 | hw->speed_downgraded = FALSE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6990 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 6991 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6992 | return E1000_SUCCESS; |
| 6993 | } |
| 6994 | |
| 6995 | /***************************************************************************** |
| 6996 | * |
| 6997 | * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a |
| 6998 | * gigabit link is achieved to improve link quality. |
| 6999 | * |
| 7000 | * hw: Struct containing variables accessed by shared code |
| 7001 | * |
| 7002 | * returns: - E1000_ERR_PHY if fail to read/write the PHY |
| 7003 | * E1000_SUCCESS at any other case. |
| 7004 | * |
| 7005 | ****************************************************************************/ |
| 7006 | |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 7007 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7008 | e1000_config_dsp_after_link_change(struct e1000_hw *hw, |
| 7009 | boolean_t link_up) |
| 7010 | { |
| 7011 | int32_t ret_val; |
| 7012 | uint16_t phy_data, phy_saved_data, speed, duplex, i; |
| 7013 | uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = |
| 7014 | {IGP01E1000_PHY_AGC_PARAM_A, |
| 7015 | IGP01E1000_PHY_AGC_PARAM_B, |
| 7016 | IGP01E1000_PHY_AGC_PARAM_C, |
| 7017 | IGP01E1000_PHY_AGC_PARAM_D}; |
| 7018 | uint16_t min_length, max_length; |
| 7019 | |
| 7020 | DEBUGFUNC("e1000_config_dsp_after_link_change"); |
| 7021 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7022 | if (hw->phy_type != e1000_phy_igp) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7023 | return E1000_SUCCESS; |
| 7024 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7025 | if (link_up) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7026 | ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7027 | if (ret_val) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7028 | DEBUGOUT("Error getting link speed and duplex\n"); |
| 7029 | return ret_val; |
| 7030 | } |
| 7031 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7032 | if (speed == SPEED_1000) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7033 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 7034 | ret_val = e1000_get_cable_length(hw, &min_length, &max_length); |
| 7035 | if (ret_val) |
| 7036 | return ret_val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7037 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7038 | if ((hw->dsp_config_state == e1000_dsp_config_enabled) && |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7039 | min_length >= e1000_igp_cable_length_50) { |
| 7040 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7041 | for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7042 | ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], |
| 7043 | &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7044 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7045 | return ret_val; |
| 7046 | |
| 7047 | phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; |
| 7048 | |
| 7049 | ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i], |
| 7050 | phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7051 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7052 | return ret_val; |
| 7053 | } |
| 7054 | hw->dsp_config_state = e1000_dsp_config_activated; |
| 7055 | } |
| 7056 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7057 | if ((hw->ffe_config_state == e1000_ffe_config_enabled) && |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7058 | (min_length < e1000_igp_cable_length_50)) { |
| 7059 | |
| 7060 | uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; |
| 7061 | uint32_t idle_errs = 0; |
| 7062 | |
| 7063 | /* clear previous idle error counts */ |
| 7064 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, |
| 7065 | &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7066 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7067 | return ret_val; |
| 7068 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7069 | for (i = 0; i < ffe_idle_err_timeout; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7070 | udelay(1000); |
| 7071 | ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, |
| 7072 | &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7073 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7074 | return ret_val; |
| 7075 | |
| 7076 | idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7077 | if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7078 | hw->ffe_config_state = e1000_ffe_config_active; |
| 7079 | |
| 7080 | ret_val = e1000_write_phy_reg(hw, |
| 7081 | IGP01E1000_PHY_DSP_FFE, |
| 7082 | IGP01E1000_PHY_DSP_FFE_CM_CP); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7083 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7084 | return ret_val; |
| 7085 | break; |
| 7086 | } |
| 7087 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7088 | if (idle_errs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7089 | ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100; |
| 7090 | } |
| 7091 | } |
| 7092 | } |
| 7093 | } else { |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7094 | if (hw->dsp_config_state == e1000_dsp_config_activated) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7095 | /* Save off the current value of register 0x2F5B to be restored at |
| 7096 | * the end of the routines. */ |
| 7097 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); |
| 7098 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7099 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7100 | return ret_val; |
| 7101 | |
| 7102 | /* Disable the PHY transmitter */ |
| 7103 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); |
| 7104 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7105 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7106 | return ret_val; |
| 7107 | |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 7108 | mdelay(20); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7109 | |
| 7110 | ret_val = e1000_write_phy_reg(hw, 0x0000, |
| 7111 | IGP01E1000_IEEE_FORCE_GIGA); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7112 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7113 | return ret_val; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7114 | for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7115 | ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7116 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7117 | return ret_val; |
| 7118 | |
| 7119 | phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; |
| 7120 | phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; |
| 7121 | |
| 7122 | ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7123 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7124 | return ret_val; |
| 7125 | } |
| 7126 | |
| 7127 | ret_val = e1000_write_phy_reg(hw, 0x0000, |
| 7128 | IGP01E1000_IEEE_RESTART_AUTONEG); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7129 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7130 | return ret_val; |
| 7131 | |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 7132 | mdelay(20); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7133 | |
| 7134 | /* Now enable the transmitter */ |
| 7135 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
| 7136 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7137 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7138 | return ret_val; |
| 7139 | |
| 7140 | hw->dsp_config_state = e1000_dsp_config_enabled; |
| 7141 | } |
| 7142 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7143 | if (hw->ffe_config_state == e1000_ffe_config_active) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7144 | /* Save off the current value of register 0x2F5B to be restored at |
| 7145 | * the end of the routines. */ |
| 7146 | ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data); |
| 7147 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7148 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7149 | return ret_val; |
| 7150 | |
| 7151 | /* Disable the PHY transmitter */ |
| 7152 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003); |
| 7153 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7154 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7155 | return ret_val; |
| 7156 | |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 7157 | mdelay(20); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7158 | |
| 7159 | ret_val = e1000_write_phy_reg(hw, 0x0000, |
| 7160 | IGP01E1000_IEEE_FORCE_GIGA); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7161 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7162 | return ret_val; |
| 7163 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE, |
| 7164 | IGP01E1000_PHY_DSP_FFE_DEFAULT); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7165 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7166 | return ret_val; |
| 7167 | |
| 7168 | ret_val = e1000_write_phy_reg(hw, 0x0000, |
| 7169 | IGP01E1000_IEEE_RESTART_AUTONEG); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7170 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7171 | return ret_val; |
| 7172 | |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 7173 | mdelay(20); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7174 | |
| 7175 | /* Now enable the transmitter */ |
| 7176 | ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data); |
| 7177 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7178 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7179 | return ret_val; |
| 7180 | |
| 7181 | hw->ffe_config_state = e1000_ffe_config_enabled; |
| 7182 | } |
| 7183 | } |
| 7184 | return E1000_SUCCESS; |
| 7185 | } |
| 7186 | |
| 7187 | /***************************************************************************** |
| 7188 | * Set PHY to class A mode |
| 7189 | * Assumes the following operations will follow to enable the new class mode. |
| 7190 | * 1. Do a PHY soft reset |
| 7191 | * 2. Restart auto-negotiation or force link. |
| 7192 | * |
| 7193 | * hw - Struct containing variables accessed by shared code |
| 7194 | ****************************************************************************/ |
| 7195 | static int32_t |
| 7196 | e1000_set_phy_mode(struct e1000_hw *hw) |
| 7197 | { |
| 7198 | int32_t ret_val; |
| 7199 | uint16_t eeprom_data; |
| 7200 | |
| 7201 | DEBUGFUNC("e1000_set_phy_mode"); |
| 7202 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7203 | if ((hw->mac_type == e1000_82545_rev_3) && |
| 7204 | (hw->media_type == e1000_media_type_copper)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7205 | ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7206 | if (ret_val) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7207 | return ret_val; |
| 7208 | } |
| 7209 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7210 | if ((eeprom_data != EEPROM_RESERVED_WORD) && |
| 7211 | (eeprom_data & EEPROM_PHY_CLASS_A)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7212 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7213 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7214 | return ret_val; |
| 7215 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7216 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7217 | return ret_val; |
| 7218 | |
| 7219 | hw->phy_reset_disable = FALSE; |
| 7220 | } |
| 7221 | } |
| 7222 | |
| 7223 | return E1000_SUCCESS; |
| 7224 | } |
| 7225 | |
| 7226 | /***************************************************************************** |
| 7227 | * |
| 7228 | * This function sets the lplu state according to the active flag. When |
| 7229 | * activating lplu this function also disables smart speed and vise versa. |
| 7230 | * lplu will not be activated unless the device autonegotiation advertisment |
| 7231 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. |
| 7232 | * hw: Struct containing variables accessed by shared code |
| 7233 | * active - true to enable lplu false to disable lplu. |
| 7234 | * |
| 7235 | * returns: - E1000_ERR_PHY if fail to read/write the PHY |
| 7236 | * E1000_SUCCESS at any other case. |
| 7237 | * |
| 7238 | ****************************************************************************/ |
| 7239 | |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 7240 | static int32_t |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7241 | e1000_set_d3_lplu_state(struct e1000_hw *hw, |
| 7242 | boolean_t active) |
| 7243 | { |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 7244 | uint32_t phy_ctrl = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7245 | int32_t ret_val; |
| 7246 | uint16_t phy_data; |
| 7247 | DEBUGFUNC("e1000_set_d3_lplu_state"); |
| 7248 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 7249 | if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 |
| 7250 | && hw->phy_type != e1000_phy_igp_3) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7251 | return E1000_SUCCESS; |
| 7252 | |
| 7253 | /* During driver activity LPLU should not be used or it will attain link |
| 7254 | * from the lowest speeds starting from 10Mbps. The capability is used for |
| 7255 | * Dx transitions and states */ |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 7256 | if (hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7257 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data); |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 7258 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7259 | return ret_val; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 7260 | } else if (hw->mac_type == e1000_ich8lan) { |
| 7261 | /* MAC writes into PHY register based on the state transition |
| 7262 | * and start auto-negotiation. SW driver can overwrite the settings |
| 7263 | * in CSR PHY power control E1000_PHY_CTRL register. */ |
| 7264 | phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7265 | } else { |
| 7266 | ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7267 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7268 | return ret_val; |
| 7269 | } |
| 7270 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7271 | if (!active) { |
| 7272 | if (hw->mac_type == e1000_82541_rev_2 || |
| 7273 | hw->mac_type == e1000_82547_rev_2) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7274 | phy_data &= ~IGP01E1000_GMII_FLEX_SPD; |
| 7275 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7276 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7277 | return ret_val; |
| 7278 | } else { |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 7279 | if (hw->mac_type == e1000_ich8lan) { |
| 7280 | phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; |
| 7281 | E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); |
| 7282 | } else { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7283 | phy_data &= ~IGP02E1000_PM_D3_LPLU; |
| 7284 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
| 7285 | phy_data); |
| 7286 | if (ret_val) |
| 7287 | return ret_val; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 7288 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7289 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7290 | |
| 7291 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during |
| 7292 | * Dx states where the power conservation is most important. During |
| 7293 | * driver activity we should enable SmartSpeed, so performance is |
| 7294 | * maintained. */ |
| 7295 | if (hw->smart_speed == e1000_smart_speed_on) { |
| 7296 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 7297 | &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7298 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7299 | return ret_val; |
| 7300 | |
| 7301 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; |
| 7302 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 7303 | phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7304 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7305 | return ret_val; |
| 7306 | } else if (hw->smart_speed == e1000_smart_speed_off) { |
| 7307 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 7308 | &phy_data); |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 7309 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7310 | return ret_val; |
| 7311 | |
| 7312 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 7313 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 7314 | phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7315 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7316 | return ret_val; |
| 7317 | } |
| 7318 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7319 | } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) || |
| 7320 | (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) || |
| 7321 | (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7322 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7323 | if (hw->mac_type == e1000_82541_rev_2 || |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 7324 | hw->mac_type == e1000_82547_rev_2) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7325 | phy_data |= IGP01E1000_GMII_FLEX_SPD; |
| 7326 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7327 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7328 | return ret_val; |
| 7329 | } else { |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 7330 | if (hw->mac_type == e1000_ich8lan) { |
| 7331 | phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; |
| 7332 | E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); |
| 7333 | } else { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7334 | phy_data |= IGP02E1000_PM_D3_LPLU; |
| 7335 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, |
| 7336 | phy_data); |
| 7337 | if (ret_val) |
| 7338 | return ret_val; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 7339 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7340 | } |
| 7341 | |
| 7342 | /* When LPLU is enabled we should disable SmartSpeed */ |
| 7343 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7344 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7345 | return ret_val; |
| 7346 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7347 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 7348 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7349 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7350 | return ret_val; |
| 7351 | |
| 7352 | } |
| 7353 | return E1000_SUCCESS; |
| 7354 | } |
| 7355 | |
| 7356 | /***************************************************************************** |
| 7357 | * |
| 7358 | * This function sets the lplu d0 state according to the active flag. When |
| 7359 | * activating lplu this function also disables smart speed and vise versa. |
| 7360 | * lplu will not be activated unless the device autonegotiation advertisment |
| 7361 | * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes. |
| 7362 | * hw: Struct containing variables accessed by shared code |
| 7363 | * active - true to enable lplu false to disable lplu. |
| 7364 | * |
| 7365 | * returns: - E1000_ERR_PHY if fail to read/write the PHY |
| 7366 | * E1000_SUCCESS at any other case. |
| 7367 | * |
| 7368 | ****************************************************************************/ |
| 7369 | |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 7370 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7371 | e1000_set_d0_lplu_state(struct e1000_hw *hw, |
| 7372 | boolean_t active) |
| 7373 | { |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 7374 | uint32_t phy_ctrl = 0; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7375 | int32_t ret_val; |
| 7376 | uint16_t phy_data; |
| 7377 | DEBUGFUNC("e1000_set_d0_lplu_state"); |
| 7378 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7379 | if (hw->mac_type <= e1000_82547_rev_2) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7380 | return E1000_SUCCESS; |
| 7381 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 7382 | if (hw->mac_type == e1000_ich8lan) { |
| 7383 | phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); |
| 7384 | } else { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7385 | ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7386 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7387 | return ret_val; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 7388 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7389 | |
| 7390 | if (!active) { |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 7391 | if (hw->mac_type == e1000_ich8lan) { |
| 7392 | phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; |
| 7393 | E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); |
| 7394 | } else { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7395 | phy_data &= ~IGP02E1000_PM_D0_LPLU; |
| 7396 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); |
| 7397 | if (ret_val) |
| 7398 | return ret_val; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 7399 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7400 | |
| 7401 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during |
| 7402 | * Dx states where the power conservation is most important. During |
| 7403 | * driver activity we should enable SmartSpeed, so performance is |
| 7404 | * maintained. */ |
| 7405 | if (hw->smart_speed == e1000_smart_speed_on) { |
| 7406 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 7407 | &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7408 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7409 | return ret_val; |
| 7410 | |
| 7411 | phy_data |= IGP01E1000_PSCFR_SMART_SPEED; |
| 7412 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 7413 | phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7414 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7415 | return ret_val; |
| 7416 | } else if (hw->smart_speed == e1000_smart_speed_off) { |
| 7417 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 7418 | &phy_data); |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 7419 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7420 | return ret_val; |
| 7421 | |
| 7422 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 7423 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, |
| 7424 | phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7425 | if (ret_val) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7426 | return ret_val; |
| 7427 | } |
| 7428 | |
| 7429 | |
| 7430 | } else { |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 7431 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 7432 | if (hw->mac_type == e1000_ich8lan) { |
| 7433 | phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; |
| 7434 | E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); |
| 7435 | } else { |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 7436 | phy_data |= IGP02E1000_PM_D0_LPLU; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7437 | ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); |
| 7438 | if (ret_val) |
| 7439 | return ret_val; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 7440 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7441 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7442 | /* When LPLU is enabled we should disable SmartSpeed */ |
| 7443 | ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7444 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7445 | return ret_val; |
| 7446 | |
| 7447 | phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED; |
| 7448 | ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7449 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7450 | return ret_val; |
| 7451 | |
| 7452 | } |
| 7453 | return E1000_SUCCESS; |
| 7454 | } |
| 7455 | |
| 7456 | /****************************************************************************** |
| 7457 | * Change VCO speed register to improve Bit Error Rate performance of SERDES. |
| 7458 | * |
| 7459 | * hw - Struct containing variables accessed by shared code |
| 7460 | *****************************************************************************/ |
| 7461 | static int32_t |
| 7462 | e1000_set_vco_speed(struct e1000_hw *hw) |
| 7463 | { |
| 7464 | int32_t ret_val; |
| 7465 | uint16_t default_page = 0; |
| 7466 | uint16_t phy_data; |
| 7467 | |
| 7468 | DEBUGFUNC("e1000_set_vco_speed"); |
| 7469 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7470 | switch (hw->mac_type) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7471 | case e1000_82545_rev_3: |
| 7472 | case e1000_82546_rev_3: |
| 7473 | break; |
| 7474 | default: |
| 7475 | return E1000_SUCCESS; |
| 7476 | } |
| 7477 | |
| 7478 | /* Set PHY register 30, page 5, bit 8 to 0 */ |
| 7479 | |
| 7480 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7481 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7482 | return ret_val; |
| 7483 | |
| 7484 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7485 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7486 | return ret_val; |
| 7487 | |
| 7488 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7489 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7490 | return ret_val; |
| 7491 | |
| 7492 | phy_data &= ~M88E1000_PHY_VCO_REG_BIT8; |
| 7493 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7494 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7495 | return ret_val; |
| 7496 | |
| 7497 | /* Set PHY register 30, page 4, bit 11 to 1 */ |
| 7498 | |
| 7499 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7500 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7501 | return ret_val; |
| 7502 | |
| 7503 | ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7504 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7505 | return ret_val; |
| 7506 | |
| 7507 | phy_data |= M88E1000_PHY_VCO_REG_BIT11; |
| 7508 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7509 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7510 | return ret_val; |
| 7511 | |
| 7512 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7513 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7514 | return ret_val; |
| 7515 | |
| 7516 | return E1000_SUCCESS; |
| 7517 | } |
| 7518 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7519 | |
| 7520 | /***************************************************************************** |
| 7521 | * This function reads the cookie from ARC ram. |
| 7522 | * |
| 7523 | * returns: - E1000_SUCCESS . |
| 7524 | ****************************************************************************/ |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 7525 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7526 | e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer) |
| 7527 | { |
| 7528 | uint8_t i; |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 7529 | uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7530 | uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH; |
| 7531 | |
| 7532 | length = (length >> 2); |
| 7533 | offset = (offset >> 2); |
| 7534 | |
| 7535 | for (i = 0; i < length; i++) { |
| 7536 | *((uint32_t *) buffer + i) = |
| 7537 | E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i); |
| 7538 | } |
| 7539 | return E1000_SUCCESS; |
| 7540 | } |
| 7541 | |
| 7542 | |
| 7543 | /***************************************************************************** |
| 7544 | * This function checks whether the HOST IF is enabled for command operaton |
| 7545 | * and also checks whether the previous command is completed. |
| 7546 | * It busy waits in case of previous command is not completed. |
| 7547 | * |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 7548 | * returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7549 | * timeout |
| 7550 | * - E1000_SUCCESS for success. |
| 7551 | ****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 7552 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7553 | e1000_mng_enable_host_if(struct e1000_hw * hw) |
| 7554 | { |
| 7555 | uint32_t hicr; |
| 7556 | uint8_t i; |
| 7557 | |
| 7558 | /* Check that the host interface is enabled. */ |
| 7559 | hicr = E1000_READ_REG(hw, HICR); |
| 7560 | if ((hicr & E1000_HICR_EN) == 0) { |
| 7561 | DEBUGOUT("E1000_HOST_EN bit disabled.\n"); |
| 7562 | return -E1000_ERR_HOST_INTERFACE_COMMAND; |
| 7563 | } |
| 7564 | /* check the previous command is completed */ |
| 7565 | for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) { |
| 7566 | hicr = E1000_READ_REG(hw, HICR); |
| 7567 | if (!(hicr & E1000_HICR_C)) |
| 7568 | break; |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 7569 | mdelay(1); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7570 | } |
| 7571 | |
Auke Kok | 76c224b | 2006-05-23 13:36:06 -0700 | [diff] [blame] | 7572 | if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7573 | DEBUGOUT("Previous command timeout failed .\n"); |
| 7574 | return -E1000_ERR_HOST_INTERFACE_COMMAND; |
| 7575 | } |
| 7576 | return E1000_SUCCESS; |
| 7577 | } |
| 7578 | |
| 7579 | /***************************************************************************** |
| 7580 | * This function writes the buffer content at the offset given on the host if. |
| 7581 | * It also does alignment considerations to do the writes in most efficient way. |
| 7582 | * Also fills up the sum of the buffer in *buffer parameter. |
| 7583 | * |
| 7584 | * returns - E1000_SUCCESS for success. |
| 7585 | ****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 7586 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7587 | e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer, |
| 7588 | uint16_t length, uint16_t offset, uint8_t *sum) |
| 7589 | { |
| 7590 | uint8_t *tmp; |
| 7591 | uint8_t *bufptr = buffer; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7592 | uint32_t data = 0; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7593 | uint16_t remaining, i, j, prev_bytes; |
| 7594 | |
| 7595 | /* sum = only sum of the data and it is not checksum */ |
| 7596 | |
| 7597 | if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) { |
| 7598 | return -E1000_ERR_PARAM; |
| 7599 | } |
| 7600 | |
| 7601 | tmp = (uint8_t *)&data; |
| 7602 | prev_bytes = offset & 0x3; |
| 7603 | offset &= 0xFFFC; |
| 7604 | offset >>= 2; |
| 7605 | |
| 7606 | if (prev_bytes) { |
| 7607 | data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset); |
| 7608 | for (j = prev_bytes; j < sizeof(uint32_t); j++) { |
| 7609 | *(tmp + j) = *bufptr++; |
| 7610 | *sum += *(tmp + j); |
| 7611 | } |
| 7612 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data); |
| 7613 | length -= j - prev_bytes; |
| 7614 | offset++; |
| 7615 | } |
| 7616 | |
| 7617 | remaining = length & 0x3; |
| 7618 | length -= remaining; |
| 7619 | |
| 7620 | /* Calculate length in DWORDs */ |
| 7621 | length >>= 2; |
| 7622 | |
| 7623 | /* The device driver writes the relevant command block into the |
| 7624 | * ram area. */ |
| 7625 | for (i = 0; i < length; i++) { |
| 7626 | for (j = 0; j < sizeof(uint32_t); j++) { |
| 7627 | *(tmp + j) = *bufptr++; |
| 7628 | *sum += *(tmp + j); |
| 7629 | } |
| 7630 | |
| 7631 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); |
| 7632 | } |
| 7633 | if (remaining) { |
| 7634 | for (j = 0; j < sizeof(uint32_t); j++) { |
| 7635 | if (j < remaining) |
| 7636 | *(tmp + j) = *bufptr++; |
| 7637 | else |
| 7638 | *(tmp + j) = 0; |
| 7639 | |
| 7640 | *sum += *(tmp + j); |
| 7641 | } |
| 7642 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data); |
| 7643 | } |
| 7644 | |
| 7645 | return E1000_SUCCESS; |
| 7646 | } |
| 7647 | |
| 7648 | |
| 7649 | /***************************************************************************** |
| 7650 | * This function writes the command header after does the checksum calculation. |
| 7651 | * |
| 7652 | * returns - E1000_SUCCESS for success. |
| 7653 | ****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 7654 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7655 | e1000_mng_write_cmd_header(struct e1000_hw * hw, |
| 7656 | struct e1000_host_mng_command_header * hdr) |
| 7657 | { |
| 7658 | uint16_t i; |
| 7659 | uint8_t sum; |
| 7660 | uint8_t *buffer; |
| 7661 | |
| 7662 | /* Write the whole command header structure which includes sum of |
| 7663 | * the buffer */ |
| 7664 | |
| 7665 | uint16_t length = sizeof(struct e1000_host_mng_command_header); |
| 7666 | |
| 7667 | sum = hdr->checksum; |
| 7668 | hdr->checksum = 0; |
| 7669 | |
| 7670 | buffer = (uint8_t *) hdr; |
| 7671 | i = length; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7672 | while (i--) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7673 | sum += buffer[i]; |
| 7674 | |
| 7675 | hdr->checksum = 0 - sum; |
| 7676 | |
| 7677 | length >>= 2; |
| 7678 | /* The device driver writes the relevant command block into the ram area. */ |
Auke Kok | 4ca213a | 2006-06-27 09:07:08 -0700 | [diff] [blame] | 7679 | for (i = 0; i < length; i++) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7680 | E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, *((uint32_t *) hdr + i)); |
Auke Kok | 4ca213a | 2006-06-27 09:07:08 -0700 | [diff] [blame] | 7681 | E1000_WRITE_FLUSH(hw); |
| 7682 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7683 | |
| 7684 | return E1000_SUCCESS; |
| 7685 | } |
| 7686 | |
| 7687 | |
| 7688 | /***************************************************************************** |
| 7689 | * This function indicates to ARC that a new command is pending which completes |
| 7690 | * one write operation by the driver. |
| 7691 | * |
| 7692 | * returns - E1000_SUCCESS for success. |
| 7693 | ****************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 7694 | static int32_t |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7695 | e1000_mng_write_commit(struct e1000_hw * hw) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7696 | { |
| 7697 | uint32_t hicr; |
| 7698 | |
| 7699 | hicr = E1000_READ_REG(hw, HICR); |
| 7700 | /* Setting this bit tells the ARC that a new command is pending. */ |
| 7701 | E1000_WRITE_REG(hw, HICR, hicr | E1000_HICR_C); |
| 7702 | |
| 7703 | return E1000_SUCCESS; |
| 7704 | } |
| 7705 | |
| 7706 | |
| 7707 | /***************************************************************************** |
| 7708 | * This function checks the mode of the firmware. |
| 7709 | * |
| 7710 | * returns - TRUE when the mode is IAMT or FALSE. |
| 7711 | ****************************************************************************/ |
| 7712 | boolean_t |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 7713 | e1000_check_mng_mode(struct e1000_hw *hw) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7714 | { |
| 7715 | uint32_t fwsm; |
| 7716 | |
| 7717 | fwsm = E1000_READ_REG(hw, FWSM); |
| 7718 | |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 7719 | if (hw->mac_type == e1000_ich8lan) { |
| 7720 | if ((fwsm & E1000_FWSM_MODE_MASK) == |
| 7721 | (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) |
| 7722 | return TRUE; |
| 7723 | } else if ((fwsm & E1000_FWSM_MODE_MASK) == |
| 7724 | (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7725 | return TRUE; |
| 7726 | |
| 7727 | return FALSE; |
| 7728 | } |
| 7729 | |
| 7730 | |
| 7731 | /***************************************************************************** |
| 7732 | * This function writes the dhcp info . |
| 7733 | ****************************************************************************/ |
| 7734 | int32_t |
| 7735 | e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer, |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 7736 | uint16_t length) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7737 | { |
| 7738 | int32_t ret_val; |
| 7739 | struct e1000_host_mng_command_header hdr; |
| 7740 | |
| 7741 | hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD; |
| 7742 | hdr.command_length = length; |
| 7743 | hdr.reserved1 = 0; |
| 7744 | hdr.reserved2 = 0; |
| 7745 | hdr.checksum = 0; |
| 7746 | |
| 7747 | ret_val = e1000_mng_enable_host_if(hw); |
| 7748 | if (ret_val == E1000_SUCCESS) { |
| 7749 | ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr), |
| 7750 | &(hdr.checksum)); |
| 7751 | if (ret_val == E1000_SUCCESS) { |
| 7752 | ret_val = e1000_mng_write_cmd_header(hw, &hdr); |
| 7753 | if (ret_val == E1000_SUCCESS) |
| 7754 | ret_val = e1000_mng_write_commit(hw); |
| 7755 | } |
| 7756 | } |
| 7757 | return ret_val; |
| 7758 | } |
| 7759 | |
| 7760 | |
| 7761 | /***************************************************************************** |
| 7762 | * This function calculates the checksum. |
| 7763 | * |
| 7764 | * returns - checksum of buffer contents. |
| 7765 | ****************************************************************************/ |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 7766 | static uint8_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7767 | e1000_calculate_mng_checksum(char *buffer, uint32_t length) |
| 7768 | { |
| 7769 | uint8_t sum = 0; |
| 7770 | uint32_t i; |
| 7771 | |
| 7772 | if (!buffer) |
| 7773 | return 0; |
| 7774 | |
| 7775 | for (i=0; i < length; i++) |
| 7776 | sum += buffer[i]; |
| 7777 | |
| 7778 | return (uint8_t) (0 - sum); |
| 7779 | } |
| 7780 | |
| 7781 | /***************************************************************************** |
| 7782 | * This function checks whether tx pkt filtering needs to be enabled or not. |
| 7783 | * |
| 7784 | * returns - TRUE for packet filtering or FALSE. |
| 7785 | ****************************************************************************/ |
| 7786 | boolean_t |
| 7787 | e1000_enable_tx_pkt_filtering(struct e1000_hw *hw) |
| 7788 | { |
| 7789 | /* called in init as well as watchdog timer functions */ |
| 7790 | |
| 7791 | int32_t ret_val, checksum; |
| 7792 | boolean_t tx_filter = FALSE; |
| 7793 | struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie); |
| 7794 | uint8_t *buffer = (uint8_t *) &(hw->mng_cookie); |
| 7795 | |
| 7796 | if (e1000_check_mng_mode(hw)) { |
| 7797 | ret_val = e1000_mng_enable_host_if(hw); |
| 7798 | if (ret_val == E1000_SUCCESS) { |
| 7799 | ret_val = e1000_host_if_read_cookie(hw, buffer); |
| 7800 | if (ret_val == E1000_SUCCESS) { |
| 7801 | checksum = hdr->checksum; |
| 7802 | hdr->checksum = 0; |
| 7803 | if ((hdr->signature == E1000_IAMT_SIGNATURE) && |
| 7804 | checksum == e1000_calculate_mng_checksum((char *)buffer, |
| 7805 | E1000_MNG_DHCP_COOKIE_LENGTH)) { |
| 7806 | if (hdr->status & |
| 7807 | E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT) |
| 7808 | tx_filter = TRUE; |
| 7809 | } else |
| 7810 | tx_filter = TRUE; |
| 7811 | } else |
| 7812 | tx_filter = TRUE; |
| 7813 | } |
| 7814 | } |
| 7815 | |
| 7816 | hw->tx_pkt_filtering = tx_filter; |
| 7817 | return tx_filter; |
| 7818 | } |
| 7819 | |
| 7820 | /****************************************************************************** |
| 7821 | * Verifies the hardware needs to allow ARPs to be processed by the host |
| 7822 | * |
| 7823 | * hw - Struct containing variables accessed by shared code |
| 7824 | * |
| 7825 | * returns: - TRUE/FALSE |
| 7826 | * |
| 7827 | *****************************************************************************/ |
| 7828 | uint32_t |
| 7829 | e1000_enable_mng_pass_thru(struct e1000_hw *hw) |
| 7830 | { |
| 7831 | uint32_t manc; |
| 7832 | uint32_t fwsm, factps; |
| 7833 | |
| 7834 | if (hw->asf_firmware_present) { |
| 7835 | manc = E1000_READ_REG(hw, MANC); |
| 7836 | |
| 7837 | if (!(manc & E1000_MANC_RCV_TCO_EN) || |
| 7838 | !(manc & E1000_MANC_EN_MAC_ADDR_FILTER)) |
| 7839 | return FALSE; |
| 7840 | if (e1000_arc_subsystem_valid(hw) == TRUE) { |
| 7841 | fwsm = E1000_READ_REG(hw, FWSM); |
| 7842 | factps = E1000_READ_REG(hw, FACTPS); |
| 7843 | |
Jeff Garzik | 0fccd0e | 2006-12-15 10:56:10 -0500 | [diff] [blame] | 7844 | if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) == |
| 7845 | e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG)) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7846 | return TRUE; |
| 7847 | } else |
| 7848 | if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN)) |
| 7849 | return TRUE; |
| 7850 | } |
| 7851 | return FALSE; |
| 7852 | } |
| 7853 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7854 | static int32_t |
| 7855 | e1000_polarity_reversal_workaround(struct e1000_hw *hw) |
| 7856 | { |
| 7857 | int32_t ret_val; |
| 7858 | uint16_t mii_status_reg; |
| 7859 | uint16_t i; |
| 7860 | |
| 7861 | /* Polarity reversal workaround for forced 10F/10H links. */ |
| 7862 | |
| 7863 | /* Disable the transmitter on the PHY */ |
| 7864 | |
| 7865 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7866 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7867 | return ret_val; |
| 7868 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7869 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7870 | return ret_val; |
| 7871 | |
| 7872 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7873 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7874 | return ret_val; |
| 7875 | |
| 7876 | /* This loop will early-out if the NO link condition has been met. */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7877 | for (i = PHY_FORCE_TIME; i > 0; i--) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7878 | /* Read the MII Status Register and wait for Link Status bit |
| 7879 | * to be clear. |
| 7880 | */ |
| 7881 | |
| 7882 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7883 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7884 | return ret_val; |
| 7885 | |
| 7886 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7887 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7888 | return ret_val; |
| 7889 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7890 | if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break; |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 7891 | mdelay(100); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7892 | } |
| 7893 | |
| 7894 | /* Recommended delay time after link has been lost */ |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 7895 | mdelay(1000); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7896 | |
| 7897 | /* Now we will re-enable th transmitter on the PHY */ |
| 7898 | |
| 7899 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7900 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7901 | return ret_val; |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 7902 | mdelay(50); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7903 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7904 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7905 | return ret_val; |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 7906 | mdelay(50); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7907 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7908 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7909 | return ret_val; |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 7910 | mdelay(50); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7911 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7912 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7913 | return ret_val; |
| 7914 | |
| 7915 | ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7916 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7917 | return ret_val; |
| 7918 | |
| 7919 | /* This loop will early-out if the link condition has been met. */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7920 | for (i = PHY_FORCE_TIME; i > 0; i--) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7921 | /* Read the MII Status Register and wait for Link Status bit |
| 7922 | * to be set. |
| 7923 | */ |
| 7924 | |
| 7925 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7926 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7927 | return ret_val; |
| 7928 | |
| 7929 | ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7930 | if (ret_val) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7931 | return ret_val; |
| 7932 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7933 | if (mii_status_reg & MII_SR_LINK_STATUS) break; |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 7934 | mdelay(100); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7935 | } |
| 7936 | return E1000_SUCCESS; |
| 7937 | } |
| 7938 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7939 | /*************************************************************************** |
| 7940 | * |
| 7941 | * Disables PCI-Express master access. |
| 7942 | * |
| 7943 | * hw: Struct containing variables accessed by shared code |
| 7944 | * |
| 7945 | * returns: - none. |
| 7946 | * |
| 7947 | ***************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 7948 | static void |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7949 | e1000_set_pci_express_master_disable(struct e1000_hw *hw) |
| 7950 | { |
| 7951 | uint32_t ctrl; |
| 7952 | |
| 7953 | DEBUGFUNC("e1000_set_pci_express_master_disable"); |
| 7954 | |
| 7955 | if (hw->bus_type != e1000_bus_type_pci_express) |
| 7956 | return; |
| 7957 | |
| 7958 | ctrl = E1000_READ_REG(hw, CTRL); |
| 7959 | ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; |
| 7960 | E1000_WRITE_REG(hw, CTRL, ctrl); |
| 7961 | } |
| 7962 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7963 | /******************************************************************************* |
| 7964 | * |
| 7965 | * Disables PCI-Express master access and verifies there are no pending requests |
| 7966 | * |
| 7967 | * hw: Struct containing variables accessed by shared code |
| 7968 | * |
| 7969 | * returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't |
| 7970 | * caused the master requests to be disabled. |
| 7971 | * E1000_SUCCESS master requests disabled. |
| 7972 | * |
| 7973 | ******************************************************************************/ |
| 7974 | int32_t |
| 7975 | e1000_disable_pciex_master(struct e1000_hw *hw) |
| 7976 | { |
| 7977 | int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */ |
| 7978 | |
| 7979 | DEBUGFUNC("e1000_disable_pciex_master"); |
| 7980 | |
| 7981 | if (hw->bus_type != e1000_bus_type_pci_express) |
| 7982 | return E1000_SUCCESS; |
| 7983 | |
| 7984 | e1000_set_pci_express_master_disable(hw); |
| 7985 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7986 | while (timeout) { |
| 7987 | if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7988 | break; |
| 7989 | else |
| 7990 | udelay(100); |
| 7991 | timeout--; |
| 7992 | } |
| 7993 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 7994 | if (!timeout) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 7995 | DEBUGOUT("Master requests are pending.\n"); |
| 7996 | return -E1000_ERR_MASTER_REQUESTS_PENDING; |
| 7997 | } |
| 7998 | |
| 7999 | return E1000_SUCCESS; |
| 8000 | } |
| 8001 | |
| 8002 | /******************************************************************************* |
| 8003 | * |
| 8004 | * Check for EEPROM Auto Read bit done. |
| 8005 | * |
| 8006 | * hw: Struct containing variables accessed by shared code |
| 8007 | * |
| 8008 | * returns: - E1000_ERR_RESET if fail to reset MAC |
| 8009 | * E1000_SUCCESS at any other case. |
| 8010 | * |
| 8011 | ******************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 8012 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8013 | e1000_get_auto_rd_done(struct e1000_hw *hw) |
| 8014 | { |
| 8015 | int32_t timeout = AUTO_READ_DONE_TIMEOUT; |
| 8016 | |
| 8017 | DEBUGFUNC("e1000_get_auto_rd_done"); |
| 8018 | |
| 8019 | switch (hw->mac_type) { |
| 8020 | default: |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 8021 | msleep(5); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8022 | break; |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 8023 | case e1000_82571: |
| 8024 | case e1000_82572: |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8025 | case e1000_82573: |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 8026 | case e1000_80003es2lan: |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 8027 | case e1000_ich8lan: |
| 8028 | while (timeout) { |
| 8029 | if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) |
| 8030 | break; |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 8031 | else msleep(1); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8032 | timeout--; |
| 8033 | } |
| 8034 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 8035 | if (!timeout) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8036 | DEBUGOUT("Auto read by HW from EEPROM has not completed.\n"); |
| 8037 | return -E1000_ERR_RESET; |
| 8038 | } |
| 8039 | break; |
| 8040 | } |
| 8041 | |
Jeff Kirsher | fd80324 | 2005-12-13 00:06:22 -0500 | [diff] [blame] | 8042 | /* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high. |
| 8043 | * Need to wait for PHY configuration completion before accessing NVM |
| 8044 | * and PHY. */ |
| 8045 | if (hw->mac_type == e1000_82573) |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 8046 | msleep(25); |
Jeff Kirsher | fd80324 | 2005-12-13 00:06:22 -0500 | [diff] [blame] | 8047 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8048 | return E1000_SUCCESS; |
| 8049 | } |
| 8050 | |
| 8051 | /*************************************************************************** |
| 8052 | * Checks if the PHY configuration is done |
| 8053 | * |
| 8054 | * hw: Struct containing variables accessed by shared code |
| 8055 | * |
| 8056 | * returns: - E1000_ERR_RESET if fail to reset MAC |
| 8057 | * E1000_SUCCESS at any other case. |
| 8058 | * |
| 8059 | ***************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 8060 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8061 | e1000_get_phy_cfg_done(struct e1000_hw *hw) |
| 8062 | { |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 8063 | int32_t timeout = PHY_CFG_TIMEOUT; |
| 8064 | uint32_t cfg_mask = E1000_EEPROM_CFG_DONE; |
| 8065 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8066 | DEBUGFUNC("e1000_get_phy_cfg_done"); |
| 8067 | |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 8068 | switch (hw->mac_type) { |
| 8069 | default: |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 8070 | mdelay(10); |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 8071 | break; |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 8072 | case e1000_80003es2lan: |
| 8073 | /* Separate *_CFG_DONE_* bit for each port */ |
| 8074 | if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) |
| 8075 | cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; |
| 8076 | /* Fall Through */ |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 8077 | case e1000_82571: |
| 8078 | case e1000_82572: |
| 8079 | while (timeout) { |
| 8080 | if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask) |
| 8081 | break; |
| 8082 | else |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 8083 | msleep(1); |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 8084 | timeout--; |
| 8085 | } |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 8086 | if (!timeout) { |
| 8087 | DEBUGOUT("MNG configuration cycle has not completed.\n"); |
| 8088 | return -E1000_ERR_RESET; |
| 8089 | } |
| 8090 | break; |
| 8091 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8092 | |
| 8093 | return E1000_SUCCESS; |
| 8094 | } |
| 8095 | |
| 8096 | /*************************************************************************** |
| 8097 | * |
| 8098 | * Using the combination of SMBI and SWESMBI semaphore bits when resetting |
| 8099 | * adapter or Eeprom access. |
| 8100 | * |
| 8101 | * hw: Struct containing variables accessed by shared code |
| 8102 | * |
| 8103 | * returns: - E1000_ERR_EEPROM if fail to access EEPROM. |
| 8104 | * E1000_SUCCESS at any other case. |
| 8105 | * |
| 8106 | ***************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 8107 | static int32_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8108 | e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw) |
| 8109 | { |
| 8110 | int32_t timeout; |
| 8111 | uint32_t swsm; |
| 8112 | |
| 8113 | DEBUGFUNC("e1000_get_hw_eeprom_semaphore"); |
| 8114 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 8115 | if (!hw->eeprom_semaphore_present) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8116 | return E1000_SUCCESS; |
| 8117 | |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 8118 | if (hw->mac_type == e1000_80003es2lan) { |
| 8119 | /* Get the SW semaphore. */ |
| 8120 | if (e1000_get_software_semaphore(hw) != E1000_SUCCESS) |
| 8121 | return -E1000_ERR_EEPROM; |
| 8122 | } |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8123 | |
| 8124 | /* Get the FW semaphore. */ |
| 8125 | timeout = hw->eeprom.word_size + 1; |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 8126 | while (timeout) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8127 | swsm = E1000_READ_REG(hw, SWSM); |
| 8128 | swsm |= E1000_SWSM_SWESMBI; |
| 8129 | E1000_WRITE_REG(hw, SWSM, swsm); |
| 8130 | /* if we managed to set the bit we got the semaphore. */ |
| 8131 | swsm = E1000_READ_REG(hw, SWSM); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 8132 | if (swsm & E1000_SWSM_SWESMBI) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8133 | break; |
| 8134 | |
| 8135 | udelay(50); |
| 8136 | timeout--; |
| 8137 | } |
| 8138 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 8139 | if (!timeout) { |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8140 | /* Release semaphores */ |
| 8141 | e1000_put_hw_eeprom_semaphore(hw); |
| 8142 | DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n"); |
| 8143 | return -E1000_ERR_EEPROM; |
| 8144 | } |
| 8145 | |
| 8146 | return E1000_SUCCESS; |
| 8147 | } |
| 8148 | |
| 8149 | /*************************************************************************** |
| 8150 | * This function clears HW semaphore bits. |
| 8151 | * |
| 8152 | * hw: Struct containing variables accessed by shared code |
| 8153 | * |
| 8154 | * returns: - None. |
| 8155 | * |
| 8156 | ***************************************************************************/ |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 8157 | static void |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8158 | e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw) |
| 8159 | { |
| 8160 | uint32_t swsm; |
| 8161 | |
| 8162 | DEBUGFUNC("e1000_put_hw_eeprom_semaphore"); |
| 8163 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 8164 | if (!hw->eeprom_semaphore_present) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8165 | return; |
| 8166 | |
| 8167 | swsm = E1000_READ_REG(hw, SWSM); |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 8168 | if (hw->mac_type == e1000_80003es2lan) { |
| 8169 | /* Release both semaphores. */ |
| 8170 | swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); |
| 8171 | } else |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 8172 | swsm &= ~(E1000_SWSM_SWESMBI); |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8173 | E1000_WRITE_REG(hw, SWSM, swsm); |
| 8174 | } |
| 8175 | |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 8176 | /*************************************************************************** |
| 8177 | * |
| 8178 | * Obtaining software semaphore bit (SMBI) before resetting PHY. |
| 8179 | * |
| 8180 | * hw: Struct containing variables accessed by shared code |
| 8181 | * |
| 8182 | * returns: - E1000_ERR_RESET if fail to obtain semaphore. |
| 8183 | * E1000_SUCCESS at any other case. |
| 8184 | * |
| 8185 | ***************************************************************************/ |
Adrian Bunk | e4c780b | 2006-08-14 23:00:10 -0700 | [diff] [blame] | 8186 | static int32_t |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 8187 | e1000_get_software_semaphore(struct e1000_hw *hw) |
| 8188 | { |
| 8189 | int32_t timeout = hw->eeprom.word_size + 1; |
| 8190 | uint32_t swsm; |
| 8191 | |
| 8192 | DEBUGFUNC("e1000_get_software_semaphore"); |
| 8193 | |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 8194 | if (hw->mac_type != e1000_80003es2lan) { |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 8195 | return E1000_SUCCESS; |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 8196 | } |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 8197 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 8198 | while (timeout) { |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 8199 | swsm = E1000_READ_REG(hw, SWSM); |
| 8200 | /* If SMBI bit cleared, it is now set and we hold the semaphore */ |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 8201 | if (!(swsm & E1000_SWSM_SMBI)) |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 8202 | break; |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 8203 | mdelay(1); |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 8204 | timeout--; |
| 8205 | } |
| 8206 | |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 8207 | if (!timeout) { |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 8208 | DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); |
| 8209 | return -E1000_ERR_RESET; |
| 8210 | } |
| 8211 | |
| 8212 | return E1000_SUCCESS; |
| 8213 | } |
| 8214 | |
| 8215 | /*************************************************************************** |
| 8216 | * |
| 8217 | * Release semaphore bit (SMBI). |
| 8218 | * |
| 8219 | * hw: Struct containing variables accessed by shared code |
| 8220 | * |
| 8221 | ***************************************************************************/ |
Adrian Bunk | e4c780b | 2006-08-14 23:00:10 -0700 | [diff] [blame] | 8222 | static void |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 8223 | e1000_release_software_semaphore(struct e1000_hw *hw) |
| 8224 | { |
| 8225 | uint32_t swsm; |
| 8226 | |
| 8227 | DEBUGFUNC("e1000_release_software_semaphore"); |
| 8228 | |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 8229 | if (hw->mac_type != e1000_80003es2lan) { |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 8230 | return; |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 8231 | } |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 8232 | |
| 8233 | swsm = E1000_READ_REG(hw, SWSM); |
| 8234 | /* Release the SW semaphores.*/ |
| 8235 | swsm &= ~E1000_SWSM_SMBI; |
| 8236 | E1000_WRITE_REG(hw, SWSM, swsm); |
| 8237 | } |
| 8238 | |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8239 | /****************************************************************************** |
| 8240 | * Checks if PHY reset is blocked due to SOL/IDER session, for example. |
| 8241 | * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to |
| 8242 | * the caller to figure out how to deal with it. |
| 8243 | * |
| 8244 | * hw - Struct containing variables accessed by shared code |
| 8245 | * |
| 8246 | * returns: - E1000_BLK_PHY_RESET |
| 8247 | * E1000_SUCCESS |
| 8248 | * |
| 8249 | *****************************************************************************/ |
| 8250 | int32_t |
| 8251 | e1000_check_phy_reset_block(struct e1000_hw *hw) |
| 8252 | { |
| 8253 | uint32_t manc = 0; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 8254 | uint32_t fwsm = 0; |
| 8255 | |
| 8256 | if (hw->mac_type == e1000_ich8lan) { |
| 8257 | fwsm = E1000_READ_REG(hw, FWSM); |
| 8258 | return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS |
| 8259 | : E1000_BLK_PHY_RESET; |
| 8260 | } |
Jesse Brandeburg | 96838a4 | 2006-01-18 13:01:39 -0800 | [diff] [blame] | 8261 | |
| 8262 | if (hw->mac_type > e1000_82547_rev_2) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8263 | manc = E1000_READ_REG(hw, MANC); |
| 8264 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? |
Nicholas Nunley | 3557476 | 2006-09-27 12:53:34 -0700 | [diff] [blame] | 8265 | E1000_BLK_PHY_RESET : E1000_SUCCESS; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8266 | } |
| 8267 | |
Adrian Bunk | 3ad2cc6 | 2005-10-30 16:53:34 +0100 | [diff] [blame] | 8268 | static uint8_t |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8269 | e1000_arc_subsystem_valid(struct e1000_hw *hw) |
| 8270 | { |
| 8271 | uint32_t fwsm; |
| 8272 | |
| 8273 | /* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC |
| 8274 | * may not be provided a DMA clock when no manageability features are |
| 8275 | * enabled. We do not want to perform any reads/writes to these registers |
| 8276 | * if this is the case. We read FWSM to determine the manageability mode. |
| 8277 | */ |
| 8278 | switch (hw->mac_type) { |
Mallikarjuna R Chilakala | 868d530 | 2005-10-04 06:58:59 -0400 | [diff] [blame] | 8279 | case e1000_82571: |
| 8280 | case e1000_82572: |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8281 | case e1000_82573: |
Jeff Kirsher | 6418ecc | 2006-03-02 18:21:10 -0800 | [diff] [blame] | 8282 | case e1000_80003es2lan: |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8283 | fwsm = E1000_READ_REG(hw, FWSM); |
Auke Kok | 8fc897b | 2006-08-28 14:56:16 -0700 | [diff] [blame] | 8284 | if ((fwsm & E1000_FWSM_MODE_MASK) != 0) |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8285 | return TRUE; |
| 8286 | break; |
Auke Kok | cd94dd0 | 2006-06-27 09:08:22 -0700 | [diff] [blame] | 8287 | case e1000_ich8lan: |
| 8288 | return TRUE; |
Malli Chilakala | 2d7edb9 | 2005-04-28 19:43:52 -0700 | [diff] [blame] | 8289 | default: |
| 8290 | break; |
| 8291 | } |
| 8292 | return FALSE; |
| 8293 | } |
| 8294 | |
| 8295 | |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8296 | /****************************************************************************** |
| 8297 | * Configure PCI-Ex no-snoop |
| 8298 | * |
| 8299 | * hw - Struct containing variables accessed by shared code. |
| 8300 | * no_snoop - Bitmap of no-snoop events. |
| 8301 | * |
| 8302 | * returns: E1000_SUCCESS |
| 8303 | * |
| 8304 | *****************************************************************************/ |
Adrian Bunk | e4c780b | 2006-08-14 23:00:10 -0700 | [diff] [blame] | 8305 | static int32_t |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8306 | e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop) |
| 8307 | { |
| 8308 | uint32_t gcr_reg = 0; |
| 8309 | |
| 8310 | DEBUGFUNC("e1000_set_pci_ex_no_snoop"); |
| 8311 | |
| 8312 | if (hw->bus_type == e1000_bus_type_unknown) |
| 8313 | e1000_get_bus_info(hw); |
| 8314 | |
| 8315 | if (hw->bus_type != e1000_bus_type_pci_express) |
| 8316 | return E1000_SUCCESS; |
| 8317 | |
| 8318 | if (no_snoop) { |
| 8319 | gcr_reg = E1000_READ_REG(hw, GCR); |
| 8320 | gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL); |
| 8321 | gcr_reg |= no_snoop; |
| 8322 | E1000_WRITE_REG(hw, GCR, gcr_reg); |
| 8323 | } |
| 8324 | if (hw->mac_type == e1000_ich8lan) { |
| 8325 | uint32_t ctrl_ext; |
| 8326 | |
| 8327 | E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL); |
| 8328 | |
| 8329 | ctrl_ext = E1000_READ_REG(hw, CTRL_EXT); |
| 8330 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS; |
| 8331 | E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext); |
| 8332 | } |
| 8333 | |
| 8334 | return E1000_SUCCESS; |
| 8335 | } |
| 8336 | |
| 8337 | /*************************************************************************** |
| 8338 | * |
| 8339 | * Get software semaphore FLAG bit (SWFLAG). |
| 8340 | * SWFLAG is used to synchronize the access to all shared resource between |
| 8341 | * SW, FW and HW. |
| 8342 | * |
| 8343 | * hw: Struct containing variables accessed by shared code |
| 8344 | * |
| 8345 | ***************************************************************************/ |
Adrian Bunk | e4c780b | 2006-08-14 23:00:10 -0700 | [diff] [blame] | 8346 | static int32_t |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8347 | e1000_get_software_flag(struct e1000_hw *hw) |
| 8348 | { |
| 8349 | int32_t timeout = PHY_CFG_TIMEOUT; |
| 8350 | uint32_t extcnf_ctrl; |
| 8351 | |
| 8352 | DEBUGFUNC("e1000_get_software_flag"); |
| 8353 | |
| 8354 | if (hw->mac_type == e1000_ich8lan) { |
| 8355 | while (timeout) { |
| 8356 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); |
| 8357 | extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; |
| 8358 | E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); |
| 8359 | |
| 8360 | extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL); |
| 8361 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) |
| 8362 | break; |
Jeff Garzik | f8ec473 | 2006-09-19 15:27:07 -0400 | [diff] [blame] | 8363 | mdelay(1); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8364 | timeout--; |
| 8365 | } |
| 8366 | |
| 8367 | if (!timeout) { |
| 8368 | DEBUGOUT("FW or HW locks the resource too long.\n"); |
| 8369 | return -E1000_ERR_CONFIG; |
| 8370 | } |
| 8371 | } |
| 8372 | |
| 8373 | return E1000_SUCCESS; |
| 8374 | } |
| 8375 | |
| 8376 | /*************************************************************************** |
| 8377 | * |
| 8378 | * Release software semaphore FLAG bit (SWFLAG). |
| 8379 | * SWFLAG is used to synchronize the access to all shared resource between |
| 8380 | * SW, FW and HW. |
| 8381 | * |
| 8382 | * hw: Struct containing variables accessed by shared code |
| 8383 | * |
| 8384 | ***************************************************************************/ |
Adrian Bunk | e4c780b | 2006-08-14 23:00:10 -0700 | [diff] [blame] | 8385 | static void |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8386 | e1000_release_software_flag(struct e1000_hw *hw) |
| 8387 | { |
| 8388 | uint32_t extcnf_ctrl; |
| 8389 | |
| 8390 | DEBUGFUNC("e1000_release_software_flag"); |
| 8391 | |
| 8392 | if (hw->mac_type == e1000_ich8lan) { |
| 8393 | extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL); |
| 8394 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; |
| 8395 | E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl); |
| 8396 | } |
| 8397 | |
| 8398 | return; |
| 8399 | } |
| 8400 | |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8401 | /****************************************************************************** |
| 8402 | * Reads a 16 bit word or words from the EEPROM using the ICH8's flash access |
| 8403 | * register. |
| 8404 | * |
| 8405 | * hw - Struct containing variables accessed by shared code |
| 8406 | * offset - offset of word in the EEPROM to read |
| 8407 | * data - word read from the EEPROM |
| 8408 | * words - number of words to read |
| 8409 | *****************************************************************************/ |
Adrian Bunk | e4c780b | 2006-08-14 23:00:10 -0700 | [diff] [blame] | 8410 | static int32_t |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8411 | e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, |
| 8412 | uint16_t *data) |
| 8413 | { |
| 8414 | int32_t error = E1000_SUCCESS; |
| 8415 | uint32_t flash_bank = 0; |
| 8416 | uint32_t act_offset = 0; |
| 8417 | uint32_t bank_offset = 0; |
| 8418 | uint16_t word = 0; |
| 8419 | uint16_t i = 0; |
| 8420 | |
| 8421 | /* We need to know which is the valid flash bank. In the event |
| 8422 | * that we didn't allocate eeprom_shadow_ram, we may not be |
| 8423 | * managing flash_bank. So it cannot be trusted and needs |
| 8424 | * to be updated with each read. |
| 8425 | */ |
| 8426 | /* Value of bit 22 corresponds to the flash bank we're on. */ |
| 8427 | flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0; |
| 8428 | |
| 8429 | /* Adjust offset appropriately if we're on bank 1 - adjust for word size */ |
| 8430 | bank_offset = flash_bank * (hw->flash_bank_size * 2); |
| 8431 | |
| 8432 | error = e1000_get_software_flag(hw); |
| 8433 | if (error != E1000_SUCCESS) |
| 8434 | return error; |
| 8435 | |
| 8436 | for (i = 0; i < words; i++) { |
| 8437 | if (hw->eeprom_shadow_ram != NULL && |
| 8438 | hw->eeprom_shadow_ram[offset+i].modified == TRUE) { |
| 8439 | data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word; |
| 8440 | } else { |
| 8441 | /* The NVM part needs a byte offset, hence * 2 */ |
| 8442 | act_offset = bank_offset + ((offset + i) * 2); |
| 8443 | error = e1000_read_ich8_word(hw, act_offset, &word); |
| 8444 | if (error != E1000_SUCCESS) |
| 8445 | break; |
| 8446 | data[i] = word; |
| 8447 | } |
| 8448 | } |
| 8449 | |
| 8450 | e1000_release_software_flag(hw); |
| 8451 | |
| 8452 | return error; |
| 8453 | } |
| 8454 | |
| 8455 | /****************************************************************************** |
| 8456 | * Writes a 16 bit word or words to the EEPROM using the ICH8's flash access |
| 8457 | * register. Actually, writes are written to the shadow ram cache in the hw |
| 8458 | * structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to |
| 8459 | * the NVM, which occurs when the NVM checksum is updated. |
| 8460 | * |
| 8461 | * hw - Struct containing variables accessed by shared code |
| 8462 | * offset - offset of word in the EEPROM to write |
| 8463 | * words - number of words to write |
| 8464 | * data - words to write to the EEPROM |
| 8465 | *****************************************************************************/ |
Adrian Bunk | e4c780b | 2006-08-14 23:00:10 -0700 | [diff] [blame] | 8466 | static int32_t |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8467 | e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words, |
| 8468 | uint16_t *data) |
| 8469 | { |
| 8470 | uint32_t i = 0; |
| 8471 | int32_t error = E1000_SUCCESS; |
| 8472 | |
| 8473 | error = e1000_get_software_flag(hw); |
| 8474 | if (error != E1000_SUCCESS) |
| 8475 | return error; |
| 8476 | |
| 8477 | /* A driver can write to the NVM only if it has eeprom_shadow_ram |
| 8478 | * allocated. Subsequent reads to the modified words are read from |
| 8479 | * this cached structure as well. Writes will only go into this |
| 8480 | * cached structure unless it's followed by a call to |
| 8481 | * e1000_update_eeprom_checksum() where it will commit the changes |
| 8482 | * and clear the "modified" field. |
| 8483 | */ |
| 8484 | if (hw->eeprom_shadow_ram != NULL) { |
| 8485 | for (i = 0; i < words; i++) { |
| 8486 | if ((offset + i) < E1000_SHADOW_RAM_WORDS) { |
| 8487 | hw->eeprom_shadow_ram[offset+i].modified = TRUE; |
| 8488 | hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i]; |
| 8489 | } else { |
| 8490 | error = -E1000_ERR_EEPROM; |
| 8491 | break; |
| 8492 | } |
| 8493 | } |
| 8494 | } else { |
| 8495 | /* Drivers have the option to not allocate eeprom_shadow_ram as long |
| 8496 | * as they don't perform any NVM writes. An attempt in doing so |
| 8497 | * will result in this error. |
| 8498 | */ |
| 8499 | error = -E1000_ERR_EEPROM; |
| 8500 | } |
| 8501 | |
| 8502 | e1000_release_software_flag(hw); |
| 8503 | |
| 8504 | return error; |
| 8505 | } |
| 8506 | |
| 8507 | /****************************************************************************** |
| 8508 | * This function does initial flash setup so that a new read/write/erase cycle |
| 8509 | * can be started. |
| 8510 | * |
| 8511 | * hw - The pointer to the hw structure |
| 8512 | ****************************************************************************/ |
Adrian Bunk | e4c780b | 2006-08-14 23:00:10 -0700 | [diff] [blame] | 8513 | static int32_t |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8514 | e1000_ich8_cycle_init(struct e1000_hw *hw) |
| 8515 | { |
| 8516 | union ich8_hws_flash_status hsfsts; |
| 8517 | int32_t error = E1000_ERR_EEPROM; |
| 8518 | int32_t i = 0; |
| 8519 | |
| 8520 | DEBUGFUNC("e1000_ich8_cycle_init"); |
| 8521 | |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8522 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8523 | |
| 8524 | /* May be check the Flash Des Valid bit in Hw status */ |
| 8525 | if (hsfsts.hsf_status.fldesvalid == 0) { |
| 8526 | DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used."); |
| 8527 | return error; |
| 8528 | } |
| 8529 | |
| 8530 | /* Clear FCERR in Hw status by writing 1 */ |
| 8531 | /* Clear DAEL in Hw status by writing a 1 */ |
| 8532 | hsfsts.hsf_status.flcerr = 1; |
| 8533 | hsfsts.hsf_status.dael = 1; |
| 8534 | |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8535 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8536 | |
| 8537 | /* Either we should have a hardware SPI cycle in progress bit to check |
| 8538 | * against, in order to start a new cycle or FDONE bit should be changed |
| 8539 | * in the hardware so that it is 1 after harware reset, which can then be |
| 8540 | * used as an indication whether a cycle is in progress or has been |
| 8541 | * completed .. we should also have some software semaphore mechanism to |
| 8542 | * guard FDONE or the cycle in progress bit so that two threads access to |
| 8543 | * those bits can be sequentiallized or a way so that 2 threads dont |
| 8544 | * start the cycle at the same time */ |
| 8545 | |
| 8546 | if (hsfsts.hsf_status.flcinprog == 0) { |
| 8547 | /* There is no cycle running at present, so we can start a cycle */ |
| 8548 | /* Begin by setting Flash Cycle Done. */ |
| 8549 | hsfsts.hsf_status.flcdone = 1; |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8550 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8551 | error = E1000_SUCCESS; |
| 8552 | } else { |
| 8553 | /* otherwise poll for sometime so the current cycle has a chance |
| 8554 | * to end before giving up. */ |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8555 | for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) { |
| 8556 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8557 | if (hsfsts.hsf_status.flcinprog == 0) { |
| 8558 | error = E1000_SUCCESS; |
| 8559 | break; |
| 8560 | } |
| 8561 | udelay(1); |
| 8562 | } |
| 8563 | if (error == E1000_SUCCESS) { |
| 8564 | /* Successful in waiting for previous cycle to timeout, |
| 8565 | * now set the Flash Cycle Done. */ |
| 8566 | hsfsts.hsf_status.flcdone = 1; |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8567 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8568 | } else { |
| 8569 | DEBUGOUT("Flash controller busy, cannot get access"); |
| 8570 | } |
| 8571 | } |
| 8572 | return error; |
| 8573 | } |
| 8574 | |
| 8575 | /****************************************************************************** |
| 8576 | * This function starts a flash cycle and waits for its completion |
| 8577 | * |
| 8578 | * hw - The pointer to the hw structure |
| 8579 | ****************************************************************************/ |
Adrian Bunk | e4c780b | 2006-08-14 23:00:10 -0700 | [diff] [blame] | 8580 | static int32_t |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8581 | e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout) |
| 8582 | { |
| 8583 | union ich8_hws_flash_ctrl hsflctl; |
| 8584 | union ich8_hws_flash_status hsfsts; |
| 8585 | int32_t error = E1000_ERR_EEPROM; |
| 8586 | uint32_t i = 0; |
| 8587 | |
| 8588 | /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8589 | hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8590 | hsflctl.hsf_ctrl.flcgo = 1; |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8591 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8592 | |
| 8593 | /* wait till FDONE bit is set to 1 */ |
| 8594 | do { |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8595 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8596 | if (hsfsts.hsf_status.flcdone == 1) |
| 8597 | break; |
| 8598 | udelay(1); |
| 8599 | i++; |
| 8600 | } while (i < timeout); |
| 8601 | if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) { |
| 8602 | error = E1000_SUCCESS; |
| 8603 | } |
| 8604 | return error; |
| 8605 | } |
| 8606 | |
| 8607 | /****************************************************************************** |
| 8608 | * Reads a byte or word from the NVM using the ICH8 flash access registers. |
| 8609 | * |
| 8610 | * hw - The pointer to the hw structure |
| 8611 | * index - The index of the byte or word to read. |
| 8612 | * size - Size of data to read, 1=byte 2=word |
| 8613 | * data - Pointer to the word to store the value read. |
| 8614 | *****************************************************************************/ |
Adrian Bunk | e4c780b | 2006-08-14 23:00:10 -0700 | [diff] [blame] | 8615 | static int32_t |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8616 | e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index, |
| 8617 | uint32_t size, uint16_t* data) |
| 8618 | { |
| 8619 | union ich8_hws_flash_status hsfsts; |
| 8620 | union ich8_hws_flash_ctrl hsflctl; |
| 8621 | uint32_t flash_linear_address; |
| 8622 | uint32_t flash_data = 0; |
| 8623 | int32_t error = -E1000_ERR_EEPROM; |
| 8624 | int32_t count = 0; |
| 8625 | |
| 8626 | DEBUGFUNC("e1000_read_ich8_data"); |
| 8627 | |
| 8628 | if (size < 1 || size > 2 || data == 0x0 || |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8629 | index > ICH_FLASH_LINEAR_ADDR_MASK) |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8630 | return error; |
| 8631 | |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8632 | flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8633 | hw->flash_base_addr; |
| 8634 | |
| 8635 | do { |
| 8636 | udelay(1); |
| 8637 | /* Steps */ |
| 8638 | error = e1000_ich8_cycle_init(hw); |
| 8639 | if (error != E1000_SUCCESS) |
| 8640 | break; |
| 8641 | |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8642 | hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8643 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ |
| 8644 | hsflctl.hsf_ctrl.fldbcount = size - 1; |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8645 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; |
| 8646 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8647 | |
| 8648 | /* Write the last 24 bits of index into Flash Linear address field in |
| 8649 | * Flash Address */ |
| 8650 | /* TODO: TBD maybe check the index against the size of flash */ |
| 8651 | |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8652 | E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8653 | |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8654 | error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8655 | |
| 8656 | /* Check if FCERR is set to 1, if set to 1, clear it and try the whole |
| 8657 | * sequence a few more times, else read in (shift in) the Flash Data0, |
| 8658 | * the order is least significant byte first msb to lsb */ |
| 8659 | if (error == E1000_SUCCESS) { |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8660 | flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8661 | if (size == 1) { |
| 8662 | *data = (uint8_t)(flash_data & 0x000000FF); |
| 8663 | } else if (size == 2) { |
| 8664 | *data = (uint16_t)(flash_data & 0x0000FFFF); |
| 8665 | } |
| 8666 | break; |
| 8667 | } else { |
| 8668 | /* If we've gotten here, then things are probably completely hosed, |
| 8669 | * but if the error condition is detected, it won't hurt to give |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8670 | * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times. |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8671 | */ |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8672 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8673 | if (hsfsts.hsf_status.flcerr == 1) { |
| 8674 | /* Repeat for some time before giving up. */ |
| 8675 | continue; |
| 8676 | } else if (hsfsts.hsf_status.flcdone == 0) { |
| 8677 | DEBUGOUT("Timeout error - flash cycle did not complete."); |
| 8678 | break; |
| 8679 | } |
| 8680 | } |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8681 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8682 | |
| 8683 | return error; |
| 8684 | } |
| 8685 | |
| 8686 | /****************************************************************************** |
| 8687 | * Writes One /two bytes to the NVM using the ICH8 flash access registers. |
| 8688 | * |
| 8689 | * hw - The pointer to the hw structure |
| 8690 | * index - The index of the byte/word to read. |
| 8691 | * size - Size of data to read, 1=byte 2=word |
| 8692 | * data - The byte(s) to write to the NVM. |
| 8693 | *****************************************************************************/ |
Adrian Bunk | e4c780b | 2006-08-14 23:00:10 -0700 | [diff] [blame] | 8694 | static int32_t |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8695 | e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, |
| 8696 | uint16_t data) |
| 8697 | { |
| 8698 | union ich8_hws_flash_status hsfsts; |
| 8699 | union ich8_hws_flash_ctrl hsflctl; |
| 8700 | uint32_t flash_linear_address; |
| 8701 | uint32_t flash_data = 0; |
| 8702 | int32_t error = -E1000_ERR_EEPROM; |
| 8703 | int32_t count = 0; |
| 8704 | |
| 8705 | DEBUGFUNC("e1000_write_ich8_data"); |
| 8706 | |
| 8707 | if (size < 1 || size > 2 || data > size * 0xff || |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8708 | index > ICH_FLASH_LINEAR_ADDR_MASK) |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8709 | return error; |
| 8710 | |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8711 | flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) + |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8712 | hw->flash_base_addr; |
| 8713 | |
| 8714 | do { |
| 8715 | udelay(1); |
| 8716 | /* Steps */ |
| 8717 | error = e1000_ich8_cycle_init(hw); |
| 8718 | if (error != E1000_SUCCESS) |
| 8719 | break; |
| 8720 | |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8721 | hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8722 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ |
| 8723 | hsflctl.hsf_ctrl.fldbcount = size -1; |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8724 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; |
| 8725 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8726 | |
| 8727 | /* Write the last 24 bits of index into Flash Linear address field in |
| 8728 | * Flash Address */ |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8729 | E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8730 | |
| 8731 | if (size == 1) |
| 8732 | flash_data = (uint32_t)data & 0x00FF; |
| 8733 | else |
| 8734 | flash_data = (uint32_t)data; |
| 8735 | |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8736 | E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8737 | |
| 8738 | /* check if FCERR is set to 1 , if set to 1, clear it and try the whole |
| 8739 | * sequence a few more times else done */ |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8740 | error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8741 | if (error == E1000_SUCCESS) { |
| 8742 | break; |
| 8743 | } else { |
| 8744 | /* If we're here, then things are most likely completely hosed, |
| 8745 | * but if the error condition is detected, it won't hurt to give |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8746 | * it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times. |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8747 | */ |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8748 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8749 | if (hsfsts.hsf_status.flcerr == 1) { |
| 8750 | /* Repeat for some time before giving up. */ |
| 8751 | continue; |
| 8752 | } else if (hsfsts.hsf_status.flcdone == 0) { |
| 8753 | DEBUGOUT("Timeout error - flash cycle did not complete."); |
| 8754 | break; |
| 8755 | } |
| 8756 | } |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8757 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8758 | |
| 8759 | return error; |
| 8760 | } |
| 8761 | |
| 8762 | /****************************************************************************** |
| 8763 | * Reads a single byte from the NVM using the ICH8 flash access registers. |
| 8764 | * |
| 8765 | * hw - pointer to e1000_hw structure |
| 8766 | * index - The index of the byte to read. |
| 8767 | * data - Pointer to a byte to store the value read. |
| 8768 | *****************************************************************************/ |
Adrian Bunk | e4c780b | 2006-08-14 23:00:10 -0700 | [diff] [blame] | 8769 | static int32_t |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8770 | e1000_read_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t* data) |
| 8771 | { |
| 8772 | int32_t status = E1000_SUCCESS; |
| 8773 | uint16_t word = 0; |
| 8774 | |
| 8775 | status = e1000_read_ich8_data(hw, index, 1, &word); |
| 8776 | if (status == E1000_SUCCESS) { |
| 8777 | *data = (uint8_t)word; |
| 8778 | } |
| 8779 | |
| 8780 | return status; |
| 8781 | } |
| 8782 | |
| 8783 | /****************************************************************************** |
| 8784 | * Writes a single byte to the NVM using the ICH8 flash access registers. |
| 8785 | * Performs verification by reading back the value and then going through |
| 8786 | * a retry algorithm before giving up. |
| 8787 | * |
| 8788 | * hw - pointer to e1000_hw structure |
| 8789 | * index - The index of the byte to write. |
| 8790 | * byte - The byte to write to the NVM. |
| 8791 | *****************************************************************************/ |
Adrian Bunk | e4c780b | 2006-08-14 23:00:10 -0700 | [diff] [blame] | 8792 | static int32_t |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8793 | e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte) |
| 8794 | { |
| 8795 | int32_t error = E1000_SUCCESS; |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 8796 | int32_t program_retries = 0; |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8797 | |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 8798 | DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8799 | |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 8800 | error = e1000_write_ich8_byte(hw, index, byte); |
| 8801 | |
| 8802 | if (error != E1000_SUCCESS) { |
| 8803 | for (program_retries = 0; program_retries < 100; program_retries++) { |
| 8804 | DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index); |
| 8805 | error = e1000_write_ich8_byte(hw, index, byte); |
| 8806 | udelay(100); |
| 8807 | if (error == E1000_SUCCESS) |
| 8808 | break; |
| 8809 | } |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8810 | } |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 8811 | |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8812 | if (program_retries == 100) |
| 8813 | error = E1000_ERR_EEPROM; |
| 8814 | |
| 8815 | return error; |
| 8816 | } |
| 8817 | |
| 8818 | /****************************************************************************** |
| 8819 | * Writes a single byte to the NVM using the ICH8 flash access registers. |
| 8820 | * |
| 8821 | * hw - pointer to e1000_hw structure |
| 8822 | * index - The index of the byte to read. |
| 8823 | * data - The byte to write to the NVM. |
| 8824 | *****************************************************************************/ |
Adrian Bunk | e4c780b | 2006-08-14 23:00:10 -0700 | [diff] [blame] | 8825 | static int32_t |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8826 | e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data) |
| 8827 | { |
| 8828 | int32_t status = E1000_SUCCESS; |
| 8829 | uint16_t word = (uint16_t)data; |
| 8830 | |
| 8831 | status = e1000_write_ich8_data(hw, index, 1, word); |
| 8832 | |
| 8833 | return status; |
| 8834 | } |
| 8835 | |
| 8836 | /****************************************************************************** |
| 8837 | * Reads a word from the NVM using the ICH8 flash access registers. |
| 8838 | * |
| 8839 | * hw - pointer to e1000_hw structure |
| 8840 | * index - The starting byte index of the word to read. |
| 8841 | * data - Pointer to a word to store the value read. |
| 8842 | *****************************************************************************/ |
Adrian Bunk | e4c780b | 2006-08-14 23:00:10 -0700 | [diff] [blame] | 8843 | static int32_t |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8844 | e1000_read_ich8_word(struct e1000_hw *hw, uint32_t index, uint16_t *data) |
| 8845 | { |
| 8846 | int32_t status = E1000_SUCCESS; |
| 8847 | status = e1000_read_ich8_data(hw, index, 2, data); |
| 8848 | return status; |
| 8849 | } |
| 8850 | |
| 8851 | /****************************************************************************** |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 8852 | * Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0 |
| 8853 | * based. |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8854 | * |
| 8855 | * hw - pointer to e1000_hw structure |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 8856 | * bank - 0 for first bank, 1 for second bank |
| 8857 | * |
| 8858 | * Note that this function may actually erase as much as 8 or 64 KBytes. The |
| 8859 | * amount of NVM used in each bank is a *minimum* of 4 KBytes, but in fact the |
| 8860 | * bank size may be 4, 8 or 64 KBytes |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8861 | *****************************************************************************/ |
| 8862 | int32_t |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 8863 | e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank) |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8864 | { |
| 8865 | union ich8_hws_flash_status hsfsts; |
| 8866 | union ich8_hws_flash_ctrl hsflctl; |
| 8867 | uint32_t flash_linear_address; |
| 8868 | int32_t count = 0; |
| 8869 | int32_t error = E1000_ERR_EEPROM; |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 8870 | int32_t iteration; |
| 8871 | int32_t sub_sector_size = 0; |
| 8872 | int32_t bank_size; |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8873 | int32_t j = 0; |
| 8874 | int32_t error_flag = 0; |
| 8875 | |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8876 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8877 | |
| 8878 | /* Determine HW Sector size: Read BERASE bits of Hw flash Status register */ |
| 8879 | /* 00: The Hw sector is 256 bytes, hence we need to erase 16 |
| 8880 | * consecutive sectors. The start index for the nth Hw sector can be |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 8881 | * calculated as bank * 4096 + n * 256 |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8882 | * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. |
| 8883 | * The start index for the nth Hw sector can be calculated |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 8884 | * as bank * 4096 |
| 8885 | * 10: The HW sector is 8K bytes |
| 8886 | * 11: The Hw sector size is 64K bytes */ |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8887 | if (hsfsts.hsf_status.berasesz == 0x0) { |
| 8888 | /* Hw sector size 256 */ |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8889 | sub_sector_size = ICH_FLASH_SEG_SIZE_256; |
| 8890 | bank_size = ICH_FLASH_SECTOR_SIZE; |
| 8891 | iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256; |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8892 | } else if (hsfsts.hsf_status.berasesz == 0x1) { |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8893 | bank_size = ICH_FLASH_SEG_SIZE_4K; |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8894 | iteration = 1; |
| 8895 | } else if (hsfsts.hsf_status.berasesz == 0x3) { |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8896 | bank_size = ICH_FLASH_SEG_SIZE_64K; |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8897 | iteration = 1; |
| 8898 | } else { |
| 8899 | return error; |
| 8900 | } |
| 8901 | |
| 8902 | for (j = 0; j < iteration ; j++) { |
| 8903 | do { |
| 8904 | count++; |
| 8905 | /* Steps */ |
| 8906 | error = e1000_ich8_cycle_init(hw); |
| 8907 | if (error != E1000_SUCCESS) { |
| 8908 | error_flag = 1; |
| 8909 | break; |
| 8910 | } |
| 8911 | |
| 8912 | /* Write a value 11 (block Erase) in Flash Cycle field in Hw flash |
| 8913 | * Control */ |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8914 | hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL); |
| 8915 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; |
| 8916 | E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8917 | |
| 8918 | /* Write the last 24 bits of an index within the block into Flash |
| 8919 | * Linear address field in Flash Address. This probably needs to |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 8920 | * be calculated here based off the on-chip erase sector size and |
| 8921 | * the software bank size (4, 8 or 64 KBytes) */ |
| 8922 | flash_linear_address = bank * bank_size + j * sub_sector_size; |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8923 | flash_linear_address += hw->flash_base_addr; |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8924 | flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK; |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8925 | |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8926 | E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8927 | |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8928 | error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8929 | /* Check if FCERR is set to 1. If 1, clear it and try the whole |
| 8930 | * sequence a few more times else Done */ |
| 8931 | if (error == E1000_SUCCESS) { |
| 8932 | break; |
| 8933 | } else { |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8934 | hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8935 | if (hsfsts.hsf_status.flcerr == 1) { |
| 8936 | /* repeat for some time before giving up */ |
| 8937 | continue; |
| 8938 | } else if (hsfsts.hsf_status.flcdone == 0) { |
| 8939 | error_flag = 1; |
| 8940 | break; |
| 8941 | } |
| 8942 | } |
Jeff Kirsher | 2df7d59 | 2006-11-01 08:48:02 -0800 | [diff] [blame] | 8943 | } while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag); |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8944 | if (error_flag == 1) |
| 8945 | break; |
| 8946 | } |
| 8947 | if (error_flag != 1) |
| 8948 | error = E1000_SUCCESS; |
| 8949 | return error; |
| 8950 | } |
| 8951 | |
Adrian Bunk | e4c780b | 2006-08-14 23:00:10 -0700 | [diff] [blame] | 8952 | static int32_t |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8953 | e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, |
| 8954 | uint32_t cnf_base_addr, uint32_t cnf_size) |
| 8955 | { |
| 8956 | uint32_t ret_val = E1000_SUCCESS; |
| 8957 | uint16_t word_addr, reg_data, reg_addr; |
| 8958 | uint16_t i; |
| 8959 | |
| 8960 | /* cnf_base_addr is in DWORD */ |
| 8961 | word_addr = (uint16_t)(cnf_base_addr << 1); |
| 8962 | |
| 8963 | /* cnf_size is returned in size of dwords */ |
| 8964 | for (i = 0; i < cnf_size; i++) { |
| 8965 | ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, ®_data); |
| 8966 | if (ret_val) |
| 8967 | return ret_val; |
| 8968 | |
| 8969 | ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, ®_addr); |
| 8970 | if (ret_val) |
| 8971 | return ret_val; |
| 8972 | |
| 8973 | ret_val = e1000_get_software_flag(hw); |
| 8974 | if (ret_val != E1000_SUCCESS) |
| 8975 | return ret_val; |
| 8976 | |
| 8977 | ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data); |
| 8978 | |
| 8979 | e1000_release_software_flag(hw); |
| 8980 | } |
| 8981 | |
| 8982 | return ret_val; |
| 8983 | } |
| 8984 | |
| 8985 | |
Jeff Kirsher | 2a88c17 | 2006-09-27 12:54:05 -0700 | [diff] [blame] | 8986 | /****************************************************************************** |
| 8987 | * This function initializes the PHY from the NVM on ICH8 platforms. This |
| 8988 | * is needed due to an issue where the NVM configuration is not properly |
| 8989 | * autoloaded after power transitions. Therefore, after each PHY reset, we |
| 8990 | * will load the configuration data out of the NVM manually. |
| 8991 | * |
| 8992 | * hw: Struct containing variables accessed by shared code |
| 8993 | *****************************************************************************/ |
Adrian Bunk | e4c780b | 2006-08-14 23:00:10 -0700 | [diff] [blame] | 8994 | static int32_t |
Auke Kok | d37ea5d | 2006-06-27 09:08:17 -0700 | [diff] [blame] | 8995 | e1000_init_lcd_from_nvm(struct e1000_hw *hw) |
| 8996 | { |
| 8997 | uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop; |
| 8998 | |
| 8999 | if (hw->phy_type != e1000_phy_igp_3) |
| 9000 | return E1000_SUCCESS; |
| 9001 | |
| 9002 | /* Check if SW needs configure the PHY */ |
| 9003 | reg_data = E1000_READ_REG(hw, FEXTNVM); |
| 9004 | if (!(reg_data & FEXTNVM_SW_CONFIG)) |
| 9005 | return E1000_SUCCESS; |
| 9006 | |
| 9007 | /* Wait for basic configuration completes before proceeding*/ |
| 9008 | loop = 0; |
| 9009 | do { |
| 9010 | reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE; |
| 9011 | udelay(100); |
| 9012 | loop++; |
| 9013 | } while ((!reg_data) && (loop < 50)); |
| 9014 | |
| 9015 | /* Clear the Init Done bit for the next init event */ |
| 9016 | reg_data = E1000_READ_REG(hw, STATUS); |
| 9017 | reg_data &= ~E1000_STATUS_LAN_INIT_DONE; |
| 9018 | E1000_WRITE_REG(hw, STATUS, reg_data); |
| 9019 | |
| 9020 | /* Make sure HW does not configure LCD from PHY extended configuration |
| 9021 | before SW configuration */ |
| 9022 | reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); |
| 9023 | if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) { |
| 9024 | reg_data = E1000_READ_REG(hw, EXTCNF_SIZE); |
| 9025 | cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH; |
| 9026 | cnf_size >>= 16; |
| 9027 | if (cnf_size) { |
| 9028 | reg_data = E1000_READ_REG(hw, EXTCNF_CTRL); |
| 9029 | cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER; |
| 9030 | /* cnf_base_addr is in DWORD */ |
| 9031 | cnf_base_addr >>= 16; |
| 9032 | |
| 9033 | /* Configure LCD from extended configuration region. */ |
| 9034 | ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr, |
| 9035 | cnf_size); |
| 9036 | if (ret_val) |
| 9037 | return ret_val; |
| 9038 | } |
| 9039 | } |
| 9040 | |
| 9041 | return E1000_SUCCESS; |
| 9042 | } |
| 9043 | |