Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Emilio López |
| 3 | * |
| 4 | * Emilio López <emilio@elopez.com.ar> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/clk-provider.h> |
| 18 | #include <linux/clkdev.h> |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 19 | #include <linux/of.h> |
| 20 | #include <linux/of_address.h> |
Hans de Goede | cfb0086 | 2014-02-07 16:21:49 +0100 | [diff] [blame^] | 21 | #include <linux/reset-controller.h> |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 22 | |
| 23 | #include "clk-factors.h" |
| 24 | |
| 25 | static DEFINE_SPINLOCK(clk_lock); |
| 26 | |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 27 | /* Maximum number of parents our clocks have */ |
| 28 | #define SUNXI_MAX_PARENTS 5 |
| 29 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 30 | /** |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 31 | * sun4i_osc_clk_setup() - Setup function for gatable oscillator |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 32 | */ |
| 33 | |
| 34 | #define SUNXI_OSC24M_GATE 0 |
| 35 | |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 36 | static void __init sun4i_osc_clk_setup(struct device_node *node) |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 37 | { |
| 38 | struct clk *clk; |
Emilio López | 38e4aa0 | 2013-04-10 15:02:57 -0700 | [diff] [blame] | 39 | struct clk_fixed_rate *fixed; |
| 40 | struct clk_gate *gate; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 41 | const char *clk_name = node->name; |
Emilio López | 38e4aa0 | 2013-04-10 15:02:57 -0700 | [diff] [blame] | 42 | u32 rate; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 43 | |
Victor N. Ramos Mello | e71c69f | 2013-10-18 20:27:51 -0300 | [diff] [blame] | 44 | if (of_property_read_u32(node, "clock-frequency", &rate)) |
| 45 | return; |
| 46 | |
Emilio López | 38e4aa0 | 2013-04-10 15:02:57 -0700 | [diff] [blame] | 47 | /* allocate fixed-rate and gate clock structs */ |
| 48 | fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL); |
| 49 | if (!fixed) |
| 50 | return; |
| 51 | gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); |
Victor N. Ramos Mello | e71c69f | 2013-10-18 20:27:51 -0300 | [diff] [blame] | 52 | if (!gate) |
| 53 | goto err_free_fixed; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 54 | |
Chen-Yu Tsai | f64111e | 2014-02-03 09:51:37 +0800 | [diff] [blame] | 55 | of_property_read_string(node, "clock-output-names", &clk_name); |
| 56 | |
Emilio López | 38e4aa0 | 2013-04-10 15:02:57 -0700 | [diff] [blame] | 57 | /* set up gate and fixed rate properties */ |
| 58 | gate->reg = of_iomap(node, 0); |
| 59 | gate->bit_idx = SUNXI_OSC24M_GATE; |
| 60 | gate->lock = &clk_lock; |
| 61 | fixed->fixed_rate = rate; |
| 62 | |
| 63 | clk = clk_register_composite(NULL, clk_name, |
| 64 | NULL, 0, |
| 65 | NULL, NULL, |
| 66 | &fixed->hw, &clk_fixed_rate_ops, |
| 67 | &gate->hw, &clk_gate_ops, |
| 68 | CLK_IS_ROOT); |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 69 | |
Victor N. Ramos Mello | e71c69f | 2013-10-18 20:27:51 -0300 | [diff] [blame] | 70 | if (IS_ERR(clk)) |
| 71 | goto err_free_gate; |
| 72 | |
| 73 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 74 | clk_register_clkdev(clk, clk_name, NULL); |
| 75 | |
| 76 | return; |
| 77 | |
| 78 | err_free_gate: |
| 79 | kfree(gate); |
| 80 | err_free_fixed: |
| 81 | kfree(fixed); |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 82 | } |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 83 | CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-osc-clk", sun4i_osc_clk_setup); |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 84 | |
| 85 | |
| 86 | |
| 87 | /** |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 88 | * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1 |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 89 | * PLL1 rate is calculated as follows |
| 90 | * rate = (parent_rate * n * (k + 1) >> p) / (m + 1); |
| 91 | * parent_rate is always 24Mhz |
| 92 | */ |
| 93 | |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 94 | static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 95 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 96 | { |
| 97 | u8 div; |
| 98 | |
| 99 | /* Normalize value to a 6M multiple */ |
| 100 | div = *freq / 6000000; |
| 101 | *freq = 6000000 * div; |
| 102 | |
| 103 | /* we were called to round the frequency, we can now return */ |
| 104 | if (n == NULL) |
| 105 | return; |
| 106 | |
| 107 | /* m is always zero for pll1 */ |
| 108 | *m = 0; |
| 109 | |
| 110 | /* k is 1 only on these cases */ |
| 111 | if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000) |
| 112 | *k = 1; |
| 113 | else |
| 114 | *k = 0; |
| 115 | |
| 116 | /* p will be 3 for divs under 10 */ |
| 117 | if (div < 10) |
| 118 | *p = 3; |
| 119 | |
| 120 | /* p will be 2 for divs between 10 - 20 and odd divs under 32 */ |
| 121 | else if (div < 20 || (div < 32 && (div & 1))) |
| 122 | *p = 2; |
| 123 | |
| 124 | /* p will be 1 for even divs under 32, divs under 40 and odd pairs |
| 125 | * of divs between 40-62 */ |
| 126 | else if (div < 40 || (div < 64 && (div & 2))) |
| 127 | *p = 1; |
| 128 | |
| 129 | /* any other entries have p = 0 */ |
| 130 | else |
| 131 | *p = 0; |
| 132 | |
| 133 | /* calculate a suitable n based on k and p */ |
| 134 | div <<= *p; |
| 135 | div /= (*k + 1); |
| 136 | *n = div / 4; |
| 137 | } |
| 138 | |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 139 | /** |
| 140 | * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1 |
| 141 | * PLL1 rate is calculated as follows |
| 142 | * rate = parent_rate * (n + 1) * (k + 1) / (m + 1); |
| 143 | * parent_rate should always be 24MHz |
| 144 | */ |
| 145 | static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate, |
| 146 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 147 | { |
| 148 | /* |
| 149 | * We can operate only on MHz, this will make our life easier |
| 150 | * later. |
| 151 | */ |
| 152 | u32 freq_mhz = *freq / 1000000; |
| 153 | u32 parent_freq_mhz = parent_rate / 1000000; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 154 | |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 155 | /* |
| 156 | * Round down the frequency to the closest multiple of either |
| 157 | * 6 or 16 |
| 158 | */ |
| 159 | u32 round_freq_6 = round_down(freq_mhz, 6); |
| 160 | u32 round_freq_16 = round_down(freq_mhz, 16); |
| 161 | |
| 162 | if (round_freq_6 > round_freq_16) |
| 163 | freq_mhz = round_freq_6; |
| 164 | else |
| 165 | freq_mhz = round_freq_16; |
| 166 | |
| 167 | *freq = freq_mhz * 1000000; |
| 168 | |
| 169 | /* |
| 170 | * If the factors pointer are null, we were just called to |
| 171 | * round down the frequency. |
| 172 | * Exit. |
| 173 | */ |
| 174 | if (n == NULL) |
| 175 | return; |
| 176 | |
| 177 | /* If the frequency is a multiple of 32 MHz, k is always 3 */ |
| 178 | if (!(freq_mhz % 32)) |
| 179 | *k = 3; |
| 180 | /* If the frequency is a multiple of 9 MHz, k is always 2 */ |
| 181 | else if (!(freq_mhz % 9)) |
| 182 | *k = 2; |
| 183 | /* If the frequency is a multiple of 8 MHz, k is always 1 */ |
| 184 | else if (!(freq_mhz % 8)) |
| 185 | *k = 1; |
| 186 | /* Otherwise, we don't use the k factor */ |
| 187 | else |
| 188 | *k = 0; |
| 189 | |
| 190 | /* |
| 191 | * If the frequency is a multiple of 2 but not a multiple of |
| 192 | * 3, m is 3. This is the first time we use 6 here, yet we |
| 193 | * will use it on several other places. |
| 194 | * We use this number because it's the lowest frequency we can |
| 195 | * generate (with n = 0, k = 0, m = 3), so every other frequency |
| 196 | * somehow relates to this frequency. |
| 197 | */ |
| 198 | if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4) |
| 199 | *m = 2; |
| 200 | /* |
| 201 | * If the frequency is a multiple of 6MHz, but the factor is |
| 202 | * odd, m will be 3 |
| 203 | */ |
| 204 | else if ((freq_mhz / 6) & 1) |
| 205 | *m = 3; |
| 206 | /* Otherwise, we end up with m = 1 */ |
| 207 | else |
| 208 | *m = 1; |
| 209 | |
| 210 | /* Calculate n thanks to the above factors we already got */ |
| 211 | *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1; |
| 212 | |
| 213 | /* |
| 214 | * If n end up being outbound, and that we can still decrease |
| 215 | * m, do it. |
| 216 | */ |
| 217 | if ((*n + 1) > 31 && (*m + 1) > 1) { |
| 218 | *n = (*n + 1) / 2 - 1; |
| 219 | *m = (*m + 1) / 2 - 1; |
| 220 | } |
| 221 | } |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 222 | |
| 223 | /** |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 224 | * sun4i_get_pll5_factors() - calculates n, k factors for PLL5 |
| 225 | * PLL5 rate is calculated as follows |
| 226 | * rate = parent_rate * n * (k + 1) |
| 227 | * parent_rate is always 24Mhz |
| 228 | */ |
| 229 | |
| 230 | static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate, |
| 231 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 232 | { |
| 233 | u8 div; |
| 234 | |
| 235 | /* Normalize value to a parent_rate multiple (24M) */ |
| 236 | div = *freq / parent_rate; |
| 237 | *freq = parent_rate * div; |
| 238 | |
| 239 | /* we were called to round the frequency, we can now return */ |
| 240 | if (n == NULL) |
| 241 | return; |
| 242 | |
| 243 | if (div < 31) |
| 244 | *k = 0; |
| 245 | else if (div / 2 < 31) |
| 246 | *k = 1; |
| 247 | else if (div / 3 < 31) |
| 248 | *k = 2; |
| 249 | else |
| 250 | *k = 3; |
| 251 | |
| 252 | *n = DIV_ROUND_UP(div, (*k+1)); |
| 253 | } |
| 254 | |
| 255 | |
| 256 | |
| 257 | /** |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 258 | * sun4i_get_apb1_factors() - calculates m, p factors for APB1 |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 259 | * APB1 rate is calculated as follows |
| 260 | * rate = (parent_rate >> p) / (m + 1); |
| 261 | */ |
| 262 | |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 263 | static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 264 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 265 | { |
| 266 | u8 calcm, calcp; |
| 267 | |
| 268 | if (parent_rate < *freq) |
| 269 | *freq = parent_rate; |
| 270 | |
| 271 | parent_rate = (parent_rate + (*freq - 1)) / *freq; |
| 272 | |
| 273 | /* Invalid rate! */ |
| 274 | if (parent_rate > 32) |
| 275 | return; |
| 276 | |
| 277 | if (parent_rate <= 4) |
| 278 | calcp = 0; |
| 279 | else if (parent_rate <= 8) |
| 280 | calcp = 1; |
| 281 | else if (parent_rate <= 16) |
| 282 | calcp = 2; |
| 283 | else |
| 284 | calcp = 3; |
| 285 | |
| 286 | calcm = (parent_rate >> calcp) - 1; |
| 287 | |
| 288 | *freq = (parent_rate >> calcp) / (calcm + 1); |
| 289 | |
| 290 | /* we were called to round the frequency, we can now return */ |
| 291 | if (n == NULL) |
| 292 | return; |
| 293 | |
| 294 | *m = calcm; |
| 295 | *p = calcp; |
| 296 | } |
| 297 | |
| 298 | |
| 299 | |
| 300 | /** |
Emilio López | 7551769 | 2013-12-23 00:32:39 -0300 | [diff] [blame] | 301 | * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks |
| 302 | * MMC rate is calculated as follows |
| 303 | * rate = (parent_rate >> p) / (m + 1); |
| 304 | */ |
| 305 | |
| 306 | static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate, |
| 307 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 308 | { |
| 309 | u8 div, calcm, calcp; |
| 310 | |
| 311 | /* These clocks can only divide, so we will never be able to achieve |
| 312 | * frequencies higher than the parent frequency */ |
| 313 | if (*freq > parent_rate) |
| 314 | *freq = parent_rate; |
| 315 | |
| 316 | div = parent_rate / *freq; |
| 317 | |
| 318 | if (div < 16) |
| 319 | calcp = 0; |
| 320 | else if (div / 2 < 16) |
| 321 | calcp = 1; |
| 322 | else if (div / 4 < 16) |
| 323 | calcp = 2; |
| 324 | else |
| 325 | calcp = 3; |
| 326 | |
| 327 | calcm = DIV_ROUND_UP(div, 1 << calcp); |
| 328 | |
| 329 | *freq = (parent_rate >> calcp) / calcm; |
| 330 | |
| 331 | /* we were called to round the frequency, we can now return */ |
| 332 | if (n == NULL) |
| 333 | return; |
| 334 | |
| 335 | *m = calcm - 1; |
| 336 | *p = calcp; |
| 337 | } |
| 338 | |
| 339 | |
| 340 | |
| 341 | /** |
Chen-Yu Tsai | 6f86341 | 2013-12-24 21:26:17 +0800 | [diff] [blame] | 342 | * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B |
| 343 | * CLK_OUT rate is calculated as follows |
| 344 | * rate = (parent_rate >> p) / (m + 1); |
| 345 | */ |
| 346 | |
| 347 | static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate, |
| 348 | u8 *n, u8 *k, u8 *m, u8 *p) |
| 349 | { |
| 350 | u8 div, calcm, calcp; |
| 351 | |
| 352 | /* These clocks can only divide, so we will never be able to achieve |
| 353 | * frequencies higher than the parent frequency */ |
| 354 | if (*freq > parent_rate) |
| 355 | *freq = parent_rate; |
| 356 | |
| 357 | div = parent_rate / *freq; |
| 358 | |
| 359 | if (div < 32) |
| 360 | calcp = 0; |
| 361 | else if (div / 2 < 32) |
| 362 | calcp = 1; |
| 363 | else if (div / 4 < 32) |
| 364 | calcp = 2; |
| 365 | else |
| 366 | calcp = 3; |
| 367 | |
| 368 | calcm = DIV_ROUND_UP(div, 1 << calcp); |
| 369 | |
| 370 | *freq = (parent_rate >> calcp) / calcm; |
| 371 | |
| 372 | /* we were called to round the frequency, we can now return */ |
| 373 | if (n == NULL) |
| 374 | return; |
| 375 | |
| 376 | *m = calcm - 1; |
| 377 | *p = calcp; |
| 378 | } |
| 379 | |
| 380 | |
| 381 | |
| 382 | /** |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 383 | * sunxi_factors_clk_setup() - Setup function for factor clocks |
| 384 | */ |
| 385 | |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 386 | #define SUNXI_FACTORS_MUX_MASK 0x3 |
| 387 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 388 | struct factors_data { |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 389 | int enable; |
| 390 | int mux; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 391 | struct clk_factors_config *table; |
| 392 | void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p); |
Chen-Yu Tsai | 667f542 | 2014-02-03 09:51:39 +0800 | [diff] [blame] | 393 | const char *name; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 394 | }; |
| 395 | |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 396 | static struct clk_factors_config sun4i_pll1_config = { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 397 | .nshift = 8, |
| 398 | .nwidth = 5, |
| 399 | .kshift = 4, |
| 400 | .kwidth = 2, |
| 401 | .mshift = 0, |
| 402 | .mwidth = 2, |
| 403 | .pshift = 16, |
| 404 | .pwidth = 2, |
| 405 | }; |
| 406 | |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 407 | static struct clk_factors_config sun6i_a31_pll1_config = { |
| 408 | .nshift = 8, |
| 409 | .nwidth = 5, |
| 410 | .kshift = 4, |
| 411 | .kwidth = 2, |
| 412 | .mshift = 0, |
| 413 | .mwidth = 2, |
| 414 | }; |
| 415 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 416 | static struct clk_factors_config sun4i_pll5_config = { |
| 417 | .nshift = 8, |
| 418 | .nwidth = 5, |
| 419 | .kshift = 4, |
| 420 | .kwidth = 2, |
| 421 | }; |
| 422 | |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 423 | static struct clk_factors_config sun4i_apb1_config = { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 424 | .mshift = 0, |
| 425 | .mwidth = 5, |
| 426 | .pshift = 16, |
| 427 | .pwidth = 2, |
| 428 | }; |
| 429 | |
Emilio López | 7551769 | 2013-12-23 00:32:39 -0300 | [diff] [blame] | 430 | /* user manual says "n" but it's really "p" */ |
| 431 | static struct clk_factors_config sun4i_mod0_config = { |
| 432 | .mshift = 0, |
| 433 | .mwidth = 4, |
| 434 | .pshift = 16, |
| 435 | .pwidth = 2, |
| 436 | }; |
| 437 | |
Chen-Yu Tsai | 6f86341 | 2013-12-24 21:26:17 +0800 | [diff] [blame] | 438 | /* user manual says "n" but it's really "p" */ |
| 439 | static struct clk_factors_config sun7i_a20_out_config = { |
| 440 | .mshift = 8, |
| 441 | .mwidth = 5, |
| 442 | .pshift = 20, |
| 443 | .pwidth = 2, |
| 444 | }; |
| 445 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 446 | static const struct factors_data sun4i_pll1_data __initconst = { |
Emilio López | d838ff3 | 2013-12-23 00:32:34 -0300 | [diff] [blame] | 447 | .enable = 31, |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 448 | .table = &sun4i_pll1_config, |
| 449 | .getter = sun4i_get_pll1_factors, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 450 | }; |
| 451 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 452 | static const struct factors_data sun6i_a31_pll1_data __initconst = { |
Emilio López | d838ff3 | 2013-12-23 00:32:34 -0300 | [diff] [blame] | 453 | .enable = 31, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 454 | .table = &sun6i_a31_pll1_config, |
| 455 | .getter = sun6i_a31_get_pll1_factors, |
| 456 | }; |
| 457 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 458 | static const struct factors_data sun4i_pll5_data __initconst = { |
| 459 | .enable = 31, |
| 460 | .table = &sun4i_pll5_config, |
| 461 | .getter = sun4i_get_pll5_factors, |
Chen-Yu Tsai | 667f542 | 2014-02-03 09:51:39 +0800 | [diff] [blame] | 462 | .name = "pll5", |
| 463 | }; |
| 464 | |
| 465 | static const struct factors_data sun4i_pll6_data __initconst = { |
| 466 | .enable = 31, |
| 467 | .table = &sun4i_pll5_config, |
| 468 | .getter = sun4i_get_pll5_factors, |
| 469 | .name = "pll6", |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 470 | }; |
| 471 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 472 | static const struct factors_data sun4i_apb1_data __initconst = { |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 473 | .table = &sun4i_apb1_config, |
| 474 | .getter = sun4i_get_apb1_factors, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 475 | }; |
| 476 | |
Emilio López | 7551769 | 2013-12-23 00:32:39 -0300 | [diff] [blame] | 477 | static const struct factors_data sun4i_mod0_data __initconst = { |
| 478 | .enable = 31, |
| 479 | .mux = 24, |
| 480 | .table = &sun4i_mod0_config, |
| 481 | .getter = sun4i_get_mod0_factors, |
| 482 | }; |
| 483 | |
Chen-Yu Tsai | 6f86341 | 2013-12-24 21:26:17 +0800 | [diff] [blame] | 484 | static const struct factors_data sun7i_a20_out_data __initconst = { |
| 485 | .enable = 31, |
| 486 | .mux = 24, |
| 487 | .table = &sun7i_a20_out_config, |
| 488 | .getter = sun7i_a20_get_out_factors, |
| 489 | }; |
| 490 | |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 491 | static struct clk * __init sunxi_factors_clk_setup(struct device_node *node, |
| 492 | const struct factors_data *data) |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 493 | { |
| 494 | struct clk *clk; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 495 | struct clk_factors *factors; |
| 496 | struct clk_gate *gate = NULL; |
| 497 | struct clk_mux *mux = NULL; |
| 498 | struct clk_hw *gate_hw = NULL; |
| 499 | struct clk_hw *mux_hw = NULL; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 500 | const char *clk_name = node->name; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 501 | const char *parents[SUNXI_MAX_PARENTS]; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 502 | void *reg; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 503 | int i = 0; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 504 | |
| 505 | reg = of_iomap(node, 0); |
| 506 | |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 507 | /* if we have a mux, we will have >1 parents */ |
| 508 | while (i < SUNXI_MAX_PARENTS && |
| 509 | (parents[i] = of_clk_get_parent_name(node, i)) != NULL) |
| 510 | i++; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 511 | |
Chen-Yu Tsai | 667f542 | 2014-02-03 09:51:39 +0800 | [diff] [blame] | 512 | /* |
| 513 | * some factor clocks, such as pll5 and pll6, may have multiple |
| 514 | * outputs, and have their name designated in factors_data |
| 515 | */ |
| 516 | if (data->name) |
| 517 | clk_name = data->name; |
| 518 | else |
| 519 | of_property_read_string(node, "clock-output-names", &clk_name); |
Emilio López | 76192dc | 2013-12-23 00:32:40 -0300 | [diff] [blame] | 520 | |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 521 | factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL); |
| 522 | if (!factors) |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 523 | return NULL; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 524 | |
| 525 | /* Add a gate if this factor clock can be gated */ |
| 526 | if (data->enable) { |
| 527 | gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); |
| 528 | if (!gate) { |
| 529 | kfree(factors); |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 530 | return NULL; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 531 | } |
| 532 | |
| 533 | /* set up gate properties */ |
| 534 | gate->reg = reg; |
| 535 | gate->bit_idx = data->enable; |
| 536 | gate->lock = &clk_lock; |
| 537 | gate_hw = &gate->hw; |
| 538 | } |
| 539 | |
| 540 | /* Add a mux if this factor clock can be muxed */ |
| 541 | if (data->mux) { |
| 542 | mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); |
| 543 | if (!mux) { |
| 544 | kfree(factors); |
| 545 | kfree(gate); |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 546 | return NULL; |
Emilio López | 40a5dcb | 2013-12-23 00:32:32 -0300 | [diff] [blame] | 547 | } |
| 548 | |
| 549 | /* set up gate properties */ |
| 550 | mux->reg = reg; |
| 551 | mux->shift = data->mux; |
| 552 | mux->mask = SUNXI_FACTORS_MUX_MASK; |
| 553 | mux->lock = &clk_lock; |
| 554 | mux_hw = &mux->hw; |
| 555 | } |
| 556 | |
| 557 | /* set up factors properties */ |
| 558 | factors->reg = reg; |
| 559 | factors->config = data->table; |
| 560 | factors->get_factors = data->getter; |
| 561 | factors->lock = &clk_lock; |
| 562 | |
| 563 | clk = clk_register_composite(NULL, clk_name, |
| 564 | parents, i, |
| 565 | mux_hw, &clk_mux_ops, |
| 566 | &factors->hw, &clk_factors_ops, |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 567 | gate_hw, &clk_gate_ops, 0); |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 568 | |
Axel Lin | ee85e9b | 2013-07-12 16:15:15 +0800 | [diff] [blame] | 569 | if (!IS_ERR(clk)) { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 570 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 571 | clk_register_clkdev(clk, clk_name, NULL); |
| 572 | } |
Emilio López | 5f4e0be | 2013-12-23 00:32:36 -0300 | [diff] [blame] | 573 | |
| 574 | return clk; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 575 | } |
| 576 | |
| 577 | |
| 578 | |
| 579 | /** |
| 580 | * sunxi_mux_clk_setup() - Setup function for muxes |
| 581 | */ |
| 582 | |
| 583 | #define SUNXI_MUX_GATE_WIDTH 2 |
| 584 | |
| 585 | struct mux_data { |
| 586 | u8 shift; |
| 587 | }; |
| 588 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 589 | static const struct mux_data sun4i_cpu_mux_data __initconst = { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 590 | .shift = 16, |
| 591 | }; |
| 592 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 593 | static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 594 | .shift = 12, |
| 595 | }; |
| 596 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 597 | static const struct mux_data sun4i_apb1_mux_data __initconst = { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 598 | .shift = 24, |
| 599 | }; |
| 600 | |
| 601 | static void __init sunxi_mux_clk_setup(struct device_node *node, |
| 602 | struct mux_data *data) |
| 603 | { |
| 604 | struct clk *clk; |
| 605 | const char *clk_name = node->name; |
Emilio López | edaf3fb | 2013-12-23 00:32:33 -0300 | [diff] [blame] | 606 | const char *parents[SUNXI_MAX_PARENTS]; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 607 | void *reg; |
| 608 | int i = 0; |
| 609 | |
| 610 | reg = of_iomap(node, 0); |
| 611 | |
Emilio López | edaf3fb | 2013-12-23 00:32:33 -0300 | [diff] [blame] | 612 | while (i < SUNXI_MAX_PARENTS && |
| 613 | (parents[i] = of_clk_get_parent_name(node, i)) != NULL) |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 614 | i++; |
| 615 | |
Chen-Yu Tsai | f64111e | 2014-02-03 09:51:37 +0800 | [diff] [blame] | 616 | of_property_read_string(node, "clock-output-names", &clk_name); |
| 617 | |
James Hogan | 819c1de | 2013-07-29 12:25:01 +0100 | [diff] [blame] | 618 | clk = clk_register_mux(NULL, clk_name, parents, i, |
| 619 | CLK_SET_RATE_NO_REPARENT, reg, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 620 | data->shift, SUNXI_MUX_GATE_WIDTH, |
| 621 | 0, &clk_lock); |
| 622 | |
| 623 | if (clk) { |
| 624 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 625 | clk_register_clkdev(clk, clk_name, NULL); |
| 626 | } |
| 627 | } |
| 628 | |
| 629 | |
| 630 | |
| 631 | /** |
| 632 | * sunxi_divider_clk_setup() - Setup function for simple divider clocks |
| 633 | */ |
| 634 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 635 | struct div_data { |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 636 | u8 shift; |
| 637 | u8 pow; |
| 638 | u8 width; |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 639 | }; |
| 640 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 641 | static const struct div_data sun4i_axi_data __initconst = { |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 642 | .shift = 0, |
| 643 | .pow = 0, |
| 644 | .width = 2, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 645 | }; |
| 646 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 647 | static const struct div_data sun4i_ahb_data __initconst = { |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 648 | .shift = 4, |
| 649 | .pow = 1, |
| 650 | .width = 2, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 651 | }; |
| 652 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 653 | static const struct div_data sun4i_apb0_data __initconst = { |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 654 | .shift = 8, |
| 655 | .pow = 1, |
| 656 | .width = 2, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 657 | }; |
| 658 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 659 | static const struct div_data sun6i_a31_apb2_div_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 660 | .shift = 0, |
| 661 | .pow = 0, |
| 662 | .width = 4, |
| 663 | }; |
| 664 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 665 | static void __init sunxi_divider_clk_setup(struct device_node *node, |
| 666 | struct div_data *data) |
| 667 | { |
| 668 | struct clk *clk; |
| 669 | const char *clk_name = node->name; |
| 670 | const char *clk_parent; |
| 671 | void *reg; |
| 672 | |
| 673 | reg = of_iomap(node, 0); |
| 674 | |
| 675 | clk_parent = of_clk_get_parent_name(node, 0); |
| 676 | |
Chen-Yu Tsai | f64111e | 2014-02-03 09:51:37 +0800 | [diff] [blame] | 677 | of_property_read_string(node, "clock-output-names", &clk_name); |
| 678 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 679 | clk = clk_register_divider(NULL, clk_name, clk_parent, 0, |
Maxime Ripard | 70855bb | 2013-07-23 09:25:56 +0200 | [diff] [blame] | 680 | reg, data->shift, data->width, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 681 | data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0, |
| 682 | &clk_lock); |
| 683 | if (clk) { |
| 684 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
| 685 | clk_register_clkdev(clk, clk_name, NULL); |
| 686 | } |
| 687 | } |
| 688 | |
| 689 | |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 690 | |
| 691 | /** |
Hans de Goede | cfb0086 | 2014-02-07 16:21:49 +0100 | [diff] [blame^] | 692 | * sunxi_gates_reset... - reset bits in leaf gate clk registers handling |
| 693 | */ |
| 694 | |
| 695 | struct gates_reset_data { |
| 696 | void __iomem *reg; |
| 697 | spinlock_t *lock; |
| 698 | struct reset_controller_dev rcdev; |
| 699 | }; |
| 700 | |
| 701 | static int sunxi_gates_reset_assert(struct reset_controller_dev *rcdev, |
| 702 | unsigned long id) |
| 703 | { |
| 704 | struct gates_reset_data *data = container_of(rcdev, |
| 705 | struct gates_reset_data, |
| 706 | rcdev); |
| 707 | unsigned long flags; |
| 708 | u32 reg; |
| 709 | |
| 710 | spin_lock_irqsave(data->lock, flags); |
| 711 | |
| 712 | reg = readl(data->reg); |
| 713 | writel(reg & ~BIT(id), data->reg); |
| 714 | |
| 715 | spin_unlock_irqrestore(data->lock, flags); |
| 716 | |
| 717 | return 0; |
| 718 | } |
| 719 | |
| 720 | static int sunxi_gates_reset_deassert(struct reset_controller_dev *rcdev, |
| 721 | unsigned long id) |
| 722 | { |
| 723 | struct gates_reset_data *data = container_of(rcdev, |
| 724 | struct gates_reset_data, |
| 725 | rcdev); |
| 726 | unsigned long flags; |
| 727 | u32 reg; |
| 728 | |
| 729 | spin_lock_irqsave(data->lock, flags); |
| 730 | |
| 731 | reg = readl(data->reg); |
| 732 | writel(reg | BIT(id), data->reg); |
| 733 | |
| 734 | spin_unlock_irqrestore(data->lock, flags); |
| 735 | |
| 736 | return 0; |
| 737 | } |
| 738 | |
| 739 | static struct reset_control_ops sunxi_gates_reset_ops = { |
| 740 | .assert = sunxi_gates_reset_assert, |
| 741 | .deassert = sunxi_gates_reset_deassert, |
| 742 | }; |
| 743 | |
| 744 | /** |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 745 | * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks |
| 746 | */ |
| 747 | |
| 748 | #define SUNXI_GATES_MAX_SIZE 64 |
| 749 | |
| 750 | struct gates_data { |
| 751 | DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE); |
Hans de Goede | cfb0086 | 2014-02-07 16:21:49 +0100 | [diff] [blame^] | 752 | u32 reset_mask; |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 753 | }; |
| 754 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 755 | static const struct gates_data sun4i_axi_gates_data __initconst = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 756 | .mask = {1}, |
| 757 | }; |
| 758 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 759 | static const struct gates_data sun4i_ahb_gates_data __initconst = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 760 | .mask = {0x7F77FFF, 0x14FB3F}, |
| 761 | }; |
| 762 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 763 | static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = { |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 764 | .mask = {0x147667e7, 0x185915}, |
| 765 | }; |
| 766 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 767 | static const struct gates_data sun5i_a13_ahb_gates_data __initconst = { |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 768 | .mask = {0x107067e7, 0x185111}, |
| 769 | }; |
| 770 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 771 | static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 772 | .mask = {0xEDFE7F62, 0x794F931}, |
| 773 | }; |
| 774 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 775 | static const struct gates_data sun7i_a20_ahb_gates_data __initconst = { |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 776 | .mask = { 0x12f77fff, 0x16ff3f }, |
| 777 | }; |
| 778 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 779 | static const struct gates_data sun4i_apb0_gates_data __initconst = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 780 | .mask = {0x4EF}, |
| 781 | }; |
| 782 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 783 | static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = { |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 784 | .mask = {0x469}, |
| 785 | }; |
| 786 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 787 | static const struct gates_data sun5i_a13_apb0_gates_data __initconst = { |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 788 | .mask = {0x61}, |
| 789 | }; |
| 790 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 791 | static const struct gates_data sun7i_a20_apb0_gates_data __initconst = { |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 792 | .mask = { 0x4ff }, |
| 793 | }; |
| 794 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 795 | static const struct gates_data sun4i_apb1_gates_data __initconst = { |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 796 | .mask = {0xFF00F7}, |
| 797 | }; |
| 798 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 799 | static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = { |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 800 | .mask = {0xf0007}, |
| 801 | }; |
| 802 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 803 | static const struct gates_data sun5i_a13_apb1_gates_data __initconst = { |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 804 | .mask = {0xa0007}, |
| 805 | }; |
| 806 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 807 | static const struct gates_data sun6i_a31_apb1_gates_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 808 | .mask = {0x3031}, |
| 809 | }; |
| 810 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 811 | static const struct gates_data sun6i_a31_apb2_gates_data __initconst = { |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 812 | .mask = {0x3F000F}, |
| 813 | }; |
| 814 | |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 815 | static const struct gates_data sun7i_a20_apb1_gates_data __initconst = { |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 816 | .mask = { 0xff80ff }, |
| 817 | }; |
| 818 | |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 819 | static void __init sunxi_gates_clk_setup(struct device_node *node, |
| 820 | struct gates_data *data) |
| 821 | { |
| 822 | struct clk_onecell_data *clk_data; |
Hans de Goede | cfb0086 | 2014-02-07 16:21:49 +0100 | [diff] [blame^] | 823 | struct gates_reset_data *reset_data; |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 824 | const char *clk_parent; |
| 825 | const char *clk_name; |
| 826 | void *reg; |
| 827 | int qty; |
| 828 | int i = 0; |
| 829 | int j = 0; |
| 830 | int ignore; |
| 831 | |
| 832 | reg = of_iomap(node, 0); |
| 833 | |
| 834 | clk_parent = of_clk_get_parent_name(node, 0); |
| 835 | |
| 836 | /* Worst-case size approximation and memory allocation */ |
| 837 | qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE); |
| 838 | clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); |
| 839 | if (!clk_data) |
| 840 | return; |
| 841 | clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL); |
| 842 | if (!clk_data->clks) { |
| 843 | kfree(clk_data); |
| 844 | return; |
| 845 | } |
| 846 | |
| 847 | for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) { |
| 848 | of_property_read_string_index(node, "clock-output-names", |
| 849 | j, &clk_name); |
| 850 | |
| 851 | /* No driver claims this clock, but it should remain gated */ |
| 852 | ignore = !strcmp("ahb_sdram", clk_name) ? CLK_IGNORE_UNUSED : 0; |
| 853 | |
| 854 | clk_data->clks[i] = clk_register_gate(NULL, clk_name, |
| 855 | clk_parent, ignore, |
| 856 | reg + 4 * (i/32), i % 32, |
| 857 | 0, &clk_lock); |
| 858 | WARN_ON(IS_ERR(clk_data->clks[i])); |
| 859 | |
| 860 | j++; |
| 861 | } |
| 862 | |
| 863 | /* Adjust to the real max */ |
| 864 | clk_data->clk_num = i; |
| 865 | |
| 866 | of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
Hans de Goede | cfb0086 | 2014-02-07 16:21:49 +0100 | [diff] [blame^] | 867 | |
| 868 | /* Register a reset controler for gates with reset bits */ |
| 869 | if (data->reset_mask == 0) |
| 870 | return; |
| 871 | |
| 872 | reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL); |
| 873 | if (!reset_data) |
| 874 | return; |
| 875 | |
| 876 | reset_data->reg = reg; |
| 877 | reset_data->lock = &clk_lock; |
| 878 | reset_data->rcdev.nr_resets = __fls(data->reset_mask) + 1; |
| 879 | reset_data->rcdev.ops = &sunxi_gates_reset_ops; |
| 880 | reset_data->rcdev.of_node = node; |
| 881 | reset_controller_register(&reset_data->rcdev); |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 882 | } |
| 883 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 884 | |
| 885 | |
| 886 | /** |
| 887 | * sunxi_divs_clk_setup() helper data |
| 888 | */ |
| 889 | |
| 890 | #define SUNXI_DIVS_MAX_QTY 2 |
| 891 | #define SUNXI_DIVISOR_WIDTH 2 |
| 892 | |
| 893 | struct divs_data { |
| 894 | const struct factors_data *factors; /* data for the factor clock */ |
| 895 | struct { |
| 896 | u8 fixed; /* is it a fixed divisor? if not... */ |
| 897 | struct clk_div_table *table; /* is it a table based divisor? */ |
| 898 | u8 shift; /* otherwise it's a normal divisor with this shift */ |
| 899 | u8 pow; /* is it power-of-two based? */ |
| 900 | u8 gate; /* is it independently gateable? */ |
| 901 | } div[SUNXI_DIVS_MAX_QTY]; |
| 902 | }; |
| 903 | |
| 904 | static struct clk_div_table pll6_sata_tbl[] = { |
| 905 | { .val = 0, .div = 6, }, |
| 906 | { .val = 1, .div = 12, }, |
| 907 | { .val = 2, .div = 18, }, |
| 908 | { .val = 3, .div = 24, }, |
| 909 | { } /* sentinel */ |
| 910 | }; |
| 911 | |
| 912 | static const struct divs_data pll5_divs_data __initconst = { |
| 913 | .factors = &sun4i_pll5_data, |
| 914 | .div = { |
| 915 | { .shift = 0, .pow = 0, }, /* M, DDR */ |
| 916 | { .shift = 16, .pow = 1, }, /* P, other */ |
| 917 | } |
| 918 | }; |
| 919 | |
| 920 | static const struct divs_data pll6_divs_data __initconst = { |
Chen-Yu Tsai | 667f542 | 2014-02-03 09:51:39 +0800 | [diff] [blame] | 921 | .factors = &sun4i_pll6_data, |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 922 | .div = { |
| 923 | { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */ |
| 924 | { .fixed = 2 }, /* P, other */ |
| 925 | } |
| 926 | }; |
| 927 | |
| 928 | /** |
| 929 | * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks |
| 930 | * |
| 931 | * These clocks look something like this |
| 932 | * ________________________ |
| 933 | * | ___divisor 1---|----> to consumer |
| 934 | * parent >--| pll___/___divisor 2---|----> to consumer |
| 935 | * | \_______________|____> to consumer |
| 936 | * |________________________| |
| 937 | */ |
| 938 | |
| 939 | static void __init sunxi_divs_clk_setup(struct device_node *node, |
| 940 | struct divs_data *data) |
| 941 | { |
| 942 | struct clk_onecell_data *clk_data; |
Chen-Yu Tsai | 97e36b3 | 2014-02-03 09:51:40 +0800 | [diff] [blame] | 943 | const char *parent; |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 944 | const char *clk_name; |
| 945 | struct clk **clks, *pclk; |
| 946 | struct clk_hw *gate_hw, *rate_hw; |
| 947 | const struct clk_ops *rate_ops; |
| 948 | struct clk_gate *gate = NULL; |
| 949 | struct clk_fixed_factor *fix_factor; |
| 950 | struct clk_divider *divider; |
| 951 | void *reg; |
| 952 | int i = 0; |
| 953 | int flags, clkflags; |
| 954 | |
| 955 | /* Set up factor clock that we will be dividing */ |
| 956 | pclk = sunxi_factors_clk_setup(node, data->factors); |
Chen-Yu Tsai | 97e36b3 | 2014-02-03 09:51:40 +0800 | [diff] [blame] | 957 | parent = __clk_get_name(pclk); |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 958 | |
| 959 | reg = of_iomap(node, 0); |
| 960 | |
| 961 | clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL); |
| 962 | if (!clk_data) |
| 963 | return; |
| 964 | |
Emilio López | d193368 | 2014-01-24 22:32:41 -0300 | [diff] [blame] | 965 | clks = kzalloc((SUNXI_DIVS_MAX_QTY+1) * sizeof(*clks), GFP_KERNEL); |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 966 | if (!clks) |
| 967 | goto free_clkdata; |
| 968 | |
| 969 | clk_data->clks = clks; |
| 970 | |
| 971 | /* It's not a good idea to have automatic reparenting changing |
| 972 | * our RAM clock! */ |
| 973 | clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT; |
| 974 | |
| 975 | for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) { |
| 976 | if (of_property_read_string_index(node, "clock-output-names", |
| 977 | i, &clk_name) != 0) |
| 978 | break; |
| 979 | |
| 980 | gate_hw = NULL; |
| 981 | rate_hw = NULL; |
| 982 | rate_ops = NULL; |
| 983 | |
| 984 | /* If this leaf clock can be gated, create a gate */ |
| 985 | if (data->div[i].gate) { |
| 986 | gate = kzalloc(sizeof(*gate), GFP_KERNEL); |
| 987 | if (!gate) |
| 988 | goto free_clks; |
| 989 | |
| 990 | gate->reg = reg; |
| 991 | gate->bit_idx = data->div[i].gate; |
| 992 | gate->lock = &clk_lock; |
| 993 | |
| 994 | gate_hw = &gate->hw; |
| 995 | } |
| 996 | |
| 997 | /* Leaves can be fixed or configurable divisors */ |
| 998 | if (data->div[i].fixed) { |
| 999 | fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL); |
| 1000 | if (!fix_factor) |
| 1001 | goto free_gate; |
| 1002 | |
| 1003 | fix_factor->mult = 1; |
| 1004 | fix_factor->div = data->div[i].fixed; |
| 1005 | |
| 1006 | rate_hw = &fix_factor->hw; |
| 1007 | rate_ops = &clk_fixed_factor_ops; |
| 1008 | } else { |
| 1009 | divider = kzalloc(sizeof(*divider), GFP_KERNEL); |
| 1010 | if (!divider) |
| 1011 | goto free_gate; |
| 1012 | |
| 1013 | flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0; |
| 1014 | |
| 1015 | divider->reg = reg; |
| 1016 | divider->shift = data->div[i].shift; |
| 1017 | divider->width = SUNXI_DIVISOR_WIDTH; |
| 1018 | divider->flags = flags; |
| 1019 | divider->lock = &clk_lock; |
| 1020 | divider->table = data->div[i].table; |
| 1021 | |
| 1022 | rate_hw = ÷r->hw; |
| 1023 | rate_ops = &clk_divider_ops; |
| 1024 | } |
| 1025 | |
| 1026 | /* Wrap the (potential) gate and the divisor on a composite |
| 1027 | * clock to unify them */ |
| 1028 | clks[i] = clk_register_composite(NULL, clk_name, &parent, 1, |
| 1029 | NULL, NULL, |
| 1030 | rate_hw, rate_ops, |
| 1031 | gate_hw, &clk_gate_ops, |
| 1032 | clkflags); |
| 1033 | |
| 1034 | WARN_ON(IS_ERR(clk_data->clks[i])); |
| 1035 | clk_register_clkdev(clks[i], clk_name, NULL); |
| 1036 | } |
| 1037 | |
| 1038 | /* The last clock available on the getter is the parent */ |
| 1039 | clks[i++] = pclk; |
| 1040 | |
| 1041 | /* Adjust to the real max */ |
| 1042 | clk_data->clk_num = i; |
| 1043 | |
| 1044 | of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); |
| 1045 | |
| 1046 | return; |
| 1047 | |
| 1048 | free_gate: |
| 1049 | kfree(gate); |
| 1050 | free_clks: |
| 1051 | kfree(clks); |
| 1052 | free_clkdata: |
| 1053 | kfree(clk_data); |
| 1054 | } |
| 1055 | |
| 1056 | |
| 1057 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1058 | /* Matches for factors clocks */ |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 1059 | static const struct of_device_id clk_factors_match[] __initconst = { |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 1060 | {.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 1061 | {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,}, |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 1062 | {.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,}, |
Emilio López | 7551769 | 2013-12-23 00:32:39 -0300 | [diff] [blame] | 1063 | {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,}, |
Chen-Yu Tsai | 6f86341 | 2013-12-24 21:26:17 +0800 | [diff] [blame] | 1064 | {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,}, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1065 | {} |
| 1066 | }; |
| 1067 | |
| 1068 | /* Matches for divider clocks */ |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 1069 | static const struct of_device_id clk_div_match[] __initconst = { |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 1070 | {.compatible = "allwinner,sun4i-axi-clk", .data = &sun4i_axi_data,}, |
| 1071 | {.compatible = "allwinner,sun4i-ahb-clk", .data = &sun4i_ahb_data,}, |
| 1072 | {.compatible = "allwinner,sun4i-apb0-clk", .data = &sun4i_apb0_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 1073 | {.compatible = "allwinner,sun6i-a31-apb2-div-clk", .data = &sun6i_a31_apb2_div_data,}, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1074 | {} |
| 1075 | }; |
| 1076 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 1077 | /* Matches for divided outputs */ |
| 1078 | static const struct of_device_id clk_divs_match[] __initconst = { |
| 1079 | {.compatible = "allwinner,sun4i-pll5-clk", .data = &pll5_divs_data,}, |
| 1080 | {.compatible = "allwinner,sun4i-pll6-clk", .data = &pll6_divs_data,}, |
| 1081 | {} |
| 1082 | }; |
| 1083 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1084 | /* Matches for mux clocks */ |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 1085 | static const struct of_device_id clk_mux_match[] __initconst = { |
Maxime Ripard | 81ba6c5 | 2013-07-22 18:21:32 +0200 | [diff] [blame] | 1086 | {.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,}, |
| 1087 | {.compatible = "allwinner,sun4i-apb1-mux-clk", .data = &sun4i_apb1_mux_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 1088 | {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,}, |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1089 | {} |
| 1090 | }; |
| 1091 | |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 1092 | /* Matches for gate clocks */ |
Sachin Kamat | 52be7cc | 2013-08-12 14:44:06 +0530 | [diff] [blame] | 1093 | static const struct of_device_id clk_gates_match[] __initconst = { |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 1094 | {.compatible = "allwinner,sun4i-axi-gates-clk", .data = &sun4i_axi_gates_data,}, |
| 1095 | {.compatible = "allwinner,sun4i-ahb-gates-clk", .data = &sun4i_ahb_gates_data,}, |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 1096 | {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,}, |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 1097 | {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 1098 | {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,}, |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 1099 | {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,}, |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 1100 | {.compatible = "allwinner,sun4i-apb0-gates-clk", .data = &sun4i_apb0_gates_data,}, |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 1101 | {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,}, |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 1102 | {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,}, |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 1103 | {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,}, |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 1104 | {.compatible = "allwinner,sun4i-apb1-gates-clk", .data = &sun4i_apb1_gates_data,}, |
Maxime Ripard | 2371dd8 | 2013-07-16 11:21:59 +0200 | [diff] [blame] | 1105 | {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,}, |
Maxime Ripard | 4f985b4 | 2013-04-30 11:56:22 +0200 | [diff] [blame] | 1106 | {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 1107 | {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,}, |
Maxime Ripard | 1fb2e4a | 2013-07-25 21:06:56 +0200 | [diff] [blame] | 1108 | {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,}, |
Maxime Ripard | 6a721db | 2013-07-23 23:34:10 +0200 | [diff] [blame] | 1109 | {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,}, |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 1110 | {} |
| 1111 | }; |
| 1112 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1113 | static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match, |
| 1114 | void *function) |
| 1115 | { |
| 1116 | struct device_node *np; |
| 1117 | const struct div_data *data; |
| 1118 | const struct of_device_id *match; |
| 1119 | void (*setup_function)(struct device_node *, const void *) = function; |
| 1120 | |
| 1121 | for_each_matching_node(np, clk_match) { |
| 1122 | match = of_match_node(clk_match, np); |
| 1123 | data = match->data; |
| 1124 | setup_function(np, data); |
| 1125 | } |
| 1126 | } |
| 1127 | |
Emilio López | 8e6a4c4 | 2013-09-20 22:03:12 -0300 | [diff] [blame] | 1128 | /** |
| 1129 | * System clock protection |
| 1130 | * |
| 1131 | * By enabling these critical clocks, we prevent their accidental gating |
| 1132 | * by the framework |
| 1133 | */ |
| 1134 | static void __init sunxi_clock_protect(void) |
| 1135 | { |
| 1136 | struct clk *clk; |
| 1137 | |
| 1138 | /* memory bus clock - sun5i+ */ |
| 1139 | clk = clk_get(NULL, "mbus"); |
| 1140 | if (!IS_ERR(clk)) { |
| 1141 | clk_prepare_enable(clk); |
| 1142 | clk_put(clk); |
| 1143 | } |
| 1144 | |
| 1145 | /* DDR clock - sun4i+ */ |
| 1146 | clk = clk_get(NULL, "pll5_ddr"); |
| 1147 | if (!IS_ERR(clk)) { |
| 1148 | clk_prepare_enable(clk); |
| 1149 | clk_put(clk); |
| 1150 | } |
| 1151 | } |
| 1152 | |
Mike Turquette | 1d9438f | 2013-12-01 12:42:45 -0800 | [diff] [blame] | 1153 | static void __init sunxi_init_clocks(void) |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1154 | { |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1155 | /* Register factor clocks */ |
| 1156 | of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup); |
| 1157 | |
| 1158 | /* Register divider clocks */ |
| 1159 | of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup); |
| 1160 | |
Emilio López | d584c13 | 2013-12-23 00:32:37 -0300 | [diff] [blame] | 1161 | /* Register divided output clocks */ |
| 1162 | of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup); |
| 1163 | |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1164 | /* Register mux clocks */ |
| 1165 | of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup); |
Emilio López | 13569a7 | 2013-03-27 18:20:37 -0300 | [diff] [blame] | 1166 | |
| 1167 | /* Register gate clocks */ |
| 1168 | of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup); |
Emilio López | 8e6a4c4 | 2013-09-20 22:03:12 -0300 | [diff] [blame] | 1169 | |
| 1170 | /* Enable core system clocks */ |
| 1171 | sunxi_clock_protect(); |
Emilio López | e874a66 | 2013-02-25 11:44:26 -0300 | [diff] [blame] | 1172 | } |
Sebastian Hesselbarth | be08045 | 2013-09-06 14:59:57 +0200 | [diff] [blame] | 1173 | CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sunxi_init_clocks); |
| 1174 | CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sunxi_init_clocks); |
| 1175 | CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sunxi_init_clocks); |
| 1176 | CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sunxi_init_clocks); |
| 1177 | CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sunxi_init_clocks); |