Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 13 | #ifndef _SDE_HW_CTL_H |
| 14 | #define _SDE_HW_CTL_H |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 15 | |
| 16 | #include "sde_hw_mdss.h" |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 17 | #include "sde_hw_util.h" |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 18 | #include "sde_hw_catalog.h" |
| 19 | |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 20 | /** |
| 21 | * sde_ctl_mode_sel: Interface mode selection |
| 22 | * SDE_CTL_MODE_SEL_VID: Video mode interface |
| 23 | * SDE_CTL_MODE_SEL_CMD: Command mode interface |
| 24 | */ |
| 25 | enum sde_ctl_mode_sel { |
| 26 | SDE_CTL_MODE_SEL_VID = 0, |
| 27 | SDE_CTL_MODE_SEL_CMD |
| 28 | }; |
| 29 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 30 | struct sde_hw_ctl; |
| 31 | /** |
| 32 | * struct sde_hw_stage_cfg - blending stage cfg |
| 33 | * @stage |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 34 | */ |
| 35 | struct sde_hw_stage_cfg { |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 36 | enum sde_sspp stage[CRTC_DUAL_MIXERS][SDE_STAGE_MAX][PIPES_PER_STAGE]; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 37 | }; |
| 38 | |
| 39 | /** |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 40 | * struct sde_hw_intf_cfg :Describes how the SDE writes data to output interface |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 41 | * @intf : Interface id |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 42 | * @wb: Writeback id |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 43 | * @mode_3d: 3d mux configuration |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 44 | * @intf_mode_sel: Interface mode, cmd / vid |
| 45 | * @stream_sel: Stream selection for multi-stream interfaces |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 46 | */ |
| 47 | struct sde_hw_intf_cfg { |
| 48 | enum sde_intf intf; |
| 49 | enum sde_wb wb; |
| 50 | enum sde_3d_blend_mode mode_3d; |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 51 | enum sde_ctl_mode_sel intf_mode_sel; |
| 52 | int stream_sel; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 53 | }; |
| 54 | |
| 55 | /** |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 56 | * struct sde_hw_ctl_ops - Interface to the wb Hw driver functions |
| 57 | * Assumption is these functions will be called after clocks are enabled |
| 58 | */ |
| 59 | struct sde_hw_ctl_ops { |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 60 | /** |
| 61 | * kickoff hw operation for Sw controlled interfaces |
| 62 | * DSI cmd mode and WB interface are SW controlled |
| 63 | * @ctx : ctl path ctx pointer |
| 64 | */ |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 65 | void (*trigger_start)(struct sde_hw_ctl *ctx); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 66 | |
| 67 | /** |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 68 | * Clear the value of the cached pending_flush_mask |
| 69 | * No effect on hardware |
| 70 | * @ctx : ctl path ctx pointer |
| 71 | */ |
| 72 | void (*clear_pending_flush)(struct sde_hw_ctl *ctx); |
| 73 | |
| 74 | /** |
Clarence Ip | 110d15c | 2016-08-16 14:44:41 -0400 | [diff] [blame] | 75 | * Query the value of the cached pending_flush_mask |
| 76 | * No effect on hardware |
| 77 | * @ctx : ctl path ctx pointer |
| 78 | */ |
| 79 | u32 (*get_pending_flush)(struct sde_hw_ctl *ctx); |
| 80 | |
| 81 | /** |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 82 | * OR in the given flushbits to the cached pending_flush_mask |
| 83 | * No effect on hardware |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 84 | * @ctx : ctl path ctx pointer |
| 85 | * @flushbits : module flushmask |
| 86 | */ |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 87 | void (*update_pending_flush)(struct sde_hw_ctl *ctx, |
| 88 | u32 flushbits); |
| 89 | |
| 90 | /** |
| 91 | * Write the value of the pending_flush_mask to hardware |
| 92 | * @ctx : ctl path ctx pointer |
| 93 | */ |
| 94 | void (*trigger_flush)(struct sde_hw_ctl *ctx); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 95 | |
| 96 | /** |
| 97 | * Setup ctl_path interface config |
| 98 | * @ctx |
| 99 | * @cfg : interface config structure pointer |
| 100 | */ |
| 101 | void (*setup_intf_cfg)(struct sde_hw_ctl *ctx, |
| 102 | struct sde_hw_intf_cfg *cfg); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 103 | |
| 104 | int (*reset)(struct sde_hw_ctl *c); |
| 105 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 106 | uint32_t (*get_bitmask_sspp)(struct sde_hw_ctl *ctx, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 107 | enum sde_sspp blk); |
| 108 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 109 | uint32_t (*get_bitmask_mixer)(struct sde_hw_ctl *ctx, |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 110 | enum sde_lm blk); |
| 111 | |
| 112 | int (*get_bitmask_dspp)(struct sde_hw_ctl *ctx, |
| 113 | u32 *flushbits, |
| 114 | enum sde_dspp blk); |
| 115 | |
| 116 | int (*get_bitmask_intf)(struct sde_hw_ctl *ctx, |
| 117 | u32 *flushbits, |
| 118 | enum sde_intf blk); |
| 119 | |
| 120 | int (*get_bitmask_cdm)(struct sde_hw_ctl *ctx, |
| 121 | u32 *flushbits, |
| 122 | enum sde_cdm blk); |
| 123 | |
Alan Kwong | 3232ca5 | 2016-07-29 02:27:47 -0400 | [diff] [blame] | 124 | int (*get_bitmask_wb)(struct sde_hw_ctl *ctx, |
| 125 | u32 *flushbits, |
| 126 | enum sde_wb blk); |
| 127 | |
Lloyd Atkinson | e5ec30d | 2016-08-23 14:32:32 -0400 | [diff] [blame^] | 128 | /** |
| 129 | * Set all blend stages to disabled |
| 130 | * @ctx : ctl path ctx pointer |
| 131 | */ |
| 132 | void (*clear_all_blendstages)(struct sde_hw_ctl *ctx); |
| 133 | |
| 134 | /** |
| 135 | * Configure layer mixer to pipe configuration |
| 136 | * @ctx : ctl path ctx pointer |
| 137 | * @lm : layer mixer enumeration |
| 138 | * @cfg : blend stage configuration |
| 139 | */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 140 | void (*setup_blendstage)(struct sde_hw_ctl *ctx, |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 141 | enum sde_lm lm, struct sde_hw_stage_cfg *cfg, u32 index); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 142 | }; |
| 143 | |
| 144 | /** |
| 145 | * struct sde_hw_ctl : CTL PATH driver object |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 146 | * @hw: block register map object |
| 147 | * @idx: control path index |
| 148 | * @ctl_hw_caps: control path capabilities |
| 149 | * @mixer_count: number of mixers |
| 150 | * @mixer_hw_caps: mixer hardware capabilities |
| 151 | * @pending_flush_mask: storage for pending ctl_flush managed via ops |
| 152 | * @ops: operation list |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 153 | */ |
| 154 | struct sde_hw_ctl { |
| 155 | /* base */ |
| 156 | struct sde_hw_blk_reg_map hw; |
| 157 | |
| 158 | /* ctl path */ |
| 159 | int idx; |
| 160 | const struct sde_ctl_cfg *caps; |
| 161 | int mixer_count; |
| 162 | const struct sde_lm_cfg *mixer_hw_caps; |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 163 | u32 pending_flush_mask; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 164 | |
| 165 | /* ops */ |
| 166 | struct sde_hw_ctl_ops ops; |
| 167 | }; |
| 168 | |
| 169 | /** |
| 170 | * sde_hw_ctl_init(): Initializes the ctl_path hw driver object. |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 171 | * should be called before accessing every ctl path registers. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 172 | * @idx: ctl_path index for which driver object is required |
| 173 | * @addr: mapped register io address of MDP |
| 174 | * @m : pointer to mdss catalog data |
| 175 | */ |
| 176 | struct sde_hw_ctl *sde_hw_ctl_init(enum sde_ctl idx, |
| 177 | void __iomem *addr, |
| 178 | struct sde_mdss_cfg *m); |
| 179 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 180 | /** |
| 181 | * sde_hw_ctl_destroy(): Destroys ctl driver context |
| 182 | * should be called to free the context |
| 183 | */ |
| 184 | void sde_hw_ctl_destroy(struct sde_hw_ctl *ctx); |
| 185 | |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 186 | #endif /*_SDE_HW_CTL_H */ |