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Mike Marciniszyn77241052015-07-30 15:17:43 -04001#ifndef _HFI1_KERNEL_H
2#define _HFI1_KERNEL_H
3/*
Jubin John05d6ac12016-02-14 20:22:17 -08004 * Copyright(c) 2015, 2016 Intel Corporation.
Mike Marciniszyn77241052015-07-30 15:17:43 -04005 *
6 * This file is provided under a dual BSD/GPLv2 license. When using or
7 * redistributing this file, you may do so under either license.
8 *
9 * GPL LICENSE SUMMARY
10 *
Mike Marciniszyn77241052015-07-30 15:17:43 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * BSD LICENSE
21 *
Mike Marciniszyn77241052015-07-30 15:17:43 -040022 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions
24 * are met:
25 *
26 * - Redistributions of source code must retain the above copyright
27 * notice, this list of conditions and the following disclaimer.
28 * - Redistributions in binary form must reproduce the above copyright
29 * notice, this list of conditions and the following disclaimer in
30 * the documentation and/or other materials provided with the
31 * distribution.
32 * - Neither the name of Intel Corporation nor the names of its
33 * contributors may be used to endorse or promote products derived
34 * from this software without specific prior written permission.
35 *
36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
37 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
39 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
40 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
41 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
42 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
43 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
44 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
47 *
48 */
49
50#include <linux/interrupt.h>
51#include <linux/pci.h>
52#include <linux/dma-mapping.h>
53#include <linux/mutex.h>
54#include <linux/list.h>
55#include <linux/scatterlist.h>
56#include <linux/slab.h>
57#include <linux/io.h>
58#include <linux/fs.h>
59#include <linux/completion.h>
60#include <linux/kref.h>
61#include <linux/sched.h>
62#include <linux/cdev.h>
63#include <linux/delay.h>
64#include <linux/kthread.h>
Dean Luickdba715f2016-07-06 17:28:52 -040065#include <linux/i2c.h>
66#include <linux/i2c-algo-bit.h>
Dennis Dalessandroec3f2c12016-01-19 14:41:33 -080067#include <rdma/rdma_vt.h>
Mike Marciniszyn77241052015-07-30 15:17:43 -040068
69#include "chip_registers.h"
70#include "common.h"
71#include "verbs.h"
72#include "pio.h"
73#include "chip.h"
74#include "mad.h"
75#include "qsfp.h"
Easwar Hariharan8ebd4cf2016-02-03 14:31:14 -080076#include "platform.h"
Mitko Haralanov957558c2016-02-03 14:33:40 -080077#include "affinity.h"
Mike Marciniszyn77241052015-07-30 15:17:43 -040078
79/* bumped 1 from s/w major version of TrueScale */
80#define HFI1_CHIP_VERS_MAJ 3U
81
82/* don't care about this except printing */
83#define HFI1_CHIP_VERS_MIN 0U
84
85/* The Organization Unique Identifier (Mfg code), and its position in GUID */
86#define HFI1_OUI 0x001175
87#define HFI1_OUI_LSB 40
88
89#define DROP_PACKET_OFF 0
90#define DROP_PACKET_ON 1
91
92extern unsigned long hfi1_cap_mask;
93#define HFI1_CAP_KGET_MASK(mask, cap) ((mask) & HFI1_CAP_##cap)
94#define HFI1_CAP_UGET_MASK(mask, cap) \
95 (((mask) >> HFI1_CAP_USER_SHIFT) & HFI1_CAP_##cap)
96#define HFI1_CAP_KGET(cap) (HFI1_CAP_KGET_MASK(hfi1_cap_mask, cap))
97#define HFI1_CAP_UGET(cap) (HFI1_CAP_UGET_MASK(hfi1_cap_mask, cap))
98#define HFI1_CAP_IS_KSET(cap) (!!HFI1_CAP_KGET(cap))
99#define HFI1_CAP_IS_USET(cap) (!!HFI1_CAP_UGET(cap))
100#define HFI1_MISC_GET() ((hfi1_cap_mask >> HFI1_CAP_MISC_SHIFT) & \
101 HFI1_CAP_MISC_MASK)
Bryan Morgana9c05e32016-02-03 14:30:49 -0800102/* Offline Disabled Reason is 4-bits */
103#define HFI1_ODR_MASK(rsn) ((rsn) & OPA_PI_MASK_OFFLINE_REASON)
Mike Marciniszyn77241052015-07-30 15:17:43 -0400104
105/*
Niranjana Vishwanathapura82c26112015-11-11 00:35:19 -0500106 * Control context is always 0 and handles the error packets.
107 * It also handles the VL15 and multicast packets.
108 */
109#define HFI1_CTRL_CTXT 0
110
111/*
Joel Rosenzweig2c5b5212015-12-01 15:38:19 -0500112 * Driver context will store software counters for each of the events
113 * associated with these status registers
114 */
115#define NUM_CCE_ERR_STATUS_COUNTERS 41
116#define NUM_RCV_ERR_STATUS_COUNTERS 64
117#define NUM_MISC_ERR_STATUS_COUNTERS 13
118#define NUM_SEND_PIO_ERR_STATUS_COUNTERS 36
119#define NUM_SEND_DMA_ERR_STATUS_COUNTERS 4
120#define NUM_SEND_EGRESS_ERR_STATUS_COUNTERS 64
121#define NUM_SEND_ERR_STATUS_COUNTERS 3
122#define NUM_SEND_CTXT_ERR_STATUS_COUNTERS 5
123#define NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS 24
124
125/*
Mike Marciniszyn77241052015-07-30 15:17:43 -0400126 * per driver stats, either not device nor port-specific, or
127 * summed over all of the devices and ports.
128 * They are described by name via ipathfs filesystem, so layout
129 * and number of elements can change without breaking compatibility.
130 * If members are added or deleted hfi1_statnames[] in debugfs.c must
131 * change to match.
132 */
133struct hfi1_ib_stats {
134 __u64 sps_ints; /* number of interrupts handled */
135 __u64 sps_errints; /* number of error interrupts */
136 __u64 sps_txerrs; /* tx-related packet errors */
137 __u64 sps_rcverrs; /* non-crc rcv packet errors */
138 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */
139 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */
140 __u64 sps_ctxts; /* number of contexts currently open */
141 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */
142 __u64 sps_buffull;
143 __u64 sps_hdrfull;
144};
145
146extern struct hfi1_ib_stats hfi1_stats;
147extern const struct pci_error_handlers hfi1_pci_err_handler;
148
149/*
150 * First-cut criterion for "device is active" is
151 * two thousand dwords combined Tx, Rx traffic per
152 * 5-second interval. SMA packets are 64 dwords,
153 * and occur "a few per second", presumably each way.
154 */
155#define HFI1_TRAFFIC_ACTIVE_THRESHOLD (2000)
156
157/*
158 * Below contains all data related to a single context (formerly called port).
159 */
160
161#ifdef CONFIG_DEBUG_FS
162struct hfi1_opcode_stats_perctx;
163#endif
164
Mike Marciniszyn77241052015-07-30 15:17:43 -0400165struct ctxt_eager_bufs {
166 ssize_t size; /* total size of eager buffers */
167 u32 count; /* size of buffers array */
168 u32 numbufs; /* number of buffers allocated */
169 u32 alloced; /* number of rcvarray entries used */
170 u32 rcvtid_size; /* size of each eager rcv tid */
171 u32 threshold; /* head update threshold */
172 struct eager_buffer {
173 void *addr;
174 dma_addr_t phys;
175 ssize_t len;
176 } *buffers;
177 struct {
178 void *addr;
179 dma_addr_t phys;
180 } *rcvtids;
181};
182
Mitko Haralanova86cd352016-02-05 11:57:49 -0500183struct exp_tid_set {
184 struct list_head list;
185 u32 count;
186};
187
Mike Marciniszyn77241052015-07-30 15:17:43 -0400188struct hfi1_ctxtdata {
189 /* shadow the ctxt's RcvCtrl register */
190 u64 rcvctrl;
191 /* rcvhdrq base, needs mmap before useful */
192 void *rcvhdrq;
193 /* kernel virtual address where hdrqtail is updated */
194 volatile __le64 *rcvhdrtail_kvaddr;
195 /*
196 * Shared page for kernel to signal user processes that send buffers
197 * need disarming. The process should call HFI1_CMD_DISARM_BUFS
198 * or HFI1_CMD_ACK_EVENT with IPATH_EVENT_DISARM_BUFS set.
199 */
200 unsigned long *user_event_mask;
201 /* when waiting for rcv or pioavail */
202 wait_queue_head_t wait;
203 /* rcvhdrq size (for freeing) */
204 size_t rcvhdrq_size;
205 /* number of rcvhdrq entries */
206 u16 rcvhdrq_cnt;
207 /* size of each of the rcvhdrq entries */
208 u16 rcvhdrqentsize;
209 /* mmap of hdrq, must fit in 44 bits */
210 dma_addr_t rcvhdrq_phys;
211 dma_addr_t rcvhdrqtailaddr_phys;
212 struct ctxt_eager_bufs egrbufs;
213 /* this receive context's assigned PIO ACK send context */
214 struct send_context *sc;
215
216 /* dynamic receive available interrupt timeout */
217 u32 rcvavail_timeout;
218 /*
219 * number of opens (including slave sub-contexts) on this instance
220 * (ignoring forks, dup, etc. for now)
221 */
222 int cnt;
223 /*
224 * how much space to leave at start of eager TID entries for
225 * protocol use, on each TID
226 */
227 /* instead of calculating it */
228 unsigned ctxt;
229 /* non-zero if ctxt is being shared. */
230 u16 subctxt_cnt;
231 /* non-zero if ctxt is being shared. */
232 u16 subctxt_id;
233 u8 uuid[16];
234 /* job key */
235 u16 jkey;
236 /* number of RcvArray groups for this context. */
237 u32 rcv_array_groups;
238 /* index of first eager TID entry. */
239 u32 eager_base;
240 /* number of expected TID entries */
241 u32 expected_count;
242 /* index of first expected TID entry. */
243 u32 expected_base;
Mitko Haralanova86cd352016-02-05 11:57:49 -0500244
245 struct exp_tid_set tid_group_list;
246 struct exp_tid_set tid_used_list;
247 struct exp_tid_set tid_full_list;
248
Mike Marciniszyn77241052015-07-30 15:17:43 -0400249 /* lock protecting all Expected TID data */
Mitko Haralanov463e6eb2016-02-05 11:57:53 -0500250 struct mutex exp_lock;
Mike Marciniszyn77241052015-07-30 15:17:43 -0400251 /* number of pio bufs for this ctxt (all procs, if shared) */
252 u32 piocnt;
253 /* first pio buffer for this ctxt */
254 u32 pio_base;
255 /* chip offset of PIO buffers for this ctxt */
256 u32 piobufs;
257 /* per-context configuration flags */
Dean Luickbdf77522016-07-28 15:21:13 -0400258 unsigned long flags;
Mike Marciniszyn77241052015-07-30 15:17:43 -0400259 /* per-context event flags for fileops/intr communication */
260 unsigned long event_flags;
261 /* WAIT_RCV that timed out, no interrupt */
262 u32 rcvwait_to;
263 /* WAIT_PIO that timed out, no interrupt */
264 u32 piowait_to;
265 /* WAIT_RCV already happened, no wait */
266 u32 rcvnowait;
267 /* WAIT_PIO already happened, no wait */
268 u32 pionowait;
269 /* total number of polled urgent packets */
270 u32 urgent;
271 /* saved total number of polled urgent packets for poll edge trigger */
272 u32 urgent_poll;
Mike Marciniszyn77241052015-07-30 15:17:43 -0400273 /* same size as task_struct .comm[], command that opened context */
Geliang Tangc3af8a22015-10-08 22:04:26 -0700274 char comm[TASK_COMM_LEN];
Mike Marciniszyn77241052015-07-30 15:17:43 -0400275 /* so file ops can get at unit */
276 struct hfi1_devdata *dd;
277 /* so functions that need physical port can get it easily */
278 struct hfi1_pportdata *ppd;
279 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */
280 void *subctxt_uregbase;
281 /* An array of pages for the eager receive buffers * N */
282 void *subctxt_rcvegrbuf;
283 /* An array of pages for the eager header queue entries * N */
284 void *subctxt_rcvhdr_base;
285 /* The version of the library which opened this ctxt */
286 u32 userversion;
287 /* Bitmask of active slaves */
288 u32 active_slaves;
289 /* Type of packets or conditions we want to poll for */
290 u16 poll_type;
291 /* receive packet sequence counter */
292 u8 seq_cnt;
293 u8 redirect_seq_cnt;
294 /* ctxt rcvhdrq head offset */
295 u32 head;
296 u32 pkt_count;
297 /* QPs waiting for context processing */
298 struct list_head qp_wait_list;
299 /* interrupt handling */
300 u64 imask; /* clear interrupt mask */
301 int ireg; /* clear interrupt register */
302 unsigned numa_id; /* numa node of this context */
303 /* verbs stats per CTX */
304 struct hfi1_opcode_stats_perctx *opstats;
305 /*
306 * This is the kernel thread that will keep making
307 * progress on the user sdma requests behind the scenes.
308 * There is one per context (shared contexts use the master's).
309 */
310 struct task_struct *progress;
311 struct list_head sdma_queues;
Jubin John6a14c5e2016-02-14 20:21:34 -0800312 /* protect sdma queues */
Mike Marciniszyn77241052015-07-30 15:17:43 -0400313 spinlock_t sdma_qlock;
314
Ashutosh Dixitaffa48d2016-02-03 14:33:06 -0800315 /* Is ASPM interrupt supported for this context */
316 bool aspm_intr_supported;
317 /* ASPM state (enabled/disabled) for this context */
318 bool aspm_enabled;
319 /* Timer for re-enabling ASPM if interrupt activity quietens down */
320 struct timer_list aspm_timer;
321 /* Lock to serialize between intr, timer intr and user threads */
322 spinlock_t aspm_lock;
323 /* Is ASPM processing enabled for this context (in intr context) */
324 bool aspm_intr_enable;
325 /* Last interrupt timestamp */
326 ktime_t aspm_ts_last_intr;
327 /* Last timestamp at which we scheduled a timer for this context */
328 ktime_t aspm_ts_timer_sched;
329
Mike Marciniszyn77241052015-07-30 15:17:43 -0400330 /*
331 * The interrupt handler for a particular receive context can vary
332 * throughout it's lifetime. This is not a lock protected data member so
333 * it must be updated atomically and the prev and new value must always
334 * be valid. Worst case is we process an extra interrupt and up to 64
335 * packets with the wrong interrupt handler.
336 */
Dean Luickf4f30031c2015-10-26 10:28:44 -0400337 int (*do_interrupt)(struct hfi1_ctxtdata *rcd, int threaded);
Mike Marciniszyn77241052015-07-30 15:17:43 -0400338};
339
340/*
341 * Represents a single packet at a high level. Put commonly computed things in
342 * here so we do not have to keep doing them over and over. The rule of thumb is
343 * if something is used one time to derive some value, store that something in
344 * here. If it is used multiple times, then store the result of that derivation
345 * in here.
346 */
347struct hfi1_packet {
348 void *ebuf;
349 void *hdr;
350 struct hfi1_ctxtdata *rcd;
351 __le32 *rhf_addr;
Dennis Dalessandro895420d2016-01-19 14:42:28 -0800352 struct rvt_qp *qp;
Mike Marciniszyn77241052015-07-30 15:17:43 -0400353 struct hfi1_other_headers *ohdr;
354 u64 rhf;
355 u32 maxcnt;
356 u32 rhqoff;
357 u32 hdrqtail;
358 int numpkt;
359 u16 tlen;
360 u16 hlen;
361 s16 etail;
362 u16 rsize;
363 u8 updegr;
364 u8 rcv_flags;
365 u8 etype;
366};
367
Mike Marciniszyn77241052015-07-30 15:17:43 -0400368/*
369 * Private data for snoop/capture support.
370 */
371struct hfi1_snoop_data {
372 int mode_flag;
373 struct cdev cdev;
374 struct device *class_dev;
Jubin John6a14c5e2016-02-14 20:21:34 -0800375 /* protect snoop data */
Mike Marciniszyn77241052015-07-30 15:17:43 -0400376 spinlock_t snoop_lock;
377 struct list_head queue;
378 wait_queue_head_t waitq;
379 void *filter_value;
380 int (*filter_callback)(void *hdr, void *data, void *value);
381 u64 dcc_cfg; /* saved value of DCC Cfg register */
382};
383
384/* snoop mode_flag values */
385#define HFI1_PORT_SNOOP_MODE 1U
386#define HFI1_PORT_CAPTURE_MODE 2U
387
Dennis Dalessandro895420d2016-01-19 14:42:28 -0800388struct rvt_sge_state;
Mike Marciniszyn77241052015-07-30 15:17:43 -0400389
390/*
391 * Get/Set IB link-level config parameters for f_get/set_ib_cfg()
392 * Mostly for MADs that set or query link parameters, also ipath
393 * config interfaces
394 */
395#define HFI1_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */
396#define HFI1_IB_CFG_LWID_DG_ENB 1 /* allowed Link-width downgrade */
397#define HFI1_IB_CFG_LWID_ENB 2 /* allowed Link-width */
398#define HFI1_IB_CFG_LWID 3 /* currently active Link-width */
399#define HFI1_IB_CFG_SPD_ENB 4 /* allowed Link speeds */
400#define HFI1_IB_CFG_SPD 5 /* current Link spd */
401#define HFI1_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */
402#define HFI1_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */
403#define HFI1_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */
404#define HFI1_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */
405#define HFI1_IB_CFG_OP_VLS 10 /* operational VLs */
406#define HFI1_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */
407#define HFI1_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */
408#define HFI1_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */
409#define HFI1_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */
410#define HFI1_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */
411#define HFI1_IB_CFG_PKEYS 16 /* update partition keys */
412#define HFI1_IB_CFG_MTU 17 /* update MTU in IBC */
413#define HFI1_IB_CFG_VL_HIGH_LIMIT 19
414#define HFI1_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */
415#define HFI1_IB_CFG_PORT 21 /* switch port we are connected to */
416
417/*
418 * HFI or Host Link States
419 *
420 * These describe the states the driver thinks the logical and physical
421 * states are in. Used as an argument to set_link_state(). Implemented
422 * as bits for easy multi-state checking. The actual state can only be
423 * one.
424 */
425#define __HLS_UP_INIT_BP 0
426#define __HLS_UP_ARMED_BP 1
427#define __HLS_UP_ACTIVE_BP 2
428#define __HLS_DN_DOWNDEF_BP 3 /* link down default */
429#define __HLS_DN_POLL_BP 4
430#define __HLS_DN_DISABLE_BP 5
431#define __HLS_DN_OFFLINE_BP 6
432#define __HLS_VERIFY_CAP_BP 7
433#define __HLS_GOING_UP_BP 8
434#define __HLS_GOING_OFFLINE_BP 9
435#define __HLS_LINK_COOLDOWN_BP 10
436
jubin.john@intel.com349ac712016-01-11 18:30:52 -0500437#define HLS_UP_INIT BIT(__HLS_UP_INIT_BP)
438#define HLS_UP_ARMED BIT(__HLS_UP_ARMED_BP)
439#define HLS_UP_ACTIVE BIT(__HLS_UP_ACTIVE_BP)
440#define HLS_DN_DOWNDEF BIT(__HLS_DN_DOWNDEF_BP) /* link down default */
441#define HLS_DN_POLL BIT(__HLS_DN_POLL_BP)
442#define HLS_DN_DISABLE BIT(__HLS_DN_DISABLE_BP)
443#define HLS_DN_OFFLINE BIT(__HLS_DN_OFFLINE_BP)
444#define HLS_VERIFY_CAP BIT(__HLS_VERIFY_CAP_BP)
445#define HLS_GOING_UP BIT(__HLS_GOING_UP_BP)
446#define HLS_GOING_OFFLINE BIT(__HLS_GOING_OFFLINE_BP)
447#define HLS_LINK_COOLDOWN BIT(__HLS_LINK_COOLDOWN_BP)
Mike Marciniszyn77241052015-07-30 15:17:43 -0400448
449#define HLS_UP (HLS_UP_INIT | HLS_UP_ARMED | HLS_UP_ACTIVE)
Easwar Hariharan0c7f77a2016-05-12 10:22:33 -0700450#define HLS_DOWN ~(HLS_UP)
Mike Marciniszyn77241052015-07-30 15:17:43 -0400451
452/* use this MTU size if none other is given */
Sebastian Sanchezef699e82016-04-12 11:17:09 -0700453#define HFI1_DEFAULT_ACTIVE_MTU 10240
Mike Marciniszyn77241052015-07-30 15:17:43 -0400454/* use this MTU size as the default maximum */
Sebastian Sanchezef699e82016-04-12 11:17:09 -0700455#define HFI1_DEFAULT_MAX_MTU 10240
Mike Marciniszyn77241052015-07-30 15:17:43 -0400456/* default partition key */
457#define DEFAULT_PKEY 0xffff
458
459/*
460 * Possible fabric manager config parameters for fm_{get,set}_table()
461 */
462#define FM_TBL_VL_HIGH_ARB 1 /* Get/set VL high prio weights */
463#define FM_TBL_VL_LOW_ARB 2 /* Get/set VL low prio weights */
464#define FM_TBL_BUFFER_CONTROL 3 /* Get/set Buffer Control */
465#define FM_TBL_SC2VLNT 4 /* Get/set SC->VLnt */
466#define FM_TBL_VL_PREEMPT_ELEMS 5 /* Get (no set) VL preempt elems */
467#define FM_TBL_VL_PREEMPT_MATRIX 6 /* Get (no set) VL preempt matrix */
468
469/*
470 * Possible "operations" for f_rcvctrl(ppd, op, ctxt)
471 * these are bits so they can be combined, e.g.
472 * HFI1_RCVCTRL_INTRAVAIL_ENB | HFI1_RCVCTRL_CTXT_ENB
473 */
474#define HFI1_RCVCTRL_TAILUPD_ENB 0x01
475#define HFI1_RCVCTRL_TAILUPD_DIS 0x02
476#define HFI1_RCVCTRL_CTXT_ENB 0x04
477#define HFI1_RCVCTRL_CTXT_DIS 0x08
478#define HFI1_RCVCTRL_INTRAVAIL_ENB 0x10
479#define HFI1_RCVCTRL_INTRAVAIL_DIS 0x20
480#define HFI1_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */
481#define HFI1_RCVCTRL_PKEY_DIS 0x80
482#define HFI1_RCVCTRL_TIDFLOW_ENB 0x0400
483#define HFI1_RCVCTRL_TIDFLOW_DIS 0x0800
484#define HFI1_RCVCTRL_ONE_PKT_EGR_ENB 0x1000
485#define HFI1_RCVCTRL_ONE_PKT_EGR_DIS 0x2000
486#define HFI1_RCVCTRL_NO_RHQ_DROP_ENB 0x4000
487#define HFI1_RCVCTRL_NO_RHQ_DROP_DIS 0x8000
488#define HFI1_RCVCTRL_NO_EGR_DROP_ENB 0x10000
489#define HFI1_RCVCTRL_NO_EGR_DROP_DIS 0x20000
490
491/* partition enforcement flags */
492#define HFI1_PART_ENFORCE_IN 0x1
493#define HFI1_PART_ENFORCE_OUT 0x2
494
495/* how often we check for synthetic counter wrap around */
496#define SYNTH_CNT_TIME 2
497
498/* Counter flags */
499#define CNTR_NORMAL 0x0 /* Normal counters, just read register */
500#define CNTR_SYNTH 0x1 /* Synthetic counters, saturate at all 1s */
501#define CNTR_DISABLED 0x2 /* Disable this counter */
502#define CNTR_32BIT 0x4 /* Simulate 64 bits for this counter */
503#define CNTR_VL 0x8 /* Per VL counter */
Vennila Megavannana699c6c2016-01-11 18:30:56 -0500504#define CNTR_SDMA 0x10
Mike Marciniszyn77241052015-07-30 15:17:43 -0400505#define CNTR_INVALID_VL -1 /* Specifies invalid VL */
506#define CNTR_MODE_W 0x0
507#define CNTR_MODE_R 0x1
508
509/* VLs Supported/Operational */
510#define HFI1_MIN_VLS_SUPPORTED 1
511#define HFI1_MAX_VLS_SUPPORTED 8
512
513static inline void incr_cntr64(u64 *cntr)
514{
515 if (*cntr < (u64)-1LL)
516 (*cntr)++;
517}
518
519static inline void incr_cntr32(u32 *cntr)
520{
521 if (*cntr < (u32)-1LL)
522 (*cntr)++;
523}
524
525#define MAX_NAME_SIZE 64
526struct hfi1_msix_entry {
Mitko Haralanov957558c2016-02-03 14:33:40 -0800527 enum irq_type type;
Mike Marciniszyn77241052015-07-30 15:17:43 -0400528 struct msix_entry msix;
529 void *arg;
530 char name[MAX_NAME_SIZE];
Mitko Haralanov957558c2016-02-03 14:33:40 -0800531 cpumask_t mask;
Mike Marciniszyn77241052015-07-30 15:17:43 -0400532};
533
534/* per-SL CCA information */
535struct cca_timer {
536 struct hrtimer hrtimer;
537 struct hfi1_pportdata *ppd; /* read-only */
538 int sl; /* read-only */
539 u16 ccti; /* read/write - current value of CCTI */
540};
541
542struct link_down_reason {
543 /*
544 * SMA-facing value. Should be set from .latest when
545 * HLS_UP_* -> HLS_DN_* transition actually occurs.
546 */
547 u8 sma;
548 u8 latest;
549};
550
551enum {
552 LO_PRIO_TABLE,
553 HI_PRIO_TABLE,
554 MAX_PRIO_TABLE
555};
556
557struct vl_arb_cache {
Jubin John6a14c5e2016-02-14 20:21:34 -0800558 /* protect vl arb cache */
Mike Marciniszyn77241052015-07-30 15:17:43 -0400559 spinlock_t lock;
560 struct ib_vl_weight_elem table[VL_ARB_TABLE_SIZE];
561};
562
563/*
564 * The structure below encapsulates data relevant to a physical IB Port.
565 * Current chips support only one such port, but the separation
566 * clarifies things a bit. Note that to conform to IB conventions,
567 * port-numbers are one-based. The first or only port is port1.
568 */
569struct hfi1_pportdata {
570 struct hfi1_ibport ibport_data;
571
572 struct hfi1_devdata *dd;
573 struct kobject pport_cc_kobj;
574 struct kobject sc2vl_kobj;
575 struct kobject sl2sc_kobj;
576 struct kobject vl2mtu_kobj;
577
Easwar Hariharan8ebd4cf2016-02-03 14:31:14 -0800578 /* PHY support */
579 u32 port_type;
Mike Marciniszyn77241052015-07-30 15:17:43 -0400580 struct qsfp_data qsfp_info;
581
582 /* GUID for this interface, in host order */
583 u64 guid;
584 /* GUID for peer interface, in host order */
585 u64 neighbor_guid;
586
587 /* up or down physical link state */
588 u32 linkup;
589
590 /*
591 * this address is mapped read-only into user processes so they can
592 * get status cheaply, whenever they want. One qword of status per port
593 */
594 u64 *statusp;
595
596 /* SendDMA related entries */
597
598 struct workqueue_struct *hfi1_wq;
599
600 /* move out of interrupt context */
601 struct work_struct link_vc_work;
602 struct work_struct link_up_work;
603 struct work_struct link_down_work;
604 struct work_struct sma_message_work;
605 struct work_struct freeze_work;
606 struct work_struct link_downgrade_work;
607 struct work_struct link_bounce_work;
Dean Luick673b9752016-08-31 07:24:33 -0700608 struct delayed_work start_link_work;
Mike Marciniszyn77241052015-07-30 15:17:43 -0400609 /* host link state variables */
610 struct mutex hls_lock;
611 u32 host_link_state;
612
613 spinlock_t sdma_alllock ____cacheline_aligned_in_smp;
614
615 u32 lstate; /* logical link state */
616
617 /* these are the "32 bit" regs */
618
619 u32 ibmtu; /* The MTU programmed for this unit */
620 /*
621 * Current max size IB packet (in bytes) including IB headers, that
622 * we can send. Changes when ibmtu changes.
623 */
624 u32 ibmaxlen;
625 u32 current_egress_rate; /* units [10^6 bits/sec] */
626 /* LID programmed for this instance */
627 u16 lid;
628 /* list of pkeys programmed; 0 if not set */
629 u16 pkeys[MAX_PKEY_VALUES];
630 u16 link_width_supported;
631 u16 link_width_downgrade_supported;
632 u16 link_speed_supported;
633 u16 link_width_enabled;
634 u16 link_width_downgrade_enabled;
635 u16 link_speed_enabled;
636 u16 link_width_active;
637 u16 link_width_downgrade_tx_active;
638 u16 link_width_downgrade_rx_active;
639 u16 link_speed_active;
640 u8 vls_supported;
641 u8 vls_operational;
Mike Marciniszyn8a4d3442016-02-14 12:46:01 -0800642 u8 actual_vls_operational;
Mike Marciniszyn77241052015-07-30 15:17:43 -0400643 /* LID mask control */
644 u8 lmc;
645 /* Rx Polarity inversion (compensate for ~tx on partner) */
646 u8 rx_pol_inv;
647
648 u8 hw_pidx; /* physical port index */
649 u8 port; /* IB port number and index into dd->pports - 1 */
650 /* type of neighbor node */
651 u8 neighbor_type;
652 u8 neighbor_normal;
653 u8 neighbor_fm_security; /* 1 if firmware checking is disabled */
654 u8 neighbor_port_number;
655 u8 is_sm_config_started;
656 u8 offline_disabled_reason;
657 u8 is_active_optimize_enabled;
658 u8 driver_link_ready; /* driver ready for active link */
659 u8 link_enabled; /* link enabled? */
660 u8 linkinit_reason;
661 u8 local_tx_rate; /* rate given to 8051 firmware */
Dean Luickf45c8dc2016-02-03 14:35:31 -0800662 u8 last_pstate; /* info only */
Dean Luick673b9752016-08-31 07:24:33 -0700663 u8 qsfp_retry_count;
Mike Marciniszyn77241052015-07-30 15:17:43 -0400664
665 /* placeholders for IB MAD packet settings */
666 u8 overrun_threshold;
667 u8 phy_error_threshold;
668
Easwar Hariharan91ab4ed2016-02-03 14:35:57 -0800669 /* Used to override LED behavior for things like maintenance beaconing*/
670 /*
671 * Alternates per phase of blink
672 * [0] holds LED off duration, [1] holds LED on duration
673 */
674 unsigned long led_override_vals[2];
675 u8 led_override_phase; /* LSB picks from vals[] */
Mike Marciniszyn77241052015-07-30 15:17:43 -0400676 atomic_t led_override_timer_active;
677 /* Used to flash LEDs in override mode */
678 struct timer_list led_override_timer;
Easwar Hariharan91ab4ed2016-02-03 14:35:57 -0800679
Mike Marciniszyn77241052015-07-30 15:17:43 -0400680 u32 sm_trap_qp;
681 u32 sa_qp;
682
683 /*
684 * cca_timer_lock protects access to the per-SL cca_timer
685 * structures (specifically the ccti member).
686 */
687 spinlock_t cca_timer_lock ____cacheline_aligned_in_smp;
688 struct cca_timer cca_timer[OPA_MAX_SLS];
689
690 /* List of congestion control table entries */
691 struct ib_cc_table_entry_shadow ccti_entries[CC_TABLE_SHADOW_MAX];
692
693 /* congestion entries, each entry corresponding to a SL */
694 struct opa_congestion_setting_entry_shadow
695 congestion_entries[OPA_MAX_SLS];
696
697 /*
698 * cc_state_lock protects (write) access to the per-port
699 * struct cc_state.
700 */
701 spinlock_t cc_state_lock ____cacheline_aligned_in_smp;
702
703 struct cc_state __rcu *cc_state;
704
705 /* Total number of congestion control table entries */
706 u16 total_cct_entry;
707
708 /* Bit map identifying service level */
709 u32 cc_sl_control_map;
710
711 /* CA's max number of 64 entry units in the congestion control table */
712 u8 cc_max_table_entries;
713
Jubin John4d114fd2016-02-14 20:21:43 -0800714 /*
715 * begin congestion log related entries
716 * cc_log_lock protects all congestion log related data
717 */
Mike Marciniszyn77241052015-07-30 15:17:43 -0400718 spinlock_t cc_log_lock ____cacheline_aligned_in_smp;
Jubin John8638b772016-02-14 20:19:24 -0800719 u8 threshold_cong_event_map[OPA_MAX_SLS / 8];
Mike Marciniszyn77241052015-07-30 15:17:43 -0400720 u16 threshold_event_counter;
721 struct opa_hfi1_cong_log_event_internal cc_events[OPA_CONG_LOG_ELEMS];
722 int cc_log_idx; /* index for logging events */
723 int cc_mad_idx; /* index for reporting events */
724 /* end congestion log related entries */
725
726 struct vl_arb_cache vl_arb_cache[MAX_PRIO_TABLE];
727
728 /* port relative counter buffer */
729 u64 *cntrs;
730 /* port relative synthetic counter buffer */
731 u64 *scntrs;
Mike Marciniszyn69a00b82016-02-03 14:31:49 -0800732 /* port_xmit_discards are synthesized from different egress errors */
Mike Marciniszyn77241052015-07-30 15:17:43 -0400733 u64 port_xmit_discards;
Mike Marciniszyn69a00b82016-02-03 14:31:49 -0800734 u64 port_xmit_discards_vl[C_VL_COUNT];
Mike Marciniszyn77241052015-07-30 15:17:43 -0400735 u64 port_xmit_constraint_errors;
736 u64 port_rcv_constraint_errors;
737 /* count of 'link_err' interrupts from DC */
738 u64 link_downed;
739 /* number of times link retrained successfully */
740 u64 link_up;
Dean Luick6d014532015-12-01 15:38:23 -0500741 /* number of times a link unknown frame was reported */
742 u64 unknown_frame_count;
Mike Marciniszyn77241052015-07-30 15:17:43 -0400743 /* port_ltp_crc_mode is returned in 'portinfo' MADs */
744 u16 port_ltp_crc_mode;
745 /* port_crc_mode_enabled is the crc we support */
746 u8 port_crc_mode_enabled;
747 /* mgmt_allowed is also returned in 'portinfo' MADs */
748 u8 mgmt_allowed;
749 u8 part_enforce; /* partition enforcement flags */
750 struct link_down_reason local_link_down_reason;
751 struct link_down_reason neigh_link_down_reason;
752 /* Value to be sent to link peer on LinkDown .*/
753 u8 remote_link_down_reason;
754 /* Error events that will cause a port bounce. */
755 u32 port_error_action;
Jim Snowfb9036d2016-01-11 18:32:21 -0500756 struct work_struct linkstate_active_work;
Vennila Megavannan6c9e50f2016-02-03 14:32:57 -0800757 /* Does this port need to prescan for FECNs */
758 bool cc_prescan;
Mike Marciniszyn77241052015-07-30 15:17:43 -0400759};
760
761typedef int (*rhf_rcv_function_ptr)(struct hfi1_packet *packet);
762
763typedef void (*opcode_handler)(struct hfi1_packet *packet);
764
765/* return values for the RHF receive functions */
766#define RHF_RCV_CONTINUE 0 /* keep going */
767#define RHF_RCV_DONE 1 /* stop, this packet processed */
768#define RHF_RCV_REPROCESS 2 /* stop. retain this packet */
769
770struct rcv_array_data {
771 u8 group_size;
772 u16 ngroups;
773 u16 nctxt_extra;
774};
775
776struct per_vl_data {
777 u16 mtu;
778 struct send_context *sc;
779};
780
781/* 16 to directly index */
782#define PER_VL_SEND_CONTEXTS 16
783
784struct err_info_rcvport {
785 u8 status_and_code;
786 u64 packet_flit1;
787 u64 packet_flit2;
788};
789
790struct err_info_constraint {
791 u8 status;
792 u16 pkey;
793 u32 slid;
794};
795
796struct hfi1_temp {
797 unsigned int curr; /* current temperature */
798 unsigned int lo_lim; /* low temperature limit */
799 unsigned int hi_lim; /* high temperature limit */
800 unsigned int crit_lim; /* critical temperature limit */
801 u8 triggers; /* temperature triggers */
802};
803
Dean Luickdba715f2016-07-06 17:28:52 -0400804struct hfi1_i2c_bus {
805 struct hfi1_devdata *controlling_dd; /* current controlling device */
806 struct i2c_adapter adapter; /* bus details */
807 struct i2c_algo_bit_data algo; /* bus algorithm details */
808 int num; /* bus number, 0 or 1 */
809};
810
Dean Luick78eb1292016-03-05 08:49:45 -0800811/* common data between shared ASIC HFIs */
812struct hfi1_asic_data {
813 struct hfi1_devdata *dds[2]; /* back pointers */
814 struct mutex asic_resource_mutex;
Dean Luickdba715f2016-07-06 17:28:52 -0400815 struct hfi1_i2c_bus *i2c_bus0;
816 struct hfi1_i2c_bus *i2c_bus1;
Dean Luick78eb1292016-03-05 08:49:45 -0800817};
818
Mike Marciniszyn77241052015-07-30 15:17:43 -0400819/* device data struct now contains only "general per-device" info.
820 * fields related to a physical IB port are in a hfi1_pportdata struct.
821 */
822struct sdma_engine;
823struct sdma_vl_map;
824
825#define BOARD_VERS_MAX 96 /* how long the version string can be */
826#define SERIAL_MAX 16 /* length of the serial number */
827
Mike Marciniszyn14553ca2016-02-14 12:45:36 -0800828typedef int (*send_routine)(struct rvt_qp *, struct hfi1_pkt_state *, u64);
Mike Marciniszyn77241052015-07-30 15:17:43 -0400829struct hfi1_devdata {
830 struct hfi1_ibdev verbs_dev; /* must be first */
831 struct list_head list;
832 /* pointers to related structs for this device */
833 /* pci access data structure */
834 struct pci_dev *pcidev;
835 struct cdev user_cdev;
836 struct cdev diag_cdev;
837 struct cdev ui_cdev;
838 struct device *user_device;
839 struct device *diag_device;
840 struct device *ui_device;
841
842 /* mem-mapped pointer to base of chip regs */
843 u8 __iomem *kregbase;
844 /* end of mem-mapped chip space excluding sendbuf and user regs */
845 u8 __iomem *kregend;
846 /* physical address of chip for io_remap, etc. */
847 resource_size_t physaddr;
848 /* receive context data */
849 struct hfi1_ctxtdata **rcd;
850 /* send context data */
851 struct send_context_info *send_contexts;
852 /* map hardware send contexts to software index */
853 u8 *hw_to_sw;
854 /* spinlock for allocating and releasing send context resources */
855 spinlock_t sc_lock;
856 /* Per VL data. Enough for all VLs but not all elements are set/used. */
857 struct per_vl_data vld[PER_VL_SEND_CONTEXTS];
Jubin John35f6bef2016-02-14 12:46:10 -0800858 /* lock for pio_map */
859 spinlock_t pio_map_lock;
860 /* array of kernel send contexts */
861 struct send_context **kernel_send_context;
862 /* array of vl maps */
863 struct pio_vl_map __rcu *pio_map;
Mike Marciniszyn77241052015-07-30 15:17:43 -0400864 /* seqlock for sc2vl */
865 seqlock_t sc2vl_lock;
866 u64 sc2vl[4];
867 /* Send Context initialization lock. */
868 spinlock_t sc_init_lock;
869
870 /* fields common to all SDMA engines */
871
872 /* default flags to last descriptor */
873 u64 default_desc1;
874 volatile __le64 *sdma_heads_dma; /* DMA'ed by chip */
875 dma_addr_t sdma_heads_phys;
876 void *sdma_pad_dma; /* DMA'ed by chip */
877 dma_addr_t sdma_pad_phys;
878 /* for deallocation */
879 size_t sdma_heads_size;
880 /* number from the chip */
881 u32 chip_sdma_engines;
882 /* num used */
883 u32 num_sdma;
884 /* lock for sdma_map */
885 spinlock_t sde_map_lock;
886 /* array of engines sized by num_sdma */
887 struct sdma_engine *per_sdma;
888 /* array of vl maps */
889 struct sdma_vl_map __rcu *sdma_map;
890 /* SPC freeze waitqueue and variable */
891 wait_queue_head_t sdma_unfreeze_wq;
892 atomic_t sdma_unfreeze_count;
893
Dean Luick78eb1292016-03-05 08:49:45 -0800894 /* common data between shared ASIC HFIs in this OS */
895 struct hfi1_asic_data *asic_data;
896
Mike Marciniszyn77241052015-07-30 15:17:43 -0400897 /* hfi1_pportdata, points to array of (physical) port-specific
898 * data structs, indexed by pidx (0..n-1)
899 */
900 struct hfi1_pportdata *pport;
901
902 /* mem-mapped pointer to base of PIO buffers */
903 void __iomem *piobase;
904 /*
905 * write-combining mem-mapped pointer to base of RcvArray
906 * memory.
907 */
908 void __iomem *rcvarray_wc;
909 /*
910 * credit return base - a per-NUMA range of DMA address that
911 * the chip will use to update the per-context free counter
912 */
913 struct credit_return_base *cr_base;
914
915 /* send context numbers and sizes for each type */
916 struct sc_config_sizes sc_sizes[SC_MAX];
917
918 u32 lcb_access_count; /* count of LCB users */
919
920 char *boardname; /* human readable board info */
921
922 /* device (not port) flags, basically device capabilities */
923 u32 flags;
924
925 /* reset value */
926 u64 z_int_counter;
927 u64 z_rcv_limit;
Vennila Megavannan89abfc82016-02-03 14:34:07 -0800928 u64 z_send_schedule;
Mike Marciniszyn77241052015-07-30 15:17:43 -0400929 /* percpu int_counter */
930 u64 __percpu *int_counter;
931 u64 __percpu *rcv_limit;
Vennila Megavannan89abfc82016-02-03 14:34:07 -0800932 u64 __percpu *send_schedule;
Mike Marciniszyn77241052015-07-30 15:17:43 -0400933 /* number of receive contexts in use by the driver */
934 u32 num_rcv_contexts;
935 /* number of pio send contexts in use by the driver */
936 u32 num_send_contexts;
937 /*
938 * number of ctxts available for PSM open
939 */
940 u32 freectxts;
Ashutosh Dixitaffa48d2016-02-03 14:33:06 -0800941 /* total number of available user/PSM contexts */
942 u32 num_user_contexts;
Mike Marciniszyn77241052015-07-30 15:17:43 -0400943 /* base receive interrupt timeout, in CSR units */
944 u32 rcv_intr_timeout_csr;
945
946 u64 __iomem *egrtidbase;
947 spinlock_t sendctrl_lock; /* protect changes to SendCtrl */
948 spinlock_t rcvctrl_lock; /* protect changes to RcvCtrl */
949 /* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */
950 spinlock_t uctxt_lock; /* rcd and user context changes */
951 /* exclusive access to 8051 */
952 spinlock_t dc8051_lock;
953 /* exclusive access to 8051 memory */
954 spinlock_t dc8051_memlock;
955 int dc8051_timed_out; /* remember if the 8051 timed out */
956 /*
957 * A page that will hold event notification bitmaps for all
958 * contexts. This page will be mapped into all processes.
959 */
960 unsigned long *events;
961 /*
962 * per unit status, see also portdata statusp
963 * mapped read-only into user processes so they can get unit and
964 * IB link status cheaply
965 */
966 struct hfi1_status *status;
967 u32 freezelen; /* max length of freezemsg */
968
969 /* revision register shadow */
970 u64 revision;
971 /* Base GUID for device (network order) */
972 u64 base_guid;
973
974 /* these are the "32 bit" regs */
975
976 /* value we put in kr_rcvhdrsize */
977 u32 rcvhdrsize;
978 /* number of receive contexts the chip supports */
979 u32 chip_rcv_contexts;
980 /* number of receive array entries */
981 u32 chip_rcv_array_count;
982 /* number of PIO send contexts the chip supports */
983 u32 chip_send_contexts;
984 /* number of bytes in the PIO memory buffer */
985 u32 chip_pio_mem_size;
986 /* number of bytes in the SDMA memory buffer */
987 u32 chip_sdma_mem_size;
988
989 /* size of each rcvegrbuffer */
990 u32 rcvegrbufsize;
991 /* log2 of above */
992 u16 rcvegrbufsize_shift;
993 /* both sides of the PCIe link are gen3 capable */
994 u8 link_gen3_capable;
995 /* localbus width (1, 2,4,8,16,32) from config space */
996 u32 lbus_width;
997 /* localbus speed in MHz */
998 u32 lbus_speed;
999 int unit; /* unit # of this chip */
1000 int node; /* home node of this chip */
1001
1002 /* save these PCI fields to restore after a reset */
1003 u32 pcibar0;
1004 u32 pcibar1;
1005 u32 pci_rom;
1006 u16 pci_command;
1007 u16 pcie_devctl;
1008 u16 pcie_lnkctl;
1009 u16 pcie_devctl2;
1010 u32 pci_msix0;
1011 u32 pci_lnkctl3;
1012 u32 pci_tph2;
1013
1014 /*
1015 * ASCII serial number, from flash, large enough for original
1016 * all digit strings, and longer serial number format
1017 */
1018 u8 serial[SERIAL_MAX];
1019 /* human readable board version */
1020 u8 boardversion[BOARD_VERS_MAX];
1021 u8 lbus_info[32]; /* human readable localbus info */
1022 /* chip major rev, from CceRevision */
1023 u8 majrev;
1024 /* chip minor rev, from CceRevision */
1025 u8 minrev;
1026 /* hardware ID */
1027 u8 hfi1_id;
1028 /* implementation code */
1029 u8 icode;
1030 /* default link down value (poll/sleep) */
1031 u8 link_default;
1032 /* vAU of this device */
1033 u8 vau;
1034 /* vCU of this device */
1035 u8 vcu;
1036 /* link credits of this device */
1037 u16 link_credits;
1038 /* initial vl15 credits to use */
1039 u16 vl15_init;
1040
1041 /* Misc small ints */
1042 /* Number of physical ports available */
1043 u8 num_pports;
1044 /* Lowest context number which can be used by user processes */
1045 u8 first_user_ctxt;
1046 u8 n_krcv_queues;
1047 u8 qos_shift;
1048 u8 qpn_mask;
1049
1050 u16 rhf_offset; /* offset of RHF within receive header entry */
1051 u16 irev; /* implementation revision */
1052 u16 dc8051_ver; /* 8051 firmware version */
1053
Easwar Hariharanc3838b32016-02-09 14:29:13 -08001054 struct platform_config platform_config;
Mike Marciniszyn77241052015-07-30 15:17:43 -04001055 struct platform_config_cache pcfg_cache;
Mike Marciniszyn77241052015-07-30 15:17:43 -04001056
1057 struct diag_client *diag_client;
1058 spinlock_t hfi1_diag_trans_lock; /* protect diag observer ops */
1059
1060 u8 psxmitwait_supported;
1061 /* cycle length of PS* counters in HW (in picoseconds) */
1062 u16 psxmitwait_check_rate;
1063 /* high volume overflow errors deferred to tasklet */
1064 struct tasklet_struct error_tasklet;
Mike Marciniszyn77241052015-07-30 15:17:43 -04001065
1066 /* MSI-X information */
1067 struct hfi1_msix_entry *msix_entries;
1068 u32 num_msix_entries;
1069
1070 /* INTx information */
1071 u32 requested_intx_irq; /* did we request one? */
1072 char intx_name[MAX_NAME_SIZE]; /* INTx name */
1073
1074 /* general interrupt: mask of handled interrupts */
1075 u64 gi_mask[CCE_NUM_INT_CSRS];
1076
1077 struct rcv_array_data rcv_entries;
1078
1079 /*
1080 * 64 bit synthetic counters
1081 */
1082 struct timer_list synth_stats_timer;
1083
1084 /*
1085 * device counters
1086 */
1087 char *cntrnames;
1088 size_t cntrnameslen;
1089 size_t ndevcntrs;
1090 u64 *cntrs;
1091 u64 *scntrs;
1092
1093 /*
1094 * remembered values for synthetic counters
1095 */
1096 u64 last_tx;
1097 u64 last_rx;
1098
1099 /*
1100 * per-port counters
1101 */
1102 size_t nportcntrs;
1103 char *portcntrnames;
1104 size_t portcntrnameslen;
1105
1106 struct hfi1_snoop_data hfi1_snoop;
1107
1108 struct err_info_rcvport err_info_rcvport;
1109 struct err_info_constraint err_info_rcv_constraint;
1110 struct err_info_constraint err_info_xmit_constraint;
1111 u8 err_info_uncorrectable;
1112 u8 err_info_fmconfig;
1113
1114 atomic_t drop_packet;
1115 u8 do_drop;
1116
Joel Rosenzweig2c5b5212015-12-01 15:38:19 -05001117 /*
1118 * Software counters for the status bits defined by the
1119 * associated error status registers
1120 */
1121 u64 cce_err_status_cnt[NUM_CCE_ERR_STATUS_COUNTERS];
1122 u64 rcv_err_status_cnt[NUM_RCV_ERR_STATUS_COUNTERS];
1123 u64 misc_err_status_cnt[NUM_MISC_ERR_STATUS_COUNTERS];
1124 u64 send_pio_err_status_cnt[NUM_SEND_PIO_ERR_STATUS_COUNTERS];
1125 u64 send_dma_err_status_cnt[NUM_SEND_DMA_ERR_STATUS_COUNTERS];
1126 u64 send_egress_err_status_cnt[NUM_SEND_EGRESS_ERR_STATUS_COUNTERS];
1127 u64 send_err_status_cnt[NUM_SEND_ERR_STATUS_COUNTERS];
1128
1129 /* Software counter that spans all contexts */
1130 u64 sw_ctxt_err_status_cnt[NUM_SEND_CTXT_ERR_STATUS_COUNTERS];
1131 /* Software counter that spans all DMA engines */
1132 u64 sw_send_dma_eng_err_status_cnt[
1133 NUM_SEND_DMA_ENG_ERR_STATUS_COUNTERS];
1134 /* Software counter that aggregates all cce_err_status errors */
1135 u64 sw_cce_err_status_aggregate;
Jakub Pawlak2b719042016-07-01 16:01:22 -07001136 /* Software counter that aggregates all bypass packet rcv errors */
1137 u64 sw_rcv_bypass_packet_errors;
Mike Marciniszyn77241052015-07-30 15:17:43 -04001138 /* receive interrupt functions */
1139 rhf_rcv_function_ptr *rhf_rcv_function_map;
1140 rhf_rcv_function_ptr normal_rhf_rcv_functions[8];
1141
1142 /*
1143 * Handlers for outgoing data so that snoop/capture does not
1144 * have to have its hooks in the send path
1145 */
Mike Marciniszyn14553ca2016-02-14 12:45:36 -08001146 send_routine process_pio_send;
1147 send_routine process_dma_send;
Mike Marciniszyn77241052015-07-30 15:17:43 -04001148 void (*pio_inline_send)(struct hfi1_devdata *dd, struct pio_buf *pbuf,
1149 u64 pbc, const void *from, size_t count);
1150
1151 /* OUI comes from the HW. Used everywhere as 3 separate bytes. */
1152 u8 oui1;
1153 u8 oui2;
1154 u8 oui3;
1155 /* Timer and counter used to detect RcvBufOvflCnt changes */
1156 struct timer_list rcverr_timer;
1157 u32 rcv_ovfl_cnt;
1158
Mike Marciniszyn77241052015-07-30 15:17:43 -04001159 wait_queue_head_t event_queue;
1160
1161 /* Save the enabled LCB error bits */
1162 u64 lcb_err_en;
1163 u8 dc_shutdown;
Mark F. Brown46b010d2015-11-09 19:18:20 -05001164
1165 /* receive context tail dummy address */
1166 __le64 *rcvhdrtail_dummy_kvaddr;
1167 dma_addr_t rcvhdrtail_dummy_physaddr;
Ashutosh Dixitaffa48d2016-02-03 14:33:06 -08001168
Dean Luicke154f122016-02-03 14:37:24 -08001169 bool eprom_available; /* true if EPROM is available for this device */
Ashutosh Dixitaffa48d2016-02-03 14:33:06 -08001170 bool aspm_supported; /* Does HW support ASPM */
1171 bool aspm_enabled; /* ASPM state: enabled/disabled */
1172 /* Serialize ASPM enable/disable between multiple verbs contexts */
1173 spinlock_t aspm_lock;
1174 /* Number of verbs contexts which have disabled ASPM */
1175 atomic_t aspm_disabled_cnt;
Mitko Haralanov957558c2016-02-03 14:33:40 -08001176
1177 struct hfi1_affinity *affinity;
Dennis Dalessandroe11ffbd2016-05-19 05:26:44 -07001178 struct kobject kobj;
Mike Marciniszyn77241052015-07-30 15:17:43 -04001179};
1180
1181/* 8051 firmware version helper */
1182#define dc8051_ver(a, b) ((a) << 8 | (b))
Ira Weiny939b6ca2016-06-15 02:22:08 -04001183#define dc8051_ver_maj(a) ((a & 0xff00) >> 8)
1184#define dc8051_ver_min(a) (a & 0x00ff)
Mike Marciniszyn77241052015-07-30 15:17:43 -04001185
1186/* f_put_tid types */
1187#define PT_EXPECTED 0
1188#define PT_EAGER 1
1189#define PT_INVALID 2
1190
Mitko Haralanov06e0ffa2016-03-08 11:14:20 -08001191struct tid_rb_node;
Mitko Haralanovf727a0c2016-02-05 11:57:46 -05001192struct mmu_rb_node;
Dean Luicke0b09ac2016-07-28 15:21:20 -04001193struct mmu_rb_handler;
Mitko Haralanovf727a0c2016-02-05 11:57:46 -05001194
Mike Marciniszyn77241052015-07-30 15:17:43 -04001195/* Private data for file operations */
1196struct hfi1_filedata {
1197 struct hfi1_ctxtdata *uctxt;
1198 unsigned subctxt;
1199 struct hfi1_user_sdma_comp_q *cq;
1200 struct hfi1_user_sdma_pkt_q *pq;
1201 /* for cpu affinity; -1 if none */
1202 int rec_cpu_num;
Mitko Haralanova7922f72016-03-08 11:15:39 -08001203 u32 tid_n_pinned;
Dean Luicke0b09ac2016-07-28 15:21:20 -04001204 struct mmu_rb_handler *handler;
Mitko Haralanov06e0ffa2016-03-08 11:14:20 -08001205 struct tid_rb_node **entry_to_rb;
Mitko Haralanova86cd352016-02-05 11:57:49 -05001206 spinlock_t tid_lock; /* protect tid_[limit,used] counters */
1207 u32 tid_limit;
1208 u32 tid_used;
Mitko Haralanova86cd352016-02-05 11:57:49 -05001209 u32 *invalid_tids;
1210 u32 invalid_tid_idx;
Mitko Haralanov06e0ffa2016-03-08 11:14:20 -08001211 /* protect invalid_tids array and invalid_tid_idx */
1212 spinlock_t invalid_lock;
Ira Weiny3faa3d92016-07-28 15:21:19 -04001213 struct mm_struct *mm;
Mike Marciniszyn77241052015-07-30 15:17:43 -04001214};
1215
1216extern struct list_head hfi1_dev_list;
1217extern spinlock_t hfi1_devs_lock;
1218struct hfi1_devdata *hfi1_lookup(int unit);
1219extern u32 hfi1_cpulist_count;
1220extern unsigned long *hfi1_cpulist;
1221
1222extern unsigned int snoop_drop_send;
1223extern unsigned int snoop_force_capture;
1224int hfi1_init(struct hfi1_devdata *, int);
1225int hfi1_count_units(int *npresentp, int *nupp);
1226int hfi1_count_active_units(void);
1227
1228int hfi1_diag_add(struct hfi1_devdata *);
1229void hfi1_diag_remove(struct hfi1_devdata *);
1230void handle_linkup_change(struct hfi1_devdata *dd, u32 linkup);
1231
1232void handle_user_interrupt(struct hfi1_ctxtdata *rcd);
1233
1234int hfi1_create_rcvhdrq(struct hfi1_devdata *, struct hfi1_ctxtdata *);
1235int hfi1_setup_eagerbufs(struct hfi1_ctxtdata *);
1236int hfi1_create_ctxts(struct hfi1_devdata *dd);
Mitko Haralanov957558c2016-02-03 14:33:40 -08001237struct hfi1_ctxtdata *hfi1_create_ctxtdata(struct hfi1_pportdata *, u32, int);
Mike Marciniszyn77241052015-07-30 15:17:43 -04001238void hfi1_init_pportdata(struct pci_dev *, struct hfi1_pportdata *,
1239 struct hfi1_devdata *, u8, u8);
1240void hfi1_free_ctxtdata(struct hfi1_devdata *, struct hfi1_ctxtdata *);
1241
Dean Luickf4f30031c2015-10-26 10:28:44 -04001242int handle_receive_interrupt(struct hfi1_ctxtdata *, int);
1243int handle_receive_interrupt_nodma_rtail(struct hfi1_ctxtdata *, int);
1244int handle_receive_interrupt_dma_rtail(struct hfi1_ctxtdata *, int);
Jim Snowfb9036d2016-01-11 18:32:21 -05001245void set_all_slowpath(struct hfi1_devdata *dd);
Dean Luickf4f30031c2015-10-26 10:28:44 -04001246
Sebastian Sanchezd6373012016-07-25 07:54:48 -07001247extern const struct pci_device_id hfi1_pci_tbl[];
1248
Dean Luickf4f30031c2015-10-26 10:28:44 -04001249/* receive packet handler dispositions */
1250#define RCV_PKT_OK 0x0 /* keep going */
1251#define RCV_PKT_LIMIT 0x1 /* stop, hit limit, start thread */
1252#define RCV_PKT_DONE 0x2 /* stop, no more packets detected */
1253
1254/* calculate the current RHF address */
1255static inline __le32 *get_rhf_addr(struct hfi1_ctxtdata *rcd)
1256{
1257 return (__le32 *)rcd->rcvhdrq + rcd->head + rcd->dd->rhf_offset;
1258}
1259
Mike Marciniszyn77241052015-07-30 15:17:43 -04001260int hfi1_reset_device(int);
1261
1262/* return the driver's idea of the logical OPA port state */
1263static inline u32 driver_lstate(struct hfi1_pportdata *ppd)
1264{
1265 return ppd->lstate; /* use the cached value */
1266}
1267
Jim Snowfb9036d2016-01-11 18:32:21 -05001268void receive_interrupt_work(struct work_struct *work);
1269
1270/* extract service channel from header and rhf */
1271static inline int hdr2sc(struct hfi1_message_header *hdr, u64 rhf)
1272{
1273 return ((be16_to_cpu(hdr->lrh[0]) >> 12) & 0xf) |
Dasaratharaman Chandramoulib736a462016-07-25 13:40:34 -07001274 ((!!(rhf_dc_info(rhf))) << 4);
Jim Snowfb9036d2016-01-11 18:32:21 -05001275}
1276
Mitko Haralanov08fe16f2016-08-16 13:26:12 -07001277#define HFI1_JKEY_WIDTH 16
1278#define HFI1_JKEY_MASK (BIT(16) - 1)
1279#define HFI1_ADMIN_JKEY_RANGE 32
1280
1281/*
1282 * J_KEYs are split and allocated in the following groups:
1283 * 0 - 31 - users with administrator privileges
1284 * 32 - 63 - kernel protocols using KDETH packets
1285 * 64 - 65535 - all other users using KDETH packets
1286 */
Mike Marciniszyn77241052015-07-30 15:17:43 -04001287static inline u16 generate_jkey(kuid_t uid)
1288{
Mitko Haralanov08fe16f2016-08-16 13:26:12 -07001289 u16 jkey = from_kuid(current_user_ns(), uid) & HFI1_JKEY_MASK;
1290
1291 if (capable(CAP_SYS_ADMIN))
1292 jkey &= HFI1_ADMIN_JKEY_RANGE - 1;
1293 else if (jkey < 64)
1294 jkey |= BIT(HFI1_JKEY_WIDTH - 1);
1295
1296 return jkey;
Mike Marciniszyn77241052015-07-30 15:17:43 -04001297}
1298
1299/*
1300 * active_egress_rate
1301 *
1302 * returns the active egress rate in units of [10^6 bits/sec]
1303 */
1304static inline u32 active_egress_rate(struct hfi1_pportdata *ppd)
1305{
1306 u16 link_speed = ppd->link_speed_active;
1307 u16 link_width = ppd->link_width_active;
1308 u32 egress_rate;
1309
1310 if (link_speed == OPA_LINK_SPEED_25G)
1311 egress_rate = 25000;
1312 else /* assume OPA_LINK_SPEED_12_5G */
1313 egress_rate = 12500;
1314
1315 switch (link_width) {
1316 case OPA_LINK_WIDTH_4X:
1317 egress_rate *= 4;
1318 break;
1319 case OPA_LINK_WIDTH_3X:
1320 egress_rate *= 3;
1321 break;
1322 case OPA_LINK_WIDTH_2X:
1323 egress_rate *= 2;
1324 break;
1325 default:
1326 /* assume IB_WIDTH_1X */
1327 break;
1328 }
1329
1330 return egress_rate;
1331}
1332
1333/*
1334 * egress_cycles
1335 *
1336 * Returns the number of 'fabric clock cycles' to egress a packet
1337 * of length 'len' bytes, at 'rate' Mbit/s. Since the fabric clock
1338 * rate is (approximately) 805 MHz, the units of the returned value
1339 * are (1/805 MHz).
1340 */
1341static inline u32 egress_cycles(u32 len, u32 rate)
1342{
1343 u32 cycles;
1344
1345 /*
1346 * cycles is:
1347 *
1348 * (length) [bits] / (rate) [bits/sec]
1349 * ---------------------------------------------------
1350 * fabric_clock_period == 1 /(805 * 10^6) [cycles/sec]
1351 */
1352
1353 cycles = len * 8; /* bits */
1354 cycles *= 805;
1355 cycles /= rate;
1356
1357 return cycles;
1358}
1359
1360void set_link_ipg(struct hfi1_pportdata *ppd);
1361void process_becn(struct hfi1_pportdata *ppd, u8 sl, u16 rlid, u32 lqpn,
1362 u32 rqpn, u8 svc_type);
Dennis Dalessandro895420d2016-01-19 14:42:28 -08001363void return_cnp(struct hfi1_ibport *ibp, struct rvt_qp *qp, u32 remote_qpn,
Mike Marciniszyn77241052015-07-30 15:17:43 -04001364 u32 pkey, u32 slid, u32 dlid, u8 sc5,
1365 const struct ib_grh *old_grh);
Sebastian Sancheze38d1e42016-04-12 11:22:21 -07001366#define PKEY_CHECK_INVALID -1
1367int egress_pkey_check(struct hfi1_pportdata *ppd, __be16 *lrh, __be32 *bth,
1368 u8 sc5, int8_t s_pkey_index);
Mike Marciniszyn77241052015-07-30 15:17:43 -04001369
1370#define PACKET_EGRESS_TIMEOUT 350
1371static inline void pause_for_credit_return(struct hfi1_devdata *dd)
1372{
1373 /* Pause at least 1us, to ensure chip returns all credits */
1374 u32 usec = cclock_to_ns(dd, PACKET_EGRESS_TIMEOUT) / 1000;
1375
1376 udelay(usec ? usec : 1);
1377}
1378
1379/**
1380 * sc_to_vlt() reverse lookup sc to vl
1381 * @dd - devdata
1382 * @sc5 - 5 bit sc
1383 */
1384static inline u8 sc_to_vlt(struct hfi1_devdata *dd, u8 sc5)
1385{
1386 unsigned seq;
1387 u8 rval;
1388
1389 if (sc5 >= OPA_MAX_SCS)
1390 return (u8)(0xff);
1391
1392 do {
1393 seq = read_seqbegin(&dd->sc2vl_lock);
1394 rval = *(((u8 *)dd->sc2vl) + sc5);
1395 } while (read_seqretry(&dd->sc2vl_lock, seq));
1396
1397 return rval;
1398}
1399
1400#define PKEY_MEMBER_MASK 0x8000
1401#define PKEY_LOW_15_MASK 0x7fff
1402
1403/*
1404 * ingress_pkey_matches_entry - return 1 if the pkey matches ent (ent
1405 * being an entry from the ingress partition key table), return 0
1406 * otherwise. Use the matching criteria for ingress partition keys
1407 * specified in the OPAv1 spec., section 9.10.14.
1408 */
1409static inline int ingress_pkey_matches_entry(u16 pkey, u16 ent)
1410{
1411 u16 mkey = pkey & PKEY_LOW_15_MASK;
1412 u16 ment = ent & PKEY_LOW_15_MASK;
1413
1414 if (mkey == ment) {
1415 /*
1416 * If pkey[15] is clear (limited partition member),
1417 * is bit 15 in the corresponding table element
1418 * clear (limited member)?
1419 */
1420 if (!(pkey & PKEY_MEMBER_MASK))
1421 return !!(ent & PKEY_MEMBER_MASK);
1422 return 1;
1423 }
1424 return 0;
1425}
1426
1427/*
1428 * ingress_pkey_table_search - search the entire pkey table for
1429 * an entry which matches 'pkey'. return 0 if a match is found,
1430 * and 1 otherwise.
1431 */
1432static int ingress_pkey_table_search(struct hfi1_pportdata *ppd, u16 pkey)
1433{
1434 int i;
1435
1436 for (i = 0; i < MAX_PKEY_VALUES; i++) {
1437 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[i]))
1438 return 0;
1439 }
1440 return 1;
1441}
1442
1443/*
1444 * ingress_pkey_table_fail - record a failure of ingress pkey validation,
1445 * i.e., increment port_rcv_constraint_errors for the port, and record
1446 * the 'error info' for this failure.
1447 */
1448static void ingress_pkey_table_fail(struct hfi1_pportdata *ppd, u16 pkey,
1449 u16 slid)
1450{
1451 struct hfi1_devdata *dd = ppd->dd;
1452
1453 incr_cntr64(&ppd->port_rcv_constraint_errors);
1454 if (!(dd->err_info_rcv_constraint.status & OPA_EI_STATUS_SMASK)) {
1455 dd->err_info_rcv_constraint.status |= OPA_EI_STATUS_SMASK;
1456 dd->err_info_rcv_constraint.slid = slid;
1457 dd->err_info_rcv_constraint.pkey = pkey;
1458 }
1459}
1460
1461/*
1462 * ingress_pkey_check - Return 0 if the ingress pkey is valid, return 1
1463 * otherwise. Use the criteria in the OPAv1 spec, section 9.10.14. idx
1464 * is a hint as to the best place in the partition key table to begin
1465 * searching. This function should not be called on the data path because
1466 * of performance reasons. On datapath pkey check is expected to be done
1467 * by HW and rcv_pkey_check function should be called instead.
1468 */
1469static inline int ingress_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1470 u8 sc5, u8 idx, u16 slid)
1471{
1472 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1473 return 0;
1474
1475 /* If SC15, pkey[0:14] must be 0x7fff */
1476 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1477 goto bad;
1478
1479 /* Is the pkey = 0x0, or 0x8000? */
1480 if ((pkey & PKEY_LOW_15_MASK) == 0)
1481 goto bad;
1482
1483 /* The most likely matching pkey has index 'idx' */
1484 if (ingress_pkey_matches_entry(pkey, ppd->pkeys[idx]))
1485 return 0;
1486
1487 /* no match - try the whole table */
1488 if (!ingress_pkey_table_search(ppd, pkey))
1489 return 0;
1490
1491bad:
1492 ingress_pkey_table_fail(ppd, pkey, slid);
1493 return 1;
1494}
1495
1496/*
1497 * rcv_pkey_check - Return 0 if the ingress pkey is valid, return 1
1498 * otherwise. It only ensures pkey is vlid for QP0. This function
1499 * should be called on the data path instead of ingress_pkey_check
1500 * as on data path, pkey check is done by HW (except for QP0).
1501 */
1502static inline int rcv_pkey_check(struct hfi1_pportdata *ppd, u16 pkey,
1503 u8 sc5, u16 slid)
1504{
1505 if (!(ppd->part_enforce & HFI1_PART_ENFORCE_IN))
1506 return 0;
1507
1508 /* If SC15, pkey[0:14] must be 0x7fff */
1509 if ((sc5 == 0xf) && ((pkey & PKEY_LOW_15_MASK) != PKEY_LOW_15_MASK))
1510 goto bad;
1511
1512 return 0;
1513bad:
1514 ingress_pkey_table_fail(ppd, pkey, slid);
1515 return 1;
1516}
1517
1518/* MTU handling */
1519
1520/* MTU enumeration, 256-4k match IB */
1521#define OPA_MTU_0 0
1522#define OPA_MTU_256 1
1523#define OPA_MTU_512 2
1524#define OPA_MTU_1024 3
1525#define OPA_MTU_2048 4
1526#define OPA_MTU_4096 5
1527
1528u32 lrh_max_header_bytes(struct hfi1_devdata *dd);
1529int mtu_to_enum(u32 mtu, int default_if_bad);
1530u16 enum_to_mtu(int);
1531static inline int valid_ib_mtu(unsigned int mtu)
1532{
1533 return mtu == 256 || mtu == 512 ||
1534 mtu == 1024 || mtu == 2048 ||
1535 mtu == 4096;
1536}
Jubin Johnf4d507c2016-02-14 20:20:25 -08001537
Mike Marciniszyn77241052015-07-30 15:17:43 -04001538static inline int valid_opa_max_mtu(unsigned int mtu)
1539{
1540 return mtu >= 2048 &&
1541 (valid_ib_mtu(mtu) || mtu == 8192 || mtu == 10240);
1542}
1543
1544int set_mtu(struct hfi1_pportdata *);
1545
1546int hfi1_set_lid(struct hfi1_pportdata *, u32, u8);
1547void hfi1_disable_after_error(struct hfi1_devdata *);
1548int hfi1_set_uevent_bits(struct hfi1_pportdata *, const int);
1549int hfi1_rcvbuf_validate(u32, u8, u16 *);
1550
1551int fm_get_table(struct hfi1_pportdata *, int, void *);
1552int fm_set_table(struct hfi1_pportdata *, int, void *);
1553
1554void set_up_vl15(struct hfi1_devdata *dd, u8 vau, u16 vl15buf);
1555void reset_link_credits(struct hfi1_devdata *dd);
1556void assign_remote_cm_au_table(struct hfi1_devdata *dd, u8 vcu);
1557
1558int snoop_recv_handler(struct hfi1_packet *packet);
Dennis Dalessandro895420d2016-01-19 14:42:28 -08001559int snoop_send_dma_handler(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
Dennis Dalessandrod46e5142015-11-11 00:34:37 -05001560 u64 pbc);
Dennis Dalessandro895420d2016-01-19 14:42:28 -08001561int snoop_send_pio_handler(struct rvt_qp *qp, struct hfi1_pkt_state *ps,
Dennis Dalessandrod46e5142015-11-11 00:34:37 -05001562 u64 pbc);
Mike Marciniszyn77241052015-07-30 15:17:43 -04001563void snoop_inline_pio_send(struct hfi1_devdata *dd, struct pio_buf *pbuf,
1564 u64 pbc, const void *from, size_t count);
Mike Marciniszyn8a4d3442016-02-14 12:46:01 -08001565int set_buffer_control(struct hfi1_pportdata *ppd, struct buffer_control *bc);
Mike Marciniszyn77241052015-07-30 15:17:43 -04001566
Mike Marciniszyn77241052015-07-30 15:17:43 -04001567static inline struct hfi1_devdata *dd_from_ppd(struct hfi1_pportdata *ppd)
1568{
1569 return ppd->dd;
1570}
1571
1572static inline struct hfi1_devdata *dd_from_dev(struct hfi1_ibdev *dev)
1573{
1574 return container_of(dev, struct hfi1_devdata, verbs_dev);
1575}
1576
1577static inline struct hfi1_devdata *dd_from_ibdev(struct ib_device *ibdev)
1578{
1579 return dd_from_dev(to_idev(ibdev));
1580}
1581
1582static inline struct hfi1_pportdata *ppd_from_ibp(struct hfi1_ibport *ibp)
1583{
1584 return container_of(ibp, struct hfi1_pportdata, ibport_data);
1585}
1586
Harish Chegondi45b59ee2016-02-03 14:36:49 -08001587static inline struct hfi1_ibdev *dev_from_rdi(struct rvt_dev_info *rdi)
1588{
1589 return container_of(rdi, struct hfi1_ibdev, rdi);
1590}
1591
Mike Marciniszyn77241052015-07-30 15:17:43 -04001592static inline struct hfi1_ibport *to_iport(struct ib_device *ibdev, u8 port)
1593{
1594 struct hfi1_devdata *dd = dd_from_ibdev(ibdev);
1595 unsigned pidx = port - 1; /* IB number port from 1, hdw from 0 */
1596
1597 WARN_ON(pidx >= dd->num_pports);
1598 return &dd->pport[pidx].ibport_data;
1599}
1600
Mitko Haralanov5fd2b562016-07-25 13:38:07 -07001601void hfi1_process_ecn_slowpath(struct rvt_qp *qp, struct hfi1_packet *pkt,
1602 bool do_cnp);
1603static inline bool process_ecn(struct rvt_qp *qp, struct hfi1_packet *pkt,
1604 bool do_cnp)
1605{
1606 struct hfi1_other_headers *ohdr = pkt->ohdr;
1607 u32 bth1;
1608
1609 bth1 = be32_to_cpu(ohdr->bth[1]);
1610 if (unlikely(bth1 & (HFI1_BECN_SMASK | HFI1_FECN_SMASK))) {
1611 hfi1_process_ecn_slowpath(qp, pkt, do_cnp);
1612 return bth1 & HFI1_FECN_SMASK;
1613 }
1614 return false;
1615}
1616
Mike Marciniszyn77241052015-07-30 15:17:43 -04001617/*
1618 * Return the indexed PKEY from the port PKEY table.
1619 */
1620static inline u16 hfi1_get_pkey(struct hfi1_ibport *ibp, unsigned index)
1621{
1622 struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
1623 u16 ret;
1624
1625 if (index >= ARRAY_SIZE(ppd->pkeys))
1626 ret = 0;
1627 else
1628 ret = ppd->pkeys[index];
1629
1630 return ret;
1631}
1632
1633/*
Jianxin Xiong8adf71f2016-07-25 13:39:14 -07001634 * Called by readers of cc_state only, must call under rcu_read_lock().
Mike Marciniszyn77241052015-07-30 15:17:43 -04001635 */
1636static inline struct cc_state *get_cc_state(struct hfi1_pportdata *ppd)
1637{
1638 return rcu_dereference(ppd->cc_state);
1639}
1640
1641/*
Jianxin Xiong8adf71f2016-07-25 13:39:14 -07001642 * Called by writers of cc_state only, must call under cc_state_lock.
1643 */
1644static inline
1645struct cc_state *get_cc_state_protected(struct hfi1_pportdata *ppd)
1646{
1647 return rcu_dereference_protected(ppd->cc_state,
1648 lockdep_is_held(&ppd->cc_state_lock));
1649}
1650
1651/*
Mike Marciniszyn77241052015-07-30 15:17:43 -04001652 * values for dd->flags (_device_ related flags)
1653 */
1654#define HFI1_INITTED 0x1 /* chip and driver up and initted */
1655#define HFI1_PRESENT 0x2 /* chip accesses can be done */
1656#define HFI1_FROZEN 0x4 /* chip in SPC freeze */
1657#define HFI1_HAS_SDMA_TIMEOUT 0x8
1658#define HFI1_HAS_SEND_DMA 0x10 /* Supports Send DMA */
1659#define HFI1_FORCED_FREEZE 0x80 /* driver forced freeze mode */
Mike Marciniszyn77241052015-07-30 15:17:43 -04001660
1661/* IB dword length mask in PBC (lower 11 bits); same for all chips */
1662#define HFI1_PBC_LENGTH_MASK ((1 << 11) - 1)
1663
Mike Marciniszyn77241052015-07-30 15:17:43 -04001664/* ctxt_flag bit offsets */
1665 /* context has been setup */
1666#define HFI1_CTXT_SETUP_DONE 1
1667 /* waiting for a packet to arrive */
1668#define HFI1_CTXT_WAITING_RCV 2
1669 /* master has not finished initializing */
1670#define HFI1_CTXT_MASTER_UNINIT 4
1671 /* waiting for an urgent packet to arrive */
1672#define HFI1_CTXT_WAITING_URG 5
1673
1674/* free up any allocated data at closes */
1675struct hfi1_devdata *hfi1_init_dd(struct pci_dev *,
1676 const struct pci_device_id *);
1677void hfi1_free_devdata(struct hfi1_devdata *);
Mike Marciniszyn77241052015-07-30 15:17:43 -04001678struct hfi1_devdata *hfi1_alloc_devdata(struct pci_dev *pdev, size_t extra);
1679
Easwar Hariharan22434722016-03-07 11:35:03 -08001680/* LED beaconing functions */
1681void hfi1_start_led_override(struct hfi1_pportdata *ppd, unsigned int timeon,
1682 unsigned int timeoff);
Easwar Hariharan91ab4ed2016-02-03 14:35:57 -08001683void shutdown_led_override(struct hfi1_pportdata *ppd);
Mike Marciniszyn77241052015-07-30 15:17:43 -04001684
1685#define HFI1_CREDIT_RETURN_RATE (100)
1686
1687/*
1688 * The number of words for the KDETH protocol field. If this is
1689 * larger then the actual field used, then part of the payload
1690 * will be in the header.
1691 *
1692 * Optimally, we want this sized so that a typical case will
1693 * use full cache lines. The typical local KDETH header would
1694 * be:
1695 *
1696 * Bytes Field
1697 * 8 LRH
1698 * 12 BHT
1699 * ?? KDETH
1700 * 8 RHF
1701 * ---
1702 * 28 + KDETH
1703 *
1704 * For a 64-byte cache line, KDETH would need to be 36 bytes or 9 DWORDS
1705 */
1706#define DEFAULT_RCVHDRSIZE 9
1707
1708/*
1709 * Maximal header byte count:
1710 *
1711 * Bytes Field
1712 * 8 LRH
1713 * 40 GRH (optional)
1714 * 12 BTH
1715 * ?? KDETH
1716 * 8 RHF
1717 * ---
1718 * 68 + KDETH
1719 *
1720 * We also want to maintain a cache line alignment to assist DMA'ing
1721 * of the header bytes. Round up to a good size.
1722 */
1723#define DEFAULT_RCVHDR_ENTSIZE 32
1724
Ira Weiny3faa3d92016-07-28 15:21:19 -04001725bool hfi1_can_pin_pages(struct hfi1_devdata *dd, struct mm_struct *mm,
1726 u32 nlocked, u32 npages);
1727int hfi1_acquire_user_pages(struct mm_struct *mm, unsigned long vaddr,
1728 size_t npages, bool writable, struct page **pages);
Ira Weinyac335e72016-07-28 12:27:28 -04001729void hfi1_release_user_pages(struct mm_struct *mm, struct page **p,
1730 size_t npages, bool dirty);
Mike Marciniszyn77241052015-07-30 15:17:43 -04001731
1732static inline void clear_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
1733{
Jubin John50e5dcb2016-02-14 20:19:41 -08001734 *((u64 *)rcd->rcvhdrtail_kvaddr) = 0ULL;
Mike Marciniszyn77241052015-07-30 15:17:43 -04001735}
1736
1737static inline u32 get_rcvhdrtail(const struct hfi1_ctxtdata *rcd)
1738{
1739 /*
1740 * volatile because it's a DMA target from the chip, routine is
1741 * inlined, and don't want register caching or reordering.
1742 */
Jubin John50e5dcb2016-02-14 20:19:41 -08001743 return (u32)le64_to_cpu(*rcd->rcvhdrtail_kvaddr);
Mike Marciniszyn77241052015-07-30 15:17:43 -04001744}
1745
1746/*
1747 * sysfs interface.
1748 */
1749
1750extern const char ib_hfi1_version[];
1751
1752int hfi1_device_create(struct hfi1_devdata *);
1753void hfi1_device_remove(struct hfi1_devdata *);
1754
1755int hfi1_create_port_files(struct ib_device *ibdev, u8 port_num,
1756 struct kobject *kobj);
1757int hfi1_verbs_register_sysfs(struct hfi1_devdata *);
1758void hfi1_verbs_unregister_sysfs(struct hfi1_devdata *);
1759/* Hook for sysfs read of QSFP */
1760int qsfp_dump(struct hfi1_pportdata *ppd, char *buf, int len);
1761
1762int hfi1_pcie_init(struct pci_dev *, const struct pci_device_id *);
1763void hfi1_pcie_cleanup(struct pci_dev *);
1764int hfi1_pcie_ddinit(struct hfi1_devdata *, struct pci_dev *,
1765 const struct pci_device_id *);
1766void hfi1_pcie_ddcleanup(struct hfi1_devdata *);
1767void hfi1_pcie_flr(struct hfi1_devdata *);
1768int pcie_speeds(struct hfi1_devdata *);
1769void request_msix(struct hfi1_devdata *, u32 *, struct hfi1_msix_entry *);
1770void hfi1_enable_intx(struct pci_dev *);
Mike Marciniszyn77241052015-07-30 15:17:43 -04001771void restore_pci_variables(struct hfi1_devdata *dd);
1772int do_pcie_gen3_transition(struct hfi1_devdata *dd);
1773int parse_platform_config(struct hfi1_devdata *dd);
1774int get_platform_config_field(struct hfi1_devdata *dd,
Jubin John17fb4f22016-02-14 20:21:52 -08001775 enum platform_config_table_type_encoding
1776 table_type, int table_index, int field_index,
1777 u32 *data, u32 len);
Mike Marciniszyn77241052015-07-30 15:17:43 -04001778
Mike Marciniszyn77241052015-07-30 15:17:43 -04001779const char *get_unit_name(int unit);
Dennis Dalessandro49dbb6c2016-01-19 14:42:06 -08001780const char *get_card_name(struct rvt_dev_info *rdi);
1781struct pci_dev *get_pci_dev(struct rvt_dev_info *rdi);
Mike Marciniszyn77241052015-07-30 15:17:43 -04001782
1783/*
1784 * Flush write combining store buffers (if present) and perform a write
1785 * barrier.
1786 */
1787static inline void flush_wc(void)
1788{
1789 asm volatile("sfence" : : : "memory");
1790}
1791
1792void handle_eflags(struct hfi1_packet *packet);
1793int process_receive_ib(struct hfi1_packet *packet);
1794int process_receive_bypass(struct hfi1_packet *packet);
1795int process_receive_error(struct hfi1_packet *packet);
1796int kdeth_process_expected(struct hfi1_packet *packet);
1797int kdeth_process_eager(struct hfi1_packet *packet);
1798int process_receive_invalid(struct hfi1_packet *packet);
1799
1800extern rhf_rcv_function_ptr snoop_rhf_rcv_functions[8];
1801
Dennis Dalessandro895420d2016-01-19 14:42:28 -08001802void update_sge(struct rvt_sge_state *ss, u32 length);
Mike Marciniszyn77241052015-07-30 15:17:43 -04001803
1804/* global module parameter variables */
1805extern unsigned int hfi1_max_mtu;
1806extern unsigned int hfi1_cu;
1807extern unsigned int user_credit_return_threshold;
Sebastian Sanchez2ce6bf22015-12-11 08:44:48 -05001808extern int num_user_contexts;
Harish Chegondi429b6a72016-08-31 07:24:40 -07001809extern unsigned long n_krcvqs;
Mark F. Brown5b55ea32016-01-11 18:30:54 -05001810extern uint krcvqs[];
Mike Marciniszyn77241052015-07-30 15:17:43 -04001811extern int krcvqsset;
1812extern uint kdeth_qp;
1813extern uint loopback;
1814extern uint quick_linkup;
1815extern uint rcv_intr_timeout;
1816extern uint rcv_intr_count;
1817extern uint rcv_intr_dynamic;
1818extern ushort link_crc_mask;
1819
1820extern struct mutex hfi1_mutex;
1821
1822/* Number of seconds before our card status check... */
1823#define STATUS_TIMEOUT 60
1824
1825#define DRIVER_NAME "hfi1"
1826#define HFI1_USER_MINOR_BASE 0
1827#define HFI1_TRACE_MINOR 127
1828#define HFI1_DIAGPKT_MINOR 128
1829#define HFI1_DIAG_MINOR_BASE 129
1830#define HFI1_SNOOP_CAPTURE_BASE 200
1831#define HFI1_NMINORS 255
1832
1833#define PCI_VENDOR_ID_INTEL 0x8086
1834#define PCI_DEVICE_ID_INTEL0 0x24f0
1835#define PCI_DEVICE_ID_INTEL1 0x24f1
1836
1837#define HFI1_PKT_USER_SC_INTEGRITY \
1838 (SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK \
Sebastian Sancheze38d1e42016-04-12 11:22:21 -07001839 | SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK \
Mike Marciniszyn77241052015-07-30 15:17:43 -04001840 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK \
1841 | SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK)
1842
1843#define HFI1_PKT_KERNEL_SC_INTEGRITY \
1844 (SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK)
1845
1846static inline u64 hfi1_pkt_default_send_ctxt_mask(struct hfi1_devdata *dd,
1847 u16 ctxt_type)
1848{
1849 u64 base_sc_integrity =
1850 SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
1851 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK
1852 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
1853 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
1854 | SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
1855 | SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK
1856 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
1857 | SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
1858 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
1859 | SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK
1860 | SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
1861 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
1862 | SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK
1863 | SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK
1864 | SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK
1865 | SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK
1866 | SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK;
1867
1868 if (ctxt_type == SC_USER)
1869 base_sc_integrity |= HFI1_PKT_USER_SC_INTEGRITY;
1870 else
1871 base_sc_integrity |= HFI1_PKT_KERNEL_SC_INTEGRITY;
1872
Mike Marciniszyn995deaf2015-11-16 21:59:29 -05001873 if (is_ax(dd))
Edward Mascarenhas624be1d2016-01-11 18:31:43 -05001874 /* turn off send-side job key checks - A0 */
Mike Marciniszyn77241052015-07-30 15:17:43 -04001875 return base_sc_integrity &
1876 ~SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
1877 return base_sc_integrity;
1878}
1879
1880static inline u64 hfi1_pkt_base_sdma_integrity(struct hfi1_devdata *dd)
1881{
1882 u64 base_sdma_integrity =
1883 SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK
1884 | SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK
1885 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK
1886 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK
1887 | SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK
1888 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK
1889 | SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK
1890 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK
1891 | SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK
1892 | SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK
1893 | SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK
1894 | SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK
1895 | SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK
1896 | SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK
1897 | SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK
1898 | SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK;
1899
Mike Marciniszyn995deaf2015-11-16 21:59:29 -05001900 if (is_ax(dd))
Edward Mascarenhas624be1d2016-01-11 18:31:43 -05001901 /* turn off send-side job key checks - A0 */
Mike Marciniszyn77241052015-07-30 15:17:43 -04001902 return base_sdma_integrity &
1903 ~SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK;
1904 return base_sdma_integrity;
1905}
1906
1907/*
1908 * hfi1_early_err is used (only!) to print early errors before devdata is
1909 * allocated, or when dd->pcidev may not be valid, and at the tail end of
1910 * cleanup when devdata may have been freed, etc. hfi1_dev_porterr is
1911 * the same as dd_dev_err, but is used when the message really needs
1912 * the IB port# to be definitive as to what's happening..
1913 */
1914#define hfi1_early_err(dev, fmt, ...) \
1915 dev_err(dev, fmt, ##__VA_ARGS__)
1916
1917#define hfi1_early_info(dev, fmt, ...) \
1918 dev_info(dev, fmt, ##__VA_ARGS__)
1919
1920#define dd_dev_emerg(dd, fmt, ...) \
1921 dev_emerg(&(dd)->pcidev->dev, "%s: " fmt, \
1922 get_unit_name((dd)->unit), ##__VA_ARGS__)
1923#define dd_dev_err(dd, fmt, ...) \
1924 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
1925 get_unit_name((dd)->unit), ##__VA_ARGS__)
1926#define dd_dev_warn(dd, fmt, ...) \
1927 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \
1928 get_unit_name((dd)->unit), ##__VA_ARGS__)
1929
1930#define dd_dev_warn_ratelimited(dd, fmt, ...) \
1931 dev_warn_ratelimited(&(dd)->pcidev->dev, "%s: " fmt, \
1932 get_unit_name((dd)->unit), ##__VA_ARGS__)
1933
1934#define dd_dev_info(dd, fmt, ...) \
1935 dev_info(&(dd)->pcidev->dev, "%s: " fmt, \
1936 get_unit_name((dd)->unit), ##__VA_ARGS__)
1937
Ira Weinya1edc182016-01-11 13:04:32 -05001938#define dd_dev_dbg(dd, fmt, ...) \
1939 dev_dbg(&(dd)->pcidev->dev, "%s: " fmt, \
1940 get_unit_name((dd)->unit), ##__VA_ARGS__)
1941
Mike Marciniszyn77241052015-07-30 15:17:43 -04001942#define hfi1_dev_porterr(dd, port, fmt, ...) \
Jakub Pawlakcde10af2016-05-12 10:23:35 -07001943 dev_err(&(dd)->pcidev->dev, "%s: port %u: " fmt, \
1944 get_unit_name((dd)->unit), (port), ##__VA_ARGS__)
Mike Marciniszyn77241052015-07-30 15:17:43 -04001945
1946/*
1947 * this is used for formatting hw error messages...
1948 */
1949struct hfi1_hwerror_msgs {
1950 u64 mask;
1951 const char *msg;
1952 size_t sz;
1953};
1954
1955/* in intr.c... */
1956void hfi1_format_hwerrors(u64 hwerrs,
1957 const struct hfi1_hwerror_msgs *hwerrmsgs,
1958 size_t nhwerrmsgs, char *msg, size_t lmsg);
1959
1960#define USER_OPCODE_CHECK_VAL 0xC0
1961#define USER_OPCODE_CHECK_MASK 0xC0
1962#define OPCODE_CHECK_VAL_DISABLED 0x0
1963#define OPCODE_CHECK_MASK_DISABLED 0x0
1964
1965static inline void hfi1_reset_cpu_counters(struct hfi1_devdata *dd)
1966{
1967 struct hfi1_pportdata *ppd;
1968 int i;
1969
1970 dd->z_int_counter = get_all_cpu_total(dd->int_counter);
1971 dd->z_rcv_limit = get_all_cpu_total(dd->rcv_limit);
Vennila Megavannan89abfc82016-02-03 14:34:07 -08001972 dd->z_send_schedule = get_all_cpu_total(dd->send_schedule);
Mike Marciniszyn77241052015-07-30 15:17:43 -04001973
1974 ppd = (struct hfi1_pportdata *)(dd + 1);
1975 for (i = 0; i < dd->num_pports; i++, ppd++) {
Dennis Dalessandro4eb06882016-01-19 14:42:39 -08001976 ppd->ibport_data.rvp.z_rc_acks =
1977 get_all_cpu_total(ppd->ibport_data.rvp.rc_acks);
1978 ppd->ibport_data.rvp.z_rc_qacks =
1979 get_all_cpu_total(ppd->ibport_data.rvp.rc_qacks);
Mike Marciniszyn77241052015-07-30 15:17:43 -04001980 }
1981}
1982
1983/* Control LED state */
1984static inline void setextled(struct hfi1_devdata *dd, u32 on)
1985{
1986 if (on)
1987 write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F);
1988 else
1989 write_csr(dd, DCC_CFG_LED_CNTRL, 0x10);
1990}
1991
Dean Luick765a6fa2016-03-05 08:50:06 -08001992/* return the i2c resource given the target */
1993static inline u32 i2c_target(u32 target)
1994{
1995 return target ? CR_I2C2 : CR_I2C1;
1996}
1997
1998/* return the i2c chain chip resource that this HFI uses for QSFP */
1999static inline u32 qsfp_resource(struct hfi1_devdata *dd)
2000{
2001 return i2c_target(dd->hfi1_id);
2002}
2003
Mike Marciniszyn77241052015-07-30 15:17:43 -04002004int hfi1_tempsense_rd(struct hfi1_devdata *dd, struct hfi1_temp *temp);
2005
Sebastian Sanchez462b6b22016-07-01 16:01:06 -07002006#define DD_DEV_ENTRY(dd) __string(dev, dev_name(&(dd)->pcidev->dev))
2007#define DD_DEV_ASSIGN(dd) __assign_str(dev, dev_name(&(dd)->pcidev->dev))
2008
2009#define packettype_name(etype) { RHF_RCV_TYPE_##etype, #etype }
2010#define show_packettype(etype) \
2011__print_symbolic(etype, \
2012 packettype_name(EXPECTED), \
2013 packettype_name(EAGER), \
2014 packettype_name(IB), \
2015 packettype_name(ERROR), \
2016 packettype_name(BYPASS))
2017
2018#define ib_opcode_name(opcode) { IB_OPCODE_##opcode, #opcode }
2019#define show_ib_opcode(opcode) \
2020__print_symbolic(opcode, \
2021 ib_opcode_name(RC_SEND_FIRST), \
2022 ib_opcode_name(RC_SEND_MIDDLE), \
2023 ib_opcode_name(RC_SEND_LAST), \
2024 ib_opcode_name(RC_SEND_LAST_WITH_IMMEDIATE), \
2025 ib_opcode_name(RC_SEND_ONLY), \
2026 ib_opcode_name(RC_SEND_ONLY_WITH_IMMEDIATE), \
2027 ib_opcode_name(RC_RDMA_WRITE_FIRST), \
2028 ib_opcode_name(RC_RDMA_WRITE_MIDDLE), \
2029 ib_opcode_name(RC_RDMA_WRITE_LAST), \
2030 ib_opcode_name(RC_RDMA_WRITE_LAST_WITH_IMMEDIATE), \
2031 ib_opcode_name(RC_RDMA_WRITE_ONLY), \
2032 ib_opcode_name(RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE), \
2033 ib_opcode_name(RC_RDMA_READ_REQUEST), \
2034 ib_opcode_name(RC_RDMA_READ_RESPONSE_FIRST), \
2035 ib_opcode_name(RC_RDMA_READ_RESPONSE_MIDDLE), \
2036 ib_opcode_name(RC_RDMA_READ_RESPONSE_LAST), \
2037 ib_opcode_name(RC_RDMA_READ_RESPONSE_ONLY), \
2038 ib_opcode_name(RC_ACKNOWLEDGE), \
2039 ib_opcode_name(RC_ATOMIC_ACKNOWLEDGE), \
2040 ib_opcode_name(RC_COMPARE_SWAP), \
2041 ib_opcode_name(RC_FETCH_ADD), \
2042 ib_opcode_name(UC_SEND_FIRST), \
2043 ib_opcode_name(UC_SEND_MIDDLE), \
2044 ib_opcode_name(UC_SEND_LAST), \
2045 ib_opcode_name(UC_SEND_LAST_WITH_IMMEDIATE), \
2046 ib_opcode_name(UC_SEND_ONLY), \
2047 ib_opcode_name(UC_SEND_ONLY_WITH_IMMEDIATE), \
2048 ib_opcode_name(UC_RDMA_WRITE_FIRST), \
2049 ib_opcode_name(UC_RDMA_WRITE_MIDDLE), \
2050 ib_opcode_name(UC_RDMA_WRITE_LAST), \
2051 ib_opcode_name(UC_RDMA_WRITE_LAST_WITH_IMMEDIATE), \
2052 ib_opcode_name(UC_RDMA_WRITE_ONLY), \
2053 ib_opcode_name(UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE), \
2054 ib_opcode_name(UD_SEND_ONLY), \
2055 ib_opcode_name(UD_SEND_ONLY_WITH_IMMEDIATE), \
2056 ib_opcode_name(CNP))
Mike Marciniszyn77241052015-07-30 15:17:43 -04002057#endif /* _HFI1_KERNEL_H */