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gerrit-public.fairphone.software / kernel / msm-4.9 / ecfd6c7f05db5c3f41f846d489861646e0934b56 / . / arch / arm / boot / dts / tegra30-cardhu.dtsi
blob: ff6b68fe08af14211032dbb1cbf290e34ee37b90 [file] [log] [blame]
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]1/include/ "tegra30.dtsi"
2
Laxman Dewangan640a7af2012-08-09 16:30:38 +0530[diff] [blame]3/**
4 * This file contains common DT entry for all fab version of Cardhu.
5 * There is multiple fab version of Cardhu starting from A01 to A07.
6 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
7 * A02 will have different sets of GPIOs for fixed regulator compare to
8 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
9 * compatible with fab version A04. Based on Cardhu fab version, the
10 * related dts file need to be chosen like for Cardhu fab version A02,
11 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
12 * tegra30-cardhu-a04.dts.
13 * The identification of board is done in two ways, by looking the sticker
14 * on PCB and by reading board id eeprom.
15 * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
16 * number is the fab version like here it is 002 and hence fab version A02.
17 * The (downstream internal) U-Boot of Cardhu display the board-id as
18 * follows:
19 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
20 * In this Fab version is 02 i.e. A02.
21 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
22 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
23 * wide.
24 */
25
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]26/ {
27 model = "NVIDIA Tegra30 Cardhu evaluation board";
28 compatible = "nvidia,cardhu", "nvidia,tegra30";
29
30 memory {
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]31 reg = <0x80000000 0x40000000>;
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]32 };
33
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]34 pinmux {
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]35 pinctrl-names = "default";
36 pinctrl-0 = <&state_default>;
37
38 state_default: pinmux {
39 sdmmc1_clk_pz0 {
40 nvidia,pins = "sdmmc1_clk_pz0";
41 nvidia,function = "sdmmc1";
42 nvidia,pull = <0>;
43 nvidia,tristate = <0>;
44 };
45 sdmmc1_cmd_pz1 {
46 nvidia,pins = "sdmmc1_cmd_pz1",
47 "sdmmc1_dat0_py7",
48 "sdmmc1_dat1_py6",
49 "sdmmc1_dat2_py5",
50 "sdmmc1_dat3_py4";
51 nvidia,function = "sdmmc1";
52 nvidia,pull = <2>;
53 nvidia,tristate = <0>;
54 };
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]55 sdmmc3_clk_pa6 {
56 nvidia,pins = "sdmmc3_clk_pa6";
57 nvidia,function = "sdmmc3";
58 nvidia,pull = <0>;
59 nvidia,tristate = <0>;
60 };
61 sdmmc3_cmd_pa7 {
62 nvidia,pins = "sdmmc3_cmd_pa7",
63 "sdmmc3_dat0_pb7",
64 "sdmmc3_dat1_pb6",
65 "sdmmc3_dat2_pb5",
66 "sdmmc3_dat3_pb4";
67 nvidia,function = "sdmmc3";
68 nvidia,pull = <2>;
69 nvidia,tristate = <0>;
70 };
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]71 sdmmc4_clk_pcc4 {
72 nvidia,pins = "sdmmc4_clk_pcc4",
73 "sdmmc4_rst_n_pcc3";
74 nvidia,function = "sdmmc4";
75 nvidia,pull = <0>;
76 nvidia,tristate = <0>;
77 };
78 sdmmc4_dat0_paa0 {
79 nvidia,pins = "sdmmc4_dat0_paa0",
80 "sdmmc4_dat1_paa1",
81 "sdmmc4_dat2_paa2",
82 "sdmmc4_dat3_paa3",
83 "sdmmc4_dat4_paa4",
84 "sdmmc4_dat5_paa5",
85 "sdmmc4_dat6_paa6",
86 "sdmmc4_dat7_paa7";
87 nvidia,function = "sdmmc4";
88 nvidia,pull = <2>;
89 nvidia,tristate = <0>;
90 };
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]91 dap2_fs_pa2 {
92 nvidia,pins = "dap2_fs_pa2",
93 "dap2_sclk_pa3",
94 "dap2_din_pa4",
95 "dap2_dout_pa5";
96 nvidia,function = "i2s1";
97 nvidia,pull = <0>;
98 nvidia,tristate = <0>;
99 };
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]100 sdio3 {
101 nvidia,pins = "drive_sdio3";
102 nvidia,high-speed-mode = <0>;
103 nvidia,schmitt = <0>;
104 nvidia,pull-down-strength = <46>;
105 nvidia,pull-up-strength = <42>;
106 nvidia,slew-rate-rising = <1>;
107 nvidia,slew-rate-falling = <1>;
108 };
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame^]109 uart3_txd_pw6 {
110 nvidia,pins = "uart3_txd_pw6",
111 "uart3_cts_n_pa1",
112 "uart3_rts_n_pc0",
113 "uart3_rxd_pw7";
114 nvidia,function = "uartc";
115 nvidia,pull = <0>;
116 nvidia,tristate = <0>;
117 };
Stephen Warrene5cbeef2012-03-13 13:28:02 -0600[diff] [blame]118 };
119 };
120
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]121 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]122 status = "okay";
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]123 clock-frequency = <408000000>;
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]124 };
125
Laxman Dewanganecfd6c72013-01-16 18:36:12 +0530[diff] [blame^]126 serial@70006200 {
127 compatible = "nvidia,tegra30-hsuart";
128 status = "okay";
129 clock-frequency = <408000000>;
130 };
131
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]132 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]133 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]134 clock-frequency = <100000>;
135 };
136
137 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]138 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]139 clock-frequency = <100000>;
140 };
141
142 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]143 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]144 clock-frequency = <100000>;
Laxman Dewanganb46b0b52012-04-23 17:41:36 +0530[diff] [blame]145
146 /* ALS and Proximity sensor */
147 isl29028@44 {
148 compatible = "isil,isl29028";
149 reg = <0x44>;
150 interrupt-parent = <&gpio>;
151 interrupts = <88 0x04>; /*gpio PL0 */
152 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]153 };
154
155 i2c@7000c700 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]156 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]157 clock-frequency = <100000>;
158 };
159
160 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]161 status = "okay";
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]162 clock-frequency = <100000>;
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]163
164 wm8903: wm8903@1a {
165 compatible = "wlf,wm8903";
166 reg = <0x1a>;
167 interrupt-parent = <&gpio>;
168 interrupts = <179 0x04>; /* gpio PW3 */
169
170 gpio-controller;
171 #gpio-cells = <2>;
172
173 micdet-cfg = <0>;
174 micdet-delay = <100>;
175 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
176 };
Laxman Dewangan331da582012-05-10 20:38:45 +0000[diff] [blame]177
178 tps62361 {
179 compatible = "ti,tps62361";
180 reg = <0x60>;
181
182 regulator-name = "tps62361-vout";
183 regulator-min-microvolt = <500000>;
184 regulator-max-microvolt = <1500000>;
185 regulator-boot-on;
186 regulator-always-on;
187 ti,vsel0-state-high;
188 ti,vsel1-state-high;
189 };
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]190
191 pmic: tps65911@2d {
192 compatible = "ti,tps65911";
193 reg = <0x2d>;
194
195 interrupts = <0 86 0x4>;
196 #interrupt-cells = <2>;
197 interrupt-controller;
198
Stephen Warren44b12ef2012-09-11 11:42:26 -0600[diff] [blame]199 ti,system-power-controller;
200
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]201 #gpio-cells = <2>;
202 gpio-controller;
203
204 vcc1-supply = <&vdd_ac_bat_reg>;
205 vcc2-supply = <&vdd_ac_bat_reg>;
206 vcc3-supply = <&vio_reg>;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]207 vcc4-supply = <&vdd_5v0_reg>;
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]208 vcc5-supply = <&vdd_ac_bat_reg>;
209 vcc6-supply = <&vdd2_reg>;
210 vcc7-supply = <&vdd_ac_bat_reg>;
211 vccio-supply = <&vdd_ac_bat_reg>;
212
213 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]214 vdd1_reg: vdd1 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]215 regulator-name = "vddio_ddr_1v2";
216 regulator-min-microvolt = <1200000>;
217 regulator-max-microvolt = <1200000>;
218 regulator-always-on;
219 };
220
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]221 vdd2_reg: vdd2 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]222 regulator-name = "vdd_1v5_gen";
223 regulator-min-microvolt = <1500000>;
224 regulator-max-microvolt = <1500000>;
225 regulator-always-on;
226 };
227
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]228 vddctrl_reg: vddctrl {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]229 regulator-name = "vdd_cpu,vdd_sys";
230 regulator-min-microvolt = <1000000>;
231 regulator-max-microvolt = <1000000>;
232 regulator-always-on;
233 };
234
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]235 vio_reg: vio {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]236 regulator-name = "vdd_1v8_gen";
237 regulator-min-microvolt = <1800000>;
238 regulator-max-microvolt = <1800000>;
239 regulator-always-on;
240 };
241
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]242 ldo1_reg: ldo1 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]243 regulator-name = "vdd_pexa,vdd_pexb";
244 regulator-min-microvolt = <1050000>;
245 regulator-max-microvolt = <1050000>;
246 };
247
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]248 ldo2_reg: ldo2 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]249 regulator-name = "vdd_sata,avdd_plle";
250 regulator-min-microvolt = <1050000>;
251 regulator-max-microvolt = <1050000>;
252 };
253
254 /* LDO3 is not connected to anything */
255
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]256 ldo4_reg: ldo4 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]257 regulator-name = "vdd_rtc";
258 regulator-min-microvolt = <1200000>;
259 regulator-max-microvolt = <1200000>;
260 regulator-always-on;
261 };
262
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]263 ldo5_reg: ldo5 {
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]264 regulator-name = "vddio_sdmmc,avdd_vdac";
265 regulator-min-microvolt = <3300000>;
266 regulator-max-microvolt = <3300000>;
267 regulator-always-on;
268 };
269
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]270 ldo6_reg: ldo6 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]271 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
272 regulator-min-microvolt = <1200000>;
273 regulator-max-microvolt = <1200000>;
274 };
275
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]276 ldo7_reg: ldo7 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]277 regulator-name = "vdd_pllm,x,u,a_p_c_s";
278 regulator-min-microvolt = <1200000>;
279 regulator-max-microvolt = <1200000>;
280 regulator-always-on;
281 };
282
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]283 ldo8_reg: ldo8 {
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]284 regulator-name = "vdd_ddr_hs";
285 regulator-min-microvolt = <1000000>;
286 regulator-max-microvolt = <1000000>;
287 regulator-always-on;
288 };
289 };
290 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]291 };
Stephen Warren850c4c82012-02-01 16:29:57 -0700[diff] [blame]292
Laxman Dewanganc42cb1c2012-10-31 14:32:54 +0530[diff] [blame]293 spi@7000da00 {
294 status = "okay";
295 spi-max-frequency = <25000000>;
296 spi-flash@1 {
297 compatible = "winbond,w25q32";
298 reg = <1>;
299 spi-max-frequency = <20000000>;
300 };
301 };
302
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]303 ahub {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]304 i2s@70080400 {
305 status = "okay";
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]306 };
307 };
308
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]309 pmc {
310 status = "okay";
311 nvidia,invert-interrupt;
312 };
313
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]314 sdhci@78000000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]315 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]316 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
317 wp-gpios = <&gpio 155 0>; /* gpio PT3 */
318 power-gpios = <&gpio 31 0>; /* gpio PD7 */
Arnd Bergmann7f217792012-05-13 00:14:24 -0400[diff] [blame]319 bus-width = <4>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]320 };
321
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]322 sdhci@78000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]323 status = "okay";
Arnd Bergmann7f217792012-05-13 00:14:24 -0400[diff] [blame]324 bus-width = <8>;
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]325 };
326
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]327 regulators {
328 compatible = "simple-bus";
329 #address-cells = <1>;
330 #size-cells = <0>;
331
332 vdd_ac_bat_reg: regulator@0 {
333 compatible = "regulator-fixed";
334 reg = <0>;
335 regulator-name = "vdd_ac_bat";
336 regulator-min-microvolt = <5000000>;
337 regulator-max-microvolt = <5000000>;
338 regulator-always-on;
339 };
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]340
341 cam_1v8_reg: regulator@1 {
342 compatible = "regulator-fixed";
343 reg = <1>;
344 regulator-name = "cam_1v8";
345 regulator-min-microvolt = <1800000>;
346 regulator-max-microvolt = <1800000>;
347 enable-active-high;
348 gpio = <&gpio 220 0>; /* gpio PBB4 */
349 vin-supply = <&vio_reg>;
350 };
351
352 cp_5v_reg: regulator@2 {
353 compatible = "regulator-fixed";
354 reg = <2>;
355 regulator-name = "cp_5v";
356 regulator-min-microvolt = <5000000>;
357 regulator-max-microvolt = <5000000>;
358 regulator-boot-on;
359 regulator-always-on;
360 enable-active-high;
361 gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
362 };
363
364 emmc_3v3_reg: regulator@3 {
365 compatible = "regulator-fixed";
366 reg = <3>;
367 regulator-name = "emmc_3v3";
368 regulator-min-microvolt = <3300000>;
369 regulator-max-microvolt = <3300000>;
370 regulator-always-on;
371 regulator-boot-on;
372 enable-active-high;
373 gpio = <&gpio 25 0>; /* gpio PD1 */
374 vin-supply = <&sys_3v3_reg>;
375 };
376
377 modem_3v3_reg: regulator@4 {
378 compatible = "regulator-fixed";
379 reg = <4>;
380 regulator-name = "modem_3v3";
381 regulator-min-microvolt = <3300000>;
382 regulator-max-microvolt = <3300000>;
383 enable-active-high;
384 gpio = <&gpio 30 0>; /* gpio PD6 */
385 };
386
387 pex_hvdd_3v3_reg: regulator@5 {
388 compatible = "regulator-fixed";
389 reg = <5>;
390 regulator-name = "pex_hvdd_3v3";
391 regulator-min-microvolt = <3300000>;
392 regulator-max-microvolt = <3300000>;
393 enable-active-high;
394 gpio = <&gpio 95 0>; /* gpio PL7 */
395 vin-supply = <&sys_3v3_reg>;
396 };
397
398 vdd_cam1_ldo_reg: regulator@6 {
399 compatible = "regulator-fixed";
400 reg = <6>;
401 regulator-name = "vdd_cam1_ldo";
402 regulator-min-microvolt = <2800000>;
403 regulator-max-microvolt = <2800000>;
404 enable-active-high;
405 gpio = <&gpio 142 0>; /* gpio PR6 */
406 vin-supply = <&sys_3v3_reg>;
407 };
408
409 vdd_cam2_ldo_reg: regulator@7 {
410 compatible = "regulator-fixed";
411 reg = <7>;
412 regulator-name = "vdd_cam2_ldo";
413 regulator-min-microvolt = <2800000>;
414 regulator-max-microvolt = <2800000>;
415 enable-active-high;
416 gpio = <&gpio 143 0>; /* gpio PR7 */
417 vin-supply = <&sys_3v3_reg>;
418 };
419
420 vdd_cam3_ldo_reg: regulator@8 {
421 compatible = "regulator-fixed";
422 reg = <8>;
423 regulator-name = "vdd_cam3_ldo";
424 regulator-min-microvolt = <3300000>;
425 regulator-max-microvolt = <3300000>;
426 enable-active-high;
427 gpio = <&gpio 144 0>; /* gpio PS0 */
428 vin-supply = <&sys_3v3_reg>;
429 };
430
431 vdd_com_reg: regulator@9 {
432 compatible = "regulator-fixed";
433 reg = <9>;
434 regulator-name = "vdd_com";
435 regulator-min-microvolt = <3300000>;
436 regulator-max-microvolt = <3300000>;
Wei Ni6fb11132012-09-21 16:54:59 +0800[diff] [blame]437 regulator-always-on;
438 regulator-boot-on;
Laxman Dewanganfa4a9252012-08-09 16:30:39 +0530[diff] [blame]439 enable-active-high;
440 gpio = <&gpio 24 0>; /* gpio PD0 */
441 vin-supply = <&sys_3v3_reg>;
442 };
443
444 vdd_fuse_3v3_reg: regulator@10 {
445 compatible = "regulator-fixed";
446 reg = <10>;
447 regulator-name = "vdd_fuse_3v3";
448 regulator-min-microvolt = <3300000>;
449 regulator-max-microvolt = <3300000>;
450 enable-active-high;
451 gpio = <&gpio 94 0>; /* gpio PL6 */
452 vin-supply = <&sys_3v3_reg>;
453 };
454
455 vdd_pnl1_reg: regulator@11 {
456 compatible = "regulator-fixed";
457 reg = <11>;
458 regulator-name = "vdd_pnl1";
459 regulator-min-microvolt = <3300000>;
460 regulator-max-microvolt = <3300000>;
461 regulator-always-on;
462 regulator-boot-on;
463 enable-active-high;
464 gpio = <&gpio 92 0>; /* gpio PL4 */
465 vin-supply = <&sys_3v3_reg>;
466 };
467
468 vdd_vid_reg: regulator@12 {
469 compatible = "regulator-fixed";
470 reg = <12>;
471 regulator-name = "vddio_vid";
472 regulator-min-microvolt = <5000000>;
473 regulator-max-microvolt = <5000000>;
474 enable-active-high;
475 gpio = <&gpio 152 0>; /* GPIO PT0 */
476 gpio-open-drain;
477 vin-supply = <&vdd_5v0_reg>;
478 };
Laxman Dewangan167e6272012-08-09 16:30:37 +0530[diff] [blame]479 };
480
Stephen Warren8c6a3852012-03-27 12:41:37 -0600[diff] [blame]481 sound {
482 compatible = "nvidia,tegra-audio-wm8903-cardhu",
483 "nvidia,tegra-audio-wm8903";
484 nvidia,model = "NVIDIA Tegra Cardhu";
485
486 nvidia,audio-routing =
487 "Headphone Jack", "HPOUTR",
488 "Headphone Jack", "HPOUTL",
489 "Int Spk", "ROP",
490 "Int Spk", "RON",
491 "Int Spk", "LOP",
492 "Int Spk", "LON",
493 "Mic Jack", "MICBIAS",
494 "IN1L", "Mic Jack";
495
496 nvidia,i2s-controller = <&tegra_i2s1>;
497 nvidia,audio-codec = <&wm8903>;
498
499 nvidia,spkr-en-gpios = <&wm8903 2 0>;
500 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
501 };
Peter De Schrijver64c4e9f2011-12-14 17:03:26 +0200[diff] [blame]502};