Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* linux/drivers/mtd/nand/s3c2410.c |
| 2 | * |
Ben Dooks | 7e74a50 | 2008-05-20 17:32:27 +0100 | [diff] [blame] | 3 | * Copyright © 2004-2008 Simtec Electronics |
| 4 | * http://armlinux.simtec.co.uk/ |
Ben Dooks | fdf2fd5 | 2005-02-18 14:46:15 +0000 | [diff] [blame] | 5 | * Ben Dooks <ben@simtec.co.uk> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * |
Ben Dooks | 7e74a50 | 2008-05-20 17:32:27 +0100 | [diff] [blame] | 7 | * Samsung S3C2410/S3C2440/S3C2412 NAND driver |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | */ |
| 23 | |
Sachin Kamat | 92aeb5d | 2012-07-16 16:02:23 +0530 | [diff] [blame] | 24 | #define pr_fmt(fmt) "nand-s3c2410: " fmt |
| 25 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 26 | #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG |
| 27 | #define DEBUG |
| 28 | #endif |
| 29 | |
| 30 | #include <linux/module.h> |
| 31 | #include <linux/types.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | #include <linux/kernel.h> |
| 33 | #include <linux/string.h> |
Sachin Kamat | d2a89be | 2012-07-16 16:02:24 +0530 | [diff] [blame] | 34 | #include <linux/io.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | #include <linux/ioport.h> |
Russell King | d052d1b | 2005-10-29 19:07:23 +0100 | [diff] [blame] | 36 | #include <linux/platform_device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | #include <linux/delay.h> |
| 38 | #include <linux/err.h> |
Tim Schmielau | 4e57b68 | 2005-10-30 15:03:48 -0800 | [diff] [blame] | 39 | #include <linux/slab.h> |
Russell King | f8ce254 | 2006-01-07 16:15:52 +0000 | [diff] [blame] | 40 | #include <linux/clk.h> |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 41 | #include <linux/cpufreq.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 42 | |
| 43 | #include <linux/mtd/mtd.h> |
| 44 | #include <linux/mtd/nand.h> |
| 45 | #include <linux/mtd/nand_ecc.h> |
| 46 | #include <linux/mtd/partitions.h> |
| 47 | |
Arnd Bergmann | 436d42c | 2012-08-24 15:22:12 +0200 | [diff] [blame] | 48 | #include <linux/platform_data/mtd-nand-s3c2410.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | |
Sachin Kamat | 02d0186 | 2014-01-10 11:24:13 +0530 | [diff] [blame] | 50 | #define S3C2410_NFREG(x) (x) |
| 51 | |
| 52 | #define S3C2410_NFCONF S3C2410_NFREG(0x00) |
| 53 | #define S3C2410_NFCMD S3C2410_NFREG(0x04) |
| 54 | #define S3C2410_NFADDR S3C2410_NFREG(0x08) |
| 55 | #define S3C2410_NFDATA S3C2410_NFREG(0x0C) |
| 56 | #define S3C2410_NFSTAT S3C2410_NFREG(0x10) |
| 57 | #define S3C2410_NFECC S3C2410_NFREG(0x14) |
| 58 | #define S3C2440_NFCONT S3C2410_NFREG(0x04) |
| 59 | #define S3C2440_NFCMD S3C2410_NFREG(0x08) |
| 60 | #define S3C2440_NFADDR S3C2410_NFREG(0x0C) |
| 61 | #define S3C2440_NFDATA S3C2410_NFREG(0x10) |
| 62 | #define S3C2440_NFSTAT S3C2410_NFREG(0x20) |
| 63 | #define S3C2440_NFMECC0 S3C2410_NFREG(0x2C) |
| 64 | #define S3C2412_NFSTAT S3C2410_NFREG(0x28) |
| 65 | #define S3C2412_NFMECC0 S3C2410_NFREG(0x34) |
| 66 | #define S3C2410_NFCONF_EN (1<<15) |
| 67 | #define S3C2410_NFCONF_INITECC (1<<12) |
| 68 | #define S3C2410_NFCONF_nFCE (1<<11) |
| 69 | #define S3C2410_NFCONF_TACLS(x) ((x)<<8) |
| 70 | #define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) |
| 71 | #define S3C2410_NFCONF_TWRPH1(x) ((x)<<0) |
| 72 | #define S3C2410_NFSTAT_BUSY (1<<0) |
| 73 | #define S3C2440_NFCONF_TACLS(x) ((x)<<12) |
| 74 | #define S3C2440_NFCONF_TWRPH0(x) ((x)<<8) |
| 75 | #define S3C2440_NFCONF_TWRPH1(x) ((x)<<4) |
| 76 | #define S3C2440_NFCONT_INITECC (1<<4) |
| 77 | #define S3C2440_NFCONT_nFCE (1<<1) |
| 78 | #define S3C2440_NFCONT_ENABLE (1<<0) |
| 79 | #define S3C2440_NFSTAT_READY (1<<0) |
| 80 | #define S3C2412_NFCONF_NANDBOOT (1<<31) |
| 81 | #define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5) |
| 82 | #define S3C2412_NFCONT_nFCE0 (1<<1) |
| 83 | #define S3C2412_NFSTAT_READY (1<<0) |
| 84 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 85 | /* new oob placement block for use with hardware ecc generation |
| 86 | */ |
| 87 | |
Thomas Gleixner | 5bd34c0 | 2006-05-27 22:16:10 +0200 | [diff] [blame] | 88 | static struct nand_ecclayout nand_hw_eccoob = { |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 89 | .eccbytes = 3, |
| 90 | .eccpos = {0, 1, 2}, |
| 91 | .oobfree = {{8, 8}} |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | }; |
| 93 | |
| 94 | /* controller and mtd information */ |
| 95 | |
| 96 | struct s3c2410_nand_info; |
| 97 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 98 | /** |
| 99 | * struct s3c2410_nand_mtd - driver MTD structure |
| 100 | * @mtd: The MTD instance to pass to the MTD layer. |
| 101 | * @chip: The NAND chip information. |
| 102 | * @set: The platform information supplied for this set of NAND chips. |
| 103 | * @info: Link back to the hardware information. |
| 104 | * @scan_res: The result from calling nand_scan_ident(). |
| 105 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 106 | struct s3c2410_nand_mtd { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 107 | struct nand_chip chip; |
| 108 | struct s3c2410_nand_set *set; |
| 109 | struct s3c2410_nand_info *info; |
| 110 | int scan_res; |
| 111 | }; |
| 112 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 113 | enum s3c_cpu_type { |
| 114 | TYPE_S3C2410, |
| 115 | TYPE_S3C2412, |
| 116 | TYPE_S3C2440, |
| 117 | }; |
| 118 | |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 119 | enum s3c_nand_clk_state { |
| 120 | CLOCK_DISABLE = 0, |
| 121 | CLOCK_ENABLE, |
| 122 | CLOCK_SUSPEND, |
| 123 | }; |
| 124 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 125 | /* overview of the s3c2410 nand state */ |
| 126 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 127 | /** |
| 128 | * struct s3c2410_nand_info - NAND controller state. |
| 129 | * @mtds: An array of MTD instances on this controoler. |
| 130 | * @platform: The platform data for this board. |
| 131 | * @device: The platform device we bound to. |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 132 | * @clk: The clock resource for this controller. |
Sachin Kamat | 6f32a3e | 2012-08-21 14:24:09 +0530 | [diff] [blame] | 133 | * @regs: The area mapped for the hardware registers. |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 134 | * @sel_reg: Pointer to the register controlling the NAND selection. |
| 135 | * @sel_bit: The bit in @sel_reg to select the NAND chip. |
| 136 | * @mtd_count: The number of MTDs created from this controller. |
| 137 | * @save_sel: The contents of @sel_reg to be saved over suspend. |
| 138 | * @clk_rate: The clock rate from @clk. |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 139 | * @clk_state: The current clock state. |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 140 | * @cpu_type: The exact type of this controller. |
| 141 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 142 | struct s3c2410_nand_info { |
| 143 | /* mtd info */ |
| 144 | struct nand_hw_control controller; |
| 145 | struct s3c2410_nand_mtd *mtds; |
| 146 | struct s3c2410_platform_nand *platform; |
| 147 | |
| 148 | /* device info */ |
| 149 | struct device *device; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 150 | struct clk *clk; |
Ben Dooks | fdf2fd5 | 2005-02-18 14:46:15 +0000 | [diff] [blame] | 151 | void __iomem *regs; |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 152 | void __iomem *sel_reg; |
| 153 | int sel_bit; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 154 | int mtd_count; |
Ben Dooks | 0916083 | 2008-04-15 11:36:18 +0100 | [diff] [blame] | 155 | unsigned long save_sel; |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 156 | unsigned long clk_rate; |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 157 | enum s3c_nand_clk_state clk_state; |
Ben Dooks | 03680b1 | 2007-11-19 23:28:07 +0000 | [diff] [blame] | 158 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 159 | enum s3c_cpu_type cpu_type; |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 160 | |
| 161 | #ifdef CONFIG_CPU_FREQ |
| 162 | struct notifier_block freq_transition; |
| 163 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | }; |
| 165 | |
| 166 | /* conversion functions */ |
| 167 | |
| 168 | static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd) |
| 169 | { |
Boris BREZILLON | 7208b99 | 2015-12-10 09:00:22 +0100 | [diff] [blame] | 170 | return container_of(mtd_to_nand(mtd), struct s3c2410_nand_mtd, |
| 171 | chip); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 172 | } |
| 173 | |
| 174 | static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd) |
| 175 | { |
| 176 | return s3c2410_nand_mtd_toours(mtd)->info; |
| 177 | } |
| 178 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 179 | static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 180 | { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 181 | return platform_get_drvdata(dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 182 | } |
| 183 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 184 | static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 185 | { |
Jingoo Han | 453810b | 2013-07-30 17:18:33 +0900 | [diff] [blame] | 186 | return dev_get_platdata(&dev->dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 187 | } |
| 188 | |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 189 | static inline int allow_clk_suspend(struct s3c2410_nand_info *info) |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 190 | { |
Sachin Kamat | a68c5ec | 2012-07-16 16:02:25 +0530 | [diff] [blame] | 191 | #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP |
| 192 | return 1; |
| 193 | #else |
| 194 | return 0; |
| 195 | #endif |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 196 | } |
| 197 | |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 198 | /** |
| 199 | * s3c2410_nand_clk_set_state - Enable, disable or suspend NAND clock. |
| 200 | * @info: The controller instance. |
| 201 | * @new_state: State to which clock should be set. |
| 202 | */ |
| 203 | static void s3c2410_nand_clk_set_state(struct s3c2410_nand_info *info, |
| 204 | enum s3c_nand_clk_state new_state) |
| 205 | { |
| 206 | if (!allow_clk_suspend(info) && new_state == CLOCK_SUSPEND) |
| 207 | return; |
| 208 | |
| 209 | if (info->clk_state == CLOCK_ENABLE) { |
| 210 | if (new_state != CLOCK_ENABLE) |
Vasily Khoruzhick | 887957b | 2014-06-30 22:12:16 +0300 | [diff] [blame] | 211 | clk_disable_unprepare(info->clk); |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 212 | } else { |
| 213 | if (new_state == CLOCK_ENABLE) |
Vasily Khoruzhick | 887957b | 2014-06-30 22:12:16 +0300 | [diff] [blame] | 214 | clk_prepare_enable(info->clk); |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 215 | } |
| 216 | |
| 217 | info->clk_state = new_state; |
| 218 | } |
| 219 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 220 | /* timing calculations */ |
| 221 | |
Ben Dooks | cfd320f | 2005-10-20 22:22:58 +0100 | [diff] [blame] | 222 | #define NS_IN_KHZ 1000000 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 223 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 224 | /** |
| 225 | * s3c_nand_calc_rate - calculate timing data. |
| 226 | * @wanted: The cycle time in nanoseconds. |
| 227 | * @clk: The clock rate in kHz. |
| 228 | * @max: The maximum divider value. |
| 229 | * |
| 230 | * Calculate the timing value from the given parameters. |
| 231 | */ |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 232 | static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 233 | { |
| 234 | int result; |
| 235 | |
Ben Dooks | 947391c | 2009-05-30 18:34:16 +0100 | [diff] [blame] | 236 | result = DIV_ROUND_UP((wanted * clk), NS_IN_KHZ); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 237 | |
| 238 | pr_debug("result %d from %ld, %d\n", result, clk, wanted); |
| 239 | |
| 240 | if (result > max) { |
Sachin Kamat | 92aeb5d | 2012-07-16 16:02:23 +0530 | [diff] [blame] | 241 | pr_err("%d ns is too big for current clock rate %ld\n", |
| 242 | wanted, clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 243 | return -1; |
| 244 | } |
| 245 | |
| 246 | if (result < 1) |
| 247 | result = 1; |
| 248 | |
| 249 | return result; |
| 250 | } |
| 251 | |
Sachin Kamat | 54cd020 | 2012-07-16 16:02:26 +0530 | [diff] [blame] | 252 | #define to_ns(ticks, clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 253 | |
| 254 | /* controller setup */ |
| 255 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 256 | /** |
| 257 | * s3c2410_nand_setrate - setup controller timing information. |
| 258 | * @info: The controller instance. |
| 259 | * |
| 260 | * Given the information supplied by the platform, calculate and set |
| 261 | * the necessary timing registers in the hardware to generate the |
| 262 | * necessary timing cycles to the hardware. |
| 263 | */ |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 264 | static int s3c2410_nand_setrate(struct s3c2410_nand_info *info) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 265 | { |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 266 | struct s3c2410_platform_nand *plat = info->platform; |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 267 | int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4; |
Ben Dooks | cfd320f | 2005-10-20 22:22:58 +0100 | [diff] [blame] | 268 | int tacls, twrph0, twrph1; |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 269 | unsigned long clkrate = clk_get_rate(info->clk); |
Nelson Castillo | 2612e52 | 2009-05-10 15:41:54 -0500 | [diff] [blame] | 270 | unsigned long uninitialized_var(set), cfg, uninitialized_var(mask); |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 271 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 272 | |
| 273 | /* calculate the timing information for the controller */ |
| 274 | |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 275 | info->clk_rate = clkrate; |
Ben Dooks | cfd320f | 2005-10-20 22:22:58 +0100 | [diff] [blame] | 276 | clkrate /= 1000; /* turn clock into kHz for ease of use */ |
| 277 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 278 | if (plat != NULL) { |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 279 | tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max); |
| 280 | twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8); |
| 281 | twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 282 | } else { |
| 283 | /* default timings */ |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 284 | tacls = tacls_max; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 285 | twrph0 = 8; |
| 286 | twrph1 = 8; |
| 287 | } |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 288 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 289 | if (tacls < 0 || twrph0 < 0 || twrph1 < 0) { |
Ben Dooks | 99974c6 | 2006-06-21 15:43:05 +0100 | [diff] [blame] | 290 | dev_err(info->device, "cannot get suitable timings\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 291 | return -EINVAL; |
| 292 | } |
| 293 | |
Ben Dooks | 99974c6 | 2006-06-21 15:43:05 +0100 | [diff] [blame] | 294 | dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n", |
Sachin Kamat | 54cd020 | 2012-07-16 16:02:26 +0530 | [diff] [blame] | 295 | tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), |
| 296 | twrph1, to_ns(twrph1, clkrate)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 297 | |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 298 | switch (info->cpu_type) { |
| 299 | case TYPE_S3C2410: |
| 300 | mask = (S3C2410_NFCONF_TACLS(3) | |
| 301 | S3C2410_NFCONF_TWRPH0(7) | |
| 302 | S3C2410_NFCONF_TWRPH1(7)); |
| 303 | set = S3C2410_NFCONF_EN; |
| 304 | set |= S3C2410_NFCONF_TACLS(tacls - 1); |
| 305 | set |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); |
| 306 | set |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); |
| 307 | break; |
| 308 | |
| 309 | case TYPE_S3C2440: |
| 310 | case TYPE_S3C2412: |
Peter Korsgaard | a755a38 | 2009-06-03 13:46:54 +0200 | [diff] [blame] | 311 | mask = (S3C2440_NFCONF_TACLS(tacls_max - 1) | |
| 312 | S3C2440_NFCONF_TWRPH0(7) | |
| 313 | S3C2440_NFCONF_TWRPH1(7)); |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 314 | |
| 315 | set = S3C2440_NFCONF_TACLS(tacls - 1); |
| 316 | set |= S3C2440_NFCONF_TWRPH0(twrph0 - 1); |
| 317 | set |= S3C2440_NFCONF_TWRPH1(twrph1 - 1); |
| 318 | break; |
| 319 | |
| 320 | default: |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 321 | BUG(); |
| 322 | } |
| 323 | |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 324 | local_irq_save(flags); |
| 325 | |
| 326 | cfg = readl(info->regs + S3C2410_NFCONF); |
| 327 | cfg &= ~mask; |
| 328 | cfg |= set; |
| 329 | writel(cfg, info->regs + S3C2410_NFCONF); |
| 330 | |
| 331 | local_irq_restore(flags); |
| 332 | |
Andy Green | ae7304e | 2009-05-10 15:42:02 -0500 | [diff] [blame] | 333 | dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg); |
| 334 | |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 335 | return 0; |
| 336 | } |
| 337 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 338 | /** |
| 339 | * s3c2410_nand_inithw - basic hardware initialisation |
| 340 | * @info: The hardware state. |
| 341 | * |
| 342 | * Do the basic initialisation of the hardware, using s3c2410_nand_setrate() |
| 343 | * to setup the hardware access speeds and set the controller to be enabled. |
| 344 | */ |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 345 | static int s3c2410_nand_inithw(struct s3c2410_nand_info *info) |
| 346 | { |
| 347 | int ret; |
| 348 | |
| 349 | ret = s3c2410_nand_setrate(info); |
| 350 | if (ret < 0) |
| 351 | return ret; |
| 352 | |
Sachin Kamat | 54cd020 | 2012-07-16 16:02:26 +0530 | [diff] [blame] | 353 | switch (info->cpu_type) { |
| 354 | case TYPE_S3C2410: |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 355 | default: |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 356 | break; |
| 357 | |
Sachin Kamat | 54cd020 | 2012-07-16 16:02:26 +0530 | [diff] [blame] | 358 | case TYPE_S3C2440: |
| 359 | case TYPE_S3C2412: |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 360 | /* enable the controller and de-assert nFCE */ |
| 361 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 362 | writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT); |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 363 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 364 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 365 | return 0; |
| 366 | } |
| 367 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 368 | /** |
| 369 | * s3c2410_nand_select_chip - select the given nand chip |
| 370 | * @mtd: The MTD instance for this chip. |
| 371 | * @chip: The chip number. |
| 372 | * |
| 373 | * This is called by the MTD layer to either select a given chip for the |
| 374 | * @mtd instance, or to indicate that the access has finished and the |
| 375 | * chip can be de-selected. |
| 376 | * |
| 377 | * The routine ensures that the nFCE line is correctly setup, and any |
| 378 | * platform specific selection code is called to route nFCE to the specific |
| 379 | * chip. |
| 380 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 381 | static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip) |
| 382 | { |
| 383 | struct s3c2410_nand_info *info; |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 384 | struct s3c2410_nand_mtd *nmtd; |
Boris BREZILLON | 4bd4ebc | 2015-12-01 12:03:04 +0100 | [diff] [blame] | 385 | struct nand_chip *this = mtd_to_nand(mtd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 386 | unsigned long cur; |
| 387 | |
Boris BREZILLON | d699ed2 | 2015-12-10 09:00:41 +0100 | [diff] [blame] | 388 | nmtd = nand_get_controller_data(this); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 389 | info = nmtd->info; |
| 390 | |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 391 | if (chip != -1) |
| 392 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 393 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 394 | cur = readl(info->sel_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 395 | |
| 396 | if (chip == -1) { |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 397 | cur |= info->sel_bit; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 398 | } else { |
Ben Dooks | fb8d82a | 2005-07-06 21:05:10 +0100 | [diff] [blame] | 399 | if (nmtd->set != NULL && chip > nmtd->set->nr_chips) { |
Ben Dooks | 99974c6 | 2006-06-21 15:43:05 +0100 | [diff] [blame] | 400 | dev_err(info->device, "invalid chip %d\n", chip); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 401 | return; |
| 402 | } |
| 403 | |
| 404 | if (info->platform != NULL) { |
| 405 | if (info->platform->select_chip != NULL) |
David Woodhouse | e0c7d76 | 2006-05-13 18:07:53 +0100 | [diff] [blame] | 406 | (info->platform->select_chip) (nmtd->set, chip); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 407 | } |
| 408 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 409 | cur &= ~info->sel_bit; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 410 | } |
| 411 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 412 | writel(cur, info->sel_reg); |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 413 | |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 414 | if (chip == -1) |
| 415 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 416 | } |
| 417 | |
Ben Dooks | ad3b5fb | 2006-06-19 09:43:23 +0100 | [diff] [blame] | 418 | /* s3c2410_nand_hwcontrol |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 419 | * |
Ben Dooks | ad3b5fb | 2006-06-19 09:43:23 +0100 | [diff] [blame] | 420 | * Issue command and address cycles to the chip |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 421 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 422 | |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 423 | static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
David Woodhouse | f906887 | 2006-06-10 00:53:16 +0100 | [diff] [blame] | 424 | unsigned int ctrl) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 425 | { |
| 426 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
David Woodhouse | c9ac597 | 2006-11-30 08:17:38 +0000 | [diff] [blame] | 427 | |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 428 | if (cmd == NAND_CMD_NONE) |
| 429 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 430 | |
David Woodhouse | f906887 | 2006-06-10 00:53:16 +0100 | [diff] [blame] | 431 | if (ctrl & NAND_CLE) |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 432 | writeb(cmd, info->regs + S3C2410_NFCMD); |
| 433 | else |
| 434 | writeb(cmd, info->regs + S3C2410_NFADDR); |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 435 | } |
| 436 | |
| 437 | /* command and control functions */ |
| 438 | |
David Woodhouse | f906887 | 2006-06-10 00:53:16 +0100 | [diff] [blame] | 439 | static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd, |
| 440 | unsigned int ctrl) |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 441 | { |
| 442 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 443 | |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 444 | if (cmd == NAND_CMD_NONE) |
| 445 | return; |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 446 | |
David Woodhouse | f906887 | 2006-06-10 00:53:16 +0100 | [diff] [blame] | 447 | if (ctrl & NAND_CLE) |
Thomas Gleixner | 7abd3ef | 2006-05-23 23:25:53 +0200 | [diff] [blame] | 448 | writeb(cmd, info->regs + S3C2440_NFCMD); |
| 449 | else |
| 450 | writeb(cmd, info->regs + S3C2440_NFADDR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 451 | } |
| 452 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 453 | /* s3c2410_nand_devready() |
| 454 | * |
| 455 | * returns 0 if the nand is busy, 1 if it is ready |
| 456 | */ |
| 457 | |
| 458 | static int s3c2410_nand_devready(struct mtd_info *mtd) |
| 459 | { |
| 460 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 461 | return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY; |
| 462 | } |
| 463 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 464 | static int s3c2440_nand_devready(struct mtd_info *mtd) |
| 465 | { |
| 466 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 467 | return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY; |
| 468 | } |
| 469 | |
| 470 | static int s3c2412_nand_devready(struct mtd_info *mtd) |
| 471 | { |
| 472 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 473 | return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY; |
| 474 | } |
| 475 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 476 | /* ECC handling functions */ |
| 477 | |
Sachin Kamat | 19da415 | 2012-08-21 14:24:10 +0530 | [diff] [blame] | 478 | #ifdef CONFIG_MTD_NAND_S3C2410_HWECC |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 479 | static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, |
| 480 | u_char *read_ecc, u_char *calc_ecc) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 481 | { |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 482 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 483 | unsigned int diff0, diff1, diff2; |
| 484 | unsigned int bit, byte; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 485 | |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 486 | pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 487 | |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 488 | diff0 = read_ecc[0] ^ calc_ecc[0]; |
| 489 | diff1 = read_ecc[1] ^ calc_ecc[1]; |
| 490 | diff2 = read_ecc[2] ^ calc_ecc[2]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 491 | |
Andy Shevchenko | 13e8597 | 2012-08-02 16:06:47 +0300 | [diff] [blame] | 492 | pr_debug("%s: rd %*phN calc %*phN diff %02x%02x%02x\n", |
| 493 | __func__, 3, read_ecc, 3, calc_ecc, |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 494 | diff0, diff1, diff2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 495 | |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 496 | if (diff0 == 0 && diff1 == 0 && diff2 == 0) |
| 497 | return 0; /* ECC is ok */ |
| 498 | |
Ben Dooks | c45c6c6 | 2008-04-15 11:36:20 +0100 | [diff] [blame] | 499 | /* sometimes people do not think about using the ECC, so check |
| 500 | * to see if we have an 0xff,0xff,0xff read ECC and then ignore |
| 501 | * the error, on the assumption that this is an un-eccd page. |
| 502 | */ |
| 503 | if (read_ecc[0] == 0xff && read_ecc[1] == 0xff && read_ecc[2] == 0xff |
| 504 | && info->platform->ignore_unset_ecc) |
| 505 | return 0; |
| 506 | |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 507 | /* Can we correct this ECC (ie, one row and column change). |
| 508 | * Note, this is similar to the 256 error code on smartmedia */ |
| 509 | |
| 510 | if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 && |
| 511 | ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 && |
| 512 | ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) { |
| 513 | /* calculate the bit position of the error */ |
| 514 | |
Matt Reimer | d0bf379 | 2007-10-18 18:02:43 -0700 | [diff] [blame] | 515 | bit = ((diff2 >> 3) & 1) | |
| 516 | ((diff2 >> 4) & 2) | |
| 517 | ((diff2 >> 5) & 4); |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 518 | |
| 519 | /* calculate the byte position of the error */ |
| 520 | |
Matt Reimer | d0bf379 | 2007-10-18 18:02:43 -0700 | [diff] [blame] | 521 | byte = ((diff2 << 7) & 0x100) | |
| 522 | ((diff1 << 0) & 0x80) | |
| 523 | ((diff1 << 1) & 0x40) | |
| 524 | ((diff1 << 2) & 0x20) | |
| 525 | ((diff1 << 3) & 0x10) | |
| 526 | ((diff0 >> 4) & 0x08) | |
| 527 | ((diff0 >> 3) & 0x04) | |
| 528 | ((diff0 >> 2) & 0x02) | |
| 529 | ((diff0 >> 1) & 0x01); |
Ben Dooks | a259324 | 2007-02-02 16:59:33 +0000 | [diff] [blame] | 530 | |
| 531 | dev_dbg(info->device, "correcting error bit %d, byte %d\n", |
| 532 | bit, byte); |
| 533 | |
| 534 | dat[byte] ^= (1 << bit); |
| 535 | return 1; |
| 536 | } |
| 537 | |
| 538 | /* if there is only one bit difference in the ECC, then |
| 539 | * one of only a row or column parity has changed, which |
| 540 | * means the error is most probably in the ECC itself */ |
| 541 | |
| 542 | diff0 |= (diff1 << 8); |
| 543 | diff0 |= (diff2 << 16); |
| 544 | |
| 545 | if ((diff0 & ~(1<<fls(diff0))) == 0) |
| 546 | return 1; |
| 547 | |
Matt Reimer | 4fac9f6 | 2007-10-18 18:02:44 -0700 | [diff] [blame] | 548 | return -1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 549 | } |
| 550 | |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 551 | /* ECC functions |
| 552 | * |
| 553 | * These allow the s3c2410 and s3c2440 to use the controller's ECC |
| 554 | * generator block to ECC the data as it passes through] |
| 555 | */ |
| 556 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 557 | static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
| 558 | { |
| 559 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 560 | unsigned long ctrl; |
| 561 | |
| 562 | ctrl = readl(info->regs + S3C2410_NFCONF); |
| 563 | ctrl |= S3C2410_NFCONF_INITECC; |
| 564 | writel(ctrl, info->regs + S3C2410_NFCONF); |
| 565 | } |
| 566 | |
Matthieu CASTET | 4f65992 | 2007-02-13 12:30:38 +0100 | [diff] [blame] | 567 | static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
| 568 | { |
| 569 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 570 | unsigned long ctrl; |
| 571 | |
| 572 | ctrl = readl(info->regs + S3C2440_NFCONT); |
Sachin Kamat | f938bc5 | 2012-08-21 10:21:15 +0530 | [diff] [blame] | 573 | writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC, |
| 574 | info->regs + S3C2440_NFCONT); |
Matthieu CASTET | 4f65992 | 2007-02-13 12:30:38 +0100 | [diff] [blame] | 575 | } |
| 576 | |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 577 | static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode) |
| 578 | { |
| 579 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 580 | unsigned long ctrl; |
| 581 | |
| 582 | ctrl = readl(info->regs + S3C2440_NFCONT); |
| 583 | writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT); |
| 584 | } |
| 585 | |
Sachin Kamat | f938bc5 | 2012-08-21 10:21:15 +0530 | [diff] [blame] | 586 | static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
| 587 | u_char *ecc_code) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 588 | { |
| 589 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 590 | |
| 591 | ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0); |
| 592 | ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1); |
| 593 | ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2); |
| 594 | |
Andy Shevchenko | 13e8597 | 2012-08-02 16:06:47 +0300 | [diff] [blame] | 595 | pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 596 | |
| 597 | return 0; |
| 598 | } |
| 599 | |
Sachin Kamat | f938bc5 | 2012-08-21 10:21:15 +0530 | [diff] [blame] | 600 | static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
| 601 | u_char *ecc_code) |
Matthieu CASTET | 4f65992 | 2007-02-13 12:30:38 +0100 | [diff] [blame] | 602 | { |
| 603 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 604 | unsigned long ecc = readl(info->regs + S3C2412_NFMECC0); |
| 605 | |
| 606 | ecc_code[0] = ecc; |
| 607 | ecc_code[1] = ecc >> 8; |
| 608 | ecc_code[2] = ecc >> 16; |
| 609 | |
Andy Shevchenko | 13e8597 | 2012-08-02 16:06:47 +0300 | [diff] [blame] | 610 | pr_debug("%s: returning ecc %*phN\n", __func__, 3, ecc_code); |
Matthieu CASTET | 4f65992 | 2007-02-13 12:30:38 +0100 | [diff] [blame] | 611 | |
| 612 | return 0; |
| 613 | } |
| 614 | |
Sachin Kamat | f938bc5 | 2012-08-21 10:21:15 +0530 | [diff] [blame] | 615 | static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, |
| 616 | u_char *ecc_code) |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 617 | { |
| 618 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
| 619 | unsigned long ecc = readl(info->regs + S3C2440_NFMECC0); |
| 620 | |
| 621 | ecc_code[0] = ecc; |
| 622 | ecc_code[1] = ecc >> 8; |
| 623 | ecc_code[2] = ecc >> 16; |
| 624 | |
Ben Dooks | 71d54f3 | 2008-04-15 11:36:19 +0100 | [diff] [blame] | 625 | pr_debug("%s: returning ecc %06lx\n", __func__, ecc & 0xffffff); |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 626 | |
| 627 | return 0; |
| 628 | } |
Sachin Kamat | 19da415 | 2012-08-21 14:24:10 +0530 | [diff] [blame] | 629 | #endif |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 630 | |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 631 | /* over-ride the standard functions for a little more speed. We can |
| 632 | * use read/write block to move the data buffers to/from the controller |
| 633 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 634 | |
| 635 | static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
| 636 | { |
Boris BREZILLON | 4bd4ebc | 2015-12-01 12:03:04 +0100 | [diff] [blame] | 637 | struct nand_chip *this = mtd_to_nand(mtd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 638 | readsb(this->IO_ADDR_R, buf, len); |
| 639 | } |
| 640 | |
Matt Reimer | b773bb2 | 2007-10-18 17:43:07 -0700 | [diff] [blame] | 641 | static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) |
| 642 | { |
| 643 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
Ben Dooks | dea2aa6 | 2009-05-30 18:30:18 +0100 | [diff] [blame] | 644 | |
| 645 | readsl(info->regs + S3C2440_NFDATA, buf, len >> 2); |
| 646 | |
| 647 | /* cleanup if we've got less than a word to do */ |
| 648 | if (len & 3) { |
| 649 | buf += len & ~3; |
| 650 | |
| 651 | for (; len & 3; len--) |
| 652 | *buf++ = readb(info->regs + S3C2440_NFDATA); |
| 653 | } |
Matt Reimer | b773bb2 | 2007-10-18 17:43:07 -0700 | [diff] [blame] | 654 | } |
| 655 | |
Sachin Kamat | f938bc5 | 2012-08-21 10:21:15 +0530 | [diff] [blame] | 656 | static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, |
| 657 | int len) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 658 | { |
Boris BREZILLON | 4bd4ebc | 2015-12-01 12:03:04 +0100 | [diff] [blame] | 659 | struct nand_chip *this = mtd_to_nand(mtd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 660 | writesb(this->IO_ADDR_W, buf, len); |
| 661 | } |
| 662 | |
Sachin Kamat | f938bc5 | 2012-08-21 10:21:15 +0530 | [diff] [blame] | 663 | static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf, |
| 664 | int len) |
Matt Reimer | b773bb2 | 2007-10-18 17:43:07 -0700 | [diff] [blame] | 665 | { |
| 666 | struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); |
Ben Dooks | dea2aa6 | 2009-05-30 18:30:18 +0100 | [diff] [blame] | 667 | |
| 668 | writesl(info->regs + S3C2440_NFDATA, buf, len >> 2); |
| 669 | |
| 670 | /* cleanup any fractional write */ |
| 671 | if (len & 3) { |
| 672 | buf += len & ~3; |
| 673 | |
| 674 | for (; len & 3; len--, buf++) |
| 675 | writeb(*buf, info->regs + S3C2440_NFDATA); |
| 676 | } |
Matt Reimer | b773bb2 | 2007-10-18 17:43:07 -0700 | [diff] [blame] | 677 | } |
| 678 | |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 679 | /* cpufreq driver support */ |
| 680 | |
| 681 | #ifdef CONFIG_CPU_FREQ |
| 682 | |
| 683 | static int s3c2410_nand_cpufreq_transition(struct notifier_block *nb, |
| 684 | unsigned long val, void *data) |
| 685 | { |
| 686 | struct s3c2410_nand_info *info; |
| 687 | unsigned long newclk; |
| 688 | |
| 689 | info = container_of(nb, struct s3c2410_nand_info, freq_transition); |
| 690 | newclk = clk_get_rate(info->clk); |
| 691 | |
| 692 | if ((val == CPUFREQ_POSTCHANGE && newclk < info->clk_rate) || |
| 693 | (val == CPUFREQ_PRECHANGE && newclk > info->clk_rate)) { |
| 694 | s3c2410_nand_setrate(info); |
| 695 | } |
| 696 | |
| 697 | return 0; |
| 698 | } |
| 699 | |
| 700 | static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) |
| 701 | { |
| 702 | info->freq_transition.notifier_call = s3c2410_nand_cpufreq_transition; |
| 703 | |
| 704 | return cpufreq_register_notifier(&info->freq_transition, |
| 705 | CPUFREQ_TRANSITION_NOTIFIER); |
| 706 | } |
| 707 | |
Sachin Kamat | f938bc5 | 2012-08-21 10:21:15 +0530 | [diff] [blame] | 708 | static inline void |
| 709 | s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 710 | { |
| 711 | cpufreq_unregister_notifier(&info->freq_transition, |
| 712 | CPUFREQ_TRANSITION_NOTIFIER); |
| 713 | } |
| 714 | |
| 715 | #else |
| 716 | static inline int s3c2410_nand_cpufreq_register(struct s3c2410_nand_info *info) |
| 717 | { |
| 718 | return 0; |
| 719 | } |
| 720 | |
Sachin Kamat | f938bc5 | 2012-08-21 10:21:15 +0530 | [diff] [blame] | 721 | static inline void |
| 722 | s3c2410_nand_cpufreq_deregister(struct s3c2410_nand_info *info) |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 723 | { |
| 724 | } |
| 725 | #endif |
| 726 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 727 | /* device management functions */ |
| 728 | |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 729 | static int s3c24xx_nand_remove(struct platform_device *pdev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 730 | { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 731 | struct s3c2410_nand_info *info = to_nand_info(pdev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 732 | |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 733 | if (info == NULL) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 734 | return 0; |
| 735 | |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 736 | s3c2410_nand_cpufreq_deregister(info); |
| 737 | |
| 738 | /* Release all our mtds and their partitions, then go through |
| 739 | * freeing the resources used |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 740 | */ |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 741 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 742 | if (info->mtds != NULL) { |
| 743 | struct s3c2410_nand_mtd *ptr = info->mtds; |
| 744 | int mtdno; |
| 745 | |
| 746 | for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) { |
| 747 | pr_debug("releasing mtd %d (%p)\n", mtdno, ptr); |
Boris BREZILLON | 7208b99 | 2015-12-10 09:00:22 +0100 | [diff] [blame] | 748 | nand_release(nand_to_mtd(&ptr->chip)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 749 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 750 | } |
| 751 | |
| 752 | /* free the common resources */ |
| 753 | |
Sachin Kamat | 6f32a3e | 2012-08-21 14:24:09 +0530 | [diff] [blame] | 754 | if (!IS_ERR(info->clk)) |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 755 | s3c2410_nand_clk_set_state(info, CLOCK_DISABLE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 756 | |
| 757 | return 0; |
| 758 | } |
| 759 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 760 | static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info, |
| 761 | struct s3c2410_nand_mtd *mtd, |
| 762 | struct s3c2410_nand_set *set) |
| 763 | { |
Sachin Kamat | ded4c55 | 2012-11-16 16:08:22 +0530 | [diff] [blame] | 764 | if (set) { |
Boris BREZILLON | 7208b99 | 2015-12-10 09:00:22 +0100 | [diff] [blame] | 765 | struct mtd_info *mtdinfo = nand_to_mtd(&mtd->chip); |
Andy Green | ed27f02 | 2009-05-10 15:42:09 -0500 | [diff] [blame] | 766 | |
Boris BREZILLON | 7208b99 | 2015-12-10 09:00:22 +0100 | [diff] [blame] | 767 | mtdinfo->name = set->name; |
| 768 | |
| 769 | return mtd_device_parse_register(mtdinfo, NULL, NULL, |
Artem Bityutskiy | 42d7fbe | 2012-03-09 19:24:26 +0200 | [diff] [blame] | 770 | set->partitions, set->nr_partitions); |
Sachin Kamat | ded4c55 | 2012-11-16 16:08:22 +0530 | [diff] [blame] | 771 | } |
| 772 | |
| 773 | return -ENODEV; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 774 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 775 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 776 | /** |
| 777 | * s3c2410_nand_init_chip - initialise a single instance of an chip |
| 778 | * @info: The base NAND controller the chip is on. |
| 779 | * @nmtd: The new controller MTD instance to fill in. |
| 780 | * @set: The information passed from the board specific platform data. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 781 | * |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 782 | * Initialise the given @nmtd from the information in @info and @set. This |
| 783 | * readies the structure for use with the MTD layer functions by ensuring |
| 784 | * all pointers are setup and the necessary control routines selected. |
| 785 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 786 | static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, |
| 787 | struct s3c2410_nand_mtd *nmtd, |
| 788 | struct s3c2410_nand_set *set) |
| 789 | { |
| 790 | struct nand_chip *chip = &nmtd->chip; |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 791 | void __iomem *regs = info->regs; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 792 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 793 | chip->write_buf = s3c2410_nand_write_buf; |
| 794 | chip->read_buf = s3c2410_nand_read_buf; |
| 795 | chip->select_chip = s3c2410_nand_select_chip; |
| 796 | chip->chip_delay = 50; |
Boris BREZILLON | d699ed2 | 2015-12-10 09:00:41 +0100 | [diff] [blame] | 797 | nand_set_controller_data(chip, nmtd); |
Ben Dooks | 74218fe | 2009-11-02 18:12:51 +0000 | [diff] [blame] | 798 | chip->options = set->options; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 799 | chip->controller = &info->controller; |
| 800 | |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 801 | switch (info->cpu_type) { |
| 802 | case TYPE_S3C2410: |
| 803 | chip->IO_ADDR_W = regs + S3C2410_NFDATA; |
| 804 | info->sel_reg = regs + S3C2410_NFCONF; |
| 805 | info->sel_bit = S3C2410_NFCONF_nFCE; |
| 806 | chip->cmd_ctrl = s3c2410_nand_hwcontrol; |
| 807 | chip->dev_ready = s3c2410_nand_devready; |
| 808 | break; |
| 809 | |
| 810 | case TYPE_S3C2440: |
| 811 | chip->IO_ADDR_W = regs + S3C2440_NFDATA; |
| 812 | info->sel_reg = regs + S3C2440_NFCONT; |
| 813 | info->sel_bit = S3C2440_NFCONT_nFCE; |
| 814 | chip->cmd_ctrl = s3c2440_nand_hwcontrol; |
| 815 | chip->dev_ready = s3c2440_nand_devready; |
Matt Reimer | b773bb2 | 2007-10-18 17:43:07 -0700 | [diff] [blame] | 816 | chip->read_buf = s3c2440_nand_read_buf; |
| 817 | chip->write_buf = s3c2440_nand_write_buf; |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 818 | break; |
| 819 | |
| 820 | case TYPE_S3C2412: |
| 821 | chip->IO_ADDR_W = regs + S3C2440_NFDATA; |
| 822 | info->sel_reg = regs + S3C2440_NFCONT; |
| 823 | info->sel_bit = S3C2412_NFCONT_nFCE0; |
| 824 | chip->cmd_ctrl = s3c2440_nand_hwcontrol; |
| 825 | chip->dev_ready = s3c2412_nand_devready; |
| 826 | |
| 827 | if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT) |
| 828 | dev_info(info->device, "System booted from NAND\n"); |
| 829 | |
| 830 | break; |
Sachin Kamat | 54cd020 | 2012-07-16 16:02:26 +0530 | [diff] [blame] | 831 | } |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 832 | |
| 833 | chip->IO_ADDR_R = chip->IO_ADDR_W; |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 834 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 835 | nmtd->info = info; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 836 | nmtd->set = set; |
| 837 | |
Sachin Kamat | a68c5ec | 2012-07-16 16:02:25 +0530 | [diff] [blame] | 838 | #ifdef CONFIG_MTD_NAND_S3C2410_HWECC |
| 839 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; |
| 840 | chip->ecc.correct = s3c2410_nand_correct_data; |
| 841 | chip->ecc.mode = NAND_ECC_HW; |
| 842 | chip->ecc.strength = 1; |
| 843 | |
| 844 | switch (info->cpu_type) { |
| 845 | case TYPE_S3C2410: |
| 846 | chip->ecc.hwctl = s3c2410_nand_enable_hwecc; |
Thomas Gleixner | 6dfc6d2 | 2006-05-23 12:00:46 +0200 | [diff] [blame] | 847 | chip->ecc.calculate = s3c2410_nand_calculate_ecc; |
Sachin Kamat | a68c5ec | 2012-07-16 16:02:25 +0530 | [diff] [blame] | 848 | break; |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 849 | |
Sachin Kamat | a68c5ec | 2012-07-16 16:02:25 +0530 | [diff] [blame] | 850 | case TYPE_S3C2412: |
| 851 | chip->ecc.hwctl = s3c2412_nand_enable_hwecc; |
| 852 | chip->ecc.calculate = s3c2412_nand_calculate_ecc; |
| 853 | break; |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 854 | |
Sachin Kamat | a68c5ec | 2012-07-16 16:02:25 +0530 | [diff] [blame] | 855 | case TYPE_S3C2440: |
| 856 | chip->ecc.hwctl = s3c2440_nand_enable_hwecc; |
| 857 | chip->ecc.calculate = s3c2440_nand_calculate_ecc; |
| 858 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 859 | } |
Sachin Kamat | a68c5ec | 2012-07-16 16:02:25 +0530 | [diff] [blame] | 860 | #else |
| 861 | chip->ecc.mode = NAND_ECC_SOFT; |
| 862 | #endif |
Ben Dooks | 1c21ab6 | 2008-04-15 11:36:21 +0100 | [diff] [blame] | 863 | |
Ben Dooks | 37e5ffa | 2008-04-15 11:36:22 +0100 | [diff] [blame] | 864 | if (set->disable_ecc) |
| 865 | chip->ecc.mode = NAND_ECC_NONE; |
Andy Green | 8c3e843 | 2009-05-10 15:41:25 -0500 | [diff] [blame] | 866 | |
| 867 | switch (chip->ecc.mode) { |
| 868 | case NAND_ECC_NONE: |
| 869 | dev_info(info->device, "NAND ECC disabled\n"); |
| 870 | break; |
| 871 | case NAND_ECC_SOFT: |
| 872 | dev_info(info->device, "NAND soft ECC\n"); |
| 873 | break; |
| 874 | case NAND_ECC_HW: |
| 875 | dev_info(info->device, "NAND hardware ECC\n"); |
| 876 | break; |
| 877 | default: |
| 878 | dev_info(info->device, "NAND ECC UNKNOWN\n"); |
| 879 | break; |
| 880 | } |
Michel Pollet | 9db41f9 | 2009-05-13 16:54:14 +0100 | [diff] [blame] | 881 | |
| 882 | /* If you use u-boot BBT creation code, specifying this flag will |
| 883 | * let the kernel fish out the BBT from the NAND, and also skip the |
| 884 | * full NAND scan that can take 1/2s or so. Little things... */ |
Brian Norris | a40f734 | 2011-05-31 16:31:22 -0700 | [diff] [blame] | 885 | if (set->flash_bbt) { |
Brian Norris | bb9ebd4 | 2011-05-31 16:31:23 -0700 | [diff] [blame] | 886 | chip->bbt_options |= NAND_BBT_USE_FLASH; |
Brian Norris | a40f734 | 2011-05-31 16:31:22 -0700 | [diff] [blame] | 887 | chip->options |= NAND_SKIP_BBTSCAN; |
| 888 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 889 | } |
| 890 | |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 891 | /** |
| 892 | * s3c2410_nand_update_chip - post probe update |
| 893 | * @info: The controller instance. |
| 894 | * @nmtd: The driver version of the MTD instance. |
Ben Dooks | 71d54f3 | 2008-04-15 11:36:19 +0100 | [diff] [blame] | 895 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 896 | * This routine is called after the chip probe has successfully completed |
Ben Dooks | 3db7215 | 2009-05-30 17:18:15 +0100 | [diff] [blame] | 897 | * and the relevant per-chip information updated. This call ensure that |
| 898 | * we update the internal state accordingly. |
| 899 | * |
| 900 | * The internal state is currently limited to the ECC state information. |
| 901 | */ |
Ben Dooks | 71d54f3 | 2008-04-15 11:36:19 +0100 | [diff] [blame] | 902 | static void s3c2410_nand_update_chip(struct s3c2410_nand_info *info, |
| 903 | struct s3c2410_nand_mtd *nmtd) |
| 904 | { |
| 905 | struct nand_chip *chip = &nmtd->chip; |
| 906 | |
Ben Dooks | 451d339 | 2008-05-20 17:32:14 +0100 | [diff] [blame] | 907 | dev_dbg(info->device, "chip %p => page shift %d\n", |
| 908 | chip, chip->page_shift); |
Ben Dooks | 71d54f3 | 2008-04-15 11:36:19 +0100 | [diff] [blame] | 909 | |
Andy Green | 8c3e843 | 2009-05-10 15:41:25 -0500 | [diff] [blame] | 910 | if (chip->ecc.mode != NAND_ECC_HW) |
| 911 | return; |
| 912 | |
Adam Buchbinder | 48fc7f7 | 2012-09-19 21:48:00 -0400 | [diff] [blame] | 913 | /* change the behaviour depending on whether we are using |
Ben Dooks | 71d54f3 | 2008-04-15 11:36:19 +0100 | [diff] [blame] | 914 | * the large or small page nand device */ |
| 915 | |
Andy Green | 8c3e843 | 2009-05-10 15:41:25 -0500 | [diff] [blame] | 916 | if (chip->page_shift > 10) { |
| 917 | chip->ecc.size = 256; |
| 918 | chip->ecc.bytes = 3; |
| 919 | } else { |
| 920 | chip->ecc.size = 512; |
| 921 | chip->ecc.bytes = 3; |
| 922 | chip->ecc.layout = &nand_hw_eccoob; |
Ben Dooks | 71d54f3 | 2008-04-15 11:36:19 +0100 | [diff] [blame] | 923 | } |
| 924 | } |
| 925 | |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 926 | /* s3c24xx_nand_probe |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 927 | * |
| 928 | * called by device layer when it finds a device matching |
| 929 | * one our driver can handled. This code checks to see if |
| 930 | * it can allocate all necessary resources then calls the |
| 931 | * nand layer to look for devices |
| 932 | */ |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 933 | static int s3c24xx_nand_probe(struct platform_device *pdev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 934 | { |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 935 | struct s3c2410_platform_nand *plat = to_nand_plat(pdev); |
Sachin Kamat | 54cd020 | 2012-07-16 16:02:26 +0530 | [diff] [blame] | 936 | enum s3c_cpu_type cpu_type; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 937 | struct s3c2410_nand_info *info; |
| 938 | struct s3c2410_nand_mtd *nmtd; |
| 939 | struct s3c2410_nand_set *sets; |
| 940 | struct resource *res; |
| 941 | int err = 0; |
| 942 | int size; |
| 943 | int nr_sets; |
| 944 | int setno; |
| 945 | |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 946 | cpu_type = platform_get_device_id(pdev)->driver_data; |
| 947 | |
Sachin Kamat | 6f32a3e | 2012-08-21 14:24:09 +0530 | [diff] [blame] | 948 | info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 949 | if (info == NULL) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 950 | err = -ENOMEM; |
| 951 | goto exit_error; |
| 952 | } |
| 953 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 954 | platform_set_drvdata(pdev, info); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 955 | |
| 956 | spin_lock_init(&info->controller.lock); |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 957 | init_waitqueue_head(&info->controller.wq); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 958 | |
| 959 | /* get the clock source and enable it */ |
| 960 | |
Sachin Kamat | 6f32a3e | 2012-08-21 14:24:09 +0530 | [diff] [blame] | 961 | info->clk = devm_clk_get(&pdev->dev, "nand"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 962 | if (IS_ERR(info->clk)) { |
Joe Perches | 898eb71 | 2007-10-18 03:06:30 -0700 | [diff] [blame] | 963 | dev_err(&pdev->dev, "failed to get clock\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 964 | err = -ENOENT; |
| 965 | goto exit_error; |
| 966 | } |
| 967 | |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 968 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 969 | |
| 970 | /* allocate and map the resource */ |
| 971 | |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 972 | /* currently we assume we have the one resource */ |
Sachin Kamat | 6f32a3e | 2012-08-21 14:24:09 +0530 | [diff] [blame] | 973 | res = pdev->resource; |
H Hartley Sweeten | fc161c4 | 2009-12-14 16:56:22 -0500 | [diff] [blame] | 974 | size = resource_size(res); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 975 | |
Sachin Kamat | 6f32a3e | 2012-08-21 14:24:09 +0530 | [diff] [blame] | 976 | info->device = &pdev->dev; |
| 977 | info->platform = plat; |
| 978 | info->cpu_type = cpu_type; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 979 | |
Thierry Reding | b0de774 | 2013-01-21 11:09:12 +0100 | [diff] [blame] | 980 | info->regs = devm_ioremap_resource(&pdev->dev, res); |
| 981 | if (IS_ERR(info->regs)) { |
| 982 | err = PTR_ERR(info->regs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 983 | goto exit_error; |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 984 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 985 | |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 986 | dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 987 | |
| 988 | /* initialise the hardware */ |
| 989 | |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 990 | err = s3c2410_nand_inithw(info); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 991 | if (err != 0) |
| 992 | goto exit_error; |
| 993 | |
| 994 | sets = (plat != NULL) ? plat->sets : NULL; |
| 995 | nr_sets = (plat != NULL) ? plat->nr_sets : 1; |
| 996 | |
| 997 | info->mtd_count = nr_sets; |
| 998 | |
| 999 | /* allocate our information */ |
| 1000 | |
| 1001 | size = nr_sets * sizeof(*info->mtds); |
Sachin Kamat | 6f32a3e | 2012-08-21 14:24:09 +0530 | [diff] [blame] | 1002 | info->mtds = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1003 | if (info->mtds == NULL) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1004 | err = -ENOMEM; |
| 1005 | goto exit_error; |
| 1006 | } |
| 1007 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1008 | /* initialise all possible chips */ |
| 1009 | |
| 1010 | nmtd = info->mtds; |
| 1011 | |
| 1012 | for (setno = 0; setno < nr_sets; setno++, nmtd++) { |
Boris BREZILLON | 7208b99 | 2015-12-10 09:00:22 +0100 | [diff] [blame] | 1013 | struct mtd_info *mtd = nand_to_mtd(&nmtd->chip); |
| 1014 | |
Sachin Kamat | f938bc5 | 2012-08-21 10:21:15 +0530 | [diff] [blame] | 1015 | pr_debug("initialising set %d (%p, info %p)\n", |
| 1016 | setno, nmtd, info); |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 1017 | |
Boris BREZILLON | 7208b99 | 2015-12-10 09:00:22 +0100 | [diff] [blame] | 1018 | mtd->dev.parent = &pdev->dev; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1019 | s3c2410_nand_init_chip(info, nmtd, sets); |
| 1020 | |
Boris BREZILLON | 7208b99 | 2015-12-10 09:00:22 +0100 | [diff] [blame] | 1021 | nmtd->scan_res = nand_scan_ident(mtd, |
David Woodhouse | 5e81e88 | 2010-02-26 18:32:56 +0000 | [diff] [blame] | 1022 | (sets) ? sets->nr_chips : 1, |
| 1023 | NULL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1024 | |
| 1025 | if (nmtd->scan_res == 0) { |
Ben Dooks | 71d54f3 | 2008-04-15 11:36:19 +0100 | [diff] [blame] | 1026 | s3c2410_nand_update_chip(info, nmtd); |
Boris BREZILLON | 7208b99 | 2015-12-10 09:00:22 +0100 | [diff] [blame] | 1027 | nand_scan_tail(mtd); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1028 | s3c2410_nand_add_partition(info, nmtd, sets); |
| 1029 | } |
| 1030 | |
| 1031 | if (sets != NULL) |
| 1032 | sets++; |
| 1033 | } |
Thomas Gleixner | 61b03bd | 2005-11-07 11:15:49 +0000 | [diff] [blame] | 1034 | |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 1035 | err = s3c2410_nand_cpufreq_register(info); |
| 1036 | if (err < 0) { |
| 1037 | dev_err(&pdev->dev, "failed to init cpufreq support\n"); |
| 1038 | goto exit_error; |
| 1039 | } |
| 1040 | |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 1041 | if (allow_clk_suspend(info)) { |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 1042 | dev_info(&pdev->dev, "clock idle support enabled\n"); |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 1043 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 1044 | } |
| 1045 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1046 | return 0; |
| 1047 | |
| 1048 | exit_error: |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 1049 | s3c24xx_nand_remove(pdev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1050 | |
| 1051 | if (err == 0) |
| 1052 | err = -EINVAL; |
| 1053 | return err; |
| 1054 | } |
| 1055 | |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 1056 | /* PM Support */ |
| 1057 | #ifdef CONFIG_PM |
| 1058 | |
| 1059 | static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm) |
| 1060 | { |
| 1061 | struct s3c2410_nand_info *info = platform_get_drvdata(dev); |
| 1062 | |
| 1063 | if (info) { |
Ben Dooks | 0916083 | 2008-04-15 11:36:18 +0100 | [diff] [blame] | 1064 | info->save_sel = readl(info->sel_reg); |
Ben Dooks | 03680b1 | 2007-11-19 23:28:07 +0000 | [diff] [blame] | 1065 | |
| 1066 | /* For the moment, we must ensure nFCE is high during |
| 1067 | * the time we are suspended. This really should be |
| 1068 | * handled by suspending the MTDs we are using, but |
| 1069 | * that is currently not the case. */ |
| 1070 | |
Ben Dooks | 0916083 | 2008-04-15 11:36:18 +0100 | [diff] [blame] | 1071 | writel(info->save_sel | info->sel_bit, info->sel_reg); |
Ben Dooks | 03680b1 | 2007-11-19 23:28:07 +0000 | [diff] [blame] | 1072 | |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 1073 | s3c2410_nand_clk_set_state(info, CLOCK_DISABLE); |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 1074 | } |
| 1075 | |
| 1076 | return 0; |
| 1077 | } |
| 1078 | |
| 1079 | static int s3c24xx_nand_resume(struct platform_device *dev) |
| 1080 | { |
| 1081 | struct s3c2410_nand_info *info = platform_get_drvdata(dev); |
Ben Dooks | 0916083 | 2008-04-15 11:36:18 +0100 | [diff] [blame] | 1082 | unsigned long sel; |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 1083 | |
| 1084 | if (info) { |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 1085 | s3c2410_nand_clk_set_state(info, CLOCK_ENABLE); |
Ben Dooks | 30821fe | 2008-07-15 11:58:31 +0100 | [diff] [blame] | 1086 | s3c2410_nand_inithw(info); |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 1087 | |
Ben Dooks | 03680b1 | 2007-11-19 23:28:07 +0000 | [diff] [blame] | 1088 | /* Restore the state of the nFCE line. */ |
| 1089 | |
Ben Dooks | 0916083 | 2008-04-15 11:36:18 +0100 | [diff] [blame] | 1090 | sel = readl(info->sel_reg); |
| 1091 | sel &= ~info->sel_bit; |
| 1092 | sel |= info->save_sel & info->sel_bit; |
| 1093 | writel(sel, info->sel_reg); |
Ben Dooks | 03680b1 | 2007-11-19 23:28:07 +0000 | [diff] [blame] | 1094 | |
Jiri Pinkava | ac497c1 | 2011-04-13 11:59:30 +0200 | [diff] [blame] | 1095 | s3c2410_nand_clk_set_state(info, CLOCK_SUSPEND); |
Ben Dooks | d1fef3c | 2006-06-19 09:29:38 +0100 | [diff] [blame] | 1096 | } |
| 1097 | |
| 1098 | return 0; |
| 1099 | } |
| 1100 | |
| 1101 | #else |
| 1102 | #define s3c24xx_nand_suspend NULL |
| 1103 | #define s3c24xx_nand_resume NULL |
| 1104 | #endif |
| 1105 | |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 1106 | /* driver device registration */ |
| 1107 | |
Krzysztof Kozlowski | 0abe75d | 2015-05-02 00:50:02 +0900 | [diff] [blame] | 1108 | static const struct platform_device_id s3c24xx_driver_ids[] = { |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 1109 | { |
| 1110 | .name = "s3c2410-nand", |
| 1111 | .driver_data = TYPE_S3C2410, |
| 1112 | }, { |
| 1113 | .name = "s3c2440-nand", |
| 1114 | .driver_data = TYPE_S3C2440, |
| 1115 | }, { |
| 1116 | .name = "s3c2412-nand", |
| 1117 | .driver_data = TYPE_S3C2412, |
Peter Korsgaard | 9dbc090 | 2009-06-07 06:04:23 -0700 | [diff] [blame] | 1118 | }, { |
| 1119 | .name = "s3c6400-nand", |
| 1120 | .driver_data = TYPE_S3C2412, /* compatible with 2412 */ |
Russell King | 3ae5eae | 2005-11-09 22:32:44 +0000 | [diff] [blame] | 1121 | }, |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 1122 | { } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1123 | }; |
| 1124 | |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 1125 | MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids); |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 1126 | |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 1127 | static struct platform_driver s3c24xx_nand_driver = { |
| 1128 | .probe = s3c24xx_nand_probe, |
| 1129 | .remove = s3c24xx_nand_remove, |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 1130 | .suspend = s3c24xx_nand_suspend, |
| 1131 | .resume = s3c24xx_nand_resume, |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 1132 | .id_table = s3c24xx_driver_ids, |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 1133 | .driver = { |
Ben Dooks | ec0482e | 2009-05-30 16:55:29 +0100 | [diff] [blame] | 1134 | .name = "s3c24xx-nand", |
Ben Dooks | 2c06a08 | 2006-06-27 14:35:46 +0100 | [diff] [blame] | 1135 | }, |
| 1136 | }; |
| 1137 | |
Sachin Kamat | 056fcab | 2012-07-16 16:02:22 +0530 | [diff] [blame] | 1138 | module_platform_driver(s3c24xx_nand_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1139 | |
| 1140 | MODULE_LICENSE("GPL"); |
| 1141 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); |
Ben Dooks | a4f957f | 2005-06-20 12:48:25 +0100 | [diff] [blame] | 1142 | MODULE_DESCRIPTION("S3C24XX MTD NAND driver"); |