blob: 84ea0dca7d299ae337b7b9fa971c99a28264ed0e [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
2 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
Matt Carlsonba5b0bf2010-01-12 10:11:40 +00007 * Copyright (C) 2007-2010 Broadcom Corporation.
Linus Torvalds1da177e2005-04-16 15:20:36 -07008 */
9
10#ifndef _T3_H
11#define _T3_H
12
13#define TG3_64BIT_REG_HIGH 0x00UL
14#define TG3_64BIT_REG_LOW 0x04UL
15
16/* Descriptor block info. */
17#define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
18#define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
19#define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
20#define BDINFO_FLAGS_DISABLED 0x00000002
21#define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
22#define BDINFO_FLAGS_MAXLEN_SHIFT 16
23#define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
24#define TG3_BDINFO_SIZE 0x10UL
25
Michael Chanb5d37722006-09-27 16:06:21 -070026#define TG3_RX_INTERNAL_RING_SZ_5906 32
27
Linus Torvalds1da177e2005-04-16 15:20:36 -070028#define RX_STD_MAX_SIZE_5705 512
29#define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */
30
31/* First 256 bytes are a mirror of PCI config space. */
32#define TG3PCI_VENDOR 0x00000000
33#define TG3PCI_VENDOR_BROADCOM 0x14e4
34#define TG3PCI_DEVICE 0x00000002
35#define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */
36#define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */
37#define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */
38#define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */
Matt Carlsonc88e6682008-11-03 16:49:18 -080039#define TG3PCI_DEVICE_TIGON3_5761S 0x1688
40#define TG3PCI_DEVICE_TIGON3_5761SE 0x1689
Matt Carlson321d32a2008-11-21 17:22:19 -080041#define TG3PCI_DEVICE_TIGON3_57780 0x1692
42#define TG3PCI_DEVICE_TIGON3_57760 0x1690
43#define TG3PCI_DEVICE_TIGON3_57790 0x1694
Matt Carlson5e7ccf22009-08-25 10:08:42 +000044#define TG3PCI_DEVICE_TIGON3_57788 0x1691
Matt Carlson2befdce2009-08-28 12:28:45 +000045#define TG3PCI_DEVICE_TIGON3_5785_G 0x1699 /* GPHY */
46#define TG3PCI_DEVICE_TIGON3_5785_F 0x16a0 /* 10/100 only */
Matt Carlson5001e2f2009-11-13 13:03:51 +000047#define TG3PCI_DEVICE_TIGON3_5717 0x1655
48#define TG3PCI_DEVICE_TIGON3_5718 0x1656
49#define TG3PCI_DEVICE_TIGON3_5724 0x165c
Matt Carlsonb703df62009-12-03 08:36:21 +000050#define TG3PCI_DEVICE_TIGON3_57781 0x16b1
51#define TG3PCI_DEVICE_TIGON3_57785 0x16b5
52#define TG3PCI_DEVICE_TIGON3_57761 0x16b0
53#define TG3PCI_DEVICE_TIGON3_57765 0x16b4
54#define TG3PCI_DEVICE_TIGON3_57791 0x16b2
55#define TG3PCI_DEVICE_TIGON3_57795 0x16b6
Matt Carlson24daf2b2010-02-17 15:17:02 +000056/* 0x04 --> 0x2c unused */
57#define TG3PCI_SUBVENDOR_ID_BROADCOM PCI_VENDOR_ID_BROADCOM
58#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6 0x1644
59#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5 0x0001
60#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6 0x0002
61#define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9 0x0003
62#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1 0x0005
63#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8 0x0006
64#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7 0x0007
65#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10 0x0008
66#define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12 0x8008
67#define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1 0x0009
68#define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2 0x8009
69#define TG3PCI_SUBVENDOR_ID_3COM PCI_VENDOR_ID_3COM
70#define TG3PCI_SUBDEVICE_ID_3COM_3C996T 0x1000
71#define TG3PCI_SUBDEVICE_ID_3COM_3C996BT 0x1006
72#define TG3PCI_SUBDEVICE_ID_3COM_3C996SX 0x1004
73#define TG3PCI_SUBDEVICE_ID_3COM_3C1000T 0x1007
74#define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01 0x1008
75#define TG3PCI_SUBVENDOR_ID_DELL PCI_VENDOR_ID_DELL
76#define TG3PCI_SUBDEVICE_ID_DELL_VIPER 0x00d1
77#define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR 0x0106
78#define TG3PCI_SUBDEVICE_ID_DELL_MERLOT 0x0109
79#define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT 0x010a
80#define TG3PCI_SUBVENDOR_ID_COMPAQ PCI_VENDOR_ID_COMPAQ
81#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE 0x007c
82#define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2 0x009a
83#define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING 0x007d
84#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780 0x0085
85#define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2 0x0099
86#define TG3PCI_SUBVENDOR_ID_IBM PCI_VENDOR_ID_IBM
87#define TG3PCI_SUBDEVICE_ID_IBM_5703SAX2 0x0281
88/* 0x30 --> 0x64 unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -070089#define TG3PCI_MSI_DATA 0x00000064
90/* 0x66 --> 0x68 unused */
91#define TG3PCI_MISC_HOST_CTRL 0x00000068
92#define MISC_HOST_CTRL_CLEAR_INT 0x00000001
93#define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002
94#define MISC_HOST_CTRL_BYTE_SWAP 0x00000004
95#define MISC_HOST_CTRL_WORD_SWAP 0x00000008
96#define MISC_HOST_CTRL_PCISTATE_RW 0x00000010
97#define MISC_HOST_CTRL_CLKREG_RW 0x00000020
98#define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040
99#define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080
100#define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100
101#define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200
102#define MISC_HOST_CTRL_CHIPREV 0xffff0000
103#define MISC_HOST_CTRL_CHIPREV_SHIFT 16
104#define GET_CHIP_REV_ID(MISC_HOST_CTRL) \
105 (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
106 MISC_HOST_CTRL_CHIPREV_SHIFT)
107#define CHIPREV_ID_5700_A0 0x7000
108#define CHIPREV_ID_5700_A1 0x7001
109#define CHIPREV_ID_5700_B0 0x7100
110#define CHIPREV_ID_5700_B1 0x7101
111#define CHIPREV_ID_5700_B3 0x7102
112#define CHIPREV_ID_5700_ALTIMA 0x7104
113#define CHIPREV_ID_5700_C0 0x7200
114#define CHIPREV_ID_5701_A0 0x0000
115#define CHIPREV_ID_5701_B0 0x0100
116#define CHIPREV_ID_5701_B2 0x0102
117#define CHIPREV_ID_5701_B5 0x0105
118#define CHIPREV_ID_5703_A0 0x1000
119#define CHIPREV_ID_5703_A1 0x1001
120#define CHIPREV_ID_5703_A2 0x1002
121#define CHIPREV_ID_5703_A3 0x1003
122#define CHIPREV_ID_5704_A0 0x2000
123#define CHIPREV_ID_5704_A1 0x2001
124#define CHIPREV_ID_5704_A2 0x2002
125#define CHIPREV_ID_5704_A3 0x2003
126#define CHIPREV_ID_5705_A0 0x3000
127#define CHIPREV_ID_5705_A1 0x3001
128#define CHIPREV_ID_5705_A2 0x3002
129#define CHIPREV_ID_5705_A3 0x3003
130#define CHIPREV_ID_5750_A0 0x4000
131#define CHIPREV_ID_5750_A1 0x4001
132#define CHIPREV_ID_5750_A3 0x4003
Michael Chan52c0fd82006-06-29 20:15:54 -0700133#define CHIPREV_ID_5750_C2 0x4202
Michael Chanff645be2005-04-21 17:09:53 -0700134#define CHIPREV_ID_5752_A0_HW 0x5000
135#define CHIPREV_ID_5752_A0 0x6000
John W. Linville053d7802005-04-21 17:03:52 -0700136#define CHIPREV_ID_5752_A1 0x6001
Michael Chan7544b092007-05-05 13:08:32 -0700137#define CHIPREV_ID_5714_A2 0x9002
Michael Chanb5d37722006-09-27 16:06:21 -0700138#define CHIPREV_ID_5906_A1 0xc001
Matt Carlson9cf74eb2009-04-20 06:58:27 +0000139#define CHIPREV_ID_57780_A0 0x57780000
140#define CHIPREV_ID_57780_A1 0x57780001
Matt Carlson615774f2009-11-13 13:03:39 +0000141#define CHIPREV_ID_5717_A0 0x05717000
Matt Carlson6b10c162010-02-12 14:47:08 +0000142#define CHIPREV_ID_57765_A0 0x57785000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700143#define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
144#define ASIC_REV_5700 0x07
145#define ASIC_REV_5701 0x00
146#define ASIC_REV_5703 0x01
147#define ASIC_REV_5704 0x02
148#define ASIC_REV_5705 0x03
149#define ASIC_REV_5750 0x04
Michael Chanff645be2005-04-21 17:09:53 -0700150#define ASIC_REV_5752 0x06
Michael Chan4cf78e42005-07-25 12:29:19 -0700151#define ASIC_REV_5780 0x08
Michael Chana4e2b342005-10-26 15:46:52 -0700152#define ASIC_REV_5714 0x09
Michael Chanaf36e6b2006-03-23 01:28:06 -0800153#define ASIC_REV_5755 0x0a
Michael Chand9ab5ad2006-03-20 22:27:35 -0800154#define ASIC_REV_5787 0x0b
Michael Chanb5d37722006-09-27 16:06:21 -0700155#define ASIC_REV_5906 0x0c
Matt Carlson795d01c2007-10-07 23:28:17 -0700156#define ASIC_REV_USE_PROD_ID_REG 0x0f
Matt Carlsond30cdd22007-10-07 23:28:35 -0700157#define ASIC_REV_5784 0x5784
Matt Carlson6b91fa02007-10-10 18:01:09 -0700158#define ASIC_REV_5761 0x5761
Matt Carlson57e69832008-05-25 23:48:31 -0700159#define ASIC_REV_5785 0x5785
Matt Carlson321d32a2008-11-21 17:22:19 -0800160#define ASIC_REV_57780 0x57780
Matt Carlsonf6eb9b12009-09-01 13:19:53 +0000161#define ASIC_REV_5717 0x5717
Matt Carlsonb703df62009-12-03 08:36:21 +0000162#define ASIC_REV_57765 0x57785
Linus Torvalds1da177e2005-04-16 15:20:36 -0700163#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
164#define CHIPREV_5700_AX 0x70
165#define CHIPREV_5700_BX 0x71
166#define CHIPREV_5700_CX 0x72
167#define CHIPREV_5701_AX 0x00
168#define CHIPREV_5703_AX 0x10
169#define CHIPREV_5704_AX 0x20
170#define CHIPREV_5704_BX 0x21
171#define CHIPREV_5750_AX 0x40
172#define CHIPREV_5750_BX 0x41
Matt Carlsonb2a5c192008-04-03 21:44:44 -0700173#define CHIPREV_5784_AX 0x57840
174#define CHIPREV_5761_AX 0x57610
Linus Torvalds1da177e2005-04-16 15:20:36 -0700175#define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
176#define METAL_REV_A0 0x00
177#define METAL_REV_A1 0x01
178#define METAL_REV_B0 0x00
179#define METAL_REV_B1 0x01
180#define METAL_REV_B2 0x02
181#define TG3PCI_DMA_RW_CTRL 0x0000006c
Matt Carlsoncbf9ca62009-11-13 13:03:40 +0000182#define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001
Matt Carlson1a319022010-04-12 06:58:25 +0000183#define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380
Linus Torvalds1da177e2005-04-16 15:20:36 -0700184#define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
185#define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
186#define DMA_RWCTRL_READ_BNDRY_16 0x00000100
187#define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100
188#define DMA_RWCTRL_READ_BNDRY_32 0x00000200
189#define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200
190#define DMA_RWCTRL_READ_BNDRY_64 0x00000300
191#define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300
192#define DMA_RWCTRL_READ_BNDRY_128 0x00000400
193#define DMA_RWCTRL_READ_BNDRY_256 0x00000500
194#define DMA_RWCTRL_READ_BNDRY_512 0x00000600
195#define DMA_RWCTRL_READ_BNDRY_1024 0x00000700
196#define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800
197#define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000
198#define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800
199#define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
200#define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000
201#define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
202#define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800
203#define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
204#define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000
205#define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800
206#define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000
207#define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800
208#define DMA_RWCTRL_ONE_DMA 0x00004000
209#define DMA_RWCTRL_READ_WATER 0x00070000
210#define DMA_RWCTRL_READ_WATER_SHIFT 16
211#define DMA_RWCTRL_WRITE_WATER 0x00380000
212#define DMA_RWCTRL_WRITE_WATER_SHIFT 19
213#define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000
214#define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000
215#define DMA_RWCTRL_PCI_READ_CMD 0x0f000000
216#define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24
217#define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000
218#define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28
219#define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000
220#define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
221#define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
222#define TG3PCI_PCISTATE 0x00000070
223#define PCISTATE_FORCE_RESET 0x00000001
224#define PCISTATE_INT_NOT_ACTIVE 0x00000002
225#define PCISTATE_CONV_PCI_MODE 0x00000004
226#define PCISTATE_BUS_SPEED_HIGH 0x00000008
227#define PCISTATE_BUS_32BIT 0x00000010
228#define PCISTATE_ROM_ENABLE 0x00000020
229#define PCISTATE_ROM_RETRY_ENABLE 0x00000040
230#define PCISTATE_FLAT_VIEW 0x00000100
231#define PCISTATE_RETRY_SAME_DMA 0x00002000
Matt Carlson0d3031d2007-10-10 18:02:43 -0700232#define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000
233#define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000
Matt Carlsonf92d9dc12010-06-05 17:24:30 +0000234#define PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235#define TG3PCI_CLOCK_CTRL 0x00000074
236#define CLOCK_CTRL_CORECLK_DISABLE 0x00000200
237#define CLOCK_CTRL_RXCLK_DISABLE 0x00000400
238#define CLOCK_CTRL_TXCLK_DISABLE 0x00000800
239#define CLOCK_CTRL_ALTCLK 0x00001000
240#define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000
241#define CLOCK_CTRL_44MHZ_CORE 0x00040000
242#define CLOCK_CTRL_625_CORE 0x00100000
243#define CLOCK_CTRL_FORCE_CLKRUN 0x00200000
244#define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000
245#define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000
246#define TG3PCI_REG_BASE_ADDR 0x00000078
247#define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c
248#define TG3PCI_REG_DATA 0x00000080
249#define TG3PCI_MEM_WIN_DATA 0x00000084
Linus Torvalds1da177e2005-04-16 15:20:36 -0700250#define TG3PCI_MISC_LOCAL_CTRL 0x00000090
251/* 0x94 --> 0x98 unused */
252#define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
253#define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
Matt Carlsonc6cdf432010-04-05 10:19:26 +0000254/* 0xa8 --> 0xb8 unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700255#define TG3PCI_DUAL_MAC_CTRL 0x000000b8
256#define DUAL_MAC_CTRL_CH_MASK 0x00000003
257#define DUAL_MAC_CTRL_ID 0x00000004
Matt Carlson795d01c2007-10-07 23:28:17 -0700258#define TG3PCI_PRODID_ASICREV 0x000000bc
259#define PROD_ID_ASIC_REV_MASK 0x0fffffff
Matt Carlsonf6eb9b12009-09-01 13:19:53 +0000260/* 0xc0 --> 0xf4 unused */
261
262#define TG3PCI_GEN2_PRODID_ASICREV 0x000000f4
Matt Carlsonb703df62009-12-03 08:36:21 +0000263#define TG3PCI_GEN15_PRODID_ASICREV 0x000000fc
Matt Carlsonf6eb9b12009-09-01 13:19:53 +0000264/* 0xf8 --> 0x200 unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700265
Matt Carlson521e6b92009-08-25 10:06:01 +0000266#define TG3_CORR_ERR_STAT 0x00000110
267#define TG3_CORR_ERR_STAT_CLEAR 0xffffffff
268/* 0x114 --> 0x200 unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269
270/* Mailbox registers */
271#define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
272#define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
273#define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
274#define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
275#define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
276#define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */
277#define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */
278#define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */
279#define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */
280#define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */
281#define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */
282#define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */
283#define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */
284#define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */
Matt Carlson66711e62009-11-13 13:03:49 +0000285#define TG3_RX_STD_PROD_IDX_REG (MAILBOX_RCV_STD_PROD_IDX + \
286 TG3_64BIT_REG_LOW)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700287#define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */
Matt Carlson66711e62009-11-13 13:03:49 +0000288#define TG3_RX_JMB_PROD_IDX_REG (MAILBOX_RCV_JUMBO_PROD_IDX + \
289 TG3_64BIT_REG_LOW)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700290#define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */
291#define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */
292#define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */
293#define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */
294#define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */
295#define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */
296#define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */
297#define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */
298#define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */
299#define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */
300#define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */
301#define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */
302#define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */
303#define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */
304#define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */
305#define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */
306#define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */
307#define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */
308#define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */
309#define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */
310#define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */
311#define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */
312#define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */
313#define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */
314#define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */
315#define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */
316#define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */
317#define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */
318#define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */
319#define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */
320#define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */
321#define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */
322#define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */
323#define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */
324#define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */
325#define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */
326#define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */
327#define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */
328#define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */
329#define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */
330#define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */
331#define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */
332#define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */
333#define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */
334#define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */
335#define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */
336#define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */
337#define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */
338#define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */
339
340/* MAC control registers */
341#define MAC_MODE 0x00000400
342#define MAC_MODE_RESET 0x00000001
343#define MAC_MODE_HALF_DUPLEX 0x00000002
344#define MAC_MODE_PORT_MODE_MASK 0x0000000c
345#define MAC_MODE_PORT_MODE_TBI 0x0000000c
346#define MAC_MODE_PORT_MODE_GMII 0x00000008
347#define MAC_MODE_PORT_MODE_MII 0x00000004
348#define MAC_MODE_PORT_MODE_NONE 0x00000000
349#define MAC_MODE_PORT_INT_LPBACK 0x00000010
350#define MAC_MODE_TAGGED_MAC_CTRL 0x00000080
351#define MAC_MODE_TX_BURSTING 0x00000100
352#define MAC_MODE_MAX_DEFER 0x00000200
353#define MAC_MODE_LINK_POLARITY 0x00000400
354#define MAC_MODE_RXSTAT_ENABLE 0x00000800
355#define MAC_MODE_RXSTAT_CLEAR 0x00001000
356#define MAC_MODE_RXSTAT_FLUSH 0x00002000
357#define MAC_MODE_TXSTAT_ENABLE 0x00004000
358#define MAC_MODE_TXSTAT_CLEAR 0x00008000
359#define MAC_MODE_TXSTAT_FLUSH 0x00010000
360#define MAC_MODE_SEND_CONFIGS 0x00020000
361#define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000
362#define MAC_MODE_ACPI_ENABLE 0x00080000
363#define MAC_MODE_MIP_ENABLE 0x00100000
364#define MAC_MODE_TDE_ENABLE 0x00200000
365#define MAC_MODE_RDE_ENABLE 0x00400000
366#define MAC_MODE_FHDE_ENABLE 0x00800000
Matt Carlsonb2aee152008-11-03 16:51:11 -0800367#define MAC_MODE_KEEP_FRAME_IN_WOL 0x01000000
Matt Carlson3bda1252008-08-15 14:08:22 -0700368#define MAC_MODE_APE_RX_EN 0x08000000
369#define MAC_MODE_APE_TX_EN 0x10000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370#define MAC_STATUS 0x00000404
371#define MAC_STATUS_PCS_SYNCED 0x00000001
372#define MAC_STATUS_SIGNAL_DET 0x00000002
373#define MAC_STATUS_RCVD_CFG 0x00000004
374#define MAC_STATUS_CFG_CHANGED 0x00000008
375#define MAC_STATUS_SYNC_CHANGED 0x00000010
376#define MAC_STATUS_PORT_DEC_ERR 0x00000400
377#define MAC_STATUS_LNKSTATE_CHANGED 0x00001000
378#define MAC_STATUS_MI_COMPLETION 0x00400000
379#define MAC_STATUS_MI_INTERRUPT 0x00800000
380#define MAC_STATUS_AP_ERROR 0x01000000
381#define MAC_STATUS_ODI_ERROR 0x02000000
382#define MAC_STATUS_RXSTAT_OVERRUN 0x04000000
383#define MAC_STATUS_TXSTAT_OVERRUN 0x08000000
384#define MAC_EVENT 0x00000408
385#define MAC_EVENT_PORT_DECODE_ERR 0x00000400
386#define MAC_EVENT_LNKSTATE_CHANGED 0x00001000
387#define MAC_EVENT_MI_COMPLETION 0x00400000
388#define MAC_EVENT_MI_INTERRUPT 0x00800000
389#define MAC_EVENT_AP_ERROR 0x01000000
390#define MAC_EVENT_ODI_ERROR 0x02000000
391#define MAC_EVENT_RXSTAT_OVERRUN 0x04000000
392#define MAC_EVENT_TXSTAT_OVERRUN 0x08000000
393#define MAC_LED_CTRL 0x0000040c
394#define LED_CTRL_LNKLED_OVERRIDE 0x00000001
395#define LED_CTRL_1000MBPS_ON 0x00000002
396#define LED_CTRL_100MBPS_ON 0x00000004
397#define LED_CTRL_10MBPS_ON 0x00000008
398#define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010
399#define LED_CTRL_TRAFFIC_BLINK 0x00000020
400#define LED_CTRL_TRAFFIC_LED 0x00000040
401#define LED_CTRL_1000MBPS_STATUS 0x00000080
402#define LED_CTRL_100MBPS_STATUS 0x00000100
403#define LED_CTRL_10MBPS_STATUS 0x00000200
404#define LED_CTRL_TRAFFIC_STATUS 0x00000400
405#define LED_CTRL_MODE_MAC 0x00000000
406#define LED_CTRL_MODE_PHY_1 0x00000800
407#define LED_CTRL_MODE_PHY_2 0x00001000
408#define LED_CTRL_MODE_SHASTA_MAC 0x00002000
409#define LED_CTRL_MODE_SHARED 0x00004000
410#define LED_CTRL_MODE_COMBO 0x00008000
411#define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
412#define LED_CTRL_BLINK_RATE_SHIFT 19
413#define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000
414#define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000
415#define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */
416#define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */
417#define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */
418#define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */
419#define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */
420#define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */
421#define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */
422#define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */
423#define MAC_ACPI_MBUF_PTR 0x00000430
424#define MAC_ACPI_LEN_OFFSET 0x00000434
425#define ACPI_LENOFF_LEN_MASK 0x0000ffff
426#define ACPI_LENOFF_LEN_SHIFT 0
427#define ACPI_LENOFF_OFF_MASK 0x0fff0000
428#define ACPI_LENOFF_OFF_SHIFT 16
429#define MAC_TX_BACKOFF_SEED 0x00000438
430#define TX_BACKOFF_SEED_MASK 0x000003ff
431#define MAC_RX_MTU_SIZE 0x0000043c
432#define RX_MTU_SIZE_MASK 0x0000ffff
433#define MAC_PCS_TEST 0x00000440
434#define PCS_TEST_PATTERN_MASK 0x000fffff
435#define PCS_TEST_PATTERN_SHIFT 0
436#define PCS_TEST_ENABLE 0x00100000
437#define MAC_TX_AUTO_NEG 0x00000444
438#define TX_AUTO_NEG_MASK 0x0000ffff
439#define TX_AUTO_NEG_SHIFT 0
440#define MAC_RX_AUTO_NEG 0x00000448
441#define RX_AUTO_NEG_MASK 0x0000ffff
442#define RX_AUTO_NEG_SHIFT 0
443#define MAC_MI_COM 0x0000044c
444#define MI_COM_CMD_MASK 0x0c000000
445#define MI_COM_CMD_WRITE 0x04000000
446#define MI_COM_CMD_READ 0x08000000
447#define MI_COM_READ_FAILED 0x10000000
448#define MI_COM_START 0x20000000
449#define MI_COM_BUSY 0x20000000
450#define MI_COM_PHY_ADDR_MASK 0x03e00000
451#define MI_COM_PHY_ADDR_SHIFT 21
452#define MI_COM_REG_ADDR_MASK 0x001f0000
453#define MI_COM_REG_ADDR_SHIFT 16
454#define MI_COM_DATA_MASK 0x0000ffff
455#define MAC_MI_STAT 0x00000450
456#define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001
Matt Carlsonfcb389d2008-11-03 16:55:44 -0800457#define MAC_MI_STAT_10MBPS_MODE 0x00000002
Linus Torvalds1da177e2005-04-16 15:20:36 -0700458#define MAC_MI_MODE 0x00000454
459#define MAC_MI_MODE_CLK_10MHZ 0x00000001
460#define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002
461#define MAC_MI_MODE_AUTO_POLL 0x00000010
Matt Carlson8ef21422008-05-02 16:47:53 -0700462#define MAC_MI_MODE_500KHZ_CONST 0x00008000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700463#define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */
464#define MAC_AUTO_POLL_STATUS 0x00000458
465#define MAC_AUTO_POLL_ERROR 0x00000001
466#define MAC_TX_MODE 0x0000045c
467#define TX_MODE_RESET 0x00000001
468#define TX_MODE_ENABLE 0x00000002
469#define TX_MODE_FLOW_CTRL_ENABLE 0x00000010
470#define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
471#define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
472#define MAC_TX_STATUS 0x00000460
473#define TX_STATUS_XOFFED 0x00000001
474#define TX_STATUS_SENT_XOFF 0x00000002
475#define TX_STATUS_SENT_XON 0x00000004
476#define TX_STATUS_LINK_UP 0x00000008
477#define TX_STATUS_ODI_UNDERRUN 0x00000010
478#define TX_STATUS_ODI_OVERRUN 0x00000020
479#define MAC_TX_LENGTHS 0x00000464
480#define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff
481#define TX_LENGTHS_SLOT_TIME_SHIFT 0
482#define TX_LENGTHS_IPG_MASK 0x00000f00
483#define TX_LENGTHS_IPG_SHIFT 8
484#define TX_LENGTHS_IPG_CRS_MASK 0x00003000
485#define TX_LENGTHS_IPG_CRS_SHIFT 12
486#define MAC_RX_MODE 0x00000468
487#define RX_MODE_RESET 0x00000001
488#define RX_MODE_ENABLE 0x00000002
489#define RX_MODE_FLOW_CTRL_ENABLE 0x00000004
490#define RX_MODE_KEEP_MAC_CTRL 0x00000008
491#define RX_MODE_KEEP_PAUSE 0x00000010
492#define RX_MODE_ACCEPT_OVERSIZED 0x00000020
493#define RX_MODE_ACCEPT_RUNTS 0x00000040
494#define RX_MODE_LEN_CHECK 0x00000080
495#define RX_MODE_PROMISC 0x00000100
496#define RX_MODE_NO_CRC_CHECK 0x00000200
497#define RX_MODE_KEEP_VLAN_TAG 0x00000400
Matt Carlsonbaf8a942009-09-01 13:13:00 +0000498#define RX_MODE_RSS_IPV4_HASH_EN 0x00010000
499#define RX_MODE_RSS_TCP_IPV4_HASH_EN 0x00020000
500#define RX_MODE_RSS_IPV6_HASH_EN 0x00040000
501#define RX_MODE_RSS_TCP_IPV6_HASH_EN 0x00080000
502#define RX_MODE_RSS_ITBL_HASH_BITS_7 0x00700000
503#define RX_MODE_RSS_ENABLE 0x00800000
Michael Chanaf36e6b2006-03-23 01:28:06 -0800504#define RX_MODE_IPV6_CSUM_ENABLE 0x01000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700505#define MAC_RX_STATUS 0x0000046c
506#define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
507#define RX_STATUS_XOFF_RCVD 0x00000002
508#define RX_STATUS_XON_RCVD 0x00000004
509#define MAC_HASH_REG_0 0x00000470
510#define MAC_HASH_REG_1 0x00000474
511#define MAC_HASH_REG_2 0x00000478
512#define MAC_HASH_REG_3 0x0000047c
513#define MAC_RCV_RULE_0 0x00000480
514#define MAC_RCV_VALUE_0 0x00000484
515#define MAC_RCV_RULE_1 0x00000488
516#define MAC_RCV_VALUE_1 0x0000048c
517#define MAC_RCV_RULE_2 0x00000490
518#define MAC_RCV_VALUE_2 0x00000494
519#define MAC_RCV_RULE_3 0x00000498
520#define MAC_RCV_VALUE_3 0x0000049c
521#define MAC_RCV_RULE_4 0x000004a0
522#define MAC_RCV_VALUE_4 0x000004a4
523#define MAC_RCV_RULE_5 0x000004a8
524#define MAC_RCV_VALUE_5 0x000004ac
525#define MAC_RCV_RULE_6 0x000004b0
526#define MAC_RCV_VALUE_6 0x000004b4
527#define MAC_RCV_RULE_7 0x000004b8
528#define MAC_RCV_VALUE_7 0x000004bc
529#define MAC_RCV_RULE_8 0x000004c0
530#define MAC_RCV_VALUE_8 0x000004c4
531#define MAC_RCV_RULE_9 0x000004c8
532#define MAC_RCV_VALUE_9 0x000004cc
533#define MAC_RCV_RULE_10 0x000004d0
534#define MAC_RCV_VALUE_10 0x000004d4
535#define MAC_RCV_RULE_11 0x000004d8
536#define MAC_RCV_VALUE_11 0x000004dc
537#define MAC_RCV_RULE_12 0x000004e0
538#define MAC_RCV_VALUE_12 0x000004e4
539#define MAC_RCV_RULE_13 0x000004e8
540#define MAC_RCV_VALUE_13 0x000004ec
541#define MAC_RCV_RULE_14 0x000004f0
542#define MAC_RCV_VALUE_14 0x000004f4
543#define MAC_RCV_RULE_15 0x000004f8
544#define MAC_RCV_VALUE_15 0x000004fc
545#define RCV_RULE_DISABLE_MASK 0x7fffffff
546#define MAC_RCV_RULE_CFG 0x00000500
547#define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008
548#define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504
549/* 0x508 --> 0x520 unused */
550#define MAC_HASHREGU_0 0x00000520
551#define MAC_HASHREGU_1 0x00000524
552#define MAC_HASHREGU_2 0x00000528
553#define MAC_HASHREGU_3 0x0000052c
554#define MAC_EXTADDR_0_HIGH 0x00000530
555#define MAC_EXTADDR_0_LOW 0x00000534
556#define MAC_EXTADDR_1_HIGH 0x00000538
557#define MAC_EXTADDR_1_LOW 0x0000053c
558#define MAC_EXTADDR_2_HIGH 0x00000540
559#define MAC_EXTADDR_2_LOW 0x00000544
560#define MAC_EXTADDR_3_HIGH 0x00000548
561#define MAC_EXTADDR_3_LOW 0x0000054c
562#define MAC_EXTADDR_4_HIGH 0x00000550
563#define MAC_EXTADDR_4_LOW 0x00000554
564#define MAC_EXTADDR_5_HIGH 0x00000558
565#define MAC_EXTADDR_5_LOW 0x0000055c
566#define MAC_EXTADDR_6_HIGH 0x00000560
567#define MAC_EXTADDR_6_LOW 0x00000564
568#define MAC_EXTADDR_7_HIGH 0x00000568
569#define MAC_EXTADDR_7_LOW 0x0000056c
570#define MAC_EXTADDR_8_HIGH 0x00000570
571#define MAC_EXTADDR_8_LOW 0x00000574
572#define MAC_EXTADDR_9_HIGH 0x00000578
573#define MAC_EXTADDR_9_LOW 0x0000057c
574#define MAC_EXTADDR_10_HIGH 0x00000580
575#define MAC_EXTADDR_10_LOW 0x00000584
576#define MAC_EXTADDR_11_HIGH 0x00000588
577#define MAC_EXTADDR_11_LOW 0x0000058c
578#define MAC_SERDES_CFG 0x00000590
579#define MAC_SERDES_CFG_EDGE_SELECT 0x00001000
580#define MAC_SERDES_STAT 0x00000594
Matt Carlsona9daf362008-05-25 23:49:44 -0700581/* 0x598 --> 0x5a0 unused */
582#define MAC_PHYCFG1 0x000005a0
583#define MAC_PHYCFG1_RGMII_INT 0x00000001
Matt Carlsonbb85fbb2009-08-25 10:09:07 +0000584#define MAC_PHYCFG1_RXCLK_TO_MASK 0x00001ff0
585#define MAC_PHYCFG1_RXCLK_TIMEOUT 0x00001000
586#define MAC_PHYCFG1_TXCLK_TO_MASK 0x01ff0000
587#define MAC_PHYCFG1_TXCLK_TIMEOUT 0x01000000
Matt Carlsona9daf362008-05-25 23:49:44 -0700588#define MAC_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000
589#define MAC_PHYCFG1_RGMII_SND_STAT_EN 0x04000000
590#define MAC_PHYCFG1_TXC_DRV 0x20000000
591#define MAC_PHYCFG2 0x000005a4
592#define MAC_PHYCFG2_INBAND_ENABLE 0x00000001
Matt Carlsonfcb389d2008-11-03 16:55:44 -0800593#define MAC_PHYCFG2_EMODE_MASK_MASK 0x000001c0
594#define MAC_PHYCFG2_EMODE_MASK_AC131 0x000000c0
595#define MAC_PHYCFG2_EMODE_MASK_50610 0x00000100
596#define MAC_PHYCFG2_EMODE_MASK_RT8211 0x00000000
597#define MAC_PHYCFG2_EMODE_MASK_RT8201 0x000001c0
598#define MAC_PHYCFG2_EMODE_COMP_MASK 0x00000e00
599#define MAC_PHYCFG2_EMODE_COMP_AC131 0x00000600
600#define MAC_PHYCFG2_EMODE_COMP_50610 0x00000400
601#define MAC_PHYCFG2_EMODE_COMP_RT8211 0x00000800
602#define MAC_PHYCFG2_EMODE_COMP_RT8201 0x00000000
603#define MAC_PHYCFG2_FMODE_MASK_MASK 0x00007000
604#define MAC_PHYCFG2_FMODE_MASK_AC131 0x00006000
605#define MAC_PHYCFG2_FMODE_MASK_50610 0x00004000
606#define MAC_PHYCFG2_FMODE_MASK_RT8211 0x00000000
607#define MAC_PHYCFG2_FMODE_MASK_RT8201 0x00007000
608#define MAC_PHYCFG2_FMODE_COMP_MASK 0x00038000
609#define MAC_PHYCFG2_FMODE_COMP_AC131 0x00030000
610#define MAC_PHYCFG2_FMODE_COMP_50610 0x00008000
611#define MAC_PHYCFG2_FMODE_COMP_RT8211 0x00038000
612#define MAC_PHYCFG2_FMODE_COMP_RT8201 0x00000000
613#define MAC_PHYCFG2_GMODE_MASK_MASK 0x001c0000
614#define MAC_PHYCFG2_GMODE_MASK_AC131 0x001c0000
615#define MAC_PHYCFG2_GMODE_MASK_50610 0x00100000
616#define MAC_PHYCFG2_GMODE_MASK_RT8211 0x00000000
617#define MAC_PHYCFG2_GMODE_MASK_RT8201 0x001c0000
618#define MAC_PHYCFG2_GMODE_COMP_MASK 0x00e00000
619#define MAC_PHYCFG2_GMODE_COMP_AC131 0x00e00000
620#define MAC_PHYCFG2_GMODE_COMP_50610 0x00000000
621#define MAC_PHYCFG2_GMODE_COMP_RT8211 0x00200000
622#define MAC_PHYCFG2_GMODE_COMP_RT8201 0x00000000
623#define MAC_PHYCFG2_ACT_MASK_MASK 0x03000000
624#define MAC_PHYCFG2_ACT_MASK_AC131 0x03000000
625#define MAC_PHYCFG2_ACT_MASK_50610 0x01000000
626#define MAC_PHYCFG2_ACT_MASK_RT8211 0x03000000
627#define MAC_PHYCFG2_ACT_MASK_RT8201 0x01000000
628#define MAC_PHYCFG2_ACT_COMP_MASK 0x0c000000
629#define MAC_PHYCFG2_ACT_COMP_AC131 0x00000000
630#define MAC_PHYCFG2_ACT_COMP_50610 0x00000000
631#define MAC_PHYCFG2_ACT_COMP_RT8211 0x00000000
632#define MAC_PHYCFG2_ACT_COMP_RT8201 0x08000000
633#define MAC_PHYCFG2_QUAL_MASK_MASK 0x30000000
634#define MAC_PHYCFG2_QUAL_MASK_AC131 0x30000000
635#define MAC_PHYCFG2_QUAL_MASK_50610 0x30000000
636#define MAC_PHYCFG2_QUAL_MASK_RT8211 0x30000000
637#define MAC_PHYCFG2_QUAL_MASK_RT8201 0x30000000
638#define MAC_PHYCFG2_QUAL_COMP_MASK 0xc0000000
639#define MAC_PHYCFG2_QUAL_COMP_AC131 0x00000000
640#define MAC_PHYCFG2_QUAL_COMP_50610 0x00000000
641#define MAC_PHYCFG2_QUAL_COMP_RT8211 0x00000000
642#define MAC_PHYCFG2_QUAL_COMP_RT8201 0x00000000
643#define MAC_PHYCFG2_50610_LED_MODES \
644 (MAC_PHYCFG2_EMODE_MASK_50610 | \
645 MAC_PHYCFG2_EMODE_COMP_50610 | \
646 MAC_PHYCFG2_FMODE_MASK_50610 | \
647 MAC_PHYCFG2_FMODE_COMP_50610 | \
648 MAC_PHYCFG2_GMODE_MASK_50610 | \
649 MAC_PHYCFG2_GMODE_COMP_50610 | \
650 MAC_PHYCFG2_ACT_MASK_50610 | \
651 MAC_PHYCFG2_ACT_COMP_50610 | \
652 MAC_PHYCFG2_QUAL_MASK_50610 | \
653 MAC_PHYCFG2_QUAL_COMP_50610)
654#define MAC_PHYCFG2_AC131_LED_MODES \
655 (MAC_PHYCFG2_EMODE_MASK_AC131 | \
656 MAC_PHYCFG2_EMODE_COMP_AC131 | \
657 MAC_PHYCFG2_FMODE_MASK_AC131 | \
658 MAC_PHYCFG2_FMODE_COMP_AC131 | \
659 MAC_PHYCFG2_GMODE_MASK_AC131 | \
660 MAC_PHYCFG2_GMODE_COMP_AC131 | \
661 MAC_PHYCFG2_ACT_MASK_AC131 | \
662 MAC_PHYCFG2_ACT_COMP_AC131 | \
663 MAC_PHYCFG2_QUAL_MASK_AC131 | \
664 MAC_PHYCFG2_QUAL_COMP_AC131)
665#define MAC_PHYCFG2_RTL8211C_LED_MODES \
666 (MAC_PHYCFG2_EMODE_MASK_RT8211 | \
667 MAC_PHYCFG2_EMODE_COMP_RT8211 | \
668 MAC_PHYCFG2_FMODE_MASK_RT8211 | \
669 MAC_PHYCFG2_FMODE_COMP_RT8211 | \
670 MAC_PHYCFG2_GMODE_MASK_RT8211 | \
671 MAC_PHYCFG2_GMODE_COMP_RT8211 | \
672 MAC_PHYCFG2_ACT_MASK_RT8211 | \
673 MAC_PHYCFG2_ACT_COMP_RT8211 | \
674 MAC_PHYCFG2_QUAL_MASK_RT8211 | \
675 MAC_PHYCFG2_QUAL_COMP_RT8211)
676#define MAC_PHYCFG2_RTL8201E_LED_MODES \
677 (MAC_PHYCFG2_EMODE_MASK_RT8201 | \
678 MAC_PHYCFG2_EMODE_COMP_RT8201 | \
679 MAC_PHYCFG2_FMODE_MASK_RT8201 | \
680 MAC_PHYCFG2_FMODE_COMP_RT8201 | \
681 MAC_PHYCFG2_GMODE_MASK_RT8201 | \
682 MAC_PHYCFG2_GMODE_COMP_RT8201 | \
683 MAC_PHYCFG2_ACT_MASK_RT8201 | \
684 MAC_PHYCFG2_ACT_COMP_RT8201 | \
685 MAC_PHYCFG2_QUAL_MASK_RT8201 | \
686 MAC_PHYCFG2_QUAL_COMP_RT8201)
Matt Carlsona9daf362008-05-25 23:49:44 -0700687#define MAC_EXT_RGMII_MODE 0x000005a8
688#define MAC_RGMII_MODE_TX_ENABLE 0x00000001
689#define MAC_RGMII_MODE_TX_LOWPWR 0x00000002
690#define MAC_RGMII_MODE_TX_RESET 0x00000004
691#define MAC_RGMII_MODE_RX_INT_B 0x00000100
692#define MAC_RGMII_MODE_RX_QUALITY 0x00000200
693#define MAC_RGMII_MODE_RX_ACTIVITY 0x00000400
694#define MAC_RGMII_MODE_RX_ENG_DET 0x00000800
695/* 0x5ac --> 0x5b0 unused */
Michael Chana4e2b342005-10-26 15:46:52 -0700696#define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */
697#define SERDES_RX_SIG_DETECT 0x00000400
Linus Torvalds1da177e2005-04-16 15:20:36 -0700698#define SG_DIG_CTRL 0x000005b0
699#define SG_DIG_USING_HW_AUTONEG 0x80000000
700#define SG_DIG_SOFT_RESET 0x40000000
701#define SG_DIG_DISABLE_LINKRDY 0x20000000
702#define SG_DIG_CRC16_CLEAR_N 0x01000000
703#define SG_DIG_EN10B 0x00800000
704#define SG_DIG_CLEAR_STATUS 0x00400000
705#define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000
706#define SG_DIG_LOCAL_LINK_STATUS 0x00100000
707#define SG_DIG_SPEED_STATUS_MASK 0x000c0000
708#define SG_DIG_SPEED_STATUS_SHIFT 18
709#define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000
710#define SG_DIG_RESTART_AUTONEG 0x00010000
711#define SG_DIG_FIBER_MODE 0x00008000
712#define SG_DIG_REMOTE_FAULT_MASK 0x00006000
713#define SG_DIG_PAUSE_MASK 0x00001800
Matt Carlsonc98f6e32007-12-20 20:08:32 -0800714#define SG_DIG_PAUSE_CAP 0x00000800
715#define SG_DIG_ASYM_PAUSE 0x00001000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700716#define SG_DIG_GBIC_ENABLE 0x00000400
717#define SG_DIG_CHECK_END_ENABLE 0x00000200
718#define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100
719#define SG_DIG_CLOCK_PHASE_SELECT 0x00000080
720#define SG_DIG_GMII_INPUT_SELECT 0x00000040
721#define SG_DIG_MRADV_CRC16_SELECT 0x00000020
722#define SG_DIG_COMMA_DETECT_ENABLE 0x00000010
723#define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008
724#define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004
725#define SG_DIG_REMOTE_LOOPBACK 0x00000002
726#define SG_DIG_LOOPBACK 0x00000001
Matt Carlsonc98f6e32007-12-20 20:08:32 -0800727#define SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \
728 SG_DIG_LOCAL_DUPLEX_STATUS | \
729 SG_DIG_LOCAL_LINK_STATUS | \
730 (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \
731 SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700732#define SG_DIG_STATUS 0x000005b4
733#define SG_DIG_CRC16_BUS_MASK 0xffff0000
734#define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */
735#define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */
736#define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */
737#define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */
738#define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */
739#define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */
740#define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0
Matt Carlson882e9792009-09-01 13:21:36 +0000741#define SG_DIG_IS_SERDES 0x00000100
Linus Torvalds1da177e2005-04-16 15:20:36 -0700742#define SG_DIG_COMMA_DETECTOR 0x00000008
743#define SG_DIG_MAC_ACK_STATUS 0x00000004
744#define SG_DIG_AUTONEG_COMPLETE 0x00000002
745#define SG_DIG_AUTONEG_ERROR 0x00000001
746/* 0x5b8 --> 0x600 unused */
747#define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */
748#define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */
Matt Carlsonbaf8a942009-09-01 13:13:00 +0000749/* 0x624 --> 0x670 unused */
750
751#define MAC_RSS_INDIR_TBL_0 0x00000630
752
753#define MAC_RSS_HASH_KEY_0 0x00000670
754#define MAC_RSS_HASH_KEY_1 0x00000674
755#define MAC_RSS_HASH_KEY_2 0x00000678
756#define MAC_RSS_HASH_KEY_3 0x0000067c
757#define MAC_RSS_HASH_KEY_4 0x00000680
758#define MAC_RSS_HASH_KEY_5 0x00000684
759#define MAC_RSS_HASH_KEY_6 0x00000688
760#define MAC_RSS_HASH_KEY_7 0x0000068c
761#define MAC_RSS_HASH_KEY_8 0x00000690
762#define MAC_RSS_HASH_KEY_9 0x00000694
763/* 0x698 --> 0x800 unused */
764
Linus Torvalds1da177e2005-04-16 15:20:36 -0700765#define MAC_TX_STATS_OCTETS 0x00000800
766#define MAC_TX_STATS_RESV1 0x00000804
767#define MAC_TX_STATS_COLLISIONS 0x00000808
768#define MAC_TX_STATS_XON_SENT 0x0000080c
769#define MAC_TX_STATS_XOFF_SENT 0x00000810
770#define MAC_TX_STATS_RESV2 0x00000814
771#define MAC_TX_STATS_MAC_ERRORS 0x00000818
772#define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c
773#define MAC_TX_STATS_MULT_COLLISIONS 0x00000820
774#define MAC_TX_STATS_DEFERRED 0x00000824
775#define MAC_TX_STATS_RESV3 0x00000828
776#define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c
777#define MAC_TX_STATS_LATE_COL 0x00000830
778#define MAC_TX_STATS_RESV4_1 0x00000834
779#define MAC_TX_STATS_RESV4_2 0x00000838
780#define MAC_TX_STATS_RESV4_3 0x0000083c
781#define MAC_TX_STATS_RESV4_4 0x00000840
782#define MAC_TX_STATS_RESV4_5 0x00000844
783#define MAC_TX_STATS_RESV4_6 0x00000848
784#define MAC_TX_STATS_RESV4_7 0x0000084c
785#define MAC_TX_STATS_RESV4_8 0x00000850
786#define MAC_TX_STATS_RESV4_9 0x00000854
787#define MAC_TX_STATS_RESV4_10 0x00000858
788#define MAC_TX_STATS_RESV4_11 0x0000085c
789#define MAC_TX_STATS_RESV4_12 0x00000860
790#define MAC_TX_STATS_RESV4_13 0x00000864
791#define MAC_TX_STATS_RESV4_14 0x00000868
792#define MAC_TX_STATS_UCAST 0x0000086c
793#define MAC_TX_STATS_MCAST 0x00000870
794#define MAC_TX_STATS_BCAST 0x00000874
795#define MAC_TX_STATS_RESV5_1 0x00000878
796#define MAC_TX_STATS_RESV5_2 0x0000087c
797#define MAC_RX_STATS_OCTETS 0x00000880
798#define MAC_RX_STATS_RESV1 0x00000884
799#define MAC_RX_STATS_FRAGMENTS 0x00000888
800#define MAC_RX_STATS_UCAST 0x0000088c
801#define MAC_RX_STATS_MCAST 0x00000890
802#define MAC_RX_STATS_BCAST 0x00000894
803#define MAC_RX_STATS_FCS_ERRORS 0x00000898
804#define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c
805#define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0
806#define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4
807#define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8
808#define MAC_RX_STATS_XOFF_ENTERED 0x000008ac
809#define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0
810#define MAC_RX_STATS_JABBERS 0x000008b4
811#define MAC_RX_STATS_UNDERSIZE 0x000008b8
812/* 0x8bc --> 0xc00 unused */
813
814/* Send data initiator control registers */
815#define SNDDATAI_MODE 0x00000c00
816#define SNDDATAI_MODE_RESET 0x00000001
817#define SNDDATAI_MODE_ENABLE 0x00000002
818#define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004
819#define SNDDATAI_STATUS 0x00000c04
820#define SNDDATAI_STATUS_STAT_OFLOW 0x00000004
821#define SNDDATAI_STATSCTRL 0x00000c08
822#define SNDDATAI_SCTRL_ENABLE 0x00000001
823#define SNDDATAI_SCTRL_FASTUPD 0x00000002
824#define SNDDATAI_SCTRL_CLEAR 0x00000004
825#define SNDDATAI_SCTRL_FLUSH 0x00000008
826#define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010
827#define SNDDATAI_STATSENAB 0x00000c0c
828#define SNDDATAI_STATSINCMASK 0x00000c10
Michael Chanb5d37722006-09-27 16:06:21 -0700829#define ISO_PKT_TX 0x00000c20
830/* 0xc24 --> 0xc80 unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700831#define SNDDATAI_COS_CNT_0 0x00000c80
832#define SNDDATAI_COS_CNT_1 0x00000c84
833#define SNDDATAI_COS_CNT_2 0x00000c88
834#define SNDDATAI_COS_CNT_3 0x00000c8c
835#define SNDDATAI_COS_CNT_4 0x00000c90
836#define SNDDATAI_COS_CNT_5 0x00000c94
837#define SNDDATAI_COS_CNT_6 0x00000c98
838#define SNDDATAI_COS_CNT_7 0x00000c9c
839#define SNDDATAI_COS_CNT_8 0x00000ca0
840#define SNDDATAI_COS_CNT_9 0x00000ca4
841#define SNDDATAI_COS_CNT_10 0x00000ca8
842#define SNDDATAI_COS_CNT_11 0x00000cac
843#define SNDDATAI_COS_CNT_12 0x00000cb0
844#define SNDDATAI_COS_CNT_13 0x00000cb4
845#define SNDDATAI_COS_CNT_14 0x00000cb8
846#define SNDDATAI_COS_CNT_15 0x00000cbc
847#define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0
848#define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4
849#define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8
850#define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc
851#define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0
852#define SNDDATAI_INTERRUPTS_CNT 0x00000cd4
853#define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8
854#define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc
855/* 0xce0 --> 0x1000 unused */
856
857/* Send data completion control registers */
858#define SNDDATAC_MODE 0x00001000
859#define SNDDATAC_MODE_RESET 0x00000001
860#define SNDDATAC_MODE_ENABLE 0x00000002
Matt Carlson9936bcf2007-10-10 18:03:07 -0700861#define SNDDATAC_MODE_CDELAY 0x00000010
Linus Torvalds1da177e2005-04-16 15:20:36 -0700862/* 0x1004 --> 0x1400 unused */
863
864/* Send BD ring selector */
865#define SNDBDS_MODE 0x00001400
866#define SNDBDS_MODE_RESET 0x00000001
867#define SNDBDS_MODE_ENABLE 0x00000002
868#define SNDBDS_MODE_ATTN_ENABLE 0x00000004
869#define SNDBDS_STATUS 0x00001404
870#define SNDBDS_STATUS_ERROR_ATTN 0x00000004
871#define SNDBDS_HWDIAG 0x00001408
872/* 0x140c --> 0x1440 */
873#define SNDBDS_SEL_CON_IDX_0 0x00001440
874#define SNDBDS_SEL_CON_IDX_1 0x00001444
875#define SNDBDS_SEL_CON_IDX_2 0x00001448
876#define SNDBDS_SEL_CON_IDX_3 0x0000144c
877#define SNDBDS_SEL_CON_IDX_4 0x00001450
878#define SNDBDS_SEL_CON_IDX_5 0x00001454
879#define SNDBDS_SEL_CON_IDX_6 0x00001458
880#define SNDBDS_SEL_CON_IDX_7 0x0000145c
881#define SNDBDS_SEL_CON_IDX_8 0x00001460
882#define SNDBDS_SEL_CON_IDX_9 0x00001464
883#define SNDBDS_SEL_CON_IDX_10 0x00001468
884#define SNDBDS_SEL_CON_IDX_11 0x0000146c
885#define SNDBDS_SEL_CON_IDX_12 0x00001470
886#define SNDBDS_SEL_CON_IDX_13 0x00001474
887#define SNDBDS_SEL_CON_IDX_14 0x00001478
888#define SNDBDS_SEL_CON_IDX_15 0x0000147c
889/* 0x1480 --> 0x1800 unused */
890
891/* Send BD initiator control registers */
892#define SNDBDI_MODE 0x00001800
893#define SNDBDI_MODE_RESET 0x00000001
894#define SNDBDI_MODE_ENABLE 0x00000002
895#define SNDBDI_MODE_ATTN_ENABLE 0x00000004
Matt Carlsonfe5f5782009-09-01 13:09:39 +0000896#define SNDBDI_MODE_MULTI_TXQ_EN 0x00000020
Linus Torvalds1da177e2005-04-16 15:20:36 -0700897#define SNDBDI_STATUS 0x00001804
898#define SNDBDI_STATUS_ERROR_ATTN 0x00000004
899#define SNDBDI_IN_PROD_IDX_0 0x00001808
900#define SNDBDI_IN_PROD_IDX_1 0x0000180c
901#define SNDBDI_IN_PROD_IDX_2 0x00001810
902#define SNDBDI_IN_PROD_IDX_3 0x00001814
903#define SNDBDI_IN_PROD_IDX_4 0x00001818
904#define SNDBDI_IN_PROD_IDX_5 0x0000181c
905#define SNDBDI_IN_PROD_IDX_6 0x00001820
906#define SNDBDI_IN_PROD_IDX_7 0x00001824
907#define SNDBDI_IN_PROD_IDX_8 0x00001828
908#define SNDBDI_IN_PROD_IDX_9 0x0000182c
909#define SNDBDI_IN_PROD_IDX_10 0x00001830
910#define SNDBDI_IN_PROD_IDX_11 0x00001834
911#define SNDBDI_IN_PROD_IDX_12 0x00001838
912#define SNDBDI_IN_PROD_IDX_13 0x0000183c
913#define SNDBDI_IN_PROD_IDX_14 0x00001840
914#define SNDBDI_IN_PROD_IDX_15 0x00001844
915/* 0x1848 --> 0x1c00 unused */
916
917/* Send BD completion control registers */
918#define SNDBDC_MODE 0x00001c00
919#define SNDBDC_MODE_RESET 0x00000001
920#define SNDBDC_MODE_ENABLE 0x00000002
921#define SNDBDC_MODE_ATTN_ENABLE 0x00000004
922/* 0x1c04 --> 0x2000 unused */
923
924/* Receive list placement control registers */
925#define RCVLPC_MODE 0x00002000
926#define RCVLPC_MODE_RESET 0x00000001
927#define RCVLPC_MODE_ENABLE 0x00000002
928#define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004
929#define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008
930#define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010
931#define RCVLPC_STATUS 0x00002004
932#define RCVLPC_STATUS_CLASS0 0x00000004
933#define RCVLPC_STATUS_MAPOOR 0x00000008
934#define RCVLPC_STATUS_STAT_OFLOW 0x00000010
935#define RCVLPC_LOCK 0x00002008
936#define RCVLPC_LOCK_REQ_MASK 0x0000ffff
937#define RCVLPC_LOCK_REQ_SHIFT 0
938#define RCVLPC_LOCK_GRANT_MASK 0xffff0000
939#define RCVLPC_LOCK_GRANT_SHIFT 16
940#define RCVLPC_NON_EMPTY_BITS 0x0000200c
941#define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff
942#define RCVLPC_CONFIG 0x00002010
943#define RCVLPC_STATSCTRL 0x00002014
944#define RCVLPC_STATSCTRL_ENABLE 0x00000001
945#define RCVLPC_STATSCTRL_FASTUPD 0x00000002
946#define RCVLPC_STATS_ENABLE 0x00002018
Matt Carlson255ca312009-08-25 10:07:27 +0000947#define RCVLPC_STATSENAB_ASF_FIX 0x00000002
Michael Chan16613942006-06-29 20:15:13 -0700948#define RCVLPC_STATSENAB_DACK_FIX 0x00040000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700949#define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
950#define RCVLPC_STATS_INCMASK 0x0000201c
951/* 0x2020 --> 0x2100 unused */
952#define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */
953#define SELLST_TAIL 0x00000004
954#define SELLST_CONT 0x00000008
955#define SELLST_UNUSED 0x0000000c
956#define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */
957#define RCVLPC_DROP_FILTER_CNT 0x00002240
958#define RCVLPC_DMA_WQ_FULL_CNT 0x00002244
959#define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248
960#define RCVLPC_NO_RCV_BD_CNT 0x0000224c
961#define RCVLPC_IN_DISCARDS_CNT 0x00002250
962#define RCVLPC_IN_ERRORS_CNT 0x00002254
963#define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258
964/* 0x225c --> 0x2400 unused */
965
966/* Receive Data and Receive BD Initiator Control */
967#define RCVDBDI_MODE 0x00002400
968#define RCVDBDI_MODE_RESET 0x00000001
969#define RCVDBDI_MODE_ENABLE 0x00000002
970#define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004
971#define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008
972#define RCVDBDI_MODE_INV_RING_SZ 0x00000010
973#define RCVDBDI_STATUS 0x00002404
974#define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004
975#define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008
976#define RCVDBDI_STATUS_INV_RING_SZ 0x00000010
977#define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408
978/* 0x240c --> 0x2440 unused */
979#define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */
980#define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */
981#define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */
982#define RCVDBDI_JUMBO_CON_IDX 0x00002470
983#define RCVDBDI_STD_CON_IDX 0x00002474
984#define RCVDBDI_MINI_CON_IDX 0x00002478
985/* 0x247c --> 0x2480 unused */
986#define RCVDBDI_BD_PROD_IDX_0 0x00002480
987#define RCVDBDI_BD_PROD_IDX_1 0x00002484
988#define RCVDBDI_BD_PROD_IDX_2 0x00002488
989#define RCVDBDI_BD_PROD_IDX_3 0x0000248c
990#define RCVDBDI_BD_PROD_IDX_4 0x00002490
991#define RCVDBDI_BD_PROD_IDX_5 0x00002494
992#define RCVDBDI_BD_PROD_IDX_6 0x00002498
993#define RCVDBDI_BD_PROD_IDX_7 0x0000249c
994#define RCVDBDI_BD_PROD_IDX_8 0x000024a0
995#define RCVDBDI_BD_PROD_IDX_9 0x000024a4
996#define RCVDBDI_BD_PROD_IDX_10 0x000024a8
997#define RCVDBDI_BD_PROD_IDX_11 0x000024ac
998#define RCVDBDI_BD_PROD_IDX_12 0x000024b0
999#define RCVDBDI_BD_PROD_IDX_13 0x000024b4
1000#define RCVDBDI_BD_PROD_IDX_14 0x000024b8
1001#define RCVDBDI_BD_PROD_IDX_15 0x000024bc
1002#define RCVDBDI_HWDIAG 0x000024c0
1003/* 0x24c4 --> 0x2800 unused */
1004
1005/* Receive Data Completion Control */
1006#define RCVDCC_MODE 0x00002800
1007#define RCVDCC_MODE_RESET 0x00000001
1008#define RCVDCC_MODE_ENABLE 0x00000002
1009#define RCVDCC_MODE_ATTN_ENABLE 0x00000004
1010/* 0x2804 --> 0x2c00 unused */
1011
1012/* Receive BD Initiator Control Registers */
1013#define RCVBDI_MODE 0x00002c00
1014#define RCVBDI_MODE_RESET 0x00000001
1015#define RCVBDI_MODE_ENABLE 0x00000002
1016#define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004
1017#define RCVBDI_STATUS 0x00002c04
1018#define RCVBDI_STATUS_RCB_ATTN 0x00000004
1019#define RCVBDI_JUMBO_PROD_IDX 0x00002c08
1020#define RCVBDI_STD_PROD_IDX 0x00002c0c
1021#define RCVBDI_MINI_PROD_IDX 0x00002c10
1022#define RCVBDI_MINI_THRESH 0x00002c14
1023#define RCVBDI_STD_THRESH 0x00002c18
1024#define RCVBDI_JUMBO_THRESH 0x00002c1c
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00001025/* 0x2c20 --> 0x2d00 unused */
1026
1027#define STD_REPLENISH_LWM 0x00002d00
1028#define JMB_REPLENISH_LWM 0x00002d04
1029/* 0x2d08 --> 0x3000 unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001030
1031/* Receive BD Completion Control Registers */
1032#define RCVCC_MODE 0x00003000
1033#define RCVCC_MODE_RESET 0x00000001
1034#define RCVCC_MODE_ENABLE 0x00000002
1035#define RCVCC_MODE_ATTN_ENABLE 0x00000004
1036#define RCVCC_STATUS 0x00003004
1037#define RCVCC_STATUS_ERROR_ATTN 0x00000004
1038#define RCVCC_JUMP_PROD_IDX 0x00003008
1039#define RCVCC_STD_PROD_IDX 0x0000300c
1040#define RCVCC_MINI_PROD_IDX 0x00003010
1041/* 0x3014 --> 0x3400 unused */
1042
1043/* Receive list selector control registers */
1044#define RCVLSC_MODE 0x00003400
1045#define RCVLSC_MODE_RESET 0x00000001
1046#define RCVLSC_MODE_ENABLE 0x00000002
1047#define RCVLSC_MODE_ATTN_ENABLE 0x00000004
1048#define RCVLSC_STATUS 0x00003404
1049#define RCVLSC_STATUS_ERROR_ATTN 0x00000004
Matt Carlsond30cdd22007-10-07 23:28:35 -07001050/* 0x3408 --> 0x3600 unused */
1051
1052/* CPMU registers */
1053#define TG3_CPMU_CTRL 0x00003600
1054#define CPMU_CTRL_LINK_IDLE_MODE 0x00000200
1055#define CPMU_CTRL_LINK_AWARE_MODE 0x00000400
Matt Carlson9936bcf2007-10-10 18:03:07 -07001056#define CPMU_CTRL_LINK_SPEED_MODE 0x00004000
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001057#define CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000
Matt Carlson9acb9612007-11-12 21:10:06 -08001058#define TG3_CPMU_LSPD_10MB_CLK 0x00003604
1059#define CPMU_LSPD_10MB_MACCLK_MASK 0x001f0000
1060#define CPMU_LSPD_10MB_MACCLK_6_25 0x00130000
1061/* 0x3608 --> 0x360c unused */
Matt Carlsonce057f02007-11-12 21:08:03 -08001062
1063#define TG3_CPMU_LSPD_1000MB_CLK 0x0000360c
1064#define CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000
1065#define CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000
1066#define CPMU_LSPD_1000MB_MACCLK_MASK 0x001f0000
Matt Carlson9acb9612007-11-12 21:10:06 -08001067#define TG3_CPMU_LNK_AWARE_PWRMD 0x00003610
1068#define CPMU_LNK_AWARE_MACCLK_MASK 0x001f0000
1069#define CPMU_LNK_AWARE_MACCLK_6_25 0x00130000
1070/* 0x3614 --> 0x361c unused */
1071
1072#define TG3_CPMU_HST_ACC 0x0000361c
1073#define CPMU_HST_ACC_MACCLK_MASK 0x001f0000
1074#define CPMU_HST_ACC_MACCLK_6_25 0x00130000
Matt Carlsona1b950d2009-09-01 13:20:17 +00001075/* 0x3620 --> 0x362c unused */
Matt Carlsonaa6c91f2007-11-12 21:18:04 -08001076
Matt Carlsona1b950d2009-09-01 13:20:17 +00001077#define TG3_CPMU_STATUS 0x0000362c
1078#define TG3_CPMU_STATUS_PCIE_FUNC 0x20000000
Matt Carlsonaa6c91f2007-11-12 21:18:04 -08001079#define TG3_CPMU_CLCK_STAT 0x00003630
1080#define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000
1081#define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000
1082#define CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000
1083#define CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000
1084/* 0x3634 --> 0x365c unused */
Matt Carlson9936bcf2007-10-10 18:03:07 -07001085
1086#define TG3_CPMU_MUTEX_REQ 0x0000365c
1087#define CPMU_MUTEX_REQ_DRIVER 0x00001000
1088#define TG3_CPMU_MUTEX_GNT 0x00003660
1089#define CPMU_MUTEX_GNT_DRIVER 0x00001000
Matt Carlsond1ec96a2010-01-12 10:11:38 +00001090#define TG3_CPMU_PHY_STRAP 0x00003664
1091#define TG3_CPMU_PHY_STRAP_IS_SERDES 0x00000020
Matt Carlson9936bcf2007-10-10 18:03:07 -07001092/* 0x3664 --> 0x3800 unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001093
1094/* Mbuf cluster free registers */
1095#define MBFREE_MODE 0x00003800
1096#define MBFREE_MODE_RESET 0x00000001
1097#define MBFREE_MODE_ENABLE 0x00000002
1098#define MBFREE_STATUS 0x00003804
1099/* 0x3808 --> 0x3c00 unused */
1100
1101/* Host coalescing control registers */
1102#define HOSTCC_MODE 0x00003c00
1103#define HOSTCC_MODE_RESET 0x00000001
1104#define HOSTCC_MODE_ENABLE 0x00000002
1105#define HOSTCC_MODE_ATTN 0x00000004
1106#define HOSTCC_MODE_NOW 0x00000008
1107#define HOSTCC_MODE_FULL_STATUS 0x00000000
1108#define HOSTCC_MODE_64BYTE 0x00000080
1109#define HOSTCC_MODE_32BYTE 0x00000100
1110#define HOSTCC_MODE_CLRTICK_RXBD 0x00000200
1111#define HOSTCC_MODE_CLRTICK_TXBD 0x00000400
1112#define HOSTCC_MODE_NOINT_ON_NOW 0x00000800
1113#define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000
Matt Carlsonfd2ce372009-09-01 12:51:13 +00001114#define HOSTCC_MODE_COAL_VEC1_NOW 0x00002000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001115#define HOSTCC_STATUS 0x00003c04
1116#define HOSTCC_STATUS_ERROR_ATTN 0x00000004
1117#define HOSTCC_RXCOL_TICKS 0x00003c08
1118#define LOW_RXCOL_TICKS 0x00000032
David S. Miller15f98502005-05-18 22:49:26 -07001119#define LOW_RXCOL_TICKS_CLRTCKS 0x00000014
Linus Torvalds1da177e2005-04-16 15:20:36 -07001120#define DEFAULT_RXCOL_TICKS 0x00000048
1121#define HIGH_RXCOL_TICKS 0x00000096
Michael Chand244c892005-07-05 14:42:33 -07001122#define MAX_RXCOL_TICKS 0x000003ff
Linus Torvalds1da177e2005-04-16 15:20:36 -07001123#define HOSTCC_TXCOL_TICKS 0x00003c0c
1124#define LOW_TXCOL_TICKS 0x00000096
David S. Miller15f98502005-05-18 22:49:26 -07001125#define LOW_TXCOL_TICKS_CLRTCKS 0x00000048
Linus Torvalds1da177e2005-04-16 15:20:36 -07001126#define DEFAULT_TXCOL_TICKS 0x0000012c
1127#define HIGH_TXCOL_TICKS 0x00000145
Michael Chand244c892005-07-05 14:42:33 -07001128#define MAX_TXCOL_TICKS 0x000003ff
Linus Torvalds1da177e2005-04-16 15:20:36 -07001129#define HOSTCC_RXMAX_FRAMES 0x00003c10
1130#define LOW_RXMAX_FRAMES 0x00000005
1131#define DEFAULT_RXMAX_FRAMES 0x00000008
1132#define HIGH_RXMAX_FRAMES 0x00000012
Michael Chand244c892005-07-05 14:42:33 -07001133#define MAX_RXMAX_FRAMES 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -07001134#define HOSTCC_TXMAX_FRAMES 0x00003c14
1135#define LOW_TXMAX_FRAMES 0x00000035
1136#define DEFAULT_TXMAX_FRAMES 0x0000004b
1137#define HIGH_TXMAX_FRAMES 0x00000052
Michael Chand244c892005-07-05 14:42:33 -07001138#define MAX_TXMAX_FRAMES 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -07001139#define HOSTCC_RXCOAL_TICK_INT 0x00003c18
1140#define DEFAULT_RXCOAL_TICK_INT 0x00000019
David S. Miller15f98502005-05-18 22:49:26 -07001141#define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
Michael Chand244c892005-07-05 14:42:33 -07001142#define MAX_RXCOAL_TICK_INT 0x000003ff
Linus Torvalds1da177e2005-04-16 15:20:36 -07001143#define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
1144#define DEFAULT_TXCOAL_TICK_INT 0x00000019
David S. Miller15f98502005-05-18 22:49:26 -07001145#define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
Michael Chand244c892005-07-05 14:42:33 -07001146#define MAX_TXCOAL_TICK_INT 0x000003ff
Linus Torvalds1da177e2005-04-16 15:20:36 -07001147#define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
1148#define DEFAULT_RXCOAL_MAXF_INT 0x00000005
Michael Chand244c892005-07-05 14:42:33 -07001149#define MAX_RXCOAL_MAXF_INT 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -07001150#define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
1151#define DEFAULT_TXCOAL_MAXF_INT 0x00000005
Michael Chand244c892005-07-05 14:42:33 -07001152#define MAX_TXCOAL_MAXF_INT 0x000000ff
Linus Torvalds1da177e2005-04-16 15:20:36 -07001153#define HOSTCC_STAT_COAL_TICKS 0x00003c28
1154#define DEFAULT_STAT_COAL_TICKS 0x000f4240
Michael Chand244c892005-07-05 14:42:33 -07001155#define MAX_STAT_COAL_TICKS 0xd693d400
1156#define MIN_STAT_COAL_TICKS 0x00000064
Linus Torvalds1da177e2005-04-16 15:20:36 -07001157/* 0x3c2c --> 0x3c30 unused */
1158#define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */
1159#define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */
1160#define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40
1161#define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44
1162#define HOSTCC_FLOW_ATTN 0x00003c48
1163/* 0x3c4c --> 0x3c50 unused */
1164#define HOSTCC_JUMBO_CON_IDX 0x00003c50
1165#define HOSTCC_STD_CON_IDX 0x00003c54
1166#define HOSTCC_MINI_CON_IDX 0x00003c58
1167/* 0x3c5c --> 0x3c80 unused */
1168#define HOSTCC_RET_PROD_IDX_0 0x00003c80
1169#define HOSTCC_RET_PROD_IDX_1 0x00003c84
1170#define HOSTCC_RET_PROD_IDX_2 0x00003c88
1171#define HOSTCC_RET_PROD_IDX_3 0x00003c8c
1172#define HOSTCC_RET_PROD_IDX_4 0x00003c90
1173#define HOSTCC_RET_PROD_IDX_5 0x00003c94
1174#define HOSTCC_RET_PROD_IDX_6 0x00003c98
1175#define HOSTCC_RET_PROD_IDX_7 0x00003c9c
1176#define HOSTCC_RET_PROD_IDX_8 0x00003ca0
1177#define HOSTCC_RET_PROD_IDX_9 0x00003ca4
1178#define HOSTCC_RET_PROD_IDX_10 0x00003ca8
1179#define HOSTCC_RET_PROD_IDX_11 0x00003cac
1180#define HOSTCC_RET_PROD_IDX_12 0x00003cb0
1181#define HOSTCC_RET_PROD_IDX_13 0x00003cb4
1182#define HOSTCC_RET_PROD_IDX_14 0x00003cb8
1183#define HOSTCC_RET_PROD_IDX_15 0x00003cbc
1184#define HOSTCC_SND_CON_IDX_0 0x00003cc0
1185#define HOSTCC_SND_CON_IDX_1 0x00003cc4
1186#define HOSTCC_SND_CON_IDX_2 0x00003cc8
1187#define HOSTCC_SND_CON_IDX_3 0x00003ccc
1188#define HOSTCC_SND_CON_IDX_4 0x00003cd0
1189#define HOSTCC_SND_CON_IDX_5 0x00003cd4
1190#define HOSTCC_SND_CON_IDX_6 0x00003cd8
1191#define HOSTCC_SND_CON_IDX_7 0x00003cdc
1192#define HOSTCC_SND_CON_IDX_8 0x00003ce0
1193#define HOSTCC_SND_CON_IDX_9 0x00003ce4
1194#define HOSTCC_SND_CON_IDX_10 0x00003ce8
1195#define HOSTCC_SND_CON_IDX_11 0x00003cec
1196#define HOSTCC_SND_CON_IDX_12 0x00003cf0
1197#define HOSTCC_SND_CON_IDX_13 0x00003cf4
1198#define HOSTCC_SND_CON_IDX_14 0x00003cf8
1199#define HOSTCC_SND_CON_IDX_15 0x00003cfc
Matt Carlsonf77a6a82009-09-01 13:04:37 +00001200#define HOSTCC_STATBLCK_RING1 0x00003d00
Matt Carlsonb6080e12009-09-01 13:12:00 +00001201/* 0x3d00 --> 0x3d80 unused */
1202
1203#define HOSTCC_RXCOL_TICKS_VEC1 0x00003d80
1204#define HOSTCC_TXCOL_TICKS_VEC1 0x00003d84
1205#define HOSTCC_RXMAX_FRAMES_VEC1 0x00003d88
1206#define HOSTCC_TXMAX_FRAMES_VEC1 0x00003d8c
1207#define HOSTCC_RXCOAL_MAXF_INT_VEC1 0x00003d90
1208#define HOSTCC_TXCOAL_MAXF_INT_VEC1 0x00003d94
1209/* 0x3d98 --> 0x4000 unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001210
1211/* Memory arbiter control registers */
1212#define MEMARB_MODE 0x00004000
1213#define MEMARB_MODE_RESET 0x00000001
1214#define MEMARB_MODE_ENABLE 0x00000002
1215#define MEMARB_STATUS 0x00004004
1216#define MEMARB_TRAP_ADDR_LOW 0x00004008
1217#define MEMARB_TRAP_ADDR_HIGH 0x0000400c
1218/* 0x4010 --> 0x4400 unused */
1219
1220/* Buffer manager control registers */
1221#define BUFMGR_MODE 0x00004400
1222#define BUFMGR_MODE_RESET 0x00000001
1223#define BUFMGR_MODE_ENABLE 0x00000002
1224#define BUFMGR_MODE_ATTN_ENABLE 0x00000004
1225#define BUFMGR_MODE_BM_TEST 0x00000008
1226#define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010
1227#define BUFMGR_STATUS 0x00004404
1228#define BUFMGR_STATUS_ERROR 0x00000004
1229#define BUFMGR_STATUS_MBLOW 0x00000010
1230#define BUFMGR_MB_POOL_ADDR 0x00004408
1231#define BUFMGR_MB_POOL_SIZE 0x0000440c
1232#define BUFMGR_MB_RDMA_LOW_WATER 0x00004410
1233#define DEFAULT_MB_RDMA_LOW_WATER 0x00000050
1234#define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000
1235#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
Michael Chanfdfec1722005-07-25 12:31:48 -07001236#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001237#define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
1238#define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
1239#define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010
Michael Chanb5d37722006-09-27 16:06:21 -07001240#define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004
Matt Carlson666bc832010-01-20 16:58:03 +00001241#define DEFAULT_MB_MACRX_LOW_WATER_57765 0x0000002a
Linus Torvalds1da177e2005-04-16 15:20:36 -07001242#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
Michael Chanfdfec1722005-07-25 12:31:48 -07001243#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
Matt Carlson666bc832010-01-20 16:58:03 +00001244#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765 0x0000007e
Linus Torvalds1da177e2005-04-16 15:20:36 -07001245#define BUFMGR_MB_HIGH_WATER 0x00004418
1246#define DEFAULT_MB_HIGH_WATER 0x00000060
1247#define DEFAULT_MB_HIGH_WATER_5705 0x00000060
Michael Chanb5d37722006-09-27 16:06:21 -07001248#define DEFAULT_MB_HIGH_WATER_5906 0x00000010
Matt Carlson666bc832010-01-20 16:58:03 +00001249#define DEFAULT_MB_HIGH_WATER_57765 0x000000a0
Linus Torvalds1da177e2005-04-16 15:20:36 -07001250#define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
Michael Chanfdfec1722005-07-25 12:31:48 -07001251#define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
Matt Carlson666bc832010-01-20 16:58:03 +00001252#define DEFAULT_MB_HIGH_WATER_JUMBO_57765 0x000000ea
Linus Torvalds1da177e2005-04-16 15:20:36 -07001253#define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
1254#define BUFMGR_MB_ALLOC_BIT 0x10000000
1255#define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
1256#define BUFMGR_TX_MB_ALLOC_REQ 0x00004424
1257#define BUFMGR_TX_MB_ALLOC_RESP 0x00004428
1258#define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c
1259#define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430
1260#define BUFMGR_DMA_LOW_WATER 0x00004434
1261#define DEFAULT_DMA_LOW_WATER 0x00000005
1262#define BUFMGR_DMA_HIGH_WATER 0x00004438
1263#define DEFAULT_DMA_HIGH_WATER 0x0000000a
1264#define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c
1265#define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440
1266#define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444
1267#define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448
1268#define BUFMGR_HWDIAG_0 0x0000444c
1269#define BUFMGR_HWDIAG_1 0x00004450
1270#define BUFMGR_HWDIAG_2 0x00004454
1271/* 0x4458 --> 0x4800 unused */
1272
1273/* Read DMA control registers */
1274#define RDMAC_MODE 0x00004800
1275#define RDMAC_MODE_RESET 0x00000001
1276#define RDMAC_MODE_ENABLE 0x00000002
1277#define RDMAC_MODE_TGTABORT_ENAB 0x00000004
1278#define RDMAC_MODE_MSTABORT_ENAB 0x00000008
1279#define RDMAC_MODE_PARITYERR_ENAB 0x00000010
1280#define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1281#define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1282#define RDMAC_MODE_FIFOURUN_ENAB 0x00000080
1283#define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1284#define RDMAC_MODE_LNGREAD_ENAB 0x00000200
1285#define RDMAC_MODE_SPLIT_ENABLE 0x00000800
Matt Carlsond30cdd22007-10-07 23:28:35 -07001286#define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800
Linus Torvalds1da177e2005-04-16 15:20:36 -07001287#define RDMAC_MODE_SPLIT_RESET 0x00001000
Matt Carlsond30cdd22007-10-07 23:28:35 -07001288#define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000
1289#define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001290#define RDMAC_MODE_FIFO_SIZE_128 0x00020000
1291#define RDMAC_MODE_FIFO_LONG_BURST 0x00030000
Matt Carlson0339e4e2010-02-12 14:47:09 +00001292#define RDMAC_MODE_MULT_DMA_RD_DIS 0x01000000
Matt Carlson027455a2008-12-21 20:19:30 -08001293#define RDMAC_MODE_IPV4_LSO_EN 0x08000000
1294#define RDMAC_MODE_IPV6_LSO_EN 0x10000000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001295#define RDMAC_STATUS 0x00004804
1296#define RDMAC_STATUS_TGTABORT 0x00000004
1297#define RDMAC_STATUS_MSTABORT 0x00000008
1298#define RDMAC_STATUS_PARITYERR 0x00000010
1299#define RDMAC_STATUS_ADDROFLOW 0x00000020
1300#define RDMAC_STATUS_FIFOOFLOW 0x00000040
1301#define RDMAC_STATUS_FIFOURUN 0x00000080
1302#define RDMAC_STATUS_FIFOOREAD 0x00000100
1303#define RDMAC_STATUS_LNGREAD 0x00000200
1304/* 0x4808 --> 0x4c00 unused */
1305
1306/* Write DMA control registers */
1307#define WDMAC_MODE 0x00004c00
1308#define WDMAC_MODE_RESET 0x00000001
1309#define WDMAC_MODE_ENABLE 0x00000002
1310#define WDMAC_MODE_TGTABORT_ENAB 0x00000004
1311#define WDMAC_MODE_MSTABORT_ENAB 0x00000008
1312#define WDMAC_MODE_PARITYERR_ENAB 0x00000010
1313#define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1314#define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1315#define WDMAC_MODE_FIFOURUN_ENAB 0x00000080
1316#define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1317#define WDMAC_MODE_LNGREAD_ENAB 0x00000200
Matt Carlson788a0352009-11-02 14:26:03 +00001318#define WDMAC_MODE_RX_ACCEL 0x00000400
Matt Carlsonf51f3562008-05-25 23:45:08 -07001319#define WDMAC_MODE_STATUS_TAG_FIX 0x20000000
Matt Carlson788a0352009-11-02 14:26:03 +00001320#define WDMAC_MODE_BURST_ALL_DATA 0xc0000000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001321#define WDMAC_STATUS 0x00004c04
1322#define WDMAC_STATUS_TGTABORT 0x00000004
1323#define WDMAC_STATUS_MSTABORT 0x00000008
1324#define WDMAC_STATUS_PARITYERR 0x00000010
1325#define WDMAC_STATUS_ADDROFLOW 0x00000020
1326#define WDMAC_STATUS_FIFOOFLOW 0x00000040
1327#define WDMAC_STATUS_FIFOURUN 0x00000080
1328#define WDMAC_STATUS_FIFOOREAD 0x00000100
1329#define WDMAC_STATUS_LNGREAD 0x00000200
1330/* 0x4c08 --> 0x5000 unused */
1331
1332/* Per-cpu register offsets (arm9) */
1333#define CPU_MODE 0x00000000
1334#define CPU_MODE_RESET 0x00000001
1335#define CPU_MODE_HALT 0x00000400
1336#define CPU_STATE 0x00000004
1337#define CPU_EVTMASK 0x00000008
1338/* 0xc --> 0x1c reserved */
1339#define CPU_PC 0x0000001c
1340#define CPU_INSN 0x00000020
1341#define CPU_SPAD_UFLOW 0x00000024
1342#define CPU_WDOG_CLEAR 0x00000028
1343#define CPU_WDOG_VECTOR 0x0000002c
1344#define CPU_WDOG_PC 0x00000030
1345#define CPU_HW_BP 0x00000034
1346/* 0x38 --> 0x44 unused */
1347#define CPU_WDOG_SAVED_STATE 0x00000044
1348#define CPU_LAST_BRANCH_ADDR 0x00000048
1349#define CPU_SPAD_UFLOW_SET 0x0000004c
1350/* 0x50 --> 0x200 unused */
1351#define CPU_R0 0x00000200
1352#define CPU_R1 0x00000204
1353#define CPU_R2 0x00000208
1354#define CPU_R3 0x0000020c
1355#define CPU_R4 0x00000210
1356#define CPU_R5 0x00000214
1357#define CPU_R6 0x00000218
1358#define CPU_R7 0x0000021c
1359#define CPU_R8 0x00000220
1360#define CPU_R9 0x00000224
1361#define CPU_R10 0x00000228
1362#define CPU_R11 0x0000022c
1363#define CPU_R12 0x00000230
1364#define CPU_R13 0x00000234
1365#define CPU_R14 0x00000238
1366#define CPU_R15 0x0000023c
1367#define CPU_R16 0x00000240
1368#define CPU_R17 0x00000244
1369#define CPU_R18 0x00000248
1370#define CPU_R19 0x0000024c
1371#define CPU_R20 0x00000250
1372#define CPU_R21 0x00000254
1373#define CPU_R22 0x00000258
1374#define CPU_R23 0x0000025c
1375#define CPU_R24 0x00000260
1376#define CPU_R25 0x00000264
1377#define CPU_R26 0x00000268
1378#define CPU_R27 0x0000026c
1379#define CPU_R28 0x00000270
1380#define CPU_R29 0x00000274
1381#define CPU_R30 0x00000278
1382#define CPU_R31 0x0000027c
1383/* 0x280 --> 0x400 unused */
1384
1385#define RX_CPU_BASE 0x00005000
Chris Elmquist091465d2005-12-20 13:25:19 -08001386#define RX_CPU_MODE 0x00005000
1387#define RX_CPU_STATE 0x00005004
1388#define RX_CPU_PGMCTR 0x0000501c
1389#define RX_CPU_HWBKPT 0x00005034
Linus Torvalds1da177e2005-04-16 15:20:36 -07001390#define TX_CPU_BASE 0x00005400
Chris Elmquist091465d2005-12-20 13:25:19 -08001391#define TX_CPU_MODE 0x00005400
1392#define TX_CPU_STATE 0x00005404
1393#define TX_CPU_PGMCTR 0x0000541c
Linus Torvalds1da177e2005-04-16 15:20:36 -07001394
Michael Chanb5d37722006-09-27 16:06:21 -07001395#define VCPU_STATUS 0x00005100
1396#define VCPU_STATUS_INIT_DONE 0x04000000
1397#define VCPU_STATUS_DRV_RESET 0x08000000
1398
Matt Carlson8ed5d972007-05-07 00:25:49 -07001399#define VCPU_CFGSHDW 0x00005104
Matt Carlson0527ba32007-10-10 18:03:30 -07001400#define VCPU_CFGSHDW_WOL_ENABLE 0x00000001
1401#define VCPU_CFGSHDW_WOL_MAGPKT 0x00000004
Matt Carlson8ed5d972007-05-07 00:25:49 -07001402#define VCPU_CFGSHDW_ASPM_DBNC 0x00001000
1403
Linus Torvalds1da177e2005-04-16 15:20:36 -07001404/* Mailboxes */
Michael Chanb5d37722006-09-27 16:06:21 -07001405#define GRCMBOX_BASE 0x00005600
Linus Torvalds1da177e2005-04-16 15:20:36 -07001406#define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
1407#define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */
1408#define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */
1409#define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */
1410#define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */
1411#define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */
1412#define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */
1413#define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */
1414#define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */
1415#define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */
1416#define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */
1417#define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */
1418#define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */
1419#define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */
1420#define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */
1421#define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */
1422#define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */
1423#define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */
1424#define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */
1425#define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */
1426#define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */
1427#define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */
1428#define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */
1429#define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */
1430#define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */
1431#define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */
1432#define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */
1433#define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */
1434#define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */
1435#define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */
1436#define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */
1437#define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */
1438#define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */
1439#define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */
1440#define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */
1441#define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */
1442#define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */
1443#define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */
1444#define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */
1445#define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */
1446#define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */
1447#define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */
1448#define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */
1449#define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */
1450#define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */
1451#define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */
1452#define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */
1453#define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */
1454#define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */
1455#define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */
1456#define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */
1457#define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */
1458#define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */
1459#define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */
1460#define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */
1461#define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */
1462#define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */
1463#define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */
1464#define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */
1465#define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */
1466#define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */
1467#define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */
1468#define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */
1469#define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */
1470#define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00
1471#define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04
1472#define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08
1473#define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c
1474/* 0x5a10 --> 0x5c00 */
1475
1476/* Flow Through queues */
1477#define FTQ_RESET 0x00005c00
1478/* 0x5c04 --> 0x5c10 unused */
1479#define FTQ_DMA_NORM_READ_CTL 0x00005c10
1480#define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
1481#define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18
1482#define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c
1483#define FTQ_DMA_HIGH_READ_CTL 0x00005c20
1484#define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24
1485#define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28
1486#define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c
1487#define FTQ_DMA_COMP_DISC_CTL 0x00005c30
1488#define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34
1489#define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38
1490#define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c
1491#define FTQ_SEND_BD_COMP_CTL 0x00005c40
1492#define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44
1493#define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48
1494#define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c
1495#define FTQ_SEND_DATA_INIT_CTL 0x00005c50
1496#define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54
1497#define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58
1498#define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c
1499#define FTQ_DMA_NORM_WRITE_CTL 0x00005c60
1500#define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64
1501#define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68
1502#define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c
1503#define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70
1504#define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74
1505#define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78
1506#define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c
1507#define FTQ_SWTYPE1_CTL 0x00005c80
1508#define FTQ_SWTYPE1_FULL_CNT 0x00005c84
1509#define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88
1510#define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c
1511#define FTQ_SEND_DATA_COMP_CTL 0x00005c90
1512#define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94
1513#define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98
1514#define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c
1515#define FTQ_HOST_COAL_CTL 0x00005ca0
1516#define FTQ_HOST_COAL_FULL_CNT 0x00005ca4
1517#define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8
1518#define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac
1519#define FTQ_MAC_TX_CTL 0x00005cb0
1520#define FTQ_MAC_TX_FULL_CNT 0x00005cb4
1521#define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8
1522#define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc
1523#define FTQ_MB_FREE_CTL 0x00005cc0
1524#define FTQ_MB_FREE_FULL_CNT 0x00005cc4
1525#define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8
1526#define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc
1527#define FTQ_RCVBD_COMP_CTL 0x00005cd0
1528#define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4
1529#define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8
1530#define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc
1531#define FTQ_RCVLST_PLMT_CTL 0x00005ce0
1532#define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4
1533#define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8
1534#define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec
1535#define FTQ_RCVDATA_INI_CTL 0x00005cf0
1536#define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4
1537#define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8
1538#define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc
1539#define FTQ_RCVDATA_COMP_CTL 0x00005d00
1540#define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04
1541#define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08
1542#define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c
1543#define FTQ_SWTYPE2_CTL 0x00005d10
1544#define FTQ_SWTYPE2_FULL_CNT 0x00005d14
1545#define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18
1546#define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c
1547/* 0x5d20 --> 0x6000 unused */
1548
1549/* Message signaled interrupt registers */
1550#define MSGINT_MODE 0x00006000
1551#define MSGINT_MODE_RESET 0x00000001
1552#define MSGINT_MODE_ENABLE 0x00000002
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00001553#define MSGINT_MODE_ONE_SHOT_DISABLE 0x00000020
Matt Carlsonbaf8a942009-09-01 13:13:00 +00001554#define MSGINT_MODE_MULTIVEC_EN 0x00000080
Linus Torvalds1da177e2005-04-16 15:20:36 -07001555#define MSGINT_STATUS 0x00006004
1556#define MSGINT_FIFO 0x00006008
1557/* 0x600c --> 0x6400 unused */
1558
1559/* DMA completion registers */
1560#define DMAC_MODE 0x00006400
1561#define DMAC_MODE_RESET 0x00000001
1562#define DMAC_MODE_ENABLE 0x00000002
1563/* 0x6404 --> 0x6800 unused */
1564
1565/* GRC registers */
1566#define GRC_MODE 0x00006800
1567#define GRC_MODE_UPD_ON_COAL 0x00000001
1568#define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002
1569#define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
1570#define GRC_MODE_BSWAP_DATA 0x00000010
1571#define GRC_MODE_WSWAP_DATA 0x00000020
1572#define GRC_MODE_SPLITHDR 0x00000100
1573#define GRC_MODE_NOFRM_CRACKING 0x00000200
1574#define GRC_MODE_INCL_CRC 0x00000400
1575#define GRC_MODE_ALLOW_BAD_FRMS 0x00000800
1576#define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
1577#define GRC_MODE_NOIRQ_ON_RCV 0x00004000
1578#define GRC_MODE_FORCE_PCI32BIT 0x00008000
1579#define GRC_MODE_HOST_STACKUP 0x00010000
1580#define GRC_MODE_HOST_SENDBDS 0x00020000
1581#define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
1582#define GRC_MODE_NVRAM_WR_ENABLE 0x00200000
Matt Carlson614b0592010-01-20 16:58:02 +00001583#define GRC_MODE_PCIE_TL_SEL 0x00000000
1584#define GRC_MODE_PCIE_PL_SEL 0x00400000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001585#define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000
1586#define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000
1587#define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000
1588#define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000
1589#define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000
1590#define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000
1591#define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000
Matt Carlson614b0592010-01-20 16:58:02 +00001592#define GRC_MODE_PCIE_DL_SEL 0x20000000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001593#define GRC_MODE_MCAST_FRM_ENABLE 0x40000000
Matt Carlson614b0592010-01-20 16:58:02 +00001594#define GRC_MODE_PCIE_HI_1K_EN 0x80000000
1595#define GRC_MODE_PCIE_PORT_MASK (GRC_MODE_PCIE_TL_SEL | \
1596 GRC_MODE_PCIE_PL_SEL | \
1597 GRC_MODE_PCIE_DL_SEL | \
1598 GRC_MODE_PCIE_HI_1K_EN)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001599#define GRC_MISC_CFG 0x00006804
1600#define GRC_MISC_CFG_CORECLK_RESET 0x00000001
1601#define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe
1602#define GRC_MISC_CFG_PRESCALAR_SHIFT 1
1603#define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000
1604#define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000
1605#define GRC_MISC_CFG_BOARD_ID_5701 0x00000000
1606#define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000
1607#define GRC_MISC_CFG_BOARD_ID_5703 0x00000000
1608#define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000
1609#define GRC_MISC_CFG_BOARD_ID_5704 0x00000000
1610#define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1611#define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000
1612#define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
1613#define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
1614#define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
Michael Chan60189dd2006-12-17 17:08:07 -08001615#define GRC_MISC_CFG_EPHY_IDDQ 0x00200000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001616#define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
1617#define GRC_LOCAL_CTRL 0x00006808
1618#define GRC_LCLCTRL_INT_ACTIVE 0x00000001
1619#define GRC_LCLCTRL_CLEARINT 0x00000002
1620#define GRC_LCLCTRL_SETINT 0x00000004
1621#define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
Michael Chanaf36e6b2006-03-23 01:28:06 -08001622#define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */
Michael Chana4e2b342005-10-26 15:46:52 -07001623#define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */
1624#define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */
Michael Chan3e7d83b2005-04-21 17:10:36 -07001625#define GRC_LCLCTRL_GPIO_INPUT3 0x00000020
1626#define GRC_LCLCTRL_GPIO_OE3 0x00000040
1627#define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080
Linus Torvalds1da177e2005-04-16 15:20:36 -07001628#define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
1629#define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
1630#define GRC_LCLCTRL_GPIO_INPUT2 0x00000400
1631#define GRC_LCLCTRL_GPIO_OE0 0x00000800
1632#define GRC_LCLCTRL_GPIO_OE1 0x00001000
1633#define GRC_LCLCTRL_GPIO_OE2 0x00002000
1634#define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000
1635#define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000
1636#define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000
1637#define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000
1638#define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000
1639#define GRC_LCLCTRL_MEMSZ_256K 0x00000000
1640#define GRC_LCLCTRL_MEMSZ_512K 0x00040000
1641#define GRC_LCLCTRL_MEMSZ_1M 0x00080000
1642#define GRC_LCLCTRL_MEMSZ_2M 0x000c0000
1643#define GRC_LCLCTRL_MEMSZ_4M 0x00100000
1644#define GRC_LCLCTRL_MEMSZ_8M 0x00140000
1645#define GRC_LCLCTRL_MEMSZ_16M 0x00180000
1646#define GRC_LCLCTRL_BANK_SELECT 0x00200000
1647#define GRC_LCLCTRL_SSRAM_TYPE 0x00400000
1648#define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000
1649#define GRC_TIMER 0x0000680c
1650#define GRC_RX_CPU_EVENT 0x00006810
Matt Carlson7c5026a2008-05-02 16:49:29 -07001651#define GRC_RX_CPU_DRIVER_EVENT 0x00004000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001652#define GRC_RX_TIMER_REF 0x00006814
1653#define GRC_RX_CPU_SEM 0x00006818
1654#define GRC_REMOTE_RX_CPU_ATTN 0x0000681c
1655#define GRC_TX_CPU_EVENT 0x00006820
1656#define GRC_TX_TIMER_REF 0x00006824
1657#define GRC_TX_CPU_SEM 0x00006828
1658#define GRC_REMOTE_TX_CPU_ATTN 0x0000682c
1659#define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */
1660#define GRC_EEPROM_ADDR 0x00006838
1661#define EEPROM_ADDR_WRITE 0x00000000
1662#define EEPROM_ADDR_READ 0x80000000
1663#define EEPROM_ADDR_COMPLETE 0x40000000
1664#define EEPROM_ADDR_FSM_RESET 0x20000000
1665#define EEPROM_ADDR_DEVID_MASK 0x1c000000
1666#define EEPROM_ADDR_DEVID_SHIFT 26
1667#define EEPROM_ADDR_START 0x02000000
1668#define EEPROM_ADDR_CLKPERD_SHIFT 16
1669#define EEPROM_ADDR_ADDR_MASK 0x0000ffff
1670#define EEPROM_ADDR_ADDR_SHIFT 0
1671#define EEPROM_DEFAULT_CLOCK_PERIOD 0x60
1672#define EEPROM_CHIP_SIZE (64 * 1024)
1673#define GRC_EEPROM_DATA 0x0000683c
1674#define GRC_EEPROM_CTRL 0x00006840
1675#define GRC_MDI_CTRL 0x00006844
1676#define GRC_SEEPROM_DELAY 0x00006848
Michael Chanb5d37722006-09-27 16:06:21 -07001677/* 0x684c --> 0x6890 unused */
1678#define GRC_VCPU_EXT_CTRL 0x00006890
1679#define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000
1680#define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000
Michael Chand9ab5ad2006-03-20 22:27:35 -08001681#define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001682
1683/* 0x6c00 --> 0x7000 unused */
1684
1685/* NVRAM Control registers */
1686#define NVRAM_CMD 0x00007000
1687#define NVRAM_CMD_RESET 0x00000001
1688#define NVRAM_CMD_DONE 0x00000008
1689#define NVRAM_CMD_GO 0x00000010
1690#define NVRAM_CMD_WR 0x00000020
1691#define NVRAM_CMD_RD 0x00000000
1692#define NVRAM_CMD_ERASE 0x00000040
1693#define NVRAM_CMD_FIRST 0x00000080
1694#define NVRAM_CMD_LAST 0x00000100
1695#define NVRAM_CMD_WREN 0x00010000
1696#define NVRAM_CMD_WRDI 0x00020000
1697#define NVRAM_STAT 0x00007004
1698#define NVRAM_WRDATA 0x00007008
1699#define NVRAM_ADDR 0x0000700c
1700#define NVRAM_ADDR_MSK 0x00ffffff
1701#define NVRAM_RDDATA 0x00007010
1702#define NVRAM_CFG1 0x00007014
1703#define NVRAM_CFG1_FLASHIF_ENAB 0x00000001
1704#define NVRAM_CFG1_BUFFERED_MODE 0x00000002
1705#define NVRAM_CFG1_PASS_THRU 0x00000004
1706#define NVRAM_CFG1_STATUS_BITS 0x00000070
1707#define NVRAM_CFG1_BIT_BANG 0x00000008
1708#define NVRAM_CFG1_FLASH_SIZE 0x02000000
1709#define NVRAM_CFG1_COMPAT_BYPASS 0x80000000
1710#define NVRAM_CFG1_VENDOR_MASK 0x03000003
1711#define FLASH_VENDOR_ATMEL_EEPROM 0x02000000
1712#define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1713#define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003
1714#define FLASH_VENDOR_ST 0x03000001
1715#define FLASH_VENDOR_SAIFUN 0x01000003
1716#define FLASH_VENDOR_SST_SMALL 0x00000001
1717#define FLASH_VENDOR_SST_LARGE 0x02000001
Michael Chan361b4ac2005-04-21 17:11:21 -07001718#define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003
1719#define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000
1720#define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000
1721#define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1722#define FLASH_5752VENDOR_ST_M45PE10 0x02400000
1723#define FLASH_5752VENDOR_ST_M45PE20 0x02400002
1724#define FLASH_5752VENDOR_ST_M45PE40 0x02400001
Michael Chan1b277772006-03-20 22:27:48 -08001725#define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001
1726#define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002
1727#define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000
Michael Chand3c7b882006-03-23 01:28:25 -08001728#define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003
Matt Carlson70b65a22007-07-11 19:48:50 -07001729#define FLASH_5755VENDOR_ATMEL_FLASH_5 0x02000003
Michael Chand3c7b882006-03-23 01:28:25 -08001730#define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003
1731#define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002
Michael Chan1b277772006-03-20 22:27:48 -08001732#define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003
1733#define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002
1734#define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000
1735#define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000
Matt Carlson6b91fa02007-10-10 18:01:09 -07001736#define FLASH_5761VENDOR_ATMEL_MDB021D 0x00800003
1737#define FLASH_5761VENDOR_ATMEL_MDB041D 0x00800000
1738#define FLASH_5761VENDOR_ATMEL_MDB081D 0x00800002
1739#define FLASH_5761VENDOR_ATMEL_MDB161D 0x00800001
1740#define FLASH_5761VENDOR_ATMEL_ADB021D 0x00000003
1741#define FLASH_5761VENDOR_ATMEL_ADB041D 0x00000000
1742#define FLASH_5761VENDOR_ATMEL_ADB081D 0x00000002
1743#define FLASH_5761VENDOR_ATMEL_ADB161D 0x00000001
1744#define FLASH_5761VENDOR_ST_M_M45PE20 0x02800001
1745#define FLASH_5761VENDOR_ST_M_M45PE40 0x02800000
1746#define FLASH_5761VENDOR_ST_M_M45PE80 0x02800002
1747#define FLASH_5761VENDOR_ST_M_M45PE16 0x02800003
1748#define FLASH_5761VENDOR_ST_A_M45PE20 0x02000001
1749#define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000
1750#define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002
1751#define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003
Matt Carlson321d32a2008-11-21 17:22:19 -08001752#define FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000
1753#define FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000
1754#define FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002
1755#define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002
1756#define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001
1757#define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001
Matt Carlsona1b950d2009-09-01 13:20:17 +00001758#define FLASH_5717VENDOR_ATMEL_EEPROM 0x02000001
1759#define FLASH_5717VENDOR_MICRO_EEPROM 0x02000003
1760#define FLASH_5717VENDOR_ATMEL_MDB011D 0x01000001
1761#define FLASH_5717VENDOR_ATMEL_MDB021D 0x01000003
1762#define FLASH_5717VENDOR_ST_M_M25PE10 0x02000000
1763#define FLASH_5717VENDOR_ST_M_M25PE20 0x02000002
1764#define FLASH_5717VENDOR_ST_M_M45PE10 0x00000001
1765#define FLASH_5717VENDOR_ST_M_M45PE20 0x00000003
1766#define FLASH_5717VENDOR_ATMEL_ADB011B 0x01400000
1767#define FLASH_5717VENDOR_ATMEL_ADB021B 0x01400002
1768#define FLASH_5717VENDOR_ATMEL_ADB011D 0x01400001
1769#define FLASH_5717VENDOR_ATMEL_ADB021D 0x01400003
1770#define FLASH_5717VENDOR_ST_A_M25PE10 0x02400000
1771#define FLASH_5717VENDOR_ST_A_M25PE20 0x02400002
1772#define FLASH_5717VENDOR_ST_A_M45PE10 0x02400001
1773#define FLASH_5717VENDOR_ST_A_M45PE20 0x02400003
1774#define FLASH_5717VENDOR_ATMEL_45USPT 0x03400000
1775#define FLASH_5717VENDOR_ST_25USPT 0x03400002
1776#define FLASH_5717VENDOR_ST_45USPT 0x03400001
Michael Chan361b4ac2005-04-21 17:11:21 -07001777#define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
1778#define FLASH_5752PAGE_SIZE_256 0x00000000
1779#define FLASH_5752PAGE_SIZE_512 0x10000000
1780#define FLASH_5752PAGE_SIZE_1K 0x20000000
1781#define FLASH_5752PAGE_SIZE_2K 0x30000000
1782#define FLASH_5752PAGE_SIZE_4K 0x40000000
1783#define FLASH_5752PAGE_SIZE_264 0x50000000
Matt Carlson321d32a2008-11-21 17:22:19 -08001784#define FLASH_5752PAGE_SIZE_528 0x60000000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001785#define NVRAM_CFG2 0x00007018
1786#define NVRAM_CFG3 0x0000701c
1787#define NVRAM_SWARB 0x00007020
1788#define SWARB_REQ_SET0 0x00000001
1789#define SWARB_REQ_SET1 0x00000002
1790#define SWARB_REQ_SET2 0x00000004
1791#define SWARB_REQ_SET3 0x00000008
1792#define SWARB_REQ_CLR0 0x00000010
1793#define SWARB_REQ_CLR1 0x00000020
1794#define SWARB_REQ_CLR2 0x00000040
1795#define SWARB_REQ_CLR3 0x00000080
1796#define SWARB_GNT0 0x00000100
1797#define SWARB_GNT1 0x00000200
1798#define SWARB_GNT2 0x00000400
1799#define SWARB_GNT3 0x00000800
1800#define SWARB_REQ0 0x00001000
1801#define SWARB_REQ1 0x00002000
1802#define SWARB_REQ2 0x00004000
1803#define SWARB_REQ3 0x00008000
1804#define NVRAM_ACCESS 0x00007024
1805#define ACCESS_ENABLE 0x00000001
1806#define ACCESS_WR_ENABLE 0x00000002
1807#define NVRAM_WRITE1 0x00007028
Matt Carlson6b91fa02007-10-10 18:01:09 -07001808/* 0x702c unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001809
Matt Carlson6b91fa02007-10-10 18:01:09 -07001810#define NVRAM_ADDR_LOCKOUT 0x00007030
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001811/* 0x7034 --> 0x7500 unused */
1812
1813#define OTP_MODE 0x00007500
1814#define OTP_MODE_OTP_THRU_GRC 0x00000001
1815#define OTP_CTRL 0x00007504
1816#define OTP_CTRL_OTP_PROG_ENABLE 0x00200000
1817#define OTP_CTRL_OTP_CMD_READ 0x00000000
1818#define OTP_CTRL_OTP_CMD_INIT 0x00000008
1819#define OTP_CTRL_OTP_CMD_START 0x00000001
1820#define OTP_STATUS 0x00007508
1821#define OTP_STATUS_CMD_DONE 0x00000001
1822#define OTP_ADDRESS 0x0000750c
1823#define OTP_ADDRESS_MAGIC1 0x000000a0
1824#define OTP_ADDRESS_MAGIC2 0x00000080
1825/* 0x7510 unused */
1826
1827#define OTP_READ_DATA 0x00007514
1828/* 0x7518 --> 0x7c04 unused */
Matt Carlson6b91fa02007-10-10 18:01:09 -07001829
Michael Chanb5d37722006-09-27 16:06:21 -07001830#define PCIE_TRANSACTION_CFG 0x00007c04
1831#define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000
1832#define PCIE_TRANS_CFG_LOM 0x00000020
Matt Carlson521e6b92009-08-25 10:06:01 +00001833/* 0x7c08 --> 0x7d28 unused */
Michael Chanb5d37722006-09-27 16:06:21 -07001834
Matt Carlson8ed5d972007-05-07 00:25:49 -07001835#define PCIE_PWR_MGMT_THRESH 0x00007d28
1836#define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00
Matt Carlson33466d92009-04-20 06:57:41 +00001837#define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00
1838#define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000
Matt Carlson255ca312009-08-25 10:07:27 +00001839/* 0x7d2c --> 0x7d54 unused */
1840
1841#define TG3_PCIE_LNKCTL 0x00007d54
1842#define TG3_PCIE_LNKCTL_L1_PLL_PD_EN 0x00000008
1843#define TG3_PCIE_LNKCTL_L1_PLL_PD_DIS 0x00000080
1844/* 0x7d58 --> 0x7e70 unused */
Matt Carlson521e6b92009-08-25 10:06:01 +00001845
1846#define TG3_PCIE_EIDLE_DELAY 0x00007e70
1847#define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f
1848#define TG3_PCIE_EIDLE_DELAY_13_CLKS 0x0000000c
1849/* 0x7e74 --> 0x8000 unused */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001850
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001851
Matt Carlson614b0592010-01-20 16:58:02 +00001852/* Alternate PCIE definitions */
1853#define TG3_PCIE_TLDLPL_PORT 0x00007c00
1854#define TG3_PCIE_PL_LO_PHYCTL1 0x00000004
1855#define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000
Matt Carlsoncea46462010-04-12 06:58:24 +00001856#define TG3_PCIE_PL_LO_PHYCTL5 0x00000014
1857#define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000
Matt Carlson614b0592010-01-20 16:58:02 +00001858
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001859/* OTP bit definitions */
1860#define TG3_OTP_AGCTGT_MASK 0x000000e0
1861#define TG3_OTP_AGCTGT_SHIFT 1
1862#define TG3_OTP_HPFFLTR_MASK 0x00000300
1863#define TG3_OTP_HPFFLTR_SHIFT 1
1864#define TG3_OTP_HPFOVER_MASK 0x00000400
1865#define TG3_OTP_HPFOVER_SHIFT 1
1866#define TG3_OTP_LPFDIS_MASK 0x00000800
1867#define TG3_OTP_LPFDIS_SHIFT 11
1868#define TG3_OTP_VDAC_MASK 0xff000000
1869#define TG3_OTP_VDAC_SHIFT 24
1870#define TG3_OTP_10BTAMP_MASK 0x0000f000
1871#define TG3_OTP_10BTAMP_SHIFT 8
1872#define TG3_OTP_ROFF_MASK 0x00e00000
1873#define TG3_OTP_ROFF_SHIFT 11
1874#define TG3_OTP_RCOFF_MASK 0x001c0000
1875#define TG3_OTP_RCOFF_SHIFT 16
1876
1877#define TG3_OTP_DEFAULT 0x286c1640
1878
Matt Carlson141518c2009-12-03 08:36:22 +00001879
1880/* Hardware Legacy NVRAM layout */
1881#define TG3_NVM_VPD_OFF 0x100
1882#define TG3_NVM_VPD_LEN 256
1883
Matt Carlsona6f6cb12009-02-25 14:27:43 +00001884/* Hardware Selfboot NVRAM layout */
1885#define TG3_NVM_HWSB_CFG1 0x00000004
1886#define TG3_NVM_HWSB_CFG1_MAJMSK 0xf8000000
1887#define TG3_NVM_HWSB_CFG1_MAJSFT 27
1888#define TG3_NVM_HWSB_CFG1_MINMSK 0x07c00000
1889#define TG3_NVM_HWSB_CFG1_MINSFT 22
Matt Carlsonb2a5c192008-04-03 21:44:44 -07001890
Linus Torvalds1da177e2005-04-16 15:20:36 -07001891#define TG3_EEPROM_MAGIC 0x669955aa
Michael Chanb16250e2006-09-27 16:10:14 -07001892#define TG3_EEPROM_MAGIC_FW 0xa5000000
1893#define TG3_EEPROM_MAGIC_FW_MSK 0xff000000
Matt Carlsona5767de2007-11-12 21:10:58 -08001894#define TG3_EEPROM_SB_FORMAT_MASK 0x00e00000
1895#define TG3_EEPROM_SB_FORMAT_1 0x00200000
1896#define TG3_EEPROM_SB_REVISION_MASK 0x001f0000
1897#define TG3_EEPROM_SB_REVISION_0 0x00000000
1898#define TG3_EEPROM_SB_REVISION_2 0x00020000
1899#define TG3_EEPROM_SB_REVISION_3 0x00030000
Matt Carlsona4153d42010-02-17 15:16:56 +00001900#define TG3_EEPROM_SB_REVISION_4 0x00040000
1901#define TG3_EEPROM_SB_REVISION_5 0x00050000
Michael Chanb16250e2006-09-27 16:10:14 -07001902#define TG3_EEPROM_MAGIC_HW 0xabcd
1903#define TG3_EEPROM_MAGIC_HW_MSK 0xffff
Linus Torvalds1da177e2005-04-16 15:20:36 -07001904
Matt Carlson9c8a6202007-10-21 16:16:08 -07001905#define TG3_NVM_DIR_START 0x18
1906#define TG3_NVM_DIR_END 0x78
1907#define TG3_NVM_DIRENT_SIZE 0xc
1908#define TG3_NVM_DIRTYPE_SHIFT 24
1909#define TG3_NVM_DIRTYPE_ASFINI 1
Matt Carlsonff3a7cb2009-02-25 14:26:58 +00001910#define TG3_NVM_PTREV_BCVER 0x94
1911#define TG3_NVM_BCVER_MAJMSK 0x0000ff00
1912#define TG3_NVM_BCVER_MAJSFT 8
1913#define TG3_NVM_BCVER_MINMSK 0x000000ff
Matt Carlson9c8a6202007-10-21 16:16:08 -07001914
Matt Carlsondfe00d72008-11-21 17:19:41 -08001915#define TG3_EEPROM_SB_F1R0_EDH_OFF 0x10
1916#define TG3_EEPROM_SB_F1R2_EDH_OFF 0x14
1917#define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
1918#define TG3_EEPROM_SB_F1R3_EDH_OFF 0x18
Matt Carlsona4153d42010-02-17 15:16:56 +00001919#define TG3_EEPROM_SB_F1R4_EDH_OFF 0x1c
1920#define TG3_EEPROM_SB_F1R5_EDH_OFF 0x20
Matt Carlsondfe00d72008-11-21 17:19:41 -08001921#define TG3_EEPROM_SB_EDH_MAJ_MASK 0x00000700
1922#define TG3_EEPROM_SB_EDH_MAJ_SHFT 8
1923#define TG3_EEPROM_SB_EDH_MIN_MASK 0x000000ff
1924#define TG3_EEPROM_SB_EDH_BLD_MASK 0x0000f800
1925#define TG3_EEPROM_SB_EDH_BLD_SHFT 11
1926
1927
Linus Torvalds1da177e2005-04-16 15:20:36 -07001928/* 32K Window into NIC internal memory */
1929#define NIC_SRAM_WIN_BASE 0x00008000
1930
1931/* Offsets into first 32k of NIC internal memory. */
1932#define NIC_SRAM_PAGE_ZERO 0x00000000
1933#define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */
1934#define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */
1935#define NIC_SRAM_STATS_BLK 0x00000300
1936#define NIC_SRAM_STATUS_BLK 0x00000b00
1937
1938#define NIC_SRAM_FIRMWARE_MBOX 0x00000b50
1939#define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654
1940#define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */
1941
1942#define NIC_SRAM_DATA_SIG 0x00000b54
1943#define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */
1944
1945#define NIC_SRAM_DATA_CFG 0x00000b58
1946#define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c
1947#define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000
1948#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004
1949#define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008
1950#define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030
1951#define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000
1952#define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010
1953#define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020
1954#define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040
1955#define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080
1956#define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100
1957#define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000
1958#define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000
1959#define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000
Matt Carlson0d3031d2007-10-10 18:02:43 -07001960#define NIC_SRAM_DATA_CFG_APE_ENABLE 0x00200000
Linus Torvalds1da177e2005-04-16 15:20:36 -07001961
1962#define NIC_SRAM_DATA_VER 0x00000b5c
1963#define NIC_SRAM_DATA_VER_SHIFT 16
1964
1965#define NIC_SRAM_DATA_PHY_ID 0x00000b74
1966#define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000
1967#define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff
1968
1969#define NIC_SRAM_FW_CMD_MBOX 0x00000b78
1970#define FWCMD_NICDRV_ALIVE 0x00000001
1971#define FWCMD_NICDRV_PAUSE_FW 0x00000002
1972#define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003
1973#define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004
1974#define FWCMD_NICDRV_FIX_DMAR 0x00000005
1975#define FWCMD_NICDRV_FIX_DMAW 0x00000006
Matt Carlson7c5026a2008-05-02 16:49:29 -07001976#define FWCMD_NICDRV_LINK_UPDATE 0x0000000c
Michael Chan28fbef72005-10-26 15:48:35 -07001977#define FWCMD_NICDRV_ALIVE2 0x0000000d
Michael Chan130b8e42006-09-27 16:00:40 -07001978#define FWCMD_NICDRV_ALIVE3 0x0000000e
Linus Torvalds1da177e2005-04-16 15:20:36 -07001979#define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c
1980#define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80
1981#define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00
1982#define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04
1983#define DRV_STATE_START 0x00000001
1984#define DRV_STATE_START_DONE 0x80000001
1985#define DRV_STATE_UNLOAD 0x00000002
1986#define DRV_STATE_UNLOAD_DONE 0x80000002
1987#define DRV_STATE_WOL 0x00000003
1988#define DRV_STATE_SUSPEND 0x00000004
1989
1990#define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08
1991
1992#define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
1993#define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
1994
Michael Chan6921d202005-12-13 21:15:53 -08001995#define NIC_SRAM_WOL_MBOX 0x00000d30
1996#define WOL_SIGNATURE 0x474c0000
1997#define WOL_DRV_STATE_SHUTDOWN 0x00000001
1998#define WOL_DRV_WOL 0x00000002
1999#define WOL_SET_MAGIC_PKT 0x00000004
2000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002001#define NIC_SRAM_DATA_CFG_2 0x00000d38
2002
Matt Carlson6833c042008-11-21 17:18:59 -08002003#define NIC_SRAM_DATA_CFG_2_APD_EN 0x00000400
Linus Torvalds1da177e2005-04-16 15:20:36 -07002004#define SHASTA_EXT_LED_MODE_MASK 0x00018000
2005#define SHASTA_EXT_LED_LEGACY 0x00000000
2006#define SHASTA_EXT_LED_SHARED 0x00008000
2007#define SHASTA_EXT_LED_MAC 0x00010000
2008#define SHASTA_EXT_LED_COMBO 0x00018000
2009
Matt Carlson8ed5d972007-05-07 00:25:49 -07002010#define NIC_SRAM_DATA_CFG_3 0x00000d3c
2011#define NIC_SRAM_ASPM_DEBOUNCE 0x00000002
2012
Matt Carlsona9daf362008-05-25 23:49:44 -07002013#define NIC_SRAM_DATA_CFG_4 0x00000d60
2014#define NIC_SRAM_GMII_MODE 0x00000002
Matt Carlson14417062010-02-17 15:16:59 +00002015#define NIC_SRAM_RGMII_INBAND_DISABLE 0x00000004
Matt Carlsona9daf362008-05-25 23:49:44 -07002016#define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008
2017#define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010
2018
Linus Torvalds1da177e2005-04-16 15:20:36 -07002019#define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
2020
2021#define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
2022#define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000
2023#define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */
2024#define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */
2025#define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */
2026#define NIC_SRAM_MBUF_POOL_BASE 0x00008000
2027#define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000
2028#define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000
2029#define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
2030#define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
2031
Matt Carlson52cdf852009-11-02 14:25:06 +00002032
Linus Torvalds1da177e2005-04-16 15:20:36 -07002033/* Currently this is fixed. */
Matt Carlson52cdf852009-11-02 14:25:06 +00002034#define TG3_PHY_PCIE_ADDR 0x00
Matt Carlson3f0e3ad2009-11-02 14:24:36 +00002035#define TG3_PHY_MII_ADDR 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -07002036
Matt Carlson52cdf852009-11-02 14:25:06 +00002037
2038/*** Tigon3 specific PHY PCIE registers. ***/
2039
2040#define TG3_PCIEPHY_BLOCK_ADDR 0x1f
2041#define TG3_PCIEPHY_XGXS_BLK1 0x0801
2042#define TG3_PCIEPHY_TXB_BLK 0x0861
2043#define TG3_PCIEPHY_BLOCK_SHIFT 4
2044
2045/* TG3_PCIEPHY_TXB_BLK */
2046#define TG3_PCIEPHY_TX0CTRL1 0x15
2047#define TG3_PCIEPHY_TX0CTRL1_TXOCM 0x0003
2048#define TG3_PCIEPHY_TX0CTRL1_RDCTL 0x0008
2049#define TG3_PCIEPHY_TX0CTRL1_TXCMV 0x0030
2050#define TG3_PCIEPHY_TX0CTRL1_TKSEL 0x0040
2051#define TG3_PCIEPHY_TX0CTRL1_NB_EN 0x0400
2052
2053/* TG3_PCIEPHY_XGXS_BLK1 */
2054#define TG3_PCIEPHY_PWRMGMT4 0x1a
2055#define TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN 0x0038
2056#define TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN 0x4000
2057
2058
2059/*** Tigon3 specific PHY MII registers. ***/
Linus Torvalds1da177e2005-04-16 15:20:36 -07002060#define TG3_BMCR_SPEED1000 0x0040
2061
2062#define MII_TG3_CTRL 0x09 /* 1000-baseT control register */
2063#define MII_TG3_CTRL_ADV_1000_HALF 0x0100
2064#define MII_TG3_CTRL_ADV_1000_FULL 0x0200
2065#define MII_TG3_CTRL_AS_MASTER 0x0800
2066#define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
2067
2068#define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
2069#define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
2070#define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
Michael Chan6921d202005-12-13 21:15:53 -08002071#define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
Linus Torvalds1da177e2005-04-16 15:20:36 -07002072#define MII_TG3_EXT_CTRL_TBI 0x8000
2073
2074#define MII_TG3_EXT_STAT 0x11 /* Extended status register */
2075#define MII_TG3_EXT_STAT_LPASS 0x0100
2076
2077#define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
2078
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002079#define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
2080
2081#define MII_TG3_DSP_TAP1 0x0001
2082#define MII_TG3_DSP_TAP1_AGCTGT_DFLT 0x0007
2083#define MII_TG3_DSP_AADJ1CH0 0x001f
2084#define MII_TG3_DSP_AADJ1CH3 0x601f
2085#define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002
Matt Carlsonc1f614a2010-04-05 10:19:19 +00002086#define MII_TG3_DSP_EXP8 0x0f08
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002087#define MII_TG3_DSP_EXP8_REJ2MHz 0x0001
2088#define MII_TG3_DSP_EXP8_AEDW 0x0200
2089#define MII_TG3_DSP_EXP75 0x0f75
2090#define MII_TG3_DSP_EXP96 0x0f96
2091#define MII_TG3_DSP_EXP97 0x0f97
Linus Torvalds1da177e2005-04-16 15:20:36 -07002092
2093#define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */
2094
Matt Carlson0a459aa2008-11-03 16:54:15 -08002095#define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010
2096#define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020
2097#define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180
2098#define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002
2099
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002100#define MII_TG3_AUXCTL_MISC_WREN 0x8000
2101#define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
2102#define MII_TG3_AUXCTL_MISC_RDSEL_MISC 0x7000
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002103#define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007
2104
2105#define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800
2106#define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400
2107#define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000
Matt Carlson9ef8ca92007-07-11 19:48:29 -07002108
Linus Torvalds1da177e2005-04-16 15:20:36 -07002109#define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */
2110#define MII_TG3_AUX_STAT_LPASS 0x0004
2111#define MII_TG3_AUX_STAT_SPDMASK 0x0700
2112#define MII_TG3_AUX_STAT_10HALF 0x0100
2113#define MII_TG3_AUX_STAT_10FULL 0x0200
2114#define MII_TG3_AUX_STAT_100HALF 0x0300
2115#define MII_TG3_AUX_STAT_100_4 0x0400
2116#define MII_TG3_AUX_STAT_100FULL 0x0500
2117#define MII_TG3_AUX_STAT_1000HALF 0x0600
2118#define MII_TG3_AUX_STAT_1000FULL 0x0700
Michael Chan715116a2006-09-27 16:09:25 -07002119#define MII_TG3_AUX_STAT_100 0x0008
2120#define MII_TG3_AUX_STAT_FULL 0x0001
Linus Torvalds1da177e2005-04-16 15:20:36 -07002121
2122#define MII_TG3_ISTAT 0x1a /* IRQ status register */
2123#define MII_TG3_IMASK 0x1b /* IRQ mask register */
2124
2125/* ISTAT/IMASK event bits */
2126#define MII_TG3_INT_LINKCHG 0x0002
2127#define MII_TG3_INT_SPEEDCHG 0x0004
2128#define MII_TG3_INT_DUPLEXCHG 0x0008
2129#define MII_TG3_INT_ANEG_PAGE_RX 0x0400
2130
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002131#define MII_TG3_MISC_SHDW 0x1c
2132#define MII_TG3_MISC_SHDW_WREN 0x8000
Matt Carlsonaa10f272008-12-21 20:21:18 -08002133
2134#define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001
2135#define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002136#define MII_TG3_MISC_SHDW_APD_SEL 0x2800
2137
2138#define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001
2139#define MII_TG3_MISC_SHDW_SCR5_DLLAPD 0x0002
2140#define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004
2141#define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008
2142#define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010
Matt Carlsonaa10f272008-12-21 20:21:18 -08002143#define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002144
Michael Chanc1d2a192007-01-08 19:57:20 -08002145#define MII_TG3_TEST1 0x1e
2146#define MII_TG3_TEST1_TRIM_EN 0x0010
Michael Chan569a5df2007-02-13 12:18:15 -08002147#define MII_TG3_TEST1_CRC_EN 0x8000
Michael Chanc1d2a192007-01-08 19:57:20 -08002148
Matt Carlson535ef6e2009-08-25 10:09:36 +00002149
2150/* Fast Ethernet Tranceiver definitions */
2151#define MII_TG3_FET_PTEST 0x17
Matt Carlson1061b7c2010-02-12 14:47:12 +00002152#define MII_TG3_FET_PTEST_FRC_TX_LINK 0x1000
2153#define MII_TG3_FET_PTEST_FRC_TX_LOCK 0x0800
2154
Matt Carlson535ef6e2009-08-25 10:09:36 +00002155#define MII_TG3_FET_TEST 0x1f
2156#define MII_TG3_FET_SHADOW_EN 0x0080
2157
2158#define MII_TG3_FET_SHDW_MISCCTRL 0x10
2159#define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000
2160
Matt Carlson0e5f7842009-11-02 14:26:38 +00002161#define MII_TG3_FET_SHDW_AUXMODE4 0x1a
2162#define MII_TG3_FET_SHDW_AUXMODE4_SBPD 0x0008
2163
Matt Carlson535ef6e2009-08-25 10:09:36 +00002164#define MII_TG3_FET_SHDW_AUXSTAT2 0x1b
2165#define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020
2166
2167
Matt Carlson0d3031d2007-10-10 18:02:43 -07002168/* APE registers. Accessible through BAR1 */
2169#define TG3_APE_EVENT 0x000c
2170#define APE_EVENT_1 0x00000001
2171#define TG3_APE_LOCK_REQ 0x002c
2172#define APE_LOCK_REQ_DRIVER 0x00001000
2173#define TG3_APE_LOCK_GRANT 0x004c
2174#define APE_LOCK_GRANT_DRIVER 0x00001000
2175#define TG3_APE_SEG_SIG 0x4000
2176#define APE_SEG_SIG_MAGIC 0x41504521
2177
2178/* APE shared memory. Accessible through BAR1 */
2179#define TG3_APE_FW_STATUS 0x400c
2180#define APE_FW_STATUS_READY 0x00000100
Matt Carlson7fd76442009-02-25 14:27:20 +00002181#define TG3_APE_FW_VERSION 0x4018
2182#define APE_FW_VERSION_MAJMSK 0xff000000
2183#define APE_FW_VERSION_MAJSFT 24
2184#define APE_FW_VERSION_MINMSK 0x00ff0000
2185#define APE_FW_VERSION_MINSFT 16
2186#define APE_FW_VERSION_REVMSK 0x0000ff00
2187#define APE_FW_VERSION_REVSFT 8
2188#define APE_FW_VERSION_BLDMSK 0x000000ff
Matt Carlson0d3031d2007-10-10 18:02:43 -07002189#define TG3_APE_HOST_SEG_SIG 0x4200
2190#define APE_HOST_SEG_SIG_MAGIC 0x484f5354
2191#define TG3_APE_HOST_SEG_LEN 0x4204
2192#define APE_HOST_SEG_LEN_MAGIC 0x0000001c
2193#define TG3_APE_HOST_INIT_COUNT 0x4208
2194#define TG3_APE_HOST_DRIVER_ID 0x420c
2195#define APE_HOST_DRIVER_ID_MAGIC 0xf0035100
2196#define TG3_APE_HOST_BEHAVIOR 0x4210
2197#define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001
2198#define TG3_APE_HOST_HEARTBEAT_INT_MS 0x4214
2199#define APE_HOST_HEARTBEAT_INT_DISABLE 0
2200#define APE_HOST_HEARTBEAT_INT_5SEC 5000
2201#define TG3_APE_HOST_HEARTBEAT_COUNT 0x4218
2202
2203#define TG3_APE_EVENT_STATUS 0x4300
2204
2205#define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010
2206#define APE_EVENT_STATUS_STATE_CHNGE 0x00000500
2207#define APE_EVENT_STATUS_STATE_START 0x00010000
2208#define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000
2209#define APE_EVENT_STATUS_STATE_WOL 0x00030000
2210#define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000
2211#define APE_EVENT_STATUS_EVENT_PENDING 0x80000000
2212
Matt Carlsonf92d9dc12010-06-05 17:24:30 +00002213#define TG3_APE_PER_LOCK_REQ 0x8400
2214#define APE_LOCK_PER_REQ_DRIVER 0x00001000
2215#define TG3_APE_PER_LOCK_GRANT 0x8420
2216#define APE_PER_LOCK_GRANT_DRIVER 0x00001000
2217
Matt Carlson0d3031d2007-10-10 18:02:43 -07002218/* APE convenience enumerations. */
Matt Carlson77b483f2008-08-15 14:07:24 -07002219#define TG3_APE_LOCK_GRC 1
Matt Carlson0d3031d2007-10-10 18:02:43 -07002220#define TG3_APE_LOCK_MEM 4
2221
Matt Carlsona5767de2007-11-12 21:10:58 -08002222#define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
2223
Matt Carlson0d3031d2007-10-10 18:02:43 -07002224
Linus Torvalds1da177e2005-04-16 15:20:36 -07002225/* There are two ways to manage the TX descriptors on the tigon3.
2226 * Either the descriptors are in host DMA'able memory, or they
2227 * exist only in the cards on-chip SRAM. All 16 send bds are under
2228 * the same mode, they may not be configured individually.
2229 *
2230 * This driver always uses host memory TX descriptors.
2231 *
2232 * To use host memory TX descriptors:
2233 * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
2234 * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
2235 * 2) Allocate DMA'able memory.
2236 * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
2237 * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
2238 * obtained in step 2
2239 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
2240 * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
2241 * of TX descriptors. Leave flags field clear.
2242 * 4) Access TX descriptors via host memory. The chip
2243 * will refetch into local SRAM as needed when producer
2244 * index mailboxes are updated.
2245 *
2246 * To use on-chip TX descriptors:
2247 * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
2248 * Make sure GRC_MODE_HOST_SENDBDS is clear.
2249 * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
2250 * a) Set TG3_BDINFO_HOST_ADDR to zero.
2251 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
2252 * c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
2253 * 3) Access TX descriptors directly in on-chip SRAM
2254 * using normal {read,write}l(). (and not using
2255 * pointer dereferencing of ioremap()'d memory like
2256 * the broken Broadcom driver does)
2257 *
2258 * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
2259 * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
2260 */
2261struct tg3_tx_buffer_desc {
2262 u32 addr_hi;
2263 u32 addr_lo;
2264
2265 u32 len_flags;
2266#define TXD_FLAG_TCPUDP_CSUM 0x0001
2267#define TXD_FLAG_IP_CSUM 0x0002
2268#define TXD_FLAG_END 0x0004
2269#define TXD_FLAG_IP_FRAG 0x0008
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00002270#define TXD_FLAG_JMB_PKT 0x0008
Linus Torvalds1da177e2005-04-16 15:20:36 -07002271#define TXD_FLAG_IP_FRAG_END 0x0010
2272#define TXD_FLAG_VLAN 0x0040
2273#define TXD_FLAG_COAL_NOW 0x0080
2274#define TXD_FLAG_CPU_PRE_DMA 0x0100
2275#define TXD_FLAG_CPU_POST_DMA 0x0200
2276#define TXD_FLAG_ADD_SRC_ADDR 0x1000
2277#define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000
2278#define TXD_FLAG_NO_CRC 0x8000
2279#define TXD_LEN_SHIFT 16
2280
2281 u32 vlan_tag;
2282#define TXD_VLAN_TAG_SHIFT 0
2283#define TXD_MSS_SHIFT 16
2284};
2285
2286#define TXD_ADDR 0x00UL /* 64-bit */
2287#define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */
2288#define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */
2289#define TXD_SIZE 0x10UL
2290
2291struct tg3_rx_buffer_desc {
2292 u32 addr_hi;
2293 u32 addr_lo;
2294
2295 u32 idx_len;
2296#define RXD_IDX_MASK 0xffff0000
2297#define RXD_IDX_SHIFT 16
2298#define RXD_LEN_MASK 0x0000ffff
2299#define RXD_LEN_SHIFT 0
2300
2301 u32 type_flags;
2302#define RXD_TYPE_SHIFT 16
2303#define RXD_FLAGS_SHIFT 0
2304
2305#define RXD_FLAG_END 0x0004
2306#define RXD_FLAG_MINI 0x0800
2307#define RXD_FLAG_JUMBO 0x0020
2308#define RXD_FLAG_VLAN 0x0040
2309#define RXD_FLAG_ERROR 0x0400
2310#define RXD_FLAG_IP_CSUM 0x1000
2311#define RXD_FLAG_TCPUDP_CSUM 0x2000
2312#define RXD_FLAG_IS_TCP 0x4000
2313
2314 u32 ip_tcp_csum;
2315#define RXD_IPCSUM_MASK 0xffff0000
2316#define RXD_IPCSUM_SHIFT 16
2317#define RXD_TCPCSUM_MASK 0x0000ffff
2318#define RXD_TCPCSUM_SHIFT 0
2319
2320 u32 err_vlan;
2321
2322#define RXD_VLAN_MASK 0x0000ffff
2323
2324#define RXD_ERR_BAD_CRC 0x00010000
2325#define RXD_ERR_COLLISION 0x00020000
2326#define RXD_ERR_LINK_LOST 0x00040000
2327#define RXD_ERR_PHY_DECODE 0x00080000
2328#define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000
2329#define RXD_ERR_MAC_ABRT 0x00200000
2330#define RXD_ERR_TOO_SMALL 0x00400000
2331#define RXD_ERR_NO_RESOURCES 0x00800000
2332#define RXD_ERR_HUGE_FRAME 0x01000000
2333#define RXD_ERR_MASK 0xffff0000
2334
2335 u32 reserved;
2336 u32 opaque;
2337#define RXD_OPAQUE_INDEX_MASK 0x0000ffff
2338#define RXD_OPAQUE_INDEX_SHIFT 0
2339#define RXD_OPAQUE_RING_STD 0x00010000
2340#define RXD_OPAQUE_RING_JUMBO 0x00020000
2341#define RXD_OPAQUE_RING_MINI 0x00040000
2342#define RXD_OPAQUE_RING_MASK 0x00070000
2343};
2344
2345struct tg3_ext_rx_buffer_desc {
2346 struct {
2347 u32 addr_hi;
2348 u32 addr_lo;
2349 } addrlist[3];
2350 u32 len2_len1;
2351 u32 resv_len3;
2352 struct tg3_rx_buffer_desc std;
2353};
2354
2355/* We only use this when testing out the DMA engine
2356 * at probe time. This is the internal format of buffer
2357 * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
2358 */
2359struct tg3_internal_buffer_desc {
2360 u32 addr_hi;
2361 u32 addr_lo;
2362 u32 nic_mbuf;
2363 /* XXX FIX THIS */
2364#ifdef __BIG_ENDIAN
2365 u16 cqid_sqid;
2366 u16 len;
2367#else
2368 u16 len;
2369 u16 cqid_sqid;
2370#endif
2371 u32 flags;
2372 u32 __cookie1;
2373 u32 __cookie2;
2374 u32 __cookie3;
2375};
2376
2377#define TG3_HW_STATUS_SIZE 0x50
2378struct tg3_hw_status {
2379 u32 status;
2380#define SD_STATUS_UPDATED 0x00000001
2381#define SD_STATUS_LINK_CHG 0x00000002
2382#define SD_STATUS_ERROR 0x00000004
2383
2384 u32 status_tag;
2385
2386#ifdef __BIG_ENDIAN
2387 u16 rx_consumer;
2388 u16 rx_jumbo_consumer;
2389#else
2390 u16 rx_jumbo_consumer;
2391 u16 rx_consumer;
2392#endif
2393
2394#ifdef __BIG_ENDIAN
2395 u16 reserved;
2396 u16 rx_mini_consumer;
2397#else
2398 u16 rx_mini_consumer;
2399 u16 reserved;
2400#endif
2401 struct {
2402#ifdef __BIG_ENDIAN
2403 u16 tx_consumer;
2404 u16 rx_producer;
2405#else
2406 u16 rx_producer;
2407 u16 tx_consumer;
2408#endif
2409 } idx[16];
2410};
2411
2412typedef struct {
2413 u32 high, low;
2414} tg3_stat64_t;
2415
2416struct tg3_hw_stats {
2417 u8 __reserved0[0x400-0x300];
2418
2419 /* Statistics maintained by Receive MAC. */
2420 tg3_stat64_t rx_octets;
2421 u64 __reserved1;
2422 tg3_stat64_t rx_fragments;
2423 tg3_stat64_t rx_ucast_packets;
2424 tg3_stat64_t rx_mcast_packets;
2425 tg3_stat64_t rx_bcast_packets;
2426 tg3_stat64_t rx_fcs_errors;
2427 tg3_stat64_t rx_align_errors;
2428 tg3_stat64_t rx_xon_pause_rcvd;
2429 tg3_stat64_t rx_xoff_pause_rcvd;
2430 tg3_stat64_t rx_mac_ctrl_rcvd;
2431 tg3_stat64_t rx_xoff_entered;
2432 tg3_stat64_t rx_frame_too_long_errors;
2433 tg3_stat64_t rx_jabbers;
2434 tg3_stat64_t rx_undersize_packets;
2435 tg3_stat64_t rx_in_length_errors;
2436 tg3_stat64_t rx_out_length_errors;
2437 tg3_stat64_t rx_64_or_less_octet_packets;
2438 tg3_stat64_t rx_65_to_127_octet_packets;
2439 tg3_stat64_t rx_128_to_255_octet_packets;
2440 tg3_stat64_t rx_256_to_511_octet_packets;
2441 tg3_stat64_t rx_512_to_1023_octet_packets;
2442 tg3_stat64_t rx_1024_to_1522_octet_packets;
2443 tg3_stat64_t rx_1523_to_2047_octet_packets;
2444 tg3_stat64_t rx_2048_to_4095_octet_packets;
2445 tg3_stat64_t rx_4096_to_8191_octet_packets;
2446 tg3_stat64_t rx_8192_to_9022_octet_packets;
2447
2448 u64 __unused0[37];
2449
2450 /* Statistics maintained by Transmit MAC. */
2451 tg3_stat64_t tx_octets;
2452 u64 __reserved2;
2453 tg3_stat64_t tx_collisions;
2454 tg3_stat64_t tx_xon_sent;
2455 tg3_stat64_t tx_xoff_sent;
2456 tg3_stat64_t tx_flow_control;
2457 tg3_stat64_t tx_mac_errors;
2458 tg3_stat64_t tx_single_collisions;
2459 tg3_stat64_t tx_mult_collisions;
2460 tg3_stat64_t tx_deferred;
2461 u64 __reserved3;
2462 tg3_stat64_t tx_excessive_collisions;
2463 tg3_stat64_t tx_late_collisions;
2464 tg3_stat64_t tx_collide_2times;
2465 tg3_stat64_t tx_collide_3times;
2466 tg3_stat64_t tx_collide_4times;
2467 tg3_stat64_t tx_collide_5times;
2468 tg3_stat64_t tx_collide_6times;
2469 tg3_stat64_t tx_collide_7times;
2470 tg3_stat64_t tx_collide_8times;
2471 tg3_stat64_t tx_collide_9times;
2472 tg3_stat64_t tx_collide_10times;
2473 tg3_stat64_t tx_collide_11times;
2474 tg3_stat64_t tx_collide_12times;
2475 tg3_stat64_t tx_collide_13times;
2476 tg3_stat64_t tx_collide_14times;
2477 tg3_stat64_t tx_collide_15times;
2478 tg3_stat64_t tx_ucast_packets;
2479 tg3_stat64_t tx_mcast_packets;
2480 tg3_stat64_t tx_bcast_packets;
2481 tg3_stat64_t tx_carrier_sense_errors;
2482 tg3_stat64_t tx_discards;
2483 tg3_stat64_t tx_errors;
2484
2485 u64 __unused1[31];
2486
2487 /* Statistics maintained by Receive List Placement. */
2488 tg3_stat64_t COS_rx_packets[16];
2489 tg3_stat64_t COS_rx_filter_dropped;
2490 tg3_stat64_t dma_writeq_full;
2491 tg3_stat64_t dma_write_prioq_full;
2492 tg3_stat64_t rxbds_empty;
2493 tg3_stat64_t rx_discards;
2494 tg3_stat64_t rx_errors;
2495 tg3_stat64_t rx_threshold_hit;
2496
2497 u64 __unused2[9];
2498
2499 /* Statistics maintained by Send Data Initiator. */
2500 tg3_stat64_t COS_out_packets[16];
2501 tg3_stat64_t dma_readq_full;
2502 tg3_stat64_t dma_read_prioq_full;
2503 tg3_stat64_t tx_comp_queue_full;
2504
2505 /* Statistics maintained by Host Coalescing. */
2506 tg3_stat64_t ring_set_send_prod_index;
2507 tg3_stat64_t ring_status_update;
2508 tg3_stat64_t nic_irqs;
2509 tg3_stat64_t nic_avoided_irqs;
2510 tg3_stat64_t nic_tx_threshold_hit;
2511
2512 u8 __reserved4[0xb00-0x9c0];
2513};
2514
2515/* 'mapping' is superfluous as the chip does not write into
2516 * the tx/rx post rings so we could just fetch it from there.
2517 * But the cache behavior is better how we are doing it now.
2518 */
2519struct ring_info {
2520 struct sk_buff *skb;
FUJITA Tomonori4e5e4f02010-04-12 14:32:09 +00002521 DEFINE_DMA_UNMAP_ADDR(mapping);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002522};
2523
Linus Torvalds1da177e2005-04-16 15:20:36 -07002524struct tg3_config_info {
2525 u32 flags;
2526};
2527
2528struct tg3_link_config {
2529 /* Describes what we're trying to get. */
2530 u32 advertising;
2531 u16 speed;
2532 u8 duplex;
2533 u8 autoneg;
Matt Carlson8d018622007-12-20 20:05:44 -08002534 u8 flowctrl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002535
2536 /* Describes what we actually have. */
Matt Carlson8d018622007-12-20 20:05:44 -08002537 u8 active_flowctrl;
2538
Linus Torvalds1da177e2005-04-16 15:20:36 -07002539 u8 active_duplex;
2540#define SPEED_INVALID 0xffff
2541#define DUPLEX_INVALID 0xff
2542#define AUTONEG_INVALID 0xff
Matt Carlson8d018622007-12-20 20:05:44 -08002543 u16 active_speed;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002544
2545 /* When we go in and out of low power mode we need
2546 * to swap with this state.
2547 */
2548 int phy_is_low_power;
2549 u16 orig_speed;
2550 u8 orig_duplex;
2551 u8 orig_autoneg;
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002552 u32 orig_advertising;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002553};
2554
2555struct tg3_bufmgr_config {
2556 u32 mbuf_read_dma_low_water;
2557 u32 mbuf_mac_rx_low_water;
2558 u32 mbuf_high_water;
2559
2560 u32 mbuf_read_dma_low_water_jumbo;
2561 u32 mbuf_mac_rx_low_water_jumbo;
2562 u32 mbuf_high_water_jumbo;
2563
2564 u32 dma_low_water;
2565 u32 dma_high_water;
2566};
2567
2568struct tg3_ethtool_stats {
2569 /* Statistics maintained by Receive MAC. */
Matt Carlsonc6cdf432010-04-05 10:19:26 +00002570 u64 rx_octets;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002571 u64 rx_fragments;
2572 u64 rx_ucast_packets;
2573 u64 rx_mcast_packets;
2574 u64 rx_bcast_packets;
2575 u64 rx_fcs_errors;
2576 u64 rx_align_errors;
2577 u64 rx_xon_pause_rcvd;
2578 u64 rx_xoff_pause_rcvd;
2579 u64 rx_mac_ctrl_rcvd;
2580 u64 rx_xoff_entered;
2581 u64 rx_frame_too_long_errors;
2582 u64 rx_jabbers;
2583 u64 rx_undersize_packets;
2584 u64 rx_in_length_errors;
2585 u64 rx_out_length_errors;
2586 u64 rx_64_or_less_octet_packets;
2587 u64 rx_65_to_127_octet_packets;
2588 u64 rx_128_to_255_octet_packets;
2589 u64 rx_256_to_511_octet_packets;
2590 u64 rx_512_to_1023_octet_packets;
2591 u64 rx_1024_to_1522_octet_packets;
2592 u64 rx_1523_to_2047_octet_packets;
2593 u64 rx_2048_to_4095_octet_packets;
2594 u64 rx_4096_to_8191_octet_packets;
2595 u64 rx_8192_to_9022_octet_packets;
2596
2597 /* Statistics maintained by Transmit MAC. */
2598 u64 tx_octets;
2599 u64 tx_collisions;
2600 u64 tx_xon_sent;
2601 u64 tx_xoff_sent;
2602 u64 tx_flow_control;
2603 u64 tx_mac_errors;
2604 u64 tx_single_collisions;
2605 u64 tx_mult_collisions;
2606 u64 tx_deferred;
2607 u64 tx_excessive_collisions;
2608 u64 tx_late_collisions;
2609 u64 tx_collide_2times;
2610 u64 tx_collide_3times;
2611 u64 tx_collide_4times;
2612 u64 tx_collide_5times;
2613 u64 tx_collide_6times;
2614 u64 tx_collide_7times;
2615 u64 tx_collide_8times;
2616 u64 tx_collide_9times;
2617 u64 tx_collide_10times;
2618 u64 tx_collide_11times;
2619 u64 tx_collide_12times;
2620 u64 tx_collide_13times;
2621 u64 tx_collide_14times;
2622 u64 tx_collide_15times;
2623 u64 tx_ucast_packets;
2624 u64 tx_mcast_packets;
2625 u64 tx_bcast_packets;
2626 u64 tx_carrier_sense_errors;
2627 u64 tx_discards;
2628 u64 tx_errors;
2629
2630 /* Statistics maintained by Receive List Placement. */
2631 u64 dma_writeq_full;
2632 u64 dma_write_prioq_full;
2633 u64 rxbds_empty;
2634 u64 rx_discards;
2635 u64 rx_errors;
2636 u64 rx_threshold_hit;
2637
2638 /* Statistics maintained by Send Data Initiator. */
2639 u64 dma_readq_full;
2640 u64 dma_read_prioq_full;
2641 u64 tx_comp_queue_full;
2642
2643 /* Statistics maintained by Host Coalescing. */
2644 u64 ring_set_send_prod_index;
2645 u64 ring_status_update;
2646 u64 nic_irqs;
2647 u64 nic_avoided_irqs;
2648 u64 nic_tx_threshold_hit;
2649};
2650
Matt Carlson21f581a2009-08-28 14:00:25 +00002651struct tg3_rx_prodring_set {
Matt Carlson411da642009-11-13 13:03:46 +00002652 u32 rx_std_prod_idx;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00002653 u32 rx_std_cons_idx;
Matt Carlson411da642009-11-13 13:03:46 +00002654 u32 rx_jmb_prod_idx;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00002655 u32 rx_jmb_cons_idx;
Matt Carlson21f581a2009-08-28 14:00:25 +00002656 struct tg3_rx_buffer_desc *rx_std;
Matt Carlson79ed5ac2009-08-28 14:00:55 +00002657 struct tg3_ext_rx_buffer_desc *rx_jmb;
Matt Carlson21f581a2009-08-28 14:00:25 +00002658 struct ring_info *rx_std_buffers;
2659 struct ring_info *rx_jmb_buffers;
2660 dma_addr_t rx_std_mapping;
2661 dma_addr_t rx_jmb_mapping;
2662};
2663
Matt Carlsonf6eb9b12009-09-01 13:19:53 +00002664#define TG3_IRQ_MAX_VECS 5
Matt Carlson8ef04422009-08-28 14:01:37 +00002665
2666struct tg3_napi {
2667 struct napi_struct napi ____cacheline_aligned;
2668 struct tg3 *tp;
Matt Carlson898a56f2009-08-28 14:02:40 +00002669 struct tg3_hw_status *hw_status;
2670
2671 u32 last_tag;
2672 u32 last_irq_tag;
2673 u32 int_mbox;
Matt Carlsonfd2ce372009-09-01 12:51:13 +00002674 u32 coal_now;
Matt Carlsonf3f3f272009-08-28 14:03:21 +00002675 u32 tx_prod;
2676 u32 tx_cons;
2677 u32 tx_pending;
2678 u32 prodmbox;
2679
Matt Carlson72334482009-08-28 14:03:01 +00002680 u32 consmbox;
2681 u32 rx_rcb_ptr;
Matt Carlson8d9d7cf2009-09-01 13:19:05 +00002682 u16 *rx_rcb_prod_idx;
Matt Carlsonb196c7e2009-11-13 13:03:50 +00002683 struct tg3_rx_prodring_set *prodring;
Matt Carlson72334482009-08-28 14:03:01 +00002684
2685 struct tg3_rx_buffer_desc *rx_rcb;
Matt Carlsonf3f3f272009-08-28 14:03:21 +00002686 struct tg3_tx_buffer_desc *tx_ring;
Alexander Duyckf4188d82009-12-02 16:48:38 +00002687 struct ring_info *tx_buffers;
Matt Carlson898a56f2009-08-28 14:02:40 +00002688
2689 dma_addr_t status_mapping;
Matt Carlson72334482009-08-28 14:03:01 +00002690 dma_addr_t rx_rcb_mapping;
Matt Carlsonf3f3f272009-08-28 14:03:21 +00002691 dma_addr_t tx_desc_mapping;
Matt Carlson4f125f42009-09-01 12:55:02 +00002692
2693 char irq_lbl[IFNAMSIZ];
2694 unsigned int irq_vec;
Matt Carlson8ef04422009-08-28 14:01:37 +00002695};
2696
Linus Torvalds1da177e2005-04-16 15:20:36 -07002697struct tg3 {
2698 /* begin "general, frequently-used members" cacheline section */
2699
David S. Millerf47c11e2005-06-24 20:18:35 -07002700 /* If the IRQ handler (which runs lockless) needs to be
2701 * quiesced, the following bitmask state is used. The
2702 * SYNC flag is set by non-IRQ context code to initiate
2703 * the quiescence.
2704 *
2705 * When the IRQ handler notices that SYNC is set, it
2706 * disables interrupts and returns.
2707 *
2708 * When all outstanding IRQ handlers have returned after
2709 * the SYNC flag has been set, the setter can be assured
2710 * that interrupts will no longer get run.
2711 *
2712 * In this way all SMP driver locks are never acquired
2713 * in hw IRQ context, only sw IRQ context or lower.
2714 */
2715 unsigned int irq_sync;
2716
Linus Torvalds1da177e2005-04-16 15:20:36 -07002717 /* SMP locking strategy:
2718 *
Michael Chan00b70502006-06-17 21:58:45 -07002719 * lock: Held during reset, PHY access, timer, and when
2720 * updating tg3_flags and tg3_flags2.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002721 *
Michael Chan1b2a7202006-08-07 21:46:02 -07002722 * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
2723 * netif_tx_lock when it needs to call
2724 * netif_wake_queue.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002725 *
David S. Millerf47c11e2005-06-24 20:18:35 -07002726 * Both of these locks are to be held with BH safety.
Michael Chan00b70502006-06-17 21:58:45 -07002727 *
2728 * Because the IRQ handler, tg3_poll, and tg3_start_xmit
2729 * are running lockless, it is necessary to completely
2730 * quiesce the chip with tg3_netif_stop and tg3_full_lock
2731 * before reconfiguring the device.
2732 *
2733 * indirect_lock: Held when accessing registers indirectly
2734 * with IRQ disabling.
Linus Torvalds1da177e2005-04-16 15:20:36 -07002735 */
2736 spinlock_t lock;
2737 spinlock_t indirect_lock;
2738
Michael Chan20094932005-08-09 20:16:32 -07002739 u32 (*read32) (struct tg3 *, u32);
2740 void (*write32) (struct tg3 *, u32, u32);
Michael Chan09ee9292005-08-09 20:17:00 -07002741 u32 (*read32_mbox) (struct tg3 *, u32);
Michael Chan20094932005-08-09 20:16:32 -07002742 void (*write32_mbox) (struct tg3 *, u32,
2743 u32);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002744 void __iomem *regs;
Matt Carlson0d3031d2007-10-10 18:02:43 -07002745 void __iomem *aperegs;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002746 struct net_device *dev;
2747 struct pci_dev *pdev;
2748
Matt Carlsonf89f38b2010-02-12 14:47:07 +00002749 u32 coal_now;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002750 u32 msg_enable;
2751
2752 /* begin "tx thread" cacheline section */
Michael Chan20094932005-08-09 20:16:32 -07002753 void (*write32_tx_mbox) (struct tg3 *, u32,
2754 u32);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002755
2756 /* begin "rx thread" cacheline section */
Matt Carlson8ef04422009-08-28 14:01:37 +00002757 struct tg3_napi napi[TG3_IRQ_MAX_VECS];
Michael Chan20094932005-08-09 20:16:32 -07002758 void (*write32_rx_mbox) (struct tg3 *, u32,
2759 u32);
Matt Carlsond2757fc2010-04-12 06:58:27 +00002760 u32 rx_copy_thresh;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002761 u32 rx_pending;
2762 u32 rx_jumbo_pending;
Matt Carlson21f581a2009-08-28 14:00:25 +00002763 u32 rx_std_max_post;
Matt Carlsond2757fc2010-04-12 06:58:27 +00002764 u32 rx_offset;
Matt Carlson21f581a2009-08-28 14:00:25 +00002765 u32 rx_pkt_map_sz;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002766#if TG3_VLAN_TAG_USED
2767 struct vlan_group *vlgrp;
2768#endif
2769
Matt Carlsone4af1af2010-02-12 14:47:05 +00002770 struct tg3_rx_prodring_set prodring[TG3_IRQ_MAX_VECS];
Matt Carlson21f581a2009-08-28 14:00:25 +00002771
Michael Chan7e72aad2005-07-25 12:31:17 -07002772
Linus Torvalds1da177e2005-04-16 15:20:36 -07002773 /* begin "everything else" cacheline(s) section */
2774 struct net_device_stats net_stats;
2775 struct net_device_stats net_stats_prev;
2776 struct tg3_ethtool_stats estats;
2777 struct tg3_ethtool_stats estats_prev;
2778
Matt Carlson4ba526c2008-08-15 14:10:04 -07002779 union {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002780 unsigned long phy_crc_errors;
Matt Carlson4ba526c2008-08-15 14:10:04 -07002781 unsigned long last_event_jiffies;
2782 };
Linus Torvalds1da177e2005-04-16 15:20:36 -07002783
Linus Torvalds1da177e2005-04-16 15:20:36 -07002784 u32 tg3_flags;
David S. Millerfac9b832005-05-18 22:46:34 -07002785#define TG3_FLAG_TAGGED_STATUS 0x00000001
Linus Torvalds1da177e2005-04-16 15:20:36 -07002786#define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002
2787#define TG3_FLAG_RX_CHECKSUMS 0x00000004
2788#define TG3_FLAG_USE_LINKCHG_REG 0x00000008
2789#define TG3_FLAG_USE_MI_INTERRUPT 0x00000010
2790#define TG3_FLAG_ENABLE_ASF 0x00000020
Matt Carlson8ed5d972007-05-07 00:25:49 -07002791#define TG3_FLAG_ASPM_WORKAROUND 0x00000040
Linus Torvalds1da177e2005-04-16 15:20:36 -07002792#define TG3_FLAG_POLL_SERDES 0x00000080
Linus Torvalds1da177e2005-04-16 15:20:36 -07002793#define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
Linus Torvalds1da177e2005-04-16 15:20:36 -07002794#define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
2795#define TG3_FLAG_WOL_SPEED_100MB 0x00000400
2796#define TG3_FLAG_WOL_ENABLE 0x00000800
2797#define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000
2798#define TG3_FLAG_NVRAM 0x00002000
2799#define TG3_FLAG_NVRAM_BUFFERED 0x00004000
Matt Carlson8f666b02009-08-28 13:58:24 +00002800#define TG3_FLAG_SUPPORT_MSI 0x00008000
Matt Carlson679563f2009-09-01 12:55:46 +00002801#define TG3_FLAG_SUPPORT_MSIX 0x00010000
2802#define TG3_FLAG_SUPPORT_MSI_OR_MSIX (TG3_FLAG_SUPPORT_MSI | \
2803 TG3_FLAG_SUPPORT_MSIX)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002804#define TG3_FLAG_PCIX_MODE 0x00020000
2805#define TG3_FLAG_PCI_HIGH_SPEED 0x00040000
2806#define TG3_FLAG_PCI_32BIT 0x00080000
Michael Chanbbadf502006-04-06 21:46:34 -07002807#define TG3_FLAG_SRAM_USE_CONFIG 0x00100000
Michael Chandf3e6542006-05-26 17:48:07 -07002808#define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000
Gary Zambranoa85feb82007-05-05 11:52:19 -07002809#define TG3_FLAG_WOL_CAP 0x00400000
Michael Chan0f893dc2005-07-25 12:30:38 -07002810#define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002811#define TG3_FLAG_10_100_ONLY 0x01000000
2812#define TG3_FLAG_PAUSE_AUTONEG 0x02000000
Matt Carlson795d01c2007-10-07 23:28:17 -07002813#define TG3_FLAG_CPMU_PRESENT 0x04000000
Michael Chan4a29cc22006-03-19 13:21:12 -08002814#define TG3_FLAG_40BIT_DMA_BUG 0x08000000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002815#define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000
Matt Carlson8f666b02009-08-28 13:58:24 +00002816#define TG3_FLAG_JUMBO_CAPABLE 0x20000000
Michael Chand18edcb2007-03-24 20:57:11 -07002817#define TG3_FLAG_CHIP_RESETTING 0x40000000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002818#define TG3_FLAG_INIT_COMPLETE 0x80000000
2819 u32 tg3_flags2;
2820#define TG3_FLG2_RESTART_TIMER 0x00000001
Michael Chan7f62ad52007-02-20 23:25:40 -08002821#define TG3_FLG2_TSO_BUG 0x00000002
Linus Torvalds1da177e2005-04-16 15:20:36 -07002822#define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004
2823#define TG3_FLG2_IS_5788 0x00000008
2824#define TG3_FLG2_MAX_RXPEND_64 0x00000010
2825#define TG3_FLG2_TSO_CAPABLE 0x00000020
2826#define TG3_FLG2_PHY_ADC_BUG 0x00000040
2827#define TG3_FLG2_PHY_5704_A0_BUG 0x00000080
2828#define TG3_FLG2_PHY_BER_BUG 0x00000100
2829#define TG3_FLG2_PCI_EXPRESS 0x00000200
2830#define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400
2831#define TG3_FLG2_HW_AUTONEG 0x00000800
Michael Chan9d26e212006-12-07 00:21:14 -08002832#define TG3_FLG2_IS_NIC 0x00001000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002833#define TG3_FLG2_PHY_SERDES 0x00002000
2834#define TG3_FLG2_CAPACITIVE_COUPLING 0x00004000
2835#define TG3_FLG2_FLASH 0x00008000
Michael Chan5a6f3072006-03-20 22:28:05 -08002836#define TG3_FLG2_HW_TSO_1 0x00010000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002837#define TG3_FLG2_SERDES_PREEMPHASIS 0x00020000
2838#define TG3_FLG2_5705_PLUS 0x00040000
John W. Linville6708e5c2005-04-21 17:00:52 -07002839#define TG3_FLG2_5750_PLUS 0x00080000
Matt Carlsone849cdc2009-11-13 13:03:38 +00002840#define TG3_FLG2_HW_TSO_3 0x00100000
Michael Chan88b06bc22005-04-21 17:13:25 -07002841#define TG3_FLG2_USING_MSI 0x00200000
Matt Carlson679563f2009-09-01 12:55:46 +00002842#define TG3_FLG2_USING_MSIX 0x00400000
2843#define TG3_FLG2_USING_MSI_OR_MSIX (TG3_FLG2_USING_MSI | \
2844 TG3_FLG2_USING_MSIX)
Michael Chan747e8f82005-07-25 12:33:22 -07002845#define TG3_FLG2_MII_SERDES 0x00800000
2846#define TG3_FLG2_ANY_SERDES (TG3_FLG2_PHY_SERDES | \
2847 TG3_FLG2_MII_SERDES)
2848#define TG3_FLG2_PARALLEL_DETECT 0x01000000
Michael Chan68929142005-08-09 20:17:14 -07002849#define TG3_FLG2_ICH_WORKAROUND 0x02000000
Michael Chana4e2b342005-10-26 15:46:52 -07002850#define TG3_FLG2_5780_CLASS 0x04000000
Michael Chan5a6f3072006-03-20 22:28:05 -08002851#define TG3_FLG2_HW_TSO_2 0x08000000
Matt Carlsone849cdc2009-11-13 13:03:38 +00002852#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | \
2853 TG3_FLG2_HW_TSO_2 | \
2854 TG3_FLG2_HW_TSO_3)
Michael Chanfcfa0a32006-03-20 22:28:41 -08002855#define TG3_FLG2_1SHOT_MSI 0x10000000
Michael Chanc424cb22006-04-29 18:56:34 -07002856#define TG3_FLG2_PHY_JITTER_BUG 0x20000000
David S. Millerf49639e2006-06-09 11:58:36 -07002857#define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
Michael Chanc1d2a192007-01-08 19:57:20 -08002858#define TG3_FLG2_PHY_ADJUST_TRIM 0x80000000
Matt Carlson6b91fa02007-10-10 18:01:09 -07002859 u32 tg3_flags3;
2860#define TG3_FLG3_NO_NVRAM_ADDR_TRANS 0x00000001
Matt Carlson0d3031d2007-10-10 18:02:43 -07002861#define TG3_FLG3_ENABLE_APE 0x00000002
Matt Carlsonf66a29b2009-11-13 13:03:36 +00002862#define TG3_FLG3_PROTECTED_NVRAM 0x00000004
Matt Carlson41588ba2008-04-19 18:12:33 -07002863#define TG3_FLG3_5701_DMA_BUG 0x00000008
Matt Carlsondd477002008-05-25 23:45:58 -07002864#define TG3_FLG3_USE_PHYLIB 0x00000010
Matt Carlson158d7ab2008-05-29 01:37:54 -07002865#define TG3_FLG3_MDIOBUS_INITED 0x00000020
Matt Carlsonb02fd9e2008-05-25 23:47:41 -07002866#define TG3_FLG3_PHY_CONNECTED 0x00000080
Matt Carlson14417062010-02-17 15:16:59 +00002867#define TG3_FLG3_RGMII_INBAND_DISABLE 0x00000100
Matt Carlsona9daf362008-05-25 23:49:44 -07002868#define TG3_FLG3_RGMII_EXT_IBND_RX_EN 0x00000200
2869#define TG3_FLG3_RGMII_EXT_IBND_TX_EN 0x00000400
Matt Carlson5e7dfd02008-11-21 17:18:16 -08002870#define TG3_FLG3_CLKREQ_BUG 0x00000800
Matt Carlson6833c042008-11-21 17:18:59 -08002871#define TG3_FLG3_PHY_ENABLE_APD 0x00001000
Matt Carlson321d32a2008-11-21 17:22:19 -08002872#define TG3_FLG3_5755_PLUS 0x00002000
Matt Carlsondf259d82009-04-20 06:57:14 +00002873#define TG3_FLG3_NO_NVRAM 0x00004000
Matt Carlson7f97a4b2009-08-25 10:10:03 +00002874#define TG3_FLG3_PHY_IS_FET 0x00010000
Matt Carlsonbaf8a942009-09-01 13:13:00 +00002875#define TG3_FLG3_ENABLE_RSS 0x00020000
Matt Carlson19cfaec2009-12-03 08:36:20 +00002876#define TG3_FLG3_ENABLE_TSS 0x00040000
Matt Carlson0e1406d2009-11-02 12:33:33 +00002877#define TG3_FLG3_4G_DMA_BNDRY_BUG 0x00080000
2878#define TG3_FLG3_40BIT_DMA_LIMIT_BUG 0x00100000
Matt Carlson92c6b8d2009-11-02 14:23:27 +00002879#define TG3_FLG3_SHORT_DMA_BUG 0x00200000
Matt Carlsonb703df62009-12-03 08:36:21 +00002880#define TG3_FLG3_USE_JUMBO_BDFLAG 0x00400000
Matt Carlson614b0592010-01-20 16:58:02 +00002881#define TG3_FLG3_L1PLLPD_EN 0x00800000
Linus Torvalds1da177e2005-04-16 15:20:36 -07002882
Linus Torvalds1da177e2005-04-16 15:20:36 -07002883 struct timer_list timer;
2884 u16 timer_counter;
2885 u16 timer_multiplier;
2886 u32 timer_offset;
2887 u16 asf_counter;
2888 u16 asf_multiplier;
2889
Michael Chan3d3ebe72006-09-27 15:59:15 -07002890 /* 1 second counter for transient serdes link events */
2891 u32 serdes_counter;
2892#define SERDES_AN_TIMEOUT_5704S 2
2893#define SERDES_PARALLEL_DET_TIMEOUT 1
2894#define SERDES_AN_TIMEOUT_5714S 1
2895
Linus Torvalds1da177e2005-04-16 15:20:36 -07002896 struct tg3_link_config link_config;
2897 struct tg3_bufmgr_config bufmgr_config;
2898
2899 /* cache h/w values, often passed straight to h/w */
2900 u32 rx_mode;
2901 u32 tx_mode;
2902 u32 mac_mode;
2903 u32 mi_mode;
2904 u32 misc_host_ctrl;
2905 u32 grc_mode;
2906 u32 grc_local_ctrl;
2907 u32 dma_rwctrl;
2908 u32 coalesce_mode;
Matt Carlson8ed5d972007-05-07 00:25:49 -07002909 u32 pwrmgmt_thresh;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002910
2911 /* PCI block */
Matt Carlson795d01c2007-10-07 23:28:17 -07002912 u32 pci_chip_rev_id;
Matt Carlson69fc4052008-12-21 20:19:57 -08002913 u16 pci_cmd;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002914 u8 pci_cacheline_sz;
2915 u8 pci_lat_timer;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002916
2917 int pm_cap;
Michael Chan4cf78e42005-07-25 12:29:19 -07002918 int msi_cap;
Matt Carlson5e7dfd02008-11-21 17:18:16 -08002919 union {
Matt Carlson9974a352007-10-07 23:27:28 -07002920 int pcix_cap;
Matt Carlson5e7dfd02008-11-21 17:18:16 -08002921 int pcie_cap;
2922 };
Linus Torvalds1da177e2005-04-16 15:20:36 -07002923
Lennert Buytenhek298cf9be2008-10-08 16:29:57 -07002924 struct mii_bus *mdio_bus;
Matt Carlson158d7ab2008-05-29 01:37:54 -07002925 int mdio_irq[PHY_MAX_ADDR];
2926
Matt Carlson882e9792009-09-01 13:21:36 +00002927 u8 phy_addr;
2928
Linus Torvalds1da177e2005-04-16 15:20:36 -07002929 /* PHY info */
2930 u32 phy_id;
Matt Carlson79eb6902010-02-17 15:17:03 +00002931#define TG3_PHY_ID_MASK 0xfffffff0
2932#define TG3_PHY_ID_BCM5400 0x60008040
2933#define TG3_PHY_ID_BCM5401 0x60008050
2934#define TG3_PHY_ID_BCM5411 0x60008070
2935#define TG3_PHY_ID_BCM5701 0x60008110
2936#define TG3_PHY_ID_BCM5703 0x60008160
2937#define TG3_PHY_ID_BCM5704 0x60008190
2938#define TG3_PHY_ID_BCM5705 0x600081a0
2939#define TG3_PHY_ID_BCM5750 0x60008180
2940#define TG3_PHY_ID_BCM5752 0x60008100
2941#define TG3_PHY_ID_BCM5714 0x60008340
2942#define TG3_PHY_ID_BCM5780 0x60008350
2943#define TG3_PHY_ID_BCM5755 0xbc050cc0
2944#define TG3_PHY_ID_BCM5787 0xbc050ce0
2945#define TG3_PHY_ID_BCM5756 0xbc050ed0
2946#define TG3_PHY_ID_BCM5784 0xbc050fa0
2947#define TG3_PHY_ID_BCM5761 0xbc050fd0
2948#define TG3_PHY_ID_BCM5718C 0x5c0d8a00
2949#define TG3_PHY_ID_BCM5718S 0xbc050ff0
2950#define TG3_PHY_ID_BCM57765 0x5c0d8a40
2951#define TG3_PHY_ID_BCM5906 0xdc00ac40
2952#define TG3_PHY_ID_BCM8002 0x60010140
Matt Carlson79eb6902010-02-17 15:17:03 +00002953#define TG3_PHY_ID_INVALID 0xffffffff
2954
Matt Carlson6a443a02010-02-17 15:17:04 +00002955#define PHY_ID_RTL8211C 0x001cc910
2956#define PHY_ID_RTL8201E 0x00008200
2957
Matt Carlson79eb6902010-02-17 15:17:03 +00002958#define TG3_PHY_ID_REV_MASK 0x0000000f
2959#define TG3_PHY_REV_BCM5401_B0 0x1
2960
Matt Carlson79eb6902010-02-17 15:17:03 +00002961 /* This macro assumes the passed PHY ID is
2962 * already masked with TG3_PHY_ID_MASK.
2963 */
2964#define TG3_KNOWN_PHY_ID(X) \
2965 ((X) == TG3_PHY_ID_BCM5400 || (X) == TG3_PHY_ID_BCM5401 || \
2966 (X) == TG3_PHY_ID_BCM5411 || (X) == TG3_PHY_ID_BCM5701 || \
2967 (X) == TG3_PHY_ID_BCM5703 || (X) == TG3_PHY_ID_BCM5704 || \
2968 (X) == TG3_PHY_ID_BCM5705 || (X) == TG3_PHY_ID_BCM5750 || \
2969 (X) == TG3_PHY_ID_BCM5752 || (X) == TG3_PHY_ID_BCM5714 || \
2970 (X) == TG3_PHY_ID_BCM5780 || (X) == TG3_PHY_ID_BCM5787 || \
2971 (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \
2972 (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
2973 (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
2974 (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM8002)
2975
Linus Torvalds1da177e2005-04-16 15:20:36 -07002976 u32 led_ctrl;
Matt Carlsonb2a5c192008-04-03 21:44:44 -07002977 u32 phy_otp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002978
Matt Carlson141518c2009-12-03 08:36:22 +00002979#define TG3_BPN_SIZE 24
2980 char board_part_number[TG3_BPN_SIZE];
2981#define TG3_VER_SIZE ETHTOOL_FWVERS_LEN
Matt Carlson9c8a6202007-10-21 16:16:08 -07002982 char fw_ver[TG3_VER_SIZE];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002983 u32 nic_sram_data_cfg;
2984 u32 pci_clock_ctrl;
2985 struct pci_dev *pdev_peer;
2986
Linus Torvalds1da177e2005-04-16 15:20:36 -07002987 struct tg3_hw_stats *hw_stats;
2988 dma_addr_t stats_mapping;
2989 struct work_struct reset_task;
2990
Michael Chanec41c7d2006-01-17 02:40:55 -08002991 int nvram_lock_cnt;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002992 u32 nvram_size;
Matt Carlsonfd1122a2008-05-02 16:48:36 -07002993#define TG3_NVRAM_SIZE_64KB 0x00010000
2994#define TG3_NVRAM_SIZE_128KB 0x00020000
2995#define TG3_NVRAM_SIZE_256KB 0x00040000
2996#define TG3_NVRAM_SIZE_512KB 0x00080000
2997#define TG3_NVRAM_SIZE_1MB 0x00100000
2998#define TG3_NVRAM_SIZE_2MB 0x00200000
2999
Linus Torvalds1da177e2005-04-16 15:20:36 -07003000 u32 nvram_pagesize;
3001 u32 nvram_jedecnum;
3002
3003#define JEDEC_ATMEL 0x1f
3004#define JEDEC_ST 0x20
3005#define JEDEC_SAIFUN 0x4f
3006#define JEDEC_SST 0xbf
3007
Matt Carlsonfd1122a2008-05-02 16:48:36 -07003008#define ATMEL_AT24C64_CHIP_SIZE TG3_NVRAM_SIZE_64KB
Linus Torvalds1da177e2005-04-16 15:20:36 -07003009#define ATMEL_AT24C64_PAGE_SIZE (32)
3010
Matt Carlsonfd1122a2008-05-02 16:48:36 -07003011#define ATMEL_AT24C512_CHIP_SIZE TG3_NVRAM_SIZE_512KB
Linus Torvalds1da177e2005-04-16 15:20:36 -07003012#define ATMEL_AT24C512_PAGE_SIZE (128)
3013
3014#define ATMEL_AT45DB0X1B_PAGE_POS 9
3015#define ATMEL_AT45DB0X1B_PAGE_SIZE 264
3016
3017#define ATMEL_AT25F512_PAGE_SIZE 256
3018
3019#define ST_M45PEX0_PAGE_SIZE 256
3020
3021#define SAIFUN_SA25F0XX_PAGE_SIZE 256
3022
3023#define SST_25VF0X0_PAGE_SIZE 4098
3024
Matt Carlson4f125f42009-09-01 12:55:02 +00003025 unsigned int irq_max;
3026 unsigned int irq_cnt;
3027
David S. Miller15f98502005-05-18 22:49:26 -07003028 struct ethtool_coalesce coal;
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08003029
3030 /* firmware info */
Matt Carlson9e9fd122009-01-19 16:57:45 -08003031 const char *fw_needed;
Jaswinder Singh Rajput077f8492009-01-04 16:11:25 -08003032 const struct firmware *fw;
3033 u32 fw_len; /* includes BSS */
Linus Torvalds1da177e2005-04-16 15:20:36 -07003034};
3035
3036#endif /* !(_T3_H) */