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Michael Chanb6016b72005-05-26 13:03:09 -07001/* bnx2.c: Broadcom NX2 network driver.
2 *
Michael Chanfeebb332008-01-21 17:07:29 -08003 * Copyright (c) 2004-2008 Broadcom Corporation
Michael Chanb6016b72005-05-26 13:03:09 -07004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
Michael Chanf2a4f052006-03-23 01:13:12 -080012
13#include <linux/module.h>
14#include <linux/moduleparam.h>
15
16#include <linux/kernel.h>
17#include <linux/timer.h>
18#include <linux/errno.h>
19#include <linux/ioport.h>
20#include <linux/slab.h>
21#include <linux/vmalloc.h>
22#include <linux/interrupt.h>
23#include <linux/pci.h>
24#include <linux/init.h>
25#include <linux/netdevice.h>
26#include <linux/etherdevice.h>
27#include <linux/skbuff.h>
28#include <linux/dma-mapping.h>
Jiri Slaby1977f032007-10-18 23:40:25 -070029#include <linux/bitops.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080030#include <asm/io.h>
31#include <asm/irq.h>
32#include <linux/delay.h>
33#include <asm/byteorder.h>
Michael Chanc86a31f2006-06-13 15:03:47 -070034#include <asm/page.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080035#include <linux/time.h>
36#include <linux/ethtool.h>
37#include <linux/mii.h>
38#ifdef NETIF_F_HW_VLAN_TX
39#include <linux/if_vlan.h>
40#define BCM_VLAN 1
41#endif
Michael Chanf2a4f052006-03-23 01:13:12 -080042#include <net/ip.h>
Linus Torvaldsde081fa2007-07-12 16:40:08 -070043#include <net/tcp.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080044#include <net/checksum.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080045#include <linux/workqueue.h>
46#include <linux/crc32.h>
47#include <linux/prefetch.h>
Michael Chan29b12172006-03-23 01:13:43 -080048#include <linux/cache.h>
Michael Chanfba9fe92006-06-12 22:21:25 -070049#include <linux/zlib.h>
Michael Chanf2a4f052006-03-23 01:13:12 -080050
Michael Chanb6016b72005-05-26 13:03:09 -070051#include "bnx2.h"
52#include "bnx2_fw.h"
Michael Chand43584c2006-11-19 14:14:35 -080053#include "bnx2_fw2.h"
Michael Chanb6016b72005-05-26 13:03:09 -070054
Michael Chan110d0ef2007-12-12 11:18:34 -080055#define FW_BUF_SIZE 0x10000
Denys Vlasenkob3448b02007-09-30 17:55:51 -070056
Michael Chanb6016b72005-05-26 13:03:09 -070057#define DRV_MODULE_NAME "bnx2"
58#define PFX DRV_MODULE_NAME ": "
Michael Chan18c02262008-01-29 21:38:52 -080059#define DRV_MODULE_VERSION "1.7.3"
60#define DRV_MODULE_RELDATE "January 29, 2008"
Michael Chanb6016b72005-05-26 13:03:09 -070061
62#define RUN_AT(x) (jiffies + (x))
63
64/* Time in jiffies before concluding the transmitter is hung. */
65#define TX_TIMEOUT (5*HZ)
66
Andrew Mortonfefa8642008-02-09 23:17:15 -080067static char version[] __devinitdata =
Michael Chanb6016b72005-05-26 13:03:09 -070068 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
69
70MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
Michael Chan05d0f1c2005-11-04 08:53:48 -080071MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
Michael Chanb6016b72005-05-26 13:03:09 -070072MODULE_LICENSE("GPL");
73MODULE_VERSION(DRV_MODULE_VERSION);
74
75static int disable_msi = 0;
76
77module_param(disable_msi, int, 0);
78MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
79
80typedef enum {
81 BCM5706 = 0,
82 NC370T,
83 NC370I,
84 BCM5706S,
85 NC370F,
Michael Chan5b0c76a2005-11-04 08:45:49 -080086 BCM5708,
87 BCM5708S,
Michael Chanbac0dff2006-11-19 14:15:05 -080088 BCM5709,
Michael Chan27a005b2007-05-03 13:23:41 -070089 BCM5709S,
Michael Chanb6016b72005-05-26 13:03:09 -070090} board_t;
91
92/* indexed by board_t, above */
Andrew Mortonfefa8642008-02-09 23:17:15 -080093static struct {
Michael Chanb6016b72005-05-26 13:03:09 -070094 char *name;
95} board_info[] __devinitdata = {
96 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
97 { "HP NC370T Multifunction Gigabit Server Adapter" },
98 { "HP NC370i Multifunction Gigabit Server Adapter" },
99 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
100 { "HP NC370F Multifunction Gigabit Server Adapter" },
Michael Chan5b0c76a2005-11-04 08:45:49 -0800101 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
102 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
Michael Chanbac0dff2006-11-19 14:15:05 -0800103 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
Michael Chan27a005b2007-05-03 13:23:41 -0700104 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
Michael Chanb6016b72005-05-26 13:03:09 -0700105 };
106
107static struct pci_device_id bnx2_pci_tbl[] = {
108 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
109 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
110 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
111 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
112 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
Michael Chan5b0c76a2005-11-04 08:45:49 -0800114 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
Michael Chanb6016b72005-05-26 13:03:09 -0700116 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
117 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
118 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
Michael Chan5b0c76a2005-11-04 08:45:49 -0800120 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
Michael Chanbac0dff2006-11-19 14:15:05 -0800122 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
Michael Chan27a005b2007-05-03 13:23:41 -0700124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
Michael Chanb6016b72005-05-26 13:03:09 -0700126 { 0, }
127};
128
129static struct flash_spec flash_table[] =
130{
Michael Chane30372c2007-07-16 18:26:23 -0700131#define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
132#define NONBUFFERED_FLAGS (BNX2_NV_WREN)
Michael Chanb6016b72005-05-26 13:03:09 -0700133 /* Slow EEPROM */
Michael Chan37137702005-11-04 08:49:17 -0800134 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700135 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
Michael Chanb6016b72005-05-26 13:03:09 -0700136 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
137 "EEPROM - slow"},
Michael Chan37137702005-11-04 08:49:17 -0800138 /* Expansion entry 0001 */
139 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700140 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800141 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
142 "Entry 0001"},
Michael Chanb6016b72005-05-26 13:03:09 -0700143 /* Saifun SA25F010 (non-buffered flash) */
144 /* strap, cfg1, & write1 need updates */
Michael Chan37137702005-11-04 08:49:17 -0800145 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700146 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chanb6016b72005-05-26 13:03:09 -0700147 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
148 "Non-buffered flash (128kB)"},
149 /* Saifun SA25F020 (non-buffered flash) */
150 /* strap, cfg1, & write1 need updates */
Michael Chan37137702005-11-04 08:49:17 -0800151 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700152 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chanb6016b72005-05-26 13:03:09 -0700153 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
154 "Non-buffered flash (256kB)"},
Michael Chan37137702005-11-04 08:49:17 -0800155 /* Expansion entry 0100 */
156 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700157 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800158 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
159 "Entry 0100"},
160 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400161 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700162 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800163 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
164 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
165 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
166 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700167 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800168 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
169 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
170 /* Saifun SA25F005 (non-buffered flash) */
171 /* strap, cfg1, & write1 need updates */
172 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700173 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800174 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
175 "Non-buffered flash (64kB)"},
176 /* Fast EEPROM */
177 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700178 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800179 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
180 "EEPROM - fast"},
181 /* Expansion entry 1001 */
182 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700183 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800184 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
185 "Entry 1001"},
186 /* Expansion entry 1010 */
187 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800189 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
190 "Entry 1010"},
191 /* ATMEL AT45DB011B (buffered flash) */
192 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700193 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800194 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
195 "Buffered flash (128kB)"},
196 /* Expansion entry 1100 */
197 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700198 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800199 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
200 "Entry 1100"},
201 /* Expansion entry 1101 */
202 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
Michael Chane30372c2007-07-16 18:26:23 -0700203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
205 "Entry 1101"},
206 /* Ateml Expansion entry 1110 */
207 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700208 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800209 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
210 "Entry 1110 (Atmel)"},
211 /* ATMEL AT45DB021B (buffered flash) */
212 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
Michael Chane30372c2007-07-16 18:26:23 -0700213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
Michael Chan37137702005-11-04 08:49:17 -0800214 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
215 "Buffered flash (256kB)"},
Michael Chanb6016b72005-05-26 13:03:09 -0700216};
217
Michael Chane30372c2007-07-16 18:26:23 -0700218static struct flash_spec flash_5709 = {
219 .flags = BNX2_NV_BUFFERED,
220 .page_bits = BCM5709_FLASH_PAGE_BITS,
221 .page_size = BCM5709_FLASH_PAGE_SIZE,
222 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
223 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
224 .name = "5709 Buffered flash (256kB)",
225};
226
Michael Chanb6016b72005-05-26 13:03:09 -0700227MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
228
Michael Chana550c992007-12-20 19:56:59 -0800229static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_napi *bnapi)
Michael Chane89bbf12005-08-25 15:36:58 -0700230{
Michael Chan2f8af122006-08-15 01:39:10 -0700231 u32 diff;
Michael Chane89bbf12005-08-25 15:36:58 -0700232
Michael Chan2f8af122006-08-15 01:39:10 -0700233 smp_mb();
Michael Chanfaac9c42006-12-14 15:56:32 -0800234
235 /* The ring uses 256 indices for 255 entries, one of them
236 * needs to be skipped.
237 */
Michael Chana550c992007-12-20 19:56:59 -0800238 diff = bp->tx_prod - bnapi->tx_cons;
Michael Chanfaac9c42006-12-14 15:56:32 -0800239 if (unlikely(diff >= TX_DESC_CNT)) {
240 diff &= 0xffff;
241 if (diff == TX_DESC_CNT)
242 diff = MAX_TX_DESC_CNT;
243 }
Michael Chane89bbf12005-08-25 15:36:58 -0700244 return (bp->tx_ring_size - diff);
245}
246
Michael Chanb6016b72005-05-26 13:03:09 -0700247static u32
248bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
249{
Michael Chan1b8227c2007-05-03 13:24:05 -0700250 u32 val;
251
252 spin_lock_bh(&bp->indirect_lock);
Michael Chanb6016b72005-05-26 13:03:09 -0700253 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
Michael Chan1b8227c2007-05-03 13:24:05 -0700254 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
255 spin_unlock_bh(&bp->indirect_lock);
256 return val;
Michael Chanb6016b72005-05-26 13:03:09 -0700257}
258
259static void
260bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
261{
Michael Chan1b8227c2007-05-03 13:24:05 -0700262 spin_lock_bh(&bp->indirect_lock);
Michael Chanb6016b72005-05-26 13:03:09 -0700263 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
264 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
Michael Chan1b8227c2007-05-03 13:24:05 -0700265 spin_unlock_bh(&bp->indirect_lock);
Michael Chanb6016b72005-05-26 13:03:09 -0700266}
267
268static void
Michael Chan2726d6e2008-01-29 21:35:05 -0800269bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
270{
271 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
272}
273
274static u32
275bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
276{
277 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
278}
279
280static void
Michael Chanb6016b72005-05-26 13:03:09 -0700281bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
282{
283 offset += cid_addr;
Michael Chan1b8227c2007-05-03 13:24:05 -0700284 spin_lock_bh(&bp->indirect_lock);
Michael Chan59b47d82006-11-19 14:10:45 -0800285 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
286 int i;
287
288 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
289 REG_WR(bp, BNX2_CTX_CTX_CTRL,
290 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
291 for (i = 0; i < 5; i++) {
292 u32 val;
293 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
294 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
295 break;
296 udelay(5);
297 }
298 } else {
299 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
300 REG_WR(bp, BNX2_CTX_DATA, val);
301 }
Michael Chan1b8227c2007-05-03 13:24:05 -0700302 spin_unlock_bh(&bp->indirect_lock);
Michael Chanb6016b72005-05-26 13:03:09 -0700303}
304
305static int
306bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
307{
308 u32 val1;
309 int i, ret;
310
Michael Chan583c28e2008-01-21 19:51:35 -0800311 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
Michael Chanb6016b72005-05-26 13:03:09 -0700312 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
313 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
314
315 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
316 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
317
318 udelay(40);
319 }
320
321 val1 = (bp->phy_addr << 21) | (reg << 16) |
322 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
323 BNX2_EMAC_MDIO_COMM_START_BUSY;
324 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
325
326 for (i = 0; i < 50; i++) {
327 udelay(10);
328
329 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
330 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
331 udelay(5);
332
333 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
334 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
335
336 break;
337 }
338 }
339
340 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
341 *val = 0x0;
342 ret = -EBUSY;
343 }
344 else {
345 *val = val1;
346 ret = 0;
347 }
348
Michael Chan583c28e2008-01-21 19:51:35 -0800349 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
Michael Chanb6016b72005-05-26 13:03:09 -0700350 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
351 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
352
353 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
354 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
355
356 udelay(40);
357 }
358
359 return ret;
360}
361
362static int
363bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
364{
365 u32 val1;
366 int i, ret;
367
Michael Chan583c28e2008-01-21 19:51:35 -0800368 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
Michael Chanb6016b72005-05-26 13:03:09 -0700369 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
370 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
371
372 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
373 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
374
375 udelay(40);
376 }
377
378 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
379 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
380 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
381 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400382
Michael Chanb6016b72005-05-26 13:03:09 -0700383 for (i = 0; i < 50; i++) {
384 udelay(10);
385
386 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
387 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
388 udelay(5);
389 break;
390 }
391 }
392
393 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
394 ret = -EBUSY;
395 else
396 ret = 0;
397
Michael Chan583c28e2008-01-21 19:51:35 -0800398 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
Michael Chanb6016b72005-05-26 13:03:09 -0700399 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
400 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
401
402 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
403 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
404
405 udelay(40);
406 }
407
408 return ret;
409}
410
411static void
412bnx2_disable_int(struct bnx2 *bp)
413{
Michael Chanb4b36042007-12-20 19:59:30 -0800414 int i;
415 struct bnx2_napi *bnapi;
416
417 for (i = 0; i < bp->irq_nvecs; i++) {
418 bnapi = &bp->bnx2_napi[i];
419 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
420 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
421 }
Michael Chanb6016b72005-05-26 13:03:09 -0700422 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
423}
424
425static void
426bnx2_enable_int(struct bnx2 *bp)
427{
Michael Chanb4b36042007-12-20 19:59:30 -0800428 int i;
429 struct bnx2_napi *bnapi;
Michael Chan1269a8a2006-01-23 16:11:03 -0800430
Michael Chanb4b36042007-12-20 19:59:30 -0800431 for (i = 0; i < bp->irq_nvecs; i++) {
432 bnapi = &bp->bnx2_napi[i];
Michael Chan35efa7c2007-12-20 19:56:37 -0800433
Michael Chanb4b36042007-12-20 19:59:30 -0800434 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
435 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
436 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
437 bnapi->last_status_idx);
Michael Chanb6016b72005-05-26 13:03:09 -0700438
Michael Chanb4b36042007-12-20 19:59:30 -0800439 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
440 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
441 bnapi->last_status_idx);
442 }
Michael Chanbf5295b2006-03-23 01:11:56 -0800443 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
Michael Chanb6016b72005-05-26 13:03:09 -0700444}
445
446static void
447bnx2_disable_int_sync(struct bnx2 *bp)
448{
Michael Chanb4b36042007-12-20 19:59:30 -0800449 int i;
450
Michael Chanb6016b72005-05-26 13:03:09 -0700451 atomic_inc(&bp->intr_sem);
452 bnx2_disable_int(bp);
Michael Chanb4b36042007-12-20 19:59:30 -0800453 for (i = 0; i < bp->irq_nvecs; i++)
454 synchronize_irq(bp->irq_tbl[i].vector);
Michael Chanb6016b72005-05-26 13:03:09 -0700455}
456
457static void
Michael Chan35efa7c2007-12-20 19:56:37 -0800458bnx2_napi_disable(struct bnx2 *bp)
459{
Michael Chanb4b36042007-12-20 19:59:30 -0800460 int i;
461
462 for (i = 0; i < bp->irq_nvecs; i++)
463 napi_disable(&bp->bnx2_napi[i].napi);
Michael Chan35efa7c2007-12-20 19:56:37 -0800464}
465
466static void
467bnx2_napi_enable(struct bnx2 *bp)
468{
Michael Chanb4b36042007-12-20 19:59:30 -0800469 int i;
470
471 for (i = 0; i < bp->irq_nvecs; i++)
472 napi_enable(&bp->bnx2_napi[i].napi);
Michael Chan35efa7c2007-12-20 19:56:37 -0800473}
474
475static void
Michael Chanb6016b72005-05-26 13:03:09 -0700476bnx2_netif_stop(struct bnx2 *bp)
477{
478 bnx2_disable_int_sync(bp);
479 if (netif_running(bp->dev)) {
Michael Chan35efa7c2007-12-20 19:56:37 -0800480 bnx2_napi_disable(bp);
Michael Chanb6016b72005-05-26 13:03:09 -0700481 netif_tx_disable(bp->dev);
482 bp->dev->trans_start = jiffies; /* prevent tx timeout */
483 }
484}
485
486static void
487bnx2_netif_start(struct bnx2 *bp)
488{
489 if (atomic_dec_and_test(&bp->intr_sem)) {
490 if (netif_running(bp->dev)) {
491 netif_wake_queue(bp->dev);
Michael Chan35efa7c2007-12-20 19:56:37 -0800492 bnx2_napi_enable(bp);
Michael Chanb6016b72005-05-26 13:03:09 -0700493 bnx2_enable_int(bp);
494 }
495 }
496}
497
498static void
499bnx2_free_mem(struct bnx2 *bp)
500{
Michael Chan13daffa2006-03-20 17:49:20 -0800501 int i;
502
Michael Chan59b47d82006-11-19 14:10:45 -0800503 for (i = 0; i < bp->ctx_pages; i++) {
504 if (bp->ctx_blk[i]) {
505 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
506 bp->ctx_blk[i],
507 bp->ctx_blk_mapping[i]);
508 bp->ctx_blk[i] = NULL;
509 }
510 }
Michael Chanb6016b72005-05-26 13:03:09 -0700511 if (bp->status_blk) {
Michael Chan0f31f992006-03-23 01:12:38 -0800512 pci_free_consistent(bp->pdev, bp->status_stats_size,
Michael Chanb6016b72005-05-26 13:03:09 -0700513 bp->status_blk, bp->status_blk_mapping);
514 bp->status_blk = NULL;
Michael Chan0f31f992006-03-23 01:12:38 -0800515 bp->stats_blk = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -0700516 }
517 if (bp->tx_desc_ring) {
Michael Chane343d552007-12-12 11:16:19 -0800518 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
Michael Chanb6016b72005-05-26 13:03:09 -0700519 bp->tx_desc_ring, bp->tx_desc_mapping);
520 bp->tx_desc_ring = NULL;
521 }
Jesper Juhlb4558ea2005-10-28 16:53:13 -0400522 kfree(bp->tx_buf_ring);
523 bp->tx_buf_ring = NULL;
Michael Chan13daffa2006-03-20 17:49:20 -0800524 for (i = 0; i < bp->rx_max_ring; i++) {
525 if (bp->rx_desc_ring[i])
Michael Chane343d552007-12-12 11:16:19 -0800526 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
Michael Chan13daffa2006-03-20 17:49:20 -0800527 bp->rx_desc_ring[i],
528 bp->rx_desc_mapping[i]);
529 bp->rx_desc_ring[i] = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -0700530 }
Michael Chan13daffa2006-03-20 17:49:20 -0800531 vfree(bp->rx_buf_ring);
Jesper Juhlb4558ea2005-10-28 16:53:13 -0400532 bp->rx_buf_ring = NULL;
Michael Chan47bf4242007-12-12 11:19:12 -0800533 for (i = 0; i < bp->rx_max_pg_ring; i++) {
534 if (bp->rx_pg_desc_ring[i])
535 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
536 bp->rx_pg_desc_ring[i],
537 bp->rx_pg_desc_mapping[i]);
538 bp->rx_pg_desc_ring[i] = NULL;
539 }
540 if (bp->rx_pg_ring)
541 vfree(bp->rx_pg_ring);
542 bp->rx_pg_ring = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -0700543}
544
545static int
546bnx2_alloc_mem(struct bnx2 *bp)
547{
Michael Chan0f31f992006-03-23 01:12:38 -0800548 int i, status_blk_size;
Michael Chan13daffa2006-03-20 17:49:20 -0800549
Michael Chane343d552007-12-12 11:16:19 -0800550 bp->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
Michael Chanb6016b72005-05-26 13:03:09 -0700551 if (bp->tx_buf_ring == NULL)
552 return -ENOMEM;
553
Michael Chane343d552007-12-12 11:16:19 -0800554 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
Michael Chanb6016b72005-05-26 13:03:09 -0700555 &bp->tx_desc_mapping);
556 if (bp->tx_desc_ring == NULL)
557 goto alloc_mem_err;
558
Michael Chane343d552007-12-12 11:16:19 -0800559 bp->rx_buf_ring = vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
Michael Chanb6016b72005-05-26 13:03:09 -0700560 if (bp->rx_buf_ring == NULL)
561 goto alloc_mem_err;
562
Michael Chane343d552007-12-12 11:16:19 -0800563 memset(bp->rx_buf_ring, 0, SW_RXBD_RING_SIZE * bp->rx_max_ring);
Michael Chan13daffa2006-03-20 17:49:20 -0800564
565 for (i = 0; i < bp->rx_max_ring; i++) {
566 bp->rx_desc_ring[i] =
Michael Chane343d552007-12-12 11:16:19 -0800567 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
Michael Chan13daffa2006-03-20 17:49:20 -0800568 &bp->rx_desc_mapping[i]);
569 if (bp->rx_desc_ring[i] == NULL)
570 goto alloc_mem_err;
571
572 }
Michael Chanb6016b72005-05-26 13:03:09 -0700573
Michael Chan47bf4242007-12-12 11:19:12 -0800574 if (bp->rx_pg_ring_size) {
575 bp->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
576 bp->rx_max_pg_ring);
577 if (bp->rx_pg_ring == NULL)
578 goto alloc_mem_err;
579
580 memset(bp->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
581 bp->rx_max_pg_ring);
582 }
583
584 for (i = 0; i < bp->rx_max_pg_ring; i++) {
585 bp->rx_pg_desc_ring[i] =
586 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
587 &bp->rx_pg_desc_mapping[i]);
588 if (bp->rx_pg_desc_ring[i] == NULL)
589 goto alloc_mem_err;
590
591 }
592
Michael Chan0f31f992006-03-23 01:12:38 -0800593 /* Combine status and statistics blocks into one allocation. */
594 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
David S. Millerf86e82f2008-01-21 17:15:40 -0800595 if (bp->flags & BNX2_FLAG_MSIX_CAP)
Michael Chanb4b36042007-12-20 19:59:30 -0800596 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
597 BNX2_SBLK_MSIX_ALIGN_SIZE);
Michael Chan0f31f992006-03-23 01:12:38 -0800598 bp->status_stats_size = status_blk_size +
599 sizeof(struct statistics_block);
600
601 bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
Michael Chanb6016b72005-05-26 13:03:09 -0700602 &bp->status_blk_mapping);
603 if (bp->status_blk == NULL)
604 goto alloc_mem_err;
605
Michael Chan0f31f992006-03-23 01:12:38 -0800606 memset(bp->status_blk, 0, bp->status_stats_size);
Michael Chanb6016b72005-05-26 13:03:09 -0700607
Michael Chanb4b36042007-12-20 19:59:30 -0800608 bp->bnx2_napi[0].status_blk = bp->status_blk;
David S. Millerf86e82f2008-01-21 17:15:40 -0800609 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
Michael Chanb4b36042007-12-20 19:59:30 -0800610 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
611 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
612
Michael Chan57851d82007-12-20 20:01:44 -0800613 bnapi->status_blk_msix = (void *)
Michael Chanb4b36042007-12-20 19:59:30 -0800614 ((unsigned long) bp->status_blk +
615 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
616 bnapi->int_num = i << 24;
617 }
618 }
Michael Chan35efa7c2007-12-20 19:56:37 -0800619
Michael Chan0f31f992006-03-23 01:12:38 -0800620 bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
621 status_blk_size);
Michael Chanb6016b72005-05-26 13:03:09 -0700622
Michael Chan0f31f992006-03-23 01:12:38 -0800623 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
Michael Chanb6016b72005-05-26 13:03:09 -0700624
Michael Chan59b47d82006-11-19 14:10:45 -0800625 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
626 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
627 if (bp->ctx_pages == 0)
628 bp->ctx_pages = 1;
629 for (i = 0; i < bp->ctx_pages; i++) {
630 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
631 BCM_PAGE_SIZE,
632 &bp->ctx_blk_mapping[i]);
633 if (bp->ctx_blk[i] == NULL)
634 goto alloc_mem_err;
635 }
636 }
Michael Chanb6016b72005-05-26 13:03:09 -0700637 return 0;
638
639alloc_mem_err:
640 bnx2_free_mem(bp);
641 return -ENOMEM;
642}
643
644static void
Michael Chane3648b32005-11-04 08:51:21 -0800645bnx2_report_fw_link(struct bnx2 *bp)
646{
647 u32 fw_link_status = 0;
648
Michael Chan583c28e2008-01-21 19:51:35 -0800649 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -0700650 return;
651
Michael Chane3648b32005-11-04 08:51:21 -0800652 if (bp->link_up) {
653 u32 bmsr;
654
655 switch (bp->line_speed) {
656 case SPEED_10:
657 if (bp->duplex == DUPLEX_HALF)
658 fw_link_status = BNX2_LINK_STATUS_10HALF;
659 else
660 fw_link_status = BNX2_LINK_STATUS_10FULL;
661 break;
662 case SPEED_100:
663 if (bp->duplex == DUPLEX_HALF)
664 fw_link_status = BNX2_LINK_STATUS_100HALF;
665 else
666 fw_link_status = BNX2_LINK_STATUS_100FULL;
667 break;
668 case SPEED_1000:
669 if (bp->duplex == DUPLEX_HALF)
670 fw_link_status = BNX2_LINK_STATUS_1000HALF;
671 else
672 fw_link_status = BNX2_LINK_STATUS_1000FULL;
673 break;
674 case SPEED_2500:
675 if (bp->duplex == DUPLEX_HALF)
676 fw_link_status = BNX2_LINK_STATUS_2500HALF;
677 else
678 fw_link_status = BNX2_LINK_STATUS_2500FULL;
679 break;
680 }
681
682 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
683
684 if (bp->autoneg) {
685 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
686
Michael Chanca58c3a2007-05-03 13:22:52 -0700687 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
688 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
Michael Chane3648b32005-11-04 08:51:21 -0800689
690 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
Michael Chan583c28e2008-01-21 19:51:35 -0800691 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
Michael Chane3648b32005-11-04 08:51:21 -0800692 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
693 else
694 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
695 }
696 }
697 else
698 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
699
Michael Chan2726d6e2008-01-29 21:35:05 -0800700 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
Michael Chane3648b32005-11-04 08:51:21 -0800701}
702
Michael Chan9b1084b2007-07-07 22:50:37 -0700703static char *
704bnx2_xceiver_str(struct bnx2 *bp)
705{
706 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
Michael Chan583c28e2008-01-21 19:51:35 -0800707 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
Michael Chan9b1084b2007-07-07 22:50:37 -0700708 "Copper"));
709}
710
Michael Chane3648b32005-11-04 08:51:21 -0800711static void
Michael Chanb6016b72005-05-26 13:03:09 -0700712bnx2_report_link(struct bnx2 *bp)
713{
714 if (bp->link_up) {
715 netif_carrier_on(bp->dev);
Michael Chan9b1084b2007-07-07 22:50:37 -0700716 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
717 bnx2_xceiver_str(bp));
Michael Chanb6016b72005-05-26 13:03:09 -0700718
719 printk("%d Mbps ", bp->line_speed);
720
721 if (bp->duplex == DUPLEX_FULL)
722 printk("full duplex");
723 else
724 printk("half duplex");
725
726 if (bp->flow_ctrl) {
727 if (bp->flow_ctrl & FLOW_CTRL_RX) {
728 printk(", receive ");
729 if (bp->flow_ctrl & FLOW_CTRL_TX)
730 printk("& transmit ");
731 }
732 else {
733 printk(", transmit ");
734 }
735 printk("flow control ON");
736 }
737 printk("\n");
738 }
739 else {
740 netif_carrier_off(bp->dev);
Michael Chan9b1084b2007-07-07 22:50:37 -0700741 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
742 bnx2_xceiver_str(bp));
Michael Chanb6016b72005-05-26 13:03:09 -0700743 }
Michael Chane3648b32005-11-04 08:51:21 -0800744
745 bnx2_report_fw_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -0700746}
747
748static void
749bnx2_resolve_flow_ctrl(struct bnx2 *bp)
750{
751 u32 local_adv, remote_adv;
752
753 bp->flow_ctrl = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -0400754 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
Michael Chanb6016b72005-05-26 13:03:09 -0700755 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
756
757 if (bp->duplex == DUPLEX_FULL) {
758 bp->flow_ctrl = bp->req_flow_ctrl;
759 }
760 return;
761 }
762
763 if (bp->duplex != DUPLEX_FULL) {
764 return;
765 }
766
Michael Chan583c28e2008-01-21 19:51:35 -0800767 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chan5b0c76a2005-11-04 08:45:49 -0800768 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
769 u32 val;
770
771 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
772 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
773 bp->flow_ctrl |= FLOW_CTRL_TX;
774 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
775 bp->flow_ctrl |= FLOW_CTRL_RX;
776 return;
777 }
778
Michael Chanca58c3a2007-05-03 13:22:52 -0700779 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
780 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
Michael Chanb6016b72005-05-26 13:03:09 -0700781
Michael Chan583c28e2008-01-21 19:51:35 -0800782 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanb6016b72005-05-26 13:03:09 -0700783 u32 new_local_adv = 0;
784 u32 new_remote_adv = 0;
785
786 if (local_adv & ADVERTISE_1000XPAUSE)
787 new_local_adv |= ADVERTISE_PAUSE_CAP;
788 if (local_adv & ADVERTISE_1000XPSE_ASYM)
789 new_local_adv |= ADVERTISE_PAUSE_ASYM;
790 if (remote_adv & ADVERTISE_1000XPAUSE)
791 new_remote_adv |= ADVERTISE_PAUSE_CAP;
792 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
793 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
794
795 local_adv = new_local_adv;
796 remote_adv = new_remote_adv;
797 }
798
799 /* See Table 28B-3 of 802.3ab-1999 spec. */
800 if (local_adv & ADVERTISE_PAUSE_CAP) {
801 if(local_adv & ADVERTISE_PAUSE_ASYM) {
802 if (remote_adv & ADVERTISE_PAUSE_CAP) {
803 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
804 }
805 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
806 bp->flow_ctrl = FLOW_CTRL_RX;
807 }
808 }
809 else {
810 if (remote_adv & ADVERTISE_PAUSE_CAP) {
811 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
812 }
813 }
814 }
815 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
816 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
817 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
818
819 bp->flow_ctrl = FLOW_CTRL_TX;
820 }
821 }
822}
823
824static int
Michael Chan27a005b2007-05-03 13:23:41 -0700825bnx2_5709s_linkup(struct bnx2 *bp)
826{
827 u32 val, speed;
828
829 bp->link_up = 1;
830
831 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
832 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
833 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
834
835 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
836 bp->line_speed = bp->req_line_speed;
837 bp->duplex = bp->req_duplex;
838 return 0;
839 }
840 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
841 switch (speed) {
842 case MII_BNX2_GP_TOP_AN_SPEED_10:
843 bp->line_speed = SPEED_10;
844 break;
845 case MII_BNX2_GP_TOP_AN_SPEED_100:
846 bp->line_speed = SPEED_100;
847 break;
848 case MII_BNX2_GP_TOP_AN_SPEED_1G:
849 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
850 bp->line_speed = SPEED_1000;
851 break;
852 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
853 bp->line_speed = SPEED_2500;
854 break;
855 }
856 if (val & MII_BNX2_GP_TOP_AN_FD)
857 bp->duplex = DUPLEX_FULL;
858 else
859 bp->duplex = DUPLEX_HALF;
860 return 0;
861}
862
863static int
Michael Chan5b0c76a2005-11-04 08:45:49 -0800864bnx2_5708s_linkup(struct bnx2 *bp)
865{
866 u32 val;
867
868 bp->link_up = 1;
869 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
870 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
871 case BCM5708S_1000X_STAT1_SPEED_10:
872 bp->line_speed = SPEED_10;
873 break;
874 case BCM5708S_1000X_STAT1_SPEED_100:
875 bp->line_speed = SPEED_100;
876 break;
877 case BCM5708S_1000X_STAT1_SPEED_1G:
878 bp->line_speed = SPEED_1000;
879 break;
880 case BCM5708S_1000X_STAT1_SPEED_2G5:
881 bp->line_speed = SPEED_2500;
882 break;
883 }
884 if (val & BCM5708S_1000X_STAT1_FD)
885 bp->duplex = DUPLEX_FULL;
886 else
887 bp->duplex = DUPLEX_HALF;
888
889 return 0;
890}
891
892static int
893bnx2_5706s_linkup(struct bnx2 *bp)
Michael Chanb6016b72005-05-26 13:03:09 -0700894{
895 u32 bmcr, local_adv, remote_adv, common;
896
897 bp->link_up = 1;
898 bp->line_speed = SPEED_1000;
899
Michael Chanca58c3a2007-05-03 13:22:52 -0700900 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -0700901 if (bmcr & BMCR_FULLDPLX) {
902 bp->duplex = DUPLEX_FULL;
903 }
904 else {
905 bp->duplex = DUPLEX_HALF;
906 }
907
908 if (!(bmcr & BMCR_ANENABLE)) {
909 return 0;
910 }
911
Michael Chanca58c3a2007-05-03 13:22:52 -0700912 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
913 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
Michael Chanb6016b72005-05-26 13:03:09 -0700914
915 common = local_adv & remote_adv;
916 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
917
918 if (common & ADVERTISE_1000XFULL) {
919 bp->duplex = DUPLEX_FULL;
920 }
921 else {
922 bp->duplex = DUPLEX_HALF;
923 }
924 }
925
926 return 0;
927}
928
929static int
930bnx2_copper_linkup(struct bnx2 *bp)
931{
932 u32 bmcr;
933
Michael Chanca58c3a2007-05-03 13:22:52 -0700934 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -0700935 if (bmcr & BMCR_ANENABLE) {
936 u32 local_adv, remote_adv, common;
937
938 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
939 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
940
941 common = local_adv & (remote_adv >> 2);
942 if (common & ADVERTISE_1000FULL) {
943 bp->line_speed = SPEED_1000;
944 bp->duplex = DUPLEX_FULL;
945 }
946 else if (common & ADVERTISE_1000HALF) {
947 bp->line_speed = SPEED_1000;
948 bp->duplex = DUPLEX_HALF;
949 }
950 else {
Michael Chanca58c3a2007-05-03 13:22:52 -0700951 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
952 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
Michael Chanb6016b72005-05-26 13:03:09 -0700953
954 common = local_adv & remote_adv;
955 if (common & ADVERTISE_100FULL) {
956 bp->line_speed = SPEED_100;
957 bp->duplex = DUPLEX_FULL;
958 }
959 else if (common & ADVERTISE_100HALF) {
960 bp->line_speed = SPEED_100;
961 bp->duplex = DUPLEX_HALF;
962 }
963 else if (common & ADVERTISE_10FULL) {
964 bp->line_speed = SPEED_10;
965 bp->duplex = DUPLEX_FULL;
966 }
967 else if (common & ADVERTISE_10HALF) {
968 bp->line_speed = SPEED_10;
969 bp->duplex = DUPLEX_HALF;
970 }
971 else {
972 bp->line_speed = 0;
973 bp->link_up = 0;
974 }
975 }
976 }
977 else {
978 if (bmcr & BMCR_SPEED100) {
979 bp->line_speed = SPEED_100;
980 }
981 else {
982 bp->line_speed = SPEED_10;
983 }
984 if (bmcr & BMCR_FULLDPLX) {
985 bp->duplex = DUPLEX_FULL;
986 }
987 else {
988 bp->duplex = DUPLEX_HALF;
989 }
990 }
991
992 return 0;
993}
994
Michael Chan83e3fc82008-01-29 21:37:17 -0800995static void
996bnx2_init_rx_context0(struct bnx2 *bp)
997{
998 u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
999
1000 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1001 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1002 val |= 0x02 << 8;
1003
1004 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1005 u32 lo_water, hi_water;
1006
1007 if (bp->flow_ctrl & FLOW_CTRL_TX)
1008 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1009 else
1010 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1011 if (lo_water >= bp->rx_ring_size)
1012 lo_water = 0;
1013
1014 hi_water = bp->rx_ring_size / 4;
1015
1016 if (hi_water <= lo_water)
1017 lo_water = 0;
1018
1019 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1020 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1021
1022 if (hi_water > 0xf)
1023 hi_water = 0xf;
1024 else if (hi_water == 0)
1025 lo_water = 0;
1026 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1027 }
1028 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1029}
1030
Michael Chanb6016b72005-05-26 13:03:09 -07001031static int
1032bnx2_set_mac_link(struct bnx2 *bp)
1033{
1034 u32 val;
1035
1036 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1037 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1038 (bp->duplex == DUPLEX_HALF)) {
1039 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1040 }
1041
1042 /* Configure the EMAC mode register. */
1043 val = REG_RD(bp, BNX2_EMAC_MODE);
1044
1045 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
Michael Chan5b0c76a2005-11-04 08:45:49 -08001046 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
Michael Chan59b47d82006-11-19 14:10:45 -08001047 BNX2_EMAC_MODE_25G_MODE);
Michael Chanb6016b72005-05-26 13:03:09 -07001048
1049 if (bp->link_up) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08001050 switch (bp->line_speed) {
1051 case SPEED_10:
Michael Chan59b47d82006-11-19 14:10:45 -08001052 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1053 val |= BNX2_EMAC_MODE_PORT_MII_10M;
Michael Chan5b0c76a2005-11-04 08:45:49 -08001054 break;
1055 }
1056 /* fall through */
1057 case SPEED_100:
1058 val |= BNX2_EMAC_MODE_PORT_MII;
1059 break;
1060 case SPEED_2500:
Michael Chan59b47d82006-11-19 14:10:45 -08001061 val |= BNX2_EMAC_MODE_25G_MODE;
Michael Chan5b0c76a2005-11-04 08:45:49 -08001062 /* fall through */
1063 case SPEED_1000:
1064 val |= BNX2_EMAC_MODE_PORT_GMII;
1065 break;
1066 }
Michael Chanb6016b72005-05-26 13:03:09 -07001067 }
1068 else {
1069 val |= BNX2_EMAC_MODE_PORT_GMII;
1070 }
1071
1072 /* Set the MAC to operate in the appropriate duplex mode. */
1073 if (bp->duplex == DUPLEX_HALF)
1074 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1075 REG_WR(bp, BNX2_EMAC_MODE, val);
1076
1077 /* Enable/disable rx PAUSE. */
1078 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1079
1080 if (bp->flow_ctrl & FLOW_CTRL_RX)
1081 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1082 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1083
1084 /* Enable/disable tx PAUSE. */
1085 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1086 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1087
1088 if (bp->flow_ctrl & FLOW_CTRL_TX)
1089 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1090 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1091
1092 /* Acknowledge the interrupt. */
1093 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1094
Michael Chan83e3fc82008-01-29 21:37:17 -08001095 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1096 bnx2_init_rx_context0(bp);
1097
Michael Chanb6016b72005-05-26 13:03:09 -07001098 return 0;
1099}
1100
Michael Chan27a005b2007-05-03 13:23:41 -07001101static void
1102bnx2_enable_bmsr1(struct bnx2 *bp)
1103{
Michael Chan583c28e2008-01-21 19:51:35 -08001104 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chan27a005b2007-05-03 13:23:41 -07001105 (CHIP_NUM(bp) == CHIP_NUM_5709))
1106 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1107 MII_BNX2_BLK_ADDR_GP_STATUS);
1108}
1109
1110static void
1111bnx2_disable_bmsr1(struct bnx2 *bp)
1112{
Michael Chan583c28e2008-01-21 19:51:35 -08001113 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chan27a005b2007-05-03 13:23:41 -07001114 (CHIP_NUM(bp) == CHIP_NUM_5709))
1115 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1116 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1117}
1118
Michael Chanb6016b72005-05-26 13:03:09 -07001119static int
Michael Chan605a9e22007-05-03 13:23:13 -07001120bnx2_test_and_enable_2g5(struct bnx2 *bp)
1121{
1122 u32 up1;
1123 int ret = 1;
1124
Michael Chan583c28e2008-01-21 19:51:35 -08001125 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan605a9e22007-05-03 13:23:13 -07001126 return 0;
1127
1128 if (bp->autoneg & AUTONEG_SPEED)
1129 bp->advertising |= ADVERTISED_2500baseX_Full;
1130
Michael Chan27a005b2007-05-03 13:23:41 -07001131 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1132 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1133
Michael Chan605a9e22007-05-03 13:23:13 -07001134 bnx2_read_phy(bp, bp->mii_up1, &up1);
1135 if (!(up1 & BCM5708S_UP1_2G5)) {
1136 up1 |= BCM5708S_UP1_2G5;
1137 bnx2_write_phy(bp, bp->mii_up1, up1);
1138 ret = 0;
1139 }
1140
Michael Chan27a005b2007-05-03 13:23:41 -07001141 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1142 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1143 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1144
Michael Chan605a9e22007-05-03 13:23:13 -07001145 return ret;
1146}
1147
1148static int
1149bnx2_test_and_disable_2g5(struct bnx2 *bp)
1150{
1151 u32 up1;
1152 int ret = 0;
1153
Michael Chan583c28e2008-01-21 19:51:35 -08001154 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan605a9e22007-05-03 13:23:13 -07001155 return 0;
1156
Michael Chan27a005b2007-05-03 13:23:41 -07001157 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1158 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1159
Michael Chan605a9e22007-05-03 13:23:13 -07001160 bnx2_read_phy(bp, bp->mii_up1, &up1);
1161 if (up1 & BCM5708S_UP1_2G5) {
1162 up1 &= ~BCM5708S_UP1_2G5;
1163 bnx2_write_phy(bp, bp->mii_up1, up1);
1164 ret = 1;
1165 }
1166
Michael Chan27a005b2007-05-03 13:23:41 -07001167 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1168 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1169 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1170
Michael Chan605a9e22007-05-03 13:23:13 -07001171 return ret;
1172}
1173
1174static void
1175bnx2_enable_forced_2g5(struct bnx2 *bp)
1176{
1177 u32 bmcr;
1178
Michael Chan583c28e2008-01-21 19:51:35 -08001179 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan605a9e22007-05-03 13:23:13 -07001180 return;
1181
Michael Chan27a005b2007-05-03 13:23:41 -07001182 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1183 u32 val;
1184
1185 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1186 MII_BNX2_BLK_ADDR_SERDES_DIG);
1187 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1188 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1189 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1190 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1191
1192 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1193 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1194 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1195
1196 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
Michael Chan605a9e22007-05-03 13:23:13 -07001197 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1198 bmcr |= BCM5708S_BMCR_FORCE_2500;
1199 }
1200
1201 if (bp->autoneg & AUTONEG_SPEED) {
1202 bmcr &= ~BMCR_ANENABLE;
1203 if (bp->req_duplex == DUPLEX_FULL)
1204 bmcr |= BMCR_FULLDPLX;
1205 }
1206 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1207}
1208
1209static void
1210bnx2_disable_forced_2g5(struct bnx2 *bp)
1211{
1212 u32 bmcr;
1213
Michael Chan583c28e2008-01-21 19:51:35 -08001214 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan605a9e22007-05-03 13:23:13 -07001215 return;
1216
Michael Chan27a005b2007-05-03 13:23:41 -07001217 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1218 u32 val;
1219
1220 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1221 MII_BNX2_BLK_ADDR_SERDES_DIG);
1222 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1223 val &= ~MII_BNX2_SD_MISC1_FORCE;
1224 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1225
1226 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1227 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1228 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1229
1230 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
Michael Chan605a9e22007-05-03 13:23:13 -07001231 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1232 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1233 }
1234
1235 if (bp->autoneg & AUTONEG_SPEED)
1236 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1237 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1238}
1239
Michael Chanb2fadea2008-01-21 17:07:06 -08001240static void
1241bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1242{
1243 u32 val;
1244
1245 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1246 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1247 if (start)
1248 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1249 else
1250 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1251}
1252
Michael Chan605a9e22007-05-03 13:23:13 -07001253static int
Michael Chanb6016b72005-05-26 13:03:09 -07001254bnx2_set_link(struct bnx2 *bp)
1255{
1256 u32 bmsr;
1257 u8 link_up;
1258
Michael Chan80be4432006-11-19 14:07:28 -08001259 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
Michael Chanb6016b72005-05-26 13:03:09 -07001260 bp->link_up = 1;
1261 return 0;
1262 }
1263
Michael Chan583c28e2008-01-21 19:51:35 -08001264 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -07001265 return 0;
1266
Michael Chanb6016b72005-05-26 13:03:09 -07001267 link_up = bp->link_up;
1268
Michael Chan27a005b2007-05-03 13:23:41 -07001269 bnx2_enable_bmsr1(bp);
1270 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1271 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1272 bnx2_disable_bmsr1(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001273
Michael Chan583c28e2008-01-21 19:51:35 -08001274 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chanb6016b72005-05-26 13:03:09 -07001275 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1276 u32 val;
1277
Michael Chan583c28e2008-01-21 19:51:35 -08001278 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
Michael Chanb2fadea2008-01-21 17:07:06 -08001279 bnx2_5706s_force_link_dn(bp, 0);
Michael Chan583c28e2008-01-21 19:51:35 -08001280 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
Michael Chanb2fadea2008-01-21 17:07:06 -08001281 }
Michael Chanb6016b72005-05-26 13:03:09 -07001282 val = REG_RD(bp, BNX2_EMAC_STATUS);
1283 if (val & BNX2_EMAC_STATUS_LINK)
1284 bmsr |= BMSR_LSTATUS;
1285 else
1286 bmsr &= ~BMSR_LSTATUS;
1287 }
1288
1289 if (bmsr & BMSR_LSTATUS) {
1290 bp->link_up = 1;
1291
Michael Chan583c28e2008-01-21 19:51:35 -08001292 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08001293 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1294 bnx2_5706s_linkup(bp);
1295 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1296 bnx2_5708s_linkup(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07001297 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1298 bnx2_5709s_linkup(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001299 }
1300 else {
1301 bnx2_copper_linkup(bp);
1302 }
1303 bnx2_resolve_flow_ctrl(bp);
1304 }
1305 else {
Michael Chan583c28e2008-01-21 19:51:35 -08001306 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
Michael Chan605a9e22007-05-03 13:23:13 -07001307 (bp->autoneg & AUTONEG_SPEED))
1308 bnx2_disable_forced_2g5(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001309
Michael Chan583c28e2008-01-21 19:51:35 -08001310 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
Michael Chanb2fadea2008-01-21 17:07:06 -08001311 u32 bmcr;
1312
1313 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1314 bmcr |= BMCR_ANENABLE;
1315 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1316
Michael Chan583c28e2008-01-21 19:51:35 -08001317 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
Michael Chanb2fadea2008-01-21 17:07:06 -08001318 }
Michael Chanb6016b72005-05-26 13:03:09 -07001319 bp->link_up = 0;
1320 }
1321
1322 if (bp->link_up != link_up) {
1323 bnx2_report_link(bp);
1324 }
1325
1326 bnx2_set_mac_link(bp);
1327
1328 return 0;
1329}
1330
1331static int
1332bnx2_reset_phy(struct bnx2 *bp)
1333{
1334 int i;
1335 u32 reg;
1336
Michael Chanca58c3a2007-05-03 13:22:52 -07001337 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
Michael Chanb6016b72005-05-26 13:03:09 -07001338
1339#define PHY_RESET_MAX_WAIT 100
1340 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1341 udelay(10);
1342
Michael Chanca58c3a2007-05-03 13:22:52 -07001343 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
Michael Chanb6016b72005-05-26 13:03:09 -07001344 if (!(reg & BMCR_RESET)) {
1345 udelay(20);
1346 break;
1347 }
1348 }
1349 if (i == PHY_RESET_MAX_WAIT) {
1350 return -EBUSY;
1351 }
1352 return 0;
1353}
1354
1355static u32
1356bnx2_phy_get_pause_adv(struct bnx2 *bp)
1357{
1358 u32 adv = 0;
1359
1360 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1361 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1362
Michael Chan583c28e2008-01-21 19:51:35 -08001363 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanb6016b72005-05-26 13:03:09 -07001364 adv = ADVERTISE_1000XPAUSE;
1365 }
1366 else {
1367 adv = ADVERTISE_PAUSE_CAP;
1368 }
1369 }
1370 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
Michael Chan583c28e2008-01-21 19:51:35 -08001371 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanb6016b72005-05-26 13:03:09 -07001372 adv = ADVERTISE_1000XPSE_ASYM;
1373 }
1374 else {
1375 adv = ADVERTISE_PAUSE_ASYM;
1376 }
1377 }
1378 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
Michael Chan583c28e2008-01-21 19:51:35 -08001379 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanb6016b72005-05-26 13:03:09 -07001380 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1381 }
1382 else {
1383 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1384 }
1385 }
1386 return adv;
1387}
1388
Michael Chan0d8a6572007-07-07 22:49:43 -07001389static int bnx2_fw_sync(struct bnx2 *, u32, int);
1390
Michael Chanb6016b72005-05-26 13:03:09 -07001391static int
Michael Chan0d8a6572007-07-07 22:49:43 -07001392bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1393{
1394 u32 speed_arg = 0, pause_adv;
1395
1396 pause_adv = bnx2_phy_get_pause_adv(bp);
1397
1398 if (bp->autoneg & AUTONEG_SPEED) {
1399 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1400 if (bp->advertising & ADVERTISED_10baseT_Half)
1401 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1402 if (bp->advertising & ADVERTISED_10baseT_Full)
1403 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1404 if (bp->advertising & ADVERTISED_100baseT_Half)
1405 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1406 if (bp->advertising & ADVERTISED_100baseT_Full)
1407 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1408 if (bp->advertising & ADVERTISED_1000baseT_Full)
1409 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1410 if (bp->advertising & ADVERTISED_2500baseX_Full)
1411 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1412 } else {
1413 if (bp->req_line_speed == SPEED_2500)
1414 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1415 else if (bp->req_line_speed == SPEED_1000)
1416 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1417 else if (bp->req_line_speed == SPEED_100) {
1418 if (bp->req_duplex == DUPLEX_FULL)
1419 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1420 else
1421 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1422 } else if (bp->req_line_speed == SPEED_10) {
1423 if (bp->req_duplex == DUPLEX_FULL)
1424 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1425 else
1426 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1427 }
1428 }
1429
1430 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1431 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
Michael Chanc26736e2008-01-31 17:07:21 -08001432 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
Michael Chan0d8a6572007-07-07 22:49:43 -07001433 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1434
1435 if (port == PORT_TP)
1436 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1437 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1438
Michael Chan2726d6e2008-01-29 21:35:05 -08001439 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
Michael Chan0d8a6572007-07-07 22:49:43 -07001440
1441 spin_unlock_bh(&bp->phy_lock);
1442 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0);
1443 spin_lock_bh(&bp->phy_lock);
1444
1445 return 0;
1446}
1447
1448static int
1449bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
Michael Chanb6016b72005-05-26 13:03:09 -07001450{
Michael Chan605a9e22007-05-03 13:23:13 -07001451 u32 adv, bmcr;
Michael Chanb6016b72005-05-26 13:03:09 -07001452 u32 new_adv = 0;
1453
Michael Chan583c28e2008-01-21 19:51:35 -08001454 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -07001455 return (bnx2_setup_remote_phy(bp, port));
1456
Michael Chanb6016b72005-05-26 13:03:09 -07001457 if (!(bp->autoneg & AUTONEG_SPEED)) {
1458 u32 new_bmcr;
Michael Chan5b0c76a2005-11-04 08:45:49 -08001459 int force_link_down = 0;
1460
Michael Chan605a9e22007-05-03 13:23:13 -07001461 if (bp->req_line_speed == SPEED_2500) {
1462 if (!bnx2_test_and_enable_2g5(bp))
1463 force_link_down = 1;
1464 } else if (bp->req_line_speed == SPEED_1000) {
1465 if (bnx2_test_and_disable_2g5(bp))
1466 force_link_down = 1;
1467 }
Michael Chanca58c3a2007-05-03 13:22:52 -07001468 bnx2_read_phy(bp, bp->mii_adv, &adv);
Michael Chan80be4432006-11-19 14:07:28 -08001469 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1470
Michael Chanca58c3a2007-05-03 13:22:52 -07001471 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chan605a9e22007-05-03 13:23:13 -07001472 new_bmcr = bmcr & ~BMCR_ANENABLE;
Michael Chan80be4432006-11-19 14:07:28 -08001473 new_bmcr |= BMCR_SPEED1000;
Michael Chan605a9e22007-05-03 13:23:13 -07001474
Michael Chan27a005b2007-05-03 13:23:41 -07001475 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1476 if (bp->req_line_speed == SPEED_2500)
1477 bnx2_enable_forced_2g5(bp);
1478 else if (bp->req_line_speed == SPEED_1000) {
1479 bnx2_disable_forced_2g5(bp);
1480 new_bmcr &= ~0x2000;
1481 }
1482
1483 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
Michael Chan605a9e22007-05-03 13:23:13 -07001484 if (bp->req_line_speed == SPEED_2500)
1485 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1486 else
1487 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
Michael Chan5b0c76a2005-11-04 08:45:49 -08001488 }
1489
Michael Chanb6016b72005-05-26 13:03:09 -07001490 if (bp->req_duplex == DUPLEX_FULL) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08001491 adv |= ADVERTISE_1000XFULL;
Michael Chanb6016b72005-05-26 13:03:09 -07001492 new_bmcr |= BMCR_FULLDPLX;
1493 }
1494 else {
Michael Chan5b0c76a2005-11-04 08:45:49 -08001495 adv |= ADVERTISE_1000XHALF;
Michael Chanb6016b72005-05-26 13:03:09 -07001496 new_bmcr &= ~BMCR_FULLDPLX;
1497 }
Michael Chan5b0c76a2005-11-04 08:45:49 -08001498 if ((new_bmcr != bmcr) || (force_link_down)) {
Michael Chanb6016b72005-05-26 13:03:09 -07001499 /* Force a link down visible on the other side */
1500 if (bp->link_up) {
Michael Chanca58c3a2007-05-03 13:22:52 -07001501 bnx2_write_phy(bp, bp->mii_adv, adv &
Michael Chan5b0c76a2005-11-04 08:45:49 -08001502 ~(ADVERTISE_1000XFULL |
1503 ADVERTISE_1000XHALF));
Michael Chanca58c3a2007-05-03 13:22:52 -07001504 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
Michael Chanb6016b72005-05-26 13:03:09 -07001505 BMCR_ANRESTART | BMCR_ANENABLE);
1506
1507 bp->link_up = 0;
1508 netif_carrier_off(bp->dev);
Michael Chanca58c3a2007-05-03 13:22:52 -07001509 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
Michael Chan80be4432006-11-19 14:07:28 -08001510 bnx2_report_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001511 }
Michael Chanca58c3a2007-05-03 13:22:52 -07001512 bnx2_write_phy(bp, bp->mii_adv, adv);
1513 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
Michael Chan605a9e22007-05-03 13:23:13 -07001514 } else {
1515 bnx2_resolve_flow_ctrl(bp);
1516 bnx2_set_mac_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001517 }
1518 return 0;
1519 }
1520
Michael Chan605a9e22007-05-03 13:23:13 -07001521 bnx2_test_and_enable_2g5(bp);
Michael Chan5b0c76a2005-11-04 08:45:49 -08001522
Michael Chanb6016b72005-05-26 13:03:09 -07001523 if (bp->advertising & ADVERTISED_1000baseT_Full)
1524 new_adv |= ADVERTISE_1000XFULL;
1525
1526 new_adv |= bnx2_phy_get_pause_adv(bp);
1527
Michael Chanca58c3a2007-05-03 13:22:52 -07001528 bnx2_read_phy(bp, bp->mii_adv, &adv);
1529 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07001530
1531 bp->serdes_an_pending = 0;
1532 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1533 /* Force a link down visible on the other side */
1534 if (bp->link_up) {
Michael Chanca58c3a2007-05-03 13:22:52 -07001535 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
Michael Chan80be4432006-11-19 14:07:28 -08001536 spin_unlock_bh(&bp->phy_lock);
1537 msleep(20);
1538 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07001539 }
1540
Michael Chanca58c3a2007-05-03 13:22:52 -07001541 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1542 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
Michael Chanb6016b72005-05-26 13:03:09 -07001543 BMCR_ANENABLE);
Michael Chanf8dd0642006-11-19 14:08:29 -08001544 /* Speed up link-up time when the link partner
1545 * does not autonegotiate which is very common
1546 * in blade servers. Some blade servers use
1547 * IPMI for kerboard input and it's important
1548 * to minimize link disruptions. Autoneg. involves
1549 * exchanging base pages plus 3 next pages and
1550 * normally completes in about 120 msec.
1551 */
1552 bp->current_interval = SERDES_AN_TIMEOUT;
1553 bp->serdes_an_pending = 1;
1554 mod_timer(&bp->timer, jiffies + bp->current_interval);
Michael Chan605a9e22007-05-03 13:23:13 -07001555 } else {
1556 bnx2_resolve_flow_ctrl(bp);
1557 bnx2_set_mac_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001558 }
1559
1560 return 0;
1561}
1562
1563#define ETHTOOL_ALL_FIBRE_SPEED \
Michael Chan583c28e2008-01-21 19:51:35 -08001564 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
Michael Chandeaf3912007-07-07 22:48:00 -07001565 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1566 (ADVERTISED_1000baseT_Full)
Michael Chanb6016b72005-05-26 13:03:09 -07001567
1568#define ETHTOOL_ALL_COPPER_SPEED \
1569 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1570 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1571 ADVERTISED_1000baseT_Full)
1572
1573#define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1574 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001575
Michael Chanb6016b72005-05-26 13:03:09 -07001576#define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1577
Michael Chandeaf3912007-07-07 22:48:00 -07001578static void
Michael Chan0d8a6572007-07-07 22:49:43 -07001579bnx2_set_default_remote_link(struct bnx2 *bp)
1580{
1581 u32 link;
1582
1583 if (bp->phy_port == PORT_TP)
Michael Chan2726d6e2008-01-29 21:35:05 -08001584 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
Michael Chan0d8a6572007-07-07 22:49:43 -07001585 else
Michael Chan2726d6e2008-01-29 21:35:05 -08001586 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
Michael Chan0d8a6572007-07-07 22:49:43 -07001587
1588 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1589 bp->req_line_speed = 0;
1590 bp->autoneg |= AUTONEG_SPEED;
1591 bp->advertising = ADVERTISED_Autoneg;
1592 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1593 bp->advertising |= ADVERTISED_10baseT_Half;
1594 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1595 bp->advertising |= ADVERTISED_10baseT_Full;
1596 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1597 bp->advertising |= ADVERTISED_100baseT_Half;
1598 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1599 bp->advertising |= ADVERTISED_100baseT_Full;
1600 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1601 bp->advertising |= ADVERTISED_1000baseT_Full;
1602 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1603 bp->advertising |= ADVERTISED_2500baseX_Full;
1604 } else {
1605 bp->autoneg = 0;
1606 bp->advertising = 0;
1607 bp->req_duplex = DUPLEX_FULL;
1608 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1609 bp->req_line_speed = SPEED_10;
1610 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1611 bp->req_duplex = DUPLEX_HALF;
1612 }
1613 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1614 bp->req_line_speed = SPEED_100;
1615 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1616 bp->req_duplex = DUPLEX_HALF;
1617 }
1618 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1619 bp->req_line_speed = SPEED_1000;
1620 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1621 bp->req_line_speed = SPEED_2500;
1622 }
1623}
1624
1625static void
Michael Chandeaf3912007-07-07 22:48:00 -07001626bnx2_set_default_link(struct bnx2 *bp)
1627{
Michael Chan583c28e2008-01-21 19:51:35 -08001628 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -07001629 return bnx2_set_default_remote_link(bp);
1630
Michael Chandeaf3912007-07-07 22:48:00 -07001631 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1632 bp->req_line_speed = 0;
Michael Chan583c28e2008-01-21 19:51:35 -08001633 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chandeaf3912007-07-07 22:48:00 -07001634 u32 reg;
1635
1636 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1637
Michael Chan2726d6e2008-01-29 21:35:05 -08001638 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
Michael Chandeaf3912007-07-07 22:48:00 -07001639 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1640 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1641 bp->autoneg = 0;
1642 bp->req_line_speed = bp->line_speed = SPEED_1000;
1643 bp->req_duplex = DUPLEX_FULL;
1644 }
1645 } else
1646 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1647}
1648
Michael Chan0d8a6572007-07-07 22:49:43 -07001649static void
Michael Chandf149d72007-07-07 22:51:36 -07001650bnx2_send_heart_beat(struct bnx2 *bp)
1651{
1652 u32 msg;
1653 u32 addr;
1654
1655 spin_lock(&bp->indirect_lock);
1656 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1657 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1658 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1659 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1660 spin_unlock(&bp->indirect_lock);
1661}
1662
1663static void
Michael Chan0d8a6572007-07-07 22:49:43 -07001664bnx2_remote_phy_event(struct bnx2 *bp)
1665{
1666 u32 msg;
1667 u8 link_up = bp->link_up;
1668 u8 old_port;
1669
Michael Chan2726d6e2008-01-29 21:35:05 -08001670 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
Michael Chan0d8a6572007-07-07 22:49:43 -07001671
Michael Chandf149d72007-07-07 22:51:36 -07001672 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1673 bnx2_send_heart_beat(bp);
1674
1675 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1676
Michael Chan0d8a6572007-07-07 22:49:43 -07001677 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1678 bp->link_up = 0;
1679 else {
1680 u32 speed;
1681
1682 bp->link_up = 1;
1683 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1684 bp->duplex = DUPLEX_FULL;
1685 switch (speed) {
1686 case BNX2_LINK_STATUS_10HALF:
1687 bp->duplex = DUPLEX_HALF;
1688 case BNX2_LINK_STATUS_10FULL:
1689 bp->line_speed = SPEED_10;
1690 break;
1691 case BNX2_LINK_STATUS_100HALF:
1692 bp->duplex = DUPLEX_HALF;
1693 case BNX2_LINK_STATUS_100BASE_T4:
1694 case BNX2_LINK_STATUS_100FULL:
1695 bp->line_speed = SPEED_100;
1696 break;
1697 case BNX2_LINK_STATUS_1000HALF:
1698 bp->duplex = DUPLEX_HALF;
1699 case BNX2_LINK_STATUS_1000FULL:
1700 bp->line_speed = SPEED_1000;
1701 break;
1702 case BNX2_LINK_STATUS_2500HALF:
1703 bp->duplex = DUPLEX_HALF;
1704 case BNX2_LINK_STATUS_2500FULL:
1705 bp->line_speed = SPEED_2500;
1706 break;
1707 default:
1708 bp->line_speed = 0;
1709 break;
1710 }
1711
1712 spin_lock(&bp->phy_lock);
1713 bp->flow_ctrl = 0;
1714 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1715 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1716 if (bp->duplex == DUPLEX_FULL)
1717 bp->flow_ctrl = bp->req_flow_ctrl;
1718 } else {
1719 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1720 bp->flow_ctrl |= FLOW_CTRL_TX;
1721 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1722 bp->flow_ctrl |= FLOW_CTRL_RX;
1723 }
1724
1725 old_port = bp->phy_port;
1726 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1727 bp->phy_port = PORT_FIBRE;
1728 else
1729 bp->phy_port = PORT_TP;
1730
1731 if (old_port != bp->phy_port)
1732 bnx2_set_default_link(bp);
1733
1734 spin_unlock(&bp->phy_lock);
1735 }
1736 if (bp->link_up != link_up)
1737 bnx2_report_link(bp);
1738
1739 bnx2_set_mac_link(bp);
1740}
1741
1742static int
1743bnx2_set_remote_link(struct bnx2 *bp)
1744{
1745 u32 evt_code;
1746
Michael Chan2726d6e2008-01-29 21:35:05 -08001747 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
Michael Chan0d8a6572007-07-07 22:49:43 -07001748 switch (evt_code) {
1749 case BNX2_FW_EVT_CODE_LINK_EVENT:
1750 bnx2_remote_phy_event(bp);
1751 break;
1752 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1753 default:
Michael Chandf149d72007-07-07 22:51:36 -07001754 bnx2_send_heart_beat(bp);
Michael Chan0d8a6572007-07-07 22:49:43 -07001755 break;
1756 }
1757 return 0;
1758}
1759
Michael Chanb6016b72005-05-26 13:03:09 -07001760static int
1761bnx2_setup_copper_phy(struct bnx2 *bp)
1762{
1763 u32 bmcr;
1764 u32 new_bmcr;
1765
Michael Chanca58c3a2007-05-03 13:22:52 -07001766 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07001767
1768 if (bp->autoneg & AUTONEG_SPEED) {
1769 u32 adv_reg, adv1000_reg;
1770 u32 new_adv_reg = 0;
1771 u32 new_adv1000_reg = 0;
1772
Michael Chanca58c3a2007-05-03 13:22:52 -07001773 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
Michael Chanb6016b72005-05-26 13:03:09 -07001774 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1775 ADVERTISE_PAUSE_ASYM);
1776
1777 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1778 adv1000_reg &= PHY_ALL_1000_SPEED;
1779
1780 if (bp->advertising & ADVERTISED_10baseT_Half)
1781 new_adv_reg |= ADVERTISE_10HALF;
1782 if (bp->advertising & ADVERTISED_10baseT_Full)
1783 new_adv_reg |= ADVERTISE_10FULL;
1784 if (bp->advertising & ADVERTISED_100baseT_Half)
1785 new_adv_reg |= ADVERTISE_100HALF;
1786 if (bp->advertising & ADVERTISED_100baseT_Full)
1787 new_adv_reg |= ADVERTISE_100FULL;
1788 if (bp->advertising & ADVERTISED_1000baseT_Full)
1789 new_adv1000_reg |= ADVERTISE_1000FULL;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001790
Michael Chanb6016b72005-05-26 13:03:09 -07001791 new_adv_reg |= ADVERTISE_CSMA;
1792
1793 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1794
1795 if ((adv1000_reg != new_adv1000_reg) ||
1796 (adv_reg != new_adv_reg) ||
1797 ((bmcr & BMCR_ANENABLE) == 0)) {
1798
Michael Chanca58c3a2007-05-03 13:22:52 -07001799 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
Michael Chanb6016b72005-05-26 13:03:09 -07001800 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
Michael Chanca58c3a2007-05-03 13:22:52 -07001801 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
Michael Chanb6016b72005-05-26 13:03:09 -07001802 BMCR_ANENABLE);
1803 }
1804 else if (bp->link_up) {
1805 /* Flow ctrl may have changed from auto to forced */
1806 /* or vice-versa. */
1807
1808 bnx2_resolve_flow_ctrl(bp);
1809 bnx2_set_mac_link(bp);
1810 }
1811 return 0;
1812 }
1813
1814 new_bmcr = 0;
1815 if (bp->req_line_speed == SPEED_100) {
1816 new_bmcr |= BMCR_SPEED100;
1817 }
1818 if (bp->req_duplex == DUPLEX_FULL) {
1819 new_bmcr |= BMCR_FULLDPLX;
1820 }
1821 if (new_bmcr != bmcr) {
1822 u32 bmsr;
Michael Chanb6016b72005-05-26 13:03:09 -07001823
Michael Chanca58c3a2007-05-03 13:22:52 -07001824 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1825 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04001826
Michael Chanb6016b72005-05-26 13:03:09 -07001827 if (bmsr & BMSR_LSTATUS) {
1828 /* Force link down */
Michael Chanca58c3a2007-05-03 13:22:52 -07001829 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
Michael Chana16dda02006-11-19 14:08:56 -08001830 spin_unlock_bh(&bp->phy_lock);
1831 msleep(50);
1832 spin_lock_bh(&bp->phy_lock);
1833
Michael Chanca58c3a2007-05-03 13:22:52 -07001834 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1835 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
Michael Chanb6016b72005-05-26 13:03:09 -07001836 }
1837
Michael Chanca58c3a2007-05-03 13:22:52 -07001838 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07001839
1840 /* Normally, the new speed is setup after the link has
1841 * gone down and up again. In some cases, link will not go
1842 * down so we need to set up the new speed here.
1843 */
1844 if (bmsr & BMSR_LSTATUS) {
1845 bp->line_speed = bp->req_line_speed;
1846 bp->duplex = bp->req_duplex;
1847 bnx2_resolve_flow_ctrl(bp);
1848 bnx2_set_mac_link(bp);
1849 }
Michael Chan27a005b2007-05-03 13:23:41 -07001850 } else {
1851 bnx2_resolve_flow_ctrl(bp);
1852 bnx2_set_mac_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07001853 }
1854 return 0;
1855}
1856
1857static int
Michael Chan0d8a6572007-07-07 22:49:43 -07001858bnx2_setup_phy(struct bnx2 *bp, u8 port)
Michael Chanb6016b72005-05-26 13:03:09 -07001859{
1860 if (bp->loopback == MAC_LOOPBACK)
1861 return 0;
1862
Michael Chan583c28e2008-01-21 19:51:35 -08001863 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chan0d8a6572007-07-07 22:49:43 -07001864 return (bnx2_setup_serdes_phy(bp, port));
Michael Chanb6016b72005-05-26 13:03:09 -07001865 }
1866 else {
1867 return (bnx2_setup_copper_phy(bp));
1868 }
1869}
1870
1871static int
Michael Chan27a005b2007-05-03 13:23:41 -07001872bnx2_init_5709s_phy(struct bnx2 *bp)
1873{
1874 u32 val;
1875
1876 bp->mii_bmcr = MII_BMCR + 0x10;
1877 bp->mii_bmsr = MII_BMSR + 0x10;
1878 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1879 bp->mii_adv = MII_ADVERTISE + 0x10;
1880 bp->mii_lpa = MII_LPA + 0x10;
1881 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1882
1883 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1884 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1885
1886 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1887 bnx2_reset_phy(bp);
1888
1889 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1890
1891 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1892 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1893 val |= MII_BNX2_SD_1000XCTL1_FIBER;
1894 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1895
1896 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1897 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
Michael Chan583c28e2008-01-21 19:51:35 -08001898 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
Michael Chan27a005b2007-05-03 13:23:41 -07001899 val |= BCM5708S_UP1_2G5;
1900 else
1901 val &= ~BCM5708S_UP1_2G5;
1902 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
1903
1904 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
1905 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
1906 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
1907 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
1908
1909 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
1910
1911 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
1912 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
1913 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
1914
1915 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1916
1917 return 0;
1918}
1919
1920static int
Michael Chan5b0c76a2005-11-04 08:45:49 -08001921bnx2_init_5708s_phy(struct bnx2 *bp)
1922{
1923 u32 val;
1924
Michael Chan27a005b2007-05-03 13:23:41 -07001925 bnx2_reset_phy(bp);
1926
1927 bp->mii_up1 = BCM5708S_UP1;
1928
Michael Chan5b0c76a2005-11-04 08:45:49 -08001929 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1930 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1931 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1932
1933 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1934 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1935 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1936
1937 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1938 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1939 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1940
Michael Chan583c28e2008-01-21 19:51:35 -08001941 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08001942 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1943 val |= BCM5708S_UP1_2G5;
1944 bnx2_write_phy(bp, BCM5708S_UP1, val);
1945 }
1946
1947 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
Michael Chandda1e392006-01-23 16:08:14 -08001948 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1949 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08001950 /* increase tx signal amplitude */
1951 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1952 BCM5708S_BLK_ADDR_TX_MISC);
1953 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1954 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1955 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1956 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1957 }
1958
Michael Chan2726d6e2008-01-29 21:35:05 -08001959 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
Michael Chan5b0c76a2005-11-04 08:45:49 -08001960 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1961
1962 if (val) {
1963 u32 is_backplane;
1964
Michael Chan2726d6e2008-01-29 21:35:05 -08001965 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
Michael Chan5b0c76a2005-11-04 08:45:49 -08001966 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1967 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1968 BCM5708S_BLK_ADDR_TX_MISC);
1969 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1970 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1971 BCM5708S_BLK_ADDR_DIG);
1972 }
1973 }
1974 return 0;
1975}
1976
1977static int
1978bnx2_init_5706s_phy(struct bnx2 *bp)
Michael Chanb6016b72005-05-26 13:03:09 -07001979{
Michael Chan27a005b2007-05-03 13:23:41 -07001980 bnx2_reset_phy(bp);
1981
Michael Chan583c28e2008-01-21 19:51:35 -08001982 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
Michael Chanb6016b72005-05-26 13:03:09 -07001983
Michael Chan59b47d82006-11-19 14:10:45 -08001984 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1985 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
Michael Chanb6016b72005-05-26 13:03:09 -07001986
1987 if (bp->dev->mtu > 1500) {
1988 u32 val;
1989
1990 /* Set extended packet length bit */
1991 bnx2_write_phy(bp, 0x18, 0x7);
1992 bnx2_read_phy(bp, 0x18, &val);
1993 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1994
1995 bnx2_write_phy(bp, 0x1c, 0x6c00);
1996 bnx2_read_phy(bp, 0x1c, &val);
1997 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1998 }
1999 else {
2000 u32 val;
2001
2002 bnx2_write_phy(bp, 0x18, 0x7);
2003 bnx2_read_phy(bp, 0x18, &val);
2004 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2005
2006 bnx2_write_phy(bp, 0x1c, 0x6c00);
2007 bnx2_read_phy(bp, 0x1c, &val);
2008 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2009 }
2010
2011 return 0;
2012}
2013
2014static int
2015bnx2_init_copper_phy(struct bnx2 *bp)
2016{
Michael Chan5b0c76a2005-11-04 08:45:49 -08002017 u32 val;
2018
Michael Chan27a005b2007-05-03 13:23:41 -07002019 bnx2_reset_phy(bp);
2020
Michael Chan583c28e2008-01-21 19:51:35 -08002021 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
Michael Chanb6016b72005-05-26 13:03:09 -07002022 bnx2_write_phy(bp, 0x18, 0x0c00);
2023 bnx2_write_phy(bp, 0x17, 0x000a);
2024 bnx2_write_phy(bp, 0x15, 0x310b);
2025 bnx2_write_phy(bp, 0x17, 0x201f);
2026 bnx2_write_phy(bp, 0x15, 0x9506);
2027 bnx2_write_phy(bp, 0x17, 0x401f);
2028 bnx2_write_phy(bp, 0x15, 0x14e2);
2029 bnx2_write_phy(bp, 0x18, 0x0400);
2030 }
2031
Michael Chan583c28e2008-01-21 19:51:35 -08002032 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
Michael Chanb659f442007-02-02 00:46:35 -08002033 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2034 MII_BNX2_DSP_EXPAND_REG | 0x8);
2035 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2036 val &= ~(1 << 8);
2037 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2038 }
2039
Michael Chanb6016b72005-05-26 13:03:09 -07002040 if (bp->dev->mtu > 1500) {
Michael Chanb6016b72005-05-26 13:03:09 -07002041 /* Set extended packet length bit */
2042 bnx2_write_phy(bp, 0x18, 0x7);
2043 bnx2_read_phy(bp, 0x18, &val);
2044 bnx2_write_phy(bp, 0x18, val | 0x4000);
2045
2046 bnx2_read_phy(bp, 0x10, &val);
2047 bnx2_write_phy(bp, 0x10, val | 0x1);
2048 }
2049 else {
Michael Chanb6016b72005-05-26 13:03:09 -07002050 bnx2_write_phy(bp, 0x18, 0x7);
2051 bnx2_read_phy(bp, 0x18, &val);
2052 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2053
2054 bnx2_read_phy(bp, 0x10, &val);
2055 bnx2_write_phy(bp, 0x10, val & ~0x1);
2056 }
2057
Michael Chan5b0c76a2005-11-04 08:45:49 -08002058 /* ethernet@wirespeed */
2059 bnx2_write_phy(bp, 0x18, 0x7007);
2060 bnx2_read_phy(bp, 0x18, &val);
2061 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
Michael Chanb6016b72005-05-26 13:03:09 -07002062 return 0;
2063}
2064
2065
2066static int
2067bnx2_init_phy(struct bnx2 *bp)
2068{
2069 u32 val;
2070 int rc = 0;
2071
Michael Chan583c28e2008-01-21 19:51:35 -08002072 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2073 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
Michael Chanb6016b72005-05-26 13:03:09 -07002074
Michael Chanca58c3a2007-05-03 13:22:52 -07002075 bp->mii_bmcr = MII_BMCR;
2076 bp->mii_bmsr = MII_BMSR;
Michael Chan27a005b2007-05-03 13:23:41 -07002077 bp->mii_bmsr1 = MII_BMSR;
Michael Chanca58c3a2007-05-03 13:22:52 -07002078 bp->mii_adv = MII_ADVERTISE;
2079 bp->mii_lpa = MII_LPA;
2080
Michael Chanb6016b72005-05-26 13:03:09 -07002081 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2082
Michael Chan583c28e2008-01-21 19:51:35 -08002083 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -07002084 goto setup_phy;
2085
Michael Chanb6016b72005-05-26 13:03:09 -07002086 bnx2_read_phy(bp, MII_PHYSID1, &val);
2087 bp->phy_id = val << 16;
2088 bnx2_read_phy(bp, MII_PHYSID2, &val);
2089 bp->phy_id |= val & 0xffff;
2090
Michael Chan583c28e2008-01-21 19:51:35 -08002091 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08002092 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2093 rc = bnx2_init_5706s_phy(bp);
2094 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2095 rc = bnx2_init_5708s_phy(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07002096 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2097 rc = bnx2_init_5709s_phy(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07002098 }
2099 else {
2100 rc = bnx2_init_copper_phy(bp);
2101 }
2102
Michael Chan0d8a6572007-07-07 22:49:43 -07002103setup_phy:
2104 if (!rc)
2105 rc = bnx2_setup_phy(bp, bp->phy_port);
Michael Chanb6016b72005-05-26 13:03:09 -07002106
2107 return rc;
2108}
2109
2110static int
2111bnx2_set_mac_loopback(struct bnx2 *bp)
2112{
2113 u32 mac_mode;
2114
2115 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2116 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2117 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2118 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2119 bp->link_up = 1;
2120 return 0;
2121}
2122
Michael Chanbc5a0692006-01-23 16:13:22 -08002123static int bnx2_test_link(struct bnx2 *);
2124
2125static int
2126bnx2_set_phy_loopback(struct bnx2 *bp)
2127{
2128 u32 mac_mode;
2129 int rc, i;
2130
2131 spin_lock_bh(&bp->phy_lock);
Michael Chanca58c3a2007-05-03 13:22:52 -07002132 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
Michael Chanbc5a0692006-01-23 16:13:22 -08002133 BMCR_SPEED1000);
2134 spin_unlock_bh(&bp->phy_lock);
2135 if (rc)
2136 return rc;
2137
2138 for (i = 0; i < 10; i++) {
2139 if (bnx2_test_link(bp) == 0)
2140 break;
Michael Chan80be4432006-11-19 14:07:28 -08002141 msleep(100);
Michael Chanbc5a0692006-01-23 16:13:22 -08002142 }
2143
2144 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2145 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2146 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
Michael Chan59b47d82006-11-19 14:10:45 -08002147 BNX2_EMAC_MODE_25G_MODE);
Michael Chanbc5a0692006-01-23 16:13:22 -08002148
2149 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2150 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2151 bp->link_up = 1;
2152 return 0;
2153}
2154
Michael Chanb6016b72005-05-26 13:03:09 -07002155static int
Michael Chanb090ae22006-01-23 16:07:10 -08002156bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
Michael Chanb6016b72005-05-26 13:03:09 -07002157{
2158 int i;
2159 u32 val;
2160
Michael Chanb6016b72005-05-26 13:03:09 -07002161 bp->fw_wr_seq++;
2162 msg_data |= bp->fw_wr_seq;
2163
Michael Chan2726d6e2008-01-29 21:35:05 -08002164 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
Michael Chanb6016b72005-05-26 13:03:09 -07002165
2166 /* wait for an acknowledgement. */
Michael Chanb090ae22006-01-23 16:07:10 -08002167 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2168 msleep(10);
Michael Chanb6016b72005-05-26 13:03:09 -07002169
Michael Chan2726d6e2008-01-29 21:35:05 -08002170 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
Michael Chanb6016b72005-05-26 13:03:09 -07002171
2172 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2173 break;
2174 }
Michael Chanb090ae22006-01-23 16:07:10 -08002175 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2176 return 0;
Michael Chanb6016b72005-05-26 13:03:09 -07002177
2178 /* If we timed out, inform the firmware that this is the case. */
Michael Chanb090ae22006-01-23 16:07:10 -08002179 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2180 if (!silent)
2181 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2182 "%x\n", msg_data);
Michael Chanb6016b72005-05-26 13:03:09 -07002183
2184 msg_data &= ~BNX2_DRV_MSG_CODE;
2185 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2186
Michael Chan2726d6e2008-01-29 21:35:05 -08002187 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
Michael Chanb6016b72005-05-26 13:03:09 -07002188
Michael Chanb6016b72005-05-26 13:03:09 -07002189 return -EBUSY;
2190 }
2191
Michael Chanb090ae22006-01-23 16:07:10 -08002192 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2193 return -EIO;
2194
Michael Chanb6016b72005-05-26 13:03:09 -07002195 return 0;
2196}
2197
Michael Chan59b47d82006-11-19 14:10:45 -08002198static int
2199bnx2_init_5709_context(struct bnx2 *bp)
2200{
2201 int i, ret = 0;
2202 u32 val;
2203
2204 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2205 val |= (BCM_PAGE_BITS - 8) << 16;
2206 REG_WR(bp, BNX2_CTX_COMMAND, val);
Michael Chan641bdcd2007-06-04 21:22:24 -07002207 for (i = 0; i < 10; i++) {
2208 val = REG_RD(bp, BNX2_CTX_COMMAND);
2209 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2210 break;
2211 udelay(2);
2212 }
2213 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2214 return -EBUSY;
2215
Michael Chan59b47d82006-11-19 14:10:45 -08002216 for (i = 0; i < bp->ctx_pages; i++) {
2217 int j;
2218
2219 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2220 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2221 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2222 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2223 (u64) bp->ctx_blk_mapping[i] >> 32);
2224 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2225 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2226 for (j = 0; j < 10; j++) {
2227
2228 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2229 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2230 break;
2231 udelay(5);
2232 }
2233 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2234 ret = -EBUSY;
2235 break;
2236 }
2237 }
2238 return ret;
2239}
2240
Michael Chanb6016b72005-05-26 13:03:09 -07002241static void
2242bnx2_init_context(struct bnx2 *bp)
2243{
2244 u32 vcid;
2245
2246 vcid = 96;
2247 while (vcid) {
2248 u32 vcid_addr, pcid_addr, offset;
Michael Chan7947b202007-06-04 21:17:10 -07002249 int i;
Michael Chanb6016b72005-05-26 13:03:09 -07002250
2251 vcid--;
2252
2253 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2254 u32 new_vcid;
2255
2256 vcid_addr = GET_PCID_ADDR(vcid);
2257 if (vcid & 0x8) {
2258 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2259 }
2260 else {
2261 new_vcid = vcid;
2262 }
2263 pcid_addr = GET_PCID_ADDR(new_vcid);
2264 }
2265 else {
2266 vcid_addr = GET_CID_ADDR(vcid);
2267 pcid_addr = vcid_addr;
2268 }
2269
Michael Chan7947b202007-06-04 21:17:10 -07002270 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2271 vcid_addr += (i << PHY_CTX_SHIFT);
2272 pcid_addr += (i << PHY_CTX_SHIFT);
Michael Chanb6016b72005-05-26 13:03:09 -07002273
Michael Chan5d5d0012007-12-12 11:17:43 -08002274 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
Michael Chan7947b202007-06-04 21:17:10 -07002275 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2276
2277 /* Zero out the context. */
2278 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
Michael Chan62a83132008-01-29 21:35:40 -08002279 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07002280 }
Michael Chanb6016b72005-05-26 13:03:09 -07002281 }
2282}
2283
2284static int
2285bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2286{
2287 u16 *good_mbuf;
2288 u32 good_mbuf_cnt;
2289 u32 val;
2290
2291 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2292 if (good_mbuf == NULL) {
2293 printk(KERN_ERR PFX "Failed to allocate memory in "
2294 "bnx2_alloc_bad_rbuf\n");
2295 return -ENOMEM;
2296 }
2297
2298 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2299 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2300
2301 good_mbuf_cnt = 0;
2302
2303 /* Allocate a bunch of mbufs and save the good ones in an array. */
Michael Chan2726d6e2008-01-29 21:35:05 -08002304 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
Michael Chanb6016b72005-05-26 13:03:09 -07002305 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
Michael Chan2726d6e2008-01-29 21:35:05 -08002306 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2307 BNX2_RBUF_COMMAND_ALLOC_REQ);
Michael Chanb6016b72005-05-26 13:03:09 -07002308
Michael Chan2726d6e2008-01-29 21:35:05 -08002309 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
Michael Chanb6016b72005-05-26 13:03:09 -07002310
2311 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2312
2313 /* The addresses with Bit 9 set are bad memory blocks. */
2314 if (!(val & (1 << 9))) {
2315 good_mbuf[good_mbuf_cnt] = (u16) val;
2316 good_mbuf_cnt++;
2317 }
2318
Michael Chan2726d6e2008-01-29 21:35:05 -08002319 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
Michael Chanb6016b72005-05-26 13:03:09 -07002320 }
2321
2322 /* Free the good ones back to the mbuf pool thus discarding
2323 * all the bad ones. */
2324 while (good_mbuf_cnt) {
2325 good_mbuf_cnt--;
2326
2327 val = good_mbuf[good_mbuf_cnt];
2328 val = (val << 9) | val | 1;
2329
Michael Chan2726d6e2008-01-29 21:35:05 -08002330 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
Michael Chanb6016b72005-05-26 13:03:09 -07002331 }
2332 kfree(good_mbuf);
2333 return 0;
2334}
2335
2336static void
Jeff Garzik6aa20a22006-09-13 13:24:59 -04002337bnx2_set_mac_addr(struct bnx2 *bp)
Michael Chanb6016b72005-05-26 13:03:09 -07002338{
2339 u32 val;
2340 u8 *mac_addr = bp->dev->dev_addr;
2341
2342 val = (mac_addr[0] << 8) | mac_addr[1];
2343
2344 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
2345
Jeff Garzik6aa20a22006-09-13 13:24:59 -04002346 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
Michael Chanb6016b72005-05-26 13:03:09 -07002347 (mac_addr[4] << 8) | mac_addr[5];
2348
2349 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
2350}
2351
2352static inline int
Michael Chan47bf4242007-12-12 11:19:12 -08002353bnx2_alloc_rx_page(struct bnx2 *bp, u16 index)
2354{
2355 dma_addr_t mapping;
2356 struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
2357 struct rx_bd *rxbd =
2358 &bp->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2359 struct page *page = alloc_page(GFP_ATOMIC);
2360
2361 if (!page)
2362 return -ENOMEM;
2363 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2364 PCI_DMA_FROMDEVICE);
2365 rx_pg->page = page;
2366 pci_unmap_addr_set(rx_pg, mapping, mapping);
2367 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2368 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2369 return 0;
2370}
2371
2372static void
2373bnx2_free_rx_page(struct bnx2 *bp, u16 index)
2374{
2375 struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
2376 struct page *page = rx_pg->page;
2377
2378 if (!page)
2379 return;
2380
2381 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2382 PCI_DMA_FROMDEVICE);
2383
2384 __free_page(page);
2385 rx_pg->page = NULL;
2386}
2387
2388static inline int
Michael Chana1f60192007-12-20 19:57:19 -08002389bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, u16 index)
Michael Chanb6016b72005-05-26 13:03:09 -07002390{
2391 struct sk_buff *skb;
2392 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
2393 dma_addr_t mapping;
Michael Chan13daffa2006-03-20 17:49:20 -08002394 struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
Michael Chanb6016b72005-05-26 13:03:09 -07002395 unsigned long align;
2396
Michael Chan932f3772006-08-15 01:39:36 -07002397 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
Michael Chanb6016b72005-05-26 13:03:09 -07002398 if (skb == NULL) {
2399 return -ENOMEM;
2400 }
2401
Michael Chan59b47d82006-11-19 14:10:45 -08002402 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2403 skb_reserve(skb, BNX2_RX_ALIGN - align);
Michael Chanb6016b72005-05-26 13:03:09 -07002404
Michael Chanb6016b72005-05-26 13:03:09 -07002405 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2406 PCI_DMA_FROMDEVICE);
2407
2408 rx_buf->skb = skb;
2409 pci_unmap_addr_set(rx_buf, mapping, mapping);
2410
2411 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2412 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2413
Michael Chana1f60192007-12-20 19:57:19 -08002414 bnapi->rx_prod_bseq += bp->rx_buf_use_size;
Michael Chanb6016b72005-05-26 13:03:09 -07002415
2416 return 0;
2417}
2418
Michael Chanda3e4fb2007-05-03 13:24:23 -07002419static int
Michael Chan35efa7c2007-12-20 19:56:37 -08002420bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
Michael Chanda3e4fb2007-05-03 13:24:23 -07002421{
Michael Chan35efa7c2007-12-20 19:56:37 -08002422 struct status_block *sblk = bnapi->status_blk;
Michael Chanda3e4fb2007-05-03 13:24:23 -07002423 u32 new_link_state, old_link_state;
2424 int is_set = 1;
2425
2426 new_link_state = sblk->status_attn_bits & event;
2427 old_link_state = sblk->status_attn_bits_ack & event;
2428 if (new_link_state != old_link_state) {
2429 if (new_link_state)
2430 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2431 else
2432 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2433 } else
2434 is_set = 0;
2435
2436 return is_set;
2437}
2438
Michael Chanb6016b72005-05-26 13:03:09 -07002439static void
Michael Chan35efa7c2007-12-20 19:56:37 -08002440bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
Michael Chanb6016b72005-05-26 13:03:09 -07002441{
Michael Chan35efa7c2007-12-20 19:56:37 -08002442 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE)) {
Michael Chanda3e4fb2007-05-03 13:24:23 -07002443 spin_lock(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07002444 bnx2_set_link(bp);
Michael Chanda3e4fb2007-05-03 13:24:23 -07002445 spin_unlock(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07002446 }
Michael Chan35efa7c2007-12-20 19:56:37 -08002447 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
Michael Chan0d8a6572007-07-07 22:49:43 -07002448 bnx2_set_remote_link(bp);
2449
Michael Chanb6016b72005-05-26 13:03:09 -07002450}
2451
Michael Chanead72702007-12-20 19:55:39 -08002452static inline u16
Michael Chan35efa7c2007-12-20 19:56:37 -08002453bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
Michael Chanead72702007-12-20 19:55:39 -08002454{
2455 u16 cons;
2456
Michael Chanc76c0472007-12-20 20:01:19 -08002457 if (bnapi->int_num == 0)
2458 cons = bnapi->status_blk->status_tx_quick_consumer_index0;
2459 else
2460 cons = bnapi->status_blk_msix->status_tx_quick_consumer_index;
Michael Chanead72702007-12-20 19:55:39 -08002461
2462 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2463 cons++;
2464 return cons;
2465}
2466
Michael Chan57851d82007-12-20 20:01:44 -08002467static int
2468bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
Michael Chanb6016b72005-05-26 13:03:09 -07002469{
2470 u16 hw_cons, sw_cons, sw_ring_cons;
Michael Chan57851d82007-12-20 20:01:44 -08002471 int tx_pkt = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07002472
Michael Chan35efa7c2007-12-20 19:56:37 -08002473 hw_cons = bnx2_get_hw_tx_cons(bnapi);
Michael Chana550c992007-12-20 19:56:59 -08002474 sw_cons = bnapi->tx_cons;
Michael Chanb6016b72005-05-26 13:03:09 -07002475
2476 while (sw_cons != hw_cons) {
2477 struct sw_bd *tx_buf;
2478 struct sk_buff *skb;
2479 int i, last;
2480
2481 sw_ring_cons = TX_RING_IDX(sw_cons);
2482
2483 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
2484 skb = tx_buf->skb;
Arjan van de Ven1d39ed52006-12-12 14:06:23 +01002485
Michael Chanb6016b72005-05-26 13:03:09 -07002486 /* partial BD completions possible with TSO packets */
Herbert Xu89114af2006-07-08 13:34:32 -07002487 if (skb_is_gso(skb)) {
Michael Chanb6016b72005-05-26 13:03:09 -07002488 u16 last_idx, last_ring_idx;
2489
2490 last_idx = sw_cons +
2491 skb_shinfo(skb)->nr_frags + 1;
2492 last_ring_idx = sw_ring_cons +
2493 skb_shinfo(skb)->nr_frags + 1;
2494 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2495 last_idx++;
2496 }
2497 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2498 break;
2499 }
2500 }
Arjan van de Ven1d39ed52006-12-12 14:06:23 +01002501
Michael Chanb6016b72005-05-26 13:03:09 -07002502 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2503 skb_headlen(skb), PCI_DMA_TODEVICE);
2504
2505 tx_buf->skb = NULL;
2506 last = skb_shinfo(skb)->nr_frags;
2507
2508 for (i = 0; i < last; i++) {
2509 sw_cons = NEXT_TX_BD(sw_cons);
2510
2511 pci_unmap_page(bp->pdev,
2512 pci_unmap_addr(
2513 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
2514 mapping),
2515 skb_shinfo(skb)->frags[i].size,
2516 PCI_DMA_TODEVICE);
2517 }
2518
2519 sw_cons = NEXT_TX_BD(sw_cons);
2520
Michael Chan745720e2006-06-29 12:37:41 -07002521 dev_kfree_skb(skb);
Michael Chan57851d82007-12-20 20:01:44 -08002522 tx_pkt++;
2523 if (tx_pkt == budget)
2524 break;
Michael Chanb6016b72005-05-26 13:03:09 -07002525
Michael Chan35efa7c2007-12-20 19:56:37 -08002526 hw_cons = bnx2_get_hw_tx_cons(bnapi);
Michael Chanb6016b72005-05-26 13:03:09 -07002527 }
2528
Michael Chana550c992007-12-20 19:56:59 -08002529 bnapi->hw_tx_cons = hw_cons;
2530 bnapi->tx_cons = sw_cons;
Michael Chan2f8af122006-08-15 01:39:10 -07002531 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2532 * before checking for netif_queue_stopped(). Without the
2533 * memory barrier, there is a small possibility that bnx2_start_xmit()
2534 * will miss it and cause the queue to be stopped forever.
2535 */
2536 smp_mb();
Michael Chanb6016b72005-05-26 13:03:09 -07002537
Michael Chan2f8af122006-08-15 01:39:10 -07002538 if (unlikely(netif_queue_stopped(bp->dev)) &&
Michael Chana550c992007-12-20 19:56:59 -08002539 (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)) {
Michael Chan2f8af122006-08-15 01:39:10 -07002540 netif_tx_lock(bp->dev);
Michael Chanb6016b72005-05-26 13:03:09 -07002541 if ((netif_queue_stopped(bp->dev)) &&
Michael Chana550c992007-12-20 19:56:59 -08002542 (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh))
Michael Chanb6016b72005-05-26 13:03:09 -07002543 netif_wake_queue(bp->dev);
Michael Chan2f8af122006-08-15 01:39:10 -07002544 netif_tx_unlock(bp->dev);
Michael Chanb6016b72005-05-26 13:03:09 -07002545 }
Michael Chan57851d82007-12-20 20:01:44 -08002546 return tx_pkt;
Michael Chanb6016b72005-05-26 13:03:09 -07002547}
2548
Michael Chan1db82f22007-12-12 11:19:35 -08002549static void
Michael Chana1f60192007-12-20 19:57:19 -08002550bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_napi *bnapi,
2551 struct sk_buff *skb, int count)
Michael Chan1db82f22007-12-12 11:19:35 -08002552{
2553 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2554 struct rx_bd *cons_bd, *prod_bd;
2555 dma_addr_t mapping;
2556 int i;
Michael Chana1f60192007-12-20 19:57:19 -08002557 u16 hw_prod = bnapi->rx_pg_prod, prod;
2558 u16 cons = bnapi->rx_pg_cons;
Michael Chan1db82f22007-12-12 11:19:35 -08002559
2560 for (i = 0; i < count; i++) {
2561 prod = RX_PG_RING_IDX(hw_prod);
2562
2563 prod_rx_pg = &bp->rx_pg_ring[prod];
2564 cons_rx_pg = &bp->rx_pg_ring[cons];
2565 cons_bd = &bp->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2566 prod_bd = &bp->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2567
2568 if (i == 0 && skb) {
2569 struct page *page;
2570 struct skb_shared_info *shinfo;
2571
2572 shinfo = skb_shinfo(skb);
2573 shinfo->nr_frags--;
2574 page = shinfo->frags[shinfo->nr_frags].page;
2575 shinfo->frags[shinfo->nr_frags].page = NULL;
2576 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2577 PCI_DMA_FROMDEVICE);
2578 cons_rx_pg->page = page;
2579 pci_unmap_addr_set(cons_rx_pg, mapping, mapping);
2580 dev_kfree_skb(skb);
2581 }
2582 if (prod != cons) {
2583 prod_rx_pg->page = cons_rx_pg->page;
2584 cons_rx_pg->page = NULL;
2585 pci_unmap_addr_set(prod_rx_pg, mapping,
2586 pci_unmap_addr(cons_rx_pg, mapping));
2587
2588 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2589 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2590
2591 }
2592 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2593 hw_prod = NEXT_RX_BD(hw_prod);
2594 }
Michael Chana1f60192007-12-20 19:57:19 -08002595 bnapi->rx_pg_prod = hw_prod;
2596 bnapi->rx_pg_cons = cons;
Michael Chan1db82f22007-12-12 11:19:35 -08002597}
2598
Michael Chanb6016b72005-05-26 13:03:09 -07002599static inline void
Michael Chana1f60192007-12-20 19:57:19 -08002600bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
Michael Chanb6016b72005-05-26 13:03:09 -07002601 u16 cons, u16 prod)
2602{
Michael Chan236b6392006-03-20 17:49:02 -08002603 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2604 struct rx_bd *cons_bd, *prod_bd;
2605
2606 cons_rx_buf = &bp->rx_buf_ring[cons];
2607 prod_rx_buf = &bp->rx_buf_ring[prod];
Michael Chanb6016b72005-05-26 13:03:09 -07002608
2609 pci_dma_sync_single_for_device(bp->pdev,
2610 pci_unmap_addr(cons_rx_buf, mapping),
2611 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2612
Michael Chana1f60192007-12-20 19:57:19 -08002613 bnapi->rx_prod_bseq += bp->rx_buf_use_size;
Michael Chan236b6392006-03-20 17:49:02 -08002614
2615 prod_rx_buf->skb = skb;
2616
2617 if (cons == prod)
2618 return;
2619
Michael Chanb6016b72005-05-26 13:03:09 -07002620 pci_unmap_addr_set(prod_rx_buf, mapping,
2621 pci_unmap_addr(cons_rx_buf, mapping));
2622
Michael Chan3fdfcc22006-03-20 17:49:49 -08002623 cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2624 prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
Michael Chan236b6392006-03-20 17:49:02 -08002625 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2626 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
Michael Chanb6016b72005-05-26 13:03:09 -07002627}
2628
Michael Chan85833c62007-12-12 11:17:01 -08002629static int
Michael Chana1f60192007-12-20 19:57:19 -08002630bnx2_rx_skb(struct bnx2 *bp, struct bnx2_napi *bnapi, struct sk_buff *skb,
2631 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2632 u32 ring_idx)
Michael Chan85833c62007-12-12 11:17:01 -08002633{
2634 int err;
2635 u16 prod = ring_idx & 0xffff;
2636
Michael Chana1f60192007-12-20 19:57:19 -08002637 err = bnx2_alloc_rx_skb(bp, bnapi, prod);
Michael Chan85833c62007-12-12 11:17:01 -08002638 if (unlikely(err)) {
Michael Chana1f60192007-12-20 19:57:19 -08002639 bnx2_reuse_rx_skb(bp, bnapi, skb, (u16) (ring_idx >> 16), prod);
Michael Chan1db82f22007-12-12 11:19:35 -08002640 if (hdr_len) {
2641 unsigned int raw_len = len + 4;
2642 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2643
Michael Chana1f60192007-12-20 19:57:19 -08002644 bnx2_reuse_rx_skb_pages(bp, bnapi, NULL, pages);
Michael Chan1db82f22007-12-12 11:19:35 -08002645 }
Michael Chan85833c62007-12-12 11:17:01 -08002646 return err;
2647 }
2648
2649 skb_reserve(skb, bp->rx_offset);
2650 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2651 PCI_DMA_FROMDEVICE);
2652
Michael Chan1db82f22007-12-12 11:19:35 -08002653 if (hdr_len == 0) {
2654 skb_put(skb, len);
2655 return 0;
2656 } else {
2657 unsigned int i, frag_len, frag_size, pages;
2658 struct sw_pg *rx_pg;
Michael Chana1f60192007-12-20 19:57:19 -08002659 u16 pg_cons = bnapi->rx_pg_cons;
2660 u16 pg_prod = bnapi->rx_pg_prod;
Michael Chan1db82f22007-12-12 11:19:35 -08002661
2662 frag_size = len + 4 - hdr_len;
2663 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2664 skb_put(skb, hdr_len);
2665
2666 for (i = 0; i < pages; i++) {
2667 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2668 if (unlikely(frag_len <= 4)) {
2669 unsigned int tail = 4 - frag_len;
2670
Michael Chana1f60192007-12-20 19:57:19 -08002671 bnapi->rx_pg_cons = pg_cons;
2672 bnapi->rx_pg_prod = pg_prod;
2673 bnx2_reuse_rx_skb_pages(bp, bnapi, NULL,
2674 pages - i);
Michael Chan1db82f22007-12-12 11:19:35 -08002675 skb->len -= tail;
2676 if (i == 0) {
2677 skb->tail -= tail;
2678 } else {
2679 skb_frag_t *frag =
2680 &skb_shinfo(skb)->frags[i - 1];
2681 frag->size -= tail;
2682 skb->data_len -= tail;
2683 skb->truesize -= tail;
2684 }
2685 return 0;
2686 }
2687 rx_pg = &bp->rx_pg_ring[pg_cons];
2688
2689 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping),
2690 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2691
2692 if (i == pages - 1)
2693 frag_len -= 4;
2694
2695 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2696 rx_pg->page = NULL;
2697
2698 err = bnx2_alloc_rx_page(bp, RX_PG_RING_IDX(pg_prod));
2699 if (unlikely(err)) {
Michael Chana1f60192007-12-20 19:57:19 -08002700 bnapi->rx_pg_cons = pg_cons;
2701 bnapi->rx_pg_prod = pg_prod;
2702 bnx2_reuse_rx_skb_pages(bp, bnapi, skb,
2703 pages - i);
Michael Chan1db82f22007-12-12 11:19:35 -08002704 return err;
2705 }
2706
2707 frag_size -= frag_len;
2708 skb->data_len += frag_len;
2709 skb->truesize += frag_len;
2710 skb->len += frag_len;
2711
2712 pg_prod = NEXT_RX_BD(pg_prod);
2713 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2714 }
Michael Chana1f60192007-12-20 19:57:19 -08002715 bnapi->rx_pg_prod = pg_prod;
2716 bnapi->rx_pg_cons = pg_cons;
Michael Chan1db82f22007-12-12 11:19:35 -08002717 }
Michael Chan85833c62007-12-12 11:17:01 -08002718 return 0;
2719}
2720
Michael Chanc09c2622007-12-10 17:18:37 -08002721static inline u16
Michael Chan35efa7c2007-12-20 19:56:37 -08002722bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
Michael Chanc09c2622007-12-10 17:18:37 -08002723{
Michael Chan35efa7c2007-12-20 19:56:37 -08002724 u16 cons = bnapi->status_blk->status_rx_quick_consumer_index0;
Michael Chanc09c2622007-12-10 17:18:37 -08002725
2726 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2727 cons++;
2728 return cons;
2729}
2730
Michael Chanb6016b72005-05-26 13:03:09 -07002731static int
Michael Chan35efa7c2007-12-20 19:56:37 -08002732bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
Michael Chanb6016b72005-05-26 13:03:09 -07002733{
2734 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2735 struct l2_fhdr *rx_hdr;
Michael Chan1db82f22007-12-12 11:19:35 -08002736 int rx_pkt = 0, pg_ring_used = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07002737
Michael Chan35efa7c2007-12-20 19:56:37 -08002738 hw_cons = bnx2_get_hw_rx_cons(bnapi);
Michael Chana1f60192007-12-20 19:57:19 -08002739 sw_cons = bnapi->rx_cons;
2740 sw_prod = bnapi->rx_prod;
Michael Chanb6016b72005-05-26 13:03:09 -07002741
2742 /* Memory barrier necessary as speculative reads of the rx
2743 * buffer can be ahead of the index in the status block
2744 */
2745 rmb();
2746 while (sw_cons != hw_cons) {
Michael Chan1db82f22007-12-12 11:19:35 -08002747 unsigned int len, hdr_len;
Michael Chanade2bfe2006-01-23 16:09:51 -08002748 u32 status;
Michael Chanb6016b72005-05-26 13:03:09 -07002749 struct sw_bd *rx_buf;
2750 struct sk_buff *skb;
Michael Chan236b6392006-03-20 17:49:02 -08002751 dma_addr_t dma_addr;
Michael Chanb6016b72005-05-26 13:03:09 -07002752
2753 sw_ring_cons = RX_RING_IDX(sw_cons);
2754 sw_ring_prod = RX_RING_IDX(sw_prod);
2755
2756 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
2757 skb = rx_buf->skb;
Michael Chan236b6392006-03-20 17:49:02 -08002758
2759 rx_buf->skb = NULL;
2760
2761 dma_addr = pci_unmap_addr(rx_buf, mapping);
2762
2763 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
Michael Chanb6016b72005-05-26 13:03:09 -07002764 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2765
2766 rx_hdr = (struct l2_fhdr *) skb->data;
Michael Chan1db82f22007-12-12 11:19:35 -08002767 len = rx_hdr->l2_fhdr_pkt_len;
Michael Chanb6016b72005-05-26 13:03:09 -07002768
Michael Chanade2bfe2006-01-23 16:09:51 -08002769 if ((status = rx_hdr->l2_fhdr_status) &
Michael Chanb6016b72005-05-26 13:03:09 -07002770 (L2_FHDR_ERRORS_BAD_CRC |
2771 L2_FHDR_ERRORS_PHY_DECODE |
2772 L2_FHDR_ERRORS_ALIGNMENT |
2773 L2_FHDR_ERRORS_TOO_SHORT |
2774 L2_FHDR_ERRORS_GIANT_FRAME)) {
2775
Michael Chana1f60192007-12-20 19:57:19 -08002776 bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons,
2777 sw_ring_prod);
Michael Chan85833c62007-12-12 11:17:01 -08002778 goto next_rx;
Michael Chanb6016b72005-05-26 13:03:09 -07002779 }
Michael Chan1db82f22007-12-12 11:19:35 -08002780 hdr_len = 0;
2781 if (status & L2_FHDR_STATUS_SPLIT) {
2782 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2783 pg_ring_used = 1;
2784 } else if (len > bp->rx_jumbo_thresh) {
2785 hdr_len = bp->rx_jumbo_thresh;
2786 pg_ring_used = 1;
2787 }
2788
2789 len -= 4;
Michael Chanb6016b72005-05-26 13:03:09 -07002790
Michael Chan5d5d0012007-12-12 11:17:43 -08002791 if (len <= bp->rx_copy_thresh) {
Michael Chanb6016b72005-05-26 13:03:09 -07002792 struct sk_buff *new_skb;
2793
Michael Chan932f3772006-08-15 01:39:36 -07002794 new_skb = netdev_alloc_skb(bp->dev, len + 2);
Michael Chan85833c62007-12-12 11:17:01 -08002795 if (new_skb == NULL) {
Michael Chana1f60192007-12-20 19:57:19 -08002796 bnx2_reuse_rx_skb(bp, bnapi, skb, sw_ring_cons,
Michael Chan85833c62007-12-12 11:17:01 -08002797 sw_ring_prod);
2798 goto next_rx;
2799 }
Michael Chanb6016b72005-05-26 13:03:09 -07002800
2801 /* aligned copy */
Arnaldo Carvalho de Melod626f622007-03-27 18:55:52 -03002802 skb_copy_from_linear_data_offset(skb, bp->rx_offset - 2,
2803 new_skb->data, len + 2);
Michael Chanb6016b72005-05-26 13:03:09 -07002804 skb_reserve(new_skb, 2);
2805 skb_put(new_skb, len);
Michael Chanb6016b72005-05-26 13:03:09 -07002806
Michael Chana1f60192007-12-20 19:57:19 -08002807 bnx2_reuse_rx_skb(bp, bnapi, skb,
Michael Chanb6016b72005-05-26 13:03:09 -07002808 sw_ring_cons, sw_ring_prod);
2809
2810 skb = new_skb;
Michael Chana1f60192007-12-20 19:57:19 -08002811 } else if (unlikely(bnx2_rx_skb(bp, bnapi, skb, len, hdr_len,
2812 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
Michael Chanb6016b72005-05-26 13:03:09 -07002813 goto next_rx;
Michael Chanb6016b72005-05-26 13:03:09 -07002814
2815 skb->protocol = eth_type_trans(skb, bp->dev);
2816
2817 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
Alexey Dobriyand1e100b2006-06-11 20:57:17 -07002818 (ntohs(skb->protocol) != 0x8100)) {
Michael Chanb6016b72005-05-26 13:03:09 -07002819
Michael Chan745720e2006-06-29 12:37:41 -07002820 dev_kfree_skb(skb);
Michael Chanb6016b72005-05-26 13:03:09 -07002821 goto next_rx;
2822
2823 }
2824
Michael Chanb6016b72005-05-26 13:03:09 -07002825 skb->ip_summed = CHECKSUM_NONE;
2826 if (bp->rx_csum &&
2827 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2828 L2_FHDR_STATUS_UDP_DATAGRAM))) {
2829
Michael Chanade2bfe2006-01-23 16:09:51 -08002830 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2831 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
Michael Chanb6016b72005-05-26 13:03:09 -07002832 skb->ip_summed = CHECKSUM_UNNECESSARY;
2833 }
2834
2835#ifdef BCM_VLAN
Al Viro79ea13c2008-01-24 02:06:46 -08002836 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && bp->vlgrp) {
Michael Chanb6016b72005-05-26 13:03:09 -07002837 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
2838 rx_hdr->l2_fhdr_vlan_tag);
2839 }
2840 else
2841#endif
2842 netif_receive_skb(skb);
2843
2844 bp->dev->last_rx = jiffies;
2845 rx_pkt++;
2846
2847next_rx:
Michael Chanb6016b72005-05-26 13:03:09 -07002848 sw_cons = NEXT_RX_BD(sw_cons);
2849 sw_prod = NEXT_RX_BD(sw_prod);
2850
2851 if ((rx_pkt == budget))
2852 break;
Michael Chanf4e418f2005-11-04 08:53:48 -08002853
2854 /* Refresh hw_cons to see if there is new work */
2855 if (sw_cons == hw_cons) {
Michael Chan35efa7c2007-12-20 19:56:37 -08002856 hw_cons = bnx2_get_hw_rx_cons(bnapi);
Michael Chanf4e418f2005-11-04 08:53:48 -08002857 rmb();
2858 }
Michael Chanb6016b72005-05-26 13:03:09 -07002859 }
Michael Chana1f60192007-12-20 19:57:19 -08002860 bnapi->rx_cons = sw_cons;
2861 bnapi->rx_prod = sw_prod;
Michael Chanb6016b72005-05-26 13:03:09 -07002862
Michael Chan1db82f22007-12-12 11:19:35 -08002863 if (pg_ring_used)
2864 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX,
Michael Chana1f60192007-12-20 19:57:19 -08002865 bnapi->rx_pg_prod);
Michael Chan1db82f22007-12-12 11:19:35 -08002866
Michael Chanb6016b72005-05-26 13:03:09 -07002867 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
2868
Michael Chana1f60192007-12-20 19:57:19 -08002869 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq);
Michael Chanb6016b72005-05-26 13:03:09 -07002870
2871 mmiowb();
2872
2873 return rx_pkt;
2874
2875}
2876
2877/* MSI ISR - The only difference between this and the INTx ISR
2878 * is that the MSI interrupt is always serviced.
2879 */
2880static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +01002881bnx2_msi(int irq, void *dev_instance)
Michael Chanb6016b72005-05-26 13:03:09 -07002882{
2883 struct net_device *dev = dev_instance;
Michael Chan972ec0d2006-01-23 16:12:43 -08002884 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb4b36042007-12-20 19:59:30 -08002885 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
Michael Chanb6016b72005-05-26 13:03:09 -07002886
Michael Chan35efa7c2007-12-20 19:56:37 -08002887 prefetch(bnapi->status_blk);
Michael Chanb6016b72005-05-26 13:03:09 -07002888 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2889 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2890 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2891
2892 /* Return here if interrupt is disabled. */
Michael Chan73eef4c2005-08-25 15:39:15 -07002893 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2894 return IRQ_HANDLED;
Michael Chanb6016b72005-05-26 13:03:09 -07002895
Michael Chan35efa7c2007-12-20 19:56:37 -08002896 netif_rx_schedule(dev, &bnapi->napi);
Michael Chanb6016b72005-05-26 13:03:09 -07002897
Michael Chan73eef4c2005-08-25 15:39:15 -07002898 return IRQ_HANDLED;
Michael Chanb6016b72005-05-26 13:03:09 -07002899}
2900
2901static irqreturn_t
Michael Chan8e6a72c2007-05-03 13:24:48 -07002902bnx2_msi_1shot(int irq, void *dev_instance)
2903{
2904 struct net_device *dev = dev_instance;
2905 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb4b36042007-12-20 19:59:30 -08002906 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
Michael Chan8e6a72c2007-05-03 13:24:48 -07002907
Michael Chan35efa7c2007-12-20 19:56:37 -08002908 prefetch(bnapi->status_blk);
Michael Chan8e6a72c2007-05-03 13:24:48 -07002909
2910 /* Return here if interrupt is disabled. */
2911 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2912 return IRQ_HANDLED;
2913
Michael Chan35efa7c2007-12-20 19:56:37 -08002914 netif_rx_schedule(dev, &bnapi->napi);
Michael Chan8e6a72c2007-05-03 13:24:48 -07002915
2916 return IRQ_HANDLED;
2917}
2918
2919static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +01002920bnx2_interrupt(int irq, void *dev_instance)
Michael Chanb6016b72005-05-26 13:03:09 -07002921{
2922 struct net_device *dev = dev_instance;
Michael Chan972ec0d2006-01-23 16:12:43 -08002923 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb4b36042007-12-20 19:59:30 -08002924 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
Michael Chan35efa7c2007-12-20 19:56:37 -08002925 struct status_block *sblk = bnapi->status_blk;
Michael Chanb6016b72005-05-26 13:03:09 -07002926
2927 /* When using INTx, it is possible for the interrupt to arrive
2928 * at the CPU before the status block posted prior to the
2929 * interrupt. Reading a register will flush the status block.
2930 * When using MSI, the MSI message will always complete after
2931 * the status block write.
2932 */
Michael Chan35efa7c2007-12-20 19:56:37 -08002933 if ((sblk->status_idx == bnapi->last_status_idx) &&
Michael Chanb6016b72005-05-26 13:03:09 -07002934 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2935 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
Michael Chan73eef4c2005-08-25 15:39:15 -07002936 return IRQ_NONE;
Michael Chanb6016b72005-05-26 13:03:09 -07002937
2938 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2939 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2940 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2941
Michael Chanb8a7ce72007-07-07 22:51:03 -07002942 /* Read back to deassert IRQ immediately to avoid too many
2943 * spurious interrupts.
2944 */
2945 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
2946
Michael Chanb6016b72005-05-26 13:03:09 -07002947 /* Return here if interrupt is shared and is disabled. */
Michael Chan73eef4c2005-08-25 15:39:15 -07002948 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2949 return IRQ_HANDLED;
Michael Chanb6016b72005-05-26 13:03:09 -07002950
Michael Chan35efa7c2007-12-20 19:56:37 -08002951 if (netif_rx_schedule_prep(dev, &bnapi->napi)) {
2952 bnapi->last_status_idx = sblk->status_idx;
2953 __netif_rx_schedule(dev, &bnapi->napi);
Michael Chanb8a7ce72007-07-07 22:51:03 -07002954 }
Michael Chanb6016b72005-05-26 13:03:09 -07002955
Michael Chan73eef4c2005-08-25 15:39:15 -07002956 return IRQ_HANDLED;
Michael Chanb6016b72005-05-26 13:03:09 -07002957}
2958
Michael Chan57851d82007-12-20 20:01:44 -08002959static irqreturn_t
2960bnx2_tx_msix(int irq, void *dev_instance)
2961{
2962 struct net_device *dev = dev_instance;
2963 struct bnx2 *bp = netdev_priv(dev);
2964 struct bnx2_napi *bnapi = &bp->bnx2_napi[BNX2_TX_VEC];
2965
2966 prefetch(bnapi->status_blk_msix);
2967
2968 /* Return here if interrupt is disabled. */
2969 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2970 return IRQ_HANDLED;
2971
2972 netif_rx_schedule(dev, &bnapi->napi);
2973 return IRQ_HANDLED;
2974}
2975
Michael Chan0d8a6572007-07-07 22:49:43 -07002976#define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
2977 STATUS_ATTN_BITS_TIMER_ABORT)
Michael Chanda3e4fb2007-05-03 13:24:23 -07002978
Michael Chanf4e418f2005-11-04 08:53:48 -08002979static inline int
Michael Chan35efa7c2007-12-20 19:56:37 -08002980bnx2_has_work(struct bnx2_napi *bnapi)
Michael Chanf4e418f2005-11-04 08:53:48 -08002981{
Michael Chan1097f5e2008-01-21 17:06:41 -08002982 struct status_block *sblk = bnapi->status_blk;
Michael Chanf4e418f2005-11-04 08:53:48 -08002983
Michael Chana1f60192007-12-20 19:57:19 -08002984 if ((bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons) ||
Michael Chana550c992007-12-20 19:56:59 -08002985 (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons))
Michael Chanf4e418f2005-11-04 08:53:48 -08002986 return 1;
2987
Michael Chanda3e4fb2007-05-03 13:24:23 -07002988 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
2989 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
Michael Chanf4e418f2005-11-04 08:53:48 -08002990 return 1;
2991
2992 return 0;
2993}
2994
Michael Chan57851d82007-12-20 20:01:44 -08002995static int bnx2_tx_poll(struct napi_struct *napi, int budget)
2996{
2997 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
2998 struct bnx2 *bp = bnapi->bp;
2999 int work_done = 0;
3000 struct status_block_msix *sblk = bnapi->status_blk_msix;
3001
3002 do {
3003 work_done += bnx2_tx_int(bp, bnapi, budget - work_done);
3004 if (unlikely(work_done >= budget))
3005 return work_done;
3006
3007 bnapi->last_status_idx = sblk->status_idx;
3008 rmb();
3009 } while (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons);
3010
3011 netif_rx_complete(bp->dev, napi);
3012 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3013 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3014 bnapi->last_status_idx);
3015 return work_done;
3016}
3017
Michael Chan35efa7c2007-12-20 19:56:37 -08003018static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3019 int work_done, int budget)
Michael Chanb6016b72005-05-26 13:03:09 -07003020{
Michael Chan35efa7c2007-12-20 19:56:37 -08003021 struct status_block *sblk = bnapi->status_blk;
Michael Chanda3e4fb2007-05-03 13:24:23 -07003022 u32 status_attn_bits = sblk->status_attn_bits;
3023 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
Michael Chanb6016b72005-05-26 13:03:09 -07003024
Michael Chanda3e4fb2007-05-03 13:24:23 -07003025 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3026 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
Michael Chanb6016b72005-05-26 13:03:09 -07003027
Michael Chan35efa7c2007-12-20 19:56:37 -08003028 bnx2_phy_int(bp, bnapi);
Michael Chanbf5295b2006-03-23 01:11:56 -08003029
3030 /* This is needed to take care of transient status
3031 * during link changes.
3032 */
3033 REG_WR(bp, BNX2_HC_COMMAND,
3034 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3035 REG_RD(bp, BNX2_HC_COMMAND);
Michael Chanb6016b72005-05-26 13:03:09 -07003036 }
3037
Michael Chana550c992007-12-20 19:56:59 -08003038 if (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons)
Michael Chan57851d82007-12-20 20:01:44 -08003039 bnx2_tx_int(bp, bnapi, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07003040
Michael Chana1f60192007-12-20 19:57:19 -08003041 if (bnx2_get_hw_rx_cons(bnapi) != bnapi->rx_cons)
Michael Chan35efa7c2007-12-20 19:56:37 -08003042 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04003043
David S. Miller6f535762007-10-11 18:08:29 -07003044 return work_done;
3045}
Michael Chanf4e418f2005-11-04 08:53:48 -08003046
David S. Miller6f535762007-10-11 18:08:29 -07003047static int bnx2_poll(struct napi_struct *napi, int budget)
3048{
Michael Chan35efa7c2007-12-20 19:56:37 -08003049 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3050 struct bnx2 *bp = bnapi->bp;
David S. Miller6f535762007-10-11 18:08:29 -07003051 int work_done = 0;
Michael Chan35efa7c2007-12-20 19:56:37 -08003052 struct status_block *sblk = bnapi->status_blk;
David S. Miller6f535762007-10-11 18:08:29 -07003053
3054 while (1) {
Michael Chan35efa7c2007-12-20 19:56:37 -08003055 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
David S. Miller6f535762007-10-11 18:08:29 -07003056
3057 if (unlikely(work_done >= budget))
3058 break;
3059
Michael Chan35efa7c2007-12-20 19:56:37 -08003060 /* bnapi->last_status_idx is used below to tell the hw how
Michael Chan6dee6422007-10-12 01:40:38 -07003061 * much work has been processed, so we must read it before
3062 * checking for more work.
3063 */
Michael Chan35efa7c2007-12-20 19:56:37 -08003064 bnapi->last_status_idx = sblk->status_idx;
Michael Chan6dee6422007-10-12 01:40:38 -07003065 rmb();
Michael Chan35efa7c2007-12-20 19:56:37 -08003066 if (likely(!bnx2_has_work(bnapi))) {
David S. Miller6f535762007-10-11 18:08:29 -07003067 netif_rx_complete(bp->dev, napi);
David S. Millerf86e82f2008-01-21 17:15:40 -08003068 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
David S. Miller6f535762007-10-11 18:08:29 -07003069 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3070 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
Michael Chan35efa7c2007-12-20 19:56:37 -08003071 bnapi->last_status_idx);
Michael Chan6dee6422007-10-12 01:40:38 -07003072 break;
David S. Miller6f535762007-10-11 18:08:29 -07003073 }
3074 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3075 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3076 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
Michael Chan35efa7c2007-12-20 19:56:37 -08003077 bnapi->last_status_idx);
David S. Miller6f535762007-10-11 18:08:29 -07003078
Michael Chan1269a8a2006-01-23 16:11:03 -08003079 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3080 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
Michael Chan35efa7c2007-12-20 19:56:37 -08003081 bnapi->last_status_idx);
David S. Miller6f535762007-10-11 18:08:29 -07003082 break;
Michael Chan1269a8a2006-01-23 16:11:03 -08003083 }
Michael Chanb6016b72005-05-26 13:03:09 -07003084 }
3085
Stephen Hemmingerbea33482007-10-03 16:41:36 -07003086 return work_done;
Michael Chanb6016b72005-05-26 13:03:09 -07003087}
3088
Herbert Xu932ff272006-06-09 12:20:56 -07003089/* Called with rtnl_lock from vlan functions and also netif_tx_lock
Michael Chanb6016b72005-05-26 13:03:09 -07003090 * from set_multicast.
3091 */
3092static void
3093bnx2_set_rx_mode(struct net_device *dev)
3094{
Michael Chan972ec0d2006-01-23 16:12:43 -08003095 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07003096 u32 rx_mode, sort_mode;
3097 int i;
Michael Chanb6016b72005-05-26 13:03:09 -07003098
Michael Chanc770a652005-08-25 15:38:39 -07003099 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07003100
3101 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3102 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3103 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3104#ifdef BCM_VLAN
David S. Millerf86e82f2008-01-21 17:15:40 -08003105 if (!bp->vlgrp && !(bp->flags & BNX2_FLAG_ASF_ENABLE))
Michael Chanb6016b72005-05-26 13:03:09 -07003106 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
Michael Chanb6016b72005-05-26 13:03:09 -07003107#else
David S. Millerf86e82f2008-01-21 17:15:40 -08003108 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
Michael Chane29054f2006-01-23 16:06:06 -08003109 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
Michael Chanb6016b72005-05-26 13:03:09 -07003110#endif
3111 if (dev->flags & IFF_PROMISC) {
3112 /* Promiscuous mode. */
3113 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
Michael Chan75108732006-11-19 14:06:40 -08003114 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3115 BNX2_RPM_SORT_USER0_PROM_VLAN;
Michael Chanb6016b72005-05-26 13:03:09 -07003116 }
3117 else if (dev->flags & IFF_ALLMULTI) {
3118 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3119 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3120 0xffffffff);
3121 }
3122 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3123 }
3124 else {
3125 /* Accept one or more multicast(s). */
3126 struct dev_mc_list *mclist;
3127 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3128 u32 regidx;
3129 u32 bit;
3130 u32 crc;
3131
3132 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3133
3134 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3135 i++, mclist = mclist->next) {
3136
3137 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3138 bit = crc & 0xff;
3139 regidx = (bit & 0xe0) >> 5;
3140 bit &= 0x1f;
3141 mc_filter[regidx] |= (1 << bit);
3142 }
3143
3144 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3145 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3146 mc_filter[i]);
3147 }
3148
3149 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3150 }
3151
3152 if (rx_mode != bp->rx_mode) {
3153 bp->rx_mode = rx_mode;
3154 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3155 }
3156
3157 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3158 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3159 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3160
Michael Chanc770a652005-08-25 15:38:39 -07003161 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07003162}
3163
3164static void
Al Virob491edd2007-12-22 19:44:51 +00003165load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
Michael Chanb6016b72005-05-26 13:03:09 -07003166 u32 rv2p_proc)
3167{
3168 int i;
3169 u32 val;
3170
3171
3172 for (i = 0; i < rv2p_code_len; i += 8) {
Al Virob491edd2007-12-22 19:44:51 +00003173 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
Michael Chanb6016b72005-05-26 13:03:09 -07003174 rv2p_code++;
Al Virob491edd2007-12-22 19:44:51 +00003175 REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
Michael Chanb6016b72005-05-26 13:03:09 -07003176 rv2p_code++;
3177
3178 if (rv2p_proc == RV2P_PROC1) {
3179 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3180 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
3181 }
3182 else {
3183 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3184 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
3185 }
3186 }
3187
3188 /* Reset the processor, un-stall is done later. */
3189 if (rv2p_proc == RV2P_PROC1) {
3190 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3191 }
3192 else {
3193 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3194 }
3195}
3196
Michael Chanaf3ee512006-11-19 14:09:25 -08003197static int
Michael Chanb6016b72005-05-26 13:03:09 -07003198load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
3199{
3200 u32 offset;
3201 u32 val;
Michael Chanaf3ee512006-11-19 14:09:25 -08003202 int rc;
Michael Chanb6016b72005-05-26 13:03:09 -07003203
3204 /* Halt the CPU. */
Michael Chan2726d6e2008-01-29 21:35:05 -08003205 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
Michael Chanb6016b72005-05-26 13:03:09 -07003206 val |= cpu_reg->mode_value_halt;
Michael Chan2726d6e2008-01-29 21:35:05 -08003207 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3208 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
Michael Chanb6016b72005-05-26 13:03:09 -07003209
3210 /* Load the Text area. */
3211 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
Michael Chanaf3ee512006-11-19 14:09:25 -08003212 if (fw->gz_text) {
Michael Chanb6016b72005-05-26 13:03:09 -07003213 int j;
3214
Michael Chanea1f8d52007-10-02 16:27:35 -07003215 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3216 fw->gz_text_len);
3217 if (rc < 0)
Denys Vlasenkob3448b02007-09-30 17:55:51 -07003218 return rc;
Michael Chanea1f8d52007-10-02 16:27:35 -07003219
Michael Chanb6016b72005-05-26 13:03:09 -07003220 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
Michael Chan2726d6e2008-01-29 21:35:05 -08003221 bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
Michael Chanb6016b72005-05-26 13:03:09 -07003222 }
3223 }
3224
3225 /* Load the Data area. */
3226 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3227 if (fw->data) {
3228 int j;
3229
3230 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
Michael Chan2726d6e2008-01-29 21:35:05 -08003231 bnx2_reg_wr_ind(bp, offset, fw->data[j]);
Michael Chanb6016b72005-05-26 13:03:09 -07003232 }
3233 }
3234
3235 /* Load the SBSS area. */
3236 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
Michael Chanea1f8d52007-10-02 16:27:35 -07003237 if (fw->sbss_len) {
Michael Chanb6016b72005-05-26 13:03:09 -07003238 int j;
3239
3240 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
Michael Chan2726d6e2008-01-29 21:35:05 -08003241 bnx2_reg_wr_ind(bp, offset, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07003242 }
3243 }
3244
3245 /* Load the BSS area. */
3246 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
Michael Chanea1f8d52007-10-02 16:27:35 -07003247 if (fw->bss_len) {
Michael Chanb6016b72005-05-26 13:03:09 -07003248 int j;
3249
3250 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
Michael Chan2726d6e2008-01-29 21:35:05 -08003251 bnx2_reg_wr_ind(bp, offset, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07003252 }
3253 }
3254
3255 /* Load the Read-Only area. */
3256 offset = cpu_reg->spad_base +
3257 (fw->rodata_addr - cpu_reg->mips_view_base);
3258 if (fw->rodata) {
3259 int j;
3260
3261 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
Michael Chan2726d6e2008-01-29 21:35:05 -08003262 bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
Michael Chanb6016b72005-05-26 13:03:09 -07003263 }
3264 }
3265
3266 /* Clear the pre-fetch instruction. */
Michael Chan2726d6e2008-01-29 21:35:05 -08003267 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3268 bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
Michael Chanb6016b72005-05-26 13:03:09 -07003269
3270 /* Start the CPU. */
Michael Chan2726d6e2008-01-29 21:35:05 -08003271 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
Michael Chanb6016b72005-05-26 13:03:09 -07003272 val &= ~cpu_reg->mode_value_halt;
Michael Chan2726d6e2008-01-29 21:35:05 -08003273 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3274 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
Michael Chanaf3ee512006-11-19 14:09:25 -08003275
3276 return 0;
Michael Chanb6016b72005-05-26 13:03:09 -07003277}
3278
Michael Chanfba9fe92006-06-12 22:21:25 -07003279static int
Michael Chanb6016b72005-05-26 13:03:09 -07003280bnx2_init_cpus(struct bnx2 *bp)
3281{
3282 struct cpu_reg cpu_reg;
Michael Chanaf3ee512006-11-19 14:09:25 -08003283 struct fw_info *fw;
Michael Chan110d0ef2007-12-12 11:18:34 -08003284 int rc, rv2p_len;
3285 void *text, *rv2p;
Michael Chanb6016b72005-05-26 13:03:09 -07003286
3287 /* Initialize the RV2P processor. */
Denys Vlasenkob3448b02007-09-30 17:55:51 -07003288 text = vmalloc(FW_BUF_SIZE);
3289 if (!text)
3290 return -ENOMEM;
Michael Chan110d0ef2007-12-12 11:18:34 -08003291 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3292 rv2p = bnx2_xi_rv2p_proc1;
3293 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3294 } else {
3295 rv2p = bnx2_rv2p_proc1;
3296 rv2p_len = sizeof(bnx2_rv2p_proc1);
3297 }
3298 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
Michael Chanea1f8d52007-10-02 16:27:35 -07003299 if (rc < 0)
Michael Chanfba9fe92006-06-12 22:21:25 -07003300 goto init_cpu_err;
Michael Chanea1f8d52007-10-02 16:27:35 -07003301
Denys Vlasenkob3448b02007-09-30 17:55:51 -07003302 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
Michael Chanfba9fe92006-06-12 22:21:25 -07003303
Michael Chan110d0ef2007-12-12 11:18:34 -08003304 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3305 rv2p = bnx2_xi_rv2p_proc2;
3306 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3307 } else {
3308 rv2p = bnx2_rv2p_proc2;
3309 rv2p_len = sizeof(bnx2_rv2p_proc2);
3310 }
3311 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
Michael Chanea1f8d52007-10-02 16:27:35 -07003312 if (rc < 0)
Michael Chanfba9fe92006-06-12 22:21:25 -07003313 goto init_cpu_err;
Michael Chanea1f8d52007-10-02 16:27:35 -07003314
Denys Vlasenkob3448b02007-09-30 17:55:51 -07003315 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
Michael Chanb6016b72005-05-26 13:03:09 -07003316
3317 /* Initialize the RX Processor. */
3318 cpu_reg.mode = BNX2_RXP_CPU_MODE;
3319 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
3320 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
3321 cpu_reg.state = BNX2_RXP_CPU_STATE;
3322 cpu_reg.state_value_clear = 0xffffff;
3323 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
3324 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
3325 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
3326 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
3327 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
3328 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
3329 cpu_reg.mips_view_base = 0x8000000;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04003330
Michael Chand43584c2006-11-19 14:14:35 -08003331 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3332 fw = &bnx2_rxp_fw_09;
3333 else
3334 fw = &bnx2_rxp_fw_06;
Michael Chanb6016b72005-05-26 13:03:09 -07003335
Michael Chanea1f8d52007-10-02 16:27:35 -07003336 fw->text = text;
Michael Chanaf3ee512006-11-19 14:09:25 -08003337 rc = load_cpu_fw(bp, &cpu_reg, fw);
Michael Chanfba9fe92006-06-12 22:21:25 -07003338 if (rc)
3339 goto init_cpu_err;
3340
Michael Chanb6016b72005-05-26 13:03:09 -07003341 /* Initialize the TX Processor. */
3342 cpu_reg.mode = BNX2_TXP_CPU_MODE;
3343 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
3344 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
3345 cpu_reg.state = BNX2_TXP_CPU_STATE;
3346 cpu_reg.state_value_clear = 0xffffff;
3347 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
3348 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
3349 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
3350 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
3351 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
3352 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
3353 cpu_reg.mips_view_base = 0x8000000;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04003354
Michael Chand43584c2006-11-19 14:14:35 -08003355 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3356 fw = &bnx2_txp_fw_09;
3357 else
3358 fw = &bnx2_txp_fw_06;
Michael Chanb6016b72005-05-26 13:03:09 -07003359
Michael Chanea1f8d52007-10-02 16:27:35 -07003360 fw->text = text;
Michael Chanaf3ee512006-11-19 14:09:25 -08003361 rc = load_cpu_fw(bp, &cpu_reg, fw);
Michael Chanfba9fe92006-06-12 22:21:25 -07003362 if (rc)
3363 goto init_cpu_err;
3364
Michael Chanb6016b72005-05-26 13:03:09 -07003365 /* Initialize the TX Patch-up Processor. */
3366 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
3367 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
3368 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
3369 cpu_reg.state = BNX2_TPAT_CPU_STATE;
3370 cpu_reg.state_value_clear = 0xffffff;
3371 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
3372 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
3373 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
3374 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
3375 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
3376 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
3377 cpu_reg.mips_view_base = 0x8000000;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04003378
Michael Chand43584c2006-11-19 14:14:35 -08003379 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3380 fw = &bnx2_tpat_fw_09;
3381 else
3382 fw = &bnx2_tpat_fw_06;
Michael Chanb6016b72005-05-26 13:03:09 -07003383
Michael Chanea1f8d52007-10-02 16:27:35 -07003384 fw->text = text;
Michael Chanaf3ee512006-11-19 14:09:25 -08003385 rc = load_cpu_fw(bp, &cpu_reg, fw);
Michael Chanfba9fe92006-06-12 22:21:25 -07003386 if (rc)
3387 goto init_cpu_err;
3388
Michael Chanb6016b72005-05-26 13:03:09 -07003389 /* Initialize the Completion Processor. */
3390 cpu_reg.mode = BNX2_COM_CPU_MODE;
3391 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
3392 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
3393 cpu_reg.state = BNX2_COM_CPU_STATE;
3394 cpu_reg.state_value_clear = 0xffffff;
3395 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
3396 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
3397 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
3398 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
3399 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
3400 cpu_reg.spad_base = BNX2_COM_SCRATCH;
3401 cpu_reg.mips_view_base = 0x8000000;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04003402
Michael Chand43584c2006-11-19 14:14:35 -08003403 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3404 fw = &bnx2_com_fw_09;
3405 else
3406 fw = &bnx2_com_fw_06;
Michael Chanb6016b72005-05-26 13:03:09 -07003407
Michael Chanea1f8d52007-10-02 16:27:35 -07003408 fw->text = text;
Michael Chanaf3ee512006-11-19 14:09:25 -08003409 rc = load_cpu_fw(bp, &cpu_reg, fw);
Michael Chanfba9fe92006-06-12 22:21:25 -07003410 if (rc)
3411 goto init_cpu_err;
3412
Michael Chand43584c2006-11-19 14:14:35 -08003413 /* Initialize the Command Processor. */
3414 cpu_reg.mode = BNX2_CP_CPU_MODE;
3415 cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
3416 cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
3417 cpu_reg.state = BNX2_CP_CPU_STATE;
3418 cpu_reg.state_value_clear = 0xffffff;
3419 cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
3420 cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
3421 cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
3422 cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
3423 cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
3424 cpu_reg.spad_base = BNX2_CP_SCRATCH;
3425 cpu_reg.mips_view_base = 0x8000000;
Michael Chanb6016b72005-05-26 13:03:09 -07003426
Michael Chan110d0ef2007-12-12 11:18:34 -08003427 if (CHIP_NUM(bp) == CHIP_NUM_5709)
Michael Chand43584c2006-11-19 14:14:35 -08003428 fw = &bnx2_cp_fw_09;
Michael Chan110d0ef2007-12-12 11:18:34 -08003429 else
3430 fw = &bnx2_cp_fw_06;
Michael Chanb6016b72005-05-26 13:03:09 -07003431
Michael Chan110d0ef2007-12-12 11:18:34 -08003432 fw->text = text;
3433 rc = load_cpu_fw(bp, &cpu_reg, fw);
3434
Michael Chanfba9fe92006-06-12 22:21:25 -07003435init_cpu_err:
Michael Chanea1f8d52007-10-02 16:27:35 -07003436 vfree(text);
Michael Chanfba9fe92006-06-12 22:21:25 -07003437 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07003438}
3439
3440static int
Pavel Machek829ca9a2005-09-03 15:56:56 -07003441bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
Michael Chanb6016b72005-05-26 13:03:09 -07003442{
3443 u16 pmcsr;
3444
3445 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3446
3447 switch (state) {
Pavel Machek829ca9a2005-09-03 15:56:56 -07003448 case PCI_D0: {
Michael Chanb6016b72005-05-26 13:03:09 -07003449 u32 val;
3450
3451 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3452 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3453 PCI_PM_CTRL_PME_STATUS);
3454
3455 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3456 /* delay required during transition out of D3hot */
3457 msleep(20);
3458
3459 val = REG_RD(bp, BNX2_EMAC_MODE);
3460 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3461 val &= ~BNX2_EMAC_MODE_MPKT;
3462 REG_WR(bp, BNX2_EMAC_MODE, val);
3463
3464 val = REG_RD(bp, BNX2_RPM_CONFIG);
3465 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3466 REG_WR(bp, BNX2_RPM_CONFIG, val);
3467 break;
3468 }
Pavel Machek829ca9a2005-09-03 15:56:56 -07003469 case PCI_D3hot: {
Michael Chanb6016b72005-05-26 13:03:09 -07003470 int i;
3471 u32 val, wol_msg;
3472
3473 if (bp->wol) {
3474 u32 advertising;
3475 u8 autoneg;
3476
3477 autoneg = bp->autoneg;
3478 advertising = bp->advertising;
3479
Michael Chan239cd342007-10-17 19:26:15 -07003480 if (bp->phy_port == PORT_TP) {
3481 bp->autoneg = AUTONEG_SPEED;
3482 bp->advertising = ADVERTISED_10baseT_Half |
3483 ADVERTISED_10baseT_Full |
3484 ADVERTISED_100baseT_Half |
3485 ADVERTISED_100baseT_Full |
3486 ADVERTISED_Autoneg;
3487 }
Michael Chanb6016b72005-05-26 13:03:09 -07003488
Michael Chan239cd342007-10-17 19:26:15 -07003489 spin_lock_bh(&bp->phy_lock);
3490 bnx2_setup_phy(bp, bp->phy_port);
3491 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07003492
3493 bp->autoneg = autoneg;
3494 bp->advertising = advertising;
3495
3496 bnx2_set_mac_addr(bp);
3497
3498 val = REG_RD(bp, BNX2_EMAC_MODE);
3499
3500 /* Enable port mode. */
3501 val &= ~BNX2_EMAC_MODE_PORT;
Michael Chan239cd342007-10-17 19:26:15 -07003502 val |= BNX2_EMAC_MODE_MPKT_RCVD |
Michael Chanb6016b72005-05-26 13:03:09 -07003503 BNX2_EMAC_MODE_ACPI_RCVD |
Michael Chanb6016b72005-05-26 13:03:09 -07003504 BNX2_EMAC_MODE_MPKT;
Michael Chan239cd342007-10-17 19:26:15 -07003505 if (bp->phy_port == PORT_TP)
3506 val |= BNX2_EMAC_MODE_PORT_MII;
3507 else {
3508 val |= BNX2_EMAC_MODE_PORT_GMII;
3509 if (bp->line_speed == SPEED_2500)
3510 val |= BNX2_EMAC_MODE_25G_MODE;
3511 }
Michael Chanb6016b72005-05-26 13:03:09 -07003512
3513 REG_WR(bp, BNX2_EMAC_MODE, val);
3514
3515 /* receive all multicast */
3516 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3517 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3518 0xffffffff);
3519 }
3520 REG_WR(bp, BNX2_EMAC_RX_MODE,
3521 BNX2_EMAC_RX_MODE_SORT_MODE);
3522
3523 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3524 BNX2_RPM_SORT_USER0_MC_EN;
3525 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3526 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3527 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3528 BNX2_RPM_SORT_USER0_ENA);
3529
3530 /* Need to enable EMAC and RPM for WOL. */
3531 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3532 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3533 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3534 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3535
3536 val = REG_RD(bp, BNX2_RPM_CONFIG);
3537 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3538 REG_WR(bp, BNX2_RPM_CONFIG, val);
3539
3540 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3541 }
3542 else {
3543 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3544 }
3545
David S. Millerf86e82f2008-01-21 17:15:40 -08003546 if (!(bp->flags & BNX2_FLAG_NO_WOL))
Michael Chandda1e392006-01-23 16:08:14 -08003547 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
Michael Chanb6016b72005-05-26 13:03:09 -07003548
3549 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3550 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3551 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3552
3553 if (bp->wol)
3554 pmcsr |= 3;
3555 }
3556 else {
3557 pmcsr |= 3;
3558 }
3559 if (bp->wol) {
3560 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3561 }
3562 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3563 pmcsr);
3564
3565 /* No more memory access after this point until
3566 * device is brought back to D0.
3567 */
3568 udelay(50);
3569 break;
3570 }
3571 default:
3572 return -EINVAL;
3573 }
3574 return 0;
3575}
3576
3577static int
3578bnx2_acquire_nvram_lock(struct bnx2 *bp)
3579{
3580 u32 val;
3581 int j;
3582
3583 /* Request access to the flash interface. */
3584 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3585 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3586 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3587 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3588 break;
3589
3590 udelay(5);
3591 }
3592
3593 if (j >= NVRAM_TIMEOUT_COUNT)
3594 return -EBUSY;
3595
3596 return 0;
3597}
3598
3599static int
3600bnx2_release_nvram_lock(struct bnx2 *bp)
3601{
3602 int j;
3603 u32 val;
3604
3605 /* Relinquish nvram interface. */
3606 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3607
3608 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3609 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3610 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3611 break;
3612
3613 udelay(5);
3614 }
3615
3616 if (j >= NVRAM_TIMEOUT_COUNT)
3617 return -EBUSY;
3618
3619 return 0;
3620}
3621
3622
3623static int
3624bnx2_enable_nvram_write(struct bnx2 *bp)
3625{
3626 u32 val;
3627
3628 val = REG_RD(bp, BNX2_MISC_CFG);
3629 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3630
Michael Chane30372c2007-07-16 18:26:23 -07003631 if (bp->flash_info->flags & BNX2_NV_WREN) {
Michael Chanb6016b72005-05-26 13:03:09 -07003632 int j;
3633
3634 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3635 REG_WR(bp, BNX2_NVM_COMMAND,
3636 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3637
3638 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3639 udelay(5);
3640
3641 val = REG_RD(bp, BNX2_NVM_COMMAND);
3642 if (val & BNX2_NVM_COMMAND_DONE)
3643 break;
3644 }
3645
3646 if (j >= NVRAM_TIMEOUT_COUNT)
3647 return -EBUSY;
3648 }
3649 return 0;
3650}
3651
3652static void
3653bnx2_disable_nvram_write(struct bnx2 *bp)
3654{
3655 u32 val;
3656
3657 val = REG_RD(bp, BNX2_MISC_CFG);
3658 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3659}
3660
3661
3662static void
3663bnx2_enable_nvram_access(struct bnx2 *bp)
3664{
3665 u32 val;
3666
3667 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3668 /* Enable both bits, even on read. */
Jeff Garzik6aa20a22006-09-13 13:24:59 -04003669 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
Michael Chanb6016b72005-05-26 13:03:09 -07003670 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3671}
3672
3673static void
3674bnx2_disable_nvram_access(struct bnx2 *bp)
3675{
3676 u32 val;
3677
3678 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3679 /* Disable both bits, even after read. */
Jeff Garzik6aa20a22006-09-13 13:24:59 -04003680 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
Michael Chanb6016b72005-05-26 13:03:09 -07003681 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3682 BNX2_NVM_ACCESS_ENABLE_WR_EN));
3683}
3684
3685static int
3686bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3687{
3688 u32 cmd;
3689 int j;
3690
Michael Chane30372c2007-07-16 18:26:23 -07003691 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
Michael Chanb6016b72005-05-26 13:03:09 -07003692 /* Buffered flash, no erase needed */
3693 return 0;
3694
3695 /* Build an erase command */
3696 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3697 BNX2_NVM_COMMAND_DOIT;
3698
3699 /* Need to clear DONE bit separately. */
3700 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3701
3702 /* Address of the NVRAM to read from. */
3703 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3704
3705 /* Issue an erase command. */
3706 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3707
3708 /* Wait for completion. */
3709 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3710 u32 val;
3711
3712 udelay(5);
3713
3714 val = REG_RD(bp, BNX2_NVM_COMMAND);
3715 if (val & BNX2_NVM_COMMAND_DONE)
3716 break;
3717 }
3718
3719 if (j >= NVRAM_TIMEOUT_COUNT)
3720 return -EBUSY;
3721
3722 return 0;
3723}
3724
3725static int
3726bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3727{
3728 u32 cmd;
3729 int j;
3730
3731 /* Build the command word. */
3732 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3733
Michael Chane30372c2007-07-16 18:26:23 -07003734 /* Calculate an offset of a buffered flash, not needed for 5709. */
3735 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
Michael Chanb6016b72005-05-26 13:03:09 -07003736 offset = ((offset / bp->flash_info->page_size) <<
3737 bp->flash_info->page_bits) +
3738 (offset % bp->flash_info->page_size);
3739 }
3740
3741 /* Need to clear DONE bit separately. */
3742 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3743
3744 /* Address of the NVRAM to read from. */
3745 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3746
3747 /* Issue a read command. */
3748 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3749
3750 /* Wait for completion. */
3751 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3752 u32 val;
3753
3754 udelay(5);
3755
3756 val = REG_RD(bp, BNX2_NVM_COMMAND);
3757 if (val & BNX2_NVM_COMMAND_DONE) {
Al Virob491edd2007-12-22 19:44:51 +00003758 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3759 memcpy(ret_val, &v, 4);
Michael Chanb6016b72005-05-26 13:03:09 -07003760 break;
3761 }
3762 }
3763 if (j >= NVRAM_TIMEOUT_COUNT)
3764 return -EBUSY;
3765
3766 return 0;
3767}
3768
3769
3770static int
3771bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3772{
Al Virob491edd2007-12-22 19:44:51 +00003773 u32 cmd;
3774 __be32 val32;
Michael Chanb6016b72005-05-26 13:03:09 -07003775 int j;
3776
3777 /* Build the command word. */
3778 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3779
Michael Chane30372c2007-07-16 18:26:23 -07003780 /* Calculate an offset of a buffered flash, not needed for 5709. */
3781 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
Michael Chanb6016b72005-05-26 13:03:09 -07003782 offset = ((offset / bp->flash_info->page_size) <<
3783 bp->flash_info->page_bits) +
3784 (offset % bp->flash_info->page_size);
3785 }
3786
3787 /* Need to clear DONE bit separately. */
3788 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3789
3790 memcpy(&val32, val, 4);
Michael Chanb6016b72005-05-26 13:03:09 -07003791
3792 /* Write the data. */
Al Virob491edd2007-12-22 19:44:51 +00003793 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
Michael Chanb6016b72005-05-26 13:03:09 -07003794
3795 /* Address of the NVRAM to write to. */
3796 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3797
3798 /* Issue the write command. */
3799 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3800
3801 /* Wait for completion. */
3802 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3803 udelay(5);
3804
3805 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3806 break;
3807 }
3808 if (j >= NVRAM_TIMEOUT_COUNT)
3809 return -EBUSY;
3810
3811 return 0;
3812}
3813
3814static int
3815bnx2_init_nvram(struct bnx2 *bp)
3816{
3817 u32 val;
Michael Chane30372c2007-07-16 18:26:23 -07003818 int j, entry_count, rc = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07003819 struct flash_spec *flash;
3820
Michael Chane30372c2007-07-16 18:26:23 -07003821 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3822 bp->flash_info = &flash_5709;
3823 goto get_flash_size;
3824 }
3825
Michael Chanb6016b72005-05-26 13:03:09 -07003826 /* Determine the selected interface. */
3827 val = REG_RD(bp, BNX2_NVM_CFG1);
3828
Denis Chengff8ac602007-09-02 18:30:18 +08003829 entry_count = ARRAY_SIZE(flash_table);
Michael Chanb6016b72005-05-26 13:03:09 -07003830
Michael Chanb6016b72005-05-26 13:03:09 -07003831 if (val & 0x40000000) {
3832
3833 /* Flash interface has been reconfigured */
3834 for (j = 0, flash = &flash_table[0]; j < entry_count;
Michael Chan37137702005-11-04 08:49:17 -08003835 j++, flash++) {
3836 if ((val & FLASH_BACKUP_STRAP_MASK) ==
3837 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
Michael Chanb6016b72005-05-26 13:03:09 -07003838 bp->flash_info = flash;
3839 break;
3840 }
3841 }
3842 }
3843 else {
Michael Chan37137702005-11-04 08:49:17 -08003844 u32 mask;
Michael Chanb6016b72005-05-26 13:03:09 -07003845 /* Not yet been reconfigured */
3846
Michael Chan37137702005-11-04 08:49:17 -08003847 if (val & (1 << 23))
3848 mask = FLASH_BACKUP_STRAP_MASK;
3849 else
3850 mask = FLASH_STRAP_MASK;
3851
Michael Chanb6016b72005-05-26 13:03:09 -07003852 for (j = 0, flash = &flash_table[0]; j < entry_count;
3853 j++, flash++) {
3854
Michael Chan37137702005-11-04 08:49:17 -08003855 if ((val & mask) == (flash->strapping & mask)) {
Michael Chanb6016b72005-05-26 13:03:09 -07003856 bp->flash_info = flash;
3857
3858 /* Request access to the flash interface. */
3859 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3860 return rc;
3861
3862 /* Enable access to flash interface */
3863 bnx2_enable_nvram_access(bp);
3864
3865 /* Reconfigure the flash interface */
3866 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3867 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3868 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3869 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3870
3871 /* Disable access to flash interface */
3872 bnx2_disable_nvram_access(bp);
3873 bnx2_release_nvram_lock(bp);
3874
3875 break;
3876 }
3877 }
3878 } /* if (val & 0x40000000) */
3879
3880 if (j == entry_count) {
3881 bp->flash_info = NULL;
John W. Linville2f23c522005-11-10 12:57:33 -08003882 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
Michael Chan1122db72006-01-23 16:11:42 -08003883 return -ENODEV;
Michael Chanb6016b72005-05-26 13:03:09 -07003884 }
3885
Michael Chane30372c2007-07-16 18:26:23 -07003886get_flash_size:
Michael Chan2726d6e2008-01-29 21:35:05 -08003887 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
Michael Chan1122db72006-01-23 16:11:42 -08003888 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
3889 if (val)
3890 bp->flash_size = val;
3891 else
3892 bp->flash_size = bp->flash_info->total_size;
3893
Michael Chanb6016b72005-05-26 13:03:09 -07003894 return rc;
3895}
3896
3897static int
3898bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
3899 int buf_size)
3900{
3901 int rc = 0;
3902 u32 cmd_flags, offset32, len32, extra;
3903
3904 if (buf_size == 0)
3905 return 0;
3906
3907 /* Request access to the flash interface. */
3908 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3909 return rc;
3910
3911 /* Enable access to flash interface */
3912 bnx2_enable_nvram_access(bp);
3913
3914 len32 = buf_size;
3915 offset32 = offset;
3916 extra = 0;
3917
3918 cmd_flags = 0;
3919
3920 if (offset32 & 3) {
3921 u8 buf[4];
3922 u32 pre_len;
3923
3924 offset32 &= ~3;
3925 pre_len = 4 - (offset & 3);
3926
3927 if (pre_len >= len32) {
3928 pre_len = len32;
3929 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3930 BNX2_NVM_COMMAND_LAST;
3931 }
3932 else {
3933 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3934 }
3935
3936 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3937
3938 if (rc)
3939 return rc;
3940
3941 memcpy(ret_buf, buf + (offset & 3), pre_len);
3942
3943 offset32 += 4;
3944 ret_buf += pre_len;
3945 len32 -= pre_len;
3946 }
3947 if (len32 & 3) {
3948 extra = 4 - (len32 & 3);
3949 len32 = (len32 + 4) & ~3;
3950 }
3951
3952 if (len32 == 4) {
3953 u8 buf[4];
3954
3955 if (cmd_flags)
3956 cmd_flags = BNX2_NVM_COMMAND_LAST;
3957 else
3958 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3959 BNX2_NVM_COMMAND_LAST;
3960
3961 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3962
3963 memcpy(ret_buf, buf, 4 - extra);
3964 }
3965 else if (len32 > 0) {
3966 u8 buf[4];
3967
3968 /* Read the first word. */
3969 if (cmd_flags)
3970 cmd_flags = 0;
3971 else
3972 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3973
3974 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
3975
3976 /* Advance to the next dword. */
3977 offset32 += 4;
3978 ret_buf += 4;
3979 len32 -= 4;
3980
3981 while (len32 > 4 && rc == 0) {
3982 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
3983
3984 /* Advance to the next dword. */
3985 offset32 += 4;
3986 ret_buf += 4;
3987 len32 -= 4;
3988 }
3989
3990 if (rc)
3991 return rc;
3992
3993 cmd_flags = BNX2_NVM_COMMAND_LAST;
3994 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3995
3996 memcpy(ret_buf, buf, 4 - extra);
3997 }
3998
3999 /* Disable access to flash interface */
4000 bnx2_disable_nvram_access(bp);
4001
4002 bnx2_release_nvram_lock(bp);
4003
4004 return rc;
4005}
4006
4007static int
4008bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4009 int buf_size)
4010{
4011 u32 written, offset32, len32;
Michael Chane6be7632007-01-08 19:56:13 -08004012 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -07004013 int rc = 0;
4014 int align_start, align_end;
4015
4016 buf = data_buf;
4017 offset32 = offset;
4018 len32 = buf_size;
4019 align_start = align_end = 0;
4020
4021 if ((align_start = (offset32 & 3))) {
4022 offset32 &= ~3;
Michael Chanc8738792007-03-30 14:53:06 -07004023 len32 += align_start;
4024 if (len32 < 4)
4025 len32 = 4;
Michael Chanb6016b72005-05-26 13:03:09 -07004026 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4027 return rc;
4028 }
4029
4030 if (len32 & 3) {
Michael Chanc8738792007-03-30 14:53:06 -07004031 align_end = 4 - (len32 & 3);
4032 len32 += align_end;
4033 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4034 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07004035 }
4036
4037 if (align_start || align_end) {
Michael Chane6be7632007-01-08 19:56:13 -08004038 align_buf = kmalloc(len32, GFP_KERNEL);
4039 if (align_buf == NULL)
Michael Chanb6016b72005-05-26 13:03:09 -07004040 return -ENOMEM;
4041 if (align_start) {
Michael Chane6be7632007-01-08 19:56:13 -08004042 memcpy(align_buf, start, 4);
Michael Chanb6016b72005-05-26 13:03:09 -07004043 }
4044 if (align_end) {
Michael Chane6be7632007-01-08 19:56:13 -08004045 memcpy(align_buf + len32 - 4, end, 4);
Michael Chanb6016b72005-05-26 13:03:09 -07004046 }
Michael Chane6be7632007-01-08 19:56:13 -08004047 memcpy(align_buf + align_start, data_buf, buf_size);
4048 buf = align_buf;
Michael Chanb6016b72005-05-26 13:03:09 -07004049 }
4050
Michael Chane30372c2007-07-16 18:26:23 -07004051 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
Michael Chanae181bc2006-05-22 16:39:20 -07004052 flash_buffer = kmalloc(264, GFP_KERNEL);
4053 if (flash_buffer == NULL) {
4054 rc = -ENOMEM;
4055 goto nvram_write_end;
4056 }
4057 }
4058
Michael Chanb6016b72005-05-26 13:03:09 -07004059 written = 0;
4060 while ((written < len32) && (rc == 0)) {
4061 u32 page_start, page_end, data_start, data_end;
4062 u32 addr, cmd_flags;
4063 int i;
Michael Chanb6016b72005-05-26 13:03:09 -07004064
4065 /* Find the page_start addr */
4066 page_start = offset32 + written;
4067 page_start -= (page_start % bp->flash_info->page_size);
4068 /* Find the page_end addr */
4069 page_end = page_start + bp->flash_info->page_size;
4070 /* Find the data_start addr */
4071 data_start = (written == 0) ? offset32 : page_start;
4072 /* Find the data_end addr */
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004073 data_end = (page_end > offset32 + len32) ?
Michael Chanb6016b72005-05-26 13:03:09 -07004074 (offset32 + len32) : page_end;
4075
4076 /* Request access to the flash interface. */
4077 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4078 goto nvram_write_end;
4079
4080 /* Enable access to flash interface */
4081 bnx2_enable_nvram_access(bp);
4082
4083 cmd_flags = BNX2_NVM_COMMAND_FIRST;
Michael Chane30372c2007-07-16 18:26:23 -07004084 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
Michael Chanb6016b72005-05-26 13:03:09 -07004085 int j;
4086
4087 /* Read the whole page into the buffer
4088 * (non-buffer flash only) */
4089 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4090 if (j == (bp->flash_info->page_size - 4)) {
4091 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4092 }
4093 rc = bnx2_nvram_read_dword(bp,
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004094 page_start + j,
4095 &flash_buffer[j],
Michael Chanb6016b72005-05-26 13:03:09 -07004096 cmd_flags);
4097
4098 if (rc)
4099 goto nvram_write_end;
4100
4101 cmd_flags = 0;
4102 }
4103 }
4104
4105 /* Enable writes to flash interface (unlock write-protect) */
4106 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4107 goto nvram_write_end;
4108
Michael Chanb6016b72005-05-26 13:03:09 -07004109 /* Loop to write back the buffer data from page_start to
4110 * data_start */
4111 i = 0;
Michael Chane30372c2007-07-16 18:26:23 -07004112 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
Michael Chanc8738792007-03-30 14:53:06 -07004113 /* Erase the page */
4114 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4115 goto nvram_write_end;
4116
4117 /* Re-enable the write again for the actual write */
4118 bnx2_enable_nvram_write(bp);
4119
Michael Chanb6016b72005-05-26 13:03:09 -07004120 for (addr = page_start; addr < data_start;
4121 addr += 4, i += 4) {
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004122
Michael Chanb6016b72005-05-26 13:03:09 -07004123 rc = bnx2_nvram_write_dword(bp, addr,
4124 &flash_buffer[i], cmd_flags);
4125
4126 if (rc != 0)
4127 goto nvram_write_end;
4128
4129 cmd_flags = 0;
4130 }
4131 }
4132
4133 /* Loop to write the new data from data_start to data_end */
Michael Chanbae25762006-05-22 16:38:38 -07004134 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
Michael Chanb6016b72005-05-26 13:03:09 -07004135 if ((addr == page_end - 4) ||
Michael Chane30372c2007-07-16 18:26:23 -07004136 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
Michael Chanb6016b72005-05-26 13:03:09 -07004137 (addr == data_end - 4))) {
4138
4139 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4140 }
4141 rc = bnx2_nvram_write_dword(bp, addr, buf,
4142 cmd_flags);
4143
4144 if (rc != 0)
4145 goto nvram_write_end;
4146
4147 cmd_flags = 0;
4148 buf += 4;
4149 }
4150
4151 /* Loop to write back the buffer data from data_end
4152 * to page_end */
Michael Chane30372c2007-07-16 18:26:23 -07004153 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
Michael Chanb6016b72005-05-26 13:03:09 -07004154 for (addr = data_end; addr < page_end;
4155 addr += 4, i += 4) {
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004156
Michael Chanb6016b72005-05-26 13:03:09 -07004157 if (addr == page_end-4) {
4158 cmd_flags = BNX2_NVM_COMMAND_LAST;
4159 }
4160 rc = bnx2_nvram_write_dword(bp, addr,
4161 &flash_buffer[i], cmd_flags);
4162
4163 if (rc != 0)
4164 goto nvram_write_end;
4165
4166 cmd_flags = 0;
4167 }
4168 }
4169
4170 /* Disable writes to flash interface (lock write-protect) */
4171 bnx2_disable_nvram_write(bp);
4172
4173 /* Disable access to flash interface */
4174 bnx2_disable_nvram_access(bp);
4175 bnx2_release_nvram_lock(bp);
4176
4177 /* Increment written */
4178 written += data_end - data_start;
4179 }
4180
4181nvram_write_end:
Michael Chane6be7632007-01-08 19:56:13 -08004182 kfree(flash_buffer);
4183 kfree(align_buf);
Michael Chanb6016b72005-05-26 13:03:09 -07004184 return rc;
4185}
4186
Michael Chan0d8a6572007-07-07 22:49:43 -07004187static void
4188bnx2_init_remote_phy(struct bnx2 *bp)
4189{
4190 u32 val;
4191
Michael Chan583c28e2008-01-21 19:51:35 -08004192 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4193 if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES))
Michael Chan0d8a6572007-07-07 22:49:43 -07004194 return;
4195
Michael Chan2726d6e2008-01-29 21:35:05 -08004196 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
Michael Chan0d8a6572007-07-07 22:49:43 -07004197 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4198 return;
4199
4200 if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) {
Michael Chan583c28e2008-01-21 19:51:35 -08004201 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
Michael Chan0d8a6572007-07-07 22:49:43 -07004202
Michael Chan2726d6e2008-01-29 21:35:05 -08004203 val = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
Michael Chan0d8a6572007-07-07 22:49:43 -07004204 if (val & BNX2_LINK_STATUS_SERDES_LINK)
4205 bp->phy_port = PORT_FIBRE;
4206 else
4207 bp->phy_port = PORT_TP;
Michael Chan489310a2007-10-10 16:16:31 -07004208
4209 if (netif_running(bp->dev)) {
4210 u32 sig;
4211
4212 if (val & BNX2_LINK_STATUS_LINK_UP) {
4213 bp->link_up = 1;
4214 netif_carrier_on(bp->dev);
4215 } else {
4216 bp->link_up = 0;
4217 netif_carrier_off(bp->dev);
4218 }
4219 sig = BNX2_DRV_ACK_CAP_SIGNATURE |
4220 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
Michael Chan2726d6e2008-01-29 21:35:05 -08004221 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
Michael Chan489310a2007-10-10 16:16:31 -07004222 }
Michael Chan0d8a6572007-07-07 22:49:43 -07004223 }
4224}
4225
Michael Chanb4b36042007-12-20 19:59:30 -08004226static void
4227bnx2_setup_msix_tbl(struct bnx2 *bp)
4228{
4229 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4230
4231 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4232 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4233}
4234
Michael Chanb6016b72005-05-26 13:03:09 -07004235static int
4236bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4237{
4238 u32 val;
4239 int i, rc = 0;
Michael Chan489310a2007-10-10 16:16:31 -07004240 u8 old_port;
Michael Chanb6016b72005-05-26 13:03:09 -07004241
4242 /* Wait for the current PCI transaction to complete before
4243 * issuing a reset. */
4244 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4245 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4246 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4247 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4248 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4249 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4250 udelay(5);
4251
Michael Chanb090ae22006-01-23 16:07:10 -08004252 /* Wait for the firmware to tell us it is ok to issue a reset. */
4253 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
4254
Michael Chanb6016b72005-05-26 13:03:09 -07004255 /* Deposit a driver reset signature so the firmware knows that
4256 * this is a soft reset. */
Michael Chan2726d6e2008-01-29 21:35:05 -08004257 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4258 BNX2_DRV_RESET_SIGNATURE_MAGIC);
Michael Chanb6016b72005-05-26 13:03:09 -07004259
Michael Chanb6016b72005-05-26 13:03:09 -07004260 /* Do a dummy read to force the chip to complete all current transaction
4261 * before we issue a reset. */
4262 val = REG_RD(bp, BNX2_MISC_ID);
4263
Michael Chan234754d2006-11-19 14:11:41 -08004264 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4265 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4266 REG_RD(bp, BNX2_MISC_COMMAND);
4267 udelay(5);
Michael Chanb6016b72005-05-26 13:03:09 -07004268
Michael Chan234754d2006-11-19 14:11:41 -08004269 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4270 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
Michael Chanb6016b72005-05-26 13:03:09 -07004271
Michael Chan234754d2006-11-19 14:11:41 -08004272 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
Michael Chanb6016b72005-05-26 13:03:09 -07004273
Michael Chan234754d2006-11-19 14:11:41 -08004274 } else {
4275 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4276 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4277 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4278
4279 /* Chip reset. */
4280 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4281
Michael Chan594a9df2007-08-28 15:39:42 -07004282 /* Reading back any register after chip reset will hang the
4283 * bus on 5706 A0 and A1. The msleep below provides plenty
4284 * of margin for write posting.
4285 */
Michael Chan234754d2006-11-19 14:11:41 -08004286 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
Arjan van de Ven8e545882007-08-28 14:34:43 -07004287 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4288 msleep(20);
Michael Chanb6016b72005-05-26 13:03:09 -07004289
Michael Chan234754d2006-11-19 14:11:41 -08004290 /* Reset takes approximate 30 usec */
4291 for (i = 0; i < 10; i++) {
4292 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4293 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4294 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4295 break;
4296 udelay(10);
4297 }
4298
4299 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4300 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4301 printk(KERN_ERR PFX "Chip reset did not complete\n");
4302 return -EBUSY;
4303 }
Michael Chanb6016b72005-05-26 13:03:09 -07004304 }
4305
4306 /* Make sure byte swapping is properly configured. */
4307 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4308 if (val != 0x01020304) {
4309 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4310 return -ENODEV;
4311 }
4312
Michael Chanb6016b72005-05-26 13:03:09 -07004313 /* Wait for the firmware to finish its initialization. */
Michael Chanb090ae22006-01-23 16:07:10 -08004314 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
4315 if (rc)
4316 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07004317
Michael Chan0d8a6572007-07-07 22:49:43 -07004318 spin_lock_bh(&bp->phy_lock);
Michael Chan489310a2007-10-10 16:16:31 -07004319 old_port = bp->phy_port;
Michael Chan0d8a6572007-07-07 22:49:43 -07004320 bnx2_init_remote_phy(bp);
Michael Chan583c28e2008-01-21 19:51:35 -08004321 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4322 old_port != bp->phy_port)
Michael Chan0d8a6572007-07-07 22:49:43 -07004323 bnx2_set_default_remote_link(bp);
4324 spin_unlock_bh(&bp->phy_lock);
4325
Michael Chanb6016b72005-05-26 13:03:09 -07004326 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4327 /* Adjust the voltage regular to two steps lower. The default
4328 * of this register is 0x0000000e. */
4329 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4330
4331 /* Remove bad rbuf memory from the free pool. */
4332 rc = bnx2_alloc_bad_rbuf(bp);
4333 }
4334
David S. Millerf86e82f2008-01-21 17:15:40 -08004335 if (bp->flags & BNX2_FLAG_USING_MSIX)
Michael Chanb4b36042007-12-20 19:59:30 -08004336 bnx2_setup_msix_tbl(bp);
4337
Michael Chanb6016b72005-05-26 13:03:09 -07004338 return rc;
4339}
4340
4341static int
4342bnx2_init_chip(struct bnx2 *bp)
4343{
4344 u32 val;
Michael Chanb4b36042007-12-20 19:59:30 -08004345 int rc, i;
Michael Chanb6016b72005-05-26 13:03:09 -07004346
4347 /* Make sure the interrupt is not active. */
4348 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4349
4350 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4351 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4352#ifdef __BIG_ENDIAN
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004353 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
Michael Chanb6016b72005-05-26 13:03:09 -07004354#endif
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004355 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
Michael Chanb6016b72005-05-26 13:03:09 -07004356 DMA_READ_CHANS << 12 |
4357 DMA_WRITE_CHANS << 16;
4358
4359 val |= (0x2 << 20) | (1 << 11);
4360
David S. Millerf86e82f2008-01-21 17:15:40 -08004361 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
Michael Chanb6016b72005-05-26 13:03:09 -07004362 val |= (1 << 23);
4363
4364 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
David S. Millerf86e82f2008-01-21 17:15:40 -08004365 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
Michael Chanb6016b72005-05-26 13:03:09 -07004366 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4367
4368 REG_WR(bp, BNX2_DMA_CONFIG, val);
4369
4370 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4371 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4372 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4373 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4374 }
4375
David S. Millerf86e82f2008-01-21 17:15:40 -08004376 if (bp->flags & BNX2_FLAG_PCIX) {
Michael Chanb6016b72005-05-26 13:03:09 -07004377 u16 val16;
4378
4379 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4380 &val16);
4381 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4382 val16 & ~PCI_X_CMD_ERO);
4383 }
4384
4385 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4386 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4387 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4388 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4389
4390 /* Initialize context mapping and zero out the quick contexts. The
4391 * context block must have already been enabled. */
Michael Chan641bdcd2007-06-04 21:22:24 -07004392 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4393 rc = bnx2_init_5709_context(bp);
4394 if (rc)
4395 return rc;
4396 } else
Michael Chan59b47d82006-11-19 14:10:45 -08004397 bnx2_init_context(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07004398
Michael Chanfba9fe92006-06-12 22:21:25 -07004399 if ((rc = bnx2_init_cpus(bp)) != 0)
4400 return rc;
4401
Michael Chanb6016b72005-05-26 13:03:09 -07004402 bnx2_init_nvram(bp);
4403
4404 bnx2_set_mac_addr(bp);
4405
4406 val = REG_RD(bp, BNX2_MQ_CONFIG);
4407 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4408 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
Michael Chan68c9f752007-04-24 15:35:53 -07004409 if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4410 val |= BNX2_MQ_CONFIG_HALT_DIS;
4411
Michael Chanb6016b72005-05-26 13:03:09 -07004412 REG_WR(bp, BNX2_MQ_CONFIG, val);
4413
4414 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4415 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4416 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4417
4418 val = (BCM_PAGE_BITS - 8) << 24;
4419 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4420
4421 /* Configure page size. */
4422 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4423 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4424 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4425 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4426
4427 val = bp->mac_addr[0] +
4428 (bp->mac_addr[1] << 8) +
4429 (bp->mac_addr[2] << 16) +
4430 bp->mac_addr[3] +
4431 (bp->mac_addr[4] << 8) +
4432 (bp->mac_addr[5] << 16);
4433 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4434
4435 /* Program the MTU. Also include 4 bytes for CRC32. */
4436 val = bp->dev->mtu + ETH_HLEN + 4;
4437 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4438 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4439 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4440
Michael Chanb4b36042007-12-20 19:59:30 -08004441 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4442 bp->bnx2_napi[i].last_status_idx = 0;
4443
Michael Chanb6016b72005-05-26 13:03:09 -07004444 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4445
4446 /* Set up how to generate a link change interrupt. */
4447 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4448
4449 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4450 (u64) bp->status_blk_mapping & 0xffffffff);
4451 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4452
4453 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4454 (u64) bp->stats_blk_mapping & 0xffffffff);
4455 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4456 (u64) bp->stats_blk_mapping >> 32);
4457
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004458 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
Michael Chanb6016b72005-05-26 13:03:09 -07004459 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4460
4461 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4462 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4463
4464 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4465 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4466
4467 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4468
4469 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4470
4471 REG_WR(bp, BNX2_HC_COM_TICKS,
4472 (bp->com_ticks_int << 16) | bp->com_ticks);
4473
4474 REG_WR(bp, BNX2_HC_CMD_TICKS,
4475 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4476
Michael Chan02537b062007-06-04 21:24:07 -07004477 if (CHIP_NUM(bp) == CHIP_NUM_5708)
4478 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4479 else
Michael Chan7ea69202007-07-16 18:27:10 -07004480 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
Michael Chanb6016b72005-05-26 13:03:09 -07004481 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4482
4483 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
Michael Chan8e6a72c2007-05-03 13:24:48 -07004484 val = BNX2_HC_CONFIG_COLLECT_STATS;
Michael Chanb6016b72005-05-26 13:03:09 -07004485 else {
Michael Chan8e6a72c2007-05-03 13:24:48 -07004486 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4487 BNX2_HC_CONFIG_COLLECT_STATS;
Michael Chanb6016b72005-05-26 13:03:09 -07004488 }
4489
David S. Millerf86e82f2008-01-21 17:15:40 -08004490 if (bp->flags & BNX2_FLAG_USING_MSIX) {
Michael Chan6f743ca2008-01-29 21:34:08 -08004491 u32 base = ((BNX2_TX_VEC - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4492 BNX2_HC_SB_CONFIG_1;
4493
Michael Chanc76c0472007-12-20 20:01:19 -08004494 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4495 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4496
Michael Chan6f743ca2008-01-29 21:34:08 -08004497 REG_WR(bp, base,
Michael Chanc76c0472007-12-20 20:01:19 -08004498 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4499 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4500
Michael Chan6f743ca2008-01-29 21:34:08 -08004501 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
Michael Chanc76c0472007-12-20 20:01:19 -08004502 (bp->tx_quick_cons_trip_int << 16) |
4503 bp->tx_quick_cons_trip);
4504
Michael Chan6f743ca2008-01-29 21:34:08 -08004505 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
Michael Chanc76c0472007-12-20 20:01:19 -08004506 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4507
4508 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4509 }
4510
David S. Millerf86e82f2008-01-21 17:15:40 -08004511 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
Michael Chan8e6a72c2007-05-03 13:24:48 -07004512 val |= BNX2_HC_CONFIG_ONE_SHOT;
4513
4514 REG_WR(bp, BNX2_HC_CONFIG, val);
4515
Michael Chanb6016b72005-05-26 13:03:09 -07004516 /* Clear internal stats counters. */
4517 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4518
Michael Chanda3e4fb2007-05-03 13:24:23 -07004519 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
Michael Chanb6016b72005-05-26 13:03:09 -07004520
4521 /* Initialize the receive filter. */
4522 bnx2_set_rx_mode(bp->dev);
4523
Michael Chan0aa38df2007-06-04 21:23:06 -07004524 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4525 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4526 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4527 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4528 }
Michael Chanb090ae22006-01-23 16:07:10 -08004529 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4530 0);
Michael Chanb6016b72005-05-26 13:03:09 -07004531
Michael Chandf149d72007-07-07 22:51:36 -07004532 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
Michael Chanb6016b72005-05-26 13:03:09 -07004533 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4534
4535 udelay(20);
4536
Michael Chanbf5295b2006-03-23 01:11:56 -08004537 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4538
Michael Chanb090ae22006-01-23 16:07:10 -08004539 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07004540}
4541
Michael Chan59b47d82006-11-19 14:10:45 -08004542static void
Michael Chanc76c0472007-12-20 20:01:19 -08004543bnx2_clear_ring_states(struct bnx2 *bp)
4544{
4545 struct bnx2_napi *bnapi;
4546 int i;
4547
4548 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4549 bnapi = &bp->bnx2_napi[i];
4550
4551 bnapi->tx_cons = 0;
4552 bnapi->hw_tx_cons = 0;
4553 bnapi->rx_prod_bseq = 0;
4554 bnapi->rx_prod = 0;
4555 bnapi->rx_cons = 0;
4556 bnapi->rx_pg_prod = 0;
4557 bnapi->rx_pg_cons = 0;
4558 }
4559}
4560
4561static void
Michael Chan59b47d82006-11-19 14:10:45 -08004562bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
4563{
4564 u32 val, offset0, offset1, offset2, offset3;
Michael Chan62a83132008-01-29 21:35:40 -08004565 u32 cid_addr = GET_CID_ADDR(cid);
Michael Chan59b47d82006-11-19 14:10:45 -08004566
4567 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4568 offset0 = BNX2_L2CTX_TYPE_XI;
4569 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4570 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4571 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4572 } else {
4573 offset0 = BNX2_L2CTX_TYPE;
4574 offset1 = BNX2_L2CTX_CMD_TYPE;
4575 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4576 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4577 }
4578 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
Michael Chan62a83132008-01-29 21:35:40 -08004579 bnx2_ctx_wr(bp, cid_addr, offset0, val);
Michael Chan59b47d82006-11-19 14:10:45 -08004580
4581 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
Michael Chan62a83132008-01-29 21:35:40 -08004582 bnx2_ctx_wr(bp, cid_addr, offset1, val);
Michael Chan59b47d82006-11-19 14:10:45 -08004583
4584 val = (u64) bp->tx_desc_mapping >> 32;
Michael Chan62a83132008-01-29 21:35:40 -08004585 bnx2_ctx_wr(bp, cid_addr, offset2, val);
Michael Chan59b47d82006-11-19 14:10:45 -08004586
4587 val = (u64) bp->tx_desc_mapping & 0xffffffff;
Michael Chan62a83132008-01-29 21:35:40 -08004588 bnx2_ctx_wr(bp, cid_addr, offset3, val);
Michael Chan59b47d82006-11-19 14:10:45 -08004589}
Michael Chanb6016b72005-05-26 13:03:09 -07004590
4591static void
4592bnx2_init_tx_ring(struct bnx2 *bp)
4593{
4594 struct tx_bd *txbd;
Michael Chanc76c0472007-12-20 20:01:19 -08004595 u32 cid = TX_CID;
4596 struct bnx2_napi *bnapi;
4597
4598 bp->tx_vec = 0;
David S. Millerf86e82f2008-01-21 17:15:40 -08004599 if (bp->flags & BNX2_FLAG_USING_MSIX) {
Michael Chanc76c0472007-12-20 20:01:19 -08004600 cid = TX_TSS_CID;
4601 bp->tx_vec = BNX2_TX_VEC;
4602 REG_WR(bp, BNX2_TSCH_TSS_CFG, BNX2_TX_INT_NUM |
4603 (TX_TSS_CID << 7));
4604 }
4605 bnapi = &bp->bnx2_napi[bp->tx_vec];
Michael Chanb6016b72005-05-26 13:03:09 -07004606
Michael Chan2f8af122006-08-15 01:39:10 -07004607 bp->tx_wake_thresh = bp->tx_ring_size / 2;
4608
Michael Chanb6016b72005-05-26 13:03:09 -07004609 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004610
Michael Chanb6016b72005-05-26 13:03:09 -07004611 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
4612 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
4613
4614 bp->tx_prod = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07004615 bp->tx_prod_bseq = 0;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04004616
Michael Chan59b47d82006-11-19 14:10:45 -08004617 bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4618 bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
Michael Chanb6016b72005-05-26 13:03:09 -07004619
Michael Chan59b47d82006-11-19 14:10:45 -08004620 bnx2_init_tx_context(bp, cid);
Michael Chanb6016b72005-05-26 13:03:09 -07004621}
4622
4623static void
Michael Chan5d5d0012007-12-12 11:17:43 -08004624bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4625 int num_rings)
Michael Chanb6016b72005-05-26 13:03:09 -07004626{
Michael Chanb6016b72005-05-26 13:03:09 -07004627 int i;
Michael Chan5d5d0012007-12-12 11:17:43 -08004628 struct rx_bd *rxbd;
Michael Chanb6016b72005-05-26 13:03:09 -07004629
Michael Chan5d5d0012007-12-12 11:17:43 -08004630 for (i = 0; i < num_rings; i++) {
Michael Chan13daffa2006-03-20 17:49:20 -08004631 int j;
Michael Chanb6016b72005-05-26 13:03:09 -07004632
Michael Chan5d5d0012007-12-12 11:17:43 -08004633 rxbd = &rx_ring[i][0];
Michael Chan13daffa2006-03-20 17:49:20 -08004634 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
Michael Chan5d5d0012007-12-12 11:17:43 -08004635 rxbd->rx_bd_len = buf_size;
Michael Chan13daffa2006-03-20 17:49:20 -08004636 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4637 }
Michael Chan5d5d0012007-12-12 11:17:43 -08004638 if (i == (num_rings - 1))
Michael Chan13daffa2006-03-20 17:49:20 -08004639 j = 0;
4640 else
4641 j = i + 1;
Michael Chan5d5d0012007-12-12 11:17:43 -08004642 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4643 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
Michael Chan13daffa2006-03-20 17:49:20 -08004644 }
Michael Chan5d5d0012007-12-12 11:17:43 -08004645}
4646
4647static void
4648bnx2_init_rx_ring(struct bnx2 *bp)
4649{
4650 int i;
4651 u16 prod, ring_prod;
4652 u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
Michael Chanb4b36042007-12-20 19:59:30 -08004653 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
Michael Chan5d5d0012007-12-12 11:17:43 -08004654
Michael Chan5d5d0012007-12-12 11:17:43 -08004655 bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping,
4656 bp->rx_buf_use_size, bp->rx_max_ring);
4657
Michael Chan83e3fc82008-01-29 21:37:17 -08004658 bnx2_init_rx_context0(bp);
4659
4660 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4661 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4662 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4663 }
4664
Michael Chan62a83132008-01-29 21:35:40 -08004665 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
Michael Chan47bf4242007-12-12 11:19:12 -08004666 if (bp->rx_pg_ring_size) {
4667 bnx2_init_rxbd_rings(bp->rx_pg_desc_ring,
4668 bp->rx_pg_desc_mapping,
4669 PAGE_SIZE, bp->rx_max_pg_ring);
4670 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
Michael Chan62a83132008-01-29 21:35:40 -08004671 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4672 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
Michael Chan47bf4242007-12-12 11:19:12 -08004673 BNX2_L2CTX_RBDC_JUMBO_KEY);
4674
4675 val = (u64) bp->rx_pg_desc_mapping[0] >> 32;
Michael Chan62a83132008-01-29 21:35:40 -08004676 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
Michael Chan47bf4242007-12-12 11:19:12 -08004677
4678 val = (u64) bp->rx_pg_desc_mapping[0] & 0xffffffff;
Michael Chan62a83132008-01-29 21:35:40 -08004679 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
Michael Chan47bf4242007-12-12 11:19:12 -08004680
4681 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4682 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4683 }
Michael Chanb6016b72005-05-26 13:03:09 -07004684
Michael Chan13daffa2006-03-20 17:49:20 -08004685 val = (u64) bp->rx_desc_mapping[0] >> 32;
Michael Chan62a83132008-01-29 21:35:40 -08004686 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
Michael Chanb6016b72005-05-26 13:03:09 -07004687
Michael Chan13daffa2006-03-20 17:49:20 -08004688 val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
Michael Chan62a83132008-01-29 21:35:40 -08004689 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
Michael Chanb6016b72005-05-26 13:03:09 -07004690
Michael Chana1f60192007-12-20 19:57:19 -08004691 ring_prod = prod = bnapi->rx_pg_prod;
Michael Chan47bf4242007-12-12 11:19:12 -08004692 for (i = 0; i < bp->rx_pg_ring_size; i++) {
4693 if (bnx2_alloc_rx_page(bp, ring_prod) < 0)
4694 break;
4695 prod = NEXT_RX_BD(prod);
4696 ring_prod = RX_PG_RING_IDX(prod);
4697 }
Michael Chana1f60192007-12-20 19:57:19 -08004698 bnapi->rx_pg_prod = prod;
Michael Chan47bf4242007-12-12 11:19:12 -08004699
Michael Chana1f60192007-12-20 19:57:19 -08004700 ring_prod = prod = bnapi->rx_prod;
Michael Chan236b6392006-03-20 17:49:02 -08004701 for (i = 0; i < bp->rx_ring_size; i++) {
Michael Chana1f60192007-12-20 19:57:19 -08004702 if (bnx2_alloc_rx_skb(bp, bnapi, ring_prod) < 0) {
Michael Chanb6016b72005-05-26 13:03:09 -07004703 break;
4704 }
4705 prod = NEXT_RX_BD(prod);
4706 ring_prod = RX_RING_IDX(prod);
4707 }
Michael Chana1f60192007-12-20 19:57:19 -08004708 bnapi->rx_prod = prod;
Michael Chanb6016b72005-05-26 13:03:09 -07004709
Michael Chana1f60192007-12-20 19:57:19 -08004710 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX,
4711 bnapi->rx_pg_prod);
Michael Chanb6016b72005-05-26 13:03:09 -07004712 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
4713
Michael Chana1f60192007-12-20 19:57:19 -08004714 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bnapi->rx_prod_bseq);
Michael Chanb6016b72005-05-26 13:03:09 -07004715}
4716
Michael Chan5d5d0012007-12-12 11:17:43 -08004717static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
Michael Chan13daffa2006-03-20 17:49:20 -08004718{
Michael Chan5d5d0012007-12-12 11:17:43 -08004719 u32 max, num_rings = 1;
Michael Chan13daffa2006-03-20 17:49:20 -08004720
Michael Chan5d5d0012007-12-12 11:17:43 -08004721 while (ring_size > MAX_RX_DESC_CNT) {
4722 ring_size -= MAX_RX_DESC_CNT;
Michael Chan13daffa2006-03-20 17:49:20 -08004723 num_rings++;
4724 }
4725 /* round to next power of 2 */
Michael Chan5d5d0012007-12-12 11:17:43 -08004726 max = max_size;
Michael Chan13daffa2006-03-20 17:49:20 -08004727 while ((max & num_rings) == 0)
4728 max >>= 1;
4729
4730 if (num_rings != max)
4731 max <<= 1;
4732
Michael Chan5d5d0012007-12-12 11:17:43 -08004733 return max;
4734}
4735
4736static void
4737bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4738{
Michael Chan84eaa182007-12-12 11:19:57 -08004739 u32 rx_size, rx_space, jumbo_size;
Michael Chan5d5d0012007-12-12 11:17:43 -08004740
4741 /* 8 for CRC and VLAN */
4742 rx_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
4743
Michael Chan84eaa182007-12-12 11:19:57 -08004744 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4745 sizeof(struct skb_shared_info);
4746
Michael Chan5d5d0012007-12-12 11:17:43 -08004747 bp->rx_copy_thresh = RX_COPY_THRESH;
Michael Chan47bf4242007-12-12 11:19:12 -08004748 bp->rx_pg_ring_size = 0;
4749 bp->rx_max_pg_ring = 0;
4750 bp->rx_max_pg_ring_idx = 0;
David S. Millerf86e82f2008-01-21 17:15:40 -08004751 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
Michael Chan84eaa182007-12-12 11:19:57 -08004752 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4753
4754 jumbo_size = size * pages;
4755 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
4756 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
4757
4758 bp->rx_pg_ring_size = jumbo_size;
4759 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
4760 MAX_RX_PG_RINGS);
4761 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
4762 rx_size = RX_COPY_THRESH + bp->rx_offset;
4763 bp->rx_copy_thresh = 0;
4764 }
Michael Chan5d5d0012007-12-12 11:17:43 -08004765
4766 bp->rx_buf_use_size = rx_size;
4767 /* hw alignment */
4768 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
Michael Chan1db82f22007-12-12 11:19:35 -08004769 bp->rx_jumbo_thresh = rx_size - bp->rx_offset;
Michael Chan5d5d0012007-12-12 11:17:43 -08004770 bp->rx_ring_size = size;
4771 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
Michael Chan13daffa2006-03-20 17:49:20 -08004772 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4773}
4774
4775static void
Michael Chanb6016b72005-05-26 13:03:09 -07004776bnx2_free_tx_skbs(struct bnx2 *bp)
4777{
4778 int i;
4779
4780 if (bp->tx_buf_ring == NULL)
4781 return;
4782
4783 for (i = 0; i < TX_DESC_CNT; ) {
4784 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
4785 struct sk_buff *skb = tx_buf->skb;
4786 int j, last;
4787
4788 if (skb == NULL) {
4789 i++;
4790 continue;
4791 }
4792
4793 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
4794 skb_headlen(skb), PCI_DMA_TODEVICE);
4795
4796 tx_buf->skb = NULL;
4797
4798 last = skb_shinfo(skb)->nr_frags;
4799 for (j = 0; j < last; j++) {
4800 tx_buf = &bp->tx_buf_ring[i + j + 1];
4801 pci_unmap_page(bp->pdev,
4802 pci_unmap_addr(tx_buf, mapping),
4803 skb_shinfo(skb)->frags[j].size,
4804 PCI_DMA_TODEVICE);
4805 }
Michael Chan745720e2006-06-29 12:37:41 -07004806 dev_kfree_skb(skb);
Michael Chanb6016b72005-05-26 13:03:09 -07004807 i += j + 1;
4808 }
4809
4810}
4811
4812static void
4813bnx2_free_rx_skbs(struct bnx2 *bp)
4814{
4815 int i;
4816
4817 if (bp->rx_buf_ring == NULL)
4818 return;
4819
Michael Chan13daffa2006-03-20 17:49:20 -08004820 for (i = 0; i < bp->rx_max_ring_idx; i++) {
Michael Chanb6016b72005-05-26 13:03:09 -07004821 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
4822 struct sk_buff *skb = rx_buf->skb;
4823
Michael Chan05d0f1c2005-11-04 08:53:48 -08004824 if (skb == NULL)
Michael Chanb6016b72005-05-26 13:03:09 -07004825 continue;
4826
4827 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
4828 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
4829
4830 rx_buf->skb = NULL;
4831
Michael Chan745720e2006-06-29 12:37:41 -07004832 dev_kfree_skb(skb);
Michael Chanb6016b72005-05-26 13:03:09 -07004833 }
Michael Chan47bf4242007-12-12 11:19:12 -08004834 for (i = 0; i < bp->rx_max_pg_ring_idx; i++)
4835 bnx2_free_rx_page(bp, i);
Michael Chanb6016b72005-05-26 13:03:09 -07004836}
4837
4838static void
4839bnx2_free_skbs(struct bnx2 *bp)
4840{
4841 bnx2_free_tx_skbs(bp);
4842 bnx2_free_rx_skbs(bp);
4843}
4844
4845static int
4846bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
4847{
4848 int rc;
4849
4850 rc = bnx2_reset_chip(bp, reset_code);
4851 bnx2_free_skbs(bp);
4852 if (rc)
4853 return rc;
4854
Michael Chanfba9fe92006-06-12 22:21:25 -07004855 if ((rc = bnx2_init_chip(bp)) != 0)
4856 return rc;
4857
Michael Chanc76c0472007-12-20 20:01:19 -08004858 bnx2_clear_ring_states(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07004859 bnx2_init_tx_ring(bp);
4860 bnx2_init_rx_ring(bp);
4861 return 0;
4862}
4863
4864static int
4865bnx2_init_nic(struct bnx2 *bp)
4866{
4867 int rc;
4868
4869 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
4870 return rc;
4871
Michael Chan80be4432006-11-19 14:07:28 -08004872 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07004873 bnx2_init_phy(bp);
4874 bnx2_set_link(bp);
Michael Chan0d8a6572007-07-07 22:49:43 -07004875 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07004876 return 0;
4877}
4878
4879static int
4880bnx2_test_registers(struct bnx2 *bp)
4881{
4882 int ret;
Michael Chan5bae30c2007-05-03 13:18:46 -07004883 int i, is_5709;
Arjan van de Venf71e1302006-03-03 21:33:57 -05004884 static const struct {
Michael Chanb6016b72005-05-26 13:03:09 -07004885 u16 offset;
4886 u16 flags;
Michael Chan5bae30c2007-05-03 13:18:46 -07004887#define BNX2_FL_NOT_5709 1
Michael Chanb6016b72005-05-26 13:03:09 -07004888 u32 rw_mask;
4889 u32 ro_mask;
4890 } reg_tbl[] = {
4891 { 0x006c, 0, 0x00000000, 0x0000003f },
4892 { 0x0090, 0, 0xffffffff, 0x00000000 },
4893 { 0x0094, 0, 0x00000000, 0x00000000 },
4894
Michael Chan5bae30c2007-05-03 13:18:46 -07004895 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
4896 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4897 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4898 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
4899 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
4900 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4901 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
4902 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4903 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
Michael Chanb6016b72005-05-26 13:03:09 -07004904
Michael Chan5bae30c2007-05-03 13:18:46 -07004905 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4906 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4907 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4908 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4909 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4910 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
Michael Chanb6016b72005-05-26 13:03:09 -07004911
Michael Chan5bae30c2007-05-03 13:18:46 -07004912 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4913 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
4914 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07004915
4916 { 0x1000, 0, 0x00000000, 0x00000001 },
4917 { 0x1004, 0, 0x00000000, 0x000f0001 },
Michael Chanb6016b72005-05-26 13:03:09 -07004918
4919 { 0x1408, 0, 0x01c00800, 0x00000000 },
4920 { 0x149c, 0, 0x8000ffff, 0x00000000 },
4921 { 0x14a8, 0, 0x00000000, 0x000001ff },
Michael Chan5b0c76a2005-11-04 08:45:49 -08004922 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07004923 { 0x14b0, 0, 0x00000002, 0x00000001 },
4924 { 0x14b8, 0, 0x00000000, 0x00000000 },
4925 { 0x14c0, 0, 0x00000000, 0x00000009 },
4926 { 0x14c4, 0, 0x00003fff, 0x00000000 },
4927 { 0x14cc, 0, 0x00000000, 0x00000001 },
4928 { 0x14d0, 0, 0xffffffff, 0x00000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07004929
4930 { 0x1800, 0, 0x00000000, 0x00000001 },
4931 { 0x1804, 0, 0x00000000, 0x00000003 },
Michael Chanb6016b72005-05-26 13:03:09 -07004932
4933 { 0x2800, 0, 0x00000000, 0x00000001 },
4934 { 0x2804, 0, 0x00000000, 0x00003f01 },
4935 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
4936 { 0x2810, 0, 0xffff0000, 0x00000000 },
4937 { 0x2814, 0, 0xffff0000, 0x00000000 },
4938 { 0x2818, 0, 0xffff0000, 0x00000000 },
4939 { 0x281c, 0, 0xffff0000, 0x00000000 },
4940 { 0x2834, 0, 0xffffffff, 0x00000000 },
4941 { 0x2840, 0, 0x00000000, 0xffffffff },
4942 { 0x2844, 0, 0x00000000, 0xffffffff },
4943 { 0x2848, 0, 0xffffffff, 0x00000000 },
4944 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
4945
4946 { 0x2c00, 0, 0x00000000, 0x00000011 },
4947 { 0x2c04, 0, 0x00000000, 0x00030007 },
4948
Michael Chanb6016b72005-05-26 13:03:09 -07004949 { 0x3c00, 0, 0x00000000, 0x00000001 },
4950 { 0x3c04, 0, 0x00000000, 0x00070000 },
4951 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
4952 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
4953 { 0x3c10, 0, 0xffffffff, 0x00000000 },
4954 { 0x3c14, 0, 0x00000000, 0xffffffff },
4955 { 0x3c18, 0, 0x00000000, 0xffffffff },
4956 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
4957 { 0x3c20, 0, 0xffffff00, 0x00000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07004958
4959 { 0x5004, 0, 0x00000000, 0x0000007f },
4960 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
Michael Chanb6016b72005-05-26 13:03:09 -07004961
Michael Chanb6016b72005-05-26 13:03:09 -07004962 { 0x5c00, 0, 0x00000000, 0x00000001 },
4963 { 0x5c04, 0, 0x00000000, 0x0003000f },
4964 { 0x5c08, 0, 0x00000003, 0x00000000 },
4965 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
4966 { 0x5c10, 0, 0x00000000, 0xffffffff },
4967 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
4968 { 0x5c84, 0, 0x00000000, 0x0000f333 },
4969 { 0x5c88, 0, 0x00000000, 0x00077373 },
4970 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
4971
4972 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
4973 { 0x680c, 0, 0xffffffff, 0x00000000 },
4974 { 0x6810, 0, 0xffffffff, 0x00000000 },
4975 { 0x6814, 0, 0xffffffff, 0x00000000 },
4976 { 0x6818, 0, 0xffffffff, 0x00000000 },
4977 { 0x681c, 0, 0xffffffff, 0x00000000 },
4978 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
4979 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
4980 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
4981 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
4982 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
4983 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
4984 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
4985 { 0x683c, 0, 0x0000ffff, 0x00000000 },
4986 { 0x6840, 0, 0x00000ff0, 0x00000000 },
4987 { 0x6844, 0, 0x00ffff00, 0x00000000 },
4988 { 0x684c, 0, 0xffffffff, 0x00000000 },
4989 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
4990 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
4991 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
4992 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
4993 { 0x6908, 0, 0x00000000, 0x0001ff0f },
4994 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
4995
4996 { 0xffff, 0, 0x00000000, 0x00000000 },
4997 };
4998
4999 ret = 0;
Michael Chan5bae30c2007-05-03 13:18:46 -07005000 is_5709 = 0;
5001 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5002 is_5709 = 1;
5003
Michael Chanb6016b72005-05-26 13:03:09 -07005004 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5005 u32 offset, rw_mask, ro_mask, save_val, val;
Michael Chan5bae30c2007-05-03 13:18:46 -07005006 u16 flags = reg_tbl[i].flags;
5007
5008 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5009 continue;
Michael Chanb6016b72005-05-26 13:03:09 -07005010
5011 offset = (u32) reg_tbl[i].offset;
5012 rw_mask = reg_tbl[i].rw_mask;
5013 ro_mask = reg_tbl[i].ro_mask;
5014
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005015 save_val = readl(bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005016
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005017 writel(0, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005018
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005019 val = readl(bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005020 if ((val & rw_mask) != 0) {
5021 goto reg_test_err;
5022 }
5023
5024 if ((val & ro_mask) != (save_val & ro_mask)) {
5025 goto reg_test_err;
5026 }
5027
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005028 writel(0xffffffff, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005029
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005030 val = readl(bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005031 if ((val & rw_mask) != rw_mask) {
5032 goto reg_test_err;
5033 }
5034
5035 if ((val & ro_mask) != (save_val & ro_mask)) {
5036 goto reg_test_err;
5037 }
5038
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005039 writel(save_val, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005040 continue;
5041
5042reg_test_err:
Peter Hagervall14ab9b82005-08-10 14:18:16 -07005043 writel(save_val, bp->regview + offset);
Michael Chanb6016b72005-05-26 13:03:09 -07005044 ret = -ENODEV;
5045 break;
5046 }
5047 return ret;
5048}
5049
5050static int
5051bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5052{
Arjan van de Venf71e1302006-03-03 21:33:57 -05005053 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
Michael Chanb6016b72005-05-26 13:03:09 -07005054 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5055 int i;
5056
5057 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5058 u32 offset;
5059
5060 for (offset = 0; offset < size; offset += 4) {
5061
Michael Chan2726d6e2008-01-29 21:35:05 -08005062 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
Michael Chanb6016b72005-05-26 13:03:09 -07005063
Michael Chan2726d6e2008-01-29 21:35:05 -08005064 if (bnx2_reg_rd_ind(bp, start + offset) !=
Michael Chanb6016b72005-05-26 13:03:09 -07005065 test_pattern[i]) {
5066 return -ENODEV;
5067 }
5068 }
5069 }
5070 return 0;
5071}
5072
5073static int
5074bnx2_test_memory(struct bnx2 *bp)
5075{
5076 int ret = 0;
5077 int i;
Michael Chan5bae30c2007-05-03 13:18:46 -07005078 static struct mem_entry {
Michael Chanb6016b72005-05-26 13:03:09 -07005079 u32 offset;
5080 u32 len;
Michael Chan5bae30c2007-05-03 13:18:46 -07005081 } mem_tbl_5706[] = {
Michael Chanb6016b72005-05-26 13:03:09 -07005082 { 0x60000, 0x4000 },
Michael Chan5b0c76a2005-11-04 08:45:49 -08005083 { 0xa0000, 0x3000 },
Michael Chanb6016b72005-05-26 13:03:09 -07005084 { 0xe0000, 0x4000 },
5085 { 0x120000, 0x4000 },
5086 { 0x1a0000, 0x4000 },
5087 { 0x160000, 0x4000 },
5088 { 0xffffffff, 0 },
Michael Chan5bae30c2007-05-03 13:18:46 -07005089 },
5090 mem_tbl_5709[] = {
5091 { 0x60000, 0x4000 },
5092 { 0xa0000, 0x3000 },
5093 { 0xe0000, 0x4000 },
5094 { 0x120000, 0x4000 },
5095 { 0x1a0000, 0x4000 },
5096 { 0xffffffff, 0 },
Michael Chanb6016b72005-05-26 13:03:09 -07005097 };
Michael Chan5bae30c2007-05-03 13:18:46 -07005098 struct mem_entry *mem_tbl;
5099
5100 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5101 mem_tbl = mem_tbl_5709;
5102 else
5103 mem_tbl = mem_tbl_5706;
Michael Chanb6016b72005-05-26 13:03:09 -07005104
5105 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5106 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5107 mem_tbl[i].len)) != 0) {
5108 return ret;
5109 }
5110 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005111
Michael Chanb6016b72005-05-26 13:03:09 -07005112 return ret;
5113}
5114
Michael Chanbc5a0692006-01-23 16:13:22 -08005115#define BNX2_MAC_LOOPBACK 0
5116#define BNX2_PHY_LOOPBACK 1
5117
Michael Chanb6016b72005-05-26 13:03:09 -07005118static int
Michael Chanbc5a0692006-01-23 16:13:22 -08005119bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
Michael Chanb6016b72005-05-26 13:03:09 -07005120{
5121 unsigned int pkt_size, num_pkts, i;
5122 struct sk_buff *skb, *rx_skb;
5123 unsigned char *packet;
Michael Chanbc5a0692006-01-23 16:13:22 -08005124 u16 rx_start_idx, rx_idx;
Michael Chanb6016b72005-05-26 13:03:09 -07005125 dma_addr_t map;
5126 struct tx_bd *txbd;
5127 struct sw_bd *rx_buf;
5128 struct l2_fhdr *rx_hdr;
5129 int ret = -ENODEV;
Michael Chanc76c0472007-12-20 20:01:19 -08005130 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5131
5132 tx_napi = bnapi;
David S. Millerf86e82f2008-01-21 17:15:40 -08005133 if (bp->flags & BNX2_FLAG_USING_MSIX)
Michael Chanc76c0472007-12-20 20:01:19 -08005134 tx_napi = &bp->bnx2_napi[BNX2_TX_VEC];
Michael Chanb6016b72005-05-26 13:03:09 -07005135
Michael Chanbc5a0692006-01-23 16:13:22 -08005136 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5137 bp->loopback = MAC_LOOPBACK;
5138 bnx2_set_mac_loopback(bp);
5139 }
5140 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
Michael Chan583c28e2008-01-21 19:51:35 -08005141 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan489310a2007-10-10 16:16:31 -07005142 return 0;
5143
Michael Chan80be4432006-11-19 14:07:28 -08005144 bp->loopback = PHY_LOOPBACK;
Michael Chanbc5a0692006-01-23 16:13:22 -08005145 bnx2_set_phy_loopback(bp);
5146 }
5147 else
5148 return -EINVAL;
Michael Chanb6016b72005-05-26 13:03:09 -07005149
Michael Chan84eaa182007-12-12 11:19:57 -08005150 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
Michael Chan932f3772006-08-15 01:39:36 -07005151 skb = netdev_alloc_skb(bp->dev, pkt_size);
John W. Linvilleb6cbc3b62005-11-10 12:58:00 -08005152 if (!skb)
5153 return -ENOMEM;
Michael Chanb6016b72005-05-26 13:03:09 -07005154 packet = skb_put(skb, pkt_size);
Michael Chan66342922006-12-14 15:57:04 -08005155 memcpy(packet, bp->dev->dev_addr, 6);
Michael Chanb6016b72005-05-26 13:03:09 -07005156 memset(packet + 6, 0x0, 8);
5157 for (i = 14; i < pkt_size; i++)
5158 packet[i] = (unsigned char) (i & 0xff);
5159
5160 map = pci_map_single(bp->pdev, skb->data, pkt_size,
5161 PCI_DMA_TODEVICE);
5162
Michael Chanbf5295b2006-03-23 01:11:56 -08005163 REG_WR(bp, BNX2_HC_COMMAND,
5164 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5165
Michael Chanb6016b72005-05-26 13:03:09 -07005166 REG_RD(bp, BNX2_HC_COMMAND);
5167
5168 udelay(5);
Michael Chan35efa7c2007-12-20 19:56:37 -08005169 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
Michael Chanb6016b72005-05-26 13:03:09 -07005170
Michael Chanb6016b72005-05-26 13:03:09 -07005171 num_pkts = 0;
5172
Michael Chanbc5a0692006-01-23 16:13:22 -08005173 txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
Michael Chanb6016b72005-05-26 13:03:09 -07005174
5175 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5176 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5177 txbd->tx_bd_mss_nbytes = pkt_size;
5178 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5179
5180 num_pkts++;
Michael Chanbc5a0692006-01-23 16:13:22 -08005181 bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
5182 bp->tx_prod_bseq += pkt_size;
Michael Chanb6016b72005-05-26 13:03:09 -07005183
Michael Chan234754d2006-11-19 14:11:41 -08005184 REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod);
5185 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
Michael Chanb6016b72005-05-26 13:03:09 -07005186
5187 udelay(100);
5188
Michael Chanbf5295b2006-03-23 01:11:56 -08005189 REG_WR(bp, BNX2_HC_COMMAND,
5190 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5191
Michael Chanb6016b72005-05-26 13:03:09 -07005192 REG_RD(bp, BNX2_HC_COMMAND);
5193
5194 udelay(5);
5195
5196 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
Michael Chan745720e2006-06-29 12:37:41 -07005197 dev_kfree_skb(skb);
Michael Chanb6016b72005-05-26 13:03:09 -07005198
Michael Chanc76c0472007-12-20 20:01:19 -08005199 if (bnx2_get_hw_tx_cons(tx_napi) != bp->tx_prod)
Michael Chanb6016b72005-05-26 13:03:09 -07005200 goto loopback_test_done;
Michael Chanb6016b72005-05-26 13:03:09 -07005201
Michael Chan35efa7c2007-12-20 19:56:37 -08005202 rx_idx = bnx2_get_hw_rx_cons(bnapi);
Michael Chanb6016b72005-05-26 13:03:09 -07005203 if (rx_idx != rx_start_idx + num_pkts) {
5204 goto loopback_test_done;
5205 }
5206
5207 rx_buf = &bp->rx_buf_ring[rx_start_idx];
5208 rx_skb = rx_buf->skb;
5209
5210 rx_hdr = (struct l2_fhdr *) rx_skb->data;
5211 skb_reserve(rx_skb, bp->rx_offset);
5212
5213 pci_dma_sync_single_for_cpu(bp->pdev,
5214 pci_unmap_addr(rx_buf, mapping),
5215 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5216
Michael Chanade2bfe2006-01-23 16:09:51 -08005217 if (rx_hdr->l2_fhdr_status &
Michael Chanb6016b72005-05-26 13:03:09 -07005218 (L2_FHDR_ERRORS_BAD_CRC |
5219 L2_FHDR_ERRORS_PHY_DECODE |
5220 L2_FHDR_ERRORS_ALIGNMENT |
5221 L2_FHDR_ERRORS_TOO_SHORT |
5222 L2_FHDR_ERRORS_GIANT_FRAME)) {
5223
5224 goto loopback_test_done;
5225 }
5226
5227 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5228 goto loopback_test_done;
5229 }
5230
5231 for (i = 14; i < pkt_size; i++) {
5232 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5233 goto loopback_test_done;
5234 }
5235 }
5236
5237 ret = 0;
5238
5239loopback_test_done:
5240 bp->loopback = 0;
5241 return ret;
5242}
5243
Michael Chanbc5a0692006-01-23 16:13:22 -08005244#define BNX2_MAC_LOOPBACK_FAILED 1
5245#define BNX2_PHY_LOOPBACK_FAILED 2
5246#define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5247 BNX2_PHY_LOOPBACK_FAILED)
5248
5249static int
5250bnx2_test_loopback(struct bnx2 *bp)
5251{
5252 int rc = 0;
5253
5254 if (!netif_running(bp->dev))
5255 return BNX2_LOOPBACK_FAILED;
5256
5257 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5258 spin_lock_bh(&bp->phy_lock);
5259 bnx2_init_phy(bp);
5260 spin_unlock_bh(&bp->phy_lock);
5261 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5262 rc |= BNX2_MAC_LOOPBACK_FAILED;
5263 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5264 rc |= BNX2_PHY_LOOPBACK_FAILED;
5265 return rc;
5266}
5267
Michael Chanb6016b72005-05-26 13:03:09 -07005268#define NVRAM_SIZE 0x200
5269#define CRC32_RESIDUAL 0xdebb20e3
5270
5271static int
5272bnx2_test_nvram(struct bnx2 *bp)
5273{
Al Virob491edd2007-12-22 19:44:51 +00005274 __be32 buf[NVRAM_SIZE / 4];
Michael Chanb6016b72005-05-26 13:03:09 -07005275 u8 *data = (u8 *) buf;
5276 int rc = 0;
5277 u32 magic, csum;
5278
5279 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5280 goto test_nvram_done;
5281
5282 magic = be32_to_cpu(buf[0]);
5283 if (magic != 0x669955aa) {
5284 rc = -ENODEV;
5285 goto test_nvram_done;
5286 }
5287
5288 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5289 goto test_nvram_done;
5290
5291 csum = ether_crc_le(0x100, data);
5292 if (csum != CRC32_RESIDUAL) {
5293 rc = -ENODEV;
5294 goto test_nvram_done;
5295 }
5296
5297 csum = ether_crc_le(0x100, data + 0x100);
5298 if (csum != CRC32_RESIDUAL) {
5299 rc = -ENODEV;
5300 }
5301
5302test_nvram_done:
5303 return rc;
5304}
5305
5306static int
5307bnx2_test_link(struct bnx2 *bp)
5308{
5309 u32 bmsr;
5310
Michael Chan583c28e2008-01-21 19:51:35 -08005311 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
Michael Chan489310a2007-10-10 16:16:31 -07005312 if (bp->link_up)
5313 return 0;
5314 return -ENODEV;
5315 }
Michael Chanc770a652005-08-25 15:38:39 -07005316 spin_lock_bh(&bp->phy_lock);
Michael Chan27a005b2007-05-03 13:23:41 -07005317 bnx2_enable_bmsr1(bp);
5318 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5319 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5320 bnx2_disable_bmsr1(bp);
Michael Chanc770a652005-08-25 15:38:39 -07005321 spin_unlock_bh(&bp->phy_lock);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005322
Michael Chanb6016b72005-05-26 13:03:09 -07005323 if (bmsr & BMSR_LSTATUS) {
5324 return 0;
5325 }
5326 return -ENODEV;
5327}
5328
5329static int
5330bnx2_test_intr(struct bnx2 *bp)
5331{
5332 int i;
Michael Chanb6016b72005-05-26 13:03:09 -07005333 u16 status_idx;
5334
5335 if (!netif_running(bp->dev))
5336 return -ENODEV;
5337
5338 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5339
5340 /* This register is not touched during run-time. */
Michael Chanbf5295b2006-03-23 01:11:56 -08005341 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
Michael Chanb6016b72005-05-26 13:03:09 -07005342 REG_RD(bp, BNX2_HC_COMMAND);
5343
5344 for (i = 0; i < 10; i++) {
5345 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5346 status_idx) {
5347
5348 break;
5349 }
5350
5351 msleep_interruptible(10);
5352 }
5353 if (i < 10)
5354 return 0;
5355
5356 return -ENODEV;
5357}
5358
Michael Chanb2fadea2008-01-21 17:07:06 -08005359static int
5360bnx2_5706_serdes_has_link(struct bnx2 *bp)
5361{
5362 u32 mode_ctl, an_dbg, exp;
5363
5364 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5365 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5366
5367 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5368 return 0;
5369
5370 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5371 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5372 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5373
Michael Chanf3014c02008-01-29 21:33:03 -08005374 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
Michael Chanb2fadea2008-01-21 17:07:06 -08005375 return 0;
5376
5377 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5378 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5379 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5380
5381 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5382 return 0;
5383
5384 return 1;
5385}
5386
Michael Chanb6016b72005-05-26 13:03:09 -07005387static void
Michael Chan48b01e22006-11-19 14:08:00 -08005388bnx2_5706_serdes_timer(struct bnx2 *bp)
5389{
Michael Chanb2fadea2008-01-21 17:07:06 -08005390 int check_link = 1;
5391
Michael Chan48b01e22006-11-19 14:08:00 -08005392 spin_lock(&bp->phy_lock);
Michael Chan583c28e2008-01-21 19:51:35 -08005393 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
Michael Chanb2fadea2008-01-21 17:07:06 -08005394 bnx2_5706s_force_link_dn(bp, 0);
Michael Chan583c28e2008-01-21 19:51:35 -08005395 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
Michael Chanb2fadea2008-01-21 17:07:06 -08005396 spin_unlock(&bp->phy_lock);
5397 return;
5398 }
5399
5400 if (bp->serdes_an_pending) {
Michael Chan48b01e22006-11-19 14:08:00 -08005401 bp->serdes_an_pending--;
Michael Chanb2fadea2008-01-21 17:07:06 -08005402 check_link = 0;
5403 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
Michael Chan48b01e22006-11-19 14:08:00 -08005404 u32 bmcr;
5405
5406 bp->current_interval = bp->timer_interval;
5407
Michael Chanca58c3a2007-05-03 13:22:52 -07005408 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chan48b01e22006-11-19 14:08:00 -08005409
5410 if (bmcr & BMCR_ANENABLE) {
Michael Chanb2fadea2008-01-21 17:07:06 -08005411 if (bnx2_5706_serdes_has_link(bp)) {
Michael Chan48b01e22006-11-19 14:08:00 -08005412 bmcr &= ~BMCR_ANENABLE;
5413 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
Michael Chanca58c3a2007-05-03 13:22:52 -07005414 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
Michael Chan583c28e2008-01-21 19:51:35 -08005415 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
Michael Chan48b01e22006-11-19 14:08:00 -08005416 }
5417 }
5418 }
5419 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
Michael Chan583c28e2008-01-21 19:51:35 -08005420 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
Michael Chan48b01e22006-11-19 14:08:00 -08005421 u32 phy2;
5422
Michael Chanb2fadea2008-01-21 17:07:06 -08005423 check_link = 0;
Michael Chan48b01e22006-11-19 14:08:00 -08005424 bnx2_write_phy(bp, 0x17, 0x0f01);
5425 bnx2_read_phy(bp, 0x15, &phy2);
5426 if (phy2 & 0x20) {
5427 u32 bmcr;
5428
Michael Chanca58c3a2007-05-03 13:22:52 -07005429 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chan48b01e22006-11-19 14:08:00 -08005430 bmcr |= BMCR_ANENABLE;
Michael Chanca58c3a2007-05-03 13:22:52 -07005431 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
Michael Chan48b01e22006-11-19 14:08:00 -08005432
Michael Chan583c28e2008-01-21 19:51:35 -08005433 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
Michael Chan48b01e22006-11-19 14:08:00 -08005434 }
5435 } else
5436 bp->current_interval = bp->timer_interval;
5437
Michael Chanb2fadea2008-01-21 17:07:06 -08005438 if (bp->link_up && (bp->autoneg & AUTONEG_SPEED) && check_link) {
5439 u32 val;
5440
5441 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5442 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5443 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5444
5445 if (val & MISC_SHDW_AN_DBG_NOSYNC) {
5446 bnx2_5706s_force_link_dn(bp, 1);
Michael Chan583c28e2008-01-21 19:51:35 -08005447 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
Michael Chanb2fadea2008-01-21 17:07:06 -08005448 }
5449 }
Michael Chan48b01e22006-11-19 14:08:00 -08005450 spin_unlock(&bp->phy_lock);
5451}
5452
5453static void
Michael Chanf8dd0642006-11-19 14:08:29 -08005454bnx2_5708_serdes_timer(struct bnx2 *bp)
5455{
Michael Chan583c28e2008-01-21 19:51:35 -08005456 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan0d8a6572007-07-07 22:49:43 -07005457 return;
5458
Michael Chan583c28e2008-01-21 19:51:35 -08005459 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
Michael Chanf8dd0642006-11-19 14:08:29 -08005460 bp->serdes_an_pending = 0;
5461 return;
5462 }
5463
5464 spin_lock(&bp->phy_lock);
5465 if (bp->serdes_an_pending)
5466 bp->serdes_an_pending--;
5467 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5468 u32 bmcr;
5469
Michael Chanca58c3a2007-05-03 13:22:52 -07005470 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanf8dd0642006-11-19 14:08:29 -08005471 if (bmcr & BMCR_ANENABLE) {
Michael Chan605a9e22007-05-03 13:23:13 -07005472 bnx2_enable_forced_2g5(bp);
Michael Chanf8dd0642006-11-19 14:08:29 -08005473 bp->current_interval = SERDES_FORCED_TIMEOUT;
5474 } else {
Michael Chan605a9e22007-05-03 13:23:13 -07005475 bnx2_disable_forced_2g5(bp);
Michael Chanf8dd0642006-11-19 14:08:29 -08005476 bp->serdes_an_pending = 2;
5477 bp->current_interval = bp->timer_interval;
5478 }
5479
5480 } else
5481 bp->current_interval = bp->timer_interval;
5482
5483 spin_unlock(&bp->phy_lock);
5484}
5485
5486static void
Michael Chanb6016b72005-05-26 13:03:09 -07005487bnx2_timer(unsigned long data)
5488{
5489 struct bnx2 *bp = (struct bnx2 *) data;
Michael Chanb6016b72005-05-26 13:03:09 -07005490
Michael Chancd339a02005-08-25 15:35:24 -07005491 if (!netif_running(bp->dev))
5492 return;
5493
Michael Chanb6016b72005-05-26 13:03:09 -07005494 if (atomic_read(&bp->intr_sem) != 0)
5495 goto bnx2_restart_timer;
5496
Michael Chandf149d72007-07-07 22:51:36 -07005497 bnx2_send_heart_beat(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07005498
Michael Chan2726d6e2008-01-29 21:35:05 -08005499 bp->stats_blk->stat_FwRxDrop =
5500 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
Michael Chancea94db2006-06-12 22:16:13 -07005501
Michael Chan02537b062007-06-04 21:24:07 -07005502 /* workaround occasional corrupted counters */
5503 if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5504 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5505 BNX2_HC_COMMAND_STATS_NOW);
5506
Michael Chan583c28e2008-01-21 19:51:35 -08005507 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanf8dd0642006-11-19 14:08:29 -08005508 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5509 bnx2_5706_serdes_timer(bp);
Michael Chan27a005b2007-05-03 13:23:41 -07005510 else
Michael Chanf8dd0642006-11-19 14:08:29 -08005511 bnx2_5708_serdes_timer(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07005512 }
5513
5514bnx2_restart_timer:
Michael Chancd339a02005-08-25 15:35:24 -07005515 mod_timer(&bp->timer, jiffies + bp->current_interval);
Michael Chanb6016b72005-05-26 13:03:09 -07005516}
5517
Michael Chan8e6a72c2007-05-03 13:24:48 -07005518static int
5519bnx2_request_irq(struct bnx2 *bp)
5520{
5521 struct net_device *dev = bp->dev;
Michael Chan6d866ff2007-12-20 19:56:09 -08005522 unsigned long flags;
Michael Chanb4b36042007-12-20 19:59:30 -08005523 struct bnx2_irq *irq;
5524 int rc = 0, i;
Michael Chan8e6a72c2007-05-03 13:24:48 -07005525
David S. Millerf86e82f2008-01-21 17:15:40 -08005526 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
Michael Chan6d866ff2007-12-20 19:56:09 -08005527 flags = 0;
5528 else
5529 flags = IRQF_SHARED;
Michael Chanb4b36042007-12-20 19:59:30 -08005530
5531 for (i = 0; i < bp->irq_nvecs; i++) {
5532 irq = &bp->irq_tbl[i];
Michael Chanc76c0472007-12-20 20:01:19 -08005533 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
Michael Chanb4b36042007-12-20 19:59:30 -08005534 dev);
5535 if (rc)
5536 break;
5537 irq->requested = 1;
5538 }
Michael Chan8e6a72c2007-05-03 13:24:48 -07005539 return rc;
5540}
5541
5542static void
5543bnx2_free_irq(struct bnx2 *bp)
5544{
5545 struct net_device *dev = bp->dev;
Michael Chanb4b36042007-12-20 19:59:30 -08005546 struct bnx2_irq *irq;
5547 int i;
Michael Chan8e6a72c2007-05-03 13:24:48 -07005548
Michael Chanb4b36042007-12-20 19:59:30 -08005549 for (i = 0; i < bp->irq_nvecs; i++) {
5550 irq = &bp->irq_tbl[i];
5551 if (irq->requested)
5552 free_irq(irq->vector, dev);
5553 irq->requested = 0;
Michael Chan6d866ff2007-12-20 19:56:09 -08005554 }
David S. Millerf86e82f2008-01-21 17:15:40 -08005555 if (bp->flags & BNX2_FLAG_USING_MSI)
Michael Chanb4b36042007-12-20 19:59:30 -08005556 pci_disable_msi(bp->pdev);
David S. Millerf86e82f2008-01-21 17:15:40 -08005557 else if (bp->flags & BNX2_FLAG_USING_MSIX)
Michael Chanb4b36042007-12-20 19:59:30 -08005558 pci_disable_msix(bp->pdev);
5559
David S. Millerf86e82f2008-01-21 17:15:40 -08005560 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
Michael Chanb4b36042007-12-20 19:59:30 -08005561}
5562
5563static void
5564bnx2_enable_msix(struct bnx2 *bp)
5565{
Michael Chan57851d82007-12-20 20:01:44 -08005566 int i, rc;
5567 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
5568
Michael Chanb4b36042007-12-20 19:59:30 -08005569 bnx2_setup_msix_tbl(bp);
5570 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5571 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5572 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
Michael Chan57851d82007-12-20 20:01:44 -08005573
5574 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5575 msix_ent[i].entry = i;
5576 msix_ent[i].vector = 0;
5577 }
5578
5579 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5580 if (rc != 0)
5581 return;
5582
5583 bp->irq_tbl[BNX2_BASE_VEC].handler = bnx2_msi_1shot;
5584 bp->irq_tbl[BNX2_TX_VEC].handler = bnx2_tx_msix;
5585
5586 strcpy(bp->irq_tbl[BNX2_BASE_VEC].name, bp->dev->name);
5587 strcat(bp->irq_tbl[BNX2_BASE_VEC].name, "-base");
5588 strcpy(bp->irq_tbl[BNX2_TX_VEC].name, bp->dev->name);
5589 strcat(bp->irq_tbl[BNX2_TX_VEC].name, "-tx");
5590
5591 bp->irq_nvecs = BNX2_MAX_MSIX_VEC;
David S. Millerf86e82f2008-01-21 17:15:40 -08005592 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
Michael Chan57851d82007-12-20 20:01:44 -08005593 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5594 bp->irq_tbl[i].vector = msix_ent[i].vector;
Michael Chan6d866ff2007-12-20 19:56:09 -08005595}
5596
5597static void
5598bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5599{
5600 bp->irq_tbl[0].handler = bnx2_interrupt;
5601 strcpy(bp->irq_tbl[0].name, bp->dev->name);
Michael Chanb4b36042007-12-20 19:59:30 -08005602 bp->irq_nvecs = 1;
5603 bp->irq_tbl[0].vector = bp->pdev->irq;
Michael Chan6d866ff2007-12-20 19:56:09 -08005604
David S. Millerf86e82f2008-01-21 17:15:40 -08005605 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi)
Michael Chanb4b36042007-12-20 19:59:30 -08005606 bnx2_enable_msix(bp);
5607
David S. Millerf86e82f2008-01-21 17:15:40 -08005608 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5609 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
Michael Chan6d866ff2007-12-20 19:56:09 -08005610 if (pci_enable_msi(bp->pdev) == 0) {
David S. Millerf86e82f2008-01-21 17:15:40 -08005611 bp->flags |= BNX2_FLAG_USING_MSI;
Michael Chan6d866ff2007-12-20 19:56:09 -08005612 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
David S. Millerf86e82f2008-01-21 17:15:40 -08005613 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
Michael Chan6d866ff2007-12-20 19:56:09 -08005614 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5615 } else
5616 bp->irq_tbl[0].handler = bnx2_msi;
Michael Chanb4b36042007-12-20 19:59:30 -08005617
5618 bp->irq_tbl[0].vector = bp->pdev->irq;
Michael Chan6d866ff2007-12-20 19:56:09 -08005619 }
5620 }
Michael Chan8e6a72c2007-05-03 13:24:48 -07005621}
5622
Michael Chanb6016b72005-05-26 13:03:09 -07005623/* Called with rtnl_lock */
5624static int
5625bnx2_open(struct net_device *dev)
5626{
Michael Chan972ec0d2006-01-23 16:12:43 -08005627 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07005628 int rc;
5629
Michael Chan1b2f9222007-05-03 13:20:19 -07005630 netif_carrier_off(dev);
5631
Pavel Machek829ca9a2005-09-03 15:56:56 -07005632 bnx2_set_power_state(bp, PCI_D0);
Michael Chanb6016b72005-05-26 13:03:09 -07005633 bnx2_disable_int(bp);
5634
5635 rc = bnx2_alloc_mem(bp);
5636 if (rc)
5637 return rc;
5638
Michael Chan6d866ff2007-12-20 19:56:09 -08005639 bnx2_setup_int_mode(bp, disable_msi);
Michael Chan35efa7c2007-12-20 19:56:37 -08005640 bnx2_napi_enable(bp);
Michael Chan8e6a72c2007-05-03 13:24:48 -07005641 rc = bnx2_request_irq(bp);
5642
Michael Chanb6016b72005-05-26 13:03:09 -07005643 if (rc) {
Michael Chan35efa7c2007-12-20 19:56:37 -08005644 bnx2_napi_disable(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07005645 bnx2_free_mem(bp);
5646 return rc;
5647 }
5648
5649 rc = bnx2_init_nic(bp);
5650
5651 if (rc) {
Michael Chan35efa7c2007-12-20 19:56:37 -08005652 bnx2_napi_disable(bp);
Michael Chan8e6a72c2007-05-03 13:24:48 -07005653 bnx2_free_irq(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07005654 bnx2_free_skbs(bp);
5655 bnx2_free_mem(bp);
5656 return rc;
5657 }
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005658
Michael Chancd339a02005-08-25 15:35:24 -07005659 mod_timer(&bp->timer, jiffies + bp->current_interval);
Michael Chanb6016b72005-05-26 13:03:09 -07005660
5661 atomic_set(&bp->intr_sem, 0);
5662
5663 bnx2_enable_int(bp);
5664
David S. Millerf86e82f2008-01-21 17:15:40 -08005665 if (bp->flags & BNX2_FLAG_USING_MSI) {
Michael Chanb6016b72005-05-26 13:03:09 -07005666 /* Test MSI to make sure it is working
5667 * If MSI test fails, go back to INTx mode
5668 */
5669 if (bnx2_test_intr(bp) != 0) {
5670 printk(KERN_WARNING PFX "%s: No interrupt was generated"
5671 " using MSI, switching to INTx mode. Please"
5672 " report this failure to the PCI maintainer"
5673 " and include system chipset information.\n",
5674 bp->dev->name);
5675
5676 bnx2_disable_int(bp);
Michael Chan8e6a72c2007-05-03 13:24:48 -07005677 bnx2_free_irq(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07005678
Michael Chan6d866ff2007-12-20 19:56:09 -08005679 bnx2_setup_int_mode(bp, 1);
5680
Michael Chanb6016b72005-05-26 13:03:09 -07005681 rc = bnx2_init_nic(bp);
5682
Michael Chan8e6a72c2007-05-03 13:24:48 -07005683 if (!rc)
5684 rc = bnx2_request_irq(bp);
5685
Michael Chanb6016b72005-05-26 13:03:09 -07005686 if (rc) {
Michael Chan35efa7c2007-12-20 19:56:37 -08005687 bnx2_napi_disable(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07005688 bnx2_free_skbs(bp);
5689 bnx2_free_mem(bp);
5690 del_timer_sync(&bp->timer);
5691 return rc;
5692 }
5693 bnx2_enable_int(bp);
5694 }
5695 }
David S. Millerf86e82f2008-01-21 17:15:40 -08005696 if (bp->flags & BNX2_FLAG_USING_MSI)
Michael Chanb6016b72005-05-26 13:03:09 -07005697 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
David S. Millerf86e82f2008-01-21 17:15:40 -08005698 else if (bp->flags & BNX2_FLAG_USING_MSIX)
Michael Chan57851d82007-12-20 20:01:44 -08005699 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
Michael Chanb6016b72005-05-26 13:03:09 -07005700
5701 netif_start_queue(dev);
5702
5703 return 0;
5704}
5705
5706static void
David Howellsc4028952006-11-22 14:57:56 +00005707bnx2_reset_task(struct work_struct *work)
Michael Chanb6016b72005-05-26 13:03:09 -07005708{
David Howellsc4028952006-11-22 14:57:56 +00005709 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
Michael Chanb6016b72005-05-26 13:03:09 -07005710
Michael Chanafdc08b2005-08-25 15:34:29 -07005711 if (!netif_running(bp->dev))
5712 return;
5713
5714 bp->in_reset_task = 1;
Michael Chanb6016b72005-05-26 13:03:09 -07005715 bnx2_netif_stop(bp);
5716
5717 bnx2_init_nic(bp);
5718
5719 atomic_set(&bp->intr_sem, 1);
5720 bnx2_netif_start(bp);
Michael Chanafdc08b2005-08-25 15:34:29 -07005721 bp->in_reset_task = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07005722}
5723
5724static void
5725bnx2_tx_timeout(struct net_device *dev)
5726{
Michael Chan972ec0d2006-01-23 16:12:43 -08005727 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07005728
5729 /* This allows the netif to be shutdown gracefully before resetting */
5730 schedule_work(&bp->reset_task);
5731}
5732
5733#ifdef BCM_VLAN
5734/* Called with rtnl_lock */
5735static void
5736bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5737{
Michael Chan972ec0d2006-01-23 16:12:43 -08005738 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07005739
5740 bnx2_netif_stop(bp);
5741
5742 bp->vlgrp = vlgrp;
5743 bnx2_set_rx_mode(dev);
5744
5745 bnx2_netif_start(bp);
5746}
Michael Chanb6016b72005-05-26 13:03:09 -07005747#endif
5748
Herbert Xu932ff272006-06-09 12:20:56 -07005749/* Called with netif_tx_lock.
Michael Chan2f8af122006-08-15 01:39:10 -07005750 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5751 * netif_wake_queue().
Michael Chanb6016b72005-05-26 13:03:09 -07005752 */
5753static int
5754bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5755{
Michael Chan972ec0d2006-01-23 16:12:43 -08005756 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07005757 dma_addr_t mapping;
5758 struct tx_bd *txbd;
5759 struct sw_bd *tx_buf;
5760 u32 len, vlan_tag_flags, last_frag, mss;
5761 u16 prod, ring_prod;
5762 int i;
Michael Chan57851d82007-12-20 20:01:44 -08005763 struct bnx2_napi *bnapi = &bp->bnx2_napi[bp->tx_vec];
Michael Chanb6016b72005-05-26 13:03:09 -07005764
Michael Chana550c992007-12-20 19:56:59 -08005765 if (unlikely(bnx2_tx_avail(bp, bnapi) <
5766 (skb_shinfo(skb)->nr_frags + 1))) {
Michael Chanb6016b72005-05-26 13:03:09 -07005767 netif_stop_queue(dev);
5768 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5769 dev->name);
5770
5771 return NETDEV_TX_BUSY;
5772 }
5773 len = skb_headlen(skb);
5774 prod = bp->tx_prod;
5775 ring_prod = TX_RING_IDX(prod);
5776
5777 vlan_tag_flags = 0;
Patrick McHardy84fa7932006-08-29 16:44:56 -07005778 if (skb->ip_summed == CHECKSUM_PARTIAL) {
Michael Chanb6016b72005-05-26 13:03:09 -07005779 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5780 }
5781
Al Viro79ea13c2008-01-24 02:06:46 -08005782 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
Michael Chanb6016b72005-05-26 13:03:09 -07005783 vlan_tag_flags |=
5784 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
5785 }
Michael Chanfde82052007-05-03 17:23:35 -07005786 if ((mss = skb_shinfo(skb)->gso_size)) {
Michael Chanb6016b72005-05-26 13:03:09 -07005787 u32 tcp_opt_len, ip_tcp_len;
Arnaldo Carvalho de Meloeddc9ec2007-04-20 22:47:35 -07005788 struct iphdr *iph;
Michael Chanb6016b72005-05-26 13:03:09 -07005789
Michael Chanb6016b72005-05-26 13:03:09 -07005790 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
5791
Michael Chan4666f872007-05-03 13:22:28 -07005792 tcp_opt_len = tcp_optlen(skb);
Arnaldo Carvalho de Meloab6a5bb2007-03-18 17:43:48 -07005793
Michael Chan4666f872007-05-03 13:22:28 -07005794 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5795 u32 tcp_off = skb_transport_offset(skb) -
5796 sizeof(struct ipv6hdr) - ETH_HLEN;
Michael Chanb6016b72005-05-26 13:03:09 -07005797
Michael Chan4666f872007-05-03 13:22:28 -07005798 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
5799 TX_BD_FLAGS_SW_FLAGS;
5800 if (likely(tcp_off == 0))
5801 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
5802 else {
5803 tcp_off >>= 3;
5804 vlan_tag_flags |= ((tcp_off & 0x3) <<
5805 TX_BD_FLAGS_TCP6_OFF0_SHL) |
5806 ((tcp_off & 0x10) <<
5807 TX_BD_FLAGS_TCP6_OFF4_SHL);
5808 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
5809 }
5810 } else {
5811 if (skb_header_cloned(skb) &&
5812 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5813 dev_kfree_skb(skb);
5814 return NETDEV_TX_OK;
5815 }
5816
5817 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5818
5819 iph = ip_hdr(skb);
5820 iph->check = 0;
5821 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5822 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5823 iph->daddr, 0,
5824 IPPROTO_TCP,
5825 0);
5826 if (tcp_opt_len || (iph->ihl > 5)) {
5827 vlan_tag_flags |= ((iph->ihl - 5) +
5828 (tcp_opt_len >> 2)) << 8;
5829 }
Michael Chanb6016b72005-05-26 13:03:09 -07005830 }
Michael Chan4666f872007-05-03 13:22:28 -07005831 } else
Michael Chanb6016b72005-05-26 13:03:09 -07005832 mss = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07005833
5834 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005835
Michael Chanb6016b72005-05-26 13:03:09 -07005836 tx_buf = &bp->tx_buf_ring[ring_prod];
5837 tx_buf->skb = skb;
5838 pci_unmap_addr_set(tx_buf, mapping, mapping);
5839
5840 txbd = &bp->tx_desc_ring[ring_prod];
5841
5842 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5843 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5844 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5845 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
5846
5847 last_frag = skb_shinfo(skb)->nr_frags;
5848
5849 for (i = 0; i < last_frag; i++) {
5850 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5851
5852 prod = NEXT_TX_BD(prod);
5853 ring_prod = TX_RING_IDX(prod);
5854 txbd = &bp->tx_desc_ring[ring_prod];
5855
5856 len = frag->size;
5857 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
5858 len, PCI_DMA_TODEVICE);
5859 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
5860 mapping, mapping);
5861
5862 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5863 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5864 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5865 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
5866
5867 }
5868 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
5869
5870 prod = NEXT_TX_BD(prod);
5871 bp->tx_prod_bseq += skb->len;
5872
Michael Chan234754d2006-11-19 14:11:41 -08005873 REG_WR16(bp, bp->tx_bidx_addr, prod);
5874 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
Michael Chanb6016b72005-05-26 13:03:09 -07005875
5876 mmiowb();
5877
5878 bp->tx_prod = prod;
5879 dev->trans_start = jiffies;
5880
Michael Chana550c992007-12-20 19:56:59 -08005881 if (unlikely(bnx2_tx_avail(bp, bnapi) <= MAX_SKB_FRAGS)) {
Michael Chane89bbf12005-08-25 15:36:58 -07005882 netif_stop_queue(dev);
Michael Chana550c992007-12-20 19:56:59 -08005883 if (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)
Michael Chane89bbf12005-08-25 15:36:58 -07005884 netif_wake_queue(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07005885 }
5886
5887 return NETDEV_TX_OK;
5888}
5889
5890/* Called with rtnl_lock */
5891static int
5892bnx2_close(struct net_device *dev)
5893{
Michael Chan972ec0d2006-01-23 16:12:43 -08005894 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07005895 u32 reset_code;
5896
Michael Chanafdc08b2005-08-25 15:34:29 -07005897 /* Calling flush_scheduled_work() may deadlock because
5898 * linkwatch_event() may be on the workqueue and it will try to get
5899 * the rtnl_lock which we are holding.
5900 */
5901 while (bp->in_reset_task)
5902 msleep(1);
5903
Stephen Hemmingerbea33482007-10-03 16:41:36 -07005904 bnx2_disable_int_sync(bp);
Michael Chan35efa7c2007-12-20 19:56:37 -08005905 bnx2_napi_disable(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07005906 del_timer_sync(&bp->timer);
David S. Millerf86e82f2008-01-21 17:15:40 -08005907 if (bp->flags & BNX2_FLAG_NO_WOL)
Michael Chan6c4f0952006-06-29 12:38:15 -07005908 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
Michael Chandda1e392006-01-23 16:08:14 -08005909 else if (bp->wol)
Michael Chanb6016b72005-05-26 13:03:09 -07005910 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5911 else
5912 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5913 bnx2_reset_chip(bp, reset_code);
Michael Chan8e6a72c2007-05-03 13:24:48 -07005914 bnx2_free_irq(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07005915 bnx2_free_skbs(bp);
5916 bnx2_free_mem(bp);
5917 bp->link_up = 0;
5918 netif_carrier_off(bp->dev);
Pavel Machek829ca9a2005-09-03 15:56:56 -07005919 bnx2_set_power_state(bp, PCI_D3hot);
Michael Chanb6016b72005-05-26 13:03:09 -07005920 return 0;
5921}
5922
5923#define GET_NET_STATS64(ctr) \
5924 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
5925 (unsigned long) (ctr##_lo)
5926
5927#define GET_NET_STATS32(ctr) \
5928 (ctr##_lo)
5929
5930#if (BITS_PER_LONG == 64)
5931#define GET_NET_STATS GET_NET_STATS64
5932#else
5933#define GET_NET_STATS GET_NET_STATS32
5934#endif
5935
5936static struct net_device_stats *
5937bnx2_get_stats(struct net_device *dev)
5938{
Michael Chan972ec0d2006-01-23 16:12:43 -08005939 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07005940 struct statistics_block *stats_blk = bp->stats_blk;
5941 struct net_device_stats *net_stats = &bp->net_stats;
5942
5943 if (bp->stats_blk == NULL) {
5944 return net_stats;
5945 }
5946 net_stats->rx_packets =
5947 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
5948 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
5949 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
5950
5951 net_stats->tx_packets =
5952 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
5953 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
5954 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
5955
5956 net_stats->rx_bytes =
5957 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
5958
5959 net_stats->tx_bytes =
5960 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
5961
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005962 net_stats->multicast =
Michael Chanb6016b72005-05-26 13:03:09 -07005963 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
5964
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005965 net_stats->collisions =
Michael Chanb6016b72005-05-26 13:03:09 -07005966 (unsigned long) stats_blk->stat_EtherStatsCollisions;
5967
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005968 net_stats->rx_length_errors =
Michael Chanb6016b72005-05-26 13:03:09 -07005969 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
5970 stats_blk->stat_EtherStatsOverrsizePkts);
5971
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005972 net_stats->rx_over_errors =
Michael Chanb6016b72005-05-26 13:03:09 -07005973 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
5974
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005975 net_stats->rx_frame_errors =
Michael Chanb6016b72005-05-26 13:03:09 -07005976 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
5977
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005978 net_stats->rx_crc_errors =
Michael Chanb6016b72005-05-26 13:03:09 -07005979 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
5980
5981 net_stats->rx_errors = net_stats->rx_length_errors +
5982 net_stats->rx_over_errors + net_stats->rx_frame_errors +
5983 net_stats->rx_crc_errors;
5984
5985 net_stats->tx_aborted_errors =
5986 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
5987 stats_blk->stat_Dot3StatsLateCollisions);
5988
Michael Chan5b0c76a2005-11-04 08:45:49 -08005989 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
5990 (CHIP_ID(bp) == CHIP_ID_5708_A0))
Michael Chanb6016b72005-05-26 13:03:09 -07005991 net_stats->tx_carrier_errors = 0;
5992 else {
5993 net_stats->tx_carrier_errors =
5994 (unsigned long)
5995 stats_blk->stat_Dot3StatsCarrierSenseErrors;
5996 }
5997
5998 net_stats->tx_errors =
Jeff Garzik6aa20a22006-09-13 13:24:59 -04005999 (unsigned long)
Michael Chanb6016b72005-05-26 13:03:09 -07006000 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6001 +
6002 net_stats->tx_aborted_errors +
6003 net_stats->tx_carrier_errors;
6004
Michael Chancea94db2006-06-12 22:16:13 -07006005 net_stats->rx_missed_errors =
6006 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
6007 stats_blk->stat_FwRxDrop);
6008
Michael Chanb6016b72005-05-26 13:03:09 -07006009 return net_stats;
6010}
6011
6012/* All ethtool functions called with rtnl_lock */
6013
6014static int
6015bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6016{
Michael Chan972ec0d2006-01-23 16:12:43 -08006017 struct bnx2 *bp = netdev_priv(dev);
Michael Chan7b6b8342007-07-07 22:50:15 -07006018 int support_serdes = 0, support_copper = 0;
Michael Chanb6016b72005-05-26 13:03:09 -07006019
6020 cmd->supported = SUPPORTED_Autoneg;
Michael Chan583c28e2008-01-21 19:51:35 -08006021 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
Michael Chan7b6b8342007-07-07 22:50:15 -07006022 support_serdes = 1;
6023 support_copper = 1;
6024 } else if (bp->phy_port == PORT_FIBRE)
6025 support_serdes = 1;
6026 else
6027 support_copper = 1;
6028
6029 if (support_serdes) {
Michael Chanb6016b72005-05-26 13:03:09 -07006030 cmd->supported |= SUPPORTED_1000baseT_Full |
6031 SUPPORTED_FIBRE;
Michael Chan583c28e2008-01-21 19:51:35 -08006032 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
Michael Chan605a9e22007-05-03 13:23:13 -07006033 cmd->supported |= SUPPORTED_2500baseX_Full;
Michael Chanb6016b72005-05-26 13:03:09 -07006034
Michael Chanb6016b72005-05-26 13:03:09 -07006035 }
Michael Chan7b6b8342007-07-07 22:50:15 -07006036 if (support_copper) {
Michael Chanb6016b72005-05-26 13:03:09 -07006037 cmd->supported |= SUPPORTED_10baseT_Half |
6038 SUPPORTED_10baseT_Full |
6039 SUPPORTED_100baseT_Half |
6040 SUPPORTED_100baseT_Full |
6041 SUPPORTED_1000baseT_Full |
6042 SUPPORTED_TP;
6043
Michael Chanb6016b72005-05-26 13:03:09 -07006044 }
6045
Michael Chan7b6b8342007-07-07 22:50:15 -07006046 spin_lock_bh(&bp->phy_lock);
6047 cmd->port = bp->phy_port;
Michael Chanb6016b72005-05-26 13:03:09 -07006048 cmd->advertising = bp->advertising;
6049
6050 if (bp->autoneg & AUTONEG_SPEED) {
6051 cmd->autoneg = AUTONEG_ENABLE;
6052 }
6053 else {
6054 cmd->autoneg = AUTONEG_DISABLE;
6055 }
6056
6057 if (netif_carrier_ok(dev)) {
6058 cmd->speed = bp->line_speed;
6059 cmd->duplex = bp->duplex;
6060 }
6061 else {
6062 cmd->speed = -1;
6063 cmd->duplex = -1;
6064 }
Michael Chan7b6b8342007-07-07 22:50:15 -07006065 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006066
6067 cmd->transceiver = XCVR_INTERNAL;
6068 cmd->phy_address = bp->phy_addr;
6069
6070 return 0;
6071}
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006072
Michael Chanb6016b72005-05-26 13:03:09 -07006073static int
6074bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6075{
Michael Chan972ec0d2006-01-23 16:12:43 -08006076 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006077 u8 autoneg = bp->autoneg;
6078 u8 req_duplex = bp->req_duplex;
6079 u16 req_line_speed = bp->req_line_speed;
6080 u32 advertising = bp->advertising;
Michael Chan7b6b8342007-07-07 22:50:15 -07006081 int err = -EINVAL;
6082
6083 spin_lock_bh(&bp->phy_lock);
6084
6085 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6086 goto err_out_unlock;
6087
Michael Chan583c28e2008-01-21 19:51:35 -08006088 if (cmd->port != bp->phy_port &&
6089 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
Michael Chan7b6b8342007-07-07 22:50:15 -07006090 goto err_out_unlock;
Michael Chanb6016b72005-05-26 13:03:09 -07006091
6092 if (cmd->autoneg == AUTONEG_ENABLE) {
6093 autoneg |= AUTONEG_SPEED;
6094
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006095 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
Michael Chanb6016b72005-05-26 13:03:09 -07006096
6097 /* allow advertising 1 speed */
6098 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6099 (cmd->advertising == ADVERTISED_10baseT_Full) ||
6100 (cmd->advertising == ADVERTISED_100baseT_Half) ||
6101 (cmd->advertising == ADVERTISED_100baseT_Full)) {
6102
Michael Chan7b6b8342007-07-07 22:50:15 -07006103 if (cmd->port == PORT_FIBRE)
6104 goto err_out_unlock;
Michael Chanb6016b72005-05-26 13:03:09 -07006105
6106 advertising = cmd->advertising;
6107
Michael Chan27a005b2007-05-03 13:23:41 -07006108 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
Michael Chan583c28e2008-01-21 19:51:35 -08006109 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
Michael Chan7b6b8342007-07-07 22:50:15 -07006110 (cmd->port == PORT_TP))
6111 goto err_out_unlock;
6112 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
Michael Chanb6016b72005-05-26 13:03:09 -07006113 advertising = cmd->advertising;
Michael Chan7b6b8342007-07-07 22:50:15 -07006114 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6115 goto err_out_unlock;
Michael Chanb6016b72005-05-26 13:03:09 -07006116 else {
Michael Chan7b6b8342007-07-07 22:50:15 -07006117 if (cmd->port == PORT_FIBRE)
Michael Chanb6016b72005-05-26 13:03:09 -07006118 advertising = ETHTOOL_ALL_FIBRE_SPEED;
Michael Chan7b6b8342007-07-07 22:50:15 -07006119 else
Michael Chanb6016b72005-05-26 13:03:09 -07006120 advertising = ETHTOOL_ALL_COPPER_SPEED;
Michael Chanb6016b72005-05-26 13:03:09 -07006121 }
6122 advertising |= ADVERTISED_Autoneg;
6123 }
6124 else {
Michael Chan7b6b8342007-07-07 22:50:15 -07006125 if (cmd->port == PORT_FIBRE) {
Michael Chan80be4432006-11-19 14:07:28 -08006126 if ((cmd->speed != SPEED_1000 &&
6127 cmd->speed != SPEED_2500) ||
6128 (cmd->duplex != DUPLEX_FULL))
Michael Chan7b6b8342007-07-07 22:50:15 -07006129 goto err_out_unlock;
Michael Chan80be4432006-11-19 14:07:28 -08006130
6131 if (cmd->speed == SPEED_2500 &&
Michael Chan583c28e2008-01-21 19:51:35 -08006132 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
Michael Chan7b6b8342007-07-07 22:50:15 -07006133 goto err_out_unlock;
Michael Chanb6016b72005-05-26 13:03:09 -07006134 }
Michael Chan7b6b8342007-07-07 22:50:15 -07006135 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6136 goto err_out_unlock;
6137
Michael Chanb6016b72005-05-26 13:03:09 -07006138 autoneg &= ~AUTONEG_SPEED;
6139 req_line_speed = cmd->speed;
6140 req_duplex = cmd->duplex;
6141 advertising = 0;
6142 }
6143
6144 bp->autoneg = autoneg;
6145 bp->advertising = advertising;
6146 bp->req_line_speed = req_line_speed;
6147 bp->req_duplex = req_duplex;
6148
Michael Chan7b6b8342007-07-07 22:50:15 -07006149 err = bnx2_setup_phy(bp, cmd->port);
Michael Chanb6016b72005-05-26 13:03:09 -07006150
Michael Chan7b6b8342007-07-07 22:50:15 -07006151err_out_unlock:
Michael Chanc770a652005-08-25 15:38:39 -07006152 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006153
Michael Chan7b6b8342007-07-07 22:50:15 -07006154 return err;
Michael Chanb6016b72005-05-26 13:03:09 -07006155}
6156
6157static void
6158bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6159{
Michael Chan972ec0d2006-01-23 16:12:43 -08006160 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006161
6162 strcpy(info->driver, DRV_MODULE_NAME);
6163 strcpy(info->version, DRV_MODULE_VERSION);
6164 strcpy(info->bus_info, pci_name(bp->pdev));
Michael Chan58fc2ea2007-07-07 22:52:02 -07006165 strcpy(info->fw_version, bp->fw_version);
Michael Chanb6016b72005-05-26 13:03:09 -07006166}
6167
Michael Chan244ac4f2006-03-20 17:48:46 -08006168#define BNX2_REGDUMP_LEN (32 * 1024)
6169
6170static int
6171bnx2_get_regs_len(struct net_device *dev)
6172{
6173 return BNX2_REGDUMP_LEN;
6174}
6175
6176static void
6177bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6178{
6179 u32 *p = _p, i, offset;
6180 u8 *orig_p = _p;
6181 struct bnx2 *bp = netdev_priv(dev);
6182 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6183 0x0800, 0x0880, 0x0c00, 0x0c10,
6184 0x0c30, 0x0d08, 0x1000, 0x101c,
6185 0x1040, 0x1048, 0x1080, 0x10a4,
6186 0x1400, 0x1490, 0x1498, 0x14f0,
6187 0x1500, 0x155c, 0x1580, 0x15dc,
6188 0x1600, 0x1658, 0x1680, 0x16d8,
6189 0x1800, 0x1820, 0x1840, 0x1854,
6190 0x1880, 0x1894, 0x1900, 0x1984,
6191 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6192 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6193 0x2000, 0x2030, 0x23c0, 0x2400,
6194 0x2800, 0x2820, 0x2830, 0x2850,
6195 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6196 0x3c00, 0x3c94, 0x4000, 0x4010,
6197 0x4080, 0x4090, 0x43c0, 0x4458,
6198 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6199 0x4fc0, 0x5010, 0x53c0, 0x5444,
6200 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6201 0x5fc0, 0x6000, 0x6400, 0x6428,
6202 0x6800, 0x6848, 0x684c, 0x6860,
6203 0x6888, 0x6910, 0x8000 };
6204
6205 regs->version = 0;
6206
6207 memset(p, 0, BNX2_REGDUMP_LEN);
6208
6209 if (!netif_running(bp->dev))
6210 return;
6211
6212 i = 0;
6213 offset = reg_boundaries[0];
6214 p += offset;
6215 while (offset < BNX2_REGDUMP_LEN) {
6216 *p++ = REG_RD(bp, offset);
6217 offset += 4;
6218 if (offset == reg_boundaries[i + 1]) {
6219 offset = reg_boundaries[i + 2];
6220 p = (u32 *) (orig_p + offset);
6221 i += 2;
6222 }
6223 }
6224}
6225
Michael Chanb6016b72005-05-26 13:03:09 -07006226static void
6227bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6228{
Michael Chan972ec0d2006-01-23 16:12:43 -08006229 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006230
David S. Millerf86e82f2008-01-21 17:15:40 -08006231 if (bp->flags & BNX2_FLAG_NO_WOL) {
Michael Chanb6016b72005-05-26 13:03:09 -07006232 wol->supported = 0;
6233 wol->wolopts = 0;
6234 }
6235 else {
6236 wol->supported = WAKE_MAGIC;
6237 if (bp->wol)
6238 wol->wolopts = WAKE_MAGIC;
6239 else
6240 wol->wolopts = 0;
6241 }
6242 memset(&wol->sopass, 0, sizeof(wol->sopass));
6243}
6244
6245static int
6246bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6247{
Michael Chan972ec0d2006-01-23 16:12:43 -08006248 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006249
6250 if (wol->wolopts & ~WAKE_MAGIC)
6251 return -EINVAL;
6252
6253 if (wol->wolopts & WAKE_MAGIC) {
David S. Millerf86e82f2008-01-21 17:15:40 -08006254 if (bp->flags & BNX2_FLAG_NO_WOL)
Michael Chanb6016b72005-05-26 13:03:09 -07006255 return -EINVAL;
6256
6257 bp->wol = 1;
6258 }
6259 else {
6260 bp->wol = 0;
6261 }
6262 return 0;
6263}
6264
6265static int
6266bnx2_nway_reset(struct net_device *dev)
6267{
Michael Chan972ec0d2006-01-23 16:12:43 -08006268 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006269 u32 bmcr;
6270
6271 if (!(bp->autoneg & AUTONEG_SPEED)) {
6272 return -EINVAL;
6273 }
6274
Michael Chanc770a652005-08-25 15:38:39 -07006275 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006276
Michael Chan583c28e2008-01-21 19:51:35 -08006277 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
Michael Chan7b6b8342007-07-07 22:50:15 -07006278 int rc;
6279
6280 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6281 spin_unlock_bh(&bp->phy_lock);
6282 return rc;
6283 }
6284
Michael Chanb6016b72005-05-26 13:03:09 -07006285 /* Force a link down visible on the other side */
Michael Chan583c28e2008-01-21 19:51:35 -08006286 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chanca58c3a2007-05-03 13:22:52 -07006287 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
Michael Chanc770a652005-08-25 15:38:39 -07006288 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006289
6290 msleep(20);
6291
Michael Chanc770a652005-08-25 15:38:39 -07006292 spin_lock_bh(&bp->phy_lock);
Michael Chanf8dd0642006-11-19 14:08:29 -08006293
6294 bp->current_interval = SERDES_AN_TIMEOUT;
6295 bp->serdes_an_pending = 1;
6296 mod_timer(&bp->timer, jiffies + bp->current_interval);
Michael Chanb6016b72005-05-26 13:03:09 -07006297 }
6298
Michael Chanca58c3a2007-05-03 13:22:52 -07006299 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
Michael Chanb6016b72005-05-26 13:03:09 -07006300 bmcr &= ~BMCR_LOOPBACK;
Michael Chanca58c3a2007-05-03 13:22:52 -07006301 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
Michael Chanb6016b72005-05-26 13:03:09 -07006302
Michael Chanc770a652005-08-25 15:38:39 -07006303 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006304
6305 return 0;
6306}
6307
6308static int
6309bnx2_get_eeprom_len(struct net_device *dev)
6310{
Michael Chan972ec0d2006-01-23 16:12:43 -08006311 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006312
Michael Chan1122db72006-01-23 16:11:42 -08006313 if (bp->flash_info == NULL)
Michael Chanb6016b72005-05-26 13:03:09 -07006314 return 0;
6315
Michael Chan1122db72006-01-23 16:11:42 -08006316 return (int) bp->flash_size;
Michael Chanb6016b72005-05-26 13:03:09 -07006317}
6318
6319static int
6320bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6321 u8 *eebuf)
6322{
Michael Chan972ec0d2006-01-23 16:12:43 -08006323 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006324 int rc;
6325
John W. Linville1064e942005-11-10 12:58:24 -08006326 /* parameters already validated in ethtool_get_eeprom */
Michael Chanb6016b72005-05-26 13:03:09 -07006327
6328 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6329
6330 return rc;
6331}
6332
6333static int
6334bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6335 u8 *eebuf)
6336{
Michael Chan972ec0d2006-01-23 16:12:43 -08006337 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006338 int rc;
6339
John W. Linville1064e942005-11-10 12:58:24 -08006340 /* parameters already validated in ethtool_set_eeprom */
Michael Chanb6016b72005-05-26 13:03:09 -07006341
6342 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6343
6344 return rc;
6345}
6346
6347static int
6348bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6349{
Michael Chan972ec0d2006-01-23 16:12:43 -08006350 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006351
6352 memset(coal, 0, sizeof(struct ethtool_coalesce));
6353
6354 coal->rx_coalesce_usecs = bp->rx_ticks;
6355 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6356 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6357 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6358
6359 coal->tx_coalesce_usecs = bp->tx_ticks;
6360 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6361 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6362 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6363
6364 coal->stats_block_coalesce_usecs = bp->stats_ticks;
6365
6366 return 0;
6367}
6368
6369static int
6370bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6371{
Michael Chan972ec0d2006-01-23 16:12:43 -08006372 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006373
6374 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6375 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6376
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006377 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
Michael Chanb6016b72005-05-26 13:03:09 -07006378 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6379
6380 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6381 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6382
6383 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6384 if (bp->rx_quick_cons_trip_int > 0xff)
6385 bp->rx_quick_cons_trip_int = 0xff;
6386
6387 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6388 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6389
6390 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6391 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6392
6393 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6394 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6395
6396 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6397 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6398 0xff;
6399
6400 bp->stats_ticks = coal->stats_block_coalesce_usecs;
Michael Chan02537b062007-06-04 21:24:07 -07006401 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6402 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6403 bp->stats_ticks = USEC_PER_SEC;
6404 }
Michael Chan7ea69202007-07-16 18:27:10 -07006405 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6406 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6407 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
Michael Chanb6016b72005-05-26 13:03:09 -07006408
6409 if (netif_running(bp->dev)) {
6410 bnx2_netif_stop(bp);
6411 bnx2_init_nic(bp);
6412 bnx2_netif_start(bp);
6413 }
6414
6415 return 0;
6416}
6417
6418static void
6419bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6420{
Michael Chan972ec0d2006-01-23 16:12:43 -08006421 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006422
Michael Chan13daffa2006-03-20 17:49:20 -08006423 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
Michael Chanb6016b72005-05-26 13:03:09 -07006424 ering->rx_mini_max_pending = 0;
Michael Chan47bf4242007-12-12 11:19:12 -08006425 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
Michael Chanb6016b72005-05-26 13:03:09 -07006426
6427 ering->rx_pending = bp->rx_ring_size;
6428 ering->rx_mini_pending = 0;
Michael Chan47bf4242007-12-12 11:19:12 -08006429 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
Michael Chanb6016b72005-05-26 13:03:09 -07006430
6431 ering->tx_max_pending = MAX_TX_DESC_CNT;
6432 ering->tx_pending = bp->tx_ring_size;
6433}
6434
6435static int
Michael Chan5d5d0012007-12-12 11:17:43 -08006436bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
Michael Chanb6016b72005-05-26 13:03:09 -07006437{
Michael Chan13daffa2006-03-20 17:49:20 -08006438 if (netif_running(bp->dev)) {
6439 bnx2_netif_stop(bp);
6440 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6441 bnx2_free_skbs(bp);
6442 bnx2_free_mem(bp);
6443 }
6444
Michael Chan5d5d0012007-12-12 11:17:43 -08006445 bnx2_set_rx_ring_size(bp, rx);
6446 bp->tx_ring_size = tx;
Michael Chanb6016b72005-05-26 13:03:09 -07006447
6448 if (netif_running(bp->dev)) {
Michael Chan13daffa2006-03-20 17:49:20 -08006449 int rc;
6450
6451 rc = bnx2_alloc_mem(bp);
6452 if (rc)
6453 return rc;
Michael Chanb6016b72005-05-26 13:03:09 -07006454 bnx2_init_nic(bp);
6455 bnx2_netif_start(bp);
6456 }
Michael Chanb6016b72005-05-26 13:03:09 -07006457 return 0;
6458}
6459
Michael Chan5d5d0012007-12-12 11:17:43 -08006460static int
6461bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6462{
6463 struct bnx2 *bp = netdev_priv(dev);
6464 int rc;
6465
6466 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6467 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6468 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6469
6470 return -EINVAL;
6471 }
6472 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6473 return rc;
6474}
6475
Michael Chanb6016b72005-05-26 13:03:09 -07006476static void
6477bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6478{
Michael Chan972ec0d2006-01-23 16:12:43 -08006479 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006480
6481 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6482 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6483 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6484}
6485
6486static int
6487bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6488{
Michael Chan972ec0d2006-01-23 16:12:43 -08006489 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006490
6491 bp->req_flow_ctrl = 0;
6492 if (epause->rx_pause)
6493 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6494 if (epause->tx_pause)
6495 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6496
6497 if (epause->autoneg) {
6498 bp->autoneg |= AUTONEG_FLOW_CTRL;
6499 }
6500 else {
6501 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6502 }
6503
Michael Chanc770a652005-08-25 15:38:39 -07006504 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006505
Michael Chan0d8a6572007-07-07 22:49:43 -07006506 bnx2_setup_phy(bp, bp->phy_port);
Michael Chanb6016b72005-05-26 13:03:09 -07006507
Michael Chanc770a652005-08-25 15:38:39 -07006508 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006509
6510 return 0;
6511}
6512
6513static u32
6514bnx2_get_rx_csum(struct net_device *dev)
6515{
Michael Chan972ec0d2006-01-23 16:12:43 -08006516 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006517
6518 return bp->rx_csum;
6519}
6520
6521static int
6522bnx2_set_rx_csum(struct net_device *dev, u32 data)
6523{
Michael Chan972ec0d2006-01-23 16:12:43 -08006524 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006525
6526 bp->rx_csum = data;
6527 return 0;
6528}
6529
Michael Chanb11d6212006-06-29 12:31:21 -07006530static int
6531bnx2_set_tso(struct net_device *dev, u32 data)
6532{
Michael Chan4666f872007-05-03 13:22:28 -07006533 struct bnx2 *bp = netdev_priv(dev);
6534
6535 if (data) {
Michael Chanb11d6212006-06-29 12:31:21 -07006536 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
Michael Chan4666f872007-05-03 13:22:28 -07006537 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6538 dev->features |= NETIF_F_TSO6;
6539 } else
6540 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6541 NETIF_F_TSO_ECN);
Michael Chanb11d6212006-06-29 12:31:21 -07006542 return 0;
6543}
6544
Michael Chancea94db2006-06-12 22:16:13 -07006545#define BNX2_NUM_STATS 46
Michael Chanb6016b72005-05-26 13:03:09 -07006546
Peter Hagervall14ab9b82005-08-10 14:18:16 -07006547static struct {
Michael Chanb6016b72005-05-26 13:03:09 -07006548 char string[ETH_GSTRING_LEN];
6549} bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6550 { "rx_bytes" },
6551 { "rx_error_bytes" },
6552 { "tx_bytes" },
6553 { "tx_error_bytes" },
6554 { "rx_ucast_packets" },
6555 { "rx_mcast_packets" },
6556 { "rx_bcast_packets" },
6557 { "tx_ucast_packets" },
6558 { "tx_mcast_packets" },
6559 { "tx_bcast_packets" },
6560 { "tx_mac_errors" },
6561 { "tx_carrier_errors" },
6562 { "rx_crc_errors" },
6563 { "rx_align_errors" },
6564 { "tx_single_collisions" },
6565 { "tx_multi_collisions" },
6566 { "tx_deferred" },
6567 { "tx_excess_collisions" },
6568 { "tx_late_collisions" },
6569 { "tx_total_collisions" },
6570 { "rx_fragments" },
6571 { "rx_jabbers" },
6572 { "rx_undersize_packets" },
6573 { "rx_oversize_packets" },
6574 { "rx_64_byte_packets" },
6575 { "rx_65_to_127_byte_packets" },
6576 { "rx_128_to_255_byte_packets" },
6577 { "rx_256_to_511_byte_packets" },
6578 { "rx_512_to_1023_byte_packets" },
6579 { "rx_1024_to_1522_byte_packets" },
6580 { "rx_1523_to_9022_byte_packets" },
6581 { "tx_64_byte_packets" },
6582 { "tx_65_to_127_byte_packets" },
6583 { "tx_128_to_255_byte_packets" },
6584 { "tx_256_to_511_byte_packets" },
6585 { "tx_512_to_1023_byte_packets" },
6586 { "tx_1024_to_1522_byte_packets" },
6587 { "tx_1523_to_9022_byte_packets" },
6588 { "rx_xon_frames" },
6589 { "rx_xoff_frames" },
6590 { "tx_xon_frames" },
6591 { "tx_xoff_frames" },
6592 { "rx_mac_ctrl_frames" },
6593 { "rx_filtered_packets" },
6594 { "rx_discards" },
Michael Chancea94db2006-06-12 22:16:13 -07006595 { "rx_fw_discards" },
Michael Chanb6016b72005-05-26 13:03:09 -07006596};
6597
6598#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6599
Arjan van de Venf71e1302006-03-03 21:33:57 -05006600static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
Michael Chanb6016b72005-05-26 13:03:09 -07006601 STATS_OFFSET32(stat_IfHCInOctets_hi),
6602 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6603 STATS_OFFSET32(stat_IfHCOutOctets_hi),
6604 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6605 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6606 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6607 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6608 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6609 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6610 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6611 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006612 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6613 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6614 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6615 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6616 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6617 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6618 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6619 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6620 STATS_OFFSET32(stat_EtherStatsCollisions),
6621 STATS_OFFSET32(stat_EtherStatsFragments),
6622 STATS_OFFSET32(stat_EtherStatsJabbers),
6623 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6624 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6625 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6626 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6627 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6628 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6629 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6630 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6631 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6632 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6633 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6634 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6635 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6636 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6637 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6638 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6639 STATS_OFFSET32(stat_XonPauseFramesReceived),
6640 STATS_OFFSET32(stat_XoffPauseFramesReceived),
6641 STATS_OFFSET32(stat_OutXonSent),
6642 STATS_OFFSET32(stat_OutXoffSent),
6643 STATS_OFFSET32(stat_MacControlFramesReceived),
6644 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6645 STATS_OFFSET32(stat_IfInMBUFDiscards),
Michael Chancea94db2006-06-12 22:16:13 -07006646 STATS_OFFSET32(stat_FwRxDrop),
Michael Chanb6016b72005-05-26 13:03:09 -07006647};
6648
6649/* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6650 * skipped because of errata.
Jeff Garzik6aa20a22006-09-13 13:24:59 -04006651 */
Peter Hagervall14ab9b82005-08-10 14:18:16 -07006652static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
Michael Chanb6016b72005-05-26 13:03:09 -07006653 8,0,8,8,8,8,8,8,8,8,
6654 4,0,4,4,4,4,4,4,4,4,
6655 4,4,4,4,4,4,4,4,4,4,
6656 4,4,4,4,4,4,4,4,4,4,
Michael Chancea94db2006-06-12 22:16:13 -07006657 4,4,4,4,4,4,
Michael Chanb6016b72005-05-26 13:03:09 -07006658};
6659
Michael Chan5b0c76a2005-11-04 08:45:49 -08006660static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6661 8,0,8,8,8,8,8,8,8,8,
6662 4,4,4,4,4,4,4,4,4,4,
6663 4,4,4,4,4,4,4,4,4,4,
6664 4,4,4,4,4,4,4,4,4,4,
Michael Chancea94db2006-06-12 22:16:13 -07006665 4,4,4,4,4,4,
Michael Chan5b0c76a2005-11-04 08:45:49 -08006666};
6667
Michael Chanb6016b72005-05-26 13:03:09 -07006668#define BNX2_NUM_TESTS 6
6669
Peter Hagervall14ab9b82005-08-10 14:18:16 -07006670static struct {
Michael Chanb6016b72005-05-26 13:03:09 -07006671 char string[ETH_GSTRING_LEN];
6672} bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6673 { "register_test (offline)" },
6674 { "memory_test (offline)" },
6675 { "loopback_test (offline)" },
6676 { "nvram_test (online)" },
6677 { "interrupt_test (online)" },
6678 { "link_test (online)" },
6679};
6680
6681static int
Jeff Garzikb9f2c042007-10-03 18:07:32 -07006682bnx2_get_sset_count(struct net_device *dev, int sset)
Michael Chanb6016b72005-05-26 13:03:09 -07006683{
Jeff Garzikb9f2c042007-10-03 18:07:32 -07006684 switch (sset) {
6685 case ETH_SS_TEST:
6686 return BNX2_NUM_TESTS;
6687 case ETH_SS_STATS:
6688 return BNX2_NUM_STATS;
6689 default:
6690 return -EOPNOTSUPP;
6691 }
Michael Chanb6016b72005-05-26 13:03:09 -07006692}
6693
6694static void
6695bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6696{
Michael Chan972ec0d2006-01-23 16:12:43 -08006697 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006698
6699 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6700 if (etest->flags & ETH_TEST_FL_OFFLINE) {
Michael Chan80be4432006-11-19 14:07:28 -08006701 int i;
6702
Michael Chanb6016b72005-05-26 13:03:09 -07006703 bnx2_netif_stop(bp);
6704 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6705 bnx2_free_skbs(bp);
6706
6707 if (bnx2_test_registers(bp) != 0) {
6708 buf[0] = 1;
6709 etest->flags |= ETH_TEST_FL_FAILED;
6710 }
6711 if (bnx2_test_memory(bp) != 0) {
6712 buf[1] = 1;
6713 etest->flags |= ETH_TEST_FL_FAILED;
6714 }
Michael Chanbc5a0692006-01-23 16:13:22 -08006715 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
Michael Chanb6016b72005-05-26 13:03:09 -07006716 etest->flags |= ETH_TEST_FL_FAILED;
Michael Chanb6016b72005-05-26 13:03:09 -07006717
6718 if (!netif_running(bp->dev)) {
6719 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6720 }
6721 else {
6722 bnx2_init_nic(bp);
6723 bnx2_netif_start(bp);
6724 }
6725
6726 /* wait for link up */
Michael Chan80be4432006-11-19 14:07:28 -08006727 for (i = 0; i < 7; i++) {
6728 if (bp->link_up)
6729 break;
6730 msleep_interruptible(1000);
6731 }
Michael Chanb6016b72005-05-26 13:03:09 -07006732 }
6733
6734 if (bnx2_test_nvram(bp) != 0) {
6735 buf[3] = 1;
6736 etest->flags |= ETH_TEST_FL_FAILED;
6737 }
6738 if (bnx2_test_intr(bp) != 0) {
6739 buf[4] = 1;
6740 etest->flags |= ETH_TEST_FL_FAILED;
6741 }
6742
6743 if (bnx2_test_link(bp) != 0) {
6744 buf[5] = 1;
6745 etest->flags |= ETH_TEST_FL_FAILED;
6746
6747 }
6748}
6749
6750static void
6751bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6752{
6753 switch (stringset) {
6754 case ETH_SS_STATS:
6755 memcpy(buf, bnx2_stats_str_arr,
6756 sizeof(bnx2_stats_str_arr));
6757 break;
6758 case ETH_SS_TEST:
6759 memcpy(buf, bnx2_tests_str_arr,
6760 sizeof(bnx2_tests_str_arr));
6761 break;
6762 }
6763}
6764
Michael Chanb6016b72005-05-26 13:03:09 -07006765static void
6766bnx2_get_ethtool_stats(struct net_device *dev,
6767 struct ethtool_stats *stats, u64 *buf)
6768{
Michael Chan972ec0d2006-01-23 16:12:43 -08006769 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006770 int i;
6771 u32 *hw_stats = (u32 *) bp->stats_blk;
Peter Hagervall14ab9b82005-08-10 14:18:16 -07006772 u8 *stats_len_arr = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -07006773
6774 if (hw_stats == NULL) {
6775 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
6776 return;
6777 }
6778
Michael Chan5b0c76a2005-11-04 08:45:49 -08006779 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
6780 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
6781 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
6782 (CHIP_ID(bp) == CHIP_ID_5708_A0))
Michael Chanb6016b72005-05-26 13:03:09 -07006783 stats_len_arr = bnx2_5706_stats_len_arr;
Michael Chan5b0c76a2005-11-04 08:45:49 -08006784 else
6785 stats_len_arr = bnx2_5708_stats_len_arr;
Michael Chanb6016b72005-05-26 13:03:09 -07006786
6787 for (i = 0; i < BNX2_NUM_STATS; i++) {
6788 if (stats_len_arr[i] == 0) {
6789 /* skip this counter */
6790 buf[i] = 0;
6791 continue;
6792 }
6793 if (stats_len_arr[i] == 4) {
6794 /* 4-byte counter */
6795 buf[i] = (u64)
6796 *(hw_stats + bnx2_stats_offset_arr[i]);
6797 continue;
6798 }
6799 /* 8-byte counter */
6800 buf[i] = (((u64) *(hw_stats +
6801 bnx2_stats_offset_arr[i])) << 32) +
6802 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
6803 }
6804}
6805
6806static int
6807bnx2_phys_id(struct net_device *dev, u32 data)
6808{
Michael Chan972ec0d2006-01-23 16:12:43 -08006809 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006810 int i;
6811 u32 save;
6812
6813 if (data == 0)
6814 data = 2;
6815
6816 save = REG_RD(bp, BNX2_MISC_CFG);
6817 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
6818
6819 for (i = 0; i < (data * 2); i++) {
6820 if ((i % 2) == 0) {
6821 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
6822 }
6823 else {
6824 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
6825 BNX2_EMAC_LED_1000MB_OVERRIDE |
6826 BNX2_EMAC_LED_100MB_OVERRIDE |
6827 BNX2_EMAC_LED_10MB_OVERRIDE |
6828 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
6829 BNX2_EMAC_LED_TRAFFIC);
6830 }
6831 msleep_interruptible(500);
6832 if (signal_pending(current))
6833 break;
6834 }
6835 REG_WR(bp, BNX2_EMAC_LED, 0);
6836 REG_WR(bp, BNX2_MISC_CFG, save);
6837 return 0;
6838}
6839
Michael Chan4666f872007-05-03 13:22:28 -07006840static int
6841bnx2_set_tx_csum(struct net_device *dev, u32 data)
6842{
6843 struct bnx2 *bp = netdev_priv(dev);
6844
6845 if (CHIP_NUM(bp) == CHIP_NUM_5709)
Michael Chan6460d942007-07-14 19:07:52 -07006846 return (ethtool_op_set_tx_ipv6_csum(dev, data));
Michael Chan4666f872007-05-03 13:22:28 -07006847 else
6848 return (ethtool_op_set_tx_csum(dev, data));
6849}
6850
Jeff Garzik7282d492006-09-13 14:30:00 -04006851static const struct ethtool_ops bnx2_ethtool_ops = {
Michael Chanb6016b72005-05-26 13:03:09 -07006852 .get_settings = bnx2_get_settings,
6853 .set_settings = bnx2_set_settings,
6854 .get_drvinfo = bnx2_get_drvinfo,
Michael Chan244ac4f2006-03-20 17:48:46 -08006855 .get_regs_len = bnx2_get_regs_len,
6856 .get_regs = bnx2_get_regs,
Michael Chanb6016b72005-05-26 13:03:09 -07006857 .get_wol = bnx2_get_wol,
6858 .set_wol = bnx2_set_wol,
6859 .nway_reset = bnx2_nway_reset,
6860 .get_link = ethtool_op_get_link,
6861 .get_eeprom_len = bnx2_get_eeprom_len,
6862 .get_eeprom = bnx2_get_eeprom,
6863 .set_eeprom = bnx2_set_eeprom,
6864 .get_coalesce = bnx2_get_coalesce,
6865 .set_coalesce = bnx2_set_coalesce,
6866 .get_ringparam = bnx2_get_ringparam,
6867 .set_ringparam = bnx2_set_ringparam,
6868 .get_pauseparam = bnx2_get_pauseparam,
6869 .set_pauseparam = bnx2_set_pauseparam,
6870 .get_rx_csum = bnx2_get_rx_csum,
6871 .set_rx_csum = bnx2_set_rx_csum,
Michael Chan4666f872007-05-03 13:22:28 -07006872 .set_tx_csum = bnx2_set_tx_csum,
Michael Chanb6016b72005-05-26 13:03:09 -07006873 .set_sg = ethtool_op_set_sg,
Michael Chanb11d6212006-06-29 12:31:21 -07006874 .set_tso = bnx2_set_tso,
Michael Chanb6016b72005-05-26 13:03:09 -07006875 .self_test = bnx2_self_test,
6876 .get_strings = bnx2_get_strings,
6877 .phys_id = bnx2_phys_id,
Michael Chanb6016b72005-05-26 13:03:09 -07006878 .get_ethtool_stats = bnx2_get_ethtool_stats,
Jeff Garzikb9f2c042007-10-03 18:07:32 -07006879 .get_sset_count = bnx2_get_sset_count,
Michael Chanb6016b72005-05-26 13:03:09 -07006880};
6881
6882/* Called with rtnl_lock */
6883static int
6884bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6885{
Peter Hagervall14ab9b82005-08-10 14:18:16 -07006886 struct mii_ioctl_data *data = if_mii(ifr);
Michael Chan972ec0d2006-01-23 16:12:43 -08006887 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006888 int err;
6889
6890 switch(cmd) {
6891 case SIOCGMIIPHY:
6892 data->phy_id = bp->phy_addr;
6893
6894 /* fallthru */
6895 case SIOCGMIIREG: {
6896 u32 mii_regval;
6897
Michael Chan583c28e2008-01-21 19:51:35 -08006898 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan7b6b8342007-07-07 22:50:15 -07006899 return -EOPNOTSUPP;
6900
Michael Chandad3e452007-05-03 13:18:03 -07006901 if (!netif_running(dev))
6902 return -EAGAIN;
6903
Michael Chanc770a652005-08-25 15:38:39 -07006904 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006905 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
Michael Chanc770a652005-08-25 15:38:39 -07006906 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006907
6908 data->val_out = mii_regval;
6909
6910 return err;
6911 }
6912
6913 case SIOCSMIIREG:
6914 if (!capable(CAP_NET_ADMIN))
6915 return -EPERM;
6916
Michael Chan583c28e2008-01-21 19:51:35 -08006917 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
Michael Chan7b6b8342007-07-07 22:50:15 -07006918 return -EOPNOTSUPP;
6919
Michael Chandad3e452007-05-03 13:18:03 -07006920 if (!netif_running(dev))
6921 return -EAGAIN;
6922
Michael Chanc770a652005-08-25 15:38:39 -07006923 spin_lock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006924 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
Michael Chanc770a652005-08-25 15:38:39 -07006925 spin_unlock_bh(&bp->phy_lock);
Michael Chanb6016b72005-05-26 13:03:09 -07006926
6927 return err;
6928
6929 default:
6930 /* do nothing */
6931 break;
6932 }
6933 return -EOPNOTSUPP;
6934}
6935
6936/* Called with rtnl_lock */
6937static int
6938bnx2_change_mac_addr(struct net_device *dev, void *p)
6939{
6940 struct sockaddr *addr = p;
Michael Chan972ec0d2006-01-23 16:12:43 -08006941 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006942
Michael Chan73eef4c2005-08-25 15:39:15 -07006943 if (!is_valid_ether_addr(addr->sa_data))
6944 return -EINVAL;
6945
Michael Chanb6016b72005-05-26 13:03:09 -07006946 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6947 if (netif_running(dev))
6948 bnx2_set_mac_addr(bp);
6949
6950 return 0;
6951}
6952
6953/* Called with rtnl_lock */
6954static int
6955bnx2_change_mtu(struct net_device *dev, int new_mtu)
6956{
Michael Chan972ec0d2006-01-23 16:12:43 -08006957 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006958
6959 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
6960 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
6961 return -EINVAL;
6962
6963 dev->mtu = new_mtu;
Michael Chan5d5d0012007-12-12 11:17:43 -08006964 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
Michael Chanb6016b72005-05-26 13:03:09 -07006965}
6966
6967#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
6968static void
6969poll_bnx2(struct net_device *dev)
6970{
Michael Chan972ec0d2006-01-23 16:12:43 -08006971 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006972
6973 disable_irq(bp->pdev->irq);
David Howells7d12e782006-10-05 14:55:46 +01006974 bnx2_interrupt(bp->pdev->irq, dev);
Michael Chanb6016b72005-05-26 13:03:09 -07006975 enable_irq(bp->pdev->irq);
6976}
6977#endif
6978
Michael Chan253c8b72007-01-08 19:56:01 -08006979static void __devinit
6980bnx2_get_5709_media(struct bnx2 *bp)
6981{
6982 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
6983 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
6984 u32 strap;
6985
6986 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
6987 return;
6988 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
Michael Chan583c28e2008-01-21 19:51:35 -08006989 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
Michael Chan253c8b72007-01-08 19:56:01 -08006990 return;
6991 }
6992
6993 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
6994 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
6995 else
6996 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
6997
6998 if (PCI_FUNC(bp->pdev->devfn) == 0) {
6999 switch (strap) {
7000 case 0x4:
7001 case 0x5:
7002 case 0x6:
Michael Chan583c28e2008-01-21 19:51:35 -08007003 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
Michael Chan253c8b72007-01-08 19:56:01 -08007004 return;
7005 }
7006 } else {
7007 switch (strap) {
7008 case 0x1:
7009 case 0x2:
7010 case 0x4:
Michael Chan583c28e2008-01-21 19:51:35 -08007011 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
Michael Chan253c8b72007-01-08 19:56:01 -08007012 return;
7013 }
7014 }
7015}
7016
Michael Chan883e5152007-05-03 13:25:11 -07007017static void __devinit
7018bnx2_get_pci_speed(struct bnx2 *bp)
7019{
7020 u32 reg;
7021
7022 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7023 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7024 u32 clkreg;
7025
David S. Millerf86e82f2008-01-21 17:15:40 -08007026 bp->flags |= BNX2_FLAG_PCIX;
Michael Chan883e5152007-05-03 13:25:11 -07007027
7028 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7029
7030 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7031 switch (clkreg) {
7032 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7033 bp->bus_speed_mhz = 133;
7034 break;
7035
7036 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7037 bp->bus_speed_mhz = 100;
7038 break;
7039
7040 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7041 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7042 bp->bus_speed_mhz = 66;
7043 break;
7044
7045 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7046 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7047 bp->bus_speed_mhz = 50;
7048 break;
7049
7050 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7051 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7052 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7053 bp->bus_speed_mhz = 33;
7054 break;
7055 }
7056 }
7057 else {
7058 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7059 bp->bus_speed_mhz = 66;
7060 else
7061 bp->bus_speed_mhz = 33;
7062 }
7063
7064 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
David S. Millerf86e82f2008-01-21 17:15:40 -08007065 bp->flags |= BNX2_FLAG_PCI_32BIT;
Michael Chan883e5152007-05-03 13:25:11 -07007066
7067}
7068
Michael Chanb6016b72005-05-26 13:03:09 -07007069static int __devinit
7070bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7071{
7072 struct bnx2 *bp;
7073 unsigned long mem_len;
Michael Chan58fc2ea2007-07-07 22:52:02 -07007074 int rc, i, j;
Michael Chanb6016b72005-05-26 13:03:09 -07007075 u32 reg;
Michael Chan40453c82007-05-03 13:19:18 -07007076 u64 dma_mask, persist_dma_mask;
Michael Chanb6016b72005-05-26 13:03:09 -07007077
Michael Chanb6016b72005-05-26 13:03:09 -07007078 SET_NETDEV_DEV(dev, &pdev->dev);
Michael Chan972ec0d2006-01-23 16:12:43 -08007079 bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007080
7081 bp->flags = 0;
7082 bp->phy_flags = 0;
7083
7084 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7085 rc = pci_enable_device(pdev);
7086 if (rc) {
Joe Perches898eb712007-10-18 03:06:30 -07007087 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007088 goto err_out;
7089 }
7090
7091 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007092 dev_err(&pdev->dev,
Jeff Garzik2e8a5382006-06-27 10:47:51 -04007093 "Cannot find PCI device base address, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007094 rc = -ENODEV;
7095 goto err_out_disable;
7096 }
7097
7098 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7099 if (rc) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007100 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007101 goto err_out_disable;
7102 }
7103
7104 pci_set_master(pdev);
7105
7106 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7107 if (bp->pm_cap == 0) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007108 dev_err(&pdev->dev,
Jeff Garzik2e8a5382006-06-27 10:47:51 -04007109 "Cannot find power management capability, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007110 rc = -EIO;
7111 goto err_out_release;
7112 }
7113
Michael Chanb6016b72005-05-26 13:03:09 -07007114 bp->dev = dev;
7115 bp->pdev = pdev;
7116
7117 spin_lock_init(&bp->phy_lock);
Michael Chan1b8227c2007-05-03 13:24:05 -07007118 spin_lock_init(&bp->indirect_lock);
David Howellsc4028952006-11-22 14:57:56 +00007119 INIT_WORK(&bp->reset_task, bnx2_reset_task);
Michael Chanb6016b72005-05-26 13:03:09 -07007120
7121 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
Michael Chan59b47d82006-11-19 14:10:45 -08007122 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + 1);
Michael Chanb6016b72005-05-26 13:03:09 -07007123 dev->mem_end = dev->mem_start + mem_len;
7124 dev->irq = pdev->irq;
7125
7126 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7127
7128 if (!bp->regview) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007129 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007130 rc = -ENOMEM;
7131 goto err_out_release;
7132 }
7133
7134 /* Configure byte swap and enable write to the reg_window registers.
7135 * Rely on CPU to do target byte swapping on big endian systems
7136 * The chip's target access swapping will not swap all accesses
7137 */
7138 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7139 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7140 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7141
Pavel Machek829ca9a2005-09-03 15:56:56 -07007142 bnx2_set_power_state(bp, PCI_D0);
Michael Chanb6016b72005-05-26 13:03:09 -07007143
7144 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7145
Michael Chan883e5152007-05-03 13:25:11 -07007146 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7147 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7148 dev_err(&pdev->dev,
7149 "Cannot find PCIE capability, aborting.\n");
7150 rc = -EIO;
7151 goto err_out_unmap;
7152 }
David S. Millerf86e82f2008-01-21 17:15:40 -08007153 bp->flags |= BNX2_FLAG_PCIE;
Michael Chan2dd201d2008-01-21 17:06:09 -08007154 if (CHIP_REV(bp) == CHIP_REV_Ax)
David S. Millerf86e82f2008-01-21 17:15:40 -08007155 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
Michael Chan883e5152007-05-03 13:25:11 -07007156 } else {
Michael Chan59b47d82006-11-19 14:10:45 -08007157 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7158 if (bp->pcix_cap == 0) {
7159 dev_err(&pdev->dev,
7160 "Cannot find PCIX capability, aborting.\n");
7161 rc = -EIO;
7162 goto err_out_unmap;
7163 }
7164 }
7165
Michael Chanb4b36042007-12-20 19:59:30 -08007166 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7167 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
David S. Millerf86e82f2008-01-21 17:15:40 -08007168 bp->flags |= BNX2_FLAG_MSIX_CAP;
Michael Chanb4b36042007-12-20 19:59:30 -08007169 }
7170
Michael Chan8e6a72c2007-05-03 13:24:48 -07007171 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7172 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
David S. Millerf86e82f2008-01-21 17:15:40 -08007173 bp->flags |= BNX2_FLAG_MSI_CAP;
Michael Chan8e6a72c2007-05-03 13:24:48 -07007174 }
7175
Michael Chan40453c82007-05-03 13:19:18 -07007176 /* 5708 cannot support DMA addresses > 40-bit. */
7177 if (CHIP_NUM(bp) == CHIP_NUM_5708)
7178 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
7179 else
7180 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
7181
7182 /* Configure DMA attributes. */
7183 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7184 dev->features |= NETIF_F_HIGHDMA;
7185 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7186 if (rc) {
7187 dev_err(&pdev->dev,
7188 "pci_set_consistent_dma_mask failed, aborting.\n");
7189 goto err_out_unmap;
7190 }
7191 } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
7192 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7193 goto err_out_unmap;
7194 }
7195
David S. Millerf86e82f2008-01-21 17:15:40 -08007196 if (!(bp->flags & BNX2_FLAG_PCIE))
Michael Chan883e5152007-05-03 13:25:11 -07007197 bnx2_get_pci_speed(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07007198
7199 /* 5706A0 may falsely detect SERR and PERR. */
7200 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7201 reg = REG_RD(bp, PCI_COMMAND);
7202 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7203 REG_WR(bp, PCI_COMMAND, reg);
7204 }
7205 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
David S. Millerf86e82f2008-01-21 17:15:40 -08007206 !(bp->flags & BNX2_FLAG_PCIX)) {
Michael Chanb6016b72005-05-26 13:03:09 -07007207
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007208 dev_err(&pdev->dev,
Jeff Garzik2e8a5382006-06-27 10:47:51 -04007209 "5706 A1 can only be used in a PCIX bus, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007210 goto err_out_unmap;
7211 }
7212
7213 bnx2_init_nvram(bp);
7214
Michael Chan2726d6e2008-01-29 21:35:05 -08007215 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
Michael Chane3648b32005-11-04 08:51:21 -08007216
7217 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
Michael Chan24cb2302007-01-25 15:49:56 -08007218 BNX2_SHM_HDR_SIGNATURE_SIG) {
7219 u32 off = PCI_FUNC(pdev->devfn) << 2;
7220
Michael Chan2726d6e2008-01-29 21:35:05 -08007221 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
Michael Chan24cb2302007-01-25 15:49:56 -08007222 } else
Michael Chane3648b32005-11-04 08:51:21 -08007223 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7224
Michael Chanb6016b72005-05-26 13:03:09 -07007225 /* Get the permanent MAC address. First we need to make sure the
7226 * firmware is actually running.
7227 */
Michael Chan2726d6e2008-01-29 21:35:05 -08007228 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
Michael Chanb6016b72005-05-26 13:03:09 -07007229
7230 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7231 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007232 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007233 rc = -ENODEV;
7234 goto err_out_unmap;
7235 }
7236
Michael Chan2726d6e2008-01-29 21:35:05 -08007237 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
Michael Chan58fc2ea2007-07-07 22:52:02 -07007238 for (i = 0, j = 0; i < 3; i++) {
7239 u8 num, k, skip0;
7240
7241 num = (u8) (reg >> (24 - (i * 8)));
7242 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7243 if (num >= k || !skip0 || k == 1) {
7244 bp->fw_version[j++] = (num / k) + '0';
7245 skip0 = 0;
7246 }
7247 }
7248 if (i != 2)
7249 bp->fw_version[j++] = '.';
7250 }
Michael Chan2726d6e2008-01-29 21:35:05 -08007251 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
Michael Chan846f5c62007-10-10 16:16:51 -07007252 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7253 bp->wol = 1;
7254
7255 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
David S. Millerf86e82f2008-01-21 17:15:40 -08007256 bp->flags |= BNX2_FLAG_ASF_ENABLE;
Michael Chanc2d3db82007-07-16 18:26:43 -07007257
7258 for (i = 0; i < 30; i++) {
Michael Chan2726d6e2008-01-29 21:35:05 -08007259 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
Michael Chanc2d3db82007-07-16 18:26:43 -07007260 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7261 break;
7262 msleep(10);
7263 }
7264 }
Michael Chan2726d6e2008-01-29 21:35:05 -08007265 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
Michael Chan58fc2ea2007-07-07 22:52:02 -07007266 reg &= BNX2_CONDITION_MFW_RUN_MASK;
7267 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7268 reg != BNX2_CONDITION_MFW_RUN_NONE) {
7269 int i;
Michael Chan2726d6e2008-01-29 21:35:05 -08007270 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
Michael Chan58fc2ea2007-07-07 22:52:02 -07007271
7272 bp->fw_version[j++] = ' ';
7273 for (i = 0; i < 3; i++) {
Michael Chan2726d6e2008-01-29 21:35:05 -08007274 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
Michael Chan58fc2ea2007-07-07 22:52:02 -07007275 reg = swab32(reg);
7276 memcpy(&bp->fw_version[j], &reg, 4);
7277 j += 4;
7278 }
7279 }
Michael Chanb6016b72005-05-26 13:03:09 -07007280
Michael Chan2726d6e2008-01-29 21:35:05 -08007281 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
Michael Chanb6016b72005-05-26 13:03:09 -07007282 bp->mac_addr[0] = (u8) (reg >> 8);
7283 bp->mac_addr[1] = (u8) reg;
7284
Michael Chan2726d6e2008-01-29 21:35:05 -08007285 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
Michael Chanb6016b72005-05-26 13:03:09 -07007286 bp->mac_addr[2] = (u8) (reg >> 24);
7287 bp->mac_addr[3] = (u8) (reg >> 16);
7288 bp->mac_addr[4] = (u8) (reg >> 8);
7289 bp->mac_addr[5] = (u8) reg;
7290
Michael Chan5d5d0012007-12-12 11:17:43 -08007291 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
7292
Michael Chanb6016b72005-05-26 13:03:09 -07007293 bp->tx_ring_size = MAX_TX_DESC_CNT;
Michael Chan932f3772006-08-15 01:39:36 -07007294 bnx2_set_rx_ring_size(bp, 255);
Michael Chanb6016b72005-05-26 13:03:09 -07007295
7296 bp->rx_csum = 1;
7297
Michael Chanb6016b72005-05-26 13:03:09 -07007298 bp->tx_quick_cons_trip_int = 20;
7299 bp->tx_quick_cons_trip = 20;
7300 bp->tx_ticks_int = 80;
7301 bp->tx_ticks = 80;
Jeff Garzik6aa20a22006-09-13 13:24:59 -04007302
Michael Chanb6016b72005-05-26 13:03:09 -07007303 bp->rx_quick_cons_trip_int = 6;
7304 bp->rx_quick_cons_trip = 6;
7305 bp->rx_ticks_int = 18;
7306 bp->rx_ticks = 18;
7307
Michael Chan7ea69202007-07-16 18:27:10 -07007308 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
Michael Chanb6016b72005-05-26 13:03:09 -07007309
7310 bp->timer_interval = HZ;
Michael Chancd339a02005-08-25 15:35:24 -07007311 bp->current_interval = HZ;
Michael Chanb6016b72005-05-26 13:03:09 -07007312
Michael Chan5b0c76a2005-11-04 08:45:49 -08007313 bp->phy_addr = 1;
7314
Michael Chanb6016b72005-05-26 13:03:09 -07007315 /* Disable WOL support if we are running on a SERDES chip. */
Michael Chan253c8b72007-01-08 19:56:01 -08007316 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7317 bnx2_get_5709_media(bp);
7318 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
Michael Chan583c28e2008-01-21 19:51:35 -08007319 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
Michael Chanbac0dff2006-11-19 14:15:05 -08007320
Michael Chan0d8a6572007-07-07 22:49:43 -07007321 bp->phy_port = PORT_TP;
Michael Chan583c28e2008-01-21 19:51:35 -08007322 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
Michael Chan0d8a6572007-07-07 22:49:43 -07007323 bp->phy_port = PORT_FIBRE;
Michael Chan2726d6e2008-01-29 21:35:05 -08007324 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
Michael Chan846f5c62007-10-10 16:16:51 -07007325 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
David S. Millerf86e82f2008-01-21 17:15:40 -08007326 bp->flags |= BNX2_FLAG_NO_WOL;
Michael Chan846f5c62007-10-10 16:16:51 -07007327 bp->wol = 0;
7328 }
Michael Chanbac0dff2006-11-19 14:15:05 -08007329 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
Michael Chan5b0c76a2005-11-04 08:45:49 -08007330 bp->phy_addr = 2;
Michael Chan5b0c76a2005-11-04 08:45:49 -08007331 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
Michael Chan583c28e2008-01-21 19:51:35 -08007332 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
Michael Chan5b0c76a2005-11-04 08:45:49 -08007333 }
Michael Chan0d8a6572007-07-07 22:49:43 -07007334 bnx2_init_remote_phy(bp);
7335
Michael Chan261dd5c2007-01-08 19:55:46 -08007336 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7337 CHIP_NUM(bp) == CHIP_NUM_5708)
Michael Chan583c28e2008-01-21 19:51:35 -08007338 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
Michael Chanfb0c18b2007-12-10 17:18:23 -08007339 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7340 (CHIP_REV(bp) == CHIP_REV_Ax ||
7341 CHIP_REV(bp) == CHIP_REV_Bx))
Michael Chan583c28e2008-01-21 19:51:35 -08007342 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
Michael Chanb6016b72005-05-26 13:03:09 -07007343
Michael Chan16088272006-06-12 22:16:43 -07007344 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7345 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
Michael Chan846f5c62007-10-10 16:16:51 -07007346 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
David S. Millerf86e82f2008-01-21 17:15:40 -08007347 bp->flags |= BNX2_FLAG_NO_WOL;
Michael Chan846f5c62007-10-10 16:16:51 -07007348 bp->wol = 0;
7349 }
Michael Chandda1e392006-01-23 16:08:14 -08007350
Michael Chanb6016b72005-05-26 13:03:09 -07007351 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7352 bp->tx_quick_cons_trip_int =
7353 bp->tx_quick_cons_trip;
7354 bp->tx_ticks_int = bp->tx_ticks;
7355 bp->rx_quick_cons_trip_int =
7356 bp->rx_quick_cons_trip;
7357 bp->rx_ticks_int = bp->rx_ticks;
7358 bp->comp_prod_trip_int = bp->comp_prod_trip;
7359 bp->com_ticks_int = bp->com_ticks;
7360 bp->cmd_ticks_int = bp->cmd_ticks;
7361 }
7362
Michael Chanf9317a42006-09-29 17:06:23 -07007363 /* Disable MSI on 5706 if AMD 8132 bridge is found.
7364 *
7365 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
7366 * with byte enables disabled on the unused 32-bit word. This is legal
7367 * but causes problems on the AMD 8132 which will eventually stop
7368 * responding after a while.
7369 *
7370 * AMD believes this incompatibility is unique to the 5706, and
Michael Ellerman88187df2007-01-25 19:34:07 +11007371 * prefers to locally disable MSI rather than globally disabling it.
Michael Chanf9317a42006-09-29 17:06:23 -07007372 */
7373 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7374 struct pci_dev *amd_8132 = NULL;
7375
7376 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7377 PCI_DEVICE_ID_AMD_8132_BRIDGE,
7378 amd_8132))) {
Michael Chanf9317a42006-09-29 17:06:23 -07007379
Auke Kok44c10132007-06-08 15:46:36 -07007380 if (amd_8132->revision >= 0x10 &&
7381 amd_8132->revision <= 0x13) {
Michael Chanf9317a42006-09-29 17:06:23 -07007382 disable_msi = 1;
7383 pci_dev_put(amd_8132);
7384 break;
7385 }
7386 }
7387 }
7388
Michael Chandeaf3912007-07-07 22:48:00 -07007389 bnx2_set_default_link(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07007390 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7391
Michael Chancd339a02005-08-25 15:35:24 -07007392 init_timer(&bp->timer);
7393 bp->timer.expires = RUN_AT(bp->timer_interval);
7394 bp->timer.data = (unsigned long) bp;
7395 bp->timer.function = bnx2_timer;
7396
Michael Chanb6016b72005-05-26 13:03:09 -07007397 return 0;
7398
7399err_out_unmap:
7400 if (bp->regview) {
7401 iounmap(bp->regview);
Michael Chan73eef4c2005-08-25 15:39:15 -07007402 bp->regview = NULL;
Michael Chanb6016b72005-05-26 13:03:09 -07007403 }
7404
7405err_out_release:
7406 pci_release_regions(pdev);
7407
7408err_out_disable:
7409 pci_disable_device(pdev);
7410 pci_set_drvdata(pdev, NULL);
7411
7412err_out:
7413 return rc;
7414}
7415
Michael Chan883e5152007-05-03 13:25:11 -07007416static char * __devinit
7417bnx2_bus_string(struct bnx2 *bp, char *str)
7418{
7419 char *s = str;
7420
David S. Millerf86e82f2008-01-21 17:15:40 -08007421 if (bp->flags & BNX2_FLAG_PCIE) {
Michael Chan883e5152007-05-03 13:25:11 -07007422 s += sprintf(s, "PCI Express");
7423 } else {
7424 s += sprintf(s, "PCI");
David S. Millerf86e82f2008-01-21 17:15:40 -08007425 if (bp->flags & BNX2_FLAG_PCIX)
Michael Chan883e5152007-05-03 13:25:11 -07007426 s += sprintf(s, "-X");
David S. Millerf86e82f2008-01-21 17:15:40 -08007427 if (bp->flags & BNX2_FLAG_PCI_32BIT)
Michael Chan883e5152007-05-03 13:25:11 -07007428 s += sprintf(s, " 32-bit");
7429 else
7430 s += sprintf(s, " 64-bit");
7431 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7432 }
7433 return str;
7434}
7435
Michael Chan2ba582b2007-12-21 15:04:49 -08007436static void __devinit
Michael Chan35efa7c2007-12-20 19:56:37 -08007437bnx2_init_napi(struct bnx2 *bp)
7438{
Michael Chanb4b36042007-12-20 19:59:30 -08007439 int i;
7440 struct bnx2_napi *bnapi;
Michael Chan35efa7c2007-12-20 19:56:37 -08007441
Michael Chanb4b36042007-12-20 19:59:30 -08007442 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
7443 bnapi = &bp->bnx2_napi[i];
7444 bnapi->bp = bp;
7445 }
7446 netif_napi_add(bp->dev, &bp->bnx2_napi[0].napi, bnx2_poll, 64);
Michael Chan57851d82007-12-20 20:01:44 -08007447 netif_napi_add(bp->dev, &bp->bnx2_napi[BNX2_TX_VEC].napi, bnx2_tx_poll,
7448 64);
Michael Chan35efa7c2007-12-20 19:56:37 -08007449}
7450
7451static int __devinit
Michael Chanb6016b72005-05-26 13:03:09 -07007452bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7453{
7454 static int version_printed = 0;
7455 struct net_device *dev = NULL;
7456 struct bnx2 *bp;
Joe Perches0795af52007-10-03 17:59:30 -07007457 int rc;
Michael Chan883e5152007-05-03 13:25:11 -07007458 char str[40];
Joe Perches0795af52007-10-03 17:59:30 -07007459 DECLARE_MAC_BUF(mac);
Michael Chanb6016b72005-05-26 13:03:09 -07007460
7461 if (version_printed++ == 0)
7462 printk(KERN_INFO "%s", version);
7463
7464 /* dev zeroed in init_etherdev */
7465 dev = alloc_etherdev(sizeof(*bp));
7466
7467 if (!dev)
7468 return -ENOMEM;
7469
7470 rc = bnx2_init_board(pdev, dev);
7471 if (rc < 0) {
7472 free_netdev(dev);
7473 return rc;
7474 }
7475
7476 dev->open = bnx2_open;
7477 dev->hard_start_xmit = bnx2_start_xmit;
7478 dev->stop = bnx2_close;
7479 dev->get_stats = bnx2_get_stats;
7480 dev->set_multicast_list = bnx2_set_rx_mode;
7481 dev->do_ioctl = bnx2_ioctl;
7482 dev->set_mac_address = bnx2_change_mac_addr;
7483 dev->change_mtu = bnx2_change_mtu;
7484 dev->tx_timeout = bnx2_tx_timeout;
7485 dev->watchdog_timeo = TX_TIMEOUT;
7486#ifdef BCM_VLAN
7487 dev->vlan_rx_register = bnx2_vlan_rx_register;
Michael Chanb6016b72005-05-26 13:03:09 -07007488#endif
Michael Chanb6016b72005-05-26 13:03:09 -07007489 dev->ethtool_ops = &bnx2_ethtool_ops;
Michael Chanb6016b72005-05-26 13:03:09 -07007490
Michael Chan972ec0d2006-01-23 16:12:43 -08007491 bp = netdev_priv(dev);
Michael Chan35efa7c2007-12-20 19:56:37 -08007492 bnx2_init_napi(bp);
Michael Chanb6016b72005-05-26 13:03:09 -07007493
7494#if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7495 dev->poll_controller = poll_bnx2;
7496#endif
7497
Michael Chan1b2f9222007-05-03 13:20:19 -07007498 pci_set_drvdata(pdev, dev);
7499
7500 memcpy(dev->dev_addr, bp->mac_addr, 6);
7501 memcpy(dev->perm_addr, bp->mac_addr, 6);
7502 bp->name = board_info[ent->driver_data].name;
7503
Stephen Hemmingerd212f872007-06-27 00:47:37 -07007504 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
Michael Chan4666f872007-05-03 13:22:28 -07007505 if (CHIP_NUM(bp) == CHIP_NUM_5709)
Stephen Hemmingerd212f872007-06-27 00:47:37 -07007506 dev->features |= NETIF_F_IPV6_CSUM;
7507
Michael Chan1b2f9222007-05-03 13:20:19 -07007508#ifdef BCM_VLAN
7509 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7510#endif
7511 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
Michael Chan4666f872007-05-03 13:22:28 -07007512 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7513 dev->features |= NETIF_F_TSO6;
Michael Chan1b2f9222007-05-03 13:20:19 -07007514
Michael Chanb6016b72005-05-26 13:03:09 -07007515 if ((rc = register_netdev(dev))) {
Jeff Garzik9b91cf92006-06-27 11:39:50 -04007516 dev_err(&pdev->dev, "Cannot register net device\n");
Michael Chanb6016b72005-05-26 13:03:09 -07007517 if (bp->regview)
7518 iounmap(bp->regview);
7519 pci_release_regions(pdev);
7520 pci_disable_device(pdev);
7521 pci_set_drvdata(pdev, NULL);
7522 free_netdev(dev);
7523 return rc;
7524 }
7525
Michael Chan883e5152007-05-03 13:25:11 -07007526 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
Joe Perches0795af52007-10-03 17:59:30 -07007527 "IRQ %d, node addr %s\n",
Michael Chanb6016b72005-05-26 13:03:09 -07007528 dev->name,
7529 bp->name,
7530 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7531 ((CHIP_ID(bp) & 0x0ff0) >> 4),
Michael Chan883e5152007-05-03 13:25:11 -07007532 bnx2_bus_string(bp, str),
Michael Chanb6016b72005-05-26 13:03:09 -07007533 dev->base_addr,
Joe Perches0795af52007-10-03 17:59:30 -07007534 bp->pdev->irq, print_mac(mac, dev->dev_addr));
Michael Chanb6016b72005-05-26 13:03:09 -07007535
Michael Chanb6016b72005-05-26 13:03:09 -07007536 return 0;
7537}
7538
7539static void __devexit
7540bnx2_remove_one(struct pci_dev *pdev)
7541{
7542 struct net_device *dev = pci_get_drvdata(pdev);
Michael Chan972ec0d2006-01-23 16:12:43 -08007543 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007544
Michael Chanafdc08b2005-08-25 15:34:29 -07007545 flush_scheduled_work();
7546
Michael Chanb6016b72005-05-26 13:03:09 -07007547 unregister_netdev(dev);
7548
7549 if (bp->regview)
7550 iounmap(bp->regview);
7551
7552 free_netdev(dev);
7553 pci_release_regions(pdev);
7554 pci_disable_device(pdev);
7555 pci_set_drvdata(pdev, NULL);
7556}
7557
7558static int
Pavel Machek829ca9a2005-09-03 15:56:56 -07007559bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
Michael Chanb6016b72005-05-26 13:03:09 -07007560{
7561 struct net_device *dev = pci_get_drvdata(pdev);
Michael Chan972ec0d2006-01-23 16:12:43 -08007562 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007563 u32 reset_code;
7564
Michael Chan6caebb02007-08-03 20:57:25 -07007565 /* PCI register 4 needs to be saved whether netif_running() or not.
7566 * MSI address and data need to be saved if using MSI and
7567 * netif_running().
7568 */
7569 pci_save_state(pdev);
Michael Chanb6016b72005-05-26 13:03:09 -07007570 if (!netif_running(dev))
7571 return 0;
7572
Michael Chan1d60290f2006-03-20 17:50:08 -08007573 flush_scheduled_work();
Michael Chanb6016b72005-05-26 13:03:09 -07007574 bnx2_netif_stop(bp);
7575 netif_device_detach(dev);
7576 del_timer_sync(&bp->timer);
David S. Millerf86e82f2008-01-21 17:15:40 -08007577 if (bp->flags & BNX2_FLAG_NO_WOL)
Michael Chan6c4f0952006-06-29 12:38:15 -07007578 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
Michael Chandda1e392006-01-23 16:08:14 -08007579 else if (bp->wol)
Michael Chanb6016b72005-05-26 13:03:09 -07007580 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
7581 else
7582 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
7583 bnx2_reset_chip(bp, reset_code);
7584 bnx2_free_skbs(bp);
Pavel Machek829ca9a2005-09-03 15:56:56 -07007585 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
Michael Chanb6016b72005-05-26 13:03:09 -07007586 return 0;
7587}
7588
7589static int
7590bnx2_resume(struct pci_dev *pdev)
7591{
7592 struct net_device *dev = pci_get_drvdata(pdev);
Michael Chan972ec0d2006-01-23 16:12:43 -08007593 struct bnx2 *bp = netdev_priv(dev);
Michael Chanb6016b72005-05-26 13:03:09 -07007594
Michael Chan6caebb02007-08-03 20:57:25 -07007595 pci_restore_state(pdev);
Michael Chanb6016b72005-05-26 13:03:09 -07007596 if (!netif_running(dev))
7597 return 0;
7598
Pavel Machek829ca9a2005-09-03 15:56:56 -07007599 bnx2_set_power_state(bp, PCI_D0);
Michael Chanb6016b72005-05-26 13:03:09 -07007600 netif_device_attach(dev);
7601 bnx2_init_nic(bp);
7602 bnx2_netif_start(bp);
7603 return 0;
7604}
7605
7606static struct pci_driver bnx2_pci_driver = {
Peter Hagervall14ab9b82005-08-10 14:18:16 -07007607 .name = DRV_MODULE_NAME,
7608 .id_table = bnx2_pci_tbl,
7609 .probe = bnx2_init_one,
7610 .remove = __devexit_p(bnx2_remove_one),
7611 .suspend = bnx2_suspend,
7612 .resume = bnx2_resume,
Michael Chanb6016b72005-05-26 13:03:09 -07007613};
7614
7615static int __init bnx2_init(void)
7616{
Jeff Garzik29917622006-08-19 17:48:59 -04007617 return pci_register_driver(&bnx2_pci_driver);
Michael Chanb6016b72005-05-26 13:03:09 -07007618}
7619
7620static void __exit bnx2_cleanup(void)
7621{
7622 pci_unregister_driver(&bnx2_pci_driver);
7623}
7624
7625module_init(bnx2_init);
7626module_exit(bnx2_cleanup);
7627
7628
7629