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gerrit-public.fairphone.software / kernel / msm / aa42c69c67f82e88f0726258efe7306708e1cf14 / . / include / asm-powerpc / cputable.h
blob: aca72f90849ee48b41ee49a76afab1ebfbf3fdc4 [file] [log] [blame]
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
David Gibson3ddfbcf2005-11-10 12:56:55 +1100[diff] [blame]4#include <asm/asm-compat.h>
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]5
6#define PPC_FEATURE_32 0x80000000
7#define PPC_FEATURE_64 0x40000000
8#define PPC_FEATURE_601_INSTR 0x20000000
9#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
10#define PPC_FEATURE_HAS_FPU 0x08000000
11#define PPC_FEATURE_HAS_MMU 0x04000000
12#define PPC_FEATURE_HAS_4xxMAC 0x02000000
13#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
14#define PPC_FEATURE_HAS_SPE 0x00800000
15#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
16#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
Paul Mackerras98599012005-10-22 16:51:34 +1000[diff] [blame]17#define PPC_FEATURE_NO_TB 0x00100000
Paul Mackerrasa7ddc5e2005-11-10 14:29:18 +1100[diff] [blame]18#define PPC_FEATURE_POWER4 0x00080000
19#define PPC_FEATURE_POWER5 0x00040000
20#define PPC_FEATURE_POWER5_PLUS 0x00020000
21#define PPC_FEATURE_CELL 0x00010000
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]22#define PPC_FEATURE_BOOKE 0x00008000
Benjamin Herrenschmidtaa5cb022006-03-01 15:07:07 +1100[diff] [blame]23#define PPC_FEATURE_SMT 0x00004000
24#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]25#define PPC_FEATURE_ARCH_2_05 0x00001000
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -0500[diff] [blame]26#define PPC_FEATURE_PA6T 0x00000800
Paul Mackerras974a76f2006-11-10 20:38:53 +1100[diff] [blame]27#define PPC_FEATURE_HAS_DFP 0x00000400
28#define PPC_FEATURE_POWER6_EXT 0x00000200
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]29
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]30#define PPC_FEATURE_TRUE_LE 0x00000002
31#define PPC_FEATURE_PPC_LE 0x00000001
32
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]33#ifdef __KERNEL__
34#ifndef __ASSEMBLY__
35
36/* This structure can grow, it's real size is used by head.S code
37 * via the mkdefs mechanism.
38 */
39struct cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]40
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]41typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
Olof Johanssonf39b7a52006-08-11 00:07:08 -0500[diff] [blame]42typedef void (*cpu_restore_t)(void);
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]43
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]44enum powerpc_oprofile_type {
Andy Whitcroft7a45fb12006-01-13 12:35:49 +0000[diff] [blame]45 PPC_OPROFILE_INVALID = 0,
46 PPC_OPROFILE_RS64 = 1,
47 PPC_OPROFILE_POWER4 = 2,
48 PPC_OPROFILE_G4 = 3,
49 PPC_OPROFILE_BOOKE = 4,
Maynard Johnson18f21902006-11-20 18:45:16 +0100[diff] [blame]50 PPC_OPROFILE_CELL = 5,
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]51};
52
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]53struct cpu_spec {
54 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
55 unsigned int pvr_mask;
56 unsigned int pvr_value;
57
58 char *cpu_name;
59 unsigned long cpu_features; /* Kernel features */
60 unsigned int cpu_user_features; /* Userland features */
61
62 /* cache line sizes */
63 unsigned int icache_bsize;
64 unsigned int dcache_bsize;
65
66 /* number of performance monitor counters */
67 unsigned int num_pmcs;
68
69 /* this is called to initialize various CPU bits like L1 cache,
70 * BHT, SPD, etc... from head.S before branching to identify_machine
71 */
72 cpu_setup_t cpu_setup;
Olof Johanssonf39b7a52006-08-11 00:07:08 -0500[diff] [blame]73 /* Used to restore cpu setup on secondary processors and at resume */
74 cpu_restore_t cpu_restore;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]75
76 /* Used by oprofile userspace to select the right counters */
77 char *oprofile_cpu_type;
78
79 /* Processor specific oprofile operations */
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]80 enum powerpc_oprofile_type oprofile_type;
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]81
Michael Neulinge78dbc82006-06-08 14:42:34 +1000[diff] [blame]82 /* Bit locations inside the mmcra change */
83 unsigned long oprofile_mmcra_sihv;
84 unsigned long oprofile_mmcra_sipr;
85
86 /* Bits to clear during an oprofile exception */
87 unsigned long oprofile_mmcra_clear;
88
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]89 /* Name of processor class, for the ELF AT_PLATFORM entry */
90 char *platform;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]91};
92
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]93extern struct cpu_spec *cur_cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]94
Benjamin Herrenschmidt42c4aaa2006-10-24 16:42:40 +1000[diff] [blame]95extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
96
Paul Mackerras974a76f2006-11-10 20:38:53 +1100[diff] [blame]97extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000[diff] [blame]98extern void do_feature_fixups(unsigned long value, void *fixup_start,
99 void *fixup_end);
Paul Mackerras9b6b5632005-10-06 12:06:20 +1000[diff] [blame]100
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]101#endif /* __ASSEMBLY__ */
102
103/* CPU kernel features */
104
105/* Retain the 32b definitions all use bottom half of word */
106#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
107#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
108#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
109#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
110#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
111#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
112#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
113#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
114#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
115#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
116#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
117#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
118#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
119#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
120#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
121#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
122#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
123#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
124#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
125#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
Michael Ellerman3d159102006-03-21 20:45:58 +1100[diff] [blame]126#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]127#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
128#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
Kim Phillipsaa42c692006-12-08 02:43:30 -0600[diff] [blame^]129#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]130
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]131/*
132 * Add the 64-bit processor unique features in the top half of the word;
133 * on 32-bit, make the names available but defined to be 0.
134 */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]135#ifdef __powerpc64__
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]136#define LONG_ASM_CONST(x) ASM_CONST(x)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]137#else
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]138#define LONG_ASM_CONST(x) 0
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]139#endif
140
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]141#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
142#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
143#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
144#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
145#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
146#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
147#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
148#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
149#define CPU_FTR_COHERENT_ICACHE LONG_ASM_CONST(0x0000020000000000)
150#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
151#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
152#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
153#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +1000[diff] [blame]154#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
Paul Mackerras974a76f2006-11-10 20:38:53 +1100[diff] [blame]155#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]156
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]157#ifndef __ASSEMBLY__
158
Stephen Rothwell04704662006-11-30 11:46:22 +1100[diff] [blame]159#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
160 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
161 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]162
163/* We only set the altivec features if the kernel was compiled with altivec
164 * support
165 */
166#ifdef CONFIG_ALTIVEC
167#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
168#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
169#else
170#define CPU_FTR_ALTIVEC_COMP 0
171#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
172#endif
173
174/* We need to mark all pages as being coherent if we're SMP or we
Kumar Gala1775dbb2006-02-22 09:46:02 -0600[diff] [blame]175 * have a 74[45]x and an MPC107 host bridge. Also 83xx requires
176 * it for PCI "streaming/prefetch" to work properly.
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]177 */
Kumar Gala1775dbb2006-02-22 09:46:02 -0600[diff] [blame]178#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
179 || defined(CONFIG_PPC_83xx)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]180#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
181#else
182#define CPU_FTR_COMMON 0
183#endif
184
185/* The powersave features NAP & DOZE seems to confuse BDI when
186 debugging. So if a BDI is used, disable theses
187 */
188#ifndef CONFIG_BDI_SWITCH
189#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
190#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
191#else
192#define CPU_FTR_MAYBE_CAN_DOZE 0
193#define CPU_FTR_MAYBE_CAN_NAP 0
194#endif
195
196#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
197 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
198 !defined(CONFIG_BOOKE))
199
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]200#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE)
201#define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
202 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]203 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]204#define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]205 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
206 CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]207#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
208 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]209 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]210#define CPU_FTRS_740 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
211 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]212 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
213 CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]214#define CPU_FTRS_750 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
215 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]216 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
217 CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]218#define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
219 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
220 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]221 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]222#define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
223 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
224 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]225 CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]226#define CPU_FTRS_750FX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
227 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
228 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]229 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]230#define CPU_FTRS_750GX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
231 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \
232 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]233 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]234#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
235 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
236 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]237 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]238#define CPU_FTRS_7400 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
239 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
240 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]241 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]242#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
243 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
244 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]245 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]246#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
247 CPU_FTR_USE_TB | \
248 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
249 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
250 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]251 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]252#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
253 CPU_FTR_USE_TB | \
254 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
255 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]256 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]257#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
258 CPU_FTR_USE_TB | \
259 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
260 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]261 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]262#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
263 CPU_FTR_USE_TB | \
264 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
265 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
266 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]267 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]268#define CPU_FTRS_7455 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
269 CPU_FTR_USE_TB | \
270 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
271 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
272 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]273 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]274#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
275 CPU_FTR_USE_TB | \
276 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
277 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
278 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]279 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]280#define CPU_FTRS_7447 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
281 CPU_FTR_USE_TB | \
282 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
283 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
284 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]285 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]286#define CPU_FTRS_7447A (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
287 CPU_FTR_USE_TB | \
288 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
289 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
290 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]291 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]292#define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
293 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
294#define CPU_FTRS_G2_LE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
295 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
296#define CPU_FTRS_E300 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
297 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
298 CPU_FTR_COMMON)
Kim Phillipsaa42c692006-12-08 02:43:30 -0600[diff] [blame^]299#define CPU_FTRS_E300C2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
300 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
301 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]302#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
303 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]304#define CPU_FTRS_8XX (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
305#define CPU_FTRS_40X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
306 CPU_FTR_NODSISRALIGN)
307#define CPU_FTRS_44X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
308 CPU_FTR_NODSISRALIGN)
309#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
310#define CPU_FTRS_E500 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
311 CPU_FTR_NODSISRALIGN)
312#define CPU_FTRS_E500_2 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
313 CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN)
314#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
Michael Ellerman0b8e2e12006-11-23 00:46:46 +0100[diff] [blame]315
316/* 64-bit CPUs */
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]317#define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]318 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]319#define CPU_FTRS_RS64 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
320 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
321 CPU_FTR_MMCRA | CPU_FTR_CTRL)
322#define CPU_FTRS_POWER4 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]323 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
324 CPU_FTR_MMCRA)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]325#define CPU_FTRS_PPC970 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]326 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]327 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
328#define CPU_FTRS_POWER5 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]329 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]330 CPU_FTR_MMCRA | CPU_FTR_SMT | \
331 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
Michael Neulinge78dbc82006-06-08 14:42:34 +1000[diff] [blame]332 CPU_FTR_PURR)
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]333#define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]334 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]335 CPU_FTR_MMCRA | CPU_FTR_SMT | \
336 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
Paul Mackerras974a76f2006-11-10 20:38:53 +1100[diff] [blame]337 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE)
338#define CPU_FTRS_POWER6X (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
339 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
340 CPU_FTR_MMCRA | CPU_FTR_SMT | \
341 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
342 CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | \
343 CPU_FTR_SPURR | CPU_FTR_REAL_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]344#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]345 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]346 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +1000[diff] [blame]347 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -0500[diff] [blame]348#define CPU_FTRS_PA6T (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
349 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
350 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
351 CPU_FTR_PURR | CPU_FTR_REAL_LE)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]352#define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
353 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]354
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]355#ifdef __powerpc64__
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]356#define CPU_FTRS_POSSIBLE \
357 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]358 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -0500[diff] [blame]359 CPU_FTRS_CELL | CPU_FTRS_PA6T)
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]360#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]361enum {
362 CPU_FTRS_POSSIBLE =
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]363#if CLASSIC_PPC
364 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
365 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
366 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
367 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
368 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
369 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
370 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
Kim Phillipsaa42c692006-12-08 02:43:30 -0600[diff] [blame^]371 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
372 CPU_FTRS_CLASSIC32 |
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]373#else
374 CPU_FTRS_GENERIC_32 |
375#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]376#ifdef CONFIG_8xx
377 CPU_FTRS_8XX |
378#endif
379#ifdef CONFIG_40x
380 CPU_FTRS_40X |
381#endif
382#ifdef CONFIG_44x
383 CPU_FTRS_44X |
384#endif
385#ifdef CONFIG_E200
386 CPU_FTRS_E200 |
387#endif
388#ifdef CONFIG_E500
389 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
390#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]391 0,
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]392};
393#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]394
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]395#ifdef __powerpc64__
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]396#define CPU_FTRS_ALWAYS \
397 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]398 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -0500[diff] [blame]399 CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]400#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]401enum {
402 CPU_FTRS_ALWAYS =
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]403#if CLASSIC_PPC
404 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
405 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
406 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
407 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
408 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
409 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
410 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
Kim Phillipsaa42c692006-12-08 02:43:30 -0600[diff] [blame^]411 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
412 CPU_FTRS_CLASSIC32 &
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]413#else
414 CPU_FTRS_GENERIC_32 &
415#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]416#ifdef CONFIG_8xx
417 CPU_FTRS_8XX &
418#endif
419#ifdef CONFIG_40x
420 CPU_FTRS_40X &
421#endif
422#ifdef CONFIG_44x
423 CPU_FTRS_44X &
424#endif
425#ifdef CONFIG_E200
426 CPU_FTRS_E200 &
427#endif
428#ifdef CONFIG_E500
429 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
430#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]431 CPU_FTRS_POSSIBLE,
432};
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]433#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]434
435static inline int cpu_has_feature(unsigned long feature)
436{
437 return (CPU_FTRS_ALWAYS & feature) ||
438 (CPU_FTRS_POSSIBLE
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]439 & cur_cpu_spec->cpu_features
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]440 & feature);
441}
442
443#endif /* !__ASSEMBLY__ */
444
445#ifdef __ASSEMBLY__
446
Benjamin Herrenschmidt7aeb7322006-10-20 11:47:16 +1000[diff] [blame]447#define BEGIN_FTR_SECTION_NESTED(label) label:
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000[diff] [blame]448#define BEGIN_FTR_SECTION BEGIN_FTR_SECTION_NESTED(97)
Benjamin Herrenschmidt7aeb7322006-10-20 11:47:16 +1000[diff] [blame]449#define END_FTR_SECTION_NESTED(msk, val, label) \
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000[diff] [blame]450 MAKE_FTR_SECTION_ENTRY(msk, val, label, __ftr_fixup)
Benjamin Herrenschmidt7aeb7322006-10-20 11:47:16 +1000[diff] [blame]451#define END_FTR_SECTION(msk, val) \
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000[diff] [blame]452 END_FTR_SECTION_NESTED(msk, val, 97)
Benjamin Herrenschmidt7aeb7322006-10-20 11:47:16 +1000[diff] [blame]453
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]454#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
455#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
456#endif /* __ASSEMBLY__ */
457
458#endif /* __KERNEL__ */
459#endif /* __ASM_POWERPC_CPUTABLE_H */