Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Jeff Garzik | af36d7f | 2005-08-28 20:18:39 -0400 | [diff] [blame] | 2 | * ata_piix.c - Intel PATA/SATA controllers |
| 3 | * |
| 4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> |
| 5 | * Please ALWAYS copy linux-ide@vger.kernel.org |
| 6 | * on emails. |
| 7 | * |
| 8 | * |
| 9 | * Copyright 2003-2005 Red Hat Inc |
| 10 | * Copyright 2003-2005 Jeff Garzik |
| 11 | * |
| 12 | * |
| 13 | * Copyright header from piix.c: |
| 14 | * |
| 15 | * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer |
| 16 | * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org> |
| 17 | * Copyright (C) 2003 Red Hat Inc <alan@redhat.com> |
| 18 | * |
| 19 | * |
| 20 | * This program is free software; you can redistribute it and/or modify |
| 21 | * it under the terms of the GNU General Public License as published by |
| 22 | * the Free Software Foundation; either version 2, or (at your option) |
| 23 | * any later version. |
| 24 | * |
| 25 | * This program is distributed in the hope that it will be useful, |
| 26 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 27 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 28 | * GNU General Public License for more details. |
| 29 | * |
| 30 | * You should have received a copy of the GNU General Public License |
| 31 | * along with this program; see the file COPYING. If not, write to |
| 32 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. |
| 33 | * |
| 34 | * |
| 35 | * libata documentation is available via 'make {ps|pdf}docs', |
| 36 | * as Documentation/DocBook/libata.* |
| 37 | * |
| 38 | * Hardware documentation available at http://developer.intel.com/ |
| 39 | * |
Alan Cox | d96212e | 2005-12-08 19:19:50 +0000 | [diff] [blame] | 40 | * Documentation |
| 41 | * Publically available from Intel web site. Errata documentation |
| 42 | * is also publically available. As an aide to anyone hacking on this |
Alan | 2c5ff67 | 2006-12-04 16:33:20 +0000 | [diff] [blame] | 43 | * driver the list of errata that are relevant is below, going back to |
Alan Cox | d96212e | 2005-12-08 19:19:50 +0000 | [diff] [blame] | 44 | * PIIX4. Older device documentation is now a bit tricky to find. |
| 45 | * |
| 46 | * The chipsets all follow very much the same design. The orginal Triton |
| 47 | * series chipsets do _not_ support independant device timings, but this |
| 48 | * is fixed in Triton II. With the odd mobile exception the chips then |
| 49 | * change little except in gaining more modes until SATA arrives. This |
| 50 | * driver supports only the chips with independant timing (that is those |
| 51 | * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix |
| 52 | * for the early chip drivers. |
| 53 | * |
| 54 | * Errata of note: |
| 55 | * |
| 56 | * Unfixable |
| 57 | * PIIX4 errata #9 - Only on ultra obscure hw |
| 58 | * ICH3 errata #13 - Not observed to affect real hw |
| 59 | * by Intel |
| 60 | * |
| 61 | * Things we must deal with |
| 62 | * PIIX4 errata #10 - BM IDE hang with non UDMA |
| 63 | * (must stop/start dma to recover) |
| 64 | * 440MX errata #15 - As PIIX4 errata #10 |
| 65 | * PIIX4 errata #15 - Must not read control registers |
| 66 | * during a PIO transfer |
| 67 | * 440MX errata #13 - As PIIX4 errata #15 |
| 68 | * ICH2 errata #21 - DMA mode 0 doesn't work right |
| 69 | * ICH0/1 errata #55 - As ICH2 errata #21 |
| 70 | * ICH2 spec c #9 - Extra operations needed to handle |
| 71 | * drive hotswap [NOT YET SUPPORTED] |
| 72 | * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary |
| 73 | * and must be dword aligned |
| 74 | * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3 |
| 75 | * |
| 76 | * Should have been BIOS fixed: |
| 77 | * 450NX: errata #19 - DMA hangs on old 450NX |
| 78 | * 450NX: errata #20 - DMA hangs on old 450NX |
| 79 | * 450NX: errata #25 - Corruption with DMA on old 450NX |
| 80 | * ICH3 errata #15 - IDE deadlock under high load |
| 81 | * (BIOS must set dev 31 fn 0 bit 23) |
| 82 | * ICH3 errata #18 - Don't use native mode |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | */ |
| 84 | |
| 85 | #include <linux/kernel.h> |
| 86 | #include <linux/module.h> |
| 87 | #include <linux/pci.h> |
| 88 | #include <linux/init.h> |
| 89 | #include <linux/blkdev.h> |
| 90 | #include <linux/delay.h> |
Jeff Garzik | 6248e64 | 2005-10-30 06:42:18 -0500 | [diff] [blame] | 91 | #include <linux/device.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 92 | #include <scsi/scsi_host.h> |
| 93 | #include <linux/libata.h> |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 94 | #include <linux/dmi.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 95 | |
| 96 | #define DRV_NAME "ata_piix" |
Jeff Garzik | 2a3103c | 2007-08-31 04:54:06 -0400 | [diff] [blame] | 97 | #define DRV_VERSION "2.12" |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 98 | |
| 99 | enum { |
| 100 | PIIX_IOCFG = 0x54, /* IDE I/O configuration register */ |
| 101 | ICH5_PMR = 0x90, /* port mapping register */ |
| 102 | ICH5_PCS = 0x92, /* port control and status */ |
Tejun Heo | c729072 | 2008-01-18 18:36:30 +0900 | [diff] [blame] | 103 | PIIX_SIDPR_BAR = 5, |
| 104 | PIIX_SIDPR_LEN = 16, |
| 105 | PIIX_SIDPR_IDX = 0, |
| 106 | PIIX_SIDPR_DATA = 4, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 107 | |
Tejun Heo | ff0fc14 | 2005-12-18 17:17:07 +0900 | [diff] [blame] | 108 | PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */ |
Tejun Heo | c729072 | 2008-01-18 18:36:30 +0900 | [diff] [blame] | 109 | PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 110 | |
Tejun Heo | 800b399 | 2006-12-03 21:34:13 +0900 | [diff] [blame] | 111 | PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS, |
| 112 | PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR, |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 113 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 114 | PIIX_80C_PRI = (1 << 5) | (1 << 4), |
| 115 | PIIX_80C_SEC = (1 << 7) | (1 << 6), |
| 116 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 117 | /* constants for mapping table */ |
| 118 | P0 = 0, /* port 0 */ |
| 119 | P1 = 1, /* port 1 */ |
| 120 | P2 = 2, /* port 2 */ |
| 121 | P3 = 3, /* port 3 */ |
| 122 | IDE = -1, /* IDE */ |
| 123 | NA = -2, /* not avaliable */ |
| 124 | RV = -3, /* reserved */ |
| 125 | |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 126 | PIIX_AHCI_DEVICE = 6, |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 127 | |
| 128 | /* host->flags bits */ |
| 129 | PIIX_HOST_BROKEN_SUSPEND = (1 << 24), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 130 | }; |
| 131 | |
Tejun Heo | 9cde9ed1 | 2007-11-24 21:16:07 +0900 | [diff] [blame] | 132 | enum piix_controller_ids { |
| 133 | /* controller IDs */ |
| 134 | piix_pata_mwdma, /* PIIX3 MWDMA only */ |
| 135 | piix_pata_33, /* PIIX4 at 33Mhz */ |
| 136 | ich_pata_33, /* ICH up to UDMA 33 only */ |
| 137 | ich_pata_66, /* ICH up to 66 Mhz */ |
| 138 | ich_pata_100, /* ICH up to UDMA 100 */ |
| 139 | ich5_sata, |
| 140 | ich6_sata, |
Tejun Heo | 9c0bf67 | 2008-03-26 16:00:58 +0900 | [diff] [blame] | 141 | ich6m_sata, |
| 142 | ich8_sata, |
Tejun Heo | 9cde9ed1 | 2007-11-24 21:16:07 +0900 | [diff] [blame] | 143 | ich8_2port_sata, |
Tejun Heo | 9c0bf67 | 2008-03-26 16:00:58 +0900 | [diff] [blame] | 144 | ich8m_apple_sata, /* locks up on second port enable */ |
| 145 | tolapai_sata, |
Tejun Heo | 9cde9ed1 | 2007-11-24 21:16:07 +0900 | [diff] [blame] | 146 | piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */ |
| 147 | }; |
| 148 | |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 149 | struct piix_map_db { |
| 150 | const u32 mask; |
Jeff Garzik | 73291a1 | 2006-07-11 13:11:17 -0400 | [diff] [blame] | 151 | const u16 port_enable; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 152 | const int map[][4]; |
| 153 | }; |
| 154 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 155 | struct piix_host_priv { |
| 156 | const int *map; |
Tejun Heo | c729072 | 2008-01-18 18:36:30 +0900 | [diff] [blame] | 157 | void __iomem *sidpr; |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 158 | }; |
| 159 | |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 160 | static int piix_init_one(struct pci_dev *pdev, |
| 161 | const struct pci_device_id *ent); |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 162 | static int piix_pata_prereset(struct ata_link *link, unsigned long deadline); |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 163 | static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev); |
| 164 | static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev); |
| 165 | static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev); |
Alan Cox | eb4a2c7 | 2007-04-11 00:04:20 +0100 | [diff] [blame] | 166 | static int ich_pata_cable_detect(struct ata_port *ap); |
Tejun Heo | 25f9813 | 2008-01-07 19:38:53 +0900 | [diff] [blame] | 167 | static u8 piix_vmw_bmdma_status(struct ata_port *ap); |
Tejun Heo | c729072 | 2008-01-18 18:36:30 +0900 | [diff] [blame] | 168 | static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val); |
| 169 | static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val); |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 170 | #ifdef CONFIG_PM |
| 171 | static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); |
| 172 | static int piix_pci_device_resume(struct pci_dev *pdev); |
| 173 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 174 | |
| 175 | static unsigned int in_module_init = 1; |
| 176 | |
Jeff Garzik | 3b7d697 | 2005-11-10 11:04:11 -0500 | [diff] [blame] | 177 | static const struct pci_device_id piix_pci_tbl[] = { |
Alan | d2cdfc0 | 2007-01-10 17:13:38 +0000 | [diff] [blame] | 178 | /* Intel PIIX3 for the 430HX etc */ |
| 179 | { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma }, |
Tejun Heo | 25f9813 | 2008-01-07 19:38:53 +0900 | [diff] [blame] | 180 | /* VMware ICH4 */ |
| 181 | { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw }, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 182 | /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */ |
| 183 | /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */ |
| 184 | { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 185 | /* Intel PIIX4 */ |
| 186 | { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, |
| 187 | /* Intel PIIX4 */ |
| 188 | { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, |
| 189 | /* Intel PIIX */ |
| 190 | { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 }, |
| 191 | /* Intel ICH (i810, i815, i840) UDMA 66*/ |
| 192 | { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 }, |
| 193 | /* Intel ICH0 : UDMA 33*/ |
| 194 | { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 }, |
| 195 | /* Intel ICH2M */ |
| 196 | { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 197 | /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */ |
| 198 | { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 199 | /* Intel ICH3M */ |
| 200 | { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 201 | /* Intel ICH3 (E7500/1) UDMA 100 */ |
| 202 | { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 203 | /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */ |
| 204 | { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 205 | { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 206 | /* Intel ICH5 */ |
Christian Lamparter | 2eb829e | 2007-08-10 13:59:51 -0700 | [diff] [blame] | 207 | { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 208 | /* C-ICH (i810E2) */ |
| 209 | { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 210 | /* ESB (855GME/875P + 6300ESB) UDMA 100 */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 211 | { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 212 | /* ICH6 (and 6) (i915) UDMA 100 */ |
| 213 | { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
| 214 | /* ICH7/7-R (i945, i975) UDMA 100*/ |
Christian Lamparter | 2eb829e | 2007-08-10 13:59:51 -0700 | [diff] [blame] | 215 | { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 216 | { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
Christian Lamparter | c1e6f28 | 2007-07-03 10:19:20 -0400 | [diff] [blame] | 217 | /* ICH8 Mobile PATA Controller */ |
| 218 | { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 219 | |
| 220 | /* NOTE: The following PCI ids must be kept in sync with the |
| 221 | * list in drivers/pci/quirks.c. |
| 222 | */ |
| 223 | |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 224 | /* 82801EB (ICH5) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 225 | { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 226 | /* 82801EB (ICH5) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 227 | { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 228 | /* 6300ESB (ICH5 variant with broken PCS present bits) */ |
Tejun Heo | 5e56a37 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 229 | { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 230 | /* 6300ESB pretending RAID */ |
Tejun Heo | 5e56a37 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 231 | { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 232 | /* 82801FB/FW (ICH6/ICH6W) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 233 | { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 234 | /* 82801FR/FRW (ICH6R/ICH6RW) */ |
Tejun Heo | 9c0bf67 | 2008-03-26 16:00:58 +0900 | [diff] [blame] | 235 | { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
Tejun Heo | 5016d7d | 2008-03-26 15:46:58 +0900 | [diff] [blame] | 236 | /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented). |
| 237 | * Attach iff the controller is in IDE mode. */ |
| 238 | { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, |
Tejun Heo | 9c0bf67 | 2008-03-26 16:00:58 +0900 | [diff] [blame] | 239 | PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 240 | /* 82801GB/GR/GH (ICH7, identical to ICH6) */ |
Tejun Heo | 9c0bf67 | 2008-03-26 16:00:58 +0900 | [diff] [blame] | 241 | { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 242 | /* 2801GBM/GHM (ICH7M, identical to ICH6M) */ |
Tejun Heo | 9c0bf67 | 2008-03-26 16:00:58 +0900 | [diff] [blame] | 243 | { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata }, |
Jason Gaston | f98b657 | 2006-12-07 08:57:32 -0800 | [diff] [blame] | 244 | /* Enterprise Southbridge 2 (631xESB/632xESB) */ |
Tejun Heo | 9c0bf67 | 2008-03-26 16:00:58 +0900 | [diff] [blame] | 245 | { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata }, |
Jason Gaston | f98b657 | 2006-12-07 08:57:32 -0800 | [diff] [blame] | 246 | /* SATA Controller 1 IDE (ICH8) */ |
Tejun Heo | 9c0bf67 | 2008-03-26 16:00:58 +0900 | [diff] [blame] | 247 | { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
Jason Gaston | f98b657 | 2006-12-07 08:57:32 -0800 | [diff] [blame] | 248 | /* SATA Controller 2 IDE (ICH8) */ |
Tejun Heo | 00242ec | 2007-11-19 11:24:25 +0900 | [diff] [blame] | 249 | { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
Thomas Rohwer | 8d8ef2f | 2007-11-19 11:54:24 +0900 | [diff] [blame] | 250 | /* Mobile SATA Controller IDE (ICH8M), Apple */ |
Tejun Heo | 9c0bf67 | 2008-03-26 16:00:58 +0900 | [diff] [blame] | 251 | { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata }, |
Tejun Heo | 23cf296 | 2008-05-29 22:04:22 +0900 | [diff] [blame] | 252 | { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata }, |
Tejun Heo | 487eff6 | 2008-07-29 15:06:26 +0900 | [diff] [blame] | 253 | { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata }, |
Tejun Heo | 23cf296 | 2008-05-29 22:04:22 +0900 | [diff] [blame] | 254 | /* Mobile SATA Controller IDE (ICH8M) */ |
| 255 | { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
Jason Gaston | f98b657 | 2006-12-07 08:57:32 -0800 | [diff] [blame] | 256 | /* SATA Controller IDE (ICH9) */ |
Tejun Heo | 9c0bf67 | 2008-03-26 16:00:58 +0900 | [diff] [blame] | 257 | { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
Jason Gaston | f98b657 | 2006-12-07 08:57:32 -0800 | [diff] [blame] | 258 | /* SATA Controller IDE (ICH9) */ |
Tejun Heo | 00242ec | 2007-11-19 11:24:25 +0900 | [diff] [blame] | 259 | { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
Jason Gaston | f98b657 | 2006-12-07 08:57:32 -0800 | [diff] [blame] | 260 | /* SATA Controller IDE (ICH9) */ |
Tejun Heo | 00242ec | 2007-11-19 11:24:25 +0900 | [diff] [blame] | 261 | { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
Jason Gaston | f98b657 | 2006-12-07 08:57:32 -0800 | [diff] [blame] | 262 | /* SATA Controller IDE (ICH9M) */ |
Tejun Heo | 00242ec | 2007-11-19 11:24:25 +0900 | [diff] [blame] | 263 | { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
Jason Gaston | f98b657 | 2006-12-07 08:57:32 -0800 | [diff] [blame] | 264 | /* SATA Controller IDE (ICH9M) */ |
Tejun Heo | 00242ec | 2007-11-19 11:24:25 +0900 | [diff] [blame] | 265 | { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
Jason Gaston | f98b657 | 2006-12-07 08:57:32 -0800 | [diff] [blame] | 266 | /* SATA Controller IDE (ICH9M) */ |
Tejun Heo | 9c0bf67 | 2008-03-26 16:00:58 +0900 | [diff] [blame] | 267 | { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
Jason Gaston | c5cf0ff | 2007-08-30 21:36:56 -0700 | [diff] [blame] | 268 | /* SATA Controller IDE (Tolapai) */ |
Tejun Heo | 9c0bf67 | 2008-03-26 16:00:58 +0900 | [diff] [blame] | 269 | { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata }, |
Jason Gaston | bf7f22b | 2008-01-28 17:36:45 -0800 | [diff] [blame] | 270 | /* SATA Controller IDE (ICH10) */ |
Tejun Heo | 9c0bf67 | 2008-03-26 16:00:58 +0900 | [diff] [blame] | 271 | { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
Jason Gaston | bf7f22b | 2008-01-28 17:36:45 -0800 | [diff] [blame] | 272 | /* SATA Controller IDE (ICH10) */ |
| 273 | { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
| 274 | /* SATA Controller IDE (ICH10) */ |
Tejun Heo | 9c0bf67 | 2008-03-26 16:00:58 +0900 | [diff] [blame] | 275 | { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
Jason Gaston | bf7f22b | 2008-01-28 17:36:45 -0800 | [diff] [blame] | 276 | /* SATA Controller IDE (ICH10) */ |
| 277 | { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
Seth Heasley | c6c6a1a | 2008-08-11 17:03:18 -0700 | [diff] [blame^] | 278 | /* SATA Controller IDE (PCH) */ |
| 279 | { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
| 280 | /* SATA Controller IDE (PCH) */ |
| 281 | { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
| 282 | /* SATA Controller IDE (PCH) */ |
| 283 | { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, |
| 284 | /* SATA Controller IDE (PCH) */ |
| 285 | { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 286 | |
| 287 | { } /* terminate list */ |
| 288 | }; |
| 289 | |
| 290 | static struct pci_driver piix_pci_driver = { |
| 291 | .name = DRV_NAME, |
| 292 | .id_table = piix_pci_tbl, |
| 293 | .probe = piix_init_one, |
| 294 | .remove = ata_pci_remove_one, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 295 | #ifdef CONFIG_PM |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 296 | .suspend = piix_pci_device_suspend, |
| 297 | .resume = piix_pci_device_resume, |
Tejun Heo | 438ac6d | 2007-03-02 17:31:26 +0900 | [diff] [blame] | 298 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 299 | }; |
| 300 | |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 301 | static struct scsi_host_template piix_sht = { |
Tejun Heo | 68d1d07 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 302 | ATA_BMDMA_SHT(DRV_NAME), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 303 | }; |
| 304 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 305 | static struct ata_port_operations piix_pata_ops = { |
| 306 | .inherits = &ata_bmdma_port_ops, |
Alan Cox | eb4a2c7 | 2007-04-11 00:04:20 +0100 | [diff] [blame] | 307 | .cable_detect = ata_cable_40wire, |
Tejun Heo | 25f9813 | 2008-01-07 19:38:53 +0900 | [diff] [blame] | 308 | .set_piomode = piix_set_piomode, |
| 309 | .set_dmamode = piix_set_dmamode, |
Tejun Heo | a1efdab | 2008-03-25 12:22:50 +0900 | [diff] [blame] | 310 | .prereset = piix_pata_prereset, |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 311 | }; |
Tejun Heo | 25f9813 | 2008-01-07 19:38:53 +0900 | [diff] [blame] | 312 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 313 | static struct ata_port_operations piix_vmw_ops = { |
| 314 | .inherits = &piix_pata_ops, |
Tejun Heo | 25f9813 | 2008-01-07 19:38:53 +0900 | [diff] [blame] | 315 | .bmdma_status = piix_vmw_bmdma_status, |
Tejun Heo | 25f9813 | 2008-01-07 19:38:53 +0900 | [diff] [blame] | 316 | }; |
| 317 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 318 | static struct ata_port_operations ich_pata_ops = { |
| 319 | .inherits = &piix_pata_ops, |
| 320 | .cable_detect = ich_pata_cable_detect, |
| 321 | .set_dmamode = ich_set_dmamode, |
| 322 | }; |
Tejun Heo | c729072 | 2008-01-18 18:36:30 +0900 | [diff] [blame] | 323 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 324 | static struct ata_port_operations piix_sata_ops = { |
| 325 | .inherits = &ata_bmdma_port_ops, |
| 326 | }; |
Tejun Heo | c729072 | 2008-01-18 18:36:30 +0900 | [diff] [blame] | 327 | |
Tejun Heo | 029cfd6 | 2008-03-25 12:22:49 +0900 | [diff] [blame] | 328 | static struct ata_port_operations piix_sidpr_sata_ops = { |
| 329 | .inherits = &piix_sata_ops, |
Tejun Heo | 57c9efd | 2008-04-07 22:47:19 +0900 | [diff] [blame] | 330 | .hardreset = sata_std_hardreset, |
Tejun Heo | c729072 | 2008-01-18 18:36:30 +0900 | [diff] [blame] | 331 | .scr_read = piix_sidpr_scr_read, |
| 332 | .scr_write = piix_sidpr_scr_write, |
Tejun Heo | c729072 | 2008-01-18 18:36:30 +0900 | [diff] [blame] | 333 | }; |
| 334 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 335 | static const struct piix_map_db ich5_map_db = { |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 336 | .mask = 0x7, |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 337 | .port_enable = 0x3, |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 338 | .map = { |
| 339 | /* PM PS SM SS MAP */ |
| 340 | { P0, NA, P1, NA }, /* 000b */ |
| 341 | { P1, NA, P0, NA }, /* 001b */ |
| 342 | { RV, RV, RV, RV }, |
| 343 | { RV, RV, RV, RV }, |
| 344 | { P0, P1, IDE, IDE }, /* 100b */ |
| 345 | { P1, P0, IDE, IDE }, /* 101b */ |
| 346 | { IDE, IDE, P0, P1 }, /* 110b */ |
| 347 | { IDE, IDE, P1, P0 }, /* 111b */ |
| 348 | }, |
| 349 | }; |
| 350 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 351 | static const struct piix_map_db ich6_map_db = { |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 352 | .mask = 0x3, |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 353 | .port_enable = 0xf, |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 354 | .map = { |
| 355 | /* PM PS SM SS MAP */ |
Tejun Heo | 79ea24e | 2006-03-31 20:01:50 +0900 | [diff] [blame] | 356 | { P0, P2, P1, P3 }, /* 00b */ |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 357 | { IDE, IDE, P1, P3 }, /* 01b */ |
| 358 | { P0, P2, IDE, IDE }, /* 10b */ |
| 359 | { RV, RV, RV, RV }, |
| 360 | }, |
| 361 | }; |
| 362 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 363 | static const struct piix_map_db ich6m_map_db = { |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 364 | .mask = 0x3, |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 365 | .port_enable = 0x5, |
Tejun Heo | 6708374 | 2006-09-11 06:29:03 +0900 | [diff] [blame] | 366 | |
| 367 | /* Map 01b isn't specified in the doc but some notebooks use |
Tejun Heo | c6446a4 | 2006-10-09 13:23:58 +0900 | [diff] [blame] | 368 | * it anyway. MAP 01b have been spotted on both ICH6M and |
| 369 | * ICH7M. |
Tejun Heo | 6708374 | 2006-09-11 06:29:03 +0900 | [diff] [blame] | 370 | */ |
| 371 | .map = { |
| 372 | /* PM PS SM SS MAP */ |
Tejun Heo | e04b3b9 | 2007-07-10 17:58:21 +0900 | [diff] [blame] | 373 | { P0, P2, NA, NA }, /* 00b */ |
Tejun Heo | 6708374 | 2006-09-11 06:29:03 +0900 | [diff] [blame] | 374 | { IDE, IDE, P1, P3 }, /* 01b */ |
| 375 | { P0, P2, IDE, IDE }, /* 10b */ |
| 376 | { RV, RV, RV, RV }, |
| 377 | }, |
| 378 | }; |
| 379 | |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 380 | static const struct piix_map_db ich8_map_db = { |
| 381 | .mask = 0x3, |
Tejun Heo | a0ce9ac | 2007-11-19 12:06:37 +0900 | [diff] [blame] | 382 | .port_enable = 0xf, |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 383 | .map = { |
| 384 | /* PM PS SM SS MAP */ |
Kristen Carlson Accardi | 158f30c8 | 2006-10-19 13:27:39 -0700 | [diff] [blame] | 385 | { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */ |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 386 | { RV, RV, RV, RV }, |
Tejun Heo | ac2b043 | 2007-08-07 02:43:27 +0900 | [diff] [blame] | 387 | { P0, P2, IDE, IDE }, /* 10b (IDE mode) */ |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 388 | { RV, RV, RV, RV }, |
| 389 | }, |
| 390 | }; |
| 391 | |
Tejun Heo | 00242ec | 2007-11-19 11:24:25 +0900 | [diff] [blame] | 392 | static const struct piix_map_db ich8_2port_map_db = { |
Jason Gaston | e2d352a | 2007-09-07 17:21:03 -0700 | [diff] [blame] | 393 | .mask = 0x3, |
| 394 | .port_enable = 0x3, |
| 395 | .map = { |
| 396 | /* PM PS SM SS MAP */ |
| 397 | { P0, NA, P1, NA }, /* 00b */ |
| 398 | { RV, RV, RV, RV }, /* 01b */ |
| 399 | { RV, RV, RV, RV }, /* 10b */ |
| 400 | { RV, RV, RV, RV }, |
| 401 | }, |
Jason Gaston | c5cf0ff | 2007-08-30 21:36:56 -0700 | [diff] [blame] | 402 | }; |
| 403 | |
Thomas Rohwer | 8d8ef2f | 2007-11-19 11:54:24 +0900 | [diff] [blame] | 404 | static const struct piix_map_db ich8m_apple_map_db = { |
| 405 | .mask = 0x3, |
| 406 | .port_enable = 0x1, |
| 407 | .map = { |
| 408 | /* PM PS SM SS MAP */ |
| 409 | { P0, NA, NA, NA }, /* 00b */ |
| 410 | { RV, RV, RV, RV }, |
| 411 | { P0, P2, IDE, IDE }, /* 10b */ |
| 412 | { RV, RV, RV, RV }, |
| 413 | }, |
| 414 | }; |
| 415 | |
Tejun Heo | 00242ec | 2007-11-19 11:24:25 +0900 | [diff] [blame] | 416 | static const struct piix_map_db tolapai_map_db = { |
Jason Gaston | 8f73a68 | 2007-10-11 16:05:15 -0700 | [diff] [blame] | 417 | .mask = 0x3, |
| 418 | .port_enable = 0x3, |
| 419 | .map = { |
| 420 | /* PM PS SM SS MAP */ |
| 421 | { P0, NA, P1, NA }, /* 00b */ |
| 422 | { RV, RV, RV, RV }, /* 01b */ |
| 423 | { RV, RV, RV, RV }, /* 10b */ |
| 424 | { RV, RV, RV, RV }, |
| 425 | }, |
| 426 | }; |
| 427 | |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 428 | static const struct piix_map_db *piix_map_db_table[] = { |
| 429 | [ich5_sata] = &ich5_map_db, |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 430 | [ich6_sata] = &ich6_map_db, |
Tejun Heo | 9c0bf67 | 2008-03-26 16:00:58 +0900 | [diff] [blame] | 431 | [ich6m_sata] = &ich6m_map_db, |
| 432 | [ich8_sata] = &ich8_map_db, |
Tejun Heo | 00242ec | 2007-11-19 11:24:25 +0900 | [diff] [blame] | 433 | [ich8_2port_sata] = &ich8_2port_map_db, |
Tejun Heo | 9c0bf67 | 2008-03-26 16:00:58 +0900 | [diff] [blame] | 434 | [ich8m_apple_sata] = &ich8m_apple_map_db, |
| 435 | [tolapai_sata] = &tolapai_map_db, |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 436 | }; |
| 437 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 438 | static struct ata_port_info piix_port_info[] = { |
Tejun Heo | 00242ec | 2007-11-19 11:24:25 +0900 | [diff] [blame] | 439 | [piix_pata_mwdma] = /* PIIX3 MWDMA only */ |
| 440 | { |
Tejun Heo | 00242ec | 2007-11-19 11:24:25 +0900 | [diff] [blame] | 441 | .flags = PIIX_PATA_FLAGS, |
| 442 | .pio_mask = 0x1f, /* pio0-4 */ |
| 443 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ |
| 444 | .port_ops = &piix_pata_ops, |
| 445 | }, |
| 446 | |
Jeff Garzik | ec300d9 | 2007-09-01 07:17:36 -0400 | [diff] [blame] | 447 | [piix_pata_33] = /* PIIX4 at 33MHz */ |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 448 | { |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 449 | .flags = PIIX_PATA_FLAGS, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 450 | .pio_mask = 0x1f, /* pio0-4 */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 451 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 452 | .udma_mask = ATA_UDMA_MASK_40C, |
| 453 | .port_ops = &piix_pata_ops, |
| 454 | }, |
| 455 | |
Jeff Garzik | ec300d9 | 2007-09-01 07:17:36 -0400 | [diff] [blame] | 456 | [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 457 | { |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 458 | .flags = PIIX_PATA_FLAGS, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 459 | .pio_mask = 0x1f, /* pio 0-4 */ |
| 460 | .mwdma_mask = 0x06, /* Check: maybe 0x07 */ |
| 461 | .udma_mask = ATA_UDMA2, /* UDMA33 */ |
| 462 | .port_ops = &ich_pata_ops, |
| 463 | }, |
Jeff Garzik | ec300d9 | 2007-09-01 07:17:36 -0400 | [diff] [blame] | 464 | |
| 465 | [ich_pata_66] = /* ICH controllers up to 66MHz */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 466 | { |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 467 | .flags = PIIX_PATA_FLAGS, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 468 | .pio_mask = 0x1f, /* pio 0-4 */ |
| 469 | .mwdma_mask = 0x06, /* MWDMA0 is broken on chip */ |
| 470 | .udma_mask = ATA_UDMA4, |
| 471 | .port_ops = &ich_pata_ops, |
| 472 | }, |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 473 | |
Jeff Garzik | ec300d9 | 2007-09-01 07:17:36 -0400 | [diff] [blame] | 474 | [ich_pata_100] = |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 475 | { |
Tejun Heo | b3362f8 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 476 | .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 477 | .pio_mask = 0x1f, /* pio0-4 */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 478 | .mwdma_mask = 0x06, /* mwdma1-2 */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 479 | .udma_mask = ATA_UDMA5, /* udma0-5 */ |
| 480 | .port_ops = &ich_pata_ops, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 481 | }, |
| 482 | |
Jeff Garzik | ec300d9 | 2007-09-01 07:17:36 -0400 | [diff] [blame] | 483 | [ich5_sata] = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 484 | { |
Tejun Heo | 228c159 | 2006-11-10 18:08:10 +0900 | [diff] [blame] | 485 | .flags = PIIX_SATA_FLAGS, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 486 | .pio_mask = 0x1f, /* pio0-4 */ |
| 487 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 488 | .udma_mask = ATA_UDMA6, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 489 | .port_ops = &piix_sata_ops, |
| 490 | }, |
| 491 | |
Jeff Garzik | ec300d9 | 2007-09-01 07:17:36 -0400 | [diff] [blame] | 492 | [ich6_sata] = |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 493 | { |
Tejun Heo | 723159c | 2008-01-04 18:42:20 +0900 | [diff] [blame] | 494 | .flags = PIIX_SATA_FLAGS, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 495 | .pio_mask = 0x1f, /* pio0-4 */ |
| 496 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 497 | .udma_mask = ATA_UDMA6, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 498 | .port_ops = &piix_sata_ops, |
| 499 | }, |
| 500 | |
Tejun Heo | 9c0bf67 | 2008-03-26 16:00:58 +0900 | [diff] [blame] | 501 | [ich6m_sata] = |
Jason Gaston | c368ca4 | 2005-04-16 15:24:44 -0700 | [diff] [blame] | 502 | { |
Tejun Heo | 5016d7d | 2008-03-26 15:46:58 +0900 | [diff] [blame] | 503 | .flags = PIIX_SATA_FLAGS, |
Jason Gaston | c368ca4 | 2005-04-16 15:24:44 -0700 | [diff] [blame] | 504 | .pio_mask = 0x1f, /* pio0-4 */ |
| 505 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 506 | .udma_mask = ATA_UDMA6, |
Jason Gaston | c368ca4 | 2005-04-16 15:24:44 -0700 | [diff] [blame] | 507 | .port_ops = &piix_sata_ops, |
| 508 | }, |
Tejun Heo | 1d076e5 | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 509 | |
Tejun Heo | 9c0bf67 | 2008-03-26 16:00:58 +0900 | [diff] [blame] | 510 | [ich8_sata] = |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 511 | { |
Tejun Heo | 5016d7d | 2008-03-26 15:46:58 +0900 | [diff] [blame] | 512 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 513 | .pio_mask = 0x1f, /* pio0-4 */ |
| 514 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
Jeff Garzik | bf6263a | 2007-07-09 12:16:50 -0400 | [diff] [blame] | 515 | .udma_mask = ATA_UDMA6, |
Jeff Garzik | 08f12ed | 2006-07-11 11:57:44 -0400 | [diff] [blame] | 516 | .port_ops = &piix_sata_ops, |
| 517 | }, |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 518 | |
Tejun Heo | 00242ec | 2007-11-19 11:24:25 +0900 | [diff] [blame] | 519 | [ich8_2port_sata] = |
Jason Gaston | c5cf0ff | 2007-08-30 21:36:56 -0700 | [diff] [blame] | 520 | { |
Tejun Heo | 5016d7d | 2008-03-26 15:46:58 +0900 | [diff] [blame] | 521 | .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR, |
Jason Gaston | c5cf0ff | 2007-08-30 21:36:56 -0700 | [diff] [blame] | 522 | .pio_mask = 0x1f, /* pio0-4 */ |
| 523 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 524 | .udma_mask = ATA_UDMA6, |
| 525 | .port_ops = &piix_sata_ops, |
| 526 | }, |
Jason Gaston | 8f73a68 | 2007-10-11 16:05:15 -0700 | [diff] [blame] | 527 | |
Tejun Heo | 9c0bf67 | 2008-03-26 16:00:58 +0900 | [diff] [blame] | 528 | [tolapai_sata] = |
Jason Gaston | 8f73a68 | 2007-10-11 16:05:15 -0700 | [diff] [blame] | 529 | { |
Tejun Heo | 5016d7d | 2008-03-26 15:46:58 +0900 | [diff] [blame] | 530 | .flags = PIIX_SATA_FLAGS, |
Jason Gaston | 8f73a68 | 2007-10-11 16:05:15 -0700 | [diff] [blame] | 531 | .pio_mask = 0x1f, /* pio0-4 */ |
| 532 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 533 | .udma_mask = ATA_UDMA6, |
| 534 | .port_ops = &piix_sata_ops, |
| 535 | }, |
Thomas Rohwer | 8d8ef2f | 2007-11-19 11:54:24 +0900 | [diff] [blame] | 536 | |
Tejun Heo | 9c0bf67 | 2008-03-26 16:00:58 +0900 | [diff] [blame] | 537 | [ich8m_apple_sata] = |
Thomas Rohwer | 8d8ef2f | 2007-11-19 11:54:24 +0900 | [diff] [blame] | 538 | { |
Tejun Heo | 23cf296 | 2008-05-29 22:04:22 +0900 | [diff] [blame] | 539 | .flags = PIIX_SATA_FLAGS, |
Thomas Rohwer | 8d8ef2f | 2007-11-19 11:54:24 +0900 | [diff] [blame] | 540 | .pio_mask = 0x1f, /* pio0-4 */ |
| 541 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 542 | .udma_mask = ATA_UDMA6, |
| 543 | .port_ops = &piix_sata_ops, |
| 544 | }, |
| 545 | |
Tejun Heo | 25f9813 | 2008-01-07 19:38:53 +0900 | [diff] [blame] | 546 | [piix_pata_vmw] = |
| 547 | { |
Tejun Heo | 25f9813 | 2008-01-07 19:38:53 +0900 | [diff] [blame] | 548 | .flags = PIIX_PATA_FLAGS, |
| 549 | .pio_mask = 0x1f, /* pio0-4 */ |
| 550 | .mwdma_mask = 0x06, /* mwdma1-2 ?? CHECK 0 should be ok but slow */ |
| 551 | .udma_mask = ATA_UDMA_MASK_40C, |
| 552 | .port_ops = &piix_vmw_ops, |
| 553 | }, |
| 554 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 555 | }; |
| 556 | |
| 557 | static struct pci_bits piix_enable_bits[] = { |
| 558 | { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ |
| 559 | { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ |
| 560 | }; |
| 561 | |
| 562 | MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik"); |
| 563 | MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers"); |
| 564 | MODULE_LICENSE("GPL"); |
| 565 | MODULE_DEVICE_TABLE(pci, piix_pci_tbl); |
| 566 | MODULE_VERSION(DRV_VERSION); |
| 567 | |
Alan Cox | fc08515 | 2006-10-10 14:28:11 -0700 | [diff] [blame] | 568 | struct ich_laptop { |
| 569 | u16 device; |
| 570 | u16 subvendor; |
| 571 | u16 subdevice; |
| 572 | }; |
| 573 | |
| 574 | /* |
| 575 | * List of laptops that use short cables rather than 80 wire |
| 576 | */ |
| 577 | |
| 578 | static const struct ich_laptop ich_laptop[] = { |
| 579 | /* devid, subvendor, subdev */ |
| 580 | { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */ |
Alan Cox | 2655e2c | 2007-11-05 22:51:09 +0000 | [diff] [blame] | 581 | { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */ |
J J | babfb68 | 2007-01-09 02:26:30 +0900 | [diff] [blame] | 582 | { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */ |
Robin H\. Johnson | 1234010 | 2007-03-28 18:02:07 -0700 | [diff] [blame] | 583 | { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */ |
Jeff Garzik | 54174db | 2007-09-29 04:01:43 -0400 | [diff] [blame] | 584 | { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */ |
Tejun Heo | b33620f | 2007-05-22 11:34:22 +0200 | [diff] [blame] | 585 | { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */ |
Colin Ian King | e1fefea | 2008-06-03 18:59:02 +0200 | [diff] [blame] | 586 | { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */ |
| 587 | { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */ |
Dan McGee | 01ce260 | 2008-04-20 22:03:27 -0500 | [diff] [blame] | 588 | { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */ |
Alan Cox | fc08515 | 2006-10-10 14:28:11 -0700 | [diff] [blame] | 589 | /* end marker */ |
| 590 | { 0, } |
| 591 | }; |
| 592 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 593 | /** |
Alan Cox | eb4a2c7 | 2007-04-11 00:04:20 +0100 | [diff] [blame] | 594 | * ich_pata_cable_detect - Probe host controller cable detect info |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 595 | * @ap: Port for which cable detect info is desired |
| 596 | * |
| 597 | * Read 80c cable indicator from ATA PCI device's PCI config |
| 598 | * register. This register is normally set by firmware (BIOS). |
| 599 | * |
| 600 | * LOCKING: |
| 601 | * None (inherited from caller). |
| 602 | */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 603 | |
Alan Cox | eb4a2c7 | 2007-04-11 00:04:20 +0100 | [diff] [blame] | 604 | static int ich_pata_cable_detect(struct ata_port *ap) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 605 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 606 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
Alan Cox | fc08515 | 2006-10-10 14:28:11 -0700 | [diff] [blame] | 607 | const struct ich_laptop *lap = &ich_laptop[0]; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 608 | u8 tmp, mask; |
| 609 | |
Alan Cox | fc08515 | 2006-10-10 14:28:11 -0700 | [diff] [blame] | 610 | /* Check for specials - Acer Aspire 5602WLMi */ |
| 611 | while (lap->device) { |
| 612 | if (lap->device == pdev->device && |
| 613 | lap->subvendor == pdev->subsystem_vendor && |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 614 | lap->subdevice == pdev->subsystem_device) |
Alan Cox | eb4a2c7 | 2007-04-11 00:04:20 +0100 | [diff] [blame] | 615 | return ATA_CBL_PATA40_SHORT; |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 616 | |
Alan Cox | fc08515 | 2006-10-10 14:28:11 -0700 | [diff] [blame] | 617 | lap++; |
| 618 | } |
| 619 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 620 | /* check BIOS cable detect results */ |
Tejun Heo | 2a88d1a | 2006-08-10 16:59:16 +0900 | [diff] [blame] | 621 | mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 622 | pci_read_config_byte(pdev, PIIX_IOCFG, &tmp); |
| 623 | if ((tmp & mask) == 0) |
Alan Cox | eb4a2c7 | 2007-04-11 00:04:20 +0100 | [diff] [blame] | 624 | return ATA_CBL_PATA40; |
| 625 | return ATA_CBL_PATA80; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 626 | } |
| 627 | |
| 628 | /** |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 629 | * piix_pata_prereset - prereset for PATA host controller |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 630 | * @link: Target link |
Tejun Heo | d4b2bab | 2007-02-02 16:50:52 +0900 | [diff] [blame] | 631 | * @deadline: deadline jiffies for the operation |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 632 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 633 | * LOCKING: |
| 634 | * None (inherited from caller). |
| 635 | */ |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 636 | static int piix_pata_prereset(struct ata_link *link, unsigned long deadline) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 637 | { |
Tejun Heo | cc0680a | 2007-08-06 18:36:23 +0900 | [diff] [blame] | 638 | struct ata_port *ap = link->ap; |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 639 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 640 | |
Alan Cox | c961922 | 2006-09-26 17:53:38 +0100 | [diff] [blame] | 641 | if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no])) |
| 642 | return -ENOENT; |
Tejun Heo | 9363c38 | 2008-04-07 22:47:16 +0900 | [diff] [blame] | 643 | return ata_sff_prereset(link, deadline); |
Tejun Heo | ccc4672 | 2006-05-31 18:28:14 +0900 | [diff] [blame] | 644 | } |
| 645 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 646 | /** |
| 647 | * piix_set_piomode - Initialize host controller PATA PIO timings |
| 648 | * @ap: Port whose timings we are configuring |
| 649 | * @adev: um |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 650 | * |
| 651 | * Set PIO mode for device, in host controller PCI config space. |
| 652 | * |
| 653 | * LOCKING: |
| 654 | * None (inherited from caller). |
| 655 | */ |
| 656 | |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 657 | static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 658 | { |
| 659 | unsigned int pio = adev->pio_mode - XFER_PIO_0; |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 660 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 661 | unsigned int is_slave = (adev->devno != 0); |
Tejun Heo | 2a88d1a | 2006-08-10 16:59:16 +0900 | [diff] [blame] | 662 | unsigned int master_port= ap->port_no ? 0x42 : 0x40; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 663 | unsigned int slave_port = 0x44; |
| 664 | u16 master_data; |
| 665 | u8 slave_data; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 666 | u8 udma_enable; |
| 667 | int control = 0; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 668 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 669 | /* |
| 670 | * See Intel Document 298600-004 for the timing programing rules |
| 671 | * for ICH controllers. |
| 672 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 673 | |
| 674 | static const /* ISP RTC */ |
| 675 | u8 timings[][2] = { { 0, 0 }, |
| 676 | { 0, 0 }, |
| 677 | { 1, 0 }, |
| 678 | { 2, 1 }, |
| 679 | { 2, 3 }, }; |
| 680 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 681 | if (pio >= 2) |
| 682 | control |= 1; /* TIME1 enable */ |
| 683 | if (ata_pio_need_iordy(adev)) |
| 684 | control |= 2; /* IE enable */ |
| 685 | |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 686 | /* Intel specifies that the PPE functionality is for disk only */ |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 687 | if (adev->class == ATA_DEV_ATA) |
| 688 | control |= 4; /* PPE enable */ |
| 689 | |
Tejun Heo | a5bf5f5 | 2007-05-25 19:16:58 +0200 | [diff] [blame] | 690 | /* PIO configuration clears DTE unconditionally. It will be |
| 691 | * programmed in set_dmamode which is guaranteed to be called |
| 692 | * after set_piomode if any DMA mode is available. |
| 693 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 694 | pci_read_config_word(dev, master_port, &master_data); |
| 695 | if (is_slave) { |
Tejun Heo | a5bf5f5 | 2007-05-25 19:16:58 +0200 | [diff] [blame] | 696 | /* clear TIME1|IE1|PPE1|DTE1 */ |
| 697 | master_data &= 0xff0f; |
Joe Perches | 1967b7f | 2008-02-03 17:08:11 +0200 | [diff] [blame] | 698 | /* Enable SITRE (separate slave timing register) */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 699 | master_data |= 0x4000; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 700 | /* enable PPE1, IE1 and TIME1 as needed */ |
| 701 | master_data |= (control << 4); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 702 | pci_read_config_byte(dev, slave_port, &slave_data); |
Tejun Heo | 2a88d1a | 2006-08-10 16:59:16 +0900 | [diff] [blame] | 703 | slave_data &= (ap->port_no ? 0x0f : 0xf0); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 704 | /* Load the timing nibble for this slave */ |
Tejun Heo | a5bf5f5 | 2007-05-25 19:16:58 +0200 | [diff] [blame] | 705 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) |
| 706 | << (ap->port_no ? 4 : 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 707 | } else { |
Tejun Heo | a5bf5f5 | 2007-05-25 19:16:58 +0200 | [diff] [blame] | 708 | /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */ |
| 709 | master_data &= 0xccf0; |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 710 | /* Enable PPE, IE and TIME as appropriate */ |
| 711 | master_data |= control; |
Tejun Heo | a5bf5f5 | 2007-05-25 19:16:58 +0200 | [diff] [blame] | 712 | /* load ISP and RCT */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 713 | master_data |= |
| 714 | (timings[pio][0] << 12) | |
| 715 | (timings[pio][1] << 8); |
| 716 | } |
| 717 | pci_write_config_word(dev, master_port, master_data); |
| 718 | if (is_slave) |
| 719 | pci_write_config_byte(dev, slave_port, slave_data); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 720 | |
| 721 | /* Ensure the UDMA bit is off - it will be turned back on if |
| 722 | UDMA is selected */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 723 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 724 | if (ap->udma_mask) { |
| 725 | pci_read_config_byte(dev, 0x48, &udma_enable); |
| 726 | udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); |
| 727 | pci_write_config_byte(dev, 0x48, udma_enable); |
| 728 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 729 | } |
| 730 | |
| 731 | /** |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 732 | * do_pata_set_dmamode - Initialize host controller PATA PIO timings |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 733 | * @ap: Port whose timings we are configuring |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 734 | * @adev: Drive in question |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 735 | * @udma: udma mode, 0 - 6 |
Henne | c32a8fd | 2006-09-25 22:00:46 +0200 | [diff] [blame] | 736 | * @isich: set if the chip is an ICH device |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 737 | * |
| 738 | * Set UDMA mode for device, in host controller PCI config space. |
| 739 | * |
| 740 | * LOCKING: |
| 741 | * None (inherited from caller). |
| 742 | */ |
| 743 | |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 744 | static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 745 | { |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 746 | struct pci_dev *dev = to_pci_dev(ap->host->dev); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 747 | u8 master_port = ap->port_no ? 0x42 : 0x40; |
| 748 | u16 master_data; |
| 749 | u8 speed = adev->dma_mode; |
| 750 | int devid = adev->devno + 2 * ap->port_no; |
Andrew Morton | dedf61d | 2007-01-10 17:20:34 -0800 | [diff] [blame] | 751 | u8 udma_enable = 0; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 752 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 753 | static const /* ISP RTC */ |
| 754 | u8 timings[][2] = { { 0, 0 }, |
| 755 | { 0, 0 }, |
| 756 | { 1, 0 }, |
| 757 | { 2, 1 }, |
| 758 | { 2, 3 }, }; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 759 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 760 | pci_read_config_word(dev, master_port, &master_data); |
Alan | d2cdfc0 | 2007-01-10 17:13:38 +0000 | [diff] [blame] | 761 | if (ap->udma_mask) |
| 762 | pci_read_config_byte(dev, 0x48, &udma_enable); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 763 | |
| 764 | if (speed >= XFER_UDMA_0) { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 765 | unsigned int udma = adev->dma_mode - XFER_UDMA_0; |
| 766 | u16 udma_timing; |
| 767 | u16 ideconf; |
| 768 | int u_clock, u_speed; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 769 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 770 | /* |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 771 | * UDMA is handled by a combination of clock switching and |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 772 | * selection of dividers |
| 773 | * |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 774 | * Handy rule: Odd modes are UDMATIMx 01, even are 02 |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 775 | * except UDMA0 which is 00 |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 776 | */ |
| 777 | u_speed = min(2 - (udma & 1), udma); |
| 778 | if (udma == 5) |
| 779 | u_clock = 0x1000; /* 100Mhz */ |
| 780 | else if (udma > 2) |
| 781 | u_clock = 1; /* 66Mhz */ |
| 782 | else |
| 783 | u_clock = 0; /* 33Mhz */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 784 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 785 | udma_enable |= (1 << devid); |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 786 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 787 | /* Load the CT/RP selection */ |
| 788 | pci_read_config_word(dev, 0x4A, &udma_timing); |
| 789 | udma_timing &= ~(3 << (4 * devid)); |
| 790 | udma_timing |= u_speed << (4 * devid); |
| 791 | pci_write_config_word(dev, 0x4A, udma_timing); |
| 792 | |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 793 | if (isich) { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 794 | /* Select a 33/66/100Mhz clock */ |
| 795 | pci_read_config_word(dev, 0x54, &ideconf); |
| 796 | ideconf &= ~(0x1001 << devid); |
| 797 | ideconf |= u_clock << devid; |
| 798 | /* For ICH or later we should set bit 10 for better |
| 799 | performance (WR_PingPong_En) */ |
| 800 | pci_write_config_word(dev, 0x54, ideconf); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 801 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 802 | } else { |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 803 | /* |
| 804 | * MWDMA is driven by the PIO timings. We must also enable |
| 805 | * IORDY unconditionally along with TIME1. PPE has already |
| 806 | * been set when the PIO timing was set. |
| 807 | */ |
| 808 | unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; |
| 809 | unsigned int control; |
| 810 | u8 slave_data; |
| 811 | const unsigned int needed_pio[3] = { |
| 812 | XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 |
| 813 | }; |
| 814 | int pio = needed_pio[mwdma] - XFER_PIO_0; |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 815 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 816 | control = 3; /* IORDY|TIME1 */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 817 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 818 | /* If the drive MWDMA is faster than it can do PIO then |
| 819 | we must force PIO into PIO0 */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 820 | |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 821 | if (adev->pio_mode < needed_pio[mwdma]) |
| 822 | /* Enable DMA timing only */ |
| 823 | control |= 8; /* PIO cycles in PIO0 */ |
| 824 | |
| 825 | if (adev->devno) { /* Slave */ |
| 826 | master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ |
| 827 | master_data |= control << 4; |
| 828 | pci_read_config_byte(dev, 0x44, &slave_data); |
Tejun Heo | a5bf5f5 | 2007-05-25 19:16:58 +0200 | [diff] [blame] | 829 | slave_data &= (ap->port_no ? 0x0f : 0xf0); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 830 | /* Load the matching timing */ |
| 831 | slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); |
| 832 | pci_write_config_byte(dev, 0x44, slave_data); |
| 833 | } else { /* Master */ |
Jeff Garzik | 85cd725 | 2006-08-31 00:03:49 -0400 | [diff] [blame] | 834 | master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 835 | and master timing bits */ |
| 836 | master_data |= control; |
| 837 | master_data |= |
| 838 | (timings[pio][0] << 12) | |
| 839 | (timings[pio][1] << 8); |
| 840 | } |
Tejun Heo | a5bf5f5 | 2007-05-25 19:16:58 +0200 | [diff] [blame] | 841 | |
| 842 | if (ap->udma_mask) { |
| 843 | udma_enable &= ~(1 << devid); |
| 844 | pci_write_config_word(dev, master_port, master_data); |
| 845 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 846 | } |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 847 | /* Don't scribble on 0x48 if the controller does not support UDMA */ |
| 848 | if (ap->udma_mask) |
| 849 | pci_write_config_byte(dev, 0x48, udma_enable); |
| 850 | } |
| 851 | |
| 852 | /** |
| 853 | * piix_set_dmamode - Initialize host controller PATA DMA timings |
| 854 | * @ap: Port whose timings we are configuring |
| 855 | * @adev: um |
| 856 | * |
| 857 | * Set MW/UDMA mode for device, in host controller PCI config space. |
| 858 | * |
| 859 | * LOCKING: |
| 860 | * None (inherited from caller). |
| 861 | */ |
| 862 | |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 863 | static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 864 | { |
| 865 | do_pata_set_dmamode(ap, adev, 0); |
| 866 | } |
| 867 | |
| 868 | /** |
| 869 | * ich_set_dmamode - Initialize host controller PATA DMA timings |
| 870 | * @ap: Port whose timings we are configuring |
| 871 | * @adev: um |
| 872 | * |
| 873 | * Set MW/UDMA mode for device, in host controller PCI config space. |
| 874 | * |
| 875 | * LOCKING: |
| 876 | * None (inherited from caller). |
| 877 | */ |
| 878 | |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 879 | static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 880 | { |
| 881 | do_pata_set_dmamode(ap, adev, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 882 | } |
| 883 | |
Tejun Heo | c729072 | 2008-01-18 18:36:30 +0900 | [diff] [blame] | 884 | /* |
| 885 | * Serial ATA Index/Data Pair Superset Registers access |
| 886 | * |
| 887 | * Beginning from ICH8, there's a sane way to access SCRs using index |
| 888 | * and data register pair located at BAR5. This creates an |
| 889 | * interesting problem of mapping two SCRs to one port. |
| 890 | * |
| 891 | * Although they have separate SCRs, the master and slave aren't |
| 892 | * independent enough to be treated as separate links - e.g. softreset |
| 893 | * resets both. Also, there's no protocol defined for hard resetting |
| 894 | * singled device sharing the virtual port (no defined way to acquire |
| 895 | * device signature). This is worked around by merging the SCR values |
| 896 | * into one sensible value and requesting follow-up SRST after |
| 897 | * hardreset. |
| 898 | * |
| 899 | * SCR merging is perfomed in nibbles which is the unit contents in |
| 900 | * SCRs are organized. If two values are equal, the value is used. |
| 901 | * When they differ, merge table which lists precedence of possible |
| 902 | * values is consulted and the first match or the last entry when |
| 903 | * nothing matches is used. When there's no merge table for the |
| 904 | * specific nibble, value from the first port is used. |
| 905 | */ |
| 906 | static const int piix_sidx_map[] = { |
| 907 | [SCR_STATUS] = 0, |
| 908 | [SCR_ERROR] = 2, |
| 909 | [SCR_CONTROL] = 1, |
| 910 | }; |
| 911 | |
| 912 | static void piix_sidpr_sel(struct ata_device *dev, unsigned int reg) |
| 913 | { |
| 914 | struct ata_port *ap = dev->link->ap; |
| 915 | struct piix_host_priv *hpriv = ap->host->private_data; |
| 916 | |
| 917 | iowrite32(((ap->port_no * 2 + dev->devno) << 8) | piix_sidx_map[reg], |
| 918 | hpriv->sidpr + PIIX_SIDPR_IDX); |
| 919 | } |
| 920 | |
| 921 | static int piix_sidpr_read(struct ata_device *dev, unsigned int reg) |
| 922 | { |
| 923 | struct piix_host_priv *hpriv = dev->link->ap->host->private_data; |
| 924 | |
| 925 | piix_sidpr_sel(dev, reg); |
| 926 | return ioread32(hpriv->sidpr + PIIX_SIDPR_DATA); |
| 927 | } |
| 928 | |
| 929 | static void piix_sidpr_write(struct ata_device *dev, unsigned int reg, u32 val) |
| 930 | { |
| 931 | struct piix_host_priv *hpriv = dev->link->ap->host->private_data; |
| 932 | |
| 933 | piix_sidpr_sel(dev, reg); |
| 934 | iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA); |
| 935 | } |
| 936 | |
Adrian Bunk | 4a537a5 | 2008-01-29 00:10:19 +0200 | [diff] [blame] | 937 | static u32 piix_merge_scr(u32 val0, u32 val1, const int * const *merge_tbl) |
Tejun Heo | c729072 | 2008-01-18 18:36:30 +0900 | [diff] [blame] | 938 | { |
| 939 | u32 val = 0; |
| 940 | int i, mi; |
| 941 | |
| 942 | for (i = 0, mi = 0; i < 32 / 4; i++) { |
| 943 | u8 c0 = (val0 >> (i * 4)) & 0xf; |
| 944 | u8 c1 = (val1 >> (i * 4)) & 0xf; |
| 945 | u8 merged = c0; |
| 946 | const int *cur; |
| 947 | |
| 948 | /* if no merge preference, assume the first value */ |
| 949 | cur = merge_tbl[mi]; |
| 950 | if (!cur) |
| 951 | goto done; |
| 952 | mi++; |
| 953 | |
| 954 | /* if two values equal, use it */ |
| 955 | if (c0 == c1) |
| 956 | goto done; |
| 957 | |
| 958 | /* choose the first match or the last from the merge table */ |
| 959 | while (*cur != -1) { |
| 960 | if (c0 == *cur || c1 == *cur) |
| 961 | break; |
| 962 | cur++; |
| 963 | } |
| 964 | if (*cur == -1) |
| 965 | cur--; |
| 966 | merged = *cur; |
| 967 | done: |
| 968 | val |= merged << (i * 4); |
| 969 | } |
| 970 | |
| 971 | return val; |
| 972 | } |
| 973 | |
| 974 | static int piix_sidpr_scr_read(struct ata_port *ap, unsigned int reg, u32 *val) |
| 975 | { |
| 976 | const int * const sstatus_merge_tbl[] = { |
| 977 | /* DET */ (const int []){ 1, 3, 0, 4, 3, -1 }, |
| 978 | /* SPD */ (const int []){ 2, 1, 0, -1 }, |
| 979 | /* IPM */ (const int []){ 6, 2, 1, 0, -1 }, |
| 980 | NULL, |
| 981 | }; |
| 982 | const int * const scontrol_merge_tbl[] = { |
| 983 | /* DET */ (const int []){ 1, 0, 4, 0, -1 }, |
| 984 | /* SPD */ (const int []){ 0, 2, 1, 0, -1 }, |
| 985 | /* IPM */ (const int []){ 0, 1, 2, 3, 0, -1 }, |
| 986 | NULL, |
| 987 | }; |
| 988 | u32 v0, v1; |
| 989 | |
| 990 | if (reg >= ARRAY_SIZE(piix_sidx_map)) |
| 991 | return -EINVAL; |
| 992 | |
| 993 | if (!(ap->flags & ATA_FLAG_SLAVE_POSS)) { |
| 994 | *val = piix_sidpr_read(&ap->link.device[0], reg); |
| 995 | return 0; |
| 996 | } |
| 997 | |
| 998 | v0 = piix_sidpr_read(&ap->link.device[0], reg); |
| 999 | v1 = piix_sidpr_read(&ap->link.device[1], reg); |
| 1000 | |
| 1001 | switch (reg) { |
| 1002 | case SCR_STATUS: |
| 1003 | *val = piix_merge_scr(v0, v1, sstatus_merge_tbl); |
| 1004 | break; |
| 1005 | case SCR_ERROR: |
| 1006 | *val = v0 | v1; |
| 1007 | break; |
| 1008 | case SCR_CONTROL: |
| 1009 | *val = piix_merge_scr(v0, v1, scontrol_merge_tbl); |
| 1010 | break; |
| 1011 | } |
| 1012 | |
| 1013 | return 0; |
| 1014 | } |
| 1015 | |
| 1016 | static int piix_sidpr_scr_write(struct ata_port *ap, unsigned int reg, u32 val) |
| 1017 | { |
| 1018 | if (reg >= ARRAY_SIZE(piix_sidx_map)) |
| 1019 | return -EINVAL; |
| 1020 | |
| 1021 | piix_sidpr_write(&ap->link.device[0], reg, val); |
| 1022 | |
| 1023 | if (ap->flags & ATA_FLAG_SLAVE_POSS) |
| 1024 | piix_sidpr_write(&ap->link.device[1], reg, val); |
| 1025 | |
| 1026 | return 0; |
| 1027 | } |
| 1028 | |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 1029 | #ifdef CONFIG_PM |
Tejun Heo | 8c3832e | 2007-07-27 14:53:28 +0900 | [diff] [blame] | 1030 | static int piix_broken_suspend(void) |
| 1031 | { |
Jeff Garzik | 1855256 | 2007-10-03 15:15:40 -0400 | [diff] [blame] | 1032 | static const struct dmi_system_id sysids[] = { |
Tejun Heo | 8c3832e | 2007-07-27 14:53:28 +0900 | [diff] [blame] | 1033 | { |
Tejun Heo | 4c74d4e | 2007-09-30 01:11:20 -0700 | [diff] [blame] | 1034 | .ident = "TECRA M3", |
| 1035 | .matches = { |
| 1036 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
| 1037 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"), |
| 1038 | }, |
| 1039 | }, |
| 1040 | { |
Peter Schwenke | 04d86d6 | 2007-11-30 15:28:29 +0900 | [diff] [blame] | 1041 | .ident = "TECRA M3", |
| 1042 | .matches = { |
| 1043 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
| 1044 | DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"), |
| 1045 | }, |
| 1046 | }, |
| 1047 | { |
Peter Schwenke | d1aa690 | 2007-12-05 10:39:49 +0900 | [diff] [blame] | 1048 | .ident = "TECRA M4", |
| 1049 | .matches = { |
| 1050 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
| 1051 | DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"), |
| 1052 | }, |
| 1053 | }, |
| 1054 | { |
Tejun Heo | 040dee5 | 2008-06-13 18:05:02 +0900 | [diff] [blame] | 1055 | .ident = "TECRA M4", |
| 1056 | .matches = { |
| 1057 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
| 1058 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"), |
| 1059 | }, |
| 1060 | }, |
| 1061 | { |
Tejun Heo | 8c3832e | 2007-07-27 14:53:28 +0900 | [diff] [blame] | 1062 | .ident = "TECRA M5", |
| 1063 | .matches = { |
| 1064 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
| 1065 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"), |
| 1066 | }, |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 1067 | }, |
Tejun Heo | 8c3832e | 2007-07-27 14:53:28 +0900 | [diff] [blame] | 1068 | { |
Peter Schwenke | ffe188d | 2008-01-17 23:08:55 +1000 | [diff] [blame] | 1069 | .ident = "TECRA M6", |
| 1070 | .matches = { |
| 1071 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
| 1072 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"), |
| 1073 | }, |
| 1074 | }, |
| 1075 | { |
Tejun Heo | 5c08ea0 | 2007-08-14 19:56:04 +0900 | [diff] [blame] | 1076 | .ident = "TECRA M7", |
| 1077 | .matches = { |
| 1078 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
| 1079 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"), |
| 1080 | }, |
| 1081 | }, |
| 1082 | { |
Peter Schwenke | 04d86d6 | 2007-11-30 15:28:29 +0900 | [diff] [blame] | 1083 | .ident = "TECRA A8", |
| 1084 | .matches = { |
| 1085 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
| 1086 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"), |
| 1087 | }, |
| 1088 | }, |
| 1089 | { |
Peter Schwenke | ffe188d | 2008-01-17 23:08:55 +1000 | [diff] [blame] | 1090 | .ident = "Satellite R20", |
| 1091 | .matches = { |
| 1092 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
| 1093 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"), |
| 1094 | }, |
| 1095 | }, |
| 1096 | { |
Peter Schwenke | 04d86d6 | 2007-11-30 15:28:29 +0900 | [diff] [blame] | 1097 | .ident = "Satellite R25", |
| 1098 | .matches = { |
| 1099 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
| 1100 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"), |
| 1101 | }, |
| 1102 | }, |
| 1103 | { |
Tejun Heo | 3cc0b9d | 2007-08-25 08:31:02 +0900 | [diff] [blame] | 1104 | .ident = "Satellite U200", |
| 1105 | .matches = { |
| 1106 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
| 1107 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"), |
| 1108 | }, |
| 1109 | }, |
| 1110 | { |
Peter Schwenke | 04d86d6 | 2007-11-30 15:28:29 +0900 | [diff] [blame] | 1111 | .ident = "Satellite U200", |
| 1112 | .matches = { |
| 1113 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
| 1114 | DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"), |
| 1115 | }, |
| 1116 | }, |
| 1117 | { |
Yann Chachkoff | 62320e2 | 2007-11-07 12:02:27 +0900 | [diff] [blame] | 1118 | .ident = "Satellite Pro U200", |
| 1119 | .matches = { |
| 1120 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
| 1121 | DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"), |
| 1122 | }, |
| 1123 | }, |
| 1124 | { |
Tejun Heo | 8c3832e | 2007-07-27 14:53:28 +0900 | [diff] [blame] | 1125 | .ident = "Satellite U205", |
| 1126 | .matches = { |
| 1127 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
| 1128 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"), |
| 1129 | }, |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 1130 | }, |
Tejun Heo | 8c3832e | 2007-07-27 14:53:28 +0900 | [diff] [blame] | 1131 | { |
Tejun Heo | de753e5 | 2007-11-12 17:56:24 +0900 | [diff] [blame] | 1132 | .ident = "SATELLITE U205", |
| 1133 | .matches = { |
| 1134 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
| 1135 | DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"), |
| 1136 | }, |
| 1137 | }, |
| 1138 | { |
Tejun Heo | 8c3832e | 2007-07-27 14:53:28 +0900 | [diff] [blame] | 1139 | .ident = "Portege M500", |
| 1140 | .matches = { |
| 1141 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), |
| 1142 | DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"), |
| 1143 | }, |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 1144 | }, |
Jeff Garzik | 7d05154 | 2007-09-01 06:48:52 -0400 | [diff] [blame] | 1145 | |
| 1146 | { } /* terminate list */ |
Tejun Heo | 8c3832e | 2007-07-27 14:53:28 +0900 | [diff] [blame] | 1147 | }; |
Tejun Heo | 7abe79c | 2007-07-27 14:55:07 +0900 | [diff] [blame] | 1148 | static const char *oemstrs[] = { |
| 1149 | "Tecra M3,", |
| 1150 | }; |
| 1151 | int i; |
Tejun Heo | 8c3832e | 2007-07-27 14:53:28 +0900 | [diff] [blame] | 1152 | |
| 1153 | if (dmi_check_system(sysids)) |
| 1154 | return 1; |
| 1155 | |
Tejun Heo | 7abe79c | 2007-07-27 14:55:07 +0900 | [diff] [blame] | 1156 | for (i = 0; i < ARRAY_SIZE(oemstrs); i++) |
| 1157 | if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL)) |
| 1158 | return 1; |
| 1159 | |
Tejun Heo | 8c3832e | 2007-07-27 14:53:28 +0900 | [diff] [blame] | 1160 | return 0; |
| 1161 | } |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 1162 | |
| 1163 | static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) |
| 1164 | { |
| 1165 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
| 1166 | unsigned long flags; |
| 1167 | int rc = 0; |
| 1168 | |
| 1169 | rc = ata_host_suspend(host, mesg); |
| 1170 | if (rc) |
| 1171 | return rc; |
| 1172 | |
| 1173 | /* Some braindamaged ACPI suspend implementations expect the |
| 1174 | * controller to be awake on entry; otherwise, it burns cpu |
| 1175 | * cycles and power trying to do something to the sleeping |
| 1176 | * beauty. |
| 1177 | */ |
Rafael J. Wysocki | 3a2d5b7 | 2008-02-23 19:13:25 +0100 | [diff] [blame] | 1178 | if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) { |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 1179 | pci_save_state(pdev); |
| 1180 | |
| 1181 | /* mark its power state as "unknown", since we don't |
| 1182 | * know if e.g. the BIOS will change its device state |
| 1183 | * when we suspend. |
| 1184 | */ |
| 1185 | if (pdev->current_state == PCI_D0) |
| 1186 | pdev->current_state = PCI_UNKNOWN; |
| 1187 | |
| 1188 | /* tell resume that it's waking up from broken suspend */ |
| 1189 | spin_lock_irqsave(&host->lock, flags); |
| 1190 | host->flags |= PIIX_HOST_BROKEN_SUSPEND; |
| 1191 | spin_unlock_irqrestore(&host->lock, flags); |
| 1192 | } else |
| 1193 | ata_pci_device_do_suspend(pdev, mesg); |
| 1194 | |
| 1195 | return 0; |
| 1196 | } |
| 1197 | |
| 1198 | static int piix_pci_device_resume(struct pci_dev *pdev) |
| 1199 | { |
| 1200 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
| 1201 | unsigned long flags; |
| 1202 | int rc; |
| 1203 | |
| 1204 | if (host->flags & PIIX_HOST_BROKEN_SUSPEND) { |
| 1205 | spin_lock_irqsave(&host->lock, flags); |
| 1206 | host->flags &= ~PIIX_HOST_BROKEN_SUSPEND; |
| 1207 | spin_unlock_irqrestore(&host->lock, flags); |
| 1208 | |
| 1209 | pci_set_power_state(pdev, PCI_D0); |
| 1210 | pci_restore_state(pdev); |
| 1211 | |
| 1212 | /* PCI device wasn't disabled during suspend. Use |
Tejun Heo | 0b62e13 | 2007-07-27 14:43:35 +0900 | [diff] [blame] | 1213 | * pci_reenable_device() to avoid affecting the enable |
| 1214 | * count. |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 1215 | */ |
Tejun Heo | 0b62e13 | 2007-07-27 14:43:35 +0900 | [diff] [blame] | 1216 | rc = pci_reenable_device(pdev); |
Tejun Heo | b8b275e | 2007-07-10 15:55:43 +0900 | [diff] [blame] | 1217 | if (rc) |
| 1218 | dev_printk(KERN_ERR, &pdev->dev, "failed to enable " |
| 1219 | "device after resume (%d)\n", rc); |
| 1220 | } else |
| 1221 | rc = ata_pci_device_do_resume(pdev); |
| 1222 | |
| 1223 | if (rc == 0) |
| 1224 | ata_host_resume(host); |
| 1225 | |
| 1226 | return rc; |
| 1227 | } |
| 1228 | #endif |
| 1229 | |
Tejun Heo | 25f9813 | 2008-01-07 19:38:53 +0900 | [diff] [blame] | 1230 | static u8 piix_vmw_bmdma_status(struct ata_port *ap) |
| 1231 | { |
| 1232 | return ata_bmdma_status(ap) & ~ATA_DMA_ERR; |
| 1233 | } |
| 1234 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1235 | #define AHCI_PCI_BAR 5 |
| 1236 | #define AHCI_GLOBAL_CTL 0x04 |
| 1237 | #define AHCI_ENABLE (1 << 31) |
| 1238 | static int piix_disable_ahci(struct pci_dev *pdev) |
| 1239 | { |
Jeff Garzik | ea6ba10 | 2005-08-30 05:18:18 -0400 | [diff] [blame] | 1240 | void __iomem *mmio; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1241 | u32 tmp; |
| 1242 | int rc = 0; |
| 1243 | |
| 1244 | /* BUG: pci_enable_device has not yet been called. This |
| 1245 | * works because this device is usually set up by BIOS. |
| 1246 | */ |
| 1247 | |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 1248 | if (!pci_resource_start(pdev, AHCI_PCI_BAR) || |
| 1249 | !pci_resource_len(pdev, AHCI_PCI_BAR)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1250 | return 0; |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 1251 | |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 1252 | mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1253 | if (!mmio) |
| 1254 | return -ENOMEM; |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 1255 | |
Alan Cox | c47a631 | 2007-11-19 14:28:28 +0000 | [diff] [blame] | 1256 | tmp = ioread32(mmio + AHCI_GLOBAL_CTL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1257 | if (tmp & AHCI_ENABLE) { |
| 1258 | tmp &= ~AHCI_ENABLE; |
Alan Cox | c47a631 | 2007-11-19 14:28:28 +0000 | [diff] [blame] | 1259 | iowrite32(tmp, mmio + AHCI_GLOBAL_CTL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1260 | |
Alan Cox | c47a631 | 2007-11-19 14:28:28 +0000 | [diff] [blame] | 1261 | tmp = ioread32(mmio + AHCI_GLOBAL_CTL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1262 | if (tmp & AHCI_ENABLE) |
| 1263 | rc = -EIO; |
| 1264 | } |
Greg Felix | 7b6dbd6 | 2005-07-28 15:54:15 -0400 | [diff] [blame] | 1265 | |
Jeff Garzik | 374b187 | 2005-08-30 05:42:52 -0400 | [diff] [blame] | 1266 | pci_iounmap(pdev, mmio); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1267 | return rc; |
| 1268 | } |
| 1269 | |
| 1270 | /** |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1271 | * piix_check_450nx_errata - Check for problem 450NX setup |
Randy Dunlap | c893a3a | 2006-01-28 13:15:32 -0500 | [diff] [blame] | 1272 | * @ata_dev: the PCI device to check |
Jeff Garzik | 2e9edbf | 2006-03-24 09:56:57 -0500 | [diff] [blame] | 1273 | * |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1274 | * Check for the present of 450NX errata #19 and errata #25. If |
| 1275 | * they are found return an error code so we can turn off DMA |
| 1276 | */ |
| 1277 | |
| 1278 | static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev) |
| 1279 | { |
| 1280 | struct pci_dev *pdev = NULL; |
| 1281 | u16 cfg; |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1282 | int no_piix_dma = 0; |
Jeff Garzik | 2e9edbf | 2006-03-24 09:56:57 -0500 | [diff] [blame] | 1283 | |
Jeff Garzik | 2dcb407 | 2007-10-19 06:42:56 -0400 | [diff] [blame] | 1284 | while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) { |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1285 | /* Look for 450NX PXB. Check for problem configurations |
| 1286 | A PCI quirk checks bit 6 already */ |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1287 | pci_read_config_word(pdev, 0x41, &cfg); |
| 1288 | /* Only on the original revision: IDE DMA can hang */ |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 1289 | if (pdev->revision == 0x00) |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1290 | no_piix_dma = 1; |
| 1291 | /* On all revisions below 5 PXB bus lock must be disabled for IDE */ |
Auke Kok | 44c1013 | 2007-06-08 15:46:36 -0700 | [diff] [blame] | 1292 | else if (cfg & (1<<14) && pdev->revision < 5) |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1293 | no_piix_dma = 2; |
| 1294 | } |
Alan Cox | 31a34fe | 2006-05-22 22:58:14 +0100 | [diff] [blame] | 1295 | if (no_piix_dma) |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1296 | dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n"); |
Alan Cox | 31a34fe | 2006-05-22 22:58:14 +0100 | [diff] [blame] | 1297 | if (no_piix_dma == 2) |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1298 | dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n"); |
| 1299 | return no_piix_dma; |
Jeff Garzik | 2e9edbf | 2006-03-24 09:56:57 -0500 | [diff] [blame] | 1300 | } |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1301 | |
Tejun Heo | 8b09f0d | 2008-01-18 18:36:29 +0900 | [diff] [blame] | 1302 | static void __devinit piix_init_pcs(struct ata_host *host, |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 1303 | const struct piix_map_db *map_db) |
| 1304 | { |
Tejun Heo | 8b09f0d | 2008-01-18 18:36:29 +0900 | [diff] [blame] | 1305 | struct pci_dev *pdev = to_pci_dev(host->dev); |
Jeff Garzik | ea35d29 | 2006-07-11 11:48:50 -0400 | [diff] [blame] | 1306 | u16 pcs, new_pcs; |
| 1307 | |
| 1308 | pci_read_config_word(pdev, ICH5_PCS, &pcs); |
| 1309 | |
| 1310 | new_pcs = pcs | map_db->port_enable; |
| 1311 | |
| 1312 | if (new_pcs != pcs) { |
| 1313 | DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs); |
| 1314 | pci_write_config_word(pdev, ICH5_PCS, new_pcs); |
| 1315 | msleep(150); |
| 1316 | } |
| 1317 | } |
| 1318 | |
Tejun Heo | 8b09f0d | 2008-01-18 18:36:29 +0900 | [diff] [blame] | 1319 | static const int *__devinit piix_init_sata_map(struct pci_dev *pdev, |
| 1320 | struct ata_port_info *pinfo, |
| 1321 | const struct piix_map_db *map_db) |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1322 | { |
Al Viro | b4482a4 | 2007-10-14 19:35:40 +0100 | [diff] [blame] | 1323 | const int *map; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1324 | int i, invalid_map = 0; |
| 1325 | u8 map_value; |
| 1326 | |
| 1327 | pci_read_config_byte(pdev, ICH5_PMR, &map_value); |
| 1328 | |
| 1329 | map = map_db->map[map_value & map_db->mask]; |
| 1330 | |
| 1331 | dev_printk(KERN_INFO, &pdev->dev, "MAP ["); |
| 1332 | for (i = 0; i < 4; i++) { |
| 1333 | switch (map[i]) { |
| 1334 | case RV: |
| 1335 | invalid_map = 1; |
| 1336 | printk(" XX"); |
| 1337 | break; |
| 1338 | |
| 1339 | case NA: |
| 1340 | printk(" --"); |
| 1341 | break; |
| 1342 | |
| 1343 | case IDE: |
| 1344 | WARN_ON((i & 1) || map[i + 1] != IDE); |
Jeff Garzik | 669a5db | 2006-08-29 18:12:40 -0400 | [diff] [blame] | 1345 | pinfo[i / 2] = piix_port_info[ich_pata_100]; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1346 | i++; |
| 1347 | printk(" IDE IDE"); |
| 1348 | break; |
| 1349 | |
| 1350 | default: |
| 1351 | printk(" P%d", map[i]); |
| 1352 | if (i & 1) |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1353 | pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1354 | break; |
| 1355 | } |
| 1356 | } |
| 1357 | printk(" ]\n"); |
| 1358 | |
| 1359 | if (invalid_map) |
| 1360 | dev_printk(KERN_ERR, &pdev->dev, |
| 1361 | "invalid MAP value %u\n", map_value); |
| 1362 | |
Tejun Heo | 8b09f0d | 2008-01-18 18:36:29 +0900 | [diff] [blame] | 1363 | return map; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1364 | } |
| 1365 | |
Tejun Heo | c729072 | 2008-01-18 18:36:30 +0900 | [diff] [blame] | 1366 | static void __devinit piix_init_sidpr(struct ata_host *host) |
| 1367 | { |
| 1368 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| 1369 | struct piix_host_priv *hpriv = host->private_data; |
Tejun Heo | cb6716c | 2008-05-01 10:03:08 +0900 | [diff] [blame] | 1370 | struct ata_device *dev0 = &host->ports[0]->link.device[0]; |
| 1371 | u32 scontrol; |
Tejun Heo | c729072 | 2008-01-18 18:36:30 +0900 | [diff] [blame] | 1372 | int i; |
| 1373 | |
| 1374 | /* check for availability */ |
| 1375 | for (i = 0; i < 4; i++) |
| 1376 | if (hpriv->map[i] == IDE) |
| 1377 | return; |
| 1378 | |
| 1379 | if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR)) |
| 1380 | return; |
| 1381 | |
| 1382 | if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 || |
| 1383 | pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN) |
| 1384 | return; |
| 1385 | |
| 1386 | if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME)) |
| 1387 | return; |
| 1388 | |
| 1389 | hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR]; |
Tejun Heo | cb6716c | 2008-05-01 10:03:08 +0900 | [diff] [blame] | 1390 | |
| 1391 | /* SCR access via SIDPR doesn't work on some configurations. |
| 1392 | * Give it a test drive by inhibiting power save modes which |
| 1393 | * we'll do anyway. |
| 1394 | */ |
| 1395 | scontrol = piix_sidpr_read(dev0, SCR_CONTROL); |
| 1396 | |
| 1397 | /* if IPM is already 3, SCR access is probably working. Don't |
| 1398 | * un-inhibit power save modes as BIOS might have inhibited |
| 1399 | * them for a reason. |
| 1400 | */ |
| 1401 | if ((scontrol & 0xf00) != 0x300) { |
| 1402 | scontrol |= 0x300; |
| 1403 | piix_sidpr_write(dev0, SCR_CONTROL, scontrol); |
| 1404 | scontrol = piix_sidpr_read(dev0, SCR_CONTROL); |
| 1405 | |
| 1406 | if ((scontrol & 0xf00) != 0x300) { |
| 1407 | dev_printk(KERN_INFO, host->dev, "SCR access via " |
| 1408 | "SIDPR is available but doesn't work\n"); |
| 1409 | return; |
| 1410 | } |
| 1411 | } |
| 1412 | |
Tejun Heo | c729072 | 2008-01-18 18:36:30 +0900 | [diff] [blame] | 1413 | host->ports[0]->ops = &piix_sidpr_sata_ops; |
| 1414 | host->ports[1]->ops = &piix_sidpr_sata_ops; |
| 1415 | } |
| 1416 | |
Tejun Heo | 43a98f0 | 2007-08-23 10:15:18 +0900 | [diff] [blame] | 1417 | static void piix_iocfg_bit18_quirk(struct pci_dev *pdev) |
| 1418 | { |
Jeff Garzik | 1855256 | 2007-10-03 15:15:40 -0400 | [diff] [blame] | 1419 | static const struct dmi_system_id sysids[] = { |
Tejun Heo | 43a98f0 | 2007-08-23 10:15:18 +0900 | [diff] [blame] | 1420 | { |
| 1421 | /* Clevo M570U sets IOCFG bit 18 if the cdrom |
| 1422 | * isn't used to boot the system which |
| 1423 | * disables the channel. |
| 1424 | */ |
| 1425 | .ident = "M570U", |
| 1426 | .matches = { |
| 1427 | DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."), |
| 1428 | DMI_MATCH(DMI_PRODUCT_NAME, "M570U"), |
| 1429 | }, |
| 1430 | }, |
Jeff Garzik | 7d05154 | 2007-09-01 06:48:52 -0400 | [diff] [blame] | 1431 | |
| 1432 | { } /* terminate list */ |
Tejun Heo | 43a98f0 | 2007-08-23 10:15:18 +0900 | [diff] [blame] | 1433 | }; |
| 1434 | u32 iocfg; |
| 1435 | |
| 1436 | if (!dmi_check_system(sysids)) |
| 1437 | return; |
| 1438 | |
| 1439 | /* The datasheet says that bit 18 is NOOP but certain systems |
| 1440 | * seem to use it to disable a channel. Clear the bit on the |
| 1441 | * affected systems. |
| 1442 | */ |
| 1443 | pci_read_config_dword(pdev, PIIX_IOCFG, &iocfg); |
| 1444 | if (iocfg & (1 << 18)) { |
| 1445 | dev_printk(KERN_INFO, &pdev->dev, |
| 1446 | "applying IOCFG bit18 quirk\n"); |
| 1447 | iocfg &= ~(1 << 18); |
| 1448 | pci_write_config_dword(pdev, PIIX_IOCFG, iocfg); |
| 1449 | } |
| 1450 | } |
| 1451 | |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1452 | /** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1453 | * piix_init_one - Register PIIX ATA PCI device with kernel services |
| 1454 | * @pdev: PCI device to register |
| 1455 | * @ent: Entry in piix_pci_tbl matching with @pdev |
| 1456 | * |
| 1457 | * Called from kernel PCI layer. We probe for combined mode (sigh), |
| 1458 | * and then hand over control to libata, for it to do the rest. |
| 1459 | * |
| 1460 | * LOCKING: |
| 1461 | * Inherited from PCI layer (may sleep). |
| 1462 | * |
| 1463 | * RETURNS: |
| 1464 | * Zero on success, or -ERRNO value. |
| 1465 | */ |
| 1466 | |
Adrian Bunk | bc5468f | 2008-01-30 22:02:02 +0200 | [diff] [blame] | 1467 | static int __devinit piix_init_one(struct pci_dev *pdev, |
| 1468 | const struct pci_device_id *ent) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1469 | { |
| 1470 | static int printed_version; |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1471 | struct device *dev = &pdev->dev; |
Tejun Heo | d33f58b | 2006-03-01 01:25:39 +0900 | [diff] [blame] | 1472 | struct ata_port_info port_info[2]; |
Tejun Heo | 1626aeb | 2007-05-04 12:43:58 +0200 | [diff] [blame] | 1473 | const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] }; |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1474 | unsigned long port_flags; |
Tejun Heo | 8b09f0d | 2008-01-18 18:36:29 +0900 | [diff] [blame] | 1475 | struct ata_host *host; |
| 1476 | struct piix_host_priv *hpriv; |
| 1477 | int rc; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1478 | |
| 1479 | if (!printed_version++) |
Jeff Garzik | 6248e64 | 2005-10-30 06:42:18 -0500 | [diff] [blame] | 1480 | dev_printk(KERN_DEBUG, &pdev->dev, |
| 1481 | "version " DRV_VERSION "\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1482 | |
| 1483 | /* no hotplugging support (FIXME) */ |
| 1484 | if (!in_module_init) |
| 1485 | return -ENODEV; |
| 1486 | |
Tejun Heo | 8b09f0d | 2008-01-18 18:36:29 +0900 | [diff] [blame] | 1487 | port_info[0] = piix_port_info[ent->driver_data]; |
| 1488 | port_info[1] = piix_port_info[ent->driver_data]; |
| 1489 | |
| 1490 | port_flags = port_info[0].flags; |
| 1491 | |
| 1492 | /* enable device and prepare host */ |
| 1493 | rc = pcim_enable_device(pdev); |
| 1494 | if (rc) |
| 1495 | return rc; |
| 1496 | |
Tejun Heo | 5016d7d | 2008-03-26 15:46:58 +0900 | [diff] [blame] | 1497 | /* ICH6R may be driven by either ata_piix or ahci driver |
| 1498 | * regardless of BIOS configuration. Make sure AHCI mode is |
| 1499 | * off. |
| 1500 | */ |
| 1501 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) { |
| 1502 | int rc = piix_disable_ahci(pdev); |
| 1503 | if (rc) |
| 1504 | return rc; |
| 1505 | } |
| 1506 | |
Tejun Heo | 8b09f0d | 2008-01-18 18:36:29 +0900 | [diff] [blame] | 1507 | /* SATA map init can change port_info, do it before prepping host */ |
Tejun Heo | 24dc5f3 | 2007-01-20 16:00:28 +0900 | [diff] [blame] | 1508 | hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
Tejun Heo | d96715c | 2006-06-29 01:58:28 +0900 | [diff] [blame] | 1509 | if (!hpriv) |
| 1510 | return -ENOMEM; |
| 1511 | |
Tejun Heo | 8b09f0d | 2008-01-18 18:36:29 +0900 | [diff] [blame] | 1512 | if (port_flags & ATA_FLAG_SATA) |
| 1513 | hpriv->map = piix_init_sata_map(pdev, port_info, |
| 1514 | piix_map_db_table[ent->driver_data]); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1515 | |
Tejun Heo | 9363c38 | 2008-04-07 22:47:16 +0900 | [diff] [blame] | 1516 | rc = ata_pci_sff_prepare_host(pdev, ppi, &host); |
Tejun Heo | 8b09f0d | 2008-01-18 18:36:29 +0900 | [diff] [blame] | 1517 | if (rc) |
| 1518 | return rc; |
| 1519 | host->private_data = hpriv; |
Tejun Heo | ff0fc14 | 2005-12-18 17:17:07 +0900 | [diff] [blame] | 1520 | |
Tejun Heo | 8b09f0d | 2008-01-18 18:36:29 +0900 | [diff] [blame] | 1521 | /* initialize controller */ |
Tejun Heo | c729072 | 2008-01-18 18:36:30 +0900 | [diff] [blame] | 1522 | if (port_flags & ATA_FLAG_SATA) { |
Tejun Heo | 8b09f0d | 2008-01-18 18:36:29 +0900 | [diff] [blame] | 1523 | piix_init_pcs(host, piix_map_db_table[ent->driver_data]); |
Tejun Heo | c729072 | 2008-01-18 18:36:30 +0900 | [diff] [blame] | 1524 | piix_init_sidpr(host); |
| 1525 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1526 | |
Tejun Heo | 43a98f0 | 2007-08-23 10:15:18 +0900 | [diff] [blame] | 1527 | /* apply IOCFG bit18 quirk */ |
| 1528 | piix_iocfg_bit18_quirk(pdev); |
| 1529 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1530 | /* On ICH5, some BIOSen disable the interrupt using the |
| 1531 | * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3. |
| 1532 | * On ICH6, this bit has the same effect, but only when |
| 1533 | * MSI is disabled (and it is disabled, as we don't use |
| 1534 | * message-signalled interrupts currently). |
| 1535 | */ |
Jeff Garzik | cca3974 | 2006-08-24 03:19:22 -0400 | [diff] [blame] | 1536 | if (port_flags & PIIX_FLAG_CHECKINTR) |
Brett M Russ | a04ce0f | 2005-08-15 15:23:41 -0400 | [diff] [blame] | 1537 | pci_intx(pdev, 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1538 | |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1539 | if (piix_check_450nx_errata(pdev)) { |
| 1540 | /* This writes into the master table but it does not |
| 1541 | really matter for this errata as we will apply it to |
| 1542 | all the PIIX devices on the board */ |
Tejun Heo | 8b09f0d | 2008-01-18 18:36:29 +0900 | [diff] [blame] | 1543 | host->ports[0]->mwdma_mask = 0; |
| 1544 | host->ports[0]->udma_mask = 0; |
| 1545 | host->ports[1]->mwdma_mask = 0; |
| 1546 | host->ports[1]->udma_mask = 0; |
Alan Cox | c621b14 | 2005-12-08 19:22:28 +0000 | [diff] [blame] | 1547 | } |
Tejun Heo | 8b09f0d | 2008-01-18 18:36:29 +0900 | [diff] [blame] | 1548 | |
| 1549 | pci_set_master(pdev); |
Tejun Heo | 9363c38 | 2008-04-07 22:47:16 +0900 | [diff] [blame] | 1550 | return ata_pci_sff_activate_host(host, ata_sff_interrupt, &piix_sht); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1551 | } |
| 1552 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1553 | static int __init piix_init(void) |
| 1554 | { |
| 1555 | int rc; |
| 1556 | |
Pavel Roskin | b788719 | 2006-08-10 18:13:18 +0900 | [diff] [blame] | 1557 | DPRINTK("pci_register_driver\n"); |
| 1558 | rc = pci_register_driver(&piix_pci_driver); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1559 | if (rc) |
| 1560 | return rc; |
| 1561 | |
| 1562 | in_module_init = 0; |
| 1563 | |
| 1564 | DPRINTK("done\n"); |
| 1565 | return 0; |
| 1566 | } |
| 1567 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1568 | static void __exit piix_exit(void) |
| 1569 | { |
| 1570 | pci_unregister_driver(&piix_pci_driver); |
| 1571 | } |
| 1572 | |
| 1573 | module_init(piix_init); |
| 1574 | module_exit(piix_exit); |