blob: fad189e01ec631606a13c4583f030225a5d5a109 [file] [log] [blame]
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
Stephen Hemminger747802a2005-06-27 11:33:16 -070010 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040011 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
Stephen Hemminger798b6b12006-10-22 20:16:57 -070014 * the Free Software Foundation; either version 2 of the License.
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040015 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
Arnaldo Carvalho de Melo14c85022005-12-27 02:43:12 -020026#include <linux/in.h>
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040027#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/if_vlan.h>
35#include <linux/ip.h>
36#include <linux/delay.h>
37#include <linux/crc32.h>
Al Viro40754002005-04-03 09:15:52 +010038#include <linux/dma-mapping.h>
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -080039#include <linux/mii.h>
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040040#include <asm/irq.h>
41
42#include "skge.h"
43
44#define DRV_NAME "skge"
Stephen Hemmingera407a6a2007-02-02 08:22:54 -080045#define DRV_VERSION "1.10"
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040046#define PFX DRV_NAME " "
47
48#define DEFAULT_TX_RING_SIZE 128
49#define DEFAULT_RX_RING_SIZE 512
50#define MAX_TX_RING_SIZE 1024
Stephen Hemminger9db96472006-06-06 10:11:12 -070051#define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040052#define MAX_RX_RING_SIZE 4096
Stephen Hemminger19a33d42005-06-27 11:33:15 -070053#define RX_COPY_THRESHOLD 128
54#define RX_BUF_SIZE 1536
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040055#define PHY_RETRIES 1000
56#define ETH_JUMBO_MTU 9000
57#define TX_WATCHDOG (5 * HZ)
58#define NAPI_WEIGHT 64
Stephen Hemminger6abebb52005-07-22 16:26:10 -070059#define BLINK_MS 250
Stephen Hemminger64f6b642006-09-23 21:25:28 -070060#define LINK_HZ (HZ/2)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040061
62MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
Stephen Hemminger65ebe632007-01-23 11:38:57 -080063MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040064MODULE_LICENSE("GPL");
65MODULE_VERSION(DRV_VERSION);
66
67static const u32 default_msg
68 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
70
71static int debug = -1; /* defaults above */
72module_param(debug, int, 0);
73MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
74
75static const struct pci_device_id skge_id_table[] = {
Stephen Hemminger275834d2005-06-27 11:33:03 -070076 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
Stephen Hemmingerf19841f2007-02-23 14:04:54 -080080 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
Stephen Hemminger2d2a3872006-05-17 14:37:04 -070081 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
Stephen Hemminger275834d2005-06-27 11:33:03 -070082 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
84 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
Stephen Hemminger275834d2005-06-27 11:33:03 -070085 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
Stephen Hemmingerf19841f2007-02-23 14:04:54 -080086 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040087 { 0 }
88};
89MODULE_DEVICE_TABLE(pci, skge_id_table);
90
91static int skge_up(struct net_device *dev);
92static int skge_down(struct net_device *dev);
Stephen Hemmingeree294dc2005-12-14 15:47:44 -080093static void skge_phy_reset(struct skge_port *skge);
Stephen Hemminger513f5332006-09-01 15:53:49 -070094static void skge_tx_clean(struct net_device *dev);
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -080095static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -040097static void genesis_get_stats(struct skge_port *skge, u64 *data);
98static void yukon_get_stats(struct skge_port *skge, u64 *data);
99static void yukon_init(struct skge_hw *hw, int port);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400100static void genesis_mac_init(struct skge_hw *hw, int port);
Stephen Hemminger45bada62005-06-27 11:33:12 -0700101static void genesis_link_up(struct skge_port *skge);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400102
Stephen Hemminger7e676d92005-06-27 11:33:13 -0700103/* Avoid conditionals by using array */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400104static const int txqaddr[] = { Q_XA1, Q_XA2 };
105static const int rxqaddr[] = { Q_R1, Q_R2 };
106static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
107static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
Stephen Hemminger513f5332006-09-01 15:53:49 -0700108static const u32 irqmask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400109
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400110static int skge_get_regs_len(struct net_device *dev)
111{
Stephen Hemmingerc3f8be92005-09-19 15:37:34 -0700112 return 0x4000;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400113}
114
115/*
Stephen Hemmingerc3f8be92005-09-19 15:37:34 -0700116 * Returns copy of whole control register region
117 * Note: skip RAM address register because accessing it will
118 * cause bus hangs!
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400119 */
120static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
121 void *p)
122{
123 const struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400124 const void __iomem *io = skge->hw->regs;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400125
126 regs->version = 1;
Stephen Hemmingerc3f8be92005-09-19 15:37:34 -0700127 memset(p, 0, regs->len);
128 memcpy_fromio(p, io, B3_RAM_ADDR);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400129
Stephen Hemmingerc3f8be92005-09-19 15:37:34 -0700130 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
131 regs->len - B3_RI_WTO_R1);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400132}
133
Stephen Hemminger8f3f8192005-11-08 10:33:45 -0800134/* Wake on Lan only supported on Yukon chips with rev 1 or above */
Stephen Hemmingera504e642007-02-02 08:22:53 -0800135static u32 wol_supported(const struct skge_hw *hw)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400136{
Stephen Hemmingera504e642007-02-02 08:22:53 -0800137 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev != 0)
138 return WAKE_MAGIC | WAKE_PHY;
139 else
140 return 0;
141}
142
143static u32 pci_wake_enabled(struct pci_dev *dev)
144{
145 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
146 u16 value;
147
148 /* If device doesn't support PM Capabilities, but request is to disable
149 * wake events, it's a nop; otherwise fail */
150 if (!pm)
151 return 0;
152
153 pci_read_config_word(dev, pm + PCI_PM_PMC, &value);
154
155 value &= PCI_PM_CAP_PME_MASK;
156 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
157
158 return value != 0;
159}
160
161static void skge_wol_init(struct skge_port *skge)
162{
163 struct skge_hw *hw = skge->hw;
164 int port = skge->port;
165 enum pause_control save_mode;
166 u32 ctrl;
167
168 /* Bring hardware out of reset */
169 skge_write16(hw, B0_CTST, CS_RST_CLR);
170 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
171
172 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
173 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
174
175 /* Force to 10/100 skge_reset will re-enable on resume */
176 save_mode = skge->flow_control;
177 skge->flow_control = FLOW_MODE_SYMMETRIC;
178
179 ctrl = skge->advertising;
180 skge->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
181
182 skge_phy_reset(skge);
183
184 skge->flow_control = save_mode;
185 skge->advertising = ctrl;
186
187 /* Set GMAC to no flow control and auto update for speed/duplex */
188 gma_write16(hw, port, GM_GP_CTRL,
189 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
190 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
191
192 /* Set WOL address */
193 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
194 skge->netdev->dev_addr, ETH_ALEN);
195
196 /* Turn on appropriate WOL control bits */
197 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
198 ctrl = 0;
199 if (skge->wol & WAKE_PHY)
200 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
201 else
202 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
203
204 if (skge->wol & WAKE_MAGIC)
205 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
206 else
207 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
208
209 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
210 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
211
212 /* block receiver */
213 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400214}
215
216static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
217{
218 struct skge_port *skge = netdev_priv(dev);
219
Stephen Hemmingera504e642007-02-02 08:22:53 -0800220 wol->supported = wol_supported(skge->hw);
221 wol->wolopts = skge->wol;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400222}
223
224static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
225{
226 struct skge_port *skge = netdev_priv(dev);
227 struct skge_hw *hw = skge->hw;
228
Stephen Hemmingera504e642007-02-02 08:22:53 -0800229 if (wol->wolopts & wol_supported(hw))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400230 return -EOPNOTSUPP;
231
Stephen Hemmingera504e642007-02-02 08:22:53 -0800232 skge->wol = wol->wolopts;
233 if (!netif_running(dev))
234 skge_wol_init(skge);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400235 return 0;
236}
237
Stephen Hemminger8f3f8192005-11-08 10:33:45 -0800238/* Determine supported/advertised modes based on hardware.
239 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700240 */
241static u32 skge_supported_modes(const struct skge_hw *hw)
242{
243 u32 supported;
244
Stephen Hemminger5e1705d2005-08-16 14:00:58 -0700245 if (hw->copper) {
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700246 supported = SUPPORTED_10baseT_Half
247 | SUPPORTED_10baseT_Full
248 | SUPPORTED_100baseT_Half
249 | SUPPORTED_100baseT_Full
250 | SUPPORTED_1000baseT_Half
251 | SUPPORTED_1000baseT_Full
252 | SUPPORTED_Autoneg| SUPPORTED_TP;
253
254 if (hw->chip_id == CHIP_ID_GENESIS)
255 supported &= ~(SUPPORTED_10baseT_Half
256 | SUPPORTED_10baseT_Full
257 | SUPPORTED_100baseT_Half
258 | SUPPORTED_100baseT_Full);
259
260 else if (hw->chip_id == CHIP_ID_YUKON)
261 supported &= ~SUPPORTED_1000baseT_Half;
262 } else
Stephen Hemminger4b67be92006-10-05 15:49:51 -0700263 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
264 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700265
266 return supported;
267}
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400268
269static int skge_get_settings(struct net_device *dev,
270 struct ethtool_cmd *ecmd)
271{
272 struct skge_port *skge = netdev_priv(dev);
273 struct skge_hw *hw = skge->hw;
274
275 ecmd->transceiver = XCVR_INTERNAL;
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700276 ecmd->supported = skge_supported_modes(hw);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400277
Stephen Hemminger5e1705d2005-08-16 14:00:58 -0700278 if (hw->copper) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400279 ecmd->port = PORT_TP;
280 ecmd->phy_address = hw->phy_addr;
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700281 } else
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400282 ecmd->port = PORT_FIBRE;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400283
284 ecmd->advertising = skge->advertising;
285 ecmd->autoneg = skge->autoneg;
286 ecmd->speed = skge->speed;
287 ecmd->duplex = skge->duplex;
288 return 0;
289}
290
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400291static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
292{
293 struct skge_port *skge = netdev_priv(dev);
294 const struct skge_hw *hw = skge->hw;
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700295 u32 supported = skge_supported_modes(hw);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400296
297 if (ecmd->autoneg == AUTONEG_ENABLE) {
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700298 ecmd->advertising = supported;
299 skge->duplex = -1;
300 skge->speed = -1;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400301 } else {
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700302 u32 setting;
303
Stephen Hemminger2c668512005-07-22 16:26:07 -0700304 switch (ecmd->speed) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400305 case SPEED_1000:
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700306 if (ecmd->duplex == DUPLEX_FULL)
307 setting = SUPPORTED_1000baseT_Full;
308 else if (ecmd->duplex == DUPLEX_HALF)
309 setting = SUPPORTED_1000baseT_Half;
310 else
311 return -EINVAL;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400312 break;
313 case SPEED_100:
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700314 if (ecmd->duplex == DUPLEX_FULL)
315 setting = SUPPORTED_100baseT_Full;
316 else if (ecmd->duplex == DUPLEX_HALF)
317 setting = SUPPORTED_100baseT_Half;
318 else
319 return -EINVAL;
320 break;
321
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400322 case SPEED_10:
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700323 if (ecmd->duplex == DUPLEX_FULL)
324 setting = SUPPORTED_10baseT_Full;
325 else if (ecmd->duplex == DUPLEX_HALF)
326 setting = SUPPORTED_10baseT_Half;
327 else
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400328 return -EINVAL;
329 break;
330 default:
331 return -EINVAL;
332 }
Stephen Hemminger31b619c2005-06-27 11:33:11 -0700333
334 if ((setting & supported) == 0)
335 return -EINVAL;
336
337 skge->speed = ecmd->speed;
338 skge->duplex = ecmd->duplex;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400339 }
340
341 skge->autoneg = ecmd->autoneg;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400342 skge->advertising = ecmd->advertising;
343
Stephen Hemmingeree294dc2005-12-14 15:47:44 -0800344 if (netif_running(dev))
345 skge_phy_reset(skge);
346
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400347 return (0);
348}
349
350static void skge_get_drvinfo(struct net_device *dev,
351 struct ethtool_drvinfo *info)
352{
353 struct skge_port *skge = netdev_priv(dev);
354
355 strcpy(info->driver, DRV_NAME);
356 strcpy(info->version, DRV_VERSION);
357 strcpy(info->fw_version, "N/A");
358 strcpy(info->bus_info, pci_name(skge->hw->pdev));
359}
360
361static const struct skge_stat {
362 char name[ETH_GSTRING_LEN];
363 u16 xmac_offset;
364 u16 gma_offset;
365} skge_stats[] = {
366 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
367 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
368
369 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
370 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
371 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
372 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
373 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
374 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
375 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
376 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
377
378 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
379 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
380 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
381 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
382 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
383 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
384
385 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
386 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
387 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
388 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
389 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
390};
391
392static int skge_get_stats_count(struct net_device *dev)
393{
394 return ARRAY_SIZE(skge_stats);
395}
396
397static void skge_get_ethtool_stats(struct net_device *dev,
398 struct ethtool_stats *stats, u64 *data)
399{
400 struct skge_port *skge = netdev_priv(dev);
401
402 if (skge->hw->chip_id == CHIP_ID_GENESIS)
403 genesis_get_stats(skge, data);
404 else
405 yukon_get_stats(skge, data);
406}
407
408/* Use hardware MIB variables for critical path statistics and
409 * transmit feedback not reported at interrupt.
410 * Other errors are accounted for in interrupt handler.
411 */
412static struct net_device_stats *skge_get_stats(struct net_device *dev)
413{
414 struct skge_port *skge = netdev_priv(dev);
415 u64 data[ARRAY_SIZE(skge_stats)];
416
417 if (skge->hw->chip_id == CHIP_ID_GENESIS)
418 genesis_get_stats(skge, data);
419 else
420 yukon_get_stats(skge, data);
421
422 skge->net_stats.tx_bytes = data[0];
423 skge->net_stats.rx_bytes = data[1];
424 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
425 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
Stephen Hemminger4c180fc2006-03-23 11:07:26 -0800426 skge->net_stats.multicast = data[3] + data[5];
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400427 skge->net_stats.collisions = data[10];
428 skge->net_stats.tx_aborted_errors = data[12];
429
430 return &skge->net_stats;
431}
432
433static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
434{
435 int i;
436
Stephen Hemminger95566062005-06-27 11:33:02 -0700437 switch (stringset) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400438 case ETH_SS_STATS:
439 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
440 memcpy(data + i * ETH_GSTRING_LEN,
441 skge_stats[i].name, ETH_GSTRING_LEN);
442 break;
443 }
444}
445
446static void skge_get_ring_param(struct net_device *dev,
447 struct ethtool_ringparam *p)
448{
449 struct skge_port *skge = netdev_priv(dev);
450
451 p->rx_max_pending = MAX_RX_RING_SIZE;
452 p->tx_max_pending = MAX_TX_RING_SIZE;
453 p->rx_mini_max_pending = 0;
454 p->rx_jumbo_max_pending = 0;
455
456 p->rx_pending = skge->rx_ring.count;
457 p->tx_pending = skge->tx_ring.count;
458 p->rx_mini_pending = 0;
459 p->rx_jumbo_pending = 0;
460}
461
462static int skge_set_ring_param(struct net_device *dev,
463 struct ethtool_ringparam *p)
464{
465 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger3b8bb472005-12-14 15:47:48 -0800466 int err;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400467
468 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
Stephen Hemminger9db96472006-06-06 10:11:12 -0700469 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400470 return -EINVAL;
471
472 skge->rx_ring.count = p->rx_pending;
473 skge->tx_ring.count = p->tx_pending;
474
475 if (netif_running(dev)) {
476 skge_down(dev);
Stephen Hemminger3b8bb472005-12-14 15:47:48 -0800477 err = skge_up(dev);
478 if (err)
479 dev_close(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400480 }
481
482 return 0;
483}
484
485static u32 skge_get_msglevel(struct net_device *netdev)
486{
487 struct skge_port *skge = netdev_priv(netdev);
488 return skge->msg_enable;
489}
490
491static void skge_set_msglevel(struct net_device *netdev, u32 value)
492{
493 struct skge_port *skge = netdev_priv(netdev);
494 skge->msg_enable = value;
495}
496
497static int skge_nway_reset(struct net_device *dev)
498{
499 struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400500
501 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
502 return -EINVAL;
503
Stephen Hemmingeree294dc2005-12-14 15:47:44 -0800504 skge_phy_reset(skge);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400505 return 0;
506}
507
508static int skge_set_sg(struct net_device *dev, u32 data)
509{
510 struct skge_port *skge = netdev_priv(dev);
511 struct skge_hw *hw = skge->hw;
512
513 if (hw->chip_id == CHIP_ID_GENESIS && data)
514 return -EOPNOTSUPP;
515 return ethtool_op_set_sg(dev, data);
516}
517
518static int skge_set_tx_csum(struct net_device *dev, u32 data)
519{
520 struct skge_port *skge = netdev_priv(dev);
521 struct skge_hw *hw = skge->hw;
522
523 if (hw->chip_id == CHIP_ID_GENESIS && data)
524 return -EOPNOTSUPP;
525
526 return ethtool_op_set_tx_csum(dev, data);
527}
528
529static u32 skge_get_rx_csum(struct net_device *dev)
530{
531 struct skge_port *skge = netdev_priv(dev);
532
533 return skge->rx_csum;
534}
535
536/* Only Yukon supports checksum offload. */
537static int skge_set_rx_csum(struct net_device *dev, u32 data)
538{
539 struct skge_port *skge = netdev_priv(dev);
540
541 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
542 return -EOPNOTSUPP;
543
544 skge->rx_csum = data;
545 return 0;
546}
547
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400548static void skge_get_pauseparam(struct net_device *dev,
549 struct ethtool_pauseparam *ecmd)
550{
551 struct skge_port *skge = netdev_priv(dev);
552
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -0700553 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_SYMMETRIC)
554 || (skge->flow_control == FLOW_MODE_SYM_OR_REM);
555 ecmd->tx_pause = ecmd->rx_pause || (skge->flow_control == FLOW_MODE_LOC_SEND);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400556
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -0700557 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400558}
559
560static int skge_set_pauseparam(struct net_device *dev,
561 struct ethtool_pauseparam *ecmd)
562{
563 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -0700564 struct ethtool_pauseparam old;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400565
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -0700566 skge_get_pauseparam(dev, &old);
567
568 if (ecmd->autoneg != old.autoneg)
569 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
570 else {
571 if (ecmd->rx_pause && ecmd->tx_pause)
572 skge->flow_control = FLOW_MODE_SYMMETRIC;
573 else if (ecmd->rx_pause && !ecmd->tx_pause)
574 skge->flow_control = FLOW_MODE_SYM_OR_REM;
575 else if (!ecmd->rx_pause && ecmd->tx_pause)
576 skge->flow_control = FLOW_MODE_LOC_SEND;
577 else
578 skge->flow_control = FLOW_MODE_NONE;
579 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400580
Stephen Hemmingere8df8552005-12-14 15:47:45 -0800581 if (netif_running(dev))
582 skge_phy_reset(skge);
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -0700583
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400584 return 0;
585}
586
587/* Chip internal frequency for clock calculations */
588static inline u32 hwkhz(const struct skge_hw *hw)
589{
Stephen Hemminger187ff3b2006-07-19 14:08:42 -0700590 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400591}
592
Stephen Hemminger8f3f8192005-11-08 10:33:45 -0800593/* Chip HZ to microseconds */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400594static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
595{
596 return (ticks * 1000) / hwkhz(hw);
597}
598
Stephen Hemminger8f3f8192005-11-08 10:33:45 -0800599/* Microseconds to chip HZ */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400600static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
601{
602 return hwkhz(hw) * usec / 1000;
603}
604
605static int skge_get_coalesce(struct net_device *dev,
606 struct ethtool_coalesce *ecmd)
607{
608 struct skge_port *skge = netdev_priv(dev);
609 struct skge_hw *hw = skge->hw;
610 int port = skge->port;
611
612 ecmd->rx_coalesce_usecs = 0;
613 ecmd->tx_coalesce_usecs = 0;
614
615 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
616 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
617 u32 msk = skge_read32(hw, B2_IRQM_MSK);
618
619 if (msk & rxirqmask[port])
620 ecmd->rx_coalesce_usecs = delay;
621 if (msk & txirqmask[port])
622 ecmd->tx_coalesce_usecs = delay;
623 }
624
625 return 0;
626}
627
628/* Note: interrupt timer is per board, but can turn on/off per port */
629static int skge_set_coalesce(struct net_device *dev,
630 struct ethtool_coalesce *ecmd)
631{
632 struct skge_port *skge = netdev_priv(dev);
633 struct skge_hw *hw = skge->hw;
634 int port = skge->port;
635 u32 msk = skge_read32(hw, B2_IRQM_MSK);
636 u32 delay = 25;
637
638 if (ecmd->rx_coalesce_usecs == 0)
639 msk &= ~rxirqmask[port];
640 else if (ecmd->rx_coalesce_usecs < 25 ||
641 ecmd->rx_coalesce_usecs > 33333)
642 return -EINVAL;
643 else {
644 msk |= rxirqmask[port];
645 delay = ecmd->rx_coalesce_usecs;
646 }
647
648 if (ecmd->tx_coalesce_usecs == 0)
649 msk &= ~txirqmask[port];
650 else if (ecmd->tx_coalesce_usecs < 25 ||
651 ecmd->tx_coalesce_usecs > 33333)
652 return -EINVAL;
653 else {
654 msk |= txirqmask[port];
655 delay = min(delay, ecmd->rx_coalesce_usecs);
656 }
657
658 skge_write32(hw, B2_IRQM_MSK, msk);
659 if (msk == 0)
660 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
661 else {
662 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
663 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
664 }
665 return 0;
666}
667
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700668enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
669static void skge_led(struct skge_port *skge, enum led_mode mode)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400670{
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400671 struct skge_hw *hw = skge->hw;
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700672 int port = skge->port;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400673
Stephen Hemmingerd85b5142006-06-06 10:11:11 -0700674 mutex_lock(&hw->phy_mutex);
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700675 if (hw->chip_id == CHIP_ID_GENESIS) {
676 switch (mode) {
677 case LED_MODE_OFF:
Stephen Hemminger64f6b642006-09-23 21:25:28 -0700678 if (hw->phy_type == SK_PHY_BCOM)
679 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
680 else {
681 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
682 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
683 }
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700684 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
685 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
686 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
687 break;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400688
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700689 case LED_MODE_ON:
690 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
691 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
692
693 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
694 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
695
696 break;
697
698 case LED_MODE_TST:
699 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
700 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
701 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
702
Stephen Hemminger64f6b642006-09-23 21:25:28 -0700703 if (hw->phy_type == SK_PHY_BCOM)
704 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
705 else {
706 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
707 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
708 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
709 }
710
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700711 }
712 } else {
713 switch (mode) {
714 case LED_MODE_OFF:
715 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
716 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
717 PHY_M_LED_MO_DUP(MO_LED_OFF) |
718 PHY_M_LED_MO_10(MO_LED_OFF) |
719 PHY_M_LED_MO_100(MO_LED_OFF) |
720 PHY_M_LED_MO_1000(MO_LED_OFF) |
721 PHY_M_LED_MO_RX(MO_LED_OFF));
722 break;
723 case LED_MODE_ON:
724 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
725 PHY_M_LED_PULS_DUR(PULS_170MS) |
726 PHY_M_LED_BLINK_RT(BLINK_84MS) |
727 PHY_M_LEDC_TX_CTRL |
728 PHY_M_LEDC_DP_CTRL);
Stephen Hemminger46a60f22005-09-09 12:54:56 -0700729
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700730 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
731 PHY_M_LED_MO_RX(MO_LED_OFF) |
732 (skge->speed == SPEED_100 ?
733 PHY_M_LED_MO_100(MO_LED_ON) : 0));
734 break;
735 case LED_MODE_TST:
736 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
737 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
738 PHY_M_LED_MO_DUP(MO_LED_ON) |
739 PHY_M_LED_MO_10(MO_LED_ON) |
740 PHY_M_LED_MO_100(MO_LED_ON) |
741 PHY_M_LED_MO_1000(MO_LED_ON) |
742 PHY_M_LED_MO_RX(MO_LED_ON));
743 }
744 }
Stephen Hemmingerd85b5142006-06-06 10:11:11 -0700745 mutex_unlock(&hw->phy_mutex);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400746}
747
748/* blink LED's for finding board */
749static int skge_phys_id(struct net_device *dev, u32 data)
750{
751 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700752 unsigned long ms;
753 enum led_mode mode = LED_MODE_TST;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400754
Stephen Hemminger95566062005-06-27 11:33:02 -0700755 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700756 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
757 else
758 ms = data * 1000;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400759
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700760 while (ms > 0) {
761 skge_led(skge, mode);
762 mode ^= LED_MODE_TST;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400763
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700764 if (msleep_interruptible(BLINK_MS))
765 break;
766 ms -= BLINK_MS;
767 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400768
Stephen Hemminger6abebb52005-07-22 16:26:10 -0700769 /* back to regular LED state */
770 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400771
772 return 0;
773}
774
Jeff Garzik7282d492006-09-13 14:30:00 -0400775static const struct ethtool_ops skge_ethtool_ops = {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400776 .get_settings = skge_get_settings,
777 .set_settings = skge_set_settings,
778 .get_drvinfo = skge_get_drvinfo,
779 .get_regs_len = skge_get_regs_len,
780 .get_regs = skge_get_regs,
781 .get_wol = skge_get_wol,
782 .set_wol = skge_set_wol,
783 .get_msglevel = skge_get_msglevel,
784 .set_msglevel = skge_set_msglevel,
785 .nway_reset = skge_nway_reset,
786 .get_link = ethtool_op_get_link,
787 .get_ringparam = skge_get_ring_param,
788 .set_ringparam = skge_set_ring_param,
789 .get_pauseparam = skge_get_pauseparam,
790 .set_pauseparam = skge_set_pauseparam,
791 .get_coalesce = skge_get_coalesce,
792 .set_coalesce = skge_set_coalesce,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400793 .get_sg = ethtool_op_get_sg,
794 .set_sg = skge_set_sg,
795 .get_tx_csum = ethtool_op_get_tx_csum,
796 .set_tx_csum = skge_set_tx_csum,
797 .get_rx_csum = skge_get_rx_csum,
798 .set_rx_csum = skge_set_rx_csum,
799 .get_strings = skge_get_strings,
800 .phys_id = skge_phys_id,
801 .get_stats_count = skge_get_stats_count,
802 .get_ethtool_stats = skge_get_ethtool_stats,
John W. Linville56230d52005-09-12 10:48:57 -0400803 .get_perm_addr = ethtool_op_get_perm_addr,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400804};
805
806/*
807 * Allocate ring elements and chain them together
808 * One-to-one association of board descriptors with ring elements
809 */
Stephen Hemmingerc3da1442006-03-21 10:57:01 -0800810static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400811{
812 struct skge_tx_desc *d;
813 struct skge_element *e;
814 int i;
815
Robert P. J. Daycd861282006-12-13 00:34:52 -0800816 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400817 if (!ring->start)
818 return -ENOMEM;
819
820 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
821 e->desc = d;
822 if (i == ring->count - 1) {
823 e->next = ring->start;
824 d->next_offset = base;
825 } else {
826 e->next = e + 1;
827 d->next_offset = base + (i+1) * sizeof(*d);
828 }
829 }
830 ring->to_use = ring->to_clean = ring->start;
831
832 return 0;
833}
834
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700835/* Allocate and setup a new buffer for receiving */
836static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
837 struct sk_buff *skb, unsigned int bufsize)
838{
839 struct skge_rx_desc *rd = e->desc;
840 u64 map;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400841
842 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
843 PCI_DMA_FROMDEVICE);
844
845 rd->dma_lo = map;
846 rd->dma_hi = map >> 32;
847 e->skb = skb;
848 rd->csum1_start = ETH_HLEN;
849 rd->csum2_start = ETH_HLEN;
850 rd->csum1 = 0;
851 rd->csum2 = 0;
852
853 wmb();
854
855 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
856 pci_unmap_addr_set(e, mapaddr, map);
857 pci_unmap_len_set(e, maplen, bufsize);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400858}
859
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700860/* Resume receiving using existing skb,
861 * Note: DMA address is not changed by chip.
862 * MTU not changed while receiver active.
863 */
Stephen Hemminger5a011442006-03-23 11:07:25 -0800864static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700865{
866 struct skge_rx_desc *rd = e->desc;
867
868 rd->csum2 = 0;
869 rd->csum2_start = ETH_HLEN;
870
871 wmb();
872
873 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
874}
875
876
877/* Free all buffers in receive ring, assumes receiver stopped */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400878static void skge_rx_clean(struct skge_port *skge)
879{
880 struct skge_hw *hw = skge->hw;
881 struct skge_ring *ring = &skge->rx_ring;
882 struct skge_element *e;
883
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700884 e = ring->start;
885 do {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400886 struct skge_rx_desc *rd = e->desc;
887 rd->control = 0;
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700888 if (e->skb) {
889 pci_unmap_single(hw->pdev,
890 pci_unmap_addr(e, mapaddr),
891 pci_unmap_len(e, maplen),
892 PCI_DMA_FROMDEVICE);
893 dev_kfree_skb(e->skb);
894 e->skb = NULL;
895 }
896 } while ((e = e->next) != ring->start);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400897}
898
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700899
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400900/* Allocate buffers for receive ring
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700901 * For receive: to_clean is next received frame.
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400902 */
Stephen Hemmingerc54f9762006-09-01 15:53:47 -0700903static int skge_rx_fill(struct net_device *dev)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400904{
Stephen Hemmingerc54f9762006-09-01 15:53:47 -0700905 struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400906 struct skge_ring *ring = &skge->rx_ring;
907 struct skge_element *e;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400908
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700909 e = ring->start;
910 do {
Stephen Hemminger383181a2005-09-19 15:37:16 -0700911 struct sk_buff *skb;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400912
Stephen Hemmingerc54f9762006-09-01 15:53:47 -0700913 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
914 GFP_KERNEL);
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700915 if (!skb)
916 return -ENOMEM;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400917
Stephen Hemminger383181a2005-09-19 15:37:16 -0700918 skb_reserve(skb, NET_IP_ALIGN);
919 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
Stephen Hemminger19a33d42005-06-27 11:33:15 -0700920 } while ( (e = e->next) != ring->start);
921
922 ring->to_clean = ring->start;
923 return 0;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400924}
925
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -0700926static const char *skge_pause(enum pause_status status)
927{
928 switch(status) {
929 case FLOW_STAT_NONE:
930 return "none";
931 case FLOW_STAT_REM_SEND:
932 return "rx only";
933 case FLOW_STAT_LOC_SEND:
934 return "tx_only";
935 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
936 return "both";
937 default:
938 return "indeterminated";
939 }
940}
941
942
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400943static void skge_link_up(struct skge_port *skge)
944{
Stephen Hemminger46a60f22005-09-09 12:54:56 -0700945 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
Stephen Hemminger54cfb5a2005-08-16 14:01:05 -0700946 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
947
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400948 netif_carrier_on(skge->netdev);
Stephen Hemminger29b4e882006-03-23 11:07:28 -0800949 netif_wake_queue(skge->netdev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400950
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -0700951 if (netif_msg_link(skge)) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400952 printk(KERN_INFO PFX
953 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
954 skge->netdev->name, skge->speed,
955 skge->duplex == DUPLEX_FULL ? "full" : "half",
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -0700956 skge_pause(skge->flow_status));
957 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400958}
959
960static void skge_link_down(struct skge_port *skge)
961{
Stephen Hemminger54cfb5a2005-08-16 14:01:05 -0700962 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400963 netif_carrier_off(skge->netdev);
964 netif_stop_queue(skge->netdev);
965
966 if (netif_msg_link(skge))
967 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
968}
969
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -0700970
971static void xm_link_down(struct skge_hw *hw, int port)
972{
973 struct net_device *dev = hw->dev[port];
974 struct skge_port *skge = netdev_priv(dev);
975 u16 cmd, msk;
976
977 if (hw->phy_type == SK_PHY_XMAC) {
978 msk = xm_read16(hw, port, XM_IMSK);
979 msk |= XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND;
980 xm_write16(hw, port, XM_IMSK, msk);
981 }
982
983 cmd = xm_read16(hw, port, XM_MMU_CMD);
984 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
985 xm_write16(hw, port, XM_MMU_CMD, cmd);
986 /* dummy read to ensure writing */
987 (void) xm_read16(hw, port, XM_MMU_CMD);
988
989 if (netif_carrier_ok(dev))
990 skge_link_down(skge);
991}
992
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -0800993static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400994{
995 int i;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400996
Stephen Hemminger6b0c1482005-06-27 11:33:04 -0700997 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
Stephen Hemminger07811912006-02-22 10:28:34 -0800998 *val = xm_read16(hw, port, XM_PHY_DATA);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -0400999
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001000 if (hw->phy_type == SK_PHY_XMAC)
1001 goto ready;
1002
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001003 for (i = 0; i < PHY_RETRIES; i++) {
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001004 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001005 goto ready;
Stephen Hemminger07811912006-02-22 10:28:34 -08001006 udelay(1);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001007 }
1008
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001009 return -ETIMEDOUT;
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001010 ready:
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001011 *val = xm_read16(hw, port, XM_PHY_DATA);
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001012
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001013 return 0;
1014}
1015
1016static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1017{
1018 u16 v = 0;
1019 if (__xm_phy_read(hw, port, reg, &v))
1020 printk(KERN_WARNING PFX "%s: phy read timed out\n",
1021 hw->dev[port]->name);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001022 return v;
1023}
1024
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001025static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001026{
1027 int i;
1028
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001029 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001030 for (i = 0; i < PHY_RETRIES; i++) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001031 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001032 goto ready;
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001033 udelay(1);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001034 }
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001035 return -EIO;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001036
1037 ready:
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001038 xm_write16(hw, port, XM_PHY_DATA, val);
Stephen Hemminger07811912006-02-22 10:28:34 -08001039 for (i = 0; i < PHY_RETRIES; i++) {
1040 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1041 return 0;
1042 udelay(1);
1043 }
1044 return -ETIMEDOUT;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001045}
1046
1047static void genesis_init(struct skge_hw *hw)
1048{
1049 /* set blink source counter */
1050 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1051 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1052
1053 /* configure mac arbiter */
1054 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1055
1056 /* configure mac arbiter timeout values */
1057 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1058 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1059 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1060 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1061
1062 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1063 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1064 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1065 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1066
1067 /* configure packet arbiter timeout */
1068 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1069 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1070 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1071 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1072 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1073}
1074
1075static void genesis_reset(struct skge_hw *hw, int port)
1076{
Stephen Hemminger45bada62005-06-27 11:33:12 -07001077 const u8 zero[8] = { 0 };
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001078
Stephen Hemminger46a60f22005-09-09 12:54:56 -07001079 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1080
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001081 /* reset the statistics module */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001082 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1083 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
1084 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1085 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1086 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001087
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001088 /* disable Broadcom PHY IRQ */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001089 if (hw->phy_type == SK_PHY_BCOM)
1090 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001091
Stephen Hemminger45bada62005-06-27 11:33:12 -07001092 xm_outhash(hw, port, XM_HSM, zero);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001093}
1094
1095
Stephen Hemminger45bada62005-06-27 11:33:12 -07001096/* Convert mode to MII values */
1097static const u16 phy_pause_map[] = {
1098 [FLOW_MODE_NONE] = 0,
1099 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1100 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001101 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
Stephen Hemminger45bada62005-06-27 11:33:12 -07001102};
1103
Stephen Hemminger4b67be92006-10-05 15:49:51 -07001104/* special defines for FIBER (88E1011S only) */
1105static const u16 fiber_pause_map[] = {
1106 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1107 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1108 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001109 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
Stephen Hemminger4b67be92006-10-05 15:49:51 -07001110};
1111
Stephen Hemminger45bada62005-06-27 11:33:12 -07001112
1113/* Check status of Broadcom phy link */
1114static void bcom_check_link(struct skge_hw *hw, int port)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001115{
Stephen Hemminger45bada62005-06-27 11:33:12 -07001116 struct net_device *dev = hw->dev[port];
1117 struct skge_port *skge = netdev_priv(dev);
1118 u16 status;
1119
1120 /* read twice because of latch */
1121 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1122 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1123
Stephen Hemminger45bada62005-06-27 11:33:12 -07001124 if ((status & PHY_ST_LSYNC) == 0) {
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001125 xm_link_down(hw, port);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001126 return;
1127 }
Stephen Hemminger45bada62005-06-27 11:33:12 -07001128
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001129 if (skge->autoneg == AUTONEG_ENABLE) {
1130 u16 lpa, aux;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001131
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001132 if (!(status & PHY_ST_AN_OVER))
1133 return;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001134
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001135 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1136 if (lpa & PHY_B_AN_RF) {
1137 printk(KERN_NOTICE PFX "%s: remote fault\n",
1138 dev->name);
1139 return;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001140 }
1141
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001142 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1143
1144 /* Check Duplex mismatch */
1145 switch (aux & PHY_B_AS_AN_RES_MSK) {
1146 case PHY_B_RES_1000FD:
1147 skge->duplex = DUPLEX_FULL;
1148 break;
1149 case PHY_B_RES_1000HD:
1150 skge->duplex = DUPLEX_HALF;
1151 break;
1152 default:
1153 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1154 dev->name);
1155 return;
1156 }
1157
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001158 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1159 switch (aux & PHY_B_AS_PAUSE_MSK) {
1160 case PHY_B_AS_PAUSE_MSK:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001161 skge->flow_status = FLOW_STAT_SYMMETRIC;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001162 break;
1163 case PHY_B_AS_PRR:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001164 skge->flow_status = FLOW_STAT_REM_SEND;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001165 break;
1166 case PHY_B_AS_PRT:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001167 skge->flow_status = FLOW_STAT_LOC_SEND;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001168 break;
1169 default:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001170 skge->flow_status = FLOW_STAT_NONE;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001171 }
1172 skge->speed = SPEED_1000;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001173 }
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001174
1175 if (!netif_carrier_ok(dev))
1176 genesis_link_up(skge);
Stephen Hemminger45bada62005-06-27 11:33:12 -07001177}
1178
1179/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1180 * Phy on for 100 or 10Mbit operation
1181 */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001182static void bcom_phy_init(struct skge_port *skge)
Stephen Hemminger45bada62005-06-27 11:33:12 -07001183{
1184 struct skge_hw *hw = skge->hw;
1185 int port = skge->port;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001186 int i;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001187 u16 id1, r, ext, ctl;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001188
1189 /* magic workaround patterns for Broadcom */
1190 static const struct {
1191 u16 reg;
1192 u16 val;
1193 } A1hack[] = {
1194 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1195 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1196 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1197 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1198 }, C0hack[] = {
1199 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1200 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1201 };
1202
Stephen Hemminger45bada62005-06-27 11:33:12 -07001203 /* read Id from external PHY (all have the same address) */
1204 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1205
1206 /* Optimize MDIO transfer by suppressing preamble. */
1207 r = xm_read16(hw, port, XM_MMU_CMD);
1208 r |= XM_MMU_NO_PRE;
1209 xm_write16(hw, port, XM_MMU_CMD,r);
1210
Stephen Hemminger2c668512005-07-22 16:26:07 -07001211 switch (id1) {
Stephen Hemminger45bada62005-06-27 11:33:12 -07001212 case PHY_BCOM_ID1_C0:
1213 /*
1214 * Workaround BCOM Errata for the C0 type.
1215 * Write magic patterns to reserved registers.
1216 */
1217 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1218 xm_phy_write(hw, port,
1219 C0hack[i].reg, C0hack[i].val);
1220
1221 break;
1222 case PHY_BCOM_ID1_A1:
1223 /*
1224 * Workaround BCOM Errata for the A1 type.
1225 * Write magic patterns to reserved registers.
1226 */
1227 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1228 xm_phy_write(hw, port,
1229 A1hack[i].reg, A1hack[i].val);
1230 break;
1231 }
1232
1233 /*
1234 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1235 * Disable Power Management after reset.
1236 */
1237 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1238 r |= PHY_B_AC_DIS_PM;
1239 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1240
1241 /* Dummy read */
1242 xm_read16(hw, port, XM_ISRC);
1243
1244 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1245 ctl = PHY_CT_SP1000; /* always 1000mbit */
1246
1247 if (skge->autoneg == AUTONEG_ENABLE) {
1248 /*
1249 * Workaround BCOM Errata #1 for the C5 type.
1250 * 1000Base-T Link Acquisition Failure in Slave Mode
1251 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1252 */
1253 u16 adv = PHY_B_1000C_RD;
1254 if (skge->advertising & ADVERTISED_1000baseT_Half)
1255 adv |= PHY_B_1000C_AHD;
1256 if (skge->advertising & ADVERTISED_1000baseT_Full)
1257 adv |= PHY_B_1000C_AFD;
1258 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1259
1260 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1261 } else {
1262 if (skge->duplex == DUPLEX_FULL)
1263 ctl |= PHY_CT_DUP_MD;
1264 /* Force to slave */
1265 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1266 }
1267
1268 /* Set autonegotiation pause parameters */
1269 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1270 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1271
1272 /* Handle Jumbo frames */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001273 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
Stephen Hemminger45bada62005-06-27 11:33:12 -07001274 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1275 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1276
1277 ext |= PHY_B_PEC_HIGH_LA;
1278
1279 }
1280
1281 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1282 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1283
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08001284 /* Use link status change interrupt */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001285 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001286}
Stephen Hemminger45bada62005-06-27 11:33:12 -07001287
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001288static void xm_phy_init(struct skge_port *skge)
1289{
1290 struct skge_hw *hw = skge->hw;
1291 int port = skge->port;
1292 u16 ctrl = 0;
1293
1294 if (skge->autoneg == AUTONEG_ENABLE) {
1295 if (skge->advertising & ADVERTISED_1000baseT_Half)
1296 ctrl |= PHY_X_AN_HD;
1297 if (skge->advertising & ADVERTISED_1000baseT_Full)
1298 ctrl |= PHY_X_AN_FD;
1299
Stephen Hemminger4b67be92006-10-05 15:49:51 -07001300 ctrl |= fiber_pause_map[skge->flow_control];
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001301
1302 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1303
1304 /* Restart Auto-negotiation */
1305 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1306 } else {
1307 /* Set DuplexMode in Config register */
1308 if (skge->duplex == DUPLEX_FULL)
1309 ctrl |= PHY_CT_DUP_MD;
1310 /*
1311 * Do NOT enable Auto-negotiation here. This would hold
1312 * the link down because no IDLEs are transmitted
1313 */
1314 }
1315
1316 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1317
1318 /* Poll PHY for status changes */
1319 schedule_delayed_work(&skge->link_thread, LINK_HZ);
1320}
1321
1322static void xm_check_link(struct net_device *dev)
1323{
1324 struct skge_port *skge = netdev_priv(dev);
1325 struct skge_hw *hw = skge->hw;
1326 int port = skge->port;
1327 u16 status;
1328
1329 /* read twice because of latch */
1330 (void) xm_phy_read(hw, port, PHY_XMAC_STAT);
1331 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1332
1333 if ((status & PHY_ST_LSYNC) == 0) {
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001334 xm_link_down(hw, port);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001335 return;
1336 }
1337
1338 if (skge->autoneg == AUTONEG_ENABLE) {
1339 u16 lpa, res;
1340
1341 if (!(status & PHY_ST_AN_OVER))
1342 return;
1343
1344 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1345 if (lpa & PHY_B_AN_RF) {
1346 printk(KERN_NOTICE PFX "%s: remote fault\n",
1347 dev->name);
1348 return;
1349 }
1350
1351 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1352
1353 /* Check Duplex mismatch */
1354 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1355 case PHY_X_RS_FD:
1356 skge->duplex = DUPLEX_FULL;
1357 break;
1358 case PHY_X_RS_HD:
1359 skge->duplex = DUPLEX_HALF;
1360 break;
1361 default:
1362 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1363 dev->name);
1364 return;
1365 }
1366
1367 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001368 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1369 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1370 (lpa & PHY_X_P_SYM_MD))
1371 skge->flow_status = FLOW_STAT_SYMMETRIC;
1372 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1373 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1374 /* Enable PAUSE receive, disable PAUSE transmit */
1375 skge->flow_status = FLOW_STAT_REM_SEND;
1376 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1377 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1378 /* Disable PAUSE receive, enable PAUSE transmit */
1379 skge->flow_status = FLOW_STAT_LOC_SEND;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001380 else
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001381 skge->flow_status = FLOW_STAT_NONE;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001382
1383 skge->speed = SPEED_1000;
1384 }
1385
1386 if (!netif_carrier_ok(dev))
1387 genesis_link_up(skge);
1388}
1389
1390/* Poll to check for link coming up.
1391 * Since internal PHY is wired to a level triggered pin, can't
1392 * get an interrupt when carrier is detected.
1393 */
David Howellsc4028952006-11-22 14:57:56 +00001394static void xm_link_timer(struct work_struct *work)
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001395{
David Howellsc4028952006-11-22 14:57:56 +00001396 struct skge_port *skge =
1397 container_of(work, struct skge_port, link_thread.work);
1398 struct net_device *dev = skge->netdev;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001399 struct skge_hw *hw = skge->hw;
1400 int port = skge->port;
1401
1402 if (!netif_running(dev))
1403 return;
1404
1405 if (netif_carrier_ok(dev)) {
1406 xm_read16(hw, port, XM_ISRC);
1407 if (!(xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS))
1408 goto nochange;
1409 } else {
1410 if (xm_read32(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1411 goto nochange;
1412 xm_read16(hw, port, XM_ISRC);
1413 if (xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
1414 goto nochange;
1415 }
1416
1417 mutex_lock(&hw->phy_mutex);
1418 xm_check_link(dev);
1419 mutex_unlock(&hw->phy_mutex);
1420
1421nochange:
Stephen Hemminger208491d82007-02-16 15:37:39 -08001422 if (netif_running(dev))
1423 schedule_delayed_work(&skge->link_thread, LINK_HZ);
Stephen Hemminger45bada62005-06-27 11:33:12 -07001424}
1425
1426static void genesis_mac_init(struct skge_hw *hw, int port)
1427{
1428 struct net_device *dev = hw->dev[port];
1429 struct skge_port *skge = netdev_priv(dev);
1430 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1431 int i;
1432 u32 r;
1433 const u8 zero[6] = { 0 };
1434
Stephen Hemminger07811912006-02-22 10:28:34 -08001435 for (i = 0; i < 10; i++) {
1436 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1437 MFF_SET_MAC_RST);
1438 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1439 goto reset_ok;
1440 udelay(1);
1441 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001442
Stephen Hemminger07811912006-02-22 10:28:34 -08001443 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1444
1445 reset_ok:
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001446 /* Unreset the XMAC. */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001447 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001448
1449 /*
1450 * Perform additional initialization for external PHYs,
1451 * namely for the 1000baseTX cards that use the XMAC's
1452 * GMII mode.
1453 */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001454 if (hw->phy_type != SK_PHY_XMAC) {
1455 /* Take external Phy out of reset */
1456 r = skge_read32(hw, B2_GP_IO);
1457 if (port == 0)
1458 r |= GP_DIR_0|GP_IO_0;
1459 else
1460 r |= GP_DIR_2|GP_IO_2;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001461
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001462 skge_write32(hw, B2_GP_IO, r);
1463
1464 /* Enable GMII interface */
1465 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1466 }
Stephen Hemminger07811912006-02-22 10:28:34 -08001467
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001468
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001469 switch(hw->phy_type) {
1470 case SK_PHY_XMAC:
1471 xm_phy_init(skge);
1472 break;
1473 case SK_PHY_BCOM:
1474 bcom_phy_init(skge);
1475 bcom_check_link(hw, port);
1476 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001477
Stephen Hemminger45bada62005-06-27 11:33:12 -07001478 /* Set Station Address */
1479 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001480
Stephen Hemminger45bada62005-06-27 11:33:12 -07001481 /* We don't use match addresses so clear */
1482 for (i = 1; i < 16; i++)
1483 xm_outaddr(hw, port, XM_EXM(i), zero);
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001484
Stephen Hemminger07811912006-02-22 10:28:34 -08001485 /* Clear MIB counters */
1486 xm_write16(hw, port, XM_STAT_CMD,
1487 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1488 /* Clear two times according to Errata #3 */
1489 xm_write16(hw, port, XM_STAT_CMD,
1490 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1491
Stephen Hemminger45bada62005-06-27 11:33:12 -07001492 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1493 xm_write16(hw, port, XM_RX_HI_WM, 1450);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001494
1495 /* We don't need the FCS appended to the packet. */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001496 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1497 if (jumbo)
1498 r |= XM_RX_BIG_PK_OK;
1499
1500 if (skge->duplex == DUPLEX_HALF) {
1501 /*
1502 * If in manual half duplex mode the other side might be in
1503 * full duplex mode, so ignore if a carrier extension is not seen
1504 * on frames received
1505 */
1506 r |= XM_RX_DIS_CEXT;
1507 }
1508 xm_write16(hw, port, XM_RX_CMD, r);
1509
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001510
1511 /* We want short frames padded to 60 bytes. */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001512 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1513
1514 /*
1515 * Bump up the transmit threshold. This helps hold off transmit
1516 * underruns when we're blasting traffic from both ports at once.
1517 */
1518 xm_write16(hw, port, XM_TX_THR, 512);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001519
1520 /*
1521 * Enable the reception of all error frames. This is is
1522 * a necessary evil due to the design of the XMAC. The
1523 * XMAC's receive FIFO is only 8K in size, however jumbo
1524 * frames can be up to 9000 bytes in length. When bad
1525 * frame filtering is enabled, the XMAC's RX FIFO operates
1526 * in 'store and forward' mode. For this to work, the
1527 * entire frame has to fit into the FIFO, but that means
1528 * that jumbo frames larger than 8192 bytes will be
1529 * truncated. Disabling all bad frame filtering causes
1530 * the RX FIFO to operate in streaming mode, in which
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08001531 * case the XMAC will start transferring frames out of the
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001532 * RX FIFO as soon as the FIFO threshold is reached.
1533 */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001534 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001535
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001536
1537 /*
Stephen Hemminger45bada62005-06-27 11:33:12 -07001538 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1539 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1540 * and 'Octets Rx OK Hi Cnt Ov'.
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001541 */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001542 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1543
1544 /*
1545 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1546 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1547 * and 'Octets Tx OK Hi Cnt Ov'.
1548 */
1549 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001550
1551 /* Configure MAC arbiter */
1552 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1553
1554 /* configure timeout values */
1555 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1556 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1557 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1558 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1559
1560 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1561 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1562 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1563 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1564
1565 /* Configure Rx MAC FIFO */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001566 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1567 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1568 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001569
1570 /* Configure Tx MAC FIFO */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001571 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1572 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1573 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001574
Stephen Hemminger45bada62005-06-27 11:33:12 -07001575 if (jumbo) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001576 /* Enable frame flushing if jumbo frames used */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001577 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001578 } else {
1579 /* enable timeout timers if normal frames */
1580 skge_write16(hw, B3_PA_CTRL,
Stephen Hemminger45bada62005-06-27 11:33:12 -07001581 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001582 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001583}
1584
1585static void genesis_stop(struct skge_port *skge)
1586{
1587 struct skge_hw *hw = skge->hw;
1588 int port = skge->port;
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001589 u32 reg;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001590
Stephen Hemminger46a60f22005-09-09 12:54:56 -07001591 genesis_reset(hw, port);
1592
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001593 /* Clear Tx packet arbiter timeout IRQ */
1594 skge_write16(hw, B3_PA_CTRL,
1595 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1596
1597 /*
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08001598 * If the transfer sticks at the MAC the STOP command will not
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001599 * terminate if we don't flush the XMAC's transmit FIFO !
1600 */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001601 xm_write32(hw, port, XM_MODE,
1602 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001603
1604
1605 /* Reset the MAC */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001606 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001607
1608 /* For external PHYs there must be special handling */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001609 if (hw->phy_type != SK_PHY_XMAC) {
1610 reg = skge_read32(hw, B2_GP_IO);
1611 if (port == 0) {
1612 reg |= GP_DIR_0;
1613 reg &= ~GP_IO_0;
1614 } else {
1615 reg |= GP_DIR_2;
1616 reg &= ~GP_IO_2;
1617 }
1618 skge_write32(hw, B2_GP_IO, reg);
1619 skge_read32(hw, B2_GP_IO);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001620 }
1621
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001622 xm_write16(hw, port, XM_MMU_CMD,
1623 xm_read16(hw, port, XM_MMU_CMD)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001624 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1625
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001626 xm_read16(hw, port, XM_MMU_CMD);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001627}
1628
1629
1630static void genesis_get_stats(struct skge_port *skge, u64 *data)
1631{
1632 struct skge_hw *hw = skge->hw;
1633 int port = skge->port;
1634 int i;
1635 unsigned long timeout = jiffies + HZ;
1636
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001637 xm_write16(hw, port,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001638 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1639
1640 /* wait for update to complete */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001641 while (xm_read16(hw, port, XM_STAT_CMD)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001642 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1643 if (time_after(jiffies, timeout))
1644 break;
1645 udelay(10);
1646 }
1647
1648 /* special case for 64 bit octet counter */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001649 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1650 | xm_read32(hw, port, XM_TXO_OK_LO);
1651 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1652 | xm_read32(hw, port, XM_RXO_OK_LO);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001653
1654 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001655 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001656}
1657
1658static void genesis_mac_intr(struct skge_hw *hw, int port)
1659{
1660 struct skge_port *skge = netdev_priv(hw->dev[port]);
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001661 u16 status = xm_read16(hw, port, XM_ISRC);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001662
Stephen Hemminger7e676d92005-06-27 11:33:13 -07001663 if (netif_msg_intr(skge))
1664 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1665 skge->netdev->name, status);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001666
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001667 if (hw->phy_type == SK_PHY_XMAC &&
1668 (status & (XM_IS_INP_ASS | XM_IS_LIPA_RC)))
1669 xm_link_down(hw, port);
1670
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001671 if (status & XM_IS_TXF_UR) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001672 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001673 ++skge->net_stats.tx_fifo_errors;
1674 }
1675 if (status & XM_IS_RXF_OV) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001676 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001677 ++skge->net_stats.rx_fifo_errors;
1678 }
1679}
1680
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001681static void genesis_link_up(struct skge_port *skge)
1682{
1683 struct skge_hw *hw = skge->hw;
1684 int port = skge->port;
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001685 u16 cmd, msk;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001686 u32 mode;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001687
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001688 cmd = xm_read16(hw, port, XM_MMU_CMD);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001689
1690 /*
1691 * enabling pause frame reception is required for 1000BT
1692 * because the XMAC is not reset if the link is going down
1693 */
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001694 if (skge->flow_status == FLOW_STAT_NONE ||
1695 skge->flow_status == FLOW_STAT_LOC_SEND)
Stephen Hemminger7e676d92005-06-27 11:33:13 -07001696 /* Disable Pause Frame Reception */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001697 cmd |= XM_MMU_IGN_PF;
1698 else
1699 /* Enable Pause Frame Reception */
1700 cmd &= ~XM_MMU_IGN_PF;
1701
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001702 xm_write16(hw, port, XM_MMU_CMD, cmd);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001703
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001704 mode = xm_read32(hw, port, XM_MODE);
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07001705 if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
1706 skge->flow_status == FLOW_STAT_LOC_SEND) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001707 /*
1708 * Configure Pause Frame Generation
1709 * Use internal and external Pause Frame Generation.
1710 * Sending pause frames is edge triggered.
1711 * Send a Pause frame with the maximum pause time if
1712 * internal oder external FIFO full condition occurs.
1713 * Send a zero pause time frame to re-start transmission.
1714 */
1715 /* XM_PAUSE_DA = '010000C28001' (default) */
1716 /* XM_MAC_PTIME = 0xffff (maximum) */
1717 /* remember this value is defined in big endian (!) */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001718 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001719
1720 mode |= XM_PAUSE_MODE;
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001721 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001722 } else {
1723 /*
1724 * disable pause frame generation is required for 1000BT
1725 * because the XMAC is not reset if the link is going down
1726 */
1727 /* Disable Pause Mode in Mode Register */
1728 mode &= ~XM_PAUSE_MODE;
1729
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001730 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001731 }
1732
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001733 xm_write32(hw, port, XM_MODE, mode);
Stephen Hemmingera1bc9b82006-10-05 15:49:50 -07001734 msk = XM_DEF_MSK;
1735 if (hw->phy_type != SK_PHY_XMAC)
1736 msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */
1737
1738 xm_write16(hw, port, XM_IMSK, msk);
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001739 xm_read16(hw, port, XM_ISRC);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001740
1741 /* get MMU Command Reg. */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001742 cmd = xm_read16(hw, port, XM_MMU_CMD);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001743 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001744 cmd |= XM_MMU_GMII_FD;
1745
Stephen Hemminger89bf5f22005-06-27 11:33:10 -07001746 /*
1747 * Workaround BCOM Errata (#10523) for all BCom Phys
1748 * Enable Power Management after link up
1749 */
Stephen Hemminger64f6b642006-09-23 21:25:28 -07001750 if (hw->phy_type == SK_PHY_BCOM) {
1751 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1752 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1753 & ~PHY_B_AC_DIS_PM);
1754 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1755 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001756
1757 /* enable Rx/Tx */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001758 xm_write16(hw, port, XM_MMU_CMD,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001759 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1760 skge_link_up(skge);
1761}
1762
1763
Stephen Hemminger45bada62005-06-27 11:33:12 -07001764static inline void bcom_phy_intr(struct skge_port *skge)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001765{
1766 struct skge_hw *hw = skge->hw;
1767 int port = skge->port;
Stephen Hemminger45bada62005-06-27 11:33:12 -07001768 u16 isrc;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001769
Stephen Hemminger45bada62005-06-27 11:33:12 -07001770 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
Stephen Hemminger7e676d92005-06-27 11:33:13 -07001771 if (netif_msg_intr(skge))
1772 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1773 skge->netdev->name, isrc);
Stephen Hemminger45bada62005-06-27 11:33:12 -07001774
1775 if (isrc & PHY_B_IS_PSE)
1776 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1777 hw->dev[port]->name);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001778
1779 /* Workaround BCom Errata:
1780 * enable and disable loopback mode if "NO HCD" occurs.
1781 */
Stephen Hemminger45bada62005-06-27 11:33:12 -07001782 if (isrc & PHY_B_IS_NO_HDCL) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001783 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1784 xm_phy_write(hw, port, PHY_BCOM_CTRL,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001785 ctrl | PHY_CT_LOOP);
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001786 xm_phy_write(hw, port, PHY_BCOM_CTRL,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001787 ctrl & ~PHY_CT_LOOP);
1788 }
1789
Stephen Hemminger45bada62005-06-27 11:33:12 -07001790 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1791 bcom_check_link(hw, port);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001792
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001793}
1794
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08001795static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1796{
1797 int i;
1798
1799 gma_write16(hw, port, GM_SMI_DATA, val);
1800 gma_write16(hw, port, GM_SMI_CTRL,
1801 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1802 for (i = 0; i < PHY_RETRIES; i++) {
1803 udelay(1);
1804
1805 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1806 return 0;
1807 }
1808
1809 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1810 hw->dev[port]->name);
1811 return -EIO;
1812}
1813
1814static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1815{
1816 int i;
1817
1818 gma_write16(hw, port, GM_SMI_CTRL,
1819 GM_SMI_CT_PHY_AD(hw->phy_addr)
1820 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1821
1822 for (i = 0; i < PHY_RETRIES; i++) {
1823 udelay(1);
1824 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1825 goto ready;
1826 }
1827
1828 return -ETIMEDOUT;
1829 ready:
1830 *val = gma_read16(hw, port, GM_SMI_DATA);
1831 return 0;
1832}
1833
1834static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1835{
1836 u16 v = 0;
1837 if (__gm_phy_read(hw, port, reg, &v))
1838 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1839 hw->dev[port]->name);
1840 return v;
1841}
1842
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08001843/* Marvell Phy Initialization */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001844static void yukon_init(struct skge_hw *hw, int port)
1845{
1846 struct skge_port *skge = netdev_priv(hw->dev[port]);
1847 u16 ctrl, ct1000, adv;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001848
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001849 if (skge->autoneg == AUTONEG_ENABLE) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001850 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001851
1852 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1853 PHY_M_EC_MAC_S_MSK);
1854 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1855
Stephen Hemmingerc506a502005-06-27 11:33:09 -07001856 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001857
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001858 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001859 }
1860
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001861 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001862 if (skge->autoneg == AUTONEG_DISABLE)
1863 ctrl &= ~PHY_CT_ANE;
1864
1865 ctrl |= PHY_CT_RESET;
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001866 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001867
1868 ctrl = 0;
1869 ct1000 = 0;
Stephen Hemmingerb18f2092005-06-27 11:33:08 -07001870 adv = PHY_AN_CSMA;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001871
1872 if (skge->autoneg == AUTONEG_ENABLE) {
Stephen Hemminger5e1705d2005-08-16 14:00:58 -07001873 if (hw->copper) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001874 if (skge->advertising & ADVERTISED_1000baseT_Full)
1875 ct1000 |= PHY_M_1000C_AFD;
1876 if (skge->advertising & ADVERTISED_1000baseT_Half)
1877 ct1000 |= PHY_M_1000C_AHD;
1878 if (skge->advertising & ADVERTISED_100baseT_Full)
1879 adv |= PHY_M_AN_100_FD;
1880 if (skge->advertising & ADVERTISED_100baseT_Half)
1881 adv |= PHY_M_AN_100_HD;
1882 if (skge->advertising & ADVERTISED_10baseT_Full)
1883 adv |= PHY_M_AN_10_FD;
1884 if (skge->advertising & ADVERTISED_10baseT_Half)
1885 adv |= PHY_M_AN_10_HD;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001886
Stephen Hemminger4b67be92006-10-05 15:49:51 -07001887 /* Set Flow-control capabilities */
1888 adv |= phy_pause_map[skge->flow_control];
1889 } else {
1890 if (skge->advertising & ADVERTISED_1000baseT_Full)
1891 adv |= PHY_M_AN_1000X_AFD;
1892 if (skge->advertising & ADVERTISED_1000baseT_Half)
1893 adv |= PHY_M_AN_1000X_AHD;
1894
1895 adv |= fiber_pause_map[skge->flow_control];
1896 }
Stephen Hemminger45bada62005-06-27 11:33:12 -07001897
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001898 /* Restart Auto-negotiation */
1899 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1900 } else {
1901 /* forced speed/duplex settings */
1902 ct1000 = PHY_M_1000C_MSE;
1903
1904 if (skge->duplex == DUPLEX_FULL)
1905 ctrl |= PHY_CT_DUP_MD;
1906
1907 switch (skge->speed) {
1908 case SPEED_1000:
1909 ctrl |= PHY_CT_SP1000;
1910 break;
1911 case SPEED_100:
1912 ctrl |= PHY_CT_SP100;
1913 break;
1914 }
1915
1916 ctrl |= PHY_CT_RESET;
1917 }
1918
Stephen Hemmingerc506a502005-06-27 11:33:09 -07001919 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001920
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001921 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1922 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001923
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001924 /* Enable phy interrupt on autonegotiation complete (or link up) */
1925 if (skge->autoneg == AUTONEG_ENABLE)
Stephen Hemminger4cde06e2005-07-22 16:26:09 -07001926 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001927 else
Stephen Hemminger4cde06e2005-07-22 16:26:09 -07001928 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001929}
1930
1931static void yukon_reset(struct skge_hw *hw, int port)
1932{
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001933 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1934 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1935 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1936 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1937 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001938
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001939 gma_write16(hw, port, GM_RX_CTRL,
1940 gma_read16(hw, port, GM_RX_CTRL)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001941 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1942}
1943
Stephen Hemmingerc8868612005-09-23 09:08:30 -07001944/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1945static int is_yukon_lite_a0(struct skge_hw *hw)
1946{
1947 u32 reg;
1948 int ret;
1949
1950 if (hw->chip_id != CHIP_ID_YUKON)
1951 return 0;
1952
1953 reg = skge_read32(hw, B2_FAR);
1954 skge_write8(hw, B2_FAR + 3, 0xff);
1955 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1956 skge_write32(hw, B2_FAR, reg);
1957 return ret;
1958}
1959
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001960static void yukon_mac_init(struct skge_hw *hw, int port)
1961{
1962 struct skge_port *skge = netdev_priv(hw->dev[port]);
1963 int i;
1964 u32 reg;
1965 const u8 *addr = hw->dev[port]->dev_addr;
1966
1967 /* WA code for COMA mode -- set PHY reset */
1968 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
Stephen Hemminger46a60f22005-09-09 12:54:56 -07001969 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1970 reg = skge_read32(hw, B2_GP_IO);
1971 reg |= GP_DIR_9 | GP_IO_9;
1972 skge_write32(hw, B2_GP_IO, reg);
1973 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001974
1975 /* hard reset */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001976 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1977 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001978
1979 /* WA code for COMA mode -- clear PHY reset */
1980 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
Stephen Hemminger46a60f22005-09-09 12:54:56 -07001981 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1982 reg = skge_read32(hw, B2_GP_IO);
1983 reg |= GP_DIR_9;
1984 reg &= ~GP_IO_9;
1985 skge_write32(hw, B2_GP_IO, reg);
1986 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001987
1988 /* Set hardware config mode */
1989 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1990 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
Stephen Hemminger5e1705d2005-08-16 14:00:58 -07001991 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001992
1993 /* Clear GMC reset */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07001994 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1995 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1996 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08001997
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04001998 if (skge->autoneg == AUTONEG_DISABLE) {
1999 reg = GM_GPCR_AU_ALL_DIS;
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002000 gma_write16(hw, port, GM_GP_CTRL,
2001 gma_read16(hw, port, GM_GP_CTRL) | reg);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002002
2003 switch (skge->speed) {
2004 case SPEED_1000:
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08002005 reg &= ~GM_GPCR_SPEED_100;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002006 reg |= GM_GPCR_SPEED_1000;
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08002007 break;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002008 case SPEED_100:
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08002009 reg &= ~GM_GPCR_SPEED_1000;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002010 reg |= GM_GPCR_SPEED_100;
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08002011 break;
2012 case SPEED_10:
2013 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2014 break;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002015 }
2016
2017 if (skge->duplex == DUPLEX_FULL)
2018 reg |= GM_GPCR_DUP_FULL;
2019 } else
2020 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
Stephen Hemminger564f9ab2006-02-13 15:46:48 -08002021
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002022 switch (skge->flow_control) {
2023 case FLOW_MODE_NONE:
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002024 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002025 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2026 break;
2027 case FLOW_MODE_LOC_SEND:
2028 /* disable Rx flow-control */
2029 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002030 break;
2031 case FLOW_MODE_SYMMETRIC:
2032 case FLOW_MODE_SYM_OR_REM:
2033 /* enable Tx & Rx flow-control */
2034 break;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002035 }
2036
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002037 gma_write16(hw, port, GM_GP_CTRL, reg);
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002038 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002039
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002040 yukon_init(hw, port);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002041
2042 /* MIB clear */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002043 reg = gma_read16(hw, port, GM_PHY_ADDR);
2044 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002045
2046 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002047 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2048 gma_write16(hw, port, GM_PHY_ADDR, reg);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002049
2050 /* transmit control */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002051 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002052
2053 /* receive control reg: unicast + multicast + no FCS */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002054 gma_write16(hw, port, GM_RX_CTRL,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002055 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2056
2057 /* transmit flow control */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002058 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002059
2060 /* transmit parameter */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002061 gma_write16(hw, port, GM_TX_PARAM,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002062 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2063 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2064 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2065
2066 /* serial mode register */
2067 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2068 if (hw->dev[port]->mtu > 1500)
2069 reg |= GM_SMOD_JUMBO_ENA;
2070
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002071 gma_write16(hw, port, GM_SERIAL_MODE, reg);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002072
2073 /* physical address: used for pause frames */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002074 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002075 /* virtual address for data */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002076 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002077
2078 /* enable interrupt mask for counter overflows */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002079 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2080 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2081 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002082
2083 /* Initialize Mac Fifo */
2084
2085 /* Configure Rx MAC FIFO */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002086 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002087 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
Stephen Hemmingerc8868612005-09-23 09:08:30 -07002088
2089 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2090 if (is_yukon_lite_a0(hw))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002091 reg &= ~GMF_RX_F_FL_ON;
Stephen Hemmingerc8868612005-09-23 09:08:30 -07002092
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002093 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2094 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
Stephen Hemmingerc5923082005-08-16 14:01:02 -07002095 /*
2096 * because Pause Packet Truncation in GMAC is not working
2097 * we have to increase the Flush Threshold to 64 bytes
2098 * in order to flush pause packets in Rx FIFO on Yukon-1
2099 */
2100 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002101
2102 /* Configure Tx MAC FIFO */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002103 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2104 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002105}
2106
Stephen Hemminger355ec572005-11-08 10:33:43 -08002107/* Go into power down mode */
2108static void yukon_suspend(struct skge_hw *hw, int port)
2109{
2110 u16 ctrl;
2111
2112 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2113 ctrl |= PHY_M_PC_POL_R_DIS;
2114 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2115
2116 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2117 ctrl |= PHY_CT_RESET;
2118 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2119
2120 /* switch IEEE compatible power down mode on */
2121 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2122 ctrl |= PHY_CT_PDOWN;
2123 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2124}
2125
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002126static void yukon_stop(struct skge_port *skge)
2127{
2128 struct skge_hw *hw = skge->hw;
2129 int port = skge->port;
2130
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002131 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2132 yukon_reset(hw, port);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002133
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002134 gma_write16(hw, port, GM_GP_CTRL,
2135 gma_read16(hw, port, GM_GP_CTRL)
Stephen Hemminger0eedf4a2005-07-22 16:26:04 -07002136 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002137 gma_read16(hw, port, GM_GP_CTRL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002138
Stephen Hemminger355ec572005-11-08 10:33:43 -08002139 yukon_suspend(hw, port);
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002140
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002141 /* set GPHY Control reset */
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002142 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2143 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002144}
2145
2146static void yukon_get_stats(struct skge_port *skge, u64 *data)
2147{
2148 struct skge_hw *hw = skge->hw;
2149 int port = skge->port;
2150 int i;
2151
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002152 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2153 | gma_read32(hw, port, GM_TXO_OK_LO);
2154 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2155 | gma_read32(hw, port, GM_RXO_OK_LO);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002156
2157 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002158 data[i] = gma_read32(hw, port,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002159 skge_stats[i].gma_offset);
2160}
2161
2162static void yukon_mac_intr(struct skge_hw *hw, int port)
2163{
Stephen Hemminger7e676d92005-06-27 11:33:13 -07002164 struct net_device *dev = hw->dev[port];
2165 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002166 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002167
Stephen Hemminger7e676d92005-06-27 11:33:13 -07002168 if (netif_msg_intr(skge))
2169 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
2170 dev->name, status);
2171
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002172 if (status & GM_IS_RX_FF_OR) {
2173 ++skge->net_stats.rx_fifo_errors;
Stephen Hemmingerd8a09942005-07-22 16:26:08 -07002174 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002175 }
Stephen Hemmingerd8a09942005-07-22 16:26:08 -07002176
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002177 if (status & GM_IS_TX_FF_UR) {
2178 ++skge->net_stats.tx_fifo_errors;
Stephen Hemmingerd8a09942005-07-22 16:26:08 -07002179 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002180 }
2181
2182}
2183
2184static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2185{
Stephen Hemminger95566062005-06-27 11:33:02 -07002186 switch (aux & PHY_M_PS_SPEED_MSK) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002187 case PHY_M_PS_SPEED_1000:
2188 return SPEED_1000;
2189 case PHY_M_PS_SPEED_100:
2190 return SPEED_100;
2191 default:
2192 return SPEED_10;
2193 }
2194}
2195
2196static void yukon_link_up(struct skge_port *skge)
2197{
2198 struct skge_hw *hw = skge->hw;
2199 int port = skge->port;
2200 u16 reg;
2201
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002202 /* Enable Transmit FIFO Underrun */
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002203 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002204
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002205 reg = gma_read16(hw, port, GM_GP_CTRL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002206 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2207 reg |= GM_GPCR_DUP_FULL;
2208
2209 /* enable Rx/Tx */
2210 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002211 gma_write16(hw, port, GM_GP_CTRL, reg);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002212
Stephen Hemminger4cde06e2005-07-22 16:26:09 -07002213 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002214 skge_link_up(skge);
2215}
2216
2217static void yukon_link_down(struct skge_port *skge)
2218{
2219 struct skge_hw *hw = skge->hw;
2220 int port = skge->port;
Stephen Hemmingerd8a09942005-07-22 16:26:08 -07002221 u16 ctrl;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002222
Stephen Hemmingerd8a09942005-07-22 16:26:08 -07002223 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2224 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2225 gma_write16(hw, port, GM_GP_CTRL, ctrl);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002226
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002227 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2228 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2229 ctrl |= PHY_M_AN_ASP;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002230 /* restore Asymmetric Pause bit */
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002231 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002232 }
2233
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002234 skge_link_down(skge);
2235
2236 yukon_init(hw, port);
2237}
2238
2239static void yukon_phy_intr(struct skge_port *skge)
2240{
2241 struct skge_hw *hw = skge->hw;
2242 int port = skge->port;
2243 const char *reason = NULL;
2244 u16 istatus, phystat;
2245
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002246 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2247 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
Stephen Hemminger7e676d92005-06-27 11:33:13 -07002248
2249 if (netif_msg_intr(skge))
2250 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
2251 skge->netdev->name, istatus, phystat);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002252
2253 if (istatus & PHY_M_IS_AN_COMPL) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002254 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002255 & PHY_M_AN_RF) {
2256 reason = "remote fault";
2257 goto failed;
2258 }
2259
Stephen Hemmingerc506a502005-06-27 11:33:09 -07002260 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002261 reason = "master/slave fault";
2262 goto failed;
2263 }
2264
2265 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2266 reason = "speed/duplex";
2267 goto failed;
2268 }
2269
2270 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2271 ? DUPLEX_FULL : DUPLEX_HALF;
2272 skge->speed = yukon_speed(hw, phystat);
2273
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002274 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2275 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2276 case PHY_M_PS_PAUSE_MSK:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002277 skge->flow_status = FLOW_STAT_SYMMETRIC;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002278 break;
2279 case PHY_M_PS_RX_P_EN:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002280 skge->flow_status = FLOW_STAT_REM_SEND;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002281 break;
2282 case PHY_M_PS_TX_P_EN:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002283 skge->flow_status = FLOW_STAT_LOC_SEND;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002284 break;
2285 default:
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002286 skge->flow_status = FLOW_STAT_NONE;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002287 }
2288
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07002289 if (skge->flow_status == FLOW_STAT_NONE ||
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002290 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002291 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002292 else
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002293 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002294 yukon_link_up(skge);
2295 return;
2296 }
2297
2298 if (istatus & PHY_M_IS_LSP_CHANGE)
2299 skge->speed = yukon_speed(hw, phystat);
2300
2301 if (istatus & PHY_M_IS_DUP_CHANGE)
2302 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2303 if (istatus & PHY_M_IS_LST_CHANGE) {
2304 if (phystat & PHY_M_PS_LINK_UP)
2305 yukon_link_up(skge);
2306 else
2307 yukon_link_down(skge);
2308 }
2309 return;
2310 failed:
2311 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2312 skge->netdev->name, reason);
2313
2314 /* XXX restart autonegotiation? */
2315}
2316
Stephen Hemmingeree294dc2005-12-14 15:47:44 -08002317static void skge_phy_reset(struct skge_port *skge)
2318{
2319 struct skge_hw *hw = skge->hw;
2320 int port = skge->port;
Jeff Garzikaae343d2006-12-02 07:14:39 -05002321 struct net_device *dev = hw->dev[port];
Stephen Hemmingeree294dc2005-12-14 15:47:44 -08002322
2323 netif_stop_queue(skge->netdev);
2324 netif_carrier_off(skge->netdev);
2325
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07002326 mutex_lock(&hw->phy_mutex);
Stephen Hemmingeree294dc2005-12-14 15:47:44 -08002327 if (hw->chip_id == CHIP_ID_GENESIS) {
2328 genesis_reset(hw, port);
2329 genesis_mac_init(hw, port);
2330 } else {
2331 yukon_reset(hw, port);
2332 yukon_init(hw, port);
2333 }
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07002334 mutex_unlock(&hw->phy_mutex);
Stephen Hemminger75814092006-12-01 11:41:08 -08002335
2336 dev->set_multicast_list(dev);
Stephen Hemmingeree294dc2005-12-14 15:47:44 -08002337}
2338
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08002339/* Basic MII support */
2340static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2341{
2342 struct mii_ioctl_data *data = if_mii(ifr);
2343 struct skge_port *skge = netdev_priv(dev);
2344 struct skge_hw *hw = skge->hw;
2345 int err = -EOPNOTSUPP;
2346
2347 if (!netif_running(dev))
2348 return -ENODEV; /* Phy still in reset */
2349
2350 switch(cmd) {
2351 case SIOCGMIIPHY:
2352 data->phy_id = hw->phy_addr;
2353
2354 /* fallthru */
2355 case SIOCGMIIREG: {
2356 u16 val = 0;
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07002357 mutex_lock(&hw->phy_mutex);
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08002358 if (hw->chip_id == CHIP_ID_GENESIS)
2359 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2360 else
2361 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07002362 mutex_unlock(&hw->phy_mutex);
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08002363 data->val_out = val;
2364 break;
2365 }
2366
2367 case SIOCSMIIREG:
2368 if (!capable(CAP_NET_ADMIN))
2369 return -EPERM;
2370
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07002371 mutex_lock(&hw->phy_mutex);
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08002372 if (hw->chip_id == CHIP_ID_GENESIS)
2373 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2374 data->val_in);
2375 else
2376 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2377 data->val_in);
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07002378 mutex_unlock(&hw->phy_mutex);
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08002379 break;
2380 }
2381 return err;
2382}
2383
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002384static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2385{
2386 u32 end;
2387
2388 start /= 8;
2389 len /= 8;
2390 end = start + len - 1;
2391
2392 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2393 skge_write32(hw, RB_ADDR(q, RB_START), start);
2394 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2395 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2396 skge_write32(hw, RB_ADDR(q, RB_END), end);
2397
2398 if (q == Q_R1 || q == Q_R2) {
2399 /* Set thresholds on receive queue's */
2400 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2401 start + (2*len)/3);
2402 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2403 start + (len/3));
2404 } else {
2405 /* Enable store & forward on Tx queue's because
2406 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2407 */
2408 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2409 }
2410
2411 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2412}
2413
2414/* Setup Bus Memory Interface */
2415static void skge_qset(struct skge_port *skge, u16 q,
2416 const struct skge_element *e)
2417{
2418 struct skge_hw *hw = skge->hw;
2419 u32 watermark = 0x600;
2420 u64 base = skge->dma + (e->desc - skge->mem);
2421
2422 /* optimization to reduce window on 32bit/33mhz */
2423 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2424 watermark /= 2;
2425
2426 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2427 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2428 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2429 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2430}
2431
2432static int skge_up(struct net_device *dev)
2433{
2434 struct skge_port *skge = netdev_priv(dev);
2435 struct skge_hw *hw = skge->hw;
2436 int port = skge->port;
2437 u32 chunk, ram_addr;
2438 size_t rx_size, tx_size;
2439 int err;
2440
Stephen Hemmingerfae87592007-02-02 08:22:51 -08002441 if (!is_valid_ether_addr(dev->dev_addr))
2442 return -EINVAL;
2443
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002444 if (netif_msg_ifup(skge))
2445 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2446
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002447 if (dev->mtu > RX_BUF_SIZE)
Stephen Hemminger901ccef2006-03-23 11:07:23 -08002448 skge->rx_buf_size = dev->mtu + ETH_HLEN;
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002449 else
2450 skge->rx_buf_size = RX_BUF_SIZE;
2451
2452
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002453 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2454 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2455 skge->mem_size = tx_size + rx_size;
2456 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2457 if (!skge->mem)
2458 return -ENOMEM;
2459
Stephen Hemmingerc3da1442006-03-21 10:57:01 -08002460 BUG_ON(skge->dma & 7);
2461
2462 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08002463 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
Stephen Hemmingerc3da1442006-03-21 10:57:01 -08002464 err = -EINVAL;
2465 goto free_pci_mem;
2466 }
2467
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002468 memset(skge->mem, 0, skge->mem_size);
2469
Stephen Hemminger203babb2006-03-21 10:57:05 -08002470 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2471 if (err)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002472 goto free_pci_mem;
2473
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07002474 err = skge_rx_fill(dev);
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002475 if (err)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002476 goto free_rx_ring;
2477
Stephen Hemminger203babb2006-03-21 10:57:05 -08002478 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2479 skge->dma + rx_size);
2480 if (err)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002481 goto free_rx_ring;
2482
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08002483 /* Initialize MAC */
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07002484 mutex_lock(&hw->phy_mutex);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002485 if (hw->chip_id == CHIP_ID_GENESIS)
2486 genesis_mac_init(hw, port);
2487 else
2488 yukon_mac_init(hw, port);
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07002489 mutex_unlock(&hw->phy_mutex);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002490
2491 /* Configure RAMbuffers */
Stephen Hemminger981d0372005-06-27 11:33:06 -07002492 chunk = hw->ram_size / ((hw->ports + 1)*2);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002493 ram_addr = hw->ram_offset + 2 * chunk * port;
2494
2495 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2496 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2497
2498 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2499 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2500 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2501
2502 /* Start receiver BMU */
2503 wmb();
2504 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
Stephen Hemminger6abebb52005-07-22 16:26:10 -07002505 skge_led(skge, LED_MODE_ON);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002506
Edgar E. Iglesias239e44e2006-08-14 23:00:24 -07002507 netif_poll_enable(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002508 return 0;
2509
2510 free_rx_ring:
2511 skge_rx_clean(skge);
2512 kfree(skge->rx_ring.start);
2513 free_pci_mem:
2514 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002515 skge->mem = NULL;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002516
2517 return err;
2518}
2519
2520static int skge_down(struct net_device *dev)
2521{
2522 struct skge_port *skge = netdev_priv(dev);
2523 struct skge_hw *hw = skge->hw;
2524 int port = skge->port;
2525
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002526 if (skge->mem == NULL)
2527 return 0;
2528
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002529 if (netif_msg_ifdown(skge))
2530 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2531
2532 netif_stop_queue(dev);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07002533 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
Stephen Hemminger208491d82007-02-16 15:37:39 -08002534 cancel_delayed_work(&skge->link_thread);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002535
Stephen Hemminger46a60f22005-09-09 12:54:56 -07002536 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2537 if (hw->chip_id == CHIP_ID_GENESIS)
2538 genesis_stop(skge);
2539 else
2540 yukon_stop(skge);
2541
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002542 /* Stop transmitter */
2543 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2544 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2545 RB_RST_SET|RB_DIS_OP_MD);
2546
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002547
2548 /* Disable Force Sync bit and Enable Alloc bit */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002549 skge_write8(hw, SK_REG(port, TXA_CTRL),
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002550 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2551
2552 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002553 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2554 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002555
2556 /* Reset PCI FIFO */
2557 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2558 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2559
2560 /* Reset the RAM Buffer async Tx queue */
2561 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2562 /* stop receiver */
2563 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2564 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2565 RB_RST_SET|RB_DIS_OP_MD);
2566 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2567
2568 if (hw->chip_id == CHIP_ID_GENESIS) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002569 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2570 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002571 } else {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002572 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2573 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002574 }
2575
Stephen Hemminger6abebb52005-07-22 16:26:10 -07002576 skge_led(skge, LED_MODE_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002577
Edgar E. Iglesias239e44e2006-08-14 23:00:24 -07002578 netif_poll_disable(dev);
Stephen Hemmingere3a1b992007-03-16 14:01:26 -07002579
2580 netif_tx_lock_bh(dev);
Stephen Hemminger513f5332006-09-01 15:53:49 -07002581 skge_tx_clean(dev);
Stephen Hemmingere3a1b992007-03-16 14:01:26 -07002582 netif_tx_unlock_bh(dev);
2583
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002584 skge_rx_clean(skge);
2585
2586 kfree(skge->rx_ring.start);
2587 kfree(skge->tx_ring.start);
2588 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002589 skge->mem = NULL;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002590 return 0;
2591}
2592
Stephen Hemminger29b4e882006-03-23 11:07:28 -08002593static inline int skge_avail(const struct skge_ring *ring)
2594{
2595 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2596 + (ring->to_clean - ring->to_use) - 1;
2597}
2598
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002599static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2600{
2601 struct skge_port *skge = netdev_priv(dev);
2602 struct skge_hw *hw = skge->hw;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002603 struct skge_element *e;
2604 struct skge_tx_desc *td;
2605 int i;
2606 u32 control, len;
2607 u64 map;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002608
Herbert Xu5b057c62006-06-23 02:06:41 -07002609 if (skb_padto(skb, ETH_ZLEN))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002610 return NETDEV_TX_OK;
2611
Stephen Hemminger513f5332006-09-01 15:53:49 -07002612 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002613 return NETDEV_TX_BUSY;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002614
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002615 e = skge->tx_ring.to_use;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002616 td = e->desc;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002617 BUG_ON(td->control & BMU_OWN);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002618 e->skb = skb;
2619 len = skb_headlen(skb);
2620 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2621 pci_unmap_addr_set(e, mapaddr, map);
2622 pci_unmap_len_set(e, maplen, len);
2623
2624 td->dma_lo = map;
2625 td->dma_hi = map >> 32;
2626
Patrick McHardy84fa7932006-08-29 16:44:56 -07002627 if (skb->ip_summed == CHECKSUM_PARTIAL) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002628 int offset = skb->h.raw - skb->data;
2629
2630 /* This seems backwards, but it is what the sk98lin
2631 * does. Looks like hardware is wrong?
2632 */
Jeff Garzikea182d42005-12-01 04:31:32 -05002633 if (skb->h.ipiph->protocol == IPPROTO_UDP
Stephen Hemminger981d0372005-06-27 11:33:06 -07002634 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002635 control = BMU_TCP_CHECK;
2636 else
2637 control = BMU_UDP_CHECK;
2638
2639 td->csum_offs = 0;
2640 td->csum_start = offset;
Al Viroff1dcad2006-11-20 18:07:29 -08002641 td->csum_write = offset + skb->csum_offset;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002642 } else
2643 control = BMU_CHECK;
2644
2645 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2646 control |= BMU_EOF| BMU_IRQ_EOF;
2647 else {
2648 struct skge_tx_desc *tf = td;
2649
2650 control |= BMU_STFWD;
2651 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2652 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2653
2654 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2655 frag->size, PCI_DMA_TODEVICE);
2656
2657 e = e->next;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002658 e->skb = skb;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002659 tf = e->desc;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002660 BUG_ON(tf->control & BMU_OWN);
2661
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002662 tf->dma_lo = map;
2663 tf->dma_hi = (u64) map >> 32;
2664 pci_unmap_addr_set(e, mapaddr, map);
2665 pci_unmap_len_set(e, maplen, frag->size);
2666
2667 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2668 }
2669 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2670 }
2671 /* Make sure all the descriptors written */
2672 wmb();
2673 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2674 wmb();
2675
2676 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2677
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002678 if (unlikely(netif_msg_tx_queued(skge)))
Al Viro0b2d7fe2005-04-03 09:15:52 +01002679 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002680 dev->name, e - skge->tx_ring.start, skb->len);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002681
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002682 skge->tx_ring.to_use = e->next;
Stephen Hemminger9db96472006-06-06 10:11:12 -07002683 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002684 pr_debug("%s: transmit queue full\n", dev->name);
2685 netif_stop_queue(dev);
2686 }
2687
Stephen Hemmingerc68ce712006-03-21 10:57:04 -08002688 dev->trans_start = jiffies;
2689
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002690 return NETDEV_TX_OK;
2691}
2692
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002693
2694/* Free resources associated with this reing element */
2695static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2696 u32 control)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002697{
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002698 struct pci_dev *pdev = skge->hw->pdev;
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002699
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002700 BUG_ON(!e->skb);
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002701
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002702 /* skb header vs. fragment */
2703 if (control & BMU_STF)
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002704 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002705 pci_unmap_len(e, maplen),
2706 PCI_DMA_TODEVICE);
2707 else
2708 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2709 pci_unmap_len(e, maplen),
2710 PCI_DMA_TODEVICE);
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002711
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002712 if (control & BMU_EOF) {
2713 if (unlikely(netif_msg_tx_done(skge)))
2714 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2715 skge->netdev->name, e - skge->tx_ring.start);
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002716
Stephen Hemminger513f5332006-09-01 15:53:49 -07002717 dev_kfree_skb(e->skb);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002718 }
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002719 e->skb = NULL;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002720}
2721
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002722/* Free all buffers in transmit ring */
Stephen Hemminger513f5332006-09-01 15:53:49 -07002723static void skge_tx_clean(struct net_device *dev)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002724{
Stephen Hemminger513f5332006-09-01 15:53:49 -07002725 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002726 struct skge_element *e;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002727
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002728 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2729 struct skge_tx_desc *td = e->desc;
2730 skge_tx_free(skge, e, td->control);
2731 td->control = 0;
2732 }
2733
2734 skge->tx_ring.to_clean = e;
Stephen Hemminger513f5332006-09-01 15:53:49 -07002735 netif_wake_queue(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002736}
2737
2738static void skge_tx_timeout(struct net_device *dev)
2739{
2740 struct skge_port *skge = netdev_priv(dev);
2741
2742 if (netif_msg_timer(skge))
2743 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2744
2745 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
Stephen Hemminger513f5332006-09-01 15:53:49 -07002746 skge_tx_clean(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002747}
2748
2749static int skge_change_mtu(struct net_device *dev, int new_mtu)
2750{
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002751 int err;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002752
Stephen Hemminger95566062005-06-27 11:33:02 -07002753 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002754 return -EINVAL;
2755
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002756 if (!netif_running(dev)) {
2757 dev->mtu = new_mtu;
2758 return 0;
2759 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002760
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002761 skge_down(dev);
2762
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002763 dev->mtu = new_mtu;
Stephen Hemminger7731a4e2005-12-14 15:47:46 -08002764
2765 err = skge_up(dev);
2766 if (err)
2767 dev_close(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002768
2769 return err;
2770}
2771
Stephen Hemmingerc4cd29d2007-02-23 14:03:00 -08002772static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2773
2774static void genesis_add_filter(u8 filter[8], const u8 *addr)
2775{
2776 u32 crc, bit;
2777
2778 crc = ether_crc_le(ETH_ALEN, addr);
2779 bit = ~crc & 0x3f;
2780 filter[bit/8] |= 1 << (bit%8);
2781}
2782
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002783static void genesis_set_multicast(struct net_device *dev)
2784{
2785 struct skge_port *skge = netdev_priv(dev);
2786 struct skge_hw *hw = skge->hw;
2787 int port = skge->port;
2788 int i, count = dev->mc_count;
2789 struct dev_mc_list *list = dev->mc_list;
2790 u32 mode;
2791 u8 filter[8];
2792
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002793 mode = xm_read32(hw, port, XM_MODE);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002794 mode |= XM_MD_ENA_HASH;
2795 if (dev->flags & IFF_PROMISC)
2796 mode |= XM_MD_ENA_PROM;
2797 else
2798 mode &= ~XM_MD_ENA_PROM;
2799
2800 if (dev->flags & IFF_ALLMULTI)
2801 memset(filter, 0xff, sizeof(filter));
2802 else {
2803 memset(filter, 0, sizeof(filter));
Stephen Hemmingerc4cd29d2007-02-23 14:03:00 -08002804
2805 if (skge->flow_status == FLOW_STAT_REM_SEND
2806 || skge->flow_status == FLOW_STAT_SYMMETRIC)
2807 genesis_add_filter(filter, pause_mc_addr);
2808
2809 for (i = 0; list && i < count; i++, list = list->next)
2810 genesis_add_filter(filter, list->dmi_addr);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002811 }
2812
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002813 xm_write32(hw, port, XM_MODE, mode);
Stephen Hemminger45bada62005-06-27 11:33:12 -07002814 xm_outhash(hw, port, XM_HSM, filter);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002815}
2816
Stephen Hemmingerc4cd29d2007-02-23 14:03:00 -08002817static void yukon_add_filter(u8 filter[8], const u8 *addr)
2818{
2819 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2820 filter[bit/8] |= 1 << (bit%8);
2821}
2822
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002823static void yukon_set_multicast(struct net_device *dev)
2824{
2825 struct skge_port *skge = netdev_priv(dev);
2826 struct skge_hw *hw = skge->hw;
2827 int port = skge->port;
2828 struct dev_mc_list *list = dev->mc_list;
Stephen Hemmingerc4cd29d2007-02-23 14:03:00 -08002829 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND
2830 || skge->flow_status == FLOW_STAT_SYMMETRIC);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002831 u16 reg;
2832 u8 filter[8];
2833
2834 memset(filter, 0, sizeof(filter));
2835
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002836 reg = gma_read16(hw, port, GM_RX_CTRL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002837 reg |= GM_RXCR_UCF_ENA;
2838
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08002839 if (dev->flags & IFF_PROMISC) /* promiscuous */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002840 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2841 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2842 memset(filter, 0xff, sizeof(filter));
Stephen Hemmingerc4cd29d2007-02-23 14:03:00 -08002843 else if (dev->mc_count == 0 && !rx_pause)/* no multicast */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002844 reg &= ~GM_RXCR_MCF_ENA;
2845 else {
2846 int i;
2847 reg |= GM_RXCR_MCF_ENA;
2848
Stephen Hemmingerc4cd29d2007-02-23 14:03:00 -08002849 if (rx_pause)
2850 yukon_add_filter(filter, pause_mc_addr);
2851
2852 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2853 yukon_add_filter(filter, list->dmi_addr);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002854 }
2855
2856
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002857 gma_write16(hw, port, GM_MC_ADDR_H1,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002858 (u16)filter[0] | ((u16)filter[1] << 8));
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002859 gma_write16(hw, port, GM_MC_ADDR_H2,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002860 (u16)filter[2] | ((u16)filter[3] << 8));
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002861 gma_write16(hw, port, GM_MC_ADDR_H3,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002862 (u16)filter[4] | ((u16)filter[5] << 8));
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002863 gma_write16(hw, port, GM_MC_ADDR_H4,
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002864 (u16)filter[6] | ((u16)filter[7] << 8));
2865
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07002866 gma_write16(hw, port, GM_RX_CTRL, reg);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002867}
2868
Stephen Hemminger383181a2005-09-19 15:37:16 -07002869static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2870{
2871 if (hw->chip_id == CHIP_ID_GENESIS)
2872 return status >> XMR_FS_LEN_SHIFT;
2873 else
2874 return status >> GMR_FS_LEN_SHIFT;
2875}
2876
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002877static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2878{
2879 if (hw->chip_id == CHIP_ID_GENESIS)
2880 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2881 else
2882 return (status & GMR_FS_ANY_ERR) ||
2883 (status & GMR_FS_RX_OK) == 0;
2884}
2885
Stephen Hemminger383181a2005-09-19 15:37:16 -07002886
2887/* Get receive buffer from descriptor.
2888 * Handles copy of small buffers and reallocation failures
2889 */
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07002890static struct sk_buff *skge_rx_get(struct net_device *dev,
2891 struct skge_element *e,
2892 u32 control, u32 status, u16 csum)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002893{
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07002894 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger383181a2005-09-19 15:37:16 -07002895 struct sk_buff *skb;
2896 u16 len = control & BMU_BBC;
2897
2898 if (unlikely(netif_msg_rx_status(skge)))
2899 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07002900 dev->name, e - skge->rx_ring.start,
Stephen Hemminger383181a2005-09-19 15:37:16 -07002901 status, len);
2902
2903 if (len > skge->rx_buf_size)
2904 goto error;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002905
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002906 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
Stephen Hemminger383181a2005-09-19 15:37:16 -07002907 goto error;
2908
2909 if (bad_phy_status(skge->hw, status))
2910 goto error;
2911
2912 if (phy_length(skge->hw, status) != len)
2913 goto error;
2914
2915 if (len < RX_COPY_THRESHOLD) {
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07002916 skb = netdev_alloc_skb(dev, len + 2);
Stephen Hemminger383181a2005-09-19 15:37:16 -07002917 if (!skb)
2918 goto resubmit;
2919
2920 skb_reserve(skb, 2);
2921 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2922 pci_unmap_addr(e, mapaddr),
2923 len, PCI_DMA_FROMDEVICE);
2924 memcpy(skb->data, e->skb->data, len);
2925 pci_dma_sync_single_for_device(skge->hw->pdev,
2926 pci_unmap_addr(e, mapaddr),
2927 len, PCI_DMA_FROMDEVICE);
2928 skge_rx_reuse(e, skge->rx_buf_size);
2929 } else {
2930 struct sk_buff *nskb;
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07002931 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
Stephen Hemminger383181a2005-09-19 15:37:16 -07002932 if (!nskb)
2933 goto resubmit;
2934
Stephen Hemminger901ccef2006-03-23 11:07:23 -08002935 skb_reserve(nskb, NET_IP_ALIGN);
Stephen Hemminger383181a2005-09-19 15:37:16 -07002936 pci_unmap_single(skge->hw->pdev,
2937 pci_unmap_addr(e, mapaddr),
2938 pci_unmap_len(e, maplen),
2939 PCI_DMA_FROMDEVICE);
2940 skb = e->skb;
2941 prefetch(skb->data);
2942 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2943 }
2944
2945 skb_put(skb, len);
Stephen Hemminger383181a2005-09-19 15:37:16 -07002946 if (skge->rx_csum) {
2947 skb->csum = csum;
Patrick McHardy84fa7932006-08-29 16:44:56 -07002948 skb->ip_summed = CHECKSUM_COMPLETE;
Stephen Hemminger383181a2005-09-19 15:37:16 -07002949 }
2950
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07002951 skb->protocol = eth_type_trans(skb, dev);
Stephen Hemminger383181a2005-09-19 15:37:16 -07002952
2953 return skb;
2954error:
2955
2956 if (netif_msg_rx_err(skge))
2957 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07002958 dev->name, e - skge->rx_ring.start,
Stephen Hemminger383181a2005-09-19 15:37:16 -07002959 control, status);
2960
2961 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002962 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2963 skge->net_stats.rx_length_errors++;
2964 if (status & XMR_FS_FRA_ERR)
2965 skge->net_stats.rx_frame_errors++;
2966 if (status & XMR_FS_FCS_ERR)
2967 skge->net_stats.rx_crc_errors++;
2968 } else {
2969 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2970 skge->net_stats.rx_length_errors++;
2971 if (status & GMR_FS_FRAGMENT)
2972 skge->net_stats.rx_frame_errors++;
2973 if (status & GMR_FS_CRC_ERR)
2974 skge->net_stats.rx_crc_errors++;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002975 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04002976
Stephen Hemminger383181a2005-09-19 15:37:16 -07002977resubmit:
2978 skge_rx_reuse(e, skge->rx_buf_size);
2979 return NULL;
Stephen Hemminger19a33d42005-06-27 11:33:15 -07002980}
2981
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002982/* Free all buffers in Tx ring which are no longer owned by device */
Stephen Hemminger513f5332006-09-01 15:53:49 -07002983static void skge_tx_done(struct net_device *dev)
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08002984{
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002985 struct skge_port *skge = netdev_priv(dev);
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08002986 struct skge_ring *ring = &skge->tx_ring;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002987 struct skge_element *e;
2988
Stephen Hemminger513f5332006-09-01 15:53:49 -07002989 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08002990
Stephen Hemminger513f5332006-09-01 15:53:49 -07002991 netif_tx_lock(dev);
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002992 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08002993 struct skge_tx_desc *td = e->desc;
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08002994
Stephen Hemminger866b4f32006-03-23 11:07:27 -08002995 if (td->control & BMU_OWN)
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08002996 break;
2997
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07002998 skge_tx_free(skge, e, td->control);
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08002999 }
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003000 skge->tx_ring.to_clean = e;
Stephen Hemminger866b4f32006-03-23 11:07:27 -08003001
Stephen Hemminger513f5332006-09-01 15:53:49 -07003002 if (skge_avail(&skge->tx_ring) > TX_LOW_WATER)
3003 netif_wake_queue(dev);
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08003004
Stephen Hemminger513f5332006-09-01 15:53:49 -07003005 netif_tx_unlock(dev);
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08003006}
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003007
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003008static int skge_poll(struct net_device *dev, int *budget)
3009{
3010 struct skge_port *skge = netdev_priv(dev);
3011 struct skge_hw *hw = skge->hw;
3012 struct skge_ring *ring = &skge->rx_ring;
3013 struct skge_element *e;
Francois Romieud15e9c42006-12-17 23:03:15 +01003014 unsigned long flags;
Stephen Hemminger00a6cae2006-03-21 10:56:59 -08003015 int to_do = min(dev->quota, *budget);
3016 int work_done = 0;
3017
Stephen Hemminger513f5332006-09-01 15:53:49 -07003018 skge_tx_done(dev);
3019
3020 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3021
Stephen Hemminger1631aef2005-11-08 10:33:44 -08003022 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003023 struct skge_rx_desc *rd = e->desc;
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003024 struct sk_buff *skb;
Stephen Hemminger383181a2005-09-19 15:37:16 -07003025 u32 control;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003026
3027 rmb();
3028 control = rd->control;
3029 if (control & BMU_OWN)
3030 break;
3031
Stephen Hemmingerc54f9762006-09-01 15:53:47 -07003032 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003033 if (likely(skb)) {
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003034 dev->last_rx = jiffies;
3035 netif_receive_skb(skb);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003036
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003037 ++work_done;
Stephen Hemminger5a011442006-03-23 11:07:25 -08003038 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003039 }
3040 ring->to_clean = e;
3041
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003042 /* restart receiver */
3043 wmb();
Stephen Hemmingera9cdab82006-02-22 10:28:33 -08003044 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003045
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003046 *budget -= work_done;
3047 dev->quota -= work_done;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003048
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003049 if (work_done >= to_do)
3050 return 1; /* not done */
3051
Francois Romieud15e9c42006-12-17 23:03:15 +01003052 spin_lock_irqsave(&hw->hw_lock, flags);
Stephen Hemminger513f5332006-09-01 15:53:49 -07003053 __netif_rx_complete(dev);
3054 hw->intr_mask |= irqmask[skge->port];
Stephen Hemminger80dd8572006-02-22 10:28:35 -08003055 skge_write32(hw, B0_IMSK, hw->intr_mask);
Stephen Hemminger78bc2182006-08-28 16:19:36 -07003056 skge_read32(hw, B0_IMSK);
Francois Romieud15e9c42006-12-17 23:03:15 +01003057 spin_unlock_irqrestore(&hw->hw_lock, flags);
Stephen Hemminger1631aef2005-11-08 10:33:44 -08003058
Stephen Hemminger19a33d42005-06-27 11:33:15 -07003059 return 0;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003060}
3061
Stephen Hemmingerf6620ca2005-07-22 16:26:02 -07003062/* Parity errors seem to happen when Genesis is connected to a switch
3063 * with no other ports present. Heartbeat error??
3064 */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003065static void skge_mac_parity(struct skge_hw *hw, int port)
3066{
Stephen Hemmingerf6620ca2005-07-22 16:26:02 -07003067 struct net_device *dev = hw->dev[port];
3068
3069 if (dev) {
3070 struct skge_port *skge = netdev_priv(dev);
3071 ++skge->net_stats.tx_heartbeat_errors;
3072 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003073
3074 if (hw->chip_id == CHIP_ID_GENESIS)
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07003075 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003076 MFF_CLR_PERR);
3077 else
3078 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07003079 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
Stephen Hemminger981d0372005-06-27 11:33:06 -07003080 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003081 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3082}
3083
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003084static void skge_mac_intr(struct skge_hw *hw, int port)
3085{
Stephen Hemminger95566062005-06-27 11:33:02 -07003086 if (hw->chip_id == CHIP_ID_GENESIS)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003087 genesis_mac_intr(hw, port);
3088 else
3089 yukon_mac_intr(hw, port);
3090}
3091
3092/* Handle device specific framing and timeout interrupts */
3093static void skge_error_irq(struct skge_hw *hw)
3094{
Stephen Hemminger1479d132007-02-02 08:22:52 -08003095 struct pci_dev *pdev = hw->pdev;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003096 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3097
3098 if (hw->chip_id == CHIP_ID_GENESIS) {
3099 /* clear xmac errors */
3100 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
Stephen Hemminger46a60f22005-09-09 12:54:56 -07003101 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003102 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
Stephen Hemminger46a60f22005-09-09 12:54:56 -07003103 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003104 } else {
3105 /* Timestamp (unused) overflow */
3106 if (hwstatus & IS_IRQ_TIST_OV)
3107 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003108 }
3109
3110 if (hwstatus & IS_RAM_RD_PAR) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003111 dev_err(&pdev->dev, "Ram read data parity error\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003112 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3113 }
3114
3115 if (hwstatus & IS_RAM_WR_PAR) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003116 dev_err(&pdev->dev, "Ram write data parity error\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003117 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3118 }
3119
3120 if (hwstatus & IS_M1_PAR_ERR)
3121 skge_mac_parity(hw, 0);
3122
3123 if (hwstatus & IS_M2_PAR_ERR)
3124 skge_mac_parity(hw, 1);
3125
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003126 if (hwstatus & IS_R1_PAR_ERR) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003127 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3128 hw->dev[0]->name);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003129 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003130 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003131
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003132 if (hwstatus & IS_R2_PAR_ERR) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003133 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3134 hw->dev[1]->name);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003135 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003136 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003137
3138 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003139 u16 pci_status, pci_cmd;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003140
Stephen Hemminger1479d132007-02-02 08:22:52 -08003141 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3142 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003143
Stephen Hemminger1479d132007-02-02 08:22:52 -08003144 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3145 pci_cmd, pci_status);
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003146
3147 /* Write the error bits back to clear them. */
3148 pci_status &= PCI_STATUS_ERROR_BITS;
3149 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
Stephen Hemminger1479d132007-02-02 08:22:52 -08003150 pci_write_config_word(pdev, PCI_COMMAND,
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003151 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
Stephen Hemminger1479d132007-02-02 08:22:52 -08003152 pci_write_config_word(pdev, PCI_STATUS, pci_status);
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003153 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003154
Stephen Hemminger050ec182005-08-16 14:00:54 -07003155 /* if error still set then just ignore it */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003156 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3157 if (hwstatus & IS_IRQ_STAT) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003158 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003159 hw->intr_mask &= ~IS_HW_ERR;
3160 }
3161 }
3162}
3163
3164/*
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07003165 * Interrupt from PHY are handled in work queue
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003166 * because accessing phy registers requires spin wait which might
3167 * cause excess interrupt latency.
3168 */
David Howellsc4028952006-11-22 14:57:56 +00003169static void skge_extirq(struct work_struct *work)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003170{
David Howellsc4028952006-11-22 14:57:56 +00003171 struct skge_hw *hw = container_of(work, struct skge_hw, phy_work);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003172 int port;
3173
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07003174 mutex_lock(&hw->phy_mutex);
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003175 for (port = 0; port < hw->ports; port++) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003176 struct net_device *dev = hw->dev[port];
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003177 struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003178
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003179 if (netif_running(dev)) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003180 if (hw->chip_id != CHIP_ID_GENESIS)
3181 yukon_phy_intr(skge);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003182 else if (hw->phy_type == SK_PHY_BCOM)
Stephen Hemminger45bada62005-06-27 11:33:12 -07003183 bcom_phy_intr(skge);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003184 }
3185 }
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07003186 mutex_unlock(&hw->phy_mutex);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003187
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003188 spin_lock_irq(&hw->hw_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003189 hw->intr_mask |= IS_EXT_REG;
3190 skge_write32(hw, B0_IMSK, hw->intr_mask);
Stephen Hemminger78bc2182006-08-28 16:19:36 -07003191 skge_read32(hw, B0_IMSK);
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003192 spin_unlock_irq(&hw->hw_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003193}
3194
David Howells7d12e782006-10-05 14:55:46 +01003195static irqreturn_t skge_intr(int irq, void *dev_id)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003196{
3197 struct skge_hw *hw = dev_id;
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003198 u32 status;
Stephen Hemminger29365c92006-09-01 15:53:48 -07003199 int handled = 0;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003200
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003201 spin_lock(&hw->hw_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003202 /* Reading this register masks IRQ */
3203 status = skge_read32(hw, B0_SP_ISRC);
Stephen Hemminger0486a8c2006-09-06 11:06:10 -07003204 if (status == 0 || status == ~0)
Stephen Hemminger29365c92006-09-01 15:53:48 -07003205 goto out;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003206
Stephen Hemminger29365c92006-09-01 15:53:48 -07003207 handled = 1;
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003208 status &= hw->intr_mask;
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003209 if (status & IS_EXT_REG) {
3210 hw->intr_mask &= ~IS_EXT_REG;
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07003211 schedule_work(&hw->phy_work);
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003212 }
3213
Stephen Hemminger513f5332006-09-01 15:53:49 -07003214 if (status & (IS_XA1_F|IS_R1_F)) {
3215 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
Stephen Hemmingera9cdab82006-02-22 10:28:33 -08003216 netif_rx_schedule(hw->dev[0]);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003217 }
3218
Stephen Hemmingerd25f5a62005-06-27 11:33:14 -07003219 if (status & IS_PA_TO_TX1)
3220 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3221
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003222 if (status & IS_PA_TO_RX1) {
3223 struct skge_port *skge = netdev_priv(hw->dev[0]);
3224
3225 ++skge->net_stats.rx_over_errors;
3226 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3227 }
3228
Stephen Hemmingerd25f5a62005-06-27 11:33:14 -07003229
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003230 if (status & IS_MAC1)
3231 skge_mac_intr(hw, 0);
Stephen Hemminger95566062005-06-27 11:33:02 -07003232
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003233 if (hw->dev[1]) {
Stephen Hemminger513f5332006-09-01 15:53:49 -07003234 if (status & (IS_XA2_F|IS_R2_F)) {
3235 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003236 netif_rx_schedule(hw->dev[1]);
3237 }
3238
3239 if (status & IS_PA_TO_RX2) {
3240 struct skge_port *skge = netdev_priv(hw->dev[1]);
3241 ++skge->net_stats.rx_over_errors;
3242 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3243 }
3244
3245 if (status & IS_PA_TO_TX2)
3246 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3247
3248 if (status & IS_MAC2)
3249 skge_mac_intr(hw, 1);
3250 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003251
3252 if (status & IS_HW_ERR)
3253 skge_error_irq(hw);
3254
Stephen Hemminger7e676d92005-06-27 11:33:13 -07003255 skge_write32(hw, B0_IMSK, hw->intr_mask);
Stephen Hemminger78bc2182006-08-28 16:19:36 -07003256 skge_read32(hw, B0_IMSK);
Stephen Hemminger29365c92006-09-01 15:53:48 -07003257out:
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003258 spin_unlock(&hw->hw_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003259
Stephen Hemminger29365c92006-09-01 15:53:48 -07003260 return IRQ_RETVAL(handled);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003261}
3262
3263#ifdef CONFIG_NET_POLL_CONTROLLER
3264static void skge_netpoll(struct net_device *dev)
3265{
3266 struct skge_port *skge = netdev_priv(dev);
3267
3268 disable_irq(dev->irq);
David Howells7d12e782006-10-05 14:55:46 +01003269 skge_intr(dev->irq, skge->hw);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003270 enable_irq(dev->irq);
3271}
3272#endif
3273
3274static int skge_set_mac_address(struct net_device *dev, void *p)
3275{
3276 struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingerc2681dd2005-10-03 12:03:13 -07003277 struct skge_hw *hw = skge->hw;
3278 unsigned port = skge->port;
3279 const struct sockaddr *addr = p;
Stephen Hemminger2eb3e622007-03-12 15:16:26 -07003280 u16 ctrl;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003281
3282 if (!is_valid_ether_addr(addr->sa_data))
3283 return -EADDRNOTAVAIL;
3284
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003285 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
Stephen Hemmingerc2681dd2005-10-03 12:03:13 -07003286
Stephen Hemminger2eb3e622007-03-12 15:16:26 -07003287 /* disable Rx */
3288 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3289 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3290
3291 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3292 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3293
3294 if (netif_running(dev)) {
3295 if (hw->chip_id == CHIP_ID_GENESIS)
3296 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3297 else {
3298 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3299 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3300 }
Stephen Hemmingerc2681dd2005-10-03 12:03:13 -07003301 }
Stephen Hemminger2eb3e622007-03-12 15:16:26 -07003302
3303 gma_write16(hw, port, GM_GP_CTRL, ctrl);
Stephen Hemmingerc2681dd2005-10-03 12:03:13 -07003304
3305 return 0;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003306}
3307
3308static const struct {
3309 u8 id;
3310 const char *name;
3311} skge_chips[] = {
3312 { CHIP_ID_GENESIS, "Genesis" },
3313 { CHIP_ID_YUKON, "Yukon" },
3314 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3315 { CHIP_ID_YUKON_LP, "Yukon-LP"},
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003316};
3317
3318static const char *skge_board_name(const struct skge_hw *hw)
3319{
3320 int i;
3321 static char buf[16];
3322
3323 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3324 if (skge_chips[i].id == hw->chip_id)
3325 return skge_chips[i].name;
3326
3327 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3328 return buf;
3329}
3330
3331
3332/*
3333 * Setup the board data structure, but don't bring up
3334 * the port(s)
3335 */
3336static int skge_reset(struct skge_hw *hw)
3337{
Stephen Hemmingeradba9e22005-11-08 10:33:40 -08003338 u32 reg;
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003339 u16 ctst, pci_status;
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003340 u8 t8, mac_cfg, pmd_type;
Stephen Hemminger981d0372005-06-27 11:33:06 -07003341 int i;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003342
3343 ctst = skge_read16(hw, B0_CTST);
3344
3345 /* do a SW reset */
3346 skge_write8(hw, B0_CTST, CS_RST_SET);
3347 skge_write8(hw, B0_CTST, CS_RST_CLR);
3348
3349 /* clear PCI errors, if any */
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003350 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3351 skge_write8(hw, B2_TST_CTRL2, 0);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003352
Stephen Hemmingerb9d64ac2006-03-21 10:57:06 -08003353 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3354 pci_write_config_word(hw->pdev, PCI_STATUS,
3355 pci_status | PCI_STATUS_ERROR_BITS);
3356 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003357 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3358
3359 /* restore CLK_RUN bits (for Yukon-Lite) */
3360 skge_write16(hw, B0_CTST,
3361 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3362
3363 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003364 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
Stephen Hemminger5e1705d2005-08-16 14:00:58 -07003365 pmd_type = skge_read8(hw, B2_PMD_TYP);
3366 hw->copper = (pmd_type == 'T' || pmd_type == '1');
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003367
Stephen Hemminger95566062005-06-27 11:33:02 -07003368 switch (hw->chip_id) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003369 case CHIP_ID_GENESIS:
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003370 switch (hw->phy_type) {
3371 case SK_PHY_XMAC:
3372 hw->phy_addr = PHY_ADDR_XMAC;
3373 break;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003374 case SK_PHY_BCOM:
3375 hw->phy_addr = PHY_ADDR_BCOM;
3376 break;
3377 default:
Stephen Hemminger1479d132007-02-02 08:22:52 -08003378 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3379 hw->phy_type);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003380 return -EOPNOTSUPP;
3381 }
3382 break;
3383
3384 case CHIP_ID_YUKON:
3385 case CHIP_ID_YUKON_LITE:
3386 case CHIP_ID_YUKON_LP:
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003387 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
Stephen Hemminger5e1705d2005-08-16 14:00:58 -07003388 hw->copper = 1;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003389
3390 hw->phy_addr = PHY_ADDR_MARV;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003391 break;
3392
3393 default:
Stephen Hemminger1479d132007-02-02 08:22:52 -08003394 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3395 hw->chip_id);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003396 return -EOPNOTSUPP;
3397 }
3398
Stephen Hemminger981d0372005-06-27 11:33:06 -07003399 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3400 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3401 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003402
3403 /* read the adapters RAM size */
3404 t8 = skge_read8(hw, B2_E_0);
3405 if (hw->chip_id == CHIP_ID_GENESIS) {
3406 if (t8 == 3) {
3407 /* special case: 4 x 64k x 36, offset = 0x80000 */
3408 hw->ram_size = 0x100000;
3409 hw->ram_offset = 0x80000;
3410 } else
3411 hw->ram_size = t8 * 512;
3412 }
3413 else if (t8 == 0)
3414 hw->ram_size = 0x20000;
3415 else
3416 hw->ram_size = t8 * 4096;
3417
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003418 hw->intr_mask = IS_HW_ERR | IS_PORT_1;
Stephen Hemmingercfc3ed72006-03-21 10:57:00 -08003419 if (hw->ports > 1)
3420 hw->intr_mask |= IS_PORT_2;
3421
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003422 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3423 hw->intr_mask |= IS_EXT_REG;
3424
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003425 if (hw->chip_id == CHIP_ID_GENESIS)
3426 genesis_init(hw);
3427 else {
3428 /* switch power to VCC (WA for VAUX problem) */
3429 skge_write8(hw, B0_POWER_CTRL,
3430 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
Stephen Hemmingeradba9e22005-11-08 10:33:40 -08003431
Stephen Hemminger050ec182005-08-16 14:00:54 -07003432 /* avoid boards with stuck Hardware error bits */
3433 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3434 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003435 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
Stephen Hemminger050ec182005-08-16 14:00:54 -07003436 hw->intr_mask &= ~IS_HW_ERR;
3437 }
3438
Stephen Hemmingeradba9e22005-11-08 10:33:40 -08003439 /* Clear PHY COMA */
3440 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3441 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3442 reg &= ~PCI_PHY_COMA;
3443 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3444 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3445
3446
Stephen Hemminger981d0372005-06-27 11:33:06 -07003447 for (i = 0; i < hw->ports; i++) {
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07003448 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3449 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003450 }
3451 }
3452
3453 /* turn off hardware timer (unused) */
3454 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3455 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3456 skge_write8(hw, B0_LED, LED_STAT_ON);
3457
3458 /* enable the Tx Arbiters */
Stephen Hemminger981d0372005-06-27 11:33:06 -07003459 for (i = 0; i < hw->ports; i++)
Stephen Hemminger6b0c1482005-06-27 11:33:04 -07003460 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003461
3462 /* Initialize ram interface */
3463 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3464
3465 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3466 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3467 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3468 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3469 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3470 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3471 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3472 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3473 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3474 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3475 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3476 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3477
3478 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3479
3480 /* Set interrupt moderation for Transmit only
3481 * Receive interrupts avoided by NAPI
3482 */
3483 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3484 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3485 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3486
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003487 skge_write32(hw, B0_IMSK, hw->intr_mask);
3488
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07003489 mutex_lock(&hw->phy_mutex);
Stephen Hemminger981d0372005-06-27 11:33:06 -07003490 for (i = 0; i < hw->ports; i++) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003491 if (hw->chip_id == CHIP_ID_GENESIS)
3492 genesis_reset(hw, i);
3493 else
3494 yukon_reset(hw, i);
3495 }
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07003496 mutex_unlock(&hw->phy_mutex);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003497
3498 return 0;
3499}
3500
3501/* Initialize network device */
Stephen Hemminger981d0372005-06-27 11:33:06 -07003502static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3503 int highmem)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003504{
3505 struct skge_port *skge;
3506 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3507
3508 if (!dev) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003509 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003510 return NULL;
3511 }
3512
3513 SET_MODULE_OWNER(dev);
3514 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3515 dev->open = skge_up;
3516 dev->stop = skge_down;
Stephen Hemminger2cd8e5d2005-11-08 10:33:42 -08003517 dev->do_ioctl = skge_ioctl;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003518 dev->hard_start_xmit = skge_xmit_frame;
3519 dev->get_stats = skge_get_stats;
3520 if (hw->chip_id == CHIP_ID_GENESIS)
3521 dev->set_multicast_list = genesis_set_multicast;
3522 else
3523 dev->set_multicast_list = yukon_set_multicast;
3524
3525 dev->set_mac_address = skge_set_mac_address;
3526 dev->change_mtu = skge_change_mtu;
3527 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3528 dev->tx_timeout = skge_tx_timeout;
3529 dev->watchdog_timeo = TX_WATCHDOG;
3530 dev->poll = skge_poll;
3531 dev->weight = NAPI_WEIGHT;
3532#ifdef CONFIG_NET_POLL_CONTROLLER
3533 dev->poll_controller = skge_netpoll;
3534#endif
3535 dev->irq = hw->pdev->irq;
Stephen Hemminger513f5332006-09-01 15:53:49 -07003536
Stephen Hemminger981d0372005-06-27 11:33:06 -07003537 if (highmem)
3538 dev->features |= NETIF_F_HIGHDMA;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003539
3540 skge = netdev_priv(dev);
3541 skge->netdev = dev;
3542 skge->hw = hw;
3543 skge->msg_enable = netif_msg_init(debug, default_msg);
3544 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3545 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3546
3547 /* Auto speed and flow control */
3548 skge->autoneg = AUTONEG_ENABLE;
Stephen Hemminger5d5c8e02006-10-05 15:49:52 -07003549 skge->flow_control = FLOW_MODE_SYM_OR_REM;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003550 skge->duplex = -1;
3551 skge->speed = -1;
Stephen Hemminger31b619c2005-06-27 11:33:11 -07003552 skge->advertising = skge_supported_modes(hw);
Stephen Hemmingera504e642007-02-02 08:22:53 -08003553 skge->wol = pci_wake_enabled(hw->pdev) ? wol_supported(hw) : 0;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003554
3555 hw->dev[port] = dev;
3556
3557 skge->port = port;
3558
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003559 /* Only used for Genesis XMAC */
David Howellsc4028952006-11-22 14:57:56 +00003560 INIT_DELAYED_WORK(&skge->link_thread, xm_link_timer);
Stephen Hemminger64f6b642006-09-23 21:25:28 -07003561
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003562 if (hw->chip_id != CHIP_ID_GENESIS) {
3563 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3564 skge->rx_csum = 1;
3565 }
3566
3567 /* read the mac address */
3568 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
John W. Linville56230d52005-09-12 10:48:57 -04003569 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003570
3571 /* device is off until link detection */
3572 netif_carrier_off(dev);
3573 netif_stop_queue(dev);
3574
3575 return dev;
3576}
3577
3578static void __devinit skge_show_addr(struct net_device *dev)
3579{
3580 const struct skge_port *skge = netdev_priv(dev);
3581
3582 if (netif_msg_probe(skge))
3583 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3584 dev->name,
3585 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3586 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3587}
3588
3589static int __devinit skge_probe(struct pci_dev *pdev,
3590 const struct pci_device_id *ent)
3591{
3592 struct net_device *dev, *dev1;
3593 struct skge_hw *hw;
3594 int err, using_dac = 0;
3595
Stephen Hemminger203babb2006-03-21 10:57:05 -08003596 err = pci_enable_device(pdev);
3597 if (err) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003598 dev_err(&pdev->dev, "cannot enable PCI device\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003599 goto err_out;
3600 }
3601
Stephen Hemminger203babb2006-03-21 10:57:05 -08003602 err = pci_request_regions(pdev, DRV_NAME);
3603 if (err) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003604 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003605 goto err_out_disable_pdev;
3606 }
3607
3608 pci_set_master(pdev);
3609
Stephen Hemminger93aea712006-03-21 10:57:02 -08003610 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003611 using_dac = 1;
Stephen Hemminger77783a72006-01-05 16:26:05 -08003612 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
Stephen Hemminger93aea712006-03-21 10:57:02 -08003613 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3614 using_dac = 0;
3615 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3616 }
3617
3618 if (err) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003619 dev_err(&pdev->dev, "no usable DMA configuration\n");
Stephen Hemminger93aea712006-03-21 10:57:02 -08003620 goto err_out_free_regions;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003621 }
3622
3623#ifdef __BIG_ENDIAN
Stephen Hemminger8f3f8192005-11-08 10:33:45 -08003624 /* byte swap descriptors in hardware */
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003625 {
3626 u32 reg;
3627
3628 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3629 reg |= PCI_REV_DESC;
3630 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3631 }
3632#endif
3633
3634 err = -ENOMEM;
Stephen Hemminger7e863062005-11-08 10:33:41 -08003635 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003636 if (!hw) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003637 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003638 goto err_out_free_regions;
3639 }
3640
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003641 hw->pdev = pdev;
Stephen Hemmingerd85b5142006-06-06 10:11:11 -07003642 mutex_init(&hw->phy_mutex);
David Howellsc4028952006-11-22 14:57:56 +00003643 INIT_WORK(&hw->phy_work, skge_extirq);
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003644 spin_lock_init(&hw->hw_lock);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003645
3646 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3647 if (!hw->regs) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003648 dev_err(&pdev->dev, "cannot map device registers\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003649 goto err_out_free_hw;
3650 }
3651
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003652 err = skge_reset(hw);
3653 if (err)
Stephen Hemmingerccdaa2a2006-08-28 16:19:38 -07003654 goto err_out_iounmap;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003655
Greg Kroah-Hartman7c7459d2006-06-12 15:13:08 -07003656 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3657 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
Stephen Hemminger981d0372005-06-27 11:33:06 -07003658 skge_board_name(hw), hw->chip_rev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003659
Stephen Hemmingerccdaa2a2006-08-28 16:19:38 -07003660 dev = skge_devinit(hw, 0, using_dac);
3661 if (!dev)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003662 goto err_out_led_off;
3663
Stephen Hemmingerfae87592007-02-02 08:22:51 -08003664 /* Some motherboards are broken and has zero in ROM. */
Stephen Hemminger1479d132007-02-02 08:22:52 -08003665 if (!is_valid_ether_addr(dev->dev_addr))
3666 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
Stephen Hemminger631ae322006-06-06 10:11:14 -07003667
Stephen Hemminger203babb2006-03-21 10:57:05 -08003668 err = register_netdev(dev);
3669 if (err) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003670 dev_err(&pdev->dev, "cannot register net device\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003671 goto err_out_free_netdev;
3672 }
3673
Stephen Hemmingerccdaa2a2006-08-28 16:19:38 -07003674 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3675 if (err) {
Stephen Hemminger1479d132007-02-02 08:22:52 -08003676 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
Stephen Hemmingerccdaa2a2006-08-28 16:19:38 -07003677 dev->name, pdev->irq);
3678 goto err_out_unregister;
3679 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003680 skge_show_addr(dev);
3681
Stephen Hemminger981d0372005-06-27 11:33:06 -07003682 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003683 if (register_netdev(dev1) == 0)
3684 skge_show_addr(dev1);
3685 else {
3686 /* Failure to register second port need not be fatal */
Stephen Hemminger1479d132007-02-02 08:22:52 -08003687 dev_warn(&pdev->dev, "register of second port failed\n");
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003688 hw->dev[1] = NULL;
3689 free_netdev(dev1);
3690 }
3691 }
Stephen Hemmingerccdaa2a2006-08-28 16:19:38 -07003692 pci_set_drvdata(pdev, hw);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003693
3694 return 0;
3695
Stephen Hemmingerccdaa2a2006-08-28 16:19:38 -07003696err_out_unregister:
3697 unregister_netdev(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003698err_out_free_netdev:
3699 free_netdev(dev);
3700err_out_led_off:
3701 skge_write16(hw, B0_LED, LED_STAT_OFF);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003702err_out_iounmap:
3703 iounmap(hw->regs);
3704err_out_free_hw:
3705 kfree(hw);
3706err_out_free_regions:
3707 pci_release_regions(pdev);
3708err_out_disable_pdev:
3709 pci_disable_device(pdev);
3710 pci_set_drvdata(pdev, NULL);
3711err_out:
3712 return err;
3713}
3714
3715static void __devexit skge_remove(struct pci_dev *pdev)
3716{
3717 struct skge_hw *hw = pci_get_drvdata(pdev);
3718 struct net_device *dev0, *dev1;
3719
Stephen Hemminger95566062005-06-27 11:33:02 -07003720 if (!hw)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003721 return;
3722
Stephen Hemminger208491d82007-02-16 15:37:39 -08003723 flush_scheduled_work();
3724
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003725 if ((dev1 = hw->dev[1]))
3726 unregister_netdev(dev1);
3727 dev0 = hw->dev[0];
3728 unregister_netdev(dev0);
3729
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003730 spin_lock_irq(&hw->hw_lock);
3731 hw->intr_mask = 0;
Stephen Hemminger46a60f22005-09-09 12:54:56 -07003732 skge_write32(hw, B0_IMSK, 0);
Stephen Hemminger78bc2182006-08-28 16:19:36 -07003733 skge_read32(hw, B0_IMSK);
Stephen Hemminger7c442fa2006-06-06 10:11:13 -07003734 spin_unlock_irq(&hw->hw_lock);
3735
Stephen Hemminger46a60f22005-09-09 12:54:56 -07003736 skge_write16(hw, B0_LED, LED_STAT_OFF);
Stephen Hemminger46a60f22005-09-09 12:54:56 -07003737 skge_write8(hw, B0_CTST, CS_RST_SET);
3738
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003739 free_irq(pdev->irq, hw);
3740 pci_release_regions(pdev);
3741 pci_disable_device(pdev);
3742 if (dev1)
3743 free_netdev(dev1);
3744 free_netdev(dev0);
Stephen Hemminger46a60f22005-09-09 12:54:56 -07003745
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003746 iounmap(hw->regs);
3747 kfree(hw);
3748 pci_set_drvdata(pdev, NULL);
3749}
3750
3751#ifdef CONFIG_PM
Stephen Hemmingera504e642007-02-02 08:22:53 -08003752static int vaux_avail(struct pci_dev *pdev)
3753{
3754 int pm_cap;
3755
3756 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3757 if (pm_cap) {
3758 u16 ctl;
3759 pci_read_config_word(pdev, pm_cap + PCI_PM_PMC, &ctl);
3760 if (ctl & PCI_PM_CAP_AUX_POWER)
3761 return 1;
3762 }
3763 return 0;
3764}
3765
3766
Pavel Machek2a569572005-07-07 17:56:40 -07003767static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003768{
3769 struct skge_hw *hw = pci_get_drvdata(pdev);
Stephen Hemmingera504e642007-02-02 08:22:53 -08003770 int i, err, wol = 0;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003771
Stephen Hemmingera504e642007-02-02 08:22:53 -08003772 err = pci_save_state(pdev);
3773 if (err)
3774 return err;
3775
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003776 for (i = 0; i < hw->ports; i++) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003777 struct net_device *dev = hw->dev[i];
Stephen Hemmingera504e642007-02-02 08:22:53 -08003778 struct skge_port *skge = netdev_priv(dev);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003779
Stephen Hemmingera504e642007-02-02 08:22:53 -08003780 if (netif_running(dev))
3781 skge_down(dev);
3782 if (skge->wol)
3783 skge_wol_init(skge);
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003784
Stephen Hemmingera504e642007-02-02 08:22:53 -08003785 wol |= skge->wol;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003786 }
3787
Stephen Hemmingera504e642007-02-02 08:22:53 -08003788 if (wol && vaux_avail(pdev))
3789 skge_write8(hw, B0_POWER_CTRL,
3790 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
3791
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003792 skge_write32(hw, B0_IMSK, 0);
Pavel Machek2a569572005-07-07 17:56:40 -07003793 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003794 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3795
3796 return 0;
3797}
3798
3799static int skge_resume(struct pci_dev *pdev)
3800{
3801 struct skge_hw *hw = pci_get_drvdata(pdev);
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003802 int i, err;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003803
Stephen Hemmingera504e642007-02-02 08:22:53 -08003804 err = pci_set_power_state(pdev, PCI_D0);
3805 if (err)
3806 goto out;
3807
3808 err = pci_restore_state(pdev);
3809 if (err)
3810 goto out;
3811
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003812 pci_enable_wake(pdev, PCI_D0, 0);
3813
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003814 err = skge_reset(hw);
3815 if (err)
3816 goto out;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003817
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003818 for (i = 0; i < hw->ports; i++) {
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003819 struct net_device *dev = hw->dev[i];
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003820
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003821 if (netif_running(dev)) {
3822 err = skge_up(dev);
3823
3824 if (err) {
3825 printk(KERN_ERR PFX "%s: could not up: %d\n",
3826 dev->name, err);
Stephen Hemmingeredd702e2005-12-15 12:18:00 -08003827 dev_close(dev);
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003828 goto out;
3829 }
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003830 }
3831 }
Stephen Hemmingerd38efdd2006-08-28 16:19:35 -07003832out:
3833 return err;
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003834}
3835#endif
3836
3837static struct pci_driver skge_driver = {
3838 .name = DRV_NAME,
3839 .id_table = skge_id_table,
3840 .probe = skge_probe,
3841 .remove = __devexit_p(skge_remove),
3842#ifdef CONFIG_PM
3843 .suspend = skge_suspend,
3844 .resume = skge_resume,
3845#endif
3846};
3847
3848static int __init skge_init_module(void)
3849{
Jeff Garzik29917622006-08-19 17:48:59 -04003850 return pci_register_driver(&skge_driver);
Stephen Hemmingerbaef58b2005-05-12 20:14:36 -04003851}
3852
3853static void __exit skge_cleanup_module(void)
3854{
3855 pci_unregister_driver(&skge_driver);
3856}
3857
3858module_init(skge_init_module);
3859module_exit(skge_cleanup_module);