Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #include "disassembler_arm.h" |
| 18 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 19 | #include <iostream> |
| 20 | |
Elliott Hughes | 07ed66b | 2012-12-12 18:34:25 -0800 | [diff] [blame] | 21 | #include "base/logging.h" |
Elliott Hughes | e222ee0 | 2012-12-13 14:41:43 -0800 | [diff] [blame] | 22 | #include "base/stringprintf.h" |
Elliott Hughes | 28fa76d | 2012-04-09 17:31:46 -0700 | [diff] [blame] | 23 | #include "thread.h" |
Elliott Hughes | 0f3c553 | 2012-03-30 14:51:51 -0700 | [diff] [blame] | 24 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 25 | namespace art { |
| 26 | namespace arm { |
| 27 | |
| 28 | DisassemblerArm::DisassemblerArm() { |
| 29 | } |
| 30 | |
Ian Rogers | b23a772 | 2012-10-09 16:54:26 -0700 | [diff] [blame] | 31 | size_t DisassemblerArm::Dump(std::ostream& os, const uint8_t* begin) { |
| 32 | if ((reinterpret_cast<intptr_t>(begin) & 1) == 0) { |
| 33 | DumpArm(os, begin); |
| 34 | return 4; |
| 35 | } else { |
| 36 | // remove thumb specifier bits |
| 37 | begin = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(begin) & ~1); |
| 38 | return DumpThumb16(os, begin); |
| 39 | } |
| 40 | } |
| 41 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 42 | void DisassemblerArm::Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) { |
| 43 | if ((reinterpret_cast<intptr_t>(begin) & 1) == 0) { |
| 44 | for (const uint8_t* cur = begin; cur < end; cur += 4) { |
| 45 | DumpArm(os, cur); |
| 46 | } |
| 47 | } else { |
| 48 | // remove thumb specifier bits |
| 49 | begin = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(begin) & ~1); |
| 50 | end = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(end) & ~1); |
| 51 | for (const uint8_t* cur = begin; cur < end;) { |
| 52 | cur += DumpThumb16(os, cur); |
| 53 | } |
| 54 | } |
| 55 | } |
| 56 | |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 57 | static const char* kConditionCodeNames[] = { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 58 | "eq", // 0000 - equal |
| 59 | "ne", // 0001 - not-equal |
| 60 | "cs", // 0010 - carry-set, greater than, equal or unordered |
| 61 | "cc", // 0011 - carry-clear, less than |
| 62 | "mi", // 0100 - minus, negative |
| 63 | "pl", // 0101 - plus, positive or zero |
| 64 | "vs", // 0110 - overflow |
| 65 | "vc", // 0111 - no overflow |
| 66 | "hi", // 1000 - unsigned higher |
| 67 | "ls", // 1001 - unsigned lower or same |
| 68 | "ge", // 1010 - signed greater than or equal |
| 69 | "lt", // 1011 - signed less than |
| 70 | "gt", // 1100 - signed greater than |
| 71 | "le", // 1101 - signed less than or equal |
| 72 | "", // 1110 - always |
| 73 | "nv", // 1111 - never (mostly obsolete, but might be a clue that we're mistranslating) |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 74 | }; |
| 75 | |
| 76 | void DisassemblerArm::DumpCond(std::ostream& os, uint32_t cond) { |
| 77 | if (cond < 15) { |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 78 | os << kConditionCodeNames[cond]; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 79 | } else { |
| 80 | os << "Unexpected condition: " << cond; |
| 81 | } |
| 82 | } |
| 83 | |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 84 | void DisassemblerArm::DumpBranchTarget(std::ostream& os, const uint8_t* instr_ptr, int32_t imm32) { |
Elliott Hughes | 1ca9849 | 2012-04-12 17:21:02 -0700 | [diff] [blame] | 85 | os << StringPrintf("%+d (%p)", imm32, instr_ptr + imm32); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 86 | } |
| 87 | |
| 88 | static uint32_t ReadU16(const uint8_t* ptr) { |
| 89 | return ptr[0] | (ptr[1] << 8); |
| 90 | } |
| 91 | |
| 92 | static uint32_t ReadU32(const uint8_t* ptr) { |
| 93 | return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24); |
| 94 | } |
| 95 | |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 96 | static const char* kDataProcessingOperations[] = { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 97 | "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", |
| 98 | "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn", |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 99 | }; |
| 100 | |
Ian Rogers | ad03ef5 | 2012-03-18 19:34:47 -0700 | [diff] [blame] | 101 | static const char* kThumbDataProcessingOperations[] = { |
| 102 | "and", "eor", "lsl", "lsr", "asr", "adc", "sbc", "ror", |
| 103 | "tst", "rsb", "cmp", "cmn", "orr", "mul", "bic", "mvn", |
| 104 | }; |
| 105 | |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 106 | struct ArmRegister { |
Elliott Hughes | 7484741 | 2012-06-20 18:10:21 -0700 | [diff] [blame] | 107 | explicit ArmRegister(uint32_t r) : r(r) { CHECK_LE(r, 15U); } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 108 | ArmRegister(uint32_t instruction, uint32_t at_bit) : r((instruction >> at_bit) & 0xf) { CHECK_LE(r, 15U); } |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 109 | uint32_t r; |
| 110 | }; |
| 111 | std::ostream& operator<<(std::ostream& os, const ArmRegister& r) { |
| 112 | if (r.r == 13) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 113 | os << "sp"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 114 | } else if (r.r == 14) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 115 | os << "lr"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 116 | } else if (r.r == 15) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 117 | os << "pc"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 118 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 119 | os << "r" << r.r; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 120 | } |
| 121 | return os; |
| 122 | } |
| 123 | |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 124 | struct ThumbRegister : ArmRegister { |
| 125 | ThumbRegister(uint16_t instruction, uint16_t at_bit) : ArmRegister((instruction >> at_bit) & 0x7) {} |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 126 | }; |
| 127 | |
| 128 | struct Rm { |
Elliott Hughes | 7484741 | 2012-06-20 18:10:21 -0700 | [diff] [blame] | 129 | explicit Rm(uint32_t instruction) : shift((instruction >> 4) & 0xff), rm(instruction & 0xf) {} |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 130 | uint32_t shift; |
| 131 | ArmRegister rm; |
| 132 | }; |
| 133 | std::ostream& operator<<(std::ostream& os, const Rm& r) { |
| 134 | os << r.rm; |
| 135 | if (r.shift != 0) { |
| 136 | os << "-shift-" << r.shift; // TODO |
| 137 | } |
| 138 | return os; |
| 139 | } |
| 140 | |
Elliott Hughes | 1ca9849 | 2012-04-12 17:21:02 -0700 | [diff] [blame] | 141 | struct ShiftedImmediate { |
Elliott Hughes | 7484741 | 2012-06-20 18:10:21 -0700 | [diff] [blame] | 142 | explicit ShiftedImmediate(uint32_t instruction) { |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 143 | uint32_t rotate = ((instruction >> 8) & 0xf); |
| 144 | uint32_t imm = (instruction & 0xff); |
| 145 | value = (imm >> (2 * rotate)) | (imm << (32 - (2 * rotate))); |
| 146 | } |
| 147 | uint32_t value; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 148 | }; |
Elliott Hughes | 1ca9849 | 2012-04-12 17:21:02 -0700 | [diff] [blame] | 149 | std::ostream& operator<<(std::ostream& os, const ShiftedImmediate& rhs) { |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 150 | os << "#" << rhs.value; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 151 | return os; |
| 152 | } |
| 153 | |
| 154 | struct RegisterList { |
Elliott Hughes | 7484741 | 2012-06-20 18:10:21 -0700 | [diff] [blame] | 155 | explicit RegisterList(uint32_t instruction) : register_list(instruction & 0xffff) {} |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 156 | uint32_t register_list; |
| 157 | }; |
| 158 | std::ostream& operator<<(std::ostream& os, const RegisterList& rhs) { |
| 159 | if (rhs.register_list == 0) { |
| 160 | os << "<no register list?>"; |
| 161 | return os; |
| 162 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 163 | os << "{"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 164 | bool first = true; |
| 165 | for (size_t i = 0; i < 16; i++) { |
| 166 | if ((rhs.register_list & (1 << i)) != 0) { |
| 167 | if (first) { |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 168 | first = false; |
| 169 | } else { |
| 170 | os << ", "; |
| 171 | } |
| 172 | os << ArmRegister(i); |
| 173 | } |
| 174 | } |
| 175 | os << "}"; |
| 176 | return os; |
| 177 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 178 | |
| 179 | void DisassemblerArm::DumpArm(std::ostream& os, const uint8_t* instr_ptr) { |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 180 | uint32_t instruction = ReadU32(instr_ptr); |
| 181 | uint32_t cond = (instruction >> 28) & 0xf; |
| 182 | uint32_t op1 = (instruction >> 25) & 0x7; |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 183 | std::string opcode; |
| 184 | std::string suffixes; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 185 | std::ostringstream args; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 186 | switch (op1) { |
| 187 | case 0: |
| 188 | case 1: // Data processing instructions. |
| 189 | { |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 190 | if ((instruction & 0x0ff000f0) == 0x01200070) { // BKPT |
| 191 | opcode = "bkpt"; |
| 192 | uint32_t imm12 = (instruction >> 8) & 0xfff; |
| 193 | uint32_t imm4 = (instruction & 0xf); |
| 194 | args << '#' << ((imm12 << 4) | imm4); |
| 195 | break; |
| 196 | } |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 197 | if ((instruction & 0x0fffffd0) == 0x012fff10) { // BX and BLX (register) |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 198 | opcode = (((instruction >> 5) & 1) ? "blx" : "bx"); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 199 | args << ArmRegister(instruction & 0xf); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 200 | break; |
| 201 | } |
| 202 | bool i = (instruction & (1 << 25)) != 0; |
| 203 | bool s = (instruction & (1 << 20)) != 0; |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 204 | uint32_t op = (instruction >> 21) & 0xf; |
| 205 | opcode = kDataProcessingOperations[op]; |
| 206 | bool implicit_s = ((op & ~3) == 8); // TST, TEQ, CMP, and CMN. |
| 207 | if (implicit_s) { |
| 208 | // Rd is unused (and not shown), and we don't show the 's' suffix either. |
| 209 | } else { |
| 210 | if (s) { |
| 211 | suffixes += 's'; |
| 212 | } |
| 213 | args << ArmRegister(instruction, 12) << ", "; |
| 214 | } |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 215 | if (i) { |
Elliott Hughes | 1ca9849 | 2012-04-12 17:21:02 -0700 | [diff] [blame] | 216 | args << ArmRegister(instruction, 16) << ", " << ShiftedImmediate(instruction); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 217 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 218 | args << Rm(instruction); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 219 | } |
| 220 | } |
| 221 | break; |
| 222 | case 2: // Load/store word and unsigned byte. |
| 223 | { |
| 224 | bool p = (instruction & (1 << 24)) != 0; |
| 225 | bool b = (instruction & (1 << 22)) != 0; |
| 226 | bool w = (instruction & (1 << 21)) != 0; |
| 227 | bool l = (instruction & (1 << 20)) != 0; |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 228 | opcode = StringPrintf("%s%s", (l ? "ldr" : "str"), (b ? "b" : "")); |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 229 | args << ArmRegister(instruction, 12) << ", "; |
| 230 | ArmRegister rn(instruction, 16); |
| 231 | if (rn.r == 0xf) { |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 232 | UNIMPLEMENTED(FATAL) << "literals"; |
| 233 | } else { |
| 234 | bool wback = !p || w; |
Elliott Hughes | 1ca9849 | 2012-04-12 17:21:02 -0700 | [diff] [blame] | 235 | uint32_t offset = (instruction & 0xfff); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 236 | if (p && !wback) { |
Elliott Hughes | 1ca9849 | 2012-04-12 17:21:02 -0700 | [diff] [blame] | 237 | args << "[" << rn << ", #" << offset << "]"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 238 | } else if (p && wback) { |
Elliott Hughes | 1ca9849 | 2012-04-12 17:21:02 -0700 | [diff] [blame] | 239 | args << "[" << rn << ", #" << offset << "]!"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 240 | } else if (!p && wback) { |
Elliott Hughes | 1ca9849 | 2012-04-12 17:21:02 -0700 | [diff] [blame] | 241 | args << "[" << rn << "], #" << offset; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 242 | } else { |
| 243 | LOG(FATAL) << p << " " << w; |
| 244 | } |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 245 | if (rn.r == 9) { |
| 246 | args << " ; "; |
Elliott Hughes | 1ca9849 | 2012-04-12 17:21:02 -0700 | [diff] [blame] | 247 | Thread::DumpThreadOffset(args, offset, 4); |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 248 | } |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 249 | } |
| 250 | } |
| 251 | break; |
| 252 | case 4: // Load/store multiple. |
| 253 | { |
| 254 | bool p = (instruction & (1 << 24)) != 0; |
| 255 | bool u = (instruction & (1 << 23)) != 0; |
| 256 | bool w = (instruction & (1 << 21)) != 0; |
| 257 | bool l = (instruction & (1 << 20)) != 0; |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 258 | opcode = StringPrintf("%s%c%c", (l ? "ldm" : "stm"), (u ? 'i' : 'd'), (p ? 'b' : 'a')); |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 259 | args << ArmRegister(instruction, 16) << (w ? "!" : "") << ", " << RegisterList(instruction); |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 260 | } |
| 261 | break; |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 262 | case 5: // Branch/branch with link. |
| 263 | { |
| 264 | bool bl = (instruction & (1 << 24)) != 0; |
| 265 | opcode = (bl ? "bl" : "b"); |
Elliott Hughes | d86261e | 2012-04-11 11:23:23 -0700 | [diff] [blame] | 266 | int32_t imm26 = (instruction & 0xffffff) << 2; |
| 267 | int32_t imm32 = (imm26 << 6) >> 6; // Sign extend. |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 268 | DumpBranchTarget(args, instr_ptr + 8, imm32); |
| 269 | } |
| 270 | break; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 271 | default: |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 272 | opcode = "???"; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 273 | break; |
| 274 | } |
Elliott Hughes | 3d71d07 | 2012-04-10 18:28:35 -0700 | [diff] [blame] | 275 | opcode += kConditionCodeNames[cond]; |
| 276 | opcode += suffixes; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 277 | // TODO: a more complete ARM disassembler could generate wider opcodes. |
Ian Rogers | 2bcb4a4 | 2012-11-08 10:39:18 -0800 | [diff] [blame] | 278 | os << StringPrintf("%p: %08x\t%-7s ", instr_ptr, instruction, opcode.c_str()) << args.str() << '\n'; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 279 | } |
| 280 | |
| 281 | size_t DisassemblerArm::DumpThumb32(std::ostream& os, const uint8_t* instr_ptr) { |
| 282 | uint32_t instr = (ReadU16(instr_ptr) << 16) | ReadU16(instr_ptr + 2); |
| 283 | // |111|1 1|1000000|0000|1111110000000000| |
| 284 | // |5 3|2 1|0987654|3 0|5 0 5 0| |
| 285 | // |---|---|-------|----|----------------| |
| 286 | // |332|2 2|2222222|1111|1111110000000000| |
| 287 | // |1 9|8 7|6543210|9 6|5 0 5 0| |
| 288 | // |---|---|-------|----|----------------| |
| 289 | // |111|op1| op2 | | | |
| 290 | uint32_t op1 = (instr >> 27) & 3; |
Elliott Hughes | 7740579 | 2012-03-15 15:22:12 -0700 | [diff] [blame] | 291 | if (op1 == 0) { |
| 292 | return DumpThumb16(os, instr_ptr); |
| 293 | } |
| 294 | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 295 | uint32_t op2 = (instr >> 20) & 0x7F; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 296 | std::ostringstream opcode; |
| 297 | std::ostringstream args; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 298 | switch (op1) { |
| 299 | case 0: |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 300 | break; |
| 301 | case 1: |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 302 | if ((op2 & 0x64) == 0) { // 00x x0xx |
| 303 | // |111|11|10|00|0|00|0000|1111110000000000| |
| 304 | // |5 3|21|09|87|6|54|3 0|5 0 5 0| |
| 305 | // |---|--|--|--|-|--|----|----------------| |
| 306 | // |332|22|22|22|2|22|1111|1111110000000000| |
| 307 | // |1 9|87|65|43|2|10|9 6|5 0 5 0| |
| 308 | // |---|--|--|--|-|--|----|----------------| |
| 309 | // |111|01|00|op|0|WL| Rn | | |
| 310 | // |111|01| op2 | | | |
| 311 | // STM - 111 01 00-01-0-W0 nnnn rrrrrrrrrrrrrrrr |
| 312 | // LDM - 111 01 00-01-0-W1 nnnn rrrrrrrrrrrrrrrr |
| 313 | // PUSH- 111 01 00-01-0-10 1101 0M0rrrrrrrrrrrrr |
| 314 | // POP - 111 01 00-01-0-11 1101 PM0rrrrrrrrrrrrr |
| 315 | uint32_t op = (instr >> 23) & 3; |
| 316 | uint32_t W = (instr >> 21) & 1; |
| 317 | uint32_t L = (instr >> 20) & 1; |
| 318 | ArmRegister Rn(instr, 16); |
| 319 | if (op == 1 || op == 2) { |
| 320 | if (op == 1) { |
| 321 | if (L == 0) { |
| 322 | opcode << "stm"; |
| 323 | args << Rn << (W == 0 ? "" : "!") << ", "; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 324 | } else { |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 325 | if (Rn.r != 13) { |
| 326 | opcode << "ldm"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 327 | args << Rn << (W == 0 ? "" : "!") << ", "; |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 328 | } else { |
| 329 | opcode << "pop"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 330 | } |
| 331 | } |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 332 | } else { |
| 333 | if (L == 0) { |
| 334 | if (Rn.r != 13) { |
| 335 | opcode << "stmdb"; |
| 336 | args << Rn << (W == 0 ? "" : "!") << ", "; |
| 337 | } else { |
| 338 | opcode << "push"; |
| 339 | } |
| 340 | } else { |
| 341 | opcode << "ldmdb"; |
| 342 | args << Rn << (W == 0 ? "" : "!") << ", "; |
| 343 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 344 | } |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 345 | args << RegisterList(instr); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 346 | } |
Ian Rogers | 9af8940 | 2012-09-07 11:29:35 -0700 | [diff] [blame] | 347 | } else if ((op2 & 0x64) == 4) { // 00x x1xx |
| 348 | uint32_t op3 = (instr >> 23) & 3; |
| 349 | uint32_t op4 = (instr >> 20) & 3; |
| 350 | //uint32_t op5 = (instr >> 4) & 0xF; |
| 351 | ArmRegister Rn(instr, 16); |
| 352 | ArmRegister Rt(instr, 12); |
| 353 | uint32_t imm8 = instr & 0xFF; |
| 354 | if (op3 == 0 && op4 == 0) { // STREX |
| 355 | ArmRegister Rd(instr, 8); |
| 356 | opcode << "strex"; |
| 357 | args << Rd << ", " << Rt << ", [" << Rn << ", #" << (imm8 << 2) << "]"; |
| 358 | } else if (op3 == 0 && op4 == 1) { // LDREX |
| 359 | opcode << "ldrex"; |
| 360 | args << Rt << ", [" << Rn << ", #" << (imm8 << 2) << "]"; |
| 361 | } |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 362 | } else if ((op2 & 0x60) == 0x20) { // 01x xxxx |
| 363 | // Data-processing (shifted register) |
| 364 | // |111|1110|0000|0|0000|1111|1100|0000|0000| |
| 365 | // |5 3|2109|8765|4|3 0|5 |10 8|7 5 |3 0| |
| 366 | // |---|----|----|-|----|----|----|----|----| |
| 367 | // |332|2222|2222|2|1111|1111|1100|0000|0000| |
| 368 | // |1 9|8765|4321|0|9 6|5 |10 8|7 5 |3 0| |
| 369 | // |---|----|----|-|----|----|----|----|----| |
| 370 | // |111|0101| op3|S| Rn | | Rd | | Rm | |
| 371 | uint32_t op3 = (instr >> 21) & 0xF; |
| 372 | uint32_t S = (instr >> 20) & 1; |
| 373 | uint32_t Rn = (instr >> 16) & 0xF; |
| 374 | ArmRegister Rd(instr, 8); |
| 375 | ArmRegister Rm(instr, 0); |
| 376 | switch (op3) { |
| 377 | case 0x0: |
| 378 | if (Rn != 0xF) { |
| 379 | opcode << "and"; |
| 380 | } else { |
| 381 | opcode << "tst"; |
| 382 | S = 0; // don't print 's' |
| 383 | } |
| 384 | break; |
| 385 | case 0x1: opcode << "bic"; break; |
| 386 | case 0x2: |
| 387 | if (Rn != 0xF) { |
| 388 | opcode << "orr"; |
| 389 | } else { |
| 390 | opcode << "mov"; |
| 391 | } |
| 392 | break; |
| 393 | case 0x3: |
| 394 | if (Rn != 0xF) { |
| 395 | opcode << "orn"; |
| 396 | } else { |
| 397 | opcode << "mvn"; |
| 398 | } |
| 399 | break; |
| 400 | case 0x4: |
| 401 | if (Rn != 0xF) { |
| 402 | opcode << "eor"; |
| 403 | } else { |
| 404 | opcode << "teq"; |
| 405 | S = 0; // don't print 's' |
| 406 | } |
| 407 | break; |
| 408 | case 0x6: opcode << "pkh"; break; |
| 409 | case 0x8: |
| 410 | if (Rn != 0xF) { |
| 411 | opcode << "add"; |
| 412 | } else { |
| 413 | opcode << "cmn"; |
| 414 | S = 0; // don't print 's' |
| 415 | } |
| 416 | break; |
| 417 | case 0xA: opcode << "adc"; break; |
| 418 | case 0xB: opcode << "sbc"; break; |
| 419 | } |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 420 | |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 421 | if (S == 1) { |
| 422 | opcode << "s"; |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 423 | } |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 424 | opcode << ".w"; |
| 425 | args << Rd << ", " << Rm; |
| 426 | } else if ((op2 & 0x40) == 0x40) { // 1xx xxxx |
| 427 | // Co-processor instructions |
| 428 | // |111|1|11|000000|0000|1111|1100|000|0 |0000| |
| 429 | // |5 3|2|10|987654|3 0|54 2|10 8|7 5|4 | 0| |
| 430 | // |---|-|--|------|----|----|----|---|---|----| |
| 431 | // |332|2|22|222222|1111|1111|1100|000|0 |0000| |
| 432 | // |1 9|8|76|543210|9 6|54 2|10 8|7 5|4 | 0| |
| 433 | // |---|-|--|------|----|----|----|---|---|----| |
| 434 | // |111| |11| op3 | Rn | |copr| |op4| | |
| 435 | uint32_t op3 = (instr >> 20) & 0x3F; |
| 436 | uint32_t coproc = (instr >> 8) & 0xF; |
| 437 | uint32_t op4 = (instr >> 4) & 0x1; |
Ian Rogers | 9af8940 | 2012-09-07 11:29:35 -0700 | [diff] [blame] | 438 | if ((op3 == 2 || op3 == 2 || op3 == 6 || op3 == 7) || // 00x1x |
| 439 | (op3 >= 8 && op3 <= 15) || (op3 >= 16 && op3 <= 31)) { // 001xxx, 01xxxx |
| 440 | // Extension register load/store instructions |
| 441 | // |111|1|110|00000|0000|1111|110|000000000| |
| 442 | // |5 3|2|109|87654|3 0|54 2|10 |87 54 0| |
| 443 | // |---|-|---|-----|----|----|---|---------| |
| 444 | // |332|2|222|22222|1111|1111|110|000000000| |
| 445 | // |1 9|8|765|43210|9 6|54 2|10 |87 54 0| |
| 446 | // |---|-|---|-----|----|----|---|---------| |
| 447 | // |111|T|110| op3 | Rn | |101| | |
| 448 | // 111 0 110 01001 0011 0000 101 000000011 - ec930a03 |
| 449 | if (op3 == 9 || op3 == 0xD) { // VLDM |
| 450 | // 1110 110 PUDW1 nnnn dddd 101S iiii iiii |
| 451 | uint32_t P = (instr >> 24) & 1; |
| 452 | uint32_t U = (instr >> 23) & 1; |
| 453 | uint32_t D = (instr >> 22) & 1; |
| 454 | uint32_t W = (instr >> 21) & 1; |
| 455 | uint32_t S = (instr >> 8) & 1; |
| 456 | ArmRegister Rn(instr, 16); |
| 457 | uint32_t Vd = (instr >> 12) & 0xF; |
| 458 | uint32_t imm8 = instr & 0xFF; |
| 459 | uint32_t d = (S == 0 ? ((Vd << 1) | D) : (Vd | (D << 4))); |
| 460 | if (P == 0 && U == 0 && W == 0) { |
| 461 | // TODO: 64bit transfers between ARM core and extension registers. |
| 462 | } else if (P == 0 && U == 1 && Rn.r == 13) { // VPOP |
| 463 | opcode << "vpop" << (S == 0 ? ".f64" : ".f32"); |
| 464 | args << d << " .. " << (d + imm8); |
| 465 | } else if (P == 1 && W == 0) { // VLDR |
| 466 | opcode << "vldr" << (S == 0 ? ".f64" : ".f32"); |
| 467 | args << d << ", [" << Rn << ", #" << imm8 << "]"; |
| 468 | } else { // VLDM |
| 469 | opcode << "vldm" << (S == 0 ? ".f64" : ".f32"); |
| 470 | args << Rn << ", " << d << " .. " << (d + imm8); |
| 471 | } |
| 472 | } |
Ian Rogers | 0183dd7 | 2012-09-17 23:06:51 -0700 | [diff] [blame] | 473 | } else if ((op3 & 0x30) == 0x20 && op4 == 0) { // 10 xxxx ... 0 |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 474 | if ((coproc & 0xE) == 0xA) { |
| 475 | // VFP data-processing instructions |
| 476 | // |111|1|1100|0000|0000|1111|110|0|00 |0|0|0000| |
| 477 | // |5 3|2|1098|7654|3 0|54 2|10 |8|76 |5|4|3 0| |
| 478 | // |---|-|----|----|----|----|---|-|----|-|-|----| |
| 479 | // |332|2|2222|2222|1111|1111|110|0|00 |0|0|0000| |
| 480 | // |1 9|8|7654|3210|9 6|54 2|109|8|76 |5|4|3 0| |
| 481 | // |---|-|----|----|----|----|---|-|----|-|-|----| |
| 482 | // |111|T|1110|opc1|opc2| |101| |opc3| | | | |
| 483 | // 111 0 1110|1111 0100 1110 101 0 01 1 0 1001 - eef4ea69 |
| 484 | uint32_t opc1 = (instr >> 20) & 0xF; |
| 485 | uint32_t opc2 = (instr >> 16) & 0xF; |
Ian Rogers | 0183dd7 | 2012-09-17 23:06:51 -0700 | [diff] [blame] | 486 | uint32_t opc3 = (instr >> 6) & 0x3; |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 487 | if ((opc1 & 0xB) == 0xB) { // 1x11 |
| 488 | // Other VFP data-processing instructions. |
Ian Rogers | 0183dd7 | 2012-09-17 23:06:51 -0700 | [diff] [blame] | 489 | uint32_t D = (instr >> 22) & 0x1; |
| 490 | uint32_t Vd = (instr >> 12) & 0xF; |
| 491 | uint32_t sz = (instr >> 8) & 1; |
| 492 | uint32_t M = (instr >> 5) & 1; |
| 493 | uint32_t Vm = instr & 0xF; |
| 494 | bool dp_operation = sz == 1; |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 495 | switch (opc2) { |
Ian Rogers | 0183dd7 | 2012-09-17 23:06:51 -0700 | [diff] [blame] | 496 | case 0x1: // Vneg/Vsqrt |
| 497 | // 1110 11101 D 11 0001 dddd 101s o1M0 mmmm |
| 498 | opcode << (opc3 == 1 ? "vneg" : "vsqrt") << (dp_operation ? ".f64" : ".f32"); |
| 499 | if (dp_operation) { |
| 500 | args << "f" << ((D << 4) | Vd) << ", " << "f" << ((M << 4) | Vm); |
| 501 | } else { |
| 502 | args << "f" << ((Vd << 1) | D) << ", " << "f" << ((Vm << 1) | M); |
| 503 | } |
| 504 | break; |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 505 | case 0x4: case 0x5: { // Vector compare |
| 506 | // 1110 11101 D 11 0100 dddd 101 sE1M0 mmmm |
Ian Rogers | 0183dd7 | 2012-09-17 23:06:51 -0700 | [diff] [blame] | 507 | opcode << (opc3 == 1 ? "vcmp" : "vcmpe") << (dp_operation ? ".f64" : ".f32"); |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 508 | if (dp_operation) { |
| 509 | args << "f" << ((D << 4) | Vd) << ", " << "f" << ((M << 4) | Vm); |
| 510 | } else { |
| 511 | args << "f" << ((Vd << 1) | D) << ", " << "f" << ((Vm << 1) | M); |
| 512 | } |
| 513 | break; |
| 514 | } |
| 515 | } |
| 516 | } |
| 517 | } |
Ian Rogers | 0183dd7 | 2012-09-17 23:06:51 -0700 | [diff] [blame] | 518 | } else if ((op3 & 0x30) == 0x30) { // 11 xxxx |
| 519 | // Advanced SIMD |
| 520 | if ((instr & 0xFFBF0ED0) == 0xeeb10ac0) { // Vsqrt |
| 521 | // 1110 11101 D 11 0001 dddd 101S 11M0 mmmm |
| 522 | // 1110 11101 0 11 0001 1101 1011 1100 1000 - eeb1dbc8 |
| 523 | uint32_t D = (instr >> 22) & 1; |
| 524 | uint32_t Vd = (instr >> 12) & 0xF; |
| 525 | uint32_t sz = (instr >> 8) & 1; |
| 526 | uint32_t M = (instr >> 5) & 1; |
| 527 | uint32_t Vm = instr & 0xF; |
| 528 | bool dp_operation = sz == 1; |
| 529 | opcode << "vsqrt" << (dp_operation ? ".f64" : ".f32"); |
| 530 | if (dp_operation) { |
| 531 | args << "f" << ((D << 4) | Vd) << ", " << "f" << ((M << 4) | Vm); |
| 532 | } else { |
| 533 | args << "f" << ((Vd << 1) | D) << ", " << "f" << ((Vm << 1) | M); |
| 534 | } |
| 535 | } |
Ian Rogers | c7fe4e0 | 2012-03-29 21:36:21 -0700 | [diff] [blame] | 536 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 537 | } |
| 538 | break; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 539 | case 2: |
| 540 | if ((instr & 0x8000) == 0 && (op2 & 0x20) == 0) { |
| 541 | // Data-processing (modified immediate) |
| 542 | // |111|11|10|0000|0|0000|1|111|1100|00000000| |
| 543 | // |5 3|21|09|8765|4|3 0|5|4 2|10 8|7 5 0| |
| 544 | // |---|--|--|----|-|----|-|---|----|--------| |
| 545 | // |332|22|22|2222|2|1111|1|111|1100|00000000| |
| 546 | // |1 9|87|65|4321|0|9 6|5|4 2|10 8|7 5 0| |
| 547 | // |---|--|--|----|-|----|-|---|----|--------| |
| 548 | // |111|10|i0| op3|S| Rn |0|iii| Rd |iiiiiiii| |
| 549 | // 111 10 x0 xxxx x xxxx opxxx xxxx xxxxxxxx |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 550 | uint32_t i = (instr >> 26) & 1; |
| 551 | uint32_t op3 = (instr >> 21) & 0xF; |
| 552 | uint32_t S = (instr >> 20) & 1; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 553 | ArmRegister Rn(instr, 16); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 554 | uint32_t imm3 = (instr >> 12) & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 555 | ArmRegister Rd(instr, 8); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 556 | uint32_t imm8 = instr & 0xFF; |
Jeff Hao | 7cb0f9c | 2013-02-04 16:15:27 -0800 | [diff] [blame] | 557 | int32_t imm32 = (i << 11) | (imm3 << 8) | imm8; |
| 558 | if (Rn.r == 0xF && (op3 == 0x2 || op3 == 0x3)) { |
| 559 | if (op3 == 0x2) { |
| 560 | opcode << "mov"; |
| 561 | if (S == 1) { |
| 562 | opcode << "s"; |
| 563 | } |
| 564 | opcode << ".w"; |
| 565 | } else { |
| 566 | opcode << "mvn"; |
| 567 | if (S == 1) { |
| 568 | opcode << "s"; |
| 569 | } |
| 570 | } |
| 571 | args << Rd << ", ThumbExpand(" << imm32 << ")"; |
| 572 | } else if (Rd.r == 0xF && S == 1 && |
| 573 | (op3 == 0x0 || op3 == 0x4 || op3 == 0x8 || op3 == 0xD)) { |
| 574 | if (op3 == 0x0) { |
| 575 | opcode << "tst"; |
| 576 | } else if (op3 == 0x4) { |
| 577 | opcode << "teq"; |
| 578 | } else if (op3 == 0x8) { |
| 579 | opcode << "cmw"; |
| 580 | } else { |
| 581 | opcode << "cmp.w"; |
| 582 | } |
| 583 | args << Rn << ", ThumbExpand(" << imm32 << ")"; |
| 584 | } else { |
| 585 | switch (op3) { |
| 586 | case 0x0: opcode << "and"; break; |
| 587 | case 0x1: opcode << "bic"; break; |
| 588 | case 0x2: opcode << "orr"; break; |
| 589 | case 0x3: opcode << "orn"; break; |
| 590 | case 0x4: opcode << "eor"; break; |
| 591 | case 0x8: opcode << "add"; break; |
| 592 | case 0xA: opcode << "adc"; break; |
| 593 | case 0xB: opcode << "sbc"; break; |
| 594 | case 0xD: opcode << "sub"; break; |
| 595 | case 0xE: opcode << "rsb"; break; |
| 596 | default: opcode << "UNKNOWN DPMI-" << op3; break; |
| 597 | } |
| 598 | if (S == 1) { |
| 599 | opcode << "s"; |
| 600 | } |
| 601 | args << Rd << ", " << Rn << ", ThumbExpand(" << imm32 << ")"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 602 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 603 | } else if ((instr & 0x8000) == 0 && (op2 & 0x20) != 0) { |
| 604 | // Data-processing (plain binary immediate) |
| 605 | // |111|11|10|00000|0000|1|111110000000000| |
| 606 | // |5 3|21|09|87654|3 0|5|4 0 5 0| |
| 607 | // |---|--|--|-----|----|-|---------------| |
| 608 | // |332|22|22|22222|1111|1|111110000000000| |
| 609 | // |1 9|87|65|43210|9 6|5|4 0 5 0| |
| 610 | // |---|--|--|-----|----|-|---------------| |
| 611 | // |111|10|x1| op3 | Rn |0|xxxxxxxxxxxxxxx| |
| 612 | uint32_t op3 = (instr >> 20) & 0x1F; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 613 | switch (op3) { |
Ian Rogers | 5501913 | 2013-02-08 01:05:23 -0800 | [diff] [blame^] | 614 | case 0x00: case 0x0A: { |
| 615 | // ADD/SUB.W Rd, Rn #imm12 - 111 10 i1 0101 0 nnnn 0 iii dddd iiiiiiii |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 616 | ArmRegister Rd(instr, 8); |
| 617 | ArmRegister Rn(instr, 16); |
| 618 | uint32_t i = (instr >> 26) & 1; |
| 619 | uint32_t imm3 = (instr >> 12) & 0x7; |
| 620 | uint32_t imm8 = instr & 0xFF; |
| 621 | uint32_t imm12 = (i << 11) | (imm3 << 8) | imm8; |
| 622 | if (Rn.r != 0xF) { |
Ian Rogers | 5501913 | 2013-02-08 01:05:23 -0800 | [diff] [blame^] | 623 | opcode << (op3 == 0 ? "addw" : "subw"); |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 624 | args << Rd << ", " << Rn << ", #" << imm12; |
| 625 | } else { |
| 626 | opcode << "adr"; |
| 627 | args << Rd << ", "; |
Ian Rogers | 5501913 | 2013-02-08 01:05:23 -0800 | [diff] [blame^] | 628 | DumpBranchTarget(args, instr_ptr + 4, (op3 == 0) ? imm12 : -imm12); |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 629 | } |
| 630 | break; |
| 631 | } |
Ian Rogers | 5501913 | 2013-02-08 01:05:23 -0800 | [diff] [blame^] | 632 | case 0x04: case 0x0C: { |
| 633 | // MOVW/T Rd, #imm16 - 111 10 i0 0010 0 iiii 0 iii dddd iiiiiiii |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 634 | ArmRegister Rd(instr, 8); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 635 | uint32_t i = (instr >> 26) & 1; |
| 636 | uint32_t imm3 = (instr >> 12) & 0x7; |
| 637 | uint32_t imm8 = instr & 0xFF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 638 | uint32_t Rn = (instr >> 16) & 0xF; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 639 | uint32_t imm16 = (Rn << 12) | (i << 11) | (imm3 << 8) | imm8; |
Ian Rogers | 5501913 | 2013-02-08 01:05:23 -0800 | [diff] [blame^] | 640 | opcode << (op3 == 0x04 ? "movw" : "movt"); |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 641 | args << Rd << ", #" << imm16; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 642 | break; |
| 643 | } |
jeffhao | eae2691 | 2013-01-28 16:29:54 -0800 | [diff] [blame] | 644 | case 0x16: { |
| 645 | // BFI Rd, Rn, #lsb, #width - 111 10 0 11 011 0 nnnn 0 iii dddd ii 0 iiiii |
| 646 | ArmRegister Rd(instr, 8); |
| 647 | ArmRegister Rn(instr, 16); |
| 648 | uint32_t msb = instr & 0x1F; |
| 649 | uint32_t imm2 = (instr >> 6) & 0x3; |
| 650 | uint32_t imm3 = (instr >> 12) & 0x7; |
| 651 | uint32_t lsb = (imm3 << 2) | imm2; |
| 652 | uint32_t width = msb - lsb + 1; |
| 653 | if (Rn.r != 0xF) { |
| 654 | opcode << "bfi"; |
| 655 | args << Rd << ", " << Rn << ", #" << lsb << ", #" << width; |
| 656 | } else { |
| 657 | opcode << "bfc"; |
| 658 | args << Rd << ", #" << lsb << ", #" << width; |
| 659 | } |
| 660 | break; |
| 661 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 662 | default: |
| 663 | break; |
| 664 | } |
| 665 | } else { |
| 666 | // Branches and miscellaneous control |
| 667 | // |111|11|1000000|0000|1|111|1100|00000000| |
| 668 | // |5 3|21|0987654|3 0|5|4 2|10 8|7 5 0| |
| 669 | // |---|--|-------|----|-|---|----|--------| |
| 670 | // |332|22|2222222|1111|1|111|1100|00000000| |
| 671 | // |1 9|87|6543210|9 6|5|4 2|10 8|7 5 0| |
| 672 | // |---|--|-------|----|-|---|----|--------| |
| 673 | // |111|10| op2 | |1|op3|op4 | | |
| 674 | |
| 675 | uint32_t op3 = (instr >> 12) & 7; |
| 676 | //uint32_t op4 = (instr >> 8) & 0xF; |
| 677 | switch (op3) { |
| 678 | case 0: |
| 679 | if ((op2 & 0x38) != 0x38) { |
| 680 | // Conditional branch |
| 681 | // |111|11|1|0000|000000|1|1|1 |1|1 |10000000000| |
| 682 | // |5 3|21|0|9876|543 0|5|4|3 |2|1 |0 5 0| |
| 683 | // |---|--|-|----|------|-|-|--|-|--|-----------| |
| 684 | // |332|22|2|2222|221111|1|1|1 |1|1 |10000000000| |
| 685 | // |1 9|87|6|5432|109 6|5|4|3 |2|1 |0 5 0| |
| 686 | // |---|--|-|----|------|-|-|--|-|--|-----------| |
| 687 | // |111|10|S|cond| imm6 |1|0|J1|0|J2| imm11 | |
| 688 | uint32_t S = (instr >> 26) & 1; |
| 689 | uint32_t J2 = (instr >> 11) & 1; |
| 690 | uint32_t J1 = (instr >> 13) & 1; |
| 691 | uint32_t imm6 = (instr >> 16) & 0x3F; |
| 692 | uint32_t imm11 = instr & 0x7FF; |
| 693 | uint32_t cond = (instr >> 22) & 0xF; |
| 694 | int32_t imm32 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1); |
| 695 | imm32 = (imm32 << 11) >> 11; // sign extend 21bit immediate |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 696 | opcode << "b"; |
| 697 | DumpCond(opcode, cond); |
| 698 | opcode << ".w"; |
| 699 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
Ian Rogers | 9af8940 | 2012-09-07 11:29:35 -0700 | [diff] [blame] | 700 | } else if (op2 == 0x3B) { |
| 701 | // Miscellaneous control instructions |
| 702 | uint32_t op5 = (instr >> 4) & 0xF; |
| 703 | switch (op5) { |
| 704 | case 4: opcode << "dsb"; break; |
| 705 | case 5: opcode << "dmb"; break; |
| 706 | case 6: opcode << "isb"; break; |
| 707 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 708 | } |
| 709 | break; |
| 710 | case 2: |
| 711 | case 1: case 3: |
| 712 | break; |
| 713 | case 4: case 6: case 5: case 7: { |
| 714 | // BL, BLX (immediate) |
| 715 | // |111|11|1|0000000000|11|1 |1|1 |10000000000| |
| 716 | // |5 3|21|0|9876543 0|54|3 |2|1 |0 5 0| |
| 717 | // |---|--|-|----------|--|--|-|--|-----------| |
| 718 | // |332|22|2|2222221111|11|1 |1|1 |10000000000| |
| 719 | // |1 9|87|6|5 0 6|54|3 |2|1 |0 5 0| |
| 720 | // |---|--|-|----------|--|--|-|--|-----------| |
| 721 | // |111|10|S| imm10 |11|J1|L|J2| imm11 | |
| 722 | uint32_t S = (instr >> 26) & 1; |
| 723 | uint32_t J2 = (instr >> 11) & 1; |
| 724 | uint32_t L = (instr >> 12) & 1; |
| 725 | uint32_t J1 = (instr >> 13) & 1; |
| 726 | uint32_t imm10 = (instr >> 16) & 0x3FF; |
| 727 | uint32_t imm11 = instr & 0x7FF; |
| 728 | if (L == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 729 | opcode << "bx"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 730 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 731 | opcode << "blx"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 732 | } |
| 733 | uint32_t I1 = ~(J1 ^ S); |
| 734 | uint32_t I2 = ~(J2 ^ S); |
| 735 | int32_t imm32 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1); |
| 736 | imm32 = (imm32 << 8) >> 8; // sign extend 24 bit immediate. |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 737 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 738 | break; |
| 739 | } |
| 740 | } |
| 741 | } |
| 742 | break; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 743 | case 3: |
| 744 | switch (op2) { |
| 745 | case 0x00: case 0x02: case 0x04: case 0x06: // 000xxx0 |
| 746 | case 0x08: case 0x0A: case 0x0C: case 0x0E: { |
| 747 | // Store single data item |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 748 | // |111|11|100|000|0|0000|1111|110000|000000| |
| 749 | // |5 3|21|098|765|4|3 0|5 2|10 6|5 0| |
| 750 | // |---|--|---|---|-|----|----|------|------| |
| 751 | // |332|22|222|222|2|1111|1111|110000|000000| |
| 752 | // |1 9|87|654|321|0|9 6|5 2|10 6|5 0| |
| 753 | // |---|--|---|---|-|----|----|------|------| |
| 754 | // |111|11|000|op3|0| | | op4 | | |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 755 | uint32_t op3 = (instr >> 21) & 7; |
| 756 | //uint32_t op4 = (instr >> 6) & 0x3F; |
| 757 | switch (op3) { |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 758 | case 0x0: case 0x4: { |
| 759 | // STRB Rt,[Rn,#+/-imm8] - 111 11 00 0 0 00 0 nnnn tttt 1 PUWii ii iiii |
| 760 | // STRB Rt,[Rn,Rm,lsl #imm2] - 111 11 00 0 0 00 0 nnnn tttt 0 00000 ii mmmm |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 761 | ArmRegister Rn(instr, 16); |
| 762 | ArmRegister Rt(instr, 12); |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 763 | opcode << "strb"; |
| 764 | if ((instr & 0x800) != 0) { |
| 765 | uint32_t imm8 = instr & 0xFF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 766 | args << Rt << ", [" << Rn << ",#" << imm8 << "]"; |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 767 | } else { |
| 768 | uint32_t imm2 = (instr >> 4) & 3; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 769 | ArmRegister Rm(instr, 0); |
| 770 | args << Rt << ", [" << Rn << ", " << Rm; |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 771 | if (imm2 != 0) { |
| 772 | args << ", " << "lsl #" << imm2; |
| 773 | } |
| 774 | args << "]"; |
| 775 | } |
| 776 | break; |
| 777 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 778 | case 0x2: case 0x6: { |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 779 | ArmRegister Rn(instr, 16); |
| 780 | ArmRegister Rt(instr, 12); |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 781 | if (op3 == 2) { |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 782 | if ((instr & 0x800) != 0) { |
| 783 | // STR Rt, [Rn, #imm8] - 111 11 000 010 0 nnnn tttt 1PUWiiiiiiii |
| 784 | uint32_t P = (instr >> 10) & 1; |
| 785 | uint32_t U = (instr >> 9) & 1; |
| 786 | uint32_t W = (instr >> 8) & 1; |
| 787 | uint32_t imm8 = instr & 0xFF; |
| 788 | int32_t imm32 = (imm8 << 24) >> 24; // sign-extend imm8 |
| 789 | if (Rn.r == 13 && P == 1 && U == 0 && W == 1 && imm32 == 4) { |
| 790 | opcode << "push"; |
| 791 | args << Rt; |
| 792 | } else if (Rn.r == 15 || (P == 0 && W == 0)) { |
| 793 | opcode << "UNDEFINED"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 794 | } else { |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 795 | if (P == 1 && U == 1 && W == 0) { |
| 796 | opcode << "strt"; |
| 797 | } else { |
| 798 | opcode << "str"; |
| 799 | } |
| 800 | args << Rt << ", [" << Rn; |
| 801 | if (P == 0 && W == 1) { |
| 802 | args << "], #" << imm32; |
| 803 | } else { |
| 804 | args << ", #" << imm32 << "]"; |
| 805 | if (W == 1) { |
| 806 | args << "!"; |
| 807 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 808 | } |
| 809 | } |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 810 | } else { |
| 811 | // STR Rt, [Rn, Rm, LSL #imm2] - 111 11 000 010 0 nnnn tttt 000000iimmmm |
| 812 | ArmRegister Rn(instr, 16); |
| 813 | ArmRegister Rt(instr, 12); |
| 814 | ArmRegister Rm(instr, 0); |
| 815 | uint32_t imm2 = (instr >> 4) & 3; |
| 816 | opcode << "str.w"; |
| 817 | args << Rt << ", [" << Rn << ", " << Rm; |
| 818 | if (imm2 != 0) { |
| 819 | args << ", lsl #" << imm2; |
| 820 | } |
| 821 | args << "]"; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 822 | } |
| 823 | } else if (op3 == 6) { |
Ian Rogers | 66a3fca | 2012-04-09 19:51:34 -0700 | [diff] [blame] | 824 | // STR.W Rt, [Rn, #imm12] - 111 11 000 110 0 nnnn tttt iiiiiiiiiiii |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 825 | uint32_t imm12 = instr & 0xFFF; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 826 | opcode << "str.w"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 827 | args << Rt << ", [" << Rn << ", #" << imm12 << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 828 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 829 | break; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 830 | } |
| 831 | } |
| 832 | |
| 833 | break; |
| 834 | } |
jeffhao | eae2691 | 2013-01-28 16:29:54 -0800 | [diff] [blame] | 835 | case 0x03: case 0x0B: case 0x13: case 0x1B: { // 00xx011 |
| 836 | // Load halfword |
| 837 | // |111|11|10|0 0|00|0|0000|1111|110000|000000| |
| 838 | // |5 3|21|09|8 7|65|4|3 0|5 2|10 6|5 0| |
| 839 | // |---|--|--|---|--|-|----|----|------|------| |
| 840 | // |332|22|22|2 2|22|2|1111|1111|110000|000000| |
| 841 | // |1 9|87|65|4 3|21|0|9 6|5 2|10 6|5 0| |
| 842 | // |---|--|--|---|--|-|----|----|------|------| |
| 843 | // |111|11|00|op3|01|1| Rn | Rt | op4 | | |
| 844 | // |111|11| op2 | | | imm12 | |
| 845 | uint32_t op3 = (instr >> 23) & 3; |
| 846 | ArmRegister Rn(instr, 16); |
| 847 | ArmRegister Rt(instr, 12); |
| 848 | if (Rt.r != 15) { |
| 849 | if (op3 == 1) { |
| 850 | // LDRH.W Rt, [Rn, #imm12] - 111 11 00 01 011 nnnn tttt iiiiiiiiiiii |
| 851 | uint32_t imm12 = instr & 0xFFF; |
| 852 | opcode << "ldrh.w"; |
| 853 | args << Rt << ", [" << Rn << ", #" << imm12 << "]"; |
| 854 | if (Rn.r == 9) { |
| 855 | args << " ; "; |
| 856 | Thread::DumpThreadOffset(args, imm12, 4); |
| 857 | } else if (Rn.r == 15) { |
| 858 | intptr_t lit_adr = reinterpret_cast<intptr_t>(instr_ptr); |
| 859 | lit_adr = RoundDown(lit_adr, 4) + 4 + imm12; |
| 860 | args << " ; " << reinterpret_cast<void*>(*reinterpret_cast<int32_t*>(lit_adr)); |
| 861 | } |
| 862 | } else if (op3 == 3) { |
| 863 | // LDRSH.W Rt, [Rn, #imm12] - 111 11 00 11 011 nnnn tttt iiiiiiiiiiii |
| 864 | uint32_t imm12 = instr & 0xFFF; |
| 865 | opcode << "ldrsh.w"; |
| 866 | args << Rt << ", [" << Rn << ", #" << imm12 << "]"; |
| 867 | if (Rn.r == 9) { |
| 868 | args << " ; "; |
| 869 | Thread::DumpThreadOffset(args, imm12, 4); |
| 870 | } else if (Rn.r == 15) { |
| 871 | intptr_t lit_adr = reinterpret_cast<intptr_t>(instr_ptr); |
| 872 | lit_adr = RoundDown(lit_adr, 4) + 4 + imm12; |
| 873 | args << " ; " << reinterpret_cast<void*>(*reinterpret_cast<int32_t*>(lit_adr)); |
| 874 | } |
| 875 | } |
| 876 | } |
| 877 | break; |
| 878 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 879 | case 0x05: case 0x0D: case 0x15: case 0x1D: { // 00xx101 |
| 880 | // Load word |
| 881 | // |111|11|10|0 0|00|0|0000|1111|110000|000000| |
| 882 | // |5 3|21|09|8 7|65|4|3 0|5 2|10 6|5 0| |
| 883 | // |---|--|--|---|--|-|----|----|------|------| |
| 884 | // |332|22|22|2 2|22|2|1111|1111|110000|000000| |
| 885 | // |1 9|87|65|4 3|21|0|9 6|5 2|10 6|5 0| |
| 886 | // |---|--|--|---|--|-|----|----|------|------| |
| 887 | // |111|11|00|op3|10|1| Rn | Rt | op4 | | |
| 888 | // |111|11| op2 | | | imm12 | |
| 889 | uint32_t op3 = (instr >> 23) & 3; |
| 890 | uint32_t op4 = (instr >> 6) & 0x3F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 891 | ArmRegister Rn(instr, 16); |
| 892 | ArmRegister Rt(instr, 12); |
| 893 | if (op3 == 1 || Rn.r == 15) { |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 894 | // LDR.W Rt, [Rn, #imm12] - 111 11 00 00 101 nnnn tttt iiiiiiiiiiii |
| 895 | // LDR.W Rt, [PC, #imm12] - 111 11 00 0x 101 1111 tttt iiiiiiiiiiii |
| 896 | uint32_t imm12 = instr & 0xFFF; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 897 | opcode << "ldr.w"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 898 | args << Rt << ", [" << Rn << ", #" << imm12 << "]"; |
Elliott Hughes | 28fa76d | 2012-04-09 17:31:46 -0700 | [diff] [blame] | 899 | if (Rn.r == 9) { |
| 900 | args << " ; "; |
| 901 | Thread::DumpThreadOffset(args, imm12, 4); |
Ian Rogers | 5b9b1bc | 2012-04-09 22:51:43 -0700 | [diff] [blame] | 902 | } else if (Rn.r == 15) { |
| 903 | intptr_t lit_adr = reinterpret_cast<intptr_t>(instr_ptr); |
| 904 | lit_adr = RoundDown(lit_adr, 4) + 4 + imm12; |
| 905 | args << " ; " << reinterpret_cast<void*>(*reinterpret_cast<int32_t*>(lit_adr)); |
Elliott Hughes | 28fa76d | 2012-04-09 17:31:46 -0700 | [diff] [blame] | 906 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 907 | } else if (op4 == 0) { |
| 908 | // LDR.W Rt, [Rn, Rm{, LSL #imm2}] - 111 11 00 00 101 nnnn tttt 000000iimmmm |
| 909 | uint32_t imm2 = (instr >> 4) & 0xF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 910 | ArmRegister rm(instr, 0); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 911 | opcode << "ldr.w"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 912 | args << Rt << ", [" << Rn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 913 | if (imm2 != 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 914 | args << ", lsl #" << imm2; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 915 | } |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 916 | args << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 917 | } else { |
| 918 | // LDRT Rt, [Rn, #imm8] - 111 11 00 00 101 nnnn tttt 1110iiiiiiii |
| 919 | uint32_t imm8 = instr & 0xFF; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 920 | opcode << "ldrt"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 921 | args << Rt << ", [" << Rn << ", #" << imm8 << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 922 | } |
| 923 | break; |
| 924 | } |
| 925 | } |
| 926 | default: |
| 927 | break; |
| 928 | } |
Ian Rogers | 9af8940 | 2012-09-07 11:29:35 -0700 | [diff] [blame] | 929 | |
| 930 | // Apply any IT-block conditions to the opcode if necessary. |
| 931 | if (!it_conditions_.empty()) { |
| 932 | opcode << it_conditions_.back(); |
| 933 | it_conditions_.pop_back(); |
| 934 | } |
| 935 | |
Ian Rogers | 2bcb4a4 | 2012-11-08 10:39:18 -0800 | [diff] [blame] | 936 | os << StringPrintf("%p: %08x\t%-7s ", instr_ptr, instr, opcode.str().c_str()) << args.str() << '\n'; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 937 | return 4; |
| 938 | } |
| 939 | |
| 940 | size_t DisassemblerArm::DumpThumb16(std::ostream& os, const uint8_t* instr_ptr) { |
| 941 | uint16_t instr = ReadU16(instr_ptr); |
| 942 | bool is_32bit = ((instr & 0xF000) == 0xF000) || ((instr & 0xF800) == 0xE800); |
| 943 | if (is_32bit) { |
| 944 | return DumpThumb32(os, instr_ptr); |
| 945 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 946 | std::ostringstream opcode; |
| 947 | std::ostringstream args; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 948 | uint16_t opcode1 = instr >> 10; |
| 949 | if (opcode1 < 0x10) { |
| 950 | // shift (immediate), add, subtract, move, and compare |
| 951 | uint16_t opcode2 = instr >> 9; |
| 952 | switch (opcode2) { |
| 953 | case 0x0: case 0x1: case 0x2: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7: |
| 954 | case 0x8: case 0x9: case 0xA: case 0xB: { |
| 955 | // Logical shift left - 00 000xx xxxxxxxxx |
| 956 | // Logical shift right - 00 001xx xxxxxxxxx |
| 957 | // Arithmetic shift right - 00 010xx xxxxxxxxx |
| 958 | uint16_t imm5 = (instr >> 6) & 0x1F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 959 | ThumbRegister rm(instr, 3); |
| 960 | ThumbRegister Rd(instr, 7); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 961 | if (opcode2 <= 3) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 962 | opcode << "lsls"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 963 | } else if (opcode2 <= 7) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 964 | opcode << "lsrs"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 965 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 966 | opcode << "asrs"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 967 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 968 | args << Rd << ", " << rm << ", #" << imm5; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 969 | break; |
| 970 | } |
| 971 | case 0xC: case 0xD: case 0xE: case 0xF: { |
| 972 | // Add register - 00 01100 mmm nnn ddd |
| 973 | // Sub register - 00 01101 mmm nnn ddd |
| 974 | // Add 3-bit immediate - 00 01110 iii nnn ddd |
| 975 | // Sub 3-bit immediate - 00 01111 iii nnn ddd |
| 976 | uint16_t imm3_or_Rm = (instr >> 6) & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 977 | ThumbRegister Rn(instr, 3); |
| 978 | ThumbRegister Rd(instr, 0); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 979 | if ((opcode2 & 2) != 0 && imm3_or_Rm == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 980 | opcode << "mov"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 981 | } else { |
| 982 | if ((opcode2 & 1) == 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 983 | opcode << "adds"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 984 | } else { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 985 | opcode << "subs"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 986 | } |
| 987 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 988 | args << Rd << ", " << Rn; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 989 | if ((opcode2 & 2) == 0) { |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 990 | ArmRegister Rm(imm3_or_Rm); |
| 991 | args << ", " << Rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 992 | } else if (imm3_or_Rm != 0) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 993 | args << ", #" << imm3_or_Rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 994 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 995 | break; |
| 996 | } |
| 997 | case 0x10: case 0x11: case 0x12: case 0x13: |
| 998 | case 0x14: case 0x15: case 0x16: case 0x17: |
| 999 | case 0x18: case 0x19: case 0x1A: case 0x1B: |
| 1000 | case 0x1C: case 0x1D: case 0x1E: case 0x1F: { |
| 1001 | // MOVS Rd, #imm8 - 00100 ddd iiiiiiii |
| 1002 | // CMP Rn, #imm8 - 00101 nnn iiiiiiii |
| 1003 | // ADDS Rn, #imm8 - 00110 nnn iiiiiiii |
| 1004 | // SUBS Rn, #imm8 - 00111 nnn iiiiiiii |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1005 | ThumbRegister Rn(instr, 8); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1006 | uint16_t imm8 = instr & 0xFF; |
| 1007 | switch (opcode2 >> 2) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1008 | case 4: opcode << "movs"; break; |
| 1009 | case 5: opcode << "cmp"; break; |
| 1010 | case 6: opcode << "adds"; break; |
| 1011 | case 7: opcode << "subs"; break; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1012 | } |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1013 | args << Rn << ", #" << imm8; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1014 | break; |
| 1015 | } |
| 1016 | default: |
| 1017 | break; |
| 1018 | } |
Ian Rogers | ad03ef5 | 2012-03-18 19:34:47 -0700 | [diff] [blame] | 1019 | } else if (opcode1 == 0x10) { |
| 1020 | // Data-processing |
| 1021 | uint16_t opcode2 = (instr >> 6) & 0xF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1022 | ThumbRegister rm(instr, 3); |
| 1023 | ThumbRegister rdn(instr, 0); |
Ian Rogers | ad03ef5 | 2012-03-18 19:34:47 -0700 | [diff] [blame] | 1024 | opcode << kThumbDataProcessingOperations[opcode2]; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1025 | args << rdn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1026 | } else if (opcode1 == 0x11) { |
| 1027 | // Special data instructions and branch and exchange |
| 1028 | uint16_t opcode2 = (instr >> 6) & 0x0F; |
| 1029 | switch (opcode2) { |
| 1030 | case 0x0: case 0x1: case 0x2: case 0x3: { |
| 1031 | // Add low registers - 010001 0000 xxxxxx |
| 1032 | // Add high registers - 010001 0001/001x xxxxxx |
| 1033 | uint16_t DN = (instr >> 7) & 1; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1034 | ArmRegister rm(instr, 3); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1035 | uint16_t Rdn = instr & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1036 | ArmRegister DN_Rdn((DN << 3) | Rdn); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1037 | opcode << "add"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1038 | args << DN_Rdn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1039 | break; |
| 1040 | } |
| 1041 | case 0x8: case 0x9: case 0xA: case 0xB: { |
| 1042 | // Move low registers - 010001 1000 xxxxxx |
| 1043 | // Move high registers - 010001 1001/101x xxxxxx |
| 1044 | uint16_t DN = (instr >> 7) & 1; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1045 | ArmRegister rm(instr, 3); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1046 | uint16_t Rdn = instr & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1047 | ArmRegister DN_Rdn((DN << 3) | Rdn); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1048 | opcode << "mov"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1049 | args << DN_Rdn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1050 | break; |
| 1051 | } |
| 1052 | case 0x5: case 0x6: case 0x7: { |
| 1053 | // Compare high registers - 010001 0101/011x xxxxxx |
| 1054 | uint16_t N = (instr >> 7) & 1; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1055 | ArmRegister rm(instr, 3); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1056 | uint16_t Rn = instr & 7; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1057 | ArmRegister N_Rn((N << 3) | Rn); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1058 | opcode << "cmp"; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1059 | args << N_Rn << ", " << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1060 | break; |
| 1061 | } |
| 1062 | case 0xC: case 0xD: case 0xE: case 0xF: { |
| 1063 | // Branch and exchange - 010001 110x xxxxxx |
| 1064 | // Branch with link and exchange - 010001 111x xxxxxx |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1065 | ArmRegister rm(instr, 3); |
| 1066 | opcode << ((opcode2 & 0x2) == 0 ? "bx" : "blx"); |
| 1067 | args << rm; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1068 | break; |
| 1069 | } |
| 1070 | default: |
| 1071 | break; |
| 1072 | } |
jeffhao | eae2691 | 2013-01-28 16:29:54 -0800 | [diff] [blame] | 1073 | } else if (opcode1 == 0x12 || opcode1 == 0x13) { // 01001x |
| 1074 | ThumbRegister Rt(instr, 8); |
| 1075 | uint16_t imm8 = instr & 0xFF; |
| 1076 | opcode << "ldr"; |
| 1077 | args << Rt << ", [pc, #" << (imm8 << 2) << "]"; |
Ian Rogers | d83bc36 | 2012-09-07 17:43:13 -0700 | [diff] [blame] | 1078 | } else if ((opcode1 >= 0x14 && opcode1 <= 0x17) || // 0101xx |
| 1079 | (opcode1 >= 0x18 && opcode1 <= 0x1f) || // 011xxx |
| 1080 | (opcode1 >= 0x20 && opcode1 <= 0x27)) { // 100xxx |
| 1081 | // Load/store single data item |
| 1082 | uint16_t opA = (instr >> 12) & 0xF; |
| 1083 | if (opA == 0x5) { |
| 1084 | uint16_t opB = (instr >> 9) & 0x7; |
| 1085 | ThumbRegister Rm(instr, 6); |
| 1086 | ThumbRegister Rn(instr, 3); |
| 1087 | ThumbRegister Rt(instr, 0); |
| 1088 | switch(opB) { |
| 1089 | case 0: opcode << "str"; break; |
| 1090 | case 1: opcode << "strh"; break; |
| 1091 | case 2: opcode << "strb"; break; |
| 1092 | case 3: opcode << "ldrsb"; break; |
| 1093 | case 4: opcode << "ldr"; break; |
| 1094 | case 5: opcode << "ldrh"; break; |
| 1095 | case 6: opcode << "ldrb"; break; |
| 1096 | case 7: opcode << "ldrsh"; break; |
| 1097 | } |
| 1098 | args << Rt << ", [" << Rn << ", " << Rm << "]"; |
| 1099 | } else if (opA == 9) { |
| 1100 | uint16_t opB = (instr >> 11) & 1; |
| 1101 | ThumbRegister Rt(instr, 8); |
| 1102 | uint16_t imm8 = instr & 0xFF; |
| 1103 | opcode << (opB == 0 ? "str" : "ldr"); |
Ian Rogers | 137e88f | 2012-10-08 17:46:47 -0700 | [diff] [blame] | 1104 | args << Rt << ", [sp, #" << (imm8 << 2) << "]"; |
Ian Rogers | d83bc36 | 2012-09-07 17:43:13 -0700 | [diff] [blame] | 1105 | } else { |
| 1106 | uint16_t imm5 = (instr >> 6) & 0x1F; |
| 1107 | uint16_t opB = (instr >> 11) & 1; |
| 1108 | ThumbRegister Rn(instr, 3); |
| 1109 | ThumbRegister Rt(instr, 0); |
| 1110 | switch(opA) { |
| 1111 | case 6: |
| 1112 | imm5 <<= 2; |
| 1113 | opcode << (opB == 0 ? "str" : "ldr"); |
| 1114 | break; |
| 1115 | case 7: |
| 1116 | imm5 <<= 0; |
| 1117 | opcode << (opB == 0 ? "strb" : "ldrb"); |
| 1118 | break; |
| 1119 | case 8: |
| 1120 | imm5 <<= 1; |
| 1121 | opcode << (opB == 0 ? "strh" : "ldrh"); |
| 1122 | break; |
| 1123 | } |
| 1124 | args << Rt << ", [" << Rn << ", #" << imm5 << "]"; |
| 1125 | } |
jeffhao | eae2691 | 2013-01-28 16:29:54 -0800 | [diff] [blame] | 1126 | } else if (opcode1 >= 0x34 && opcode1 <= 0x37) { // 1101xx |
| 1127 | uint32_t imm8 = instr & 0xFF; |
| 1128 | uint32_t cond = (instr >> 8) & 0xF; |
| 1129 | opcode << "b"; |
| 1130 | DumpCond(opcode, cond); |
| 1131 | DumpBranchTarget(args, instr_ptr + 4, (imm8 << 1)); |
Ian Rogers | 9af8940 | 2012-09-07 11:29:35 -0700 | [diff] [blame] | 1132 | } else if ((instr & 0xF800) == 0xA800) { |
| 1133 | // Generate SP-relative address |
| 1134 | ThumbRegister rd(instr, 8); |
| 1135 | int imm8 = instr & 0xFF; |
| 1136 | opcode << "add"; |
| 1137 | args << rd << ", sp, #" << (imm8 << 2); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1138 | } else if ((instr & 0xF000) == 0xB000) { |
| 1139 | // Miscellaneous 16-bit instructions |
| 1140 | uint16_t opcode2 = (instr >> 5) & 0x7F; |
| 1141 | switch (opcode2) { |
| 1142 | case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07: { |
| 1143 | // Add immediate to SP - 1011 00000 ii iiiii |
| 1144 | // Subtract immediate from SP - 1011 00001 ii iiiii |
| 1145 | int imm7 = instr & 0x7F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1146 | opcode << ((opcode2 & 4) == 0 ? "add" : "sub"); |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1147 | args << "sp, sp, #" << (imm7 << 2); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1148 | break; |
| 1149 | } |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 1150 | case 0x08: case 0x09: case 0x0A: case 0x0B: // 0001xxx |
Ian Rogers | ebbc577 | 2012-04-11 17:00:08 -0700 | [diff] [blame] | 1151 | case 0x0C: case 0x0D: case 0x0E: case 0x0F: |
Ian Rogers | 5501913 | 2013-02-08 01:05:23 -0800 | [diff] [blame^] | 1152 | case 0x18: case 0x19: case 0x1A: case 0x1B: // 0011xxx |
| 1153 | case 0x1C: case 0x1D: case 0x1E: case 0x1F: |
Ian Rogers | ebbc577 | 2012-04-11 17:00:08 -0700 | [diff] [blame] | 1154 | case 0x48: case 0x49: case 0x4A: case 0x4B: // 1001xxx |
Ian Rogers | 5501913 | 2013-02-08 01:05:23 -0800 | [diff] [blame^] | 1155 | case 0x4C: case 0x4D: case 0x4E: case 0x4F: |
| 1156 | case 0x58: case 0x59: case 0x5A: case 0x5B: // 1011xxx |
| 1157 | case 0x5C: case 0x5D: case 0x5E: case 0x5F: { |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 1158 | // CBNZ, CBZ |
| 1159 | uint16_t op = (instr >> 11) & 1; |
| 1160 | uint16_t i = (instr >> 9) & 1; |
| 1161 | uint16_t imm5 = (instr >> 3) & 0x1F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1162 | ThumbRegister Rn(instr, 0); |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 1163 | opcode << (op != 0 ? "cbnz" : "cbz"); |
| 1164 | uint32_t imm32 = (i << 7) | (imm5 << 1); |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1165 | args << Rn << ", "; |
Ian Rogers | 087b241 | 2012-03-21 01:30:32 -0700 | [diff] [blame] | 1166 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
| 1167 | break; |
| 1168 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 1169 | case 0x78: case 0x79: case 0x7A: case 0x7B: // 1111xxx |
| 1170 | case 0x7C: case 0x7D: case 0x7E: case 0x7F: { |
| 1171 | // If-Then, and hints |
| 1172 | uint16_t opA = (instr >> 4) & 0xF; |
| 1173 | uint16_t opB = instr & 0xF; |
| 1174 | if (opB == 0) { |
| 1175 | switch (opA) { |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1176 | case 0: opcode << "nop"; break; |
| 1177 | case 1: opcode << "yield"; break; |
| 1178 | case 2: opcode << "wfe"; break; |
| 1179 | case 3: opcode << "sev"; break; |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 1180 | default: break; |
| 1181 | } |
| 1182 | } else { |
Elliott Hughes | 105afd2 | 2012-04-10 15:04:25 -0700 | [diff] [blame] | 1183 | uint32_t first_cond = opA; |
| 1184 | uint32_t mask = opB; |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1185 | opcode << "it"; |
Elliott Hughes | 105afd2 | 2012-04-10 15:04:25 -0700 | [diff] [blame] | 1186 | |
| 1187 | // Flesh out the base "it" opcode with the specific collection of 't's and 'e's, |
| 1188 | // and store up the actual condition codes we'll want to add to the next few opcodes. |
| 1189 | size_t count = 3 - CTZ(mask); |
| 1190 | it_conditions_.resize(count + 2); // Plus the implicit 't', plus the "" for the IT itself. |
| 1191 | for (size_t i = 0; i < count; ++i) { |
| 1192 | bool positive_cond = ((first_cond & 1) != 0); |
| 1193 | bool positive_mask = ((mask & (1 << (3 - i))) != 0); |
| 1194 | if (positive_mask == positive_cond) { |
| 1195 | opcode << 't'; |
| 1196 | it_conditions_[i] = kConditionCodeNames[first_cond]; |
| 1197 | } else { |
| 1198 | opcode << 'e'; |
| 1199 | it_conditions_[i] = kConditionCodeNames[first_cond ^ 1]; |
| 1200 | } |
| 1201 | } |
| 1202 | it_conditions_[count] = kConditionCodeNames[first_cond]; // The implicit 't'. |
| 1203 | |
| 1204 | it_conditions_[count + 1] = ""; // No condition code for the IT itself... |
| 1205 | DumpCond(args, first_cond); // ...because it's considered an argument. |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 1206 | } |
| 1207 | break; |
| 1208 | } |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1209 | default: |
| 1210 | break; |
| 1211 | } |
| 1212 | } else if (((instr & 0xF000) == 0x5000) || ((instr & 0xE000) == 0x6000) || |
| 1213 | ((instr & 0xE000) == 0x8000)) { |
| 1214 | // Load/store single data item |
| 1215 | uint16_t opA = instr >> 12; |
| 1216 | //uint16_t opB = (instr >> 9) & 7; |
| 1217 | switch (opA) { |
| 1218 | case 0x6: { |
Elliott Hughes | 28fa76d | 2012-04-09 17:31:46 -0700 | [diff] [blame] | 1219 | // STR Rt, [Rn, #imm] - 01100 iiiii nnn ttt |
| 1220 | // LDR Rt, [Rn, #imm] - 01101 iiiii nnn ttt |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1221 | uint16_t imm5 = (instr >> 6) & 0x1F; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1222 | ThumbRegister Rn(instr, 3); |
Elliott Hughes | 28fa76d | 2012-04-09 17:31:46 -0700 | [diff] [blame] | 1223 | ThumbRegister Rt(instr, 0); |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1224 | opcode << ((instr & 0x800) == 0 ? "str" : "ldr"); |
| 1225 | args << Rt << ", [" << Rn << ", #" << (imm5 << 2) << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1226 | break; |
| 1227 | } |
| 1228 | case 0x9: { |
| 1229 | // STR Rt, [SP, #imm] - 01100 ttt iiiiiiii |
| 1230 | // LDR Rt, [SP, #imm] - 01101 ttt iiiiiiii |
| 1231 | uint16_t imm8 = instr & 0xFF; |
Elliott Hughes | 630e77d | 2012-03-22 19:20:56 -0700 | [diff] [blame] | 1232 | ThumbRegister Rt(instr, 8); |
| 1233 | opcode << ((instr & 0x800) == 0 ? "str" : "ldr"); |
| 1234 | args << Rt << ", [sp, #" << (imm8 << 2) << "]"; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1235 | break; |
| 1236 | } |
| 1237 | default: |
| 1238 | break; |
| 1239 | } |
Ian Rogers | 40627db | 2012-03-04 17:31:09 -0800 | [diff] [blame] | 1240 | } else if (opcode1 == 0x38 || opcode1 == 0x39) { |
| 1241 | uint16_t imm11 = instr & 0x7FFF; |
| 1242 | int32_t imm32 = imm11 << 1; |
| 1243 | imm32 = (imm32 << 20) >> 20; // sign extend 12 bit immediate |
Elliott Hughes | cbf0b61 | 2012-03-15 16:23:47 -0700 | [diff] [blame] | 1244 | opcode << "b"; |
| 1245 | DumpBranchTarget(args, instr_ptr + 4, imm32); |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1246 | } |
Elliott Hughes | 105afd2 | 2012-04-10 15:04:25 -0700 | [diff] [blame] | 1247 | |
| 1248 | // Apply any IT-block conditions to the opcode if necessary. |
| 1249 | if (!it_conditions_.empty()) { |
| 1250 | opcode << it_conditions_.back(); |
| 1251 | it_conditions_.pop_back(); |
| 1252 | } |
| 1253 | |
Ian Rogers | 2bcb4a4 | 2012-11-08 10:39:18 -0800 | [diff] [blame] | 1254 | os << StringPrintf("%p: %04x \t%-7s ", instr_ptr, instr, opcode.str().c_str()) << args.str() << '\n'; |
Ian Rogers | 3a5c1ce | 2012-02-29 10:06:46 -0800 | [diff] [blame] | 1255 | } |
| 1256 | return 2; |
| 1257 | } |
| 1258 | |
| 1259 | } // namespace arm |
| 1260 | } // namespace art |