Merge "Merge remote-tracking branch 'aosp/upstream-master' into HEAD" am: 340853027b am: 0e7ad30895 am: 4c63dcff82 am: 8a51068b5f am: f4dc25e77d
Original change: https://android-review.googlesource.com/c/platform/external/arm-trusted-firmware/+/1824194
Change-Id: I9c0d1e863a9ee0cf8c64a31cb1970e8f279991a1
diff --git a/.cz.json b/.cz.json
new file mode 100644
index 0000000..cb500ba
--- /dev/null
+++ b/.cz.json
@@ -0,0 +1,5 @@
+{
+ "path": "./node_modules/cz-conventional-changelog",
+ "maxHeaderWidth": 50,
+ "maxLineWidth": 72
+}
\ No newline at end of file
diff --git a/.gitignore b/.gitignore
index 79c5104..f524658 100644
--- a/.gitignore
+++ b/.gitignore
@@ -42,3 +42,5 @@
# Ctags
tags
+# Node.js
+node_modules/
diff --git a/.husky/.gitignore b/.husky/.gitignore
new file mode 100644
index 0000000..31354ec
--- /dev/null
+++ b/.husky/.gitignore
@@ -0,0 +1 @@
+_
diff --git a/.husky/commit-msg b/.husky/commit-msg
new file mode 100755
index 0000000..c1c9600
--- /dev/null
+++ b/.husky/commit-msg
@@ -0,0 +1,7 @@
+#!/bin/sh
+
+# shellcheck source=./_/husky.sh
+. "$(dirname "$0")/_/husky.sh"
+
+"$(dirname "$0")/commit-msg.gerrit" "$@"
+"$(dirname "$0")/commit-msg.commitlint" "$@"
diff --git a/.husky/commit-msg.commitlint b/.husky/commit-msg.commitlint
new file mode 100755
index 0000000..ca25ce1
--- /dev/null
+++ b/.husky/commit-msg.commitlint
@@ -0,0 +1,3 @@
+#!/bin/sh
+
+npx --no-install commitlint --edit "$1"
diff --git a/.husky/commit-msg.gerrit b/.husky/commit-msg.gerrit
new file mode 100755
index 0000000..b8ce477
--- /dev/null
+++ b/.husky/commit-msg.gerrit
@@ -0,0 +1,194 @@
+#!/bin/sh
+# From Gerrit Code Review 2.14.20
+#
+# Part of Gerrit Code Review (https://www.gerritcodereview.com/)
+#
+# Copyright (C) 2009 The Android Open Source Project
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+
+unset GREP_OPTIONS
+
+CHANGE_ID_AFTER="Bug|Depends-On|Issue|Test|Feature|Fixes|Fixed"
+MSG="$1"
+
+# Check for, and add if missing, a unique Change-Id
+#
+add_ChangeId() {
+ clean_message=`sed -e '
+ /^diff --git .*/{
+ s///
+ q
+ }
+ /^Signed-off-by:/d
+ /^#/d
+ ' "$MSG" | git stripspace`
+ if test -z "$clean_message"
+ then
+ return
+ fi
+
+ # Do not add Change-Id to temp commits
+ if echo "$clean_message" | head -1 | grep -q '^\(fixup\|squash\)!'
+ then
+ return
+ fi
+
+ if test "false" = "`git config --bool --get gerrit.createChangeId`"
+ then
+ return
+ fi
+
+ # Does Change-Id: already exist? if so, exit (no change).
+ if grep -i '^Change-Id:' "$MSG" >/dev/null
+ then
+ return
+ fi
+
+ id=`_gen_ChangeId`
+ T="$MSG.tmp.$$"
+ AWK=awk
+ if [ -x /usr/xpg4/bin/awk ]; then
+ # Solaris AWK is just too broken
+ AWK=/usr/xpg4/bin/awk
+ fi
+
+ # Get core.commentChar from git config or use default symbol
+ commentChar=`git config --get core.commentChar`
+ commentChar=${commentChar:-#}
+
+ # How this works:
+ # - parse the commit message as (textLine+ blankLine*)*
+ # - assume textLine+ to be a footer until proven otherwise
+ # - exception: the first block is not footer (as it is the title)
+ # - read textLine+ into a variable
+ # - then count blankLines
+ # - once the next textLine appears, print textLine+ blankLine* as these
+ # aren't footer
+ # - in END, the last textLine+ block is available for footer parsing
+ $AWK '
+ BEGIN {
+ if (match(ENVIRON["OS"], "Windows")) {
+ RS="\r?\n" # Required on recent Cygwin
+ }
+ # while we start with the assumption that textLine+
+ # is a footer, the first block is not.
+ isFooter = 0
+ footerComment = 0
+ blankLines = 0
+ }
+
+ # Skip lines starting with commentChar without any spaces before it.
+ /^'"$commentChar"'/ { next }
+
+ # Skip the line starting with the diff command and everything after it,
+ # up to the end of the file, assuming it is only patch data.
+ # If more than one line before the diff was empty, strip all but one.
+ /^diff --git / {
+ blankLines = 0
+ while (getline) { }
+ next
+ }
+
+ # Count blank lines outside footer comments
+ /^$/ && (footerComment == 0) {
+ blankLines++
+ next
+ }
+
+ # Catch footer comment
+ /^\[[a-zA-Z0-9-]+:/ && (isFooter == 1) {
+ footerComment = 1
+ }
+
+ /]$/ && (footerComment == 1) {
+ footerComment = 2
+ }
+
+ # We have a non-blank line after blank lines. Handle this.
+ (blankLines > 0) {
+ print lines
+ for (i = 0; i < blankLines; i++) {
+ print ""
+ }
+
+ lines = ""
+ blankLines = 0
+ isFooter = 1
+ footerComment = 0
+ }
+
+ # Detect that the current block is not the footer
+ (footerComment == 0) && (!/^\[?[a-zA-Z0-9-]+:/ || /^[a-zA-Z0-9-]+:\/\//) {
+ isFooter = 0
+ }
+
+ {
+ # We need this information about the current last comment line
+ if (footerComment == 2) {
+ footerComment = 0
+ }
+ if (lines != "") {
+ lines = lines "\n";
+ }
+ lines = lines $0
+ }
+
+ # Footer handling:
+ # If the last block is considered a footer, splice in the Change-Id at the
+ # right place.
+ # Look for the right place to inject Change-Id by considering
+ # CHANGE_ID_AFTER. Keys listed in it (case insensitive) come first,
+ # then Change-Id, then everything else (eg. Signed-off-by:).
+ #
+ # Otherwise just print the last block, a new line and the Change-Id as a
+ # block of its own.
+ END {
+ unprinted = 1
+ if (isFooter == 0) {
+ print lines "\n"
+ lines = ""
+ }
+ changeIdAfter = "^(" tolower("'"$CHANGE_ID_AFTER"'") "):"
+ numlines = split(lines, footer, "\n")
+ for (line = 1; line <= numlines; line++) {
+ if (unprinted && match(tolower(footer[line]), changeIdAfter) != 1) {
+ unprinted = 0
+ print "Change-Id: I'"$id"'"
+ }
+ print footer[line]
+ }
+ if (unprinted) {
+ print "Change-Id: I'"$id"'"
+ }
+ }' "$MSG" > "$T" && mv "$T" "$MSG" || rm -f "$T"
+}
+_gen_ChangeIdInput() {
+ echo "tree `git write-tree`"
+ if parent=`git rev-parse "HEAD^0" 2>/dev/null`
+ then
+ echo "parent $parent"
+ fi
+ echo "author `git var GIT_AUTHOR_IDENT`"
+ echo "committer `git var GIT_COMMITTER_IDENT`"
+ echo
+ printf '%s' "$clean_message"
+}
+_gen_ChangeId() {
+ _gen_ChangeIdInput |
+ git hash-object -t commit --stdin
+}
+
+
+add_ChangeId
diff --git a/.husky/prepare-commit-msg b/.husky/prepare-commit-msg
new file mode 100755
index 0000000..593dfa8
--- /dev/null
+++ b/.husky/prepare-commit-msg
@@ -0,0 +1,6 @@
+#!/bin/sh
+
+# shellcheck source=./_/husky.sh
+. "$(dirname "$0")/_/husky.sh"
+
+"$(dirname "$0")/prepare-commit-msg.cz" "$@"
diff --git a/.husky/prepare-commit-msg.cz b/.husky/prepare-commit-msg.cz
new file mode 100755
index 0000000..724527d
--- /dev/null
+++ b/.husky/prepare-commit-msg.cz
@@ -0,0 +1,28 @@
+#!/bin/bash
+
+file="$1"
+type="$2"
+
+if [ -z "$type" ]; then # only run on new commits
+ #
+ # Save any commit message trailers generated by Git.
+ #
+
+ trailers=$(git interpret-trailers --parse "$file")
+
+ #
+ # Execute the Commitizen hook.
+ #
+
+ (exec < "/dev/tty" && npx --no-install git-cz --hook) || true
+
+ #
+ # Restore any trailers that Commitizen might have overwritten.
+ #
+
+ printf "\n" >> "$file"
+
+ while IFS= read -r trailer; do
+ git interpret-trailers --in-place --trailer "$trailer" "$file"
+ done <<< "$trailers"
+fi
diff --git a/METADATA b/METADATA
index 8a98a30..0dfb494 100644
--- a/METADATA
+++ b/METADATA
@@ -12,7 +12,7 @@
type: GIT
value: "https://github.com/ARM-software/arm-trusted-firmware.git"
}
- version: "v2.2"
- last_upgrade_date { year: 2020 month: 2 day: 5 }
+ version: "v2.5+"
+ last_upgrade_date { year: 2021 month: 9 day: 10 }
license_type: NOTICE
}
diff --git a/Makefile b/Makefile
index f899dac..b4bebf1 100644
--- a/Makefile
+++ b/Makefile
@@ -8,7 +8,7 @@
# Trusted Firmware Version
#
VERSION_MAJOR := 2
-VERSION_MINOR := 4
+VERSION_MINOR := 5
# Default goal is build all images
.DEFAULT_GOAL := all
@@ -245,6 +245,13 @@
# Determine if FEAT_RNG is supported
ENABLE_FEAT_RNG = $(if $(findstring rng,${arch-features}),1,0)
+# Determine if FEAT_SB is supported
+ENABLE_FEAT_SB = $(if $(findstring sb,${arch-features}),1,0)
+
+ifeq "8.5" "$(word 1, $(sort 8.5 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
+ENABLE_FEAT_SB = 1
+endif
+
ifneq ($(findstring armclang,$(notdir $(CC))),)
TF_CFLAGS_aarch32 = -target arm-arm-none-eabi $(march32-directive)
TF_CFLAGS_aarch64 = -target aarch64-arm-none-eabi $(march64-directive)
@@ -327,7 +334,7 @@
# General warnings
WARNINGS := -Wall -Wmissing-include-dirs -Wunused \
- -Wdisabled-optimization -Wvla -Wshadow \
+ -Wdisabled-optimization -Wvla -Wshadow \
-Wno-unused-parameter -Wredundant-decls
# Additional warnings
@@ -514,6 +521,10 @@
ifeq ($(findstring optee_sp,$(ARM_SPMC_MANIFEST_DTS)),optee_sp)
DTC_CPPFLAGS += -DOPTEE_SP_FW_CONFIG
endif
+
+ ifeq ($(TS_SP_FW_CONFIG),1)
+ DTC_CPPFLAGS += -DTS_SP_FW_CONFIG
+ endif
else
# All other SPDs in spd directory
SPD_DIR := spd
@@ -572,11 +583,9 @@
endif
BL31_CFLAGS += -fpie
BL31_LDFLAGS += $(PIE_LDFLAGS)
-ifeq ($(ARCH),aarch64)
BL32_CFLAGS += -fpie
BL32_LDFLAGS += $(PIE_LDFLAGS)
endif
-endif
ifeq (${ARCH},aarch64)
BL1_CPPFLAGS += -DIMAGE_AT_EL3
@@ -726,6 +735,9 @@
endif
endif
+# Trusted Boot is a prerequisite for Measured Boot. It provides trust that the
+# code taking the measurements and recording them has not been tampered
+# with. This is referred to as the Root of Trust for Measurement.
ifeq ($(MEASURED_BOOT),1)
ifneq (${TRUSTED_BOARD_BOOT},1)
$(error MEASURED_BOOT requires TRUSTED_BOARD_BOOT=1)
@@ -734,6 +746,10 @@
endif
endif
+ifeq ($(PSA_FWU_SUPPORT),1)
+ $(info PSA_FWU_SUPPORT is an experimental feature)
+endif
+
ifeq (${ARM_XLAT_TABLES_LIB_V1}, 1)
ifeq (${ALLOW_RO_XLAT_TABLES}, 1)
$(error "ALLOW_RO_XLAT_TABLES requires translation tables library v2")
@@ -895,6 +911,7 @@
DYN_DISABLE_AUTH \
EL3_EXCEPTION_HANDLING \
ENABLE_AMU \
+ AMU_RESTRICT_COUNTERS \
ENABLE_ASSERTIONS \
ENABLE_MPAM_FOR_LOWER_ELS \
ENABLE_PIE \
@@ -903,6 +920,7 @@
ENABLE_RUNTIME_INSTRUMENTATION \
ENABLE_SPE_FOR_LOWER_ELS \
ENABLE_SVE_FOR_NS \
+ ENABLE_SVE_FOR_SWD \
ERROR_DEPRECATED \
FAULT_INJECTION_SUPPORT \
GENERATE_COT \
@@ -944,6 +962,8 @@
COT_DESC_IN_DTB \
USE_SP804_TIMER \
ENABLE_FEAT_RNG \
+ ENABLE_FEAT_SB \
+ PSA_FWU_SUPPORT \
)))
$(eval $(call assert_numerics,\
@@ -952,6 +972,8 @@
ARM_ARCH_MINOR \
BRANCH_PROTECTION \
FW_ENC_STATUS \
+ NR_OF_FW_BANKS \
+ NR_OF_IMAGES_IN_FW_BANK \
)))
ifdef KEY_SIZE
@@ -984,6 +1006,7 @@
DECRYPTION_SUPPORT_${DECRYPTION_SUPPORT} \
DISABLE_MTPMU \
ENABLE_AMU \
+ AMU_RESTRICT_COUNTERS \
ENABLE_ASSERTIONS \
ENABLE_BTI \
ENABLE_MPAM_FOR_LOWER_ELS \
@@ -994,6 +1017,7 @@
ENABLE_RUNTIME_INSTRUMENTATION \
ENABLE_SPE_FOR_LOWER_ELS \
ENABLE_SVE_FOR_NS \
+ ENABLE_SVE_FOR_SWD \
ENCRYPT_BL31 \
ENCRYPT_BL32 \
ERROR_DEPRECATED \
@@ -1036,6 +1060,10 @@
COT_DESC_IN_DTB \
USE_SP804_TIMER \
ENABLE_FEAT_RNG \
+ ENABLE_FEAT_SB \
+ NR_OF_FW_BANKS \
+ NR_OF_IMAGES_IN_FW_BANK \
+ PSA_FWU_SUPPORT \
)))
ifeq (${SANITIZE_UB},trap)
@@ -1296,8 +1324,6 @@
fwu_fip: ${BUILD_PLAT}/${FWU_FIP_NAME}
${FIPTOOL}: FORCE
- @${ECHO_BLANK_LINE}
- @echo "Building $@"
ifdef UNIX_MK
${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} --no-print-directory -C ${FIPTOOLPATH}
else
@@ -1305,7 +1331,6 @@
# to pass the gnumake flags to nmake.
${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL))
endif
- @${ECHO_BLANK_LINE}
sptool: ${SPTOOL}
${SPTOOL}: FORCE
diff --git a/bl1/aarch32/bl1_entrypoint.S b/bl1/aarch32/bl1_entrypoint.S
index 6a15566..94dfd37 100644
--- a/bl1/aarch32/bl1_entrypoint.S
+++ b/bl1/aarch32/bl1_entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -49,7 +49,8 @@
_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
_init_memory=1 \
_init_c_runtime=1 \
- _exception_vectors=bl1_vector_table
+ _exception_vectors=bl1_vector_table \
+ _pie_fixup_size=0
/* -----------------------------------------------------
* Perform BL1 setup
diff --git a/bl2/aarch32/bl2_el3_entrypoint.S b/bl2/aarch32/bl2_el3_entrypoint.S
index 2e851e6..7e85551 100644
--- a/bl2/aarch32/bl2_el3_entrypoint.S
+++ b/bl2/aarch32/bl2_el3_entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -26,7 +26,8 @@
_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
_init_memory=1 \
_init_c_runtime=1 \
- _exception_vectors=bl2_vector_table
+ _exception_vectors=bl2_vector_table \
+ _pie_fixup_size=0
/*
* Restore parameters of boot rom
diff --git a/bl2/aarch32/bl2_entrypoint.S b/bl2/aarch32/bl2_entrypoint.S
index 102fd2f..6e8e2c1 100644
--- a/bl2/aarch32/bl2_entrypoint.S
+++ b/bl2/aarch32/bl2_entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -80,12 +80,14 @@
* ---------------------------------------------
*/
ldr r0, =__BSS_START__
- ldr r1, =__BSS_SIZE__
+ ldr r1, =__BSS_END__
+ sub r1, r1, r0
bl zeromem
#if USE_COHERENT_MEM
ldr r0, =__COHERENT_RAM_START__
- ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__
+ ldr r1, =__COHERENT_RAM_END_UNALIGNED__
+ sub r1, r1, r0
bl zeromem
#endif
diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c
index 203e1d4..d2de135 100644
--- a/bl2/bl2_main.c
+++ b/bl2/bl2_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,6 +14,7 @@
#include <common/debug.h>
#include <drivers/auth/auth_mod.h>
#include <drivers/console.h>
+#include <drivers/fwu/fwu.h>
#if MEASURED_BOOT
#include <drivers/measured_boot/measured_boot.h>
#endif
@@ -88,6 +89,10 @@
/* Perform remaining generic architectural setup in S-EL1 */
bl2_arch_setup();
+#if PSA_FWU_SUPPORT
+ fwu_init();
+#endif /* PSA_FWU_SUPPORT */
+
#if TRUSTED_BOARD_BOOT
/* Initialize authentication module */
auth_mod_init();
diff --git a/bl2u/aarch32/bl2u_entrypoint.S b/bl2u/aarch32/bl2u_entrypoint.S
index 6391f53..e4dd03d 100644
--- a/bl2u/aarch32/bl2u_entrypoint.S
+++ b/bl2u/aarch32/bl2u_entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -79,7 +79,8 @@
* ---------------------------------------------
*/
ldr r0, =__BSS_START__
- ldr r1, =__BSS_SIZE__
+ ldr r1, =__BSS_END__
+ sub r1, r1, r0
bl zeromem
/* --------------------------------------------
diff --git a/bl2u/aarch64/bl2u_entrypoint.S b/bl2u/aarch64/bl2u_entrypoint.S
index 3e37b44..15978b6 100644
--- a/bl2u/aarch64/bl2u_entrypoint.S
+++ b/bl2u/aarch64/bl2u_entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -69,8 +69,11 @@
* - the coherent memory section.
* ---------------------------------------------
*/
- ldr x0, =__BSS_START__
- ldr x1, =__BSS_SIZE__
+ adrp x0, __BSS_START__
+ add x0, x0, :lo12:__BSS_START__
+ adrp x1, __BSS_END__
+ add x1, x1, :lo12:__BSS_END__
+ sub x1, x1, x0
bl zeromem
/* --------------------------------------------
diff --git a/bl31/bl31.mk b/bl31/bl31.mk
index 2088533..1fdf545 100644
--- a/bl31/bl31.mk
+++ b/bl31/bl31.mk
@@ -95,6 +95,10 @@
lib/cpus/aarch64/wa_cve_2017_5715_mmu.S
endif
+ifeq ($(SMC_PCI_SUPPORT),1)
+BL31_SOURCES += services/std_svc/pci_svc.c
+endif
+
BL31_LINKERFILE := bl31/bl31.ld.S
# Flag used to indicate if Crash reporting via console should be included
diff --git a/bl32/sp_min/aarch32/entrypoint.S b/bl32/sp_min/aarch32/entrypoint.S
index f3a1e44..39f1065 100644
--- a/bl32/sp_min/aarch32/entrypoint.S
+++ b/bl32/sp_min/aarch32/entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -23,6 +23,8 @@
.globl sp_min_handle_smc
.globl sp_min_handle_fiq
+#define FIXUP_SIZE ((BL32_LIMIT) - (BL32_BASE))
+
.macro route_fiq_to_sp_min reg
/* -----------------------------------------------------
* FIQs are secure interrupts trapped by Monitor and non
@@ -87,7 +89,8 @@
_secondary_cold_boot=0 \
_init_memory=0 \
_init_c_runtime=1 \
- _exception_vectors=sp_min_vector_table
+ _exception_vectors=sp_min_vector_table \
+ _pie_fixup_size=FIXUP_SIZE
/* ---------------------------------------------------------------------
* Relay the previous bootloader's arguments to the platform layer
@@ -106,7 +109,8 @@
_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
_init_memory=1 \
_init_c_runtime=1 \
- _exception_vectors=sp_min_vector_table
+ _exception_vectors=sp_min_vector_table \
+ _pie_fixup_size=FIXUP_SIZE
/* ---------------------------------------------------------------------
* For RESET_TO_SP_MIN systems, BL32 (SP_MIN) is the first bootloader
@@ -306,7 +310,8 @@
_secondary_cold_boot=0 \
_init_memory=0 \
_init_c_runtime=0 \
- _exception_vectors=sp_min_vector_table
+ _exception_vectors=sp_min_vector_table \
+ _pie_fixup_size=0
/*
* We're about to enable MMU and participate in PSCI state coordination.
diff --git a/bl32/sp_min/sp_min.ld.S b/bl32/sp_min/sp_min.ld.S
index f202c7a..475affa 100644
--- a/bl32/sp_min/sp_min.ld.S
+++ b/bl32/sp_min/sp_min.ld.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -92,6 +92,7 @@
__RW_START__ = . ;
DATA_SECTION >RAM
+ RELA_SECTION >RAM
#ifdef BL32_PROGBITS_LIMIT
ASSERT(. <= BL32_PROGBITS_LIMIT, "BL32 progbits has exceeded its limit.")
@@ -141,5 +142,9 @@
__BL32_END__ = .;
+ /DISCARD/ : {
+ *(.dynsym .dynstr .hash .gnu.hash)
+ }
+
ASSERT(. <= BL32_LIMIT, "BL32 image has exceeded its limit.")
}
diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S
index a007bab..795c586 100644
--- a/bl32/tsp/aarch64/tsp_entrypoint.S
+++ b/bl32/tsp/aarch64/tsp_entrypoint.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -114,13 +114,19 @@
* - the coherent memory section.
* ---------------------------------------------
*/
- ldr x0, =__BSS_START__
- ldr x1, =__BSS_SIZE__
+ adrp x0, __BSS_START__
+ add x0, x0, :lo12:__BSS_START__
+ adrp x1, __BSS_END__
+ add x1, x1, :lo12:__BSS_END__
+ sub x1, x1, x0
bl zeromem
#if USE_COHERENT_MEM
- ldr x0, =__COHERENT_RAM_START__
- ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
+ adrp x0, __COHERENT_RAM_START__
+ add x0, x0, :lo12:__COHERENT_RAM_START__
+ adrp x1, __COHERENT_RAM_END_UNALIGNED__
+ add x1, x1, :lo12:__COHERENT_RAM_END_UNALIGNED__
+ sub x1, x1, x0
bl zeromem
#endif
diff --git a/commitlint.config.js b/commitlint.config.js
new file mode 100644
index 0000000..94cad8f
--- /dev/null
+++ b/commitlint.config.js
@@ -0,0 +1,14 @@
+/* eslint-env node */
+
+"use strict";
+
+const config = require("./.cz.json");
+
+module.exports = {
+ extends: ["@commitlint/config-conventional"],
+ rules: {
+ "header-max-length": [1, "always", config.maxHeaderWidth], /* Warning */
+ "body-max-line-length": [1, "always", config.maxLineWidth], /* Warning */
+ "signed-off-by": [0, "always", "Signed-off-by:"] /* Disabled - buggy */
+ }
+};
diff --git a/common/aarch64/debug.S b/common/aarch64/debug.S
index ad6acd9..d105d08 100644
--- a/common/aarch64/debug.S
+++ b/common/aarch64/debug.S
@@ -208,6 +208,9 @@
sub x4, x4, #4
bl asm_print_hex
+ /* Print new line */
+ bl asm_print_newline
+
bl plat_crash_console_flush
_panic_handler:
diff --git a/common/bl_common.c b/common/bl_common.c
index f17afcb..a7e2816 100644
--- a/common/bl_common.c
+++ b/common/bl_common.c
@@ -239,9 +239,18 @@
{
int err;
+/*
+ * All firmware banks should be part of the same non-volatile storage as per
+ * PSA FWU specification, hence don't check for any alternate boot source
+ * when PSA FWU is enabled.
+ */
+#if PSA_FWU_SUPPORT
+ err = load_auth_image_internal(image_id, image_data);
+#else
do {
err = load_auth_image_internal(image_id, image_data);
} while ((err != 0) && (plat_try_next_boot_source() != 0));
+#endif /* PSA_FWU_SUPPORT */
return err;
}
diff --git a/common/fdt_fixup.c b/common/fdt_fixup.c
index e88a550..46606fb 100644
--- a/common/fdt_fixup.c
+++ b/common/fdt_fixup.c
@@ -188,6 +188,8 @@
*
* See reserved-memory/reserved-memory.txt in the (Linux kernel) DT binding
* documentation for details.
+ * According to this binding, the address-cells and size-cells must match
+ * those of the root node.
*
* Return: 0 on success, a negative error value otherwise.
******************************************************************************/
@@ -195,23 +197,37 @@
uintptr_t base, size_t size)
{
int offs = fdt_path_offset(dtb, "/reserved-memory");
- uint32_t addresses[3];
+ uint32_t addresses[4];
+ int ac, sc;
+ unsigned int idx = 0;
+ ac = fdt_address_cells(dtb, 0);
+ sc = fdt_size_cells(dtb, 0);
if (offs < 0) { /* create if not existing yet */
offs = fdt_add_subnode(dtb, 0, "reserved-memory");
- if (offs < 0)
+ if (offs < 0) {
return offs;
- fdt_setprop_u32(dtb, offs, "#address-cells", 2);
- fdt_setprop_u32(dtb, offs, "#size-cells", 1);
+ }
+ fdt_setprop_u32(dtb, offs, "#address-cells", ac);
+ fdt_setprop_u32(dtb, offs, "#size-cells", sc);
fdt_setprop(dtb, offs, "ranges", NULL, 0);
}
- addresses[0] = cpu_to_fdt32(HIGH_BITS(base));
- addresses[1] = cpu_to_fdt32(base & 0xffffffff);
- addresses[2] = cpu_to_fdt32(size & 0xffffffff);
+ if (ac > 1) {
+ addresses[idx] = cpu_to_fdt32(HIGH_BITS(base));
+ idx++;
+ }
+ addresses[idx] = cpu_to_fdt32(base & 0xffffffff);
+ idx++;
+ if (sc > 1) {
+ addresses[idx] = cpu_to_fdt32(HIGH_BITS(size));
+ idx++;
+ }
+ addresses[idx] = cpu_to_fdt32(size & 0xffffffff);
+ idx++;
offs = fdt_add_subnode(dtb, offs, node_name);
fdt_setprop(dtb, offs, "no-map", NULL, 0);
- fdt_setprop(dtb, offs, "reg", addresses, 12);
+ fdt_setprop(dtb, offs, "reg", addresses, idx * sizeof(uint32_t));
return 0;
}
diff --git a/common/fdt_wrappers.c b/common/fdt_wrappers.c
index 5aad14e..dd7a0fa 100644
--- a/common/fdt_wrappers.c
+++ b/common/fdt_wrappers.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,12 +7,14 @@
/* Helper functions to offer easier navigation of Device Tree Blob */
#include <assert.h>
+#include <errno.h>
#include <string.h>
#include <libfdt.h>
#include <common/debug.h>
#include <common/fdt_wrappers.h>
+#include <common/uuid.h>
/*
* Read cells from a given property of the given node. Any number of 32-bit
@@ -152,6 +154,39 @@
}
/*
+ * Read UUID from a given property of the given node. Returns 0 on success,
+ * and a negative value upon error.
+ */
+int fdtw_read_uuid(const void *dtb, int node, const char *prop,
+ unsigned int length, uint8_t *uuid)
+{
+ /* Buffer for UUID string (plus NUL terminator) */
+ char uuid_string[UUID_STRING_LENGTH + 1U];
+ int err;
+
+ assert(dtb != NULL);
+ assert(prop != NULL);
+ assert(uuid != NULL);
+ assert(node >= 0);
+
+ if (length < UUID_BYTES_LENGTH) {
+ return -EINVAL;
+ }
+
+ err = fdtw_read_string(dtb, node, prop, uuid_string,
+ UUID_STRING_LENGTH + 1U);
+ if (err != 0) {
+ return err;
+ }
+
+ if (read_uuid(uuid, uuid_string) != 0) {
+ return -FDT_ERR_BADVALUE;
+ }
+
+ return 0;
+}
+
+/*
* Write cells in place to a given property of the given node. At most 2 cells
* of the property are written. Returns 0 on success, and -1 upon error.
*/
diff --git a/common/tf_crc32.c b/common/tf_crc32.c
new file mode 100644
index 0000000..b33d36e
--- /dev/null
+++ b/common/tf_crc32.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdarg.h>
+#include <assert.h>
+
+#include <arm_acle.h>
+#include <common/debug.h>
+#include <common/tf_crc32.h>
+
+/* compute CRC using Arm intrinsic function
+ *
+ * This function is useful for the platforms with the CPU ARMv8.0
+ * (with CRC instructions supported), and onwards.
+ * Platforms with CPU ARMv8.0 should make sure to add a compile switch
+ * '-march=armv8-a+crc" for successful compilation of this file.
+ *
+ * @crc: previous accumulated CRC
+ * @buf: buffer base address
+ * @size: the size of the buffer
+ *
+ * Return calculated CRC value
+ */
+uint32_t tf_crc32(uint32_t crc, const unsigned char *buf, size_t size)
+{
+ assert(buf != NULL);
+
+ uint32_t calc_crc = ~crc;
+ const unsigned char *local_buf = buf;
+ size_t local_size = size;
+
+ /*
+ * calculate CRC over byte data
+ */
+ while (local_size != 0UL) {
+ calc_crc = __crc32b(calc_crc, *local_buf);
+ local_buf++;
+ local_size--;
+ }
+
+ return ~calc_crc;
+}
diff --git a/common/tf_log.c b/common/tf_log.c
index 08d3cf4..68f1be4 100644
--- a/common/tf_log.c
+++ b/common/tf_log.c
@@ -49,6 +49,20 @@
va_end(args);
}
+void tf_log_newline(const char log_fmt[2])
+{
+ unsigned int log_level = log_fmt[0];
+
+ /* Verify that log_level is one of LOG_MARKER_* macro defined in debug.h */
+ assert((log_level > 0U) && (log_level <= LOG_LEVEL_VERBOSE));
+ assert((log_level % 10U) == 0U);
+
+ if (log_level > max_log_level)
+ return;
+
+ putchar('\n');
+}
+
/*
* The helper function to set the log level dynamically by platform. The
* maximum log level is determined by `LOG_LEVEL` build flag at compile time
diff --git a/common/uuid.c b/common/uuid.c
new file mode 100644
index 0000000..ac6db50
--- /dev/null
+++ b/common/uuid.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <common/uuid.h>
+
+/* Return the hex nibble value of a char */
+static int8_t hex_val(char hex)
+{
+ int8_t val = 0;
+
+ if ((hex >= '0') && (hex <= '9')) {
+ val = (int8_t)(hex - '0');
+ } else if ((hex >= 'a') && (hex <= 'f')) {
+ val = (int8_t)(hex - 'a' + 0xa);
+ } else if ((hex >= 'A') && (hex <= 'F')) {
+ val = (int8_t)(hex - 'A' + 0xa);
+ } else {
+ val = -1;
+ }
+
+ return val;
+}
+
+/*
+ * Read hex_src_len hex characters from hex_src, convert to bytes and
+ * store in buffer pointed to by dest
+ */
+static int read_hex(uint8_t *dest, char *hex_src, unsigned int hex_src_len)
+{
+ int8_t nibble;
+ uint8_t byte;
+
+ /*
+ * The string length must be a multiple of 2 to represent an
+ * exact number of bytes.
+ */
+ assert((hex_src_len % 2U) == 0U);
+
+ for (unsigned int i = 0U; i < (hex_src_len / 2U); i++) {
+ nibble = 0;
+ byte = 0U;
+
+ nibble = hex_val(hex_src[2U * i]);
+ if (nibble < 0) {
+ return -1;
+ }
+ byte = (uint8_t)nibble;
+ byte <<= 4U;
+
+ nibble = hex_val(hex_src[(2U * i) + 1U]);
+ if (nibble < 0) {
+ return -1;
+ }
+ byte |= (uint8_t)nibble;
+
+ *dest = byte;
+ dest++;
+ }
+
+ return 0;
+}
+
+/* Parse UUIDs of the form aabbccdd-eeff-4099-8877-665544332211 */
+int read_uuid(uint8_t *dest, char *uuid)
+{
+ int err;
+ uint8_t *dest_start = dest;
+
+ /* Check that we have enough characters */
+ if (strnlen(uuid, UUID_STRING_LENGTH) != UUID_STRING_LENGTH) {
+ WARN("UUID string is too short\n");
+ return -EINVAL;
+ }
+
+ /* aabbccdd */
+ err = read_hex(dest, uuid, 8);
+ uuid += 8;
+ dest += 4;
+
+ /* Check for '-' */
+ err |= ((*uuid == '-') ? 0 : -1);
+ uuid++;
+
+ /* eeff */
+ err |= read_hex(dest, uuid, 4);
+ uuid += 4;
+ dest += 2;
+
+ /* Check for '-' */
+ err |= ((*uuid == '-') ? 0 : -1);
+ uuid++;
+
+ /* 4099 */
+ err |= read_hex(dest, uuid, 4);
+ uuid += 4;
+ dest += 2;
+
+ /* Check for '-' */
+ err |= ((*uuid == '-') ? 0 : -1);
+ uuid++;
+
+ /* 8877 */
+ err |= read_hex(dest, uuid, 4);
+ uuid += 4;
+ dest += 2;
+
+ /* Check for '-' */
+ err |= ((*uuid == '-') ? 0 : -1);
+ uuid++;
+
+ /* 665544332211 */
+ err |= read_hex(dest, uuid, 12);
+ uuid += 12;
+ dest += 6;
+
+ if (err < 0) {
+ WARN("Error parsing UUID\n");
+ /* Clear the buffer on error */
+ memset((void *)dest_start, '\0', UUID_BYTES_LENGTH * sizeof(uint8_t));
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
diff --git a/docs/_static/css/custom.css b/docs/_static/css/custom.css
new file mode 100644
index 0000000..f6f5fa0
--- /dev/null
+++ b/docs/_static/css/custom.css
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * Set the white-space property of tables to normal.
+ * With this setting sequences of whitespace inside
+ * a table will collapse into a single whitespace,
+ * and text will wrap when necessary.
+ */
+.wy-table-responsive table td {
+white-space: normal;
+}
diff --git a/docs/about/features.rst b/docs/about/features.rst
index 964cb25..f5fc1e0 100644
--- a/docs/about/features.rst
+++ b/docs/about/features.rst
@@ -108,7 +108,7 @@
- Refinements to Position Independent Executable (PIE) support.
-- Continued support for the PSA FF-A v1.0 (formally known as SPCI) specification, to enable the
+- Continued support for the FF-A v1.0 (formally known as SPCI) specification, to enable the
use of secure partition management in the secure world.
- Documentation enhancements.
@@ -126,4 +126,4 @@
--------------
-*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 14a3b45..07f258c 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -9,42 +9,45 @@
More details may be found in the `Project Maintenance Process`_ document.
+.. |M| replace:: **Mail**
+.. |G| replace:: **GitHub ID**
+.. |F| replace:: **Files**
.. _maintainers:
Maintainers
-----------
-:M: Dan Handley <dan.handley@arm.com>
-:G: `danh-arm`_
-:M: Soby Mathew <soby.mathew@arm.com>
-:G: `soby-mathew`_
-:M: Sandrine Bailleux <sandrine.bailleux@arm.com>
-:G: `sandrine-bailleux-arm`_
-:M: Alexei Fedorov <Alexei.Fedorov@arm.com>
-:G: `AlexeiFedorov`_
-:M: Manish Pandey <manish.pandey2@arm.com>
-:G: `manish-pandey-arm`_
-:M: Mark Dykes <mark.dykes@arm.com>
-:G: `mardyk01`_
-:M: Olivier Deprez <olivier.deprez@arm.com>
-:G: `odeprez`_
-:M: Bipin Ravi <bipin.ravi@arm.com>
-:G: `bipinravi-arm`_
-:M: Joanna Farley <joanna.farley@arm.com>
-:G: `joannafarley-arm`_
-:M: Julius Werner <jwerner@chromium.org>
-:G: `jwerner-chromium`_
-:M: Varun Wadekar <vwadekar@nvidia.com>
-:G: `vwadekar`_
-:M: Andre Przywara <andre.przywara@arm.com>
-:G: `Andre-ARM`_
-:M: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
-:G: `laurenw-arm`_
-:M: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
-:G: `madhukar-Arm`_
-:M: Raghu Krishnamurthy <raghu.ncstate@icloud.com>
-:G: `raghuncstate`_
+:|M|: Dan Handley <dan.handley@arm.com>
+:|G|: `danh-arm`_
+:|M|: Soby Mathew <soby.mathew@arm.com>
+:|G|: `soby-mathew`_
+:|M|: Sandrine Bailleux <sandrine.bailleux@arm.com>
+:|G|: `sandrine-bailleux-arm`_
+:|M|: Alexei Fedorov <Alexei.Fedorov@arm.com>
+:|G|: `AlexeiFedorov`_
+:|M|: Manish Pandey <manish.pandey2@arm.com>
+:|G|: `manish-pandey-arm`_
+:|M|: Mark Dykes <mark.dykes@arm.com>
+:|G|: `mardyk01`_
+:|M|: Olivier Deprez <olivier.deprez@arm.com>
+:|G|: `odeprez`_
+:|M|: Bipin Ravi <bipin.ravi@arm.com>
+:|G|: `bipinravi-arm`_
+:|M|: Joanna Farley <joanna.farley@arm.com>
+:|G|: `joannafarley-arm`_
+:|M|: Julius Werner <jwerner@chromium.org>
+:|G|: `jwerner-chromium`_
+:|M|: Varun Wadekar <vwadekar@nvidia.com>
+:|G|: `vwadekar`_
+:|M|: Andre Przywara <andre.przywara@arm.com>
+:|G|: `Andre-ARM`_
+:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
+:|G|: `laurenw-arm`_
+:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
+:|G|: `madhukar-Arm`_
+:|M|: Raghu Krishnamurthy <raghu.ncstate@icloud.com>
+:|G|: `raghuncstate`_
.. _code owners:
@@ -52,59 +55,59 @@
Code owners
-----------
-Core Code
-~~~~~~~~~
+Common Code
+~~~~~~~~~~~
Armv7-A architecture port
^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Etienne Carriere <etienne.carriere@linaro.org>
-:G: `etienne-lms`_
+:|M|: Etienne Carriere <etienne.carriere@linaro.org>
+:|G|: `etienne-lms`_
Build Definitions for CMake Build System
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Javier Almansa Sobrino <Javier.AlmansaSobrino@arm.com>
-:G: `javieralso-arm`_
-:M: Chris Kay <chris.kay@arm.com>
-:G: `CJkay`_
-:F: /
+:|M|: Javier Almansa Sobrino <Javier.AlmansaSobrino@arm.com>
+:|G|: `javieralso-arm`_
+:|M|: Chris Kay <chris.kay@arm.com>
+:|G|: `CJKay`_
+:|F|: /
Software Delegated Exception Interface (SDEI)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Mark Dykes <mark.dykes@arm.com>
-:G: `mardyk01`_
-:M: John Powell <John.Powell@arm.com>
-:G: `john-powell-arm`_
-:F: services/std_svc/sdei/
+:|M|: Mark Dykes <mark.dykes@arm.com>
+:|G|: `mardyk01`_
+:|M|: John Powell <John.Powell@arm.com>
+:|G|: `john-powell-arm`_
+:|F|: services/std_svc/sdei/
Trusted Boot
^^^^^^^^^^^^
-:M: Sandrine Bailleux <sandrine.bailleux@arm.com>
-:G: `sandrine-bailleux-arm`_
-:M: Manish Pandey <manish.pandey2@arm.com>
-:G: `manish-pandey-arm`_
-:M: Manish Badarkhe <manish.badarkhe@arm.com>
-:G: `ManishVB-Arm`_
-:F: drivers/auth/
+:|M|: Sandrine Bailleux <sandrine.bailleux@arm.com>
+:|G|: `sandrine-bailleux-arm`_
+:|M|: Manish Pandey <manish.pandey2@arm.com>
+:|G|: `manish-pandey-arm`_
+:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
+:|G|: `ManishVB-Arm`_
+:|F|: drivers/auth/
Secure Partition Manager (SPM)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Olivier Deprez <olivier.deprez@arm.com>
-:G: `odeprez`_
-:M: Manish Pandey <manish.pandey2@arm.com>
-:G: `manish-pandey-arm`_
-:M: Maksims Svecovs <maksims.svecovs@arm.com>
-:G: `max-shvetsov`_
-:M: Joao Alves <Joao.Alves@arm.com>
-:G: `J-Alves`_
-:F: services/std_svc/spm\*
+:|M|: Olivier Deprez <olivier.deprez@arm.com>
+:|G|: `odeprez`_
+:|M|: Manish Pandey <manish.pandey2@arm.com>
+:|G|: `manish-pandey-arm`_
+:|M|: Maksims Svecovs <maksims.svecovs@arm.com>
+:|G|: `max-shvetsov`_
+:|M|: Joao Alves <Joao.Alves@arm.com>
+:|G|: `J-Alves`_
+:|F|: services/std_svc/spm\*
Exception Handling Framework (EHF)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Manish Badarkhe <manish.badarkhe@arm.com>
-:G: `ManishVB-Arm`_
-:M: John Powell <John.Powell@arm.com>
-:G: `john-powell-arm`_
-:F: bl31/ehf.c
+:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
+:|G|: `ManishVB-Arm`_
+:|M|: John Powell <John.Powell@arm.com>
+:|G|: `john-powell-arm`_
+:|F|: bl31/ehf.c
Drivers, Libraries and Framework Code
@@ -112,455 +115,530 @@
Console API framework
^^^^^^^^^^^^^^^^^^^^^
-:M: Julius Werner <jwerner@chromium.org>
-:G: `jwerner-chromium`_
-:F: drivers/console/
-:F: include/drivers/console.h
-:F: plat/common/aarch64/crash_console_helpers.S
+:|M|: Julius Werner <jwerner@chromium.org>
+:|G|: `jwerner-chromium`_
+:|F|: drivers/console/
+:|F|: include/drivers/console.h
+:|F|: plat/common/aarch64/crash_console_helpers.S
coreboot support libraries
^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Julius Werner <jwerner@chromium.org>
-:G: `jwerner-chromium`_
-:F: drivers/coreboot/
-:F: include/drivers/coreboot/
-:F: include/lib/coreboot.h
-:F: lib/coreboot/
+:|M|: Julius Werner <jwerner@chromium.org>
+:|G|: `jwerner-chromium`_
+:|F|: drivers/coreboot/
+:|F|: include/drivers/coreboot/
+:|F|: include/lib/coreboot.h
+:|F|: lib/coreboot/
eMMC/UFS drivers
^^^^^^^^^^^^^^^^
-:M: Haojian Zhuang <haojian.zhuang@linaro.org>
-:G: `hzhuang1`_
-:F: drivers/partition/
-:F: drivers/synopsys/emmc/
-:F: drivers/synopsys/ufs/
-:F: drivers/ufs/
-:F: include/drivers/dw_ufs.h
-:F: include/drivers/ufs.h
-:F: include/drivers/synopsys/dw_mmc.h
+:|M|: Haojian Zhuang <haojian.zhuang@linaro.org>
+:|G|: `hzhuang1`_
+:|F|: drivers/partition/
+:|F|: drivers/synopsys/emmc/
+:|F|: drivers/synopsys/ufs/
+:|F|: drivers/ufs/
+:|F|: include/drivers/dw_ufs.h
+:|F|: include/drivers/ufs.h
+:|F|: include/drivers/synopsys/dw_mmc.h
+
+JTAG DCC console driver
+^^^^^^^^^^^^^^^^^^^^^^^
+:M: Michal Simek <michal.simek@xilinx.com>
+:G: `michalsimek`_
+:M: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
+:G: `venkatesh`_
+:F: drivers/arm/dcc/
+:F: include/drivers/arm/dcc.h
Power State Coordination Interface (PSCI)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Javier Almansa Sobrino <Javier.AlmansaSobrino@arm.com>
-:G: `javieralso-arm`_
-:M: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
-:G: `madhukar-Arm`_
-:M: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
-:G: `laurenw-arm`_
-:M: Zelalem Aweke <Zelalem.Aweke@arm.com>
-:G: `zelalem-aweke`_
-:F: lib/psci/
+:|M|: Javier Almansa Sobrino <Javier.AlmansaSobrino@arm.com>
+:|G|: `javieralso-arm`_
+:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
+:|G|: `madhukar-Arm`_
+:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
+:|G|: `laurenw-arm`_
+:|M|: Zelalem Aweke <Zelalem.Aweke@arm.com>
+:|G|: `zelalem-aweke`_
+:|F|: lib/psci/
DebugFS
^^^^^^^
-:M: Olivier Deprez <olivier.deprez@arm.com>
-:G: `odeprez`_
-:F: lib/debugfs/
+:|M|: Olivier Deprez <olivier.deprez@arm.com>
+:|G|: `odeprez`_
+:|F|: lib/debugfs/
Firmware Configuration Framework (FCONF)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
-:G: `madhukar-Arm`_
-:M: Manish Badarkhe <manish.badarkhe@arm.com>
-:G: `ManishVB-Arm`_
-:M: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
-:G: `laurenw-arm`_
-:F: lib/fconf/
+:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
+:|G|: `madhukar-Arm`_
+:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
+:|G|: `ManishVB-Arm`_
+:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
+:|G|: `laurenw-arm`_
+:|F|: lib/fconf/
Performance Measurement Framework (PMF)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Joao Alves <Joao.Alves@arm.com>
-:G: `J-Alves`_
-:M: Jimmy Brisson <Jimmy.Brisson@arm.com>
-:G: `theotherjimmy`_
-:F: lib/pmf/
+:|M|: Joao Alves <Joao.Alves@arm.com>
+:|G|: `J-Alves`_
+:|M|: Jimmy Brisson <Jimmy.Brisson@arm.com>
+:|G|: `theotherjimmy`_
+:|F|: lib/pmf/
Arm CPU libraries
^^^^^^^^^^^^^^^^^
-:M: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
-:G: `laurenw-arm`_
-:M: John Powell <John.Powell@arm.com>
-:G: `john-powell-arm`_
-:F: lib/cpus/
+:|M|: Lauren Wehrmeister <Lauren.Wehrmeister@arm.com>
+:|G|: `laurenw-arm`_
+:|M|: John Powell <John.Powell@arm.com>
+:|G|: `john-powell-arm`_
+:|F|: lib/cpus/
Reliability Availability Serviceabilty (RAS) framework
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Olivier Deprez <olivier.deprez@arm.com>
-:G: `odeprez`_
-:M: Manish Pandey <manish.pandey2@arm.com>
-:G: `manish-pandey-arm`_
-:F: lib/extensions/ras/
+:|M|: Olivier Deprez <olivier.deprez@arm.com>
+:|G|: `odeprez`_
+:|M|: Manish Pandey <manish.pandey2@arm.com>
+:|G|: `manish-pandey-arm`_
+:|F|: lib/extensions/ras/
Activity Monitors Unit (AMU) extensions
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Alexei Fedorov <Alexei.Fedorov@arm.com>
-:G: `AlexeiFedorov`_
-:F: lib/extensions/amu/
+:|M|: Alexei Fedorov <Alexei.Fedorov@arm.com>
+:|G|: `AlexeiFedorov`_
+:|F|: lib/extensions/amu/
Memory Partitioning And Monitoring (MPAM) extensions
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Zelalem Aweke <Zelalem.Aweke@arm.com>
-:G: `zelalem-aweke`_
-:M: Jimmy Brisson <Jimmy.Brisson@arm.com>
-:G: `theotherjimmy`_
-:F: lib/extensions/mpam/
+:|M|: Zelalem Aweke <Zelalem.Aweke@arm.com>
+:|G|: `zelalem-aweke`_
+:|M|: Jimmy Brisson <Jimmy.Brisson@arm.com>
+:|G|: `theotherjimmy`_
+:|F|: lib/extensions/mpam/
Pointer Authentication (PAuth) and Branch Target Identification (BTI) extensions
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Alexei Fedorov <Alexei.Fedorov@arm.com>
-:G: `AlexeiFedorov`_
-:M: Zelalem Aweke <Zelalem.Aweke@arm.com>
-:G: `zelalem-aweke`_
-:F: lib/extensions/pauth/
+:|M|: Alexei Fedorov <Alexei.Fedorov@arm.com>
+:|G|: `AlexeiFedorov`_
+:|M|: Zelalem Aweke <Zelalem.Aweke@arm.com>
+:|G|: `zelalem-aweke`_
+:|F|: lib/extensions/pauth/
Statistical Profiling Extension (SPE)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Zelalem Aweke <Zelalem.Aweke@arm.com>
-:G: `zelalem-aweke`_
-:M: Jimmy Brisson <Jimmy.Brisson@arm.com>
-:G: `theotherjimmy`_
-:F: lib/extensions/spe/
+:|M|: Zelalem Aweke <Zelalem.Aweke@arm.com>
+:|G|: `zelalem-aweke`_
+:|M|: Jimmy Brisson <Jimmy.Brisson@arm.com>
+:|G|: `theotherjimmy`_
+:|F|: lib/extensions/spe/
Scalable Vector Extension (SVE)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Jimmy Brisson <Jimmy.Brisson@arm.com>
-:G: `theotherjimmy`_
-:F: lib/extensions/sve/
+:|M|: Jimmy Brisson <Jimmy.Brisson@arm.com>
+:|G|: `theotherjimmy`_
+:|F|: lib/extensions/sve/
Standard C library
^^^^^^^^^^^^^^^^^^
-:M: Alexei Fedorov <Alexei.Fedorov@arm.com>
-:G: `AlexeiFedorov`_
-:M: John Powell <John.Powell@arm.com>
-:G: `john-powell-arm`_
-:F: lib/libc/
+:|M|: Alexei Fedorov <Alexei.Fedorov@arm.com>
+:|G|: `AlexeiFedorov`_
+:|M|: John Powell <John.Powell@arm.com>
+:|G|: `john-powell-arm`_
+:|F|: lib/libc/
Library At ROM (ROMlib)
^^^^^^^^^^^^^^^^^^^^^^^
-:M: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
-:G: `madhukar-Arm`_
-:F: lib/romlib/
+:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
+:|G|: `madhukar-Arm`_
+:|F|: lib/romlib/
Translation tables (``xlat_tables``) library
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Javier Almansa Sobrino <Javier.AlmansaSobrino@arm.com>
-:G: `javieralso-arm`_
-:M: Joao Alves <Joao.Alves@arm.com>
-:G: `J-Alves`_
-:F: lib/xlat\_tables_\*/
+:|M|: Javier Almansa Sobrino <Javier.AlmansaSobrino@arm.com>
+:|G|: `javieralso-arm`_
+:|M|: Joao Alves <Joao.Alves@arm.com>
+:|G|: `J-Alves`_
+:|F|: lib/xlat\_tables_\*/
IO abstraction layer
^^^^^^^^^^^^^^^^^^^^
-:M: Manish Pandey <manish.pandey2@arm.com>
-:G: `manish-pandey-arm`_
-:M: Olivier Deprez <olivier.deprez@arm.com>
-:G: `odeprez`_
-:F: drivers/io/
+:|M|: Manish Pandey <manish.pandey2@arm.com>
+:|G|: `manish-pandey-arm`_
+:|M|: Olivier Deprez <olivier.deprez@arm.com>
+:|G|: `odeprez`_
+:|F|: drivers/io/
GIC driver
^^^^^^^^^^
-:M: Alexei Fedorov <Alexei.Fedorov@arm.com>
-:G: `AlexeiFedorov`_
-:M: Manish Pandey <manish.pandey2@arm.com>
-:G: `manish-pandey-arm`_
-:M: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
-:G: `madhukar-Arm`_
-:M: Olivier Deprez <olivier.deprez@arm.com>
-:G: `odeprez`_
-:F: drivers/arm/gic/
+:|M|: Alexei Fedorov <Alexei.Fedorov@arm.com>
+:|G|: `AlexeiFedorov`_
+:|M|: Manish Pandey <manish.pandey2@arm.com>
+:|G|: `manish-pandey-arm`_
+:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
+:|G|: `madhukar-Arm`_
+:|M|: Olivier Deprez <olivier.deprez@arm.com>
+:|G|: `odeprez`_
+:|F|: drivers/arm/gic/
Libfdt wrappers
^^^^^^^^^^^^^^^
-:M: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
-:G: `madhukar-Arm`_
-:M: Manish Badarkhe <manish.badarkhe@arm.com>
-:G: `ManishVB-Arm`_
-:F: common/fdt_wrappers.c
+:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
+:|G|: `madhukar-Arm`_
+:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
+:|G|: `ManishVB-Arm`_
+:|F|: common/fdt_wrappers.c
Firmware Encryption Framework
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Sumit Garg <sumit.garg@linaro.org>
-:G: `b49020`_
-:F: drivers/io/io_encrypted.c
-:F: include/drivers/io/io_encrypted.h
-:F: include/tools_share/firmware_encrypted.h
+:|M|: Sumit Garg <sumit.garg@linaro.org>
+:|G|: `b49020`_
+:|F|: drivers/io/io_encrypted.c
+:|F|: include/drivers/io/io_encrypted.h
+:|F|: include/tools_share/firmware_encrypted.h
Measured Boot
^^^^^^^^^^^^^
-:M: Alexei Fedorov <Alexei.Fedorov@arm.com>
-:G: `AlexeiFedorov`_
-:M: Javier Almansa Sobrino <Javier.AlmansaSobrino@arm.com>
-:G: `javieralso-arm`_
-:F: drivers/measured_boot
-:F: include/drivers/measured_boot
-:F: plat/arm/board/fvp/fvp_measured_boot.c
+:|M|: Alexei Fedorov <Alexei.Fedorov@arm.com>
+:|G|: `AlexeiFedorov`_
+:|M|: Javier Almansa Sobrino <Javier.AlmansaSobrino@arm.com>
+:|G|: `javieralso-arm`_
+:|F|: drivers/measured_boot
+:|F|: include/drivers/measured_boot
+:|F|: plat/arm/board/fvp/fvp_measured_boot.c
System Control and Management Interface (SCMI) Server
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Etienne Carriere <etienne.carriere@st.com>
-:G: `etienne-lms`_
-:M: Peng Fan <peng.fan@nxp.com>
-:G: `MrVan`_
-:F: drivers/scmi-msg
-:F: include/drivers/scmi\*
+:|M|: Etienne Carriere <etienne.carriere@st.com>
+:|G|: `etienne-lms`_
+:|M|: Peng Fan <peng.fan@nxp.com>
+:|G|: `MrVan`_
+:|F|: drivers/scmi-msg
+:|F|: include/drivers/scmi\*
Platform Ports
~~~~~~~~~~~~~~
Allwinner ARMv8 platform port
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Andre Przywara <andre.przywara@arm.com>
-:G: `Andre-ARM`_
-:M: Samuel Holland <samuel@sholland.org>
-:G: `smaeul`_
-:F: docs/plat/allwinner.rst
-:F: plat/allwinner/
-:F: drivers/allwinner/
+:|M|: Andre Przywara <andre.przywara@arm.com>
+:|G|: `Andre-ARM`_
+:|M|: Samuel Holland <samuel@sholland.org>
+:|G|: `smaeul`_
+:|F|: docs/plat/allwinner.rst
+:|F|: plat/allwinner/
+:|F|: drivers/allwinner/
Amlogic Meson S905 (GXBB) platform port
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Andre Przywara <andre.przywara@arm.com>
-:G: `Andre-ARM`_
-:F: docs/plat/meson-gxbb.rst
-:F: drivers/amlogic/
-:F: plat/amlogic/gxbb/
+:|M|: Andre Przywara <andre.przywara@arm.com>
+:|G|: `Andre-ARM`_
+:|F|: docs/plat/meson-gxbb.rst
+:|F|: drivers/amlogic/
+:|F|: plat/amlogic/gxbb/
Amlogic Meson S905x (GXL) platform port
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Remi Pommarel <repk@triplefau.lt>
-:G: `remi-triplefault`_
-:F: docs/plat/meson-gxl.rst
-:F: plat/amlogic/gxl/
+:|M|: Remi Pommarel <repk@triplefau.lt>
+:|G|: `remi-triplefault`_
+:|F|: docs/plat/meson-gxl.rst
+:|F|: plat/amlogic/gxl/
Amlogic Meson S905X2 (G12A) platform port
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Carlo Caione <ccaione@baylibre.com>
-:G: `carlocaione`_
-:F: docs/plat/meson-g12a.rst
-:F: plat/amlogic/g12a/
+:|M|: Carlo Caione <ccaione@baylibre.com>
+:|G|: `carlocaione`_
+:|F|: docs/plat/meson-g12a.rst
+:|F|: plat/amlogic/g12a/
Amlogic Meson A113D (AXG) platform port
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Carlo Caione <ccaione@baylibre.com>
-:G: `carlocaione`_
-:F: docs/plat/meson-axg.rst
-:F: plat/amlogic/axg/
+:|M|: Carlo Caione <ccaione@baylibre.com>
+:|G|: `carlocaione`_
+:|F|: docs/plat/meson-axg.rst
+:|F|: plat/amlogic/axg/
Arm FPGA platform port
^^^^^^^^^^^^^^^^^^^^^^
-:M: Andre Przywara <andre.przywara@arm.com>
-:G: `Andre-ARM`_
-:M: Javier Almansa Sobrino <Javier.AlmansaSobrino@arm.com>
-:G: `javieralso-arm`_
-:F: plat/arm/board/arm_fpga
+:|M|: Andre Przywara <andre.przywara@arm.com>
+:|G|: `Andre-ARM`_
+:|M|: Javier Almansa Sobrino <Javier.AlmansaSobrino@arm.com>
+:|G|: `javieralso-arm`_
+:|F|: plat/arm/board/arm_fpga
-Arm System Guidance for Infrastructure / Mobile FVP platforms
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Nariman Poushin <nariman.poushin@linaro.org>
-:G: `npoushin`_
-:M: Thomas Abraham <thomas.abraham@arm.com>
-:G: `thomas-arm`_
-:F: plat/arm/css/sgi/
-:F: plat/arm/css/sgm/
-:F: plat/arm/board/sgi575/
-:F: plat/arm/board/sgm775/
+Arm FVP Platform port
+^^^^^^^^^^^^^^^^^^^^^
+:|M|: Manish Pandey <manish.pandey2@arm.com>
+:|G|: `manish-pandey-arm`_
+:|M|: Madhukar Pappireddy <Madhukar.Pappireddy@arm.com>
+:|G|: `madhukar-Arm`_
+:|F|: plat/arm/board/fvp
+
+Arm Juno Platform port
+^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Manish Pandey <manish.pandey2@arm.com>
+:|G|: `manish-pandey-arm`_
+:|M|: Chris Kay <chris.kay@arm.com>
+:|G|: `CJKay`_
+:|F|: plat/arm/board/juno
+
+Arm Morello and N1SDP Platform ports
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Manoj Kumar <manoj.kumar3@arm.com>
+:|G|: `manojkumar-arm`_
+:|M|: Chandni Cherukuri <chandni.cherukuri@arm.com>
+:|G|: `chandnich`_
+:|F|: plat/arm/board/morello
+:|F|: plat/arm/board/n1sdp
+
+Arm Rich IoT Platform ports
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
+:|G|: `abdellatif-elkhlifi`_
+:|M|: Vishnu Banavath <vishnu.banavath@arm.com>
+:|G|: `vishnu-banavath`_
+:|F|: plat/arm/board/corstone700
+:|F|: plat/arm/board/a5ds
+:|F|: plat/arm/board/diphda
+
+Arm Reference Design platform ports
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Thomas Abraham <thomas.abraham@arm.com>
+:|G|: `thomas-arm`_
+:|M|: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
+:|G|: `vijayenthiran-arm`_
+:|F|: plat/arm/css/sgi/
+:|F|: plat/arm/board/rde1edge/
+:|F|: plat/arm/board/rdn1edge/
+:|F|: plat/arm/board/rdn2/
+:|F|: plat/arm/board/rdv1/
+:|F|: plat/arm/board/rdv1mc/
+:|F|: plat/arm/board/sgi575/
+
+Arm Total Compute platform port
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
+:|G|: `arugan02`_
+:|M|: Usama Arif <usama.arif@arm.com>
+:|G|: `uarif1`_
+:|F|: plat/arm/board/tc
HiSilicon HiKey and HiKey960 platform ports
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Haojian Zhuang <haojian.zhuang@linaro.org>
-:G: `hzhuang1`_
-:F: docs/plat/hikey.rst
-:F: docs/plat/hikey960.rst
-:F: plat/hisilicon/hikey/
-:F: plat/hisilicon/hikey960/
+:|M|: Haojian Zhuang <haojian.zhuang@linaro.org>
+:|G|: `hzhuang1`_
+:|F|: docs/plat/hikey.rst
+:|F|: docs/plat/hikey960.rst
+:|F|: plat/hisilicon/hikey/
+:|F|: plat/hisilicon/hikey960/
HiSilicon Poplar platform port
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Shawn Guo <shawn.guo@linaro.org>
-:G: `shawnguo2`_
-:F: docs/plat/poplar.rst
-:F: plat/hisilicon/poplar/
+:|M|: Shawn Guo <shawn.guo@linaro.org>
+:|G|: `shawnguo2`_
+:|F|: docs/plat/poplar.rst
+:|F|: plat/hisilicon/poplar/
Intel SocFPGA platform ports
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Tien Hock Loh <tien.hock.loh@intel.com>
-:G: `thloh85-intel`_
-:M: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
-:G: mabdulha
-:F: plat/intel/soc
-:F: drivers/intel/soc/
+:|M|: Tien Hock Loh <tien.hock.loh@intel.com>
+:|G|: `thloh85-intel`_
+:|M|: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
+:|G|: mabdulha
+:|F|: plat/intel/soc
+:|F|: drivers/intel/soc/
MediaTek platform ports
^^^^^^^^^^^^^^^^^^^^^^^
-:M: Yidi Lin (林以廸) <yidi.lin@mediatek.com>
-:G: `mtk09422`_
-:F: plat/mediatek/
+:|M|: Rex-BC Chen <rex-bc.chen@mediatek.com>
+:|G|: `mtk-rex-bc-chen`_
+:|F|: plat/mediatek/
Marvell platform ports and SoC drivers
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Konstantin Porotchkin <kostap@marvell.com>
-:G: `kostapr`_
-:F: docs/plat/marvell/
-:F: plat/marvell/
-:F: drivers/marvell/
-:F: tools/marvell/
+:|M|: Konstantin Porotchkin <kostap@marvell.com>
+:|G|: `kostapr`_
+:|F|: docs/plat/marvell/
+:|F|: plat/marvell/
+:|F|: drivers/marvell/
+:|F|: tools/marvell/
NVidia platform ports
^^^^^^^^^^^^^^^^^^^^^
-:M: Varun Wadekar <vwadekar@nvidia.com>
-:G: `vwadekar`_
-:F: docs/plat/nvidia-tegra.rst
-:F: include/lib/cpus/aarch64/denver.h
-:F: lib/cpus/aarch64/denver.S
-:F: plat/nvidia/
+:|M|: Varun Wadekar <vwadekar@nvidia.com>
+:|G|: `vwadekar`_
+:|F|: docs/plat/nvidia-tegra.rst
+:|F|: include/lib/cpus/aarch64/denver.h
+:|F|: lib/cpus/aarch64/denver.S
+:|F|: plat/nvidia/
NXP QorIQ Layerscape platform ports
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Jiafei Pan <jiafei.pan@nxp.com>
-:G: `qoriq-open-source`_
-:F: docs/plat/ls1043a.rst
-:F: plat/layerscape/
+:|M|: Jiafei Pan <jiafei.pan@nxp.com>
+:|G|: `qoriq-open-source`_
+:|F|: docs/plat/ls1043a.rst
+:|F|: plat/layerscape/
NXP i.MX 7 WaRP7 platform port and SoC drivers
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
-:G: `bryanodonoghue`_
-:M: Jun Nie <jun.nie@linaro.org>
-:G: `niej`_
-:F: docs/plat/warp7.rst
-:F: plat/imx/common/
-:F: plat/imx/imx7/
-:F: drivers/imx/timer/
-:F: drivers/imx/uart/
-:F: drivers/imx/usdhc/
+:|M|: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
+:|G|: `bryanodonoghue`_
+:|M|: Jun Nie <jun.nie@linaro.org>
+:|G|: `niej`_
+:|F|: docs/plat/warp7.rst
+:|F|: plat/imx/common/
+:|F|: plat/imx/imx7/
+:|F|: drivers/imx/timer/
+:|F|: drivers/imx/uart/
+:|F|: drivers/imx/usdhc/
NXP i.MX 8 platform port
^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Anson Huang <Anson.Huang@nxp.com>
-:G: `Anson-Huang`_
-:F: docs/plat/imx8.rst
-:F: plat/imx/
+:|M|: Peng Fan <peng.fan@nxp.com>
+:|G|: `MrVan`_
+:|F|: docs/plat/imx8.rst
+:|F|: plat/imx/
NXP i.MX8M platform port
^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Jacky Bai <ping.bai@nxp.com>
-:G: `JackyBai`_
-:F: docs/plat/imx8m.rst
-:F: plat/imx/imx8m/
+:|M|: Jacky Bai <ping.bai@nxp.com>
+:|G|: `JackyBai`_
+:|F|: docs/plat/imx8m.rst
+:|F|: plat/imx/imx8m/
+
+NXP QorIQ Layerscape common code for platform ports
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Pankaj Gupta <pankaj.gupta@nxp.com>
+:|G|: `pangupta`_
+:|F|: docs/plat/nxp/
+:|F|: plat/nxp/
+:|F|: drivers/nxp/
+:|F|: tools/nxp/
+
+NXP SoC Part LX2160A and its platform port
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Pankaj Gupta <pankaj.gupta@nxp.com>
+:|G|: `pangupta`_
+:|F|: plat/nxp/soc-lx2160a
+:|F|: plat/nxp/soc-lx2160a/lx2162aqds
+:|F|: plat/nxp/soc-lx2160a/lx2160aqds
+:|F|: plat/nxp/soc-lx2160a/lx2160ardb
QEMU platform port
^^^^^^^^^^^^^^^^^^
-:M: Jens Wiklander <jens.wiklander@linaro.org>
-:G: `jenswi-linaro`_
-:F: docs/plat/qemu.rst
-:F: plat/qemu/
+:|M|: Jens Wiklander <jens.wiklander@linaro.org>
+:|G|: `jenswi-linaro`_
+:|F|: docs/plat/qemu.rst
+:|F|: plat/qemu/
QTI platform port
^^^^^^^^^^^^^^^^^
-:M: Saurabh Gorecha <sgorecha@codeaurora.org>
-:G: `sgorecha`_
-:M: Debasish Mandal <dmandal@codeaurora.org>
-:M: QTI TF Maintainers <qti.trustedfirmware.maintainers@codeaurora.org>
-:F: docs/plat/qti.rst
-:F: plat/qti/
+:|M|: Saurabh Gorecha <sgorecha@codeaurora.org>
+:|G|: `sgorecha`_
+:|M|: Debasish Mandal <dmandal@codeaurora.org>
+:|M|: QTI TF Maintainers <qti.trustedfirmware.maintainers@codeaurora.org>
+:|F|: docs/plat/qti.rst
+:|F|: plat/qti/
Raspberry Pi 3 platform port
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
-:G: `grandpaul`_
-:F: docs/plat/rpi3.rst
-:F: plat/rpi/rpi3/
-:F: plat/rpi/common/
-:F: drivers/rpi3/
-:F: include/drivers/rpi3/
+:|M|: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
+:|G|: `grandpaul`_
+:|F|: docs/plat/rpi3.rst
+:|F|: plat/rpi/rpi3/
+:|F|: plat/rpi/common/
+:|F|: drivers/rpi3/
+:|F|: include/drivers/rpi3/
Raspberry Pi 4 platform port
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Andre Przywara <andre.przywara@arm.com>
-:G: `Andre-ARM`_
-:F: docs/plat/rpi4.rst
-:F: plat/rpi/rpi4/
-:F: plat/rpi/common/
-:F: drivers/rpi3/
-:F: include/drivers/rpi3/
+:|M|: Andre Przywara <andre.przywara@arm.com>
+:|G|: `Andre-ARM`_
+:|F|: docs/plat/rpi4.rst
+:|F|: plat/rpi/rpi4/
+:|F|: plat/rpi/common/
+:|F|: drivers/rpi3/
+:|F|: include/drivers/rpi3/
Renesas rcar-gen3 platform port
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
-:G: `ldts`_
-:M: Marek Vasut <marek.vasut@gmail.com>
-:G: `marex`_
-:F: docs/plat/rcar-gen3.rst
-:F: plat/renesas/common
-:F: plat/renesas/rcar
-:F: drivers/renesas/common
-:F: drivers/renesas/rcar
-:F: tools/renesas/rcar_layout_create
+:|M|: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
+:|G|: `ldts`_
+:|M|: Marek Vasut <marek.vasut@gmail.com>
+:|G|: `marex`_
+:|F|: docs/plat/rcar-gen3.rst
+:|F|: plat/renesas/common
+:|F|: plat/renesas/rcar
+:|F|: drivers/renesas/common
+:|F|: drivers/renesas/rcar
+:|F|: tools/renesas/rcar_layout_create
Renesas RZ/G2 platform port
^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Biju Das <biju.das.jz@bp.renesas.com>
-:G: `bijucdas`_
-:M: Marek Vasut <marek.vasut@gmail.com>
-:G: `marex`_
-:M: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
-:G: `prabhakarlad`_
-:F: docs/plat/rz-g2.rst
-:F: plat/renesas/common
-:F: plat/renesas/rzg
-:F: drivers/renesas/common
-:F: drivers/renesas/rzg
-:F: tools/renesas/rzg_layout_create
+:|M|: Biju Das <biju.das.jz@bp.renesas.com>
+:|G|: `bijucdas`_
+:|M|: Marek Vasut <marek.vasut@gmail.com>
+:|G|: `marex`_
+:|M|: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+:|G|: `prabhakarlad`_
+:|F|: docs/plat/rz-g2.rst
+:|F|: plat/renesas/common
+:|F|: plat/renesas/rzg
+:|F|: drivers/renesas/common
+:|F|: drivers/renesas/rzg
+:|F|: tools/renesas/rzg_layout_create
RockChip platform port
^^^^^^^^^^^^^^^^^^^^^^
-:M: Tony Xie <tony.xie@rock-chips.com>
-:G: `TonyXie06`_
-:G: `rockchip-linux`_
-:M: Heiko Stuebner <heiko@sntech.de>
-:G: `mmind`_
-:F: plat/rockchip/
+:|M|: Tony Xie <tony.xie@rock-chips.com>
+:|G|: `TonyXie06`_
+:|G|: `rockchip-linux`_
+:|M|: Heiko Stuebner <heiko@sntech.de>
+:|G|: `mmind`_
+:|M|: Julius Werner <jwerner@chromium.org>
+:|G|: `jwerner-chromium`_
+:|F|: plat/rockchip/
STM32MP1 platform port
^^^^^^^^^^^^^^^^^^^^^^
-:M: Yann Gautier <yann.gautier@st.com>
-:G: `Yann-lms`_
-:F: docs/plat/stm32mp1.rst
-:F: drivers/st/
-:F: fdts/stm32\*
-:F: include/drivers/st/
-:F: include/dt-bindings/\*/stm32\*
-:F: plat/st/
-:F: tools/stm32image/
+:|M|: Yann Gautier <yann.gautier@st.com>
+:|G|: `Yann-lms`_
+:|F|: docs/plat/stm32mp1.rst
+:|F|: drivers/st/
+:|F|: fdts/stm32\*
+:|F|: include/drivers/st/
+:|F|: include/dt-bindings/\*/stm32\*
+:|F|: plat/st/
+:|F|: tools/stm32image/
Synquacer platform port
^^^^^^^^^^^^^^^^^^^^^^^
-:M: Sumit Garg <sumit.garg@linaro.org>
-:G: `b49020`_
-:F: docs/plat/synquacer.rst
-:F: plat/socionext/synquacer/
+:|M|: Sumit Garg <sumit.garg@linaro.org>
+:|G|: `b49020`_
+:|F|: docs/plat/synquacer.rst
+:|F|: plat/socionext/synquacer/
Texas Instruments platform port
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Nishanth Menon <nm@ti.com>
-:G: `nmenon`_
-:F: docs/plat/ti-k3.rst
-:F: plat/ti/
+:|M|: Nishanth Menon <nm@ti.com>
+:|G|: `nmenon`_
+:|F|: docs/plat/ti-k3.rst
+:|F|: plat/ti/
UniPhier platform port
^^^^^^^^^^^^^^^^^^^^^^
-:M: Orphan
-:F: docs/plat/socionext-uniphier.rst
-:F: plat/socionext/uniphier/
+:|M|: Orphan
+:|F|: docs/plat/socionext-uniphier.rst
+:|F|: plat/socionext/uniphier/
Xilinx platform port
^^^^^^^^^^^^^^^^^^^^
-:M: Michal Simek <michal.simek@xilinx.com>
-:G: `michalsimek`_
-:M: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
-:G: `venkatesh`_
-:F: docs/plat/xilinx-zynqmp.rst
-:F: plat/xilinx/
+:|M|: Michal Simek <michal.simek@xilinx.com>
+:|G|: `michalsimek`_
+:|M|: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
+:|G|: `venkatesh`_
+:|F|: docs/plat/xilinx-zynqmp.rst
+:|F|: plat/xilinx/
Secure Payloads and Dispatchers
@@ -568,61 +646,75 @@
OP-TEE dispatcher
^^^^^^^^^^^^^^^^^
-:M: Jens Wiklander <jens.wiklander@linaro.org>
-:G: `jenswi-linaro`_
-:F: docs/components/spd/optee-dispatcher.rst
-:F: services/spd/opteed/
+:|M|: Jens Wiklander <jens.wiklander@linaro.org>
+:|G|: `jenswi-linaro`_
+:|F|: docs/components/spd/optee-dispatcher.rst
+:|F|: services/spd/opteed/
TLK/Trusty secure payloads
^^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Varun Wadekar <vwadekar@nvidia.com>
-:G: `vwadekar`_
-:F: docs/components/spd/tlk-dispatcher.rst
-:F: docs/components/spd/trusty-dispatcher.rst
-:F: include/bl32/payloads/tlk.h
-:F: services/spd/tlkd/
-:F: services/spd/trusty/
+:|M|: Varun Wadekar <vwadekar@nvidia.com>
+:|G|: `vwadekar`_
+:|F|: docs/components/spd/tlk-dispatcher.rst
+:|F|: docs/components/spd/trusty-dispatcher.rst
+:|F|: include/bl32/payloads/tlk.h
+:|F|: services/spd/tlkd/
+:|F|: services/spd/trusty/
Test Secure Payload (TSP)
^^^^^^^^^^^^^^^^^^^^^^^^^
-:M: Manish Badarkhe <manish.badarkhe@arm.com>
-:G: `ManishVB-Arm`_
-:F: bl32/tsp/
-:F: services/spd/tspd/
+:|M|: Manish Badarkhe <manish.badarkhe@arm.com>
+:|G|: `ManishVB-Arm`_
+:|F|: bl32/tsp/
+:|F|: services/spd/tspd/
Tools
~~~~~
Fiptool
^^^^^^^
-:M: Joao Alves <Joao.Alves@arm.com>
-:G: `J-Alves`_
-:F: tools/fiptool/
+:|M|: Joao Alves <Joao.Alves@arm.com>
+:|G|: `J-Alves`_
+:|F|: tools/fiptool/
Cert_create tool
^^^^^^^^^^^^^^^^
-:M: Sandrine Bailleux <sandrine.bailleux@arm.com>
-:G: `sandrine-bailleux-arm`_
-:F: tools/cert_create/
+:|M|: Sandrine Bailleux <sandrine.bailleux@arm.com>
+:|G|: `sandrine-bailleux-arm`_
+:|F|: tools/cert_create/
Encrypt_fw tool
^^^^^^^^^^^^^^^
-:M: Sumit Garg <sumit.garg@linaro.org>
-:G: `b49020`_
-:F: tools/encrypt_fw/
+:|M|: Sumit Garg <sumit.garg@linaro.org>
+:|G|: `b49020`_
+:|F|: tools/encrypt_fw/
Sptool
^^^^^^
-:M: Manish Pandey <manish.pandey2@arm.com>
-:G: `manish-pandey-arm`_
-:F: tools/sptool/
+:|M|: Manish Pandey <manish.pandey2@arm.com>
+:|G|: `manish-pandey-arm`_
+:|F|: tools/sptool/
Build system
^^^^^^^^^^^^
-:M: Manish Pandey <manish.pandey2@arm.com>
-:G: `manish-pandey-arm`_
-:F: Makefile
-:F: make_helpers/
+:|M|: Manish Pandey <manish.pandey2@arm.com>
+:|G|: `manish-pandey-arm`_
+:|F|: Makefile
+:|F|: make_helpers/
+
+Threat Model
+~~~~~~~~~~~~~
+:|M|: Zelalem Aweke <Zelalem.Aweke@arm.com>
+:|G|: `zelalem-aweke`_
+:|M|: Sandrine Bailleux <sandrine.bailleux@arm.com>
+:|G|: `sandrine-bailleux-arm`_
+:|M|: Joanna Farley <joanna.farley@arm.com>
+:|G|: `joannafarley-arm`_
+:|M|: Raghu Krishnamurthy <raghu.ncstate@icloud.com>
+:|G|: `raghuncstate`_
+:|M|: Varun Wadekar <vwadekar@nvidia.com>
+:|G|: `vwadekar`_
+:|F|: docs/threat_model/
.. _AlexeiFedorov: https://github.com/AlexeiFedorov
.. _Andre-ARM: https://github.com/Andre-ARM
@@ -646,7 +738,7 @@
.. _michalsimek: https://github.com/michalsimek
.. _mmind: https://github.com/mmind
.. _MrVan: https://github.com/MrVan
-.. _mtk09422: https://github.com/mtk09422
+.. _mtk-rex-bc-chen: https://github.com/mtk-rex-bc-chen
.. _niej: https://github.com/niej
.. _npoushin: https://github.com/npoushin
.. _prabhakarlad: https://github.com/prabhakarlad
@@ -681,5 +773,13 @@
.. _raghuncstate: https://github.com/raghuncstate
.. _CJKay: https://github.com/cjkay
.. _nmenon: https://github.com/nmenon
+.. _manojkumar-arm: https://github.com/manojkumar-arm
+.. _chandnich: https://github.com/chandnich
+.. _abdellatif-elkhlifi: https://github.com/abdellatif-elkhlifi
+.. _vishnu-banavath: https://github.com/vishnu-banavath
+.. _vijayenthiran-arm: https://github.com/vijayenthiran-arm
+.. _arugan02: https://github.com/arugan02
+.. _uarif1: https://github.com/uarif1
+.. _pangupta: https://github.com/pangupta
.. _Project Maintenance Process: https://developer.trustedfirmware.org/w/collaboration/project-maintenance-process/
diff --git a/docs/about/release-information.rst b/docs/about/release-information.rst
index 55c8bda..3e8dd91 100644
--- a/docs/about/release-information.rst
+++ b/docs/about/release-information.rst
@@ -44,7 +44,9 @@
+-----------------+---------------------------+------------------------------+
| v2.4 | 2nd week of Nov '20 | 4th week of Oct '20 |
+-----------------+---------------------------+------------------------------+
-| v2.5 | 2nd week of May '21 | 4th week of Apr '21 |
+| v2.5 | 3rd week of May '21 | 5th week of Apr '21 |
++-----------------+---------------------------+------------------------------+
+| v2.6 | 4th week of Oct '21 | 1st week of Oct '21 |
+-----------------+---------------------------+------------------------------+
Removal of Deprecated Interfaces
@@ -64,4 +66,4 @@
--------------
-*Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/change-log-upcoming.rst b/docs/change-log-upcoming.rst
deleted file mode 100644
index 03806d9..0000000
--- a/docs/change-log-upcoming.rst
+++ /dev/null
@@ -1,149 +0,0 @@
-Change Log for Upcoming Release
-===============================
-
-This document contains a summary of the new features, changes, fixes and known
-issues to be included in the upcoming release of Trusted Firmware-A. The contents
-of this file will be moved to the collective change-log.rst file at the time of
-release code freeze.
-
-
-Upcoming Release Version 2.4
-----------------------------
-
-**Trusted Firmware-A Contributors,
-Please log all relevant new features, changes, fixes, and known issues for the
-upcoming release. For the CPU support, drivers, and tools sections please preface
-the log description with the relevant key word, example: "<CPU>: <CPU Support
-addition>". Use the RST format convention already used in the Change Log.**
-
-New Features
-^^^^^^^^^^^^
-
-- Arm Architecture
- - Example: "Add support for Branch Target Identification (BTI)"
-
-- BL-specific
- - Example: "Enhanced BL2 bootloader flow to load secure partitions based
- on firmware configuration data (fconf)."
-
-- Build System
- - Example: "Modify FVP makefile for CPUs that support both AArch64/32"
-
-- CPU Support
- - Example: "cortex-a55: Workaround for erratum 1221012"
-
-- Drivers
- - Example: "console: Allow the console to register multiple times"
-
-- Libraries
- - Example: "Introduce BTI support in Library at ROM (romlib)"
-
-- New Platforms Support
- - Example: "qemu/qemu_sbsa: New platform support added for QEMU SBSA platform"
-
-- Platforms
- - Example: "arm/common: Introduce wrapper functions to setup secure watchdog"
-
-- PSCI
- - Example: "Adding new optional PSCI hook ``pwr_domain_on_finish_late``"
-
-- Security
- - Example: "UBSAN support and handlers"
-
-- Tools
- - Example: "fiptool: Add support to build fiptool on Windows."
-
-
-Changed
-^^^^^^^
-
-- Arm Architecture
- - Example: "Refactor ARMv8.3 Pointer Authentication support code"
-
-- BL-Specific
- - Example: "BL2: Invalidate dcache build option for BL2 entry at EL3"
-
-- Boot Flow
- - Example: "Add helper to parse BL31 parameters (both versions)"
-
-- Drivers
- - Example: "gicv3: Prevent pending G1S interrupt from becoming G0 interrupt"
-
-- Platforms
- - Example: "arm/common: Shorten the Firmware Update (FWU) process"
-
-- PSCI
- - Example: "PSCI: Lookup list of parent nodes to lock only once"
-
-- Secure Partition Manager (SPM)
- - Example: "Move shim layer to TTBR1_EL1"
-
-- Security
- - Example: "Refactor SPSR initialisation code"
-
-- Tools
- - Example: "cert_create: Remove RSA PKCS#1 v1.5 support"
-
-
-Resolved Issues
-^^^^^^^^^^^^^^^
-
-- Arm Architecture
- - Example: "Fix restoration of PAuth context"
-
-- BL-Specific
- - Example: "Fix BL31 crash reporting on AArch64 only platforms"
-
-- Build System
- - Example: "Remove several warnings reported with W=2 and W=1"
-
-- Code Quality
- - Example: "Unify type of "cpu_idx" across PSCI module"
-
-- CPU Support
- - Example: "cortex-a12: Fix MIDR mask"
-
-- Drivers
- - Example: "scmi: Fix wrong payload length"
-
-- Library Code
- - Example: "libc: Fix memchr implementation"
-
-- Platforms
- - Example: "rpi: rpi3: Fix compilation error when stack protector is enabled"
-
-- Security
- - Example: "AArch32: Disable Secure Cycle Counter"
-
-Deprecations
-^^^^^^^^^^^^
-
-- Common Code
- - Example: "Remove MULTI_CONSOLE_API flag and references to it"
-
-- Drivers
- - Example: "console: Remove deprecated finish_console_register"
-
-- Secure Partition Manager (SPM):
- - Example: "Prototype SPCI-based SPM (services/std_svc/spm) will be replaced
- with alternative methods of secure partitioning support."
-
-Known Issues
-^^^^^^^^^^^^
-
-- Build System
- - dtb: DTB creation not supported when building on a Windows host.
-
- This step in the build process is skipped when running on a Windows host. A
- known issue from the 1.6 release.
-
-- Platforms
- - arm/juno: System suspend from Linux does not function as documented in the
- user guide
-
- Following the instructions provided in the user guide document does not
- result in the platform entering system suspend state as expected. A message
- relating to the hdlcd driver failing to suspend will be emitted on the
- Linux terminal.
-
- - mediatek/mt6795: This platform does not build in this release
diff --git a/docs/change-log.rst b/docs/change-log.rst
index ec88df9..9c47568 100644
--- a/docs/change-log.rst
+++ b/docs/change-log.rst
@@ -4,6 +4,675 @@
This document contains a summary of the new features, changes, fixes and known
issues in each release of Trusted Firmware-A.
+Version 2.5
+-----------
+
+New Features
+^^^^^^^^^^^^
+
+- Architecture support
+ - Added support for speculation barrier(``FEAT_SB``) for non-Armv8.5
+ platforms starting from Armv8.0
+ - Added support for Activity Monitors Extension version 1.1(``FEAT_AMUv1p1``)
+ - Added helper functions for Random number generator(``FEAT_RNG``) registers
+ - Added support for Armv8.6 Multi-threaded PMU extensions (``FEAT_MTPMU``)
+ - Added support for MTE Asymmetric Fault Handling extensions(``FEAT_MTE3``)
+ - Added support for Privileged Access Never extensions(``FEAT_PANx``)
+
+- Bootloader images
+ - Added PIE support for AArch32 builds
+ - Enable Trusted Random Number Generator service for BL32(sp_min)
+
+- Build System
+ - Added build option for Arm Feature Modifiers
+
+- Drivers
+ - Added support for interrupts in TZC-400 driver
+
+ - Broadcom
+ - Added support for I2C, MDIO and USB drivers
+
+ - Marvell
+ - Added support for secure read/write of dfc register-set
+ - Added support for thermal sensor driver
+ - Implement a3700_core_getc API in console driver
+ - Added rx training on 10G port
+
+ - Marvell Mochi
+ - Added support for cn913x in PCIe mode
+
+ - Marvell Armada A8K
+ - Added support for TRNG-IP-76 driver and accessing RNG register
+
+ - Mediatek MT8192
+ - Added support for following drivers
+ - MPU configuration for SCP/PCIe
+ - SPM suspend
+ - Vcore DVFS
+ - LPM
+ - PTP3
+ - UART save and restore
+ - Power-off
+ - PMIC
+ - CPU hotplug and MCDI support
+ - SPMC
+ - MPU
+
+ - Mediatek MT8195
+ - Added support for following drivers
+ - GPIO, NCDI, SPMC drivers
+ - Power-off
+ - CPU hotplug, reboot and MCDI
+ - Delay timer and sys timer
+ - GIC
+
+ - NXP
+ - Added support for
+ - non-volatile storage API
+ - chain of trust and trusted board boot using two modes: MBEDTLS and CSF
+ - fip-handler necessary for DDR initialization
+ - SMMU and console drivers
+ - crypto hardware accelerator driver
+ - following drivers: SD, EMMC, QSPI, FLEXSPI, GPIO, GIC, CSU, PMU, DDR
+ - NXP Security Monitor and SFP driver
+ - interconnect config APIs using ARM CCN-CCI driver
+ - TZC APIs to configure DDR region
+ - generic timer driver
+ - Device configuration driver
+
+ - IMX
+ - Added support for image loading and io-storage driver for TBBR fip booting
+
+ - Renesas
+ - Added support for PFC and EMMC driver
+
+ - RZ Family:
+ - G2N, G2E and G2H SoCs
+ - Added support for watchdog, QoS, PFC and DRAM initialization
+
+ - RZG Family:
+ - G2M
+ - Added support for QoS and DRAM initialization
+
+ - Xilinx
+ - Added JTAG DCC support for Versal and ZynqMP SoC family.
+
+- Libraries
+ - C standard library
+ - Added support to print ``%`` in ``snprintf()`` and ``printf()`` APIs
+ - Added support for strtoull, strtoll, strtoul, strtol APIs from FreeBSD project
+
+ - CPU support
+ - Added support for
+ - Cortex_A78C CPU
+ - Makalu ELP CPU
+ - Makalu CPU
+ - Matterhorn ELP CPU
+ - Neoverse-N2 CPU
+
+ - CPU Errata
+ - Arm Cortex-A76: Added workaround for erratum 1946160
+
+ - Arm Cortex-A77: Added workaround for erratum 1946167
+
+ - Arm Cortex-A78: Added workaround for erratum 1941498 and 1951500
+
+ - Arm Neoverse-N1: Added workaround for erratum 1946160
+
+ - Flattened device tree(libfdt)
+ - Added support for wrapper function to read UUIDs in string format from dtb
+
+- Platforms
+ - Added support for MediaTek MT8195
+ - Added support for Arm RD-N2 board
+
+ - Allwinner
+ - Added support for H616 SoC
+
+ - Arm
+ - Added support for GPT parser
+ - Protect GICR frames for fused/unused cores
+
+ - Arm Morello
+ - Added VirtIO network device to Morello FVP fdts
+
+ - Arm RD-N2
+ - Added support for variant 1 of RD-N2 platform
+ - Enable AMU support
+
+ - Arm RD-V1
+ - Enable AMU support
+
+ - Arm SGI
+ - Added support for platform variant build option
+
+ - Arm TC0
+ - Added Matterhorn ELP CPU support
+ - Added support for opteed
+
+ - Arm Juno
+ - Added support to use hw_config in BL31
+ - Use TRNG entropy source for SMCCC TRNG interface
+ - Condition Juno entropy source with CRC instructions
+
+ - Marvell Mochi
+ - Added support for detection of secure mode
+
+ - Marvell ARMADA
+ - Added support for new compile option A3720_DB_PM_WAKEUP_SRC
+ - Added support doing system reset via CM3 secure coprocessor
+ - Made several makefile enhancements required to build WTMI_MULTI_IMG and TIMDDRTOOL
+ - Added support for building DOIMAGETOOL tool
+ - Added new target mrvl_bootimage
+
+ - Mediatek MT8192
+ - Added support for rtc power off sequence
+
+ - Mediatek MT8195
+ - Added support for SiP service
+
+ - STM32MP1
+ - Added support for
+ - Seeed ODYSSEY SoM and board
+ - SDMMC2 and I2C2 pins in pinctrl
+ - I2C2 peripheral in DTS
+ - PIE for BL32
+ - TZC-400 interrupt managament
+ - Linux Automation MC-1 board
+
+ - Renesas RZG
+ - Added support for identifying EK874 RZ/G2E board
+ - Added support for identifying HopeRun HiHope RZ/G2H and RZ/G2H boards
+
+ - Rockchip
+ - Added support for stack protector
+
+ - QEMU
+ - Added support for ``max`` CPU
+ - Added Cortex-A72 support to ``virt`` platform
+ - Enabled trigger reboot from secure pl061
+
+ - QEMU SBSA
+ - Added support for sbsa-ref Embedded Controller
+
+ - NXP
+ - Added support for warm reset to retain ddr content
+ - Added support for image loader necessary for loading fip image
+
+ - lx2160a SoC Family
+ - Added support for
+ - new platform lx2160a-aqds
+ - new platform lx2160a-rdb
+ - new platform lx2162a-aqds
+ - errata handling
+
+ - IMX imx8mm
+ - Added support for trusted board boot
+
+ - TI K3
+ - Added support for lite device board
+ - Enabled Cortex-A72 erratum 1319367
+ - Enabled Cortex-A53 erratum 1530924
+
+ - Xilinx ZynqMP
+ - Added support for PS and system reset on WDT restart
+ - Added support for error management
+ - Enable support for log messages necessary for debug
+ - Added support for PM API SMC call for efuse and register access
+
+- Processes
+ - Introduced process for platform deprecation
+ - Added documentation for TF-A threat model
+ - Provided a copy of the MIT license to comply with the license
+ requirements of the arm-gic.h source file (originating from the Linux
+ kernel project and re-distributed in TF-A).
+
+- Services
+ - Added support for TRNG firmware interface service
+
+ - Arm
+ - Added SiP service to configure Ethos-N NPU
+
+ - SPMC
+ - Added documentation for SPM(Hafnium) SMMUv3 driver
+
+ - SPMD
+ - Added support for
+ - FFA_INTERRUPT forwading ABI
+ - FFA_SECONDARY_EP_REGISTER ABI
+ - FF-A v1.0 boot time power management, SPMC secondary core boot and
+ early run-time power management
+
+- Tools
+
+ - FIPTool
+ - Added mechanism to allow platform specific image UUID
+
+ - git hooks
+ - Added support for conventional commits through commitlint hook,
+ commitizen hook and husky configuration files.
+
+ - NXP tool
+ - Added support for a tool that creates pbl file from BL2
+
+ - Renesas RZ/G2
+ - Added tool support for creating bootparam and cert_header images
+
+ - CertCreate
+ - Added support for platform-defined certificates, keys, and extensions using
+ the platform's makefile
+
+ - shared tools
+ - Added EFI_GUID representation to uuid helper data structure
+
+Changed
+^^^^^^^
+
+- Common components
+ - Print newline after hex address in aarch64 el3_panic function
+ - Use proper ``#address-cells`` and ``#size-cells`` for reserved-memory in dtbs
+
+- Drivers
+
+ - Move SCMI driver from ST platform directory and make it common to all platforms
+
+ - Arm GICv3
+ - Shift eSPI register offset in GICD_OFFSET_64()
+ - Use mpidr to probe GICR for current CPU
+
+ - Arm TZC-400
+ - Adjust filter tag if it set to FILTER_BIT_ALL
+
+ - Cadence
+ - Enhance UART driver APIs to put characters to fifo
+
+ - Mediatek MT8192
+ - Move timer driver to common folder
+ - Enhanced sys_cirq driver to add more IC services
+
+ - Renesas
+ - Move ddr and delay driver to common directory
+
+ - Renesas rcar
+ - Treat log as device memory in console driver
+
+ - Renesas RZ Family:
+ - G2N and G2H SoCs
+ - Select MMC_CH1 for eMMC channel
+
+ - Marvell
+ - Added support for checking if TRNG unit is present
+
+ - Marvell A3K
+ - Set TXDCLK_2X_SEL bit during PCIe initialization
+ - Set mask parameter for every reg_set call
+
+ - Marvell Mochi
+ - Added missing stream IDs configurations
+
+ - MbedTLS
+ - Migrated to Mbed TLS v2.26.0
+
+ - IMX imx8mp
+ - Change the bl31 physical load address
+
+ - QEMU SBSA
+ - Enable secure variable storage
+
+ - SCMI
+ - Update power domain protocol version to 2.0
+
+ - STM32
+ - Remove dead code from nand FMC driver
+
+- Libraries
+ - C Standard Library
+ - Use macros to reduce duplicated code between snprintf and printf
+
+ - CPU support
+ - Sanity check pointers before use in AArch32 builds
+
+ - Arm Cortex-A78
+ - Remove rainier cpu workaround for errata 1542319
+
+ - Arm Makalu ELP
+ - Added "_arm" suffix to Makalu ELP CPU lib
+
+
+- Miscellaneous
+ - Editorconfig
+ - set max line length to 100
+
+- Platforms
+ - Allwinner
+ - Added reserved-memory node to DT
+ - Express memmap more dynamically
+ - Move SEPARATE_NOBITS_REGION to platforms
+ - Limit FDT checks to reduce code size
+ - Use CPUIDLE hardware when available
+ - Allow conditional compilation of SCPI and native PSCI ops
+ - Always use a 3MHz RSB bus clock
+ - Enable workaround for Cortex-A53 erratum 1530924
+ - Fixed non-default PRELOADED_BL33_BASE
+ - Leave CPU power alone during BL31 setup
+ - Added several psci hooks enhancements to improve system shutdown/reset
+ sequence
+ - Return the PMIC to I2C mode after use
+ - Separate code to power off self and other CPUs
+ - Split native and SCPI-based PSCI implementations
+
+ - Allwinner H6
+ - Added R_PRCM security setup for H6 board
+ - Added SPC security setup for H6 board
+ - Use RSB for the PMIC connection on H6
+
+ - Arm
+ - Store UUID as a string, rather than ints
+ - Replace FIP base and size macro with a generic name
+ - Move compile time switch from source to dt file
+ - Don't provide NT_FW_CONFIG when booting hafnium
+ - Do not setup 'disabled' regulator
+ - Increase SP max size
+ - Remove false dependency of ARM_LINUX_KERNEL_AS_BL33 on RESET_TO_BL31
+ and allow it to be enabled independently
+
+ - Arm FVP
+ - Do not map GIC region in BL1 and BL2
+
+ - Arm Juno
+ - Refactor juno_getentropy() to return 64 bits on each call
+
+ - Arm Morello
+ - Remove "virtio-rng" from Morello FVP
+ - Enable virtIO P9 device for Morello fvp
+
+ - Arm RDV1
+ - Allow all PSCI callbacks on RD-V1
+ - Rename rddaniel to rdv1
+
+ - Arm RDV1MC
+ - Rename rddanielxlr to rdv1mc
+ - Initialize TZC-400 controllers
+
+ - Arm TC0
+ - Updated GICR base address
+ - Use scmi_dvfs clock index 1 for cores 4-7 through fdt
+ - Added reserved-memory node for OP-TEE fdts
+ - Enabled Theodul DSU in TC platform
+ - OP-TEE as S-EL1 SP with SPMC at S-EL2
+ - Update Matterhorm ELP DVFS clock index
+
+ - Arm SGI
+ - Allow access to TZC controller on all chips
+ - Define memory regions for multi-chip platforms
+ - Allow access to nor2 flash and system registers from S-EL0
+ - Define default list of memory regions for DMC-620 TZC
+ - Improve macros defining cper buffer memory region
+ - Refactor DMC-620 error handling SMC function id
+ - Refactor SDEI specific macros
+ - Added platform id value for RDN2 platform
+ - Refactored header file inclusions and inclusion of memory mapping
+
+ - Arm RDN2
+ - Allow usage of secure partitions on RDN2 platform
+ - Update GIC redistributor and TZC base address
+
+ - Arm SGM775
+ - Deprecate Arm sgm775 FVP platform
+
+ - Marvell
+ - Increase TX FIFO EMPTY timeout from 2ms to 3ms
+ - Update delay code to be compatible with 1200 MHz CPU
+
+ - Marvell ARMADA
+ - Postpone MSS CPU startup to BL31 stage
+ - Allow builds without MSS support
+ - Use MSS SRAM in secure mode
+ - Added missing FORCE, .PHONY and clean targets
+ - Cleanup MSS SRAM if used for copy
+ - Move definition of mrvl_flash target to common marvell_common.mk file
+ - Show informative build messages and blank lines
+
+ - Marvell ARMADA A3K
+ - Added a new target mrvl_uart which builds UART image
+ - Added checks that WTP, MV_DDR_PATH and CRYPTOPP_PATH are correctly defined
+ - Allow use of the system Crypto++ library
+ - Build $(WTMI_ENC_IMG) in $(BUILD_PLAT) directory
+ - Build intermediate files in $(BUILD_PLAT) directory
+ - Build UART image files directly in $(BUILD_UART) subdirectory
+ - Correctly set DDR_TOPOLOGY and CLOCKSPRESET for WTMI
+ - Do not use 'echo -e' in Makefile
+ - Improve 4GB DRAM usage from 3.375 GB to 3.75 GB
+ - Remove unused variable WTMI_SYSINIT_IMG from Makefile
+ - Simplify check if WTP variable is defined
+ - Split building $(WTMI_MULTI_IMG) and $(TIMDDRTOOL)
+
+ - Marvell ARMADA A8K
+ - Allow CP1/CP2 mapping at BLE stage
+
+ - Mediatek MT8183
+ - Added timer V20 compensation
+
+ - Nvidia Tegra
+ - Rename SMC API
+
+ - TI K3
+ - Make plat_get_syscnt_freq2 helper check CNT_FID0 register
+ - Fill non-message data fields in sec_proxy with 0x0
+ - Update ti_sci_msg_req_reboot ABI to include domain
+ - Enable USE_COHERENT_MEM only for the generic board
+ - Explicitly map SEC_SRAM_BASE to 0x0
+ - Use BL31_SIZE instead of computing
+ - Define the correct number of max table entries and increase SRAM size
+ to account for additional table
+
+ - Raspberry Pi4
+ - Switch to gicv2.mk and GICV2_SOURCES
+
+ - Renesas
+ - Move headers and assembly files to common folder
+
+ - Renesas rzg
+ - Added device tree memory node enhancements
+
+ - Rockchip
+ - Switch to using common gicv3.mk
+
+ - STM32MP1
+ - Set BL sizes regardless of flags
+
+ - QEMU
+ - Include gicv2.mk for compiling GICv2 source files
+ - Change DEVICE2 definition for MMU
+ - Added helper to calculate the position shift from MPIDR
+
+ - QEMU SBSA
+ - Include libraries for Cortex-A72
+ - Increase SHARED_RAM_SIZE
+ - Addes support in spm_mm for upto 512 cores
+ - Added support for topology handling
+
+ - QTI
+ - Mandate SMC implementation
+
+ - Xilinx
+ - Rename the IPI CRC checksum macro
+ - Use fno-jump-tables flag in CPPFLAGS
+
+ - Xilinx versal
+ - Added the IPI CRC checksum macro support
+ - Mark IPI calls secure/non-secure
+ - Enable sgi to communicate with linux using IPI
+ - Remove Cortex-A53 compilation
+
+ - Xilinx ZynqMP
+ - Configure counter frequency during initialization
+ - Filter errors related to clock gate permissions
+ - Implement pinctrl request/release EEMI API
+ - Reimplement pinctrl get/set config parameter EEMI API calls
+ - Reimplement pinctrl set/get function EEMI API
+ - Update error codes to match Linux and PMU Firmware
+ - Update PM version and support PM version check
+ - Update return type in query functions
+ - Added missing ids for 43/46/47dr devices
+ - Checked for DLL status before doing reset
+ - Disable ITAPDLYENA bit for zero ITAP delay
+ - Include GICv2 makefile
+ - Remove the custom crash implementation
+
+- Services
+
+ - SPMD
+ - Lock the g_spmd_pm structure
+ - Declare third cactus instance as UP SP
+ - Provide number of vCPUs and VM size for first SP
+ - Remove ``chosen`` node from SPMC manifests
+ - Move OP-TEE SP manifest DTS to FVP platform
+ - Update OP-TEE SP manifest with device-regions node
+ - Remove device-memory node from SPMC manifests
+
+ - SPM_MM
+ - Use sp_boot_info to set SP context
+
+ - SDEI
+ - Updata the affinity of shared event
+
+- Tools
+ - FIPtool
+ - Do not print duplicate verbose lines about building fiptool
+
+ - CertCreate
+ - Updated tool for platform defined certs, keys & extensions
+ - Create only requested certificates
+ - Avoid duplicates in extension stack
+
+Resolved Issues
+^^^^^^^^^^^^^^^
+- Several fixes for typos and mis-spellings in documentation
+
+- Build system
+ - Fixed ${FIP_NAME} to be rebuilt only when needed in Makefile
+ - Do not mark file targets as .PHONY target in Makefile
+
+- Drivers
+ - Authorization
+ - Avoid NV counter upgrade without certificate validation
+
+ - Arm GICv3
+ - Fixed logical issue for num_eints
+ - Limit SPI ID to avoid misjudgement in GICD_OFFSET()
+ - Fixed potential GICD context override with ESPI enabled
+
+ - Marvell A3700
+ - Fixed configuring polarity invert bits
+
+ - Arm TZC-400
+ - Correct FAIL_CONTROL Privileged bit
+ - Fixed logical error in FILTER_BIT definitions
+
+ - Renesas rcar
+ - Fixed several coding style violations reported by checkpatch
+
+- Libraries
+ - Arch helpers
+ - Fixed assertions in processing dynamic relocations for AArch64 builds
+
+ - C standard library
+ - Fixed MISRA issues in memset() ABI
+
+ - RAS
+ - Fixed bug of binary search in RAS interrupt handler
+
+- Platforms
+
+ - Arm
+ - Fixed missing copyrights in arm-gic.h file
+ - Fixed the order of header files in several dts files
+ - Fixed error message printing in board makefile
+ - Fixed bug of overriding the last node in image load helper API
+ - Fixed stdout-path in fdts files of TC0 and N1SDP platforms
+ - Turn ON/OFF redistributor in sync with GIC CPU interface ON/OFF for css platforms
+
+ - Arm FVP
+ - Fixed Generic Timer interrupt types in platform dts files
+
+ - Arm Juno
+ - Fixed parallel build issue for romlib config
+
+ - Arm SGI
+ - Fixed bug in SDEI receive event of RAS handler
+
+ - Intel Agilex
+ - Fixed PLAT_MAX_PWR_LVL value
+
+ - Marvell
+ - Fixed SPD handling in dram port
+
+ - Marvell ARMADA
+ - Fixed TRNG return SMC handling
+ - Fixed the logic used for LD selector mask
+ - Fixed MSS firmware loader for A8K family
+
+ - ST
+ - Fixed few violations reported by coverity static checks
+
+ - STM32MP1
+ - Fixed SELFREF_TO_X32 mask in ddr driver
+ - Do not keep mmc_device_info in stack
+ - Correct plat_crash_console_flush()
+
+ - QEMU SBSA
+ - Fixed memory type of secure NOR flash
+
+ - QTI
+ - Fixed NUM_APID and REG_APID_MAP() argument in SPMI driver
+
+ - Intel
+ - Do not keep mmc_device_info in stack
+
+ - Hisilicon
+ - Do not keep mmc_device_info in stack
+
+
+- Services
+
+ - EL3 runtime
+ - Fixed the EL2 context save/restore routine by removing EL2 generic
+ timer system registers
+ - Added fix for exception handler in BL31 by synchronizing pending EA
+ using DSB barrier
+
+ - SPMD
+ - Fixed error codes to use int32_t type
+
+ - TSPD
+ - Added bug fix in tspd interrupt handling when TSP_NS_INTR_ASYNC_PREEMPT is enabled
+
+ - TRNG
+ - Fixed compilation errors with -O0 compile option
+
+ - DebugFS
+ - Checked channel index before calling clone function
+
+ - PSCI
+ - Fixed limit of 256 CPUs caused by cast to unsigned char
+
+ - TSP
+ - Fixed compilation erros when built with GCC 11.0.0 toolchain
+
+- Tools
+ - FIPtool
+ - Do not call ``make clean`` for ``all`` target
+
+ - CertCreate
+ - Fixed bug to avoid cleaning when building the binary
+ - Used preallocated parts of the HASH struct to avoid leaking HASH struct fields
+ - Free arguments copied with strdup
+ - Free keys after use
+ - Free X509_EXTENSION structures on stack to avoid leaking them
+ - Optimized the code to avoid unnecessary attempts to create non-requested
+ certificates
+
Version 2.4
-----------
@@ -89,7 +758,7 @@
- Added workaround for erratum 1800714
- Added workaround for erratum 1925769
- - Arm Neoverse N1
+ - Arm Neoverse-N1
- Added workaround for erratum 1868343
- EL3 Runtime
diff --git a/docs/components/ffa-manifest-binding.rst b/docs/components/ffa-manifest-binding.rst
new file mode 100644
index 0000000..437df67
--- /dev/null
+++ b/docs/components/ffa-manifest-binding.rst
@@ -0,0 +1,249 @@
+FF-A manifest binding to device tree
+========================================
+
+This document defines the nodes and properties used to define a partition,
+according to the FF-A specification.
+
+Version 1.0
+-----------
+
+Partition Properties
+^^^^^^^^^^^^^^^^^^^^
+
+- compatible [mandatory]
+ - value type: <string>
+ - Must be the string "arm,ffa-manifest-X.Y" which specifies the major and
+ minor versions of the device tree binding for the FFA manifest represented
+ by this node. The minor number is incremented if the binding changes in a
+ backwards compatible manner.
+
+ - X is an integer representing the major version number of this document.
+ - Y is an integer representing the minor version number of this document.
+
+- ffa-version [mandatory]
+ - value type: <u32>
+ - Must be two 16 bits values (X, Y), concatenated as 31:16 -> X,
+ 15:0 -> Y, where:
+
+ - X is the major version of FF-A expected by the partition at the FFA
+ instance it will execute.
+ - Y is the minor version of FF-A expected by the partition at the FFA
+ instance it will execute.
+
+- uuid [mandatory]
+ - value type: <prop-encoded-array>
+ - An array consisting of 4 <u32> values, identifying the UUID of the service
+ implemented by this partition. The UUID format is described in RFC 4122.
+
+- id
+ - value type: <u32>
+ - Pre-allocated partition ID.
+
+- auxiliary-id
+ - value type: <u32>
+ - Pre-allocated ID that could be used in memory management transactions.
+
+- description
+ - value type: <string>
+ - Name of the partition e.g. for debugging purposes.
+
+- execution-ctx-count [mandatory]
+ - value type: <u32>
+ - Number of vCPUs that a VM or SP wants to instantiate.
+
+ - In the absence of virtualization, this is the number of execution
+ contexts that a partition implements.
+ - If value of this field = 1 and number of PEs > 1 then the partition is
+ treated as UP & migrate capable.
+ - If the value of this field > 1 then the partition is treated as a MP
+ capable partition irrespective of the number of PEs.
+
+- exception-level [mandatory]
+ - value type: <u32>
+ - The target exception level for the partition:
+
+ - 0x0: EL1
+ - 0x1: S_EL0
+ - 0x2: S_EL1
+
+- execution-state [mandatory]
+ - value type: <u32>
+ - The target execution state of the partition:
+
+ - 0: AArch64
+ - 1: AArch32
+
+- load-address
+ - value type: <u64>
+ - Physical base address of the partition in memory. Absence of this field
+ indicates that the partition is position independent and can be loaded at
+ any address chosen at boot time.
+
+- entrypoint-offset
+ - value type: <u64>
+ - Offset from the base of the partition's binary image to the entry point of
+ the partition. Absence of this field indicates that the entry point is at
+ offset 0x0 from the base of the partition's binary.
+
+- xlat-granule [mandatory]
+ - value type: <u32>
+ - Translation granule used with the partition:
+
+ - 0x0: 4k
+ - 0x1: 16k
+ - 0x2: 64k
+
+- boot-order
+ - value type: <u32>
+ - A unique number amongst all partitions that specifies if this partition
+ must be booted before others. The partition with the smaller number will be
+ booted first.
+
+- rx-tx-buffer
+ - value type: "memory-regions" node
+ - Specific "memory-regions" nodes that describe the RX/TX buffers expected
+ by the partition.
+ The "compatible" must be the string "arm,ffa-manifest-rx_tx-buffer".
+
+- messaging-method [mandatory]
+ - value type: <u8>
+ - Specifies which messaging methods are supported by the partition, set bit
+ means the feature is supported, clear bit - not supported:
+
+ - Bit[0]: support for receiving direct message requests
+ - Bit[1]: support for sending direct messages
+ - Bit[2]: support for indirect messaging
+ - Bit[3]: support for managed exit
+
+- has-primary-scheduler
+ - value type: <empty>
+ - Presence of this field indicates that the partition implements the primary
+ scheduler. If so, run-time EL must be EL1.
+
+- run-time-model
+ - value type: <u32>
+ - Run time model that the SPM must enforce for this SP:
+
+ - 0x0: Run to completion
+ - 0x1: Preemptible
+
+- time-slice-mem
+ - value type: <empty>
+ - Presence of this field indicates that the partition doesn't expect the
+ partition manager to time slice long running memory management functions.
+
+- gp-register-num
+ - value type: <u32>
+ - Presence of this field indicates that the partition expects the
+ ffa_init_info structure to be passed in via the specified general purpose
+ register.
+ The field specifies the general purpose register number but not its width.
+ The width is derived from the partition's execution state, as specified in
+ the partition properties. For example, if the number value is 1 then the
+ general-purpose register used will be x1 in AArch64 state and w1 in AArch32
+ state.
+
+- stream-endpoint-ids
+ - value type: <prop-encoded-array>
+ - List of <u32> tuples, identifying the IDs this partition is acting as
+ proxy for.
+
+Memory Regions
+--------------
+
+- compatible [mandatory]
+ - value type: <string>
+ - Must be the string "arm,ffa-manifest-memory-regions".
+
+- description
+ - value type: <string>
+ - Name of the memory region e.g. for debugging purposes.
+
+- pages-count [mandatory]
+ - value type: <u32>
+ - Count of pages of memory region as a multiple of the translation granule
+ size
+
+- attributes [mandatory]
+ - value type: <u32>
+ - Mapping modes: ORed to get required permission
+
+ - 0x1: Read
+ - 0x2: Write
+ - 0x4: Execute
+
+- base-address
+ - value type: <u64>
+ - Base address of the region. The address must be aligned to the translation
+ granule size.
+ The address given may be a Physical Address (PA), Virtual Address (VA), or
+ Intermediate Physical Address (IPA). Refer to the FFA specification for
+ more information on the restrictions around the address type.
+ If the base address is omitted then the partition manager must map a memory
+ region of the specified size into the partition's translation regime and
+ then communicate the region properties (including the base address chosen
+ by the partition manager) to the partition.
+
+Device Regions
+--------------
+
+- compatible [mandatory]
+ - value type: <string>
+ - Must be the string "arm,ffa-manifest-device-regions".
+
+- description
+ - value type: <string>
+ - Name of the device region e.g. for debugging purposes.
+
+- reg [mandatory]
+ - value type: <prop-encoded-array>
+ - A (address, num-pages) pair describing the device, where:
+
+ - address: The physical base address <u64> value of the device MMIO
+ region.
+ - num-pages: The <u32> number of pages of the region. The total size of
+ the region is this value multiplied by the translation granule size.
+
+- attributes [mandatory]
+ - value type: <u32>
+ - Mapping modes: ORed to get required permission
+
+ - 0x1: Read
+ - 0x2: Write
+ - 0x4: Execute
+
+- smmu-id
+ - value type: <u32>
+ - On systems with multiple System Memory Management Units (SMMUs) this
+ identifier is used to inform the partition manager which SMMU the device is
+ upstream of. If the field is omitted then it is assumed that the device is
+ not upstream of any SMMU.
+
+- stream-ids
+ - value type: <prop-encoded-array>
+ - A list of (id, mem-manage) pair, where:
+
+ - id: A unique <u32> value amongst all devices assigned to the partition.
+
+- interrupts [mandatory]
+ - value type: <prop-encoded-array>
+ - A list of (id, attributes) pair describing the device interrupts, where:
+
+ - id: The <u32> interrupt IDs.
+ - attributes: A <u32> value,
+ containing the attributes for each interrupt ID:
+
+ - Interrupt type: SPI, PPI, SGI
+ - Interrupt configuration: Edge triggered, Level triggered
+ - Interrupt security state: Secure, Non-secure
+ - Interrupt priority value
+ - Target execution context/vCPU for each SPI
+
+- exclusive-access
+ - value type: <empty>
+ - Presence of this field implies that this endpoint must be granted exclusive
+ access and ownership of this device's MMIO region.
+
+--------------
+
+*Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/components/index.rst b/docs/components/index.rst
index ffeef80..2409f96 100644
--- a/docs/components/index.rst
+++ b/docs/components/index.rst
@@ -19,6 +19,6 @@
sdei
secure-partition-manager
secure-partition-manager-mm
- psa-ffa-manifest-binding
+ ffa-manifest-binding
xlat-tables-lib-v2-design
cot-binding
diff --git a/docs/components/psa-ffa-manifest-binding.rst b/docs/components/psa-ffa-manifest-binding.rst
deleted file mode 100644
index af79074..0000000
--- a/docs/components/psa-ffa-manifest-binding.rst
+++ /dev/null
@@ -1,247 +0,0 @@
-PSA FF-A manifest binding to device tree
-========================================
-
-This document defines the nodes and properties used to define a partition,
-according to the PSA FF-A specification.
-
-Version 1.0
------------
-
-Partition Properties
-^^^^^^^^^^^^^^^^^^^^
-
-- compatible [mandatory]
- - value type: <string>
- - Must be the string "arm,ffa-manifest-X.Y" which specifies the major and
- minor versions of the device tree binding for the FFA manifest represented
- by this node. The minor number is incremented if the binding changes in a
- backwards compatible manner.
-
- - X is an integer representing the major version number of this document.
- - Y is an integer representing the minor version number of this document.
-
-- ffa-version [mandatory]
- - value type: <u32>
- - Must be two 16 bits values (X, Y), concatenated as 31:16 -> X,
- 15:0 -> Y, where:
-
- - X is the major version of PSA-FF-A expected by the partition at the FFA
- instance it will execute.
- - Y is the minor version of PSA-FF-A expected by the partition at the FFA
- instance it will execute.
-
-- uuid [mandatory]
- - value type: <prop-encoded-array>
- - An array consisting of 4 <u32> values, identifying the UUID of the service
- implemented by this partition. The UUID format is described in RFC 4122.
-
-- id
- - value type: <u32>
- - Pre-allocated partition ID.
-
-- auxiliary-id
- - value type: <u32>
- - Pre-allocated ID that could be used in memory management transactions.
-
-- description
- - value type: <string>
- - Name of the partition e.g. for debugging purposes.
-
-- execution-ctx-count [mandatory]
- - value type: <u32>
- - Number of vCPUs that a VM or SP wants to instantiate.
-
- - In the absence of virtualization, this is the number of execution
- contexts that a partition implements.
- - If value of this field = 1 and number of PEs > 1 then the partition is
- treated as UP & migrate capable.
- - If the value of this field > 1 then the partition is treated as a MP
- capable partition irrespective of the number of PEs.
-
-- exception-level [mandatory]
- - value type: <u32>
- - The target exception level for the partition:
-
- - 0x0: EL1
- - 0x1: S_EL0
- - 0x2: S_EL1
-
-- execution-state [mandatory]
- - value type: <u32>
- - The target execution state of the partition:
-
- - 0: AArch64
- - 1: AArch32
-
-- load-address
- - value type: <u64>
- - Physical base address of the partition in memory. Absence of this field
- indicates that the partition is position independent and can be loaded at
- any address chosen at boot time.
-
-- entrypoint-offset
- - value type: <u64>
- - Offset from the base of the partition's binary image to the entry point of
- the partition. Absence of this field indicates that the entry point is at
- offset 0x0 from the base of the partition's binary.
-
-- xlat-granule [mandatory]
- - value type: <u32>
- - Translation granule used with the partition:
-
- - 0x0: 4k
- - 0x1: 16k
- - 0x2: 64k
-
-- boot-order
- - value type: <u32>
- - A unique number amongst all partitions that specifies if this partition
- must be booted before others. The partition with the smaller number will be
- booted first.
-
-- rx-tx-buffer
- - value type: "memory-regions" node
- - Specific "memory-regions" nodes that describe the RX/TX buffers expected
- by the partition.
- The "compatible" must be the string "arm,ffa-manifest-rx_tx-buffer".
-
-- messaging-method [mandatory]
- - value type: <u32>
- - Specifies which messaging methods are supported by the partition:
-
- - 0x0: direct messaging method
- - 0x1: indirect messaging method
- - 0x2: both direct and indirect messaging methods
-
-- has-primary-scheduler
- - value type: <empty>
- - Presence of this field indicates that the partition implements the primary
- scheduler. If so, run-time EL must be EL1.
-
-- run-time-model
- - value type: <u32>
- - Run time model that the SPM must enforce for this SP:
-
- - 0x0: Run to completion
- - 0x1: Preemptible
-
-- time-slice-mem
- - value type: <empty>
- - Presence of this field indicates that the partition doesn't expect the
- partition manager to time slice long running memory management functions.
-
-- gp-register-num
- - value type: <u32>
- - Presence of this field indicates that the partition expects the
- ffa_init_info structure to be passed in via the specified general purpose
- register.
- The field specifies the general purpose register number but not its width.
- The width is derived from the partition's execution state, as specified in
- the partition properties. For example, if the number value is 1 then the
- general-purpose register used will be x1 in AArch64 state and w1 in AArch32
- state.
-
-- stream-endpoint-ids
- - value type: <prop-encoded-array>
- - List of <u32> tuples, identifying the IDs this partition is acting as
- proxy for.
-
-Memory Regions
---------------
-
-- compatible [mandatory]
- - value type: <string>
- - Must be the string "arm,ffa-manifest-memory-regions".
-
-- description
- - value type: <string>
- - Name of the memory region e.g. for debugging purposes.
-
-- pages-count [mandatory]
- - value type: <u32>
- - Count of pages of memory region as a multiple of the translation granule
- size
-
-- attributes [mandatory]
- - value type: <u32>
- - Mapping modes: ORed to get required permission
-
- - 0x1: Read
- - 0x2: Write
- - 0x4: Execute
-
-- base-address
- - value type: <u64>
- - Base address of the region. The address must be aligned to the translation
- granule size.
- The address given may be a Physical Address (PA), Virtual Address (VA), or
- Intermediate Physical Address (IPA). Refer to the FFA specification for
- more information on the restrictions around the address type.
- If the base address is omitted then the partition manager must map a memory
- region of the specified size into the partition's translation regime and
- then communicate the region properties (including the base address chosen
- by the partition manager) to the partition.
-
-Device Regions
---------------
-
-- compatible [mandatory]
- - value type: <string>
- - Must be the string "arm,ffa-manifest-device-regions".
-
-- description
- - value type: <string>
- - Name of the device region e.g. for debugging purposes.
-
-- reg [mandatory]
- - value type: <prop-encoded-array>
- - A (address, num-pages) pair describing the device, where:
-
- - address: The physical base address <u64> value of the device MMIO
- region.
- - num-pages: The <u32> number of pages of the region. The total size of
- the region is this value multiplied by the translation granule size.
-
-- attributes [mandatory]
- - value type: <u32>
- - Mapping modes: ORed to get required permission
-
- - 0x1: Read
- - 0x2: Write
- - 0x4: Execute
-
-- smmu-id
- - value type: <u32>
- - On systems with multiple System Memory Management Units (SMMUs) this
- identifier is used to inform the partition manager which SMMU the device is
- upstream of. If the field is omitted then it is assumed that the device is
- not upstream of any SMMU.
-
-- stream-ids
- - value type: <prop-encoded-array>
- - A list of (id, mem-manage) pair, where:
-
- - id: A unique <u32> value amongst all devices assigned to the partition.
-
-- interrupts [mandatory]
- - value type: <prop-encoded-array>
- - A list of (id, attributes) pair describing the device interrupts, where:
-
- - id: The <u32> interrupt IDs.
- - attributes: A <u32> value,
- containing the attributes for each interrupt ID:
-
- - Interrupt type: SPI, PPI, SGI
- - Interrupt configuration: Edge triggered, Level triggered
- - Interrupt security state: Secure, Non-secure
- - Interrupt priority value
- - Target execution context/vCPU for each SPI
-
-- exclusive-access
- - value type: <empty>
- - Presence of this field implies that this endpoint must be granted exclusive
- access and ownership of this device's MMIO region.
-
---------------
-
-*Copyright (c) 2019-2020, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/components/secure-partition-manager-mm.rst b/docs/components/secure-partition-manager-mm.rst
index d532901..30312ee 100644
--- a/docs/components/secure-partition-manager-mm.rst
+++ b/docs/components/secure-partition-manager-mm.rst
@@ -6,7 +6,7 @@
Two implementations of a Secure Partition Manager co-exist in the TF-A codebase:
-- SPM based on the PSA FF-A specification (:ref:`Secure Partition Manager`).
+- SPM based on the FF-A specification (:ref:`Secure Partition Manager`).
- SPM based on the MM interface.
Both implementations differ in their architectures and only one can be selected
@@ -822,7 +822,7 @@
--------------
-*Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.*
.. _Armv8-A ARM: https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile
.. _instructions in the EDK2 repository: https://github.com/tianocore/edk2-staging/blob/AArch64StandaloneMm/HowtoBuild.MD
diff --git a/docs/components/secure-partition-manager.rst b/docs/components/secure-partition-manager.rst
index 9a65e64..a5e7e8e 100644
--- a/docs/components/secure-partition-manager.rst
+++ b/docs/components/secure-partition-manager.rst
@@ -7,6 +7,10 @@
========
+--------+-----------------------------------+
+| CoT | Chain of Trust |
++--------+-----------------------------------+
+| DMA | Direct Memory Access |
++--------+-----------------------------------+
| DTB | Device Tree Blob |
+--------+-----------------------------------+
| DTS | Device Tree Source |
@@ -15,7 +19,7 @@
+--------+-----------------------------------+
| FIP | Firmware Image Package |
+--------+-----------------------------------+
-| FF-A | Firmware Framework for A-class |
+| FF-A | Firmware Framework for Armv8-A |
+--------+-----------------------------------+
| IPA | Intermediate Physical Address |
+--------+-----------------------------------+
@@ -29,12 +33,16 @@
+--------+-----------------------------------+
| PE | Processing Element |
+--------+-----------------------------------+
+| PM | Power Management |
++--------+-----------------------------------+
| PVM | Primary VM |
+--------+-----------------------------------+
-| PSA | Platform Security Architecture |
+| SMMU | System Memory Management Unit |
+--------+-----------------------------------+
| SP | Secure Partition |
+--------+-----------------------------------+
+| SPD | Secure Payload Dispatcher |
++--------+-----------------------------------+
| SPM | Secure Partition Manager |
+--------+-----------------------------------+
| SPMC | SPM Core |
@@ -57,111 +65,117 @@
Two implementations of a Secure Partition Manager co-exist in the TF-A codebase:
-- SPM based on the PSA FF-A specification `[1]`_.
-- SPM based on the MM interface to communicate with an S-EL0 partition `[2]`_.
+- SPM based on the FF-A specification `[1]`_.
+- SPM based on the MM interface to communicate with an S-EL0 partition `[2]`_.
Both implementations differ in their architectures and only one can be selected
at build time.
This document:
-- describes the PSA FF-A implementation where the Secure Partition Manager
- resides at EL3 and S-EL2 (or EL3 and S-EL1).
-- is not an architecture specification and it might provide assumptions
- on sections mandated as implementation-defined in the specification.
-- covers the implications to TF-A used as a bootloader, and Hafnium
- used as a reference code base for an S-EL2 secure firmware on
- platforms implementing Armv8.4-SecEL2.
+- describes the FF-A implementation where the Secure Partition Manager
+ resides at EL3 and S-EL2 (or EL3 and S-EL1).
+- is not an architecture specification and it might provide assumptions
+ on sections mandated as implementation-defined in the specification.
+- covers the implications to TF-A used as a bootloader, and Hafnium
+ used as a reference code base for an S-EL2 secure firmware on
+ platforms implementing the FEAT_SEL2 (formerly Armv8.4 Secure EL2)
+ architecture extension.
Terminology
-----------
-- Hypervisor refers to the NS-EL2 component managing Virtual Machines (or
- partitions) in the Normal World.
-- SPMC refers to the S-EL2 component managing Virtual Machines (or Secure
- Partitions) in the Secure World when Armv8.4-SecEL2 extension is implemented.
-- Alternatively, SPMC can refer to an S-EL1 component, itself being a Secure
- Partition and implementing the FF-A ABI on pre-Armv8.4 platforms.
-- VM refers to a Normal World Virtual Machine managed by an Hypervisor.
-- SP refers to a Secure World "Virtual Machine" managed by the SPMC component.
+- The term Hypervisor refers to the NS-EL2 component managing Virtual Machines
+ (or partitions) in the normal world.
+- The term SPMC refers to the S-EL2 component managing secure partitions in
+ the secure world when the FEAT_SEL2 architecture extension is implemented.
+- Alternatively, SPMC can refer to an S-EL1 component, itself being a secure
+ partition and implementing the FF-A ABI on platforms not implementing the
+ FEAT_SEL2 architecture extension.
+- The term VM refers to a normal world Virtual Machine managed by an Hypervisor.
+- The term SP refers to a secure world "Virtual Machine" managed by an SPMC.
Support for legacy platforms
----------------------------
-In the implementation, the SPM is split into SPMD and SPMC components
-(although not strictly mandated by the specification). SPMD is located
-at EL3 and principally relays FF-A messages from NWd (Hypervisor or OS
-kernel) to SPMC located either at S-EL1 or S-EL2.
+In the implementation, the SPM is split into SPMD and SPMC components.
+The SPMD is located at EL3 and mainly relays FF-A messages from
+NWd (Hypervisor or OS kernel) to SPMC located either at S-EL1 or S-EL2.
-Hence TF-A must support both cases where SPMC is either located at:
+Hence TF-A supports both cases where the SPMC is located either at:
-- S-EL1 supporting pre-Armv8.4 platforms. SPMD conveys FF-A protocol
- from EL3 to S-EL1.
-- S-EL2 supporting platforms implementing Armv8.4-SecEL2 extension.
- SPMD conveys FF-A protocol from EL3 to S-EL2.
+- S-EL1 supporting platforms not implementing the FEAT_SEL2 architecture
+ extension. The SPMD relays the FF-A protocol from EL3 to S-EL1.
+- or S-EL2 supporting platforms implementing the FEAT_SEL2 architecture
+ extension. The SPMD relays the FF-A protocol from EL3 to S-EL2.
-The same SPMD component is used to support both configurations. The SPMC
-execution level is a build time choice.
+The same TF-A SPMD component is used to support both configurations.
+The SPMC exception level is a build time choice.
Sample reference stack
======================
-The following diagram illustrates a possible configuration with SPMD and SPMC,
-one or multiple Secure Partitions, with or without an optional Hypervisor:
+The following diagram illustrates a possible configuration when the
+FEAT_SEL2 architecture extension is implemented, showing the SPMD
+and SPMC, one or multiple secure partitions, with an optional
+Hypervisor:
.. image:: ../resources/diagrams/ff-a-spm-sel2.png
TF-A build options
==================
-The following TF-A build options are provisioned:
+This section explains the TF-A build options involved in building with
+support for an FF-A based SPM where the SPMD is located at EL3 and the
+SPMC located at S-EL1 or S-EL2:
-- **SPD=spmd**: this option selects the SPMD component to relay FF-A
- protocol from NWd to SWd back and forth. It is not possible to
- enable another Secure Payload Dispatcher when this option is chosen.
-- **SPMD_SPM_AT_SEL2**: this option adjusts the SPMC execution
- level to being S-EL1 or S-EL2. It defaults to enabled (value 1) when
- SPD=spmd is chosen.
-- **CTX_INCLUDE_EL2_REGS**: this option permits saving (resp.
- restoring) the EL2 system register context before entering (resp.
- after leaving) the SPMC. It is mandatory when ``SPMD_SPM_AT_SEL2`` is
- enabled. The context save/restore routine and exhaustive list of
- registers is visible at `[4]`_.
-- **SP_LAYOUT_FILE**: this option provides a text description file
- providing paths to SP binary images and DTS format manifests
- (see `Specifying partition binary image and DT`_). It
- is required when ``SPMD_SPM_AT_SEL2`` is enabled hence when multiple
- secure partitions are to be loaded on behalf of SPMC.
+- **SPD=spmd**: this option selects the SPMD component to relay the FF-A
+ protocol from NWd to SWd back and forth. It is not possible to
+ enable another Secure Payload Dispatcher when this option is chosen.
+- **SPMD_SPM_AT_SEL2**: this option adjusts the SPMC exception
+ level to being S-EL1 or S-EL2. It defaults to enabled (value 1) when
+ SPD=spmd is chosen.
+- **CTX_INCLUDE_EL2_REGS**: this option permits saving (resp.
+ restoring) the EL2 system register context before entering (resp.
+ after leaving) the SPMC. It is mandatorily enabled when
+ ``SPMD_SPM_AT_SEL2`` is enabled. The context save/restore routine
+ and exhaustive list of registers is visible at `[4]`_.
+- **SP_LAYOUT_FILE**: this option specifies a text description file
+ providing paths to SP binary images and manifests in DTS format
+ (see `Describing secure partitions`_). It
+ is required when ``SPMD_SPM_AT_SEL2`` is enabled hence when multiple
+ secure partitions are to be loaded on behalf of the SPMC.
-+------------------------------+----------------------+------------------+
-| | CTX_INCLUDE_EL2_REGS | SPMD_SPM_AT_SEL2 |
-+------------------------------+----------------------+------------------+
-| SPMC at S-EL1 (e.g. OP-TEE) | 0 | 0 |
-+------------------------------+----------------------+------------------+
-| SPMC at S-EL2 (e.g. Hafnium) | 1 | 1 (default when |
-| | | SPD=spmd) |
-+------------------------------+----------------------+------------------+
++---------------+----------------------+------------------+
+| | CTX_INCLUDE_EL2_REGS | SPMD_SPM_AT_SEL2 |
++---------------+----------------------+------------------+
+| SPMC at S-EL1 | 0 | 0 |
++---------------+----------------------+------------------+
+| SPMC at S-EL2 | 1 | 1 (default when |
+| | | SPD=spmd) |
++---------------+----------------------+------------------+
Other combinations of such build options either break the build or are not
supported.
-Note, the ``CTX_INCLUDE_EL2_REGS`` option provides the generic support for
-barely saving/restoring EL2 registers from an Arm arch perspective. As such
-it is decoupled from the ``SPD=spmd`` option.
+Notes:
-BL32 option is re-purposed to specify the SPMC image. It can specify either the
-Hafnium binary path (built for the secure world) or the path to a TEE binary
-implementing the FF-A protocol.
-
-BL33 option can specify either:
-
-- the TFTF binary or
-- the Hafnium binary path (built for the normal world) if VMs were loaded by
- TF-A beforehand or
-- a minimal loader performing the loading of VMs and Hafnium.
+- Only Arm's FVP platform is supported to use with the TF-A reference software
+ stack.
+- The reference software stack uses FEAT_PAuth (formerly Armv8.3-PAuth) and
+ FEAT_BTI (formerly Armv8.5-BTI) architecture extensions by default at EL3
+ and S-EL2.
+- The ``CTX_INCLUDE_EL2_REGS`` option provides the generic support for
+ barely saving/restoring EL2 registers from an Arm arch perspective. As such
+ it is decoupled from the ``SPD=spmd`` option.
+- BL32 option is re-purposed to specify the SPMC image. It can specify either
+ the Hafnium binary path (built for the secure world) or the path to a TEE
+ binary implementing FF-A interfaces.
+- BL33 option can specify the TFTF binary or a normal world loader
+ such as U-Boot or the UEFI framework.
Sample TF-A build command line when SPMC is located at S-EL1
-(typically pre-Armv8.4):
+(e.g. when the FEAT_EL2 architecture extension is not implemented):
.. code:: shell
@@ -170,67 +184,108 @@
SPD=spmd \
SPMD_SPM_AT_SEL2=0 \
BL32=<path-to-tee-binary> \
- BL33=<path-to-nwd-binary> \
+ BL33=<path-to-bl33-binary> \
PLAT=fvp \
all fip
-Sample TF-A build command line for an Armv8.4-SecEL2 enabled system
-where SPMC is located at S-EL2:
+Sample TF-A build command line for a FEAT_SEL2 enabled system where the SPMC is
+located at S-EL2:
.. code:: shell
make \
CROSS_COMPILE=aarch64-none-elf- \
+ PLAT=fvp \
SPD=spmd \
CTX_INCLUDE_EL2_REGS=1 \
- ARM_ARCH_MINOR=4 \
- BL32=<path-to-swd-hafnium-binary>
- BL33=<path-to-nwd-binary> \
+ ARM_ARCH_MINOR=5 \
+ BRANCH_PROTECTION=1 \
+ CTX_INCLUDE_PAUTH_REGS=1 \
+ BL32=<path-to-hafnium-binary> \
+ BL33=<path-to-bl33-binary> \
SP_LAYOUT_FILE=sp_layout.json \
- PLAT=fvp \
all fip
-Build options to enable secure boot:
+Same as above with enabling secure boot in addition:
.. code:: shell
make \
CROSS_COMPILE=aarch64-none-elf- \
+ PLAT=fvp \
SPD=spmd \
CTX_INCLUDE_EL2_REGS=1 \
- ARM_ARCH_MINOR=4 \
- BL32=<path-to-swd-hafnium-binary>
- BL33=<path-to-nwd-binary> \
- SP_LAYOUT_FILE=../tf-a-tests/build/fvp/debug/sp_layout.json \
+ ARM_ARCH_MINOR=5 \
+ BRANCH_PROTECTION=1 \
+ CTX_INCLUDE_PAUTH_REGS=1 \
+ BL32=<path-to-hafnium-binary> \
+ BL33=<path-to-bl33-binary> \
+ SP_LAYOUT_FILE=sp_layout.json \
MBEDTLS_DIR=<path-to-mbedtls-lib> \
TRUSTED_BOARD_BOOT=1 \
COT=dualroot \
ARM_ROTPK_LOCATION=devel_rsa \
ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
GENERATE_COT=1 \
- PLAT=fvp \
all fip
+FVP model invocation
+====================
+
+The FVP command line needs the following options to exercise the S-EL2 SPMC:
+
++---------------------------------------------------+------------------------------------+
+| - cluster0.has_arm_v8-5=1 | Implements FEAT_SEL2, FEAT_PAuth, |
+| - cluster1.has_arm_v8-5=1 | and FEAT_BTI. |
++---------------------------------------------------+------------------------------------+
+| - pci.pci_smmuv3.mmu.SMMU_AIDR=2 | Parameters required for the |
+| - pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B | SMMUv3.2 modeling. |
+| - pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002 | |
+| - pci.pci_smmuv3.mmu.SMMU_IDR3=0x1714 | |
+| - pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0472 | |
+| - pci.pci_smmuv3.mmu.SMMU_S_IDR1=0xA0000002 | |
+| - pci.pci_smmuv3.mmu.SMMU_S_IDR2=0 | |
+| - pci.pci_smmuv3.mmu.SMMU_S_IDR3=0 | |
++---------------------------------------------------+------------------------------------+
+| - cluster0.has_branch_target_exception=1 | Implements FEAT_BTI. |
+| - cluster1.has_branch_target_exception=1 | |
++---------------------------------------------------+------------------------------------+
+| - cluster0.restriction_on_speculative_execution=2 | Required by the EL2 context |
+| - cluster1.restriction_on_speculative_execution=2 | save/restore routine. |
++---------------------------------------------------+------------------------------------+
+
+Sample FVP command line invocation:
+
+.. code:: shell
+
+ <path-to-fvp-model>/FVP_Base_RevC-2xAEMv8A -C pctl.startup=0.0.0.0
+ -C cluster0.NUM_CORES=4 -C cluster1.NUM_CORES=4 -C bp.secure_memory=1 \
+ -C bp.secureflashloader.fname=trusted-firmware-a/build/fvp/debug/bl1.bin \
+ -C bp.flashloader0.fname=trusted-firmware-a/build/fvp/debug/fip.bin \
+ -C bp.pl011_uart0.out_file=fvp-uart0.log -C bp.pl011_uart1.out_file=fvp-uart1.log \
+ -C bp.pl011_uart2.out_file=fvp-uart2.log \
+ -C cluster0.has_arm_v8-5=1 -C cluster1.has_arm_v8-5=1 -C pci.pci_smmuv3.mmu.SMMU_AIDR=2 \
+ -C pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B -C pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002 \
+ -C pci.pci_smmuv3.mmu.SMMU_IDR3=0x1714 -C pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0472 \
+ -C pci.pci_smmuv3.mmu.SMMU_S_IDR1=0xA0000002 -C pci.pci_smmuv3.mmu.SMMU_S_IDR2=0 \
+ -C pci.pci_smmuv3.mmu.SMMU_S_IDR3=0 \
+ -C cluster0.has_branch_target_exception=1 \
+ -C cluster1.has_branch_target_exception=1 \
+ -C cluster0.restriction_on_speculative_execution=2 \
+ -C cluster1.restriction_on_speculative_execution=2
+
Boot process
============
-Loading Hafnium and Secure Partitions in the secure world
+Loading Hafnium and secure partitions in the secure world
---------------------------------------------------------
-The Hafnium implementation in normal world requires VMs to be loaded in
-memory prior to booting. The mechanism upon which VMs are loaded and
-exposed to Hafnium are either:
+TF-A BL2 is the bootlader for the SPMC and SPs in the secure world.
-- by supplying a ramdisk image where VM images are concatenated (1)
-- or by providing VM load addresses within Hafnium manifest (2)
-
-TF-A is the bootlader for the Hafnium and SPs in the secure world. TF-A
-does not provide tooling or libraries manipulating ramdisks as required
-by (1). Thus BL2 loads SPs payloads independently.
SPs may be signed by different parties (SiP, OEM/ODM, TOS vendor, etc.).
-Thus they are supplied as distinct “self-contained” signed entities within
-the FIP flash image. The FIP image itself is not signed hence providing
-ability to upgrade SPs in the field.
+Thus they are supplied as distinct signed entities within the FIP flash
+image. The FIP image itself is not signed hence this provides the ability
+to upgrade SPs in the field.
Booting through TF-A
--------------------
@@ -239,26 +294,27 @@
~~~~~~~~~~~~
An SP manifest describes SP attributes as defined in `[1]`_
-section 3.1 (partition manifest at virtual FF-A instance) in DTS text format. It
-is represented as a single file associated with the SP. A sample is
+(partition manifest at virtual FF-A instance) in DTS format. It is
+represented as a single file associated with the SP. A sample is
provided by `[5]`_. A binding document is provided by `[6]`_.
Secure Partition packages
~~~~~~~~~~~~~~~~~~~~~~~~~
-Secure Partitions are bundled as independent package files consisting
+Secure partitions are bundled as independent package files consisting
of:
-- a header
-- a DTB
-- an image payload
+- a header
+- a DTB
+- an image payload
The header starts with a magic value and offset values to SP DTB and
image payload. Each SP package is loaded independently by BL2 loader
and verified for authenticity and integrity.
-The SP package identified by its UUID (matching FF-A uuid) is inserted
-as a single entry into the FIP at end of the TF-A build flow as shown:
+The SP package identified by its UUID (matching FF-A uuid property) is
+inserted as a single entry into the FIP at end of the TF-A build flow
+as shown:
.. code:: shell
@@ -276,18 +332,17 @@
.. uml:: ../resources/diagrams/plantuml/fip-secure-partitions.puml
-Specifying partition binary image and DT
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Describing secure partitions
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-A description file (json format) is passed to the build flow specifying
-paths to the SP binary image and associated DTS partition manifest file.
-The latter is going through the dtc compiler to generate the dtb fed into
-the SP package.
-This file also specifies the owner of the SP, which is an optional field and
-identifies the signing domain in case of dualroot CoT.
-The possible owner of an SP could either be Silicon Provider or Platform, and
-the corresponding "owner" field value could either be "SiP" or "Plat".
-In absence of "owner" field, it defaults to "SiP".
+A json-formatted description file is passed to the build flow specifying paths
+to the SP binary image and associated DTS partition manifest file. The latter
+is processed by the dtc compiler to generate a DTB fed into the SP package.
+This file also specifies the SP owner (as an optional field) identifying the
+signing domain in case of dual root CoT.
+The SP owner can either be the silicon or the platform provider. The
+corresponding "owner" field value can either take the value of "SiP" or "Plat".
+In absence of "owner" field, it defaults to "SiP" owner.
.. code:: shell
@@ -308,14 +363,16 @@
SPMC manifest
~~~~~~~~~~~~~
-This manifest contains an SPMC attributes node consumed by SPMD at boot time. It
-is implementing the description from `[1]`_ section 3.2 (SP manifest at physical
-FF-A instance). The SP manifest at physical FF-A instance is used by the SPMD to
-setup a SP that co-resides with the SPMC and executes at S-EL1 or Secure
-Supervisor mode.
+This manifest contains the SPMC *attribute* node consumed by the SPMD at boot
+time. It implements `[1]`_ (SP manifest at physical FF-A instance) and serves
+two different cases:
-In this implementation its usage is extended to the secure physical FF-A
-instance where SPMC executes at S-EL2.
+- The SPMC resides at S-EL1: the SPMC manifest is used by the SPMD to setup a
+ SP that co-resides with the SPMC and executes at S-EL1 or Secure Supervisor
+ mode.
+- The SPMC resides at S-EL2: the SPMC manifest is used by the SPMD to setup
+ the environment required by the SPMC to run at S-EL2. SPs run at S-EL1 or
+ S-EL0.
.. code:: shell
@@ -329,28 +386,28 @@
binary_size = <0x60000>;
};
-- *spmc_id* defines the endpoint ID value that SPMC can query through
- ``FFA_ID_GET``.
-- *maj_ver/min_ver*. SPMD checks provided version versus its internal
- version and aborts if not matching.
-- *exec_state* defines SPMC execution state (can be AArch64 for
- Hafnium, or AArch64/AArch32 for OP-TEE at S-EL1).
-- *load_address* and *binary_size* are mostly used to verify secondary
- entry points fit into the loaded binary image.
-- *entrypoint* defines the cold boot primary core entry point used by
- SPMD (currently matches ``BL32_BASE``)
+- *spmc_id* defines the endpoint ID value that SPMC can query through
+ ``FFA_ID_GET``.
+- *maj_ver/min_ver*. SPMD checks provided version versus its internal
+ version and aborts if not matching.
+- *exec_state* defines the SPMC execution state (AArch64 or AArch32).
+ Notice Hafnium used as a SPMC only supports AArch64.
+- *load_address* and *binary_size* are mostly used to verify secondary
+ entry points fit into the loaded binary image.
+- *entrypoint* defines the cold boot primary core entry point used by
+ SPMD (currently matches ``BL32_BASE``) to enter the SPMC.
Other nodes in the manifest are consumed by Hafnium in the secure world.
A sample can be found at [7]:
-- The *chosen* node is currently unused in SWd. It is meant for NWd to
- specify the init ramdisk image.
-- The *hypervisor* node describes SPs. *is_ffa_partition* boolean
- attribute indicates an SP. Load-addr field specifies the load address
- at which TF-A loaded the SP package.
-- *cpus* node provide the platform topology and allows MPIDR to VMPIDR
- mapping. Notice with current implementation primary cpu is declared
- first, then secondary cpus must be declared in reverse order.
+- The *hypervisor* node describes SPs. *is_ffa_partition* boolean attribute
+ indicates a FF-A compliant SP. The *load_address* field specifies the load
+ address at which TF-A loaded the SP package.
+- *cpus* node provide the platform topology and allows MPIDR to VMPIDR mapping.
+ Note the primary core is declared first, then secondary core are declared
+ in reverse order.
+- The *memory* node provides platform information on the ranges of memory
+ available to the SPMC.
SPMC boot
~~~~~~~~~
@@ -361,134 +418,111 @@
BL2 passes the SPMC manifest address to BL31 through a register.
-BL31(SPMD) runs from primary core, initializes the core contexts and
-launches BL32 passing the SPMC manifest address through a register.
+At boot time, the SPMD in BL31 runs from the primary core, initializes the core
+contexts and launches the SPMC (BL32) passing the SPMC manifest address through
+a register.
Loading of SPs
~~~~~~~~~~~~~~
+At boot time, BL2 loads SPs sequentially in addition to the SPMC as depicted
+below:
+
.. uml:: ../resources/diagrams/plantuml/bl2-loading-sp.puml
-
-Notice this boot flow is an implementation sample on Arm's FVP platform. Platforms
-not using FW_CONFIG would adjust to a different implementation.
+Note this boot flow is an implementation sample on Arm's FVP platform.
+Platforms not using TF-A's *Firmware CONFiguration* framework would adjust to a
+different implementation.
Secure boot
~~~~~~~~~~~
The SP content certificate is inserted as a separate FIP item so that BL2 loads SPMC,
-SPMC manifest and Secure Partitions and verifies them for authenticity and integrity.
+SPMC manifest, secure partitions and verifies them for authenticity and integrity.
Refer to TBBR specification `[3]`_.
-The multiple-signing domain feature (in current state dual signing domain) allows
-the use of two root keys namely S-ROTPK and NS-ROTPK (see `[8]`_):
+The multiple-signing domain feature (in current state dual signing domain `[8]`_) allows
+the use of two root keys namely S-ROTPK and NS-ROTPK:
-- SPMC (BL32) and SPMC manifest are signed by the SiP using the S-ROTPK.
-- BL33 may be signed by the OEM using NS-ROTPK.
-- An SP may be signed either by SiP (using S-ROTPK) or by OEM (using NS-ROTPK).
+- SPMC (BL32) and SPMC manifest are signed by the SiP using the S-ROTPK.
+- BL33 may be signed by the OEM using NS-ROTPK.
+- An SP may be signed either by SiP (using S-ROTPK) or by OEM (using NS-ROTPK).
-Longer term multiple signing domain will allow additional signing keys, e.g.
-if SPs originate from different parties.
-
-See `TF-A build options`_ for a sample build command line.
+Also refer to `Describing secure partitions`_ and `TF-A build options`_ sections.
Hafnium in the secure world
===========================
-**NOTE: this section is work in progress. Descriptions and implementation choices
-are subject to evolve.**
-
General considerations
----------------------
Build platform for the secure world
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-The implementation might add specific code parts only relevant to the
-secure world. Such code parts might be isolated into different files
-and/or conditional code enclosed by a ``SECURE_WORLD`` macro.
+In the Hafnium reference implementation specific code parts are only relevant to
+the secure world. Such portions are isolated in architecture specific files
+and/or enclosed by a ``SECURE_WORLD`` macro.
-Secure Partitions CPU scheduling
+Secure partitions CPU scheduling
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-In the normal world, VMs are scheduled by the FFA_RUN ABI invoked from the
-primary scheduler (in the primary VM), or by a direct message request or
-response.
+The FF-A v1.0 specification `[1]`_ provides two ways to relinquinsh CPU time to
+secure partitions. For this a VM (Hypervisor or OS kernel), or SP invokes one of:
-With the FF-A EAC specification, Secure Partitions are scheduled by direct
-message invocations from a NWd VM or another SP.
+- the FFA_MSG_SEND_DIRECT_REQ interface.
+- the FFA_RUN interface.
Platform topology
~~~~~~~~~~~~~~~~~
-As stated in `[1]`_ section 4.4.1 the SPMC implementation assumes the
+The *execution-ctx-count* SP manifest field can take the value of one or the
+total number of PEs. The FF-A v1.0 specification `[1]`_ recommends the
following SP types:
-- Pinned MP SPs: an Execution Context id matches a physical PE id. MP
- SPs must implement the same number of ECs as the number of PEs in the
- platform. Hence the *execution-ctx-count* as defined by
- `[1]`_ (or NWd-Hafnium *vcpu_count*) can only take the
- value of one or the number of physical PEs.
-- Migratable UP SPs: a single execution context can run and be migrated
- on any physical PE. It declares a single EC in its SP manifest. An UP
- SP can receive a direct message request on any physical core.
-
-Usage of PSCI services in the secure world
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-- The normal world Hypervisor (optional) or OS kernel issues PSCI service
- invocations e.g. to request PSCI version, wake-up a secondary core, or request
- core suspend. This happens at the non-secure physical FF-A instance. In the
- example case of Hafnium in the normal world, it boots on the primary core and
- one of the first initialization step is to request the PSCI version. It then
- launches the primary VM. The primary VM upon initializing performs PSCI service
- calls (at non-secure virtual FF-A instance) which are trapped by the
- Hypervisor. Invocation from OS Kernel ends straight at EL3. The PVM issues
- ``PSCI_CPU_ON`` service calls to wake-up secondary cores by passing an
- ``MPIDR``, entry point address and a CPU context address. The EL3 PSCI layer
- then performs an exception return to the secondary core entry point on the
- targeted core. Other PSCI calls can happen at run-time from the PVM e.g. to
- request core suspend.
-- In the existing TF-A PSCI standard library, PSCI service calls are filtered at
- EL3 to only originate from the NWd. Thus concerning the SPMC (at secure
- physical FF-A instance) the PSCI service invocations cannot happen as in the
- normal world. For example, a ``PSCI_CPU_ON`` service invocation from the SPMC
- does not reach the PSCI layer.
+- Pinned MP SPs: an execution context matches a physical PE. MP SPs must
+ implement the same number of ECs as the number of PEs in the platform.
+- Migratable UP SPs: a single execution context can run and be migrated on any
+ physical PE. Such SP declares a single EC in its SP manifest. An UP SP can
+ receive a direct message request originating from any physical core targeting
+ the single execution context.
Parsing SP partition manifests
------------------------------
-Hafnium must be able to consume SP manifests as defined in
-`[1]`_ section 3.1, at least for the mandatory fields.
+Hafnium consumes SP manifests as defined in `[1]`_ and `SP manifests`_.
+Note the current implementation may not implement all optional fields.
-The SP manifest may contain memory and device regions nodes.
+The SP manifest may contain memory and device regions nodes. In case of
+an S-EL2 SPMC:
-- Memory regions shall be mapped in the SP Stage-2 translation regime at
- load time. A memory region node can specify RX/TX buffer regions in which
- case it is not necessary for an SP to explicitly call the ``FFA_RXTX_MAP``
- service.
-- Device regions shall be mapped in SP Stage-2 translation regime as
- peripherals and possibly allocate additional resources (e.g. interrupts)
+- Memory regions are mapped in the SP EL1&0 Stage-2 translation regime at
+ load time (or EL1&0 Stage-1 for an S-EL1 SPMC). A memory region node can
+ specify RX/TX buffer regions in which case it is not necessary for an SP
+ to explicitly invoke the ``FFA_RXTX_MAP`` interface.
+- Device regions are mapped in the SP EL1&0 Stage-2 translation regime (or
+ EL1&0 Stage-1 for an S-EL1 SPMC) as peripherals and possibly allocate
+ additional resources (e.g. interrupts).
-Base addresses for memory and device region nodes are IPAs provided SPMC
-identity maps IPAs to PAs within SP Stage-2 translation regime.
+For the S-EL2 SPMC, base addresses for memory and device region nodes are IPAs
+provided the SPMC identity maps IPAs to PAs within SP EL1&0 Stage-2 translation
+regime.
-Note: currently both VTTBR_EL2 and VSTTBR_EL2 resolve to the same set of page
-tables. It is still open whether two sets of page tables shall be provided per
-SP. The memory region node as defined in the spec (section 3.1 Table 10)
+Note: in the current implementation both VTTBR_EL2 and VSTTBR_EL2 point to the
+same set of page tables. It is still open whether two sets of page tables shall
+be provided per SP. The memory region node as defined in the specification
provides a memory security attribute hinting to map either to the secure or
-non-secure stage-2 table.
+non-secure EL1&0 Stage-2 table if it exists.
Passing boot data to the SP
---------------------------
-`[1]`_ Section 3.4.2 “Protocol for passing data” defines a
-method to passing boot data to SPs (not currently implemented).
+In `[1]`_ , the "Protocol for passing data" section defines a method for passing
+boot data to SPs (not currently implemented).
-Provided that the whole Secure Partition package image (see `Secure
-Partition packages`_) is mapped to the SP's secure Stage-2 translation
-regime, an SP can access its own manifest DTB blob and extract its partition
-manifest properties.
+Provided that the whole secure partition package image (see
+`Secure Partition packages`_) is mapped to the SP secure EL1&0 Stage-2
+translation regime, an SP can access its own manifest DTB blob and extract its
+partition manifest properties.
SP Boot order
-------------
@@ -497,347 +531,396 @@
dependencies such as an SP providing a service required to properly boot
another SP.
+It is possible for an SP to call into another SP through a direct request
+provided the latter SP has already been booted.
+
Boot phases
-----------
Primary core boot-up
~~~~~~~~~~~~~~~~~~~~
-The SPMC performs its platform initializations then loads and creates
-secure partitions based on SP packages and manifests. Then each secure
-partition is launched in sequence (see `SP Boot order`_) on their primary
-Execution Context.
+Upon boot-up, BL31 hands over to the SPMC (BL32) on the primary boot physical
+core. The SPMC performs its platform initializations and registers the SPMC
+secondary physical core entry point physical address by the use of the
+FFA_SECONDARY_EP_REGISTER interface (SMC invocation from the SPMC to the SPMD
+at secure physical FF-A instance). This interface is implementation-defined in
+context of FF-A v1.0.
-Notice the primary physical core may not be core 0. Hence if the primary
-core linear id is N, the 1:1 mapping requires MP SPs are launched using
-EC[N] on PE[N] (see `Platform topology`_).
+The SPMC then creates secure partitions based on SP packages and manifests. Each
+secure partition is launched in sequence (`SP Boot order`_) on their "primary"
+execution context. If the primary boot physical core linear id is N, an MP SP is
+started using EC[N] on PE[N] (see `Platform topology`_). If the partition is a
+UP SP, it is started using its unique EC0 on PE[N].
-The SP's primary Execution Context (or the EC used when the partition is booted)
-exits through ``FFA_MSG_WAIT`` to indicate successful initialization.
+The SP primary EC (or the EC used when the partition is booted as described
+above):
-Secondary physical core boot-up
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+- Performs the overall SP boot time initialization, and in case of a MP SP,
+ prepares the SP environment for other execution contexts.
+- In the case of a MP SP, it invokes the FFA_SECONDARY_EP_REGISTER at secure
+ virtual FF-A instance (SMC invocation from SP to SPMC) to provide the IPA
+ entry point for other execution contexts.
+- Exits through ``FFA_MSG_WAIT`` to indicate successful initialization or
+ ``FFA_ERROR`` in case of failure.
-Upon boot-up, the SPMC running on the primary core performs
-implementation-defined SPMD service calls at secure physical FF-A instance
-to register the secondary physical cores entry points and context information:
+Secondary cores boot-up
+~~~~~~~~~~~~~~~~~~~~~~~
-- This is done through a direct message request invocation to the SPMD
- (``SET_ENTRY_POINT``). This service call does not wake-up the targeted
- core immediately. The secondary core is woken up later by a NWd
- ``PSCI_CPU_ON`` service invocation. A notification is passed from EL3
- PSCI layer to the SPMD, and then to SPMC through an implementation-defined
- interface.
-- The SPMC/SPMD interface can consist of FF-A direct message requests/responses
- transporting PM events.
+Once the system is started and NWd brought up, a secondary physical core is
+woken up by the ``PSCI_CPU_ON`` service invocation. The TF-A SPD hook mechanism
+calls into the SPMD on the newly woken up physical core. Then the SPMC is
+entered at the secondary physical core entry point.
-If there is no Hypervisor in the normal world, the OS Kernel issues
-``PSCI_CPU_ON`` calls that are directly trapped to EL3.
+In the current implementation, the first SP is resumed on the coresponding EC
+(the virtual CPU which matches the physical core). The implication is that the
+first SP must be a MP SP.
-When a secondary physical core wakes-up the SPMD notifies the SPMC which updates
-its internal states reflecting current physical core is being turned on.
-It might then return straight to the SPMD and then to the NWd.
+In a linux based system, once secure and normal worlds are booted but prior to
+a NWd FF-A driver has been loaded:
-*(under discussion)* There may be possibility that an SP registers "PM events"
-(during primary EC boot stage) through an ad-hoc interface. Such events would
-be relayed by SPMC to one or more registered SPs on need basis
-(see `Power management`_).
+- The first SP has initialized all its ECs in response to primary core boot up
+ (at system initialization) and secondary core boot up (as a result of linux
+ invoking PSCI_CPU_ON for all secondary cores).
+- Other SPs have their first execution context initialized as a result of secure
+ world initialization on the primary boot core. Other ECs for those SPs have to
+ be run first through ffa_run to complete their initialization (which results
+ in the EC completing with FFA_MSG_WAIT).
-Secondary virtual core boot-up
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-In the example case where Hafnium exists in the normal world, secondary VMs
-issue a ``PSCI_CPU_ON`` service call which is trapped to the Hypervisor. The
-latter then enables the vCPU context for the targeted core, and switches to
-the PVM down to the kernel driver with an ``HF_WAKE_UP`` message. The NWd
-driver in PVM can then schedule the newly woken up vCPU context.
-
-In the secure world the primary EC of a given SP passes the secondary EC entry
-point and context. The SMC service call is trapped into the SPMC. This can be
-either *(under discussion)*:
-
-- a specific interface registering the secondary EC entry point,
- similarly to above ``SET_ENTRY_POINT`` service.
-- Re-purposing the ``PSCI_CPU_ON`` function id. It is
- assumed that even if the input arguments are the same as the ones defined in
- the PSCI standard, the usage deviates by the fact the secondary EC is not
- woken up immediately. At least for the PSA-FF-A EAC where only
- direct messaging is allowed, it is only after the first direct
- message invocation that the secondary EC is entered. This option
- might be preferred when the same code base is re-used for a VM or
- an SP. The ABI to wake-up a secondary EC can remain similar.
-
-SPs are always scheduled from the NWd, this paradigm did not change from legacy
-TEEs. There must always be some logic (or driver) in the NWd to relinquish CPU
-cycles to the SWd. If primary core is 0, an SP EC[x>0] entry point is supplied
-by the SP EC[0] when the system boots in SWd. But this EC[x] is not immediately
-entered at boot. Later in the boot process when NWd is up, a direct message
-request issued from physical core 1 ends up in SP EC[1], and only at this stage
-this context is effectively scheduled.
-
-It should be possible for an SP to call into another SP through direct message
-provided the latter SP has been booted already. The "boot-order" field in
-partition manifests (`SP Boot order`_) fulfills the dependency towards availability
-of a service within an SP offered to another SP.
+Refer to `Power management`_ for further details.
Mandatory interfaces
--------------------
-The following interfaces must be exposed to any VM or SP:
+The following interfaces are exposed to SPs:
-- ``FFA_STATUS``
-- ``FFA_ERROR``
-- ``FFA_INTERRUPT``
- ``FFA_VERSION``
- ``FFA_FEATURES``
- ``FFA_RX_RELEASE``
- ``FFA_RXTX_MAP``
-- ``FFA_RXTX_UNMAP``
+- ``FFA_RXTX_UNMAP`` (not implemented)
- ``FFA_PARTITION_INFO_GET``
- ``FFA_ID_GET``
+- ``FFA_MSG_WAIT``
+- ``FFA_MSG_SEND_DIRECT_REQ``
+- ``FFA_MSG_SEND_DIRECT_RESP``
+- ``FFA_MEM_DONATE``
+- ``FFA_MEM_LEND``
+- ``FFA_MEM_SHARE``
+- ``FFA_MEM_RETRIEVE_REQ``
+- ``FFA_MEM_RETRIEVE_RESP``
+- ``FFA_MEM_RELINQUISH``
+- ``FFA_MEM_RECLAIM``
+- ``FFA_SECONDARY_EP_REGISTER``
FFA_VERSION
~~~~~~~~~~~
-Per `[1]`_ section 8.1 ``FFA_VERSION`` requires a
-*requested_version* parameter from the caller.
+``FFA_VERSION`` requires a *requested_version* parameter from the caller.
+The returned value depends on the caller:
-In the current implementation when ``FFA_VERSION`` is invoked from:
-
-- Hypervisor in NS-EL2: the SPMD returns the SPMC version specified
- in the SPMC manifest.
-- OS kernel in NS-EL1 when NS-EL2 is not present: the SPMD returns the
- SPMC version specified in the SPMC manifest.
-- VM in NWd: the Hypervisor returns its implemented version.
-- SP in SWd: the SPMC returns its implemented version.
-- SPMC at S-EL1/S-EL2: the SPMD returns its implemented version.
+- Hypervisor or OS kernel in NS-EL1/EL2: the SPMD returns the SPMC version
+ specified in the SPMC manifest.
+- SP: the SPMC returns its own implemented version.
+- SPMC at S-EL1/S-EL2: the SPMD returns its own implemented version.
FFA_FEATURES
~~~~~~~~~~~~
-FF-A features may be discovered by Secure Partitions while booting
-through the SPMC. However, SPMC cannot get features from Hypervisor
-early at boot time as NS world is not setup yet.
+FF-A features supported by the SPMC may be discovered by secure partitions at
+boot (that is prior to NWd is booted) or run-time.
-The Hypervisor may decide to gather FF-A features from SPMC through SPMD
-once at boot time and store the result. Later when a VM requests FF-A
-features, the Hypervisor can adjust its own set of features with what
-SPMC advertised, if necessary. Another approach is to always forward FF-A
-features to the SPMC when a VM requests it to the Hypervisor. Although
-the result is not supposed to change over time so there may not be added
-value doing the systematic forwarding.
+The SPMC calling FFA_FEATURES at secure physical FF-A instance always get
+FFA_SUCCESS from the SPMD.
+
+The request made by an Hypervisor or OS kernel is forwarded to the SPMC and
+the response relayed back to the NWd.
FFA_RXTX_MAP/FFA_RXTX_UNMAP
~~~~~~~~~~~~~~~~~~~~~~~~~~~
-VM mailboxes are re-purposed to serve as SP RX/TX buffers. The RX/TX
-map API maps the send and receive buffer IPAs to the SP Stage-2 translation regime.
+When invoked from a secure partition FFA_RXTX_MAP maps the provided send and
+receive buffers described by their IPAs to the SP EL1&0 Stage-2 translation
+regime as secure buffers in the MMU descriptors.
-Hafnium in the normal world defines VMs and their attributes as logical structures,
-including a mailbox used for FF-A indirect messaging, memory sharing, or the
-`FFA_PARTITION_INFO_GET`_ ABI.
-This same mailbox structure is re-used in the SPMC. `[1]`_ states only direct
-messaging is allowed to SPs. Thus mailbox usage is restricted to implementing
-`FFA_PARTITION_INFO_GET`_ and memory sharing ABIs.
+When invoked from the Hypervisor or OS kernel, the buffers are mapped into the
+SPMC EL2 Stage-1 translation regime and marked as NS buffers in the MMU
+descriptors.
+
+Note:
+
+- FFA_RXTX_UNMAP is not implemented.
FFA_PARTITION_INFO_GET
~~~~~~~~~~~~~~~~~~~~~~
-Partition info get service call can originate:
+Partition info get call can originate:
-- from SP to SPM
-- from VM to Hypervisor
-- from Hypervisor to SPM
-
-For the latter case, the service call must be forwarded through the SPMD.
+- from SP to SPMC
+- from Hypervisor or OS kernel to SPMC. The request is relayed by the SPMD.
FFA_ID_GET
~~~~~~~~~~
-The SPMD returns:
-
-- a default zero value on invocation from the Hypervisor.
-- The ``spmc_id`` value specified in the SPMC manifest on invocation from
- the SPMC (see `SPMC manifest`_)
-
The FF-A id space is split into a non-secure space and secure space:
-- FF-A id with bit 15 clear refer to normal world VMs.
-- FF-A id with bit 15 set refer to secure world SPs
+- FF-A ID with bit 15 clear relates to VMs.
+- FF-A ID with bit 15 set related to SPs.
+- FF-A IDs 0, 0xffff, 0x8000 are assigned respectively to the Hypervisor, SPMD
+ and SPMC.
-Such convention helps the SPMC discriminating the origin and destination worlds
-in an FF-A service invocation. In particular the SPMC shall filter unauthorized
+The SPMD returns:
+
+- The default zero value on invocation from the Hypervisor.
+- The ``spmc_id`` value specified in the SPMC manifest on invocation from
+ the SPMC (see `SPMC manifest`_)
+
+This convention helps the SPMC to determine the origin and destination worlds in
+an FF-A ABI invocation. In particular the SPMC shall filter unauthorized
transactions in its world switch routine. It must not be permitted for a VM to
-use a secure FF-A id as origin world through spoofing:
+use a secure FF-A ID as origin world by spoofing:
-- A VM-to-SP messaging passing shall have an origin world being non-secure
- (FF-A id bit 15 clear) and destination world being secure (FF-A id bit 15
- set).
-- Similarly, an SP-to-SP message shall have FF-A id bit 15 set for both origin
- and destination ids.
+- A VM-to-SP direct request/response shall set the origin world to be non-secure
+ (FF-A ID bit 15 clear) and destination world to be secure (FF-A ID bit 15
+ set).
+- Similarly, an SP-to-SP direct request/response shall set the FF-A ID bit 15
+ for both origin and destination IDs.
An incoming direct message request arriving at SPMD from NWd is forwarded to
SPMC without a specific check. The SPMC is resumed through eret and "knows" the
message is coming from normal world in this specific code path. Thus the origin
-endpoint id must be checked by SPMC for being a normal world id.
+endpoint ID must be checked by SPMC for being a normal world ID.
An SP sending a direct message request must have bit 15 set in its origin
-endpoint id and this can be checked by the SPMC when the SP invokes the ABI.
+endpoint ID and this can be checked by the SPMC when the SP invokes the ABI.
The SPMC shall reject the direct message if the claimed world in origin endpoint
-id is not consistent:
+ID is not consistent:
-- It is either forwarded by SPMD and thus origin endpoint id must be a "normal
- world id",
-- or initiated by an SP and thus origin endpoint id must be a "secure world id".
+- It is either forwarded by SPMD and thus origin endpoint ID must be a "normal
+ world ID",
+- or initiated by an SP and thus origin endpoint ID must be a "secure world ID".
-Direct messaging
-----------------
-This is a mandatory interface for Secure Partitions consisting in direct
-message request and responses.
+FFA_MSG_SEND_DIRECT_REQ/FFA_MSG_SEND_DIRECT_RESP
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-The ``ffa_handler`` Hafnium function may:
+This is a mandatory interface for secure partitions consisting in direct request
+and responses with the following rules:
-- trigger a world change e.g. when an SP invokes the direct message
- response ABI to a VM.
-- handle multiple requests from the NWd without resuming an SP.
+- An SP can send a direct request to another SP.
+- An SP can receive a direct request from another SP.
+- An SP can send a direct response to another SP.
+- An SP cannot send a direct request to an Hypervisor or OS kernel.
+- An Hypervisor or OS kernel can send a direct request to an SP.
+- An SP can send a direct response to an Hypervisor or OS kernel.
-SP-to-SP
-~~~~~~~~
+SPMC-SPMD direct requests/responses
+-----------------------------------
-- An SP can send a direct message request to another SP
-- An SP can receive a direct message response from another SP.
+Implementation-defined FF-A IDs are allocated to the SPMC and SPMD.
+Using those IDs in source/destination fields of a direct request/response
+permits SPMD to SPMC communication and either way.
-VM-to-SP
-~~~~~~~~
+- SPMC to SPMD direct request/response uses SMC conduit.
+- SPMD to SPMC direct request/response uses ERET conduit.
-- A VM can send a direct message request to an SP
-- An SP can send a direct message response to a VM
+PE MMU configuration
+--------------------
-SPMC-SPMD messaging
-~~~~~~~~~~~~~~~~~~~
+With secure virtualization enabled, two IPA spaces are output from the secure
+EL1&0 Stage-1 translation (secure and non-secure). The EL1&0 Stage-2 translation
+hardware is fed by:
-Specific implementation-defined endpoint IDs are allocated to the SPMC and SPMD.
-Referring those IDs in source/destination fields of a direct message
-request/response permits SPMD to SPMC messaging back and forth.
+- A single secure IPA space when the SP EL1&0 Stage-1 MMU is disabled.
+- Two IPA spaces (secure and non-secure) when the SP EL1&0 Stage-1 MMU is
+ enabled.
-Per `[1]`_ Table 114 Config No. 1 (physical FF-A instance):
+``VTCR_EL2`` and ``VSTCR_EL2`` provide configuration bits for controlling the
+NS/S IPA translations.
+``VSTCR_EL2.SW`` = 0, ``VSTCR_EL2.SA`` = 0,``VTCR_EL2.NSW`` = 0, ``VTCR_EL2.NSA`` = 1:
-- SPMC=>SPMD direct message request uses SMC conduit
-- SPMD=>SPMC direct message request uses ERET conduit
+- Stage-2 translations for the NS IPA space access the NS PA space.
+- Stage-2 translation table walks for the NS IPA space are to the secure PA space.
-Per `[1]`_ Table 118 Config No. 1 (physical FF-A instance):
-
-- SPMC=>SPMD direct message response uses SMC conduit
-- SPMD=>SPMC direct message response uses ERET conduit
-
-Memory management
------------------
-
-This section only deals with the PE MMU configuration.
-
-Hafnium in the normal world deals with NS buffers only and provisions
-a single root page table directory to VMs. In context of S-EL2 enabled
-firmware, two IPA spaces are output from Stage-1 translation (secure
-and non-secure). The Stage-2 translation handles:
-
-- A single secure IPA space when an SP Stage-1 MMU is disabled.
-- Two IPA spaces (secure and non-secure) when Stage-1 MMU is enabled.
-
-``VTCR_EL2`` and ``VSTCR_EL2`` provide additional bits for controlling the
-NS/S IPA translations (``VSTCR_EL2.SW``, ``VSTCR_EL2.SA``, ``VTCR_EL2.NSW``,
-``VTCR_EL2.NSA``). There may be two approaches:
-
-- secure and non-secure mappings are rooted as two separate root page
- tables
-- secure and non-secure mappings use the same root page table. Access
- from S-EL1 to an NS region translates to a secure physical address
- space access.
+Secure and non-secure IPA regions use the same set of Stage-2 page tables within
+a SP.
Interrupt management
--------------------
-Road to a para-virtualized interface
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+GIC ownership
+~~~~~~~~~~~~~
-Current Hafnium implementation uses an ad-hoc mechanism for a VM to get
-a pending interrupt number through an hypercall. The PVM injects
-interrupts to VMs by delegation from the Hypervisor. The PVM probes a
-pending interrupt directly from the GIC distributor.
+The SPMC owns the GIC configuration. Secure and non-secure interrupts are
+trapped at S-EL2. The SPMC manages interrupt resources and allocates interrupt
+IDs based on SP manifests. The SPMC acknowledges physical interrupts and injects
+virtual interrupts by setting the use of vIRQ/vFIQ bits before resuming a SP.
-The short-term plan is to have Hafnium/SPMC in the secure world owner
-of the GIC configuration.
+Non-secure interrupt handling
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-The SPMC fully owns the GIC configuration at S-EL2. The SPMC manages
-interrupt resources and allocates interrupt ID based on SP manifests.
-The SPMC acknowledges physical interrupts and injects virtual interrupts
-by setting the vIRQ bit when resuming an SP. A Secure Partition gathers
-the interrupt number through an hypercall.
+The following illustrate the scenarios of non secure physical interrupts trapped
+by the SPMC:
-Notice the SPMC/SPMD has to handle Group0 secure interrupts in addition
-to Group1 S/NS interrupts.
+- The SP handles a managed exit operation:
+
+.. image:: ../resources/diagrams/ffa-ns-interrupt-handling-managed-exit.png
+
+- The SP is pre-empted without managed exit:
+
+.. image:: ../resources/diagrams/ffa-ns-interrupt-handling-sp-preemption.png
+
+Secure interrupt handling
+~~~~~~~~~~~~~~~~~~~~~~~~~
+
+The current implementation does not support handling of secure interrupts
+trapped by the SPMC at S-EL2. This is work in progress planned for future
+releases.
Power management
----------------
-Assumption on the Nwd:
+In platforms with or without secure virtualization:
-- NWd is the best candidate to own the platform Power Management
- policy. It is master to invoking PSCI service calls from physical
- CPUs.
-- EL3 monitor is in charge of the PM control part (its PSCI layer
- actually writing to platform registers).
-- It is fine for the Hypervisor to trap PSCI calls and relay to EL3, or
- OS kernel driver to emit PSCI service calls.
+- The NWd owns the platform PM policy.
+- The Hypervisor or OS kernel is the component initiating PSCI service calls.
+- The EL3 PSCI library is in charge of the PM coordination and control
+ (eventually writing to platform registers).
+- While coordinating PM events, the PSCI library calls backs into the Secure
+ Payload Dispatcher for events the latter has statically registered to.
-PSCI notification are relayed through the SPMD/SPD PM hooks to the SPMC.
-This can either be through re-use of PSCI FIDs or an FF-A direct message
-from SPMD to SPMC.
+When using the SPMD as a Secure Payload Dispatcher:
-The SPMD performs an exception return to the SPMC which is resumed to
-its ``eret_handler`` routine. It is then either consuming a PSCI FID or
-an FF-A FID. Depending on the servicing, the SPMC may return directly to
-the SPMD (and then NWd) without resuming an SP at this stage. An example
-of this is invocation of ``FFA_PARTITION_INFO_GET`` from NWd relayed by
-the SPMD to the SPMC. The SPMC returns the needed partition information
-to the SPMD (then NWd) without actually resuming a partition in secure world.
+- A power management event is relayed through the SPD hook to the SPMC.
+- In the current implementation only cpu on (svc_on_finish) and cpu off
+ (svc_off) hooks are registered.
+- The behavior for the cpu on event is described in `Secondary cores boot-up`_.
+ The SPMC is entered through its secondary physical core entry point.
+- The cpu off event occurs when the NWd calls PSCI_CPU_OFF. The method by which
+ the PM event is conveyed to the SPMC is implementation-defined in context of
+ FF-A v1.0 (`SPMC-SPMD direct requests/responses`_). It consists in a SPMD-to-SPMC
+ direct request/response conveying the PM event details and SPMC response.
+ The SPMD performs a synchronous entry into the SPMC. The SPMC is entered and
+ updates its internal state to reflect the physical core is being turned off.
+ In the current implementation no SP is resumed as a consequence. This behavior
+ ensures a minimal support for CPU hotplug e.g. when initiated by the NWd linux
+ userspace.
-*(under discussion)*
-About using PSCI FIDs from SPMD to SPMC to notify of PM events, it is still
-questioned what to use as the return code from the SPMC.
-If the function ID used by the SPMC is not an FF-A ID when doing SMC, then the
-EL3 std svc handler won't route the response to the SPMD. That's where comes the
-idea to embed the notification into an FF-A message. The SPMC can discriminate
-this message as being a PSCI event, process it, and reply with an FF-A return
-message that the SPMD receives as an acknowledgement.
+SMMUv3 support in Hafnium
+=========================
-SP notification
+An SMMU is analogous to an MMU in a CPU. It performs address translations for
+Direct Memory Access (DMA) requests from system I/O devices.
+The responsibilities of an SMMU include:
+
+- Translation: Incoming DMA requests are translated from bus address space to
+ system physical address space using translation tables compliant to
+ Armv8/Armv7 VMSA descriptor format.
+- Protection: An I/O device can be prohibited from read, write access to a
+ memory region or allowed.
+- Isolation: Traffic from each individial device can be independently managed.
+ The devices are differentiated from each other using unique translation
+ tables.
+
+The following diagram illustrates a typical SMMU IP integrated in a SoC with
+several I/O devices along with Interconnect and Memory system.
+
+.. image:: ../resources/diagrams/MMU-600.png
+
+SMMU has several versions including SMMUv1, SMMUv2 and SMMUv3. Hafnium provides
+support for SMMUv3 driver in both normal and secure world. A brief introduction
+of SMMUv3 functionality and the corresponding software support in Hafnium is
+provided here.
+
+SMMUv3 features
---------------
-Power management notifications are conveyed from PSCI library to the
-SPMD / SPD hooks. A range of events can be relayed to SPMC.
+- SMMUv3 provides Stage1, Stage2 translation as well as nested (Stage1 + Stage2)
+ translation support. It can either bypass or abort incoming translations as
+ well.
+- Traffic (memory transactions) from each upstream I/O peripheral device,
+ referred to as Stream, can be independently managed using a combination of
+ several memory based configuration structures. This allows the SMMUv3 to
+ support a large number of streams with each stream assigned to a unique
+ translation context.
+- Support for Armv8.1 VMSA where the SMMU shares the translation tables with
+ a Processing Element. AArch32(LPAE) and AArch64 translation table format
+ are supported by SMMUv3.
+- SMMUv3 offers non-secure stream support with secure stream support being
+ optional. Logically, SMMUv3 behaves as if there is an indepdendent SMMU
+ instance for secure and non-secure stream support.
+- It also supports sub-streams to differentiate traffic from a virtualized
+ peripheral associated with a VM/SP.
+- Additionally, SMMUv3.2 provides support for PEs implementing Armv8.4-A
+ extensions. Consequently, SPM depends on Secure EL2 support in SMMUv3.2
+ for providing Secure Stage2 translation support to upstream peripheral
+ devices.
-SPs may need to be notified about specific PM events.
+SMMUv3 Programming Interfaces
+-----------------------------
-- SPs might register PM events to the SPMC
-- On SPMD to SPMC notification, a limited range of SPs may be notified
- through a direct message.
-- This assumes the mentioned SPs supports managed exit.
+SMMUv3 has three software interfaces that are used by the Hafnium driver to
+configure the behaviour of SMMUv3 and manage the streams.
-The SPMC is the first to be notified about PM events from the SPMD. It is up
-to the SPMC to arbitrate to which SP it needs to send PM events.
-An SP explicitly registers to receive notifications to specific PM events.
-The register operation can either be an implementation-defined service call
-to the SPMC when the primary SP EC boots, or be supplied through the SP
-manifest.
+- Memory based data strutures that provide unique translation context for
+ each stream.
+- Memory based circular buffers for command queue and event queue.
+- A large number of SMMU configuration registers that are memory mapped during
+ boot time by Hafnium driver. Except a few registers, all configuration
+ registers have independent secure and non-secure versions to configure the
+ behaviour of SMMUv3 for translation of secure and non-secure streams
+ respectively.
+
+Peripheral device manifest
+--------------------------
+
+Currently, SMMUv3 driver in Hafnium only supports dependent peripheral devices.
+These devices are dependent on PE endpoint to initiate and receive memory
+management transactions on their behalf. The acccess to the MMIO regions of
+any such device is assigned to the endpoint during boot. Moreover, SMMUv3 driver
+uses the same stage 2 translations for the device as those used by partition
+manager on behalf of the PE endpoint. This ensures that the peripheral device
+has the same visibility of the physical address space as the endpoint. The
+device node of the corresponding partition manifest (refer to `[1]`_ section 3.2
+) must specify these additional properties for each peripheral device in the
+system :
+
+- smmu-id: This field helps to identify the SMMU instance that this device is
+ upstream of.
+- stream-ids: List of stream IDs assigned to this device.
+
+.. code:: shell
+
+ smmuv3-testengine {
+ base-address = <0x00000000 0x2bfe0000>;
+ pages-count = <32>;
+ attributes = <0x3>;
+ smmu-id = <0>;
+ stream-ids = <0x0 0x1>;
+ interrupts = <0x2 0x3>, <0x4 0x5>;
+ exclusive-access;
+ };
+
+SMMUv3 driver limitations
+-------------------------
+
+The primary design goal for the Hafnium SMMU driver is to support secure
+streams.
+
+- Currently, the driver only supports Stage2 translations. No support for
+ Stage1 or nested translations.
+- Supports only AArch64 translation format.
+- No support for features such as PCI Express (PASIDs, ATS, PRI), MSI, RAS,
+ Fault handling, Performance Monitor Extensions, Event Handling, MPAM.
+- No support for independent peripheral devices.
References
==========
.. _[1]:
-[1] `Platform Security Architecture Firmware Framework for Arm® v8-A 1.0 Platform Design Document <https://developer.arm.com/docs/den0077/latest>`__
+[1] `Arm Firmware Framework for Armv8-A <https://developer.arm.com/docs/den0077/latest>`__
.. _[2]:
@@ -846,7 +929,7 @@
.. _[3]:
[3] `Trusted Boot Board Requirements
-Client <https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a>`__
+Client <https://developer.arm.com/documentation/den0006/d/>`__
.. _[4]:
@@ -854,11 +937,11 @@
.. _[5]:
-[5] https://git.trustedfirmware.org/TF-A/tf-a-tests.git/tree/spm/cactus/cactus.dts
+[5] https://git.trustedfirmware.org/TF-A/tf-a-tests.git/tree/spm/cactus/plat/arm/fvp/fdts/cactus.dts
.. _[6]:
-[6] https://trustedfirmware-a.readthedocs.io/en/latest/components/psa-ffa-manifest-binding.html
+[6] https://trustedfirmware-a.readthedocs.io/en/latest/components/ffa-manifest-binding.html
.. _[7]:
@@ -866,8 +949,8 @@
.. _[8]:
-[8] https://developer.trustedfirmware.org/w/tf_a/poc-multiple-signing-domains/
+[8] https://lists.trustedfirmware.org/pipermail/tf-a/2020-February/000296.html
--------------
-*Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/conf.py b/docs/conf.py
index a100241..356be99 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -1,6 +1,6 @@
# -*- coding: utf-8 -*-
#
-# Copyright (c) 2019, Arm Limited. All rights reserved.
+# Copyright (c) 2019-2021, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -76,6 +76,14 @@
'style_external_links': True # Display an icon next to external links
}
+# Path to _static directory
+html_static_path = ['_static']
+
+# Path to css file relative to html_static_path
+html_css_files = [
+ 'css/custom.css',
+]
+
# -- Options for autosectionlabel --------------------------------------------
# Only generate automatic section labels for document titles
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 7c142d1..bde6d97 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -260,6 +260,12 @@
- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77
CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
+- ``ERRATA_A77_1946167``: This applies errata 1946167 workaround to Cortex-A77
+ CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
+
+- ``ERRATA_A77_1791578``: This applies errata 1791578 workaround to Cortex-A77
+ CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
+
For Cortex-A78, the following errata build flags are defined :
- ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78
@@ -272,6 +278,22 @@
CPU. This needs to be enabled for revisions r1p0 and r1p1, r0p0 has the same
issue but there is no workaround for that revision.
+- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78
+ CPU. This needs to be enabled for revisions r0p0 and r1p0.
+
+- ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78
+ CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0.
+
+For Cortex-A78 AE, the following errata build flags are defined :
+
+- ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to Cortex-A78
+ AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is
+ still open.
+
+- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to Cortex-A78
+ AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is
+ still open.
+
For Neoverse N1, the following errata build flags are defined :
- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1
@@ -314,6 +336,73 @@
CPU. This needs to be enabled for revisions r3p0, r3p1, r4p0, and r4p1, for
revisions r0p0, r1p0, and r2p0 there is no workaround.
+For Neoverse N2, the following errata build flags are defined :
+
+- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2
+ CPU. This needs to be enabled for revision r0p0 of the CPU, it is still open.
+
+For Neoverse V1, the following errata build flags are defined :
+
+- ``ERRATA_V1_1774420``: This applies errata 1774420 workaround to Neoverse-V1
+ CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
+ in r1p1.
+
+- ``ERRATA_V1_1791573``: This applies errata 1791573 workaround to Neoverse-V1
+ CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
+ in r1p1.
+
+- ``ERRATA_V1_1852267``: This applies errata 1852267 workaround to Neoverse-V1
+ CPU. This needs to be enabled only for revisions r0p0 and r1p0, it is fixed
+ in r1p1.
+
+- ``ERRATA_V1_1925756``: This applies errata 1925756 workaround to Neoverse-V1
+ CPU. This needs to be enabled for r0p0, r1p0, and r1p1, it is still open.
+
+- ``ERRATA_V1_1940577``: This applies errata 1940577 workaround to Neoverse-V1
+ CPU. This needs to be enabled only for revision r1p0 and r1p1 of the
+ CPU.
+
+- ``ERRATA_V1_1966096``: This applies errata 1966096 workaround to Neoverse-V1
+ CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
+ issue is present in r0p0 as well but there is no workaround for that
+ revision. It is still open.
+
+- ``ERRATA_V1_2139242``: This applies errata 2139242 workaround to Neoverse-V1
+ CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the
+ CPU. It is still open.
+
+For Cortex-A710, the following errata build flags are defined :
+
+- ``ERRATA_A710_1987031``: This applies errata 1987031 workaround to
+ Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
+ r2p0 of the CPU. It is still open.
+
+- ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to
+ Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
+ r2p0 of the CPU. It is still open.
+
+- ``ERRATA_A710_2055002``: This applies errata 2055002 workaround to
+ Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU
+ and is still open.
+
+- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to
+ Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
+ of the CPU and is still open.
+
+For Neoverse N2, the following errata build flags are defined :
+
+- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+
+- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+
+- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+
+- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+
DSU Errata Workarounds
----------------------
@@ -385,7 +474,7 @@
--------------
-*Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.*
.. _CVE-2017-5715: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2017-5715
.. _CVE-2018-3639: http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3639
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index c520e0c..901a72a 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -22,6 +22,10 @@
directory containing the SP source, relative to the ``bl32/``; the directory
is expected to contain a makefile called ``<aarch32_sp-value>.mk``.
+- ``AMU_RESTRICT_COUNTERS``: Register reads to the group 1 counters will return
+ zero at all but the highest implemented exception level. Reads from the
+ memory mapped view are unaffected by this control.
+
- ``ARCH`` : Choose the target build architecture for TF-A. It can take either
``aarch64`` or ``aarch32`` as values. By default, it is defined to
``aarch64``.
@@ -248,7 +252,8 @@
- ``ENABLE_PIE``: Boolean option to enable Position Independent Executable(PIE)
support within generic code in TF-A. This option is currently only supported
- in BL2_AT_EL3, BL31, and BL32 (TSP). Default is 0.
+ in BL2_AT_EL3, BL31, and BL32 (TSP) for AARCH64 binaries, and in BL32
+ (SP_min) for AARCH32. Default is 0.
- ``ENABLE_PMF``: Boolean option to enable support for optional Performance
Measurement Framework(PMF). Default is 0.
@@ -273,7 +278,8 @@
- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
(SVE) for the Non-secure world only. SVE is an optional architectural feature
for AArch64. Note that when SVE is enabled for the Non-secure world, access
- to SIMD and floating-point functionality from the Secure world is disabled.
+ to SIMD and floating-point functionality from the Secure world is disabled by
+ default and controlled with ENABLE_SVE_FOR_SWD.
This is to avoid corruption of the Non-secure world data in the Z-registers
which are aliased by the SIMD and FP registers. The build option is not
compatible with the ``CTX_INCLUDE_FPREGS`` build option, and will raise an
@@ -281,6 +287,11 @@
1. The default is 1 but is automatically disabled when the target
architecture is AArch32.
+- ``ENABLE_SVE_FOR_SWD``: Boolean option to enable SVE for the Secure world.
+ SVE is an optional architectural feature for AArch64. Note that this option
+ requires ENABLE_SVE_FOR_NS to be enabled. The default is 0 and it is
+ automatically disabled when the target architecture is AArch32.
+
- ``ENABLE_STACK_PROTECTOR``: String option to enable the stack protection
checks in GCC. Allowed values are "all", "strong", "default" and "none". The
default value is set to "none". "strong" is the recommended stack protection
@@ -458,7 +469,10 @@
the build. The default value is 40 in debug builds and 20 in release builds.
- ``MEASURED_BOOT``: Boolean flag to include support for the Measured Boot
- feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set.
+ feature. If this flag is enabled ``TRUSTED_BOARD_BOOT`` must be set as well
+ in order to provide trust that the code taking the measurements and recording
+ them has not been tampered with.
+
This option defaults to 0 and is an experimental feature in the stage of
development.
@@ -574,6 +588,11 @@
``BL31_NOBITS_LIMIT``. When the option is ``0`` (the default), NOBITS
sections are placed in RAM immediately following the loaded firmware image.
+- ``SMC_PCI_SUPPORT``: This option allows platforms to handle PCI configuration
+ access requests via a standard SMCCC defined in `DEN0115`_. When combined with
+ UEFI+ACPI this can provide a certain amount of OS forward compatibility
+ with newer platforms that aren't ECAM compliant.
+
- ``SPD``: Choose a Secure Payload Dispatcher component to be built into TF-A.
This build option is only valid if ``ARCH=aarch64``. The value should be
the path to the directory containing the SPD source, relative to
@@ -841,6 +860,31 @@
# Resume execution
continue
+Firmware update options
+-----------------------
+
+- ``NR_OF_FW_BANKS``: Define the number of firmware banks. This flag is used
+ in defining the firmware update metadata structure. This flag is by default
+ set to '2'.
+
+- ``NR_OF_IMAGES_IN_FW_BANK``: Define the number of firmware images in each
+ firmware bank. Each firmware bank must have the same number of images as per
+ the `PSA FW update specification`_.
+ This flag is used in defining the firmware update metadata structure. This
+ flag is by default set to '1'.
+
+- ``PSA_FWU_SUPPORT``: Enable the firmware update mechanism as per the
+ `PSA FW update specification`_. The default value is 0, and this is an
+ experimental feature.
+ PSA firmware update implementation has some limitations, such as BL2 is
+ not part of the protocol-updatable images, if BL2 needs to be updated, then
+ it should be done through another platform-defined mechanism, and it assumes
+ that the platform's hardware supports CRC32 instructions.
+
--------------
-*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
+
+.. _DEN0115: https://developer.arm.com/docs/den0115/latest
+.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/
+
diff --git a/docs/getting_started/porting-guide.rst b/docs/getting_started/porting-guide.rst
index be3f0bb..54754fe 100644
--- a/docs/getting_started/porting-guide.rst
+++ b/docs/getting_started/porting-guide.rst
@@ -894,6 +894,54 @@
Note that this API depends on ``DECRYPTION_SUPPORT`` build flag which is
marked as experimental.
+Function : plat_fwu_set_images_source() [when PSA_FWU_SUPPORT == 1]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+ Argument : struct fwu_metadata *metadata
+ Return : void
+
+This function is mandatory when PSA_FWU_SUPPORT is enabled.
+It provides a means to retrieve image specification (offset in
+non-volatile storage and length) of active/updated images using the passed
+FWU metadata, and update I/O policies of active/updated images using retrieved
+image specification information.
+Further I/O layer operations such as I/O open, I/O read, etc. on these
+images rely on this function call.
+
+In Arm platforms, this function is used to set an I/O policy of the FIP image,
+container of all active/updated secure and non-secure images.
+
+Function : plat_fwu_set_metadata_image_source() [when PSA_FWU_SUPPORT == 1]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+ Argument : unsigned int image_id, uintptr_t *dev_handle,
+ uintptr_t *image_spec
+ Return : int
+
+This function is mandatory when PSA_FWU_SUPPORT is enabled. It is
+responsible for setting up the platform I/O policy of the requested metadata
+image (either FWU_METADATA_IMAGE_ID or BKUP_FWU_METADATA_IMAGE_ID) that will
+be used to load this image from the platform's non-volatile storage.
+
+FWU metadata can not be always stored as a raw image in non-volatile storage
+to define its image specification (offset in non-volatile storage and length)
+statically in I/O policy.
+For example, the FWU metadata image is stored as a partition inside the GUID
+partition table image. Its specification is defined in the partition table
+that needs to be parsed dynamically.
+This function provides a means to retrieve such dynamic information to set
+the I/O policy of the FWU metadata image.
+Further I/O layer operations such as I/O open, I/O read, etc. on FWU metadata
+image relies on this function call.
+
+It returns '0' on success, otherwise a negative error value on error.
+Alongside, returns device handle and image specification from the I/O policy
+of the requested FWU metadata image.
+
Common optional modifications
-----------------------------
@@ -1742,9 +1790,9 @@
which is list of executable images following BL31,
arg1 - Points to load address of SOC_FW_CONFIG if present
- except in case of Arm FVP platform.
+ except in case of Arm FVP and Juno platform.
- In case of Arm FVP platform, Points to load address
+ In case of Arm FVP and Juno platform, points to load address
of FW_CONFIG.
arg2 - Points to load address of HW_CONFIG if present
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index 91ecdf3..aa1ae67 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -26,7 +26,7 @@
|TF-A| can be built with any of the following *cross-compiler* toolchains that
target the Armv7-A or Armv8-A architectures:
-- GCC >= 9.2-2019.12 (from the `Arm Developer website`_)
+- GCC >= 10.2-2020.11 (from the `Arm Developer website`_)
- Clang >= 4.0
- Arm Compiler >= 6.0
@@ -60,7 +60,7 @@
The following libraries are required for Trusted Board Boot support:
-- mbed TLS == 2.24.0 (tag: ``mbedtls-2.24.0``)
+- mbed TLS == 2.26.0 (tag: ``mbedtls-2.26.0``)
These tools are optional:
@@ -75,6 +75,12 @@
The standard software package used for debugging software on Arm development
platforms and |FVP| models.
+- Node.js >= 14
+
+ Highly recommended, and necessary in order to install and use the packaged
+ Git hooks and helper tools. Without these tools you will need to rely on the
+ CI for feedback on commit message conformance.
+
Package Installation (Linux)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -91,11 +97,22 @@
sudo apt install device-tree-compiler
+Additionally, to install an up-to-date version of Node.js, you can use the `Node
+Version Manager`_ to install a version of your choosing (we recommend 14, but
+later LTS versions might offer a more stable experience):
+
+.. code:: shell
+
+ curl -o- https://raw.githubusercontent.com/nvm-sh/nvm/v0.38.0/install.sh | "$SHELL"
+ exec "$SHELL" -ic "nvm install 14; exec $SHELL"
+
+.. _Node Version Manager: https://github.com/nvm-sh/nvm#install--update-script
+
Supporting Files
----------------
TF-A has been tested with pre-built binaries and file systems from `Linaro
-Release 19.06`_. Alternatively, you can build the binaries from source using
+Release 20.01`_. Alternatively, you can build the binaries from source using
instructions in :ref:`Performing an Initial Build`.
.. _prerequisites_get_source:
@@ -109,28 +126,44 @@
.. code:: shell
- git clone "https://review.trustedfirmware.org/TF-A/trusted-firmware-a" && (cd "trusted-firmware-a" && mkdir -p .git/hooks && curl -Lo `git rev-parse --git-dir`/hooks/commit-msg https://review.trustedfirmware.org/tools/hooks/commit-msg; chmod +x `git rev-parse --git-dir`/hooks/commit-msg)
+ git clone "https://review.trustedfirmware.org/TF-A/trusted-firmware-a"
-This will clone the Git repository also install a *commit hook* that
-automatically inserts appropriate *Change-Id:* lines at the end of your
-commit messages. These change IDs are required when committing changes that you
-intend to push for review via our Gerrit system.
+Additional Steps for Contributors
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-You can read more about Git hooks in the *githooks* page of the Git documentation,
-available at: https://git-scm.com/docs/githooks
+If you are planning on contributing back to TF-A, there are some things you'll
+want to know.
-Alternatively, you can clone without the commit hook using:
+TF-A is hosted by a `Gerrit Code Review`_ server. Gerrit requires that all
+commits include a ``Change-Id`` footer, and this footer is typically
+automatically generated by a Git hook installed by you, the developer.
+
+If you have Node.js installed already, you can automatically install this hook,
+along with any additional hooks and Javascript-based tooling that we use, by
+running from within your newly-cloned repository:
.. code:: shell
- git clone "https://review.trustedfirmware.org/TF-A/trusted-firmware-a"
+ npm install --no-save
+
+If you have opted **not** to install Node.js, you can install the Gerrit hook
+manually by running:
+
+.. code:: shell
+
+ curl -Lo $(git rev-parse --git-dir)/hooks/commit-msg https://review.trustedfirmware.org/tools/hooks/commit-msg
+ chmod +x $(git rev-parse --git-dir)/hooks/commit-msg
+
+You can read more about Git hooks in the *githooks* page of the Git
+documentation, available `here <https://git-scm.com/docs/githooks>`_.
--------------
-*Copyright (c) 2019, Arm Limited. All rights reserved.*
+*Copyright (c) 2021, Arm Limited. All rights reserved.*
.. _Arm Developer website: https://developer.arm.com/open-source/gnu-toolchain/gnu-a/downloads
+.. _Gerrit Code Review: https://www.gerritcodereview.com/
.. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-release-notes
.. _Linaro instructions: https://community.arm.com/dev-platforms/w/docs/304/arm-reference-platforms-deliverables
.. _Development Studio 5 (DS-5): https://developer.arm.com/products/software-development-tools/ds-5-development-studio
-.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06
+.. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01
diff --git a/docs/index.rst b/docs/index.rst
index cb53127..edc2535 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -15,8 +15,8 @@
perf/index
security_advisories/index
design_documents/index
+ threat_model/index
change-log
- change-log-upcoming
glossary
license
@@ -30,6 +30,7 @@
- `SMC Calling Convention`_
- `System Control and Management Interface (SCMI)`_
- `Software Delegated Exception Interface (SDEI)`_
+- `PSA FW update specification`_
Where possible, the code is designed for reuse or porting to other Armv7-A and
Armv8-A model and hardware platforms.
@@ -83,7 +84,7 @@
--------------
-*Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.*
.. _Armv7-A and Armv8-A: https://developer.arm.com/products/architecture/a-profile
.. _Secure Monitor: http://www.arm.com/products/processors/technologies/trustzone/tee-smc.php
@@ -92,3 +93,4 @@
.. _System Control and Management Interface (SCMI): http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf
.. _Software Delegated Exception Interface (SDEI): http://infocenter.arm.com/help/topic/com.arm.doc.den0054a/ARM_DEN0054A_Software_Delegated_Exception_Interface.pdf
.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest
+.. _PSA FW update specification: https://developer.arm.com/documentation/den0118/a/
diff --git a/docs/license.rst b/docs/license.rst
index 2f97043..80f1118 100644
--- a/docs/license.rst
+++ b/docs/license.rst
@@ -76,5 +76,15 @@
BSD-3-Clause license. Any contributions to this code must be made under the
terms of both licenses.
+- Some source files originating from the Linux source tree, which are
+ disjunctively dual licensed (GPL-2.0 OR MIT), are redistributed under the
+ terms of the MIT license. These files are:
+
+ - ``include/dt-bindings/interrupt-controller/arm-gic.h``
+ - ``include/dt-bindings/interrupt-controller/irq.h``
+
+ See the original `Linux MIT license`_.
+
.. _FreeBSD: http://www.freebsd.org
+.. _Linux MIT license: https://raw.githubusercontent.com/torvalds/linux/master/LICENSES/preferred/MIT
.. _SCC: http://www.simple-cc.org/
diff --git a/docs/plat/allwinner.rst b/docs/plat/allwinner.rst
index d82380d..b696989 100644
--- a/docs/plat/allwinner.rst
+++ b/docs/plat/allwinner.rst
@@ -5,22 +5,8 @@
SoCs with ARMv8 cores. Only BL31 is used to provide proper EL3 setup and
PSCI runtime services.
-U-Boot's SPL acts as a loader, loading both BL31 and BL33 (typically U-Boot).
-Loading is done from SD card, eMMC or SPI flash, also via an USB debug
-interface (FEL).
-
-BL31 lives in SRAM A2, which is documented to be accessible from secure
-world only.
-
-Current limitations:
-
-- Missing PMIC support
-
-After building bl31.bin, the binary must be fed to the U-Boot build system
-to include it in the FIT image that the SPL loader will process.
-bl31.bin can be either copied (or sym-linked) into U-Boot's root directory,
-or the environment variable BL31 must contain the binary's path.
-See the respective `U-Boot documentation`_ for more details.
+Building TF-A
+-------------
To build for machines with an A64 or H5 SoC:
@@ -34,8 +20,75 @@
make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_h6 DEBUG=1 bl31
+To build for machines with an H616 or H313 SoC:
+
+.. code:: shell
+
+ make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_h616 DEBUG=1 bl31
+
+
+Installation
+------------
+
+U-Boot's SPL acts as a loader, loading both BL31 and BL33 (typically U-Boot).
+Loading is done from SD card, eMMC or SPI flash, also via an USB debug
+interface (FEL).
+
+After building bl31.bin, the binary must be fed to the U-Boot build system
+to include it in the FIT image that the SPL loader will process.
+bl31.bin can be either copied (or sym-linked) into U-Boot's root directory,
+or the environment variable BL31 must contain the binary's path.
+See the respective `U-Boot documentation`_ for more details.
+
.. _U-Boot documentation: https://gitlab.denx.de/u-boot/u-boot/-/blob/master/board/sunxi/README.sunxi64
+Memory layout
+-------------
+
+A64, H5 and H6 SoCs
+~~~~~~~~~~~~~~~~~~~
+
+BL31 lives in SRAM A2, which is documented to be accessible from secure
+world only. Since this SRAM region is very limited (48 KB), we take
+several measures to reduce memory consumption. One of them is to confine
+BL31 to only 28 bits of virtual address space, which reduces the number
+of required page tables (each occupying 4KB of memory).
+The mapping we use on those SoCs is as follows:
+
+::
+
+ 0 64K 16M 1GB 1G+160M physical address
+ +-+------+-+---+------+--...---+-------+----+------+----------
+ |B| |S|///| |//...///| |////| |
+ |R| SRAM |C|///| dev |//...///| (sec) |////| BL33 | DRAM ...
+ |O| |P|///| MMIO |//...///| DRAM |////| |
+ |M| | |///| |//...///| (32M) |////| |
+ +-+------+-+---+------+--...---+-------+----+------+----------
+ | | | | | | / / / /
+ | | | | | | / / / /
+ | | | | | | / / / /
+ | | | | | | / // /
+ | | | | | | / / /
+ +-+------+-+---+------+--+-------+------+
+ |B| |S|///| |//| | |
+ |R| SRAM |C|///| dev |//| sec | BL33 |
+ |O| |P|///| MMIO |//| DRAM | |
+ |M| | |///| |//| | |
+ +-+------+-+---+------+--+-------+------+
+ 0 64K 16M 160M 192M 256M virtual address
+
+
+H616 SoC
+~~~~~~~~
+
+The H616 lacks the secure SRAM region present on the other SoCs, also
+lacks the "ARISC" management processor (SCP) we use. BL31 thus needs to
+run from DRAM, which prevents our compressed virtual memory map described
+above. Since running in DRAM also lifts the restriction of the limited
+SRAM size, we use the normal 1:1 mapping with 32 bits worth of virtual
+address space. So the virtual addresses used in BL31 match the physical
+addresses as presented above.
+
Trusted OS dispatcher
---------------------
diff --git a/docs/plat/arm/arm-build-options.rst b/docs/plat/arm/arm-build-options.rst
index a1d2313..d4fa98d 100644
--- a/docs/plat/arm/arm-build-options.rst
+++ b/docs/plat/arm/arm-build-options.rst
@@ -91,6 +91,12 @@
platforms. If this option is specified, then the path to the CryptoCell
SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
+- ``ARM_ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can
+ configure an Arm Ethos-N NPU. To use this service the target platform's
+ ``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only
+ the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform
+ only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0.
+
- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the
SPMC Core manifest. Valid when ``SPD=spmd`` is selected.
@@ -98,6 +104,17 @@
device tree. This flag is defined only when ``ARM_SPMC_MANIFEST_DTS`` manifest
file name contains pattern optee_sp.
+- ``TS_SP_FW_CONFIG``: DTC build flag to include Trusted Services (Crypto and
+ secure-storage) as SP in tb_fw_config device tree.
+
+- ``ARM_GPT_SUPPORT``: Enable GPT parser to get the entry address and length of
+ the various partitions present in the GPT image. This support is available
+ only for the BL2 component, and it is disabled by default.
+ The following diagram shows the view of the FIP partition inside the GPT
+ image:
+
+ |FIP in a GPT image|
+
For a better understanding of these options, the Arm development platform memory
map is explained in the :ref:`Firmware Design`.
@@ -126,6 +143,14 @@
valid value greater than 1, the platform code performs required configuration
to support multi-chip operation.
+- ``CSS_SGI_PLATFORM_VARIANT``: Selects the variant of a SGI/RD platform. A
+ particular SGI/RD platform may have multiple variants which may differ in
+ core count, cluster count or other peripherals. This build option is used
+ to select the appropriate platform variant for the build. The range of
+ valid values is platform specific.
+
--------------
-*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*
+.. |FIP in a GPT image| image:: ../../resources/diagrams/FIP_in_a_GPT_image.png
+
+*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
diff --git a/docs/plat/arm/diphda/index.rst b/docs/plat/arm/diphda/index.rst
new file mode 100644
index 0000000..27afda4
--- /dev/null
+++ b/docs/plat/arm/diphda/index.rst
@@ -0,0 +1,61 @@
+Diphda Platform
+==========================
+
+Some of the features of the Diphda platform referenced in TF-A include:
+
+- Cortex-A35 application processor (64-bit mode)
+- Secure Enclave
+- GIC-400
+- Trusted Board Boot
+
+Boot Sequence
+-------------
+
+The board boot relies on CoT (chain of trust). The trusted-firmware-a
+BL2 is extracted from the FIP and verified by the Secure Enclave
+processor. BL2 verification relies on the signature area at the
+beginning of the BL2 image. This area is needed by the SecureEnclave
+bootloader.
+
+Then, the application processor is released from reset and starts by
+executing BL2.
+
+BL2 performs the actions described in the trusted-firmware-a TBB design
+document.
+
+Build Procedure (TF-A only)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- Obtain AArch64 ELF bare-metal target `toolchain <https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads>`_.
+ Set the CROSS_COMPILE environment variable to point to the toolchain folder.
+
+- Build TF-A:
+
+ .. code:: shell
+
+ make LD=aarch64-none-elf-ld \
+ CC=aarch64-none-elf-gcc \
+ V=1 \
+ BUILD_BASE=<path to the build folder> \
+ PLAT=diphda \
+ SPD=spmd \
+ SPMD_SPM_AT_SEL2=0 \
+ DEBUG=1 \
+ MBEDTLS_DIR=mbedtls \
+ OPENSSL_DIR=<path to openssl usr folder> \
+ RUNTIME_SYSROOT=<path to the sysroot> \
+ ARCH=aarch64 \
+ TARGET_PLATFORM=<fpga or fvp> \
+ ENABLE_PIE=1 \
+ BL2_AT_EL3=1 \
+ CREATE_KEYS=1 \
+ GENERATE_COT=1 \
+ TRUSTED_BOARD_BOOT=1 \
+ COT=tbbr \
+ ARM_ROTPK_LOCATION=devel_rsa \
+ ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
+ BL32=<path to optee binary> \
+ BL33=<path to u-boot binary> \
+ bl2
+
+*Copyright (c) 2021, Arm Limited. All rights reserved.*
diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst
index 235b7b6..d41982f 100644
--- a/docs/plat/arm/fvp/index.rst
+++ b/docs/plat/arm/fvp/index.rst
@@ -12,13 +12,13 @@
(64-bit host machine only).
.. note::
- The FVP models used are Version 11.12 Build 38, unless otherwise stated.
+ The FVP models used are Version 11.15 Build 14, unless otherwise stated.
- ``FVP_Base_AEMvA``
- ``FVP_Base_AEMv8A-AEMv8A``
- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
-- ``FVP_Base_RevC-2xAEMv8A``
-- ``FVP_Base_Cortex-A32x4``
+- ``FVP_Base_RevC-2xAEMvA``
+- ``FVP_Base_Cortex-A32x4`` (Version 11.12 build 38)
- ``FVP_Base_Cortex-A35x4``
- ``FVP_Base_Cortex-A53x4``
- ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
@@ -39,10 +39,13 @@
- ``FVP_Base_Cortex-A76AEx8``
- ``FVP_Base_Cortex-A77x4``
- ``FVP_Base_Cortex-A78x4``
+- ``FVP_Base_Cortex-A710x4``
+- ``FVP_Morello`` (Version 0.10 build 542)
- ``FVP_Base_Neoverse-E1x1``
- ``FVP_Base_Neoverse-E1x2``
- ``FVP_Base_Neoverse-E1x4``
- ``FVP_Base_Neoverse-N1x4``
+- ``FVP_Base_Neoverse-N2x4`` (Version 11.12 build 38)
- ``FVP_Base_Neoverse-V1x4``
- ``FVP_CSS_SGI-575`` (Version 11.10 build 36)
- ``FVP_CSS_SGM-775``
@@ -51,7 +54,8 @@
- ``FVP_RD_N1_edge_dual`` (Version 11.10 build 36)
- ``FVP_RD_Daniel`` (Version 11.13 build 10)
- ``FVP_RD_N2`` (Version 11.13 build 10)
-- ``FVP_TC0`` (Version 0.0 build 6114)
+- ``FVP_TC0`` (Version 0.0 build 6509)
+- ``FVP_Base_AEMv8A-GIC600AE`` (Version 0.0 build 6415)
- ``Foundation_Platform``
The latest version of the AArch32 build of TF-A has been tested on the
@@ -97,7 +101,7 @@
the models. The models can be launched with ``-Q 100`` option if they are
required to match the run time characteristics of the older versions.
-All the above platforms have been tested with `Linaro Release 19.06`_.
+All the above platforms have been tested with `Linaro Release 20.01`_.
.. _build_options_arm_fvp_platform:
@@ -522,8 +526,8 @@
Notes:
-- If Position Independent Executable (PIE) support is enabled for BL31
- in this config, it can be loaded at any valid address for execution.
+- Position Independent Executable (PIE) support is enabled in this
+ config allowing BL31 to be loaded at any valid address for execution.
- Since a FIP is not loaded when using BL31 as reset entrypoint, the
``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
@@ -584,8 +588,8 @@
--data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
.. note::
- The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
- It should match the address programmed into the RVBAR register as well.
+ Position Independent Executable (PIE) support is enabled in this
+ config allowing SP_MIN to be loaded at any valid address for execution.
Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -640,10 +644,10 @@
--------------
-*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
.. _TB_FW_CONFIG for FVP: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
.. _Arm's website: `FVP models`_
.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
-.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06
+.. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01
.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms
diff --git a/docs/plat/arm/index.rst b/docs/plat/arm/index.rst
index f72992b..c834f6a 100644
--- a/docs/plat/arm/index.rst
+++ b/docs/plat/arm/index.rst
@@ -8,10 +8,11 @@
juno/index
fvp/index
fvp-ve/index
- tc0/index
+ tc/index
arm_fpga/index
arm-build-options
morello/index
+ diphda/index
This chapter holds documentation related to Arm's development platforms,
including both software models (FVPs) and hardware development boards
@@ -19,4 +20,4 @@
--------------
-*Copyright (c) 2019, Arm Limited. All rights reserved.*
+*Copyright (c) 2021, Arm Limited. All rights reserved.*
diff --git a/docs/plat/arm/juno/index.rst b/docs/plat/arm/juno/index.rst
index cf328fa..8b9d453 100644
--- a/docs/plat/arm/juno/index.rst
+++ b/docs/plat/arm/juno/index.rst
@@ -12,24 +12,21 @@
This version of TF-A has been tested on variants r0, r1 and r2 of Juno.
-To execute the software stack on Juno, the version of the Juno board recovery
-image indicated in the `Linaro Release Notes`_ must be installed. If you have an
-earlier version installed or are unsure which version is installed, please
-re-install the recovery image by following the
-`Instructions for using Linaro's deliverables on Juno`_.
+To run TF-A on Juno, you need to first prepare an SD card with Juno software
+stack that includes TF-A. This version of TF-A is tested with pre-built
+`Linaro release software stack`_ version 20.01. You can alternatively
+build the software stack yourself by following the
+`Juno platform software user guide`_. Once you prepare the software stack
+on an SD card, you can replace the ``bl1.bin`` and ``fip.bin``
+binaries in the ``SOFTWARE/`` directory with custom built TF-A binaries.
Preparing TF-A images
---------------------
-After building TF-A, the files ``bl1.bin`` and ``fip.bin`` need copying to the
-``SOFTWARE/`` directory of the Juno SD card.
-
-Creating a Firmware Image Package (FIP)
----------------------------------------
-
This section provides Juno and FVP specific instructions to build Trusted
Firmware, obtain the additional required firmware, and pack it all together in
-a single FIP binary. It assumes that a Linaro release has been installed.
+a single FIP binary. It assumes that a Linaro release software stack has been
+installed.
.. note::
Pre-built binaries for AArch32 are available from Linaro Release 16.12
@@ -57,9 +54,16 @@
make realclean
-#. Obtain SCP_BL2 (Juno) and BL33 (all platforms)
+#. Obtain SCP binaries (Juno)
- Use the fiptool to extract the SCP_BL2 and BL33 images from the FIP
+ This version of TF-A is tested with SCP version 2.8.0 on Juno. You can
+ download pre-built SCP binaries (``scp_bl1.bin`` and ``scp_bl2.bin``)
+ from `TF-A downloads page`_. Alternatively, you can `build
+ the binaries from source`_.
+
+#. Obtain BL33 (all platforms)
+
+ Use the fiptool to extract the BL33 image from the FIP
package included in the Linaro release:
.. code:: shell
@@ -71,8 +75,7 @@
./tools/fiptool/fiptool unpack <path-to-linaro-release>/[SOFTWARE]/fip.bin
The unpack operation will result in a set of binary images extracted to the
- current working directory. The SCP_BL2 image corresponds to
- ``scp-fw.bin`` and BL33 corresponds to ``nt-fw.bin``.
+ current working directory. BL33 corresponds to ``nt-fw.bin``.
.. note::
The fiptool will complain if the images to be unpacked already
@@ -102,7 +105,7 @@
.. code:: shell
- make PLAT=juno BL33=nt-fw.bin SCP_BL2=scp-fw.bin all fip
+ make PLAT=juno BL33=nt-fw.bin SCP_BL2=scp_bl2.bin all fip
For AArch32:
@@ -144,7 +147,7 @@
.. code:: shell
make ARCH=aarch64 PLAT=juno JUNO_AARCH32_EL3_RUNTIME=1 \
- BL33=nt-fw.bin SCP_BL2=scp-fw.bin \
+ BL33=nt-fw.bin SCP_BL2=scp_bl2.bin \
BL32=<path-to-temporary>/bl32.bin all fip
The resulting BL1 and FIP images may be found in:
@@ -159,6 +162,8 @@
./build/fvp/release/bl1.bin
./build/fvp/release/fip.bin
+After building TF-A, the files ``bl1.bin``, ``fip.bin`` and ``scp_bl1.bin``
+need to be copied to the ``SOFTWARE/`` directory on the Juno SD card.
Booting Firmware Update images
------------------------------
@@ -236,10 +241,12 @@
--------------
-*Copyright (c) 2019, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
-.. _Linaro Release Notes: https://community.arm.com/dev-platforms/w/docs/226/old-release-notes
-.. _Instructions for using Linaro's deliverables on Juno: https://community.arm.com/dev-platforms/w/docs/303/juno
+.. _Linaro release software stack: http://releases.linaro.org/members/arm/platforms/
+.. _Juno platform software user guide: https://git.linaro.org/landing-teams/working/arm/arm-reference-platforms.git/about/docs/juno/user-guide.rst
+.. _TF-A downloads page: https://downloads.trustedfirmware.org/tf-a/css_scp_2.8.0/juno/
+.. _build the binaries from source: https://github.com/ARM-software/SCP-firmware/blob/master/user_guide.md#scp-firmware-user-guide
.. _Arm Platforms Portal: https://community.arm.com/dev-platforms/
.. _Juno Getting Started Guide: http://infocenter.arm.com/help/topic/com.arm.doc.dui0928e/DUI0928E_juno_arm_development_platform_gsg.pdf
.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
diff --git a/docs/plat/arm/tc/index.rst b/docs/plat/arm/tc/index.rst
new file mode 100644
index 0000000..20d3e56
--- /dev/null
+++ b/docs/plat/arm/tc/index.rst
@@ -0,0 +1,56 @@
+TC Total Compute Platform
+==========================
+
+Some of the features of TC platform referenced in TF-A include:
+
+- A `System Control Processor <https://github.com/ARM-software/SCP-firmware>`_
+ to abstract power and system management tasks away from application
+ processors. The RAM firmware for SCP is included in the TF-A FIP and is
+ loaded by AP BL2 from FIP in flash to SRAM for copying by SCP (SCP has access
+ to AP SRAM).
+- GICv4
+- Trusted Board Boot
+- SCMI
+- MHUv2
+
+Currently, the main difference between TC0 (TARGET_PLATFORM=0) and TC1
+(TARGET_PLATFORM=1) platforms w.r.t to TF-A is the CPUs supported. TC0 has
+support for Cortex A510, Cortex A710 and Cortex X2, while TC1 has support for
+Cortex A510, Cortex Makalu and Cortex Makalu ELP Arm CPUs.
+
+
+Boot Sequence
+-------------
+
+The execution begins from SCP_BL1. SCP_BL1 powers up the AP which starts
+executing AP_BL1 and then executes AP_BL2 which loads the SCP_BL2 from
+FIP to SRAM. The SCP has access to AP SRAM. The address and size of SCP_BL2
+is communicated to SCP using SDS. SCP copies SCP_BL2 from SRAM to its own
+RAM and starts executing it. The AP then continues executing the rest of TF-A
+stages including BL31 runtime stage and hands off executing to
+Non-secure world (u-boot).
+
+Build Procedure (TF-A only)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+- Obtain arm `toolchain <https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads>`_.
+ Set the CROSS_COMPILE environment variable to point to the toolchain folder.
+
+- Build TF-A:
+
+ .. code:: shell
+
+ make PLAT=tc BL33=<path_to_uboot.bin> \
+ SCP_BL2=<path_to_scp_ramfw.bin> TARGET_PLATFORM={0,1} all fip
+
+ Enable TBBR by adding the following options to the make command:
+
+ .. code:: shell
+
+ MBEDTLS_DIR=<path_to_mbedtls_directory> \
+ TRUSTED_BOARD_BOOT=1 \
+ GENERATE_COT=1 \
+ ARM_ROTPK_LOCATION=devel_rsa \
+ ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
+
+*Copyright (c) 2020-2021, Arm Limited. All rights reserved.*
diff --git a/docs/plat/arm/tc0/index.rst b/docs/plat/arm/tc0/index.rst
deleted file mode 100644
index 34d1f13..0000000
--- a/docs/plat/arm/tc0/index.rst
+++ /dev/null
@@ -1,50 +0,0 @@
-TC0 Total Compute Platform
-==========================
-
-Some of the features of TC0 platform referenced in TF-A include:
-
-- A `System Control Processor <https://github.com/ARM-software/SCP-firmware>`_
- to abstract power and system management tasks away from application
- processors. The RAM firmware for SCP is included in the TF-A FIP and is
- loaded by AP BL2 from FIP in flash to SRAM for copying by SCP (SCP has access
- to AP SRAM).
-- GICv4
-- Trusted Board Boot
-- SCMI
-- MHUv2
-
-Boot Sequence
--------------
-
-The execution begins from SCP_BL1. SCP_BL1 powers up the AP which starts
-executing AP_BL1 and then executes AP_BL2 which loads the SCP_BL2 from
-FIP to SRAM. The SCP has access to AP SRAM. The address and size of SCP_BL2
-is communicated to SCP using SDS. SCP copies SCP_BL2 from SRAM to its own
-RAM and starts executing it. The AP then continues executing the rest of TF-A
-stages including BL31 runtime stage and hands off executing to
-Non-secure world (u-boot).
-
-Build Procedure (TF-A only)
-~~~~~~~~~~~~~~~~~~~~~~~~~~~
-
-- Obtain arm `toolchain <https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads>`_.
- Set the CROSS_COMPILE environment variable to point to the toolchain folder.
-
-- Build TF-A:
-
- .. code:: shell
-
- make PLAT=tc0 BL33=<path_to_uboot.bin> \
- SCP_BL2=<path_to_scp_ramfw.bin> all fip
-
- Enable TBBR by adding the following options to the make command:
-
- .. code:: shell
-
- MBEDTLS_DIR=<path_to_mbedtls_directory> \
- TRUSTED_BOARD_BOOT=1 \
- GENERATE_COT=1 \
- ARM_ROTPK_LOCATION=devel_rsa \
- ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
-
-*Copyright (c) 2020, Arm Limited. All rights reserved.*
diff --git a/docs/plat/deprecated.rst b/docs/plat/deprecated.rst
new file mode 100644
index 0000000..7cc4258
--- /dev/null
+++ b/docs/plat/deprecated.rst
@@ -0,0 +1,20 @@
+Deprecated platforms
+====================
+
+Process of deprecating a platform
+---------------------------------
+
+Platform can be deprecated and its source can be kept in repository for a cooling
+off period before deleting it or it can be deleted straight away. For later types
+Deprecated/Deleted version would be same.
+
+List of deprecated platforms
+----------------------------
+
++----------------+----------------+--------------------+--------------------+
+| Platform | Vendor | Deprecated version | Deleted version |
++================+================+====================+====================+
+| sgm775 | Arm | 2.5 | 2.7 |
++----------------+----------------+--------------------+--------------------+
+| mt6795 | MTK | 2.5 | 2.7 |
++----------------+----------------+--------------------+--------------------+
diff --git a/docs/plat/imx8m.rst b/docs/plat/imx8m.rst
index f184b69..0fe15c9 100644
--- a/docs/plat/imx8m.rst
+++ b/docs/plat/imx8m.rst
@@ -6,6 +6,9 @@
reliability and embedded security needed to drive the growth of fast-growing
edge node computing, streaming multimedia, and machine learning applications.
+imx8mq is dropped in TF-A CI build due to the small OCRAM size, but still actively
+maintained in NXP official release.
+
Boot Sequence
-------------
@@ -43,3 +46,17 @@
used to generate flash.bin, and flash.bin needs to be flashed into SD card
with certain offset for BOOT ROM. the u-boot and imx-mkimage will be upstreamed
soon, this doc will be updated once they are ready, and the link will be posted.
+
+TBBR Boot Sequence
+------------------
+
+When setting NEED_BL2=1 on imx8mm. We support an alternative way of
+boot sequence to support TBBR.
+
+Bootrom --> SPL --> BL2 --> BL31 --> BL33(u-boot with UEFI) --> grub
+
+This helps us to fulfill the SystemReady EBBR standard.
+BL2 will be in the FIT image and SPL will verify it.
+All of the BL3x will be put in the FIP image. BL2 will verify them.
+In U-boot we turn on the UEFI secure boot features so it can verify
+grub. And we use grub to verify linux kernel.
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index 3cbb552..4dc9ecd 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -9,6 +9,7 @@
allwinner
arm/index
+ deprecated
meson-axg
meson-gxbb
meson-gxl
@@ -20,6 +21,7 @@
marvell/index
mt8183
mt8192
+ mt8195
nvidia-tegra
warp7
imx8
diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst
index e55ce3c..8af27b1 100644
--- a/docs/plat/marvell/armada/build.rst
+++ b/docs/plat/marvell/armada/build.rst
@@ -26,7 +26,7 @@
*u-boot.bin* should be used and not *u-boot-spl.bin*
-Set MSS/SCP image path (mandatory only for A7K/8K/CN913x)
+Set MSS/SCP image path (mandatory only for A7K/8K/CN913x when MSS_SUPPORT=1)
.. code:: shell
@@ -62,6 +62,7 @@
- a80x0_mcbin - MacchiatoBin
- a80x0_puzzle - IEI Puzzle-M801
- t9130 - CN913x
+ - t9130_cex7_eval - CN913x CEx7 Evaluation Board
- DEBUG
@@ -98,10 +99,64 @@
There is no reason to enable this feature if OP-TEE OS built with CFG_WITH_PAGER=n.
Only set LLC_SRAM=1 if OP-TEE OS is built with CFG_WITH_PAGER=y.
+- MARVELL_SECURE_BOOT
+
+ Build trusted(=1)/non trusted(=0) image, default is non trusted.
+ This parameter is used only for ``mrvl_flash`` and ``mrvl_uart`` targets.
+
+- MV_DDR_PATH
+
+ This parameter is required for ``mrvl_flash`` and ``mrvl_uart`` targets.
+ For A7K/8K/CN913x it is used for BLE build and for Armada37x0 it used
+ for ddr_tool build.
+
+ Specify path to the full checkout of Marvell mv-ddr-marvell git
+ repository. Checkout must contain also .git subdirectory because
+ mv-ddr build process calls git commands.
+
+ Do not remove any parts of git checkout becuase build process and other
+ applications need them for correct building and version determination.
+
+
+CN913x specific build options:
+
+- CP_NUM
+
+ Total amount of CPs (South Bridge) connected to AP. When the parameter is omitted,
+ the build uses the default number of CPs, which is a number of embedded CPs inside the
+ package: 1 or 2 depending on the SoC used. The parameter is valid for OcteonTX2 CN913x SoC
+ family (PLAT=t9130), which can have external CPs connected to the MCI ports. Valid
+ values with CP_NUM are in a range of 1 to 3.
+
+
+A7K/8K/CN913x specific build options:
+
+- BLE_PATH
+
+ Points to BLE (Binary ROM extension) sources folder.
+ The parameter is optional, its default value is ``plat/marvell/armada/a8k/common/ble``
+ which uses TF-A in-tree BLE implementation.
+
+- MSS_SUPPORT
+
+ When ``MSS_SUPPORT=1``, then TF-A includes support for Management SubSystem (MSS).
+ When enabled it is required to specify path to the MSS firmware image via ``SCP_BL2``
+ option.
+
+ This option is by default enabled.
+
+- SCP_BL2
+
+ Specify path to the MSS fimware image binary which will run on Cortex-M3 coprocessor.
+ It is available in Marvell binaries-marvell git repository. Required when ``MSS_SUPPORT=1``.
+
+
+Armada37x0 specific build options:
+
- CM3_SYSTEM_RESET
- For Armada37x0 only, when ``CM3_SYSTEM_RESET=1``, the Cortex-M3 secure coprocessor will
- be used for system reset.
+ When ``CM3_SYSTEM_RESET=1``, the Cortex-M3 secure coprocessor will be used for system reset.
+
TF-A will send command 0x0009 with a magic value via the rWTM mailbox interface to the
Cortex-M3 secure coprocessor.
The firmware running in the coprocessor must either implement this functionality or
@@ -112,43 +167,17 @@
This option is needed on Turris MOX as a workaround to a HW bug which causes reset to
sometime hang the board.
-- MARVELL_SECURE_BOOT
+- A3720_DB_PM_WAKEUP_SRC
- Build trusted(=1)/non trusted(=0) image, default is non trusted.
+ For Armada 3720 Development Board only, when ``A3720_DB_PM_WAKEUP_SRC=1``,
+ TF-A will setup PM wake up src configuration. This option is disabled by default.
-- BLE_PATH
- Points to BLE (Binary ROM extension) sources folder.
- Only required for A7K/8K/CN913x builds.
- The parameter is optional, its default value is ``plat/marvell/armada/a8k/common/ble``.
-
-- MV_DDR_PATH
-
- For A7K/8K/CN913x, use this parameter to point to mv_ddr driver sources to allow BLE build. For A37x0,
- it is used for ddr_tool build.
-
- Usage example: MV_DDR_PATH=path/to/mv_ddr
-
- The parameter is optional for A7K/8K/CN913x, when this parameter is not set, the mv_ddr
- sources are expected to be located at: drivers/marvell/mv_ddr. However, the parameter
- is necessary for A37x0.
-
- For the mv_ddr source location, check the section "Tools and external components installation"
-
- If MV_DDR_PATH source code is a git snapshot then provide path to the full git
- repository (including .git subdir) because mv_ddr build process calls git commands.
-
-- CP_NUM
-
- Total amount of CPs (South Bridge) connected to AP. When the parameter is omitted,
- the build uses the default number of CPs, which is a number of embedded CPs inside the
- package: 1 or 2 depending on the SoC used. The parameter is valid for OcteonTX2 CN913x SoC
- family (PLAT=t9130), which can have external CPs connected to the MCI ports. Valid
- values with CP_NUM are in a range of 1 to 3.
+Armada37x0 specific build options for ``mrvl_flash`` and ``mrvl_uart`` targets:
- DDR_TOPOLOGY
- For Armada37x0 only, the DDR topology map index/name, default is 0.
+ The DDR topology map index/name, default is 0.
Supported Options:
- 0 - DDR3 1CS 512MB (DB-88F3720-DDR3-Modular, EspressoBin V3-V5)
@@ -163,7 +192,7 @@
- CLOCKSPRESET
- For Armada37x0 only, the clock tree configuration preset including CPU and DDR frequency,
+ The clock tree configuration preset including CPU and DDR frequency,
default is CPU_800_DDR_800.
- CPU_600_DDR_600 - CPU at 600 MHz, DDR at 600 MHz
@@ -180,7 +209,7 @@
- BOOTDEV
- For Armada37x0 only, the flash boot device, default is ``SPINOR``.
+ The flash boot device, default is ``SPINOR``.
Currently, Armada37x0 only supports ``SPINOR``, ``SPINAND``, ``EMMCNORM`` and ``SATA``:
@@ -199,7 +228,7 @@
- PARTNUM
- For Armada37x0 only, the boot partition number, default is 0.
+ The boot partition number, default is 0.
To boot from eMMC, the value should be aligned with the parameter in
U-Boot with name of ``CONFIG_SYS_MMC_ENV_PART``, whose value by default is
@@ -208,7 +237,7 @@
- WTMI_IMG
- For Armada37x0 only, the path of the binary can point to an image which
+ The path of the binary can point to an image which
does nothing, an image which supports EFUSE or a customized CM3 firmware
binary. The default image is ``fuse.bin`` that built from sources in WTP
folder, which is the next option. If the default image is OK, then this
@@ -219,18 +248,31 @@
binary and sys-init code from the WTP directory which sets DDR and CPU
clocks according to DDR_TOPOLOGY and CLOCKSPRESET options.
+ CZ.NIC as part of Turris project released free and open source WTMI
+ application firmware ``wtmi_app.bin`` for all Armada 3720 devices.
+ This firmware includes additional features like access to Hardware
+ Random Number Generator of Armada 3720 SoC which original Marvell's
+ ``fuse.bin`` image does not have.
+
+ CZ.NIC's Armada 3720 Secure Firmware is available at website:
+
+ https://gitlab.nic.cz/turris/mox-boot-builder/
+
- WTP
- For Armada37x0 only, use this parameter to point to wtptools source code
- directory, which can be found as a3700_utils.zip in the release. Usage
- example: ``WTP=/path/to/a3700_utils``
+ Specify path to the full checkout of Marvell A3700-utils-marvell git
+ repository. Checkout must contain also .git subdirectory because WTP
+ build process calls git commands.
- If WTP source code is a git snapshot then provide path to the full git
- repository (including .git subdir) because WTP build process calls git commands.
+ WTP build process uses also Marvell mv-ddr-marvell git repository
+ specified in MV_DDR_PATH option.
+
+ Do not remove any parts of git checkout becuase build process and other
+ applications need them for correct building and version determination.
- CRYPTOPP_PATH
- For Armada37x0 only, use this parameter to point to Crypto++ source code
+ Use this parameter to point to Crypto++ source code
directory. If this option is specified then Crypto++ source code in
CRYPTOPP_PATH directory will be automatically compiled. Crypto++ library
is required for building WTP image tool. Either CRYPTOPP_PATH or
@@ -238,12 +280,12 @@
- CRYPTOPP_LIBDIR
- For Armada37x0 only, use this parameter to point to the directory with
+ Use this parameter to point to the directory with
compiled Crypto++ library. By default it points to the CRYPTOPP_PATH.
- CRYPTOPP_INCDIR
- For Armada37x0 only, use this parameter to point to the directory with
+ Use this parameter to point to the directory with
header files of Crypto++ library. By default it points to the CRYPTOPP_PATH.
@@ -274,21 +316,25 @@
CROSS_COMPILE=aarch64-linux-gnu- mrvl_bootimage
Here is full example how to build production release of Marvell firmware image (concatenated
-binary of Marvell secure firmware, TF-A and U-Boot) for EspressoBin board (PLAT=a3700) with
-1GHz CPU (CLOCKSPRESET=CPU_1000_DDR_800) and 1GB DDR4 RAM (DDR_TOPOLOGY=5):
+binary of Marvell's A3720 sys-init, CZ.NIC's Armada 3720 Secure Firmware, TF-A and U-Boot) for
+EspressoBin board (PLAT=a3700) with 1GHz CPU (CLOCKSPRESET=CPU_1000_DDR_800) and
+1GB DDR4 RAM (DDR_TOPOLOGY=5):
.. code:: shell
- > git clone https://review.trustedfirmware.org/TF-A/trusted-firmware-a
- > git clone https://gitlab.denx.de/u-boot/u-boot.git
+ > git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git
+ > git clone https://source.denx.de/u-boot/u-boot.git
> git clone https://github.com/weidai11/cryptopp.git
- > git clone https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git -b master
- > git clone https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git -b master
+ > git clone https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
+ > git clone https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git
+ > git clone https://gitlab.nic.cz/turris/mox-boot-builder.git
> make -C u-boot CROSS_COMPILE=aarch64-linux-gnu- mvebu_espressobin-88f3720_defconfig u-boot.bin
+ > make -C mox-boot-builder CROSS_CM3=arm-linux-gnueabi- wtmi_app.bin
> make -C trusted-firmware-a CROSS_COMPILE=aarch64-linux-gnu- CROSS_CM3=arm-linux-gnueabi- \
USE_COHERENT_MEM=0 PLAT=a3700 CLOCKSPRESET=CPU_1000_DDR_800 DDR_TOPOLOGY=5 \
- MV_DDR_PATH=$PWD/mv-ddr-marvell/ WTP=$PWD/A3700-utils-marvell/ CRYPTOPP_PATH=$PWD/cryptopp/ \
- BL33=$PWD/u-boot/u-boot.bin mrvl_flash
+ MV_DDR_PATH=$PWD/mv-ddr-marvell/ WTP=$PWD/A3700-utils-marvell/ \
+ CRYPTOPP_PATH=$PWD/cryptopp/ BL33=$PWD/u-boot/u-boot.bin \
+ WTMI_IMG=$PWD/mox-boot-builder/wtmi_app.bin FIP_ALIGN=0x100 mrvl_flash
Produced Marvell firmware flash image: ``trusted-firmware-a/build/a3700/release/flash-image.bin``
@@ -335,8 +381,8 @@
Tools and external components installation
------------------------------------------
-Armada37x0 Builds require installation of 3 components
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Armada37x0 Builds require installation of additional components
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
(1) ARM cross compiler capable of building images for the service CPU (CM3).
This component is usually included in the Linux host packages.
@@ -369,10 +415,19 @@
https://github.com/weidai11/cryptopp.git
-Armada70x0 and Armada80x0 Builds require installation of an additional component
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+(5) Optional CZ.NIC's Armada 3720 Secure Firmware:
+
+ https://gitlab.nic.cz/turris/mox-boot-builder.git
+
+Armada70x0, Armada80x0 and CN913x Builds require installation of additional components
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
(1) DDR initialization library sources (mv_ddr) available at the following repository
(use the "master" branch):
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
+
+(2) MSS Management SubSystem Firmware available at the following repository
+ (use the "binaries-marvell-armada-SDK10.0.1.0" branch):
+
+ https://github.com/MarvellEmbeddedProcessors/binaries-marvell.git
diff --git a/docs/plat/mt8195.rst b/docs/plat/mt8195.rst
new file mode 100644
index 0000000..b2aeea2
--- /dev/null
+++ b/docs/plat/mt8195.rst
@@ -0,0 +1,21 @@
+MediaTek 8195
+=============
+
+MediaTek 8195 (MT8195) is a 64-bit ARM SoC introduced by MediaTek in 2021.
+The chip incorporates eight cores - four Cortex-A55 little cores and Cortex-A76.
+Cortex-A76 can operate at up to 2.2 GHz.
+Cortex-A55 can operate at up to 2.0 GHz.
+
+Boot Sequence
+-------------
+
+::
+
+ Boot Rom --> Coreboot --> TF-A BL31 --> Depthcharge --> Linux Kernel
+
+How to Build
+------------
+
+.. code:: shell
+
+ make CROSS_COMPILE=aarch64-linux-gnu- PLAT=mt8195 DEBUG=1 COREBOOT=1
diff --git a/docs/plat/nvidia-tegra.rst b/docs/plat/nvidia-tegra.rst
index 02ff38b..391c7c8 100644
--- a/docs/plat/nvidia-tegra.rst
+++ b/docs/plat/nvidia-tegra.rst
@@ -19,7 +19,7 @@
multi-processing (HMP) solution designed to optimize performance and
efficiency.
-T186 has Dual NVIDIA Denver 2 ARM® CPU cores, plus Quad ARM Cortex®-A57 cores,
+T186 has Dual NVIDIA Denver2 ARM® CPU cores, plus Quad ARM Cortex®-A57 cores,
in a coherent multiprocessor configuration. The Denver 2 and Cortex-A57 cores
support ARMv8, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code
including legacy ARMv7 applications. The Denver 2 processors each have 128 KB
@@ -29,20 +29,6 @@
high speed coherency fabric connects these two processor complexes and allows
heterogeneous multi-processing with all six cores if required.
-- .. rubric:: T210
- :name: t210
-
-T210 has Quad Arm® Cortex®-A57 cores in a switched configuration with a
-companion set of quad Arm Cortex-A53 cores. The Cortex-A57 and A53 cores
-support Armv8-A, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code
-including legacy Armv7-A applications. The Cortex-A57 processors each have
-48 KB Instruction and 32 KB Data Level 1 caches; and have a 2 MB shared
-Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction
-and 32 KB Data Level 1 caches; and have a 512 KB shared Level 2 unified cache.
-
-- .. rubric:: T132
- :name: t132
-
Denver is NVIDIA's own custom-designed, 64-bit, dual-core CPU which is
fully Armv8-A architecture compatible. Each of the two Denver cores
implements a 7-way superscalar microarchitecture (up to 7 concurrent
@@ -68,6 +54,17 @@
to extensive power-gating and dynamic voltage and clock scaling based on
workloads.
+- .. rubric:: T210
+ :name: t210
+
+T210 has Quad Arm® Cortex®-A57 cores in a switched configuration with a
+companion set of quad Arm Cortex-A53 cores. The Cortex-A57 and A53 cores
+support Armv8-A, executing both 64-bit Aarch64 code, and 32-bit Aarch32 code
+including legacy Armv7-A applications. The Cortex-A57 processors each have
+48 KB Instruction and 32 KB Data Level 1 caches; and have a 2 MB shared
+Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction
+and 32 KB Data Level 1 caches; and have a 512 KB shared Level 2 unified cache.
+
Directory structure
-------------------
@@ -89,7 +86,6 @@
These are the supported Trusted OS' by Tegra platforms.
-- Tegra132: TLK
- Tegra210: TLK and Trusty
- Tegra186: Trusty
- Tegra194: Trusty
@@ -110,7 +106,7 @@
.. code:: shell
CROSS_COMPILE=<path-to-aarch64-gcc>/bin/aarch64-none-elf- make PLAT=tegra \
- TARGET_SOC=<target-soc e.g. t194|t186|t210|t132> SPD=<dispatcher e.g. trusty|tlkd>
+ TARGET_SOC=<target-soc e.g. t194|t186|t210> SPD=<dispatcher e.g. trusty|tlkd>
bl31
Platforms wanting to use different TZDRAM\_BASE, can add ``TZDRAM_BASE=<value>``
diff --git a/docs/plat/stm32mp1.rst b/docs/plat/stm32mp1.rst
index f597460..0ef2923 100644
--- a/docs/plat/stm32mp1.rst
+++ b/docs/plat/stm32mp1.rst
@@ -95,6 +95,7 @@
------------------
Boot media(s) supported by BL2 must be specified in the build command.
Available storage medias are:
+
- ``STM32MP_SDMMC``
- ``STM32MP_EMMC``
- ``STM32MP_RAW_NAND``
@@ -112,6 +113,7 @@
make DEVICE_TREE=stm32mp157c-ev1 all
To build TF-A with OP-TEE support for all bootable devices:
+
.. code:: bash
make CROSS_COMPILE=arm-linux-gnueabihf- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 AARCH32_SP=optee STM32MP_SDMMC=1 STM32MP_EMMC=1 STM32MP_RAW_NAND=1 STM32MP_SPI_NAND=1 STM32MP_SPI_NOR=1 DTB_FILE_NAME=stm32mp157c-ev1.dtb
diff --git a/docs/plat/xilinx-versal.rst b/docs/plat/xilinx-versal.rst
index 57a363b..d65b048 100644
--- a/docs/plat/xilinx-versal.rst
+++ b/docs/plat/xilinx-versal.rst
@@ -19,6 +19,16 @@
make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal VERSAL_PLATFORM=versal_virt bl31
```
+To build TF-A for JTAG DCC console
+```bash
+make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal bl31 VERSAL_CONSOLE=dcc
+```
+
+To build TF-A with Straight-Line Speculation(SLS)
+```bash
+make RESET_TO_BL31=1 CROSS_COMPILE=aarch64-none-elf- PLAT=versal bl31 HARDEN_SLS_ALL=1
+```
+
Xilinx Versal platform specific build options
---------------------------------------------
diff --git a/docs/plat/xilinx-zynqmp.rst b/docs/plat/xilinx-zynqmp.rst
index 5db4488..79c2535 100644
--- a/docs/plat/xilinx-zynqmp.rst
+++ b/docs/plat/xilinx-zynqmp.rst
@@ -22,6 +22,12 @@
make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd bl31 bl32
+To build TF-A for JTAG DCC console:
+
+.. code:: bash
+
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 bl31 ZYNQMP_CONSOLE=dcc
+
ZynqMP platform specific build options
--------------------------------------
diff --git a/docs/process/contributing.rst b/docs/process/contributing.rst
index 15c2b45..c91903a 100644
--- a/docs/process/contributing.rst
+++ b/docs/process/contributing.rst
@@ -29,6 +29,20 @@
- Make commits of logical units. See these general `Git guidelines`_ for
contributing to a project.
+- Ensure your commit messages comply with the `Conventional Commits`_
+ specification:
+
+ .. code::
+
+ <type>[optional scope]: <description>
+
+ [optional body]
+
+ [optional footer(s)]
+
+ You can use the tooling installed by the optional steps in the
+ :ref:`prerequisites <Prerequisites>` guide to validate this locally.
+
- Keep the commits on topic. If you need to fix another bug or make another
enhancement, please address it on a separate topic branch.
@@ -216,6 +230,7 @@
*Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.*
+.. _Conventional Commits: https://www.conventionalcommits.org/en/v1.0.0
.. _developer.trustedfirmware.org: https://developer.trustedfirmware.org
.. _review.trustedfirmware.org: https://review.trustedfirmware.org
.. _issue: https://developer.trustedfirmware.org/project/board/1/
diff --git a/docs/resources/diagrams/FIP_in_a_GPT_image.png b/docs/resources/diagrams/FIP_in_a_GPT_image.png
new file mode 100644
index 0000000..4bafed9
--- /dev/null
+++ b/docs/resources/diagrams/FIP_in_a_GPT_image.png
Binary files differ
diff --git a/docs/resources/diagrams/MMU-600.png b/docs/resources/diagrams/MMU-600.png
new file mode 100644
index 0000000..9cbc243
--- /dev/null
+++ b/docs/resources/diagrams/MMU-600.png
Binary files differ
diff --git a/docs/resources/diagrams/ff-a-spm-sel2.png b/docs/resources/diagrams/ff-a-spm-sel2.png
index 6479ff5..605fd9b 100644
--- a/docs/resources/diagrams/ff-a-spm-sel2.png
+++ b/docs/resources/diagrams/ff-a-spm-sel2.png
Binary files differ
diff --git a/docs/resources/diagrams/ffa-ns-interrupt-handling-managed-exit.png b/docs/resources/diagrams/ffa-ns-interrupt-handling-managed-exit.png
new file mode 100644
index 0000000..0619cf2
--- /dev/null
+++ b/docs/resources/diagrams/ffa-ns-interrupt-handling-managed-exit.png
Binary files differ
diff --git a/docs/resources/diagrams/ffa-ns-interrupt-handling-sp-preemption.png b/docs/resources/diagrams/ffa-ns-interrupt-handling-sp-preemption.png
new file mode 100644
index 0000000..f110028
--- /dev/null
+++ b/docs/resources/diagrams/ffa-ns-interrupt-handling-sp-preemption.png
Binary files differ
diff --git a/docs/resources/diagrams/plantuml/spm_dfd.puml b/docs/resources/diagrams/plantuml/spm_dfd.puml
new file mode 100644
index 0000000..ad4996e
--- /dev/null
+++ b/docs/resources/diagrams/plantuml/spm_dfd.puml
@@ -0,0 +1,82 @@
+/'
+ ' Copyright (c) 2021, Arm Limited. All rights reserved.
+ '
+ ' SPDX-License-Identifier: BSD-3-Clause
+ '/
+
+/'
+TF-A SPMC Data Flow Diagram
+'/
+
+@startuml
+digraph tfa_dfd {
+
+ # Allow arrows to end on cluster boundaries
+ compound=true
+
+ # Default settings for edges and nodes
+ edge [minlen=2 color="#8c1b07"]
+ node [fillcolor="#ffb866" style=filled shape=box fixedsize=true width=1.6 height=0.7]
+
+ # Nodes outside of the trust boundary
+ nsec [label="NS Client"]
+ ddr [label="External memory (DDR)"]
+
+ # Trust boundary cluster
+ subgraph cluster_trusted {
+ graph [style=dashed color="#f22430"]
+
+ # HW IPs cluster
+ subgraph cluster_ip {
+ label ="Hardware IPs";
+ graph [style=filled color="#000000" fillcolor="#ffd29e"]
+
+ rank="same"
+ gic [label="GIC" width=1.2 height=0.5]
+ smmu [label="SMMU" width=1.2 height=0.5]
+ uart [label="UART" width=1.2 height=0.5]
+ pe [label="PE" width=1.2 height=0.5]
+ }
+
+ # TF-A cluster
+ subgraph cluster_tfa {
+ label ="EL3 monitor";
+ graph [style=filled color="#000000" fillcolor="#faf9cd"]
+
+ bl31 [label="BL31" fillcolor="#ddffb3"];
+ spmd [label="SPMD" fillcolor="#ddffb3" height=1]
+ }
+
+ # SPMC cluster
+ subgraph cluster_spmc {
+ label ="SPMC";
+ graph [style=filled color="#000000" fillcolor="#faf9cd"]
+
+ spmc [label="SPMC" fillcolor="#ddffb3" height=1]
+ }
+ bl2 [label="BL2" width=1.2 height=0.5]
+ }
+
+ # Secure Partitions cluster
+ subgraph cluster_sp {
+ label ="Secure Partitions";
+ graph [style=filled color="#000000" fillcolor="#faf9cd"]
+
+ sp1 [label="SP1" fillcolor="#ddffb3" height=1]
+ sp2 [label="SP2" fillcolor="#ddffb3" height=1]
+ spn [label="SP..." fillcolor="#ddffb3" height=1]
+ }
+
+ # Interactions between nodes
+ sp1 -> spmc [dir="both" label="DF1"]
+ spmc -> spmd [dir="both" label="DF2"]
+ spmd -> nsec [dir="both" label="DF3"]
+ sp1 -> sp2 [dir="both" label="DF4"]
+ spmc -> smmu [lhead=cluster_spmc label="DF5"]
+ bl2 -> spmc [lhead=cluster_spmc label="DF6"]
+ bl2 -> spn [lhead=cluster_spmc label="DF6"]
+ sp1 -> ddr [dir="both" label="DF7"]
+ spmc -> ddr [dir="both" label="DF7"]
+}
+
+@enduml
diff --git a/docs/resources/diagrams/plantuml/tfa_dfd.puml b/docs/resources/diagrams/plantuml/tfa_dfd.puml
new file mode 100644
index 0000000..0007911
--- /dev/null
+++ b/docs/resources/diagrams/plantuml/tfa_dfd.puml
@@ -0,0 +1,66 @@
+/'
+ ' Copyright (c) 2021, Arm Limited. All rights reserved.
+ '
+ ' SPDX-License-Identifier: BSD-3-Clause
+ '/
+
+/'
+TF-A Data Flow Diagram
+'/
+
+@startuml
+digraph tfa_dfd {
+
+ # Arrange nodes from left to right
+ rankdir="LR"
+
+ # Allow arrows to end on cluster boundaries
+ compound=true
+
+ # Default settings for edges and nodes
+ edge [minlen=2 color="#8c1b07"]
+ node [fillcolor="#ffb866" style=filled shape=box fixedsize=true width=1.6 height=0.7]
+
+ # Nodes outside of the trust boundary
+ nsec [label="Non-secure\nClients"]
+ sec [label="Secure\nClients"]
+ dbg [label="Debug & Trace"]
+ logs [label="Logs\n(UART)"]
+ nvm [label="Non-volatile\nMemory"]
+
+ # Trust boundary cluster
+ subgraph cluster_trusted{
+ graph [style=dashed color="#f22430"]
+
+ # HW IPs cluster
+ subgraph cluster_ip{
+ label ="Hardware IPs";
+ graph [style=filled color="#000000" fillcolor="#ffd29e"]
+
+ rank="same"
+ gic [label="GIC" width=1.2 height=0.5]
+ tzc [label="TZ\nController" width=1.2 height=0.5]
+ etc [label="..." shape=none style=none height=0.5]
+ }
+
+ # TF-A cluster
+ subgraph cluster_tfa{
+ label ="TF-A";
+ graph [style=filled color="#000000" fillcolor="#faf9cd"]
+
+ bl1 [label="Boot ROM\n(BL1)" fillcolor="#ddffb3"];
+ bl2 [label="Trusted Boot\nFirmware\n(BL2)" fillcolor="#ddffb3" height=1]
+ bl31 [label="TF-A Runtime\n(BL31)" fillcolor="#ddffb3"]
+ }
+ }
+
+ # Interactions between nodes
+ nvm -> bl31 [lhead=cluster_tfa label="DF1"]
+ logs -> bl31 [dir="back" lhead=cluster_tfa label="DF2"]
+ dbg -> bl2 [dir="both" lhead=cluster_tfa label="DF3"]
+ sec -> bl2 [dir="both" lhead=cluster_tfa label="DF4"]
+ nsec -> bl1 [dir="both" lhead=cluster_tfa, label="DF5"]
+ bl2 -> tzc [dir="both" ltail=cluster_tfa lhead=cluster_ip label="DF6" minlen=1]
+}
+
+@enduml
diff --git a/docs/resources/diagrams/spm-threat-model-trust-boundaries.png b/docs/resources/diagrams/spm-threat-model-trust-boundaries.png
new file mode 100644
index 0000000..58898c5
--- /dev/null
+++ b/docs/resources/diagrams/spm-threat-model-trust-boundaries.png
Binary files differ
diff --git a/docs/threat_model/index.rst b/docs/threat_model/index.rst
new file mode 100644
index 0000000..b5ede69
--- /dev/null
+++ b/docs/threat_model/index.rst
@@ -0,0 +1,21 @@
+Threat Model
+============
+
+Threat modeling is an important part of Secure Development Lifecycle (SDL)
+that helps us identify potential threats and mitigations affecting a system.
+
+In the next sections, we first give a description of the target of evaluation
+using a data flow diagram. Then we provide a list of threats we have identified
+based on the data flow diagram and potential threat mitigations.
+
+.. toctree::
+ :maxdepth: 1
+ :caption: Contents
+ :numbered:
+
+ threat_model
+ threat_model_spm
+
+--------------
+
+*Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.*
diff --git a/docs/threat_model/threat_model.rst b/docs/threat_model/threat_model.rst
new file mode 100644
index 0000000..9f26487
--- /dev/null
+++ b/docs/threat_model/threat_model.rst
@@ -0,0 +1,781 @@
+Generic threat model
+********************
+
+************************
+Introduction
+************************
+This document provides a generic threat model for TF-A firmware.
+
+************************
+Target of Evaluation
+************************
+In this threat model, the target of evaluation is the Trusted
+Firmware for A-class Processors (TF-A). This includes the boot ROM (BL1),
+the trusted boot firmware (BL2) and the runtime EL3 firmware (BL31) as
+shown on Figure 1. Everything else on Figure 1 is outside of the scope of
+the evaluation.
+
+TF-A can be configured in various ways. In this threat model we consider
+only the most basic configuration. To that end we make the following
+assumptions:
+
+- All TF-A images are run from either ROM or on-chip trusted SRAM. This means
+ TF-A is not vulnerable to an attacker that can probe or tamper with off-chip
+ memory.
+- Trusted boot is enabled. This means an attacker can't boot arbitrary images
+ that are not approved by platform providers.
+- There is no Secure-EL2. We don't consider threats that may come with
+ Secure-EL2 software.
+
+Data Flow Diagram
+======================
+Figure 1 shows a high-level data flow diagram for TF-A. The diagram
+shows a model of the different components of a TF-A-based system and
+their interactions with TF-A. A description of each diagram element
+is given on Table 1. On the diagram, the red broken lines indicate
+trust boundaries. Components outside of the broken lines
+are considered untrusted by TF-A.
+
+.. uml:: ../resources/diagrams/plantuml/tfa_dfd.puml
+ :caption: Figure 1: TF-A Data Flow Diagram
+
+.. table:: Table 1: TF-A Data Flow Diagram Description
+
+ +-----------------+--------------------------------------------------------+
+ | Diagram Element | Description |
+ +=================+========================================================+
+ | ``DF1`` | | At boot time, images are loaded from non-volatile |
+ | | memory and verified by TF-A boot firmware. These |
+ | | images include TF-A BL2 and BL31 images, as well as |
+ | | other secure and non-secure images. |
+ +-----------------+--------------------------------------------------------+
+ | ``DF2`` | | TF-A log system framework outputs debug messages |
+ | | over a UART interface. |
+ +-----------------+--------------------------------------------------------+
+ | ``DF3`` | | Debug and trace IP on a platform can allow access |
+ | | to registers and memory of TF-A. |
+ +-----------------+--------------------------------------------------------+
+ | ``DF4`` | | Secure world software (e.g. trusted OS) interact |
+ | | with TF-A through SMC call interface and/or shared |
+ | | memory. |
+ +-----------------+--------------------------------------------------------+
+ | ``DF5`` | | Non-secure world software (e.g. rich OS) interact |
+ | | with TF-A through SMC call interface and/or shared |
+ | | memory. |
+ +-----------------+--------------------------------------------------------+
+ | ``DF6`` | | This path represents the interaction between TF-A and|
+ | | various hardware IPs such as TrustZone controller |
+ | | and GIC. At boot time TF-A configures/initializes the|
+ | | IPs and interacts with them at runtime through |
+ | | interrupts and registers. |
+ +-----------------+--------------------------------------------------------+
+
+
+*********************
+Threat Analysis
+*********************
+In this section we identify and provide assessment of potential threats to TF-A
+firmware. The threats are identified for each diagram element on the
+data flow diagram above.
+
+For each threat, we identify the *asset* that is under threat, the
+*threat agent* and the *threat type*. Each threat is given a *risk rating*
+that represents the impact and likelihood of that threat. We also discuss
+potential mitigations.
+
+Assets
+==================
+We have identified the following assets for TF-A:
+
+.. table:: Table 2: TF-A Assets
+
+ +--------------------+---------------------------------------------------+
+ | Asset | Description |
+ +====================+===================================================+
+ | ``Sensitive Data`` | | These include sensitive data that an attacker |
+ | | must not be able to tamper with (e.g. the Root |
+ | | of Trust Public Key) or see (e.g. secure logs, |
+ | | debugging information such as crash reports). |
+ +--------------------+---------------------------------------------------+
+ | ``Code Execution`` | | This represents the requirement that the |
+ | | platform should run only TF-A code approved by |
+ | | the platform provider. |
+ +--------------------+---------------------------------------------------+
+ | ``Availability`` | | This represents the requirement that TF-A |
+ | | services should always be available for use. |
+ +--------------------+---------------------------------------------------+
+
+Threat Agents
+=====================
+To understand the attack surface, it is important to identify potential
+attackers, i.e. attack entry points. The following threat agents are
+in scope of this threat model.
+
+.. table:: Table 3: Threat Agents
+
+ +-------------------+-------------------------------------------------------+
+ | Threat Agent | Description |
+ +===================+=======================================================+
+ | ``NSCode`` | | Malicious or faulty code running in the Non-secure |
+ | | world, including NS-EL0 NS-EL1 and NS-EL2 levels |
+ +-------------------+-------------------------------------------------------+
+ | ``SecCode`` | | Malicious or faulty code running in the secure |
+ | | world, including S-EL0 and S-EL1 levels |
+ +-------------------+-------------------------------------------------------+
+ | ``AppDebug`` | | Physical attacker using debug signals to access |
+ | | TF-A resources |
+ +-------------------+-------------------------------------------------------+
+ | ``PhysicalAccess``| | Physical attacker having access to external device |
+ | | communication bus and to external flash |
+ | | communication bus using common hardware |
+ +-------------------+-------------------------------------------------------+
+
+.. note::
+
+ In this threat model an advanced physical attacker that has the capability
+ to tamper with a hardware (e.g. "rewiring" a chip using a focused
+ ion beam (FIB) workstation or decapsulate the chip using chemicals) is
+ considered out-of-scope.
+
+Threat Types
+========================
+In this threat model we categorize threats using the `STRIDE threat
+analysis technique`_. In this technique a threat is categorized as one
+or more of these types: ``Spoofing``, ``Tampering``, ``Repudiation``,
+``Information disclosure``, ``Denial of service`` or
+``Elevation of privilege``.
+
+Threat Risk Ratings
+========================
+For each threat identified, a risk rating that ranges
+from *informational* to *critical* is given based on the likelihood of the
+threat occuring if a mitigation is not in place, and the impact of the
+threat (i.e. how severe the consequences could be). Table 4 explains each
+rating in terms of score, impact and likelihood.
+
+.. table:: Table 4: Rating and score as applied to impact and likelihood
+
+ +-----------------------+-------------------------+---------------------------+
+ | **Rating (Score)** | **Impact** | **Likelihood** |
+ +=======================+=========================+===========================+
+ | ``Critical (5)`` | | Extreme impact to | | Threat is almost |
+ | | entire organization | certain to be exploited.|
+ | | if exploited. | |
+ | | | | Knowledge of the threat |
+ | | | and how to exploit it |
+ | | | are in the public |
+ | | | domain. |
+ +-----------------------+-------------------------+---------------------------+
+ | ``High (4)`` | | Major impact to entire| | Threat is relatively |
+ | | organization or single| easy to detect and |
+ | | line of business if | exploit by an attacker |
+ | | exploited | with little skill. |
+ +-----------------------+-------------------------+---------------------------+
+ | ``Medium (3)`` | | Noticeable impact to | | A knowledgeable insider |
+ | | line of business if | or expert attacker could|
+ | | exploited. | exploit the threat |
+ | | | without much difficulty.|
+ +-----------------------+-------------------------+---------------------------+
+ | ``Low (2)`` | | Minor damage if | | Exploiting the threat |
+ | | exploited or could | would require |
+ | | be used in conjunction| considerable expertise |
+ | | with other | and resources |
+ | | vulnerabilities to | |
+ | | perform a more serious| |
+ | | attack | |
+ +-----------------------+-------------------------+---------------------------+
+ | ``Informational (1)`` | | Poor programming | | Threat is not likely |
+ | | practice or poor | to be exploited on its |
+ | | design decision that | own, but may be used to |
+ | | may not represent an | gain information for |
+ | | immediate risk on its | launching another |
+ | | own, but may have | attack |
+ | | security implications | |
+ | | if multiplied and/or | |
+ | | combined with other | |
+ | | threats. | |
+ +-----------------------+-------------------------+---------------------------+
+
+Aggregate risk scores are assigned to identified threats;
+specifically, the impact score multiplied by the likelihood score.
+For example, a threat with high likelihood and low impact would have an
+aggregate risk score of eight (8); that is, four (4) for high likelihood
+multiplied by two (2) for low impact. The aggregate risk score determines
+the finding's overall risk level, as shown in the following table.
+
+.. table:: Table 5: Overall risk levels and corresponding aggregate scores
+
+ +---------------------+-----------------------------------+
+ | Overall Risk Level | Aggregate Risk Score |
+ | | (Impact multiplied by Likelihood) |
+ +=====================+===================================+
+ | Critical | 20–25 |
+ +---------------------+-----------------------------------+
+ | High | 12–19 |
+ +---------------------+-----------------------------------+
+ | Medium | 6–11 |
+ +---------------------+-----------------------------------+
+ | Low | 2–5 |
+ +---------------------+-----------------------------------+
+ | Informational | 1 |
+ +---------------------+-----------------------------------+
+
+The likelihood and impact of a threat depends on the
+target environment in which TF-A is running. For example, attacks
+that require physical access are unlikely in server environments while
+they are more common in Internet of Things(IoT) environments.
+In this threat model we consider three target environments:
+``Internet of Things(IoT)``, ``Mobile`` and ``Server``.
+
+Threat Assessment
+============================
+The following threats were identified by applying STRIDE analysis on
+each diagram element of the data flow diagram.
+
++------------------------+----------------------------------------------------+
+| ID | 01 |
++========================+====================================================+
+| ``Threat`` | | **An attacker can mangle firmware images to |
+| | execute arbitrary code** |
+| | |
+| | | Some TF-A images are loaded from external |
+| | storage. It is possible for an attacker to access|
+| | the external flash memory and change its contents|
+| | physically, through the Rich OS, or using the |
+| | updating mechanism to modify the non-volatile |
+| | images to execute arbitrary code. |
++------------------------+----------------------------------------------------+
+| ``Diagram Elements`` | DF1, DF4, DF5 |
++------------------------+----------------------------------------------------+
+| ``Affected TF-A | BL2, BL31 |
+| Components`` | |
++------------------------+----------------------------------------------------+
+| ``Assets`` | Code Execution |
++------------------------+----------------------------------------------------+
+| ``Threat Agent`` | PhysicalAccess, NSCode, SecCode |
++------------------------+----------------------------------------------------+
+| ``Threat Type`` | Tampering, Elevation of Privilege |
++------------------------+------------------+-----------------+---------------+
+| ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` |
++------------------------+------------------+-----------------+---------------+
+| ``Impact`` | Critical (5) | Critical (5) | Critical (5) |
++------------------------+------------------+-----------------+---------------+
+| ``Likelihood`` | Critical (5) | Critical (5) | Critical (5) |
++------------------------+------------------+-----------------+---------------+
+| ``Total Risk Rating`` | Critical (25) | Critical (25) | Critical (25) |
++------------------------+------------------+-----------------+---------------+
+| ``Mitigations`` | | TF-A implements the `Trusted Board Boot (TBB)`_ |
+| | feature which prevents malicious firmware from |
+| | running on the platform by authenticating all |
+| | firmware images. In addition to this, the TF-A |
+| | boot firmware performs extra checks on |
+| | unauthenticated data, such as FIP metadata, prior|
+| | to use. |
++------------------------+----------------------------------------------------+
+
++------------------------+----------------------------------------------------+
+| ID | 02 |
++========================+====================================================+
+| ``Threat`` | | **An attacker may attempt to boot outdated, |
+| | potentially vulnerable firmware image** |
+| | |
+| | | When updating firmware, an attacker may attempt |
+| | to rollback to an older version that has unfixed |
+| | vulnerabilities. |
++------------------------+----------------------------------------------------+
+| ``Diagram Elements`` | DF1, DF4, DF5 |
++------------------------+----------------------------------------------------+
+| ``Affected TF-A | BL2, BL31 |
+| Components`` | |
++------------------------+----------------------------------------------------+
+| ``Assets`` | Code Execution |
++------------------------+----------------------------------------------------+
+| ``Threat Agent`` | PhysicalAccess, NSCode, SecCode |
++------------------------+----------------------------------------------------+
+| ``Threat Type`` | Tampering |
++------------------------+------------------+-----------------+---------------+
+| ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` |
++------------------------+------------------+-----------------+---------------+
+| ``Impact`` | Critical (5) | Critical (5) | Critical (5) |
++------------------------+------------------+-----------------+---------------+
+| ``Likelihood`` | Critical (5) | Critical (5) | Critical (5) |
++------------------------+------------------+-----------------+---------------+
+| ``Total Risk Rating`` | Critical (25) | Critical (25) | Critical (25) |
++------------------------+------------------+-----------------+---------------+
+| ``Mitigations`` | | TF-A supports anti-rollback protection using |
+| | non-volatile counters (NV counters) as required |
+| | by `TBBR-Client specification`_. After a firmware|
+| | image is validated, the image revision number |
+| | taken from a certificate extension field is |
+| | compared with the corresponding NV counter stored|
+| | in hardware to make sure the new counter value is|
+| | larger or equal to the current counter value. |
+| | Platforms must implement this protection using |
+| | platform specific hardware NV counters. |
++------------------------+----------------------------------------------------+
+
++------------------------+-------------------------------------------------------+
+| ID | 03 |
++========================+=======================================================+
+| ``Threat`` | | **An attacker can use Time-of-Check-Time-of-Use |
+| | (TOCTOU) attack to bypass image authentication |
+| | during the boot process** |
+| | |
+| | | Time-of-Check-Time-of-Use (TOCTOU) threats occur |
+| | when the security check is produced before the time |
+| | the resource is accessed. If an attacker is sitting |
+| | in the middle of the off-chip images, they could |
+| | change the binary containing executable code right |
+| | after the integrity and authentication check has |
+| | been performed. |
++------------------------+-------------------------------------------------------+
+| ``Diagram Elements`` | DF1 |
++------------------------+-------------------------------------------------------+
+| ``Affected TF-A | BL1, BL2 |
+| Components`` | |
++------------------------+-------------------------------------------------------+
+| ``Assets`` | Code Execution, Sensitive Data |
++------------------------+-------------------------------------------------------+
+| ``Threat Agent`` | PhysicalAccess |
++------------------------+-------------------------------------------------------+
+| ``Threat Type`` | Elevation of Privilege |
++------------------------+---------------------+-----------------+---------------+
+| ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` |
++------------------------+---------------------+-----------------+---------------+
+| ``Impact`` | N/A | Critical (5) | Critical (5) |
++------------------------+---------------------+-----------------+---------------+
+| ``Likelihood`` | N/A | Medium (3) | Medium (3) |
++------------------------+---------------------+-----------------+---------------+
+| ``Total Risk Rating`` | N/A | High (15) | High (15) |
++------------------------+---------------------+-----------------+---------------+
+| ``Mitigations`` | | TF-A boot firmware copies image to on-chip |
+| | memory before authenticating an image. |
++------------------------+-------------------------------------------------------+
+
++------------------------+-------------------------------------------------------+
+| ID | 04 |
++========================+=======================================================+
+| ``Threat`` | | **An attacker with physical access can execute |
+| | arbitrary image by bypassing the signature |
+| | verification stage using glitching techniques** |
+| | |
+| | | Glitching (Fault injection) attacks attempt to put |
+| | a hardware into a undefined state by manipulating an|
+| | environmental variable such as power supply. |
+| | |
+| | | TF-A relies on a chain of trust that starts with the|
+| | ROTPK, which is the key stored inside the chip and |
+| | the root of all validation processes. If an attacker|
+| | can break this chain of trust, they could execute |
+| | arbitrary code on the device. This could be |
+| | achieved with physical access to the device by |
+| | attacking the normal execution flow of the |
+| | process using glitching techniques that target |
+| | points where the image is validated against the |
+| | signature. |
++------------------------+-------------------------------------------------------+
+| ``Diagram Elements`` | DF1 |
++------------------------+-------------------------------------------------------+
+| ``Affected TF-A | BL1, BL2 |
+| Components`` | |
++------------------------+-------------------------------------------------------+
+| ``Assets`` | Code Execution |
++------------------------+-------------------------------------------------------+
+| ``Threat Agent`` | PhysicalAccess |
++------------------------+-------------------------------------------------------+
+| ``Threat Type`` | Tampering, Elevation of Privilege |
++------------------------+---------------------+-----------------+---------------+
+| ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` |
++------------------------+---------------------+-----------------+---------------+
+| ``Impact`` | N/A | Critical (5) | Critical (5) |
++------------------------+---------------------+-----------------+---------------+
+| ``Likelihood`` | N/A | Medium (3) | Medium (3) |
++------------------------+---------------------+-----------------+---------------+
+| ``Total Risk Rating`` | N/A | High (15) | High (15) |
++------------------------+---------------------+-----------------+---------------+
+| ``Mitigations`` | | The most effective mitigation is adding glitching |
+| | detection and mitigation circuit at the hardware |
+| | level. However, software techniques, |
+| | such as adding redundant checks when performing |
+| | conditional branches that are security sensitive, |
+| | can be used to harden TF-A against such attacks. |
+| | **At the moment TF-A doesn't implement such |
+| | mitigations.** |
++------------------------+-------------------------------------------------------+
+
++------------------------+---------------------------------------------------+
+| ID | 05 |
++========================+===================================================+
+| ``Threat`` | | **Information leak via UART logs such as |
+| | crashes** |
+| | |
+| | | During the development stages of software it is |
+| | common to include crash reports with detailed |
+| | information of the CPU state including current |
+| | values of the registers, privilege level and |
+| | stack dumps. This information is useful when |
+| | debugging problems before releasing the |
+| | production version, but it could be used by an |
+| | attacker to develop a working exploit if left |
+| | in the production version. |
++------------------------+---------------------------------------------------+
+| ``Diagram Elements`` | DF2 |
++------------------------+---------------------------------------------------+
+| ``Affected TF-A | BL1, BL2, BL31 |
+| Components`` | |
++------------------------+---------------------------------------------------+
+| ``Assets`` | Sensitive Data |
++------------------------+---------------------------------------------------+
+| ``Threat Agent`` | AppDebug |
++------------------------+---------------------------------------------------+
+| ``Threat Type`` | Information Disclosure |
++------------------------+------------------+----------------+---------------+
+| ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` |
++------------------------+------------------+----------------+---------------+
+| ``Impact`` | N/A | Low (2) | Low (2) |
++------------------------+------------------+----------------+---------------+
+| ``Likelihood`` | N/A | High (4) | High (4) |
++------------------------+------------------+----------------+---------------+
+| ``Total Risk Rating`` | N/A | Medium (8) | Medium (8) |
++------------------------+------------------+----------------+---------------+
+| ``Mitigations`` | | In TF-A, crash reporting is only enabled for |
+| | debug builds by default. Alternatively, the log |
+| | level can be tuned at build time (from verbose |
+| | to no output at all), independently of the |
+| | build type. |
++------------------------+---------------------------------------------------+
+
++------------------------+----------------------------------------------------+
+| ID | 06 |
++========================+====================================================+
+| ``Threat`` | | **An attacker can read sensitive data and |
+| | execute arbitrary code through the external |
+| | debug and trace interface** |
+| | |
+| | | Arm processors include hardware-assisted debug |
+| | and trace features that can be controlled without|
+| | the need for software operating on the platform. |
+| | If left enabled without authentication, this |
+| | feature can be used by an attacker to inspect and|
+| | modify TF-A registers and memory allowing the |
+| | attacker to read sensitive data and execute |
+| | arbitrary code. |
++------------------------+----------------------------------------------------+
+| ``Diagram Elements`` | DF3 |
++------------------------+----------------------------------------------------+
+| ``Affected TF-A | BL1, BL2, BL31 |
+| Components`` | |
++------------------------+----------------------------------------------------+
+| ``Assets`` | Code Execution, Sensitive Data |
++------------------------+----------------------------------------------------+
+| ``Threat Agent`` | AppDebug |
++------------------------+----------------------------------------------------+
+| ``Threat Type`` | Tampering, Information Disclosure, |
+| | Elevation of privilege |
++------------------------+------------------+---------------+-----------------+
+| ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` |
++------------------------+------------------+---------------+-----------------+
+| ``Impact`` | N/A | High (4) | High (4) |
++------------------------+------------------+---------------+-----------------+
+| ``Likelihood`` | N/A | Critical (5) | Critical (5) |
++------------------------+------------------+---------------+-----------------+
+| ``Total Risk Rating`` | N/A | Critical (20) | Critical (20) |
++------------------------+------------------+---------------+-----------------+
+| ``Mitigations`` | | Configuration of debug and trace capabilities is |
+| | platform specific. Therefore, platforms must |
+| | disable the debug and trace capability for |
+| | production releases or enable proper debug |
+| | authentication as recommended by [`DEN0034`_]. |
++------------------------+----------------------------------------------------+
+
++------------------------+------------------------------------------------------+
+| ID | 07 |
++========================+======================================================+
+| ``Threat`` | | **An attacker can perform a denial-of-service |
+| | attack by using a broken SMC call that causes the |
+| | system to reboot or enter into unknown state.** |
+| | |
+| | | Secure and non-secure clients access TF-A services |
+| | through SMC calls. Malicious code can attempt to |
+| | place the TF-A runtime into an inconsistent state |
+| | by calling unimplemented SMC call or by passing |
+| | invalid arguments. |
++------------------------+------------------------------------------------------+
+| ``Diagram Elements`` | DF4, DF5 |
++------------------------+------------------------------------------------------+
+| ``Affected TF-A | BL31 |
+| Components`` | |
++------------------------+------------------------------------------------------+
+| ``Assets`` | Availability |
++------------------------+------------------------------------------------------+
+| ``Threat Agent`` | NSCode, SecCode |
++------------------------+------------------------------------------------------+
+| ``Threat Type`` | Denial of Service |
++------------------------+-------------------+----------------+-----------------+
+| ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` |
++------------------------+-------------------+----------------+-----------------+
+| ``Impact`` | Medium (3) | Medium (3) | Medium (3) |
++------------------------+-------------------+----------------+-----------------+
+| ``Likelihood`` | High (4) | High (4) | High (4) |
++------------------------+-------------------+----------------+-----------------+
+| ``Total Risk Rating`` | High (12) | High (12) | High (12) |
++------------------------+-------------------+----------------+-----------------+
+| ``Mitigations`` | | The generic TF-A code validates SMC function ids |
+| | and arguments before using them. |
+| | Platforms that implement SiP services must also |
+| | validate SMC call arguments. |
++------------------------+------------------------------------------------------+
+
++------------------------+------------------------------------------------------+
+| ID | 08 |
++========================+======================================================+
+| ``Threat`` | | **Memory corruption due to memory overflows and |
+| | lack of boundary checking when accessing resources |
+| | could allow an attacker to execute arbitrary code, |
+| | modify some state variable to change the normal |
+| | flow of the program, or leak sensitive |
+| | information** |
+| | |
+| | | Like in other software, the Trusted Firmware has |
+| | multiple points where memory corruption security |
+| | errors can arise. Memory corruption is a dangerous |
+| | security issue since it could allow an attacker |
+| | to execute arbitrary code, modify some state |
+| | variable to change the normal flow of the program, |
+| | or leak sensitive information. |
+| | |
+| | | Some of the errors include integer overflow, |
+| | buffer overflow, incorrect array boundary checks, |
+| | and incorrect error management. |
+| | Improper use of asserts instead of proper input |
+| | validations might also result in these kinds of |
+| | errors in release builds. |
++------------------------+------------------------------------------------------+
+| ``Diagram Elements`` | DF4, DF5 |
++------------------------+------------------------------------------------------+
+| ``Affected TF-A | BL1, BL2, BL31 |
+| Components`` | |
++------------------------+------------------------------------------------------+
+| ``Assets`` | Code Execution, Sensitive Data |
++------------------------+------------------------------------------------------+
+| ``Threat Agent`` | NSCode, SecCode |
++------------------------+------------------------------------------------------+
+| ``Threat Type`` | Tampering, Information Disclosure, |
+| | Elevation of Privilege |
++------------------------+-------------------+-----------------+----------------+
+| ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` |
++------------------------+-------------------+-----------------+----------------+
+| ``Impact`` | Critical (5) | Critical (5) | Critical (5) |
++------------------------+-------------------+-----------------+----------------+
+| ``Likelihood`` | Medium (3 | Medium (3) | Medium (3) |
++------------------------+-------------------+-----------------+----------------+
+| ``Total Risk Rating`` | High (15) | High (15) | High (15) |
++------------------------+-------------------+-----------------+----------------+
+| ``Mitigations`` | | TF-A uses a combination of manual code reviews and |
+| | automated program analysis and testing to detect |
+| | and fix memory corruption bugs. All TF-A code |
+| | including platform code go through manual code |
+| | reviews. Additionally, static code analysis is |
+| | performed using Coverity Scan on all TF-A code. |
+| | The code is also tested with |
+| | `Trusted Firmware-A Tests`_ on Juno and FVP |
+| | platforms. |
+| | |
+| | | Data received from normal world, such as addresses |
+| | and sizes identifying memory regions, are |
+| | sanitized before being used. These security checks |
+| | make sure that the normal world software does not |
+| | access memory beyond its limit. |
+| | |
+| | | By default *asserts* are only used to check for |
+| | programming errors in debug builds. Other types of |
+| | errors are handled through condition checks that |
+| | remain enabled in release builds. See |
+| | `TF-A error handling policy`_. TF-A provides an |
+| | option to use *asserts* in release builds, however |
+| | we recommend using proper runtime checks instead |
+| | of relying on asserts in release builds. |
++------------------------+------------------------------------------------------+
+
++------------------------+------------------------------------------------------+
+| ID | 09 |
++========================+======================================================+
+| ``Threat`` | | **Improperly handled SMC calls can leak register |
+| | contents** |
+| | |
+| | | When switching between secure and non-secure |
+| | states, register contents of Secure world or |
+| | register contents of other normal world clients |
+| | can be leaked. |
++------------------------+------------------------------------------------------+
+| ``Diagram Elements`` | DF5 |
++------------------------+------------------------------------------------------+
+| ``Affected TF-A | BL31 |
+| Components`` | |
++------------------------+------------------------------------------------------+
+| ``Assets`` | Sensitive Data |
++------------------------+------------------------------------------------------+
+| ``Threat Agent`` | NSCode |
++------------------------+------------------------------------------------------+
+| ``Threat Type`` | Information Disclosure |
++------------------------+-------------------+----------------+-----------------+
+| ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` |
++------------------------+-------------------+----------------+-----------------+
+| ``Impact`` | Medium (3) | Medium (3) | Medium (3) |
++------------------------+-------------------+----------------+-----------------+
+| ``Likelihood`` | High (4) | High (4) | High (4) |
++------------------------+-------------------+----------------+-----------------+
+| ``Total Risk Rating`` | High (12) | High (12) | High (12) |
++------------------------+-------------------+----------------+-----------------+
+| ``Mitigations`` | | TF-A saves and restores registers |
+| | by default when switching contexts. Build options |
+| | are also provided to save/restore additional |
+| | registers such as floating-point registers. |
++------------------------+------------------------------------------------------+
+
++------------------------+-----------------------------------------------------+
+| ID | 10 |
++========================+=====================================================+
+| ``Threat`` | | **SMC calls can leak sensitive information from |
+| | TF-A memory via microarchitectural side channels**|
+| | |
+| | | Microarchitectural side-channel attacks such as |
+| | `Spectre`_ can be used to leak data across |
+| | security boundaries. An attacker might attempt to |
+| | use this kind of attack to leak sensitive |
+| | data from TF-A memory. |
++------------------------+-----------------------------------------------------+
+| ``Diagram Elements`` | DF4, DF5 |
++------------------------+-----------------------------------------------------+
+| ``Affected TF-A | BL31 |
+| Components`` | |
++------------------------+-----------------------------------------------------+
+| ``Assets`` | Sensitive Data |
++------------------------+-----------------------------------------------------+
+| ``Threat Agent`` | SecCode, NSCode |
++------------------------+-----------------------------------------------------+
+| ``Threat Type`` | Information Disclosure |
++------------------------+-------------------+----------------+----------------+
+| ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` |
++------------------------+-------------------+----------------+----------------+
+| ``Impact`` | Medium (3) | Medium (3) | Medium (3) |
++------------------------+-------------------+----------------+----------------+
+| ``Likelihood`` | Medium (3) | Medium (3) | Medium (3) |
++------------------------+-------------------+----------------+----------------+
+| ``Total Risk Rating`` | Medium (9) | Medium (9) | Medium (9) |
++------------------------+-------------------+----------------+----------------+
+| ``Mitigations`` | | TF-A implements software mitigations for Spectre |
+| | type attacks as recommended by `Cache Speculation |
+| | Side-channels`_ for the generic code. SiPs should |
+| | implement similar mitigations for code that is |
+| | deemed to be vulnerable to such attacks. |
++------------------------+-----------------------------------------------------+
+
++------------------------+----------------------------------------------------+
+| ID | 11 |
++========================+====================================================+
+| ``Threat`` | | **Misconfiguration of the Memory Management Unit |
+| | (MMU) may allow a normal world software to |
+| | access sensitive data or execute arbitrary |
+| | code** |
+| | |
+| | | A misconfiguration of the MMU could |
+| | lead to an open door for software running in the |
+| | normal world to access sensitive data or even |
+| | execute code if the proper security mechanisms |
+| | are not in place. |
++------------------------+----------------------------------------------------+
+| ``Diagram Elements`` | DF5, DF6 |
++------------------------+----------------------------------------------------+
+| ``Affected TF-A | BL1, BL2, BL31 |
+| Components`` | |
++------------------------+----------------------------------------------------+
+| ``Assets`` | Sensitive Data, Code execution |
++------------------------+----------------------------------------------------+
+| ``Threat Agent`` | NSCode |
++------------------------+----------------------------------------------------+
+| ``Threat Type`` | Information Disclosure, Elevation of Privilege |
++------------------------+-----------------+-----------------+----------------+
+| ``Application`` | ``Server`` | ``IoT`` | ``Mobile`` |
++------------------------+-----------------+-----------------+----------------+
+| ``Impact`` | Critical (5) | Critical (5) | Critical (5) |
++------------------------+-----------------+-----------------+----------------+
+| ``Likelihood`` | High (4) | High (4) | High (4) |
++------------------------+-----------------+-----------------+----------------+
+| ``Total Risk Rating`` | Critical (20) | Critical (20) | Critical (20) |
++------------------------+-----------------+-----------------+----------------+
+| ``Mitigations`` | | In TF-A, configuration of the MMU is done |
+| | through a translation tables library. The |
+| | library provides APIs to define memory regions |
+| | and assign attributes including memory types and |
+| | access permissions. Memory configurations are |
+| | platform specific, therefore platforms need make |
+| | sure the correct attributes are assigned to |
+| | memory regions. When assigning access |
+| | permissions, principle of least privilege ought |
+| | to be enforced, i.e. we should not grant more |
+| | privileges than strictly needed, e.g. code |
+| | should be read-only executable, RO data should |
+| | be read-only XN, and so on. |
++------------------------+----------------------------------------------------+
+
++------------------------+-----------------------------------------------------+
+| ID | 12 |
++========================+=====================================================+
+| ``Threat`` | | **Incorrect configuration of Performance Monitor |
+| | Unit (PMU) counters can allow an attacker to |
+| | mount side-channel attacks using information |
+| | exposed by the counters** |
+| | |
+| | | Non-secure software can configure PMU registers |
+| | to count events at any exception level and in |
+| | both Secure and Non-secure states. This allows |
+| | a Non-secure software (or a lower-level Secure |
+| | software) to potentially carry out |
+| | side-channel timing attacks against TF-A. |
++------------------------+-----------------------------------------------------+
+| ``Diagram Elements`` | DF5, DF6 |
++------------------------+-----------------------------------------------------+
+| ``Affected TF-A | BL31 |
+| Components`` | |
++------------------------+-----------------------------------------------------+
+| ``Assets`` | Sensitive Data |
++------------------------+-----------------------------------------------------+
+| ``Threat Agent`` | NSCode |
++------------------------+-----------------------------------------------------+
+| ``Threat Type`` | Information Disclosure |
++------------------------+-------------------+----------------+----------------+
+| ``Impact`` | Medium (3) | Medium (3) | Medium (3) |
++------------------------+-------------------+----------------+----------------+
+| ``Likelihood`` | Low (2) | Low (2) | Low (2) |
++------------------------+-------------------+----------------+----------------+
+| ``Total Risk Rating`` | Medium (6) | Medium (6) | Medium (6) |
++------------------------+-------------------+----------------+----------------+
+| ``Mitigations`` | | TF-A follows mitigation strategies as described |
+| | in `Secure Development Guidelines`_. General |
+| | events and cycle counting in the Secure world is |
+| | prohibited by default when applicable. However, |
+| | on some implementations (e.g. PMUv3) Secure world |
+| | event counting depends on external debug interface|
+| | signals, i.e. Secure world event counting is |
+| | enabled if external debug is enabled. |
+| | Configuration of debug signals is platform |
+| | specific, therefore platforms need to make sure |
+| | that external debug is disabled in production or |
+| | proper debug authentication is in place. |
++------------------------+-----------------------------------------------------+
+
+--------------
+
+*Copyright (c) 2021, Arm Limited. All rights reserved.*
+
+
+.. _STRIDE threat analysis technique: https://docs.microsoft.com/en-us/azure/security/develop/threat-modeling-tool-threats#stride-model
+.. _DEN0034: https://developer.arm.com/documentation/den0034/latest
+.. _Cache Speculation Side-channels: https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability
+.. _Spectre: https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability
+.. _TBBR-Client specification: https://developer.arm.com/documentation/den0006/d/
+.. _Trusted Board Boot (TBB): https://trustedfirmware-a.readthedocs.io/en/latest/design/trusted-board-boot.html
+.. _TF-A error handling policy: https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#error-handling-and-robustness
+.. _Secure Development Guidelines: https://trustedfirmware-a.readthedocs.io/en/latest/process/security-hardening.html#secure-development-guidelines
+.. _Trusted Firmware-A Tests: https://git.trustedfirmware.org/TF-A/tf-a-tests.git/about/
diff --git a/docs/threat_model/threat_model_spm.rst b/docs/threat_model/threat_model_spm.rst
new file mode 100644
index 0000000..96d33a2
--- /dev/null
+++ b/docs/threat_model/threat_model_spm.rst
@@ -0,0 +1,617 @@
+SPMC threat model
+*****************
+
+************************
+Introduction
+************************
+This document provides a threat model for the TF-A `Secure Partition Manager`_
+(SPM) implementation or more generally the S-EL2 reference firmware running on
+systems implementing the FEAT_SEL2 (formerly Armv8.4 Secure EL2) architecture
+extension. The SPM implementation is based on the `Arm Firmware Framework for
+Armv8-A`_ specification.
+
+In brief, the broad FF-A specification and S-EL2 firmware implementation
+provide:
+
+- Isolation of mutually mistrusting SW components, or endpoints in the FF-A
+ terminology.
+- Distinct sandboxes in the secure world called secure partitions. This permits
+ isolation of services from multiple vendors.
+- A standard protocol for communication and memory sharing between FF-A
+ endpoints.
+- Mutual isolation of the normal world and the secure world (e.g. a Trusted OS
+ is prevented to map an arbitrary NS physical memory region such as the kernel
+ or the Hypervisor).
+
+************************
+Target of Evaluation
+************************
+In this threat model, the target of evaluation is the S-EL2 firmware or the
+``Secure Partition Manager Core`` component (SPMC).
+The monitor and SPMD at EL3 are covered by the `Generic TF-A threat model`_.
+
+The scope for this threat model is:
+
+- The TF-A implementation for the S-EL2 SPMC based on the Hafnium hypervisor
+ running in the secure world of TrustZone (at S-EL2 exception level).
+ The threat model is not related to the normal world Hypervisor or VMs.
+ The S-EL1 SPMC solution is not covered.
+- The implementation complies with the FF-A v1.0 specification.
+- Secure partitions are statically provisioned at boot time.
+- Focus on the run-time part of the life-cycle (no specific emphasis on boot
+ time, factory firmware provisioning, firmware udpate etc.)
+- Not covering advanced or invasive physical attacks such as decapsulation,
+ FIB etc.
+- Assumes secure boot or in particular TF-A trusted boot (TBBR or dual CoT) is
+ enabled. An attacker cannot boot arbitrary images that are not approved by the
+ SiP or platform providers.
+
+Data Flow Diagram
+======================
+Figure 1 shows a high-level data flow diagram for the SPM split into an SPMD
+component at EL3 and an SPMC component at S-EL2. The SPMD mostly acts as a
+relayer/pass-through between the normal world and the secure world. It is
+assumed to expose small attack surface.
+
+A description of each diagram element is given in Table 1. In the diagram, the
+red broken lines indicate trust boundaries.
+
+Components outside of the broken lines are considered untrusted.
+
+.. uml:: ../resources/diagrams/plantuml/spm_dfd.puml
+ :caption: Figure 1: SPMC Data Flow Diagram
+
+.. table:: Table 1: SPMC Data Flow Diagram Description
+
+ +---------------------+--------------------------------------------------------+
+ | Diagram Element | Description |
+ +=====================+========================================================+
+ | ``DF1`` | SP to SPMC communication. FF-A function invocation or |
+ | | implementation-defined Hypervisor call. |
+ +---------------------+--------------------------------------------------------+
+ | ``DF2`` | SPMC to SPMD FF-A call. |
+ +---------------------+--------------------------------------------------------+
+ | ``DF3`` | SPMD to NS forwarding. |
+ +---------------------+--------------------------------------------------------+
+ | ``DF4`` | SP to SP FF-A direct message request/response. |
+ | | Note as a matter of simplifying the diagram |
+ | | the SP to SP communication happens through the SPMC |
+ | | (SP1 performs a direct message request to the |
+ | | SPMC targeting SP2 as destination. And similarly for |
+ | | the direct message response from SP2 to SP1). |
+ +---------------------+--------------------------------------------------------+
+ | ``DF5`` | HW control. |
+ +---------------------+--------------------------------------------------------+
+ | ``DF6`` | Bootloader image loading. |
+ +---------------------+--------------------------------------------------------+
+ | ``DF7`` | External memory access. |
+ +---------------------+--------------------------------------------------------+
+
+*********************
+Threat Analysis
+*********************
+
+This threat model follows a similar methodology to the `Generic TF-A threat model`_.
+The following sections define:
+
+- Trust boundaries
+- Assets
+- Theat agents
+- Threat types
+
+Trust boundaries
+============================
+
+- Normal world is untrusted.
+- Secure world and normal world are separate trust boundaries.
+- EL3 monitor, SPMD and SPMC are trusted.
+- Bootloaders (in particular BL1/BL2 if using TF-A) and run-time BL31 are
+ implicitely trusted by the usage of secure boot.
+- EL3 monitor, SPMD, SPMC do not trust SPs.
+
+.. figure:: ../resources/diagrams/spm-threat-model-trust-boundaries.png
+
+ Figure 2: Trust boundaries
+
+Assets
+============================
+
+The following assets are identified:
+
+- SPMC state.
+- SP state.
+- Information exchange between endpoints (partition messages).
+- SPMC secrets (e.g. pointer authentication key when enabled)
+- SP secrets (e.g. application keys).
+- Scheduling cycles.
+- Shared memory.
+
+Threat Agents
+============================
+
+The following threat agents are identified:
+
+- NS-Endpoint identifies a non-secure endpoint: normal world client at NS-EL2
+ (Hypervisor) or NS-EL1 (VM or OS kernel).
+- S-Endpoint identifies a secure endpoint typically a secure partition.
+- Hardware attacks (non-invasive) requiring a physical access to the device,
+ such as bus probing or DRAM stress.
+
+Threat types
+============================
+
+The following threat categories as exposed in the `Generic TF-A threat model`_
+are re-used:
+
+- Spoofing
+- Tampering
+- Repudiation
+- Information disclosure
+- Denial of service
+- Elevation of privileges
+
+Similarly this threat model re-uses the same threat risk ratings. The risk
+analysis is evaluated based on the environment being ``Server`` or ``Mobile``.
+
+Threat Assessment
+============================
+
+The following threats are identified by applying STRIDE analysis on each diagram
+element of the data flow diagram.
+
++------------------------+----------------------------------------------------+
+| ID | 01 |
++========================+====================================================+
+| ``Threat`` | **An endpoint impersonates the sender or receiver |
+| | FF-A ID in a direct request/response invocation.** |
++------------------------+----------------------------------------------------+
+| ``Diagram Elements`` | DF1, DF2, DF3, DF4 |
++------------------------+----------------------------------------------------+
+| ``Affected TF-A | SPMD, SPMC |
+| Components`` | |
++------------------------+----------------------------------------------------+
+| ``Assets`` | SP state |
++------------------------+----------------------------------------------------+
+| ``Threat Agent`` | NS-Endpoint, S-Endpoint |
++------------------------+----------------------------------------------------+
+| ``Threat Type`` | Spoofing |
++------------------------+------------------+-----------------+---------------+
+| ``Application`` | ``Server`` | ``Mobile`` | |
++------------------------+------------------++----------------+---------------+
+| ``Impact`` | Critical(5) | Critical(5) | |
++------------------------+------------------++----------------+---------------+
+| ``Likelihood`` | Critical(5) | Critical(5) | |
++------------------------+------------------++----------------+---------------+
+| ``Total Risk Rating`` | Critical(25) | Critical(25) | |
++------------------------+------------------+-----------------+---------------+
+| ``Mitigations`` | The TF-A SPMC does not mitigate this threat. |
+| | The guidance below is left for a system integrator |
+| | to implemented as necessary. |
+| | The SPMC must enforce checks in the direct message |
+| | request/response interfaces such an endpoint cannot|
+| | spoof the origin and destination worlds (e.g. a NWd|
+| | originated message directed to the SWd cannot use a|
+| | SWd ID as the sender ID). |
+| | Additionally a software component residing in the |
+| | SPMC can be added for the purpose of direct |
+| | request/response filtering. |
+| | It can be configured with the list of known IDs |
+| | and about which interaction can occur between one |
+| | and another endpoint (e.g. which NWd endpoint ID |
+| | sends a direct request to which SWd endpoint ID). |
+| | This component checks the sender/receiver fields |
+| | for a legitimate communication between endpoints. |
+| | A similar component can exist in the OS kernel |
+| | driver, or Hypervisor although it remains untrusted|
+| | by the SPMD/SPMC. |
++------------------------+----------------------------------------------------+
+
++------------------------+----------------------------------------------------+
+| ID | 02 |
++========================+====================================================+
+| ``Threat`` | **Tampering with memory shared between an endpoint |
+| | and the SPMC.** |
+| | A malicious endpoint may attempt tampering with its|
+| | RX/TX buffer contents while the SPMC is processing |
+| | it (TOCTOU). |
++------------------------+----------------------------------------------------+
+| ``Diagram Elements`` | DF1, DF3, DF4, DF7 |
++------------------------+----------------------------------------------------+
+| ``Affected TF-A | SPMC |
+| Components`` | |
++------------------------+----------------------------------------------------+
+| ``Assets`` | Shared memory, Information exchange |
++------------------------+----------------------------------------------------+
+| ``Threat Agent`` | NS-Endpoint, S-Endpoint |
++------------------------+----------------------------------------------------+
+| ``Threat Type`` | Tampering |
++------------------------+------------------+-----------------+---------------+
+| ``Application`` | ``Server`` | ``Mobile`` | |
++------------------------+------------------+-----------------+---------------+
+| ``Impact`` | High (4) | High (4) | |
++------------------------+------------------+-----------------+---------------+
+| ``Likelihood`` | High (4) | High (4) | |
++------------------------+------------------+-----------------+---------------+
+| ``Total Risk Rating`` | High (16) | High (16) | |
++------------------------+------------------+-----------------+---------------+
+| ``Mitigations`` | In context of FF-A v1.0 this is the case of sharing|
+| | the RX/TX buffer pair and usage in the |
+| | PARTITION_INFO_GET or mem sharing primitives. |
+| | The SPMC must copy the contents of the TX buffer |
+| | to an internal temporary buffer before processing |
+| | its contents. The SPMC must implement hardened |
+| | input validation on data transmitted through the TX|
+| | buffer by an untrusted endpoint. |
+| | The TF-A SPMC mitigates this threat by enforcing |
+| | checks on data transmitted through RX/TX buffers. |
++------------------------+----------------------------------------------------+
+
++------------------------+----------------------------------------------------+
+| ID | 03 |
++========================+====================================================+
+| ``Threat`` | **An endpoint may tamper with its own state or the |
+| | state of another endpoint.** |
+| | A malicious endpoint may attempt violating: |
+| | - its own or another SP state by using an unusual |
+| | combination (or out-of-order) FF-A function |
+| | invocations. |
+| | This can also be an endpoint emitting |
+| | FF-A function invocations to another endpoint while|
+| | the latter in not in a state to receive it (e.g. a |
+| | SP sends a direct request to the normal world early|
+| | while the normal world is not booted yet). |
+| | - the SPMC state itself by employing unexpected |
+| | transitions in FF-A memory sharing, direct requests|
+| | and responses, or handling of interrupts. |
+| | This can be led by random stimuli injection or |
+| | fuzzing. |
++------------------------+----------------------------------------------------+
+| ``Diagram Elements`` | DF1, DF2, DF3, DF4 |
++------------------------+----------------------------------------------------+
+| ``Affected TF-A | SPMD, SPMC |
+| Components`` | |
++------------------------+----------------------------------------------------+
+| ``Assets`` | SP state, SPMC state |
++------------------------+----------------------------------------------------+
+| ``Threat Agent`` | NS-Endpoint, S-Endpoint |
++------------------------+----------------------------------------------------+
+| ``Threat Type`` | Tampering |
++------------------------+------------------+-----------------+---------------+
+| ``Application`` | ``Server`` | ``Mobile`` | |
++------------------------+------------------+-----------------+---------------+
+| ``Impact`` | High (4) | High (4) | |
++------------------------+------------------+-----------------+---------------+
+| ``Likelihood`` | Medium (3) | Medium (3) | |
++------------------------+------------------+-----------------+---------------+
+| ``Total Risk Rating`` | High (12) | High (12) | |
++------------------------+------------------+-----------------+---------------+
+| ``Mitigations`` | The SPMC may be vulnerable to invalid state |
+| | transitions for itself or while handling an SP |
+| | state. The FF-A v1.1 specification provides a |
+| | guidance on those state transitions (run-time |
+| | model). The TF-A SPMC will be hardened in future |
+| | releases to follow this guidance. |
+| | Additionally The TF-A SPMC mitigates the threat by |
+| | runs of the Arm `FF-A ACS`_ compliance test suite. |
++------------------------+----------------------------------------------------+
+
++------------------------+----------------------------------------------------+
+| ID | 04 |
++========================+====================================================+
+| ``Threat`` | *An attacker may attempt injecting errors by the |
+| | use of external DRAM stress techniques.** |
+| | A malicious agent may attempt toggling an SP |
+| | Stage-2 MMU descriptor bit within the page tables |
+| | that the SPMC manages. This can happen in Rowhammer|
+| | types of attack. |
++------------------------+----------------------------------------------------+
+| ``Diagram Elements`` | DF7 |
++------------------------+----------------------------------------------------+
+| ``Affected TF-A | SPMC |
+| Components`` | |
++------------------------+----------------------------------------------------+
+| ``Assets`` | SP or SPMC state |
++------------------------+----------------------------------------------------+
+| ``Threat Agent`` | Hardware attack |
++------------------------+----------------------------------------------------+
+| ``Threat Type`` | Tampering |
++------------------------+------------------+---------------+-----------------+
+| ``Application`` | ``Server`` | ``Mobile`` | |
++------------------------+------------------+---------------+-----------------+
+| ``Impact`` | High (4) | High (4) | |
++------------------------+------------------+---------------+-----------------+
+| ``Likelihood`` | Low (2) | Medium (3) | |
++------------------------+------------------+---------------+-----------------+
+| ``Total Risk Rating`` | Medium (8) | High (12) | |
++------------------------+------------------+---------------+-----------------+
+| ``Mitigations`` | The TF-A SPMC does not provide mitigations to this |
+| | type of attack. It can be addressed by the use of |
+| | dedicated HW circuity or hardening at the chipset |
+| | or platform level left to the integrator. |
++------------------------+----------------------------------------------------+
+
++------------------------+----------------------------------------------------+
+| ID | 05 |
++========================+====================================================+
+| ``Threat`` | **Protection of the SPMC from a DMA capable device |
+| | upstream to an SMMU.** |
+| | A device may attempt to tamper with the internal |
+| | SPMC code/data sections. |
++------------------------+----------------------------------------------------+
+| ``Diagram Elements`` | DF5 |
++------------------------+----------------------------------------------------+
+| ``Affected TF-A | SPMC |
+| Components`` | |
++------------------------+----------------------------------------------------+
+| ``Assets`` | SPMC or SP state |
++------------------------+----------------------------------------------------+
+| ``Threat Agent`` | NS-Endpoint, S-Endpoint |
++------------------------+----------------------------------------------------+
+| ``Threat Type`` | Tampering, Elevation of privileges |
++------------------------+------------------+---------------+-----------------+
+| ``Application`` | ``Server`` | ``Mobile`` | |
++------------------------+------------------+---------------+-----------------+
+| ``Impact`` | High (4) | High (4) | |
++------------------------+------------------+---------------+-----------------+
+| ``Likelihood`` | Medium (3) | Medium (3) | |
++------------------------+------------------+---------------+-----------------+
+| ``Total Risk Rating`` | High (12) | High (12) | |
++------------------------+------------------+---------------+-----------------+
+| ``Mitigations`` | A platform may prefer assigning boot time, |
+| | statically alocated memory regions through the SMMU|
+| | configuration and page tables. The FF-A v1.1 |
+| | specification provisions this capability through |
+| | static DMA isolation. |
+| | The TF-A SPMC does not mitigate this threat. |
+| | It will adopt the static DMA isolation approach in |
+| | a future release. |
++------------------------+----------------------------------------------------+
+
++------------------------+----------------------------------------------------+
+| ID | 06 |
++========================+====================================================+
+| ``Threat`` | **Replay fragments of past communication between |
+| | endpoints.** |
+| | A malicious endpoint may replay a message exchange |
+| | that occured between two legitimate endpoint as |
+| | a matter of triggering a malfunction or extracting |
+| | secrets from the receiving endpoint. In particular |
+| | the memory sharing operation with fragmented |
+| | messages between an endpoint and the SPMC may be |
+| | replayed by a malicious agent as a matter of |
+| | getting access or gaining permissions to a memory |
+| | region which does not belong to this agent. |
++------------------------+----------------------------------------------------+
+| ``Diagram Elements`` | DF2, DF3 |
++------------------------+----------------------------------------------------+
+| ``Affected TF-A | SPMC |
+| Components`` | |
++------------------------+----------------------------------------------------+
+| ``Assets`` | Information exchange |
++------------------------+----------------------------------------------------+
+| ``Threat Agent`` | NS-Endpoint, S-Endpoint |
++------------------------+----------------------------------------------------+
+| ``Threat Type`` | Repdudiation |
++------------------------+------------------+---------------+-----------------+
+| ``Application`` | ``Server`` | ``Mobile`` | |
++------------------------+------------------+---------------+-----------------+
+| ``Impact`` | Medium (3) | Medium (3) | |
++------------------------+------------------+---------------+-----------------+
+| ``Likelihood`` | High (4) | High (4) | |
++------------------------+------------------+---------------+-----------------+
+| ``Total Risk Rating`` | High (12) | High (12) | |
++------------------------+------------------+---------------+-----------------+
+| ``Mitigations`` | The TF-A SPMC does not mitigate this threat. |
++------------------------+----------------------------------------------------+
+
++------------------------+----------------------------------------------------+
+| ID | 07 |
++========================+====================================================+
+| ``Threat`` | **A malicious endpoint may attempt to extract data |
+| | or state information by the use of invalid or |
+| | incorrect input arguments.** |
+| | Lack of input parameter validation or side effects |
+| | of maliciously forged input parameters might affect|
+| | the SPMC. |
++------------------------+----------------------------------------------------+
+| ``Diagram Elements`` | DF1, DF2, DF3, DF4 |
++------------------------+----------------------------------------------------+
+| ``Affected TF-A | SPMD, SPMC |
+| Components`` | |
++------------------------+----------------------------------------------------+
+| ``Assets`` | SP secrets, SPMC secrets, SP state, SPMC state |
++------------------------+----------------------------------------------------+
+| ``Threat Agent`` | NS-Endpoint, S-Endpoint |
++------------------------+----------------------------------------------------+
+| ``Threat Type`` | Information discolure |
++------------------------+------------------+---------------+-----------------+
+| ``Application`` | ``Server`` | ``Mobile`` | |
++------------------------+------------------+---------------+-----------------+
+| ``Impact`` | High (4) | High (4) | |
++------------------------+------------------+---------------+-----------------+
+| ``Likelihood`` | Medium (3) | Medium (3) | |
++------------------------+------------------+---------------+-----------------+
+| ``Total Risk Rating`` | High (12) | High (12) | |
++------------------------+------------------+---------------+-----------------+
+| ``Mitigations`` | Secure Partitions must follow security standards |
+| | and best practises as a way to mitigate the risk |
+| | of common vulnerabilities to be exploited. |
+| | The use of software (canaries) or hardware |
+| | hardening techniques (XN, WXN, BTI, pointer |
+| | authentication, MTE) helps detecting and stopping |
+| | an exploitation early. |
+| | The TF-A SPMC mitigates this threat by implementing|
+| | stack protector, pointer authentication, BTI, XN, |
+| | WXN, security hardening techniques. |
++------------------------+----------------------------------------------------+
+
++------------------------+----------------------------------------------------+
+| ID | 08 |
++========================+====================================================+
+| ``Threat`` | **A malicious endpoint may forge a direct message |
+| | request such that it reveals the internal state of |
+| | another endpoint through the direct message |
+| | response.** |
+| | The secure partition or SPMC replies to a partition|
+| | message by a direct message response with |
+| | information which may reveal its internal state |
+| | (.e.g. partition message response outside of |
+| | allowed bounds). |
++------------------------+----------------------------------------------------+
+| ``Diagram Elements`` | DF1, DF2, DF3, DF4 |
++------------------------+----------------------------------------------------+
+| ``Affected TF-A | SPMC |
+| Components`` | |
++------------------------+----------------------------------------------------+
+| ``Assets`` | SPMC or SP state |
++------------------------+----------------------------------------------------+
+| ``Threat Agent`` | NS-Endpoint, S-Endpoint |
++------------------------+----------------------------------------------------+
+| ``Threat Type`` | Information discolure |
++------------------------+------------------+---------------+-----------------+
+| ``Application`` | ``Server`` | ``Mobile`` | |
++------------------------+------------------+---------------+-----------------+
+| ``Impact`` | Medium (3) | Medium (3) | |
++------------------------+------------------+---------------+-----------------+
+| ``Likelihood`` | Low (2) | Low (2) | |
++------------------------+------------------+---------------+-----------------+
+| ``Total Risk Rating`` | Medium (6) | Medium (6) | |
++------------------------+------------------+---------------+-----------------+
+| ``Mitigations`` | For the specific case of direct requests targetting|
+| | the SPMC, the latter is hardened to prevent |
+| | its internal state or the state of an SP to be |
+| | revealed through a direct message response. |
+| | Further FF-A v1.1 guidance about run time models |
+| | and partition states will be implemented in future |
+| | TF-A SPMC releases. |
++------------------------+----------------------------------------------------+
+
++------------------------+----------------------------------------------------+
+| ID | 09 |
++========================+====================================================+
+| ``Threat`` | **Probing the FF-A communication between |
+| | endpoints.** |
+| | SPMC and SPs are typically loaded to external |
+| | memory (protected by a TrustZone memory |
+| | controller). A malicious agent may use non invasive|
+| | methods to probe the external memory bus and |
+| | extract the traffic between an SP and the SPMC or |
+| | among SPs when shared buffers are held in external |
+| | memory. |
++------------------------+----------------------------------------------------+
+| ``Diagram Elements`` | DF7 |
++------------------------+----------------------------------------------------+
+| ``Affected TF-A | SPMC |
+| Components`` | |
++------------------------+----------------------------------------------------+
+| ``Assets`` | SP/SPMC state, SP/SPMC secrets |
++------------------------+----------------------------------------------------+
+| ``Threat Agent`` | Hardware attack |
++------------------------+----------------------------------------------------+
+| ``Threat Type`` | Information disclosure |
++------------------------+------------------+-----------------+---------------+
+| ``Application`` | ``Server`` | ``Mobile`` | |
++------------------------+------------------+-----------------+---------------+
+| ``Impact`` | Medium (3) | Medium (3) | |
++------------------------+------------------+-----------------+---------------+
+| ``Likelihood`` | Low (2) | Medium (3) | |
++------------------------+------------------+-----------------+---------------+
+| ``Total Risk Rating`` | Medium (6) | Medium (9) | |
++------------------------+------------------+-----------------+---------------+
+| ``Mitigations`` | It is expected the platform or chipset provides |
+| | guarantees in protecting the DRAM contents. |
+| | The TF-A SPMC does not mitigate this class of |
+| | attack and this is left to the integrator. |
++------------------------+----------------------------------------------------+
+
++------------------------+----------------------------------------------------+
+| ID | 10 |
++========================+====================================================+
+| ``Threat`` | **A malicious agent may attempt revealing the SPMC |
+| | state or secrets by the use of software-based cache|
+| | side-channel attack techniques.** |
++------------------------+----------------------------------------------------+
+| ``Diagram Elements`` | DF7 |
++------------------------+----------------------------------------------------+
+| ``Affected TF-A | SPMC |
+| Components`` | |
++------------------------+----------------------------------------------------+
+| ``Assets`` | SP or SPMC state |
++------------------------+----------------------------------------------------+
+| ``Threat Agent`` | NS-Endpoint, S-Endpoint |
++------------------------+----------------------------------------------------+
+| ``Threat Type`` | Information disclosure |
++------------------------+------------------+-----------------+---------------+
+| ``Application`` | ``Server`` | ``Mobile`` | |
++------------------------+------------------+-----------------+---------------+
+| ``Impact`` | Medium (3) | Medium (3) | |
++------------------------+------------------+-----------------+---------------+
+| ``Likelihood`` | Low (2) | Low (2) | |
++------------------------+------------------+-----------------+---------------+
+| ``Total Risk Rating`` | Medium (6) | Medium (6) | |
++------------------------+------------------+-----------------+---------------+
+| ``Mitigations`` | From an integration perspective it is assumed |
+| | platforms consuming the SPMC component at S-EL2 |
+| | (hence implementing the Armv8.4 FEAT_SEL2 |
+| | architecture extension) implement mitigations to |
+| | Spectre, Meltdown or other cache timing |
+| | side-channel type of attacks. |
+| | The TF-A SPMC implements one mitigation (barrier |
+| | preventing speculation past exeception returns). |
+| | The SPMC may be hardened further with SW |
+| | mitigations (e.g. speculation barriers) for the |
+| | cases not covered in HW. Usage of hardened |
+| | compilers and appropriate options, code inspection |
+| | are recommended ways to mitigate Spectre types of |
+| | attacks. For non-hardened cores, the usage of |
+| | techniques such a kernel page table isolation can |
+| | help mitigating Meltdown type of attacks. |
++------------------------+----------------------------------------------------+
+
++------------------------+----------------------------------------------------+
+| ID | 11 |
++========================+====================================================+
+| ``Threat`` | **A malicious endpoint may attempt flooding the |
+| | SPMC with requests targetting a service within an |
+| | endpoint such that it denies another endpoint to |
+| | access this service.** |
+| | Similarly, the malicious endpoint may target a |
+| | a service within an endpoint such that the latter |
+| | is unable to request services from another |
+| | endpoint. |
++------------------------+----------------------------------------------------+
+| ``Diagram Elements`` | DF1, DF2, DF3, DF4 |
++------------------------+----------------------------------------------------+
+| ``Affected TF-A | SPMC |
+| Components`` | |
++------------------------+----------------------------------------------------+
+| ``Assets`` | SPMC state |
++------------------------+----------------------------------------------------+
+| ``Threat Agent`` | NS-Endpoint, S-Endpoint |
++------------------------+----------------------------------------------------+
+| ``Threat Type`` | Denial of service |
++------------------------+------------------+-----------------+---------------+
+| ``Application`` | ``Server`` | ``Mobile`` | |
++------------------------+------------------+-----------------+---------------+
+| ``Impact`` | Medium (3) | Medium (3) | |
++------------------------+------------------+-----------------+---------------+
+| ``Likelihood`` | Medium (3) | Medium (3) | |
++------------------------+------------------+-----------------+---------------+
+| ``Total Risk Rating`` | Medium (9) | Medium (9) | |
++------------------------+------------------+-----------------+---------------+
+| ``Mitigations`` | The TF-A SPMC does not mitigate this threat. |
+| | Bounding the time for operations to complete can |
+| | be achieved by the usage of a trusted watchdog. |
+| | Other quality of service monitoring can be achieved|
+| | in the SPMC such as counting a number of operations|
+| | in a limited timeframe. |
++------------------------+----------------------------------------------------+
+
+--------------
+
+*Copyright (c) 2021, Arm Limited. All rights reserved.*
+
+.. _Arm Firmware Framework for Armv8-A: https://developer.arm.com/docs/den0077/latest
+.. _Secure Partition Manager: ../components/secure-partition-manager.html
+.. _Generic TF-A threat model: ./threat_model.html#threat-analysis
+.. _FF-A ACS: https://github.com/ARM-software/ff-a-acs/releases
diff --git a/drivers/allwinner/axp/common.c b/drivers/allwinner/axp/common.c
index e98b16f..143fb0f 100644
--- a/drivers/allwinner/axp/common.c
+++ b/drivers/allwinner/axp/common.c
@@ -96,12 +96,27 @@
return 0;
}
+static bool is_node_disabled(const void *fdt, int node)
+{
+ const char *cell;
+ cell = fdt_getprop(fdt, node, "status", NULL);
+ if (cell == NULL) {
+ return false;
+ }
+ return strcmp(cell, "okay") != 0;
+}
+
static bool should_enable_regulator(const void *fdt, int node)
{
- if (fdt_getprop(fdt, node, "phandle", NULL) != NULL)
+ if (is_node_disabled(fdt, node)) {
+ return false;
+ }
+ if (fdt_getprop(fdt, node, "phandle", NULL) != NULL) {
return true;
- if (fdt_getprop(fdt, node, "regulator-always-on", NULL) != NULL)
+ }
+ if (fdt_getprop(fdt, node, "regulator-always-on", NULL) != NULL) {
return true;
+ }
return false;
}
diff --git a/drivers/arm/css/scmi/scmi_common.c b/drivers/arm/css/scmi/scmi_common.c
index 5b3724a..ec749fb 100644
--- a/drivers/arm/css/scmi/scmi_common.c
+++ b/drivers/arm/css/scmi/scmi_common.c
@@ -173,12 +173,12 @@
ret = scmi_proto_version(ch, SCMI_PWR_DMN_PROTO_ID, &version);
if (ret != SCMI_E_SUCCESS) {
- WARN("SCMI power domain protocol version message failed");
+ WARN("SCMI power domain protocol version message failed\n");
goto error;
}
if (!is_scmi_version_compatible(SCMI_PWR_DMN_PROTO_VER, version)) {
- WARN("SCMI power domain protocol version 0x%x incompatible with driver version 0x%x",
+ WARN("SCMI power domain protocol version 0x%x incompatible with driver version 0x%x\n",
version, SCMI_PWR_DMN_PROTO_VER);
goto error;
}
@@ -187,12 +187,12 @@
ret = scmi_proto_version(ch, SCMI_SYS_PWR_PROTO_ID, &version);
if ((ret != SCMI_E_SUCCESS)) {
- WARN("SCMI system power protocol version message failed");
+ WARN("SCMI system power protocol version message failed\n");
goto error;
}
if (!is_scmi_version_compatible(SCMI_SYS_PWR_PROTO_VER, version)) {
- WARN("SCMI system power management protocol version 0x%x incompatible with driver version 0x%x",
+ WARN("SCMI system power management protocol version 0x%x incompatible with driver version 0x%x\n",
version, SCMI_SYS_PWR_PROTO_VER);
goto error;
}
diff --git a/drivers/arm/dcc/dcc_console.c b/drivers/arm/dcc/dcc_console.c
new file mode 100644
index 0000000..0b7e541
--- /dev/null
+++ b/drivers/arm/dcc/dcc_console.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2015-2021, Xilinx Inc.
+ * Written by Michal Simek.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <errno.h>
+#include <stddef.h>
+#include <arch_helpers.h>
+#include <drivers/arm/dcc.h>
+#include <drivers/console.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+/* DCC Status Bits */
+#define DCC_STATUS_RX BIT(30)
+#define DCC_STATUS_TX BIT(29)
+#define TIMEOUT_COUNT_US U(0x10624)
+
+struct dcc_console {
+ struct console console;
+};
+
+static inline uint32_t __dcc_getstatus(void)
+{
+ return read_mdccsr_el0();
+}
+
+static inline char __dcc_getchar(void)
+{
+ char c;
+
+ c = read_dbgdtrrx_el0();
+
+ return c;
+}
+
+static inline void __dcc_putchar(char c)
+{
+ /*
+ * The typecast is to make absolutely certain that 'c' is
+ * zero-extended.
+ */
+ write_dbgdtrtx_el0((unsigned char)c);
+}
+
+static int32_t dcc_status_timeout(uint32_t mask)
+{
+ const unsigned int timeout_count = TIMEOUT_COUNT_US;
+ uint64_t timeout;
+ unsigned int status;
+
+ timeout = timeout_init_us(timeout_count);
+
+ do {
+ status = (__dcc_getstatus() & mask);
+ if (timeout_elapsed(timeout)) {
+ return -ETIMEDOUT;
+ }
+ } while ((status != 0U));
+
+ return 0;
+}
+
+static int32_t dcc_console_putc(int32_t ch, struct console *console)
+{
+ unsigned int status;
+
+ status = dcc_status_timeout(DCC_STATUS_TX);
+ if (status != 0U) {
+ return status;
+ }
+ __dcc_putchar(ch);
+
+ return ch;
+}
+
+static int32_t dcc_console_getc(struct console *console)
+{
+ unsigned int status;
+
+ status = dcc_status_timeout(DCC_STATUS_RX);
+ if (status != 0U) {
+ return status;
+ }
+
+ return __dcc_getchar();
+}
+
+int32_t dcc_console_init(unsigned long base_addr, uint32_t uart_clk,
+ uint32_t baud_rate)
+{
+ return 0; /* No init needed */
+}
+
+/**
+ * dcc_console_flush() - Function to force a write of all buffered data
+ * that hasn't been output.
+ * @console Console struct
+ *
+ */
+static void dcc_console_flush(struct console *console)
+{
+ unsigned int status;
+
+ status = dcc_status_timeout(DCC_STATUS_TX);
+ if (status != 0U) {
+ return;
+ }
+}
+
+static struct dcc_console dcc_console = {
+ .console = {
+ .flags = CONSOLE_FLAG_BOOT |
+ CONSOLE_FLAG_RUNTIME,
+ .putc = dcc_console_putc,
+ .getc = dcc_console_getc,
+ .flush = dcc_console_flush,
+ },
+};
+
+int console_dcc_register(void)
+{
+ return console_register(&dcc_console.console);
+}
diff --git a/drivers/arm/ethosn/ethosn_smc.c b/drivers/arm/ethosn/ethosn_smc.c
new file mode 100644
index 0000000..299d07c
--- /dev/null
+++ b/drivers/arm/ethosn/ethosn_smc.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include <common/debug.h>
+#include <common/runtime_svc.h>
+#include <drivers/arm/ethosn.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <plat/arm/common/fconf_ethosn_getter.h>
+
+/* Arm Ethos-N NPU (NPU) status */
+#define ETHOSN_STATUS \
+ FCONF_GET_PROPERTY(hw_config, ethosn_config, status)
+
+/* Number of NPU cores available */
+#define ETHOSN_NUM_CORES \
+ FCONF_GET_PROPERTY(hw_config, ethosn_config, num_cores)
+
+/* Address to an NPU core */
+#define ETHOSN_CORE_ADDR(core_idx) \
+ FCONF_GET_PROPERTY(hw_config, ethosn_core_addr, core_idx)
+
+/* NPU core sec registry address */
+#define ETHOSN_CORE_SEC_REG(core_addr, reg_offset) \
+ (core_addr + reg_offset)
+
+/* Reset timeout in us */
+#define ETHOSN_RESET_TIMEOUT_US U(10 * 1000 * 1000)
+#define ETHOSN_RESET_WAIT_US U(1)
+
+#define SEC_DEL_REG U(0x0004)
+#define SEC_DEL_VAL U(0x81C)
+#define SEC_DEL_EXCC_MASK U(0x20)
+
+#define SEC_SECCTLR_REG U(0x0010)
+#define SEC_SECCTLR_VAL U(0x3)
+
+#define SEC_DEL_MMUSID_REG U(0x2008)
+#define SEC_DEL_MMUSID_VAL U(0x3FFFF)
+
+#define SEC_DEL_ADDR_EXT_REG U(0x201C)
+#define SEC_DEL_ADDR_EXT_VAL U(0x15)
+
+#define SEC_SYSCTRL0_REG U(0x0018)
+#define SEC_SYSCTRL0_SOFT_RESET U(3U << 29)
+#define SEC_SYSCTRL0_HARD_RESET U(1U << 31)
+
+static void ethosn_delegate_to_ns(uintptr_t core_addr)
+{
+ mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_SECCTLR_REG),
+ SEC_SECCTLR_VAL);
+
+ mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_DEL_REG),
+ SEC_DEL_VAL);
+
+ mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_DEL_MMUSID_REG),
+ SEC_DEL_MMUSID_VAL);
+
+ mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_DEL_ADDR_EXT_REG),
+ SEC_DEL_ADDR_EXT_VAL);
+}
+
+static int ethosn_is_sec(void)
+{
+ if ((mmio_read_32(ETHOSN_CORE_SEC_REG(ETHOSN_CORE_ADDR(0), SEC_DEL_REG))
+ & SEC_DEL_EXCC_MASK) != 0U) {
+ return 0;
+ }
+
+ return 1;
+}
+
+static bool ethosn_reset(uintptr_t core_addr, int hard_reset)
+{
+ unsigned int timeout;
+ const uintptr_t sysctrl0_reg =
+ ETHOSN_CORE_SEC_REG(core_addr, SEC_SYSCTRL0_REG);
+ const uint32_t reset_val = (hard_reset != 0) ? SEC_SYSCTRL0_HARD_RESET
+ : SEC_SYSCTRL0_SOFT_RESET;
+
+ mmio_write_32(sysctrl0_reg, reset_val);
+
+ /* Wait for reset to complete */
+ for (timeout = 0U; timeout < ETHOSN_RESET_TIMEOUT_US;
+ timeout += ETHOSN_RESET_WAIT_US) {
+
+ if ((mmio_read_32(sysctrl0_reg) & reset_val) == 0U) {
+ break;
+ }
+
+ udelay(ETHOSN_RESET_WAIT_US);
+ }
+
+ return timeout < ETHOSN_RESET_TIMEOUT_US;
+}
+
+uintptr_t ethosn_smc_handler(uint32_t smc_fid,
+ u_register_t core_idx,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *cookie,
+ void *handle,
+ u_register_t flags)
+{
+ uintptr_t core_addr;
+ int hard_reset = 0;
+
+ /* Only SiP fast calls are expected */
+ if ((GET_SMC_TYPE(smc_fid) != SMC_TYPE_FAST) ||
+ (GET_SMC_OEN(smc_fid) != OEN_SIP_START)) {
+ SMC_RET1(handle, SMC_UNK);
+ }
+
+ /* Truncate parameters to 32-bits for SMC32 */
+ if (GET_SMC_CC(smc_fid) == SMC_32) {
+ core_idx &= 0xFFFFFFFF;
+ x2 &= 0xFFFFFFFF;
+ x3 &= 0xFFFFFFFF;
+ x4 &= 0xFFFFFFFF;
+ }
+
+ if (!is_ethosn_fid(smc_fid)) {
+ SMC_RET1(handle, SMC_UNK);
+ }
+
+ if (ETHOSN_STATUS == ETHOSN_STATUS_DISABLED) {
+ WARN("ETHOSN: Arm Ethos-N NPU not available\n");
+ SMC_RET1(handle, ETHOSN_NOT_SUPPORTED);
+ }
+
+ switch (smc_fid & FUNCID_NUM_MASK) {
+ case ETHOSN_FNUM_VERSION:
+ SMC_RET2(handle, ETHOSN_VERSION_MAJOR, ETHOSN_VERSION_MINOR);
+ case ETHOSN_FNUM_IS_SEC:
+ SMC_RET1(handle, ethosn_is_sec());
+ case ETHOSN_FNUM_HARD_RESET:
+ hard_reset = 1;
+ /* Fallthrough */
+ case ETHOSN_FNUM_SOFT_RESET:
+ if (core_idx >= ETHOSN_NUM_CORES) {
+ WARN("ETHOSN: core index out of range\n");
+ SMC_RET1(handle, ETHOSN_CORE_IDX_OUT_OF_RANGE);
+ }
+
+ core_addr = ETHOSN_CORE_ADDR(core_idx);
+
+ if (!ethosn_reset(core_addr, hard_reset)) {
+ SMC_RET1(handle, ETHOSN_FAILURE);
+ }
+
+ ethosn_delegate_to_ns(core_addr);
+
+ SMC_RET1(handle, ETHOSN_SUCCESS);
+ default:
+ SMC_RET1(handle, SMC_UNK);
+ }
+}
diff --git a/drivers/arm/gic/v3/gicv3_helpers.c b/drivers/arm/gic/v3/gicv3_helpers.c
index ff346f9..a0f44e9 100644
--- a/drivers/arm/gic/v3/gicv3_helpers.c
+++ b/drivers/arm/gic/v3/gicv3_helpers.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -92,6 +92,47 @@
}
/*******************************************************************************
+ * Helper function to get the maximum SPI INTID + 1.
+ ******************************************************************************/
+unsigned int gicv3_get_spi_limit(uintptr_t gicd_base)
+{
+ unsigned int spi_limit;
+ unsigned int typer_reg = gicd_read_typer(gicd_base);
+
+ /* (maximum SPI INTID + 1) is equal to 32 * (GICD_TYPER.ITLinesNumber+1) */
+ spi_limit = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5;
+
+ /* Filter out special INTIDs 1020-1023 */
+ if (spi_limit > (MAX_SPI_ID + 1U)) {
+ return MAX_SPI_ID + 1U;
+ }
+
+ return spi_limit;
+}
+
+#if GIC_EXT_INTID
+/*******************************************************************************
+ * Helper function to get the maximum ESPI INTID + 1.
+ ******************************************************************************/
+unsigned int gicv3_get_espi_limit(uintptr_t gicd_base)
+{
+ unsigned int typer_reg = gicd_read_typer(gicd_base);
+
+ /* Check if extended SPI range is implemented */
+ if ((typer_reg & TYPER_ESPI) != 0U) {
+ /*
+ * (maximum ESPI INTID + 1) is equal to
+ * 32 * (GICD_TYPER.ESPI_range + 1) + 4096
+ */
+ return ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
+ TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID;
+ }
+
+ return 0U;
+}
+#endif /* GIC_EXT_INTID */
+
+/*******************************************************************************
* Helper function to configure the default attributes of (E)SPIs.
******************************************************************************/
void gicv3_spis_config_defaults(uintptr_t gicd_base)
@@ -100,10 +141,9 @@
#if GIC_EXT_INTID
unsigned int num_eints;
#endif
- unsigned int typer_reg = gicd_read_typer(gicd_base);
- /* Maximum SPI INTID is 32 * (GICD_TYPER.ITLinesNumber + 1) - 1 */
- num_ints = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5;
+ num_ints = gicv3_get_spi_limit(gicd_base);
+ INFO("Maximum SPI INTID supported: %u\n", num_ints - 1);
/* Treat all (E)SPIs as G1NS by default. We do 32 at a time. */
for (i = MIN_SPI_ID; i < num_ints; i += (1U << IGROUPR_SHIFT)) {
@@ -111,20 +151,16 @@
}
#if GIC_EXT_INTID
- /* Check if extended SPI range is implemented */
- if ((typer_reg & TYPER_ESPI) != 0U) {
- /*
- * Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095
- */
- num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
- TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID - 1;
+ num_eints = gicv3_get_espi_limit(gicd_base);
+ if (num_eints != 0U) {
+ INFO("Maximum ESPI INTID supported: %u\n", num_eints - 1);
for (i = MIN_ESPI_ID; i < num_eints;
i += (1U << IGROUPR_SHIFT)) {
gicd_write_igroupr(gicd_base, i, ~0U);
}
} else {
- num_eints = 0U;
+ INFO("ESPI range is not implemented.\n");
}
#endif
diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c
index 22efd45..b1139b5 100644
--- a/drivers/arm/gic/v3/gicv3_main.c
+++ b/drivers/arm/gic/v3/gicv3_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -70,7 +70,8 @@
for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\
int_id += (1U << REG##R_SHIFT)) { \
gicd_write_##reg((base), int_id, \
- (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - MIN_SPI_ID))\
+ (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \
+ round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\
>> REG##R_SHIFT]); \
} \
} while (false)
@@ -79,7 +80,8 @@
do { \
for (unsigned int int_id = MIN_ESPI_ID; int_id < (intr_num);\
int_id += (1U << REG##R_SHIFT)) { \
- (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - MIN_SPI_ID))\
+ (ctx)->gicd_##reg[(int_id - (MIN_ESPI_ID - \
+ round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\
>> REG##R_SHIFT] = gicd_read_##reg((base), int_id);\
} \
} while (false)
@@ -330,6 +332,8 @@
write_icc_igrpen1_el3(read_icc_igrpen1_el3() |
IGRPEN1_EL3_ENABLE_G1S_BIT);
isb();
+ /* Add DSB to ensure visibility of System register writes */
+ dsb();
}
/*******************************************************************************
@@ -361,6 +365,8 @@
/* Synchronise accesses to group enable registers */
isb();
+ /* Add DSB to ensure visibility of System register writes */
+ dsb();
/* Mark the connected core as asleep */
gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
@@ -726,40 +732,17 @@
*****************************************************************************/
void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx)
{
- unsigned int typer_reg, num_ints;
-#if GIC_EXT_INTID
- unsigned int num_eints;
-#endif
-
assert(gicv3_driver_data != NULL);
assert(gicv3_driver_data->gicd_base != 0U);
assert(IS_IN_EL3());
assert(dist_ctx != NULL);
uintptr_t gicd_base = gicv3_driver_data->gicd_base;
-
- typer_reg = gicd_read_typer(gicd_base);
-
- /* Maximum SPI INTID is 32 * (GICD_TYPER.ITLinesNumber + 1) - 1 */
- num_ints = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5;
-
- /* Filter out special INTIDs 1020-1023 */
- if (num_ints > (MAX_SPI_ID + 1U)) {
- num_ints = MAX_SPI_ID + 1U;
- }
-
+ unsigned int num_ints = gicv3_get_spi_limit(gicd_base);
#if GIC_EXT_INTID
- /* Check if extended SPI range is implemented */
- if ((typer_reg & TYPER_ESPI) != 0U) {
- /*
- * Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095
- */
- num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
- TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID - 1;
- } else {
- num_eints = 0U;
- }
+ unsigned int num_eints = gicv3_get_espi_limit(gicd_base);
#endif
+
/* Wait for pending write to complete */
gicd_wait_for_pending_write(gicd_base);
@@ -836,11 +819,6 @@
*****************************************************************************/
void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx)
{
- unsigned int typer_reg, num_ints;
-#if GIC_EXT_INTID
- unsigned int num_eints;
-#endif
-
assert(gicv3_driver_data != NULL);
assert(gicv3_driver_data->gicd_base != 0U);
assert(IS_IN_EL3());
@@ -862,27 +840,9 @@
/* Set the ARE_S and ARE_NS bit now that interrupts have been disabled */
gicd_set_ctlr(gicd_base, CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE);
- typer_reg = gicd_read_typer(gicd_base);
-
- /* Maximum SPI INTID is 32 * (GICD_TYPER.ITLinesNumber + 1) - 1 */
- num_ints = ((typer_reg & TYPER_IT_LINES_NO_MASK) + 1U) << 5;
-
- /* Filter out special INTIDs 1020-1023 */
- if (num_ints > (MAX_SPI_ID + 1U)) {
- num_ints = MAX_SPI_ID + 1U;
- }
-
+ unsigned int num_ints = gicv3_get_spi_limit(gicd_base);
#if GIC_EXT_INTID
- /* Check if extended SPI range is implemented */
- if ((typer_reg & TYPER_ESPI) != 0U) {
- /*
- * Maximum ESPI INTID is 32 * (GICD_TYPER.ESPI_range + 1) + 4095
- */
- num_eints = ((((typer_reg >> TYPER_ESPI_RANGE_SHIFT) &
- TYPER_ESPI_RANGE_MASK) + 1U) << 5) + MIN_ESPI_ID - 1;
- } else {
- num_eints = 0U;
- }
+ unsigned int num_eints = gicv3_get_espi_limit(gicd_base);
#endif
/* Restore GICD_IGROUPR for INTIDs 32 - 1019 */
RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUP);
@@ -1299,8 +1259,8 @@
******************************************************************************/
int gicv3_rdistif_probe(const uintptr_t gicr_frame)
{
- u_register_t mpidr;
- unsigned int proc_num, proc_self;
+ u_register_t mpidr, mpidr_self;
+ unsigned int proc_num;
uint64_t typer_val;
uintptr_t rdistif_base;
bool gicr_frame_found = false;
@@ -1314,18 +1274,18 @@
assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U);
#endif /* !__aarch64__ */
- proc_self = gicv3_driver_data->mpidr_to_core_pos(read_mpidr_el1());
+ mpidr_self = read_mpidr_el1() & MPIDR_AFFINITY_MASK;
rdistif_base = gicr_frame;
do {
typer_val = gicr_read_typer(rdistif_base);
+ mpidr = mpidr_from_gicr_typer(typer_val);
if (gicv3_driver_data->mpidr_to_core_pos != NULL) {
- mpidr = mpidr_from_gicr_typer(typer_val);
proc_num = gicv3_driver_data->mpidr_to_core_pos(mpidr);
} else {
proc_num = (unsigned int)(typer_val >>
TYPER_PROC_NUM_SHIFT) & TYPER_PROC_NUM_MASK;
}
- if (proc_num == proc_self) {
+ if (mpidr == mpidr_self) {
/* The base address doesn't need to be initialized on
* every warm boot.
*/
diff --git a/drivers/arm/gic/v3/gicv3_private.h b/drivers/arm/gic/v3/gicv3_private.h
index c5d027d..93ee1a1 100644
--- a/drivers/arm/gic/v3/gicv3_private.h
+++ b/drivers/arm/gic/v3/gicv3_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -48,7 +48,8 @@
#define GICD_OFFSET_64(REG, id) \
(((id) <= MAX_SPI_ID) ? \
GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3) : \
- GICD_##REG##RE + (((uintptr_t)(id) - MIN_ESPI_ID) << 3))
+ GICD_##REG##RE + ((((uintptr_t)(id) - MIN_ESPI_ID) >> \
+ REG##R_SHIFT) << 3))
#else /* GICv3 */
#define GICD_OFFSET_8(REG, id) \
@@ -232,6 +233,8 @@
/*******************************************************************************
* Private GICv3 helper function prototypes
******************************************************************************/
+unsigned int gicv3_get_spi_limit(uintptr_t gicd_base);
+unsigned int gicv3_get_espi_limit(uintptr_t gicd_base);
void gicv3_spis_config_defaults(uintptr_t gicd_base);
void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base);
unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
diff --git a/drivers/arm/tzc/tzc400.c b/drivers/arm/tzc/tzc400.c
index 95a5e7f..9fc1578 100644
--- a/drivers/arm/tzc/tzc400.c
+++ b/drivers/arm/tzc/tzc400.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,6 +10,7 @@
#include <common/debug.h>
#include <drivers/arm/tzc400.h>
#include <lib/mmio.h>
+#include <lib/utils_def.h>
#include "tzc_common_private.h"
@@ -70,6 +71,77 @@
DEFINE_TZC_COMMON_CONFIGURE_REGION0(400)
DEFINE_TZC_COMMON_CONFIGURE_REGION(400)
+static void _tzc400_clear_it(uintptr_t base, uint32_t filter)
+{
+ mmio_write_32(base + INT_CLEAR, BIT_32(filter));
+}
+
+static uint32_t _tzc400_get_int_by_filter(uintptr_t base, uint32_t filter)
+{
+ return mmio_read_32(base + INT_STATUS) & BIT_32(filter);
+}
+
+#if DEBUG
+static unsigned long _tzc400_get_fail_address(uintptr_t base, uint32_t filter)
+{
+ unsigned long fail_address;
+
+ fail_address = mmio_read_32(base + FAIL_ADDRESS_LOW_OFF +
+ (filter * FILTER_OFFSET));
+#ifdef __aarch64__
+ fail_address += (unsigned long)mmio_read_32(base + FAIL_ADDRESS_HIGH_OFF +
+ (filter * FILTER_OFFSET)) << 32;
+#endif
+
+ return fail_address;
+}
+
+static uint32_t _tzc400_get_fail_id(uintptr_t base, uint32_t filter)
+{
+ return mmio_read_32(base + FAIL_ID + (filter * FILTER_OFFSET));
+}
+
+static uint32_t _tzc400_get_fail_control(uintptr_t base, uint32_t filter)
+{
+ return mmio_read_32(base + FAIL_CONTROL_OFF + (filter * FILTER_OFFSET));
+}
+
+static void _tzc400_dump_fail_filter(uintptr_t base, uint32_t filter)
+{
+ uint32_t control_fail;
+ uint32_t fail_id;
+ unsigned long address_fail;
+
+ address_fail = _tzc400_get_fail_address(base, filter);
+ ERROR("Illegal access to 0x%lx:\n", address_fail);
+
+ fail_id = _tzc400_get_fail_id(base, filter);
+ ERROR("\tFAIL_ID = 0x%x\n", fail_id);
+
+ control_fail = _tzc400_get_fail_control(base, filter);
+ if (((control_fail & BIT_32(FAIL_CONTROL_NS_SHIFT)) >> FAIL_CONTROL_NS_SHIFT) ==
+ FAIL_CONTROL_NS_NONSECURE) {
+ ERROR("\tNon-Secure\n");
+ } else {
+ ERROR("\tSecure\n");
+ }
+
+ if (((control_fail & BIT_32(FAIL_CONTROL_PRIV_SHIFT)) >> FAIL_CONTROL_PRIV_SHIFT) ==
+ FAIL_CONTROL_PRIV_PRIV) {
+ ERROR("\tPrivilege\n");
+ } else {
+ ERROR("\tUnprivilege\n");
+ }
+
+ if (((control_fail & BIT_32(FAIL_CONTROL_DIR_SHIFT)) >> FAIL_CONTROL_DIR_SHIFT) ==
+ FAIL_CONTROL_DIR_WRITE) {
+ ERROR("\tWrite\n");
+ } else {
+ ERROR("\tRead\n");
+ }
+}
+#endif /* DEBUG */
+
static unsigned int _tzc400_get_gate_keeper(uintptr_t base,
unsigned int filter)
{
@@ -108,11 +180,6 @@
assert(tzc400.base != 0U);
assert(action <= TZC_ACTION_ERR_INT);
- /*
- * - Currently no handler is provided to trap an error via interrupt
- * or exception.
- * - The interrupt action has not been tested.
- */
_tzc400_write_action(tzc400.base, action);
}
@@ -162,7 +229,9 @@
/*
* `tzc400_configure_region` is used to program regions into the TrustZone
* controller. A region can be associated with more than one filter. The
- * associated filters are passed in as a bitmap (bit0 = filter0).
+ * associated filters are passed in as a bitmap (bit0 = filter0), except that
+ * the value TZC_400_REGION_ATTR_FILTER_BIT_ALL selects all filters, based on
+ * the value of tzc400.num_filters.
* NOTE:
* Region 0 is special; it is preferable to use tzc400_configure_region0
* for this region (see comment for that function).
@@ -176,6 +245,11 @@
{
assert(tzc400.base != 0U);
+ /* Adjust filter mask by real filter number */
+ if (filters == TZC_400_REGION_ATTR_FILTER_BIT_ALL) {
+ filters = (1U << tzc400.num_filters) - 1U;
+ }
+
/* Do range checks on filters and regions. */
assert(((filters >> tzc400.num_filters) == 0U) &&
(region < tzc400.num_regions));
@@ -238,3 +312,31 @@
for (filter = 0; filter < tzc400.num_filters; filter++)
_tzc400_set_gate_keeper(tzc400.base, filter, 0);
}
+
+int tzc400_it_handler(void)
+{
+ uint32_t filter;
+ uint32_t filter_it_pending = tzc400.num_filters;
+
+ assert(tzc400.base != 0U);
+
+ for (filter = 0U; filter < tzc400.num_filters; filter++) {
+ if (_tzc400_get_int_by_filter(tzc400.base, filter) != 0U) {
+ filter_it_pending = filter;
+ break;
+ }
+ }
+
+ if (filter_it_pending == tzc400.num_filters) {
+ ERROR("TZC-400: No interrupt pending!\n");
+ return -1;
+ }
+
+#if DEBUG
+ _tzc400_dump_fail_filter(tzc400.base, filter_it_pending);
+#endif
+
+ _tzc400_clear_it(tzc400.base, filter_it_pending);
+
+ return 0;
+}
diff --git a/drivers/auth/auth_mod.c b/drivers/auth/auth_mod.c
index 91ee1be..917ee4a 100644
--- a/drivers/auth/auth_mod.c
+++ b/drivers/auth/auth_mod.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,6 +16,7 @@
#include <drivers/auth/auth_mod.h>
#include <drivers/auth/crypto_mod.h>
#include <drivers/auth/img_parser_mod.h>
+#include <drivers/fwu/fwu.h>
#include <lib/fconf/fconf_tbbr_getter.h>
#include <plat/common/platform.h>
@@ -222,20 +223,27 @@
* To protect the system against rollback, the platform includes a non-volatile
* counter whose value can only be increased. All certificates include a counter
* value that should not be lower than the value stored in the platform. If the
- * value is larger, the counter in the platform must be updated to the new
- * value.
+ * value is larger, the counter in the platform must be updated to the new value
+ * (provided it has been authenticated).
*
* Return: 0 = success, Otherwise = error
+ * Returns additionally,
+ * cert_nv_ctr -> NV counter value present in the certificate
+ * need_nv_ctr_upgrade = 0 -> platform NV counter upgrade is not needed
+ * need_nv_ctr_upgrade = 1 -> platform NV counter upgrade is needed
*/
static int auth_nvctr(const auth_method_param_nv_ctr_t *param,
const auth_img_desc_t *img_desc,
- void *img, unsigned int img_len)
+ void *img, unsigned int img_len,
+ unsigned int *cert_nv_ctr,
+ bool *need_nv_ctr_upgrade)
{
char *p;
void *data_ptr = NULL;
unsigned int data_len, len, i;
- unsigned int cert_nv_ctr, plat_nv_ctr;
+ unsigned int plat_nv_ctr;
int rc = 0;
+ bool is_trial_run = false;
/* Get the counter value from current image. The AM expects the IPM
* to return the counter value as a DER encoded integer */
@@ -265,22 +273,23 @@
}
/* Convert to unsigned int. This code is for a little-endian CPU */
- cert_nv_ctr = 0;
+ *cert_nv_ctr = 0;
for (i = 0; i < len; i++) {
- cert_nv_ctr = (cert_nv_ctr << 8) | *p++;
+ *cert_nv_ctr = (*cert_nv_ctr << 8) | *p++;
}
/* Get the counter from the platform */
rc = plat_get_nv_ctr(param->plat_nv_ctr->cookie, &plat_nv_ctr);
return_if_error(rc);
- if (cert_nv_ctr < plat_nv_ctr) {
+ if (*cert_nv_ctr < plat_nv_ctr) {
/* Invalid NV-counter */
return 1;
- } else if (cert_nv_ctr > plat_nv_ctr) {
- rc = plat_set_nv_ctr2(param->plat_nv_ctr->cookie,
- img_desc, cert_nv_ctr);
- return_if_error(rc);
+ } else if (*cert_nv_ctr > plat_nv_ctr) {
+#if PSA_FWU_SUPPORT && IMAGE_BL2
+ is_trial_run = fwu_is_trial_run_state();
+#endif /* PSA_FWU_SUPPORT && IMAGE_BL2 */
+ *need_nv_ctr_upgrade = !is_trial_run;
}
return 0;
@@ -351,6 +360,10 @@
void *param_ptr;
unsigned int param_len;
int rc, i;
+ unsigned int cert_nv_ctr = 0;
+ bool need_nv_ctr_upgrade = false;
+ bool sig_auth_done = false;
+ const auth_method_param_nv_ctr_t *nv_ctr_param = NULL;
/* Get the image descriptor from the chain of trust */
img_desc = FCONF_GET_PROPERTY(tbbr, cot, img_id);
@@ -376,10 +389,13 @@
case AUTH_METHOD_SIG:
rc = auth_signature(&auth_method->param.sig,
img_desc, img_ptr, img_len);
+ sig_auth_done = true;
break;
case AUTH_METHOD_NV_CTR:
- rc = auth_nvctr(&auth_method->param.nv_ctr,
- img_desc, img_ptr, img_len);
+ nv_ctr_param = &auth_method->param.nv_ctr;
+ rc = auth_nvctr(nv_ctr_param,
+ img_desc, img_ptr, img_len,
+ &cert_nv_ctr, &need_nv_ctr_upgrade);
break;
default:
/* Unknown authentication method */
@@ -389,6 +405,16 @@
return_if_error(rc);
}
+ /*
+ * Do platform NV counter upgrade only if the certificate gets
+ * authenticated, and platform NV-counter upgrade is needed.
+ */
+ if (need_nv_ctr_upgrade && sig_auth_done) {
+ rc = plat_set_nv_ctr2(nv_ctr_param->plat_nv_ctr->cookie,
+ img_desc, cert_nv_ctr);
+ return_if_error(rc);
+ }
+
/* Extract the parameters indicated in the image descriptor to
* authenticate the children images. */
if (img_desc->authenticated_data != NULL) {
diff --git a/drivers/brcm/i2c/i2c.c b/drivers/brcm/i2c/i2c.c
new file mode 100644
index 0000000..2096a82
--- /dev/null
+++ b/drivers/brcm/i2c/i2c.c
@@ -0,0 +1,886 @@
+/*
+ * Copyright (c) 2016 - 2021, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <i2c.h>
+#include <i2c_regs.h>
+#include <lib/mmio.h>
+
+#include <platform_def.h>
+
+/* Max instances */
+#define MAX_I2C 2U
+
+/* Transaction error codes defined in Master command register (0x30) */
+#define MSTR_STS_XACT_SUCCESS 0U
+#define MSTR_STS_LOST_ARB 1U
+#define MSTR_STS_NACK_FIRST_BYTE 2U
+ /* NACK on a byte other than the first byte */
+#define MSTR_STS_NACK_NON_FIRST_BYTE 3U
+
+#define MSTR_STS_TTIMEOUT_EXCEEDED 4U
+#define MSTR_STS_TX_TLOW_MEXT_EXCEEDED 5U
+#define MSTR_STS_RX_TLOW_MEXT_EXCEEDED 6U
+
+/* SMBUS protocol values defined in register 0x30 */
+#define SMBUS_PROT_QUICK_CMD 0U
+#define SMBUS_PROT_SEND_BYTE 1U
+#define SMBUS_PROT_RECV_BYTE 2U
+#define SMBUS_PROT_WR_BYTE 3U
+#define SMBUS_PROT_RD_BYTE 4U
+#define SMBUS_PROT_WR_WORD 5U
+#define SMBUS_PROT_RD_WORD 6U
+#define SMBUS_PROT_BLK_WR 7U
+#define SMBUS_PROT_BLK_RD 8U
+#define SMBUS_PROT_PROC_CALL 9U
+#define SMBUS_PROT_BLK_WR_BLK_RD_PROC_CALL 10U
+
+/* Number can be changed later */
+#define BUS_BUSY_COUNT 100000U
+
+#define IPROC_I2C_INVALID_ADDR 0xFFU
+
+#define I2C_SMBUS_BLOCK_MAX 32U
+
+/*
+ * Enum to specify clock speed. The user will provide it during initialization.
+ * If needed, it can be changed dynamically
+ */
+typedef enum iproc_smb_clk_freq {
+ IPROC_SMB_SPEED_100KHz = 0,
+ IPROC_SMB_SPEED_400KHz = 1,
+ IPROC_SMB_SPEED_INVALID = 255
+} smb_clk_freq_t;
+
+/* Structure used to pass information to read/write functions. */
+struct iproc_xact_info {
+ /* Bus Identifier */
+ uint32_t bus_id;
+ /* Device Address */
+ uint8_t devaddr;
+ /* Passed by caller to send SMBus command cod e*/
+ uint8_t command;
+ /* actual data passed by the caller */
+ uint8_t *data;
+ /* Size of data buffer passed */
+ uint32_t size;
+ /* Sent by caller specifying PEC, 10-bit addresses */
+ uint16_t flags;
+ /* SMBus protocol to use to perform transaction */
+ uint8_t smb_proto;
+ /* true if command field below is valid. Otherwise, false */
+ uint32_t cmd_valid;
+};
+
+static const uintptr_t smbus_base_reg_addr[MAX_I2C] = {
+ SMBUS0_REGS_BASE,
+ SMBUS1_REGS_BASE
+};
+
+/* Function to read a value from specified register. */
+static uint32_t iproc_i2c_reg_read(uint32_t bus_id, unsigned long reg_addr)
+{
+ uint32_t val;
+ uintptr_t smbus;
+
+ smbus = smbus_base_reg_addr[bus_id];
+
+ val = mmio_read_32(smbus + reg_addr);
+ VERBOSE("i2c %u: reg %p read 0x%x\n", bus_id,
+ (void *)(smbus + reg_addr), val);
+ return val;
+}
+
+/* Function to write a value ('val') in to a specified register. */
+static void iproc_i2c_reg_write(uint32_t bus_id,
+ unsigned long reg_addr,
+ uint32_t val)
+{
+ uintptr_t smbus;
+
+ smbus = smbus_base_reg_addr[bus_id];
+
+ mmio_write_32((smbus + reg_addr), val);
+ VERBOSE("i2c %u: reg %p wrote 0x%x\n", bus_id,
+ (void *)(smbus + reg_addr), val);
+}
+
+/* Function to clear and set bits in a specified register. */
+static void iproc_i2c_reg_clearset(uint32_t bus_id,
+ unsigned long reg_addr,
+ uint32_t clear,
+ uint32_t set)
+{
+ uintptr_t smbus;
+
+ smbus = smbus_base_reg_addr[bus_id];
+
+ mmio_clrsetbits_32((smbus + reg_addr), clear, set);
+ VERBOSE("i2c %u: reg %p clear 0x%x, set 0x%x\n", bus_id,
+ (void *)(smbus + reg_addr), clear, set);
+}
+
+/* Function to dump all SMBUS register */
+#ifdef BCM_I2C_DEBUG
+static int iproc_dump_i2c_regs(uint32_t bus_id)
+{
+ uint32_t regval;
+
+ if (bus_id > MAX_I2C) {
+ return -1;
+ }
+
+ INFO("----------------------------------------------\n");
+ INFO("%s: Dumping SMBus %u registers...\n", __func__, bus_id);
+
+ regval = iproc_i2c_reg_read(bus_id, SMB_CFG_REG);
+ INFO("SMB_CFG_REG=0x%x\n", regval);
+
+ regval = iproc_i2c_reg_read(bus_id, SMB_TIMGCFG_REG);
+ INFO("SMB_TIMGCFG_REG=0x%x\n", regval);
+
+ regval = iproc_i2c_reg_read(bus_id, SMB_ADDR_REG);
+ INFO("SMB_ADDR_REG=0x%x\n", regval);
+
+ regval = iproc_i2c_reg_read(bus_id, SMB_MSTRFIFOCTL_REG);
+ INFO("SMB_MSTRFIFOCTL_REG=0x%x\n", regval);
+
+ regval = iproc_i2c_reg_read(bus_id, SMB_SLVFIFOCTL_REG);
+ INFO("SMB_SLVFIFOCTL_REG=0x%x\n", regval);
+
+ regval = iproc_i2c_reg_read(bus_id, SMB_BITBANGCTL_REG);
+ INFO("SMB_BITBANGCTL_REG=0x%x\n", regval);
+
+ regval = iproc_i2c_reg_read(bus_id, SMB_MSTRCMD_REG);
+ INFO("SMB_MSTRCMD_REG=0x%x\n", regval);
+
+ regval = iproc_i2c_reg_read(bus_id, SMB_SLVCMD_REG);
+ INFO("SMB_SLVCMD_REG=0x%x\n", regval);
+
+ regval = iproc_i2c_reg_read(bus_id, SMB_EVTEN_REG);
+ INFO("SMB_EVTEN_REG=0x%x\n", regval);
+
+ regval = iproc_i2c_reg_read(bus_id, SMB_EVTSTS_REG);
+ INFO("SMB_EVTSTS_REG=0x%x\n", regval);
+
+ regval = iproc_i2c_reg_read(bus_id, SMB_MSTRDATAWR_REG);
+ INFO("SMB_MSTRDATAWR_REG=0x%x\n", regval);
+
+ regval = iproc_i2c_reg_read(bus_id, SMB_MSTRDATARD_REG);
+ INFO("SMB_MSTRDATARD_REG=0x%x\n", regval);
+
+ regval = iproc_i2c_reg_read(bus_id, SMB_SLVDATAWR_REG);
+ INFO("SMB_SLVDATAWR_REG=0x%x\n", regval);
+
+ regval = iproc_i2c_reg_read(bus_id, SMB_SLVDATARD_REG);
+ INFO("SMB_SLVDATARD_REG=0x%x\n", regval);
+
+ INFO("----------------------------------------------\n");
+ return 0;
+}
+#endif
+
+/*
+ * Function to ensure that the previous transaction was completed before
+ * initiating a new transaction. It can also be used in polling mode to
+ * check status of completion of a command
+ */
+static int iproc_i2c_startbusy_wait(uint32_t bus_id)
+{
+ uint32_t regval;
+ uint32_t retry = 0U;
+
+ /*
+ * Check if an operation is in progress. During probe it won't be.
+ * Want to make sure that the transaction in progress is completed.
+ */
+ do {
+ udelay(1U);
+ regval = iproc_i2c_reg_read(bus_id, SMB_MSTRCMD_REG);
+ regval &= SMB_MSTRSTARTBUSYCMD_MASK;
+ if (retry++ > BUS_BUSY_COUNT) {
+ ERROR("%s: START_BUSY bit didn't clear, exiting\n",
+ __func__);
+ return -1;
+ }
+
+ } while (regval != 0U);
+
+ return 0;
+}
+
+/*
+ * This function copies data to SMBus's Tx FIFO. Valid for write transactions
+ * info: Data to copy in to Tx FIFO. For read commands, the size should be
+ * set to zero by the caller
+ */
+static void iproc_i2c_write_trans_data(struct iproc_xact_info *info)
+{
+ uint32_t regval;
+ uint8_t devaddr;
+ uint32_t i;
+ uint32_t num_data_bytes = 0U;
+
+#ifdef BCM_I2C_DEBUG
+ INFO("%s:dev_addr=0x%x,cmd_valid=%d, cmd=0x%x, size=%u proto=%d\n",
+ __func__, info->devaddr, info->cmd_valid, info->command,
+ info->size, info->smb_proto);
+#endif
+ /* Shift devaddr by 1 bit since SMBus uses the low bit[0] for R/W_n */
+ devaddr = (info->devaddr << 1);
+
+ /*
+ * Depending on the SMBus protocol, we need to write additional
+ * transaction data in to Tx FIFO. Refer to section 5.5 of SMBus spec
+ * for sequence for a transaction
+ */
+ switch (info->smb_proto) {
+ case SMBUS_PROT_RECV_BYTE:
+ /* No additional data to be written */
+ iproc_i2c_reg_write(info->bus_id, SMB_MSTRDATAWR_REG,
+ devaddr | 0x1U | SMB_MSTRWRSTS_MASK);
+ break;
+ case SMBUS_PROT_SEND_BYTE:
+ num_data_bytes = info->size;
+ iproc_i2c_reg_write(info->bus_id, SMB_MSTRDATAWR_REG,
+ devaddr);
+ break;
+ case SMBUS_PROT_RD_BYTE:
+ case SMBUS_PROT_RD_WORD:
+ case SMBUS_PROT_BLK_RD:
+ /* Write slave address with R/W~ set (bit #0) */
+ iproc_i2c_reg_write(info->bus_id, SMB_MSTRDATAWR_REG,
+ devaddr | 0x1U);
+ break;
+ case SMBUS_PROT_BLK_WR_BLK_RD_PROC_CALL:
+ iproc_i2c_reg_write(info->bus_id, SMB_MSTRDATAWR_REG,
+ devaddr | 0x1U | SMB_MSTRWRSTS_MASK);
+ break;
+ case SMBUS_PROT_WR_BYTE:
+ case SMBUS_PROT_WR_WORD:
+ iproc_i2c_reg_write(info->bus_id, SMB_MSTRDATAWR_REG,
+ devaddr);
+ /*
+ * No additional bytes to be written. Data portion is written
+ * in the 'for' loop below
+ */
+ num_data_bytes = info->size;
+ break;
+ case SMBUS_PROT_BLK_WR:
+ iproc_i2c_reg_write(info->bus_id, SMB_MSTRDATAWR_REG,
+ devaddr);
+ /* 3rd byte is byte count */
+ iproc_i2c_reg_write(info->bus_id, SMB_MSTRDATAWR_REG,
+ info->size);
+ num_data_bytes = info->size;
+ break;
+ default:
+ return;
+ }
+
+ /* If the protocol needs command code, copy it */
+ if (info->cmd_valid) {
+ iproc_i2c_reg_write(info->bus_id, SMB_MSTRDATAWR_REG,
+ info->command);
+ }
+
+ /*
+ * Copy actual data from caller. In general, for reads,
+ * no data is copied.
+ */
+ for (i = 0U; num_data_bytes; --num_data_bytes, i++) {
+ /* For the last byte, set MASTER_WR_STATUS bit */
+ regval = (num_data_bytes == 1U) ?
+ info->data[i] | SMB_MSTRWRSTS_MASK : info->data[i];
+ iproc_i2c_reg_write(info->bus_id, SMB_MSTRDATAWR_REG,
+ regval);
+ }
+}
+
+/*
+ * This function writes to the master command register and
+ * then polls for completion
+ */
+static int iproc_i2c_write_master_command(uint32_t mastercmd,
+ struct iproc_xact_info *info)
+{
+ uint32_t retry = 0U;
+ uint32_t regval;
+
+ iproc_i2c_reg_write(info->bus_id, SMB_MSTRCMD_REG, mastercmd);
+
+ /* Check for Master Busy status */
+ regval = iproc_i2c_reg_read(info->bus_id, SMB_MSTRCMD_REG);
+ while ((regval & SMB_MSTRSTARTBUSYCMD_MASK) != 0U) {
+ udelay(1U);
+ if (retry++ > BUS_BUSY_COUNT) {
+ ERROR("%s: START_BUSY bit didn't clear, exiting\n",
+ __func__);
+ return -1;
+ }
+ regval = iproc_i2c_reg_read(info->bus_id, SMB_MSTRCMD_REG);
+ }
+
+ /* If start_busy bit cleared, check if there are any errors */
+ if (!(regval & SMB_MSTRSTARTBUSYCMD_MASK)) {
+ /* start_busy bit cleared, check master_status field now */
+ regval &= SMB_MSTRSTS_MASK;
+ regval >>= SMB_MSTRSTS_SHIFT;
+ if (regval != MSTR_STS_XACT_SUCCESS) {
+ /* Error We can flush Tx FIFO here */
+ ERROR("%s: ERROR: %u exiting\n", __func__, regval);
+ return -1;
+ }
+ }
+ return 0;
+
+}
+/* Function to initiate data send and verify completion status */
+static int iproc_i2c_data_send(struct iproc_xact_info *info)
+{
+ int rc;
+ uint32_t mastercmd;
+
+ /* Make sure the previous transaction completed */
+ rc = iproc_i2c_startbusy_wait(info->bus_id);
+
+ if (rc < 0) {
+ WARN("%s: Send: bus is busy, exiting\n", __func__);
+ return rc;
+ }
+ /* Write transaction bytes to Tx FIFO */
+ iproc_i2c_write_trans_data(info);
+
+ /*
+ * Program master command register (0x30) with protocol type and set
+ * start_busy_command bit to initiate the write transaction
+ */
+ mastercmd = (info->smb_proto << SMB_MSTRSMBUSPROTO_SHIFT) |
+ SMB_MSTRSTARTBUSYCMD_MASK;
+
+ if (iproc_i2c_write_master_command(mastercmd, info)) {
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * Function to initiate data receive, verify completion status,
+ * and read from SMBUS Read FIFO
+ */
+static int iproc_i2c_data_recv(struct iproc_xact_info *info,
+ uint32_t *num_bytes_read)
+{
+ int rc;
+ uint32_t mastercmd;
+ uint32_t regval;
+
+ /* Make sure the previous transaction completed */
+ rc = iproc_i2c_startbusy_wait(info->bus_id);
+
+ if (rc < 0) {
+ WARN("%s: Receive: Bus is busy, exiting\n", __func__);
+ return rc;
+ }
+
+ /* Program all transaction bytes into master Tx FIFO */
+ iproc_i2c_write_trans_data(info);
+
+ /*
+ * Program master command register (0x30) with protocol type and set
+ * start_busy_command bit to initiate the write transaction
+ */
+ mastercmd = (info->smb_proto << SMB_MSTRSMBUSPROTO_SHIFT) |
+ SMB_MSTRSTARTBUSYCMD_MASK | info->size;
+
+ if (iproc_i2c_write_master_command(mastercmd, info)) {
+ return -1;
+ }
+
+ /* Read received byte(s), after TX out address etc */
+ regval = iproc_i2c_reg_read(info->bus_id, SMB_MSTRDATARD_REG);
+
+ /* For block read, protocol (hw) returns byte count,as the first byte */
+ if (info->smb_proto == SMBUS_PROT_BLK_RD) {
+ uint32_t i;
+
+ *num_bytes_read = regval & SMB_MSTRRDDATA_MASK;
+ /*
+ * Limit to reading a max of 32 bytes only; just a safeguard.
+ * If # bytes read is a number > 32, check transaction set up,
+ * and contact hw engg.
+ * Assumption: PEC is disabled
+ */
+ for (i = 0U; (i < *num_bytes_read) &&
+ (i < I2C_SMBUS_BLOCK_MAX); i++) {
+ /* Read Rx FIFO for data bytes */
+ regval = iproc_i2c_reg_read(info->bus_id,
+ SMB_MSTRDATARD_REG);
+ info->data[i] = regval & SMB_MSTRRDDATA_MASK;
+ }
+ } else {
+ /* 1 Byte data */
+ *info->data = regval & SMB_MSTRRDDATA_MASK;
+ *num_bytes_read = 1U;
+ }
+
+ return 0;
+}
+
+/*
+ * This function set clock frequency for SMBus block. As per hardware
+ * engineering, the clock frequency can be changed dynamically.
+ */
+static int iproc_i2c_set_clk_freq(uint32_t bus_id, smb_clk_freq_t freq)
+{
+ uint32_t val;
+
+ switch (freq) {
+ case IPROC_SMB_SPEED_100KHz:
+ val = 0U;
+ break;
+ case IPROC_SMB_SPEED_400KHz:
+ val = 1U;
+ break;
+ default:
+ return -1;
+ }
+
+ iproc_i2c_reg_clearset(bus_id, SMB_TIMGCFG_REG,
+ SMB_TIMGCFG_MODE400_MASK,
+ val << SMB_TIMGCFG_MODE400_SHIFT);
+
+ return 0;
+}
+
+/* Helper function to fill the iproc_xact_info structure */
+static void iproc_i2c_fill_info(struct iproc_xact_info *info, uint32_t bus_id,
+ uint8_t devaddr, uint8_t cmd, uint8_t *value,
+ uint8_t smb_proto, uint32_t cmd_valid)
+{
+ info->bus_id = bus_id;
+ info->devaddr = devaddr;
+ info->command = (uint8_t)cmd;
+ info->smb_proto = smb_proto;
+ info->data = value;
+ info->size = 1U;
+ info->flags = 0U;
+ info->cmd_valid = cmd_valid;
+}
+
+/* This function initializes the SMBUS */
+static void iproc_i2c_init(uint32_t bus_id, int speed)
+{
+ uint32_t regval;
+
+#ifdef BCM_I2C_DEBUG
+ INFO("%s: Enter Init\n", __func__);
+#endif
+
+ /* Put controller in reset */
+ regval = iproc_i2c_reg_read(bus_id, SMB_CFG_REG);
+ regval |= BIT(SMB_CFG_RST_SHIFT);
+ regval &= ~(BIT(SMB_CFG_SMBEN_SHIFT));
+ iproc_i2c_reg_write(bus_id, SMB_CFG_REG, regval);
+
+ /* Wait 100 usec per spec */
+ udelay(100U);
+
+ /* Bring controller out of reset */
+ regval &= ~(BIT(SMB_CFG_RST_SHIFT));
+ iproc_i2c_reg_write(bus_id, SMB_CFG_REG, regval);
+
+ /*
+ * Flush Tx, Rx FIFOs. Note we are setting the Rx FIFO threshold to 0.
+ * May be OK since we are setting RX_EVENT and RX_FIFO_FULL interrupts
+ */
+ regval = SMB_MSTRRXFIFOFLSH_MASK | SMB_MSTRTXFIFOFLSH_MASK;
+ iproc_i2c_reg_write(bus_id, SMB_MSTRFIFOCTL_REG, regval);
+
+ /*
+ * Enable SMbus block. Note, we are setting MASTER_RETRY_COUNT to zero
+ * since there will be only one master
+ */
+
+ regval = iproc_i2c_reg_read(bus_id, SMB_CFG_REG);
+ regval |= SMB_CFG_SMBEN_MASK;
+ iproc_i2c_reg_write(bus_id, SMB_CFG_REG, regval);
+ /* Wait a minimum of 50 Usec, as per SMB hw doc. But we wait longer */
+ mdelay(10U);
+
+ /* If error then set default speed */
+ if (i2c_set_bus_speed(bus_id, speed)) {
+ i2c_set_bus_speed(bus_id, I2C_SPEED_DEFAULT);
+ }
+
+ /* Disable intrs */
+ regval = 0x0U;
+ iproc_i2c_reg_write(bus_id, SMB_EVTEN_REG, regval);
+
+ /* Clear intrs (W1TC) */
+ regval = iproc_i2c_reg_read(bus_id, SMB_EVTSTS_REG);
+ iproc_i2c_reg_write(bus_id, SMB_EVTSTS_REG, regval);
+
+#ifdef BCM_I2C_DEBUG
+ iproc_dump_i2c_regs(bus_id);
+
+ INFO("%s: Exit Init Successfully\n", __func__);
+#endif
+}
+
+/*
+ * Function Name: i2c_init
+ *
+ * Description:
+ * This function initializes the SMBUS.
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ * speed - I2C bus speed in Hz
+ *
+ * Return:
+ * 0 on success, or -1 on failure.
+ */
+int i2c_init(uint32_t bus_id, int speed)
+{
+ if (bus_id > MAX_I2C) {
+ WARN("%s: Invalid Bus %u\n", __func__, bus_id);
+ return -1;
+ }
+
+ iproc_i2c_init(bus_id, speed);
+ return 0U;
+}
+
+/*
+ * Function Name: i2c_probe
+ *
+ * Description:
+ * This function probes the I2C bus for the existence of the specified
+ * device.
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ * devaddr - Device Address
+ *
+ * Return:
+ * 0 on success, or -1 on failure.
+ */
+int i2c_probe(uint32_t bus_id, uint8_t devaddr)
+{
+ uint32_t regval;
+ int rc;
+
+ /*
+ * i2c_init() Initializes internal regs, disable intrs (and then clear intrs),
+ * set fifo thresholds, etc.
+ * Shift devaddr by 1 bit since SMBus uses the low bit[0] for R/W_n
+ */
+ regval = (devaddr << 1U);
+ iproc_i2c_reg_write(bus_id, SMB_MSTRDATAWR_REG, regval);
+
+ regval = ((SMBUS_PROT_QUICK_CMD << SMB_MSTRSMBUSPROTO_SHIFT) |
+ SMB_MSTRSTARTBUSYCMD_MASK);
+ iproc_i2c_reg_write(bus_id, SMB_MSTRCMD_REG, regval);
+
+ rc = iproc_i2c_startbusy_wait(bus_id);
+
+ if (rc < 0) {
+ WARN("%s: Probe: bus is busy, exiting\n", __func__);
+ return rc;
+ }
+
+ regval = iproc_i2c_reg_read(bus_id, SMB_MSTRCMD_REG);
+ if (((regval & SMB_MSTRSTS_MASK) >> SMB_MSTRSTS_SHIFT) == 0)
+ VERBOSE("i2c device address: 0x%x\n", devaddr);
+ else
+ return -1;
+
+#ifdef BCM_I2C_DEBUG
+ iproc_dump_i2c_regs(bus_id);
+#endif
+ return 0;
+}
+
+/*
+ * Function Name: i2c_recv_byte
+ *
+ * Description:
+ * This function reads I2C data from a device without specifying
+ * a command regsiter.
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ * devaddr - Device Address
+ * value - Data Read
+ *
+ * Return:
+ * 0 on success, or -1 on failure.
+ */
+int i2c_recv_byte(uint32_t bus_id, uint8_t devaddr, uint8_t *value)
+{
+ int rc;
+ struct iproc_xact_info info;
+ uint32_t num_bytes_read = 0;
+
+ iproc_i2c_fill_info(&info, bus_id, devaddr, 0U, value,
+ SMBUS_PROT_RECV_BYTE, 0U);
+
+ /* Refer to i2c_smbus_read_byte for params passed. */
+ rc = iproc_i2c_data_recv(&info, &num_bytes_read);
+
+ if (rc < 0) {
+ printf("%s: %s error accessing device 0x%x\n",
+ __func__, "Read", devaddr);
+ }
+
+ return rc;
+}
+
+/*
+ * Function Name: i2c_send_byte
+ *
+ * Description:
+ * This function send I2C data to a device without specifying
+ * a command regsiter.
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ * devaddr - Device Address
+ * value - Data Send
+ *
+ * Return:
+ * 0 on success, or -1 on failure.
+ */
+int i2c_send_byte(uint32_t bus_id, uint8_t devaddr, uint8_t value)
+{
+ int rc;
+ struct iproc_xact_info info;
+
+ iproc_i2c_fill_info(&info, bus_id, devaddr, 0U, &value,
+ SMBUS_PROT_SEND_BYTE, 0U);
+
+ /* Refer to i2c_smbus_write_byte params passed. */
+ rc = iproc_i2c_data_send(&info);
+
+ if (rc < 0) {
+ ERROR("%s: %s error accessing device 0x%x\n",
+ __func__, "Write", devaddr);
+ }
+
+ return rc;
+}
+
+/* Helper function to read a single byte */
+static int i2c_read_byte(uint32_t bus_id,
+ uint8_t devaddr,
+ uint8_t regoffset,
+ uint8_t *value)
+{
+ int rc;
+ struct iproc_xact_info info;
+ uint32_t num_bytes_read = 0U;
+
+ iproc_i2c_fill_info(&info, bus_id, devaddr, regoffset, value,
+ SMBUS_PROT_RD_BYTE, 1U);
+
+ /* Refer to i2c_smbus_read_byte for params passed. */
+ rc = iproc_i2c_data_recv(&info, &num_bytes_read);
+
+ if (rc < 0) {
+ ERROR("%s: %s error accessing device 0x%x\n",
+ __func__, "Read", devaddr);
+ }
+ return rc;
+}
+
+/*
+ * Function Name: i2c_read
+ *
+ * Description:
+ * This function reads I2C data from a device with a designated
+ * command register
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ * devaddr - Device Address
+ * addr - Register Offset
+ * alen - Address Length, 1 for byte, 2 for word (not supported)
+ * buffer - Data Buffer
+ * len - Data Length in bytes
+ *
+ * Return:
+ * 0 on success, or -1 on failure.
+ */
+int i2c_read(uint32_t bus_id,
+ uint8_t devaddr,
+ uint32_t addr,
+ int alen,
+ uint8_t *buffer,
+ int len)
+{
+ uint32_t i;
+
+ if (alen > 1) {
+ WARN("I2C read: addr len %d not supported\n", alen);
+ return -1;
+ }
+
+ if (addr + len > 256) {
+ WARN("I2C read: address out of range\n");
+ return -1;
+ }
+
+ for (i = 0U; i < len; i++) {
+ if (i2c_read_byte(bus_id, devaddr, addr + i, &buffer[i])) {
+ ERROR("I2C read: I/O error\n");
+ iproc_i2c_init(bus_id, i2c_get_bus_speed(bus_id));
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+/* Helper function to write a single byte */
+static int i2c_write_byte(uint32_t bus_id,
+ uint8_t devaddr,
+ uint8_t regoffset,
+ uint8_t value)
+{
+ int rc;
+ struct iproc_xact_info info;
+
+ iproc_i2c_fill_info(&info, bus_id, devaddr, regoffset, &value,
+ SMBUS_PROT_WR_BYTE, 1U);
+
+ /* Refer to i2c_smbus_write_byte params passed. */
+ rc = iproc_i2c_data_send(&info);
+
+ if (rc < 0) {
+ ERROR("%s: %s error accessing device 0x%x\n",
+ __func__, "Write", devaddr);
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * Function Name: i2c_write
+ *
+ * Description:
+ * This function write I2C data to a device with a designated
+ * command register
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ * devaddr - Device Address
+ * addr - Register Offset
+ * alen - Address Length, 1 for byte, 2 for word (not supported)
+ * buffer - Data Buffer
+ * len - Data Length in bytes
+ *
+ * Return:
+ * 0 on success, or -1 on failure.
+ */
+int i2c_write(uint32_t bus_id,
+ uint8_t devaddr,
+ uint32_t addr,
+ int alen,
+ uint8_t *buffer,
+ int len)
+{
+ uint32_t i;
+
+ if (alen > 1) {
+ WARN("I2C write: addr len %d not supported\n", alen);
+ return -1;
+ }
+
+ if (addr + len > 256U) {
+ WARN("I2C write: address out of range\n");
+ return -1;
+ }
+
+ for (i = 0U; i < len; i++) {
+ if (i2c_write_byte(bus_id, devaddr, addr + i, buffer[i])) {
+ ERROR("I2C write: I/O error\n");
+ iproc_i2c_init(bus_id, i2c_get_bus_speed(bus_id));
+ return -1;
+ }
+ }
+ return 0;
+}
+
+/*
+ * Function Name: i2c_set_bus_speed
+ *
+ * Description:
+ * This function configures the SMBUS speed
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ * speed - I2C bus speed in Hz
+ *
+ * Return:
+ * 0 on success, or -1 on failure.
+ */
+int i2c_set_bus_speed(uint32_t bus_id, uint32_t speed)
+{
+ switch (speed) {
+ case I2C_SPEED_100KHz:
+ iproc_i2c_set_clk_freq(bus_id, IPROC_SMB_SPEED_100KHz);
+ break;
+
+ case I2C_SPEED_400KHz:
+ iproc_i2c_set_clk_freq(bus_id, IPROC_SMB_SPEED_400KHz);
+ break;
+
+ default:
+ return -1;
+ }
+ return 0;
+}
+
+/*
+ * Function Name: i2c_get_bus_speed
+ *
+ * Description:
+ * This function returns the SMBUS speed.
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ *
+ * Return:
+ * Bus speed in Hz, 0 on failure
+ */
+uint32_t i2c_get_bus_speed(uint32_t bus_id)
+{
+ uint32_t regval;
+ uint32_t retval = 0U;
+
+ regval = iproc_i2c_reg_read(bus_id, SMB_TIMGCFG_REG);
+ regval &= SMB_TIMGCFG_MODE400_MASK;
+ regval >>= SMB_TIMGCFG_MODE400_SHIFT;
+
+ switch (regval) {
+ case IPROC_SMB_SPEED_100KHz:
+ retval = I2C_SPEED_100KHz;
+ break;
+
+ case IPROC_SMB_SPEED_400KHz:
+ retval = I2C_SPEED_400KHz;
+ break;
+
+ default:
+ break;
+ }
+ return retval;
+}
+
diff --git a/drivers/brcm/mdio/mdio.c b/drivers/brcm/mdio/mdio.c
new file mode 100644
index 0000000..1cf9d66
--- /dev/null
+++ b/drivers/brcm/mdio/mdio.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2016 - 2021, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <string.h>
+
+#include <platform_def.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <mdio.h>
+
+static int mdio_op_status(uint32_t result)
+{
+ uint32_t timeout = 1000000U; /* loop for 1s */
+ uint32_t val;
+
+ do {
+ val = mmio_read_32(CMIC_MIIM_STAT);
+ if ((val & MDIO_STAT_DONE) == result) {
+ return 0;
+ }
+
+ udelay(1U);
+ } while (timeout-- != 0U);
+ return -1;
+}
+
+static int mdio_op(uint16_t busid, uint16_t phyid, uint32_t reg,
+ uint16_t val, uint8_t op)
+{
+ uint32_t param;
+ int ret;
+
+ mmio_write_32(CMIC_MIIM_CTRL, 0U);
+ ret = mdio_op_status(0U);
+ if (ret != 0) {
+ goto err;
+ }
+
+ param = 0U;
+ param |= 1U << MDIO_PARAM_INTERNAL_SEL;
+ param |= (busid & MDIO_PARAM_BUSID_MASK) << MDIO_PARAM_BUSID;
+ param |= (phyid & MDIO_PARAM_PHYID_MASK) << MDIO_PARAM_PHYID;
+ param |= (val & MDIO_PARAM_DATA_MASK) << MDIO_PARAM_DATA;
+
+ mmio_write_32(CMIC_MIIM_PARAM, param);
+
+ mmio_write_32(CMIC_MIIM_ADDRESS, reg);
+
+ mmio_write_32(CMIC_MIIM_CTRL, op);
+
+ ret = mdio_op_status(1U);
+ if (ret != 0) {
+ goto err;
+ }
+
+ if (op == MDIO_CTRL_READ_OP) {
+ ret = mmio_read_32(CMIC_MIIM_READ_DATA) & MDIO_READ_DATA_MASK;
+ }
+err:
+ return ret;
+}
+
+int mdio_write(uint16_t busid, uint16_t phyid, uint32_t reg, uint16_t val)
+{
+ int ret;
+
+ ret = mdio_op(busid, phyid, reg, val, MDIO_CTRL_WRITE_OP);
+ if (ret == -1) {
+ INFO("MDIO write fail\n");
+ }
+ return ret;
+}
+
+int mdio_read(uint16_t busid, uint16_t phyid, uint32_t reg)
+{
+ int ret;
+
+ ret = mdio_op(busid, phyid, reg, 0U, MDIO_CTRL_READ_OP);
+ if (ret == -1) {
+ INFO("MDIO read fail\n");
+ }
+ return ret;
+}
diff --git a/drivers/fwu/fwu.c b/drivers/fwu/fwu.c
new file mode 100644
index 0000000..7cb4c29
--- /dev/null
+++ b/drivers/fwu/fwu.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <common/debug.h>
+#include <common/tf_crc32.h>
+#include <common/tbbr/tbbr_img_def.h>
+#include <drivers/fwu/fwu.h>
+#include <drivers/fwu/fwu_metadata.h>
+#include <drivers/io/io_storage.h>
+
+#include <plat/common/platform.h>
+
+/*
+ * Assert that crc_32 is the first member of fwu_metadata structure.
+ * It avoids accessing data outside of the metadata structure during
+ * CRC32 computation if the crc_32 field gets moved due the structure
+ * member(s) addition in the future.
+ */
+CASSERT((offsetof(struct fwu_metadata, crc_32) == 0),
+ crc_32_must_be_first_member_of_structure);
+
+static struct fwu_metadata metadata;
+static bool is_fwu_initialized;
+
+/*******************************************************************************
+ * Compute CRC32 of the FWU metadata, and check it against the CRC32 value
+ * present in the FWU metadata.
+ *
+ * return -1 on error, otherwise 0
+ ******************************************************************************/
+static int fwu_metadata_crc_check(void)
+{
+ unsigned char *data = (unsigned char *)&metadata;
+
+ uint32_t calc_crc = tf_crc32(0U, data + sizeof(metadata.crc_32),
+ (sizeof(metadata) -
+ sizeof(metadata.crc_32)));
+
+ if (metadata.crc_32 != calc_crc) {
+ return -1;
+ }
+
+ return 0;
+}
+
+/*******************************************************************************
+ * Check the sanity of FWU metadata.
+ *
+ * return -1 on error, otherwise 0
+ ******************************************************************************/
+static int fwu_metadata_sanity_check(void)
+{
+ /* ToDo: add more conditions for sanity check */
+ if ((metadata.active_index >= NR_OF_FW_BANKS) ||
+ (metadata.previous_active_index >= NR_OF_FW_BANKS)) {
+ return -1;
+ }
+
+ return 0;
+}
+
+/*******************************************************************************
+ * Verify and load specified FWU metadata image to local FWU metadata structure.
+ *
+ * @image_id: FWU metadata image id (either FWU_METADATA_IMAGE_ID or
+ * BKUP_FWU_METADATA_IMAGE_ID)
+ *
+ * return a negative value on error, otherwise 0
+ ******************************************************************************/
+static int fwu_metadata_load(unsigned int image_id)
+{
+ int result;
+ uintptr_t dev_handle, image_handle, image_spec;
+ size_t bytes_read;
+
+ assert((image_id == FWU_METADATA_IMAGE_ID) ||
+ (image_id == BKUP_FWU_METADATA_IMAGE_ID));
+
+ result = plat_fwu_set_metadata_image_source(image_id,
+ &dev_handle,
+ &image_spec);
+ if (result != 0) {
+ WARN("Failed to set reference to image id=%u (%i)\n",
+ image_id, result);
+ return result;
+ }
+
+ result = io_open(dev_handle, image_spec, &image_handle);
+ if (result != 0) {
+ WARN("Failed to load image id id=%u (%i)\n",
+ image_id, result);
+ return result;
+ }
+
+ result = io_read(image_handle, (uintptr_t)&metadata,
+ sizeof(struct fwu_metadata), &bytes_read);
+
+ if (result != 0) {
+ WARN("Failed to read image id=%u (%i)\n", image_id, result);
+ goto exit;
+ }
+
+ if (sizeof(struct fwu_metadata) != bytes_read) {
+ /* return -1 in case of partial/no read */
+ result = -1;
+ WARN("Read bytes (%zu) instead of expected (%zu) bytes\n",
+ bytes_read, sizeof(struct fwu_metadata));
+ goto exit;
+ }
+
+ /* sanity check on loaded parameters */
+ result = fwu_metadata_sanity_check();
+ if (result != 0) {
+ WARN("Sanity %s\n", "check failed on FWU metadata");
+ goto exit;
+ }
+
+ /* CRC check on loaded parameters */
+ result = fwu_metadata_crc_check();
+ if (result != 0) {
+ WARN("CRC %s\n", "check failed on FWU metadata");
+ }
+
+exit:
+ (void)io_close(image_handle);
+
+ return result;
+}
+
+/*******************************************************************************
+ * The system runs in the trial run state if any of the images in the active
+ * firmware bank has not been accepted yet.
+ *
+ * Returns true if the system is running in the trial state.
+ ******************************************************************************/
+bool fwu_is_trial_run_state(void)
+{
+ bool trial_run = false;
+
+ assert(is_fwu_initialized == true);
+
+ for (unsigned int i = 0U; i < NR_OF_IMAGES_IN_FW_BANK; i++) {
+ struct fwu_image_entry *entry = &metadata.img_entry[i];
+ struct fwu_image_properties *img_props =
+ &entry->img_props[metadata.active_index];
+ if (img_props->accepted == 0) {
+ trial_run = true;
+ break;
+ }
+ }
+
+ return trial_run;
+}
+
+/*******************************************************************************
+ * Load verified copy of FWU metadata image kept in the platform NV storage
+ * into local FWU metadata structure.
+ * Also, update platform I/O policies with the offset address and length of
+ * firmware-updated images kept in the platform NV storage.
+ ******************************************************************************/
+void fwu_init(void)
+{
+ /* Load FWU metadata which will be used to load the images in the
+ * active bank as per PSA FWU specification
+ */
+ int result = fwu_metadata_load(FWU_METADATA_IMAGE_ID);
+
+ if (result != 0) {
+ WARN("loading of FWU-Metadata failed, "
+ "using Bkup-FWU-Metadata\n");
+
+ result = fwu_metadata_load(BKUP_FWU_METADATA_IMAGE_ID);
+ if (result != 0) {
+ ERROR("loading of Bkup-FWU-Metadata failed\n");
+ panic();
+ }
+ }
+
+ plat_fwu_set_images_source(&metadata);
+
+ is_fwu_initialized = true;
+}
diff --git a/drivers/fwu/fwu.mk b/drivers/fwu/fwu.mk
new file mode 100644
index 0000000..f4452e0
--- /dev/null
+++ b/drivers/fwu/fwu.mk
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2021, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+FWU_SRC_DIR := drivers/fwu/
+
+FWU_SRCS := ${FWU_SRC_DIR}fwu.c
+
+BL2_SOURCES += ${FWU_SRCS}
diff --git a/drivers/io/io_mtd.c b/drivers/io/io_mtd.c
index 7575fa2..ba8cecd 100644
--- a/drivers/io/io_mtd.c
+++ b/drivers/io/io_mtd.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -18,8 +18,9 @@
typedef struct {
io_mtd_dev_spec_t *dev_spec;
uintptr_t base;
- unsigned long long offset; /* Offset in bytes */
- unsigned long long size; /* Size of device in bytes */
+ unsigned long long pos; /* Offset in bytes */
+ unsigned long long size; /* Size of device in bytes */
+ unsigned long long extra_offset; /* Extra offset in bytes */
} mtd_dev_state_t;
io_type_t device_type_mtd(void);
@@ -110,16 +111,47 @@
return 0;
}
+static int mtd_add_extra_offset(mtd_dev_state_t *cur, size_t *extra_offset)
+{
+ io_mtd_ops_t *ops = &cur->dev_spec->ops;
+ int ret;
+
+ if (ops->seek == NULL) {
+ return 0;
+ }
+
+ ret = ops->seek(cur->base, cur->pos, extra_offset);
+ if (ret != 0) {
+ ERROR("%s: Seek error %d\n", __func__, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
static int mtd_open(io_dev_info_t *dev_info, const uintptr_t spec,
io_entity_t *entity)
{
mtd_dev_state_t *cur;
+ io_block_spec_t *region;
+ size_t extra_offset = 0U;
+ int ret;
assert((dev_info->info != 0UL) && (entity->info == 0UL));
+ region = (io_block_spec_t *)spec;
cur = (mtd_dev_state_t *)dev_info->info;
entity->info = (uintptr_t)cur;
- cur->offset = 0U;
+ cur->base = region->offset;
+ cur->pos = 0U;
+ cur->extra_offset = 0U;
+
+ ret = mtd_add_extra_offset(cur, &extra_offset);
+ if (ret != 0) {
+ return ret;
+ }
+
+ cur->base += extra_offset;
return 0;
}
@@ -128,6 +160,8 @@
static int mtd_seek(io_entity_t *entity, int mode, signed long long offset)
{
mtd_dev_state_t *cur;
+ size_t extra_offset = 0U;
+ int ret;
assert((entity->info != (uintptr_t)NULL) && (offset >= 0));
@@ -140,22 +174,29 @@
return -EINVAL;
}
- cur->offset = offset;
+ cur->pos = offset;
break;
case IO_SEEK_CUR:
- if (((cur->offset + (unsigned long long)offset) >=
+ if (((cur->base + cur->pos + (unsigned long long)offset) >=
cur->size) ||
- ((cur->offset + (unsigned long long)offset) <
- cur->offset)) {
+ ((cur->base + cur->pos + (unsigned long long)offset) <
+ cur->base + cur->pos)) {
return -EINVAL;
}
- cur->offset += (unsigned long long)offset;
+ cur->pos += (unsigned long long)offset;
break;
default:
return -EINVAL;
}
+ ret = mtd_add_extra_offset(cur, &extra_offset);
+ if (ret != 0) {
+ return ret;
+ }
+
+ cur->extra_offset = extra_offset;
+
return 0;
}
@@ -174,18 +215,19 @@
assert(ops->read != NULL);
VERBOSE("Read at %llx into %lx, length %zi\n",
- cur->offset, buffer, length);
- if ((cur->offset + length) > cur->dev_spec->device_size) {
+ cur->base + cur->pos, buffer, length);
+ if ((cur->base + cur->pos + length) > cur->dev_spec->device_size) {
return -EINVAL;
}
- ret = ops->read(cur->offset, buffer, length, out_length);
+ ret = ops->read(cur->base + cur->pos + cur->extra_offset, buffer,
+ length, out_length);
if (ret < 0) {
return ret;
}
assert(*out_length == length);
- cur->offset += *out_length;
+ cur->pos += *out_length;
return 0;
}
diff --git a/drivers/marvell/comphy/phy-comphy-3700.c b/drivers/marvell/comphy/phy-comphy-3700.c
index f6a40a5..7377e5e 100644
--- a/drivers/marvell/comphy/phy-comphy-3700.c
+++ b/drivers/marvell/comphy/phy-comphy-3700.c
@@ -14,6 +14,7 @@
#include <mvebu.h>
#include <mvebu_def.h>
+#include <plat_marvell.h>
#include "phy-comphy-3700.h"
#include "phy-comphy-common.h"
@@ -29,15 +30,6 @@
#define USB3_GBE1_PHY (MVEBU_REGS_BASE + 0x5C000)
#define COMPHY_SD_ADDR (MVEBU_REGS_BASE + 0x1F000)
-/*
- * Below address in used only for reading, therefore no problem with concurrent
- * Linux access.
- */
-#define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8)
- #define MVEBU_XTAL_MODE_MASK BIT(9)
- #define MVEBU_XTAL_MODE_OFFS 9
- #define MVEBU_XTAL_CLOCK_25MHZ 0x0
-
struct sgmii_phy_init_data_fix {
uint16_t addr;
uint16_t value;
@@ -125,20 +117,6 @@
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */
};
-/* returns reference clock in MHz (25 or 40) */
-static uint32_t get_ref_clk(void)
-{
- uint32_t val;
-
- val = (mmio_read_32(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
- MVEBU_XTAL_MODE_OFFS;
-
- if (val == MVEBU_XTAL_CLOCK_25MHZ)
- return 25;
- else
- return 40;
-}
-
/* PHY selector configures with corresponding modes */
static void mvebu_a3700_comphy_set_phy_selector(uint8_t comphy_index,
uint32_t comphy_mode)
@@ -525,7 +503,8 @@
data |= TXD_INVERT_BIT;
if (invert & COMPHY_POLARITY_RXD_INVERT)
data |= RXD_INVERT_BIT;
- reg_set16(SGMIIPHY_ADDR(COMPHY_SYNC_PATTERN_REG, sd_ip_addr), data, 0);
+ mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
+ reg_set16(SGMIIPHY_ADDR(COMPHY_SYNC_PATTERN_REG, sd_ip_addr), data, mask);
/*
* 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to
@@ -563,7 +542,7 @@
* refer to RX initialization part for details.
*/
reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index),
- PHY_RX_INIT_BIT, 0x0);
+ PHY_RX_INIT_BIT, PHY_RX_INIT_BIT);
ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE +
COMPHY_PHY_STATUS_OFFSET(comphy_index),
@@ -594,7 +573,7 @@
debug_enter();
data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT;
- mask = 0;
+ mask = data;
offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index);
reg_set(offset, data, mask);
@@ -746,12 +725,15 @@
/*
* 13. Check the Polarity invert bit
*/
- if (invert & COMPHY_POLARITY_TXD_INVERT)
- usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, TXD_INVERT_BIT,
- TXD_INVERT_BIT, mode);
- if (invert & COMPHY_POLARITY_RXD_INVERT)
- usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, RXD_INVERT_BIT,
- RXD_INVERT_BIT, mode);
+ data = 0U;
+ if (invert & COMPHY_POLARITY_TXD_INVERT) {
+ data |= TXD_INVERT_BIT;
+ }
+ if (invert & COMPHY_POLARITY_RXD_INVERT) {
+ data |= RXD_INVERT_BIT;
+ }
+ mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
+ usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, data, mask, mode);
/*
* 14. Set max speed generation to USB3.0 5Gbps
@@ -802,21 +784,22 @@
{
int ret;
uint32_t ref_clk;
+ uint32_t mask, data;
int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode);
debug_enter();
/* 1. Enable max PLL. */
reg_set16(LANE_CFG1_ADDR(PCIE) + COMPHY_SD_ADDR,
- USE_MAX_PLL_RATE_EN, 0x0);
+ USE_MAX_PLL_RATE_EN, USE_MAX_PLL_RATE_EN);
/* 2. Select 20 bit SERDES interface. */
reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE) + COMPHY_SD_ADDR,
- CFG_SEL_20B, 0);
+ CFG_SEL_20B, CFG_SEL_20B);
/* 3. Force to use reg setting for PCIe mode */
reg_set16(MISC_REG1_ADDR(PCIE) + COMPHY_SD_ADDR,
- SEL_BITS_PCIE_FORCE, 0);
+ SEL_BITS_PCIE_FORCE, SEL_BITS_PCIE_FORCE);
/* 4. Change RX wait */
reg_set16(PWR_MGM_TIM1_ADDR(PCIE) + COMPHY_SD_ADDR,
@@ -830,7 +813,7 @@
/* 6. Enable the output of 100M/125M/500M clock */
reg_set16(MISC_REG0_ADDR(PCIE) + COMPHY_SD_ADDR,
- MISC_REG0_DEFAULT_VALUE | CLK500M_EN | CLK100M_125M_EN,
+ MISC_REG0_DEFAULT_VALUE | CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN,
REG_16_BIT_MASK);
/*
@@ -858,13 +841,15 @@
SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT, REG_16_BIT_MASK);
/* 10. Check the Polarity invert bit */
- if (invert & COMPHY_POLARITY_TXD_INVERT)
- reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR,
- TXD_INVERT_BIT, 0x0);
-
- if (invert & COMPHY_POLARITY_RXD_INVERT)
- reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR,
- RXD_INVERT_BIT, 0x0);
+ data = 0U;
+ if (invert & COMPHY_POLARITY_TXD_INVERT) {
+ data |= TXD_INVERT_BIT;
+ }
+ if (invert & COMPHY_POLARITY_RXD_INVERT) {
+ data |= RXD_INVERT_BIT;
+ }
+ mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
+ reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask);
/* 11. Release SW reset */
reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR,
diff --git a/drivers/marvell/comphy/phy-comphy-3700.h b/drivers/marvell/comphy/phy-comphy-3700.h
index 1628e36..94056f1 100644
--- a/drivers/marvell/comphy/phy-comphy-3700.h
+++ b/drivers/marvell/comphy/phy-comphy-3700.h
@@ -104,6 +104,7 @@
#define COMPHY_MISC_REG0_ADDR 0x4F
#define MISC_REG0_ADDR(unit) (COMPHY_MISC_REG0_ADDR * PHY_SHFT(unit))
#define CLK100M_125M_EN BIT(4)
+#define TXDCLK_2X_SEL BIT(6)
#define CLK500M_EN BIT(7)
#define PHY_REF_CLK_SEL BIT(10)
#define MISC_REG0_DEFAULT_VALUE 0xA00D
diff --git a/drivers/marvell/comphy/phy-comphy-cp110.c b/drivers/marvell/comphy/phy-comphy-cp110.c
index d1c26f8..86f4c77 100644
--- a/drivers/marvell/comphy/phy-comphy-cp110.c
+++ b/drivers/marvell/comphy/phy-comphy-cp110.c
@@ -53,14 +53,19 @@
#define SYS_CTRL_FROM_COMPHY_ADDR(x) ((x & ~0xffffff) + 0x440000)
/* DFX register spaces */
-#define SAR_RST_PCIE0_CLOCK_CONFIG_CP1_OFFSET (0)
-#define SAR_RST_PCIE0_CLOCK_CONFIG_CP1_MASK (0x1 << \
- SAR_RST_PCIE0_CLOCK_CONFIG_CP1_OFFSET)
-#define SAR_RST_PCIE1_CLOCK_CONFIG_CP1_OFFSET (1)
-#define SAR_RST_PCIE1_CLOCK_CONFIG_CP1_MASK (0x1 << \
- SAR_RST_PCIE1_CLOCK_CONFIG_CP1_OFFSET)
-#define SAR_STATUS_0_REG 200
+#define SAR_RST_PCIE0_CLOCK_CONFIG_CP0_OFFSET (30)
+#define SAR_RST_PCIE0_CLOCK_CONFIG_CP0_MASK (0x1UL << \
+ SAR_RST_PCIE0_CLOCK_CONFIG_CP0_OFFSET)
+#define SAR_RST_PCIE1_CLOCK_CONFIG_CP0_OFFSET (31)
+#define SAR_RST_PCIE1_CLOCK_CONFIG_CP0_MASK (0x1UL << \
+ SAR_RST_PCIE1_CLOCK_CONFIG_CP0_OFFSET)
+#define SAR_STATUS_0_REG 0x40600
#define DFX_FROM_COMPHY_ADDR(x) ((x & ~0xffffff) + DFX_BASE)
+/* Common Phy training */
+#define COMPHY_TRX_TRAIN_COMPHY_OFFS 0x1000
+#define COMPHY_TRX_TRAIN_RX_TRAIN_ENABLE 0x1
+#define COMPHY_TRX_RELATIVE_ADDR(comphy_index) (comphy_train_base + \
+ (comphy_index) * COMPHY_TRX_TRAIN_COMPHY_OFFS)
/* The same Units Soft Reset Config register are accessed in all PCIe ports
* initialization, so a spin lock is defined in case when more than 1 CPUs
@@ -829,7 +834,8 @@
static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base,
uint8_t comphy_index,
- uint32_t comphy_mode)
+ uint32_t comphy_mode,
+ uint64_t comphy_train_base)
{
uintptr_t hpipe_addr, sd_ip_addr, comphy_addr, addr;
uint32_t mask, data, speed = COMPHY_GET_SPEED(comphy_mode);
@@ -837,7 +843,6 @@
uint8_t ap_nr, cp_nr;
debug_enter();
-
mvebu_cp110_get_ap_and_cp_nr(&ap_nr, &cp_nr, comphy_base);
if (rx_trainng_done[ap_nr][cp_nr][comphy_index]) {
@@ -1234,6 +1239,14 @@
data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
+ /* Force rx training on 10G port */
+ data = mmio_read_32(COMPHY_TRX_RELATIVE_ADDR(comphy_index));
+ data |= COMPHY_TRX_TRAIN_RX_TRAIN_ENABLE;
+ mmio_write_32(COMPHY_TRX_RELATIVE_ADDR(comphy_index), data);
+ mdelay(200);
+ data &= ~COMPHY_TRX_TRAIN_RX_TRAIN_ENABLE;
+ mmio_write_32(COMPHY_TRX_RELATIVE_ADDR(comphy_index), data);
+
debug_exit();
return ret;
@@ -1305,11 +1318,11 @@
reg = mmio_read_32(DFX_FROM_COMPHY_ADDR(comphy_base) +
SAR_STATUS_0_REG);
if (comphy_index == COMPHY_LANE4 || comphy_index == COMPHY_LANE5)
- clk_dir = (reg & SAR_RST_PCIE1_CLOCK_CONFIG_CP1_MASK) >>
- SAR_RST_PCIE1_CLOCK_CONFIG_CP1_OFFSET;
+ clk_dir = (reg & SAR_RST_PCIE1_CLOCK_CONFIG_CP0_MASK) >>
+ SAR_RST_PCIE1_CLOCK_CONFIG_CP0_OFFSET;
else
- clk_dir = (reg & SAR_RST_PCIE0_CLOCK_CONFIG_CP1_MASK) >>
- SAR_RST_PCIE0_CLOCK_CONFIG_CP1_OFFSET;
+ clk_dir = (reg & SAR_RST_PCIE0_CLOCK_CONFIG_CP0_MASK) >>
+ SAR_RST_PCIE0_CLOCK_CONFIG_CP0_OFFSET;
debug("On lane %d\n", comphy_index);
debug("PCIe clock direction = %x\n", clk_dir);
@@ -2284,7 +2297,6 @@
uint32_t comphy_mode)
{
uint32_t mask, data;
- uint8_t ap_nr, cp_nr;
uintptr_t comphy_addr = comphy_addr =
COMPHY_ADDR(comphy_base, comphy_index);
@@ -2301,10 +2313,16 @@
reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
debug_exit();
- /* Start AP Firmware */
- mvebu_cp110_get_ap_and_cp_nr(&ap_nr, &cp_nr, comphy_base);
- mg_start_ap_fw(cp_nr, comphy_index);
+#if MSS_SUPPORT
+ do {
+ uint8_t ap_nr, cp_nr;
+ /* start ap fw */
+ mvebu_cp110_get_ap_and_cp_nr(&ap_nr, &cp_nr, comphy_base);
+ mg_start_ap_fw(cp_nr, comphy_index);
+
+ } while (0);
+#endif
return 0;
}
@@ -2343,8 +2361,10 @@
return 0;
}
-int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint8_t comphy_index,
- uint64_t comphy_mode)
+int mvebu_cp110_comphy_power_on(uint64_t comphy_base,
+ uint8_t comphy_index,
+ uint64_t comphy_mode,
+ uint64_t comphy_train_base)
{
int mode = COMPHY_GET_MODE(comphy_mode);
int err = 0;
@@ -2368,7 +2388,8 @@
case (COMPHY_SFI_MODE):
err = mvebu_cp110_comphy_xfi_power_on(comphy_base,
comphy_index,
- comphy_mode);
+ comphy_mode,
+ comphy_train_base);
break;
case (COMPHY_PCIE_MODE):
err = mvebu_cp110_comphy_pcie_power_on(comphy_base,
diff --git a/drivers/marvell/comphy/phy-comphy-cp110.h b/drivers/marvell/comphy/phy-comphy-cp110.h
index b4a2102..0be6c26 100644
--- a/drivers/marvell/comphy/phy-comphy-cp110.h
+++ b/drivers/marvell/comphy/phy-comphy-cp110.h
@@ -89,8 +89,9 @@
uint8_t comphy_index);
int mvebu_cp110_comphy_power_off(uint64_t comphy_base,
uint8_t comphy_index, uint64_t comphy_mode);
-int mvebu_cp110_comphy_power_on(uint64_t comphy_base,
- uint8_t comphy_index, uint64_t comphy_mode);
+int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint8_t comphy_index,
+ uint64_t comphy_mode,
+ uint64_t comphy_train_base);
int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
uint8_t comphy_index);
int mvebu_cp110_comphy_digital_reset(uint64_t comphy_base, uint8_t comphy_index,
diff --git a/drivers/marvell/ddr_phy_access.c b/drivers/marvell/ddr_phy_access.c
new file mode 100644
index 0000000..352d1ef
--- /dev/null
+++ b/drivers/marvell/ddr_phy_access.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2021 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include "ddr_phy_access.h"
+#include <lib/mmio.h>
+#include <drivers/marvell/ccu.h>
+#include <errno.h>
+
+#define DDR_PHY_END_ADDRESS 0x100000
+
+#ifdef DDR_PHY_DEBUG
+#define debug_printf(...) printf(__VA_ARGS__)
+#else
+#define debug_printf(...)
+#endif
+
+
+/*
+ * This routine writes 'data' to specified 'address' offset,
+ * with optional debug print support
+ */
+int snps_fw_write(uintptr_t offset, uint16_t data)
+{
+ debug_printf("In %s\n", __func__);
+
+ if (offset < DDR_PHY_END_ADDRESS) {
+ mmio_write_16(DDR_PHY_BASE_ADDR + (2 * offset), data);
+ return 0;
+ }
+ debug_printf("%s: illegal offset value: 0x%x\n", __func__, offset);
+ return -EINVAL;
+}
+
+int snps_fw_read(uintptr_t offset, uint16_t *read)
+{
+ debug_printf("In %s\n", __func__);
+
+ if (offset < DDR_PHY_END_ADDRESS) {
+ *read = mmio_read_16(DDR_PHY_BASE_ADDR + (2 * offset));
+ return 0;
+ }
+ debug_printf("%s: illegal offset value: 0x%x\n", __func__, offset);
+ return -EINVAL;
+}
+
+int mvebu_ddr_phy_write(uintptr_t offset, uint16_t data)
+{
+ return snps_fw_write(offset, data);
+}
+
+int mvebu_ddr_phy_read(uintptr_t offset, uint16_t *read)
+{
+ return snps_fw_read(offset, read);
+}
diff --git a/drivers/marvell/ddr_phy_access.h b/drivers/marvell/ddr_phy_access.h
new file mode 100644
index 0000000..5f9a668
--- /dev/null
+++ b/drivers/marvell/ddr_phy_access.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2021 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <plat_marvell.h>
+
+#define DEVICE_BASE 0xF0000000
+#define DDR_PHY_OFFSET 0x1000000
+#define DDR_PHY_BASE_ADDR (DEVICE_BASE + DDR_PHY_OFFSET)
+
+int mvebu_ddr_phy_write(uintptr_t offset, uint16_t data);
+int mvebu_ddr_phy_read(uintptr_t offset, uint16_t *read);
diff --git a/drivers/marvell/iob.c b/drivers/marvell/iob.c
index 87f147a..29088aa 100644
--- a/drivers/marvell/iob.c
+++ b/drivers/marvell/iob.c
@@ -44,6 +44,10 @@
#define IOB_WIN_ALR_OFFSET(win) (iob_base + 0x8 + (0x20 * win))
#define IOB_WIN_AHR_OFFSET(win) (iob_base + 0xC + (0x20 * win))
+#define IOB_WIN_DIOB_CR_OFFSET(win) (iob_base + 0x10 + (0x20 * win))
+#define IOB_WIN_XOR0_DIOB_EN BIT(0)
+#define IOB_WIN_XOR1_DIOB_EN BIT(1)
+
uintptr_t iob_base;
static void iob_win_check(struct addr_map_win *win, uint32_t win_num)
@@ -71,6 +75,17 @@
uint32_t iob_win_reg;
uint32_t alr, ahr;
uint64_t end_addr;
+ uint32_t reg_en;
+
+ /* move XOR (DMA) to use WIN1 which is used for PCI-EP address space */
+ reg_en = IOB_WIN_XOR0_DIOB_EN | IOB_WIN_XOR1_DIOB_EN;
+ iob_win_reg = mmio_read_32(IOB_WIN_DIOB_CR_OFFSET(0));
+ iob_win_reg &= ~reg_en;
+ mmio_write_32(IOB_WIN_DIOB_CR_OFFSET(0), iob_win_reg);
+
+ iob_win_reg = mmio_read_32(IOB_WIN_DIOB_CR_OFFSET(1));
+ iob_win_reg |= reg_en;
+ mmio_write_32(IOB_WIN_DIOB_CR_OFFSET(1), iob_win_reg);
end_addr = (win->base_addr + win->win_size - 1);
alr = (uint32_t)((win->base_addr >> ADDRESS_SHIFT) & ADDRESS_MASK);
diff --git a/drivers/marvell/mochi/ap807_setup.c b/drivers/marvell/mochi/ap807_setup.c
index 1069f8c..75e9654 100644
--- a/drivers/marvell/mochi/ap807_setup.c
+++ b/drivers/marvell/mochi/ap807_setup.c
@@ -15,8 +15,9 @@
#include <drivers/marvell/mci.h>
#include <drivers/marvell/mochi/ap_setup.h>
#include <lib/mmio.h>
+#include <lib/utils_def.h>
-#include <mvebu_def.h>
+#include <a8k_plat_def.h>
#define SMMU_sACR (MVEBU_SMMU_BASE + 0x10)
#define SMMU_sACR_PG_64K (1 << 16)
@@ -71,6 +72,23 @@
#define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + \
0x4 * index)
+#define XOR_STREAM_ID_REG(ch) (MVEBU_REGS_BASE + 0x410010 + (ch) * 0x20000)
+#define XOR_STREAM_ID_MASK 0xFFFF
+#define SDIO_STREAM_ID_REG (MVEBU_RFU_BASE + 0x4600)
+#define SDIO_STREAM_ID_MASK 0xFF
+
+/* Do not use the default Stream ID 0 */
+#define A807_STREAM_ID_BASE (0x1)
+
+static uintptr_t stream_id_reg[] = {
+ XOR_STREAM_ID_REG(0),
+ XOR_STREAM_ID_REG(1),
+ XOR_STREAM_ID_REG(2),
+ XOR_STREAM_ID_REG(3),
+ SDIO_STREAM_ID_REG,
+ 0
+};
+
enum axi_attr {
AXI_SDIO_ATTR = 0,
AXI_DFX_ATTR,
@@ -162,6 +180,21 @@
MCI_REMAP_OFF_SHIFT);
}
+/* Set a unique stream id for all DMA capable devices */
+static void ap807_stream_id_init(void)
+{
+ uint32_t i;
+
+ for (i = 0;
+ stream_id_reg[i] != 0 && i < ARRAY_SIZE(stream_id_reg); i++) {
+ uint32_t mask = stream_id_reg[i] == SDIO_STREAM_ID_REG ?
+ SDIO_STREAM_ID_MASK : XOR_STREAM_ID_MASK;
+
+ mmio_clrsetbits_32(stream_id_reg[i], mask,
+ i + A807_STREAM_ID_BASE);
+ }
+}
+
static void ap807_axi_attr_init(void)
{
uint32_t index, data;
@@ -265,6 +298,9 @@
/* configure CCU windows */
init_ccu(MVEBU_AP0);
+ /* Set the stream IDs for DMA masters */
+ ap807_stream_id_init();
+
/* configure the SMMU */
setup_smmu();
diff --git a/drivers/marvell/mochi/apn806_setup.c b/drivers/marvell/mochi/apn806_setup.c
index 8c3ba92..5c71fed 100644
--- a/drivers/marvell/mochi/apn806_setup.c
+++ b/drivers/marvell/mochi/apn806_setup.c
@@ -15,7 +15,7 @@
#include <drivers/marvell/mochi/ap_setup.h>
#include <lib/mmio.h>
-#include <mvebu_def.h>
+#include <a8k_plat_def.h>
#define SMMU_sACR (MVEBU_SMMU_BASE + 0x10)
#define SMMU_sACR_PG_64K (1 << 16)
@@ -67,6 +67,23 @@
#define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + \
0x4 * index)
+#define XOR_STREAM_ID_REG(ch) (MVEBU_REGS_BASE + 0x410010 + (ch) * 0x20000)
+#define XOR_STREAM_ID_MASK 0xFFFF
+#define SDIO_STREAM_ID_REG (MVEBU_RFU_BASE + 0x4600)
+#define SDIO_STREAM_ID_MASK 0xFF
+
+/* Do not use the default Stream ID 0 */
+#define A806_STREAM_ID_BASE (0x1)
+
+static uintptr_t stream_id_reg[] = {
+ XOR_STREAM_ID_REG(0),
+ XOR_STREAM_ID_REG(1),
+ XOR_STREAM_ID_REG(2),
+ XOR_STREAM_ID_REG(3),
+ SDIO_STREAM_ID_REG,
+ 0
+};
+
enum axi_attr {
AXI_SDIO_ATTR = 0,
AXI_DFX_ATTR,
@@ -158,6 +175,20 @@
MCI_REMAP_OFF_SHIFT);
}
+/* Set a unique stream id for all DMA capable devices */
+static void ap806_stream_id_init(void)
+{
+ int i;
+
+ for (i = 0; stream_id_reg[i] != 0; i++) {
+ uint32_t mask = stream_id_reg[i] == SDIO_STREAM_ID_REG ?
+ SDIO_STREAM_ID_MASK : XOR_STREAM_ID_MASK;
+
+ mmio_clrsetbits_32(stream_id_reg[i], mask,
+ i + A806_STREAM_ID_BASE);
+ }
+}
+
static void apn806_axi_attr_init(void)
{
uint32_t index, data;
@@ -236,6 +267,9 @@
/* configure DSS */
dss_setup();
+ /* Set the stream IDs for DMA masters */
+ ap806_stream_id_init();
+
/* configure the SMMU */
setup_smmu();
diff --git a/drivers/marvell/mochi/cp110_setup.c b/drivers/marvell/mochi/cp110_setup.c
index 0fa0497..f12da0e 100644
--- a/drivers/marvell/mochi/cp110_setup.c
+++ b/drivers/marvell/mochi/cp110_setup.c
@@ -12,7 +12,9 @@
#include <drivers/marvell/amb_adec.h>
#include <drivers/marvell/iob.h>
#include <drivers/marvell/mochi/cp110_setup.h>
+#include <drivers/rambus/trng_ip_76.h>
+#include <efuse_def.h>
#include <plat_marvell.h>
/*
@@ -105,6 +107,13 @@
#define MVEBU_RTC_READ_OUTPUT_DELAY_MASK 0xFFFF
#define MVEBU_RTC_READ_OUTPUT_DELAY_DEFAULT 0x1F
+/*******************************************************************************
+ * TRNG Configuration
+ ******************************************************************************/
+#define MVEBU_TRNG_BASE (0x760000)
+#define MVEBU_EFUSE_TRNG_ENABLE_EFUSE_WORD MVEBU_AP_LDX_220_189_EFUSE_OFFS
+#define MVEBU_EFUSE_TRNG_ENABLE_BIT_OFFSET 13 /* LD0[202] */
+
enum axi_attr {
AXI_ADUNIT_ATTR = 0,
AXI_COMUNIT_ATTR,
@@ -130,7 +139,7 @@
#define USB3H_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x10)
#define SATA_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x14)
#define SATA_1_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x18)
-#define SDIO_0_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x28)
+#define SDIO_STREAM_ID_REG (RFU_STREAM_ID_BASE + 0x28)
#define CP_DMA_0_STREAM_ID_REG (0x6B0010)
#define CP_DMA_1_STREAM_ID_REG (0x6D0010)
@@ -138,14 +147,14 @@
/* We allocate IDs 128-255 for PCIe */
#define MAX_STREAM_ID (0x80)
-uintptr_t stream_id_reg[] = {
+static uintptr_t stream_id_reg[] = {
USB3H_0_STREAM_ID_REG,
USB3H_1_STREAM_ID_REG,
CP_DMA_0_STREAM_ID_REG,
CP_DMA_1_STREAM_ID_REG,
SATA_0_STREAM_ID_REG,
SATA_1_STREAM_ID_REG,
- SDIO_0_STREAM_ID_REG,
+ SDIO_STREAM_ID_REG,
0
};
@@ -180,8 +189,9 @@
pcie0_clk = (reg & SAR_PCIE0_CLK_CFG_MASK) >> SAR_PCIE0_CLK_CFG_OFFSET;
pcie1_clk = (reg & SAR_PCIE1_CLK_CFG_MASK) >> SAR_PCIE1_CLK_CFG_OFFSET;
- /* CP110 revision A2 */
- if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A2) {
+ /* CP110 revision A2 or CN913x */
+ if (cp110_rev_id_get(base) == MVEBU_CP110_REF_ID_A2 ||
+ cp110_device_id_get(base) == MVEBU_CN9130_DEV_ID) {
/*
* PCIe Reference Clock Buffer Control register must be
* set according to the clock direction (input/output)
@@ -378,6 +388,36 @@
init_amb_adec(base);
}
+static void cp110_trng_init(uintptr_t base)
+{
+ static bool done;
+ int ret;
+ uint32_t reg_val, efuse;
+
+ /* Set access to LD0 */
+ reg_val = mmio_read_32(MVEBU_AP_EFUSE_SRV_CTRL_REG);
+ reg_val &= ~EFUSE_SRV_CTRL_LD_SELECT_MASK;
+ mmio_write_32(MVEBU_AP_EFUSE_SRV_CTRL_REG, reg_val);
+
+ /* Obtain the AP LD0 bit defining TRNG presence */
+ efuse = mmio_read_32(MVEBU_EFUSE_TRNG_ENABLE_EFUSE_WORD);
+ efuse >>= MVEBU_EFUSE_TRNG_ENABLE_BIT_OFFSET;
+ efuse &= 1;
+
+ if (efuse == 0) {
+ VERBOSE("TRNG is not present, skipping");
+ return;
+ }
+
+ if (!done) {
+ ret = eip76_rng_probe(base + MVEBU_TRNG_BASE);
+ if (ret != 0) {
+ ERROR("Failed to init TRNG @ 0x%lx\n", base);
+ return;
+ }
+ done = true;
+ }
+}
void cp110_init(uintptr_t cp110_base, uint32_t stream_id)
{
INFO("%s: Initialize CPx - base = %lx\n", __func__, cp110_base);
@@ -405,6 +445,9 @@
/* Reset RTC if needed */
cp110_rtc_init(cp110_base);
+
+ /* TRNG init - for CP0 only */
+ cp110_trng_init(cp110_base);
}
/* Do the minimal setup required to configure the CP in BLE */
diff --git a/drivers/marvell/secure_dfx_access/armada_thermal.c b/drivers/marvell/secure_dfx_access/armada_thermal.c
new file mode 100644
index 0000000..4f7191b
--- /dev/null
+++ b/drivers/marvell/secure_dfx_access/armada_thermal.c
@@ -0,0 +1,253 @@
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <errno.h>
+#include <lib/mmio.h>
+#include <mvebu.h>
+#include <stdbool.h>
+#include "dfx.h"
+
+/* #define DEBUG_DFX */
+#ifdef DEBUG_DFX
+#define debug(format...) NOTICE(format)
+#else
+#define debug(format, arg...)
+#endif
+
+#define TSEN_CTRL0 0xf06f8084
+ #define TSEN_CTRL0_START BIT(0)
+ #define TSEN_CTRL0_RESET BIT(1)
+ #define TSEN_CTRL0_ENABLE BIT(2)
+ #define TSEN_CTRL0_AVG_BYPASS BIT(6)
+ #define TSEN_CTRL0_CHAN_SHIFT 13
+ #define TSEN_CTRL0_CHAN_MASK 0xF
+ #define TSEN_CTRL0_OSR_SHIFT 24
+ #define TSEN_CTRL0_OSR_MAX 0x3
+ #define TSEN_CTRL0_MODE_SHIFT 30
+ #define TSEN_CTRL0_MODE_EXTERNAL 0x2U
+ #define TSEN_CTRL0_MODE_MASK 0x3U
+
+#define TSEN_CTRL1 0xf06f8088
+ #define TSEN_CTRL1_INT_EN BIT(25)
+ #define TSEN_CTRL1_HYST_SHIFT 19
+ #define TSEN_CTRL1_HYST_MASK (0x3 << TSEN_CTRL1_HYST_SHIFT)
+ #define TSEN_CTRL1_THRESH_SHIFT 3
+ #define TSEN_CTRL1_THRESH_MASK (0x3ff << TSEN_CTRL1_THRESH_SHIFT)
+
+#define TSEN_STATUS 0xf06f808c
+ #define TSEN_STATUS_VALID_OFFSET 16
+ #define TSEN_STATUS_VALID_MASK (0x1 << TSEN_STATUS_VALID_OFFSET)
+ #define TSEN_STATUS_TEMP_OUT_OFFSET 0
+ #define TSEN_STATUS_TEMP_OUT_MASK (0x3FF << TSEN_STATUS_TEMP_OUT_OFFSET)
+
+#define DFX_SERVER_IRQ_SUM_MASK_REG 0xf06f8104
+ #define DFX_SERVER_IRQ_EN BIT(1)
+
+#define DFX_IRQ_CAUSE_REG 0xf06f8108
+
+#define DFX_IRQ_MASK_REG 0xf06f810c
+ #define DFX_IRQ_TSEN_OVERHEAT_OFFSET BIT(22)
+
+#define THERMAL_SEN_OUTPUT_MSB 512
+#define THERMAL_SEN_OUTPUT_COMP 1024
+
+#define COEF_M 423
+#define COEF_B -150000LL
+
+static void armada_ap806_thermal_read(u_register_t *temp)
+{
+ uint32_t reg;
+
+ reg = mmio_read_32(TSEN_STATUS);
+
+ reg = ((reg & TSEN_STATUS_TEMP_OUT_MASK) >>
+ TSEN_STATUS_TEMP_OUT_OFFSET);
+
+ /*
+ * TSEN output format is signed as a 2s complement number
+ * ranging from-512 to +511. when MSB is set, need to
+ * calculate the complement number
+ */
+ if (reg >= THERMAL_SEN_OUTPUT_MSB)
+ reg -= THERMAL_SEN_OUTPUT_COMP;
+
+ *temp = ((COEF_M * ((signed int)reg)) - COEF_B);
+}
+
+static void armada_ap806_thermal_irq(void)
+{
+ /* Dummy read, register ROC */
+ mmio_read_32(DFX_IRQ_CAUSE_REG);
+}
+
+static void armada_ap806_thermal_overheat_irq_init(void)
+{
+ uint32_t reg;
+
+ /* Clear DFX temperature IRQ cause */
+ reg = mmio_read_32(DFX_IRQ_CAUSE_REG);
+
+ /* Enable DFX Temperature IRQ */
+ reg = mmio_read_32(DFX_IRQ_MASK_REG);
+ reg |= DFX_IRQ_TSEN_OVERHEAT_OFFSET;
+ mmio_write_32(DFX_IRQ_MASK_REG, reg);
+
+ /* Enable DFX server IRQ */
+ reg = mmio_read_32(DFX_SERVER_IRQ_SUM_MASK_REG);
+ reg |= DFX_SERVER_IRQ_EN;
+ mmio_write_32(DFX_SERVER_IRQ_SUM_MASK_REG, reg);
+
+ /* Enable overheat interrupt */
+ reg = mmio_read_32(TSEN_CTRL1);
+ reg |= TSEN_CTRL1_INT_EN;
+ mmio_write_32(TSEN_CTRL1, reg);
+}
+
+static unsigned int armada_mc_to_reg_temp(unsigned int temp_mc)
+{
+ unsigned int sample;
+
+ sample = (temp_mc + COEF_B) / COEF_M;
+
+ return sample & 0x3ff;
+}
+
+/*
+ * The documentation states:
+ * high/low watermark = threshold +/- 0.4761 * 2^(hysteresis + 2)
+ * which is the mathematical derivation for:
+ * 0x0 <=> 1.9°C, 0x1 <=> 3.8°C, 0x2 <=> 7.6°C, 0x3 <=> 15.2°C
+ */
+static unsigned int hyst_levels_mc[] = {1900, 3800, 7600, 15200};
+
+static unsigned int armada_mc_to_reg_hyst(int hyst_mc)
+{
+ int i;
+
+ /*
+ * We will always take the smallest possible hysteresis to avoid risking
+ * the hardware integrity by enlarging the threshold by +8°C in the
+ * worst case.
+ */
+ for (i = ARRAY_SIZE(hyst_levels_mc) - 1; i > 0; i--)
+ if (hyst_mc >= hyst_levels_mc[i])
+ break;
+
+ return i;
+}
+
+static void armada_ap806_thermal_threshold(int thresh_mc, int hyst_mc)
+{
+ uint32_t ctrl1;
+ unsigned int threshold = armada_mc_to_reg_temp(thresh_mc);
+ unsigned int hysteresis = armada_mc_to_reg_hyst(hyst_mc);
+
+ ctrl1 = mmio_read_32(TSEN_CTRL1);
+ /* Set Threshold */
+ if (thresh_mc >= 0) {
+ ctrl1 &= ~(TSEN_CTRL1_THRESH_MASK);
+ ctrl1 |= threshold << TSEN_CTRL1_THRESH_SHIFT;
+ }
+
+ /* Set Hysteresis */
+ if (hyst_mc >= 0) {
+ ctrl1 &= ~(TSEN_CTRL1_HYST_MASK);
+ ctrl1 |= hysteresis << TSEN_CTRL1_HYST_SHIFT;
+ }
+
+ mmio_write_32(TSEN_CTRL1, ctrl1);
+}
+
+static void armada_select_channel(int channel)
+{
+ uint32_t ctrl0;
+
+ /* Stop the measurements */
+ ctrl0 = mmio_read_32(TSEN_CTRL0);
+ ctrl0 &= ~TSEN_CTRL0_START;
+ mmio_write_32(TSEN_CTRL0, ctrl0);
+
+ /* Reset the mode, internal sensor will be automatically selected */
+ ctrl0 &= ~(TSEN_CTRL0_MODE_MASK << TSEN_CTRL0_MODE_SHIFT);
+
+ /* Other channels are external and should be selected accordingly */
+ if (channel) {
+ /* Change the mode to external */
+ ctrl0 |= TSEN_CTRL0_MODE_EXTERNAL <<
+ TSEN_CTRL0_MODE_SHIFT;
+ /* Select the sensor */
+ ctrl0 &= ~(TSEN_CTRL0_CHAN_MASK << TSEN_CTRL0_CHAN_SHIFT);
+ ctrl0 |= (channel - 1) << TSEN_CTRL0_CHAN_SHIFT;
+ }
+
+ /* Actually set the mode/channel */
+ mmio_write_32(TSEN_CTRL0, ctrl0);
+
+ /* Re-start the measurements */
+ ctrl0 |= TSEN_CTRL0_START;
+ mmio_write_32(TSEN_CTRL0, ctrl0);
+}
+
+static void armada_ap806_thermal_init(void)
+{
+ uint32_t reg;
+
+ reg = mmio_read_32(TSEN_CTRL0);
+ reg &= ~TSEN_CTRL0_RESET;
+ reg |= TSEN_CTRL0_START | TSEN_CTRL0_ENABLE;
+
+ /* Sample every ~2ms */
+ reg |= TSEN_CTRL0_OSR_MAX << TSEN_CTRL0_OSR_SHIFT;
+
+ /* Enable average (2 samples by default) */
+ reg &= ~TSEN_CTRL0_AVG_BYPASS;
+
+ mmio_write_32(TSEN_CTRL0, reg);
+
+ debug("thermal: Initialization done\n");
+}
+
+static void armada_is_valid(u_register_t *read)
+{
+ *read = (mmio_read_32(TSEN_STATUS) & TSEN_STATUS_VALID_MASK);
+}
+
+int mvebu_dfx_thermal_handle(u_register_t func, u_register_t *read,
+ u_register_t x2, u_register_t x3)
+{
+ debug_enter();
+
+ switch (func) {
+ case MV_SIP_DFX_THERMAL_INIT:
+ armada_ap806_thermal_init();
+ break;
+ case MV_SIP_DFX_THERMAL_READ:
+ armada_ap806_thermal_read(read);
+ break;
+ case MV_SIP_DFX_THERMAL_IRQ:
+ armada_ap806_thermal_irq();
+ break;
+ case MV_SIP_DFX_THERMAL_THRESH:
+ armada_ap806_thermal_threshold(x2, x3);
+ armada_ap806_thermal_overheat_irq_init();
+ break;
+ case MV_SIP_DFX_THERMAL_IS_VALID:
+ armada_is_valid(read);
+ break;
+ case MV_SIP_DFX_THERMAL_SEL_CHANNEL:
+ armada_select_channel(x2);
+ break;
+ default:
+ ERROR("unsupported dfx func\n");
+ return -EINVAL;
+ }
+
+ debug_exit();
+
+ return 0;
+}
diff --git a/drivers/marvell/secure_dfx_access/dfx.h b/drivers/marvell/secure_dfx_access/dfx.h
new file mode 100644
index 0000000..88c4de8
--- /dev/null
+++ b/drivers/marvell/secure_dfx_access/dfx.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+/* DFX sub-FID */
+#define MV_SIP_DFX_THERMAL_INIT 1
+#define MV_SIP_DFX_THERMAL_READ 2
+#define MV_SIP_DFX_THERMAL_IS_VALID 3
+#define MV_SIP_DFX_THERMAL_IRQ 4
+#define MV_SIP_DFX_THERMAL_THRESH 5
+#define MV_SIP_DFX_THERMAL_SEL_CHANNEL 6
+
+#define MV_SIP_DFX_SREAD 20
+#define MV_SIP_DFX_SWRITE 21
+
+int mvebu_dfx_thermal_handle(u_register_t func, u_register_t *read,
+ u_register_t x2, u_register_t x3);
+int mvebu_dfx_misc_handle(u_register_t func, u_register_t *read,
+ u_register_t addr, u_register_t val);
diff --git a/drivers/marvell/secure_dfx_access/misc_dfx.c b/drivers/marvell/secure_dfx_access/misc_dfx.c
new file mode 100644
index 0000000..189105f
--- /dev/null
+++ b/drivers/marvell/secure_dfx_access/misc_dfx.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright (C) 2021 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include "dfx.h"
+#include <mvebu_def.h>
+#include <mvebu.h>
+#include <errno.h>
+
+/* #define DEBUG_DFX */
+#ifdef DEBUG_DFX
+#define debug(format...) NOTICE(format)
+#else
+#define debug(format, arg...)
+#endif
+
+#define SAR_BASE (MVEBU_REGS_BASE + 0x6F8200)
+#define SAR_SIZE 0x4
+#define AP_DEV_ID_STATUS_REG (MVEBU_REGS_BASE + 0x6F8240)
+#define JTAG_DEV_ID_STATUS_REG (MVEBU_REGS_BASE + 0x6F8244)
+#define EFUSE_CTRL (MVEBU_REGS_BASE + 0x6F8008)
+#define EFUSE_LD_BASE (MVEBU_REGS_BASE + 0x6F8F00)
+#define EFUSE_LD_SIZE 0x1C
+#define EFUSE_HD_BASE (MVEBU_REGS_BASE + 0x6F9000)
+#define EFUSE_HD_SIZE 0x3F8
+
+/* AP806 CPU DFS register mapping*/
+#define AP806_CA72MP2_0_PLL_CR_0_BASE (MVEBU_REGS_BASE + 0x6F8278)
+#define AP806_CA72MP2_0_PLL_CR_1_BASE (MVEBU_REGS_BASE + 0x6F8280)
+#define AP806_CA72MP2_0_PLL_CR_2_BASE (MVEBU_REGS_BASE + 0x6F8284)
+#define AP806_CA72MP2_0_PLL_SR_BASE (MVEBU_REGS_BASE + 0x6F8C94)
+
+/* AP807 CPU DFS register mapping */
+#define AP807_DEVICE_GENERAL_CR_10_BASE (MVEBU_REGS_BASE + 0x6F8278)
+#define AP807_DEVICE_GENERAL_CR_11_BASE (MVEBU_REGS_BASE + 0x6F827C)
+#define AP807_DEVICE_GENERAL_STATUS_6_BASE (MVEBU_REGS_BASE + 0x6F8C98)
+
+#ifdef MVEBU_SOC_AP807
+ #define CLUSTER_OFFSET 0x8
+ #define CLK_DIVIDER_REG AP807_DEVICE_GENERAL_CR_10_BASE
+ #define CLK_FORCE_REG AP807_DEVICE_GENERAL_CR_11_BASE
+ #define CLK_RATIO_REG AP807_DEVICE_GENERAL_CR_11_BASE
+ #define CLK_RATIO_STATE_REG AP807_DEVICE_GENERAL_STATUS_6_BASE
+#else
+ #define CLUSTER_OFFSET 0x14
+ #define CLK_DIVIDER_REG AP806_CA72MP2_0_PLL_CR_0_BASE
+ #define CLK_FORCE_REG AP806_CA72MP2_0_PLL_CR_1_BASE
+ #define CLK_RATIO_REG AP806_CA72MP2_0_PLL_CR_2_BASE
+ #define CLK_RATIO_STATE_REG AP806_CA72MP2_0_PLL_SR_BASE
+#endif /* MVEBU_SOC_AP807 */
+
+static _Bool is_valid(u_register_t addr)
+{
+ switch (addr) {
+ case AP_DEV_ID_STATUS_REG:
+ case JTAG_DEV_ID_STATUS_REG:
+ case SAR_BASE ... (SAR_BASE + SAR_SIZE):
+ case EFUSE_LD_BASE ... (EFUSE_LD_BASE + EFUSE_LD_SIZE):
+ case EFUSE_HD_BASE ... (EFUSE_HD_BASE + EFUSE_HD_SIZE):
+ case EFUSE_CTRL:
+ /* cpu-clk related registers */
+ case CLK_DIVIDER_REG:
+ case CLK_DIVIDER_REG + CLUSTER_OFFSET:
+ case CLK_FORCE_REG:
+ case CLK_FORCE_REG + CLUSTER_OFFSET:
+#ifndef MVEBU_SOC_AP807
+ case CLK_RATIO_REG:
+ case CLK_RATIO_REG + CLUSTER_OFFSET:
+#endif
+ case CLK_RATIO_STATE_REG:
+ case CLK_RATIO_STATE_REG + CLUSTER_OFFSET:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static int armada_dfx_sread(u_register_t *read, u_register_t addr)
+{
+ if (!is_valid(addr))
+ return -EINVAL;
+
+ *read = mmio_read_32(addr);
+
+ return 0;
+}
+
+static int armada_dfx_swrite(u_register_t addr, u_register_t val)
+{
+ if (!is_valid(addr))
+ return -EINVAL;
+
+ mmio_write_32(addr, val);
+
+ return 0;
+}
+
+int mvebu_dfx_misc_handle(u_register_t func, u_register_t *read,
+ u_register_t addr, u_register_t val)
+{
+ debug_enter();
+
+ debug("func %ld, addr 0x%lx, val 0x%lx\n", func, addr, val);
+
+ switch (func) {
+ case MV_SIP_DFX_SREAD:
+ return armada_dfx_sread(read, addr);
+ case MV_SIP_DFX_SWRITE:
+ return armada_dfx_swrite(addr, val);
+ default:
+ ERROR("unsupported dfx misc sub-func\n");
+ return -EINVAL;
+ }
+
+ debug_exit();
+
+ return 0;
+}
diff --git a/drivers/marvell/uart/a3700_console.S b/drivers/marvell/uart/a3700_console.S
index 58dad7a..218fd86 100644
--- a/drivers/marvell/uart/a3700_console.S
+++ b/drivers/marvell/uart/a3700_console.S
@@ -45,25 +45,23 @@
cbz w2, init_fail
/* Program the baudrate */
- /* Divisor = Uart clock / (16 * baudrate) */
+ /* Divisor = Round(Uartclock / (16 * baudrate)) */
lsl w2, w2, #4
+ add w1, w1, w2, lsr #1
udiv w2, w1, w2
- and w2, w2, #0x3ff
+ and w2, w2, #0x3ff /* clear all other bits to use default clock */
- ldr w3, [x0, #UART_BAUD_REG]
- bic w3, w3, 0x3ff
- orr w3, w3, w2
- str w3, [x0, #UART_BAUD_REG]/* set baud rate divisor */
+ str w2, [x0, #UART_BAUD_REG]/* set baud rate divisor */
/* Set UART to default 16X scheme */
mov w3, #0
str w3, [x0, #UART_POSSR_REG]
/*
- * Wait for the TX (THR and TSR) to be empty. If wait for 20ms, the TX FIFO is
+ * Wait for the TX (THR and TSR) to be empty. If wait for 3ms, the TX FIFO is
* still not empty, TX FIFO will reset by all means.
*/
- mov w1, #20 /* max time out 20ms */
+ mov w1, #30 /* max time out 30 * 100 us */
2:
/* Check whether TX (THR and TSR) is empty */
ldr w3, [x0, #UART_STATUS_REG]
@@ -72,13 +70,13 @@
b.ne 4f
/* Delay */
- mov w2, #30000
+ mov w2, #60000 /* 60000 cycles of below 3 instructions on 1200 MHz CPU ~~ 100 us */
3:
sub w2, w2, #1
cmp w2, #0
b.ne 3b
- /* Check whether 10ms is waited */
+ /* Check whether wait timeout expired */
sub w1, w1, #1
cmp w1, #0
b.ne 2b
diff --git a/drivers/measured_boot/event_log.c b/drivers/measured_boot/event_log.c
index 727bdf5..0157b03 100644
--- a/drivers/measured_boot/event_log.c
+++ b/drivers/measured_boot/event_log.c
@@ -58,78 +58,48 @@
};
static const event2_header_t locality_event_header = {
- /*
- * All EV_NO_ACTION events SHALL set
- * TCG_PCR_EVENT2.pcrIndex = 0, unless otherwise specified
- */
- .pcr_index = PCR_0,
+ /*
+ * All EV_NO_ACTION events SHALL set
+ * TCG_PCR_EVENT2.pcrIndex = 0, unless otherwise specified
+ */
+ .pcr_index = PCR_0,
- /*
- * All EV_NO_ACTION events SHALL set
- * TCG_PCR_EVENT2.eventType = 03h
- */
- .event_type = EV_NO_ACTION,
+ /*
+ * All EV_NO_ACTION events SHALL set
+ * TCG_PCR_EVENT2.eventType = 03h
+ */
+ .event_type = EV_NO_ACTION,
- /*
- * All EV_NO_ACTION events SHALL set
- * TCG_PCR_EVENT2.digests to all
- * 0x00's for each allocated Hash algorithm
- */
- .digests = {
- .count = HASH_ALG_COUNT
- }
+ /*
+ * All EV_NO_ACTION events SHALL set TCG_PCR_EVENT2.digests to all
+ * 0x00's for each allocated Hash algorithm
+ */
+ .digests = {
+ .count = HASH_ALG_COUNT
+ }
};
-/* Platform's table with platform specific image IDs, names and PCRs */
-static const image_data_t plat_images_data[] = {
- { BL2_IMAGE_ID, BL2_STRING, PCR_0 }, /* Reserved for BL2 */
- { INVALID_ID, NULL, (unsigned int)(-1) } /* Terminator */
-};
-
-static const measured_boot_data_t plat_measured_boot_data = {
- plat_images_data,
- NULL, /* platform_set_nt_fw_info */
- NULL /* platform_set_tos_fw_info */
-};
-
-/*
- * Function retuns pointer to platform's measured_boot_data_t structure
- *
- * Must be overridden in the platform code
- */
-#pragma weak plat_get_measured_boot_data
-
-const measured_boot_data_t *plat_get_measured_boot_data(void)
-{
- return &plat_measured_boot_data;
-}
-
/*
* Add TCG_PCR_EVENT2 event
*
* @param[in] hash Pointer to hash data of TCG_DIGEST_SIZE bytes
* @param[in] image_ptr Pointer to image_data_t structure
- * @return:
- * 0 = success
- * < 0 = error code
+ *
+ * There must be room for storing this new event into the event log buffer.
*/
-static int add_event2(const uint8_t *hash, const image_data_t *image_ptr)
+static void add_event2(const uint8_t *hash, const image_data_t *image_ptr)
{
void *ptr = log_ptr;
uint32_t name_len;
- uint32_t size_of_event;
assert(image_ptr != NULL);
assert(image_ptr->name != NULL);
name_len = (uint32_t)strlen(image_ptr->name) + 1U;
- size_of_event = name_len + (uint32_t)EVENT2_HDR_SIZE;
/* Check for space in Event Log buffer */
- if (((uintptr_t)ptr + size_of_event) > EVENT_LOG_END) {
- ERROR("%s(): Event Log is short of memory", __func__);
- return -ENOMEM;
- }
+ assert(((uintptr_t)ptr + (uint32_t)EVENT2_HDR_SIZE + name_len) <=
+ EVENT_LOG_END);
/*
* As per TCG specifications, firmware components that are measured
@@ -156,12 +126,6 @@
/* TCG_PCR_EVENT2.Digests[].Digest[] */
ptr = (uint8_t *)((uintptr_t)ptr + offsetof(tpmt_ha, digest));
- /* Check for space in Event Log buffer */
- if (((uintptr_t)ptr + TCG_DIGEST_SIZE) > EVENT_LOG_END) {
- ERROR("%s(): Event Log is short of memory", __func__);
- return -ENOMEM;
- }
-
if (hash == NULL) {
/* Get BL2 hash from DTB */
bl2_plat_get_hash(ptr);
@@ -181,8 +145,6 @@
/* End of event data */
log_ptr = (uint8_t *)((uintptr_t)ptr +
offsetof(event2_data_t, event) + name_len);
-
- return 0;
}
/*
@@ -194,7 +156,6 @@
void event_log_init(void)
{
const char locality_signature[] = TCG_STARTUP_LOCALITY_SIGNATURE;
- const uint8_t *start_ptr;
void *ptr = event_log;
/* Get pointer to platform's measured_boot_data_t structure */
@@ -221,11 +182,6 @@
((id_event_struct_data_t *)ptr)->vendor_info_size = 0;
ptr = (uint8_t *)((uintptr_t)ptr +
offsetof(id_event_struct_data_t, vendor_info));
- if ((uintptr_t)ptr != ((uintptr_t)event_log + ID_EVENT_SIZE)) {
- panic();
- }
-
- start_ptr = (uint8_t *)ptr;
/*
* The Startup Locality event should be placed in the log before
@@ -262,16 +218,11 @@
*/
((startup_locality_event_t *)ptr)->startup_locality = 0U;
ptr = (uint8_t *)((uintptr_t)ptr + sizeof(startup_locality_event_t));
- if ((uintptr_t)ptr != ((uintptr_t)start_ptr + LOC_EVENT_SIZE)) {
- panic();
- }
log_ptr = (uint8_t *)ptr;
/* Add BL2 event */
- if (add_event2(NULL, plat_data_ptr->images_data) != 0) {
- panic();
- }
+ add_event2(NULL, plat_data_ptr->images_data);
}
/*
@@ -292,14 +243,11 @@
unsigned char hash_data[MBEDTLS_MD_MAX_SIZE];
int rc;
- /* Check if image_id is supported */
- while (data_ptr->id != data_id) {
- if ((data_ptr++)->id == INVALID_ID) {
- ERROR("%s(): image_id %u not supported\n",
- __func__, data_id);
- return -EINVAL;
- }
+ /* Get the metadata associated with this image. */
+ while ((data_ptr->id != INVALID_ID) && (data_ptr->id != data_id)) {
+ data_ptr++;
}
+ assert(data_ptr->id != INVALID_ID);
if (data_id == TOS_FW_CONFIG_ID) {
tos_fw_config_base = data_base;
@@ -316,7 +264,8 @@
return rc;
}
- return add_event2(hash_data, data_ptr);
+ add_event2(hash_data, data_ptr);
+ return 0;
}
/*
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index b5f6a10..c327e71 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -105,6 +105,36 @@
return MMC_GET_STATE(resp_data[0]);
}
+static int mmc_send_part_switch_cmd(unsigned int part_config)
+{
+ int ret;
+ unsigned int part_time = 0;
+
+ ret = mmc_send_cmd(MMC_CMD(6),
+ EXTCSD_WRITE_BYTES |
+ EXTCSD_CMD(CMD_EXTCSD_PARTITION_CONFIG) |
+ EXTCSD_VALUE(part_config) |
+ EXTCSD_CMD_SET_NORMAL,
+ MMC_RESPONSE_R1B, NULL);
+ if (ret != 0) {
+ return ret;
+ }
+
+ /* Partition switch timing is in 10ms units */
+ part_time = mmc_ext_csd[CMD_EXTCSD_PART_SWITCH_TIME] * 10;
+
+ mdelay(part_time);
+
+ do {
+ ret = mmc_device_state();
+ if (ret < 0) {
+ return ret;
+ }
+ } while (ret == MMC_STATE_PRG);
+
+ return 0;
+}
+
static int mmc_set_ext_csd(unsigned int ext_cmd, unsigned int value)
{
int ret;
@@ -392,7 +422,7 @@
ret = mmc_reset_to_idle();
if (ret != 0) {
return ret;
- };
+ }
for (n = 0; n < SEND_OP_COND_MAX_RETRIES; n++) {
ret = mmc_send_cmd(MMC_CMD(1), OCR_SECTOR_MODE |
@@ -425,7 +455,7 @@
ret = mmc_reset_to_idle();
if (ret != 0) {
return ret;
- };
+ }
if (mmc_dev_info->mmc_dev_type == MMC_IS_EMMC) {
ret = mmc_send_op_cond();
@@ -668,7 +698,7 @@
{
mmc_set_ext_csd(CMD_EXTCSD_PARTITION_CONFIG,
PART_CFG_BOOT_PARTITION1_ENABLE |
- PART_CFG_PARTITION1_ACCESS);
+ PART_CFG_BOOT_PARTITION1_ACCESS);
}
static inline void mmc_rpmb_disable(void)
@@ -710,6 +740,50 @@
return size_erased;
}
+static int mmc_part_switch(unsigned int part_type)
+{
+ uint8_t part_config = mmc_ext_csd[CMD_EXTCSD_PARTITION_CONFIG];
+
+ part_config &= ~EXT_CSD_PART_CONFIG_ACC_MASK;
+ part_config |= part_type;
+
+ return mmc_send_part_switch_cmd(part_config);
+}
+
+static unsigned char mmc_current_boot_part(void)
+{
+ return PART_CFG_CURRENT_BOOT_PARTITION(mmc_ext_csd[CMD_EXTCSD_PARTITION_CONFIG]);
+}
+
+size_t mmc_boot_part_read_blocks(int lba, uintptr_t buf, size_t size)
+{
+ size_t size_read;
+ int ret;
+ unsigned char current_boot_part = mmc_current_boot_part();
+
+ if (current_boot_part != 1U &&
+ current_boot_part != 2U) {
+ ERROR("Got unexpected value for active boot partition, %u\n", current_boot_part);
+ return 0;
+ }
+
+ ret = mmc_part_switch(current_boot_part);
+ if (ret < 0) {
+ ERROR("Failed to switch to boot partition, %d\n", ret);
+ return 0;
+ }
+
+ size_read = mmc_read_blocks(lba, buf, size);
+
+ ret = mmc_part_switch(0);
+ if (ret < 0) {
+ ERROR("Failed to switch back to user partition, %d\n", ret);
+ return 0;
+ }
+
+ return size_read;
+}
+
int mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk,
unsigned int width, unsigned int flags,
struct mmc_device_info *device_info)
diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c
index 44b001e..9f0331a 100644
--- a/drivers/mtd/nand/core.c
+++ b/drivers/mtd/nand/core.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -112,6 +112,47 @@
return 0;
}
+int nand_seek_bb(uintptr_t base, unsigned int offset, size_t *extra_offset)
+{
+ unsigned int block;
+ unsigned int offset_block;
+ unsigned int max_block;
+ int is_bad;
+ size_t count_bb = 0U;
+
+ block = base / nand_dev.block_size;
+
+ if (offset != 0U) {
+ offset_block = (base + offset - 1U) / nand_dev.block_size;
+ } else {
+ offset_block = block;
+ }
+
+ max_block = nand_dev.size / nand_dev.block_size;
+
+ while (block <= offset_block) {
+ if (offset_block >= max_block) {
+ return -EIO;
+ }
+
+ is_bad = nand_dev.mtd_block_is_bad(block);
+ if (is_bad < 0) {
+ return is_bad;
+ }
+
+ if (is_bad == 1) {
+ count_bb++;
+ offset_block++;
+ }
+
+ block++;
+ }
+
+ *extra_offset = count_bb * nand_dev.block_size;
+
+ return 0;
+}
+
struct nand_device *get_nand_device(void)
{
return &nand_dev;
diff --git a/drivers/mtd/nor/spi_nor.c b/drivers/mtd/nor/spi_nor.c
index 108f893..6b4643e 100644
--- a/drivers/mtd/nor/spi_nor.c
+++ b/drivers/mtd/nor/spi_nor.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -103,7 +103,7 @@
0 : 1;
}
- return (((sr & SR_WIP) != 0U) ? 1 : 0);
+ return (((sr & SR_WIP) == 0U) ? 0 : 1);
}
static int spi_nor_wait_ready(void)
@@ -131,7 +131,7 @@
return ret;
}
- if ((sr & SR_QUAD_EN_MX) == 0U) {
+ if ((sr & SR_QUAD_EN_MX) != 0U) {
return 0;
}
@@ -141,7 +141,7 @@
}
sr |= SR_QUAD_EN_MX;
- ret = spi_nor_reg(SPI_NOR_OP_WRSR, &sr, 1, SPI_MEM_DATA_OUT);
+ ret = spi_nor_reg(SPI_NOR_OP_WRSR, &sr, 1U, SPI_MEM_DATA_OUT);
if (ret != 0) {
return ret;
}
@@ -168,7 +168,7 @@
return ret;
}
- ret = spi_nor_reg(SPI_NOR_OP_WRSR, sr_cr, 2, SPI_MEM_DATA_OUT);
+ ret = spi_nor_reg(SPI_NOR_OP_WRSR, sr_cr, 2U, SPI_MEM_DATA_OUT);
if (ret != 0) {
return -EINVAL;
}
@@ -230,7 +230,7 @@
}
return spi_nor_reg(nor_dev.bank_write_cmd, &nor_dev.selected_bank,
- 1, SPI_MEM_DATA_OUT);
+ 1U, SPI_MEM_DATA_OUT);
}
static int spi_nor_write_bar(uint32_t offset)
@@ -248,7 +248,7 @@
}
ret = spi_nor_reg(nor_dev.bank_write_cmd, &selected_bank,
- 1, SPI_MEM_DATA_OUT);
+ 1U, SPI_MEM_DATA_OUT);
if (ret != 0) {
return ret;
}
@@ -260,11 +260,11 @@
static int spi_nor_read_bar(void)
{
- uint8_t selected_bank = 0;
+ uint8_t selected_bank = 0U;
int ret;
ret = spi_nor_reg(nor_dev.bank_read_cmd, &selected_bank,
- 1, SPI_MEM_DATA_IN);
+ 1U, SPI_MEM_DATA_IN);
if (ret != 0) {
return ret;
}
@@ -280,7 +280,7 @@
size_t remain_len;
int ret;
- *length_read = 0;
+ *length_read = 0U;
nor_dev.read_op.addr.val = offset;
nor_dev.read_op.data.buf = (void *)buffer;
@@ -324,7 +324,7 @@
int spi_nor_init(unsigned long long *size, unsigned int *erase_size)
{
- int ret = 0;
+ int ret;
uint8_t id;
/* Default read command used */
@@ -339,7 +339,7 @@
return -EINVAL;
}
- assert(nor_dev.size != 0);
+ assert(nor_dev.size != 0U);
if (nor_dev.size > BANK_SIZE) {
nor_dev.flags |= SPI_NOR_USE_BANK;
diff --git a/drivers/nxp/auth/csf_hdr_parser/cot.c b/drivers/nxp/auth/csf_hdr_parser/cot.c
new file mode 100644
index 0000000..4502ed6
--- /dev/null
+++ b/drivers/nxp/auth/csf_hdr_parser/cot.c
@@ -0,0 +1,284 @@
+/*
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+
+#include <drivers/auth/auth_mod.h>
+
+#if USE_TBBR_DEFS
+#include <tools_share/tbbr_oid.h>
+#else
+#include <platform_oid.h>
+#endif
+
+
+static auth_param_type_desc_t sig = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_SIG, 0);
+static auth_param_type_desc_t sig_alg = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_SIG_ALG, 0);
+static auth_param_type_desc_t sig_hash = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_HASH, 0);
+
+static auth_param_type_desc_t non_trusted_world_pk = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_PUB_KEY, NON_TRUSTED_WORLD_PK_OID);
+
+/*
+ * TBBR Chain of trust definition
+ */
+static const auth_img_desc_t bl31_image = {
+ .img_id = BL31_IMAGE_ID,
+ .img_type = IMG_PLAT,
+ .parent = NULL,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &non_trusted_world_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &sig_hash
+ }
+ }
+ }
+};
+static const auth_img_desc_t scp_bl2_image = {
+ .img_id = SCP_BL2_IMAGE_ID,
+ .img_type = IMG_PLAT,
+ .parent = NULL,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &non_trusted_world_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &sig_hash
+ }
+ }
+ }
+};
+static const auth_img_desc_t bl32_image = {
+ .img_id = BL32_IMAGE_ID,
+ .img_type = IMG_PLAT,
+ .parent = NULL,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &non_trusted_world_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &sig_hash
+ }
+ }
+ }
+};
+static const auth_img_desc_t bl33_image = {
+ .img_id = BL33_IMAGE_ID,
+ .img_type = IMG_PLAT,
+ .parent = NULL,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &non_trusted_world_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &sig_hash
+ }
+ }
+ }
+};
+#ifdef POLICY_FUSE_PROVISION
+static const auth_img_desc_t fuse_prov_img = {
+ .img_id = FUSE_PROV_IMAGE_ID,
+ .img_type = IMG_PLAT,
+ .parent = NULL,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &non_trusted_world_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &sig_hash
+ }
+ }
+ }
+};
+static const auth_img_desc_t fuse_upgrade_img = {
+ .img_id = FUSE_UP_IMAGE_ID,
+ .img_type = IMG_PLAT,
+ .parent = NULL,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &non_trusted_world_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &sig_hash
+ }
+ }
+ }
+};
+#endif
+#ifdef CONFIG_DDR_FIP_IMAGE
+static const auth_img_desc_t ddr_imem_udimm_1d_img = {
+ .img_id = DDR_IMEM_UDIMM_1D_IMAGE_ID,
+ .img_type = IMG_PLAT,
+ .parent = NULL,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &non_trusted_world_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &sig_hash
+ }
+ }
+ }
+};
+static const auth_img_desc_t ddr_imem_udimm_2d_img = {
+ .img_id = DDR_IMEM_UDIMM_2D_IMAGE_ID,
+ .img_type = IMG_PLAT,
+ .parent = NULL,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &non_trusted_world_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &sig_hash
+ }
+ }
+ }
+};
+static const auth_img_desc_t ddr_dmem_udimm_1d_img = {
+ .img_id = DDR_DMEM_UDIMM_1D_IMAGE_ID,
+ .img_type = IMG_PLAT,
+ .parent = NULL,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &non_trusted_world_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &sig_hash
+ }
+ }
+ }
+};
+static const auth_img_desc_t ddr_dmem_udimm_2d_img = {
+ .img_id = DDR_DMEM_UDIMM_2D_IMAGE_ID,
+ .img_type = IMG_PLAT,
+ .parent = NULL,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &non_trusted_world_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &sig_hash
+ }
+ }
+ }
+};
+static const auth_img_desc_t ddr_imem_rdimm_1d_img = {
+ .img_id = DDR_IMEM_RDIMM_1D_IMAGE_ID,
+ .img_type = IMG_PLAT,
+ .parent = NULL,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &non_trusted_world_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &sig_hash
+ }
+ }
+ }
+};
+static const auth_img_desc_t ddr_imem_rdimm_2d_img = {
+ .img_id = DDR_IMEM_RDIMM_2D_IMAGE_ID,
+ .img_type = IMG_PLAT,
+ .parent = NULL,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &non_trusted_world_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &sig_hash
+ }
+ }
+ }
+};
+static const auth_img_desc_t ddr_dmem_rdimm_1d_img = {
+ .img_id = DDR_DMEM_RDIMM_1D_IMAGE_ID,
+ .img_type = IMG_PLAT,
+ .parent = NULL,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &non_trusted_world_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &sig_hash
+ }
+ }
+ }
+};
+static const auth_img_desc_t ddr_dmem_rdimm_2d_img = {
+ .img_id = DDR_DMEM_RDIMM_2D_IMAGE_ID,
+ .img_type = IMG_PLAT,
+ .parent = NULL,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &non_trusted_world_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &sig_hash
+ }
+ }
+ }
+};
+#endif
+
+static const auth_img_desc_t * const cot_desc[] = {
+ [BL31_IMAGE_ID] = &bl31_image,
+ [SCP_BL2_IMAGE_ID] = &scp_bl2_image,
+ [BL32_IMAGE_ID] = &bl32_image,
+ [BL33_IMAGE_ID] = &bl33_image,
+#ifdef POLICY_FUSE_PROVISION
+ [FUSE_PROV_IMAGE_ID] = &fuse_prov_img,
+ [FUSE_UP_IMAGE_ID] = &fuse_upgrade_img,
+#endif
+#ifdef CONFIG_DDR_FIP_IMAGE
+ [DDR_IMEM_UDIMM_1D_IMAGE_ID] = &ddr_imem_udimm_1d_img,
+ [DDR_IMEM_UDIMM_2D_IMAGE_ID] = &ddr_imem_udimm_2d_img,
+ [DDR_DMEM_UDIMM_1D_IMAGE_ID] = &ddr_dmem_udimm_1d_img,
+ [DDR_DMEM_UDIMM_2D_IMAGE_ID] = &ddr_dmem_udimm_2d_img,
+ [DDR_IMEM_RDIMM_1D_IMAGE_ID] = &ddr_imem_rdimm_1d_img,
+ [DDR_IMEM_RDIMM_2D_IMAGE_ID] = &ddr_imem_rdimm_2d_img,
+ [DDR_DMEM_RDIMM_1D_IMAGE_ID] = &ddr_dmem_rdimm_1d_img,
+ [DDR_DMEM_RDIMM_2D_IMAGE_ID] = &ddr_dmem_rdimm_2d_img,
+#endif
+};
+
+/* Register the CoT in the authentication module */
+REGISTER_COT(cot_desc);
diff --git a/drivers/nxp/auth/csf_hdr_parser/csf_hdr.mk b/drivers/nxp/auth/csf_hdr_parser/csf_hdr.mk
new file mode 100644
index 0000000..1af51f8
--- /dev/null
+++ b/drivers/nxp/auth/csf_hdr_parser/csf_hdr.mk
@@ -0,0 +1,64 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+
+CSF_HDR_SOURCES := $(PLAT_DRIVERS_PATH)/auth/csf_hdr_parser/csf_hdr_parser.c
+
+CSF_HDR_SOURCES += $(PLAT_DRIVERS_PATH)/auth/csf_hdr_parser/plat_img_parser.c
+
+PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLUDE_PATH)/auth/csf_hdr_parser/
+
+$(eval $(call add_define, CSF_HEADER_PREPENDED))
+
+
+# Path to CST directory is required to generate the CSF header
+# and prepend it to image before fip image gets generated
+ifeq (${CST_DIR},)
+ $(error Error: CST_DIR not set)
+endif
+
+# Rules are created for generating and appending CSF header to images before
+# FIT image generation
+
+# CST_BL31
+define CST_BL31_RULE
+$(1): $(2)
+ @echo " Generating CSF Header for $$@ $$<"
+ $(Q)$(CST_DIR)/create_hdr_esbc --in $(2) --out $(1) --app_off ${CSF_HDR_SZ} \
+ --app $(2) ${BL31_INPUT_FILE}
+endef
+
+CST_BL31_SUFFIX := .cst
+
+# CST_BL32
+define CST_BL32_RULE
+$(1): $(2)
+ @echo " Generating CSF Header for $$@ $$<"
+ $(Q)$(CST_DIR)/create_hdr_esbc --in $(2) --out $(1) --app_off ${CSF_HDR_SZ} \
+ --app $(2) ${BL32_INPUT_FILE}
+endef
+
+CST_BL32_SUFFIX := .cst
+
+# CST_BL33
+define CST_BL33_RULE
+$(1): $(2)
+ @echo " Generating CSF Header for $$@ $$<"
+ $(Q)$(CST_DIR)/create_hdr_esbc --in $(2) --out $(1) --app_off ${CSF_HDR_SZ} \
+ --app $(2) ${BL33_INPUT_FILE}
+endef
+
+CST_BL33_SUFFIX := .cst
+
+# CST_SCP_BL2
+define CST_SCP_BL2_RULE
+$(1): $(2)
+ @echo " Generating CSF Header for $$@ $$<"
+ $(Q)$(CST_DIR)/create_hdr_esbc --in $(2) --out $(1) --app_off ${CSF_HDR_SZ} \
+ --app $(2) ${FUSE_INPUT_FILE}
+endef
+
+CST_SCP_BL2_SUFFIX := .cst
diff --git a/drivers/nxp/auth/csf_hdr_parser/csf_hdr_parser.c b/drivers/nxp/auth/csf_hdr_parser/csf_hdr_parser.c
new file mode 100644
index 0000000..b878082
--- /dev/null
+++ b/drivers/nxp/auth/csf_hdr_parser/csf_hdr_parser.c
@@ -0,0 +1,365 @@
+/*
+ * Copyright (c) 2014-2016, Freescale Semiconductor, Inc.
+ * Copyright 2017-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <assert.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <arch_helpers.h>
+#include <cassert.h>
+#include <common/debug.h>
+#include <csf_hdr.h>
+#include <dcfg.h>
+#include <drivers/auth/crypto_mod.h>
+#include <lib/utils.h>
+#include <sfp.h>
+
+/* Maximum OID string length ("a.b.c.d.e.f ...") */
+#define MAX_OID_STR_LEN 64
+
+#define LIB_NAME "NXP CSFv2"
+
+#ifdef CSF_HDR_CH3
+/* Barker Code for LS Ch3 ESBC Header */
+static const uint8_t barker_code[CSF_BARKER_LEN] = { 0x12, 0x19, 0x20, 0x01 };
+#else
+static const uint8_t barker_code[CSF_BARKER_LEN] = { 0x68, 0x39, 0x27, 0x81 };
+#endif
+
+#define CHECK_KEY_LEN(key_len) (((key_len) == 2 * RSA_1K_KEY_SZ_BYTES) || \
+ ((key_len) == 2 * RSA_2K_KEY_SZ_BYTES) || \
+ ((key_len) == 2 * RSA_4K_KEY_SZ_BYTES))
+
+/* Flag to indicate if values are there in rotpk_hash_table */
+bool rotpk_not_dpld = true;
+uint8_t rotpk_hash_table[MAX_KEY_ENTRIES][SHA256_BYTES];
+uint32_t num_rotpk_hash_entries;
+
+/*
+ * This function deploys the hashes of the various platform keys in
+ * rotpk_hash_table. This is done in case of secure boot after comparison
+ * of table's hash with the hash in SFP fuses. This installation is done
+ * only in the first header parsing.
+ */
+static int deploy_rotpk_hash_table(void *srk_buffer, uint16_t num_srk)
+{
+ void *ctx;
+ int ret = 0;
+ int i, j = 0;
+ unsigned int digest_size = SHA256_BYTES;
+ enum hash_algo algo = SHA256;
+ uint8_t hash[SHA256_BYTES];
+ uint32_t srk_hash[SHA256_BYTES/4] __aligned(CACHE_WRITEBACK_GRANULE);
+ struct srk_table *srktbl = (void *)srk_buffer;
+ struct sfp_ccsr_regs_t *sfp_ccsr_regs = (void *)(get_sfp_addr()
+ + SFP_FUSE_REGS_OFFSET);
+
+
+ if (num_srk > MAX_KEY_ENTRIES) {
+ return -1;
+ }
+
+ ret = hash_init(algo, &ctx);
+ if (ret != 0) {
+ return -1;
+ }
+
+ /* Update hash with that of SRK table */
+ ret = hash_update(algo, ctx, (uint8_t *)((uint8_t *)srk_buffer),
+ num_srk * sizeof(struct srk_table));
+ if (ret != 0) {
+ return -1;
+ }
+
+ /* Copy hash at destination buffer */
+ ret = hash_final(algo, ctx, hash, digest_size);
+ if (ret != 0) {
+ return -1;
+ }
+
+ /* Add comparison of hash with SFP hash here */
+ for (i = 0; i < SHA256_BYTES/4; i++) {
+ srk_hash[i] =
+ mmio_read_32((uintptr_t)&sfp_ccsr_regs->srk_hash[i]);
+ }
+
+ VERBOSE("SRK table HASH\n");
+ for (i = 0; i < 8; i++) {
+ VERBOSE("%x\n", *((uint32_t *)hash + i));
+ }
+
+ if (memcmp(hash, srk_hash, SHA256_BYTES) != 0) {
+ ERROR("Error in installing ROTPK table\n");
+ ERROR("SRK hash doesn't match the fuse hash\n");
+ return -1;
+ }
+
+ /* Hash table already deployed */
+ if (rotpk_not_dpld == false) {
+ return 0;
+ }
+
+ for (i = 0; i < num_srk; i++) {
+ ret = hash_init(algo, &ctx);
+ if (ret != 0) {
+ return -1;
+ }
+
+ /* Update hash with that of SRK table */
+ ret = hash_update(algo, ctx, srktbl[i].pkey, srktbl[i].key_len);
+ if (ret != 0) {
+ return -1;
+ }
+
+ /* Copy hash at destination buffer */
+ ret = hash_final(algo, ctx, rotpk_hash_table[i], digest_size);
+ if (ret != 0) {
+ return -1;
+ }
+ VERBOSE("Table key %d HASH\n", i);
+ for (j = 0; j < 8; j++) {
+ VERBOSE("%x\n", *((uint32_t *)rotpk_hash_table[i] + j));
+ }
+ }
+ rotpk_not_dpld = false;
+ num_rotpk_hash_entries = num_srk;
+
+ return 0;
+}
+
+/*
+ * Calculate hash of ESBC hdr and ESBC. This function calculates the
+ * single hash of ESBC header and ESBC image
+ */
+int calc_img_hash(struct csf_hdr *hdr,
+ void *img_addr, uint32_t img_size,
+ uint8_t *img_hash, uint32_t *hash_len)
+{
+ void *ctx;
+ int ret = 0;
+ unsigned int digest_size = SHA256_BYTES;
+ enum hash_algo algo = SHA256;
+
+ ret = hash_init(algo, &ctx);
+ /* Copy hash at destination buffer */
+ if (ret != 0) {
+ return -1;
+ }
+
+ /* Update hash for CSF Header */
+ ret = hash_update(algo, ctx, (uint8_t *)hdr, sizeof(struct csf_hdr));
+ if (ret != 0) {
+ return -1;
+ }
+
+ /* Update hash with that of SRK table */
+ ret = hash_update(algo, ctx,
+ (uint8_t *)((uint8_t *)hdr + hdr->srk_tbl_off),
+ hdr->len_kr.num_srk * sizeof(struct srk_table));
+ if (ret != 0) {
+ return -1;
+ }
+
+ /* Update hash for actual Image */
+ ret = hash_update(algo, ctx, (uint8_t *)(img_addr), img_size);
+ if (ret != 0) {
+ return -1;
+ }
+
+ /* Copy hash at destination buffer */
+ ret = hash_final(algo, ctx, img_hash, digest_size);
+ if (ret != 0) {
+ return -1;
+ }
+
+ *hash_len = digest_size;
+
+ VERBOSE("IMG encoded HASH\n");
+ for (int i = 0; i < 8; i++) {
+ VERBOSE("%x\n", *((uint32_t *)img_hash + i));
+ }
+
+ return 0;
+}
+
+/* This function checks if selected key is revoked or not.*/
+static uint32_t is_key_revoked(uint32_t keynum, uint32_t rev_flag)
+{
+ if (keynum == UNREVOCABLE_KEY) {
+ return 0;
+ }
+
+ if (((uint32_t)(1 << (REVOC_KEY_ALIGN - keynum)) & rev_flag) != 0) {
+ return 1;
+ }
+
+ return 0;
+}
+
+/* Parse the header to extract the type of key,
+ * Check if key is not revoked
+ * and return the key , key length and key_type
+ */
+static int32_t get_key(struct csf_hdr *hdr, uint8_t **key, uint32_t *len,
+ enum sig_alg *key_type)
+{
+ int i = 0;
+ uint32_t ret = 0U;
+ uint32_t key_num, key_revoc_flag;
+ void *esbc = hdr;
+ struct srk_table *srktbl = (void *)((uint8_t *)esbc + hdr->srk_tbl_off);
+ bool sb;
+ uint32_t mode;
+
+ /* We currently support only RSA keys and signature */
+ *key_type = RSA;
+
+ /* Check for number of SRK entries */
+ if ((hdr->len_kr.num_srk == 0) ||
+ (hdr->len_kr.num_srk > MAX_KEY_ENTRIES)) {
+ ERROR("Error in NUM entries in SRK Table\n");
+ return -1;
+ }
+
+ /*
+ * Check the key number field. It should be not greater than
+ * number of entries in SRK table.
+ */
+ key_num = hdr->len_kr.srk_sel;
+ if ((key_num == 0) || (key_num > hdr->len_kr.num_srk)) {
+ ERROR("Invalid Key number\n");
+ return -1;
+ }
+
+ /* Get revoc key from sfp */
+ key_revoc_flag = get_key_revoc();
+
+ /* Check if selected key has been revoked */
+ ret = is_key_revoked(key_num, key_revoc_flag);
+ if (ret != 0) {
+ ERROR("Selected key has been revoked\n");
+ return -1;
+ }
+
+ /* Check for valid key length - allowed key sized 1k, 2k and 4K */
+ for (i = 0; i < hdr->len_kr.num_srk; i++) {
+ if (CHECK_KEY_LEN(srktbl[i].key_len) == 0) {
+ ERROR("Invalid key length\n");
+ return -1;
+ }
+ }
+
+ /* We don't return error from here. While parsing we just try to
+ * install the srk table. Failure needs to be taken care of in
+ * case of secure boot. This failure will be handled at the time
+ * of rotpk comparison in plat_get_rotpk_info function
+ */
+ sb = check_boot_mode_secure(&mode);
+ if (sb) {
+ ret = deploy_rotpk_hash_table(srktbl, hdr->len_kr.num_srk);
+ if (ret != 0) {
+ ERROR("ROTPK FAILURE\n");
+ /* For ITS =1 , return failure */
+ if (mode != 0) {
+ return -1;
+ }
+ ERROR("SECURE BOOT DEV-ENV MODE:\n");
+ ERROR("\tCHECK ROTPK !\n");
+ ERROR("\tCONTINUING ON FAILURE...\n");
+ }
+ }
+
+ /* Return the length of the selected key */
+ *len = srktbl[key_num - 1].key_len;
+
+ /* Point key to the selected key */
+ *key = (uint8_t *)&(srktbl[key_num - 1].pkey);
+
+ return 0;
+}
+
+/*
+ * This function would parse the CSF header and do the following:
+ * 1. Basic integrity checks
+ * 2. Key checks and extract the key from SRK/IE Table
+ * 3. Key hash comparison with SRKH in fuses in case of SRK Table
+ * 4. OEM/UID checks - To be added
+ * 5. Hash calculation for various components used in signature
+ * 6. Signature integrity checks
+ * return -> 0 on success, -1 on failure
+ */
+int validate_esbc_header(void *img_hdr, void **img_key, uint32_t *key_len,
+ void **img_sign, uint32_t *sign_len,
+ enum sig_alg *algo)
+{
+ struct csf_hdr *hdr = img_hdr;
+ uint8_t *s;
+ int32_t ret = 0;
+ void *esbc = (uint8_t *)img_hdr;
+ uint8_t *key;
+ uint32_t klen;
+
+ /* check barker code */
+ if (memcmp(hdr->barker, barker_code, CSF_BARKER_LEN) != 0) {
+ ERROR("Wrong barker code in header\n");
+ return -1;
+ }
+
+ ret = get_key(hdr, &key, &klen, algo);
+ if (ret != 0) {
+ return -1;
+ }
+
+ /* check signaure */
+ if (klen == (2 * hdr->sign_len)) {
+ /* check signature length */
+ if (((hdr->sign_len == RSA_1K_KEY_SZ_BYTES) ||
+ (hdr->sign_len == RSA_2K_KEY_SZ_BYTES) ||
+ (hdr->sign_len == RSA_4K_KEY_SZ_BYTES)) == 0) {
+ ERROR("Wrong Signature length in header\n");
+ return -1;
+ }
+ } else {
+ ERROR("RSA key length not twice the signature length\n");
+ return -1;
+ }
+
+ /* modulus most significant bit should be set */
+
+ if ((key[0] & 0x80) == 0U) {
+ ERROR("RSA Public key MSB not set\n");
+ return -1;
+ }
+
+ /* modulus value should be odd */
+ if ((key[klen / 2 - 1] & 0x1) == 0U) {
+ ERROR("Public key Modulus in header not odd\n");
+ return -1;
+ }
+
+ /* Check signature value < modulus value */
+ s = (uint8_t *)(esbc + hdr->psign);
+
+ if (!(memcmp(s, key, hdr->sign_len) < 0)) {
+ ERROR("Signature not less than modulus");
+ return -1;
+ }
+
+ /* Populate the return addresses */
+ *img_sign = (void *)(s);
+
+ /* Save the length of signature */
+ *sign_len = hdr->sign_len;
+
+ *img_key = (uint8_t *)key;
+
+ *key_len = klen;
+
+ return ret;
+}
diff --git a/drivers/nxp/auth/csf_hdr_parser/input_bl2_ch2 b/drivers/nxp/auth/csf_hdr_parser/input_bl2_ch2
new file mode 100644
index 0000000..bf8934b
--- /dev/null
+++ b/drivers/nxp/auth/csf_hdr_parser/input_bl2_ch2
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2014-2016, Freescale Semiconductor, Inc.
+ * Copyright 2017-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+---------------------------------------------------
+# Specify the platform. [Mandatory]
+# Choose Platform - 1010/1040/2041/3041/4080/5020/5040/9131/9132/9164/4240/C290/LS1
+PLATFORM=LS1043
+# ESBC Flag. Specify ESBC=0 to sign u-boot and ESBC=1 to sign ESBC images.(default is 0)
+ESBC=0
+---------------------------------------------------
+# Entry Point/Image start address field in the header.[Mandatory]
+# (default=ADDRESS of first file specified in images)
+ENTRY_POINT=10000000
+---------------------------------------------------
+# Specify the file name of the keys separated by comma.
+# The number of files and key select should lie between 1 and 4 for 1040 and C290.
+# For rest of the platforms only one key is required and key select should not be provided.
+
+# USAGE (for 4080/5020/5040/3041/2041/1010/913x): PRI_KEY = <key1.pri>
+# USAGE (for 1040/C290/9164/4240/LS1): PRI_KEY = <key1.pri>, <key2.pri>, <key3.pri>, <key4.pri>
+
+# PRI_KEY (Default private key :srk.pri) - [Optional]
+PRI_KEY=srk.pri
+# PUB_KEY (Default public key :srk.pub) - [Optional]
+PUB_KEY=srk.pub
+# Please provide KEY_SELECT(between 1 to 4) (Required for 1040/C290/9164/4240/LS1 only) - [Optional]
+KEY_SELECT=
+---------------------------------------------------
+# Specify SG table address, only for (2041/3041/4080/5020/5040) with ESBC=0 - [Optional]
+SG_TABLE_ADDR=
+---------------------------------------------------
+# Specify the target where image will be loaded. (Default is NOR_16B) - [Optional]
+# Only required for Non-PBL Devices (1010/1040/9131/9132i/C290)
+# Select from - NOR_8B/NOR_16B/NAND_8B_512/NAND_8B_2K/NAND_8B_4K/NAND_16B_512/NAND_16B_2K/NAND_16B_4K/SD/MMC/SPI
+IMAGE_TARGET=
+---------------------------------------------------
+# Specify IMAGE, Max 8 images are possible. DST_ADDR is required only for Non-PBL Platform. [Mandatory]
+# USAGE : IMAGE_NO = {IMAGE_NAME, SRC_ADDR, DST_ADDR}
+IMAGE_1={bl2.bin,10000000,ffffffff}
+IMAGE_2={,,}
+IMAGE_3={,,}
+IMAGE_4={,,}
+IMAGE_5={,,}
+IMAGE_6={,,}
+IMAGE_7={,,}
+IMAGE_8={,,}
+---------------------------------------------------
+# Specify OEM AND FSL ID to be populated in header. [Optional]
+# e.g FSL_UID=11111111
+FSL_UID_0=
+FSL_UID_1=
+OEM_UID_0=
+OEM_UID_1=
+---------------------------------------------------
+# Specify the file names of csf header and sg table. (Default :hdr.out) [Optional]
+OUTPUT_HDR_FILENAME=hdr_bl2.out
+
+# Specify the file names of hash file and sign file.
+HASH_FILENAME=img_hash.out
+INPUT_SIGN_FILENAME=sign.out
+
+# Specify the signature size.It is mandatory when neither public key nor private key is specified.
+# Signature size would be [0x80 for 1k key, 0x100 for 2k key, and 0x200 for 4k key].
+SIGN_SIZE=
+---------------------------------------------------
+# Specify the output file name of sg table. (Default :sg_table.out). [Optional]
+# Please note that OUTPUT SG BIN is only required for 2041/3041/4080/5020/5040 when ESBC flag is not set.
+OUTPUT_SG_BIN=
+---------------------------------------------------
+# Following fields are Required for 4240/9164/1040/C290 only
+
+# Specify House keeping Area
+# Required for 4240/9164/1040/C290 only when ESBC flag is not set. [Mandatory]
+HK_AREA_POINTER=
+HK_AREA_SIZE=
+---------------------------------------------------
+# Following field Required for 4240/9164/1040/C290 only
+# Specify Secondary Image Flag. (0 or 1) - [Optional]
+# (Default is 0)
+SEC_IMAGE=0
+# Specify Manufacturing Protection Flag. (0 or 1) - [Optional]
+# Required only for LS1(Default is 0)
+MP_FLAG=1
+---------------------------------------------------
diff --git a/drivers/nxp/auth/csf_hdr_parser/input_bl2_ch3 b/drivers/nxp/auth/csf_hdr_parser/input_bl2_ch3
new file mode 100644
index 0000000..5fdad9c
--- /dev/null
+++ b/drivers/nxp/auth/csf_hdr_parser/input_bl2_ch3
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+---------------------------------------------------
+# Specify the platform. [Mandatory]
+# Choose Platform -
+# TRUST 3.2: LX2160
+PLATFORM=LS2088
+---------------------------------------------------
+# Entry Point/Image start address field in the header.[Mandatory]
+# (default=ADDRESS of first file specified in images)
+# Address can be 64 bit
+ENTRY_POINT=1800A000
+---------------------------------------------------
+# Specify the Key Information.
+# PUB_KEY [Mandatory] Comma Separated List
+# Usage: <srk1.pub> <srk2.pub> .....
+PUB_KEY=srk.pub
+# KEY_SELECT [Mandatory]
+# USAGE (for TRUST 3.x): (between 1 to 8)
+KEY_SELECT=1
+# PRI_KEY [Mandatory] Single Key Used for Signing
+# USAGE: <srk.pri>
+PRI_KEY=srk.pri
+---------------------------------------------------
+# Specify IMAGE, Max 8 images are possible.
+# DST_ADDR is required only for Non-PBL Platform. [Mandatory]
+# USAGE : IMAGE_NO = {IMAGE_NAME, SRC_ADDR, DST_ADDR}
+# Address can be 64 bit
+IMAGE_1={bl2.bin,1800A000,ffffffff}
+IMAGE_2={,,}
+IMAGE_3={,,}
+IMAGE_4={,,}
+IMAGE_5={,,}
+IMAGE_6={,,}
+IMAGE_7={,,}
+IMAGE_8={,,}
+---------------------------------------------------
+# Specify OEM AND FSL ID to be populated in header. [Optional]
+# e.g FSL_UID_0=11111111
+FSL_UID_0=
+FSL_UID_1=
+OEM_UID_0=
+OEM_UID_1=
+OEM_UID_2=
+OEM_UID_3=
+OEM_UID_4=
+---------------------------------------------------
+# Specify the output file names [Optional].
+# Default Values chosen in Tool
+OUTPUT_HDR_FILENAME=hdr_bl2.out
+IMAGE_HASH_FILENAME=
+RSA_SIGN_FILENAME=
+---------------------------------------------------
+# Specify The Flags. (0 or 1) - [Optional]
+MP_FLAG=0
+ISS_FLAG=1
+LW_FLAG=0
+---------------------------------------------------
+# Specify VERBOSE as 1, if you want to Display Header Information [Optional]
+VERBOSE=1
diff --git a/drivers/nxp/auth/csf_hdr_parser/input_bl2_ch3_2 b/drivers/nxp/auth/csf_hdr_parser/input_bl2_ch3_2
new file mode 100644
index 0000000..cc7c07c
--- /dev/null
+++ b/drivers/nxp/auth/csf_hdr_parser/input_bl2_ch3_2
@@ -0,0 +1,65 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+---------------------------------------------------
+# Specify the platform. [Mandatory]
+# Choose Platform -
+# TRUST 3.2: LX2160
+PLATFORM=LX2160
+---------------------------------------------------
+# Entry Point/Image start address field in the header.[Mandatory]
+# (default=ADDRESS of first file specified in images)
+# Address can be 64 bit
+ENTRY_POINT=1800D000
+---------------------------------------------------
+# Specify the Key Information.
+# PUB_KEY [Mandatory] Comma Separated List
+# Usage: <srk1.pub> <srk2.pub> .....
+PUB_KEY=srk.pub
+# KEY_SELECT [Mandatory]
+# USAGE (for TRUST 3.x): (between 1 to 8)
+KEY_SELECT=1
+# PRI_KEY [Mandatory] Single Key Used for Signing
+# USAGE: <srk.pri>
+PRI_KEY=srk.pri
+---------------------------------------------------
+# Specify IMAGE, Max 8 images are possible.
+# DST_ADDR is required only for Non-PBL Platform. [Mandatory]
+# USAGE : IMAGE_NO = {IMAGE_NAME, SRC_ADDR, DST_ADDR}
+# Address can be 64 bit
+IMAGE_1={bl2.bin,1800D000,ffffffff}
+IMAGE_2={,,}
+IMAGE_3={,,}
+IMAGE_4={,,}
+IMAGE_5={,,}
+IMAGE_6={,,}
+IMAGE_7={,,}
+IMAGE_8={,,}
+---------------------------------------------------
+# Specify OEM AND FSL ID to be populated in header. [Optional]
+# e.g FSL_UID_0=11111111
+FSL_UID_0=
+FSL_UID_1=
+OEM_UID_0=
+OEM_UID_1=
+OEM_UID_2=
+OEM_UID_3=
+OEM_UID_4=
+---------------------------------------------------
+# Specify the output file names [Optional].
+# Default Values chosen in Tool
+OUTPUT_HDR_FILENAME=hdr_bl2.out
+IMAGE_HASH_FILENAME=
+RSA_SIGN_FILENAME=
+---------------------------------------------------
+# Specify The Flags. (0 or 1) - [Optional]
+MP_FLAG=0
+ISS_FLAG=1
+LW_FLAG=0
+---------------------------------------------------
+# Specify VERBOSE as 1, if you want to Display Header Information [Optional]
+VERBOSE=1
diff --git a/drivers/nxp/auth/csf_hdr_parser/input_blx_ch2 b/drivers/nxp/auth/csf_hdr_parser/input_blx_ch2
new file mode 100644
index 0000000..93b020b
--- /dev/null
+++ b/drivers/nxp/auth/csf_hdr_parser/input_blx_ch2
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2017-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+---------------------------------------------------
+# Specify the platform. [Mandatory]
+# Choose Platform - 1010/1040/2041/3041/4080/5020/5040/9131/9132/9164/4240/C290/LS1
+PLATFORM=LS1043
+# ESBC Flag. Specify ESBC=0 to sign u-boot and ESBC=1 to sign ESBC images.(default is 0)
+ESBC=1
+---------------------------------------------------
+# Specify the file name of the keys separated by comma.
+
+# PRI_KEY (Default private key :srk.pri) - [Optional]
+PRI_KEY=srk.pri
+# PUB_KEY (Default public key :srk.pub) - [Optional]
+PUB_KEY=srk.pub
+# Please provide KEY_SELECT(between 1 to 4) (Required for 1040/C290/9164/4240 only) - [Optional]
+KEY_SELECT=1
+---------------------------------------------------
+# Specify OEM AND FSL ID to be populated in header. [Optional]
+# e.g FSL_UID=11111111
+FSL_UID_0=
+FSL_UID_1=
+OEM_UID_0=
+OEM_UID_1=
+---------------------------------------------------
diff --git a/drivers/nxp/auth/csf_hdr_parser/input_blx_ch3 b/drivers/nxp/auth/csf_hdr_parser/input_blx_ch3
new file mode 100644
index 0000000..18e8e3b
--- /dev/null
+++ b/drivers/nxp/auth/csf_hdr_parser/input_blx_ch3
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2017-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+ESBC=1
+---------------------------------------------------
+# Specify the platform. [Mandatory]
+# Choose Platform -
+# TRUST 3.0: LS2085
+# TRUST 3.1: LS2088, LS1088
+PLATFORM=LS2088
+---------------------------------------------------
+# Specify the Key Information.
+# PUB_KEY [Mandatory] Comma Separated List
+# Usage: <srk1.pub> <srk2.pub> .....
+PUB_KEY=srk.pub
+# KEY_SELECT [Mandatory]
+# USAGE (for TRUST 3.x): (between 1 to 8)
+KEY_SELECT=1
+# PRI_KEY [Mandatory] Single Key Used for Signing
+# USAGE: <srk.pri>
+PRI_KEY=srk.pri
+
+---------------------------------------------------
+# Specify OEM AND FSL ID to be populated in header. [Optional]
+# e.g FSL_UID_0=11111111
+FSL_UID_0=
+FSL_UID_1=
+OEM_UID_0=
+OEM_UID_1=
+OEM_UID_2=
+OEM_UID_3=
+OEM_UID_4=
+---------------------------------------------------
diff --git a/drivers/nxp/auth/csf_hdr_parser/input_pbi_ch3 b/drivers/nxp/auth/csf_hdr_parser/input_pbi_ch3
new file mode 100644
index 0000000..9111a2a
--- /dev/null
+++ b/drivers/nxp/auth/csf_hdr_parser/input_pbi_ch3
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2016-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+---------------------------------------------------
+# Specify the platform. [Mandatory]
+# Choose Platform -
+# TRUST 3.0: LS2085
+# TRUST 3.1: LS2088, LS1088
+PLATFORM=LS2088
+---------------------------------------------------
+# Specify the Key Information.
+# PUB_KEY [Mandatory] Comma Separated List
+# Usage: <srk1.pub> <srk2.pub> .....
+PUB_KEY=srk.pub
+# KEY_SELECT [Mandatory]
+# USAGE (for TRUST 3.x): (between 1 to 8)
+KEY_SELECT=1
+# PRI_KEY [Mandatory] Single Key Used for Signing
+# USAGE: <srk.pri>
+PRI_KEY=srk.pri
+---------------------------------------------------
+# Specify OEM AND FSL ID to be populated in header. [Optional]
+# e.g FSL_UID_0=11111111
+FSL_UID_0=
+FSL_UID_1=
+OEM_UID_0=
+OEM_UID_1=
+OEM_UID_2=
+OEM_UID_3=
+OEM_UID_4=
+---------------------------------------------------
+# Specify The Flags. (0 or 1) - [Optional]
+MP_FLAG=0
+ISS_FLAG=1
+LW_FLAG=0
+---------------------------------------------------
+# Specify VERBOSE as 1, if you want to Display Header Information [Optional]
+VERBOSE=1
+---------------------------------------------------
diff --git a/drivers/nxp/auth/csf_hdr_parser/input_pbi_ch3_2 b/drivers/nxp/auth/csf_hdr_parser/input_pbi_ch3_2
new file mode 100644
index 0000000..c2d7ce4
--- /dev/null
+++ b/drivers/nxp/auth/csf_hdr_parser/input_pbi_ch3_2
@@ -0,0 +1,43 @@
+/*
+ * Copyright 2017-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+---------------------------------------------------
+# Specify the platform. [Mandatory]
+# Choose Platform -
+# TRUST 3.0: LS2085
+# TRUST 3.1: LS2088, LS1088
+PLATFORM=LX2160
+---------------------------------------------------
+# Specify the Key Information.
+# PUB_KEY [Mandatory] Comma Separated List
+# Usage: <srk1.pub> <srk2.pub> .....
+PUB_KEY=srk.pub
+# KEY_SELECT [Mandatory]
+# USAGE (for TRUST 3.x): (between 1 to 8)
+KEY_SELECT=1
+# PRI_KEY [Mandatory] Single Key Used for Signing
+# USAGE: <srk.pri>
+PRI_KEY=srk.pri
+---------------------------------------------------
+# Specify OEM AND FSL ID to be populated in header. [Optional]
+# e.g FSL_UID_0=11111111
+FSL_UID_0=
+FSL_UID_1=
+OEM_UID_0=
+OEM_UID_1=
+OEM_UID_2=
+OEM_UID_3=
+OEM_UID_4=
+---------------------------------------------------
+# Specify The Flags. (0 or 1) - [Optional]
+MP_FLAG=0
+ISS_FLAG=1
+LW_FLAG=0
+---------------------------------------------------
+# Specify VERBOSE as 1, if you want to Display Header Information [Optional]
+VERBOSE=1
+---------------------------------------------------
diff --git a/drivers/nxp/auth/csf_hdr_parser/plat_img_parser.c b/drivers/nxp/auth/csf_hdr_parser/plat_img_parser.c
new file mode 100644
index 0000000..43b78e5
--- /dev/null
+++ b/drivers/nxp/auth/csf_hdr_parser/plat_img_parser.c
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2014-2016, Freescale Semiconductor, Inc.
+ * Copyright 2017-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <assert.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <csf_hdr.h>
+#include <drivers/auth/crypto_mod.h>
+#include <drivers/auth/img_parser_mod.h>
+#include <lib/utils.h>
+#include <sfp.h>
+
+/* Temporary variables to speed up the authentication parameters search. These
+ * variables are assigned once during the integrity check and used any time an
+ * authentication parameter is requested, so we do not have to parse the image
+ * again.
+ */
+
+/* Hash of Image + CSF Header + SRK table */
+uint8_t img_hash[SHA256_BYTES] __aligned(CACHE_WRITEBACK_GRANULE);
+uint32_t hash_len;
+
+/* Key being used for authentication
+ * Points to the key in CSF header copied in DDR
+ * ESBC client key
+ */
+void *img_key;
+uint32_t key_len;
+
+/* ESBC client signature */
+void *img_sign;
+uint32_t sign_len;
+enum sig_alg alg;
+
+/* Maximum OID string length ("a.b.c.d.e.f ...") */
+#define MAX_OID_STR_LEN 64
+
+#define LIB_NAME "NXP CSFv2"
+
+/*
+ * Clear all static temporary variables.
+ */
+static void clear_temp_vars(void)
+{
+#define ZERO_AND_CLEAN(x) \
+ do { \
+ zeromem(&x, sizeof(x)); \
+ clean_dcache_range((uintptr_t)&x, sizeof(x)); \
+ } while (0)
+
+ ZERO_AND_CLEAN(img_key);
+ ZERO_AND_CLEAN(img_sign);
+ ZERO_AND_CLEAN(img_hash);
+ ZERO_AND_CLEAN(key_len);
+ ZERO_AND_CLEAN(hash_len);
+ ZERO_AND_CLEAN(sign_len);
+
+#undef ZERO_AND_CLEAN
+}
+
+/* Exported functions */
+
+static void init(void)
+{
+ clear_temp_vars();
+}
+
+/*
+ * This function would check the integrity of the CSF header
+ */
+static int check_integrity(void *img, unsigned int img_len)
+{
+ int ret;
+
+ /*
+ * The image file has been successfully loaded till here.
+ *
+ * Flush the image to main memory so that it can be authenticated
+ * by CAAM, a HW accelerator regardless of cache and MMU state.
+ */
+ flush_dcache_range((uintptr_t) img, img_len);
+
+ /*
+ * Image is appended at an offset of 16K (IMG_OFFSET) to the header.
+ * So the size in header should be equal to img_len - IMG_OFFSET
+ */
+ VERBOSE("Barker code is %x\n", *(unsigned int *)img);
+ ret = validate_esbc_header(img, &img_key, &key_len, &img_sign,
+ &sign_len, &alg);
+ if (ret < 0) {
+ ERROR("Header authentication failed\n");
+ clear_temp_vars();
+ return IMG_PARSER_ERR;
+ }
+ /* Calculate the hash of various components from the image */
+ ret = calc_img_hash(img, (uint8_t *)img + CSF_HDR_SZ,
+ img_len - CSF_HDR_SZ, img_hash, &hash_len);
+ if (ret != 0) {
+ ERROR("Issue in hash calculation %d\n", ret);
+ clear_temp_vars();
+ return IMG_PARSER_ERR;
+ }
+
+ return IMG_PARSER_OK;
+}
+
+/*
+ * Extract an authentication parameter from CSF header
+ *
+ * CSF header has already been parsed and the required information like
+ * hash of data, signature, length stored in global variables has been
+ * extracted in chek_integrity function. This data
+ * is returned back to the caller.
+ */
+static int get_auth_param(const auth_param_type_desc_t *type_desc,
+ void *img, unsigned int img_len,
+ void **param, unsigned int *param_len)
+{
+ int rc = IMG_PARSER_OK;
+
+ /* We do not use img because the check_integrity function has already
+ * extracted the relevant data ( pk, sig_alg, etc)
+ */
+
+ switch (type_desc->type) {
+
+ /* Hash will be returned for comparison with signature */
+ case AUTH_PARAM_HASH:
+ *param = (void *)img_hash;
+ *param_len = (unsigned int)SHA256_BYTES;
+ break;
+
+ /* Return the public key used for signature extracted from the SRK table
+ * after checks with key revocation
+ */
+ case AUTH_PARAM_PUB_KEY:
+ /* Get the subject public key */
+ /* For a 1K key - the length would be 2k/8 = 0x100 bytes
+ * 2K RSA key - 0x200 , 4K RSA - 0x400
+ */
+ *param = img_key;
+ *param_len = (unsigned int)key_len;
+ break;
+
+ /* Call a function to tell if signature is RSA or ECDSA. ECDSA to be
+ * supported in later platforms like LX2 etc
+ */
+ case AUTH_PARAM_SIG_ALG:
+ /* Algo will be signature - RSA or ECDSA on hash */
+ *param = (void *)&alg;
+ *param_len = 4U;
+ break;
+
+ /* Return the signature */
+ case AUTH_PARAM_SIG:
+ *param = img_sign;
+ *param_len = (unsigned int)sign_len;
+ break;
+
+ case AUTH_PARAM_NV_CTR:
+
+ default:
+ rc = IMG_PARSER_ERR_NOT_FOUND;
+ break;
+ }
+
+ return rc;
+}
+
+REGISTER_IMG_PARSER_LIB(IMG_PLAT, LIB_NAME, init,
+ check_integrity, get_auth_param);
diff --git a/drivers/nxp/auth/tbbr/tbbr_cot.c b/drivers/nxp/auth/tbbr/tbbr_cot.c
new file mode 100644
index 0000000..bb21fa0
--- /dev/null
+++ b/drivers/nxp/auth/tbbr/tbbr_cot.c
@@ -0,0 +1,820 @@
+/*
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+
+#include <drivers/auth/auth_mod.h>
+
+#if USE_TBBR_DEFS
+#include <tools_share/tbbr_oid.h>
+#else
+#include <platform_oid.h>
+#endif
+
+
+#if TF_MBEDTLS_HASH_ALG_ID == TF_MBEDTLS_SHA256
+#define HASH_DER_LEN 51
+#elif TF_MBEDTLS_HASH_ALG_ID == TF_MBEDTLS_SHA384
+#define HASH_DER_LEN 67
+#elif TF_MBEDTLS_HASH_ALG_ID == TF_MBEDTLS_SHA512
+#define HASH_DER_LEN 83
+#else
+#error "Invalid value for TF_MBEDTLS_HASH_ALG_ID"
+#endif
+
+/*
+ * The platform must allocate buffers to store the authentication parameters
+ * extracted from the certificates. In this case, because of the way the CoT is
+ * established, we can reuse some of the buffers on different stages
+ */
+
+static unsigned char nt_world_bl_hash_buf[HASH_DER_LEN];
+
+static unsigned char soc_fw_hash_buf[HASH_DER_LEN];
+static unsigned char tos_fw_hash_buf[HASH_DER_LEN];
+static unsigned char tos_fw_extra1_hash_buf[HASH_DER_LEN];
+static unsigned char tos_fw_extra2_hash_buf[HASH_DER_LEN];
+static unsigned char trusted_world_pk_buf[PK_DER_LEN];
+static unsigned char non_trusted_world_pk_buf[PK_DER_LEN];
+static unsigned char content_pk_buf[PK_DER_LEN];
+static unsigned char soc_fw_config_hash_buf[HASH_DER_LEN];
+static unsigned char tos_fw_config_hash_buf[HASH_DER_LEN];
+static unsigned char nt_fw_config_hash_buf[HASH_DER_LEN];
+
+#ifdef CONFIG_DDR_FIP_IMAGE
+static unsigned char ddr_fw_content_pk_buf[PK_DER_LEN];
+static unsigned char ddr_imem_udimm_1d_hash_buf[HASH_DER_LEN];
+static unsigned char ddr_imem_udimm_2d_hash_buf[HASH_DER_LEN];
+static unsigned char ddr_dmem_udimm_1d_hash_buf[HASH_DER_LEN];
+static unsigned char ddr_dmem_udimm_2d_hash_buf[HASH_DER_LEN];
+
+static unsigned char ddr_imem_rdimm_1d_hash_buf[HASH_DER_LEN];
+static unsigned char ddr_imem_rdimm_2d_hash_buf[HASH_DER_LEN];
+static unsigned char ddr_dmem_rdimm_1d_hash_buf[HASH_DER_LEN];
+static unsigned char ddr_dmem_rdimm_2d_hash_buf[HASH_DER_LEN];
+#endif
+
+/*
+ * Parameter type descriptors
+ */
+static auth_param_type_desc_t trusted_nv_ctr = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_NV_CTR, TRUSTED_FW_NVCOUNTER_OID);
+
+static auth_param_type_desc_t subject_pk = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_PUB_KEY, 0);
+static auth_param_type_desc_t sig = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_SIG, 0);
+static auth_param_type_desc_t sig_alg = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_SIG_ALG, 0);
+static auth_param_type_desc_t raw_data = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_RAW_DATA, 0);
+
+
+static auth_param_type_desc_t non_trusted_nv_ctr = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_NV_CTR, NON_TRUSTED_FW_NVCOUNTER_OID);
+static auth_param_type_desc_t trusted_world_pk = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_PUB_KEY, TRUSTED_WORLD_PK_OID);
+static auth_param_type_desc_t non_trusted_world_pk = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_PUB_KEY, NON_TRUSTED_WORLD_PK_OID);
+static auth_param_type_desc_t soc_fw_content_pk = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_PUB_KEY, SOC_FW_CONTENT_CERT_PK_OID);
+static auth_param_type_desc_t tos_fw_content_pk = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_PUB_KEY, TRUSTED_OS_FW_CONTENT_CERT_PK_OID);
+static auth_param_type_desc_t nt_fw_content_pk = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_PUB_KEY, NON_TRUSTED_FW_CONTENT_CERT_PK_OID);
+static auth_param_type_desc_t soc_fw_hash = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_HASH, SOC_AP_FW_HASH_OID);
+static auth_param_type_desc_t soc_fw_config_hash = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_HASH, SOC_FW_CONFIG_HASH_OID);
+static auth_param_type_desc_t tos_fw_hash = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_HASH, TRUSTED_OS_FW_HASH_OID);
+static auth_param_type_desc_t tos_fw_config_hash = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_HASH, TRUSTED_OS_FW_CONFIG_HASH_OID);
+static auth_param_type_desc_t tos_fw_extra1_hash = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_HASH, TRUSTED_OS_FW_EXTRA1_HASH_OID);
+static auth_param_type_desc_t tos_fw_extra2_hash = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_HASH, TRUSTED_OS_FW_EXTRA2_HASH_OID);
+static auth_param_type_desc_t nt_world_bl_hash = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_HASH, NON_TRUSTED_WORLD_BOOTLOADER_HASH_OID);
+static auth_param_type_desc_t nt_fw_config_hash = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_HASH, NON_TRUSTED_FW_CONFIG_HASH_OID);
+
+#ifdef CONFIG_DDR_FIP_IMAGE
+static auth_param_type_desc_t ddr_fw_content_pk = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_PUB_KEY, DDR_FW_CONTENT_CERT_PK_OID);
+
+static auth_param_type_desc_t ddr_imem_udimm_1d_fw_hash = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_HASH, DDR_IMEM_UDIMM_1D_HASH_OID);
+static auth_param_type_desc_t ddr_imem_udimm_2d_fw_hash = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_HASH, DDR_IMEM_UDIMM_2D_HASH_OID);
+static auth_param_type_desc_t ddr_dmem_udimm_1d_fw_hash = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_HASH, DDR_DMEM_UDIMM_1D_HASH_OID);
+static auth_param_type_desc_t ddr_dmem_udimm_2d_fw_hash = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_HASH, DDR_DMEM_UDIMM_2D_HASH_OID);
+
+static auth_param_type_desc_t ddr_imem_rdimm_1d_fw_hash = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_HASH, DDR_IMEM_RDIMM_1D_HASH_OID);
+static auth_param_type_desc_t ddr_imem_rdimm_2d_fw_hash = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_HASH, DDR_IMEM_RDIMM_2D_HASH_OID);
+static auth_param_type_desc_t ddr_dmem_rdimm_1d_fw_hash = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_HASH, DDR_DMEM_RDIMM_1D_HASH_OID);
+static auth_param_type_desc_t ddr_dmem_rdimm_2d_fw_hash = AUTH_PARAM_TYPE_DESC(
+ AUTH_PARAM_HASH, DDR_DMEM_RDIMM_2D_HASH_OID);
+#endif
+
+
+/*
+ * Trusted key certificate
+ */
+static const auth_img_desc_t trusted_key_cert = {
+ .img_id = TRUSTED_KEY_CERT_ID,
+ .img_type = IMG_CERT,
+ .parent = NULL,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &subject_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &raw_data
+ }
+ },
+ [1] = {
+ .type = AUTH_METHOD_NV_CTR,
+ .param.nv_ctr = {
+ .cert_nv_ctr = &trusted_nv_ctr,
+ .plat_nv_ctr = &trusted_nv_ctr
+ }
+ }
+ },
+ .authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) {
+ [0] = {
+ .type_desc = &trusted_world_pk,
+ .data = {
+ .ptr = (void *)trusted_world_pk_buf,
+ .len = (unsigned int)PK_DER_LEN
+ }
+ },
+ [1] = {
+ .type_desc = &non_trusted_world_pk,
+ .data = {
+ .ptr = (void *)non_trusted_world_pk_buf,
+ .len = (unsigned int)PK_DER_LEN
+ }
+ }
+ }
+};
+
+/*
+ * SoC Firmware
+ */
+static const auth_img_desc_t soc_fw_key_cert = {
+ .img_id = SOC_FW_KEY_CERT_ID,
+ .img_type = IMG_CERT,
+ .parent = &trusted_key_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &trusted_world_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &raw_data
+ }
+ },
+ [1] = {
+ .type = AUTH_METHOD_NV_CTR,
+ .param.nv_ctr = {
+ .cert_nv_ctr = &trusted_nv_ctr,
+ .plat_nv_ctr = &trusted_nv_ctr
+ }
+ }
+ },
+ .authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) {
+ [0] = {
+ .type_desc = &soc_fw_content_pk,
+ .data = {
+ .ptr = (void *)content_pk_buf,
+ .len = (unsigned int)PK_DER_LEN
+ }
+ }
+ }
+};
+static const auth_img_desc_t soc_fw_content_cert = {
+ .img_id = SOC_FW_CONTENT_CERT_ID,
+ .img_type = IMG_CERT,
+ .parent = &soc_fw_key_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &soc_fw_content_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &raw_data
+ }
+ },
+ [1] = {
+ .type = AUTH_METHOD_NV_CTR,
+ .param.nv_ctr = {
+ .cert_nv_ctr = &trusted_nv_ctr,
+ .plat_nv_ctr = &trusted_nv_ctr
+ }
+ }
+ },
+ .authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) {
+ [0] = {
+ .type_desc = &soc_fw_hash,
+ .data = {
+ .ptr = (void *)soc_fw_hash_buf,
+ .len = (unsigned int)HASH_DER_LEN
+ }
+ },
+ [1] = {
+ .type_desc = &soc_fw_config_hash,
+ .data = {
+ .ptr = (void *)soc_fw_config_hash_buf,
+ .len = (unsigned int)HASH_DER_LEN
+ }
+ }
+ }
+};
+static const auth_img_desc_t bl31_image = {
+ .img_id = BL31_IMAGE_ID,
+ .img_type = IMG_RAW,
+ .parent = &soc_fw_content_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_HASH,
+ .param.hash = {
+ .data = &raw_data,
+ .hash = &soc_fw_hash
+ }
+ }
+ }
+};
+/* SOC FW Config */
+static const auth_img_desc_t soc_fw_config = {
+ .img_id = SOC_FW_CONFIG_ID,
+ .img_type = IMG_RAW,
+ .parent = &soc_fw_content_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_HASH,
+ .param.hash = {
+ .data = &raw_data,
+ .hash = &soc_fw_config_hash
+ }
+ }
+ }
+};
+/*
+ * Trusted OS Firmware
+ */
+static const auth_img_desc_t trusted_os_fw_key_cert = {
+ .img_id = TRUSTED_OS_FW_KEY_CERT_ID,
+ .img_type = IMG_CERT,
+ .parent = &trusted_key_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &trusted_world_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &raw_data
+ }
+ },
+ [1] = {
+ .type = AUTH_METHOD_NV_CTR,
+ .param.nv_ctr = {
+ .cert_nv_ctr = &trusted_nv_ctr,
+ .plat_nv_ctr = &trusted_nv_ctr
+ }
+ }
+ },
+ .authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) {
+ [0] = {
+ .type_desc = &tos_fw_content_pk,
+ .data = {
+ .ptr = (void *)content_pk_buf,
+ .len = (unsigned int)PK_DER_LEN
+ }
+ }
+ }
+};
+static const auth_img_desc_t trusted_os_fw_content_cert = {
+ .img_id = TRUSTED_OS_FW_CONTENT_CERT_ID,
+ .img_type = IMG_CERT,
+ .parent = &trusted_os_fw_key_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &tos_fw_content_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &raw_data
+ }
+ },
+ [1] = {
+ .type = AUTH_METHOD_NV_CTR,
+ .param.nv_ctr = {
+ .cert_nv_ctr = &trusted_nv_ctr,
+ .plat_nv_ctr = &trusted_nv_ctr
+ }
+ }
+ },
+ .authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) {
+ [0] = {
+ .type_desc = &tos_fw_hash,
+ .data = {
+ .ptr = (void *)tos_fw_hash_buf,
+ .len = (unsigned int)HASH_DER_LEN
+ }
+ },
+ [1] = {
+ .type_desc = &tos_fw_extra1_hash,
+ .data = {
+ .ptr = (void *)tos_fw_extra1_hash_buf,
+ .len = (unsigned int)HASH_DER_LEN
+ }
+ },
+ [2] = {
+ .type_desc = &tos_fw_extra2_hash,
+ .data = {
+ .ptr = (void *)tos_fw_extra2_hash_buf,
+ .len = (unsigned int)HASH_DER_LEN
+ }
+ },
+ [3] = {
+ .type_desc = &tos_fw_config_hash,
+ .data = {
+ .ptr = (void *)tos_fw_config_hash_buf,
+ .len = (unsigned int)HASH_DER_LEN
+ }
+ }
+ }
+};
+static const auth_img_desc_t bl32_image = {
+ .img_id = BL32_IMAGE_ID,
+ .img_type = IMG_RAW,
+ .parent = &trusted_os_fw_content_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_HASH,
+ .param.hash = {
+ .data = &raw_data,
+ .hash = &tos_fw_hash
+ }
+ }
+ }
+};
+static const auth_img_desc_t bl32_extra1_image = {
+ .img_id = BL32_EXTRA1_IMAGE_ID,
+ .img_type = IMG_RAW,
+ .parent = &trusted_os_fw_content_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_HASH,
+ .param.hash = {
+ .data = &raw_data,
+ .hash = &tos_fw_extra1_hash
+ }
+ }
+ }
+};
+static const auth_img_desc_t bl32_extra2_image = {
+ .img_id = BL32_EXTRA2_IMAGE_ID,
+ .img_type = IMG_RAW,
+ .parent = &trusted_os_fw_content_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_HASH,
+ .param.hash = {
+ .data = &raw_data,
+ .hash = &tos_fw_extra2_hash
+ }
+ }
+ }
+};
+/* TOS FW Config */
+static const auth_img_desc_t tos_fw_config = {
+ .img_id = TOS_FW_CONFIG_ID,
+ .img_type = IMG_RAW,
+ .parent = &trusted_os_fw_content_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_HASH,
+ .param.hash = {
+ .data = &raw_data,
+ .hash = &tos_fw_config_hash
+ }
+ }
+ }
+};
+/*
+ * Non-Trusted Firmware
+ */
+static const auth_img_desc_t non_trusted_fw_key_cert = {
+ .img_id = NON_TRUSTED_FW_KEY_CERT_ID,
+ .img_type = IMG_CERT,
+ .parent = &trusted_key_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &non_trusted_world_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &raw_data
+ }
+ },
+ [1] = {
+ .type = AUTH_METHOD_NV_CTR,
+ .param.nv_ctr = {
+ .cert_nv_ctr = &non_trusted_nv_ctr,
+ .plat_nv_ctr = &non_trusted_nv_ctr
+ }
+ }
+ },
+ .authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) {
+ [0] = {
+ .type_desc = &nt_fw_content_pk,
+ .data = {
+ .ptr = (void *)content_pk_buf,
+ .len = (unsigned int)PK_DER_LEN
+ }
+ }
+ }
+};
+static const auth_img_desc_t non_trusted_fw_content_cert = {
+ .img_id = NON_TRUSTED_FW_CONTENT_CERT_ID,
+ .img_type = IMG_CERT,
+ .parent = &non_trusted_fw_key_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &nt_fw_content_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &raw_data
+ }
+ },
+ [1] = {
+ .type = AUTH_METHOD_NV_CTR,
+ .param.nv_ctr = {
+ .cert_nv_ctr = &non_trusted_nv_ctr,
+ .plat_nv_ctr = &non_trusted_nv_ctr
+ }
+ }
+ },
+ .authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) {
+ [0] = {
+ .type_desc = &nt_world_bl_hash,
+ .data = {
+ .ptr = (void *)nt_world_bl_hash_buf,
+ .len = (unsigned int)HASH_DER_LEN
+ }
+ },
+ [1] = {
+ .type_desc = &nt_fw_config_hash,
+ .data = {
+ .ptr = (void *)nt_fw_config_hash_buf,
+ .len = (unsigned int)HASH_DER_LEN
+ }
+ }
+ }
+};
+static const auth_img_desc_t bl33_image = {
+ .img_id = BL33_IMAGE_ID,
+ .img_type = IMG_RAW,
+ .parent = &non_trusted_fw_content_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_HASH,
+ .param.hash = {
+ .data = &raw_data,
+ .hash = &nt_world_bl_hash
+ }
+ }
+ }
+};
+/* NT FW Config */
+static const auth_img_desc_t nt_fw_config = {
+ .img_id = NT_FW_CONFIG_ID,
+ .img_type = IMG_RAW,
+ .parent = &non_trusted_fw_content_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_HASH,
+ .param.hash = {
+ .data = &raw_data,
+ .hash = &nt_fw_config_hash
+ }
+ }
+ }
+};
+#ifdef CONFIG_DDR_FIP_IMAGE
+/*
+ * DDR Firmware
+ */
+static const auth_img_desc_t ddr_fw_key_cert = {
+ .img_id = DDR_FW_KEY_CERT_ID,
+ .img_type = IMG_CERT,
+ .parent = &trusted_key_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &trusted_world_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &raw_data
+ }
+ },
+ [1] = {
+ .type = AUTH_METHOD_NV_CTR,
+ .param.nv_ctr = {
+ .cert_nv_ctr = &trusted_nv_ctr,
+ .plat_nv_ctr = &trusted_nv_ctr
+ }
+ }
+ },
+ .authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) {
+ [0] = {
+ .type_desc = &ddr_fw_content_pk,
+ .data = {
+ .ptr = (void *)ddr_fw_content_pk_buf,
+ .len = (unsigned int)PK_DER_LEN
+ }
+ }
+ }
+};
+static const auth_img_desc_t ddr_udimm_fw_content_cert = {
+ .img_id = DDR_UDIMM_FW_CONTENT_CERT_ID,
+ .img_type = IMG_CERT,
+ .parent = &ddr_fw_key_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &ddr_fw_content_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &raw_data
+ }
+ },
+ [1] = {
+ .type = AUTH_METHOD_NV_CTR,
+ .param.nv_ctr = {
+ .cert_nv_ctr = &trusted_nv_ctr,
+ .plat_nv_ctr = &trusted_nv_ctr
+ }
+ }
+ },
+ .authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) {
+ [0] = {
+ .type_desc = &ddr_imem_udimm_1d_fw_hash,
+ .data = {
+ .ptr = (void *)ddr_imem_udimm_1d_hash_buf,
+ .len = (unsigned int)HASH_DER_LEN
+ }
+ },
+ [1] = {
+ .type_desc = &ddr_imem_udimm_2d_fw_hash,
+ .data = {
+ .ptr = (void *)ddr_imem_udimm_2d_hash_buf,
+ .len = (unsigned int)HASH_DER_LEN
+ }
+ },
+ [2] = {
+ .type_desc = &ddr_dmem_udimm_1d_fw_hash,
+ .data = {
+ .ptr = (void *)ddr_dmem_udimm_1d_hash_buf,
+ .len = (unsigned int)HASH_DER_LEN
+ }
+ },
+ [3] = {
+ .type_desc = &ddr_dmem_udimm_2d_fw_hash,
+ .data = {
+ .ptr = (void *)ddr_dmem_udimm_2d_hash_buf,
+ .len = (unsigned int)HASH_DER_LEN
+ }
+ },
+ }
+};
+
+static const auth_img_desc_t ddr_imem_udimm_1d_img = {
+ .img_id = DDR_IMEM_UDIMM_1D_IMAGE_ID,
+ .img_type = IMG_RAW,
+ .parent = &ddr_udimm_fw_content_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_HASH,
+ .param.hash = {
+ .data = &raw_data,
+ .hash = &ddr_imem_udimm_1d_fw_hash
+ }
+ }
+ }
+};
+static const auth_img_desc_t ddr_imem_udimm_2d_img = {
+ .img_id = DDR_IMEM_UDIMM_2D_IMAGE_ID,
+ .img_type = IMG_RAW,
+ .parent = &ddr_udimm_fw_content_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_HASH,
+ .param.hash = {
+ .data = &raw_data,
+ .hash = &ddr_imem_udimm_2d_fw_hash
+ }
+ }
+ }
+};
+static const auth_img_desc_t ddr_dmem_udimm_1d_img = {
+ .img_id = DDR_DMEM_UDIMM_1D_IMAGE_ID,
+ .img_type = IMG_RAW,
+ .parent = &ddr_udimm_fw_content_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_HASH,
+ .param.hash = {
+ .data = &raw_data,
+ .hash = &ddr_dmem_udimm_1d_fw_hash
+ }
+ }
+ }
+};
+static const auth_img_desc_t ddr_dmem_udimm_2d_img = {
+ .img_id = DDR_DMEM_UDIMM_2D_IMAGE_ID,
+ .img_type = IMG_RAW,
+ .parent = &ddr_udimm_fw_content_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_HASH,
+ .param.hash = {
+ .data = &raw_data,
+ .hash = &ddr_dmem_udimm_2d_fw_hash
+ }
+ }
+ }
+};
+
+static const auth_img_desc_t ddr_rdimm_fw_content_cert = {
+ .img_id = DDR_RDIMM_FW_CONTENT_CERT_ID,
+ .img_type = IMG_CERT,
+ .parent = &ddr_fw_key_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_SIG,
+ .param.sig = {
+ .pk = &ddr_fw_content_pk,
+ .sig = &sig,
+ .alg = &sig_alg,
+ .data = &raw_data
+ }
+ },
+ [1] = {
+ .type = AUTH_METHOD_NV_CTR,
+ .param.nv_ctr = {
+ .cert_nv_ctr = &trusted_nv_ctr,
+ .plat_nv_ctr = &trusted_nv_ctr
+ }
+ }
+ },
+ .authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) {
+ [0] = {
+ .type_desc = &ddr_imem_rdimm_1d_fw_hash,
+ .data = {
+ .ptr = (void *)ddr_imem_rdimm_1d_hash_buf,
+ .len = (unsigned int)HASH_DER_LEN
+ }
+ },
+ [1] = {
+ .type_desc = &ddr_imem_rdimm_2d_fw_hash,
+ .data = {
+ .ptr = (void *)ddr_imem_rdimm_2d_hash_buf,
+ .len = (unsigned int)HASH_DER_LEN
+ }
+ },
+ [2] = {
+ .type_desc = &ddr_dmem_rdimm_1d_fw_hash,
+ .data = {
+ .ptr = (void *)ddr_dmem_rdimm_1d_hash_buf,
+ .len = (unsigned int)HASH_DER_LEN
+ }
+ },
+ [3] = {
+ .type_desc = &ddr_dmem_rdimm_2d_fw_hash,
+ .data = {
+ .ptr = (void *)ddr_dmem_rdimm_2d_hash_buf,
+ .len = (unsigned int)HASH_DER_LEN
+ }
+ },
+ }
+};
+
+static const auth_img_desc_t ddr_imem_rdimm_1d_img = {
+ .img_id = DDR_IMEM_RDIMM_1D_IMAGE_ID,
+ .img_type = IMG_RAW,
+ .parent = &ddr_rdimm_fw_content_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_HASH,
+ .param.hash = {
+ .data = &raw_data,
+ .hash = &ddr_imem_rdimm_1d_fw_hash
+ }
+ }
+ }
+};
+static const auth_img_desc_t ddr_imem_rdimm_2d_img = {
+ .img_id = DDR_IMEM_RDIMM_2D_IMAGE_ID,
+ .img_type = IMG_RAW,
+ .parent = &ddr_rdimm_fw_content_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_HASH,
+ .param.hash = {
+ .data = &raw_data,
+ .hash = &ddr_imem_rdimm_2d_fw_hash
+ }
+ }
+ }
+};
+static const auth_img_desc_t ddr_dmem_rdimm_1d_img = {
+ .img_id = DDR_DMEM_RDIMM_1D_IMAGE_ID,
+ .img_type = IMG_RAW,
+ .parent = &ddr_rdimm_fw_content_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_HASH,
+ .param.hash = {
+ .data = &raw_data,
+ .hash = &ddr_dmem_rdimm_1d_fw_hash
+ }
+ }
+ }
+};
+static const auth_img_desc_t ddr_dmem_rdimm_2d_img = {
+ .img_id = DDR_DMEM_RDIMM_2D_IMAGE_ID,
+ .img_type = IMG_RAW,
+ .parent = &ddr_rdimm_fw_content_cert,
+ .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
+ [0] = {
+ .type = AUTH_METHOD_HASH,
+ .param.hash = {
+ .data = &raw_data,
+ .hash = &ddr_dmem_rdimm_2d_fw_hash
+ }
+ }
+ }
+};
+#endif
+
+/*
+ * TBBR Chain of trust definition
+ */
+
+static const auth_img_desc_t * const cot_desc[] = {
+ [TRUSTED_KEY_CERT_ID] = &trusted_key_cert,
+ [SOC_FW_KEY_CERT_ID] = &soc_fw_key_cert,
+ [SOC_FW_CONTENT_CERT_ID] = &soc_fw_content_cert,
+ [BL31_IMAGE_ID] = &bl31_image,
+ [SOC_FW_CONFIG_ID] = &soc_fw_config,
+ [TRUSTED_OS_FW_KEY_CERT_ID] = &trusted_os_fw_key_cert,
+ [TRUSTED_OS_FW_CONTENT_CERT_ID] = &trusted_os_fw_content_cert,
+ [BL32_IMAGE_ID] = &bl32_image,
+ [BL32_EXTRA1_IMAGE_ID] = &bl32_extra1_image,
+ [BL32_EXTRA2_IMAGE_ID] = &bl32_extra2_image,
+ [TOS_FW_CONFIG_ID] = &tos_fw_config,
+ [NON_TRUSTED_FW_KEY_CERT_ID] = &non_trusted_fw_key_cert,
+ [NON_TRUSTED_FW_CONTENT_CERT_ID] = &non_trusted_fw_content_cert,
+ [BL33_IMAGE_ID] = &bl33_image,
+ [NT_FW_CONFIG_ID] = &nt_fw_config,
+#ifdef CONFIG_DDR_FIP_IMAGE
+ [DDR_FW_KEY_CERT_ID] = &ddr_fw_key_cert,
+ [DDR_UDIMM_FW_CONTENT_CERT_ID] = &ddr_udimm_fw_content_cert,
+ [DDR_RDIMM_FW_CONTENT_CERT_ID] = &ddr_rdimm_fw_content_cert,
+ [DDR_IMEM_UDIMM_1D_IMAGE_ID] = &ddr_imem_udimm_1d_img,
+ [DDR_IMEM_UDIMM_2D_IMAGE_ID] = &ddr_imem_udimm_2d_img,
+ [DDR_DMEM_UDIMM_1D_IMAGE_ID] = &ddr_dmem_udimm_1d_img,
+ [DDR_DMEM_UDIMM_2D_IMAGE_ID] = &ddr_dmem_udimm_2d_img,
+ [DDR_IMEM_RDIMM_1D_IMAGE_ID] = &ddr_imem_rdimm_1d_img,
+ [DDR_IMEM_RDIMM_2D_IMAGE_ID] = &ddr_imem_rdimm_2d_img,
+ [DDR_DMEM_RDIMM_1D_IMAGE_ID] = &ddr_dmem_rdimm_1d_img,
+ [DDR_DMEM_RDIMM_2D_IMAGE_ID] = &ddr_dmem_rdimm_2d_img,
+#endif
+};
+
+/* Register the CoT in the authentication module */
+REGISTER_COT(cot_desc);
diff --git a/drivers/nxp/console/16550_console.S b/drivers/nxp/console/16550_console.S
new file mode 100644
index 0000000..044d3d0
--- /dev/null
+++ b/drivers/nxp/console/16550_console.S
@@ -0,0 +1,319 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <assert_macros.S>
+#include <console_macros.S>
+
+/* UART16550 Registers */
+#define UARTTX 0x0
+#define UARTRX 0x0
+#define UARTDLL 0x0
+#define UARTIER 0x1
+#define UARTDLLM 0x1
+#define UARTFCR 0x2
+#define UARTLCR 0x3
+#define UARTLSR 0x5
+#define UARTMCR 0x4
+
+/* FIFO Control Register bits */
+#define UARTFCR_FIFOMD_16450 (0 << 6)
+#define UARTFCR_FIFOMD_16550 (1 << 6)
+#define UARTFCR_RXTRIG_1 (0 << 6)
+#define UARTFCR_RXTRIG_4 (1 << 6)
+#define UARTFCR_RXTRIG_8 (2 << 6)
+#define UARTFCR_RXTRIG_16 (3 << 6)
+#define UARTFCR_TXTRIG_1 (0 << 4)
+#define UARTFCR_TXTRIG_4 (1 << 4)
+#define UARTFCR_TXTRIG_8 (2 << 4)
+#define UARTFCR_TXTRIG_16 (3 << 4)
+#define UARTFCR_DMAEN (1 << 3) /* Enable DMA mode */
+#define UARTFCR_TXCLR (1 << 2) /* Clear contents of Tx FIFO */
+#define UARTFCR_RXCLR (1 << 1) /* Clear contents of Rx FIFO */
+#define UARTFCR_FIFOEN (1 << 0) /* Enable the Tx/Rx FIFO */
+#define UARTFCR_64FIFO (1 << 5)
+
+/* Line Control Register bits */
+#define UARTLCR_DLAB (1 << 7) /* Divisor Latch Access */
+#define UARTLCR_SETB (1 << 6) /* Set BREAK Condition */
+#define UARTLCR_SETP (1 << 5) /* Set Parity to LCR[4] */
+#define UARTLCR_EVEN (1 << 4) /* Even Parity Format */
+#define UARTLCR_PAR (1 << 3) /* Parity */
+#define UARTLCR_STOP (1 << 2) /* Stop Bit */
+#define UARTLCR_WORDSZ_5 0 /* Word Length of 5 */
+#define UARTLCR_WORDSZ_6 1 /* Word Length of 6 */
+#define UARTLCR_WORDSZ_7 2 /* Word Length of 7 */
+#define UARTLCR_WORDSZ_8 3 /* Word Length of 8 */
+
+/* Line Status Register bits */
+#define UARTLSR_RXFIFOEMT (1 << 9) /* Rx Fifo Empty */
+#define UARTLSR_TXFIFOFULL (1 << 8) /* Tx Fifo Full */
+#define UARTLSR_RXFIFOERR (1 << 7) /* Rx Fifo Error */
+#define UARTLSR_TEMT (1 << 6) /* Tx Shift Register Empty */
+#define UARTLSR_THRE (1 << 5) /* Tx Holding Register Empty */
+#define UARTLSR_BRK (1 << 4) /* Break Condition Detected */
+#define UARTLSR_FERR (1 << 3) /* Framing Error */
+#define UARTLSR_PERR (1 << 3) /* Parity Error */
+#define UARTLSR_OVRF (1 << 2) /* Rx Overrun Error */
+#define UARTLSR_RDR (1 << 2) /* Rx Data Ready */
+
+#define CONSOLE_T_16550_BASE CONSOLE_T_BASE
+
+ /*
+ * "core" functions are low-level implementations that don't require
+ * writable memory and are thus safe to call in BL1 crash context.
+ */
+ .globl nxp_console_16550_core_init
+ .globl nxp_console_16550_core_putc
+ .globl nxp_console_16550_core_getc
+ .globl nxp_console_16550_core_flush
+
+ .globl console_16550_putc
+ .globl console_16550_getc
+ .globl console_16550_flush
+
+ /* -----------------------------------------------
+ * int nxp_console_16550_core_init(uintptr_t base_addr,
+ * unsigned int uart_clk, unsigned int baud_rate)
+ * Function to initialize the console without a
+ * C Runtime to print debug information. This
+ * function will be accessed by console_init and
+ * crash reporting.
+ * In: x0 - console base address
+ * w1 - Uart clock in Hz
+ * w2 - Baud rate
+ * Out: return 1 on success, 0 on error
+ * Clobber list : x1, x2, x3
+ * -----------------------------------------------
+ */
+func nxp_console_16550_core_init
+ /* Check the input base address */
+ cbz x0, init_fail
+ /* Check baud rate and uart clock for sanity */
+ cbz w1, init_fail
+ cbz w2, init_fail
+
+ /* Program the baudrate */
+ /* Divisor = Uart clock / (16 * baudrate) */
+ lsl w2, w2, #4
+ udiv w2, w1, w2
+ and w1, w2, #0xff /* w1 = DLL */
+ lsr w2, w2, #8
+ and w2, w2, #0xff /* w2 = DLLM */
+ ldrb w3, [x0, #UARTLCR]
+ orr w3, w3, #UARTLCR_DLAB
+ strb w3, [x0, #UARTLCR] /* enable DLL, DLLM programming */
+ strb w1, [x0, #UARTDLL] /* program DLL */
+ strb w2, [x0, #UARTDLLM] /* program DLLM */
+ mov w2, #~UARTLCR_DLAB
+ and w3, w3, w2
+ strb w3, [x0, #UARTLCR] /* disable DLL, DLLM programming */
+
+ /* 8n1 */
+ mov w3, #3
+ strb w3, [x0, #UARTLCR]
+ /* no interrupt */
+ mov w3, #0
+ strb w3, [x0, #UARTIER]
+ /* enable fifo, DMA */
+ mov w3, #(UARTFCR_FIFOEN |UARTFCR_TXCLR | UARTFCR_RXCLR)
+ strb w3, [x0, #UARTFCR]
+ /* DTR + RTS */
+ mov w3, #3
+ str w3, [x0, #UARTMCR]
+ mov w0, #1
+ ret
+init_fail:
+ mov w0, #0
+ ret
+endfunc nxp_console_16550_core_init
+
+ .globl nxp_console_16550_register
+
+ /* -----------------------------------------------
+ * int nxp_console_16550_register(uintptr_t baseaddr,
+ * uint32_t clock, uint32_t baud,
+ * console_t *console);
+ * Function to initialize and register a new 16550
+ * console. Storage passed in for the console struct
+ * *must* be persistent (i.e. not from the stack).
+ * If w1 (UART clock) is 0, initialisation will be
+ * skipped, relying on previous code to have done
+ * this already. w2 is ignored then as well.
+ * In: x0 - UART register base address
+ * w1 - UART clock in Hz
+ * w2 - Baud rate (ignored if w1 is 0)
+ * x3 - pointer to empty console_t struct
+ * Out: return 1 on success, 0 on error
+ * Clobber list : x0, x1, x2, x6, x7, x14
+ * -----------------------------------------------
+ */
+func nxp_console_16550_register
+ mov x7, x30
+ mov x6, x3
+ cbz x6, register_fail
+ str x0, [x6, #CONSOLE_T_16550_BASE]
+
+ /* A clock rate of zero means to skip the initialisation. */
+ cbz w1, register_16550
+
+ bl nxp_console_16550_core_init
+ cbz x0, register_fail
+
+register_16550:
+ mov x0, x6
+ mov x30, x7
+ finish_console_register 16550 putc=1, getc=1, flush=1
+
+register_fail:
+ ret x7
+endfunc nxp_console_16550_register
+
+ /* --------------------------------------------------------
+ * int console_16550_core_putc(int c, uintptr_t base_addr)
+ * Function to output a character over the console. It
+ * returns the character printed on success or -1 on error.
+ * In : w0 - character to be printed
+ * x1 - console base address
+ * Out : return -1 on error else return character.
+ * Clobber list : x2
+ * --------------------------------------------------------
+ */
+func nxp_console_16550_core_putc
+#if ENABLE_ASSERTIONS
+ cmp x1, #0
+ ASM_ASSERT(ne)
+#endif /* ENABLE_ASSERTIONS */
+
+ /* Prepend '\r' to '\n' */
+ cmp w0, #'\n'
+ b.ne 2f
+ /* Check if the transmit FIFO is full */
+1: ldrb w2, [x1, #UARTLSR]
+ and w2, w2, #UARTLSR_THRE /* #(UARTLSR_TEMT | UARTLSR_THRE)*/
+ cmp w2, #(UARTLSR_THRE)
+ b.ne 1b
+ mov w2, #'\r'
+ strb w2, [x1, #UARTTX]
+ ldrb w2, [x1, #UARTFCR]
+ orr w2, w2, #UARTFCR_TXCLR
+
+ /* Check if the transmit FIFO is full */
+2: ldrb w2, [x1, #UARTLSR]
+ and w2, w2, #(UARTLSR_THRE)
+ cmp w2, #(UARTLSR_THRE)
+ b.ne 2b
+ strb w0, [x1, #UARTTX]
+ ret
+endfunc nxp_console_16550_core_putc
+
+ /* --------------------------------------------------------
+ * int console_16550_putc(int c, console_t *console)
+ * Function to output a character over the console. It
+ * returns the character printed on success or -1 on error.
+ * In : w0 - character to be printed
+ * x1 - pointer to console_t structure
+ * Out : return -1 on error else return character.
+ * Clobber list : x2
+ * --------------------------------------------------------
+ */
+func console_16550_putc
+#if ENABLE_ASSERTIONS
+ cmp x1, #0
+ ASM_ASSERT(ne)
+#endif /* ENABLE_ASSERTIONS */
+ ldr x1, [x1, #CONSOLE_T_16550_BASE]
+ b nxp_console_16550_core_putc
+endfunc console_16550_putc
+
+ /* ---------------------------------------------
+ * int console_16550_core_getc(uintptr_t base_addr)
+ * Function to get a character from the console.
+ * It returns the character grabbed on success
+ * or -1 on if no character is available.
+ * In : x0 - console base address
+ * Out : w0 - character if available, else -1
+ * Clobber list : x0, x1
+ * ---------------------------------------------
+ */
+func nxp_console_16550_core_getc
+#if ENABLE_ASSERTIONS
+ cmp x0, #0
+ ASM_ASSERT(ne)
+#endif /* ENABLE_ASSERTIONS */
+
+ /* Check if the receive FIFO is empty */
+1: ldrb w1, [x0, #UARTLSR]
+ tbz w1, #UARTLSR_RDR, 1b
+ ldrb w0, [x0, #UARTRX]
+ ret
+no_char:
+ mov w0, #ERROR_NO_PENDING_CHAR
+ ret
+endfunc nxp_console_16550_core_getc
+
+ /* ---------------------------------------------
+ * int console_16550_getc(console_t *console)
+ * Function to get a character from the console.
+ * It returns the character grabbed on success
+ * or -1 on if no character is available.
+ * In : x0 - pointer to console_t structure
+ * Out : w0 - character if available, else -1
+ * Clobber list : x0, x1
+ * ---------------------------------------------
+ */
+func console_16550_getc
+#if ENABLE_ASSERTIONS
+ cmp x1, #0
+ ASM_ASSERT(ne)
+#endif /* ENABLE_ASSERTIONS */
+ ldr x0, [x0, #CONSOLE_T_16550_BASE]
+ b nxp_console_16550_core_getc
+endfunc console_16550_getc
+
+ /* ---------------------------------------------
+ * int console_16550_core_flush(uintptr_t base_addr)
+ * Function to force a write of all buffered
+ * data that hasn't been output.
+ * In : x0 - console base address
+ * Out : return -1 on error else return 0.
+ * Clobber list : x0, x1
+ * ---------------------------------------------
+ */
+func nxp_console_16550_core_flush
+#if ENABLE_ASSERTIONS
+ cmp x0, #0
+ ASM_ASSERT(ne)
+#endif /* ENABLE_ASSERTIONS */
+
+ /* Loop until the transmit FIFO is empty */
+1: ldrb w1, [x0, #UARTLSR]
+ and w1, w1, #(UARTLSR_THRE)
+ cmp w1, #(UARTLSR_THRE)
+ b.ne 1b
+
+ mov w0, #0
+ ret
+endfunc nxp_console_16550_core_flush
+
+ /* ---------------------------------------------
+ * int console_16550_flush(console_t *console)
+ * Function to force a write of all buffered
+ * data that hasn't been output.
+ * In : x0 - pointer to console_t structure
+ * Out : return -1 on error else return 0.
+ * Clobber list : x0, x1
+ * ---------------------------------------------
+ */
+func console_16550_flush
+#if ENABLE_ASSERTIONS
+ cmp x0, #0
+ ASM_ASSERT(ne)
+#endif /* ENABLE_ASSERTIONS */
+ ldr x0, [x0, #CONSOLE_T_16550_BASE]
+ b nxp_console_16550_core_flush
+endfunc console_16550_flush
diff --git a/drivers/nxp/console/console.mk b/drivers/nxp/console/console.mk
new file mode 100644
index 0000000..6174650
--- /dev/null
+++ b/drivers/nxp/console/console.mk
@@ -0,0 +1,46 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+#------------------------------------------------------------------------------
+#
+# Select the CORE files
+#
+# -----------------------------------------------------------------------------
+
+ifeq (${ADD_CONSOLE},)
+
+ADD_CONSOLE := 1
+
+PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLUDE_PATH)/console
+
+ifeq ($(CONSOLE), NS16550)
+NXP_CONSOLE := NS16550
+
+$(eval $(call add_define_val,NXP_CONSOLE,${NXP_CONSOLE}))
+
+CONSOLE_SOURCES := $(PLAT_DRIVERS_PATH)/console/16550_console.S \
+ $(PLAT_DRIVERS_PATH)/console/console_16550.c
+else
+ifeq ($(CONSOLE), PL011)
+CONSOLE_SOURCES := drivers/arm/pl011/aarch64/pl011_console.S \
+ ${PLAT_DRIVERS_PATH}/console/console_pl011.c
+else
+ $(error -> CONSOLE not set!)
+endif
+endif
+
+ifeq (${BL_COMM_CONSOLE_NEEDED},yes)
+BL_COMMON_SOURCES += ${CONSOLE_SOURCES}
+else
+ifeq (${BL2_CONSOLE_NEEDED},yes)
+BL2_SOURCES += ${CONSOLE_SOURCES}
+endif
+ifeq (${BL31_CONSOLE_NEEDED},yes)
+BL31_SOURCES += ${CONSOLE_SOURCES}
+endif
+endif
+endif
+# -----------------------------------------------------------------------------
diff --git a/drivers/nxp/console/console_16550.c b/drivers/nxp/console/console_16550.c
new file mode 100644
index 0000000..fa5c5bb
--- /dev/null
+++ b/drivers/nxp/console/console_16550.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <assert.h>
+
+#include <common/debug.h>
+#include <dcfg.h>
+#include <lib/utils.h>
+#include <plat_console.h>
+
+/*
+ * Perform Arm specific early platform setup. At this moment we only initialize
+ * the console and the memory layout.
+ */
+void plat_console_init(uintptr_t nxp_console_addr, uint32_t uart_clk_div,
+ uint32_t baud)
+{
+ struct sysinfo sys;
+ static console_t nxp_console;
+
+ zeromem(&sys, sizeof(sys));
+ if (get_clocks(&sys)) {
+ ERROR("System clocks are not set\n");
+ panic();
+ }
+ nxp_console_16550_register(nxp_console_addr,
+ (sys.freq_platform/uart_clk_div),
+ baud, &nxp_console);
+}
diff --git a/drivers/nxp/console/console_pl011.c b/drivers/nxp/console/console_pl011.c
new file mode 100644
index 0000000..93f2fc2
--- /dev/null
+++ b/drivers/nxp/console/console_pl011.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <assert.h>
+
+#include <common/debug.h>
+#include <dcfg.h>
+#include <drivers/arm/pl011.h>
+#include <drivers/console.h>
+#include <lib/utils.h>
+
+/*
+ * Perform Arm specific early platform setup. At this moment we only initialize
+ * the console and the memory layout.
+ */
+void plat_console_init(uintptr_t nxp_console_addr, uint32_t uart_clk_div,
+ uint32_t baud)
+{
+ struct sysinfo sys;
+ static console_t nxp_console;
+
+ zeromem(&sys, sizeof(sys));
+ if (get_clocks(&sys)) {
+ ERROR("System clocks are not set\n");
+ panic();
+ }
+
+ console_pl011_register(nxp_console_addr,
+ (sys.freq_platform/uart_clk_div),
+ baud, &nxp_console);
+}
diff --git a/drivers/nxp/crypto/caam/caam.mk b/drivers/nxp/crypto/caam/caam.mk
new file mode 100644
index 0000000..f929f53
--- /dev/null
+++ b/drivers/nxp/crypto/caam/caam.mk
@@ -0,0 +1,27 @@
+#
+# Copyright 2020-2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+
+ifeq (${ADD_CAAM},)
+
+ADD_CAAM := 1
+
+CAAM_DRIVER_SOURCES += $(wildcard $(PLAT_DRIVERS_PATH)/crypto/caam/src/*.c)
+
+PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLUDE_PATH)/crypto/caam
+
+ifeq (${BL_COMM_CRYPTO_NEEDED},yes)
+BL_COMMON_SOURCES += ${CAAM_DRIVER_SOURCES}
+else
+ifeq (${BL2_CRYPTO_NEEDED},yes)
+BL2_SOURCES += ${CAAM_DRIVER_SOURCES}
+endif
+ifeq (${BL31_CRYPTO_NEEDED},yes)
+BL31_SOURCES += ${CAAM_DRIVER_SOURCES}
+endif
+endif
+
+endif
diff --git a/drivers/nxp/crypto/caam/src/auth/auth.mk b/drivers/nxp/crypto/caam/src/auth/auth.mk
new file mode 100644
index 0000000..d1f8c75
--- /dev/null
+++ b/drivers/nxp/crypto/caam/src/auth/auth.mk
@@ -0,0 +1,12 @@
+#
+# Copyright 2018-2020 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+
+SEC_DRIVERS_PATH := drivers/nxp/crypto/caam
+
+ifeq (${TRUSTED_BOARD_BOOT},1)
+AUTH_SOURCES += $(wildcard $(SEC_DRIVERS_PATH)/src/auth/*.c)
+endif
diff --git a/drivers/nxp/crypto/caam/src/auth/hash.c b/drivers/nxp/crypto/caam/src/auth/hash.c
new file mode 100644
index 0000000..1665df1
--- /dev/null
+++ b/drivers/nxp/crypto/caam/src/auth/hash.c
@@ -0,0 +1,155 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <arch_helpers.h>
+#include "caam.h"
+#include <common/debug.h>
+#include <drivers/auth/crypto_mod.h>
+
+#include "hash.h"
+#include "jobdesc.h"
+#include "sec_hw_specific.h"
+
+/* Since no Allocator is available . Taking a global static ctx.
+ * This would mean that only one active ctx can be there at a time.
+ */
+
+static struct hash_ctx glbl_ctx;
+
+static void hash_done(uint32_t *desc, uint32_t status, void *arg,
+ void *job_ring)
+{
+ INFO("Hash Desc SUCCESS with status %x\n", status);
+}
+
+/***************************************************************************
+ * Function : hash_init
+ * Arguments : ctx - SHA context
+ * Return : init,
+ * Description : This function initializes the context for SHA calculation
+ ***************************************************************************/
+int hash_init(enum hash_algo algo, void **ctx)
+{
+ if (glbl_ctx.active == false) {
+ memset(&glbl_ctx, 0, sizeof(struct hash_ctx));
+ glbl_ctx.active = true;
+ glbl_ctx.algo = algo;
+ *ctx = &glbl_ctx;
+ return 0;
+ } else {
+ return -1;
+ }
+}
+
+/***************************************************************************
+ * Function : hash_update
+ * Arguments : ctx - SHA context
+ * buffer - Data
+ * length - Length
+ * Return : -1 on error
+ * 0 on SUCCESS
+ * Description : This function creates SG entry of the data provided
+ ***************************************************************************/
+int hash_update(enum hash_algo algo, void *context, void *data_ptr,
+ unsigned int data_len)
+{
+ struct hash_ctx *ctx = context;
+ /* MAX_SG would be MAX_SG_ENTRIES + key + hdr + sg table */
+ if (ctx->sg_num >= MAX_SG) {
+ ERROR("Reached limit for calling %s\n", __func__);
+ ctx->active = false;
+ return -EINVAL;
+
+ }
+
+ if (ctx->algo != algo) {
+ ERROR("ctx for algo not correct\n");
+ ctx->active = false;
+ return -EINVAL;
+ }
+
+#if defined(SEC_MEM_NON_COHERENT) && defined(IMAGE_BL2)
+ flush_dcache_range((uintptr_t)data_ptr, data_len);
+ dmbsy();
+#endif
+
+#ifdef CONFIG_PHYS_64BIT
+ sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi,
+ (uint32_t) ((uintptr_t) data_ptr >> 32));
+#else
+ sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, 0x0);
+#endif
+ sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_lo, (uintptr_t) data_ptr);
+
+ sec_out32(&ctx->sg_tbl[ctx->sg_num].len_flag,
+ (data_len & SG_ENTRY_LENGTH_MASK));
+
+ ctx->sg_num++;
+
+ ctx->len += data_len;
+
+ return 0;
+}
+
+/***************************************************************************
+ * Function : hash_final
+ * Arguments : ctx - SHA context
+ * Return : SUCCESS or FAILURE
+ * Description : This function sets the final bit and enqueues the decriptor
+ ***************************************************************************/
+int hash_final(enum hash_algo algo, void *context, void *hash_ptr,
+ unsigned int hash_len)
+{
+ int ret = 0;
+ struct hash_ctx *ctx = context;
+ uint32_t final = 0U;
+
+ struct job_descriptor jobdesc __aligned(CACHE_WRITEBACK_GRANULE);
+
+ jobdesc.arg = NULL;
+ jobdesc.callback = hash_done;
+
+ if (ctx->algo != algo) {
+ ERROR("ctx for algo not correct\n");
+ ctx->active = false;
+ return -EINVAL;
+ }
+
+ final = sec_in32(&ctx->sg_tbl[ctx->sg_num - 1].len_flag) |
+ SG_ENTRY_FINAL_BIT;
+ sec_out32(&ctx->sg_tbl[ctx->sg_num - 1].len_flag, final);
+
+ dsb();
+
+ /* create the hw_rng descriptor */
+ cnstr_hash_jobdesc(jobdesc.desc, (uint8_t *) ctx->sg_tbl,
+ ctx->len, hash_ptr);
+
+#if defined(SEC_MEM_NON_COHERENT) && defined(IMAGE_BL2)
+ flush_dcache_range((uintptr_t)ctx->sg_tbl,
+ (sizeof(struct sg_entry) * MAX_SG));
+ inv_dcache_range((uintptr_t)hash_ptr, hash_len);
+
+ dmbsy();
+#endif
+
+ /* Finally, generate the requested random data bytes */
+ ret = run_descriptor_jr(&jobdesc);
+ if (ret != 0) {
+ ERROR("Error in running descriptor\n");
+ ret = -1;
+ }
+ ctx->active = false;
+ return ret;
+}
diff --git a/drivers/nxp/crypto/caam/src/auth/nxp_crypto.c b/drivers/nxp/crypto/caam/src/auth/nxp_crypto.c
new file mode 100644
index 0000000..646e981
--- /dev/null
+++ b/drivers/nxp/crypto/caam/src/auth/nxp_crypto.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stddef.h>
+#include <string.h>
+
+#include "caam.h"
+#include <common/debug.h>
+#include <drivers/auth/crypto_mod.h>
+
+#include "hash.h"
+#include "rsa.h"
+
+#define LIB_NAME "NXP crypto"
+
+/*
+ * Initialize the library and export the descriptor
+ */
+static void init(void)
+{
+ /* Initialize NXP crypto library`:*/
+ NOTICE("Initializing & configuring SEC block.\n");
+
+ if (config_sec_block() < 0) {
+ ERROR("Init & config failure for caam.\n");
+ }
+}
+
+/*
+ * Verify a signature.
+ *
+ * For IMG_PLAT - data points to a PKCS#1.5 encoded HASH
+ * sig_alg will be RSA or ECC
+ * Parameters are passed using the DER encoding format following the ASN.1
+ * structures detailed above.
+ */
+static int verify_signature(void *data_ptr, unsigned int data_len,
+ void *sig_ptr, unsigned int sig_len,
+ void *sign_alg, unsigned int sig_alg_len,
+ void *pk_ptr, unsigned int pk_len)
+{
+ int ret = CRYPTO_SUCCESS;
+
+ enum sig_alg alg = *(enum sig_alg *)sign_alg;
+
+ switch (alg) {
+ case RSA:
+ NOTICE("Verifying RSA\n");
+ ret = rsa_verify_signature(data_ptr, data_len, sig_ptr, sig_len,
+ pk_ptr, pk_len);
+ break;
+ case ECC:
+ default:
+ ret = CRYPTO_ERR_SIGNATURE;
+ break;
+ }
+
+ if (ret != 0) {
+ ERROR("RSA verification Failed\n");
+ }
+ return ret;
+
+}
+
+/*
+ * Match a hash
+ *
+ * Digest info is passed as a table of SHA-26 hashes and digest_info_len
+ * is number of entries in the table
+ * This implementation is very specific to the CSF header parser ROTPK
+ * comparison.
+ */
+static int verify_hash(void *data_ptr, unsigned int data_len,
+ void *digest_info_ptr, unsigned int digest_info_len)
+{
+ void *ctx = NULL;
+ int i = 0, ret = 0;
+ enum hash_algo algo = SHA256;
+ uint8_t hash[SHA256_BYTES] __aligned(CACHE_WRITEBACK_GRANULE) = {0};
+ uint32_t digest_size = SHA256_BYTES;
+ uint8_t *hash_tbl = digest_info_ptr;
+
+ NOTICE("Verifying hash\n");
+ ret = hash_init(algo, &ctx);
+ if (ret != 0) {
+ return CRYPTO_ERR_HASH;
+ }
+
+ /* Update hash with that of SRK table */
+ ret = hash_update(algo, ctx, data_ptr, data_len);
+ if (ret != 0) {
+ return CRYPTO_ERR_HASH;
+ }
+
+ /* Copy hash at destination buffer */
+ ret = hash_final(algo, ctx, hash, digest_size);
+ if (ret != 0) {
+ return CRYPTO_ERR_HASH;
+ }
+
+ VERBOSE("%s Calculated hash\n", __func__);
+ for (i = 0; i < SHA256_BYTES/4; i++) {
+ VERBOSE("%x\n", *((uint32_t *)hash + i));
+ }
+
+ for (i = 0; i < digest_info_len; i++) {
+ if (memcmp(hash, (hash_tbl + (i * digest_size)),
+ digest_size) == 0) {
+ return CRYPTO_SUCCESS;
+ }
+ }
+
+ return CRYPTO_ERR_HASH;
+}
+
+/*
+ * Register crypto library descriptor
+ */
+REGISTER_CRYPTO_LIB(LIB_NAME, init, verify_signature, verify_hash, NULL);
diff --git a/drivers/nxp/crypto/caam/src/auth/rsa.c b/drivers/nxp/crypto/caam/src/auth/rsa.c
new file mode 100644
index 0000000..0c44462
--- /dev/null
+++ b/drivers/nxp/crypto/caam/src/auth/rsa.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <arch_helpers.h>
+#include "caam.h"
+#include <common/debug.h>
+#include <drivers/auth/crypto_mod.h>
+
+#include "jobdesc.h"
+#include "rsa.h"
+#include "sec_hw_specific.h"
+
+/* This array contains DER value for SHA-256 */
+static const uint8_t hash_identifier[] = {
+ 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60,
+ 0x86, 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00,
+ 0x04, 0x20
+};
+
+static void rsa_done(uint32_t *desc, uint32_t status, void *arg,
+ void *job_ring)
+{
+ INFO("RSA Desc SUCCESS with status %x\n", status);
+}
+
+static int rsa_public_verif_sec(uint8_t *sign, uint8_t *to,
+ uint8_t *rsa_pub_key, uint32_t klen)
+{
+ int ret = 0;
+ struct rsa_context ctx __aligned(CACHE_WRITEBACK_GRANULE);
+ struct job_descriptor jobdesc __aligned(CACHE_WRITEBACK_GRANULE);
+
+ jobdesc.arg = NULL;
+ jobdesc.callback = rsa_done;
+
+ memset(&ctx, 0, sizeof(struct rsa_context));
+
+ ctx.pkin.a = sign;
+ ctx.pkin.a_siz = klen;
+ ctx.pkin.n = rsa_pub_key;
+ ctx.pkin.n_siz = klen;
+ ctx.pkin.e = rsa_pub_key + klen;
+ ctx.pkin.e_siz = klen;
+
+ cnstr_jobdesc_pkha_rsaexp(jobdesc.desc, &ctx.pkin, to, klen);
+
+#if defined(SEC_MEM_NON_COHERENT) && defined(IMAGE_BL2)
+ flush_dcache_range((uintptr_t)sign, klen);
+ flush_dcache_range((uintptr_t)rsa_pub_key, 2 * klen);
+ flush_dcache_range((uintptr_t)&ctx.pkin, sizeof(ctx.pkin));
+ inv_dcache_range((uintptr_t)to, klen);
+
+ dmbsy();
+ dsbsy();
+ isb();
+#endif
+
+ /* Finally, generate the requested random data bytes */
+ ret = run_descriptor_jr(&jobdesc);
+ if (ret != 0) {
+ ERROR("Error in running descriptor\n");
+ ret = -1;
+ }
+#if defined(SEC_MEM_NON_COHERENT) && defined(IMAGE_BL2)
+ inv_dcache_range((uintptr_t)to, klen);
+ dmbsy();
+ dsbsy();
+ isb();
+#endif
+ return ret;
+}
+
+/*
+ * Construct encoded hash EM' wrt PKCSv1.5. This function calculates the
+ * pointers for padding, DER value and hash. And finally, constructs EM'
+ * which includes hash of complete CSF header and ESBC image. If SG flag
+ * is on, hash of SG table and entries is also included.
+ */
+static int construct_img_encoded_hash_second(uint8_t *hash, uint8_t hash_len,
+ uint8_t *encoded_hash_second,
+ unsigned int key_len)
+{
+ /*
+ * RSA PKCSv1.5 encoding format for encoded message is below
+ * EM = 0x0 || 0x1 || PS || 0x0 || DER || Hash
+ * PS is Padding String
+ * DER is DER value for SHA-256
+ * Hash is SHA-256 hash
+ * *********************************************************
+ * representative points to first byte of EM initially and is
+ * filled with 0x0
+ * representative is incremented by 1 and second byte is filled
+ * with 0x1
+ * padding points to third byte of EM
+ * digest points to full length of EM - 32 bytes
+ * hash_id (DER value) points to 19 bytes before pDigest
+ * separator is one byte which separates padding and DER
+ */
+
+ unsigned int len;
+ uint8_t *representative;
+ uint8_t *padding, *digest;
+ uint8_t *hash_id, *separator;
+ int i;
+ int ret = 0;
+
+ if (hash_len != SHA256_BYTES) {
+ return -1;
+ }
+
+ /* Key length = Modulus length */
+ len = (key_len / 2U) - 1U;
+ representative = encoded_hash_second;
+ representative[0] = 0U;
+ representative[1] = 1U; /* block type 1 */
+
+ padding = &representative[2];
+ digest = &representative[1] + len - 32;
+ hash_id = digest - sizeof(hash_identifier);
+ separator = hash_id - 1;
+
+ /* fill padding area pointed by padding with 0xff */
+ memset(padding, 0xff, separator - padding);
+
+ /* fill byte pointed by separator */
+ *separator = 0U;
+
+ /* fill SHA-256 DER value pointed by HashId */
+ memcpy(hash_id, hash_identifier, sizeof(hash_identifier));
+
+ /* fill hash pointed by Digest */
+ for (i = 0; i < SHA256_BYTES; i++) {
+ digest[i] = hash[i];
+ }
+
+ return ret;
+}
+
+int rsa_verify_signature(void *hash_ptr, unsigned int hash_len,
+ void *sig_ptr, unsigned int sig_len,
+ void *pk_ptr, unsigned int pk_len)
+{
+ uint8_t img_encoded_hash_second[RSA_4K_KEY_SZ_BYTES];
+ uint8_t encoded_hash[RSA_4K_KEY_SZ_BYTES] __aligned(CACHE_WRITEBACK_GRANULE);
+ int ret = 0;
+
+ ret = construct_img_encoded_hash_second(hash_ptr, hash_len,
+ img_encoded_hash_second,
+ pk_len);
+ if (ret != 0) {
+ ERROR("Encoded Hash Failure\n");
+ return CRYPTO_ERR_SIGNATURE;
+ }
+
+ ret = rsa_public_verif_sec(sig_ptr, encoded_hash, pk_ptr, pk_len / 2);
+ if (ret != 0) {
+ ERROR("RSA signature Failure\n");
+ return CRYPTO_ERR_SIGNATURE;
+ }
+
+ ret = memcmp(img_encoded_hash_second, encoded_hash, sig_len);
+ if (ret != 0) {
+ ERROR("Comparison Failure\n");
+ return CRYPTO_ERR_SIGNATURE;
+ }
+
+ return CRYPTO_SUCCESS;
+}
diff --git a/drivers/nxp/crypto/caam/src/caam.c b/drivers/nxp/crypto/caam/src/caam.c
new file mode 100644
index 0000000..e594f7b
--- /dev/null
+++ b/drivers/nxp/crypto/caam/src/caam.c
@@ -0,0 +1,339 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <arch_helpers.h>
+#include "caam.h"
+#include <common/debug.h>
+#include "jobdesc.h"
+#include "sec_hw_specific.h"
+
+static uintptr_t g_nxp_caam_addr;
+static void *job_ring;
+
+uintptr_t get_caam_addr(void)
+{
+ if (g_nxp_caam_addr == 0) {
+ ERROR("Sec Init is not done.\n");
+ panic();
+ }
+ return g_nxp_caam_addr;
+}
+
+/* This function sets the TZ bit for the Job ring number passed as @num */
+static void config_tz(int num)
+{
+ uint32_t jricid;
+
+ /* Setting TZ bit of job ring */
+ switch (num) {
+ case 0:
+ jricid = sec_in32(g_nxp_caam_addr + SEC_REG_JR0ICIDR_MS_OFFSET);
+ sec_out32(g_nxp_caam_addr + SEC_REG_JR0ICIDR_MS_OFFSET,
+ jricid | JRICID_MS_TZ);
+ break;
+ case 1:
+ jricid = sec_in32(g_nxp_caam_addr + SEC_REG_JR1ICIDR_MS_OFFSET);
+ sec_out32(g_nxp_caam_addr + SEC_REG_JR1ICIDR_MS_OFFSET,
+ jricid | JRICID_MS_TZ);
+ break;
+ case 2:
+ jricid = sec_in32(g_nxp_caam_addr + SEC_REG_JR2ICIDR_MS_OFFSET);
+ sec_out32(g_nxp_caam_addr + SEC_REG_JR2ICIDR_MS_OFFSET,
+ jricid | JRICID_MS_TZ);
+ break;
+ case 3:
+ jricid = sec_in32(g_nxp_caam_addr + SEC_REG_JR3ICIDR_MS_OFFSET);
+ sec_out32(g_nxp_caam_addr + SEC_REG_JR3ICIDR_MS_OFFSET,
+ jricid | JRICID_MS_TZ);
+ break;
+ default:
+ break;
+ }
+}
+
+/* This function checks if Virtualization is enabled for JR and
+ * accordingly sets the bot for starting JR<num> in JRSTARTR register
+ */
+static inline void start_jr(int num)
+{
+ uint32_t ctpr = sec_in32((g_nxp_caam_addr + SEC_REG_CTPR_MS_OFFSET));
+ uint32_t tmp = sec_in32((g_nxp_caam_addr + SEC_REG_JRSTARTR_OFFSET));
+ uint32_t scfgr = sec_in32((g_nxp_caam_addr + SEC_REG_SCFGR_OFFSET));
+ bool start = false;
+
+ if ((ctpr & CTPR_VIRT_EN_INC) != 0U) {
+ if (((ctpr & CTPR_VIRT_EN_POR) != 0U) ||
+ ((scfgr & SCFGR_VIRT_EN) != 0U)) {
+ start = true;
+ }
+ } else {
+ if ((ctpr & CTPR_VIRT_EN_POR) != 0U) {
+ start = true;
+ }
+ }
+
+ if (start == true) {
+ switch (num) {
+ case 0:
+ tmp |= JRSTARTR_STARTJR0;
+ break;
+ case 1:
+ tmp |= JRSTARTR_STARTJR1;
+ break;
+ case 2:
+ tmp |= JRSTARTR_STARTJR2;
+ break;
+ case 3:
+ tmp |= JRSTARTR_STARTJR3;
+ break;
+ default:
+ break;
+ }
+ }
+ sec_out32((g_nxp_caam_addr + SEC_REG_JRSTARTR_OFFSET), tmp);
+}
+
+/* This functions configures the Job Ring
+ * JR3 is reserved for use by Secure world
+ */
+static int configure_jr(int num)
+{
+ int ret;
+ void *reg_base_addr;
+
+ switch (num) {
+ case 0:
+ reg_base_addr = (void *)(g_nxp_caam_addr + CAAM_JR0_OFFSET);
+ break;
+ case 1:
+ reg_base_addr = (void *)(g_nxp_caam_addr + CAAM_JR1_OFFSET);
+ break;
+ case 2:
+ reg_base_addr = (void *)(g_nxp_caam_addr + CAAM_JR2_OFFSET);
+ break;
+ case 3:
+ reg_base_addr = (void *)(g_nxp_caam_addr + CAAM_JR3_OFFSET);
+ break;
+ default:
+ break;
+ }
+
+ /* Initialize the JR library */
+ ret = sec_jr_lib_init();
+ if (ret != 0) {
+ ERROR("Error in sec_jr_lib_init");
+ return -1;
+ }
+
+ start_jr(num);
+
+ /* Do HW configuration of the JR */
+ job_ring = init_job_ring(SEC_NOTIFICATION_TYPE_POLL, 0, 0,
+ reg_base_addr, 0);
+
+ if (job_ring == NULL) {
+ ERROR("Error in init_job_ring");
+ return -1;
+ }
+
+ return ret;
+}
+
+/* TBD - Configures and locks the ICID values for various JR */
+static inline void configure_icid(void)
+{
+}
+
+/* TBD configures the TZ settings of RTIC */
+static inline void configure_rtic(void)
+{
+}
+
+int sec_init(uintptr_t nxp_caam_addr)
+{
+ g_nxp_caam_addr = nxp_caam_addr;
+ return config_sec_block();
+}
+
+/* This function configure SEC block:
+ * - It does basic parameter setting
+ * - Configures the default Job ring assigned to TZ /secure world
+ * - Instantiates the RNG
+ */
+int config_sec_block(void)
+{
+ int ret = 0;
+ uint32_t mcfgr;
+
+ if (g_nxp_caam_addr == 0) {
+ ERROR("Sec Init is not done.\n");
+ return -1;
+ } else if (job_ring != NULL) {
+ NOTICE("Sec is already initialized and configured.\n");
+ return ret;
+ }
+
+ mcfgr = sec_in32(g_nxp_caam_addr + SEC_REG_MCFGR_OFFSET);
+
+ /* Modify CAAM Read/Write attributes
+ * AXI Write - Cacheable, WB and WA
+ * AXI Read - Cacheable, RA
+ */
+#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS2088A)
+ mcfgr = (mcfgr & ~MCFGR_AWCACHE_MASK) | (0xb << MCFGR_AWCACHE_SHIFT);
+ mcfgr = (mcfgr & ~MCFGR_ARCACHE_MASK) | (0x6 << MCFGR_ARCACHE_SHIFT);
+#else
+ mcfgr = (mcfgr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT);
+#endif
+
+ /* Set PS bit to 1 */
+#ifdef CONFIG_PHYS_64BIT
+ mcfgr |= (1 << MCFGR_PS_SHIFT);
+#endif
+ sec_out32(g_nxp_caam_addr + SEC_REG_MCFGR_OFFSET, mcfgr);
+
+ /* Asssign ICID to all Job rings and lock them for usage */
+ configure_icid();
+
+ /* Configure the RTIC */
+ configure_rtic();
+
+ /* Configure the default JR for usage */
+ ret = configure_jr(DEFAULT_JR);
+ if (ret != 0) {
+ ERROR("\nFSL_JR: configuration failure\n");
+ return -1;
+ }
+ /* Do TZ configuration of default JR for sec firmware */
+ config_tz(DEFAULT_JR);
+
+#ifdef CONFIG_RNG_INIT
+ /* Instantiate the RNG */
+ ret = hw_rng_instantiate();
+ if (ret != 0) {
+ ERROR("\nRNG Instantiation failure\n");
+ return -1;
+ }
+#endif
+
+ return ret;
+}
+
+/* This function is used for sumbitting job to the Job Ring
+ * [param] [in] - jobdesc to be submitted
+ * Return - -1 in case of error and 0 in case of SUCCESS
+ */
+int run_descriptor_jr(struct job_descriptor *jobdesc)
+{
+ int i = 0, ret = 0;
+ uint32_t *desc_addr = jobdesc->desc;
+ uint32_t desc_len = desc_length(jobdesc->desc);
+ uint32_t desc_word;
+
+ for (i = 0; i < desc_len; i++) {
+ desc_word = desc_addr[i];
+ VERBOSE("%x\n", desc_word);
+ sec_out32((uint32_t *)&desc_addr[i], desc_word);
+ }
+ dsb();
+
+#if defined(SEC_MEM_NON_COHERENT) && defined(IMAGE_BL2)
+ flush_dcache_range((uintptr_t)desc_addr, desc_len * 4);
+ dmbsy();
+ dsbsy();
+ isb();
+#endif
+
+ ret = enq_jr_desc(job_ring, jobdesc);
+ if (ret == 0) {
+ VERBOSE("JR enqueue done...\n");
+ } else {
+ ERROR("Error in Enqueue\n");
+ return ret;
+ }
+
+ VERBOSE("Dequeue in progress");
+
+ ret = dequeue_jr(job_ring, -1);
+ if (ret >= 0) {
+ VERBOSE("Dequeue of %x desc success\n", ret);
+ ret = 0;
+ } else {
+ ERROR("deq_ret %x\n", ret);
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/* this function returns a random number using HW RNG Algo
+ * In case of failure, random number returned is 0
+ * prngWidth = 0 - 32 bit random number
+ * prngWidth > 0 means 64 bit random number
+ */
+unsigned long long get_random(int rngWidth)
+{
+ unsigned long long result = 0;
+ uint8_t rand_byte[64] __aligned(CACHE_WRITEBACK_GRANULE);
+ uint8_t rand_byte_swp[8];
+ int bytes = 0;
+ int i = 0;
+ int ret = 0;
+
+#ifdef CAAM_TEST
+ rand_byte[0] = U(0x12);
+ rand_byte[1] = U(0x34);
+ rand_byte[2] = U(0x56);
+ rand_byte[3] = U(0x78);
+ rand_byte[4] = U(0x9a);
+ rand_byte[5] = U(0xbc);
+ rand_byte[6] = U(0xde);
+ rand_byte[7] = U(0xf1);
+#endif
+
+ if (rngWidth == 0U) {
+ bytes = 4;
+ } else {
+ bytes = 8;
+ }
+
+ memset(rand_byte, 0, 64);
+
+ ret = get_rand_bytes_hw(rand_byte, bytes);
+
+ for (i = 0; i < bytes; i++) {
+ if (ret != 0) {
+ /* Return 0 in case of failure */
+ rand_byte_swp[i] = 0;
+ } else {
+ rand_byte_swp[i] = rand_byte[bytes - i - 1];
+ result = (result << 8) | rand_byte_swp[i];
+ }
+ }
+
+ INFO("result %llx\n", result);
+
+ return result;
+
+} /* _get_RNG() */
+
+unsigned int _get_hw_unq_key(uint64_t hw_key_phy_addr, unsigned int size)
+{
+ int ret = 0;
+ uint8_t *hw_key = (uint8_t *) ptov((phys_addr_t *) hw_key_phy_addr);
+
+ ret = get_hw_unq_key_blob_hw(hw_key, size);
+
+ return ret;
+}
diff --git a/drivers/nxp/crypto/caam/src/hw_key_blob.c b/drivers/nxp/crypto/caam/src/hw_key_blob.c
new file mode 100644
index 0000000..0720695
--- /dev/null
+++ b/drivers/nxp/crypto/caam/src/hw_key_blob.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "caam.h"
+#include <common/debug.h>
+#include "jobdesc.h"
+#include "sec_hw_specific.h"
+
+
+/* Callback function after Instantiation decsriptor is submitted to SEC
+ */
+static void blob_done(uint32_t *desc, uint32_t status, void *arg,
+ void *job_ring)
+{
+ INFO("Blob Desc SUCCESS with status %x\n", status);
+}
+
+/* @brief Submit descriptor to create blob
+ * @retval 0 on success
+ * @retval -1 on error
+ */
+int get_hw_unq_key_blob_hw(uint8_t *hw_key, int size)
+{
+ int ret = 0;
+ int i = 0;
+
+ uint32_t key_sz = KEY_IDNFR_SZ_BYTES;
+ uint8_t key_data[KEY_IDNFR_SZ_BYTES];
+ uint8_t in_data[16];
+ uint8_t out_data[16 + KEY_BLOB_SIZE + MAC_SIZE];
+ struct job_descriptor desc __aligned(CACHE_WRITEBACK_GRANULE);
+ struct job_descriptor *jobdesc = &desc;
+ uint32_t in_sz = 16U;
+
+ /* Output blob will have 32 bytes key blob in beginning and
+ * 16 byte HMAC identifier at end of data blob
+ */
+ uint32_t out_sz = in_sz + KEY_BLOB_SIZE + MAC_SIZE;
+
+ uint32_t operation = CMD_OPERATION | OP_TYPE_ENCAP_PROTOCOL |
+ OP_PCLID_BLOB | BLOB_PROTO_INFO;
+
+ memset(key_data, 0xff, KEY_IDNFR_SZ_BYTES);
+ memset(in_data, 0x00, in_sz);
+ memset(out_data, 0x00, in_sz);
+
+ jobdesc->arg = NULL;
+ jobdesc->callback = blob_done;
+
+ INFO("\nGenerating Master Key Verification Blob.\n");
+
+ /* Create the hw_rng descriptor */
+ ret = cnstr_hw_encap_blob_jobdesc(jobdesc->desc, key_data, key_sz,
+ CLASS_2, in_data, in_sz, out_data,
+ out_sz, operation);
+
+ /* Finally, generate the blob. */
+ ret = run_descriptor_jr(jobdesc);
+ if (ret != 0) {
+ ERROR("Error in running hw unq key blob descriptor\n");
+ return -1;
+ }
+ /* Copying alternate bytes of the Master Key Verification Blob.
+ */
+ for (i = 0; i < size; i++) {
+ hw_key[i] = out_data[2 * i];
+ }
+
+ return ret;
+}
diff --git a/drivers/nxp/crypto/caam/src/jobdesc.c b/drivers/nxp/crypto/caam/src/jobdesc.c
new file mode 100644
index 0000000..9c235af
--- /dev/null
+++ b/drivers/nxp/crypto/caam/src/jobdesc.c
@@ -0,0 +1,236 @@
+/*
+ * Copyright 2017-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "caam.h"
+#include <common/debug.h>
+#include "jobdesc.h"
+#include "rsa.h"
+#include "sec_hw_specific.h"
+
+
+/* Return Length of desctiptr from first word */
+uint32_t desc_length(uint32_t *desc)
+{
+ return desc[0] & DESC_LEN_MASK;
+}
+
+/*Update start index in first word of descriptor */
+void desc_update_start_index(uint32_t *desc, uint32_t index)
+{
+ desc[0] |= (index << DESC_START_SHIFT);
+}
+
+/* Initialize the descriptor */
+void desc_init(uint32_t *desc)
+{
+ *desc = 0;
+}
+
+/* Add word in the descriptor and increment the length */
+void desc_add_word(uint32_t *desc, uint32_t word)
+{
+ uint32_t len = desc_length(desc);
+
+ /* Add Word at Last */
+ uint32_t *last = desc + len;
+ *last = word;
+
+ /* Increase the length */
+ desc[0] += 1;
+}
+
+/* Add Pointer to the descriptor */
+void desc_add_ptr(uint32_t *desc, phys_addr_t *ptr)
+{
+ uint32_t len = desc_length(desc);
+
+ /* Add Word at Last */
+ phys_addr_t *last = (phys_addr_t *) (desc + len);
+
+#ifdef CONFIG_PHYS_64BIT
+ ptr_addr_t *ptr_addr = (ptr_addr_t *) last;
+
+ ptr_addr->m_halves.high = PHYS_ADDR_HI(ptr);
+ ptr_addr->m_halves.low = PHYS_ADDR_LO(ptr);
+#else
+ *last = ptr;
+#endif
+
+ /* Increase the length */
+ desc[0] += (uint32_t) (sizeof(phys_addr_t) / sizeof(uint32_t));
+}
+
+/* Descriptor to generate Random words */
+int cnstr_rng_jobdesc(uint32_t *desc, uint32_t state_handle,
+ uint32_t *add_inp, uint32_t add_ip_len,
+ uint8_t *out_data, uint32_t len)
+{
+ phys_addr_t *phys_addr_out = vtop(out_data);
+
+ /* Current descriptor support only 64K length */
+ if (len > U(0xffff))
+ return -1;
+ /* Additional Input not supported by current descriptor */
+ if (add_ip_len > 0U)
+ return -1;
+
+ VERBOSE("Constructing descriptor\n");
+ desc_init(desc);
+ /* Class1 Alg Operation,RNG Optype, Generate */
+ desc_add_word(desc, U(0xb0800000));
+ desc_add_word(desc, U(0x82500000) | (state_handle << ALG_AAI_SH_SHIFT));
+ desc_add_word(desc, U(0x60340000) | len);
+ desc_add_ptr(desc, phys_addr_out);
+
+ return 0;
+
+}
+
+/* Construct descriptor to instantiate RNG */
+int cnstr_rng_instantiate_jobdesc(uint32_t *desc)
+{
+ desc_init(desc);
+ desc_add_word(desc, U(0xb0800000));
+ /* Class1 Alg Operation,RNG Optype, Instantiate */
+ desc_add_word(desc, U(0x82500004));
+ /* Wait for done */
+ desc_add_word(desc, U(0xa2000001));
+ /*Load to clear written */
+ desc_add_word(desc, U(0x10880004));
+ /*Pri Mode Reg clear */
+ desc_add_word(desc, U(0x00000001));
+ /* Generate secure keys */
+ desc_add_word(desc, U(0x82501000));
+
+ return 0;
+}
+
+/* Construct descriptor to generate hw key blob */
+int cnstr_hw_encap_blob_jobdesc(uint32_t *desc,
+ uint8_t *key_idnfr, uint32_t key_sz,
+ uint32_t key_class, uint8_t *plain_txt,
+ uint32_t in_sz, uint8_t *enc_blob,
+ uint32_t out_sz, uint32_t operation)
+{
+ phys_addr_t *phys_key_idnfr, *phys_addr_in, *phys_addr_out;
+ int i = 0;
+
+ phys_key_idnfr = vtop((void *)key_idnfr);
+ phys_addr_in = vtop((void *)plain_txt);
+ phys_addr_out = vtop((void *)enc_blob);
+
+ desc_init(desc);
+
+ desc_add_word(desc, U(0xb0800000));
+
+ /* Key Identifier */
+ desc_add_word(desc, (key_class | key_sz));
+ desc_add_ptr(desc, phys_key_idnfr);
+
+ /* Source Address */
+ desc_add_word(desc, U(0xf0400000));
+ desc_add_ptr(desc, phys_addr_in);
+
+ /* In Size = 0x10 */
+ desc_add_word(desc, in_sz);
+
+ /* Out Address */
+ desc_add_word(desc, U(0xf8400000));
+ desc_add_ptr(desc, phys_addr_out);
+
+ /* Out Size = 0x10 */
+ desc_add_word(desc, out_sz);
+
+ /* Operation */
+ desc_add_word(desc, operation);
+
+ for (i = 0; i < 15; i++)
+ VERBOSE("desc word %x\n", desc[i]);
+
+ return 0;
+}
+
+/***************************************************************************
+ * Function : inline_cnstr_jobdesc_pkha_rsaexp
+ * Arguments : desc - Pointer to Descriptor
+ * pkin - Pointer to Input Params
+ * out - Pointer to Output
+ * out_siz - Output Size
+ * Return : Void
+ * Description : Creates the descriptor for PKHA RSA
+ ***************************************************************************/
+void cnstr_jobdesc_pkha_rsaexp(uint32_t *desc,
+ struct pk_in_params *pkin, uint8_t *out,
+ uint32_t out_siz)
+{
+ phys_addr_t *ptr_addr_e, *ptr_addr_a, *ptr_addr_n, *ptr_addr_out;
+
+ ptr_addr_e = vtop((void *)(pkin->e));
+ ptr_addr_a = vtop((void *)(pkin->a));
+ ptr_addr_n = vtop((void *)(pkin->n));
+ ptr_addr_out = vtop((void *)(out));
+
+ desc_init(desc);
+ desc_add_word(desc, U(0xb0800000));
+ desc_add_word(desc, U(0x02010000) | pkin->e_siz);
+ desc_add_ptr(desc, ptr_addr_e);
+ desc_add_word(desc, U(0x220c0000) | pkin->a_siz);
+ desc_add_ptr(desc, ptr_addr_a);
+ desc_add_word(desc, U(0x22080000) | pkin->n_siz);
+ desc_add_ptr(desc, ptr_addr_n);
+ desc_add_word(desc, U(0x81800006));
+ desc_add_word(desc, U(0x620d0000) | out_siz);
+ desc_add_ptr(desc, ptr_addr_out);
+}
+
+/***************************************************************************
+ * Function : inline_cnstr_jobdesc_sha256
+ * Arguments : desc - Pointer to Descriptor
+ * msg - Pointer to SG Table
+ * msgsz - Size of SG Table
+ * digest - Pointer to Output Digest
+ * Return : Void
+ * Description : Creates the descriptor for SHA256 HASH calculation
+ ***************************************************************************/
+void cnstr_hash_jobdesc(uint32_t *desc, uint8_t *msg, uint32_t msgsz,
+ uint8_t *digest)
+{
+ /* SHA 256 , output is of length 32 words */
+ phys_addr_t *ptr_addr_in, *ptr_addr_out;
+
+ ptr_addr_in = (void *)vtop(msg);
+ ptr_addr_out = (void *)vtop(digest);
+
+ desc_init(desc);
+ desc_add_word(desc, U(0xb0800000));
+
+ /* Operation Command
+ * OP_TYPE_CLASS2_ALG | OP_ALG_ALGSEL_SHA256 | OP_ALG_AAI_HASH |
+ * OP_ALG_AS_INITFINAL | OP_ALG_ENCRYPT | OP_ALG_ICV_OFF)
+ */
+ desc_add_word(desc, U(0x8443000d));
+
+ if (msgsz > U(0xffff)) {
+ desc_add_word(desc, U(0x25540000)); /* FIFO Load */
+ desc_add_ptr(desc, ptr_addr_in); /* Pointer to msg */
+ desc_add_word(desc, msgsz); /* Size */
+ desc_add_word(desc, U(0x54200020)); /* FIFO Store */
+ desc_add_ptr(desc, ptr_addr_out); /* Pointer to Result */
+ } else {
+ desc_add_word(desc, U(0x25140000) | msgsz);
+ desc_add_ptr(desc, ptr_addr_in);
+ desc_add_word(desc, U(0x54200020));
+ desc_add_ptr(desc, ptr_addr_out);
+ }
+
+}
diff --git a/drivers/nxp/crypto/caam/src/rng.c b/drivers/nxp/crypto/caam/src/rng.c
new file mode 100644
index 0000000..0b9d87d
--- /dev/null
+++ b/drivers/nxp/crypto/caam/src/rng.c
@@ -0,0 +1,251 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <arch_helpers.h>
+#include "caam.h"
+#include <common/debug.h>
+#include "jobdesc.h"
+#include "sec_hw_specific.h"
+
+
+/* Callback function after Instantiation decsriptor is submitted to SEC */
+static void rng_done(uint32_t *desc, uint32_t status, void *arg,
+ void *job_ring)
+{
+ INFO("RNG Desc SUCCESS with status %x\n", status);
+}
+
+/* Is the HW RNG instantiated?
+ * Return code:
+ * 0 - Not in the instantiated state
+ * 1 - In the instantiated state
+ * state_handle - 0 for SH0, 1 for SH1
+ */
+static int is_hw_rng_instantiated(uint32_t *state_handle)
+{
+ int ret_code = 0;
+ uint32_t rdsta;
+
+ rdsta = sec_in32(get_caam_addr() + RNG_REG_RDSTA_OFFSET);
+
+ /*Check if either of the two state handles has been instantiated */
+ if (rdsta & RNG_STATE0_HANDLE_INSTANTIATED) {
+ *state_handle = 0;
+ ret_code = 1;
+ } else if (rdsta & RNG_STATE0_HANDLE_INSTANTIATED) {
+ *state_handle = 1;
+ ret_code = 1;
+ }
+
+ return ret_code;
+}
+
+/* @brief Kick the TRNG block of the RNG HW Engine
+ * @param [in] ent_delay Entropy delay to be used
+ * By default, the TRNG runs for 200 clocks per sample;
+ * 1200 clocks per sample generates better entropy.
+ * @retval 0 on success
+ * @retval -1 on error
+ */
+static void kick_trng(int ent_delay)
+{
+ uint32_t val;
+
+ /* put RNG4 into program mode */
+ val = sec_in32(get_caam_addr() + RNG_REG_RTMCTL_OFFSET);
+ val = val | RTMCTL_PRGM;
+ sec_out32(get_caam_addr() + RNG_REG_RTMCTL_OFFSET, val);
+
+ /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
+ * length (in system clocks) of each Entropy sample taken
+ */
+ val = sec_in32(get_caam_addr() + RNG_REG_RTSDCTL_OFFSET);
+ val = (val & ~RTSDCTL_ENT_DLY_MASK) |
+ (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
+ sec_out32(get_caam_addr() + RNG_REG_RTSDCTL_OFFSET, val);
+ /* min. freq. count, equal to 1/4 of the entropy sample length */
+ sec_out32(get_caam_addr() + RNG_REG_RTFRQMIN_OFFSET, ent_delay >> 2);
+ /* disable maximum frequency count */
+ sec_out32(get_caam_addr() + RNG_REG_RTFRQMAX_OFFSET, RTFRQMAX_DISABLE);
+
+ /* select raw sampling in both entropy shifter
+ * and statistical checker
+ */
+ val = sec_in32(get_caam_addr() + RNG_REG_RTMCTL_OFFSET);
+ val = val | RTMCTL_SAMP_MODE_RAW_ES_SC;
+ sec_out32(get_caam_addr() + RNG_REG_RTMCTL_OFFSET, val);
+
+ /* put RNG4 into run mode */
+ val = sec_in32(get_caam_addr() + RNG_REG_RTMCTL_OFFSET);
+ val = val & ~RTMCTL_PRGM;
+ sec_out32(get_caam_addr() + RNG_REG_RTMCTL_OFFSET, val);
+}
+
+/* @brief Submit descriptor to instantiate the RNG
+ * @retval 0 on success
+ * @retval -1 on error
+ */
+static int instantiate_rng(void)
+{
+ int ret = 0;
+ struct job_descriptor desc __aligned(CACHE_WRITEBACK_GRANULE);
+ struct job_descriptor *jobdesc = &desc;
+
+ jobdesc->arg = NULL;
+ jobdesc->callback = rng_done;
+
+ /* create the hw_rng descriptor */
+ cnstr_rng_instantiate_jobdesc(jobdesc->desc);
+
+ /* Finally, generate the requested random data bytes */
+ ret = run_descriptor_jr(jobdesc);
+ if (ret != 0) {
+ ERROR("Error in running descriptor\n");
+ ret = -1;
+ }
+ return ret;
+}
+
+/* Generate Random Data using HW RNG
+ * Parameters:
+ * uint8_t* add_input - user specified optional input byte array
+ * uint32_t add_input_len - number of bytes of additional input
+ * uint8_t* out - user specified output byte array
+ * uint32_t out_len - number of bytes to store in output byte array
+ * Return code:
+ * 0 - SUCCESS
+ * -1 - ERROR
+ */
+static int
+hw_rng_generate(uint32_t *add_input, uint32_t add_input_len,
+ uint8_t *out, uint32_t out_len, uint32_t state_handle)
+{
+ int ret = 0;
+ struct job_descriptor desc __aligned(CACHE_WRITEBACK_GRANULE);
+ struct job_descriptor *jobdesc = &desc;
+
+ jobdesc->arg = NULL;
+ jobdesc->callback = rng_done;
+
+#if defined(SEC_MEM_NON_COHERENT) && defined(IMAGE_BL2)
+ inv_dcache_range((uintptr_t)out, out_len);
+ dmbsy();
+#endif
+
+ /* create the hw_rng descriptor */
+ ret = cnstr_rng_jobdesc(jobdesc->desc, state_handle,
+ add_input, add_input_len, out, out_len);
+ if (ret != 0) {
+ ERROR("Descriptor construction failed\n");
+ ret = -1;
+ goto out;
+ }
+ /* Finally, generate the requested random data bytes */
+ ret = run_descriptor_jr(jobdesc);
+ if (ret != 0) {
+ ERROR("Error in running descriptor\n");
+ ret = -1;
+ }
+
+out:
+ return ret;
+}
+
+/* this function instantiates the rng
+ *
+ * Return code:
+ * 0 - All is well
+ * <0 - Error occurred somewhere
+ */
+int hw_rng_instantiate(void)
+{
+ int ret = 0;
+ int ent_delay = RTSDCTL_ENT_DLY_MIN;
+ uint32_t state_handle;
+
+ ret = is_hw_rng_instantiated(&state_handle);
+ if (ret != 0) {
+ NOTICE("RNG already instantiated\n");
+ return 0;
+ }
+ do {
+ kick_trng(ent_delay);
+ ent_delay += 400;
+ /*if instantiate_rng(...) fails, the loop will rerun
+ *and the kick_trng(...) function will modify the
+ *upper and lower limits of the entropy sampling
+ *interval, leading to a sucessful initialization of
+ */
+ ret = instantiate_rng();
+ } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
+ if (ret != 0) {
+ ERROR("RNG: Failed to instantiate RNG\n");
+ return ret;
+ }
+
+ NOTICE("RNG: INSTANTIATED\n");
+
+ /* Enable RDB bit so that RNG works faster */
+ // sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE);
+
+ return ret;
+}
+
+/* Generate random bytes, and stuff them into the bytes buffer
+ *
+ * If the HW RNG has not already been instantiated,
+ * it will be instantiated before data is generated.
+ *
+ * Parameters:
+ * uint8_t* bytes - byte buffer large enough to hold the requested random date
+ * int byte_len - number of random bytes to generate
+ *
+ * Return code:
+ * 0 - All is well
+ * ~0 - Error occurred somewhere
+ */
+int get_rand_bytes_hw(uint8_t *bytes, int byte_len)
+{
+ int ret_code = 0;
+ uint32_t state_handle;
+
+ /* If this is the first time this routine is called,
+ * then the hash_drbg will not already be instantiated.
+ * Therefore, before generating data, instantiate the hash_drbg
+ */
+ ret_code = is_hw_rng_instantiated(&state_handle);
+ if (ret_code == 0) {
+ INFO("Instantiating the HW RNG\n");
+
+ /* Instantiate the hw RNG */
+ ret_code = hw_rng_instantiate();
+ if (ret_code != 0) {
+ ERROR("HW RNG Instantiate failed\n");
+ return ret_code;
+ }
+ }
+ /* If HW RNG is still not instantiated, something must have gone wrong,
+ * it must be in the error state, we will not generate any random data
+ */
+ if (is_hw_rng_instantiated(&state_handle) == 0) {
+ ERROR("HW RNG is in an Error state, and cannot be used\n");
+ return -1;
+ }
+ /* Generate a random 256-bit value, as 32 bytes */
+ ret_code = hw_rng_generate(0, 0, bytes, byte_len, state_handle);
+ if (ret_code != 0) {
+ ERROR("HW RNG Generate failed\n");
+ return ret_code;
+ }
+
+ return ret_code;
+}
diff --git a/drivers/nxp/crypto/caam/src/sec_hw_specific.c b/drivers/nxp/crypto/caam/src/sec_hw_specific.c
new file mode 100644
index 0000000..92b7762
--- /dev/null
+++ b/drivers/nxp/crypto/caam/src/sec_hw_specific.c
@@ -0,0 +1,635 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <arch_helpers.h>
+#include "caam.h"
+#include <common/debug.h>
+#include "jobdesc.h"
+#include "sec_hw_specific.h"
+
+
+/* Job rings used for communication with SEC HW */
+extern struct sec_job_ring_t g_job_rings[MAX_SEC_JOB_RINGS];
+
+/* The current state of SEC user space driver */
+extern volatile sec_driver_state_t g_driver_state;
+
+/* The number of job rings used by SEC user space driver */
+extern int g_job_rings_no;
+
+/* LOCAL FUNCTIONS */
+static inline void hw_set_input_ring_start_addr(struct jobring_regs *regs,
+ phys_addr_t *start_addr)
+{
+#if defined(CONFIG_PHYS_64BIT)
+ sec_out32(®s->irba_h, PHYS_ADDR_HI(start_addr));
+#else
+ sec_out32(®s->irba_h, 0);
+#endif
+ sec_out32(®s->irba_l, PHYS_ADDR_LO(start_addr));
+}
+
+static inline void hw_set_output_ring_start_addr(struct jobring_regs *regs,
+ phys_addr_t *start_addr)
+{
+#if defined(CONFIG_PHYS_64BIT)
+ sec_out32(®s->orba_h, PHYS_ADDR_HI(start_addr));
+#else
+ sec_out32(®s->orba_h, 0);
+#endif
+ sec_out32(®s->orba_l, PHYS_ADDR_LO(start_addr));
+}
+
+/* ORJR - Output Ring Jobs Removed Register shows how many jobs were
+ * removed from the Output Ring for processing by software. This is done after
+ * the software has processed the entries.
+ */
+static inline void hw_remove_entries(sec_job_ring_t *jr, int num)
+{
+ struct jobring_regs *regs =
+ (struct jobring_regs *)jr->register_base_addr;
+
+ sec_out32(®s->orjr, num);
+}
+
+/* IRSA - Input Ring Slots Available register holds the number of entries in
+ * the Job Ring's input ring. Once a job is enqueued, the value returned is
+ * decremented by the hardware by the number of jobs enqueued.
+ */
+static inline int hw_get_available_slots(sec_job_ring_t *jr)
+{
+ struct jobring_regs *regs =
+ (struct jobring_regs *)jr->register_base_addr;
+
+ return sec_in32(®s->irsa);
+}
+
+/* ORSFR - Output Ring Slots Full register holds the number of jobs which were
+ * processed by the SEC and can be retrieved by the software. Once a job has
+ * been processed by software, the user will call hw_remove_one_entry in order
+ * to notify the SEC that the entry was processed
+ */
+static inline int hw_get_no_finished_jobs(sec_job_ring_t *jr)
+{
+ struct jobring_regs *regs =
+ (struct jobring_regs *)jr->register_base_addr;
+
+ return sec_in32(®s->orsf);
+}
+
+/* @brief Process Jump Halt Condition related errors
+ * @param [in] error_code The error code in the descriptor status word
+ */
+static inline void hw_handle_jmp_halt_cond_err(union hw_error_code error_code)
+{
+ ERROR("JMP %x\n", error_code.error_desc.jmp_halt_cond_src.jmp);
+ ERROR("Descriptor Index: %d\n",
+ error_code.error_desc.jmp_halt_cond_src.desc_idx);
+ ERROR(" Condition %x\n", error_code.error_desc.jmp_halt_cond_src.cond);
+}
+
+/* @brief Process DECO related errors
+ * @param [in] error_code The error code in the descriptor status word
+ */
+static inline void hw_handle_deco_err(union hw_error_code error_code)
+{
+ ERROR("JMP %x\n", error_code.error_desc.deco_src.jmp);
+ ERROR("Descriptor Index: 0x%x",
+ error_code.error_desc.deco_src.desc_idx);
+
+ switch (error_code.error_desc.deco_src.desc_err) {
+ case SEC_HW_ERR_DECO_HFN_THRESHOLD:
+ WARN(" Descriptor completed but exceeds the Threshold");
+ break;
+ default:
+ ERROR("Error 0x%04x not implemented",
+ error_code.error_desc.deco_src.desc_err);
+ break;
+ }
+}
+
+/* @brief Process Jump Halt User Status related errors
+ * @param [in] error_code The error code in the descriptor status word
+ */
+static inline void hw_handle_jmp_halt_user_err(union hw_error_code error_code)
+{
+ WARN(" Not implemented");
+}
+
+/* @brief Process CCB related errors
+ * @param [in] error_code The error code in the descriptor status word
+ */
+static inline void hw_handle_ccb_err(union hw_error_code hw_error_code)
+{
+ WARN(" Not implemented");
+}
+
+/* @brief Process Job Ring related errors
+ * @param [in] error_code The error code in the descriptor status word
+ */
+static inline void hw_handle_jr_err(union hw_error_code hw_error_code)
+{
+ WARN(" Not implemented");
+}
+
+/* GLOBAL FUNCTIONS */
+
+int hw_reset_job_ring(sec_job_ring_t *job_ring)
+{
+ int ret = 0;
+ struct jobring_regs *regs =
+ (struct jobring_regs *)job_ring->register_base_addr;
+
+ /* First reset the job ring in hw */
+ ret = hw_shutdown_job_ring(job_ring);
+ if (ret != 0) {
+ ERROR("Failed resetting job ring in hardware");
+ return ret;
+ }
+ /* In order to have the HW JR in a workable state
+ *after a reset, I need to re-write the input
+ * queue size, input start address, output queue
+ * size and output start address
+ * Write the JR input queue size to the HW register
+ */
+ sec_out32(®s->irs, SEC_JOB_RING_SIZE);
+
+ /* Write the JR output queue size to the HW register */
+ sec_out32(®s->ors, SEC_JOB_RING_SIZE);
+
+ /* Write the JR input queue start address */
+ hw_set_input_ring_start_addr(regs, vtop(job_ring->input_ring));
+
+ /* Write the JR output queue start address */
+ hw_set_output_ring_start_addr(regs, vtop(job_ring->output_ring));
+
+ return 0;
+}
+
+int hw_shutdown_job_ring(sec_job_ring_t *job_ring)
+{
+ struct jobring_regs *regs =
+ (struct jobring_regs *)job_ring->register_base_addr;
+ unsigned int timeout = SEC_TIMEOUT;
+ uint32_t tmp = 0U;
+
+ VERBOSE("Resetting Job ring\n");
+
+ /*
+ * Mask interrupts since we are going to poll
+ * for reset completion status
+ * Also, at POR, interrupts are ENABLED on a JR, thus
+ * this is the point where I can disable them without
+ * changing the code logic too much
+ */
+
+ jr_disable_irqs(job_ring);
+
+ /* initiate flush (required prior to reset) */
+ sec_out32(®s->jrcr, JR_REG_JRCR_VAL_RESET);
+
+ /* dummy read */
+ tmp = sec_in32(®s->jrcr);
+
+ do {
+ tmp = sec_in32(®s->jrint);
+ } while (((tmp & JRINT_ERR_HALT_MASK) ==
+ JRINT_ERR_HALT_INPROGRESS) && ((--timeout) != 0U));
+
+ if ((tmp & JRINT_ERR_HALT_MASK) != JRINT_ERR_HALT_COMPLETE ||
+ timeout == 0U) {
+ ERROR("Failed to flush hw job ring %x\n %u", tmp, timeout);
+ /* unmask interrupts */
+ if (job_ring->jr_mode != SEC_NOTIFICATION_TYPE_POLL) {
+ jr_enable_irqs(job_ring);
+ }
+ return -1;
+ }
+ /* Initiate reset */
+ timeout = SEC_TIMEOUT;
+ sec_out32(®s->jrcr, JR_REG_JRCR_VAL_RESET);
+
+ do {
+ tmp = sec_in32(®s->jrcr);
+ } while (((tmp & JR_REG_JRCR_VAL_RESET) != 0U) &&
+ ((--timeout) != 0U));
+
+ if (timeout == 0U) {
+ ERROR("Failed to reset hw job ring\n");
+ /* unmask interrupts */
+ if (job_ring->jr_mode != SEC_NOTIFICATION_TYPE_POLL) {
+ jr_enable_irqs(job_ring);
+ }
+ return -1;
+ }
+ /* unmask interrupts */
+ if (job_ring->jr_mode != SEC_NOTIFICATION_TYPE_POLL) {
+ jr_enable_irqs(job_ring);
+ }
+ return 0;
+
+}
+
+void hw_handle_job_ring_error(sec_job_ring_t *job_ring, uint32_t error_code)
+{
+ union hw_error_code hw_err_code;
+
+ hw_err_code.error = error_code;
+
+ switch (hw_err_code.error_desc.value.ssrc) {
+ case SEC_HW_ERR_SSRC_NO_SRC:
+ INFO("No Status Source ");
+ break;
+ case SEC_HW_ERR_SSRC_CCB_ERR:
+ INFO("CCB Status Source");
+ hw_handle_ccb_err(hw_err_code);
+ break;
+ case SEC_HW_ERR_SSRC_JMP_HALT_U:
+ INFO("Jump Halt User Status Source");
+ hw_handle_jmp_halt_user_err(hw_err_code);
+ break;
+ case SEC_HW_ERR_SSRC_DECO:
+ INFO("DECO Status Source");
+ hw_handle_deco_err(hw_err_code);
+ break;
+ case SEC_HW_ERR_SSRC_JR:
+ INFO("Job Ring Status Source");
+ hw_handle_jr_err(hw_err_code);
+ break;
+ case SEC_HW_ERR_SSRC_JMP_HALT_COND:
+ INFO("Jump Halt Condition Codes");
+ hw_handle_jmp_halt_cond_err(hw_err_code);
+ break;
+ default:
+ INFO("Unknown SSRC");
+ break;
+ }
+}
+
+int hw_job_ring_error(sec_job_ring_t *job_ring)
+{
+ uint32_t jrint_error_code;
+ struct jobring_regs *regs =
+ (struct jobring_regs *)job_ring->register_base_addr;
+
+ if (JR_REG_JRINT_JRE_EXTRACT(sec_in32(®s->jrint)) == 0) {
+ return 0;
+ }
+
+ jrint_error_code =
+ JR_REG_JRINT_ERR_TYPE_EXTRACT(sec_in32(®s->jrint));
+ switch (jrint_error_code) {
+ case JRINT_ERR_WRITE_STATUS:
+ ERROR("Error writing status to Output Ring ");
+ break;
+ case JRINT_ERR_BAD_INPUT_BASE:
+ ERROR("Bad Input Ring Base (not on a 4-byte boundary)\n");
+ break;
+ case JRINT_ERR_BAD_OUTPUT_BASE:
+ ERROR("Bad Output Ring Base (not on a 4-byte boundary)\n");
+ break;
+ case JRINT_ERR_WRITE_2_IRBA:
+ ERROR("Invalid write to Input Ring Base Address Register\n");
+ break;
+ case JRINT_ERR_WRITE_2_ORBA:
+ ERROR("Invalid write to Output Ring Base Address Register\n");
+ break;
+ case JRINT_ERR_RES_B4_HALT:
+ ERROR("Job Ring released before Job Ring is halted\n");
+ break;
+ case JRINT_ERR_REM_TOO_MANY:
+ ERROR("Removed too many jobs from job ring\n");
+ break;
+ case JRINT_ERR_ADD_TOO_MANY:
+ ERROR("Added too many jobs on job ring\n");
+ break;
+ default:
+ ERROR("Unknown SEC JR Error :%d\n", jrint_error_code);
+ break;
+ }
+ return jrint_error_code;
+}
+
+int hw_job_ring_set_coalescing_param(sec_job_ring_t *job_ring,
+ uint16_t irq_coalescing_timer,
+ uint8_t irq_coalescing_count)
+{
+ uint32_t reg_val = 0U;
+ struct jobring_regs *regs =
+ (struct jobring_regs *)job_ring->register_base_addr;
+
+ /* Set descriptor count coalescing */
+ reg_val |= (irq_coalescing_count << JR_REG_JRCFG_LO_ICDCT_SHIFT);
+
+ /* Set coalescing timer value */
+ reg_val |= (irq_coalescing_timer << JR_REG_JRCFG_LO_ICTT_SHIFT);
+
+ /* Update parameters in HW */
+ sec_out32(®s->jrcfg1, reg_val);
+
+ VERBOSE("Set coalescing params on jr\n");
+
+ return 0;
+}
+
+int hw_job_ring_enable_coalescing(sec_job_ring_t *job_ring)
+{
+ uint32_t reg_val = 0U;
+ struct jobring_regs *regs =
+ (struct jobring_regs *)job_ring->register_base_addr;
+
+ /* Get the current value of the register */
+ reg_val = sec_in32(®s->jrcfg1);
+
+ /* Enable coalescing */
+ reg_val |= JR_REG_JRCFG_LO_ICEN_EN;
+
+ /* Write in hw */
+ sec_out32(®s->jrcfg1, reg_val);
+
+ VERBOSE("Enabled coalescing on jr\n");
+
+ return 0;
+}
+
+int hw_job_ring_disable_coalescing(sec_job_ring_t *job_ring)
+{
+ uint32_t reg_val = 0U;
+ struct jobring_regs *regs =
+ (struct jobring_regs *)job_ring->register_base_addr;
+
+ /* Get the current value of the register */
+ reg_val = sec_in32(®s->jrcfg1);
+
+ /* Disable coalescing */
+ reg_val &= ~JR_REG_JRCFG_LO_ICEN_EN;
+
+ /* Write in hw */
+ sec_out32(®s->jrcfg1, reg_val);
+
+ VERBOSE("Disabled coalescing on jr");
+
+ return 0;
+
+}
+
+void hw_flush_job_ring(struct sec_job_ring_t *job_ring,
+ uint32_t do_notify,
+ uint32_t error_code, uint32_t *notified_descs)
+{
+ int32_t jobs_no_to_discard = 0;
+ int32_t discarded_descs_no = 0;
+ int32_t number_of_jobs_available = 0;
+
+ VERBOSE("JR pi[%d]i ci[%d]\n", job_ring->pidx, job_ring->cidx);
+ VERBOSE("error code %x\n", error_code);
+ VERBOSE("Notify_desc = %d\n", do_notify);
+
+ number_of_jobs_available = hw_get_no_finished_jobs(job_ring);
+
+ /* Discard all jobs */
+ jobs_no_to_discard = number_of_jobs_available;
+
+ VERBOSE("JR pi[%d]i ci[%d]\n", job_ring->pidx, job_ring->cidx);
+ VERBOSE("Discarding desc = %d\n", jobs_no_to_discard);
+
+ while (jobs_no_to_discard > discarded_descs_no) {
+ discarded_descs_no++;
+ /* Now increment the consumer index for the current job ring,
+ * AFTER saving job in temporary location!
+ * Increment the consumer index for the current job ring
+ */
+
+ job_ring->cidx = SEC_CIRCULAR_COUNTER(job_ring->cidx,
+ SEC_JOB_RING_SIZE);
+
+ hw_remove_entries(job_ring, 1);
+ }
+
+ if (do_notify == true) {
+ if (notified_descs == NULL) {
+ return;
+ }
+ *notified_descs = discarded_descs_no;
+ }
+}
+
+/* return >0 in case of success
+ * -1 in case of error from SEC block
+ * 0 in case job not yet processed by SEC
+ * or Descriptor returned is NULL after dequeue
+ */
+int hw_poll_job_ring(struct sec_job_ring_t *job_ring, int32_t limit)
+{
+ int32_t jobs_no_to_notify = 0;
+ int32_t number_of_jobs_available = 0;
+ int32_t notified_descs_no = 0;
+ uint32_t error_descs_no = 0U;
+ uint32_t sec_error_code = 0U;
+ uint32_t do_driver_shutdown = false;
+ phys_addr_t *fnptr, *arg_addr;
+ user_callback usercall = NULL;
+ uint8_t *current_desc;
+ void *arg;
+ uintptr_t current_desc_addr;
+ phys_addr_t current_desc_loc;
+
+#if defined(SEC_MEM_NON_COHERENT) && defined(IMAGE_BL2)
+ inv_dcache_range((uintptr_t)job_ring->register_base_addr, sizeof(struct jobring_regs));
+ dmbsy();
+#endif
+
+ /* check here if any JR error that cannot be written
+ * in the output status word has occurred
+ */
+ sec_error_code = hw_job_ring_error(job_ring);
+ if (unlikely(sec_error_code) != 0) {
+ ERROR("Error here itself %x\n", sec_error_code);
+ return -1;
+ }
+ /* Compute the number of notifications that need to be raised to UA
+ * If limit < 0 -> notify all done jobs
+ * If limit > total number of done jobs -> notify all done jobs
+ * If limit = 0 -> error
+ * If limit > 0 && limit < total number of done jobs -> notify a number
+ * of done jobs equal with limit
+ */
+
+ /*compute the number of jobs available in the job ring based on the
+ * producer and consumer index values.
+ */
+
+ number_of_jobs_available = hw_get_no_finished_jobs(job_ring);
+ jobs_no_to_notify = (limit < 0 || limit > number_of_jobs_available) ?
+ number_of_jobs_available : limit;
+ VERBOSE("JR - pi %d, ci %d, ", job_ring->pidx, job_ring->cidx);
+ VERBOSE("Jobs submitted %d", number_of_jobs_available);
+ VERBOSE("Jobs to notify %d\n", jobs_no_to_notify);
+
+ while (jobs_no_to_notify > notified_descs_no) {
+
+#if defined(SEC_MEM_NON_COHERENT) && defined(IMAGE_BL2)
+ inv_dcache_range(
+ (uintptr_t)(&job_ring->output_ring[job_ring->cidx]),
+ sizeof(struct sec_outring_entry));
+ dmbsy();
+#endif
+
+ /* Get job status here */
+ sec_error_code =
+ sec_in32(&(job_ring->output_ring[job_ring->cidx].status));
+
+ /* Get completed descriptor
+ */
+ current_desc_loc = (uintptr_t)
+ &job_ring->output_ring[job_ring->cidx].desc;
+ current_desc_addr = sec_read_addr(current_desc_loc);
+
+ current_desc = ptov((phys_addr_t *) current_desc_addr);
+ if (current_desc == 0) {
+ ERROR("No descriptor returned from SEC");
+ assert(current_desc);
+ return 0;
+ }
+ /* now increment the consumer index for the current job ring,
+ * AFTER saving job in temporary location!
+ */
+ job_ring->cidx = SEC_CIRCULAR_COUNTER(job_ring->cidx,
+ SEC_JOB_RING_SIZE);
+
+ if (sec_error_code != 0) {
+ ERROR("desc at cidx %d\n ", job_ring->cidx);
+ ERROR("generated error %x\n", sec_error_code);
+
+ sec_handle_desc_error(job_ring,
+ sec_error_code,
+ &error_descs_no,
+ &do_driver_shutdown);
+ hw_remove_entries(job_ring, 1);
+
+ return -1;
+ }
+ /* Signal that the job has been processed & the slot is free */
+ hw_remove_entries(job_ring, 1);
+ notified_descs_no++;
+
+ arg_addr = (phys_addr_t *) (current_desc +
+ (MAX_DESC_SIZE_WORDS * sizeof(uint32_t)));
+
+ fnptr = (phys_addr_t *) (current_desc +
+ (MAX_DESC_SIZE_WORDS * sizeof(uint32_t)
+ + sizeof(void *)));
+
+ arg = (void *)*(arg_addr);
+ if (*fnptr != 0) {
+ VERBOSE("Callback Function called\n");
+ usercall = (user_callback) *(fnptr);
+ (*usercall) ((uint32_t *) current_desc,
+ sec_error_code, arg, job_ring);
+ }
+ }
+
+ return notified_descs_no;
+}
+
+void sec_handle_desc_error(sec_job_ring_t *job_ring,
+ uint32_t sec_error_code,
+ uint32_t *notified_descs,
+ uint32_t *do_driver_shutdown)
+{
+ /* Analyze the SEC error on this job ring */
+ hw_handle_job_ring_error(job_ring, sec_error_code);
+}
+
+void flush_job_rings(void)
+{
+ struct sec_job_ring_t *job_ring = NULL;
+ int i = 0;
+
+ for (i = 0; i < g_job_rings_no; i++) {
+ job_ring = &g_job_rings[i];
+ /* Producer index is frozen. If consumer index is not equal
+ * with producer index, then we have descs to flush.
+ */
+ while (job_ring->pidx != job_ring->cidx) {
+ hw_flush_job_ring(job_ring, false, 0, /* no error */
+ NULL);
+ }
+ }
+}
+
+int shutdown_job_ring(struct sec_job_ring_t *job_ring)
+{
+ int ret = 0;
+
+ ret = hw_shutdown_job_ring(job_ring);
+ if (ret != 0) {
+ ERROR("Failed to shutdown hardware job ring\n");
+ return ret;
+ }
+
+ if (job_ring->coalescing_en != 0) {
+ hw_job_ring_disable_coalescing(job_ring);
+ }
+
+ if (job_ring->jr_mode != SEC_NOTIFICATION_TYPE_POLL) {
+ ret = jr_disable_irqs(job_ring);
+ if (ret != 0) {
+ ERROR("Failed to disable irqs for job ring");
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+int jr_enable_irqs(struct sec_job_ring_t *job_ring)
+{
+ uint32_t reg_val = 0U;
+ struct jobring_regs *regs =
+ (struct jobring_regs *)job_ring->register_base_addr;
+
+ /* Get the current value of the register */
+ reg_val = sec_in32(®s->jrcfg1);
+
+ /* Enable interrupts by disabling interrupt masking*/
+ reg_val &= ~JR_REG_JRCFG_LO_IMSK_EN;
+
+ /* Update parameters in HW */
+ sec_out32(®s->jrcfg1, reg_val);
+
+ VERBOSE("Enable interrupts on JR\n");
+
+ return 0;
+}
+
+int jr_disable_irqs(struct sec_job_ring_t *job_ring)
+{
+ uint32_t reg_val = 0U;
+ struct jobring_regs *regs =
+ (struct jobring_regs *)job_ring->register_base_addr;
+
+ /* Get the current value of the register */
+ reg_val = sec_in32(®s->jrcfg1);
+
+ /* Disable interrupts by enabling interrupt masking*/
+ reg_val |= JR_REG_JRCFG_LO_IMSK_EN;
+
+ /* Update parameters in HW */
+ sec_out32(®s->jrcfg1, reg_val);
+
+ VERBOSE("Disable interrupts on JR\n");
+
+ return 0;
+}
diff --git a/drivers/nxp/crypto/caam/src/sec_jr_driver.c b/drivers/nxp/crypto/caam/src/sec_jr_driver.c
new file mode 100644
index 0000000..1fe7007
--- /dev/null
+++ b/drivers/nxp/crypto/caam/src/sec_jr_driver.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <arch_helpers.h>
+#include "caam.h"
+#include <common/debug.h>
+#include "jobdesc.h"
+#include "nxp_timer.h"
+#include "sec_hw_specific.h"
+#include "sec_jr_driver.h"
+
+
+/* Job rings used for communication with SEC HW */
+struct sec_job_ring_t g_job_rings[MAX_SEC_JOB_RINGS];
+
+/* The current state of SEC user space driver */
+volatile sec_driver_state_t g_driver_state = SEC_DRIVER_STATE_IDLE;
+
+int g_job_rings_no;
+
+uint8_t ip_ring[SEC_DMA_MEM_INPUT_RING_SIZE] __aligned(CACHE_WRITEBACK_GRANULE);
+uint8_t op_ring[SEC_DMA_MEM_OUTPUT_RING_SIZE] __aligned(CACHE_WRITEBACK_GRANULE);
+
+void *init_job_ring(uint8_t jr_mode,
+ uint16_t irq_coalescing_timer,
+ uint8_t irq_coalescing_count,
+ void *reg_base_addr, uint32_t irq_id)
+{
+ struct sec_job_ring_t *job_ring = &g_job_rings[g_job_rings_no++];
+ int ret = 0;
+
+ job_ring->register_base_addr = reg_base_addr;
+ job_ring->jr_mode = jr_mode;
+ job_ring->irq_fd = irq_id;
+
+ job_ring->input_ring = vtop(ip_ring);
+ memset(job_ring->input_ring, 0, SEC_DMA_MEM_INPUT_RING_SIZE);
+
+ job_ring->output_ring = (struct sec_outring_entry *)vtop(op_ring);
+ memset(job_ring->output_ring, 0, SEC_DMA_MEM_OUTPUT_RING_SIZE);
+
+ dsb();
+
+#if defined(SEC_MEM_NON_COHERENT) && defined(IMAGE_BL2)
+ flush_dcache_range((uintptr_t)(job_ring->input_ring),
+ SEC_DMA_MEM_INPUT_RING_SIZE),
+ flush_dcache_range((uintptr_t)(job_ring->output_ring),
+ SEC_DMA_MEM_OUTPUT_RING_SIZE),
+
+ dmbsy();
+#endif
+ /* Reset job ring in SEC hw and configure job ring registers */
+ ret = hw_reset_job_ring(job_ring);
+ if (ret != 0) {
+ ERROR("Failed to reset hardware job ring\n");
+ return NULL;
+ }
+
+ if (jr_mode == SEC_NOTIFICATION_TYPE_IRQ) {
+ /* Enable IRQ if driver work sin interrupt mode */
+ ERROR("Enabling DONE IRQ generation on job ring\n");
+ ret = jr_enable_irqs(job_ring);
+ if (ret != 0) {
+ ERROR("Failed to enable irqs for job ring\n");
+ return NULL;
+ }
+ }
+ if ((irq_coalescing_timer != 0) || (irq_coalescing_count != 0)) {
+ hw_job_ring_set_coalescing_param(job_ring,
+ irq_coalescing_timer,
+ irq_coalescing_count);
+
+ hw_job_ring_enable_coalescing(job_ring);
+ job_ring->coalescing_en = 1;
+ }
+
+ job_ring->jr_state = SEC_JOB_RING_STATE_STARTED;
+
+ return job_ring;
+}
+
+int sec_release(void)
+{
+ int i;
+
+ /* Validate driver state */
+ if (g_driver_state == SEC_DRIVER_STATE_RELEASE) {
+ ERROR("Driver release is already in progress");
+ return SEC_DRIVER_RELEASE_IN_PROGRESS;
+ }
+ /* Update driver state */
+ g_driver_state = SEC_DRIVER_STATE_RELEASE;
+
+ /* If any descriptors in flight , poll and wait
+ * until all descriptors are received and silently discarded.
+ */
+
+ flush_job_rings();
+
+ for (i = 0; i < g_job_rings_no; i++) {
+ shutdown_job_ring(&g_job_rings[i]);
+ }
+ g_job_rings_no = 0;
+ g_driver_state = SEC_DRIVER_STATE_IDLE;
+
+ return SEC_SUCCESS;
+}
+
+int sec_jr_lib_init(void)
+{
+ /* Validate driver state */
+ if (g_driver_state != SEC_DRIVER_STATE_IDLE) {
+ ERROR("Driver already initialized\n");
+ return 0;
+ }
+
+ memset(g_job_rings, 0, sizeof(g_job_rings));
+ g_job_rings_no = 0;
+
+ /* Update driver state */
+ g_driver_state = SEC_DRIVER_STATE_STARTED;
+ return 0;
+}
+
+int dequeue_jr(void *job_ring_handle, int32_t limit)
+{
+ int ret = 0;
+ int notified_descs_no = 0;
+ struct sec_job_ring_t *job_ring = (sec_job_ring_t *) job_ring_handle;
+ uint64_t start_time;
+
+ /* Validate driver state */
+ if (g_driver_state != SEC_DRIVER_STATE_STARTED) {
+ ERROR("Driver release in progress or driver not initialized\n");
+ return -1;
+ }
+
+ /* Validate input arguments */
+ if (job_ring == NULL) {
+ ERROR("job_ring_handle is NULL\n");
+ return -1;
+ }
+ if (((limit == 0) || (limit > SEC_JOB_RING_SIZE))) {
+ ERROR("Invalid limit parameter configuration\n");
+ return -1;
+ }
+
+ VERBOSE("JR Polling limit[%d]\n", limit);
+
+ /* Poll job ring
+ * If limit < 0 -> poll JR until no more notifications are available.
+ * If limit > 0 -> poll JR until limit is reached.
+ */
+
+ start_time = get_timer_val(0);
+
+ while (notified_descs_no == 0) {
+ /* Run hw poll job ring */
+ notified_descs_no = hw_poll_job_ring(job_ring, limit);
+ if (notified_descs_no < 0) {
+ ERROR("Error polling SEC engine job ring ");
+ return notified_descs_no;
+ }
+ VERBOSE("Jobs notified[%d]. ", notified_descs_no);
+
+ if (get_timer_val(start_time) >= CAAM_TIMEOUT) {
+ break;
+ }
+ }
+
+ if (job_ring->jr_mode == SEC_NOTIFICATION_TYPE_IRQ) {
+
+ /* Always enable IRQ generation when in pure IRQ mode */
+ ret = jr_enable_irqs(job_ring);
+ if (ret != 0) {
+ ERROR("Failed to enable irqs for job ring");
+ return ret;
+ }
+ }
+ return notified_descs_no;
+}
+
+int enq_jr_desc(void *job_ring_handle, struct job_descriptor *jobdescr)
+{
+ struct sec_job_ring_t *job_ring;
+
+ job_ring = (struct sec_job_ring_t *)job_ring_handle;
+
+ /* Validate driver state */
+ if (g_driver_state != SEC_DRIVER_STATE_STARTED) {
+ ERROR("Driver release in progress or driver not initialized\n");
+ return -1;
+ }
+
+ /* Check job ring state */
+ if (job_ring->jr_state != SEC_JOB_RING_STATE_STARTED) {
+ ERROR("Job ring is currently resetting\n");
+ return -1;
+ }
+
+ if (SEC_JOB_RING_IS_FULL(job_ring->pidx, job_ring->cidx,
+ SEC_JOB_RING_SIZE, SEC_JOB_RING_SIZE)) {
+ ERROR("Job ring is full\n");
+ return -1;
+ }
+
+ /* Set ptr in input ring to current descriptor */
+ sec_write_addr(&job_ring->input_ring[job_ring->pidx],
+ (phys_addr_t) vtop(jobdescr->desc));
+
+ dsb();
+
+#if defined(SEC_MEM_NON_COHERENT) && defined(IMAGE_BL2)
+ flush_dcache_range((uintptr_t)(&job_ring->input_ring[job_ring->pidx]),
+ sizeof(phys_addr_t));
+
+ inv_dcache_range((uintptr_t)(&job_ring->output_ring[job_ring->cidx]),
+ sizeof(struct sec_outring_entry));
+ dmbsy();
+#endif
+ /* Notify HW that a new job is enqueued */
+ hw_enqueue_desc_on_job_ring(
+ (struct jobring_regs *)job_ring->register_base_addr, 1);
+
+ /* increment the producer index for the current job ring */
+ job_ring->pidx = SEC_CIRCULAR_COUNTER(job_ring->pidx,
+ SEC_JOB_RING_SIZE);
+
+ return 0;
+}
diff --git a/drivers/nxp/csu/csu.c b/drivers/nxp/csu/csu.c
new file mode 100644
index 0000000..9f90fe0
--- /dev/null
+++ b/drivers/nxp/csu/csu.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <endian.h>
+
+#include <common/debug.h>
+#include <csu.h>
+#include <lib/mmio.h>
+
+void enable_layerscape_ns_access(struct csu_ns_dev_st *csu_ns_dev,
+ uint32_t num, uintptr_t nxp_csu_addr)
+{
+ uint32_t *base = (uint32_t *)nxp_csu_addr;
+ uint32_t *reg;
+ uint32_t val;
+ int i;
+
+ for (i = 0; i < num; i++) {
+ reg = base + csu_ns_dev[i].ind / 2U;
+ val = be32toh(mmio_read_32((uintptr_t)reg));
+ if (csu_ns_dev[i].ind % 2U == 0U) {
+ val &= 0x0000ffffU;
+ val |= csu_ns_dev[i].val << 16U;
+ } else {
+ val &= 0xffff0000U;
+ val |= csu_ns_dev[i].val;
+ }
+ mmio_write_32((uintptr_t)reg, htobe32(val));
+ }
+}
diff --git a/drivers/nxp/csu/csu.mk b/drivers/nxp/csu/csu.mk
new file mode 100644
index 0000000..bc16035
--- /dev/null
+++ b/drivers/nxp/csu/csu.mk
@@ -0,0 +1,26 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-----------------------------------------------------------------------------
+ifeq (${CSU_ADDED},)
+
+CSU_ADDED := 1
+
+PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLUDE_PATH)/csu
+
+CSU_SOURCES += $(PLAT_DRIVERS_PATH)/csu/csu.c
+
+ifeq (${BL_COMM_CSU_NEEDED},yes)
+BL_COMMON_SOURCES += ${CSU_SOURCES}
+else
+ifeq (${BL2_CSU_NEEDED},yes)
+BL2_SOURCES += ${CSU_SOURCES}
+endif
+ifeq (${BL31_CSU_NEEDED},yes)
+BL31_SOURCES += ${CSU_SOURCES}
+endif
+endif
+
+endif
diff --git a/drivers/nxp/dcfg/dcfg.c b/drivers/nxp/dcfg/dcfg.c
new file mode 100644
index 0000000..a988c5d
--- /dev/null
+++ b/drivers/nxp/dcfg/dcfg.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright 2020-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <common/debug.h>
+#include "dcfg.h"
+#include <lib/mmio.h>
+#ifdef NXP_SFP_ENABLED
+#include <sfp.h>
+#endif
+
+static soc_info_t soc_info = {0};
+static devdisr5_info_t devdisr5_info = {0};
+static dcfg_init_info_t *dcfg_init_info;
+
+/* Read the PORSR1 register */
+uint32_t read_reg_porsr1(void)
+{
+ unsigned int *porsr1_addr = NULL;
+
+ if (dcfg_init_info->porsr1 != 0U) {
+ return dcfg_init_info->porsr1;
+ }
+
+ porsr1_addr = (void *)
+ (dcfg_init_info->g_nxp_dcfg_addr + DCFG_PORSR1_OFFSET);
+ dcfg_init_info->porsr1 = gur_in32(porsr1_addr);
+
+ return dcfg_init_info->porsr1;
+}
+
+
+const soc_info_t *get_soc_info(void)
+{
+ uint32_t reg;
+
+ if (soc_info.is_populated == true) {
+ return (const soc_info_t *) &soc_info;
+ }
+
+ reg = gur_in32(dcfg_init_info->g_nxp_dcfg_addr + DCFG_SVR_OFFSET);
+
+ soc_info.svr_reg.val = reg;
+
+ /* zero means SEC enabled. */
+ soc_info.sec_enabled =
+ (((reg & SVR_SEC_MASK) >> SVR_SEC_SHIFT) == 0) ? true : false;
+
+ soc_info.is_populated = true;
+ return (const soc_info_t *) &soc_info;
+}
+
+void dcfg_init(dcfg_init_info_t *dcfg_init_data)
+{
+ dcfg_init_info = dcfg_init_data;
+ read_reg_porsr1();
+ get_soc_info();
+}
+
+bool is_sec_enabled(void)
+{
+ return soc_info.sec_enabled;
+}
+
+const devdisr5_info_t *get_devdisr5_info(void)
+{
+ uint32_t reg;
+
+ if (devdisr5_info.is_populated == true)
+ return (const devdisr5_info_t *) &devdisr5_info;
+
+ reg = gur_in32(dcfg_init_info->g_nxp_dcfg_addr + DCFG_DEVDISR5_OFFSET);
+
+#if defined(CONFIG_CHASSIS_3_2)
+ devdisr5_info.ddrc1_present = (reg & DISR5_DDRC1_MASK) ? 0 : 1;
+ devdisr5_info.ddrc2_present = (reg & DISR5_DDRC2_MASK) ? 0 : 1;
+ devdisr5_info.ocram_present = (reg & DISR5_OCRAM_MASK) ? 0 : 1;
+#elif defined(CONFIG_CHASSIS_2)
+ devdisr5_info.ddrc1_present = (reg & DISR5_DDRC1_MASK) ? 0 : 1;
+ devdisr5_info.ocram_present = (reg & DISR5_OCRAM_MASK) ? 0 : 1;
+#endif
+ devdisr5_info.is_populated = true;
+
+ return (const devdisr5_info_t *) &devdisr5_info;
+}
+
+int get_clocks(struct sysinfo *sys)
+{
+ unsigned int *rcwsr0 = NULL;
+ const unsigned long sysclk = dcfg_init_info->nxp_sysclk_freq;
+ const unsigned long ddrclk = dcfg_init_info->nxp_ddrclk_freq;
+
+ rcwsr0 = (void *)(dcfg_init_info->g_nxp_dcfg_addr + RCWSR0_OFFSET);
+ sys->freq_platform = sysclk;
+ sys->freq_ddr_pll0 = ddrclk;
+ sys->freq_ddr_pll1 = ddrclk;
+
+ sys->freq_platform *= (gur_in32(rcwsr0) >>
+ RCWSR0_SYS_PLL_RAT_SHIFT) &
+ RCWSR0_SYS_PLL_RAT_MASK;
+
+ sys->freq_platform /= dcfg_init_info->nxp_plat_clk_divider;
+
+ sys->freq_ddr_pll0 *= (gur_in32(rcwsr0) >>
+ RCWSR0_MEM_PLL_RAT_SHIFT) &
+ RCWSR0_MEM_PLL_RAT_MASK;
+ sys->freq_ddr_pll1 *= (gur_in32(rcwsr0) >>
+ RCWSR0_MEM2_PLL_RAT_SHIFT) &
+ RCWSR0_MEM2_PLL_RAT_MASK;
+ if (sys->freq_platform == 0) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+#ifdef NXP_SFP_ENABLED
+/*******************************************************************************
+ * Returns true if secur eboot is enabled on board
+ * mode = 0 (development mode - sb_en = 1)
+ * mode = 1 (production mode - ITS = 1)
+ ******************************************************************************/
+bool check_boot_mode_secure(uint32_t *mode)
+{
+ uint32_t val = 0U;
+ uint32_t *rcwsr = NULL;
+ *mode = 0U;
+
+ if (sfp_check_its() == 1) {
+ /* ITS =1 , Production mode */
+ *mode = 1U;
+ return true;
+ }
+
+ rcwsr = (void *)(dcfg_init_info->g_nxp_dcfg_addr + RCWSR_SB_EN_OFFSET);
+
+ val = (gur_in32(rcwsr) >> RCWSR_SBEN_SHIFT) &
+ RCWSR_SBEN_MASK;
+
+ if (val == RCWSR_SBEN_MASK) {
+ *mode = 0U;
+ return true;
+ }
+
+ return false;
+}
+#endif
+
+void error_handler(int error_code)
+{
+ /* Dump error code in SCRATCH4 register */
+ INFO("Error in Fuse Provisioning: %x\n", error_code);
+ gur_out32((void *)
+ (dcfg_init_info->g_nxp_dcfg_addr + DCFG_SCRATCH4_OFFSET),
+ error_code);
+}
diff --git a/drivers/nxp/dcfg/dcfg.mk b/drivers/nxp/dcfg/dcfg.mk
new file mode 100644
index 0000000..206595f
--- /dev/null
+++ b/drivers/nxp/dcfg/dcfg.mk
@@ -0,0 +1,26 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${ADD_DCFG},)
+
+ADD_DCFG := 1
+
+PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLUDE_PATH)/dcfg
+
+DCFG_SOURCES += $(PLAT_DRIVERS_PATH)/dcfg/dcfg.c
+
+ifeq (${BL_COMM_DCFG_NEEDED},yes)
+BL_COMMON_SOURCES += ${DCFG_SOURCES}
+else
+ifeq (${BL2_DCFG_NEEDED},yes)
+BL2_SOURCES += ${DCFG_SOURCES}
+endif
+ifeq (${BL31_DCFG_NEEDED},yes)
+BL31_SOURCES += ${DCFG_SOURCES}
+endif
+endif
+
+endif
diff --git a/drivers/nxp/ddr/fsl-mmdc/ddr.mk b/drivers/nxp/ddr/fsl-mmdc/ddr.mk
new file mode 100644
index 0000000..afccb62
--- /dev/null
+++ b/drivers/nxp/ddr/fsl-mmdc/ddr.mk
@@ -0,0 +1,19 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-----------------------------------------------------------------------------
+
+# MMDC ddr cntlr driver files
+
+DDR_DRIVERS_PATH := drivers/nxp/ddr
+
+DDR_CNTLR_SOURCES := ${PLAT_DRIVERS_PATH}/ddr/fsl-mmdc/fsl_mmdc.c \
+ ${PLAT_DRIVERS_PATH}/ddr/nxp-ddr/utility.c \
+ ${PLAT_DRIVERS_PATH}/ddr/nxp-ddr/ddr.c \
+ ${PLAT_DRIVERS_PATH}/ddr/nxp-ddr/ddrc.c
+
+PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLUDE_PATH)/ddr \
+ -I$(PLAT_DRIVERS_INCLUDE_PATH)/ddr/fsl-mmdc
+#------------------------------------------------
diff --git a/drivers/nxp/ddr/fsl-mmdc/fsl_mmdc.c b/drivers/nxp/ddr/fsl-mmdc/fsl_mmdc.c
new file mode 100644
index 0000000..7e6504e
--- /dev/null
+++ b/drivers/nxp/ddr/fsl-mmdc/fsl_mmdc.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/*
+ * Generic driver for Freescale MMDC(Multi Mode DDR Controller).
+ */
+
+#include <errno.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include "ddr_io.h"
+#include <drivers/delay_timer.h>
+#include <fsl_mmdc.h>
+
+static void set_wait_for_bits_clear(void *ptr, unsigned int value,
+ unsigned int bits)
+{
+ int timeout = 1000;
+
+ ddr_out32(ptr, value);
+
+ while ((ddr_in32(ptr) & bits) != 0) {
+ udelay(100);
+ timeout--;
+ }
+ if (timeout <= 0) {
+ INFO("Error: %llx", (unsigned long long)ptr);
+ INFO(" wait for clear timeout.\n");
+ }
+}
+
+void mmdc_init(const struct fsl_mmdc_info *priv, uintptr_t nxp_ddr_addr)
+{
+ struct mmdc_regs *mmdc = (struct mmdc_regs *)nxp_ddr_addr;
+ unsigned int tmp;
+
+ /* 1. set configuration request */
+ ddr_out32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
+
+ /* 2. configure the desired timing parameters */
+ ddr_out32(&mmdc->mdotc, priv->mdotc);
+ ddr_out32(&mmdc->mdcfg0, priv->mdcfg0);
+ ddr_out32(&mmdc->mdcfg1, priv->mdcfg1);
+ ddr_out32(&mmdc->mdcfg2, priv->mdcfg2);
+
+ /* 3. configure DDR type and other miscellaneous parameters */
+ ddr_out32(&mmdc->mdmisc, priv->mdmisc);
+ ddr_out32(&mmdc->mpmur0, MMDC_MPMUR0_FRC_MSR);
+ ddr_out32(&mmdc->mdrwd, priv->mdrwd);
+ ddr_out32(&mmdc->mpodtctrl, priv->mpodtctrl);
+
+ /* 4. configure the required delay while leaving reset */
+ ddr_out32(&mmdc->mdor, priv->mdor);
+
+ /* 5. configure DDR physical parameters */
+ /* set row/column address width, burst length, data bus width */
+ tmp = priv->mdctl & ~(MDCTL_SDE0 | MDCTL_SDE1);
+ ddr_out32(&mmdc->mdctl, tmp);
+ /* configure address space partition */
+ ddr_out32(&mmdc->mdasp, priv->mdasp);
+
+ /* 6. perform a ZQ calibration - not needed here, doing in #8b */
+
+ /* 7. enable MMDC with the desired chip select */
+#if (DDRC_NUM_CS == 1)
+ ddr_out32(&mmdc->mdctl, tmp | MDCTL_SDE0);
+#elif (DDRC_NUM_CS == 2)
+ ddr_out32(&mmdc->mdctl, tmp | MDCTL_SDE0 | MDCTL_SDE1);
+#else
+#error "Unsupported DDRC_NUM_CS"
+#endif
+
+ /* 8a. dram init sequence: update MRs for ZQ, ODT, PRE, etc */
+ ddr_out32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(8) |
+ MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_2);
+
+ ddr_out32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(0) |
+ MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3);
+
+ ddr_out32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) |
+ MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_1);
+
+ ddr_out32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(0x19) |
+ CMD_ADDR_LSB_MR_ADDR(0x30) |
+ MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0);
+
+ /* 8b. ZQ calibration */
+ ddr_out32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(0x4) |
+ MDSCR_ENABLE_CON_REQ |
+ CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0);
+
+ set_wait_for_bits_clear(&mmdc->mpzqhwctrl, priv->mpzqhwctrl,
+ MPZQHWCTRL_ZQ_HW_FORCE);
+
+ /* 9a. calibrations now, wr lvl */
+ ddr_out32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(0x84) | MDSCR_WL_EN |
+ MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
+
+ set_wait_for_bits_clear(&mmdc->mpwlgcr, MPWLGCR_HW_WL_EN,
+ MPWLGCR_HW_WL_EN);
+
+ mdelay(1);
+
+ ddr_out32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) |
+ MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1);
+
+ ddr_out32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ);
+
+ mdelay(1);
+
+ /* 9b. read DQS gating calibration */
+ ddr_out32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0);
+
+ ddr_out32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
+
+ ddr_out32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN);
+
+ /* set absolute read delay offset */
+ if (priv->mprddlctl != 0) {
+ ddr_out32(&mmdc->mprddlctl, priv->mprddlctl);
+ } else {
+ ddr_out32(&mmdc->mprddlctl, MMDC_MPRDDLCTL_DEFAULT_DELAY);
+ }
+
+ set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN,
+ AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+ ddr_out32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3);
+
+ /* 9c. read calibration */
+ ddr_out32(&mmdc->mdscr, CMD_ADDR_MSB_MR_OP(4) | MDSCR_ENABLE_CON_REQ |
+ CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0);
+ ddr_out32(&mmdc->mdscr, CMD_ADDR_LSB_MR_ADDR(4) | MDSCR_ENABLE_CON_REQ |
+ CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3);
+ ddr_out32(&mmdc->mppdcmpr2, MPPDCMPR2_MPR_COMPARE_EN);
+ set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+ MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN,
+ MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN);
+
+ ddr_out32(&mmdc->mdscr, MDSCR_ENABLE_CON_REQ | CMD_LOAD_MODE_REG |
+ CMD_BANK_ADDR_3);
+
+ /* 10. configure power-down, self-refresh entry, exit parameters */
+ ddr_out32(&mmdc->mdpdc, priv->mdpdc);
+ ddr_out32(&mmdc->mapsr, MMDC_MAPSR_PWR_SAV_CTRL_STAT);
+
+ /* 11. ZQ config again? do nothing here */
+
+ /* 12. refresh scheme */
+ set_wait_for_bits_clear(&mmdc->mdref, priv->mdref,
+ MDREF_START_REFRESH);
+
+ /* 13. disable CON_REQ */
+ ddr_out32(&mmdc->mdscr, MDSCR_DISABLE_CFG_REQ);
+}
diff --git a/drivers/nxp/ddr/nxp-ddr/README.odt b/drivers/nxp/ddr/nxp-ddr/README.odt
new file mode 100644
index 0000000..8796302
--- /dev/null
+++ b/drivers/nxp/ddr/nxp-ddr/README.odt
@@ -0,0 +1,31 @@
+Table for dynamic ODT for DDR4 with PHY generation 2
+====================================================
+Two-slot system
+Only symmetric configurations are supported for interleaving. Non-symmetric
+configurations are possible but not covered here. First slot empty is possbile
+but prohibited for simplicity.
++-----------------------+-------------+---------------+-----------------------------+-----------------------------+
+| Configuration | |DRAM controller| Slot 1 | Slot 2 |
++-----------+-----------+-------------+-------+-------+--------------+--------------+--------------+--------------+
+| | | | | | Rank 1 | Rank 2 | Rank 1 | Rank 2 |
+| Slot 1 | Slot 2 | Write/Read | Write | Read |-------+------+-------+------+-------+------+-------+------+
+| | | | | | Write | Read | Write | Read | Write | Read | Write | Read |
++-----------+-----------+------+------+-------+-------+-------+------+-------+------+-------+------+-------+------+
+| | | |Rank 1| off | 60 | 240 | off | 60 | 240 | 60 | 60 | 60 | 60 |
+| | |Slot 1|------+-------+-------+-------+------+-------+------+-------+------+-------+------+
+| | | |Rank 2| off | 60 | 60 | 240 | 240 | off | 60 | 60 | 60 | 60 |
+| Dual Rank | Dual Rank |------+------+-------+-------+-------+------+-------+------+-------+------+-------+------+
+| | | |Rank 1| off | 60 | 60 | 60 | 60 | 60 | 240 | off | 60 | 240 |
+| | |Slot 2|------+-------+-------+-------+------+-------+------+-------+------+-------+------+
+| | | |Rank 2| off | 60 | 60 | 60 | 60 | 60 | 60 | 240 | 240 | off |
++-----------+-----------+------+------+-------+-------+-------+------+-------+------+-------+------+-------+------+
+| | | Slot 1 | off | 60 | 80 | off | | | | | | |
+|Single Rank|Single Rank|-------------+-------+-------+-------+------+-------+------+-------+------+-------+------+
+| | | Slot 2 | off | 60 | | | | | 80 | off |
++-----------+-----------+------+------+-------+-------+-------+------+-------+------+-------+------+
+| | | |Rank 1| off | 80 | 80 | off | off | off |
+| Dual Rank | |Slot 1|------+-------+-------+-------+------+-------+------+
+| | | |Rank 2| off | 80 | 80 | off | off | off |
++-----------+-----------+-------------+-------+-------+-------+------+-------+------+
+|Single Rank| | Slot 1 | off | 80 | 80 | off |
++-----------+-----------+-------------+-------+-------+-------+------+
diff --git a/drivers/nxp/ddr/nxp-ddr/ddr.c b/drivers/nxp/ddr/nxp-ddr/ddr.c
new file mode 100644
index 0000000..216e05c
--- /dev/null
+++ b/drivers/nxp/ddr/nxp-ddr/ddr.c
@@ -0,0 +1,930 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <ddr.h>
+#ifndef CONFIG_DDR_NODIMM
+#include <i2c.h>
+#endif
+#include <nxp_timer.h>
+
+struct dynamic_odt {
+ unsigned int odt_rd_cfg;
+ unsigned int odt_wr_cfg;
+ unsigned int odt_rtt_norm;
+ unsigned int odt_rtt_wr;
+};
+
+#ifndef CONFIG_STATIC_DDR
+#if defined(PHY_GEN2_FW_IMAGE_BUFFER) && !defined(NXP_DDR_PHY_GEN2)
+#error Missing NXP_DDR_PHY_GEN2
+#endif
+#ifdef NXP_DDR_PHY_GEN2
+static const struct dynamic_odt single_D[4] = {
+ { /* cs0 */
+ DDR_ODT_NEVER,
+ DDR_ODT_ALL,
+ DDR4_RTT_80_OHM,
+ DDR4_RTT_WR_OFF
+ },
+ { /* cs1 */
+ DDR_ODT_NEVER,
+ DDR_ODT_NEVER,
+ DDR4_RTT_OFF,
+ DDR4_RTT_WR_OFF
+ },
+ {},
+ {}
+};
+
+static const struct dynamic_odt single_S[4] = {
+ { /* cs0 */
+ DDR_ODT_NEVER,
+ DDR_ODT_ALL,
+ DDR4_RTT_80_OHM,
+ DDR4_RTT_WR_OFF
+ },
+ {},
+ {},
+ {},
+};
+
+static const struct dynamic_odt dual_DD[4] = {
+ { /* cs0 */
+ DDR_ODT_OTHER_DIMM,
+ DDR_ODT_ALL,
+ DDR4_RTT_60_OHM,
+ DDR4_RTT_WR_240_OHM
+ },
+ { /* cs1 */
+ DDR_ODT_OTHER_DIMM,
+ DDR_ODT_ALL,
+ DDR4_RTT_60_OHM,
+ DDR4_RTT_WR_240_OHM
+ },
+ { /* cs2 */
+ DDR_ODT_OTHER_DIMM,
+ DDR_ODT_ALL,
+ DDR4_RTT_60_OHM,
+ DDR4_RTT_WR_240_OHM
+ },
+ { /* cs3 */
+ DDR_ODT_OTHER_DIMM,
+ DDR_ODT_ALL,
+ DDR4_RTT_60_OHM,
+ DDR4_RTT_WR_240_OHM
+ }
+};
+
+static const struct dynamic_odt dual_SS[4] = {
+ { /* cs0 */
+ DDR_ODT_NEVER,
+ DDR_ODT_ALL,
+ DDR4_RTT_80_OHM,
+ DDR4_RTT_WR_OFF
+ },
+ {},
+ { /* cs2 */
+ DDR_ODT_NEVER,
+ DDR_ODT_ALL,
+ DDR4_RTT_80_OHM,
+ DDR4_RTT_WR_OFF
+ },
+ {}
+};
+
+static const struct dynamic_odt dual_D0[4] = {
+ { /* cs0 */
+ DDR_ODT_NEVER,
+ DDR_ODT_SAME_DIMM,
+ DDR4_RTT_80_OHM,
+ DDR4_RTT_WR_OFF
+ },
+ { /* cs1 */
+ DDR_ODT_NEVER,
+ DDR_ODT_NEVER,
+ DDR4_RTT_80_OHM,
+ DDR4_RTT_WR_OFF
+ },
+ {},
+ {}
+};
+
+static const struct dynamic_odt dual_S0[4] = {
+ { /* cs0 */
+ DDR_ODT_NEVER,
+ DDR_ODT_CS,
+ DDR4_RTT_80_OHM,
+ DDR4_RTT_WR_OFF
+ },
+ {},
+ {},
+ {}
+};
+#else
+static const struct dynamic_odt single_D[4] = {
+ { /* cs0 */
+ DDR_ODT_NEVER,
+ DDR_ODT_ALL,
+ DDR4_RTT_40_OHM,
+ DDR4_RTT_WR_OFF
+ },
+ { /* cs1 */
+ DDR_ODT_NEVER,
+ DDR_ODT_NEVER,
+ DDR4_RTT_OFF,
+ DDR4_RTT_WR_OFF
+ },
+ {},
+ {}
+};
+
+static const struct dynamic_odt single_S[4] = {
+ { /* cs0 */
+ DDR_ODT_NEVER,
+ DDR_ODT_ALL,
+ DDR4_RTT_40_OHM,
+ DDR4_RTT_WR_OFF
+ },
+ {},
+ {},
+ {},
+};
+
+static const struct dynamic_odt dual_DD[4] = {
+ { /* cs0 */
+ DDR_ODT_NEVER,
+ DDR_ODT_SAME_DIMM,
+ DDR4_RTT_120_OHM,
+ DDR4_RTT_WR_OFF
+ },
+ { /* cs1 */
+ DDR_ODT_OTHER_DIMM,
+ DDR_ODT_OTHER_DIMM,
+ DDR4_RTT_34_OHM,
+ DDR4_RTT_WR_OFF
+ },
+ { /* cs2 */
+ DDR_ODT_NEVER,
+ DDR_ODT_SAME_DIMM,
+ DDR4_RTT_120_OHM,
+ DDR4_RTT_WR_OFF
+ },
+ { /* cs3 */
+ DDR_ODT_OTHER_DIMM,
+ DDR_ODT_OTHER_DIMM,
+ DDR4_RTT_34_OHM,
+ DDR4_RTT_WR_OFF
+ }
+};
+
+static const struct dynamic_odt dual_SS[4] = {
+ { /* cs0 */
+ DDR_ODT_OTHER_DIMM,
+ DDR_ODT_ALL,
+ DDR4_RTT_34_OHM,
+ DDR4_RTT_WR_120_OHM
+ },
+ {},
+ { /* cs2 */
+ DDR_ODT_OTHER_DIMM,
+ DDR_ODT_ALL,
+ DDR4_RTT_34_OHM,
+ DDR4_RTT_WR_120_OHM
+ },
+ {}
+};
+
+static const struct dynamic_odt dual_D0[4] = {
+ { /* cs0 */
+ DDR_ODT_NEVER,
+ DDR_ODT_SAME_DIMM,
+ DDR4_RTT_40_OHM,
+ DDR4_RTT_WR_OFF
+ },
+ { /* cs1 */
+ DDR_ODT_NEVER,
+ DDR_ODT_NEVER,
+ DDR4_RTT_OFF,
+ DDR4_RTT_WR_OFF
+ },
+ {},
+ {}
+};
+
+static const struct dynamic_odt dual_S0[4] = {
+ { /* cs0 */
+ DDR_ODT_NEVER,
+ DDR_ODT_CS,
+ DDR4_RTT_40_OHM,
+ DDR4_RTT_WR_OFF
+ },
+ {},
+ {},
+ {}
+};
+#endif /* NXP_DDR_PHY_GEN2 */
+
+/*
+ * Automatically select bank interleaving mode based on DIMMs
+ * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
+ * This function only deal with one or two slots per controller.
+ */
+static inline unsigned int auto_bank_intlv(const int cs_in_use,
+ const struct dimm_params *pdimm)
+{
+ switch (cs_in_use) {
+ case 0xf:
+ return DDR_BA_INTLV_CS0123;
+ case 0x3:
+ return DDR_BA_INTLV_CS01;
+ case 0x1:
+ return DDR_BA_NONE;
+ case 0x5:
+ return DDR_BA_NONE;
+ default:
+ break;
+ }
+
+ return 0U;
+}
+
+static int cal_odt(const unsigned int clk,
+ struct memctl_opt *popts,
+ struct ddr_conf *conf,
+ struct dimm_params *pdimm,
+ const int dimm_slot_per_ctrl)
+
+{
+ unsigned int i;
+ const struct dynamic_odt *pdodt = NULL;
+
+ const static struct dynamic_odt *table[2][5] = {
+ {single_S, single_D, NULL, NULL},
+ {dual_SS, dual_DD, NULL, NULL},
+ };
+
+ if (dimm_slot_per_ctrl != 1 && dimm_slot_per_ctrl != 2) {
+ ERROR("Unsupported number of DIMMs\n");
+ return -EINVAL;
+ }
+
+ pdodt = table[dimm_slot_per_ctrl - 1][pdimm->n_ranks - 1];
+ if (pdodt == dual_SS) {
+ pdodt = (conf->cs_in_use == 0x5) ? dual_SS :
+ ((conf->cs_in_use == 0x1) ? dual_S0 : NULL);
+ } else if (pdodt == dual_DD) {
+ pdodt = (conf->cs_in_use == 0xf) ? dual_DD :
+ ((conf->cs_in_use == 0x3) ? dual_D0 : NULL);
+ }
+ if (pdodt == dual_DD && pdimm->package_3ds) {
+ ERROR("Too many 3DS DIMMs.\n");
+ return -EINVAL;
+ }
+
+ if (pdodt == NULL) {
+ ERROR("Error determing ODT.\n");
+ return -EINVAL;
+ }
+
+ /* Pick chip-select local options. */
+ for (i = 0U; i < DDRC_NUM_CS; i++) {
+ debug("cs %d\n", i);
+ popts->cs_odt[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
+ debug(" odt_rd_cfg 0x%x\n",
+ popts->cs_odt[i].odt_rd_cfg);
+ popts->cs_odt[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
+ debug(" odt_wr_cfg 0x%x\n",
+ popts->cs_odt[i].odt_wr_cfg);
+ popts->cs_odt[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
+ debug(" odt_rtt_norm 0x%x\n",
+ popts->cs_odt[i].odt_rtt_norm);
+ popts->cs_odt[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
+ debug(" odt_rtt_wr 0x%x\n",
+ popts->cs_odt[i].odt_rtt_wr);
+ popts->cs_odt[i].auto_precharge = 0;
+ debug(" auto_precharge %d\n",
+ popts->cs_odt[i].auto_precharge);
+ }
+
+ return 0;
+}
+
+static int cal_opts(const unsigned int clk,
+ struct memctl_opt *popts,
+ struct ddr_conf *conf,
+ struct dimm_params *pdimm,
+ const int dimm_slot_per_ctrl,
+ const unsigned int ip_rev)
+{
+ popts->rdimm = pdimm->rdimm;
+ popts->mirrored_dimm = pdimm->mirrored_dimm;
+#ifdef CONFIG_DDR_ECC_EN
+ popts->ecc_mode = pdimm->edc_config == 0x02 ? 1 : 0;
+#endif
+ popts->ctlr_init_ecc = popts->ecc_mode;
+ debug("ctlr_init_ecc %d\n", popts->ctlr_init_ecc);
+ popts->self_refresh_in_sleep = 1;
+ popts->dynamic_power = 0;
+
+ /*
+ * check sdram width, allow platform override
+ * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
+ */
+ if (pdimm->primary_sdram_width == 64) {
+ popts->data_bus_dimm = DDR_DBUS_64;
+ popts->otf_burst_chop_en = 1;
+ } else if (pdimm->primary_sdram_width == 32) {
+ popts->data_bus_dimm = DDR_DBUS_32;
+ popts->otf_burst_chop_en = 0;
+ } else if (pdimm->primary_sdram_width == 16) {
+ popts->data_bus_dimm = DDR_DBUS_16;
+ popts->otf_burst_chop_en = 0;
+ } else {
+ ERROR("primary sdram width invalid!\n");
+ return -EINVAL;
+ }
+ popts->data_bus_used = popts->data_bus_dimm;
+ popts->x4_en = (pdimm->device_width == 4) ? 1 : 0;
+ debug("x4_en %d\n", popts->x4_en);
+
+ /* for RDIMM and DDR4 UDIMM/discrete memory, address parity enable */
+ if (popts->rdimm != 0) {
+ popts->ap_en = 1; /* 0 = disable, 1 = enable */
+ } else {
+ popts->ap_en = 0; /* disabled for DDR4 UDIMM/discrete default */
+ }
+
+ if (ip_rev == 0x50500) {
+ popts->ap_en = 0;
+ }
+
+ debug("ap_en %d\n", popts->ap_en);
+
+ /* BSTTOPRE precharge interval uses 1/4 of refint value. */
+ popts->bstopre = picos_to_mclk(clk, pdimm->refresh_rate_ps) >> 2;
+ popts->tfaw_ps = pdimm->tfaw_ps;
+
+ return 0;
+}
+
+static void cal_intlv(const int num_ctlrs,
+ struct memctl_opt *popts,
+ struct ddr_conf *conf,
+ struct dimm_params *pdimm)
+{
+#ifdef NXP_DDR_INTLV_256B
+ if (num_ctlrs == 2) {
+ popts->ctlr_intlv = 1;
+ popts->ctlr_intlv_mode = DDR_256B_INTLV;
+ }
+#endif
+ debug("ctlr_intlv %d\n", popts->ctlr_intlv);
+ debug("ctlr_intlv_mode %d\n", popts->ctlr_intlv_mode);
+
+ popts->ba_intlv = auto_bank_intlv(conf->cs_in_use, pdimm);
+ debug("ba_intlv 0x%x\n", popts->ba_intlv);
+}
+
+static int update_burst_length(struct memctl_opt *popts)
+{
+ /* Choose burst length. */
+ if ((popts->data_bus_used == DDR_DBUS_32) ||
+ (popts->data_bus_used == DDR_DBUS_16)) {
+ /* 32-bit or 16-bit bus */
+ popts->otf_burst_chop_en = 0;
+ popts->burst_length = DDR_BL8;
+ } else if (popts->otf_burst_chop_en != 0) { /* on-the-fly burst chop */
+ popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
+ } else {
+ popts->burst_length = DDR_BL8;
+ }
+ debug("data_bus_used %d\n", popts->data_bus_used);
+ debug("otf_burst_chop_en %d\n", popts->otf_burst_chop_en);
+ debug("burst_length 0x%x\n", popts->burst_length);
+ /*
+ * If a reduced data width is requested, but the SPD
+ * specifies a physically wider device, adjust the
+ * computed dimm capacities accordingly before
+ * assigning addresses.
+ * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
+ */
+ if (popts->data_bus_dimm > popts->data_bus_used) {
+ ERROR("Data bus configuration error\n");
+ return -EINVAL;
+ }
+ popts->dbw_cap_shift = popts->data_bus_used - popts->data_bus_dimm;
+ debug("dbw_cap_shift %d\n", popts->dbw_cap_shift);
+
+ return 0;
+}
+
+int cal_board_params(struct ddr_info *priv,
+ const struct board_timing *dimm,
+ int len)
+{
+ const unsigned long speed = priv->clk / 1000000;
+ const struct dimm_params *pdimm = &priv->dimm;
+ struct memctl_opt *popts = &priv->opt;
+ struct rc_timing const *prt = NULL;
+ struct rc_timing const *chosen = NULL;
+ int i;
+
+ for (i = 0; i < len; i++) {
+ if (pdimm->rc == dimm[i].rc) {
+ prt = dimm[i].p;
+ break;
+ }
+ }
+ if (prt == NULL) {
+ ERROR("Board parameters no match.\n");
+ return -EINVAL;
+ }
+ while (prt->speed_bin != 0) {
+ if (speed <= prt->speed_bin) {
+ chosen = prt;
+ break;
+ }
+ prt++;
+ }
+ if (chosen == NULL) {
+ ERROR("timing no match for speed %lu\n", speed);
+ return -EINVAL;
+ }
+ popts->clk_adj = prt->clk_adj;
+ popts->wrlvl_start = prt->wrlvl;
+ popts->wrlvl_ctl_2 = (prt->wrlvl * 0x01010101 + dimm[i].add1) &
+ 0xFFFFFFFF;
+ popts->wrlvl_ctl_3 = (prt->wrlvl * 0x01010101 + dimm[i].add2) &
+ 0xFFFFFFFF;
+
+ return 0;
+}
+
+static int synthesize_ctlr(struct ddr_info *priv)
+{
+ int ret;
+
+ ret = cal_odt(priv->clk,
+ &priv->opt,
+ &priv->conf,
+ &priv->dimm,
+ priv->dimm_on_ctlr);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = cal_opts(priv->clk,
+ &priv->opt,
+ &priv->conf,
+ &priv->dimm,
+ priv->dimm_on_ctlr,
+ priv->ip_rev);
+
+ if (ret != 0) {
+ return ret;
+ }
+
+ cal_intlv(priv->num_ctlrs, &priv->opt, &priv->conf, &priv->dimm);
+ ret = ddr_board_options(priv);
+ if (ret != 0) {
+ ERROR("Failed matching board timing.\n");
+ }
+
+ ret = update_burst_length(&priv->opt);
+
+ return ret;
+}
+
+/* Return the bit mask of valid DIMMs found */
+static int parse_spd(struct ddr_info *priv)
+{
+ struct ddr_conf *conf = &priv->conf;
+ struct dimm_params *dimm = &priv->dimm;
+ int j, valid_mask = 0;
+
+#ifdef CONFIG_DDR_NODIMM
+ valid_mask = ddr_get_ddr_params(dimm, conf);
+ if (valid_mask < 0) {
+ ERROR("DDR params error\n");
+ return valid_mask;
+ }
+#else
+ const int *spd_addr = priv->spd_addr;
+ const int num_ctlrs = priv->num_ctlrs;
+ const int num_dimm = priv->dimm_on_ctlr;
+ struct ddr4_spd spd[2];
+ unsigned int spd_checksum[2];
+ int addr_idx = 0;
+ int spd_idx = 0;
+ int ret, addr, i;
+
+ /* Scan all DIMMs */
+ for (i = 0; i < num_ctlrs; i++) {
+ debug("Controller %d\n", i);
+ for (j = 0; j < num_dimm; j++, addr_idx++) {
+ debug("DIMM %d\n", j);
+ addr = spd_addr[addr_idx];
+ if (addr == 0) {
+ if (j == 0) {
+ ERROR("First SPD addr wrong.\n");
+ return -EINVAL;
+ }
+ continue;
+ }
+ debug("addr 0x%x\n", addr);
+ ret = read_spd(addr, &spd[spd_idx],
+ sizeof(struct ddr4_spd));
+ if (ret != 0) { /* invalid */
+ debug("Invalid SPD at address 0x%x\n", addr);
+ continue;
+ }
+
+ spd_checksum[spd_idx] =
+ (spd[spd_idx].crc[1] << 24) |
+ (spd[spd_idx].crc[0] << 16) |
+ (spd[spd_idx].mod_section.uc[127] << 8) |
+ (spd[spd_idx].mod_section.uc[126] << 0);
+ debug("checksum 0x%x\n", spd_checksum[spd_idx]);
+ if (spd_checksum[spd_idx] == 0) {
+ debug("Bad checksum, ignored.\n");
+ continue;
+ }
+ if (spd_idx == 0) {
+ /* first valid SPD */
+ ret = cal_dimm_params(&spd[0], dimm);
+ if (ret != 0) {
+ ERROR("SPD calculation error\n");
+ return -EINVAL;
+ }
+ }
+
+ if (spd_idx != 0 && spd_checksum[0] !=
+ spd_checksum[spd_idx]) {
+ ERROR("Not identical DIMMs.\n");
+ return -EINVAL;
+ }
+ conf->dimm_in_use[j] = 1;
+ valid_mask |= 1 << addr_idx;
+ spd_idx = 1;
+ }
+ debug("done with controller %d\n", i);
+ }
+ switch (num_ctlrs) {
+ case 1:
+ if ((valid_mask & 0x1) == 0) {
+ ERROR("First slot cannot be empty.\n");
+ return -EINVAL;
+ }
+ break;
+ case 2:
+ switch (num_dimm) {
+ case 1:
+ if (valid_mask == 0) {
+ ERROR("Both slot empty\n");
+ return -EINVAL;
+ }
+ break;
+ case 2:
+ if (valid_mask != 0x5 &&
+ valid_mask != 0xf &&
+ (valid_mask & 0x7) != 0x4 &&
+ (valid_mask & 0xd) != 0x1) {
+ ERROR("Invalid DIMM combination.\n");
+ return -EINVAL;
+ }
+ break;
+ default:
+ ERROR("Invalid number of DIMMs.\n");
+ return -EINVAL;
+ }
+ break;
+ default:
+ ERROR("Invalid number of controllers.\n");
+ return -EINVAL;
+ }
+ /* now we have valid and identical DIMMs on controllers */
+#endif /* CONFIG_DDR_NODIMM */
+
+ debug("cal cs\n");
+ conf->cs_in_use = 0;
+ for (j = 0; j < DDRC_NUM_DIMM; j++) {
+ if (conf->dimm_in_use[j] == 0) {
+ continue;
+ }
+ switch (dimm->n_ranks) {
+ case 4:
+ ERROR("Quad-rank DIMM not supported\n");
+ return -EINVAL;
+ case 2:
+ conf->cs_on_dimm[j] = 0x3 << (j * CONFIG_CS_PER_SLOT);
+ conf->cs_in_use |= conf->cs_on_dimm[j];
+ break;
+ case 1:
+ conf->cs_on_dimm[j] = 0x1 << (j * CONFIG_CS_PER_SLOT);
+ conf->cs_in_use |= conf->cs_on_dimm[j];
+ break;
+ default:
+ ERROR("SPD error with n_ranks\n");
+ return -EINVAL;
+ }
+ debug("cs_in_use = %x\n", conf->cs_in_use);
+ debug("cs_on_dimm[%d] = %x\n", j, conf->cs_on_dimm[j]);
+ }
+#ifndef CONFIG_DDR_NODIMM
+ if (priv->dimm.rdimm != 0) {
+ NOTICE("RDIMM %s\n", priv->dimm.mpart);
+ } else {
+ NOTICE("UDIMM %s\n", priv->dimm.mpart);
+ }
+#else
+ NOTICE("%s\n", priv->dimm.mpart);
+#endif
+
+ return valid_mask;
+}
+
+static unsigned long long assign_intlv_addr(
+ const struct dimm_params *pdimm,
+ const struct memctl_opt *opt,
+ struct ddr_conf *conf,
+ const unsigned long long current_mem_base)
+{
+ int i;
+ int ctlr_density_mul = 0;
+ const unsigned long long rank_density = pdimm->rank_density >>
+ opt->dbw_cap_shift;
+ unsigned long long total_ctlr_mem;
+
+ debug("rank density 0x%llx\n", rank_density);
+ switch (opt->ba_intlv & DDR_BA_INTLV_CS0123) {
+ case DDR_BA_INTLV_CS0123:
+ ctlr_density_mul = 4;
+ break;
+ case DDR_BA_INTLV_CS01:
+ ctlr_density_mul = 2;
+ break;
+ default:
+ ctlr_density_mul = 1;
+ break;
+ }
+ debug("ctlr density mul %d\n", ctlr_density_mul);
+ switch (opt->ctlr_intlv_mode) {
+ case DDR_256B_INTLV:
+ total_ctlr_mem = 2 * ctlr_density_mul * rank_density;
+ break;
+ default:
+ ERROR("Unknown interleaving mode");
+ return 0;
+ }
+ conf->base_addr = current_mem_base;
+ conf->total_mem = total_ctlr_mem;
+
+ /* overwrite cs_in_use bitmask with controller interleaving */
+ conf->cs_in_use = (1 << ctlr_density_mul) - 1;
+ debug("Overwrite cs_in_use as %x\n", conf->cs_in_use);
+
+ /* Fill addr with each cs in use */
+ for (i = 0; i < ctlr_density_mul; i++) {
+ conf->cs_base_addr[i] = current_mem_base;
+ conf->cs_size[i] = total_ctlr_mem;
+ debug("CS %d\n", i);
+ debug(" base_addr 0x%llx\n", conf->cs_base_addr[i]);
+ debug(" size 0x%llx\n", conf->cs_size[i]);
+ }
+
+ return total_ctlr_mem;
+}
+
+static unsigned long long assign_non_intlv_addr(
+ const struct dimm_params *pdimm,
+ const struct memctl_opt *opt,
+ struct ddr_conf *conf,
+ unsigned long long current_mem_base)
+{
+ int i;
+ const unsigned long long rank_density = pdimm->rank_density >>
+ opt->dbw_cap_shift;
+ unsigned long long total_ctlr_mem = 0ULL;
+
+ debug("rank density 0x%llx\n", rank_density);
+ conf->base_addr = current_mem_base;
+
+ /* assign each cs */
+ switch (opt->ba_intlv & DDR_BA_INTLV_CS0123) {
+ case DDR_BA_INTLV_CS0123:
+ for (i = 0; i < DDRC_NUM_CS; i++) {
+ conf->cs_base_addr[i] = current_mem_base;
+ conf->cs_size[i] = rank_density << 2;
+ total_ctlr_mem += rank_density;
+ }
+ break;
+ case DDR_BA_INTLV_CS01:
+ for (i = 0; ((conf->cs_in_use & (1 << i)) != 0) && i < 2; i++) {
+ conf->cs_base_addr[i] = current_mem_base;
+ conf->cs_size[i] = rank_density << 1;
+ total_ctlr_mem += rank_density;
+ }
+ current_mem_base += total_ctlr_mem;
+ for (; ((conf->cs_in_use & (1 << i)) != 0) && i < DDRC_NUM_CS;
+ i++) {
+ conf->cs_base_addr[i] = current_mem_base;
+ conf->cs_size[i] = rank_density;
+ total_ctlr_mem += rank_density;
+ current_mem_base += rank_density;
+ }
+ break;
+ case DDR_BA_NONE:
+ for (i = 0; ((conf->cs_in_use & (1 << i)) != 0) &&
+ (i < DDRC_NUM_CS); i++) {
+ conf->cs_base_addr[i] = current_mem_base;
+ conf->cs_size[i] = rank_density;
+ current_mem_base += rank_density;
+ total_ctlr_mem += rank_density;
+ }
+ break;
+ default:
+ ERROR("Unsupported bank interleaving\n");
+ return 0;
+ }
+ for (i = 0; ((conf->cs_in_use & (1 << i)) != 0) &&
+ (i < DDRC_NUM_CS); i++) {
+ debug("CS %d\n", i);
+ debug(" base_addr 0x%llx\n", conf->cs_base_addr[i]);
+ debug(" size 0x%llx\n", conf->cs_size[i]);
+ }
+
+ return total_ctlr_mem;
+}
+
+unsigned long long assign_addresses(struct ddr_info *priv)
+ __attribute__ ((weak));
+
+unsigned long long assign_addresses(struct ddr_info *priv)
+{
+ struct memctl_opt *opt = &priv->opt;
+ const struct dimm_params *dimm = &priv->dimm;
+ struct ddr_conf *conf = &priv->conf;
+ unsigned long long current_mem_base = priv->mem_base;
+ unsigned long long total_mem;
+
+ total_mem = 0ULL;
+ debug("ctlr_intlv %d\n", opt->ctlr_intlv);
+ if (opt->ctlr_intlv != 0) {
+ total_mem = assign_intlv_addr(dimm, opt, conf,
+ current_mem_base);
+ } else {
+ /*
+ * Simple linear assignment if memory controllers are not
+ * interleaved. This is only valid for SoCs with single DDRC.
+ */
+ total_mem = assign_non_intlv_addr(dimm, opt, conf,
+ current_mem_base);
+ }
+ conf->total_mem = total_mem;
+ debug("base 0x%llx\n", current_mem_base);
+ debug("Total mem by assignment is 0x%llx\n", total_mem);
+
+ return total_mem;
+}
+
+static int cal_ddrc_regs(struct ddr_info *priv)
+{
+ int ret;
+
+ ret = compute_ddrc(priv->clk,
+ &priv->opt,
+ &priv->conf,
+ &priv->ddr_reg,
+ &priv->dimm,
+ priv->ip_rev);
+ if (ret != 0) {
+ ERROR("Calculating DDR registers failed\n");
+ }
+
+ return ret;
+}
+
+#endif /* CONFIG_STATIC_DDR */
+
+static int write_ddrc_regs(struct ddr_info *priv)
+{
+ int i;
+ int ret;
+
+ for (i = 0; i < priv->num_ctlrs; i++) {
+ ret = ddrc_set_regs(priv->clk, &priv->ddr_reg, priv->ddr[i], 0);
+ if (ret != 0) {
+ ERROR("Writing DDR register(s) failed\n");
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+long long dram_init(struct ddr_info *priv
+#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
+ , uintptr_t nxp_ccn_hn_f0_addr
+#endif
+ )
+{
+ uint64_t time __unused;
+ long long dram_size;
+ int ret;
+ const uint64_t time_base = get_timer_val(0);
+ unsigned int ip_rev = get_ddrc_version(priv->ddr[0]);
+
+ int valid_spd_mask __unused;
+ int scratch = 0x0;
+
+ priv->ip_rev = ip_rev;
+
+#ifndef CONFIG_STATIC_DDR
+ INFO("time base %llu ms\n", time_base);
+ debug("Parse DIMM SPD(s)\n");
+ valid_spd_mask = parse_spd(priv);
+
+ if (valid_spd_mask < 0) {
+ ERROR("Parsing DIMM Error\n");
+ return valid_spd_mask;
+ }
+
+#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
+ if (priv->num_ctlrs == 2 || priv->num_ctlrs == 1) {
+ ret = disable_unused_ddrc(priv, valid_spd_mask,
+ nxp_ccn_hn_f0_addr);
+ if (ret != 0) {
+ return ret;
+ }
+ }
+#endif
+
+ time = get_timer_val(time_base);
+ INFO("Time after parsing SPD %llu ms\n", time);
+ debug("Synthesize configurations\n");
+ ret = synthesize_ctlr(priv);
+ if (ret != 0) {
+ ERROR("Synthesize config error\n");
+ return ret;
+ }
+
+ debug("Assign binding addresses\n");
+ dram_size = assign_addresses(priv);
+ if (dram_size == 0) {
+ ERROR("Assigning address error\n");
+ return -EINVAL;
+ }
+
+ debug("Calculate controller registers\n");
+ ret = cal_ddrc_regs(priv);
+ if (ret != 0) {
+ ERROR("Calculate register error\n");
+ return ret;
+ }
+
+ ret = compute_ddr_phy(priv);
+ if (ret != 0)
+ ERROR("Calculating DDR PHY registers failed.\n");
+
+#else
+ dram_size = board_static_ddr(priv);
+ if (dram_size == 0) {
+ ERROR("Error getting static DDR settings.\n");
+ return -EINVAL;
+ }
+#endif
+
+ if (priv->warm_boot_flag == DDR_WARM_BOOT) {
+ scratch = (priv->ddr_reg).sdram_cfg[1];
+ scratch = scratch & ~(SDRAM_CFG2_D_INIT);
+ priv->ddr_reg.sdram_cfg[1] = scratch;
+ }
+
+ time = get_timer_val(time_base);
+ INFO("Time before programming controller %llu ms\n", time);
+ debug("Program controller registers\n");
+ ret = write_ddrc_regs(priv);
+ if (ret != 0) {
+ ERROR("Programing DDRC error\n");
+ return ret;
+ }
+
+ puts("");
+ NOTICE("%lld GB ", dram_size >> 30);
+ print_ddr_info(priv->ddr[0]);
+
+ time = get_timer_val(time_base);
+ INFO("Time used by DDR driver %llu ms\n", time);
+
+ return dram_size;
+}
diff --git a/drivers/nxp/ddr/nxp-ddr/ddr.mk b/drivers/nxp/ddr/nxp-ddr/ddr.mk
new file mode 100644
index 0000000..6bdd947
--- /dev/null
+++ b/drivers/nxp/ddr/nxp-ddr/ddr.mk
@@ -0,0 +1,76 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq ($(PLAT_DDR_PHY), PHY_GEN2)
+$(eval $(call add_define, PHY_GEN2))
+PLAT_DDR_PHY_DIR := phy-gen2
+ifeq (${APPLY_MAX_CDD},yes)
+$(eval $(call add_define,NXP_APPLY_MAX_CDD))
+endif
+
+ifeq (${ERRATA_DDR_A011396}, 1)
+$(eval $(call add_define,ERRATA_DDR_A011396))
+endif
+
+ifeq (${ERRATA_DDR_A050450}, 1)
+$(eval $(call add_define,ERRATA_DDR_A050450))
+endif
+
+endif
+
+ifeq ($(PLAT_DDR_PHY), PHY_GEN1)
+PLAT_DDR_PHY_DIR := phy-gen1
+
+ifeq (${ERRATA_DDR_A008511},1)
+$(eval $(call add_define,ERRATA_DDR_A008511))
+endif
+
+ifeq (${ERRATA_DDR_A009803},1)
+$(eval $(call add_define,ERRATA_DDR_A009803))
+endif
+
+ifeq (${ERRATA_DDR_A009942},1)
+$(eval $(call add_define,ERRATA_DDR_A009942))
+endif
+
+ifeq (${ERRATA_DDR_A010165},1)
+$(eval $(call add_define,ERRATA_DDR_A010165))
+endif
+
+endif
+
+ifeq ($(DDR_BIST), yes)
+$(eval $(call add_define, BIST_EN))
+endif
+
+ifeq ($(DDR_DEBUG), yes)
+$(eval $(call add_define, DDR_DEBUG))
+endif
+
+ifeq ($(DDR_PHY_DEBUG), yes)
+$(eval $(call add_define, DDR_PHY_DEBUG))
+endif
+
+ifeq ($(DEBUG_PHY_IO), yes)
+$(eval $(call add_define, DEBUG_PHY_IO))
+endif
+
+ifeq ($(DEBUG_WARM_RESET), yes)
+$(eval $(call add_define, DEBUG_WARM_RESET))
+endif
+
+ifeq ($(DEBUG_DDR_INPUT_CONFIG), yes)
+$(eval $(call add_define, DEBUG_DDR_INPUT_CONFIG))
+endif
+
+DDR_CNTLR_SOURCES := $(PLAT_DRIVERS_PATH)/ddr/nxp-ddr/ddr.c \
+ $(PLAT_DRIVERS_PATH)/ddr/nxp-ddr/ddrc.c \
+ $(PLAT_DRIVERS_PATH)/ddr/nxp-ddr/dimm.c \
+ $(PLAT_DRIVERS_PATH)/ddr/nxp-ddr/regs.c \
+ $(PLAT_DRIVERS_PATH)/ddr/nxp-ddr/utility.c \
+ $(PLAT_DRIVERS_PATH)/ddr/$(PLAT_DDR_PHY_DIR)/phy.c
+
+PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLUDE_PATH)/ddr
diff --git a/drivers/nxp/ddr/nxp-ddr/ddrc.c b/drivers/nxp/ddr/nxp-ddr/ddrc.c
new file mode 100644
index 0000000..17a2b6a
--- /dev/null
+++ b/drivers/nxp/ddr/nxp-ddr/ddrc.c
@@ -0,0 +1,594 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <common/debug.h>
+#include <ddr.h>
+#include <drivers/delay_timer.h>
+#include <immap.h>
+
+#define BIST_CR 0x80060000
+#define BIST_CR_EN 0x80000000
+#define BIST_CR_STAT 0x00000001
+#define CTLR_INTLV_MASK 0x20000000
+
+#pragma weak run_bist
+
+bool run_bist(void)
+{
+#ifdef BIST_EN
+ return true;
+#else
+ return false;
+#endif
+}
+
+/*
+ * Perform build-in test on memory
+ * timeout value in 10ms
+ */
+int bist(const struct ccsr_ddr *ddr, int timeout)
+{
+ const unsigned int test_pattern[10] = {
+ 0xffffffff,
+ 0x00000000,
+ 0xaaaaaaaa,
+ 0x55555555,
+ 0xcccccccc,
+ 0x33333333,
+ 0x12345678,
+ 0xabcdef01,
+ 0xaa55aa55,
+ 0x55aa55aa
+ };
+ unsigned int mtcr, err_detect, err_sbe;
+ unsigned int cs0_config;
+ unsigned int csn_bnds[4];
+ int ret = 0;
+ uint32_t i;
+#ifdef CONFIG_DDR_ADDR_DEC
+ uint32_t dec_9 = ddr_in32(&ddr->dec[9]);
+ uint32_t pos = 0U;
+ uint32_t map_save = 0U;
+ uint32_t temp32 = 0U;
+ uint32_t map, shift, highest;
+#endif
+
+ cs0_config = ddr_in32(&ddr->csn_cfg[0]);
+ if ((cs0_config & CTLR_INTLV_MASK) != 0U) {
+ /* set bnds to non-interleaving */
+ for (i = 0U; i < 4U; i++) {
+ csn_bnds[i] = ddr_in32(&ddr->bnds[i].a);
+ ddr_out32(&ddr->bnds[i].a,
+ (csn_bnds[i] & U(0xfffefffe)) >> 1U);
+ }
+ ddr_out32(&ddr->csn_cfg[0], cs0_config & ~CTLR_INTLV_MASK);
+#ifdef CONFIG_DDR_ADDR_DEC
+ if ((dec_9 & 0x1U) != 0U) {
+ highest = (dec_9 >> 26U) == U(0x3F) ? 0U : dec_9 >> 26U;
+ pos = 37U;
+ for (i = 0U; i < 36U; i++) { /* Go through all 37 */
+ if ((i % 4U) == 0U) {
+ temp32 = ddr_in32(&ddr->dec[i >> 2U]);
+ }
+ shift = (3U - i % 4U) * 8U + 2U;
+ map = (temp32 >> shift) & U(0x3F);
+ if (map > highest && map != U(0x3F)) {
+ highest = map;
+ pos = i;
+ }
+ }
+ debug("\nFound highest position %d, mapping to %d, ",
+ pos, highest);
+ map_save = ddr_in32(&ddr->dec[pos >> 2]);
+ shift = (3U - pos % 4U) * 8U + 2U;
+ debug("in dec[%d], bit %d (0x%x)\n",
+ pos >> 2U, shift, map_save);
+ temp32 = map_save & ~(U(0x3F) << shift);
+ temp32 |= 8U << shift;
+ ddr_out32(&ddr->dec[pos >> 2U], temp32);
+ timeout <<= 2U;
+ debug("Increase wait time to %d ms\n", timeout * 10);
+ }
+#endif
+ }
+ for (i = 0U; i < 10U; i++) {
+ ddr_out32(&ddr->mtp[i], test_pattern[i]);
+ }
+ mtcr = BIST_CR;
+ ddr_out32(&ddr->mtcr, mtcr);
+ do {
+ mdelay(10);
+ mtcr = ddr_in32(&ddr->mtcr);
+ } while (timeout-- > 0 && ((mtcr & BIST_CR_EN) != 0));
+ if (timeout <= 0) {
+ ERROR("Timeout\n");
+ } else {
+ debug("Timer remains %d\n", timeout);
+ }
+
+ err_detect = ddr_in32(&ddr->err_detect);
+ err_sbe = ddr_in32(&ddr->err_sbe);
+ if (err_detect != 0U || ((err_sbe & U(0xffff)) != 0U)) {
+ ERROR("ECC error detected\n");
+ ret = -EIO;
+ }
+
+ if ((cs0_config & CTLR_INTLV_MASK) != 0) {
+ for (i = 0U; i < 4U; i++) {
+ ddr_out32(&ddr->bnds[i].a, csn_bnds[i]);
+ }
+ ddr_out32(&ddr->csn_cfg[0], cs0_config);
+#ifdef CONFIG_DDR_ADDR_DEC
+ if ((dec_9 & U(0x1)) != 0U) {
+ ddr_out32(&ddr->dec[pos >> 2], map_save);
+ }
+#endif
+ }
+ if ((mtcr & BIST_CR_STAT) != 0) {
+ ERROR("Built-in self test failed\n");
+ ret = -EIO;
+ } else {
+ NOTICE("Build-in self test passed\n");
+ }
+
+ return ret;
+}
+
+void dump_ddrc(unsigned int *ddr)
+{
+#ifdef DDR_DEBUG
+ uint32_t i;
+ unsigned long val;
+
+ for (i = 0U; i < U(0x400); i++, ddr++) {
+ val = ddr_in32(ddr);
+ if (val != 0U) { /* skip zeros */
+ debug("*0x%lx = 0x%lx\n", (unsigned long)ddr, val);
+ }
+ }
+#endif
+}
+
+#ifdef ERRATA_DDR_A009803
+static void set_wait_for_bits_clear(const void *ptr,
+ unsigned int value,
+ unsigned int bits)
+{
+ int timeout = 1000;
+
+ ddr_out32(ptr, value);
+ do {
+ udelay(100);
+ } while (timeout-- > 0 && ((ddr_in32(ptr) & bits) != 0));
+
+ if (timeout <= 0) {
+ ERROR("wait for clear timeout.\n");
+ }
+}
+#endif
+
+#if (DDRC_NUM_CS > 4)
+#error Invalid setting for DDRC_NUM_CS
+#endif
+
+/*
+ * If supported by the platform, writing to DDR controller takes two
+ * passes to deassert DDR reset to comply with JEDEC specs for RDIMMs.
+ */
+int ddrc_set_regs(const unsigned long clk,
+ const struct ddr_cfg_regs *regs,
+ const struct ccsr_ddr *ddr,
+ int twopass)
+{
+ unsigned int i, bus_width;
+ unsigned int temp_sdram_cfg;
+ unsigned int total_mem_per_ctrl, total_mem_per_ctrl_adj;
+ const int mod_bnds = regs->cs[0].config & CTLR_INTLV_MASK;
+ int timeout;
+ int ret = 0;
+#if defined(ERRATA_DDR_A009942) || defined(ERRATA_DDR_A010165)
+ unsigned long ddr_freq;
+ unsigned int tmp;
+#ifdef ERRATA_DDR_A009942
+ unsigned int check;
+ unsigned int cpo_min = U(0xff);
+ unsigned int cpo_max = 0U;
+#endif
+#endif
+
+ if (twopass == 2U) {
+ goto after_reset;
+ }
+
+ /* Set cdr1 first in case 0.9v VDD is enabled for some SoCs*/
+ ddr_out32(&ddr->ddr_cdr1, regs->cdr[0]);
+
+ ddr_out32(&ddr->sdram_clk_cntl, regs->clk_cntl);
+
+ for (i = 0U; i < DDRC_NUM_CS; i++) {
+ if (mod_bnds != 0U) {
+ ddr_out32(&ddr->bnds[i].a,
+ (regs->cs[i].bnds & U(0xfffefffe)) >> 1U);
+ } else {
+ ddr_out32(&ddr->bnds[i].a, regs->cs[i].bnds);
+ }
+ ddr_out32(&ddr->csn_cfg_2[i], regs->cs[i].config_2);
+ }
+
+ ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg[0]);
+ ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg[1]);
+ ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg[2]);
+ ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg[3]);
+ ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg[4]);
+ ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg[5]);
+ ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg[6]);
+ ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg[7]);
+ ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg[8]);
+ ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg[9]);
+ ddr_out32(&ddr->zq_cntl, regs->zq_cntl);
+ for (i = 0U; i < 4U; i++) {
+ ddr_out32(&ddr->dq_map[i], regs->dq_map[i]);
+ }
+ ddr_out32(&ddr->sdram_cfg_3, regs->sdram_cfg[2]);
+ ddr_out32(&ddr->sdram_mode, regs->sdram_mode[0]);
+ ddr_out32(&ddr->sdram_mode_2, regs->sdram_mode[1]);
+ ddr_out32(&ddr->sdram_mode_3, regs->sdram_mode[2]);
+ ddr_out32(&ddr->sdram_mode_4, regs->sdram_mode[3]);
+ ddr_out32(&ddr->sdram_mode_5, regs->sdram_mode[4]);
+ ddr_out32(&ddr->sdram_mode_6, regs->sdram_mode[5]);
+ ddr_out32(&ddr->sdram_mode_7, regs->sdram_mode[6]);
+ ddr_out32(&ddr->sdram_mode_8, regs->sdram_mode[7]);
+ ddr_out32(&ddr->sdram_mode_9, regs->sdram_mode[8]);
+ ddr_out32(&ddr->sdram_mode_10, regs->sdram_mode[9]);
+ ddr_out32(&ddr->sdram_mode_11, regs->sdram_mode[10]);
+ ddr_out32(&ddr->sdram_mode_12, regs->sdram_mode[11]);
+ ddr_out32(&ddr->sdram_mode_13, regs->sdram_mode[12]);
+ ddr_out32(&ddr->sdram_mode_14, regs->sdram_mode[13]);
+ ddr_out32(&ddr->sdram_mode_15, regs->sdram_mode[14]);
+ ddr_out32(&ddr->sdram_mode_16, regs->sdram_mode[15]);
+ ddr_out32(&ddr->sdram_md_cntl, regs->md_cntl);
+#ifdef ERRATA_DDR_A009663
+ ddr_out32(&ddr->sdram_interval,
+ regs->interval & ~SDRAM_INTERVAL_BSTOPRE);
+#else
+ ddr_out32(&ddr->sdram_interval, regs->interval);
+#endif
+ ddr_out32(&ddr->sdram_data_init, regs->data_init);
+ if (regs->eor != 0) {
+ ddr_out32(&ddr->eor, regs->eor);
+ }
+
+ ddr_out32(&ddr->wrlvl_cntl, regs->wrlvl_cntl[0]);
+#ifndef NXP_DDR_EMU
+ /*
+ * Skip these two registers if running on emulator
+ * because emulator doesn't have skew between bytes.
+ */
+
+ if (regs->wrlvl_cntl[1] != 0) {
+ ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->wrlvl_cntl[1]);
+ }
+ if (regs->wrlvl_cntl[2] != 0) {
+ ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->wrlvl_cntl[2]);
+ }
+#endif
+
+ ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
+ ddr_out32(&ddr->ddr_sdram_rcw_1, regs->sdram_rcw[0]);
+ ddr_out32(&ddr->ddr_sdram_rcw_2, regs->sdram_rcw[1]);
+ ddr_out32(&ddr->ddr_sdram_rcw_3, regs->sdram_rcw[2]);
+ ddr_out32(&ddr->ddr_sdram_rcw_4, regs->sdram_rcw[3]);
+ ddr_out32(&ddr->ddr_sdram_rcw_5, regs->sdram_rcw[4]);
+ ddr_out32(&ddr->ddr_sdram_rcw_6, regs->sdram_rcw[5]);
+ ddr_out32(&ddr->ddr_cdr2, regs->cdr[1]);
+ ddr_out32(&ddr->sdram_cfg_2, regs->sdram_cfg[1]);
+ ddr_out32(&ddr->init_addr, regs->init_addr);
+ ddr_out32(&ddr->init_ext_addr, regs->init_ext_addr);
+
+#ifdef ERRATA_DDR_A009803
+ /* part 1 of 2 */
+ if ((regs->sdram_cfg[1] & SDRAM_CFG2_AP_EN) != 0) {
+ if ((regs->sdram_cfg[0] & SDRAM_CFG_RD_EN) != 0) {
+ ddr_out32(&ddr->ddr_sdram_rcw_2,
+ regs->sdram_rcw[1] & ~0xf0);
+ }
+
+ ddr_out32(&ddr->err_disable,
+ regs->err_disable | DDR_ERR_DISABLE_APED);
+ }
+#else
+ ddr_out32(&ddr->err_disable, regs->err_disable);
+#endif
+ ddr_out32(&ddr->err_int_en, regs->err_int_en);
+
+ /* For DDRC 5.05 only */
+ if (get_ddrc_version(ddr) == 0x50500) {
+ ddr_out32(&ddr->tx_cfg[1], 0x1f1f1f1f);
+ ddr_out32(&ddr->debug[3], 0x124a02c0);
+ }
+
+ for (i = 0U; i < 4U; i++) {
+ if (regs->tx_cfg[i] != 0) {
+ ddr_out32(&ddr->tx_cfg[i], regs->tx_cfg[i]);
+ }
+ }
+ for (i = 0U; i < 64U; i++) {
+ if (regs->debug[i] != 0) {
+#ifdef ERRATA_DDR_A009942
+ if (i == 28U) {
+ continue;
+ }
+#endif
+ ddr_out32(&ddr->debug[i], regs->debug[i]);
+ }
+ }
+#ifdef CONFIG_DDR_ADDR_DEC
+ if ((regs->dec[9] & 1) != 0U) {
+ for (i = 0U; i < 10U; i++) {
+ ddr_out32(&ddr->dec[i], regs->dec[i]);
+ }
+ if (mod_bnds != 0) {
+ debug("Disable address decoding\n");
+ ddr_out32(&ddr->dec[9], 0);
+ }
+ }
+#endif
+
+#ifdef ERRATA_DDR_A008511
+ /* Part 1 of 2 */
+ /* This erraum only applies to verion 5.2.1 */
+ if (get_ddrc_version(ddr) == 0x50200) {
+ ERROR("Unsupported SoC.\n");
+ } else if (get_ddrc_version(ddr) == 0x50201) {
+ ddr_out32(&ddr->debug[37], (U(1) << 31));
+ ddr_out32(&ddr->ddr_cdr2,
+ regs->cdr[1] | DDR_CDR2_VREF_TRAIN_EN);
+ } else {
+ debug("Erratum A008511 doesn't apply.\n");
+ }
+#endif
+
+#ifdef ERRATA_DDR_A009942
+ ddr_freq = clk / 1000000U;
+ tmp = ddr_in32(&ddr->debug[28]);
+ tmp &= U(0xff0fff00);
+ tmp |= ddr_freq <= 1333U ? U(0x0080006a) :
+ (ddr_freq <= 1600U ? U(0x0070006f) :
+ (ddr_freq <= 1867U ? U(0x00700076) : U(0x0060007b)));
+ if (regs->debug[28] != 0) {
+ tmp &= ~0xff;
+ tmp |= regs->debug[28] & 0xff;
+ } else {
+ WARN("Warning: Optimal CPO value not set.\n");
+ }
+ ddr_out32(&ddr->debug[28], tmp);
+#endif
+
+#ifdef ERRATA_DDR_A010165
+ ddr_freq = clk / 1000000U;
+ if ((ddr_freq > 1900) && (ddr_freq < 2300)) {
+ tmp = ddr_in32(&ddr->debug[28]);
+ ddr_out32(&ddr->debug[28], tmp | 0x000a0000);
+ }
+#endif
+ /*
+ * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
+ * deasserted. Clocks start when any chip select is enabled and clock
+ * control register is set. Because all DDR components are connected to
+ * one reset signal, this needs to be done in two steps. Step 1 is to
+ * get the clocks started. Step 2 resumes after reset signal is
+ * deasserted.
+ */
+ if (twopass == 1) {
+ udelay(200);
+ return 0;
+ }
+
+ /* As per new sequence flow shall be write CSn_CONFIG registers needs to
+ * be set after all the other DDR controller registers are set, then poll
+ * for PHY_INIT_CMPLT = 1 , then wait at least 100us (micro seconds),
+ * then set the MEM_EN = 1
+ */
+ for (i = 0U; i < DDRC_NUM_CS; i++) {
+ if (mod_bnds != 0U && i == 0U) {
+ ddr_out32(&ddr->csn_cfg[i],
+ (regs->cs[i].config & ~CTLR_INTLV_MASK));
+ } else {
+ ddr_out32(&ddr->csn_cfg[i], regs->cs[i].config);
+ }
+ }
+
+after_reset:
+ /* Set, but do not enable the memory */
+ temp_sdram_cfg = regs->sdram_cfg[0];
+ temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
+ ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);
+
+ if (get_ddrc_version(ddr) < U(0x50500)) {
+ /*
+ * 500 painful micro-seconds must elapse between
+ * the DDR clock setup and the DDR config enable.
+ * DDR2 need 200 us, and DDR3 need 500 us from spec,
+ * we choose the max, that is 500 us for all of case.
+ */
+ udelay(500);
+ /* applied memory barrier */
+ mb();
+ isb();
+ } else {
+ /* wait for PHY complete */
+ timeout = 40;
+ while (((ddr_in32(&ddr->ddr_dsr2) & 0x4) != 0) &&
+ (timeout > 0)) {
+ udelay(500);
+ timeout--;
+ }
+ if (timeout <= 0) {
+ printf("PHY handshake timeout, ddr_dsr2 = %x\n",
+ ddr_in32(&ddr->ddr_dsr2));
+ } else {
+ debug("PHY handshake completed, timer remains %d\n",
+ timeout);
+ }
+ }
+
+ temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg);
+ /* Let the controller go */
+ udelay(100);
+ ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
+
+ /* applied memory barrier */
+ mb();
+ isb();
+
+ total_mem_per_ctrl = 0;
+ for (i = 0; i < DDRC_NUM_CS; i++) {
+ if ((regs->cs[i].config & 0x80000000) == 0) {
+ continue;
+ }
+ total_mem_per_ctrl += 1 << (
+ ((regs->cs[i].config >> 14) & 0x3) + 2 +
+ ((regs->cs[i].config >> 8) & 0x7) + 12 +
+ ((regs->cs[i].config >> 4) & 0x3) + 0 +
+ ((regs->cs[i].config >> 0) & 0x7) + 8 +
+ ((regs->sdram_cfg[2] >> 4) & 0x3) +
+ 3 - ((regs->sdram_cfg[0] >> 19) & 0x3) -
+ 26); /* minus 26 (count of 64M) */
+ }
+ total_mem_per_ctrl_adj = total_mem_per_ctrl;
+ /*
+ * total memory / bus width = transactions needed
+ * transactions needed / data rate = seconds
+ * to add plenty of buffer, double the time
+ * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
+ * Let's wait for 800ms
+ */
+ bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
+ >> SDRAM_CFG_DBW_SHIFT);
+ timeout = ((total_mem_per_ctrl_adj << (6 - bus_width)) * 100 /
+ (clk >> 20)) << 2;
+ total_mem_per_ctrl_adj >>= 4; /* shift down to gb size */
+ if ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) != 0) {
+ debug("total size %d GB\n", total_mem_per_ctrl_adj);
+ debug("Need to wait up to %d ms\n", timeout * 10);
+
+ do {
+ mdelay(10);
+ } while (timeout-- > 0 &&
+ ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT)) != 0);
+
+ if (timeout <= 0) {
+ if (ddr_in32(&ddr->debug[1]) & 0x3d00) {
+ ERROR("Found training error(s): 0x%x\n",
+ ddr_in32(&ddr->debug[1]));
+ }
+ ERROR("Error: Waiting for D_INIT timeout.\n");
+ return -EIO;
+ }
+ }
+
+ if (mod_bnds != 0U) {
+ debug("Restore original bnds\n");
+ for (i = 0U; i < DDRC_NUM_CS; i++) {
+ ddr_out32(&ddr->bnds[i].a, regs->cs[i].bnds);
+ }
+ ddr_out32(&ddr->csn_cfg[0], regs->cs[0].config);
+#ifdef CONFIG_DDR_ADDR_DEC
+ if ((regs->dec[9] & U(0x1)) != 0U) {
+ debug("Restore address decoding\n");
+ ddr_out32(&ddr->dec[9], regs->dec[9]);
+ }
+#endif
+ }
+
+#ifdef ERRATA_DDR_A009803
+ /* Part 2 of 2 */
+ if ((regs->sdram_cfg[1] & SDRAM_CFG2_AP_EN) != 0) {
+ timeout = 400;
+ do {
+ mdelay(1);
+ } while (timeout-- > 0 && ((ddr_in32(&ddr->debug[1]) & 0x2) == 0));
+
+ if ((regs->sdram_cfg[0] & SDRAM_CFG_RD_EN) != 0) {
+ for (i = 0U; i < DDRC_NUM_CS; i++) {
+ if ((regs->cs[i].config & SDRAM_CS_CONFIG_EN) == 0) {
+ continue;
+ }
+ set_wait_for_bits_clear(&ddr->sdram_md_cntl,
+ MD_CNTL_MD_EN |
+ MD_CNTL_CS_SEL(i) |
+ 0x070000ed,
+ MD_CNTL_MD_EN);
+ udelay(1);
+ }
+ }
+
+ ddr_out32(&ddr->err_disable,
+ regs->err_disable & ~DDR_ERR_DISABLE_APED);
+ }
+#endif
+
+#ifdef ERRATA_DDR_A009663
+ ddr_out32(&ddr->sdram_interval, regs->interval);
+#endif
+
+#ifdef ERRATA_DDR_A009942
+ timeout = 400;
+ do {
+ mdelay(1);
+ } while (timeout-- > 0 && ((ddr_in32(&ddr->debug[1]) & 0x2) == 0));
+ tmp = (regs->sdram_cfg[0] >> 19) & 0x3;
+ check = (tmp == DDR_DBUS_64) ? 4 : ((tmp == DDR_DBUS_32) ? 2 : 1);
+ for (i = 0; i < check; i++) {
+ tmp = ddr_in32(&ddr->debug[9 + i]);
+ debug("Reading debug[%d] as 0x%x\n", i + 9, tmp);
+ cpo_min = min(cpo_min,
+ min((tmp >> 24) & 0xff, (tmp >> 8) & 0xff));
+ cpo_max = max(cpo_max,
+ max((tmp >> 24) & 0xff, (tmp >> 8) & 0xff));
+ }
+ if ((regs->sdram_cfg[0] & SDRAM_CFG_ECC_EN) != 0) {
+ tmp = ddr_in32(&ddr->debug[13]);
+ cpo_min = min(cpo_min, (tmp >> 24) & 0xff);
+ cpo_max = max(cpo_max, (tmp >> 24) & 0xff);
+ }
+ debug("cpo_min 0x%x\n", cpo_min);
+ debug("cpo_max 0x%x\n", cpo_max);
+ tmp = ddr_in32(&ddr->debug[28]);
+ debug("debug[28] 0x%x\n", tmp);
+ if ((cpo_min + 0x3B) < (tmp & 0xff)) {
+ WARN("Warning: A009942 requires setting cpo_sample to 0x%x\n",
+ (cpo_min + cpo_max) / 2 + 0x27);
+ } else {
+ debug("Optimal cpo_sample 0x%x\n",
+ (cpo_min + cpo_max) / 2 + 0x27);
+ }
+#endif
+ if (run_bist() != 0) {
+ if ((ddr_in32(&ddr->debug[1]) &
+ ((get_ddrc_version(ddr) == 0x50500) ? 0x3c00 : 0x3d00)) != 0) {
+ ERROR("Found training error(s): 0x%x\n",
+ ddr_in32(&ddr->debug[1]));
+ return -EIO;
+ }
+ INFO("Running built-in self test ...\n");
+ /* give it 10x time to cover whole memory */
+ timeout = ((total_mem_per_ctrl << (6 - bus_width)) *
+ 100 / (clk >> 20)) * 10;
+ INFO("\tWait up to %d ms\n", timeout * 10);
+ ret = bist(ddr, timeout);
+ }
+ dump_ddrc((void *)ddr);
+
+ return ret;
+}
diff --git a/drivers/nxp/ddr/nxp-ddr/dimm.c b/drivers/nxp/ddr/nxp-ddr/dimm.c
new file mode 100644
index 0000000..16efcba
--- /dev/null
+++ b/drivers/nxp/ddr/nxp-ddr/dimm.c
@@ -0,0 +1,399 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+
+#include <common/debug.h>
+#include <ddr.h>
+#include <dimm.h>
+#include <i2c.h>
+#include <lib/utils.h>
+
+int read_spd(unsigned char chip, void *buf, int len)
+{
+ unsigned char dummy = 0U;
+ int ret;
+
+ if (len < 256) {
+ ERROR("Invalid SPD length\n");
+ return -EINVAL;
+ }
+
+ i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1);
+ ret = i2c_read(chip, 0, 1, buf, 256);
+ if (ret == 0) {
+ i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1);
+ ret = i2c_read(chip, 0, 1, buf + 256, min(256, len - 256));
+ }
+ if (ret != 0) {
+ zeromem(buf, len);
+ }
+
+ return ret;
+}
+
+int crc16(unsigned char *ptr, int count)
+{
+ int i;
+ int crc = 0;
+
+ while (--count >= 0) {
+ crc = crc ^ (int)*ptr++ << 8;
+ for (i = 0; i < 8; ++i) {
+ if ((crc & 0x8000) != 0) {
+ crc = crc << 1 ^ 0x1021;
+ } else {
+ crc = crc << 1;
+ }
+ }
+ }
+ return crc & 0xffff;
+}
+
+static int ddr4_spd_check(const struct ddr4_spd *spd)
+{
+ void *p = (void *)spd;
+ int csum16;
+ int len;
+ char crc_lsb; /* byte 126 */
+ char crc_msb; /* byte 127 */
+
+ len = 126;
+ csum16 = crc16(p, len);
+
+ crc_lsb = (char) (csum16 & 0xff);
+ crc_msb = (char) (csum16 >> 8);
+
+ if (spd->crc[0] != crc_lsb || spd->crc[1] != crc_msb) {
+ ERROR("SPD CRC = 0x%x%x, computed CRC = 0x%x%x\n",
+ spd->crc[1], spd->crc[0], crc_msb, crc_lsb);
+ return -EINVAL;
+ }
+
+ p = (void *)spd + 128;
+ len = 126;
+ csum16 = crc16(p, len);
+
+ crc_lsb = (char) (csum16 & 0xff);
+ crc_msb = (char) (csum16 >> 8);
+
+ if (spd->mod_section.uc[126] != crc_lsb ||
+ spd->mod_section.uc[127] != crc_msb) {
+ ERROR("SPD CRC = 0x%x%x, computed CRC = 0x%x%x\n",
+ spd->mod_section.uc[127], spd->mod_section.uc[126],
+ crc_msb, crc_lsb);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static unsigned long long
+compute_ranksize(const struct ddr4_spd *spd)
+{
+ unsigned long long bsize;
+
+ int nbit_sdram_cap_bsize = 0;
+ int nbit_primary_bus_width = 0;
+ int nbit_sdram_width = 0;
+ int die_count = 0;
+ bool package_3ds;
+
+ if ((spd->density_banks & 0xf) <= 7) {
+ nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
+ }
+ if ((spd->bus_width & 0x7) < 4) {
+ nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
+ }
+ if ((spd->organization & 0x7) < 4) {
+ nbit_sdram_width = (spd->organization & 0x7) + 2;
+ }
+ package_3ds = (spd->package_type & 0x3) == 0x2;
+ if (package_3ds) {
+ die_count = (spd->package_type >> 4) & 0x7;
+ }
+
+ bsize = 1ULL << (nbit_sdram_cap_bsize - 3 +
+ nbit_primary_bus_width - nbit_sdram_width +
+ die_count);
+
+ return bsize;
+}
+
+int cal_dimm_params(const struct ddr4_spd *spd, struct dimm_params *pdimm)
+{
+ int ret;
+ int i;
+ static const unsigned char udimm_rc_e_dq[18] = {
+ 0x0c, 0x2c, 0x15, 0x35, 0x15, 0x35, 0x0b, 0x2c, 0x15,
+ 0x35, 0x0b, 0x35, 0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36
+ };
+ int spd_error = 0;
+ unsigned char *ptr;
+ unsigned char val;
+
+ if (spd->mem_type != SPD_MEMTYPE_DDR4) {
+ ERROR("Not a DDR4 DIMM.\n");
+ return -EINVAL;
+ }
+
+ ret = ddr4_spd_check(spd);
+ if (ret != 0) {
+ ERROR("DIMM SPD checksum mismatch\n");
+ return -EINVAL;
+ }
+
+ /*
+ * The part name in ASCII in the SPD EEPROM is not null terminated.
+ * Guarantee null termination here by presetting all bytes to 0
+ * and copying the part name in ASCII from the SPD onto it
+ */
+ if ((spd->info_size_crc & 0xF) > 2) {
+ memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
+ }
+
+ /* DIMM organization parameters */
+ pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
+ debug("n_ranks %d\n", pdimm->n_ranks);
+ pdimm->rank_density = compute_ranksize(spd);
+ if (pdimm->rank_density == 0) {
+ return -EINVAL;
+ }
+
+ debug("rank_density 0x%llx\n", pdimm->rank_density);
+ pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
+ debug("capacity 0x%llx\n", pdimm->capacity);
+ pdimm->die_density = spd->density_banks & 0xf;
+ debug("die density 0x%x\n", pdimm->die_density);
+ pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
+ debug("primary_sdram_width %d\n", pdimm->primary_sdram_width);
+ if (((spd->bus_width >> 3) & 0x3) != 0) {
+ pdimm->ec_sdram_width = 8;
+ } else {
+ pdimm->ec_sdram_width = 0;
+ }
+ debug("ec_sdram_width %d\n", pdimm->ec_sdram_width);
+ pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
+ debug("device_width %d\n", pdimm->device_width);
+ pdimm->package_3ds = (spd->package_type & 0x3) == 0x2 ?
+ (spd->package_type >> 4) & 0x7 : 0;
+ debug("package_3ds %d\n", pdimm->package_3ds);
+
+ switch (spd->module_type & DDR4_SPD_MODULETYPE_MASK) {
+ case DDR4_SPD_RDIMM:
+ case DDR4_SPD_MINI_RDIMM:
+ case DDR4_SPD_72B_SO_RDIMM:
+ pdimm->rdimm = 1;
+ pdimm->rc = spd->mod_section.registered.ref_raw_card & 0x8f;
+ if ((spd->mod_section.registered.reg_map & 0x1) != 0) {
+ pdimm->mirrored_dimm = 1;
+ }
+ val = spd->mod_section.registered.ca_stren;
+ pdimm->rcw[3] = val >> 4;
+ pdimm->rcw[4] = ((val & 0x3) << 2) | ((val & 0xc) >> 2);
+ val = spd->mod_section.registered.clk_stren;
+ pdimm->rcw[5] = ((val & 0x3) << 2) | ((val & 0xc) >> 2);
+ pdimm->rcw[6] = 0xf;
+ /* A17 used for 16Gb+, C[2:0] used for 3DS */
+ pdimm->rcw[8] = pdimm->die_density >= 0x6 ? 0x0 : 0x8 |
+ (pdimm->package_3ds > 0x3 ? 0x0 :
+ (pdimm->package_3ds > 0x1 ? 0x1 :
+ (pdimm->package_3ds > 0 ? 0x2 : 0x3)));
+ if (pdimm->package_3ds != 0 || pdimm->n_ranks != 4) {
+ pdimm->rcw[13] = 0x4;
+ } else {
+ pdimm->rcw[13] = 0x5;
+ }
+ pdimm->rcw[13] |= pdimm->mirrored_dimm ? 0x8 : 0;
+ break;
+
+ case DDR4_SPD_UDIMM:
+ case DDR4_SPD_SO_DIMM:
+ case DDR4_SPD_MINI_UDIMM:
+ case DDR4_SPD_72B_SO_UDIMM:
+ case DDR4_SPD_16B_SO_DIMM:
+ case DDR4_SPD_32B_SO_DIMM:
+ pdimm->rc = spd->mod_section.unbuffered.ref_raw_card & 0x8f;
+ if ((spd->mod_section.unbuffered.addr_mapping & 0x1) != 0) {
+ pdimm->mirrored_dimm = 1;
+ }
+ if ((spd->mod_section.unbuffered.mod_height & 0xe0) == 0 &&
+ (spd->mod_section.unbuffered.ref_raw_card == 0x04)) {
+ /* Fix SPD error found on DIMMs with raw card E0 */
+ for (i = 0; i < 18; i++) {
+ if (spd->mapping[i] == udimm_rc_e_dq[i]) {
+ continue;
+ }
+ spd_error = 1;
+ ptr = (unsigned char *)&spd->mapping[i];
+ *ptr = udimm_rc_e_dq[i];
+ }
+ if (spd_error != 0) {
+ INFO("SPD DQ mapping error fixed\n");
+ }
+ }
+ break;
+
+ default:
+ ERROR("Unknown module_type 0x%x\n", spd->module_type);
+ return -EINVAL;
+ }
+ debug("rdimm %d\n", pdimm->rdimm);
+ debug("mirrored_dimm %d\n", pdimm->mirrored_dimm);
+ debug("rc 0x%x\n", pdimm->rc);
+
+ /* SDRAM device parameters */
+ pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
+ debug("n_row_addr %d\n", pdimm->n_row_addr);
+ pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
+ debug("n_col_addr %d\n", pdimm->n_col_addr);
+ pdimm->bank_addr_bits = (spd->density_banks >> 4) & 0x3;
+ debug("bank_addr_bits %d\n", pdimm->bank_addr_bits);
+ pdimm->bank_group_bits = (spd->density_banks >> 6) & 0x3;
+ debug("bank_group_bits %d\n", pdimm->bank_group_bits);
+
+ if (pdimm->ec_sdram_width != 0) {
+ pdimm->edc_config = 0x02;
+ } else {
+ pdimm->edc_config = 0x00;
+ }
+ debug("edc_config %d\n", pdimm->edc_config);
+
+ /* DDR4 spec has BL8 -bit3, BC4 -bit2 */
+ pdimm->burst_lengths_bitmask = 0x0c;
+ debug("burst_lengths_bitmask 0x%x\n", pdimm->burst_lengths_bitmask);
+
+ /* MTB - medium timebase
+ * The MTB in the SPD spec is 125ps,
+ *
+ * FTB - fine timebase
+ * use 1/10th of ps as our unit to avoid floating point
+ * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps
+ */
+ if ((spd->timebases & 0xf) == 0x0) {
+ pdimm->mtb_ps = 125;
+ pdimm->ftb_10th_ps = 10;
+
+ } else {
+ ERROR("Unknown Timebases\n");
+ return -EINVAL;
+ }
+
+ /* sdram minimum cycle time */
+ pdimm->tckmin_x_ps = spd_to_ps(spd->tck_min, spd->fine_tck_min);
+ debug("tckmin_x_ps %d\n", pdimm->tckmin_x_ps);
+
+ /* sdram max cycle time */
+ pdimm->tckmax_ps = spd_to_ps(spd->tck_max, spd->fine_tck_max);
+ debug("tckmax_ps %d\n", pdimm->tckmax_ps);
+
+ /*
+ * CAS latency supported
+ * bit0 - CL7
+ * bit4 - CL11
+ * bit8 - CL15
+ * bit12- CL19
+ * bit16- CL23
+ */
+ pdimm->caslat_x = (spd->caslat_b1 << 7) |
+ (spd->caslat_b2 << 15) |
+ (spd->caslat_b3 << 23);
+ debug("caslat_x 0x%x\n", pdimm->caslat_x);
+
+ if (spd->caslat_b4 != 0) {
+ WARN("Unhandled caslat_b4 value\n");
+ }
+
+ /*
+ * min CAS latency time
+ */
+ pdimm->taa_ps = spd_to_ps(spd->taa_min, spd->fine_taa_min);
+ debug("taa_ps %d\n", pdimm->taa_ps);
+
+ /*
+ * min RAS to CAS delay time
+ */
+ pdimm->trcd_ps = spd_to_ps(spd->trcd_min, spd->fine_trcd_min);
+ debug("trcd_ps %d\n", pdimm->trcd_ps);
+
+ /*
+ * Min Row Precharge Delay Time
+ */
+ pdimm->trp_ps = spd_to_ps(spd->trp_min, spd->fine_trp_min);
+ debug("trp_ps %d\n", pdimm->trp_ps);
+
+ /* min active to precharge delay time */
+ pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) +
+ spd->tras_min_lsb) * pdimm->mtb_ps;
+ debug("tras_ps %d\n", pdimm->tras_ps);
+
+ /* min active to actice/refresh delay time */
+ pdimm->trc_ps = spd_to_ps((((spd->tras_trc_ext & 0xf0) << 4) +
+ spd->trc_min_lsb), spd->fine_trc_min);
+ debug("trc_ps %d\n", pdimm->trc_ps);
+ /* Min Refresh Recovery Delay Time */
+ pdimm->trfc1_ps = ((spd->trfc1_min_msb << 8) | (spd->trfc1_min_lsb)) *
+ pdimm->mtb_ps;
+ debug("trfc1_ps %d\n", pdimm->trfc1_ps);
+ pdimm->trfc2_ps = ((spd->trfc2_min_msb << 8) | (spd->trfc2_min_lsb)) *
+ pdimm->mtb_ps;
+ debug("trfc2_ps %d\n", pdimm->trfc2_ps);
+ pdimm->trfc4_ps = ((spd->trfc4_min_msb << 8) | (spd->trfc4_min_lsb)) *
+ pdimm->mtb_ps;
+ debug("trfc4_ps %d\n", pdimm->trfc4_ps);
+ /* min four active window delay time */
+ pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) *
+ pdimm->mtb_ps;
+ debug("tfaw_ps %d\n", pdimm->tfaw_ps);
+
+ /* min row active to row active delay time, different bank group */
+ pdimm->trrds_ps = spd_to_ps(spd->trrds_min, spd->fine_trrds_min);
+ debug("trrds_ps %d\n", pdimm->trrds_ps);
+ /* min row active to row active delay time, same bank group */
+ pdimm->trrdl_ps = spd_to_ps(spd->trrdl_min, spd->fine_trrdl_min);
+ debug("trrdl_ps %d\n", pdimm->trrdl_ps);
+ /* min CAS to CAS Delay Time (tCCD_Lmin), same bank group */
+ pdimm->tccdl_ps = spd_to_ps(spd->tccdl_min, spd->fine_tccdl_min);
+ debug("tccdl_ps %d\n", pdimm->tccdl_ps);
+ if (pdimm->package_3ds != 0) {
+ if (pdimm->die_density > 5) {
+ debug("Unsupported logical rank density 0x%x\n",
+ pdimm->die_density);
+ return -EINVAL;
+ }
+ pdimm->trfc_slr_ps = (pdimm->die_density <= 4) ?
+ 260000 : 350000;
+ }
+ debug("trfc_slr_ps %d\n", pdimm->trfc_slr_ps);
+
+ /* 15ns for all speed bins */
+ pdimm->twr_ps = 15000;
+ debug("twr_ps %d\n", pdimm->twr_ps);
+
+ /*
+ * Average periodic refresh interval
+ * tREFI = 7.8 us at normal temperature range
+ */
+ pdimm->refresh_rate_ps = 7800000;
+ debug("refresh_rate_ps %d\n", pdimm->refresh_rate_ps);
+
+ for (i = 0; i < 18; i++) {
+ pdimm->dq_mapping[i] = spd->mapping[i];
+ debug("dq_mapping 0x%x\n", pdimm->dq_mapping[i]);
+ }
+
+ pdimm->dq_mapping_ors = ((spd->mapping[0] >> 6) & 0x3) == 0 ? 1 : 0;
+ debug("dq_mapping_ors %d\n", pdimm->dq_mapping_ors);
+
+ return 0;
+}
diff --git a/drivers/nxp/ddr/nxp-ddr/regs.c b/drivers/nxp/ddr/nxp-ddr/regs.c
new file mode 100644
index 0000000..cedd7ca
--- /dev/null
+++ b/drivers/nxp/ddr/nxp-ddr/regs.c
@@ -0,0 +1,1394 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <common/debug.h>
+#include <ddr.h>
+#include <lib/utils.h>
+
+static inline unsigned int cal_cwl(const unsigned long clk)
+{
+ const unsigned int mclk_ps = get_memory_clk_ps(clk);
+
+ return mclk_ps >= 1250U ? 9U :
+ (mclk_ps >= 1070U ? 10U :
+ (mclk_ps >= 935U ? 11U :
+ (mclk_ps >= 833U ? 12U :
+ (mclk_ps >= 750U ? 14U :
+ (mclk_ps >= 625U ? 16U : 18U)))));
+}
+
+static void cal_csn_config(int i,
+ struct ddr_cfg_regs *regs,
+ const struct memctl_opt *popts,
+ const struct dimm_params *pdimm)
+{
+ unsigned int intlv_en = 0U;
+ unsigned int intlv_ctl = 0U;
+ const unsigned int cs_n_en = 1U;
+ const unsigned int ap_n_en = popts->cs_odt[i].auto_precharge;
+ const unsigned int odt_rd_cfg = popts->cs_odt[i].odt_rd_cfg;
+ const unsigned int odt_wr_cfg = popts->cs_odt[i].odt_wr_cfg;
+ const unsigned int ba_bits_cs_n = pdimm->bank_addr_bits;
+ const unsigned int row_bits_cs_n = pdimm->n_row_addr - 12U;
+ const unsigned int col_bits_cs_n = pdimm->n_col_addr - 8U;
+ const unsigned int bg_bits_cs_n = pdimm->bank_group_bits;
+
+ if (i == 0) {
+ /* These fields only available in CS0_CONFIG */
+ if (popts->ctlr_intlv != 0) {
+ switch (popts->ctlr_intlv_mode) {
+ case DDR_256B_INTLV:
+ intlv_en = popts->ctlr_intlv;
+ intlv_ctl = popts->ctlr_intlv_mode;
+ break;
+ default:
+ break;
+ }
+ }
+ }
+ regs->cs[i].config = ((cs_n_en & 0x1) << 31) |
+ ((intlv_en & 0x3) << 29) |
+ ((intlv_ctl & 0xf) << 24) |
+ ((ap_n_en & 0x1) << 23) |
+ ((odt_rd_cfg & 0x7) << 20) |
+ ((odt_wr_cfg & 0x7) << 16) |
+ ((ba_bits_cs_n & 0x3) << 14) |
+ ((row_bits_cs_n & 0x7) << 8) |
+ ((bg_bits_cs_n & 0x3) << 4) |
+ ((col_bits_cs_n & 0x7) << 0);
+ debug("cs%d\n", i);
+ debug(" _config = 0x%x\n", regs->cs[i].config);
+}
+
+static inline int avoid_odt_overlap(const struct ddr_conf *conf,
+ const struct dimm_params *pdimm)
+{
+ if ((conf->cs_in_use == 0xf) != 0) {
+ return 2;
+ }
+
+#if DDRC_NUM_DIMM >= 2
+ if (conf->dimm_in_use[0] != 0 && conf->dimm_in_use[1] != 0) {
+ return 1;
+ }
+#endif
+ return 0;
+}
+
+/* Requires rcw2 set first */
+static void cal_timing_cfg(const unsigned long clk,
+ struct ddr_cfg_regs *regs,
+ const struct memctl_opt *popts,
+ const struct dimm_params *pdimm,
+ const struct ddr_conf *conf,
+ unsigned int cas_latency,
+ unsigned int additive_latency)
+{
+ const unsigned int mclk_ps = get_memory_clk_ps(clk);
+ /* tXP=max(4nCK, 6ns) */
+ const int txp = max((int)mclk_ps * 4, 6000);
+ /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
+ static const int wrrec_table[] = {
+ 10, 10, 10, 10, 10,
+ 10, 10, 10, 10, 10,
+ 12, 12, 14, 14, 16,
+ 16, 18, 18, 20, 20,
+ 24, 24, 24, 24,
+ };
+ int trwt_mclk = (clk / 1000000 > 1900) ? 3 : 2;
+ int twrt_mclk;
+ int trrt_mclk;
+ int twwt_mclk;
+ const int act_pd_exit_mclk = picos_to_mclk(clk, txp);
+ const int pre_pd_exit_mclk = act_pd_exit_mclk;
+ const int taxpd_mclk = 0;
+ /*
+ * MRS_CYC = max(tMRD, tMOD)
+ * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
+ */
+ const int tmrd_mclk = max(24U, picos_to_mclk(clk, 15000));
+ const int pretoact_mclk = picos_to_mclk(clk, pdimm->trp_ps);
+ const int acttopre_mclk = picos_to_mclk(clk, pdimm->tras_ps);
+ const int acttorw_mclk = picos_to_mclk(clk, pdimm->trcd_ps);
+ const int caslat_ctrl = (cas_latency - 1) << 1;
+ const int trfc1_min = pdimm->die_density >= 0x3 ? 16000 :
+ (pdimm->die_density == 0x4 ? 26000 :
+ (pdimm->die_density == 0x5 ? 35000 :
+ 55000));
+ const int refrec_ctrl = picos_to_mclk(clk,
+ pdimm->trfc1_ps) - 8;
+ int wrrec_mclk = picos_to_mclk(clk, pdimm->twr_ps);
+ const int acttoact_mclk = max(picos_to_mclk(clk,
+ pdimm->trrds_ps),
+ 4U);
+ int wrtord_mclk = max(2U, picos_to_mclk(clk, 2500));
+ const unsigned int cpo = 0U;
+ const int wr_lat = cal_cwl(clk);
+ int rd_to_pre = picos_to_mclk(clk, 7500);
+ const int wr_data_delay = popts->wr_data_delay;
+ const int cke_pls = max(3U, picos_to_mclk(clk, 5000));
+#ifdef ERRATA_DDR_A050450
+ const unsigned short four_act = ((popts->twot_en == 0) &&
+ (popts->threet_en == 0) &&
+ (popts->tfaw_ps % 2 == 0)) ?
+ (picos_to_mclk(clk, popts->tfaw_ps) + 1) :
+ picos_to_mclk(clk, popts->tfaw_ps);
+#else
+ const unsigned short four_act = picos_to_mclk(clk,
+ popts->tfaw_ps);
+#endif
+ const unsigned int cntl_adj = 0U;
+ const unsigned int ext_pretoact = picos_to_mclk(clk,
+ pdimm->trp_ps) >> 4U;
+ const unsigned int ext_acttopre = picos_to_mclk(clk,
+ pdimm->tras_ps) >> 4U;
+ const unsigned int ext_acttorw = picos_to_mclk(clk,
+ pdimm->trcd_ps) >> 4U;
+ const unsigned int ext_caslat = (2U * cas_latency - 1U) >> 4U;
+ const unsigned int ext_add_lat = additive_latency >> 4U;
+ const unsigned int ext_refrec = (picos_to_mclk(clk,
+ pdimm->trfc1_ps) - 8U) >> 4U;
+ const unsigned int ext_wrrec = (picos_to_mclk(clk, pdimm->twr_ps) +
+ (popts->otf_burst_chop_en ? 2U : 0U)) >> 4U;
+ const unsigned int rwt_same_cs = 0U;
+ const unsigned int wrt_same_cs = 0U;
+ const unsigned int rrt_same_cs = popts->burst_length == DDR_BL8 ? 0U : 2U;
+ const unsigned int wwt_same_cs = popts->burst_length == DDR_BL8 ? 0U : 2U;
+ const unsigned int dll_lock = 2U;
+ unsigned int rodt_on = 0U;
+ const unsigned int rodt_off = 4U;
+ const unsigned int wodt_on = 1U;
+ const unsigned int wodt_off = 4U;
+ const unsigned int hs_caslat = 0U;
+ const unsigned int hs_wrlat = 0U;
+ const unsigned int hs_wrrec = 0U;
+ const unsigned int hs_clkadj = 0U;
+ const unsigned int hs_wrlvl_start = 0U;
+ const unsigned int txpr = max(5U,
+ picos_to_mclk(clk,
+ pdimm->trfc1_ps + 10000U));
+ const unsigned int tcksre = max(5U, picos_to_mclk(clk, 10000U));
+ const unsigned int tcksrx = max(5U, picos_to_mclk(clk, 10000U));
+ const unsigned int cs_to_cmd = 0U;
+ const unsigned int cke_rst = txpr <= 200U ? 0U :
+ (txpr <= 256U ? 1U :
+ (txpr <= 512U ? 2U : 3U));
+ const unsigned int cksre = tcksre <= 19U ? tcksre - 5U : 15U;
+ const unsigned int cksrx = tcksrx <= 19U ? tcksrx - 5U : 15U;
+ unsigned int par_lat = 0U;
+ const int tccdl = max(5U, picos_to_mclk(clk, pdimm->tccdl_ps));
+ int rwt_bg = cas_latency + 2 + 4 - wr_lat;
+ int wrt_bg = wr_lat + 4 + 1 - cas_latency;
+ const int rrt_bg = popts->burst_length == DDR_BL8 ?
+ tccdl - 4 : tccdl - 2;
+ const int wwt_bg = popts->burst_length == DDR_BL8 ?
+ tccdl - 4 : tccdl - 2;
+ const unsigned int acttoact_bg = picos_to_mclk(clk, pdimm->trrdl_ps);
+ const unsigned int wrtord_bg = max(4U, picos_to_mclk(clk, 7500)) +
+ (popts->otf_burst_chop_en ? 2 : 0);
+ const unsigned int pre_all_rec = 0;
+ const unsigned int refrec_cid_mclk = pdimm->package_3ds ?
+ picos_to_mclk(clk, pdimm->trfc_slr_ps) : 0;
+ const unsigned int acttoact_cid_mclk = pdimm->package_3ds ? 4U : 0;
+
+
+ /* for two dual-rank DIMMs to avoid ODT overlap */
+ if (avoid_odt_overlap(conf, pdimm) == 2) {
+ twrt_mclk = 2;
+ twwt_mclk = 2;
+ trrt_mclk = 2;
+ } else {
+ twrt_mclk = 1;
+ twwt_mclk = 1;
+ trrt_mclk = 0;
+ }
+
+ if (popts->trwt_override != 0) {
+ trwt_mclk = popts->trwt;
+ if (popts->twrt != 0) {
+ twrt_mclk = popts->twrt;
+ }
+ if (popts->trrt != 0) {
+ trrt_mclk = popts->trrt;
+ }
+ if (popts->twwt != 0) {
+ twwt_mclk = popts->twwt;
+ }
+ }
+ regs->timing_cfg[0] = (((trwt_mclk & 0x3) << 30) |
+ ((twrt_mclk & 0x3) << 28) |
+ ((trrt_mclk & 0x3) << 26) |
+ ((twwt_mclk & 0x3) << 24) |
+ ((act_pd_exit_mclk & 0xf) << 20) |
+ ((pre_pd_exit_mclk & 0xF) << 16) |
+ ((taxpd_mclk & 0xf) << 8) |
+ ((tmrd_mclk & 0x1f) << 0));
+ debug("timing_cfg[0] = 0x%x\n", regs->timing_cfg[0]);
+
+ if ((wrrec_mclk < 1) || (wrrec_mclk > 24)) {
+ ERROR("WRREC doesn't support clock %d\n", wrrec_mclk);
+ } else {
+ wrrec_mclk = wrrec_table[wrrec_mclk - 1];
+ }
+
+ if (popts->otf_burst_chop_en != 0) {
+ wrrec_mclk += 2;
+ wrtord_mclk += 2;
+ }
+
+ if (pdimm->trfc1_ps < trfc1_min) {
+ ERROR("trfc1_ps (%d) < %d\n", pdimm->trfc1_ps, trfc1_min);
+ }
+
+ regs->timing_cfg[1] = (((pretoact_mclk & 0x0F) << 28) |
+ ((acttopre_mclk & 0x0F) << 24) |
+ ((acttorw_mclk & 0xF) << 20) |
+ ((caslat_ctrl & 0xF) << 16) |
+ ((refrec_ctrl & 0xF) << 12) |
+ ((wrrec_mclk & 0x0F) << 8) |
+ ((acttoact_mclk & 0x0F) << 4) |
+ ((wrtord_mclk & 0x0F) << 0));
+ debug("timing_cfg[1] = 0x%x\n", regs->timing_cfg[1]);
+
+ if (rd_to_pre < 4) {
+ rd_to_pre = 4;
+ }
+ if (popts->otf_burst_chop_en) {
+ rd_to_pre += 2;
+ }
+
+ regs->timing_cfg[2] = (((additive_latency & 0xf) << 28) |
+ ((cpo & 0x1f) << 23) |
+ ((wr_lat & 0xf) << 19) |
+ (((wr_lat & 0x10) >> 4) << 18) |
+ ((rd_to_pre & 0xf) << 13) |
+ ((wr_data_delay & 0xf) << 9) |
+ ((cke_pls & 0x7) << 6) |
+ ((four_act & 0x3f) << 0));
+ debug("timing_cfg[2] = 0x%x\n", regs->timing_cfg[2]);
+
+ regs->timing_cfg[3] = (((ext_pretoact & 0x1) << 28) |
+ ((ext_acttopre & 0x3) << 24) |
+ ((ext_acttorw & 0x1) << 22) |
+ ((ext_refrec & 0x3F) << 16) |
+ ((ext_caslat & 0x3) << 12) |
+ ((ext_add_lat & 0x1) << 10) |
+ ((ext_wrrec & 0x1) << 8) |
+ ((cntl_adj & 0x7) << 0));
+ debug("timing_cfg[3] = 0x%x\n", regs->timing_cfg[3]);
+
+ regs->timing_cfg[4] = (((rwt_same_cs & 0xf) << 28) |
+ ((wrt_same_cs & 0xf) << 24) |
+ ((rrt_same_cs & 0xf) << 20) |
+ ((wwt_same_cs & 0xf) << 16) |
+ ((trwt_mclk & 0xc) << 12) |
+ ((twrt_mclk & 0x4) << 10) |
+ ((trrt_mclk & 0x4) << 8) |
+ ((twwt_mclk & 0x4) << 6) |
+ (dll_lock & 0x3));
+ debug("timing_cfg[4] = 0x%x\n", regs->timing_cfg[4]);
+
+ /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
+ if (cas_latency >= wr_lat) {
+ rodt_on = cas_latency - wr_lat + 1;
+ }
+
+ regs->timing_cfg[5] = (((rodt_on & 0x1f) << 24) |
+ ((rodt_off & 0x7) << 20) |
+ ((wodt_on & 0x1f) << 12) |
+ (wodt_off & 0x7) << 8);
+ debug("timing_cfg[5] = 0x%x\n", regs->timing_cfg[5]);
+
+ regs->timing_cfg[6] = (((hs_caslat & 0x1f) << 24) |
+ ((hs_wrlat & 0x1f) << 19) |
+ ((hs_wrrec & 0x1f) << 12) |
+ ((hs_clkadj & 0x1f) << 6) |
+ ((hs_wrlvl_start & 0x1f) << 0));
+ debug("timing_cfg[6] = 0x%x\n", regs->timing_cfg[6]);
+
+ if (popts->ap_en != 0) {
+ par_lat = (regs->sdram_rcw[1] & 0xf) + 1;
+ debug("PAR_LAT = 0x%x\n", par_lat);
+ }
+
+ regs->timing_cfg[7] = (((cke_rst & 0x3) << 28) |
+ ((cksre & 0xf) << 24) |
+ ((cksrx & 0xf) << 20) |
+ ((par_lat & 0xf) << 16) |
+ ((cs_to_cmd & 0xf) << 4));
+ debug("timing_cfg[7] = 0x%x\n", regs->timing_cfg[7]);
+
+ if (rwt_bg < tccdl) {
+ rwt_bg = tccdl - rwt_bg;
+ } else {
+ rwt_bg = 0;
+ }
+ if (wrt_bg < tccdl) {
+ wrt_bg = tccdl - wrt_bg;
+ } else {
+ wrt_bg = 0;
+ }
+ regs->timing_cfg[8] = (((rwt_bg & 0xf) << 28) |
+ ((wrt_bg & 0xf) << 24) |
+ ((rrt_bg & 0xf) << 20) |
+ ((wwt_bg & 0xf) << 16) |
+ ((acttoact_bg & 0xf) << 12) |
+ ((wrtord_bg & 0xf) << 8) |
+ ((pre_all_rec & 0x1f) << 0));
+ debug("timing_cfg[8] = 0x%x\n", regs->timing_cfg[8]);
+
+ regs->timing_cfg[9] = (refrec_cid_mclk & 0x3ff) << 16 |
+ (acttoact_cid_mclk & 0xf) << 8;
+ debug("timing_cfg[9] = 0x%x\n", regs->timing_cfg[9]);
+}
+
+static void cal_ddr_sdram_rcw(const unsigned long clk,
+ struct ddr_cfg_regs *regs,
+ const struct memctl_opt *popts,
+ const struct dimm_params *pdimm)
+{
+ const unsigned int freq = clk / 1000000U;
+ unsigned int rc0a, rc0f;
+
+ if (pdimm->rdimm == 0) {
+ return;
+ }
+
+ rc0a = freq > 3200U ? 7U :
+ (freq > 2933U ? 6U :
+ (freq > 2666U ? 5U :
+ (freq > 2400U ? 4U :
+ (freq > 2133U ? 3U :
+ (freq > 1866U ? 2U :
+ (freq > 1600U ? 1U : 0U))))));
+ rc0f = freq > 3200U ? 3U :
+ (freq > 2400U ? 2U :
+ (freq > 2133U ? 1U : 0U));
+ rc0f = (regs->sdram_cfg[1] & SDRAM_CFG2_AP_EN) ? rc0f : 4;
+ regs->sdram_rcw[0] =
+ pdimm->rcw[0] << 28 |
+ pdimm->rcw[1] << 24 |
+ pdimm->rcw[2] << 20 |
+ pdimm->rcw[3] << 16 |
+ pdimm->rcw[4] << 12 |
+ pdimm->rcw[5] << 8 |
+ pdimm->rcw[6] << 4 |
+ pdimm->rcw[7];
+ regs->sdram_rcw[1] =
+ pdimm->rcw[8] << 28 |
+ pdimm->rcw[9] << 24 |
+ rc0a << 20 |
+ pdimm->rcw[11] << 16 |
+ pdimm->rcw[12] << 12 |
+ pdimm->rcw[13] << 8 |
+ pdimm->rcw[14] << 4 |
+ rc0f;
+ regs->sdram_rcw[2] =
+ ((freq - 1260 + 19) / 20) << 8;
+
+ debug("sdram_rcw[0] = 0x%x\n", regs->sdram_rcw[0]);
+ debug("sdram_rcw[1] = 0x%x\n", regs->sdram_rcw[1]);
+ debug("sdram_rcw[2] = 0x%x\n", regs->sdram_rcw[2]);
+}
+
+static void cal_ddr_sdram_cfg(const unsigned long clk,
+ struct ddr_cfg_regs *regs,
+ const struct memctl_opt *popts,
+ const struct dimm_params *pdimm,
+ const unsigned int ip_rev)
+{
+ const unsigned int mem_en = 1U;
+ const unsigned int sren = popts->self_refresh_in_sleep;
+ const unsigned int ecc_en = popts->ecc_mode;
+ const unsigned int rd_en = (pdimm->rdimm != 0U) ? 1U : 0U;
+ const unsigned int dyn_pwr = popts->dynamic_power;
+ const unsigned int dbw = popts->data_bus_used;
+ const unsigned int eight_be = (dbw == 1U ||
+ popts->burst_length == DDR_BL8) ? 1U : 0U;
+ const unsigned int ncap = 0U;
+ const unsigned int threet_en = popts->threet_en;
+ const unsigned int twot_en = pdimm->rdimm ?
+ 0U : popts->twot_en;
+ const unsigned int ba_intlv = popts->ba_intlv;
+ const unsigned int x32_en = 0U;
+ const unsigned int pchb8 = 0U;
+ const unsigned int hse = popts->half_strength_drive_en;
+ const unsigned int acc_ecc_en = (dbw != 0U && ecc_en == 1U) ? 1U : 0U;
+ const unsigned int mem_halt = 0U;
+#ifdef PHY_GEN2
+ const unsigned int bi = 1U;
+#else
+ const unsigned int bi = 0U;
+#endif
+ const unsigned int sdram_type = SDRAM_TYPE_DDR4;
+ unsigned int odt_cfg = 0U;
+ const unsigned int frc_sr = 0U;
+ const unsigned int sr_ie = popts->self_refresh_irq_en;
+ const unsigned int num_pr = pdimm->package_3ds + 1U;
+ const unsigned int slow = (clk < 1249000000U) ? 1U : 0U;
+ const unsigned int x4_en = popts->x4_en;
+ const unsigned int obc_cfg = popts->otf_burst_chop_en;
+ const unsigned int ap_en = ip_rev == 0x50500U ? 0U : popts->ap_en;
+ const unsigned int d_init = popts->ctlr_init_ecc;
+ const unsigned int rcw_en = popts->rdimm;
+ const unsigned int md_en = popts->mirrored_dimm;
+ const unsigned int qd_en = popts->quad_rank_present;
+ const unsigned int unq_mrs_en = ip_rev < 0x50500U ? 1U : 0U;
+ const unsigned int rd_pre = popts->quad_rank_present;
+ int i;
+
+ regs->sdram_cfg[0] = ((mem_en & 0x1) << 31) |
+ ((sren & 0x1) << 30) |
+ ((ecc_en & 0x1) << 29) |
+ ((rd_en & 0x1) << 28) |
+ ((sdram_type & 0x7) << 24) |
+ ((dyn_pwr & 0x1) << 21) |
+ ((dbw & 0x3) << 19) |
+ ((eight_be & 0x1) << 18) |
+ ((ncap & 0x1) << 17) |
+ ((threet_en & 0x1) << 16) |
+ ((twot_en & 0x1) << 15) |
+ ((ba_intlv & 0x7F) << 8) |
+ ((x32_en & 0x1) << 5) |
+ ((pchb8 & 0x1) << 4) |
+ ((hse & 0x1) << 3) |
+ ((acc_ecc_en & 0x1) << 2) |
+ ((mem_halt & 0x1) << 1) |
+ ((bi & 0x1) << 0);
+ debug("sdram_cfg[0] = 0x%x\n", regs->sdram_cfg[0]);
+
+ for (i = 0; i < DDRC_NUM_CS; i++) {
+ if (popts->cs_odt[i].odt_rd_cfg != 0 ||
+ popts->cs_odt[i].odt_wr_cfg != 0) {
+ odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
+ break;
+ }
+ }
+
+ regs->sdram_cfg[1] = (0
+ | ((frc_sr & 0x1) << 31)
+ | ((sr_ie & 0x1) << 30)
+ | ((odt_cfg & 0x3) << 21)
+ | ((num_pr & 0xf) << 12)
+ | ((slow & 1) << 11)
+ | (x4_en << 10)
+ | (qd_en << 9)
+ | (unq_mrs_en << 8)
+ | ((obc_cfg & 0x1) << 6)
+ | ((ap_en & 0x1) << 5)
+ | ((d_init & 0x1) << 4)
+ | ((rcw_en & 0x1) << 2)
+ | ((md_en & 0x1) << 0)
+ );
+ debug("sdram_cfg[1] = 0x%x\n", regs->sdram_cfg[1]);
+
+ regs->sdram_cfg[2] = (rd_pre & 0x1) << 16 |
+ (popts->rdimm ? 1 : 0);
+ if (pdimm->package_3ds != 0) {
+ if (((pdimm->package_3ds + 1) & 0x1) != 0) {
+ WARN("Unsupported 3DS DIMM\n");
+ } else {
+ regs->sdram_cfg[2] |= ((pdimm->package_3ds + 1) >> 1)
+ << 4;
+ }
+ }
+ debug("sdram_cfg[2] = 0x%x\n", regs->sdram_cfg[2]);
+}
+
+
+static void cal_ddr_sdram_interval(const unsigned long clk,
+ struct ddr_cfg_regs *regs,
+ const struct memctl_opt *popts,
+ const struct dimm_params *pdimm)
+{
+ const unsigned int refint = picos_to_mclk(clk, pdimm->refresh_rate_ps);
+ const unsigned int bstopre = popts->bstopre;
+
+ regs->interval = ((refint & 0xFFFF) << 16) |
+ ((bstopre & 0x3FFF) << 0);
+ debug("interval = 0x%x\n", regs->interval);
+}
+
+/* Require cs and cfg first */
+static void cal_ddr_sdram_mode(const unsigned long clk,
+ struct ddr_cfg_regs *regs,
+ const struct memctl_opt *popts,
+ const struct ddr_conf *conf,
+ const struct dimm_params *pdimm,
+ unsigned int cas_latency,
+ unsigned int additive_latency,
+ const unsigned int ip_rev)
+{
+ int i;
+ unsigned short esdmode; /* Extended SDRAM mode */
+ unsigned short sdmode; /* SDRAM mode */
+
+ /* Mode Register - MR1 */
+ const unsigned int qoff = 0;
+ const unsigned int tdqs_en = 0;
+ unsigned int rtt;
+ const unsigned int wrlvl_en = 0;
+ unsigned int al = 0;
+ unsigned int dic = 0;
+ const unsigned int dll_en = 1;
+
+ /* Mode Register - MR0 */
+ unsigned int wr = 0;
+ const unsigned int dll_rst = 0;
+ const unsigned int mode = 0;
+ unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
+ /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
+ const unsigned int bt = 0;
+ const unsigned int bl = popts->burst_length == DDR_BL8 ? 0 :
+ (popts->burst_length == DDR_BC4 ? 2 : 1);
+
+ const unsigned int wr_mclk = picos_to_mclk(clk, pdimm->twr_ps);
+ /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
+ static const int wr_table[] = {
+ 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6
+ };
+ /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
+ static const int cas_latency_table[] = {
+ 0, 1, 2, 3, 4, 5, 6, 7, 13, 8,
+ 14, 9, 15, 10, 12, 11, 16, 17,
+ 18, 19, 20, 21, 22, 23
+ };
+ const unsigned int unq_mrs_en = ip_rev < U(0x50500) ? 1U : 0U;
+ unsigned short esdmode2 = 0U;
+ unsigned short esdmode3 = 0U;
+ const unsigned int wr_crc = 0U;
+ unsigned int rtt_wr = 0U;
+ const unsigned int srt = 0U;
+ unsigned int cwl = cal_cwl(clk);
+ const unsigned int mpr = 0U;
+ const unsigned int mclk_ps = get_memory_clk_ps(clk);
+ const unsigned int wc_lat = 0U;
+ unsigned short esdmode4 = 0U;
+ unsigned short esdmode5;
+ int rtt_park_all = 0;
+ unsigned int rtt_park;
+ const bool four_cs = conf->cs_in_use == 0xf ? true : false;
+ unsigned short esdmode6 = 0U; /* Extended SDRAM mode 6 */
+ unsigned short esdmode7 = 0U; /* Extended SDRAM mode 7 */
+ const unsigned int tccdl_min = max(5U,
+ picos_to_mclk(clk, pdimm->tccdl_ps));
+
+ if (popts->rtt_override != 0U) {
+ rtt = popts->rtt_override_value;
+ } else {
+ rtt = popts->cs_odt[0].odt_rtt_norm;
+ }
+
+ if (additive_latency == (cas_latency - 1)) {
+ al = 1;
+ }
+ if (additive_latency == (cas_latency - 2)) {
+ al = 2;
+ }
+
+ if (popts->quad_rank_present != 0 || popts->output_driver_impedance != 0) {
+ dic = 1; /* output driver impedance 240/7 ohm */
+ }
+
+ esdmode = (((qoff & 0x1) << 12) |
+ ((tdqs_en & 0x1) << 11) |
+ ((rtt & 0x7) << 8) |
+ ((wrlvl_en & 0x1) << 7) |
+ ((al & 0x3) << 3) |
+ ((dic & 0x3) << 1) |
+ ((dll_en & 0x1) << 0));
+
+ if (wr_mclk >= 10 && wr_mclk <= 24) {
+ wr = wr_table[wr_mclk - 10];
+ } else {
+ ERROR("unsupported wc_mclk = %d for mode register\n", wr_mclk);
+ }
+
+ /* look up table to get the cas latency bits */
+ if (cas_latency >= 9 && cas_latency <= 32) {
+ caslat = cas_latency_table[cas_latency - 9];
+ } else {
+ WARN("Error: unsupported cas latency for mode register\n");
+ }
+
+ sdmode = (((caslat & 0x10) << 8) |
+ ((wr & 0x7) << 9) |
+ ((dll_rst & 0x1) << 8) |
+ ((mode & 0x1) << 7) |
+ (((caslat >> 1) & 0x7) << 4) |
+ ((bt & 0x1) << 3) |
+ ((caslat & 1) << 2) |
+ ((bl & 0x3) << 0));
+
+ regs->sdram_mode[0] = (((esdmode & 0xFFFF) << 16) |
+ ((sdmode & 0xFFFF) << 0));
+ debug("sdram_mode[0] = 0x%x\n", regs->sdram_mode[0]);
+
+ switch (cwl) {
+ case 9:
+ case 10:
+ case 11:
+ case 12:
+ cwl -= 9;
+ break;
+ case 14:
+ cwl -= 10;
+ break;
+ case 16:
+ cwl -= 11;
+ break;
+ case 18:
+ cwl -= 12;
+ break;
+ case 20:
+ cwl -= 13;
+ break;
+ default:
+ printf("Error CWL\n");
+ break;
+ }
+
+ if (popts->rtt_override != 0) {
+ rtt_wr = popts->rtt_wr_override_value;
+ } else {
+ rtt_wr = popts->cs_odt[0].odt_rtt_wr;
+ }
+
+ esdmode2 = ((wr_crc & 0x1) << 12) |
+ ((rtt_wr & 0x7) << 9) |
+ ((srt & 0x3) << 6) |
+ ((cwl & 0x7) << 3);
+ esdmode3 = ((mpr & 0x3) << 11) | ((wc_lat & 0x3) << 9);
+
+ regs->sdram_mode[1] = ((esdmode2 & 0xFFFF) << 16) |
+ ((esdmode3 & 0xFFFF) << 0);
+ debug("sdram_mode[1] = 0x%x\n", regs->sdram_mode[1]);
+
+ esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
+ if (popts->vref_dimm != 0) {
+ esdmode6 |= popts->vref_dimm & 0x7f;
+ } else if ((popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2) != 0) {
+ esdmode6 |= 1 << 6; /* Range 2 */
+ }
+
+ regs->sdram_mode[9] = ((esdmode6 & 0xffff) << 16) |
+ ((esdmode7 & 0xffff) << 0);
+ debug("sdram_mode[9] = 0x%x\n", regs->sdram_mode[9]);
+
+ rtt_park = (popts->rtt_park != 0) ? popts->rtt_park : 240;
+ switch (rtt_park) {
+ case 240:
+ rtt_park = 0x4;
+ break;
+ case 120:
+ rtt_park = 0x2;
+ break;
+ case 80:
+ rtt_park = 0x6;
+ break;
+ case 60:
+ rtt_park = 0x1;
+ break;
+ case 48:
+ rtt_park = 0x5;
+ break;
+ case 40:
+ rtt_park = 0x3;
+ break;
+ case 34:
+ rtt_park = 0x7;
+ break;
+ default:
+ rtt_park = 0;
+ break;
+ }
+
+ for (i = 0; i < DDRC_NUM_CS; i++) {
+ if (i != 0 && unq_mrs_en == 0) {
+ break;
+ }
+
+ if (popts->rtt_override != 0) {
+ rtt = popts->rtt_override_value;
+ rtt_wr = popts->rtt_wr_override_value;
+ } else {
+ rtt = popts->cs_odt[i].odt_rtt_norm;
+ rtt_wr = popts->cs_odt[i].odt_rtt_wr;
+ }
+
+ esdmode &= 0xF8FF; /* clear bit 10,9,8 for rtt */
+ esdmode |= (rtt & 0x7) << 8;
+ esdmode2 &= 0xF9FF; /* clear bit 10, 9 */
+ esdmode2 |= (rtt_wr & 0x3) << 9;
+ esdmode5 = (popts->x4_en) ? 0 : 0x400; /* data mask */
+
+ if (rtt_park_all == 0 &&
+ ((regs->cs[i].config & SDRAM_CS_CONFIG_EN) != 0)) {
+ esdmode5 |= rtt_park << 6;
+ rtt_park_all = four_cs ? 0 : 1;
+ }
+
+ if (((regs->sdram_cfg[1] & SDRAM_CFG2_AP_EN) != 0) &&
+ (popts->rdimm == 0)) {
+ if (mclk_ps >= 935) {
+ esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
+ } else if (mclk_ps >= 833) {
+ esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
+ } else {
+ esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
+ WARN("mclk_ps not supported %d", mclk_ps);
+
+ }
+ }
+
+ switch (i) {
+ case 0:
+ regs->sdram_mode[8] = ((esdmode4 & 0xffff) << 16) |
+ ((esdmode5 & 0xffff) << 0);
+ debug("sdram_mode[8] = 0x%x\n", regs->sdram_mode[8]);
+ break;
+ case 1:
+ regs->sdram_mode[2] = (((esdmode & 0xFFFF) << 16) |
+ ((sdmode & 0xFFFF) << 0));
+ regs->sdram_mode[3] = ((esdmode2 & 0xFFFF) << 16) |
+ ((esdmode3 & 0xFFFF) << 0);
+ regs->sdram_mode[10] = ((esdmode4 & 0xFFFF) << 16) |
+ ((esdmode5 & 0xFFFF) << 0);
+ regs->sdram_mode[11] = ((esdmode6 & 0xFFFF) << 16) |
+ ((esdmode7 & 0xFFFF) << 0);
+ debug("sdram_mode[2] = 0x%x\n", regs->sdram_mode[2]);
+ debug("sdram_mode[3] = 0x%x\n", regs->sdram_mode[3]);
+ debug("sdram_mode[10] = 0x%x\n", regs->sdram_mode[10]);
+ debug("sdram_mode[11] = 0x%x\n", regs->sdram_mode[11]);
+ break;
+ case 2:
+ regs->sdram_mode[4] = (((esdmode & 0xFFFF) << 16) |
+ ((sdmode & 0xFFFF) << 0));
+ regs->sdram_mode[5] = ((esdmode2 & 0xFFFF) << 16) |
+ ((esdmode3 & 0xFFFF) << 0);
+ regs->sdram_mode[12] = ((esdmode4 & 0xFFFF) << 16) |
+ ((esdmode5 & 0xFFFF) << 0);
+ regs->sdram_mode[13] = ((esdmode6 & 0xFFFF) << 16) |
+ ((esdmode7 & 0xFFFF) << 0);
+ debug("sdram_mode[4] = 0x%x\n", regs->sdram_mode[4]);
+ debug("sdram_mode[5] = 0x%x\n", regs->sdram_mode[5]);
+ debug("sdram_mode[12] = 0x%x\n", regs->sdram_mode[12]);
+ debug("sdram_mode[13] = 0x%x\n", regs->sdram_mode[13]);
+ break;
+ case 3:
+ regs->sdram_mode[6] = (((esdmode & 0xFFFF) << 16) |
+ ((sdmode & 0xFFFF) << 0));
+ regs->sdram_mode[7] = ((esdmode2 & 0xFFFF) << 16) |
+ ((esdmode3 & 0xFFFF) << 0);
+ regs->sdram_mode[14] = ((esdmode4 & 0xFFFF) << 16) |
+ ((esdmode5 & 0xFFFF) << 0);
+ regs->sdram_mode[15] = ((esdmode6 & 0xFFFF) << 16) |
+ ((esdmode7 & 0xFFFF) << 0);
+ debug("sdram_mode[6] = 0x%x\n", regs->sdram_mode[6]);
+ debug("sdram_mode[7] = 0x%x\n", regs->sdram_mode[7]);
+ debug("sdram_mode[14] = 0x%x\n", regs->sdram_mode[14]);
+ debug("sdram_mode[15] = 0x%x\n", regs->sdram_mode[15]);
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+#ifndef CONFIG_MEM_INIT_VALUE
+#define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
+#endif
+static void cal_ddr_data_init(struct ddr_cfg_regs *regs)
+{
+ regs->data_init = CONFIG_MEM_INIT_VALUE;
+}
+
+static void cal_ddr_dq_mapping(struct ddr_cfg_regs *regs,
+ const struct dimm_params *pdimm)
+{
+ const unsigned int acc_ecc_en = (regs->sdram_cfg[0] >> 2) & 0x1;
+/* FIXME: revert the dq mapping from DIMM */
+ regs->dq_map[0] = ((pdimm->dq_mapping[0] & 0x3F) << 26) |
+ ((pdimm->dq_mapping[1] & 0x3F) << 20) |
+ ((pdimm->dq_mapping[2] & 0x3F) << 14) |
+ ((pdimm->dq_mapping[3] & 0x3F) << 8) |
+ ((pdimm->dq_mapping[4] & 0x3F) << 2);
+
+ regs->dq_map[1] = ((pdimm->dq_mapping[5] & 0x3F) << 26) |
+ ((pdimm->dq_mapping[6] & 0x3F) << 20) |
+ ((pdimm->dq_mapping[7] & 0x3F) << 14) |
+ ((pdimm->dq_mapping[10] & 0x3F) << 8) |
+ ((pdimm->dq_mapping[11] & 0x3F) << 2);
+
+ regs->dq_map[2] = ((pdimm->dq_mapping[12] & 0x3F) << 26) |
+ ((pdimm->dq_mapping[13] & 0x3F) << 20) |
+ ((pdimm->dq_mapping[14] & 0x3F) << 14) |
+ ((pdimm->dq_mapping[15] & 0x3F) << 8) |
+ ((pdimm->dq_mapping[16] & 0x3F) << 2);
+
+ /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
+ regs->dq_map[3] = ((pdimm->dq_mapping[17] & 0x3F) << 26) |
+ ((pdimm->dq_mapping[8] & 0x3F) << 20) |
+ ((acc_ecc_en != 0) ? 0 :
+ (pdimm->dq_mapping[9] & 0x3F) << 14) |
+ pdimm->dq_mapping_ors;
+ debug("dq_map[0] = 0x%x\n", regs->dq_map[0]);
+ debug("dq_map[1] = 0x%x\n", regs->dq_map[1]);
+ debug("dq_map[2] = 0x%x\n", regs->dq_map[2]);
+ debug("dq_map[3] = 0x%x\n", regs->dq_map[3]);
+}
+static void cal_ddr_zq_cntl(struct ddr_cfg_regs *regs)
+{
+ const unsigned int zqinit = 10U; /* 1024 clocks */
+ const unsigned int zqoper = 9U; /* 512 clocks */
+ const unsigned int zqcs = 7U; /* 128 clocks */
+ const unsigned int zqcs_init = 5U; /* 1024 refresh seqences */
+ const unsigned int zq_en = 1U; /* enabled */
+
+ regs->zq_cntl = ((zq_en & 0x1) << 31) |
+ ((zqinit & 0xF) << 24) |
+ ((zqoper & 0xF) << 16) |
+ ((zqcs & 0xF) << 8) |
+ ((zqcs_init & 0xF) << 0);
+ debug("zq_cntl = 0x%x\n", regs->zq_cntl);
+}
+
+static void cal_ddr_sr_cntr(struct ddr_cfg_regs *regs,
+ const struct memctl_opt *popts)
+{
+ const unsigned int sr_it = (popts->auto_self_refresh_en) ?
+ popts->sr_it : 0;
+
+ regs->ddr_sr_cntr = (sr_it & 0xF) << 16;
+ debug("ddr_sr_cntr = 0x%x\n", regs->ddr_sr_cntr);
+}
+
+static void cal_ddr_eor(struct ddr_cfg_regs *regs,
+ const struct memctl_opt *popts)
+{
+ if (popts->addr_hash != 0) {
+ regs->eor = 0x40000000; /* address hash enable */
+ debug("eor = 0x%x\n", regs->eor);
+ }
+}
+
+static void cal_ddr_csn_bnds(struct ddr_cfg_regs *regs,
+ const struct memctl_opt *popts,
+ const struct ddr_conf *conf,
+ const struct dimm_params *pdimm)
+{
+ int i;
+ unsigned long long ea, sa;
+
+ /* Chip Select Memory Bounds (CSn_BNDS) */
+ for (i = 0;
+ i < DDRC_NUM_CS && conf->cs_size[i];
+ i++) {
+ debug("cs_in_use = 0x%x\n", conf->cs_in_use);
+ if (conf->cs_in_use != 0) {
+ sa = conf->cs_base_addr[i];
+ ea = sa + conf->cs_size[i] - 1;
+ sa >>= 24;
+ ea >>= 24;
+ regs->cs[i].bnds = ((sa & 0xffff) << 16) |
+ ((ea & 0xffff) << 0);
+ cal_csn_config(i, regs, popts, pdimm);
+ } else {
+ /* setting bnds to 0xffffffff for inactive CS */
+ regs->cs[i].bnds = 0xffffffff;
+ }
+
+ debug("cs[%d].bnds = 0x%x\n", i, regs->cs[i].bnds);
+ }
+}
+
+static void cal_ddr_addr_dec(struct ddr_cfg_regs *regs)
+{
+#ifdef CONFIG_DDR_ADDR_DEC
+ unsigned int ba_bits __unused;
+ char p __unused;
+ const unsigned int cs0_config = regs->cs[0].config;
+ const int cacheline = PLATFORM_CACHE_LINE_SHIFT;
+ unsigned int bg_bits;
+ unsigned int row_bits;
+ unsigned int col_bits;
+ unsigned int cs;
+ unsigned int map_row[18];
+ unsigned int map_col[11];
+ unsigned int map_ba[2];
+ unsigned int map_cid[2] = {0x3F, 0x3F};
+ unsigned int map_bg[2] = {0x3F, 0x3F};
+ unsigned int map_cs[2] = {0x3F, 0x3F};
+ unsigned int dbw;
+ unsigned int ba_intlv;
+ int placement;
+ int intlv;
+ int abort = 0;
+ int i;
+ int j;
+
+ col_bits = (cs0_config >> 0) & 0x7;
+ if (col_bits < 4) {
+ col_bits += 8;
+ } else if (col_bits < 7 || col_bits > 10) {
+ ERROR("Error %s col_bits = %d\n", __func__, col_bits);
+ }
+ row_bits = ((cs0_config >> 8) & 0x7) + 12;
+ ba_bits = ((cs0_config >> 14) & 0x3) + 2;
+ bg_bits = ((cs0_config >> 4) & 0x3) + 0;
+ intlv = (cs0_config >> 24) & 0xf;
+ ba_intlv = (regs->sdram_cfg[0] >> 8) & 0x7f;
+ switch (ba_intlv) {
+ case DDR_BA_INTLV_CS01:
+ cs = 1;
+ break;
+ case DDR_BA_INTLV_CS0123:
+ cs = 2;
+ break;
+ case DDR_BA_NONE:
+ cs = 0;
+ break;
+ default:
+ ERROR("%s ba_intlv 0x%x\n", __func__, ba_intlv);
+ return;
+ }
+ debug("col %d, row %d, ba %d, bg %d, intlv %d\n",
+ col_bits, row_bits, ba_bits, bg_bits, intlv);
+ /*
+ * Example mapping of 15x2x2x10
+ * ---- --rr rrrr rrrr rrrr rCBB Gccc cccI cGcc cbbb
+ */
+ dbw = (regs->sdram_cfg[0] >> 19) & 0x3;
+ switch (dbw) {
+ case 0: /* 64-bit */
+ placement = 3;
+ break;
+ case 1: /* 32-bit */
+ placement = 2;
+ break;
+ default:
+ ERROR("%s dbw = %d\n", __func__, dbw);
+ return;
+ }
+ debug("cacheline size %d\n", cacheline);
+ for (i = 0; placement < cacheline; i++) {
+ map_col[i] = placement++;
+ }
+ map_bg[0] = placement++;
+ for ( ; i < col_bits; i++) {
+ map_col[i] = placement++;
+ if (placement == intlv) {
+ placement++;
+ }
+ }
+ for ( ; i < 11; i++) {
+ map_col[i] = 0x3F; /* unused col bits */
+ }
+
+ if (bg_bits >= 2) {
+ map_bg[1] = placement++;
+ }
+ map_ba[0] = placement++;
+ map_ba[1] = placement++;
+ if (cs != 0U) {
+ map_cs[0] = placement++;
+ if (cs == 2U) {
+ map_cs[1] = placement++;
+ }
+ } else {
+ map_cs[0] = U(0x3F);
+ }
+
+ for (i = 0; i < row_bits; i++) {
+ map_row[i] = placement++;
+ }
+
+ for ( ; i < 18; i++) {
+ map_row[i] = 0x3F; /* unused row bits */
+ }
+
+ for (i = 39; i >= 0 ; i--) {
+ if (i == intlv) {
+ placement = 8;
+ p = 'I';
+ } else if (i < 3) {
+ p = 'b';
+ placement = 0;
+ } else {
+ placement = 0;
+ p = '-';
+ }
+ for (j = 0; j < 18; j++) {
+ if (map_row[j] != i) {
+ continue;
+ }
+ if (placement != 0) {
+ abort = 1;
+ ERROR("%s wrong address bit %d\n", __func__, i);
+ }
+ placement = i;
+ p = 'r';
+ }
+ for (j = 0; j < 11; j++) {
+ if (map_col[j] != i) {
+ continue;
+ }
+ if (placement != 0) {
+ abort = 1;
+ ERROR("%s wrong address bit %d\n", __func__, i);
+ }
+ placement = i;
+ p = 'c';
+ }
+ for (j = 0; j < 2; j++) {
+ if (map_ba[j] != i) {
+ continue;
+ }
+ if (placement != 0) {
+ abort = 1;
+ ERROR("%s wrong address bit %d\n", __func__, i);
+ }
+ placement = i;
+ p = 'B';
+ }
+ for (j = 0; j < 2; j++) {
+ if (map_bg[j] != i) {
+ continue;
+ }
+ if (placement != 0) {
+ abort = 1;
+ ERROR("%s wrong address bit %d\n", __func__, i);
+ }
+ placement = i;
+ p = 'G';
+ }
+ for (j = 0; j < 2; j++) {
+ if (map_cs[j] != i) {
+ continue;
+ }
+ if (placement != 0) {
+ abort = 1;
+ ERROR("%s wrong address bit %d\n", __func__, i);
+ }
+ placement = i;
+ p = 'C';
+ }
+#ifdef DDR_DEBUG
+ printf("%c", p);
+ if ((i % 4) == 0) {
+ printf(" ");
+ }
+#endif
+ }
+#ifdef DDR_DEBUG
+ puts("\n");
+#endif
+
+ if (abort != 0) {
+ return;
+ }
+
+ regs->dec[0] = map_row[17] << 26 |
+ map_row[16] << 18 |
+ map_row[15] << 10 |
+ map_row[14] << 2;
+ regs->dec[1] = map_row[13] << 26 |
+ map_row[12] << 18 |
+ map_row[11] << 10 |
+ map_row[10] << 2;
+ regs->dec[2] = map_row[9] << 26 |
+ map_row[8] << 18 |
+ map_row[7] << 10 |
+ map_row[6] << 2;
+ regs->dec[3] = map_row[5] << 26 |
+ map_row[4] << 18 |
+ map_row[3] << 10 |
+ map_row[2] << 2;
+ regs->dec[4] = map_row[1] << 26 |
+ map_row[0] << 18 |
+ map_col[10] << 10 |
+ map_col[9] << 2;
+ regs->dec[5] = map_col[8] << 26 |
+ map_col[7] << 18 |
+ map_col[6] << 10 |
+ map_col[5] << 2;
+ regs->dec[6] = map_col[4] << 26 |
+ map_col[3] << 18 |
+ map_col[2] << 10 |
+ map_col[1] << 2;
+ regs->dec[7] = map_col[0] << 26 |
+ map_ba[1] << 18 |
+ map_ba[0] << 10 |
+ map_cid[1] << 2;
+ regs->dec[8] = map_cid[1] << 26 |
+ map_cs[1] << 18 |
+ map_cs[0] << 10 |
+ map_bg[1] << 2;
+ regs->dec[9] = map_bg[0] << 26 |
+ 1;
+ for (i = 0; i < 10; i++) {
+ debug("dec[%d] = 0x%x\n", i, regs->dec[i]);
+ }
+#endif
+}
+static unsigned int skip_caslat(unsigned int tckmin_ps,
+ unsigned int taamin_ps,
+ unsigned int mclk_ps,
+ unsigned int package_3ds)
+{
+ int i, j, k;
+ struct cas {
+ const unsigned int tckmin_ps;
+ const unsigned int caslat[4];
+ };
+ struct speed {
+ const struct cas *cl;
+ const unsigned int taamin_ps[4];
+ };
+ const struct cas cl_3200[] = {
+ {625, {0xa00000, 0xb00000, 0xf000000,} },
+ {750, { 0x20000, 0x60000, 0xe00000,} },
+ {833, { 0x8000, 0x18000, 0x38000,} },
+ {937, { 0x4000, 0x4000, 0xc000,} },
+ {1071, { 0x1000, 0x1000, 0x3000,} },
+ {1250, { 0x400, 0x400, 0xc00,} },
+ {1500, { 0, 0x600, 0x200,} },
+ };
+ const struct cas cl_2933[] = {
+ {682, { 0, 0x80000, 0x180000, 0x380000} },
+ {750, { 0x20000, 0x60000, 0x60000, 0xe0000} },
+ {833, { 0x8000, 0x18000, 0x18000, 0x38000} },
+ {937, { 0x4000, 0x4000, 0x4000, 0xc000} },
+ {1071, { 0x1000, 0x1000, 0x1000, 0x3000} },
+ {1250, { 0x400, 0x400, 0x400, 0xc00} },
+ {1500, { 0, 0x200, 0x200, 0x200} },
+ };
+ const struct cas cl_2666[] = {
+ {750, { 0, 0x20000, 0x60000, 0xe0000} },
+ {833, { 0x8000, 0x18000, 0x18000, 0x38000} },
+ {937, { 0x4000, 0x4000, 0x4000, 0xc000} },
+ {1071, { 0x1000, 0x1000, 0x1000, 0x3000} },
+ {1250, { 0x400, 0x400, 0x400, 0xc00} },
+ {1500, { 0, 0, 0x200, 0x200} },
+ };
+ const struct cas cl_2400[] = {
+ {833, { 0, 0x8000, 0x18000, 0x38000} },
+ {937, { 0xc000, 0x4000, 0x4000, 0xc000} },
+ {1071, { 0x3000, 0x1000, 0x1000, 0x3000} },
+ {1250, { 0xc00, 0x400, 0x400, 0xc00} },
+ {1500, { 0, 0x400, 0x200, 0x200} },
+ };
+ const struct cas cl_2133[] = {
+ {937, { 0, 0x4000, 0xc000,} },
+ {1071, { 0x2000, 0, 0x2000,} },
+ {1250, { 0x800, 0, 0x800,} },
+ {1500, { 0, 0x400, 0x200,} },
+ };
+ const struct cas cl_1866[] = {
+ {1071, { 0, 0x1000, 0x3000,} },
+ {1250, { 0xc00, 0x400, 0xc00,} },
+ {1500, { 0, 0x400, 0x200,} },
+ };
+ const struct cas cl_1600[] = {
+ {1250, { 0, 0x400, 0xc00,} },
+ {1500, { 0, 0x400, 0x200,} },
+ };
+ const struct speed bin_0[] = {
+ {cl_3200, {12500, 13750, 15000,} },
+ {cl_2933, {12960, 13640, 13750, 15000,} },
+ {cl_2666, {12750, 13500, 13750, 15000,} },
+ {cl_2400, {12500, 13320, 13750, 15000,} },
+ {cl_2133, {13130, 13500, 15000,} },
+ {cl_1866, {12850, 13500, 15000,} },
+ {cl_1600, {12500, 13500, 15000,} }
+ };
+ const struct cas cl_3200_3ds[] = {
+ {625, { 0xa000000, 0xb000000, 0xf000000,} },
+ {750, { 0xaa00000, 0xab00000, 0xef00000,} },
+ {833, { 0xaac0000, 0xaac0000, 0xebc0000,} },
+ {937, { 0xaab0000, 0xaab0000, 0xeaf0000,} },
+ {1071, { 0xaaa4000, 0xaaac000, 0xeaec000,} },
+ {1250, { 0xaaa0000, 0xaaa2000, 0xeaeb000,} },
+ };
+ const struct cas cl_2666_3ds[] = {
+ {750, { 0xa00000, 0xb00000, 0xf00000,} },
+ {833, { 0xac0000, 0xac0000, 0xbc0000,} },
+ {937, { 0xab0000, 0xab0000, 0xaf0000,} },
+ {1071, { 0xaa4000, 0xaac000, 0xaac000,} },
+ {1250, { 0xaa0000, 0xaaa000, 0xaaa000,} },
+ };
+ const struct cas cl_2400_3ds[] = {
+ {833, { 0xe00000, 0xe40000, 0xec0000, 0xb00000} },
+ {937, { 0xe00000, 0xe00000, 0xea0000, 0xae0000} },
+ {1071, { 0xe00000, 0xe04000, 0xeac000, 0xaec000} },
+ {1250, { 0xe00000, 0xe00000, 0xeaa000, 0xae2000} },
+ };
+ const struct cas cl_2133_3ds[] = {
+ {937, { 0x90000, 0xb0000, 0xf0000,} },
+ {1071, { 0x84000, 0xac000, 0xec000,} },
+ {1250, { 0x80000, 0xa2000, 0xe2000,} },
+ };
+ const struct cas cl_1866_3ds[] = {
+ {1071, { 0, 0x4000, 0xc000,} },
+ {1250, { 0, 0x1000, 0x3000,} },
+ };
+ const struct cas cl_1600_3ds[] = {
+ {1250, { 0, 0x1000, 0x3000,} },
+ };
+ const struct speed bin_3ds[] = {
+ {cl_3200_3ds, {15000, 16250, 17140,} },
+ {cl_2666_3ds, {15000, 16500, 17140,} },
+ {cl_2400_3ds, {15000, 15830, 16670, 17140} },
+ {cl_2133_3ds, {15950, 16880, 17140,} },
+ {cl_1866_3ds, {15000, 16070, 17140,} },
+ {cl_1600_3ds, {15000, 16250, 17500,} },
+ };
+ const struct speed *bin;
+ int size;
+ unsigned int taamin_max, tck_max;
+
+ if (taamin_ps > ((package_3ds != 0) ? 21500 : 18000)) {
+ ERROR("taamin_ps %u invalid\n", taamin_ps);
+ return 0;
+ }
+ if (package_3ds != 0) {
+ bin = bin_3ds;
+ size = ARRAY_SIZE(bin_3ds);
+ taamin_max = 1250;
+ tck_max = 1500;
+ } else {
+ bin = bin_0;
+ size = ARRAY_SIZE(bin_0);
+ taamin_max = 1500;
+ tck_max = 1600;
+ }
+ if (mclk_ps < 625 || mclk_ps > tck_max) {
+ ERROR("mclk %u invalid\n", mclk_ps);
+ return 0;
+ }
+
+ for (i = 0; i < size; i++) {
+ if (bin[i].cl[0].tckmin_ps >= tckmin_ps) {
+ break;
+ }
+ }
+ if (i >= size) {
+ ERROR("speed bin not found\n");
+ return 0;
+ }
+ if (bin[i].cl[0].tckmin_ps > tckmin_ps && i > 0) {
+ i--;
+ }
+
+ for (j = 0; j < 4; j++) {
+ if ((bin[i].taamin_ps[j] == 0) ||
+ bin[i].taamin_ps[j] >= taamin_ps) {
+ break;
+ }
+ }
+
+ if (j >= 4) {
+ ERROR("taamin_ps out of range.\n");
+ return 0;
+ }
+
+ if ((bin[i].taamin_ps[j] == 0) ||
+ (bin[i].taamin_ps[j] > taamin_ps && j > 0)) {
+ j--;
+ }
+
+ for (k = 0; bin[i].cl[k].tckmin_ps < mclk_ps &&
+ bin[i].cl[k].tckmin_ps < taamin_max; k++)
+ ;
+ if (bin[i].cl[k].tckmin_ps > mclk_ps && k > 0) {
+ k--;
+ }
+
+ debug("Skip CL mask for this speed 0x%x\n", bin[i].cl[k].caslat[j]);
+
+ return bin[i].cl[k].caslat[j];
+}
+
+int compute_ddrc(const unsigned long clk,
+ const struct memctl_opt *popts,
+ const struct ddr_conf *conf,
+ struct ddr_cfg_regs *regs,
+ const struct dimm_params *pdimm,
+ unsigned int ip_rev)
+{
+ unsigned int cas_latency;
+ unsigned int caslat_skip;
+ unsigned int additive_latency;
+ const unsigned int mclk_ps = get_memory_clk_ps(clk);
+ int i;
+
+ zeromem(regs, sizeof(struct ddr_cfg_regs));
+
+ if (mclk_ps < pdimm->tckmin_x_ps) {
+ ERROR("DDR Clk: MCLK cycle is %u ps.\n", mclk_ps);
+ ERROR("DDR Clk is faster than DIMM can support.\n");
+ }
+
+ /* calculate cas latency, override first */
+ cas_latency = (popts->caslat_override != 0) ?
+ popts->caslat_override_value :
+ (pdimm->taa_ps + mclk_ps - 1) / mclk_ps;
+
+ /* skip unsupported caslat based on speed bin */
+ caslat_skip = skip_caslat(pdimm->tckmin_x_ps,
+ pdimm->taa_ps,
+ mclk_ps,
+ pdimm->package_3ds);
+ debug("Skip caslat 0x%x\n", caslat_skip);
+
+ /* Check if DIMM supports the cas latency */
+ i = 24;
+ while (((pdimm->caslat_x & ~caslat_skip & (1 << cas_latency)) == 0) &&
+ (i-- > 0)) {
+ cas_latency++;
+ }
+
+ if (i <= 0) {
+ ERROR("Failed to find a proper cas latency\n");
+ return -EINVAL;
+ }
+ /* Verify cas latency does not exceed 18ns for DDR4 */
+ if (cas_latency * mclk_ps > 18000) {
+ ERROR("cas latency is too large %d\n", cas_latency);
+ return -EINVAL;
+ }
+
+ additive_latency = (popts->addt_lat_override != 0) ?
+ popts->addt_lat_override_value : 0;
+
+ cal_ddr_csn_bnds(regs, popts, conf, pdimm);
+ cal_ddr_sdram_cfg(clk, regs, popts, pdimm, ip_rev);
+ cal_ddr_sdram_rcw(clk, regs, popts, pdimm);
+ cal_timing_cfg(clk, regs, popts, pdimm, conf, cas_latency,
+ additive_latency);
+ cal_ddr_dq_mapping(regs, pdimm);
+
+ if (ip_rev >= 0x50500) {
+ cal_ddr_addr_dec(regs);
+ }
+
+ cal_ddr_sdram_mode(clk, regs, popts, conf, pdimm, cas_latency,
+ additive_latency, ip_rev);
+ cal_ddr_eor(regs, popts);
+ cal_ddr_data_init(regs);
+ cal_ddr_sdram_interval(clk, regs, popts, pdimm);
+ cal_ddr_zq_cntl(regs);
+ cal_ddr_sr_cntr(regs, popts);
+
+ return 0;
+}
diff --git a/drivers/nxp/ddr/nxp-ddr/utility.c b/drivers/nxp/ddr/nxp-ddr/utility.c
new file mode 100644
index 0000000..d33ad77
--- /dev/null
+++ b/drivers/nxp/ddr/nxp-ddr/utility.c
@@ -0,0 +1,275 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <errno.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <common/debug.h>
+#include <ddr.h>
+#include <immap.h>
+#include <lib/mmio.h>
+
+#define UL_5POW12 244140625UL
+#define ULL_2E12 2000000000000ULL
+#define UL_2POW13 (1UL << 13)
+#define ULL_8FS 0xFFFFFFFFULL
+
+#define do_div(n, base) ({ \
+ unsigned int __base = (base); \
+ unsigned int __rem; \
+ __rem = ((unsigned long long)(n)) % __base; \
+ (n) = ((unsigned long long)(n)) / __base; \
+ __rem; \
+})
+
+#define CCN_HN_F_SAM_NODEID_MASK 0x7f
+#ifdef NXP_HAS_CCN504
+#define CCN_HN_F_SAM_NODEID_DDR0 0x4
+#define CCN_HN_F_SAM_NODEID_DDR1 0xe
+#elif defined(NXP_HAS_CCN508)
+#define CCN_HN_F_SAM_NODEID_DDR0 0x8
+#define CCN_HN_F_SAM_NODEID_DDR1 0x18
+#endif
+
+unsigned long get_ddr_freq(struct sysinfo *sys, int ctrl_num)
+{
+ if (sys->freq_ddr_pll0 == 0) {
+ get_clocks(sys);
+ }
+
+ switch (ctrl_num) {
+ case 0:
+ return sys->freq_ddr_pll0;
+ case 1:
+ return sys->freq_ddr_pll0;
+ case 2:
+ return sys->freq_ddr_pll1;
+ }
+
+ return 0;
+}
+
+unsigned int get_memory_clk_ps(const unsigned long data_rate)
+{
+ unsigned int result;
+ /* Round to nearest 10ps, being careful about 64-bit multiply/divide */
+ unsigned long long rem, mclk_ps = ULL_2E12;
+
+ /* Now perform the big divide, the result fits in 32-bits */
+ rem = do_div(mclk_ps, data_rate);
+ result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
+
+ return result;
+}
+
+unsigned int picos_to_mclk(unsigned long data_rate, unsigned int picos)
+{
+ unsigned long long clks, clks_rem;
+
+ /* Short circuit for zero picos */
+ if ((picos == 0U) || (data_rate == 0UL)) {
+ return 0U;
+ }
+
+ /* First multiply the time by the data rate (32x32 => 64) */
+ clks = picos * (unsigned long long)data_rate;
+ /*
+ * Now divide by 5^12 and track the 32-bit remainder, then divide
+ * by 2*(2^12) using shifts (and updating the remainder).
+ */
+ clks_rem = do_div(clks, UL_5POW12);
+ clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12;
+ clks >>= 13U;
+
+ /* If we had a remainder greater than the 1ps error, then round up */
+ if (clks_rem > data_rate) {
+ clks++;
+ }
+
+ /* Clamp to the maximum representable value */
+ if (clks > ULL_8FS) {
+ clks = ULL_8FS;
+ }
+ return (unsigned int) clks;
+}
+
+/* valid_spd_mask has been checked by parse_spd */
+int disable_unused_ddrc(struct ddr_info *priv,
+ int valid_spd_mask, uintptr_t nxp_ccn_hn_f0_addr)
+{
+#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
+ void *hnf_sam_ctrl = (void *)(nxp_ccn_hn_f0_addr + CCN_HN_F_SAM_CTL);
+ uint32_t val, nodeid;
+#ifdef NXP_HAS_CCN504
+ uint32_t num_hnf_nodes = 4U;
+#else
+ uint32_t num_hnf_nodes = 8U;
+#endif
+ int disable_ddrc = 0;
+ int i;
+
+ if (priv->num_ctlrs < 2) {
+ debug("%s: nothing to do.\n", __func__);
+ }
+
+ switch (priv->dimm_on_ctlr) {
+ case 1:
+ disable_ddrc = ((valid_spd_mask &0x2) == 0) ? 2 : 0;
+ disable_ddrc = ((valid_spd_mask &0x1) == 0) ? 1 : disable_ddrc;
+ break;
+ case 2:
+ disable_ddrc = ((valid_spd_mask &0x4) == 0) ? 2 : 0;
+ disable_ddrc = ((valid_spd_mask &0x1) == 0) ? 1 : disable_ddrc;
+ break;
+ default:
+ ERROR("Invalid number of DIMMs %d\n", priv->dimm_on_ctlr);
+ return -EINVAL;
+ }
+
+ if (disable_ddrc != 0) {
+ debug("valid_spd_mask = 0x%x\n", valid_spd_mask);
+ }
+
+ switch (disable_ddrc) {
+ case 1:
+ priv->num_ctlrs = 1;
+ priv->spd_addr = &priv->spd_addr[priv->dimm_on_ctlr];
+ priv->ddr[0] = priv->ddr[1];
+ priv->ddr[1] = NULL;
+ priv->phy[0] = priv->phy[0];
+ priv->phy[1] = NULL;
+ debug("Disable first DDR controller\n");
+ break;
+ case 2:
+ priv->num_ctlrs = 1;
+ priv->ddr[1] = NULL;
+ priv->phy[1] = NULL;
+ debug("Disable second DDR controller\n");
+ /* fallthrough */
+ case 0:
+ break;
+ default:
+ ERROR("Program error.\n");
+ return -EINVAL;
+ }
+
+ if (disable_ddrc == 0) {
+ debug("Both controllers in use.\n");
+ return 0;
+ }
+
+ for (i = 0; i < num_hnf_nodes; i++) {
+ val = mmio_read_64((uintptr_t)hnf_sam_ctrl);
+ nodeid = disable_ddrc == 1 ? CCN_HN_F_SAM_NODEID_DDR1 :
+ (disable_ddrc == 2 ? CCN_HN_F_SAM_NODEID_DDR0 :
+ (i < 4 ? CCN_HN_F_SAM_NODEID_DDR0
+ : CCN_HN_F_SAM_NODEID_DDR1));
+ if (nodeid != (val & CCN_HN_F_SAM_NODEID_MASK)) {
+ debug("Setting HN-F node %d\n", i);
+ debug("nodeid = 0x%x\n", nodeid);
+ val &= ~CCN_HN_F_SAM_NODEID_MASK;
+ val |= nodeid;
+ mmio_write_64((uintptr_t)hnf_sam_ctrl, val);
+ }
+ hnf_sam_ctrl += CCN_HN_F_REGION_SIZE;
+ }
+#endif
+ return 0;
+}
+
+unsigned int get_ddrc_version(const struct ccsr_ddr *ddr)
+{
+ unsigned int ver;
+
+ ver = (ddr_in32(&ddr->ip_rev1) & 0xFFFF) << 8U;
+ ver |= (ddr_in32(&ddr->ip_rev2) & 0xFF00) >> 8U;
+
+ return ver;
+}
+
+void print_ddr_info(struct ccsr_ddr *ddr)
+{
+ unsigned int cs0_config = ddr_in32(&ddr->csn_cfg[0]);
+ unsigned int sdram_cfg = ddr_in32(&ddr->sdram_cfg);
+ int cas_lat;
+
+ if ((sdram_cfg & SDRAM_CFG_MEM_EN) == 0U) {
+ printf(" (DDR not enabled)\n");
+ return;
+ }
+
+ printf("DDR");
+ switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
+ SDRAM_CFG_SDRAM_TYPE_SHIFT) {
+ case SDRAM_TYPE_DDR4:
+ printf("4");
+ break;
+ default:
+ printf("?");
+ break;
+ }
+
+ switch (sdram_cfg & SDRAM_CFG_DBW_MASK) {
+ case SDRAM_CFG_32_BW:
+ printf(", 32-bit");
+ break;
+ case SDRAM_CFG_16_BW:
+ printf(", 16-bit");
+ break;
+ case SDRAM_CFG_8_BW:
+ printf(", 8-bit");
+ break;
+ default:
+ printf(", 64-bit");
+ break;
+ }
+
+ /* Calculate CAS latency based on timing cfg values */
+ cas_lat = ((ddr_in32(&ddr->timing_cfg_1) >> 16) & 0xf);
+ cas_lat += 2; /* for DDRC newer than 4.4 */
+ cas_lat += ((ddr_in32(&ddr->timing_cfg_3) >> 12) & 3) << 4;
+ printf(", CL=%d", cas_lat >> 1);
+ if ((cas_lat & 0x1) != 0) {
+ printf(".5");
+ }
+
+ if ((sdram_cfg & SDRAM_CFG_ECC_EN) != 0) {
+ printf(", ECC on");
+ } else {
+ printf(", ECC off");
+ }
+
+ if ((cs0_config & 0x20000000) != 0) {
+ printf(", ");
+ switch ((cs0_config >> 24) & 0xf) {
+ case DDR_256B_INTLV:
+ printf("256B");
+ break;
+ default:
+ printf("invalid");
+ break;
+ }
+ }
+
+ if (((sdram_cfg >> 8) & 0x7f) != 0) {
+ printf(", ");
+ switch (sdram_cfg >> 8 & 0x7f) {
+ case DDR_BA_INTLV_CS0123:
+ printf("CS0+CS1+CS2+CS3");
+ break;
+ case DDR_BA_INTLV_CS01:
+ printf("CS0+CS1");
+ break;
+ default:
+ printf("invalid");
+ break;
+ }
+ }
+ printf("\n");
+}
diff --git a/drivers/nxp/ddr/phy-gen1/phy.c b/drivers/nxp/ddr/phy-gen1/phy.c
new file mode 100644
index 0000000..4b66d38
--- /dev/null
+++ b/drivers/nxp/ddr/phy-gen1/phy.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <common/debug.h>
+#include <ddr.h>
+
+static void cal_ddr_sdram_clk_cntl(struct ddr_cfg_regs *regs,
+ const struct memctl_opt *popts)
+{
+ const unsigned int clk_adj = popts->clk_adj;
+ const unsigned int ss_en = 0U;
+
+ regs->clk_cntl = ((ss_en & U(0x1)) << 31U) |
+ ((clk_adj & U(0x1F)) << 22U);
+ debug("clk_cntl = 0x%x\n", regs->clk_cntl);
+}
+
+static void cal_ddr_cdr(struct ddr_cfg_regs *regs,
+ const struct memctl_opt *popts)
+{
+ regs->cdr[0] = popts->ddr_cdr1;
+ regs->cdr[1] = popts->ddr_cdr2;
+ debug("cdr[0] = 0x%x\n", regs->cdr[0]);
+ debug("cdr[1] = 0x%x\n", regs->cdr[1]);
+}
+
+static void cal_ddr_wrlvl_cntl(struct ddr_cfg_regs *regs,
+ const struct memctl_opt *popts)
+{
+ const unsigned int wrlvl_en = 1U; /* enabled */
+ const unsigned int wrlvl_mrd = U(0x6); /* > 40nCK */
+ const unsigned int wrlvl_odten = U(0x7); /* 128 */
+ const unsigned int wrlvl_dqsen = U(0x5); /* > 25nCK */
+ const unsigned int wrlvl_wlr = U(0x6); /* > tWLO + 6 */
+ const unsigned int wrlvl_smpl = popts->wrlvl_override ?
+ popts->wrlvl_sample : U(0xf);
+ const unsigned int wrlvl_start = popts->wrlvl_start;
+
+ regs->wrlvl_cntl[0] = ((wrlvl_en & U(0x1)) << 31U) |
+ ((wrlvl_mrd & U(0x7)) << 24U) |
+ ((wrlvl_odten & U(0x7)) << 20U) |
+ ((wrlvl_dqsen & U(0x7)) << 16U) |
+ ((wrlvl_smpl & U(0xf)) << 12U) |
+ ((wrlvl_wlr & U(0x7)) << 8U) |
+ ((wrlvl_start & U(0x1F)) << 0U);
+ regs->wrlvl_cntl[1] = popts->wrlvl_ctl_2;
+ regs->wrlvl_cntl[2] = popts->wrlvl_ctl_3;
+ debug("wrlvl_cntl[0] = 0x%x\n", regs->wrlvl_cntl[0]);
+ debug("wrlvl_cntl[1] = 0x%x\n", regs->wrlvl_cntl[1]);
+ debug("wrlvl_cntl[2] = 0x%x\n", regs->wrlvl_cntl[2]);
+
+}
+
+static void cal_ddr_dbg(struct ddr_cfg_regs *regs,
+ const struct memctl_opt *popts)
+{
+ if (popts->cswl_override != 0) {
+ regs->debug[18] = popts->cswl_override;
+ }
+
+#ifdef CONFIG_SYS_FSL_DDR_EMU
+ /* disable DDR training for emulator */
+ regs->debug[2] = U(0x00000400);
+ regs->debug[4] = U(0xff800800);
+ regs->debug[5] = U(0x08000800);
+ regs->debug[6] = U(0x08000800);
+ regs->debug[7] = U(0x08000800);
+ regs->debug[8] = U(0x08000800);
+#endif
+ if (popts->cpo_sample != 0U) {
+ regs->debug[28] = popts->cpo_sample;
+ debug("debug[28] = 0x%x\n", regs->debug[28]);
+ }
+}
+
+int compute_ddr_phy(struct ddr_info *priv)
+{
+ const struct memctl_opt *popts = &priv->opt;
+ struct ddr_cfg_regs *regs = &priv->ddr_reg;
+
+ cal_ddr_sdram_clk_cntl(regs, popts);
+ cal_ddr_cdr(regs, popts);
+ cal_ddr_wrlvl_cntl(regs, popts);
+ cal_ddr_dbg(regs, popts);
+
+ return 0;
+}
diff --git a/drivers/nxp/ddr/phy-gen2/csr.h b/drivers/nxp/ddr/phy-gen2/csr.h
new file mode 100644
index 0000000..ee7b4d8
--- /dev/null
+++ b/drivers/nxp/ddr/phy-gen2/csr.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright 2021 NXP
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef CSR_H
+#define CSR_H
+
+#define t_anib 0
+#define t_dbyte 0x10000
+#define t_master 0x20000
+#define t_acsm 0x40000
+#define t_initeng 0x90000
+#define t_drtub 0xc0000
+#define t_apbonly 0xd0000
+#define csr_dbyte_misc_mode_addr 0x00
+#define csr_micro_cont_mux_sel_addr 0x00
+#define csr_uct_shadow_regs 0x04
+#define csr_cal_uclk_info_addr 0x08
+#define csr_seq0bdly0_addr 0x0b
+#define csr_seq0bdly1_addr 0x0c
+#define csr_seq0bdly2_addr 0x0d
+#define csr_seq0bdly3_addr 0x0e
+#define csr_seq0bdisable_flag0_addr 0x0c
+#define csr_seq0bdisable_flag1_addr 0x0d
+#define csr_seq0bdisable_flag2_addr 0x0e
+#define csr_seq0bdisable_flag3_addr 0x0f
+#define csr_seq0bdisable_flag4_addr 0x10
+#define csr_seq0bdisable_flag5_addr 0x11
+#define csr_seq0bdisable_flag6_addr 0x12
+#define csr_seq0bdisable_flag7_addr 0x13
+#define csr_dfi_mode_addr 0x18
+#define csr_tristate_mode_ca_addr 0x19
+#define csr_dfiphyupd_addr 0x21
+#define csr_dqs_preamble_control_addr 0x24
+#define csr_master_x4config_addr 0x25
+#define csr_enable_cs_multicast_addr 0x27
+#define csr_acx4_anib_dis_addr 0x2c
+#define csr_dmipin_present_addr 0x2d
+#define csr_ard_ptr_init_val_addr 0x2e
+#define csr_dct_write_prot 0x31
+#define csr_uct_write_only_shadow 0x32
+#define csr_uct_write_prot 0x33
+#define csr_uct_dat_write_only_shadow 0x34
+#define csr_dbyte_dll_mode_cntrl_addr 0x3a
+#define csr_atx_impedance_addr 0x43
+#define csr_dq_dqs_rcv_cntrl_addr 0x43
+#define csr_cal_offsets_addr 0x45
+#define csr_tx_impedance_ctrl1_addr 0x49
+#define csr_dq_dqs_rcv_cntrl1_addr 0x4a
+#define csr_tx_odt_drv_stren_addr 0x4d
+#define csr_cal_drv_str0_addr 0x50
+#define csr_atx_slew_rate_addr 0x55
+#define csr_proc_odt_time_ctl_addr 0x56
+#define csr_mem_alert_control_addr 0x5b
+#define csr_mem_alert_control2_addr 0x5c
+#define csr_tx_slew_rate_addr 0x5f
+#define csr_mem_reset_l_addr 0x60
+#define csr_dfi_camode_addr 0x75
+#define csr_dll_gain_ctl_addr 0x7c
+#define csr_dll_lockparam_addr 0x7d
+#define csr_ucclk_hclk_enables_addr 0x80
+#define csr_acsm_playback0x0_addr 0x80
+#define csr_acsm_playback1x0_addr 0x81
+#define csr_cal_rate_addr 0x88
+#define csr_cal_zap_addr 0x89
+#define csr_cal_misc2_addr 0x98
+#define csr_micro_reset_addr 0x99
+#define csr_dfi_rd_data_cs_dest_map_addr 0xb0
+#define csr_vref_in_global_addr 0xb2
+#define csr_dfi_wr_data_cs_dest_map_addr 0xb4
+#define csr_pll_pwr_dn_addr 0xc3
+#define csr_pll_ctrl2_addr 0xc5
+#define csr_pll_ctrl1_addr 0xc7
+#define csr_pll_test_mode_addr 0xca
+#define csr_pll_ctrl4_addr 0xcc
+#define csr_dfi_freq_xlat0_addr 0xf0
+#define csr_acsm_ctrl0_addr 0xf0
+#define csr_dfi_freq_ratio_addr 0xfa
+#define csr_acsm_ctrl13_addr 0xfd
+#define csr_tx_pre_drv_mode_lsb 8
+#define csr_tx_pre_n_lsb 4
+#define csr_tx_pre_p_lsb 0
+#define csr_atx_pre_drv_mode_lsb 8
+#define csr_atx_pre_n_lsb 4
+#define csr_atx_pre_p_lsb 0
+#define csr_wdqsextension_lsb 8
+#define csr_lp4sttc_pre_bridge_rx_en_lsb 7
+#define csr_lp4postamble_ext_lsb 6
+#define csr_lp4tgl_two_tck_tx_dqs_pre_lsb 5
+#define csr_position_dfe_init_lsb 2
+#define csr_two_tck_tx_dqs_pre_lsb 1
+#define csr_two_tck_rx_dqs_pre_lsb 0
+#define csr_dll_rx_preamble_mode_lsb 1
+#define csr_odtstren_n_lsb 6
+#define csr_drv_stren_fsdq_n_lsb 6
+#define csr_drv_stren_fsdq_p_lsb 0
+#define csr_adrv_stren_n_lsb 5
+#define csr_adrv_stren_p_lsb 0
+#define csr_cal_drv_str_pu50_lsb 4
+#define csr_cal_once_lsb 5
+#define csr_cal_interval_lsb 0
+#define csr_cal_run_lsb 4
+#define csr_global_vref_in_dac_lsb 3
+#define csr_gain_curr_adj_lsb 7
+#define csr_major_mode_dbyte_lsb 4
+#define csr_dfe_ctrl_lsb 2
+#define csr_ext_vref_range_lsb 1
+#define csr_sel_analog_vref_lsb 0
+#define csr_malertsync_bypass_lsb 0
+#define csr_ck_dis_val_lsb 2
+#define csr_ddr2tmode_lsb 1
+#define csr_dis_dyn_adr_tri_lsb 0
+#define csr_dbyte_disable_lsb 2
+#define csr_power_down_rcvr_lsb 0
+#define csr_power_down_rcvr_dqs_lsb 9
+#define csr_rx_pad_standby_en_lsb 10
+#define csr_rx_pad_standby_en_mask 0x400
+#define csr_x4tg_lsb 0
+#define csr_reset_to_micro_mask 0x8
+#define csr_protect_mem_reset_mask 0x2
+#define csr_stall_to_micro_mask 0x1
+#define uct_write_prot_shadow_mask 0x1
+#define csr_acsm_par_mode_mask 0x4000
+#define csr_acsm_cke_enb_lsb 0
+#define csr_dfiphyupd_threshold_lsb 8
+#define csr_dfiphyupd_threshold_msb 11
+#define csr_dfiphyupd_threshold_mask 0xf00
+#define csr_dfi_rd_destm0_lsb 0
+#define csr_dfi_rd_destm1_lsb 2
+#define csr_dfi_rd_destm2_lsb 4
+#define csr_dfi_rd_destm3_lsb 6
+#define csr_dfi_wr_destm0_lsb 0
+#define csr_dfi_wr_destm1_lsb 2
+#define csr_dfi_wr_destm2_lsb 4
+#define csr_dfi_wr_destm3_lsb 6
+#define csr_acsm_2t_mode_mask 0x40
+#define csr_cal_misc2_err_dis 13
+#define csr_cal_offset_pdc_lsb 6
+#define csr_cal_offset_pdc_msb 9
+#define csr_cal_offset_pdc_mask 0xe0
+#define csr_cal_drv_pdth_mask 0x3c0
+
+
+struct impedance_mapping {
+ int ohm;
+ int code;
+};
+
+#endif
diff --git a/drivers/nxp/ddr/phy-gen2/ddr4fw.h b/drivers/nxp/ddr/phy-gen2/ddr4fw.h
new file mode 100644
index 0000000..f17f2e7
--- /dev/null
+++ b/drivers/nxp/ddr/phy-gen2/ddr4fw.h
@@ -0,0 +1,2897 @@
+/*
+ * Copyright 2021 NXP
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DDR4FW
+#define DDR4FW
+
+#define PHY_GEN2_MAX_IMAGE_SIZE 32768
+#define PHY_GEN2_IMEM_ADDR 0x50000
+#define PHY_GEN2_DMEM_ADDR 0x54000
+
+struct ddr4u1d {
+ uint8_t reserved00;
+ uint8_t msg_misc;
+ uint16_t pmu_revision;
+ uint8_t pstate;
+ uint8_t pll_bypass_en;
+ uint16_t dramfreq;
+ uint8_t dfi_freq_ratio;
+ uint8_t bpznres_val;
+ uint8_t phy_odt_impedance;
+ uint8_t phy_drv_impedance;
+ uint8_t phy_vref;
+ uint8_t dram_type;
+ uint8_t disabled_dbyte;
+ uint8_t enabled_dqs;
+ uint8_t cs_present;
+ uint8_t cs_present_d0;
+ uint8_t cs_present_d1;
+ uint8_t addr_mirror;
+ uint8_t cs_test_fail;
+ uint8_t phy_cfg;
+ uint16_t sequence_ctrl;
+ uint8_t hdt_ctrl;
+ uint8_t reserved19[0x1B - 0x19];
+ uint8_t share2dvref_result;
+ uint8_t reserved1c[0x22 - 0x1c];
+ uint16_t phy_config_override;
+ uint8_t dfimrlmargin;
+ int8_t cdd_rr_3_2;
+ int8_t cdd_rr_3_1;
+ int8_t cdd_rr_3_0;
+ int8_t cdd_rr_2_3;
+ int8_t cdd_rr_2_1;
+ int8_t cdd_rr_2_0;
+ int8_t cdd_rr_1_3;
+ int8_t cdd_rr_1_2;
+ int8_t cdd_rr_1_0;
+ int8_t cdd_rr_0_3;
+ int8_t cdd_rr_0_2;
+ int8_t cdd_rr_0_1;
+ int8_t cdd_ww_3_2;
+ int8_t cdd_ww_3_1;
+ int8_t cdd_ww_3_0;
+ int8_t cdd_ww_2_3;
+ int8_t cdd_ww_2_1;
+ int8_t cdd_ww_2_0;
+ int8_t cdd_ww_1_3;
+ int8_t cdd_ww_1_2;
+ int8_t cdd_ww_1_0;
+ int8_t cdd_ww_0_3;
+ int8_t cdd_ww_0_2;
+ int8_t cdd_ww_0_1;
+ int8_t cdd_rw_3_3;
+ int8_t cdd_rw_3_2;
+ int8_t cdd_rw_3_1;
+ int8_t cdd_rw_3_0;
+ int8_t cdd_rw_2_3;
+ int8_t cdd_rw_2_2;
+ int8_t cdd_rw_2_1;
+ int8_t cdd_rw_2_0;
+ int8_t cdd_rw_1_3;
+ int8_t cdd_rw_1_2;
+ int8_t cdd_rw_1_1;
+ int8_t cdd_rw_1_0;
+ int8_t cdd_rw_0_3;
+ int8_t cdd_rw_0_2;
+ int8_t cdd_rw_0_1;
+ int8_t cdd_rw_0_0;
+ int8_t cdd_wr_3_3;
+ int8_t cdd_wr_3_2;
+ int8_t cdd_wr_3_1;
+ int8_t cdd_wr_3_0;
+ int8_t cdd_wr_2_3;
+ int8_t cdd_wr_2_2;
+ int8_t cdd_wr_2_1;
+ int8_t cdd_wr_2_0;
+ int8_t cdd_wr_1_3;
+ int8_t cdd_wr_1_2;
+ int8_t cdd_wr_1_1;
+ int8_t cdd_wr_1_0;
+ int8_t cdd_wr_0_3;
+ int8_t cdd_wr_0_2;
+ int8_t cdd_wr_0_1;
+ int8_t cdd_wr_0_0;
+ uint8_t reserved5d;
+ uint16_t mr0;
+ uint16_t mr1;
+ uint16_t mr2;
+ uint16_t mr3;
+ uint16_t mr4;
+ uint16_t mr5;
+ uint16_t mr6;
+ uint8_t x16present;
+ uint8_t cs_setup_gddec;
+ uint16_t rtt_nom_wr_park0;
+ uint16_t rtt_nom_wr_park1;
+ uint16_t rtt_nom_wr_park2;
+ uint16_t rtt_nom_wr_park3;
+ uint16_t rtt_nom_wr_park4;
+ uint16_t rtt_nom_wr_park5;
+ uint16_t rtt_nom_wr_park6;
+ uint16_t rtt_nom_wr_park7;
+ uint8_t acsm_odt_ctrl0;
+ uint8_t acsm_odt_ctrl1;
+ uint8_t acsm_odt_ctrl2;
+ uint8_t acsm_odt_ctrl3;
+ uint8_t acsm_odt_ctrl4;
+ uint8_t acsm_odt_ctrl5;
+ uint8_t acsm_odt_ctrl6;
+ uint8_t acsm_odt_ctrl7;
+ uint8_t vref_dq_r0nib0;
+ uint8_t vref_dq_r0nib1;
+ uint8_t vref_dq_r0nib2;
+ uint8_t vref_dq_r0nib3;
+ uint8_t vref_dq_r0nib4;
+ uint8_t vref_dq_r0nib5;
+ uint8_t vref_dq_r0nib6;
+ uint8_t vref_dq_r0nib7;
+ uint8_t vref_dq_r0nib8;
+ uint8_t vref_dq_r0nib9;
+ uint8_t vref_dq_r0nib10;
+ uint8_t vref_dq_r0nib11;
+ uint8_t vref_dq_r0nib12;
+ uint8_t vref_dq_r0nib13;
+ uint8_t vref_dq_r0nib14;
+ uint8_t vref_dq_r0nib15;
+ uint8_t vref_dq_r0nib16;
+ uint8_t vref_dq_r0nib17;
+ uint8_t vref_dq_r0nib18;
+ uint8_t vref_dq_r0nib19;
+ uint8_t vref_dq_r1nib0;
+ uint8_t vref_dq_r1nib1;
+ uint8_t vref_dq_r1nib2;
+ uint8_t vref_dq_r1nib3;
+ uint8_t vref_dq_r1nib4;
+ uint8_t vref_dq_r1nib5;
+ uint8_t vref_dq_r1nib6;
+ uint8_t vref_dq_r1nib7;
+ uint8_t vref_dq_r1nib8;
+ uint8_t vref_dq_r1nib9;
+ uint8_t vref_dq_r1nib10;
+ uint8_t vref_dq_r1nib11;
+ uint8_t vref_dq_r1nib12;
+ uint8_t vref_dq_r1nib13;
+ uint8_t vref_dq_r1nib14;
+ uint8_t vref_dq_r1nib15;
+ uint8_t vref_dq_r1nib16;
+ uint8_t vref_dq_r1nib17;
+ uint8_t vref_dq_r1nib18;
+ uint8_t vref_dq_r1nib19;
+ uint8_t vref_dq_r2nib0;
+ uint8_t vref_dq_r2nib1;
+ uint8_t vref_dq_r2nib2;
+ uint8_t vref_dq_r2nib3;
+ uint8_t vref_dq_r2nib4;
+ uint8_t vref_dq_r2nib5;
+ uint8_t vref_dq_r2nib6;
+ uint8_t vref_dq_r2nib7;
+ uint8_t vref_dq_r2nib8;
+ uint8_t vref_dq_r2nib9;
+ uint8_t vref_dq_r2nib10;
+ uint8_t vref_dq_r2nib11;
+ uint8_t vref_dq_r2nib12;
+ uint8_t vref_dq_r2nib13;
+ uint8_t vref_dq_r2nib14;
+ uint8_t vref_dq_r2nib15;
+ uint8_t vref_dq_r2nib16;
+ uint8_t vref_dq_r2nib17;
+ uint8_t vref_dq_r2nib18;
+ uint8_t vref_dq_r2nib19;
+ uint8_t vref_dq_r3nib0;
+ uint8_t vref_dq_r3nib1;
+ uint8_t vref_dq_r3nib2;
+ uint8_t vref_dq_r3nib3;
+ uint8_t vref_dq_r3nib4;
+ uint8_t vref_dq_r3nib5;
+ uint8_t vref_dq_r3nib6;
+ uint8_t vref_dq_r3nib7;
+ uint8_t vref_dq_r3nib8;
+ uint8_t vref_dq_r3nib9;
+ uint8_t vref_dq_r3nib10;
+ uint8_t vref_dq_r3nib11;
+ uint8_t vref_dq_r3nib12;
+ uint8_t vref_dq_r3nib13;
+ uint8_t vref_dq_r3nib14;
+ uint8_t vref_dq_r3nib15;
+ uint8_t vref_dq_r3nib16;
+ uint8_t vref_dq_r3nib17;
+ uint8_t vref_dq_r3nib18;
+ uint8_t vref_dq_r3nib19;
+ uint8_t reserved_d6[0x3f6 - 0xd6];
+ uint16_t alt_cas_l;
+ uint8_t alt_wcas_l;
+ uint8_t d4misc;
+} __packed;
+
+struct ddr4u2d {
+ uint8_t reserved00;
+ uint8_t msg_misc;
+ uint16_t pmu_revision;
+ uint8_t pstate;
+ uint8_t pll_bypass_en;
+ uint16_t dramfreq;
+ uint8_t dfi_freq_ratio;
+ uint8_t bpznres_val;
+ uint8_t phy_odt_impedance;
+ uint8_t phy_drv_impedance;
+ uint8_t phy_vref;
+ uint8_t dram_type;
+ uint8_t disabled_dbyte;
+ uint8_t enabled_dqs;
+ uint8_t cs_present;
+ uint8_t cs_present_d0;
+ uint8_t cs_present_d1;
+ uint8_t addr_mirror;
+ uint8_t cs_test_fail;
+ uint8_t phy_cfg;
+ uint16_t sequence_ctrl;
+ uint8_t hdt_ctrl;
+ uint8_t rx2d_train_opt;
+ uint8_t tx2d_train_opt;
+ uint8_t share2dvref_result;
+ uint8_t delay_weight2d;
+ uint8_t voltage_weight2d;
+ uint8_t reserved1e[0x22 - 0x1e];
+ uint16_t phy_config_override;
+ uint8_t dfimrlmargin;
+ uint8_t r0_rx_clk_dly_margin;
+ uint8_t r0_vref_dac_margin;
+ uint8_t r0_tx_dq_dly_margin;
+ uint8_t r0_device_vref_margin;
+ uint8_t reserved29[0x33 - 0x29];
+ uint8_t r1_rx_clk_dly_margin;
+ uint8_t r1_vref_dac_margin;
+ uint8_t r1_tx_dq_dly_margin;
+ uint8_t r1_device_vref_margin;
+ uint8_t reserved37[0x41 - 0x37];
+ uint8_t r2_rx_clk_dly_margin;
+ uint8_t r2_vref_dac_margin;
+ uint8_t r2_tx_dq_dly_margin;
+ uint8_t r2_device_vref_margin;
+ uint8_t reserved45[0x4f - 0x45];
+ uint8_t r3_rx_clk_dly_margin;
+ uint8_t r3_vref_dac_margin;
+ uint8_t r3_tx_dq_dly_margin;
+ uint8_t r3_device_vref_margin;
+ uint8_t reserved53[0x5e - 0x53];
+ uint16_t mr0;
+ uint16_t mr1;
+ uint16_t mr2;
+ uint16_t mr3;
+ uint16_t mr4;
+ uint16_t mr5;
+ uint16_t mr6;
+ uint8_t x16present;
+ uint8_t cs_setup_gddec;
+ uint16_t rtt_nom_wr_park0;
+ uint16_t rtt_nom_wr_park1;
+ uint16_t rtt_nom_wr_park2;
+ uint16_t rtt_nom_wr_park3;
+ uint16_t rtt_nom_wr_park4;
+ uint16_t rtt_nom_wr_park5;
+ uint16_t rtt_nom_wr_park6;
+ uint16_t rtt_nom_wr_park7;
+ uint8_t acsm_odt_ctrl0;
+ uint8_t acsm_odt_ctrl1;
+ uint8_t acsm_odt_ctrl2;
+ uint8_t acsm_odt_ctrl3;
+ uint8_t acsm_odt_ctrl4;
+ uint8_t acsm_odt_ctrl5;
+ uint8_t acsm_odt_ctrl6;
+ uint8_t acsm_odt_ctrl7;
+ uint8_t vref_dq_r0nib0;
+ uint8_t vref_dq_r0nib1;
+ uint8_t vref_dq_r0nib2;
+ uint8_t vref_dq_r0nib3;
+ uint8_t vref_dq_r0nib4;
+ uint8_t vref_dq_r0nib5;
+ uint8_t vref_dq_r0nib6;
+ uint8_t vref_dq_r0nib7;
+ uint8_t vref_dq_r0nib8;
+ uint8_t vref_dq_r0nib9;
+ uint8_t vref_dq_r0nib10;
+ uint8_t vref_dq_r0nib11;
+ uint8_t vref_dq_r0nib12;
+ uint8_t vref_dq_r0nib13;
+ uint8_t vref_dq_r0nib14;
+ uint8_t vref_dq_r0nib15;
+ uint8_t vref_dq_r0nib16;
+ uint8_t vref_dq_r0nib17;
+ uint8_t vref_dq_r0nib18;
+ uint8_t vref_dq_r0nib19;
+ uint8_t vref_dq_r1nib0;
+ uint8_t vref_dq_r1nib1;
+ uint8_t vref_dq_r1nib2;
+ uint8_t vref_dq_r1nib3;
+ uint8_t vref_dq_r1nib4;
+ uint8_t vref_dq_r1nib5;
+ uint8_t vref_dq_r1nib6;
+ uint8_t vref_dq_r1nib7;
+ uint8_t vref_dq_r1nib8;
+ uint8_t vref_dq_r1nib9;
+ uint8_t vref_dq_r1nib10;
+ uint8_t vref_dq_r1nib11;
+ uint8_t vref_dq_r1nib12;
+ uint8_t vref_dq_r1nib13;
+ uint8_t vref_dq_r1nib14;
+ uint8_t vref_dq_r1nib15;
+ uint8_t vref_dq_r1nib16;
+ uint8_t vref_dq_r1nib17;
+ uint8_t vref_dq_r1nib18;
+ uint8_t vref_dq_r1nib19;
+ uint8_t vref_dq_r2nib0;
+ uint8_t vref_dq_r2nib1;
+ uint8_t vref_dq_r2nib2;
+ uint8_t vref_dq_r2nib3;
+ uint8_t vref_dq_r2nib4;
+ uint8_t vref_dq_r2nib5;
+ uint8_t vref_dq_r2nib6;
+ uint8_t vref_dq_r2nib7;
+ uint8_t vref_dq_r2nib8;
+ uint8_t vref_dq_r2nib9;
+ uint8_t vref_dq_r2nib10;
+ uint8_t vref_dq_r2nib11;
+ uint8_t vref_dq_r2nib12;
+ uint8_t vref_dq_r2nib13;
+ uint8_t vref_dq_r2nib14;
+ uint8_t vref_dq_r2nib15;
+ uint8_t vref_dq_r2nib16;
+ uint8_t vref_dq_r2nib17;
+ uint8_t vref_dq_r2nib18;
+ uint8_t vref_dq_r2nib19;
+ uint8_t vref_dq_r3nib0;
+ uint8_t vref_dq_r3nib1;
+ uint8_t vref_dq_r3nib2;
+ uint8_t vref_dq_r3nib3;
+ uint8_t vref_dq_r3nib4;
+ uint8_t vref_dq_r3nib5;
+ uint8_t vref_dq_r3nib6;
+ uint8_t vref_dq_r3nib7;
+ uint8_t vref_dq_r3nib8;
+ uint8_t vref_dq_r3nib9;
+ uint8_t vref_dq_r3nib10;
+ uint8_t vref_dq_r3nib11;
+ uint8_t vref_dq_r3nib12;
+ uint8_t vref_dq_r3nib13;
+ uint8_t vref_dq_r3nib14;
+ uint8_t vref_dq_r3nib15;
+ uint8_t vref_dq_r3nib16;
+ uint8_t vref_dq_r3nib17;
+ uint8_t vref_dq_r3nib18;
+ uint8_t vref_dq_r3nib19;
+ uint8_t reserved_d6[0x3f6 - 0xd6];
+ uint16_t alt_cas_l;
+ uint8_t alt_wcas_l;
+ uint8_t d4misc;
+} __packed;
+
+struct ddr4r1d {
+ uint8_t reserved00;
+ uint8_t msg_misc;
+ uint16_t pmu_revision;
+ uint8_t pstate;
+ uint8_t pll_bypass_en;
+ uint16_t dramfreq;
+ uint8_t dfi_freq_ratio;
+ uint8_t bpznres_val;
+ uint8_t phy_odt_impedance;
+ uint8_t phy_drv_impedance;
+ uint8_t phy_vref;
+ uint8_t dram_type;
+ uint8_t disabled_dbyte;
+ uint8_t enabled_dqs;
+ uint8_t cs_present;
+ uint8_t cs_present_d0;
+ uint8_t cs_present_d1;
+ uint8_t addr_mirror;
+ uint8_t cs_test_fail;
+ uint8_t phy_cfg;
+ uint16_t sequence_ctrl;
+ uint8_t hdt_ctrl;
+ uint8_t reserved19[0x22 - 0x19];
+ uint16_t phy_config_override;
+ uint8_t dfimrlmargin;
+ int8_t cdd_rr_3_2;
+ int8_t cdd_rr_3_1;
+ int8_t cdd_rr_3_0;
+ int8_t cdd_rr_2_3;
+ int8_t cdd_rr_2_1;
+ int8_t cdd_rr_2_0;
+ int8_t cdd_rr_1_3;
+ int8_t cdd_rr_1_2;
+ int8_t cdd_rr_1_0;
+ int8_t cdd_rr_0_3;
+ int8_t cdd_rr_0_2;
+ int8_t cdd_rr_0_1;
+ int8_t cdd_ww_3_2;
+ int8_t cdd_ww_3_1;
+ int8_t cdd_ww_3_0;
+ int8_t cdd_ww_2_3;
+ int8_t cdd_ww_2_1;
+ int8_t cdd_ww_2_0;
+ int8_t cdd_ww_1_3;
+ int8_t cdd_ww_1_2;
+ int8_t cdd_ww_1_0;
+ int8_t cdd_ww_0_3;
+ int8_t cdd_ww_0_2;
+ int8_t cdd_ww_0_1;
+ int8_t cdd_rw_3_3;
+ int8_t cdd_rw_3_2;
+ int8_t cdd_rw_3_1;
+ int8_t cdd_rw_3_0;
+ int8_t cdd_rw_2_3;
+ int8_t cdd_rw_2_2;
+ int8_t cdd_rw_2_1;
+ int8_t cdd_rw_2_0;
+ int8_t cdd_rw_1_3;
+ int8_t cdd_rw_1_2;
+ int8_t cdd_rw_1_1;
+ int8_t cdd_rw_1_0;
+ int8_t cdd_rw_0_3;
+ int8_t cdd_rw_0_2;
+ int8_t cdd_rw_0_1;
+ int8_t cdd_rw_0_0;
+ int8_t cdd_wr_3_3;
+ int8_t cdd_wr_3_2;
+ int8_t cdd_wr_3_1;
+ int8_t cdd_wr_3_0;
+ int8_t cdd_wr_2_3;
+ int8_t cdd_wr_2_2;
+ int8_t cdd_wr_2_1;
+ int8_t cdd_wr_2_0;
+ int8_t cdd_wr_1_3;
+ int8_t cdd_wr_1_2;
+ int8_t cdd_wr_1_1;
+ int8_t cdd_wr_1_0;
+ int8_t cdd_wr_0_3;
+ int8_t cdd_wr_0_2;
+ int8_t cdd_wr_0_1;
+ int8_t cdd_wr_0_0;
+ uint8_t reserved5d;
+ uint16_t mr0;
+ uint16_t mr1;
+ uint16_t mr2;
+ uint16_t mr3;
+ uint16_t mr4;
+ uint16_t mr5;
+ uint16_t mr6;
+ uint8_t x16present;
+ uint8_t cs_setup_gddec;
+ uint16_t rtt_nom_wr_park0;
+ uint16_t rtt_nom_wr_park1;
+ uint16_t rtt_nom_wr_park2;
+ uint16_t rtt_nom_wr_park3;
+ uint16_t rtt_nom_wr_park4;
+ uint16_t rtt_nom_wr_park5;
+ uint16_t rtt_nom_wr_park6;
+ uint16_t rtt_nom_wr_park7;
+ uint8_t acsm_odt_ctrl0;
+ uint8_t acsm_odt_ctrl1;
+ uint8_t acsm_odt_ctrl2;
+ uint8_t acsm_odt_ctrl3;
+ uint8_t acsm_odt_ctrl4;
+ uint8_t acsm_odt_ctrl5;
+ uint8_t acsm_odt_ctrl6;
+ uint8_t acsm_odt_ctrl7;
+ uint8_t vref_dq_r0nib0;
+ uint8_t vref_dq_r0nib1;
+ uint8_t vref_dq_r0nib2;
+ uint8_t vref_dq_r0nib3;
+ uint8_t vref_dq_r0nib4;
+ uint8_t vref_dq_r0nib5;
+ uint8_t vref_dq_r0nib6;
+ uint8_t vref_dq_r0nib7;
+ uint8_t vref_dq_r0nib8;
+ uint8_t vref_dq_r0nib9;
+ uint8_t vref_dq_r0nib10;
+ uint8_t vref_dq_r0nib11;
+ uint8_t vref_dq_r0nib12;
+ uint8_t vref_dq_r0nib13;
+ uint8_t vref_dq_r0nib14;
+ uint8_t vref_dq_r0nib15;
+ uint8_t vref_dq_r0nib16;
+ uint8_t vref_dq_r0nib17;
+ uint8_t vref_dq_r0nib18;
+ uint8_t vref_dq_r0nib19;
+ uint8_t vref_dq_r1nib0;
+ uint8_t vref_dq_r1nib1;
+ uint8_t vref_dq_r1nib2;
+ uint8_t vref_dq_r1nib3;
+ uint8_t vref_dq_r1nib4;
+ uint8_t vref_dq_r1nib5;
+ uint8_t vref_dq_r1nib6;
+ uint8_t vref_dq_r1nib7;
+ uint8_t vref_dq_r1nib8;
+ uint8_t vref_dq_r1nib9;
+ uint8_t vref_dq_r1nib10;
+ uint8_t vref_dq_r1nib11;
+ uint8_t vref_dq_r1nib12;
+ uint8_t vref_dq_r1nib13;
+ uint8_t vref_dq_r1nib14;
+ uint8_t vref_dq_r1nib15;
+ uint8_t vref_dq_r1nib16;
+ uint8_t vref_dq_r1nib17;
+ uint8_t vref_dq_r1nib18;
+ uint8_t vref_dq_r1nib19;
+ uint8_t vref_dq_r2nib0;
+ uint8_t vref_dq_r2nib1;
+ uint8_t vref_dq_r2nib2;
+ uint8_t vref_dq_r2nib3;
+ uint8_t vref_dq_r2nib4;
+ uint8_t vref_dq_r2nib5;
+ uint8_t vref_dq_r2nib6;
+ uint8_t vref_dq_r2nib7;
+ uint8_t vref_dq_r2nib8;
+ uint8_t vref_dq_r2nib9;
+ uint8_t vref_dq_r2nib10;
+ uint8_t vref_dq_r2nib11;
+ uint8_t vref_dq_r2nib12;
+ uint8_t vref_dq_r2nib13;
+ uint8_t vref_dq_r2nib14;
+ uint8_t vref_dq_r2nib15;
+ uint8_t vref_dq_r2nib16;
+ uint8_t vref_dq_r2nib17;
+ uint8_t vref_dq_r2nib18;
+ uint8_t vref_dq_r2nib19;
+ uint8_t vref_dq_r3nib0;
+ uint8_t vref_dq_r3nib1;
+ uint8_t vref_dq_r3nib2;
+ uint8_t vref_dq_r3nib3;
+ uint8_t vref_dq_r3nib4;
+ uint8_t vref_dq_r3nib5;
+ uint8_t vref_dq_r3nib6;
+ uint8_t vref_dq_r3nib7;
+ uint8_t vref_dq_r3nib8;
+ uint8_t vref_dq_r3nib9;
+ uint8_t vref_dq_r3nib10;
+ uint8_t vref_dq_r3nib11;
+ uint8_t vref_dq_r3nib12;
+ uint8_t vref_dq_r3nib13;
+ uint8_t vref_dq_r3nib14;
+ uint8_t vref_dq_r3nib15;
+ uint8_t vref_dq_r3nib16;
+ uint8_t vref_dq_r3nib17;
+ uint8_t vref_dq_r3nib18;
+ uint8_t vref_dq_r3nib19;
+ uint8_t f0rc00_d0;
+ uint8_t f0rc01_d0;
+ uint8_t f0rc02_d0;
+ uint8_t f0rc03_d0;
+ uint8_t f0rc04_d0;
+ uint8_t f0rc05_d0;
+ uint8_t f0rc06_d0;
+ uint8_t f0rc07_d0;
+ uint8_t f0rc08_d0;
+ uint8_t f0rc09_d0;
+ uint8_t f0rc0a_d0;
+ uint8_t f0rc0b_d0;
+ uint8_t f0rc0c_d0;
+ uint8_t f0rc0d_d0;
+ uint8_t f0rc0e_d0;
+ uint8_t f0rc0f_d0;
+ uint8_t f0rc1x_d0;
+ uint8_t f0rc2x_d0;
+ uint8_t f0rc3x_d0;
+ uint8_t f0rc4x_d0;
+ uint8_t f0rc5x_d0;
+ uint8_t f0rc6x_d0;
+ uint8_t f0rc7x_d0;
+ uint8_t f0rc8x_d0;
+ uint8_t f0rc9x_d0;
+ uint8_t f0rcax_d0;
+ uint8_t f0rcbx_d0;
+ uint8_t f1rc00_d0;
+ uint8_t f1rc01_d0;
+ uint8_t f1rc02_d0;
+ uint8_t f1rc03_d0;
+ uint8_t f1rc04_d0;
+ uint8_t f1rc05_d0;
+ uint8_t f1rc06_d0;
+ uint8_t f1rc07_d0;
+ uint8_t f1rc08_d0;
+ uint8_t f1rc09_d0;
+ uint8_t f1rc0a_d0;
+ uint8_t f1rc0b_d0;
+ uint8_t f1rc0c_d0;
+ uint8_t f1rc0d_d0;
+ uint8_t f1rc0e_d0;
+ uint8_t f1rc0f_d0;
+ uint8_t f1rc1x_d0;
+ uint8_t f1rc2x_d0;
+ uint8_t f1rc3x_d0;
+ uint8_t f1rc4x_d0;
+ uint8_t f1rc5x_d0;
+ uint8_t f1rc6x_d0;
+ uint8_t f1rc7x_d0;
+ uint8_t f1rc8x_d0;
+ uint8_t f1rc9x_d0;
+ uint8_t f1rcax_d0;
+ uint8_t f1rcbx_d0;
+ uint8_t f0rc00_d1;
+ uint8_t f0rc01_d1;
+ uint8_t f0rc02_d1;
+ uint8_t f0rc03_d1;
+ uint8_t f0rc04_d1;
+ uint8_t f0rc05_d1;
+ uint8_t f0rc06_d1;
+ uint8_t f0rc07_d1;
+ uint8_t f0rc08_d1;
+ uint8_t f0rc09_d1;
+ uint8_t f0rc0a_d1;
+ uint8_t f0rc0b_d1;
+ uint8_t f0rc0c_d1;
+ uint8_t f0rc0d_d1;
+ uint8_t f0rc0e_d1;
+ uint8_t f0rc0f_d1;
+ uint8_t f0rc1x_d1;
+ uint8_t f0rc2x_d1;
+ uint8_t f0rc3x_d1;
+ uint8_t f0rc4x_d1;
+ uint8_t f0rc5x_d1;
+ uint8_t f0rc6x_d1;
+ uint8_t f0rc7x_d1;
+ uint8_t f0rc8x_d1;
+ uint8_t f0rc9x_d1;
+ uint8_t f0rcax_d1;
+ uint8_t f0rcbx_d1;
+ uint8_t f1rc00_d1;
+ uint8_t f1rc01_d1;
+ uint8_t f1rc02_d1;
+ uint8_t f1rc03_d1;
+ uint8_t f1rc04_d1;
+ uint8_t f1rc05_d1;
+ uint8_t f1rc06_d1;
+ uint8_t f1rc07_d1;
+ uint8_t f1rc08_d1;
+ uint8_t f1rc09_d1;
+ uint8_t f1rc0a_d1;
+ uint8_t f1rc0b_d1;
+ uint8_t f1rc0c_d1;
+ uint8_t f1rc0d_d1;
+ uint8_t f1rc0e_d1;
+ uint8_t f1rc0f_d1;
+ uint8_t f1rc1x_d1;
+ uint8_t f1rc2x_d1;
+ uint8_t f1rc3x_d1;
+ uint8_t f1rc4x_d1;
+ uint8_t f1rc5x_d1;
+ uint8_t f1rc6x_d1;
+ uint8_t f1rc7x_d1;
+ uint8_t f1rc8x_d1;
+ uint8_t f1rc9x_d1;
+ uint8_t f1rcax_d1;
+ uint8_t f1rcbx_d1;
+ uint8_t reserved142[0x3f6 - 0x142];
+ uint16_t alt_cas_l;
+ uint8_t alt_wcas_l;
+ uint8_t d4misc;
+} __packed;
+
+struct ddr4r2d {
+ uint8_t reserved00;
+ uint8_t msg_misc;
+ uint16_t pmu_revision;
+ uint8_t pstate;
+ uint8_t pll_bypass_en;
+ uint16_t dramfreq;
+ uint8_t dfi_freq_ratio;
+ uint8_t bpznres_val;
+ uint8_t phy_odt_impedance;
+ uint8_t phy_drv_impedance;
+ uint8_t phy_vref;
+ uint8_t dram_type;
+ uint8_t disabled_dbyte;
+ uint8_t enabled_dqs;
+ uint8_t cs_present;
+ uint8_t cs_present_d0;
+ uint8_t cs_present_d1;
+ uint8_t addr_mirror;
+ uint8_t cs_test_fail;
+ uint8_t phy_cfg;
+ uint16_t sequence_ctrl;
+ uint8_t hdt_ctrl;
+ uint8_t rx2d_train_opt;
+ uint8_t tx2d_train_opt;
+ uint8_t share2dvref_result;
+ uint8_t delay_weight2d;
+ uint8_t voltage_weight2d;
+ uint8_t reserved1e[0x22-0x1e];
+ uint16_t phy_config_override;
+ uint8_t dfimrlmargin;
+ uint8_t r0_rx_clk_dly_margin;
+ uint8_t r0_vref_dac_margin;
+ uint8_t r0_tx_dq_dly_margin;
+ uint8_t r0_device_vref_margin;
+ uint8_t reserved29[0x33-0x29];
+ uint8_t r1_rx_clk_dly_margin;
+ uint8_t r1_vref_dac_margin;
+ uint8_t r1_tx_dq_dly_margin;
+ uint8_t r1_device_vref_margin;
+ uint8_t reserved37[0x41-0x37];
+ uint8_t r2_rx_clk_dly_margin;
+ uint8_t r2_vref_dac_margin;
+ uint8_t r2_tx_dq_dly_margin;
+ uint8_t r2_device_vref_margin;
+ uint8_t reserved45[0x4f - 0x45];
+ uint8_t r3_rx_clk_dly_margin;
+ uint8_t r3_vref_dac_margin;
+ uint8_t r3_tx_dq_dly_margin;
+ uint8_t r3_device_vref_margin;
+ uint8_t reserved53[0x5e - 0x53];
+ uint16_t mr0;
+ uint16_t mr1;
+ uint16_t mr2;
+ uint16_t mr3;
+ uint16_t mr4;
+ uint16_t mr5;
+ uint16_t mr6;
+ uint8_t x16present;
+ uint8_t cs_setup_gddec;
+ uint16_t rtt_nom_wr_park0;
+ uint16_t rtt_nom_wr_park1;
+ uint16_t rtt_nom_wr_park2;
+ uint16_t rtt_nom_wr_park3;
+ uint16_t rtt_nom_wr_park4;
+ uint16_t rtt_nom_wr_park5;
+ uint16_t rtt_nom_wr_park6;
+ uint16_t rtt_nom_wr_park7;
+ uint8_t acsm_odt_ctrl0;
+ uint8_t acsm_odt_ctrl1;
+ uint8_t acsm_odt_ctrl2;
+ uint8_t acsm_odt_ctrl3;
+ uint8_t acsm_odt_ctrl4;
+ uint8_t acsm_odt_ctrl5;
+ uint8_t acsm_odt_ctrl6;
+ uint8_t acsm_odt_ctrl7;
+ uint8_t vref_dq_r0nib0;
+ uint8_t vref_dq_r0nib1;
+ uint8_t vref_dq_r0nib2;
+ uint8_t vref_dq_r0nib3;
+ uint8_t vref_dq_r0nib4;
+ uint8_t vref_dq_r0nib5;
+ uint8_t vref_dq_r0nib6;
+ uint8_t vref_dq_r0nib7;
+ uint8_t vref_dq_r0nib8;
+ uint8_t vref_dq_r0nib9;
+ uint8_t vref_dq_r0nib10;
+ uint8_t vref_dq_r0nib11;
+ uint8_t vref_dq_r0nib12;
+ uint8_t vref_dq_r0nib13;
+ uint8_t vref_dq_r0nib14;
+ uint8_t vref_dq_r0nib15;
+ uint8_t vref_dq_r0nib16;
+ uint8_t vref_dq_r0nib17;
+ uint8_t vref_dq_r0nib18;
+ uint8_t vref_dq_r0nib19;
+ uint8_t vref_dq_r1nib0;
+ uint8_t vref_dq_r1nib1;
+ uint8_t vref_dq_r1nib2;
+ uint8_t vref_dq_r1nib3;
+ uint8_t vref_dq_r1nib4;
+ uint8_t vref_dq_r1nib5;
+ uint8_t vref_dq_r1nib6;
+ uint8_t vref_dq_r1nib7;
+ uint8_t vref_dq_r1nib8;
+ uint8_t vref_dq_r1nib9;
+ uint8_t vref_dq_r1nib10;
+ uint8_t vref_dq_r1nib11;
+ uint8_t vref_dq_r1nib12;
+ uint8_t vref_dq_r1nib13;
+ uint8_t vref_dq_r1nib14;
+ uint8_t vref_dq_r1nib15;
+ uint8_t vref_dq_r1nib16;
+ uint8_t vref_dq_r1nib17;
+ uint8_t vref_dq_r1nib18;
+ uint8_t vref_dq_r1nib19;
+ uint8_t vref_dq_r2nib0;
+ uint8_t vref_dq_r2nib1;
+ uint8_t vref_dq_r2nib2;
+ uint8_t vref_dq_r2nib3;
+ uint8_t vref_dq_r2nib4;
+ uint8_t vref_dq_r2nib5;
+ uint8_t vref_dq_r2nib6;
+ uint8_t vref_dq_r2nib7;
+ uint8_t vref_dq_r2nib8;
+ uint8_t vref_dq_r2nib9;
+ uint8_t vref_dq_r2nib10;
+ uint8_t vref_dq_r2nib11;
+ uint8_t vref_dq_r2nib12;
+ uint8_t vref_dq_r2nib13;
+ uint8_t vref_dq_r2nib14;
+ uint8_t vref_dq_r2nib15;
+ uint8_t vref_dq_r2nib16;
+ uint8_t vref_dq_r2nib17;
+ uint8_t vref_dq_r2nib18;
+ uint8_t vref_dq_r2nib19;
+ uint8_t vref_dq_r3nib0;
+ uint8_t vref_dq_r3nib1;
+ uint8_t vref_dq_r3nib2;
+ uint8_t vref_dq_r3nib3;
+ uint8_t vref_dq_r3nib4;
+ uint8_t vref_dq_r3nib5;
+ uint8_t vref_dq_r3nib6;
+ uint8_t vref_dq_r3nib7;
+ uint8_t vref_dq_r3nib8;
+ uint8_t vref_dq_r3nib9;
+ uint8_t vref_dq_r3nib10;
+ uint8_t vref_dq_r3nib11;
+ uint8_t vref_dq_r3nib12;
+ uint8_t vref_dq_r3nib13;
+ uint8_t vref_dq_r3nib14;
+ uint8_t vref_dq_r3nib15;
+ uint8_t vref_dq_r3nib16;
+ uint8_t vref_dq_r3nib17;
+ uint8_t vref_dq_r3nib18;
+ uint8_t vref_dq_r3nib19;
+ uint8_t f0rc00_d0;
+ uint8_t f0rc01_d0;
+ uint8_t f0rc02_d0;
+ uint8_t f0rc03_d0;
+ uint8_t f0rc04_d0;
+ uint8_t f0rc05_d0;
+ uint8_t f0rc06_d0;
+ uint8_t f0rc07_d0;
+ uint8_t f0rc08_d0;
+ uint8_t f0rc09_d0;
+ uint8_t f0rc0a_d0;
+ uint8_t f0rc0b_d0;
+ uint8_t f0rc0c_d0;
+ uint8_t f0rc0d_d0;
+ uint8_t f0rc0e_d0;
+ uint8_t f0rc0f_d0;
+ uint8_t f0rc1x_d0;
+ uint8_t f0rc2x_d0;
+ uint8_t f0rc3x_d0;
+ uint8_t f0rc4x_d0;
+ uint8_t f0rc5x_d0;
+ uint8_t f0rc6x_d0;
+ uint8_t f0rc7x_d0;
+ uint8_t f0rc8x_d0;
+ uint8_t f0rc9x_d0;
+ uint8_t f0rcax_d0;
+ uint8_t f0rcbx_d0;
+ uint8_t f1rc00_d0;
+ uint8_t f1rc01_d0;
+ uint8_t f1rc02_d0;
+ uint8_t f1rc03_d0;
+ uint8_t f1rc04_d0;
+ uint8_t f1rc05_d0;
+ uint8_t f1rc06_d0;
+ uint8_t f1rc07_d0;
+ uint8_t f1rc08_d0;
+ uint8_t f1rc09_d0;
+ uint8_t f1rc0a_d0;
+ uint8_t f1rc0b_d0;
+ uint8_t f1rc0c_d0;
+ uint8_t f1rc0d_d0;
+ uint8_t f1rc0e_d0;
+ uint8_t f1rc0f_d0;
+ uint8_t f1rc1x_d0;
+ uint8_t f1rc2x_d0;
+ uint8_t f1rc3x_d0;
+ uint8_t f1rc4x_d0;
+ uint8_t f1rc5x_d0;
+ uint8_t f1rc6x_d0;
+ uint8_t f1rc7x_d0;
+ uint8_t f1rc8x_d0;
+ uint8_t f1rc9x_d0;
+ uint8_t f1rcax_d0;
+ uint8_t f1rcbx_d0;
+ uint8_t f0rc00_d1;
+ uint8_t f0rc01_d1;
+ uint8_t f0rc02_d1;
+ uint8_t f0rc03_d1;
+ uint8_t f0rc04_d1;
+ uint8_t f0rc05_d1;
+ uint8_t f0rc06_d1;
+ uint8_t f0rc07_d1;
+ uint8_t f0rc08_d1;
+ uint8_t f0rc09_d1;
+ uint8_t f0rc0a_d1;
+ uint8_t f0rc0b_d1;
+ uint8_t f0rc0c_d1;
+ uint8_t f0rc0d_d1;
+ uint8_t f0rc0e_d1;
+ uint8_t f0rc0f_d1;
+ uint8_t f0rc1x_d1;
+ uint8_t f0rc2x_d1;
+ uint8_t f0rc3x_d1;
+ uint8_t f0rc4x_d1;
+ uint8_t f0rc5x_d1;
+ uint8_t f0rc6x_d1;
+ uint8_t f0rc7x_d1;
+ uint8_t f0rc8x_d1;
+ uint8_t f0rc9x_d1;
+ uint8_t f0rcax_d1;
+ uint8_t f0rcbx_d1;
+ uint8_t f1rc00_d1;
+ uint8_t f1rc01_d1;
+ uint8_t f1rc02_d1;
+ uint8_t f1rc03_d1;
+ uint8_t f1rc04_d1;
+ uint8_t f1rc05_d1;
+ uint8_t f1rc06_d1;
+ uint8_t f1rc07_d1;
+ uint8_t f1rc08_d1;
+ uint8_t f1rc09_d1;
+ uint8_t f1rc0a_d1;
+ uint8_t f1rc0b_d1;
+ uint8_t f1rc0c_d1;
+ uint8_t f1rc0d_d1;
+ uint8_t f1rc0e_d1;
+ uint8_t f1rc0f_d1;
+ uint8_t f1rc1x_d1;
+ uint8_t f1rc2x_d1;
+ uint8_t f1rc3x_d1;
+ uint8_t f1rc4x_d1;
+ uint8_t f1rc5x_d1;
+ uint8_t f1rc6x_d1;
+ uint8_t f1rc7x_d1;
+ uint8_t f1rc8x_d1;
+ uint8_t f1rc9x_d1;
+ uint8_t f1rcax_d1;
+ uint8_t f1rcbx_d1;
+ uint8_t reserved142[0x3f6 - 0x142];
+ uint16_t alt_cas_l;
+ uint8_t alt_wcas_l;
+ uint8_t d4misc;
+} __packed;
+
+struct ddr4lr1d {
+ uint8_t reserved00;
+ uint8_t msg_misc;
+ uint16_t pmu_revision;
+ uint8_t pstate;
+ uint8_t pll_bypass_en;
+ uint16_t dramfreq;
+ uint8_t dfi_freq_ratio;
+ uint8_t bpznres_val;
+ uint8_t phy_odt_impedance;
+ uint8_t phy_drv_impedance;
+ uint8_t phy_vref;
+ uint8_t dram_type;
+ uint8_t disabled_dbyte;
+ uint8_t enabled_dqs;
+ uint8_t cs_present;
+ uint8_t cs_present_d0;
+ uint8_t cs_present_d1;
+ uint8_t addr_mirror;
+ uint8_t cs_test_fail;
+ uint8_t phy_cfg;
+ uint16_t sequence_ctrl;
+ uint8_t hdt_ctrl;
+ uint8_t reserved19[0x22 - 0x19];
+ uint16_t phy_config_override;
+ uint8_t dfimrlmargin;
+ int8_t cdd_rr_3_2;
+ int8_t cdd_rr_3_1;
+ int8_t cdd_rr_3_0;
+ int8_t cdd_rr_2_3;
+ int8_t cdd_rr_2_1;
+ int8_t cdd_rr_2_0;
+ int8_t cdd_rr_1_3;
+ int8_t cdd_rr_1_2;
+ int8_t cdd_rr_1_0;
+ int8_t cdd_rr_0_3;
+ int8_t cdd_rr_0_2;
+ int8_t cdd_rr_0_1;
+ int8_t cdd_ww_3_2;
+ int8_t cdd_ww_3_1;
+ int8_t cdd_ww_3_0;
+ int8_t cdd_ww_2_3;
+ int8_t cdd_ww_2_1;
+ int8_t cdd_ww_2_0;
+ int8_t cdd_ww_1_3;
+ int8_t cdd_ww_1_2;
+ int8_t cdd_ww_1_0;
+ int8_t cdd_ww_0_3;
+ int8_t cdd_ww_0_2;
+ int8_t cdd_ww_0_1;
+ int8_t cdd_rw_3_3;
+ int8_t cdd_rw_3_2;
+ int8_t cdd_rw_3_1;
+ int8_t cdd_rw_3_0;
+ int8_t cdd_rw_2_3;
+ int8_t cdd_rw_2_2;
+ int8_t cdd_rw_2_1;
+ int8_t cdd_rw_2_0;
+ int8_t cdd_rw_1_3;
+ int8_t cdd_rw_1_2;
+ int8_t cdd_rw_1_1;
+ int8_t cdd_rw_1_0;
+ int8_t cdd_rw_0_3;
+ int8_t cdd_rw_0_2;
+ int8_t cdd_rw_0_1;
+ int8_t cdd_rw_0_0;
+ int8_t cdd_wr_3_3;
+ int8_t cdd_wr_3_2;
+ int8_t cdd_wr_3_1;
+ int8_t cdd_wr_3_0;
+ int8_t cdd_wr_2_3;
+ int8_t cdd_wr_2_2;
+ int8_t cdd_wr_2_1;
+ int8_t cdd_wr_2_0;
+ int8_t cdd_wr_1_3;
+ int8_t cdd_wr_1_2;
+ int8_t cdd_wr_1_1;
+ int8_t cdd_wr_1_0;
+ int8_t cdd_wr_0_3;
+ int8_t cdd_wr_0_2;
+ int8_t cdd_wr_0_1;
+ int8_t cdd_wr_0_0;
+ uint8_t reserved5d;
+ uint16_t mr0;
+ uint16_t mr1;
+ uint16_t mr2;
+ uint16_t mr3;
+ uint16_t mr4;
+ uint16_t mr5;
+ uint16_t mr6;
+ uint8_t x16present;
+ uint8_t cs_setup_gddec;
+ uint16_t rtt_nom_wr_park0;
+ uint16_t rtt_nom_wr_park1;
+ uint16_t rtt_nom_wr_park2;
+ uint16_t rtt_nom_wr_park3;
+ uint16_t rtt_nom_wr_park4;
+ uint16_t rtt_nom_wr_park5;
+ uint16_t rtt_nom_wr_park6;
+ uint16_t rtt_nom_wr_park7;
+ uint8_t acsm_odt_ctrl0;
+ uint8_t acsm_odt_ctrl1;
+ uint8_t acsm_odt_ctrl2;
+ uint8_t acsm_odt_ctrl3;
+ uint8_t acsm_odt_ctrl4;
+ uint8_t acsm_odt_ctrl5;
+ uint8_t acsm_odt_ctrl6;
+ uint8_t acsm_odt_ctrl7;
+ uint8_t vref_dq_r0nib0;
+ uint8_t vref_dq_r0nib1;
+ uint8_t vref_dq_r0nib2;
+ uint8_t vref_dq_r0nib3;
+ uint8_t vref_dq_r0nib4;
+ uint8_t vref_dq_r0nib5;
+ uint8_t vref_dq_r0nib6;
+ uint8_t vref_dq_r0nib7;
+ uint8_t vref_dq_r0nib8;
+ uint8_t vref_dq_r0nib9;
+ uint8_t vref_dq_r0nib10;
+ uint8_t vref_dq_r0nib11;
+ uint8_t vref_dq_r0nib12;
+ uint8_t vref_dq_r0nib13;
+ uint8_t vref_dq_r0nib14;
+ uint8_t vref_dq_r0nib15;
+ uint8_t vref_dq_r0nib16;
+ uint8_t vref_dq_r0nib17;
+ uint8_t vref_dq_r0nib18;
+ uint8_t vref_dq_r0nib19;
+ uint8_t vref_dq_r1nib0;
+ uint8_t vref_dq_r1nib1;
+ uint8_t vref_dq_r1nib2;
+ uint8_t vref_dq_r1nib3;
+ uint8_t vref_dq_r1nib4;
+ uint8_t vref_dq_r1nib5;
+ uint8_t vref_dq_r1nib6;
+ uint8_t vref_dq_r1nib7;
+ uint8_t vref_dq_r1nib8;
+ uint8_t vref_dq_r1nib9;
+ uint8_t vref_dq_r1nib10;
+ uint8_t vref_dq_r1nib11;
+ uint8_t vref_dq_r1nib12;
+ uint8_t vref_dq_r1nib13;
+ uint8_t vref_dq_r1nib14;
+ uint8_t vref_dq_r1nib15;
+ uint8_t vref_dq_r1nib16;
+ uint8_t vref_dq_r1nib17;
+ uint8_t vref_dq_r1nib18;
+ uint8_t vref_dq_r1nib19;
+ uint8_t vref_dq_r2nib0;
+ uint8_t vref_dq_r2nib1;
+ uint8_t vref_dq_r2nib2;
+ uint8_t vref_dq_r2nib3;
+ uint8_t vref_dq_r2nib4;
+ uint8_t vref_dq_r2nib5;
+ uint8_t vref_dq_r2nib6;
+ uint8_t vref_dq_r2nib7;
+ uint8_t vref_dq_r2nib8;
+ uint8_t vref_dq_r2nib9;
+ uint8_t vref_dq_r2nib10;
+ uint8_t vref_dq_r2nib11;
+ uint8_t vref_dq_r2nib12;
+ uint8_t vref_dq_r2nib13;
+ uint8_t vref_dq_r2nib14;
+ uint8_t vref_dq_r2nib15;
+ uint8_t vref_dq_r2nib16;
+ uint8_t vref_dq_r2nib17;
+ uint8_t vref_dq_r2nib18;
+ uint8_t vref_dq_r2nib19;
+ uint8_t vref_dq_r3nib0;
+ uint8_t vref_dq_r3nib1;
+ uint8_t vref_dq_r3nib2;
+ uint8_t vref_dq_r3nib3;
+ uint8_t vref_dq_r3nib4;
+ uint8_t vref_dq_r3nib5;
+ uint8_t vref_dq_r3nib6;
+ uint8_t vref_dq_r3nib7;
+ uint8_t vref_dq_r3nib8;
+ uint8_t vref_dq_r3nib9;
+ uint8_t vref_dq_r3nib10;
+ uint8_t vref_dq_r3nib11;
+ uint8_t vref_dq_r3nib12;
+ uint8_t vref_dq_r3nib13;
+ uint8_t vref_dq_r3nib14;
+ uint8_t vref_dq_r3nib15;
+ uint8_t vref_dq_r3nib16;
+ uint8_t vref_dq_r3nib17;
+ uint8_t vref_dq_r3nib18;
+ uint8_t vref_dq_r3nib19;
+ uint8_t f0rc00_d0;
+ uint8_t f0rc01_d0;
+ uint8_t f0rc02_d0;
+ uint8_t f0rc03_d0;
+ uint8_t f0rc04_d0;
+ uint8_t f0rc05_d0;
+ uint8_t f0rc06_d0;
+ uint8_t f0rc07_d0;
+ uint8_t f0rc08_d0;
+ uint8_t f0rc09_d0;
+ uint8_t f0rc0a_d0;
+ uint8_t f0rc0b_d0;
+ uint8_t f0rc0c_d0;
+ uint8_t f0rc0d_d0;
+ uint8_t f0rc0e_d0;
+ uint8_t f0rc0f_d0;
+ uint8_t f0rc1x_d0;
+ uint8_t f0rc2x_d0;
+ uint8_t f0rc3x_d0;
+ uint8_t f0rc4x_d0;
+ uint8_t f0rc5x_d0;
+ uint8_t f0rc6x_d0;
+ uint8_t f0rc7x_d0;
+ uint8_t f0rc8x_d0;
+ uint8_t f0rc9x_d0;
+ uint8_t f0rcax_d0;
+ uint8_t f0rcbx_d0;
+ uint8_t f1rc00_d0;
+ uint8_t f1rc01_d0;
+ uint8_t f1rc02_d0;
+ uint8_t f1rc03_d0;
+ uint8_t f1rc04_d0;
+ uint8_t f1rc05_d0;
+ uint8_t f1rc06_d0;
+ uint8_t f1rc07_d0;
+ uint8_t f1rc08_d0;
+ uint8_t f1rc09_d0;
+ uint8_t f1rc0a_d0;
+ uint8_t f1rc0b_d0;
+ uint8_t f1rc0c_d0;
+ uint8_t f1rc0d_d0;
+ uint8_t f1rc0e_d0;
+ uint8_t f1rc0f_d0;
+ uint8_t f1rc1x_d0;
+ uint8_t f1rc2x_d0;
+ uint8_t f1rc3x_d0;
+ uint8_t f1rc4x_d0;
+ uint8_t f1rc5x_d0;
+ uint8_t f1rc6x_d0;
+ uint8_t f1rc7x_d0;
+ uint8_t f1rc8x_d0;
+ uint8_t f1rc9x_d0;
+ uint8_t f1rcax_d0;
+ uint8_t f1rcbx_d0;
+ uint8_t f0rc00_d1;
+ uint8_t f0rc01_d1;
+ uint8_t f0rc02_d1;
+ uint8_t f0rc03_d1;
+ uint8_t f0rc04_d1;
+ uint8_t f0rc05_d1;
+ uint8_t f0rc06_d1;
+ uint8_t f0rc07_d1;
+ uint8_t f0rc08_d1;
+ uint8_t f0rc09_d1;
+ uint8_t f0rc0a_d1;
+ uint8_t f0rc0b_d1;
+ uint8_t f0rc0c_d1;
+ uint8_t f0rc0d_d1;
+ uint8_t f0rc0e_d1;
+ uint8_t f0rc0f_d1;
+ uint8_t f0rc1x_d1;
+ uint8_t f0rc2x_d1;
+ uint8_t f0rc3x_d1;
+ uint8_t f0rc4x_d1;
+ uint8_t f0rc5x_d1;
+ uint8_t f0rc6x_d1;
+ uint8_t f0rc7x_d1;
+ uint8_t f0rc8x_d1;
+ uint8_t f0rc9x_d1;
+ uint8_t f0rcax_d1;
+ uint8_t f0rcbx_d1;
+ uint8_t f1rc00_d1;
+ uint8_t f1rc01_d1;
+ uint8_t f1rc02_d1;
+ uint8_t f1rc03_d1;
+ uint8_t f1rc04_d1;
+ uint8_t f1rc05_d1;
+ uint8_t f1rc06_d1;
+ uint8_t f1rc07_d1;
+ uint8_t f1rc08_d1;
+ uint8_t f1rc09_d1;
+ uint8_t f1rc0a_d1;
+ uint8_t f1rc0b_d1;
+ uint8_t f1rc0c_d1;
+ uint8_t f1rc0d_d1;
+ uint8_t f1rc0e_d1;
+ uint8_t f1rc0f_d1;
+ uint8_t f1rc1x_d1;
+ uint8_t f1rc2x_d1;
+ uint8_t f1rc3x_d1;
+ uint8_t f1rc4x_d1;
+ uint8_t f1rc5x_d1;
+ uint8_t f1rc6x_d1;
+ uint8_t f1rc7x_d1;
+ uint8_t f1rc8x_d1;
+ uint8_t f1rc9x_d1;
+ uint8_t f1rcax_d1;
+ uint8_t f1rcbx_d1;
+ uint8_t bc00_d0;
+ uint8_t bc01_d0;
+ uint8_t bc02_d0;
+ uint8_t bc03_d0;
+ uint8_t bc04_d0;
+ uint8_t bc05_d0;
+ uint8_t bc06_d0;
+ uint8_t bc07_d0;
+ uint8_t bc08_d0;
+ uint8_t bc09_d0;
+ uint8_t bc0a_d0;
+ uint8_t bc0b_d0;
+ uint8_t bc0c_d0;
+ uint8_t bc0d_d0;
+ uint8_t bc0e_d0;
+ uint8_t f0bc6x_d0;
+ uint8_t f0bccx_d0;
+ uint8_t f0bcdx_d0;
+ uint8_t f0bcex_d0;
+ uint8_t f0bcfx_d0;
+ uint8_t f1bccx_d0;
+ uint8_t f1bcdx_d0;
+ uint8_t f1bcex_d0;
+ uint8_t f1bcfx_d0;
+ uint8_t f0bc2x_b0_d0;
+ uint8_t f0bc3x_b0_d0;
+ uint8_t f0bc4x_b0_d0;
+ uint8_t f0bc5x_b0_d0;
+ uint8_t f0bc8x_b0_d0;
+ uint8_t f0bc9x_b0_d0;
+ uint8_t f0bcax_b0_d0;
+ uint8_t f0bcbx_b0_d0;
+ uint8_t f1bc2x_b0_d0;
+ uint8_t f1bc3x_b0_d0;
+ uint8_t f1bc4x_b0_d0;
+ uint8_t f1bc5x_b0_d0;
+ uint8_t f1bc8x_b0_d0;
+ uint8_t f1bc9x_b0_d0;
+ uint8_t f1bcax_b0_d0;
+ uint8_t f1bcbx_b0_d0;
+ uint8_t f2bc2x_b0_d0;
+ uint8_t f2bc3x_b0_d0;
+ uint8_t f2bc4x_b0_d0;
+ uint8_t f2bc5x_b0_d0;
+ uint8_t f2bc8x_b0_d0;
+ uint8_t f2bc9x_b0_d0;
+ uint8_t f2bcax_b0_d0;
+ uint8_t f2bcbx_b0_d0;
+ uint8_t f3bc2x_b0_d0;
+ uint8_t f3bc3x_b0_d0;
+ uint8_t f3bc4x_b0_d0;
+ uint8_t f3bc5x_b0_d0;
+ uint8_t f3bc8x_b0_d0;
+ uint8_t f3bc9x_b0_d0;
+ uint8_t f3bcax_b0_d0;
+ uint8_t f3bcbx_b0_d0;
+ uint8_t f0bc2x_b1_d0;
+ uint8_t f0bc3x_b1_d0;
+ uint8_t f0bc4x_b1_d0;
+ uint8_t f0bc5x_b1_d0;
+ uint8_t f0bc8x_b1_d0;
+ uint8_t f0bc9x_b1_d0;
+ uint8_t f0bcax_b1_d0;
+ uint8_t f0bcbx_b1_d0;
+ uint8_t f1bc2x_b1_d0;
+ uint8_t f1bc3x_b1_d0;
+ uint8_t f1bc4x_b1_d0;
+ uint8_t f1bc5x_b1_d0;
+ uint8_t f1bc8x_b1_d0;
+ uint8_t f1bc9x_b1_d0;
+ uint8_t f1bcax_b1_d0;
+ uint8_t f1bcbx_b1_d0;
+ uint8_t f2bc2x_b1_d0;
+ uint8_t f2bc3x_b1_d0;
+ uint8_t f2bc4x_b1_d0;
+ uint8_t f2bc5x_b1_d0;
+ uint8_t f2bc8x_b1_d0;
+ uint8_t f2bc9x_b1_d0;
+ uint8_t f2bcax_b1_d0;
+ uint8_t f2bcbx_b1_d0;
+ uint8_t f3bc2x_b1_d0;
+ uint8_t f3bc3x_b1_d0;
+ uint8_t f3bc4x_b1_d0;
+ uint8_t f3bc5x_b1_d0;
+ uint8_t f3bc8x_b1_d0;
+ uint8_t f3bc9x_b1_d0;
+ uint8_t f3bcax_b1_d0;
+ uint8_t f3bcbx_b1_d0;
+ uint8_t f0bc2x_b2_d0;
+ uint8_t f0bc3x_b2_d0;
+ uint8_t f0bc4x_b2_d0;
+ uint8_t f0bc5x_b2_d0;
+ uint8_t f0bc8x_b2_d0;
+ uint8_t f0bc9x_b2_d0;
+ uint8_t f0bcax_b2_d0;
+ uint8_t f0bcbx_b2_d0;
+ uint8_t f1bc2x_b2_d0;
+ uint8_t f1bc3x_b2_d0;
+ uint8_t f1bc4x_b2_d0;
+ uint8_t f1bc5x_b2_d0;
+ uint8_t f1bc8x_b2_d0;
+ uint8_t f1bc9x_b2_d0;
+ uint8_t f1bcax_b2_d0;
+ uint8_t f1bcbx_b2_d0;
+ uint8_t f2bc2x_b2_d0;
+ uint8_t f2bc3x_b2_d0;
+ uint8_t f2bc4x_b2_d0;
+ uint8_t f2bc5x_b2_d0;
+ uint8_t f2bc8x_b2_d0;
+ uint8_t f2bc9x_b2_d0;
+ uint8_t f2bcax_b2_d0;
+ uint8_t f2bcbx_b2_d0;
+ uint8_t f3bc2x_b2_d0;
+ uint8_t f3bc3x_b2_d0;
+ uint8_t f3bc4x_b2_d0;
+ uint8_t f3bc5x_b2_d0;
+ uint8_t f3bc8x_b2_d0;
+ uint8_t f3bc9x_b2_d0;
+ uint8_t f3bcax_b2_d0;
+ uint8_t f3bcbx_b2_d0;
+ uint8_t f0bc2x_b3_d0;
+ uint8_t f0bc3x_b3_d0;
+ uint8_t f0bc4x_b3_d0;
+ uint8_t f0bc5x_b3_d0;
+ uint8_t f0bc8x_b3_d0;
+ uint8_t f0bc9x_b3_d0;
+ uint8_t f0bcax_b3_d0;
+ uint8_t f0bcbx_b3_d0;
+ uint8_t f1bc2x_b3_d0;
+ uint8_t f1bc3x_b3_d0;
+ uint8_t f1bc4x_b3_d0;
+ uint8_t f1bc5x_b3_d0;
+ uint8_t f1bc8x_b3_d0;
+ uint8_t f1bc9x_b3_d0;
+ uint8_t f1bcax_b3_d0;
+ uint8_t f1bcbx_b3_d0;
+ uint8_t f2bc2x_b3_d0;
+ uint8_t f2bc3x_b3_d0;
+ uint8_t f2bc4x_b3_d0;
+ uint8_t f2bc5x_b3_d0;
+ uint8_t f2bc8x_b3_d0;
+ uint8_t f2bc9x_b3_d0;
+ uint8_t f2bcax_b3_d0;
+ uint8_t f2bcbx_b3_d0;
+ uint8_t f3bc2x_b3_d0;
+ uint8_t f3bc3x_b3_d0;
+ uint8_t f3bc4x_b3_d0;
+ uint8_t f3bc5x_b3_d0;
+ uint8_t f3bc8x_b3_d0;
+ uint8_t f3bc9x_b3_d0;
+ uint8_t f3bcax_b3_d0;
+ uint8_t f3bcbx_b3_d0;
+ uint8_t f0bc2x_b4_d0;
+ uint8_t f0bc3x_b4_d0;
+ uint8_t f0bc4x_b4_d0;
+ uint8_t f0bc5x_b4_d0;
+ uint8_t f0bc8x_b4_d0;
+ uint8_t f0bc9x_b4_d0;
+ uint8_t f0bcax_b4_d0;
+ uint8_t f0bcbx_b4_d0;
+ uint8_t f1bc2x_b4_d0;
+ uint8_t f1bc3x_b4_d0;
+ uint8_t f1bc4x_b4_d0;
+ uint8_t f1bc5x_b4_d0;
+ uint8_t f1bc8x_b4_d0;
+ uint8_t f1bc9x_b4_d0;
+ uint8_t f1bcax_b4_d0;
+ uint8_t f1bcbx_b4_d0;
+ uint8_t f2bc2x_b4_d0;
+ uint8_t f2bc3x_b4_d0;
+ uint8_t f2bc4x_b4_d0;
+ uint8_t f2bc5x_b4_d0;
+ uint8_t f2bc8x_b4_d0;
+ uint8_t f2bc9x_b4_d0;
+ uint8_t f2bcax_b4_d0;
+ uint8_t f2bcbx_b4_d0;
+ uint8_t f3bc2x_b4_d0;
+ uint8_t f3bc3x_b4_d0;
+ uint8_t f3bc4x_b4_d0;
+ uint8_t f3bc5x_b4_d0;
+ uint8_t f3bc8x_b4_d0;
+ uint8_t f3bc9x_b4_d0;
+ uint8_t f3bcax_b4_d0;
+ uint8_t f3bcbx_b4_d0;
+ uint8_t f0bc2x_b5_d0;
+ uint8_t f0bc3x_b5_d0;
+ uint8_t f0bc4x_b5_d0;
+ uint8_t f0bc5x_b5_d0;
+ uint8_t f0bc8x_b5_d0;
+ uint8_t f0bc9x_b5_d0;
+ uint8_t f0bcax_b5_d0;
+ uint8_t f0bcbx_b5_d0;
+ uint8_t f1bc2x_b5_d0;
+ uint8_t f1bc3x_b5_d0;
+ uint8_t f1bc4x_b5_d0;
+ uint8_t f1bc5x_b5_d0;
+ uint8_t f1bc8x_b5_d0;
+ uint8_t f1bc9x_b5_d0;
+ uint8_t f1bcax_b5_d0;
+ uint8_t f1bcbx_b5_d0;
+ uint8_t f2bc2x_b5_d0;
+ uint8_t f2bc3x_b5_d0;
+ uint8_t f2bc4x_b5_d0;
+ uint8_t f2bc5x_b5_d0;
+ uint8_t f2bc8x_b5_d0;
+ uint8_t f2bc9x_b5_d0;
+ uint8_t f2bcax_b5_d0;
+ uint8_t f2bcbx_b5_d0;
+ uint8_t f3bc2x_b5_d0;
+ uint8_t f3bc3x_b5_d0;
+ uint8_t f3bc4x_b5_d0;
+ uint8_t f3bc5x_b5_d0;
+ uint8_t f3bc8x_b5_d0;
+ uint8_t f3bc9x_b5_d0;
+ uint8_t f3bcax_b5_d0;
+ uint8_t f3bcbx_b5_d0;
+ uint8_t f0bc2x_b6_d0;
+ uint8_t f0bc3x_b6_d0;
+ uint8_t f0bc4x_b6_d0;
+ uint8_t f0bc5x_b6_d0;
+ uint8_t f0bc8x_b6_d0;
+ uint8_t f0bc9x_b6_d0;
+ uint8_t f0bcax_b6_d0;
+ uint8_t f0bcbx_b6_d0;
+ uint8_t f1bc2x_b6_d0;
+ uint8_t f1bc3x_b6_d0;
+ uint8_t f1bc4x_b6_d0;
+ uint8_t f1bc5x_b6_d0;
+ uint8_t f1bc8x_b6_d0;
+ uint8_t f1bc9x_b6_d0;
+ uint8_t f1bcax_b6_d0;
+ uint8_t f1bcbx_b6_d0;
+ uint8_t f2bc2x_b6_d0;
+ uint8_t f2bc3x_b6_d0;
+ uint8_t f2bc4x_b6_d0;
+ uint8_t f2bc5x_b6_d0;
+ uint8_t f2bc8x_b6_d0;
+ uint8_t f2bc9x_b6_d0;
+ uint8_t f2bcax_b6_d0;
+ uint8_t f2bcbx_b6_d0;
+ uint8_t f3bc2x_b6_d0;
+ uint8_t f3bc3x_b6_d0;
+ uint8_t f3bc4x_b6_d0;
+ uint8_t f3bc5x_b6_d0;
+ uint8_t f3bc8x_b6_d0;
+ uint8_t f3bc9x_b6_d0;
+ uint8_t f3bcax_b6_d0;
+ uint8_t f3bcbx_b6_d0;
+ uint8_t f0bc2x_b7_d0;
+ uint8_t f0bc3x_b7_d0;
+ uint8_t f0bc4x_b7_d0;
+ uint8_t f0bc5x_b7_d0;
+ uint8_t f0bc8x_b7_d0;
+ uint8_t f0bc9x_b7_d0;
+ uint8_t f0bcax_b7_d0;
+ uint8_t f0bcbx_b7_d0;
+ uint8_t f1bc2x_b7_d0;
+ uint8_t f1bc3x_b7_d0;
+ uint8_t f1bc4x_b7_d0;
+ uint8_t f1bc5x_b7_d0;
+ uint8_t f1bc8x_b7_d0;
+ uint8_t f1bc9x_b7_d0;
+ uint8_t f1bcax_b7_d0;
+ uint8_t f1bcbx_b7_d0;
+ uint8_t f2bc2x_b7_d0;
+ uint8_t f2bc3x_b7_d0;
+ uint8_t f2bc4x_b7_d0;
+ uint8_t f2bc5x_b7_d0;
+ uint8_t f2bc8x_b7_d0;
+ uint8_t f2bc9x_b7_d0;
+ uint8_t f2bcax_b7_d0;
+ uint8_t f2bcbx_b7_d0;
+ uint8_t f3bc2x_b7_d0;
+ uint8_t f3bc3x_b7_d0;
+ uint8_t f3bc4x_b7_d0;
+ uint8_t f3bc5x_b7_d0;
+ uint8_t f3bc8x_b7_d0;
+ uint8_t f3bc9x_b7_d0;
+ uint8_t f3bcax_b7_d0;
+ uint8_t f3bcbx_b7_d0;
+ uint8_t f0bc2x_b8_d0;
+ uint8_t f0bc3x_b8_d0;
+ uint8_t f0bc4x_b8_d0;
+ uint8_t f0bc5x_b8_d0;
+ uint8_t f0bc8x_b8_d0;
+ uint8_t f0bc9x_b8_d0;
+ uint8_t f0bcax_b8_d0;
+ uint8_t f0bcbx_b8_d0;
+ uint8_t f1bc2x_b8_d0;
+ uint8_t f1bc3x_b8_d0;
+ uint8_t f1bc4x_b8_d0;
+ uint8_t f1bc5x_b8_d0;
+ uint8_t f1bc8x_b8_d0;
+ uint8_t f1bc9x_b8_d0;
+ uint8_t f1bcax_b8_d0;
+ uint8_t f1bcbx_b8_d0;
+ uint8_t f2bc2x_b8_d0;
+ uint8_t f2bc3x_b8_d0;
+ uint8_t f2bc4x_b8_d0;
+ uint8_t f2bc5x_b8_d0;
+ uint8_t f2bc8x_b8_d0;
+ uint8_t f2bc9x_b8_d0;
+ uint8_t f2bcax_b8_d0;
+ uint8_t f2bcbx_b8_d0;
+ uint8_t f3bc2x_b8_d0;
+ uint8_t f3bc3x_b8_d0;
+ uint8_t f3bc4x_b8_d0;
+ uint8_t f3bc5x_b8_d0;
+ uint8_t f3bc8x_b8_d0;
+ uint8_t f3bc9x_b8_d0;
+ uint8_t f3bcax_b8_d0;
+ uint8_t f3bcbx_b8_d0;
+ uint8_t f5bc5x_d0;
+ uint8_t f5bc6x_d0;
+ uint8_t f4bc8x_d0;
+ uint8_t f4bc9x_d0;
+ uint8_t f4bcax_d0;
+ uint8_t f4bcbx_d0;
+ uint8_t f4bccx_d0;
+ uint8_t f4bcdx_d0;
+ uint8_t f4bcex_d0;
+ uint8_t f4bcfx_d0;
+ uint8_t f5bc8x_d0;
+ uint8_t f5bc9x_d0;
+ uint8_t f5bcax_d0;
+ uint8_t f5bcbx_d0;
+ uint8_t f5bccx_d0;
+ uint8_t f5bcdx_d0;
+ uint8_t f5bcex_d0;
+ uint8_t f5bcfx_d0;
+ uint8_t f6bc8x_d0;
+ uint8_t f6bc9x_d0;
+ uint8_t f6bcax_d0;
+ uint8_t f6bcbx_d0;
+ uint8_t f6bccx_d0;
+ uint8_t f6bcdx_d0;
+ uint8_t f6bcex_d0;
+ uint8_t f6bcfx_d0;
+ uint8_t f7bc8x_d0;
+ uint8_t f7bc9x_d0;
+ uint8_t f7bcax_d0;
+ uint8_t f7bcbx_d0;
+ uint8_t f7bccx_d0;
+ uint8_t f7bcdx_d0;
+ uint8_t f7bcex_d0;
+ uint8_t f7bcfx_d0;
+ uint8_t bc00_d1;
+ uint8_t bc01_d1;
+ uint8_t bc02_d1;
+ uint8_t bc03_d1;
+ uint8_t bc04_d1;
+ uint8_t bc05_d1;
+ uint8_t bc06_d1;
+ uint8_t bc07_d1;
+ uint8_t bc08_d1;
+ uint8_t bc09_d1;
+ uint8_t bc0a_d1;
+ uint8_t bc0b_d1;
+ uint8_t bc0c_d1;
+ uint8_t bc0d_d1;
+ uint8_t bc0e_d1;
+ uint8_t f0bc6x_d1;
+ uint8_t f0bccx_d1;
+ uint8_t f0bcdx_d1;
+ uint8_t f0bcex_d1;
+ uint8_t f0bcfx_d1;
+ uint8_t f1bccx_d1;
+ uint8_t f1bcdx_d1;
+ uint8_t f1bcex_d1;
+ uint8_t f1bcfx_d1;
+ uint8_t f0bc2x_b0_d1;
+ uint8_t f0bc3x_b0_d1;
+ uint8_t f0bc4x_b0_d1;
+ uint8_t f0bc5x_b0_d1;
+ uint8_t f0bc8x_b0_d1;
+ uint8_t f0bc9x_b0_d1;
+ uint8_t f0bcax_b0_d1;
+ uint8_t f0bcbx_b0_d1;
+ uint8_t f1bc2x_b0_d1;
+ uint8_t f1bc3x_b0_d1;
+ uint8_t f1bc4x_b0_d1;
+ uint8_t f1bc5x_b0_d1;
+ uint8_t f1bc8x_b0_d1;
+ uint8_t f1bc9x_b0_d1;
+ uint8_t f1bcax_b0_d1;
+ uint8_t f1bcbx_b0_d1;
+ uint8_t f2bc2x_b0_d1;
+ uint8_t f2bc3x_b0_d1;
+ uint8_t f2bc4x_b0_d1;
+ uint8_t f2bc5x_b0_d1;
+ uint8_t f2bc8x_b0_d1;
+ uint8_t f2bc9x_b0_d1;
+ uint8_t f2bcax_b0_d1;
+ uint8_t f2bcbx_b0_d1;
+ uint8_t f3bc2x_b0_d1;
+ uint8_t f3bc3x_b0_d1;
+ uint8_t f3bc4x_b0_d1;
+ uint8_t f3bc5x_b0_d1;
+ uint8_t f3bc8x_b0_d1;
+ uint8_t f3bc9x_b0_d1;
+ uint8_t f3bcax_b0_d1;
+ uint8_t f3bcbx_b0_d1;
+ uint8_t f0bc2x_b1_d1;
+ uint8_t f0bc3x_b1_d1;
+ uint8_t f0bc4x_b1_d1;
+ uint8_t f0bc5x_b1_d1;
+ uint8_t f0bc8x_b1_d1;
+ uint8_t f0bc9x_b1_d1;
+ uint8_t f0bcax_b1_d1;
+ uint8_t f0bcbx_b1_d1;
+ uint8_t f1bc2x_b1_d1;
+ uint8_t f1bc3x_b1_d1;
+ uint8_t f1bc4x_b1_d1;
+ uint8_t f1bc5x_b1_d1;
+ uint8_t f1bc8x_b1_d1;
+ uint8_t f1bc9x_b1_d1;
+ uint8_t f1bcax_b1_d1;
+ uint8_t f1bcbx_b1_d1;
+ uint8_t f2bc2x_b1_d1;
+ uint8_t f2bc3x_b1_d1;
+ uint8_t f2bc4x_b1_d1;
+ uint8_t f2bc5x_b1_d1;
+ uint8_t f2bc8x_b1_d1;
+ uint8_t f2bc9x_b1_d1;
+ uint8_t f2bcax_b1_d1;
+ uint8_t f2bcbx_b1_d1;
+ uint8_t f3bc2x_b1_d1;
+ uint8_t f3bc3x_b1_d1;
+ uint8_t f3bc4x_b1_d1;
+ uint8_t f3bc5x_b1_d1;
+ uint8_t f3bc8x_b1_d1;
+ uint8_t f3bc9x_b1_d1;
+ uint8_t f3bcax_b1_d1;
+ uint8_t f3bcbx_b1_d1;
+ uint8_t f0bc2x_b2_d1;
+ uint8_t f0bc3x_b2_d1;
+ uint8_t f0bc4x_b2_d1;
+ uint8_t f0bc5x_b2_d1;
+ uint8_t f0bc8x_b2_d1;
+ uint8_t f0bc9x_b2_d1;
+ uint8_t f0bcax_b2_d1;
+ uint8_t f0bcbx_b2_d1;
+ uint8_t f1bc2x_b2_d1;
+ uint8_t f1bc3x_b2_d1;
+ uint8_t f1bc4x_b2_d1;
+ uint8_t f1bc5x_b2_d1;
+ uint8_t f1bc8x_b2_d1;
+ uint8_t f1bc9x_b2_d1;
+ uint8_t f1bcax_b2_d1;
+ uint8_t f1bcbx_b2_d1;
+ uint8_t f2bc2x_b2_d1;
+ uint8_t f2bc3x_b2_d1;
+ uint8_t f2bc4x_b2_d1;
+ uint8_t f2bc5x_b2_d1;
+ uint8_t f2bc8x_b2_d1;
+ uint8_t f2bc9x_b2_d1;
+ uint8_t f2bcax_b2_d1;
+ uint8_t f2bcbx_b2_d1;
+ uint8_t f3bc2x_b2_d1;
+ uint8_t f3bc3x_b2_d1;
+ uint8_t f3bc4x_b2_d1;
+ uint8_t f3bc5x_b2_d1;
+ uint8_t f3bc8x_b2_d1;
+ uint8_t f3bc9x_b2_d1;
+ uint8_t f3bcax_b2_d1;
+ uint8_t f3bcbx_b2_d1;
+ uint8_t f0bc2x_b3_d1;
+ uint8_t f0bc3x_b3_d1;
+ uint8_t f0bc4x_b3_d1;
+ uint8_t f0bc5x_b3_d1;
+ uint8_t f0bc8x_b3_d1;
+ uint8_t f0bc9x_b3_d1;
+ uint8_t f0bcax_b3_d1;
+ uint8_t f0bcbx_b3_d1;
+ uint8_t f1bc2x_b3_d1;
+ uint8_t f1bc3x_b3_d1;
+ uint8_t f1bc4x_b3_d1;
+ uint8_t f1bc5x_b3_d1;
+ uint8_t f1bc8x_b3_d1;
+ uint8_t f1bc9x_b3_d1;
+ uint8_t f1bcax_b3_d1;
+ uint8_t f1bcbx_b3_d1;
+ uint8_t f2bc2x_b3_d1;
+ uint8_t f2bc3x_b3_d1;
+ uint8_t f2bc4x_b3_d1;
+ uint8_t f2bc5x_b3_d1;
+ uint8_t f2bc8x_b3_d1;
+ uint8_t f2bc9x_b3_d1;
+ uint8_t f2bcax_b3_d1;
+ uint8_t f2bcbx_b3_d1;
+ uint8_t f3bc2x_b3_d1;
+ uint8_t f3bc3x_b3_d1;
+ uint8_t f3bc4x_b3_d1;
+ uint8_t f3bc5x_b3_d1;
+ uint8_t f3bc8x_b3_d1;
+ uint8_t f3bc9x_b3_d1;
+ uint8_t f3bcax_b3_d1;
+ uint8_t f3bcbx_b3_d1;
+ uint8_t f0bc2x_b4_d1;
+ uint8_t f0bc3x_b4_d1;
+ uint8_t f0bc4x_b4_d1;
+ uint8_t f0bc5x_b4_d1;
+ uint8_t f0bc8x_b4_d1;
+ uint8_t f0bc9x_b4_d1;
+ uint8_t f0bcax_b4_d1;
+ uint8_t f0bcbx_b4_d1;
+ uint8_t f1bc2x_b4_d1;
+ uint8_t f1bc3x_b4_d1;
+ uint8_t f1bc4x_b4_d1;
+ uint8_t f1bc5x_b4_d1;
+ uint8_t f1bc8x_b4_d1;
+ uint8_t f1bc9x_b4_d1;
+ uint8_t f1bcax_b4_d1;
+ uint8_t f1bcbx_b4_d1;
+ uint8_t f2bc2x_b4_d1;
+ uint8_t f2bc3x_b4_d1;
+ uint8_t f2bc4x_b4_d1;
+ uint8_t f2bc5x_b4_d1;
+ uint8_t f2bc8x_b4_d1;
+ uint8_t f2bc9x_b4_d1;
+ uint8_t f2bcax_b4_d1;
+ uint8_t f2bcbx_b4_d1;
+ uint8_t f3bc2x_b4_d1;
+ uint8_t f3bc3x_b4_d1;
+ uint8_t f3bc4x_b4_d1;
+ uint8_t f3bc5x_b4_d1;
+ uint8_t f3bc8x_b4_d1;
+ uint8_t f3bc9x_b4_d1;
+ uint8_t f3bcax_b4_d1;
+ uint8_t f3bcbx_b4_d1;
+ uint8_t f0bc2x_b5_d1;
+ uint8_t f0bc3x_b5_d1;
+ uint8_t f0bc4x_b5_d1;
+ uint8_t f0bc5x_b5_d1;
+ uint8_t f0bc8x_b5_d1;
+ uint8_t f0bc9x_b5_d1;
+ uint8_t f0bcax_b5_d1;
+ uint8_t f0bcbx_b5_d1;
+ uint8_t f1bc2x_b5_d1;
+ uint8_t f1bc3x_b5_d1;
+ uint8_t f1bc4x_b5_d1;
+ uint8_t f1bc5x_b5_d1;
+ uint8_t f1bc8x_b5_d1;
+ uint8_t f1bc9x_b5_d1;
+ uint8_t f1bcax_b5_d1;
+ uint8_t f1bcbx_b5_d1;
+ uint8_t f2bc2x_b5_d1;
+ uint8_t f2bc3x_b5_d1;
+ uint8_t f2bc4x_b5_d1;
+ uint8_t f2bc5x_b5_d1;
+ uint8_t f2bc8x_b5_d1;
+ uint8_t f2bc9x_b5_d1;
+ uint8_t f2bcax_b5_d1;
+ uint8_t f2bcbx_b5_d1;
+ uint8_t f3bc2x_b5_d1;
+ uint8_t f3bc3x_b5_d1;
+ uint8_t f3bc4x_b5_d1;
+ uint8_t f3bc5x_b5_d1;
+ uint8_t f3bc8x_b5_d1;
+ uint8_t f3bc9x_b5_d1;
+ uint8_t f3bcax_b5_d1;
+ uint8_t f3bcbx_b5_d1;
+ uint8_t f0bc2x_b6_d1;
+ uint8_t f0bc3x_b6_d1;
+ uint8_t f0bc4x_b6_d1;
+ uint8_t f0bc5x_b6_d1;
+ uint8_t f0bc8x_b6_d1;
+ uint8_t f0bc9x_b6_d1;
+ uint8_t f0bcax_b6_d1;
+ uint8_t f0bcbx_b6_d1;
+ uint8_t f1bc2x_b6_d1;
+ uint8_t f1bc3x_b6_d1;
+ uint8_t f1bc4x_b6_d1;
+ uint8_t f1bc5x_b6_d1;
+ uint8_t f1bc8x_b6_d1;
+ uint8_t f1bc9x_b6_d1;
+ uint8_t f1bcax_b6_d1;
+ uint8_t f1bcbx_b6_d1;
+ uint8_t f2bc2x_b6_d1;
+ uint8_t f2bc3x_b6_d1;
+ uint8_t f2bc4x_b6_d1;
+ uint8_t f2bc5x_b6_d1;
+ uint8_t f2bc8x_b6_d1;
+ uint8_t f2bc9x_b6_d1;
+ uint8_t f2bcax_b6_d1;
+ uint8_t f2bcbx_b6_d1;
+ uint8_t f3bc2x_b6_d1;
+ uint8_t f3bc3x_b6_d1;
+ uint8_t f3bc4x_b6_d1;
+ uint8_t f3bc5x_b6_d1;
+ uint8_t f3bc8x_b6_d1;
+ uint8_t f3bc9x_b6_d1;
+ uint8_t f3bcax_b6_d1;
+ uint8_t f3bcbx_b6_d1;
+ uint8_t f0bc2x_b7_d1;
+ uint8_t f0bc3x_b7_d1;
+ uint8_t f0bc4x_b7_d1;
+ uint8_t f0bc5x_b7_d1;
+ uint8_t f0bc8x_b7_d1;
+ uint8_t f0bc9x_b7_d1;
+ uint8_t f0bcax_b7_d1;
+ uint8_t f0bcbx_b7_d1;
+ uint8_t f1bc2x_b7_d1;
+ uint8_t f1bc3x_b7_d1;
+ uint8_t f1bc4x_b7_d1;
+ uint8_t f1bc5x_b7_d1;
+ uint8_t f1bc8x_b7_d1;
+ uint8_t f1bc9x_b7_d1;
+ uint8_t f1bcax_b7_d1;
+ uint8_t f1bcbx_b7_d1;
+ uint8_t f2bc2x_b7_d1;
+ uint8_t f2bc3x_b7_d1;
+ uint8_t f2bc4x_b7_d1;
+ uint8_t f2bc5x_b7_d1;
+ uint8_t f2bc8x_b7_d1;
+ uint8_t f2bc9x_b7_d1;
+ uint8_t f2bcax_b7_d1;
+ uint8_t f2bcbx_b7_d1;
+ uint8_t f3bc2x_b7_d1;
+ uint8_t f3bc3x_b7_d1;
+ uint8_t f3bc4x_b7_d1;
+ uint8_t f3bc5x_b7_d1;
+ uint8_t f3bc8x_b7_d1;
+ uint8_t f3bc9x_b7_d1;
+ uint8_t f3bcax_b7_d1;
+ uint8_t f3bcbx_b7_d1;
+ uint8_t f0bc2x_b8_d1;
+ uint8_t f0bc3x_b8_d1;
+ uint8_t f0bc4x_b8_d1;
+ uint8_t f0bc5x_b8_d1;
+ uint8_t f0bc8x_b8_d1;
+ uint8_t f0bc9x_b8_d1;
+ uint8_t f0bcax_b8_d1;
+ uint8_t f0bcbx_b8_d1;
+ uint8_t f1bc2x_b8_d1;
+ uint8_t f1bc3x_b8_d1;
+ uint8_t f1bc4x_b8_d1;
+ uint8_t f1bc5x_b8_d1;
+ uint8_t f1bc8x_b8_d1;
+ uint8_t f1bc9x_b8_d1;
+ uint8_t f1bcax_b8_d1;
+ uint8_t f1bcbx_b8_d1;
+ uint8_t f2bc2x_b8_d1;
+ uint8_t f2bc3x_b8_d1;
+ uint8_t f2bc4x_b8_d1;
+ uint8_t f2bc5x_b8_d1;
+ uint8_t f2bc8x_b8_d1;
+ uint8_t f2bc9x_b8_d1;
+ uint8_t f2bcax_b8_d1;
+ uint8_t f2bcbx_b8_d1;
+ uint8_t f3bc2x_b8_d1;
+ uint8_t f3bc3x_b8_d1;
+ uint8_t f3bc4x_b8_d1;
+ uint8_t f3bc5x_b8_d1;
+ uint8_t f3bc8x_b8_d1;
+ uint8_t f3bc9x_b8_d1;
+ uint8_t f3bcax_b8_d1;
+ uint8_t f3bcbx_b8_d1;
+ uint8_t f5bc5x_d1;
+ uint8_t f5bc6x_d1;
+ uint8_t f4bc8x_d1;
+ uint8_t f4bc9x_d1;
+ uint8_t f4bcax_d1;
+ uint8_t f4bcbx_d1;
+ uint8_t f4bccx_d1;
+ uint8_t f4bcdx_d1;
+ uint8_t f4bcex_d1;
+ uint8_t f4bcfx_d1;
+ uint8_t f5bc8x_d1;
+ uint8_t f5bc9x_d1;
+ uint8_t f5bcax_d1;
+ uint8_t f5bcbx_d1;
+ uint8_t f5bccx_d1;
+ uint8_t f5bcdx_d1;
+ uint8_t f5bcex_d1;
+ uint8_t f5bcfx_d1;
+ uint8_t f6bc8x_d1;
+ uint8_t f6bc9x_d1;
+ uint8_t f6bcax_d1;
+ uint8_t f6bcbx_d1;
+ uint8_t f6bccx_d1;
+ uint8_t f6bcdx_d1;
+ uint8_t f6bcex_d1;
+ uint8_t f6bcfx_d1;
+ uint8_t f7bc8x_d1;
+ uint8_t f7bc9x_d1;
+ uint8_t f7bcax_d1;
+ uint8_t f7bcbx_d1;
+ uint8_t f7bccx_d1;
+ uint8_t f7bcdx_d1;
+ uint8_t f7bcex_d1;
+ uint8_t f7bcfx_d1;
+ uint16_t alt_cas_l;
+ uint8_t alt_wcas_l;
+ uint8_t d4misc;
+} __packed;
+
+struct ddr4lr2d {
+ uint8_t reserved00;
+ uint8_t msg_misc;
+ uint16_t pmu_revision;
+ uint8_t pstate;
+ uint8_t pll_bypass_en;
+ uint16_t dramfreq;
+ uint8_t dfi_freq_ratio;
+ uint8_t bpznres_val;
+ uint8_t phy_odt_impedance;
+ uint8_t phy_drv_impedance;
+ uint8_t phy_vref;
+ uint8_t dram_type;
+ uint8_t disabled_dbyte;
+ uint8_t enabled_dqs;
+ uint8_t cs_present;
+ uint8_t cs_present_d0;
+ uint8_t cs_present_d1;
+ uint8_t addr_mirror;
+ uint8_t cs_test_fail;
+ uint8_t phy_cfg;
+ uint16_t sequence_ctrl;
+ uint8_t hdt_ctrl;
+ uint8_t rx2d_train_opt;
+ uint8_t tx2d_train_opt;
+ uint8_t share2dvref_result;
+ uint8_t delay_weight2d;
+ uint8_t voltage_weight2d;
+ uint8_t reserved1e[0x22 - 0x1e];
+ uint16_t phy_config_override;
+ uint8_t dfimrlmargin;
+ uint8_t r0_rx_clk_dly_margin;
+ uint8_t r0_vref_dac_margin;
+ uint8_t r0_tx_dq_dly_margin;
+ uint8_t r0_device_vref_margin;
+ uint8_t reserved29[0x33 - 0x29];
+ uint8_t r1_rx_clk_dly_margin;
+ uint8_t r1_vref_dac_margin;
+ uint8_t r1_tx_dq_dly_margin;
+ uint8_t r1_device_vref_margin;
+ uint8_t reserved37[0x41 - 0x37];
+ uint8_t r2_rx_clk_dly_margin;
+ uint8_t r2_vref_dac_margin;
+ uint8_t r2_tx_dq_dly_margin;
+ uint8_t r2_device_vref_margin;
+ uint8_t reserved45[0x4f - 0x45];
+ uint8_t r3_rx_clk_dly_margin;
+ uint8_t r3_vref_dac_margin;
+ uint8_t r3_tx_dq_dly_margin;
+ uint8_t r3_device_vref_margin;
+ uint8_t reserved53[0x5e - 0x53];
+ uint16_t mr0;
+ uint16_t mr1;
+ uint16_t mr2;
+ uint16_t mr3;
+ uint16_t mr4;
+ uint16_t mr5;
+ uint16_t mr6;
+ uint8_t x16present;
+ uint8_t cs_setup_gddec;
+ uint16_t rtt_nom_wr_park0;
+ uint16_t rtt_nom_wr_park1;
+ uint16_t rtt_nom_wr_park2;
+ uint16_t rtt_nom_wr_park3;
+ uint16_t rtt_nom_wr_park4;
+ uint16_t rtt_nom_wr_park5;
+ uint16_t rtt_nom_wr_park6;
+ uint16_t rtt_nom_wr_park7;
+ uint8_t acsm_odt_ctrl0;
+ uint8_t acsm_odt_ctrl1;
+ uint8_t acsm_odt_ctrl2;
+ uint8_t acsm_odt_ctrl3;
+ uint8_t acsm_odt_ctrl4;
+ uint8_t acsm_odt_ctrl5;
+ uint8_t acsm_odt_ctrl6;
+ uint8_t acsm_odt_ctrl7;
+ uint8_t vref_dq_r0nib0;
+ uint8_t vref_dq_r0nib1;
+ uint8_t vref_dq_r0nib2;
+ uint8_t vref_dq_r0nib3;
+ uint8_t vref_dq_r0nib4;
+ uint8_t vref_dq_r0nib5;
+ uint8_t vref_dq_r0nib6;
+ uint8_t vref_dq_r0nib7;
+ uint8_t vref_dq_r0nib8;
+ uint8_t vref_dq_r0nib9;
+ uint8_t vref_dq_r0nib10;
+ uint8_t vref_dq_r0nib11;
+ uint8_t vref_dq_r0nib12;
+ uint8_t vref_dq_r0nib13;
+ uint8_t vref_dq_r0nib14;
+ uint8_t vref_dq_r0nib15;
+ uint8_t vref_dq_r0nib16;
+ uint8_t vref_dq_r0nib17;
+ uint8_t vref_dq_r0nib18;
+ uint8_t vref_dq_r0nib19;
+ uint8_t vref_dq_r1nib0;
+ uint8_t vref_dq_r1nib1;
+ uint8_t vref_dq_r1nib2;
+ uint8_t vref_dq_r1nib3;
+ uint8_t vref_dq_r1nib4;
+ uint8_t vref_dq_r1nib5;
+ uint8_t vref_dq_r1nib6;
+ uint8_t vref_dq_r1nib7;
+ uint8_t vref_dq_r1nib8;
+ uint8_t vref_dq_r1nib9;
+ uint8_t vref_dq_r1nib10;
+ uint8_t vref_dq_r1nib11;
+ uint8_t vref_dq_r1nib12;
+ uint8_t vref_dq_r1nib13;
+ uint8_t vref_dq_r1nib14;
+ uint8_t vref_dq_r1nib15;
+ uint8_t vref_dq_r1nib16;
+ uint8_t vref_dq_r1nib17;
+ uint8_t vref_dq_r1nib18;
+ uint8_t vref_dq_r1nib19;
+ uint8_t vref_dq_r2nib0;
+ uint8_t vref_dq_r2nib1;
+ uint8_t vref_dq_r2nib2;
+ uint8_t vref_dq_r2nib3;
+ uint8_t vref_dq_r2nib4;
+ uint8_t vref_dq_r2nib5;
+ uint8_t vref_dq_r2nib6;
+ uint8_t vref_dq_r2nib7;
+ uint8_t vref_dq_r2nib8;
+ uint8_t vref_dq_r2nib9;
+ uint8_t vref_dq_r2nib10;
+ uint8_t vref_dq_r2nib11;
+ uint8_t vref_dq_r2nib12;
+ uint8_t vref_dq_r2nib13;
+ uint8_t vref_dq_r2nib14;
+ uint8_t vref_dq_r2nib15;
+ uint8_t vref_dq_r2nib16;
+ uint8_t vref_dq_r2nib17;
+ uint8_t vref_dq_r2nib18;
+ uint8_t vref_dq_r2nib19;
+ uint8_t vref_dq_r3nib0;
+ uint8_t vref_dq_r3nib1;
+ uint8_t vref_dq_r3nib2;
+ uint8_t vref_dq_r3nib3;
+ uint8_t vref_dq_r3nib4;
+ uint8_t vref_dq_r3nib5;
+ uint8_t vref_dq_r3nib6;
+ uint8_t vref_dq_r3nib7;
+ uint8_t vref_dq_r3nib8;
+ uint8_t vref_dq_r3nib9;
+ uint8_t vref_dq_r3nib10;
+ uint8_t vref_dq_r3nib11;
+ uint8_t vref_dq_r3nib12;
+ uint8_t vref_dq_r3nib13;
+ uint8_t vref_dq_r3nib14;
+ uint8_t vref_dq_r3nib15;
+ uint8_t vref_dq_r3nib16;
+ uint8_t vref_dq_r3nib17;
+ uint8_t vref_dq_r3nib18;
+ uint8_t vref_dq_r3nib19;
+ uint8_t f0rc00_d0;
+ uint8_t f0rc01_d0;
+ uint8_t f0rc02_d0;
+ uint8_t f0rc03_d0;
+ uint8_t f0rc04_d0;
+ uint8_t f0rc05_d0;
+ uint8_t f0rc06_d0;
+ uint8_t f0rc07_d0;
+ uint8_t f0rc08_d0;
+ uint8_t f0rc09_d0;
+ uint8_t f0rc0a_d0;
+ uint8_t f0rc0b_d0;
+ uint8_t f0rc0c_d0;
+ uint8_t f0rc0d_d0;
+ uint8_t f0rc0e_d0;
+ uint8_t f0rc0f_d0;
+ uint8_t f0rc1x_d0;
+ uint8_t f0rc2x_d0;
+ uint8_t f0rc3x_d0;
+ uint8_t f0rc4x_d0;
+ uint8_t f0rc5x_d0;
+ uint8_t f0rc6x_d0;
+ uint8_t f0rc7x_d0;
+ uint8_t f0rc8x_d0;
+ uint8_t f0rc9x_d0;
+ uint8_t f0rcax_d0;
+ uint8_t f0rcbx_d0;
+ uint8_t f1rc00_d0;
+ uint8_t f1rc01_d0;
+ uint8_t f1rc02_d0;
+ uint8_t f1rc03_d0;
+ uint8_t f1rc04_d0;
+ uint8_t f1rc05_d0;
+ uint8_t f1rc06_d0;
+ uint8_t f1rc07_d0;
+ uint8_t f1rc08_d0;
+ uint8_t f1rc09_d0;
+ uint8_t f1rc0a_d0;
+ uint8_t f1rc0b_d0;
+ uint8_t f1rc0c_d0;
+ uint8_t f1rc0d_d0;
+ uint8_t f1rc0e_d0;
+ uint8_t f1rc0f_d0;
+ uint8_t f1rc1x_d0;
+ uint8_t f1rc2x_d0;
+ uint8_t f1rc3x_d0;
+ uint8_t f1rc4x_d0;
+ uint8_t f1rc5x_d0;
+ uint8_t f1rc6x_d0;
+ uint8_t f1rc7x_d0;
+ uint8_t f1rc8x_d0;
+ uint8_t f1rc9x_d0;
+ uint8_t f1rcax_d0;
+ uint8_t f1rcbx_d0;
+ uint8_t f0rc00_d1;
+ uint8_t f0rc01_d1;
+ uint8_t f0rc02_d1;
+ uint8_t f0rc03_d1;
+ uint8_t f0rc04_d1;
+ uint8_t f0rc05_d1;
+ uint8_t f0rc06_d1;
+ uint8_t f0rc07_d1;
+ uint8_t f0rc08_d1;
+ uint8_t f0rc09_d1;
+ uint8_t f0rc0a_d1;
+ uint8_t f0rc0b_d1;
+ uint8_t f0rc0c_d1;
+ uint8_t f0rc0d_d1;
+ uint8_t f0rc0e_d1;
+ uint8_t f0rc0f_d1;
+ uint8_t f0rc1x_d1;
+ uint8_t f0rc2x_d1;
+ uint8_t f0rc3x_d1;
+ uint8_t f0rc4x_d1;
+ uint8_t f0rc5x_d1;
+ uint8_t f0rc6x_d1;
+ uint8_t f0rc7x_d1;
+ uint8_t f0rc8x_d1;
+ uint8_t f0rc9x_d1;
+ uint8_t f0rcax_d1;
+ uint8_t f0rcbx_d1;
+ uint8_t f1rc00_d1;
+ uint8_t f1rc01_d1;
+ uint8_t f1rc02_d1;
+ uint8_t f1rc03_d1;
+ uint8_t f1rc04_d1;
+ uint8_t f1rc05_d1;
+ uint8_t f1rc06_d1;
+ uint8_t f1rc07_d1;
+ uint8_t f1rc08_d1;
+ uint8_t f1rc09_d1;
+ uint8_t f1rc0a_d1;
+ uint8_t f1rc0b_d1;
+ uint8_t f1rc0c_d1;
+ uint8_t f1rc0d_d1;
+ uint8_t f1rc0e_d1;
+ uint8_t f1rc0f_d1;
+ uint8_t f1rc1x_d1;
+ uint8_t f1rc2x_d1;
+ uint8_t f1rc3x_d1;
+ uint8_t f1rc4x_d1;
+ uint8_t f1rc5x_d1;
+ uint8_t f1rc6x_d1;
+ uint8_t f1rc7x_d1;
+ uint8_t f1rc8x_d1;
+ uint8_t f1rc9x_d1;
+ uint8_t f1rcax_d1;
+ uint8_t f1rcbx_d1;
+ uint8_t bc00_d0;
+ uint8_t bc01_d0;
+ uint8_t bc02_d0;
+ uint8_t bc03_d0;
+ uint8_t bc04_d0;
+ uint8_t bc05_d0;
+ uint8_t bc06_d0;
+ uint8_t bc07_d0;
+ uint8_t bc08_d0;
+ uint8_t bc09_d0;
+ uint8_t bc0a_d0;
+ uint8_t bc0b_d0;
+ uint8_t bc0c_d0;
+ uint8_t bc0d_d0;
+ uint8_t bc0e_d0;
+ uint8_t f0bc6x_d0;
+ uint8_t f0bccx_d0;
+ uint8_t f0bcdx_d0;
+ uint8_t f0bcex_d0;
+ uint8_t f0bcfx_d0;
+ uint8_t f1bccx_d0;
+ uint8_t f1bcdx_d0;
+ uint8_t f1bcex_d0;
+ uint8_t f1bcfx_d0;
+ uint8_t f0bc2x_b0_d0;
+ uint8_t f0bc3x_b0_d0;
+ uint8_t f0bc4x_b0_d0;
+ uint8_t f0bc5x_b0_d0;
+ uint8_t f0bc8x_b0_d0;
+ uint8_t f0bc9x_b0_d0;
+ uint8_t f0bcax_b0_d0;
+ uint8_t f0bcbx_b0_d0;
+ uint8_t f1bc2x_b0_d0;
+ uint8_t f1bc3x_b0_d0;
+ uint8_t f1bc4x_b0_d0;
+ uint8_t f1bc5x_b0_d0;
+ uint8_t f1bc8x_b0_d0;
+ uint8_t f1bc9x_b0_d0;
+ uint8_t f1bcax_b0_d0;
+ uint8_t f1bcbx_b0_d0;
+ uint8_t f2bc2x_b0_d0;
+ uint8_t f2bc3x_b0_d0;
+ uint8_t f2bc4x_b0_d0;
+ uint8_t f2bc5x_b0_d0;
+ uint8_t f2bc8x_b0_d0;
+ uint8_t f2bc9x_b0_d0;
+ uint8_t f2bcax_b0_d0;
+ uint8_t f2bcbx_b0_d0;
+ uint8_t f3bc2x_b0_d0;
+ uint8_t f3bc3x_b0_d0;
+ uint8_t f3bc4x_b0_d0;
+ uint8_t f3bc5x_b0_d0;
+ uint8_t f3bc8x_b0_d0;
+ uint8_t f3bc9x_b0_d0;
+ uint8_t f3bcax_b0_d0;
+ uint8_t f3bcbx_b0_d0;
+ uint8_t f0bc2x_b1_d0;
+ uint8_t f0bc3x_b1_d0;
+ uint8_t f0bc4x_b1_d0;
+ uint8_t f0bc5x_b1_d0;
+ uint8_t f0bc8x_b1_d0;
+ uint8_t f0bc9x_b1_d0;
+ uint8_t f0bcax_b1_d0;
+ uint8_t f0bcbx_b1_d0;
+ uint8_t f1bc2x_b1_d0;
+ uint8_t f1bc3x_b1_d0;
+ uint8_t f1bc4x_b1_d0;
+ uint8_t f1bc5x_b1_d0;
+ uint8_t f1bc8x_b1_d0;
+ uint8_t f1bc9x_b1_d0;
+ uint8_t f1bcax_b1_d0;
+ uint8_t f1bcbx_b1_d0;
+ uint8_t f2bc2x_b1_d0;
+ uint8_t f2bc3x_b1_d0;
+ uint8_t f2bc4x_b1_d0;
+ uint8_t f2bc5x_b1_d0;
+ uint8_t f2bc8x_b1_d0;
+ uint8_t f2bc9x_b1_d0;
+ uint8_t f2bcax_b1_d0;
+ uint8_t f2bcbx_b1_d0;
+ uint8_t f3bc2x_b1_d0;
+ uint8_t f3bc3x_b1_d0;
+ uint8_t f3bc4x_b1_d0;
+ uint8_t f3bc5x_b1_d0;
+ uint8_t f3bc8x_b1_d0;
+ uint8_t f3bc9x_b1_d0;
+ uint8_t f3bcax_b1_d0;
+ uint8_t f3bcbx_b1_d0;
+ uint8_t f0bc2x_b2_d0;
+ uint8_t f0bc3x_b2_d0;
+ uint8_t f0bc4x_b2_d0;
+ uint8_t f0bc5x_b2_d0;
+ uint8_t f0bc8x_b2_d0;
+ uint8_t f0bc9x_b2_d0;
+ uint8_t f0bcax_b2_d0;
+ uint8_t f0bcbx_b2_d0;
+ uint8_t f1bc2x_b2_d0;
+ uint8_t f1bc3x_b2_d0;
+ uint8_t f1bc4x_b2_d0;
+ uint8_t f1bc5x_b2_d0;
+ uint8_t f1bc8x_b2_d0;
+ uint8_t f1bc9x_b2_d0;
+ uint8_t f1bcax_b2_d0;
+ uint8_t f1bcbx_b2_d0;
+ uint8_t f2bc2x_b2_d0;
+ uint8_t f2bc3x_b2_d0;
+ uint8_t f2bc4x_b2_d0;
+ uint8_t f2bc5x_b2_d0;
+ uint8_t f2bc8x_b2_d0;
+ uint8_t f2bc9x_b2_d0;
+ uint8_t f2bcax_b2_d0;
+ uint8_t f2bcbx_b2_d0;
+ uint8_t f3bc2x_b2_d0;
+ uint8_t f3bc3x_b2_d0;
+ uint8_t f3bc4x_b2_d0;
+ uint8_t f3bc5x_b2_d0;
+ uint8_t f3bc8x_b2_d0;
+ uint8_t f3bc9x_b2_d0;
+ uint8_t f3bcax_b2_d0;
+ uint8_t f3bcbx_b2_d0;
+ uint8_t f0bc2x_b3_d0;
+ uint8_t f0bc3x_b3_d0;
+ uint8_t f0bc4x_b3_d0;
+ uint8_t f0bc5x_b3_d0;
+ uint8_t f0bc8x_b3_d0;
+ uint8_t f0bc9x_b3_d0;
+ uint8_t f0bcax_b3_d0;
+ uint8_t f0bcbx_b3_d0;
+ uint8_t f1bc2x_b3_d0;
+ uint8_t f1bc3x_b3_d0;
+ uint8_t f1bc4x_b3_d0;
+ uint8_t f1bc5x_b3_d0;
+ uint8_t f1bc8x_b3_d0;
+ uint8_t f1bc9x_b3_d0;
+ uint8_t f1bcax_b3_d0;
+ uint8_t f1bcbx_b3_d0;
+ uint8_t f2bc2x_b3_d0;
+ uint8_t f2bc3x_b3_d0;
+ uint8_t f2bc4x_b3_d0;
+ uint8_t f2bc5x_b3_d0;
+ uint8_t f2bc8x_b3_d0;
+ uint8_t f2bc9x_b3_d0;
+ uint8_t f2bcax_b3_d0;
+ uint8_t f2bcbx_b3_d0;
+ uint8_t f3bc2x_b3_d0;
+ uint8_t f3bc3x_b3_d0;
+ uint8_t f3bc4x_b3_d0;
+ uint8_t f3bc5x_b3_d0;
+ uint8_t f3bc8x_b3_d0;
+ uint8_t f3bc9x_b3_d0;
+ uint8_t f3bcax_b3_d0;
+ uint8_t f3bcbx_b3_d0;
+ uint8_t f0bc2x_b4_d0;
+ uint8_t f0bc3x_b4_d0;
+ uint8_t f0bc4x_b4_d0;
+ uint8_t f0bc5x_b4_d0;
+ uint8_t f0bc8x_b4_d0;
+ uint8_t f0bc9x_b4_d0;
+ uint8_t f0bcax_b4_d0;
+ uint8_t f0bcbx_b4_d0;
+ uint8_t f1bc2x_b4_d0;
+ uint8_t f1bc3x_b4_d0;
+ uint8_t f1bc4x_b4_d0;
+ uint8_t f1bc5x_b4_d0;
+ uint8_t f1bc8x_b4_d0;
+ uint8_t f1bc9x_b4_d0;
+ uint8_t f1bcax_b4_d0;
+ uint8_t f1bcbx_b4_d0;
+ uint8_t f2bc2x_b4_d0;
+ uint8_t f2bc3x_b4_d0;
+ uint8_t f2bc4x_b4_d0;
+ uint8_t f2bc5x_b4_d0;
+ uint8_t f2bc8x_b4_d0;
+ uint8_t f2bc9x_b4_d0;
+ uint8_t f2bcax_b4_d0;
+ uint8_t f2bcbx_b4_d0;
+ uint8_t f3bc2x_b4_d0;
+ uint8_t f3bc3x_b4_d0;
+ uint8_t f3bc4x_b4_d0;
+ uint8_t f3bc5x_b4_d0;
+ uint8_t f3bc8x_b4_d0;
+ uint8_t f3bc9x_b4_d0;
+ uint8_t f3bcax_b4_d0;
+ uint8_t f3bcbx_b4_d0;
+ uint8_t f0bc2x_b5_d0;
+ uint8_t f0bc3x_b5_d0;
+ uint8_t f0bc4x_b5_d0;
+ uint8_t f0bc5x_b5_d0;
+ uint8_t f0bc8x_b5_d0;
+ uint8_t f0bc9x_b5_d0;
+ uint8_t f0bcax_b5_d0;
+ uint8_t f0bcbx_b5_d0;
+ uint8_t f1bc2x_b5_d0;
+ uint8_t f1bc3x_b5_d0;
+ uint8_t f1bc4x_b5_d0;
+ uint8_t f1bc5x_b5_d0;
+ uint8_t f1bc8x_b5_d0;
+ uint8_t f1bc9x_b5_d0;
+ uint8_t f1bcax_b5_d0;
+ uint8_t f1bcbx_b5_d0;
+ uint8_t f2bc2x_b5_d0;
+ uint8_t f2bc3x_b5_d0;
+ uint8_t f2bc4x_b5_d0;
+ uint8_t f2bc5x_b5_d0;
+ uint8_t f2bc8x_b5_d0;
+ uint8_t f2bc9x_b5_d0;
+ uint8_t f2bcax_b5_d0;
+ uint8_t f2bcbx_b5_d0;
+ uint8_t f3bc2x_b5_d0;
+ uint8_t f3bc3x_b5_d0;
+ uint8_t f3bc4x_b5_d0;
+ uint8_t f3bc5x_b5_d0;
+ uint8_t f3bc8x_b5_d0;
+ uint8_t f3bc9x_b5_d0;
+ uint8_t f3bcax_b5_d0;
+ uint8_t f3bcbx_b5_d0;
+ uint8_t f0bc2x_b6_d0;
+ uint8_t f0bc3x_b6_d0;
+ uint8_t f0bc4x_b6_d0;
+ uint8_t f0bc5x_b6_d0;
+ uint8_t f0bc8x_b6_d0;
+ uint8_t f0bc9x_b6_d0;
+ uint8_t f0bcax_b6_d0;
+ uint8_t f0bcbx_b6_d0;
+ uint8_t f1bc2x_b6_d0;
+ uint8_t f1bc3x_b6_d0;
+ uint8_t f1bc4x_b6_d0;
+ uint8_t f1bc5x_b6_d0;
+ uint8_t f1bc8x_b6_d0;
+ uint8_t f1bc9x_b6_d0;
+ uint8_t f1bcax_b6_d0;
+ uint8_t f1bcbx_b6_d0;
+ uint8_t f2bc2x_b6_d0;
+ uint8_t f2bc3x_b6_d0;
+ uint8_t f2bc4x_b6_d0;
+ uint8_t f2bc5x_b6_d0;
+ uint8_t f2bc8x_b6_d0;
+ uint8_t f2bc9x_b6_d0;
+ uint8_t f2bcax_b6_d0;
+ uint8_t f2bcbx_b6_d0;
+ uint8_t f3bc2x_b6_d0;
+ uint8_t f3bc3x_b6_d0;
+ uint8_t f3bc4x_b6_d0;
+ uint8_t f3bc5x_b6_d0;
+ uint8_t f3bc8x_b6_d0;
+ uint8_t f3bc9x_b6_d0;
+ uint8_t f3bcax_b6_d0;
+ uint8_t f3bcbx_b6_d0;
+ uint8_t f0bc2x_b7_d0;
+ uint8_t f0bc3x_b7_d0;
+ uint8_t f0bc4x_b7_d0;
+ uint8_t f0bc5x_b7_d0;
+ uint8_t f0bc8x_b7_d0;
+ uint8_t f0bc9x_b7_d0;
+ uint8_t f0bcax_b7_d0;
+ uint8_t f0bcbx_b7_d0;
+ uint8_t f1bc2x_b7_d0;
+ uint8_t f1bc3x_b7_d0;
+ uint8_t f1bc4x_b7_d0;
+ uint8_t f1bc5x_b7_d0;
+ uint8_t f1bc8x_b7_d0;
+ uint8_t f1bc9x_b7_d0;
+ uint8_t f1bcax_b7_d0;
+ uint8_t f1bcbx_b7_d0;
+ uint8_t f2bc2x_b7_d0;
+ uint8_t f2bc3x_b7_d0;
+ uint8_t f2bc4x_b7_d0;
+ uint8_t f2bc5x_b7_d0;
+ uint8_t f2bc8x_b7_d0;
+ uint8_t f2bc9x_b7_d0;
+ uint8_t f2bcax_b7_d0;
+ uint8_t f2bcbx_b7_d0;
+ uint8_t f3bc2x_b7_d0;
+ uint8_t f3bc3x_b7_d0;
+ uint8_t f3bc4x_b7_d0;
+ uint8_t f3bc5x_b7_d0;
+ uint8_t f3bc8x_b7_d0;
+ uint8_t f3bc9x_b7_d0;
+ uint8_t f3bcax_b7_d0;
+ uint8_t f3bcbx_b7_d0;
+ uint8_t f0bc2x_b8_d0;
+ uint8_t f0bc3x_b8_d0;
+ uint8_t f0bc4x_b8_d0;
+ uint8_t f0bc5x_b8_d0;
+ uint8_t f0bc8x_b8_d0;
+ uint8_t f0bc9x_b8_d0;
+ uint8_t f0bcax_b8_d0;
+ uint8_t f0bcbx_b8_d0;
+ uint8_t f1bc2x_b8_d0;
+ uint8_t f1bc3x_b8_d0;
+ uint8_t f1bc4x_b8_d0;
+ uint8_t f1bc5x_b8_d0;
+ uint8_t f1bc8x_b8_d0;
+ uint8_t f1bc9x_b8_d0;
+ uint8_t f1bcax_b8_d0;
+ uint8_t f1bcbx_b8_d0;
+ uint8_t f2bc2x_b8_d0;
+ uint8_t f2bc3x_b8_d0;
+ uint8_t f2bc4x_b8_d0;
+ uint8_t f2bc5x_b8_d0;
+ uint8_t f2bc8x_b8_d0;
+ uint8_t f2bc9x_b8_d0;
+ uint8_t f2bcax_b8_d0;
+ uint8_t f2bcbx_b8_d0;
+ uint8_t f3bc2x_b8_d0;
+ uint8_t f3bc3x_b8_d0;
+ uint8_t f3bc4x_b8_d0;
+ uint8_t f3bc5x_b8_d0;
+ uint8_t f3bc8x_b8_d0;
+ uint8_t f3bc9x_b8_d0;
+ uint8_t f3bcax_b8_d0;
+ uint8_t f3bcbx_b8_d0;
+ uint8_t f5bc5x_d0;
+ uint8_t f5bc6x_d0;
+ uint8_t f4bc8x_d0;
+ uint8_t f4bc9x_d0;
+ uint8_t f4bcax_d0;
+ uint8_t f4bcbx_d0;
+ uint8_t f4bccx_d0;
+ uint8_t f4bcdx_d0;
+ uint8_t f4bcex_d0;
+ uint8_t f4bcfx_d0;
+ uint8_t f5bc8x_d0;
+ uint8_t f5bc9x_d0;
+ uint8_t f5bcax_d0;
+ uint8_t f5bcbx_d0;
+ uint8_t f5bccx_d0;
+ uint8_t f5bcdx_d0;
+ uint8_t f5bcex_d0;
+ uint8_t f5bcfx_d0;
+ uint8_t f6bc8x_d0;
+ uint8_t f6bc9x_d0;
+ uint8_t f6bcax_d0;
+ uint8_t f6bcbx_d0;
+ uint8_t f6bccx_d0;
+ uint8_t f6bcdx_d0;
+ uint8_t f6bcex_d0;
+ uint8_t f6bcfx_d0;
+ uint8_t f7bc8x_d0;
+ uint8_t f7bc9x_d0;
+ uint8_t f7bcax_d0;
+ uint8_t f7bcbx_d0;
+ uint8_t f7bccx_d0;
+ uint8_t f7bcdx_d0;
+ uint8_t f7bcex_d0;
+ uint8_t f7bcfx_d0;
+ uint8_t bc00_d1;
+ uint8_t bc01_d1;
+ uint8_t bc02_d1;
+ uint8_t bc03_d1;
+ uint8_t bc04_d1;
+ uint8_t bc05_d1;
+ uint8_t bc06_d1;
+ uint8_t bc07_d1;
+ uint8_t bc08_d1;
+ uint8_t bc09_d1;
+ uint8_t bc0a_d1;
+ uint8_t bc0b_d1;
+ uint8_t bc0c_d1;
+ uint8_t bc0d_d1;
+ uint8_t bc0e_d1;
+ uint8_t f0bc6x_d1;
+ uint8_t f0bccx_d1;
+ uint8_t f0bcdx_d1;
+ uint8_t f0bcex_d1;
+ uint8_t f0bcfx_d1;
+ uint8_t f1bccx_d1;
+ uint8_t f1bcdx_d1;
+ uint8_t f1bcex_d1;
+ uint8_t f1bcfx_d1;
+ uint8_t f0bc2x_b0_d1;
+ uint8_t f0bc3x_b0_d1;
+ uint8_t f0bc4x_b0_d1;
+ uint8_t f0bc5x_b0_d1;
+ uint8_t f0bc8x_b0_d1;
+ uint8_t f0bc9x_b0_d1;
+ uint8_t f0bcax_b0_d1;
+ uint8_t f0bcbx_b0_d1;
+ uint8_t f1bc2x_b0_d1;
+ uint8_t f1bc3x_b0_d1;
+ uint8_t f1bc4x_b0_d1;
+ uint8_t f1bc5x_b0_d1;
+ uint8_t f1bc8x_b0_d1;
+ uint8_t f1bc9x_b0_d1;
+ uint8_t f1bcax_b0_d1;
+ uint8_t f1bcbx_b0_d1;
+ uint8_t f2bc2x_b0_d1;
+ uint8_t f2bc3x_b0_d1;
+ uint8_t f2bc4x_b0_d1;
+ uint8_t f2bc5x_b0_d1;
+ uint8_t f2bc8x_b0_d1;
+ uint8_t f2bc9x_b0_d1;
+ uint8_t f2bcax_b0_d1;
+ uint8_t f2bcbx_b0_d1;
+ uint8_t f3bc2x_b0_d1;
+ uint8_t f3bc3x_b0_d1;
+ uint8_t f3bc4x_b0_d1;
+ uint8_t f3bc5x_b0_d1;
+ uint8_t f3bc8x_b0_d1;
+ uint8_t f3bc9x_b0_d1;
+ uint8_t f3bcax_b0_d1;
+ uint8_t f3bcbx_b0_d1;
+ uint8_t f0bc2x_b1_d1;
+ uint8_t f0bc3x_b1_d1;
+ uint8_t f0bc4x_b1_d1;
+ uint8_t f0bc5x_b1_d1;
+ uint8_t f0bc8x_b1_d1;
+ uint8_t f0bc9x_b1_d1;
+ uint8_t f0bcax_b1_d1;
+ uint8_t f0bcbx_b1_d1;
+ uint8_t f1bc2x_b1_d1;
+ uint8_t f1bc3x_b1_d1;
+ uint8_t f1bc4x_b1_d1;
+ uint8_t f1bc5x_b1_d1;
+ uint8_t f1bc8x_b1_d1;
+ uint8_t f1bc9x_b1_d1;
+ uint8_t f1bcax_b1_d1;
+ uint8_t f1bcbx_b1_d1;
+ uint8_t f2bc2x_b1_d1;
+ uint8_t f2bc3x_b1_d1;
+ uint8_t f2bc4x_b1_d1;
+ uint8_t f2bc5x_b1_d1;
+ uint8_t f2bc8x_b1_d1;
+ uint8_t f2bc9x_b1_d1;
+ uint8_t f2bcax_b1_d1;
+ uint8_t f2bcbx_b1_d1;
+ uint8_t f3bc2x_b1_d1;
+ uint8_t f3bc3x_b1_d1;
+ uint8_t f3bc4x_b1_d1;
+ uint8_t f3bc5x_b1_d1;
+ uint8_t f3bc8x_b1_d1;
+ uint8_t f3bc9x_b1_d1;
+ uint8_t f3bcax_b1_d1;
+ uint8_t f3bcbx_b1_d1;
+ uint8_t f0bc2x_b2_d1;
+ uint8_t f0bc3x_b2_d1;
+ uint8_t f0bc4x_b2_d1;
+ uint8_t f0bc5x_b2_d1;
+ uint8_t f0bc8x_b2_d1;
+ uint8_t f0bc9x_b2_d1;
+ uint8_t f0bcax_b2_d1;
+ uint8_t f0bcbx_b2_d1;
+ uint8_t f1bc2x_b2_d1;
+ uint8_t f1bc3x_b2_d1;
+ uint8_t f1bc4x_b2_d1;
+ uint8_t f1bc5x_b2_d1;
+ uint8_t f1bc8x_b2_d1;
+ uint8_t f1bc9x_b2_d1;
+ uint8_t f1bcax_b2_d1;
+ uint8_t f1bcbx_b2_d1;
+ uint8_t f2bc2x_b2_d1;
+ uint8_t f2bc3x_b2_d1;
+ uint8_t f2bc4x_b2_d1;
+ uint8_t f2bc5x_b2_d1;
+ uint8_t f2bc8x_b2_d1;
+ uint8_t f2bc9x_b2_d1;
+ uint8_t f2bcax_b2_d1;
+ uint8_t f2bcbx_b2_d1;
+ uint8_t f3bc2x_b2_d1;
+ uint8_t f3bc3x_b2_d1;
+ uint8_t f3bc4x_b2_d1;
+ uint8_t f3bc5x_b2_d1;
+ uint8_t f3bc8x_b2_d1;
+ uint8_t f3bc9x_b2_d1;
+ uint8_t f3bcax_b2_d1;
+ uint8_t f3bcbx_b2_d1;
+ uint8_t f0bc2x_b3_d1;
+ uint8_t f0bc3x_b3_d1;
+ uint8_t f0bc4x_b3_d1;
+ uint8_t f0bc5x_b3_d1;
+ uint8_t f0bc8x_b3_d1;
+ uint8_t f0bc9x_b3_d1;
+ uint8_t f0bcax_b3_d1;
+ uint8_t f0bcbx_b3_d1;
+ uint8_t f1bc2x_b3_d1;
+ uint8_t f1bc3x_b3_d1;
+ uint8_t f1bc4x_b3_d1;
+ uint8_t f1bc5x_b3_d1;
+ uint8_t f1bc8x_b3_d1;
+ uint8_t f1bc9x_b3_d1;
+ uint8_t f1bcax_b3_d1;
+ uint8_t f1bcbx_b3_d1;
+ uint8_t f2bc2x_b3_d1;
+ uint8_t f2bc3x_b3_d1;
+ uint8_t f2bc4x_b3_d1;
+ uint8_t f2bc5x_b3_d1;
+ uint8_t f2bc8x_b3_d1;
+ uint8_t f2bc9x_b3_d1;
+ uint8_t f2bcax_b3_d1;
+ uint8_t f2bcbx_b3_d1;
+ uint8_t f3bc2x_b3_d1;
+ uint8_t f3bc3x_b3_d1;
+ uint8_t f3bc4x_b3_d1;
+ uint8_t f3bc5x_b3_d1;
+ uint8_t f3bc8x_b3_d1;
+ uint8_t f3bc9x_b3_d1;
+ uint8_t f3bcax_b3_d1;
+ uint8_t f3bcbx_b3_d1;
+ uint8_t f0bc2x_b4_d1;
+ uint8_t f0bc3x_b4_d1;
+ uint8_t f0bc4x_b4_d1;
+ uint8_t f0bc5x_b4_d1;
+ uint8_t f0bc8x_b4_d1;
+ uint8_t f0bc9x_b4_d1;
+ uint8_t f0bcax_b4_d1;
+ uint8_t f0bcbx_b4_d1;
+ uint8_t f1bc2x_b4_d1;
+ uint8_t f1bc3x_b4_d1;
+ uint8_t f1bc4x_b4_d1;
+ uint8_t f1bc5x_b4_d1;
+ uint8_t f1bc8x_b4_d1;
+ uint8_t f1bc9x_b4_d1;
+ uint8_t f1bcax_b4_d1;
+ uint8_t f1bcbx_b4_d1;
+ uint8_t f2bc2x_b4_d1;
+ uint8_t f2bc3x_b4_d1;
+ uint8_t f2bc4x_b4_d1;
+ uint8_t f2bc5x_b4_d1;
+ uint8_t f2bc8x_b4_d1;
+ uint8_t f2bc9x_b4_d1;
+ uint8_t f2bcax_b4_d1;
+ uint8_t f2bcbx_b4_d1;
+ uint8_t f3bc2x_b4_d1;
+ uint8_t f3bc3x_b4_d1;
+ uint8_t f3bc4x_b4_d1;
+ uint8_t f3bc5x_b4_d1;
+ uint8_t f3bc8x_b4_d1;
+ uint8_t f3bc9x_b4_d1;
+ uint8_t f3bcax_b4_d1;
+ uint8_t f3bcbx_b4_d1;
+ uint8_t f0bc2x_b5_d1;
+ uint8_t f0bc3x_b5_d1;
+ uint8_t f0bc4x_b5_d1;
+ uint8_t f0bc5x_b5_d1;
+ uint8_t f0bc8x_b5_d1;
+ uint8_t f0bc9x_b5_d1;
+ uint8_t f0bcax_b5_d1;
+ uint8_t f0bcbx_b5_d1;
+ uint8_t f1bc2x_b5_d1;
+ uint8_t f1bc3x_b5_d1;
+ uint8_t f1bc4x_b5_d1;
+ uint8_t f1bc5x_b5_d1;
+ uint8_t f1bc8x_b5_d1;
+ uint8_t f1bc9x_b5_d1;
+ uint8_t f1bcax_b5_d1;
+ uint8_t f1bcbx_b5_d1;
+ uint8_t f2bc2x_b5_d1;
+ uint8_t f2bc3x_b5_d1;
+ uint8_t f2bc4x_b5_d1;
+ uint8_t f2bc5x_b5_d1;
+ uint8_t f2bc8x_b5_d1;
+ uint8_t f2bc9x_b5_d1;
+ uint8_t f2bcax_b5_d1;
+ uint8_t f2bcbx_b5_d1;
+ uint8_t f3bc2x_b5_d1;
+ uint8_t f3bc3x_b5_d1;
+ uint8_t f3bc4x_b5_d1;
+ uint8_t f3bc5x_b5_d1;
+ uint8_t f3bc8x_b5_d1;
+ uint8_t f3bc9x_b5_d1;
+ uint8_t f3bcax_b5_d1;
+ uint8_t f3bcbx_b5_d1;
+ uint8_t f0bc2x_b6_d1;
+ uint8_t f0bc3x_b6_d1;
+ uint8_t f0bc4x_b6_d1;
+ uint8_t f0bc5x_b6_d1;
+ uint8_t f0bc8x_b6_d1;
+ uint8_t f0bc9x_b6_d1;
+ uint8_t f0bcax_b6_d1;
+ uint8_t f0bcbx_b6_d1;
+ uint8_t f1bc2x_b6_d1;
+ uint8_t f1bc3x_b6_d1;
+ uint8_t f1bc4x_b6_d1;
+ uint8_t f1bc5x_b6_d1;
+ uint8_t f1bc8x_b6_d1;
+ uint8_t f1bc9x_b6_d1;
+ uint8_t f1bcax_b6_d1;
+ uint8_t f1bcbx_b6_d1;
+ uint8_t f2bc2x_b6_d1;
+ uint8_t f2bc3x_b6_d1;
+ uint8_t f2bc4x_b6_d1;
+ uint8_t f2bc5x_b6_d1;
+ uint8_t f2bc8x_b6_d1;
+ uint8_t f2bc9x_b6_d1;
+ uint8_t f2bcax_b6_d1;
+ uint8_t f2bcbx_b6_d1;
+ uint8_t f3bc2x_b6_d1;
+ uint8_t f3bc3x_b6_d1;
+ uint8_t f3bc4x_b6_d1;
+ uint8_t f3bc5x_b6_d1;
+ uint8_t f3bc8x_b6_d1;
+ uint8_t f3bc9x_b6_d1;
+ uint8_t f3bcax_b6_d1;
+ uint8_t f3bcbx_b6_d1;
+ uint8_t f0bc2x_b7_d1;
+ uint8_t f0bc3x_b7_d1;
+ uint8_t f0bc4x_b7_d1;
+ uint8_t f0bc5x_b7_d1;
+ uint8_t f0bc8x_b7_d1;
+ uint8_t f0bc9x_b7_d1;
+ uint8_t f0bcax_b7_d1;
+ uint8_t f0bcbx_b7_d1;
+ uint8_t f1bc2x_b7_d1;
+ uint8_t f1bc3x_b7_d1;
+ uint8_t f1bc4x_b7_d1;
+ uint8_t f1bc5x_b7_d1;
+ uint8_t f1bc8x_b7_d1;
+ uint8_t f1bc9x_b7_d1;
+ uint8_t f1bcax_b7_d1;
+ uint8_t f1bcbx_b7_d1;
+ uint8_t f2bc2x_b7_d1;
+ uint8_t f2bc3x_b7_d1;
+ uint8_t f2bc4x_b7_d1;
+ uint8_t f2bc5x_b7_d1;
+ uint8_t f2bc8x_b7_d1;
+ uint8_t f2bc9x_b7_d1;
+ uint8_t f2bcax_b7_d1;
+ uint8_t f2bcbx_b7_d1;
+ uint8_t f3bc2x_b7_d1;
+ uint8_t f3bc3x_b7_d1;
+ uint8_t f3bc4x_b7_d1;
+ uint8_t f3bc5x_b7_d1;
+ uint8_t f3bc8x_b7_d1;
+ uint8_t f3bc9x_b7_d1;
+ uint8_t f3bcax_b7_d1;
+ uint8_t f3bcbx_b7_d1;
+ uint8_t f0bc2x_b8_d1;
+ uint8_t f0bc3x_b8_d1;
+ uint8_t f0bc4x_b8_d1;
+ uint8_t f0bc5x_b8_d1;
+ uint8_t f0bc8x_b8_d1;
+ uint8_t f0bc9x_b8_d1;
+ uint8_t f0bcax_b8_d1;
+ uint8_t f0bcbx_b8_d1;
+ uint8_t f1bc2x_b8_d1;
+ uint8_t f1bc3x_b8_d1;
+ uint8_t f1bc4x_b8_d1;
+ uint8_t f1bc5x_b8_d1;
+ uint8_t f1bc8x_b8_d1;
+ uint8_t f1bc9x_b8_d1;
+ uint8_t f1bcax_b8_d1;
+ uint8_t f1bcbx_b8_d1;
+ uint8_t f2bc2x_b8_d1;
+ uint8_t f2bc3x_b8_d1;
+ uint8_t f2bc4x_b8_d1;
+ uint8_t f2bc5x_b8_d1;
+ uint8_t f2bc8x_b8_d1;
+ uint8_t f2bc9x_b8_d1;
+ uint8_t f2bcax_b8_d1;
+ uint8_t f2bcbx_b8_d1;
+ uint8_t f3bc2x_b8_d1;
+ uint8_t f3bc3x_b8_d1;
+ uint8_t f3bc4x_b8_d1;
+ uint8_t f3bc5x_b8_d1;
+ uint8_t f3bc8x_b8_d1;
+ uint8_t f3bc9x_b8_d1;
+ uint8_t f3bcax_b8_d1;
+ uint8_t f3bcbx_b8_d1;
+ uint8_t f5bc5x_d1;
+ uint8_t f5bc6x_d1;
+ uint8_t f4bc8x_d1;
+ uint8_t f4bc9x_d1;
+ uint8_t f4bcax_d1;
+ uint8_t f4bcbx_d1;
+ uint8_t f4bccx_d1;
+ uint8_t f4bcdx_d1;
+ uint8_t f4bcex_d1;
+ uint8_t f4bcfx_d1;
+ uint8_t f5bc8x_d1;
+ uint8_t f5bc9x_d1;
+ uint8_t f5bcax_d1;
+ uint8_t f5bcbx_d1;
+ uint8_t f5bccx_d1;
+ uint8_t f5bcdx_d1;
+ uint8_t f5bcex_d1;
+ uint8_t f5bcfx_d1;
+ uint8_t f6bc8x_d1;
+ uint8_t f6bc9x_d1;
+ uint8_t f6bcax_d1;
+ uint8_t f6bcbx_d1;
+ uint8_t f6bccx_d1;
+ uint8_t f6bcdx_d1;
+ uint8_t f6bcex_d1;
+ uint8_t f6bcfx_d1;
+ uint8_t f7bc8x_d1;
+ uint8_t f7bc9x_d1;
+ uint8_t f7bcax_d1;
+ uint8_t f7bcbx_d1;
+ uint8_t f7bccx_d1;
+ uint8_t f7bcdx_d1;
+ uint8_t f7bcex_d1;
+ uint8_t f7bcfx_d1;
+ uint16_t alt_cas_l;
+ uint8_t alt_wcas_l;
+ uint8_t d4misc;
+} __packed;
+#endif
diff --git a/drivers/nxp/ddr/phy-gen2/ddrphy.mk b/drivers/nxp/ddr/phy-gen2/ddrphy.mk
new file mode 100644
index 0000000..ba5c774
--- /dev/null
+++ b/drivers/nxp/ddr/phy-gen2/ddrphy.mk
@@ -0,0 +1,20 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+#-----------------------------------------------------------------------------
+
+# SNPS ddr phy driver files
+
+DDR_PHY_C =
+DDR_PHY_H =
+
+$(DDR_PHY_C): $(DDR_PHY_H) $(COMMON_HDRS) src
+ @cp -r "$(DDR_PHY_PATH)/$@" "$(SRC_DIR)/$@"
+
+$(DDR_PHY_H): src
+ @cp -r "$(DDR_PHY_PATH)/$@" "$(SRC_DIR)/$@"
+
+#------------------------------------------------
diff --git a/drivers/nxp/ddr/phy-gen2/input.h b/drivers/nxp/ddr/phy-gen2/input.h
new file mode 100644
index 0000000..dbcd1ae
--- /dev/null
+++ b/drivers/nxp/ddr/phy-gen2/input.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2021 NXP
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _INPUT_H_
+#define _INPUT_H_
+
+enum dram_types {
+ DDR4,
+ DDR3,
+ LPDDR4,
+ LPDDR3,
+ LPDDR2,
+ DDR5,
+};
+
+enum dimm_types {
+ UDIMM,
+ SODIMM,
+ RDIMM,
+ LRDIMM,
+ NODIMM,
+};
+
+struct input_basic {
+ enum dram_types dram_type;
+ enum dimm_types dimm_type;
+ int lp4x_mode; /* 0x1 = lpddr4x mode, when dram_type is lpddr4
+ */
+ /* not used for protocols other than lpddr4 */
+ int num_dbyte; /* number of dbytes physically instantiated */
+ int num_active_dbyte_dfi0; /* number of active dbytes to be
+ * controlled by dfi0
+ */
+ int num_active_dbyte_dfi1; /* number of active dbytes to be
+ * controlled by dfi1. Not used for
+ * protocols other than lpddr3 and
+ * lpddr4
+ */
+ int num_anib; /* number of anibs physically instantiated */
+ int num_rank_dfi0; /* number of ranks in dfi0 channel */
+ int num_rank_dfi1; /* number of ranks in dfi1 channel */
+ int dram_data_width; /* 4,8,16 or 32 depending on protocol and dram
+ * type
+ */
+ int num_pstates;
+ int frequency; /* memclk frequency in mhz -- round up */
+ int pll_bypass; /* pll bypass enable */
+ int dfi_freq_ratio; /* selected dfi frequency ratio */
+ int dfi1exists; /* whether they phy config has dfi1 channel */
+ int train2d;
+ int hard_macro_ver;
+ int read_dbienable;
+ int dfi_mode; /* no longer used */
+};
+
+struct input_advanced {
+ int d4rx_preamble_length;
+ int d4tx_preamble_length;
+ int ext_cal_res_val; /* external pull-down resistor */
+ int is2ttiming;
+ int odtimpedance;
+ int tx_impedance;
+ int atx_impedance;
+ int mem_alert_en;
+ int mem_alert_puimp;
+ int mem_alert_vref_level;
+ int mem_alert_sync_bypass;
+ int dis_dyn_adr_tri;
+ int phy_mstr_train_interval;
+ int phy_mstr_max_req_to_ack;
+ int wdqsext;
+ int cal_interval;
+ int cal_once;
+ int dram_byte_swap;
+ int rx_en_back_off;
+ int train_sequence_ctrl;
+ int phy_gen2_umctl_opt;
+ int phy_gen2_umctl_f0rc5x;
+ int tx_slew_rise_dq;
+ int tx_slew_fall_dq;
+ int tx_slew_rise_ac;
+ int tx_slew_fall_ac;
+ int enable_high_clk_skew_fix;
+ int disable_unused_addr_lns;
+ int phy_init_sequence_num;
+ int cs_mode; /* rdimm */
+ int cast_cs_to_cid; /* rdimm */
+};
+
+struct input {
+ struct input_basic basic;
+ struct input_advanced adv;
+ unsigned int mr[7];
+ unsigned int cs_d0;
+ unsigned int cs_d1;
+ unsigned int mirror;
+ unsigned int odt[4];
+ unsigned int rcw[16];
+ unsigned int rcw3x;
+ unsigned int vref;
+};
+
+#endif
diff --git a/drivers/nxp/ddr/phy-gen2/messages.h b/drivers/nxp/ddr/phy-gen2/messages.h
new file mode 100644
index 0000000..7dec7df
--- /dev/null
+++ b/drivers/nxp/ddr/phy-gen2/messages.h
@@ -0,0 +1,2909 @@
+/*
+ * Copyright 2021 NXP
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef MESSAGE_H
+#define MESSAGE_H
+
+#ifdef DEBUG
+struct phy_msg {
+ uint32_t index;
+ const char *msg;
+};
+
+const static struct phy_msg messages_1d[] = {
+ {0x00000001,
+ "PMU1:prbsGenCtl:%x\n"
+ },
+ {0x00010000,
+ "PMU1: loading 2D acsm sequence\n"
+ },
+ {0x00020000,
+ "PMU1: loading 1D acsm sequence\n"
+ },
+ {0x00030002,
+ "PMU3: %d memclocks @ %d to get half of 300ns\n"
+ },
+ {0x00040000,
+ "PMU: Error: User requested MPR read pattern for read DQS training in DDR3 Mode\n"
+ },
+ {0x00050000,
+ "PMU3: Running 1D search for left eye edge\n"
+ },
+ {0x00060001,
+ "PMU1: In Phase Left Edge Search cs %d\n"
+ },
+ {0x00070001,
+ "PMU1: Out of Phase Left Edge Search cs %d\n"
+ },
+ {0x00080000,
+ "PMU3: Running 1D search for right eye edge\n"
+ },
+ {0x00090001,
+ "PMU1: In Phase Right Edge Search cs %d\n"
+ },
+ {0x000a0001,
+ "PMU1: Out of Phase Right Edge Search cs %d\n"
+ },
+ {0x000b0001,
+ "PMU1: mxRdLat training pstate %d\n"
+ },
+ {0x000c0001,
+ "PMU1: mxRdLat search for cs %d\n"
+ },
+ {0x000d0001,
+ "PMU0: MaxRdLat non consistent DtsmLoThldXingInd 0x%03x\n"
+ },
+ {0x000e0003,
+ "PMU4: CS %d Dbyte %d worked with DFIMRL = %d DFICLKs\n"
+ },
+ {0x000f0004,
+ "PMU3: MaxRdLat Read Lane err mask for csn %d, DFIMRL %2d DFIClks, dbyte %d = 0x%03x\n"
+ },
+ {0x00100003,
+ "PMU3: MaxRdLat Read Lane err mask for csn %d DFIMRL %2d, All dbytes = 0x%03x\n"
+ },
+ {0x00110001,
+ "PMU: Error: CS%d failed to find a DFIMRL setting that worked for all bytes during MaxRdLat training\n"
+ },
+ {0x00120002,
+ "PMU3: Smallest passing DFIMRL for all dbytes in CS%d = %d DFIClks\n"
+ },
+ {0x00130000,
+ "PMU: Error: No passing DFIMRL value found for any chip select during MaxRdLat training\n"
+ },
+ {0x00140003,
+ "PMU: Error: Dbyte %d lane %d txDqDly passing region is too small (width = %d)\n"
+ },
+ {0x00150006,
+ "PMU10: Adjusting rxclkdly db %d nib %d from %d+%d=%d->%d\n"
+ },
+ {0x00160000,
+ "PMU4: TxDqDly Passing Regions (EyeLeft EyeRight -> EyeCenter) Units=1/32 UI\n"
+ },
+ {0x00170005,
+ "PMU4: DB %d Lane %d: %3d %3d -> %3d\n"
+ },
+ {0x00180002,
+ "PMU2: TXDQ delayLeft[%2d] = %3d (DISCONNECTED)\n"
+ },
+ {0x00190004,
+ "PMU2: TXDQ delayLeft[%2d] = %3d oopScaled = %3d selectOop %d\n"
+ },
+ {0x001a0002,
+ "PMU2: TXDQ delayRight[%2d] = %3d (DISCONNECTED)\n"
+ },
+ {0x001b0004,
+ "PMU2: TXDQ delayRight[%2d] = %3d oopScaled = %3d selectOop %d\n"
+ },
+ {0x001c0003,
+ "PMU: Error: Dbyte %d lane %d txDqDly passing region is too small (width = %d)\n"
+ },
+ {0x001d0000,
+ "PMU4: TxDqDly Passing Regions (EyeLeft EyeRight -> EyeCenter) Units=1/32 UI\n"
+ },
+ {0x001e0002,
+ "PMU4: DB %d Lane %d: (DISCONNECTED)\n"
+ },
+ {0x001f0005,
+ "PMU4: DB %d Lane %d: %3d %3d -> %3d\n"
+ },
+ {0x00200002,
+ "PMU3: Running 1D search csn %d for DM Right/NotLeft(%d) eye edge\n"
+ },
+ {0x00210002,
+ "PMU3: WrDq DM byte%2d with Errcnt %d\n"
+ },
+ {0x00220002,
+ "PMU3: WrDq DM byte%2d avgDly 0x%04x\n"
+ },
+ {0x00230002,
+ "PMU1: WrDq DM byte%2d with Errcnt %d\n"
+ },
+ {0x00240001,
+ "PMU: Error: Dbyte %d txDqDly DM training did not start inside the eye\n"
+ },
+ {0x00250000,
+ "PMU4: DM TxDqDly Passing Regions (EyeLeft EyeRight -> EyeCenter) Units=1/32 UI\n"
+ },
+ {0x00260002,
+ "PMU4: DB %d Lane %d: (DISCONNECTED)\n"
+ },
+ {0x00270005,
+ "PMU4: DB %d Lane %d: %3d %3d -> %3d\n"
+ },
+ {0x00280003,
+ "PMU: Error: Dbyte %d lane %d txDqDly DM passing region is too small (width = %d)\n"
+ },
+ {0x00290004,
+ "PMU3: Errcnt for MRD/MWD search nib %2d delay = (%d, 0x%02x) = %d\n"
+ },
+ {0x002a0000,
+ "PMU3: Precharge all open banks\n"
+ },
+ {0x002b0002,
+ "PMU: Error: Dbyte %d nibble %d found mutliple working coarse delay setting for MRD/MWD\n"
+ },
+ {0x002c0000,
+ "PMU4: MRD Passing Regions (coarseVal, fineLeft fineRight -> fineCenter)\n"
+ },
+ {0x002d0000,
+ "PMU4: MWD Passing Regions (coarseVal, fineLeft fineRight -> fineCenter)\n"
+ },
+ {0x002e0004,
+ "PMU10: Warning: DB %d nibble %d has multiple working coarse delays, %d and %d, choosing the smaller delay\n"
+ },
+ {0x002f0003,
+ "PMU: Error: Dbyte %d nibble %d MRD/MWD passing region is too small (width = %d)\n"
+ },
+ {0x00300006,
+ "PMU4: DB %d nibble %d: %3d, %3d %3d -> %3d\n"
+ },
+ {0x00310002,
+ "PMU1: Start MRD/nMWD %d for csn %d\n"
+ },
+ {0x00320002,
+ "PMU2: RXDQS delayLeft[%2d] = %3d (DISCONNECTED)\n"
+ },
+ {0x00330006,
+ "PMU2: RXDQS delayLeft[%2d] = %3d delayOop[%2d] = %3d OopScaled %4d, selectOop %d\n"
+ },
+ {0x00340002,
+ "PMU2: RXDQS delayRight[%2d] = %3d (DISCONNECTED)\n"
+ },
+ {0x00350006,
+ "PMU2: RXDQS delayRight[%2d] = %3d delayOop[%2d] = %4d OopScaled %4d, selectOop %d\n"
+ },
+ {0x00360000,
+ "PMU4: RxClkDly Passing Regions (EyeLeft EyeRight -> EyeCenter)\n"
+ },
+ {0x00370002,
+ "PMU4: DB %d nibble %d: (DISCONNECTED)\n"
+ },
+ {0x00380005,
+ "PMU4: DB %d nibble %d: %3d %3d -> %3d\n"
+ },
+ {0x00390003,
+ "PMU: Error: Dbyte %d nibble %d rxClkDly passing region is too small (width = %d)\n"
+ },
+ {0x003a0002,
+ "PMU0: goodbar = %d for RDWR_BLEN %d\n"
+ },
+ {0x003b0001,
+ "PMU3: RxClkDly = %d\n"
+ },
+ {0x003c0005,
+ "PMU0: db %d l %d absLane %d -> bottom %d top %d\n"
+ },
+ {0x003d0009,
+ "PMU3: BYTE %d - %3d %3d %3d %3d %3d %3d %3d %3d\n"
+ },
+ {0x003e0002,
+ "PMU: Error: dbyte %d lane %d's per-lane vrefDAC's had no passing region\n"
+ },
+ {0x003f0004,
+ "PMU0: db%d l%d - %d %d\n"
+ },
+ {0x00400002,
+ "PMU0: goodbar = %d for RDWR_BLEN %d\n"
+ },
+ {0x00410004,
+ "PMU3: db%d l%d saw %d issues at rxClkDly %d\n"
+ },
+ {0x00420003,
+ "PMU3: db%d l%d first saw a pass->fail edge at rxClkDly %d\n"
+ },
+ {0x00430002,
+ "PMU3: lane %d PBD = %d\n"
+ },
+ {0x00440003,
+ "PMU3: db%d l%d first saw a DBI pass->fail edge at rxClkDly %d\n"
+ },
+ {0x00450003,
+ "PMU2: db%d l%d already passed rxPBD = %d\n"
+ },
+ {0x00460003,
+ "PMU0: db%d l%d, PBD = %d\n"
+ },
+ {0x00470002,
+ "PMU: Error: dbyte %d lane %d failed read deskew\n"
+ },
+ {0x00480003,
+ "PMU0: db%d l%d, inc PBD = %d\n"
+ },
+ {0x00490003,
+ "PMU1: Running lane deskew on pstate %d csn %d rdDBIEn %d\n"
+ },
+ {0x004a0000,
+ "PMU: Error: Read deskew training has been requested, but csrMajorModeDbyte[2] is set\n"
+ },
+ {0x004b0002,
+ "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
+ },
+ {0x004c0002,
+ "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
+ },
+ {0x004d0001,
+ "PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D3U Type\n"
+ },
+ {0x004e0001,
+ "PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D3R Type\n"
+ },
+ {0x004f0001,
+ "PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D4U Type\n"
+ },
+ {0x00500001,
+ "PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D4R Type\n"
+ },
+ {0x00510001,
+ "PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D4LR Type\n"
+ },
+ {0x00520000,
+ "PMU: Error: Both 2t timing mode and ddr4 geardown mode specified in the messageblock's PhyCfg and MR3 fields. Only one can be enabled\n"
+ },
+ {0x00530003,
+ "PMU10: PHY TOTALS - NUM_DBYTES %d NUM_NIBBLES %d NUM_ANIBS %d\n"
+ },
+ {0x00540006,
+ "PMU10: CSA=0x%02x, CSB=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, MMISC=%d DRAMFreq=%dMT DramType=LPDDR3\n"
+ },
+ {0x00550006,
+ "PMU10: CSA=0x%02x, CSB=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, MMISC=%d DRAMFreq=%dMT DramType=LPDDR4\n"
+ },
+ {0x00560008,
+ "PMU10: CS=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, 2T=%d, MMISC=%d AddrMirror=%d DRAMFreq=%dMT DramType=%d\n"
+ },
+ {0x00570004,
+ "PMU10: Pstate%d MR0=0x%04x MR1=0x%04x MR2=0x%04x\n"
+ },
+ {0x00580008,
+ "PMU10: Pstate%d MRS MR0=0x%04x MR1=0x%04x MR2=0x%04x MR3=0x%04x MR4=0x%04x MR5=0x%04x MR6=0x%04x\n"
+ },
+ {0x00590005,
+ "PMU10: Pstate%d MRS MR1_A0=0x%04x MR2_A0=0x%04x MR3_A0=0x%04x MR11_A0=0x%04x\n"
+ },
+ {0x005a0000,
+ "PMU10: UseBroadcastMR set. All ranks and channels use MRXX_A0 for MR settings.\n"
+ },
+ {0x005b0005,
+ "PMU10: Pstate%d MRS MR01_A0=0x%02x MR02_A0=0x%02x MR03_A0=0x%02x MR11_A0=0x%02x\n"
+ },
+ {0x005c0005,
+ "PMU10: Pstate%d MRS MR12_A0=0x%02x MR13_A0=0x%02x MR14_A0=0x%02x MR22_A0=0x%02x\n"
+ },
+ {0x005d0005,
+ "PMU10: Pstate%d MRS MR01_A1=0x%02x MR02_A1=0x%02x MR03_A1=0x%02x MR11_A1=0x%02x\n"
+ },
+ {0x005e0005,
+ "PMU10: Pstate%d MRS MR12_A1=0x%02x MR13_A1=0x%02x MR14_A1=0x%02x MR22_A1=0x%02x\n"
+ },
+ {0x005f0005,
+ "PMU10: Pstate%d MRS MR01_B0=0x%02x MR02_B0=0x%02x MR03_B0=0x%02x MR11_B0=0x%02x\n"
+ },
+ {0x00600005,
+ "PMU10: Pstate%d MRS MR12_B0=0x%02x MR13_B0=0x%02x MR14_B0=0x%02x MR22_B0=0x%02x\n"
+ },
+ {0x00610005,
+ "PMU10: Pstate%d MRS MR01_B1=0x%02x MR02_B1=0x%02x MR03_B1=0x%02x MR11_B1=0x%02x\n"
+ },
+ {0x00620005,
+ "PMU10: Pstate%d MRS MR12_B1=0x%02x MR13_B1=0x%02x MR14_B1=0x%02x MR22_B1=0x%02x\n"
+ },
+ {0x00630002,
+ "PMU1: AcsmOdtCtrl%02d 0x%02x\n"
+ },
+ {0x00640002,
+ "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
+ },
+ {0x00650002,
+ "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
+ },
+ {0x00660000,
+ "PMU1: HwtCAMode set\n"
+ },
+ {0x00670001,
+ "PMU3: DDR4 infinite preamble enter/exit mode %d\n"
+ },
+ {0x00680002,
+ "PMU1: In rxenb_train() csn=%d pstate=%d\n"
+ },
+ {0x00690000,
+ "PMU3: Finding DQS falling edge\n"
+ },
+ {0x006a0000,
+ "PMU3: Searching for DDR3/LPDDR3/LPDDR4 read preamble\n"
+ },
+ {0x006b0009,
+ "PMU3: dtsm fails Even Nibbles : %2x %2x %2x %2x %2x %2x %2x %2x %2x\n"
+ },
+ {0x006c0009,
+ "PMU3: dtsm fails Odd Nibbles : %2x %2x %2x %2x %2x %2x %2x %2x %2x\n"
+ },
+ {0x006d0002,
+ "PMU3: Preamble search pass=%d anyfail=%d\n"
+ },
+ {0x006e0000,
+ "PMU: Error: RxEn training preamble not found\n"
+ },
+ {0x006f0000,
+ "PMU3: Found DQS pre-amble\n"
+ },
+ {0x00700001,
+ "PMU: Error: Dbyte %d couldn't find the rising edge of DQS during RxEn Training\n"
+ },
+ {0x00710000,
+ "PMU3: RxEn aligning to first rising edge of burst\n"
+ },
+ {0x00720001,
+ "PMU3: Decreasing RxEn delay by %d fine step to allow full capture of reads\n"
+ },
+ {0x00730001,
+ "PMU3: MREP Delay = %d\n"
+ },
+ {0x00740003,
+ "PMU3: Errcnt for MREP nib %2d delay = %2d is %d\n"
+ },
+ {0x00750002,
+ "PMU3: MREP nibble %d sampled a 1 at data buffer delay %d\n"
+ },
+ {0x00760002,
+ "PMU3: MREP nibble %d saw a 0 to 1 transition at data buffer delay %d\n"
+ },
+ {0x00770000,
+ "PMU2: MREP did not find a 0 to 1 transition for all nibbles. Failing nibbles assumed to have rising edge close to fine delay 63\n"
+ },
+ {0x00780002,
+ "PMU2: Rising edge found in alias window, setting rxDly for nibble %d = %d\n"
+ },
+ {0x00790002,
+ "PMU: Error: Failed MREP for nib %d with %d one\n"
+ },
+ {0x007a0003,
+ "PMU2: Rising edge not found in alias window with %d one, leaving rxDly for nibble %d = %d\n"
+ },
+ {0x007b0002,
+ "PMU3: Training DIMM %d CSn %d\n"
+ },
+ {0x007c0001,
+ "PMU3: exitCAtrain_lp3 cs 0x%x\n"
+ },
+ {0x007d0001,
+ "PMU3: enterCAtrain_lp3 cs 0x%x\n"
+ },
+ {0x007e0001,
+ "PMU3: CAtrain_switchmsb_lp3 cs 0x%x\n"
+ },
+ {0x007f0001,
+ "PMU3: CATrain_rdwr_lp3 looking for pattern %x\n"
+ },
+ {0x00800000,
+ "PMU3: exitCAtrain_lp4\n"
+ },
+ {0x00810001,
+ "PMU3: DEBUG enterCAtrain_lp4 1: cs 0x%x\n"
+ },
+ {0x00820001,
+ "PMU3: DEBUG enterCAtrain_lp4 3: Put dbyte %d in async mode\n"
+ },
+ {0x00830000,
+ "PMU3: DEBUG enterCAtrain_lp4 5: Send MR13 to turn on CA training\n"
+ },
+ {0x00840003,
+ "PMU3: DEBUG enterCAtrain_lp4 7: idx = %d vref = %x mr12 = %x\n"
+ },
+ {0x00850001,
+ "PMU3: CATrain_rdwr_lp4 looking for pattern %x\n"
+ },
+ {0x00860004,
+ "PMU3: Phase %d CAreadbackA db:%d %x xo:%x\n"
+ },
+ {0x00870005,
+ "PMU3: DEBUG lp4SetCatrVref 1: cs=%d chan=%d mr12=%x vref=%d.%d%%\n"
+ },
+ {0x00880003,
+ "PMU3: DEBUG lp4SetCatrVref 3: mr12 = %x send vref= %x to db=%d\n"
+ },
+ {0x00890000,
+ "PMU10:Optimizing vref\n"
+ },
+ {0x008a0004,
+ "PMU4:mr12:%2x cs:%d chan %d r:%4x\n"
+ },
+ {0x008b0005,
+ "PMU3: i:%2d bstr:%2d bsto:%2d st:%d r:%d\n"
+ },
+ {0x008c0002,
+ "Failed to find sufficient CA Vref Passing Region for CS %d ch. %d\n"
+ },
+ {0x008d0005,
+ "PMU3:Found %d.%d%% MR12:%x for cs:%d chan %d\n"
+ },
+ {0x008e0002,
+ "PMU3:Calculated %d for AtxImpedence from acx %d.\n"
+ },
+ {0x008f0000,
+ "PMU3:CA Odt impedence ==0. Use default vref.\n"
+ },
+ {0x00900003,
+ "PMU3:Calculated %d.%d%% for Vref MR12=0x%x.\n"
+ },
+ {0x00910000,
+ "PMU3: CAtrain_lp\n"
+ },
+ {0x00920000,
+ "PMU3: CAtrain Begins.\n"
+ },
+ {0x00930001,
+ "PMU3: CAtrain_lp testing dly %d\n"
+ },
+ {0x00940001,
+ "PMU5: CA bitmap dump for cs %x\n"
+ },
+ {0x00950001,
+ "PMU5: CAA%d "
+ },
+ {0x00960001, "%02x"
+ },
+ {0x00970000, "\n"
+ },
+ {0x00980001,
+ "PMU5: CAB%d "
+ },
+ {0x00990001, "%02x"
+ },
+ {0x009a0000, "\n"
+ },
+ {0x009b0003,
+ "PMU3: anibi=%d, anibichan[anibi]=%d ,chan=%d\n"
+ },
+ {0x009c0001, "%02x"
+ },
+ {0x009d0001, "\nPMU3:Raw CA setting :%x"
+ },
+ {0x009e0002, "\nPMU3:ATxDly setting:%x margin:%d\n"
+ },
+ {0x009f0002, "\nPMU3:InvClk ATxDly setting:%x margin:%d\n"
+ },
+ {0x00a00000, "\nPMU3:No Range found!\n"
+ },
+ {0x00a10003,
+ "PMU3: 2 anibi=%d, anibichan[anibi]=%d ,chan=%d"
+ },
+ {0x00a20002, "\nPMU3: no neg clock => CA setting anib=%d, :%d\n"
+ },
+ {0x00a30001,
+ "PMU3:Normal margin:%d\n"
+ },
+ {0x00a40001,
+ "PMU3:Inverted margin:%d\n"
+ },
+ {0x00a50000,
+ "PMU3:Using Inverted clock\n"
+ },
+ {0x00a60000,
+ "PMU3:Using normal clk\n"
+ },
+ {0x00a70003,
+ "PMU3: 3 anibi=%d, anibichan[anibi]=%d ,chan=%d\n"
+ },
+ {0x00a80002,
+ "PMU3: Setting ATxDly for anib %x to %x\n"
+ },
+ {0x00a90000,
+ "PMU: Error: CA Training Failed.\n"
+ },
+ {0x00aa0000,
+ "PMU1: Writing MRs\n"
+ },
+ {0x00ab0000,
+ "PMU4:Using MR12 values from 1D CA VREF training.\n"
+ },
+ {0x00ac0000,
+ "PMU3:Writing all MRs to fsp 1\n"
+ },
+ {0x00ad0000,
+ "PMU10:Lp4Quickboot mode.\n"
+ },
+ {0x00ae0000,
+ "PMU3: Writing MRs\n"
+ },
+ {0x00af0001,
+ "PMU10: Setting boot clock divider to %d\n"
+ },
+ {0x00b00000,
+ "PMU3: Resetting DRAM\n"
+ },
+ {0x00b10000,
+ "PMU3: setup for RCD initalization\n"
+ },
+ {0x00b20000,
+ "PMU3: pmu_exit_SR from dev_init()\n"
+ },
+ {0x00b30000,
+ "PMU3: initializing RCD\n"
+ },
+ {0x00b40000,
+ "PMU10: **** Executing 2D Image ****\n"
+ },
+ {0x00b50001,
+ "PMU10: **** Start DDR4 Training. PMU Firmware Revision 0x%04x ****\n"
+ },
+ {0x00b60001,
+ "PMU10: **** Start DDR3 Training. PMU Firmware Revision 0x%04x ****\n"
+ },
+ {0x00b70001,
+ "PMU10: **** Start LPDDR3 Training. PMU Firmware Revision 0x%04x ****\n"
+ },
+ {0x00b80001,
+ "PMU10: **** Start LPDDR4 Training. PMU Firmware Revision 0x%04x ****\n"
+ },
+ {0x00b90000,
+ "PMU: Error: Mismatched internal revision between DCCM and ICCM images\n"
+ },
+ {0x00ba0001,
+ "PMU10: **** Testchip %d Specific Firmware ****\n"
+ },
+ {0x00bb0000,
+ "PMU1: LRDIMM with EncodedCS mode, one DIMM\n"
+ },
+ {0x00bc0000,
+ "PMU1: LRDIMM with EncodedCS mode, two DIMMs\n"
+ },
+ {0x00bd0000,
+ "PMU1: RDIMM with EncodedCS mode, one DIMM\n"
+ },
+ {0x00be0000,
+ "PMU2: Starting LRDIMM MREP training for all ranks\n"
+ },
+ {0x00bf0000,
+ "PMU199: LRDIMM MREP training for all ranks completed\n"
+ },
+ {0x00c00000,
+ "PMU2: Starting LRDIMM DWL training for all ranks\n"
+ },
+ {0x00c10000,
+ "PMU199: LRDIMM DWL training for all ranks completed\n"
+ },
+ {0x00c20000,
+ "PMU2: Starting LRDIMM MRD training for all ranks\n"
+ },
+ {0x00c30000,
+ "PMU199: LRDIMM MRD training for all ranks completed\n"
+ },
+ {0x00c40000,
+ "PMU2: Starting RXEN training for all ranks\n"
+ },
+ {0x00c50000,
+ "PMU2: Starting write leveling fine delay training for all ranks\n"
+ },
+ {0x00c60000,
+ "PMU2: Starting LRDIMM MWD training for all ranks\n"
+ },
+ {0x00c70000,
+ "PMU199: LRDIMM MWD training for all ranks completed\n"
+ },
+ {0x00c80000,
+ "PMU2: Starting write leveling fine delay training for all ranks\n"
+ },
+ {0x00c90000,
+ "PMU2: Starting read deskew training\n"
+ },
+ {0x00ca0000,
+ "PMU2: Starting SI friendly 1d RdDqs training for all ranks\n"
+ },
+ {0x00cb0000,
+ "PMU2: Starting write leveling coarse delay training for all ranks\n"
+ },
+ {0x00cc0000,
+ "PMU2: Starting 1d WrDq training for all ranks\n"
+ },
+ {0x00cd0000,
+ "PMU2: Running DQS2DQ Oscillator for all ranks\n"
+ },
+ {0x00ce0000,
+ "PMU2: Starting again read deskew training but with PRBS\n"
+ },
+ {0x00cf0000,
+ "PMU2: Starting 1d RdDqs training for all ranks\n"
+ },
+ {0x00d00000,
+ "PMU2: Starting again 1d WrDq training for all ranks\n"
+ },
+ {0x00d10000,
+ "PMU2: Starting MaxRdLat training\n"
+ },
+ {0x00d20000,
+ "PMU2: Starting 2d WrDq training for all ranks\n"
+ },
+ {0x00d30000,
+ "PMU2: Starting 2d RdDqs training for all ranks\n"
+ },
+ {0x00d40002,
+ "PMU3:read_fifo %x %x\n"
+ },
+ {0x00d50001,
+ "PMU: Error: Invalid PhyDrvImpedance of 0x%x specified in message block.\n"
+ },
+ {0x00d60001,
+ "PMU: Error: Invalid PhyOdtImpedance of 0x%x specified in message block.\n"
+ },
+ {0x00d70001,
+ "PMU: Error: Invalid BPZNResVal of 0x%x specified in message block.\n"
+ },
+ {0x00d80005,
+ "PMU3: fixRxEnBackOff csn:%d db:%d dn:%d bo:%d dly:%x\n"
+ },
+ {0x00d90001,
+ "PMU3: fixRxEnBackOff dly:%x\n"
+ },
+ {0x00da0000,
+ "PMU3: Entering setupPpt\n"
+ },
+ {0x00db0000,
+ "PMU3: Start lp4PopulateHighLowBytes\n"
+ },
+ {0x00dc0002,
+ "PMU3:Dbyte Detect: db%d received %x\n"
+ },
+ {0x00dd0002,
+ "PMU3:getDqs2Dq read %x from dbyte %d\n"
+ },
+ {0x00de0002,
+ "PMU3:getDqs2Dq(2) read %x from dbyte %d\n"
+ },
+ {0x00df0001,
+ "PMU: Error: Dbyte %d read 0 from the DQS oscillator it is connected to\n"
+ },
+ {0x00e00002,
+ "PMU4: Dbyte %d dqs2dq = %d/32 UI\n"
+ },
+ {0x00e10003,
+ "PMU3:getDqs2Dq set dqs2dq:%d/32 ui (%d ps) from dbyte %d\n"
+ },
+ {0x00e20003,
+ "PMU3: Setting coarse delay in AtxDly chiplet %d from 0x%02x to 0x%02x\n"
+ },
+ {0x00e30003,
+ "PMU3: Clearing coarse delay in AtxDly chiplet %d from 0x%02x to 0x%02x\n"
+ },
+ {0x00e40000,
+ "PMU3: Performing DDR4 geardown sync sequence\n"
+ },
+ {0x00e50000,
+ "PMU1: Enter self refresh\n"
+ },
+ {0x00e60000,
+ "PMU1: Exit self refresh\n"
+ },
+ {0x00e70000,
+ "PMU: Error: No dbiEnable with lp4\n"
+ },
+ {0x00e80000,
+ "PMU: Error: No dbiDisable with lp4\n"
+ },
+ {0x00e90001,
+ "PMU1: DDR4 update Rx DBI Setting disable %d\n"
+ },
+ {0x00ea0001,
+ "PMU1: DDR4 update 2nCk WPre Setting disable %d\n"
+ },
+ {0x00eb0005,
+ "PMU1: read_delay: db%d lane%d delays[%2d] = 0x%02x (max 0x%02x)\n"
+ },
+ {0x00ec0004,
+ "PMU1: write_delay: db%d lane%d delays[%2d] = 0x%04x\n"
+ },
+ {0x00ed0001,
+ "PMU5: ID=%d -- db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 --\n"
+ },
+ {0x00ee000b,
+ "PMU5: [%d]:0x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n"
+ },
+ {0x00ef0003,
+ "PMU2: dump delays - pstate=%d dimm=%d csn=%d\n"
+ },
+ {0x00f00000,
+ "PMU3: Printing Mid-Training Delay Information\n"
+ },
+ {0x00f10001,
+ "PMU5: CS%d <<KEY>> 0 TrainingCntr <<KEY>> coarse(15:10) fine(9:0)\n"
+ },
+ {0x00f20001,
+ "PMU5: CS%d <<KEY>> 0 RxEnDly, 1 RxClkDly <<KEY>> coarse(10:6) fine(5:0)\n"
+ },
+ {0x00f30001,
+ "PMU5: CS%d <<KEY>> 0 TxDqsDly, 1 TxDqDly <<KEY>> coarse(9:6) fine(5:0)\n"
+ },
+ {0x00f40001,
+ "PMU5: CS%d <<KEY>> 0 RxPBDly <<KEY>> 1 Delay Unit ~= 7ps\n"
+ },
+ {0x00f50000,
+ "PMU5: all CS <<KEY>> 0 DFIMRL <<KEY>> Units = DFI clocks\n"
+ },
+ {0x00f60000,
+ "PMU5: all CS <<KEY>> VrefDACs <<KEY>> DAC(6:0)\n"
+ },
+ {0x00f70000,
+ "PMU1: Set DMD in MR13 and wrDBI in MR3 for training\n"
+ },
+ {0x00f80000,
+ "PMU: Error: getMaxRxen() failed to find largest rxen nibble delay\n"
+ },
+ {0x00f90003,
+ "PMU2: getMaxRxen(): maxDly %d maxTg %d maxNib %d\n"
+ },
+ {0x00fa0003,
+ "PMU2: getRankMaxRxen(): maxDly %d Tg %d maxNib %d\n"
+ },
+ {0x00fb0000,
+ "PMU1: skipping CDD calculation in 2D image\n"
+ },
+ {0x00fc0001,
+ "PMU3: Calculating CDDs for pstate %d\n"
+ },
+ {0x00fd0003,
+ "PMU3: rxFromDly[%d][%d] = %d\n"
+ },
+ {0x00fe0003,
+ "PMU3: rxToDly [%d][%d] = %d\n"
+ },
+ {0x00ff0003,
+ "PMU3: rxDly [%d][%d] = %d\n"
+ },
+ {0x01000003,
+ "PMU3: txDly [%d][%d] = %d\n"
+ },
+ {0x01010003,
+ "PMU3: allFine CDD_RR_%d_%d = %d\n"
+ },
+ {0x01020003,
+ "PMU3: allFine CDD_WW_%d_%d = %d\n"
+ },
+ {0x01030003,
+ "PMU3: CDD_RR_%d_%d = %d\n"
+ },
+ {0x01040003,
+ "PMU3: CDD_WW_%d_%d = %d\n"
+ },
+ {0x01050003,
+ "PMU3: allFine CDD_RW_%d_%d = %d\n"
+ },
+ {0x01060003,
+ "PMU3: allFine CDD_WR_%d_%d = %d\n"
+ },
+ {0x01070003,
+ "PMU3: CDD_RW_%d_%d = %d\n"
+ },
+ {0x01080003,
+ "PMU3: CDD_WR_%d_%d = %d\n"
+ },
+ {0x01090004,
+ "PMU3: F%dBC2x_B%d_D%d = 0x%02x\n"
+ },
+ {0x010a0004,
+ "PMU3: F%dBC3x_B%d_D%d = 0x%02x\n"
+ },
+ {0x010b0004,
+ "PMU3: F%dBC4x_B%d_D%d = 0x%02x\n"
+ },
+ {0x010c0004,
+ "PMU3: F%dBC5x_B%d_D%d = 0x%02x\n"
+ },
+ {0x010d0004,
+ "PMU3: F%dBC8x_B%d_D%d = 0x%02x\n"
+ },
+ {0x010e0004,
+ "PMU3: F%dBC9x_B%d_D%d = 0x%02x\n"
+ },
+ {0x010f0004,
+ "PMU3: F%dBCAx_B%d_D%d = 0x%02x\n"
+ },
+ {0x01100004,
+ "PMU3: F%dBCBx_B%d_D%d = 0x%02x\n"
+ },
+ {0x01110000,
+ "PMU10: Entering context_switch_postamble\n"
+ },
+ {0x01120003,
+ "PMU10: context_switch_postamble is enabled for DIMM %d, RC0A=0x%x, RC3x=0x%x\n"
+ },
+ {0x01130000,
+ "PMU10: Setting bcw fspace 0\n"
+ },
+ {0x01140001,
+ "PMU10: Sending BC0A = 0x%x\n"
+ },
+ {0x01150001,
+ "PMU10: Sending BC6x = 0x%x\n"
+ },
+ {0x01160001,
+ "PMU10: Sending RC0A = 0x%x\n"
+ },
+ {0x01170001,
+ "PMU10: Sending RC3x = 0x%x\n"
+ },
+ {0x01180001,
+ "PMU10: Sending RC0A = 0x%x\n"
+ },
+ {0x01190001,
+ "PMU1: enter_lp3: DEBUG: pstate = %d\n"
+ },
+ {0x011a0001,
+ "PMU1: enter_lp3: DEBUG: dfifreqxlat_pstate = %d\n"
+ },
+ {0x011b0001,
+ "PMU1: enter_lp3: DEBUG: pllbypass = %d\n"
+ },
+ {0x011c0001,
+ "PMU1: enter_lp3: DEBUG: forcecal = %d\n"
+ },
+ {0x011d0001,
+ "PMU1: enter_lp3: DEBUG: pllmaxrange = 0x%x\n"
+ },
+ {0x011e0001,
+ "PMU1: enter_lp3: DEBUG: dacval_out = 0x%x\n"
+ },
+ {0x011f0001,
+ "PMU1: enter_lp3: DEBUG: pllctrl3 = 0x%x\n"
+ },
+ {0x01200000,
+ "PMU3: Loading DRAM with BIOS supplied MR values and entering self refresh prior to exiting PMU code.\n"
+ },
+ {0x01210002,
+ "PMU3: Setting DataBuffer function space of dimmcs 0x%02x to %d\n"
+ },
+ {0x01220002,
+ "PMU4: Setting RCW FxRC%Xx = 0x%02x\n"
+ },
+ {0x01230002,
+ "PMU4: Setting RCW FxRC%02x = 0x%02x\n"
+ },
+ {0x01240001,
+ "PMU1: DDR4 update Rd Pre Setting disable %d\n"
+ },
+ {0x01250002,
+ "PMU2: Setting BCW FxBC%Xx = 0x%02x\n"
+ },
+ {0x01260002,
+ "PMU2: Setting BCW BC%02x = 0x%02x\n"
+ },
+ {0x01270002,
+ "PMU2: Setting BCW PBA mode FxBC%Xx = 0x%02x\n"
+ },
+ {0x01280002,
+ "PMU2: Setting BCW PBA mode BC%02x = 0x%02x\n"
+ },
+ {0x01290003,
+ "PMU4: BCW value for dimm %d, fspace %d, addr 0x%04x\n"
+ },
+ {0x012a0002,
+ "PMU4: DB %d, value 0x%02x\n"
+ },
+ {0x012b0000,
+ "PMU6: WARNING MREP underflow, set to min value -2 coarse, 0 fine\n"
+ },
+ {0x012c0004,
+ "PMU6: LRDIMM Writing final data buffer fine delay value nib %2d, trainDly %3d, fineDly code %2d, new MREP fine %2d\n"
+ },
+ {0x012d0003,
+ "PMU6: LRDIMM Writing final data buffer fine delay value nib %2d, trainDly %3d, fineDly code %2d\n"
+ },
+ {0x012e0003,
+ "PMU6: LRDIMM Writing data buffer fine delay type %d nib %2d, code %2d\n"
+ },
+ {0x012f0002,
+ "PMU6: Writing final data buffer coarse delay value dbyte %2d, coarse = 0x%02x\n"
+ },
+ {0x01300003,
+ "PMU4: data 0x%04x at MB addr 0x%08x saved at CSR addr 0x%08x\n"
+ },
+ {0x01310003,
+ "PMU4: data 0x%04x at MB addr 0x%08x restored from CSR addr 0x%08x\n"
+ },
+ {0x01320003,
+ "PMU4: data 0x%04x at MB addr 0x%08x saved at CSR addr 0x%08x\n"
+ },
+ {0x01330003,
+ "PMU4: data 0x%04x at MB addr 0x%08x restored from CSR addr 0x%08x\n"
+ },
+ {0x01340001,
+ "PMU3: Update BC00, BC01, BC02 for rank-dimm 0x%02x\n"
+ },
+ {0x01350000,
+ "PMU3: Writing D4 RDIMM RCD Control words F0RC00 -> F0RC0F\n"
+ },
+ {0x01360000,
+ "PMU3: Disable parity in F0RC0E\n"
+ },
+ {0x01370000,
+ "PMU3: Writing D4 RDIMM RCD Control words F1RC00 -> F1RC05\n"
+ },
+ {0x01380000,
+ "PMU3: Writing D4 RDIMM RCD Control words F1RC1x -> F1RC9x\n"
+ },
+ {0x01390000,
+ "PMU3: Writing D4 Data buffer Control words BC00 -> BC0E\n"
+ },
+ {0x013a0002,
+ "PMU1: setAltCL Sending MR0 0x%x cl=%d\n"
+ },
+ {0x013b0002,
+ "PMU1: restoreFromAltCL Sending MR0 0x%x cl=%d\n"
+ },
+ {0x013c0002,
+ "PMU1: restoreAcsmFromAltCL Sending MR0 0x%x cl=%d\n"
+ },
+ {0x013d0002,
+ "PMU2: Setting D3R RC%d = 0x%01x\n"
+ },
+ {0x013e0000,
+ "PMU3: Writing D3 RDIMM RCD Control words RC0 -> RC11\n"
+ },
+ {0x013f0002,
+ "PMU0: VrefDAC0/1 vddqStart %d dacToVddq %d\n"
+ },
+ {0x01400001,
+ "PMU: Error: Messageblock phyVref=0x%x is above the limit for TSMC28's attenuated LPDDR4 receivers. Please see the pub databook\n"
+ },
+ {0x01410001,
+ "PMU: Error: Messageblock phyVref=0x%x is above the limit for TSMC28's attenuated DDR4 receivers. Please see the pub databook\n"
+ },
+ {0x01420001,
+ "PMU0: PHY VREF @ (%d/1000) VDDQ\n"
+ },
+ {0x01430002,
+ "PMU0: initalizing phy vrefDacs to %d ExtVrefRange %x\n"
+ },
+ {0x01440002,
+ "PMU0: initalizing global vref to %d range %d\n"
+ },
+ {0x01450002,
+ "PMU4: Setting initial device vrefDQ for CS%d to MR6 = 0x%04x\n"
+ },
+ {0x01460003,
+ "PMU1: In write_level_fine() csn=%d dimm=%d pstate=%d\n"
+ },
+ {0x01470000,
+ "PMU3: Fine write leveling hardware search increasing TxDqsDly until full bursts are seen\n"
+ },
+ {0x01480000,
+ "PMU4: WL normalized pos : ........................|........................\n"
+ },
+ {0x01490007,
+ "PMU4: WL margin for nib %2d: %08x%08x%08x%08x%08x%08x\n"
+ },
+ {0x014a0000,
+ "PMU4: WL normalized pos : ........................|........................\n"
+ },
+ {0x014b0000,
+ "PMU3: Exiting write leveling mode\n"
+ },
+ {0x014c0001,
+ "PMU3: got %d for cl in load_wrlvl_acsm\n"
+ },
+ {0x014d0003,
+ "PMU1: In write_level_coarse() csn=%d dimm=%d pstate=%d\n"
+ },
+ {0x014e0003,
+ "PMU3: left eye edge search db:%d ln:%d dly:0x%x\n"
+ },
+ {0x014f0003,
+ "PMU3: right eye edge search db:%d ln:%d dly:0x%x\n"
+ },
+ {0x01500004,
+ "PMU3: eye center db:%d ln:%d dly:0x%x (maxdq:%x)\n"
+ },
+ {0x01510003,
+ "PMU3: Wrote to TxDqDly db:%d ln:%d dly:0x%x\n"
+ },
+ {0x01520003,
+ "PMU3: Wrote to TxDqDly db:%d ln:%d dly:0x%x\n"
+ },
+ {0x01530002,
+ "PMU3: Coarse write leveling dbyte%2d is still failing for TxDqsDly=0x%04x\n"
+ },
+ {0x01540002,
+ "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n"
+ },
+ {0x01550000,
+ "PMU: Error: Failed write leveling coarse\n"
+ },
+ {0x01560001,
+ "PMU3: got %d for cl in load_wrlvl_acsm\n"
+ },
+ {0x01570003,
+ "PMU3: In write_level_coarse() csn=%d dimm=%d pstate=%d\n"
+ },
+ {0x01580003,
+ "PMU3: left eye edge search db:%d ln:%d dly:0x%x\n"
+ },
+ {0x01590003,
+ "PMU3: right eye edge search db: %d ln: %d dly: 0x%x\n"
+ },
+ {0x015a0004,
+ "PMU3: eye center db: %d ln: %d dly: 0x%x (maxdq: 0x%x)\n"
+ },
+ {0x015b0003,
+ "PMU3: Wrote to TxDqDly db: %d ln: %d dly: 0x%x\n"
+ },
+ {0x015c0003,
+ "PMU3: Wrote to TxDqDly db: %d ln: %d dly: 0x%x\n"
+ },
+ {0x015d0002,
+ "PMU3: Coarse write leveling nibble%2d is still failing for TxDqsDly=0x%04x\n"
+ },
+ {0x015e0002,
+ "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n"
+ },
+ {0x015f0000,
+ "PMU: Error: Failed write leveling coarse\n"
+ },
+ {0x01600000,
+ "PMU4: WL normalized pos : ................................|................................\n"
+ },
+ {0x01610009,
+ "PMU4: WL margin for nib %2d: %08x%08x%08x%08x%08x%08x%08x%08x\n"
+ },
+ {0x01620000,
+ "PMU4: WL normalized pos : ................................|................................\n"
+ },
+ {0x01630001,
+ "PMU8: Adjust margin after WL coarse to be larger than %d\n"
+ },
+ {0x01640001,
+ "PMU: Error: All margin after write leveling coarse are smaller than minMargin %d\n"
+ },
+ {0x01650002,
+ "PMU8: Decrement nib %d TxDqsDly by %d fine step\n"
+ },
+ {0x01660003,
+ "PMU3: In write_level_coarse() csn=%d dimm=%d pstate=%d\n"
+ },
+ {0x01670005,
+ "PMU2: Write level: dbyte %d nib%d dq/dmbi %2d dqsfine 0x%04x dqDly 0x%04x\n"
+ },
+ {0x01680002,
+ "PMU3: Coarse write leveling nibble%2d is still failing for TxDqsDly=0x%04x\n"
+ },
+ {0x01690002,
+ "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n"
+ },
+ {0x016a0000,
+ "PMU: Error: Failed write leveling coarse\n"
+ },
+ {0x016b0001,
+ "PMU3: DWL delay = %d\n"
+ },
+ {0x016c0003,
+ "PMU3: Errcnt for DWL nib %2d delay = %2d is %d\n"
+ },
+ {0x016d0002,
+ "PMU3: DWL nibble %d sampled a 1 at delay %d\n"
+ },
+ {0x016e0003,
+ "PMU3: DWL nibble %d passed at delay %d. Rising edge was at %d\n"
+ },
+ {0x016f0000,
+ "PMU2: DWL did nto find a rising edge of memclk for all nibbles. Failing nibbles assumed to have rising edge close to fine delay 63\n"
+ },
+ {0x01700002,
+ "PMU2: Rising edge found in alias window, setting wrlvlDly for nibble %d = %d\n"
+ },
+ {0x01710002,
+ "PMU: Error: Failed DWL for nib %d with %d one\n"
+ },
+ {0x01720003,
+ "PMU2: Rising edge not found in alias window with %d one, leaving wrlvlDly for nibble %d = %d\n"
+ },
+ {0x04000000,
+ "PMU: Error:Mailbox Buffer Overflowed.\n"
+ },
+ {0x04010000,
+ "PMU: Error:Mailbox Buffer Overflowed.\n"
+ },
+ {0x04020000,
+ "PMU: ***** Assertion Error - terminating *****\n"
+ },
+ {0x04030002,
+ "PMU1: swapByte db %d by %d\n"
+ },
+ {0x04040003,
+ "PMU3: get_cmd_dly max(%d ps, %d memclk) = %d\n"
+ },
+ {0x04050002,
+ "PMU0: Write CSR 0x%06x 0x%04x\n"
+ },
+ {0x04060002,
+ "PMU0: hwt_init_ppgc_prbs(): Polynomial: %x, Deg: %d\n"
+ },
+ {0x04070001,
+ "PMU: Error: acsm_set_cmd to non existent instruction address %d\n"
+ },
+ {0x04080001,
+ "PMU: Error: acsm_set_cmd with unknown ddr cmd 0x%x\n"
+ },
+ {0x0409000c,
+ "PMU1: acsm_addr %02x, acsm_flgs %04x, ddr_cmd %02x, cmd_dly %02x, ddr_addr %04x, ddr_bnk %02x, ddr_cs %02x, cmd_rcnt %02x, AcsmSeq0/1/2/3 %04x %04x %04x %04x\n"
+ },
+ {0x040a0000,
+ "PMU: Error: Polling on ACSM done failed to complete in acsm_poll_done()...\n"
+ },
+ {0x040b0000,
+ "PMU1: acsm RUN\n"
+ },
+ {0x040c0000,
+ "PMU1: acsm STOPPED\n"
+ },
+ {0x040d0002,
+ "PMU1: acsm_init: acsm_mode %04x mxrdlat %04x\n"
+ },
+ {0x040e0002,
+ "PMU: Error: setAcsmCLCWL: cl and cwl must be each >= 2 and 5, resp. CL=%d CWL=%d\n"
+ },
+ {0x040f0002,
+ "PMU: Error: setAcsmCLCWL: cl and cwl must be each >= 5. CL=%d CWL=%d\n"
+ },
+ {0x04100002,
+ "PMU1: setAcsmCLCWL: CASL %04d WCASL %04d\n"
+ },
+ {0x04110001,
+ "PMU: Error: Reserved value of register F0RC0F found in message block: 0x%04x\n"
+ },
+ {0x04120001,
+ "PMU3: Written MRS to CS=0x%02x\n"
+ },
+ {0x04130001,
+ "PMU3: Written MRS to CS=0x%02x\n"
+ },
+ {0x04140000,
+ "PMU3: Entering Boot Freq Mode.\n"
+ },
+ {0x04150001,
+ "PMU: Error: Boot clock divider setting of %d is too small\n"
+ },
+ {0x04160000,
+ "PMU3: Exiting Boot Freq Mode.\n"
+ },
+ {0x04170002,
+ "PMU3: Writing MR%d OP=%x\n"
+ },
+ {0x04180000,
+ "PMU: Error: Delay too large in slomo\n"
+ },
+ {0x04190001,
+ "PMU3: Written MRS to CS=0x%02x\n"
+ },
+ {0x041a0000,
+ "PMU3: Enable Channel A\n"
+ },
+ {0x041b0000,
+ "PMU3: Enable Channel B\n"
+ },
+ {0x041c0000,
+ "PMU3: Enable All Channels\n"
+ },
+ {0x041d0002,
+ "PMU2: Use PDA mode to set MR%d with value 0x%02x\n"
+ },
+ {0x041e0001,
+ "PMU3: Written Vref with PDA to CS=0x%02x\n"
+ },
+ {0x041f0000,
+ "PMU1: start_cal: DEBUG: setting CalRun to 1\n"
+ },
+ {0x04200000,
+ "PMU1: start_cal: DEBUG: setting CalRun to 0\n"
+ },
+ {0x04210001,
+ "PMU1: lock_pll_dll: DEBUG: pstate = %d\n"
+ },
+ {0x04220001,
+ "PMU1: lock_pll_dll: DEBUG: dfifreqxlat_pstate = %d\n"
+ },
+ {0x04230001,
+ "PMU1: lock_pll_dll: DEBUG: pllbypass = %d\n"
+ },
+ {0x04240001,
+ "PMU3: SaveLcdlSeed: Saving seed %d\n"
+ },
+ {0x04250000,
+ "PMU1: in phy_defaults()\n"
+ },
+ {0x04260003,
+ "PMU3: ACXConf:%d MaxNumDbytes:%d NumDfi:%d\n"
+ },
+ {0x04270005,
+ "PMU1: setAltAcsmCLCWL setting cl=%d cwl=%d\n"
+ },
+};
+
+const static struct phy_msg messages_2d[] = {
+ {0x00000001,
+ "PMU0: Converting %d into an MR\n"
+ },
+ {0x00010003,
+ "PMU DEBUG: vref_idx %d -= %d, range_idx = %d\n"
+ },
+ {0x00020002,
+ "PMU0: vrefIdx. Passing range %d, remaining vrefidx = %d\n"
+ },
+ {0x00030002,
+ "PMU0: VrefIdx %d -> MR[6:0] 0x%02x\n"
+ },
+ {0x00040001,
+ "PMU0: Converting MR 0x%04x to vrefIdx\n"
+ },
+ {0x00050002,
+ "PMU0: DAC %d Range %d\n"
+ },
+ {0x00060003,
+ "PMU0: Range %d, Range_idx %d, vref_idx offset %d\n"
+ },
+ {0x00070002,
+ "PMU0: MR 0x%04x -> VrefIdx %d\n"
+ },
+ {0x00080001,
+ "PMU: Error: Illegal timing group number ,%d, in getPtrVrefDq\n"
+ },
+ {0x00090003,
+ "PMU1: VrefDqR%dNib%d = %d\n"
+ },
+ {0x000a0003,
+ "PMU0: VrefDqR%dNib%d = %d\n"
+ },
+ {0x000b0000,
+ "PMU0: ----------------MARGINS-------\n"
+ },
+ {0x000c0002,
+ "PMU0: R%d_RxClkDly_Margin = %d\n"
+ },
+ {0x000d0002,
+ "PMU0: R%d_VrefDac_Margin = %d\n"
+ },
+ {0x000e0002,
+ "PMU0: R%d_TxDqDly_Margin = %d\n"
+ },
+ {0x000f0002,
+ "PMU0: R%d_DeviceVref_Margin = %d\n"
+ },
+ {0x00100000,
+ "PMU0: -----------------------\n"
+ },
+ {0x00110003,
+ "PMU0: eye %d's for all TG's is [%d ... %d]\n"
+ },
+ {0x00120000,
+ "PMU0: ------- settingWeight -----\n"
+ },
+ {0x00130002,
+ "PMU0: Weight %d @ Setting %d\n"
+ },
+ {0x0014001f,
+ "PMU4: %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d >%3d< %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d\n"
+ },
+ {0x00150002,
+ "PMU3: Voltage Range = [%d, %d]\n"
+ },
+ {0x00160004,
+ "PMU4: -- DB%d L%d -- centers: delay = %d, voltage = %d\n"
+ },
+ {0x00170001,
+ "PMU5: <<KEY>> 0 TxDqDlyTg%d <<KEY>> coarse(6:6) fine(5:0)\n"
+ },
+ {0x00180001,
+ "PMU5: <<KEY>> 0 messageBlock VrefDqR%d <<KEY>> MR6(6:0)\n"
+ },
+ {0x00190001,
+ "PMU5: <<KEY>> 0 RxClkDlyTg%d <<KEY>> fine(5:0)\n"
+ },
+ {0x001a0003,
+ "PMU0: tgToCsn: tg %d + 0x%04x -> csn %d\n"
+ },
+ {0x001b0002,
+ "PMU: Error: LP4 rank %d cannot be mapped on tg %d\n"
+ },
+ {0x001c0002,
+ "PMU3: Sending vref %d, Mr = 0X%05x, to all devices\n"
+ },
+ {0x001d0004,
+ "PMU4: -------- %dD Write Scanning TG %d (CS 0x%x) Lanes 0x%03x --------\n"
+ },
+ {0x001e0002,
+ "PMU0: training lanes 0x%03x using lanes 0x%03x\n"
+ },
+ {0x001f0003,
+ "PMU4: ------- 2D-DFE Read Scanning TG %d (CS 0x%x) Lanes 0x%03x -------\n"
+ },
+ {0x00200004,
+ "PMU4: ------- %dD Read Scanning TG %d (CS 0x%x) Lanes 0x%03x -------\n"
+ },
+ {0x00210003,
+ "PMU4: TG%d MR1[13,6,5]=0x%x MR6[13,9,8]=0x%x\n"
+ },
+ {0x00220002,
+ "PMU0: training lanes 0x%03x using lanes 0x%03x\n"
+ },
+ {0x00230003,
+ "PMU4: ------- 2D-DFE Read Scanning TG %d (CS 0x%x) Lanes 0x%03x -------\n"
+ },
+ {0x00240004,
+ "PMU4: ------- %dD Read Scanning TG %d (CS 0x%x) Lanes 0x%03x -------\n"
+ },
+ {0x00250002,
+ "PMU0: training lanes 0x%03x using lanes 0x%03x\n"
+ },
+ {0x00260002,
+ "PMU3: Sending vref %d, Mr = 0X%05x, to all devices\n"
+ },
+ {0x00270004,
+ "PMU4: -------- %dD Write Scanning TG %d (CS 0x%x) Lanes 0x%03x --------\n"
+ },
+ {0x00280001,
+ "PMU0: input %d\n"
+ },
+ {0x00290002,
+ "PMU4: Programmed Voltage Search Range [%d, %d]\n"
+ },
+ {0x002a0002,
+ "PMU3: Delay Stepsize = %d Fine, Voltage Stepsize = %d DAC\n"
+ },
+ {0x002b0002,
+ "PMU4: Delay Weight = %d, Voltage Weight = %d\n"
+ },
+ {0x002c0003,
+ "PMU0: raw 0x%x allFine %d incDec %d"
+ },
+ {0x002d0008,
+ "PMU0: db%d l%d, voltage 0x%x (u_r %d) delay 0x%x (u_r %d) - lcdl %d mask 0x%x\n"
+ },
+ {0x002e0005,
+ "PMU0: DB%d L%d, Eye %d, Seed = (0x%x, 0x%x)\n"
+ },
+ {0x002f0002,
+ "PMU3: 2D Enables : %d, 1, %d\n"
+ },
+ {0x00300006,
+ "PMU3: 2D Delay Ranges: OOPL[0x%04x,0x%04x], IP[0x%04x,0x%04x], OOPR[0x%04x,0x%04x]\n"
+ },
+ {0x00310002,
+ "PMU3: 2D Voltage Search Range : [%d, %d]\n"
+ },
+ {0x00320002,
+ "PMU4: Found Voltage Search Range [%d, %d]\n"
+ },
+ {0x00330002,
+ "PMU0: User Weight = %d, Voltage Weight = %d\n"
+ },
+ {0x00340005,
+ "PMU0: D(%d,%d) V(%d,%d | %d)\n"
+ },
+ {0x00350002,
+ "PMU0: Norm Weight = %d, Voltage Weight = %d\n"
+ },
+ {0x00360002,
+ "PMU0: seed 0 = (%d,%d) (center)\n"
+ },
+ {0x00370003,
+ "PMU0: seed 1 = (%d,%d).min edge at idx %d\n"
+ },
+ {0x00380003,
+ "PMU0: seed 2 = (%d,%d) max edge at idx %d\n"
+ },
+ {0x00390003,
+ "PMU0: Search point %d = (%d,%d)\n"
+ },
+ {0x003a0005,
+ "PMU0: YMARGIN: ^ %d, - %d, v %d. rate %d = %d\n"
+ },
+ {0x003b0003,
+ "PMU0: XMARGIN: center %d, edge %d. = %d\n"
+ },
+ {0x003c0002,
+ "PMU0: ----------- weighting (%d,%d) ----------------\n"
+ },
+ {0x003d0003,
+ "PMU0: X margin - L %d R %d - Min %d\n"
+ },
+ {0x003e0003,
+ "PMU0: Y margin - L %d R %d - Min %d\n"
+ },
+ {0x003f0003,
+ "PMU0: center (%d,%d) weight = %d\n"
+ },
+ {0x00400003,
+ "PMU4: Eye argest blob area %d from %d to %d\n"
+ },
+ {0x00410002,
+ "PMU0: Compute centroid min_x %d max_x %d\n"
+ },
+ {0x00420003,
+ "PMU0: Compute centroid sumLnDlyWidth %d sumLnVrefWidth %d sumLnWidht %d\n"
+ },
+ {0x00430000,
+ "PMU: Error: No passing region found for 1 or more lanes. Set hdtCtrl=4 to see passing regions\n"
+ },
+ {0x00440003,
+ "PMU0: Centroid ( %d, %d ) found with sumLnWidht %d\n"
+ },
+ {0x00450003,
+ "PMU0: Optimal allFine Center ( %d + %d ,%d )\n"
+ },
+ {0x00460003,
+ "PMU3: point %d starting at (%d,%d)\n"
+ },
+ {0x00470002,
+ "PMU0: picking left (%d > %d)\n"
+ },
+ {0x00480002,
+ "PMU0: picking right (%d > %d)\n"
+ },
+ {0x00490002,
+ "PMU0: picking down (%d > %d)\n"
+ },
+ {0x004a0002,
+ "PMU0: picking up (%d > %d)\n"
+ },
+ {0x004b0009,
+ "PMU3: new center @ (%3d, %3d). Moved (%2i, %2i) -- L %d, R %d, C %d, U %d, D %d\n"
+ },
+ {0x004c0003,
+ "PMU3: cordNum %d imporved %d to %d\n"
+ },
+ {0x004d0000,
+ "PMU: Error: No passing region found for 1 or more lanes. Set hdtCtrl=4 to see passing regions\n"
+ },
+ {0x004e0004,
+ "PMU0: Optimal allFine Center ( %d + %d ,%d ), found with weight %d.\n"
+ },
+ {0x004f0003,
+ "PMU0: merging lanes=%d..%d, centerMerge_t %d\n"
+ },
+ {0x00500001,
+ "PMU0: laneVal %d is disable\n"
+ },
+ {0x00510002,
+ "PMU0: checking common center %d against current center %d\n"
+ },
+ {0x00520001,
+ "PMU: Error: getCompoundEye Called on lane%d eye with non-compatible centers\n"
+ },
+ {0x00530001,
+ "PMU0: laneItr %d is disable\n"
+ },
+ {0x00540005,
+ "PMU0: lane %d, data_idx %d, offset_idx %d, = [%d..%d]\n"
+ },
+ {0x00550003,
+ "PMU0: lane %d, data_idx %d, offset_idx %d, offset_idx out of range!\n"
+ },
+ {0x00560003,
+ "PMU0: mergeData[%d] = max_v_low %d, min_v_high %d\n"
+ },
+ {0x00570005,
+ "PMU1: writing merged center (%d,%d) back to dataBlock[%d]. doDelay %d, doVoltage %d\n"
+ },
+ {0x00580005,
+ "PMU0: applying relative (%i,%i) back to dataBlock[%d]. doDelay %d, doVoltage %d\n"
+ },
+ {0x00590002,
+ "PMU0: drvstren %x is idx %d in the table\n"
+ },
+ {0x005a0000,
+ "PMU4: truncating FFE drive strength search range. Out of drive strengths to check.\n"
+ },
+ {0x005b0002,
+ "PMU5: Weak 1 changed to pull-up %5d ohms, pull-down %5d ohms\n"
+ },
+ {0x005c0002,
+ "PMU5: Weak 0 changed to pull-up %5d ohms, pull-down %5d ohms\n"
+ },
+ {0x005d0003,
+ "PMU0: dlyMargin L %02d R %02d, min %02d\n"
+ },
+ {0x005e0003,
+ "PMU0: vrefMargin T %02d B %02d, min %02d\n"
+ },
+ {0x005f0002,
+ "PMU3: new minimum VrefMargin (%d < %d) recorded\n"
+ },
+ {0x00600002,
+ "PMU3: new minimum DlyMargin (%d < %d) recorded\n"
+ },
+ {0x00610000,
+ "PMU0: RX finding the per-nibble, per-tg rxClkDly values\n"
+ },
+ {0x00620003,
+ "PMU0: Merging collected eyes [%d..%d) and analyzing for nibble %d's optimal rxClkDly\n"
+ },
+ {0x00630002,
+ "PMU0: -- centers: delay = %d, voltage = %d\n"
+ },
+ {0x00640003,
+ "PMU0: dumping optimized eye -- centers: delay = %d (%d), voltage = %d\n"
+ },
+ {0x00650000,
+ "PMU0: TX optimizing txDqDelays\n"
+ },
+ {0x00660001,
+ "PMU3: Analyzing collected eye %d for a lane's optimal TxDqDly\n"
+ },
+ {0x00670001,
+ "PMU0: eye-lane %d is disable\n"
+ },
+ {0x00680000,
+ "PMU0: TX optimizing device voltages\n"
+ },
+ {0x00690002,
+ "PMU0: Merging collected eyes [%d..%d) and analyzing for optimal device txVref\n"
+ },
+ {0x006a0002,
+ "PMU0: -- centers: delay = %d, voltage = %d\n"
+ },
+ {0x006b0003,
+ "PMU0: dumping optimized eye -- centers: delay = %d (%d), voltage = %d\n"
+ },
+ {0x006c0000,
+ "PMU4: VrefDac (compound all TG) Bottom Top -> Center\n"
+ },
+ {0x006d0005,
+ "PMU4: DB%d L%d %3d %3d -> %3d (DISCONNECTED)\n"
+ },
+ {0x006e0005,
+ "PMU4: DB%d L%d %3d %3d -> %3d\n"
+ },
+ {0x006f0005,
+ "PMU0: writing rxClkDelay for tg%d db%1d nib%1d to 0x%02x from eye[%02d] (DISCONNECTED)\n"
+ },
+ {0x00700003,
+ "PMU: Error: Dbyte %d nibble %d's optimal rxClkDly of 0x%x is out of bounds\n"
+ },
+ {0x00710005,
+ "PMU0: writing rxClkDelay for tg%d db%1d nib%1d to 0x%02x from eye[%02d]\n"
+ },
+ {0x00720005,
+ "PMU0: tx voltage for tg%2d nib%2d to %3d (%d) from eye[%02d]\n"
+ },
+ {0x00730001,
+ "PMU0: vref Sum = %d\n"
+ },
+ {0x00740004,
+ "PMU0: tx voltage total is %d/%d -> %d -> %d\n"
+ },
+ {0x00750007,
+ "PMU0: writing txDqDelay for tg%1d db%1d ln%1d to 0x%02x (%d coarse, %d fine) from eye[%02d] (DISCONNECTED)\n"
+ },
+ {0x00760003,
+ "PMU: Error: Dbyte %d lane %d's optimal txDqDly of 0x%x is out of bounds\n"
+ },
+ {0x00770007,
+ "PMU0: writing txDqDelay for tg%1d db%1d l%1d to 0x%02x (%d coarse, %d fine) from eye[%02d]\n"
+ },
+ {0x00780002,
+ "PMU0: %d (0=tx, 1=rx) TgMask for this simulation: %x\n"
+ },
+ {0x00790001,
+ "PMU0: eye-byte %d is disable\n"
+ },
+ {0x007a0001,
+ "PMU0: eye-lane %d is disable\n"
+ },
+ {0x007b0003,
+ "PMU10: Start d4_2d_lrdimm_rx_dfe dimm %d nbTap %d biasStepMode %d\n"
+ },
+ {0x007c0001,
+ "PMU10: DB DFE feature not fully supported, F2BCEx value is 0x%02x\n"
+ },
+ {0x007d0001,
+ "PMU10: DB DFE feature fully supported, F2BCEx value is 0x%02x\n"
+ },
+ {0x007e0002,
+ "PMU8: Start d4_2d_lrdimm_rx_dfe for tap %d biasStepInc %d\n"
+ },
+ {0x007f0001,
+ "PMU7: Start d4_2d_lrdimm_rx_dfe tapCoff 0x%0x\n"
+ },
+ {0x00800003,
+ "PMU6: d4_2d_lrdimm_rx_dfe db %d lane %d area %d\n"
+ },
+ {0x00810004,
+ "PMU7: d4_2d_lrdimm_rx_dfe db %d lane %d max area %d best bias 0x%0x\n"
+ },
+ {0x00820001,
+ "PMU0: eye-lane %d is disable\n"
+ },
+ {0x00830003,
+ "PMU5: Setting 0x%x improved rank weight (%4d < %4d)\n"
+ },
+ {0x00840001,
+ "PMU4: Setting 0x%x still optimal\n"
+ },
+ {0x00850002,
+ "PMU5: ---- Training CS%d MR%d DRAM Equalization ----\n"
+ },
+ {0x00860001,
+ "PMU0: eye-lane %d is disable\n"
+ },
+ {0x00870003,
+ "PMU0: eye %d weight %d allTgWeight %d\n"
+ },
+ {0x00880002,
+ "PMU5: FFE figure of merit improved from %d to %d\n"
+ },
+ {0x00890002,
+ "PMU: Error: LP4 rank %d cannot be mapped on tg %d\n"
+ },
+ {0x008a0000,
+ "PMU4: Adjusting vrefDac0 for just 1->x transitions\n"
+ },
+ {0x008b0000,
+ "PMU4: Adjusting vrefDac1 for just 0->x transitions\n"
+ },
+ {0x008c0001,
+ "PMU5: Strong 1, pull-up %d ohms\n"
+ },
+ {0x008d0001,
+ "PMU5: Strong 0, pull-down %d ohms\n"
+ },
+ {0x008e0000,
+ "PMU4: Enabling weak drive strengths (FFE)\n"
+ },
+ {0x008f0000,
+ "PMU5: Changing all weak driver strengths\n"
+ },
+ {0x00900000,
+ "PMU5: Finalizing weak drive strengths\n"
+ },
+ {0x00910000,
+ "PMU4: retraining with optimal drive strength settings\n"
+ },
+ {0x00920002,
+ "PMU0: targeting CsX = %d and CsY = %d\n"
+ },
+ {0x00930001,
+ "PMU1:prbsGenCtl:%x\n"
+ },
+ {0x00940000,
+ "PMU1: loading 2D acsm sequence\n"
+ },
+ {0x00950000,
+ "PMU1: loading 1D acsm sequence\n"
+ },
+ {0x00960002,
+ "PMU3: %d memclocks @ %d to get half of 300ns\n"
+ },
+ {0x00970000,
+ "PMU: Error: User requested MPR read pattern for read DQS training in DDR3 Mode\n"
+ },
+ {0x00980000,
+ "PMU3: Running 1D search for left eye edge\n"
+ },
+ {0x00990001,
+ "PMU1: In Phase Left Edge Search cs %d\n"
+ },
+ {0x009a0001,
+ "PMU1: Out of Phase Left Edge Search cs %d\n"
+ },
+ {0x009b0000,
+ "PMU3: Running 1D search for right eye edge\n"
+ },
+ {0x009c0001,
+ "PMU1: In Phase Right Edge Search cs %d\n"
+ },
+ {0x009d0001,
+ "PMU1: Out of Phase Right Edge Search cs %d\n"
+ },
+ {0x009e0001,
+ "PMU1: mxRdLat training pstate %d\n"
+ },
+ {0x009f0001,
+ "PMU1: mxRdLat search for cs %d\n"
+ },
+ {0x00a00001,
+ "PMU0: MaxRdLat non consistent DtsmLoThldXingInd 0x%03x\n"
+ },
+ {0x00a10003,
+ "PMU4: CS %d Dbyte %d worked with DFIMRL = %d DFICLKs\n"
+ },
+ {0x00a20004,
+ "PMU3: MaxRdLat Read Lane err mask for csn %d, DFIMRL %2d DFIClks, dbyte %d = 0x%03x\n"
+ },
+ {0x00a30003,
+ "PMU3: MaxRdLat Read Lane err mask for csn %d DFIMRL %2d, All dbytes = 0x%03x\n"
+ },
+ {0x00a40001,
+ "PMU: Error: CS%d failed to find a DFIMRL setting that worked for all bytes during MaxRdLat training\n"
+ },
+ {0x00a50002,
+ "PMU3: Smallest passing DFIMRL for all dbytes in CS%d = %d DFIClks\n"
+ },
+ {0x00a60000,
+ "PMU: Error: No passing DFIMRL value found for any chip select during MaxRdLat training\n"
+ },
+ {0x00a70003,
+ "PMU: Error: Dbyte %d lane %d txDqDly passing region is too small (width = %d)\n"
+ },
+ {0x00a80006,
+ "PMU10: Adjusting rxclkdly db %d nib %d from %d+%d=%d->%d\n"
+ },
+ {0x00a90000,
+ "PMU4: TxDqDly Passing Regions (EyeLeft EyeRight -> EyeCenter) Units=1/32 UI\n"
+ },
+ {0x00aa0005,
+ "PMU4: DB %d Lane %d: %3d %3d -> %3d\n"
+ },
+ {0x00ab0002,
+ "PMU2: TXDQ delayLeft[%2d] = %3d (DISCONNECTED)\n"
+ },
+ {0x00ac0004,
+ "PMU2: TXDQ delayLeft[%2d] = %3d oopScaled = %3d selectOop %d\n"
+ },
+ {0x00ad0002,
+ "PMU2: TXDQ delayRight[%2d] = %3d (DISCONNECTED)\n"
+ },
+ {0x00ae0004,
+ "PMU2: TXDQ delayRight[%2d] = %3d oopScaled = %3d selectOop %d\n"
+ },
+ {0x00af0003,
+ "PMU: Error: Dbyte %d lane %d txDqDly passing region is too small (width = %d)\n"
+ },
+ {0x00b00000,
+ "PMU4: TxDqDly Passing Regions (EyeLeft EyeRight -> EyeCenter) Units=1/32 UI\n"
+ },
+ {0x00b10002,
+ "PMU4: DB %d Lane %d: (DISCONNECTED)\n"
+ },
+ {0x00b20005,
+ "PMU4: DB %d Lane %d: %3d %3d -> %3d\n"
+ },
+ {0x00b30002,
+ "PMU3: Running 1D search csn %d for DM Right/NotLeft(%d) eye edge\n"
+ },
+ {0x00b40002,
+ "PMU3: WrDq DM byte%2d with Errcnt %d\n"
+ },
+ {0x00b50002,
+ "PMU3: WrDq DM byte%2d avgDly 0x%04x\n"
+ },
+ {0x00b60002,
+ "PMU1: WrDq DM byte%2d with Errcnt %d\n"
+ },
+ {0x00b70001,
+ "PMU: Error: Dbyte %d txDqDly DM training did not start inside the eye\n"
+ },
+ {0x00b80000,
+ "PMU4: DM TxDqDly Passing Regions (EyeLeft EyeRight -> EyeCenter) Units=1/32 UI\n"
+ },
+ {0x00b90002,
+ "PMU4: DB %d Lane %d: (DISCONNECTED)\n"
+ },
+ {0x00ba0005,
+ "PMU4: DB %d Lane %d: %3d %3d -> %3d\n"
+ },
+ {0x00bb0003,
+ "PMU: Error: Dbyte %d lane %d txDqDly DM passing region is too small (width = %d)\n"
+ },
+ {0x00bc0004,
+ "PMU3: Errcnt for MRD/MWD search nib %2d delay = (%d, 0x%02x) = %d\n"
+ },
+ {0x00bd0000,
+ "PMU3: Precharge all open banks\n"
+ },
+ {0x00be0002,
+ "PMU: Error: Dbyte %d nibble %d found mutliple working coarse delay setting for MRD/MWD\n"
+ },
+ {0x00bf0000,
+ "PMU4: MRD Passing Regions (coarseVal, fineLeft fineRight -> fineCenter)\n"
+ },
+ {0x00c00000,
+ "PMU4: MWD Passing Regions (coarseVal, fineLeft fineRight -> fineCenter)\n"
+ },
+ {0x00c10004,
+ "PMU10: Warning: DB %d nibble %d has multiple working coarse delays, %d and %d, choosing the smaller delay\n"
+ },
+ {0x00c20003,
+ "PMU: Error: Dbyte %d nibble %d MRD/MWD passing region is too small (width = %d)\n"
+ },
+ {0x00c30006,
+ "PMU4: DB %d nibble %d: %3d, %3d %3d -> %3d\n"
+ },
+ {0x00c40002,
+ "PMU1: Start MRD/nMWD %d for csn %d\n"
+ },
+ {0x00c50002,
+ "PMU2: RXDQS delayLeft[%2d] = %3d (DISCONNECTED)\n"
+ },
+ {0x00c60006,
+ "PMU2: RXDQS delayLeft[%2d] = %3d delayOop[%2d] = %3d OopScaled %4d, selectOop %d\n"
+ },
+ {0x00c70002,
+ "PMU2: RXDQS delayRight[%2d] = %3d (DISCONNECTED)\n"
+ },
+ {0x00c80006,
+ "PMU2: RXDQS delayRight[%2d] = %3d delayOop[%2d] = %4d OopScaled %4d, selectOop %d\n"
+ },
+ {0x00c90000,
+ "PMU4: RxClkDly Passing Regions (EyeLeft EyeRight -> EyeCenter)\n"
+ },
+ {0x00ca0002,
+ "PMU4: DB %d nibble %d: (DISCONNECTED)\n"
+ },
+ {0x00cb0005,
+ "PMU4: DB %d nibble %d: %3d %3d -> %3d\n"
+ },
+ {0x00cc0003,
+ "PMU: Error: Dbyte %d nibble %d rxClkDly passing region is too small (width = %d)\n"
+ },
+ {0x00cd0002,
+ "PMU0: goodbar = %d for RDWR_BLEN %d\n"
+ },
+ {0x00ce0001,
+ "PMU3: RxClkDly = %d\n"
+ },
+ {0x00cf0005,
+ "PMU0: db %d l %d absLane %d -> bottom %d top %d\n"
+ },
+ {0x00d00009,
+ "PMU3: BYTE %d - %3d %3d %3d %3d %3d %3d %3d %3d\n"
+ },
+ {0x00d10002,
+ "PMU: Error: dbyte %d lane %d's per-lane vrefDAC's had no passing region\n"
+ },
+ {0x00d20004,
+ "PMU0: db%d l%d - %d %d\n"
+ },
+ {0x00d30002,
+ "PMU0: goodbar = %d for RDWR_BLEN %d\n"
+ },
+ {0x00d40004,
+ "PMU3: db%d l%d saw %d issues at rxClkDly %d\n"
+ },
+ {0x00d50003,
+ "PMU3: db%d l%d first saw a pass->fail edge at rxClkDly %d\n"
+ },
+ {0x00d60002,
+ "PMU3: lane %d PBD = %d\n"
+ },
+ {0x00d70003,
+ "PMU3: db%d l%d first saw a DBI pass->fail edge at rxClkDly %d\n"
+ },
+ {0x00d80003,
+ "PMU2: db%d l%d already passed rxPBD = %d\n"
+ },
+ {0x00d90003,
+ "PMU0: db%d l%d, PBD = %d\n"
+ },
+ {0x00da0002,
+ "PMU: Error: dbyte %d lane %d failed read deskew\n"
+ },
+ {0x00db0003,
+ "PMU0: db%d l%d, inc PBD = %d\n"
+ },
+ {0x00dc0003,
+ "PMU1: Running lane deskew on pstate %d csn %d rdDBIEn %d\n"
+ },
+ {0x00dd0000,
+ "PMU: Error: Read deskew training has been requested, but csrMajorModeDbyte[2] is set\n"
+ },
+ {0x00de0002,
+ "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
+ },
+ {0x00df0002,
+ "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
+ },
+ {0x00e00001,
+ "PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D3U Type\n"
+ },
+ {0x00e10001,
+ "PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D3R Type\n"
+ },
+ {0x00e20001,
+ "PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D4U Type\n"
+ },
+ {0x00e30001,
+ "PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D4R Type\n"
+ },
+ {0x00e40001,
+ "PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D4LR Type\n"
+ },
+ {0x00e50000,
+ "PMU: Error: Both 2t timing mode and ddr4 geardown mode specified in the messageblock's PhyCfg and MR3 fields. Only one can be enabled\n"
+ },
+ {0x00e60003,
+ "PMU10: PHY TOTALS - NUM_DBYTES %d NUM_NIBBLES %d NUM_ANIBS %d\n"
+ },
+ {0x00e70006,
+ "PMU10: CSA=0x%02x, CSB=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, MMISC=%d DRAMFreq=%dMT DramType=LPDDR3\n"
+ },
+ {0x00e80006,
+ "PMU10: CSA=0x%02x, CSB=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, MMISC=%d DRAMFreq=%dMT DramType=LPDDR4\n"
+ },
+ {0x00e90008,
+ "PMU10: CS=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, 2T=%d, MMISC=%d AddrMirror=%d DRAMFreq=%dMT DramType=%d\n"
+ },
+ {0x00ea0004,
+ "PMU10: Pstate%d MR0=0x%04x MR1=0x%04x MR2=0x%04x\n"
+ },
+ {0x00eb0008,
+ "PMU10: Pstate%d MRS MR0=0x%04x MR1=0x%04x MR2=0x%04x MR3=0x%04x MR4=0x%04x MR5=0x%04x MR6=0x%04x\n"
+ },
+ {0x00ec0005,
+ "PMU10: Pstate%d MRS MR1_A0=0x%04x MR2_A0=0x%04x MR3_A0=0x%04x MR11_A0=0x%04x\n"
+ },
+ {0x00ed0000,
+ "PMU10: UseBroadcastMR set. All ranks and channels use MRXX_A0 for MR settings.\n"
+ },
+ {0x00ee0005,
+ "PMU10: Pstate%d MRS MR01_A0=0x%02x MR02_A0=0x%02x MR03_A0=0x%02x MR11_A0=0x%02x\n"
+ },
+ {0x00ef0005,
+ "PMU10: Pstate%d MRS MR12_A0=0x%02x MR13_A0=0x%02x MR14_A0=0x%02x MR22_A0=0x%02x\n"
+ },
+ {0x00f00005,
+ "PMU10: Pstate%d MRS MR01_A1=0x%02x MR02_A1=0x%02x MR03_A1=0x%02x MR11_A1=0x%02x\n"
+ },
+ {0x00f10005,
+ "PMU10: Pstate%d MRS MR12_A1=0x%02x MR13_A1=0x%02x MR14_A1=0x%02x MR22_A1=0x%02x\n"
+ },
+ {0x00f20005,
+ "PMU10: Pstate%d MRS MR01_B0=0x%02x MR02_B0=0x%02x MR03_B0=0x%02x MR11_B0=0x%02x\n"
+ },
+ {0x00f30005,
+ "PMU10: Pstate%d MRS MR12_B0=0x%02x MR13_B0=0x%02x MR14_B0=0x%02x MR22_B0=0x%02x\n"
+ },
+ {0x00f40005,
+ "PMU10: Pstate%d MRS MR01_B1=0x%02x MR02_B1=0x%02x MR03_B1=0x%02x MR11_B1=0x%02x\n"
+ },
+ {0x00f50005,
+ "PMU10: Pstate%d MRS MR12_B1=0x%02x MR13_B1=0x%02x MR14_B1=0x%02x MR22_B1=0x%02x\n"
+ },
+ {0x00f60002,
+ "PMU1: AcsmOdtCtrl%02d 0x%02x\n"
+ },
+ {0x00f70002,
+ "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
+ },
+ {0x00f80002,
+ "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
+ },
+ {0x00f90000,
+ "PMU1: HwtCAMode set\n"
+ },
+ {0x00fa0001,
+ "PMU3: DDR4 infinite preamble enter/exit mode %d\n"
+ },
+ {0x00fb0002,
+ "PMU1: In rxenb_train() csn=%d pstate=%d\n"
+ },
+ {0x00fc0000,
+ "PMU3: Finding DQS falling edge\n"
+ },
+ {0x00fd0000,
+ "PMU3: Searching for DDR3/LPDDR3/LPDDR4 read preamble\n"
+ },
+ {0x00fe0009,
+ "PMU3: dtsm fails Even Nibbles : %2x %2x %2x %2x %2x %2x %2x %2x %2x\n"
+ },
+ {0x00ff0009,
+ "PMU3: dtsm fails Odd Nibbles : %2x %2x %2x %2x %2x %2x %2x %2x %2x\n"
+ },
+ {0x01000002,
+ "PMU3: Preamble search pass=%d anyfail=%d\n"
+ },
+ {0x01010000,
+ "PMU: Error: RxEn training preamble not found\n"
+ },
+ {0x01020000,
+ "PMU3: Found DQS pre-amble\n"
+ },
+ {0x01030001,
+ "PMU: Error: Dbyte %d couldn't find the rising edge of DQS during RxEn Training\n"
+ },
+ {0x01040000,
+ "PMU3: RxEn aligning to first rising edge of burst\n"
+ },
+ {0x01050001,
+ "PMU3: Decreasing RxEn delay by %d fine step to allow full capture of reads\n"
+ },
+ {0x01060001,
+ "PMU3: MREP Delay = %d\n"
+ },
+ {0x01070003,
+ "PMU3: Errcnt for MREP nib %2d delay = %2d is %d\n"
+ },
+ {0x01080002,
+ "PMU3: MREP nibble %d sampled a 1 at data buffer delay %d\n"
+ },
+ {0x01090002,
+ "PMU3: MREP nibble %d saw a 0 to 1 transition at data buffer delay %d\n"
+ },
+ {0x010a0000,
+ "PMU2: MREP did not find a 0 to 1 transition for all nibbles. Failing nibbles assumed to have rising edge close to fine delay 63\n"
+ },
+ {0x010b0002,
+ "PMU2: Rising edge found in alias window, setting rxDly for nibble %d = %d\n"
+ },
+ {0x010c0002,
+ "PMU: Error: Failed MREP for nib %d with %d one\n"
+ },
+ {0x010d0003,
+ "PMU2: Rising edge not found in alias window with %d one, leaving rxDly for nibble %d = %d\n"
+ },
+ {0x010e0002,
+ "PMU3: Training DIMM %d CSn %d\n"
+ },
+ {0x010f0001,
+ "PMU3: exitCAtrain_lp3 cs 0x%x\n"
+ },
+ {0x01100001,
+ "PMU3: enterCAtrain_lp3 cs 0x%x\n"
+ },
+ {0x01110001,
+ "PMU3: CAtrain_switchmsb_lp3 cs 0x%x\n"
+ },
+ {0x01120001,
+ "PMU3: CATrain_rdwr_lp3 looking for pattern %x\n"
+ },
+ {0x01130000,
+ "PMU3: exitCAtrain_lp4\n"
+ },
+ {0x01140001,
+ "PMU3: DEBUG enterCAtrain_lp4 1: cs 0x%x\n"
+ },
+ {0x01150001,
+ "PMU3: DEBUG enterCAtrain_lp4 3: Put dbyte %d in async mode\n"
+ },
+ {0x01160000,
+ "PMU3: DEBUG enterCAtrain_lp4 5: Send MR13 to turn on CA training\n"
+ },
+ {0x01170003,
+ "PMU3: DEBUG enterCAtrain_lp4 7: idx = %d vref = %x mr12 = %x\n"
+ },
+ {0x01180001,
+ "PMU3: CATrain_rdwr_lp4 looking for pattern %x\n"
+ },
+ {0x01190004,
+ "PMU3: Phase %d CAreadbackA db:%d %x xo:%x\n"
+ },
+ {0x011a0005,
+ "PMU3: DEBUG lp4SetCatrVref 1: cs=%d chan=%d mr12=%x vref=%d.%d%%\n"
+ },
+ {0x011b0003,
+ "PMU3: DEBUG lp4SetCatrVref 3: mr12 = %x send vref= %x to db=%d\n"
+ },
+ {0x011c0000,
+ "PMU10:Optimizing vref\n"
+ },
+ {0x011d0004,
+ "PMU4:mr12:%2x cs:%d chan %d r:%4x\n"
+ },
+ {0x011e0005,
+ "PMU3: i:%2d bstr:%2d bsto:%2d st:%d r:%d\n"
+ },
+ {0x011f0002,
+ "Failed to find sufficient CA Vref Passing Region for CS %d ch. %d\n"
+ },
+ {0x01200005,
+ "PMU3:Found %d.%d%% MR12:%x for cs:%d chan %d\n"
+ },
+ {0x01210002,
+ "PMU3:Calculated %d for AtxImpedence from acx %d.\n"
+ },
+ {0x01220000,
+ "PMU3:CA Odt impedence ==0. Use default vref.\n"
+ },
+ {0x01230003,
+ "PMU3:Calculated %d.%d%% for Vref MR12=0x%x.\n"
+ },
+ {0x01240000,
+ "PMU3: CAtrain_lp\n"
+ },
+ {0x01250000,
+ "PMU3: CAtrain Begins.\n"
+ },
+ {0x01260001,
+ "PMU3: CAtrain_lp testing dly %d\n"
+ },
+ {0x01270001,
+ "PMU5: CA bitmap dump for cs %x\n"
+ },
+ {0x01280001,
+ "PMU5: CAA%d "
+ },
+ {0x01290001, "%02x"
+ },
+ {0x012a0000, "\n"
+ },
+ {0x012b0001,
+ "PMU5: CAB%d "
+ },
+ {0x012c0001, "%02x"
+ },
+ {0x012d0000, "\n"
+ },
+ {0x012e0003,
+ "PMU3: anibi=%d, anibichan[anibi]=%d ,chan=%d\n"
+ },
+ {0x012f0001, "%02x"
+ },
+ {0x01300001, "\nPMU3:Raw CA setting :%x"
+ },
+ {0x01310002, "\nPMU3:ATxDly setting:%x margin:%d\n"
+ },
+ {0x01320002, "\nPMU3:InvClk ATxDly setting:%x margin:%d\n"
+ },
+ {0x01330000, "\nPMU3:No Range found!\n"
+ },
+ {0x01340003,
+ "PMU3: 2 anibi=%d, anibichan[anibi]=%d ,chan=%d"
+ },
+ {0x01350002, "\nPMU3: no neg clock => CA setting anib=%d, :%d\n"
+ },
+ {0x01360001,
+ "PMU3:Normal margin:%d\n"
+ },
+ {0x01370001,
+ "PMU3:Inverted margin:%d\n"
+ },
+ {0x01380000,
+ "PMU3:Using Inverted clock\n"
+ },
+ {0x01390000,
+ "PMU3:Using normal clk\n"
+ },
+ {0x013a0003,
+ "PMU3: 3 anibi=%d, anibichan[anibi]=%d ,chan=%d\n"
+ },
+ {0x013b0002,
+ "PMU3: Setting ATxDly for anib %x to %x\n"
+ },
+ {0x013c0000,
+ "PMU: Error: CA Training Failed.\n"
+ },
+ {0x013d0000,
+ "PMU1: Writing MRs\n"
+ },
+ {0x013e0000,
+ "PMU4:Using MR12 values from 1D CA VREF training.\n"
+ },
+ {0x013f0000,
+ "PMU3:Writing all MRs to fsp 1\n"
+ },
+ {0x01400000,
+ "PMU10:Lp4Quickboot mode.\n"
+ },
+ {0x01410000,
+ "PMU3: Writing MRs\n"
+ },
+ {0x01420001,
+ "PMU10: Setting boot clock divider to %d\n"
+ },
+ {0x01430000,
+ "PMU3: Resetting DRAM\n"
+ },
+ {0x01440000,
+ "PMU3: setup for RCD initalization\n"
+ },
+ {0x01450000,
+ "PMU3: pmu_exit_SR from dev_init()\n"
+ },
+ {0x01460000,
+ "PMU3: initializing RCD\n"
+ },
+ {0x01470000,
+ "PMU10: **** Executing 2D Image ****\n"
+ },
+ {0x01480001,
+ "PMU10: **** Start DDR4 Training. PMU Firmware Revision 0x%04x ****\n"
+ },
+ {0x01490001,
+ "PMU10: **** Start DDR3 Training. PMU Firmware Revision 0x%04x ****\n"
+ },
+ {0x014a0001,
+ "PMU10: **** Start LPDDR3 Training. PMU Firmware Revision 0x%04x ****\n"
+ },
+ {0x014b0001,
+ "PMU10: **** Start LPDDR4 Training. PMU Firmware Revision 0x%04x ****\n"
+ },
+ {0x014c0000,
+ "PMU: Error: Mismatched internal revision between DCCM and ICCM images\n"
+ },
+ {0x014d0001,
+ "PMU10: **** Testchip %d Specific Firmware ****\n"
+ },
+ {0x014e0000,
+ "PMU1: LRDIMM with EncodedCS mode, one DIMM\n"
+ },
+ {0x014f0000,
+ "PMU1: LRDIMM with EncodedCS mode, two DIMMs\n"
+ },
+ {0x01500000,
+ "PMU1: RDIMM with EncodedCS mode, one DIMM\n"
+ },
+ {0x01510000,
+ "PMU2: Starting LRDIMM MREP training for all ranks\n"
+ },
+ {0x01520000,
+ "PMU199: LRDIMM MREP training for all ranks completed\n"
+ },
+ {0x01530000,
+ "PMU2: Starting LRDIMM DWL training for all ranks\n"
+ },
+ {0x01540000,
+ "PMU199: LRDIMM DWL training for all ranks completed\n"
+ },
+ {0x01550000,
+ "PMU2: Starting LRDIMM MRD training for all ranks\n"
+ },
+ {0x01560000,
+ "PMU199: LRDIMM MRD training for all ranks completed\n"
+ },
+ {0x01570000,
+ "PMU2: Starting RXEN training for all ranks\n"
+ },
+ {0x01580000,
+ "PMU2: Starting write leveling fine delay training for all ranks\n"
+ },
+ {0x01590000,
+ "PMU2: Starting LRDIMM MWD training for all ranks\n"
+ },
+ {0x015a0000,
+ "PMU199: LRDIMM MWD training for all ranks completed\n"
+ },
+ {0x015b0000,
+ "PMU2: Starting write leveling fine delay training for all ranks\n"
+ },
+ {0x015c0000,
+ "PMU2: Starting read deskew training\n"
+ },
+ {0x015d0000,
+ "PMU2: Starting SI friendly 1d RdDqs training for all ranks\n"
+ },
+ {0x015e0000,
+ "PMU2: Starting write leveling coarse delay training for all ranks\n"
+ },
+ {0x015f0000,
+ "PMU2: Starting 1d WrDq training for all ranks\n"
+ },
+ {0x01600000,
+ "PMU2: Running DQS2DQ Oscillator for all ranks\n"
+ },
+ {0x01610000,
+ "PMU2: Starting again read deskew training but with PRBS\n"
+ },
+ {0x01620000,
+ "PMU2: Starting 1d RdDqs training for all ranks\n"
+ },
+ {0x01630000,
+ "PMU2: Starting again 1d WrDq training for all ranks\n"
+ },
+ {0x01640000,
+ "PMU2: Starting MaxRdLat training\n"
+ },
+ {0x01650000,
+ "PMU2: Starting 2d WrDq training for all ranks\n"
+ },
+ {0x01660000,
+ "PMU2: Starting 2d RdDqs training for all ranks\n"
+ },
+ {0x01670002,
+ "PMU3:read_fifo %x %x\n"
+ },
+ {0x01680001,
+ "PMU: Error: Invalid PhyDrvImpedance of 0x%x specified in message block.\n"
+ },
+ {0x01690001,
+ "PMU: Error: Invalid PhyOdtImpedance of 0x%x specified in message block.\n"
+ },
+ {0x016a0001,
+ "PMU: Error: Invalid BPZNResVal of 0x%x specified in message block.\n"
+ },
+ {0x016b0005,
+ "PMU3: fixRxEnBackOff csn:%d db:%d dn:%d bo:%d dly:%x\n"
+ },
+ {0x016c0001,
+ "PMU3: fixRxEnBackOff dly:%x\n"
+ },
+ {0x016d0000,
+ "PMU3: Entering setupPpt\n"
+ },
+ {0x016e0000,
+ "PMU3: Start lp4PopulateHighLowBytes\n"
+ },
+ {0x016f0002,
+ "PMU3:Dbyte Detect: db%d received %x\n"
+ },
+ {0x01700002,
+ "PMU3:getDqs2Dq read %x from dbyte %d\n"
+ },
+ {0x01710002,
+ "PMU3:getDqs2Dq(2) read %x from dbyte %d\n"
+ },
+ {0x01720001,
+ "PMU: Error: Dbyte %d read 0 from the DQS oscillator it is connected to\n"
+ },
+ {0x01730002,
+ "PMU4: Dbyte %d dqs2dq = %d/32 UI\n"
+ },
+ {0x01740003,
+ "PMU3:getDqs2Dq set dqs2dq:%d/32 ui (%d ps) from dbyte %d\n"
+ },
+ {0x01750003,
+ "PMU3: Setting coarse delay in AtxDly chiplet %d from 0x%02x to 0x%02x\n"
+ },
+ {0x01760003,
+ "PMU3: Clearing coarse delay in AtxDly chiplet %d from 0x%02x to 0x%02x\n"
+ },
+ {0x01770000,
+ "PMU3: Performing DDR4 geardown sync sequence\n"
+ },
+ {0x01780000,
+ "PMU1: Enter self refresh\n"
+ },
+ {0x01790000,
+ "PMU1: Exit self refresh\n"
+ },
+ {0x017a0000,
+ "PMU: Error: No dbiEnable with lp4\n"
+ },
+ {0x017b0000,
+ "PMU: Error: No dbiDisable with lp4\n"
+ },
+ {0x017c0001,
+ "PMU1: DDR4 update Rx DBI Setting disable %d\n"
+ },
+ {0x017d0001,
+ "PMU1: DDR4 update 2nCk WPre Setting disable %d\n"
+ },
+ {0x017e0005,
+ "PMU1: read_delay: db%d lane%d delays[%2d] = 0x%02x (max 0x%02x)\n"
+ },
+ {0x017f0004,
+ "PMU1: write_delay: db%d lane%d delays[%2d] = 0x%04x\n"
+ },
+ {0x01800001,
+ "PMU5: ID=%d -- db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 --\n"
+ },
+ {0x0181000b,
+ "PMU5: [%d]:0x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n"
+ },
+ {0x01820003,
+ "PMU2: dump delays - pstate=%d dimm=%d csn=%d\n"
+ },
+ {0x01830000,
+ "PMU3: Printing Mid-Training Delay Information\n"
+ },
+ {0x01840001,
+ "PMU5: CS%d <<KEY>> 0 TrainingCntr <<KEY>> coarse(15:10) fine(9:0)\n"
+ },
+ {0x01850001,
+ "PMU5: CS%d <<KEY>> 0 RxEnDly, 1 RxClkDly <<KEY>> coarse(10:6) fine(5:0)\n"
+ },
+ {0x01860001,
+ "PMU5: CS%d <<KEY>> 0 TxDqsDly, 1 TxDqDly <<KEY>> coarse(9:6) fine(5:0)\n"
+ },
+ {0x01870001,
+ "PMU5: CS%d <<KEY>> 0 RxPBDly <<KEY>> 1 Delay Unit ~= 7ps\n"
+ },
+ {0x01880000,
+ "PMU5: all CS <<KEY>> 0 DFIMRL <<KEY>> Units = DFI clocks\n"
+ },
+ {0x01890000,
+ "PMU5: all CS <<KEY>> VrefDACs <<KEY>> DAC(6:0)\n"
+ },
+ {0x018a0000,
+ "PMU1: Set DMD in MR13 and wrDBI in MR3 for training\n"
+ },
+ {0x018b0000,
+ "PMU: Error: getMaxRxen() failed to find largest rxen nibble delay\n"
+ },
+ {0x018c0003,
+ "PMU2: getMaxRxen(): maxDly %d maxTg %d maxNib %d\n"
+ },
+ {0x018d0003,
+ "PMU2: getRankMaxRxen(): maxDly %d Tg %d maxNib %d\n"
+ },
+ {0x018e0000,
+ "PMU1: skipping CDD calculation in 2D image\n"
+ },
+ {0x018f0001,
+ "PMU3: Calculating CDDs for pstate %d\n"
+ },
+ {0x01900003,
+ "PMU3: rxFromDly[%d][%d] = %d\n"
+ },
+ {0x01910003,
+ "PMU3: rxToDly [%d][%d] = %d\n"
+ },
+ {0x01920003,
+ "PMU3: rxDly [%d][%d] = %d\n"
+ },
+ {0x01930003,
+ "PMU3: txDly [%d][%d] = %d\n"
+ },
+ {0x01940003,
+ "PMU3: allFine CDD_RR_%d_%d = %d\n"
+ },
+ {0x01950003,
+ "PMU3: allFine CDD_WW_%d_%d = %d\n"
+ },
+ {0x01960003,
+ "PMU3: CDD_RR_%d_%d = %d\n"
+ },
+ {0x01970003,
+ "PMU3: CDD_WW_%d_%d = %d\n"
+ },
+ {0x01980003,
+ "PMU3: allFine CDD_RW_%d_%d = %d\n"
+ },
+ {0x01990003,
+ "PMU3: allFine CDD_WR_%d_%d = %d\n"
+ },
+ {0x019a0003,
+ "PMU3: CDD_RW_%d_%d = %d\n"
+ },
+ {0x019b0003,
+ "PMU3: CDD_WR_%d_%d = %d\n"
+ },
+ {0x019c0004,
+ "PMU3: F%dBC2x_B%d_D%d = 0x%02x\n"
+ },
+ {0x019d0004,
+ "PMU3: F%dBC3x_B%d_D%d = 0x%02x\n"
+ },
+ {0x019e0004,
+ "PMU3: F%dBC4x_B%d_D%d = 0x%02x\n"
+ },
+ {0x019f0004,
+ "PMU3: F%dBC5x_B%d_D%d = 0x%02x\n"
+ },
+ {0x01a00004,
+ "PMU3: F%dBC8x_B%d_D%d = 0x%02x\n"
+ },
+ {0x01a10004,
+ "PMU3: F%dBC9x_B%d_D%d = 0x%02x\n"
+ },
+ {0x01a20004,
+ "PMU3: F%dBCAx_B%d_D%d = 0x%02x\n"
+ },
+ {0x01a30004,
+ "PMU3: F%dBCBx_B%d_D%d = 0x%02x\n"
+ },
+ {0x01a40000,
+ "PMU10: Entering context_switch_postamble\n"
+ },
+ {0x01a50003,
+ "PMU10: context_switch_postamble is enabled for DIMM %d, RC0A=0x%x, RC3x=0x%x\n"
+ },
+ {0x01a60000,
+ "PMU10: Setting bcw fspace 0\n"
+ },
+ {0x01a70001,
+ "PMU10: Sending BC0A = 0x%x\n"
+ },
+ {0x01a80001,
+ "PMU10: Sending BC6x = 0x%x\n"
+ },
+ {0x01a90001,
+ "PMU10: Sending RC0A = 0x%x\n"
+ },
+ {0x01aa0001,
+ "PMU10: Sending RC3x = 0x%x\n"
+ },
+ {0x01ab0001,
+ "PMU10: Sending RC0A = 0x%x\n"
+ },
+ {0x01ac0001,
+ "PMU1: enter_lp3: DEBUG: pstate = %d\n"
+ },
+ {0x01ad0001,
+ "PMU1: enter_lp3: DEBUG: dfifreqxlat_pstate = %d\n"
+ },
+ {0x01ae0001,
+ "PMU1: enter_lp3: DEBUG: pllbypass = %d\n"
+ },
+ {0x01af0001,
+ "PMU1: enter_lp3: DEBUG: forcecal = %d\n"
+ },
+ {0x01b00001,
+ "PMU1: enter_lp3: DEBUG: pllmaxrange = 0x%x\n"
+ },
+ {0x01b10001,
+ "PMU1: enter_lp3: DEBUG: dacval_out = 0x%x\n"
+ },
+ {0x01b20001,
+ "PMU1: enter_lp3: DEBUG: pllctrl3 = 0x%x\n"
+ },
+ {0x01b30000,
+ "PMU3: Loading DRAM with BIOS supplied MR values and entering self refresh prior to exiting PMU code.\n"
+ },
+ {0x01b40002,
+ "PMU3: Setting DataBuffer function space of dimmcs 0x%02x to %d\n"
+ },
+ {0x01b50002,
+ "PMU4: Setting RCW FxRC%Xx = 0x%02x\n"
+ },
+ {0x01b60002,
+ "PMU4: Setting RCW FxRC%02x = 0x%02x\n"
+ },
+ {0x01b70001,
+ "PMU1: DDR4 update Rd Pre Setting disable %d\n"
+ },
+ {0x01b80002,
+ "PMU2: Setting BCW FxBC%Xx = 0x%02x\n"
+ },
+ {0x01b90002,
+ "PMU2: Setting BCW BC%02x = 0x%02x\n"
+ },
+ {0x01ba0002,
+ "PMU2: Setting BCW PBA mode FxBC%Xx = 0x%02x\n"
+ },
+ {0x01bb0002,
+ "PMU2: Setting BCW PBA mode BC%02x = 0x%02x\n"
+ },
+ {0x01bc0003,
+ "PMU4: BCW value for dimm %d, fspace %d, addr 0x%04x\n"
+ },
+ {0x01bd0002,
+ "PMU4: DB %d, value 0x%02x\n"
+ },
+ {0x01be0000,
+ "PMU6: WARNING MREP underflow, set to min value -2 coarse, 0 fine\n"
+ },
+ {0x01bf0004,
+ "PMU6: LRDIMM Writing final data buffer fine delay value nib %2d, trainDly %3d, fineDly code %2d, new MREP fine %2d\n"
+ },
+ {0x01c00003,
+ "PMU6: LRDIMM Writing final data buffer fine delay value nib %2d, trainDly %3d, fineDly code %2d\n"
+ },
+ {0x01c10003,
+ "PMU6: LRDIMM Writing data buffer fine delay type %d nib %2d, code %2d\n"
+ },
+ {0x01c20002,
+ "PMU6: Writing final data buffer coarse delay value dbyte %2d, coarse = 0x%02x\n"
+ },
+ {0x01c30003,
+ "PMU4: data 0x%04x at MB addr 0x%08x saved at CSR addr 0x%08x\n"
+ },
+ {0x01c40003,
+ "PMU4: data 0x%04x at MB addr 0x%08x restored from CSR addr 0x%08x\n"
+ },
+ {0x01c50003,
+ "PMU4: data 0x%04x at MB addr 0x%08x saved at CSR addr 0x%08x\n"
+ },
+ {0x01c60003,
+ "PMU4: data 0x%04x at MB addr 0x%08x restored from CSR addr 0x%08x\n"
+ },
+ {0x01c70001,
+ "PMU3: Update BC00, BC01, BC02 for rank-dimm 0x%02x\n"
+ },
+ {0x01c80000,
+ "PMU3: Writing D4 RDIMM RCD Control words F0RC00 -> F0RC0F\n"
+ },
+ {0x01c90000,
+ "PMU3: Disable parity in F0RC0E\n"
+ },
+ {0x01ca0000,
+ "PMU3: Writing D4 RDIMM RCD Control words F1RC00 -> F1RC05\n"
+ },
+ {0x01cb0000,
+ "PMU3: Writing D4 RDIMM RCD Control words F1RC1x -> F1RC9x\n"
+ },
+ {0x01cc0000,
+ "PMU3: Writing D4 Data buffer Control words BC00 -> BC0E\n"
+ },
+ {0x01cd0002,
+ "PMU1: setAltCL Sending MR0 0x%x cl=%d\n"
+ },
+ {0x01ce0002,
+ "PMU1: restoreFromAltCL Sending MR0 0x%x cl=%d\n"
+ },
+ {0x01cf0002,
+ "PMU1: restoreAcsmFromAltCL Sending MR0 0x%x cl=%d\n"
+ },
+ {0x01d00002,
+ "PMU2: Setting D3R RC%d = 0x%01x\n"
+ },
+ {0x01d10000,
+ "PMU3: Writing D3 RDIMM RCD Control words RC0 -> RC11\n"
+ },
+ {0x01d20002,
+ "PMU0: VrefDAC0/1 vddqStart %d dacToVddq %d\n"
+ },
+ {0x01d30001,
+ "PMU: Error: Messageblock phyVref=0x%x is above the limit for TSMC28's attenuated LPDDR4 receivers. Please see the pub databook\n"
+ },
+ {0x01d40001,
+ "PMU: Error: Messageblock phyVref=0x%x is above the limit for TSMC28's attenuated DDR4 receivers. Please see the pub databook\n"
+ },
+ {0x01d50001,
+ "PMU0: PHY VREF @ (%d/1000) VDDQ\n"
+ },
+ {0x01d60002,
+ "PMU0: initalizing phy vrefDacs to %d ExtVrefRange %x\n"
+ },
+ {0x01d70002,
+ "PMU0: initalizing global vref to %d range %d\n"
+ },
+ {0x01d80002,
+ "PMU4: Setting initial device vrefDQ for CS%d to MR6 = 0x%04x\n"
+ },
+ {0x01d90003,
+ "PMU1: In write_level_fine() csn=%d dimm=%d pstate=%d\n"
+ },
+ {0x01da0000,
+ "PMU3: Fine write leveling hardware search increasing TxDqsDly until full bursts are seen\n"
+ },
+ {0x01db0000,
+ "PMU4: WL normalized pos : ........................|........................\n"
+ },
+ {0x01dc0007,
+ "PMU4: WL margin for nib %2d: %08x%08x%08x%08x%08x%08x\n"
+ },
+ {0x01dd0000,
+ "PMU4: WL normalized pos : ........................|........................\n"
+ },
+ {0x01de0000,
+ "PMU3: Exiting write leveling mode\n"
+ },
+ {0x01df0001,
+ "PMU3: got %d for cl in load_wrlvl_acsm\n"
+ },
+ {0x01e00003,
+ "PMU1: In write_level_coarse() csn=%d dimm=%d pstate=%d\n"
+ },
+ {0x01e10003,
+ "PMU3: left eye edge search db:%d ln:%d dly:0x%x\n"
+ },
+ {0x01e20003,
+ "PMU3: right eye edge search db:%d ln:%d dly:0x%x\n"
+ },
+ {0x01e30004,
+ "PMU3: eye center db:%d ln:%d dly:0x%x (maxdq:%x)\n"
+ },
+ {0x01e40003,
+ "PMU3: Wrote to TxDqDly db:%d ln:%d dly:0x%x\n"
+ },
+ {0x01e50003,
+ "PMU3: Wrote to TxDqDly db:%d ln:%d dly:0x%x\n"
+ },
+ {0x01e60002,
+ "PMU3: Coarse write leveling dbyte%2d is still failing for TxDqsDly=0x%04x\n"
+ },
+ {0x01e70002,
+ "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n"
+ },
+ {0x01e80000,
+ "PMU: Error: Failed write leveling coarse\n"
+ },
+ {0x01e90001,
+ "PMU3: got %d for cl in load_wrlvl_acsm\n"
+ },
+ {0x01ea0003,
+ "PMU3: In write_level_coarse() csn=%d dimm=%d pstate=%d\n"
+ },
+ {0x01eb0003,
+ "PMU3: left eye edge search db:%d ln:%d dly:0x%x\n"
+ },
+ {0x01ec0003,
+ "PMU3: right eye edge search db: %d ln: %d dly: 0x%x\n"
+ },
+ {0x01ed0004,
+ "PMU3: eye center db: %d ln: %d dly: 0x%x (maxdq: 0x%x)\n"
+ },
+ {0x01ee0003,
+ "PMU3: Wrote to TxDqDly db: %d ln: %d dly: 0x%x\n"
+ },
+ {0x01ef0003,
+ "PMU3: Wrote to TxDqDly db: %d ln: %d dly: 0x%x\n"
+ },
+ {0x01f00002,
+ "PMU3: Coarse write leveling nibble%2d is still failing for TxDqsDly=0x%04x\n"
+ },
+ {0x01f10002,
+ "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n"
+ },
+ {0x01f20000,
+ "PMU: Error: Failed write leveling coarse\n"
+ },
+ {0x01f30000,
+ "PMU4: WL normalized pos : ................................|................................\n"
+ },
+ {0x01f40009,
+ "PMU4: WL margin for nib %2d: %08x%08x%08x%08x%08x%08x%08x%08x\n"
+ },
+ {0x01f50000,
+ "PMU4: WL normalized pos : ................................|................................\n"
+ },
+ {0x01f60001,
+ "PMU8: Adjust margin after WL coarse to be larger than %d\n"
+ },
+ {0x01f70001,
+ "PMU: Error: All margin after write leveling coarse are smaller than minMargin %d\n"
+ },
+ {0x01f80002,
+ "PMU8: Decrement nib %d TxDqsDly by %d fine step\n"
+ },
+ {0x01f90003,
+ "PMU3: In write_level_coarse() csn=%d dimm=%d pstate=%d\n"
+ },
+ {0x01fa0005,
+ "PMU2: Write level: dbyte %d nib%d dq/dmbi %2d dqsfine 0x%04x dqDly 0x%04x\n"
+ },
+ {0x01fb0002,
+ "PMU3: Coarse write leveling nibble%2d is still failing for TxDqsDly=0x%04x\n"
+ },
+ {0x01fc0002,
+ "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n"
+ },
+ {0x01fd0000,
+ "PMU: Error: Failed write leveling coarse\n"
+ },
+ {0x01fe0001,
+ "PMU3: DWL delay = %d\n"
+ },
+ {0x01ff0003,
+ "PMU3: Errcnt for DWL nib %2d delay = %2d is %d\n"
+ },
+ {0x02000002,
+ "PMU3: DWL nibble %d sampled a 1 at delay %d\n"
+ },
+ {0x02010003,
+ "PMU3: DWL nibble %d passed at delay %d. Rising edge was at %d\n"
+ },
+ {0x02020000,
+ "PMU2: DWL did nto find a rising edge of memclk for all nibbles. Failing nibbles assumed to have rising edge close to fine delay 63\n"
+ },
+ {0x02030002,
+ "PMU2: Rising edge found in alias window, setting wrlvlDly for nibble %d = %d\n"
+ },
+ {0x02040002,
+ "PMU: Error: Failed DWL for nib %d with %d one\n"
+ },
+ {0x02050003,
+ "PMU2: Rising edge not found in alias window with %d one, leaving wrlvlDly for nibble %d = %d\n"
+ },
+ {0x04000000,
+ "PMU: Error:Mailbox Buffer Overflowed.\n"
+ },
+ {0x04010000,
+ "PMU: Error:Mailbox Buffer Overflowed.\n"
+ },
+ {0x04020000,
+ "PMU: ***** Assertion Error - terminating *****\n"
+ },
+ {0x04030002,
+ "PMU1: swapByte db %d by %d\n"
+ },
+ {0x04040003,
+ "PMU3: get_cmd_dly max(%d ps, %d memclk) = %d\n"
+ },
+ {0x04050002,
+ "PMU0: Write CSR 0x%06x 0x%04x\n"
+ },
+ {0x04060002,
+ "PMU0: hwt_init_ppgc_prbs(): Polynomial: %x, Deg: %d\n"
+ },
+ {0x04070001,
+ "PMU: Error: acsm_set_cmd to non existent instruction address %d\n"
+ },
+ {0x04080001,
+ "PMU: Error: acsm_set_cmd with unknown ddr cmd 0x%x\n"
+ },
+ {0x0409000c,
+ "PMU1: acsm_addr %02x, acsm_flgs %04x, ddr_cmd %02x, cmd_dly %02x, ddr_addr %04x, ddr_bnk %02x, ddr_cs %02x, cmd_rcnt %02x, AcsmSeq0/1/2/3 %04x %04x %04x %04x\n"
+ },
+ {0x040a0000,
+ "PMU: Error: Polling on ACSM done failed to complete in acsm_poll_done()...\n"
+ },
+ {0x040b0000,
+ "PMU1: acsm RUN\n"
+ },
+ {0x040c0000,
+ "PMU1: acsm STOPPED\n"
+ },
+ {0x040d0002,
+ "PMU1: acsm_init: acsm_mode %04x mxrdlat %04x\n"
+ },
+ {0x040e0002,
+ "PMU: Error: setAcsmCLCWL: cl and cwl must be each >= 2 and 5, resp. CL=%d CWL=%d\n"
+ },
+ {0x040f0002,
+ "PMU: Error: setAcsmCLCWL: cl and cwl must be each >= 5. CL=%d CWL=%d\n"
+ },
+ {0x04100002,
+ "PMU1: setAcsmCLCWL: CASL %04d WCASL %04d\n"
+ },
+ {0x04110001,
+ "PMU: Error: Reserved value of register F0RC0F found in message block: 0x%04x\n"
+ },
+ {0x04120001,
+ "PMU3: Written MRS to CS=0x%02x\n"
+ },
+ {0x04130001,
+ "PMU3: Written MRS to CS=0x%02x\n"
+ },
+ {0x04140000,
+ "PMU3: Entering Boot Freq Mode.\n"
+ },
+ {0x04150001,
+ "PMU: Error: Boot clock divider setting of %d is too small\n"
+ },
+ {0x04160000,
+ "PMU3: Exiting Boot Freq Mode.\n"
+ },
+ {0x04170002,
+ "PMU3: Writing MR%d OP=%x\n"
+ },
+ {0x04180000,
+ "PMU: Error: Delay too large in slomo\n"
+ },
+ {0x04190001,
+ "PMU3: Written MRS to CS=0x%02x\n"
+ },
+ {0x041a0000,
+ "PMU3: Enable Channel A\n"
+ },
+ {0x041b0000,
+ "PMU3: Enable Channel B\n"
+ },
+ {0x041c0000,
+ "PMU3: Enable All Channels\n"
+ },
+ {0x041d0002,
+ "PMU2: Use PDA mode to set MR%d with value 0x%02x\n"
+ },
+ {0x041e0001,
+ "PMU3: Written Vref with PDA to CS=0x%02x\n"
+ },
+ {0x041f0000,
+ "PMU1: start_cal: DEBUG: setting CalRun to 1\n"
+ },
+ {0x04200000,
+ "PMU1: start_cal: DEBUG: setting CalRun to 0\n"
+ },
+ {0x04210001,
+ "PMU1: lock_pll_dll: DEBUG: pstate = %d\n"
+ },
+ {0x04220001,
+ "PMU1: lock_pll_dll: DEBUG: dfifreqxlat_pstate = %d\n"
+ },
+ {0x04230001,
+ "PMU1: lock_pll_dll: DEBUG: pllbypass = %d\n"
+ },
+ {0x04240001,
+ "PMU3: SaveLcdlSeed: Saving seed %d\n"
+ },
+ {0x04250000,
+ "PMU1: in phy_defaults()\n"
+ },
+ {0x04260003,
+ "PMU3: ACXConf:%d MaxNumDbytes:%d NumDfi:%d\n"
+ },
+ {0x04270005,
+ "PMU1: setAltAcsmCLCWL setting cl=%d cwl=%d\n"
+ },
+};
+#endif /* DEBUG */
+#endif
diff --git a/drivers/nxp/ddr/phy-gen2/phy.c b/drivers/nxp/ddr/phy-gen2/phy.c
new file mode 100644
index 0000000..9c84b00
--- /dev/null
+++ b/drivers/nxp/ddr/phy-gen2/phy.c
@@ -0,0 +1,2669 @@
+/*
+ * Copyright 2021 NXP
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <errno.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include "csr.h"
+#include <ddr.h>
+#include "ddr4fw.h"
+#include <drivers/delay_timer.h>
+#ifdef NXP_WARM_BOOT
+#include <fspi_api.h>
+#endif
+#include "input.h"
+#include <lib/mmio.h>
+#include <lib/utils.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+#ifdef DDR_PHY_DEBUG
+#include "messages.h"
+#endif
+#ifdef NXP_WARM_BOOT
+#include "phy.h"
+#endif
+#include "pie.h"
+
+#define TIMEOUTDEFAULT 500
+#define MAP_PHY_ADDR(pstate, n, instance, offset, c) \
+ ((((pstate * n) + instance + c) << 12) + offset)
+
+static uint32_t map_phy_addr_space(uint32_t addr)
+{
+ /* 23 bit addressing */
+ uint32_t pstate = (addr & U(0x700000)) >> 20U; /* bit 22:20 */
+ uint32_t block_type = (addr & U(0x0f0000)) >> 16U; /* bit 19:16 */
+ uint32_t instance = (addr & U(0x00f000)) >> 12U; /* bit 15:12 */
+ uint32_t offset = (addr & U(0x000fff)); /* bit 11:0 */
+
+ switch (block_type) {
+ case 0x0: /* 0x0 : ANIB */
+ return MAP_PHY_ADDR(pstate, 12, instance, offset, 0);
+ case 0x1: /* 0x1 : DBYTE */
+ return MAP_PHY_ADDR(pstate, 10, instance, offset, 0x30);
+ case 0x2: /* 0x2 : MASTER */
+ return MAP_PHY_ADDR(pstate, 1, 0, offset, 0x58);
+ case 0x4: /* 0x4 : ACSM */
+ return MAP_PHY_ADDR(pstate, 1, 0, offset, 0x5c);
+ case 0x5: /* 0x5 : μCTL Memory */
+ return MAP_PHY_ADDR(pstate, 0, instance, offset, 0x60);
+ case 0x7: /* 0x7 : PPGC */
+ return MAP_PHY_ADDR(pstate, 0, 0, offset, 0x68);
+ case 0x9: /* 0x9 : INITENG */
+ return MAP_PHY_ADDR(pstate, 1, 0, offset, 0x69);
+ case 0xc: /* 0xC : DRTUB */
+ return MAP_PHY_ADDR(pstate, 0, 0, offset, 0x6d);
+ case 0xd: /* 0xD : APB Only */
+ return MAP_PHY_ADDR(pstate, 0, 0, offset, 0x6e);
+ default:
+ printf("ERR: Invalid block_type = 0x%x\n", block_type);
+ return 0;
+ }
+}
+
+static inline uint16_t *phy_io_addr(void *phy, uint32_t addr)
+{
+ return phy + (map_phy_addr_space(addr) << 2);
+}
+
+static inline void phy_io_write16(uint16_t *phy, uint32_t addr, uint16_t data)
+{
+ mmio_write_16((uintptr_t)phy_io_addr(phy, addr), data);
+#ifdef DEBUG_PHY_IO
+ printf("0x%06x,0x%x\n", addr, data);
+#endif
+}
+
+static inline uint16_t phy_io_read16(uint16_t *phy, uint32_t addr)
+{
+ uint16_t reg = mmio_read_16((uintptr_t) phy_io_addr(phy, addr));
+
+#ifdef DEBUG_PHY_IO
+ printf("R: 0x%06x,0x%x\n", addr, reg);
+#endif
+
+ return reg;
+}
+
+#ifdef NXP_APPLY_MAX_CDD
+
+#define CDD_VAL_READ_ADDR (0x054012)
+#define CDD_DATA_LEN (60)
+
+static void read_phy_reg(uint16_t *phy, uint32_t addr,
+ uint16_t *buf, uint32_t len)
+{
+ uint32_t i = 0U;
+
+ for (i = 0U; i < len/2; i++) {
+ buf[i] = phy_io_read16(phy, (addr + i));
+ }
+}
+
+static uint32_t findrank(uint32_t cs_in_use)
+{
+ uint32_t val = 0U;
+
+ switch (cs_in_use) {
+ case U(0xf):
+ val = 4U;
+ break;
+ case U(0x3):
+ val = 2U;
+ break;
+ case U(0x1):
+ val = 1U;
+ break;
+ default:
+ printf("Error - Invalid cs_in_use value\n");
+ }
+ return val;
+}
+
+static uint8_t findmax(uint8_t *buf, uint32_t len)
+{
+ uint8_t max = 0U;
+ uint32_t i = 0U;
+
+ for (i = 0U; i < len; i++) {
+ if (buf[i] > max) {
+ max = buf[i];
+ }
+ }
+
+ return max;
+}
+
+static void get_cdd_val(uint16_t **phy_ptr, uint32_t rank, uint32_t freq,
+ uint32_t *tcfg0, uint32_t *tcfg4)
+{
+ uint8_t cdd[CDD_DATA_LEN+4] = {0U};
+ uint32_t i, val = 0U;
+ uint16_t *phy;
+ uint8_t buf[16] = {U(0x0)};
+ uint8_t trr = 0U, tww = 0U, trw = 0U, twr = 0U;
+ uint8_t rrmax = 0U, wwmax = 0U, rwmax = 0U, wrmax = 0U;
+ uint8_t tmp = U(0x0);
+ uint8_t *c = NULL;
+
+ for (i = 0U; i < NUM_OF_DDRC; i++) {
+
+ phy = phy_ptr[i];
+ if (phy == NULL) {
+ continue;
+ }
+
+ phy_io_write16(phy, t_apbonly |
+ csr_micro_cont_mux_sel_addr, U(0x0));
+
+ read_phy_reg(phy, CDD_VAL_READ_ADDR,
+ (uint16_t *)&cdd, CDD_DATA_LEN);
+
+ phy_io_write16(phy, t_apbonly |
+ csr_micro_cont_mux_sel_addr, U(0x1));
+
+ /* CDD values and address
+ *
+ * 0x054012 0x24 cdd[0] CDD[X][X]
+ * 0x054012 0x25 cdd[1] RR[3][2]
+ * 0x054013 0x26 cdd[2] RR[3][1]
+ * 0x054013 0x27 cdd[3] RR[3][0]
+ * 0x054014 0x28 cdd[4] RR[2][3]
+ * 0x054014 0x29 cdd[5] RR[2][1]
+ * 0x054015 0x2a cdd[6] RR[2][0]
+ * 0x054015 0x2b cdd[7] RR[1][3]
+ * 0x054016 0x2c cdd[8] RR[1][2]
+ * 0x054016 0x2d cdd[9] RR[1][0]
+ * 0x054017 0x2e cdd[10] RR[0][3]
+ * 0x054017 0x2f cdd[11] RR[0][2]
+ * 0x054018 0x30 cdd[12] RR[0][1]
+
+ * 0x054018 0x31 cdd[13] WW[3][2]
+ * 0x054019 0x32 cdd[14] WW[3][1]
+ * 0x054019 0x33 cdd[15] WW[3][0]
+ * 0x05401a 0x34 cdd[16] WW[2][3]
+ * 0x05401a 0x35 cdd[17] WW[2][1]
+ * 0x05401b 0x36 cdd[18] WW[2][0]
+ * 0x05401b 0x37 cdd[19] WW[1][3]
+ * 0x05401c 0x38 cdd[20] WW[1][2]
+ * 0x05401c 0x39 cdd[21] WW[1][0]
+ * 0x05401d 0x3a cdd[22] WW[0][3]
+ * 0x05401d 0x3b cdd[23] WW[0][2]
+ * 0x05401e 0x3c cdd[24] WW[0][1]
+
+ * 0x05401e 0x3d cdd[25] RW[3][3]
+ * 0x05401f 0x3e cdd[26] RW[3][2]
+ * 0x05401f 0x3f cdd[27] RW[3][1]
+ * 0x054020 0x40 cdd[28] RW[3][0]
+ * 0x054020 0x41 cdd[29] RW[2][3]
+ * 0x054021 0x42 cdd[30] RW[2][2]
+ * 0x054021 0x43 cdd[31] RW[2][1]
+ * 0x054022 0x44 cdd[32] RW[2][0]
+ * 0x054022 0x45 cdd[33] RW[1][3]
+ * 0x054023 0x46 cdd[34] RW[1][2]
+ * 0x054023 0x47 cdd[35] RW[1][1]
+ * 0x054024 0x48 cdd[36] RW[1][0]
+ * 0x054024 0x49 cdd[37] RW[0][3]
+ * 0x054025 0x4a cdd[38] RW[0][2]
+ * 0x054025 0x4b cdd[39] RW[0][1]
+ * 0x054026 0x4c cdd[40] RW[0][0]
+
+ * 0x054026 0x4d cdd[41] WR[3][3]
+ * 0x054027 0x4e cdd[42] WR[3][2]
+ * 0x054027 0x4f cdd[43] WR[3][1]
+ * 0x054028 0x50 cdd[44] WR[3][0]
+ * 0x054028 0x51 cdd[45] WR[2][3]
+ * 0x054029 0x52 cdd[46] WR[2][2]
+ * 0x054029 0x53 cdd[47] WR[2][1]
+ * 0x05402a 0x54 cdd[48] WR[2][0]
+ * 0x05402a 0x55 cdd[49] WR[1][3]
+ * 0x05402b 0x56 cdd[50] WR[1][2]
+ * 0x05402b 0x57 cdd[51] WR[1][1]
+ * 0x05402c 0x58 cdd[52] WR[1][0]
+ * 0x05402c 0x59 cdd[53] WR[0][3]
+ * 0x05402d 0x5a cdd[54] WR[0][2]
+ * 0x05402d 0x5b cdd[55] WR[0][1]
+ * 0x05402e 0x5c cdd[56] WR[0][0]
+ * 0x05402e 0x5d cdd[57] CDD[Y][Y]
+ */
+
+ switch (rank) {
+ case 1U:
+ tmp = rwmax;
+ rwmax = cdd[40];
+ if (tmp > rwmax) {
+ rwmax = tmp;
+ }
+
+ tmp = wrmax;
+ wrmax = cdd[56];
+ if (tmp > wrmax) {
+ wrmax = tmp;
+ }
+
+ break;
+
+ case 2U:
+ buf[0] = cdd[12];
+ buf[1] = cdd[9];
+ tmp = rrmax;
+ rrmax = findmax(buf, 2U);
+ if (tmp > rrmax) {
+ rrmax = tmp;
+ }
+
+ buf[0] = cdd[24];
+ buf[1] = cdd[21];
+ tmp = wwmax;
+ wwmax = findmax(buf, 2U);
+ if (tmp > wwmax) {
+ wwmax = tmp;
+ }
+
+ buf[0] = cdd[40];
+ buf[1] = cdd[39];
+ buf[2] = cdd[36];
+ buf[3] = cdd[35];
+ tmp = rwmax;
+ rwmax = findmax(buf, 4U);
+ if (tmp > rwmax) {
+ rwmax = tmp;
+ }
+
+ buf[0] = cdd[56];
+ buf[1] = cdd[55];
+ buf[2] = cdd[52];
+ buf[3] = cdd[51];
+ tmp = wrmax;
+ wrmax = findmax(buf, 4U);
+ if (tmp > wrmax) {
+ wrmax = tmp;
+ }
+
+ break;
+
+ case 4U:
+ tmp = rrmax;
+ c = &cdd[1];
+ rrmax = findmax(c, 12U);
+ if (tmp > rrmax) {
+ rrmax = tmp;
+ }
+
+ tmp = wwmax;
+ c = &cdd[13];
+ wwmax = findmax(c, 12U);
+ if (tmp > wwmax) {
+ wwmax = tmp;
+ }
+
+ tmp = rwmax;
+ c = &cdd[25];
+ rwmax = findmax(c, 16U);
+ if (tmp > rwmax) {
+ rwmax = tmp;
+ }
+
+ tmp = wrmax;
+ c = &cdd[41];
+ wrmax = findmax(c, 16U);
+ if (tmp > wrmax) {
+ wrmax = tmp;
+ }
+
+ break;
+
+ }
+ }
+
+ rrmax += 3U;
+ wwmax += 4U;
+
+ if (wwmax > 7U) {
+ wwmax = 7U;
+ }
+
+ if (rrmax > 7U) {
+ rrmax = 7U;
+ }
+
+ if (wrmax > U(0xf)) {
+ wrmax = 0U;
+ }
+
+ if (rwmax > U(0x7)) {
+ rwmax = U(0x7);
+ }
+
+ val = *tcfg0;
+ tww = (val >> 24U) & U(0x3);
+ trr = (val >> 26U) & U(0x3);
+ twr = (val >> 28U) & U(0x3);
+ trw = (val >> 30U) & U(0x3);
+
+ val = *tcfg4;
+ tww = tww | (((val >> 8U) & U(0x1)) << 2U);
+ trr = trr | (((val >> 10U) & U(0x1)) << 2U);
+ twr = twr | (((val >> 12U) & U(0x1)) << 2U);
+ trw = trw | (((val >> 14U) & U(0x3)) << 2U);
+
+ if (trr > rrmax) {
+ rrmax = trr;
+ }
+
+ if (tww > wwmax) {
+ wwmax = tww;
+ }
+
+ if (trw > rwmax) {
+ rwmax = trw;
+ }
+
+ if (twr > wrmax) {
+ wrmax = twr;
+ }
+
+ debug("CDD rrmax %x wwmax %x rwmax %x wrmax %x\n",
+ rrmax, wwmax, rwmax, wrmax);
+
+ val = ((wwmax & U(0x3)) << 24U)
+ | ((rrmax & U(0x3)) << 26U)
+ | ((wrmax & U(0x3)) << 28U)
+ | ((rwmax & U(0x3)) << 30U);
+
+ *tcfg0 = (*tcfg0 & U(0x00FFFFFF)) | (val);
+
+ val = (((wwmax >> 2U) & U(0x1)) << 8U)
+ | (((rrmax >> 2U) & U(0x1)) << 10U)
+ | (((wrmax >> 2U) & U(0x1)) << 12U)
+ | (((rwmax >> 2U) & U(0x3)) << 14U);
+
+ *tcfg4 = (*tcfg4 & U(0xffff00ff)) | val;
+}
+#endif
+
+#ifdef NXP_WARM_BOOT
+int save_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_store,
+ uint32_t num_of_phy, int train2d)
+{
+ uint16_t *phy = NULL, value = 0x0;
+ uint32_t size = 1U, num_of_regs = 1U, phy_store = 0U;
+ int i = 0, j = 0, ret = -EINVAL;
+
+ ret = xspi_sector_erase(address_to_store, PHY_ERASE_SIZE);
+ if (ret != 0) {
+ return -EINVAL;
+ }
+
+ for (j = 0; j < num_of_phy; j++) {
+ /* Save training values of all PHYs */
+ phy = phy_ptr[j];
+ size = sizeof(training_1D_values);
+ num_of_regs = ARRAY_SIZE(training_1D_values);
+
+ /* Enable access to the internal CSRs */
+ phy_io_write16(phy, t_apbonly |
+ csr_micro_cont_mux_sel_addr, 0x0);
+ /* Enable clocks in case they were disabled. */
+ phy_io_write16(phy, t_drtub |
+ csr_ucclk_hclk_enables_addr, 0x3);
+ if (train2d != 0) {
+ /* Address to store training values is
+ * to be appended for next PHY
+ */
+ phy_store = address_to_store + (j *
+ (sizeof(training_1D_values) +
+ sizeof(training_2D_values)));
+ } else {
+ phy_store = address_to_store + (j *
+ (sizeof(training_1D_values)));
+ }
+ debug("Saving 1D Training reg val at: %d\n", phy_store);
+ for (i = 0; i < num_of_regs; i++) {
+ value = phy_io_read16(phy, training_1D_values[i].addr);
+#ifdef DEBUG_WARM_RESET
+ debug("%d. Reg: %x, value: %x PHY: %p\n", i,
+ training_1D_values[i].addr, value,
+ phy_io_addr(phy,
+ training_1D_values[i].addr));
+#endif
+ training_1D_values[i].data = value;
+ }
+ /* Storing 1D training values on flash */
+ ret = xspi_write(phy_store, (void *)training_1D_values, size);
+ if (train2d != 0) {
+ phy_store = phy_store+size;
+ size = sizeof(training_2D_values);
+ num_of_regs = ARRAY_SIZE(training_2D_values);
+ debug("Saving 2D Training reg val at:%d\n", phy_store);
+ for (i = 0; i < num_of_regs; i++) {
+ value = phy_io_read16(phy,
+ training_2D_values[i].addr);
+ training_2D_values[i].data = value;
+#ifdef DEBUG_WARM_RESET
+ debug("%d.2D addr:0x%x,val:0x%x,PHY:0x%p\n",
+ i, training_2D_values[i].addr,
+ value, phy_io_addr(phy,
+ training_2D_values[i].addr));
+#endif
+ }
+ /* Storing 2D training values on flash */
+ ret = xspi_write(phy_store, training_2D_values,
+ size);
+ }
+ /* Disable clocks in case they were disabled. */
+ phy_io_write16(phy, t_drtub |
+ csr_ucclk_hclk_enables_addr, 0x0);
+ /* Disable access to the internal CSRs */
+ phy_io_write16(phy, t_apbonly |
+ csr_micro_cont_mux_sel_addr, 0x1);
+ }
+ if (ret != 0) {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int restore_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_restore,
+ uint32_t num_of_phy, int train2d)
+{
+ uint16_t *phy = NULL;
+ uint32_t size = 1U, num_of_regs = 1U, phy_store = 0U;
+ int i = 0, j = 0, ret = -EINVAL;
+
+ debug("Restoring Training register values\n");
+ for (j = 0; j < num_of_phy; j++) {
+ phy = phy_ptr[j];
+ size = sizeof(training_1D_values);
+ num_of_regs = ARRAY_SIZE(training_1D_values);
+ if (train2d != 0) {
+ /* The address to restore training values is
+ * to be appended for next PHY
+ */
+ phy_store = address_to_restore + (j *
+ (sizeof(training_1D_values) +
+ sizeof(training_2D_values)));
+ } else {
+ phy_store = address_to_restore + (j *
+ (sizeof(training_1D_values)));
+ }
+ /* Enable access to the internal CSRs */
+ phy_io_write16(phy, t_apbonly |
+ csr_micro_cont_mux_sel_addr, 0x0);
+ /* Enable clocks in case they were disabled. */
+ phy_io_write16(phy, t_drtub |
+ csr_ucclk_hclk_enables_addr, 0x3);
+
+ /* Reading 1D training values from flash*/
+ ret = xspi_read(phy_store, (uint32_t *)training_1D_values,
+ size);
+ debug("Restoring 1D Training reg val at:%08x\n", phy_store);
+ for (i = 0; i < num_of_regs; i++) {
+ phy_io_write16(phy, training_1D_values[i].addr,
+ training_1D_values[i].data);
+#ifdef DEBUG_WARM_RESET
+ debug("%d. Reg: %x, value: %x PHY: %p\n", i,
+ training_1D_values[i].addr,
+ training_1D_values[i].data,
+ phy_io_addr(phy,
+ training_1D_values[i].addr));
+#endif
+ }
+ if (train2d != 0) {
+ phy_store = phy_store + size;
+ size = sizeof(training_2D_values);
+ num_of_regs = ARRAY_SIZE(training_2D_values);
+ /* Reading 2D training values from flash */
+ ret = xspi_read(phy_store,
+ (uint32_t *)training_2D_values, size);
+ debug("Restoring 2D Training reg val at:%08x\n",
+ phy_store);
+ for (i = 0; i < num_of_regs; i++) {
+ phy_io_write16(phy, training_2D_values[i].addr,
+ training_2D_values[i].data);
+#ifdef DEBUG_WARM_RESET
+ debug("%d. Reg: %x, value: %x PHY: %p\n", i,
+ training_2D_values[i].addr,
+ training_2D_values[i].data,
+ phy_io_addr(phy,
+ training_1D_values[i].addr));
+#endif
+ }
+ }
+ /* Disable clocks in case they were disabled. */
+ phy_io_write16(phy, t_drtub |
+ csr_ucclk_hclk_enables_addr, 0x0);
+ /* Disable access to the internal CSRs */
+ phy_io_write16(phy, t_apbonly |
+ csr_micro_cont_mux_sel_addr, 0x1);
+ }
+ if (ret != 0) {
+ return -EINVAL;
+ }
+ return 0;
+}
+#endif
+
+static void load_pieimage(uint16_t *phy,
+ enum dimm_types dimm_type)
+{
+ int i;
+ int size;
+ const struct pie *image = NULL;
+
+ switch (dimm_type) {
+ case UDIMM:
+ case SODIMM:
+ case NODIMM:
+ image = pie_udimm;
+ size = ARRAY_SIZE(pie_udimm);
+ break;
+ case RDIMM:
+ image = pie_rdimm;
+ size = ARRAY_SIZE(pie_rdimm);
+ break;
+ case LRDIMM:
+ image = pie_lrdimm;
+ size = ARRAY_SIZE(pie_lrdimm);
+ break;
+ default:
+ printf("Unsupported DIMM type\n");
+ break;
+ }
+
+ if (image != NULL) {
+ for (i = 0; i < size; i++)
+ phy_io_write16(phy, image[i].addr, image[i].data);
+ }
+}
+
+static void prog_acsm_playback(uint16_t *phy,
+ const struct input *input, const void *msg)
+{
+ int vec;
+ const struct ddr4r1d *msg_blk;
+ uint16_t acsmplayback[2][3];
+ uint32_t f0rc0a;
+ uint32_t f0rc3x;
+ uint32_t f0rc5x;
+
+ if (input->basic.dimm_type != RDIMM) {
+ return;
+ }
+
+ msg_blk = msg;
+ f0rc0a = (msg_blk->f0rc0a_d0 & U(0xf)) | U(0xa0);
+ f0rc3x = (msg_blk->f0rc3x_d0 & U(0xff)) | U(0x300);
+ f0rc5x = (input->adv.phy_gen2_umctl_f0rc5x & U(0xff)) | U(0x500);
+
+ acsmplayback[0][0] = U(0x3ff) & f0rc0a;
+ acsmplayback[1][0] = (U(0x1c00) & f0rc0a) >> 10U;
+ acsmplayback[0][1] = U(0x3ff) & f0rc3x;
+ acsmplayback[1][1] = (U(0x1c00) & f0rc3x) >> 10U;
+ acsmplayback[0][2] = U(0x3ff) & f0rc5x;
+ acsmplayback[1][2] = (U(0x1c00) & f0rc5x) >> 10U;
+ for (vec = 0; vec < 3; vec++) {
+ phy_io_write16(phy, t_acsm | (csr_acsm_playback0x0_addr +
+ (vec << 1)), acsmplayback[0][vec]);
+ phy_io_write16(phy, t_acsm | (csr_acsm_playback1x0_addr +
+ (vec << 1)), acsmplayback[1][vec]);
+ }
+}
+
+static void prog_acsm_ctr(uint16_t *phy,
+ const struct input *input)
+{
+ if (input->basic.dimm_type != RDIMM) {
+ return;
+ }
+
+ phy_io_write16(phy, t_acsm | csr_acsm_ctrl13_addr,
+ 0xf << csr_acsm_cke_enb_lsb);
+
+ phy_io_write16(phy, t_acsm | csr_acsm_ctrl0_addr,
+ csr_acsm_par_mode_mask | csr_acsm_2t_mode_mask);
+}
+
+static void prog_cal_rate_run(uint16_t *phy,
+ const struct input *input)
+{
+ int cal_rate;
+ int cal_interval;
+ int cal_once;
+ uint32_t addr;
+
+ cal_interval = input->adv.cal_interval;
+ cal_once = input->adv.cal_once;
+ cal_rate = 0x1 << csr_cal_run_lsb |
+ cal_once << csr_cal_once_lsb |
+ cal_interval << csr_cal_interval_lsb;
+ addr = t_master | csr_cal_rate_addr;
+ phy_io_write16(phy, addr, cal_rate);
+}
+
+static void prog_seq0bdly0(uint16_t *phy,
+ const struct input *input)
+{
+ int ps_count[4];
+ int frq;
+ uint32_t addr;
+ int lower_freq_opt = 0;
+
+ __unused const soc_info_t *soc_info;
+
+ frq = input->basic.frequency >> 1;
+ ps_count[0] = frq >> 3; /* 0.5 * frq / 4*/
+ if (input->basic.frequency < 400) {
+ lower_freq_opt = (input->basic.dimm_type == RDIMM) ? 7 : 3;
+ } else if (input->basic.frequency < 533) {
+ lower_freq_opt = (input->basic.dimm_type == RDIMM) ? 14 : 11;
+ }
+
+ /* 1.0 * frq / 4 - lower_freq */
+ ps_count[1] = (frq >> 2) - lower_freq_opt;
+ ps_count[2] = (frq << 1) + (frq >> 1); /* 10.0 * frq / 4 */
+
+#ifdef DDR_PLL_FIX
+ soc_info = get_soc_info();
+ if (soc_info->svr_reg.bf.maj_ver == 1) {
+ ps_count[0] = 0x520; /* seq0bdly0 */
+ ps_count[1] = 0xa41; /* seq0bdly1 */
+ ps_count[2] = 0x668a; /* seq0bdly2 */
+ }
+#endif
+ if (frq > 266) {
+ ps_count[3] = 44;
+ } else if (frq > 200) {
+ ps_count[3] = 33;
+ } else {
+ ps_count[3] = 16;
+ }
+
+ addr = t_master | csr_seq0bdly0_addr;
+ phy_io_write16(phy, addr, ps_count[0]);
+
+ debug("seq0bdly0 = 0x%x\n", phy_io_read16(phy, addr));
+
+ addr = t_master | csr_seq0bdly1_addr;
+ phy_io_write16(phy, addr, ps_count[1]);
+
+ debug("seq0bdly1 = 0x%x\n", phy_io_read16(phy, addr));
+
+ addr = t_master | csr_seq0bdly2_addr;
+ phy_io_write16(phy, addr, ps_count[2]);
+
+ debug("seq0bdly2 = 0x%x\n", phy_io_read16(phy, addr));
+
+ addr = t_master | csr_seq0bdly3_addr;
+ phy_io_write16(phy, addr, ps_count[3]);
+
+ debug("seq0bdly3 = 0x%x\n", phy_io_read16(phy, addr));
+}
+
+/* Only RDIMM requires msg_blk */
+static void i_load_pie(uint16_t **phy_ptr,
+ const struct input *input,
+ const void *msg)
+{
+ int i;
+ uint16_t *phy;
+
+ for (i = 0; i < NUM_OF_DDRC; i++) {
+ phy = phy_ptr[i];
+ if (phy == NULL) {
+ continue;
+ }
+
+ phy_io_write16(phy,
+ t_apbonly | csr_micro_cont_mux_sel_addr,
+ 0U);
+
+ load_pieimage(phy, input->basic.dimm_type);
+
+ prog_seq0bdly0(phy, input);
+ phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag0_addr,
+ U(0x0000));
+ phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag1_addr,
+ U(0x0173));
+ phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag2_addr,
+ U(0x0060));
+ phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag3_addr,
+ U(0x6110));
+ phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag4_addr,
+ U(0x2152));
+ phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag5_addr,
+ U(0xdfbd));
+ phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag6_addr,
+ input->basic.dimm_type == RDIMM &&
+ input->adv.phy_gen2_umctl_opt == 1U ?
+ U(0x6000) : U(0xffff));
+ phy_io_write16(phy, t_initeng | csr_seq0bdisable_flag7_addr,
+ U(0x6152));
+ prog_acsm_playback(phy, input, msg); /* rdimm */
+ prog_acsm_ctr(phy, input); /* rdimm */
+
+ phy_io_write16(phy, t_master | csr_cal_zap_addr, U(0x1));
+ prog_cal_rate_run(phy, input);
+
+ phy_io_write16(phy, t_drtub | csr_ucclk_hclk_enables_addr,
+ input->basic.dimm_type == RDIMM ? U(0x2) : 0U);
+
+ phy_io_write16(phy, t_apbonly | csr_micro_cont_mux_sel_addr, 1U);
+ }
+}
+
+static void phy_gen2_init_input(struct input *input)
+{
+ int i;
+
+ input->adv.dram_byte_swap = 0;
+ input->adv.ext_cal_res_val = 0;
+ input->adv.tx_slew_rise_dq = 0xf;
+ input->adv.tx_slew_fall_dq = 0xf;
+ input->adv.tx_slew_rise_ac = 0xf;
+ input->adv.tx_slew_fall_ac = 0xf;
+ input->adv.mem_alert_en = 0;
+ input->adv.mem_alert_puimp = 5;
+ input->adv.mem_alert_vref_level = 0x29;
+ input->adv.mem_alert_sync_bypass = 0;
+ input->adv.cal_interval = 0x9;
+ input->adv.cal_once = 0;
+ input->adv.dis_dyn_adr_tri = 0;
+ input->adv.is2ttiming = 0;
+ input->adv.d4rx_preamble_length = 0;
+ input->adv.d4tx_preamble_length = 0;
+
+ for (i = 0; i < 7; i++) {
+ debug("mr[%d] = 0x%x\n", i, input->mr[i]);
+ }
+
+ debug("input->cs_d0 = 0x%x\n", input->cs_d0);
+ debug("input->cs_d1 = 0x%x\n", input->cs_d1);
+ debug("input->mirror = 0x%x\n", input->mirror);
+ debug("PHY ODT impedance = %d ohm\n", input->adv.odtimpedance);
+ debug("PHY DQ driver impedance = %d ohm\n", input->adv.tx_impedance);
+ debug("PHY Addr driver impedance = %d ohm\n", input->adv.atx_impedance);
+
+ for (i = 0; i < 4; i++) {
+ debug("odt[%d] = 0x%x\n", i, input->odt[i]);
+ }
+
+ if (input->basic.dimm_type == RDIMM) {
+ for (i = 0; i < 16; i++) {
+ debug("input->rcw[%d] = 0x%x\n", i, input->rcw[i]);
+ }
+ debug("input->rcw3x = 0x%x\n", input->rcw3x);
+ }
+}
+
+/*
+ * All protocols share the same base structure of message block.
+ * RDIMM and LRDIMM have more entries defined than UDIMM.
+ * Create message blocks for 1D and 2D training.
+ * Update len with message block size.
+ */
+static int phy_gen2_msg_init(void *msg_1d,
+ void *msg_2d,
+ const struct input *input)
+{
+ struct ddr4u1d *msg_blk = msg_1d;
+ struct ddr4u2d *msg_blk_2d = msg_2d;
+ struct ddr4r1d *msg_blk_r;
+ struct ddr4lr1d *msg_blk_lr;
+
+ switch (input->basic.dimm_type) {
+ case UDIMM:
+ case SODIMM:
+ case NODIMM:
+ msg_blk->dram_type = U(0x2);
+ break;
+ case RDIMM:
+ msg_blk->dram_type = U(0x4);
+ break;
+ case LRDIMM:
+ msg_blk->dram_type = U(0x5);
+ break;
+ default:
+ ERROR("Unsupported DIMM type\n");
+ return -EINVAL;
+ }
+ msg_blk->pstate = 0U;
+
+ /*Enable quickRd2D, a substage of read deskew, to 1D training.*/
+ msg_blk->reserved00 = U(0x20);
+
+ /*Enable High-Effort WrDQ1D.*/
+ msg_blk->reserved00 |= U(0x40);
+
+ /* Enable 1D extra effort training.*/
+ msg_blk->reserved1c[3] = U(0x3);
+
+ if (input->basic.dimm_type == LRDIMM) {
+ msg_blk->sequence_ctrl = U(0x3f1f);
+ } else {
+ msg_blk->sequence_ctrl = U(0x031f);
+ }
+ msg_blk->phy_config_override = 0U;
+#ifdef DDR_PHY_DEBUG
+ msg_blk->hdt_ctrl = U(0x5);
+#else
+ msg_blk->hdt_ctrl = U(0xc9);
+#endif
+ msg_blk->msg_misc = U(0x0);
+ msg_blk->dfimrlmargin = U(0x1);
+ msg_blk->phy_vref = input->vref ? input->vref : U(0x61);
+ msg_blk->cs_present = input->cs_d0 | input->cs_d1;
+ msg_blk->cs_present_d0 = input->cs_d0;
+ msg_blk->cs_present_d1 = input->cs_d1;
+ if (input->mirror != 0) {
+ msg_blk->addr_mirror = U(0x0a); /* odd CS are mirrored */
+ }
+ msg_blk->share2dvref_result = 1U;
+
+ msg_blk->acsm_odt_ctrl0 = input->odt[0];
+ msg_blk->acsm_odt_ctrl1 = input->odt[1];
+ msg_blk->acsm_odt_ctrl2 = input->odt[2];
+ msg_blk->acsm_odt_ctrl3 = input->odt[3];
+ msg_blk->enabled_dqs = (input->basic.num_active_dbyte_dfi0 +
+ input->basic.num_active_dbyte_dfi1) * 8;
+ msg_blk->x16present = input->basic.dram_data_width == 0x10 ?
+ msg_blk->cs_present : 0;
+ msg_blk->d4misc = U(0x1);
+ msg_blk->cs_setup_gddec = U(0x1);
+ msg_blk->rtt_nom_wr_park0 = 0U;
+ msg_blk->rtt_nom_wr_park1 = 0U;
+ msg_blk->rtt_nom_wr_park2 = 0U;
+ msg_blk->rtt_nom_wr_park3 = 0U;
+ msg_blk->rtt_nom_wr_park4 = 0U;
+ msg_blk->rtt_nom_wr_park5 = 0U;
+ msg_blk->rtt_nom_wr_park6 = 0U;
+ msg_blk->rtt_nom_wr_park7 = 0U;
+ msg_blk->mr0 = input->mr[0];
+ msg_blk->mr1 = input->mr[1];
+ msg_blk->mr2 = input->mr[2];
+ msg_blk->mr3 = input->mr[3];
+ msg_blk->mr4 = input->mr[4];
+ msg_blk->mr5 = input->mr[5];
+ msg_blk->mr6 = input->mr[6];
+ if ((msg_blk->mr4 & U(0x1c0)) != 0U) {
+ ERROR("Setting DRAM CAL mode is not supported\n");
+ }
+
+ msg_blk->alt_cas_l = 0U;
+ msg_blk->alt_wcas_l = 0U;
+
+ msg_blk->dramfreq = input->basic.frequency * 2U;
+ msg_blk->pll_bypass_en = input->basic.pll_bypass;
+ msg_blk->dfi_freq_ratio = input->basic.dfi_freq_ratio == 0U ? 1U :
+ input->basic.dfi_freq_ratio == 1U ? 2U :
+ 4U;
+ msg_blk->bpznres_val = input->adv.ext_cal_res_val;
+ msg_blk->disabled_dbyte = 0U;
+
+ debug("msg_blk->dram_type = 0x%x\n", msg_blk->dram_type);
+ debug("msg_blk->sequence_ctrl = 0x%x\n", msg_blk->sequence_ctrl);
+ debug("msg_blk->phy_cfg = 0x%x\n", msg_blk->phy_cfg);
+ debug("msg_blk->x16present = 0x%x\n", msg_blk->x16present);
+ debug("msg_blk->dramfreq = 0x%x\n", msg_blk->dramfreq);
+ debug("msg_blk->pll_bypass_en = 0x%x\n", msg_blk->pll_bypass_en);
+ debug("msg_blk->dfi_freq_ratio = 0x%x\n", msg_blk->dfi_freq_ratio);
+ debug("msg_blk->phy_odt_impedance = 0x%x\n",
+ msg_blk->phy_odt_impedance);
+ debug("msg_blk->phy_drv_impedance = 0x%x\n",
+ msg_blk->phy_drv_impedance);
+ debug("msg_blk->bpznres_val = 0x%x\n", msg_blk->bpznres_val);
+ debug("msg_blk->enabled_dqs = 0x%x\n", msg_blk->enabled_dqs);
+ debug("msg_blk->acsm_odt_ctrl0 = 0x%x\n", msg_blk->acsm_odt_ctrl0);
+ debug("msg_blk->acsm_odt_ctrl1 = 0x%x\n", msg_blk->acsm_odt_ctrl1);
+ debug("msg_blk->acsm_odt_ctrl2 = 0x%x\n", msg_blk->acsm_odt_ctrl2);
+ debug("msg_blk->acsm_odt_ctrl3 = 0x%x\n", msg_blk->acsm_odt_ctrl3);
+
+ /* RDIMM only */
+ if (input->basic.dimm_type == RDIMM ||
+ input->basic.dimm_type == LRDIMM) {
+ msg_blk_r = (struct ddr4r1d *)msg_blk;
+ if (msg_blk_r->cs_present_d0 != 0U) {
+ msg_blk_r->f0rc00_d0 = input->rcw[0];
+ msg_blk_r->f0rc01_d0 = input->rcw[1];
+ msg_blk_r->f0rc02_d0 = input->rcw[2];
+ msg_blk_r->f0rc03_d0 = input->rcw[3];
+ msg_blk_r->f0rc04_d0 = input->rcw[4];
+ msg_blk_r->f0rc05_d0 = input->rcw[5];
+ msg_blk_r->f0rc06_d0 = input->rcw[6];
+ msg_blk_r->f0rc07_d0 = input->rcw[7];
+ msg_blk_r->f0rc08_d0 = input->rcw[8];
+ msg_blk_r->f0rc09_d0 = input->rcw[9];
+ msg_blk_r->f0rc0a_d0 = input->rcw[10];
+ msg_blk_r->f0rc0b_d0 = input->rcw[11];
+ msg_blk_r->f0rc0c_d0 = input->rcw[12];
+ msg_blk_r->f0rc0d_d0 = input->rcw[13];
+ msg_blk_r->f0rc0e_d0 = input->rcw[14];
+ msg_blk_r->f0rc0f_d0 = input->rcw[15];
+ msg_blk_r->f0rc3x_d0 = input->rcw3x;
+ }
+ if (msg_blk_r->cs_present_d1 != 0) {
+ msg_blk_r->f0rc00_d1 = input->rcw[0];
+ msg_blk_r->f0rc01_d1 = input->rcw[1];
+ msg_blk_r->f0rc02_d1 = input->rcw[2];
+ msg_blk_r->f0rc03_d1 = input->rcw[3];
+ msg_blk_r->f0rc04_d1 = input->rcw[4];
+ msg_blk_r->f0rc05_d1 = input->rcw[5];
+ msg_blk_r->f0rc06_d1 = input->rcw[6];
+ msg_blk_r->f0rc07_d1 = input->rcw[7];
+ msg_blk_r->f0rc08_d1 = input->rcw[8];
+ msg_blk_r->f0rc09_d1 = input->rcw[9];
+ msg_blk_r->f0rc0a_d1 = input->rcw[10];
+ msg_blk_r->f0rc0b_d1 = input->rcw[11];
+ msg_blk_r->f0rc0c_d1 = input->rcw[12];
+ msg_blk_r->f0rc0d_d1 = input->rcw[13];
+ msg_blk_r->f0rc0e_d1 = input->rcw[14];
+ msg_blk_r->f0rc0f_d1 = input->rcw[15];
+ msg_blk_r->f0rc3x_d1 = input->rcw3x;
+ }
+ if (input->basic.dimm_type == LRDIMM) {
+ msg_blk_lr = (struct ddr4lr1d *)msg_blk;
+ msg_blk_lr->bc0a_d0 = msg_blk_lr->f0rc0a_d0;
+ msg_blk_lr->bc0a_d1 = msg_blk_lr->f0rc0a_d1;
+ msg_blk_lr->f0bc6x_d0 = msg_blk_lr->f0rc3x_d0;
+ msg_blk_lr->f0bc6x_d1 = msg_blk_lr->f0rc3x_d1;
+ }
+ }
+
+ /* below is different for 1D and 2D message block */
+ if (input->basic.train2d != 0) {
+ memcpy(msg_blk_2d, msg_blk, sizeof(struct ddr4u1d));
+ /*High-Effort WrDQ1D is applicable to 2D traning also*/
+ msg_blk_2d->reserved00 |= U(0x40);
+ msg_blk_2d->sequence_ctrl = U(0x0061);
+ msg_blk_2d->rx2d_train_opt = 0U;
+ msg_blk_2d->tx2d_train_opt = 0U;
+ msg_blk_2d->share2dvref_result = 1U;
+ msg_blk_2d->delay_weight2d = U(0x20);
+ msg_blk_2d->voltage_weight2d = U(0x80);
+ debug("rx2d_train_opt %d, tx2d_train_opt %d\n",
+ msg_blk_2d->rx2d_train_opt,
+ msg_blk_2d->tx2d_train_opt);
+ }
+
+ msg_blk->phy_cfg = (((msg_blk->mr3 & U(0x8)) != 0U) ||
+ ((msg_blk_2d->mr3 & 0x8) != 0U)) ? 0U
+ : input->adv.is2ttiming;
+
+ return 0;
+}
+
+static void prog_tx_pre_drv_mode(uint16_t *phy,
+ const struct input *input)
+{
+ int lane, byte, b_addr, c_addr, p_addr;
+ int tx_slew_rate, tx_pre_p, tx_pre_n;
+ int tx_pre_drv_mode = 0x2;
+ uint32_t addr;
+
+ /* Program TxPreDrvMode with 0x2 */
+ /* FIXME: TxPreDrvMode depends on DramType? */
+ tx_pre_p = input->adv.tx_slew_rise_dq;
+ tx_pre_n = input->adv.tx_slew_fall_dq;
+ tx_slew_rate = tx_pre_drv_mode << csr_tx_pre_drv_mode_lsb |
+ tx_pre_p << csr_tx_pre_p_lsb |
+ tx_pre_n << csr_tx_pre_n_lsb;
+ p_addr = 0;
+ for (byte = 0; byte < input->basic.num_dbyte; byte++) {
+ c_addr = byte << 12;
+ for (lane = 0; lane <= 1; lane++) {
+ b_addr = lane << 8;
+ addr = p_addr | t_dbyte | c_addr | b_addr |
+ csr_tx_slew_rate_addr;
+ phy_io_write16(phy, addr, tx_slew_rate);
+ }
+ }
+}
+
+static void prog_atx_pre_drv_mode(uint16_t *phy,
+ const struct input *input)
+{
+ int anib, c_addr;
+ int atx_slew_rate, atx_pre_p, atx_pre_n, atx_pre_drv_mode,
+ ck_anib_inst[2];
+ uint32_t addr;
+
+ atx_pre_n = input->adv.tx_slew_fall_ac;
+ atx_pre_p = input->adv.tx_slew_rise_ac;
+
+ if (input->basic.num_anib == 8) {
+ ck_anib_inst[0] = 1;
+ ck_anib_inst[1] = 1;
+ } else if (input->basic.num_anib == 10 || input->basic.num_anib == 12 ||
+ input->basic.num_anib == 13) {
+ ck_anib_inst[0] = 4;
+ ck_anib_inst[1] = 5;
+ } else {
+ ERROR("Invalid number of aNIBs: %d\n", input->basic.num_anib);
+ return;
+ }
+
+ for (anib = 0; anib < input->basic.num_anib; anib++) {
+ c_addr = anib << 12;
+ if (anib == ck_anib_inst[0] || anib == ck_anib_inst[1]) {
+ atx_pre_drv_mode = 0;
+ } else {
+ atx_pre_drv_mode = 3;
+ }
+ atx_slew_rate = atx_pre_drv_mode << csr_atx_pre_drv_mode_lsb |
+ atx_pre_n << csr_atx_pre_n_lsb |
+ atx_pre_p << csr_atx_pre_p_lsb;
+ addr = t_anib | c_addr | csr_atx_slew_rate_addr;
+ phy_io_write16(phy, addr, atx_slew_rate);
+ }
+}
+
+static void prog_enable_cs_multicast(uint16_t *phy,
+ const struct input *input)
+{
+ uint32_t addr = t_master | csr_enable_cs_multicast_addr;
+
+ if (input->basic.dimm_type != RDIMM &&
+ input->basic.dimm_type != LRDIMM) {
+ return;
+ }
+
+ phy_io_write16(phy, addr, input->adv.cast_cs_to_cid);
+}
+
+static void prog_dfi_rd_data_cs_dest_map(uint16_t *phy,
+ unsigned int ip_rev,
+ const struct input *input,
+ const struct ddr4lr1d *msg)
+{
+ const struct ddr4lr1d *msg_blk;
+ uint16_t dfi_xxdestm0 = 0U;
+ uint16_t dfi_xxdestm1 = 0U;
+ uint16_t dfi_xxdestm2 = 0U;
+ uint16_t dfi_xxdestm3 = 0U;
+ uint16_t dfi_rd_data_cs_dest_map;
+ uint16_t dfi_wr_data_cs_dest_map;
+ __unused const soc_info_t *soc_info;
+
+#ifdef ERRATA_DDR_A011396
+ /* Only apply to DDRC 5.05.00 */
+ soc_info = get_soc_info();
+ if ((soc_info->svr_reg.bf.maj_ver == 1U) && (ip_rev == U(0x50500))) {
+ phy_io_write16(phy,
+ t_master | csr_dfi_rd_data_cs_dest_map_addr,
+ 0U);
+ return;
+ }
+#endif
+
+ msg_blk = msg;
+
+ switch (input->basic.dimm_type) {
+ case UDIMM:
+ case SODIMM:
+ case NODIMM:
+ if ((msg_blk->msg_misc & U(0x40)) != 0U) {
+ dfi_rd_data_cs_dest_map = U(0xa0);
+ dfi_wr_data_cs_dest_map = U(0xa0);
+
+ phy_io_write16(phy,
+ t_master | csr_dfi_rd_data_cs_dest_map_addr,
+ dfi_rd_data_cs_dest_map);
+ phy_io_write16(phy,
+ t_master | csr_dfi_wr_data_cs_dest_map_addr,
+ dfi_wr_data_cs_dest_map);
+ }
+ break;
+ case LRDIMM:
+ if (msg->cs_present_d1 != 0U) {
+ dfi_xxdestm2 = 1U;
+ dfi_xxdestm3 = 1U;
+ }
+
+ dfi_rd_data_cs_dest_map =
+ dfi_xxdestm0 << csr_dfi_rd_destm0_lsb |
+ dfi_xxdestm1 << csr_dfi_rd_destm1_lsb |
+ dfi_xxdestm2 << csr_dfi_rd_destm2_lsb |
+ dfi_xxdestm3 << csr_dfi_rd_destm3_lsb;
+ dfi_wr_data_cs_dest_map =
+ dfi_xxdestm0 << csr_dfi_wr_destm0_lsb |
+ dfi_xxdestm1 << csr_dfi_wr_destm1_lsb |
+ dfi_xxdestm2 << csr_dfi_wr_destm2_lsb |
+ dfi_xxdestm3 << csr_dfi_wr_destm3_lsb;
+ phy_io_write16(phy, t_master | csr_dfi_rd_data_cs_dest_map_addr,
+ dfi_rd_data_cs_dest_map);
+ phy_io_write16(phy, t_master | csr_dfi_wr_data_cs_dest_map_addr,
+ dfi_wr_data_cs_dest_map);
+
+ break;
+ default:
+ break;
+ }
+}
+
+static void prog_pll_ctrl(uint16_t *phy,
+ const struct input *input)
+{
+ uint32_t addr;
+ int pll_ctrl1 = 0x21; /* 000100001b */
+ int pll_ctrl4 = 0x17f; /* 101111111b */
+ int pll_test_mode = 0x24; /* 00100100b */
+
+ addr = t_master | csr_pll_ctrl1_addr;
+ phy_io_write16(phy, addr, pll_ctrl1);
+
+ debug("pll_ctrl1 = 0x%x\n", phy_io_read16(phy, addr));
+
+ addr = t_master | csr_pll_test_mode_addr;
+ phy_io_write16(phy, addr, pll_test_mode);
+
+ debug("pll_test_mode = 0x%x\n", phy_io_read16(phy, addr));
+
+ addr = t_master | csr_pll_ctrl4_addr;
+ phy_io_write16(phy, addr, pll_ctrl4);
+
+ debug("pll_ctrl4 = 0x%x\n", phy_io_read16(phy, addr));
+}
+
+static void prog_pll_ctrl2(uint16_t *phy,
+ const struct input *input)
+{
+ int pll_ctrl2;
+ uint32_t addr = t_master | csr_pll_ctrl2_addr;
+
+ if (input->basic.frequency / 2 < 235) {
+ pll_ctrl2 = 0x7;
+ } else if (input->basic.frequency / 2 < 313) {
+ pll_ctrl2 = 0x6;
+ } else if (input->basic.frequency / 2 < 469) {
+ pll_ctrl2 = 0xb;
+ } else if (input->basic.frequency / 2 < 625) {
+ pll_ctrl2 = 0xa;
+ } else if (input->basic.frequency / 2 < 938) {
+ pll_ctrl2 = 0x19;
+ } else if (input->basic.frequency / 2 < 1067) {
+ pll_ctrl2 = 0x18;
+ } else {
+ pll_ctrl2 = 0x19;
+ }
+
+ phy_io_write16(phy, addr, pll_ctrl2);
+
+ debug("pll_ctrl2 = 0x%x\n", phy_io_read16(phy, addr));
+}
+
+static void prog_dll_lck_param(uint16_t *phy, const struct input *input)
+{
+ uint32_t addr = t_master | csr_dll_lockparam_addr;
+
+ phy_io_write16(phy, addr, U(0x212));
+ debug("dll_lck_param = 0x%x\n", phy_io_read16(phy, addr));
+}
+
+static void prog_dll_gain_ctl(uint16_t *phy, const struct input *input)
+{
+ uint32_t addr = t_master | csr_dll_gain_ctl_addr;
+
+ phy_io_write16(phy, addr, U(0x61));
+ debug("dll_gain_ctl = 0x%x\n", phy_io_read16(phy, addr));
+}
+
+static void prog_pll_pwr_dn(uint16_t *phy,
+ const struct input *input)
+{
+ uint32_t addr;
+
+ addr = t_master | csr_pll_pwr_dn_addr;
+ phy_io_write16(phy, addr, 0U);
+
+ debug("pll_pwrdn = 0x%x\n", phy_io_read16(phy, addr));
+}
+
+static void prog_ard_ptr_init_val(uint16_t *phy,
+ const struct input *input)
+{
+ int ard_ptr_init_val;
+ uint32_t addr = t_master | csr_ard_ptr_init_val_addr;
+
+ if (input->basic.frequency >= 933) {
+ ard_ptr_init_val = 0x2;
+ } else {
+ ard_ptr_init_val = 0x1;
+ }
+
+ phy_io_write16(phy, addr, ard_ptr_init_val);
+}
+
+static void prog_dqs_preamble_control(uint16_t *phy,
+ const struct input *input)
+{
+ int data;
+ uint32_t addr = t_master | csr_dqs_preamble_control_addr;
+ const int wdqsextension = 0;
+ const int lp4sttc_pre_bridge_rx_en = 0;
+ const int lp4postamble_ext = 0;
+ const int lp4tgl_two_tck_tx_dqs_pre = 0;
+ const int position_dfe_init = 2;
+ const int dll_rx_preamble_mode = 1;
+ int two_tck_tx_dqs_pre = input->adv.d4tx_preamble_length;
+ int two_tck_rx_dqs_pre = input->adv.d4rx_preamble_length;
+
+ data = wdqsextension << csr_wdqsextension_lsb |
+ lp4sttc_pre_bridge_rx_en << csr_lp4sttc_pre_bridge_rx_en_lsb |
+ lp4postamble_ext << csr_lp4postamble_ext_lsb |
+ lp4tgl_two_tck_tx_dqs_pre << csr_lp4tgl_two_tck_tx_dqs_pre_lsb |
+ position_dfe_init << csr_position_dfe_init_lsb |
+ two_tck_tx_dqs_pre << csr_two_tck_tx_dqs_pre_lsb |
+ two_tck_rx_dqs_pre << csr_two_tck_rx_dqs_pre_lsb;
+ phy_io_write16(phy, addr, data);
+
+ data = dll_rx_preamble_mode << csr_dll_rx_preamble_mode_lsb;
+ addr = t_master | csr_dbyte_dll_mode_cntrl_addr;
+ phy_io_write16(phy, addr, data);
+}
+
+static void prog_proc_odt_time_ctl(uint16_t *phy,
+ const struct input *input)
+{
+ int proc_odt_time_ctl;
+ uint32_t addr = t_master | csr_proc_odt_time_ctl_addr;
+
+ if (input->adv.wdqsext != 0) {
+ proc_odt_time_ctl = 0x3;
+ } else if (input->basic.frequency <= 933) {
+ proc_odt_time_ctl = 0xa;
+ } else if (input->basic.frequency <= 1200) {
+ if (input->adv.d4rx_preamble_length == 1) {
+ proc_odt_time_ctl = 0x2;
+ } else {
+ proc_odt_time_ctl = 0x6;
+ }
+ } else {
+ if (input->adv.d4rx_preamble_length == 1) {
+ proc_odt_time_ctl = 0x3;
+ } else {
+ proc_odt_time_ctl = 0x7;
+ }
+ }
+ phy_io_write16(phy, addr, proc_odt_time_ctl);
+}
+
+static const struct impedance_mapping map[] = {
+ { 29, 0x3f },
+ { 31, 0x3e },
+ { 33, 0x3b },
+ { 36, 0x3a },
+ { 39, 0x39 },
+ { 42, 0x38 },
+ { 46, 0x1b },
+ { 51, 0x1a },
+ { 57, 0x19 },
+ { 64, 0x18 },
+ { 74, 0x0b },
+ { 88, 0x0a },
+ { 108, 0x09 },
+ { 140, 0x08 },
+ { 200, 0x03 },
+ { 360, 0x02 },
+ { 481, 0x01 },
+ {}
+};
+
+static int map_impedance(int strength)
+{
+ const struct impedance_mapping *tbl = map;
+ int val = 0;
+
+ if (strength == 0) {
+ return 0;
+ }
+
+ while (tbl->ohm != 0U) {
+ if (strength < tbl->ohm) {
+ val = tbl->code;
+ break;
+ }
+ tbl++;
+ }
+
+ return val;
+}
+
+static int map_odtstren_p(int strength, int hard_macro_ver)
+{
+ int val = -1;
+
+ if (hard_macro_ver == 4) {
+ if (strength == 0) {
+ val = 0;
+ } else if (strength == 120) {
+ val = 0x8;
+ } else if (strength == 60) {
+ val = 0x18;
+ } else if (strength == 40) {
+ val = 0x38;
+ } else {
+ printf("error: unsupported ODTStrenP %d\n", strength);
+ }
+ } else {
+ val = map_impedance(strength);
+ }
+
+ return val;
+}
+
+static void prog_tx_odt_drv_stren(uint16_t *phy,
+ const struct input *input)
+{
+ int lane, byte, b_addr, c_addr;
+ int tx_odt_drv_stren;
+ int odtstren_p, odtstren_n;
+ uint32_t addr;
+
+ odtstren_p = map_odtstren_p(input->adv.odtimpedance,
+ input->basic.hard_macro_ver);
+ if (odtstren_p < 0) {
+ return;
+ }
+
+ odtstren_n = 0; /* always high-z */
+ tx_odt_drv_stren = odtstren_n << csr_odtstren_n_lsb | odtstren_p;
+ for (byte = 0; byte < input->basic.num_dbyte; byte++) {
+ c_addr = byte << 12;
+ for (lane = 0; lane <= 1; lane++) {
+ b_addr = lane << 8;
+ addr = t_dbyte | c_addr | b_addr |
+ csr_tx_odt_drv_stren_addr;
+ phy_io_write16(phy, addr, tx_odt_drv_stren);
+ }
+ }
+}
+
+static int map_drvstren_fsdq_p(int strength, int hard_macro_ver)
+{
+ int val = -1;
+
+ if (hard_macro_ver == 4) {
+ if (strength == 0) {
+ val = 0x07;
+ } else if (strength == 120) {
+ val = 0x0F;
+ } else if (strength == 60) {
+ val = 0x1F;
+ } else if (strength == 40) {
+ val = 0x3F;
+ } else {
+ printf("error: unsupported drv_stren_fSDq_p %d\n",
+ strength);
+ }
+ } else {
+ val = map_impedance(strength);
+ }
+
+ return val;
+}
+
+static int map_drvstren_fsdq_n(int strength, int hard_macro_ver)
+{
+ int val = -1;
+
+ if (hard_macro_ver == 4) {
+ if (strength == 0) {
+ val = 0x00;
+ } else if (strength == 120) {
+ val = 0x08;
+ } else if (strength == 60) {
+ val = 0x18;
+ } else if (strength == 40) {
+ val = 0x38;
+ } else {
+ printf("error: unsupported drvStrenFSDqN %d\n",
+ strength);
+ }
+ } else {
+ val = map_impedance(strength);
+ }
+
+ return val;
+}
+
+static void prog_tx_impedance_ctrl1(uint16_t *phy,
+ const struct input *input)
+{
+ int lane, byte, b_addr, c_addr;
+ int tx_impedance_ctrl1;
+ int drv_stren_fsdq_p, drv_stren_fsdq_n;
+ uint32_t addr;
+
+ drv_stren_fsdq_p = map_drvstren_fsdq_p(input->adv.tx_impedance,
+ input->basic.hard_macro_ver);
+ drv_stren_fsdq_n = map_drvstren_fsdq_n(input->adv.tx_impedance,
+ input->basic.hard_macro_ver);
+ tx_impedance_ctrl1 = drv_stren_fsdq_n << csr_drv_stren_fsdq_n_lsb |
+ drv_stren_fsdq_p << csr_drv_stren_fsdq_p_lsb;
+
+ for (byte = 0; byte < input->basic.num_dbyte; byte++) {
+ c_addr = byte << 12;
+ for (lane = 0; lane <= 1; lane++) {
+ b_addr = lane << 8;
+ addr = t_dbyte | c_addr | b_addr |
+ csr_tx_impedance_ctrl1_addr;
+ phy_io_write16(phy, addr, tx_impedance_ctrl1);
+ }
+ }
+}
+
+static int map_adrv_stren_p(int strength, int hard_macro_ver)
+{
+ int val = -1;
+
+ if (hard_macro_ver == 4) {
+ if (strength == 120) {
+ val = 0x1c;
+ } else if (strength == 60) {
+ val = 0x1d;
+ } else if (strength == 40) {
+ val = 0x1f;
+ } else {
+ printf("error: unsupported aDrv_stren_p %d\n",
+ strength);
+ }
+ } else {
+ if (strength == 120) {
+ val = 0x00;
+ } else if (strength == 60) {
+ val = 0x01;
+ } else if (strength == 40) {
+ val = 0x03;
+ } else if (strength == 30) {
+ val = 0x07;
+ } else if (strength == 24) {
+ val = 0x0f;
+ } else if (strength == 20) {
+ val = 0x1f;
+ } else {
+ printf("error: unsupported aDrv_stren_p %d\n",
+ strength);
+ }
+ }
+
+ return val;
+}
+
+static int map_adrv_stren_n(int strength, int hard_macro_ver)
+{
+ int val = -1;
+
+ if (hard_macro_ver == 4) {
+ if (strength == 120) {
+ val = 0x00;
+ } else if (strength == 60) {
+ val = 0x01;
+ } else if (strength == 40) {
+ val = 0x03;
+ } else {
+ printf("Error: unsupported ADrvStrenP %d\n", strength);
+ }
+ } else {
+ if (strength == 120) {
+ val = 0x00;
+ } else if (strength == 60) {
+ val = 0x01;
+ } else if (strength == 40) {
+ val = 0x03;
+ } else if (strength == 30) {
+ val = 0x07;
+ } else if (strength == 24) {
+ val = 0x0f;
+ } else if (strength == 20) {
+ val = 0x1f;
+ } else {
+ printf("Error: unsupported ADrvStrenP %d\n", strength);
+ }
+ }
+
+ return val;
+}
+
+static void prog_atx_impedance(uint16_t *phy,
+ const struct input *input)
+{
+ int anib, c_addr;
+ int atx_impedance;
+ int adrv_stren_p;
+ int adrv_stren_n;
+ uint32_t addr;
+
+ if (input->basic.hard_macro_ver == 4 &&
+ input->adv.atx_impedance == 20) {
+ printf("Error:ATxImpedance has to be 40 for HardMacroVer 4\n");
+ return;
+ }
+
+ adrv_stren_p = map_adrv_stren_p(input->adv.atx_impedance,
+ input->basic.hard_macro_ver);
+ adrv_stren_n = map_adrv_stren_n(input->adv.atx_impedance,
+ input->basic.hard_macro_ver);
+ atx_impedance = adrv_stren_n << csr_adrv_stren_n_lsb |
+ adrv_stren_p << csr_adrv_stren_p_lsb;
+ for (anib = 0; anib < input->basic.num_anib; anib++) {
+ c_addr = anib << 12;
+ addr = t_anib | c_addr | csr_atx_impedance_addr;
+ phy_io_write16(phy, addr, atx_impedance);
+ }
+}
+
+static void prog_dfi_mode(uint16_t *phy,
+ const struct input *input)
+{
+ int dfi_mode;
+ uint32_t addr;
+
+ if (input->basic.dfi1exists == 1) {
+ dfi_mode = 0x5; /* DFI1 exists but disabled */
+ } else {
+ dfi_mode = 0x1; /* DFI1 does not physically exists */
+ }
+ addr = t_master | csr_dfi_mode_addr;
+ phy_io_write16(phy, addr, dfi_mode);
+}
+
+static void prog_acx4_anib_dis(uint16_t *phy, const struct input *input)
+{
+ uint32_t addr;
+
+ addr = t_master | csr_acx4_anib_dis_addr;
+ phy_io_write16(phy, addr, 0x0);
+ debug("%s 0x%x\n", __func__, phy_io_read16(phy, addr));
+}
+
+static void prog_dfi_camode(uint16_t *phy,
+ const struct input *input)
+{
+ int dfi_camode = 2;
+ uint32_t addr = t_master | csr_dfi_camode_addr;
+
+ phy_io_write16(phy, addr, dfi_camode);
+}
+
+static void prog_cal_drv_str0(uint16_t *phy,
+ const struct input *input)
+{
+ int cal_drv_str0;
+ int cal_drv_str_pd50;
+ int cal_drv_str_pu50;
+ uint32_t addr;
+
+ cal_drv_str_pu50 = input->adv.ext_cal_res_val;
+ cal_drv_str_pd50 = cal_drv_str_pu50;
+ cal_drv_str0 = cal_drv_str_pu50 << csr_cal_drv_str_pu50_lsb |
+ cal_drv_str_pd50;
+ addr = t_master | csr_cal_drv_str0_addr;
+ phy_io_write16(phy, addr, cal_drv_str0);
+}
+
+static void prog_cal_uclk_info(uint16_t *phy,
+ const struct input *input)
+{
+ int cal_uclk_ticks_per1u_s;
+ uint32_t addr;
+
+ cal_uclk_ticks_per1u_s = input->basic.frequency >> 1;
+ if (cal_uclk_ticks_per1u_s < 24) {
+ cal_uclk_ticks_per1u_s = 24;
+ }
+
+ addr = t_master | csr_cal_uclk_info_addr;
+ phy_io_write16(phy, addr, cal_uclk_ticks_per1u_s);
+}
+
+static void prog_cal_rate(uint16_t *phy,
+ const struct input *input)
+{
+ int cal_rate;
+ int cal_interval;
+ int cal_once;
+ uint32_t addr;
+
+ cal_interval = input->adv.cal_interval;
+ cal_once = input->adv.cal_once;
+ cal_rate = cal_once << csr_cal_once_lsb |
+ cal_interval << csr_cal_interval_lsb;
+ addr = t_master | csr_cal_rate_addr;
+ phy_io_write16(phy, addr, cal_rate);
+}
+
+static void prog_vref_in_global(uint16_t *phy,
+ const struct input *input,
+ const struct ddr4u1d *msg)
+{
+ int vref_in_global;
+ int global_vref_in_dac = 0;
+ int global_vref_in_sel = 0;
+ uint32_t addr;
+
+ /*
+ * phy_vref_prcnt = msg->phy_vref / 128.0
+ * global_vref_in_dac = (phy_vref_prcnt - 0.345) / 0.005;
+ */
+ global_vref_in_dac = (msg->phy_vref * 1000 - 345 * 128 + 320) /
+ (5 * 128);
+
+ vref_in_global = global_vref_in_dac << csr_global_vref_in_dac_lsb |
+ global_vref_in_sel;
+ addr = t_master | csr_vref_in_global_addr;
+ phy_io_write16(phy, addr, vref_in_global);
+}
+
+static void prog_dq_dqs_rcv_cntrl(uint16_t *phy,
+ const struct input *input)
+{
+ int lane, byte, b_addr, c_addr;
+ int dq_dqs_rcv_cntrl;
+ int gain_curr_adj_defval = 0xb;
+ int major_mode_dbyte = 3;
+ int dfe_ctrl_defval = 0;
+ int ext_vref_range_defval = 0;
+ int sel_analog_vref = 1;
+ uint32_t addr;
+
+ dq_dqs_rcv_cntrl = gain_curr_adj_defval << csr_gain_curr_adj_lsb |
+ major_mode_dbyte << csr_major_mode_dbyte_lsb |
+ dfe_ctrl_defval << csr_dfe_ctrl_lsb |
+ ext_vref_range_defval << csr_ext_vref_range_lsb |
+ sel_analog_vref << csr_sel_analog_vref_lsb;
+ for (byte = 0; byte < input->basic.num_dbyte; byte++) {
+ c_addr = byte << 12;
+ for (lane = 0; lane <= 1; lane++) {
+ b_addr = lane << 8;
+ addr = t_dbyte | c_addr | b_addr |
+ csr_dq_dqs_rcv_cntrl_addr;
+ phy_io_write16(phy, addr, dq_dqs_rcv_cntrl);
+ }
+ }
+}
+
+static void prog_mem_alert_control(uint16_t *phy,
+ const struct input *input)
+{
+ int mem_alert_control;
+ int mem_alert_control2;
+ int malertpu_en;
+ int malertrx_en;
+ int malertvref_level;
+ int malertpu_stren;
+ int malertsync_bypass;
+ int malertdisable_val_defval = 1;
+ uint32_t addr;
+
+ if (input->basic.dram_type == DDR4 && input->adv.mem_alert_en == 1) {
+ malertpu_en = 1;
+ malertrx_en = 1;
+ malertpu_stren = input->adv.mem_alert_puimp;
+ malertvref_level = input->adv.mem_alert_vref_level;
+ malertsync_bypass = input->adv.mem_alert_sync_bypass;
+ mem_alert_control = malertdisable_val_defval << 14 |
+ malertrx_en << 13 |
+ malertpu_en << 12 |
+ malertpu_stren << 8 |
+ malertvref_level;
+ mem_alert_control2 = malertsync_bypass <<
+ csr_malertsync_bypass_lsb;
+ addr = t_master | csr_mem_alert_control_addr;
+ phy_io_write16(phy, addr, mem_alert_control);
+ addr = t_master | csr_mem_alert_control2_addr;
+ phy_io_write16(phy, addr, mem_alert_control2);
+ }
+}
+
+static void prog_dfi_freq_ratio(uint16_t *phy,
+ const struct input *input)
+{
+ int dfi_freq_ratio;
+ uint32_t addr = t_master | csr_dfi_freq_ratio_addr;
+
+ dfi_freq_ratio = input->basic.dfi_freq_ratio;
+ phy_io_write16(phy, addr, dfi_freq_ratio);
+}
+
+static void prog_tristate_mode_ca(uint16_t *phy,
+ const struct input *input)
+{
+ int tristate_mode_ca;
+ int dis_dyn_adr_tri;
+ int ddr2tmode;
+ int ck_dis_val_def = 1;
+ uint32_t addr = t_master | csr_tristate_mode_ca_addr;
+
+ dis_dyn_adr_tri = input->adv.dis_dyn_adr_tri;
+ ddr2tmode = input->adv.is2ttiming;
+ tristate_mode_ca = ck_dis_val_def << csr_ck_dis_val_lsb |
+ ddr2tmode << csr_ddr2tmode_lsb |
+ dis_dyn_adr_tri << csr_dis_dyn_adr_tri_lsb;
+ phy_io_write16(phy, addr, tristate_mode_ca);
+}
+
+static void prog_dfi_xlat(uint16_t *phy,
+ const struct input *input)
+{
+ uint16_t loop_vector;
+ int dfifreqxlat_dat;
+ int pllbypass_dat;
+ uint32_t addr;
+
+ /* fIXME: Shall unused P1, P2, P3 be bypassed? */
+ pllbypass_dat = input->basic.pll_bypass; /* only [0] is used */
+ for (loop_vector = 0; loop_vector < 8; loop_vector++) {
+ if (loop_vector == 0) {
+ dfifreqxlat_dat = pllbypass_dat + 0x5555;
+ } else if (loop_vector == 7) {
+ dfifreqxlat_dat = 0xf000;
+ } else {
+ dfifreqxlat_dat = 0x5555;
+ }
+ addr = t_master | (csr_dfi_freq_xlat0_addr + loop_vector);
+ phy_io_write16(phy, addr, dfifreqxlat_dat);
+ }
+}
+
+static void prog_dbyte_misc_mode(uint16_t *phy,
+ const struct input *input,
+ const struct ddr4u1d *msg)
+{
+ int dbyte_misc_mode;
+ int dq_dqs_rcv_cntrl1;
+ int dq_dqs_rcv_cntrl1_1;
+ int byte, c_addr;
+ uint32_t addr;
+
+ dbyte_misc_mode = 0x1 << csr_dbyte_disable_lsb;
+ dq_dqs_rcv_cntrl1 = 0x1ff << csr_power_down_rcvr_lsb |
+ 0x1 << csr_power_down_rcvr_dqs_lsb |
+ 0x1 << csr_rx_pad_standby_en_lsb;
+ dq_dqs_rcv_cntrl1_1 = (0x100 << csr_power_down_rcvr_lsb |
+ csr_rx_pad_standby_en_mask);
+ for (byte = 0; byte < input->basic.num_dbyte; byte++) {
+ c_addr = byte << 12;
+ if (byte <= input->basic.num_active_dbyte_dfi0 - 1) {
+ /* disable RDBI lane if not used. */
+ if ((input->basic.dram_data_width != 4) &&
+ (((msg->mr5 >> 12) & 0x1) == 0)) {
+ addr = t_dbyte
+ | c_addr
+ | csr_dq_dqs_rcv_cntrl1_addr;
+ phy_io_write16(phy, addr, dq_dqs_rcv_cntrl1_1);
+ }
+ } else {
+ addr = t_dbyte | c_addr | csr_dbyte_misc_mode_addr;
+ phy_io_write16(phy, addr, dbyte_misc_mode);
+ addr = t_dbyte | c_addr | csr_dq_dqs_rcv_cntrl1_addr;
+ phy_io_write16(phy, addr, dq_dqs_rcv_cntrl1);
+ }
+ }
+}
+
+static void prog_master_x4config(uint16_t *phy,
+ const struct input *input)
+{
+ int master_x4config;
+ int x4tg;
+ uint32_t addr = t_master | csr_master_x4config_addr;
+
+ x4tg = input->basic.dram_data_width == 4 ? 0xf : 0;
+ master_x4config = x4tg << csr_x4tg_lsb;
+ phy_io_write16(phy, addr, master_x4config);
+}
+
+static void prog_dmipin_present(uint16_t *phy,
+ const struct input *input,
+ const struct ddr4u1d *msg)
+{
+ int dmipin_present;
+ uint32_t addr = t_master | csr_dmipin_present_addr;
+
+ dmipin_present = (msg->mr5 >> 12) & 0x1;
+ phy_io_write16(phy, addr, dmipin_present);
+}
+
+static void prog_dfi_phyupd(uint16_t *phy,
+ const struct input *input)
+{
+ int dfiphyupd_dat;
+ uint32_t addr;
+
+ addr = t_master | (csr_dfiphyupd_addr);
+ dfiphyupd_dat = phy_io_read16(phy, addr) &
+ ~csr_dfiphyupd_threshold_mask;
+
+ phy_io_write16(phy, addr, dfiphyupd_dat);
+}
+
+static void prog_cal_misc2(uint16_t *phy,
+ const struct input *input)
+{
+ int cal_misc2_dat, cal_drv_pdth_data, cal_offsets_dat;
+ uint32_t addr;
+
+ addr = t_master | (csr_cal_misc2_addr);
+ cal_misc2_dat = phy_io_read16(phy, addr) |
+ (1 << csr_cal_misc2_err_dis);
+
+ phy_io_write16(phy, addr, cal_misc2_dat);
+
+ addr = t_master | (csr_cal_offsets_addr);
+
+ cal_drv_pdth_data = 0x9 << 6;
+ cal_offsets_dat = (phy_io_read16(phy, addr) & ~csr_cal_drv_pdth_mask)
+ | cal_drv_pdth_data;
+
+ phy_io_write16(phy, addr, cal_offsets_dat);
+}
+
+static int c_init_phy_config(uint16_t **phy_ptr,
+ unsigned int ip_rev,
+ const struct input *input,
+ const void *msg)
+{
+ int i;
+ uint16_t *phy;
+ __unused const soc_info_t *soc_info;
+
+ for (i = 0; i < NUM_OF_DDRC; i++) {
+ phy = phy_ptr[i];
+ if (phy == NULL) {
+ continue;
+ }
+
+ debug("Initialize PHY %d config\n", i);
+ prog_dfi_phyupd(phy, input);
+ prog_cal_misc2(phy, input);
+ prog_tx_pre_drv_mode(phy, input);
+ prog_atx_pre_drv_mode(phy, input);
+ prog_enable_cs_multicast(phy, input); /* rdimm and lrdimm */
+ prog_dfi_rd_data_cs_dest_map(phy, ip_rev, input, msg);
+ prog_pll_ctrl2(phy, input);
+#ifdef DDR_PLL_FIX
+ soc_info = get_soc_info();
+ debug("SOC_SI_REV = %x\n", soc_info->svr_reg.bf.maj_ver);
+ if (soc_info->svr_reg.bf.maj_ver == 1) {
+ prog_pll_pwr_dn(phy, input);
+
+ /*Enable FFE aka TxEqualizationMode for rev1 SI*/
+ phy_io_write16(phy, 0x010048, 0x1);
+ }
+#endif
+ prog_ard_ptr_init_val(phy, input);
+ prog_dqs_preamble_control(phy, input);
+ prog_dll_lck_param(phy, input);
+ prog_dll_gain_ctl(phy, input);
+ prog_proc_odt_time_ctl(phy, input);
+ prog_tx_odt_drv_stren(phy, input);
+ prog_tx_impedance_ctrl1(phy, input);
+ prog_atx_impedance(phy, input);
+ prog_dfi_mode(phy, input);
+ prog_dfi_camode(phy, input);
+ prog_cal_drv_str0(phy, input);
+ prog_cal_uclk_info(phy, input);
+ prog_cal_rate(phy, input);
+ prog_vref_in_global(phy, input, msg);
+ prog_dq_dqs_rcv_cntrl(phy, input);
+ prog_mem_alert_control(phy, input);
+ prog_dfi_freq_ratio(phy, input);
+ prog_tristate_mode_ca(phy, input);
+ prog_dfi_xlat(phy, input);
+ prog_dbyte_misc_mode(phy, input, msg);
+ prog_master_x4config(phy, input);
+ prog_dmipin_present(phy, input, msg);
+ prog_acx4_anib_dis(phy, input);
+ }
+
+ return 0;
+}
+
+static uint32_t get_mail(uint16_t *phy, int stream)
+{
+ int timeout;
+ uint32_t mail = 0U;
+
+ timeout = TIMEOUTDEFAULT;
+ while (((--timeout) != 0) &&
+ ((phy_io_read16(phy, t_apbonly | csr_uct_shadow_regs)
+ & uct_write_prot_shadow_mask) != 0)) {
+ mdelay(10);
+ }
+ if (timeout == 0) {
+ ERROR("Timeout getting mail from PHY\n");
+ return 0xFFFF;
+ }
+
+ mail = phy_io_read16(phy, t_apbonly |
+ csr_uct_write_only_shadow);
+ if (stream != 0) {
+ mail |= phy_io_read16(phy, t_apbonly |
+ csr_uct_dat_write_only_shadow) << 16;
+ }
+
+ /* Ack */
+ phy_io_write16(phy, t_apbonly | csr_dct_write_prot, 0);
+
+ timeout = TIMEOUTDEFAULT;
+ while (((--timeout) != 0) &&
+ ((phy_io_read16(phy, t_apbonly | csr_uct_shadow_regs)
+ & uct_write_prot_shadow_mask) == 0)) {
+ mdelay(1);
+ }
+ if (timeout == 0) {
+ ERROR("Timeout ack PHY mail\n");
+ }
+
+ /* completed */
+ phy_io_write16(phy, t_apbonly | csr_dct_write_prot, 1U);
+
+ return mail;
+}
+
+#ifdef DDR_PHY_DEBUG
+static const char *lookup_msg(uint32_t index, int train2d)
+{
+ int i;
+ int size;
+ const struct phy_msg *messages;
+ const char *ptr = NULL;
+
+ if (train2d != 0) {
+ messages = messages_2d;
+ size = ARRAY_SIZE(messages_2d);
+ } else {
+ messages = messages_1d;
+ size = ARRAY_SIZE(messages_1d);
+ }
+ for (i = 0; i < size; i++) {
+ if (messages[i].index == index) {
+ ptr = messages[i].msg;
+ break;
+ }
+ }
+
+ return ptr;
+}
+#endif
+
+#define MAX_ARGS 32
+static void decode_stream_message(uint16_t *phy, int train2d)
+{
+ uint32_t index __unused;
+
+ __unused const char *format;
+ __unused uint32_t args[MAX_ARGS];
+ __unused int i;
+
+#ifdef DDR_PHY_DEBUG
+ index = get_mail(phy, 1);
+ if ((index & 0xffff) > MAX_ARGS) { /* up to MAX_ARGS args so far */
+ printf("Program error in %s\n", __func__);
+ }
+ for (i = 0; i < (index & 0xffff) && i < MAX_ARGS; i++) {
+ args[i] = get_mail(phy, 1);
+ }
+
+ format = lookup_msg(index, train2d);
+ if (format != NULL) {
+ printf("0x%08x: ", index);
+ printf(format, args[0], args[1], args[2], args[3], args[4],
+ args[5], args[6], args[7], args[8], args[9], args[10],
+ args[11], args[12], args[13], args[14], args[15],
+ args[16], args[17], args[18], args[19], args[20],
+ args[21], args[22], args[23], args[24], args[25],
+ args[26], args[27], args[28], args[29], args[30],
+ args[31]);
+ }
+#endif
+}
+
+static int wait_fw_done(uint16_t *phy, int train2d)
+{
+ uint32_t mail = 0U;
+
+ while (mail == U(0x0)) {
+ mail = get_mail(phy, 0);
+ switch (mail) {
+ case U(0x7):
+ debug("%s Training completed\n", train2d ? "2D" : "1D");
+ break;
+ case U(0xff):
+ debug("%s Training failure\n", train2d ? "2D" : "1D");
+ break;
+ case U(0x0):
+ debug("End of initialization\n");
+ mail = 0U;
+ break;
+ case U(0x1):
+ debug("End of fine write leveling\n");
+ mail = 0U;
+ break;
+ case U(0x2):
+ debug("End of read enable training\n");
+ mail = 0U;
+ break;
+ case U(0x3):
+ debug("End of read delay center optimization\n");
+ mail = 0U;
+ break;
+ case U(0x4):
+ debug("End of write delay center optimization\n");
+ mail = 0U;
+ break;
+ case U(0x5):
+ debug("End of 2D read delay/voltage center optimztn\n");
+ mail = 0U;
+ break;
+ case U(0x6):
+ debug("End of 2D write delay/voltage center optmztn\n");
+ mail = 0U;
+ break;
+ case U(0x8):
+ decode_stream_message(phy, train2d);
+ mail = 0U;
+ break;
+ case U(0x9):
+ debug("End of max read latency training\n");
+ mail = 0U;
+ break;
+ case U(0xa):
+ debug("End of read dq deskew training\n");
+ mail = 0U;
+ break;
+ case U(0xc):
+ debug("End of LRDIMM Specific training, including:\n");
+ debug("/tDWL, MREP, MRD and MWD\n");
+ mail = 0U;
+ break;
+ case U(0xd):
+ debug("End of CA training\n");
+ mail = 0U;
+ break;
+ case U(0xfd):
+ debug("End of MPR read delay center optimization\n");
+ mail = 0U;
+ break;
+ case U(0xfe):
+ debug("End of Write leveling coarse delay\n");
+ mail = 0U;
+ break;
+ case U(0xffff):
+ debug("Timed out\n");
+ break;
+ default:
+ mail = 0U;
+ break;
+ }
+ }
+
+ if (mail == U(0x7)) {
+ return 0;
+ } else if (mail == U(0xff)) {
+ return -EIO;
+ } else if (mail == U(0xffff)) {
+ return -ETIMEDOUT;
+ }
+
+ debug("PHY_GEN2 FW: Unxpected mail = 0x%x\n", mail);
+
+ return -EINVAL;
+}
+
+static int g_exec_fw(uint16_t **phy_ptr, int train2d, struct input *input)
+{
+ int ret = -EINVAL;
+ int i;
+ uint16_t *phy;
+
+ for (i = 0; i < NUM_OF_DDRC; i++) {
+ phy = phy_ptr[i];
+ if (phy == NULL) {
+ continue;
+ }
+ debug("Applying PLL optimal settings\n");
+ prog_pll_ctrl2(phy, input);
+ prog_pll_ctrl(phy, input);
+ phy_io_write16(phy,
+ t_apbonly | csr_micro_cont_mux_sel_addr,
+ 0x1);
+ phy_io_write16(phy,
+ t_apbonly | csr_micro_reset_addr,
+ csr_reset_to_micro_mask |
+ csr_stall_to_micro_mask);
+ phy_io_write16(phy,
+ t_apbonly | csr_micro_reset_addr,
+ csr_stall_to_micro_mask);
+ phy_io_write16(phy,
+ t_apbonly | csr_micro_reset_addr,
+ 0);
+
+ ret = wait_fw_done(phy, train2d);
+ if (ret == -ETIMEDOUT) {
+ ERROR("Wait timed out: Firmware execution on PHY %d\n",
+ i);
+ }
+ }
+ return ret;
+}
+
+static inline int send_fw(uint16_t *phy,
+ uint32_t dst,
+ uint16_t *img,
+ uint32_t size)
+{
+ uint32_t i;
+
+ if ((size % 2U) != 0U) {
+ ERROR("Wrong image size 0x%x\n", size);
+ return -EINVAL;
+ }
+
+ for (i = 0U; i < size / 2; i++) {
+ phy_io_write16(phy, dst + i, *(img + i));
+ }
+
+ return 0;
+}
+
+static int load_fw(uint16_t **phy_ptr,
+ struct input *input,
+ int train2d,
+ void *msg,
+ size_t len,
+ uintptr_t phy_gen2_fw_img_buf,
+ int (*img_loadr)(unsigned int, uintptr_t *, uint32_t *),
+ uint32_t warm_boot_flag)
+{
+ uint32_t imem_id, dmem_id;
+ uintptr_t image_buf;
+ uint32_t size;
+ int ret;
+ int i;
+ uint16_t *phy;
+
+ switch (input->basic.dimm_type) {
+ case UDIMM:
+ case SODIMM:
+ case NODIMM:
+ imem_id = train2d ? DDR_IMEM_UDIMM_2D_IMAGE_ID :
+ DDR_IMEM_UDIMM_1D_IMAGE_ID;
+ dmem_id = train2d ? DDR_DMEM_UDIMM_2D_IMAGE_ID :
+ DDR_DMEM_UDIMM_1D_IMAGE_ID;
+ break;
+ case RDIMM:
+ imem_id = train2d ? DDR_IMEM_RDIMM_2D_IMAGE_ID :
+ DDR_IMEM_RDIMM_1D_IMAGE_ID;
+ dmem_id = train2d ? DDR_DMEM_RDIMM_2D_IMAGE_ID :
+ DDR_DMEM_RDIMM_1D_IMAGE_ID;
+ break;
+ default:
+ ERROR("Unsupported DIMM type\n");
+ return -EINVAL;
+ }
+
+ size = PHY_GEN2_MAX_IMAGE_SIZE;
+ image_buf = (uintptr_t)phy_gen2_fw_img_buf;
+ mmap_add_dynamic_region(phy_gen2_fw_img_buf,
+ phy_gen2_fw_img_buf,
+ PHY_GEN2_MAX_IMAGE_SIZE,
+ MT_MEMORY | MT_RW | MT_SECURE);
+ ret = img_loadr(imem_id, &image_buf, &size);
+ if (ret != 0) {
+ ERROR("Failed to load %d firmware.\n", imem_id);
+ return ret;
+ }
+ debug("Loaded Imaged id %d of size %x at address %lx\n",
+ imem_id, size, image_buf);
+
+ for (i = 0; i < NUM_OF_DDRC; i++) {
+ phy = phy_ptr[i];
+ if (phy == NULL) {
+ continue;
+ }
+
+ if (warm_boot_flag != DDR_WARM_BOOT) {
+ if (train2d == 0) {
+ phy_io_write16(phy, t_master |
+ csr_mem_reset_l_addr,
+ csr_protect_mem_reset_mask);
+ }
+ }
+ /* Enable access to the internal CSRs */
+ phy_io_write16(phy, t_apbonly | csr_micro_cont_mux_sel_addr, 0);
+
+ ret = send_fw(phy, PHY_GEN2_IMEM_ADDR,
+ (uint16_t *)image_buf, size);
+ if (ret != 0) {
+ return ret;
+ }
+ }
+
+ size = PHY_GEN2_MAX_IMAGE_SIZE;
+ image_buf = (uintptr_t)phy_gen2_fw_img_buf;
+ ret = img_loadr(dmem_id, &image_buf, &size);
+ if (ret != 0) {
+ ERROR("Failed to load %d firmware.\n", dmem_id);
+ return ret;
+ }
+ debug("Loaded Imaged id %d of size %x at address %lx\n",
+ dmem_id, size, image_buf);
+ image_buf += len;
+ size -= len;
+
+ for (i = 0; i < NUM_OF_DDRC; i++) {
+ phy = phy_ptr[i];
+ if (phy == NULL) {
+ continue;
+ }
+
+ ret = send_fw(phy, PHY_GEN2_DMEM_ADDR, msg, len);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = send_fw(phy, PHY_GEN2_DMEM_ADDR + len / 2,
+ (uint16_t *)image_buf, size);
+ if (ret != 0) {
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+static void parse_odt(const unsigned int val,
+ const int read,
+ const int i,
+ const unsigned int cs_d0,
+ const unsigned int cs_d1,
+ unsigned int *odt)
+{
+ int shift = read ? 4 : 0;
+ int j;
+
+ if (i < 0 || i > 3) {
+ printf("Error: invalid chip-select value\n");
+ }
+ switch (val) {
+ case DDR_ODT_CS:
+ odt[i] |= (1 << i) << shift;
+ break;
+ case DDR_ODT_ALL_OTHER_CS:
+ for (j = 0; j < DDRC_NUM_CS; j++) {
+ if (i == j) {
+ continue;
+ }
+ if (((cs_d0 | cs_d1) & (1 << j)) == 0) {
+ continue;
+ }
+ odt[j] |= (1 << i) << shift;
+ }
+ break;
+ case DDR_ODT_CS_AND_OTHER_DIMM:
+ odt[i] |= (1 << i) << 4;
+ /* fallthrough */
+ case DDR_ODT_OTHER_DIMM:
+ for (j = 0; j < DDRC_NUM_CS; j++) {
+ if ((((cs_d0 & (1 << i)) != 0) &&
+ ((cs_d1 & (1 << j)) != 0)) ||
+ (((cs_d1 & (1 << i)) != 0) &&
+ ((cs_d0 & (1 << j)) != 0))) {
+ odt[j] |= (1 << i) << shift;
+ }
+ }
+ break;
+ case DDR_ODT_ALL:
+ for (j = 0; j < DDRC_NUM_CS; j++) {
+ if (((cs_d0 | cs_d1) & (1 << j)) == 0) {
+ continue;
+ }
+ odt[j] |= (1 << i) << shift;
+ }
+ break;
+ case DDR_ODT_SAME_DIMM:
+ for (j = 0; j < DDRC_NUM_CS; j++) {
+ if ((((cs_d0 & (1 << i)) != 0) &&
+ ((cs_d0 & (1 << j)) != 0)) ||
+ (((cs_d1 & (1 << i)) != 0) &&
+ ((cs_d1 & (1 << j)) != 0))) {
+ odt[j] |= (1 << i) << shift;
+ }
+ }
+ break;
+ case DDR_ODT_OTHER_CS_ONSAMEDIMM:
+ for (j = 0; j < DDRC_NUM_CS; j++) {
+ if (i == j) {
+ continue;
+ }
+ if ((((cs_d0 & (1 << i)) != 0) &&
+ ((cs_d0 & (1 << j)) != 0)) ||
+ (((cs_d1 & (1 << i)) != 0) &&
+ ((cs_d1 & (1 << j)) != 0))) {
+ odt[j] |= (1 << i) << shift;
+ }
+ }
+ break;
+ case DDR_ODT_NEVER:
+ break;
+ default:
+ break;
+ }
+}
+
+#ifdef DEBUG_DDR_INPUT_CONFIG
+char *dram_types_str[] = {
+ "DDR4",
+ "DDR3",
+ "LDDDR4",
+ "LPDDR3",
+ "LPDDR2",
+ "DDR5"
+};
+
+char *dimm_types_str[] = {
+ "UDIMM",
+ "SODIMM",
+ "RDIMM",
+ "LRDIMM",
+ "NODIMM",
+};
+
+
+static void print_jason_format(struct input *input,
+ struct ddr4u1d *msg_1d,
+ struct ddr4u2d *msg_2d)
+{
+
+ printf("\n{");
+ printf("\n \"dram_type\": \"%s\",", dram_types_str[input->basic.dram_type]);
+ printf("\n \"dimm_type\": \"%s\",", dimm_types_str[input->basic.dimm_type]);
+ printf("\n \"hard_macro_ver\": \"%d\",", input->basic.hard_macro_ver);
+ printf("\n \"num_dbyte\": \"0x%04x\",", (unsigned int)input->basic.num_dbyte);
+ printf("\n \"num_active_dbyte_dfi0\": \"0x%04x\",", (unsigned int)input->basic.num_active_dbyte_dfi0);
+ printf("\n \"num_anib\": \"0x%04x\",", (unsigned int)input->basic.num_anib);
+ printf("\n \"num_rank_dfi0\": \"0x%04x\",", (unsigned int)input->basic.num_rank_dfi0);
+ printf("\n \"num_pstates\": \"0x%04x\",", (unsigned int)input->basic.num_pstates);
+ printf("\n \"frequency\": \"%d\",", input->basic.frequency);
+ printf("\n \"pll_bypass\": \"0x%04x\",", (unsigned int)input->basic.dfi_freq_ratio);
+ printf("\n \"dfi_freq_ratio\": \"0x%04x\",", (unsigned int)input->basic.dfi_freq_ratio);
+ printf("\n \"dfi1_exists\": \"0x%04x\",", (unsigned int)input->basic.dfi1exists);
+ printf("\n \"dram_data_width\": \"0x%04x\",", (unsigned int)input->basic.dram_data_width);
+ printf("\n \"dram_byte_swap\": \"0x%04x\",", (unsigned int)input->adv.dram_byte_swap);
+ printf("\n \"ext_cal_res_val\": \"0x%04x\",", (unsigned int)input->adv.ext_cal_res_val);
+ printf("\n \"tx_slew_rise_dq\": \"0x%04x\",", (unsigned int)input->adv.tx_slew_rise_dq);
+ printf("\n \"tx_slew_fall_dq\": \"0x%04x\",", (unsigned int)input->adv.tx_slew_fall_dq);
+ printf("\n \"tx_slew_rise_ac\": \"0x%04x\",", (unsigned int)input->adv.tx_slew_rise_ac);
+ printf("\n \"tx_slew_fall_ac\": \"0x%04x\",", (unsigned int)input->adv.tx_slew_fall_ac);
+ printf("\n \"odt_impedance\": \"%d\",", input->adv.odtimpedance);
+ printf("\n \"tx_impedance\": \"%d\",", input->adv.tx_impedance);
+ printf("\n \"atx_impedance\": \"%d\",", input->adv.atx_impedance);
+ printf("\n \"mem_alert_en\": \"0x%04x\",", (unsigned int)input->adv.mem_alert_en);
+ printf("\n \"mem_alert_pu_imp\": \"0x%04x\",", (unsigned int)input->adv.mem_alert_puimp);
+ printf("\n \"mem_alert_vref_level\": \"0x%04x\",", (unsigned int)input->adv.mem_alert_vref_level);
+ printf("\n \"mem_alert_sync_bypass\": \"0x%04x\",", (unsigned int)input->adv.mem_alert_sync_bypass);
+ printf("\n \"cal_interval\": \"0x%04x\",", (unsigned int)input->adv.cal_interval);
+ printf("\n \"cal_once\": \"0x%04x\",", (unsigned int)input->adv.cal_once);
+ printf("\n \"dis_dyn_adr_tri\": \"0x%04x\",", (unsigned int)input->adv.dis_dyn_adr_tri);
+ printf("\n \"is2t_timing\": \"0x%04x\",", (unsigned int)input->adv.is2ttiming);
+ printf("\n \"d4rx_preabmle_length\": \"0x%04x\",", (unsigned int)input->adv.d4rx_preamble_length);
+ printf("\n \"d4tx_preamble_length\": \"0x%04x\",", (unsigned int)input->adv.d4tx_preamble_length);
+ printf("\n \"msg_misc\": \"0x%02x\",", (unsigned int)msg_1d->msg_misc);
+ printf("\n \"reserved00\": \"0x%01x\",", (unsigned int)msg_1d->reserved00);
+ printf("\n \"hdt_ctrl\": \"0x%02x\",", (unsigned int)msg_1d->hdt_ctrl);
+ printf("\n \"cs_present\": \"0x%02x\",", (unsigned int)msg_1d->cs_present);
+ printf("\n \"phy_vref\": \"0x%02x\",", (unsigned int)msg_1d->phy_vref);
+ printf("\n \"dfi_mrl_margin\": \"0x%02x\",", (unsigned int)msg_1d->dfimrlmargin);
+ printf("\n \"addr_mirror\": \"0x%02x\",", (unsigned int)msg_1d->addr_mirror);
+ printf("\n \"wr_odt_pat_rank0\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl0 & 0x0f));
+ printf("\n \"wr_odt_pat_rank1\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl1 & 0x0f));
+ printf("\n \"wr_odt_pat_rank2\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl2 & 0x0f));
+ printf("\n \"wr_odt_pat_rank3\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl3 & 0x0f));
+ printf("\n \"rd_odt_pat_rank0\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl0 & 0xf0));
+ printf("\n \"rd_odt_pat_rank1\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl1 & 0xf0));
+ printf("\n \"rd_odt_pat_rank2\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl2 & 0xf0));
+ printf("\n \"rd_odt_pat_rank3\": \"0x%02x\",", (unsigned int)(msg_1d->acsm_odt_ctrl3 & 0xf0));
+ printf("\n \"d4_misc\": \"0x%01x\",", (unsigned int)msg_1d->d4misc);
+ printf("\n \"share_2d_vref_results\": \"0x%01x\",", (unsigned int)msg_1d->share2dvref_result);
+ printf("\n \"sequence_ctrl\": \"0x%04x\",", (unsigned int)msg_1d->sequence_ctrl);
+ printf("\n \"mr0\": \"0x%04x\",", (unsigned int)msg_1d->mr0);
+ printf("\n \"mr1\": \"0x%04x\",", (unsigned int)msg_1d->mr1);
+ printf("\n \"mr2\": \"0x%04x\",", (unsigned int)msg_1d->mr2);
+ printf("\n \"mr3\": \"0x%04x\",", (unsigned int)msg_1d->mr3);
+ printf("\n \"mr4\": \"0x%04x\",", (unsigned int)msg_1d->mr4);
+ printf("\n \"mr5\": \"0x%04x\",", (unsigned int)msg_1d->mr5);
+ printf("\n \"mr6\": \"0x%04x\",", (unsigned int)msg_1d->mr6);
+ printf("\n \"alt_cal_l\": \"0x%04x\",", (unsigned int)msg_1d->alt_cas_l);
+ printf("\n \"alt_wcal_l\": \"0x%04x\",", (unsigned int)msg_1d->alt_wcas_l);
+ printf("\n \"sequence_ctrl_2d\": \"0x%04x\",", (unsigned int)msg_2d->sequence_ctrl);
+ printf("\n \"rtt_nom_wr_park0\": \"0x%01x\",", (unsigned int)msg_1d->rtt_nom_wr_park0);
+ printf("\n \"rtt_nom_wr_park1\": \"0x%01x\",", (unsigned int)msg_1d->rtt_nom_wr_park1);
+ printf("\n \"rtt_nom_wr_park2\": \"0x%01x\",", (unsigned int)msg_1d->rtt_nom_wr_park2);
+ printf("\n \"rtt_nom_wr_park3\": \"0x%01x\",", (unsigned int)msg_1d->rtt_nom_wr_park3);
+ printf("\n \"rtt_nom_wr_park4\": \"0x%01x\",", (unsigned int)msg_1d->rtt_nom_wr_park4);
+ printf("\n \"rtt_nom_wr_park5\": \"0x%01x\",", (unsigned int)msg_1d->rtt_nom_wr_park5);
+ printf("\n \"rtt_nom_wr_park6\": \"0x%01x\",", (unsigned int)msg_1d->rtt_nom_wr_park6);
+ printf("\n \"rtt_nom_wr_park7\": \"0x%01x\"", (unsigned int)msg_1d->rtt_nom_wr_park7);
+ printf("\n}");
+ printf("\n");
+}
+#endif
+
+int compute_ddr_phy(struct ddr_info *priv)
+{
+ const unsigned long clk = priv->clk;
+ const struct memctl_opt *popts = &priv->opt;
+ const struct ddr_conf *conf = &priv->conf;
+ const struct dimm_params *dimm_param = &priv->dimm;
+ struct ddr_cfg_regs *regs = &priv->ddr_reg;
+ int ret;
+ static struct input input;
+ static struct ddr4u1d msg_1d;
+ static struct ddr4u2d msg_2d;
+ unsigned int i;
+ unsigned int odt_rd, odt_wr;
+ __unused const soc_info_t *soc_info;
+#ifdef NXP_APPLY_MAX_CDD
+ unsigned int tcfg0, tcfg4, rank;
+#endif
+
+ if (dimm_param == NULL) {
+ ERROR("Empty DIMM parameters.\n");
+ return -EINVAL;
+ }
+
+ zeromem(&input, sizeof(input));
+ zeromem(&msg_1d, sizeof(msg_1d));
+ zeromem(&msg_2d, sizeof(msg_2d));
+
+ input.basic.dram_type = DDR4;
+ /* FIXME: Add condition for LRDIMM */
+ input.basic.dimm_type = (dimm_param->rdimm != 0) ? RDIMM : UDIMM;
+ input.basic.num_dbyte = dimm_param->primary_sdram_width / 8 +
+ dimm_param->ec_sdram_width / 8;
+ input.basic.num_active_dbyte_dfi0 = input.basic.num_dbyte;
+ input.basic.num_rank_dfi0 = dimm_param->n_ranks;
+ input.basic.dram_data_width = dimm_param->device_width;
+ input.basic.hard_macro_ver = 0xa;
+ input.basic.num_pstates = 1;
+ input.basic.dfi_freq_ratio = 1;
+ input.basic.num_anib = 0xc;
+ input.basic.train2d = popts->skip2d ? 0 : 1;
+ input.basic.frequency = (int) (clk / 2000000ul);
+ debug("frequency = %dMHz\n", input.basic.frequency);
+ input.cs_d0 = conf->cs_on_dimm[0];
+#if DDRC_NUM_DIMM > 1
+ input.cs_d1 = conf->cs_on_dimm[1];
+#endif
+ input.mirror = dimm_param->mirrored_dimm;
+ input.mr[0] = regs->sdram_mode[0] & U(0xffff);
+ input.mr[1] = regs->sdram_mode[0] >> 16U;
+ input.mr[2] = regs->sdram_mode[1] >> 16U;
+ input.mr[3] = regs->sdram_mode[1] & U(0xffff);
+ input.mr[4] = regs->sdram_mode[8] >> 16U;
+ input.mr[5] = regs->sdram_mode[8] & U(0xffff);
+ input.mr[6] = regs->sdram_mode[9] >> 16U;
+ input.vref = popts->vref_phy;
+ debug("Vref_phy = %d percent\n", (input.vref * 100U) >> 7U);
+ for (i = 0U; i < DDRC_NUM_CS; i++) {
+ if ((regs->cs[i].config & SDRAM_CS_CONFIG_EN) == 0U) {
+ continue;
+ }
+ odt_rd = (regs->cs[i].config >> 20U) & U(0x7);
+ odt_wr = (regs->cs[i].config >> 16U) & U(0x7);
+ parse_odt(odt_rd, true, i, input.cs_d0, input.cs_d1,
+ input.odt);
+ parse_odt(odt_wr, false, i, input.cs_d0, input.cs_d1,
+ input.odt);
+ }
+
+ /* Do not set sdram_cfg[RD_EN] or sdram_cfg2[RCW_EN] for RDIMM */
+ if (dimm_param->rdimm != 0U) {
+ regs->sdram_cfg[0] &= ~(1 << 28U);
+ regs->sdram_cfg[1] &= ~(1 << 2U);
+ input.rcw[0] = (regs->sdram_rcw[0] >> 28U) & U(0xf);
+ input.rcw[1] = (regs->sdram_rcw[0] >> 24U) & U(0xf);
+ input.rcw[2] = (regs->sdram_rcw[0] >> 20U) & U(0xf);
+ input.rcw[3] = (regs->sdram_rcw[0] >> 16U) & U(0xf);
+ input.rcw[4] = (regs->sdram_rcw[0] >> 12U) & U(0xf);
+ input.rcw[5] = (regs->sdram_rcw[0] >> 8U) & U(0xf);
+ input.rcw[6] = (regs->sdram_rcw[0] >> 4U) & U(0xf);
+ input.rcw[7] = (regs->sdram_rcw[0] >> 0U) & U(0xf);
+ input.rcw[8] = (regs->sdram_rcw[1] >> 28U) & U(0xf);
+ input.rcw[9] = (regs->sdram_rcw[1] >> 24U) & U(0xf);
+ input.rcw[10] = (regs->sdram_rcw[1] >> 20U) & U(0xf);
+ input.rcw[11] = (regs->sdram_rcw[1] >> 16U) & U(0xf);
+ input.rcw[12] = (regs->sdram_rcw[1] >> 12U) & U(0xf);
+ input.rcw[13] = (regs->sdram_rcw[1] >> 8U) & U(0xf);
+ input.rcw[14] = (regs->sdram_rcw[1] >> 4U) & U(0xf);
+ input.rcw[15] = (regs->sdram_rcw[1] >> 0U) & U(0xf);
+ input.rcw3x = (regs->sdram_rcw[2] >> 8U) & U(0xff);
+ }
+
+ input.adv.odtimpedance = popts->odt ? popts->odt : 60;
+ input.adv.tx_impedance = popts->phy_tx_impedance ?
+ popts->phy_tx_impedance : 28;
+ input.adv.atx_impedance = popts->phy_atx_impedance ?
+ popts->phy_atx_impedance : 30;
+
+ debug("Initializing input adv data structure\n");
+ phy_gen2_init_input(&input);
+
+ debug("Initializing message block\n");
+ ret = phy_gen2_msg_init(&msg_1d, &msg_2d, &input);
+ if (ret != 0) {
+ ERROR("Init msg failed (error code %d)\n", ret);
+ return ret;
+ }
+
+ ret = c_init_phy_config(priv->phy, priv->ip_rev, &input, &msg_1d);
+ if (ret != 0) {
+ ERROR("Init PHY failed (error code %d)\n", ret);
+ return ret;
+ }
+#ifdef NXP_WARM_BOOT
+ debug("Warm boot flag value %0x\n", priv->warm_boot_flag);
+ if (priv->warm_boot_flag == DDR_WARM_BOOT) {
+ debug("Restoring the Phy training data\n");
+ // Restore the training data
+ ret = restore_phy_training_values(priv->phy,
+ PHY_TRAINING_REGS_ON_FLASH,
+ priv->num_ctlrs,
+ input.basic.train2d);
+ if (ret != 0) {
+ ERROR("Restoring of training data failed %d\n", ret);
+ return ret;
+ }
+ } else {
+#endif
+
+ debug("Load 1D firmware\n");
+ ret = load_fw(priv->phy, &input, 0, &msg_1d,
+ sizeof(struct ddr4u1d), priv->phy_gen2_fw_img_buf,
+ priv->img_loadr, priv->warm_boot_flag);
+ if (ret != 0) {
+ ERROR("Loading firmware failed (error code %d)\n", ret);
+ return ret;
+ }
+
+ debug("Execute firmware\n");
+ ret = g_exec_fw(priv->phy, 0, &input);
+ if (ret != 0) {
+ ERROR("Execution FW failed (error code %d)\n", ret);
+ }
+
+#ifdef NXP_APPLY_MAX_CDD
+ soc_info = get_soc_info();
+ if (soc_info->svr_reg.bf.maj_ver == 2) {
+ tcfg0 = regs->timing_cfg[0];
+ tcfg4 = regs->timing_cfg[4];
+ rank = findrank(conf->cs_in_use);
+ get_cdd_val(priv->phy, rank, input.basic.frequency,
+ &tcfg0, &tcfg4);
+ regs->timing_cfg[0] = tcfg0;
+ regs->timing_cfg[4] = tcfg4;
+ }
+#endif
+
+ if ((ret == 0) && (input.basic.train2d != 0)) {
+ /* 2D training starts here */
+ debug("Load 2D firmware\n");
+ ret = load_fw(priv->phy, &input, 1, &msg_2d,
+ sizeof(struct ddr4u2d),
+ priv->phy_gen2_fw_img_buf,
+ priv->img_loadr,
+ priv->warm_boot_flag);
+ if (ret != 0) {
+ ERROR("Loading fw failed (err code %d)\n", ret);
+ } else {
+ debug("Execute 2D firmware\n");
+ ret = g_exec_fw(priv->phy, 1, &input);
+ if (ret != 0) {
+ ERROR("Execution FW failed (err %d)\n",
+ ret);
+ }
+ }
+ }
+#ifdef NXP_WARM_BOOT
+ if (priv->warm_boot_flag != DDR_WRM_BOOT_NT_SUPPORTED &&
+ ret == 0) {
+ debug("save the phy training data\n");
+ //Save training data TBD
+ ret = save_phy_training_values(priv->phy,
+ PHY_TRAINING_REGS_ON_FLASH,
+ priv->num_ctlrs,
+ input.basic.train2d);
+ if (ret != 0) {
+ ERROR("Saving training data failed.");
+ ERROR("Warm boot will fail. Error=%d.\n", ret);
+ }
+ }
+ } /* else */
+#endif
+
+ if (ret == 0) {
+ debug("Load PIE\n");
+ i_load_pie(priv->phy, &input, &msg_1d);
+
+ NOTICE("DDR4 %s with %d-rank %d-bit bus (x%d)\n",
+ input.basic.dimm_type == RDIMM ? "RDIMM" :
+ input.basic.dimm_type == LRDIMM ? "LRDIMM" :
+ "UDIMM",
+ dimm_param->n_ranks,
+ dimm_param->primary_sdram_width,
+ dimm_param->device_width);
+ }
+#ifdef DEBUG_DDR_INPUT_CONFIG
+ print_jason_format(&input, &msg_1d, &msg_2d);
+#endif
+
+ return ret;
+}
diff --git a/drivers/nxp/ddr/phy-gen2/phy.h b/drivers/nxp/ddr/phy-gen2/phy.h
new file mode 100644
index 0000000..15e80d1
--- /dev/null
+++ b/drivers/nxp/ddr/phy-gen2/phy.h
@@ -0,0 +1,334 @@
+/*
+ * Copyright 2021 NXP
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#if !defined(PHY_H) && defined(NXP_WARM_BOOT)
+#define PHY_H
+
+#include <flash_info.h>
+
+/* To store sector size to be erase on flash*/
+#define PHY_ERASE_SIZE F_SECTOR_ERASE_SZ
+
+/*Structure to implement address-data map tuples to store PHY training values*/
+struct phy_training_values {
+ uint32_t addr;
+ uint16_t data;
+};
+/* Saves PHY Training Register values after cold reset
+ *@param[in] phy_ptr array to store addresses of PHYs
+ *@param[in] address_to_store address to save PHY training register values
+ *on flash
+ *@param[in] num_of_phy the number of PHY for which training values are
+ *to be saved
+ *@param[in] train2d flag to store whether 2D training registers are to
+ *be saved or not
+ *
+ *PHY training values will be stored on flash at contigous memory in the order:
+ *1D training registers, 2D training registers
+ *for each PHY
+ *
+ *if train2d is false saving 2D training registers will be skipped
+ */
+int save_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_store,
+ uint32_t num_of_phy, int train2d);
+
+/*Restores PHY Training Register values after warm reset
+ *@param[in] phy_ptr array to store addresses of PHYs
+ *@param[in] address_to_store address to retrieve PHY training register
+ *values from flash
+ *@param[in] num_of_phy the number of PHY for which training values are
+ *to be restored
+ *@param[in] train2d flag to store whether 2D training registers are
+ *to be restored or not
+ *
+ *if train2d is false saving 2D training registers will be skipped
+ */
+
+int restore_phy_training_values(uint16_t **phy_ptr, uint32_t address_to_restore,
+ uint32_t num_of_phy, int train2d);
+
+/*
+ * Address data tuples to store the PHY 1D
+ */
+
+struct phy_training_values training_1D_values[] = {
+ {0x200B2, 0}, {0x200CB, 0}, {0x10043, 0}, {0x11043, 0},
+ {0x12043, 0}, {0x13043, 0}, {0x14043, 0}, {0x15043, 0},
+ {0x16043, 0}, {0x17043, 0}, {0x18043, 0}, {0x10143, 0},
+ {0x11143, 0}, {0x12143, 0}, {0x13143, 0}, {0x14143, 0},
+ {0x15143, 0}, {0x16143, 0}, {0x17143, 0}, {0x18143, 0},
+ {0x10080, 0}, {0x11080, 0}, {0x12080, 0}, {0x13080, 0},
+ {0x14080, 0}, {0x15080, 0}, {0x16080, 0}, {0x17080, 0},
+ {0x18080, 0}, {0x10180, 0}, {0x11180, 0}, {0x12180, 0},
+ {0x13180, 0}, {0x14180, 0}, {0x15180, 0}, {0x16180, 0},
+ {0x17180, 0}, {0x18180, 0}, {0x10081, 0}, {0x11081, 0},
+ {0x12081, 0}, {0x13081, 0}, {0x14081, 0}, {0x15081, 0},
+ {0x16081, 0}, {0x17081, 0}, {0x18081, 0}, {0x10181, 0},
+ {0x11181, 0}, {0x12181, 0}, {0x13181, 0}, {0x14181, 0},
+ {0x15181, 0}, {0x16181, 0}, {0x17181, 0}, {0x18181, 0},
+ {0x10082, 0}, {0x11082, 0}, {0x12082, 0}, {0x13082, 0},
+ {0x14082, 0}, {0x15082, 0}, {0x16082, 0}, {0x17082, 0},
+ {0x18082, 0}, {0x10182, 0}, {0x11182, 0}, {0x12182, 0},
+ {0x13182, 0}, {0x14182, 0}, {0x15182, 0}, {0x16182, 0},
+ {0x17182, 0}, {0x18182, 0}, {0x10083, 0}, {0x11083, 0},
+ {0x12083, 0}, {0x13083, 0}, {0x14083, 0}, {0x15083, 0},
+ {0x16083, 0}, {0x17083, 0}, {0x18083, 0}, {0x10183, 0},
+ {0x11183, 0}, {0x12183, 0}, {0x13183, 0}, {0x14183, 0},
+ {0x15183, 0}, {0x16183, 0}, {0x17183, 0}, {0x18183, 0},
+ {0x100D0, 0}, {0x110D0, 0}, {0x120D0, 0}, {0x130D0, 0},
+ {0x140D0, 0}, {0x150D0, 0}, {0x160D0, 0}, {0x170D0, 0},
+ {0x180D0, 0}, {0x101D0, 0}, {0x111D0, 0}, {0x121D0, 0},
+ {0x131D0, 0}, {0x141D0, 0}, {0x151D0, 0}, {0x161D0, 0},
+ {0x171D0, 0}, {0x181D0, 0}, {0x100D1, 0}, {0x110D1, 0},
+ {0x120D1, 0}, {0x130D1, 0}, {0x140D1, 0}, {0x150D1, 0},
+ {0x160D1, 0}, {0x170D1, 0}, {0x180D1, 0}, {0x101D1, 0},
+ {0x111D1, 0}, {0x121D1, 0}, {0x131D1, 0}, {0x141D1, 0},
+ {0x151D1, 0}, {0x161D1, 0}, {0x171D1, 0}, {0x181D1, 0},
+ {0x100D2, 0}, {0x110D2, 0}, {0x120D2, 0}, {0x130D2, 0},
+ {0x140D2, 0}, {0x150D2, 0}, {0x160D2, 0}, {0x170D2, 0},
+ {0x180D2, 0}, {0x101D2, 0}, {0x111D2, 0}, {0x121D2, 0},
+ {0x131D2, 0}, {0x141D2, 0}, {0x151D2, 0}, {0x161D2, 0},
+ {0x171D2, 0}, {0x181D2, 0}, {0x100D3, 0}, {0x110D3, 0},
+ {0x120D3, 0}, {0x130D3, 0}, {0x140D3, 0}, {0x150D3, 0},
+ {0x160D3, 0}, {0x170D3, 0}, {0x180D3, 0}, {0x101D3, 0},
+ {0x111D3, 0}, {0x121D3, 0}, {0x131D3, 0}, {0x141D3, 0},
+ {0x151D3, 0}, {0x161D3, 0}, {0x171D3, 0}, {0x181D3, 0},
+ {0x10068, 0}, {0x11068, 0}, {0x12068, 0}, {0x13068, 0},
+ {0x14068, 0}, {0x15068, 0}, {0x16068, 0}, {0x17068, 0},
+ {0x18068, 0}, {0x10168, 0}, {0x11168, 0}, {0x12168, 0},
+ {0x13168, 0}, {0x14168, 0}, {0x15168, 0}, {0x16168, 0},
+ {0x17168, 0}, {0x18168, 0}, {0x10268, 0}, {0x11268, 0},
+ {0x12268, 0}, {0x13268, 0}, {0x14268, 0}, {0x15268, 0},
+ {0x16268, 0}, {0x17268, 0}, {0x18268, 0}, {0x10368, 0},
+ {0x11368, 0}, {0x12368, 0}, {0x13368, 0}, {0x14368, 0},
+ {0x15368, 0}, {0x16368, 0}, {0x17368, 0}, {0x18368, 0},
+ {0x10468, 0}, {0x11468, 0}, {0x12468, 0}, {0x13468, 0},
+ {0x14468, 0}, {0x15468, 0}, {0x16468, 0}, {0x17468, 0},
+ {0x18468, 0}, {0x10568, 0}, {0x11568, 0}, {0x12568, 0},
+ {0x13568, 0}, {0x14568, 0}, {0x15568, 0}, {0x16568, 0},
+ {0x17568, 0}, {0x18568, 0}, {0x10668, 0}, {0x11668, 0},
+ {0x12668, 0}, {0x13668, 0}, {0x14668, 0}, {0x15668, 0},
+ {0x16668, 0}, {0x17668, 0}, {0x18668, 0}, {0x10768, 0},
+ {0x11768, 0}, {0x12768, 0}, {0x13768, 0}, {0x14768, 0},
+ {0x15768, 0}, {0x16768, 0}, {0x17768, 0}, {0x18768, 0},
+ {0x10868, 0}, {0x11868, 0}, {0x12868, 0}, {0x13868, 0},
+ {0x14868, 0}, {0x15868, 0}, {0x16868, 0}, {0x17868, 0},
+ {0x18868, 0}, {0x10069, 0}, {0x11069, 0}, {0x12069, 0},
+ {0x13069, 0}, {0x14069, 0}, {0x15069, 0}, {0x16069, 0},
+ {0x17069, 0}, {0x18069, 0}, {0x10169, 0}, {0x11169, 0},
+ {0x12169, 0}, {0x13169, 0}, {0x14169, 0}, {0x15169, 0},
+ {0x16169, 0}, {0x17169, 0}, {0x18169, 0}, {0x10269, 0},
+ {0x11269, 0}, {0x12269, 0}, {0x13269, 0}, {0x14269, 0},
+ {0x15269, 0}, {0x16269, 0}, {0x17269, 0}, {0x18269, 0},
+ {0x10369, 0}, {0x11369, 0}, {0x12369, 0}, {0x13369, 0},
+ {0x14369, 0}, {0x15369, 0}, {0x16369, 0}, {0x17369, 0},
+ {0x18369, 0}, {0x10469, 0}, {0x11469, 0}, {0x12469, 0},
+ {0x13469, 0}, {0x14469, 0}, {0x15469, 0}, {0x16469, 0},
+ {0x17469, 0}, {0x18469, 0}, {0x10569, 0}, {0x11569, 0},
+ {0x12569, 0}, {0x13569, 0}, {0x14569, 0}, {0x15569, 0},
+ {0x16569, 0}, {0x17569, 0}, {0x18569, 0}, {0x10669, 0},
+ {0x11669, 0}, {0x12669, 0}, {0x13669, 0}, {0x14669, 0},
+ {0x15669, 0}, {0x16669, 0}, {0x17669, 0}, {0x18669, 0},
+ {0x10769, 0}, {0x11769, 0}, {0x12769, 0}, {0x13769, 0},
+ {0x14769, 0}, {0x15769, 0}, {0x16769, 0}, {0x17769, 0},
+ {0x18769, 0}, {0x10869, 0}, {0x11869, 0}, {0x12869, 0},
+ {0x13869, 0}, {0x14869, 0}, {0x15869, 0}, {0x16869, 0},
+ {0x17869, 0}, {0x18869, 0}, {0x1006A, 0}, {0x1106A, 0},
+ {0x1206A, 0}, {0x1306A, 0}, {0x1406A, 0}, {0x1506A, 0},
+ {0x1606A, 0}, {0x1706A, 0}, {0x1806A, 0}, {0x1016A, 0},
+ {0x1116A, 0}, {0x1216A, 0}, {0x1316A, 0}, {0x1416A, 0},
+ {0x1516A, 0}, {0x1616A, 0}, {0x1716A, 0}, {0x1816A, 0},
+ {0x1026A, 0}, {0x1126A, 0}, {0x1226A, 0}, {0x1326A, 0},
+ {0x1426A, 0}, {0x1526A, 0}, {0x1626A, 0}, {0x1726A, 0},
+ {0x1826A, 0}, {0x1036A, 0}, {0x1136A, 0}, {0x1236A, 0},
+ {0x1336A, 0}, {0x1436A, 0}, {0x1536A, 0}, {0x1636A, 0},
+ {0x1736A, 0}, {0x1836A, 0}, {0x1046A, 0}, {0x1146A, 0},
+ {0x1246A, 0}, {0x1346A, 0}, {0x1446A, 0}, {0x1546A, 0},
+ {0x1646A, 0}, {0x1746A, 0}, {0x1846A, 0}, {0x1056A, 0},
+ {0x1156A, 0}, {0x1256A, 0}, {0x1356A, 0}, {0x1456A, 0},
+ {0x1556A, 0}, {0x1656A, 0}, {0x1756A, 0}, {0x1856A, 0},
+ {0x1066A, 0}, {0x1166A, 0}, {0x1266A, 0}, {0x1366A, 0},
+ {0x1466A, 0}, {0x1566A, 0}, {0x1666A, 0}, {0x1766A, 0},
+ {0x1866A, 0}, {0x1076A, 0}, {0x1176A, 0}, {0x1276A, 0},
+ {0x1376A, 0}, {0x1476A, 0}, {0x1576A, 0}, {0x1676A, 0},
+ {0x1776A, 0}, {0x1876A, 0}, {0x1086A, 0}, {0x1186A, 0},
+ {0x1286A, 0}, {0x1386A, 0}, {0x1486A, 0}, {0x1586A, 0},
+ {0x1686A, 0}, {0x1786A, 0}, {0x1886A, 0}, {0x1006B, 0},
+ {0x1106B, 0}, {0x1206B, 0}, {0x1306B, 0}, {0x1406B, 0},
+ {0x1506B, 0}, {0x1606B, 0}, {0x1706B, 0}, {0x1806B, 0},
+ {0x1016B, 0}, {0x1116B, 0}, {0x1216B, 0}, {0x1316B, 0},
+ {0x1416B, 0}, {0x1516B, 0}, {0x1616B, 0}, {0x1716B, 0},
+ {0x1816B, 0}, {0x1026B, 0}, {0x1126B, 0}, {0x1226B, 0},
+ {0x1326B, 0}, {0x1426B, 0}, {0x1526B, 0}, {0x1626B, 0},
+ {0x1726B, 0}, {0x1826B, 0}, {0x1036B, 0}, {0x1136B, 0},
+ {0x1236B, 0}, {0x1336B, 0}, {0x1436B, 0}, {0x1536B, 0},
+ {0x1636B, 0}, {0x1736B, 0}, {0x1836B, 0}, {0x1046B, 0},
+ {0x1146B, 0}, {0x1246B, 0}, {0x1346B, 0}, {0x1446B, 0},
+ {0x1546B, 0}, {0x1646B, 0}, {0x1746B, 0}, {0x1846B, 0},
+ {0x1056B, 0}, {0x1156B, 0}, {0x1256B, 0}, {0x1356B, 0},
+ {0x1456B, 0}, {0x1556B, 0}, {0x1656B, 0}, {0x1756B, 0},
+ {0x1856B, 0}, {0x1066B, 0}, {0x1166B, 0}, {0x1266B, 0},
+ {0x1366B, 0}, {0x1466B, 0}, {0x1566B, 0}, {0x1666B, 0},
+ {0x1766B, 0}, {0x1866B, 0}, {0x1076B, 0}, {0x1176B, 0},
+ {0x1276B, 0}, {0x1376B, 0}, {0x1476B, 0}, {0x1576B, 0},
+ {0x1676B, 0}, {0x1776B, 0}, {0x1876B, 0}, {0x1086B, 0},
+ {0x1186B, 0}, {0x1286B, 0}, {0x1386B, 0}, {0x1486B, 0},
+ {0x1586B, 0}, {0x1686B, 0}, {0x1786B, 0}, {0x1886B, 0},
+ {0x1008C, 0}, {0x1108C, 0}, {0x1208C, 0}, {0x1308C, 0},
+ {0x1408C, 0}, {0x1508C, 0}, {0x1608C, 0}, {0x1708C, 0},
+ {0x1808C, 0}, {0x1018C, 0}, {0x1118C, 0}, {0x1218C, 0},
+ {0x1318C, 0}, {0x1418C, 0}, {0x1518C, 0}, {0x1618C, 0},
+ {0x1718C, 0}, {0x1818C, 0}, {0x1008D, 0}, {0x1108D, 0},
+ {0x1208D, 0}, {0x1308D, 0}, {0x1408D, 0}, {0x1508D, 0},
+ {0x1608D, 0}, {0x1708D, 0}, {0x1808D, 0}, {0x1018D, 0},
+ {0x1118D, 0}, {0x1218D, 0}, {0x1318D, 0}, {0x1418D, 0},
+ {0x1518D, 0}, {0x1618D, 0}, {0x1718D, 0}, {0x1818D, 0},
+ {0x1008E, 0}, {0x1108E, 0}, {0x1208E, 0}, {0x1308E, 0},
+ {0x1408E, 0}, {0x1508E, 0}, {0x1608E, 0}, {0x1708E, 0},
+ {0x1808E, 0}, {0x1018E, 0}, {0x1118E, 0}, {0x1218E, 0},
+ {0x1318E, 0}, {0x1418E, 0}, {0x1518E, 0}, {0x1618E, 0},
+ {0x1718E, 0}, {0x1818E, 0}, {0x1008F, 0}, {0x1108F, 0},
+ {0x1208F, 0}, {0x1308F, 0}, {0x1408F, 0}, {0x1508F, 0},
+ {0x1608F, 0}, {0x1708F, 0}, {0x1808F, 0}, {0x1018F, 0},
+ {0x1118F, 0}, {0x1218F, 0}, {0x1318F, 0}, {0x1418F, 0},
+ {0x1518F, 0}, {0x1618F, 0}, {0x1718F, 0}, {0x1818F, 0},
+ {0x100C0, 0}, {0x110C0, 0}, {0x120C0, 0}, {0x130C0, 0},
+ {0x140C0, 0}, {0x150C0, 0}, {0x160C0, 0}, {0x170C0, 0},
+ {0x180C0, 0}, {0x101C0, 0}, {0x111C0, 0}, {0x121C0, 0},
+ {0x131C0, 0}, {0x141C0, 0}, {0x151C0, 0}, {0x161C0, 0},
+ {0x171C0, 0}, {0x181C0, 0}, {0x102C0, 0}, {0x112C0, 0},
+ {0x122C0, 0}, {0x132C0, 0}, {0x142C0, 0}, {0x152C0, 0},
+ {0x162C0, 0}, {0x172C0, 0}, {0x182C0, 0}, {0x103C0, 0},
+ {0x113C0, 0}, {0x123C0, 0}, {0x133C0, 0}, {0x143C0, 0},
+ {0x153C0, 0}, {0x163C0, 0}, {0x173C0, 0}, {0x183C0, 0},
+ {0x104C0, 0}, {0x114C0, 0}, {0x124C0, 0}, {0x134C0, 0},
+ {0x144C0, 0}, {0x154C0, 0}, {0x164C0, 0}, {0x174C0, 0},
+ {0x184C0, 0}, {0x105C0, 0}, {0x115C0, 0}, {0x125C0, 0},
+ {0x135C0, 0}, {0x145C0, 0}, {0x155C0, 0}, {0x165C0, 0},
+ {0x175C0, 0}, {0x185C0, 0}, {0x106C0, 0}, {0x116C0, 0},
+ {0x126C0, 0}, {0x136C0, 0}, {0x146C0, 0}, {0x156C0, 0},
+ {0x166C0, 0}, {0x176C0, 0}, {0x186C0, 0}, {0x107C0, 0},
+ {0x117C0, 0}, {0x127C0, 0}, {0x137C0, 0}, {0x147C0, 0},
+ {0x157C0, 0}, {0x167C0, 0}, {0x177C0, 0}, {0x187C0, 0},
+ {0x108C0, 0}, {0x118C0, 0}, {0x128C0, 0}, {0x138C0, 0},
+ {0x148C0, 0}, {0x158C0, 0}, {0x168C0, 0}, {0x178C0, 0},
+ {0x188C0, 0}, {0x100C1, 0}, {0x110C1, 0}, {0x120C1, 0},
+ {0x130C1, 0}, {0x140C1, 0}, {0x150C1, 0}, {0x160C1, 0},
+ {0x170C1, 0}, {0x180C1, 0}, {0x101C1, 0}, {0x111C1, 0},
+ {0x121C1, 0}, {0x131C1, 0}, {0x141C1, 0}, {0x151C1, 0},
+ {0x161C1, 0}, {0x171C1, 0}, {0x181C1, 0}, {0x102C1, 0},
+ {0x112C1, 0}, {0x122C1, 0}, {0x132C1, 0}, {0x142C1, 0},
+ {0x152C1, 0}, {0x162C1, 0}, {0x172C1, 0}, {0x182C1, 0},
+ {0x103C1, 0}, {0x113C1, 0}, {0x123C1, 0}, {0x133C1, 0},
+ {0x143C1, 0}, {0x153C1, 0}, {0x163C1, 0}, {0x173C1, 0},
+ {0x183C1, 0}, {0x104C1, 0}, {0x114C1, 0}, {0x124C1, 0},
+ {0x134C1, 0}, {0x144C1, 0}, {0x154C1, 0}, {0x164C1, 0},
+ {0x174C1, 0}, {0x184C1, 0}, {0x105C1, 0}, {0x115C1, 0},
+ {0x125C1, 0}, {0x135C1, 0}, {0x145C1, 0}, {0x155C1, 0},
+ {0x165C1, 0}, {0x175C1, 0}, {0x185C1, 0}, {0x106C1, 0},
+ {0x116C1, 0}, {0x126C1, 0}, {0x136C1, 0}, {0x146C1, 0},
+ {0x156C1, 0}, {0x166C1, 0}, {0x176C1, 0}, {0x186C1, 0},
+ {0x107C1, 0}, {0x117C1, 0}, {0x127C1, 0}, {0x137C1, 0},
+ {0x147C1, 0}, {0x157C1, 0}, {0x167C1, 0}, {0x177C1, 0},
+ {0x187C1, 0}, {0x108C1, 0}, {0x118C1, 0}, {0x128C1, 0},
+ {0x138C1, 0}, {0x148C1, 0}, {0x158C1, 0}, {0x168C1, 0},
+ {0x178C1, 0}, {0x188C1, 0}, {0x100C2, 0}, {0x110C2, 0},
+ {0x120C2, 0}, {0x130C2, 0}, {0x140C2, 0}, {0x150C2, 0},
+ {0x160C2, 0}, {0x170C2, 0}, {0x180C2, 0}, {0x101C2, 0},
+ {0x111C2, 0}, {0x121C2, 0}, {0x131C2, 0}, {0x141C2, 0},
+ {0x151C2, 0}, {0x161C2, 0}, {0x171C2, 0}, {0x181C2, 0},
+ {0x102C2, 0}, {0x112C2, 0}, {0x122C2, 0}, {0x132C2, 0},
+ {0x142C2, 0}, {0x152C2, 0}, {0x162C2, 0}, {0x172C2, 0},
+ {0x182C2, 0}, {0x103C2, 0}, {0x113C2, 0}, {0x123C2, 0},
+ {0x133C2, 0}, {0x143C2, 0}, {0x153C2, 0}, {0x163C2, 0},
+ {0x173C2, 0}, {0x183C2, 0}, {0x104C2, 0}, {0x114C2, 0},
+ {0x124C2, 0}, {0x134C2, 0}, {0x144C2, 0}, {0x154C2, 0},
+ {0x164C2, 0}, {0x174C2, 0}, {0x184C2, 0}, {0x105C2, 0},
+ {0x115C2, 0}, {0x125C2, 0}, {0x135C2, 0}, {0x145C2, 0},
+ {0x155C2, 0}, {0x165C2, 0}, {0x175C2, 0}, {0x185C2, 0},
+ {0x106C2, 0}, {0x116C2, 0}, {0x126C2, 0}, {0x136C2, 0},
+ {0x146C2, 0}, {0x156C2, 0}, {0x166C2, 0}, {0x176C2, 0},
+ {0x186C2, 0}, {0x107C2, 0}, {0x117C2, 0}, {0x127C2, 0},
+ {0x137C2, 0}, {0x147C2, 0}, {0x157C2, 0}, {0x167C2, 0},
+ {0x177C2, 0}, {0x187C2, 0}, {0x108C2, 0}, {0x118C2, 0},
+ {0x128C2, 0}, {0x138C2, 0}, {0x148C2, 0}, {0x158C2, 0},
+ {0x168C2, 0}, {0x178C2, 0}, {0x188C2, 0}, {0x100C3, 0},
+ {0x110C3, 0}, {0x120C3, 0}, {0x130C3, 0}, {0x140C3, 0},
+ {0x150C3, 0}, {0x160C3, 0}, {0x170C3, 0}, {0x180C3, 0},
+ {0x101C3, 0}, {0x111C3, 0}, {0x121C3, 0}, {0x131C3, 0},
+ {0x141C3, 0}, {0x151C3, 0}, {0x161C3, 0}, {0x171C3, 0},
+ {0x181C3, 0}, {0x102C3, 0}, {0x112C3, 0}, {0x122C3, 0},
+ {0x132C3, 0}, {0x142C3, 0}, {0x152C3, 0}, {0x162C3, 0},
+ {0x172C3, 0}, {0x182C3, 0}, {0x103C3, 0}, {0x113C3, 0},
+ {0x123C3, 0}, {0x133C3, 0}, {0x143C3, 0}, {0x153C3, 0},
+ {0x163C3, 0}, {0x173C3, 0}, {0x183C3, 0}, {0x104C3, 0},
+ {0x114C3, 0}, {0x124C3, 0}, {0x134C3, 0}, {0x144C3, 0},
+ {0x154C3, 0}, {0x164C3, 0}, {0x174C3, 0}, {0x184C3, 0},
+ {0x105C3, 0}, {0x115C3, 0}, {0x125C3, 0}, {0x135C3, 0},
+ {0x145C3, 0}, {0x155C3, 0}, {0x165C3, 0}, {0x175C3, 0},
+ {0x185C3, 0}, {0x106C3, 0}, {0x116C3, 0}, {0x126C3, 0},
+ {0x136C3, 0}, {0x146C3, 0}, {0x156C3, 0}, {0x166C3, 0},
+ {0x176C3, 0}, {0x186C3, 0}, {0x107C3, 0}, {0x117C3, 0},
+ {0x127C3, 0}, {0x137C3, 0}, {0x147C3, 0}, {0x157C3, 0},
+ {0x167C3, 0}, {0x177C3, 0}, {0x187C3, 0}, {0x108C3, 0},
+ {0x118C3, 0}, {0x128C3, 0}, {0x138C3, 0}, {0x148C3, 0},
+ {0x158C3, 0}, {0x168C3, 0}, {0x178C3, 0}, {0x188C3, 0},
+ {0x10020, 0}, {0x11020, 0}, {0x12020, 0}, {0x13020, 0},
+ {0x14020, 0}, {0x15020, 0}, {0x16020, 0}, {0x17020, 0},
+ {0x18020, 0}, {0x2007D, 0}, {0x20077, 0}
+};
+
+/*
+ *Array to store the PHY 2D Training register addresses
+ */
+struct phy_training_values training_2D_values[] = {
+ {0x1008C, 0}, {0x1108C, 0}, {0x1208C, 0}, {0x1308C, 0},
+ {0x1408C, 0}, {0x1508C, 0}, {0x1608C, 0}, {0x1708C, 0},
+ {0x1808C, 0}, {0x1018C, 0}, {0x1118C, 0}, {0x1218C, 0},
+ {0x1318C, 0}, {0x1418C, 0}, {0x1518C, 0}, {0x1618C, 0},
+ {0x1718C, 0}, {0x1818C, 0}, {0x10040, 0}, {0x11040, 0},
+ {0x12040, 0}, {0x13040, 0}, {0x14040, 0}, {0x15040, 0},
+ {0x16040, 0}, {0x17040, 0}, {0x18040, 0}, {0x10140, 0},
+ {0x11140, 0}, {0x12140, 0}, {0x13140, 0}, {0x14140, 0},
+ {0x15140, 0}, {0x16140, 0}, {0x17140, 0}, {0x18140, 0},
+ {0x10240, 0}, {0x11240, 0}, {0x12240, 0}, {0x13240, 0},
+ {0x14240, 0}, {0x15240, 0}, {0x16240, 0}, {0x17240, 0},
+ {0x18240, 0}, {0x10340, 0}, {0x11340, 0}, {0x12340, 0},
+ {0x13340, 0}, {0x14340, 0}, {0x15340, 0}, {0x16340, 0},
+ {0x17340, 0}, {0x18340, 0}, {0x10440, 0}, {0x11440, 0},
+ {0x12440, 0}, {0x13440, 0}, {0x14440, 0}, {0x15440, 0},
+ {0x16440, 0}, {0x17440, 0}, {0x18440, 0}, {0x10540, 0},
+ {0x11540, 0}, {0x12540, 0}, {0x13540, 0}, {0x14540, 0},
+ {0x15540, 0}, {0x16540, 0}, {0x17540, 0}, {0x18540, 0},
+ {0x10640, 0}, {0x11640, 0}, {0x12640, 0}, {0x13640, 0},
+ {0x14640, 0}, {0x15640, 0}, {0x16640, 0}, {0x17640, 0},
+ {0x18640, 0}, {0x10740, 0}, {0x11740, 0}, {0x12740, 0},
+ {0x13740, 0}, {0x14740, 0}, {0x15740, 0}, {0x16740, 0},
+ {0x17740, 0}, {0x18740, 0}, {0x10840, 0}, {0x11840, 0},
+ {0x12840, 0}, {0x13840, 0}, {0x14840, 0}, {0x15840, 0},
+ {0x16840, 0}, {0x17840, 0}, {0x18840, 0}, {0x10030, 0},
+ {0x11030, 0}, {0x12030, 0}, {0x13030, 0}, {0x14030, 0},
+ {0x15030, 0}, {0x16030, 0}, {0x17030, 0}, {0x18030, 0},
+ {0x10130, 0}, {0x11130, 0}, {0x12130, 0}, {0x13130, 0},
+ {0x14130, 0}, {0x15130, 0}, {0x16130, 0}, {0x17130, 0},
+ {0x18130, 0}, {0x10230, 0}, {0x11230, 0}, {0x12230, 0},
+ {0x13230, 0}, {0x14230, 0}, {0x15230, 0}, {0x16230, 0},
+ {0x17230, 0}, {0x18230, 0}, {0x10330, 0}, {0x11330, 0},
+ {0x12330, 0}, {0x13330, 0}, {0x14330, 0}, {0x15330, 0},
+ {0x16330, 0}, {0x17330, 0}, {0x18330, 0}, {0x10430, 0},
+ {0x11430, 0}, {0x12430, 0}, {0x13430, 0}, {0x14430, 0},
+ {0x15430, 0}, {0x16430, 0}, {0x17430, 0}, {0x18430, 0},
+ {0x10530, 0}, {0x11530, 0}, {0x12530, 0}, {0x13530, 0},
+ {0x14530, 0}, {0x15530, 0}, {0x16530, 0}, {0x17530, 0},
+ {0x18530, 0}, {0x10630, 0}, {0x11630, 0}, {0x12630, 0},
+ {0x13630, 0}, {0x14630, 0}, {0x15630, 0}, {0x16630, 0},
+ {0x17630, 0}, {0x18630, 0}, {0x10730, 0}, {0x11730, 0},
+ {0x12730, 0}, {0x13730, 0}, {0x14730, 0}, {0x15730, 0},
+ {0x16730, 0}, {0x17730, 0}, {0x18730, 0}, {0x10830, 0},
+ {0x11830, 0}, {0x12830, 0}, {0x13830, 0}, {0x14830, 0},
+ {0x15830, 0}, {0x16830, 0}, {0x17830, 0}, {0x18830, 0}
+};
+
+#endif
diff --git a/drivers/nxp/ddr/phy-gen2/pie.h b/drivers/nxp/ddr/phy-gen2/pie.h
new file mode 100644
index 0000000..b89066a
--- /dev/null
+++ b/drivers/nxp/ddr/phy-gen2/pie.h
@@ -0,0 +1,632 @@
+/*
+ * Copyright 2021 NXP
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PIE_H
+#define PIE_H
+
+struct pie {
+ uint32_t addr;
+ uint16_t data;
+};
+
+static const struct pie pie_udimm[] = {
+ {0x90000, 0x10},
+ {0x90001, 0x400},
+ {0x90002, 0x10e},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x8},
+ {0x90029, 0xb},
+ {0x9002a, 0x480},
+ {0x9002b, 0x109},
+ {0x9002c, 0x8},
+ {0x9002d, 0x448},
+ {0x9002e, 0x139},
+ {0x9002f, 0x8},
+ {0x90030, 0x478},
+ {0x90031, 0x109},
+ {0x90032, 0x2},
+ {0x90033, 0x10},
+ {0x90034, 0x139},
+ {0x90035, 0xb},
+ {0x90036, 0x7c0},
+ {0x90037, 0x139},
+ {0x90038, 0x44},
+ {0x90039, 0x633},
+ {0x9003a, 0x159},
+ {0x9003b, 0x14f},
+ {0x9003c, 0x630},
+ {0x9003d, 0x159},
+ {0x9003e, 0x47},
+ {0x9003f, 0x633},
+ {0x90040, 0x149},
+ {0x90041, 0x4f},
+ {0x90042, 0x633},
+ {0x90043, 0x179},
+ {0x90044, 0x8},
+ {0x90045, 0xe0},
+ {0x90046, 0x109},
+ {0x90047, 0x0},
+ {0x90048, 0x7c8},
+ {0x90049, 0x109},
+ {0x9004a, 0x0},
+ {0x9004b, 0x1},
+ {0x9004c, 0x8},
+ {0x9004d, 0x0},
+ {0x9004e, 0x45a},
+ {0x9004f, 0x9},
+ {0x90050, 0x0},
+ {0x90051, 0x448},
+ {0x90052, 0x109},
+ {0x90053, 0x40},
+ {0x90054, 0x633},
+ {0x90055, 0x179},
+ {0x90056, 0x1},
+ {0x90057, 0x618},
+ {0x90058, 0x109},
+ {0x90059, 0x40c0},
+ {0x9005a, 0x633},
+ {0x9005b, 0x149},
+ {0x9005c, 0x8},
+ {0x9005d, 0x4},
+ {0x9005e, 0x48},
+ {0x9005f, 0x4040},
+ {0x90060, 0x633},
+ {0x90061, 0x149},
+ {0x90062, 0x0},
+ {0x90063, 0x4},
+ {0x90064, 0x48},
+ {0x90065, 0x40},
+ {0x90066, 0x633},
+ {0x90067, 0x149},
+ {0x90068, 0x10},
+ {0x90069, 0x4},
+ {0x9006a, 0x18},
+ {0x9006b, 0x0},
+ {0x9006c, 0x4},
+ {0x9006d, 0x78},
+ {0x9006e, 0x549},
+ {0x9006f, 0x633},
+ {0x90070, 0x159},
+ {0x90071, 0xd49},
+ {0x90072, 0x633},
+ {0x90073, 0x159},
+ {0x90074, 0x94a},
+ {0x90075, 0x633},
+ {0x90076, 0x159},
+ {0x90077, 0x441},
+ {0x90078, 0x633},
+ {0x90079, 0x149},
+ {0x9007a, 0x42},
+ {0x9007b, 0x633},
+ {0x9007c, 0x149},
+ {0x9007d, 0x1},
+ {0x9007e, 0x633},
+ {0x9007f, 0x149},
+ {0x90080, 0x0},
+ {0x90081, 0xe0},
+ {0x90082, 0x109},
+ {0x90083, 0xa},
+ {0x90084, 0x10},
+ {0x90085, 0x109},
+ {0x90086, 0x9},
+ {0x90087, 0x3c0},
+ {0x90088, 0x149},
+ {0x90089, 0x9},
+ {0x9008a, 0x3c0},
+ {0x9008b, 0x159},
+ {0x9008c, 0x18},
+ {0x9008d, 0x10},
+ {0x9008e, 0x109},
+ {0x9008f, 0x0},
+ {0x90090, 0x3c0},
+ {0x90091, 0x109},
+ {0x90092, 0x18},
+ {0x90093, 0x4},
+ {0x90094, 0x48},
+ {0x90095, 0x18},
+ {0x90096, 0x4},
+ {0x90097, 0x58},
+ {0x90098, 0xb},
+ {0x90099, 0x10},
+ {0x9009a, 0x109},
+ {0x9009b, 0x1},
+ {0x9009c, 0x10},
+ {0x9009d, 0x109},
+ {0x9009e, 0x5},
+ {0x9009f, 0x7c0},
+ {0x900a0, 0x109},
+ {0x900a1, 0x0},
+ {0x900a2, 0x8140},
+ {0x900a3, 0x10c},
+ {0x900a4, 0x10},
+ {0x900a5, 0x8138},
+ {0x900a6, 0x10c},
+ {0x900a7, 0x8},
+ {0x900a8, 0x7c8},
+ {0x900a9, 0x101},
+ {0x900aa, 0x8},
+ {0x900ab, 0x448},
+ {0x900ac, 0x109},
+ {0x900ad, 0xf},
+ {0x900ae, 0x7c0},
+ {0x900af, 0x109},
+ {0x900b0, 0x47},
+ {0x900b1, 0x630},
+ {0x900b2, 0x109},
+ {0x900b3, 0x8},
+ {0x900b4, 0x618},
+ {0x900b5, 0x109},
+ {0x900b6, 0x8},
+ {0x900b7, 0xe0},
+ {0x900b8, 0x109},
+ {0x900b9, 0x0},
+ {0x900ba, 0x7c8},
+ {0x900bb, 0x109},
+ {0x900bc, 0x8},
+ {0x900bd, 0x8140},
+ {0x900be, 0x10c},
+ {0x900bf, 0x0},
+ {0x900c0, 0x478},
+ {0x900c1, 0x109},
+ {0x900c2, 0x0},
+ {0x900c3, 0x1},
+ {0x900c4, 0x8},
+ {0x900c5, 0x8},
+ {0x900c6, 0x4},
+ {0x900c7, 0x8},
+ {0x900c8, 0x8},
+ {0x900c9, 0x7c8},
+ {0x900ca, 0x101},
+ {0x90006, 0x0},
+ {0x90007, 0x0},
+ {0x90008, 0x8},
+ {0x90009, 0x0},
+ {0x9000a, 0x0},
+ {0x9000b, 0x0},
+ {0xd00e7, 0x400},
+ {0x90017, 0x0},
+ {0x90026, 0x2b},
+};
+
+static const struct pie pie_rdimm[] = {
+ {0x90000, 0x10},
+ {0x90001, 0x400},
+ {0x90002, 0x10e},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x8},
+ {0x40000, 0x10},
+ {0x40020, 0x0},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x70a},
+ {0x40021, 0x7005},
+ {0x40041, 0x0},
+ {0x40061, 0x2001},
+ {0x40002, 0x4010},
+ {0x40022, 0x0},
+ {0x40042, 0x0},
+ {0x40062, 0x0},
+ {0x90029, 0x10},
+ {0x9002a, 0x400},
+ {0x9002b, 0x16e},
+ {0x9002c, 0x8},
+ {0x9002d, 0x370},
+ {0x9002e, 0x169},
+ {0x9002f, 0x8},
+ {0x90030, 0x7aa},
+ {0x90031, 0x6a},
+ {0x90032, 0x10},
+ {0x90033, 0x7b2},
+ {0x90034, 0x6a},
+ {0x90035, 0x0},
+ {0x90036, 0x48a},
+ {0x90037, 0x6a},
+ {0x90038, 0x9},
+ {0x90039, 0x480},
+ {0x9003a, 0x16a},
+ {0x9003b, 0x4},
+ {0x9003c, 0x790},
+ {0x9003d, 0x16a},
+ {0x9003e, 0xc},
+ {0x9003f, 0x408},
+ {0x90040, 0x169},
+ {0x90041, 0xa},
+ {0x90042, 0x0},
+ {0x90043, 0x68},
+ {0x90044, 0x0},
+ {0x90045, 0x408},
+ {0x90046, 0x169},
+ {0x90047, 0x1},
+ {0x90048, 0x480},
+ {0x90049, 0x16a},
+ {0x9004a, 0xb},
+ {0x9004b, 0x480},
+ {0x9004c, 0x109},
+ {0x9004d, 0x8},
+ {0x9004e, 0x448},
+ {0x9004f, 0x139},
+ {0x90050, 0x78},
+ {0x90051, 0x8},
+ {0x90052, 0x139},
+ {0x90053, 0x2},
+ {0x90054, 0x10},
+ {0x90055, 0x139},
+ {0x90056, 0xb},
+ {0x90057, 0x7c0},
+ {0x90058, 0x139},
+ {0x90059, 0x44},
+ {0x9005a, 0x633},
+ {0x9005b, 0x159},
+ {0x9005c, 0x14f},
+ {0x9005d, 0x630},
+ {0x9005e, 0x159},
+ {0x9005f, 0x47},
+ {0x90060, 0x633},
+ {0x90061, 0x149},
+ {0x90062, 0x4f},
+ {0x90063, 0x633},
+ {0x90064, 0x179},
+ {0x90065, 0x8},
+ {0x90066, 0xe0},
+ {0x90067, 0x109},
+ {0x90068, 0x0},
+ {0x90069, 0x7c8},
+ {0x9006a, 0x109},
+ {0x9006b, 0x0},
+ {0x9006c, 0x1},
+ {0x9006d, 0x8},
+ {0x9006e, 0x0},
+ {0x9006f, 0x45a},
+ {0x90070, 0x9},
+ {0x90071, 0x0},
+ {0x90072, 0x448},
+ {0x90073, 0x109},
+ {0x90074, 0x40},
+ {0x90075, 0x633},
+ {0x90076, 0x179},
+ {0x90077, 0x1},
+ {0x90078, 0x618},
+ {0x90079, 0x109},
+ {0x9007a, 0x40c0},
+ {0x9007b, 0x633},
+ {0x9007c, 0x149},
+ {0x9007d, 0x8},
+ {0x9007e, 0x4},
+ {0x9007f, 0x48},
+ {0x90080, 0x4040},
+ {0x90081, 0x633},
+ {0x90082, 0x149},
+ {0x90083, 0x0},
+ {0x90084, 0x4},
+ {0x90085, 0x48},
+ {0x90086, 0x40},
+ {0x90087, 0x633},
+ {0x90088, 0x149},
+ {0x90089, 0x10},
+ {0x9008a, 0x4},
+ {0x9008b, 0x18},
+ {0x9008c, 0x0},
+ {0x9008d, 0x4},
+ {0x9008e, 0x78},
+ {0x9008f, 0x549},
+ {0x90090, 0x633},
+ {0x90091, 0x159},
+ {0x90092, 0xd49},
+ {0x90093, 0x633},
+ {0x90094, 0x159},
+ {0x90095, 0x94a},
+ {0x90096, 0x633},
+ {0x90097, 0x159},
+ {0x90098, 0x441},
+ {0x90099, 0x633},
+ {0x9009a, 0x149},
+ {0x9009b, 0x42},
+ {0x9009c, 0x633},
+ {0x9009d, 0x149},
+ {0x9009e, 0x1},
+ {0x9009f, 0x633},
+ {0x900a0, 0x149},
+ {0x900a1, 0x0},
+ {0x900a2, 0xe0},
+ {0x900a3, 0x109},
+ {0x900a4, 0xa},
+ {0x900a5, 0x10},
+ {0x900a6, 0x109},
+ {0x900a7, 0x9},
+ {0x900a8, 0x3c0},
+ {0x900a9, 0x149},
+ {0x900aa, 0x9},
+ {0x900ab, 0x3c0},
+ {0x900ac, 0x159},
+ {0x900ad, 0x18},
+ {0x900ae, 0x10},
+ {0x900af, 0x109},
+ {0x900b0, 0x0},
+ {0x900b1, 0x3c0},
+ {0x900b2, 0x109},
+ {0x900b3, 0x18},
+ {0x900b4, 0x4},
+ {0x900b5, 0x48},
+ {0x900b6, 0x18},
+ {0x900b7, 0x4},
+ {0x900b8, 0x58},
+ {0x900b9, 0xb},
+ {0x900ba, 0x10},
+ {0x900bb, 0x109},
+ {0x900bc, 0x1},
+ {0x900bd, 0x10},
+ {0x900be, 0x109},
+ {0x900bf, 0x5},
+ {0x900c0, 0x7c0},
+ {0x900c1, 0x109},
+ {0x900c2, 0x3},
+ {0x900c3, 0x370},
+ {0x900c4, 0x169},
+ {0x900c5, 0x3},
+ {0x900c6, 0x8},
+ {0x900c7, 0x139},
+ {0x900c8, 0x0},
+ {0x900c9, 0x400},
+ {0x900ca, 0x16e},
+ {0x900cb, 0x8},
+ {0x900cc, 0x478},
+ {0x900cd, 0x109},
+ {0x900ce, 0x0},
+ {0x900cf, 0x8140},
+ {0x900d0, 0x10c},
+ {0x900d1, 0x10},
+ {0x900d2, 0x8138},
+ {0x900d3, 0x10c},
+ {0x900d4, 0x8},
+ {0x900d5, 0x7c8},
+ {0x900d6, 0x101},
+ {0x900d7, 0x7a},
+ {0x900d8, 0x8},
+ {0x900d9, 0x109},
+ {0x900da, 0x8},
+ {0x900db, 0x448},
+ {0x900dc, 0x109},
+ {0x900dd, 0xf},
+ {0x900de, 0x7c0},
+ {0x900df, 0x109},
+ {0x900e0, 0x47},
+ {0x900e1, 0x630},
+ {0x900e2, 0x109},
+ {0x900e3, 0x8},
+ {0x900e4, 0x618},
+ {0x900e5, 0x109},
+ {0x900e6, 0x8},
+ {0x900e7, 0xe0},
+ {0x900e8, 0x109},
+ {0x900e9, 0x0},
+ {0x900ea, 0x8},
+ {0x900eb, 0x109},
+ {0x900ec, 0x0},
+ {0x900ed, 0x7c8},
+ {0x900ee, 0x109},
+ {0x900ef, 0x8},
+ {0x900f0, 0x8140},
+ {0x900f1, 0x10c},
+ {0x900f2, 0x0},
+ {0x900f3, 0x478},
+ {0x900f4, 0x109},
+ {0x900f5, 0x0},
+ {0x900f6, 0x1},
+ {0x900f7, 0x8},
+ {0x900f8, 0x8},
+ {0x900f9, 0x4},
+ {0x900fa, 0x8},
+ {0x900fb, 0x8},
+ {0x900fc, 0x7c8},
+ {0x900fd, 0x101},
+ {0x90006, 0x0},
+ {0x90007, 0x0},
+ {0x90008, 0x8},
+ {0x90009, 0x0},
+ {0x9000a, 0x0},
+ {0x9000b, 0x0},
+ {0xd00e7, 0x400},
+ {0x90017, 0x0},
+ {0x90026, 0x3a},
+};
+
+static const struct pie pie_lrdimm[] = {
+ {0x90000, 0x10},
+ {0x90001, 0x400},
+ {0x90002, 0x10e},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x8},
+ {0x90029, 0xb},
+ {0x9002a, 0x480},
+ {0x9002b, 0x109},
+ {0x9002c, 0x8},
+ {0x9002d, 0x448},
+ {0x9002e, 0x139},
+ {0x9002f, 0x78},
+ {0x90030, 0x8},
+ {0x90031, 0x139},
+ {0x90032, 0x2},
+ {0x90033, 0x10},
+ {0x90034, 0x139},
+ {0x90035, 0xb},
+ {0x90036, 0x7c0},
+ {0x90037, 0x139},
+ {0x90038, 0x44},
+ {0x90039, 0x633},
+ {0x9003a, 0x159},
+ {0x9003b, 0x14f},
+ {0x9003c, 0x630},
+ {0x9003d, 0x159},
+ {0x9003e, 0x47},
+ {0x9003f, 0x633},
+ {0x90040, 0x149},
+ {0x90041, 0x4f},
+ {0x90042, 0x633},
+ {0x90043, 0x179},
+ {0x90044, 0x8},
+ {0x90045, 0xe0},
+ {0x90046, 0x109},
+ {0x90047, 0x0},
+ {0x90048, 0x7c8},
+ {0x90049, 0x109},
+ {0x9004a, 0x0},
+ {0x9004b, 0x1},
+ {0x9004c, 0x8},
+ {0x9004d, 0x0},
+ {0x9004e, 0x45a},
+ {0x9004f, 0x9},
+ {0x90050, 0x0},
+ {0x90051, 0x448},
+ {0x90052, 0x109},
+ {0x90053, 0x40},
+ {0x90054, 0x633},
+ {0x90055, 0x179},
+ {0x90056, 0x1},
+ {0x90057, 0x618},
+ {0x90058, 0x109},
+ {0x90059, 0x40c0},
+ {0x9005a, 0x633},
+ {0x9005b, 0x149},
+ {0x9005c, 0x8},
+ {0x9005d, 0x4},
+ {0x9005e, 0x48},
+ {0x9005f, 0x4040},
+ {0x90060, 0x633},
+ {0x90061, 0x149},
+ {0x90062, 0x0},
+ {0x90063, 0x4},
+ {0x90064, 0x48},
+ {0x90065, 0x40},
+ {0x90066, 0x633},
+ {0x90067, 0x149},
+ {0x90068, 0x10},
+ {0x90069, 0x4},
+ {0x9006a, 0x18},
+ {0x9006b, 0x0},
+ {0x9006c, 0x4},
+ {0x9006d, 0x78},
+ {0x9006e, 0x549},
+ {0x9006f, 0x633},
+ {0x90070, 0x159},
+ {0x90071, 0xd49},
+ {0x90072, 0x633},
+ {0x90073, 0x159},
+ {0x90074, 0x94a},
+ {0x90075, 0x633},
+ {0x90076, 0x159},
+ {0x90077, 0x441},
+ {0x90078, 0x633},
+ {0x90079, 0x149},
+ {0x9007a, 0x42},
+ {0x9007b, 0x633},
+ {0x9007c, 0x149},
+ {0x9007d, 0x1},
+ {0x9007e, 0x633},
+ {0x9007f, 0x149},
+ {0x90080, 0x0},
+ {0x90081, 0xe0},
+ {0x90082, 0x109},
+ {0x90083, 0xa},
+ {0x90084, 0x10},
+ {0x90085, 0x109},
+ {0x90086, 0x9},
+ {0x90087, 0x3c0},
+ {0x90088, 0x149},
+ {0x90089, 0x9},
+ {0x9008a, 0x3c0},
+ {0x9008b, 0x159},
+ {0x9008c, 0x18},
+ {0x9008d, 0x10},
+ {0x9008e, 0x109},
+ {0x9008f, 0x0},
+ {0x90090, 0x3c0},
+ {0x90091, 0x109},
+ {0x90092, 0x18},
+ {0x90093, 0x4},
+ {0x90094, 0x48},
+ {0x90095, 0x18},
+ {0x90096, 0x4},
+ {0x90097, 0x58},
+ {0x90098, 0xb},
+ {0x90099, 0x10},
+ {0x9009a, 0x109},
+ {0x9009b, 0x1},
+ {0x9009c, 0x10},
+ {0x9009d, 0x109},
+ {0x9009e, 0x5},
+ {0x9009f, 0x7c0},
+ {0x900a0, 0x109},
+ {0x900a1, 0x3},
+ {0x900a2, 0x8},
+ {0x900a3, 0x139},
+ {0x900a4, 0x0},
+ {0x900a5, 0x400},
+ {0x900a6, 0x16e},
+ {0x900a7, 0x8},
+ {0x900a8, 0x478},
+ {0x900a9, 0x109},
+ {0x900aa, 0x0},
+ {0x900ab, 0x8140},
+ {0x900ac, 0x10c},
+ {0x900ad, 0x10},
+ {0x900ae, 0x8138},
+ {0x900af, 0x10c},
+ {0x900b0, 0x8},
+ {0x900b1, 0x7c8},
+ {0x900b2, 0x101},
+ {0x900b3, 0x7a},
+ {0x900b4, 0x8},
+ {0x900b5, 0x109},
+ {0x900b6, 0x8},
+ {0x900b7, 0x448},
+ {0x900b8, 0x109},
+ {0x900b9, 0xf},
+ {0x900ba, 0x7c0},
+ {0x900bb, 0x109},
+ {0x900bc, 0x47},
+ {0x900bd, 0x630},
+ {0x900be, 0x109},
+ {0x900bf, 0x8},
+ {0x900c0, 0x618},
+ {0x900c1, 0x109},
+ {0x900c2, 0x8},
+ {0x900c3, 0xe0},
+ {0x900c4, 0x109},
+ {0x900c5, 0x0},
+ {0x900c6, 0x8},
+ {0x900c7, 0x109},
+ {0x900c8, 0x0},
+ {0x900c9, 0x7c8},
+ {0x900ca, 0x109},
+ {0x900cb, 0x8},
+ {0x900cc, 0x8140},
+ {0x900cd, 0x10c},
+ {0x900ce, 0x0},
+ {0x900cf, 0x478},
+ {0x900d0, 0x109},
+ {0x900d1, 0x0},
+ {0x900d2, 0x1},
+ {0x900d3, 0x8},
+ {0x900d4, 0x8},
+ {0x900d5, 0x4},
+ {0x900d6, 0x8},
+ {0x900d7, 0x8},
+ {0x900d8, 0x7c8},
+ {0x900d9, 0x101},
+ {0x90006, 0x0},
+ {0x90007, 0x0},
+ {0x90008, 0x8},
+ {0x90009, 0x0},
+ {0x9000a, 0x0},
+ {0x9000b, 0x0},
+ {0xd00e7, 0x400},
+ {0x90017, 0x0},
+ {0x90026, 0x2e},
+};
+#endif
diff --git a/drivers/nxp/drivers.mk b/drivers/nxp/drivers.mk
new file mode 100644
index 0000000..c2db363
--- /dev/null
+++ b/drivers/nxp/drivers.mk
@@ -0,0 +1,91 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+
+###############################################################################
+
+
+PLAT_DRIVERS_PATH := drivers/nxp
+PLAT_DRIVERS_INCLUDE_PATH := include/drivers/nxp
+
+ifeq (${SMMU_NEEDED},yes)
+PLAT_INCLUDES += -Iinclude/drivers/nxp/smmu/
+endif
+
+ifeq (${DCFG_NEEDED},yes)
+include $(PLAT_DRIVERS_PATH)/dcfg/dcfg.mk
+endif
+
+ifeq (${CSU_NEEDED},yes)
+include $(PLAT_DRIVERS_PATH)/csu/csu.mk
+endif
+
+ifeq (${TIMER_NEEDED},yes)
+include $(PLAT_DRIVERS_PATH)/timer/timer.mk
+endif
+
+ifeq (${INTERCONNECT_NEEDED},yes)
+include ${PLAT_DRIVERS_PATH}/interconnect/interconnect.mk
+endif
+
+ifeq (${GIC_NEEDED},yes)
+include ${PLAT_DRIVERS_PATH}/gic/gic.mk
+endif
+
+ifeq (${SD_MMC_NEEDED},yes)
+include $(PLAT_DRIVERS_PATH)/sd/sd_mmc.mk
+endif
+
+ifeq (${CONSOLE_NEEDED},yes)
+include $(PLAT_DRIVERS_PATH)/console/console.mk
+endif
+
+ifeq (${SFP_NEEDED},yes)
+include $(PLAT_DRIVERS_PATH)/sfp/sfp.mk
+endif
+
+ifeq (${XSPI_NEEDED},yes)
+include $(PLAT_DRIVERS_PATH)/flexspi/nor/flexspi_nor.mk
+endif
+
+ifeq (${QSPI_NEEDED},yes)
+include $(PLAT_DRIVERS_PATH)/qspi/qspi.mk
+endif
+
+ifeq (${SNVS_NEEDED},yes)
+include $(PLAT_DRIVERS_PATH)/sec_mon/sec_mon.mk
+endif
+
+ifeq ($(I2C_NEEDED),yes)
+$(eval $(call add_define, I2C_INIT))
+include $(PLAT_DRIVERS_PATH)/i2c/i2c.mk
+endif
+
+ifeq ($(DDR_DRIVER_NEEDED),yes)
+$(eval $(call add_define, DDR_INIT))
+# define DDR_CNTRL_SOURCES
+ifeq ($(DDRCNTLR),MMDC)
+include $(PLAT_DRIVERS_PATH)/ddr/fsl-mmdc/ddr.mk
+else
+include $(PLAT_DRIVERS_PATH)/ddr/nxp-ddr/ddr.mk
+endif # DDR_CNTRL_SOURCES
+endif
+
+ifeq (${PMU_NEEDED},yes)
+include $(PLAT_DRIVERS_PATH)/pmu/pmu.mk
+endif
+
+ifeq (${CRYPTO_NEEDED},yes)
+include $(PLAT_DRIVERS_PATH)/crypto/caam/caam.mk
+endif
+
+ifeq (${TZASC_NEEDED},yes)
+include $(PLAT_DRIVERS_PATH)/tzc/tzc.mk
+endif
+
+ifeq (${GPIO_NEEDED},yes)
+include ${PLAT_DRIVERS_PATH}/gpio/gpio.mk
+endif
diff --git a/drivers/nxp/flexspi/nor/flexspi_nor.c b/drivers/nxp/flexspi/nor/flexspi_nor.c
new file mode 100644
index 0000000..748228d
--- /dev/null
+++ b/drivers/nxp/flexspi/nor/flexspi_nor.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <assert.h>
+
+#include <fspi_api.h>
+#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+
+int flexspi_nor_io_setup(uintptr_t nxp_flexspi_flash_addr,
+ size_t nxp_flexspi_flash_size, uint32_t fspi_base_reg_addr)
+{
+ int ret = 0;
+
+ ret = fspi_init(fspi_base_reg_addr, nxp_flexspi_flash_addr);
+ /* Adding NOR Memory Map in XLAT Table */
+ mmap_add_region(nxp_flexspi_flash_addr, nxp_flexspi_flash_addr,
+ nxp_flexspi_flash_size, MT_MEMORY | MT_RW);
+
+ return ret;
+}
diff --git a/drivers/nxp/flexspi/nor/flexspi_nor.h b/drivers/nxp/flexspi/nor/flexspi_nor.h
new file mode 100644
index 0000000..61fc236
--- /dev/null
+++ b/drivers/nxp/flexspi/nor/flexspi_nor.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef FLEXSPI_NOR_H
+#define FLEXSPI_NOR_H
+
+int flexspi_nor_io_setup(uintptr_t nxp_flexspi_flash_addr,
+ size_t nxp_flexspi_flash_size,
+ uint32_t fspi_base_reg_addr);
+
+#endif /* FLEXSPI_NOR_H */
diff --git a/drivers/nxp/flexspi/nor/flexspi_nor.mk b/drivers/nxp/flexspi/nor/flexspi_nor.mk
new file mode 100644
index 0000000..6d9eebb
--- /dev/null
+++ b/drivers/nxp/flexspi/nor/flexspi_nor.mk
@@ -0,0 +1,35 @@
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${XSPI_NOR},)
+XSPI_NOR := 1
+
+FLEXSPI_DRIVERS_PATH := ${PLAT_DRIVERS_PATH}/flexspi/nor
+
+PLAT_XSPI_INCLUDES += -I$(FLEXSPI_DRIVERS_PATH)
+
+XSPI_BOOT_SOURCES += $(FLEXSPI_DRIVERS_PATH)/flexspi_nor.c \
+ ${FLEXSPI_DRIVERS_PATH}/fspi.c
+ifeq ($(DEBUG),1)
+XSPI_BOOT_SOURCES += ${FLEXSPI_DRIVERS_PATH}/test_fspi.c
+endif
+
+PLAT_XSPI_INCLUDES += -Iinclude/drivers/nxp/flexspi
+
+PLAT_INCLUDES += ${PLAT_XSPI_INCLUDES}
+
+ifeq (${BL_COMM_XSPI_NEEDED},yes)
+BL_COMMON_SOURCES += ${XSPI_BOOT_SOURCES}
+else
+ifeq (${BL2_XSPI_NEEDED},yes)
+BL2_SOURCES += ${XSPI_BOOT_SOURCES}
+endif
+ifeq (${BL31_XSPI_NEEDED},yes)
+BL31_SOURCES += ${XSPI_BOOT_SOURCES}
+endif
+endif
+
+endif
diff --git a/drivers/nxp/flexspi/nor/fspi.c b/drivers/nxp/flexspi/nor/fspi.c
new file mode 100644
index 0000000..7c919b8
--- /dev/null
+++ b/drivers/nxp/flexspi/nor/fspi.c
@@ -0,0 +1,853 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * NXP FlexSpi Controller Driver.
+ * Copyright 2021 NXP
+ *
+ */
+#include <endian.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <flash_info.h>
+#include "fspi.h"
+#include <fspi_api.h>
+#include <xspi_error_codes.h>
+
+#ifdef DEBUG_FLEXSPI
+#define PR printf("In [%s][%d]\n", __func__, __LINE__)
+#define PRA(a, b) printf("In [%s][%d] %s="a"\n", __func__, __LINE__, #b, b)
+#else
+#define PR
+#define PRA(a, b)
+#endif
+
+/*
+ * This errata is valid for all NXP SoC.
+ */
+#define ERRATA_FLASH_A050272 1
+
+static uintptr_t fspi_base_reg_addr;
+static uintptr_t fspi_flash_base_addr;
+
+static void fspi_RDSR(uint32_t *, const void *, uint32_t);
+
+static void fspi_writel(uint32_t x_addr, uint32_t x_val)
+{
+ fspi_out32((uint32_t *)(fspi_base_reg_addr + x_addr),
+ (uint32_t) x_val);
+}
+
+static uint32_t fspi_readl(uint32_t x_addr)
+{
+ return fspi_in32((uint32_t *)(fspi_base_reg_addr + x_addr));
+}
+
+static void fspi_MDIS(uint8_t x_disable)
+{
+ uint32_t ui_reg;
+
+ ui_reg = fspi_readl(FSPI_MCR0);
+ if (x_disable != 0U) {
+ ui_reg |= FSPI_MCR0_MDIS;
+ } else {
+ ui_reg &= (uint32_t) (~FSPI_MCR0_MDIS);
+ }
+
+ fspi_writel(FSPI_MCR0, ui_reg);
+}
+
+static void fspi_lock_LUT(void)
+{
+ fspi_writel(FSPI_LUTKEY, FSPI_LUTKEY_VALUE);
+ VERBOSE("%s 0x%x\n", __func__, fspi_readl(FSPI_LCKCR));
+ fspi_writel(FSPI_LCKCR, FSPI_LCKER_LOCK);
+ VERBOSE("%s 0x%x\n", __func__, fspi_readl(FSPI_LCKCR));
+}
+
+static void fspi_unlock_LUT(void)
+{
+ fspi_writel(FSPI_LUTKEY, FSPI_LUTKEY_VALUE);
+ VERBOSE("%s 0x%x\n", __func__, fspi_readl(FSPI_LCKCR));
+ fspi_writel(FSPI_LCKCR, FSPI_LCKER_UNLOCK);
+ VERBOSE("%s 0x%x\n", __func__, fspi_readl(FSPI_LCKCR));
+}
+
+static void fspi_op_setup(uint32_t fspi_op_seq_id, bool ignore_flash_sz)
+{
+ uint32_t x_addr, x_instr0 = 0, x_instr1 = 0, x_instr2 = 0;
+ uint32_t cmd_id1, cmd_id2;
+
+ VERBOSE("In func %s\n", __func__);
+
+ switch (fspi_op_seq_id) {
+ case FSPI_READ_SEQ_ID:
+ cmd_id1 = FSPI_NOR_CMD_READ;
+ cmd_id2 = FSPI_NOR_CMD_READ_4B;
+ x_instr2 = FSPI_INSTR_OPRND0(0) | FSPI_INSTR_PAD0(FSPI_LUT_PAD1)
+ | FSPI_INSTR_OPCODE0(FSPI_LUT_READ);
+ break;
+ case FSPI_FASTREAD_SEQ_ID:
+ cmd_id1 = FSPI_NOR_CMD_FASTREAD;
+ cmd_id2 = FSPI_NOR_CMD_FASTREAD_4B;
+ x_instr2 = FSPI_INSTR_OPRND0(8) | FSPI_INSTR_PAD0(FSPI_LUT_PAD1)
+ | FSPI_INSTR_OPCODE0(FSPI_DUMMY_SDR)
+ | FSPI_INSTR_OPRND1(0)
+ | FSPI_INSTR_PAD1(FSPI_LUT_PAD1)
+ | FSPI_INSTR_OPCODE1(FSPI_LUT_READ);
+ break;
+ case FSPI_WRITE_SEQ_ID:
+ cmd_id1 = FSPI_NOR_CMD_PP;
+ cmd_id2 = FSPI_NOR_CMD_PP_4B;
+ x_instr2 = FSPI_INSTR_OPRND0(0) | FSPI_INSTR_PAD0(FSPI_LUT_PAD1)
+ | FSPI_INSTR_OPCODE0(FSPI_LUT_WRITE);
+ break;
+ case FSPI_WREN_SEQ_ID:
+ cmd_id1 = FSPI_NOR_CMD_WREN;
+ cmd_id2 = FSPI_NOR_CMD_WREN;
+ break;
+ case FSPI_SE_SEQ_ID:
+ cmd_id1 = FSPI_NOR_CMD_SE_64K;
+ cmd_id2 = FSPI_NOR_CMD_SE_64K_4B;
+ break;
+ case FSPI_4K_SEQ_ID:
+ cmd_id1 = FSPI_NOR_CMD_SE_4K;
+ cmd_id2 = FSPI_NOR_CMD_SE_4K_4B;
+ break;
+ case FSPI_BE_SEQ_ID:
+ cmd_id1 = FSPI_NOR_CMD_BE;
+ cmd_id2 = FSPI_NOR_CMD_BE;
+ break;
+ case FSPI_RDSR_SEQ_ID:
+ cmd_id1 = FSPI_NOR_CMD_RDSR;
+ cmd_id2 = FSPI_NOR_CMD_RDSR;
+ break;
+ }
+
+ x_addr = FSPI_LUTREG_OFFSET + (uint32_t)(0x10 * fspi_op_seq_id);
+ if ((F_FLASH_SIZE_BYTES <= SZ_16M_BYTES) || (ignore_flash_sz)) {
+ x_instr0 = FSPI_INSTR_OPRND0(cmd_id1);
+ x_instr1 = FSPI_INSTR_OPRND1(FSPI_LUT_ADDR24BIT);
+ VERBOSE("CMD_ID = %x offset = 0x%x\n", cmd_id1, x_addr);
+ } else {
+ x_instr0 = FSPI_INSTR_OPRND0(cmd_id2);
+ x_instr1 = FSPI_INSTR_OPRND1(FSPI_LUT_ADDR32BIT);
+ VERBOSE("CMD_ID = %x offset = 0x%x\n", cmd_id2, x_addr);
+ }
+ x_instr0 |= FSPI_INSTR_PAD0(FSPI_LUT_PAD1)
+ | FSPI_INSTR_OPCODE0(FSPI_LUT_CMD);
+
+ x_instr1 |= FSPI_INSTR_PAD1(FSPI_LUT_PAD1)
+ | FSPI_INSTR_OPCODE1(FSPI_LUT_ADDR);
+
+ if (fspi_op_seq_id == FSPI_RDSR_SEQ_ID) {
+ x_instr0 |= FSPI_INSTR_OPRND1(1) | FSPI_INSTR_PAD1(FSPI_LUT_PAD1)
+ | FSPI_INSTR_OPCODE1(FSPI_LUT_READ);
+ } else if ((fspi_op_seq_id != FSPI_BE_SEQ_ID)
+ && (fspi_op_seq_id != FSPI_WREN_SEQ_ID)) {
+ x_instr0 |= x_instr1;
+ }
+
+ fspi_writel((x_addr), x_instr0);
+ fspi_writel((x_addr + U(0x4)), x_instr2);
+ fspi_writel((x_addr + U(0x8)), (uint32_t) 0x0); /* STOP command */
+ fspi_writel((x_addr + U(0xc)), (uint32_t) 0x0); /* STOP command */
+}
+
+static void fspi_setup_LUT(void)
+{
+ VERBOSE("In func %s\n", __func__);
+ fspi_unlock_LUT();
+
+ /* LUT Setup for READ Command 3-Byte low Frequency */
+ fspi_op_setup(FSPI_READ_SEQ_ID, false);
+
+ /* LUT Setup for FAST READ Command 3-Byte/4-Byte high Frequency */
+ fspi_op_setup(FSPI_FASTREAD_SEQ_ID, false);
+
+ /* LUT Setup for Page Program */
+ fspi_op_setup(FSPI_WRITE_SEQ_ID, false);
+
+ /* LUT Setup for WREN */
+ fspi_op_setup(FSPI_WREN_SEQ_ID, true);
+
+ /* LUT Setup for Sector_Erase */
+ fspi_op_setup(FSPI_SE_SEQ_ID, false);
+
+ /* LUT Setup for Sub Sector 4K Erase */
+ fspi_op_setup(FSPI_4K_SEQ_ID, false);
+
+ /* LUT Setup for Bulk_Erase */
+ fspi_op_setup(FSPI_BE_SEQ_ID, true);
+
+ /* Read Status */
+ fspi_op_setup(FSPI_RDSR_SEQ_ID, true);
+
+ fspi_lock_LUT();
+}
+
+static inline void fspi_ahb_invalidate(void)
+{
+ uint32_t reg;
+
+ VERBOSE("In func %s %d\n", __func__, __LINE__);
+ reg = fspi_readl(FSPI_MCR0);
+ reg |= FSPI_MCR0_SWRST;
+ fspi_writel(FSPI_MCR0, reg);
+ while ((fspi_readl(FSPI_MCR0) & FSPI_MCR0_SWRST) != 0)
+ ; /* FSPI_MCR0_SWRESET_MASK */
+ VERBOSE("In func %s %d\n", __func__, __LINE__);
+}
+
+#if defined(CONFIG_FSPI_AHB)
+static void fspi_init_ahb(void)
+{
+ uint32_t i, x_flash_cr2, seq_id;
+
+ x_flash_cr2 = 0;
+ /* Reset AHB RX buffer CR configuration */
+ for (i = 0; i < 8; i++) {
+ fspi_writel((FSPI_AHBRX_BUF0CR0 + 4 * i), 0U);
+ }
+
+ /* Set ADATSZ with the maximum AHB buffer size */
+ fspi_writel(FSPI_AHBRX_BUF7CR0,
+ ((uint32_t) ((FSPI_RX_MAX_AHBBUF_SIZE / 8U) |
+ FSPI_AHBRXBUF0CR7_PREF)));
+
+ /* Known limitation handling: prefetch and
+ * no start address alignment.*/
+ fspi_writel(FSPI_AHBCR, FSPI_AHBCR_PREF_EN);
+ INFO("xAhbcr=0x%x\n", fspi_readl(FSPI_AHBCR));
+
+ // Setup AHB READ sequenceID for all flashes.
+ x_flash_cr2 = fspi_readl(FSPI_FLSHA1CR2);
+ INFO("x_flash_cr2=0x%x\n", x_flash_cr2);
+
+ seq_id = CONFIG_FSPI_FASTREAD ?
+ FSPI_FASTREAD_SEQ_ID : FSPI_READ_SEQ_ID;
+ x_flash_cr2 |= ((seq_id << FSPI_FLSHXCR2_ARDSEQI_SHIFT) & 0x1f);
+
+ INFO("x_flash_cr2=0x%x\n", x_flash_cr2);
+
+ fspi_writel(FSPI_FLSHA1CR2, x_flash_cr2);
+ x_flash_cr2 = fspi_readl(FSPI_FLSHA1CR2);
+ INFO("x_flash_cr2=0x%x\n", x_flash_cr2);
+}
+#endif
+
+int xspi_read(uint32_t pc_rx_addr, uint32_t *pc_rx_buf, uint32_t x_size_bytes)
+{
+ if (x_size_bytes == 0) {
+ ERROR("Zero length reads are not allowed\n");
+ return XSPI_READ_FAIL;
+ }
+
+#if defined(CONFIG_FSPI_AHB)
+ return xspi_ahb_read(pc_rx_addr, pc_rx_buf, x_size_bytes);
+#else
+ return xspi_ip_read(pc_rx_addr, pc_rx_buf, x_size_bytes);
+#endif
+}
+#if defined(CONFIG_FSPI_AHB)
+int xspi_ahb_read(uint32_t pc_rx_addr, uint32_t *pc_rx_buf, uint32_t x_size_bytes)
+{
+ VERBOSE("In func %s 0x%x\n", __func__, (pc_rx_addr));
+
+ if (F_FLASH_SIZE_BYTES <= SZ_16M_BYTES) {
+ pc_rx_addr = ((uint32_t)(pcRxAddr & MASK_24BIT_ADDRESS));
+ } else {
+ pc_rx_addr = ((uint32_t)(pcRxAddr & MASK_32BIT_ADDRESS));
+ }
+
+ pc_rx_addr = ((uint32_t)(pcRxAddr + fspi_flash_base_addr));
+
+ if (((pc_rx_addr % 4) != 0) || (((uintptr_t)pc_rx_buf % 4) != 0)) {
+ WARN("%s: unaligned Start Address src=%ld dst=0x%p\n",
+ __func__, (pc_rx_addr - fspi_flash_base_addr), pc_rx_buf);
+ }
+
+ /* Directly copy from AHB Buffer */
+ memcpy(pc_rx_buf, (void *)(uintptr_t)pc_rx_addr, x_size_bytes);
+
+ fspi_ahb_invalidate();
+ return XSPI_SUCCESS;
+}
+#endif
+
+int xspi_ip_read(uint32_t pc_rx_addr, uint32_t *pv_rx_buf, uint32_t ui_len)
+{
+
+ uint32_t i = 0U, j = 0U, x_rem = 0U;
+ uint32_t x_iteration = 0U, x_size_rx = 0U, x_size_wm, temp_size;
+ uint32_t data = 0U;
+ uint32_t x_len_bytes;
+ uint32_t x_addr, sts0, intr, seq_id;
+
+ x_addr = (uint32_t) pc_rx_addr;
+ x_len_bytes = ui_len;
+
+ /* Watermark level : 8 bytes. (BY DEFAULT) */
+ x_size_wm = 8U;
+
+ /* Clear RX Watermark interrupt in INT register, if any existing. */
+ fspi_writel(FSPI_INTR, FSPI_INTR_IPRXWA);
+ PRA("0x%x", fspi_readl(FSPI_INTR));
+ /* Invalid the RXFIFO, to run next IP Command */
+ /* Clears data entries in IP Rx FIFOs, Also reset R/W pointers */
+ fspi_writel(FSPI_IPRXFCR, FSPI_IPRXFCR_CLR);
+ fspi_writel(FSPI_INTR, FSPI_INTEN_IPCMDDONE);
+
+ while (x_len_bytes) {
+
+ /* FlexSPI can store no more than FSPI_RX_IPBUF_SIZE */
+ x_size_rx = (x_len_bytes > FSPI_RX_IPBUF_SIZE) ?
+ FSPI_RX_IPBUF_SIZE : x_len_bytes;
+
+ /* IP Control Register0 - SF Address to be read */
+ fspi_writel(FSPI_IPCR0, x_addr);
+ PRA("0x%x", fspi_readl(FSPI_IPCR0));
+ /* IP Control Register1 - SEQID_READ operation, Size */
+
+ seq_id = CONFIG_FSPI_FASTREAD ?
+ FSPI_FASTREAD_SEQ_ID : FSPI_READ_SEQ_ID;
+
+ fspi_writel(FSPI_IPCR1,
+ (uint32_t)(seq_id << FSPI_IPCR1_ISEQID_SHIFT) |
+ (uint16_t) x_size_rx);
+
+ PRA("0x%x", fspi_readl(FSPI_IPCR1));
+
+ do {
+ sts0 = fspi_readl(FSPI_STS0);
+ } while (((sts0 & FSPI_STS0_ARB_IDLE) == 0) &&
+ ((sts0 & FSPI_STS0_SEQ_IDLE) == 0));
+
+ /* Trigger IP Read Command */
+ fspi_writel(FSPI_IPCMD, FSPI_IPCMD_TRG_MASK);
+ PRA("0x%x", fspi_readl(FSPI_IPCMD));
+
+ intr = fspi_readl(FSPI_INTR);
+ if (((intr & FSPI_INTR_IPCMDGE) != 0) ||
+ ((intr & FSPI_INTR_IPCMDERR) != 0)) {
+ ERROR("Error in IP READ INTR=0x%x\n", intr);
+ return -XSPI_IP_READ_FAIL;
+ }
+ /* Will read in n iterations of each 8 FIFO's(WM level) */
+ x_iteration = x_size_rx / x_size_wm;
+ for (i = 0U; i < x_iteration; i++) {
+ if ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPRXWA_MASK) == 0) {
+ PRA("0x%x", fspi_readl(FSPI_INTR));
+ }
+ /* Wait for IP Rx Watermark Fill event */
+ while (!(fspi_readl(FSPI_INTR) & FSPI_INTR_IPRXWA_MASK)) {
+ PRA("0x%x", fspi_readl(FSPI_INTR));
+ }
+
+ /* Read RX FIFO's(upto WM level) & copy to rxbuffer */
+ for (j = 0U; j < x_size_wm; j += 4U) {
+ /* Read FIFO Data Register */
+ data = fspi_readl(FSPI_RFDR + j);
+#if FSPI_IPDATA_SWAP /* Just In case you want swap */
+ data = bswap32(data);
+#endif
+ memcpy(pv_rx_buf++, &data, 4);
+ }
+
+ /* Clear IP_RX_WATERMARK Event in INTR register */
+ /* Reset FIFO Read pointer for next iteration.*/
+ fspi_writel(FSPI_INTR, FSPI_INTR_IPRXWA);
+ }
+
+ x_rem = x_size_rx % x_size_wm;
+
+ if (x_rem != 0U) {
+ /* Wait for data filled */
+ while (!(fspi_readl(FSPI_IPRXFSTS) & FSPI_IPRXFSTS_FILL_MASK)) {
+ PRA("0x%x", fspi_readl(FSPI_IPRXFSTS));
+ }
+
+ temp_size = 0;
+ j = 0U;
+ while (x_rem > 0U) {
+ data = 0U;
+ data = fspi_readl(FSPI_RFDR + j);
+#if FSPI_IPDATA_SWAP /* Just In case you want swap */
+ data = bswap32(data);
+#endif
+ temp_size = (x_rem < 4) ? x_rem : 4;
+ memcpy(pv_rx_buf++, &data, temp_size);
+ x_rem -= temp_size;
+ }
+ }
+
+
+ while (!(fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK)) {
+ PRA("0x%x", fspi_readl(FSPI_INTR));
+ }
+
+ /* Invalid the RX FIFO, to run next IP Command */
+ fspi_writel(FSPI_IPRXFCR, FSPI_IPRXFCR_CLR);
+ /* Clear IP Command Done flag in interrupt register*/
+ fspi_writel(FSPI_INTR, FSPI_INTR_IPCMDDONE_MASK);
+
+ /* Update remaining len, Increment x_addr read pointer. */
+ x_len_bytes -= x_size_rx;
+ x_addr += x_size_rx;
+ }
+ PR;
+ return XSPI_SUCCESS;
+}
+
+void xspi_ip_write(uint32_t pc_wr_addr, uint32_t *pv_wr_buf, uint32_t ui_len)
+{
+
+ uint32_t x_iteration = 0U, x_rem = 0U;
+ uint32_t x_size_tx = 0U, x_size_wm, temp_size;
+ uint32_t i = 0U, j = 0U;
+ uint32_t ui_data = 0U;
+ uint32_t x_addr, x_len_bytes;
+
+
+ x_size_wm = 8U; /* Default TX WaterMark level: 8 Bytes. */
+ x_addr = (uint32_t)pc_wr_addr;
+ x_len_bytes = ui_len;
+ VERBOSE("In func %s[%d] x_addr =0x%x xLen_bytes=%d\n",
+ __func__, __LINE__, x_addr, x_len_bytes);
+
+ while (x_len_bytes != 0U) {
+
+ x_size_tx = (x_len_bytes > FSPI_TX_IPBUF_SIZE) ?
+ FSPI_TX_IPBUF_SIZE : x_len_bytes;
+
+ /* IP Control Register0 - SF Address to be read */
+ fspi_writel(FSPI_IPCR0, x_addr);
+ INFO("In func %s[%d] x_addr =0x%x xLen_bytes=%d\n",
+ __func__, __LINE__, x_addr, x_len_bytes);
+
+ /*
+ * Fill TX FIFO's..
+ *
+ */
+
+ x_iteration = x_size_tx / x_size_wm;
+ for (i = 0U; i < x_iteration; i++) {
+
+ /* Ensure TX FIFO Watermark Available */
+ while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPTXWE_MASK) == 0)
+ ;
+
+
+ /* Fill TxFIFO's ( upto watermark level) */
+ for (j = 0U; j < x_size_wm; j += 4U) {
+ memcpy(&ui_data, pv_wr_buf++, 4);
+ /* Write TX FIFO Data Register */
+ fspi_writel((FSPI_TFDR + j), ui_data);
+
+ }
+
+ /* Clear IP_TX_WATERMARK Event in INTR register */
+ /* Reset the FIFO Write pointer for next iteration */
+ fspi_writel(FSPI_INTR, FSPI_INTR_IPTXWE);
+ }
+
+ x_rem = x_size_tx % x_size_wm;
+
+ if (x_rem != 0U) {
+ /* Wait for TXFIFO empty */
+ while (!(fspi_readl(FSPI_INTR) & FSPI_INTR_IPTXWE))
+ ;
+
+ temp_size = 0U;
+ j = 0U;
+ while (x_rem > 0U) {
+ ui_data = 0U;
+ temp_size = (x_rem < 4U) ? x_rem : 4U;
+ memcpy(&ui_data, pv_wr_buf++, temp_size);
+ INFO("%d ---> pv_wr_buf=0x%p\n", __LINE__, pv_wr_buf);
+ fspi_writel((FSPI_TFDR + j), ui_data);
+ x_rem -= temp_size;
+ j += 4U ; /* TODO: May not be needed*/
+ }
+ /* Clear IP_TX_WATERMARK Event in INTR register */
+ /* Reset FIFO's Write pointer for next iteration.*/
+ fspi_writel(FSPI_INTR, FSPI_INTR_IPTXWE);
+ }
+
+ /* IP Control Register1 - SEQID_WRITE operation, Size */
+ fspi_writel(FSPI_IPCR1, (uint32_t)(FSPI_WRITE_SEQ_ID << FSPI_IPCR1_ISEQID_SHIFT) | (uint16_t) x_size_tx);
+ /* Trigger IP Write Command */
+ fspi_writel(FSPI_IPCMD, FSPI_IPCMD_TRG_MASK);
+
+ /* Wait for IP Write command done */
+ while (!(fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK))
+ ;
+
+ /* Invalidate TX FIFOs & acknowledge IP_CMD_DONE event */
+ fspi_writel(FSPI_IPTXFCR, FSPI_IPTXFCR_CLR);
+ fspi_writel(FSPI_INTR, FSPI_INTR_IPCMDDONE_MASK);
+
+ /* for next iteration */
+ x_len_bytes -= x_size_tx;
+ x_addr += x_size_tx;
+ }
+
+}
+
+int xspi_write(uint32_t pc_wr_addr, void *pv_wr_buf, uint32_t ui_len)
+{
+
+ uint32_t x_addr;
+ uint32_t x_page1_len = 0U, x_page_l_len = 0U;
+ uint32_t i, j = 0U;
+ void *buf = pv_wr_buf;
+
+ VERBOSE("\nIn func %s\n", __func__);
+
+ x_addr = (uint32_t)(pc_wr_addr);
+ if ((ui_len <= F_PAGE_256) && ((x_addr % F_PAGE_256) == 0)) {
+ x_page1_len = ui_len;
+ INFO("%d ---> x_page1_len=0x%x x_page_l_len =0x%x j=0x%x\n", __LINE__, x_page1_len, x_page_l_len, j);
+ } else if ((ui_len <= F_PAGE_256) && ((x_addr % F_PAGE_256) != 0)) {
+ x_page1_len = (F_PAGE_256 - (x_addr % F_PAGE_256));
+ if (ui_len > x_page1_len) {
+ x_page_l_len = (ui_len - x_page1_len) % F_PAGE_256;
+ } else {
+ x_page1_len = ui_len;
+ x_page_l_len = 0;
+ }
+ j = 0U;
+ INFO("%d 0x%x 0x%x\n", x_addr % F_PAGE_256, x_addr % F_PAGE_256, F_PAGE_256);
+ INFO("%d ---> x_page1_len=0x%x x_page_l_len =0x%x j=0x%x\n", __LINE__, x_page1_len, x_page_l_len, j);
+ } else if ((ui_len > F_PAGE_256) && ((x_addr % F_PAGE_256) == 0)) {
+ j = ui_len / F_PAGE_256;
+ x_page_l_len = ui_len % F_PAGE_256;
+ INFO("%d ---> x_page1_len=0x%x x_page_l_len =0x%x j=0x%x\n", __LINE__, x_page1_len, x_page_l_len, j);
+ } else if ((ui_len > F_PAGE_256) && ((x_addr % F_PAGE_256) != 0)) {
+ x_page1_len = (F_PAGE_256 - (x_addr % F_PAGE_256));
+ j = (ui_len - x_page1_len) / F_PAGE_256;
+ x_page_l_len = (ui_len - x_page1_len) % F_PAGE_256;
+ INFO("%d ---> x_page1_len=0x%x x_page_l_len =0x%x j=0x%x\n", __LINE__, x_page1_len, x_page_l_len, j);
+ }
+
+ if (x_page1_len != 0U) {
+ xspi_wren(x_addr);
+ xspi_ip_write(x_addr, (uint32_t *)buf, x_page1_len);
+ while (is_flash_busy())
+ ;
+ INFO("%d Initial pc_wr_addr=0x%x, Final x_addr=0x%x, Initial ui_len=0x%x Final ui_len=0x%x\n",
+ __LINE__, pc_wr_addr, x_addr, ui_len, (x_addr-pc_wr_addr));
+ INFO("Initial Buf pv_wr_buf=%p, final Buf=%p\n", pv_wr_buf, buf);
+ x_addr += x_page1_len;
+ /* TODO What is buf start is not 4 aligned */
+ buf = buf + x_page1_len;
+ }
+
+ for (i = 0U; i < j; i++) {
+ INFO("In for loop Buf pv_wr_buf=%p, final Buf=%p x_addr=0x%x offset_buf %d.\n",
+ pv_wr_buf, buf, x_addr, x_page1_len/4);
+ xspi_wren(x_addr);
+ xspi_ip_write(x_addr, (uint32_t *)buf, F_PAGE_256);
+ while (is_flash_busy())
+ ;
+ INFO("%d Initial pc_wr_addr=0x%x, Final x_addr=0x%x, Initial ui_len=0x%x Final ui_len=0x%x\n",
+ __LINE__, pc_wr_addr, x_addr, ui_len, (x_addr-pc_wr_addr));
+ x_addr += F_PAGE_256;
+ /* TODO What is buf start is not 4 aligned */
+ buf = buf + F_PAGE_256;
+ INFO("Initial Buf pv_wr_buf=%p, final Buf=%p\n", pv_wr_buf, buf);
+ }
+
+ if (x_page_l_len != 0U) {
+ INFO("%d Initial Buf pv_wr_buf=%p, final Buf=%p x_page_l_len=0x%x\n", __LINE__, pv_wr_buf, buf, x_page_l_len);
+ xspi_wren(x_addr);
+ xspi_ip_write(x_addr, (uint32_t *)buf, x_page_l_len);
+ while (is_flash_busy())
+ ;
+ INFO("%d Initial pc_wr_addr=0x%x, Final x_addr=0x%x, Initial ui_len=0x%x Final ui_len=0x%x\n",
+ __LINE__, pc_wr_addr, x_addr, ui_len, (x_addr-pc_wr_addr));
+ }
+
+ VERBOSE("Now calling func call Invalidate%s\n", __func__);
+ fspi_ahb_invalidate();
+ return XSPI_SUCCESS;
+}
+
+int xspi_wren(uint32_t pc_wr_addr)
+{
+ VERBOSE("In func %s Addr=0x%x\n", __func__, pc_wr_addr);
+
+ fspi_writel(FSPI_IPTXFCR, FSPI_IPTXFCR_CLR);
+
+ fspi_writel(FSPI_IPCR0, (uint32_t)pc_wr_addr);
+ fspi_writel(FSPI_IPCR1, ((FSPI_WREN_SEQ_ID << FSPI_IPCR1_ISEQID_SHIFT) | 0));
+ fspi_writel(FSPI_IPCMD, FSPI_IPCMD_TRG_MASK);
+
+ while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK) == 0)
+ ;
+
+ fspi_writel(FSPI_INTR, FSPI_INTR_IPCMDDONE_MASK);
+ return XSPI_SUCCESS;
+}
+
+static void fspi_bbluk_er(void)
+{
+ VERBOSE("In func %s\n", __func__);
+ fspi_writel(FSPI_IPCR0, 0x0);
+ fspi_writel(FSPI_IPCR1, ((FSPI_BE_SEQ_ID << FSPI_IPCR1_ISEQID_SHIFT) | 20));
+ fspi_writel(FSPI_IPCMD, FSPI_IPCMD_TRG_MASK);
+
+ while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK) == 0)
+ ;
+ fspi_writel(FSPI_INTR, FSPI_INTR_IPCMDDONE_MASK);
+
+}
+
+static void fspi_RDSR(uint32_t *rxbuf, const void *p_addr, uint32_t size)
+{
+ uint32_t iprxfcr = 0U;
+ uint32_t data = 0U;
+
+ iprxfcr = fspi_readl(FSPI_IPRXFCR);
+ /* IP RX FIFO would be read by processor */
+ iprxfcr = iprxfcr & (uint32_t)~FSPI_IPRXFCR_CLR;
+ /* Invalid data entries in IP RX FIFO */
+ iprxfcr = iprxfcr | FSPI_IPRXFCR_CLR;
+ fspi_writel(FSPI_IPRXFCR, iprxfcr);
+
+ fspi_writel(FSPI_IPCR0, (uintptr_t) p_addr);
+ fspi_writel(FSPI_IPCR1,
+ (uint32_t) ((FSPI_RDSR_SEQ_ID << FSPI_IPCR1_ISEQID_SHIFT)
+ | (uint16_t) size));
+ /* Trigger the command */
+ fspi_writel(FSPI_IPCMD, FSPI_IPCMD_TRG_MASK);
+ /* Wait for command done */
+ while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK) == 0)
+ ;
+ fspi_writel(FSPI_INTR, FSPI_INTR_IPCMDDONE_MASK);
+
+ data = fspi_readl(FSPI_RFDR);
+ memcpy(rxbuf, &data, size);
+
+ /* Rx FIFO invalidation needs to be done prior w1c of INTR.IPRXWA bit */
+ fspi_writel(FSPI_IPRXFCR, FSPI_IPRXFCR_CLR);
+ fspi_writel(FSPI_INTR, FSPI_INTR_IPRXWA_MASK);
+ fspi_writel(FSPI_INTR, FSPI_INTR_IPCMDDONE_MASK);
+
+}
+
+bool is_flash_busy(void)
+{
+#define FSPI_ONE_BYTE 1
+ uint8_t data[4];
+
+ VERBOSE("In func %s\n\n", __func__);
+ fspi_RDSR((uint32_t *) data, 0, FSPI_ONE_BYTE);
+
+ return !!((uint32_t) data[0] & FSPI_NOR_SR_WIP_MASK);
+}
+
+int xspi_bulk_erase(void)
+{
+ VERBOSE("In func %s\n", __func__);
+ xspi_wren((uint32_t) 0x0);
+ fspi_bbluk_er();
+ while (is_flash_busy())
+ ;
+ fspi_ahb_invalidate();
+ return XSPI_SUCCESS;
+}
+
+static void fspi_sec_er(uint32_t pc_wr_addr)
+{
+ uint32_t x_addr;
+
+ VERBOSE("In func %s\n", __func__);
+ x_addr = (uint32_t)(pc_wr_addr);
+
+ fspi_writel(FSPI_IPCR0, x_addr);
+ INFO("In [%s][%d] Erase address 0x%x\n", __func__, __LINE__, (x_addr));
+#if CONFIG_FSPI_ERASE_4K
+ fspi_writel(FSPI_IPCR1, ((FSPI_4K_SEQ_ID << FSPI_IPCR1_ISEQID_SHIFT) | 0));
+#else
+ fspi_writel(FSPI_IPCR1, ((FSPI_SE_SEQ_ID << FSPI_IPCR1_ISEQID_SHIFT) | 0));
+#endif
+ fspi_writel(FSPI_IPCMD, FSPI_IPCMD_TRG_MASK);
+
+ while ((fspi_readl(FSPI_INTR) & FSPI_INTR_IPCMDDONE_MASK) == 0) {
+ PRA("0x%x", fspi_readl(FSPI_INTR));
+ }
+ fspi_writel(FSPI_INTR, FSPI_INTR_IPCMDDONE_MASK);
+}
+
+int xspi_sector_erase(uint32_t pc_wr_addr, uint32_t ui_len)
+{
+ uint32_t x_addr, x_len_bytes, i, num_sector = 0U;
+
+ VERBOSE("In func %s\n", __func__);
+ x_addr = (uint32_t)(pc_wr_addr);
+ if ((x_addr % F_SECTOR_ERASE_SZ) != 0) {
+ ERROR("!!! In func %s, unalinged start address can only be in multiples of 0x%x\n",
+ __func__, F_SECTOR_ERASE_SZ);
+ return -XSPI_ERASE_FAIL;
+ }
+
+ x_len_bytes = ui_len * 1;
+ if (x_len_bytes < F_SECTOR_ERASE_SZ) {
+ ERROR("!!! In func %s, Less than 1 sector can only be in multiples of 0x%x\n",
+ __func__, F_SECTOR_ERASE_SZ);
+ return -XSPI_ERASE_FAIL;
+ }
+
+ num_sector = x_len_bytes/F_SECTOR_ERASE_SZ;
+ num_sector += x_len_bytes % F_SECTOR_ERASE_SZ ? 1U : 0U;
+ INFO("F_SECTOR_ERASE_SZ: 0x%08x, num_sector: %d\n", F_SECTOR_ERASE_SZ, num_sector);
+
+ for (i = 0U; i < num_sector ; i++) {
+ xspi_wren(x_addr + (F_SECTOR_ERASE_SZ * i));
+ fspi_sec_er(x_addr + (F_SECTOR_ERASE_SZ * i));
+ while (is_flash_busy())
+ ;
+ }
+ fspi_ahb_invalidate();
+ return XSPI_SUCCESS;
+}
+
+
+__attribute__((unused)) static void fspi_delay_ms(uint32_t x)
+{
+ volatile unsigned long ul_count;
+
+ for (ul_count = 0U; ul_count < (30U * x); ul_count++)
+ ;
+
+}
+
+
+#if defined(DEBUG_FLEXSPI)
+static void fspi_dump_regs(void)
+{
+ uint32_t i;
+
+ VERBOSE("\nRegisters Dump:\n");
+ VERBOSE("Flexspi: Register FSPI_MCR0(0x%x) = 0x%08x\n", FSPI_MCR0, fspi_readl(FSPI_MCR0));
+ VERBOSE("Flexspi: Register FSPI_MCR2(0x%x) = 0x%08x\n", FSPI_MCR2, fspi_readl(FSPI_MCR2));
+ VERBOSE("Flexspi: Register FSPI_DLL_A_CR(0x%x) = 0x%08x\n", FSPI_DLLACR, fspi_readl(FSPI_DLLACR));
+ VERBOSE("\n");
+
+ for (i = 0U; i < 8U; i++) {
+ VERBOSE("Flexspi: Register FSPI_AHBRX_BUF0CR0(0x%x) = 0x%08x\n", FSPI_AHBRX_BUF0CR0 + i * 4, fspi_readl((FSPI_AHBRX_BUF0CR0 + i * 4)));
+ }
+ VERBOSE("\n");
+
+ VERBOSE("Flexspi: Register FSPI_AHBRX_BUF7CR0(0x%x) = 0x%08x\n", FSPI_AHBRX_BUF7CR0, fspi_readl(FSPI_AHBRX_BUF7CR0));
+ VERBOSE("Flexspi: Register FSPI_AHB_CR(0x%x) \t = 0x%08x\n", FSPI_AHBCR, fspi_readl(FSPI_AHBCR));
+ VERBOSE("\n");
+
+ for (i = 0U; i < 4U; i++) {
+ VERBOSE("Flexspi: Register FSPI_FLSH_A1_CR2,(0x%x) = 0x%08x\n", FSPI_FLSHA1CR2 + i * 4, fspi_readl(FSPI_FLSHA1CR2 + i * 4));
+ }
+}
+#endif
+
+int fspi_init(uint32_t base_reg_addr, uint32_t flash_start_addr)
+{
+ uint32_t mcrx;
+ uint32_t flash_size;
+
+ if (fspi_base_reg_addr != 0U) {
+ INFO("FSPI is already initialized.\n");
+ return XSPI_SUCCESS;
+ }
+
+ fspi_base_reg_addr = base_reg_addr;
+ fspi_flash_base_addr = flash_start_addr;
+
+ INFO("Flexspi driver: Version v1.0\n");
+ INFO("Flexspi: Default MCR0 = 0x%08x, before reset\n", fspi_readl(FSPI_MCR0));
+ VERBOSE("Flexspi: Resetting controller...\n");
+
+ /* Reset FlexSpi Controller */
+ fspi_writel(FSPI_MCR0, FSPI_MCR0_SWRST);
+ while ((fspi_readl(FSPI_MCR0) & FSPI_MCR0_SWRST))
+ ; /* FSPI_MCR0_SWRESET_MASK */
+
+
+ /* Disable Controller Module before programming its registersi, especially MCR0 (Master Control Register0) */
+ fspi_MDIS(1);
+ /*
+ * Program MCR0 with default values, AHB Timeout(0xff), IP Timeout(0xff). {FSPI_MCR0- 0xFFFF0000}
+ */
+
+ /* Timeout wait cycle for AHB command grant */
+ mcrx = fspi_readl(FSPI_MCR0);
+ mcrx |= (uint32_t)((FSPI_MAX_TIMEOUT_AHBCMD << FSPI_MCR0_AHBGRANTWAIT_SHIFT) & (FSPI_MCR0_AHBGRANTWAIT_MASK));
+
+ /* Time out wait cycle for IP command grant*/
+ mcrx |= (uint32_t) (FSPI_MAX_TIMEOUT_IPCMD << FSPI_MCR0_IPGRANTWAIT_SHIFT) & (FSPI_MCR0_IPGRANTWAIT_MASK);
+
+ /* TODO why BE64 set BE32*/
+ mcrx |= (uint32_t) (FSPI_ENDCFG_LE64 << FSPI_MCR0_ENDCFG_SHIFT) & FSPI_MCR0_ENDCFG_MASK;
+
+ fspi_writel(FSPI_MCR0, mcrx);
+
+ /* Reset the DLL register to default value */
+ fspi_writel(FSPI_DLLACR, FSPI_DLLACR_OVRDEN);
+ fspi_writel(FSPI_DLLBCR, FSPI_DLLBCR_OVRDEN);
+
+#if ERRATA_FLASH_A050272 /* ERRATA DLL */
+ for (uint8_t delay = 100U; delay > 0U; delay--) {
+ __asm__ volatile ("nop");
+ }
+#endif
+
+ /* Configure flash control registers for different chip select */
+ flash_size = (F_FLASH_SIZE_BYTES * FLASH_NUM) / FSPI_BYTES_PER_KBYTES;
+ fspi_writel(FSPI_FLSHA1CR0, flash_size);
+ fspi_writel(FSPI_FLSHA2CR0, 0U);
+ fspi_writel(FSPI_FLSHB1CR0, 0U);
+ fspi_writel(FSPI_FLSHB2CR0, 0U);
+
+#if defined(CONFIG_FSPI_AHB)
+ fspi_init_ahb();
+#endif
+ /* RE-Enable Controller Module */
+ fspi_MDIS(0);
+ INFO("Flexspi: After MCR0 = 0x%08x,\n", fspi_readl(FSPI_MCR0));
+ fspi_setup_LUT();
+
+ /* Dump of all registers, ensure controller not disabled anymore*/
+#if defined(DEBUG_FLEXSPI)
+ fspi_dump_regs();
+#endif
+
+ INFO("Flexspi: Init done!!\n");
+
+#if DEBUG_FLEXSPI
+
+ uint32_t xspi_addr = SZ_57M;
+
+ /*
+ * Second argument of fspi_test is the size of buffer(s) passed
+ * to the function.
+ * SIZE_BUFFER defined in test_fspi.c is kept large enough to
+ * accommodate variety of sizes for regressive tests.
+ */
+ fspi_test(xspi_addr, 0x40, 0);
+ fspi_test(xspi_addr, 0x15, 2);
+ fspi_test(xspi_addr, 0x80, 0);
+ fspi_test(xspi_addr, 0x81, 0);
+ fspi_test(xspi_addr, 0x79, 3);
+
+ fspi_test(xspi_addr + 0x11, 0x15, 0);
+ fspi_test(xspi_addr + 0x11, 0x40, 0);
+ fspi_test(xspi_addr + 0xff, 0x40, 1);
+ fspi_test(xspi_addr + 0x25, 0x81, 2);
+ fspi_test(xspi_addr + 0xef, 0x6f, 3);
+
+ fspi_test((xspi_addr - F_SECTOR_ERASE_SZ), 0x229, 0);
+#endif
+
+ return XSPI_SUCCESS;
+}
diff --git a/drivers/nxp/flexspi/nor/fspi.h b/drivers/nxp/flexspi/nor/fspi.h
new file mode 100644
index 0000000..da2e269
--- /dev/null
+++ b/drivers/nxp/flexspi/nor/fspi.h
@@ -0,0 +1,385 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * FlexSpi Registers & Bits definition.
+ *
+ */
+
+#ifndef FSPI_H
+#define FSPI_H
+
+#ifndef __ASSEMBLER__
+#include <lib/mmio.h>
+
+#ifdef NXP_FSPI_BE
+#define fspi_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
+#define fspi_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
+#elif defined(NXP_FSPI_LE)
+#define fspi_in32(a) mmio_read_32((uintptr_t)(a))
+#define fspi_out32(a, v) mmio_write_32((uintptr_t)(a), v)
+#else
+#error Please define FSPI register endianness
+#endif
+
+#endif
+
+/* All LE so not swap needed */
+#define FSPI_IPDATA_SWAP 0U
+#define FSPI_AHBDATA_SWAP 0U
+
+#define CONFIG_FSPI_FASTREAD 1U
+
+#define FSPI_BYTES_PER_KBYTES 0x400U
+#define FLASH_NUM 1U
+
+#define FSPI_READ_SEQ_ID 0U
+#define FSPI_WREN_SEQ_ID 1U
+#define FSPI_WRITE_SEQ_ID 2U
+#define FSPI_SE_SEQ_ID 3U
+#define FSPI_RDSR_SEQ_ID 4U
+#define FSPI_BE_SEQ_ID 5U
+#define FSPI_FASTREAD_SEQ_ID 6U
+#define FSPI_4K_SEQ_ID 7U
+
+/*
+ * LUT register layout:
+ *
+ * ---------------------------------------------------
+ * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
+ * ---------------------------------------------------
+ *
+ * INSTR_SHIFT- 10, PAD_SHIFT - 8, OPRND_SHIFT -0
+ */
+#define FSPI_INSTR_OPRND0_SHIFT 0
+#define FSPI_INSTR_OPRND0(x) (x << FSPI_INSTR_OPRND0_SHIFT)
+#define FSPI_INSTR_PAD0_SHIFT 8
+#define FSPI_INSTR_PAD0(x) ((x) << FSPI_INSTR_PAD0_SHIFT)
+#define FSPI_INSTR_OPCODE0_SHIFT 10
+#define FSPI_INSTR_OPCODE0(x) ((x) << FSPI_INSTR_OPCODE0_SHIFT)
+#define FSPI_INSTR_OPRND1_SHIFT 16
+#define FSPI_INSTR_OPRND1(x) ((x) << FSPI_INSTR_OPRND1_SHIFT)
+#define FSPI_INSTR_PAD1_SHIFT 24
+#define FSPI_INSTR_PAD1(x) ((x) << FSPI_INSTR_PAD1_SHIFT)
+#define FSPI_INSTR_OPCODE1_SHIFT 26
+#define FSPI_INSTR_OPCODE1(x) ((x) << FSPI_INSTR_OPCODE1_SHIFT)
+
+/* Instruction set for the LUT register. */
+#define LUT_STOP 0x00
+#define LUT_CMD 0x01
+#define LUT_ADDR 0x02
+#define LUT_CADDR_SDR 0x03
+#define LUT_MODE 0x04
+#define LUT_MODE2 0x05
+#define LUT_MODE4 0x06
+#define LUT_MODE8 0x07
+#define LUT_NXP_WRITE 0x08
+#define LUT_NXP_READ 0x09
+
+#define LUT_LEARN_SDR 0x0A
+#define LUT_DATSZ_SDR 0x0B
+#define LUT_DUMMY 0x0C
+#define LUT_DUMMY_RWDS_SDR 0x0D
+#define LUT_JMP_ON_CS 0x1F
+#define LUT_CMD_DDR 0x21
+#define LUT_ADDR_DDR 0x22
+#define LUT_CADDR_DDR 0x23
+#define LUT_MODE_DDR 0x24
+#define LUT_MODE2_DDR 0x25
+#define LUT_MODE4_DDR 0x26
+#define LUT_MODE8_DDR 0x27
+#define LUT_WRITE_DDR 0x28
+#define LUT_READ_DDR 0x29
+#define LUT_LEARN_DDR 0x2A
+#define LUT_DATSZ_DDR 0x2B
+#define LUT_DUMMY_DDR 0x2C
+#define LUT_DUMMY_RWDS_DDR 0x2D
+
+#define FSPI_NOR_CMD_READ 0x03
+#define FSPI_NOR_CMD_READ_4B 0x13
+#define FSPI_NOR_CMD_FASTREAD 0x0b
+#define FSPI_NOR_CMD_FASTREAD_4B 0x0c
+#define FSPI_NOR_CMD_PP 0x02
+#define FSPI_NOR_CMD_PP_4B 0x12
+#define FSPI_NOR_CMD_WREN 0x06
+#define FSPI_NOR_CMD_SE_64K 0xd8
+#define FSPI_NOR_CMD_SE_64K_4B 0xdc
+#define FSPI_NOR_CMD_SE_4K 0x20
+#define FSPI_NOR_CMD_SE_4K_4B 0x21
+#define FSPI_NOR_CMD_BE 0x60
+#define FSPI_NOR_CMD_RDSR 0x05
+#define FSPI_NOR_CMD_WREN_STOP 0x04
+
+#define FSPI_LUT_STOP 0x00
+#define FSPI_LUT_CMD 0x01
+#define FSPI_LUT_ADDR 0x02
+
+#define FSPI_LUT_PAD1 0
+#define FSPI_LUT_PAD2 1
+#define FSPI_LUT_PAD4 2
+#define FSPI_LUT_PAD8 3
+
+#define FSPI_LUT_ADDR24BIT 0x18
+#define FSPI_LUT_ADDR32BIT 0x20
+
+#define FSPI_LUT_WRITE 0x08
+#define FSPI_LUT_READ 0x09
+#define FSPI_DUMMY_SDR 0x0c
+
+/* TODO Check size if functional*/
+#define FSPI_RX_IPBUF_SIZE 0x200 /* 64*64 bits */
+#define FSPI_TX_IPBUF_SIZE 0x400 /* 128*64 bits */
+
+#define FSPI_RX_MAX_AHBBUF_SIZE 0x800 /* 256 * 64bits */
+#define FSPI_TX_MAX_AHBBUF_SIZE 0x40 /* 8 * 64bits */
+
+#define FSPI_LUTREG_OFFSET 0x200ul
+
+#define FSPI_MAX_TIMEOUT_AHBCMD 0xFFU
+#define FSPI_MAX_TIMEOUT_IPCMD 0xFF
+#define FSPI_SER_CLK_DIV 0x04
+#define FSPI_HSEN 0
+#define FSPI_ENDCFG_BE64 0x01
+#define FSPI_ENDCFG_BE32 0x03
+#define FSPI_ENDCFG_LE32 0x02
+#define FSPI_ENDCFG_LE64 0x0
+
+#define MASK_24BIT_ADDRESS 0x00ffffff
+#define MASK_32BIT_ADDRESS 0xffffffff
+
+/* Registers used by the driver */
+#define FSPI_MCR0 0x0ul
+#define FSPI_MCR0_AHB_TIMEOUT(x) ((x) << 24)
+#define FSPI_MCR0_IP_TIMEOUT(x) ((x) << 16)
+#define FSPI_MCR0_LEARN_EN BIT(15)
+#define FSPI_MCR0_SCRFRUN_EN BIT(14)
+#define FSPI_MCR0_OCTCOMB_EN BIT(13)
+#define FSPI_MCR0_DOZE_EN BIT(12)
+#define FSPI_MCR0_HSEN BIT(11)
+#define FSPI_MCR0_SERCLKDIV BIT(8)
+#define FSPI_MCR0_ATDF_EN BIT(7)
+#define FSPI_MCR0_ARDF_EN BIT(6)
+#define FSPI_MCR0_RXCLKSRC(x) ((x) << 4)
+#define FSPI_MCR0_END_CFG(x) ((x) << 2)
+#define FSPI_MCR0_MDIS BIT(1)
+#define FSPI_MCR0_SWRST BIT(0)
+
+#define FSPI_MCR0_AHBGRANTWAIT_SHIFT 24
+#define FSPI_MCR0_AHBGRANTWAIT_MASK (0xFFU << FSPI_MCR0_AHBGRANTWAIT_SHIFT)
+#define FSPI_MCR0_IPGRANTWAIT_SHIFT 16
+#define FSPI_MCR0_IPGRANTWAIT_MASK (0xFF << FSPI_MCR0_IPGRANTWAIT_SHIFT)
+#define FSPI_MCR0_HSEN_SHIFT 11
+#define FSPI_MCR0_HSEN_MASK (1 << FSPI_MCR0_HSEN_SHIFT)
+#define FSPI_MCR0_SERCLKDIV_SHIFT 8
+#define FSPI_MCR0_SERCLKDIV_MASK (7 << FSPI_MCR0_SERCLKDIV_SHIFT)
+#define FSPI_MCR0_ENDCFG_SHIFT 2
+#define FSPI_MCR0_ENDCFG_MASK (3 << FSPI_MCR0_ENDCFG_SHIFT)
+#define FSPI_MCR0_RXCLKSRC_SHIFT 4
+#define FSPI_MCR0_RXCLKSRC_MASK (3 << FSPI_MCR0_RXCLKSRC_SHIFT)
+
+#define FSPI_MCR1 0x04
+#define FSPI_MCR1_SEQ_TIMEOUT(x) ((x) << 16)
+#define FSPI_MCR1_AHB_TIMEOUT(x) (x)
+
+#define FSPI_MCR2 0x08
+#define FSPI_MCR2_IDLE_WAIT(x) ((x) << 24)
+#define FSPI_MCR2_SAMEDEVICEEN BIT(15)
+#define FSPI_MCR2_CLRLRPHS BIT(14)
+#define FSPI_MCR2_ABRDATSZ BIT(8)
+#define FSPI_MCR2_ABRLEARN BIT(7)
+#define FSPI_MCR2_ABR_READ BIT(6)
+#define FSPI_MCR2_ABRWRITE BIT(5)
+#define FSPI_MCR2_ABRDUMMY BIT(4)
+#define FSPI_MCR2_ABR_MODE BIT(3)
+#define FSPI_MCR2_ABRCADDR BIT(2)
+#define FSPI_MCR2_ABRRADDR BIT(1)
+#define FSPI_MCR2_ABR_CMD BIT(0)
+
+#define FSPI_AHBCR 0x0c
+#define FSPI_AHBCR_RDADDROPT BIT(6)
+#define FSPI_AHBCR_PREF_EN BIT(5)
+#define FSPI_AHBCR_BUFF_EN BIT(4)
+#define FSPI_AHBCR_CACH_EN BIT(3)
+#define FSPI_AHBCR_CLRTXBUF BIT(2)
+#define FSPI_AHBCR_CLRRXBUF BIT(1)
+#define FSPI_AHBCR_PAR_EN BIT(0)
+
+#define FSPI_INTEN 0x10
+#define FSPI_INTEN_SCLKSBWR BIT(9)
+#define FSPI_INTEN_SCLKSBRD BIT(8)
+#define FSPI_INTEN_DATALRNFL BIT(7)
+#define FSPI_INTEN_IPTXWE BIT(6)
+#define FSPI_INTEN_IPRXWA BIT(5)
+#define FSPI_INTEN_AHBCMDERR BIT(4)
+#define FSPI_INTEN_IPCMDERR BIT(3)
+#define FSPI_INTEN_AHBCMDGE BIT(2)
+#define FSPI_INTEN_IPCMDGE BIT(1)
+#define FSPI_INTEN_IPCMDDONE BIT(0)
+
+#define FSPI_INTR 0x14
+#define FSPI_INTR_SCLKSBWR BIT(9)
+#define FSPI_INTR_SCLKSBRD BIT(8)
+#define FSPI_INTR_DATALRNFL BIT(7)
+#define FSPI_INTR_IPTXWE BIT(6)
+#define FSPI_INTR_IPRXWA BIT(5)
+#define FSPI_INTR_AHBCMDERR BIT(4)
+#define FSPI_INTR_IPCMDERR BIT(3)
+#define FSPI_INTR_AHBCMDGE BIT(2)
+#define FSPI_INTR_IPCMDGE BIT(1)
+#define FSPI_INTR_IPCMDDONE BIT(0)
+
+#define FSPI_LUTKEY 0x18
+#define FSPI_LUTKEY_VALUE 0x5AF05AF0
+
+#define FSPI_LCKCR 0x1C
+
+#define FSPI_LCKER_LOCK 0x1
+#define FSPI_LCKER_UNLOCK 0x2
+
+#define FSPI_BUFXCR_INVALID_MSTRID 0xE
+#define FSPI_AHBRX_BUF0CR0 0x20
+#define FSPI_AHBRX_BUF1CR0 0x24
+#define FSPI_AHBRX_BUF2CR0 0x28
+#define FSPI_AHBRX_BUF3CR0 0x2C
+#define FSPI_AHBRX_BUF4CR0 0x30
+#define FSPI_AHBRX_BUF5CR0 0x34
+#define FSPI_AHBRX_BUF6CR0 0x38
+#define FSPI_AHBRX_BUF7CR0 0x3C
+
+#define FSPI_AHBRXBUF0CR7_PREF BIT(31)
+
+#define FSPI_AHBRX_BUF0CR1 0x40
+#define FSPI_AHBRX_BUF1CR1 0x44
+#define FSPI_AHBRX_BUF2CR1 0x48
+#define FSPI_AHBRX_BUF3CR1 0x4C
+#define FSPI_AHBRX_BUF4CR1 0x50
+#define FSPI_AHBRX_BUF5CR1 0x54
+#define FSPI_AHBRX_BUF6CR1 0x58
+#define FSPI_AHBRX_BUF7CR1 0x5C
+
+#define FSPI_FLSHA1CR0 0x60
+#define FSPI_FLSHA2CR0 0x64
+#define FSPI_FLSHB1CR0 0x68
+#define FSPI_FLSHB2CR0 0x6C
+#define FSPI_FLSHXCR0_SZ_KB 10
+#define FSPI_FLSHXCR0_SZ(x) ((x) >> FSPI_FLSHXCR0_SZ_KB)
+
+#define FSPI_FLSHA1CR1 0x70
+#define FSPI_FLSHA2CR1 0x74
+#define FSPI_FLSHB1CR1 0x78
+#define FSPI_FLSHB2CR1 0x7C
+#define FSPI_FLSHXCR1_CSINTR(x) ((x) << 16)
+#define FSPI_FLSHXCR1_CAS(x) ((x) << 11)
+#define FSPI_FLSHXCR1_WA BIT(10)
+#define FSPI_FLSHXCR1_TCSH(x) ((x) << 5)
+#define FSPI_FLSHXCR1_TCSS(x) (x)
+
+#define FSPI_FLSHXCR1_TCSH_SHIFT 5
+#define FSPI_FLSHXCR1_TCSH_MASK (0x1F << FSPI_FLSHXCR1_TCSH_SHIFT)
+#define FSPI_FLSHXCR1_TCSS_SHIFT 0
+#define FSPI_FLSHXCR1_TCSS_MASK (0x1F << FSPI_FLSHXCR1_TCSS_SHIFT)
+
+#define FSPI_FLSHA1CR2 0x80
+#define FSPI_FLSHA2CR2 0x84
+#define FSPI_FLSHB1CR2 0x88
+#define FSPI_FLSHB2CR2 0x8C
+#define FSPI_FLSHXCR2_CLRINSP BIT(24)
+#define FSPI_FLSHXCR2_AWRWAIT BIT(16)
+#define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13
+#define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8
+#define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5
+#define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0
+
+#define FSPI_IPCR0 0xA0
+
+#define FSPI_IPCR1 0xA4
+#define FSPI_IPCR1_IPAREN BIT(31)
+#define FSPI_IPCR1_SEQNUM_SHIFT 24
+#define FSPI_IPCR1_SEQID_SHIFT 16
+#define FSPI_IPCR1_IDATSZ(x) (x)
+
+#define FSPI_IPCMD 0xB0
+#define FSPI_IPCMD_TRG BIT(0)
+
+
+/* IP Command Register */
+#define FSPI_IPCMD_TRG_SHIFT 0
+#define FSPI_IPCMD_TRG_MASK (1 << FSPI_IPCMD_TRG_SHIFT)
+
+#define FSPI_INTR_IPRXWA_SHIFT 5
+#define FSPI_INTR_IPRXWA_MASK (1 << FSPI_INTR_IPRXWA_SHIFT)
+
+#define FSPI_INTR_IPCMDDONE_SHIFT 0
+#define FSPI_INTR_IPCMDDONE_MASK (1 << FSPI_INTR_IPCMDDONE_SHIFT)
+
+#define FSPI_INTR_IPTXWE_SHIFT 6
+#define FSPI_INTR_IPTXWE_MASK (1 << FSPI_INTR_IPTXWE_SHIFT)
+
+#define FSPI_IPTXFSTS_FILL_SHIFT 0
+#define FSPI_IPTXFSTS_FILL_MASK (0xFF << FSPI_IPTXFSTS_FILL_SHIFT)
+
+#define FSPI_IPCR1_ISEQID_SHIFT 16
+#define FSPI_IPCR1_ISEQID_MASK (0x1F << FSPI_IPCR1_ISEQID_SHIFT)
+
+#define FSPI_IPRXFSTS_FILL_SHIFT 0
+#define FSPI_IPRXFSTS_FILL_MASK (0xFF << FSPI_IPRXFSTS_FILL_SHIFT)
+
+#define FSPI_DLPR 0xB4
+
+#define FSPI_IPRXFCR 0xB8
+#define FSPI_IPRXFCR_CLR BIT(0)
+#define FSPI_IPRXFCR_DMA_EN BIT(1)
+#define FSPI_IPRXFCR_WMRK(x) ((x) << 2)
+
+#define FSPI_IPTXFCR 0xBC
+#define FSPI_IPTXFCR_CLR BIT(0)
+#define FSPI_IPTXFCR_DMA_EN BIT(1)
+#define FSPI_IPTXFCR_WMRK(x) ((x) << 2)
+
+#define FSPI_DLLACR 0xC0
+#define FSPI_DLLACR_OVRDEN BIT(8)
+
+#define FSPI_DLLBCR 0xC4
+#define FSPI_DLLBCR_OVRDEN BIT(8)
+
+#define FSPI_STS0 0xE0
+#define FSPI_STS0_DLPHB(x) ((x) << 8)
+#define FSPI_STS0_DLPHA(x) ((x) << 4)
+#define FSPI_STS0_CMD_SRC(x) ((x) << 2)
+#define FSPI_STS0_ARB_IDLE BIT(1)
+#define FSPI_STS0_SEQ_IDLE BIT(0)
+
+#define FSPI_STS1 0xE4
+#define FSPI_STS1_IP_ERRCD(x) ((x) << 24)
+#define FSPI_STS1_IP_ERRID(x) ((x) << 16)
+#define FSPI_STS1_AHB_ERRCD(x) ((x) << 8)
+#define FSPI_STS1_AHB_ERRID(x) (x)
+
+#define FSPI_AHBSPNST 0xEC
+#define FSPI_AHBSPNST_DATLFT(x) ((x) << 16)
+#define FSPI_AHBSPNST_BUFID(x) ((x) << 1)
+#define FSPI_AHBSPNST_ACTIVE BIT(0)
+
+#define FSPI_IPRXFSTS 0xF0
+#define FSPI_IPRXFSTS_RDCNTR(x) ((x) << 16)
+#define FSPI_IPRXFSTS_FILL(x) (x)
+
+#define FSPI_IPTXFSTS 0xF4
+#define FSPI_IPTXFSTS_WRCNTR(x) ((x) << 16)
+#define FSPI_IPTXFSTS_FILL(x) (x)
+
+#define FSPI_NOR_SR_WIP_SHIFT (0)
+#define FSPI_NOR_SR_WIP_MASK (1 << FSPI_NOR_SR_WIP_SHIFT)
+
+#define FSPI_RFDR 0x100
+#define FSPI_TFDR 0x180
+
+#define FSPI_LUT_BASE 0x200
+#define FSPI_LUT_OFFSET (SEQID_LUT * 4 * 4)
+#define FSPI_LUT_REG(idx) \
+ (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4)
+
+/* register map end */
+
+#endif
diff --git a/drivers/nxp/flexspi/nor/test_fspi.c b/drivers/nxp/flexspi/nor/test_fspi.c
new file mode 100644
index 0000000..c36c5b8
--- /dev/null
+++ b/drivers/nxp/flexspi/nor/test_fspi.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+
+#include <common/debug.h>
+#include <flash_info.h>
+#include "fspi.h"
+#include <fspi_api.h>
+
+/*
+ * The macros are defined to be used as test vector for testing fspi.
+ */
+#define SIZE_BUFFER 0x250
+
+/*
+ * You may choose fspi_swap based on core endianness and flexspi IP/AHB
+ * buffer endianness set in MCR.
+ */
+#define fspi_swap32(A) (A)
+
+void fspi_test(uint32_t fspi_test_addr, uint32_t size, int extra)
+{
+ uint32_t buffer[SIZE_BUFFER];
+ uint32_t count = 1;
+ uint32_t failed, i;
+
+ NOTICE("-------------------------- %d----------------------------------\n", count++);
+ INFO("Sector Erase size: 0x%08x, size: %d\n", F_SECTOR_ERASE_SZ, size);
+ /* Test Sector Erase */
+ xspi_sector_erase(fspi_test_addr - fspi_test_addr % F_SECTOR_ERASE_SZ,
+ F_SECTOR_ERASE_SZ);
+
+ /* Test Erased data using IP read */
+ xspi_ip_read((fspi_test_addr), buffer, size * 4);
+
+ failed = 0;
+ for (i = 0; i < size; i++)
+ if (fspi_swap32(0xffffffff) != buffer[i]) {
+ failed = 1;
+ break;
+ }
+
+ if (failed == 0) {
+ NOTICE("[%d]: Success Erase: data in buffer[%d] 0x%08x\n", __LINE__, i-3, buffer[i-3]);
+ } else {
+ ERROR("Erase: Failed -->xxx with buffer[%d]=0x%08x\n", i, buffer[i]);
+ }
+
+ for (i = 0; i < SIZE_BUFFER; i++)
+ buffer[i] = 0x12345678;
+
+ /* Write data from buffer to flash */
+ xspi_write(fspi_test_addr, (void *)buffer, (size * 4 + extra));
+ /* Check written data using IP read */
+ xspi_ip_read(fspi_test_addr, buffer, (size * 4 + extra));
+ failed = 0;
+ for (i = 0; i < size; i++)
+ if (fspi_swap32(0x12345678) != buffer[i]) {
+ failed = 1;
+ break;
+ }
+
+ if (failed == 0) {
+ NOTICE("[%d]: Success IpWrite with IP READ in buffer[%d] 0x%08x\n", __LINE__, i-3, buffer[i-3]);
+ } else {
+ ERROR("Write: Failed -->xxxx with IP READ in buffer[%d]=0x%08x\n", i, buffer[i]);
+ return;
+ }
+
+ /* xspi_read may use AHB read */
+ xspi_read((fspi_test_addr), buffer, (size * 4 + extra));
+ failed = 0;
+ for (i = 0; i < size; i++)
+ if (fspi_swap32(0x12345678) != buffer[i]) {
+ failed = 1;
+ break;
+ }
+
+ if (failed == 0) {
+ NOTICE("[%d]: Success IpWrite with AHB OR IP READ on buffer[%d] 0x%08x\n", __LINE__, i-3, buffer[i-3]);
+ } else {
+ ERROR("Write: Failed -->xxxx with AHB READ on buffer[%d]=0x%08x\n", i, buffer[i]);
+ return;
+ }
+}
diff --git a/drivers/nxp/gic/gic.mk b/drivers/nxp/gic/gic.mk
new file mode 100644
index 0000000..d75e071
--- /dev/null
+++ b/drivers/nxp/gic/gic.mk
@@ -0,0 +1,46 @@
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+#------------------------------------------------------------------------------
+#
+# Select the GIC files
+#
+# -----------------------------------------------------------------------------
+
+ifeq (${ADD_GIC},)
+ADD_GIC := 1
+ifeq ($(GIC), GIC400)
+include drivers/arm/gic/v2/gicv2.mk
+GIC_SOURCES += ${GICV2_SOURCES}
+GIC_SOURCES += ${PLAT_DRIVERS_PATH}/gic/ls_gicv2.c \
+ plat/common/plat_gicv2.c
+
+PLAT_INCLUDES += -I${PLAT_DRIVERS_INCLUDE_PATH}/gic/gicv2
+else
+ifeq ($(GIC), GIC500)
+include drivers/arm/gic/v3/gicv3.mk
+GIC_SOURCES += ${GICV3_SOURCES}
+GIC_SOURCES += ${PLAT_DRIVERS_PATH}/gic/ls_gicv3.c \
+ plat/common/plat_gicv3.c
+
+PLAT_INCLUDES += -I${PLAT_DRIVERS_INCLUDE_PATH}/gic/gicv3
+else
+ $(error -> GIC type not set!)
+endif
+endif
+
+ifeq (${BL_COMM_GIC_NEEDED},yes)
+BL_COMMON_SOURCES += ${GIC_SOURCES}
+else
+ifeq (${BL2_GIC_NEEDED},yes)
+BL2_SOURCES += ${GIC_SOURCES}
+endif
+ifeq (${BL31_GIC_NEEDED},yes)
+BL31_SOURCES += ${GIC_SOURCES}
+endif
+endif
+endif
+
+# -----------------------------------------------------------------------------
diff --git a/drivers/nxp/gic/ls_gicv2.c b/drivers/nxp/gic/ls_gicv2.c
new file mode 100644
index 0000000..62bc8db
--- /dev/null
+++ b/drivers/nxp/gic/ls_gicv2.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <gicv2.h>
+#include <plat_gic.h>
+
+
+/*
+ * NXP common helper to initialize the GICv3 only driver.
+ */
+void plat_ls_gic_driver_init(uintptr_t nxp_gicd_addr,
+ uintptr_t nxp_gicc_addr,
+ uint8_t plat_core_count,
+ interrupt_prop_t *ls_interrupt_props,
+ uint8_t ls_interrupt_prop_count,
+ uint32_t *target_mask_array)
+{
+ static struct gicv2_driver_data ls_gic_data;
+
+ ls_gic_data.gicd_base = nxp_gicd_addr;
+ ls_gic_data.gicc_base = nxp_gicc_addr;
+ ls_gic_data.target_masks = target_mask_array;
+ ls_gic_data.target_masks_num = plat_core_count;
+ ls_gic_data.interrupt_props = ls_interrupt_props;
+ ls_gic_data.interrupt_props_num = ls_interrupt_prop_count;
+
+ gicv2_driver_init(&ls_gic_data);
+}
+
+void plat_ls_gic_init(void)
+{
+ gicv2_distif_init();
+ gicv2_pcpu_distif_init();
+ gicv2_cpuif_enable();
+}
+
+/******************************************************************************
+ * ARM common helper to enable the GICv2 CPU interface
+ *****************************************************************************/
+void plat_ls_gic_cpuif_enable(void)
+{
+ gicv2_cpuif_enable();
+}
+
+/******************************************************************************
+ * ARM common helper to disable the GICv2 CPU interface
+ *****************************************************************************/
+void plat_ls_gic_cpuif_disable(void)
+{
+ gicv2_cpuif_disable();
+}
+
+/******************************************************************************
+ * NXP common helper to initialize GICv2 per cpu
+ *****************************************************************************/
+void plat_gic_pcpu_init(void)
+{
+ gicv2_pcpu_distif_init();
+ gicv2_cpuif_enable();
+}
+
+/******************************************************************************
+ * Stubs for Redistributor power management. Although GICv2 doesn't have
+ * Redistributor interface, these are provided for the sake of uniform GIC API
+ *****************************************************************************/
+void plat_ls_gic_redistif_on(void)
+{
+}
+
+void plat_ls_gic_redistif_off(void)
+{
+}
diff --git a/drivers/nxp/gic/ls_gicv3.c b/drivers/nxp/gic/ls_gicv3.c
new file mode 100644
index 0000000..9c02bd6
--- /dev/null
+++ b/drivers/nxp/gic/ls_gicv3.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <drivers/arm/gicv3.h>
+#include <plat_gic.h>
+#include <plat/common/platform.h>
+
+/*
+ * NXP common helper to initialize the GICv3 only driver.
+ */
+void plat_ls_gic_driver_init(uintptr_t nxp_gicd_addr,
+ uintptr_t nxp_gicr_addr,
+ uint8_t plat_core_count,
+ interrupt_prop_t *ls_interrupt_props,
+ uint8_t ls_interrupt_prop_count,
+ uintptr_t *target_mask_array,
+ mpidr_hash_fn mpidr_to_core_pos)
+{
+ static struct gicv3_driver_data ls_gic_data;
+
+ ls_gic_data.gicd_base = nxp_gicd_addr;
+ ls_gic_data.gicr_base = nxp_gicr_addr;
+ ls_gic_data.interrupt_props = ls_interrupt_props;
+ ls_gic_data.interrupt_props_num = ls_interrupt_prop_count;
+ ls_gic_data.rdistif_num = plat_core_count;
+ ls_gic_data.rdistif_base_addrs = target_mask_array;
+ ls_gic_data.mpidr_to_core_pos = mpidr_to_core_pos;
+
+ gicv3_driver_init(&ls_gic_data);
+}
+
+void plat_ls_gic_init(void)
+{
+ gicv3_distif_init();
+ gicv3_rdistif_init(plat_my_core_pos());
+ gicv3_cpuif_enable(plat_my_core_pos());
+}
+
+/*
+ * NXP common helper to enable the GICv3 CPU interface
+ */
+void plat_ls_gic_cpuif_enable(void)
+{
+ gicv3_cpuif_enable(plat_my_core_pos());
+}
+
+/*
+ * NXP common helper to disable the GICv3 CPU interface
+ */
+void plat_ls_gic_cpuif_disable(void)
+{
+ gicv3_cpuif_disable(plat_my_core_pos());
+}
+
+/*
+ * NXP common helper to initialize the per cpu distributor interface in GICv3
+ */
+void plat_gic_pcpu_init(void)
+{
+ gicv3_rdistif_init(plat_my_core_pos());
+ gicv3_cpuif_enable(plat_my_core_pos());
+}
+
+/*
+ * Stubs for Redistributor power management. Although GICv3 doesn't have
+ * Redistributor interface, these are provided for the sake of uniform GIC API
+ */
+void plat_ls_gic_redistif_on(void)
+{
+}
+
+void plat_ls_gic_redistif_off(void)
+{
+}
diff --git a/drivers/nxp/gpio/gpio.mk b/drivers/nxp/gpio/gpio.mk
new file mode 100644
index 0000000..74f0dc4
--- /dev/null
+++ b/drivers/nxp/gpio/gpio.mk
@@ -0,0 +1,28 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-----------------------------------------------------------------------------
+
+ifeq (${GPIO_ADDED},)
+
+GPIO_ADDED := 1
+
+PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLUDE_PATH)/gpio
+
+GPIO_SOURCES := $(PLAT_DRIVERS_PATH)/gpio/nxp_gpio.c
+
+ifeq (${BL_COMM_GPIO_NEEDED},yes)
+BL_COMMON_SOURCES += ${GPIO_SOURCES}
+else
+ifeq (${BL2_GPIO_NEEDED},yes)
+BL2_SOURCES += ${GPIO_SOURCES}
+endif
+ifeq (${BL31_GPIO_NEEDED},yes)
+BL31_SOURCES += ${GPIO_SOURCES}
+endif
+endif
+
+endif
+#------------------------------------------------
diff --git a/drivers/nxp/gpio/nxp_gpio.c b/drivers/nxp/gpio/nxp_gpio.c
new file mode 100644
index 0000000..28c9db9
--- /dev/null
+++ b/drivers/nxp/gpio/nxp_gpio.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <nxp_gpio.h>
+
+static gpio_init_info_t *gpio_init_info;
+
+void gpio_init(gpio_init_info_t *gpio_init_data)
+{
+ gpio_init_info = gpio_init_data;
+}
+
+/* This function set GPIO pin for raising POVDD. */
+int set_gpio_bit(uint32_t *gpio_base_addr,
+ uint32_t bit_num)
+{
+ uint32_t val = 0U;
+ uint32_t *gpdir = NULL;
+ uint32_t *gpdat = NULL;
+
+ if (gpio_init_info == NULL) {
+ ERROR("GPIO is not initialized.\n");
+ return GPIO_FAILURE;
+ }
+
+ gpdir = gpio_base_addr + GPDIR_REG_OFFSET;
+ gpdat = gpio_base_addr + (GPDAT_REG_OFFSET >> 2);
+
+ /*
+ * Set the corresponding bit in direction register
+ * to configure the GPIO as output.
+ */
+ val = gpio_read32(gpdir);
+ val = val | bit_num;
+ gpio_write32(gpdir, val);
+
+ /* Set the corresponding bit in GPIO data register */
+ val = gpio_read32(gpdat);
+ val = val | bit_num;
+ gpio_write32(gpdat, val);
+
+ val = gpio_read32(gpdat);
+
+ if ((val & bit_num) == 0U) {
+ return GPIO_FAILURE;
+ }
+
+ return GPIO_SUCCESS;
+}
+
+/* This function reset GPIO pin set for raising POVDD. */
+int clr_gpio_bit(uint32_t *gpio_base_addr, uint32_t bit_num)
+{
+ uint32_t val = 0U;
+ uint32_t *gpdir = NULL;
+ uint32_t *gpdat = NULL;
+
+
+ if (gpio_init_info == NULL) {
+ ERROR("GPIO is not initialized.\n");
+ return GPIO_FAILURE;
+ }
+
+ gpdir = gpio_base_addr + GPDIR_REG_OFFSET;
+ gpdat = gpio_base_addr + GPDAT_REG_OFFSET;
+
+ /*
+ * Reset the corresponding bit in direction and data register
+ * to configure the GPIO as input.
+ */
+ val = gpio_read32(gpdat);
+ val = val & ~(bit_num);
+ gpio_write32(gpdat, val);
+
+ val = gpio_read32(gpdat);
+
+ val = gpio_read32(gpdir);
+ val = val & ~(bit_num);
+ gpio_write32(gpdir, val);
+
+ val = gpio_read32(gpdat);
+
+ if ((val & bit_num) != 0U) {
+ return GPIO_FAILURE;
+ }
+
+ return GPIO_SUCCESS;
+}
+
+uint32_t *select_gpio_n_bitnum(uint32_t povdd_gpio, uint32_t *bit_num)
+{
+ uint32_t *ret_gpio;
+ uint32_t povdd_gpio_val = 0U;
+ uint32_t gpio_num = 0U;
+
+ if (gpio_init_info == NULL) {
+ ERROR("GPIO is not initialized.\n");
+ }
+ /*
+ * Subtract 1 from fuse_hdr povdd_gpio value as
+ * for 0x1 value, bit 0 is to be set
+ * for 0x20 value i.e 32, bit 31 i.e. 0x1f is to be set.
+ * 0x1f - 0x00 : GPIO_1
+ * 0x3f - 0x20 : GPIO_2
+ * 0x5f - 0x40 : GPIO_3
+ * 0x7f - 0x60 : GPIO_4
+ */
+ povdd_gpio_val = (povdd_gpio - 1U) & GPIO_SEL_MASK;
+
+ /* Right shift by 5 to divide by 32 */
+ gpio_num = povdd_gpio_val >> GPIO_ID_BASE_ADDR_SHIFT;
+ *bit_num = 1U << (GPIO_BITS_PER_BASE_REG
+ - (povdd_gpio_val & GPIO_BIT_MASK)
+ - 1U);
+
+ switch (gpio_num) {
+ case GPIO_0:
+ ret_gpio = (uint32_t *) gpio_init_info->gpio1_base_addr;
+ break;
+ case GPIO_1:
+ ret_gpio = (uint32_t *) gpio_init_info->gpio2_base_addr;
+ break;
+ case GPIO_2:
+ ret_gpio = (uint32_t *) gpio_init_info->gpio3_base_addr;
+ break;
+ case GPIO_3:
+ ret_gpio = (uint32_t *) gpio_init_info->gpio4_base_addr;
+ break;
+ default:
+ ret_gpio = NULL;
+ }
+
+ if (ret_gpio == NULL) {
+ INFO("GPIO_NUM = %d doesn't exist.\n", gpio_num);
+ }
+
+ return ret_gpio;
+}
diff --git a/drivers/nxp/i2c/i2c.c b/drivers/nxp/i2c/i2c.c
new file mode 100644
index 0000000..9281409
--- /dev/null
+++ b/drivers/nxp/i2c/i2c.c
@@ -0,0 +1,257 @@
+/*
+ * Copyright 2016-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <errno.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include "i2c.h"
+#include <nxp_timer.h>
+
+static uintptr_t g_nxp_i2c_addr;
+
+void i2c_init(uintptr_t nxp_i2c_addr)
+{
+ struct ls_i2c *ccsr_i2c = (void *)nxp_i2c_addr;
+
+ g_nxp_i2c_addr = nxp_i2c_addr;
+ /* Presume workaround for erratum a009203 applied */
+ i2c_out(&ccsr_i2c->cr, I2C_CR_DIS);
+ i2c_out(&ccsr_i2c->fd, I2C_FD_CONSERV);
+ i2c_out(&ccsr_i2c->sr, I2C_SR_RST);
+ i2c_out(&ccsr_i2c->cr, I2C_CR_EN);
+}
+
+static int wait_for_state(struct ls_i2c *ccsr_i2c,
+ unsigned char state, unsigned char mask)
+{
+ unsigned char sr;
+ uint64_t start_time = get_timer_val(0);
+ uint64_t timer;
+
+ do {
+ sr = i2c_in(&ccsr_i2c->sr);
+ if (sr & I2C_SR_AL) {
+ i2c_out(&ccsr_i2c->sr, sr);
+ WARN("I2C arbitration lost\n");
+ return -EIO;
+ }
+ if ((sr & mask) == state) {
+ return (int)sr;
+ }
+
+ timer = get_timer_val(start_time);
+ if (timer > I2C_TIMEOUT)
+ break;
+ mdelay(1);
+ } while (1);
+ WARN("I2C: Timeout waiting for state 0x%x, sr = 0x%x\n", state, sr);
+
+ return -ETIMEDOUT;
+}
+
+static int tx_byte(struct ls_i2c *ccsr_i2c, unsigned char c)
+{
+ int ret;
+
+ i2c_out(&ccsr_i2c->sr, I2C_SR_IF);
+ i2c_out(&ccsr_i2c->dr, c);
+ ret = wait_for_state(ccsr_i2c, I2C_SR_IF, I2C_SR_IF);
+ if (ret < 0) {
+ WARN("%s: state error\n", __func__);
+ return ret;
+ }
+ if (ret & I2C_SR_RX_NAK) {
+ WARN("%s: nodev\n", __func__);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int gen_stop(struct ls_i2c *ccsr_i2c)
+{
+ unsigned char cr;
+ int ret;
+
+ cr = i2c_in(&ccsr_i2c->cr);
+ cr &= ~(I2C_CR_MA | I2C_CR_TX);
+ i2c_out(&ccsr_i2c->cr, cr);
+ ret = wait_for_state(ccsr_i2c, I2C_SR_IDLE, I2C_SR_BB);
+ if (ret < 0) {
+ WARN("I2C: Generating stop failed.\n");
+ }
+ return ret;
+}
+
+static int i2c_write_addr(struct ls_i2c *ccsr_i2c, unsigned char chip,
+ int addr, int alen)
+{
+ int ret;
+ unsigned char cr;
+
+ if (alen != 1) {
+ WARN("I2C: Unsupported address len [%d]\n", alen);
+ return -EIO;
+ }
+
+ if (i2c_in(&ccsr_i2c->ad) == (chip << 1)) {
+ WARN("I2C: slave address same as self\n");
+ return -ENODEV;
+ }
+ i2c_out(&ccsr_i2c->sr, I2C_SR_IF);
+ ret = wait_for_state(ccsr_i2c, I2C_SR_IDLE, I2C_SR_BB);
+ if (ret < 0) {
+ return ret;
+ }
+
+ cr = i2c_in(&ccsr_i2c->cr);
+ cr |= I2C_CR_MA;
+ i2c_out(&ccsr_i2c->cr, cr);
+ ret = wait_for_state(ccsr_i2c, I2C_SR_BB, I2C_SR_BB);
+ if (ret < 0) {
+ return ret;
+ }
+
+ VERBOSE("Before writing chip %d\n", chip);
+ cr |= I2C_CR_TX | I2C_CR_TX_NAK;
+ i2c_out(&ccsr_i2c->cr, cr);
+ ret = tx_byte(ccsr_i2c, chip << 1);
+ if (ret < 0) {
+ gen_stop(ccsr_i2c);
+ return ret;
+ }
+
+ VERBOSE("Before writing addr\n");
+ while (alen--) {
+ ret = tx_byte(ccsr_i2c, (addr >> (alen << 3)) & 0xff);
+ if (ret < 0) {
+ gen_stop(ccsr_i2c);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int read_data(struct ls_i2c *ccsr_i2c, unsigned char chip,
+ unsigned char *buf, int len)
+{
+ int i;
+ int ret;
+ unsigned char cr;
+
+ cr = i2c_in(&ccsr_i2c->cr);
+ cr &= ~(I2C_CR_TX | I2C_CR_TX_NAK);
+ if (len == 1) {
+ cr |= I2C_CR_TX_NAK;
+ }
+ i2c_out(&ccsr_i2c->cr, cr);
+ i2c_out(&ccsr_i2c->sr, I2C_SR_IF);
+ i2c_in(&ccsr_i2c->dr); /* dummy read */
+ for (i = 0; i < len; i++) {
+ ret = wait_for_state(ccsr_i2c, I2C_SR_IF, I2C_SR_IF);
+ if (ret < 0) {
+ gen_stop(ccsr_i2c);
+ return ret;
+ }
+ if (i == (len - 1)) {
+ gen_stop(ccsr_i2c);
+ } else if (i == (len - 2)) {
+ /* Updating the command to send
+ * No ACK.
+ */
+ cr = i2c_in(&ccsr_i2c->cr);
+ cr |= I2C_CR_TX_NAK;
+ i2c_out(&ccsr_i2c->cr, cr);
+ }
+ i2c_out(&ccsr_i2c->sr, I2C_SR_IF);
+ buf[i] = i2c_in(&ccsr_i2c->dr);
+ }
+
+ return 0;
+}
+
+static int write_data(struct ls_i2c *ccsr_i2c, unsigned char chip,
+ const unsigned char *buf, int len)
+{
+ int i;
+ int ret;
+
+ for (i = 0; i < len; i++) {
+ ret = tx_byte(ccsr_i2c, buf[i]);
+ if (ret < 0) {
+ break;
+ }
+ }
+ ret = gen_stop(ccsr_i2c);
+
+ return ret;
+}
+
+
+int i2c_read(unsigned char chip, int addr, int alen,
+ unsigned char *buf, int len)
+{
+ int ret;
+ unsigned char cr;
+ struct ls_i2c *ccsr_i2c = (void *)g_nxp_i2c_addr;
+
+ ret = i2c_write_addr(ccsr_i2c, chip, addr, alen);
+ if (ret < 0) {
+ gen_stop(ccsr_i2c);
+ return ret;
+ }
+
+ cr = i2c_in(&ccsr_i2c->cr);
+ cr |= I2C_CR_RSTA;
+ i2c_out(&ccsr_i2c->cr, cr);
+
+ ret = tx_byte(ccsr_i2c, (chip << 1) | 1);
+ if (ret < 0) {
+ gen_stop(ccsr_i2c);
+ return ret;
+ }
+
+ return read_data(ccsr_i2c, chip, buf, len);
+}
+
+int i2c_write(unsigned char chip, int addr, int alen,
+ const unsigned char *buf, int len)
+{
+ int ret;
+ struct ls_i2c *ccsr_i2c = (void *)g_nxp_i2c_addr;
+
+ ret = i2c_write_addr(ccsr_i2c, chip, addr, alen);
+ if (ret < 0) {
+ return ret;
+ }
+
+ return write_data(ccsr_i2c, chip, buf, len);
+}
+
+int i2c_probe_chip(unsigned char chip)
+{
+ int ret;
+ struct ls_i2c *ccsr_i2c = (void *)g_nxp_i2c_addr;
+
+ ret = i2c_write_addr(ccsr_i2c, chip, 0, 0);
+ if (ret < 0) {
+ WARN("write addr failed\n");
+ return ret;
+ }
+
+ ret = gen_stop(ccsr_i2c);
+ if (ret < 0) {
+ WARN("I2C: Probe not complete.\n");
+ }
+
+ return ret;
+}
diff --git a/drivers/nxp/i2c/i2c.mk b/drivers/nxp/i2c/i2c.mk
new file mode 100644
index 0000000..716e14a
--- /dev/null
+++ b/drivers/nxp/i2c/i2c.mk
@@ -0,0 +1,25 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${ADD_I2C},)
+
+ADD_I2C := 1
+
+I2C_SOURCES += $(PLAT_DRIVERS_PATH)/i2c/i2c.c
+
+PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLUDE_PATH)/i2c
+
+ifeq (${BL_COMM_I2C_NEEDED},yes)
+BL_COMMON_SOURCES += ${I2C_SOURCES}
+else
+ifeq (${BL2_I2C_NEEDED},yes)
+BL2_SOURCES += ${I2C_SOURCES}
+endif
+ifeq (${BL31_I2C_NEEDED},yes)
+BL31_SOURCES += ${I2C_SOURCES}
+endif
+endif
+endif
diff --git a/drivers/nxp/interconnect/interconnect.mk b/drivers/nxp/interconnect/interconnect.mk
new file mode 100644
index 0000000..aa51be4
--- /dev/null
+++ b/drivers/nxp/interconnect/interconnect.mk
@@ -0,0 +1,44 @@
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+#------------------------------------------------------------------------------
+#
+# Select the Interconnect files
+#
+# -----------------------------------------------------------------------------
+
+ifeq (${ADD_INTERCONNECT},)
+
+ADD_INTERCONNECT := 1
+PLAT_INCLUDES += -I${PLAT_DRIVERS_INCLUDE_PATH}/interconnect
+
+ifeq (, $(filter $(INTERCONNECT), CCI400 CCN502 CCN504 CCN508))
+ $(error -> Interconnect type not set!)
+else
+$(eval $(call add_define_val,INTERCONNECT,${INTERCONNECT}))
+ifeq ($(INTERCONNECT), $(filter $(INTERCONNECT), CCN502 CCN504 CCN508))
+INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \
+ ${PLAT_DRIVERS_PATH}/interconnect/ls_ccn.c
+else
+ifeq ($(INTERCONNECT), CCI400)
+INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \
+ ${PLAT_DRIVERS_PATH}/interconnect/ls_cci.c
+endif
+endif
+endif
+
+ifeq (${BL_COMM_INTERCONNECT_NEEDED},yes)
+BL_COMMON_SOURCES += ${INTERCONNECT_SOURCES}
+else
+ifeq (${BL2_INTERCONNECT_NEEDED},yes)
+BL2_SOURCES += ${INTERCONNECT_SOURCES}
+endif
+ifeq (${BL31_INTERCONNECT_NEEDED},yes)
+BL31_SOURCES += ${INTERCONNECT_SOURCES}
+endif
+endif
+endif
+
+# -----------------------------------------------------------------------------
diff --git a/drivers/nxp/interconnect/ls_cci.c b/drivers/nxp/interconnect/ls_cci.c
new file mode 100644
index 0000000..72a898a
--- /dev/null
+++ b/drivers/nxp/interconnect/ls_cci.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <arch.h>
+#include <cci.h>
+
+#include <plat_arm.h>
+
+/******************************************************************************
+ * The following functions are defined as weak to allow a platform to override
+ * the way ARM CCI driver is initialised and used.
+ *****************************************************************************/
+#pragma weak plat_arm_interconnect_enter_coherency
+#pragma weak plat_arm_interconnect_exit_coherency
+
+/******************************************************************************
+ * Helper function to place current master into coherency
+ *****************************************************************************/
+void plat_ls_interconnect_enter_coherency(unsigned int num_clusters)
+{
+ cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
+
+ for (uint32_t index = 1U; index < num_clusters; index++) {
+ cci_enable_snoop_dvm_reqs(index);
+ }
+}
+
+/******************************************************************************
+ * Helper function to remove current master from coherency
+ *****************************************************************************/
+void plat_ls_interconnect_exit_coherency(void)
+{
+ cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
+}
diff --git a/drivers/nxp/interconnect/ls_ccn.c b/drivers/nxp/interconnect/ls_ccn.c
new file mode 100644
index 0000000..8f90325
--- /dev/null
+++ b/drivers/nxp/interconnect/ls_ccn.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <arch.h>
+#include <ccn.h>
+
+#include <plat_arm.h>
+
+/******************************************************************************
+ * Helper function to place current master into coherency
+ *****************************************************************************/
+void plat_ls_interconnect_enter_coherency(unsigned int num_clusters)
+{
+ ccn_enter_snoop_dvm_domain(1ULL << MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
+
+ for (uint32_t index = 1U; index < num_clusters; index++) {
+ ccn_enter_snoop_dvm_domain(1ULL << index);
+ }
+}
+
+/******************************************************************************
+ * Helper function to remove current master from coherency
+ *****************************************************************************/
+void plat_ls_interconnect_exit_coherency(void)
+{
+ ccn_exit_snoop_dvm_domain(1ULL << MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
+}
diff --git a/drivers/nxp/pmu/pmu.c b/drivers/nxp/pmu/pmu.c
new file mode 100644
index 0000000..2a907c8
--- /dev/null
+++ b/drivers/nxp/pmu/pmu.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <dcfg.h>
+#include <lib/mmio.h>
+#include <pmu.h>
+
+void enable_timer_base_to_cluster(uintptr_t nxp_pmu_addr)
+{
+ uint32_t *cltbenr = NULL;
+ uint32_t cltbenr_val = 0U;
+
+ cltbenr = (uint32_t *)(nxp_pmu_addr
+ + CLUST_TIMER_BASE_ENBL_OFFSET);
+
+ cltbenr_val = mmio_read_32((uintptr_t)cltbenr);
+
+ cltbenr_val = cltbenr_val
+ | (1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
+
+ mmio_write_32((uintptr_t)cltbenr, cltbenr_val);
+
+ VERBOSE("Enable cluster time base\n");
+}
+
+/*
+ * Enable core timebase. In certain Layerscape SoCs, the clock for each core's
+ * has an enable bit in the PMU Physical Core Time Base Enable
+ * Register (PCTBENR), which allows the watchdog to operate.
+ */
+
+void enable_core_tb(uintptr_t nxp_pmu_addr)
+{
+ uint32_t *pctbenr = (uint32_t *) (nxp_pmu_addr +
+ CORE_TIMEBASE_ENBL_OFFSET);
+
+ mmio_write_32((uintptr_t)pctbenr, 0xff);
+}
diff --git a/drivers/nxp/pmu/pmu.mk b/drivers/nxp/pmu/pmu.mk
new file mode 100644
index 0000000..8d2ef07
--- /dev/null
+++ b/drivers/nxp/pmu/pmu.mk
@@ -0,0 +1,26 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-----------------------------------------------------------------------------
+ifeq (${PMU_ADDED},)
+
+PMU_ADDED := 1
+
+PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLUDE_PATH)/pmu
+
+PMU_SOURCES += $(PLAT_DRIVERS_PATH)/pmu/pmu.c
+
+ifeq (${BL_COMM_PMU_NEEDED},yes)
+BL_COMMON_SOURCES += ${PMU_SOURCES}
+else
+ifeq (${BL2_PMU_NEEDED},yes)
+BL2_SOURCES += ${PMU_SOURCES}
+endif
+ifeq (${BL31_PMU_NEEDED},yes)
+BL31_SOURCES += ${PMU_SOURCES}
+endif
+endif
+endif
+#------------------------------------------------
diff --git a/drivers/nxp/qspi/qspi.c b/drivers/nxp/qspi/qspi.c
new file mode 100644
index 0000000..97b2a19
--- /dev/null
+++ b/drivers/nxp/qspi/qspi.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <assert.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <qspi.h>
+
+int qspi_io_setup(uintptr_t nxp_qspi_flash_addr,
+ size_t nxp_qspi_flash_size,
+ uintptr_t fip_offset)
+{
+ uint32_t qspi_mcr_val = qspi_in32(CHS_QSPI_MCR);
+
+ /* Enable and change endianness of QSPI IP */
+ qspi_out32(CHS_QSPI_MCR, (qspi_mcr_val | CHS_QSPI_64LE));
+
+ /* Adding QSPI Memory Map in XLAT Table */
+ mmap_add_region(nxp_qspi_flash_addr, nxp_qspi_flash_addr,
+ nxp_qspi_flash_size, MT_MEMORY | MT_RW);
+
+ return 0;
+}
diff --git a/drivers/nxp/qspi/qspi.mk b/drivers/nxp/qspi/qspi.mk
new file mode 100644
index 0000000..b83dee2
--- /dev/null
+++ b/drivers/nxp/qspi/qspi.mk
@@ -0,0 +1,26 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${QSPI_ADDED},)
+
+QSPI_ADDED := 1
+
+QSPI_SOURCES := $(PLAT_DRIVERS_PATH)/qspi/qspi.c
+
+PLAT_INCLUDES += -I$(PLAT_DRIVERS_PATH)/qspi
+
+ifeq (${BL_COMM_QSPI_NEEDED},yes)
+BL_COMMON_SOURCES += ${QSPI_SOURCES}
+else
+ifeq (${BL2_QSPI_NEEDED},yes)
+BL2_SOURCES += ${QSPI_SOURCES}
+endif
+ifeq (${BL31_QSPI_NEEDED},yes)
+BL31_SOURCES += ${QSPI_SOURCES}
+endif
+endif
+
+endif
diff --git a/drivers/nxp/sd/sd_mmc.c b/drivers/nxp/sd/sd_mmc.c
new file mode 100644
index 0000000..f7f48e7
--- /dev/null
+++ b/drivers/nxp/sd/sd_mmc.c
@@ -0,0 +1,1496 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ *
+ */
+
+#include <endian.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/io/io_block.h>
+#include "nxp_timer.h"
+#include "sd_mmc.h"
+#include <utils.h>
+#include <utils_def.h>
+
+
+/* Private structure for MMC driver data */
+static struct mmc mmc_drv_data;
+
+#ifndef NXP_POLICY_OTA
+/*
+ * For NXP_POLICY_OTA, SD needs to do R/W on OCRAM. OCRAM is secure memory at
+ * default. SD can only do non-secure DMA. Configuring SD to work in PIO mode
+ * instead of DMA mode will make SD R/W on OCRAM available.
+ */
+/* To debug without dma comment this MACRO */
+#define NXP_SD_DMA_CAPABILITY
+#endif
+#define SD_TIMEOUT 1000 /* ms */
+#define SD_TIMEOUT_HIGH 20000 /* ms */
+#define SD_BLOCK_TIMEOUT 8 /* ms */
+
+#define ERROR_ESDHC_CARD_DETECT_FAIL -1
+#define ERROR_ESDHC_UNUSABLE_CARD -2
+#define ERROR_ESDHC_COMMUNICATION_ERROR -3
+#define ERROR_ESDHC_BLOCK_LENGTH -4
+#define ERROR_ESDHC_DMA_ERROR -5
+#define ERROR_ESDHC_BUSY -6
+
+/***************************************************************
+ * Function : set_speed
+ * Arguments : mmc - Pointer to mmc struct
+ * clock - Clock Value to be set
+ * Return : void
+ * Description : Calculates the value of SDCLKFS and DVS to be set
+ * for getting the required clock assuming the base_clk
+ * as a fixed value (MAX_PLATFORM_CLOCK)
+ *****************************************************************/
+static void set_speed(struct mmc *mmc, uint32_t clock)
+{
+ /* sdhc_clk = (base clock) / [(SDCLKFS × 2) × (DVS +1)] */
+
+ uint32_t dvs = 1U;
+ uint32_t sdclkfs = 2U;
+ /* TBD - Change this to actual platform clock by reading via RCW */
+ uint32_t base_clk = MAX_PLATFORM_CLOCK;
+
+ if (base_clk / 16 > clock) {
+ for (sdclkfs = 2U; sdclkfs < 256U; sdclkfs *= 2U) {
+ if ((base_clk / sdclkfs) <= (clock * 16)) {
+ break;
+ }
+ }
+ }
+
+ for (dvs = 1U; dvs <= 16U; dvs++) {
+ if ((base_clk / (dvs * sdclkfs)) <= clock) {
+ break;
+ }
+ }
+
+ sdclkfs >>= 1U;
+ dvs -= 1U;
+
+ esdhc_out32(&mmc->esdhc_regs->sysctl,
+ (ESDHC_SYSCTL_DTOCV(TIMEOUT_COUNTER_SDCLK_2_27) |
+ ESDHC_SYSCTL_SDCLKFS(sdclkfs) | ESDHC_SYSCTL_DVS(dvs) |
+ ESDHC_SYSCTL_SDCLKEN));
+}
+
+/***************************************************************************
+ * Function : esdhc_init
+ * Arguments : mmc - Pointer to mmc struct
+ * card_detect - flag to indicate if card insert needs
+ * to be detected or not. For SDHC2 controller, Card detect
+ * is not present, so this field will be false
+ * Return : SUCCESS or Error Code
+ * Description : 1. Set Initial Clock Speed
+ * 2. Card Detect if not eMMC
+ * 3. Enable Controller Clock
+ * 4. Send 80 ticks for card to power up
+ * 5. Set LE mode and Bus Width as 1 bit.
+ ***************************************************************************/
+static int esdhc_init(struct mmc *mmc, bool card_detect)
+{
+ uint32_t val;
+ uint64_t start_time;
+
+ /* Reset the entire host controller */
+ val = esdhc_in32(&mmc->esdhc_regs->sysctl) | ESDHC_SYSCTL_RSTA;
+ esdhc_out32(&mmc->esdhc_regs->sysctl, val);
+
+ /* Wait until the controller is available */
+ start_time = get_timer_val(0);
+ while (get_timer_val(start_time) < SD_TIMEOUT_HIGH) {
+ val = esdhc_in32(&mmc->esdhc_regs->sysctl) & ESDHC_SYSCTL_RSTA;
+ if (val == 0U) {
+ break;
+ }
+ }
+
+ val = esdhc_in32(&mmc->esdhc_regs->sysctl) &
+ (ESDHC_SYSCTL_RSTA);
+ if (val != 0U) {
+ ERROR("SD Reset failed\n");
+ return ERROR_ESDHC_BUSY;
+ }
+
+ /* Set initial clock speed */
+ set_speed(mmc, CARD_IDENTIFICATION_FREQ);
+
+ if (card_detect) {
+ /* Check CINS in prsstat register */
+ val = esdhc_in32(&mmc->esdhc_regs->prsstat) &
+ ESDHC_PRSSTAT_CINS;
+ if (val == 0) {
+ ERROR("CINS not set in prsstat\n");
+ return ERROR_ESDHC_CARD_DETECT_FAIL;
+ }
+ }
+
+ /* Enable controller clock */
+ val = esdhc_in32(&mmc->esdhc_regs->sysctl) | ESDHC_SYSCTL_SDCLKEN;
+ esdhc_out32(&mmc->esdhc_regs->sysctl, val);
+
+ /* Send 80 clock ticks for the card to power up */
+ val = esdhc_in32(&mmc->esdhc_regs->sysctl) | ESDHC_SYSCTL_INITA;
+ esdhc_out32(&mmc->esdhc_regs->sysctl, val);
+
+ start_time = get_timer_val(0);
+ while (get_timer_val(start_time) < SD_TIMEOUT) {
+ val = esdhc_in32(&mmc->esdhc_regs->sysctl) & ESDHC_SYSCTL_INITA;
+ if (val != 0U) {
+ break;
+ }
+ }
+
+ val = esdhc_in32(&mmc->esdhc_regs->sysctl) & ESDHC_SYSCTL_INITA;
+ if (val == 0U) {
+ ERROR("Failed to power up the card\n");
+ return ERROR_ESDHC_CARD_DETECT_FAIL;
+ }
+
+ INFO("Card detected successfully\n");
+
+ val = esdhc_in32(&mmc->esdhc_regs->proctl);
+ val = val | (ESDHC_PROCTL_EMODE_LE | ESDHC_PROCTL_DTW_1BIT);
+
+ /* Set little endian mode, set bus width as 1-bit */
+ esdhc_out32(&mmc->esdhc_regs->proctl, val);
+
+ /* Enable cache snooping for DMA transactions */
+ val = esdhc_in32(&mmc->esdhc_regs->ctl) | ESDHC_DCR_SNOOP;
+ esdhc_out32(&mmc->esdhc_regs->ctl, val);
+
+ return 0;
+}
+
+/***************************************************************************
+ * Function : esdhc_send_cmd
+ * Arguments : mmc - Pointer to mmc struct
+ * cmd - Command Number
+ * args - Command Args
+ * Return : SUCCESS is 0, or Error Code ( < 0)
+ * Description : Updates the eSDHC registers cmdargs and xfertype
+ ***************************************************************************/
+static int esdhc_send_cmd(struct mmc *mmc, uint32_t cmd, uint32_t args)
+{
+ uint32_t val;
+ uint64_t start_time;
+ uint32_t xfertyp = 0;
+
+ esdhc_out32(&mmc->esdhc_regs->irqstat, ESDHC_IRQSTAT_CLEAR_ALL);
+
+ /* Wait for the command line & data line to be free */
+ /* (poll the CIHB,CDIHB bit of the present state register) */
+ start_time = get_timer_val(0);
+ while (get_timer_val(start_time) < SD_TIMEOUT_HIGH) {
+ val = esdhc_in32(&mmc->esdhc_regs->prsstat) &
+ (ESDHC_PRSSTAT_CIHB | ESDHC_PRSSTAT_CDIHB);
+ if (val == 0U) {
+ break;
+ }
+ }
+
+ val = esdhc_in32(&mmc->esdhc_regs->prsstat) &
+ (ESDHC_PRSSTAT_CIHB | ESDHC_PRSSTAT_CDIHB);
+ if (val != 0U) {
+ ERROR("SD send cmd: Command Line or Data Line Busy cmd = %x\n",
+ cmd);
+ return ERROR_ESDHC_BUSY;
+ }
+
+ if (cmd == CMD2 || cmd == CMD9) {
+ xfertyp |= ESDHC_XFERTYP_RSPTYP_136;
+ } else if (cmd == CMD7 || (cmd == CMD6 && mmc->card.type == MMC_CARD)) {
+ xfertyp |= ESDHC_XFERTYP_RSPTYP_48_BUSY;
+ } else if (cmd != CMD0) {
+ xfertyp |= ESDHC_XFERTYP_RSPTYP_48;
+ }
+
+ if (cmd == CMD2 || cmd == CMD9) {
+ xfertyp |= ESDHC_XFERTYP_CCCEN; /* Command index check enable */
+ } else if ((cmd != CMD0) && (cmd != ACMD41) && (cmd != CMD1)) {
+ xfertyp = xfertyp | ESDHC_XFERTYP_CCCEN | ESDHC_XFERTYP_CICEN;
+ }
+
+ if ((cmd == CMD8 || cmd == CMD14 || cmd == CMD19) &&
+ mmc->card.type == MMC_CARD) {
+ xfertyp |= ESDHC_XFERTYP_DPSEL;
+ if (cmd != CMD19) {
+ xfertyp |= ESDHC_XFERTYP_DTDSEL;
+ }
+ }
+
+ if (cmd == CMD6 || cmd == CMD17 || cmd == CMD18 || cmd == CMD24 ||
+ cmd == ACMD51) {
+ if (!(mmc->card.type == MMC_CARD && cmd == CMD6)) {
+ if (cmd == CMD24) {
+ xfertyp |= ESDHC_XFERTYP_DPSEL;
+ } else {
+ xfertyp |= (ESDHC_XFERTYP_DPSEL |
+ ESDHC_XFERTYP_DTDSEL);
+ }
+ }
+
+ if (cmd == CMD18) {
+ xfertyp |= ESDHC_XFERTYP_BCEN;
+ if (mmc->dma_support != 0) {
+ /* Set BCEN of XFERTYP */
+ xfertyp |= ESDHC_XFERTYP_DMAEN;
+ }
+ }
+
+ if ((cmd == CMD17 || cmd == CMD24) && (mmc->dma_support != 0)) {
+ xfertyp |= ESDHC_XFERTYP_DMAEN;
+ }
+ }
+
+ xfertyp |= ((cmd & 0x3F) << 24);
+ esdhc_out32(&mmc->esdhc_regs->cmdarg, args);
+ esdhc_out32(&mmc->esdhc_regs->xfertyp, xfertyp);
+
+#ifdef NXP_SD_DEBUG
+ INFO("cmd = %d\n", cmd);
+ INFO("args = %x\n", args);
+ INFO("xfertyp: = %x\n", xfertyp);
+#endif
+ return 0;
+}
+
+/***************************************************************************
+ * Function : esdhc_wait_response
+ * Arguments : mmc - Pointer to mmc struct
+ * response - Value updated
+ * Return : SUCCESS - Response Received
+ * COMMUNICATION_ERROR - Command not Complete
+ * COMMAND_ERROR - CIE, CCE or CEBE error
+ * RESP_TIMEOUT - CTOE error
+ * Description : Checks for successful command completion.
+ * Clears the CC bit at the end.
+ ***************************************************************************/
+static int esdhc_wait_response(struct mmc *mmc, uint32_t *response)
+{
+ uint32_t val;
+ uint64_t start_time;
+ uint32_t status = 0U;
+
+ /* Wait for the command to complete */
+ start_time = get_timer_val(0);
+ while (get_timer_val(start_time) < SD_TIMEOUT_HIGH) {
+ val = esdhc_in32(&mmc->esdhc_regs->irqstat) & ESDHC_IRQSTAT_CC;
+ if (val != 0U) {
+ break;
+ }
+ }
+
+ val = esdhc_in32(&mmc->esdhc_regs->irqstat) & ESDHC_IRQSTAT_CC;
+ if (val == 0U) {
+ ERROR("%s:IRQSTAT Cmd not complete(CC not set)\n", __func__);
+ return ERROR_ESDHC_COMMUNICATION_ERROR;
+ }
+
+ status = esdhc_in32(&mmc->esdhc_regs->irqstat);
+
+ /* Check whether the interrupt is a CRC, CTOE or CIE error */
+ if ((status & (ESDHC_IRQSTAT_CIE | ESDHC_IRQSTAT_CEBE |
+ ESDHC_IRQSTAT_CCE)) != 0) {
+ ERROR("%s: IRQSTAT CRC, CEBE or CIE error = %x\n",
+ __func__, status);
+ return COMMAND_ERROR;
+ }
+
+ if ((status & ESDHC_IRQSTAT_CTOE) != 0) {
+ INFO("%s: IRQSTAT CTOE set = %x\n", __func__, status);
+ return RESP_TIMEOUT;
+ }
+
+ if ((status & ESDHC_IRQSTAT_DMAE) != 0) {
+ ERROR("%s: IRQSTAT DMAE set = %x\n", __func__, status);
+ return ERROR_ESDHC_DMA_ERROR;
+ }
+
+ if (response != NULL) {
+ /* Get response values from eSDHC CMDRSPx registers. */
+ response[0] = esdhc_in32(&mmc->esdhc_regs->cmdrsp[0]);
+ response[1] = esdhc_in32(&mmc->esdhc_regs->cmdrsp[1]);
+ response[2] = esdhc_in32(&mmc->esdhc_regs->cmdrsp[2]);
+ response[3] = esdhc_in32(&mmc->esdhc_regs->cmdrsp[3]);
+#ifdef NXP_SD_DEBUG
+ INFO("Resp R1 R2 R3 R4\n");
+ INFO("Resp R1 = %x\n", response[0]);
+ INFO("R2 = %x\n", response[1]);
+ INFO("R3 = %x\n", response[2]);
+ INFO("R4 = %x\n", response[3]);
+ INFO("\n");
+#endif
+ }
+
+ /* Clear the CC bit - w1c */
+ val = esdhc_in32(&mmc->esdhc_regs->irqstat) | ESDHC_IRQSTAT_CC;
+ esdhc_out32(&mmc->esdhc_regs->irqstat, val);
+
+ return 0;
+}
+
+/***************************************************************************
+ * Function : mmc_switch_to_high_frquency
+ * Arguments : mmc - Pointer to mmc struct
+ * Return : SUCCESS or Error Code
+ * Description : mmc card bellow ver 4.0 does not support high speed
+ * freq = 20 MHz
+ * Send CMD6 (CMD_SWITCH_FUNC) With args 0x03B90100
+ * Send CMD13 (CMD_SEND_STATUS)
+ * if SWITCH Error, freq = 26 MHz
+ * if no error, freq = 52 MHz
+ ***************************************************************************/
+static int mmc_switch_to_high_frquency(struct mmc *mmc)
+{
+ int error;
+ uint32_t response[4];
+ uint64_t start_time;
+
+ mmc->card.bus_freq = MMC_SS_20MHZ;
+ /* mmc card bellow ver 4.0 does not support high speed */
+ if (mmc->card.version < MMC_CARD_VERSION_4_X) {
+ return 0;
+ }
+
+ /* send switch cmd to change the card to High speed */
+ error = esdhc_send_cmd(mmc, CMD_SWITCH_FUNC, SET_EXT_CSD_HS_TIMING);
+ if (error != 0) {
+ return error;
+ }
+ error = esdhc_wait_response(mmc, response);
+ if (error != 0) {
+ return error;
+ }
+
+ start_time = get_timer_val(0);
+ do {
+ /* check the status for which error */
+ error = esdhc_send_cmd(mmc,
+ CMD_SEND_STATUS, mmc->card.rca << 16);
+ if (error != 0) {
+ return error;
+ }
+
+ error = esdhc_wait_response(mmc, response);
+ if (error != 0) {
+ return error;
+ }
+ } while (((response[0] & SWITCH_ERROR) != 0) &&
+ (get_timer_val(start_time) < SD_TIMEOUT));
+
+ /* Check for the present state of card */
+ if ((response[0] & SWITCH_ERROR) != 0) {
+ mmc->card.bus_freq = MMC_HS_26MHZ;
+ } else {
+ mmc->card.bus_freq = MMC_HS_52MHZ;
+ }
+
+ return 0;
+}
+
+/***************************************************************************
+ * Function : esdhc_set_data_attributes
+ * Arguments : mmc - Pointer to mmc struct
+ * blkcnt
+ * blklen
+ * Return : SUCCESS or Error Code
+ * Description : Set block attributes and watermark level register
+ ***************************************************************************/
+static int esdhc_set_data_attributes(struct mmc *mmc, uint32_t *dest_ptr,
+ uint32_t blkcnt, uint32_t blklen)
+{
+ uint32_t val;
+ uint64_t start_time;
+ uint32_t wml;
+ uint32_t wl;
+ uint32_t dst = (uint32_t)((uint64_t)(dest_ptr));
+
+ /* set blkattr when no transactions are executing */
+ start_time = get_timer_val(0);
+ while (get_timer_val(start_time) < SD_TIMEOUT_HIGH) {
+ val = esdhc_in32(&mmc->esdhc_regs->prsstat) & ESDHC_PRSSTAT_DLA;
+ if (val == 0U) {
+ break;
+ }
+ }
+
+ val = esdhc_in32(&mmc->esdhc_regs->prsstat) & ESDHC_PRSSTAT_DLA;
+ if (val != 0U) {
+ ERROR("%s: Data line active.Can't set attribute\n", __func__);
+ return ERROR_ESDHC_COMMUNICATION_ERROR;
+ }
+
+ wml = esdhc_in32(&mmc->esdhc_regs->wml);
+ wml &= ~(ESDHC_WML_WR_BRST_MASK | ESDHC_WML_RD_BRST_MASK |
+ ESDHC_WML_RD_WML_MASK | ESDHC_WML_WR_WML_MASK);
+
+ if ((mmc->dma_support != 0) && (dest_ptr != NULL)) {
+ /* Set burst length to 128 bytes */
+ esdhc_out32(&mmc->esdhc_regs->wml,
+ wml | ESDHC_WML_WR_BRST(BURST_128_BYTES));
+ esdhc_out32(&mmc->esdhc_regs->wml,
+ wml | ESDHC_WML_RD_BRST(BURST_128_BYTES));
+
+ /* Set DMA System Destination Address */
+ esdhc_out32(&mmc->esdhc_regs->dsaddr, dst);
+ } else {
+ wl = (blklen >= BLOCK_LEN_512) ?
+ WML_512_BYTES : ((blklen + 3) / 4);
+ /* Set 'Read Water Mark Level' register */
+ esdhc_out32(&mmc->esdhc_regs->wml, wml | ESDHC_WML_RD_WML(wl));
+ }
+
+ /* Configure block Attributes register */
+ esdhc_out32(&mmc->esdhc_regs->blkattr,
+ ESDHC_BLKATTR_BLKCNT(blkcnt) | ESDHC_BLKATTR_BLKSZE(blklen));
+
+ mmc->block_len = blklen;
+
+ return 0;
+}
+
+/***************************************************************************
+ * Function : esdhc_read_data_nodma
+ * Arguments : mmc - Pointer to mmc struct
+ * dest_ptr - Bufffer where read data is to be copied
+ * len - Length of Data to be read
+ * Return : SUCCESS or Error Code
+ * Description : Read data from the sdhc buffer without using DMA
+ * and using polling mode
+ ***************************************************************************/
+static int esdhc_read_data_nodma(struct mmc *mmc, void *dest_ptr, uint32_t len)
+{
+ uint32_t i = 0U;
+ uint32_t status;
+ uint32_t num_blocks;
+ uint32_t *dst = (uint32_t *)dest_ptr;
+ uint32_t val;
+ uint64_t start_time;
+
+ num_blocks = len / mmc->block_len;
+
+ while ((num_blocks--) != 0U) {
+
+ start_time = get_timer_val(0);
+ while (get_timer_val(start_time) < SD_TIMEOUT_HIGH) {
+ val = esdhc_in32(&mmc->esdhc_regs->prsstat) &
+ ESDHC_PRSSTAT_BREN;
+ if (val != 0U) {
+ break;
+ }
+ }
+
+ val = esdhc_in32(&mmc->esdhc_regs->prsstat)
+ & ESDHC_PRSSTAT_BREN;
+ if (val == 0U) {
+ return ERROR_ESDHC_COMMUNICATION_ERROR;
+ }
+
+ for (i = 0U, status = esdhc_in32(&mmc->esdhc_regs->irqstat);
+ i < mmc->block_len / 4; i++, dst++) {
+ /* get data from data port */
+ val = mmio_read_32(
+ (uintptr_t)&mmc->esdhc_regs->datport);
+ esdhc_out32(dst, val);
+ /* Increment destination pointer */
+ status = esdhc_in32(&mmc->esdhc_regs->irqstat);
+ }
+ /* Check whether the interrupt is an DTOE/DCE/DEBE */
+ if ((status & (ESDHC_IRQSTAT_DTOE | ESDHC_IRQSTAT_DCE |
+ ESDHC_IRQSTAT_DEBE)) != 0) {
+ ERROR("SD read error - DTOE, DCE, DEBE bit set = %x\n",
+ status);
+ return ERROR_ESDHC_COMMUNICATION_ERROR;
+ }
+ }
+
+ /* Wait for TC */
+
+ start_time = get_timer_val(0);
+ while (get_timer_val(start_time) < SD_TIMEOUT_HIGH) {
+ val = esdhc_in32(&mmc->esdhc_regs->irqstat) & ESDHC_IRQSTAT_TC;
+ if (val != 0U) {
+ break;
+ }
+ }
+
+ val = esdhc_in32(&mmc->esdhc_regs->irqstat) & ESDHC_IRQSTAT_TC;
+ if (val == 0U) {
+ ERROR("SD read timeout: Transfer bit not set in IRQSTAT\n");
+ return ERROR_ESDHC_COMMUNICATION_ERROR;
+ }
+
+ return 0;
+}
+
+/***************************************************************************
+ * Function : esdhc_write_data_nodma
+ * Arguments : mmc - Pointer to mmc struct
+ * src_ptr - Buffer where data is copied from
+ * len - Length of Data to be written
+ * Return : SUCCESS or Error Code
+ * Description : Write data to the sdhc buffer without using DMA
+ * and using polling mode
+ ***************************************************************************/
+static int esdhc_write_data_nodma(struct mmc *mmc, void *src_ptr, uint32_t len)
+{
+ uint32_t i = 0U;
+ uint32_t status;
+ uint32_t num_blocks;
+ uint32_t *src = (uint32_t *)src_ptr;
+ uint32_t val;
+ uint64_t start_time;
+
+ num_blocks = len / mmc->block_len;
+
+ while ((num_blocks--) != 0U) {
+ start_time = get_timer_val(0);
+ while (get_timer_val(start_time) < SD_TIMEOUT_HIGH) {
+ val = esdhc_in32(&mmc->esdhc_regs->prsstat) &
+ ESDHC_PRSSTAT_BWEN;
+ if (val != 0U) {
+ break;
+ }
+ }
+
+ val = esdhc_in32(&mmc->esdhc_regs->prsstat) &
+ ESDHC_PRSSTAT_BWEN;
+ if (val == 0U) {
+ return ERROR_ESDHC_COMMUNICATION_ERROR;
+ }
+
+ for (i = 0U, status = esdhc_in32(&mmc->esdhc_regs->irqstat);
+ i < mmc->block_len / 4; i++, src++) {
+ val = esdhc_in32(src);
+ /* put data to data port */
+ mmio_write_32((uintptr_t)&mmc->esdhc_regs->datport,
+ val);
+ /* Increment source pointer */
+ status = esdhc_in32(&mmc->esdhc_regs->irqstat);
+ }
+ /* Check whether the interrupt is an DTOE/DCE/DEBE */
+ if ((status & (ESDHC_IRQSTAT_DTOE | ESDHC_IRQSTAT_DCE |
+ ESDHC_IRQSTAT_DEBE)) != 0) {
+ ERROR("SD write error - DTOE, DCE, DEBE bit set = %x\n",
+ status);
+ return ERROR_ESDHC_COMMUNICATION_ERROR;
+ }
+ }
+
+ /* Wait for TC */
+ start_time = get_timer_val(0);
+ while (get_timer_val(start_time) < SD_TIMEOUT_HIGH) {
+ val = esdhc_in32(&mmc->esdhc_regs->irqstat) & ESDHC_IRQSTAT_TC;
+ if (val != 0U) {
+ break;
+ }
+ }
+
+ val = esdhc_in32(&mmc->esdhc_regs->irqstat) & ESDHC_IRQSTAT_TC;
+ if (val == 0U) {
+ ERROR("SD write timeout: Transfer bit not set in IRQSTAT\n");
+ return ERROR_ESDHC_COMMUNICATION_ERROR;
+ }
+
+ return 0;
+}
+
+/***************************************************************************
+ * Function : esdhc_read_data_dma
+ * Arguments : mmc - Pointer to mmc struct
+ * len - Length of Data to be read
+ * Return : SUCCESS or Error Code
+ * Description : Read data from the sd card using DMA.
+ ***************************************************************************/
+static int esdhc_read_data_dma(struct mmc *mmc, uint32_t len)
+{
+ uint32_t status;
+ uint32_t tblk;
+ uint64_t start_time;
+
+ tblk = SD_BLOCK_TIMEOUT * (len / mmc->block_len);
+
+ start_time = get_timer_val(0);
+
+ /* poll till TC is set */
+ do {
+ status = esdhc_in32(&mmc->esdhc_regs->irqstat);
+
+ if ((status & (ESDHC_IRQSTAT_DEBE | ESDHC_IRQSTAT_DCE
+ | ESDHC_IRQSTAT_DTOE)) != 0) {
+ ERROR("SD read error - DTOE, DCE, DEBE bit set = %x\n",
+ status);
+ return ERROR_ESDHC_COMMUNICATION_ERROR;
+ }
+
+ if ((status & ESDHC_IRQSTAT_DMAE) != 0) {
+ ERROR("SD read error - DMA error = %x\n", status);
+ return ERROR_ESDHC_DMA_ERROR;
+ }
+
+ } while (((status & ESDHC_IRQSTAT_TC) == 0) &&
+ ((esdhc_in32(&mmc->esdhc_regs->prsstat) & ESDHC_PRSSTAT_DLA) != 0) &&
+ (get_timer_val(start_time) < SD_TIMEOUT_HIGH + tblk));
+
+ if (get_timer_val(start_time) > SD_TIMEOUT_HIGH + tblk) {
+ ERROR("SD read DMA timeout\n");
+ return ERROR_ESDHC_COMMUNICATION_ERROR;
+ }
+
+ return 0;
+}
+
+/***************************************************************************
+ * Function : esdhc_write_data_dma
+ * Arguments : mmc - Pointer to mmc struct
+ * len - Length of Data to be written
+ * Return : SUCCESS or Error Code
+ * Description : Write data to the sd card using DMA.
+ ***************************************************************************/
+static int esdhc_write_data_dma(struct mmc *mmc, uint32_t len)
+{
+ uint32_t status;
+ uint32_t tblk;
+ uint64_t start_time;
+
+ tblk = SD_BLOCK_TIMEOUT * (len / mmc->block_len);
+
+ start_time = get_timer_val(0);
+
+ /* poll till TC is set */
+ do {
+ status = esdhc_in32(&mmc->esdhc_regs->irqstat);
+
+ if ((status & (ESDHC_IRQSTAT_DEBE | ESDHC_IRQSTAT_DCE
+ | ESDHC_IRQSTAT_DTOE)) != 0) {
+ ERROR("SD write error - DTOE, DCE, DEBE bit set = %x\n",
+ status);
+ return ERROR_ESDHC_COMMUNICATION_ERROR;
+ }
+
+ if ((status & ESDHC_IRQSTAT_DMAE) != 0) {
+ ERROR("SD write error - DMA error = %x\n", status);
+ return ERROR_ESDHC_DMA_ERROR;
+ }
+ } while (((status & ESDHC_IRQSTAT_TC) == 0) &&
+ ((esdhc_in32(&mmc->esdhc_regs->prsstat) & ESDHC_PRSSTAT_DLA) != 0) &&
+ (get_timer_val(start_time) < SD_TIMEOUT_HIGH + tblk));
+
+ if (get_timer_val(start_time) > SD_TIMEOUT_HIGH + tblk) {
+ ERROR("SD write DMA timeout\n");
+ return ERROR_ESDHC_COMMUNICATION_ERROR;
+ }
+
+ return 0;
+}
+
+/***************************************************************************
+ * Function : esdhc_read_data
+ * Arguments : mmc - Pointer to mmc struct
+ * dest_ptr - Bufffer where read data is to be copied
+ * len - Length of Data to be read
+ * Return : SUCCESS or Error Code
+ * Description : Calls esdhc_read_data_nodma and clear interrupt status
+ ***************************************************************************/
+int esdhc_read_data(struct mmc *mmc, void *dest_ptr, uint32_t len)
+{
+ int ret;
+
+ if (mmc->dma_support && len > 64) {
+ ret = esdhc_read_data_dma(mmc, len);
+ } else {
+ ret = esdhc_read_data_nodma(mmc, dest_ptr, len);
+ }
+
+ /* clear interrupt status */
+ esdhc_out32(&mmc->esdhc_regs->irqstat, ESDHC_IRQSTAT_CLEAR_ALL);
+
+ return ret;
+}
+
+/***************************************************************************
+ * Function : esdhc_write_data
+ * Arguments : mmc - Pointer to mmc struct
+ * src_ptr - Buffer where data is copied from
+ * len - Length of Data to be written
+ * Return : SUCCESS or Error Code
+ * Description : Calls esdhc_write_data_nodma and clear interrupt status
+ ***************************************************************************/
+int esdhc_write_data(struct mmc *mmc, void *src_ptr, uint32_t len)
+{
+ int ret;
+
+ if (mmc->dma_support && len > 64) {
+ ret = esdhc_write_data_dma(mmc, len);
+ } else {
+ ret = esdhc_write_data_nodma(mmc, src_ptr, len);
+ }
+
+ /* clear interrupt status */
+ esdhc_out32(&mmc->esdhc_regs->irqstat, ESDHC_IRQSTAT_CLEAR_ALL);
+
+ return ret;
+}
+
+/***************************************************************************
+ * Function : sd_switch_to_high_freq
+ * Arguments : mmc - Pointer to mmc struct
+ * Return : SUCCESS or Error Code
+ * Description : 1. Send ACMD51 (CMD_SEND_SCR)
+ * 2. Read the SCR to check if card supports higher freq
+ * 3. check version from SCR
+ * 4. If SD 1.0, return (no Switch) freq = 25 MHz.
+ * 5. Send CMD6 (CMD_SWITCH_FUNC) with args 0x00FFFFF1 to
+ * check the status of switch func
+ * 6. Send CMD6 (CMD_SWITCH_FUNC) With args 0x80FFFFF1 to
+ * switch to high frequency = 50 Mhz
+ ***************************************************************************/
+static int sd_switch_to_high_freq(struct mmc *mmc)
+{
+ int err;
+ uint8_t scr[8];
+ uint8_t status[64];
+ uint32_t response[4];
+ uint32_t version;
+ uint32_t count;
+ uint32_t sd_versions[] = {SD_CARD_VERSION_1_0, SD_CARD_VERSION_1_10,
+ SD_CARD_VERSION_2_0};
+
+ mmc->card.bus_freq = SD_SS_25MHZ;
+ /* Send Application command */
+ err = esdhc_send_cmd(mmc, CMD_APP_CMD, mmc->card.rca << 16);
+ if (err != 0) {
+ return err;
+ }
+
+ err = esdhc_wait_response(mmc, response);
+ if (err != 0) {
+ return err;
+ }
+
+ esdhc_set_data_attributes(mmc, NULL, 1, 8);
+ /* Read the SCR to find out if this card supports higher speeds */
+ err = esdhc_send_cmd(mmc, CMD_SEND_SCR, mmc->card.rca << 16);
+ if (err != 0) {
+ return err;
+ }
+ err = esdhc_wait_response(mmc, response);
+ if (err != 0) {
+ return err;
+ }
+
+ /* read 8 bytes of scr data */
+ err = esdhc_read_data(mmc, scr, 8U);
+ if (err != 0) {
+ return ERROR_ESDHC_COMMUNICATION_ERROR;
+ }
+
+ /* check version from SCR */
+ version = scr[0] & U(0xF);
+ if (version <= 2U) {
+ mmc->card.version = sd_versions[version];
+ } else {
+ mmc->card.version = SD_CARD_VERSION_2_0;
+ }
+
+ /* does not support switch func */
+ if (mmc->card.version == SD_CARD_VERSION_1_0) {
+ return 0;
+ }
+
+ /* read 64 bytes of status */
+ esdhc_set_data_attributes(mmc, NULL, 1U, 64U);
+
+ /* check the status of switch func */
+ for (count = 0U; count < 4U; count++) {
+ err = esdhc_send_cmd(mmc, CMD_SWITCH_FUNC,
+ SD_SWITCH_FUNC_CHECK_MODE);
+ if (err != 0) {
+ return err;
+ }
+ err = esdhc_wait_response(mmc, response);
+ if (err != 0) {
+ return err;
+ }
+ /* read 64 bytes of scr data */
+ err = esdhc_read_data(mmc, status, 64U);
+ if (err != 0) {
+ return ERROR_ESDHC_COMMUNICATION_ERROR;
+ }
+
+ if ((status[29] & SD_SWITCH_FUNC_HIGH_SPEED) == 0) {
+ break;
+ }
+ }
+
+ if ((status[13] & SD_SWITCH_FUNC_HIGH_SPEED) == 0) {
+ return 0;
+ }
+
+ /* SWITCH */
+ esdhc_set_data_attributes(mmc, NULL, 1, 64);
+ err = esdhc_send_cmd(mmc, CMD_SWITCH_FUNC, SD_SWITCH_FUNC_SWITCH_MODE);
+ if (err != 0) {
+ return err;
+ }
+ err = esdhc_wait_response(mmc, response);
+ if (err != 0) {
+ return err;
+ }
+
+ err = esdhc_read_data(mmc, status, 64U);
+ if (err != 0) {
+ return ERROR_ESDHC_COMMUNICATION_ERROR;
+ }
+
+ if ((status[16]) == U(0x01)) {
+ mmc->card.bus_freq = SD_HS_50MHZ;
+ }
+
+ return 0;
+}
+
+/***************************************************************************
+ * Function : change_state_to_transfer_state
+ * Arguments : mmc - Pointer to mmc struct
+ * Return : SUCCESS or Error Code
+ * Description : 1. Send CMD7 (CMD_SELECT_CARD) to toggles the card
+ * between stand-by and transfer state
+ * 2. Send CMD13 (CMD_SEND_STATUS) to check state as
+ * Transfer State
+ ***************************************************************************/
+static int change_state_to_transfer_state(struct mmc *mmc)
+{
+ int error = 0;
+ uint32_t response[4];
+ uint64_t start_time;
+
+ /* Command CMD_SELECT_CARD/CMD7 toggles the card between stand-by
+ * and transfer states
+ */
+ error = esdhc_send_cmd(mmc, CMD_SELECT_CARD, mmc->card.rca << 16);
+ if (error != 0) {
+ return error;
+ }
+ error = esdhc_wait_response(mmc, response);
+ if (error != 0) {
+ return error;
+ }
+
+ start_time = get_timer_val(0);
+ while (get_timer_val(start_time) < SD_TIMEOUT_HIGH) {
+ /* send CMD13 to check card status */
+ error = esdhc_send_cmd(mmc,
+ CMD_SEND_STATUS, mmc->card.rca << 16);
+ if (error != 0) {
+ return error;
+ }
+ error = esdhc_wait_response(mmc, response);
+ if ((error != 0) || ((response[0] & R1_ERROR) != 0)) {
+ return error;
+ }
+
+ /* Check for the present state of card */
+ if (((response[0] >> 9U) & U(0xF)) == STATE_TRAN) {
+ break;
+ }
+ }
+ if (((response[0] >> 9U) & U(0xF)) == STATE_TRAN) {
+ return 0;
+ } else {
+ return ERROR_ESDHC_COMMUNICATION_ERROR;
+ }
+}
+
+/***************************************************************************
+ * Function : get_cid_rca_csd
+ * Arguments : mmc - Pointer to mmc struct
+ * Return : SUCCESS or Error Code
+ * Description : 1. Send CMD2 (CMD_ALL_SEND_CID)
+ * 2. get RCA for SD cards, set rca for mmc cards
+ * Send CMD3 (CMD_SEND_RELATIVE_ADDR)
+ * 3. Send CMD9 (CMD_SEND_CSD)
+ * 4. Get MMC Version from CSD
+ ***************************************************************************/
+static int get_cid_rca_csd(struct mmc *mmc)
+{
+ int err;
+ uint32_t version;
+ uint32_t response[4];
+ uint32_t mmc_version[] = {MMC_CARD_VERSION_1_2, MMC_CARD_VERSION_1_4,
+ MMC_CARD_VERSION_2_X, MMC_CARD_VERSION_3_X,
+ MMC_CARD_VERSION_4_X};
+
+ err = esdhc_send_cmd(mmc, CMD_ALL_SEND_CID, 0);
+ if (err != 0) {
+ return err;
+ }
+ err = esdhc_wait_response(mmc, response);
+ if (err != 0) {
+ return err;
+ }
+
+ /* get RCA for SD cards, set rca for mmc cards */
+ mmc->card.rca = SD_MMC_CARD_RCA;
+
+ /* send RCA cmd */
+ err = esdhc_send_cmd(mmc, CMD_SEND_RELATIVE_ADDR, mmc->card.rca << 16);
+ if (err != 0) {
+ return err;
+ }
+ err = esdhc_wait_response(mmc, response);
+ if (err != 0) {
+ return err;
+ }
+
+ /* for SD, get the the RCA */
+ if (mmc->card.type == SD_CARD) {
+ mmc->card.rca = (response[0] >> 16) & 0xFFFF;
+ }
+
+ /* Get the CSD (card specific data) from card. */
+ err = esdhc_send_cmd(mmc, CMD_SEND_CSD, mmc->card.rca << 16);
+ if (err != 0) {
+ return err;
+ }
+ err = esdhc_wait_response(mmc, response);
+ if (err != 0) {
+ return err;
+ }
+
+ version = (response[3] >> 18U) & U(0xF);
+ if (mmc->card.type == MMC_CARD) {
+ if (version <= MMC_CARD_VERSION_4_X) {
+ mmc->card.version = mmc_version[version];
+ } else {
+ mmc->card.version = MMC_CARD_VERSION_4_X;
+ }
+ }
+
+ mmc->card.block_len = 1 << ((response[2] >> 8) & 0xF);
+
+ if (mmc->card.block_len > BLOCK_LEN_512) {
+ mmc->card.block_len = BLOCK_LEN_512;
+ }
+
+ return 0;
+}
+
+/***************************************************************************
+ * Function : identify_mmc_card
+ * Arguments : mmc - Pointer to mmc struct
+ * Return : SUCCESS or Error Code
+ * Description : 1. Send Reset Command
+ * 2. Send CMD1 with args to set voltage range and Sector
+ * Mode. (Voltage Args = 0xFF8)
+ * 3. Check the OCR Response
+ ***************************************************************************/
+static int identify_mmc_card(struct mmc *mmc)
+{
+ uint64_t start_time;
+ uint32_t resp[4];
+ int ret;
+ uint32_t args;
+
+ /* card reset */
+ ret = esdhc_send_cmd(mmc, CMD_GO_IDLE_STATE, 0U);
+ if (ret != 0) {
+ return ret;
+ }
+ ret = esdhc_wait_response(mmc, resp);
+ if (ret != 0) {
+ return ret;
+ }
+
+ /* Send CMD1 to get the ocr value repeatedly till the card */
+ /* busy is clear. timeout = 20sec */
+
+ start_time = get_timer_val(0);
+ do {
+ /* set the bits for the voltage ranges supported by host */
+ args = mmc->voltages_caps | MMC_OCR_SECTOR_MODE;
+ ret = esdhc_send_cmd(mmc, CMD_MMC_SEND_OP_COND, args);
+ if (ret != 0) {
+ return ret;
+ }
+ ret = esdhc_wait_response(mmc, resp);
+ if (ret != 0) {
+ return ERROR_ESDHC_UNUSABLE_CARD;
+ }
+ } while (((resp[0] & MMC_OCR_BUSY) == 0U) &&
+ (get_timer_val(start_time) < SD_TIMEOUT_HIGH));
+
+ if (get_timer_val(start_time) > SD_TIMEOUT_HIGH) {
+ return ERROR_ESDHC_UNUSABLE_CARD;
+ }
+
+ if ((resp[0] & MMC_OCR_CCS) == MMC_OCR_CCS) {
+ mmc->card.is_high_capacity = 1;
+ }
+
+ return MMC_CARD;
+}
+
+/***************************************************************************
+ * Function : check_for_sd_card
+ * Arguments : mmc - Pointer to mmc struct
+ * Return : SUCCESS or Error Code
+ * Description : 1. Send Reset Command
+ * 2. Send CMD8 with pattern 0xAA (to check for SD 2.0)
+ * 3. Send ACMD41 with args to set voltage range and HCS
+ * HCS is set only for SD Card > 2.0
+ * Voltage Caps = 0xFF8
+ * 4. Check the OCR Response
+ ***************************************************************************/
+static int check_for_sd_card(struct mmc *mmc)
+{
+ uint64_t start_time;
+ uint32_t args;
+ int ret;
+ uint32_t resp[4];
+
+ /* Send reset command */
+ ret = esdhc_send_cmd(mmc, CMD_GO_IDLE_STATE, 0U);
+ if (ret != 0) {
+ return ret;
+ }
+ ret = esdhc_wait_response(mmc, resp);
+ if (ret != 0) {
+ return ret;
+ }
+
+ /* send CMD8 with pattern 0xAA */
+ args = MMC_VDD_HIGH_VOLTAGE | 0xAA;
+ ret = esdhc_send_cmd(mmc, CMD_SEND_IF_COND, args);
+ if (ret != 0) {
+ return ret;
+ }
+ ret = esdhc_wait_response(mmc, resp);
+ if (ret == RESP_TIMEOUT) { /* sd ver 1.x or not sd */
+ mmc->card.is_high_capacity = 0;
+ } else if ((resp[0] & U(0xFF)) == U(0xAA)) { /* ver 2.0 or later */
+ mmc->card.version = SD_CARD_VERSION_2_0;
+ } else {
+ return NOT_SD_CARD;
+ }
+ /* Send Application command-55 to get the ocr value repeatedly till
+ * the card busy is clear. timeout = 20sec
+ */
+
+ start_time = get_timer_val(0);
+ do {
+ ret = esdhc_send_cmd(mmc, CMD_APP_CMD, 0U);
+ if (ret != 0) {
+ return ret;
+ }
+ ret = esdhc_wait_response(mmc, resp);
+ if (ret == COMMAND_ERROR) {
+ return ERROR_ESDHC_UNUSABLE_CARD;
+ }
+
+ /* set the bits for the voltage ranges supported by host */
+ args = mmc->voltages_caps;
+ if (mmc->card.version == SD_CARD_VERSION_2_0) {
+ args |= SD_OCR_HCS;
+ }
+
+ /* Send ACMD41 to set voltage range */
+ ret = esdhc_send_cmd(mmc, CMD_SD_SEND_OP_COND, args);
+ if (ret != 0) {
+ return ret;
+ }
+ ret = esdhc_wait_response(mmc, resp);
+ if (ret == COMMAND_ERROR) {
+ return ERROR_ESDHC_UNUSABLE_CARD;
+ } else if (ret == RESP_TIMEOUT) {
+ return NOT_SD_CARD;
+ }
+ } while (((resp[0] & MMC_OCR_BUSY) == 0U) &&
+ (get_timer_val(start_time) < SD_TIMEOUT_HIGH));
+
+ if (get_timer_val(start_time) > SD_TIMEOUT_HIGH) {
+ INFO("SD_TIMEOUT_HIGH\n");
+ return ERROR_ESDHC_UNUSABLE_CARD;
+ }
+
+ /* bit set in card capacity status */
+ if ((resp[0] & MMC_OCR_CCS) == MMC_OCR_CCS) {
+ mmc->card.is_high_capacity = 1;
+ }
+
+ return SD_CARD;
+}
+
+/***************************************************************************
+ * Function : esdhc_emmc_init
+ * Arguments : mmc - Pointer to mmc struct
+ * src_emmc - Flag to Indicate SRC as emmc
+ * Return : SUCCESS or Error Code (< 0)
+ * Description : Base Function called from sd_mmc_init or emmc_init
+ ***************************************************************************/
+int esdhc_emmc_init(struct mmc *mmc, bool card_detect)
+{
+ int error = 0;
+ int ret = 0;
+
+ error = esdhc_init(mmc, card_detect);
+ if (error != 0) {
+ return error;
+ }
+
+ mmc->card.bus_freq = CARD_IDENTIFICATION_FREQ;
+ mmc->card.rca = 0;
+ mmc->card.is_high_capacity = 0;
+ mmc->card.type = ERROR_ESDHC_UNUSABLE_CARD;
+
+ /* Set Voltage caps as FF8 i.e all supported */
+ /* high voltage bits 2.7 - 3.6 */
+ mmc->voltages_caps = MMC_OCR_VDD_FF8;
+
+#ifdef NXP_SD_DMA_CAPABILITY
+ /* Getting host DMA capabilities. */
+ mmc->dma_support = esdhc_in32(&mmc->esdhc_regs->hostcapblt) &
+ ESDHC_HOSTCAPBLT_DMAS;
+#else
+ mmc->dma_support = 0;
+#endif
+
+ ret = NOT_SD_CARD;
+ /* If SRC is not EMMC, check for SD or MMC */
+ ret = check_for_sd_card(mmc);
+ switch (ret) {
+ case SD_CARD:
+ mmc->card.type = SD_CARD;
+ break;
+
+ case NOT_SD_CARD:
+ /* try for MMC card */
+ if (identify_mmc_card(mmc) == MMC_CARD) {
+ mmc->card.type = MMC_CARD;
+ } else {
+ return ERROR_ESDHC_UNUSABLE_CARD;
+ }
+ break;
+
+ default:
+ return ERROR_ESDHC_UNUSABLE_CARD;
+ }
+
+ /* get CID, RCA and CSD. For MMC, set the rca */
+ error = get_cid_rca_csd(mmc);
+ if (error != 0) {
+ return ERROR_ESDHC_COMMUNICATION_ERROR;
+ }
+
+ /* change state to Transfer mode */
+ error = change_state_to_transfer_state(mmc);
+ if (error != 0) {
+ return ERROR_ESDHC_COMMUNICATION_ERROR;
+ }
+
+ /* change to high frequency if supported */
+ if (mmc->card.type == SD_CARD) {
+ error = sd_switch_to_high_freq(mmc);
+ } else {
+ error = mmc_switch_to_high_frquency(mmc);
+ }
+ if (error != 0) {
+ return ERROR_ESDHC_COMMUNICATION_ERROR;
+ }
+
+ /* mmc: 20000000, 26000000, 52000000 */
+ /* sd: 25000000, 50000000 */
+ set_speed(mmc, mmc->card.bus_freq);
+
+ INFO("init done:\n");
+ return 0;
+}
+
+/***************************************************************************
+ * Function : sd_mmc_init
+ * Arguments : mmc - Pointer to mmc struct
+ * Return : SUCCESS or Error Code
+ * Description : Base Function called via hal_init for SD/MMC
+ * initialization
+ ***************************************************************************/
+int sd_mmc_init(uintptr_t nxp_esdhc_addr, bool card_detect)
+{
+ struct mmc *mmc = NULL;
+ int ret;
+
+ mmc = &mmc_drv_data;
+ memset(mmc, 0, sizeof(struct mmc));
+ mmc->esdhc_regs = (struct esdhc_regs *)nxp_esdhc_addr;
+
+ INFO("esdhc_emmc_init\n");
+ ret = esdhc_emmc_init(mmc, card_detect);
+ return ret;
+}
+
+/***************************************************************************
+ * Function : esdhc_read_block
+ * Arguments : mmc - Pointer to mmc struct
+ * dst - Destination Pointer
+ * block - Block Number
+ * Return : SUCCESS or Error Code
+ * Description : Read a Single block to Destination Pointer
+ * 1. Send CMD16 (CMD_SET_BLOCKLEN) with args as blocklen
+ * 2. Send CMD17 (CMD_READ_SINGLE_BLOCK) with args offset
+ ***************************************************************************/
+static int esdhc_read_block(struct mmc *mmc, void *dst, uint32_t block)
+{
+ uint32_t offset;
+ int err;
+
+ /* send cmd16 to set the block size. */
+ err = esdhc_send_cmd(mmc, CMD_SET_BLOCKLEN, mmc->card.block_len);
+ if (err != 0) {
+ return err;
+ }
+ err = esdhc_wait_response(mmc, NULL);
+ if (err != 0) {
+ return ERROR_ESDHC_COMMUNICATION_ERROR;
+ }
+
+ if (mmc->card.is_high_capacity != 0) {
+ offset = block;
+ } else {
+ offset = block * mmc->card.block_len;
+ }
+
+ esdhc_set_data_attributes(mmc, dst, 1, mmc->card.block_len);
+ err = esdhc_send_cmd(mmc, CMD_READ_SINGLE_BLOCK, offset);
+ if (err != 0) {
+ return err;
+ }
+ err = esdhc_wait_response(mmc, NULL);
+ if (err != 0) {
+ return err;
+ }
+
+ err = esdhc_read_data(mmc, dst, mmc->card.block_len);
+
+ return err;
+}
+
+/***************************************************************************
+ * Function : esdhc_write_block
+ * Arguments : mmc - Pointer to mmc struct
+ * src - Source Pointer
+ * block - Block Number
+ * Return : SUCCESS or Error Code
+ * Description : Write a Single block from Source Pointer
+ * 1. Send CMD16 (CMD_SET_BLOCKLEN) with args as blocklen
+ * 2. Send CMD24 (CMD_WRITE_SINGLE_BLOCK) with args offset
+ ***************************************************************************/
+static int esdhc_write_block(struct mmc *mmc, void *src, uint32_t block)
+{
+ uint32_t offset;
+ int err;
+
+ /* send cmd16 to set the block size. */
+ err = esdhc_send_cmd(mmc, CMD_SET_BLOCKLEN, mmc->card.block_len);
+ if (err != 0) {
+ return err;
+ }
+ err = esdhc_wait_response(mmc, NULL);
+ if (err != 0) {
+ return ERROR_ESDHC_COMMUNICATION_ERROR;
+ }
+
+ if (mmc->card.is_high_capacity != 0) {
+ offset = block;
+ } else {
+ offset = block * mmc->card.block_len;
+ }
+
+ esdhc_set_data_attributes(mmc, src, 1, mmc->card.block_len);
+ err = esdhc_send_cmd(mmc, CMD_WRITE_SINGLE_BLOCK, offset);
+ if (err != 0) {
+ return err;
+ }
+ err = esdhc_wait_response(mmc, NULL);
+ if (err != 0) {
+ return err;
+ }
+
+ err = esdhc_write_data(mmc, src, mmc->card.block_len);
+
+ return err;
+}
+
+/***************************************************************************
+ * Function : esdhc_read
+ * Arguments : src_offset - offset on sd/mmc to read from. Should be block
+ * size aligned
+ * dst - Destination Pointer
+ * size - Length of Data ( Multiple of block size)
+ * Return : SUCCESS or Error Code
+ * Description : Calls esdhc_read_block repeatedly for reading the
+ * data.
+ ***************************************************************************/
+int esdhc_read(struct mmc *mmc, uint32_t src_offset, uintptr_t dst, size_t size)
+{
+ int error = 0;
+ uint32_t blk, num_blocks;
+ uint8_t *buff = (uint8_t *)dst;
+
+#ifdef NXP_SD_DEBUG
+ INFO("sd mmc read\n");
+ INFO("src = %x, dst = %lxsize = %lu\n", src_offset, dst, size);
+#endif
+
+ /* check for size */
+ if (size == 0) {
+ return 0;
+ }
+
+ if ((size % mmc->card.block_len) != 0) {
+ ERROR("Size is not block aligned\n");
+ return -1;
+ }
+
+ if ((src_offset % mmc->card.block_len) != 0) {
+ ERROR("Size is not block aligned\n");
+ return -1;
+ }
+
+ /* start block */
+ blk = src_offset / mmc->card.block_len;
+#ifdef NXP_SD_DEBUG
+ INFO("blk = %x\n", blk);
+#endif
+
+ /* Number of blocks to be read */
+ num_blocks = size / mmc->card.block_len;
+
+ while (num_blocks) {
+ error = esdhc_read_block(mmc, buff, blk);
+ if (error != 0) {
+ ERROR("Read error = %x\n", error);
+ return error;
+ }
+
+ buff = buff + mmc->card.block_len;
+ blk++;
+ num_blocks--;
+ }
+
+ INFO("sd-mmc read done.\n");
+ return error;
+}
+
+/***************************************************************************
+ * Function : esdhc_write
+ * Arguments : src - Source Pointer
+ * dst_offset - offset on sd/mmc to write to. Should be block
+ * size aligned
+ * size - Length of Data (Multiple of block size)
+ * Return : SUCCESS or Error Code
+ * Description : Calls esdhc_write_block repeatedly for writing the
+ * data.
+ ***************************************************************************/
+int esdhc_write(struct mmc *mmc, uintptr_t src, uint32_t dst_offset,
+ size_t size)
+{
+ int error = 0;
+ uint32_t blk, num_blocks;
+ uint8_t *buff = (uint8_t *)src;
+
+#ifdef NXP_SD_DEBUG
+ INFO("sd mmc write\n");
+ INFO("src = %x, dst = %lxsize = %lu\n", src, dst_offset, size);
+#endif
+
+ /* check for size */
+ if (size == 0) {
+ return 0;
+ }
+
+ if ((size % mmc->card.block_len) != 0) {
+ ERROR("Size is not block aligned\n");
+ return -1;
+ }
+
+ if ((dst_offset % mmc->card.block_len) != 0) {
+ ERROR("Size is not block aligned\n");
+ return -1;
+ }
+
+ /* start block */
+ blk = dst_offset / mmc->card.block_len;
+#ifdef NXP_SD_DEBUG
+ INFO("blk = %x\n", blk);
+#endif
+
+ /* Number of blocks to be written */
+ num_blocks = size / mmc->card.block_len;
+
+ while (num_blocks != 0U) {
+ error = esdhc_write_block(mmc, buff, blk);
+ if (error != 0U) {
+ ERROR("Write error = %x\n", error);
+ return error;
+ }
+
+ buff = buff + mmc->card.block_len;
+ blk++;
+ num_blocks--;
+ }
+
+ INFO("sd-mmc write done.\n");
+ return error;
+}
+
+static size_t ls_sd_emmc_read(int lba, uintptr_t buf, size_t size)
+{
+ struct mmc *mmc = NULL;
+ int ret;
+
+ mmc = &mmc_drv_data;
+ lba *= BLOCK_LEN_512;
+ ret = esdhc_read(mmc, lba, buf, size);
+ return ret ? 0 : size;
+}
+
+static struct io_block_dev_spec ls_emmc_dev_spec = {
+ .buffer = {
+ .offset = 0,
+ .length = 0,
+ },
+ .ops = {
+ .read = ls_sd_emmc_read,
+ },
+ .block_size = BLOCK_LEN_512,
+};
+
+int sd_emmc_init(uintptr_t *block_dev_spec,
+ uintptr_t nxp_esdhc_addr,
+ size_t nxp_sd_block_offset,
+ size_t nxp_sd_block_size,
+ bool card_detect)
+{
+ int ret;
+
+ ret = sd_mmc_init(nxp_esdhc_addr, card_detect);
+ if (ret != 0) {
+ return ret;
+ }
+
+ ls_emmc_dev_spec.buffer.offset = nxp_sd_block_offset;
+ ls_emmc_dev_spec.buffer.length = nxp_sd_block_size;
+ *block_dev_spec = (uintptr_t)&ls_emmc_dev_spec;
+
+ return 0;
+}
diff --git a/drivers/nxp/sd/sd_mmc.mk b/drivers/nxp/sd/sd_mmc.mk
new file mode 100644
index 0000000..c83b1bd
--- /dev/null
+++ b/drivers/nxp/sd/sd_mmc.mk
@@ -0,0 +1,26 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${ADD_SD_MMC},)
+
+ADD_SD_MMC := 1
+
+SD_MMC_BOOT_SOURCES += ${PLAT_DRIVERS_PATH}/sd/sd_mmc.c \
+ drivers/io/io_block.c
+
+PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLUDE_PATH)/sd
+
+ifeq (${BL_COMM_SD_MMC_NEEDED},yes)
+BL_COMMON_SOURCES += ${SD_MMC_BOOT_SOURCES}
+else
+ifeq (${BL2_SD_MMC_NEEDED},yes)
+BL2_SOURCES += ${SD_MMC_BOOT_SOURCES}
+endif
+ifeq (${BL3_SD_MMC_NEEDED},yes)
+BL31_SOURCES += ${SD_MMC_BOOT_SOURCES}
+endif
+endif
+endif
diff --git a/drivers/nxp/sec_mon/sec_mon.mk b/drivers/nxp/sec_mon/sec_mon.mk
new file mode 100644
index 0000000..aaac53f
--- /dev/null
+++ b/drivers/nxp/sec_mon/sec_mon.mk
@@ -0,0 +1,25 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${ADD_SNVS},)
+
+ADD_SNVS := 1
+
+PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLUDE_PATH)/sec_mon
+
+SNVS_SOURCES += $(PLAT_DRIVERS_PATH)/sec_mon/snvs.c
+
+ifeq (${BL_COMM_SNVS_NEEDED},yes)
+BL_COMMON_SOURCES += ${SNVS_SOURCES}
+else
+ifeq (${BL2_SNVS_NEEDED},yes)
+BL2_SOURCES += ${SNVS_SOURCES}
+endif
+ifeq (${BL31_SNVS_NEEDED},yes)
+BL31_SOURCES += ${SNVS_SOURCES}
+endif
+endif
+endif
diff --git a/drivers/nxp/sec_mon/snvs.c b/drivers/nxp/sec_mon/snvs.c
new file mode 100644
index 0000000..6208b67
--- /dev/null
+++ b/drivers/nxp/sec_mon/snvs.c
@@ -0,0 +1,186 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <snvs.h>
+
+static uintptr_t g_nxp_snvs_addr;
+
+void snvs_init(uintptr_t nxp_snvs_addr)
+{
+ g_nxp_snvs_addr = nxp_snvs_addr;
+}
+
+uint32_t get_snvs_state(void)
+{
+ struct snvs_regs *snvs = (struct snvs_regs *) (g_nxp_snvs_addr);
+
+ return (snvs_read32(&snvs->hp_stat) & HPSTS_MASK_SSM_ST);
+}
+
+static uint32_t do_snvs_state_transition(uint32_t state_transtion_bit,
+ uint32_t target_state)
+{
+ struct snvs_regs *snvs = (struct snvs_regs *) (g_nxp_snvs_addr);
+ uint32_t sts = get_snvs_state();
+ uint32_t fetch_cnt = 16U;
+ uint32_t val = snvs_read32(&snvs->hp_com) | state_transtion_bit;
+
+ snvs_write32(&snvs->hp_com, val);
+
+ /* polling loop till SNVS is in target state */
+ do {
+ sts = get_snvs_state();
+ } while ((sts != target_state) && ((--fetch_cnt) != 0));
+
+ return sts;
+}
+void transition_snvs_non_secure(void)
+{
+ struct snvs_regs *snvs = (struct snvs_regs *) (g_nxp_snvs_addr);
+ uint32_t sts = get_snvs_state();
+
+ switch (sts) {
+ /* If initial state is check or Non-Secure, then
+ * set the Software Security Violation Bit and
+ * transition to Non-Secure State.
+ */
+ case HPSTS_CHECK_SSM_ST:
+ sts = do_snvs_state_transition(HPCOM_SW_SV, HPSTS_NON_SECURE_SSM_ST);
+ break;
+
+ /* If initial state is Trusted, Secure or Soft-Fail, then
+ * first set the Software Security Violation Bit and
+ * transition to Soft-Fail State.
+ */
+ case HPSTS_TRUST_SSM_ST:
+ case HPSTS_SECURE_SSM_ST:
+ case HPSTS_SOFT_FAIL_SSM_ST:
+ sts = do_snvs_state_transition(HPCOM_SW_SV, HPSTS_NON_SECURE_SSM_ST);
+
+ /* If SSM Soft Fail to Non-Secure State Transition
+ * Disable is not set, then set SSM_ST bit and
+ * transition to Non-Secure State.
+ */
+ if ((snvs_read32(&snvs->hp_com) & HPCOM_SSM_SFNS_DIS) == 0) {
+ sts = do_snvs_state_transition(HPCOM_SSM_ST, HPSTS_NON_SECURE_SSM_ST);
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+void transition_snvs_soft_fail(void)
+{
+ do_snvs_state_transition(HPCOM_SW_FSV, HPSTS_SOFT_FAIL_SSM_ST);
+}
+
+uint32_t transition_snvs_trusted(void)
+{
+ struct snvs_regs *snvs = (struct snvs_regs *) (g_nxp_snvs_addr);
+ uint32_t sts = get_snvs_state();
+
+ switch (sts) {
+ /* If initial state is check, set the SSM_ST bit to
+ * change the state to trusted.
+ */
+ case HPSTS_CHECK_SSM_ST:
+ sts = do_snvs_state_transition(HPCOM_SSM_ST, HPSTS_TRUST_SSM_ST);
+ break;
+ /* If SSM Secure to Trusted State Transition Disable
+ * is not set, then set SSM_ST bit and
+ * transition to Trusted State.
+ */
+ case HPSTS_SECURE_SSM_ST:
+ if ((snvs_read32(&snvs->hp_com) & HPCOM_SSM_ST_DIS) == 0) {
+ sts = do_snvs_state_transition(HPCOM_SSM_ST, HPSTS_TRUST_SSM_ST);
+ }
+ break;
+ /* If initial state is Soft-Fail or Non-Secure, then
+ * transition to Trusted is not Possible.
+ */
+ default:
+ break;
+ }
+
+ return sts;
+}
+
+uint32_t transition_snvs_secure(void)
+{
+ uint32_t sts = get_snvs_state();
+
+ if (sts == HPSTS_SECURE_SSM_ST) {
+ return sts;
+ }
+
+ if (sts != HPSTS_TRUST_SSM_ST) {
+ sts = transition_snvs_trusted();
+ if (sts != HPSTS_TRUST_SSM_ST) {
+ return sts;
+ }
+ }
+
+ sts = do_snvs_state_transition(HPCOM_SSM_ST, HPSTS_TRUST_SSM_ST);
+
+ return sts;
+}
+
+void snvs_write_lp_gpr_bit(uint32_t offset, uint32_t bit_pos, bool flag_val)
+{
+ if (flag_val) {
+ snvs_write32(g_nxp_snvs_addr + offset,
+ (snvs_read32(g_nxp_snvs_addr + offset))
+ | (1 << bit_pos));
+ } else {
+ snvs_write32(g_nxp_snvs_addr + offset,
+ (snvs_read32(g_nxp_snvs_addr + offset))
+ & ~(1 << bit_pos));
+ }
+}
+
+uint32_t snvs_read_lp_gpr_bit(uint32_t offset, uint32_t bit_pos)
+{
+ return (snvs_read32(g_nxp_snvs_addr + offset) & (1 << bit_pos));
+}
+
+void snvs_disable_zeroize_lp_gpr(void)
+{
+ snvs_write_lp_gpr_bit(NXP_LPCR_OFFSET,
+ NXP_GPR_Z_DIS_BIT,
+ true);
+}
+
+#if defined(NXP_NV_SW_MAINT_LAST_EXEC_DATA) && defined(NXP_COINED_BB)
+void snvs_write_app_data_bit(uint32_t bit_pos)
+{
+ snvs_write_lp_gpr_bit(NXP_APP_DATA_LP_GPR_OFFSET,
+ bit_pos,
+ true);
+}
+
+uint32_t snvs_read_app_data(void)
+{
+ return snvs_read32(g_nxp_snvs_addr + NXP_APP_DATA_LP_GPR_OFFSET);
+}
+
+uint32_t snvs_read_app_data_bit(uint32_t bit_pos)
+{
+ uint8_t ret = snvs_read_lp_gpr_bit(NXP_APP_DATA_LP_GPR_OFFSET, bit_pos);
+
+ return ((ret != 0U) ? 1U : 0U);
+}
+
+void snvs_clear_app_data(void)
+{
+ snvs_write32(g_nxp_snvs_addr + NXP_APP_DATA_LP_GPR_OFFSET, 0x0);
+}
+#endif
diff --git a/drivers/nxp/sfp/fuse_prov.c b/drivers/nxp/sfp/fuse_prov.c
new file mode 100644
index 0000000..4d30f5f
--- /dev/null
+++ b/drivers/nxp/sfp/fuse_prov.c
@@ -0,0 +1,462 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <caam.h>
+#include <common/debug.h>
+#include <dcfg.h>
+#include <drivers/delay_timer.h>
+#include <fuse_prov.h>
+#include <sfp.h>
+#include <sfp_error_codes.h>
+
+
+static int write_a_fuse(uint32_t *fuse_addr, uint32_t *fuse_hdr_val,
+ uint32_t mask)
+{
+ uint32_t last_stored_val = sfp_read32(fuse_addr);
+
+ /* Check if fuse already blown or not */
+ if ((last_stored_val & mask) == mask) {
+ return ERROR_ALREADY_BLOWN;
+ }
+
+ /* Write fuse in mirror registers */
+ sfp_write32(fuse_addr, last_stored_val | (*fuse_hdr_val & mask));
+
+ /* Read back to check if write success */
+ if (sfp_read32(fuse_addr) != (last_stored_val | (*fuse_hdr_val & mask))) {
+ return ERROR_WRITE;
+ }
+
+ return 0;
+}
+
+static int write_fuses(uint32_t *fuse_addr, uint32_t *fuse_hdr_val, uint8_t len)
+{
+ int i;
+
+ /* Check if fuse already blown or not */
+ for (i = 0; i < len; i++) {
+ if (sfp_read32(&fuse_addr[i]) != 0) {
+ return ERROR_ALREADY_BLOWN;
+ }
+ }
+
+ /* Write fuse in mirror registers */
+ for (i = 0; i < len; i++) {
+ sfp_write32(&fuse_addr[i], fuse_hdr_val[i]);
+ }
+
+ /* Read back to check if write success */
+ for (i = 0; i < len; i++) {
+ if (sfp_read32(&fuse_addr[i]) != fuse_hdr_val[i]) {
+ return ERROR_WRITE;
+ }
+ }
+
+ return 0;
+}
+
+/*
+ * This function program Super Root Key Hash (SRKH) in fuse
+ * registers.
+ */
+static int prog_srkh(struct fuse_hdr_t *fuse_hdr,
+ struct sfp_ccsr_regs_t *sfp_ccsr_regs)
+{
+ int ret = 0;
+
+ ret = write_fuses(sfp_ccsr_regs->srk_hash, fuse_hdr->srkh, 8);
+
+ if (ret != 0) {
+ ret = (ret == ERROR_ALREADY_BLOWN) ?
+ ERROR_SRKH_ALREADY_BLOWN : ERROR_SRKH_WRITE;
+ }
+
+ return ret;
+}
+
+/* This function program OEMUID[0-4] in fuse registers. */
+static int prog_oemuid(struct fuse_hdr_t *fuse_hdr,
+ struct sfp_ccsr_regs_t *sfp_ccsr_regs)
+{
+ int i, ret = 0;
+
+ for (i = 0; i < 5; i++) {
+ /* Check OEMUIDx to be blown or not */
+ if (((fuse_hdr->flags >> (FLAG_OUID0_SHIFT + i)) & 0x1) != 0) {
+ /* Check if OEMUID[i] already blown or not */
+ ret = write_fuses(&sfp_ccsr_regs->oem_uid[i],
+ &fuse_hdr->oem_uid[i], 1);
+
+ if (ret != 0) {
+ ret = (ret == ERROR_ALREADY_BLOWN) ?
+ ERROR_OEMUID_ALREADY_BLOWN
+ : ERROR_OEMUID_WRITE;
+ }
+ }
+ }
+ return ret;
+}
+
+/* This function program DCV[0-1], DRV[0-1] in fuse registers. */
+static int prog_debug(struct fuse_hdr_t *fuse_hdr,
+ struct sfp_ccsr_regs_t *sfp_ccsr_regs)
+{
+ int ret;
+
+ /* Check DCV to be blown or not */
+ if (((fuse_hdr->flags >> (FLAG_DCV0_SHIFT)) & 0x3) != 0) {
+ /* Check if DCV[i] already blown or not */
+ ret = write_fuses(sfp_ccsr_regs->dcv, fuse_hdr->dcv, 2);
+
+ if (ret != 0) {
+ ret = (ret == ERROR_ALREADY_BLOWN) ?
+ ERROR_DCV_ALREADY_BLOWN
+ : ERROR_DCV_WRITE;
+ }
+ }
+
+ /* Check DRV to be blown or not */
+ if ((((fuse_hdr->flags >> (FLAG_DRV0_SHIFT)) & 0x3)) != 0) {
+ /* Check if DRV[i] already blown or not */
+ ret = write_fuses(sfp_ccsr_regs->drv, fuse_hdr->drv, 2);
+
+ if (ret != 0) {
+ ret = (ret == ERROR_ALREADY_BLOWN) ?
+ ERROR_DRV_ALREADY_BLOWN
+ : ERROR_DRV_WRITE;
+ } else {
+ /* Check for DRV hamming error */
+ if (sfp_read32((void *)(get_sfp_addr()
+ + SFP_SVHESR_OFFSET))
+ & SFP_SVHESR_DRV_MASK) {
+ return ERROR_DRV_HAMMING_ERROR;
+ }
+ }
+ }
+
+ return 0;
+}
+
+ /*
+ * Turn a 256-bit random value (32 bytes) into an OTPMK code word
+ * modifying the input data array in place
+ */
+static void otpmk_make_code_word_256(uint8_t *otpmk, bool minimal_flag)
+{
+ int i;
+ uint8_t parity_bit;
+ uint8_t code_bit;
+
+ if (minimal_flag == true) {
+ /*
+ * Force bits 252, 253, 254 and 255 to 1
+ * This is because these fuses may have already been blown
+ * and the OTPMK cannot force them back to 0
+ */
+ otpmk[252/8] |= (1 << (252%8));
+ otpmk[253/8] |= (1 << (253%8));
+ otpmk[254/8] |= (1 << (254%8));
+ otpmk[255/8] |= (1 << (255%8));
+ }
+
+ /* Generate the hamming code for the code word */
+ parity_bit = 0;
+ code_bit = 0;
+ for (i = 0; i < 256; i += 1) {
+ if ((otpmk[i/8] & (1 << (i%8))) != 0) {
+ parity_bit ^= 1;
+ code_bit ^= i;
+ }
+ }
+
+ /* Inverting otpmk[code_bit] will cause the otpmk
+ * to become a valid code word (except for overall parity)
+ */
+ if (code_bit < 252) {
+ otpmk[code_bit/8] ^= (1 << (code_bit % 8));
+ parity_bit ^= 1; // account for flipping a bit changing parity
+ } else {
+ /* Invert two bits: (code_bit - 4) and 4
+ * Because we invert two bits, no need to touch the parity bit
+ */
+ otpmk[(code_bit - 4)/8] ^= (1 << ((code_bit - 4) % 8));
+ otpmk[4/8] ^= (1 << (4 % 8));
+ }
+
+ /* Finally, adjust the overall parity of the otpmk
+ * otpmk bit 0
+ */
+ otpmk[0] ^= parity_bit;
+}
+
+/* This function program One Time Programmable Master Key (OTPMK)
+ * in fuse registers.
+ */
+static int prog_otpmk(struct fuse_hdr_t *fuse_hdr,
+ struct sfp_ccsr_regs_t *sfp_ccsr_regs)
+{
+ int ret = 0;
+ uint32_t otpmk_flags;
+ uint32_t otpmk_random[8] __aligned(CACHE_WRITEBACK_GRANULE);
+
+ otpmk_flags = (fuse_hdr->flags >> (FLAG_OTPMK_SHIFT)) & FLAG_OTPMK_MASK;
+
+ switch (otpmk_flags) {
+ case PROG_OTPMK_MIN:
+ memset(fuse_hdr->otpmk, 0, sizeof(fuse_hdr->otpmk));
+
+ /* Minimal OTPMK value (252-255 bits set to 1) */
+ fuse_hdr->otpmk[0] |= OTPMK_MIM_BITS_MASK;
+ break;
+
+ case PROG_OTPMK_RANDOM:
+ if (is_sec_enabled() == false) {
+ ret = ERROR_OTPMK_SEC_DISABLED;
+ goto out;
+ }
+
+ /* Generate Random number using CAAM for OTPMK */
+ memset(otpmk_random, 0, sizeof(otpmk_random));
+ if (get_rand_bytes_hw((uint8_t *)otpmk_random,
+ sizeof(otpmk_random)) != 0) {
+ ret = ERROR_OTPMK_SEC_ERROR;
+ goto out;
+ }
+
+ /* Run hamming over random no. to make OTPMK */
+ otpmk_make_code_word_256((uint8_t *)otpmk_random, false);
+
+ /* Swap OTPMK */
+ fuse_hdr->otpmk[0] = otpmk_random[7];
+ fuse_hdr->otpmk[1] = otpmk_random[6];
+ fuse_hdr->otpmk[2] = otpmk_random[5];
+ fuse_hdr->otpmk[3] = otpmk_random[4];
+ fuse_hdr->otpmk[4] = otpmk_random[3];
+ fuse_hdr->otpmk[5] = otpmk_random[2];
+ fuse_hdr->otpmk[6] = otpmk_random[1];
+ fuse_hdr->otpmk[7] = otpmk_random[0];
+ break;
+
+ case PROG_OTPMK_USER:
+ break;
+
+ case PROG_OTPMK_RANDOM_MIN:
+ /* Here assumption is that user is aware of minimal OTPMK
+ * already blown.
+ */
+
+ /* Generate Random number using CAAM for OTPMK */
+ if (is_sec_enabled() == false) {
+ ret = ERROR_OTPMK_SEC_DISABLED;
+ goto out;
+ }
+
+ memset(otpmk_random, 0, sizeof(otpmk_random));
+ if (get_rand_bytes_hw((uint8_t *)otpmk_random,
+ sizeof(otpmk_random)) != 0) {
+ ret = ERROR_OTPMK_SEC_ERROR;
+ goto out;
+ }
+
+ /* Run hamming over random no. to make OTPMK */
+ otpmk_make_code_word_256((uint8_t *)otpmk_random, true);
+
+ /* Swap OTPMK */
+ fuse_hdr->otpmk[0] = otpmk_random[7];
+ fuse_hdr->otpmk[1] = otpmk_random[6];
+ fuse_hdr->otpmk[2] = otpmk_random[5];
+ fuse_hdr->otpmk[3] = otpmk_random[4];
+ fuse_hdr->otpmk[4] = otpmk_random[3];
+ fuse_hdr->otpmk[5] = otpmk_random[2];
+ fuse_hdr->otpmk[6] = otpmk_random[1];
+ fuse_hdr->otpmk[7] = otpmk_random[0];
+ break;
+
+ case PROG_OTPMK_USER_MIN:
+ /*
+ * Here assumption is that user is aware of minimal OTPMK
+ * already blown. Check if minimal bits are set in user
+ * supplied OTPMK.
+ */
+ if ((fuse_hdr->otpmk[0] & OTPMK_MIM_BITS_MASK) !=
+ OTPMK_MIM_BITS_MASK) {
+ ret = ERROR_OTPMK_USER_MIN;
+ goto out;
+ }
+ break;
+
+ default:
+ ret = 0;
+ goto out;
+ }
+
+ ret = write_fuses(sfp_ccsr_regs->otpmk, fuse_hdr->otpmk, 8);
+
+ if (ret != 0) {
+ ret = (ret == ERROR_ALREADY_BLOWN) ?
+ ERROR_OTPMK_ALREADY_BLOWN
+ : ERROR_OTPMK_WRITE;
+ } else {
+ /* Check for DRV hamming error */
+ if ((sfp_read32((void *)(get_sfp_addr() + SFP_SVHESR_OFFSET))
+ & SFP_SVHESR_OTPMK_MASK) != 0) {
+ ret = ERROR_OTPMK_HAMMING_ERROR;
+ }
+ }
+
+out:
+ return ret;
+}
+
+/* This function program OSPR1 in fuse registers.
+ */
+static int prog_ospr1(struct fuse_hdr_t *fuse_hdr,
+ struct sfp_ccsr_regs_t *sfp_ccsr_regs)
+{
+ int ret;
+ uint32_t mask;
+
+#ifdef NXP_SFP_VER_3_4
+ if (((fuse_hdr->flags >> FLAG_MC_SHIFT) & 0x1) != 0) {
+ mask = OSPR1_MC_MASK;
+ }
+#endif
+ if (((fuse_hdr->flags >> FLAG_DBG_LVL_SHIFT) & 0x1) != 0) {
+ mask = mask | OSPR1_DBG_LVL_MASK;
+ }
+
+ ret = write_a_fuse(&sfp_ccsr_regs->ospr1, &fuse_hdr->ospr1, mask);
+
+ if (ret != 0) {
+ ret = (ret == ERROR_ALREADY_BLOWN) ?
+ ERROR_OSPR1_ALREADY_BLOWN
+ : ERROR_OSPR1_WRITE;
+ }
+
+ return ret;
+}
+
+/* This function program SYSCFG in fuse registers.
+ */
+static int prog_syscfg(struct fuse_hdr_t *fuse_hdr,
+ struct sfp_ccsr_regs_t *sfp_ccsr_regs)
+{
+ int ret;
+
+ /* Check if SYSCFG already blown or not */
+ ret = write_a_fuse(&sfp_ccsr_regs->ospr, &fuse_hdr->sc, OSPR0_SC_MASK);
+
+ if (ret != 0) {
+ ret = (ret == ERROR_ALREADY_BLOWN) ?
+ ERROR_SC_ALREADY_BLOWN
+ : ERROR_SC_WRITE;
+ }
+
+ return ret;
+}
+
+/* This function does fuse provisioning.
+ */
+int provision_fuses(unsigned long long fuse_scr_addr,
+ bool en_povdd_status)
+{
+ struct fuse_hdr_t *fuse_hdr = NULL;
+ struct sfp_ccsr_regs_t *sfp_ccsr_regs = (void *)(get_sfp_addr()
+ + SFP_FUSE_REGS_OFFSET);
+ int ret = 0;
+
+ fuse_hdr = (struct fuse_hdr_t *)fuse_scr_addr;
+
+ /*
+ * Check for Write Protect (WP) fuse. If blown then do
+ * no fuse provisioning.
+ */
+ if ((sfp_read32(&sfp_ccsr_regs->ospr) & 0x1) != 0) {
+ goto out;
+ }
+
+ /* Check if SRKH to be blown or not */
+ if (((fuse_hdr->flags >> FLAG_SRKH_SHIFT) & 0x1) != 0) {
+ INFO("Fuse: Program SRKH\n");
+ ret = prog_srkh(fuse_hdr, sfp_ccsr_regs);
+ if (ret != 0) {
+ error_handler(ret);
+ goto out;
+ }
+ }
+
+ /* Check if OEMUID to be blown or not */
+ if (((fuse_hdr->flags >> FLAG_OUID0_SHIFT) & FLAG_OUID_MASK) != 0) {
+ INFO("Fuse: Program OEMUIDs\n");
+ ret = prog_oemuid(fuse_hdr, sfp_ccsr_regs);
+ if (ret != 0) {
+ error_handler(ret);
+ goto out;
+ }
+ }
+
+ /* Check if Debug values to be blown or not */
+ if (((fuse_hdr->flags >> FLAG_DCV0_SHIFT) & FLAG_DEBUG_MASK) != 0) {
+ INFO("Fuse: Program Debug values\n");
+ ret = prog_debug(fuse_hdr, sfp_ccsr_regs);
+ if (ret != 0) {
+ error_handler(ret);
+ goto out;
+ }
+ }
+
+ /* Check if OTPMK values to be blown or not */
+ if (((fuse_hdr->flags >> FLAG_OTPMK_SHIFT) & PROG_NO_OTPMK) !=
+ PROG_NO_OTPMK) {
+ INFO("Fuse: Program OTPMK\n");
+ ret = prog_otpmk(fuse_hdr, sfp_ccsr_regs);
+ if (ret != 0) {
+ error_handler(ret);
+ goto out;
+ }
+ }
+
+
+ /* Check if MC or DBG LVL to be blown or not */
+ if ((((fuse_hdr->flags >> FLAG_MC_SHIFT) & 0x1) != 0) ||
+ (((fuse_hdr->flags >> FLAG_DBG_LVL_SHIFT) & 0x1) != 0)) {
+ INFO("Fuse: Program OSPR1\n");
+ ret = prog_ospr1(fuse_hdr, sfp_ccsr_regs);
+ if (ret != 0) {
+ error_handler(ret);
+ goto out;
+ }
+ }
+
+ /* Check if SYSCFG to be blown or not */
+ if (((fuse_hdr->flags >> FLAG_SYSCFG_SHIFT) & 0x1) != 0) {
+ INFO("Fuse: Program SYSCFG\n");
+ ret = prog_syscfg(fuse_hdr, sfp_ccsr_regs);
+ if (ret != 0) {
+ error_handler(ret);
+ goto out;
+ }
+ }
+
+ if (en_povdd_status) {
+ ret = sfp_program_fuses();
+ if (ret != 0) {
+ error_handler(ret);
+ goto out;
+ }
+ }
+out:
+ return ret;
+}
diff --git a/drivers/nxp/sfp/sfp.c b/drivers/nxp/sfp/sfp.c
new file mode 100644
index 0000000..e06c6b9
--- /dev/null
+++ b/drivers/nxp/sfp/sfp.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <caam.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <sfp.h>
+#include <sfp_error_codes.h>
+
+static uintptr_t g_nxp_sfp_addr;
+static uint32_t srk_hash[SRK_HASH_SIZE/sizeof(uint32_t)]
+ __aligned(CACHE_WRITEBACK_GRANULE);
+
+void sfp_init(uintptr_t nxp_sfp_addr)
+{
+ g_nxp_sfp_addr = nxp_sfp_addr;
+}
+
+uintptr_t get_sfp_addr(void)
+{
+ return g_nxp_sfp_addr;
+}
+
+uint32_t *get_sfp_srk_hash(void)
+{
+ struct sfp_ccsr_regs_t *sfp_ccsr_regs =
+ (void *) (g_nxp_sfp_addr + SFP_FUSE_REGS_OFFSET);
+ int i = 0;
+
+ /* Add comparison of hash with SFP hash here */
+ for (i = 0; i < SRK_HASH_SIZE/sizeof(uint32_t); i++)
+ srk_hash[i] =
+ mmio_read_32((uintptr_t)&sfp_ccsr_regs->srk_hash[i]);
+
+ return srk_hash;
+}
+
+void set_sfp_wr_disable(void)
+{
+ /*
+ * Mark SFP Write Disable and Write Disable Lock
+ * Bit to prevent write to SFP fuses like
+ * OUID's, Key Revocation fuse etc
+ */
+ void *sfpcr = (void *)(g_nxp_sfp_addr + SFP_SFPCR_OFFSET);
+ uint32_t sfpcr_val;
+
+ sfpcr_val = sfp_read32(sfpcr);
+ sfpcr_val |= (SFP_SFPCR_WD | SFP_SFPCR_WDL);
+ sfp_write32(sfpcr, sfpcr_val);
+}
+
+int sfp_program_fuses(void)
+{
+ uint32_t ingr;
+ uint32_t sfp_cmd_status = 0U;
+ int ret = 0;
+
+ /* Program SFP fuses from mirror registers */
+ sfp_write32((void *)(g_nxp_sfp_addr + SFP_INGR_OFFSET),
+ SFP_INGR_PROGFB_CMD);
+
+ /* Wait until fuse programming is successful */
+ do {
+ ingr = sfp_read32(g_nxp_sfp_addr + SFP_INGR_OFFSET);
+ } while (ingr & SFP_INGR_PROGFB_CMD);
+
+ /* Check for SFP fuse programming error */
+ sfp_cmd_status = sfp_read32(g_nxp_sfp_addr + SFP_INGR_OFFSET)
+ & SFP_INGR_ERROR_MASK;
+
+ if (sfp_cmd_status != 0U) {
+ return ERROR_PROGFB_CMD;
+ }
+
+ return ret;
+}
+
+uint32_t sfp_read_oem_uid(uint8_t oem_uid)
+{
+ uint32_t val = 0U;
+ struct sfp_ccsr_regs_t *sfp_ccsr_regs = (void *)(g_nxp_sfp_addr
+ + SFP_FUSE_REGS_OFFSET);
+
+ if (oem_uid > MAX_OEM_UID) {
+ ERROR("Invalid OEM UID received.\n");
+ return ERROR_OEMUID_WRITE;
+ }
+
+ val = sfp_read32(&sfp_ccsr_regs->oem_uid[oem_uid]);
+
+ return val;
+}
+
+/*
+ * return val: 0 - No update required.
+ * 1 - successful update done.
+ * ERROR_OEMUID_WRITE - Invalid OEM UID
+ */
+uint32_t sfp_write_oem_uid(uint8_t oem_uid, uint32_t sfp_val)
+{
+ uint32_t val = 0U;
+ struct sfp_ccsr_regs_t *sfp_ccsr_regs = (void *)(g_nxp_sfp_addr
+ + SFP_FUSE_REGS_OFFSET);
+
+ val = sfp_read_oem_uid(oem_uid);
+
+ if (val == ERROR_OEMUID_WRITE) {
+ return ERROR_OEMUID_WRITE;
+ }
+
+ /* Counter already set. No need to do anything */
+ if ((val & sfp_val) != 0U) {
+ return 0U;
+ }
+
+ val |= sfp_val;
+
+ INFO("SFP Value is %x for setting sfp_val = %d\n", val, sfp_val);
+
+ sfp_write32(&sfp_ccsr_regs->oem_uid[oem_uid], val);
+
+ return 1U;
+}
+
+int sfp_check_its(void)
+{
+ struct sfp_ccsr_regs_t *sfp_ccsr_regs = (void *)(g_nxp_sfp_addr
+ + SFP_FUSE_REGS_OFFSET);
+
+ if ((sfp_read32(&sfp_ccsr_regs->ospr) & OSPR_ITS_MASK) != 0) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+int sfp_check_oem_wp(void)
+{
+ struct sfp_ccsr_regs_t *sfp_ccsr_regs = (void *)(g_nxp_sfp_addr
+ + SFP_FUSE_REGS_OFFSET);
+
+ if ((sfp_read32(&sfp_ccsr_regs->ospr) & OSPR_WP_MASK) != 0) {
+ return 1;
+ } else {
+ return 0;
+ }
+}
+
+/* This function returns ospr's key_revoc values.*/
+uint32_t get_key_revoc(void)
+{
+ struct sfp_ccsr_regs_t *sfp_ccsr_regs = (void *)(g_nxp_sfp_addr
+ + SFP_FUSE_REGS_OFFSET);
+
+ return (sfp_read32(&sfp_ccsr_regs->ospr) & OSPR_KEY_REVOC_MASK) >>
+ OSPR_KEY_REVOC_SHIFT;
+}
diff --git a/drivers/nxp/sfp/sfp.mk b/drivers/nxp/sfp/sfp.mk
new file mode 100644
index 0000000..de708c5
--- /dev/null
+++ b/drivers/nxp/sfp/sfp.mk
@@ -0,0 +1,33 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-----------------------------------------------------------------------------
+ifeq (${SFP_ADDED},)
+
+SFP_ADDED := 1
+$(eval $(call add_define, NXP_SFP_ENABLED))
+
+PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLUDE_PATH)/sfp
+
+SFP_SOURCES += $(PLAT_DRIVERS_PATH)/sfp/sfp.c
+
+ifeq (${FUSE_PROG}, 1)
+SFP_BL2_SOURCES += $(PLAT_DRIVERS_PATH)/sfp/fuse_prov.c
+endif
+
+ifeq (${BL_COMM_SFP_NEEDED},yes)
+BL_COMMON_SOURCES += ${SFP_SOURCES}
+BL2_SOURCES += ${SFP_BL2_SOURCES}
+else
+ifeq (${BL2_SFP_NEEDED},yes)
+BL2_SOURCES += ${SFP_SOURCES}\
+ ${SFP_BL2_SOURCES}
+endif
+ifeq (${BL31_SFP_NEEDED},yes)
+BL31_SOURCES += ${SFP_SOURCES}
+endif
+endif
+endif
+#------------------------------------------------
diff --git a/drivers/nxp/timer/nxp_timer.c b/drivers/nxp/timer/nxp_timer.c
new file mode 100644
index 0000000..8eecd2e
--- /dev/null
+++ b/drivers/nxp/timer/nxp_timer.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include <nxp_timer.h>
+#include <plat/common/platform.h>
+
+static uintptr_t g_nxp_timer_addr;
+static timer_ops_t ops;
+
+uint64_t get_timer_val(uint64_t start)
+{
+ uint64_t cntpct;
+
+ isb();
+ cntpct = read_cntpct_el0();
+ return (cntpct * 1000ULL / read_cntfrq_el0() - start);
+}
+
+static uint32_t timer_get_value(void)
+{
+ uint64_t cntpct;
+
+ isb();
+ cntpct = read_cntpct_el0();
+#ifdef ERRATA_SOC_A008585
+ uint8_t max_fetch_count = 10U;
+ /* This erratum number needs to be confirmed to match ARM document */
+ uint64_t temp;
+
+ isb();
+ temp = read_cntpct_el0();
+
+ while (temp != cntpct && max_fetch_count) {
+ isb();
+ cntpct = read_cntpct_el0();
+ isb();
+ temp = read_cntpct_el0();
+ max_fetch_count--;
+ }
+#endif
+
+ /*
+ * Generic delay timer implementation expects the timer to be a down
+ * counter. We apply bitwise NOT operator to the tick values returned
+ * by read_cntpct_el0() to simulate the down counter. The value is
+ * clipped from 64 to 32 bits.
+ */
+ return (uint32_t)(~cntpct);
+}
+
+static void delay_timer_init_args(uint32_t mult, uint32_t div)
+{
+ ops.get_timer_value = timer_get_value,
+ ops.clk_mult = mult;
+ ops.clk_div = div;
+
+ timer_init(&ops);
+
+ VERBOSE("Generic delay timer configured with mult=%u and div=%u\n",
+ mult, div);
+}
+
+/*
+ * Initialise the nxp on-chip free rolling usec counter as the delay
+ * timer.
+ */
+void delay_timer_init(uintptr_t nxp_timer_addr)
+{
+ /* Value in ticks */
+ unsigned int mult = MHZ_TICKS_PER_SEC;
+
+ unsigned int div;
+
+ unsigned int counter_base_frequency = plat_get_syscnt_freq2();
+
+ g_nxp_timer_addr = nxp_timer_addr;
+ /* Rounding off the Counter Frequency to MHZ_TICKS_PER_SEC */
+ if (counter_base_frequency > MHZ_TICKS_PER_SEC) {
+ counter_base_frequency = (counter_base_frequency
+ / MHZ_TICKS_PER_SEC)
+ * MHZ_TICKS_PER_SEC;
+ } else {
+ counter_base_frequency = (counter_base_frequency
+ / KHZ_TICKS_PER_SEC)
+ * KHZ_TICKS_PER_SEC;
+ }
+
+ /* Value in ticks per second (Hz) */
+ div = counter_base_frequency;
+
+ /* Reduce multiplier and divider by dividing them repeatedly by 10 */
+ while ((mult % 10U == 0U) && (div % 10U == 0U)) {
+ mult /= 10U;
+ div /= 10U;
+ }
+
+ /* Enable and initialize the System level generic timer */
+ mmio_write_32(g_nxp_timer_addr + CNTCR_OFF,
+ CNTCR_FCREQ(0) | CNTCR_EN);
+
+ delay_timer_init_args(mult, div);
+}
+
+
+#ifdef IMAGE_BL31
+/*******************************************************************************
+ * TBD: Configures access to the system counter timer module.
+ ******************************************************************************/
+void ls_configure_sys_timer(uintptr_t ls_sys_timctl_base,
+ uint8_t ls_config_cntacr,
+ uint8_t plat_ls_ns_timer_frame_id)
+{
+ unsigned int reg_val;
+
+ if (ls_config_cntacr == 1U) {
+ reg_val = (1U << CNTACR_RPCT_SHIFT) | (1U << CNTACR_RVCT_SHIFT);
+ reg_val |= (1U << CNTACR_RFRQ_SHIFT) | (1U << CNTACR_RVOFF_SHIFT);
+ reg_val |= (1U << CNTACR_RWVT_SHIFT) | (1U << CNTACR_RWPT_SHIFT);
+ mmio_write_32(ls_sys_timctl_base +
+ CNTACR_BASE(plat_ls_ns_timer_frame_id), reg_val);
+ mmio_write_32(ls_sys_timctl_base, plat_get_syscnt_freq2());
+ }
+
+ reg_val = (1U << CNTNSAR_NS_SHIFT(plat_ls_ns_timer_frame_id));
+ mmio_write_32(ls_sys_timctl_base + CNTNSAR, reg_val);
+}
+
+void enable_init_timer(void)
+{
+ /* Enable and initialize the System level generic timer */
+ mmio_write_32(g_nxp_timer_addr + CNTCR_OFF,
+ CNTCR_FCREQ(0) | CNTCR_EN);
+}
+#endif
diff --git a/drivers/nxp/timer/timer.mk b/drivers/nxp/timer/timer.mk
new file mode 100644
index 0000000..d658d19
--- /dev/null
+++ b/drivers/nxp/timer/timer.mk
@@ -0,0 +1,25 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${ADD_TIMER},)
+
+ADD_TIMER := 1
+
+PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLUDE_PATH)/timer
+TIMER_SOURCES += drivers/delay_timer/delay_timer.c \
+ $(PLAT_DRIVERS_PATH)/timer/nxp_timer.c
+
+ifeq (${BL_COMM_TIMER_NEEDED},yes)
+BL_COMMON_SOURCES += ${TIMER_SOURCES}
+else
+ifeq (${BL2_TIMER_NEEDED},yes)
+BL2_SOURCES += ${TIMER_SOURCES}
+endif
+ifeq (${BL31_TIMER_NEEDED},yes)
+BL31_SOURCES += ${TIMER_SOURCES}
+endif
+endif
+endif
diff --git a/drivers/nxp/tzc/plat_tzc400.c b/drivers/nxp/tzc/plat_tzc400.c
new file mode 100644
index 0000000..4fe5221
--- /dev/null
+++ b/drivers/nxp/tzc/plat_tzc400.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <common/debug.h>
+
+#include <plat_tzc400.h>
+
+#pragma weak populate_tzc400_reg_list
+
+#ifdef DEFAULT_TZASC_CONFIG
+/*
+ * Typical Memory map of DRAM0
+ * |-----------NXP_NS_DRAM_ADDR ( = NXP_DRAM0_ADDR)----------|
+ * | |
+ * | |
+ * | Non-SECURE REGION |
+ * | |
+ * | |
+ * | |
+ * |------- (NXP_NS_DRAM_ADDR + NXP_NS_DRAM_SIZE - 1) -------|
+ * |-----------------NXP_SECURE_DRAM_ADDR--------------------|
+ * | |
+ * | |
+ * | |
+ * | SECURE REGION (= 64MB) |
+ * | |
+ * | |
+ * | |
+ * |--- (NXP_SECURE_DRAM_ADDR + NXP_SECURE_DRAM_SIZE - 1)----|
+ * |-----------------NXP_SP_SHRD_DRAM_ADDR-------------------|
+ * | |
+ * | Secure EL1 Payload SHARED REGION (= 2MB) |
+ * | |
+ * |-----------(NXP_DRAM0_ADDR + NXP_DRAM0_SIZE - 1)---------|
+ *
+ *
+ *
+ * Typical Memory map of DRAM1
+ * |---------------------NXP_DRAM1_ADDR----------------------|
+ * | |
+ * | |
+ * | Non-SECURE REGION |
+ * | |
+ * | |
+ * |---(NXP_DRAM1_ADDR + Dynamically calculated Size - 1) ---|
+ *
+ *
+ * Typical Memory map of DRAM2
+ * |---------------------NXP_DRAM2_ADDR----------------------|
+ * | |
+ * | |
+ * | Non-SECURE REGION |
+ * | |
+ * | |
+ * |---(NXP_DRAM2_ADDR + Dynamically calculated Size - 1) ---|
+ */
+
+/*****************************************************************************
+ * This function sets up access permissions on memory regions
+ *
+ * Input:
+ * tzc400_reg_list : TZC400 Region List
+ * dram_idx : DRAM index
+ * list_idx : TZC400 Region List Index
+ * dram_start_addr : Start address of DRAM at dram_idx.
+ * dram_size : Size of DRAM at dram_idx.
+ * secure_dram_sz : Secure DRAM Size
+ * shrd_dram_sz : Shared DRAM Size
+ *
+ * Out:
+ * list_idx : last populated index + 1
+ *
+ ****************************************************************************/
+int populate_tzc400_reg_list(struct tzc400_reg *tzc400_reg_list,
+ int dram_idx, int list_idx,
+ uint64_t dram_start_addr,
+ uint64_t dram_size,
+ uint32_t secure_dram_sz,
+ uint32_t shrd_dram_sz)
+{
+ if (list_idx == 0) {
+ /* No need to configure TZC Region 0 in this list.
+ */
+ list_idx++;
+ }
+ /* Continue with list entries for index > 0 */
+ if (dram_idx == 0) {
+ /* TZC Region 1 on DRAM0 for Secure Memory*/
+ tzc400_reg_list[list_idx].reg_filter_en = 1;
+ tzc400_reg_list[list_idx].start_addr = dram_start_addr + dram_size;
+ tzc400_reg_list[list_idx].end_addr = dram_start_addr + dram_size
+ + secure_dram_sz - 1;
+ tzc400_reg_list[list_idx].sec_attr = TZC_REGION_S_RDWR;
+ tzc400_reg_list[list_idx].nsaid_permissions = TZC_REGION_NS_NONE;
+ list_idx++;
+
+ /* TZC Region 2 on DRAM0 for Shared Memory*/
+ tzc400_reg_list[list_idx].reg_filter_en = 1;
+ tzc400_reg_list[list_idx].start_addr = dram_start_addr + dram_size
+ + secure_dram_sz;
+ tzc400_reg_list[list_idx].end_addr = dram_start_addr + dram_size
+ + secure_dram_sz
+ + shrd_dram_sz
+ - 1;
+ tzc400_reg_list[list_idx].sec_attr = TZC_REGION_S_RDWR;
+ tzc400_reg_list[list_idx].nsaid_permissions = TZC_NS_ACCESS_ID;
+ list_idx++;
+
+ /* TZC Region 3 on DRAM0 for Non-Secure Memory*/
+ tzc400_reg_list[list_idx].reg_filter_en = 1;
+ tzc400_reg_list[list_idx].start_addr = dram_start_addr;
+ tzc400_reg_list[list_idx].end_addr = dram_start_addr + dram_size
+ - 1;
+ tzc400_reg_list[list_idx].sec_attr = TZC_REGION_S_RDWR;
+ tzc400_reg_list[list_idx].nsaid_permissions = TZC_NS_ACCESS_ID;
+ list_idx++;
+ } else {
+ /* TZC Region 3+i on DRAM(> 0) for Non-Secure Memory*/
+ tzc400_reg_list[list_idx].reg_filter_en = 1;
+ tzc400_reg_list[list_idx].start_addr = dram_start_addr;
+ tzc400_reg_list[list_idx].end_addr = dram_start_addr + dram_size
+ - 1;
+ tzc400_reg_list[list_idx].sec_attr = TZC_REGION_S_RDWR;
+ tzc400_reg_list[list_idx].nsaid_permissions = TZC_NS_ACCESS_ID;
+ list_idx++;
+ }
+
+ return list_idx;
+}
+#else
+int populate_tzc400_reg_list(struct tzc400_reg *tzc400_reg_list,
+ int dram_idx, int list_idx,
+ uint64_t dram_start_addr,
+ uint64_t dram_size,
+ uint32_t secure_dram_sz,
+ uint32_t shrd_dram_sz)
+{
+ ERROR("tzc400_reg_list used is not a default list\n");
+ ERROR("%s needs to be over-written.\n", __func__);
+ return 0;
+}
+#endif /* DEFAULT_TZASC_CONFIG */
+
+/*******************************************************************************
+ * Configure memory access permissions
+ * - Region 0 with no access;
+ * - Region 1 to 4 as per the tzc400_reg_list populated by
+ * function populate_tzc400_reg_list() with default for all the SoC.
+ ******************************************************************************/
+void mem_access_setup(uintptr_t base, uint32_t total_regions,
+ struct tzc400_reg *tzc400_reg_list)
+{
+ uint32_t list_indx = 0U;
+
+ INFO("Configuring TrustZone Controller\n");
+
+ tzc400_init(base);
+
+ /* Disable filters. */
+ tzc400_disable_filters();
+
+ /* Region 0 set to no access by default */
+ tzc400_configure_region0(TZC_REGION_S_NONE, 0U);
+
+ for (list_indx = 1U; list_indx < total_regions; list_indx++) {
+ tzc400_configure_region(
+ tzc400_reg_list[list_indx].reg_filter_en,
+ list_indx,
+ tzc400_reg_list[list_indx].start_addr,
+ tzc400_reg_list[list_indx].end_addr,
+ tzc400_reg_list[list_indx].sec_attr,
+ tzc400_reg_list[list_indx].nsaid_permissions);
+ }
+
+ /*
+ * Raise an exception if a NS device tries to access secure memory
+ * TODO: Add interrupt handling support.
+ */
+ tzc400_set_action(TZC_ACTION_ERR);
+
+ /* Enable filters. */
+ tzc400_enable_filters();
+}
diff --git a/drivers/nxp/tzc/tzc.mk b/drivers/nxp/tzc/tzc.mk
new file mode 100644
index 0000000..3fba28f
--- /dev/null
+++ b/drivers/nxp/tzc/tzc.mk
@@ -0,0 +1,33 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq (${ADD_TZASC},)
+
+ADD_TZASC := 1
+
+PLAT_INCLUDES += -I$(PLAT_DRIVERS_INCLUDE_PATH)/tzc
+
+ifeq ($(TZC_ID), TZC400)
+TZASC_SOURCES += drivers/arm/tzc/tzc400.c\
+ $(PLAT_DRIVERS_PATH)/tzc/plat_tzc400.c
+else ifeq ($(TZC_ID), NONE)
+ $(info -> No TZC present on platform)
+else
+ $(error -> TZC type not set!)
+endif
+
+ifeq (${BL_COMM_TZASC_NEEDED},yes)
+BL_COMMON_SOURCES += ${TZASC_SOURCES}
+else
+ifeq (${BL2_TZASC_NEEDED},yes)
+BL2_SOURCES += ${TZASC_SOURCES}
+endif
+ifeq (${BL31_TZASC_NEEDED},yes)
+BL31_SOURCES += ${TZASC_SOURCES}
+endif
+endif
+
+endif
diff --git a/drivers/rambus/trng_ip_76.c b/drivers/rambus/trng_ip_76.c
new file mode 100644
index 0000000..8de12e9
--- /dev/null
+++ b/drivers/rambus/trng_ip_76.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2020, Marvell Technology Group Ltd. All rights reserved.
+ *
+ * Based on Linux kernel omap-rng.c - RNG driver for TI OMAP CPU family
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2005 (c) MontaVista Software, Inc.
+ *
+ * Mostly based on original driver:
+ *
+ * Copyright (C) 2005 Nokia Corporation
+ * Author: Juha Yrjölä <juha.yrjola@nokia.com>
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <drivers/rambus/trng_ip_76.h>
+#include <lib/mmio.h>
+#include <lib/spinlock.h>
+#include <lib/utils.h>
+
+#define RNG_REG_STATUS_RDY (1 << 0)
+
+#define RNG_REG_INTACK_RDY_MASK (1 << 0)
+
+#define RNG_CONTROL_ENABLE_TRNG_MASK (1 << 10)
+
+#define RNG_CONFIG_NOISE_BLOCKS(val) ((0xff & (val)) << 0)
+#define RNG_CONFIG_NOISE_BLK_VAL 0x5
+
+#define RNG_CONFIG_SAMPLE_CYCLES(val) ((0xff & (val)) << 16)
+#define RNG_CONFIG_SAMPLE_CYCLES_VAL 0x22
+
+#define RNG_REG_FRO_ENABLE_MASK 0xffffff
+#define RNG_REG_FRO_DETUNE_MASK 0x0
+
+#define EIP76_RNG_OUTPUT_SIZE 0x10
+#define EIP76_RNG_WAIT_ROUNDS 10
+
+#define RNG_HW_IS_EIP76(ver) ((ver) & (0xff == 0x4C))
+#define RNG_HW_VER_MAJOR(ver) (((ver) & (0xf << 24)) >> 24)
+#define RNG_HW_VER_MINOR(ver) (((ver) & (0xf << 20)) >> 20)
+#define RNG_HW_VER_PATCH(ver) (((ver) & (0xf << 16)) >> 16)
+
+
+enum {
+ RNG_OUTPUT_0_REG = 0,
+ RNG_OUTPUT_1_REG,
+ RNG_OUTPUT_2_REG,
+ RNG_OUTPUT_3_REG,
+ RNG_STATUS_REG,
+ RNG_INTMASK_REG,
+ RNG_INTACK_REG,
+ RNG_CONTROL_REG,
+ RNG_CONFIG_REG,
+ RNG_ALARMCNT_REG,
+ RNG_FROENABLE_REG,
+ RNG_FRODETUNE_REG,
+ RNG_ALARMMASK_REG,
+ RNG_ALARMSTOP_REG,
+ RNG_REV_REG
+};
+
+static uint16_t reg_map_eip76[] = {
+ [RNG_OUTPUT_0_REG] = 0x0,
+ [RNG_OUTPUT_1_REG] = 0x4,
+ [RNG_OUTPUT_2_REG] = 0x8,
+ [RNG_OUTPUT_3_REG] = 0xc,
+ [RNG_STATUS_REG] = 0x10,
+ [RNG_INTACK_REG] = 0x10,
+ [RNG_CONTROL_REG] = 0x14,
+ [RNG_CONFIG_REG] = 0x18,
+ [RNG_ALARMCNT_REG] = 0x1c,
+ [RNG_FROENABLE_REG] = 0x20,
+ [RNG_FRODETUNE_REG] = 0x24,
+ [RNG_ALARMMASK_REG] = 0x28,
+ [RNG_ALARMSTOP_REG] = 0x2c,
+ [RNG_REV_REG] = 0x7c,
+};
+
+struct eip76_rng_dev {
+ uintptr_t base;
+ uint16_t *regs;
+};
+
+/* Locals */
+static struct eip76_rng_dev eip76_dev;
+static spinlock_t rng_lock;
+
+static inline uint32_t eip76_rng_read(struct eip76_rng_dev *dev, uint16_t reg)
+{
+ return mmio_read_32(dev->base + dev->regs[reg]);
+}
+
+static inline void eip76_rng_write(struct eip76_rng_dev *dev,
+ uint16_t reg, uint32_t val)
+{
+ mmio_write_32(dev->base + dev->regs[reg], val);
+}
+
+static void eip76_rng_init(struct eip76_rng_dev *dev)
+{
+ uint32_t val;
+
+ /* Return if RNG is already running. */
+ if (eip76_rng_read(dev, RNG_CONTROL_REG) &
+ RNG_CONTROL_ENABLE_TRNG_MASK) {
+ return;
+ }
+
+ /* This field sets the number of 512-bit blocks of raw Noise Source
+ * output data that must be processed by either the Conditioning
+ * Function or the SP 800-90 DRBG ‘BC_DF’ functionality to yield
+ * a ‘full entropy’ output value. As according to [SP 800-90B draft]
+ * the amount of entropy input to this functionality must be twice
+ * the amount that is output and the 8-bit samples output by the Noise
+ * Source are supposed to have one bit of entropy each, the settings
+ * for this field are as follows:
+ * - SHA-1 Conditioning Function:
+ * generates 160 bits output, requiring 2560 sample bits,
+ * equivalent to 5 blocks of raw Noise Source input.
+ * - SHA-256 Conditioning Function:
+ * generates 256 bits output, requiring 4096 sample bits, equivalent
+ * to 8 blocks of raw Noise Source input. Note that two blocks of 256
+ * bits are needed to start or re-seed the SP 800-90 DRBG
+ * (in the EIP-76d-*-SHA2 configurations)
+ * - SP 800-90 DRBG ‘BC_DF’ functionality:
+ * generates 384 bits output, requiring 6144 sample bits, equivalent
+ * to 12 blocks of raw Noise Source input.
+ * This field can only be modified when ‘enable_trng’ in TRNG_CONTROL
+ * is ‘0’ or when either of the ‘test_known_noise’ or ‘test_cond_func’
+ * bits in TRNG_TEST is ‘1’. Value 0 in this field selects 256 blocks
+ * of 512 bits to be processed.
+ */
+ val = RNG_CONFIG_NOISE_BLOCKS(RNG_CONFIG_NOISE_BLK_VAL);
+
+ /* This field sets the number of FRO samples that are XOR-ed together
+ * into one bit to be shifted into the main shift register.
+ * This value must be such that there is at least one bit of entropy
+ * (in total) in each 8 bits that are shifted.
+ * This field can only be modified when ‘enable_trng’ in TRNG_CONTROL
+ * is ‘0’ or when either of the ‘test_known_noise’ or ‘test_cond_func’
+ * bits in TRNG_TEST is ‘1’. Value 0 in this field selects 65536 FRO
+ * samples to be XOR-ed together
+ */
+ val |= RNG_CONFIG_SAMPLE_CYCLES(RNG_CONFIG_SAMPLE_CYCLES_VAL);
+ eip76_rng_write(dev, RNG_CONFIG_REG, val);
+
+ /* Enable all available FROs */
+ eip76_rng_write(dev, RNG_FRODETUNE_REG, RNG_REG_FRO_DETUNE_MASK);
+ eip76_rng_write(dev, RNG_FROENABLE_REG, RNG_REG_FRO_ENABLE_MASK);
+
+ /* Enable TRNG */
+ eip76_rng_write(dev, RNG_CONTROL_REG, RNG_CONTROL_ENABLE_TRNG_MASK);
+}
+
+int32_t eip76_rng_read_rand_buf(void *data, bool wait)
+{
+ uint32_t i, present;
+
+ if (!eip76_dev.base) /* not initialized */
+ return -1;
+
+ for (i = 0; i < EIP76_RNG_WAIT_ROUNDS; i++) {
+ present = eip76_rng_read(&eip76_dev, RNG_STATUS_REG) &
+ RNG_REG_STATUS_RDY;
+ if (present || !wait) {
+ break;
+ }
+
+ udelay(10);
+ }
+
+ if (present != 0U) {
+ return 0;
+ }
+
+ memcpy(data,
+ (void *)(eip76_dev.base + eip76_dev.regs[RNG_OUTPUT_0_REG]),
+ EIP76_RNG_OUTPUT_SIZE);
+
+ eip76_rng_write(&eip76_dev, RNG_INTACK_REG, RNG_REG_INTACK_RDY_MASK);
+
+ return EIP76_RNG_OUTPUT_SIZE;
+}
+
+int32_t eip76_rng_probe(uintptr_t base_addr)
+{
+ uint32_t ver;
+
+ eip76_dev.base = base_addr;
+ eip76_dev.regs = reg_map_eip76;
+
+ eip76_rng_init(&eip76_dev);
+
+ ver = eip76_rng_read(&eip76_dev, RNG_REV_REG);
+
+ INFO("%s Random Number Generator HW ver. %01x.%01x.%01x\n",
+ RNG_HW_IS_EIP76(ver) ? "TRNG-IP-76" : "Unknown",
+ RNG_HW_VER_MAJOR(ver), RNG_HW_VER_MINOR(ver),
+ RNG_HW_VER_PATCH(ver));
+
+ return 0;
+}
+
+int32_t eip76_rng_get_random(uint8_t *data, uint32_t len)
+{
+ static uint8_t rand[EIP76_RNG_OUTPUT_SIZE];
+ static uint8_t pos;
+ uint32_t i;
+ int32_t ret = 0;
+
+ if (!data)
+ return -1;
+
+ spin_lock(&rng_lock);
+
+ for (i = 0; i < len; i++) {
+ if (pos >= EIP76_RNG_OUTPUT_SIZE) {
+ pos = 0;
+ }
+
+ if (pos != 0U) {
+ ret = eip76_rng_read_rand_buf(rand, true);
+ }
+
+ /* Only advance FIFO index if it is non zero or
+ * the update from TRNG HW was successful
+ */
+ if (pos || ret > 0) {
+ data[i] = rand[pos++];
+ ret = 0;
+ } else {
+ ret = -1;
+ break;
+ }
+ }
+
+ spin_unlock(&rng_lock);
+
+ return ret;
+}
diff --git a/drivers/renesas/common/common.c b/drivers/renesas/common/common.c
index 9b7c1eb..a0aa480 100644
--- a/drivers/renesas/common/common.c
+++ b/drivers/renesas/common/common.c
@@ -1,11 +1,12 @@
/*
- * Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <lib/mmio.h>
+#include "cpg_registers.h"
#include "rcar_private.h"
#if IMAGE_BL31
@@ -16,7 +17,7 @@
{
uint32_t value = regval;
- mmio_write_32((uintptr_t) RCAR_CPGWPR, ~value);
+ mmio_write_32(CPG_CPGWPR, ~value);
mmio_write_32(regadr, value);
}
diff --git a/drivers/renesas/rcar/ddr/boot_init_dram.h b/drivers/renesas/common/ddr/boot_init_dram.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/boot_init_dram.h
rename to drivers/renesas/common/ddr/boot_init_dram.h
diff --git a/drivers/renesas/common/ddr/ddr.mk b/drivers/renesas/common/ddr/ddr.mk
new file mode 100644
index 0000000..9483686
--- /dev/null
+++ b/drivers/renesas/common/ddr/ddr.mk
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq ($(RCAR_LSI),$(filter $(RCAR_LSI),${RCAR_E3} ${RZ_G2E}))
+ include drivers/renesas/common/ddr/ddr_a/ddr_a.mk
+ BL2_SOURCES += drivers/renesas/common/ddr/dram_sub_func.c
+else ifeq (${RCAR_LSI},${RCAR_D3})
+ include drivers/renesas/common/ddr/ddr_a/ddr_a.mk
+else ifeq (${RCAR_LSI},${RCAR_V3M})
+ include drivers/renesas/common/ddr/ddr_a/ddr_a.mk
+else
+ include drivers/renesas/common/ddr/ddr_b/ddr_b.mk
+ BL2_SOURCES += drivers/renesas/common/ddr/dram_sub_func.c
+endif
diff --git a/drivers/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h b/drivers/renesas/common/ddr/ddr_a/boot_init_dram_regdef.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_a/boot_init_dram_regdef.h
rename to drivers/renesas/common/ddr/ddr_a/boot_init_dram_regdef.h
diff --git a/drivers/renesas/common/ddr/ddr_a/ddr_a.mk b/drivers/renesas/common/ddr/ddr_a/ddr_a.mk
new file mode 100644
index 0000000..cd6433d
--- /dev/null
+++ b/drivers/renesas/common/ddr/ddr_a/ddr_a.mk
@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq ($(RCAR_LSI),$(filter $(RCAR_LSI),${RCAR_E3} ${RZ_G2E}))
+BL2_SOURCES += drivers/renesas/common/ddr/ddr_a/ddr_init_e3.c
+else ifeq (${RCAR_LSI},${RCAR_D3})
+BL2_SOURCES += drivers/renesas/common/ddr/ddr_a/ddr_init_d3.c
+else
+BL2_SOURCES += drivers/renesas/common/ddr/ddr_a/ddr_init_v3m.c
+endif
diff --git a/drivers/renesas/rcar/ddr/ddr_a/ddr_init_d3.c b/drivers/renesas/common/ddr/ddr_a/ddr_init_d3.c
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
rename to drivers/renesas/common/ddr/ddr_a/ddr_init_d3.c
diff --git a/drivers/renesas/rcar/ddr/ddr_a/ddr_init_e3.c b/drivers/renesas/common/ddr/ddr_a/ddr_init_e3.c
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
rename to drivers/renesas/common/ddr/ddr_a/ddr_init_e3.c
diff --git a/drivers/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c b/drivers/renesas/common/ddr/ddr_a/ddr_init_v3m.c
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
rename to drivers/renesas/common/ddr/ddr_a/ddr_init_v3m.c
diff --git a/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c b/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c
new file mode 100644
index 0000000..8d002de
--- /dev/null
+++ b/drivers/renesas/common/ddr/ddr_b/boot_init_dram.c
@@ -0,0 +1,4484 @@
+/*
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <stdio.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include "ddr_regdef.h"
+#include "init_dram_tbl_h3.h"
+#include "init_dram_tbl_m3.h"
+#include "init_dram_tbl_h3ver2.h"
+#include "init_dram_tbl_m3n.h"
+#include "boot_init_dram_regdef.h"
+#include "boot_init_dram.h"
+#include "dram_sub_func.h"
+#include "micro_delay.h"
+#include "rcar_def.h"
+
+#define DDR_BACKUPMODE
+#define FATAL_MSG(x) NOTICE(x)
+
+/* variables */
+#ifdef RCAR_DDR_FIXED_LSI_TYPE
+#ifndef RCAR_AUTO
+#define RCAR_AUTO 99
+#define RCAR_H3 0
+#define RCAR_M3 1
+#define RCAR_M3N 2
+#define RCAR_E3 3 /* NON */
+#define RCAR_H3N 4
+
+#define RZ_G2M 100U
+#define RZ_G2H 101U
+#define RZ_G2N 102U
+
+#define RCAR_CUT_10 0
+#define RCAR_CUT_11 1
+#define RCAR_CUT_20 10
+#define RCAR_CUT_30 20
+#endif
+#ifndef RCAR_LSI
+#define RCAR_LSI RCAR_AUTO
+#endif
+
+#if (RCAR_LSI == RCAR_AUTO)
+static uint32_t prr_product;
+static uint32_t prr_cut;
+#else
+#if (RCAR_LSI == RCAR_H3)
+static const uint32_t prr_product = PRR_PRODUCT_H3;
+#elif(RCAR_LSI == RCAR_M3 || RCAR_LSI == RZ_G2M)
+static const uint32_t prr_product = PRR_PRODUCT_M3;
+#elif(RCAR_LSI == RCAR_M3N || RCAR_LSI == RZ_G2N)
+static const uint32_t prr_product = PRR_PRODUCT_M3N;
+#elif(RCAR_LSI == RCAR_H3N || RCAR_LSI == RZ_G2H)
+static const uint32_t prr_product = PRR_PRODUCT_H3;
+#endif /* RCAR_LSI */
+
+#ifndef RCAR_LSI_CUT
+static uint32_t prr_cut;
+#else /* RCAR_LSI_CUT */
+#if (RCAR_LSI_CUT == RCAR_CUT_10)
+static const uint32_t prr_cut = PRR_PRODUCT_10;
+#elif(RCAR_LSI_CUT == RCAR_CUT_11)
+static const uint32_t prr_cut = PRR_PRODUCT_11;
+#elif(RCAR_LSI_CUT == RCAR_CUT_20)
+static const uint32_t prr_cut = PRR_PRODUCT_20;
+#elif(RCAR_LSI_CUT == RCAR_CUT_30)
+static const uint32_t prr_cut = PRR_PRODUCT_30;
+#endif /* RCAR_LSI_CUT */
+#endif /* RCAR_LSI_CUT */
+#endif /* RCAR_AUTO_NON */
+#else /* RCAR_DDR_FIXED_LSI_TYPE */
+static uint32_t prr_product;
+static uint32_t prr_cut;
+#endif /* RCAR_DDR_FIXED_LSI_TYPE */
+
+static const uint32_t *p_ddr_regdef_tbl;
+static uint32_t brd_clk;
+static uint32_t brd_clkdiv;
+static uint32_t brd_clkdiva;
+static uint32_t ddr_mbps;
+static uint32_t ddr_mbpsdiv;
+static uint32_t ddr_tccd;
+static uint32_t ddr_phycaslice;
+static const struct _boardcnf *board_cnf;
+static uint32_t ddr_phyvalid;
+static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT];
+static uint32_t ch_have_this_cs[CS_CNT] __aligned(64);
+static uint32_t rdqdm_dly[DRAM_CH_CNT][CSAB_CNT][SLICE_CNT * 2][9];
+static uint32_t max_density;
+static uint32_t ddr0800_mul;
+static uint32_t ddr_mul;
+static uint32_t DDR_PHY_SLICE_REGSET_OFS;
+static uint32_t DDR_PHY_ADR_V_REGSET_OFS;
+static uint32_t DDR_PHY_ADR_I_REGSET_OFS;
+static uint32_t DDR_PHY_ADR_G_REGSET_OFS;
+static uint32_t DDR_PI_REGSET_OFS;
+static uint32_t DDR_PHY_SLICE_REGSET_SIZE;
+static uint32_t DDR_PHY_ADR_V_REGSET_SIZE;
+static uint32_t DDR_PHY_ADR_I_REGSET_SIZE;
+static uint32_t DDR_PHY_ADR_G_REGSET_SIZE;
+static uint32_t DDR_PI_REGSET_SIZE;
+static uint32_t DDR_PHY_SLICE_REGSET_NUM;
+static uint32_t DDR_PHY_ADR_V_REGSET_NUM;
+static uint32_t DDR_PHY_ADR_I_REGSET_NUM;
+static uint32_t DDR_PHY_ADR_G_REGSET_NUM;
+static uint32_t DDR_PI_REGSET_NUM;
+static uint32_t DDR_PHY_ADR_I_NUM;
+#define DDR_PHY_REGSET_MAX 128
+#define DDR_PI_REGSET_MAX 320
+static uint32_t _cnf_DDR_PHY_SLICE_REGSET[DDR_PHY_REGSET_MAX];
+static uint32_t _cnf_DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX];
+static uint32_t _cnf_DDR_PHY_ADR_I_REGSET[DDR_PHY_REGSET_MAX];
+static uint32_t _cnf_DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX];
+static uint32_t _cnf_DDR_PI_REGSET[DDR_PI_REGSET_MAX];
+static uint32_t pll3_mode;
+static uint32_t loop_max;
+#ifdef DDR_BACKUPMODE
+uint32_t ddr_backup;
+/* #define DDR_BACKUPMODE_HALF //for Half channel(ch0,1 only) */
+#endif
+
+#ifdef ddr_qos_init_setting /* only for non qos_init */
+#define OPERATING_FREQ (400U) /* Mhz */
+#define BASE_SUB_SLOT_NUM (0x6U)
+#define SUB_SLOT_CYCLE (0x7EU) /* 126 */
+#define QOSWT_WTSET0_CYCLE \
+ ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / \
+ OPERATING_FREQ) /* unit:ns */
+
+uint32_t get_refperiod(void)
+{
+ return QOSWT_WTSET0_CYCLE;
+}
+#else /* ddr_qos_init_setting // only for non qos_init */
+extern uint32_t get_refperiod(void);
+#endif /* ddr_qos_init_setting // only for non qos_init */
+
+#define _reg_PHY_RX_CAL_X_NUM 11
+static const uint32_t _reg_PHY_RX_CAL_X[_reg_PHY_RX_CAL_X_NUM] = {
+ _reg_PHY_RX_CAL_DQ0,
+ _reg_PHY_RX_CAL_DQ1,
+ _reg_PHY_RX_CAL_DQ2,
+ _reg_PHY_RX_CAL_DQ3,
+ _reg_PHY_RX_CAL_DQ4,
+ _reg_PHY_RX_CAL_DQ5,
+ _reg_PHY_RX_CAL_DQ6,
+ _reg_PHY_RX_CAL_DQ7,
+ _reg_PHY_RX_CAL_DM,
+ _reg_PHY_RX_CAL_DQS,
+ _reg_PHY_RX_CAL_FDBK
+};
+
+#define _reg_PHY_CLK_WRX_SLAVE_DELAY_NUM 10
+static const uint32_t _reg_PHY_CLK_WRX_SLAVE_DELAY
+ [_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = {
+ _reg_PHY_CLK_WRDQ0_SLAVE_DELAY,
+ _reg_PHY_CLK_WRDQ1_SLAVE_DELAY,
+ _reg_PHY_CLK_WRDQ2_SLAVE_DELAY,
+ _reg_PHY_CLK_WRDQ3_SLAVE_DELAY,
+ _reg_PHY_CLK_WRDQ4_SLAVE_DELAY,
+ _reg_PHY_CLK_WRDQ5_SLAVE_DELAY,
+ _reg_PHY_CLK_WRDQ6_SLAVE_DELAY,
+ _reg_PHY_CLK_WRDQ7_SLAVE_DELAY,
+ _reg_PHY_CLK_WRDM_SLAVE_DELAY,
+ _reg_PHY_CLK_WRDQS_SLAVE_DELAY
+};
+
+#define _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM 9
+static const uint32_t _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY
+ [_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = {
+ _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY
+};
+
+#define _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM 9
+static const uint32_t _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY
+ [_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = {
+ _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY,
+ _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY
+};
+
+#define _reg_PHY_PAD_TERM_X_NUM 8
+static const uint32_t _reg_PHY_PAD_TERM_X[_reg_PHY_PAD_TERM_X_NUM] = {
+ _reg_PHY_PAD_FDBK_TERM,
+ _reg_PHY_PAD_DATA_TERM,
+ _reg_PHY_PAD_DQS_TERM,
+ _reg_PHY_PAD_ADDR_TERM,
+ _reg_PHY_PAD_CLK_TERM,
+ _reg_PHY_PAD_CKE_TERM,
+ _reg_PHY_PAD_RST_TERM,
+ _reg_PHY_PAD_CS_TERM
+};
+
+#define _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM 10
+static const uint32_t _reg_PHY_CLK_CACS_SLAVE_DELAY_X
+ [_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = {
+ _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY,
+ _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY,
+ _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY,
+ _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY,
+ _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY,
+ _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY,
+
+ _reg_PHY_GRP_SLAVE_DELAY_0,
+ _reg_PHY_GRP_SLAVE_DELAY_1,
+ _reg_PHY_GRP_SLAVE_DELAY_2,
+ _reg_PHY_GRP_SLAVE_DELAY_3
+};
+
+/* Prototypes */
+static inline uint32_t vch_nxt(uint32_t pos);
+static void cpg_write_32(uint32_t a, uint32_t v);
+static void pll3_control(uint32_t high);
+static inline void dsb_sev(void);
+static void wait_dbcmd(void);
+static void send_dbcmd(uint32_t cmd);
+static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd);
+static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata);
+static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata);
+static inline uint32_t ddr_regdef(uint32_t _regdef);
+static inline uint32_t ddr_regdef_adr(uint32_t _regdef);
+static inline uint32_t ddr_regdef_lsb(uint32_t _regdef);
+static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
+ uint32_t val);
+static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef);
+static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val);
+static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val);
+static void ddr_setval_ach(uint32_t regdef, uint32_t val);
+static void ddr_setval_ach_as(uint32_t regdef, uint32_t val);
+static uint32_t ddr_getval(uint32_t ch, uint32_t regdef);
+static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p);
+static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p);
+static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size);
+static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val);
+static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef);
+static uint32_t ddrphy_regif_chk(void);
+static inline void ddrphy_regif_idle(void);
+static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps,
+ uint16_t cyc);
+static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv,
+ uint16_t *_js2);
+static int16_t _f_scale_adj(int16_t ps);
+static void ddrtbl_load(void);
+static void ddr_config_sub(void);
+static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz);
+static void ddr_config_sub_h3v1x(void);
+static void ddr_config(void);
+static void dbsc_regset(void);
+static void dbsc_regset_post(void);
+static uint32_t dfi_init_start(void);
+static void change_lpddr4_en(uint32_t mode);
+static uint32_t set_term_code(void);
+static void ddr_register_set(void);
+static inline uint32_t wait_freqchgreq(uint32_t assert);
+static inline void set_freqchgack(uint32_t assert);
+static inline void set_dfifrequency(uint32_t freq);
+static uint32_t pll3_freq(uint32_t on);
+static void update_dly(void);
+static uint32_t pi_training_go(void);
+static uint32_t init_ddr(void);
+static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick);
+static uint32_t wdqdm_man1(void);
+static uint32_t wdqdm_man(void);
+static uint32_t rdqdm_man1(void);
+static uint32_t rdqdm_man(void);
+
+static int32_t _find_change(uint64_t val, uint32_t dir);
+static uint32_t _rx_offset_cal_updn(uint32_t code);
+static uint32_t rx_offset_cal(void);
+static uint32_t rx_offset_cal_hw(void);
+static void adjust_rddqs_latency(void);
+static void adjust_wpath_latency(void);
+
+struct ddrt_data {
+ int32_t init_temp; /* Initial Temperature (do) */
+ uint32_t init_cal[4]; /* Initial io-code (4 is for H3) */
+ uint32_t tcomp_cal[4]; /* Temp. compensated io-code (4 is for H3) */
+};
+
+static struct ddrt_data tcal;
+
+static void pvtcode_update(void);
+static void pvtcode_update2(void);
+static void ddr_padcal_tcompensate_getinit(uint32_t override);
+
+/* load board configuration */
+#include "boot_init_dram_config.c"
+
+#ifndef DDR_FAST_INIT
+static uint32_t rdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
+static uint32_t rdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
+static uint32_t rdqdm_nw[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
+static uint32_t rdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
+static uint32_t rdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2];
+static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
+static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
+
+static uint32_t wdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9];
+static uint32_t wdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9];
+static uint32_t wdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9];
+static uint32_t wdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
+static uint32_t wdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
+static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
+static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
+#endif/* DDR_FAST_INIT */
+
+/* macro for channel selection loop */
+static inline uint32_t vch_nxt(uint32_t pos)
+{
+ uint32_t posn;
+
+ for (posn = pos; posn < DRAM_CH_CNT; posn++) {
+ if (ddr_phyvalid & (1U << posn))
+ break;
+ }
+ return posn;
+}
+
+#define foreach_vch(ch) \
+for (ch = vch_nxt(0); ch < DRAM_CH_CNT; ch = vch_nxt(ch + 1))
+
+#define foreach_ech(ch) \
+for (ch = 0; ch < DRAM_CH_CNT; ch++)
+
+/* Printing functions */
+#define MSG_LF(...)
+
+/* clock settings, reset control */
+static void cpg_write_32(uint32_t a, uint32_t v)
+{
+ mmio_write_32(CPG_CPGWPR, ~v);
+ mmio_write_32(a, v);
+}
+
+static void pll3_control(uint32_t high)
+{
+ uint32_t data_l, data_div, data_mul, tmp_div;
+
+ if (high) {
+ tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
+ (brd_clk * ddr_mul) / 2;
+ data_mul = ((ddr_mul * tmp_div) - 1) << 24;
+ pll3_mode = 1;
+ loop_max = 2;
+ } else {
+ tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
+ (brd_clk * ddr0800_mul) / 2;
+ data_mul = ((ddr0800_mul * tmp_div) - 1) << 24;
+ pll3_mode = 0;
+ loop_max = 8;
+ }
+
+ switch (tmp_div) {
+ case 1:
+ data_div = 0;
+ break;
+ case 2:
+ case 3:
+ case 4:
+ data_div = tmp_div;
+ break;
+ default:
+ data_div = 6;
+ data_mul = (data_mul * tmp_div) / 3;
+ break;
+ }
+ data_mul = data_mul | (brd_clkdiva << 7);
+
+ /* PLL3 disable */
+ data_l = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT;
+ cpg_write_32(CPG_PLLECR, data_l);
+ dsb_sev();
+
+ if ((prr_product == PRR_PRODUCT_M3) ||
+ ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_20))) {
+ /* PLL3 DIV resetting(Lowest value:3) */
+ data_l = 0x00030003 | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
+ cpg_write_32(CPG_FRQCRD, data_l);
+ dsb_sev();
+
+ /* zb3 clk stop */
+ data_l = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR);
+ cpg_write_32(CPG_ZB3CKCR, data_l);
+ dsb_sev();
+
+ /* PLL3 enable */
+ data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
+ cpg_write_32(CPG_PLLECR, data_l);
+ dsb_sev();
+
+ do {
+ data_l = mmio_read_32(CPG_PLLECR);
+ } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
+ dsb_sev();
+
+ /* PLL3 DIV resetting (Highest value:0) */
+ data_l = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
+ cpg_write_32(CPG_FRQCRD, data_l);
+ dsb_sev();
+
+ /* DIV SET KICK */
+ data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
+ cpg_write_32(CPG_FRQCRB, data_l);
+ dsb_sev();
+
+ /* PLL3 multiplie set */
+ cpg_write_32(CPG_PLL3CR, data_mul);
+ dsb_sev();
+
+ do {
+ data_l = mmio_read_32(CPG_PLLECR);
+ } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
+ dsb_sev();
+
+ /* PLL3 DIV resetting(Target value) */
+ data_l = (data_div << 16) | data_div |
+ (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80);
+ cpg_write_32(CPG_FRQCRD, data_l);
+ dsb_sev();
+
+ /* DIV SET KICK */
+ data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
+ cpg_write_32(CPG_FRQCRB, data_l);
+ dsb_sev();
+
+ do {
+ data_l = mmio_read_32(CPG_PLLECR);
+ } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
+ dsb_sev();
+
+ /* zb3 clk start */
+ data_l = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR);
+ cpg_write_32(CPG_ZB3CKCR, data_l);
+ dsb_sev();
+
+ } else { /* H3Ver.3.0/M3N/V3H */
+
+ /* PLL3 multiplie set */
+ cpg_write_32(CPG_PLL3CR, data_mul);
+ dsb_sev();
+
+ /* PLL3 DIV set(Target value) */
+ data_l = (data_div << 16) | data_div |
+ (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80);
+ cpg_write_32(CPG_FRQCRD, data_l);
+
+ /* DIV SET KICK */
+ data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
+ cpg_write_32(CPG_FRQCRB, data_l);
+ dsb_sev();
+
+ /* PLL3 enable */
+ data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
+ cpg_write_32(CPG_PLLECR, data_l);
+ dsb_sev();
+
+ do {
+ data_l = mmio_read_32(CPG_PLLECR);
+ } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
+ dsb_sev();
+ }
+}
+
+/* barrier */
+static inline void dsb_sev(void)
+{
+ __asm__ __volatile__("dsb sy");
+}
+
+/* DDR memory register access */
+static void wait_dbcmd(void)
+{
+ uint32_t data_l;
+ /* dummy read */
+ data_l = mmio_read_32(DBSC_DBCMD);
+ dsb_sev();
+ while (1) {
+ /* wait DBCMD 1=busy, 0=ready */
+ data_l = mmio_read_32(DBSC_DBWAIT);
+ dsb_sev();
+ if ((data_l & 0x00000001) == 0x00)
+ break;
+ }
+}
+
+static void send_dbcmd(uint32_t cmd)
+{
+ /* dummy read */
+ wait_dbcmd();
+ mmio_write_32(DBSC_DBCMD, cmd);
+ dsb_sev();
+}
+
+static void dbwait_loop(uint32_t wait_loop)
+{
+ uint32_t i;
+
+ for (i = 0; i < wait_loop; i++)
+ wait_dbcmd();
+}
+
+/* DDRPHY register access (raw) */
+static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd)
+{
+ uint32_t val;
+ uint32_t loop;
+
+ val = 0;
+ if ((prr_product != PRR_PRODUCT_M3N) &&
+ (prr_product != PRR_PRODUCT_V3H)) {
+ mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
+ dsb_sev();
+
+ while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) {
+ dsb_sev();
+ }
+ dsb_sev();
+
+ for (loop = 0; loop < loop_max; loop++) {
+ val = mmio_read_32(DBSC_DBPDRGD(phyno));
+ dsb_sev();
+ }
+ (void)val;
+ } else {
+ mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00004000);
+ dsb_sev();
+ while (mmio_read_32(DBSC_DBPDRGA(phyno)) !=
+ (regadd | 0x0000C000)) {
+ dsb_sev();
+ };
+ val = mmio_read_32(DBSC_DBPDRGA(phyno));
+ mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000);
+ while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) {
+ dsb_sev();
+ };
+ dsb_sev();
+
+ mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000);
+ while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) {
+ dsb_sev();
+ };
+
+ dsb_sev();
+ val = mmio_read_32(DBSC_DBPDRGD(phyno));
+ dsb_sev();
+ (void)val;
+ }
+ return val;
+}
+
+static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata)
+{
+ uint32_t val;
+ uint32_t loop;
+
+ if ((prr_product != PRR_PRODUCT_M3N) &&
+ (prr_product != PRR_PRODUCT_V3H)) {
+ mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
+ dsb_sev();
+ for (loop = 0; loop < loop_max; loop++) {
+ val = mmio_read_32(DBSC_DBPDRGA(phyno));
+ dsb_sev();
+ }
+ mmio_write_32(DBSC_DBPDRGD(phyno), regdata);
+ dsb_sev();
+
+ for (loop = 0; loop < loop_max; loop++) {
+ val = mmio_read_32(DBSC_DBPDRGD(phyno));
+ dsb_sev();
+ }
+ } else {
+ mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
+ dsb_sev();
+
+ while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) {
+ dsb_sev();
+ };
+ dsb_sev();
+
+ mmio_write_32(DBSC_DBPDRGD(phyno), regdata);
+ dsb_sev();
+
+ while (mmio_read_32(DBSC_DBPDRGA(phyno)) !=
+ (regadd | 0x00008000)) {
+ dsb_sev();
+ };
+ mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000);
+
+ while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) {
+ dsb_sev();
+ };
+ dsb_sev();
+
+ mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
+ }
+ (void)val;
+}
+
+static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata)
+{
+ uint32_t ch;
+ uint32_t val;
+ uint32_t loop;
+
+ if ((prr_product != PRR_PRODUCT_M3N) &&
+ (prr_product != PRR_PRODUCT_V3H)) {
+ foreach_vch(ch) {
+ mmio_write_32(DBSC_DBPDRGA(ch), regadd);
+ dsb_sev();
+ }
+
+ foreach_vch(ch) {
+ mmio_write_32(DBSC_DBPDRGD(ch), regdata);
+ dsb_sev();
+ }
+
+ for (loop = 0; loop < loop_max; loop++) {
+ val = mmio_read_32(DBSC_DBPDRGD(0));
+ dsb_sev();
+ }
+ (void)val;
+ } else {
+ foreach_vch(ch) {
+ reg_ddrphy_write(ch, regadd, regdata);
+ dsb_sev();
+ }
+ }
+}
+
+static inline void ddrphy_regif_idle(void)
+{
+ uint32_t val;
+
+ val = reg_ddrphy_read(0, ddr_regdef_adr(_reg_PI_INT_STATUS));
+ dsb_sev();
+ (void)val;
+}
+
+/* DDRPHY register access (field modify) */
+static inline uint32_t ddr_regdef(uint32_t _regdef)
+{
+ return p_ddr_regdef_tbl[_regdef];
+}
+
+static inline uint32_t ddr_regdef_adr(uint32_t _regdef)
+{
+ return DDR_REGDEF_ADR(p_ddr_regdef_tbl[_regdef]);
+}
+
+static inline uint32_t ddr_regdef_lsb(uint32_t _regdef)
+{
+ return DDR_REGDEF_LSB(p_ddr_regdef_tbl[_regdef]);
+}
+
+static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
+ uint32_t val)
+{
+ uint32_t adr;
+ uint32_t lsb;
+ uint32_t len;
+ uint32_t msk;
+ uint32_t tmp;
+ uint32_t regdef;
+
+ regdef = ddr_regdef(_regdef);
+ adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice;
+ len = DDR_REGDEF_LEN(regdef);
+ lsb = DDR_REGDEF_LSB(regdef);
+ if (len == 0x20)
+ msk = 0xffffffff;
+ else
+ msk = ((1U << len) - 1) << lsb;
+
+ tmp = reg_ddrphy_read(ch, adr);
+ tmp = (tmp & (~msk)) | ((val << lsb) & msk);
+ reg_ddrphy_write(ch, adr, tmp);
+}
+
+static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef)
+{
+ uint32_t adr;
+ uint32_t lsb;
+ uint32_t len;
+ uint32_t msk;
+ uint32_t tmp;
+ uint32_t regdef;
+
+ regdef = ddr_regdef(_regdef);
+ adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice;
+ len = DDR_REGDEF_LEN(regdef);
+ lsb = DDR_REGDEF_LSB(regdef);
+ if (len == 0x20)
+ msk = 0xffffffff;
+ else
+ msk = ((1U << len) - 1);
+
+ tmp = reg_ddrphy_read(ch, adr);
+ tmp = (tmp >> lsb) & msk;
+
+ return tmp;
+}
+
+static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val)
+{
+ ddr_setval_s(ch, 0, regdef, val);
+}
+
+static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val)
+{
+ uint32_t ch;
+
+ foreach_vch(ch)
+ ddr_setval_s(ch, slice, regdef, val);
+}
+
+static void ddr_setval_ach(uint32_t regdef, uint32_t val)
+{
+ ddr_setval_ach_s(0, regdef, val);
+}
+
+static void ddr_setval_ach_as(uint32_t regdef, uint32_t val)
+{
+ uint32_t slice;
+
+ for (slice = 0; slice < SLICE_CNT; slice++)
+ ddr_setval_ach_s(slice, regdef, val);
+}
+
+static uint32_t ddr_getval(uint32_t ch, uint32_t regdef)
+{
+ return ddr_getval_s(ch, 0, regdef);
+}
+
+static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p)
+{
+ uint32_t ch;
+
+ foreach_vch(ch)
+ p[ch] = ddr_getval_s(ch, 0, regdef);
+ return p[0];
+}
+
+static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p)
+{
+ uint32_t ch, slice;
+ uint32_t *pp;
+
+ pp = p;
+ foreach_vch(ch)
+ for (slice = 0; slice < SLICE_CNT; slice++)
+ *pp++ = ddr_getval_s(ch, slice, regdef);
+ return p[0];
+}
+
+/* handling functions for setteing ddrphy value table */
+static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size)
+{
+ uint32_t i;
+
+ for (i = 0; i < size; i++) {
+ to[i] = from[i];
+ }
+}
+
+static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val)
+{
+ uint32_t adr;
+ uint32_t lsb;
+ uint32_t len;
+ uint32_t msk;
+ uint32_t tmp;
+ uint32_t adrmsk;
+ uint32_t regdef;
+
+ regdef = ddr_regdef(_regdef);
+ adr = DDR_REGDEF_ADR(regdef);
+ len = DDR_REGDEF_LEN(regdef);
+ lsb = DDR_REGDEF_LSB(regdef);
+ if (len == 0x20)
+ msk = 0xffffffff;
+ else
+ msk = ((1U << len) - 1) << lsb;
+
+ if (adr < 0x400) {
+ adrmsk = 0xff;
+ } else {
+ adrmsk = 0x7f;
+ }
+
+ tmp = tbl[adr & adrmsk];
+ tmp = (tmp & (~msk)) | ((val << lsb) & msk);
+ tbl[adr & adrmsk] = tmp;
+}
+
+static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef)
+{
+ uint32_t adr;
+ uint32_t lsb;
+ uint32_t len;
+ uint32_t msk;
+ uint32_t tmp;
+ uint32_t adrmsk;
+ uint32_t regdef;
+
+ regdef = ddr_regdef(_regdef);
+ adr = DDR_REGDEF_ADR(regdef);
+ len = DDR_REGDEF_LEN(regdef);
+ lsb = DDR_REGDEF_LSB(regdef);
+ if (len == 0x20)
+ msk = 0xffffffff;
+ else
+ msk = ((1U << len) - 1);
+
+ if (adr < 0x400) {
+ adrmsk = 0xff;
+ } else {
+ adrmsk = 0x7f;
+ }
+
+ tmp = tbl[adr & adrmsk];
+ tmp = (tmp >> lsb) & msk;
+
+ return tmp;
+}
+
+/* DDRPHY register access handling */
+static uint32_t ddrphy_regif_chk(void)
+{
+ uint32_t tmp_ach[DRAM_CH_CNT];
+ uint32_t ch;
+ uint32_t err;
+ uint32_t PI_VERSION_CODE;
+
+ if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) ||
+ (prr_product == PRR_PRODUCT_M3)) {
+ PI_VERSION_CODE = 0x2041; /* H3 Ver.1.x/M3-W */
+ } else {
+ PI_VERSION_CODE = 0x2040; /* H3 Ver.2.0 or later/M3-N/V3H */
+ }
+
+ ddr_getval_ach(_reg_PI_VERSION, (uint32_t *)tmp_ach);
+ err = 0;
+ foreach_vch(ch) {
+ if (tmp_ach[ch] != PI_VERSION_CODE)
+ err = 1;
+ }
+ return err;
+}
+
+/* functions and parameters for timing setting */
+struct _jedec_spec1 {
+ uint16_t fx3;
+ uint8_t rlwodbi;
+ uint8_t rlwdbi;
+ uint8_t WL;
+ uint8_t nwr;
+ uint8_t nrtp;
+ uint8_t odtlon;
+ uint8_t MR1;
+ uint8_t MR2;
+};
+
+#define JS1_USABLEC_SPEC_LO 2
+#define JS1_USABLEC_SPEC_HI 5
+#define JS1_FREQ_TBL_NUM 8
+#define JS1_MR1(f) (0x04 | ((f) << 4))
+#define JS1_MR2(f) (0x00 | ((f) << 3) | (f))
+const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = {
+ /* 533.333Mbps */
+ { 800, 6, 6, 4, 6, 8, 0, JS1_MR1(0), JS1_MR2(0) | 0x40 },
+ /* 1066.666Mbps */
+ { 1600, 10, 12, 8, 10, 8, 0, JS1_MR1(1), JS1_MR2(1) | 0x40 },
+ /* 1600.000Mbps */
+ { 2400, 14, 16, 12, 16, 8, 6, JS1_MR1(2), JS1_MR2(2) | 0x40 },
+ /* 2133.333Mbps */
+ { 3200, 20, 22, 10, 20, 8, 4, JS1_MR1(3), JS1_MR2(3) },
+ /* 2666.666Mbps */
+ { 4000, 24, 28, 12, 24, 10, 4, JS1_MR1(4), JS1_MR2(4) },
+ /* 3200.000Mbps */
+ { 4800, 28, 32, 14, 30, 12, 6, JS1_MR1(5), JS1_MR2(5) },
+ /* 3733.333Mbps */
+ { 5600, 32, 36, 16, 34, 14, 6, JS1_MR1(6), JS1_MR2(6) },
+ /* 4266.666Mbps */
+ { 6400, 36, 40, 18, 40, 16, 8, JS1_MR1(7), JS1_MR2(7) }
+};
+
+struct _jedec_spec2 {
+ uint16_t ps;
+ uint16_t cyc;
+};
+
+#define js2_tsr 0
+#define js2_txp 1
+#define js2_trtp 2
+#define js2_trcd 3
+#define js2_trppb 4
+#define js2_trpab 5
+#define js2_tras 6
+#define js2_twr 7
+#define js2_twtr 8
+#define js2_trrd 9
+#define js2_tppd 10
+#define js2_tfaw 11
+#define js2_tdqsck 12
+#define js2_tckehcmd 13
+#define js2_tckelcmd 14
+#define js2_tckelpd 15
+#define js2_tmrr 16
+#define js2_tmrw 17
+#define js2_tmrd 18
+#define js2_tzqcalns 19
+#define js2_tzqlat 20
+#define js2_tiedly 21
+#define js2_tODTon_min 22
+#define JS2_TBLCNT 23
+
+#define js2_trcpb (JS2_TBLCNT)
+#define js2_trcab (JS2_TBLCNT + 1)
+#define js2_trfcab (JS2_TBLCNT + 2)
+#define JS2_CNT (JS2_TBLCNT + 3)
+
+#ifndef JS2_DERATE
+#define JS2_DERATE 0
+#endif
+const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = {
+ {
+/*tSR */ {15000, 3},
+/*tXP */ {7500, 3},
+/*tRTP */ {7500, 8},
+/*tRCD */ {18000, 4},
+/*tRPpb */ {18000, 3},
+/*tRPab */ {21000, 3},
+/*tRAS */ {42000, 3},
+/*tWR */ {18000, 4},
+/*tWTR */ {10000, 8},
+/*tRRD */ {10000, 4},
+/*tPPD */ {0, 0},
+/*tFAW */ {40000, 0},
+/*tDQSCK*/ {3500, 0},
+/*tCKEHCMD*/ {7500, 3},
+/*tCKELCMD*/ {7500, 3},
+/*tCKELPD*/ {7500, 3},
+/*tMRR*/ {0, 8},
+/*tMRW*/ {10000, 10},
+/*tMRD*/ {14000, 10},
+/*tZQCALns*/ {1000 * 10, 0},
+/*tZQLAT*/ {30000, 10},
+/*tIEdly*/ {12500, 0},
+/*tODTon_min*/ {1500, 0}
+ }, {
+/*tSR */ {15000, 3},
+/*tXP */ {7500, 3},
+/*tRTP */ {7500, 8},
+/*tRCD */ {19875, 4},
+/*tRPpb */ {19875, 3},
+/*tRPab */ {22875, 3},
+/*tRAS */ {43875, 3},
+/*tWR */ {18000, 4},
+/*tWTR */ {10000, 8},
+/*tRRD */ {11875, 4},
+/*tPPD */ {0, 0},
+/*tFAW */ {40000, 0},
+/*tDQSCK*/ {3600, 0},
+/*tCKEHCMD*/ {7500, 3},
+/*tCKELCMD*/ {7500, 3},
+/*tCKELPD*/ {7500, 3},
+/*tMRR*/ {0, 8},
+/*tMRW*/ {10000, 10},
+/*tMRD*/ {14000, 10},
+/*tZQCALns*/ {1000 * 10, 0},
+/*tZQLAT*/ {30000, 10},
+/*tIEdly*/ {12500, 0},
+/*tODTon_min*/ {1500, 0}
+ }
+};
+
+const uint16_t jedec_spec2_trfc_ab[7] = {
+/* 4Gb, 6Gb, 8Gb,12Gb, 16Gb, 24Gb(non), 32Gb(non) */
+ 130, 180, 180, 280, 280, 560, 560
+};
+
+static uint32_t js1_ind;
+static uint16_t js2[JS2_CNT];
+static uint8_t RL;
+static uint8_t WL;
+
+static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps,
+ uint16_t cyc)
+{
+ uint32_t tmp;
+ uint32_t div;
+
+ tmp = (((uint32_t)(ps) + 9) / 10) * _ddr_mbps;
+ div = tmp / (200000 * _ddr_mbpsdiv);
+ if (tmp != (div * 200000 * _ddr_mbpsdiv))
+ div = div + 1;
+
+ if (div > cyc)
+ return (uint16_t)div;
+ return cyc;
+}
+
+static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv,
+ uint16_t *_js2)
+{
+ int i;
+
+ for (i = 0; i < JS2_TBLCNT; i++) {
+ _js2[i] = _f_scale(_ddr_mbps, _ddr_mbpsdiv,
+ 1UL * jedec_spec2[JS2_DERATE][i].ps,
+ jedec_spec2[JS2_DERATE][i].cyc);
+ }
+
+ _js2[js2_trcpb] = _js2[js2_tras] + _js2[js2_trppb];
+ _js2[js2_trcab] = _js2[js2_tras] + _js2[js2_trpab];
+}
+
+/* scaler for DELAY value */
+static int16_t _f_scale_adj(int16_t ps)
+{
+ int32_t tmp;
+ /*
+ * tmp = (int32_t)512 * ps * ddr_mbps /2 / ddr_mbpsdiv / 1000 / 1000;
+ * = ps * ddr_mbps /2 / ddr_mbpsdiv *512 / 8 / 8 / 125 / 125
+ * = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125
+ */
+ tmp =
+ (int32_t)4 * (int32_t)ps * (int32_t)ddr_mbps /
+ (int32_t)ddr_mbpsdiv;
+ tmp = (int32_t)tmp / (int32_t)15625;
+
+ return (int16_t)tmp;
+}
+
+static const uint32_t reg_pi_mr1_data_fx_csx[2][CSAB_CNT] = {
+ {
+ _reg_PI_MR1_DATA_F0_0,
+ _reg_PI_MR1_DATA_F0_1,
+ _reg_PI_MR1_DATA_F0_2,
+ _reg_PI_MR1_DATA_F0_3},
+ {
+ _reg_PI_MR1_DATA_F1_0,
+ _reg_PI_MR1_DATA_F1_1,
+ _reg_PI_MR1_DATA_F1_2,
+ _reg_PI_MR1_DATA_F1_3}
+};
+
+static const uint32_t reg_pi_mr2_data_fx_csx[2][CSAB_CNT] = {
+ {
+ _reg_PI_MR2_DATA_F0_0,
+ _reg_PI_MR2_DATA_F0_1,
+ _reg_PI_MR2_DATA_F0_2,
+ _reg_PI_MR2_DATA_F0_3},
+ {
+ _reg_PI_MR2_DATA_F1_0,
+ _reg_PI_MR2_DATA_F1_1,
+ _reg_PI_MR2_DATA_F1_2,
+ _reg_PI_MR2_DATA_F1_3}
+};
+
+static const uint32_t reg_pi_mr3_data_fx_csx[2][CSAB_CNT] = {
+ {
+ _reg_PI_MR3_DATA_F0_0,
+ _reg_PI_MR3_DATA_F0_1,
+ _reg_PI_MR3_DATA_F0_2,
+ _reg_PI_MR3_DATA_F0_3},
+ {
+ _reg_PI_MR3_DATA_F1_0,
+ _reg_PI_MR3_DATA_F1_1,
+ _reg_PI_MR3_DATA_F1_2,
+ _reg_PI_MR3_DATA_F1_3}
+};
+
+const uint32_t reg_pi_mr11_data_fx_csx[2][CSAB_CNT] = {
+ {
+ _reg_PI_MR11_DATA_F0_0,
+ _reg_PI_MR11_DATA_F0_1,
+ _reg_PI_MR11_DATA_F0_2,
+ _reg_PI_MR11_DATA_F0_3},
+ {
+ _reg_PI_MR11_DATA_F1_0,
+ _reg_PI_MR11_DATA_F1_1,
+ _reg_PI_MR11_DATA_F1_2,
+ _reg_PI_MR11_DATA_F1_3}
+};
+
+const uint32_t reg_pi_mr12_data_fx_csx[2][CSAB_CNT] = {
+ {
+ _reg_PI_MR12_DATA_F0_0,
+ _reg_PI_MR12_DATA_F0_1,
+ _reg_PI_MR12_DATA_F0_2,
+ _reg_PI_MR12_DATA_F0_3},
+ {
+ _reg_PI_MR12_DATA_F1_0,
+ _reg_PI_MR12_DATA_F1_1,
+ _reg_PI_MR12_DATA_F1_2,
+ _reg_PI_MR12_DATA_F1_3}
+};
+
+const uint32_t reg_pi_mr14_data_fx_csx[2][CSAB_CNT] = {
+ {
+ _reg_PI_MR14_DATA_F0_0,
+ _reg_PI_MR14_DATA_F0_1,
+ _reg_PI_MR14_DATA_F0_2,
+ _reg_PI_MR14_DATA_F0_3},
+ {
+ _reg_PI_MR14_DATA_F1_0,
+ _reg_PI_MR14_DATA_F1_1,
+ _reg_PI_MR14_DATA_F1_2,
+ _reg_PI_MR14_DATA_F1_3}
+};
+
+/*
+ * regif pll w/a ( REGIF H3 Ver.2.0 or later/M3-N/V3H WA )
+ */
+static void regif_pll_wa(void)
+{
+ uint32_t ch;
+
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
+ // PLL setting for PHY : H3 Ver.1.x
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT),
+ (0x0064U <<
+ ddr_regdef_lsb(_reg_PHY_PLL_WAIT)));
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL),
+ ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_PLL_CTRL));
+
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL),
+ ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_LP4_BOOT_PLL_CTRL));
+
+ } else {
+ /* PLL setting for PHY : M3-W/M3-N/V3H/H3 Ver.2.0 or later */
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT),
+ (0x5064U <<
+ ddr_regdef_lsb(_reg_PHY_PLL_WAIT)));
+
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL),
+ (ddrtbl_getval
+ (_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_PLL_CTRL_TOP) << 16) |
+ ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_PLL_CTRL));
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA),
+ ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_PLL_CTRL_CA));
+
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL),
+ (ddrtbl_getval
+ (_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_LP4_BOOT_PLL_CTRL_CA) << 16) |
+ ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_LP4_BOOT_PLL_CTRL));
+ reg_ddrphy_write_a(ddr_regdef_adr
+ (_reg_PHY_LP4_BOOT_TOP_PLL_CTRL),
+ ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_LP4_BOOT_TOP_PLL_CTRL
+ ));
+ }
+
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS),
+ _cnf_DDR_PHY_ADR_G_REGSET
+ [ddr_regdef_adr(_reg_PHY_LPDDR3_CS) -
+ DDR_PHY_ADR_G_REGSET_OFS]);
+
+ /* protect register interface */
+ ddrphy_regif_idle();
+ pll3_control(0);
+
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
+ /* non */
+ } else {
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_DLL_RST_EN),
+ (0x01U <<
+ ddr_regdef_lsb(_reg_PHY_DLL_RST_EN)));
+ ddrphy_regif_idle();
+ }
+
+ /* init start */
+ /* dbdficnt0:
+ * dfi_dram_clk_disable=1
+ * dfi_frequency = 0
+ * freq_ratio = 01 (2:1)
+ * init_start =0
+ */
+ foreach_vch(ch)
+ mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10);
+ dsb_sev();
+
+ /* dbdficnt0:
+ * dfi_dram_clk_disable=1
+ * dfi_frequency = 0
+ * freq_ratio = 01 (2:1)
+ * init_start =1
+ */
+ foreach_vch(ch)
+ mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11);
+ dsb_sev();
+
+ foreach_ech(ch)
+ if ((board_cnf->phyvalid) & BIT(ch))
+ while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f)
+ ;
+ dsb_sev();
+}
+
+/* load table data into DDR registers */
+static void ddrtbl_load(void)
+{
+ uint32_t i;
+ uint32_t slice;
+ uint32_t csab;
+ uint32_t adr;
+ uint32_t data_l;
+ uint32_t tmp[3];
+ uint16_t dataS;
+
+ /* TIMING REGISTERS */
+ /* search jedec_spec1 index */
+ for (i = JS1_USABLEC_SPEC_LO; i < JS1_FREQ_TBL_NUM - 1; i++) {
+ if (js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U)
+ break;
+ }
+ if (i > JS1_USABLEC_SPEC_HI)
+ js1_ind = JS1_USABLEC_SPEC_HI;
+ else
+ js1_ind = i;
+
+ if (board_cnf->dbi_en)
+ RL = js1[js1_ind].rlwdbi;
+ else
+ RL = js1[js1_ind].rlwodbi;
+
+ WL = js1[js1_ind].WL;
+
+ /* calculate jedec_spec2 */
+ _f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2);
+
+ /* PREPARE TBL */
+ if (prr_product == PRR_PRODUCT_H3) {
+ if (prr_cut <= PRR_PRODUCT_11) {
+ /* H3 Ver.1.x */
+ _tblcopy(_cnf_DDR_PHY_SLICE_REGSET,
+ DDR_PHY_SLICE_REGSET_H3,
+ DDR_PHY_SLICE_REGSET_NUM_H3);
+ _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET,
+ DDR_PHY_ADR_V_REGSET_H3,
+ DDR_PHY_ADR_V_REGSET_NUM_H3);
+ _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET,
+ DDR_PHY_ADR_I_REGSET_H3,
+ DDR_PHY_ADR_I_REGSET_NUM_H3);
+ _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET,
+ DDR_PHY_ADR_G_REGSET_H3,
+ DDR_PHY_ADR_G_REGSET_NUM_H3);
+ _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_H3,
+ DDR_PI_REGSET_NUM_H3);
+
+ DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_H3;
+ DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_H3;
+ DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_H3;
+ DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_H3;
+ DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_H3;
+ DDR_PHY_SLICE_REGSET_SIZE =
+ DDR_PHY_SLICE_REGSET_SIZE_H3;
+ DDR_PHY_ADR_V_REGSET_SIZE =
+ DDR_PHY_ADR_V_REGSET_SIZE_H3;
+ DDR_PHY_ADR_I_REGSET_SIZE =
+ DDR_PHY_ADR_I_REGSET_SIZE_H3;
+ DDR_PHY_ADR_G_REGSET_SIZE =
+ DDR_PHY_ADR_G_REGSET_SIZE_H3;
+ DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_H3;
+ DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_H3;
+ DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_H3;
+ DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_H3;
+ DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_H3;
+ DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_H3;
+
+ DDR_PHY_ADR_I_NUM = 1;
+ } else {
+ /* H3 Ver.2.0 or later */
+ _tblcopy(_cnf_DDR_PHY_SLICE_REGSET,
+ DDR_PHY_SLICE_REGSET_H3VER2,
+ DDR_PHY_SLICE_REGSET_NUM_H3VER2);
+ _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET,
+ DDR_PHY_ADR_V_REGSET_H3VER2,
+ DDR_PHY_ADR_V_REGSET_NUM_H3VER2);
+ _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET,
+ DDR_PHY_ADR_G_REGSET_H3VER2,
+ DDR_PHY_ADR_G_REGSET_NUM_H3VER2);
+ _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_H3VER2,
+ DDR_PI_REGSET_NUM_H3VER2);
+
+ DDR_PHY_SLICE_REGSET_OFS =
+ DDR_PHY_SLICE_REGSET_OFS_H3VER2;
+ DDR_PHY_ADR_V_REGSET_OFS =
+ DDR_PHY_ADR_V_REGSET_OFS_H3VER2;
+ DDR_PHY_ADR_G_REGSET_OFS =
+ DDR_PHY_ADR_G_REGSET_OFS_H3VER2;
+ DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_H3VER2;
+ DDR_PHY_SLICE_REGSET_SIZE =
+ DDR_PHY_SLICE_REGSET_SIZE_H3VER2;
+ DDR_PHY_ADR_V_REGSET_SIZE =
+ DDR_PHY_ADR_V_REGSET_SIZE_H3VER2;
+ DDR_PHY_ADR_G_REGSET_SIZE =
+ DDR_PHY_ADR_G_REGSET_SIZE_H3VER2;
+ DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_H3VER2;
+ DDR_PHY_SLICE_REGSET_NUM =
+ DDR_PHY_SLICE_REGSET_NUM_H3VER2;
+ DDR_PHY_ADR_V_REGSET_NUM =
+ DDR_PHY_ADR_V_REGSET_NUM_H3VER2;
+ DDR_PHY_ADR_G_REGSET_NUM =
+ DDR_PHY_ADR_G_REGSET_NUM_H3VER2;
+ DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_H3VER2;
+
+ DDR_PHY_ADR_I_NUM = 0;
+ }
+ } else if (prr_product == PRR_PRODUCT_M3) {
+ /* M3-W */
+ _tblcopy(_cnf_DDR_PHY_SLICE_REGSET,
+ DDR_PHY_SLICE_REGSET_M3, DDR_PHY_SLICE_REGSET_NUM_M3);
+ _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET,
+ DDR_PHY_ADR_V_REGSET_M3, DDR_PHY_ADR_V_REGSET_NUM_M3);
+ _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET,
+ DDR_PHY_ADR_I_REGSET_M3, DDR_PHY_ADR_I_REGSET_NUM_M3);
+ _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET,
+ DDR_PHY_ADR_G_REGSET_M3, DDR_PHY_ADR_G_REGSET_NUM_M3);
+ _tblcopy(_cnf_DDR_PI_REGSET,
+ DDR_PI_REGSET_M3, DDR_PI_REGSET_NUM_M3);
+
+ DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_M3;
+ DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_M3;
+ DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_M3;
+ DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_M3;
+ DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_M3;
+ DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_M3;
+ DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_M3;
+ DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_M3;
+ DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_M3;
+ DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_M3;
+ DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_M3;
+ DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_M3;
+ DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_M3;
+ DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_M3;
+ DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_M3;
+
+ DDR_PHY_ADR_I_NUM = 2;
+ } else {
+ /* M3-N/V3H */
+ _tblcopy(_cnf_DDR_PHY_SLICE_REGSET,
+ DDR_PHY_SLICE_REGSET_M3N,
+ DDR_PHY_SLICE_REGSET_NUM_M3N);
+ _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, DDR_PHY_ADR_V_REGSET_M3N,
+ DDR_PHY_ADR_V_REGSET_NUM_M3N);
+ _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, DDR_PHY_ADR_I_REGSET_M3N,
+ DDR_PHY_ADR_I_REGSET_NUM_M3N);
+ _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, DDR_PHY_ADR_G_REGSET_M3N,
+ DDR_PHY_ADR_G_REGSET_NUM_M3N);
+ _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_M3N,
+ DDR_PI_REGSET_NUM_M3N);
+
+ DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_M3N;
+ DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_M3N;
+ DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_M3N;
+ DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_M3N;
+ DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_M3N;
+ DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_M3N;
+ DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_M3N;
+ DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_M3N;
+ DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_M3N;
+ DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_M3N;
+ DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_M3N;
+ DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_M3N;
+ DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_M3N;
+ DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_M3N;
+ DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_M3N;
+
+ DDR_PHY_ADR_I_NUM = 2;
+ }
+
+ /* PLL CODE CHANGE */
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) {
+ ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL,
+ 0x1142);
+ ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_LP4_BOOT_PLL_CTRL, 0x1142);
+ }
+
+ /* on fly gate adjust */
+ if ((prr_product == PRR_PRODUCT_M3) && (prr_cut == PRR_PRODUCT_10)) {
+ ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
+ _reg_ON_FLY_GATE_ADJUST_EN, 0x00);
+ }
+
+ /* Adjust PI parameters */
+#ifdef _def_LPDDR4_ODT
+ for (i = 0; i < 2; i++) {
+ for (csab = 0; csab < CSAB_CNT; csab++) {
+ ddrtbl_setval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr11_data_fx_csx[i][csab],
+ _def_LPDDR4_ODT);
+ }
+ }
+#endif /* _def_LPDDR4_ODT */
+
+#ifdef _def_LPDDR4_VREFCA
+ for (i = 0; i < 2; i++) {
+ for (csab = 0; csab < CSAB_CNT; csab++) {
+ ddrtbl_setval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr12_data_fx_csx[i][csab],
+ _def_LPDDR4_VREFCA);
+ }
+ }
+#endif /* _def_LPDDR4_VREFCA */
+ if ((prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
+ js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7U;
+ if (js2[js2_tiedly] > (RL))
+ js2[js2_tiedly] = RL;
+ } else if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut > PRR_PRODUCT_11)) {
+ js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4U;
+ } else if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) {
+ js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0);
+ }
+
+ if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) ||
+ (prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
+ if ((js2[js2_tiedly]) >= 0x1e)
+ dataS = 0x1e;
+ else
+ dataS = js2[js2_tiedly];
+ } else {
+ if ((js2[js2_tiedly]) >= 0x0e)
+ dataS = 0x0e;
+ else
+ dataS = js2[js2_tiedly];
+ }
+
+ ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataS);
+ ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY,
+ (dataS - 2));
+ if ((prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
+ ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
+ _reg_PHY_RDDATA_EN_OE_DLY, dataS - 2);
+ }
+ ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1, RL - dataS);
+
+ if (ddrtbl_getval
+ (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) {
+ data_l = WL - 1;
+ } else {
+ data_l = WL;
+ }
+ ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, data_l - 2);
+ ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, data_l);
+
+ if (board_cnf->dbi_en) {
+ ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE,
+ 0x01);
+ ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
+ _reg_PHY_WDQLVL_DATADM_MASK, 0x000);
+ } else {
+ ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE,
+ 0x00);
+ ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
+ _reg_PHY_WDQLVL_DATADM_MASK, 0x100);
+ }
+
+ tmp[0] = js1[js1_ind].MR1;
+ tmp[1] = js1[js1_ind].MR2;
+ data_l = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0);
+ if (board_cnf->dbi_en)
+ tmp[2] = data_l | 0xc0;
+ else
+ tmp[2] = data_l & (~0xc0);
+
+ for (i = 0; i < 2; i++) {
+ for (csab = 0; csab < CSAB_CNT; csab++) {
+ ddrtbl_setval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr1_data_fx_csx[i][csab], tmp[0]);
+ ddrtbl_setval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr2_data_fx_csx[i][csab], tmp[1]);
+ ddrtbl_setval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr3_data_fx_csx[i][csab], tmp[2]);
+ }
+ }
+
+ /* DDRPHY INT START */
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
+ /* non */
+ } else {
+ regif_pll_wa();
+ dbwait_loop(5);
+ }
+
+ /* FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) */
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
+ BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
+ ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01);
+
+ /* SET DATA SLICE TABLE */
+ for (slice = 0; slice < SLICE_CNT; slice++) {
+ adr =
+ DDR_PHY_SLICE_REGSET_OFS +
+ DDR_PHY_SLICE_REGSET_SIZE * slice;
+ for (i = 0; i < DDR_PHY_SLICE_REGSET_NUM; i++) {
+ reg_ddrphy_write_a(adr + i,
+ _cnf_DDR_PHY_SLICE_REGSET[i]);
+ }
+ }
+
+ /* SET ADR SLICE TABLE */
+ adr = DDR_PHY_ADR_V_REGSET_OFS;
+ for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) {
+ reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]);
+ }
+
+ if (((prr_product == PRR_PRODUCT_M3) ||
+ (prr_product == PRR_PRODUCT_M3N)) &&
+ ((0x00ffffff & (uint32_t)((board_cnf->ch[0].ca_swap) >> 40))
+ != 0x00)) {
+ adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE;
+ for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) {
+ reg_ddrphy_write_a(adr + i,
+ _cnf_DDR_PHY_ADR_V_REGSET[i]);
+ }
+ ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_ADR_DISABLE, 0x02);
+ DDR_PHY_ADR_I_NUM -= 1;
+ ddr_phycaslice = 1;
+
+#ifndef _def_LPDDR4_ODT
+ for (i = 0; i < 2; i++) {
+ for (csab = 0; csab < CSAB_CNT; csab++) {
+ ddrtbl_setval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr11_data_fx_csx[i][csab],
+ 0x66);
+ }
+ }
+#endif/* _def_LPDDR4_ODT */
+ } else {
+ ddr_phycaslice = 0;
+ }
+
+ if (DDR_PHY_ADR_I_NUM > 0) {
+ for (slice = 0; slice < DDR_PHY_ADR_I_NUM; slice++) {
+ adr =
+ DDR_PHY_ADR_I_REGSET_OFS +
+ DDR_PHY_ADR_I_REGSET_SIZE * slice;
+ for (i = 0; i < DDR_PHY_ADR_I_REGSET_NUM; i++) {
+ reg_ddrphy_write_a(adr + i,
+ _cnf_DDR_PHY_ADR_I_REGSET
+ [i]);
+ }
+ }
+ }
+
+ /* SET ADRCTRL SLICE TABLE */
+ adr = DDR_PHY_ADR_G_REGSET_OFS;
+ for (i = 0; i < DDR_PHY_ADR_G_REGSET_NUM; i++) {
+ reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_G_REGSET[i]);
+ }
+
+ /* SET PI REGISTERS */
+ adr = DDR_PI_REGSET_OFS;
+ for (i = 0; i < DDR_PI_REGSET_NUM; i++) {
+ reg_ddrphy_write_a(adr + i, _cnf_DDR_PI_REGSET[i]);
+ }
+}
+
+/* CONFIGURE DDR REGISTERS */
+static void ddr_config_sub(void)
+{
+ uint32_t i;
+ uint32_t ch, slice;
+ uint32_t data_l;
+ uint32_t tmp;
+ uint8_t high_byte[SLICE_CNT];
+ const uint32_t _par_CALVL_DEVICE_MAP = 1;
+
+ foreach_vch(ch) {
+ /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */
+ for (slice = 0; slice < SLICE_CNT; slice++) {
+ high_byte[slice] =
+ (board_cnf->ch[ch].dqs_swap >> (4 * slice)) % 2;
+ ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0,
+ board_cnf->ch[ch].dq_swap[slice]);
+ ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1,
+ board_cnf->ch[ch].dm_swap[slice]);
+ if (high_byte[slice]) {
+ /* HIGHER 16 BYTE */
+ ddr_setval_s(ch, slice,
+ _reg_PHY_CALVL_VREF_DRIVING_SLICE,
+ 0x00);
+ } else {
+ /* LOWER 16 BYTE */
+ ddr_setval_s(ch, slice,
+ _reg_PHY_CALVL_VREF_DRIVING_SLICE,
+ 0x01);
+ }
+ }
+
+ /* BOARD SETTINGS (CA,ADDR_SEL) */
+ data_l = (0x00ffffff & (uint32_t)(board_cnf->ch[ch].ca_swap)) |
+ 0x00888888;
+
+ /* --- ADR_CALVL_SWIZZLE --- */
+ if (prr_product == PRR_PRODUCT_M3) {
+ ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, data_l);
+ ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0,
+ 0x00000000);
+ ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, data_l);
+ ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1,
+ 0x00000000);
+ ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP,
+ _par_CALVL_DEVICE_MAP);
+ } else {
+ ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, data_l);
+ ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000);
+ ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP,
+ _par_CALVL_DEVICE_MAP);
+ }
+
+ /* --- ADR_ADDR_SEL --- */
+ if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut > PRR_PRODUCT_11)) {
+ data_l = 0x00FFFFFF & board_cnf->ch[ch].ca_swap;
+ } else {
+ data_l = 0;
+ tmp = board_cnf->ch[ch].ca_swap;
+ for (i = 0; i < 6; i++) {
+ data_l |= ((tmp & 0x0f) << (i * 5));
+ tmp = tmp >> 4;
+ }
+ }
+ ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, data_l);
+ if (ddr_phycaslice == 1) {
+ /* ----------- adr slice2 swap ----------- */
+ tmp = (uint32_t)((board_cnf->ch[ch].ca_swap) >> 40);
+ data_l = (tmp & 0x00ffffff) | 0x00888888;
+
+ /* --- ADR_CALVL_SWIZZLE --- */
+ if (prr_product == PRR_PRODUCT_M3) {
+ ddr_setval_s(ch, 2,
+ _reg_PHY_ADR_CALVL_SWIZZLE0_0,
+ data_l);
+ ddr_setval_s(ch, 2,
+ _reg_PHY_ADR_CALVL_SWIZZLE1_0,
+ 0x00000000);
+ ddr_setval_s(ch, 2,
+ _reg_PHY_ADR_CALVL_SWIZZLE0_1,
+ data_l);
+ ddr_setval_s(ch, 2,
+ _reg_PHY_ADR_CALVL_SWIZZLE1_1,
+ 0x00000000);
+ ddr_setval_s(ch, 2,
+ _reg_PHY_ADR_CALVL_DEVICE_MAP,
+ _par_CALVL_DEVICE_MAP);
+ } else {
+ ddr_setval_s(ch, 2,
+ _reg_PHY_ADR_CALVL_SWIZZLE0,
+ data_l);
+ ddr_setval_s(ch, 2,
+ _reg_PHY_ADR_CALVL_SWIZZLE1,
+ 0x00000000);
+ ddr_setval_s(ch, 2,
+ _reg_PHY_CALVL_DEVICE_MAP,
+ _par_CALVL_DEVICE_MAP);
+ }
+
+ /* --- ADR_ADDR_SEL --- */
+ data_l = 0;
+ for (i = 0; i < 6; i++) {
+ data_l |= ((tmp & 0x0f) << (i * 5));
+ tmp = tmp >> 4;
+ }
+
+ ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, data_l);
+ }
+
+ /* BOARD SETTINGS (BYTE_ORDER_SEL) */
+ if (prr_product == PRR_PRODUCT_M3) {
+ /* --- DATA_BYTE_SWAP --- */
+ data_l = 0;
+ tmp = board_cnf->ch[ch].dqs_swap;
+ for (i = 0; i < 4; i++) {
+ data_l |= ((tmp & 0x03) << (i * 2));
+ tmp = tmp >> 4;
+ }
+ } else {
+ /* --- DATA_BYTE_SWAP --- */
+ data_l = board_cnf->ch[ch].dqs_swap;
+ ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 0x01);
+ ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0,
+ (data_l) & 0x0f);
+ ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1,
+ (data_l >> 4 * 1) & 0x0f);
+ ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE2,
+ (data_l >> 4 * 2) & 0x0f);
+ ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE3,
+ (data_l >> 4 * 3) & 0x0f);
+
+ ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH, 0x00);
+ }
+ ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, data_l);
+ }
+}
+
+static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz)
+{
+ uint32_t slice;
+ uint32_t tmp;
+ uint32_t tgt;
+
+ if (ddr_csn / 2) {
+ tgt = 3;
+ } else {
+ tgt = 1;
+ }
+
+ for (slice = 0; slice < SLICE_CNT; slice++) {
+ tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+ if (tgt == tmp)
+ break;
+ }
+ tmp = 0x00FFFFFF & board_cnf->ch[ch].ca_swap;
+ if (slice % 2)
+ tmp |= 0x00888888;
+ *p_swz = tmp;
+}
+
+static void ddr_config_sub_h3v1x(void)
+{
+ uint32_t ch, slice;
+ uint32_t data_l;
+ uint32_t tmp;
+ uint8_t high_byte[SLICE_CNT];
+ uint32_t ca_swizzle;
+ uint32_t ca;
+ uint32_t csmap;
+ uint32_t o_inv;
+ uint32_t inv;
+ uint32_t bit_soc;
+ uint32_t bit_mem;
+ uint32_t j;
+
+ const uint8_t o_mr15 = 0x55;
+ const uint8_t o_mr20 = 0x55;
+ const uint16_t o_mr32_mr40 = 0x5a3c;
+
+ foreach_vch(ch) {
+ /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */
+ csmap = 0;
+ for (slice = 0; slice < SLICE_CNT; slice++) {
+ tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) &
+ 0x0f;
+ high_byte[slice] = tmp % 2;
+ if (tmp == 1 && (slice >= 2))
+ csmap |= 0x05;
+ if (tmp == 3 && (slice >= 2))
+ csmap |= 0x50;
+ ddr_setval_s(ch, slice, _reg_PHY_DQ_SWIZZLING,
+ board_cnf->ch[ch].dq_swap[slice]);
+ if (high_byte[slice]) {
+ /* HIGHER 16 BYTE */
+ ddr_setval_s(ch, slice,
+ _reg_PHY_CALVL_VREF_DRIVING_SLICE,
+ 0x00);
+ } else {
+ /* LOWER 16 BYTE */
+ ddr_setval_s(ch, slice,
+ _reg_PHY_CALVL_VREF_DRIVING_SLICE,
+ 0x01);
+ }
+ }
+ /* BOARD SETTINGS (CA,ADDR_SEL) */
+ ca = 0x00FFFFFF & board_cnf->ch[ch].ca_swap;
+ ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, ca);
+ ddr_setval(ch, _reg_PHY_CALVL_CS_MAP, csmap);
+
+ get_ca_swizzle(ch, 0, &ca_swizzle);
+
+ ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, ca_swizzle);
+ ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000);
+ ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, 0x00000000);
+ ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1, 0x00000000);
+ ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, 0x01);
+
+ for (slice = 0; slice < SLICE_CNT; slice++) {
+ ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_NUM,
+ 0x01);
+ ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_START,
+ 0x08);
+
+ if (high_byte[slice])
+ o_inv = o_mr20;
+ else
+ o_inv = o_mr15;
+
+ tmp = board_cnf->ch[ch].dq_swap[slice];
+ inv = 0;
+ j = 0;
+ for (bit_soc = 0; bit_soc < 8; bit_soc++) {
+ bit_mem = (tmp >> (4 * bit_soc)) & 0x0f;
+ j |= (1U << bit_mem);
+ if (o_inv & (1U << bit_mem))
+ inv |= (1U << bit_soc);
+ }
+ data_l = o_mr32_mr40;
+ if (!high_byte[slice])
+ data_l |= (inv << 24);
+ if (high_byte[slice])
+ data_l |= (inv << 16);
+ ddr_setval_s(ch, slice, _reg_PHY_LP4_RDLVL_PATT8,
+ data_l);
+ }
+ }
+}
+
+static void ddr_config(void)
+{
+ int32_t i;
+ uint32_t ch, slice;
+ uint32_t data_l;
+ uint32_t tmp;
+ int8_t _adj;
+ int16_t adj;
+ uint32_t dq;
+ union {
+ uint32_t ui32[4];
+ uint8_t ui8[16];
+ } patt;
+ uint16_t patm;
+
+ /* configure ddrphy registers */
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
+ ddr_config_sub_h3v1x();
+ } else { /* H3 Ver.2.0 or later/M3-N/V3H is same as M3-W */
+ ddr_config_sub();
+ }
+
+ /* WDQ_USER_PATT */
+ foreach_vch(ch) {
+ for (slice = 0; slice < SLICE_CNT; slice++) {
+ patm = 0;
+ for (i = 0; i < 16; i++) {
+ tmp = board_cnf->ch[ch].wdqlvl_patt[i];
+ patt.ui8[i] = tmp & 0xff;
+ if (tmp & 0x100)
+ patm |= (1U << i);
+ }
+ ddr_setval_s(ch, slice, _reg_PHY_USER_PATT0,
+ patt.ui32[0]);
+ ddr_setval_s(ch, slice, _reg_PHY_USER_PATT1,
+ patt.ui32[1]);
+ ddr_setval_s(ch, slice, _reg_PHY_USER_PATT2,
+ patt.ui32[2]);
+ ddr_setval_s(ch, slice, _reg_PHY_USER_PATT3,
+ patt.ui32[3]);
+ ddr_setval_s(ch, slice, _reg_PHY_USER_PATT4, patm);
+ }
+ }
+
+ /* CACS DLY */
+ data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj);
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
+ 0x00U);
+ foreach_vch(ch) {
+ for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4; i++) {
+ adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
+ ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET,
+ _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
+ data_l + adj);
+ reg_ddrphy_write(ch,
+ ddr_regdef_adr
+ (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]),
+ _cnf_DDR_PHY_ADR_V_REGSET
+ [ddr_regdef_adr
+ (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
+ DDR_PHY_ADR_V_REGSET_OFS]);
+ }
+
+ for (i = (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4);
+ i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
+ adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
+ ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
+ data_l + adj);
+ reg_ddrphy_write(ch,
+ ddr_regdef_adr
+ (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]),
+ _cnf_DDR_PHY_ADR_G_REGSET
+ [ddr_regdef_adr
+ (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
+ DDR_PHY_ADR_G_REGSET_OFS]);
+ }
+
+ if (ddr_phycaslice == 1) {
+ for (i = 0; i < 6; i++) {
+ adj = _f_scale_adj
+ (board_cnf->ch[ch].cacs_adj
+ [i +
+ _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]);
+ ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET,
+ _reg_PHY_CLK_CACS_SLAVE_DELAY_X
+ [i],
+ data_l + adj);
+ reg_ddrphy_write(ch,
+ ddr_regdef_adr
+ (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) +
+ 0x0100,
+ _cnf_DDR_PHY_ADR_V_REGSET
+ [ddr_regdef_adr
+ (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
+ DDR_PHY_ADR_V_REGSET_OFS]);
+ }
+ }
+ }
+
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
+ BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
+
+ /* WDQDM DLY */
+ data_l = board_cnf->dqdm_dly_w;
+ foreach_vch(ch) {
+ for (slice = 0; slice < SLICE_CNT; slice++) {
+ for (i = 0; i <= 8; i++) {
+ dq = slice * 8 + i;
+ if (i == 8)
+ _adj = board_cnf->ch[ch].dm_adj_w[slice];
+ else
+ _adj = board_cnf->ch[ch].dq_adj_w[dq];
+ adj = _f_scale_adj(_adj);
+ ddr_setval_s(ch, slice,
+ _reg_PHY_CLK_WRX_SLAVE_DELAY[i],
+ data_l + adj);
+ }
+ }
+ }
+
+ /* RDQDM DLY */
+ data_l = board_cnf->dqdm_dly_r;
+ foreach_vch(ch) {
+ for (slice = 0; slice < SLICE_CNT; slice++) {
+ for (i = 0; i <= 8; i++) {
+ dq = slice * 8 + i;
+ if (i == 8)
+ _adj = board_cnf->ch[ch].dm_adj_r[slice];
+ else
+ _adj = board_cnf->ch[ch].dq_adj_r[dq];
+ adj = _f_scale_adj(_adj);
+ ddr_setval_s(ch, slice,
+ _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY
+ [i], data_l + adj);
+ ddr_setval_s(ch, slice,
+ _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY
+ [i], data_l + adj);
+ }
+ }
+ }
+}
+
+/* DBSC register setting functions */
+static void dbsc_regset_pre(void)
+{
+ uint32_t ch, csab;
+ uint32_t data_l;
+
+ /* PRIMARY SETTINGS */
+ /* LPDDR4, BL=16, DFI interface */
+ mmio_write_32(DBSC_DBKIND, 0x0000000a);
+ mmio_write_32(DBSC_DBBL, 0x00000002);
+ mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
+
+ /* FREQRATIO=2 */
+ mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
+
+ /* Chanel map (H3 Ver.1.x) */
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11))
+ mmio_write_32(DBSC_DBSCHCNT1, 0x00001010);
+
+ /* DRAM SIZE REGISTER:
+ * set all ranks as density=0(4Gb) for PHY initialization
+ */
+ foreach_vch(ch) {
+ for (csab = 0; csab < 4; csab++) {
+ mmio_write_32(DBSC_DBMEMCONF(ch, csab),
+ DBMEMCONF_REGD(0));
+ }
+ }
+
+ if (prr_product == PRR_PRODUCT_M3) {
+ data_l = 0xe4e4e4e4;
+ foreach_ech(ch) {
+ if ((ddr_phyvalid & (1U << ch)))
+ data_l = (data_l & (~(0x000000FF << (ch * 8))))
+ | (((board_cnf->ch[ch].dqs_swap & 0x0003)
+ | ((board_cnf->ch[ch].dqs_swap & 0x0030)
+ >> 2)
+ | ((board_cnf->ch[ch].dqs_swap & 0x0300)
+ >> 4)
+ | ((board_cnf->ch[ch].dqs_swap & 0x3000)
+ >> 6)) << (ch * 8));
+ }
+ mmio_write_32(DBSC_DBBSWAP, data_l);
+ }
+}
+
+static void dbsc_regset(void)
+{
+ int32_t i;
+ uint32_t ch;
+ uint32_t data_l;
+ uint32_t data_l2;
+ uint32_t tmp[4];
+
+ /* RFC */
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_20) &&
+ (max_density == 0)) {
+ js2[js2_trfcab] =
+ _f_scale(ddr_mbps, ddr_mbpsdiv,
+ 1UL * jedec_spec2_trfc_ab[1] * 1000, 0);
+ } else {
+ js2[js2_trfcab] =
+ _f_scale(ddr_mbps, ddr_mbpsdiv,
+ 1UL * jedec_spec2_trfc_ab[max_density] *
+ 1000, 0);
+ }
+
+ /* DBTR0.CL : RL */
+ mmio_write_32(DBSC_DBTR(0), RL);
+
+ /* DBTR1.CWL : WL */
+ mmio_write_32(DBSC_DBTR(1), WL);
+
+ /* DBTR2.AL : 0 */
+ mmio_write_32(DBSC_DBTR(2), 0);
+
+ /* DBTR3.TRCD: tRCD */
+ mmio_write_32(DBSC_DBTR(3), js2[js2_trcd]);
+
+ /* DBTR4.TRPA,TRP: tRPab,tRPpb */
+ mmio_write_32(DBSC_DBTR(4), (js2[js2_trpab] << 16) | js2[js2_trppb]);
+
+ /* DBTR5.TRC : use tRCpb */
+ mmio_write_32(DBSC_DBTR(5), js2[js2_trcpb]);
+
+ /* DBTR6.TRAS : tRAS */
+ mmio_write_32(DBSC_DBTR(6), js2[js2_tras]);
+
+ /* DBTR7.TRRD : tRRD */
+ mmio_write_32(DBSC_DBTR(7), (js2[js2_trrd] << 16) | js2[js2_trrd]);
+
+ /* DBTR8.TFAW : tFAW */
+ mmio_write_32(DBSC_DBTR(8), js2[js2_tfaw]);
+
+ /* DBTR9.TRDPR : tRTP */
+ mmio_write_32(DBSC_DBTR(9), js2[js2_trtp]);
+
+ /* DBTR10.TWR : nWR */
+ mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nwr);
+
+ /*
+ * DBTR11.TRDWR : RL + BL / 2 + Rounddown(tRPST) + PHY_ODTLoff -
+ * odtlon + tDQSCK - tODTon,min +
+ * PCB delay (out+in) + tPHY_ODToff
+ */
+ mmio_write_32(DBSC_DBTR(11),
+ RL + (16 / 2) + 1 + 2 - js1[js1_ind].odtlon +
+ js2[js2_tdqsck] - js2[js2_tODTon_min] +
+ _f_scale(ddr_mbps, ddr_mbpsdiv, 1300, 0));
+
+ /* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */
+ data_l = WL + 1 + (16 / 2) + js2[js2_twtr];
+ mmio_write_32(DBSC_DBTR(12), (data_l << 16) | data_l);
+
+ /* DBTR13.TRFCAB : tRFCab */
+ mmio_write_32(DBSC_DBTR(13), (js2[js2_trfcab]));
+
+ /* DBTR14.TCKEHDLL,tCKEH : tCKEHCMD,tCKEHCMD */
+ mmio_write_32(DBSC_DBTR(14),
+ (js2[js2_tckehcmd] << 16) | (js2[js2_tckehcmd]));
+
+ /* DBTR15.TCKESR,TCKEL : tSR,tCKELPD */
+ mmio_write_32(DBSC_DBTR(15), (js2[js2_tsr] << 16) | (js2[js2_tckelpd]));
+
+ /* DBTR16 */
+ /* WDQL : tphy_wrlat + tphy_wrdata */
+ tmp[0] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1);
+ /* DQENLTNCY : tphy_wrlat = WL-2 : PHY_WRITE_PATH_LAT_ADD == 0
+ * tphy_wrlat = WL-3 : PHY_WRITE_PATH_LAT_ADD != 0
+ */
+ tmp[1] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1);
+ /* DQL : tphy_rdlat + trdata_en */
+ /* it is not important for dbsc */
+ tmp[2] = RL + 16;
+ /* DQIENLTNCY : trdata_en */
+ tmp[3] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1) - 1;
+ mmio_write_32(DBSC_DBTR(16),
+ (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]);
+
+ /* DBTR24 */
+ /* WRCSLAT = WRLAT -5 */
+ tmp[0] -= 5;
+ /* WRCSGAP = 5 */
+ tmp[1] = 5;
+ /* RDCSLAT = RDLAT_ADJ +2 */
+ if (prr_product == PRR_PRODUCT_M3) {
+ tmp[2] = tmp[3];
+ } else {
+ tmp[2] = tmp[3] + 2;
+ }
+ /* RDCSGAP = 6 */
+ if (prr_product == PRR_PRODUCT_M3) {
+ tmp[3] = 4;
+ } else {
+ tmp[3] = 6;
+ }
+ mmio_write_32(DBSC_DBTR(24),
+ (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]);
+
+ /* DBTR17.TMODRD,TMOD,TRDMR: tMRR,tMRD,(0) */
+ mmio_write_32(DBSC_DBTR(17),
+ (js2[js2_tmrr] << 24) | (js2[js2_tmrd] << 16));
+
+ /* DBTR18.RODTL, RODTA, WODTL, WODTA : do not use in LPDDR4 */
+ mmio_write_32(DBSC_DBTR(18), 0);
+
+ /* DBTR19.TZQCL, TZQCS : do not use in LPDDR4 */
+ mmio_write_32(DBSC_DBTR(19), 0);
+
+ /* DBTR20.TXSDLL, TXS : tRFCab+tCKEHCMD */
+ data_l = js2[js2_trfcab] + js2[js2_tckehcmd];
+ mmio_write_32(DBSC_DBTR(20), (data_l << 16) | data_l);
+
+ /* DBTR21.TCCD */
+ /* DBTR23.TCCD */
+ /* H3 Ver.1.0 cannot use TBTR23 feature */
+ if (ddr_tccd == 8 &&
+ !((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_10))
+ ) {
+ data_l = 8;
+ mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
+ mmio_write_32(DBSC_DBTR(23), 0x00000002);
+ } else if (ddr_tccd <= 11) {
+ data_l = 11;
+ mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
+ mmio_write_32(DBSC_DBTR(23), 0x00000000);
+ } else {
+ data_l = ddr_tccd;
+ mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
+ mmio_write_32(DBSC_DBTR(23), 0x00000000);
+ }
+
+ /* DBTR22.ZQLAT : */
+ data_l = js2[js2_tzqcalns] * 100; /* 1000 * 1000 ps */
+ data_l = (data_l << 16) | (js2[js2_tzqlat] + 24 + 20);
+ mmio_write_32(DBSC_DBTR(22), data_l);
+
+ /* DBTR25 : do not use in LPDDR4 */
+ mmio_write_32(DBSC_DBTR(25), 0);
+
+ /* DBRNK : */
+ /*
+ * DBSC_DBRNK2 rkrr
+ * DBSC_DBRNK3 rkrw
+ * DBSC_DBRNK4 rkwr
+ * DBSC_DBRNK5 rkww
+ */
+#define _par_DBRNK_VAL (0x7007)
+
+ for (i = 0; i < 4; i++) {
+ data_l = (_par_DBRNK_VAL >> (i * 4)) & 0x0f;
+ if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut > PRR_PRODUCT_11) && (i == 0)) {
+ data_l += 1;
+ }
+ data_l2 = 0;
+ foreach_vch(ch) {
+ data_l2 = data_l2 | (data_l << (4 * ch));
+ }
+ mmio_write_32(DBSC_DBRNK(2 + i), data_l2);
+ }
+ mmio_write_32(DBSC_DBADJ0, 0x00000000);
+
+ /* timing registers for Scheduler */
+ /* SCFCTST0 */
+ /* SCFCTST0 ACT-ACT */
+ tmp[3] = 1UL * js2[js2_trcpb] * 800 * ddr_mbpsdiv / ddr_mbps;
+ /* SCFCTST0 RDA-ACT */
+ tmp[2] =
+ 1UL * ((16 / 2) + js2[js2_trtp] - 8 +
+ js2[js2_trppb]) * 800 * ddr_mbpsdiv / ddr_mbps;
+ /* SCFCTST0 WRA-ACT */
+ tmp[1] =
+ 1UL * (WL + 1 + (16 / 2) +
+ js1[js1_ind].nwr) * 800 * ddr_mbpsdiv / ddr_mbps;
+ /* SCFCTST0 PRE-ACT */
+ tmp[0] = 1UL * js2[js2_trppb];
+ mmio_write_32(DBSC_SCFCTST0,
+ (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]);
+
+ /* SCFCTST1 */
+ /* SCFCTST1 RD-WR */
+ tmp[3] =
+ 1UL * (mmio_read_32(DBSC_DBTR(11)) & 0xff) * 800 * ddr_mbpsdiv /
+ ddr_mbps;
+ /* SCFCTST1 WR-RD */
+ tmp[2] =
+ 1UL * (mmio_read_32(DBSC_DBTR(12)) & 0xff) * 800 * ddr_mbpsdiv /
+ ddr_mbps;
+ /* SCFCTST1 ACT-RD/WR */
+ tmp[1] = 1UL * js2[js2_trcd] * 800 * ddr_mbpsdiv / ddr_mbps;
+ /* SCFCTST1 ASYNCOFS */
+ tmp[0] = 12;
+ mmio_write_32(DBSC_SCFCTST1,
+ (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]);
+
+ /* DBSCHRW1 */
+ /* DBSCHRW1 SCTRFCAB */
+ tmp[0] = 1UL * js2[js2_trfcab] * 800 * ddr_mbpsdiv / ddr_mbps;
+ data_l = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000) >> 16)
+ + (mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF)
+ + (0x28 * 2)) * 400 * 2 * ddr_mbpsdiv / ddr_mbps + 7;
+ if (tmp[0] < data_l)
+ tmp[0] = data_l;
+
+ if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) {
+ mmio_write_32(DBSC_DBSCHRW1, tmp[0]
+ + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF)
+ * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) /
+ ddr_mbps - 3);
+ } else {
+ mmio_write_32(DBSC_DBSCHRW1, tmp[0]
+ + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF)
+ * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) /
+ ddr_mbps);
+ }
+
+ /* QOS and CAM */
+#ifdef ddr_qos_init_setting /* only for non qos_init */
+ /*wbkwait(0004), wbkmdhi(4,2),wbkmdlo(1,8) */
+ mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218);
+ /*0(fillunit),8(dirtymax),4(dirtymin) */
+ mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4);
+ /*stop_tolerance */
+ mmio_write_32(DBSC_DBSCHRW0, 0x22421111);
+ /*rd-wr/wr-rd toggle priority */
+ mmio_write_32(DBSC_SCFCTST2, 0x012F1123);
+ mmio_write_32(DBSC_DBSCHSZ0, 0x00000001);
+ mmio_write_32(DBSC_DBSCHCNT0, 0x000F0037);
+
+ /* QoS Settings */
+ mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
+ mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
+ mmio_write_32(DBSC_DBSCHQOS02, 0x00000000U);
+ mmio_write_32(DBSC_DBSCHQOS03, 0x00000000U);
+ mmio_write_32(DBSC_DBSCHQOS40, 0x00000300U);
+ mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
+ mmio_write_32(DBSC_DBSCHQOS42, 0x00000200U);
+ mmio_write_32(DBSC_DBSCHQOS43, 0x00000100U);
+ mmio_write_32(DBSC_DBSCHQOS90, 0x00000100U);
+ mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
+ mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
+ mmio_write_32(DBSC_DBSCHQOS93, 0x00000040U);
+ mmio_write_32(DBSC_DBSCHQOS120, 0x00000040U);
+ mmio_write_32(DBSC_DBSCHQOS121, 0x00000030U);
+ mmio_write_32(DBSC_DBSCHQOS122, 0x00000020U);
+ mmio_write_32(DBSC_DBSCHQOS123, 0x00000010U);
+ mmio_write_32(DBSC_DBSCHQOS130, 0x00000100U);
+ mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
+ mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
+ mmio_write_32(DBSC_DBSCHQOS133, 0x00000040U);
+ mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
+ mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
+ mmio_write_32(DBSC_DBSCHQOS142, 0x00000080U);
+ mmio_write_32(DBSC_DBSCHQOS143, 0x00000040U);
+ mmio_write_32(DBSC_DBSCHQOS150, 0x00000040U);
+ mmio_write_32(DBSC_DBSCHQOS151, 0x00000030U);
+ mmio_write_32(DBSC_DBSCHQOS152, 0x00000020U);
+ mmio_write_32(DBSC_DBSCHQOS153, 0x00000010U);
+
+ mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif /* ddr_qos_init_setting */
+ /* H3 Ver.1.1 need to set monitor function */
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) {
+ mmio_write_32(DBSC_DBMONCONF4, 0x00700000);
+ }
+
+ if (prr_product == PRR_PRODUCT_H3) {
+ if (prr_cut == PRR_PRODUCT_10) {
+ /* resrdis, simple mode, sc off */
+ mmio_write_32(DBSC_DBBCAMDIS, 0x00000007);
+ } else if (prr_cut == PRR_PRODUCT_11) {
+ /* resrdis, simple mode */
+ mmio_write_32(DBSC_DBBCAMDIS, 0x00000005);
+ } else if (prr_cut < PRR_PRODUCT_30) {
+ /* H3 Ver.2.0 */
+ /* resrdis */
+ mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
+ } else { /* H3 Ver.3.0(include H3N) */
+ /* exprespque */
+ mmio_write_32(DBSC_DBBCAMDIS, 0x00000010);
+ }
+ } else { /* M3-W/M3-N/V3H */
+ /* resrdis */
+ mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
+ }
+}
+
+static void dbsc_regset_post(void)
+{
+ uint32_t ch, cs;
+ uint32_t data_l;
+ uint32_t slice, rdlat_max, rdlat_min;
+
+ rdlat_max = 0;
+ rdlat_min = 0xffff;
+ foreach_vch(ch) {
+ for (cs = 0; cs < CS_CNT; cs++) {
+ if ((ch_have_this_cs[cs] & (1U << ch)) != 0) {
+ for (slice = 0; slice < SLICE_CNT; slice++) {
+ ddr_setval_s(ch, slice,
+ _reg_PHY_PER_CS_TRAINING_INDEX,
+ cs);
+ data_l = ddr_getval_s(ch, slice,
+ _reg_PHY_RDDQS_LATENCY_ADJUST);
+ if (data_l > rdlat_max)
+ rdlat_max = data_l;
+ if (data_l < rdlat_min)
+ rdlat_min = data_l;
+ }
+ }
+ }
+ }
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) {
+#if RCAR_DRAM_SPLIT == 2
+ if (board_cnf->phyvalid == 0x05) {
+ mmio_write_32(DBSC_DBTR(24),
+ (rdlat_max << 24) + (rdlat_min << 16) +
+ mmio_read_32(DBSC_DBTR(24)));
+ } else {
+ mmio_write_32(DBSC_DBTR(24),
+ ((rdlat_max * 2 - rdlat_min + 4) << 24) +
+ ((rdlat_min + 2) << 16) +
+ mmio_read_32(DBSC_DBTR(24)));
+ }
+#else /*RCAR_DRAM_SPLIT == 2 */
+ mmio_write_32(DBSC_DBTR(24),
+ ((rdlat_max * 2 - rdlat_min + 4) << 24) +
+ ((rdlat_min + 2) << 16) +
+ mmio_read_32(DBSC_DBTR(24)));
+#endif /*RCAR_DRAM_SPLIT == 2 */
+ } else {
+ mmio_write_32(DBSC_DBTR(24),
+ ((rdlat_max + 2) << 24) +
+ ((rdlat_max + 2) << 16) +
+ mmio_read_32(DBSC_DBTR(24)));
+ }
+
+ /* set ddr density information */
+ foreach_ech(ch) {
+ for (cs = 0; cs < CS_CNT; cs++) {
+ if (ddr_density[ch][cs] == 0xff) {
+ mmio_write_32(DBSC_DBMEMCONF(ch, cs), 0x00);
+ } else {
+ mmio_write_32(DBSC_DBMEMCONF(ch, cs),
+ DBMEMCONF_REGD(ddr_density[ch]
+ [cs]));
+ }
+ }
+ mmio_write_32(DBSC_DBMEMCONF(ch, 2), 0x00000000);
+ mmio_write_32(DBSC_DBMEMCONF(ch, 3), 0x00000000);
+ }
+
+ mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
+
+ /*set DBI */
+ if (board_cnf->dbi_en)
+ mmio_write_32(DBSC_DBDBICNT, 0x00000003);
+
+ /* H3 Ver.2.0 or later/M3-N/V3H DBI wa */
+ if ((((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut > PRR_PRODUCT_11)) ||
+ (prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) &&
+ board_cnf->dbi_en)
+ reg_ddrphy_write_a(0x00001010, 0x01000000);
+
+ /*set REFCYCLE */
+ data_l = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv;
+ mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (data_l & 0x0000ffff));
+ mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS);
+
+#if RCAR_REWT_TRAINING != 0
+ /* Periodic-WriteDQ Training seeting */
+ if (((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) ||
+ ((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut == PRR_PRODUCT_10))) {
+ /* non : H3 Ver.1.x/M3-W Ver.1.0 not support */
+ } else {
+ /* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H */
+ mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000);
+
+ ddr_setval_ach_as(_reg_PHY_WDQLVL_PATT, 0x04);
+ ddr_setval_ach_as(_reg_PHY_WDQLVL_QTR_DLY_STEP, 0x0F);
+ ddr_setval_ach_as(_reg_PHY_WDQLVL_DLY_STEP, 0x50);
+ ddr_setval_ach_as(_reg_PHY_WDQLVL_DQDM_SLV_DLY_START, 0x0300);
+
+ ddr_setval_ach(_reg_PI_WDQLVL_CS_MAP,
+ ddrtbl_getval(_cnf_DDR_PI_REGSET,
+ _reg_PI_WDQLVL_CS_MAP));
+ ddr_setval_ach(_reg_PI_LONG_COUNT_MASK, 0x1f);
+ ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00);
+ ddr_setval_ach(_reg_PI_WDQLVL_ROTATE, 0x01);
+ ddr_setval_ach(_reg_PI_TREF_F0, 0x0000);
+ ddr_setval_ach(_reg_PI_TREF_F1, 0x0000);
+ ddr_setval_ach(_reg_PI_TREF_F2, 0x0000);
+
+ if (prr_product == PRR_PRODUCT_M3) {
+ ddr_setval_ach(_reg_PI_WDQLVL_EN, 0x02);
+ } else {
+ ddr_setval_ach(_reg_PI_WDQLVL_EN_F1, 0x02);
+ }
+ ddr_setval_ach(_reg_PI_WDQLVL_PERIODIC, 0x01);
+
+ /* DFI_PHYMSTR_ACK , WTmode setting */
+ /* DFI_PHYMSTR_ACK: WTmode =b'01 */
+ mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011);
+ }
+#endif /* RCAR_REWT_TRAINING */
+ /* periodic dram zqcal enable */
+ mmio_write_32(DBSC_DBCALCNF, 0x01000010);
+
+ /* periodic phy ctrl update enable */
+ if (((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) ||
+ ((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut < PRR_PRODUCT_30))) {
+ /* non : H3 Ver.1.x/M3-W Ver.1.x not support */
+ } else {
+#if RCAR_DRAM_SPLIT == 2
+ if ((prr_product == PRR_PRODUCT_H3) &&
+ (board_cnf->phyvalid == 0x05))
+ mmio_write_32(DBSC_DBDFICUPDCNF, 0x2a240001);
+ else
+ mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001);
+#else /* RCAR_DRAM_SPLIT == 2 */
+ mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001);
+#endif /* RCAR_DRAM_SPLIT == 2 */
+ }
+
+#ifdef DDR_BACKUPMODE
+ /* SRX */
+ if (ddr_backup == DRAM_BOOT_STATUS_WARM) {
+#ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0, 1 only) */
+ NOTICE("BL2: [DEBUG_MESS] DDR_BACKUPMODE_HALF\n");
+ send_dbcmd(0x0A040001);
+ if (Prr_Product == PRR_PRODUCT_H3)
+ send_dbcmd(0x0A140001);
+#else /* DDR_BACKUPMODE_HALF */ /* for All channels */
+ send_dbcmd(0x0A840001);
+#endif /* DDR_BACKUPMODE_HALF */
+ }
+#endif /* DDR_BACKUPMODE */
+
+ /* set Auto Refresh */
+ mmio_write_32(DBSC_DBRFEN, 0x00000001);
+
+#if RCAR_REWT_TRAINING != 0
+ /* Periodic WriteDQ Traning */
+ if (((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) ||
+ ((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut == PRR_PRODUCT_10))) {
+ /* non : H3 Ver.1.x/M3-W Ver.1.0 not support */
+ } else {
+ /* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H */
+ ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, 0x0100);
+ }
+#endif /* RCAR_REWT_TRAINING */
+
+ /* dram access enable */
+ mmio_write_32(DBSC_DBACEN, 0x00000001);
+
+ MSG_LF(__func__ "(done)");
+}
+
+/* DFI_INIT_START */
+static uint32_t dfi_init_start(void)
+{
+ uint32_t ch;
+ uint32_t phytrainingok;
+ uint32_t retry;
+ uint32_t data_l;
+ const uint32_t RETRY_MAX = 0x10000;
+
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
+ /* PLL3 Disable */
+ /* protect register interface */
+ ddrphy_regif_idle();
+
+ pll3_control(0);
+
+ /* init start */
+ /* dbdficnt0:
+ * dfi_dram_clk_disable=1
+ * dfi_frequency = 0
+ * freq_ratio = 01 (2:1)
+ * init_start =0
+ */
+ foreach_vch(ch)
+ mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10);
+ dsb_sev();
+
+ /* dbdficnt0:
+ * dfi_dram_clk_disable=1
+ * dfi_frequency = 0
+ * freq_ratio = 01 (2:1)
+ * init_start =1
+ */
+ foreach_vch(ch)
+ mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11);
+ dsb_sev();
+
+ } else {
+ ddr_setval_ach_as(_reg_PHY_DLL_RST_EN, 0x02);
+ dsb_sev();
+ ddrphy_regif_idle();
+ }
+
+ /* dll_rst negate */
+ foreach_vch(ch)
+ mmio_write_32(DBSC_DBPDCNT3(ch), 0x0000CF01);
+ dsb_sev();
+
+ /* wait init_complete */
+ phytrainingok = 0;
+ retry = 0;
+ while (retry++ < RETRY_MAX) {
+ foreach_vch(ch) {
+ data_l = mmio_read_32(DBSC_DBDFISTAT(ch));
+ if (data_l & 0x00000001)
+ phytrainingok |= (1U << ch);
+ }
+ dsb_sev();
+ if (phytrainingok == ddr_phyvalid)
+ break;
+ if (retry % 256 == 0)
+ ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01);
+ }
+
+ /* all ch ok? */
+ if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid)
+ return 0xff;
+
+ /* dbdficnt0:
+ * dfi_dram_clk_disable=0
+ * dfi_frequency = 0
+ * freq_ratio = 01 (2:1)
+ * init_start =0
+ */
+ foreach_vch(ch)
+ mmio_write_32(DBSC_DBDFICNT(ch), 0x00000010);
+ dsb_sev();
+
+ return 0;
+}
+
+/* drivablity setting : CMOS MODE ON/OFF */
+static void change_lpddr4_en(uint32_t mode)
+{
+ uint32_t ch;
+ uint32_t i;
+ uint32_t data_l;
+ const uint32_t _reg_PHY_PAD_DRIVE_X[3] = {
+ _reg_PHY_PAD_ADDR_DRIVE,
+ _reg_PHY_PAD_CLK_DRIVE,
+ _reg_PHY_PAD_CS_DRIVE
+ };
+
+ foreach_vch(ch) {
+ for (i = 0; i < 3; i++) {
+ data_l = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]);
+ if (mode) {
+ data_l |= (1U << 14);
+ } else {
+ data_l &= ~(1U << 14);
+ }
+ ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], data_l);
+ }
+ }
+}
+
+/* drivablity setting */
+static uint32_t set_term_code(void)
+{
+ int32_t i;
+ uint32_t ch, index;
+ uint32_t data_l;
+ uint32_t chip_id[2];
+ uint32_t term_code;
+ uint32_t override;
+ uint32_t pvtr;
+ uint32_t pvtp;
+ uint32_t pvtn;
+
+ term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_PAD_DATA_TERM);
+ override = 0;
+ for (i = 0; i < 2; i++)
+ chip_id[i] = mmio_read_32(LIFEC_CHIPID(i));
+
+ index = 0;
+ while (1) {
+ if (termcode_by_sample[index][0] == 0xffffffff) {
+ break;
+ }
+ if ((termcode_by_sample[index][0] == chip_id[0]) &&
+ (termcode_by_sample[index][1] == chip_id[1])) {
+ term_code = termcode_by_sample[index][2];
+ override = 1;
+ break;
+ }
+ index++;
+ }
+
+ if (override) {
+ for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) {
+ data_l =
+ ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_PAD_TERM_X[index]);
+ data_l = (data_l & 0xfffe0000) | term_code;
+ ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], data_l);
+ }
+ } else if ((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut == PRR_PRODUCT_10)) {
+ /* non */
+ } else {
+ ddr_setval_ach(_reg_PHY_PAD_TERM_X[0],
+ (ddrtbl_getval
+ (_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_PAD_TERM_X[0]) & 0xFFFE0000));
+ ddr_setval_ach(_reg_PHY_CAL_CLEAR_0, 0x01);
+ ddr_setval_ach(_reg_PHY_CAL_START_0, 0x01);
+ foreach_vch(ch) {
+ do {
+ data_l =
+ ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0);
+ } while (!(data_l & 0x00800000));
+ }
+ if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) {
+ foreach_vch(ch) {
+ data_l = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]);
+ pvtr = (data_l >> 12) & 0x1f;
+ pvtr += 8;
+ if (pvtr > 0x1f)
+ pvtr = 0x1f;
+ data_l =
+ ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0);
+ pvtn = (data_l >> 6) & 0x03f;
+ pvtp = (data_l >> 0) & 0x03f;
+
+ for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM;
+ index++) {
+ data_l =
+ ddrtbl_getval
+ (_cnf_DDR_PHY_ADR_G_REGSET,
+ _reg_PHY_PAD_TERM_X[index]);
+ data_l = (data_l & 0xfffe0000)
+ | (pvtr << 12)
+ | (pvtn << 6)
+ | (pvtp);
+ ddr_setval(ch,
+ _reg_PHY_PAD_TERM_X[index],
+ data_l);
+ }
+ }
+ } else {
+ /* M3-W Ver.1.1 or later/H3 Ver.2.0 or later/M3-N/V3H */
+ foreach_vch(ch) {
+ for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM;
+ index++) {
+ data_l =
+ ddr_getval(ch,
+ _reg_PHY_PAD_TERM_X
+ [index]);
+ ddr_setval(ch,
+ _reg_PHY_PAD_TERM_X[index],
+ (data_l & 0xFFFE0FFF) |
+ 0x00015000);
+ }
+ }
+ }
+ }
+
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
+ /* non */
+ } else {
+ ddr_padcal_tcompensate_getinit(override);
+ }
+
+ return 0;
+}
+
+/* DDR mode register setting */
+static void ddr_register_set(void)
+{
+ int32_t fspwp;
+ uint32_t tmp;
+
+ for (fspwp = 1; fspwp >= 0; fspwp--) {
+ /*MR13, fspwp */
+ send_dbcmd(0x0e840d08 | ((2 - fspwp) << 6));
+
+ tmp =
+ ddrtbl_getval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr1_data_fx_csx[fspwp][0]);
+ send_dbcmd(0x0e840100 | tmp);
+
+ tmp =
+ ddrtbl_getval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr2_data_fx_csx[fspwp][0]);
+ send_dbcmd(0x0e840200 | tmp);
+
+ tmp =
+ ddrtbl_getval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr3_data_fx_csx[fspwp][0]);
+ send_dbcmd(0x0e840300 | tmp);
+
+ tmp =
+ ddrtbl_getval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr11_data_fx_csx[fspwp][0]);
+ send_dbcmd(0x0e840b00 | tmp);
+
+ tmp =
+ ddrtbl_getval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr12_data_fx_csx[fspwp][0]);
+ send_dbcmd(0x0e840c00 | tmp);
+
+ tmp =
+ ddrtbl_getval(_cnf_DDR_PI_REGSET,
+ reg_pi_mr14_data_fx_csx[fspwp][0]);
+ send_dbcmd(0x0e840e00 | tmp);
+ /* MR22 */
+ send_dbcmd(0x0e841616);
+
+ /* ZQCAL start */
+ send_dbcmd(0x0d84004F);
+
+ /* ZQLAT */
+ send_dbcmd(0x0d840051);
+ }
+
+ /* MR13, fspwp */
+ send_dbcmd(0x0e840d08);
+}
+
+/* Training handshake functions */
+static inline uint32_t wait_freqchgreq(uint32_t assert)
+{
+ uint32_t data_l;
+ uint32_t count;
+ uint32_t ch;
+
+ count = 100000;
+
+ /* H3 Ver.1.x cannot see frqchg_req */
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
+ return 0;
+ }
+
+ if (assert) {
+ do {
+ data_l = 1;
+ foreach_vch(ch) {
+ data_l &= mmio_read_32(DBSC_DBPDSTAT(ch));
+ }
+ count = count - 1;
+ } while (((data_l & 0x01) != 0x01) & (count != 0));
+ } else {
+ do {
+ data_l = 0;
+ foreach_vch(ch) {
+ data_l |= mmio_read_32(DBSC_DBPDSTAT(ch));
+ }
+ count = count - 1;
+ } while (((data_l & 0x01) != 0x00) & (count != 0));
+ }
+
+ return (count == 0);
+}
+
+static inline void set_freqchgack(uint32_t assert)
+{
+ uint32_t ch;
+ uint32_t data_l;
+
+ if (assert)
+ data_l = 0x0CF20000;
+ else
+ data_l = 0x00000000;
+
+ foreach_vch(ch)
+ mmio_write_32(DBSC_DBPDCNT2(ch), data_l);
+}
+
+static inline void set_dfifrequency(uint32_t freq)
+{
+ uint32_t ch;
+
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
+ foreach_vch(ch)
+ mmio_clrsetbits_32(DBSC_DBPDCNT1(ch), 0x1fU, freq);
+ } else {
+ foreach_vch(ch) {
+ mmio_clrsetbits_32(DBSC_DBDFICNT(ch), 0x1fU << 24,
+ (freq << 24));
+ }
+ }
+ dsb_sev();
+}
+
+static uint32_t pll3_freq(uint32_t on)
+{
+ uint32_t timeout;
+
+ timeout = wait_freqchgreq(1);
+
+ if (timeout) {
+ return 1;
+ }
+
+ pll3_control(on);
+ set_dfifrequency(on);
+
+ set_freqchgack(1);
+ timeout = wait_freqchgreq(0);
+ set_freqchgack(0);
+
+ if (timeout) {
+ FATAL_MSG("BL2: Time out[2]\n");
+ return 1;
+ }
+ return 0;
+}
+
+/* update dly */
+static void update_dly(void)
+{
+ ddr_setval_ach(_reg_SC_PHY_MANUAL_UPDATE, 0x01);
+ ddr_setval_ach(_reg_PHY_ADRCTL_MANUAL_UPDATE, 0x01);
+}
+
+/* training by pi */
+static uint32_t pi_training_go(void)
+{
+ uint32_t flag;
+ uint32_t data_l;
+ uint32_t retry;
+ const uint32_t RETRY_MAX = 4096 * 16;
+ uint32_t ch;
+
+ uint32_t mst_ch;
+ uint32_t cur_frq;
+ uint32_t complete;
+ uint32_t frqchg_req;
+
+ /* pi_start */
+ ddr_setval_ach(_reg_PI_START, 0x01);
+ foreach_vch(ch)
+ ddr_getval(ch, _reg_PI_INT_STATUS);
+
+ /* set dfi_phymstr_ack = 1 */
+ mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001);
+ dsb_sev();
+
+ /* wait pi_int_status[0] */
+ mst_ch = 0;
+ flag = 0;
+ complete = 0;
+ cur_frq = 0;
+ retry = RETRY_MAX;
+ do {
+ frqchg_req = mmio_read_32(DBSC_DBPDSTAT(mst_ch)) & 0x01;
+
+ /* H3 Ver.1.x cannot see frqchg_req */
+ if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) {
+ if ((retry % 4096) == 1) {
+ frqchg_req = 1;
+ } else {
+ frqchg_req = 0;
+ }
+ }
+
+ if (frqchg_req) {
+ if (cur_frq) {
+ /* Low frequency */
+ flag = pll3_freq(0);
+ cur_frq = 0;
+ } else {
+ /* High frequency */
+ flag = pll3_freq(1);
+ cur_frq = 1;
+ }
+ if (flag)
+ break;
+ } else {
+ if (cur_frq) {
+ foreach_vch(ch) {
+ if (complete & (1U << ch))
+ continue;
+ data_l =
+ ddr_getval(ch, _reg_PI_INT_STATUS);
+ if (data_l & 0x01) {
+ complete |= (1U << ch);
+ }
+ }
+ if (complete == ddr_phyvalid)
+ break;
+ }
+ }
+ } while (--retry);
+ foreach_vch(ch) {
+ /* dummy read */
+ data_l = ddr_getval_s(ch, 0, _reg_PHY_CAL_RESULT2_OBS_0);
+ data_l = ddr_getval(ch, _reg_PI_INT_STATUS);
+ ddr_setval(ch, _reg_PI_INT_ACK, data_l);
+ }
+ if (ddrphy_regif_chk()) {
+ return 0xfd;
+ }
+ return complete;
+}
+
+/* Initialize DDR */
+static uint32_t init_ddr(void)
+{
+ int32_t i;
+ uint32_t data_l;
+ uint32_t phytrainingok;
+ uint32_t ch, slice;
+ uint32_t err;
+ int16_t adj;
+
+ MSG_LF(__func__ ":0\n");
+
+#ifdef DDR_BACKUPMODE
+ rcar_dram_get_boot_status(&ddr_backup);
+#endif
+
+ /* unlock phy */
+ /* Unlock DDRPHY register(AGAIN) */
+ foreach_vch(ch)
+ mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55A);
+ dsb_sev();
+
+ if ((((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut > PRR_PRODUCT_11)) ||
+ (prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) && board_cnf->dbi_en)
+ reg_ddrphy_write_a(0x00001010, 0x01000001);
+ else
+ reg_ddrphy_write_a(0x00001010, 0x00000001);
+ /* DBSC register pre-setting */
+ dbsc_regset_pre();
+
+ /* load ddrphy registers */
+
+ ddrtbl_load();
+
+ /* configure ddrphy registers */
+ ddr_config();
+
+ /* dfi_reset assert */
+ foreach_vch(ch)
+ mmio_write_32(DBSC_DBPDCNT0(ch), 0x01);
+ dsb_sev();
+
+ /* dbsc register set */
+ dbsc_regset();
+ MSG_LF(__func__ ":1\n");
+
+ /* dfi_reset negate */
+ foreach_vch(ch)
+ mmio_write_32(DBSC_DBPDCNT0(ch), 0x00);
+ dsb_sev();
+
+ /* dfi_init_start (start ddrphy) */
+ err = dfi_init_start();
+ if (err) {
+ return INITDRAM_ERR_I;
+ }
+ MSG_LF(__func__ ":2\n");
+
+ /* ddr backupmode end */
+#ifdef DDR_BACKUPMODE
+ if (ddr_backup) {
+ NOTICE("BL2: [WARM_BOOT]\n");
+ } else {
+ NOTICE("BL2: [COLD_BOOT]\n");
+ }
+ err = rcar_dram_update_boot_status(ddr_backup);
+ if (err) {
+ NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n");
+ return INITDRAM_ERR_I;
+ }
+#endif
+ MSG_LF(__func__ ":3\n");
+
+ /* override term code after dfi_init_complete */
+ err = set_term_code();
+ if (err) {
+ return INITDRAM_ERR_I;
+ }
+ MSG_LF(__func__ ":4\n");
+
+ /* rx offset calibration */
+ if ((prr_cut > PRR_PRODUCT_11) || (prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
+ err = rx_offset_cal_hw();
+ } else {
+ err = rx_offset_cal();
+ }
+ if (err)
+ return INITDRAM_ERR_O;
+ MSG_LF(__func__ ":5\n");
+
+ /* Dummy PDE */
+ send_dbcmd(0x08840000);
+
+ /* PDX */
+ send_dbcmd(0x08840001);
+
+ /* check register i/f is alive */
+ err = ddrphy_regif_chk();
+ if (err) {
+ return INITDRAM_ERR_O;
+ }
+ MSG_LF(__func__ ":6\n");
+
+ /* phy initialize end */
+
+ /* setup DDR mode registers */
+ /* CMOS MODE */
+ change_lpddr4_en(0);
+
+ /* MRS */
+ ddr_register_set();
+
+ /* Thermal sensor setting */
+ /* THCTR Bit6: PONM=0 , Bit0: THSST=1 */
+ data_l = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001;
+ mmio_write_32(THS1_THCTR, data_l);
+
+ /* LPDDR4 MODE */
+ change_lpddr4_en(1);
+
+ MSG_LF(__func__ ":7\n");
+
+ /* mask CS_MAP if RANKx is not found */
+ foreach_vch(ch) {
+ data_l = ddr_getval(ch, _reg_PI_CS_MAP);
+ if (!(ch_have_this_cs[1] & (1U << ch)))
+ data_l = data_l & 0x05;
+ ddr_setval(ch, _reg_PI_CS_MAP, data_l);
+ }
+
+ /* exec pi_training */
+ reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
+ BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
+ ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00);
+
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
+ ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01);
+ } else {
+ foreach_vch(ch) {
+ for (slice = 0; slice < SLICE_CNT; slice++) {
+ ddr_setval_s(ch, slice,
+ _reg_PHY_PER_CS_TRAINING_EN,
+ ((ch_have_this_cs[1]) >> ch)
+ & 0x01);
+ }
+ }
+ }
+
+ phytrainingok = pi_training_go();
+
+ if (ddr_phyvalid != (phytrainingok & ddr_phyvalid)) {
+ return INITDRAM_ERR_T | phytrainingok;
+ }
+
+ MSG_LF(__func__ ":8\n");
+
+ /* CACS DLY ADJUST */
+ data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj);
+ foreach_vch(ch) {
+ for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
+ adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
+ ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
+ data_l + adj);
+ }
+
+ if (ddr_phycaslice == 1) {
+ for (i = 0; i < 6; i++) {
+ adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj
+ [i +
+ _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]);
+ ddr_setval_s(ch, 2,
+ _reg_PHY_CLK_CACS_SLAVE_DELAY_X
+ [i],
+ data_l + adj
+ );
+ }
+ }
+ }
+
+ update_dly();
+ MSG_LF(__func__ ":9\n");
+
+ /* H3 fix rd latency to avoid bug in elasitic buffer */
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11))
+ adjust_rddqs_latency();
+
+ /* Adjust Write path latency */
+ if (ddrtbl_getval
+ (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD))
+ adjust_wpath_latency();
+
+ /* RDQLVL Training */
+ if (!ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE))
+ ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01);
+
+ err = rdqdm_man();
+
+ if (!ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE))
+ ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x00);
+
+ if (err) {
+ return INITDRAM_ERR_T;
+ }
+ update_dly();
+ MSG_LF(__func__ ":10\n");
+
+ /* WDQLVL Training */
+ err = wdqdm_man();
+ if (err) {
+ return INITDRAM_ERR_T;
+ }
+ update_dly();
+ MSG_LF(__func__ ":11\n");
+
+ /* training complete, setup DBSC */
+ if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) ||
+ (prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
+ ddr_setval_ach_as(_reg_PHY_DFI40_POLARITY, 0x00);
+ ddr_setval_ach(_reg_PI_DFI40_POLARITY, 0x00);
+ }
+
+ dbsc_regset_post();
+ MSG_LF(__func__ ":12\n");
+
+ return phytrainingok;
+}
+
+/* SW LEVELING COMMON */
+static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick)
+{
+ uint32_t ch;
+ uint32_t data_l;
+ uint32_t retry;
+ uint32_t waiting;
+ uint32_t err;
+
+ const uint32_t RETRY_MAX = 0x1000;
+
+ err = 0;
+ /* set EXIT -> OP_DONE is cleared */
+ ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01);
+
+ /* kick */
+ foreach_vch(ch) {
+ if (ch_have_this_cs[ddr_csn % 2] & (1U << ch)) {
+ ddr_setval(ch, reg_cs, ddr_csn);
+ ddr_setval(ch, reg_kick, 0x01);
+ }
+ }
+ foreach_vch(ch) {
+ /*PREPARE ADDR REGISTER (for SWLVL_OP_DONE) */
+ ddr_getval(ch, _reg_PI_SWLVL_OP_DONE);
+ }
+ waiting = ch_have_this_cs[ddr_csn % 2];
+ dsb_sev();
+ retry = RETRY_MAX;
+ do {
+ foreach_vch(ch) {
+ if (!(waiting & (1U << ch)))
+ continue;
+ data_l = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE);
+ if (data_l & 0x01)
+ waiting &= ~(1U << ch);
+ }
+ retry--;
+ } while (waiting && (retry > 0));
+ if (retry == 0) {
+ err = 1;
+ }
+
+ dsb_sev();
+ /* set EXIT -> OP_DONE is cleared */
+ ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01);
+ dsb_sev();
+
+ return err;
+}
+
+/* WDQ TRAINING */
+#ifndef DDR_FAST_INIT
+static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
+{
+ int32_t i, k;
+ uint32_t cs, slice;
+ uint32_t data_l;
+
+ /* clr of training results buffer */
+ cs = ddr_csn % 2;
+ data_l = board_cnf->dqdm_dly_w;
+ for (slice = 0; slice < SLICE_CNT; slice++) {
+ k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+ if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
+ continue;
+
+ for (i = 0; i <= 8; i++) {
+ if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch))
+ wdqdm_dly[ch][cs][slice][i] =
+ wdqdm_dly[ch][CS_CNT - 1 - cs][slice][i];
+ else
+ wdqdm_dly[ch][cs][slice][i] = data_l;
+ wdqdm_le[ch][cs][slice][i] = 0;
+ wdqdm_te[ch][cs][slice][i] = 0;
+ }
+ wdqdm_st[ch][cs][slice] = 0;
+ wdqdm_win[ch][cs][slice] = 0;
+ }
+}
+
+static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
+{
+ int32_t i, k;
+ uint32_t cs, slice;
+ uint32_t data_l;
+ uint32_t err;
+ const uint32_t _par_WDQLVL_RETRY_THRES = 0x7c0;
+
+ int32_t min_win;
+ int32_t win;
+ int8_t _adj;
+ int16_t adj;
+ uint32_t dq;
+
+ /* analysis of training results */
+ err = 0;
+ for (slice = 0; slice < SLICE_CNT; slice += 1) {
+ k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+ if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
+ continue;
+
+ cs = ddr_csn % 2;
+ ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs);
+ for (i = 0; i < 9; i++) {
+ dq = slice * 8 + i;
+ if (i == 8)
+ _adj = board_cnf->ch[ch].dm_adj_w[slice];
+ else
+ _adj = board_cnf->ch[ch].dq_adj_w[dq];
+ adj = _f_scale_adj(_adj);
+
+ data_l =
+ ddr_getval_s(ch, slice,
+ _reg_PHY_CLK_WRX_SLAVE_DELAY[i]) + adj;
+ ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i],
+ data_l);
+ wdqdm_dly[ch][cs][slice][i] = data_l;
+ }
+ ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00);
+ data_l = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS);
+ wdqdm_st[ch][cs][slice] = data_l;
+ min_win = INT_LEAST32_MAX;
+ for (i = 0; i <= 8; i++) {
+ ddr_setval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_OBS_SELECT,
+ i);
+
+ data_l =
+ ddr_getval_s(ch, slice,
+ _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS);
+ wdqdm_te[ch][cs][slice][i] = data_l;
+ data_l =
+ ddr_getval_s(ch, slice,
+ _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS);
+ wdqdm_le[ch][cs][slice][i] = data_l;
+ win =
+ (int32_t)wdqdm_te[ch][cs][slice][i] -
+ wdqdm_le[ch][cs][slice][i];
+ if (min_win > win)
+ min_win = win;
+ if (data_l >= _par_WDQLVL_RETRY_THRES)
+ err = 2;
+ }
+ wdqdm_win[ch][cs][slice] = min_win;
+ if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) {
+ ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN,
+ 0x01);
+ } else {
+ ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN,
+ ((ch_have_this_cs[1]) >> ch) & 0x01);
+ }
+ }
+ return err;
+}
+#endif/* DDR_FAST_INIT */
+
+static void wdqdm_cp(uint32_t ddr_csn, uint32_t restore)
+{
+ uint32_t i;
+ uint32_t ch, slice;
+ uint32_t tgt_cs, src_cs;
+ uint32_t tmp_r;
+
+ /* copy of training results */
+ foreach_vch(ch) {
+ for (tgt_cs = 0; tgt_cs < CS_CNT; tgt_cs++) {
+ for (slice = 0; slice < SLICE_CNT; slice++) {
+ ddr_setval_s(ch, slice,
+ _reg_PHY_PER_CS_TRAINING_INDEX,
+ tgt_cs);
+ src_cs = ddr_csn % 2;
+ if (!(ch_have_this_cs[1] & (1U << ch)))
+ src_cs = 0;
+ for (i = 0; i <= 4; i += 4) {
+ if (restore)
+ tmp_r =
+ rdqdm_dly[ch][tgt_cs][slice]
+ [i];
+ else
+ tmp_r =
+ rdqdm_dly[ch][src_cs][slice]
+ [i];
+
+ ddr_setval_s(ch, slice,
+ _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY
+ [i], tmp_r);
+ }
+ }
+ }
+ }
+}
+
+static uint32_t wdqdm_man1(void)
+{
+ int32_t k;
+ uint32_t ch, cs, slice;
+ uint32_t ddr_csn;
+ uint32_t data_l;
+ uint32_t err;
+ uint32_t high_dq[DRAM_CH_CNT];
+ uint32_t mr14_csab0_bak[DRAM_CH_CNT];
+#ifndef DDR_FAST_INIT
+ uint32_t err_flg;
+#endif/* DDR_FAST_INIT */
+
+ /* manual execution of training */
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
+ foreach_vch(ch) {
+ high_dq[ch] = 0;
+ for (slice = 0; slice < SLICE_CNT; slice++) {
+ k = (board_cnf->ch[ch].dqs_swap >>
+ (4 * slice)) & 0x0f;
+ if (k >= 2)
+ high_dq[ch] |= (1U << slice);
+ }
+ ddr_setval(ch, _reg_PI_16BIT_DRAM_CONNECT, 0x00);
+ }
+ }
+ err = 0;
+ /* CLEAR PREV RESULT */
+ for (cs = 0; cs < CS_CNT; cs++) {
+ ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_INDEX, cs);
+ if (((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut > PRR_PRODUCT_11)) ||
+ (prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
+ ddr_setval_ach_as(_reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS,
+ 0x01);
+ } else {
+ ddr_setval_ach_as(_reg_PHY_WDQLVL_CLR_PREV_RESULTS,
+ 0x01);
+ }
+ }
+ ddrphy_regif_idle();
+
+#ifndef DDR_FAST_INIT
+ err_flg = 0;
+#endif/* DDR_FAST_INIT */
+ for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
+ if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) {
+ foreach_vch(ch) {
+ data_l = mmio_read_32(DBSC_DBDFICNT(ch));
+ data_l &= ~(0x00ffU << 16);
+
+ if (ddr_csn >= 2)
+ k = (high_dq[ch] ^ 0x0f);
+ else
+ k = high_dq[ch];
+ data_l |= (k << 16);
+ mmio_write_32(DBSC_DBDFICNT(ch), data_l);
+ ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, k);
+ }
+ }
+ if (((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) ||
+ ((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut == PRR_PRODUCT_10))) {
+ wdqdm_cp(ddr_csn, 0);
+ }
+
+ foreach_vch(ch) {
+ data_l =
+ ddr_getval(ch,
+ reg_pi_mr14_data_fx_csx[1][ddr_csn]);
+ ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], data_l);
+ }
+
+ /* KICK WDQLVL */
+ err = swlvl1(ddr_csn, _reg_PI_WDQLVL_CS, _reg_PI_WDQLVL_REQ);
+ if (err)
+ goto err_exit;
+
+ if (ddr_csn == 0)
+ foreach_vch(ch) {
+ mr14_csab0_bak[ch] =
+ ddr_getval(ch, reg_pi_mr14_data_fx_csx[1][0]);
+ } else
+ foreach_vch(ch) {
+ ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0],
+ mr14_csab0_bak[ch]);
+ }
+#ifndef DDR_FAST_INIT
+ foreach_vch(ch) {
+ if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) {
+ wdqdm_clr1(ch, ddr_csn);
+ continue;
+ }
+ err = wdqdm_ana1(ch, ddr_csn);
+ if (err)
+ err_flg |= (1U << (ddr_csn * 4 + ch));
+ ddrphy_regif_idle();
+ }
+#endif/* DDR_FAST_INIT */
+ }
+err_exit:
+#ifndef DDR_FAST_INIT
+ err |= err_flg;
+#endif/* DDR_FAST_INIT */
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
+ ddr_setval_ach(_reg_PI_16BIT_DRAM_CONNECT, 0x01);
+ foreach_vch(ch) {
+ data_l = mmio_read_32(DBSC_DBDFICNT(ch));
+ data_l &= ~(0x00ffU << 16);
+ mmio_write_32(DBSC_DBDFICNT(ch), data_l);
+ ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, 0x00);
+ }
+ }
+ return err;
+}
+
+static uint32_t wdqdm_man(void)
+{
+ uint32_t err, retry_cnt;
+ const uint32_t retry_max = 0x10;
+ uint32_t datal, ch, ddr_csn, mr14_bkup[4][4];
+
+ datal = RL + js2[js2_tdqsck] + (16 / 2) + 1 - WL + 2 + 2 + 19;
+ if ((mmio_read_32(DBSC_DBTR(11)) & 0xFF) > datal)
+ datal = mmio_read_32(DBSC_DBTR(11)) & 0xFF;
+ ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, datal);
+
+ if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) ||
+ (prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
+ ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F0,
+ (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10);
+ ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F1,
+ (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10);
+ } else {
+ ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR,
+ (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10);
+ }
+ ddr_setval_ach(_reg_PI_TRFC_F0, mmio_read_32(DBSC_DBTR(13)) & 0x1FF);
+ ddr_setval_ach(_reg_PI_TRFC_F1, mmio_read_32(DBSC_DBTR(13)) & 0x1FF);
+
+ retry_cnt = 0;
+ err = 0;
+ do {
+ if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) {
+ err = wdqdm_man1();
+ } else {
+ ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01);
+ ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE,
+ 0x01);
+ if ((prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
+ ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1,
+ 0x0C);
+ } else {
+ ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x0C);
+ }
+ dsb_sev();
+ err = wdqdm_man1();
+ foreach_vch(ch) {
+ for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
+ mr14_bkup[ch][ddr_csn] =
+ ddr_getval(ch,
+ reg_pi_mr14_data_fx_csx
+ [1][ddr_csn]);
+ dsb_sev();
+ }
+ }
+
+ if ((prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
+ ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1,
+ 0x04);
+ } else {
+ ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x04);
+ }
+ pvtcode_update();
+ err = wdqdm_man1();
+ foreach_vch(ch) {
+ for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
+ mr14_bkup[ch][ddr_csn] =
+ (mr14_bkup[ch][ddr_csn] +
+ ddr_getval(ch,
+ reg_pi_mr14_data_fx_csx
+ [1][ddr_csn])) / 2;
+ ddr_setval(ch,
+ reg_pi_mr14_data_fx_csx[1]
+ [ddr_csn],
+ mr14_bkup[ch][ddr_csn]);
+ }
+ }
+
+ ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE,
+ 0x00);
+ if ((prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
+ ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1,
+ 0x00);
+ ddr_setval_ach
+ (_reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F1,
+ 0x00);
+ ddr_setval_ach
+ (_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1,
+ 0x00);
+ } else {
+ ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x00);
+ ddr_setval_ach
+ (_reg_PI_WDQLVL_VREF_INITIAL_START_POINT,
+ 0x00);
+ ddr_setval_ach
+ (_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT,
+ 0x00);
+ }
+ ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE,
+ 0x00);
+
+ pvtcode_update2();
+ err = wdqdm_man1();
+ ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00);
+ }
+ } while (err && (++retry_cnt < retry_max));
+
+ if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) ||
+ ((prr_product == PRR_PRODUCT_M3) && (prr_cut <= PRR_PRODUCT_10))) {
+ wdqdm_cp(0, 1);
+ }
+
+ return (retry_cnt >= retry_max);
+}
+
+/* RDQ TRAINING */
+#ifndef DDR_FAST_INIT
+static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
+{
+ int32_t i, k;
+ uint32_t cs, slice;
+ uint32_t data_l;
+
+ /* clr of training results buffer */
+ cs = ddr_csn % 2;
+ data_l = board_cnf->dqdm_dly_r;
+ for (slice = 0; slice < SLICE_CNT; slice++) {
+ k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+ if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
+ continue;
+
+ for (i = 0; i <= 8; i++) {
+ if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) {
+ rdqdm_dly[ch][cs][slice][i] =
+ rdqdm_dly[ch][CS_CNT - 1 - cs][slice][i];
+ rdqdm_dly[ch][cs][slice + SLICE_CNT][i] =
+ rdqdm_dly[ch][CS_CNT - 1 - cs][slice +
+ SLICE_CNT]
+ [i];
+ } else {
+ rdqdm_dly[ch][cs][slice][i] = data_l;
+ rdqdm_dly[ch][cs][slice + SLICE_CNT][i] =
+ data_l;
+ }
+ rdqdm_le[ch][cs][slice][i] = 0;
+ rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0;
+ rdqdm_te[ch][cs][slice][i] = 0;
+ rdqdm_te[ch][cs][slice + SLICE_CNT][i] = 0;
+ rdqdm_nw[ch][cs][slice][i] = 0;
+ rdqdm_nw[ch][cs][slice + SLICE_CNT][i] = 0;
+ }
+ rdqdm_st[ch][cs][slice] = 0;
+ rdqdm_win[ch][cs][slice] = 0;
+ }
+}
+
+static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
+{
+ int32_t i, k;
+ uint32_t cs, slice;
+ uint32_t data_l;
+ uint32_t err;
+ int8_t _adj;
+ int16_t adj;
+ uint32_t dq;
+ int32_t min_win;
+ int32_t win;
+ uint32_t rdq_status_obs_select;
+
+ /* analysis of training results */
+ err = 0;
+ for (slice = 0; slice < SLICE_CNT; slice++) {
+ k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
+ if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
+ continue;
+
+ cs = ddr_csn % 2;
+ ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs);
+ ddrphy_regif_idle();
+
+ ddr_getval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX);
+ ddrphy_regif_idle();
+
+ for (i = 0; i <= 8; i++) {
+ dq = slice * 8 + i;
+ if (i == 8)
+ _adj = board_cnf->ch[ch].dm_adj_r[slice];
+ else
+ _adj = board_cnf->ch[ch].dq_adj_r[dq];
+
+ adj = _f_scale_adj(_adj);
+
+ data_l =
+ ddr_getval_s(ch, slice,
+ _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) +
+ adj;
+ ddr_setval_s(ch, slice,
+ _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i],
+ data_l);
+ rdqdm_dly[ch][cs][slice][i] = data_l;
+
+ data_l =
+ ddr_getval_s(ch, slice,
+ _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) +
+ adj;
+ ddr_setval_s(ch, slice,
+ _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i],
+ data_l);
+ rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l;
+ }
+ min_win = INT_LEAST32_MAX;
+ for (i = 0; i <= 8; i++) {
+ data_l =
+ ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS);
+ rdqdm_st[ch][cs][slice] = data_l;
+ rdqdm_st[ch][cs][slice + SLICE_CNT] = data_l;
+ /* k : rise/fall */
+ for (k = 0; k < 2; k++) {
+ if (i == 8) {
+ rdq_status_obs_select = 16 + 8 * k;
+ } else {
+ rdq_status_obs_select = i + k * 8;
+ }
+ ddr_setval_s(ch, slice,
+ _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT,
+ rdq_status_obs_select);
+
+ data_l =
+ ddr_getval_s(ch, slice,
+ _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS);
+ rdqdm_le[ch][cs][slice + SLICE_CNT * k][i] =
+ data_l;
+
+ data_l =
+ ddr_getval_s(ch, slice,
+ _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS);
+ rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] =
+ data_l;
+
+ data_l =
+ ddr_getval_s(ch, slice,
+ _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS);
+ rdqdm_nw[ch][cs][slice + SLICE_CNT * k][i] =
+ data_l;
+
+ win =
+ (int32_t)rdqdm_te[ch][cs][slice +
+ SLICE_CNT *
+ k][i] -
+ rdqdm_le[ch][cs][slice + SLICE_CNT * k][i];
+ if (i != 8) {
+ if (min_win > win)
+ min_win = win;
+ }
+ }
+ }
+ rdqdm_win[ch][cs][slice] = min_win;
+ if (min_win <= 0) {
+ err = 2;
+ }
+ }
+ return err;
+}
+#endif/* DDR_FAST_INIT */
+
+static uint32_t rdqdm_man1(void)
+{
+ uint32_t ch;
+ uint32_t ddr_csn;
+#ifdef DDR_FAST_INIT
+ uint32_t slice;
+ uint32_t i, adj, data_l;
+#endif/* DDR_FAST_INIT */
+ uint32_t err;
+
+ /* manual execution of training */
+ err = 0;
+
+ for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
+ /* KICK RDQLVL */
+ err = swlvl1(ddr_csn, _reg_PI_RDLVL_CS, _reg_PI_RDLVL_REQ);
+ if (err)
+ goto err_exit;
+#ifndef DDR_FAST_INIT
+ foreach_vch(ch) {
+ if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) {
+ rdqdm_clr1(ch, ddr_csn);
+ ddrphy_regif_idle();
+ continue;
+ }
+ err = rdqdm_ana1(ch, ddr_csn);
+ ddrphy_regif_idle();
+ if (err)
+ goto err_exit;
+ }
+#else/* DDR_FAST_INIT */
+ foreach_vch(ch) {
+ if (ch_have_this_cs[ddr_csn] & (1U << ch)) {
+ for (slice = 0; slice < SLICE_CNT; slice++) {
+ if (ddr_getval_s(ch, slice,
+ _reg_PHY_RDLVL_STATUS_OBS) !=
+ 0x0D00FFFF) {
+ err = (1U << ch) |
+ (0x10U << slice);
+ goto err_exit;
+ }
+ }
+ }
+ if (((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) ||
+ ((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut <= PRR_PRODUCT_10))) {
+ for (slice = 0; slice < SLICE_CNT; slice++) {
+ for (i = 0; i <= 8; i++) {
+ if (i == 8)
+ adj = _f_scale_adj(board_cnf->ch[ch].dm_adj_r[slice]);
+ else
+ adj = _f_scale_adj(board_cnf->ch[ch].dq_adj_r[slice * 8 + i]);
+ ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, ddr_csn);
+ data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj;
+ ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], data_l);
+ rdqdm_dly[ch][ddr_csn][slice][i] = data_l;
+ rdqdm_dly[ch][ddr_csn | 1][slice][i] = data_l;
+
+ data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj;
+ ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], data_l);
+ rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = data_l;
+ rdqdm_dly[ch][ddr_csn | 1][slice + SLICE_CNT][i] = data_l;
+ }
+ }
+ }
+ }
+ ddrphy_regif_idle();
+
+#endif/* DDR_FAST_INIT */
+ }
+
+err_exit:
+ return err;
+}
+
+static uint32_t rdqdm_man(void)
+{
+ uint32_t err, retry_cnt;
+ const uint32_t retry_max = 0x01;
+
+ ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE,
+ 0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+ _reg_PHY_DQ_TSEL_ENABLE));
+ ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE,
+ 0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+ _reg_PHY_DQS_TSEL_ENABLE));
+ ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT,
+ 0xFF0FFFFF & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+ _reg_PHY_DQ_TSEL_SELECT));
+ ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT,
+ 0xFF0FFFFF & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+ _reg_PHY_DQS_TSEL_SELECT));
+
+ retry_cnt = 0;
+ do {
+ err = rdqdm_man1();
+ ddrphy_regif_idle();
+ } while (err && (++retry_cnt < retry_max));
+ ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE,
+ ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+ _reg_PHY_DQ_TSEL_ENABLE));
+ ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE,
+ ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+ _reg_PHY_DQS_TSEL_ENABLE));
+ ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT,
+ ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+ _reg_PHY_DQ_TSEL_SELECT));
+ ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT,
+ ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
+ _reg_PHY_DQS_TSEL_SELECT));
+
+ return (retry_cnt >= retry_max);
+}
+
+/* rx offset calibration */
+static int32_t _find_change(uint64_t val, uint32_t dir)
+{
+ int32_t i;
+ uint32_t startval;
+ uint32_t curval;
+ const int32_t VAL_END = 0x3f;
+
+ if (dir == 0) {
+ startval = (val & 0x01);
+ for (i = 1; i <= VAL_END; i++) {
+ curval = (val >> i) & 0x01;
+ if (curval != startval)
+ return i;
+ }
+ return VAL_END;
+ }
+
+ startval = (val >> dir) & 0x01;
+ for (i = dir - 1; i >= 0; i--) {
+ curval = (val >> i) & 0x01;
+ if (curval != startval)
+ return i;
+ }
+ return 0;
+}
+
+static uint32_t _rx_offset_cal_updn(uint32_t code)
+{
+ const uint32_t CODE_MAX = 0x40;
+ uint32_t tmp;
+
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
+ if (code == 0)
+ tmp = (1U << 6) | (CODE_MAX - 1);
+ else if (code <= 0x20)
+ tmp =
+ ((CODE_MAX - 1 -
+ (0x20 - code) * 2) << 6) | (CODE_MAX - 1);
+ else
+ tmp =
+ ((CODE_MAX - 1) << 6) | (CODE_MAX - 1 -
+ (code - 0x20) * 2);
+ } else {
+ if (code == 0)
+ tmp = (1U << 6) | (CODE_MAX - 1);
+ else
+ tmp = (code << 6) | (CODE_MAX - code);
+ }
+ return tmp;
+}
+
+static uint32_t rx_offset_cal(void)
+{
+ uint32_t index;
+ uint32_t code;
+ const uint32_t CODE_MAX = 0x40;
+ const uint32_t CODE_STEP = 2;
+ uint32_t ch, slice;
+ uint32_t tmp;
+ uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT];
+ uint64_t val[DRAM_CH_CNT][SLICE_CNT][_reg_PHY_RX_CAL_X_NUM];
+ uint64_t tmpval;
+ int32_t lsb, msb;
+
+ ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x01);
+ foreach_vch(ch) {
+ for (slice = 0; slice < SLICE_CNT; slice++) {
+ for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++)
+ val[ch][slice][index] = 0;
+ }
+ }
+
+ for (code = 0; code < CODE_MAX / CODE_STEP; code++) {
+ tmp = _rx_offset_cal_updn(code * CODE_STEP);
+ for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) {
+ ddr_setval_ach_as(_reg_PHY_RX_CAL_X[index], tmp);
+ }
+ dsb_sev();
+ ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *)tmp_ach_as);
+
+ foreach_vch(ch) {
+ for (slice = 0; slice < SLICE_CNT; slice++) {
+ tmp = tmp_ach_as[ch][slice];
+ for (index = 0; index < _reg_PHY_RX_CAL_X_NUM;
+ index++) {
+ if (tmp & (1U << index)) {
+ val[ch][slice][index] |=
+ (1ULL << code);
+ } else {
+ val[ch][slice][index] &=
+ ~(1ULL << code);
+ }
+ }
+ }
+ }
+ }
+ foreach_vch(ch) {
+ for (slice = 0; slice < SLICE_CNT; slice++) {
+ for (index = 0; index < _reg_PHY_RX_CAL_X_NUM;
+ index++) {
+ tmpval = val[ch][slice][index];
+ lsb = _find_change(tmpval, 0);
+ msb =
+ _find_change(tmpval,
+ (CODE_MAX / CODE_STEP) - 1);
+ tmp = (lsb + msb) >> 1;
+
+ tmp = _rx_offset_cal_updn(tmp * CODE_STEP);
+ ddr_setval_s(ch, slice,
+ _reg_PHY_RX_CAL_X[index], tmp);
+ }
+ }
+ }
+ ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00);
+
+ return 0;
+}
+
+static uint32_t rx_offset_cal_hw(void)
+{
+ uint32_t ch, slice;
+ uint32_t retry;
+ uint32_t complete;
+ uint32_t tmp;
+ uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT];
+
+ ddr_setval_ach_as(_reg_PHY_RX_CAL_X[9], 0x00);
+ ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00);
+ ddr_setval_ach_as(_reg_PHY_RX_CAL_SAMPLE_WAIT, 0x0f);
+
+ retry = 0;
+ while (retry < 4096) {
+ if ((retry & 0xff) == 0) {
+ ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01);
+ }
+ foreach_vch(ch)
+ for (slice = 0; slice < SLICE_CNT; slice++)
+ tmp_ach_as[ch][slice] =
+ ddr_getval_s(ch, slice, _reg_PHY_RX_CAL_X[9]);
+
+ complete = 1;
+ foreach_vch(ch) {
+ for (slice = 0; slice < SLICE_CNT; slice++) {
+ tmp = tmp_ach_as[ch][slice];
+ tmp = (tmp & 0x3f) + ((tmp >> 6) & 0x3f);
+ if (((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut > PRR_PRODUCT_11)) ||
+ (prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
+ if (tmp != 0x3E)
+ complete = 0;
+ } else {
+ if (tmp != 0x40)
+ complete = 0;
+ }
+ }
+ }
+ if (complete)
+ break;
+
+ retry++;
+ }
+
+ return (complete == 0);
+}
+
+/* adjust rddqs latency */
+static void adjust_rddqs_latency(void)
+{
+ uint32_t ch, slice;
+ uint32_t dly;
+ uint32_t maxlatx2;
+ uint32_t tmp;
+ uint32_t rdlat_adjx2[SLICE_CNT];
+
+ foreach_vch(ch) {
+ maxlatx2 = 0;
+ for (slice = 0; slice < SLICE_CNT; slice++) {
+ ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX,
+ 0x00);
+
+ dly =
+ ddr_getval_s(ch, slice,
+ _reg_PHY_RDDQS_GATE_SLAVE_DELAY);
+ tmp =
+ ddr_getval_s(ch, slice,
+ _reg_PHY_RDDQS_LATENCY_ADJUST);
+ /* note gate_slave_delay[9] is always 0 */
+ tmp = (tmp << 1) + (dly >> 8);
+ rdlat_adjx2[slice] = tmp;
+ if (maxlatx2 < tmp)
+ maxlatx2 = tmp;
+ }
+ maxlatx2 = ((maxlatx2 + 1) >> 1) << 1;
+ for (slice = 0; slice < SLICE_CNT; slice++) {
+ tmp = maxlatx2 - rdlat_adjx2[slice];
+ tmp = (tmp >> 1);
+ if (tmp) {
+ ddr_setval_s(ch, slice, _reg_PHY_RPTR_UPDATE,
+ ddr_getval_s(ch, slice,
+ _reg_PHY_RPTR_UPDATE)
+ + 1);
+ }
+ }
+ }
+}
+
+/* adjust wpath latency */
+static void adjust_wpath_latency(void)
+{
+ uint32_t ch, cs, slice;
+ uint32_t dly;
+ uint32_t wpath_add;
+ const uint32_t _par_EARLY_THRESHOLD_VAL = 0x180;
+
+ foreach_vch(ch) {
+ for (slice = 0; slice < SLICE_CNT; slice += 1) {
+ for (cs = 0; cs < CS_CNT; cs++) {
+ ddr_setval_s(ch, slice,
+ _reg_PHY_PER_CS_TRAINING_INDEX,
+ cs);
+ ddr_getval_s(ch, slice,
+ _reg_PHY_PER_CS_TRAINING_INDEX);
+ dly =
+ ddr_getval_s(ch, slice,
+ _reg_PHY_CLK_WRDQS_SLAVE_DELAY);
+ if (dly <= _par_EARLY_THRESHOLD_VAL)
+ continue;
+
+ wpath_add =
+ ddr_getval_s(ch, slice,
+ _reg_PHY_WRITE_PATH_LAT_ADD);
+ ddr_setval_s(ch, slice,
+ _reg_PHY_WRITE_PATH_LAT_ADD,
+ wpath_add - 1);
+ }
+ }
+ }
+}
+
+/* DDR Initialize entry */
+int32_t rcar_dram_init(void)
+{
+ uint32_t ch, cs;
+ uint32_t data_l;
+ uint32_t bus_mbps, bus_mbpsdiv;
+ uint32_t tmp_tccd;
+ uint32_t failcount;
+ uint32_t cnf_boardtype;
+
+ /* Thermal sensor setting */
+ data_l = mmio_read_32(CPG_MSTPSR5);
+ if (data_l & BIT(22)) { /* case THS/TSC Standby */
+ data_l &= ~BIT(22);
+ cpg_write_32(CPG_SMSTPCR5, data_l);
+ while (mmio_read_32(CPG_MSTPSR5) & BIT(22))
+ ; /* wait bit=0 */
+ }
+
+ /* THCTR Bit6: PONM=0 , Bit0: THSST=0 */
+ data_l = mmio_read_32(THS1_THCTR);
+ if (data_l & 0x00000040U) {
+ data_l = data_l & 0xFFFFFFBEU;
+ } else {
+ data_l = data_l | BIT(1);
+ }
+
+ mmio_write_32(THS1_THCTR, data_l);
+
+ /* Judge product and cut */
+#ifdef RCAR_DDR_FIXED_LSI_TYPE
+#if (RCAR_LSI == RCAR_AUTO)
+ prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
+ prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
+#else /* RCAR_LSI */
+#ifndef RCAR_LSI_CUT
+ prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
+#endif /* RCAR_LSI_CUT */
+#endif /* RCAR_LSI */
+#else /* RCAR_DDR_FIXED_LSI_TYPE */
+ prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
+ prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
+#endif /* RCAR_DDR_FIXED_LSI_TYPE */
+
+ if (prr_product == PRR_PRODUCT_H3) {
+ if (prr_cut <= PRR_PRODUCT_11) {
+ p_ddr_regdef_tbl =
+ (const uint32_t *)&DDR_REGDEF_TBL[0][0];
+ } else {
+ p_ddr_regdef_tbl =
+ (const uint32_t *)&DDR_REGDEF_TBL[2][0];
+ }
+ } else if (prr_product == PRR_PRODUCT_M3) {
+ p_ddr_regdef_tbl =
+ (const uint32_t *)&DDR_REGDEF_TBL[1][0];
+ } else if ((prr_product == PRR_PRODUCT_M3N) ||
+ (prr_product == PRR_PRODUCT_V3H)) {
+ p_ddr_regdef_tbl =
+ (const uint32_t *)&DDR_REGDEF_TBL[3][0];
+ } else {
+ FATAL_MSG("BL2: DDR:Unknown Product\n");
+ return 0xff;
+ }
+
+ if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) ||
+ ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) {
+ /* non : H3 Ver.1.x/M3-W Ver.1.x not support */
+ } else {
+ mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
+ }
+
+ /* Judge board type */
+ cnf_boardtype = boardcnf_get_brd_type();
+ if (cnf_boardtype >= BOARDNUM) {
+ FATAL_MSG("BL2: DDR:Unknown Board\n");
+ return 0xff;
+ }
+ board_cnf = (const struct _boardcnf *)&boardcnfs[cnf_boardtype];
+
+/* RCAR_DRAM_SPLIT_2CH (2U) */
+#if RCAR_DRAM_SPLIT == 2
+ /* H3(Test for future H3-N): Swap ch2 and ch1 for 2ch-split */
+ if ((prr_product == PRR_PRODUCT_H3) && (board_cnf->phyvalid == 0x05)) {
+ mmio_write_32(DBSC_DBMEMSWAPCONF0, 0x00000006);
+ ddr_phyvalid = 0x03;
+ } else {
+ ddr_phyvalid = board_cnf->phyvalid;
+ }
+#else /* RCAR_DRAM_SPLIT_2CH */
+ ddr_phyvalid = board_cnf->phyvalid;
+#endif /* RCAR_DRAM_SPLIT_2CH */
+
+ max_density = 0;
+
+ for (cs = 0; cs < CS_CNT; cs++) {
+ ch_have_this_cs[cs] = 0;
+ }
+
+ foreach_ech(ch)
+ for (cs = 0; cs < CS_CNT; cs++)
+ ddr_density[ch][cs] = 0xff;
+
+ foreach_vch(ch) {
+ for (cs = 0; cs < CS_CNT; cs++) {
+ data_l = board_cnf->ch[ch].ddr_density[cs];
+ ddr_density[ch][cs] = data_l;
+
+ if (data_l == 0xff)
+ continue;
+ if (data_l > max_density)
+ max_density = data_l;
+ if ((cs == 1) && (prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11))
+ continue;
+ ch_have_this_cs[cs] |= (1U << ch);
+ }
+ }
+
+ /* Judge board clock frequency (in MHz) */
+ boardcnf_get_brd_clk(cnf_boardtype, &brd_clk, &brd_clkdiv);
+ if ((brd_clk / brd_clkdiv) > 25) {
+ brd_clkdiva = 1;
+ } else {
+ brd_clkdiva = 0;
+ }
+
+ /* Judge ddr operating frequency clock(in Mbps) */
+ boardcnf_get_ddr_mbps(cnf_boardtype, &ddr_mbps, &ddr_mbpsdiv);
+
+ ddr0800_mul = CLK_DIV(800, 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1));
+
+ ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk,
+ brd_clkdiv * (brd_clkdiva + 1));
+
+ /* Adjust tccd */
+ data_l = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13;
+ bus_mbps = 0;
+ bus_mbpsdiv = 0;
+ switch (data_l) {
+ case 0:
+ bus_mbps = brd_clk * 0x60 * 2;
+ bus_mbpsdiv = brd_clkdiv * 1;
+ break;
+ case 1:
+ bus_mbps = brd_clk * 0x50 * 2;
+ bus_mbpsdiv = brd_clkdiv * 1;
+ break;
+ case 2:
+ bus_mbps = brd_clk * 0x40 * 2;
+ bus_mbpsdiv = brd_clkdiv * 1;
+ break;
+ case 3:
+ bus_mbps = brd_clk * 0x60 * 2;
+ bus_mbpsdiv = brd_clkdiv * 2;
+ break;
+ default:
+ bus_mbps = brd_clk * 0x60 * 2;
+ bus_mbpsdiv = brd_clkdiv * 2;
+ break;
+ }
+ tmp_tccd = CLK_DIV(ddr_mbps * 8, ddr_mbpsdiv, bus_mbps, bus_mbpsdiv);
+ if (8 * ddr_mbps * bus_mbpsdiv != tmp_tccd * bus_mbps * ddr_mbpsdiv)
+ tmp_tccd = tmp_tccd + 1;
+
+ if (tmp_tccd < 8)
+ ddr_tccd = 8;
+ else
+ ddr_tccd = tmp_tccd;
+
+ NOTICE("BL2: DDR%d(%s)\n", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION);
+
+ MSG_LF("Start\n");
+
+ /* PLL Setting */
+ pll3_control(1);
+
+ /* initialize DDR */
+ data_l = init_ddr();
+ if (data_l == ddr_phyvalid) {
+ failcount = 0;
+ } else {
+ failcount = 1;
+ }
+
+ foreach_vch(ch)
+ mmio_write_32(DBSC_DBPDLK(ch), 0x00000000);
+ if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) ||
+ ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) {
+ /* non : H3 Ver.1.x/M3-W Ver.1.x not support */
+ } else {
+ mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
+ }
+
+ if (failcount == 0) {
+ return INITDRAM_OK;
+ } else {
+ return INITDRAM_NG;
+ }
+}
+
+void pvtcode_update(void)
+{
+ uint32_t ch;
+ uint32_t data_l;
+ uint32_t pvtp[4], pvtn[4], pvtp_init, pvtn_init;
+ int32_t pvtp_tmp, pvtn_tmp;
+
+ foreach_vch(ch) {
+ pvtn_init = (tcal.tcomp_cal[ch] & 0xFC0) >> 6;
+ pvtp_init = (tcal.tcomp_cal[ch] & 0x03F) >> 0;
+
+ if (8912 * pvtp_init > 44230) {
+ pvtp_tmp = (5000 + 8912 * pvtp_init - 44230) / 10000;
+ } else {
+ pvtp_tmp =
+ -((-(5000 + 8912 * pvtp_init - 44230)) / 10000);
+ }
+ pvtn_tmp = (5000 + 5776 * pvtn_init + 30280) / 10000;
+
+ pvtn[ch] = pvtn_tmp + pvtn_init;
+ pvtp[ch] = pvtp_tmp + pvtp_init;
+
+ if (pvtn[ch] > 63) {
+ pvtn[ch] = 63;
+ pvtp[ch] =
+ (pvtp_tmp) * (63 - 6 * pvtn_tmp -
+ pvtn_init) / (pvtn_tmp) +
+ 6 * pvtp_tmp + pvtp_init;
+ }
+ if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) {
+ data_l = pvtp[ch] | (pvtn[ch] << 6) |
+ (tcal.tcomp_cal[ch] & 0xfffff000);
+ reg_ddrphy_write(ch,
+ ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
+ data_l | 0x00020000);
+ reg_ddrphy_write(ch,
+ ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
+ data_l);
+ reg_ddrphy_write(ch,
+ ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
+ data_l);
+ reg_ddrphy_write(ch,
+ ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
+ data_l);
+ reg_ddrphy_write(ch,
+ ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
+ data_l);
+ } else {
+ data_l = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000;
+ reg_ddrphy_write(ch,
+ ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
+ data_l | 0x00020000);
+ reg_ddrphy_write(ch,
+ ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
+ data_l);
+ reg_ddrphy_write(ch,
+ ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
+ data_l);
+ reg_ddrphy_write(ch,
+ ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
+ data_l);
+ reg_ddrphy_write(ch,
+ ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
+ data_l);
+ }
+ }
+}
+
+void pvtcode_update2(void)
+{
+ uint32_t ch;
+
+ foreach_vch(ch) {
+ reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
+ tcal.init_cal[ch] | 0x00020000);
+ reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
+ tcal.init_cal[ch]);
+ reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
+ tcal.init_cal[ch]);
+ reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
+ tcal.init_cal[ch]);
+ reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
+ tcal.init_cal[ch]);
+ }
+}
+
+void ddr_padcal_tcompensate_getinit(uint32_t override)
+{
+ uint32_t ch;
+ uint32_t data_l;
+ uint32_t pvtp, pvtn;
+
+ tcal.init_temp = 0;
+ for (ch = 0; ch < 4; ch++) {
+ tcal.init_cal[ch] = 0;
+ tcal.tcomp_cal[ch] = 0;
+ }
+
+ foreach_vch(ch) {
+ tcal.init_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]);
+ tcal.tcomp_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]);
+ }
+
+ if (!override) {
+ data_l = mmio_read_32(THS1_TEMP);
+ if (data_l < 2800) {
+ tcal.init_temp =
+ (143 * (int32_t)data_l - 359000) / 1000;
+ } else {
+ tcal.init_temp =
+ (121 * (int32_t)data_l - 296300) / 1000;
+ }
+
+ foreach_vch(ch) {
+ pvtp = (tcal.init_cal[ch] >> 0) & 0x000003F;
+ pvtn = (tcal.init_cal[ch] >> 6) & 0x000003F;
+ if ((int32_t)pvtp >
+ ((tcal.init_temp * 29 - 3625) / 1000))
+ pvtp =
+ (int32_t)pvtp +
+ ((3625 - tcal.init_temp * 29) / 1000);
+ else
+ pvtp = 0;
+
+ if ((int32_t)pvtn >
+ ((tcal.init_temp * 54 - 6750) / 1000))
+ pvtn =
+ (int32_t)pvtn +
+ ((6750 - tcal.init_temp * 54) / 1000);
+ else
+ pvtn = 0;
+
+ if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) {
+ tcal.init_cal[ch] =
+ (tcal.init_cal[ch] & 0xfffff000) |
+ (pvtn << 6) |
+ pvtp;
+ } else {
+ tcal.init_cal[ch] =
+ 0x00015000 | (pvtn << 6) | pvtp;
+ }
+ }
+ tcal.init_temp = 125;
+ }
+}
+
+#ifndef ddr_qos_init_setting
+/* For QoS init */
+uint8_t get_boardcnf_phyvalid(void)
+{
+ return ddr_phyvalid;
+}
+#endif /* ddr_qos_init_setting */
diff --git a/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c
new file mode 100644
index 0000000..bbb0200
--- /dev/null
+++ b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_config.c
@@ -0,0 +1,2108 @@
+/*
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RZG_SOC
+#define RZG_SOC 0
+#endif
+
+#if (RZG_SOC == 1)
+#define BOARDNUM 4
+#else
+
+#include <board.h>
+
+#define BOARDNUM 22
+#endif /* RZG_SOC == 1 */
+#define BOARD_JUDGE_AUTO
+
+#ifdef BOARD_JUDGE_AUTO
+static uint32_t _board_judge(void);
+
+static uint32_t boardcnf_get_brd_type(void)
+{
+ return _board_judge();
+}
+#else
+static uint32_t boardcnf_get_brd_type(void)
+{
+ return 1;
+}
+#endif
+
+#define DDR_FAST_INIT
+
+struct _boardcnf_ch {
+ uint8_t ddr_density[CS_CNT];
+ uint64_t ca_swap;
+ uint16_t dqs_swap;
+ uint32_t dq_swap[SLICE_CNT];
+ uint8_t dm_swap[SLICE_CNT];
+ uint16_t wdqlvl_patt[16];
+ int8_t cacs_adj[16];
+ int8_t dm_adj_w[SLICE_CNT];
+ int8_t dq_adj_w[SLICE_CNT * 8];
+ int8_t dm_adj_r[SLICE_CNT];
+ int8_t dq_adj_r[SLICE_CNT * 8];
+};
+
+struct _boardcnf {
+ uint8_t phyvalid;
+ uint8_t dbi_en;
+ uint16_t cacs_dly;
+ int16_t cacs_dly_adj;
+ uint16_t dqdm_dly_w;
+ uint16_t dqdm_dly_r;
+ struct _boardcnf_ch ch[DRAM_CH_CNT];
+};
+
+#define WDQLVL_PAT {\
+ 0x00AA,\
+ 0x0055,\
+ 0x00AA,\
+ 0x0155,\
+ 0x01CC,\
+ 0x0133,\
+ 0x00CC,\
+ 0x0033,\
+ 0x00F0,\
+ 0x010F,\
+ 0x01F0,\
+ 0x010F,\
+ 0x00F0,\
+ 0x00F0,\
+ 0x000F,\
+ 0x010F}
+
+#if (RZG_SOC == 1)
+static const struct _boardcnf boardcnfs[BOARDNUM] = {
+ {
+/* boardcnf[0] HopeRun HiHope RZ/G2M 16Gbit/1rank/2ch board with G2M SoC */
+ .phyvalid = 0x03U,
+ .dbi_en = 0x01U,
+ .cacs_dly = 0x02c0U,
+ .cacs_dly_adj = 0x0U,
+ .dqdm_dly_w = 0x0300U,
+ .dqdm_dly_r = 0x00a0U,
+ .ch = {
+ {
+ { 0x04U, 0xffU },
+ 0x00345201UL,
+ 0x3201U,
+ { 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+ { 0x08U, 0x08U, 0x08U, 0x08U },
+ WDQLVL_PAT,
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 }
+ },
+ {
+ { 0x04U, 0xffU },
+ 0x00302154UL,
+ 0x2310U,
+ { 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+ { 0x08U, 0x08U, 0x08U, 0x08U },
+ WDQLVL_PAT,
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 }
+ }
+ }
+ },
+/* boardcnf[1] HopeRun HiHope RZ/G2M 8Gbit/2rank/2ch board with G2M SoC */
+ {
+ 0x03U,
+ 0x01U,
+ 0x02c0U,
+ 0x0U,
+ 0x0300U,
+ 0x00a0U,
+ {
+ {
+ { 0x02U, 0x02U },
+ 0x00345201UL,
+ 0x3201U,
+ { 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+ { 0x08U, 0x08U, 0x08U, 0x08U },
+ WDQLVL_PAT,
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 }
+ },
+ {
+ { 0x02U, 0x02U },
+ 0x00302154UL,
+ 0x2310,
+ { 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+ { 0x08U, 0x08U, 0x08U, 0x08U },
+ WDQLVL_PAT,
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 }
+ }
+ }
+ },
+/* boardcnf[2] HopeRun HiHope RZ/G2H board 16Gbit/1rank/2ch */
+ {
+ 0x05U,
+ 0x01U,
+ 0x0300U,
+ 0,
+ 0x0300U,
+ 0x00a0U,
+ {
+ {
+ { 0x04U, 0xffU },
+ 0x00345201UL,
+ 0x3201U,
+ { 0x01672543U, 0x45367012U, 0x45632107U, 0x60715234U },
+ { 0x08U, 0x08U, 0x08U, 0x08U },
+ WDQLVL_PAT,
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 }
+ },
+ {
+ { 0x04U, 0xffU },
+ 0x00302154UL,
+ 0x2310U,
+ { 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+ { 0x08U, 0x08U, 0x08U, 0x08U },
+ WDQLVL_PAT,
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 }
+ },
+ {
+ { 0x04U, 0xffU },
+ 0x00302154UL,
+ 0x2310U,
+ { 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+ { 0x08U, 0x08U, 0x08U, 0x08U },
+ WDQLVL_PAT,
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 }
+ },
+ {
+ { 0xffU, 0xffU },
+ 0UL,
+ 0U,
+ { 0U, 0U, 0U, 0U },
+ { 0U, 0U, 0U, 0U },
+ WDQLVL_PAT,
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 }
+ }
+ }
+ },
+/* boardcnf[3] HopeRun HiHope RZ/G2N board 16Gbit/2rank/1ch */
+ {
+ 0x01U,
+ 0x01U,
+ 0x0300U,
+ 0,
+ 0x0300U,
+ 0x00a0U,
+ {
+ {
+ { 0x04U, 0x04U },
+ 0x00345201UL,
+ 0x3201U,
+ { 0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U },
+ { 0x08U, 0x08U, 0x08U, 0x08U },
+ WDQLVL_PAT,
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 },
+ { 0, 0, 0, 0 },
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0 }
+ }
+ }
+ },
+};
+#else
+static const struct _boardcnf boardcnfs[BOARDNUM] = {
+ {
+/* boardcnf[0] RENESAS SALVATOR-X board with M3-W/SIP */
+ .phyvalid = 0x03,
+ .dbi_en = 0x01,
+ .cacs_dly = 0x02c0,
+ .cacs_dly_adj = 0,
+ .dqdm_dly_w = 0x0300,
+ .dqdm_dly_r = 0x00a0,
+ .ch = {
+ {
+ {0x02, 0x02},
+ 0x00543210U,
+ 0x3201U,
+ {0x70612543, 0x43251670, 0x45326170, 0x10672534},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+
+ {
+ {0x02, 0x02},
+ 0x00543210,
+ 0x2310,
+ {0x01327654, 0x34526107, 0x35421670, 0x70615324},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
+/* boardcnf[1] RENESAS KRIEK board with M3-W/SoC */
+ {
+ 0x03,
+ 0x01,
+ 0x2c0,
+ 0,
+ 0x300,
+ 0x0a0,
+ {
+ {
+ {0x02, 0x02},
+ 0x00345201,
+ 0x3201,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0x02},
+ 0x00302154,
+ 0x2310,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
+/* boardcnf[2] RENESAS SALVATOR-X board with H3 Ver.1.x/SIP(8Gbit 1rank) */
+ {
+ 0x0f,
+ 0x00,
+ 0x300,
+ -320,
+ 0x300,
+ 0x0a0,
+ {
+ {
+ {0x02, 0xff},
+ 0x00543210,
+ 0x3210,
+ {0x20741365, 0x34256107, 0x57460321, 0x70614532},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0xff},
+ 0x00543210,
+ 0x3102,
+ {0x23547610, 0x34526107, 0x67452310, 0x32106754},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0xff},
+ 0x00543210,
+ 0x0213,
+ {0x30216754, 0x67453210, 0x70165243, 0x07162345},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0xff},
+ 0x00543210,
+ 0x0213,
+ {0x01327654, 0x70615432, 0x54760123, 0x07162345},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
+/* boardcnf[3] RENESAS Starter Kit board with M3-W/SIP(8Gbit 1rank) */
+ {
+ 0x03,
+ 0x01,
+ 0x02c0,
+ 0,
+ 0x0300,
+ 0x00a0,
+ {
+ {
+ {0x02, 0xFF},
+ 0x00543210U,
+ 0x3201,
+ {0x70612543, 0x43251670, 0x45326170, 0x10672534},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0xFF},
+ 0x00543210,
+ 0x2310,
+ {0x01327654, 0x34526107, 0x35421670, 0x70615324},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
+/* boardcnf[4] RENESAS SALVATOR-M(1rank) board with H3 Ver.1.x/SoC */
+ {
+ 0x0f,
+ 0x00,
+ 0x2c0,
+ -320,
+ 0x300,
+ 0x0a0,
+ {
+ {
+ {0x02, 0xff},
+ 0x00315024,
+ 0x3120,
+ {0x30671254, 0x26541037, 0x17054623, 0x12307645},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0xff},
+ 0x00025143,
+ 0x3210,
+ {0x70613542, 0x16245307, 0x30712645, 0x21706354},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0xff},
+ 0x00523104,
+ 0x2301,
+ {0x70613542, 0x16245307, 0x30712645, 0x21706354},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0xff},
+ 0x00153402,
+ 0x2031,
+ {0x30671254, 0x26541037, 0x17054623, 0x12307645},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
+/* boardcnf[5] RENESAS KRIEK-1rank board with M3-W/SoC */
+ {
+ 0x03,
+ 0x01,
+ 0x2c0,
+ 0,
+ 0x300,
+ 0x0a0,
+ {
+ {
+ {0x02, 0xff},
+ 0x00345201,
+ 0x3201,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0xff},
+ 0x00302154,
+ 0x2310,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
+/* boardcnf[6] RENESAS SALVATOR-X board with H3 Ver.1.x/SIP(8Gbit 2rank) */
+ {
+ 0x0f,
+ 0x00,
+ 0x300,
+ -320,
+ 0x300,
+ 0x0a0,
+ {
+ {
+ {0x02, 0x02},
+ 0x00543210,
+ 0x3210,
+ {0x20741365, 0x34256107, 0x57460321, 0x70614532},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0x02},
+ 0x00543210,
+ 0x3102,
+ {0x23547610, 0x34526107, 0x67452310, 0x32106754},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0x02},
+ 0x00543210,
+ 0x0213,
+ {0x30216754, 0x67453210, 0x70165243, 0x07162345},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0x02},
+ 0x00543210,
+ 0x0213,
+ {0x01327654, 0x70615432, 0x54760123, 0x07162345},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
+/*
+ * boardcnf[7] RENESAS SALVATOR-X board with
+ * H3 Ver.2.0 or later/SIP(8Gbit 1rank)
+ */
+ {
+ 0x0f,
+ 0x01,
+ 0x300,
+ 0,
+ 0x300,
+ 0x0a0,
+ {
+ {
+ {0x02, 0xff},
+ 0x00543210,
+ 0x2310,
+ {0x70631425, 0x34527016, 0x43527610, 0x32104567},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0xff},
+ 0x00105432,
+ 0x3210,
+ {0x43256107, 0x07162354, 0x10234567, 0x01235467},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0xff},
+ 0x00543210,
+ 0x2301,
+ {0x01327654, 0x02316457, 0x10234567, 0x01325467},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0xff},
+ 0x00543210,
+ 0x2301,
+ {0x12034765, 0x23105467, 0x23017645, 0x32106745},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
+/*
+ * boardcnf[8] RENESAS SALVATOR-X board with
+ * H3 Ver.2.0 or later/SIP(8Gbit 2rank)
+ */
+ {
+#if RCAR_DRAM_CHANNEL == 5
+ 0x05,
+#else
+ 0x0f,
+#endif
+ 0x01,
+ 0x300,
+ 0,
+ 0x300,
+ 0x0a0,
+ {
+ {
+ {0x02, 0x02},
+ 0x00543210,
+ 0x2310,
+ {0x70631425, 0x34527016, 0x43527610, 0x32104567},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+#if ((RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2))
+ {
+ {0x02, 0x02},
+ 0x00543210,
+ 0x2301,
+ {0x01327654, 0x02316457, 0x10234567, 0x01325467},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+#else
+ {
+ {0x02, 0x02},
+ 0x00105432,
+ 0x3210,
+ {0x43256107, 0x07162354, 0x10234567, 0x01235467},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+#endif
+ {
+ {0x02, 0x02},
+ 0x00543210,
+ 0x2301,
+ {0x01327654, 0x02316457, 0x10234567, 0x01325467},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0x02},
+ 0x00543210,
+ 0x2301,
+ {0x12034765, 0x23105467, 0x23017645, 0x32106745},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
+/* boardcnf[9] RENESAS SALVATOR-MS(1rank) board with H3 Ver.2.0 or later/SoC */
+ {
+ 0x0f,
+ 0x01,
+ 0x300,
+ 0,
+ 0x300,
+ 0x0a0,
+ {
+ {
+ {0x02, 0xff},
+ 0x00543210,
+ 0x3210,
+ {0x27645310, 0x75346210, 0x53467210, 0x23674510},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0xff},
+ 0x00543210,
+ 0x2301,
+ {0x23764510, 0x43257610, 0x43752610, 0x37652401},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {-128, -128, -128, -128, -128, -128, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0xff},
+ 0x00452103,
+ 0x3210,
+ {0x32764510, 0x43257610, 0x43752610, 0x26573401},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0xff},
+ 0x00520413,
+ 0x2301,
+ {0x47652301, 0x75346210, 0x53467210, 0x32674501},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {30, 30, 30, 30, 30, 30, 30, 30,
+ 30, 30},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
+/* boardcnf[10] RENESAS Kriek(2rank) board with M3-N/SoC */
+ {
+ 0x01,
+ 0x01,
+ 0x300,
+ 0,
+ 0x300,
+ 0x0a0,
+ {
+ {
+ {0x02, 0x02},
+ 0x00345201,
+ 0x3201,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
+/* boardcnf[11] RENESAS SALVATOR-X board with M3-N/SIP(8Gbit 2rank) */
+ {
+ 0x01,
+ 0x01,
+ 0x300,
+ 0,
+ 0x300,
+ 0x0a0,
+ {
+ {
+#if (RCAR_DRAM_LPDDR4_MEMCONF == 2)
+ {0x04, 0x04},
+#else
+ {0x02, 0x02},
+#endif
+ 0x00342501,
+ 0x3201,
+ {0x10672534, 0x43257106, 0x34527601, 0x71605243},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
+/* boardcnf[12] RENESAS CONDOR board with V3H/SoC */
+ {
+ 0x01,
+ 0x1,
+ 0x300,
+ 0,
+ 0x300,
+ 0x0a0,
+ {
+ {
+ {0x02, 0x02},
+ 0x00501342,
+ 0x3201,
+ {0x70562134, 0x34526071, 0x23147506, 0x12430567},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
+/* boardcnf[13] RENESAS KRIEK board with PM3/SoC */
+ {
+ 0x05,
+ 0x00,
+ 0x2c0,
+ -320,
+ 0x300,
+ 0x0a0,
+ {
+ {
+ {0x02, 0x02},
+ 0x00345201,
+ 0x3201,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0x02},
+ 0x00302154,
+ 0x2310,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0x02},
+ 0x00302154,
+ 0x2310,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0xff, 0xff},
+ 0,
+ 0,
+ {0, 0, 0, 0},
+ {0, 0, 0, 0},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
+/* boardcnf[14] SALVATOR-X board with H3 Ver.2.0 or later/SIP(16Gbit 1rank) */
+ {
+#if RCAR_DRAM_CHANNEL == 5
+ 0x05,
+#else
+ 0x0f,
+#endif
+ 0x01,
+ 0x300,
+ 0,
+ 0x300,
+ 0x0a0,
+ {
+ {
+ {0x04, 0xff},
+ 0x00543210,
+ 0x2310,
+ {0x70631425, 0x34527016, 0x43527610, 0x32104567},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+#if ((RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2))
+ {
+ {0x04, 0xff},
+ 0x00543210,
+ 0x2301,
+ {0x01327654, 0x02316457, 0x10234567, 0x01325467},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+#else
+ {
+ {0x04, 0xff},
+ 0x00105432,
+ 0x3210,
+ {0x43256107, 0x07162354, 0x10234567, 0x01235467},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+#endif
+ {
+ {0x04, 0xff},
+ 0x00543210,
+ 0x2301,
+ {0x01327654, 0x02316457, 0x10234567, 0x01325467},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x04, 0xff},
+ 0x00543210,
+ 0x2301,
+ {0x12034765, 0x23105467, 0x23017645, 0x32106745},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
+/* boardcnf[15] RENESAS KRIEK board with H3N */
+ {
+ 0x05,
+ 0x01,
+ 0x300,
+ 0,
+ 0x300,
+ 0x0a0,
+ {
+ {
+ {0x02, 0x02},
+ 0x00345201,
+ 0x3201,
+ {0x01672543, 0x45367012, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0x02},
+ 0x00302154,
+ 0x2310,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x02, 0x02},
+ 0x00302154,
+ 0x2310,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0xff, 0xff},
+ 0,
+ 0,
+ {0, 0, 0, 0},
+ {0, 0, 0, 0},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
+/* boardcnf[16] RENESAS KRIEK-P2P board with M3-W/SoC */
+ {
+ 0x03,
+ 0x01,
+ 0x0320,
+ 0,
+ 0x0300,
+ 0x00a0,
+ {
+ {
+ {0x04, 0x04},
+ 0x520314FFFF523041,
+ 0x3201,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x04, 0x04},
+ 0x314250FFFF312405,
+ 0x2310,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
+/* boardcnf[17] RENESAS KRIEK-P2P board with M3-N/SoC */
+ {
+ 0x01,
+ 0x01,
+ 0x0300,
+ 0,
+ 0x0300,
+ 0x00a0,
+ {
+ {
+ {0x04, 0x04},
+ 0x520314FFFF523041,
+ 0x3201,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
+/* boardcnf[18] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 2rank) */
+ {
+ 0x03,
+ 0x01,
+ 0x02c0,
+ 0,
+ 0x0300,
+ 0x00a0,
+ {
+ {
+ {0x04, 0x04},
+ 0x00543210,
+ 0x3201,
+ {0x70612543, 0x43251670, 0x45326170, 0x10672534},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x04, 0x04},
+ 0x00543210,
+ 0x2310,
+ {0x01327654, 0x34526107, 0x35421670, 0x70615324},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
+/* boardcnf[19] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 1rank) */
+ {
+ 0x03,
+ 0x01,
+ 0x02c0,
+ 0,
+ 0x0300,
+ 0x00a0,
+ {
+ {
+ {0x04, 0xff},
+ 0x00543210,
+ 0x3201,
+ {0x70612543, 0x43251670, 0x45326170, 0x10672534},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x04, 0xff},
+ 0x00543210,
+ 0x2310,
+ {0x01327654, 0x34526107, 0x35421670, 0x70615324},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
+/* boardcnf[20] RENESAS KRIEK 16Gbit/2rank/2ch board with M3-W/SoC */
+ {
+ 0x03,
+ 0x01,
+ 0x02c0,
+ 0,
+ 0x0300,
+ 0x00a0,
+ {
+ {
+ {0x04, 0x04},
+ 0x00345201,
+ 0x3201,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x04, 0x04},
+ 0x00302154,
+ 0x2310,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ },
+/* boardcnf[21] RENESAS KRIEK 16Gbit/1rank/2ch board with M3-W/SoC */
+ {
+ 0x03,
+ 0x01,
+ 0x02c0,
+ 0,
+ 0x0300,
+ 0x00a0,
+ {
+ {
+ {0x04, 0xff},
+ 0x00345201,
+ 0x3201,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ },
+ {
+ {0x04, 0xff},
+ 0x00302154,
+ 0x2310,
+ {0x01672543, 0x45361207, 0x45632107, 0x60715234},
+ {0x08, 0x08, 0x08, 0x08},
+ WDQLVL_PAT,
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0}
+ }
+ }
+ }
+};
+#endif /* RZG_SOC == 1 */
+
+void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div)
+{
+ uint32_t md;
+
+ if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_10)) {
+ *clk = 50;
+ *div = 3;
+ } else {
+ md = (mmio_read_32(RST_MODEMR) >> 13) & 0x3;
+ switch (md) {
+ case 0x0:
+ *clk = 50;
+ *div = 3;
+ break;
+ case 0x1:
+ *clk = 60;
+ *div = 3;
+ break;
+ case 0x2:
+ *clk = 75;
+ *div = 3;
+ break;
+ case 0x3:
+ *clk = 100;
+ *div = 3;
+ break;
+ }
+ }
+ (void)brd;
+}
+
+void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div)
+{
+ uint32_t md;
+
+ if (prr_product == PRR_PRODUCT_V3H) {
+ md = (mmio_read_32(RST_MODEMR) >> 19) & 0x1;
+ md = (md | (md << 1)) & 0x3; /* 0 or 3 */
+ } else {
+ md = (mmio_read_32(RST_MODEMR) >> 17) & 0x5;
+ md = (md | (md >> 1)) & 0x3;
+ }
+ switch (md) {
+ case 0x0:
+ *mbps = 3200;
+ *div = 1;
+ break;
+ case 0x1:
+ *mbps = 2800;
+ *div = 1;
+ break;
+ case 0x2:
+ *mbps = 2400;
+ *div = 1;
+ break;
+ case 0x3:
+ *mbps = 1600;
+ *div = 1;
+ break;
+ }
+ (void)brd;
+}
+
+#define _def_REFPERIOD 1890
+
+#define M3_SAMPLE_TT_A84 0xB866CC10, 0x3B250421
+#define M3_SAMPLE_TT_A85 0xB866CC10, 0x3AA50421
+#define M3_SAMPLE_TT_A86 0xB866CC10, 0x3AA48421
+#define M3_SAMPLE_FF_B45 0xB866CC10, 0x3AB00C21
+#define M3_SAMPLE_FF_B49 0xB866CC10, 0x39B10C21
+#define M3_SAMPLE_FF_B56 0xB866CC10, 0x3AAF8C21
+#define M3_SAMPLE_SS_E24 0xB866CC10, 0x3BA39421
+#define M3_SAMPLE_SS_E28 0xB866CC10, 0x3C231421
+#define M3_SAMPLE_SS_E32 0xB866CC10, 0x3C241421
+
+static const uint32_t termcode_by_sample[20][3] = {
+ {M3_SAMPLE_TT_A84, 0x000158D5},
+ {M3_SAMPLE_TT_A85, 0x00015955},
+ {M3_SAMPLE_TT_A86, 0x00015955},
+ {M3_SAMPLE_FF_B45, 0x00015690},
+ {M3_SAMPLE_FF_B49, 0x00015753},
+ {M3_SAMPLE_FF_B56, 0x00015793},
+ {M3_SAMPLE_SS_E24, 0x00015996},
+ {M3_SAMPLE_SS_E28, 0x000159D7},
+ {M3_SAMPLE_SS_E32, 0x00015997},
+ {0xFFFFFFFF, 0xFFFFFFFF, 0x0001554F}
+};
+
+#ifdef BOARD_JUDGE_AUTO
+/*
+ * SAMPLE board detect function
+ */
+#define PFC_PMMR 0xE6060000U
+#define PFC_PUEN5 0xE6060414U
+#define PFC_PUEN6 0xE6060418U
+#define PFC_PUD5 0xE6060454U
+#define PFC_PUD6 0xE6060458U
+#define GPIO_INDT5 0xE605500CU
+#define GPIO_GPSR6 0xE6060118U
+
+#if (RCAR_GEN3_ULCB == 0) && (RZG_SOC == 0)
+static void pfc_write_and_poll(uint32_t a, uint32_t v)
+{
+ mmio_write_32(PFC_PMMR, ~v);
+ v = ~mmio_read_32(PFC_PMMR);
+ mmio_write_32(a, v);
+ while (v != mmio_read_32(a))
+ ;
+ dsb_sev();
+}
+#endif
+
+#ifndef RCAR_GEN3_ULCB
+#define RCAR_GEN3_ULCB 0
+#endif
+
+#if (RCAR_GEN3_ULCB == 0) && (RZG_SOC == 0) /* non Starter Kit */
+
+static uint32_t opencheck_SSI_WS6(void)
+{
+ uint32_t dataL, down, up;
+ uint32_t gpsr6_bak;
+ uint32_t puen5_bak;
+ uint32_t pud5_bak;
+
+ gpsr6_bak = mmio_read_32(GPIO_GPSR6);
+ puen5_bak = mmio_read_32(PFC_PUEN5);
+ pud5_bak = mmio_read_32(PFC_PUD5);
+ dsb_sev();
+
+ dataL = (gpsr6_bak & ~BIT(15));
+ pfc_write_and_poll(GPIO_GPSR6, dataL);
+
+ /* Pull-Up/Down Enable (PUEN5[22]=1) */
+ dataL = puen5_bak;
+ dataL |= (BIT(22));
+ pfc_write_and_poll(PFC_PUEN5, dataL);
+
+ /* Pull-Down-Enable (PUD5[22]=0, PUEN5[22]=1) */
+ dataL = pud5_bak;
+ dataL &= ~(BIT(22));
+ pfc_write_and_poll(PFC_PUD5, dataL);
+ /* GPSR6[15]=SSI_WS6 */
+ rcar_micro_delay(10);
+ down = (mmio_read_32(GPIO_INDT6) >> 15) & 0x1;
+ dsb_sev();
+
+ /* Pull-Up-Enable (PUD5[22]=1, PUEN5[22]=1) */
+ dataL = pud5_bak;
+ dataL |= (BIT(22));
+ pfc_write_and_poll(PFC_PUD5, dataL);
+
+ /* GPSR6[15]=SSI_WS6 */
+ rcar_micro_delay(10);
+ up = (mmio_read_32(GPIO_INDT6) >> 15) & 0x1;
+
+ dsb_sev();
+
+ pfc_write_and_poll(GPIO_GPSR6, gpsr6_bak);
+ pfc_write_and_poll(PFC_PUEN5, puen5_bak);
+ pfc_write_and_poll(PFC_PUD5, pud5_bak);
+
+ if (down == up) {
+ /* Same = Connect */
+ return 0;
+ }
+
+ /* Diff = Open */
+ return 1;
+}
+
+#endif
+
+#if (RZG_SOC == 1)
+#define LPDDR4_2RANK (0x01U << 25U)
+
+static uint32_t rzg2_board_judge(void)
+{
+ uint32_t brd;
+
+ switch (prr_product) {
+ case PRR_PRODUCT_M3:
+ brd = 1U;
+ if ((mmio_read_32(PRR) & PRR_CUT_MASK) != RCAR_M3_CUT_VER11) {
+ if ((mmio_read_32(GPIO_INDT5) & LPDDR4_2RANK) == 0U) {
+ brd = 0U;
+ }
+ }
+ break;
+ case PRR_PRODUCT_H3:
+ brd = 2U;
+ break;
+ case PRR_PRODUCT_M3N:
+ brd = 3U;
+ break;
+ default:
+ brd = 99U;
+ }
+
+ return brd;
+}
+#endif /* RZG_SOC == 1 */
+
+#if (RZG_SOC == 0) && (RCAR_DRAM_LPDDR4_MEMCONF != 0)
+static uint32_t ddr_rank_judge(void)
+{
+ uint32_t brd;
+
+#if (RCAR_DRAM_MEMRANK == 0)
+ int32_t ret;
+ uint32_t type = 0U;
+ uint32_t rev = 0U;
+
+ brd = 99U;
+ ret = rcar_get_board_type(&type, &rev);
+ if ((ret == 0) && (rev != 0xFFU)) {
+ if (type == (uint32_t)BOARD_SALVATOR_XS) {
+ if (rev == 0x11U) {
+ brd = 14U;
+ } else {
+ brd = 8U;
+ }
+ } else if (type == (uint32_t)BOARD_STARTER_KIT_PRE) {
+ if (rev == 0x21U) {
+ brd = 14U;
+ } else {
+ brd = 8U;
+ }
+ }
+ }
+#elif (RCAR_DRAM_MEMRANK == 1)
+ brd = 14U;
+#elif (RCAR_DRAM_MEMRANK == 2)
+ brd = 8U;
+#else
+#error Invalid value was set to RCAR_DRAM_MEMRANK
+#endif /* (RCAR_DRAM_MEMRANK == 0) */
+ return brd;
+}
+#endif /* (RCAR_DRAM_LPDDR4_MEMCONF != 0) */
+
+static uint32_t _board_judge(void)
+{
+ uint32_t brd;
+
+#if (RZG_SOC == 1)
+ brd = rzg2_board_judge();
+#else
+#if (RCAR_GEN3_ULCB == 1)
+ /* Starter Kit */
+ if (prr_product == PRR_PRODUCT_H3) {
+ if (prr_cut <= PRR_PRODUCT_11) {
+ /* RENESAS Starter Kit(H3 Ver.1.x/SIP) board */
+ brd = 2;
+ } else {
+ /* RENESAS Starter Kit(H3 Ver.2.0 or later/SIP) board */
+#if (RCAR_DRAM_LPDDR4_MEMCONF == 0)
+ brd = 7;
+#else
+ brd = ddr_rank_judge();
+#endif
+ }
+ } else if (prr_product == PRR_PRODUCT_M3) {
+ if (prr_cut >= PRR_PRODUCT_30) {
+ /* RENESAS Starter Kit (M3-W Ver.3.0/SIP) */
+ brd = 18;
+ } else {
+ /* RENESAS Starter Kit(M3-W/SIP 8Gbit 1rank) board */
+ brd = 3;
+ }
+ } else {
+ /* RENESAS Starter Kit(M3-N/SIP) board */
+ brd = 11;
+ }
+#else
+ uint32_t usb2_ovc_open;
+
+ usb2_ovc_open = opencheck_SSI_WS6();
+
+ /* RENESAS Eva-board */
+ brd = 99;
+ if (prr_product == PRR_PRODUCT_V3H) {
+ /* RENESAS Condor board */
+ brd = 12;
+ } else if (usb2_ovc_open) {
+ if (prr_product == PRR_PRODUCT_M3N) {
+ /* RENESAS Kriek board with M3-N */
+ brd = 10;
+ } else if (prr_product == PRR_PRODUCT_M3) {
+ /* RENESAS Kriek board with M3-W */
+ brd = 1;
+ } else if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut <= PRR_PRODUCT_11)) {
+ /* RENESAS Kriek board with PM3 */
+ brd = 13;
+ } else if ((prr_product == PRR_PRODUCT_H3) &&
+ (prr_cut > PRR_PRODUCT_20)) {
+ /* RENESAS Kriek board with H3N */
+ brd = 15;
+ }
+ } else {
+ if (prr_product == PRR_PRODUCT_H3) {
+ if (prr_cut <= PRR_PRODUCT_11) {
+ /* RENESAS SALVATOR-X (H3 Ver.1.x/SIP) */
+ brd = 2;
+ } else if (prr_cut < PRR_PRODUCT_30) {
+ /* RENESAS SALVATOR-X (H3 Ver.2.0/SIP) */
+ brd = 7; // 8Gbit/1rank
+ } else {
+ /* RENESAS SALVATOR-X (H3 Ver.3.0/SIP) */
+#if (RCAR_DRAM_LPDDR4_MEMCONF == 0)
+ brd = 7;
+#else
+ brd = ddr_rank_judge();
+#endif
+ }
+ } else if (prr_product == PRR_PRODUCT_M3N) {
+ /* RENESAS SALVATOR-X (M3-N/SIP) */
+ brd = 11;
+ } else if ((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut <= PRR_PRODUCT_20)) {
+ /* RENESAS SALVATOR-X (M3-W/SIP) */
+ brd = 0;
+ } else if ((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut < PRR_PRODUCT_30)) {
+ /* RENESAS SALVATOR-X (M3-W Ver.1.x/SIP) */
+ brd = 19;
+ } else if ((prr_product == PRR_PRODUCT_M3) &&
+ (prr_cut >= PRR_PRODUCT_30)) {
+ /* RENESAS SALVATOR-X (M3-W ver.3.0/SIP) */
+ brd = 18;
+ }
+ }
+#endif
+#endif /* RZG_SOC == 1 */
+
+ return brd;
+}
+#endif
diff --git a/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h
new file mode 100644
index 0000000..3cb1975
--- /dev/null
+++ b/drivers/renesas/common/ddr/ddr_b/boot_init_dram_regdef.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation.
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#define RCAR_DDR_VERSION "rev.0.41"
+#define DRAM_CH_CNT 0x04
+#define SLICE_CNT 0x04
+#define CS_CNT 0x02
+
+/* order : CS0A, CS0B, CS1A, CS1B */
+#define CSAB_CNT (CS_CNT * 2)
+
+/* order : CH0A, CH0B, CH1A, CH1B, CH2A, CH2B, CH3A, CH3B */
+#define CHAB_CNT (DRAM_CH_CNT * 2)
+
+/* pll setting */
+#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
+#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb)))
+
+/* for ddr deisity setting */
+#define DBMEMCONF_REG(d3, row, bank, col, dw) \
+ (((d3) << 30) | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
+
+#define DBMEMCONF_REGD(density) \
+ (DBMEMCONF_REG((density) % 2, ((density) + 1) / \
+ 2 + (29 - 3 - 10 - 2), 3, 10, 2))
+
+#define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs)))
+
+/* refresh mode */
+#define DBSC_REFINTS (0x0)
+
+/* system registers */
+#define CPG_FRQCRB (CPG_BASE + 0x0004U)
+
+#define CPG_PLLECR (CPG_BASE + 0x00D0U)
+#define CPG_MSTPSR5 (CPG_BASE + 0x003CU)
+#define CPG_SRCR4 (CPG_BASE + 0x00BCU)
+#define CPG_PLL3CR (CPG_BASE + 0x00DCU)
+#define CPG_ZB3CKCR (CPG_BASE + 0x0380U)
+#define CPG_FRQCRD (CPG_BASE + 0x00E4U)
+#define CPG_SMSTPCR5 (CPG_BASE + 0x0144U)
+#define CPG_CPGWPR (CPG_BASE + 0x0900U)
+#define CPG_SRSTCLR4 (CPG_BASE + 0x0950U)
+
+#define CPG_FRQCRB_KICK_BIT BIT(31)
+#define CPG_PLLECR_PLL3E_BIT BIT(3)
+#define CPG_PLLECR_PLL3ST_BIT BIT(11)
+#define CPG_ZB3CKCR_ZB3ST_BIT BIT(11)
+
+#define RST_BASE (0xE6160000U)
+#define RST_MODEMR (RST_BASE + 0x0060U)
+
+#define LIFEC_CHIPID(x) (0xE6110040U + 0x04U * (x))
+
+/* DBSC registers */
+#include "../ddr_regs.h"
+
+#define DBSC_DBMONCONF4 0xE6793010U
+
+#define DBSC_PLL_LOCK(ch) (0xE6794054U + 0x100U * (ch))
+#define DBSC_PLL_LOCK_0 0xE6794054U
+#define DBSC_PLL_LOCK_1 0xE6794154U
+#define DBSC_PLL_LOCK_2 0xE6794254U
+#define DBSC_PLL_LOCK_3 0xE6794354U
+
+/* STAT registers */
+#define MSTAT_SL_INIT 0xE67E8000U
+#define MSTAT_REF_ARS 0xE67E8004U
+#define MSTATQ_STATQC 0xE67E8008U
+#define MSTATQ_WTENABLE 0xE67E8030U
+#define MSTATQ_WTREFRESH 0xE67E8034U
+#define MSTATQ_WTSETTING0 0xE67E8038U
+#define MSTATQ_WTSETTING1 0xE67E803CU
+
+#define QOS_BASE1 (0xE67F0000U)
+#define QOSCTRL_RAS (QOS_BASE1 + 0x0000U)
+#define QOSCTRL_FIXTH (QOS_BASE1 + 0x0004U)
+#define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U)
+#define QOSCTRL_REGGD (QOS_BASE1 + 0x0020U)
+#define QOSCTRL_DANN (QOS_BASE1 + 0x0030U)
+#define QOSCTRL_DANT (QOS_BASE1 + 0x0038U)
+#define QOSCTRL_EC (QOS_BASE1 + 0x003CU)
+#define QOSCTRL_EMS (QOS_BASE1 + 0x0040U)
+#define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U)
+#define QOSCTRL_BERR (QOS_BASE1 + 0x0054U)
+#define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U)
+#define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U)
+
+/* other module */
+#define THS1_THCTR 0xE6198020U
+#define THS1_TEMP 0xE6198028U
diff --git a/drivers/renesas/common/ddr/ddr_b/ddr_b.mk b/drivers/renesas/common/ddr/ddr_b/ddr_b.mk
new file mode 100644
index 0000000..0334780
--- /dev/null
+++ b/drivers/renesas/common/ddr/ddr_b/ddr_b.mk
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+BL2_SOURCES += drivers/renesas/common/ddr/ddr_b/boot_init_dram.c
diff --git a/drivers/renesas/rcar/ddr/ddr_b/ddr_regdef.h b/drivers/renesas/common/ddr/ddr_b/ddr_regdef.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_b/ddr_regdef.h
rename to drivers/renesas/common/ddr/ddr_b/ddr_regdef.h
diff --git a/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_h3.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h
rename to drivers/renesas/common/ddr/ddr_b/init_dram_tbl_h3.h
diff --git a/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_h3ver2.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3ver2.h
rename to drivers/renesas/common/ddr/ddr_b/init_dram_tbl_h3ver2.h
diff --git a/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3.h
rename to drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3.h
diff --git a/drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h b/drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3n.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
rename to drivers/renesas/common/ddr/ddr_b/init_dram_tbl_m3n.h
diff --git a/drivers/renesas/rcar/ddr/dram_sub_func.c b/drivers/renesas/common/ddr/dram_sub_func.c
similarity index 100%
rename from drivers/renesas/rcar/ddr/dram_sub_func.c
rename to drivers/renesas/common/ddr/dram_sub_func.c
diff --git a/drivers/renesas/rcar/ddr/dram_sub_func.h b/drivers/renesas/common/ddr/dram_sub_func.h
similarity index 100%
rename from drivers/renesas/rcar/ddr/dram_sub_func.h
rename to drivers/renesas/common/ddr/dram_sub_func.h
diff --git a/drivers/renesas/common/emmc/emmc_init.c b/drivers/renesas/common/emmc/emmc_init.c
index 354aa3c..c0ec600 100644
--- a/drivers/renesas/common/emmc/emmc_init.c
+++ b/drivers/renesas/common/emmc/emmc_init.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,6 +14,7 @@
#include "emmc_registers.h"
#include "emmc_def.h"
#include "rcar_private.h"
+#include "cpg_registers.h"
st_mmc_base mmc_drv_obj;
@@ -87,11 +88,11 @@
SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */
SETR_32(SD_CLK_CTRL, 0x00000000U); /* MMC clock stop */
- dataL = mmio_read_32(CPG_SMSTPCR3);
+ dataL = mmio_read_32(SMSTPCR3);
if ((dataL & CPG_MSTP_MMC) == 0U) {
dataL |= (CPG_MSTP_MMC);
mmio_write_32(CPG_CPGWPR, (~dataL));
- mmio_write_32(CPG_SMSTPCR3, dataL);
+ mmio_write_32(SMSTPCR3, dataL);
}
return result;
@@ -100,7 +101,7 @@
static EMMC_ERROR_CODE emmc_dev_init(void)
{
/* Enable clock supply to eMMC. */
- mstpcr_write(CPG_SMSTPCR3, CPG_MSTPSR3, CPG_MSTP_MMC);
+ mstpcr_write(SMSTPCR3, CPG_MSTPSR3, CPG_MSTP_MMC);
/* Set SD clock */
mmio_write_32(CPG_CPGWPR, ~((uint32_t) (BIT9 | BIT0))); /* SD phy 200MHz */
diff --git a/drivers/renesas/common/emmc/emmc_registers.h b/drivers/renesas/common/emmc/emmc_registers.h
index 392abb8..67d285d 100644
--- a/drivers/renesas/common/emmc/emmc_registers.h
+++ b/drivers/renesas/common/emmc/emmc_registers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,11 +11,11 @@
#define MMC_CH0 (0U) /* SDHI2/MMC0 */
#define MMC_CH1 (1U) /* SDHI3/MMC1 */
-#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2M)
-#define USE_MMC_CH (MMC_CH1) /* R-Car E3 or RZ/G2M */
-#else /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2M */
+#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2M) || (RCAR_LSI == RZ_G2H) || (RCAR_LSI == RZ_G2N)
+#define USE_MMC_CH (MMC_CH1) /* R-Car E3 or RZ/G2{H,M,N} */
+#else /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2{H,M,N} */
#define USE_MMC_CH (MMC_CH0) /* R-Car H3/M3/M3N */
-#endif /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2M */
+#endif /* RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2{H,M,N} */
#define BIT0 (0x00000001U)
#define BIT1 (0x00000002U)
@@ -50,19 +50,6 @@
#define BIT30 (0x40000000U)
#define BIT31 (0x80000000U)
-/* Clock Pulse Generator (CPG) registers */
-#define CPG_BASE (0xE6150000U)
-/* Module stop status register 3 */
-#define CPG_MSTPSR3 (CPG_BASE + 0x0048U)
-/* System module stop control register 3 */
-#define CPG_SMSTPCR3 (CPG_BASE + 0x013CU)
-/* SDHI2 clock frequency control register */
-#define CPG_SD2CKCR (CPG_BASE + 0x0268U)
-/* SDHI3 clock frequency control register */
-#define CPG_SD3CKCR (CPG_BASE + 0x026CU)
-/* CPG Write Protect Register */
-#define CPG_CPGWPR (CPG_BASE + 0x0900U)
-
#if USE_MMC_CH == MMC_CH0
#define CPG_SDxCKCR (CPG_SD2CKCR) /* SDHI2/MMC0 */
#else /* USE_MMC_CH == MMC_CH0 */
diff --git a/drivers/renesas/common/iic_dvfs/iic_dvfs.c b/drivers/renesas/common/iic_dvfs/iic_dvfs.c
index e1c9a5b..bf80697 100644
--- a/drivers/renesas/common/iic_dvfs/iic_dvfs.c
+++ b/drivers/renesas/common/iic_dvfs/iic_dvfs.c
@@ -517,7 +517,7 @@
uint32_t err = 0U;
mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS);
- mmio_write_8(IIC_DVFS_REG_ICCR, 0U);
+ mmio_write_8(IIC_DVFS_REG_ICCR, 1U);
again:
switch (state) {
case DVFS_START:
@@ -557,7 +557,7 @@
uint32_t err = 0U;
mstpcr_write(SCMSTPCR9, CPG_MSTPSR9, CPG_BIT_SMSTPCR9_DVFS);
- mmio_write_8(IIC_DVFS_REG_ICCR, 0U);
+ mmio_write_8(IIC_DVFS_REG_ICCR, 1U);
again:
switch (state) {
case DVFS_START:
diff --git a/drivers/renesas/common/pwrc/pwrc.c b/drivers/renesas/common/pwrc/pwrc.c
index c0f015f..3f60fe6 100644
--- a/drivers/renesas/common/pwrc/pwrc.c
+++ b/drivers/renesas/common/pwrc/pwrc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -20,6 +20,7 @@
#include "pwrc.h"
#include "rcar_def.h"
#include "rcar_private.h"
+#include "cpg_registers.h"
/*
* Someday there will be a generic power controller api. At the moment each
@@ -238,7 +239,7 @@
scu_power_up(mpidr);
cpu = mpidr & MPIDR_CPU_MASK;
on_data = 1 << cpu;
- mmio_write_32(RCAR_CPGWPR, ~on_data);
+ mmio_write_32(CPG_CPGWPR, ~on_data);
mmio_write_32(on_reg, on_data);
mmio_write_32(res_reg, res_data & (~(1 << (3 - cpu))));
@@ -260,7 +261,7 @@
if (read_mpidr_el1() != mpidr)
panic();
- mmio_write_32(RCAR_CPGWPR, ~CPU_PWR_OFF);
+ mmio_write_32(CPG_CPGWPR, ~CPU_PWR_OFF);
mmio_write_32(reg + cpu * 0x0010, CPU_PWR_OFF);
rcar_lock_release();
diff --git a/drivers/renesas/common/watchdog/swdt.c b/drivers/renesas/common/watchdog/swdt.c
index 05987ab..1a351ca 100644
--- a/drivers/renesas/common/watchdog/swdt.c
+++ b/drivers/renesas/common/watchdog/swdt.c
@@ -78,7 +78,7 @@
void rcar_swdt_init(void)
{
uint32_t rmsk, sr;
-#if (RCAR_LSI != RCAR_E3)
+#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RZ_G2E)
uint32_t reg, val, product_cut, chk_data;
reg = mmio_read_32(RCAR_PRR);
@@ -94,7 +94,7 @@
mmio_write_32(SWDT_WTCSRA, WTCSRA_UPPER_BYTE |
WTCSRA_WOVFE | WTCSRA_CKS_DIV16);
-#if (RCAR_LSI == RCAR_E3)
+#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2E)
mmio_write_32(SWDT_WTCNT, WTCNT_UPPER_BYTE | WTCNT_COUNT_7p81k);
#else
val = WTCNT_UPPER_BYTE;
diff --git a/drivers/renesas/rcar/board/board.c b/drivers/renesas/rcar/board/board.c
index cd194ff..dbbaed6 100644
--- a/drivers/renesas/rcar/board/board.c
+++ b/drivers/renesas/rcar/board/board.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights
* reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -30,9 +30,9 @@
#define BOARD_CODE_SHIFT (0x03)
#define BOARD_ID_UNKNOWN (0xFF)
-#define SXS_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
+#define SXS_ID { 0x10U, 0x11U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
#define SX_ID { 0x10U, 0x11U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
-#define SKP_ID { 0x10U, 0x10U, 0x20U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
+#define SKP_ID { 0x10U, 0x10U, 0x20U, 0x21U, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
#define SK_ID { 0x10U, 0x30U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
#define EB4_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
#define EB_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
diff --git a/drivers/renesas/rcar/ddr/ddr.mk b/drivers/renesas/rcar/ddr/ddr.mk
deleted file mode 100644
index c26993d..0000000
--- a/drivers/renesas/rcar/ddr/ddr.mk
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-ifeq (${RCAR_LSI},${RCAR_E3})
- include drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
- BL2_SOURCES += drivers/renesas/rcar/ddr/dram_sub_func.c
-else ifeq (${RCAR_LSI},${RCAR_D3})
- include drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
-else ifeq (${RCAR_LSI},${RCAR_V3M})
- include drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
-else
- include drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk
- BL2_SOURCES += drivers/renesas/rcar/ddr/dram_sub_func.c
-endif
diff --git a/drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk b/drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
deleted file mode 100644
index 7882558..0000000
--- a/drivers/renesas/rcar/ddr/ddr_a/ddr_a.mk
+++ /dev/null
@@ -1,13 +0,0 @@
-#
-# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-ifeq (${RCAR_LSI},${RCAR_E3})
-BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
-else ifeq (${RCAR_LSI},${RCAR_D3})
-BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_a/ddr_init_d3.c
-else
-BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_a/ddr_init_v3m.c
-endif
diff --git a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c
deleted file mode 100644
index ac83c9a..0000000
--- a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c
+++ /dev/null
@@ -1,4474 +0,0 @@
-/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation.
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <stdio.h>
-
-#include <common/debug.h>
-#include <lib/mmio.h>
-
-#include "ddr_regdef.h"
-#include "init_dram_tbl_h3.h"
-#include "init_dram_tbl_m3.h"
-#include "init_dram_tbl_h3ver2.h"
-#include "init_dram_tbl_m3n.h"
-#include "boot_init_dram_regdef.h"
-#include "boot_init_dram.h"
-#include "dram_sub_func.h"
-#include "micro_delay.h"
-#include "rcar_def.h"
-
-#define DDR_BACKUPMODE
-#define FATAL_MSG(x) NOTICE(x)
-
-/* variables */
-#ifdef RCAR_DDR_FIXED_LSI_TYPE
-#ifndef RCAR_AUTO
-#define RCAR_AUTO 99
-#define RCAR_H3 0
-#define RCAR_M3 1
-#define RCAR_M3N 2
-#define RCAR_E3 3 /* NON */
-#define RCAR_H3N 4
-
-#define RCAR_CUT_10 0
-#define RCAR_CUT_11 1
-#define RCAR_CUT_20 10
-#define RCAR_CUT_30 20
-#endif
-#ifndef RCAR_LSI
-#define RCAR_LSI RCAR_AUTO
-#endif
-
-#if (RCAR_LSI == RCAR_AUTO)
-static uint32_t prr_product;
-static uint32_t prr_cut;
-#else
-#if (RCAR_LSI == RCAR_H3)
-static const uint32_t prr_product = PRR_PRODUCT_H3;
-#elif(RCAR_LSI == RCAR_M3)
-static const uint32_t prr_product = PRR_PRODUCT_M3;
-#elif(RCAR_LSI == RCAR_M3N)
-static const uint32_t prr_product = PRR_PRODUCT_M3N;
-#elif(RCAR_LSI == RCAR_H3N)
-static const uint32_t prr_product = PRR_PRODUCT_H3;
-#endif /* RCAR_LSI */
-
-#ifndef RCAR_LSI_CUT
-static uint32_t prr_cut;
-#else /* RCAR_LSI_CUT */
-#if (RCAR_LSI_CUT == RCAR_CUT_10)
-static const uint32_t prr_cut = PRR_PRODUCT_10;
-#elif(RCAR_LSI_CUT == RCAR_CUT_11)
-static const uint32_t prr_cut = PRR_PRODUCT_11;
-#elif(RCAR_LSI_CUT == RCAR_CUT_20)
-static const uint32_t prr_cut = PRR_PRODUCT_20;
-#elif(RCAR_LSI_CUT == RCAR_CUT_30)
-static const uint32_t prr_cut = PRR_PRODUCT_30;
-#endif /* RCAR_LSI_CUT */
-#endif /* RCAR_LSI_CUT */
-#endif /* RCAR_AUTO_NON */
-#else /* RCAR_DDR_FIXED_LSI_TYPE */
-static uint32_t prr_product;
-static uint32_t prr_cut;
-#endif /* RCAR_DDR_FIXED_LSI_TYPE */
-
-static const uint32_t *p_ddr_regdef_tbl;
-static uint32_t brd_clk;
-static uint32_t brd_clkdiv;
-static uint32_t brd_clkdiva;
-static uint32_t ddr_mbps;
-static uint32_t ddr_mbpsdiv;
-static uint32_t ddr_tccd;
-static uint32_t ddr_phycaslice;
-static const struct _boardcnf *board_cnf;
-static uint32_t ddr_phyvalid;
-static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT];
-static uint32_t ch_have_this_cs[CS_CNT] __aligned(64);
-static uint32_t rdqdm_dly[DRAM_CH_CNT][CSAB_CNT][SLICE_CNT * 2][9];
-static uint32_t max_density;
-static uint32_t ddr0800_mul;
-static uint32_t ddr_mul;
-static uint32_t DDR_PHY_SLICE_REGSET_OFS;
-static uint32_t DDR_PHY_ADR_V_REGSET_OFS;
-static uint32_t DDR_PHY_ADR_I_REGSET_OFS;
-static uint32_t DDR_PHY_ADR_G_REGSET_OFS;
-static uint32_t DDR_PI_REGSET_OFS;
-static uint32_t DDR_PHY_SLICE_REGSET_SIZE;
-static uint32_t DDR_PHY_ADR_V_REGSET_SIZE;
-static uint32_t DDR_PHY_ADR_I_REGSET_SIZE;
-static uint32_t DDR_PHY_ADR_G_REGSET_SIZE;
-static uint32_t DDR_PI_REGSET_SIZE;
-static uint32_t DDR_PHY_SLICE_REGSET_NUM;
-static uint32_t DDR_PHY_ADR_V_REGSET_NUM;
-static uint32_t DDR_PHY_ADR_I_REGSET_NUM;
-static uint32_t DDR_PHY_ADR_G_REGSET_NUM;
-static uint32_t DDR_PI_REGSET_NUM;
-static uint32_t DDR_PHY_ADR_I_NUM;
-#define DDR_PHY_REGSET_MAX 128
-#define DDR_PI_REGSET_MAX 320
-static uint32_t _cnf_DDR_PHY_SLICE_REGSET[DDR_PHY_REGSET_MAX];
-static uint32_t _cnf_DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX];
-static uint32_t _cnf_DDR_PHY_ADR_I_REGSET[DDR_PHY_REGSET_MAX];
-static uint32_t _cnf_DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX];
-static uint32_t _cnf_DDR_PI_REGSET[DDR_PI_REGSET_MAX];
-static uint32_t pll3_mode;
-static uint32_t loop_max;
-#ifdef DDR_BACKUPMODE
-uint32_t ddr_backup;
-/* #define DDR_BACKUPMODE_HALF //for Half channel(ch0,1 only) */
-#endif
-
-#ifdef ddr_qos_init_setting /* only for non qos_init */
-#define OPERATING_FREQ (400U) /* Mhz */
-#define BASE_SUB_SLOT_NUM (0x6U)
-#define SUB_SLOT_CYCLE (0x7EU) /* 126 */
-#define QOSWT_WTSET0_CYCLE \
- ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / \
- OPERATING_FREQ) /* unit:ns */
-
-uint32_t get_refperiod(void)
-{
- return QOSWT_WTSET0_CYCLE;
-}
-#else /* ddr_qos_init_setting // only for non qos_init */
-extern uint32_t get_refperiod(void);
-#endif /* ddr_qos_init_setting // only for non qos_init */
-
-#define _reg_PHY_RX_CAL_X_NUM 11
-static const uint32_t _reg_PHY_RX_CAL_X[_reg_PHY_RX_CAL_X_NUM] = {
- _reg_PHY_RX_CAL_DQ0,
- _reg_PHY_RX_CAL_DQ1,
- _reg_PHY_RX_CAL_DQ2,
- _reg_PHY_RX_CAL_DQ3,
- _reg_PHY_RX_CAL_DQ4,
- _reg_PHY_RX_CAL_DQ5,
- _reg_PHY_RX_CAL_DQ6,
- _reg_PHY_RX_CAL_DQ7,
- _reg_PHY_RX_CAL_DM,
- _reg_PHY_RX_CAL_DQS,
- _reg_PHY_RX_CAL_FDBK
-};
-
-#define _reg_PHY_CLK_WRX_SLAVE_DELAY_NUM 10
-static const uint32_t _reg_PHY_CLK_WRX_SLAVE_DELAY
- [_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = {
- _reg_PHY_CLK_WRDQ0_SLAVE_DELAY,
- _reg_PHY_CLK_WRDQ1_SLAVE_DELAY,
- _reg_PHY_CLK_WRDQ2_SLAVE_DELAY,
- _reg_PHY_CLK_WRDQ3_SLAVE_DELAY,
- _reg_PHY_CLK_WRDQ4_SLAVE_DELAY,
- _reg_PHY_CLK_WRDQ5_SLAVE_DELAY,
- _reg_PHY_CLK_WRDQ6_SLAVE_DELAY,
- _reg_PHY_CLK_WRDQ7_SLAVE_DELAY,
- _reg_PHY_CLK_WRDM_SLAVE_DELAY,
- _reg_PHY_CLK_WRDQS_SLAVE_DELAY
-};
-
-#define _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM 9
-static const uint32_t _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY
- [_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = {
- _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY,
- _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY
-};
-
-#define _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM 9
-static const uint32_t _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY
- [_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = {
- _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY,
- _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY
-};
-
-#define _reg_PHY_PAD_TERM_X_NUM 8
-static const uint32_t _reg_PHY_PAD_TERM_X[_reg_PHY_PAD_TERM_X_NUM] = {
- _reg_PHY_PAD_FDBK_TERM,
- _reg_PHY_PAD_DATA_TERM,
- _reg_PHY_PAD_DQS_TERM,
- _reg_PHY_PAD_ADDR_TERM,
- _reg_PHY_PAD_CLK_TERM,
- _reg_PHY_PAD_CKE_TERM,
- _reg_PHY_PAD_RST_TERM,
- _reg_PHY_PAD_CS_TERM
-};
-
-#define _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM 10
-static const uint32_t _reg_PHY_CLK_CACS_SLAVE_DELAY_X
- [_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = {
- _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY,
- _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY,
- _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY,
- _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY,
- _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY,
- _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY,
-
- _reg_PHY_GRP_SLAVE_DELAY_0,
- _reg_PHY_GRP_SLAVE_DELAY_1,
- _reg_PHY_GRP_SLAVE_DELAY_2,
- _reg_PHY_GRP_SLAVE_DELAY_3
-};
-
-/* Prototypes */
-static inline uint32_t vch_nxt(uint32_t pos);
-static void cpg_write_32(uint32_t a, uint32_t v);
-static void pll3_control(uint32_t high);
-static inline void dsb_sev(void);
-static void wait_dbcmd(void);
-static void send_dbcmd(uint32_t cmd);
-static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd);
-static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata);
-static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata);
-static inline uint32_t ddr_regdef(uint32_t _regdef);
-static inline uint32_t ddr_regdef_adr(uint32_t _regdef);
-static inline uint32_t ddr_regdef_lsb(uint32_t _regdef);
-static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
- uint32_t val);
-static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef);
-static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val);
-static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val);
-static void ddr_setval_ach(uint32_t regdef, uint32_t val);
-static void ddr_setval_ach_as(uint32_t regdef, uint32_t val);
-static uint32_t ddr_getval(uint32_t ch, uint32_t regdef);
-static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p);
-static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p);
-static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size);
-static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val);
-static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef);
-static uint32_t ddrphy_regif_chk(void);
-static inline void ddrphy_regif_idle(void);
-static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps,
- uint16_t cyc);
-static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv,
- uint16_t *_js2);
-static int16_t _f_scale_adj(int16_t ps);
-static void ddrtbl_load(void);
-static void ddr_config_sub(void);
-static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz);
-static void ddr_config_sub_h3v1x(void);
-static void ddr_config(void);
-static void dbsc_regset(void);
-static void dbsc_regset_post(void);
-static uint32_t dfi_init_start(void);
-static void change_lpddr4_en(uint32_t mode);
-static uint32_t set_term_code(void);
-static void ddr_register_set(void);
-static inline uint32_t wait_freqchgreq(uint32_t assert);
-static inline void set_freqchgack(uint32_t assert);
-static inline void set_dfifrequency(uint32_t freq);
-static uint32_t pll3_freq(uint32_t on);
-static void update_dly(void);
-static uint32_t pi_training_go(void);
-static uint32_t init_ddr(void);
-static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick);
-static uint32_t wdqdm_man1(void);
-static uint32_t wdqdm_man(void);
-static uint32_t rdqdm_man1(void);
-static uint32_t rdqdm_man(void);
-
-static int32_t _find_change(uint64_t val, uint32_t dir);
-static uint32_t _rx_offset_cal_updn(uint32_t code);
-static uint32_t rx_offset_cal(void);
-static uint32_t rx_offset_cal_hw(void);
-static void adjust_rddqs_latency(void);
-static void adjust_wpath_latency(void);
-
-struct ddrt_data {
- int32_t init_temp; /* Initial Temperature (do) */
- uint32_t init_cal[4]; /* Initial io-code (4 is for H3) */
- uint32_t tcomp_cal[4]; /* Temp. compensated io-code (4 is for H3) */
-};
-
-static struct ddrt_data tcal;
-
-static void pvtcode_update(void);
-static void pvtcode_update2(void);
-static void ddr_padcal_tcompensate_getinit(uint32_t override);
-
-/* load board configuration */
-#include "boot_init_dram_config.c"
-
-#ifndef DDR_FAST_INIT
-static uint32_t rdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
-static uint32_t rdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
-static uint32_t rdqdm_nw[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
-static uint32_t rdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
-static uint32_t rdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2];
-static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
-static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
-
-static uint32_t wdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9];
-static uint32_t wdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9];
-static uint32_t wdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9];
-static uint32_t wdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
-static uint32_t wdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
-static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
-static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
-#endif/* DDR_FAST_INIT */
-
-/* macro for channel selection loop */
-static inline uint32_t vch_nxt(uint32_t pos)
-{
- uint32_t posn;
-
- for (posn = pos; posn < DRAM_CH_CNT; posn++) {
- if (ddr_phyvalid & (1U << posn))
- break;
- }
- return posn;
-}
-
-#define foreach_vch(ch) \
-for (ch = vch_nxt(0); ch < DRAM_CH_CNT; ch = vch_nxt(ch + 1))
-
-#define foreach_ech(ch) \
-for (ch = 0; ch < DRAM_CH_CNT; ch++)
-
-/* Printing functions */
-#define MSG_LF(...)
-
-/* clock settings, reset control */
-static void cpg_write_32(uint32_t a, uint32_t v)
-{
- mmio_write_32(CPG_CPGWPR, ~v);
- mmio_write_32(a, v);
-}
-
-static void pll3_control(uint32_t high)
-{
- uint32_t data_l, data_div, data_mul, tmp_div;
-
- if (high) {
- tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
- (brd_clk * ddr_mul) / 2;
- data_mul = ((ddr_mul * tmp_div) - 1) << 24;
- pll3_mode = 1;
- loop_max = 2;
- } else {
- tmp_div = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
- (brd_clk * ddr0800_mul) / 2;
- data_mul = ((ddr0800_mul * tmp_div) - 1) << 24;
- pll3_mode = 0;
- loop_max = 8;
- }
-
- switch (tmp_div) {
- case 1:
- data_div = 0;
- break;
- case 2:
- case 3:
- case 4:
- data_div = tmp_div;
- break;
- default:
- data_div = 6;
- data_mul = (data_mul * tmp_div) / 3;
- break;
- }
- data_mul = data_mul | (brd_clkdiva << 7);
-
- /* PLL3 disable */
- data_l = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT;
- cpg_write_32(CPG_PLLECR, data_l);
- dsb_sev();
-
- if ((prr_product == PRR_PRODUCT_M3) ||
- ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_20))) {
- /* PLL3 DIV resetting(Lowest value:3) */
- data_l = 0x00030003 | (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
- cpg_write_32(CPG_FRQCRD, data_l);
- dsb_sev();
-
- /* zb3 clk stop */
- data_l = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR);
- cpg_write_32(CPG_ZB3CKCR, data_l);
- dsb_sev();
-
- /* PLL3 enable */
- data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
- cpg_write_32(CPG_PLLECR, data_l);
- dsb_sev();
-
- do {
- data_l = mmio_read_32(CPG_PLLECR);
- } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
- dsb_sev();
-
- /* PLL3 DIV resetting (Highest value:0) */
- data_l = (0xFF80FF80 & mmio_read_32(CPG_FRQCRD));
- cpg_write_32(CPG_FRQCRD, data_l);
- dsb_sev();
-
- /* DIV SET KICK */
- data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
- cpg_write_32(CPG_FRQCRB, data_l);
- dsb_sev();
-
- /* PLL3 multiplie set */
- cpg_write_32(CPG_PLL3CR, data_mul);
- dsb_sev();
-
- do {
- data_l = mmio_read_32(CPG_PLLECR);
- } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
- dsb_sev();
-
- /* PLL3 DIV resetting(Target value) */
- data_l = (data_div << 16) | data_div |
- (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80);
- cpg_write_32(CPG_FRQCRD, data_l);
- dsb_sev();
-
- /* DIV SET KICK */
- data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
- cpg_write_32(CPG_FRQCRB, data_l);
- dsb_sev();
-
- do {
- data_l = mmio_read_32(CPG_PLLECR);
- } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
- dsb_sev();
-
- /* zb3 clk start */
- data_l = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR);
- cpg_write_32(CPG_ZB3CKCR, data_l);
- dsb_sev();
-
- } else { /* H3Ver.3.0/M3N/V3H */
-
- /* PLL3 multiplie set */
- cpg_write_32(CPG_PLL3CR, data_mul);
- dsb_sev();
-
- /* PLL3 DIV set(Target value) */
- data_l = (data_div << 16) | data_div |
- (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80);
- cpg_write_32(CPG_FRQCRD, data_l);
-
- /* DIV SET KICK */
- data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
- cpg_write_32(CPG_FRQCRB, data_l);
- dsb_sev();
-
- /* PLL3 enable */
- data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
- cpg_write_32(CPG_PLLECR, data_l);
- dsb_sev();
-
- do {
- data_l = mmio_read_32(CPG_PLLECR);
- } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
- dsb_sev();
- }
-}
-
-/* barrier */
-static inline void dsb_sev(void)
-{
- __asm__ __volatile__("dsb sy");
-}
-
-/* DDR memory register access */
-static void wait_dbcmd(void)
-{
- uint32_t data_l;
- /* dummy read */
- data_l = mmio_read_32(DBSC_DBCMD);
- dsb_sev();
- while (1) {
- /* wait DBCMD 1=busy, 0=ready */
- data_l = mmio_read_32(DBSC_DBWAIT);
- dsb_sev();
- if ((data_l & 0x00000001) == 0x00)
- break;
- }
-}
-
-static void send_dbcmd(uint32_t cmd)
-{
- /* dummy read */
- wait_dbcmd();
- mmio_write_32(DBSC_DBCMD, cmd);
- dsb_sev();
-}
-
-static void dbwait_loop(uint32_t wait_loop)
-{
- uint32_t i;
-
- for (i = 0; i < wait_loop; i++)
- wait_dbcmd();
-}
-
-/* DDRPHY register access (raw) */
-static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd)
-{
- uint32_t val;
- uint32_t loop;
-
- val = 0;
- if ((prr_product != PRR_PRODUCT_M3N) &&
- (prr_product != PRR_PRODUCT_V3H)) {
- mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
- dsb_sev();
-
- while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) {
- dsb_sev();
- }
- dsb_sev();
-
- for (loop = 0; loop < loop_max; loop++) {
- val = mmio_read_32(DBSC_DBPDRGD(phyno));
- dsb_sev();
- }
- (void)val;
- } else {
- mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00004000);
- dsb_sev();
- while (mmio_read_32(DBSC_DBPDRGA(phyno)) !=
- (regadd | 0x0000C000)) {
- dsb_sev();
- };
- val = mmio_read_32(DBSC_DBPDRGA(phyno));
- mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000);
- while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) {
- dsb_sev();
- };
- dsb_sev();
-
- mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000);
- while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) {
- dsb_sev();
- };
-
- dsb_sev();
- val = mmio_read_32(DBSC_DBPDRGD(phyno));
- dsb_sev();
- (void)val;
- }
- return val;
-}
-
-static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata)
-{
- uint32_t val;
- uint32_t loop;
-
- if ((prr_product != PRR_PRODUCT_M3N) &&
- (prr_product != PRR_PRODUCT_V3H)) {
- mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
- dsb_sev();
- for (loop = 0; loop < loop_max; loop++) {
- val = mmio_read_32(DBSC_DBPDRGA(phyno));
- dsb_sev();
- }
- mmio_write_32(DBSC_DBPDRGD(phyno), regdata);
- dsb_sev();
-
- for (loop = 0; loop < loop_max; loop++) {
- val = mmio_read_32(DBSC_DBPDRGD(phyno));
- dsb_sev();
- }
- } else {
- mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
- dsb_sev();
-
- while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) {
- dsb_sev();
- };
- dsb_sev();
-
- mmio_write_32(DBSC_DBPDRGD(phyno), regdata);
- dsb_sev();
-
- while (mmio_read_32(DBSC_DBPDRGA(phyno)) !=
- (regadd | 0x00008000)) {
- dsb_sev();
- };
- mmio_write_32(DBSC_DBPDRGA(phyno), regadd | 0x00008000);
-
- while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) {
- dsb_sev();
- };
- dsb_sev();
-
- mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
- }
- (void)val;
-}
-
-static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata)
-{
- uint32_t ch;
- uint32_t val;
- uint32_t loop;
-
- if ((prr_product != PRR_PRODUCT_M3N) &&
- (prr_product != PRR_PRODUCT_V3H)) {
- foreach_vch(ch) {
- mmio_write_32(DBSC_DBPDRGA(ch), regadd);
- dsb_sev();
- }
-
- foreach_vch(ch) {
- mmio_write_32(DBSC_DBPDRGD(ch), regdata);
- dsb_sev();
- }
-
- for (loop = 0; loop < loop_max; loop++) {
- val = mmio_read_32(DBSC_DBPDRGD(0));
- dsb_sev();
- }
- (void)val;
- } else {
- foreach_vch(ch) {
- reg_ddrphy_write(ch, regadd, regdata);
- dsb_sev();
- }
- }
-}
-
-static inline void ddrphy_regif_idle(void)
-{
- uint32_t val;
-
- val = reg_ddrphy_read(0, ddr_regdef_adr(_reg_PI_INT_STATUS));
- dsb_sev();
- (void)val;
-}
-
-/* DDRPHY register access (field modify) */
-static inline uint32_t ddr_regdef(uint32_t _regdef)
-{
- return p_ddr_regdef_tbl[_regdef];
-}
-
-static inline uint32_t ddr_regdef_adr(uint32_t _regdef)
-{
- return DDR_REGDEF_ADR(p_ddr_regdef_tbl[_regdef]);
-}
-
-static inline uint32_t ddr_regdef_lsb(uint32_t _regdef)
-{
- return DDR_REGDEF_LSB(p_ddr_regdef_tbl[_regdef]);
-}
-
-static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
- uint32_t val)
-{
- uint32_t adr;
- uint32_t lsb;
- uint32_t len;
- uint32_t msk;
- uint32_t tmp;
- uint32_t regdef;
-
- regdef = ddr_regdef(_regdef);
- adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice;
- len = DDR_REGDEF_LEN(regdef);
- lsb = DDR_REGDEF_LSB(regdef);
- if (len == 0x20)
- msk = 0xffffffff;
- else
- msk = ((1U << len) - 1) << lsb;
-
- tmp = reg_ddrphy_read(ch, adr);
- tmp = (tmp & (~msk)) | ((val << lsb) & msk);
- reg_ddrphy_write(ch, adr, tmp);
-}
-
-static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef)
-{
- uint32_t adr;
- uint32_t lsb;
- uint32_t len;
- uint32_t msk;
- uint32_t tmp;
- uint32_t regdef;
-
- regdef = ddr_regdef(_regdef);
- adr = DDR_REGDEF_ADR(regdef) + 0x80 * slice;
- len = DDR_REGDEF_LEN(regdef);
- lsb = DDR_REGDEF_LSB(regdef);
- if (len == 0x20)
- msk = 0xffffffff;
- else
- msk = ((1U << len) - 1);
-
- tmp = reg_ddrphy_read(ch, adr);
- tmp = (tmp >> lsb) & msk;
-
- return tmp;
-}
-
-static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val)
-{
- ddr_setval_s(ch, 0, regdef, val);
-}
-
-static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val)
-{
- uint32_t ch;
-
- foreach_vch(ch)
- ddr_setval_s(ch, slice, regdef, val);
-}
-
-static void ddr_setval_ach(uint32_t regdef, uint32_t val)
-{
- ddr_setval_ach_s(0, regdef, val);
-}
-
-static void ddr_setval_ach_as(uint32_t regdef, uint32_t val)
-{
- uint32_t slice;
-
- for (slice = 0; slice < SLICE_CNT; slice++)
- ddr_setval_ach_s(slice, regdef, val);
-}
-
-static uint32_t ddr_getval(uint32_t ch, uint32_t regdef)
-{
- return ddr_getval_s(ch, 0, regdef);
-}
-
-static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p)
-{
- uint32_t ch;
-
- foreach_vch(ch)
- p[ch] = ddr_getval_s(ch, 0, regdef);
- return p[0];
-}
-
-static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p)
-{
- uint32_t ch, slice;
- uint32_t *pp;
-
- pp = p;
- foreach_vch(ch)
- for (slice = 0; slice < SLICE_CNT; slice++)
- *pp++ = ddr_getval_s(ch, slice, regdef);
- return p[0];
-}
-
-/* handling functions for setteing ddrphy value table */
-static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size)
-{
- uint32_t i;
-
- for (i = 0; i < size; i++) {
- to[i] = from[i];
- }
-}
-
-static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val)
-{
- uint32_t adr;
- uint32_t lsb;
- uint32_t len;
- uint32_t msk;
- uint32_t tmp;
- uint32_t adrmsk;
- uint32_t regdef;
-
- regdef = ddr_regdef(_regdef);
- adr = DDR_REGDEF_ADR(regdef);
- len = DDR_REGDEF_LEN(regdef);
- lsb = DDR_REGDEF_LSB(regdef);
- if (len == 0x20)
- msk = 0xffffffff;
- else
- msk = ((1U << len) - 1) << lsb;
-
- if (adr < 0x400) {
- adrmsk = 0xff;
- } else {
- adrmsk = 0x7f;
- }
-
- tmp = tbl[adr & adrmsk];
- tmp = (tmp & (~msk)) | ((val << lsb) & msk);
- tbl[adr & adrmsk] = tmp;
-}
-
-static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef)
-{
- uint32_t adr;
- uint32_t lsb;
- uint32_t len;
- uint32_t msk;
- uint32_t tmp;
- uint32_t adrmsk;
- uint32_t regdef;
-
- regdef = ddr_regdef(_regdef);
- adr = DDR_REGDEF_ADR(regdef);
- len = DDR_REGDEF_LEN(regdef);
- lsb = DDR_REGDEF_LSB(regdef);
- if (len == 0x20)
- msk = 0xffffffff;
- else
- msk = ((1U << len) - 1);
-
- if (adr < 0x400) {
- adrmsk = 0xff;
- } else {
- adrmsk = 0x7f;
- }
-
- tmp = tbl[adr & adrmsk];
- tmp = (tmp >> lsb) & msk;
-
- return tmp;
-}
-
-/* DDRPHY register access handling */
-static uint32_t ddrphy_regif_chk(void)
-{
- uint32_t tmp_ach[DRAM_CH_CNT];
- uint32_t ch;
- uint32_t err;
- uint32_t PI_VERSION_CODE;
-
- if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) ||
- (prr_product == PRR_PRODUCT_M3)) {
- PI_VERSION_CODE = 0x2041; /* H3 Ver.1.x/M3-W */
- } else {
- PI_VERSION_CODE = 0x2040; /* H3 Ver.2.0 or later/M3-N/V3H */
- }
-
- ddr_getval_ach(_reg_PI_VERSION, (uint32_t *)tmp_ach);
- err = 0;
- foreach_vch(ch) {
- if (tmp_ach[ch] != PI_VERSION_CODE)
- err = 1;
- }
- return err;
-}
-
-/* functions and parameters for timing setting */
-struct _jedec_spec1 {
- uint16_t fx3;
- uint8_t rlwodbi;
- uint8_t rlwdbi;
- uint8_t WL;
- uint8_t nwr;
- uint8_t nrtp;
- uint8_t odtlon;
- uint8_t MR1;
- uint8_t MR2;
-};
-
-#define JS1_USABLEC_SPEC_LO 2
-#define JS1_USABLEC_SPEC_HI 5
-#define JS1_FREQ_TBL_NUM 8
-#define JS1_MR1(f) (0x04 | ((f) << 4))
-#define JS1_MR2(f) (0x00 | ((f) << 3) | (f))
-const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = {
- /* 533.333Mbps */
- { 800, 6, 6, 4, 6, 8, 0, JS1_MR1(0), JS1_MR2(0) | 0x40 },
- /* 1066.666Mbps */
- { 1600, 10, 12, 8, 10, 8, 0, JS1_MR1(1), JS1_MR2(1) | 0x40 },
- /* 1600.000Mbps */
- { 2400, 14, 16, 12, 16, 8, 6, JS1_MR1(2), JS1_MR2(2) | 0x40 },
- /* 2133.333Mbps */
- { 3200, 20, 22, 10, 20, 8, 4, JS1_MR1(3), JS1_MR2(3) },
- /* 2666.666Mbps */
- { 4000, 24, 28, 12, 24, 10, 4, JS1_MR1(4), JS1_MR2(4) },
- /* 3200.000Mbps */
- { 4800, 28, 32, 14, 30, 12, 6, JS1_MR1(5), JS1_MR2(5) },
- /* 3733.333Mbps */
- { 5600, 32, 36, 16, 34, 14, 6, JS1_MR1(6), JS1_MR2(6) },
- /* 4266.666Mbps */
- { 6400, 36, 40, 18, 40, 16, 8, JS1_MR1(7), JS1_MR2(7) }
-};
-
-struct _jedec_spec2 {
- uint16_t ps;
- uint16_t cyc;
-};
-
-#define js2_tsr 0
-#define js2_txp 1
-#define js2_trtp 2
-#define js2_trcd 3
-#define js2_trppb 4
-#define js2_trpab 5
-#define js2_tras 6
-#define js2_twr 7
-#define js2_twtr 8
-#define js2_trrd 9
-#define js2_tppd 10
-#define js2_tfaw 11
-#define js2_tdqsck 12
-#define js2_tckehcmd 13
-#define js2_tckelcmd 14
-#define js2_tckelpd 15
-#define js2_tmrr 16
-#define js2_tmrw 17
-#define js2_tmrd 18
-#define js2_tzqcalns 19
-#define js2_tzqlat 20
-#define js2_tiedly 21
-#define js2_tODTon_min 22
-#define JS2_TBLCNT 23
-
-#define js2_trcpb (JS2_TBLCNT)
-#define js2_trcab (JS2_TBLCNT + 1)
-#define js2_trfcab (JS2_TBLCNT + 2)
-#define JS2_CNT (JS2_TBLCNT + 3)
-
-#ifndef JS2_DERATE
-#define JS2_DERATE 0
-#endif
-const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = {
- {
-/*tSR */ {15000, 3},
-/*tXP */ {7500, 3},
-/*tRTP */ {7500, 8},
-/*tRCD */ {18000, 4},
-/*tRPpb */ {18000, 3},
-/*tRPab */ {21000, 3},
-/*tRAS */ {42000, 3},
-/*tWR */ {18000, 4},
-/*tWTR */ {10000, 8},
-/*tRRD */ {10000, 4},
-/*tPPD */ {0, 0},
-/*tFAW */ {40000, 0},
-/*tDQSCK*/ {3500, 0},
-/*tCKEHCMD*/ {7500, 3},
-/*tCKELCMD*/ {7500, 3},
-/*tCKELPD*/ {7500, 3},
-/*tMRR*/ {0, 8},
-/*tMRW*/ {10000, 10},
-/*tMRD*/ {14000, 10},
-/*tZQCALns*/ {1000 * 10, 0},
-/*tZQLAT*/ {30000, 10},
-/*tIEdly*/ {12500, 0},
-/*tODTon_min*/ {1500, 0}
- }, {
-/*tSR */ {15000, 3},
-/*tXP */ {7500, 3},
-/*tRTP */ {7500, 8},
-/*tRCD */ {19875, 4},
-/*tRPpb */ {19875, 3},
-/*tRPab */ {22875, 3},
-/*tRAS */ {43875, 3},
-/*tWR */ {18000, 4},
-/*tWTR */ {10000, 8},
-/*tRRD */ {11875, 4},
-/*tPPD */ {0, 0},
-/*tFAW */ {40000, 0},
-/*tDQSCK*/ {3600, 0},
-/*tCKEHCMD*/ {7500, 3},
-/*tCKELCMD*/ {7500, 3},
-/*tCKELPD*/ {7500, 3},
-/*tMRR*/ {0, 8},
-/*tMRW*/ {10000, 10},
-/*tMRD*/ {14000, 10},
-/*tZQCALns*/ {1000 * 10, 0},
-/*tZQLAT*/ {30000, 10},
-/*tIEdly*/ {12500, 0},
-/*tODTon_min*/ {1500, 0}
- }
-};
-
-const uint16_t jedec_spec2_trfc_ab[7] = {
-/* 4Gb, 6Gb, 8Gb,12Gb, 16Gb, 24Gb(non), 32Gb(non) */
- 130, 180, 180, 280, 280, 560, 560
-};
-
-static uint32_t js1_ind;
-static uint16_t js2[JS2_CNT];
-static uint8_t RL;
-static uint8_t WL;
-
-static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps,
- uint16_t cyc)
-{
- uint32_t tmp;
- uint32_t div;
-
- tmp = (((uint32_t)(ps) + 9) / 10) * _ddr_mbps;
- div = tmp / (200000 * _ddr_mbpsdiv);
- if (tmp != (div * 200000 * _ddr_mbpsdiv))
- div = div + 1;
-
- if (div > cyc)
- return (uint16_t)div;
- return cyc;
-}
-
-static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv,
- uint16_t *_js2)
-{
- int i;
-
- for (i = 0; i < JS2_TBLCNT; i++) {
- _js2[i] = _f_scale(_ddr_mbps, _ddr_mbpsdiv,
- 1UL * jedec_spec2[JS2_DERATE][i].ps,
- jedec_spec2[JS2_DERATE][i].cyc);
- }
-
- _js2[js2_trcpb] = _js2[js2_tras] + _js2[js2_trppb];
- _js2[js2_trcab] = _js2[js2_tras] + _js2[js2_trpab];
-}
-
-/* scaler for DELAY value */
-static int16_t _f_scale_adj(int16_t ps)
-{
- int32_t tmp;
- /*
- * tmp = (int32_t)512 * ps * ddr_mbps /2 / ddr_mbpsdiv / 1000 / 1000;
- * = ps * ddr_mbps /2 / ddr_mbpsdiv *512 / 8 / 8 / 125 / 125
- * = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125
- */
- tmp =
- (int32_t)4 * (int32_t)ps * (int32_t)ddr_mbps /
- (int32_t)ddr_mbpsdiv;
- tmp = (int32_t)tmp / (int32_t)15625;
-
- return (int16_t)tmp;
-}
-
-static const uint32_t reg_pi_mr1_data_fx_csx[2][CSAB_CNT] = {
- {
- _reg_PI_MR1_DATA_F0_0,
- _reg_PI_MR1_DATA_F0_1,
- _reg_PI_MR1_DATA_F0_2,
- _reg_PI_MR1_DATA_F0_3},
- {
- _reg_PI_MR1_DATA_F1_0,
- _reg_PI_MR1_DATA_F1_1,
- _reg_PI_MR1_DATA_F1_2,
- _reg_PI_MR1_DATA_F1_3}
-};
-
-static const uint32_t reg_pi_mr2_data_fx_csx[2][CSAB_CNT] = {
- {
- _reg_PI_MR2_DATA_F0_0,
- _reg_PI_MR2_DATA_F0_1,
- _reg_PI_MR2_DATA_F0_2,
- _reg_PI_MR2_DATA_F0_3},
- {
- _reg_PI_MR2_DATA_F1_0,
- _reg_PI_MR2_DATA_F1_1,
- _reg_PI_MR2_DATA_F1_2,
- _reg_PI_MR2_DATA_F1_3}
-};
-
-static const uint32_t reg_pi_mr3_data_fx_csx[2][CSAB_CNT] = {
- {
- _reg_PI_MR3_DATA_F0_0,
- _reg_PI_MR3_DATA_F0_1,
- _reg_PI_MR3_DATA_F0_2,
- _reg_PI_MR3_DATA_F0_3},
- {
- _reg_PI_MR3_DATA_F1_0,
- _reg_PI_MR3_DATA_F1_1,
- _reg_PI_MR3_DATA_F1_2,
- _reg_PI_MR3_DATA_F1_3}
-};
-
-const uint32_t reg_pi_mr11_data_fx_csx[2][CSAB_CNT] = {
- {
- _reg_PI_MR11_DATA_F0_0,
- _reg_PI_MR11_DATA_F0_1,
- _reg_PI_MR11_DATA_F0_2,
- _reg_PI_MR11_DATA_F0_3},
- {
- _reg_PI_MR11_DATA_F1_0,
- _reg_PI_MR11_DATA_F1_1,
- _reg_PI_MR11_DATA_F1_2,
- _reg_PI_MR11_DATA_F1_3}
-};
-
-const uint32_t reg_pi_mr12_data_fx_csx[2][CSAB_CNT] = {
- {
- _reg_PI_MR12_DATA_F0_0,
- _reg_PI_MR12_DATA_F0_1,
- _reg_PI_MR12_DATA_F0_2,
- _reg_PI_MR12_DATA_F0_3},
- {
- _reg_PI_MR12_DATA_F1_0,
- _reg_PI_MR12_DATA_F1_1,
- _reg_PI_MR12_DATA_F1_2,
- _reg_PI_MR12_DATA_F1_3}
-};
-
-const uint32_t reg_pi_mr14_data_fx_csx[2][CSAB_CNT] = {
- {
- _reg_PI_MR14_DATA_F0_0,
- _reg_PI_MR14_DATA_F0_1,
- _reg_PI_MR14_DATA_F0_2,
- _reg_PI_MR14_DATA_F0_3},
- {
- _reg_PI_MR14_DATA_F1_0,
- _reg_PI_MR14_DATA_F1_1,
- _reg_PI_MR14_DATA_F1_2,
- _reg_PI_MR14_DATA_F1_3}
-};
-
-/*
- * regif pll w/a ( REGIF H3 Ver.2.0 or later/M3-N/V3H WA )
- */
-static void regif_pll_wa(void)
-{
- uint32_t ch;
-
- if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
- // PLL setting for PHY : H3 Ver.1.x
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT),
- (0x0064U <<
- ddr_regdef_lsb(_reg_PHY_PLL_WAIT)));
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL),
- ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_PLL_CTRL));
-
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL),
- ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_LP4_BOOT_PLL_CTRL));
-
- } else {
- /* PLL setting for PHY : M3-W/M3-N/V3H/H3 Ver.2.0 or later */
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT),
- (0x5064U <<
- ddr_regdef_lsb(_reg_PHY_PLL_WAIT)));
-
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL),
- (ddrtbl_getval
- (_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_PLL_CTRL_TOP) << 16) |
- ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_PLL_CTRL));
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA),
- ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_PLL_CTRL_CA));
-
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL),
- (ddrtbl_getval
- (_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_LP4_BOOT_PLL_CTRL_CA) << 16) |
- ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_LP4_BOOT_PLL_CTRL));
- reg_ddrphy_write_a(ddr_regdef_adr
- (_reg_PHY_LP4_BOOT_TOP_PLL_CTRL),
- ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_LP4_BOOT_TOP_PLL_CTRL
- ));
- }
-
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS),
- _cnf_DDR_PHY_ADR_G_REGSET
- [ddr_regdef_adr(_reg_PHY_LPDDR3_CS) -
- DDR_PHY_ADR_G_REGSET_OFS]);
-
- /* protect register interface */
- ddrphy_regif_idle();
- pll3_control(0);
-
- if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
- /* non */
- } else {
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_DLL_RST_EN),
- (0x01U <<
- ddr_regdef_lsb(_reg_PHY_DLL_RST_EN)));
- ddrphy_regif_idle();
- }
-
- /* init start */
- /* dbdficnt0:
- * dfi_dram_clk_disable=1
- * dfi_frequency = 0
- * freq_ratio = 01 (2:1)
- * init_start =0
- */
- foreach_vch(ch)
- mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10);
- dsb_sev();
-
- /* dbdficnt0:
- * dfi_dram_clk_disable=1
- * dfi_frequency = 0
- * freq_ratio = 01 (2:1)
- * init_start =1
- */
- foreach_vch(ch)
- mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11);
- dsb_sev();
-
- foreach_ech(ch)
- if ((board_cnf->phyvalid) & BIT(ch))
- while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1f) != 0x1f)
- ;
- dsb_sev();
-}
-
-/* load table data into DDR registers */
-static void ddrtbl_load(void)
-{
- uint32_t i;
- uint32_t slice;
- uint32_t csab;
- uint32_t adr;
- uint32_t data_l;
- uint32_t tmp[3];
- uint16_t dataS;
-
- /* TIMING REGISTERS */
- /* search jedec_spec1 index */
- for (i = JS1_USABLEC_SPEC_LO; i < JS1_FREQ_TBL_NUM - 1; i++) {
- if (js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U)
- break;
- }
- if (i > JS1_USABLEC_SPEC_HI)
- js1_ind = JS1_USABLEC_SPEC_HI;
- else
- js1_ind = i;
-
- if (board_cnf->dbi_en)
- RL = js1[js1_ind].rlwdbi;
- else
- RL = js1[js1_ind].rlwodbi;
-
- WL = js1[js1_ind].WL;
-
- /* calculate jedec_spec2 */
- _f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2);
-
- /* PREPARE TBL */
- if (prr_product == PRR_PRODUCT_H3) {
- if (prr_cut <= PRR_PRODUCT_11) {
- /* H3 Ver.1.x */
- _tblcopy(_cnf_DDR_PHY_SLICE_REGSET,
- DDR_PHY_SLICE_REGSET_H3,
- DDR_PHY_SLICE_REGSET_NUM_H3);
- _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET,
- DDR_PHY_ADR_V_REGSET_H3,
- DDR_PHY_ADR_V_REGSET_NUM_H3);
- _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET,
- DDR_PHY_ADR_I_REGSET_H3,
- DDR_PHY_ADR_I_REGSET_NUM_H3);
- _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET,
- DDR_PHY_ADR_G_REGSET_H3,
- DDR_PHY_ADR_G_REGSET_NUM_H3);
- _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_H3,
- DDR_PI_REGSET_NUM_H3);
-
- DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_H3;
- DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_H3;
- DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_H3;
- DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_H3;
- DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_H3;
- DDR_PHY_SLICE_REGSET_SIZE =
- DDR_PHY_SLICE_REGSET_SIZE_H3;
- DDR_PHY_ADR_V_REGSET_SIZE =
- DDR_PHY_ADR_V_REGSET_SIZE_H3;
- DDR_PHY_ADR_I_REGSET_SIZE =
- DDR_PHY_ADR_I_REGSET_SIZE_H3;
- DDR_PHY_ADR_G_REGSET_SIZE =
- DDR_PHY_ADR_G_REGSET_SIZE_H3;
- DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_H3;
- DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_H3;
- DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_H3;
- DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_H3;
- DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_H3;
- DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_H3;
-
- DDR_PHY_ADR_I_NUM = 1;
- } else {
- /* H3 Ver.2.0 or later */
- _tblcopy(_cnf_DDR_PHY_SLICE_REGSET,
- DDR_PHY_SLICE_REGSET_H3VER2,
- DDR_PHY_SLICE_REGSET_NUM_H3VER2);
- _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET,
- DDR_PHY_ADR_V_REGSET_H3VER2,
- DDR_PHY_ADR_V_REGSET_NUM_H3VER2);
- _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET,
- DDR_PHY_ADR_G_REGSET_H3VER2,
- DDR_PHY_ADR_G_REGSET_NUM_H3VER2);
- _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_H3VER2,
- DDR_PI_REGSET_NUM_H3VER2);
-
- DDR_PHY_SLICE_REGSET_OFS =
- DDR_PHY_SLICE_REGSET_OFS_H3VER2;
- DDR_PHY_ADR_V_REGSET_OFS =
- DDR_PHY_ADR_V_REGSET_OFS_H3VER2;
- DDR_PHY_ADR_G_REGSET_OFS =
- DDR_PHY_ADR_G_REGSET_OFS_H3VER2;
- DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_H3VER2;
- DDR_PHY_SLICE_REGSET_SIZE =
- DDR_PHY_SLICE_REGSET_SIZE_H3VER2;
- DDR_PHY_ADR_V_REGSET_SIZE =
- DDR_PHY_ADR_V_REGSET_SIZE_H3VER2;
- DDR_PHY_ADR_G_REGSET_SIZE =
- DDR_PHY_ADR_G_REGSET_SIZE_H3VER2;
- DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_H3VER2;
- DDR_PHY_SLICE_REGSET_NUM =
- DDR_PHY_SLICE_REGSET_NUM_H3VER2;
- DDR_PHY_ADR_V_REGSET_NUM =
- DDR_PHY_ADR_V_REGSET_NUM_H3VER2;
- DDR_PHY_ADR_G_REGSET_NUM =
- DDR_PHY_ADR_G_REGSET_NUM_H3VER2;
- DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_H3VER2;
-
- DDR_PHY_ADR_I_NUM = 0;
- }
- } else if (prr_product == PRR_PRODUCT_M3) {
- /* M3-W */
- _tblcopy(_cnf_DDR_PHY_SLICE_REGSET,
- DDR_PHY_SLICE_REGSET_M3, DDR_PHY_SLICE_REGSET_NUM_M3);
- _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET,
- DDR_PHY_ADR_V_REGSET_M3, DDR_PHY_ADR_V_REGSET_NUM_M3);
- _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET,
- DDR_PHY_ADR_I_REGSET_M3, DDR_PHY_ADR_I_REGSET_NUM_M3);
- _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET,
- DDR_PHY_ADR_G_REGSET_M3, DDR_PHY_ADR_G_REGSET_NUM_M3);
- _tblcopy(_cnf_DDR_PI_REGSET,
- DDR_PI_REGSET_M3, DDR_PI_REGSET_NUM_M3);
-
- DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_M3;
- DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_M3;
- DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_M3;
- DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_M3;
- DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_M3;
- DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_M3;
- DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_M3;
- DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_M3;
- DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_M3;
- DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_M3;
- DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_M3;
- DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_M3;
- DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_M3;
- DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_M3;
- DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_M3;
-
- DDR_PHY_ADR_I_NUM = 2;
- } else {
- /* M3-N/V3H */
- _tblcopy(_cnf_DDR_PHY_SLICE_REGSET,
- DDR_PHY_SLICE_REGSET_M3N,
- DDR_PHY_SLICE_REGSET_NUM_M3N);
- _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET, DDR_PHY_ADR_V_REGSET_M3N,
- DDR_PHY_ADR_V_REGSET_NUM_M3N);
- _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET, DDR_PHY_ADR_I_REGSET_M3N,
- DDR_PHY_ADR_I_REGSET_NUM_M3N);
- _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET, DDR_PHY_ADR_G_REGSET_M3N,
- DDR_PHY_ADR_G_REGSET_NUM_M3N);
- _tblcopy(_cnf_DDR_PI_REGSET, DDR_PI_REGSET_M3N,
- DDR_PI_REGSET_NUM_M3N);
-
- DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_M3N;
- DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_M3N;
- DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_M3N;
- DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_M3N;
- DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_M3N;
- DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_M3N;
- DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_M3N;
- DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_M3N;
- DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_M3N;
- DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_M3N;
- DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_M3N;
- DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_M3N;
- DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_M3N;
- DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_M3N;
- DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_M3N;
-
- DDR_PHY_ADR_I_NUM = 2;
- }
-
- /* PLL CODE CHANGE */
- if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) {
- ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, _reg_PHY_PLL_CTRL,
- 0x1142);
- ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_LP4_BOOT_PLL_CTRL, 0x1142);
- }
-
- /* on fly gate adjust */
- if ((prr_product == PRR_PRODUCT_M3) && (prr_cut == PRR_PRODUCT_10)) {
- ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_ON_FLY_GATE_ADJUST_EN, 0x00);
- }
-
- /* Adjust PI parameters */
-#ifdef _def_LPDDR4_ODT
- for (i = 0; i < 2; i++) {
- for (csab = 0; csab < CSAB_CNT; csab++) {
- ddrtbl_setval(_cnf_DDR_PI_REGSET,
- reg_pi_mr11_data_fx_csx[i][csab],
- _def_LPDDR4_ODT);
- }
- }
-#endif /* _def_LPDDR4_ODT */
-
-#ifdef _def_LPDDR4_VREFCA
- for (i = 0; i < 2; i++) {
- for (csab = 0; csab < CSAB_CNT; csab++) {
- ddrtbl_setval(_cnf_DDR_PI_REGSET,
- reg_pi_mr12_data_fx_csx[i][csab],
- _def_LPDDR4_VREFCA);
- }
- }
-#endif /* _def_LPDDR4_VREFCA */
- if ((prr_product == PRR_PRODUCT_M3N) ||
- (prr_product == PRR_PRODUCT_V3H)) {
- js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7U;
- if (js2[js2_tiedly] > (RL))
- js2[js2_tiedly] = RL;
- } else if ((prr_product == PRR_PRODUCT_H3) &&
- (prr_cut > PRR_PRODUCT_11)) {
- js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4U;
- } else if ((prr_product == PRR_PRODUCT_H3) &&
- (prr_cut <= PRR_PRODUCT_11)) {
- js2[js2_tiedly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0);
- }
-
- if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) ||
- (prr_product == PRR_PRODUCT_M3N) ||
- (prr_product == PRR_PRODUCT_V3H)) {
- if ((js2[js2_tiedly]) >= 0x1e)
- dataS = 0x1e;
- else
- dataS = js2[js2_tiedly];
- } else {
- if ((js2[js2_tiedly]) >= 0x0e)
- dataS = 0x0e;
- else
- dataS = js2[js2_tiedly];
- }
-
- ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataS);
- ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY,
- (dataS - 2));
- if ((prr_product == PRR_PRODUCT_M3N) ||
- (prr_product == PRR_PRODUCT_V3H)) {
- ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_PHY_RDDATA_EN_OE_DLY, dataS - 2);
- }
- ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1, RL - dataS);
-
- if (ddrtbl_getval
- (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD)) {
- data_l = WL - 1;
- } else {
- data_l = WL;
- }
- ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, data_l - 2);
- ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, data_l);
-
- if (board_cnf->dbi_en) {
- ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE,
- 0x01);
- ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_PHY_WDQLVL_DATADM_MASK, 0x000);
- } else {
- ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE,
- 0x00);
- ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_PHY_WDQLVL_DATADM_MASK, 0x100);
- }
-
- tmp[0] = js1[js1_ind].MR1;
- tmp[1] = js1[js1_ind].MR2;
- data_l = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0);
- if (board_cnf->dbi_en)
- tmp[2] = data_l | 0xc0;
- else
- tmp[2] = data_l & (~0xc0);
-
- for (i = 0; i < 2; i++) {
- for (csab = 0; csab < CSAB_CNT; csab++) {
- ddrtbl_setval(_cnf_DDR_PI_REGSET,
- reg_pi_mr1_data_fx_csx[i][csab], tmp[0]);
- ddrtbl_setval(_cnf_DDR_PI_REGSET,
- reg_pi_mr2_data_fx_csx[i][csab], tmp[1]);
- ddrtbl_setval(_cnf_DDR_PI_REGSET,
- reg_pi_mr3_data_fx_csx[i][csab], tmp[2]);
- }
- }
-
- /* DDRPHY INT START */
- if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
- /* non */
- } else {
- regif_pll_wa();
- dbwait_loop(5);
- }
-
- /* FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) */
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
- BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
- ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01);
-
- /* SET DATA SLICE TABLE */
- for (slice = 0; slice < SLICE_CNT; slice++) {
- adr =
- DDR_PHY_SLICE_REGSET_OFS +
- DDR_PHY_SLICE_REGSET_SIZE * slice;
- for (i = 0; i < DDR_PHY_SLICE_REGSET_NUM; i++) {
- reg_ddrphy_write_a(adr + i,
- _cnf_DDR_PHY_SLICE_REGSET[i]);
- }
- }
-
- /* SET ADR SLICE TABLE */
- adr = DDR_PHY_ADR_V_REGSET_OFS;
- for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) {
- reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]);
- }
-
- if (((prr_product == PRR_PRODUCT_M3) ||
- (prr_product == PRR_PRODUCT_M3N)) &&
- ((0x00ffffff & (uint32_t)((board_cnf->ch[0].ca_swap) >> 40))
- != 0x00)) {
- adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE;
- for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM; i++) {
- reg_ddrphy_write_a(adr + i,
- _cnf_DDR_PHY_ADR_V_REGSET[i]);
- }
- ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_ADR_DISABLE, 0x02);
- DDR_PHY_ADR_I_NUM -= 1;
- ddr_phycaslice = 1;
-
-#ifndef _def_LPDDR4_ODT
- for (i = 0; i < 2; i++) {
- for (csab = 0; csab < CSAB_CNT; csab++) {
- ddrtbl_setval(_cnf_DDR_PI_REGSET,
- reg_pi_mr11_data_fx_csx[i][csab],
- 0x66);
- }
- }
-#endif/* _def_LPDDR4_ODT */
- } else {
- ddr_phycaslice = 0;
- }
-
- if (DDR_PHY_ADR_I_NUM > 0) {
- for (slice = 0; slice < DDR_PHY_ADR_I_NUM; slice++) {
- adr =
- DDR_PHY_ADR_I_REGSET_OFS +
- DDR_PHY_ADR_I_REGSET_SIZE * slice;
- for (i = 0; i < DDR_PHY_ADR_I_REGSET_NUM; i++) {
- reg_ddrphy_write_a(adr + i,
- _cnf_DDR_PHY_ADR_I_REGSET
- [i]);
- }
- }
- }
-
- /* SET ADRCTRL SLICE TABLE */
- adr = DDR_PHY_ADR_G_REGSET_OFS;
- for (i = 0; i < DDR_PHY_ADR_G_REGSET_NUM; i++) {
- reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_G_REGSET[i]);
- }
-
- /* SET PI REGISTERS */
- adr = DDR_PI_REGSET_OFS;
- for (i = 0; i < DDR_PI_REGSET_NUM; i++) {
- reg_ddrphy_write_a(adr + i, _cnf_DDR_PI_REGSET[i]);
- }
-}
-
-/* CONFIGURE DDR REGISTERS */
-static void ddr_config_sub(void)
-{
- uint32_t i;
- uint32_t ch, slice;
- uint32_t data_l;
- uint32_t tmp;
- uint8_t high_byte[SLICE_CNT];
- const uint32_t _par_CALVL_DEVICE_MAP = 1;
-
- foreach_vch(ch) {
- /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */
- for (slice = 0; slice < SLICE_CNT; slice++) {
- high_byte[slice] =
- (board_cnf->ch[ch].dqs_swap >> (4 * slice)) % 2;
- ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0,
- board_cnf->ch[ch].dq_swap[slice]);
- ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1,
- board_cnf->ch[ch].dm_swap[slice]);
- if (high_byte[slice]) {
- /* HIGHER 16 BYTE */
- ddr_setval_s(ch, slice,
- _reg_PHY_CALVL_VREF_DRIVING_SLICE,
- 0x00);
- } else {
- /* LOWER 16 BYTE */
- ddr_setval_s(ch, slice,
- _reg_PHY_CALVL_VREF_DRIVING_SLICE,
- 0x01);
- }
- }
-
- /* BOARD SETTINGS (CA,ADDR_SEL) */
- data_l = (0x00ffffff & (uint32_t)(board_cnf->ch[ch].ca_swap)) |
- 0x00888888;
-
- /* --- ADR_CALVL_SWIZZLE --- */
- if (prr_product == PRR_PRODUCT_M3) {
- ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, data_l);
- ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0,
- 0x00000000);
- ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, data_l);
- ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1,
- 0x00000000);
- ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP,
- _par_CALVL_DEVICE_MAP);
- } else {
- ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, data_l);
- ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000);
- ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP,
- _par_CALVL_DEVICE_MAP);
- }
-
- /* --- ADR_ADDR_SEL --- */
- if ((prr_product == PRR_PRODUCT_H3) &&
- (prr_cut > PRR_PRODUCT_11)) {
- data_l = 0x00FFFFFF & board_cnf->ch[ch].ca_swap;
- } else {
- data_l = 0;
- tmp = board_cnf->ch[ch].ca_swap;
- for (i = 0; i < 6; i++) {
- data_l |= ((tmp & 0x0f) << (i * 5));
- tmp = tmp >> 4;
- }
- }
- ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, data_l);
- if (ddr_phycaslice == 1) {
- /* ----------- adr slice2 swap ----------- */
- tmp = (uint32_t)((board_cnf->ch[ch].ca_swap) >> 40);
- data_l = (tmp & 0x00ffffff) | 0x00888888;
-
- /* --- ADR_CALVL_SWIZZLE --- */
- if (prr_product == PRR_PRODUCT_M3) {
- ddr_setval_s(ch, 2,
- _reg_PHY_ADR_CALVL_SWIZZLE0_0,
- data_l);
- ddr_setval_s(ch, 2,
- _reg_PHY_ADR_CALVL_SWIZZLE1_0,
- 0x00000000);
- ddr_setval_s(ch, 2,
- _reg_PHY_ADR_CALVL_SWIZZLE0_1,
- data_l);
- ddr_setval_s(ch, 2,
- _reg_PHY_ADR_CALVL_SWIZZLE1_1,
- 0x00000000);
- ddr_setval_s(ch, 2,
- _reg_PHY_ADR_CALVL_DEVICE_MAP,
- _par_CALVL_DEVICE_MAP);
- } else {
- ddr_setval_s(ch, 2,
- _reg_PHY_ADR_CALVL_SWIZZLE0,
- data_l);
- ddr_setval_s(ch, 2,
- _reg_PHY_ADR_CALVL_SWIZZLE1,
- 0x00000000);
- ddr_setval_s(ch, 2,
- _reg_PHY_CALVL_DEVICE_MAP,
- _par_CALVL_DEVICE_MAP);
- }
-
- /* --- ADR_ADDR_SEL --- */
- data_l = 0;
- for (i = 0; i < 6; i++) {
- data_l |= ((tmp & 0x0f) << (i * 5));
- tmp = tmp >> 4;
- }
-
- ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, data_l);
- }
-
- /* BOARD SETTINGS (BYTE_ORDER_SEL) */
- if (prr_product == PRR_PRODUCT_M3) {
- /* --- DATA_BYTE_SWAP --- */
- data_l = 0;
- tmp = board_cnf->ch[ch].dqs_swap;
- for (i = 0; i < 4; i++) {
- data_l |= ((tmp & 0x03) << (i * 2));
- tmp = tmp >> 4;
- }
- } else {
- /* --- DATA_BYTE_SWAP --- */
- data_l = board_cnf->ch[ch].dqs_swap;
- ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 0x01);
- ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0,
- (data_l) & 0x0f);
- ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1,
- (data_l >> 4 * 1) & 0x0f);
- ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE2,
- (data_l >> 4 * 2) & 0x0f);
- ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE3,
- (data_l >> 4 * 3) & 0x0f);
-
- ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH, 0x00);
- }
- ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, data_l);
- }
-}
-
-static void get_ca_swizzle(uint32_t ch, uint32_t ddr_csn, uint32_t *p_swz)
-{
- uint32_t slice;
- uint32_t tmp;
- uint32_t tgt;
-
- if (ddr_csn / 2) {
- tgt = 3;
- } else {
- tgt = 1;
- }
-
- for (slice = 0; slice < SLICE_CNT; slice++) {
- tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
- if (tgt == tmp)
- break;
- }
- tmp = 0x00FFFFFF & board_cnf->ch[ch].ca_swap;
- if (slice % 2)
- tmp |= 0x00888888;
- *p_swz = tmp;
-}
-
-static void ddr_config_sub_h3v1x(void)
-{
- uint32_t ch, slice;
- uint32_t data_l;
- uint32_t tmp;
- uint8_t high_byte[SLICE_CNT];
- uint32_t ca_swizzle;
- uint32_t ca;
- uint32_t csmap;
- uint32_t o_inv;
- uint32_t inv;
- uint32_t bit_soc;
- uint32_t bit_mem;
- uint32_t j;
-
- const uint8_t o_mr15 = 0x55;
- const uint8_t o_mr20 = 0x55;
- const uint16_t o_mr32_mr40 = 0x5a3c;
-
- foreach_vch(ch) {
- /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */
- csmap = 0;
- for (slice = 0; slice < SLICE_CNT; slice++) {
- tmp = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) &
- 0x0f;
- high_byte[slice] = tmp % 2;
- if (tmp == 1 && (slice >= 2))
- csmap |= 0x05;
- if (tmp == 3 && (slice >= 2))
- csmap |= 0x50;
- ddr_setval_s(ch, slice, _reg_PHY_DQ_SWIZZLING,
- board_cnf->ch[ch].dq_swap[slice]);
- if (high_byte[slice]) {
- /* HIGHER 16 BYTE */
- ddr_setval_s(ch, slice,
- _reg_PHY_CALVL_VREF_DRIVING_SLICE,
- 0x00);
- } else {
- /* LOWER 16 BYTE */
- ddr_setval_s(ch, slice,
- _reg_PHY_CALVL_VREF_DRIVING_SLICE,
- 0x01);
- }
- }
- /* BOARD SETTINGS (CA,ADDR_SEL) */
- ca = 0x00FFFFFF & board_cnf->ch[ch].ca_swap;
- ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, ca);
- ddr_setval(ch, _reg_PHY_CALVL_CS_MAP, csmap);
-
- get_ca_swizzle(ch, 0, &ca_swizzle);
-
- ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, ca_swizzle);
- ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0, 0x00000000);
- ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, 0x00000000);
- ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1, 0x00000000);
- ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, 0x01);
-
- for (slice = 0; slice < SLICE_CNT; slice++) {
- ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_NUM,
- 0x01);
- ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_START,
- 0x08);
-
- if (high_byte[slice])
- o_inv = o_mr20;
- else
- o_inv = o_mr15;
-
- tmp = board_cnf->ch[ch].dq_swap[slice];
- inv = 0;
- j = 0;
- for (bit_soc = 0; bit_soc < 8; bit_soc++) {
- bit_mem = (tmp >> (4 * bit_soc)) & 0x0f;
- j |= (1U << bit_mem);
- if (o_inv & (1U << bit_mem))
- inv |= (1U << bit_soc);
- }
- data_l = o_mr32_mr40;
- if (!high_byte[slice])
- data_l |= (inv << 24);
- if (high_byte[slice])
- data_l |= (inv << 16);
- ddr_setval_s(ch, slice, _reg_PHY_LP4_RDLVL_PATT8,
- data_l);
- }
- }
-}
-
-static void ddr_config(void)
-{
- int32_t i;
- uint32_t ch, slice;
- uint32_t data_l;
- uint32_t tmp;
- int8_t _adj;
- int16_t adj;
- uint32_t dq;
- union {
- uint32_t ui32[4];
- uint8_t ui8[16];
- } patt;
- uint16_t patm;
-
- /* configure ddrphy registers */
- if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
- ddr_config_sub_h3v1x();
- } else { /* H3 Ver.2.0 or later/M3-N/V3H is same as M3-W */
- ddr_config_sub();
- }
-
- /* WDQ_USER_PATT */
- foreach_vch(ch) {
- for (slice = 0; slice < SLICE_CNT; slice++) {
- patm = 0;
- for (i = 0; i < 16; i++) {
- tmp = board_cnf->ch[ch].wdqlvl_patt[i];
- patt.ui8[i] = tmp & 0xff;
- if (tmp & 0x100)
- patm |= (1U << i);
- }
- ddr_setval_s(ch, slice, _reg_PHY_USER_PATT0,
- patt.ui32[0]);
- ddr_setval_s(ch, slice, _reg_PHY_USER_PATT1,
- patt.ui32[1]);
- ddr_setval_s(ch, slice, _reg_PHY_USER_PATT2,
- patt.ui32[2]);
- ddr_setval_s(ch, slice, _reg_PHY_USER_PATT3,
- patt.ui32[3]);
- ddr_setval_s(ch, slice, _reg_PHY_USER_PATT4, patm);
- }
- }
-
- /* CACS DLY */
- data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj);
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
- 0x00U);
- foreach_vch(ch) {
- for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4; i++) {
- adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
- ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET,
- _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
- data_l + adj);
- reg_ddrphy_write(ch,
- ddr_regdef_adr
- (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]),
- _cnf_DDR_PHY_ADR_V_REGSET
- [ddr_regdef_adr
- (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
- DDR_PHY_ADR_V_REGSET_OFS]);
- }
-
- for (i = (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4);
- i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
- adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
- ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
- data_l + adj);
- reg_ddrphy_write(ch,
- ddr_regdef_adr
- (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]),
- _cnf_DDR_PHY_ADR_G_REGSET
- [ddr_regdef_adr
- (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
- DDR_PHY_ADR_G_REGSET_OFS]);
- }
-
- if (ddr_phycaslice == 1) {
- for (i = 0; i < 6; i++) {
- adj = _f_scale_adj
- (board_cnf->ch[ch].cacs_adj
- [i +
- _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]);
- ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET,
- _reg_PHY_CLK_CACS_SLAVE_DELAY_X
- [i],
- data_l + adj);
- reg_ddrphy_write(ch,
- ddr_regdef_adr
- (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) +
- 0x0100,
- _cnf_DDR_PHY_ADR_V_REGSET
- [ddr_regdef_adr
- (_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
- DDR_PHY_ADR_V_REGSET_OFS]);
- }
- }
- }
-
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
- BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
-
- /* WDQDM DLY */
- data_l = board_cnf->dqdm_dly_w;
- foreach_vch(ch) {
- for (slice = 0; slice < SLICE_CNT; slice++) {
- for (i = 0; i <= 8; i++) {
- dq = slice * 8 + i;
- if (i == 8)
- _adj = board_cnf->ch[ch].dm_adj_w[slice];
- else
- _adj = board_cnf->ch[ch].dq_adj_w[dq];
- adj = _f_scale_adj(_adj);
- ddr_setval_s(ch, slice,
- _reg_PHY_CLK_WRX_SLAVE_DELAY[i],
- data_l + adj);
- }
- }
- }
-
- /* RDQDM DLY */
- data_l = board_cnf->dqdm_dly_r;
- foreach_vch(ch) {
- for (slice = 0; slice < SLICE_CNT; slice++) {
- for (i = 0; i <= 8; i++) {
- dq = slice * 8 + i;
- if (i == 8)
- _adj = board_cnf->ch[ch].dm_adj_r[slice];
- else
- _adj = board_cnf->ch[ch].dq_adj_r[dq];
- adj = _f_scale_adj(_adj);
- ddr_setval_s(ch, slice,
- _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY
- [i], data_l + adj);
- ddr_setval_s(ch, slice,
- _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY
- [i], data_l + adj);
- }
- }
- }
-}
-
-/* DBSC register setting functions */
-static void dbsc_regset_pre(void)
-{
- uint32_t ch, csab;
- uint32_t data_l;
-
- /* PRIMARY SETTINGS */
- /* LPDDR4, BL=16, DFI interface */
- mmio_write_32(DBSC_DBKIND, 0x0000000a);
- mmio_write_32(DBSC_DBBL, 0x00000002);
- mmio_write_32(DBSC_DBPHYCONF0, 0x00000001);
-
- /* FREQRATIO=2 */
- mmio_write_32(DBSC_DBSYSCONF1, 0x00000002);
-
- /* Chanel map (H3 Ver.1.x) */
- if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11))
- mmio_write_32(DBSC_DBSCHCNT1, 0x00001010);
-
- /* DRAM SIZE REGISTER:
- * set all ranks as density=0(4Gb) for PHY initialization
- */
- foreach_vch(ch) {
- for (csab = 0; csab < 4; csab++) {
- mmio_write_32(DBSC_DBMEMCONF(ch, csab),
- DBMEMCONF_REGD(0));
- }
- }
-
- if (prr_product == PRR_PRODUCT_M3) {
- data_l = 0xe4e4e4e4;
- foreach_ech(ch) {
- if ((ddr_phyvalid & (1U << ch)))
- data_l = (data_l & (~(0x000000FF << (ch * 8))))
- | (((board_cnf->ch[ch].dqs_swap & 0x0003)
- | ((board_cnf->ch[ch].dqs_swap & 0x0030)
- >> 2)
- | ((board_cnf->ch[ch].dqs_swap & 0x0300)
- >> 4)
- | ((board_cnf->ch[ch].dqs_swap & 0x3000)
- >> 6)) << (ch * 8));
- }
- mmio_write_32(DBSC_DBBSWAP, data_l);
- }
-}
-
-static void dbsc_regset(void)
-{
- int32_t i;
- uint32_t ch;
- uint32_t data_l;
- uint32_t data_l2;
- uint32_t tmp[4];
-
- /* RFC */
- if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_20) &&
- (max_density == 0)) {
- js2[js2_trfcab] =
- _f_scale(ddr_mbps, ddr_mbpsdiv,
- 1UL * jedec_spec2_trfc_ab[1] * 1000, 0);
- } else {
- js2[js2_trfcab] =
- _f_scale(ddr_mbps, ddr_mbpsdiv,
- 1UL * jedec_spec2_trfc_ab[max_density] *
- 1000, 0);
- }
-
- /* DBTR0.CL : RL */
- mmio_write_32(DBSC_DBTR(0), RL);
-
- /* DBTR1.CWL : WL */
- mmio_write_32(DBSC_DBTR(1), WL);
-
- /* DBTR2.AL : 0 */
- mmio_write_32(DBSC_DBTR(2), 0);
-
- /* DBTR3.TRCD: tRCD */
- mmio_write_32(DBSC_DBTR(3), js2[js2_trcd]);
-
- /* DBTR4.TRPA,TRP: tRPab,tRPpb */
- mmio_write_32(DBSC_DBTR(4), (js2[js2_trpab] << 16) | js2[js2_trppb]);
-
- /* DBTR5.TRC : use tRCpb */
- mmio_write_32(DBSC_DBTR(5), js2[js2_trcpb]);
-
- /* DBTR6.TRAS : tRAS */
- mmio_write_32(DBSC_DBTR(6), js2[js2_tras]);
-
- /* DBTR7.TRRD : tRRD */
- mmio_write_32(DBSC_DBTR(7), (js2[js2_trrd] << 16) | js2[js2_trrd]);
-
- /* DBTR8.TFAW : tFAW */
- mmio_write_32(DBSC_DBTR(8), js2[js2_tfaw]);
-
- /* DBTR9.TRDPR : tRTP */
- mmio_write_32(DBSC_DBTR(9), js2[js2_trtp]);
-
- /* DBTR10.TWR : nWR */
- mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nwr);
-
- /*
- * DBTR11.TRDWR : RL + BL / 2 + Rounddown(tRPST) + PHY_ODTLoff -
- * odtlon + tDQSCK - tODTon,min +
- * PCB delay (out+in) + tPHY_ODToff
- */
- mmio_write_32(DBSC_DBTR(11),
- RL + (16 / 2) + 1 + 2 - js1[js1_ind].odtlon +
- js2[js2_tdqsck] - js2[js2_tODTon_min] +
- _f_scale(ddr_mbps, ddr_mbpsdiv, 1300, 0));
-
- /* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */
- data_l = WL + 1 + (16 / 2) + js2[js2_twtr];
- mmio_write_32(DBSC_DBTR(12), (data_l << 16) | data_l);
-
- /* DBTR13.TRFCAB : tRFCab */
- mmio_write_32(DBSC_DBTR(13), (js2[js2_trfcab]));
-
- /* DBTR14.TCKEHDLL,tCKEH : tCKEHCMD,tCKEHCMD */
- mmio_write_32(DBSC_DBTR(14),
- (js2[js2_tckehcmd] << 16) | (js2[js2_tckehcmd]));
-
- /* DBTR15.TCKESR,TCKEL : tSR,tCKELPD */
- mmio_write_32(DBSC_DBTR(15), (js2[js2_tsr] << 16) | (js2[js2_tckelpd]));
-
- /* DBTR16 */
- /* WDQL : tphy_wrlat + tphy_wrdata */
- tmp[0] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1);
- /* DQENLTNCY : tphy_wrlat = WL-2 : PHY_WRITE_PATH_LAT_ADD == 0
- * tphy_wrlat = WL-3 : PHY_WRITE_PATH_LAT_ADD != 0
- */
- tmp[1] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1);
- /* DQL : tphy_rdlat + trdata_en */
- /* it is not important for dbsc */
- tmp[2] = RL + 16;
- /* DQIENLTNCY : trdata_en */
- tmp[3] = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1) - 1;
- mmio_write_32(DBSC_DBTR(16),
- (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]);
-
- /* DBTR24 */
- /* WRCSLAT = WRLAT -5 */
- tmp[0] -= 5;
- /* WRCSGAP = 5 */
- tmp[1] = 5;
- /* RDCSLAT = RDLAT_ADJ +2 */
- if (prr_product == PRR_PRODUCT_M3) {
- tmp[2] = tmp[3];
- } else {
- tmp[2] = tmp[3] + 2;
- }
- /* RDCSGAP = 6 */
- if (prr_product == PRR_PRODUCT_M3) {
- tmp[3] = 4;
- } else {
- tmp[3] = 6;
- }
- mmio_write_32(DBSC_DBTR(24),
- (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]);
-
- /* DBTR17.TMODRD,TMOD,TRDMR: tMRR,tMRD,(0) */
- mmio_write_32(DBSC_DBTR(17),
- (js2[js2_tmrr] << 24) | (js2[js2_tmrd] << 16));
-
- /* DBTR18.RODTL, RODTA, WODTL, WODTA : do not use in LPDDR4 */
- mmio_write_32(DBSC_DBTR(18), 0);
-
- /* DBTR19.TZQCL, TZQCS : do not use in LPDDR4 */
- mmio_write_32(DBSC_DBTR(19), 0);
-
- /* DBTR20.TXSDLL, TXS : tRFCab+tCKEHCMD */
- data_l = js2[js2_trfcab] + js2[js2_tckehcmd];
- mmio_write_32(DBSC_DBTR(20), (data_l << 16) | data_l);
-
- /* DBTR21.TCCD */
- /* DBTR23.TCCD */
- /* H3 Ver.1.0 cannot use TBTR23 feature */
- if (ddr_tccd == 8 &&
- !((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_10))
- ) {
- data_l = 8;
- mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
- mmio_write_32(DBSC_DBTR(23), 0x00000002);
- } else if (ddr_tccd <= 11) {
- data_l = 11;
- mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
- mmio_write_32(DBSC_DBTR(23), 0x00000000);
- } else {
- data_l = ddr_tccd;
- mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
- mmio_write_32(DBSC_DBTR(23), 0x00000000);
- }
-
- /* DBTR22.ZQLAT : */
- data_l = js2[js2_tzqcalns] * 100; /* 1000 * 1000 ps */
- data_l = (data_l << 16) | (js2[js2_tzqlat] + 24 + 20);
- mmio_write_32(DBSC_DBTR(22), data_l);
-
- /* DBTR25 : do not use in LPDDR4 */
- mmio_write_32(DBSC_DBTR(25), 0);
-
- /* DBRNK : */
- /*
- * DBSC_DBRNK2 rkrr
- * DBSC_DBRNK3 rkrw
- * DBSC_DBRNK4 rkwr
- * DBSC_DBRNK5 rkww
- */
-#define _par_DBRNK_VAL (0x7007)
-
- for (i = 0; i < 4; i++) {
- data_l = (_par_DBRNK_VAL >> (i * 4)) & 0x0f;
- if ((prr_product == PRR_PRODUCT_H3) &&
- (prr_cut > PRR_PRODUCT_11) && (i == 0)) {
- data_l += 1;
- }
- data_l2 = 0;
- foreach_vch(ch) {
- data_l2 = data_l2 | (data_l << (4 * ch));
- }
- mmio_write_32(DBSC_DBRNK(2 + i), data_l2);
- }
- mmio_write_32(DBSC_DBADJ0, 0x00000000);
-
- /* timing registers for Scheduler */
- /* SCFCTST0 */
- /* SCFCTST0 ACT-ACT */
- tmp[3] = 1UL * js2[js2_trcpb] * 800 * ddr_mbpsdiv / ddr_mbps;
- /* SCFCTST0 RDA-ACT */
- tmp[2] =
- 1UL * ((16 / 2) + js2[js2_trtp] - 8 +
- js2[js2_trppb]) * 800 * ddr_mbpsdiv / ddr_mbps;
- /* SCFCTST0 WRA-ACT */
- tmp[1] =
- 1UL * (WL + 1 + (16 / 2) +
- js1[js1_ind].nwr) * 800 * ddr_mbpsdiv / ddr_mbps;
- /* SCFCTST0 PRE-ACT */
- tmp[0] = 1UL * js2[js2_trppb];
- mmio_write_32(DBSC_SCFCTST0,
- (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]);
-
- /* SCFCTST1 */
- /* SCFCTST1 RD-WR */
- tmp[3] =
- 1UL * (mmio_read_32(DBSC_DBTR(11)) & 0xff) * 800 * ddr_mbpsdiv /
- ddr_mbps;
- /* SCFCTST1 WR-RD */
- tmp[2] =
- 1UL * (mmio_read_32(DBSC_DBTR(12)) & 0xff) * 800 * ddr_mbpsdiv /
- ddr_mbps;
- /* SCFCTST1 ACT-RD/WR */
- tmp[1] = 1UL * js2[js2_trcd] * 800 * ddr_mbpsdiv / ddr_mbps;
- /* SCFCTST1 ASYNCOFS */
- tmp[0] = 12;
- mmio_write_32(DBSC_SCFCTST1,
- (tmp[3] << 24) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]);
-
- /* DBSCHRW1 */
- /* DBSCHRW1 SCTRFCAB */
- tmp[0] = 1UL * js2[js2_trfcab] * 800 * ddr_mbpsdiv / ddr_mbps;
- data_l = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000) >> 16)
- + (mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF)
- + (0x28 * 2)) * 400 * 2 * ddr_mbpsdiv / ddr_mbps + 7;
- if (tmp[0] < data_l)
- tmp[0] = data_l;
-
- if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) {
- mmio_write_32(DBSC_DBSCHRW1, tmp[0]
- + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF)
- * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) /
- ddr_mbps - 3);
- } else {
- mmio_write_32(DBSC_DBSCHRW1, tmp[0]
- + ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFF)
- * 400 * 2 * ddr_mbpsdiv + (ddr_mbps - 1)) /
- ddr_mbps);
- }
-
- /* QOS and CAM */
-#ifdef ddr_qos_init_setting /* only for non qos_init */
- /*wbkwait(0004), wbkmdhi(4,2),wbkmdlo(1,8) */
- mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218);
- /*0(fillunit),8(dirtymax),4(dirtymin) */
- mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4);
- /*stop_tolerance */
- mmio_write_32(DBSC_DBSCHRW0, 0x22421111);
- /*rd-wr/wr-rd toggle priority */
- mmio_write_32(DBSC_SCFCTST2, 0x012F1123);
- mmio_write_32(DBSC_DBSCHSZ0, 0x00000001);
- mmio_write_32(DBSC_DBSCHCNT0, 0x000F0037);
-
- /* QoS Settings */
- mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
- mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
- mmio_write_32(DBSC_DBSCHQOS02, 0x00000000U);
- mmio_write_32(DBSC_DBSCHQOS03, 0x00000000U);
- mmio_write_32(DBSC_DBSCHQOS40, 0x00000300U);
- mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
- mmio_write_32(DBSC_DBSCHQOS42, 0x00000200U);
- mmio_write_32(DBSC_DBSCHQOS43, 0x00000100U);
- mmio_write_32(DBSC_DBSCHQOS90, 0x00000100U);
- mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
- mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
- mmio_write_32(DBSC_DBSCHQOS93, 0x00000040U);
- mmio_write_32(DBSC_DBSCHQOS120, 0x00000040U);
- mmio_write_32(DBSC_DBSCHQOS121, 0x00000030U);
- mmio_write_32(DBSC_DBSCHQOS122, 0x00000020U);
- mmio_write_32(DBSC_DBSCHQOS123, 0x00000010U);
- mmio_write_32(DBSC_DBSCHQOS130, 0x00000100U);
- mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
- mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
- mmio_write_32(DBSC_DBSCHQOS133, 0x00000040U);
- mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
- mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
- mmio_write_32(DBSC_DBSCHQOS142, 0x00000080U);
- mmio_write_32(DBSC_DBSCHQOS143, 0x00000040U);
- mmio_write_32(DBSC_DBSCHQOS150, 0x00000040U);
- mmio_write_32(DBSC_DBSCHQOS151, 0x00000030U);
- mmio_write_32(DBSC_DBSCHQOS152, 0x00000020U);
- mmio_write_32(DBSC_DBSCHQOS153, 0x00000010U);
-
- mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
-#endif /* ddr_qos_init_setting */
- /* H3 Ver.1.1 need to set monitor function */
- if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_11)) {
- mmio_write_32(DBSC_DBMONCONF4, 0x00700000);
- }
-
- if (prr_product == PRR_PRODUCT_H3) {
- if (prr_cut == PRR_PRODUCT_10) {
- /* resrdis, simple mode, sc off */
- mmio_write_32(DBSC_DBBCAMDIS, 0x00000007);
- } else if (prr_cut == PRR_PRODUCT_11) {
- /* resrdis, simple mode */
- mmio_write_32(DBSC_DBBCAMDIS, 0x00000005);
- } else if (prr_cut < PRR_PRODUCT_30) {
- /* H3 Ver.2.0 */
- /* resrdis */
- mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
- } else { /* H3 Ver.3.0(include H3N) */
- /* exprespque */
- mmio_write_32(DBSC_DBBCAMDIS, 0x00000010);
- }
- } else { /* M3-W/M3-N/V3H */
- /* resrdis */
- mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
- }
-}
-
-static void dbsc_regset_post(void)
-{
- uint32_t ch, cs;
- uint32_t data_l;
- uint32_t slice, rdlat_max, rdlat_min;
-
- rdlat_max = 0;
- rdlat_min = 0xffff;
- foreach_vch(ch) {
- for (cs = 0; cs < CS_CNT; cs++) {
- if ((ch_have_this_cs[cs] & (1U << ch)) != 0) {
- for (slice = 0; slice < SLICE_CNT; slice++) {
- ddr_setval_s(ch, slice,
- _reg_PHY_PER_CS_TRAINING_INDEX,
- cs);
- data_l = ddr_getval_s(ch, slice,
- _reg_PHY_RDDQS_LATENCY_ADJUST);
- if (data_l > rdlat_max)
- rdlat_max = data_l;
- if (data_l < rdlat_min)
- rdlat_min = data_l;
- }
- }
- }
- }
- if ((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) {
-#if RCAR_DRAM_SPLIT == 2
- if (board_cnf->phyvalid == 0x05) {
- mmio_write_32(DBSC_DBTR(24),
- (rdlat_max << 24) + (rdlat_min << 16) +
- mmio_read_32(DBSC_DBTR(24)));
- } else {
- mmio_write_32(DBSC_DBTR(24),
- ((rdlat_max * 2 - rdlat_min + 4) << 24) +
- ((rdlat_min + 2) << 16) +
- mmio_read_32(DBSC_DBTR(24)));
- }
-#else /*RCAR_DRAM_SPLIT == 2 */
- mmio_write_32(DBSC_DBTR(24),
- ((rdlat_max * 2 - rdlat_min + 4) << 24) +
- ((rdlat_min + 2) << 16) +
- mmio_read_32(DBSC_DBTR(24)));
-#endif /*RCAR_DRAM_SPLIT == 2 */
- } else {
- mmio_write_32(DBSC_DBTR(24),
- ((rdlat_max + 2) << 24) +
- ((rdlat_max + 2) << 16) +
- mmio_read_32(DBSC_DBTR(24)));
- }
-
- /* set ddr density information */
- foreach_ech(ch) {
- for (cs = 0; cs < CS_CNT; cs++) {
- if (ddr_density[ch][cs] == 0xff) {
- mmio_write_32(DBSC_DBMEMCONF(ch, cs), 0x00);
- } else {
- mmio_write_32(DBSC_DBMEMCONF(ch, cs),
- DBMEMCONF_REGD(ddr_density[ch]
- [cs]));
- }
- }
- mmio_write_32(DBSC_DBMEMCONF(ch, 2), 0x00000000);
- mmio_write_32(DBSC_DBMEMCONF(ch, 3), 0x00000000);
- }
-
- mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
-
- /*set DBI */
- if (board_cnf->dbi_en)
- mmio_write_32(DBSC_DBDBICNT, 0x00000003);
-
- /* H3 Ver.2.0 or later/M3-N/V3H DBI wa */
- if ((((prr_product == PRR_PRODUCT_H3) &&
- (prr_cut > PRR_PRODUCT_11)) ||
- (prr_product == PRR_PRODUCT_M3N) ||
- (prr_product == PRR_PRODUCT_V3H)) &&
- board_cnf->dbi_en)
- reg_ddrphy_write_a(0x00001010, 0x01000000);
-
- /*set REFCYCLE */
- data_l = (get_refperiod()) * ddr_mbps / 2000 / ddr_mbpsdiv;
- mmio_write_32(DBSC_DBRFCNF1, 0x00080000 | (data_l & 0x0000ffff));
- mmio_write_32(DBSC_DBRFCNF2, 0x00010000 | DBSC_REFINTS);
-
-#if RCAR_REWT_TRAINING != 0
- /* Periodic-WriteDQ Training seeting */
- if (((prr_product == PRR_PRODUCT_H3) &&
- (prr_cut <= PRR_PRODUCT_11)) ||
- ((prr_product == PRR_PRODUCT_M3) &&
- (prr_cut == PRR_PRODUCT_10))) {
- /* non : H3 Ver.1.x/M3-W Ver.1.0 not support */
- } else {
- /* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H */
- mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000);
-
- ddr_setval_ach_as(_reg_PHY_WDQLVL_PATT, 0x04);
- ddr_setval_ach_as(_reg_PHY_WDQLVL_QTR_DLY_STEP, 0x0F);
- ddr_setval_ach_as(_reg_PHY_WDQLVL_DLY_STEP, 0x50);
- ddr_setval_ach_as(_reg_PHY_WDQLVL_DQDM_SLV_DLY_START, 0x0300);
-
- ddr_setval_ach(_reg_PI_WDQLVL_CS_MAP,
- ddrtbl_getval(_cnf_DDR_PI_REGSET,
- _reg_PI_WDQLVL_CS_MAP));
- ddr_setval_ach(_reg_PI_LONG_COUNT_MASK, 0x1f);
- ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00);
- ddr_setval_ach(_reg_PI_WDQLVL_ROTATE, 0x01);
- ddr_setval_ach(_reg_PI_TREF_F0, 0x0000);
- ddr_setval_ach(_reg_PI_TREF_F1, 0x0000);
- ddr_setval_ach(_reg_PI_TREF_F2, 0x0000);
-
- if (prr_product == PRR_PRODUCT_M3) {
- ddr_setval_ach(_reg_PI_WDQLVL_EN, 0x02);
- } else {
- ddr_setval_ach(_reg_PI_WDQLVL_EN_F1, 0x02);
- }
- ddr_setval_ach(_reg_PI_WDQLVL_PERIODIC, 0x01);
-
- /* DFI_PHYMSTR_ACK , WTmode setting */
- /* DFI_PHYMSTR_ACK: WTmode =b'01 */
- mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011);
- }
-#endif /* RCAR_REWT_TRAINING */
- /* periodic dram zqcal enable */
- mmio_write_32(DBSC_DBCALCNF, 0x01000010);
-
- /* periodic phy ctrl update enable */
- if (((prr_product == PRR_PRODUCT_H3) &&
- (prr_cut <= PRR_PRODUCT_11)) ||
- ((prr_product == PRR_PRODUCT_M3) &&
- (prr_cut < PRR_PRODUCT_30))) {
- /* non : H3 Ver.1.x/M3-W Ver.1.x not support */
- } else {
-#if RCAR_DRAM_SPLIT == 2
- if ((prr_product == PRR_PRODUCT_H3) &&
- (board_cnf->phyvalid == 0x05))
- mmio_write_32(DBSC_DBDFICUPDCNF, 0x2a240001);
- else
- mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001);
-#else /* RCAR_DRAM_SPLIT == 2 */
- mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001);
-#endif /* RCAR_DRAM_SPLIT == 2 */
- }
-
-#ifdef DDR_BACKUPMODE
- /* SRX */
- if (ddr_backup == DRAM_BOOT_STATUS_WARM) {
-#ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0, 1 only) */
- NOTICE("BL2: [DEBUG_MESS] DDR_BACKUPMODE_HALF\n");
- send_dbcmd(0x0A040001);
- if (Prr_Product == PRR_PRODUCT_H3)
- send_dbcmd(0x0A140001);
-#else /* DDR_BACKUPMODE_HALF */ /* for All channels */
- send_dbcmd(0x0A840001);
-#endif /* DDR_BACKUPMODE_HALF */
- }
-#endif /* DDR_BACKUPMODE */
-
- /* set Auto Refresh */
- mmio_write_32(DBSC_DBRFEN, 0x00000001);
-
-#if RCAR_REWT_TRAINING != 0
- /* Periodic WriteDQ Traning */
- if (((prr_product == PRR_PRODUCT_H3) &&
- (prr_cut <= PRR_PRODUCT_11)) ||
- ((prr_product == PRR_PRODUCT_M3) &&
- (prr_cut == PRR_PRODUCT_10))) {
- /* non : H3 Ver.1.x/M3-W Ver.1.0 not support */
- } else {
- /* H3 Ver.2.0 or later/M3-W Ver.1.1 or later/M3-N/V3H */
- ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, 0x0100);
- }
-#endif /* RCAR_REWT_TRAINING */
-
- /* dram access enable */
- mmio_write_32(DBSC_DBACEN, 0x00000001);
-
- MSG_LF(__func__ "(done)");
-}
-
-/* DFI_INIT_START */
-static uint32_t dfi_init_start(void)
-{
- uint32_t ch;
- uint32_t phytrainingok;
- uint32_t retry;
- uint32_t data_l;
- const uint32_t RETRY_MAX = 0x10000;
-
- if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
- /* PLL3 Disable */
- /* protect register interface */
- ddrphy_regif_idle();
-
- pll3_control(0);
-
- /* init start */
- /* dbdficnt0:
- * dfi_dram_clk_disable=1
- * dfi_frequency = 0
- * freq_ratio = 01 (2:1)
- * init_start =0
- */
- foreach_vch(ch)
- mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10);
- dsb_sev();
-
- /* dbdficnt0:
- * dfi_dram_clk_disable=1
- * dfi_frequency = 0
- * freq_ratio = 01 (2:1)
- * init_start =1
- */
- foreach_vch(ch)
- mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11);
- dsb_sev();
-
- } else {
- ddr_setval_ach_as(_reg_PHY_DLL_RST_EN, 0x02);
- dsb_sev();
- ddrphy_regif_idle();
- }
-
- /* dll_rst negate */
- foreach_vch(ch)
- mmio_write_32(DBSC_DBPDCNT3(ch), 0x0000CF01);
- dsb_sev();
-
- /* wait init_complete */
- phytrainingok = 0;
- retry = 0;
- while (retry++ < RETRY_MAX) {
- foreach_vch(ch) {
- data_l = mmio_read_32(DBSC_DBDFISTAT(ch));
- if (data_l & 0x00000001)
- phytrainingok |= (1U << ch);
- }
- dsb_sev();
- if (phytrainingok == ddr_phyvalid)
- break;
- if (retry % 256 == 0)
- ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01);
- }
-
- /* all ch ok? */
- if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid)
- return 0xff;
-
- /* dbdficnt0:
- * dfi_dram_clk_disable=0
- * dfi_frequency = 0
- * freq_ratio = 01 (2:1)
- * init_start =0
- */
- foreach_vch(ch)
- mmio_write_32(DBSC_DBDFICNT(ch), 0x00000010);
- dsb_sev();
-
- return 0;
-}
-
-/* drivablity setting : CMOS MODE ON/OFF */
-static void change_lpddr4_en(uint32_t mode)
-{
- uint32_t ch;
- uint32_t i;
- uint32_t data_l;
- const uint32_t _reg_PHY_PAD_DRIVE_X[3] = {
- _reg_PHY_PAD_ADDR_DRIVE,
- _reg_PHY_PAD_CLK_DRIVE,
- _reg_PHY_PAD_CS_DRIVE
- };
-
- foreach_vch(ch) {
- for (i = 0; i < 3; i++) {
- data_l = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]);
- if (mode) {
- data_l |= (1U << 14);
- } else {
- data_l &= ~(1U << 14);
- }
- ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], data_l);
- }
- }
-}
-
-/* drivablity setting */
-static uint32_t set_term_code(void)
-{
- int32_t i;
- uint32_t ch, index;
- uint32_t data_l;
- uint32_t chip_id[2];
- uint32_t term_code;
- uint32_t override;
- uint32_t pvtr;
- uint32_t pvtp;
- uint32_t pvtn;
-
- term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_PAD_DATA_TERM);
- override = 0;
- for (i = 0; i < 2; i++)
- chip_id[i] = mmio_read_32(LIFEC_CHIPID(i));
-
- index = 0;
- while (1) {
- if (termcode_by_sample[index][0] == 0xffffffff) {
- break;
- }
- if ((termcode_by_sample[index][0] == chip_id[0]) &&
- (termcode_by_sample[index][1] == chip_id[1])) {
- term_code = termcode_by_sample[index][2];
- override = 1;
- break;
- }
- index++;
- }
-
- if (override) {
- for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM; index++) {
- data_l =
- ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_PAD_TERM_X[index]);
- data_l = (data_l & 0xfffe0000) | term_code;
- ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], data_l);
- }
- } else if ((prr_product == PRR_PRODUCT_M3) &&
- (prr_cut == PRR_PRODUCT_10)) {
- /* non */
- } else {
- ddr_setval_ach(_reg_PHY_PAD_TERM_X[0],
- (ddrtbl_getval
- (_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_PAD_TERM_X[0]) & 0xFFFE0000));
- ddr_setval_ach(_reg_PHY_CAL_CLEAR_0, 0x01);
- ddr_setval_ach(_reg_PHY_CAL_START_0, 0x01);
- foreach_vch(ch) {
- do {
- data_l =
- ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0);
- } while (!(data_l & 0x00800000));
- }
- if ((prr_product == PRR_PRODUCT_H3) &&
- (prr_cut <= PRR_PRODUCT_11)) {
- foreach_vch(ch) {
- data_l = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]);
- pvtr = (data_l >> 12) & 0x1f;
- pvtr += 8;
- if (pvtr > 0x1f)
- pvtr = 0x1f;
- data_l =
- ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0);
- pvtn = (data_l >> 6) & 0x03f;
- pvtp = (data_l >> 0) & 0x03f;
-
- for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM;
- index++) {
- data_l =
- ddrtbl_getval
- (_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_PAD_TERM_X[index]);
- data_l = (data_l & 0xfffe0000)
- | (pvtr << 12)
- | (pvtn << 6)
- | (pvtp);
- ddr_setval(ch,
- _reg_PHY_PAD_TERM_X[index],
- data_l);
- }
- }
- } else {
- /* M3-W Ver.1.1 or later/H3 Ver.2.0 or later/M3-N/V3H */
- foreach_vch(ch) {
- for (index = 0; index < _reg_PHY_PAD_TERM_X_NUM;
- index++) {
- data_l =
- ddr_getval(ch,
- _reg_PHY_PAD_TERM_X
- [index]);
- ddr_setval(ch,
- _reg_PHY_PAD_TERM_X[index],
- (data_l & 0xFFFE0FFF) |
- 0x00015000);
- }
- }
- }
- }
-
- if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
- /* non */
- } else {
- ddr_padcal_tcompensate_getinit(override);
- }
-
- return 0;
-}
-
-/* DDR mode register setting */
-static void ddr_register_set(void)
-{
- int32_t fspwp;
- uint32_t tmp;
-
- for (fspwp = 1; fspwp >= 0; fspwp--) {
- /*MR13, fspwp */
- send_dbcmd(0x0e840d08 | ((2 - fspwp) << 6));
-
- tmp =
- ddrtbl_getval(_cnf_DDR_PI_REGSET,
- reg_pi_mr1_data_fx_csx[fspwp][0]);
- send_dbcmd(0x0e840100 | tmp);
-
- tmp =
- ddrtbl_getval(_cnf_DDR_PI_REGSET,
- reg_pi_mr2_data_fx_csx[fspwp][0]);
- send_dbcmd(0x0e840200 | tmp);
-
- tmp =
- ddrtbl_getval(_cnf_DDR_PI_REGSET,
- reg_pi_mr3_data_fx_csx[fspwp][0]);
- send_dbcmd(0x0e840300 | tmp);
-
- tmp =
- ddrtbl_getval(_cnf_DDR_PI_REGSET,
- reg_pi_mr11_data_fx_csx[fspwp][0]);
- send_dbcmd(0x0e840b00 | tmp);
-
- tmp =
- ddrtbl_getval(_cnf_DDR_PI_REGSET,
- reg_pi_mr12_data_fx_csx[fspwp][0]);
- send_dbcmd(0x0e840c00 | tmp);
-
- tmp =
- ddrtbl_getval(_cnf_DDR_PI_REGSET,
- reg_pi_mr14_data_fx_csx[fspwp][0]);
- send_dbcmd(0x0e840e00 | tmp);
- /* MR22 */
- send_dbcmd(0x0e841616);
-
- /* ZQCAL start */
- send_dbcmd(0x0d84004F);
-
- /* ZQLAT */
- send_dbcmd(0x0d840051);
- }
-
- /* MR13, fspwp */
- send_dbcmd(0x0e840d08);
-}
-
-/* Training handshake functions */
-static inline uint32_t wait_freqchgreq(uint32_t assert)
-{
- uint32_t data_l;
- uint32_t count;
- uint32_t ch;
-
- count = 100000;
-
- /* H3 Ver.1.x cannot see frqchg_req */
- if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
- return 0;
- }
-
- if (assert) {
- do {
- data_l = 1;
- foreach_vch(ch) {
- data_l &= mmio_read_32(DBSC_DBPDSTAT(ch));
- }
- count = count - 1;
- } while (((data_l & 0x01) != 0x01) & (count != 0));
- } else {
- do {
- data_l = 0;
- foreach_vch(ch) {
- data_l |= mmio_read_32(DBSC_DBPDSTAT(ch));
- }
- count = count - 1;
- } while (((data_l & 0x01) != 0x00) & (count != 0));
- }
-
- return (count == 0);
-}
-
-static inline void set_freqchgack(uint32_t assert)
-{
- uint32_t ch;
- uint32_t data_l;
-
- if (assert)
- data_l = 0x0CF20000;
- else
- data_l = 0x00000000;
-
- foreach_vch(ch)
- mmio_write_32(DBSC_DBPDCNT2(ch), data_l);
-}
-
-static inline void set_dfifrequency(uint32_t freq)
-{
- uint32_t ch;
-
- if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
- foreach_vch(ch)
- mmio_clrsetbits_32(DBSC_DBPDCNT1(ch), 0x1fU, freq);
- } else {
- foreach_vch(ch) {
- mmio_clrsetbits_32(DBSC_DBDFICNT(ch), 0x1fU << 24,
- (freq << 24));
- }
- }
- dsb_sev();
-}
-
-static uint32_t pll3_freq(uint32_t on)
-{
- uint32_t timeout;
-
- timeout = wait_freqchgreq(1);
-
- if (timeout) {
- return 1;
- }
-
- pll3_control(on);
- set_dfifrequency(on);
-
- set_freqchgack(1);
- timeout = wait_freqchgreq(0);
- set_freqchgack(0);
-
- if (timeout) {
- FATAL_MSG("BL2: Time out[2]\n");
- return 1;
- }
- return 0;
-}
-
-/* update dly */
-static void update_dly(void)
-{
- ddr_setval_ach(_reg_SC_PHY_MANUAL_UPDATE, 0x01);
- ddr_setval_ach(_reg_PHY_ADRCTL_MANUAL_UPDATE, 0x01);
-}
-
-/* training by pi */
-static uint32_t pi_training_go(void)
-{
- uint32_t flag;
- uint32_t data_l;
- uint32_t retry;
- const uint32_t RETRY_MAX = 4096 * 16;
- uint32_t ch;
-
- uint32_t mst_ch;
- uint32_t cur_frq;
- uint32_t complete;
- uint32_t frqchg_req;
-
- /* pi_start */
- ddr_setval_ach(_reg_PI_START, 0x01);
- foreach_vch(ch)
- ddr_getval(ch, _reg_PI_INT_STATUS);
-
- /* set dfi_phymstr_ack = 1 */
- mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001);
- dsb_sev();
-
- /* wait pi_int_status[0] */
- mst_ch = 0;
- flag = 0;
- complete = 0;
- cur_frq = 0;
- retry = RETRY_MAX;
- do {
- frqchg_req = mmio_read_32(DBSC_DBPDSTAT(mst_ch)) & 0x01;
-
- /* H3 Ver.1.x cannot see frqchg_req */
- if ((prr_product == PRR_PRODUCT_H3) &&
- (prr_cut <= PRR_PRODUCT_11)) {
- if ((retry % 4096) == 1) {
- frqchg_req = 1;
- } else {
- frqchg_req = 0;
- }
- }
-
- if (frqchg_req) {
- if (cur_frq) {
- /* Low frequency */
- flag = pll3_freq(0);
- cur_frq = 0;
- } else {
- /* High frequency */
- flag = pll3_freq(1);
- cur_frq = 1;
- }
- if (flag)
- break;
- } else {
- if (cur_frq) {
- foreach_vch(ch) {
- if (complete & (1U << ch))
- continue;
- data_l =
- ddr_getval(ch, _reg_PI_INT_STATUS);
- if (data_l & 0x01) {
- complete |= (1U << ch);
- }
- }
- if (complete == ddr_phyvalid)
- break;
- }
- }
- } while (--retry);
- foreach_vch(ch) {
- /* dummy read */
- data_l = ddr_getval_s(ch, 0, _reg_PHY_CAL_RESULT2_OBS_0);
- data_l = ddr_getval(ch, _reg_PI_INT_STATUS);
- ddr_setval(ch, _reg_PI_INT_ACK, data_l);
- }
- if (ddrphy_regif_chk()) {
- return 0xfd;
- }
- return complete;
-}
-
-/* Initialize DDR */
-static uint32_t init_ddr(void)
-{
- int32_t i;
- uint32_t data_l;
- uint32_t phytrainingok;
- uint32_t ch, slice;
- uint32_t err;
- int16_t adj;
-
- MSG_LF(__func__ ":0\n");
-
-#ifdef DDR_BACKUPMODE
- rcar_dram_get_boot_status(&ddr_backup);
-#endif
-
- /* unlock phy */
- /* Unlock DDRPHY register(AGAIN) */
- foreach_vch(ch)
- mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55A);
- dsb_sev();
-
- if ((((prr_product == PRR_PRODUCT_H3) &&
- (prr_cut > PRR_PRODUCT_11)) ||
- (prr_product == PRR_PRODUCT_M3N) ||
- (prr_product == PRR_PRODUCT_V3H)) && board_cnf->dbi_en)
- reg_ddrphy_write_a(0x00001010, 0x01000001);
- else
- reg_ddrphy_write_a(0x00001010, 0x00000001);
- /* DBSC register pre-setting */
- dbsc_regset_pre();
-
- /* load ddrphy registers */
-
- ddrtbl_load();
-
- /* configure ddrphy registers */
- ddr_config();
-
- /* dfi_reset assert */
- foreach_vch(ch)
- mmio_write_32(DBSC_DBPDCNT0(ch), 0x01);
- dsb_sev();
-
- /* dbsc register set */
- dbsc_regset();
- MSG_LF(__func__ ":1\n");
-
- /* dfi_reset negate */
- foreach_vch(ch)
- mmio_write_32(DBSC_DBPDCNT0(ch), 0x00);
- dsb_sev();
-
- /* dfi_init_start (start ddrphy) */
- err = dfi_init_start();
- if (err) {
- return INITDRAM_ERR_I;
- }
- MSG_LF(__func__ ":2\n");
-
- /* ddr backupmode end */
-#ifdef DDR_BACKUPMODE
- if (ddr_backup) {
- NOTICE("BL2: [WARM_BOOT]\n");
- } else {
- NOTICE("BL2: [COLD_BOOT]\n");
- }
- err = rcar_dram_update_boot_status(ddr_backup);
- if (err) {
- NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n");
- return INITDRAM_ERR_I;
- }
-#endif
- MSG_LF(__func__ ":3\n");
-
- /* override term code after dfi_init_complete */
- err = set_term_code();
- if (err) {
- return INITDRAM_ERR_I;
- }
- MSG_LF(__func__ ":4\n");
-
- /* rx offset calibration */
- if ((prr_cut > PRR_PRODUCT_11) || (prr_product == PRR_PRODUCT_M3N) ||
- (prr_product == PRR_PRODUCT_V3H)) {
- err = rx_offset_cal_hw();
- } else {
- err = rx_offset_cal();
- }
- if (err)
- return INITDRAM_ERR_O;
- MSG_LF(__func__ ":5\n");
-
- /* Dummy PDE */
- send_dbcmd(0x08840000);
-
- /* PDX */
- send_dbcmd(0x08840001);
-
- /* check register i/f is alive */
- err = ddrphy_regif_chk();
- if (err) {
- return INITDRAM_ERR_O;
- }
- MSG_LF(__func__ ":6\n");
-
- /* phy initialize end */
-
- /* setup DDR mode registers */
- /* CMOS MODE */
- change_lpddr4_en(0);
-
- /* MRS */
- ddr_register_set();
-
- /* Thermal sensor setting */
- /* THCTR Bit6: PONM=0 , Bit0: THSST=1 */
- data_l = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBF) | 0x00000001;
- mmio_write_32(THS1_THCTR, data_l);
-
- /* LPDDR4 MODE */
- change_lpddr4_en(1);
-
- MSG_LF(__func__ ":7\n");
-
- /* mask CS_MAP if RANKx is not found */
- foreach_vch(ch) {
- data_l = ddr_getval(ch, _reg_PI_CS_MAP);
- if (!(ch_have_this_cs[1] & (1U << ch)))
- data_l = data_l & 0x05;
- ddr_setval(ch, _reg_PI_CS_MAP, data_l);
- }
-
- /* exec pi_training */
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
- BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
- ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00);
-
- if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
- ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_EN, 0x01);
- } else {
- foreach_vch(ch) {
- for (slice = 0; slice < SLICE_CNT; slice++) {
- ddr_setval_s(ch, slice,
- _reg_PHY_PER_CS_TRAINING_EN,
- ((ch_have_this_cs[1]) >> ch)
- & 0x01);
- }
- }
- }
-
- phytrainingok = pi_training_go();
-
- if (ddr_phyvalid != (phytrainingok & ddr_phyvalid)) {
- return INITDRAM_ERR_T | phytrainingok;
- }
-
- MSG_LF(__func__ ":8\n");
-
- /* CACS DLY ADJUST */
- data_l = board_cnf->cacs_dly + _f_scale_adj(board_cnf->cacs_dly_adj);
- foreach_vch(ch) {
- for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
- adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
- ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
- data_l + adj);
- }
-
- if (ddr_phycaslice == 1) {
- for (i = 0; i < 6; i++) {
- adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj
- [i +
- _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]);
- ddr_setval_s(ch, 2,
- _reg_PHY_CLK_CACS_SLAVE_DELAY_X
- [i],
- data_l + adj
- );
- }
- }
- }
-
- update_dly();
- MSG_LF(__func__ ":9\n");
-
- /* H3 fix rd latency to avoid bug in elasitic buffer */
- if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11))
- adjust_rddqs_latency();
-
- /* Adjust Write path latency */
- if (ddrtbl_getval
- (_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD))
- adjust_wpath_latency();
-
- /* RDQLVL Training */
- if (!ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE))
- ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01);
-
- err = rdqdm_man();
-
- if (!ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE))
- ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x00);
-
- if (err) {
- return INITDRAM_ERR_T;
- }
- update_dly();
- MSG_LF(__func__ ":10\n");
-
- /* WDQLVL Training */
- err = wdqdm_man();
- if (err) {
- return INITDRAM_ERR_T;
- }
- update_dly();
- MSG_LF(__func__ ":11\n");
-
- /* training complete, setup DBSC */
- if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) ||
- (prr_product == PRR_PRODUCT_M3N) ||
- (prr_product == PRR_PRODUCT_V3H)) {
- ddr_setval_ach_as(_reg_PHY_DFI40_POLARITY, 0x00);
- ddr_setval_ach(_reg_PI_DFI40_POLARITY, 0x00);
- }
-
- dbsc_regset_post();
- MSG_LF(__func__ ":12\n");
-
- return phytrainingok;
-}
-
-/* SW LEVELING COMMON */
-static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick)
-{
- uint32_t ch;
- uint32_t data_l;
- uint32_t retry;
- uint32_t waiting;
- uint32_t err;
-
- const uint32_t RETRY_MAX = 0x1000;
-
- err = 0;
- /* set EXIT -> OP_DONE is cleared */
- ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01);
-
- /* kick */
- foreach_vch(ch) {
- if (ch_have_this_cs[ddr_csn % 2] & (1U << ch)) {
- ddr_setval(ch, reg_cs, ddr_csn);
- ddr_setval(ch, reg_kick, 0x01);
- }
- }
- foreach_vch(ch) {
- /*PREPARE ADDR REGISTER (for SWLVL_OP_DONE) */
- ddr_getval(ch, _reg_PI_SWLVL_OP_DONE);
- }
- waiting = ch_have_this_cs[ddr_csn % 2];
- dsb_sev();
- retry = RETRY_MAX;
- do {
- foreach_vch(ch) {
- if (!(waiting & (1U << ch)))
- continue;
- data_l = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE);
- if (data_l & 0x01)
- waiting &= ~(1U << ch);
- }
- retry--;
- } while (waiting && (retry > 0));
- if (retry == 0) {
- err = 1;
- }
-
- dsb_sev();
- /* set EXIT -> OP_DONE is cleared */
- ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01);
- dsb_sev();
-
- return err;
-}
-
-/* WDQ TRAINING */
-#ifndef DDR_FAST_INIT
-static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
-{
- int32_t i, k;
- uint32_t cs, slice;
- uint32_t data_l;
-
- /* clr of training results buffer */
- cs = ddr_csn % 2;
- data_l = board_cnf->dqdm_dly_w;
- for (slice = 0; slice < SLICE_CNT; slice++) {
- k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
- if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
- continue;
-
- for (i = 0; i <= 8; i++) {
- if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch))
- wdqdm_dly[ch][cs][slice][i] =
- wdqdm_dly[ch][CS_CNT - 1 - cs][slice][i];
- else
- wdqdm_dly[ch][cs][slice][i] = data_l;
- wdqdm_le[ch][cs][slice][i] = 0;
- wdqdm_te[ch][cs][slice][i] = 0;
- }
- wdqdm_st[ch][cs][slice] = 0;
- wdqdm_win[ch][cs][slice] = 0;
- }
-}
-
-static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
-{
- int32_t i, k;
- uint32_t cs, slice;
- uint32_t data_l;
- uint32_t err;
- const uint32_t _par_WDQLVL_RETRY_THRES = 0x7c0;
-
- int32_t min_win;
- int32_t win;
- int8_t _adj;
- int16_t adj;
- uint32_t dq;
-
- /* analysis of training results */
- err = 0;
- for (slice = 0; slice < SLICE_CNT; slice += 1) {
- k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
- if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
- continue;
-
- cs = ddr_csn % 2;
- ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs);
- for (i = 0; i < 9; i++) {
- dq = slice * 8 + i;
- if (i == 8)
- _adj = board_cnf->ch[ch].dm_adj_w[slice];
- else
- _adj = board_cnf->ch[ch].dq_adj_w[dq];
- adj = _f_scale_adj(_adj);
-
- data_l =
- ddr_getval_s(ch, slice,
- _reg_PHY_CLK_WRX_SLAVE_DELAY[i]) + adj;
- ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i],
- data_l);
- wdqdm_dly[ch][cs][slice][i] = data_l;
- }
- ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00);
- data_l = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS);
- wdqdm_st[ch][cs][slice] = data_l;
- min_win = INT_LEAST32_MAX;
- for (i = 0; i <= 8; i++) {
- ddr_setval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_OBS_SELECT,
- i);
-
- data_l =
- ddr_getval_s(ch, slice,
- _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS);
- wdqdm_te[ch][cs][slice][i] = data_l;
- data_l =
- ddr_getval_s(ch, slice,
- _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS);
- wdqdm_le[ch][cs][slice][i] = data_l;
- win =
- (int32_t)wdqdm_te[ch][cs][slice][i] -
- wdqdm_le[ch][cs][slice][i];
- if (min_win > win)
- min_win = win;
- if (data_l >= _par_WDQLVL_RETRY_THRES)
- err = 2;
- }
- wdqdm_win[ch][cs][slice] = min_win;
- if ((prr_product == PRR_PRODUCT_H3) &&
- (prr_cut <= PRR_PRODUCT_11)) {
- ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN,
- 0x01);
- } else {
- ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN,
- ((ch_have_this_cs[1]) >> ch) & 0x01);
- }
- }
- return err;
-}
-#endif/* DDR_FAST_INIT */
-
-static void wdqdm_cp(uint32_t ddr_csn, uint32_t restore)
-{
- uint32_t i;
- uint32_t ch, slice;
- uint32_t tgt_cs, src_cs;
- uint32_t tmp_r;
-
- /* copy of training results */
- foreach_vch(ch) {
- for (tgt_cs = 0; tgt_cs < CS_CNT; tgt_cs++) {
- for (slice = 0; slice < SLICE_CNT; slice++) {
- ddr_setval_s(ch, slice,
- _reg_PHY_PER_CS_TRAINING_INDEX,
- tgt_cs);
- src_cs = ddr_csn % 2;
- if (!(ch_have_this_cs[1] & (1U << ch)))
- src_cs = 0;
- for (i = 0; i <= 4; i += 4) {
- if (restore)
- tmp_r =
- rdqdm_dly[ch][tgt_cs][slice]
- [i];
- else
- tmp_r =
- rdqdm_dly[ch][src_cs][slice]
- [i];
-
- ddr_setval_s(ch, slice,
- _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY
- [i], tmp_r);
- }
- }
- }
- }
-}
-
-static uint32_t wdqdm_man1(void)
-{
- int32_t k;
- uint32_t ch, cs, slice;
- uint32_t ddr_csn;
- uint32_t data_l;
- uint32_t err;
- uint32_t high_dq[DRAM_CH_CNT];
- uint32_t mr14_csab0_bak[DRAM_CH_CNT];
-#ifndef DDR_FAST_INIT
- uint32_t err_flg;
-#endif/* DDR_FAST_INIT */
-
- /* manual execution of training */
- if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
- foreach_vch(ch) {
- high_dq[ch] = 0;
- for (slice = 0; slice < SLICE_CNT; slice++) {
- k = (board_cnf->ch[ch].dqs_swap >>
- (4 * slice)) & 0x0f;
- if (k >= 2)
- high_dq[ch] |= (1U << slice);
- }
- ddr_setval(ch, _reg_PI_16BIT_DRAM_CONNECT, 0x00);
- }
- }
- err = 0;
- /* CLEAR PREV RESULT */
- for (cs = 0; cs < CS_CNT; cs++) {
- ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_INDEX, cs);
- if (((prr_product == PRR_PRODUCT_H3) &&
- (prr_cut > PRR_PRODUCT_11)) ||
- (prr_product == PRR_PRODUCT_M3N) ||
- (prr_product == PRR_PRODUCT_V3H)) {
- ddr_setval_ach_as(_reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS,
- 0x01);
- } else {
- ddr_setval_ach_as(_reg_PHY_WDQLVL_CLR_PREV_RESULTS,
- 0x01);
- }
- }
- ddrphy_regif_idle();
-
-#ifndef DDR_FAST_INIT
- err_flg = 0;
-#endif/* DDR_FAST_INIT */
- for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
- if ((prr_product == PRR_PRODUCT_H3) &&
- (prr_cut <= PRR_PRODUCT_11)) {
- foreach_vch(ch) {
- data_l = mmio_read_32(DBSC_DBDFICNT(ch));
- data_l &= ~(0x00ffU << 16);
-
- if (ddr_csn >= 2)
- k = (high_dq[ch] ^ 0x0f);
- else
- k = high_dq[ch];
- data_l |= (k << 16);
- mmio_write_32(DBSC_DBDFICNT(ch), data_l);
- ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, k);
- }
- }
- if (((prr_product == PRR_PRODUCT_H3) &&
- (prr_cut <= PRR_PRODUCT_11)) ||
- ((prr_product == PRR_PRODUCT_M3) &&
- (prr_cut == PRR_PRODUCT_10))) {
- wdqdm_cp(ddr_csn, 0);
- }
-
- foreach_vch(ch) {
- data_l =
- ddr_getval(ch,
- reg_pi_mr14_data_fx_csx[1][ddr_csn]);
- ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], data_l);
- }
-
- /* KICK WDQLVL */
- err = swlvl1(ddr_csn, _reg_PI_WDQLVL_CS, _reg_PI_WDQLVL_REQ);
- if (err)
- goto err_exit;
-
- if (ddr_csn == 0)
- foreach_vch(ch) {
- mr14_csab0_bak[ch] =
- ddr_getval(ch, reg_pi_mr14_data_fx_csx[1][0]);
- } else
- foreach_vch(ch) {
- ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0],
- mr14_csab0_bak[ch]);
- }
-#ifndef DDR_FAST_INIT
- foreach_vch(ch) {
- if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) {
- wdqdm_clr1(ch, ddr_csn);
- continue;
- }
- err = wdqdm_ana1(ch, ddr_csn);
- if (err)
- err_flg |= (1U << (ddr_csn * 4 + ch));
- ddrphy_regif_idle();
- }
-#endif/* DDR_FAST_INIT */
- }
-err_exit:
-#ifndef DDR_FAST_INIT
- err |= err_flg;
-#endif/* DDR_FAST_INIT */
- if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
- ddr_setval_ach(_reg_PI_16BIT_DRAM_CONNECT, 0x01);
- foreach_vch(ch) {
- data_l = mmio_read_32(DBSC_DBDFICNT(ch));
- data_l &= ~(0x00ffU << 16);
- mmio_write_32(DBSC_DBDFICNT(ch), data_l);
- ddr_setval(ch, _reg_PI_WDQLVL_RESP_MASK, 0x00);
- }
- }
- return err;
-}
-
-static uint32_t wdqdm_man(void)
-{
- uint32_t err, retry_cnt;
- const uint32_t retry_max = 0x10;
- uint32_t datal, ch, ddr_csn, mr14_bkup[4][4];
-
- datal = RL + js2[js2_tdqsck] + (16 / 2) + 1 - WL + 2 + 2 + 19;
- if ((mmio_read_32(DBSC_DBTR(11)) & 0xFF) > datal)
- datal = mmio_read_32(DBSC_DBTR(11)) & 0xFF;
- ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, datal);
-
- if (((prr_product == PRR_PRODUCT_H3) && (prr_cut > PRR_PRODUCT_11)) ||
- (prr_product == PRR_PRODUCT_M3N) ||
- (prr_product == PRR_PRODUCT_V3H)) {
- ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F0,
- (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10);
- ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR_F1,
- (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10);
- } else {
- ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR,
- (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10);
- }
- ddr_setval_ach(_reg_PI_TRFC_F0, mmio_read_32(DBSC_DBTR(13)) & 0x1FF);
- ddr_setval_ach(_reg_PI_TRFC_F1, mmio_read_32(DBSC_DBTR(13)) & 0x1FF);
-
- retry_cnt = 0;
- err = 0;
- do {
- if ((prr_product == PRR_PRODUCT_H3) &&
- (prr_cut <= PRR_PRODUCT_11)) {
- err = wdqdm_man1();
- } else {
- ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01);
- ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE,
- 0x01);
- if ((prr_product == PRR_PRODUCT_M3N) ||
- (prr_product == PRR_PRODUCT_V3H)) {
- ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1,
- 0x0C);
- } else {
- ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x0C);
- }
- dsb_sev();
- err = wdqdm_man1();
- foreach_vch(ch) {
- for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
- mr14_bkup[ch][ddr_csn] =
- ddr_getval(ch,
- reg_pi_mr14_data_fx_csx
- [1][ddr_csn]);
- dsb_sev();
- }
- }
-
- if ((prr_product == PRR_PRODUCT_M3N) ||
- (prr_product == PRR_PRODUCT_V3H)) {
- ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1,
- 0x04);
- } else {
- ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x04);
- }
- pvtcode_update();
- err = wdqdm_man1();
- foreach_vch(ch) {
- for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
- mr14_bkup[ch][ddr_csn] =
- (mr14_bkup[ch][ddr_csn] +
- ddr_getval(ch,
- reg_pi_mr14_data_fx_csx
- [1][ddr_csn])) / 2;
- ddr_setval(ch,
- reg_pi_mr14_data_fx_csx[1]
- [ddr_csn],
- mr14_bkup[ch][ddr_csn]);
- }
- }
-
- ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE,
- 0x00);
- if ((prr_product == PRR_PRODUCT_M3N) ||
- (prr_product == PRR_PRODUCT_V3H)) {
- ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA_F1,
- 0x00);
- ddr_setval_ach
- (_reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F1,
- 0x00);
- ddr_setval_ach
- (_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1,
- 0x00);
- } else {
- ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x00);
- ddr_setval_ach
- (_reg_PI_WDQLVL_VREF_INITIAL_START_POINT,
- 0x00);
- ddr_setval_ach
- (_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT,
- 0x00);
- }
- ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE,
- 0x00);
-
- pvtcode_update2();
- err = wdqdm_man1();
- ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00);
- }
- } while (err && (++retry_cnt < retry_max));
-
- if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) ||
- ((prr_product == PRR_PRODUCT_M3) && (prr_cut <= PRR_PRODUCT_10))) {
- wdqdm_cp(0, 1);
- }
-
- return (retry_cnt >= retry_max);
-}
-
-/* RDQ TRAINING */
-#ifndef DDR_FAST_INIT
-static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
-{
- int32_t i, k;
- uint32_t cs, slice;
- uint32_t data_l;
-
- /* clr of training results buffer */
- cs = ddr_csn % 2;
- data_l = board_cnf->dqdm_dly_r;
- for (slice = 0; slice < SLICE_CNT; slice++) {
- k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
- if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
- continue;
-
- for (i = 0; i <= 8; i++) {
- if (ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) {
- rdqdm_dly[ch][cs][slice][i] =
- rdqdm_dly[ch][CS_CNT - 1 - cs][slice][i];
- rdqdm_dly[ch][cs][slice + SLICE_CNT][i] =
- rdqdm_dly[ch][CS_CNT - 1 - cs][slice +
- SLICE_CNT]
- [i];
- } else {
- rdqdm_dly[ch][cs][slice][i] = data_l;
- rdqdm_dly[ch][cs][slice + SLICE_CNT][i] =
- data_l;
- }
- rdqdm_le[ch][cs][slice][i] = 0;
- rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0;
- rdqdm_te[ch][cs][slice][i] = 0;
- rdqdm_te[ch][cs][slice + SLICE_CNT][i] = 0;
- rdqdm_nw[ch][cs][slice][i] = 0;
- rdqdm_nw[ch][cs][slice + SLICE_CNT][i] = 0;
- }
- rdqdm_st[ch][cs][slice] = 0;
- rdqdm_win[ch][cs][slice] = 0;
- }
-}
-
-static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
-{
- int32_t i, k;
- uint32_t cs, slice;
- uint32_t data_l;
- uint32_t err;
- int8_t _adj;
- int16_t adj;
- uint32_t dq;
- int32_t min_win;
- int32_t win;
- uint32_t rdq_status_obs_select;
-
- /* analysis of training results */
- err = 0;
- for (slice = 0; slice < SLICE_CNT; slice++) {
- k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
- if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
- continue;
-
- cs = ddr_csn % 2;
- ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs);
- ddrphy_regif_idle();
-
- ddr_getval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX);
- ddrphy_regif_idle();
-
- for (i = 0; i <= 8; i++) {
- dq = slice * 8 + i;
- if (i == 8)
- _adj = board_cnf->ch[ch].dm_adj_r[slice];
- else
- _adj = board_cnf->ch[ch].dq_adj_r[dq];
-
- adj = _f_scale_adj(_adj);
-
- data_l =
- ddr_getval_s(ch, slice,
- _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) +
- adj;
- ddr_setval_s(ch, slice,
- _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i],
- data_l);
- rdqdm_dly[ch][cs][slice][i] = data_l;
-
- data_l =
- ddr_getval_s(ch, slice,
- _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) +
- adj;
- ddr_setval_s(ch, slice,
- _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i],
- data_l);
- rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l;
- }
- min_win = INT_LEAST32_MAX;
- for (i = 0; i <= 8; i++) {
- data_l =
- ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS);
- rdqdm_st[ch][cs][slice] = data_l;
- rdqdm_st[ch][cs][slice + SLICE_CNT] = data_l;
- /* k : rise/fall */
- for (k = 0; k < 2; k++) {
- if (i == 8) {
- rdq_status_obs_select = 16 + 8 * k;
- } else {
- rdq_status_obs_select = i + k * 8;
- }
- ddr_setval_s(ch, slice,
- _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT,
- rdq_status_obs_select);
-
- data_l =
- ddr_getval_s(ch, slice,
- _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS);
- rdqdm_le[ch][cs][slice + SLICE_CNT * k][i] =
- data_l;
-
- data_l =
- ddr_getval_s(ch, slice,
- _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS);
- rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] =
- data_l;
-
- data_l =
- ddr_getval_s(ch, slice,
- _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS);
- rdqdm_nw[ch][cs][slice + SLICE_CNT * k][i] =
- data_l;
-
- win =
- (int32_t)rdqdm_te[ch][cs][slice +
- SLICE_CNT *
- k][i] -
- rdqdm_le[ch][cs][slice + SLICE_CNT * k][i];
- if (i != 8) {
- if (min_win > win)
- min_win = win;
- }
- }
- }
- rdqdm_win[ch][cs][slice] = min_win;
- if (min_win <= 0) {
- err = 2;
- }
- }
- return err;
-}
-#endif/* DDR_FAST_INIT */
-
-static uint32_t rdqdm_man1(void)
-{
- uint32_t ch;
- uint32_t ddr_csn;
-#ifdef DDR_FAST_INIT
- uint32_t slice;
- uint32_t i, adj, data_l;
-#endif/* DDR_FAST_INIT */
- uint32_t err;
-
- /* manual execution of training */
- err = 0;
-
- for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
- /* KICK RDQLVL */
- err = swlvl1(ddr_csn, _reg_PI_RDLVL_CS, _reg_PI_RDLVL_REQ);
- if (err)
- goto err_exit;
-#ifndef DDR_FAST_INIT
- foreach_vch(ch) {
- if (!(ch_have_this_cs[ddr_csn % 2] & (1U << ch))) {
- rdqdm_clr1(ch, ddr_csn);
- ddrphy_regif_idle();
- continue;
- }
- err = rdqdm_ana1(ch, ddr_csn);
- ddrphy_regif_idle();
- if (err)
- goto err_exit;
- }
-#else/* DDR_FAST_INIT */
- foreach_vch(ch) {
- if (ch_have_this_cs[ddr_csn] & (1U << ch)) {
- for (slice = 0; slice < SLICE_CNT; slice++) {
- if (ddr_getval_s(ch, slice,
- _reg_PHY_RDLVL_STATUS_OBS) !=
- 0x0D00FFFF) {
- err = (1U << ch) |
- (0x10U << slice);
- goto err_exit;
- }
- }
- }
- if (((prr_product == PRR_PRODUCT_H3) &&
- (prr_cut <= PRR_PRODUCT_11)) ||
- ((prr_product == PRR_PRODUCT_M3) &&
- (prr_cut <= PRR_PRODUCT_10))) {
- for (slice = 0; slice < SLICE_CNT; slice++) {
- for (i = 0; i <= 8; i++) {
- if (i == 8)
- adj = _f_scale_adj(board_cnf->ch[ch].dm_adj_r[slice]);
- else
- adj = _f_scale_adj(board_cnf->ch[ch].dq_adj_r[slice * 8 + i]);
- ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, ddr_csn);
- data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj;
- ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], data_l);
- rdqdm_dly[ch][ddr_csn][slice][i] = data_l;
- rdqdm_dly[ch][ddr_csn | 1][slice][i] = data_l;
-
- data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj;
- ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], data_l);
- rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = data_l;
- rdqdm_dly[ch][ddr_csn | 1][slice + SLICE_CNT][i] = data_l;
- }
- }
- }
- }
- ddrphy_regif_idle();
-
-#endif/* DDR_FAST_INIT */
- }
-
-err_exit:
- return err;
-}
-
-static uint32_t rdqdm_man(void)
-{
- uint32_t err, retry_cnt;
- const uint32_t retry_max = 0x01;
-
- ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE,
- 0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_PHY_DQ_TSEL_ENABLE));
- ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE,
- 0x00000004 | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_PHY_DQS_TSEL_ENABLE));
- ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT,
- 0xFF0FFFFF & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_PHY_DQ_TSEL_SELECT));
- ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT,
- 0xFF0FFFFF & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_PHY_DQS_TSEL_SELECT));
-
- retry_cnt = 0;
- do {
- err = rdqdm_man1();
- ddrphy_regif_idle();
- } while (err && (++retry_cnt < retry_max));
- ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE,
- ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_PHY_DQ_TSEL_ENABLE));
- ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE,
- ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_PHY_DQS_TSEL_ENABLE));
- ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT,
- ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_PHY_DQ_TSEL_SELECT));
- ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT,
- ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_PHY_DQS_TSEL_SELECT));
-
- return (retry_cnt >= retry_max);
-}
-
-/* rx offset calibration */
-static int32_t _find_change(uint64_t val, uint32_t dir)
-{
- int32_t i;
- uint32_t startval;
- uint32_t curval;
- const int32_t VAL_END = 0x3f;
-
- if (dir == 0) {
- startval = (val & 0x01);
- for (i = 1; i <= VAL_END; i++) {
- curval = (val >> i) & 0x01;
- if (curval != startval)
- return i;
- }
- return VAL_END;
- }
-
- startval = (val >> dir) & 0x01;
- for (i = dir - 1; i >= 0; i--) {
- curval = (val >> i) & 0x01;
- if (curval != startval)
- return i;
- }
- return 0;
-}
-
-static uint32_t _rx_offset_cal_updn(uint32_t code)
-{
- const uint32_t CODE_MAX = 0x40;
- uint32_t tmp;
-
- if ((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) {
- if (code == 0)
- tmp = (1U << 6) | (CODE_MAX - 1);
- else if (code <= 0x20)
- tmp =
- ((CODE_MAX - 1 -
- (0x20 - code) * 2) << 6) | (CODE_MAX - 1);
- else
- tmp =
- ((CODE_MAX - 1) << 6) | (CODE_MAX - 1 -
- (code - 0x20) * 2);
- } else {
- if (code == 0)
- tmp = (1U << 6) | (CODE_MAX - 1);
- else
- tmp = (code << 6) | (CODE_MAX - code);
- }
- return tmp;
-}
-
-static uint32_t rx_offset_cal(void)
-{
- uint32_t index;
- uint32_t code;
- const uint32_t CODE_MAX = 0x40;
- const uint32_t CODE_STEP = 2;
- uint32_t ch, slice;
- uint32_t tmp;
- uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT];
- uint64_t val[DRAM_CH_CNT][SLICE_CNT][_reg_PHY_RX_CAL_X_NUM];
- uint64_t tmpval;
- int32_t lsb, msb;
-
- ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x01);
- foreach_vch(ch) {
- for (slice = 0; slice < SLICE_CNT; slice++) {
- for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++)
- val[ch][slice][index] = 0;
- }
- }
-
- for (code = 0; code < CODE_MAX / CODE_STEP; code++) {
- tmp = _rx_offset_cal_updn(code * CODE_STEP);
- for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) {
- ddr_setval_ach_as(_reg_PHY_RX_CAL_X[index], tmp);
- }
- dsb_sev();
- ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *)tmp_ach_as);
-
- foreach_vch(ch) {
- for (slice = 0; slice < SLICE_CNT; slice++) {
- tmp = tmp_ach_as[ch][slice];
- for (index = 0; index < _reg_PHY_RX_CAL_X_NUM;
- index++) {
- if (tmp & (1U << index)) {
- val[ch][slice][index] |=
- (1ULL << code);
- } else {
- val[ch][slice][index] &=
- ~(1ULL << code);
- }
- }
- }
- }
- }
- foreach_vch(ch) {
- for (slice = 0; slice < SLICE_CNT; slice++) {
- for (index = 0; index < _reg_PHY_RX_CAL_X_NUM;
- index++) {
- tmpval = val[ch][slice][index];
- lsb = _find_change(tmpval, 0);
- msb =
- _find_change(tmpval,
- (CODE_MAX / CODE_STEP) - 1);
- tmp = (lsb + msb) >> 1;
-
- tmp = _rx_offset_cal_updn(tmp * CODE_STEP);
- ddr_setval_s(ch, slice,
- _reg_PHY_RX_CAL_X[index], tmp);
- }
- }
- }
- ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00);
-
- return 0;
-}
-
-static uint32_t rx_offset_cal_hw(void)
-{
- uint32_t ch, slice;
- uint32_t retry;
- uint32_t complete;
- uint32_t tmp;
- uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT];
-
- ddr_setval_ach_as(_reg_PHY_RX_CAL_X[9], 0x00);
- ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00);
- ddr_setval_ach_as(_reg_PHY_RX_CAL_SAMPLE_WAIT, 0x0f);
-
- retry = 0;
- while (retry < 4096) {
- if ((retry & 0xff) == 0) {
- ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01);
- }
- foreach_vch(ch)
- for (slice = 0; slice < SLICE_CNT; slice++)
- tmp_ach_as[ch][slice] =
- ddr_getval_s(ch, slice, _reg_PHY_RX_CAL_X[9]);
-
- complete = 1;
- foreach_vch(ch) {
- for (slice = 0; slice < SLICE_CNT; slice++) {
- tmp = tmp_ach_as[ch][slice];
- tmp = (tmp & 0x3f) + ((tmp >> 6) & 0x3f);
- if (((prr_product == PRR_PRODUCT_H3) &&
- (prr_cut > PRR_PRODUCT_11)) ||
- (prr_product == PRR_PRODUCT_M3N) ||
- (prr_product == PRR_PRODUCT_V3H)) {
- if (tmp != 0x3E)
- complete = 0;
- } else {
- if (tmp != 0x40)
- complete = 0;
- }
- }
- }
- if (complete)
- break;
-
- retry++;
- }
-
- return (complete == 0);
-}
-
-/* adjust rddqs latency */
-static void adjust_rddqs_latency(void)
-{
- uint32_t ch, slice;
- uint32_t dly;
- uint32_t maxlatx2;
- uint32_t tmp;
- uint32_t rdlat_adjx2[SLICE_CNT];
-
- foreach_vch(ch) {
- maxlatx2 = 0;
- for (slice = 0; slice < SLICE_CNT; slice++) {
- ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX,
- 0x00);
-
- dly =
- ddr_getval_s(ch, slice,
- _reg_PHY_RDDQS_GATE_SLAVE_DELAY);
- tmp =
- ddr_getval_s(ch, slice,
- _reg_PHY_RDDQS_LATENCY_ADJUST);
- /* note gate_slave_delay[9] is always 0 */
- tmp = (tmp << 1) + (dly >> 8);
- rdlat_adjx2[slice] = tmp;
- if (maxlatx2 < tmp)
- maxlatx2 = tmp;
- }
- maxlatx2 = ((maxlatx2 + 1) >> 1) << 1;
- for (slice = 0; slice < SLICE_CNT; slice++) {
- tmp = maxlatx2 - rdlat_adjx2[slice];
- tmp = (tmp >> 1);
- if (tmp) {
- ddr_setval_s(ch, slice, _reg_PHY_RPTR_UPDATE,
- ddr_getval_s(ch, slice,
- _reg_PHY_RPTR_UPDATE)
- + 1);
- }
- }
- }
-}
-
-/* adjust wpath latency */
-static void adjust_wpath_latency(void)
-{
- uint32_t ch, cs, slice;
- uint32_t dly;
- uint32_t wpath_add;
- const uint32_t _par_EARLY_THRESHOLD_VAL = 0x180;
-
- foreach_vch(ch) {
- for (slice = 0; slice < SLICE_CNT; slice += 1) {
- for (cs = 0; cs < CS_CNT; cs++) {
- ddr_setval_s(ch, slice,
- _reg_PHY_PER_CS_TRAINING_INDEX,
- cs);
- ddr_getval_s(ch, slice,
- _reg_PHY_PER_CS_TRAINING_INDEX);
- dly =
- ddr_getval_s(ch, slice,
- _reg_PHY_CLK_WRDQS_SLAVE_DELAY);
- if (dly <= _par_EARLY_THRESHOLD_VAL)
- continue;
-
- wpath_add =
- ddr_getval_s(ch, slice,
- _reg_PHY_WRITE_PATH_LAT_ADD);
- ddr_setval_s(ch, slice,
- _reg_PHY_WRITE_PATH_LAT_ADD,
- wpath_add - 1);
- }
- }
- }
-}
-
-/* DDR Initialize entry */
-int32_t rcar_dram_init(void)
-{
- uint32_t ch, cs;
- uint32_t data_l;
- uint32_t bus_mbps, bus_mbpsdiv;
- uint32_t tmp_tccd;
- uint32_t failcount;
- uint32_t cnf_boardtype;
-
- /* Thermal sensor setting */
- data_l = mmio_read_32(CPG_MSTPSR5);
- if (data_l & BIT(22)) { /* case THS/TSC Standby */
- data_l &= ~BIT(22);
- cpg_write_32(CPG_SMSTPCR5, data_l);
- while (mmio_read_32(CPG_MSTPSR5) & BIT(22))
- ; /* wait bit=0 */
- }
-
- /* THCTR Bit6: PONM=0 , Bit0: THSST=0 */
- data_l = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE;
- mmio_write_32(THS1_THCTR, data_l);
-
- /* Judge product and cut */
-#ifdef RCAR_DDR_FIXED_LSI_TYPE
-#if (RCAR_LSI == RCAR_AUTO)
- prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
- prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
-#else /* RCAR_LSI */
-#ifndef RCAR_LSI_CUT
- prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
-#endif /* RCAR_LSI_CUT */
-#endif /* RCAR_LSI */
-#else /* RCAR_DDR_FIXED_LSI_TYPE */
- prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
- prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
-#endif /* RCAR_DDR_FIXED_LSI_TYPE */
-
- if (prr_product == PRR_PRODUCT_H3) {
- if (prr_cut <= PRR_PRODUCT_11) {
- p_ddr_regdef_tbl =
- (const uint32_t *)&DDR_REGDEF_TBL[0][0];
- } else {
- p_ddr_regdef_tbl =
- (const uint32_t *)&DDR_REGDEF_TBL[2][0];
- }
- } else if (prr_product == PRR_PRODUCT_M3) {
- p_ddr_regdef_tbl =
- (const uint32_t *)&DDR_REGDEF_TBL[1][0];
- } else if ((prr_product == PRR_PRODUCT_M3N) ||
- (prr_product == PRR_PRODUCT_V3H)) {
- p_ddr_regdef_tbl =
- (const uint32_t *)&DDR_REGDEF_TBL[3][0];
- } else {
- FATAL_MSG("BL2: DDR:Unknown Product\n");
- return 0xff;
- }
-
- if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) ||
- ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) {
- /* non : H3 Ver.1.x/M3-W Ver.1.x not support */
- } else {
- mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
- }
-
- /* Judge board type */
- cnf_boardtype = boardcnf_get_brd_type();
- if (cnf_boardtype >= BOARDNUM) {
- FATAL_MSG("BL2: DDR:Unknown Board\n");
- return 0xff;
- }
- board_cnf = (const struct _boardcnf *)&boardcnfs[cnf_boardtype];
-
-/* RCAR_DRAM_SPLIT_2CH (2U) */
-#if RCAR_DRAM_SPLIT == 2
- /* H3(Test for future H3-N): Swap ch2 and ch1 for 2ch-split */
- if ((prr_product == PRR_PRODUCT_H3) && (board_cnf->phyvalid == 0x05)) {
- mmio_write_32(DBSC_DBMEMSWAPCONF0, 0x00000006);
- ddr_phyvalid = 0x03;
- } else {
- ddr_phyvalid = board_cnf->phyvalid;
- }
-#else /* RCAR_DRAM_SPLIT_2CH */
- ddr_phyvalid = board_cnf->phyvalid;
-#endif /* RCAR_DRAM_SPLIT_2CH */
-
- max_density = 0;
-
- for (cs = 0; cs < CS_CNT; cs++) {
- ch_have_this_cs[cs] = 0;
- }
-
- foreach_ech(ch)
- for (cs = 0; cs < CS_CNT; cs++)
- ddr_density[ch][cs] = 0xff;
-
- foreach_vch(ch) {
- for (cs = 0; cs < CS_CNT; cs++) {
- data_l = board_cnf->ch[ch].ddr_density[cs];
- ddr_density[ch][cs] = data_l;
-
- if (data_l == 0xff)
- continue;
- if (data_l > max_density)
- max_density = data_l;
- if ((cs == 1) && (prr_product == PRR_PRODUCT_H3) &&
- (prr_cut <= PRR_PRODUCT_11))
- continue;
- ch_have_this_cs[cs] |= (1U << ch);
- }
- }
-
- /* Judge board clock frequency (in MHz) */
- boardcnf_get_brd_clk(cnf_boardtype, &brd_clk, &brd_clkdiv);
- if ((brd_clk / brd_clkdiv) > 25) {
- brd_clkdiva = 1;
- } else {
- brd_clkdiva = 0;
- }
-
- /* Judge ddr operating frequency clock(in Mbps) */
- boardcnf_get_ddr_mbps(cnf_boardtype, &ddr_mbps, &ddr_mbpsdiv);
-
- ddr0800_mul = CLK_DIV(800, 2, brd_clk, brd_clkdiv * (brd_clkdiva + 1));
-
- ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2, brd_clk,
- brd_clkdiv * (brd_clkdiva + 1));
-
- /* Adjust tccd */
- data_l = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13;
- bus_mbps = 0;
- bus_mbpsdiv = 0;
- switch (data_l) {
- case 0:
- bus_mbps = brd_clk * 0x60 * 2;
- bus_mbpsdiv = brd_clkdiv * 1;
- break;
- case 1:
- bus_mbps = brd_clk * 0x50 * 2;
- bus_mbpsdiv = brd_clkdiv * 1;
- break;
- case 2:
- bus_mbps = brd_clk * 0x40 * 2;
- bus_mbpsdiv = brd_clkdiv * 1;
- break;
- case 3:
- bus_mbps = brd_clk * 0x60 * 2;
- bus_mbpsdiv = brd_clkdiv * 2;
- break;
- default:
- bus_mbps = brd_clk * 0x60 * 2;
- bus_mbpsdiv = brd_clkdiv * 2;
- break;
- }
- tmp_tccd = CLK_DIV(ddr_mbps * 8, ddr_mbpsdiv, bus_mbps, bus_mbpsdiv);
- if (8 * ddr_mbps * bus_mbpsdiv != tmp_tccd * bus_mbps * ddr_mbpsdiv)
- tmp_tccd = tmp_tccd + 1;
-
- if (tmp_tccd < 8)
- ddr_tccd = 8;
- else
- ddr_tccd = tmp_tccd;
-
- NOTICE("BL2: DDR%d(%s)\n", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION);
-
- MSG_LF("Start\n");
-
- /* PLL Setting */
- pll3_control(1);
-
- /* initialize DDR */
- data_l = init_ddr();
- if (data_l == ddr_phyvalid) {
- failcount = 0;
- } else {
- failcount = 1;
- }
-
- foreach_vch(ch)
- mmio_write_32(DBSC_DBPDLK(ch), 0x00000000);
- if (((prr_product == PRR_PRODUCT_H3) && (prr_cut <= PRR_PRODUCT_11)) ||
- ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30))) {
- /* non : H3 Ver.1.x/M3-W Ver.1.x not support */
- } else {
- mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
- }
-
- if (failcount == 0) {
- return INITDRAM_OK;
- } else {
- return INITDRAM_NG;
- }
-}
-
-void pvtcode_update(void)
-{
- uint32_t ch;
- uint32_t data_l;
- uint32_t pvtp[4], pvtn[4], pvtp_init, pvtn_init;
- int32_t pvtp_tmp, pvtn_tmp;
-
- foreach_vch(ch) {
- pvtn_init = (tcal.tcomp_cal[ch] & 0xFC0) >> 6;
- pvtp_init = (tcal.tcomp_cal[ch] & 0x03F) >> 0;
-
- if (8912 * pvtp_init > 44230) {
- pvtp_tmp = (5000 + 8912 * pvtp_init - 44230) / 10000;
- } else {
- pvtp_tmp =
- -((-(5000 + 8912 * pvtp_init - 44230)) / 10000);
- }
- pvtn_tmp = (5000 + 5776 * pvtn_init + 30280) / 10000;
-
- pvtn[ch] = pvtn_tmp + pvtn_init;
- pvtp[ch] = pvtp_tmp + pvtp_init;
-
- if (pvtn[ch] > 63) {
- pvtn[ch] = 63;
- pvtp[ch] =
- (pvtp_tmp) * (63 - 6 * pvtn_tmp -
- pvtn_init) / (pvtn_tmp) +
- 6 * pvtp_tmp + pvtp_init;
- }
- if ((prr_product == PRR_PRODUCT_H3) &&
- (prr_cut <= PRR_PRODUCT_11)) {
- data_l = pvtp[ch] | (pvtn[ch] << 6) |
- (tcal.tcomp_cal[ch] & 0xfffff000);
- reg_ddrphy_write(ch,
- ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
- data_l | 0x00020000);
- reg_ddrphy_write(ch,
- ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
- data_l);
- reg_ddrphy_write(ch,
- ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
- data_l);
- reg_ddrphy_write(ch,
- ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
- data_l);
- reg_ddrphy_write(ch,
- ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
- data_l);
- } else {
- data_l = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000;
- reg_ddrphy_write(ch,
- ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
- data_l | 0x00020000);
- reg_ddrphy_write(ch,
- ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
- data_l);
- reg_ddrphy_write(ch,
- ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
- data_l);
- reg_ddrphy_write(ch,
- ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
- data_l);
- reg_ddrphy_write(ch,
- ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
- data_l);
- }
- }
-}
-
-void pvtcode_update2(void)
-{
- uint32_t ch;
-
- foreach_vch(ch) {
- reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
- tcal.init_cal[ch] | 0x00020000);
- reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
- tcal.init_cal[ch]);
- reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
- tcal.init_cal[ch]);
- reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
- tcal.init_cal[ch]);
- reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
- tcal.init_cal[ch]);
- }
-}
-
-void ddr_padcal_tcompensate_getinit(uint32_t override)
-{
- uint32_t ch;
- uint32_t data_l;
- uint32_t pvtp, pvtn;
-
- tcal.init_temp = 0;
- for (ch = 0; ch < 4; ch++) {
- tcal.init_cal[ch] = 0;
- tcal.tcomp_cal[ch] = 0;
- }
-
- foreach_vch(ch) {
- tcal.init_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]);
- tcal.tcomp_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]);
- }
-
- if (!override) {
- data_l = mmio_read_32(THS1_TEMP);
- if (data_l < 2800) {
- tcal.init_temp =
- (143 * (int32_t)data_l - 359000) / 1000;
- } else {
- tcal.init_temp =
- (121 * (int32_t)data_l - 296300) / 1000;
- }
-
- foreach_vch(ch) {
- pvtp = (tcal.init_cal[ch] >> 0) & 0x000003F;
- pvtn = (tcal.init_cal[ch] >> 6) & 0x000003F;
- if ((int32_t)pvtp >
- ((tcal.init_temp * 29 - 3625) / 1000))
- pvtp =
- (int32_t)pvtp +
- ((3625 - tcal.init_temp * 29) / 1000);
- else
- pvtp = 0;
-
- if ((int32_t)pvtn >
- ((tcal.init_temp * 54 - 6750) / 1000))
- pvtn =
- (int32_t)pvtn +
- ((6750 - tcal.init_temp * 54) / 1000);
- else
- pvtn = 0;
-
- if ((prr_product == PRR_PRODUCT_H3) &&
- (prr_cut <= PRR_PRODUCT_11)) {
- tcal.init_cal[ch] =
- (tcal.init_cal[ch] & 0xfffff000) |
- (pvtn << 6) |
- pvtp;
- } else {
- tcal.init_cal[ch] =
- 0x00015000 | (pvtn << 6) | pvtp;
- }
- }
- tcal.init_temp = 125;
- }
-}
-
-#ifndef ddr_qos_init_setting
-/* For QoS init */
-uint8_t get_boardcnf_phyvalid(void)
-{
- return ddr_phyvalid;
-}
-#endif /* ddr_qos_init_setting */
diff --git a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
deleted file mode 100644
index de126de..0000000
--- a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
+++ /dev/null
@@ -1,1804 +0,0 @@
-/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation.
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#define BOARDNUM 22
-#define BOARD_JUDGE_AUTO
-
-#ifdef BOARD_JUDGE_AUTO
-static uint32_t _board_judge(void);
-
-static uint32_t boardcnf_get_brd_type(void)
-{
- return _board_judge();
-}
-#else
-static uint32_t boardcnf_get_brd_type(void)
-{
- return 1;
-}
-#endif
-
-#define DDR_FAST_INIT
-
-struct _boardcnf_ch {
- uint8_t ddr_density[CS_CNT];
- uint64_t ca_swap;
- uint16_t dqs_swap;
- uint32_t dq_swap[SLICE_CNT];
- uint8_t dm_swap[SLICE_CNT];
- uint16_t wdqlvl_patt[16];
- int8_t cacs_adj[16];
- int8_t dm_adj_w[SLICE_CNT];
- int8_t dq_adj_w[SLICE_CNT * 8];
- int8_t dm_adj_r[SLICE_CNT];
- int8_t dq_adj_r[SLICE_CNT * 8];
-};
-
-struct _boardcnf {
- uint8_t phyvalid;
- uint8_t dbi_en;
- uint16_t cacs_dly;
- int16_t cacs_dly_adj;
- uint16_t dqdm_dly_w;
- uint16_t dqdm_dly_r;
- struct _boardcnf_ch ch[DRAM_CH_CNT];
-};
-
-#define WDQLVL_PAT {\
- 0x00AA,\
- 0x0055,\
- 0x00AA,\
- 0x0155,\
- 0x01CC,\
- 0x0133,\
- 0x00CC,\
- 0x0033,\
- 0x00F0,\
- 0x010F,\
- 0x01F0,\
- 0x010F,\
- 0x00F0,\
- 0x00F0,\
- 0x000F,\
- 0x010F}
-
-static const struct _boardcnf boardcnfs[BOARDNUM] = {
- {
-/* boardcnf[0] RENESAS SALVATOR-X board with M3-W/SIP */
- .phyvalid = 0x03,
- .dbi_en = 0x01,
- .cacs_dly = 0x02c0,
- .cacs_dly_adj = 0,
- .dqdm_dly_w = 0x0300,
- .dqdm_dly_r = 0x00a0,
- .ch = {
- {
- {0x02, 0x02},
- 0x00543210U,
- 0x3201U,
- {0x70612543, 0x43251670, 0x45326170, 0x10672534},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
-
- {
- {0x02, 0x02},
- 0x00543210,
- 0x2310,
- {0x01327654, 0x34526107, 0x35421670, 0x70615324},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- },
-/* boardcnf[1] RENESAS KRIEK board with M3-W/SoC */
- {
- 0x03,
- 0x01,
- 0x2c0,
- 0,
- 0x300,
- 0x0a0,
- {
- {
- {0x02, 0x02},
- 0x00345201,
- 0x3201,
- {0x01672543, 0x45361207, 0x45632107, 0x60715234},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0x02},
- 0x00302154,
- 0x2310,
- {0x01672543, 0x45361207, 0x45632107, 0x60715234},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- },
-/* boardcnf[2] RENESAS SALVATOR-X board with H3 Ver.1.x/SIP(8Gbit 1rank) */
- {
- 0x0f,
- 0x00,
- 0x300,
- -320,
- 0x300,
- 0x0a0,
- {
- {
- {0x02, 0xff},
- 0x00543210,
- 0x3210,
- {0x20741365, 0x34256107, 0x57460321, 0x70614532},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0xff},
- 0x00543210,
- 0x3102,
- {0x23547610, 0x34526107, 0x67452310, 0x32106754},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0xff},
- 0x00543210,
- 0x0213,
- {0x30216754, 0x67453210, 0x70165243, 0x07162345},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0xff},
- 0x00543210,
- 0x0213,
- {0x01327654, 0x70615432, 0x54760123, 0x07162345},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- },
-/* boardcnf[3] RENESAS Starter Kit board with M3-W/SIP(8Gbit 1rank) */
- {
- 0x03,
- 0x01,
- 0x02c0,
- 0,
- 0x0300,
- 0x00a0,
- {
- {
- {0x02, 0xFF},
- 0x00543210U,
- 0x3201,
- {0x70612543, 0x43251670, 0x45326170, 0x10672534},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0xFF},
- 0x00543210,
- 0x2310,
- {0x01327654, 0x34526107, 0x35421670, 0x70615324},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- },
-/* boardcnf[4] RENESAS SALVATOR-M(1rank) board with H3 Ver.1.x/SoC */
- {
- 0x0f,
- 0x00,
- 0x2c0,
- -320,
- 0x300,
- 0x0a0,
- {
- {
- {0x02, 0xff},
- 0x00315024,
- 0x3120,
- {0x30671254, 0x26541037, 0x17054623, 0x12307645},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0xff},
- 0x00025143,
- 0x3210,
- {0x70613542, 0x16245307, 0x30712645, 0x21706354},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0xff},
- 0x00523104,
- 0x2301,
- {0x70613542, 0x16245307, 0x30712645, 0x21706354},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0xff},
- 0x00153402,
- 0x2031,
- {0x30671254, 0x26541037, 0x17054623, 0x12307645},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- },
-/* boardcnf[5] RENESAS KRIEK-1rank board with M3-W/SoC */
- {
- 0x03,
- 0x01,
- 0x2c0,
- 0,
- 0x300,
- 0x0a0,
- {
- {
- {0x02, 0xff},
- 0x00345201,
- 0x3201,
- {0x01672543, 0x45361207, 0x45632107, 0x60715234},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0xff},
- 0x00302154,
- 0x2310,
- {0x01672543, 0x45361207, 0x45632107, 0x60715234},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- },
-/* boardcnf[6] RENESAS SALVATOR-X board with H3 Ver.1.x/SIP(8Gbit 2rank) */
- {
- 0x0f,
- 0x00,
- 0x300,
- -320,
- 0x300,
- 0x0a0,
- {
- {
- {0x02, 0x02},
- 0x00543210,
- 0x3210,
- {0x20741365, 0x34256107, 0x57460321, 0x70614532},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0x02},
- 0x00543210,
- 0x3102,
- {0x23547610, 0x34526107, 0x67452310, 0x32106754},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0x02},
- 0x00543210,
- 0x0213,
- {0x30216754, 0x67453210, 0x70165243, 0x07162345},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0x02},
- 0x00543210,
- 0x0213,
- {0x01327654, 0x70615432, 0x54760123, 0x07162345},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- },
-/*
- * boardcnf[7] RENESAS SALVATOR-X board with
- * H3 Ver.2.0 or later/SIP(8Gbit 1rank)
- */
- {
- 0x0f,
- 0x01,
- 0x300,
- 0,
- 0x300,
- 0x0a0,
- {
- {
- {0x02, 0xff},
- 0x00543210,
- 0x2310,
- {0x70631425, 0x34527016, 0x43527610, 0x32104567},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0xff},
- 0x00105432,
- 0x3210,
- {0x43256107, 0x07162354, 0x10234567, 0x01235467},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0xff},
- 0x00543210,
- 0x2301,
- {0x01327654, 0x02316457, 0x10234567, 0x01325467},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0xff},
- 0x00543210,
- 0x2301,
- {0x12034765, 0x23105467, 0x23017645, 0x32106745},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- },
-/*
- * boardcnf[8] RENESAS SALVATOR-X board with
- * H3 Ver.2.0 or later/SIP(8Gbit 2rank)
- */
- {
-#if RCAR_DRAM_CHANNEL == 5
- 0x05,
-#else
- 0x0f,
-#endif
- 0x01,
- 0x300,
- 0,
- 0x300,
- 0x0a0,
- {
- {
- {0x02, 0x02},
- 0x00543210,
- 0x2310,
- {0x70631425, 0x34527016, 0x43527610, 0x32104567},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
-#if ((RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2))
- {
- {0x02, 0x02},
- 0x00543210,
- 0x2301,
- {0x01327654, 0x02316457, 0x10234567, 0x01325467},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
-#else
- {
- {0x02, 0x02},
- 0x00105432,
- 0x3210,
- {0x43256107, 0x07162354, 0x10234567, 0x01235467},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
-#endif
- {
- {0x02, 0x02},
- 0x00543210,
- 0x2301,
- {0x01327654, 0x02316457, 0x10234567, 0x01325467},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0x02},
- 0x00543210,
- 0x2301,
- {0x12034765, 0x23105467, 0x23017645, 0x32106745},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- },
-/* boardcnf[9] RENESAS SALVATOR-MS(1rank) board with H3 Ver.2.0 or later/SoC */
- {
- 0x0f,
- 0x01,
- 0x300,
- 0,
- 0x300,
- 0x0a0,
- {
- {
- {0x02, 0xff},
- 0x00543210,
- 0x3210,
- {0x27645310, 0x75346210, 0x53467210, 0x23674510},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0xff},
- 0x00543210,
- 0x2301,
- {0x23764510, 0x43257610, 0x43752610, 0x37652401},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {-128, -128, -128, -128, -128, -128, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0xff},
- 0x00452103,
- 0x3210,
- {0x32764510, 0x43257610, 0x43752610, 0x26573401},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0xff},
- 0x00520413,
- 0x2301,
- {0x47652301, 0x75346210, 0x53467210, 0x32674501},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {30, 30, 30, 30, 30, 30, 30, 30,
- 30, 30},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- },
-/* boardcnf[10] RENESAS Kriek(2rank) board with M3-N/SoC */
- {
- 0x01,
- 0x01,
- 0x300,
- 0,
- 0x300,
- 0x0a0,
- {
- {
- {0x02, 0x02},
- 0x00345201,
- 0x3201,
- {0x01672543, 0x45361207, 0x45632107, 0x60715234},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- },
-/* boardcnf[11] RENESAS SALVATOR-X board with M3-N/SIP(8Gbit 2rank) */
- {
- 0x01,
- 0x01,
- 0x300,
- 0,
- 0x300,
- 0x0a0,
- {
- {
-#if (RCAR_DRAM_LPDDR4_MEMCONF == 2)
- {0x04, 0x04},
-#else
- {0x02, 0x02},
-#endif
- 0x00342501,
- 0x3201,
- {0x10672534, 0x43257106, 0x34527601, 0x71605243},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- },
-/* boardcnf[12] RENESAS CONDOR board with V3H/SoC */
- {
- 0x01,
- 0x1,
- 0x300,
- 0,
- 0x300,
- 0x0a0,
- {
- {
- {0x02, 0x02},
- 0x00501342,
- 0x3201,
- {0x70562134, 0x34526071, 0x23147506, 0x12430567},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- },
-/* boardcnf[13] RENESAS KRIEK board with PM3/SoC */
- {
- 0x05,
- 0x00,
- 0x2c0,
- -320,
- 0x300,
- 0x0a0,
- {
- {
- {0x02, 0x02},
- 0x00345201,
- 0x3201,
- {0x01672543, 0x45361207, 0x45632107, 0x60715234},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0x02},
- 0x00302154,
- 0x2310,
- {0x01672543, 0x45361207, 0x45632107, 0x60715234},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0x02},
- 0x00302154,
- 0x2310,
- {0x01672543, 0x45361207, 0x45632107, 0x60715234},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0xff, 0xff},
- 0,
- 0,
- {0, 0, 0, 0},
- {0, 0, 0, 0},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- },
-/* boardcnf[14] SALVATOR-X board with H3 Ver.2.0 or later/SIP(16Gbit 1rank) */
- {
-#if RCAR_DRAM_CHANNEL == 5
- 0x05,
-#else
- 0x0f,
-#endif
- 0x01,
- 0x300,
- 0,
- 0x300,
- 0x0a0,
- {
- {
- {0x04, 0xff},
- 0x00543210,
- 0x2310,
- {0x70631425, 0x34527016, 0x43527610, 0x32104567},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
-#if ((RCAR_DRAM_CHANNEL == 5) && (RCAR_DRAM_SPLIT == 2))
- {
- {0x04, 0xff},
- 0x00543210,
- 0x2301,
- {0x01327654, 0x02316457, 0x10234567, 0x01325467},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
-#else
- {
- {0x04, 0xff},
- 0x00105432,
- 0x3210,
- {0x43256107, 0x07162354, 0x10234567, 0x01235467},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
-#endif
- {
- {0x04, 0xff},
- 0x00543210,
- 0x2301,
- {0x01327654, 0x02316457, 0x10234567, 0x01325467},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x04, 0xff},
- 0x00543210,
- 0x2301,
- {0x12034765, 0x23105467, 0x23017645, 0x32106745},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- },
-/* boardcnf[15] RENESAS KRIEK board with H3N */
- {
- 0x05,
- 0x01,
- 0x300,
- 0,
- 0x300,
- 0x0a0,
- {
- {
- {0x02, 0x02},
- 0x00345201,
- 0x3201,
- {0x01672543, 0x45367012, 0x45632107, 0x60715234},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0x02},
- 0x00302154,
- 0x2310,
- {0x01672543, 0x45361207, 0x45632107, 0x60715234},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0x02},
- 0x00302154,
- 0x2310,
- {0x01672543, 0x45361207, 0x45632107, 0x60715234},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0xff, 0xff},
- 0,
- 0,
- {0, 0, 0, 0},
- {0, 0, 0, 0},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- },
-/* boardcnf[16] RENESAS KRIEK-P2P board with M3-W/SoC */
- {
- 0x03,
- 0x01,
- 0x0320,
- 0,
- 0x0300,
- 0x00a0,
- {
- {
- {0x04, 0x04},
- 0x520314FFFF523041,
- 0x3201,
- {0x01672543, 0x45361207, 0x45632107, 0x60715234},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x04, 0x04},
- 0x314250FFFF312405,
- 0x2310,
- {0x01672543, 0x45361207, 0x45632107, 0x60715234},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- },
-/* boardcnf[17] RENESAS KRIEK-P2P board with M3-N/SoC */
- {
- 0x01,
- 0x01,
- 0x0300,
- 0,
- 0x0300,
- 0x00a0,
- {
- {
- {0x04, 0x04},
- 0x520314FFFF523041,
- 0x3201,
- {0x01672543, 0x45361207, 0x45632107, 0x60715234},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- },
-/* boardcnf[18] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 2rank) */
- {
- 0x03,
- 0x01,
- 0x02c0,
- 0,
- 0x0300,
- 0x00a0,
- {
- {
- {0x04, 0x04},
- 0x00543210,
- 0x3201,
- {0x70612543, 0x43251670, 0x45326170, 0x10672534},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x04, 0x04},
- 0x00543210,
- 0x2310,
- {0x01327654, 0x34526107, 0x35421670, 0x70615324},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- },
-/* boardcnf[19] RENESAS SALVATOR-X board with M3-W/SIP(16Gbit 1rank) */
- {
- 0x03,
- 0x01,
- 0x02c0,
- 0,
- 0x0300,
- 0x00a0,
- {
- {
- {0x04, 0xff},
- 0x00543210,
- 0x3201,
- {0x70612543, 0x43251670, 0x45326170, 0x10672534},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x04, 0xff},
- 0x00543210,
- 0x2310,
- {0x01327654, 0x34526107, 0x35421670, 0x70615324},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- },
-/* boardcnf[20] RENESAS KRIEK 16Gbit/2rank/2ch board with M3-W/SoC */
- {
- 0x03,
- 0x01,
- 0x02c0,
- 0,
- 0x0300,
- 0x00a0,
- {
- {
- {0x04, 0x04},
- 0x00345201,
- 0x3201,
- {0x01672543, 0x45361207, 0x45632107, 0x60715234},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x04, 0x04},
- 0x00302154,
- 0x2310,
- {0x01672543, 0x45361207, 0x45632107, 0x60715234},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- },
-/* boardcnf[21] RENESAS KRIEK 16Gbit/1rank/2ch board with M3-W/SoC */
- {
- 0x03,
- 0x01,
- 0x02c0,
- 0,
- 0x0300,
- 0x00a0,
- {
- {
- {0x04, 0xff},
- 0x00345201,
- 0x3201,
- {0x01672543, 0x45361207, 0x45632107, 0x60715234},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x04, 0xff},
- 0x00302154,
- 0x2310,
- {0x01672543, 0x45361207, 0x45632107, 0x60715234},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- }
-};
-
-void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div)
-{
- uint32_t md;
-
- if ((prr_product == PRR_PRODUCT_H3) && (prr_cut == PRR_PRODUCT_10)) {
- *clk = 50;
- *div = 3;
- } else {
- md = (mmio_read_32(RST_MODEMR) >> 13) & 0x3;
- switch (md) {
- case 0x0:
- *clk = 50;
- *div = 3;
- break;
- case 0x1:
- *clk = 60;
- *div = 3;
- break;
- case 0x2:
- *clk = 75;
- *div = 3;
- break;
- case 0x3:
- *clk = 100;
- *div = 3;
- break;
- }
- }
- (void)brd;
-}
-
-void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div)
-{
- uint32_t md;
-
- if (prr_product == PRR_PRODUCT_V3H) {
- md = (mmio_read_32(RST_MODEMR) >> 19) & 0x1;
- md = (md | (md << 1)) & 0x3; /* 0 or 3 */
- } else {
- md = (mmio_read_32(RST_MODEMR) >> 17) & 0x5;
- md = (md | (md >> 1)) & 0x3;
- }
- switch (md) {
- case 0x0:
- *mbps = 3200;
- *div = 1;
- break;
- case 0x1:
- *mbps = 2800;
- *div = 1;
- break;
- case 0x2:
- *mbps = 2400;
- *div = 1;
- break;
- case 0x3:
- *mbps = 1600;
- *div = 1;
- break;
- }
- (void)brd;
-}
-
-#define _def_REFPERIOD 1890
-
-#define M3_SAMPLE_TT_A84 0xB866CC10, 0x3B250421
-#define M3_SAMPLE_TT_A85 0xB866CC10, 0x3AA50421
-#define M3_SAMPLE_TT_A86 0xB866CC10, 0x3AA48421
-#define M3_SAMPLE_FF_B45 0xB866CC10, 0x3AB00C21
-#define M3_SAMPLE_FF_B49 0xB866CC10, 0x39B10C21
-#define M3_SAMPLE_FF_B56 0xB866CC10, 0x3AAF8C21
-#define M3_SAMPLE_SS_E24 0xB866CC10, 0x3BA39421
-#define M3_SAMPLE_SS_E28 0xB866CC10, 0x3C231421
-#define M3_SAMPLE_SS_E32 0xB866CC10, 0x3C241421
-
-static const uint32_t termcode_by_sample[20][3] = {
- {M3_SAMPLE_TT_A84, 0x000158D5},
- {M3_SAMPLE_TT_A85, 0x00015955},
- {M3_SAMPLE_TT_A86, 0x00015955},
- {M3_SAMPLE_FF_B45, 0x00015690},
- {M3_SAMPLE_FF_B49, 0x00015753},
- {M3_SAMPLE_FF_B56, 0x00015793},
- {M3_SAMPLE_SS_E24, 0x00015996},
- {M3_SAMPLE_SS_E28, 0x000159D7},
- {M3_SAMPLE_SS_E32, 0x00015997},
- {0xFFFFFFFF, 0xFFFFFFFF, 0x0001554F}
-};
-
-#ifdef BOARD_JUDGE_AUTO
-/*
- * SAMPLE board detect function
- */
-#define PFC_PMMR 0xE6060000U
-#define PFC_PUEN5 0xE6060414U
-#define PFC_PUEN6 0xE6060418U
-#define PFC_PUD5 0xE6060454U
-#define PFC_PUD6 0xE6060458U
-#define GPIO_INDT5 0xE605500CU
-#define GPIO_GPSR6 0xE6060118U
-
-#if (RCAR_GEN3_ULCB == 0)
-static void pfc_write_and_poll(uint32_t a, uint32_t v)
-{
- mmio_write_32(PFC_PMMR, ~v);
- v = ~mmio_read_32(PFC_PMMR);
- mmio_write_32(a, v);
- while (v != mmio_read_32(a))
- ;
- dsb_sev();
-}
-#endif
-
-#ifndef RCAR_GEN3_ULCB
-#define RCAR_GEN3_ULCB 0
-#endif
-
-#if (RCAR_GEN3_ULCB == 0) /* non Starter Kit */
-
-static uint32_t opencheck_SSI_WS6(void)
-{
- uint32_t dataL, down, up;
- uint32_t gpsr6_bak;
- uint32_t puen5_bak;
- uint32_t pud5_bak;
-
- gpsr6_bak = mmio_read_32(GPIO_GPSR6);
- puen5_bak = mmio_read_32(PFC_PUEN5);
- pud5_bak = mmio_read_32(PFC_PUD5);
- dsb_sev();
-
- dataL = (gpsr6_bak & ~BIT(15));
- pfc_write_and_poll(GPIO_GPSR6, dataL);
-
- /* Pull-Up/Down Enable (PUEN5[22]=1) */
- dataL = puen5_bak;
- dataL |= (BIT(22));
- pfc_write_and_poll(PFC_PUEN5, dataL);
-
- /* Pull-Down-Enable (PUD5[22]=0, PUEN5[22]=1) */
- dataL = pud5_bak;
- dataL &= ~(BIT(22));
- pfc_write_and_poll(PFC_PUD5, dataL);
- /* GPSR6[15]=SSI_WS6 */
- rcar_micro_delay(10);
- down = (mmio_read_32(GPIO_INDT6) >> 15) & 0x1;
- dsb_sev();
-
- /* Pull-Up-Enable (PUD5[22]=1, PUEN5[22]=1) */
- dataL = pud5_bak;
- dataL |= (BIT(22));
- pfc_write_and_poll(PFC_PUD5, dataL);
-
- /* GPSR6[15]=SSI_WS6 */
- rcar_micro_delay(10);
- up = (mmio_read_32(GPIO_INDT6) >> 15) & 0x1;
-
- dsb_sev();
-
- pfc_write_and_poll(GPIO_GPSR6, gpsr6_bak);
- pfc_write_and_poll(PFC_PUEN5, puen5_bak);
- pfc_write_and_poll(PFC_PUD5, pud5_bak);
-
- if (down == up) {
- /* Same = Connect */
- return 0;
- }
-
- /* Diff = Open */
- return 1;
-}
-
-#endif
-
-static uint32_t _board_judge(void)
-{
- uint32_t brd;
-#if (RCAR_GEN3_ULCB == 1)
- /* Starter Kit */
- if (prr_product == PRR_PRODUCT_H3) {
- if (prr_cut <= PRR_PRODUCT_11) {
- /* RENESAS Starter Kit(H3 Ver.1.x/SIP) board */
- brd = 2;
- } else {
- /* RENESAS Starter Kit(H3 Ver.2.0 or later/SIP) board */
-#if (RCAR_DRAM_LPDDR4_MEMCONF == 0)
- brd = 7;
-#else
- brd = 8;
-#endif
- }
- } else if (prr_product == PRR_PRODUCT_M3) {
- if (prr_cut >= PRR_PRODUCT_30) {
- /* RENESAS Starter Kit (M3-W Ver.3.0/SIP) */
- brd = 18;
- } else {
- /* RENESAS Starter Kit(M3-W/SIP 8Gbit 1rank) board */
- brd = 3;
- }
- } else {
- /* RENESAS Starter Kit(M3-N/SIP) board */
- brd = 11;
- }
-#else
- uint32_t usb2_ovc_open;
-
- usb2_ovc_open = opencheck_SSI_WS6();
-
- /* RENESAS Eva-board */
- brd = 99;
- if (prr_product == PRR_PRODUCT_V3H) {
- /* RENESAS Condor board */
- brd = 12;
- } else if (usb2_ovc_open) {
- if (prr_product == PRR_PRODUCT_M3N) {
- /* RENESAS Kriek board with M3-N */
- brd = 10;
- } else if (prr_product == PRR_PRODUCT_M3) {
- /* RENESAS Kriek board with M3-W */
- brd = 1;
- } else if ((prr_product == PRR_PRODUCT_H3) &&
- (prr_cut <= PRR_PRODUCT_11)) {
- /* RENESAS Kriek board with PM3 */
- brd = 13;
- } else if ((prr_product == PRR_PRODUCT_H3) &&
- (prr_cut > PRR_PRODUCT_20)) {
- /* RENESAS Kriek board with H3N */
- brd = 15;
- }
- } else {
- if (prr_product == PRR_PRODUCT_H3) {
- if (prr_cut <= PRR_PRODUCT_11) {
- /* RENESAS SALVATOR-X (H3 Ver.1.x/SIP) */
- brd = 2;
- } else if (prr_cut < PRR_PRODUCT_30) {
- /* RENESAS SALVATOR-X (H3 Ver.2.0/SIP) */
- brd = 7; // 8Gbit/1rank
- } else {
- /* RENESAS SALVATOR-X (H3 Ver.3.0/SIP) */
-#if (RCAR_DRAM_LPDDR4_MEMCONF == 0)
- brd = 7;
-#else
- brd = 8;
-#endif
- }
- } else if (prr_product == PRR_PRODUCT_M3N) {
- /* RENESAS SALVATOR-X (M3-N/SIP) */
- brd = 11;
- } else if ((prr_product == PRR_PRODUCT_M3) &&
- (prr_cut <= PRR_PRODUCT_20)) {
- /* RENESAS SALVATOR-X (M3-W/SIP) */
- brd = 0;
- } else if ((prr_product == PRR_PRODUCT_M3) &&
- (prr_cut < PRR_PRODUCT_30)) {
- /* RENESAS SALVATOR-X (M3-W Ver.1.x/SIP) */
- brd = 19;
- } else if ((prr_product == PRR_PRODUCT_M3) &&
- (prr_cut >= PRR_PRODUCT_30)) {
- /* RENESAS SALVATOR-X (M3-W ver.3.0/SIP) */
- brd = 18;
- }
- }
-#endif
-
- return brd;
-}
-#endif
diff --git a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
deleted file mode 100644
index 56363eb..0000000
--- a/drivers/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation.
- * All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#define RCAR_DDR_VERSION "rev.0.40"
-#define DRAM_CH_CNT 0x04
-#define SLICE_CNT 0x04
-#define CS_CNT 0x02
-
-/* order : CS0A, CS0B, CS1A, CS1B */
-#define CSAB_CNT (CS_CNT * 2)
-
-/* order : CH0A, CH0B, CH1A, CH1B, CH2A, CH2B, CH3A, CH3B */
-#define CHAB_CNT (DRAM_CH_CNT * 2)
-
-/* pll setting */
-#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
-#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb)))
-
-/* for ddr deisity setting */
-#define DBMEMCONF_REG(d3, row, bank, col, dw) \
- (((d3) << 30) | ((row) << 24) | ((bank) << 16) | ((col) << 8) | (dw))
-
-#define DBMEMCONF_REGD(density) \
- (DBMEMCONF_REG((density) % 2, ((density) + 1) / \
- 2 + (29 - 3 - 10 - 2), 3, 10, 2))
-
-#define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs)))
-
-/* refresh mode */
-#define DBSC_REFINTS (0x0)
-
-/* system registers */
-#define CPG_FRQCRB (CPG_BASE + 0x0004U)
-
-#define CPG_PLLECR (CPG_BASE + 0x00D0U)
-#define CPG_MSTPSR5 (CPG_BASE + 0x003CU)
-#define CPG_SRCR4 (CPG_BASE + 0x00BCU)
-#define CPG_PLL3CR (CPG_BASE + 0x00DCU)
-#define CPG_ZB3CKCR (CPG_BASE + 0x0380U)
-#define CPG_FRQCRD (CPG_BASE + 0x00E4U)
-#define CPG_SMSTPCR5 (CPG_BASE + 0x0144U)
-#define CPG_CPGWPR (CPG_BASE + 0x0900U)
-#define CPG_SRSTCLR4 (CPG_BASE + 0x0950U)
-
-#define CPG_FRQCRB_KICK_BIT BIT(31)
-#define CPG_PLLECR_PLL3E_BIT BIT(3)
-#define CPG_PLLECR_PLL3ST_BIT BIT(11)
-#define CPG_ZB3CKCR_ZB3ST_BIT BIT(11)
-
-#define RST_BASE (0xE6160000U)
-#define RST_MODEMR (RST_BASE + 0x0060U)
-
-#define LIFEC_CHIPID(x) (0xE6110040U + 0x04U * (x))
-
-/* DBSC registers */
-#include "../ddr_regs.h"
-
-#define DBSC_DBMONCONF4 0xE6793010U
-
-#define DBSC_PLL_LOCK(ch) (0xE6794054U + 0x100U * (ch))
-#define DBSC_PLL_LOCK_0 0xE6794054U
-#define DBSC_PLL_LOCK_1 0xE6794154U
-#define DBSC_PLL_LOCK_2 0xE6794254U
-#define DBSC_PLL_LOCK_3 0xE6794354U
-
-/* STAT registers */
-#define MSTAT_SL_INIT 0xE67E8000U
-#define MSTAT_REF_ARS 0xE67E8004U
-#define MSTATQ_STATQC 0xE67E8008U
-#define MSTATQ_WTENABLE 0xE67E8030U
-#define MSTATQ_WTREFRESH 0xE67E8034U
-#define MSTATQ_WTSETTING0 0xE67E8038U
-#define MSTATQ_WTSETTING1 0xE67E803CU
-
-#define QOS_BASE1 (0xE67F0000U)
-#define QOSCTRL_RAS (QOS_BASE1 + 0x0000U)
-#define QOSCTRL_FIXTH (QOS_BASE1 + 0x0004U)
-#define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U)
-#define QOSCTRL_REGGD (QOS_BASE1 + 0x0020U)
-#define QOSCTRL_DANN (QOS_BASE1 + 0x0030U)
-#define QOSCTRL_DANT (QOS_BASE1 + 0x0038U)
-#define QOSCTRL_EC (QOS_BASE1 + 0x003CU)
-#define QOSCTRL_EMS (QOS_BASE1 + 0x0040U)
-#define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U)
-#define QOSCTRL_BERR (QOS_BASE1 + 0x0054U)
-#define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U)
-#define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U)
-
-/* other module */
-#define THS1_THCTR 0xE6198020U
-#define THS1_TEMP 0xE6198028U
diff --git a/drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk b/drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk
deleted file mode 100644
index 2bcc292..0000000
--- a/drivers/renesas/rcar/ddr/ddr_b/ddr_b.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-BL2_SOURCES += drivers/renesas/rcar/ddr/ddr_b/boot_init_dram.c
diff --git a/drivers/renesas/rzg/board/board.c b/drivers/renesas/rzg/board/board.c
index cfbb047..7636372 100644
--- a/drivers/renesas/rzg/board/board.c
+++ b/drivers/renesas/rzg/board/board.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,7 +13,15 @@
#include "rcar_def.h"
#ifndef BOARD_DEFAULT
+#if (RCAR_LSI == RZ_G2H)
+#define BOARD_DEFAULT (BOARD_HIHOPE_RZ_G2H << BOARD_CODE_SHIFT)
+#elif (RCAR_LSI == RZ_G2N)
+#define BOARD_DEFAULT (BOARD_HIHOPE_RZ_G2N << BOARD_CODE_SHIFT)
+#elif (RCAR_LSI == RZ_G2E)
+#define BOARD_DEFAULT (BOARD_EK874_RZ_G2E << BOARD_CODE_SHIFT)
+#else
#define BOARD_DEFAULT (BOARD_HIHOPE_RZ_G2M << BOARD_CODE_SHIFT)
+#endif /* RCAR_LSI == RZ_G2H */
#endif /* BOARD_DEFAULT */
#define BOARD_CODE_MASK (0xF8U)
@@ -27,9 +35,15 @@
#define GP5_25_BIT (0x01U << 25)
#define HM_ID { 0x10U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
+#define HH_ID HM_ID
+#define HN_ID { 0x20U, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU }
+#define EK_ID HM_ID
const char *g_board_tbl[] = {
[BOARD_HIHOPE_RZ_G2M] = "HiHope RZ/G2M",
+ [BOARD_HIHOPE_RZ_G2H] = "HiHope RZ/G2H",
+ [BOARD_HIHOPE_RZ_G2N] = "HiHope RZ/G2N",
+ [BOARD_EK874_RZ_G2E] = "EK874 RZ/G2E",
[BOARD_UNKNOWN] = "unknown"
};
@@ -38,8 +52,14 @@
static uint8_t board_id = BOARD_ID_UNKNOWN;
const uint8_t board_tbl[][8] = {
[BOARD_HIHOPE_RZ_G2M] = HM_ID,
+ [BOARD_HIHOPE_RZ_G2H] = HH_ID,
+ [BOARD_HIHOPE_RZ_G2N] = HN_ID,
+ [BOARD_EK874_RZ_G2E] = EK_ID,
};
- uint32_t reg, boardInfo;
+ uint32_t reg;
+#if (RCAR_LSI != RZ_G2E)
+ uint32_t boardInfo;
+#endif /* RCAR_LSI == RZ_G2E */
if (board_id == BOARD_ID_UNKNOWN) {
board_id = BOARD_DEFAULT;
@@ -50,15 +70,28 @@
if (*type >= ARRAY_SIZE(board_tbl)) {
/* no revision information, set Rev0.0. */
*rev = 0;
+ return;
+ }
+
+ reg = mmio_read_32(RCAR_PRR);
+#if (RCAR_LSI == RZ_G2E)
+ if (reg & RCAR_MINOR_MASK) {
+ *rev = 0x30U;
} else {
- reg = mmio_read_32(RCAR_PRR);
- if ((reg & PRR_CUT_MASK) == RCAR_M3_CUT_VER11) {
+ *rev = board_tbl[*type][(uint8_t)(board_id & BOARD_REV_MASK)];
+ }
+#else
+ if ((reg & PRR_CUT_MASK) == RCAR_M3_CUT_VER11) {
+ *rev = board_tbl[*type][(uint8_t)(board_id & BOARD_REV_MASK)];
+ } else {
+ reg = mmio_read_32(GPIO_INDT5);
+ if (reg & GP5_25_BIT) {
*rev = board_tbl[*type][(uint8_t)(board_id & BOARD_REV_MASK)];
} else {
- boardInfo = mmio_read_32(GPIO_INDT5) &
- (GP5_19_BIT | GP5_21_BIT);
+ boardInfo = reg & (GP5_19_BIT | GP5_21_BIT);
*rev = (((boardInfo & GP5_19_BIT) >> 14) |
((boardInfo & GP5_21_BIT) >> 17)) + 0x30U;
}
}
+#endif /* RCAR_LSI == RZ_G2E */
}
diff --git a/drivers/renesas/rzg/board/board.h b/drivers/renesas/rzg/board/board.h
index c0c3d0c..1a76849 100644
--- a/drivers/renesas/rzg/board/board.h
+++ b/drivers/renesas/rzg/board/board.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,6 +9,9 @@
enum rzg2_board_id {
BOARD_HIHOPE_RZ_G2M = 0,
+ BOARD_HIHOPE_RZ_G2H,
+ BOARD_HIHOPE_RZ_G2N,
+ BOARD_EK874_RZ_G2E,
BOARD_UNKNOWN
};
diff --git a/drivers/renesas/rzg/ddr/boot_init_dram.h b/drivers/renesas/rzg/ddr/boot_init_dram.h
deleted file mode 100644
index 294582f..0000000
--- a/drivers/renesas/rzg/ddr/boot_init_dram.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef BOOT_INIT_DRAM_H
-#define BOOT_INIT_DRAM_H
-
-extern int32_t rzg_dram_init(void);
-
-#define INITDRAM_OK 0
-#define INITDRAM_NG 0xffffffff
-#define INITDRAM_ERR_I 0xffffffff
-#define INITDRAM_ERR_O 0xfffffffe
-#define INITDRAM_ERR_T 0xfffffff0
-
-#endif /* BOOT_INIT_DRAM_H */
diff --git a/drivers/renesas/rzg/ddr/ddr.mk b/drivers/renesas/rzg/ddr/ddr.mk
deleted file mode 100644
index 7558216..0000000
--- a/drivers/renesas/rzg/ddr/ddr.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-include drivers/renesas/rzg/ddr/ddr_b/ddr_b.mk
diff --git a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram.c b/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram.c
deleted file mode 100644
index 45259e3..0000000
--- a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram.c
+++ /dev/null
@@ -1,3700 +0,0 @@
-/*
- * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stdint.h>
-#include <string.h>
-
-#include <common/debug.h>
-#include <lib/mmio.h>
-
-#include "boot_init_dram.h"
-#include "boot_init_dram_regdef.h"
-#include "ddr_regdef.h"
-#include "dram_sub_func.h"
-#include "init_dram_tbl_g2m.h"
-#include "micro_delay.h"
-#include "rcar_def.h"
-
-/* load board configuration */
-#include "boot_init_dram_config.c"
-
-#define DDR_BACKUPMODE
-#define FATAL_MSG(x) NOTICE(x)
-
-/* variables */
-#ifdef RCAR_DDR_FIXED_LSI_TYPE
-#ifndef RCAR_AUTO
-#define RCAR_AUTO 99U
-#define RZ_G2M 100U
-
-#define RCAR_CUT_10 0U
-#define RCAR_CUT_11 1U
-#define RCAR_CUT_20 10U
-#define RCAR_CUT_30 20U
-#endif /* RCAR_AUTO */
-#ifndef RCAR_LSI
-#define RCAR_LSI RCAR_AUTO
-#endif
-
-#if (RCAR_LSI == RCAR_AUTO)
-static uint32_t prr_product;
-static uint32_t prr_cut;
-#else /* RCAR_LSI == RCAR_AUTO */
-#if (RCAR_LSI == RZ_G2M)
-static const uint32_t prr_product = PRR_PRODUCT_M3;
-#endif /* RCAR_LSI == RZ_G2M */
-
-#ifndef RCAR_LSI_CUT
-static uint32_t prr_cut;
-#else /* RCAR_LSI_CUT */
-#if (RCAR_LSI_CUT == RCAR_CUT_10)
-static const uint32_t prr_cut = PRR_PRODUCT_10;
-#elif(RCAR_LSI_CUT == RCAR_CUT_11)
-static const uint32_t prr_cut = PRR_PRODUCT_11;
-#elif(RCAR_LSI_CUT == RCAR_CUT_20)
-static const uint32_t prr_cut = PRR_PRODUCT_20;
-#elif(RCAR_LSI_CUT == RCAR_CUT_30)
-static const uint32_t prr_cut = PRR_PRODUCT_30;
-#endif /* RCAR_LSI_CUT == RCAR_CUT_10 */
-#endif /* RCAR_LSI_CUT */
-#endif /* RCAR_LSI == RCAR_AUTO */
-#else /* RCAR_DDR_FIXED_LSI_TYPE */
-static uint32_t prr_product;
-static uint32_t prr_cut;
-#endif /* RCAR_DDR_FIXED_LSI_TYPE */
-
-static const uint32_t *p_ddr_regdef_tbl;
-static uint32_t brd_clk;
-static uint32_t brd_clkdiv;
-static uint32_t brd_clkdiva;
-static uint32_t ddr_mbps;
-static uint32_t ddr_mbpsdiv;
-static uint32_t ddr_tccd;
-static uint32_t ddr_phycaslice;
-static const struct _boardcnf *board_cnf;
-static uint32_t ddr_phyvalid;
-static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT];
-static uint32_t ch_have_this_cs[CS_CNT] __aligned(64);
-static uint32_t rdqdm_dly[DRAM_CH_CNT][CSAB_CNT][SLICE_CNT * 2U][9U];
-static uint32_t max_density;
-static uint32_t ddr0800_mul;
-static uint32_t ddr_mul;
-static uint32_t DDR_PHY_SLICE_REGSET_OFS;
-static uint32_t DDR_PHY_ADR_V_REGSET_OFS;
-static uint32_t DDR_PHY_ADR_I_REGSET_OFS;
-static uint32_t DDR_PHY_ADR_G_REGSET_OFS;
-static uint32_t DDR_PI_REGSET_OFS;
-static uint32_t DDR_PHY_SLICE_REGSET_SIZE;
-static uint32_t DDR_PHY_ADR_V_REGSET_SIZE;
-static uint32_t DDR_PHY_ADR_I_REGSET_SIZE;
-static uint32_t DDR_PHY_ADR_G_REGSET_SIZE;
-static uint32_t DDR_PI_REGSET_SIZE;
-static uint32_t DDR_PHY_SLICE_REGSET_NUM;
-static uint32_t DDR_PHY_ADR_V_REGSET_NUM;
-static uint32_t DDR_PHY_ADR_I_REGSET_NUM;
-static uint32_t DDR_PHY_ADR_G_REGSET_NUM;
-static uint32_t DDR_PI_REGSET_NUM;
-static uint32_t DDR_PHY_ADR_I_NUM;
-#define DDR_PHY_REGSET_MAX 128
-#define DDR_PI_REGSET_MAX 320
-static uint32_t _cnf_DDR_PHY_SLICE_REGSET[DDR_PHY_REGSET_MAX];
-static uint32_t _cnf_DDR_PHY_ADR_V_REGSET[DDR_PHY_REGSET_MAX];
-static uint32_t _cnf_DDR_PHY_ADR_I_REGSET[DDR_PHY_REGSET_MAX];
-static uint32_t _cnf_DDR_PHY_ADR_G_REGSET[DDR_PHY_REGSET_MAX];
-static uint32_t _cnf_DDR_PI_REGSET[DDR_PI_REGSET_MAX];
-static uint32_t pll3_mode;
-static uint32_t loop_max;
-#ifdef DDR_BACKUPMODE
-uint32_t ddr_backup = DRAM_BOOT_STATUS_COLD;
-/* #define DDR_BACKUPMODE_HALF */ /* for Half channel(ch0,1 only) */
-#endif
-
-#ifdef DDR_QOS_INIT_SETTING /* only for non qos_init */
-#define OPERATING_FREQ (400U) /* Mhz */
-#define BASE_SUB_SLOT_NUM (0x6U)
-#define SUB_SLOT_CYCLE (0x7EU) /* 126 */
-#define QOSWT_WTSET0_CYCLE \
- ((SUB_SLOT_CYCLE * BASE_SUB_SLOT_NUM * 1000U) / \
- OPERATING_FREQ) /* unit:ns */
-
-uint32_t get_refperiod(void)
-{
- return QOSWT_WTSET0_CYCLE;
-}
-#else /* DDR_QOS_INIT_SETTING */
-extern uint32_t get_refperiod(void);
-#endif /* DDR_QOS_INIT_SETTING */
-
-#define _reg_PHY_RX_CAL_X_NUM 11U
-static const uint32_t _reg_PHY_RX_CAL_X[_reg_PHY_RX_CAL_X_NUM] = {
- _reg_PHY_RX_CAL_DQ0,
- _reg_PHY_RX_CAL_DQ1,
- _reg_PHY_RX_CAL_DQ2,
- _reg_PHY_RX_CAL_DQ3,
- _reg_PHY_RX_CAL_DQ4,
- _reg_PHY_RX_CAL_DQ5,
- _reg_PHY_RX_CAL_DQ6,
- _reg_PHY_RX_CAL_DQ7,
- _reg_PHY_RX_CAL_DM,
- _reg_PHY_RX_CAL_DQS,
- _reg_PHY_RX_CAL_FDBK
-};
-
-#define _reg_PHY_CLK_WRX_SLAVE_DELAY_NUM 10U
-static const uint32_t _reg_PHY_CLK_WRX_SLAVE_DELAY
- [_reg_PHY_CLK_WRX_SLAVE_DELAY_NUM] = {
- _reg_PHY_CLK_WRDQ0_SLAVE_DELAY,
- _reg_PHY_CLK_WRDQ1_SLAVE_DELAY,
- _reg_PHY_CLK_WRDQ2_SLAVE_DELAY,
- _reg_PHY_CLK_WRDQ3_SLAVE_DELAY,
- _reg_PHY_CLK_WRDQ4_SLAVE_DELAY,
- _reg_PHY_CLK_WRDQ5_SLAVE_DELAY,
- _reg_PHY_CLK_WRDQ6_SLAVE_DELAY,
- _reg_PHY_CLK_WRDQ7_SLAVE_DELAY,
- _reg_PHY_CLK_WRDM_SLAVE_DELAY,
- _reg_PHY_CLK_WRDQS_SLAVE_DELAY
-};
-
-#define _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM 9U
-static const uint32_t _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY
- [_reg_PHY_RDDQS_X_FALL_SLAVE_DELAY_NUM] = {
- _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY,
- _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY
-};
-
-#define _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM 9U
-static const uint32_t _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY
- [_reg_PHY_RDDQS_X_RISE_SLAVE_DELAY_NUM] = {
- _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY,
- _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY,
- _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY
-};
-
-#define _reg_PHY_PAD_TERM_X_NUM 8U
-static const uint32_t _reg_PHY_PAD_TERM_X[_reg_PHY_PAD_TERM_X_NUM] = {
- _reg_PHY_PAD_FDBK_TERM,
- _reg_PHY_PAD_DATA_TERM,
- _reg_PHY_PAD_DQS_TERM,
- _reg_PHY_PAD_ADDR_TERM,
- _reg_PHY_PAD_CLK_TERM,
- _reg_PHY_PAD_CKE_TERM,
- _reg_PHY_PAD_RST_TERM,
- _reg_PHY_PAD_CS_TERM
-};
-
-#define _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM 10U
-static const uint32_t _reg_PHY_CLK_CACS_SLAVE_DELAY_X
- [_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM] = {
- _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY,
- _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY,
- _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY,
- _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY,
- _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY,
- _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY,
-
- _reg_PHY_GRP_SLAVE_DELAY_0,
- _reg_PHY_GRP_SLAVE_DELAY_1,
- _reg_PHY_GRP_SLAVE_DELAY_2,
- _reg_PHY_GRP_SLAVE_DELAY_3
-};
-
-/* Prototypes */
-static inline uint32_t vch_nxt(uint32_t pos);
-static void cpg_write_32(uint32_t a, uint32_t v);
-static void pll3_control(uint32_t high);
-static inline void dsb_sev(void);
-static void wait_dbcmd(void);
-static void send_dbcmd(uint32_t cmd);
-static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd);
-static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata);
-static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata);
-static inline uint32_t ddr_regdef(uint32_t _regdef);
-static inline uint32_t ddr_regdef_adr(uint32_t _regdef);
-static inline uint32_t ddr_regdef_lsb(uint32_t _regdef);
-static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
- uint32_t val);
-static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef);
-static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val);
-static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val);
-static void ddr_setval_ach(uint32_t regdef, uint32_t val);
-static void ddr_setval_ach_as(uint32_t regdef, uint32_t val);
-static uint32_t ddr_getval(uint32_t ch, uint32_t regdef);
-static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p);
-static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p);
-static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size);
-static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val);
-static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef);
-static uint32_t ddrphy_regif_chk(void);
-static inline void ddrphy_regif_idle(void);
-static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps,
- uint16_t cyc);
-static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv,
- uint16_t *_js2);
-static int16_t _f_scale_adj(int16_t ps);
-static void ddrtbl_load(void);
-static void ddr_config_sub(void);
-static void ddr_config(void);
-static void dbsc_regset(void);
-static void dbsc_regset_post(void);
-static uint32_t dfi_init_start(void);
-static void change_lpddr4_en(uint32_t mode);
-static uint32_t set_term_code(void);
-static void ddr_register_set(void);
-static inline uint32_t wait_freqchgreq(uint32_t assert);
-static inline void set_freqchgack(uint32_t assert);
-static inline void set_dfifrequency(uint32_t freq);
-static uint32_t pll3_freq(uint32_t on);
-static void update_dly(void);
-static uint32_t pi_training_go(void);
-static uint32_t init_ddr(void);
-static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick);
-static uint32_t wdqdm_man1(void);
-static uint32_t wdqdm_man(void);
-static uint32_t rdqdm_man1(void);
-static uint32_t rdqdm_man(void);
-
-static int32_t _find_change(uint64_t val, uint32_t dir);
-static uint32_t _rx_offset_cal_updn(uint32_t code);
-static uint32_t rx_offset_cal(void);
-static uint32_t rx_offset_cal_hw(void);
-static void adjust_wpath_latency(void);
-
-struct ddrt_data {
- int32_t init_temp; /* Initial Temperature (do) */
- uint32_t init_cal[4U]; /* Initial io-code (4 is for G2H) */
- uint32_t tcomp_cal[4U]; /* Temp. compensated io-code (4 is for G2H) */
-};
-
-static struct ddrt_data tcal;
-
-static void pvtcode_update(void);
-static void pvtcode_update2(void);
-static void ddr_padcal_tcompensate_getinit(uint32_t override);
-
-#ifndef DDR_FAST_INIT
-static uint32_t rdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2U][9U];
-static uint32_t rdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2U][9U];
-static uint32_t rdqdm_nw[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2U][9U];
-static uint32_t rdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
-static uint32_t rdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2U];
-static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
-static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
-
-static uint32_t wdqdm_le[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9U];
-static uint32_t wdqdm_te[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9U];
-static uint32_t wdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT][9U];
-static uint32_t wdqdm_st[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
-static uint32_t wdqdm_win[DRAM_CH_CNT][CS_CNT][SLICE_CNT];
-static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn);
-static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
-#endif/* DDR_FAST_INIT */
-
-/* macro for channel selection loop */
-static inline uint32_t vch_nxt(uint32_t pos)
-{
- uint32_t posn;
-
- for (posn = pos; posn < DRAM_CH_CNT; posn++) {
- if ((ddr_phyvalid & (1U << posn)) != 0U) {
- break;
- }
- }
- return posn;
-}
-
-#define foreach_vch(ch) \
-for (ch = vch_nxt(0U); ch < DRAM_CH_CNT; ch = vch_nxt(ch + 1U))
-
-#define foreach_ech(ch) \
-for (ch = 0U; ch < DRAM_CH_CNT; ch++)
-
-/* Printing functions */
-#define MSG_LF(...)
-
-/* clock settings, reset control */
-static void cpg_write_32(uint32_t a, uint32_t v)
-{
- mmio_write_32(CPG_CPGWPR, ~v);
- mmio_write_32(a, v);
-}
-
-static void wait_for_pll3_status_bit_turned_on(void)
-{
- uint32_t data_l;
-
- do {
- data_l = mmio_read_32(CPG_PLLECR);
- } while ((data_l & CPG_PLLECR_PLL3ST_BIT) == 0);
- dsb_sev();
-}
-
-static void pll3_control(uint32_t high)
-{
- uint32_t data_l, data_div, data_mul, tmp_div;
-
- if (high != 0U) {
- tmp_div = 3999U * brd_clkdiv * (brd_clkdiva + 1U) /
- (brd_clk * ddr_mul) / 2U;
- data_mul = ((ddr_mul * tmp_div) - 1U) << 24U;
- pll3_mode = 1U;
- loop_max = 2U;
- } else {
- tmp_div = 3999U * brd_clkdiv * (brd_clkdiva + 1U) /
- (brd_clk * ddr0800_mul) / 2U;
- data_mul = ((ddr0800_mul * tmp_div) - 1U) << 24U;
- pll3_mode = 0U;
- loop_max = 8U;
- }
-
- switch (tmp_div) {
- case 1:
- data_div = 0U;
- break;
- case 2:
- case 3:
- case 4:
- data_div = tmp_div;
- break;
- default:
- data_div = 6U;
- data_mul = (data_mul * tmp_div) / 3U;
- break;
- }
- data_mul = data_mul | (brd_clkdiva << 7);
-
- /* PLL3 disable */
- data_l = mmio_read_32(CPG_PLLECR) & ~CPG_PLLECR_PLL3E_BIT;
- cpg_write_32(CPG_PLLECR, data_l);
- dsb_sev();
-
- if (prr_product == PRR_PRODUCT_M3) {
- /* PLL3 DIV resetting(Lowest value:3) */
- data_l = 0x00030003U | (0xFF80FF80U & mmio_read_32(CPG_FRQCRD));
- cpg_write_32(CPG_FRQCRD, data_l);
- dsb_sev();
-
- /* zb3 clk stop */
- data_l = CPG_ZB3CKCR_ZB3ST_BIT | mmio_read_32(CPG_ZB3CKCR);
- cpg_write_32(CPG_ZB3CKCR, data_l);
- dsb_sev();
-
- /* PLL3 enable */
- data_l = CPG_PLLECR_PLL3E_BIT | mmio_read_32(CPG_PLLECR);
- cpg_write_32(CPG_PLLECR, data_l);
- dsb_sev();
-
- wait_for_pll3_status_bit_turned_on();
-
- /* PLL3 DIV resetting (Highest value:0) */
- data_l = (0xFF80FF80U & mmio_read_32(CPG_FRQCRD));
- cpg_write_32(CPG_FRQCRD, data_l);
- dsb_sev();
-
- /* DIV SET KICK */
- data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
- cpg_write_32(CPG_FRQCRB, data_l);
- dsb_sev();
-
- /* PLL3 multiplier set */
- cpg_write_32(CPG_PLL3CR, data_mul);
- dsb_sev();
-
- wait_for_pll3_status_bit_turned_on();
-
- /* PLL3 DIV resetting(Target value) */
- data_l = (data_div << 16U) | data_div |
- (mmio_read_32(CPG_FRQCRD) & 0xFF80FF80U);
- cpg_write_32(CPG_FRQCRD, data_l);
- dsb_sev();
-
- /* DIV SET KICK */
- data_l = CPG_FRQCRB_KICK_BIT | mmio_read_32(CPG_FRQCRB);
- cpg_write_32(CPG_FRQCRB, data_l);
- dsb_sev();
-
- wait_for_pll3_status_bit_turned_on();
-
- /* zb3 clk start */
- data_l = (~CPG_ZB3CKCR_ZB3ST_BIT) & mmio_read_32(CPG_ZB3CKCR);
- cpg_write_32(CPG_ZB3CKCR, data_l);
- dsb_sev();
- }
-}
-
-/* barrier */
-static inline void dsb_sev(void)
-{
- __asm__ __volatile__("dsb sy");
-}
-
-/* DDR memory register access */
-static void wait_dbcmd(void)
-{
- uint32_t data_l;
- /* dummy read */
- data_l = mmio_read_32(DBSC_DBCMD);
- dsb_sev();
- while (true) {
- /* wait DBCMD 1=busy, 0=ready */
- data_l = mmio_read_32(DBSC_DBWAIT);
- dsb_sev();
- if ((data_l & 0x00000001U) == 0x00U) {
- break;
- }
- }
-}
-
-static void send_dbcmd(uint32_t cmd)
-{
- /* dummy read */
- wait_dbcmd();
- mmio_write_32(DBSC_DBCMD, cmd);
- dsb_sev();
-}
-
-static void dbwait_loop(uint32_t wait_loop)
-{
- uint32_t i;
-
- for (i = 0U; i < wait_loop; i++) {
- wait_dbcmd();
- }
-}
-
-/* DDRPHY register access (raw) */
-static uint32_t reg_ddrphy_read(uint32_t phyno, uint32_t regadd)
-{
- uint32_t val;
- uint32_t loop;
-
- val = 0U;
- mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
- dsb_sev();
-
- while (mmio_read_32(DBSC_DBPDRGA(phyno)) != regadd) {
- dsb_sev();
- }
- dsb_sev();
-
- for (loop = 0U; loop < loop_max; loop++) {
- val = mmio_read_32(DBSC_DBPDRGD(phyno));
- dsb_sev();
- }
-
- return val;
-}
-
-static void reg_ddrphy_write(uint32_t phyno, uint32_t regadd, uint32_t regdata)
-{
- uint32_t loop;
-
- mmio_write_32(DBSC_DBPDRGA(phyno), regadd);
- dsb_sev();
- for (loop = 0U; loop < loop_max; loop++) {
- mmio_read_32(DBSC_DBPDRGA(phyno));
- dsb_sev();
- }
- mmio_write_32(DBSC_DBPDRGD(phyno), regdata);
- dsb_sev();
-
- for (loop = 0U; loop < loop_max; loop++) {
- mmio_read_32(DBSC_DBPDRGD(phyno));
- dsb_sev();
- }
-}
-
-static void reg_ddrphy_write_a(uint32_t regadd, uint32_t regdata)
-{
- uint32_t ch;
- uint32_t loop;
-
- foreach_vch(ch) {
- mmio_write_32(DBSC_DBPDRGA(ch), regadd);
- dsb_sev();
- }
-
- foreach_vch(ch) {
- mmio_write_32(DBSC_DBPDRGD(ch), regdata);
- dsb_sev();
- }
-
- for (loop = 0U; loop < loop_max; loop++) {
- mmio_read_32(DBSC_DBPDRGD(0));
- dsb_sev();
- }
-}
-
-static inline void ddrphy_regif_idle(void)
-{
- reg_ddrphy_read(0U, ddr_regdef_adr(_reg_PI_INT_STATUS));
- dsb_sev();
-}
-
-/* DDRPHY register access (field modify) */
-static inline uint32_t ddr_regdef(uint32_t _regdef)
-{
- return p_ddr_regdef_tbl[_regdef];
-}
-
-static inline uint32_t ddr_regdef_adr(uint32_t _regdef)
-{
- return DDR_REGDEF_ADR(p_ddr_regdef_tbl[_regdef]);
-}
-
-static inline uint32_t ddr_regdef_lsb(uint32_t _regdef)
-{
- return DDR_REGDEF_LSB(p_ddr_regdef_tbl[_regdef]);
-}
-
-static void ddr_setval_s(uint32_t ch, uint32_t slice, uint32_t _regdef,
- uint32_t val)
-{
- uint32_t adr;
- uint32_t lsb;
- uint32_t len;
- uint32_t msk;
- uint32_t tmp;
- uint32_t regdef;
-
- regdef = ddr_regdef(_regdef);
- adr = DDR_REGDEF_ADR(regdef) + 0x80U * slice;
- len = DDR_REGDEF_LEN(regdef);
- lsb = DDR_REGDEF_LSB(regdef);
- if (len == 0x20U) {
- msk = 0xffffffffU;
- } else {
- msk = ((1U << len) - 1U) << lsb;
- }
-
- tmp = reg_ddrphy_read(ch, adr);
- tmp = (tmp & (~msk)) | ((val << lsb) & msk);
- reg_ddrphy_write(ch, adr, tmp);
-}
-
-static uint32_t ddr_getval_s(uint32_t ch, uint32_t slice, uint32_t _regdef)
-{
- uint32_t adr;
- uint32_t lsb;
- uint32_t len;
- uint32_t msk;
- uint32_t tmp;
- uint32_t regdef;
-
- regdef = ddr_regdef(_regdef);
- adr = DDR_REGDEF_ADR(regdef) + 0x80U * slice;
- len = DDR_REGDEF_LEN(regdef);
- lsb = DDR_REGDEF_LSB(regdef);
- if (len == 0x20U) {
- msk = 0xffffffffU;
- } else {
- msk = ((1U << len) - 1U);
- }
-
- tmp = reg_ddrphy_read(ch, adr);
- tmp = (tmp >> lsb) & msk;
-
- return tmp;
-}
-
-static void ddr_setval(uint32_t ch, uint32_t regdef, uint32_t val)
-{
- ddr_setval_s(ch, 0U, regdef, val);
-}
-
-static void ddr_setval_ach_s(uint32_t slice, uint32_t regdef, uint32_t val)
-{
- uint32_t ch;
-
- foreach_vch(ch) {
- ddr_setval_s(ch, slice, regdef, val);
- }
-}
-
-static void ddr_setval_ach(uint32_t regdef, uint32_t val)
-{
- ddr_setval_ach_s(0U, regdef, val);
-}
-
-static void ddr_setval_ach_as(uint32_t regdef, uint32_t val)
-{
- uint32_t slice;
-
- for (slice = 0U; slice < SLICE_CNT; slice++) {
- ddr_setval_ach_s(slice, regdef, val);
- }
-}
-
-static uint32_t ddr_getval(uint32_t ch, uint32_t regdef)
-{
- return ddr_getval_s(ch, 0U, regdef);
-}
-
-static uint32_t ddr_getval_ach(uint32_t regdef, uint32_t *p)
-{
- uint32_t ch;
-
- foreach_vch(ch) {
- p[ch] = ddr_getval_s(ch, 0U, regdef);
- }
- return p[0U];
-}
-
-static uint32_t ddr_getval_ach_as(uint32_t regdef, uint32_t *p)
-{
- uint32_t ch, slice;
- uint32_t *pp;
-
- pp = p;
- foreach_vch(ch) {
- for (slice = 0U; slice < SLICE_CNT; slice++) {
- *pp++ = ddr_getval_s(ch, slice, regdef);
- }
- }
- return p[0U];
-}
-
-/* handling functions for setting ddrphy value table */
-static void _tblcopy(uint32_t *to, const uint32_t *from, uint32_t size)
-{
- uint32_t i;
-
- for (i = 0U; i < size; i++) {
- to[i] = from[i];
- }
-}
-
-static void ddrtbl_setval(uint32_t *tbl, uint32_t _regdef, uint32_t val)
-{
- uint32_t adr;
- uint32_t lsb;
- uint32_t len;
- uint32_t msk;
- uint32_t tmp;
- uint32_t adrmsk;
- uint32_t regdef;
-
- regdef = ddr_regdef(_regdef);
- adr = DDR_REGDEF_ADR(regdef);
- len = DDR_REGDEF_LEN(regdef);
- lsb = DDR_REGDEF_LSB(regdef);
- if (len == 0x20U) {
- msk = 0xffffffffU;
- } else {
- msk = ((1U << len) - 1U) << lsb;
- }
-
- if (adr < 0x400U) {
- adrmsk = 0xffU;
- } else {
- adrmsk = 0x7fU;
- }
-
- tmp = tbl[adr & adrmsk];
- tmp = (tmp & (~msk)) | ((val << lsb) & msk);
- tbl[adr & adrmsk] = tmp;
-}
-
-static uint32_t ddrtbl_getval(uint32_t *tbl, uint32_t _regdef)
-{
- uint32_t adr;
- uint32_t lsb;
- uint32_t len;
- uint32_t msk;
- uint32_t tmp;
- uint32_t adrmsk;
- uint32_t regdef;
-
- regdef = ddr_regdef(_regdef);
- adr = DDR_REGDEF_ADR(regdef);
- len = DDR_REGDEF_LEN(regdef);
- lsb = DDR_REGDEF_LSB(regdef);
- if (len == 0x20U) {
- msk = 0xffffffffU;
- } else {
- msk = ((1U << len) - 1U);
- }
-
- if (adr < 0x400U) {
- adrmsk = 0xffU;
- } else {
- adrmsk = 0x7fU;
- }
-
- tmp = tbl[adr & adrmsk];
- tmp = (tmp >> lsb) & msk;
-
- return tmp;
-}
-
-/* DDRPHY register access handling */
-static uint32_t ddrphy_regif_chk(void)
-{
- uint32_t tmp_ach[DRAM_CH_CNT];
- uint32_t ch;
- uint32_t err;
- uint32_t PI_VERSION_CODE;
-
- if (prr_product == PRR_PRODUCT_M3) {
- PI_VERSION_CODE = 0x2041U; /* G2M */
- }
-
- ddr_getval_ach(_reg_PI_VERSION, (uint32_t *)tmp_ach);
- err = 0U;
- foreach_vch(ch) {
- if (tmp_ach[ch] != PI_VERSION_CODE) {
- err = 1U;
- }
- }
- return err;
-}
-
-/* functions and parameters for timing setting */
-struct _jedec_spec1 {
- uint16_t fx3;
- uint8_t rlwodbi;
- uint8_t rlwdbi;
- uint8_t WL;
- uint8_t nwr;
- uint8_t nrtp;
- uint8_t odtlon;
- uint8_t MR1;
- uint8_t MR2;
-};
-
-#define JS1_USABLEC_SPEC_LO 2U
-#define JS1_USABLEC_SPEC_HI 5U
-#define JS1_FREQ_TBL_NUM 8
-#define JS1_MR1(f) (0x04U | ((f) << 4U))
-#define JS1_MR2(f) (0x00U | ((f) << 3U) | (f))
-static const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = {
- /* 533.333Mbps */
- { 800U, 6U, 6U, 4U, 6U, 8U, 0U, JS1_MR1(0U), JS1_MR2(0U) | 0x40U },
- /* 1066.666Mbps */
- { 1600U, 10U, 12U, 8U, 10U, 8U, 0U, JS1_MR1(1U), JS1_MR2(1U) | 0x40U },
- /* 1600.000Mbps */
- { 2400U, 14U, 16U, 12U, 16U, 8U, 6U, JS1_MR1(2U), JS1_MR2(2U) | 0x40U },
- /* 2133.333Mbps */
- { 3200U, 20U, 22U, 10U, 20U, 8U, 4U, JS1_MR1(3U), JS1_MR2(3U) },
- /* 2666.666Mbps */
- { 4000U, 24U, 28U, 12U, 24U, 10U, 4U, JS1_MR1(4U), JS1_MR2(4U) },
- /* 3200.000Mbps */
- { 4800U, 28U, 32U, 14U, 30U, 12U, 6U, JS1_MR1(5U), JS1_MR2(5U) },
- /* 3733.333Mbps */
- { 5600U, 32U, 36U, 16U, 34U, 14U, 6U, JS1_MR1(6U), JS1_MR2(6U) },
- /* 4266.666Mbps */
- { 6400U, 36U, 40U, 18U, 40U, 16U, 8U, JS1_MR1(7U), JS1_MR2(7U) }
-};
-
-struct _jedec_spec2 {
- uint16_t ps;
- uint16_t cyc;
-};
-
-#define js2_tsr 0
-#define js2_txp 1
-#define js2_trtp 2
-#define js2_trcd 3
-#define js2_trppb 4
-#define js2_trpab 5
-#define js2_tras 6
-#define js2_twr 7
-#define js2_twtr 8
-#define js2_trrd 9
-#define js2_tppd 10
-#define js2_tfaw 11
-#define js2_tdqsck 12
-#define js2_tckehcmd 13
-#define js2_tckelcmd 14
-#define js2_tckelpd 15
-#define js2_tmrr 16
-#define js2_tmrw 17
-#define js2_tmrd 18
-#define js2_tzqcalns 19
-#define js2_tzqlat 20
-#define js2_tiedly 21
-#define js2_tODTon_min 22
-#define JS2_TBLCNT 23
-
-#define js2_trcpb (JS2_TBLCNT)
-#define js2_trcab (JS2_TBLCNT + 1)
-#define js2_trfcab (JS2_TBLCNT + 2)
-#define JS2_CNT (JS2_TBLCNT + 3)
-
-#ifndef JS2_DERATE
-#define JS2_DERATE 0
-#endif
-static const struct _jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = {
- {
-/* tSR */ { 15000, 3 },
-/* tXP */ { 7500, 3 },
-/* tRTP */ { 7500, 8 },
-/* tRCD */ { 18000, 4 },
-/* tRPpb */ { 18000, 3 },
-/* tRPab */ { 21000, 3 },
-/* tRAS */ { 42000, 3 },
-/* tWR */ { 18000, 4 },
-/* tWTR */ { 10000, 8 },
-/* tRRD */ { 10000, 4 },
-/* tPPD */ { 0, 0 },
-/* tFAW */ { 40000, 0 },
-/* tDQSCK */ { 3500, 0 },
-/* tCKEHCMD */ { 7500, 3 },
-/* tCKELCMD */ { 7500, 3 },
-/* tCKELPD */ { 7500, 3 },
-/* tMRR */ { 0, 8 },
-/* tMRW */ { 10000, 10 },
-/* tMRD */ { 14000, 10 },
-/* tZQCALns */ { 1000 * 10, 0 },
-/* tZQLAT */ { 30000, 10 },
-/* tIEdly */ { 12500, 0 },
-/* tODTon_min */{ 1500, 0 }
- }, {
-/* tSR */ { 15000, 3 },
-/* tXP */ { 7500, 3 },
-/* tRTP */ { 7500, 8 },
-/* tRCD */ { 19875, 4 },
-/* tRPpb */ { 19875, 3 },
-/* tRPab */ { 22875, 3 },
-/* tRAS */ { 43875, 3 },
-/* tWR */ { 18000, 4 },
-/* tWTR */ { 10000, 8 },
-/* tRRD */ { 11875, 4 },
-/* tPPD */ { 0, 0 },
-/* tFAW */ { 40000, 0 },
-/* tDQSCK */ { 3600, 0 },
-/* tCKEHCMD */ { 7500, 3 },
-/* tCKELCMD */ { 7500, 3 },
-/* tCKELPD */ { 7500, 3 },
-/* tMRR */ { 0, 8 },
-/* tMRW */ { 10000, 10 },
-/* tMRD */ { 14000, 10 },
-/* tZQCALns */ { 1000 * 10, 0 },
-/* tZQLAT */ { 30000, 10 },
-/* tIEdly */ { 12500, 0 },
-/* tODTon_min */{ 1500, 0 }
- }
-};
-
-static const uint16_t jedec_spec2_trfc_ab[7] = {
- /* 4Gb, 6Gb, 8Gb, 12Gb, 16Gb, 24Gb(non), 32Gb(non) */
- 130U, 180U, 180U, 280U, 280U, 560U, 560U
-};
-
-static uint32_t js1_ind;
-static uint16_t js2[JS2_CNT];
-static uint8_t RL;
-static uint8_t WL;
-
-static uint16_t _f_scale(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv, uint32_t ps,
- uint16_t cyc)
-{
- uint16_t ret = cyc;
- uint32_t tmp;
- uint32_t div;
-
- tmp = (((uint32_t)(ps) + 9U) / 10U) * _ddr_mbps;
- div = tmp / (200000U * _ddr_mbpsdiv);
- if (tmp != (div * 200000U * _ddr_mbpsdiv)) {
- div = div + 1U;
- }
-
- if (div > cyc) {
- ret = (uint16_t)div;
- }
-
- return ret;
-}
-
-static void _f_scale_js2(uint32_t _ddr_mbps, uint32_t _ddr_mbpsdiv,
- uint16_t *_js2)
-{
- int i;
-
- for (i = 0; i < JS2_TBLCNT; i++) {
- _js2[i] = _f_scale(_ddr_mbps, _ddr_mbpsdiv,
- jedec_spec2[JS2_DERATE][i].ps,
- jedec_spec2[JS2_DERATE][i].cyc);
- }
-
- _js2[js2_trcpb] = _js2[js2_tras] + _js2[js2_trppb];
- _js2[js2_trcab] = _js2[js2_tras] + _js2[js2_trpab];
-}
-
-/* scaler for DELAY value */
-static int16_t _f_scale_adj(int16_t ps)
-{
- int32_t tmp;
- /*
- * tmp = (int32_t)512 * ps * ddr_mbps /2 / ddr_mbpsdiv / 1000 / 1000;
- * = ps * ddr_mbps /2 / ddr_mbpsdiv *512 / 8 / 8 / 125 / 125
- * = ps * ddr_mbps / ddr_mbpsdiv *4 / 125 / 125
- */
- tmp = (int32_t)4 * (int32_t)ps * (int32_t)ddr_mbps /
- (int32_t)ddr_mbpsdiv;
- tmp = (int32_t)tmp / (int32_t)15625;
-
- return (int16_t)tmp;
-}
-
-static const uint32_t reg_pi_mr1_data_fx_csx[2U][CSAB_CNT] = {
- {
- _reg_PI_MR1_DATA_F0_0,
- _reg_PI_MR1_DATA_F0_1,
- _reg_PI_MR1_DATA_F0_2,
- _reg_PI_MR1_DATA_F0_3},
- {
- _reg_PI_MR1_DATA_F1_0,
- _reg_PI_MR1_DATA_F1_1,
- _reg_PI_MR1_DATA_F1_2,
- _reg_PI_MR1_DATA_F1_3}
-};
-
-static const uint32_t reg_pi_mr2_data_fx_csx[2U][CSAB_CNT] = {
- {
- _reg_PI_MR2_DATA_F0_0,
- _reg_PI_MR2_DATA_F0_1,
- _reg_PI_MR2_DATA_F0_2,
- _reg_PI_MR2_DATA_F0_3},
- {
- _reg_PI_MR2_DATA_F1_0,
- _reg_PI_MR2_DATA_F1_1,
- _reg_PI_MR2_DATA_F1_2,
- _reg_PI_MR2_DATA_F1_3}
-};
-
-static const uint32_t reg_pi_mr3_data_fx_csx[2U][CSAB_CNT] = {
- {
- _reg_PI_MR3_DATA_F0_0,
- _reg_PI_MR3_DATA_F0_1,
- _reg_PI_MR3_DATA_F0_2,
- _reg_PI_MR3_DATA_F0_3},
- {
- _reg_PI_MR3_DATA_F1_0,
- _reg_PI_MR3_DATA_F1_1,
- _reg_PI_MR3_DATA_F1_2,
- _reg_PI_MR3_DATA_F1_3}
-};
-
-static const uint32_t reg_pi_mr11_data_fx_csx[2U][CSAB_CNT] = {
- {
- _reg_PI_MR11_DATA_F0_0,
- _reg_PI_MR11_DATA_F0_1,
- _reg_PI_MR11_DATA_F0_2,
- _reg_PI_MR11_DATA_F0_3},
- {
- _reg_PI_MR11_DATA_F1_0,
- _reg_PI_MR11_DATA_F1_1,
- _reg_PI_MR11_DATA_F1_2,
- _reg_PI_MR11_DATA_F1_3}
-};
-
-static const uint32_t reg_pi_mr12_data_fx_csx[2U][CSAB_CNT] = {
- {
- _reg_PI_MR12_DATA_F0_0,
- _reg_PI_MR12_DATA_F0_1,
- _reg_PI_MR12_DATA_F0_2,
- _reg_PI_MR12_DATA_F0_3},
- {
- _reg_PI_MR12_DATA_F1_0,
- _reg_PI_MR12_DATA_F1_1,
- _reg_PI_MR12_DATA_F1_2,
- _reg_PI_MR12_DATA_F1_3}
-};
-
-static const uint32_t reg_pi_mr14_data_fx_csx[2U][CSAB_CNT] = {
- {
- _reg_PI_MR14_DATA_F0_0,
- _reg_PI_MR14_DATA_F0_1,
- _reg_PI_MR14_DATA_F0_2,
- _reg_PI_MR14_DATA_F0_3},
- {
- _reg_PI_MR14_DATA_F1_0,
- _reg_PI_MR14_DATA_F1_1,
- _reg_PI_MR14_DATA_F1_2,
- _reg_PI_MR14_DATA_F1_3}
-};
-
-/*
- * regif pll w/a ( REGIF G2M WA )
- */
-static void regif_pll_wa(void)
-{
- uint32_t ch;
- uint32_t reg_ofs;
-
- /* PLL setting for PHY : G2M */
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_WAIT),
- (0x5064U <<
- ddr_regdef_lsb(_reg_PHY_PLL_WAIT)));
-
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL),
- (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_PLL_CTRL_TOP) << 16) |
- ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_PLL_CTRL));
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_PLL_CTRL_CA),
- ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_PLL_CTRL_CA));
-
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_PLL_CTRL),
- (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_LP4_BOOT_PLL_CTRL_CA) << 16) |
- ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_LP4_BOOT_PLL_CTRL));
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LP4_BOOT_TOP_PLL_CTRL),
- ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_LP4_BOOT_TOP_PLL_CTRL));
-
- reg_ofs = ddr_regdef_adr(_reg_PHY_LPDDR3_CS) - DDR_PHY_ADR_G_REGSET_OFS;
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_LPDDR3_CS),
- _cnf_DDR_PHY_ADR_G_REGSET[reg_ofs]);
-
- /* protect register interface */
- ddrphy_regif_idle();
- pll3_control(0U);
-
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_DLL_RST_EN),
- (0x01U << ddr_regdef_lsb(_reg_PHY_DLL_RST_EN)));
- ddrphy_regif_idle();
-
- /*
- * init start
- * dbdficnt0:
- * dfi_dram_clk_disable=1
- * dfi_frequency = 0
- * freq_ratio = 01 (2:1)
- * init_start =0
- */
- foreach_vch(ch) {
- mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F10U);
- }
- dsb_sev();
-
- /*
- * dbdficnt0:
- * dfi_dram_clk_disable=1
- * dfi_frequency = 0
- * freq_ratio = 01 (2:1)
- * init_start =1
- */
- foreach_vch(ch) {
- mmio_write_32(DBSC_DBDFICNT(ch), 0x00000F11U);
- }
- dsb_sev();
-
- foreach_ech(ch) {
- if ((board_cnf->phyvalid & BIT(ch)) != 0U) {
- while ((mmio_read_32(DBSC_PLL_LOCK(ch)) & 0x1fU) != 0x1fU) {
- }
- }
- }
- dsb_sev();
-}
-
-/* load table data into DDR registers */
-static void ddrtbl_load(void)
-{
- uint32_t i;
- uint32_t slice;
- uint32_t csab;
- uint32_t adr;
- uint32_t data_l;
- uint32_t tmp[3];
- uint16_t dataS;
-
- /*
- * TIMING REGISTERS
- * search jedec_spec1 index
- */
- for (i = JS1_USABLEC_SPEC_LO; i < (uint32_t)JS1_FREQ_TBL_NUM - 1U; i++) {
- if ((js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U) != 0U) {
- break;
- }
- }
- if (i > JS1_USABLEC_SPEC_HI) {
- js1_ind = JS1_USABLEC_SPEC_HI;
- } else {
- js1_ind = i;
- }
-
- if (board_cnf->dbi_en != 0U) {
- RL = js1[js1_ind].rlwdbi;
- } else {
- RL = js1[js1_ind].rlwodbi;
- }
-
- WL = js1[js1_ind].WL;
-
- /* calculate jedec_spec2 */
- _f_scale_js2(ddr_mbps, ddr_mbpsdiv, js2);
-
- /* PREPARE TBL */
- if (prr_product == PRR_PRODUCT_M3) {
- /* G2M */
- _tblcopy(_cnf_DDR_PHY_SLICE_REGSET,
- DDR_PHY_SLICE_REGSET_G2M, DDR_PHY_SLICE_REGSET_NUM_G2M);
- _tblcopy(_cnf_DDR_PHY_ADR_V_REGSET,
- DDR_PHY_ADR_V_REGSET_G2M, DDR_PHY_ADR_V_REGSET_NUM_G2M);
- _tblcopy(_cnf_DDR_PHY_ADR_I_REGSET,
- DDR_PHY_ADR_I_REGSET_G2M, DDR_PHY_ADR_I_REGSET_NUM_G2M);
- _tblcopy(_cnf_DDR_PHY_ADR_G_REGSET,
- DDR_PHY_ADR_G_REGSET_G2M, DDR_PHY_ADR_G_REGSET_NUM_G2M);
- _tblcopy(_cnf_DDR_PI_REGSET,
- DDR_PI_REGSET_G2M, DDR_PI_REGSET_NUM_G2M);
-
- DDR_PHY_SLICE_REGSET_OFS = DDR_PHY_SLICE_REGSET_OFS_G2M;
- DDR_PHY_ADR_V_REGSET_OFS = DDR_PHY_ADR_V_REGSET_OFS_G2M;
- DDR_PHY_ADR_I_REGSET_OFS = DDR_PHY_ADR_I_REGSET_OFS_G2M;
- DDR_PHY_ADR_G_REGSET_OFS = DDR_PHY_ADR_G_REGSET_OFS_G2M;
- DDR_PI_REGSET_OFS = DDR_PI_REGSET_OFS_G2M;
- DDR_PHY_SLICE_REGSET_SIZE = DDR_PHY_SLICE_REGSET_SIZE_G2M;
- DDR_PHY_ADR_V_REGSET_SIZE = DDR_PHY_ADR_V_REGSET_SIZE_G2M;
- DDR_PHY_ADR_I_REGSET_SIZE = DDR_PHY_ADR_I_REGSET_SIZE_G2M;
- DDR_PHY_ADR_G_REGSET_SIZE = DDR_PHY_ADR_G_REGSET_SIZE_G2M;
- DDR_PI_REGSET_SIZE = DDR_PI_REGSET_SIZE_G2M;
- DDR_PHY_SLICE_REGSET_NUM = DDR_PHY_SLICE_REGSET_NUM_G2M;
- DDR_PHY_ADR_V_REGSET_NUM = DDR_PHY_ADR_V_REGSET_NUM_G2M;
- DDR_PHY_ADR_I_REGSET_NUM = DDR_PHY_ADR_I_REGSET_NUM_G2M;
- DDR_PHY_ADR_G_REGSET_NUM = DDR_PHY_ADR_G_REGSET_NUM_G2M;
- DDR_PI_REGSET_NUM = DDR_PI_REGSET_NUM_G2M;
-
- DDR_PHY_ADR_I_NUM = 2U;
- }
-
- /* on fly gate adjust */
- if ((prr_product == PRR_PRODUCT_M3) && (prr_cut == PRR_PRODUCT_10)) {
- ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_ON_FLY_GATE_ADJUST_EN, 0x00);
- }
-
- /* Adjust PI parameters */
-#ifdef _def_LPDDR4_ODT
- for (i = 0U; i < 2U; i++) {
- for (csab = 0U; csab < CSAB_CNT; csab++) {
- ddrtbl_setval(_cnf_DDR_PI_REGSET,
- reg_pi_mr11_data_fx_csx[i][csab],
- _def_LPDDR4_ODT);
- }
- }
-#endif /* _def_LPDDR4_ODT */
-
-#ifdef _def_LPDDR4_VREFCA
- for (i = 0U; i < 2U; i++) {
- for (csab = 0U; csab < CSAB_CNT; csab++) {
- ddrtbl_setval(_cnf_DDR_PI_REGSET,
- reg_pi_mr12_data_fx_csx[i][csab],
- _def_LPDDR4_VREFCA);
- }
- }
-#endif /* _def_LPDDR4_VREFCA */
-
- if ((js2[js2_tiedly]) >= 0x0eU) {
- dataS = 0x0eU;
- } else {
- dataS = js2[js2_tiedly];
- }
-
- ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_DLY, dataS);
- ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_RDDATA_EN_TSEL_DLY,
- (dataS - 2U));
- ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1, RL - dataS);
-
- if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD) != 0U) {
- data_l = WL - 1U;
- } else {
- data_l = WL;
- }
- ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1, data_l - 2U);
- ddrtbl_setval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1, data_l);
-
- if (board_cnf->dbi_en != 0U) {
- ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE,
- 0x01U);
- ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_PHY_WDQLVL_DATADM_MASK, 0x000U);
- } else {
- ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_DBI_MODE,
- 0x00U);
- ddrtbl_setval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_PHY_WDQLVL_DATADM_MASK, 0x100U);
- }
-
- tmp[0] = js1[js1_ind].MR1;
- tmp[1] = js1[js1_ind].MR2;
- data_l = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_MR3_DATA_F1_0);
- if (board_cnf->dbi_en != 0U) {
- tmp[2] = data_l | 0xc0U;
- } else {
- tmp[2] = data_l & (~0xc0U);
- }
-
- for (i = 0U; i < 2U; i++) {
- for (csab = 0U; csab < CSAB_CNT; csab++) {
- ddrtbl_setval(_cnf_DDR_PI_REGSET,
- reg_pi_mr1_data_fx_csx[i][csab], tmp[0]);
- ddrtbl_setval(_cnf_DDR_PI_REGSET,
- reg_pi_mr2_data_fx_csx[i][csab], tmp[1]);
- ddrtbl_setval(_cnf_DDR_PI_REGSET,
- reg_pi_mr3_data_fx_csx[i][csab], tmp[2]);
- }
- }
-
- /* DDRPHY INT START */
- regif_pll_wa();
- dbwait_loop(5U);
-
- /* FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety) */
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
- BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
- ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01U);
-
- /* SET DATA SLICE TABLE */
- for (slice = 0U; slice < SLICE_CNT; slice++) {
- adr =
- DDR_PHY_SLICE_REGSET_OFS +
- DDR_PHY_SLICE_REGSET_SIZE * slice;
- for (i = 0U; i < DDR_PHY_SLICE_REGSET_NUM; i++) {
- reg_ddrphy_write_a(adr + i,
- _cnf_DDR_PHY_SLICE_REGSET[i]);
- }
- }
-
- /* SET ADR SLICE TABLE */
- adr = DDR_PHY_ADR_V_REGSET_OFS;
- for (i = 0U; i < DDR_PHY_ADR_V_REGSET_NUM; i++) {
- reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_V_REGSET[i]);
- }
-
- if ((prr_product == PRR_PRODUCT_M3) &&
- ((0x00ffffffU & (uint32_t)((board_cnf->ch[0].ca_swap) >> 40U))
- != 0x00U)) {
- adr = DDR_PHY_ADR_I_REGSET_OFS + DDR_PHY_ADR_I_REGSET_SIZE;
- for (i = 0U; i < DDR_PHY_ADR_V_REGSET_NUM; i++) {
- reg_ddrphy_write_a(adr + i,
- _cnf_DDR_PHY_ADR_V_REGSET[i]);
- }
- ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_ADR_DISABLE, 0x02);
- DDR_PHY_ADR_I_NUM -= 1U;
- ddr_phycaslice = 1U;
-
-#ifndef _def_LPDDR4_ODT
- for (i = 0U; i < 2U; i++) {
- for (csab = 0U; csab < CSAB_CNT; csab++) {
- ddrtbl_setval(_cnf_DDR_PI_REGSET,
- reg_pi_mr11_data_fx_csx[i][csab],
- 0x66);
- }
- }
-#endif/* _def_LPDDR4_ODT */
- } else {
- ddr_phycaslice = 0U;
- }
-
- if (DDR_PHY_ADR_I_NUM > 0U) {
- for (slice = 0U; slice < DDR_PHY_ADR_I_NUM; slice++) {
- adr =
- DDR_PHY_ADR_I_REGSET_OFS +
- DDR_PHY_ADR_I_REGSET_SIZE * slice;
- for (i = 0U; i < DDR_PHY_ADR_I_REGSET_NUM; i++) {
- reg_ddrphy_write_a(adr + i,
- _cnf_DDR_PHY_ADR_I_REGSET
- [i]);
- }
- }
- }
-
- /* SET ADRCTRL SLICE TABLE */
- adr = DDR_PHY_ADR_G_REGSET_OFS;
- for (i = 0U; i < DDR_PHY_ADR_G_REGSET_NUM; i++) {
- reg_ddrphy_write_a(adr + i, _cnf_DDR_PHY_ADR_G_REGSET[i]);
- }
-
- /* SET PI REGISTERS */
- adr = DDR_PI_REGSET_OFS;
- for (i = 0U; i < DDR_PI_REGSET_NUM; i++) {
- reg_ddrphy_write_a(adr + i, _cnf_DDR_PI_REGSET[i]);
- }
-}
-
-/* CONFIGURE DDR REGISTERS */
-static void ddr_config_sub(void)
-{
- const uint32_t _par_CALVL_DEVICE_MAP = 1U;
- uint8_t high_byte[SLICE_CNT];
- uint32_t ch, slice;
- uint32_t data_l;
- uint32_t tmp;
- uint32_t i;
-
- foreach_vch(ch) {
- /* BOARD SETTINGS (DQ,DM,VREF_DRIVING) */
- for (slice = 0U; slice < SLICE_CNT; slice++) {
- high_byte[slice] =
- (board_cnf->ch[ch].dqs_swap >> (4U * slice)) % 2U;
- ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE0,
- board_cnf->ch[ch].dq_swap[slice]);
- ddr_setval_s(ch, slice, _reg_PHY_DQ_DM_SWIZZLE1,
- board_cnf->ch[ch].dm_swap[slice]);
- if (high_byte[slice] != 0U) {
- /* HIGHER 16 BYTE */
- ddr_setval_s(ch, slice,
- _reg_PHY_CALVL_VREF_DRIVING_SLICE,
- 0x00);
- } else {
- /* LOWER 16 BYTE */
- ddr_setval_s(ch, slice,
- _reg_PHY_CALVL_VREF_DRIVING_SLICE,
- 0x01);
- }
- }
-
- /* BOARD SETTINGS (CA,ADDR_SEL) */
- data_l = (0x00ffffffU & (uint32_t)(board_cnf->ch[ch].ca_swap)) |
- 0x00888888U;
-
- /* --- ADR_CALVL_SWIZZLE --- */
- if (prr_product == PRR_PRODUCT_M3) {
- ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_0, data_l);
- ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_0,
- 0x00000000);
- ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0_1, data_l);
- ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1_1,
- 0x00000000);
- ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP,
- _par_CALVL_DEVICE_MAP);
- } else {
- ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE0, data_l);
- ddr_setval(ch, _reg_PHY_ADR_CALVL_SWIZZLE1, 0x00000000);
- ddr_setval(ch, _reg_PHY_CALVL_DEVICE_MAP,
- _par_CALVL_DEVICE_MAP);
- }
-
- /* --- ADR_ADDR_SEL --- */
- data_l = 0U;
- tmp = board_cnf->ch[ch].ca_swap;
- for (i = 0U; i < 6U; i++) {
- data_l |= ((tmp & 0x0fU) << (i * 5U));
- tmp = tmp >> 4;
- }
- ddr_setval(ch, _reg_PHY_ADR_ADDR_SEL, data_l);
- if (ddr_phycaslice == 1U) {
- /* ----------- adr slice2 swap ----------- */
- tmp = (uint32_t)((board_cnf->ch[ch].ca_swap) >> 40);
- data_l = (tmp & 0x00ffffffU) | 0x00888888U;
-
- /* --- ADR_CALVL_SWIZZLE --- */
- if (prr_product == PRR_PRODUCT_M3) {
- ddr_setval_s(ch, 2,
- _reg_PHY_ADR_CALVL_SWIZZLE0_0,
- data_l);
- ddr_setval_s(ch, 2,
- _reg_PHY_ADR_CALVL_SWIZZLE1_0,
- 0x00000000);
- ddr_setval_s(ch, 2,
- _reg_PHY_ADR_CALVL_SWIZZLE0_1,
- data_l);
- ddr_setval_s(ch, 2,
- _reg_PHY_ADR_CALVL_SWIZZLE1_1,
- 0x00000000);
- ddr_setval_s(ch, 2,
- _reg_PHY_ADR_CALVL_DEVICE_MAP,
- _par_CALVL_DEVICE_MAP);
- } else {
- ddr_setval_s(ch, 2,
- _reg_PHY_ADR_CALVL_SWIZZLE0,
- data_l);
- ddr_setval_s(ch, 2,
- _reg_PHY_ADR_CALVL_SWIZZLE1,
- 0x00000000);
- ddr_setval_s(ch, 2,
- _reg_PHY_CALVL_DEVICE_MAP,
- _par_CALVL_DEVICE_MAP);
- }
-
- /* --- ADR_ADDR_SEL --- */
- data_l = 0U;
- for (i = 0U; i < 6U; i++) {
- data_l |= ((tmp & 0x0fU) << (i * 5U));
- tmp = tmp >> 4U;
- }
-
- ddr_setval_s(ch, 2, _reg_PHY_ADR_ADDR_SEL, data_l);
- }
-
- /* BOARD SETTINGS (BYTE_ORDER_SEL) */
- if (prr_product == PRR_PRODUCT_M3) {
- /* --- DATA_BYTE_SWAP --- */
- data_l = 0U;
- tmp = board_cnf->ch[ch].dqs_swap;
- for (i = 0U; i < 4U; i++) {
- data_l |= ((tmp & 0x03U) << (i * 2U));
- tmp = tmp >> 4U;
- }
- } else {
- /* --- DATA_BYTE_SWAP --- */
- data_l = board_cnf->ch[ch].dqs_swap;
- ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_EN, 0x01);
- ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE0,
- (data_l) & 0x0fU);
- ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE1,
- (data_l >> 4U * 1U) & 0x0fU);
- ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE2,
- (data_l >> 4U * 2U) & 0x0fU);
- ddr_setval(ch, _reg_PI_DATA_BYTE_SWAP_SLICE3,
- (data_l >> 4U * 3U) & 0x0fU);
-
- ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH, 0x00U);
- }
- ddr_setval(ch, _reg_PHY_DATA_BYTE_ORDER_SEL, data_l);
- }
-}
-
-static void ddr_config(void)
-{
- uint32_t num_cacs_dly = _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM;
- uint32_t reg_ofs, dly;
- uint32_t ch, slice;
- uint32_t data_l;
- uint32_t tmp;
- uint32_t i;
- int8_t _adj;
- int16_t adj;
- uint32_t dq;
- union {
- uint32_t ui32[4];
- uint8_t ui8[16];
- } patt;
- uint16_t patm;
-
- /* configure ddrphy registers */
- ddr_config_sub();
-
- /* WDQ_USER_PATT */
- foreach_vch(ch) {
- for (slice = 0U; slice < SLICE_CNT; slice++) {
- patm = 0U;
- for (i = 0U; i < 16U; i++) {
- tmp = board_cnf->ch[ch].wdqlvl_patt[i];
- patt.ui8[i] = tmp & 0xffU;
- if ((tmp & 0x100U) != 0U) {
- patm |= (1U << (uint16_t)i);
- }
- }
- ddr_setval_s(ch, slice, _reg_PHY_USER_PATT0,
- patt.ui32[0]);
- ddr_setval_s(ch, slice, _reg_PHY_USER_PATT1,
- patt.ui32[1]);
- ddr_setval_s(ch, slice, _reg_PHY_USER_PATT2,
- patt.ui32[2]);
- ddr_setval_s(ch, slice, _reg_PHY_USER_PATT3,
- patt.ui32[3]);
- ddr_setval_s(ch, slice, _reg_PHY_USER_PATT4, patm);
- }
- }
-
- /* CACS DLY */
- data_l = board_cnf->cacs_dly + (uint32_t)_f_scale_adj(board_cnf->cacs_dly_adj);
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 0x00U);
- foreach_vch(ch) {
- for (i = 0U; i < num_cacs_dly - 4U; i++) {
- adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
- dly = _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i];
- ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, dly,
- data_l + (uint32_t)adj);
- reg_ofs = ddr_regdef_adr(dly) - DDR_PHY_ADR_V_REGSET_OFS;
- reg_ddrphy_write(ch, ddr_regdef_adr(dly),
- _cnf_DDR_PHY_ADR_V_REGSET[reg_ofs]);
- }
-
- for (i = num_cacs_dly - 4U; i < num_cacs_dly; i++) {
- adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
- dly = _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i];
- ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET, dly,
- data_l + (uint32_t)adj);
- reg_ofs = ddr_regdef_adr(dly) - DDR_PHY_ADR_G_REGSET_OFS;
- reg_ddrphy_write(ch, ddr_regdef_adr(dly),
- _cnf_DDR_PHY_ADR_G_REGSET[reg_ofs]);
- }
-
- if (ddr_phycaslice == 1U) {
- for (i = 0U; i < 6U; i++) {
- adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i + num_cacs_dly]);
- dly = _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i];
- ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET, dly,
- data_l + (uint32_t)adj);
- reg_ofs = ddr_regdef_adr(dly) - DDR_PHY_ADR_V_REGSET_OFS;
- reg_ddrphy_write(ch, ddr_regdef_adr(dly) + 0x0100U,
- _cnf_DDR_PHY_ADR_V_REGSET[reg_ofs]);
- }
- }
- }
-
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
- BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
-
- /* WDQDM DLY */
- data_l = board_cnf->dqdm_dly_w;
- foreach_vch(ch) {
- for (slice = 0U; slice < SLICE_CNT; slice++) {
- for (i = 0U; i <= 8U; i++) {
- dq = slice * 8U + (uint32_t)i;
- if (i == 8U) {
- _adj = board_cnf->ch[ch].dm_adj_w[slice];
- } else {
- _adj = board_cnf->ch[ch].dq_adj_w[dq];
- }
- adj = _f_scale_adj(_adj);
- ddr_setval_s(ch, slice,
- _reg_PHY_CLK_WRX_SLAVE_DELAY[i],
- data_l + (uint32_t)adj);
- }
- }
- }
-
- /* RDQDM DLY */
- data_l = board_cnf->dqdm_dly_r;
- foreach_vch(ch) {
- for (slice = 0U; slice < SLICE_CNT; slice++) {
- for (i = 0U; i <= 8U; i++) {
- dq = slice * 8U + (uint32_t)i;
- if (i == 8U) {
- _adj = board_cnf->ch[ch].dm_adj_r[slice];
- } else {
- _adj = board_cnf->ch[ch].dq_adj_r[dq];
- }
- adj = _f_scale_adj(_adj);
- dly = _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i];
- ddr_setval_s(ch, slice, dly, data_l + (uint32_t)adj);
- dly = _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i];
- ddr_setval_s(ch, slice, dly, data_l + (uint32_t)adj);
- }
- }
- }
-}
-
-/* DBSC register setting functions */
-static void dbsc_regset_pre(void)
-{
- uint32_t ch, csab;
- uint32_t data_l;
-
- /* PRIMARY SETTINGS */
- /* LPDDR4, BL=16, DFI interface */
- mmio_write_32(DBSC_DBKIND, 0x0000000aU);
- mmio_write_32(DBSC_DBBL, 0x00000002U);
- mmio_write_32(DBSC_DBPHYCONF0, 0x00000001U);
-
- /* FREQRATIO=2 */
- mmio_write_32(DBSC_DBSYSCONF1, 0x00000002U);
-
- /*
- * DRAM SIZE REGISTER:
- * set all ranks as density=0(4Gb) for PHY initialization
- */
- foreach_vch(ch) {
- for (csab = 0U; csab < 4U; csab++) {
- mmio_write_32(DBSC_DBMEMCONF(ch, csab),
- DBMEMCONF_REGD(0U));
- }
- }
-
- if (prr_product == PRR_PRODUCT_M3) {
- data_l = 0xe4e4e4e4U;
- foreach_ech(ch) {
- if ((ddr_phyvalid & (1U << ch)) != 0U) {
- data_l = (data_l & (~(0x000000FFU << (ch * 8U))))
- | (((board_cnf->ch[ch].dqs_swap & 0x0003U)
- | ((board_cnf->ch[ch].dqs_swap & 0x0030U) >> 2U)
- | ((board_cnf->ch[ch].dqs_swap & 0x0300U) >> 4U)
- | ((board_cnf->ch[ch].dqs_swap & 0x3000U) >> 6U))
- << (ch * 8U));
- }
- }
- mmio_write_32(DBSC_DBBSWAP, data_l);
- }
-}
-
-static void dbsc_regset(void)
-{
- int32_t i;
- uint32_t ch;
- uint32_t data_l;
- uint32_t data_l2;
- uint32_t wdql;
- uint32_t dqenltncy;
- uint32_t dql;
- uint32_t dqienltncy;
- uint32_t wrcslat;
- uint32_t wrcsgap;
- uint32_t rdcslat;
- uint32_t rdcsgap;
- uint32_t scfctst0_act_act;
- uint32_t scfctst0_rda_act;
- uint32_t scfctst0_wra_act;
- uint32_t scfctst0_pre_act;
- uint32_t scfctst1_rd_wr;
- uint32_t scfctst1_wr_rd;
- uint32_t scfctst1_act_rd_wr;
- uint32_t scfctst1_asyncofs;
- uint32_t dbschhrw1_sctrfcab;
-
- /* RFC */
- js2[js2_trfcab] =
- _f_scale(ddr_mbps, ddr_mbpsdiv,
- jedec_spec2_trfc_ab[max_density] * 1000U, 0U);
- /* DBTR0.CL : RL */
- mmio_write_32(DBSC_DBTR(0), RL);
-
- /* DBTR1.CWL : WL */
- mmio_write_32(DBSC_DBTR(1), WL);
-
- /* DBTR2.AL : 0 */
- mmio_write_32(DBSC_DBTR(2), 0U);
-
- /* DBTR3.TRCD: tRCD */
- mmio_write_32(DBSC_DBTR(3), js2[js2_trcd]);
-
- /* DBTR4.TRPA,TRP: tRPab,tRPpb */
- mmio_write_32(DBSC_DBTR(4), (js2[js2_trpab] << 16) | js2[js2_trppb]);
-
- /* DBTR5.TRC : use tRCpb */
- mmio_write_32(DBSC_DBTR(5), js2[js2_trcpb]);
-
- /* DBTR6.TRAS : tRAS */
- mmio_write_32(DBSC_DBTR(6), js2[js2_tras]);
-
- /* DBTR7.TRRD : tRRD */
- mmio_write_32(DBSC_DBTR(7), (js2[js2_trrd] << 16) | js2[js2_trrd]);
-
- /* DBTR8.TFAW : tFAW */
- mmio_write_32(DBSC_DBTR(8), js2[js2_tfaw]);
-
- /* DBTR9.TRDPR : tRTP */
- mmio_write_32(DBSC_DBTR(9), js2[js2_trtp]);
-
- /* DBTR10.TWR : nWR */
- mmio_write_32(DBSC_DBTR(10), js1[js1_ind].nwr);
-
- /*
- * DBTR11.TRDWR : RL + BL / 2 + Rounddown(tRPST) + PHY_ODTLoff -
- * odtlon + tDQSCK - tODTon,min +
- * PCB delay (out+in) + tPHY_ODToff
- */
- mmio_write_32(DBSC_DBTR(11),
- RL + (16U / 2U) + 1U + 2U - js1[js1_ind].odtlon +
- js2[js2_tdqsck] - js2[js2_tODTon_min] +
- _f_scale(ddr_mbps, ddr_mbpsdiv, 1300, 0));
-
- /* DBTR12.TWRRD : WL + 1 + BL/2 + tWTR */
- data_l = WL + 1U + (16U / 2U) + js2[js2_twtr];
- mmio_write_32(DBSC_DBTR(12), (data_l << 16) | data_l);
-
- /* DBTR13.TRFCAB : tRFCab */
- mmio_write_32(DBSC_DBTR(13), js2[js2_trfcab]);
-
- /* DBTR14.TCKEHDLL,tCKEH : tCKEHCMD,tCKEHCMD */
- mmio_write_32(DBSC_DBTR(14),
- (js2[js2_tckehcmd] << 16) | (js2[js2_tckehcmd]));
-
- /* DBTR15.TCKESR,TCKEL : tSR,tCKELPD */
- mmio_write_32(DBSC_DBTR(15), (js2[js2_tsr] << 16) | (js2[js2_tckelpd]));
-
- /* DBTR16 */
- /* WDQL : tphy_wrlat + tphy_wrdata */
- wdql = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_F1);
- /* DQENLTNCY : tphy_wrlat = WL-2 : PHY_WRITE_PATH_LAT_ADD == 0
- * tphy_wrlat = WL-3 : PHY_WRITE_PATH_LAT_ADD != 0
- */
- dqenltncy = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_WRLAT_ADJ_F1);
- /* DQL : tphy_rdlat + trdata_en */
- /* it is not important for dbsc */
- dql = RL + 16U;
- /* DQIENLTNCY : trdata_en */
- dqienltncy = ddrtbl_getval(_cnf_DDR_PI_REGSET, _reg_PI_RDLAT_ADJ_F1) - 1U;
- mmio_write_32(DBSC_DBTR(16),
- (dqienltncy << 24) | (dql << 16) | (dqenltncy << 8) | wdql);
-
- /* DBTR24 */
- /* WRCSLAT = WRLAT -5 */
- wrcslat = wdql - 5U;
- /* WRCSGAP = 5 */
- wrcsgap = 5U;
- /* RDCSLAT = RDLAT_ADJ +2 */
- rdcslat = dqienltncy;
- if (prr_product != PRR_PRODUCT_M3) {
- rdcslat += 2U;
- }
- /* RDCSGAP = 6 */
- rdcsgap = 6U;
- if (prr_product == PRR_PRODUCT_M3) {
- rdcsgap = 4U;
- }
- mmio_write_32(DBSC_DBTR(24),
- (rdcsgap << 24) | (rdcslat << 16) | (wrcsgap << 8) | wrcslat);
-
- /* DBTR17.TMODRD,TMOD,TRDMR: tMRR,tMRD,(0) */
- mmio_write_32(DBSC_DBTR(17),
- (js2[js2_tmrr] << 24) | (js2[js2_tmrd] << 16));
-
- /* DBTR18.RODTL, RODTA, WODTL, WODTA : do not use in LPDDR4 */
- mmio_write_32(DBSC_DBTR(18), 0);
-
- /* DBTR19.TZQCL, TZQCS : do not use in LPDDR4 */
- mmio_write_32(DBSC_DBTR(19), 0);
-
- /* DBTR20.TXSDLL, TXS : tRFCab+tCKEHCMD */
- data_l = js2[js2_trfcab] + js2[js2_tckehcmd];
- mmio_write_32(DBSC_DBTR(20), (data_l << 16) | data_l);
-
- /* DBTR21.TCCD */
- /* DBTR23.TCCD */
- if (ddr_tccd == 8U) {
- data_l = 8U;
- mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
- mmio_write_32(DBSC_DBTR(23), 0x00000002);
- } else if (ddr_tccd <= 11U) {
- data_l = 11U;
- mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
- mmio_write_32(DBSC_DBTR(23), 0x00000000);
- } else {
- data_l = ddr_tccd;
- mmio_write_32(DBSC_DBTR(21), (data_l << 16) | data_l);
- mmio_write_32(DBSC_DBTR(23), 0x00000000);
- }
-
- /* DBTR22.ZQLAT : */
- data_l = js2[js2_tzqcalns] * 100U; /* 1000 * 1000 ps */
- data_l = (data_l << 16U) | (js2[js2_tzqlat] + 24U + 20U);
- mmio_write_32(DBSC_DBTR(22), data_l);
-
- /* DBTR25 : do not use in LPDDR4 */
- mmio_write_32(DBSC_DBTR(25), 0U);
-
- /*
- * DBRNK :
- * DBSC_DBRNK2 rkrr
- * DBSC_DBRNK3 rkrw
- * DBSC_DBRNK4 rkwr
- * DBSC_DBRNK5 rkww
- */
-#define _par_DBRNK_VAL (0x7007U)
-
- for (i = 0; i < 4; i++) {
- data_l = (_par_DBRNK_VAL >> ((uint32_t)i * 4U)) & 0x0fU;
- data_l2 = 0U;
- foreach_vch(ch) {
- data_l2 = data_l2 | (data_l << (4U * ch));
- }
- mmio_write_32(DBSC_DBRNK(2 + i), data_l2);
- }
- mmio_write_32(DBSC_DBADJ0, 0x00000000U);
-
- /* timing registers for scheduler */
- /* SCFCTST0 */
- /* SCFCTST0 ACT-ACT */
- scfctst0_act_act = js2[js2_trcpb] * 800UL * ddr_mbpsdiv / ddr_mbps;
- /* SCFCTST0 RDA-ACT */
- scfctst0_rda_act = ((16U / 2U) + js2[js2_trtp] - 8U +
- js2[js2_trppb]) * 800UL * ddr_mbpsdiv / ddr_mbps;
- /* SCFCTST0 WRA-ACT */
- scfctst0_wra_act = (WL + 1U + (16U / 2U) +
- js1[js1_ind].nwr) * 800UL * ddr_mbpsdiv / ddr_mbps;
- /* SCFCTST0 PRE-ACT */
- scfctst0_pre_act = js2[js2_trppb];
- mmio_write_32(DBSC_SCFCTST0,
- (scfctst0_act_act << 24) | (scfctst0_rda_act << 16) |
- (scfctst0_wra_act << 8) | scfctst0_pre_act);
-
- /* SCFCTST1 */
- /* SCFCTST1 RD-WR */
- scfctst1_rd_wr = (mmio_read_32(DBSC_DBTR(11)) & 0xffU) * 800UL * ddr_mbpsdiv /
- ddr_mbps;
- /* SCFCTST1 WR-RD */
- scfctst1_wr_rd = (mmio_read_32(DBSC_DBTR(12)) & 0xff) * 800UL * ddr_mbpsdiv /
- ddr_mbps;
- /* SCFCTST1 ACT-RD/WR */
- scfctst1_act_rd_wr = js2[js2_trcd] * 800UL * ddr_mbpsdiv / ddr_mbps;
- /* SCFCTST1 ASYNCOFS */
- scfctst1_asyncofs = 12U;
- mmio_write_32(DBSC_SCFCTST1,
- (scfctst1_rd_wr << 24) | (scfctst1_wr_rd << 16) |
- (scfctst1_act_rd_wr << 8) | scfctst1_asyncofs);
-
- /* DBSCHRW1 */
- /* DBSCHRW1 SCTRFCAB */
- dbschhrw1_sctrfcab = js2[js2_trfcab] * 800UL * ddr_mbpsdiv / ddr_mbps;
- data_l = (((mmio_read_32(DBSC_DBTR(16)) & 0x00FF0000U) >> 16) +
- (mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFFU) +
- (0x28U * 2U)) * 400U * 2U * ddr_mbpsdiv / ddr_mbps + 7U;
- if (dbschhrw1_sctrfcab < data_l) {
- dbschhrw1_sctrfcab = data_l;
- }
-
- if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) {
- mmio_write_32(DBSC_DBSCHRW1, dbschhrw1_sctrfcab +
- ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFFU) *
- 400U * 2U * ddr_mbpsdiv + (ddr_mbps - 1U)) / ddr_mbps - 3U);
- } else {
- mmio_write_32(DBSC_DBSCHRW1, dbschhrw1_sctrfcab +
- ((mmio_read_32(DBSC_DBTR(22)) & 0x0000FFFFU) *
- 400U * 2U * ddr_mbpsdiv + (ddr_mbps - 1U)) / ddr_mbps);
- }
-
- /* QOS and CAM */
-#ifdef DDR_QOS_INIT_SETTING /* only for non qos_init */
- /* wbkwait(0004), wbkmdhi(4,2),wbkmdlo(1,8) */
- mmio_write_32(DBSC_DBCAM0CNF1, 0x00043218U);
- /* 0(fillunit),8(dirtymax),4(dirtymin) */
- mmio_write_32(DBSC_DBCAM0CNF2, 0x000000F4U);
- /* stop_tolerance */
- mmio_write_32(DBSC_DBSCHRW0, 0x22421111U);
- /* rd-wr/wr-rd toggle priority */
- mmio_write_32(DBSC_SCFCTST2, 0x012F1123U);
- mmio_write_32(DBSC_DBSCHSZ0, 0x00000001U);
- mmio_write_32(DBSC_DBSCHCNT0, 0x000F0037U);
-
- /* QoS Settings */
- mmio_write_32(DBSC_DBSCHQOS00, 0x00000F00U);
- mmio_write_32(DBSC_DBSCHQOS01, 0x00000B00U);
- mmio_write_32(DBSC_DBSCHQOS02, 0x00000000U);
- mmio_write_32(DBSC_DBSCHQOS03, 0x00000000U);
- mmio_write_32(DBSC_DBSCHQOS40, 0x00000300U);
- mmio_write_32(DBSC_DBSCHQOS41, 0x000002F0U);
- mmio_write_32(DBSC_DBSCHQOS42, 0x00000200U);
- mmio_write_32(DBSC_DBSCHQOS43, 0x00000100U);
- mmio_write_32(DBSC_DBSCHQOS90, 0x00000100U);
- mmio_write_32(DBSC_DBSCHQOS91, 0x000000F0U);
- mmio_write_32(DBSC_DBSCHQOS92, 0x000000A0U);
- mmio_write_32(DBSC_DBSCHQOS93, 0x00000040U);
- mmio_write_32(DBSC_DBSCHQOS120, 0x00000040U);
- mmio_write_32(DBSC_DBSCHQOS121, 0x00000030U);
- mmio_write_32(DBSC_DBSCHQOS122, 0x00000020U);
- mmio_write_32(DBSC_DBSCHQOS123, 0x00000010U);
- mmio_write_32(DBSC_DBSCHQOS130, 0x00000100U);
- mmio_write_32(DBSC_DBSCHQOS131, 0x000000F0U);
- mmio_write_32(DBSC_DBSCHQOS132, 0x000000A0U);
- mmio_write_32(DBSC_DBSCHQOS133, 0x00000040U);
- mmio_write_32(DBSC_DBSCHQOS140, 0x000000C0U);
- mmio_write_32(DBSC_DBSCHQOS141, 0x000000B0U);
- mmio_write_32(DBSC_DBSCHQOS142, 0x00000080U);
- mmio_write_32(DBSC_DBSCHQOS143, 0x00000040U);
- mmio_write_32(DBSC_DBSCHQOS150, 0x00000040U);
- mmio_write_32(DBSC_DBSCHQOS151, 0x00000030U);
- mmio_write_32(DBSC_DBSCHQOS152, 0x00000020U);
- mmio_write_32(DBSC_DBSCHQOS153, 0x00000010U);
-
- mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
-#endif /* DDR_QOS_INIT_SETTING */
-
- /* resrdis */
- mmio_write_32(DBSC_DBBCAMDIS, 0x00000001U);
-}
-
-static void dbsc_regset_post(void)
-{
- uint32_t slice, rdlat_max, rdlat_min;
- uint32_t ch, cs;
- uint32_t data_l;
- uint32_t srx;
-
- rdlat_max = 0U;
- rdlat_min = 0xffffU;
- foreach_vch(ch) {
- for (cs = 0U; cs < CS_CNT; cs++) {
- if ((ch_have_this_cs[cs] & (1U << ch)) != 0U) {
- for (slice = 0U; slice < SLICE_CNT; slice++) {
- ddr_setval_s(ch, slice,
- _reg_PHY_PER_CS_TRAINING_INDEX,
- cs);
- data_l = ddr_getval_s(ch, slice,
- _reg_PHY_RDDQS_LATENCY_ADJUST);
- if (data_l > rdlat_max) {
- rdlat_max = data_l;
- }
- if (data_l < rdlat_min) {
- rdlat_min = data_l;
- }
- }
- }
- }
- }
-
- mmio_write_32(DBSC_DBTR(24),
- ((rdlat_max + 2U) << 24) +
- ((rdlat_max + 2U) << 16) +
- mmio_read_32(DBSC_DBTR(24)));
-
- /* set ddr density information */
- foreach_ech(ch) {
- for (cs = 0U; cs < CS_CNT; cs++) {
- if (ddr_density[ch][cs] == 0xffU) {
- mmio_write_32(DBSC_DBMEMCONF(ch, cs), 0x00U);
- } else {
- mmio_write_32(DBSC_DBMEMCONF(ch, cs),
- DBMEMCONF_REGD(ddr_density[ch]
- [cs]));
- }
- }
- mmio_write_32(DBSC_DBMEMCONF(ch, 2), 0x00000000U);
- mmio_write_32(DBSC_DBMEMCONF(ch, 3), 0x00000000U);
- }
-
- mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010U);
-
- /* set DBI */
- if (board_cnf->dbi_en != 0U) {
- mmio_write_32(DBSC_DBDBICNT, 0x00000003U);
- }
-
- /* set REFCYCLE */
- data_l = (get_refperiod()) * ddr_mbps / 2000U / ddr_mbpsdiv;
- mmio_write_32(DBSC_DBRFCNF1, 0x00080000U | (data_l & 0x0000ffffU));
- mmio_write_32(DBSC_DBRFCNF2, 0x00010000U | DBSC_REFINTS);
-
-#if RCAR_REWT_TRAINING != 0
- /* Periodic-WriteDQ Training seeting */
- if ((prr_product == PRR_PRODUCT_M3) &&
- (prr_cut == PRR_PRODUCT_10)) {
- /* G2M Ver.1.0 not support */
- } else {
- /* G2M Ver.1.1 or later */
- mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000000U);
-
- ddr_setval_ach_as(_reg_PHY_WDQLVL_PATT, 0x04U);
- ddr_setval_ach_as(_reg_PHY_WDQLVL_QTR_DLY_STEP, 0x0FU);
- ddr_setval_ach_as(_reg_PHY_WDQLVL_DLY_STEP, 0x50U);
- ddr_setval_ach_as(_reg_PHY_WDQLVL_DQDM_SLV_DLY_START, 0x0300U);
-
- ddr_setval_ach(_reg_PI_WDQLVL_CS_MAP,
- ddrtbl_getval(_cnf_DDR_PI_REGSET,
- _reg_PI_WDQLVL_CS_MAP));
- ddr_setval_ach(_reg_PI_LONG_COUNT_MASK, 0x1fU);
- ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x00U);
- ddr_setval_ach(_reg_PI_WDQLVL_ROTATE, 0x01U);
- ddr_setval_ach(_reg_PI_TREF_F0, 0x0000U);
- ddr_setval_ach(_reg_PI_TREF_F1, 0x0000U);
- ddr_setval_ach(_reg_PI_TREF_F2, 0x0000U);
-
- if (prr_product == PRR_PRODUCT_M3) {
- ddr_setval_ach(_reg_PI_WDQLVL_EN, 0x02U);
- } else {
- ddr_setval_ach(_reg_PI_WDQLVL_EN_F1, 0x02U);
- }
- ddr_setval_ach(_reg_PI_WDQLVL_PERIODIC, 0x01U);
-
- /* DFI_PHYMSTR_ACK , WTmode setting */
- /* DFI_PHYMSTR_ACK: WTmode =b'01 */
- mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000011U);
- }
-#endif /* RCAR_REWT_TRAINING */
- /* periodic dram zqcal enable */
- mmio_write_32(DBSC_DBCALCNF, 0x01000010U);
-
- /* periodic phy ctrl update enable */
- if ((prr_product == PRR_PRODUCT_M3) &&
- (prr_cut < PRR_PRODUCT_30)) {
- /* non : G2M Ver.1.x not support */
- } else {
- mmio_write_32(DBSC_DBDFICUPDCNF, 0x28240001U);
- }
-
-#ifdef DDR_BACKUPMODE
- /* SRX */
- srx = 0x0A840001U; /* for All channels */
- if (ddr_backup == DRAM_BOOT_STATUS_WARM) {
-#ifdef DDR_BACKUPMODE_HALF /* for Half channel(ch0, 1 only) */
- NOTICE("BL2: [DEBUG_MESS] DDR_BACKUPMODE_HALF\n");
- srx = 0x0A040001U;
-#endif /* DDR_BACKUPMODE_HALF */
- send_dbcmd(srx);
- }
-#endif /* DDR_BACKUPMODE */
-
- /* set Auto Refresh */
- mmio_write_32(DBSC_DBRFEN, 0x00000001U);
-
-#if RCAR_REWT_TRAINING != 0
- /* Periodic WriteDQ Traning */
- if ((prr_product == PRR_PRODUCT_M3) &&
- (prr_cut == PRR_PRODUCT_10)) {
- /* non : G2M Ver.1.0 not support */
- } else {
- /* G2M Ver.1.1 or later */
- ddr_setval_ach(_reg_PI_WDQLVL_INTERVAL, 0x0100U);
- }
-#endif /* RCAR_REWT_TRAINING */
-
- /* dram access enable */
- mmio_write_32(DBSC_DBACEN, 0x00000001U);
-
- MSG_LF(__func__ "(done)");
-}
-
-/* DFI_INIT_START */
-static uint32_t dfi_init_start(void)
-{
- uint32_t ch;
- uint32_t phytrainingok;
- uint32_t retry;
- uint32_t data_l;
- uint32_t ret = 0U;
- const uint32_t RETRY_MAX = 0x10000U;
-
- ddr_setval_ach_as(_reg_PHY_DLL_RST_EN, 0x02U);
- dsb_sev();
- ddrphy_regif_idle();
-
- /* dll_rst negate */
- foreach_vch(ch) {
- mmio_write_32(DBSC_DBPDCNT3(ch), 0x0000CF01U);
- }
- dsb_sev();
-
- /* wait init_complete */
- phytrainingok = 0U;
- retry = 0U;
- while (retry++ < RETRY_MAX) {
- foreach_vch(ch) {
- data_l = mmio_read_32(DBSC_DBDFISTAT(ch));
- if (data_l & 0x00000001U) {
- phytrainingok |= (1U << ch);
- }
- }
- dsb_sev();
- if (phytrainingok == ddr_phyvalid) {
- break;
- }
- if (retry % 256U == 0U) {
- ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01U);
- }
- }
-
- /* all ch ok? */
- if ((phytrainingok & ddr_phyvalid) != ddr_phyvalid) {
- ret = 0xffU;
- goto done;
- }
-
- /*
- * dbdficnt0:
- * dfi_dram_clk_disable=0
- * dfi_frequency = 0
- * freq_ratio = 01 (2:1)
- * init_start =0
- */
- foreach_vch(ch) {
- mmio_write_32(DBSC_DBDFICNT(ch), 0x00000010U);
- }
- dsb_sev();
-done:
- return ret;
-}
-
-/* drivability setting : CMOS MODE ON/OFF */
-static void change_lpddr4_en(uint32_t mode)
-{
- uint32_t ch;
- uint32_t i;
- uint32_t data_l;
- const uint32_t _reg_PHY_PAD_DRIVE_X[3] = {
- _reg_PHY_PAD_ADDR_DRIVE,
- _reg_PHY_PAD_CLK_DRIVE,
- _reg_PHY_PAD_CS_DRIVE
- };
-
- foreach_vch(ch) {
- for (i = 0U; i < 3U; i++) {
- data_l = ddr_getval(ch, _reg_PHY_PAD_DRIVE_X[i]);
- if (mode != 0U) {
- data_l |= (1U << 14);
- } else {
- data_l &= ~(1U << 14);
- }
- ddr_setval(ch, _reg_PHY_PAD_DRIVE_X[i], data_l);
- }
- }
-}
-
-/* drivability setting */
-static uint32_t set_term_code(void)
-{
- uint32_t i;
- uint32_t ch, index;
- uint32_t data_l;
- uint32_t chip_id[2];
- uint32_t term_code;
- uint32_t override;
-
- term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_PAD_DATA_TERM);
- override = 0U;
- for (i = 0U; i < 2U; i++) {
- chip_id[i] = mmio_read_32(LIFEC_CHIPID(i));
- }
-
- index = 0U;
- while (true) {
- if (termcode_by_sample[index][0] == 0xffffffff) {
- break;
- }
- if ((termcode_by_sample[index][0] == chip_id[0]) &&
- (termcode_by_sample[index][1] == chip_id[1])) {
- term_code = termcode_by_sample[index][2];
- override = 1;
- break;
- }
- index++;
- }
-
- if (override != 0U) {
- for (index = 0U; index < _reg_PHY_PAD_TERM_X_NUM; index++) {
- data_l =
- ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_PAD_TERM_X[index]);
- data_l = (data_l & 0xfffe0000U) | term_code;
- ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], data_l);
- }
- } else if ((prr_product == PRR_PRODUCT_M3) &&
- (prr_cut == PRR_PRODUCT_10)) {
- /* non */
- } else {
- ddr_setval_ach(_reg_PHY_PAD_TERM_X[0],
- (ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
- _reg_PHY_PAD_TERM_X[0]) & 0xFFFE0000U));
- ddr_setval_ach(_reg_PHY_CAL_CLEAR_0, 0x01U);
- ddr_setval_ach(_reg_PHY_CAL_START_0, 0x01U);
- foreach_vch(ch) {
- do {
- data_l =
- ddr_getval(ch, _reg_PHY_CAL_RESULT2_OBS_0);
- } while (!(data_l & 0x00800000U));
- }
-
- /* G2M Ver.1.1 or later */
- foreach_vch(ch) {
- for (index = 0U; index < _reg_PHY_PAD_TERM_X_NUM;
- index++) {
- data_l = ddr_getval(ch, _reg_PHY_PAD_TERM_X[index]);
- ddr_setval(ch, _reg_PHY_PAD_TERM_X[index],
- (data_l & 0xFFFE0FFFU) | 0x00015000U);
- }
- }
- }
-
- ddr_padcal_tcompensate_getinit(override);
-
- return 0U;
-}
-
-/* DDR mode register setting */
-static void ddr_register_set(void)
-{
- int32_t fspwp;
- uint32_t tmp;
-
- for (fspwp = 1; fspwp >= 0; fspwp--) {
- /*MR13, fspwp */
- send_dbcmd(0x0e840d08U | ((2U - fspwp) << 6));
-
- tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
- reg_pi_mr1_data_fx_csx[fspwp][0]);
- send_dbcmd(0x0e840100U | tmp);
-
- tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
- reg_pi_mr2_data_fx_csx[fspwp][0]);
- send_dbcmd(0x0e840200U | tmp);
-
- tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
- reg_pi_mr3_data_fx_csx[fspwp][0]);
- send_dbcmd(0x0e840300U | tmp);
-
- tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
- reg_pi_mr11_data_fx_csx[fspwp][0]);
- send_dbcmd(0x0e840b00U | tmp);
-
- tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
- reg_pi_mr12_data_fx_csx[fspwp][0]);
- send_dbcmd(0x0e840c00U | tmp);
-
- tmp = ddrtbl_getval(_cnf_DDR_PI_REGSET,
- reg_pi_mr14_data_fx_csx[fspwp][0]);
- send_dbcmd(0x0e840e00U | tmp);
- /* MR22 */
- send_dbcmd(0x0e841616U);
-
- /* ZQCAL start */
- send_dbcmd(0x0d84004FU);
-
- /* ZQLAT */
- send_dbcmd(0x0d840051U);
- }
-
- /* MR13, fspwp */
- send_dbcmd(0x0e840d08U);
-}
-
-/* Training handshake functions */
-static inline uint32_t wait_freqchgreq(uint32_t assert)
-{
- uint32_t data_l;
- uint32_t count;
- uint32_t ch;
-
- count = 100000U;
-
- if (assert != 0U) {
- do {
- data_l = 1U;
- foreach_vch(ch) {
- data_l &= mmio_read_32(DBSC_DBPDSTAT(ch));
- }
- count = count - 1U;
- } while (((data_l & 0x01U) != 0x01U) && (count != 0U));
- } else {
- do {
- data_l = 0U;
- foreach_vch(ch) {
- data_l |= mmio_read_32(DBSC_DBPDSTAT(ch));
- }
- count = count - 1U;
- } while (((data_l & 0x01U) != 0x00U) && (count != 0U));
- }
-
- return (count == 0U);
-}
-
-static inline void set_freqchgack(uint32_t assert)
-{
- uint32_t ch;
- uint32_t data_l;
-
- if (assert != 0U) {
- data_l = 0x0CF20000U;
- } else {
- data_l = 0x00000000U;
- }
-
- foreach_vch(ch) {
- mmio_write_32(DBSC_DBPDCNT2(ch), data_l);
- }
-}
-
-static inline void set_dfifrequency(uint32_t freq)
-{
- uint32_t ch;
-
- foreach_vch(ch) {
- mmio_clrsetbits_32(DBSC_DBDFICNT(ch), 0x1fU << 24, freq << 24);
- }
- dsb_sev();
-}
-
-static uint32_t pll3_freq(uint32_t on)
-{
- uint32_t timeout;
-
- timeout = wait_freqchgreq(1U);
-
- if (timeout != 0U) {
- return 1U;
- }
-
- pll3_control(on);
- set_dfifrequency(on);
-
- set_freqchgack(1U);
- timeout = wait_freqchgreq(0U);
- set_freqchgack(0U);
-
- if (timeout != 0U) {
- FATAL_MSG("BL2: Time out[2]\n");
- return 1U;
- }
-
- return 0U;
-}
-
-/* update dly */
-static void update_dly(void)
-{
- ddr_setval_ach(_reg_SC_PHY_MANUAL_UPDATE, 0x01U);
- ddr_setval_ach(_reg_PHY_ADRCTL_MANUAL_UPDATE, 0x01U);
-}
-
-/* training by pi */
-static uint32_t pi_training_go(void)
-{
- uint32_t flag;
- uint32_t data_l;
- uint32_t retry;
- const uint32_t RETRY_MAX = 4096U * 16U;
- uint32_t ch;
- uint32_t mst_ch;
- uint32_t cur_frq;
- uint32_t complete;
- uint32_t frqchg_req;
-
- /* pi_start */
- ddr_setval_ach(_reg_PI_START, 0x01U);
- foreach_vch(ch) {
- ddr_getval(ch, _reg_PI_INT_STATUS);
- }
-
- /* set dfi_phymstr_ack = 1 */
- mmio_write_32(DBSC_DBDFIPMSTRCNF, 0x00000001U);
- dsb_sev();
-
- /* wait pi_int_status[0] */
- mst_ch = 0U;
- flag = 0U;
- complete = 0U;
- cur_frq = 0U;
- for (retry = 0U; retry < RETRY_MAX; retry++) {
- frqchg_req = mmio_read_32(DBSC_DBPDSTAT(mst_ch)) & 0x01;
-
- if (frqchg_req != 0U) {
- if (cur_frq != 0U) {
- /* Low frequency */
- flag = pll3_freq(0U);
- cur_frq = 0U;
- } else {
- /* High frequency */
- flag = pll3_freq(1U);
- cur_frq = 1U;
- }
- if (flag != 0U) {
- break;
- }
- } else {
- if (cur_frq != 0U) {
- foreach_vch(ch) {
- if ((complete & (1U << ch)) != 0U) {
- continue;
- }
- data_l = ddr_getval(ch, _reg_PI_INT_STATUS);
- if ((data_l & 0x01U) != 0U) {
- complete |= (1U << ch);
- }
- }
- if (complete == ddr_phyvalid) {
- break;
- }
- }
- }
- }
- foreach_vch(ch) {
- /* dummy read */
- data_l = ddr_getval_s(ch, 0U, _reg_PHY_CAL_RESULT2_OBS_0);
- data_l = ddr_getval(ch, _reg_PI_INT_STATUS);
- ddr_setval(ch, _reg_PI_INT_ACK, data_l);
- }
- if (ddrphy_regif_chk() != 0U) {
- complete = 0xfdU;
- }
- return complete;
-}
-
-/* Initialize DDR */
-static uint32_t init_ddr(void)
-{
- uint32_t i;
- uint32_t data_l;
- uint32_t phytrainingok;
- uint32_t ch, slice;
- uint32_t index;
- uint32_t err;
- int16_t adj;
-
- MSG_LF(__func__ ":0\n");
-
- /* unlock phy */
- /* Unlock DDRPHY register(AGAIN) */
- foreach_vch(ch) {
- mmio_write_32(DBSC_DBPDLK(ch), 0x0000A55AU);
- }
- dsb_sev();
-
- reg_ddrphy_write_a(0x00001010U, 0x00000001U);
- /* DBSC register pre-setting */
- dbsc_regset_pre();
-
- /* load ddrphy registers */
- ddrtbl_load();
-
- /* configure ddrphy registers */
- ddr_config();
-
- /* dfi_reset assert */
- foreach_vch(ch) {
- mmio_write_32(DBSC_DBPDCNT0(ch), 0x01U);
- }
- dsb_sev();
-
- /* dbsc register set */
- dbsc_regset();
- MSG_LF(__func__ ":1\n");
-
- /* dfi_reset negate */
- foreach_vch(ch) {
- mmio_write_32(DBSC_DBPDCNT0(ch), 0x00U);
- }
- dsb_sev();
-
- /* dfi_init_start (start ddrphy) */
- err = dfi_init_start();
- if (err != 0U) {
- return INITDRAM_ERR_I;
- }
- MSG_LF(__func__ ":2\n");
-
- /* ddr backupmode end */
-#ifdef DDR_BACKUPMODE
- if (ddr_backup != 0U) {
- NOTICE("BL2: [WARM_BOOT]\n");
- } else {
- NOTICE("BL2: [COLD_BOOT]\n");
- }
-#endif
- MSG_LF(__func__ ":3\n");
-
- /* override term code after dfi_init_complete */
- err = set_term_code();
- if (err != 0U) {
- return INITDRAM_ERR_I;
- }
- MSG_LF(__func__ ":4\n");
-
- /* rx offset calibration */
- if (prr_cut > PRR_PRODUCT_11) {
- err = rx_offset_cal_hw();
- } else {
- err = rx_offset_cal();
- }
- if (err != 0U) {
- return INITDRAM_ERR_O;
- }
- MSG_LF(__func__ ":5\n");
-
- /* Dummy PDE */
- send_dbcmd(0x08840000U);
-
- /* PDX */
- send_dbcmd(0x08840001U);
-
- /* check register i/f is alive */
- err = ddrphy_regif_chk();
- if (err != 0U) {
- return INITDRAM_ERR_O;
- }
- MSG_LF(__func__ ":6\n");
-
- /* phy initialize end */
-
- /* setup DDR mode registers */
- /* CMOS MODE */
- change_lpddr4_en(0);
-
- /* MRS */
- ddr_register_set();
-
- /* Thermal sensor setting */
- /* THCTR Bit6: PONM=0 , Bit0: THSST=1 */
- data_l = (mmio_read_32(THS1_THCTR) & 0xFFFFFFBFU) | 0x00000001U;
- mmio_write_32(THS1_THCTR, data_l);
-
- /* LPDDR4 MODE */
- change_lpddr4_en(1);
-
- MSG_LF(__func__ ":7\n");
-
- /* mask CS_MAP if RANKx is not found */
- foreach_vch(ch) {
- data_l = ddr_getval(ch, _reg_PI_CS_MAP);
- if ((ch_have_this_cs[1] & (1U << ch)) == 0U) {
- data_l = data_l & 0x05U;
- }
- ddr_setval(ch, _reg_PI_CS_MAP, data_l);
- }
-
- /* exec pi_training */
- reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
- BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
- ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00U);
-
- foreach_vch(ch) {
- for (slice = 0U; slice < SLICE_CNT; slice++) {
- ddr_setval_s(ch, slice,
- _reg_PHY_PER_CS_TRAINING_EN,
- ((ch_have_this_cs[1]) >> ch) & 0x01U);
- }
- }
-
- phytrainingok = pi_training_go();
-
- if (ddr_phyvalid != (phytrainingok & ddr_phyvalid)) {
- return INITDRAM_ERR_T | phytrainingok;
- }
-
- MSG_LF(__func__ ":8\n");
-
- /* CACS DLY ADJUST */
- data_l = board_cnf->cacs_dly + (uint32_t)_f_scale_adj(board_cnf->cacs_dly_adj);
- foreach_vch(ch) {
- for (i = 0U; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
- adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[i]);
- ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
- data_l + (uint32_t)adj);
- }
-
- if (ddr_phycaslice == 1U) {
- for (i = 0U; i < 6U; i++) {
- index = i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM;
- adj = _f_scale_adj(board_cnf->ch[ch].cacs_adj[index]);
- ddr_setval_s(ch, 2U,
- _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
- data_l + (uint32_t)adj);
- }
- }
- }
-
- update_dly();
- MSG_LF(__func__ ":9\n");
-
- /* Adjust write path latency */
- if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_WRITE_PATH_LAT_ADD) != 0U) {
- adjust_wpath_latency();
- }
-
- /* RDQLVL Training */
- if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0U) {
- ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x01U);
- }
-
- err = rdqdm_man();
-
- if (ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET, _reg_PHY_IE_MODE) == 0U) {
- ddr_setval_ach_as(_reg_PHY_IE_MODE, 0x00U);
- }
-
- if (err != 0U) {
- return INITDRAM_ERR_T;
- }
- update_dly();
- MSG_LF(__func__ ":10\n");
-
- /* WDQLVL Training */
- err = wdqdm_man();
- if (err != 0U) {
- return INITDRAM_ERR_T;
- }
- update_dly();
- MSG_LF(__func__ ":11\n");
-
- dbsc_regset_post();
- MSG_LF(__func__ ":12\n");
-
- return phytrainingok;
-}
-
-/* SW LEVELING COMMON */
-static uint32_t swlvl1(uint32_t ddr_csn, uint32_t reg_cs, uint32_t reg_kick)
-{
- const uint32_t RETRY_MAX = 0x1000U;
- uint32_t ch, data_l;
- uint32_t waiting;
- uint32_t retry;
- uint32_t err = 0U;
-
- /* set EXIT -> OP_DONE is cleared */
- ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01);
-
- /* kick */
- foreach_vch(ch) {
- if ((ch_have_this_cs[ddr_csn % 2U] & (1U << ch)) != 0U) {
- ddr_setval(ch, reg_cs, ddr_csn);
- ddr_setval(ch, reg_kick, 0x01U);
- }
- }
- foreach_vch(ch) {
- /*PREPARE ADDR REGISTER (for SWLVL_OP_DONE) */
- ddr_getval(ch, _reg_PI_SWLVL_OP_DONE);
- }
- waiting = ch_have_this_cs[ddr_csn % 2U];
- dsb_sev();
- retry = RETRY_MAX;
- do {
- foreach_vch(ch) {
- if ((waiting & (1U << ch)) == 0U) {
- continue;
- }
- data_l = ddr_getval(ch, _reg_PI_SWLVL_OP_DONE);
- if ((data_l & 0x01U) != 0U) {
- waiting &= ~(1U << ch);
- }
- }
- retry--;
- } while ((waiting != 0U) && (retry > 0U));
- if (retry == 0U) {
- err = 1U;
- }
-
- dsb_sev();
- /* set EXIT -> OP_DONE is cleared */
- ddr_setval_ach(_reg_PI_SWLVL_EXIT, 0x01U);
- dsb_sev();
-
- return err;
-}
-
-/* WDQ TRAINING */
-#ifndef DDR_FAST_INIT
-static void wdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
-{
- uint32_t cs, slice;
- uint32_t data_l;
- int32_t i, k;
-
- /* clr of training results buffer */
- cs = ddr_csn % 2U;
- data_l = board_cnf->dqdm_dly_w;
- for (slice = 0U; slice < SLICE_CNT; slice++) {
- k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
- if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) {
- continue;
- }
-
- for (i = 0; i <= 8; i++) {
- if ((ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) != 0U) {
- wdqdm_dly[ch][cs][slice][i] =
- wdqdm_dly[ch][CS_CNT - 1 - cs][slice][i];
- } else {
- wdqdm_dly[ch][cs][slice][i] = data_l;
- }
- wdqdm_le[ch][cs][slice][i] = 0U;
- wdqdm_te[ch][cs][slice][i] = 0U;
- }
- wdqdm_st[ch][cs][slice] = 0U;
- wdqdm_win[ch][cs][slice] = 0U;
- }
-}
-
-static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
-{
- const uint32_t _par_WDQLVL_RETRY_THRES = 0x7c0U;
- uint32_t cs, slice;
- uint32_t data_l;
- int32_t min_win;
- int32_t i, k;
- uint32_t err;
- int32_t win;
- int8_t _adj;
- int16_t adj;
- uint32_t dq;
-
- /* analysis of training results */
- err = 0U;
- for (slice = 0U; slice < SLICE_CNT; slice += 1U) {
- k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
- if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) {
- continue;
- }
-
- cs = ddr_csn % 2U;
- ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs);
- for (i = 0; i < 9; i++) {
- dq = slice * 8U + i;
- if (i == 8) {
- _adj = board_cnf->ch[ch].dm_adj_w[slice];
- } else {
- _adj = board_cnf->ch[ch].dq_adj_w[dq];
- }
- adj = _f_scale_adj(_adj);
-
- data_l =
- ddr_getval_s(ch, slice,
- _reg_PHY_CLK_WRX_SLAVE_DELAY[i]) + adj;
- ddr_setval_s(ch, slice, _reg_PHY_CLK_WRX_SLAVE_DELAY[i],
- data_l);
- wdqdm_dly[ch][cs][slice][i] = data_l;
- }
- ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN, 0x00);
- data_l = ddr_getval_s(ch, slice, _reg_PHY_WDQLVL_STATUS_OBS);
- wdqdm_st[ch][cs][slice] = data_l;
- min_win = INT_LEAST32_MAX;
- for (i = 0; i <= 8; i++) {
- ddr_setval_s(ch, slice, _reg_PHY_WDQLVL_DQDM_OBS_SELECT,
- i);
-
- data_l =
- ddr_getval_s(ch, slice,
- _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS);
- wdqdm_te[ch][cs][slice][i] = data_l;
- data_l =
- ddr_getval_s(ch, slice,
- _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS);
- wdqdm_le[ch][cs][slice][i] = data_l;
- win = (int32_t)wdqdm_te[ch][cs][slice][i] -
- wdqdm_le[ch][cs][slice][i];
- if (min_win > win) {
- min_win = win;
- }
- if (data_l >= _par_WDQLVL_RETRY_THRES) {
- err = 2;
- }
- }
- wdqdm_win[ch][cs][slice] = min_win;
- ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_EN,
- ((ch_have_this_cs[1]) >> ch) & 0x01);
- }
- return err;
-}
-#endif/* DDR_FAST_INIT */
-
-static void wdqdm_cp(uint32_t ddr_csn, uint32_t restore)
-{
- uint32_t tgt_cs, src_cs;
- uint32_t ch, slice;
- uint32_t tmp_r;
- uint32_t i;
-
- /* copy of training results */
- foreach_vch(ch) {
- for (tgt_cs = 0U; tgt_cs < CS_CNT; tgt_cs++) {
- for (slice = 0U; slice < SLICE_CNT; slice++) {
- ddr_setval_s(ch, slice,
- _reg_PHY_PER_CS_TRAINING_INDEX,
- tgt_cs);
- src_cs = ddr_csn % 2U;
- if ((ch_have_this_cs[1] & (1U << ch)) == 0U) {
- src_cs = 0U;
- }
- for (i = 0U; i <= 4U; i += 4U) {
- if (restore != 0U) {
- tmp_r = rdqdm_dly[ch][tgt_cs][slice][i];
- } else {
- tmp_r = rdqdm_dly[ch][src_cs][slice][i];
- }
-
- ddr_setval_s(ch, slice,
- _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i],
- tmp_r);
- }
- }
- }
- }
-}
-
-static uint32_t wdqdm_man1(void)
-{
- uint32_t mr14_csab0_bak[DRAM_CH_CNT];
- uint32_t ch, cs, ddr_csn;
- uint32_t data_l;
- uint32_t err = 0U;
-#ifndef DDR_FAST_INIT
- uint32_t err_flg = 0U;
-#endif/* DDR_FAST_INIT */
-
- /* CLEAR PREV RESULT */
- for (cs = 0U; cs < CS_CNT; cs++) {
- ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_INDEX, cs);
- ddr_setval_ach_as(_reg_PHY_WDQLVL_CLR_PREV_RESULTS, 0x01U);
- }
- ddrphy_regif_idle();
-
- for (ddr_csn = 0U; ddr_csn < CSAB_CNT; ddr_csn++) {
- if (((prr_product == PRR_PRODUCT_M3) &&
- (prr_cut == PRR_PRODUCT_10))) {
- wdqdm_cp(ddr_csn, 0U);
- }
-
- foreach_vch(ch) {
- data_l = ddr_getval(ch, reg_pi_mr14_data_fx_csx[1][ddr_csn]);
- ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0], data_l);
- }
-
- /* KICK WDQLVL */
- err = swlvl1(ddr_csn, _reg_PI_WDQLVL_CS, _reg_PI_WDQLVL_REQ);
- if (err != 0U) {
- goto err_exit;
- }
-
- if (ddr_csn == 0U) {
- foreach_vch(ch) {
- mr14_csab0_bak[ch] = ddr_getval(ch,
- reg_pi_mr14_data_fx_csx[1][0]);
- }
- } else {
- foreach_vch(ch) {
- ddr_setval(ch, reg_pi_mr14_data_fx_csx[1][0],
- mr14_csab0_bak[ch]);
- }
- }
-#ifndef DDR_FAST_INIT
- foreach_vch(ch) {
- if ((ch_have_this_cs[ddr_csn % 2U] & (1U << ch)) == 0U) {
- wdqdm_clr1(ch, ddr_csn);
- continue;
- }
- err = wdqdm_ana1(ch, ddr_csn);
- if (err != 0U) {
- err_flg |= (1U << (ddr_csn * 4U + ch));
- }
- ddrphy_regif_idle();
- }
-#endif/* DDR_FAST_INIT */
- }
-err_exit:
-#ifndef DDR_FAST_INIT
- err |= err_flg;
-#endif/* DDR_FAST_INIT */
-
- return err;
-}
-
-static uint32_t wdqdm_man(void)
-{
- uint32_t datal, ch, ddr_csn, mr14_bkup[4][4];
- const uint32_t retry_max = 0x10U;
- uint32_t err, retry_cnt;
-
- datal = RL + js2[js2_tdqsck] + (16U / 2U) + 1U - WL + 2U + 2U + 19U;
- if ((mmio_read_32(DBSC_DBTR(11)) & 0xFF) > datal) {
- datal = mmio_read_32(DBSC_DBTR(11)) & 0xFF;
- }
- ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, datal);
-
- ddr_setval_ach(_reg_PI_TDFI_WDQLVL_WR,
- (mmio_read_32(DBSC_DBTR(12)) & 0xFF) + 10);
-
- ddr_setval_ach(_reg_PI_TRFC_F0, mmio_read_32(DBSC_DBTR(13)) & 0x1FF);
- ddr_setval_ach(_reg_PI_TRFC_F1, mmio_read_32(DBSC_DBTR(13)) & 0x1FF);
-
- retry_cnt = 0U;
- err = 0U;
- do {
- ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01);
- ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 0x01);
- ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x0C);
- dsb_sev();
- err = wdqdm_man1();
- foreach_vch(ch) {
- for (ddr_csn = 0U; ddr_csn < CSAB_CNT; ddr_csn++) {
- mr14_bkup[ch][ddr_csn] =
- ddr_getval(ch, reg_pi_mr14_data_fx_csx
- [1][ddr_csn]);
- dsb_sev();
- }
- }
-
- ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x04);
-
- pvtcode_update();
- err = wdqdm_man1();
- foreach_vch(ch) {
- for (ddr_csn = 0U; ddr_csn < CSAB_CNT; ddr_csn++) {
- mr14_bkup[ch][ddr_csn] =
- (mr14_bkup[ch][ddr_csn] +
- ddr_getval(ch, reg_pi_mr14_data_fx_csx
- [1][ddr_csn])) / 2U;
- ddr_setval(ch,
- reg_pi_mr14_data_fx_csx[1]
- [ddr_csn],
- mr14_bkup[ch][ddr_csn]);
- }
- }
-
- ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE, 0x0U);
- ddr_setval_ach(_reg_PI_WDQLVL_VREF_DELTA, 0x0U);
- ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_START_POINT, 0x0U);
- ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT, 0x0U);
- ddr_setval_ach(_reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE, 0x0U);
-
- pvtcode_update2();
- err = wdqdm_man1();
- ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x0U);
-
- } while ((err != 0U) && (++retry_cnt < retry_max));
-
- if (prr_product == PRR_PRODUCT_M3 && prr_cut <= PRR_PRODUCT_10) {
- wdqdm_cp(0U, 1U);
- }
-
- return (retry_cnt >= retry_max);
-}
-
-/* RDQ TRAINING */
-#ifndef DDR_FAST_INIT
-static void rdqdm_clr1(uint32_t ch, uint32_t ddr_csn)
-{
- uint32_t cs, slice;
- uint32_t data_l;
- int32_t i, k;
-
- /* clr of training results buffer */
- cs = ddr_csn % 2U;
- data_l = board_cnf->dqdm_dly_r;
- for (slice = 0U; slice < SLICE_CNT; slice++) {
- k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
- if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) {
- continue;
- }
-
- for (i = 0; i <= 8; i++) {
- if ((ch_have_this_cs[CS_CNT - 1 - cs] & (1U << ch)) != 0U) {
- rdqdm_dly[ch][cs][slice][i] =
- rdqdm_dly[ch][CS_CNT - 1 - cs][slice][i];
- rdqdm_dly[ch][cs][slice + SLICE_CNT][i] =
- rdqdm_dly[ch][CS_CNT - 1 - cs][slice + SLICE_CNT][i];
- } else {
- rdqdm_dly[ch][cs][slice][i] = data_l;
- rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l;
- }
- rdqdm_le[ch][cs][slice][i] = 0U;
- rdqdm_le[ch][cs][slice + SLICE_CNT][i] = 0U;
- rdqdm_te[ch][cs][slice][i] = 0U;
- rdqdm_te[ch][cs][slice + SLICE_CNT][i] = 0U;
- rdqdm_nw[ch][cs][slice][i] = 0U;
- rdqdm_nw[ch][cs][slice + SLICE_CNT][i] = 0U;
- }
- rdqdm_st[ch][cs][slice] = 0U;
- rdqdm_win[ch][cs][slice] = 0U;
- }
-}
-
-static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
-{
- uint32_t rdq_status_obs_select;
- uint32_t cs, slice;
- uint32_t data_l;
- uint32_t err;
- uint32_t dq;
- int32_t min_win;
- int8_t _adj;
- int16_t adj;
- int32_t min_win;
- int32_t win;
- int32_t i, k;
-
- /* analysis of training results */
- err = 0U;
- for (slice = 0U; slice < SLICE_CNT; slice++) {
- k = (board_cnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
- if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2))) {
- continue;
- }
-
- cs = ddr_csn % 2U;
- ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, cs);
- ddrphy_regif_idle();
-
- ddr_getval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX);
- ddrphy_regif_idle();
-
- for (i = 0; i <= 8; i++) {
- dq = slice * 8 + i;
- if (i == 8) {
- _adj = board_cnf->ch[ch].dm_adj_r[slice];
- } else {
- _adj = board_cnf->ch[ch].dq_adj_r[dq];
- }
-
- adj = _f_scale_adj(_adj);
-
- data_l = ddr_getval_s(ch, slice,
- _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj;
- ddr_setval_s(ch, slice,
- _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i],
- data_l);
- rdqdm_dly[ch][cs][slice][i] = data_l;
-
- data_l = ddr_getval_s(ch, slice,
- _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj;
- ddr_setval_s(ch, slice,
- _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i],
- data_l);
- rdqdm_dly[ch][cs][slice + SLICE_CNT][i] = data_l;
- }
- min_win = INT_LEAST32_MAX;
- for (i = 0; i <= 8; i++) {
- data_l =
- ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS);
- rdqdm_st[ch][cs][slice] = data_l;
- rdqdm_st[ch][cs][slice + SLICE_CNT] = data_l;
- /* k : rise/fall */
- for (k = 0; k < 2; k++) {
- if (i == 8) {
- rdq_status_obs_select = 16 + 8 * k;
- } else {
- rdq_status_obs_select = i + k * 8;
- }
- ddr_setval_s(ch, slice,
- _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT,
- rdq_status_obs_select);
-
- data_l =
- ddr_getval_s(ch, slice,
- _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS);
- rdqdm_le[ch][cs][slice + SLICE_CNT * k][i] = data_l;
-
- data_l =
- ddr_getval_s(ch, slice,
- _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS);
- rdqdm_te[ch][cs][slice + SLICE_CNT * k][i] = data_l;
-
- data_l =
- ddr_getval_s(ch, slice,
- _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS);
- rdqdm_nw[ch][cs][slice + SLICE_CNT * k][i] = data_l;
-
- win =
- (int32_t)rdqdm_te[ch][cs][slice +
- SLICE_CNT *
- k][i] -
- rdqdm_le[ch][cs][slice + SLICE_CNT * k][i];
- if (i != 8) {
- if (min_win > win) {
- min_win = win;
- }
- }
- }
- }
- rdqdm_win[ch][cs][slice] = min_win;
- if (min_win <= 0) {
- err = 2;
- }
- }
- return err;
-}
-#else /* DDR_FAST_INIT */
-static void rdqdm_man1_set(uint32_t ddr_csn, uint32_t ch, uint32_t slice)
-{
- uint32_t i, adj, data_l;
-
- for (i = 0U; i <= 8U; i++) {
- if (i == 8U) {
- adj = _f_scale_adj(board_cnf->ch[ch].dm_adj_r[slice]);
- } else {
- adj = _f_scale_adj(board_cnf->ch[ch].dq_adj_r[slice * 8U + i]);
- }
- ddr_setval_s(ch, slice, _reg_PHY_PER_CS_TRAINING_INDEX, ddr_csn);
- data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i]) + adj;
- ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_RISE_SLAVE_DELAY[i], data_l);
- rdqdm_dly[ch][ddr_csn][slice][i] = data_l;
- rdqdm_dly[ch][ddr_csn | 1U][slice][i] = data_l;
-
- data_l = ddr_getval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i]) + adj;
- ddr_setval_s(ch, slice, _reg_PHY_RDDQS_X_FALL_SLAVE_DELAY[i], data_l);
- rdqdm_dly[ch][ddr_csn][slice + SLICE_CNT][i] = data_l;
- rdqdm_dly[ch][ddr_csn | 1U][slice + SLICE_CNT][i] = data_l;
- }
-}
-#endif /* DDR_FAST_INIT */
-
-static uint32_t rdqdm_man1(void)
-{
- uint32_t ch;
- uint32_t ddr_csn;
- uint32_t val;
-#ifdef DDR_FAST_INIT
- uint32_t slice;
-#endif/* DDR_FAST_INIT */
- uint32_t err;
-
- /* manual execution of training */
- err = 0U;
-
- for (ddr_csn = 0U; ddr_csn < CSAB_CNT; ddr_csn++) {
- /* KICK RDQLVL */
- err = swlvl1(ddr_csn, _reg_PI_RDLVL_CS, _reg_PI_RDLVL_REQ);
- if (err != 0U) {
- goto err_exit;
- }
-#ifndef DDR_FAST_INIT
- foreach_vch(ch) {
- if ((ch_have_this_cs[ddr_csn % 2] & (1U << ch)) == 0U) {
- rdqdm_clr1(ch, ddr_csn);
- ddrphy_regif_idle();
- continue;
- }
- err = rdqdm_ana1(ch, ddr_csn);
- ddrphy_regif_idle();
- if (err != 0U) {
- goto err_exit;
- }
- }
-#else/* DDR_FAST_INIT */
- foreach_vch(ch) {
- if ((ch_have_this_cs[ddr_csn] & (1U << ch)) != 0U) {
- for (slice = 0U; slice < SLICE_CNT; slice++) {
- val = ddr_getval_s(ch, slice, _reg_PHY_RDLVL_STATUS_OBS);
- if (val != 0x0D00FFFFU) {
- err = (1U << ch) | (0x10U << slice);
- goto err_exit;
- }
- }
- }
- if ((prr_product == PRR_PRODUCT_M3) &&
- (prr_cut <= PRR_PRODUCT_10)) {
- for (slice = 0U; slice < SLICE_CNT; slice++) {
- rdqdm_man1_set(ddr_csn, ch, slice);
- }
- }
- }
- ddrphy_regif_idle();
-
-#endif/* DDR_FAST_INIT */
- }
-
-err_exit:
- return err;
-}
-
-static uint32_t rdqdm_man(void)
-{
- uint32_t err, retry_cnt;
- const uint32_t retry_max = 0x01U;
-
- ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE,
- 0x00000004U | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_PHY_DQ_TSEL_ENABLE));
- ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE,
- 0x00000004U | ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_PHY_DQS_TSEL_ENABLE));
- ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT,
- 0xFF0FFFFFU & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_PHY_DQ_TSEL_SELECT));
- ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT,
- 0xFF0FFFFFU & ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_PHY_DQS_TSEL_SELECT));
-
- retry_cnt = 0U;
- do {
- err = rdqdm_man1();
- ddrphy_regif_idle();
- } while ((err != 0U) && (++retry_cnt < retry_max));
- ddr_setval_ach_as(_reg_PHY_DQ_TSEL_ENABLE,
- ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_PHY_DQ_TSEL_ENABLE));
- ddr_setval_ach_as(_reg_PHY_DQS_TSEL_ENABLE,
- ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_PHY_DQS_TSEL_ENABLE));
- ddr_setval_ach_as(_reg_PHY_DQ_TSEL_SELECT,
- ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_PHY_DQ_TSEL_SELECT));
- ddr_setval_ach_as(_reg_PHY_DQS_TSEL_SELECT,
- ddrtbl_getval(_cnf_DDR_PHY_SLICE_REGSET,
- _reg_PHY_DQS_TSEL_SELECT));
-
- return (retry_cnt >= retry_max);
-}
-
-/* rx offset calibration */
-static int32_t _find_change(uint64_t val, uint32_t dir)
-{
- int32_t i;
- uint32_t startval;
- uint32_t curval;
- const int32_t VAL_END = 0x3fU;
-
- if (dir == 0U) {
- startval = (val & 0x01U);
- for (i = 1; i <= VAL_END; i++) {
- curval = (val >> i) & 0x01U;
- if (curval != startval) {
- return i;
- }
- }
- return VAL_END;
- }
-
- startval = (val >> dir) & 0x01U;
- for (i = (int32_t)dir - 1; i >= 0; i--) {
- curval = (val >> i) & 0x01U;
- if (curval != startval) {
- return i;
- }
- }
-
- return 0;
-}
-
-static uint32_t _rx_offset_cal_updn(uint32_t code)
-{
- const uint32_t CODE_MAX = 0x40U;
- uint32_t tmp;
-
- if (code == 0U) {
- tmp = (1U << 6) | (CODE_MAX - 1U);
- } else {
- tmp = (code << 6) | (CODE_MAX - code);
- }
-
- return tmp;
-}
-
-static uint32_t rx_offset_cal(void)
-{
- uint32_t index;
- uint32_t code;
- const uint32_t CODE_MAX = 0x40U;
- const uint32_t CODE_STEP = 2U;
- uint32_t ch, slice;
- uint32_t tmp;
- uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT];
- uint64_t val[DRAM_CH_CNT][SLICE_CNT][_reg_PHY_RX_CAL_X_NUM];
- uint64_t tmpval;
- int32_t lsb, msb;
-
- ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x01);
- foreach_vch(ch) {
- for (slice = 0U; slice < SLICE_CNT; slice++) {
- for (index = 0U; index < _reg_PHY_RX_CAL_X_NUM; index++) {
- val[ch][slice][index] = 0U;
- }
- }
- }
-
- for (code = 0U; code < CODE_MAX / CODE_STEP; code++) {
- tmp = _rx_offset_cal_updn(code * CODE_STEP);
- for (index = 0U; index < _reg_PHY_RX_CAL_X_NUM; index++) {
- ddr_setval_ach_as(_reg_PHY_RX_CAL_X[index], tmp);
- }
- dsb_sev();
- ddr_getval_ach_as(_reg_PHY_RX_CAL_OBS, (uint32_t *)tmp_ach_as);
-
- foreach_vch(ch) {
- for (slice = 0U; slice < SLICE_CNT; slice++) {
- tmp = tmp_ach_as[ch][slice];
- for (index = 0U; index < _reg_PHY_RX_CAL_X_NUM;
- index++) {
- if ((tmp & (1U << index)) != 0U) {
- val[ch][slice][index] |=
- (1ULL << code);
- } else {
- val[ch][slice][index] &=
- ~(1ULL << code);
- }
- }
- }
- }
- }
- foreach_vch(ch) {
- for (slice = 0U; slice < SLICE_CNT; slice++) {
- for (index = 0U; index < _reg_PHY_RX_CAL_X_NUM;
- index++) {
- tmpval = val[ch][slice][index];
- lsb = _find_change(tmpval, 0U);
- msb = _find_change(tmpval,
- (CODE_MAX / CODE_STEP) - 1U);
- tmp = (lsb + msb) >> 1U;
-
- tmp = _rx_offset_cal_updn(tmp * CODE_STEP);
- ddr_setval_s(ch, slice,
- _reg_PHY_RX_CAL_X[index], tmp);
- }
- }
- }
- ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00);
-
- return 0U;
-}
-
-static uint32_t rx_offset_cal_hw(void)
-{
- uint32_t ch, slice;
- uint32_t retry;
- uint32_t complete;
- uint32_t tmp;
- uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT];
-
- ddr_setval_ach_as(_reg_PHY_RX_CAL_X[9], 0x00);
- ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x00);
- ddr_setval_ach_as(_reg_PHY_RX_CAL_SAMPLE_WAIT, 0x0f);
-
- retry = 0U;
- while (retry < 4096U) {
- if ((retry & 0xffU) == 0U) {
- ddr_setval_ach_as(_reg_SC_PHY_RX_CAL_START, 0x01);
- }
- foreach_vch(ch) {
- for (slice = 0U; slice < SLICE_CNT; slice++) {
- tmp_ach_as[ch][slice] =
- ddr_getval_s(ch, slice,
- _reg_PHY_RX_CAL_X[9]);
- }
- }
-
- complete = 1U;
- foreach_vch(ch) {
- for (slice = 0U; slice < SLICE_CNT; slice++) {
- tmp = tmp_ach_as[ch][slice];
- tmp = (tmp & 0x3fU) + ((tmp >> 6) & 0x3fU);
- if (tmp != 0x40U) {
- complete = 0U;
- }
- }
- }
- if (complete != 0U) {
- break;
- }
-
- retry++;
- }
-
- return (complete == 0U);
-}
-
-/* adjust wpath latency */
-static void adjust_wpath_latency(void)
-{
- uint32_t ch, cs, slice;
- uint32_t dly;
- uint32_t wpath_add;
- const uint32_t _par_EARLY_THRESHOLD_VAL = 0x180U;
-
- foreach_vch(ch) {
- for (slice = 0U; slice < SLICE_CNT; slice += 1U) {
- for (cs = 0U; cs < CS_CNT; cs++) {
- ddr_setval_s(ch, slice,
- _reg_PHY_PER_CS_TRAINING_INDEX,
- cs);
- ddr_getval_s(ch, slice,
- _reg_PHY_PER_CS_TRAINING_INDEX);
- dly =
- ddr_getval_s(ch, slice,
- _reg_PHY_CLK_WRDQS_SLAVE_DELAY);
- if (dly <= _par_EARLY_THRESHOLD_VAL) {
- continue;
- }
-
- wpath_add =
- ddr_getval_s(ch, slice,
- _reg_PHY_WRITE_PATH_LAT_ADD);
- ddr_setval_s(ch, slice,
- _reg_PHY_WRITE_PATH_LAT_ADD,
- wpath_add - 1U);
- }
- }
- }
-}
-
-/* DDR Initialize entry */
-int32_t rzg_dram_init(void)
-{
- uint32_t ch, cs;
- uint32_t data_l;
- uint32_t bus_mbps, bus_mbpsdiv;
- uint32_t tmp_tccd;
- uint32_t failcount;
- uint32_t cnf_boardtype;
- int32_t ret = INITDRAM_NG;
-
- /* Thermal sensor setting */
- data_l = mmio_read_32(CPG_MSTPSR5);
- if ((data_l & BIT(22)) != 0U) { /* case THS/TSC Standby */
- data_l &= ~BIT(22);
- cpg_write_32(CPG_SMSTPCR5, data_l);
- while ((mmio_read_32(CPG_MSTPSR5) & BIT(22)) != 0U) {
- /* wait bit=0 */
- }
- }
-
- /* THCTR Bit6: PONM=0 , Bit0: THSST=0 */
- data_l = mmio_read_32(THS1_THCTR) & 0xFFFFFFBE;
- mmio_write_32(THS1_THCTR, data_l);
-
- /* Judge product and cut */
-#ifdef RCAR_DDR_FIXED_LSI_TYPE
-#if (RCAR_LSI == RCAR_AUTO)
- prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
- prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
-#else /* RCAR_LSI */
-#ifndef RCAR_LSI_CUT
- prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
-#endif /* RCAR_LSI_CUT */
-#endif /* RCAR_LSI */
-#else /* RCAR_DDR_FIXED_LSI_TYPE */
- prr_product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
- prr_cut = mmio_read_32(PRR) & PRR_CUT_MASK;
-#endif /* RCAR_DDR_FIXED_LSI_TYPE */
-
- if (prr_product == PRR_PRODUCT_M3) {
- p_ddr_regdef_tbl =
- (const uint32_t *)&DDR_REGDEF_TBL[1][0];
- } else {
- FATAL_MSG("BL2: DDR:Unknown Product\n");
- goto done;
- }
-
- if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) {
- /* non : G2M Ver.1.x not support */
- } else {
- mmio_write_32(DBSC_DBSYSCNT0, 0x00001234U);
- }
-
- /* Judge board type */
- cnf_boardtype = boardcnf_get_brd_type(prr_product);
- if (cnf_boardtype >= (uint32_t)BOARDNUM) {
- FATAL_MSG("BL2: DDR:Unknown Board\n");
- goto done;
- }
- board_cnf = (const struct _boardcnf *)&boardcnfs[cnf_boardtype];
-
-/* RCAR_DRAM_SPLIT_2CH (2U) */
-#if RCAR_DRAM_SPLIT == 2
- ddr_phyvalid = board_cnf->phyvalid;
-#else /* RCAR_DRAM_SPLIT_2CH */
- ddr_phyvalid = board_cnf->phyvalid;
-#endif /* RCAR_DRAM_SPLIT_2CH */
-
- max_density = 0U;
-
- for (cs = 0U; cs < CS_CNT; cs++) {
- ch_have_this_cs[cs] = 0U;
- }
-
- foreach_ech(ch) {
- for (cs = 0U; cs < CS_CNT; cs++) {
- ddr_density[ch][cs] = 0xffU;
- }
- }
-
- foreach_vch(ch) {
- for (cs = 0U; cs < CS_CNT; cs++) {
- data_l = board_cnf->ch[ch].ddr_density[cs];
- ddr_density[ch][cs] = data_l;
-
- if (data_l == 0xffU) {
- continue;
- }
- if (data_l > max_density) {
- max_density = data_l;
- }
- ch_have_this_cs[cs] |= (1U << ch);
- }
- }
-
- /* Judge board clock frequency (in MHz) */
- boardcnf_get_brd_clk(cnf_boardtype, &brd_clk, &brd_clkdiv);
- if ((brd_clk / brd_clkdiv) > 25U) {
- brd_clkdiva = 1U;
- } else {
- brd_clkdiva = 0U;
- }
-
- /* Judge ddr operating frequency clock(in Mbps) */
- boardcnf_get_ddr_mbps(cnf_boardtype, &ddr_mbps, &ddr_mbpsdiv);
-
- ddr0800_mul = CLK_DIV(800U, 2U, brd_clk, brd_clkdiv * (brd_clkdiva + 1U));
-
- ddr_mul = CLK_DIV(ddr_mbps, ddr_mbpsdiv * 2U, brd_clk,
- brd_clkdiv * (brd_clkdiva + 1U));
-
- /* Adjust tccd */
- data_l = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13;
- bus_mbps = 0U;
- bus_mbpsdiv = 0U;
- switch (data_l) {
- case 0:
- bus_mbps = brd_clk * 0x60U * 2U;
- bus_mbpsdiv = brd_clkdiv * 1U;
- break;
- case 1:
- bus_mbps = brd_clk * 0x50U * 2U;
- bus_mbpsdiv = brd_clkdiv * 1U;
- break;
- case 2:
- bus_mbps = brd_clk * 0x40U * 2U;
- bus_mbpsdiv = brd_clkdiv * 1U;
- break;
- case 3:
- bus_mbps = brd_clk * 0x60U * 2U;
- bus_mbpsdiv = brd_clkdiv * 2U;
- break;
- default:
- bus_mbps = brd_clk * 0x60U * 2U;
- bus_mbpsdiv = brd_clkdiv * 2U;
- WARN("BL2: DDR using default values for adjusting tccd");
- break;
- }
- tmp_tccd = CLK_DIV(ddr_mbps * 8U, ddr_mbpsdiv, bus_mbps, bus_mbpsdiv);
- if (8U * ddr_mbps * bus_mbpsdiv != tmp_tccd * bus_mbps * ddr_mbpsdiv) {
- tmp_tccd = tmp_tccd + 1U;
- }
-
- if (tmp_tccd < 8U) {
- ddr_tccd = 8U;
- } else {
- ddr_tccd = tmp_tccd;
- }
-
- NOTICE("BL2: DDR%d(%s)\n", ddr_mbps / ddr_mbpsdiv, RCAR_DDR_VERSION);
-
- MSG_LF("Start\n");
-
- /* PLL Setting */
- pll3_control(1U);
-
- /* initialize DDR */
- data_l = init_ddr();
- if (data_l == ddr_phyvalid) {
- failcount = 0U;
- } else {
- failcount = 1U;
- }
-
- foreach_vch(ch) {
- mmio_write_32(DBSC_DBPDLK(ch), 0x00000000U);
- }
- if ((prr_product == PRR_PRODUCT_M3) && (prr_cut < PRR_PRODUCT_30)) {
- /* non : G2M Ver.1.x not support */
- } else {
- mmio_write_32(DBSC_DBSYSCNT0, 0x00000000);
- }
-
- if (failcount == 0U) {
- ret = INITDRAM_OK;
- }
-
-done:
- return ret;
-}
-
-static void pvtcode_update(void)
-{
- uint32_t ch;
- uint32_t data_l;
- uint32_t pvtp[4], pvtn[4], pvtp_init, pvtn_init;
- int32_t pvtp_tmp, pvtn_tmp;
-
- foreach_vch(ch) {
- pvtn_init = (tcal.tcomp_cal[ch] & 0xFC0U) >> 6;
- pvtp_init = (tcal.tcomp_cal[ch] & 0x03FU) >> 0;
-
- if (8912U * pvtp_init > 44230U) {
- pvtp_tmp = (5000U + 8912U * pvtp_init - 44230U) / 10000U;
- } else {
- pvtp_tmp =
- -((-(5000 + 8912 * pvtp_init - 44230)) / 10000);
- }
- pvtn_tmp = (5000U + 5776U * (uint32_t)pvtn_init + 30280U) / 10000U;
-
- pvtn[ch] = (uint32_t)pvtn_tmp + pvtn_init;
- pvtp[ch] = (uint32_t)pvtp_tmp + pvtp_init;
-
- if (pvtn[ch] > 63U) {
- pvtn[ch] = 63U;
- pvtp[ch] =
- (pvtp_tmp) * (63 - 6 * pvtn_tmp -
- pvtn_init) / (pvtn_tmp) +
- 6 * pvtp_tmp + pvtp_init;
- }
-
- data_l = pvtp[ch] | (pvtn[ch] << 6) | 0x00015000U;
- reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
- data_l | 0x00020000U);
- reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
- data_l);
- reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
- data_l);
- reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
- data_l);
- reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
- data_l);
- }
-}
-
-static void pvtcode_update2(void)
-{
- uint32_t ch;
-
- foreach_vch(ch) {
- reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_FDBK_TERM),
- tcal.init_cal[ch] | 0x00020000U);
- reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DATA_TERM),
- tcal.init_cal[ch]);
- reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_DQS_TERM),
- tcal.init_cal[ch]);
- reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_ADDR_TERM),
- tcal.init_cal[ch]);
- reg_ddrphy_write(ch, ddr_regdef_adr(_reg_PHY_PAD_CS_TERM),
- tcal.init_cal[ch]);
- }
-}
-
-static void ddr_padcal_tcompensate_getinit(uint32_t override)
-{
- uint32_t ch;
- uint32_t data_l;
- uint32_t pvtp, pvtn;
-
- tcal.init_temp = 0;
- for (ch = 0U; ch < 4U; ch++) {
- tcal.init_cal[ch] = 0U;
- tcal.tcomp_cal[ch] = 0U;
- }
-
- foreach_vch(ch) {
- tcal.init_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]);
- tcal.tcomp_cal[ch] = ddr_getval(ch, _reg_PHY_PAD_TERM_X[1]);
- }
-
- if (override == 0U) {
- data_l = mmio_read_32(THS1_TEMP);
- if (data_l < 2800U) {
- tcal.init_temp =
- (143 * (int32_t)data_l - 359000) / 1000;
- } else {
- tcal.init_temp =
- (121 * (int32_t)data_l - 296300) / 1000;
- }
-
- foreach_vch(ch) {
- pvtp = (tcal.init_cal[ch] >> 0) & 0x000003FU;
- pvtn = (tcal.init_cal[ch] >> 6) & 0x000003FU;
- if ((int32_t)pvtp >
- ((tcal.init_temp * 29 - 3625) / 1000)) {
- pvtp = (int32_t)pvtp +
- ((3625 - tcal.init_temp * 29) / 1000);
- } else {
- pvtp = 0U;
- }
-
- if ((int32_t)pvtn >
- ((tcal.init_temp * 54 - 6750) / 1000)) {
- pvtn = (int32_t)pvtn +
- ((6750 - tcal.init_temp * 54) / 1000);
- } else {
- pvtn = 0U;
- }
-
- tcal.init_cal[ch] = 0x00015000U | (pvtn << 6) | pvtp;
- }
- tcal.init_temp = 125;
- }
-}
-
-#ifndef DDR_QOS_INIT_SETTING
-/* For QoS init */
-uint8_t rzg_get_boardcnf_phyvalid(void)
-{
- return ddr_phyvalid;
-}
-#endif /* DDR_QOS_INIT_SETTING */
diff --git a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_config.c b/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_config.c
deleted file mode 100644
index 345ef24..0000000
--- a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_config.c
+++ /dev/null
@@ -1,277 +0,0 @@
-/*
- * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#define BOARDNUM 2
-#define BOARD_JUDGE_AUTO
-
-#ifdef BOARD_JUDGE_AUTO
-static uint32_t _board_judge(uint32_t prr_product);
-
-static uint32_t boardcnf_get_brd_type(uint32_t prr_product)
-{
- return _board_judge(prr_product);
-}
-#else /* BOARD_JUDGE_AUTO */
-static uint32_t boardcnf_get_brd_type(void)
-{
- return 1U;
-}
-#endif /* BOARD_JUDGE_AUTO */
-
-#define DDR_FAST_INIT
-
-struct _boardcnf_ch {
- uint8_t ddr_density[CS_CNT];
- uint64_t ca_swap;
- uint16_t dqs_swap;
- uint32_t dq_swap[SLICE_CNT];
- uint8_t dm_swap[SLICE_CNT];
- uint16_t wdqlvl_patt[16];
- int8_t cacs_adj[16];
- int8_t dm_adj_w[SLICE_CNT];
- int8_t dq_adj_w[SLICE_CNT * 8U];
- int8_t dm_adj_r[SLICE_CNT];
- int8_t dq_adj_r[SLICE_CNT * 8U];
-};
-
-struct _boardcnf {
- uint8_t phyvalid;
- uint8_t dbi_en;
- uint16_t cacs_dly;
- int16_t cacs_dly_adj;
- uint16_t dqdm_dly_w;
- uint16_t dqdm_dly_r;
- struct _boardcnf_ch ch[DRAM_CH_CNT];
-};
-
-#define WDQLVL_PAT {\
- 0x00AA,\
- 0x0055,\
- 0x00AA,\
- 0x0155,\
- 0x01CC,\
- 0x0133,\
- 0x00CC,\
- 0x0033,\
- 0x00F0,\
- 0x010F,\
- 0x01F0,\
- 0x010F,\
- 0x00F0,\
- 0x00F0,\
- 0x000F,\
- 0x010F}
-
-static const struct _boardcnf boardcnfs[BOARDNUM] = {
- {
-/* boardcnf[0] HopeRun HiHope RZ/G2M 16Gbit/1rank/2ch board with G2M SoC */
- .phyvalid = 0x03,
- .dbi_en = 0x01,
- .cacs_dly = 0x02c0,
- .cacs_dly_adj = 0,
- .dqdm_dly_w = 0x0300,
- .dqdm_dly_r = 0x00a0,
- .ch = {
- {
- {0x04, 0xff},
- 0x00345201U,
- 0x3201,
- {0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
-
- {
- {0x04, 0xff},
- 0x00302154U,
- 0x2310,
- {0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- },
-/* boardcnf[1] HopeRun HiHope RZ/G2M 8Gbit/2rank/2ch board with G2M SoC */
- {
- 0x03,
- 0x01,
- 0x02c0,
- 0,
- 0x0300,
- 0x00a0,
- {
- {
- {0x02, 0x02},
- 0x00345201U,
- 0x3201,
- {0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- },
- {
- {0x02, 0x02},
- 0x00302154U,
- 0x2310,
- {0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
- {0x08, 0x08, 0x08, 0x08},
- WDQLVL_PAT,
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0},
- {0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0}
- }
- }
- }
-};
-
-void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div)
-{
- uint32_t md;
-
- md = (mmio_read_32(RST_MODEMR) >> 13) & 0x3U;
- switch (md) {
- case 0x0U:
- *clk = 50U;
- *div = 3U;
- break;
- case 0x1U:
- *clk = 60U;
- *div = 3U;
- break;
- case 0x2U:
- *clk = 75U;
- *div = 3U;
- break;
- case 0x3U:
- *clk = 100U;
- *div = 3U;
- break;
- default:
- break;
- }
- (void)brd;
-}
-
-void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div)
-{
- uint32_t md;
-
- md = (mmio_read_32(RST_MODEMR) >> 17U) & 0x5U;
- md = (md | (md >> 1U)) & 0x3U;
- switch (md) {
- case 0x0U:
- *mbps = 3200U;
- *div = 1U;
- break;
- case 0x1U:
- *mbps = 2800U;
- *div = 1U;
- break;
- case 0x2U:
- *mbps = 2400U;
- *div = 1U;
- break;
- case 0x3U:
- *mbps = 1600U;
- *div = 1U;
- break;
- default:
- break;
- }
- (void)brd;
-}
-
-#define _def_REFPERIOD 1890
-
-#define M3_SAMPLE_TT_A84 0xB866CC10U, 0x3B250421U
-#define M3_SAMPLE_TT_A85 0xB866CC10U, 0x3AA50421U
-#define M3_SAMPLE_TT_A86 0xB866CC10U, 0x3AA48421U
-#define M3_SAMPLE_FF_B45 0xB866CC10U, 0x3AB00C21U
-#define M3_SAMPLE_FF_B49 0xB866CC10U, 0x39B10C21U
-#define M3_SAMPLE_FF_B56 0xB866CC10U, 0x3AAF8C21U
-#define M3_SAMPLE_SS_E24 0xB866CC10U, 0x3BA39421U
-#define M3_SAMPLE_SS_E28 0xB866CC10U, 0x3C231421U
-#define M3_SAMPLE_SS_E32 0xB866CC10U, 0x3C241421U
-
-static const uint32_t termcode_by_sample[20][3] = {
- { M3_SAMPLE_TT_A84, 0x000158D5U },
- { M3_SAMPLE_TT_A85, 0x00015955U },
- { M3_SAMPLE_TT_A86, 0x00015955U },
- { M3_SAMPLE_FF_B45, 0x00015690U },
- { M3_SAMPLE_FF_B49, 0x00015753U },
- { M3_SAMPLE_FF_B56, 0x00015793U },
- { M3_SAMPLE_SS_E24, 0x00015996U },
- { M3_SAMPLE_SS_E28, 0x000159D7U },
- { M3_SAMPLE_SS_E32, 0x00015997U },
- { 0xFFFFFFFFU, 0xFFFFFFFFU, 0x0001554FU}
-};
-
-#ifdef BOARD_JUDGE_AUTO
-/* Board detect function */
-#define GPIO_INDT5 0xE605500CU
-#define LPDDR4_2RANK (0x01U << 25U)
-
-static uint32_t _board_judge(uint32_t prr_product)
-{
- uint32_t boardInfo;
- uint32_t boardid = 1U;
-
- if (prr_product == PRR_PRODUCT_M3) {
- if ((mmio_read_32(PRR) & PRR_CUT_MASK) != RCAR_M3_CUT_VER11) {
- boardInfo = mmio_read_32(GPIO_INDT5);
- if ((boardInfo & LPDDR4_2RANK) == 0U) {
- boardid = 0U;
- }
- }
- }
-
- return boardid;
-}
-#endif /* BOARD_JUDGE_AUTO */
diff --git a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_regdef.h b/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_regdef.h
deleted file mode 100644
index 9f1c936..0000000
--- a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_regdef.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef RZG_BOOT_INIT_DRAM_REGDEF_H
-#define RZG_BOOT_INIT_DRAM_REGDEF_H
-
-#define RCAR_DDR_VERSION "rev.0.40"
-#define DRAM_CH_CNT 0x04U
-#define SLICE_CNT 0x04U
-#define CS_CNT 0x02U
-
-/* order : CS0A, CS0B, CS1A, CS1B */
-#define CSAB_CNT (CS_CNT * 2U)
-
-/* order : CH0A, CH0B, CH1A, CH1B, CH2A, CH2B, CH3A, CH3B */
-#define CHAB_CNT (DRAM_CH_CNT * 2)
-
-/* pll setting */
-#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
-#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb)))
-
-/* for ddr density setting */
-#define DBMEMCONF_REG(d3, row, bank, col, dw) \
- (((d3) << 30U) | ((row) << 24U) | ((bank) << 16U) | ((col) << 8U) | (dw))
-
-#define DBMEMCONF_REGD(density) \
- (DBMEMCONF_REG((density) % 2U, ((density) + 1U) / \
- 2U + (29U - 3U - 10U - 2U), 3U, 10U, 2U))
-
-#define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs)))
-
-/* refresh mode */
-#define DBSC_REFINTS (0x0U)
-
-/* system registers */
-#define CPG_FRQCRB (CPG_BASE + 0x0004U)
-
-#define CPG_PLLECR (CPG_BASE + 0x00D0U)
-#define CPG_MSTPSR5 (CPG_BASE + 0x003CU)
-#define CPG_SRCR4 (CPG_BASE + 0x00BCU)
-#define CPG_PLL3CR (CPG_BASE + 0x00DCU)
-#define CPG_ZB3CKCR (CPG_BASE + 0x0380U)
-#define CPG_FRQCRD (CPG_BASE + 0x00E4U)
-#define CPG_SMSTPCR5 (CPG_BASE + 0x0144U)
-#define CPG_CPGWPR (CPG_BASE + 0x0900U)
-#define CPG_SRSTCLR4 (CPG_BASE + 0x0950U)
-
-#define CPG_FRQCRB_KICK_BIT BIT(31)
-#define CPG_PLLECR_PLL3E_BIT BIT(3)
-#define CPG_PLLECR_PLL3ST_BIT BIT(11)
-#define CPG_ZB3CKCR_ZB3ST_BIT BIT(11)
-
-#define RST_BASE (0xE6160000U)
-#define RST_MODEMR (RST_BASE + 0x0060U)
-
-#define LIFEC_CHIPID(x) (0xE6110040U + 0x04U * (x))
-
-/* DBSC registers */
-#include "ddr_regs.h"
-
-#define DBSC_DBMONCONF4 0xE6793010U
-
-#define DBSC_PLL_LOCK(ch) (0xE6794054U + 0x100U * (ch))
-#define DBSC_PLL_LOCK_0 0xE6794054U
-#define DBSC_PLL_LOCK_1 0xE6794154U
-#define DBSC_PLL_LOCK_2 0xE6794254U
-#define DBSC_PLL_LOCK_3 0xE6794354U
-
-/* STAT registers */
-#define MSTAT_SL_INIT 0xE67E8000U
-#define MSTAT_REF_ARS 0xE67E8004U
-#define MSTATQ_STATQC 0xE67E8008U
-#define MSTATQ_WTENABLE 0xE67E8030U
-#define MSTATQ_WTREFRESH 0xE67E8034U
-#define MSTATQ_WTSETTING0 0xE67E8038U
-#define MSTATQ_WTSETTING1 0xE67E803CU
-
-#define QOS_BASE1 (0xE67F0000U)
-#define QOSCTRL_RAS (QOS_BASE1 + 0x0000U)
-#define QOSCTRL_FIXTH (QOS_BASE1 + 0x0004U)
-#define QOSCTRL_RAEN (QOS_BASE1 + 0x0018U)
-#define QOSCTRL_REGGD (QOS_BASE1 + 0x0020U)
-#define QOSCTRL_DANN (QOS_BASE1 + 0x0030U)
-#define QOSCTRL_DANT (QOS_BASE1 + 0x0038U)
-#define QOSCTRL_EC (QOS_BASE1 + 0x003CU)
-#define QOSCTRL_EMS (QOS_BASE1 + 0x0040U)
-#define QOSCTRL_INSFC (QOS_BASE1 + 0x0050U)
-#define QOSCTRL_BERR (QOS_BASE1 + 0x0054U)
-#define QOSCTRL_RACNT0 (QOS_BASE1 + 0x0080U)
-#define QOSCTRL_STATGEN0 (QOS_BASE1 + 0x0088U)
-
-/* other module */
-#define THS1_THCTR 0xE6198020U
-#define THS1_TEMP 0xE6198028U
-
-#endif /* RZG_BOOT_INIT_DRAM_REGDEF_H */
diff --git a/drivers/renesas/rzg/ddr/ddr_b/ddr_b.mk b/drivers/renesas/rzg/ddr/ddr_b/ddr_b.mk
deleted file mode 100644
index c137f26..0000000
--- a/drivers/renesas/rzg/ddr/ddr_b/ddr_b.mk
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-BL2_SOURCES += drivers/renesas/rzg/ddr/ddr_b/boot_init_dram.c
diff --git a/drivers/renesas/rzg/ddr/ddr_b/ddr_regdef.h b/drivers/renesas/rzg/ddr/ddr_b/ddr_regdef.h
deleted file mode 100644
index 1da455f..0000000
--- a/drivers/renesas/rzg/ddr/ddr_b/ddr_regdef.h
+++ /dev/null
@@ -1,5891 +0,0 @@
-/*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef RZG_DDR_REGDEF_H
-#define RZG_DDR_REGDEF_H
-
-#define _reg_PHY_DQ_DM_SWIZZLE0 0x00000000U
-#define _reg_PHY_DQ_DM_SWIZZLE1 0x00000001U
-#define _reg_PHY_CLK_WR_BYPASS_SLAVE_DELAY 0x00000002U
-#define _reg_PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY 0x00000003U
-#define _reg_PHY_BYPASS_TWO_CYC_PREAMBLE 0x00000004U
-#define _reg_PHY_CLK_BYPASS_OVERRIDE 0x00000005U
-#define _reg_PHY_SW_WRDQ0_SHIFT 0x00000006U
-#define _reg_PHY_SW_WRDQ1_SHIFT 0x00000007U
-#define _reg_PHY_SW_WRDQ2_SHIFT 0x00000008U
-#define _reg_PHY_SW_WRDQ3_SHIFT 0x00000009U
-#define _reg_PHY_SW_WRDQ4_SHIFT 0x0000000aU
-#define _reg_PHY_SW_WRDQ5_SHIFT 0x0000000bU
-#define _reg_PHY_SW_WRDQ6_SHIFT 0x0000000cU
-#define _reg_PHY_SW_WRDQ7_SHIFT 0x0000000dU
-#define _reg_PHY_SW_WRDM_SHIFT 0x0000000eU
-#define _reg_PHY_SW_WRDQS_SHIFT 0x0000000fU
-#define _reg_PHY_DQ_TSEL_ENABLE 0x00000010U
-#define _reg_PHY_DQ_TSEL_SELECT 0x00000011U
-#define _reg_PHY_DQS_TSEL_ENABLE 0x00000012U
-#define _reg_PHY_DQS_TSEL_SELECT 0x00000013U
-#define _reg_PHY_TWO_CYC_PREAMBLE 0x00000014U
-#define _reg_PHY_DBI_MODE 0x00000015U
-#define _reg_PHY_PER_RANK_CS_MAP 0x00000016U
-#define _reg_PHY_PER_CS_TRAINING_MULTICAST_EN 0x00000017U
-#define _reg_PHY_PER_CS_TRAINING_INDEX 0x00000018U
-#define _reg_PHY_LP4_BOOT_RDDATA_EN_IE_DLY 0x00000019U
-#define _reg_PHY_LP4_BOOT_RDDATA_EN_DLY 0x0000001aU
-#define _reg_PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY 0x0000001bU
-#define _reg_PHY_LP4_BOOT_RPTR_UPDATE 0x0000001cU
-#define _reg_PHY_LP4_BOOT_RDDQS_GATE_SLAVE_DELAY 0x0000001dU
-#define _reg_PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST 0x0000001eU
-#define _reg_PHY_LP4_BOOT_WRPATH_GATE_DISABLE 0x0000001fU
-#define _reg_PHY_LP4_BOOT_RDDATA_EN_OE_DLY 0x00000020U
-#define _reg_PHY_LPBK_CONTROL 0x00000021U
-#define _reg_PHY_LPBK_DFX_TIMEOUT_EN 0x00000022U
-#define _reg_PHY_AUTO_TIMING_MARGIN_CONTROL 0x00000023U
-#define _reg_PHY_AUTO_TIMING_MARGIN_OBS 0x00000024U
-#define _reg_PHY_SLICE_PWR_RDC_DISABLE 0x00000025U
-#define _reg_PHY_PRBS_PATTERN_START 0x00000026U
-#define _reg_PHY_PRBS_PATTERN_MASK 0x00000027U
-#define _reg_PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY 0x00000028U
-#define _reg_PHY_GATE_ERROR_DELAY_SELECT 0x00000029U
-#define _reg_SC_PHY_SNAP_OBS_REGS 0x0000002aU
-#define _reg_PHY_LPDDR 0x0000002bU
-#define _reg_PHY_LPDDR_TYPE 0x0000002cU
-#define _reg_PHY_GATE_SMPL1_SLAVE_DELAY 0x0000002dU
-#define _reg_PHY_GATE_SMPL2_SLAVE_DELAY 0x0000002eU
-#define _reg_ON_FLY_GATE_ADJUST_EN 0x0000002fU
-#define _reg_PHY_GATE_TRACKING_OBS 0x00000030U
-#define _reg_PHY_DFI40_POLARITY 0x00000031U
-#define _reg_PHY_LP4_PST_AMBLE 0x00000032U
-#define _reg_PHY_RDLVL_PATT8 0x00000033U
-#define _reg_PHY_RDLVL_PATT9 0x00000034U
-#define _reg_PHY_RDLVL_PATT10 0x00000035U
-#define _reg_PHY_RDLVL_PATT11 0x00000036U
-#define _reg_PHY_LP4_RDLVL_PATT8 0x00000037U
-#define _reg_PHY_LP4_RDLVL_PATT9 0x00000038U
-#define _reg_PHY_LP4_RDLVL_PATT10 0x00000039U
-#define _reg_PHY_LP4_RDLVL_PATT11 0x0000003aU
-#define _reg_PHY_SLAVE_LOOP_CNT_UPDATE 0x0000003bU
-#define _reg_PHY_SW_FIFO_PTR_RST_DISABLE 0x0000003cU
-#define _reg_PHY_MASTER_DLY_LOCK_OBS_SELECT 0x0000003dU
-#define _reg_PHY_RDDQ_ENC_OBS_SELECT 0x0000003eU
-#define _reg_PHY_RDDQS_DQ_ENC_OBS_SELECT 0x0000003fU
-#define _reg_PHY_WR_ENC_OBS_SELECT 0x00000040U
-#define _reg_PHY_WR_SHIFT_OBS_SELECT 0x00000041U
-#define _reg_PHY_FIFO_PTR_OBS_SELECT 0x00000042U
-#define _reg_PHY_LVL_DEBUG_MODE 0x00000043U
-#define _reg_SC_PHY_LVL_DEBUG_CONT 0x00000044U
-#define _reg_PHY_WRLVL_CAPTURE_CNT 0x00000045U
-#define _reg_PHY_WRLVL_UPDT_WAIT_CNT 0x00000046U
-#define _reg_PHY_WRLVL_DQ_MASK 0x00000047U
-#define _reg_PHY_GTLVL_CAPTURE_CNT 0x00000048U
-#define _reg_PHY_GTLVL_UPDT_WAIT_CNT 0x00000049U
-#define _reg_PHY_RDLVL_CAPTURE_CNT 0x0000004aU
-#define _reg_PHY_RDLVL_UPDT_WAIT_CNT 0x0000004bU
-#define _reg_PHY_RDLVL_OP_MODE 0x0000004cU
-#define _reg_PHY_RDLVL_RDDQS_DQ_OBS_SELECT 0x0000004dU
-#define _reg_PHY_RDLVL_DATA_MASK 0x0000004eU
-#define _reg_PHY_RDLVL_DATA_SWIZZLE 0x0000004fU
-#define _reg_PHY_WDQLVL_BURST_CNT 0x00000050U
-#define _reg_PHY_WDQLVL_PATT 0x00000051U
-#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET 0x00000052U
-#define _reg_PHY_WDQLVL_UPDT_WAIT_CNT 0x00000053U
-#define _reg_PHY_WDQLVL_DQDM_OBS_SELECT 0x00000054U
-#define _reg_PHY_WDQLVL_QTR_DLY_STEP 0x00000055U
-#define _reg_SC_PHY_WDQLVL_CLR_PREV_RESULTS 0x00000056U
-#define _reg_PHY_WDQLVL_CLR_PREV_RESULTS 0x00000057U
-#define _reg_PHY_WDQLVL_DATADM_MASK 0x00000058U
-#define _reg_PHY_USER_PATT0 0x00000059U
-#define _reg_PHY_USER_PATT1 0x0000005aU
-#define _reg_PHY_USER_PATT2 0x0000005bU
-#define _reg_PHY_USER_PATT3 0x0000005cU
-#define _reg_PHY_USER_PATT4 0x0000005dU
-#define _reg_PHY_DQ_SWIZZLING 0x0000005eU
-#define _reg_PHY_CALVL_VREF_DRIVING_SLICE 0x0000005fU
-#define _reg_SC_PHY_MANUAL_CLEAR 0x00000060U
-#define _reg_PHY_FIFO_PTR_OBS 0x00000061U
-#define _reg_PHY_LPBK_RESULT_OBS 0x00000062U
-#define _reg_PHY_LPBK_ERROR_COUNT_OBS 0x00000063U
-#define _reg_PHY_MASTER_DLY_LOCK_OBS 0x00000064U
-#define _reg_PHY_RDDQ_SLV_DLY_ENC_OBS 0x00000065U
-#define _reg_PHY_RDDQS_BASE_SLV_DLY_ENC_OBS 0x00000066U
-#define _reg_PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS 0x00000067U
-#define _reg_PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS 0x00000068U
-#define _reg_PHY_RDDQS_GATE_SLV_DLY_ENC_OBS 0x00000069U
-#define _reg_PHY_WRDQS_BASE_SLV_DLY_ENC_OBS 0x0000006aU
-#define _reg_PHY_WRDQ_BASE_SLV_DLY_ENC_OBS 0x0000006bU
-#define _reg_PHY_WR_ADDER_SLV_DLY_ENC_OBS 0x0000006cU
-#define _reg_PHY_WR_SHIFT_OBS 0x0000006dU
-#define _reg_PHY_WRLVL_HARD0_DELAY_OBS 0x0000006eU
-#define _reg_PHY_WRLVL_HARD1_DELAY_OBS 0x0000006fU
-#define _reg_PHY_WRLVL_STATUS_OBS 0x00000070U
-#define _reg_PHY_GATE_SMPL1_SLV_DLY_ENC_OBS 0x00000071U
-#define _reg_PHY_GATE_SMPL2_SLV_DLY_ENC_OBS 0x00000072U
-#define _reg_PHY_WRLVL_ERROR_OBS 0x00000073U
-#define _reg_PHY_GTLVL_HARD0_DELAY_OBS 0x00000074U
-#define _reg_PHY_GTLVL_HARD1_DELAY_OBS 0x00000075U
-#define _reg_PHY_GTLVL_STATUS_OBS 0x00000076U
-#define _reg_PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS 0x00000077U
-#define _reg_PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS 0x00000078U
-#define _reg_PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS 0x00000079U
-#define _reg_PHY_RDLVL_STATUS_OBS 0x0000007aU
-#define _reg_PHY_WDQLVL_DQDM_LE_DLY_OBS 0x0000007bU
-#define _reg_PHY_WDQLVL_DQDM_TE_DLY_OBS 0x0000007cU
-#define _reg_PHY_WDQLVL_STATUS_OBS 0x0000007dU
-#define _reg_PHY_DDL_MODE 0x0000007eU
-#define _reg_PHY_DDL_TEST_OBS 0x0000007fU
-#define _reg_PHY_DDL_TEST_MSTR_DLY_OBS 0x00000080U
-#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD 0x00000081U
-#define _reg_PHY_LP4_WDQS_OE_EXTEND 0x00000082U
-#define _reg_SC_PHY_RX_CAL_START 0x00000083U
-#define _reg_PHY_RX_CAL_OVERRIDE 0x00000084U
-#define _reg_PHY_RX_CAL_SAMPLE_WAIT 0x00000085U
-#define _reg_PHY_RX_CAL_DQ0 0x00000086U
-#define _reg_PHY_RX_CAL_DQ1 0x00000087U
-#define _reg_PHY_RX_CAL_DQ2 0x00000088U
-#define _reg_PHY_RX_CAL_DQ3 0x00000089U
-#define _reg_PHY_RX_CAL_DQ4 0x0000008aU
-#define _reg_PHY_RX_CAL_DQ5 0x0000008bU
-#define _reg_PHY_RX_CAL_DQ6 0x0000008cU
-#define _reg_PHY_RX_CAL_DQ7 0x0000008dU
-#define _reg_PHY_RX_CAL_DM 0x0000008eU
-#define _reg_PHY_RX_CAL_DQS 0x0000008fU
-#define _reg_PHY_RX_CAL_FDBK 0x00000090U
-#define _reg_PHY_RX_CAL_OBS 0x00000091U
-#define _reg_PHY_RX_CAL_LOCK_OBS 0x00000092U
-#define _reg_PHY_RX_CAL_DISABLE 0x00000093U
-#define _reg_PHY_CLK_WRDQ0_SLAVE_DELAY 0x00000094U
-#define _reg_PHY_CLK_WRDQ1_SLAVE_DELAY 0x00000095U
-#define _reg_PHY_CLK_WRDQ2_SLAVE_DELAY 0x00000096U
-#define _reg_PHY_CLK_WRDQ3_SLAVE_DELAY 0x00000097U
-#define _reg_PHY_CLK_WRDQ4_SLAVE_DELAY 0x00000098U
-#define _reg_PHY_CLK_WRDQ5_SLAVE_DELAY 0x00000099U
-#define _reg_PHY_CLK_WRDQ6_SLAVE_DELAY 0x0000009aU
-#define _reg_PHY_CLK_WRDQ7_SLAVE_DELAY 0x0000009bU
-#define _reg_PHY_CLK_WRDM_SLAVE_DELAY 0x0000009cU
-#define _reg_PHY_CLK_WRDQS_SLAVE_DELAY 0x0000009dU
-#define _reg_PHY_WRLVL_THRESHOLD_ADJUST 0x0000009eU
-#define _reg_PHY_RDDQ0_SLAVE_DELAY 0x0000009fU
-#define _reg_PHY_RDDQ1_SLAVE_DELAY 0x000000a0U
-#define _reg_PHY_RDDQ2_SLAVE_DELAY 0x000000a1U
-#define _reg_PHY_RDDQ3_SLAVE_DELAY 0x000000a2U
-#define _reg_PHY_RDDQ4_SLAVE_DELAY 0x000000a3U
-#define _reg_PHY_RDDQ5_SLAVE_DELAY 0x000000a4U
-#define _reg_PHY_RDDQ6_SLAVE_DELAY 0x000000a5U
-#define _reg_PHY_RDDQ7_SLAVE_DELAY 0x000000a6U
-#define _reg_PHY_RDDM_SLAVE_DELAY 0x000000a7U
-#define _reg_PHY_RDDQS_DQ0_RISE_SLAVE_DELAY 0x000000a8U
-#define _reg_PHY_RDDQS_DQ0_FALL_SLAVE_DELAY 0x000000a9U
-#define _reg_PHY_RDDQS_DQ1_RISE_SLAVE_DELAY 0x000000aaU
-#define _reg_PHY_RDDQS_DQ1_FALL_SLAVE_DELAY 0x000000abU
-#define _reg_PHY_RDDQS_DQ2_RISE_SLAVE_DELAY 0x000000acU
-#define _reg_PHY_RDDQS_DQ2_FALL_SLAVE_DELAY 0x000000adU
-#define _reg_PHY_RDDQS_DQ3_RISE_SLAVE_DELAY 0x000000aeU
-#define _reg_PHY_RDDQS_DQ3_FALL_SLAVE_DELAY 0x000000afU
-#define _reg_PHY_RDDQS_DQ4_RISE_SLAVE_DELAY 0x000000b0U
-#define _reg_PHY_RDDQS_DQ4_FALL_SLAVE_DELAY 0x000000b1U
-#define _reg_PHY_RDDQS_DQ5_RISE_SLAVE_DELAY 0x000000b2U
-#define _reg_PHY_RDDQS_DQ5_FALL_SLAVE_DELAY 0x000000b3U
-#define _reg_PHY_RDDQS_DQ6_RISE_SLAVE_DELAY 0x000000b4U
-#define _reg_PHY_RDDQS_DQ6_FALL_SLAVE_DELAY 0x000000b5U
-#define _reg_PHY_RDDQS_DQ7_RISE_SLAVE_DELAY 0x000000b6U
-#define _reg_PHY_RDDQS_DQ7_FALL_SLAVE_DELAY 0x000000b7U
-#define _reg_PHY_RDDQS_DM_RISE_SLAVE_DELAY 0x000000b8U
-#define _reg_PHY_RDDQS_DM_FALL_SLAVE_DELAY 0x000000b9U
-#define _reg_PHY_RDDQS_GATE_SLAVE_DELAY 0x000000baU
-#define _reg_PHY_RDDQS_LATENCY_ADJUST 0x000000bbU
-#define _reg_PHY_WRITE_PATH_LAT_ADD 0x000000bcU
-#define _reg_PHY_WRLVL_DELAY_EARLY_THRESHOLD 0x000000bdU
-#define _reg_PHY_WRLVL_DELAY_PERIOD_THRESHOLD 0x000000beU
-#define _reg_PHY_WRLVL_EARLY_FORCE_ZERO 0x000000bfU
-#define _reg_PHY_GTLVL_RDDQS_SLV_DLY_START 0x000000c0U
-#define _reg_PHY_GTLVL_LAT_ADJ_START 0x000000c1U
-#define _reg_PHY_WDQLVL_DQDM_SLV_DLY_START 0x000000c2U
-#define _reg_PHY_RDLVL_RDDQS_DQ_SLV_DLY_START 0x000000c3U
-#define _reg_PHY_FDBK_PWR_CTRL 0x000000c4U
-#define _reg_PHY_DQ_OE_TIMING 0x000000c5U
-#define _reg_PHY_DQ_TSEL_RD_TIMING 0x000000c6U
-#define _reg_PHY_DQ_TSEL_WR_TIMING 0x000000c7U
-#define _reg_PHY_DQS_OE_TIMING 0x000000c8U
-#define _reg_PHY_DQS_TSEL_RD_TIMING 0x000000c9U
-#define _reg_PHY_DQS_OE_RD_TIMING 0x000000caU
-#define _reg_PHY_DQS_TSEL_WR_TIMING 0x000000cbU
-#define _reg_PHY_PER_CS_TRAINING_EN 0x000000ccU
-#define _reg_PHY_DQ_IE_TIMING 0x000000cdU
-#define _reg_PHY_DQS_IE_TIMING 0x000000ceU
-#define _reg_PHY_RDDATA_EN_IE_DLY 0x000000cfU
-#define _reg_PHY_IE_MODE 0x000000d0U
-#define _reg_PHY_RDDATA_EN_DLY 0x000000d1U
-#define _reg_PHY_RDDATA_EN_TSEL_DLY 0x000000d2U
-#define _reg_PHY_RDDATA_EN_OE_DLY 0x000000d3U
-#define _reg_PHY_SW_MASTER_MODE 0x000000d4U
-#define _reg_PHY_MASTER_DELAY_START 0x000000d5U
-#define _reg_PHY_MASTER_DELAY_STEP 0x000000d6U
-#define _reg_PHY_MASTER_DELAY_WAIT 0x000000d7U
-#define _reg_PHY_MASTER_DELAY_HALF_MEASURE 0x000000d8U
-#define _reg_PHY_RPTR_UPDATE 0x000000d9U
-#define _reg_PHY_WRLVL_DLY_STEP 0x000000daU
-#define _reg_PHY_WRLVL_RESP_WAIT_CNT 0x000000dbU
-#define _reg_PHY_GTLVL_DLY_STEP 0x000000dcU
-#define _reg_PHY_GTLVL_RESP_WAIT_CNT 0x000000ddU
-#define _reg_PHY_GTLVL_BACK_STEP 0x000000deU
-#define _reg_PHY_GTLVL_FINAL_STEP 0x000000dfU
-#define _reg_PHY_WDQLVL_DLY_STEP 0x000000e0U
-#define _reg_PHY_TOGGLE_PRE_SUPPORT 0x000000e1U
-#define _reg_PHY_RDLVL_DLY_STEP 0x000000e2U
-#define _reg_PHY_WRPATH_GATE_DISABLE 0x000000e3U
-#define _reg_PHY_WRPATH_GATE_TIMING 0x000000e4U
-#define _reg_PHY_ADR0_SW_WRADDR_SHIFT 0x000000e5U
-#define _reg_PHY_ADR1_SW_WRADDR_SHIFT 0x000000e6U
-#define _reg_PHY_ADR2_SW_WRADDR_SHIFT 0x000000e7U
-#define _reg_PHY_ADR3_SW_WRADDR_SHIFT 0x000000e8U
-#define _reg_PHY_ADR4_SW_WRADDR_SHIFT 0x000000e9U
-#define _reg_PHY_ADR5_SW_WRADDR_SHIFT 0x000000eaU
-#define _reg_PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY 0x000000ebU
-#define _reg_PHY_ADR_CLK_BYPASS_OVERRIDE 0x000000ecU
-#define _reg_SC_PHY_ADR_MANUAL_CLEAR 0x000000edU
-#define _reg_PHY_ADR_LPBK_RESULT_OBS 0x000000eeU
-#define _reg_PHY_ADR_LPBK_ERROR_COUNT_OBS 0x000000efU
-#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT 0x000000f0U
-#define _reg_PHY_ADR_MASTER_DLY_LOCK_OBS 0x000000f1U
-#define _reg_PHY_ADR_BASE_SLV_DLY_ENC_OBS 0x000000f2U
-#define _reg_PHY_ADR_ADDER_SLV_DLY_ENC_OBS 0x000000f3U
-#define _reg_PHY_ADR_SLAVE_LOOP_CNT_UPDATE 0x000000f4U
-#define _reg_PHY_ADR_SLV_DLY_ENC_OBS_SELECT 0x000000f5U
-#define _reg_SC_PHY_ADR_SNAP_OBS_REGS 0x000000f6U
-#define _reg_PHY_ADR_TSEL_ENABLE 0x000000f7U
-#define _reg_PHY_ADR_LPBK_CONTROL 0x000000f8U
-#define _reg_PHY_ADR_PRBS_PATTERN_START 0x000000f9U
-#define _reg_PHY_ADR_PRBS_PATTERN_MASK 0x000000faU
-#define _reg_PHY_ADR_PWR_RDC_DISABLE 0x000000fbU
-#define _reg_PHY_ADR_TYPE 0x000000fcU
-#define _reg_PHY_ADR_WRADDR_SHIFT_OBS 0x000000fdU
-#define _reg_PHY_ADR_IE_MODE 0x000000feU
-#define _reg_PHY_ADR_DDL_MODE 0x000000ffU
-#define _reg_PHY_ADR_DDL_TEST_OBS 0x00000100U
-#define _reg_PHY_ADR_DDL_TEST_MSTR_DLY_OBS 0x00000101U
-#define _reg_PHY_ADR_CALVL_START 0x00000102U
-#define _reg_PHY_ADR_CALVL_COARSE_DLY 0x00000103U
-#define _reg_PHY_ADR_CALVL_QTR 0x00000104U
-#define _reg_PHY_ADR_CALVL_SWIZZLE0 0x00000105U
-#define _reg_PHY_ADR_CALVL_SWIZZLE1 0x00000106U
-#define _reg_PHY_ADR_CALVL_SWIZZLE0_0 0x00000107U
-#define _reg_PHY_ADR_CALVL_SWIZZLE1_0 0x00000108U
-#define _reg_PHY_ADR_CALVL_SWIZZLE0_1 0x00000109U
-#define _reg_PHY_ADR_CALVL_SWIZZLE1_1 0x0000010aU
-#define _reg_PHY_ADR_CALVL_DEVICE_MAP 0x0000010bU
-#define _reg_PHY_ADR_CALVL_RANK_CTRL 0x0000010cU
-#define _reg_PHY_ADR_CALVL_NUM_PATTERNS 0x0000010dU
-#define _reg_PHY_ADR_CALVL_CAPTURE_CNT 0x0000010eU
-#define _reg_PHY_ADR_CALVL_RESP_WAIT_CNT 0x0000010fU
-#define _reg_PHY_ADR_CALVL_DEBUG_MODE 0x00000110U
-#define _reg_SC_PHY_ADR_CALVL_DEBUG_CONT 0x00000111U
-#define _reg_SC_PHY_ADR_CALVL_ERROR_CLR 0x00000112U
-#define _reg_PHY_ADR_CALVL_OBS_SELECT 0x00000113U
-#define _reg_PHY_ADR_CALVL_OBS0 0x00000114U
-#define _reg_PHY_ADR_CALVL_OBS1 0x00000115U
-#define _reg_PHY_ADR_CALVL_RESULT 0x00000116U
-#define _reg_PHY_ADR_CALVL_FG_0 0x00000117U
-#define _reg_PHY_ADR_CALVL_BG_0 0x00000118U
-#define _reg_PHY_ADR_CALVL_FG_1 0x00000119U
-#define _reg_PHY_ADR_CALVL_BG_1 0x0000011aU
-#define _reg_PHY_ADR_CALVL_FG_2 0x0000011bU
-#define _reg_PHY_ADR_CALVL_BG_2 0x0000011cU
-#define _reg_PHY_ADR_CALVL_FG_3 0x0000011dU
-#define _reg_PHY_ADR_CALVL_BG_3 0x0000011eU
-#define _reg_PHY_ADR_ADDR_SEL 0x0000011fU
-#define _reg_PHY_ADR_LP4_BOOT_SLV_DELAY 0x00000120U
-#define _reg_PHY_ADR_BIT_MASK 0x00000121U
-#define _reg_PHY_ADR_SEG_MASK 0x00000122U
-#define _reg_PHY_ADR_CALVL_TRAIN_MASK 0x00000123U
-#define _reg_PHY_ADR_CSLVL_TRAIN_MASK 0x00000124U
-#define _reg_PHY_ADR_SW_TXIO_CTRL 0x00000125U
-#define _reg_PHY_ADR_TSEL_SELECT 0x00000126U
-#define _reg_PHY_ADR0_CLK_WR_SLAVE_DELAY 0x00000127U
-#define _reg_PHY_ADR1_CLK_WR_SLAVE_DELAY 0x00000128U
-#define _reg_PHY_ADR2_CLK_WR_SLAVE_DELAY 0x00000129U
-#define _reg_PHY_ADR3_CLK_WR_SLAVE_DELAY 0x0000012aU
-#define _reg_PHY_ADR4_CLK_WR_SLAVE_DELAY 0x0000012bU
-#define _reg_PHY_ADR5_CLK_WR_SLAVE_DELAY 0x0000012cU
-#define _reg_PHY_ADR_SW_MASTER_MODE 0x0000012dU
-#define _reg_PHY_ADR_MASTER_DELAY_START 0x0000012eU
-#define _reg_PHY_ADR_MASTER_DELAY_STEP 0x0000012fU
-#define _reg_PHY_ADR_MASTER_DELAY_WAIT 0x00000130U
-#define _reg_PHY_ADR_MASTER_DELAY_HALF_MEASURE 0x00000131U
-#define _reg_PHY_ADR_CALVL_DLY_STEP 0x00000132U
-#define _reg_PHY_FREQ_SEL 0x00000133U
-#define _reg_PHY_FREQ_SEL_FROM_REGIF 0x00000134U
-#define _reg_PHY_FREQ_SEL_MULTICAST_EN 0x00000135U
-#define _reg_PHY_FREQ_SEL_INDEX 0x00000136U
-#define _reg_PHY_SW_GRP_SHIFT_0 0x00000137U
-#define _reg_PHY_SW_GRP_SHIFT_1 0x00000138U
-#define _reg_PHY_SW_GRP_SHIFT_2 0x00000139U
-#define _reg_PHY_SW_GRP_SHIFT_3 0x0000013aU
-#define _reg_PHY_GRP_BYPASS_SLAVE_DELAY 0x0000013bU
-#define _reg_PHY_SW_GRP_BYPASS_SHIFT 0x0000013cU
-#define _reg_PHY_GRP_BYPASS_OVERRIDE 0x0000013dU
-#define _reg_SC_PHY_MANUAL_UPDATE 0x0000013eU
-#define _reg_SC_PHY_MANUAL_UPDATE_PHYUPD_ENABLE 0x0000013fU
-#define _reg_PHY_LP4_BOOT_DISABLE 0x00000140U
-#define _reg_PHY_CSLVL_ENABLE 0x00000141U
-#define _reg_PHY_CSLVL_CS_MAP 0x00000142U
-#define _reg_PHY_CSLVL_START 0x00000143U
-#define _reg_PHY_CSLVL_QTR 0x00000144U
-#define _reg_PHY_CSLVL_COARSE_CHK 0x00000145U
-#define _reg_PHY_CSLVL_CAPTURE_CNT 0x00000146U
-#define _reg_PHY_CSLVL_COARSE_DLY 0x00000147U
-#define _reg_PHY_CSLVL_COARSE_CAPTURE_CNT 0x00000148U
-#define _reg_PHY_CSLVL_DEBUG_MODE 0x00000149U
-#define _reg_SC_PHY_CSLVL_DEBUG_CONT 0x0000014aU
-#define _reg_SC_PHY_CSLVL_ERROR_CLR 0x0000014bU
-#define _reg_PHY_CSLVL_OBS0 0x0000014cU
-#define _reg_PHY_CSLVL_OBS1 0x0000014dU
-#define _reg_PHY_CALVL_CS_MAP 0x0000014eU
-#define _reg_PHY_GRP_SLV_DLY_ENC_OBS_SELECT 0x0000014fU
-#define _reg_PHY_GRP_SHIFT_OBS_SELECT 0x00000150U
-#define _reg_PHY_GRP_SLV_DLY_ENC_OBS 0x00000151U
-#define _reg_PHY_GRP_SHIFT_OBS 0x00000152U
-#define _reg_PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE 0x00000153U
-#define _reg_PHY_ADRCTL_SNAP_OBS_REGS 0x00000154U
-#define _reg_PHY_DFI_PHYUPD_TYPE 0x00000155U
-#define _reg_PHY_ADRCTL_LPDDR 0x00000156U
-#define _reg_PHY_LP4_ACTIVE 0x00000157U
-#define _reg_PHY_LPDDR3_CS 0x00000158U
-#define _reg_PHY_CALVL_RESULT_MASK 0x00000159U
-#define _reg_SC_PHY_UPDATE_CLK_CAL_VALUES 0x0000015aU
-#define _reg_PHY_SW_TXIO_CTRL_0 0x0000015bU
-#define _reg_PHY_SW_TXIO_CTRL_1 0x0000015cU
-#define _reg_PHY_SW_TXIO_CTRL_2 0x0000015dU
-#define _reg_PHY_SW_TXIO_CTRL_3 0x0000015eU
-#define _reg_PHY_MEMCLK_SW_TXIO_CTRL 0x0000015fU
-#define _reg_PHY_CA_SW_TXPWR_CTRL 0x00000160U
-#define _reg_PHY_MEMCLK_SW_TXPWR_CTRL 0x00000161U
-#define _reg_PHY_USER_DEF_REG_AC_0 0x00000162U
-#define _reg_PHY_USER_DEF_REG_AC_1 0x00000163U
-#define _reg_PHY_USER_DEF_REG_AC_2 0x00000164U
-#define _reg_PHY_USER_DEF_REG_AC_3 0x00000165U
-#define _reg_PHY_UPDATE_CLK_CAL_VALUES 0x00000166U
-#define _reg_PHY_CONTINUOUS_CLK_CAL_UPDATE 0x00000167U
-#define _reg_PHY_PLL_CTRL 0x00000168U
-#define _reg_PHY_PLL_CTRL_TOP 0x00000169U
-#define _reg_PHY_PLL_CTRL_CA 0x0000016aU
-#define _reg_PHY_PLL_BYPASS 0x0000016bU
-#define _reg_PHY_LOW_FREQ_SEL 0x0000016cU
-#define _reg_PHY_PAD_VREF_CTRL_DQ_0 0x0000016dU
-#define _reg_PHY_PAD_VREF_CTRL_DQ_1 0x0000016eU
-#define _reg_PHY_PAD_VREF_CTRL_DQ_2 0x0000016fU
-#define _reg_PHY_PAD_VREF_CTRL_DQ_3 0x00000170U
-#define _reg_PHY_PAD_VREF_CTRL_AC 0x00000171U
-#define _reg_PHY_CSLVL_DLY_STEP 0x00000172U
-#define _reg_PHY_SET_DFI_INPUT_0 0x00000173U
-#define _reg_PHY_SET_DFI_INPUT_1 0x00000174U
-#define _reg_PHY_SET_DFI_INPUT_2 0x00000175U
-#define _reg_PHY_SET_DFI_INPUT_3 0x00000176U
-#define _reg_PHY_GRP_SLAVE_DELAY_0 0x00000177U
-#define _reg_PHY_GRP_SLAVE_DELAY_1 0x00000178U
-#define _reg_PHY_GRP_SLAVE_DELAY_2 0x00000179U
-#define _reg_PHY_GRP_SLAVE_DELAY_3 0x0000017aU
-#define _reg_PHY_CS_ACS_ALLOCATION_0 0x0000017bU
-#define _reg_PHY_CS_ACS_ALLOCATION_1 0x0000017cU
-#define _reg_PHY_CS_ACS_ALLOCATION_2 0x0000017dU
-#define _reg_PHY_CS_ACS_ALLOCATION_3 0x0000017eU
-#define _reg_PHY_LP4_BOOT_PLL_CTRL 0x0000017fU
-#define _reg_PHY_LP4_BOOT_PLL_CTRL_CA 0x00000180U
-#define _reg_PHY_LP4_BOOT_TOP_PLL_CTRL 0x00000181U
-#define _reg_PHY_PLL_CTRL_OVERRIDE 0x00000182U
-#define _reg_PHY_PLL_WAIT 0x00000183U
-#define _reg_PHY_PLL_WAIT_TOP 0x00000184U
-#define _reg_PHY_PLL_OBS_0 0x00000185U
-#define _reg_PHY_PLL_OBS_1 0x00000186U
-#define _reg_PHY_PLL_OBS_2 0x00000187U
-#define _reg_PHY_PLL_OBS_3 0x00000188U
-#define _reg_PHY_PLL_OBS_4 0x00000189U
-#define _reg_PHY_PLL_TESTOUT_SEL 0x0000018aU
-#define _reg_PHY_TCKSRE_WAIT 0x0000018bU
-#define _reg_PHY_LP4_BOOT_LOW_FREQ_SEL 0x0000018cU
-#define _reg_PHY_LP_WAKEUP 0x0000018dU
-#define _reg_PHY_LS_IDLE_EN 0x0000018eU
-#define _reg_PHY_LP_CTRLUPD_CNTR_CFG 0x0000018fU
-#define _reg_PHY_TDFI_PHY_WRDELAY 0x00000190U
-#define _reg_PHY_PAD_FDBK_DRIVE 0x00000191U
-#define _reg_PHY_PAD_DATA_DRIVE 0x00000192U
-#define _reg_PHY_PAD_DQS_DRIVE 0x00000193U
-#define _reg_PHY_PAD_ADDR_DRIVE 0x00000194U
-#define _reg_PHY_PAD_CLK_DRIVE 0x00000195U
-#define _reg_PHY_PAD_FDBK_TERM 0x00000196U
-#define _reg_PHY_PAD_DATA_TERM 0x00000197U
-#define _reg_PHY_PAD_DQS_TERM 0x00000198U
-#define _reg_PHY_PAD_ADDR_TERM 0x00000199U
-#define _reg_PHY_PAD_CLK_TERM 0x0000019aU
-#define _reg_PHY_PAD_CKE_DRIVE 0x0000019bU
-#define _reg_PHY_PAD_CKE_TERM 0x0000019cU
-#define _reg_PHY_PAD_RST_DRIVE 0x0000019dU
-#define _reg_PHY_PAD_RST_TERM 0x0000019eU
-#define _reg_PHY_PAD_CS_DRIVE 0x0000019fU
-#define _reg_PHY_PAD_CS_TERM 0x000001a0U
-#define _reg_PHY_PAD_ODT_DRIVE 0x000001a1U
-#define _reg_PHY_PAD_ODT_TERM 0x000001a2U
-#define _reg_PHY_ADRCTL_RX_CAL 0x000001a3U
-#define _reg_PHY_ADRCTL_LP3_RX_CAL 0x000001a4U
-#define _reg_PHY_TST_CLK_PAD_CTRL 0x000001a5U
-#define _reg_PHY_TST_CLK_PAD_CTRL2 0x000001a6U
-#define _reg_PHY_CAL_MODE_0 0x000001a7U
-#define _reg_PHY_CAL_CLEAR_0 0x000001a8U
-#define _reg_PHY_CAL_START_0 0x000001a9U
-#define _reg_PHY_CAL_INTERVAL_COUNT_0 0x000001aaU
-#define _reg_PHY_CAL_SAMPLE_WAIT_0 0x000001abU
-#define _reg_PHY_LP4_BOOT_CAL_CLK_SELECT_0 0x000001acU
-#define _reg_PHY_CAL_CLK_SELECT_0 0x000001adU
-#define _reg_PHY_CAL_RESULT_OBS_0 0x000001aeU
-#define _reg_PHY_CAL_RESULT2_OBS_0 0x000001afU
-#define _reg_PHY_CAL_CPTR_CNT_0 0x000001b0U
-#define _reg_PHY_CAL_SETTLING_PRD_0 0x000001b1U
-#define _reg_PHY_CAL_PU_FINE_ADJ_0 0x000001b2U
-#define _reg_PHY_CAL_PD_FINE_ADJ_0 0x000001b3U
-#define _reg_PHY_CAL_RCV_FINE_ADJ_0 0x000001b4U
-#define _reg_PHY_CAL_DBG_CFG_0 0x000001b5U
-#define _reg_SC_PHY_PAD_DBG_CONT_0 0x000001b6U
-#define _reg_PHY_CAL_RESULT3_OBS_0 0x000001b7U
-#define _reg_PHY_ADRCTL_PVT_MAP_0 0x000001b8U
-#define _reg_PHY_CAL_SLOPE_ADJ_0 0x000001b9U
-#define _reg_PHY_CAL_SLOPE_ADJ_PASS2_0 0x000001baU
-#define _reg_PHY_CAL_TWO_PASS_CFG_0 0x000001bbU
-#define _reg_PHY_CAL_SW_CAL_CFG_0 0x000001bcU
-#define _reg_PHY_CAL_RANGE_MIN_0 0x000001bdU
-#define _reg_PHY_CAL_RANGE_MAX_0 0x000001beU
-#define _reg_PHY_PAD_ATB_CTRL 0x000001bfU
-#define _reg_PHY_ADRCTL_MANUAL_UPDATE 0x000001c0U
-#define _reg_PHY_AC_LPBK_ERR_CLEAR 0x000001c1U
-#define _reg_PHY_AC_LPBK_OBS_SELECT 0x000001c2U
-#define _reg_PHY_AC_LPBK_ENABLE 0x000001c3U
-#define _reg_PHY_AC_LPBK_CONTROL 0x000001c4U
-#define _reg_PHY_AC_PRBS_PATTERN_START 0x000001c5U
-#define _reg_PHY_AC_PRBS_PATTERN_MASK 0x000001c6U
-#define _reg_PHY_AC_LPBK_RESULT_OBS 0x000001c7U
-#define _reg_PHY_AC_CLK_LPBK_OBS_SELECT 0x000001c8U
-#define _reg_PHY_AC_CLK_LPBK_ENABLE 0x000001c9U
-#define _reg_PHY_AC_CLK_LPBK_CONTROL 0x000001caU
-#define _reg_PHY_AC_CLK_LPBK_RESULT_OBS 0x000001cbU
-#define _reg_PHY_AC_PWR_RDC_DISABLE 0x000001ccU
-#define _reg_PHY_DATA_BYTE_ORDER_SEL 0x000001cdU
-#define _reg_PHY_DATA_BYTE_ORDER_SEL_HIGH 0x000001ceU
-#define _reg_PHY_LPDDR4_CONNECT 0x000001cfU
-#define _reg_PHY_CALVL_DEVICE_MAP 0x000001d0U
-#define _reg_PHY_ADR_DISABLE 0x000001d1U
-#define _reg_PHY_ADRCTL_MSTR_DLY_ENC_SEL 0x000001d2U
-#define _reg_PHY_CS_DLY_UPT_PER_AC_SLICE 0x000001d3U
-#define _reg_PHY_DDL_AC_ENABLE 0x000001d4U
-#define _reg_PHY_DDL_AC_MODE 0x000001d5U
-#define _reg_PHY_PAD_BACKGROUND_CAL 0x000001d6U
-#define _reg_PHY_INIT_UPDATE_CONFIG 0x000001d7U
-#define _reg_PHY_DDL_TRACK_UPD_THRESHOLD_AC 0x000001d8U
-#define _reg_PHY_DLL_RST_EN 0x000001d9U
-#define _reg_PHY_AC_INIT_COMPLETE_OBS 0x000001daU
-#define _reg_PHY_DS_INIT_COMPLETE_OBS 0x000001dbU
-#define _reg_PHY_UPDATE_MASK 0x000001dcU
-#define _reg_PHY_PLL_SWITCH_CNT 0x000001ddU
-#define _reg_PI_START 0x000001deU
-#define _reg_PI_DRAM_CLASS 0x000001dfU
-#define _reg_PI_VERSION 0x000001e0U
-#define _reg_PI_NORMAL_LVL_SEQ 0x000001e1U
-#define _reg_PI_INIT_LVL_EN 0x000001e2U
-#define _reg_PI_NOTCARE_PHYUPD 0x000001e3U
-#define _reg_PI_ONBUS_MBIST 0x000001e4U
-#define _reg_PI_TCMD_GAP 0x000001e5U
-#define _reg_PI_MASTER_ACK_DURATION_MIN 0x000001e6U
-#define _reg_PI_DFI_VERSION 0x000001e7U
-#define _reg_PI_TDFI_PHYMSTR_TYPE0 0x000001e8U
-#define _reg_PI_TDFI_PHYMSTR_TYPE1 0x000001e9U
-#define _reg_PI_TDFI_PHYMSTR_TYPE2 0x000001eaU
-#define _reg_PI_TDFI_PHYMSTR_TYPE3 0x000001ebU
-#define _reg_PI_DFI_PHYMSTR_TYPE 0x000001ecU
-#define _reg_PI_DFI_PHYMSTR_CS_STATE_R 0x000001edU
-#define _reg_PI_DFI_PHYMSTR_STATE_SEL_R 0x000001eeU
-#define _reg_PI_TDFI_PHYMSTR_MAX_F0 0x000001efU
-#define _reg_PI_TDFI_PHYMSTR_RESP_F0 0x000001f0U
-#define _reg_PI_TDFI_PHYMSTR_MAX_F1 0x000001f1U
-#define _reg_PI_TDFI_PHYMSTR_RESP_F1 0x000001f2U
-#define _reg_PI_TDFI_PHYMSTR_MAX_F2 0x000001f3U
-#define _reg_PI_TDFI_PHYMSTR_RESP_F2 0x000001f4U
-#define _reg_PI_TDFI_PHYUPD_RESP_F0 0x000001f5U
-#define _reg_PI_TDFI_PHYUPD_TYPE0_F0 0x000001f6U
-#define _reg_PI_TDFI_PHYUPD_TYPE1_F0 0x000001f7U
-#define _reg_PI_TDFI_PHYUPD_TYPE2_F0 0x000001f8U
-#define _reg_PI_TDFI_PHYUPD_TYPE3_F0 0x000001f9U
-#define _reg_PI_TDFI_PHYUPD_RESP_F1 0x000001faU
-#define _reg_PI_TDFI_PHYUPD_TYPE0_F1 0x000001fbU
-#define _reg_PI_TDFI_PHYUPD_TYPE1_F1 0x000001fcU
-#define _reg_PI_TDFI_PHYUPD_TYPE2_F1 0x000001fdU
-#define _reg_PI_TDFI_PHYUPD_TYPE3_F1 0x000001feU
-#define _reg_PI_TDFI_PHYUPD_RESP_F2 0x000001ffU
-#define _reg_PI_TDFI_PHYUPD_TYPE0_F2 0x00000200U
-#define _reg_PI_TDFI_PHYUPD_TYPE1_F2 0x00000201U
-#define _reg_PI_TDFI_PHYUPD_TYPE2_F2 0x00000202U
-#define _reg_PI_TDFI_PHYUPD_TYPE3_F2 0x00000203U
-#define _reg_PI_CONTROL_ERROR_STATUS 0x00000204U
-#define _reg_PI_EXIT_AFTER_INIT_CALVL 0x00000205U
-#define _reg_PI_FREQ_MAP 0x00000206U
-#define _reg_PI_INIT_WORK_FREQ 0x00000207U
-#define _reg_PI_INIT_DFS_CALVL_ONLY 0x00000208U
-#define _reg_PI_POWER_ON_SEQ_BYPASS_ARRAY 0x00000209U
-#define _reg_PI_POWER_ON_SEQ_END_ARRAY 0x0000020aU
-#define _reg_PI_SEQ1_PAT 0x0000020bU
-#define _reg_PI_SEQ1_PAT_MASK 0x0000020cU
-#define _reg_PI_SEQ2_PAT 0x0000020dU
-#define _reg_PI_SEQ2_PAT_MASK 0x0000020eU
-#define _reg_PI_SEQ3_PAT 0x0000020fU
-#define _reg_PI_SEQ3_PAT_MASK 0x00000210U
-#define _reg_PI_SEQ4_PAT 0x00000211U
-#define _reg_PI_SEQ4_PAT_MASK 0x00000212U
-#define _reg_PI_SEQ5_PAT 0x00000213U
-#define _reg_PI_SEQ5_PAT_MASK 0x00000214U
-#define _reg_PI_SEQ6_PAT 0x00000215U
-#define _reg_PI_SEQ6_PAT_MASK 0x00000216U
-#define _reg_PI_SEQ7_PAT 0x00000217U
-#define _reg_PI_SEQ7_PAT_MASK 0x00000218U
-#define _reg_PI_SEQ8_PAT 0x00000219U
-#define _reg_PI_SEQ8_PAT_MASK 0x0000021aU
-#define _reg_PI_WDT_DISABLE 0x0000021bU
-#define _reg_PI_SW_RST_N 0x0000021cU
-#define _reg_RESERVED_R0 0x0000021dU
-#define _reg_PI_CS_MAP 0x0000021eU
-#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F0 0x0000021fU
-#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F1 0x00000220U
-#define _reg_PI_TDELAY_RDWR_2_BUS_IDLE_F2 0x00000221U
-#define _reg_PI_TMRR 0x00000222U
-#define _reg_PI_WRLAT_F0 0x00000223U
-#define _reg_PI_ADDITIVE_LAT_F0 0x00000224U
-#define _reg_PI_CASLAT_LIN_F0 0x00000225U
-#define _reg_PI_WRLAT_F1 0x00000226U
-#define _reg_PI_ADDITIVE_LAT_F1 0x00000227U
-#define _reg_PI_CASLAT_LIN_F1 0x00000228U
-#define _reg_PI_WRLAT_F2 0x00000229U
-#define _reg_PI_ADDITIVE_LAT_F2 0x0000022aU
-#define _reg_PI_CASLAT_LIN_F2 0x0000022bU
-#define _reg_PI_PREAMBLE_SUPPORT 0x0000022cU
-#define _reg_PI_AREFRESH 0x0000022dU
-#define _reg_PI_MCAREF_FORWARD_ONLY 0x0000022eU
-#define _reg_PI_TRFC_F0 0x0000022fU
-#define _reg_PI_TREF_F0 0x00000230U
-#define _reg_PI_TRFC_F1 0x00000231U
-#define _reg_PI_TREF_F1 0x00000232U
-#define _reg_PI_TRFC_F2 0x00000233U
-#define _reg_PI_TREF_F2 0x00000234U
-#define _reg_RESERVED_H3VER2 0x00000235U
-#define _reg_PI_TREF_INTERVAL 0x00000236U
-#define _reg_PI_FREQ_CHANGE_REG_COPY 0x00000237U
-#define _reg_PI_FREQ_SEL_FROM_REGIF 0x00000238U
-#define _reg_PI_SWLVL_LOAD 0x00000239U
-#define _reg_PI_SWLVL_OP_DONE 0x0000023aU
-#define _reg_PI_SW_WRLVL_RESP_0 0x0000023bU
-#define _reg_PI_SW_WRLVL_RESP_1 0x0000023cU
-#define _reg_PI_SW_WRLVL_RESP_2 0x0000023dU
-#define _reg_PI_SW_WRLVL_RESP_3 0x0000023eU
-#define _reg_PI_SW_RDLVL_RESP_0 0x0000023fU
-#define _reg_PI_SW_RDLVL_RESP_1 0x00000240U
-#define _reg_PI_SW_RDLVL_RESP_2 0x00000241U
-#define _reg_PI_SW_RDLVL_RESP_3 0x00000242U
-#define _reg_PI_SW_CALVL_RESP_0 0x00000243U
-#define _reg_PI_SW_LEVELING_MODE 0x00000244U
-#define _reg_PI_SWLVL_START 0x00000245U
-#define _reg_PI_SWLVL_EXIT 0x00000246U
-#define _reg_PI_SWLVL_WR_SLICE_0 0x00000247U
-#define _reg_PI_SWLVL_RD_SLICE_0 0x00000248U
-#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_0 0x00000249U
-#define _reg_PI_SW_WDQLVL_RESP_0 0x0000024aU
-#define _reg_PI_SWLVL_WR_SLICE_1 0x0000024bU
-#define _reg_PI_SWLVL_RD_SLICE_1 0x0000024cU
-#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_1 0x0000024dU
-#define _reg_PI_SW_WDQLVL_RESP_1 0x0000024eU
-#define _reg_PI_SWLVL_WR_SLICE_2 0x0000024fU
-#define _reg_PI_SWLVL_RD_SLICE_2 0x00000250U
-#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_2 0x00000251U
-#define _reg_PI_SW_WDQLVL_RESP_2 0x00000252U
-#define _reg_PI_SWLVL_WR_SLICE_3 0x00000253U
-#define _reg_PI_SWLVL_RD_SLICE_3 0x00000254U
-#define _reg_PI_SWLVL_VREF_UPDATE_SLICE_3 0x00000255U
-#define _reg_PI_SW_WDQLVL_RESP_3 0x00000256U
-#define _reg_PI_SW_WDQLVL_VREF 0x00000257U
-#define _reg_PI_SWLVL_SM2_START 0x00000258U
-#define _reg_PI_SWLVL_SM2_WR 0x00000259U
-#define _reg_PI_SWLVL_SM2_RD 0x0000025aU
-#define _reg_PI_SEQUENTIAL_LVL_REQ 0x0000025bU
-#define _reg_PI_DFS_PERIOD_EN 0x0000025cU
-#define _reg_PI_SRE_PERIOD_EN 0x0000025dU
-#define _reg_PI_DFI40_POLARITY 0x0000025eU
-#define _reg_PI_16BIT_DRAM_CONNECT 0x0000025fU
-#define _reg_PI_TDFI_CTRL_DELAY_F0 0x00000260U
-#define _reg_PI_TDFI_CTRL_DELAY_F1 0x00000261U
-#define _reg_PI_TDFI_CTRL_DELAY_F2 0x00000262U
-#define _reg_PI_WRLVL_REQ 0x00000263U
-#define _reg_PI_WRLVL_CS 0x00000264U
-#define _reg_PI_WLDQSEN 0x00000265U
-#define _reg_PI_WLMRD 0x00000266U
-#define _reg_PI_WRLVL_EN_F0 0x00000267U
-#define _reg_PI_WRLVL_EN_F1 0x00000268U
-#define _reg_PI_WRLVL_EN_F2 0x00000269U
-#define _reg_PI_WRLVL_EN 0x0000026aU
-#define _reg_PI_WRLVL_INTERVAL 0x0000026bU
-#define _reg_PI_WRLVL_PERIODIC 0x0000026cU
-#define _reg_PI_WRLVL_ON_SREF_EXIT 0x0000026dU
-#define _reg_PI_WRLVL_DISABLE_DFS 0x0000026eU
-#define _reg_PI_WRLVL_RESP_MASK 0x0000026fU
-#define _reg_PI_WRLVL_ROTATE 0x00000270U
-#define _reg_PI_WRLVL_CS_MAP 0x00000271U
-#define _reg_PI_WRLVL_ERROR_STATUS 0x00000272U
-#define _reg_PI_TDFI_WRLVL_EN 0x00000273U
-#define _reg_PI_TDFI_WRLVL_WW_F0 0x00000274U
-#define _reg_PI_TDFI_WRLVL_WW_F1 0x00000275U
-#define _reg_PI_TDFI_WRLVL_WW_F2 0x00000276U
-#define _reg_PI_TDFI_WRLVL_WW 0x00000277U
-#define _reg_PI_TDFI_WRLVL_RESP 0x00000278U
-#define _reg_PI_TDFI_WRLVL_MAX 0x00000279U
-#define _reg_PI_WRLVL_STROBE_NUM 0x0000027aU
-#define _reg_PI_WRLVL_MRR_DQ_RETURN_HIZ 0x0000027bU
-#define _reg_PI_WRLVL_EN_DEASSERT_2_MRR 0x0000027cU
-#define _reg_PI_TODTL_2CMD_F0 0x0000027dU
-#define _reg_PI_ODT_EN_F0 0x0000027eU
-#define _reg_PI_TODTL_2CMD_F1 0x0000027fU
-#define _reg_PI_ODT_EN_F1 0x00000280U
-#define _reg_PI_TODTL_2CMD_F2 0x00000281U
-#define _reg_PI_ODT_EN_F2 0x00000282U
-#define _reg_PI_TODTH_WR 0x00000283U
-#define _reg_PI_TODTH_RD 0x00000284U
-#define _reg_PI_ODT_RD_MAP_CS0 0x00000285U
-#define _reg_PI_ODT_WR_MAP_CS0 0x00000286U
-#define _reg_PI_ODT_RD_MAP_CS1 0x00000287U
-#define _reg_PI_ODT_WR_MAP_CS1 0x00000288U
-#define _reg_PI_ODT_RD_MAP_CS2 0x00000289U
-#define _reg_PI_ODT_WR_MAP_CS2 0x0000028aU
-#define _reg_PI_ODT_RD_MAP_CS3 0x0000028bU
-#define _reg_PI_ODT_WR_MAP_CS3 0x0000028cU
-#define _reg_PI_EN_ODT_ASSERT_EXCEPT_RD 0x0000028dU
-#define _reg_PI_ODTLON_F0 0x0000028eU
-#define _reg_PI_TODTON_MIN_F0 0x0000028fU
-#define _reg_PI_ODTLON_F1 0x00000290U
-#define _reg_PI_TODTON_MIN_F1 0x00000291U
-#define _reg_PI_ODTLON_F2 0x00000292U
-#define _reg_PI_TODTON_MIN_F2 0x00000293U
-#define _reg_PI_WR_TO_ODTH_F0 0x00000294U
-#define _reg_PI_WR_TO_ODTH_F1 0x00000295U
-#define _reg_PI_WR_TO_ODTH_F2 0x00000296U
-#define _reg_PI_RD_TO_ODTH_F0 0x00000297U
-#define _reg_PI_RD_TO_ODTH_F1 0x00000298U
-#define _reg_PI_RD_TO_ODTH_F2 0x00000299U
-#define _reg_PI_ADDRESS_MIRRORING 0x0000029aU
-#define _reg_PI_RDLVL_REQ 0x0000029bU
-#define _reg_PI_RDLVL_GATE_REQ 0x0000029cU
-#define _reg_PI_RDLVL_CS 0x0000029dU
-#define _reg_PI_RDLVL_PAT_0 0x0000029eU
-#define _reg_PI_RDLVL_PAT_1 0x0000029fU
-#define _reg_PI_RDLVL_PAT_2 0x000002a0U
-#define _reg_PI_RDLVL_PAT_3 0x000002a1U
-#define _reg_PI_RDLVL_PAT_4 0x000002a2U
-#define _reg_PI_RDLVL_PAT_5 0x000002a3U
-#define _reg_PI_RDLVL_PAT_6 0x000002a4U
-#define _reg_PI_RDLVL_PAT_7 0x000002a5U
-#define _reg_PI_RDLVL_SEQ_EN 0x000002a6U
-#define _reg_PI_RDLVL_GATE_SEQ_EN 0x000002a7U
-#define _reg_PI_RDLVL_PERIODIC 0x000002a8U
-#define _reg_PI_RDLVL_ON_SREF_EXIT 0x000002a9U
-#define _reg_PI_RDLVL_DISABLE_DFS 0x000002aaU
-#define _reg_PI_RDLVL_GATE_PERIODIC 0x000002abU
-#define _reg_PI_RDLVL_GATE_ON_SREF_EXIT 0x000002acU
-#define _reg_PI_RDLVL_GATE_DISABLE_DFS 0x000002adU
-#define _reg_RESERVED_R1 0x000002aeU
-#define _reg_PI_RDLVL_ROTATE 0x000002afU
-#define _reg_PI_RDLVL_GATE_ROTATE 0x000002b0U
-#define _reg_PI_RDLVL_CS_MAP 0x000002b1U
-#define _reg_PI_RDLVL_GATE_CS_MAP 0x000002b2U
-#define _reg_PI_TDFI_RDLVL_RR 0x000002b3U
-#define _reg_PI_TDFI_RDLVL_RESP 0x000002b4U
-#define _reg_PI_RDLVL_RESP_MASK 0x000002b5U
-#define _reg_PI_TDFI_RDLVL_EN 0x000002b6U
-#define _reg_PI_RDLVL_EN_F0 0x000002b7U
-#define _reg_PI_RDLVL_GATE_EN_F0 0x000002b8U
-#define _reg_PI_RDLVL_EN_F1 0x000002b9U
-#define _reg_PI_RDLVL_GATE_EN_F1 0x000002baU
-#define _reg_PI_RDLVL_EN_F2 0x000002bbU
-#define _reg_PI_RDLVL_GATE_EN_F2 0x000002bcU
-#define _reg_PI_RDLVL_EN 0x000002bdU
-#define _reg_PI_RDLVL_GATE_EN 0x000002beU
-#define _reg_PI_TDFI_RDLVL_MAX 0x000002bfU
-#define _reg_PI_RDLVL_ERROR_STATUS 0x000002c0U
-#define _reg_PI_RDLVL_INTERVAL 0x000002c1U
-#define _reg_PI_RDLVL_GATE_INTERVAL 0x000002c2U
-#define _reg_PI_RDLVL_PATTERN_START 0x000002c3U
-#define _reg_PI_RDLVL_PATTERN_NUM 0x000002c4U
-#define _reg_PI_RDLVL_STROBE_NUM 0x000002c5U
-#define _reg_PI_RDLVL_GATE_STROBE_NUM 0x000002c6U
-#define _reg_PI_LPDDR4_RDLVL_PATTERN_8 0x000002c7U
-#define _reg_PI_LPDDR4_RDLVL_PATTERN_9 0x000002c8U
-#define _reg_PI_LPDDR4_RDLVL_PATTERN_10 0x000002c9U
-#define _reg_PI_LPDDR4_RDLVL_PATTERN_11 0x000002caU
-#define _reg_PI_RD_PREAMBLE_TRAINING_EN 0x000002cbU
-#define _reg_PI_REG_DIMM_ENABLE 0x000002ccU
-#define _reg_PI_RDLAT_ADJ_F0 0x000002cdU
-#define _reg_PI_RDLAT_ADJ_F1 0x000002ceU
-#define _reg_PI_RDLAT_ADJ_F2 0x000002cfU
-#define _reg_PI_TDFI_RDDATA_EN 0x000002d0U
-#define _reg_PI_WRLAT_ADJ_F0 0x000002d1U
-#define _reg_PI_WRLAT_ADJ_F1 0x000002d2U
-#define _reg_PI_WRLAT_ADJ_F2 0x000002d3U
-#define _reg_PI_TDFI_PHY_WRLAT 0x000002d4U
-#define _reg_PI_TDFI_WRCSLAT_F0 0x000002d5U
-#define _reg_PI_TDFI_WRCSLAT_F1 0x000002d6U
-#define _reg_PI_TDFI_WRCSLAT_F2 0x000002d7U
-#define _reg_PI_TDFI_RDCSLAT_F0 0x000002d8U
-#define _reg_PI_TDFI_RDCSLAT_F1 0x000002d9U
-#define _reg_PI_TDFI_RDCSLAT_F2 0x000002daU
-#define _reg_PI_TDFI_PHY_WRDATA_F0 0x000002dbU
-#define _reg_PI_TDFI_PHY_WRDATA_F1 0x000002dcU
-#define _reg_PI_TDFI_PHY_WRDATA_F2 0x000002ddU
-#define _reg_PI_TDFI_PHY_WRDATA 0x000002deU
-#define _reg_PI_CALVL_REQ 0x000002dfU
-#define _reg_PI_CALVL_CS 0x000002e0U
-#define _reg_RESERVED_R2 0x000002e1U
-#define _reg_RESERVED_R3 0x000002e2U
-#define _reg_PI_CALVL_SEQ_EN 0x000002e3U
-#define _reg_PI_CALVL_PERIODIC 0x000002e4U
-#define _reg_PI_CALVL_ON_SREF_EXIT 0x000002e5U
-#define _reg_PI_CALVL_DISABLE_DFS 0x000002e6U
-#define _reg_PI_CALVL_ROTATE 0x000002e7U
-#define _reg_PI_CALVL_CS_MAP 0x000002e8U
-#define _reg_PI_TDFI_CALVL_EN 0x000002e9U
-#define _reg_PI_TDFI_CALVL_CC_F0 0x000002eaU
-#define _reg_PI_TDFI_CALVL_CAPTURE_F0 0x000002ebU
-#define _reg_PI_TDFI_CALVL_CC_F1 0x000002ecU
-#define _reg_PI_TDFI_CALVL_CAPTURE_F1 0x000002edU
-#define _reg_PI_TDFI_CALVL_CC_F2 0x000002eeU
-#define _reg_PI_TDFI_CALVL_CAPTURE_F2 0x000002efU
-#define _reg_PI_TDFI_CALVL_RESP 0x000002f0U
-#define _reg_PI_TDFI_CALVL_MAX 0x000002f1U
-#define _reg_PI_CALVL_RESP_MASK 0x000002f2U
-#define _reg_PI_CALVL_EN_F0 0x000002f3U
-#define _reg_PI_CALVL_EN_F1 0x000002f4U
-#define _reg_PI_CALVL_EN_F2 0x000002f5U
-#define _reg_PI_CALVL_EN 0x000002f6U
-#define _reg_PI_CALVL_ERROR_STATUS 0x000002f7U
-#define _reg_PI_CALVL_INTERVAL 0x000002f8U
-#define _reg_PI_TCACKEL 0x000002f9U
-#define _reg_PI_TCAMRD 0x000002faU
-#define _reg_PI_TCACKEH 0x000002fbU
-#define _reg_PI_TMRZ_F0 0x000002fcU
-#define _reg_PI_TCAENT_F0 0x000002fdU
-#define _reg_PI_TMRZ_F1 0x000002feU
-#define _reg_PI_TCAENT_F1 0x000002ffU
-#define _reg_PI_TMRZ_F2 0x00000300U
-#define _reg_PI_TCAENT_F2 0x00000301U
-#define _reg_PI_TCAEXT 0x00000302U
-#define _reg_PI_CA_TRAIN_VREF_EN 0x00000303U
-#define _reg_PI_TDFI_CACSCA_F0 0x00000304U
-#define _reg_PI_TDFI_CASEL_F0 0x00000305U
-#define _reg_PI_TVREF_SHORT_F0 0x00000306U
-#define _reg_PI_TVREF_LONG_F0 0x00000307U
-#define _reg_PI_TDFI_CACSCA_F1 0x00000308U
-#define _reg_PI_TDFI_CASEL_F1 0x00000309U
-#define _reg_PI_TVREF_SHORT_F1 0x0000030aU
-#define _reg_PI_TVREF_LONG_F1 0x0000030bU
-#define _reg_PI_TDFI_CACSCA_F2 0x0000030cU
-#define _reg_PI_TDFI_CASEL_F2 0x0000030dU
-#define _reg_PI_TVREF_SHORT_F2 0x0000030eU
-#define _reg_PI_TVREF_LONG_F2 0x0000030fU
-#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F0 0x00000310U
-#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F0 0x00000311U
-#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F1 0x00000312U
-#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F1 0x00000313U
-#define _reg_PI_CALVL_VREF_INITIAL_START_POINT_F2 0x00000314U
-#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT_F2 0x00000315U
-#define _reg_PI_CALVL_VREF_INITIAL_START_POINT 0x00000316U
-#define _reg_PI_CALVL_VREF_INITIAL_STOP_POINT 0x00000317U
-#define _reg_PI_CALVL_VREF_INITIAL_STEPSIZE 0x00000318U
-#define _reg_PI_CALVL_VREF_NORMAL_STEPSIZE 0x00000319U
-#define _reg_PI_CALVL_VREF_DELTA_F0 0x0000031aU
-#define _reg_PI_CALVL_VREF_DELTA_F1 0x0000031bU
-#define _reg_PI_CALVL_VREF_DELTA_F2 0x0000031cU
-#define _reg_PI_CALVL_VREF_DELTA 0x0000031dU
-#define _reg_PI_TDFI_INIT_START_MIN 0x0000031eU
-#define _reg_PI_TDFI_INIT_COMPLETE_MIN 0x0000031fU
-#define _reg_PI_TDFI_CALVL_STROBE_F0 0x00000320U
-#define _reg_PI_TXP_F0 0x00000321U
-#define _reg_PI_TMRWCKEL_F0 0x00000322U
-#define _reg_PI_TCKELCK_F0 0x00000323U
-#define _reg_PI_TDFI_CALVL_STROBE_F1 0x00000324U
-#define _reg_PI_TXP_F1 0x00000325U
-#define _reg_PI_TMRWCKEL_F1 0x00000326U
-#define _reg_PI_TCKELCK_F1 0x00000327U
-#define _reg_PI_TDFI_CALVL_STROBE_F2 0x00000328U
-#define _reg_PI_TXP_F2 0x00000329U
-#define _reg_PI_TMRWCKEL_F2 0x0000032aU
-#define _reg_PI_TCKELCK_F2 0x0000032bU
-#define _reg_PI_TCKCKEH 0x0000032cU
-#define _reg_PI_CALVL_STROBE_NUM 0x0000032dU
-#define _reg_PI_SW_CA_TRAIN_VREF 0x0000032eU
-#define _reg_PI_TDFI_INIT_START_F0 0x0000032fU
-#define _reg_PI_TDFI_INIT_COMPLETE_F0 0x00000330U
-#define _reg_PI_TDFI_INIT_START_F1 0x00000331U
-#define _reg_PI_TDFI_INIT_COMPLETE_F1 0x00000332U
-#define _reg_PI_TDFI_INIT_START_F2 0x00000333U
-#define _reg_PI_TDFI_INIT_COMPLETE_F2 0x00000334U
-#define _reg_PI_CLKDISABLE_2_INIT_START 0x00000335U
-#define _reg_PI_INIT_STARTORCOMPLETE_2_CLKDISABLE 0x00000336U
-#define _reg_PI_DRAM_CLK_DISABLE_DEASSERT_SEL 0x00000337U
-#define _reg_PI_REFRESH_BETWEEN_SEGMENT_DISABLE 0x00000338U
-#define _reg_PI_TCKEHDQS_F0 0x00000339U
-#define _reg_PI_TCKEHDQS_F1 0x0000033aU
-#define _reg_PI_TCKEHDQS_F2 0x0000033bU
-#define _reg_PI_MC_DFS_PI_SET_VREF_ENABLE 0x0000033cU
-#define _reg_PI_WDQLVL_VREF_EN 0x0000033dU
-#define _reg_PI_WDQLVL_BST_NUM 0x0000033eU
-#define _reg_PI_TDFI_WDQLVL_WR_F0 0x0000033fU
-#define _reg_PI_TDFI_WDQLVL_WR_F1 0x00000340U
-#define _reg_PI_TDFI_WDQLVL_WR_F2 0x00000341U
-#define _reg_PI_TDFI_WDQLVL_WR 0x00000342U
-#define _reg_PI_TDFI_WDQLVL_RW 0x00000343U
-#define _reg_PI_WDQLVL_RESP_MASK 0x00000344U
-#define _reg_PI_WDQLVL_ROTATE 0x00000345U
-#define _reg_PI_WDQLVL_CS_MAP 0x00000346U
-#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F0 0x00000347U
-#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 0x00000348U
-#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F1 0x00000349U
-#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 0x0000034aU
-#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT_F2 0x0000034bU
-#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 0x0000034cU
-#define _reg_PI_WDQLVL_VREF_INITIAL_START_POINT 0x0000034dU
-#define _reg_PI_WDQLVL_VREF_INITIAL_STOP_POINT 0x0000034eU
-#define _reg_PI_WDQLVL_VREF_INITIAL_STEPSIZE 0x0000034fU
-#define _reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE 0x00000350U
-#define _reg_PI_WDQLVL_VREF_DELTA_F0 0x00000351U
-#define _reg_PI_WDQLVL_VREF_DELTA_F1 0x00000352U
-#define _reg_PI_WDQLVL_VREF_DELTA_F2 0x00000353U
-#define _reg_PI_WDQLVL_VREF_DELTA 0x00000354U
-#define _reg_PI_WDQLVL_PERIODIC 0x00000355U
-#define _reg_PI_WDQLVL_REQ 0x00000356U
-#define _reg_PI_WDQLVL_CS 0x00000357U
-#define _reg_PI_TDFI_WDQLVL_EN 0x00000358U
-#define _reg_PI_TDFI_WDQLVL_RESP 0x00000359U
-#define _reg_PI_TDFI_WDQLVL_MAX 0x0000035aU
-#define _reg_PI_WDQLVL_INTERVAL 0x0000035bU
-#define _reg_PI_WDQLVL_EN_F0 0x0000035cU
-#define _reg_PI_WDQLVL_EN_F1 0x0000035dU
-#define _reg_PI_WDQLVL_EN_F2 0x0000035eU
-#define _reg_PI_WDQLVL_EN 0x0000035fU
-#define _reg_PI_WDQLVL_ON_SREF_EXIT 0x00000360U
-#define _reg_PI_WDQLVL_DISABLE_DFS 0x00000361U
-#define _reg_PI_WDQLVL_ERROR_STATUS 0x00000362U
-#define _reg_PI_MR1_DATA_F0_0 0x00000363U
-#define _reg_PI_MR2_DATA_F0_0 0x00000364U
-#define _reg_PI_MR3_DATA_F0_0 0x00000365U
-#define _reg_PI_MR11_DATA_F0_0 0x00000366U
-#define _reg_PI_MR12_DATA_F0_0 0x00000367U
-#define _reg_PI_MR14_DATA_F0_0 0x00000368U
-#define _reg_PI_MR22_DATA_F0_0 0x00000369U
-#define _reg_PI_MR1_DATA_F1_0 0x0000036aU
-#define _reg_PI_MR2_DATA_F1_0 0x0000036bU
-#define _reg_PI_MR3_DATA_F1_0 0x0000036cU
-#define _reg_PI_MR11_DATA_F1_0 0x0000036dU
-#define _reg_PI_MR12_DATA_F1_0 0x0000036eU
-#define _reg_PI_MR14_DATA_F1_0 0x0000036fU
-#define _reg_PI_MR22_DATA_F1_0 0x00000370U
-#define _reg_PI_MR1_DATA_F2_0 0x00000371U
-#define _reg_PI_MR2_DATA_F2_0 0x00000372U
-#define _reg_PI_MR3_DATA_F2_0 0x00000373U
-#define _reg_PI_MR11_DATA_F2_0 0x00000374U
-#define _reg_PI_MR12_DATA_F2_0 0x00000375U
-#define _reg_PI_MR14_DATA_F2_0 0x00000376U
-#define _reg_PI_MR22_DATA_F2_0 0x00000377U
-#define _reg_PI_MR13_DATA_0 0x00000378U
-#define _reg_PI_MR1_DATA_F0_1 0x00000379U
-#define _reg_PI_MR2_DATA_F0_1 0x0000037aU
-#define _reg_PI_MR3_DATA_F0_1 0x0000037bU
-#define _reg_PI_MR11_DATA_F0_1 0x0000037cU
-#define _reg_PI_MR12_DATA_F0_1 0x0000037dU
-#define _reg_PI_MR14_DATA_F0_1 0x0000037eU
-#define _reg_PI_MR22_DATA_F0_1 0x0000037fU
-#define _reg_PI_MR1_DATA_F1_1 0x00000380U
-#define _reg_PI_MR2_DATA_F1_1 0x00000381U
-#define _reg_PI_MR3_DATA_F1_1 0x00000382U
-#define _reg_PI_MR11_DATA_F1_1 0x00000383U
-#define _reg_PI_MR12_DATA_F1_1 0x00000384U
-#define _reg_PI_MR14_DATA_F1_1 0x00000385U
-#define _reg_PI_MR22_DATA_F1_1 0x00000386U
-#define _reg_PI_MR1_DATA_F2_1 0x00000387U
-#define _reg_PI_MR2_DATA_F2_1 0x00000388U
-#define _reg_PI_MR3_DATA_F2_1 0x00000389U
-#define _reg_PI_MR11_DATA_F2_1 0x0000038aU
-#define _reg_PI_MR12_DATA_F2_1 0x0000038bU
-#define _reg_PI_MR14_DATA_F2_1 0x0000038cU
-#define _reg_PI_MR22_DATA_F2_1 0x0000038dU
-#define _reg_PI_MR13_DATA_1 0x0000038eU
-#define _reg_PI_MR1_DATA_F0_2 0x0000038fU
-#define _reg_PI_MR2_DATA_F0_2 0x00000390U
-#define _reg_PI_MR3_DATA_F0_2 0x00000391U
-#define _reg_PI_MR11_DATA_F0_2 0x00000392U
-#define _reg_PI_MR12_DATA_F0_2 0x00000393U
-#define _reg_PI_MR14_DATA_F0_2 0x00000394U
-#define _reg_PI_MR22_DATA_F0_2 0x00000395U
-#define _reg_PI_MR1_DATA_F1_2 0x00000396U
-#define _reg_PI_MR2_DATA_F1_2 0x00000397U
-#define _reg_PI_MR3_DATA_F1_2 0x00000398U
-#define _reg_PI_MR11_DATA_F1_2 0x00000399U
-#define _reg_PI_MR12_DATA_F1_2 0x0000039aU
-#define _reg_PI_MR14_DATA_F1_2 0x0000039bU
-#define _reg_PI_MR22_DATA_F1_2 0x0000039cU
-#define _reg_PI_MR1_DATA_F2_2 0x0000039dU
-#define _reg_PI_MR2_DATA_F2_2 0x0000039eU
-#define _reg_PI_MR3_DATA_F2_2 0x0000039fU
-#define _reg_PI_MR11_DATA_F2_2 0x000003a0U
-#define _reg_PI_MR12_DATA_F2_2 0x000003a1U
-#define _reg_PI_MR14_DATA_F2_2 0x000003a2U
-#define _reg_PI_MR22_DATA_F2_2 0x000003a3U
-#define _reg_PI_MR13_DATA_2 0x000003a4U
-#define _reg_PI_MR1_DATA_F0_3 0x000003a5U
-#define _reg_PI_MR2_DATA_F0_3 0x000003a6U
-#define _reg_PI_MR3_DATA_F0_3 0x000003a7U
-#define _reg_PI_MR11_DATA_F0_3 0x000003a8U
-#define _reg_PI_MR12_DATA_F0_3 0x000003a9U
-#define _reg_PI_MR14_DATA_F0_3 0x000003aaU
-#define _reg_PI_MR22_DATA_F0_3 0x000003abU
-#define _reg_PI_MR1_DATA_F1_3 0x000003acU
-#define _reg_PI_MR2_DATA_F1_3 0x000003adU
-#define _reg_PI_MR3_DATA_F1_3 0x000003aeU
-#define _reg_PI_MR11_DATA_F1_3 0x000003afU
-#define _reg_PI_MR12_DATA_F1_3 0x000003b0U
-#define _reg_PI_MR14_DATA_F1_3 0x000003b1U
-#define _reg_PI_MR22_DATA_F1_3 0x000003b2U
-#define _reg_PI_MR1_DATA_F2_3 0x000003b3U
-#define _reg_PI_MR2_DATA_F2_3 0x000003b4U
-#define _reg_PI_MR3_DATA_F2_3 0x000003b5U
-#define _reg_PI_MR11_DATA_F2_3 0x000003b6U
-#define _reg_PI_MR12_DATA_F2_3 0x000003b7U
-#define _reg_PI_MR14_DATA_F2_3 0x000003b8U
-#define _reg_PI_MR22_DATA_F2_3 0x000003b9U
-#define _reg_PI_MR13_DATA_3 0x000003baU
-#define _reg_PI_BANK_DIFF 0x000003bbU
-#define _reg_PI_ROW_DIFF 0x000003bcU
-#define _reg_PI_TFC_F0 0x000003bdU
-#define _reg_PI_TFC_F1 0x000003beU
-#define _reg_PI_TFC_F2 0x000003bfU
-#define _reg_PI_TCCD 0x000003c0U
-#define _reg_PI_TRTP_F0 0x000003c1U
-#define _reg_PI_TRP_F0 0x000003c2U
-#define _reg_PI_TRCD_F0 0x000003c3U
-#define _reg_PI_TWTR_F0 0x000003c4U
-#define _reg_PI_TWR_F0 0x000003c5U
-#define _reg_PI_TRAS_MAX_F0 0x000003c6U
-#define _reg_PI_TRAS_MIN_F0 0x000003c7U
-#define _reg_PI_TDQSCK_MAX_F0 0x000003c8U
-#define _reg_PI_TCCDMW_F0 0x000003c9U
-#define _reg_PI_TSR_F0 0x000003caU
-#define _reg_PI_TMRD_F0 0x000003cbU
-#define _reg_PI_TMRW_F0 0x000003ccU
-#define _reg_PI_TMOD_F0 0x000003cdU
-#define _reg_PI_TRTP_F1 0x000003ceU
-#define _reg_PI_TRP_F1 0x000003cfU
-#define _reg_PI_TRCD_F1 0x000003d0U
-#define _reg_PI_TWTR_F1 0x000003d1U
-#define _reg_PI_TWR_F1 0x000003d2U
-#define _reg_PI_TRAS_MAX_F1 0x000003d3U
-#define _reg_PI_TRAS_MIN_F1 0x000003d4U
-#define _reg_PI_TDQSCK_MAX_F1 0x000003d5U
-#define _reg_PI_TCCDMW_F1 0x000003d6U
-#define _reg_PI_TSR_F1 0x000003d7U
-#define _reg_PI_TMRD_F1 0x000003d8U
-#define _reg_PI_TMRW_F1 0x000003d9U
-#define _reg_PI_TMOD_F1 0x000003daU
-#define _reg_PI_TRTP_F2 0x000003dbU
-#define _reg_PI_TRP_F2 0x000003dcU
-#define _reg_PI_TRCD_F2 0x000003ddU
-#define _reg_PI_TWTR_F2 0x000003deU
-#define _reg_PI_TWR_F2 0x000003dfU
-#define _reg_PI_TRAS_MAX_F2 0x000003e0U
-#define _reg_PI_TRAS_MIN_F2 0x000003e1U
-#define _reg_PI_TDQSCK_MAX_F2 0x000003e2U
-#define _reg_PI_TCCDMW_F2 0x000003e3U
-#define _reg_PI_TSR_F2 0x000003e4U
-#define _reg_PI_TMRD_F2 0x000003e5U
-#define _reg_PI_TMRW_F2 0x000003e6U
-#define _reg_PI_TMOD_F2 0x000003e7U
-#define _reg_RESERVED_R4 0x000003e8U
-#define _reg_RESERVED_R5 0x000003e9U
-#define _reg_RESERVED_R6 0x000003eaU
-#define _reg_RESERVED_R7 0x000003ebU
-#define _reg_RESERVED_R8 0x000003ecU
-#define _reg_RESERVED_R9 0x000003edU
-#define _reg_RESERVED_R10 0x000003eeU
-#define _reg_RESERVED_R11 0x000003efU
-#define _reg_RESERVED_R12 0x000003f0U
-#define _reg_RESERVED_R13 0x000003f1U
-#define _reg_RESERVED_R14 0x000003f2U
-#define _reg_RESERVED_R15 0x000003f3U
-#define _reg_RESERVED_R16 0x000003f4U
-#define _reg_RESERVED_R17 0x000003f5U
-#define _reg_RESERVED_R18 0x000003f6U
-#define _reg_RESERVED_R19 0x000003f7U
-#define _reg_RESERVED_R20 0x000003f8U
-#define _reg_RESERVED_R21 0x000003f9U
-#define _reg_RESERVED_R22 0x000003faU
-#define _reg_RESERVED_R23 0x000003fbU
-#define _reg_PI_INT_STATUS 0x000003fcU
-#define _reg_PI_INT_ACK 0x000003fdU
-#define _reg_PI_INT_MASK 0x000003feU
-#define _reg_PI_BIST_EXP_DATA_P0 0x000003ffU
-#define _reg_PI_BIST_EXP_DATA_P1 0x00000400U
-#define _reg_PI_BIST_EXP_DATA_P2 0x00000401U
-#define _reg_PI_BIST_EXP_DATA_P3 0x00000402U
-#define _reg_PI_BIST_FAIL_DATA_P0 0x00000403U
-#define _reg_PI_BIST_FAIL_DATA_P1 0x00000404U
-#define _reg_PI_BIST_FAIL_DATA_P2 0x00000405U
-#define _reg_PI_BIST_FAIL_DATA_P3 0x00000406U
-#define _reg_PI_BIST_FAIL_ADDR_P0 0x00000407U
-#define _reg_PI_BIST_FAIL_ADDR_P1 0x00000408U
-#define _reg_PI_BSTLEN 0x00000409U
-#define _reg_PI_LONG_COUNT_MASK 0x0000040aU
-#define _reg_PI_CMD_SWAP_EN 0x0000040bU
-#define _reg_PI_CKE_MUX_0 0x0000040cU
-#define _reg_PI_CKE_MUX_1 0x0000040dU
-#define _reg_PI_CKE_MUX_2 0x0000040eU
-#define _reg_PI_CKE_MUX_3 0x0000040fU
-#define _reg_PI_CS_MUX_0 0x00000410U
-#define _reg_PI_CS_MUX_1 0x00000411U
-#define _reg_PI_CS_MUX_2 0x00000412U
-#define _reg_PI_CS_MUX_3 0x00000413U
-#define _reg_PI_RAS_N_MUX 0x00000414U
-#define _reg_PI_CAS_N_MUX 0x00000415U
-#define _reg_PI_WE_N_MUX 0x00000416U
-#define _reg_PI_BANK_MUX_0 0x00000417U
-#define _reg_PI_BANK_MUX_1 0x00000418U
-#define _reg_PI_BANK_MUX_2 0x00000419U
-#define _reg_PI_ODT_MUX_0 0x0000041aU
-#define _reg_PI_ODT_MUX_1 0x0000041bU
-#define _reg_PI_ODT_MUX_2 0x0000041cU
-#define _reg_PI_ODT_MUX_3 0x0000041dU
-#define _reg_PI_RESET_N_MUX_0 0x0000041eU
-#define _reg_PI_RESET_N_MUX_1 0x0000041fU
-#define _reg_PI_RESET_N_MUX_2 0x00000420U
-#define _reg_PI_RESET_N_MUX_3 0x00000421U
-#define _reg_PI_DATA_BYTE_SWAP_EN 0x00000422U
-#define _reg_PI_DATA_BYTE_SWAP_SLICE0 0x00000423U
-#define _reg_PI_DATA_BYTE_SWAP_SLICE1 0x00000424U
-#define _reg_PI_DATA_BYTE_SWAP_SLICE2 0x00000425U
-#define _reg_PI_DATA_BYTE_SWAP_SLICE3 0x00000426U
-#define _reg_PI_CTRLUPD_REQ_PER_AREF_EN 0x00000427U
-#define _reg_PI_TDFI_CTRLUPD_MIN 0x00000428U
-#define _reg_PI_TDFI_CTRLUPD_MAX_F0 0x00000429U
-#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F0 0x0000042aU
-#define _reg_PI_TDFI_CTRLUPD_MAX_F1 0x0000042bU
-#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F1 0x0000042cU
-#define _reg_PI_TDFI_CTRLUPD_MAX_F2 0x0000042dU
-#define _reg_PI_TDFI_CTRLUPD_INTERVAL_F2 0x0000042eU
-#define _reg_PI_UPDATE_ERROR_STATUS 0x0000042fU
-#define _reg_PI_BIST_GO 0x00000430U
-#define _reg_PI_BIST_RESULT 0x00000431U
-#define _reg_PI_ADDR_SPACE 0x00000432U
-#define _reg_PI_BIST_DATA_CHECK 0x00000433U
-#define _reg_PI_BIST_ADDR_CHECK 0x00000434U
-#define _reg_PI_BIST_START_ADDRESS_P0 0x00000435U
-#define _reg_PI_BIST_START_ADDRESS_P1 0x00000436U
-#define _reg_PI_BIST_DATA_MASK_P0 0x00000437U
-#define _reg_PI_BIST_DATA_MASK_P1 0x00000438U
-#define _reg_PI_BIST_ERR_COUNT 0x00000439U
-#define _reg_PI_BIST_ERR_STOP 0x0000043aU
-#define _reg_PI_BIST_ADDR_MASK_0_P0 0x0000043bU
-#define _reg_PI_BIST_ADDR_MASK_0_P1 0x0000043cU
-#define _reg_PI_BIST_ADDR_MASK_1_P0 0x0000043dU
-#define _reg_PI_BIST_ADDR_MASK_1_P1 0x0000043eU
-#define _reg_PI_BIST_ADDR_MASK_2_P0 0x0000043fU
-#define _reg_PI_BIST_ADDR_MASK_2_P1 0x00000440U
-#define _reg_PI_BIST_ADDR_MASK_3_P0 0x00000441U
-#define _reg_PI_BIST_ADDR_MASK_3_P1 0x00000442U
-#define _reg_PI_BIST_ADDR_MASK_4_P0 0x00000443U
-#define _reg_PI_BIST_ADDR_MASK_4_P1 0x00000444U
-#define _reg_PI_BIST_ADDR_MASK_5_P0 0x00000445U
-#define _reg_PI_BIST_ADDR_MASK_5_P1 0x00000446U
-#define _reg_PI_BIST_ADDR_MASK_6_P0 0x00000447U
-#define _reg_PI_BIST_ADDR_MASK_6_P1 0x00000448U
-#define _reg_PI_BIST_ADDR_MASK_7_P0 0x00000449U
-#define _reg_PI_BIST_ADDR_MASK_7_P1 0x0000044aU
-#define _reg_PI_BIST_ADDR_MASK_8_P0 0x0000044bU
-#define _reg_PI_BIST_ADDR_MASK_8_P1 0x0000044cU
-#define _reg_PI_BIST_ADDR_MASK_9_P0 0x0000044dU
-#define _reg_PI_BIST_ADDR_MASK_9_P1 0x0000044eU
-#define _reg_PI_BIST_MODE 0x0000044fU
-#define _reg_PI_BIST_ADDR_MODE 0x00000450U
-#define _reg_PI_BIST_PAT_MODE 0x00000451U
-#define _reg_PI_BIST_USER_PAT_P0 0x00000452U
-#define _reg_PI_BIST_USER_PAT_P1 0x00000453U
-#define _reg_PI_BIST_USER_PAT_P2 0x00000454U
-#define _reg_PI_BIST_USER_PAT_P3 0x00000455U
-#define _reg_PI_BIST_PAT_NUM 0x00000456U
-#define _reg_PI_BIST_STAGE_0 0x00000457U
-#define _reg_PI_BIST_STAGE_1 0x00000458U
-#define _reg_PI_BIST_STAGE_2 0x00000459U
-#define _reg_PI_BIST_STAGE_3 0x0000045aU
-#define _reg_PI_BIST_STAGE_4 0x0000045bU
-#define _reg_PI_BIST_STAGE_5 0x0000045cU
-#define _reg_PI_BIST_STAGE_6 0x0000045dU
-#define _reg_PI_BIST_STAGE_7 0x0000045eU
-#define _reg_PI_COL_DIFF 0x0000045fU
-#define _reg_PI_SELF_REFRESH_EN 0x00000460U
-#define _reg_PI_TXSR_F0 0x00000461U
-#define _reg_PI_TXSR_F1 0x00000462U
-#define _reg_PI_TXSR_F2 0x00000463U
-#define _reg_PI_MONITOR_SRC_SEL_0 0x00000464U
-#define _reg_PI_MONITOR_CAP_SEL_0 0x00000465U
-#define _reg_PI_MONITOR_0 0x00000466U
-#define _reg_PI_MONITOR_SRC_SEL_1 0x00000467U
-#define _reg_PI_MONITOR_CAP_SEL_1 0x00000468U
-#define _reg_PI_MONITOR_1 0x00000469U
-#define _reg_PI_MONITOR_SRC_SEL_2 0x0000046aU
-#define _reg_PI_MONITOR_CAP_SEL_2 0x0000046bU
-#define _reg_PI_MONITOR_2 0x0000046cU
-#define _reg_PI_MONITOR_SRC_SEL_3 0x0000046dU
-#define _reg_PI_MONITOR_CAP_SEL_3 0x0000046eU
-#define _reg_PI_MONITOR_3 0x0000046fU
-#define _reg_PI_MONITOR_SRC_SEL_4 0x00000470U
-#define _reg_PI_MONITOR_CAP_SEL_4 0x00000471U
-#define _reg_PI_MONITOR_4 0x00000472U
-#define _reg_PI_MONITOR_SRC_SEL_5 0x00000473U
-#define _reg_PI_MONITOR_CAP_SEL_5 0x00000474U
-#define _reg_PI_MONITOR_5 0x00000475U
-#define _reg_PI_MONITOR_SRC_SEL_6 0x00000476U
-#define _reg_PI_MONITOR_CAP_SEL_6 0x00000477U
-#define _reg_PI_MONITOR_6 0x00000478U
-#define _reg_PI_MONITOR_SRC_SEL_7 0x00000479U
-#define _reg_PI_MONITOR_CAP_SEL_7 0x0000047aU
-#define _reg_PI_MONITOR_7 0x0000047bU
-#define _reg_PI_MONITOR_STROBE 0x0000047cU
-#define _reg_PI_DLL_LOCK 0x0000047dU
-#define _reg_PI_FREQ_NUMBER_STATUS 0x0000047eU
-#define _reg_RESERVED_R24 0x0000047fU
-#define _reg_PI_PHYMSTR_TYPE 0x00000480U
-#define _reg_PI_POWER_REDUC_EN 0x00000481U
-#define _reg_RESERVED_R25 0x00000482U
-#define _reg_RESERVED_R26 0x00000483U
-#define _reg_RESERVED_R27 0x00000484U
-#define _reg_RESERVED_R28 0x00000485U
-#define _reg_RESERVED_R29 0x00000486U
-#define _reg_RESERVED_R30 0x00000487U
-#define _reg_RESERVED_R31 0x00000488U
-#define _reg_RESERVED_R32 0x00000489U
-#define _reg_RESERVED_R33 0x0000048aU
-#define _reg_RESERVED_R34 0x0000048bU
-#define _reg_RESERVED_R35 0x0000048cU
-#define _reg_RESERVED_R36 0x0000048dU
-#define _reg_RESERVED_R37 0x0000048eU
-#define _reg_RESERVED_R38 0x0000048fU
-#define _reg_RESERVED_R39 0x00000490U
-#define _reg_PI_WRLVL_MAX_STROBE_PEND 0x00000491U
-#define _reg_PI_TSDO_F0 0x00000492U
-#define _reg_PI_TSDO_F1 0x00000493U
-#define _reg_PI_TSDO_F2 0x00000494U
-
-#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xffffU)
-#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xffU)
-#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xffU)
-
-static const uint32_t DDR_REGDEF_TBL[4][1173] = {
- {
-/*0000*/ 0xffffffffU,
-/*0001*/ 0xffffffffU,
-/*0002*/ 0x000b0400U,
-/*0003*/ 0xffffffffU,
-/*0004*/ 0xffffffffU,
-/*0005*/ 0x10010400U,
-/*0006*/ 0x18050400U,
-/*0007*/ 0x00050401U,
-/*0008*/ 0x08050401U,
-/*0009*/ 0x10050401U,
-/*000a*/ 0x18050401U,
-/*000b*/ 0x00050402U,
-/*000c*/ 0x08050402U,
-/*000d*/ 0x10050402U,
-/*000e*/ 0x18050402U,
-/*000f*/ 0x00040403U,
-/*0010*/ 0x08030403U,
-/*0011*/ 0x00180404U,
-/*0012*/ 0x18030404U,
-/*0013*/ 0x00180405U,
-/*0014*/ 0x18020405U,
-/*0015*/ 0x00010406U,
-/*0016*/ 0x08020406U,
-/*0017*/ 0x10010406U,
-/*0018*/ 0x18010406U,
-/*0019*/ 0x00020407U,
-/*001a*/ 0x08040407U,
-/*001b*/ 0x10040407U,
-/*001c*/ 0x18040407U,
-/*001d*/ 0x000a0408U,
-/*001e*/ 0x10040408U,
-/*001f*/ 0xffffffffU,
-/*0020*/ 0xffffffffU,
-/*0021*/ 0x18070408U,
-/*0022*/ 0xffffffffU,
-/*0023*/ 0xffffffffU,
-/*0024*/ 0xffffffffU,
-/*0025*/ 0xffffffffU,
-/*0026*/ 0xffffffffU,
-/*0027*/ 0xffffffffU,
-/*0028*/ 0x000a0409U,
-/*0029*/ 0x10040409U,
-/*002a*/ 0x18010409U,
-/*002b*/ 0x0001040aU,
-/*002c*/ 0x0802040aU,
-/*002d*/ 0x1009040aU,
-/*002e*/ 0x0009040bU,
-/*002f*/ 0x1002040bU,
-/*0030*/ 0x0020040cU,
-/*0031*/ 0xffffffffU,
-/*0032*/ 0x0001040dU,
-/*0033*/ 0xffffffffU,
-/*0034*/ 0xffffffffU,
-/*0035*/ 0xffffffffU,
-/*0036*/ 0xffffffffU,
-/*0037*/ 0x0020040eU,
-/*0038*/ 0x0020040fU,
-/*0039*/ 0x00200410U,
-/*003a*/ 0x00200411U,
-/*003b*/ 0x00030412U,
-/*003c*/ 0x08010412U,
-/*003d*/ 0x10030412U,
-/*003e*/ 0x18030412U,
-/*003f*/ 0x00040413U,
-/*0040*/ 0x08040413U,
-/*0041*/ 0x10040413U,
-/*0042*/ 0x18040413U,
-/*0043*/ 0x00010414U,
-/*0044*/ 0x08010414U,
-/*0045*/ 0x10060414U,
-/*0046*/ 0x18040414U,
-/*0047*/ 0xffffffffU,
-/*0048*/ 0x00060415U,
-/*0049*/ 0x08040415U,
-/*004a*/ 0x10060415U,
-/*004b*/ 0x18040415U,
-/*004c*/ 0x00020416U,
-/*004d*/ 0x08050416U,
-/*004e*/ 0x10080416U,
-/*004f*/ 0x00200417U,
-/*0050*/ 0x00060418U,
-/*0051*/ 0x08030418U,
-/*0052*/ 0x100b0418U,
-/*0053*/ 0x00040419U,
-/*0054*/ 0x08040419U,
-/*0055*/ 0x10040419U,
-/*0056*/ 0xffffffffU,
-/*0057*/ 0x18010419U,
-/*0058*/ 0x0009041aU,
-/*0059*/ 0x0020041bU,
-/*005a*/ 0x0020041cU,
-/*005b*/ 0x0020041dU,
-/*005c*/ 0x0020041eU,
-/*005d*/ 0x0010041fU,
-/*005e*/ 0x00200420U,
-/*005f*/ 0x00010421U,
-/*0060*/ 0x08060421U,
-/*0061*/ 0x10080421U,
-/*0062*/ 0x00200422U,
-/*0063*/ 0xffffffffU,
-/*0064*/ 0x000a0423U,
-/*0065*/ 0x10060423U,
-/*0066*/ 0x18070423U,
-/*0067*/ 0x00080424U,
-/*0068*/ 0x08080424U,
-/*0069*/ 0x100a0424U,
-/*006a*/ 0x00070425U,
-/*006b*/ 0x08080425U,
-/*006c*/ 0x10080425U,
-/*006d*/ 0x18030425U,
-/*006e*/ 0x000a0426U,
-/*006f*/ 0x100a0426U,
-/*0070*/ 0x00110427U,
-/*0071*/ 0x00090428U,
-/*0072*/ 0x10090428U,
-/*0073*/ 0x00100429U,
-/*0074*/ 0x100e0429U,
-/*0075*/ 0x000e042aU,
-/*0076*/ 0x100c042aU,
-/*0077*/ 0x000a042bU,
-/*0078*/ 0x100a042bU,
-/*0079*/ 0x0002042cU,
-/*007a*/ 0x0020042dU,
-/*007b*/ 0x000b042eU,
-/*007c*/ 0x100b042eU,
-/*007d*/ 0x0020042fU,
-/*007e*/ 0x00120430U,
-/*007f*/ 0x00200431U,
-/*0080*/ 0x00200432U,
-/*0081*/ 0xffffffffU,
-/*0082*/ 0xffffffffU,
-/*0083*/ 0x00010433U,
-/*0084*/ 0x08010433U,
-/*0085*/ 0x10080433U,
-/*0086*/ 0x000c0434U,
-/*0087*/ 0x100c0434U,
-/*0088*/ 0x000c0435U,
-/*0089*/ 0x100c0435U,
-/*008a*/ 0x000c0436U,
-/*008b*/ 0x100c0436U,
-/*008c*/ 0x000c0437U,
-/*008d*/ 0x100c0437U,
-/*008e*/ 0x000c0438U,
-/*008f*/ 0x100c0438U,
-/*0090*/ 0x000c0439U,
-/*0091*/ 0x100b0439U,
-/*0092*/ 0xffffffffU,
-/*0093*/ 0xffffffffU,
-/*0094*/ 0x000b043aU,
-/*0095*/ 0x100b043aU,
-/*0096*/ 0x000b043bU,
-/*0097*/ 0x100b043bU,
-/*0098*/ 0x000b043cU,
-/*0099*/ 0x100b043cU,
-/*009a*/ 0x000b043dU,
-/*009b*/ 0x100b043dU,
-/*009c*/ 0x000b043eU,
-/*009d*/ 0x100a043eU,
-/*009e*/ 0xffffffffU,
-/*009f*/ 0x000a043fU,
-/*00a0*/ 0x100a043fU,
-/*00a1*/ 0x000a0440U,
-/*00a2*/ 0x100a0440U,
-/*00a3*/ 0x000a0441U,
-/*00a4*/ 0x100a0441U,
-/*00a5*/ 0x000a0442U,
-/*00a6*/ 0x100a0442U,
-/*00a7*/ 0xffffffffU,
-/*00a8*/ 0x000a0443U,
-/*00a9*/ 0x100a0443U,
-/*00aa*/ 0x000a0444U,
-/*00ab*/ 0x100a0444U,
-/*00ac*/ 0x000a0445U,
-/*00ad*/ 0x100a0445U,
-/*00ae*/ 0x000a0446U,
-/*00af*/ 0x100a0446U,
-/*00b0*/ 0x000a0447U,
-/*00b1*/ 0x100a0447U,
-/*00b2*/ 0x000a0448U,
-/*00b3*/ 0x100a0448U,
-/*00b4*/ 0x000a0449U,
-/*00b5*/ 0x100a0449U,
-/*00b6*/ 0x000a044aU,
-/*00b7*/ 0x100a044aU,
-/*00b8*/ 0x000a044bU,
-/*00b9*/ 0x100a044bU,
-/*00ba*/ 0x000a044cU,
-/*00bb*/ 0x1004044cU,
-/*00bc*/ 0x1803044cU,
-/*00bd*/ 0x000a044dU,
-/*00be*/ 0x100a044dU,
-/*00bf*/ 0x0001044eU,
-/*00c0*/ 0x080a044eU,
-/*00c1*/ 0x1804044eU,
-/*00c2*/ 0x000b044fU,
-/*00c3*/ 0x100a044fU,
-/*00c4*/ 0xffffffffU,
-/*00c5*/ 0x00080450U,
-/*00c6*/ 0x08080450U,
-/*00c7*/ 0x10080450U,
-/*00c8*/ 0x18080450U,
-/*00c9*/ 0x00080451U,
-/*00ca*/ 0xffffffffU,
-/*00cb*/ 0x08080451U,
-/*00cc*/ 0x10010451U,
-/*00cd*/ 0x18080451U,
-/*00ce*/ 0x00080452U,
-/*00cf*/ 0x08020452U,
-/*00d0*/ 0x10020452U,
-/*00d1*/ 0x18040452U,
-/*00d2*/ 0x00040453U,
-/*00d3*/ 0xffffffffU,
-/*00d4*/ 0x08040453U,
-/*00d5*/ 0x100a0453U,
-/*00d6*/ 0x00060454U,
-/*00d7*/ 0x08080454U,
-/*00d8*/ 0xffffffffU,
-/*00d9*/ 0x10040454U,
-/*00da*/ 0x18040454U,
-/*00db*/ 0x00050455U,
-/*00dc*/ 0x08040455U,
-/*00dd*/ 0x10050455U,
-/*00de*/ 0x000a0456U,
-/*00df*/ 0x100a0456U,
-/*00e0*/ 0x00080457U,
-/*00e1*/ 0xffffffffU,
-/*00e2*/ 0x08040457U,
-/*00e3*/ 0xffffffffU,
-/*00e4*/ 0xffffffffU,
-/*00e5*/ 0x00050600U,
-/*00e6*/ 0x08050600U,
-/*00e7*/ 0x10050600U,
-/*00e8*/ 0x18050600U,
-/*00e9*/ 0x00050601U,
-/*00ea*/ 0x08050601U,
-/*00eb*/ 0x100b0601U,
-/*00ec*/ 0x00010602U,
-/*00ed*/ 0x08030602U,
-/*00ee*/ 0x00200603U,
-/*00ef*/ 0xffffffffU,
-/*00f0*/ 0x00030604U,
-/*00f1*/ 0x080a0604U,
-/*00f2*/ 0xffffffffU,
-/*00f3*/ 0xffffffffU,
-/*00f4*/ 0x18030604U,
-/*00f5*/ 0x00030605U,
-/*00f6*/ 0x08010605U,
-/*00f7*/ 0x10010605U,
-/*00f8*/ 0x18060605U,
-/*00f9*/ 0xffffffffU,
-/*00fa*/ 0xffffffffU,
-/*00fb*/ 0xffffffffU,
-/*00fc*/ 0x00020606U,
-/*00fd*/ 0x08030606U,
-/*00fe*/ 0x10010606U,
-/*00ff*/ 0x000f0607U,
-/*0100*/ 0x00200608U,
-/*0101*/ 0x00200609U,
-/*0102*/ 0x000b060aU,
-/*0103*/ 0x100b060aU,
-/*0104*/ 0x000b060bU,
-/*0105*/ 0xffffffffU,
-/*0106*/ 0xffffffffU,
-/*0107*/ 0x0018060cU,
-/*0108*/ 0x0018060dU,
-/*0109*/ 0x0018060eU,
-/*010a*/ 0x0018060fU,
-/*010b*/ 0x1804060fU,
-/*010c*/ 0x00050610U,
-/*010d*/ 0x08020610U,
-/*010e*/ 0x10040610U,
-/*010f*/ 0x18040610U,
-/*0110*/ 0x00010611U,
-/*0111*/ 0x08010611U,
-/*0112*/ 0x10010611U,
-/*0113*/ 0x18030611U,
-/*0114*/ 0x00200612U,
-/*0115*/ 0x00200613U,
-/*0116*/ 0x00010614U,
-/*0117*/ 0x08140614U,
-/*0118*/ 0x00140615U,
-/*0119*/ 0x00140616U,
-/*011a*/ 0x00140617U,
-/*011b*/ 0x00140618U,
-/*011c*/ 0x00140619U,
-/*011d*/ 0x0014061aU,
-/*011e*/ 0x0014061bU,
-/*011f*/ 0x0018061cU,
-/*0120*/ 0x000a061dU,
-/*0121*/ 0x1006061dU,
-/*0122*/ 0x1806061dU,
-/*0123*/ 0x0006061eU,
-/*0124*/ 0xffffffffU,
-/*0125*/ 0xffffffffU,
-/*0126*/ 0x0008061fU,
-/*0127*/ 0x080b061fU,
-/*0128*/ 0x000b0620U,
-/*0129*/ 0x100b0620U,
-/*012a*/ 0x000b0621U,
-/*012b*/ 0x100b0621U,
-/*012c*/ 0x000b0622U,
-/*012d*/ 0x10040622U,
-/*012e*/ 0x000a0623U,
-/*012f*/ 0x10060623U,
-/*0130*/ 0x18080623U,
-/*0131*/ 0xffffffffU,
-/*0132*/ 0x00040624U,
-/*0133*/ 0xffffffffU,
-/*0134*/ 0xffffffffU,
-/*0135*/ 0x00010700U,
-/*0136*/ 0x08020700U,
-/*0137*/ 0x10050700U,
-/*0138*/ 0x18050700U,
-/*0139*/ 0x00050701U,
-/*013a*/ 0x08050701U,
-/*013b*/ 0x100b0701U,
-/*013c*/ 0x00050702U,
-/*013d*/ 0x08010702U,
-/*013e*/ 0x10010702U,
-/*013f*/ 0xffffffffU,
-/*0140*/ 0x18010702U,
-/*0141*/ 0x00010703U,
-/*0142*/ 0x08040703U,
-/*0143*/ 0x100b0703U,
-/*0144*/ 0x000b0704U,
-/*0145*/ 0xffffffffU,
-/*0146*/ 0x10040704U,
-/*0147*/ 0x000b0705U,
-/*0148*/ 0x10040705U,
-/*0149*/ 0x18010705U,
-/*014a*/ 0x00010706U,
-/*014b*/ 0x08010706U,
-/*014c*/ 0x00200707U,
-/*014d*/ 0x00200708U,
-/*014e*/ 0x00080709U,
-/*014f*/ 0x080a0709U,
-/*0150*/ 0x18050709U,
-/*0151*/ 0x000a070aU,
-/*0152*/ 0x1003070aU,
-/*0153*/ 0x1803070aU,
-/*0154*/ 0x0001070bU,
-/*0155*/ 0x0802070bU,
-/*0156*/ 0x1001070bU,
-/*0157*/ 0x1801070bU,
-/*0158*/ 0x0001070cU,
-/*0159*/ 0x0802070cU,
-/*015a*/ 0xffffffffU,
-/*015b*/ 0xffffffffU,
-/*015c*/ 0xffffffffU,
-/*015d*/ 0xffffffffU,
-/*015e*/ 0xffffffffU,
-/*015f*/ 0xffffffffU,
-/*0160*/ 0xffffffffU,
-/*0161*/ 0xffffffffU,
-/*0162*/ 0xffffffffU,
-/*0163*/ 0xffffffffU,
-/*0164*/ 0xffffffffU,
-/*0165*/ 0xffffffffU,
-/*0166*/ 0x1001070cU,
-/*0167*/ 0x1801070cU,
-/*0168*/ 0x000d070dU,
-/*0169*/ 0xffffffffU,
-/*016a*/ 0xffffffffU,
-/*016b*/ 0x0005070eU,
-/*016c*/ 0x0001070fU,
-/*016d*/ 0x080e070fU,
-/*016e*/ 0x000e0710U,
-/*016f*/ 0x100e0710U,
-/*0170*/ 0x000e0711U,
-/*0171*/ 0x100e0711U,
-/*0172*/ 0x00040712U,
-/*0173*/ 0xffffffffU,
-/*0174*/ 0xffffffffU,
-/*0175*/ 0xffffffffU,
-/*0176*/ 0xffffffffU,
-/*0177*/ 0x080b0712U,
-/*0178*/ 0x000b0713U,
-/*0179*/ 0x100b0713U,
-/*017a*/ 0x000b0714U,
-/*017b*/ 0xffffffffU,
-/*017c*/ 0xffffffffU,
-/*017d*/ 0xffffffffU,
-/*017e*/ 0xffffffffU,
-/*017f*/ 0x000d0715U,
-/*0180*/ 0xffffffffU,
-/*0181*/ 0xffffffffU,
-/*0182*/ 0x10100715U,
-/*0183*/ 0x00080716U,
-/*0184*/ 0xffffffffU,
-/*0185*/ 0x08100716U,
-/*0186*/ 0x00100717U,
-/*0187*/ 0x10100717U,
-/*0188*/ 0x00100718U,
-/*0189*/ 0x10100718U,
-/*018a*/ 0x00030719U,
-/*018b*/ 0x08040719U,
-/*018c*/ 0x10010719U,
-/*018d*/ 0x18040719U,
-/*018e*/ 0xffffffffU,
-/*018f*/ 0xffffffffU,
-/*0190*/ 0x0001071aU,
-/*0191*/ 0x0812071aU,
-/*0192*/ 0x000a071bU,
-/*0193*/ 0x100c071bU,
-/*0194*/ 0x0012071cU,
-/*0195*/ 0x0014071dU,
-/*0196*/ 0x0012071eU,
-/*0197*/ 0x0011071fU,
-/*0198*/ 0x00110720U,
-/*0199*/ 0x00120721U,
-/*019a*/ 0x00120722U,
-/*019b*/ 0x00120723U,
-/*019c*/ 0x00120724U,
-/*019d*/ 0x00120725U,
-/*019e*/ 0x00120726U,
-/*019f*/ 0x00120727U,
-/*01a0*/ 0x00120728U,
-/*01a1*/ 0xffffffffU,
-/*01a2*/ 0xffffffffU,
-/*01a3*/ 0x00190729U,
-/*01a4*/ 0x0019072aU,
-/*01a5*/ 0x0020072bU,
-/*01a6*/ 0x0017072cU,
-/*01a7*/ 0x1808072cU,
-/*01a8*/ 0x0001072dU,
-/*01a9*/ 0x0801072dU,
-/*01aa*/ 0x0020072eU,
-/*01ab*/ 0x0008072fU,
-/*01ac*/ 0xffffffffU,
-/*01ad*/ 0x0803072fU,
-/*01ae*/ 0x00180730U,
-/*01af*/ 0x00180731U,
-/*01b0*/ 0xffffffffU,
-/*01b1*/ 0xffffffffU,
-/*01b2*/ 0xffffffffU,
-/*01b3*/ 0xffffffffU,
-/*01b4*/ 0xffffffffU,
-/*01b5*/ 0xffffffffU,
-/*01b6*/ 0xffffffffU,
-/*01b7*/ 0xffffffffU,
-/*01b8*/ 0xffffffffU,
-/*01b9*/ 0xffffffffU,
-/*01ba*/ 0xffffffffU,
-/*01bb*/ 0xffffffffU,
-/*01bc*/ 0xffffffffU,
-/*01bd*/ 0xffffffffU,
-/*01be*/ 0xffffffffU,
-/*01bf*/ 0x00100732U,
-/*01c0*/ 0x10010732U,
-/*01c1*/ 0x18010732U,
-/*01c2*/ 0x00050733U,
-/*01c3*/ 0x00200734U,
-/*01c4*/ 0x00090735U,
-/*01c5*/ 0xffffffffU,
-/*01c6*/ 0xffffffffU,
-/*01c7*/ 0x00200736U,
-/*01c8*/ 0x00040737U,
-/*01c9*/ 0x08100737U,
-/*01ca*/ 0x18060737U,
-/*01cb*/ 0x00100738U,
-/*01cc*/ 0xffffffffU,
-/*01cd*/ 0xffffffffU,
-/*01ce*/ 0xffffffffU,
-/*01cf*/ 0xffffffffU,
-/*01d0*/ 0xffffffffU,
-/*01d1*/ 0xffffffffU,
-/*01d2*/ 0xffffffffU,
-/*01d3*/ 0xffffffffU,
-/*01d4*/ 0x00200739U,
-/*01d5*/ 0x000b073aU,
-/*01d6*/ 0xffffffffU,
-/*01d7*/ 0xffffffffU,
-/*01d8*/ 0xffffffffU,
-/*01d9*/ 0xffffffffU,
-/*01da*/ 0xffffffffU,
-/*01db*/ 0xffffffffU,
-/*01dc*/ 0xffffffffU,
-/*01dd*/ 0xffffffffU,
-/*01de*/ 0x00010200U,
-/*01df*/ 0x08040200U,
-/*01e0*/ 0x10100200U,
-/*01e1*/ 0x00010201U,
-/*01e2*/ 0x08010201U,
-/*01e3*/ 0xffffffffU,
-/*01e4*/ 0xffffffffU,
-/*01e5*/ 0x10100201U,
-/*01e6*/ 0xffffffffU,
-/*01e7*/ 0xffffffffU,
-/*01e8*/ 0xffffffffU,
-/*01e9*/ 0xffffffffU,
-/*01ea*/ 0xffffffffU,
-/*01eb*/ 0xffffffffU,
-/*01ec*/ 0xffffffffU,
-/*01ed*/ 0xffffffffU,
-/*01ee*/ 0xffffffffU,
-/*01ef*/ 0x00200202U,
-/*01f0*/ 0x00100203U,
-/*01f1*/ 0x00200204U,
-/*01f2*/ 0x00100205U,
-/*01f3*/ 0x00200206U,
-/*01f4*/ 0x00100207U,
-/*01f5*/ 0x10100207U,
-/*01f6*/ 0x00200208U,
-/*01f7*/ 0x00200209U,
-/*01f8*/ 0x0020020aU,
-/*01f9*/ 0x0020020bU,
-/*01fa*/ 0x0010020cU,
-/*01fb*/ 0x0020020dU,
-/*01fc*/ 0x0020020eU,
-/*01fd*/ 0x0020020fU,
-/*01fe*/ 0x00200210U,
-/*01ff*/ 0x00100211U,
-/*0200*/ 0x00200212U,
-/*0201*/ 0x00200213U,
-/*0202*/ 0x00200214U,
-/*0203*/ 0x00200215U,
-/*0204*/ 0x00090216U,
-/*0205*/ 0x10010216U,
-/*0206*/ 0x00200217U,
-/*0207*/ 0x00050218U,
-/*0208*/ 0x08010218U,
-/*0209*/ 0x10080218U,
-/*020a*/ 0x18080218U,
-/*020b*/ 0x001c0219U,
-/*020c*/ 0x001c021aU,
-/*020d*/ 0x001c021bU,
-/*020e*/ 0x001c021cU,
-/*020f*/ 0x001c021dU,
-/*0210*/ 0x001c021eU,
-/*0211*/ 0x001c021fU,
-/*0212*/ 0x001c0220U,
-/*0213*/ 0x001c0221U,
-/*0214*/ 0x001c0222U,
-/*0215*/ 0x001c0223U,
-/*0216*/ 0x001c0224U,
-/*0217*/ 0x001c0225U,
-/*0218*/ 0x001c0226U,
-/*0219*/ 0x001c0227U,
-/*021a*/ 0x001c0228U,
-/*021b*/ 0x00010229U,
-/*021c*/ 0x08010229U,
-/*021d*/ 0x10010229U,
-/*021e*/ 0x18040229U,
-/*021f*/ 0x0008022aU,
-/*0220*/ 0x0808022aU,
-/*0221*/ 0x1008022aU,
-/*0222*/ 0x1804022aU,
-/*0223*/ 0x0006022bU,
-/*0224*/ 0xffffffffU,
-/*0225*/ 0x0807022bU,
-/*0226*/ 0x1006022bU,
-/*0227*/ 0xffffffffU,
-/*0228*/ 0x1807022bU,
-/*0229*/ 0x0006022cU,
-/*022a*/ 0xffffffffU,
-/*022b*/ 0x0807022cU,
-/*022c*/ 0x1002022cU,
-/*022d*/ 0x1801022cU,
-/*022e*/ 0xffffffffU,
-/*022f*/ 0x000a022dU,
-/*0230*/ 0x1010022dU,
-/*0231*/ 0x000a022eU,
-/*0232*/ 0x1010022eU,
-/*0233*/ 0x000a022fU,
-/*0234*/ 0x1010022fU,
-/*0235*/ 0xffffffffU,
-/*0236*/ 0x00100230U,
-/*0237*/ 0xffffffffU,
-/*0238*/ 0xffffffffU,
-/*0239*/ 0x10010230U,
-/*023a*/ 0x18010230U,
-/*023b*/ 0x00010231U,
-/*023c*/ 0x08010231U,
-/*023d*/ 0x10010231U,
-/*023e*/ 0x18010231U,
-/*023f*/ 0x00020232U,
-/*0240*/ 0x08020232U,
-/*0241*/ 0x10020232U,
-/*0242*/ 0x18020232U,
-/*0243*/ 0x00020233U,
-/*0244*/ 0x08030233U,
-/*0245*/ 0x10010233U,
-/*0246*/ 0x18010233U,
-/*0247*/ 0x00010234U,
-/*0248*/ 0x08010234U,
-/*0249*/ 0xffffffffU,
-/*024a*/ 0x10020234U,
-/*024b*/ 0x18010234U,
-/*024c*/ 0x00010235U,
-/*024d*/ 0xffffffffU,
-/*024e*/ 0x08020235U,
-/*024f*/ 0x10010235U,
-/*0250*/ 0x18010235U,
-/*0251*/ 0xffffffffU,
-/*0252*/ 0x00020236U,
-/*0253*/ 0x08010236U,
-/*0254*/ 0x10010236U,
-/*0255*/ 0xffffffffU,
-/*0256*/ 0x18020236U,
-/*0257*/ 0x00070237U,
-/*0258*/ 0x08010237U,
-/*0259*/ 0x10010237U,
-/*025a*/ 0x18010237U,
-/*025b*/ 0x00010238U,
-/*025c*/ 0x08010238U,
-/*025d*/ 0x10010238U,
-/*025e*/ 0xffffffffU,
-/*025f*/ 0x18010238U,
-/*0260*/ 0x00040239U,
-/*0261*/ 0x08040239U,
-/*0262*/ 0x10040239U,
-/*0263*/ 0x18010239U,
-/*0264*/ 0x0002023aU,
-/*0265*/ 0x0806023aU,
-/*0266*/ 0x1006023aU,
-/*0267*/ 0xffffffffU,
-/*0268*/ 0xffffffffU,
-/*0269*/ 0xffffffffU,
-/*026a*/ 0x1802023aU,
-/*026b*/ 0x0010023bU,
-/*026c*/ 0x1001023bU,
-/*026d*/ 0x1801023bU,
-/*026e*/ 0xffffffffU,
-/*026f*/ 0x0004023cU,
-/*0270*/ 0x0801023cU,
-/*0271*/ 0x1004023cU,
-/*0272*/ 0x1802023cU,
-/*0273*/ 0x0008023dU,
-/*0274*/ 0xffffffffU,
-/*0275*/ 0xffffffffU,
-/*0276*/ 0xffffffffU,
-/*0277*/ 0x080a023dU,
-/*0278*/ 0x0020023eU,
-/*0279*/ 0x0020023fU,
-/*027a*/ 0x00050240U,
-/*027b*/ 0x08010240U,
-/*027c*/ 0x10050240U,
-/*027d*/ 0x18080240U,
-/*027e*/ 0x00010241U,
-/*027f*/ 0x08080241U,
-/*0280*/ 0x10010241U,
-/*0281*/ 0x18080241U,
-/*0282*/ 0x00010242U,
-/*0283*/ 0x08040242U,
-/*0284*/ 0x10040242U,
-/*0285*/ 0x18040242U,
-/*0286*/ 0x00040243U,
-/*0287*/ 0x08040243U,
-/*0288*/ 0x10040243U,
-/*0289*/ 0x18040243U,
-/*028a*/ 0x00040244U,
-/*028b*/ 0x08040244U,
-/*028c*/ 0x10040244U,
-/*028d*/ 0x18010244U,
-/*028e*/ 0x00040245U,
-/*028f*/ 0x08040245U,
-/*0290*/ 0x10040245U,
-/*0291*/ 0x18040245U,
-/*0292*/ 0x00040246U,
-/*0293*/ 0x08040246U,
-/*0294*/ 0x10060246U,
-/*0295*/ 0x18060246U,
-/*0296*/ 0x00060247U,
-/*0297*/ 0x08060247U,
-/*0298*/ 0x10060247U,
-/*0299*/ 0x18060247U,
-/*029a*/ 0xffffffffU,
-/*029b*/ 0x00010248U,
-/*029c*/ 0x08010248U,
-/*029d*/ 0x10020248U,
-/*029e*/ 0xffffffffU,
-/*029f*/ 0xffffffffU,
-/*02a0*/ 0xffffffffU,
-/*02a1*/ 0xffffffffU,
-/*02a2*/ 0xffffffffU,
-/*02a3*/ 0xffffffffU,
-/*02a4*/ 0xffffffffU,
-/*02a5*/ 0xffffffffU,
-/*02a6*/ 0x18040248U,
-/*02a7*/ 0x00040249U,
-/*02a8*/ 0x08010249U,
-/*02a9*/ 0x10010249U,
-/*02aa*/ 0xffffffffU,
-/*02ab*/ 0x18010249U,
-/*02ac*/ 0x0001024aU,
-/*02ad*/ 0xffffffffU,
-/*02ae*/ 0x0801024aU,
-/*02af*/ 0x1001024aU,
-/*02b0*/ 0x1801024aU,
-/*02b1*/ 0x0004024bU,
-/*02b2*/ 0x0804024bU,
-/*02b3*/ 0x100a024bU,
-/*02b4*/ 0x0020024cU,
-/*02b5*/ 0x0004024dU,
-/*02b6*/ 0x0808024dU,
-/*02b7*/ 0xffffffffU,
-/*02b8*/ 0xffffffffU,
-/*02b9*/ 0xffffffffU,
-/*02ba*/ 0xffffffffU,
-/*02bb*/ 0xffffffffU,
-/*02bc*/ 0xffffffffU,
-/*02bd*/ 0x1002024dU,
-/*02be*/ 0x1802024dU,
-/*02bf*/ 0x0020024eU,
-/*02c0*/ 0x0002024fU,
-/*02c1*/ 0x0810024fU,
-/*02c2*/ 0x00100250U,
-/*02c3*/ 0x10040250U,
-/*02c4*/ 0x18040250U,
-/*02c5*/ 0x00050251U,
-/*02c6*/ 0x08050251U,
-/*02c7*/ 0xffffffffU,
-/*02c8*/ 0xffffffffU,
-/*02c9*/ 0xffffffffU,
-/*02ca*/ 0xffffffffU,
-/*02cb*/ 0x10010251U,
-/*02cc*/ 0x18010251U,
-/*02cd*/ 0x00070252U,
-/*02ce*/ 0x08070252U,
-/*02cf*/ 0x10070252U,
-/*02d0*/ 0x18070252U,
-/*02d1*/ 0x00070253U,
-/*02d2*/ 0x08070253U,
-/*02d3*/ 0x10070253U,
-/*02d4*/ 0x18070253U,
-/*02d5*/ 0x00070254U,
-/*02d6*/ 0x08070254U,
-/*02d7*/ 0x10070254U,
-/*02d8*/ 0xffffffffU,
-/*02d9*/ 0xffffffffU,
-/*02da*/ 0xffffffffU,
-/*02db*/ 0xffffffffU,
-/*02dc*/ 0xffffffffU,
-/*02dd*/ 0xffffffffU,
-/*02de*/ 0x18030254U,
-/*02df*/ 0x00010255U,
-/*02e0*/ 0x08020255U,
-/*02e1*/ 0x10010255U,
-/*02e2*/ 0x18040255U,
-/*02e3*/ 0x00020256U,
-/*02e4*/ 0x08010256U,
-/*02e5*/ 0x10010256U,
-/*02e6*/ 0xffffffffU,
-/*02e7*/ 0x18010256U,
-/*02e8*/ 0x00040257U,
-/*02e9*/ 0x08080257U,
-/*02ea*/ 0x100a0257U,
-/*02eb*/ 0x000a0258U,
-/*02ec*/ 0x100a0258U,
-/*02ed*/ 0x000a0259U,
-/*02ee*/ 0x100a0259U,
-/*02ef*/ 0x000a025aU,
-/*02f0*/ 0x0020025bU,
-/*02f1*/ 0x0020025cU,
-/*02f2*/ 0x0001025dU,
-/*02f3*/ 0xffffffffU,
-/*02f4*/ 0xffffffffU,
-/*02f5*/ 0xffffffffU,
-/*02f6*/ 0x0802025dU,
-/*02f7*/ 0x1002025dU,
-/*02f8*/ 0x0010025eU,
-/*02f9*/ 0x1005025eU,
-/*02fa*/ 0x1806025eU,
-/*02fb*/ 0x0005025fU,
-/*02fc*/ 0x0805025fU,
-/*02fd*/ 0x100e025fU,
-/*02fe*/ 0x00050260U,
-/*02ff*/ 0x080e0260U,
-/*0300*/ 0x18050260U,
-/*0301*/ 0x000e0261U,
-/*0302*/ 0x10050261U,
-/*0303*/ 0x18010261U,
-/*0304*/ 0x00050262U,
-/*0305*/ 0x08050262U,
-/*0306*/ 0x100a0262U,
-/*0307*/ 0x000a0263U,
-/*0308*/ 0x10050263U,
-/*0309*/ 0x18050263U,
-/*030a*/ 0x000a0264U,
-/*030b*/ 0x100a0264U,
-/*030c*/ 0x00050265U,
-/*030d*/ 0x08050265U,
-/*030e*/ 0x100a0265U,
-/*030f*/ 0x000a0266U,
-/*0310*/ 0xffffffffU,
-/*0311*/ 0xffffffffU,
-/*0312*/ 0xffffffffU,
-/*0313*/ 0xffffffffU,
-/*0314*/ 0xffffffffU,
-/*0315*/ 0xffffffffU,
-/*0316*/ 0x10070266U,
-/*0317*/ 0x18070266U,
-/*0318*/ 0x00040267U,
-/*0319*/ 0x08040267U,
-/*031a*/ 0xffffffffU,
-/*031b*/ 0xffffffffU,
-/*031c*/ 0xffffffffU,
-/*031d*/ 0x10040267U,
-/*031e*/ 0x18080267U,
-/*031f*/ 0x00080268U,
-/*0320*/ 0x08040268U,
-/*0321*/ 0xffffffffU,
-/*0322*/ 0xffffffffU,
-/*0323*/ 0xffffffffU,
-/*0324*/ 0x10040268U,
-/*0325*/ 0xffffffffU,
-/*0326*/ 0xffffffffU,
-/*0327*/ 0xffffffffU,
-/*0328*/ 0x18040268U,
-/*0329*/ 0xffffffffU,
-/*032a*/ 0xffffffffU,
-/*032b*/ 0xffffffffU,
-/*032c*/ 0x00040269U,
-/*032d*/ 0x08050269U,
-/*032e*/ 0x10070269U,
-/*032f*/ 0x18080269U,
-/*0330*/ 0x0010026aU,
-/*0331*/ 0x1008026aU,
-/*0332*/ 0x0010026bU,
-/*0333*/ 0x1008026bU,
-/*0334*/ 0x0010026cU,
-/*0335*/ 0x1008026cU,
-/*0336*/ 0x1808026cU,
-/*0337*/ 0x0001026dU,
-/*0338*/ 0x0801026dU,
-/*0339*/ 0x1006026dU,
-/*033a*/ 0x1806026dU,
-/*033b*/ 0x0006026eU,
-/*033c*/ 0xffffffffU,
-/*033d*/ 0x0801026eU,
-/*033e*/ 0x1003026eU,
-/*033f*/ 0xffffffffU,
-/*0340*/ 0xffffffffU,
-/*0341*/ 0xffffffffU,
-/*0342*/ 0x000a026fU,
-/*0343*/ 0x100a026fU,
-/*0344*/ 0x00040270U,
-/*0345*/ 0x08010270U,
-/*0346*/ 0x10040270U,
-/*0347*/ 0xffffffffU,
-/*0348*/ 0xffffffffU,
-/*0349*/ 0xffffffffU,
-/*034a*/ 0xffffffffU,
-/*034b*/ 0xffffffffU,
-/*034c*/ 0xffffffffU,
-/*034d*/ 0x18070270U,
-/*034e*/ 0x00070271U,
-/*034f*/ 0x08050271U,
-/*0350*/ 0x10050271U,
-/*0351*/ 0xffffffffU,
-/*0352*/ 0xffffffffU,
-/*0353*/ 0xffffffffU,
-/*0354*/ 0x18040271U,
-/*0355*/ 0x00010272U,
-/*0356*/ 0x08010272U,
-/*0357*/ 0x10020272U,
-/*0358*/ 0x18080272U,
-/*0359*/ 0x00200273U,
-/*035a*/ 0x00200274U,
-/*035b*/ 0x00100275U,
-/*035c*/ 0xffffffffU,
-/*035d*/ 0xffffffffU,
-/*035e*/ 0xffffffffU,
-/*035f*/ 0x10020275U,
-/*0360*/ 0x18010275U,
-/*0361*/ 0xffffffffU,
-/*0362*/ 0x00020276U,
-/*0363*/ 0x08080276U,
-/*0364*/ 0x10080276U,
-/*0365*/ 0x18080276U,
-/*0366*/ 0x00080277U,
-/*0367*/ 0x08080277U,
-/*0368*/ 0x10080277U,
-/*0369*/ 0xffffffffU,
-/*036a*/ 0x18080277U,
-/*036b*/ 0x00080278U,
-/*036c*/ 0x08080278U,
-/*036d*/ 0x10080278U,
-/*036e*/ 0x18080278U,
-/*036f*/ 0x00080279U,
-/*0370*/ 0xffffffffU,
-/*0371*/ 0x08080279U,
-/*0372*/ 0x10080279U,
-/*0373*/ 0x18080279U,
-/*0374*/ 0x0008027aU,
-/*0375*/ 0x0808027aU,
-/*0376*/ 0x1008027aU,
-/*0377*/ 0xffffffffU,
-/*0378*/ 0x1808027aU,
-/*0379*/ 0x0008027bU,
-/*037a*/ 0x0808027bU,
-/*037b*/ 0x1008027bU,
-/*037c*/ 0x1808027bU,
-/*037d*/ 0x0008027cU,
-/*037e*/ 0x0808027cU,
-/*037f*/ 0xffffffffU,
-/*0380*/ 0x1008027cU,
-/*0381*/ 0x1808027cU,
-/*0382*/ 0x0008027dU,
-/*0383*/ 0x0808027dU,
-/*0384*/ 0x1008027dU,
-/*0385*/ 0x1808027dU,
-/*0386*/ 0xffffffffU,
-/*0387*/ 0x0008027eU,
-/*0388*/ 0x0808027eU,
-/*0389*/ 0x1008027eU,
-/*038a*/ 0x1808027eU,
-/*038b*/ 0x0008027fU,
-/*038c*/ 0x0808027fU,
-/*038d*/ 0xffffffffU,
-/*038e*/ 0x1008027fU,
-/*038f*/ 0x1808027fU,
-/*0390*/ 0x00080280U,
-/*0391*/ 0x08080280U,
-/*0392*/ 0x10080280U,
-/*0393*/ 0x18080280U,
-/*0394*/ 0x00080281U,
-/*0395*/ 0xffffffffU,
-/*0396*/ 0x08080281U,
-/*0397*/ 0x10080281U,
-/*0398*/ 0x18080281U,
-/*0399*/ 0x00080282U,
-/*039a*/ 0x08080282U,
-/*039b*/ 0x10080282U,
-/*039c*/ 0xffffffffU,
-/*039d*/ 0x18080282U,
-/*039e*/ 0x00080283U,
-/*039f*/ 0x08080283U,
-/*03a0*/ 0x10080283U,
-/*03a1*/ 0x18080283U,
-/*03a2*/ 0x00080284U,
-/*03a3*/ 0xffffffffU,
-/*03a4*/ 0x08080284U,
-/*03a5*/ 0x10080284U,
-/*03a6*/ 0x18080284U,
-/*03a7*/ 0x00080285U,
-/*03a8*/ 0x08080285U,
-/*03a9*/ 0x10080285U,
-/*03aa*/ 0x18080285U,
-/*03ab*/ 0xffffffffU,
-/*03ac*/ 0x00080286U,
-/*03ad*/ 0x08080286U,
-/*03ae*/ 0x10080286U,
-/*03af*/ 0x18080286U,
-/*03b0*/ 0x00080287U,
-/*03b1*/ 0x08080287U,
-/*03b2*/ 0xffffffffU,
-/*03b3*/ 0x10080287U,
-/*03b4*/ 0x18080287U,
-/*03b5*/ 0x00080288U,
-/*03b6*/ 0x08080288U,
-/*03b7*/ 0x10080288U,
-/*03b8*/ 0x18080288U,
-/*03b9*/ 0xffffffffU,
-/*03ba*/ 0x00080289U,
-/*03bb*/ 0x08020289U,
-/*03bc*/ 0x10030289U,
-/*03bd*/ 0x000a028aU,
-/*03be*/ 0x100a028aU,
-/*03bf*/ 0x000a028bU,
-/*03c0*/ 0x1005028bU,
-/*03c1*/ 0x1804028bU,
-/*03c2*/ 0x0008028cU,
-/*03c3*/ 0x0808028cU,
-/*03c4*/ 0x1006028cU,
-/*03c5*/ 0x1806028cU,
-/*03c6*/ 0x0011028dU,
-/*03c7*/ 0x1808028dU,
-/*03c8*/ 0x0004028eU,
-/*03c9*/ 0x0806028eU,
-/*03ca*/ 0xffffffffU,
-/*03cb*/ 0x1006028eU,
-/*03cc*/ 0x1808028eU,
-/*03cd*/ 0xffffffffU,
-/*03ce*/ 0x0004028fU,
-/*03cf*/ 0x0808028fU,
-/*03d0*/ 0x1008028fU,
-/*03d1*/ 0x1806028fU,
-/*03d2*/ 0x00060290U,
-/*03d3*/ 0x08110290U,
-/*03d4*/ 0x00080291U,
-/*03d5*/ 0x08040291U,
-/*03d6*/ 0x10060291U,
-/*03d7*/ 0xffffffffU,
-/*03d8*/ 0x18060291U,
-/*03d9*/ 0x00080292U,
-/*03da*/ 0xffffffffU,
-/*03db*/ 0x08040292U,
-/*03dc*/ 0x10080292U,
-/*03dd*/ 0x18080292U,
-/*03de*/ 0x00060293U,
-/*03df*/ 0x08060293U,
-/*03e0*/ 0x00110294U,
-/*03e1*/ 0x18080294U,
-/*03e2*/ 0x00040295U,
-/*03e3*/ 0x08060295U,
-/*03e4*/ 0xffffffffU,
-/*03e5*/ 0x10060295U,
-/*03e6*/ 0x18080295U,
-/*03e7*/ 0xffffffffU,
-/*03e8*/ 0x00040296U,
-/*03e9*/ 0x08040296U,
-/*03ea*/ 0x10040296U,
-/*03eb*/ 0x18040296U,
-/*03ec*/ 0x00040297U,
-/*03ed*/ 0x08040297U,
-/*03ee*/ 0x10040297U,
-/*03ef*/ 0x18040297U,
-/*03f0*/ 0x00040298U,
-/*03f1*/ 0x08040298U,
-/*03f2*/ 0x10040298U,
-/*03f3*/ 0x18040298U,
-/*03f4*/ 0x00040299U,
-/*03f5*/ 0x08040299U,
-/*03f6*/ 0x10040299U,
-/*03f7*/ 0x18040299U,
-/*03f8*/ 0x0004029aU,
-/*03f9*/ 0x0804029aU,
-/*03fa*/ 0x1004029aU,
-/*03fb*/ 0x1804029aU,
-/*03fc*/ 0x0011029bU,
-/*03fd*/ 0x0010029cU,
-/*03fe*/ 0x0011029dU,
-/*03ff*/ 0x0020029eU,
-/*0400*/ 0x0020029fU,
-/*0401*/ 0x002002a0U,
-/*0402*/ 0x002002a1U,
-/*0403*/ 0x002002a2U,
-/*0404*/ 0x002002a3U,
-/*0405*/ 0x002002a4U,
-/*0406*/ 0x002002a5U,
-/*0407*/ 0x002002a6U,
-/*0408*/ 0x000202a7U,
-/*0409*/ 0x080502a7U,
-/*040a*/ 0x100502a7U,
-/*040b*/ 0xffffffffU,
-/*040c*/ 0xffffffffU,
-/*040d*/ 0xffffffffU,
-/*040e*/ 0xffffffffU,
-/*040f*/ 0xffffffffU,
-/*0410*/ 0xffffffffU,
-/*0411*/ 0xffffffffU,
-/*0412*/ 0xffffffffU,
-/*0413*/ 0xffffffffU,
-/*0414*/ 0xffffffffU,
-/*0415*/ 0xffffffffU,
-/*0416*/ 0xffffffffU,
-/*0417*/ 0xffffffffU,
-/*0418*/ 0xffffffffU,
-/*0419*/ 0xffffffffU,
-/*041a*/ 0xffffffffU,
-/*041b*/ 0xffffffffU,
-/*041c*/ 0xffffffffU,
-/*041d*/ 0xffffffffU,
-/*041e*/ 0xffffffffU,
-/*041f*/ 0xffffffffU,
-/*0420*/ 0xffffffffU,
-/*0421*/ 0xffffffffU,
-/*0422*/ 0xffffffffU,
-/*0423*/ 0xffffffffU,
-/*0424*/ 0xffffffffU,
-/*0425*/ 0xffffffffU,
-/*0426*/ 0xffffffffU,
-/*0427*/ 0x180102a7U,
-/*0428*/ 0x000402a8U,
-/*0429*/ 0x081002a8U,
-/*042a*/ 0x002002a9U,
-/*042b*/ 0x001002aaU,
-/*042c*/ 0x002002abU,
-/*042d*/ 0x001002acU,
-/*042e*/ 0x002002adU,
-/*042f*/ 0x000702aeU,
-/*0430*/ 0x080102aeU,
-/*0431*/ 0x100202aeU,
-/*0432*/ 0x180602aeU,
-/*0433*/ 0x000102afU,
-/*0434*/ 0x080102afU,
-/*0435*/ 0x002002b0U,
-/*0436*/ 0x000202b1U,
-/*0437*/ 0x002002b2U,
-/*0438*/ 0x002002b3U,
-/*0439*/ 0xffffffffU,
-/*043a*/ 0xffffffffU,
-/*043b*/ 0xffffffffU,
-/*043c*/ 0xffffffffU,
-/*043d*/ 0xffffffffU,
-/*043e*/ 0xffffffffU,
-/*043f*/ 0xffffffffU,
-/*0440*/ 0xffffffffU,
-/*0441*/ 0xffffffffU,
-/*0442*/ 0xffffffffU,
-/*0443*/ 0xffffffffU,
-/*0444*/ 0xffffffffU,
-/*0445*/ 0xffffffffU,
-/*0446*/ 0xffffffffU,
-/*0447*/ 0xffffffffU,
-/*0448*/ 0xffffffffU,
-/*0449*/ 0xffffffffU,
-/*044a*/ 0xffffffffU,
-/*044b*/ 0xffffffffU,
-/*044c*/ 0xffffffffU,
-/*044d*/ 0xffffffffU,
-/*044e*/ 0xffffffffU,
-/*044f*/ 0xffffffffU,
-/*0450*/ 0xffffffffU,
-/*0451*/ 0xffffffffU,
-/*0452*/ 0xffffffffU,
-/*0453*/ 0xffffffffU,
-/*0454*/ 0xffffffffU,
-/*0455*/ 0xffffffffU,
-/*0456*/ 0xffffffffU,
-/*0457*/ 0xffffffffU,
-/*0458*/ 0xffffffffU,
-/*0459*/ 0xffffffffU,
-/*045a*/ 0xffffffffU,
-/*045b*/ 0xffffffffU,
-/*045c*/ 0xffffffffU,
-/*045d*/ 0xffffffffU,
-/*045e*/ 0xffffffffU,
-/*045f*/ 0x000402b4U,
-/*0460*/ 0xffffffffU,
-/*0461*/ 0xffffffffU,
-/*0462*/ 0xffffffffU,
-/*0463*/ 0xffffffffU,
-/*0464*/ 0xffffffffU,
-/*0465*/ 0xffffffffU,
-/*0466*/ 0xffffffffU,
-/*0467*/ 0xffffffffU,
-/*0468*/ 0xffffffffU,
-/*0469*/ 0xffffffffU,
-/*046a*/ 0xffffffffU,
-/*046b*/ 0xffffffffU,
-/*046c*/ 0xffffffffU,
-/*046d*/ 0xffffffffU,
-/*046e*/ 0xffffffffU,
-/*046f*/ 0xffffffffU,
-/*0470*/ 0xffffffffU,
-/*0471*/ 0xffffffffU,
-/*0472*/ 0xffffffffU,
-/*0473*/ 0xffffffffU,
-/*0474*/ 0xffffffffU,
-/*0475*/ 0xffffffffU,
-/*0476*/ 0xffffffffU,
-/*0477*/ 0xffffffffU,
-/*0478*/ 0xffffffffU,
-/*0479*/ 0xffffffffU,
-/*047a*/ 0xffffffffU,
-/*047b*/ 0xffffffffU,
-/*047c*/ 0xffffffffU,
-/*047d*/ 0xffffffffU,
-/*047e*/ 0xffffffffU,
-/*047f*/ 0xffffffffU,
-/*0480*/ 0xffffffffU,
-/*0481*/ 0xffffffffU,
-/*0482*/ 0xffffffffU,
-/*0483*/ 0xffffffffU,
-/*0484*/ 0xffffffffU,
-/*0485*/ 0xffffffffU,
-/*0486*/ 0xffffffffU,
-/*0487*/ 0xffffffffU,
-/*0488*/ 0xffffffffU,
-/*0489*/ 0xffffffffU,
-/*048a*/ 0xffffffffU,
-/*048b*/ 0xffffffffU,
-/*048c*/ 0xffffffffU,
-/*048d*/ 0xffffffffU,
-/*048e*/ 0xffffffffU,
-/*048f*/ 0xffffffffU,
-/*0490*/ 0xffffffffU,
-/*0491*/ 0xffffffffU,
-/*0492*/ 0xffffffffU,
-/*0493*/ 0xffffffffU,
-/*0494*/ 0xffffffffU,
- },
- {
-/*0000*/ 0x00200800U,
-/*0001*/ 0x00040801U,
-/*0002*/ 0x080b0801U,
-/*0003*/ 0xffffffffU,
-/*0004*/ 0xffffffffU,
-/*0005*/ 0x18010801U,
-/*0006*/ 0x00050802U,
-/*0007*/ 0x08050802U,
-/*0008*/ 0x10050802U,
-/*0009*/ 0x18050802U,
-/*000a*/ 0x00050803U,
-/*000b*/ 0x08050803U,
-/*000c*/ 0x10050803U,
-/*000d*/ 0x18050803U,
-/*000e*/ 0x00050804U,
-/*000f*/ 0x08040804U,
-/*0010*/ 0x10030804U,
-/*0011*/ 0x00180805U,
-/*0012*/ 0x18030805U,
-/*0013*/ 0x00180806U,
-/*0014*/ 0x18020806U,
-/*0015*/ 0x00010807U,
-/*0016*/ 0x08020807U,
-/*0017*/ 0x10010807U,
-/*0018*/ 0x18010807U,
-/*0019*/ 0x00020808U,
-/*001a*/ 0x08040808U,
-/*001b*/ 0x10040808U,
-/*001c*/ 0x18040808U,
-/*001d*/ 0x000a0809U,
-/*001e*/ 0x10040809U,
-/*001f*/ 0xffffffffU,
-/*0020*/ 0xffffffffU,
-/*0021*/ 0x18070809U,
-/*0022*/ 0xffffffffU,
-/*0023*/ 0xffffffffU,
-/*0024*/ 0xffffffffU,
-/*0025*/ 0xffffffffU,
-/*0026*/ 0xffffffffU,
-/*0027*/ 0xffffffffU,
-/*0028*/ 0x000a080aU,
-/*0029*/ 0x1005080aU,
-/*002a*/ 0x1801080aU,
-/*002b*/ 0x0001080bU,
-/*002c*/ 0x0802080bU,
-/*002d*/ 0x1009080bU,
-/*002e*/ 0x0009080cU,
-/*002f*/ 0x1002080cU,
-/*0030*/ 0x0020080dU,
-/*0031*/ 0xffffffffU,
-/*0032*/ 0x0001080eU,
-/*0033*/ 0xffffffffU,
-/*0034*/ 0xffffffffU,
-/*0035*/ 0xffffffffU,
-/*0036*/ 0xffffffffU,
-/*0037*/ 0x0020080fU,
-/*0038*/ 0x00200810U,
-/*0039*/ 0x00200811U,
-/*003a*/ 0x00200812U,
-/*003b*/ 0x00030813U,
-/*003c*/ 0x08010813U,
-/*003d*/ 0x10030813U,
-/*003e*/ 0x18030813U,
-/*003f*/ 0x00040814U,
-/*0040*/ 0x08040814U,
-/*0041*/ 0x10040814U,
-/*0042*/ 0x18040814U,
-/*0043*/ 0x00010815U,
-/*0044*/ 0x08010815U,
-/*0045*/ 0x10060815U,
-/*0046*/ 0x18040815U,
-/*0047*/ 0xffffffffU,
-/*0048*/ 0x00060816U,
-/*0049*/ 0x08040816U,
-/*004a*/ 0x10060816U,
-/*004b*/ 0x18040816U,
-/*004c*/ 0x00020817U,
-/*004d*/ 0x08050817U,
-/*004e*/ 0x10080817U,
-/*004f*/ 0x00200818U,
-/*0050*/ 0x00060819U,
-/*0051*/ 0x08030819U,
-/*0052*/ 0x100b0819U,
-/*0053*/ 0x0004081aU,
-/*0054*/ 0x0804081aU,
-/*0055*/ 0x1004081aU,
-/*0056*/ 0xffffffffU,
-/*0057*/ 0x1801081aU,
-/*0058*/ 0x0009081bU,
-/*0059*/ 0x0020081cU,
-/*005a*/ 0x0020081dU,
-/*005b*/ 0x0020081eU,
-/*005c*/ 0x0020081fU,
-/*005d*/ 0x00100820U,
-/*005e*/ 0xffffffffU,
-/*005f*/ 0x10010820U,
-/*0060*/ 0x18060820U,
-/*0061*/ 0x00080821U,
-/*0062*/ 0x00200822U,
-/*0063*/ 0xffffffffU,
-/*0064*/ 0x000a0823U,
-/*0065*/ 0x10060823U,
-/*0066*/ 0x18070823U,
-/*0067*/ 0x00080824U,
-/*0068*/ 0x08080824U,
-/*0069*/ 0x100a0824U,
-/*006a*/ 0x00070825U,
-/*006b*/ 0x08080825U,
-/*006c*/ 0x10080825U,
-/*006d*/ 0x18030825U,
-/*006e*/ 0x000a0826U,
-/*006f*/ 0x100a0826U,
-/*0070*/ 0x00110827U,
-/*0071*/ 0x00090828U,
-/*0072*/ 0x10090828U,
-/*0073*/ 0x00100829U,
-/*0074*/ 0x100e0829U,
-/*0075*/ 0x000e082aU,
-/*0076*/ 0x100c082aU,
-/*0077*/ 0x000a082bU,
-/*0078*/ 0x100a082bU,
-/*0079*/ 0x0002082cU,
-/*007a*/ 0x0020082dU,
-/*007b*/ 0x000b082eU,
-/*007c*/ 0x100b082eU,
-/*007d*/ 0x0020082fU,
-/*007e*/ 0x00120830U,
-/*007f*/ 0x00200831U,
-/*0080*/ 0x00200832U,
-/*0081*/ 0xffffffffU,
-/*0082*/ 0xffffffffU,
-/*0083*/ 0x00010833U,
-/*0084*/ 0x08010833U,
-/*0085*/ 0x10080833U,
-/*0086*/ 0x000c0834U,
-/*0087*/ 0x100c0834U,
-/*0088*/ 0x000c0835U,
-/*0089*/ 0x100c0835U,
-/*008a*/ 0x000c0836U,
-/*008b*/ 0x100c0836U,
-/*008c*/ 0x000c0837U,
-/*008d*/ 0x100c0837U,
-/*008e*/ 0x000c0838U,
-/*008f*/ 0x100c0838U,
-/*0090*/ 0x000c0839U,
-/*0091*/ 0x100b0839U,
-/*0092*/ 0xffffffffU,
-/*0093*/ 0xffffffffU,
-/*0094*/ 0x000b083aU,
-/*0095*/ 0x100b083aU,
-/*0096*/ 0x000b083bU,
-/*0097*/ 0x100b083bU,
-/*0098*/ 0x000b083cU,
-/*0099*/ 0x100b083cU,
-/*009a*/ 0x000b083dU,
-/*009b*/ 0x100b083dU,
-/*009c*/ 0x000b083eU,
-/*009d*/ 0x100a083eU,
-/*009e*/ 0xffffffffU,
-/*009f*/ 0x000a083fU,
-/*00a0*/ 0x100a083fU,
-/*00a1*/ 0x000a0840U,
-/*00a2*/ 0x100a0840U,
-/*00a3*/ 0x000a0841U,
-/*00a4*/ 0x100a0841U,
-/*00a5*/ 0x000a0842U,
-/*00a6*/ 0x100a0842U,
-/*00a7*/ 0x000a0843U,
-/*00a8*/ 0x100a0843U,
-/*00a9*/ 0x000a0844U,
-/*00aa*/ 0x100a0844U,
-/*00ab*/ 0x000a0845U,
-/*00ac*/ 0x100a0845U,
-/*00ad*/ 0x000a0846U,
-/*00ae*/ 0x100a0846U,
-/*00af*/ 0x000a0847U,
-/*00b0*/ 0x100a0847U,
-/*00b1*/ 0x000a0848U,
-/*00b2*/ 0x100a0848U,
-/*00b3*/ 0x000a0849U,
-/*00b4*/ 0x100a0849U,
-/*00b5*/ 0x000a084aU,
-/*00b6*/ 0x100a084aU,
-/*00b7*/ 0x000a084bU,
-/*00b8*/ 0x100a084bU,
-/*00b9*/ 0x000a084cU,
-/*00ba*/ 0x100a084cU,
-/*00bb*/ 0x0004084dU,
-/*00bc*/ 0x0803084dU,
-/*00bd*/ 0x100a084dU,
-/*00be*/ 0x000a084eU,
-/*00bf*/ 0x1001084eU,
-/*00c0*/ 0x000a084fU,
-/*00c1*/ 0x1004084fU,
-/*00c2*/ 0x000b0850U,
-/*00c3*/ 0x100a0850U,
-/*00c4*/ 0xffffffffU,
-/*00c5*/ 0x00080851U,
-/*00c6*/ 0x08080851U,
-/*00c7*/ 0x10080851U,
-/*00c8*/ 0x18080851U,
-/*00c9*/ 0x00080852U,
-/*00ca*/ 0xffffffffU,
-/*00cb*/ 0x08080852U,
-/*00cc*/ 0x10010852U,
-/*00cd*/ 0x18080852U,
-/*00ce*/ 0x00080853U,
-/*00cf*/ 0x08020853U,
-/*00d0*/ 0x10020853U,
-/*00d1*/ 0x18040853U,
-/*00d2*/ 0x00040854U,
-/*00d3*/ 0xffffffffU,
-/*00d4*/ 0x08040854U,
-/*00d5*/ 0x100a0854U,
-/*00d6*/ 0x00060855U,
-/*00d7*/ 0x08080855U,
-/*00d8*/ 0xffffffffU,
-/*00d9*/ 0x10040855U,
-/*00da*/ 0x18040855U,
-/*00db*/ 0x00050856U,
-/*00dc*/ 0x08040856U,
-/*00dd*/ 0x10050856U,
-/*00de*/ 0x000a0857U,
-/*00df*/ 0x100a0857U,
-/*00e0*/ 0x00080858U,
-/*00e1*/ 0xffffffffU,
-/*00e2*/ 0x08040858U,
-/*00e3*/ 0xffffffffU,
-/*00e4*/ 0xffffffffU,
-/*00e5*/ 0x00050a00U,
-/*00e6*/ 0x08050a00U,
-/*00e7*/ 0x10050a00U,
-/*00e8*/ 0x18050a00U,
-/*00e9*/ 0x00050a01U,
-/*00ea*/ 0x08050a01U,
-/*00eb*/ 0x100b0a01U,
-/*00ec*/ 0x00010a02U,
-/*00ed*/ 0x08030a02U,
-/*00ee*/ 0x00200a03U,
-/*00ef*/ 0xffffffffU,
-/*00f0*/ 0x00030a04U,
-/*00f1*/ 0x080a0a04U,
-/*00f2*/ 0xffffffffU,
-/*00f3*/ 0xffffffffU,
-/*00f4*/ 0x18030a04U,
-/*00f5*/ 0x00030a05U,
-/*00f6*/ 0x08010a05U,
-/*00f7*/ 0x10010a05U,
-/*00f8*/ 0x18060a05U,
-/*00f9*/ 0xffffffffU,
-/*00fa*/ 0xffffffffU,
-/*00fb*/ 0xffffffffU,
-/*00fc*/ 0x00020a06U,
-/*00fd*/ 0x08030a06U,
-/*00fe*/ 0x10010a06U,
-/*00ff*/ 0x000f0a07U,
-/*0100*/ 0x00200a08U,
-/*0101*/ 0x00200a09U,
-/*0102*/ 0x000b0a0aU,
-/*0103*/ 0x100b0a0aU,
-/*0104*/ 0x000b0a0bU,
-/*0105*/ 0xffffffffU,
-/*0106*/ 0xffffffffU,
-/*0107*/ 0x00180a0cU,
-/*0108*/ 0x00180a0dU,
-/*0109*/ 0x00180a0eU,
-/*010a*/ 0x00180a0fU,
-/*010b*/ 0x18040a0fU,
-/*010c*/ 0x00020a10U,
-/*010d*/ 0x08020a10U,
-/*010e*/ 0x10040a10U,
-/*010f*/ 0x18040a10U,
-/*0110*/ 0x00010a11U,
-/*0111*/ 0x08010a11U,
-/*0112*/ 0x10010a11U,
-/*0113*/ 0x18030a11U,
-/*0114*/ 0x00200a12U,
-/*0115*/ 0x00200a13U,
-/*0116*/ 0xffffffffU,
-/*0117*/ 0x00140a14U,
-/*0118*/ 0x00140a15U,
-/*0119*/ 0x00140a16U,
-/*011a*/ 0x00140a17U,
-/*011b*/ 0x00140a18U,
-/*011c*/ 0x00140a19U,
-/*011d*/ 0x00140a1aU,
-/*011e*/ 0x00140a1bU,
-/*011f*/ 0x001e0a1cU,
-/*0120*/ 0x000a0a1dU,
-/*0121*/ 0x10060a1dU,
-/*0122*/ 0x18060a1dU,
-/*0123*/ 0x00060a1eU,
-/*0124*/ 0xffffffffU,
-/*0125*/ 0x08060a1eU,
-/*0126*/ 0x00080a1fU,
-/*0127*/ 0x080b0a1fU,
-/*0128*/ 0x000b0a20U,
-/*0129*/ 0x100b0a20U,
-/*012a*/ 0x000b0a21U,
-/*012b*/ 0x100b0a21U,
-/*012c*/ 0x000b0a22U,
-/*012d*/ 0x10040a22U,
-/*012e*/ 0x000a0a23U,
-/*012f*/ 0x10060a23U,
-/*0130*/ 0x18080a23U,
-/*0131*/ 0xffffffffU,
-/*0132*/ 0x00040a24U,
-/*0133*/ 0xffffffffU,
-/*0134*/ 0xffffffffU,
-/*0135*/ 0x00010b80U,
-/*0136*/ 0x08020b80U,
-/*0137*/ 0x10050b80U,
-/*0138*/ 0x18050b80U,
-/*0139*/ 0x00050b81U,
-/*013a*/ 0x08050b81U,
-/*013b*/ 0x100b0b81U,
-/*013c*/ 0x00050b82U,
-/*013d*/ 0x08010b82U,
-/*013e*/ 0x10010b82U,
-/*013f*/ 0xffffffffU,
-/*0140*/ 0x18010b82U,
-/*0141*/ 0x00010b83U,
-/*0142*/ 0x08040b83U,
-/*0143*/ 0x100b0b83U,
-/*0144*/ 0x000b0b84U,
-/*0145*/ 0xffffffffU,
-/*0146*/ 0x10040b84U,
-/*0147*/ 0x000b0b85U,
-/*0148*/ 0x10040b85U,
-/*0149*/ 0x18010b85U,
-/*014a*/ 0x00010b86U,
-/*014b*/ 0x08010b86U,
-/*014c*/ 0x00200b87U,
-/*014d*/ 0x00200b88U,
-/*014e*/ 0x00080b89U,
-/*014f*/ 0x080a0b89U,
-/*0150*/ 0x18050b89U,
-/*0151*/ 0x000a0b8aU,
-/*0152*/ 0x10030b8aU,
-/*0153*/ 0x18030b8aU,
-/*0154*/ 0x00010b8bU,
-/*0155*/ 0x08020b8bU,
-/*0156*/ 0x10010b8bU,
-/*0157*/ 0x18010b8bU,
-/*0158*/ 0x00010b8cU,
-/*0159*/ 0x08030b8cU,
-/*015a*/ 0xffffffffU,
-/*015b*/ 0x10040b8cU,
-/*015c*/ 0x18040b8cU,
-/*015d*/ 0x00040b8dU,
-/*015e*/ 0x08040b8dU,
-/*015f*/ 0xffffffffU,
-/*0160*/ 0xffffffffU,
-/*0161*/ 0xffffffffU,
-/*0162*/ 0xffffffffU,
-/*0163*/ 0xffffffffU,
-/*0164*/ 0xffffffffU,
-/*0165*/ 0xffffffffU,
-/*0166*/ 0xffffffffU,
-/*0167*/ 0xffffffffU,
-/*0168*/ 0x000d0b8eU,
-/*0169*/ 0x100d0b8eU,
-/*016a*/ 0x000d0b8fU,
-/*016b*/ 0x00050b90U,
-/*016c*/ 0x00010b91U,
-/*016d*/ 0x080e0b91U,
-/*016e*/ 0x000e0b92U,
-/*016f*/ 0x100e0b92U,
-/*0170*/ 0x000e0b93U,
-/*0171*/ 0x100e0b93U,
-/*0172*/ 0x00040b94U,
-/*0173*/ 0x08040b94U,
-/*0174*/ 0x10040b94U,
-/*0175*/ 0x18040b94U,
-/*0176*/ 0x00040b95U,
-/*0177*/ 0x080b0b95U,
-/*0178*/ 0x000b0b96U,
-/*0179*/ 0x100b0b96U,
-/*017a*/ 0x000b0b97U,
-/*017b*/ 0xffffffffU,
-/*017c*/ 0xffffffffU,
-/*017d*/ 0xffffffffU,
-/*017e*/ 0xffffffffU,
-/*017f*/ 0x000d0b98U,
-/*0180*/ 0x100d0b98U,
-/*0181*/ 0x000d0b99U,
-/*0182*/ 0x10100b99U,
-/*0183*/ 0x10080b8dU,
-/*0184*/ 0x18080b8dU,
-/*0185*/ 0x00100b9aU,
-/*0186*/ 0x10100b9aU,
-/*0187*/ 0x00100b9bU,
-/*0188*/ 0x10100b9bU,
-/*0189*/ 0x00100b9cU,
-/*018a*/ 0x10030b9cU,
-/*018b*/ 0x18040b9cU,
-/*018c*/ 0x00010b9dU,
-/*018d*/ 0x08040b9dU,
-/*018e*/ 0xffffffffU,
-/*018f*/ 0xffffffffU,
-/*0190*/ 0x10010b9dU,
-/*0191*/ 0x00140b9eU,
-/*0192*/ 0x000a0b9fU,
-/*0193*/ 0x100c0b9fU,
-/*0194*/ 0x00120ba0U,
-/*0195*/ 0x00140ba1U,
-/*0196*/ 0x00120ba2U,
-/*0197*/ 0x00110ba3U,
-/*0198*/ 0x00110ba4U,
-/*0199*/ 0x00120ba5U,
-/*019a*/ 0x00120ba6U,
-/*019b*/ 0x00120ba7U,
-/*019c*/ 0x00120ba8U,
-/*019d*/ 0x00120ba9U,
-/*019e*/ 0x00120baaU,
-/*019f*/ 0x00120babU,
-/*01a0*/ 0x00120bacU,
-/*01a1*/ 0xffffffffU,
-/*01a2*/ 0xffffffffU,
-/*01a3*/ 0x00190badU,
-/*01a4*/ 0x00190baeU,
-/*01a5*/ 0x00200bafU,
-/*01a6*/ 0x00170bb0U,
-/*01a7*/ 0x18080bb0U,
-/*01a8*/ 0x00010bb1U,
-/*01a9*/ 0x08010bb1U,
-/*01aa*/ 0x00200bb2U,
-/*01ab*/ 0x00080bb3U,
-/*01ac*/ 0xffffffffU,
-/*01ad*/ 0x08030bb3U,
-/*01ae*/ 0x00180bb4U,
-/*01af*/ 0x00180bb5U,
-/*01b0*/ 0xffffffffU,
-/*01b1*/ 0xffffffffU,
-/*01b2*/ 0xffffffffU,
-/*01b3*/ 0xffffffffU,
-/*01b4*/ 0xffffffffU,
-/*01b5*/ 0xffffffffU,
-/*01b6*/ 0xffffffffU,
-/*01b7*/ 0xffffffffU,
-/*01b8*/ 0xffffffffU,
-/*01b9*/ 0xffffffffU,
-/*01ba*/ 0xffffffffU,
-/*01bb*/ 0xffffffffU,
-/*01bc*/ 0xffffffffU,
-/*01bd*/ 0xffffffffU,
-/*01be*/ 0xffffffffU,
-/*01bf*/ 0x00100bb6U,
-/*01c0*/ 0x10010bb6U,
-/*01c1*/ 0x18010bb6U,
-/*01c2*/ 0x00050bb7U,
-/*01c3*/ 0x00200bb8U,
-/*01c4*/ 0x00090bb9U,
-/*01c5*/ 0xffffffffU,
-/*01c6*/ 0xffffffffU,
-/*01c7*/ 0x00200bbaU,
-/*01c8*/ 0x00040bbbU,
-/*01c9*/ 0x08100bbbU,
-/*01ca*/ 0x18060bbbU,
-/*01cb*/ 0x00100bbcU,
-/*01cc*/ 0xffffffffU,
-/*01cd*/ 0x10080bbcU,
-/*01ce*/ 0xffffffffU,
-/*01cf*/ 0xffffffffU,
-/*01d0*/ 0xffffffffU,
-/*01d1*/ 0x18030bbcU,
-/*01d2*/ 0x00020bbdU,
-/*01d3*/ 0xffffffffU,
-/*01d4*/ 0x00200bbeU,
-/*01d5*/ 0x000b0bbfU,
-/*01d6*/ 0xffffffffU,
-/*01d7*/ 0xffffffffU,
-/*01d8*/ 0xffffffffU,
-/*01d9*/ 0x10020bbfU,
-/*01da*/ 0xffffffffU,
-/*01db*/ 0xffffffffU,
-/*01dc*/ 0xffffffffU,
-/*01dd*/ 0xffffffffU,
-/*01de*/ 0x00010200U,
-/*01df*/ 0x08040200U,
-/*01e0*/ 0x10100200U,
-/*01e1*/ 0x00010201U,
-/*01e2*/ 0x08010201U,
-/*01e3*/ 0xffffffffU,
-/*01e4*/ 0xffffffffU,
-/*01e5*/ 0x10100201U,
-/*01e6*/ 0xffffffffU,
-/*01e7*/ 0xffffffffU,
-/*01e8*/ 0xffffffffU,
-/*01e9*/ 0xffffffffU,
-/*01ea*/ 0xffffffffU,
-/*01eb*/ 0xffffffffU,
-/*01ec*/ 0xffffffffU,
-/*01ed*/ 0xffffffffU,
-/*01ee*/ 0xffffffffU,
-/*01ef*/ 0x00200202U,
-/*01f0*/ 0x00100203U,
-/*01f1*/ 0x00200204U,
-/*01f2*/ 0x00100205U,
-/*01f3*/ 0x00200206U,
-/*01f4*/ 0x00100207U,
-/*01f5*/ 0x10100207U,
-/*01f6*/ 0x00200208U,
-/*01f7*/ 0x00200209U,
-/*01f8*/ 0x0020020aU,
-/*01f9*/ 0x0020020bU,
-/*01fa*/ 0x0010020cU,
-/*01fb*/ 0x0020020dU,
-/*01fc*/ 0x0020020eU,
-/*01fd*/ 0x0020020fU,
-/*01fe*/ 0x00200210U,
-/*01ff*/ 0x00100211U,
-/*0200*/ 0x00200212U,
-/*0201*/ 0x00200213U,
-/*0202*/ 0x00200214U,
-/*0203*/ 0x00200215U,
-/*0204*/ 0x00090216U,
-/*0205*/ 0x10010216U,
-/*0206*/ 0x00200217U,
-/*0207*/ 0x00050218U,
-/*0208*/ 0x08010218U,
-/*0209*/ 0x10080218U,
-/*020a*/ 0x18080218U,
-/*020b*/ 0x001e0219U,
-/*020c*/ 0x001e021aU,
-/*020d*/ 0x001e021bU,
-/*020e*/ 0x001e021cU,
-/*020f*/ 0x001e021dU,
-/*0210*/ 0x001e021eU,
-/*0211*/ 0x001e021fU,
-/*0212*/ 0x001e0220U,
-/*0213*/ 0x001e0221U,
-/*0214*/ 0x001e0222U,
-/*0215*/ 0x001e0223U,
-/*0216*/ 0x001e0224U,
-/*0217*/ 0x001e0225U,
-/*0218*/ 0x001e0226U,
-/*0219*/ 0x001e0227U,
-/*021a*/ 0x001e0228U,
-/*021b*/ 0x00010229U,
-/*021c*/ 0x08010229U,
-/*021d*/ 0x10010229U,
-/*021e*/ 0x18040229U,
-/*021f*/ 0x0008022aU,
-/*0220*/ 0x0808022aU,
-/*0221*/ 0x1008022aU,
-/*0222*/ 0x1804022aU,
-/*0223*/ 0x0005022bU,
-/*0224*/ 0x0806022bU,
-/*0225*/ 0x1007022bU,
-/*0226*/ 0x1805022bU,
-/*0227*/ 0x0006022cU,
-/*0228*/ 0x0807022cU,
-/*0229*/ 0x1005022cU,
-/*022a*/ 0x1806022cU,
-/*022b*/ 0x0007022dU,
-/*022c*/ 0x0802022dU,
-/*022d*/ 0x1001022dU,
-/*022e*/ 0xffffffffU,
-/*022f*/ 0x000a022eU,
-/*0230*/ 0x1010022eU,
-/*0231*/ 0x000a022fU,
-/*0232*/ 0x1010022fU,
-/*0233*/ 0x000a0230U,
-/*0234*/ 0x10100230U,
-/*0235*/ 0xffffffffU,
-/*0236*/ 0x00100231U,
-/*0237*/ 0xffffffffU,
-/*0238*/ 0xffffffffU,
-/*0239*/ 0x10010231U,
-/*023a*/ 0x18010231U,
-/*023b*/ 0x00010232U,
-/*023c*/ 0x08010232U,
-/*023d*/ 0x10010232U,
-/*023e*/ 0x18010232U,
-/*023f*/ 0x00020233U,
-/*0240*/ 0x08020233U,
-/*0241*/ 0x10020233U,
-/*0242*/ 0x18020233U,
-/*0243*/ 0x00020234U,
-/*0244*/ 0x08030234U,
-/*0245*/ 0x10010234U,
-/*0246*/ 0x18010234U,
-/*0247*/ 0x00010235U,
-/*0248*/ 0x08010235U,
-/*0249*/ 0xffffffffU,
-/*024a*/ 0x10020235U,
-/*024b*/ 0x18010235U,
-/*024c*/ 0x00010236U,
-/*024d*/ 0xffffffffU,
-/*024e*/ 0x08020236U,
-/*024f*/ 0x10010236U,
-/*0250*/ 0x18010236U,
-/*0251*/ 0xffffffffU,
-/*0252*/ 0x00020237U,
-/*0253*/ 0x08010237U,
-/*0254*/ 0x10010237U,
-/*0255*/ 0xffffffffU,
-/*0256*/ 0x18020237U,
-/*0257*/ 0x00070238U,
-/*0258*/ 0x08010238U,
-/*0259*/ 0x10010238U,
-/*025a*/ 0x18010238U,
-/*025b*/ 0x00010239U,
-/*025c*/ 0x08010239U,
-/*025d*/ 0x10010239U,
-/*025e*/ 0xffffffffU,
-/*025f*/ 0x18010239U,
-/*0260*/ 0x0004023aU,
-/*0261*/ 0x0804023aU,
-/*0262*/ 0x1004023aU,
-/*0263*/ 0x1801023aU,
-/*0264*/ 0x0002023bU,
-/*0265*/ 0x0806023bU,
-/*0266*/ 0x1006023bU,
-/*0267*/ 0xffffffffU,
-/*0268*/ 0xffffffffU,
-/*0269*/ 0xffffffffU,
-/*026a*/ 0x1802023bU,
-/*026b*/ 0x0010023cU,
-/*026c*/ 0x1001023cU,
-/*026d*/ 0x1801023cU,
-/*026e*/ 0xffffffffU,
-/*026f*/ 0x0004023dU,
-/*0270*/ 0x0801023dU,
-/*0271*/ 0x1004023dU,
-/*0272*/ 0x1802023dU,
-/*0273*/ 0x0008023eU,
-/*0274*/ 0xffffffffU,
-/*0275*/ 0xffffffffU,
-/*0276*/ 0xffffffffU,
-/*0277*/ 0x080a023eU,
-/*0278*/ 0x0020023fU,
-/*0279*/ 0x00200240U,
-/*027a*/ 0x00050241U,
-/*027b*/ 0x08010241U,
-/*027c*/ 0x10050241U,
-/*027d*/ 0x18080241U,
-/*027e*/ 0x00010242U,
-/*027f*/ 0x08080242U,
-/*0280*/ 0x10010242U,
-/*0281*/ 0x18080242U,
-/*0282*/ 0x00010243U,
-/*0283*/ 0x08040243U,
-/*0284*/ 0x10040243U,
-/*0285*/ 0x18040243U,
-/*0286*/ 0x00040244U,
-/*0287*/ 0x08040244U,
-/*0288*/ 0x10040244U,
-/*0289*/ 0x18040244U,
-/*028a*/ 0x00040245U,
-/*028b*/ 0x08040245U,
-/*028c*/ 0x10040245U,
-/*028d*/ 0x18010245U,
-/*028e*/ 0x00040246U,
-/*028f*/ 0x08040246U,
-/*0290*/ 0x10040246U,
-/*0291*/ 0x18040246U,
-/*0292*/ 0x00040247U,
-/*0293*/ 0x08040247U,
-/*0294*/ 0x10060247U,
-/*0295*/ 0x18060247U,
-/*0296*/ 0x00060248U,
-/*0297*/ 0x08060248U,
-/*0298*/ 0x10060248U,
-/*0299*/ 0x18060248U,
-/*029a*/ 0x00040249U,
-/*029b*/ 0x08010249U,
-/*029c*/ 0x10010249U,
-/*029d*/ 0x18020249U,
-/*029e*/ 0xffffffffU,
-/*029f*/ 0xffffffffU,
-/*02a0*/ 0xffffffffU,
-/*02a1*/ 0xffffffffU,
-/*02a2*/ 0xffffffffU,
-/*02a3*/ 0xffffffffU,
-/*02a4*/ 0xffffffffU,
-/*02a5*/ 0xffffffffU,
-/*02a6*/ 0x0004024aU,
-/*02a7*/ 0x0804024aU,
-/*02a8*/ 0x1001024aU,
-/*02a9*/ 0x1801024aU,
-/*02aa*/ 0xffffffffU,
-/*02ab*/ 0x0001024bU,
-/*02ac*/ 0x0801024bU,
-/*02ad*/ 0xffffffffU,
-/*02ae*/ 0x1001024bU,
-/*02af*/ 0x1801024bU,
-/*02b0*/ 0x0001024cU,
-/*02b1*/ 0x0804024cU,
-/*02b2*/ 0x1004024cU,
-/*02b3*/ 0x000a024dU,
-/*02b4*/ 0x0020024eU,
-/*02b5*/ 0x0004024fU,
-/*02b6*/ 0x0808024fU,
-/*02b7*/ 0xffffffffU,
-/*02b8*/ 0xffffffffU,
-/*02b9*/ 0xffffffffU,
-/*02ba*/ 0xffffffffU,
-/*02bb*/ 0xffffffffU,
-/*02bc*/ 0xffffffffU,
-/*02bd*/ 0x1002024fU,
-/*02be*/ 0x1802024fU,
-/*02bf*/ 0x00200250U,
-/*02c0*/ 0x00020251U,
-/*02c1*/ 0x08100251U,
-/*02c2*/ 0x00100252U,
-/*02c3*/ 0x10040252U,
-/*02c4*/ 0x18040252U,
-/*02c5*/ 0x00050253U,
-/*02c6*/ 0x08050253U,
-/*02c7*/ 0xffffffffU,
-/*02c8*/ 0xffffffffU,
-/*02c9*/ 0xffffffffU,
-/*02ca*/ 0xffffffffU,
-/*02cb*/ 0x10010253U,
-/*02cc*/ 0x18010253U,
-/*02cd*/ 0x00080254U,
-/*02ce*/ 0x08080254U,
-/*02cf*/ 0x10080254U,
-/*02d0*/ 0x18080254U,
-/*02d1*/ 0x00080255U,
-/*02d2*/ 0x08080255U,
-/*02d3*/ 0x10080255U,
-/*02d4*/ 0x18080255U,
-/*02d5*/ 0x00080256U,
-/*02d6*/ 0x08080256U,
-/*02d7*/ 0x10080256U,
-/*02d8*/ 0xffffffffU,
-/*02d9*/ 0xffffffffU,
-/*02da*/ 0xffffffffU,
-/*02db*/ 0xffffffffU,
-/*02dc*/ 0xffffffffU,
-/*02dd*/ 0xffffffffU,
-/*02de*/ 0x18030256U,
-/*02df*/ 0x00010257U,
-/*02e0*/ 0x08020257U,
-/*02e1*/ 0x10010257U,
-/*02e2*/ 0x18040257U,
-/*02e3*/ 0x00020258U,
-/*02e4*/ 0x08010258U,
-/*02e5*/ 0x10010258U,
-/*02e6*/ 0xffffffffU,
-/*02e7*/ 0x18010258U,
-/*02e8*/ 0x00040259U,
-/*02e9*/ 0x08080259U,
-/*02ea*/ 0x100a0259U,
-/*02eb*/ 0x000a025aU,
-/*02ec*/ 0x100a025aU,
-/*02ed*/ 0x000a025bU,
-/*02ee*/ 0x100a025bU,
-/*02ef*/ 0x000a025cU,
-/*02f0*/ 0x0020025dU,
-/*02f1*/ 0x0020025eU,
-/*02f2*/ 0x0001025fU,
-/*02f3*/ 0xffffffffU,
-/*02f4*/ 0xffffffffU,
-/*02f5*/ 0xffffffffU,
-/*02f6*/ 0x0802025fU,
-/*02f7*/ 0x1002025fU,
-/*02f8*/ 0x00100260U,
-/*02f9*/ 0x10050260U,
-/*02fa*/ 0x18060260U,
-/*02fb*/ 0x00050261U,
-/*02fc*/ 0x08050261U,
-/*02fd*/ 0x100e0261U,
-/*02fe*/ 0x00050262U,
-/*02ff*/ 0x080e0262U,
-/*0300*/ 0x18050262U,
-/*0301*/ 0x000e0263U,
-/*0302*/ 0x10050263U,
-/*0303*/ 0x18010263U,
-/*0304*/ 0x00050264U,
-/*0305*/ 0x08050264U,
-/*0306*/ 0x100a0264U,
-/*0307*/ 0x000a0265U,
-/*0308*/ 0x10050265U,
-/*0309*/ 0x18050265U,
-/*030a*/ 0x000a0266U,
-/*030b*/ 0x100a0266U,
-/*030c*/ 0x00050267U,
-/*030d*/ 0x08050267U,
-/*030e*/ 0x100a0267U,
-/*030f*/ 0x000a0268U,
-/*0310*/ 0xffffffffU,
-/*0311*/ 0xffffffffU,
-/*0312*/ 0xffffffffU,
-/*0313*/ 0xffffffffU,
-/*0314*/ 0xffffffffU,
-/*0315*/ 0xffffffffU,
-/*0316*/ 0x10070268U,
-/*0317*/ 0x18070268U,
-/*0318*/ 0x00040269U,
-/*0319*/ 0x08040269U,
-/*031a*/ 0xffffffffU,
-/*031b*/ 0xffffffffU,
-/*031c*/ 0xffffffffU,
-/*031d*/ 0x10040269U,
-/*031e*/ 0x18080269U,
-/*031f*/ 0x0008026aU,
-/*0320*/ 0x0804026aU,
-/*0321*/ 0xffffffffU,
-/*0322*/ 0xffffffffU,
-/*0323*/ 0xffffffffU,
-/*0324*/ 0x1004026aU,
-/*0325*/ 0xffffffffU,
-/*0326*/ 0xffffffffU,
-/*0327*/ 0xffffffffU,
-/*0328*/ 0x1804026aU,
-/*0329*/ 0xffffffffU,
-/*032a*/ 0xffffffffU,
-/*032b*/ 0xffffffffU,
-/*032c*/ 0x0004026bU,
-/*032d*/ 0x0805026bU,
-/*032e*/ 0x1007026bU,
-/*032f*/ 0x1808026bU,
-/*0330*/ 0x0010026cU,
-/*0331*/ 0x1008026cU,
-/*0332*/ 0x0010026dU,
-/*0333*/ 0x1008026dU,
-/*0334*/ 0x0010026eU,
-/*0335*/ 0x1008026eU,
-/*0336*/ 0x1808026eU,
-/*0337*/ 0x0001026fU,
-/*0338*/ 0x0801026fU,
-/*0339*/ 0x1006026fU,
-/*033a*/ 0x1806026fU,
-/*033b*/ 0x00060270U,
-/*033c*/ 0xffffffffU,
-/*033d*/ 0x08010270U,
-/*033e*/ 0x10030270U,
-/*033f*/ 0xffffffffU,
-/*0340*/ 0xffffffffU,
-/*0341*/ 0xffffffffU,
-/*0342*/ 0x000a0271U,
-/*0343*/ 0x100a0271U,
-/*0344*/ 0x00040272U,
-/*0345*/ 0x08010272U,
-/*0346*/ 0x10040272U,
-/*0347*/ 0xffffffffU,
-/*0348*/ 0xffffffffU,
-/*0349*/ 0xffffffffU,
-/*034a*/ 0xffffffffU,
-/*034b*/ 0xffffffffU,
-/*034c*/ 0xffffffffU,
-/*034d*/ 0x18070272U,
-/*034e*/ 0x00070273U,
-/*034f*/ 0x08050273U,
-/*0350*/ 0x10050273U,
-/*0351*/ 0xffffffffU,
-/*0352*/ 0xffffffffU,
-/*0353*/ 0xffffffffU,
-/*0354*/ 0x18040273U,
-/*0355*/ 0x00010274U,
-/*0356*/ 0x08010274U,
-/*0357*/ 0x10020274U,
-/*0358*/ 0x18080274U,
-/*0359*/ 0x00200275U,
-/*035a*/ 0x00200276U,
-/*035b*/ 0x00100277U,
-/*035c*/ 0xffffffffU,
-/*035d*/ 0xffffffffU,
-/*035e*/ 0xffffffffU,
-/*035f*/ 0x10020277U,
-/*0360*/ 0x18010277U,
-/*0361*/ 0xffffffffU,
-/*0362*/ 0x00020278U,
-/*0363*/ 0x08100278U,
-/*0364*/ 0x00100279U,
-/*0365*/ 0x10100279U,
-/*0366*/ 0x0008027aU,
-/*0367*/ 0x0808027aU,
-/*0368*/ 0x1008027aU,
-/*0369*/ 0xffffffffU,
-/*036a*/ 0x0010027bU,
-/*036b*/ 0x1010027bU,
-/*036c*/ 0x0010027cU,
-/*036d*/ 0x1008027cU,
-/*036e*/ 0x1808027cU,
-/*036f*/ 0x0008027dU,
-/*0370*/ 0xffffffffU,
-/*0371*/ 0x0810027dU,
-/*0372*/ 0x0010027eU,
-/*0373*/ 0x1010027eU,
-/*0374*/ 0x0008027fU,
-/*0375*/ 0x0808027fU,
-/*0376*/ 0x1008027fU,
-/*0377*/ 0xffffffffU,
-/*0378*/ 0x1808027fU,
-/*0379*/ 0x00100280U,
-/*037a*/ 0x10100280U,
-/*037b*/ 0x00100281U,
-/*037c*/ 0x10080281U,
-/*037d*/ 0x18080281U,
-/*037e*/ 0x00080282U,
-/*037f*/ 0xffffffffU,
-/*0380*/ 0x08100282U,
-/*0381*/ 0x00100283U,
-/*0382*/ 0x10100283U,
-/*0383*/ 0x00080284U,
-/*0384*/ 0x08080284U,
-/*0385*/ 0x10080284U,
-/*0386*/ 0xffffffffU,
-/*0387*/ 0x00100285U,
-/*0388*/ 0x10100285U,
-/*0389*/ 0x00100286U,
-/*038a*/ 0x10080286U,
-/*038b*/ 0x18080286U,
-/*038c*/ 0x00080287U,
-/*038d*/ 0xffffffffU,
-/*038e*/ 0x08080287U,
-/*038f*/ 0x10100287U,
-/*0390*/ 0x00100288U,
-/*0391*/ 0x10100288U,
-/*0392*/ 0x00080289U,
-/*0393*/ 0x08080289U,
-/*0394*/ 0x10080289U,
-/*0395*/ 0xffffffffU,
-/*0396*/ 0x0010028aU,
-/*0397*/ 0x1010028aU,
-/*0398*/ 0x0010028bU,
-/*0399*/ 0x1008028bU,
-/*039a*/ 0x1808028bU,
-/*039b*/ 0x0008028cU,
-/*039c*/ 0xffffffffU,
-/*039d*/ 0x0810028cU,
-/*039e*/ 0x0010028dU,
-/*039f*/ 0x1010028dU,
-/*03a0*/ 0x0008028eU,
-/*03a1*/ 0x0808028eU,
-/*03a2*/ 0x1008028eU,
-/*03a3*/ 0xffffffffU,
-/*03a4*/ 0x1808028eU,
-/*03a5*/ 0x0010028fU,
-/*03a6*/ 0x1010028fU,
-/*03a7*/ 0x00100290U,
-/*03a8*/ 0x10080290U,
-/*03a9*/ 0x18080290U,
-/*03aa*/ 0x00080291U,
-/*03ab*/ 0xffffffffU,
-/*03ac*/ 0x08100291U,
-/*03ad*/ 0x00100292U,
-/*03ae*/ 0x10100292U,
-/*03af*/ 0x00080293U,
-/*03b0*/ 0x08080293U,
-/*03b1*/ 0x10080293U,
-/*03b2*/ 0xffffffffU,
-/*03b3*/ 0x00100294U,
-/*03b4*/ 0x10100294U,
-/*03b5*/ 0x00100295U,
-/*03b6*/ 0x10080295U,
-/*03b7*/ 0x18080295U,
-/*03b8*/ 0x00080296U,
-/*03b9*/ 0xffffffffU,
-/*03ba*/ 0x08080296U,
-/*03bb*/ 0x10020296U,
-/*03bc*/ 0x18030296U,
-/*03bd*/ 0x000a0297U,
-/*03be*/ 0x100a0297U,
-/*03bf*/ 0x000a0298U,
-/*03c0*/ 0x10050298U,
-/*03c1*/ 0x18040298U,
-/*03c2*/ 0x00080299U,
-/*03c3*/ 0x08080299U,
-/*03c4*/ 0x10060299U,
-/*03c5*/ 0x18060299U,
-/*03c6*/ 0x0011029aU,
-/*03c7*/ 0x1808029aU,
-/*03c8*/ 0x0004029bU,
-/*03c9*/ 0x0806029bU,
-/*03ca*/ 0xffffffffU,
-/*03cb*/ 0x1006029bU,
-/*03cc*/ 0x1808029bU,
-/*03cd*/ 0x0008029cU,
-/*03ce*/ 0x0804029cU,
-/*03cf*/ 0x1008029cU,
-/*03d0*/ 0x1808029cU,
-/*03d1*/ 0x0006029dU,
-/*03d2*/ 0x0806029dU,
-/*03d3*/ 0x0011029eU,
-/*03d4*/ 0x1808029eU,
-/*03d5*/ 0x0004029fU,
-/*03d6*/ 0x0806029fU,
-/*03d7*/ 0xffffffffU,
-/*03d8*/ 0x1006029fU,
-/*03d9*/ 0x1808029fU,
-/*03da*/ 0x000802a0U,
-/*03db*/ 0x080402a0U,
-/*03dc*/ 0x100802a0U,
-/*03dd*/ 0x180802a0U,
-/*03de*/ 0x000602a1U,
-/*03df*/ 0x080602a1U,
-/*03e0*/ 0x001102a2U,
-/*03e1*/ 0x180802a2U,
-/*03e2*/ 0x000402a3U,
-/*03e3*/ 0x080602a3U,
-/*03e4*/ 0xffffffffU,
-/*03e5*/ 0x100602a3U,
-/*03e6*/ 0x180802a3U,
-/*03e7*/ 0x000802a4U,
-/*03e8*/ 0x080402a4U,
-/*03e9*/ 0x100402a4U,
-/*03ea*/ 0x180402a4U,
-/*03eb*/ 0x000402a5U,
-/*03ec*/ 0x080402a5U,
-/*03ed*/ 0x100402a5U,
-/*03ee*/ 0x180402a5U,
-/*03ef*/ 0x000402a6U,
-/*03f0*/ 0x080402a6U,
-/*03f1*/ 0x100402a6U,
-/*03f2*/ 0x180402a6U,
-/*03f3*/ 0x000402a7U,
-/*03f4*/ 0x080402a7U,
-/*03f5*/ 0x100402a7U,
-/*03f6*/ 0x180402a7U,
-/*03f7*/ 0x000402a8U,
-/*03f8*/ 0x080402a8U,
-/*03f9*/ 0x100402a8U,
-/*03fa*/ 0x180402a8U,
-/*03fb*/ 0x000402a9U,
-/*03fc*/ 0x081202a9U,
-/*03fd*/ 0x001102aaU,
-/*03fe*/ 0x001202abU,
-/*03ff*/ 0x002002acU,
-/*0400*/ 0x002002adU,
-/*0401*/ 0x002002aeU,
-/*0402*/ 0x002002afU,
-/*0403*/ 0x002002b0U,
-/*0404*/ 0x002002b1U,
-/*0405*/ 0x002002b2U,
-/*0406*/ 0x002002b3U,
-/*0407*/ 0x002002b4U,
-/*0408*/ 0x000302b5U,
-/*0409*/ 0x080502b5U,
-/*040a*/ 0x100502b5U,
-/*040b*/ 0x180102b5U,
-/*040c*/ 0x000502b6U,
-/*040d*/ 0x080502b6U,
-/*040e*/ 0x100502b6U,
-/*040f*/ 0x180502b6U,
-/*0410*/ 0x000502b7U,
-/*0411*/ 0x080502b7U,
-/*0412*/ 0x100502b7U,
-/*0413*/ 0x180502b7U,
-/*0414*/ 0x000502b8U,
-/*0415*/ 0x080502b8U,
-/*0416*/ 0x100502b8U,
-/*0417*/ 0x180502b8U,
-/*0418*/ 0x000502b9U,
-/*0419*/ 0x080502b9U,
-/*041a*/ 0x100502b9U,
-/*041b*/ 0x180502b9U,
-/*041c*/ 0x000502baU,
-/*041d*/ 0x080502baU,
-/*041e*/ 0x100502baU,
-/*041f*/ 0x180502baU,
-/*0420*/ 0x000502bbU,
-/*0421*/ 0x080502bbU,
-/*0422*/ 0x100102bbU,
-/*0423*/ 0x180202bbU,
-/*0424*/ 0x000202bcU,
-/*0425*/ 0x080202bcU,
-/*0426*/ 0x100202bcU,
-/*0427*/ 0x180102bcU,
-/*0428*/ 0x000402bdU,
-/*0429*/ 0x081002bdU,
-/*042a*/ 0x002002beU,
-/*042b*/ 0x001002bfU,
-/*042c*/ 0x002002c0U,
-/*042d*/ 0x001002c1U,
-/*042e*/ 0x002002c2U,
-/*042f*/ 0x000702c3U,
-/*0430*/ 0x080102c3U,
-/*0431*/ 0x100202c3U,
-/*0432*/ 0x180602c3U,
-/*0433*/ 0x000102c4U,
-/*0434*/ 0x080102c4U,
-/*0435*/ 0x002002c5U,
-/*0436*/ 0x000302c6U,
-/*0437*/ 0x002002c7U,
-/*0438*/ 0x002002c8U,
-/*0439*/ 0xffffffffU,
-/*043a*/ 0xffffffffU,
-/*043b*/ 0xffffffffU,
-/*043c*/ 0xffffffffU,
-/*043d*/ 0xffffffffU,
-/*043e*/ 0xffffffffU,
-/*043f*/ 0xffffffffU,
-/*0440*/ 0xffffffffU,
-/*0441*/ 0xffffffffU,
-/*0442*/ 0xffffffffU,
-/*0443*/ 0xffffffffU,
-/*0444*/ 0xffffffffU,
-/*0445*/ 0xffffffffU,
-/*0446*/ 0xffffffffU,
-/*0447*/ 0xffffffffU,
-/*0448*/ 0xffffffffU,
-/*0449*/ 0xffffffffU,
-/*044a*/ 0xffffffffU,
-/*044b*/ 0xffffffffU,
-/*044c*/ 0xffffffffU,
-/*044d*/ 0xffffffffU,
-/*044e*/ 0xffffffffU,
-/*044f*/ 0xffffffffU,
-/*0450*/ 0xffffffffU,
-/*0451*/ 0xffffffffU,
-/*0452*/ 0xffffffffU,
-/*0453*/ 0xffffffffU,
-/*0454*/ 0xffffffffU,
-/*0455*/ 0xffffffffU,
-/*0456*/ 0xffffffffU,
-/*0457*/ 0xffffffffU,
-/*0458*/ 0xffffffffU,
-/*0459*/ 0xffffffffU,
-/*045a*/ 0xffffffffU,
-/*045b*/ 0xffffffffU,
-/*045c*/ 0xffffffffU,
-/*045d*/ 0xffffffffU,
-/*045e*/ 0xffffffffU,
-/*045f*/ 0x000402c9U,
-/*0460*/ 0xffffffffU,
-/*0461*/ 0xffffffffU,
-/*0462*/ 0xffffffffU,
-/*0463*/ 0xffffffffU,
-/*0464*/ 0xffffffffU,
-/*0465*/ 0xffffffffU,
-/*0466*/ 0xffffffffU,
-/*0467*/ 0xffffffffU,
-/*0468*/ 0xffffffffU,
-/*0469*/ 0xffffffffU,
-/*046a*/ 0xffffffffU,
-/*046b*/ 0xffffffffU,
-/*046c*/ 0xffffffffU,
-/*046d*/ 0xffffffffU,
-/*046e*/ 0xffffffffU,
-/*046f*/ 0xffffffffU,
-/*0470*/ 0xffffffffU,
-/*0471*/ 0xffffffffU,
-/*0472*/ 0xffffffffU,
-/*0473*/ 0xffffffffU,
-/*0474*/ 0xffffffffU,
-/*0475*/ 0xffffffffU,
-/*0476*/ 0xffffffffU,
-/*0477*/ 0xffffffffU,
-/*0478*/ 0xffffffffU,
-/*0479*/ 0xffffffffU,
-/*047a*/ 0xffffffffU,
-/*047b*/ 0xffffffffU,
-/*047c*/ 0xffffffffU,
-/*047d*/ 0xffffffffU,
-/*047e*/ 0xffffffffU,
-/*047f*/ 0xffffffffU,
-/*0480*/ 0xffffffffU,
-/*0481*/ 0xffffffffU,
-/*0482*/ 0xffffffffU,
-/*0483*/ 0xffffffffU,
-/*0484*/ 0xffffffffU,
-/*0485*/ 0xffffffffU,
-/*0486*/ 0xffffffffU,
-/*0487*/ 0xffffffffU,
-/*0488*/ 0xffffffffU,
-/*0489*/ 0xffffffffU,
-/*048a*/ 0xffffffffU,
-/*048b*/ 0xffffffffU,
-/*048c*/ 0xffffffffU,
-/*048d*/ 0xffffffffU,
-/*048e*/ 0xffffffffU,
-/*048f*/ 0xffffffffU,
-/*0490*/ 0xffffffffU,
-/*0491*/ 0xffffffffU,
-/*0492*/ 0xffffffffU,
-/*0493*/ 0xffffffffU,
-/*0494*/ 0xffffffffU,
- },
- {
-/*0000*/ 0x00200400U,
-/*0001*/ 0x00040401U,
-/*0002*/ 0x080b0401U,
-/*0003*/ 0x000a0402U,
-/*0004*/ 0x10020402U,
-/*0005*/ 0x18010402U,
-/*0006*/ 0x00050403U,
-/*0007*/ 0x08050403U,
-/*0008*/ 0x10050403U,
-/*0009*/ 0x18050403U,
-/*000a*/ 0x00050404U,
-/*000b*/ 0x08050404U,
-/*000c*/ 0x10050404U,
-/*000d*/ 0x18050404U,
-/*000e*/ 0x00050405U,
-/*000f*/ 0x08040405U,
-/*0010*/ 0x10030405U,
-/*0011*/ 0x00180406U,
-/*0012*/ 0x18030406U,
-/*0013*/ 0x00180407U,
-/*0014*/ 0x18020407U,
-/*0015*/ 0x00010408U,
-/*0016*/ 0x08020408U,
-/*0017*/ 0x10010408U,
-/*0018*/ 0x18010408U,
-/*0019*/ 0x00020409U,
-/*001a*/ 0x08040409U,
-/*001b*/ 0x10040409U,
-/*001c*/ 0x18040409U,
-/*001d*/ 0xffffffffU,
-/*001e*/ 0x0004040aU,
-/*001f*/ 0xffffffffU,
-/*0020*/ 0xffffffffU,
-/*0021*/ 0x0809040aU,
-/*0022*/ 0x1801040aU,
-/*0023*/ 0x0020040bU,
-/*0024*/ 0x001c040cU,
-/*0025*/ 0x0001040dU,
-/*0026*/ 0x0807040dU,
-/*0027*/ 0x1009040dU,
-/*0028*/ 0x000a040eU,
-/*0029*/ 0x1005040eU,
-/*002a*/ 0x1801040eU,
-/*002b*/ 0x1001040fU,
-/*002c*/ 0x1802040fU,
-/*002d*/ 0x0009040fU,
-/*002e*/ 0x00090410U,
-/*002f*/ 0x10020410U,
-/*0030*/ 0x00200411U,
-/*0031*/ 0x00010412U,
-/*0032*/ 0x08020412U,
-/*0033*/ 0xffffffffU,
-/*0034*/ 0xffffffffU,
-/*0035*/ 0xffffffffU,
-/*0036*/ 0xffffffffU,
-/*0037*/ 0x00200413U,
-/*0038*/ 0x00200414U,
-/*0039*/ 0x00200415U,
-/*003a*/ 0x00200416U,
-/*003b*/ 0x00030417U,
-/*003c*/ 0x08010417U,
-/*003d*/ 0x10040417U,
-/*003e*/ 0x18030417U,
-/*003f*/ 0x00040418U,
-/*0040*/ 0x08040418U,
-/*0041*/ 0x10040418U,
-/*0042*/ 0x18040418U,
-/*0043*/ 0x00010419U,
-/*0044*/ 0x08010419U,
-/*0045*/ 0x10060419U,
-/*0046*/ 0x18040419U,
-/*0047*/ 0xffffffffU,
-/*0048*/ 0x0006041aU,
-/*0049*/ 0x0804041aU,
-/*004a*/ 0x1006041aU,
-/*004b*/ 0x1804041aU,
-/*004c*/ 0x0002041bU,
-/*004d*/ 0x0805041bU,
-/*004e*/ 0x1008041bU,
-/*004f*/ 0xffffffffU,
-/*0050*/ 0x1806041bU,
-/*0051*/ 0x0003041cU,
-/*0052*/ 0x080b041cU,
-/*0053*/ 0x1804041cU,
-/*0054*/ 0x0004041dU,
-/*0055*/ 0x0804041dU,
-/*0056*/ 0x1001041dU,
-/*0057*/ 0xffffffffU,
-/*0058*/ 0x0009041eU,
-/*0059*/ 0x0020041fU,
-/*005a*/ 0x00200420U,
-/*005b*/ 0x00200421U,
-/*005c*/ 0x00200422U,
-/*005d*/ 0x00100423U,
-/*005e*/ 0xffffffffU,
-/*005f*/ 0x10010423U,
-/*0060*/ 0x18060423U,
-/*0061*/ 0x00080424U,
-/*0062*/ 0x00200425U,
-/*0063*/ 0x00100426U,
-/*0064*/ 0x100a0426U,
-/*0065*/ 0x00060427U,
-/*0066*/ 0x08070427U,
-/*0067*/ 0x10080427U,
-/*0068*/ 0x18080427U,
-/*0069*/ 0x000a0428U,
-/*006a*/ 0x10070428U,
-/*006b*/ 0x18080428U,
-/*006c*/ 0x00080429U,
-/*006d*/ 0x08030429U,
-/*006e*/ 0x100a0429U,
-/*006f*/ 0x000a042aU,
-/*0070*/ 0x0011042bU,
-/*0071*/ 0x0009042cU,
-/*0072*/ 0x1009042cU,
-/*0073*/ 0x0010042dU,
-/*0074*/ 0x100e042dU,
-/*0075*/ 0x000e042eU,
-/*0076*/ 0x0012042fU,
-/*0077*/ 0x000a0430U,
-/*0078*/ 0x100a0430U,
-/*0079*/ 0x00020431U,
-/*007a*/ 0x00200432U,
-/*007b*/ 0x000b0433U,
-/*007c*/ 0x100b0433U,
-/*007d*/ 0x00200434U,
-/*007e*/ 0x00120435U,
-/*007f*/ 0x00200436U,
-/*0080*/ 0x00200437U,
-/*0081*/ 0x00080438U,
-/*0082*/ 0x08010438U,
-/*0083*/ 0x10010438U,
-/*0084*/ 0x18010438U,
-/*0085*/ 0x00080439U,
-/*0086*/ 0x080c0439U,
-/*0087*/ 0x000c043aU,
-/*0088*/ 0x100c043aU,
-/*0089*/ 0x000c043bU,
-/*008a*/ 0x100c043bU,
-/*008b*/ 0x000c043cU,
-/*008c*/ 0x100c043cU,
-/*008d*/ 0x000c043dU,
-/*008e*/ 0x100c043dU,
-/*008f*/ 0x000c043eU,
-/*0090*/ 0x100c043eU,
-/*0091*/ 0x000b043fU,
-/*0092*/ 0x1009043fU,
-/*0093*/ 0x00010440U,
-/*0094*/ 0x000b0441U,
-/*0095*/ 0x100b0441U,
-/*0096*/ 0x000b0442U,
-/*0097*/ 0x100b0442U,
-/*0098*/ 0x000b0443U,
-/*0099*/ 0x100b0443U,
-/*009a*/ 0x000b0444U,
-/*009b*/ 0x100b0444U,
-/*009c*/ 0x000b0445U,
-/*009d*/ 0x100a0445U,
-/*009e*/ 0x00020446U,
-/*009f*/ 0x080a0446U,
-/*00a0*/ 0x000a0447U,
-/*00a1*/ 0x100a0447U,
-/*00a2*/ 0x000a0448U,
-/*00a3*/ 0x100a0448U,
-/*00a4*/ 0x000a0449U,
-/*00a5*/ 0x100a0449U,
-/*00a6*/ 0x000a044aU,
-/*00a7*/ 0x100a044aU,
-/*00a8*/ 0x000a044bU,
-/*00a9*/ 0x100a044bU,
-/*00aa*/ 0x000a044cU,
-/*00ab*/ 0x100a044cU,
-/*00ac*/ 0x000a044dU,
-/*00ad*/ 0x100a044dU,
-/*00ae*/ 0x000a044eU,
-/*00af*/ 0x100a044eU,
-/*00b0*/ 0x000a044fU,
-/*00b1*/ 0x100a044fU,
-/*00b2*/ 0x000a0450U,
-/*00b3*/ 0x100a0450U,
-/*00b4*/ 0x000a0451U,
-/*00b5*/ 0x100a0451U,
-/*00b6*/ 0x000a0452U,
-/*00b7*/ 0x100a0452U,
-/*00b8*/ 0x000a0453U,
-/*00b9*/ 0x100a0453U,
-/*00ba*/ 0x000a0454U,
-/*00bb*/ 0x10040454U,
-/*00bc*/ 0x18030454U,
-/*00bd*/ 0x000a0455U,
-/*00be*/ 0x100a0455U,
-/*00bf*/ 0x00010456U,
-/*00c0*/ 0x080a0456U,
-/*00c1*/ 0x18040456U,
-/*00c2*/ 0x000b0457U,
-/*00c3*/ 0x100a0457U,
-/*00c4*/ 0x00030458U,
-/*00c5*/ 0x00080459U,
-/*00c6*/ 0x08080459U,
-/*00c7*/ 0x10080459U,
-/*00c8*/ 0x18080459U,
-/*00c9*/ 0x0008045aU,
-/*00ca*/ 0xffffffffU,
-/*00cb*/ 0x0808045aU,
-/*00cc*/ 0x1001045aU,
-/*00cd*/ 0x1808045aU,
-/*00ce*/ 0x0008045bU,
-/*00cf*/ 0x0802045bU,
-/*00d0*/ 0x1002045bU,
-/*00d1*/ 0x1805045bU,
-/*00d2*/ 0x0005045cU,
-/*00d3*/ 0xffffffffU,
-/*00d4*/ 0x0804045cU,
-/*00d5*/ 0x100a045cU,
-/*00d6*/ 0x0006045dU,
-/*00d7*/ 0x0808045dU,
-/*00d8*/ 0x1008045dU,
-/*00d9*/ 0x1804045dU,
-/*00da*/ 0x0004045eU,
-/*00db*/ 0x0805045eU,
-/*00dc*/ 0x1004045eU,
-/*00dd*/ 0x1805045eU,
-/*00de*/ 0x000a045fU,
-/*00df*/ 0x100a045fU,
-/*00e0*/ 0x00080460U,
-/*00e1*/ 0xffffffffU,
-/*00e2*/ 0x08040460U,
-/*00e3*/ 0xffffffffU,
-/*00e4*/ 0xffffffffU,
-/*00e5*/ 0x00050600U,
-/*00e6*/ 0x08050600U,
-/*00e7*/ 0x10050600U,
-/*00e8*/ 0x18050600U,
-/*00e9*/ 0x00050601U,
-/*00ea*/ 0x08050601U,
-/*00eb*/ 0x100b0601U,
-/*00ec*/ 0x00010602U,
-/*00ed*/ 0x08030602U,
-/*00ee*/ 0x00200603U,
-/*00ef*/ 0x00100604U,
-/*00f0*/ 0x10040604U,
-/*00f1*/ 0x000a0605U,
-/*00f2*/ 0x10090605U,
-/*00f3*/ 0x00080606U,
-/*00f4*/ 0x08030606U,
-/*00f5*/ 0x10030606U,
-/*00f6*/ 0x18010606U,
-/*00f7*/ 0x00010607U,
-/*00f8*/ 0x08070607U,
-/*00f9*/ 0x10070607U,
-/*00fa*/ 0x18050607U,
-/*00fb*/ 0x00010608U,
-/*00fc*/ 0x08020608U,
-/*00fd*/ 0x10030608U,
-/*00fe*/ 0x18010608U,
-/*00ff*/ 0x000f0609U,
-/*0100*/ 0x0020060aU,
-/*0101*/ 0x0020060bU,
-/*0102*/ 0x000b060cU,
-/*0103*/ 0x100b060cU,
-/*0104*/ 0x000b060dU,
-/*0105*/ 0x0018060eU,
-/*0106*/ 0x0018060fU,
-/*0107*/ 0xffffffffU,
-/*0108*/ 0xffffffffU,
-/*0109*/ 0xffffffffU,
-/*010a*/ 0xffffffffU,
-/*010b*/ 0xffffffffU,
-/*010c*/ 0x1802060fU,
-/*010d*/ 0x00020610U,
-/*010e*/ 0x08040610U,
-/*010f*/ 0x10040610U,
-/*0110*/ 0x18010610U,
-/*0111*/ 0x00010611U,
-/*0112*/ 0x08010611U,
-/*0113*/ 0x10030611U,
-/*0114*/ 0x00200612U,
-/*0115*/ 0x00200613U,
-/*0116*/ 0xffffffffU,
-/*0117*/ 0x00140614U,
-/*0118*/ 0x00140615U,
-/*0119*/ 0x00140616U,
-/*011a*/ 0x00140617U,
-/*011b*/ 0x00140618U,
-/*011c*/ 0x00140619U,
-/*011d*/ 0x0014061aU,
-/*011e*/ 0x0014061bU,
-/*011f*/ 0x0018061cU,
-/*0120*/ 0x000a061dU,
-/*0121*/ 0x1006061dU,
-/*0122*/ 0x1806061dU,
-/*0123*/ 0x0006061eU,
-/*0124*/ 0xffffffffU,
-/*0125*/ 0x0806061eU,
-/*0126*/ 0x0008061fU,
-/*0127*/ 0x080b061fU,
-/*0128*/ 0x000b0620U,
-/*0129*/ 0x100b0620U,
-/*012a*/ 0x000b0621U,
-/*012b*/ 0x100b0621U,
-/*012c*/ 0x000b0622U,
-/*012d*/ 0x10040622U,
-/*012e*/ 0x000a0623U,
-/*012f*/ 0x10060623U,
-/*0130*/ 0x18080623U,
-/*0131*/ 0x00080624U,
-/*0132*/ 0x08040624U,
-/*0133*/ 0x00020680U,
-/*0134*/ 0x00010681U,
-/*0135*/ 0x08010681U,
-/*0136*/ 0x10020681U,
-/*0137*/ 0x18050681U,
-/*0138*/ 0x00050682U,
-/*0139*/ 0x08050682U,
-/*013a*/ 0x10050682U,
-/*013b*/ 0x000b0683U,
-/*013c*/ 0x10050683U,
-/*013d*/ 0x18010683U,
-/*013e*/ 0x00010684U,
-/*013f*/ 0xffffffffU,
-/*0140*/ 0x08010684U,
-/*0141*/ 0x10010684U,
-/*0142*/ 0x18040684U,
-/*0143*/ 0x000b0685U,
-/*0144*/ 0x100b0685U,
-/*0145*/ 0x000b0686U,
-/*0146*/ 0x10040686U,
-/*0147*/ 0x000b0687U,
-/*0148*/ 0x10040687U,
-/*0149*/ 0x18010687U,
-/*014a*/ 0x00010688U,
-/*014b*/ 0x08010688U,
-/*014c*/ 0x00200689U,
-/*014d*/ 0x0020068aU,
-/*014e*/ 0x0008068bU,
-/*014f*/ 0x080a068bU,
-/*0150*/ 0x1805068bU,
-/*0151*/ 0x000a068cU,
-/*0152*/ 0x1003068cU,
-/*0153*/ 0x1803068cU,
-/*0154*/ 0x0001068dU,
-/*0155*/ 0x0802068dU,
-/*0156*/ 0x1001068dU,
-/*0157*/ 0x1801068dU,
-/*0158*/ 0x0001068eU,
-/*0159*/ 0x0802068eU,
-/*015a*/ 0x1001068eU,
-/*015b*/ 0x0004068fU,
-/*015c*/ 0x0804068fU,
-/*015d*/ 0x1004068fU,
-/*015e*/ 0x1804068fU,
-/*015f*/ 0x00010690U,
-/*0160*/ 0x08010690U,
-/*0161*/ 0x10010690U,
-/*0162*/ 0x00200691U,
-/*0163*/ 0x00200692U,
-/*0164*/ 0x00200693U,
-/*0165*/ 0x00200694U,
-/*0166*/ 0xffffffffU,
-/*0167*/ 0x1801068eU,
-/*0168*/ 0x000d0696U,
-/*0169*/ 0x100d0696U,
-/*016a*/ 0x000d0697U,
-/*016b*/ 0x00050698U,
-/*016c*/ 0x00010699U,
-/*016d*/ 0x080e0699U,
-/*016e*/ 0x000e069aU,
-/*016f*/ 0x100e069aU,
-/*0170*/ 0x000e069bU,
-/*0171*/ 0x100e069bU,
-/*0172*/ 0x0004069cU,
-/*0173*/ 0x0804069cU,
-/*0174*/ 0x1004069cU,
-/*0175*/ 0x1804069cU,
-/*0176*/ 0x0004069dU,
-/*0177*/ 0x080b069dU,
-/*0178*/ 0x000b069eU,
-/*0179*/ 0x100b069eU,
-/*017a*/ 0x000b069fU,
-/*017b*/ 0xffffffffU,
-/*017c*/ 0xffffffffU,
-/*017d*/ 0xffffffffU,
-/*017e*/ 0xffffffffU,
-/*017f*/ 0x000d06a0U,
-/*0180*/ 0x100d06a0U,
-/*0181*/ 0x000d06a1U,
-/*0182*/ 0x101006a1U,
-/*0183*/ 0x00080695U,
-/*0184*/ 0x08080695U,
-/*0185*/ 0x001006a2U,
-/*0186*/ 0x101006a2U,
-/*0187*/ 0x001006a3U,
-/*0188*/ 0x101006a3U,
-/*0189*/ 0x001006a4U,
-/*018a*/ 0x100306a4U,
-/*018b*/ 0x180406a4U,
-/*018c*/ 0x000106a5U,
-/*018d*/ 0x080806a5U,
-/*018e*/ 0x100106a5U,
-/*018f*/ 0x180506a5U,
-/*0190*/ 0x000106a6U,
-/*0191*/ 0x081406a6U,
-/*0192*/ 0x000a06a7U,
-/*0193*/ 0x100c06a7U,
-/*0194*/ 0x001206a8U,
-/*0195*/ 0x001406a9U,
-/*0196*/ 0x001206aaU,
-/*0197*/ 0x001106abU,
-/*0198*/ 0x001106acU,
-/*0199*/ 0x001206adU,
-/*019a*/ 0x001206aeU,
-/*019b*/ 0x001206afU,
-/*019c*/ 0x001206b0U,
-/*019d*/ 0x001206b1U,
-/*019e*/ 0x001206b2U,
-/*019f*/ 0x001206b3U,
-/*01a0*/ 0x001206b4U,
-/*01a1*/ 0x001206b5U,
-/*01a2*/ 0x001206b6U,
-/*01a3*/ 0x000e06b7U,
-/*01a4*/ 0x100d06b7U,
-/*01a5*/ 0x002006b8U,
-/*01a6*/ 0x001706b9U,
-/*01a7*/ 0x000906baU,
-/*01a8*/ 0x100106baU,
-/*01a9*/ 0x180106baU,
-/*01aa*/ 0x002006bbU,
-/*01ab*/ 0x000806bcU,
-/*01ac*/ 0x080306bcU,
-/*01ad*/ 0x100306bcU,
-/*01ae*/ 0x001806bdU,
-/*01af*/ 0x001806beU,
-/*01b0*/ 0x180706beU,
-/*01b1*/ 0x000506bfU,
-/*01b2*/ 0x080806bfU,
-/*01b3*/ 0x100806bfU,
-/*01b4*/ 0x180806bfU,
-/*01b5*/ 0x000106c0U,
-/*01b6*/ 0x080106c0U,
-/*01b7*/ 0x002006c1U,
-/*01b8*/ 0xffffffffU,
-/*01b9*/ 0xffffffffU,
-/*01ba*/ 0xffffffffU,
-/*01bb*/ 0xffffffffU,
-/*01bc*/ 0xffffffffU,
-/*01bd*/ 0xffffffffU,
-/*01be*/ 0xffffffffU,
-/*01bf*/ 0x001006c2U,
-/*01c0*/ 0x100106c2U,
-/*01c1*/ 0x180106c2U,
-/*01c2*/ 0x000206c3U,
-/*01c3*/ 0x080406c3U,
-/*01c4*/ 0x100906c3U,
-/*01c5*/ 0x000706c4U,
-/*01c6*/ 0x080406c4U,
-/*01c7*/ 0x002006c5U,
-/*01c8*/ 0x000106c6U,
-/*01c9*/ 0x080206c6U,
-/*01ca*/ 0x100606c6U,
-/*01cb*/ 0x001006c7U,
-/*01cc*/ 0x100106c7U,
-/*01cd*/ 0x002006c8U,
-/*01ce*/ 0x000806c9U,
-/*01cf*/ 0x080106c9U,
-/*01d0*/ 0x100506c9U,
-/*01d1*/ 0xffffffffU,
-/*01d2*/ 0x180206c9U,
-/*01d3*/ 0x000106caU,
-/*01d4*/ 0x002006cbU,
-/*01d5*/ 0x000b06ccU,
-/*01d6*/ 0x100106ccU,
-/*01d7*/ 0x180306ccU,
-/*01d8*/ 0x000806cdU,
-/*01d9*/ 0x080206cdU,
-/*01da*/ 0x100c06cdU,
-/*01db*/ 0x000406ceU,
-/*01dc*/ 0x080106ceU,
-/*01dd*/ 0xffffffffU,
-/*01de*/ 0x00010200U,
-/*01df*/ 0x08040200U,
-/*01e0*/ 0x10100200U,
-/*01e1*/ 0x00010201U,
-/*01e2*/ 0x08010201U,
-/*01e3*/ 0x10010201U,
-/*01e4*/ 0xffffffffU,
-/*01e5*/ 0x00100202U,
-/*01e6*/ 0x10080202U,
-/*01e7*/ 0xffffffffU,
-/*01e8*/ 0xffffffffU,
-/*01e9*/ 0xffffffffU,
-/*01ea*/ 0xffffffffU,
-/*01eb*/ 0xffffffffU,
-/*01ec*/ 0xffffffffU,
-/*01ed*/ 0xffffffffU,
-/*01ee*/ 0xffffffffU,
-/*01ef*/ 0x00200203U,
-/*01f0*/ 0x00100204U,
-/*01f1*/ 0x00200205U,
-/*01f2*/ 0x00100206U,
-/*01f3*/ 0x00200207U,
-/*01f4*/ 0x00100208U,
-/*01f5*/ 0x00140209U,
-/*01f6*/ 0x0020020aU,
-/*01f7*/ 0x0020020bU,
-/*01f8*/ 0x0020020cU,
-/*01f9*/ 0x0020020dU,
-/*01fa*/ 0x0014020eU,
-/*01fb*/ 0x0020020fU,
-/*01fc*/ 0x00200210U,
-/*01fd*/ 0x00200211U,
-/*01fe*/ 0x00200212U,
-/*01ff*/ 0x00140213U,
-/*0200*/ 0x00200214U,
-/*0201*/ 0x00200215U,
-/*0202*/ 0x00200216U,
-/*0203*/ 0x00200217U,
-/*0204*/ 0x00090218U,
-/*0205*/ 0x10010218U,
-/*0206*/ 0x00200219U,
-/*0207*/ 0x0005021aU,
-/*0208*/ 0x0801021aU,
-/*0209*/ 0x1008021aU,
-/*020a*/ 0x1808021aU,
-/*020b*/ 0x001c021bU,
-/*020c*/ 0x001c021cU,
-/*020d*/ 0x001c021dU,
-/*020e*/ 0x001c021eU,
-/*020f*/ 0x001c021fU,
-/*0210*/ 0x001c0220U,
-/*0211*/ 0x001c0221U,
-/*0212*/ 0x001c0222U,
-/*0213*/ 0x001c0223U,
-/*0214*/ 0x001c0224U,
-/*0215*/ 0x001c0225U,
-/*0216*/ 0x001c0226U,
-/*0217*/ 0x001c0227U,
-/*0218*/ 0x001c0228U,
-/*0219*/ 0x001c0229U,
-/*021a*/ 0x001c022aU,
-/*021b*/ 0x0001022bU,
-/*021c*/ 0x0801022bU,
-/*021d*/ 0x1001022bU,
-/*021e*/ 0x1804022bU,
-/*021f*/ 0x0008022cU,
-/*0220*/ 0x0808022cU,
-/*0221*/ 0x1008022cU,
-/*0222*/ 0x1804022cU,
-/*0223*/ 0x0007022dU,
-/*0224*/ 0xffffffffU,
-/*0225*/ 0x0807022dU,
-/*0226*/ 0x1007022dU,
-/*0227*/ 0xffffffffU,
-/*0228*/ 0x1807022dU,
-/*0229*/ 0x0007022eU,
-/*022a*/ 0xffffffffU,
-/*022b*/ 0x0807022eU,
-/*022c*/ 0x1002022eU,
-/*022d*/ 0x1801022eU,
-/*022e*/ 0x0001022fU,
-/*022f*/ 0x080a022fU,
-/*0230*/ 0x00140230U,
-/*0231*/ 0x000a0231U,
-/*0232*/ 0x00140232U,
-/*0233*/ 0x000a0233U,
-/*0234*/ 0x00140234U,
-/*0235*/ 0x18010234U,
-/*0236*/ 0x00100235U,
-/*0237*/ 0x10050235U,
-/*0238*/ 0x18010235U,
-/*0239*/ 0x00010236U,
-/*023a*/ 0x08010236U,
-/*023b*/ 0x10010236U,
-/*023c*/ 0x18010236U,
-/*023d*/ 0x00010237U,
-/*023e*/ 0x08010237U,
-/*023f*/ 0x10020237U,
-/*0240*/ 0x18020237U,
-/*0241*/ 0x00020238U,
-/*0242*/ 0x08020238U,
-/*0243*/ 0x10020238U,
-/*0244*/ 0x18030238U,
-/*0245*/ 0x00010239U,
-/*0246*/ 0x08010239U,
-/*0247*/ 0x10010239U,
-/*0248*/ 0x18010239U,
-/*0249*/ 0xffffffffU,
-/*024a*/ 0x0002023aU,
-/*024b*/ 0x0801023aU,
-/*024c*/ 0x1001023aU,
-/*024d*/ 0xffffffffU,
-/*024e*/ 0x1802023aU,
-/*024f*/ 0x0001023bU,
-/*0250*/ 0x0801023bU,
-/*0251*/ 0xffffffffU,
-/*0252*/ 0x1002023bU,
-/*0253*/ 0x1801023bU,
-/*0254*/ 0x0001023cU,
-/*0255*/ 0xffffffffU,
-/*0256*/ 0x0802023cU,
-/*0257*/ 0x1007023cU,
-/*0258*/ 0x1801023cU,
-/*0259*/ 0x0001023dU,
-/*025a*/ 0x0801023dU,
-/*025b*/ 0x1001023dU,
-/*025c*/ 0x1801023dU,
-/*025d*/ 0x0001023eU,
-/*025e*/ 0x0801023eU,
-/*025f*/ 0x1001023eU,
-/*0260*/ 0x1804023eU,
-/*0261*/ 0x0004023fU,
-/*0262*/ 0x0804023fU,
-/*0263*/ 0x1001023fU,
-/*0264*/ 0x1802023fU,
-/*0265*/ 0x00060240U,
-/*0266*/ 0x08060240U,
-/*0267*/ 0x10020240U,
-/*0268*/ 0x18020240U,
-/*0269*/ 0x00020241U,
-/*026a*/ 0xffffffffU,
-/*026b*/ 0x08100241U,
-/*026c*/ 0x18010241U,
-/*026d*/ 0x00010242U,
-/*026e*/ 0x08010242U,
-/*026f*/ 0x10040242U,
-/*0270*/ 0x18010242U,
-/*0271*/ 0x00040243U,
-/*0272*/ 0x08020243U,
-/*0273*/ 0x10080243U,
-/*0274*/ 0xffffffffU,
-/*0275*/ 0xffffffffU,
-/*0276*/ 0xffffffffU,
-/*0277*/ 0x000a0244U,
-/*0278*/ 0x00200245U,
-/*0279*/ 0x00200246U,
-/*027a*/ 0x00050247U,
-/*027b*/ 0x08010247U,
-/*027c*/ 0x10050247U,
-/*027d*/ 0x18080247U,
-/*027e*/ 0x00010248U,
-/*027f*/ 0x08080248U,
-/*0280*/ 0x10010248U,
-/*0281*/ 0x18080248U,
-/*0282*/ 0x00010249U,
-/*0283*/ 0x08040249U,
-/*0284*/ 0x10040249U,
-/*0285*/ 0x18040249U,
-/*0286*/ 0x0004024aU,
-/*0287*/ 0x0804024aU,
-/*0288*/ 0x1004024aU,
-/*0289*/ 0x1804024aU,
-/*028a*/ 0x0004024bU,
-/*028b*/ 0x0804024bU,
-/*028c*/ 0x1004024bU,
-/*028d*/ 0x1801024bU,
-/*028e*/ 0x0004024cU,
-/*028f*/ 0x0804024cU,
-/*0290*/ 0x1004024cU,
-/*0291*/ 0x1804024cU,
-/*0292*/ 0x0004024dU,
-/*0293*/ 0x0804024dU,
-/*0294*/ 0x1006024dU,
-/*0295*/ 0x1806024dU,
-/*0296*/ 0x0006024eU,
-/*0297*/ 0x0806024eU,
-/*0298*/ 0x1006024eU,
-/*0299*/ 0x1806024eU,
-/*029a*/ 0xffffffffU,
-/*029b*/ 0x0001024fU,
-/*029c*/ 0x0801024fU,
-/*029d*/ 0x1002024fU,
-/*029e*/ 0xffffffffU,
-/*029f*/ 0xffffffffU,
-/*02a0*/ 0xffffffffU,
-/*02a1*/ 0xffffffffU,
-/*02a2*/ 0xffffffffU,
-/*02a3*/ 0xffffffffU,
-/*02a4*/ 0xffffffffU,
-/*02a5*/ 0xffffffffU,
-/*02a6*/ 0x1804024fU,
-/*02a7*/ 0x00040250U,
-/*02a8*/ 0x08010250U,
-/*02a9*/ 0x10010250U,
-/*02aa*/ 0x18010250U,
-/*02ab*/ 0x00010251U,
-/*02ac*/ 0x08010251U,
-/*02ad*/ 0x10010251U,
-/*02ae*/ 0x18010251U,
-/*02af*/ 0x00010252U,
-/*02b0*/ 0x08010252U,
-/*02b1*/ 0x10040252U,
-/*02b2*/ 0x18040252U,
-/*02b3*/ 0x000a0253U,
-/*02b4*/ 0x00200254U,
-/*02b5*/ 0x00040255U,
-/*02b6*/ 0x08080255U,
-/*02b7*/ 0x10020255U,
-/*02b8*/ 0x18020255U,
-/*02b9*/ 0x00020256U,
-/*02ba*/ 0x08020256U,
-/*02bb*/ 0x10020256U,
-/*02bc*/ 0x18020256U,
-/*02bd*/ 0xffffffffU,
-/*02be*/ 0xffffffffU,
-/*02bf*/ 0x00200257U,
-/*02c0*/ 0x00020258U,
-/*02c1*/ 0x08100258U,
-/*02c2*/ 0x00100259U,
-/*02c3*/ 0x10040259U,
-/*02c4*/ 0x18040259U,
-/*02c5*/ 0x0005025aU,
-/*02c6*/ 0x0805025aU,
-/*02c7*/ 0x0020025bU,
-/*02c8*/ 0x0020025cU,
-/*02c9*/ 0x0020025dU,
-/*02ca*/ 0x0020025eU,
-/*02cb*/ 0x0001025fU,
-/*02cc*/ 0x0801025fU,
-/*02cd*/ 0x1007025fU,
-/*02ce*/ 0x1807025fU,
-/*02cf*/ 0x00070260U,
-/*02d0*/ 0x08070260U,
-/*02d1*/ 0x10070260U,
-/*02d2*/ 0x18070260U,
-/*02d3*/ 0x00070261U,
-/*02d4*/ 0x08070261U,
-/*02d5*/ 0x10070261U,
-/*02d6*/ 0x18070261U,
-/*02d7*/ 0x00070262U,
-/*02d8*/ 0x08070262U,
-/*02d9*/ 0x10070262U,
-/*02da*/ 0x18070262U,
-/*02db*/ 0x00030263U,
-/*02dc*/ 0x08030263U,
-/*02dd*/ 0x10030263U,
-/*02de*/ 0xffffffffU,
-/*02df*/ 0x18010263U,
-/*02e0*/ 0x00020264U,
-/*02e1*/ 0x08010264U,
-/*02e2*/ 0x10040264U,
-/*02e3*/ 0x18020264U,
-/*02e4*/ 0x00010265U,
-/*02e5*/ 0x08010265U,
-/*02e6*/ 0x10010265U,
-/*02e7*/ 0x18010265U,
-/*02e8*/ 0x00040266U,
-/*02e9*/ 0x08080266U,
-/*02ea*/ 0x100a0266U,
-/*02eb*/ 0x000a0267U,
-/*02ec*/ 0x100a0267U,
-/*02ed*/ 0x000a0268U,
-/*02ee*/ 0x100a0268U,
-/*02ef*/ 0x000a0269U,
-/*02f0*/ 0x0020026aU,
-/*02f1*/ 0x0020026bU,
-/*02f2*/ 0x0001026cU,
-/*02f3*/ 0x0802026cU,
-/*02f4*/ 0x1002026cU,
-/*02f5*/ 0x1802026cU,
-/*02f6*/ 0xffffffffU,
-/*02f7*/ 0x0002026dU,
-/*02f8*/ 0x0810026dU,
-/*02f9*/ 0x1805026dU,
-/*02fa*/ 0x0006026eU,
-/*02fb*/ 0x0805026eU,
-/*02fc*/ 0x1005026eU,
-/*02fd*/ 0x000e026fU,
-/*02fe*/ 0x1005026fU,
-/*02ff*/ 0x000e0270U,
-/*0300*/ 0x10050270U,
-/*0301*/ 0x000e0271U,
-/*0302*/ 0x10050271U,
-/*0303*/ 0x18010271U,
-/*0304*/ 0x00050272U,
-/*0305*/ 0x08050272U,
-/*0306*/ 0x100a0272U,
-/*0307*/ 0x000a0273U,
-/*0308*/ 0x10050273U,
-/*0309*/ 0x18050273U,
-/*030a*/ 0x000a0274U,
-/*030b*/ 0x100a0274U,
-/*030c*/ 0x00050275U,
-/*030d*/ 0x08050275U,
-/*030e*/ 0x100a0275U,
-/*030f*/ 0x000a0276U,
-/*0310*/ 0xffffffffU,
-/*0311*/ 0xffffffffU,
-/*0312*/ 0xffffffffU,
-/*0313*/ 0xffffffffU,
-/*0314*/ 0xffffffffU,
-/*0315*/ 0xffffffffU,
-/*0316*/ 0x10070276U,
-/*0317*/ 0x18070276U,
-/*0318*/ 0x00040277U,
-/*0319*/ 0x08040277U,
-/*031a*/ 0xffffffffU,
-/*031b*/ 0xffffffffU,
-/*031c*/ 0xffffffffU,
-/*031d*/ 0x10040277U,
-/*031e*/ 0x18080277U,
-/*031f*/ 0x00080278U,
-/*0320*/ 0x08040278U,
-/*0321*/ 0xffffffffU,
-/*0322*/ 0xffffffffU,
-/*0323*/ 0xffffffffU,
-/*0324*/ 0x10040278U,
-/*0325*/ 0xffffffffU,
-/*0326*/ 0xffffffffU,
-/*0327*/ 0xffffffffU,
-/*0328*/ 0x18040278U,
-/*0329*/ 0xffffffffU,
-/*032a*/ 0xffffffffU,
-/*032b*/ 0xffffffffU,
-/*032c*/ 0x00040279U,
-/*032d*/ 0x08050279U,
-/*032e*/ 0x10070279U,
-/*032f*/ 0x18080279U,
-/*0330*/ 0x0010027aU,
-/*0331*/ 0x1008027aU,
-/*0332*/ 0x0010027bU,
-/*0333*/ 0x1008027bU,
-/*0334*/ 0x0010027cU,
-/*0335*/ 0x1008027cU,
-/*0336*/ 0x1808027cU,
-/*0337*/ 0x0001027dU,
-/*0338*/ 0x0801027dU,
-/*0339*/ 0x1006027dU,
-/*033a*/ 0x1806027dU,
-/*033b*/ 0x0006027eU,
-/*033c*/ 0x0801027eU,
-/*033d*/ 0x1001027eU,
-/*033e*/ 0x1803027eU,
-/*033f*/ 0x000a027fU,
-/*0340*/ 0x100a027fU,
-/*0341*/ 0x000a0280U,
-/*0342*/ 0xffffffffU,
-/*0343*/ 0x100a0280U,
-/*0344*/ 0x00040281U,
-/*0345*/ 0x08010281U,
-/*0346*/ 0x10040281U,
-/*0347*/ 0xffffffffU,
-/*0348*/ 0xffffffffU,
-/*0349*/ 0xffffffffU,
-/*034a*/ 0xffffffffU,
-/*034b*/ 0xffffffffU,
-/*034c*/ 0xffffffffU,
-/*034d*/ 0x18070281U,
-/*034e*/ 0x00070282U,
-/*034f*/ 0x08050282U,
-/*0350*/ 0x10050282U,
-/*0351*/ 0xffffffffU,
-/*0352*/ 0xffffffffU,
-/*0353*/ 0xffffffffU,
-/*0354*/ 0x18040282U,
-/*0355*/ 0x00010283U,
-/*0356*/ 0x08010283U,
-/*0357*/ 0x10020283U,
-/*0358*/ 0x18080283U,
-/*0359*/ 0x00200284U,
-/*035a*/ 0x00200285U,
-/*035b*/ 0x00100286U,
-/*035c*/ 0x10020286U,
-/*035d*/ 0x18020286U,
-/*035e*/ 0x00020287U,
-/*035f*/ 0xffffffffU,
-/*0360*/ 0x08010287U,
-/*0361*/ 0x10010287U,
-/*0362*/ 0x18020287U,
-/*0363*/ 0x00080288U,
-/*0364*/ 0x08080288U,
-/*0365*/ 0x10080288U,
-/*0366*/ 0x18080288U,
-/*0367*/ 0x00080289U,
-/*0368*/ 0x08080289U,
-/*0369*/ 0xffffffffU,
-/*036a*/ 0x10080289U,
-/*036b*/ 0x18080289U,
-/*036c*/ 0x0008028aU,
-/*036d*/ 0x0808028aU,
-/*036e*/ 0x1008028aU,
-/*036f*/ 0x1808028aU,
-/*0370*/ 0xffffffffU,
-/*0371*/ 0x0008028bU,
-/*0372*/ 0x0808028bU,
-/*0373*/ 0x1008028bU,
-/*0374*/ 0x1808028bU,
-/*0375*/ 0x0008028cU,
-/*0376*/ 0x0808028cU,
-/*0377*/ 0xffffffffU,
-/*0378*/ 0x1008028cU,
-/*0379*/ 0x1808028cU,
-/*037a*/ 0x0008028dU,
-/*037b*/ 0x0808028dU,
-/*037c*/ 0x1008028dU,
-/*037d*/ 0x1808028dU,
-/*037e*/ 0x0008028eU,
-/*037f*/ 0xffffffffU,
-/*0380*/ 0x0808028eU,
-/*0381*/ 0x1008028eU,
-/*0382*/ 0x1808028eU,
-/*0383*/ 0x0008028fU,
-/*0384*/ 0x0808028fU,
-/*0385*/ 0x1008028fU,
-/*0386*/ 0xffffffffU,
-/*0387*/ 0x1808028fU,
-/*0388*/ 0x00080290U,
-/*0389*/ 0x08080290U,
-/*038a*/ 0x10080290U,
-/*038b*/ 0x18080290U,
-/*038c*/ 0x00080291U,
-/*038d*/ 0xffffffffU,
-/*038e*/ 0x08080291U,
-/*038f*/ 0x10080291U,
-/*0390*/ 0x18080291U,
-/*0391*/ 0x00080292U,
-/*0392*/ 0x08080292U,
-/*0393*/ 0x10080292U,
-/*0394*/ 0x18080292U,
-/*0395*/ 0xffffffffU,
-/*0396*/ 0x00080293U,
-/*0397*/ 0x08080293U,
-/*0398*/ 0x10080293U,
-/*0399*/ 0x18080293U,
-/*039a*/ 0x00080294U,
-/*039b*/ 0x08080294U,
-/*039c*/ 0xffffffffU,
-/*039d*/ 0x10080294U,
-/*039e*/ 0x18080294U,
-/*039f*/ 0x00080295U,
-/*03a0*/ 0x08080295U,
-/*03a1*/ 0x10080295U,
-/*03a2*/ 0x18080295U,
-/*03a3*/ 0xffffffffU,
-/*03a4*/ 0x00080296U,
-/*03a5*/ 0x08080296U,
-/*03a6*/ 0x10080296U,
-/*03a7*/ 0x18080296U,
-/*03a8*/ 0x00080297U,
-/*03a9*/ 0x08080297U,
-/*03aa*/ 0x10080297U,
-/*03ab*/ 0xffffffffU,
-/*03ac*/ 0x18080297U,
-/*03ad*/ 0x00080298U,
-/*03ae*/ 0x08080298U,
-/*03af*/ 0x10080298U,
-/*03b0*/ 0x18080298U,
-/*03b1*/ 0x00080299U,
-/*03b2*/ 0xffffffffU,
-/*03b3*/ 0x08080299U,
-/*03b4*/ 0x10080299U,
-/*03b5*/ 0x18080299U,
-/*03b6*/ 0x0008029aU,
-/*03b7*/ 0x0808029aU,
-/*03b8*/ 0x1008029aU,
-/*03b9*/ 0xffffffffU,
-/*03ba*/ 0x1808029aU,
-/*03bb*/ 0x0002029bU,
-/*03bc*/ 0x0803029bU,
-/*03bd*/ 0x100a029bU,
-/*03be*/ 0x000a029cU,
-/*03bf*/ 0x100a029cU,
-/*03c0*/ 0x0005029dU,
-/*03c1*/ 0x0808029dU,
-/*03c2*/ 0x1008029dU,
-/*03c3*/ 0x1808029dU,
-/*03c4*/ 0x0006029eU,
-/*03c5*/ 0x0806029eU,
-/*03c6*/ 0x0011029fU,
-/*03c7*/ 0x1808029fU,
-/*03c8*/ 0x000402a0U,
-/*03c9*/ 0x080602a0U,
-/*03ca*/ 0xffffffffU,
-/*03cb*/ 0x100602a0U,
-/*03cc*/ 0x180802a0U,
-/*03cd*/ 0xffffffffU,
-/*03ce*/ 0x000802a1U,
-/*03cf*/ 0x080802a1U,
-/*03d0*/ 0x100802a1U,
-/*03d1*/ 0x180602a1U,
-/*03d2*/ 0x000602a2U,
-/*03d3*/ 0x081102a2U,
-/*03d4*/ 0x000802a3U,
-/*03d5*/ 0x080402a3U,
-/*03d6*/ 0x100602a3U,
-/*03d7*/ 0xffffffffU,
-/*03d8*/ 0x180602a3U,
-/*03d9*/ 0x000802a4U,
-/*03da*/ 0xffffffffU,
-/*03db*/ 0x080802a4U,
-/*03dc*/ 0x100802a4U,
-/*03dd*/ 0x180802a4U,
-/*03de*/ 0x000602a5U,
-/*03df*/ 0x080602a5U,
-/*03e0*/ 0x001102a6U,
-/*03e1*/ 0x180802a6U,
-/*03e2*/ 0x000402a7U,
-/*03e3*/ 0x080602a7U,
-/*03e4*/ 0xffffffffU,
-/*03e5*/ 0x100602a7U,
-/*03e6*/ 0x180802a7U,
-/*03e7*/ 0xffffffffU,
-/*03e8*/ 0x000402a8U,
-/*03e9*/ 0x080402a8U,
-/*03ea*/ 0x100402a8U,
-/*03eb*/ 0x180402a8U,
-/*03ec*/ 0x000402a9U,
-/*03ed*/ 0x080402a9U,
-/*03ee*/ 0x100402a9U,
-/*03ef*/ 0x180402a9U,
-/*03f0*/ 0x000402aaU,
-/*03f1*/ 0x080402aaU,
-/*03f2*/ 0x100402aaU,
-/*03f3*/ 0x180402aaU,
-/*03f4*/ 0x000402abU,
-/*03f5*/ 0x080402abU,
-/*03f6*/ 0x100402abU,
-/*03f7*/ 0x180402abU,
-/*03f8*/ 0x000402acU,
-/*03f9*/ 0x080402acU,
-/*03fa*/ 0x100402acU,
-/*03fb*/ 0x180402acU,
-/*03fc*/ 0x001202adU,
-/*03fd*/ 0x001102aeU,
-/*03fe*/ 0x001202afU,
-/*03ff*/ 0x002002b0U,
-/*0400*/ 0x002002b1U,
-/*0401*/ 0x002002b2U,
-/*0402*/ 0x002002b3U,
-/*0403*/ 0x002002b4U,
-/*0404*/ 0x002002b5U,
-/*0405*/ 0x002002b6U,
-/*0406*/ 0x002002b7U,
-/*0407*/ 0x002002b8U,
-/*0408*/ 0x000202b9U,
-/*0409*/ 0x080502b9U,
-/*040a*/ 0x100502b9U,
-/*040b*/ 0x180102b9U,
-/*040c*/ 0x000402baU,
-/*040d*/ 0x080402baU,
-/*040e*/ 0x100402baU,
-/*040f*/ 0x180402baU,
-/*0410*/ 0x000402bbU,
-/*0411*/ 0x080402bbU,
-/*0412*/ 0x100402bbU,
-/*0413*/ 0x180402bbU,
-/*0414*/ 0xffffffffU,
-/*0415*/ 0xffffffffU,
-/*0416*/ 0xffffffffU,
-/*0417*/ 0xffffffffU,
-/*0418*/ 0xffffffffU,
-/*0419*/ 0xffffffffU,
-/*041a*/ 0x000402bcU,
-/*041b*/ 0x080402bcU,
-/*041c*/ 0x100402bcU,
-/*041d*/ 0x180402bcU,
-/*041e*/ 0x000402bdU,
-/*041f*/ 0x080402bdU,
-/*0420*/ 0x100402bdU,
-/*0421*/ 0x180402bdU,
-/*0422*/ 0x000102beU,
-/*0423*/ 0x080202beU,
-/*0424*/ 0x100202beU,
-/*0425*/ 0x180202beU,
-/*0426*/ 0x000202bfU,
-/*0427*/ 0x080102bfU,
-/*0428*/ 0x100402bfU,
-/*0429*/ 0x001002c0U,
-/*042a*/ 0x002002c1U,
-/*042b*/ 0x001002c2U,
-/*042c*/ 0x002002c3U,
-/*042d*/ 0x001002c4U,
-/*042e*/ 0x002002c5U,
-/*042f*/ 0x000702c6U,
-/*0430*/ 0x080102c6U,
-/*0431*/ 0x100202c6U,
-/*0432*/ 0x180602c6U,
-/*0433*/ 0x000102c7U,
-/*0434*/ 0x080102c7U,
-/*0435*/ 0x002002c8U,
-/*0436*/ 0x000202c9U,
-/*0437*/ 0x002002caU,
-/*0438*/ 0x002002cbU,
-/*0439*/ 0x000c02ccU,
-/*043a*/ 0x100c02ccU,
-/*043b*/ 0x002002cdU,
-/*043c*/ 0x000302ceU,
-/*043d*/ 0x002002cfU,
-/*043e*/ 0x000302d0U,
-/*043f*/ 0x002002d1U,
-/*0440*/ 0x000302d2U,
-/*0441*/ 0x002002d3U,
-/*0442*/ 0x000302d4U,
-/*0443*/ 0x002002d5U,
-/*0444*/ 0x000302d6U,
-/*0445*/ 0x002002d7U,
-/*0446*/ 0x000302d8U,
-/*0447*/ 0x002002d9U,
-/*0448*/ 0x000302daU,
-/*0449*/ 0x002002dbU,
-/*044a*/ 0x000302dcU,
-/*044b*/ 0x002002ddU,
-/*044c*/ 0x000302deU,
-/*044d*/ 0x002002dfU,
-/*044e*/ 0x000302e0U,
-/*044f*/ 0x080302e0U,
-/*0450*/ 0x100202e0U,
-/*0451*/ 0x180202e0U,
-/*0452*/ 0x002002e1U,
-/*0453*/ 0x002002e2U,
-/*0454*/ 0x002002e3U,
-/*0455*/ 0x002002e4U,
-/*0456*/ 0x000402e5U,
-/*0457*/ 0x001e02e6U,
-/*0458*/ 0x001e02e7U,
-/*0459*/ 0x001e02e8U,
-/*045a*/ 0x001e02e9U,
-/*045b*/ 0x001e02eaU,
-/*045c*/ 0x001e02ebU,
-/*045d*/ 0x001e02ecU,
-/*045e*/ 0x001e02edU,
-/*045f*/ 0x000402eeU,
-/*0460*/ 0xffffffffU,
-/*0461*/ 0xffffffffU,
-/*0462*/ 0xffffffffU,
-/*0463*/ 0xffffffffU,
-/*0464*/ 0x080402eeU,
-/*0465*/ 0x100102eeU,
-/*0466*/ 0x180802eeU,
-/*0467*/ 0x000402efU,
-/*0468*/ 0x080102efU,
-/*0469*/ 0x100802efU,
-/*046a*/ 0x180402efU,
-/*046b*/ 0x000102f0U,
-/*046c*/ 0x080802f0U,
-/*046d*/ 0x100402f0U,
-/*046e*/ 0x180102f0U,
-/*046f*/ 0x000802f1U,
-/*0470*/ 0x080402f1U,
-/*0471*/ 0x100102f1U,
-/*0472*/ 0x180802f1U,
-/*0473*/ 0x000402f2U,
-/*0474*/ 0x080102f2U,
-/*0475*/ 0x100802f2U,
-/*0476*/ 0x180402f2U,
-/*0477*/ 0x000102f3U,
-/*0478*/ 0x080802f3U,
-/*0479*/ 0x100402f3U,
-/*047a*/ 0x180102f3U,
-/*047b*/ 0x000802f4U,
-/*047c*/ 0x080802f4U,
-/*047d*/ 0x100102f4U,
-/*047e*/ 0x180502f4U,
-/*047f*/ 0xffffffffU,
-/*0480*/ 0xffffffffU,
-/*0481*/ 0xffffffffU,
-/*0482*/ 0xffffffffU,
-/*0483*/ 0xffffffffU,
-/*0484*/ 0xffffffffU,
-/*0485*/ 0xffffffffU,
-/*0486*/ 0xffffffffU,
-/*0487*/ 0xffffffffU,
-/*0488*/ 0xffffffffU,
-/*0489*/ 0xffffffffU,
-/*048a*/ 0xffffffffU,
-/*048b*/ 0xffffffffU,
-/*048c*/ 0xffffffffU,
-/*048d*/ 0xffffffffU,
-/*048e*/ 0xffffffffU,
-/*048f*/ 0xffffffffU,
-/*0490*/ 0xffffffffU,
-/*0491*/ 0xffffffffU,
-/*0492*/ 0xffffffffU,
-/*0493*/ 0xffffffffU,
-/*0494*/ 0xffffffffU,
- },
- {
-/*0000*/ 0x00200800U,
-/*0001*/ 0x00040801U,
-/*0002*/ 0x080b0801U,
-/*0003*/ 0x000a0802U,
-/*0004*/ 0x10020802U,
-/*0005*/ 0x18010802U,
-/*0006*/ 0x00060803U,
-/*0007*/ 0x08060803U,
-/*0008*/ 0x10060803U,
-/*0009*/ 0x18060803U,
-/*000a*/ 0x00060804U,
-/*000b*/ 0x08060804U,
-/*000c*/ 0x10050804U,
-/*000d*/ 0x18060804U,
-/*000e*/ 0x00060805U,
-/*000f*/ 0x08040805U,
-/*0010*/ 0x10030805U,
-/*0011*/ 0x00180806U,
-/*0012*/ 0x18030806U,
-/*0013*/ 0x00180807U,
-/*0014*/ 0x18020807U,
-/*0015*/ 0x0801085eU,
-/*0016*/ 0x00020808U,
-/*0017*/ 0x08010808U,
-/*0018*/ 0x10010808U,
-/*0019*/ 0x18020808U,
-/*001a*/ 0x00050809U,
-/*001b*/ 0x08050809U,
-/*001c*/ 0x10040809U,
-/*001d*/ 0xffffffffU,
-/*001e*/ 0x18040809U,
-/*001f*/ 0x0002080aU,
-/*0020*/ 0x0805080aU,
-/*0021*/ 0x1009080aU,
-/*0022*/ 0x0001080bU,
-/*0023*/ 0x0020080cU,
-/*0024*/ 0x001c080dU,
-/*0025*/ 0x0001080eU,
-/*0026*/ 0x0807080eU,
-/*0027*/ 0x1009080eU,
-/*0028*/ 0x000a080fU,
-/*0029*/ 0x1005080fU,
-/*002a*/ 0x1801080fU,
-/*002b*/ 0x10010810U,
-/*002c*/ 0x18020810U,
-/*002d*/ 0x00090810U,
-/*002e*/ 0x00090811U,
-/*002f*/ 0x10020811U,
-/*0030*/ 0x00200812U,
-/*0031*/ 0x00010813U,
-/*0032*/ 0x08020813U,
-/*0033*/ 0x00200814U,
-/*0034*/ 0x00200815U,
-/*0035*/ 0x00200816U,
-/*0036*/ 0x00200817U,
-/*0037*/ 0xffffffffU,
-/*0038*/ 0xffffffffU,
-/*0039*/ 0xffffffffU,
-/*003a*/ 0xffffffffU,
-/*003b*/ 0x00030818U,
-/*003c*/ 0x08010818U,
-/*003d*/ 0x10040818U,
-/*003e*/ 0x18030818U,
-/*003f*/ 0x00040819U,
-/*0040*/ 0x08040819U,
-/*0041*/ 0x10040819U,
-/*0042*/ 0x18040819U,
-/*0043*/ 0x0001081aU,
-/*0044*/ 0x0801081aU,
-/*0045*/ 0x1006081aU,
-/*0046*/ 0x1804081aU,
-/*0047*/ 0x0008081bU,
-/*0048*/ 0x0806081bU,
-/*0049*/ 0x1004081bU,
-/*004a*/ 0x1806081bU,
-/*004b*/ 0x0004081cU,
-/*004c*/ 0x0802081cU,
-/*004d*/ 0x1005081cU,
-/*004e*/ 0x1808081cU,
-/*004f*/ 0xffffffffU,
-/*0050*/ 0x0006081dU,
-/*0051*/ 0x0803081dU,
-/*0052*/ 0x100b081dU,
-/*0053*/ 0x0004081eU,
-/*0054*/ 0x0804081eU,
-/*0055*/ 0x1004081eU,
-/*0056*/ 0x1801081eU,
-/*0057*/ 0xffffffffU,
-/*0058*/ 0x0009081fU,
-/*0059*/ 0x00200820U,
-/*005a*/ 0x00200821U,
-/*005b*/ 0x00200822U,
-/*005c*/ 0x00200823U,
-/*005d*/ 0x00100824U,
-/*005e*/ 0xffffffffU,
-/*005f*/ 0x10010824U,
-/*0060*/ 0x18060824U,
-/*0061*/ 0x00080825U,
-/*0062*/ 0x00200826U,
-/*0063*/ 0x00100827U,
-/*0064*/ 0x100b0827U,
-/*0065*/ 0x00070828U,
-/*0066*/ 0x08070828U,
-/*0067*/ 0x10090828U,
-/*0068*/ 0x00090829U,
-/*0069*/ 0x100b0829U,
-/*006a*/ 0x0007082aU,
-/*006b*/ 0x0808082aU,
-/*006c*/ 0x1009082aU,
-/*006d*/ 0x0003082bU,
-/*006e*/ 0x080a082bU,
-/*006f*/ 0x000a082cU,
-/*0070*/ 0x0011082dU,
-/*0071*/ 0x000a082eU,
-/*0072*/ 0x100a082eU,
-/*0073*/ 0x0010082fU,
-/*0074*/ 0x100e082fU,
-/*0075*/ 0x000e0830U,
-/*0076*/ 0x00120831U,
-/*0077*/ 0x000a0832U,
-/*0078*/ 0x100a0832U,
-/*0079*/ 0x00020833U,
-/*007a*/ 0x00200834U,
-/*007b*/ 0x000b0835U,
-/*007c*/ 0x100b0835U,
-/*007d*/ 0x00200836U,
-/*007e*/ 0x00130837U,
-/*007f*/ 0x00200838U,
-/*0080*/ 0x00200839U,
-/*0081*/ 0x0008083aU,
-/*0082*/ 0x0801083aU,
-/*0083*/ 0x1001083aU,
-/*0084*/ 0x1801083aU,
-/*0085*/ 0x0008083bU,
-/*0086*/ 0x080c083bU,
-/*0087*/ 0x000c083cU,
-/*0088*/ 0x100c083cU,
-/*0089*/ 0x000c083dU,
-/*008a*/ 0x100c083dU,
-/*008b*/ 0x000c083eU,
-/*008c*/ 0x100c083eU,
-/*008d*/ 0x000c083fU,
-/*008e*/ 0x100c083fU,
-/*008f*/ 0x000c0840U,
-/*0090*/ 0x100c0840U,
-/*0091*/ 0x000b0841U,
-/*0092*/ 0x10090841U,
-/*0093*/ 0x00010842U,
-/*0094*/ 0x000b0843U,
-/*0095*/ 0x100b0843U,
-/*0096*/ 0x000b0844U,
-/*0097*/ 0x100b0844U,
-/*0098*/ 0x000b0845U,
-/*0099*/ 0x100b0845U,
-/*009a*/ 0x000b0846U,
-/*009b*/ 0x100b0846U,
-/*009c*/ 0x000b0847U,
-/*009d*/ 0x100a0847U,
-/*009e*/ 0x00020848U,
-/*009f*/ 0x080a0848U,
-/*00a0*/ 0x000a0849U,
-/*00a1*/ 0x100a0849U,
-/*00a2*/ 0x000a084aU,
-/*00a3*/ 0x100a084aU,
-/*00a4*/ 0x000a084bU,
-/*00a5*/ 0x100a084bU,
-/*00a6*/ 0x000a084cU,
-/*00a7*/ 0x100a084cU,
-/*00a8*/ 0x000a084dU,
-/*00a9*/ 0x100a084dU,
-/*00aa*/ 0x000a084eU,
-/*00ab*/ 0x100a084eU,
-/*00ac*/ 0x000a084fU,
-/*00ad*/ 0x100a084fU,
-/*00ae*/ 0x000a0850U,
-/*00af*/ 0x100a0850U,
-/*00b0*/ 0x000a0851U,
-/*00b1*/ 0x100a0851U,
-/*00b2*/ 0x000a0852U,
-/*00b3*/ 0x100a0852U,
-/*00b4*/ 0x000a0853U,
-/*00b5*/ 0x100a0853U,
-/*00b6*/ 0x000a0854U,
-/*00b7*/ 0x100a0854U,
-/*00b8*/ 0x000a0855U,
-/*00b9*/ 0x100a0855U,
-/*00ba*/ 0x000a0856U,
-/*00bb*/ 0x10040856U,
-/*00bc*/ 0x18030856U,
-/*00bd*/ 0x000a0857U,
-/*00be*/ 0x100a0857U,
-/*00bf*/ 0x00010858U,
-/*00c0*/ 0x080a0858U,
-/*00c1*/ 0x18040858U,
-/*00c2*/ 0x000b0859U,
-/*00c3*/ 0x100a0859U,
-/*00c4*/ 0x0003085aU,
-/*00c5*/ 0x0008085bU,
-/*00c6*/ 0x0808085bU,
-/*00c7*/ 0x1008085bU,
-/*00c8*/ 0x1808085bU,
-/*00c9*/ 0x0008085cU,
-/*00ca*/ 0x0808085cU,
-/*00cb*/ 0x1008085cU,
-/*00cc*/ 0x1801085cU,
-/*00cd*/ 0x0008085dU,
-/*00ce*/ 0x0808085dU,
-/*00cf*/ 0x1002085dU,
-/*00d0*/ 0x1802085dU,
-/*00d1*/ 0x0005085eU,
-/*00d2*/ 0x1005085eU,
-/*00d3*/ 0x1805085eU,
-/*00d4*/ 0x0004085fU,
-/*00d5*/ 0x080b085fU,
-/*00d6*/ 0x1806085fU,
-/*00d7*/ 0x00080860U,
-/*00d8*/ 0x08080860U,
-/*00d9*/ 0x10040860U,
-/*00da*/ 0x18040860U,
-/*00db*/ 0x00060861U,
-/*00dc*/ 0x08040861U,
-/*00dd*/ 0x10050861U,
-/*00de*/ 0x000a0862U,
-/*00df*/ 0x100a0862U,
-/*00e0*/ 0x00080863U,
-/*00e1*/ 0x08010863U,
-/*00e2*/ 0x10040863U,
-/*00e3*/ 0x00020864U,
-/*00e4*/ 0x08030864U,
-/*00e5*/ 0x00050a00U,
-/*00e6*/ 0x08050a00U,
-/*00e7*/ 0x10050a00U,
-/*00e8*/ 0x18050a00U,
-/*00e9*/ 0x00050a01U,
-/*00ea*/ 0x08050a01U,
-/*00eb*/ 0x100b0a01U,
-/*00ec*/ 0x00010a02U,
-/*00ed*/ 0x08030a02U,
-/*00ee*/ 0x00200a03U,
-/*00ef*/ 0x00100a04U,
-/*00f0*/ 0x10040a04U,
-/*00f1*/ 0x000b0a05U,
-/*00f2*/ 0x10070a05U,
-/*00f3*/ 0x00090a06U,
-/*00f4*/ 0x10030a06U,
-/*00f5*/ 0x18030a06U,
-/*00f6*/ 0x00010a07U,
-/*00f7*/ 0x08010a07U,
-/*00f8*/ 0x10070a07U,
-/*00f9*/ 0x18070a07U,
-/*00fa*/ 0x00050a08U,
-/*00fb*/ 0x08010a08U,
-/*00fc*/ 0x10020a08U,
-/*00fd*/ 0x18030a08U,
-/*00fe*/ 0x00010a09U,
-/*00ff*/ 0x080f0a09U,
-/*0100*/ 0x00200a0aU,
-/*0101*/ 0x00200a0bU,
-/*0102*/ 0x000b0a0cU,
-/*0103*/ 0x100b0a0cU,
-/*0104*/ 0x000b0a0dU,
-/*0105*/ 0x00180a0eU,
-/*0106*/ 0x00180a0fU,
-/*0107*/ 0xffffffffU,
-/*0108*/ 0xffffffffU,
-/*0109*/ 0xffffffffU,
-/*010a*/ 0xffffffffU,
-/*010b*/ 0xffffffffU,
-/*010c*/ 0x18020a0fU,
-/*010d*/ 0x00020a10U,
-/*010e*/ 0x08040a10U,
-/*010f*/ 0x10040a10U,
-/*0110*/ 0x18010a10U,
-/*0111*/ 0x00010a11U,
-/*0112*/ 0x08010a11U,
-/*0113*/ 0x10030a11U,
-/*0114*/ 0x00200a12U,
-/*0115*/ 0x00200a13U,
-/*0116*/ 0xffffffffU,
-/*0117*/ 0x00140a14U,
-/*0118*/ 0x00140a15U,
-/*0119*/ 0x00140a16U,
-/*011a*/ 0x00140a17U,
-/*011b*/ 0x00140a18U,
-/*011c*/ 0x00140a19U,
-/*011d*/ 0x00140a1aU,
-/*011e*/ 0x00140a1bU,
-/*011f*/ 0x001e0a1cU,
-/*0120*/ 0x000a0a1dU,
-/*0121*/ 0x10060a1dU,
-/*0122*/ 0x18060a1dU,
-/*0123*/ 0x00060a1eU,
-/*0124*/ 0x08060a1eU,
-/*0125*/ 0x10060a1eU,
-/*0126*/ 0x00080a1fU,
-/*0127*/ 0x080b0a1fU,
-/*0128*/ 0x000b0a20U,
-/*0129*/ 0x100b0a20U,
-/*012a*/ 0x000b0a21U,
-/*012b*/ 0x100b0a21U,
-/*012c*/ 0x000b0a22U,
-/*012d*/ 0x10040a22U,
-/*012e*/ 0x000b0a23U,
-/*012f*/ 0x10060a23U,
-/*0130*/ 0x18080a23U,
-/*0131*/ 0x00080a24U,
-/*0132*/ 0x08040a24U,
-/*0133*/ 0x00020b80U,
-/*0134*/ 0x00010b81U,
-/*0135*/ 0x08010b81U,
-/*0136*/ 0x10020b81U,
-/*0137*/ 0x18050b81U,
-/*0138*/ 0x00050b82U,
-/*0139*/ 0x08050b82U,
-/*013a*/ 0x10050b82U,
-/*013b*/ 0x000b0b83U,
-/*013c*/ 0x10050b83U,
-/*013d*/ 0x18010b83U,
-/*013e*/ 0x00010b84U,
-/*013f*/ 0x08010b84U,
-/*0140*/ 0x10010b84U,
-/*0141*/ 0x18010b84U,
-/*0142*/ 0x00040b85U,
-/*0143*/ 0x080b0b85U,
-/*0144*/ 0x000b0b86U,
-/*0145*/ 0x100b0b86U,
-/*0146*/ 0x00040b87U,
-/*0147*/ 0x080b0b87U,
-/*0148*/ 0x18040b87U,
-/*0149*/ 0x00010b88U,
-/*014a*/ 0x08010b88U,
-/*014b*/ 0x10010b88U,
-/*014c*/ 0x00200b89U,
-/*014d*/ 0x00200b8aU,
-/*014e*/ 0x00080b8bU,
-/*014f*/ 0x080a0b8bU,
-/*0150*/ 0x18050b8bU,
-/*0151*/ 0x000b0b8cU,
-/*0152*/ 0x10030b8cU,
-/*0153*/ 0x18030b8cU,
-/*0154*/ 0x00010b8dU,
-/*0155*/ 0x08020b8dU,
-/*0156*/ 0x10010b8dU,
-/*0157*/ 0x18010b8dU,
-/*0158*/ 0x00010b8eU,
-/*0159*/ 0xffffffffU,
-/*015a*/ 0x08010b8eU,
-/*015b*/ 0x18040b8eU,
-/*015c*/ 0x00040b8fU,
-/*015d*/ 0x08040b8fU,
-/*015e*/ 0x10040b8fU,
-/*015f*/ 0x18010b8fU,
-/*0160*/ 0x00010b90U,
-/*0161*/ 0x08010b90U,
-/*0162*/ 0x00200b91U,
-/*0163*/ 0x00200b92U,
-/*0164*/ 0x00200b93U,
-/*0165*/ 0x00200b94U,
-/*0166*/ 0xffffffffU,
-/*0167*/ 0x10010b8eU,
-/*0168*/ 0x000d0b96U,
-/*0169*/ 0x100d0b96U,
-/*016a*/ 0x000d0b97U,
-/*016b*/ 0x00050b98U,
-/*016c*/ 0x00010b99U,
-/*016d*/ 0x080e0b99U,
-/*016e*/ 0x000e0b9aU,
-/*016f*/ 0x100e0b9aU,
-/*0170*/ 0x000e0b9bU,
-/*0171*/ 0x100e0b9bU,
-/*0172*/ 0x00040b9cU,
-/*0173*/ 0x08040b9cU,
-/*0174*/ 0x10040b9cU,
-/*0175*/ 0x18040b9cU,
-/*0176*/ 0x00040b9dU,
-/*0177*/ 0x080b0b9dU,
-/*0178*/ 0x000b0b9eU,
-/*0179*/ 0x100b0b9eU,
-/*017a*/ 0x000b0b9fU,
-/*017b*/ 0x00040ba0U,
-/*017c*/ 0x08040ba0U,
-/*017d*/ 0x10040ba0U,
-/*017e*/ 0x18040ba0U,
-/*017f*/ 0x000d0ba1U,
-/*0180*/ 0x100d0ba1U,
-/*0181*/ 0x000d0ba2U,
-/*0182*/ 0x10100ba2U,
-/*0183*/ 0x00080b95U,
-/*0184*/ 0x08080b95U,
-/*0185*/ 0x00100ba3U,
-/*0186*/ 0x10100ba3U,
-/*0187*/ 0x00100ba4U,
-/*0188*/ 0x10100ba4U,
-/*0189*/ 0x00100ba5U,
-/*018a*/ 0x10030ba5U,
-/*018b*/ 0x18040ba5U,
-/*018c*/ 0x00010ba6U,
-/*018d*/ 0x08080ba6U,
-/*018e*/ 0x10010ba6U,
-/*018f*/ 0x000a0ba7U,
-/*0190*/ 0x10010ba7U,
-/*0191*/ 0x00140ba8U,
-/*0192*/ 0x000b0ba9U,
-/*0193*/ 0x100c0ba9U,
-/*0194*/ 0x00120baaU,
-/*0195*/ 0x00140babU,
-/*0196*/ 0x00120bacU,
-/*0197*/ 0x00110badU,
-/*0198*/ 0x00110baeU,
-/*0199*/ 0x00120bafU,
-/*019a*/ 0x00120bb0U,
-/*019b*/ 0x00120bb1U,
-/*019c*/ 0x00120bb2U,
-/*019d*/ 0x00120bb3U,
-/*019e*/ 0x00120bb4U,
-/*019f*/ 0x00120bb5U,
-/*01a0*/ 0x00120bb6U,
-/*01a1*/ 0x00120bb7U,
-/*01a2*/ 0x00120bb8U,
-/*01a3*/ 0x000e0bb9U,
-/*01a4*/ 0x100d0bb9U,
-/*01a5*/ 0x00200bbaU,
-/*01a6*/ 0x00170bbbU,
-/*01a7*/ 0x000d0bbcU,
-/*01a8*/ 0x10010bbcU,
-/*01a9*/ 0x18010bbcU,
-/*01aa*/ 0x00200bbdU,
-/*01ab*/ 0x00080bbeU,
-/*01ac*/ 0x08030bbeU,
-/*01ad*/ 0x10030bbeU,
-/*01ae*/ 0x00180bbfU,
-/*01af*/ 0x00180bc0U,
-/*01b0*/ 0x18070bc0U,
-/*01b1*/ 0x00070bc1U,
-/*01b2*/ 0x08080bc1U,
-/*01b3*/ 0x10080bc1U,
-/*01b4*/ 0x18080bc1U,
-/*01b5*/ 0x00010bc2U,
-/*01b6*/ 0x08010bc2U,
-/*01b7*/ 0x00200bc3U,
-/*01b8*/ 0x00070bc4U,
-/*01b9*/ 0x08140bc4U,
-/*01ba*/ 0x00140bc5U,
-/*01bb*/ 0x00190bc6U,
-/*01bc*/ 0x00170bc7U,
-/*01bd*/ 0x00110bc8U,
-/*01be*/ 0x00110bc9U,
-/*01bf*/ 0x00100bcaU,
-/*01c0*/ 0x10010bcaU,
-/*01c1*/ 0x18010bcaU,
-/*01c2*/ 0x00020bcbU,
-/*01c3*/ 0x08040bcbU,
-/*01c4*/ 0x10090bcbU,
-/*01c5*/ 0x00070bccU,
-/*01c6*/ 0x08040bccU,
-/*01c7*/ 0x00200bcdU,
-/*01c8*/ 0x00010bceU,
-/*01c9*/ 0x08020bceU,
-/*01ca*/ 0x10060bceU,
-/*01cb*/ 0x00100bcfU,
-/*01cc*/ 0x10010bcfU,
-/*01cd*/ 0x00200bd0U,
-/*01ce*/ 0x00080bd1U,
-/*01cf*/ 0x08010bd1U,
-/*01d0*/ 0x10050bd1U,
-/*01d1*/ 0x18030bd1U,
-/*01d2*/ 0x00020bd2U,
-/*01d3*/ 0xffffffffU,
-/*01d4*/ 0x00200bd3U,
-/*01d5*/ 0x000b0bd4U,
-/*01d6*/ 0xffffffffU,
-/*01d7*/ 0x10030bd4U,
-/*01d8*/ 0x18080bd4U,
-/*01d9*/ 0x00020bd5U,
-/*01da*/ 0x080c0bd5U,
-/*01db*/ 0x18040bd5U,
-/*01dc*/ 0x00010bd6U,
-/*01dd*/ 0x08050bd6U,
-/*01de*/ 0x00010200U,
-/*01df*/ 0x08040200U,
-/*01e0*/ 0x10100200U,
-/*01e1*/ 0x00010201U,
-/*01e2*/ 0x08010201U,
-/*01e3*/ 0x10010201U,
-/*01e4*/ 0x18010201U,
-/*01e5*/ 0x00100202U,
-/*01e6*/ 0x10080202U,
-/*01e7*/ 0x18010202U,
-/*01e8*/ 0x00200203U,
-/*01e9*/ 0x00200204U,
-/*01ea*/ 0x00200205U,
-/*01eb*/ 0x00200206U,
-/*01ec*/ 0x00020207U,
-/*01ed*/ 0x08010207U,
-/*01ee*/ 0x10010207U,
-/*01ef*/ 0x00200208U,
-/*01f0*/ 0x00140209U,
-/*01f1*/ 0x0020020aU,
-/*01f2*/ 0x0014020bU,
-/*01f3*/ 0x0020020cU,
-/*01f4*/ 0x0014020dU,
-/*01f5*/ 0x0014020eU,
-/*01f6*/ 0x0020020fU,
-/*01f7*/ 0x00200210U,
-/*01f8*/ 0x00200211U,
-/*01f9*/ 0x00200212U,
-/*01fa*/ 0x00140213U,
-/*01fb*/ 0x00200214U,
-/*01fc*/ 0x00200215U,
-/*01fd*/ 0x00200216U,
-/*01fe*/ 0x00200217U,
-/*01ff*/ 0x00140218U,
-/*0200*/ 0x00200219U,
-/*0201*/ 0x0020021aU,
-/*0202*/ 0x0020021bU,
-/*0203*/ 0x0020021cU,
-/*0204*/ 0x0009021dU,
-/*0205*/ 0x1001021dU,
-/*0206*/ 0x0020021eU,
-/*0207*/ 0x0005021fU,
-/*0208*/ 0x0801021fU,
-/*0209*/ 0x1008021fU,
-/*020a*/ 0x1808021fU,
-/*020b*/ 0x001e0220U,
-/*020c*/ 0x001e0221U,
-/*020d*/ 0x001e0222U,
-/*020e*/ 0x001e0223U,
-/*020f*/ 0x001e0224U,
-/*0210*/ 0x001e0225U,
-/*0211*/ 0x001e0226U,
-/*0212*/ 0x001e0227U,
-/*0213*/ 0x001e0228U,
-/*0214*/ 0x001e0229U,
-/*0215*/ 0x001e022aU,
-/*0216*/ 0x001e022bU,
-/*0217*/ 0x001e022cU,
-/*0218*/ 0x001e022dU,
-/*0219*/ 0x001e022eU,
-/*021a*/ 0x001e022fU,
-/*021b*/ 0x00010230U,
-/*021c*/ 0x08010230U,
-/*021d*/ 0x10010230U,
-/*021e*/ 0x18040230U,
-/*021f*/ 0x00080231U,
-/*0220*/ 0x08080231U,
-/*0221*/ 0x10080231U,
-/*0222*/ 0x18040231U,
-/*0223*/ 0x00070232U,
-/*0224*/ 0x08060232U,
-/*0225*/ 0x10070232U,
-/*0226*/ 0x18070232U,
-/*0227*/ 0x00060233U,
-/*0228*/ 0x08070233U,
-/*0229*/ 0x10070233U,
-/*022a*/ 0x18060233U,
-/*022b*/ 0x00070234U,
-/*022c*/ 0x08020234U,
-/*022d*/ 0x10010234U,
-/*022e*/ 0x18010234U,
-/*022f*/ 0x000a0235U,
-/*0230*/ 0x00140236U,
-/*0231*/ 0x000a0237U,
-/*0232*/ 0x00140238U,
-/*0233*/ 0x000a0239U,
-/*0234*/ 0x0014023aU,
-/*0235*/ 0xffffffffU,
-/*0236*/ 0xffffffffU,
-/*0237*/ 0x0005023bU,
-/*0238*/ 0x0001023cU,
-/*0239*/ 0x1001023cU,
-/*023a*/ 0x1801023cU,
-/*023b*/ 0x0001023dU,
-/*023c*/ 0x0801023dU,
-/*023d*/ 0x1001023dU,
-/*023e*/ 0x1801023dU,
-/*023f*/ 0x0002023eU,
-/*0240*/ 0x0802023eU,
-/*0241*/ 0x1002023eU,
-/*0242*/ 0x1802023eU,
-/*0243*/ 0x0002023fU,
-/*0244*/ 0x0803023fU,
-/*0245*/ 0x1001023fU,
-/*0246*/ 0x1801023fU,
-/*0247*/ 0x00010240U,
-/*0248*/ 0x08010240U,
-/*0249*/ 0x10010240U,
-/*024a*/ 0x18020240U,
-/*024b*/ 0x00010241U,
-/*024c*/ 0x08010241U,
-/*024d*/ 0x10010241U,
-/*024e*/ 0x18020241U,
-/*024f*/ 0x00010242U,
-/*0250*/ 0x08010242U,
-/*0251*/ 0x10010242U,
-/*0252*/ 0x18020242U,
-/*0253*/ 0x00010243U,
-/*0254*/ 0x08010243U,
-/*0255*/ 0x10010243U,
-/*0256*/ 0x18020243U,
-/*0257*/ 0xffffffffU,
-/*0258*/ 0x00010244U,
-/*0259*/ 0x08010244U,
-/*025a*/ 0x10010244U,
-/*025b*/ 0x18010244U,
-/*025c*/ 0x00010245U,
-/*025d*/ 0x08010245U,
-/*025e*/ 0x10010245U,
-/*025f*/ 0x18010245U,
-/*0260*/ 0x00040246U,
-/*0261*/ 0x08040246U,
-/*0262*/ 0x10040246U,
-/*0263*/ 0x18010246U,
-/*0264*/ 0x00020247U,
-/*0265*/ 0x08060247U,
-/*0266*/ 0x10060247U,
-/*0267*/ 0x18020247U,
-/*0268*/ 0x00020248U,
-/*0269*/ 0x08020248U,
-/*026a*/ 0xffffffffU,
-/*026b*/ 0x10100248U,
-/*026c*/ 0x00010249U,
-/*026d*/ 0x08010249U,
-/*026e*/ 0x10010249U,
-/*026f*/ 0x18040249U,
-/*0270*/ 0x0001024aU,
-/*0271*/ 0x0804024aU,
-/*0272*/ 0x1003024aU,
-/*0273*/ 0x1808024aU,
-/*0274*/ 0x000a024bU,
-/*0275*/ 0x100a024bU,
-/*0276*/ 0x000a024cU,
-/*0277*/ 0xffffffffU,
-/*0278*/ 0x0020024dU,
-/*0279*/ 0x0020024eU,
-/*027a*/ 0x0005024fU,
-/*027b*/ 0x1801023aU,
-/*027c*/ 0x0805023cU,
-/*027d*/ 0x0808024fU,
-/*027e*/ 0x1001024fU,
-/*027f*/ 0x1808024fU,
-/*0280*/ 0x00010250U,
-/*0281*/ 0x08080250U,
-/*0282*/ 0x10010250U,
-/*0283*/ 0x18040250U,
-/*0284*/ 0x00040251U,
-/*0285*/ 0x08040251U,
-/*0286*/ 0x10040251U,
-/*0287*/ 0x18040251U,
-/*0288*/ 0x00040252U,
-/*0289*/ 0x08040252U,
-/*028a*/ 0x10040252U,
-/*028b*/ 0x18040252U,
-/*028c*/ 0x00040253U,
-/*028d*/ 0x08010253U,
-/*028e*/ 0x10040253U,
-/*028f*/ 0x18040253U,
-/*0290*/ 0x00040254U,
-/*0291*/ 0x08040254U,
-/*0292*/ 0x10040254U,
-/*0293*/ 0x18040254U,
-/*0294*/ 0x00060255U,
-/*0295*/ 0x08060255U,
-/*0296*/ 0x10060255U,
-/*0297*/ 0x18060255U,
-/*0298*/ 0x00060256U,
-/*0299*/ 0x08060256U,
-/*029a*/ 0x10040256U,
-/*029b*/ 0x18010256U,
-/*029c*/ 0x00010257U,
-/*029d*/ 0x08020257U,
-/*029e*/ 0x00200258U,
-/*029f*/ 0x00200259U,
-/*02a0*/ 0x0020025aU,
-/*02a1*/ 0x0020025bU,
-/*02a2*/ 0x0020025cU,
-/*02a3*/ 0x0020025dU,
-/*02a4*/ 0x0020025eU,
-/*02a5*/ 0x0020025fU,
-/*02a6*/ 0x00040260U,
-/*02a7*/ 0x08040260U,
-/*02a8*/ 0x10010260U,
-/*02a9*/ 0x18010260U,
-/*02aa*/ 0x00010261U,
-/*02ab*/ 0x08010261U,
-/*02ac*/ 0x10010261U,
-/*02ad*/ 0x18010261U,
-/*02ae*/ 0x00010262U,
-/*02af*/ 0x08010262U,
-/*02b0*/ 0x10010262U,
-/*02b1*/ 0x18040262U,
-/*02b2*/ 0x00040263U,
-/*02b3*/ 0x080a0263U,
-/*02b4*/ 0x00200264U,
-/*02b5*/ 0x00040265U,
-/*02b6*/ 0x08080265U,
-/*02b7*/ 0x10020265U,
-/*02b8*/ 0x18020265U,
-/*02b9*/ 0x00020266U,
-/*02ba*/ 0x08020266U,
-/*02bb*/ 0x10020266U,
-/*02bc*/ 0x18020266U,
-/*02bd*/ 0xffffffffU,
-/*02be*/ 0xffffffffU,
-/*02bf*/ 0x00200267U,
-/*02c0*/ 0x00030268U,
-/*02c1*/ 0x08100268U,
-/*02c2*/ 0x00100269U,
-/*02c3*/ 0x10040269U,
-/*02c4*/ 0x18040269U,
-/*02c5*/ 0x0005026aU,
-/*02c6*/ 0x0805026aU,
-/*02c7*/ 0xffffffffU,
-/*02c8*/ 0xffffffffU,
-/*02c9*/ 0xffffffffU,
-/*02ca*/ 0xffffffffU,
-/*02cb*/ 0x1001026aU,
-/*02cc*/ 0x1801026aU,
-/*02cd*/ 0x0008026bU,
-/*02ce*/ 0x0808026bU,
-/*02cf*/ 0x1008026bU,
-/*02d0*/ 0x1808026bU,
-/*02d1*/ 0x0008026cU,
-/*02d2*/ 0x0808026cU,
-/*02d3*/ 0x1008026cU,
-/*02d4*/ 0x1808026cU,
-/*02d5*/ 0x0008026dU,
-/*02d6*/ 0x0808026dU,
-/*02d7*/ 0x1008026dU,
-/*02d8*/ 0x1808026dU,
-/*02d9*/ 0x0008026eU,
-/*02da*/ 0x0808026eU,
-/*02db*/ 0x1003026eU,
-/*02dc*/ 0x1803026eU,
-/*02dd*/ 0x0003026fU,
-/*02de*/ 0xffffffffU,
-/*02df*/ 0x0801026fU,
-/*02e0*/ 0x1002026fU,
-/*02e1*/ 0x1801026fU,
-/*02e2*/ 0x00040270U,
-/*02e3*/ 0x08020270U,
-/*02e4*/ 0x10010270U,
-/*02e5*/ 0x18010270U,
-/*02e6*/ 0x00010271U,
-/*02e7*/ 0x08010271U,
-/*02e8*/ 0x10040271U,
-/*02e9*/ 0x18080271U,
-/*02ea*/ 0x000a0272U,
-/*02eb*/ 0x100a0272U,
-/*02ec*/ 0x000a0273U,
-/*02ed*/ 0x100a0273U,
-/*02ee*/ 0x000a0274U,
-/*02ef*/ 0x100a0274U,
-/*02f0*/ 0x00200275U,
-/*02f1*/ 0x00200276U,
-/*02f2*/ 0x00010277U,
-/*02f3*/ 0x08020277U,
-/*02f4*/ 0x10020277U,
-/*02f5*/ 0x18020277U,
-/*02f6*/ 0xffffffffU,
-/*02f7*/ 0x00020278U,
-/*02f8*/ 0x08100278U,
-/*02f9*/ 0x18050278U,
-/*02fa*/ 0x00060279U,
-/*02fb*/ 0x08050279U,
-/*02fc*/ 0x10050279U,
-/*02fd*/ 0x000e027aU,
-/*02fe*/ 0x1005027aU,
-/*02ff*/ 0x000e027bU,
-/*0300*/ 0x1005027bU,
-/*0301*/ 0x000e027cU,
-/*0302*/ 0x1005027cU,
-/*0303*/ 0x1801027cU,
-/*0304*/ 0x0005027dU,
-/*0305*/ 0x0805027dU,
-/*0306*/ 0x100a027dU,
-/*0307*/ 0x000a027eU,
-/*0308*/ 0x1005027eU,
-/*0309*/ 0x1805027eU,
-/*030a*/ 0x000a027fU,
-/*030b*/ 0x100a027fU,
-/*030c*/ 0x00050280U,
-/*030d*/ 0x08050280U,
-/*030e*/ 0x100a0280U,
-/*030f*/ 0x000a0281U,
-/*0310*/ 0x10070281U,
-/*0311*/ 0x18070281U,
-/*0312*/ 0x00070282U,
-/*0313*/ 0x08070282U,
-/*0314*/ 0x10070282U,
-/*0315*/ 0x18070282U,
-/*0316*/ 0xffffffffU,
-/*0317*/ 0xffffffffU,
-/*0318*/ 0x00040283U,
-/*0319*/ 0x08040283U,
-/*031a*/ 0x10040283U,
-/*031b*/ 0x18040283U,
-/*031c*/ 0x00040284U,
-/*031d*/ 0xffffffffU,
-/*031e*/ 0x08080284U,
-/*031f*/ 0x10080284U,
-/*0320*/ 0x18040284U,
-/*0321*/ 0x00050285U,
-/*0322*/ 0x08080285U,
-/*0323*/ 0x10050285U,
-/*0324*/ 0x18040285U,
-/*0325*/ 0x00050286U,
-/*0326*/ 0x08080286U,
-/*0327*/ 0x10050286U,
-/*0328*/ 0x18040286U,
-/*0329*/ 0x00050287U,
-/*032a*/ 0x08080287U,
-/*032b*/ 0x10050287U,
-/*032c*/ 0x18040287U,
-/*032d*/ 0x00050288U,
-/*032e*/ 0x08070288U,
-/*032f*/ 0x10080288U,
-/*0330*/ 0x00100289U,
-/*0331*/ 0x10080289U,
-/*0332*/ 0x0010028aU,
-/*0333*/ 0x1008028aU,
-/*0334*/ 0x0010028bU,
-/*0335*/ 0x1008028bU,
-/*0336*/ 0x1808028bU,
-/*0337*/ 0x0001028cU,
-/*0338*/ 0x0801028cU,
-/*0339*/ 0x1006028cU,
-/*033a*/ 0x1806028cU,
-/*033b*/ 0x0006028dU,
-/*033c*/ 0x0801028dU,
-/*033d*/ 0x1001028dU,
-/*033e*/ 0x1803028dU,
-/*033f*/ 0x000a028eU,
-/*0340*/ 0x100a028eU,
-/*0341*/ 0x000a028fU,
-/*0342*/ 0xffffffffU,
-/*0343*/ 0x100a028fU,
-/*0344*/ 0x00040290U,
-/*0345*/ 0x08010290U,
-/*0346*/ 0x10040290U,
-/*0347*/ 0x18070290U,
-/*0348*/ 0x00070291U,
-/*0349*/ 0x08070291U,
-/*034a*/ 0x10070291U,
-/*034b*/ 0x18070291U,
-/*034c*/ 0x00070292U,
-/*034d*/ 0xffffffffU,
-/*034e*/ 0xffffffffU,
-/*034f*/ 0x08050292U,
-/*0350*/ 0x10050292U,
-/*0351*/ 0x18040292U,
-/*0352*/ 0x00040293U,
-/*0353*/ 0x08040293U,
-/*0354*/ 0xffffffffU,
-/*0355*/ 0x10010293U,
-/*0356*/ 0x18010293U,
-/*0357*/ 0x00020294U,
-/*0358*/ 0x08080294U,
-/*0359*/ 0x00200295U,
-/*035a*/ 0x00200296U,
-/*035b*/ 0x00100297U,
-/*035c*/ 0x10020297U,
-/*035d*/ 0x18020297U,
-/*035e*/ 0x00020298U,
-/*035f*/ 0xffffffffU,
-/*0360*/ 0x08010298U,
-/*0361*/ 0x10010298U,
-/*0362*/ 0x18020298U,
-/*0363*/ 0x00100299U,
-/*0364*/ 0x10100299U,
-/*0365*/ 0x0010029aU,
-/*0366*/ 0x1008029aU,
-/*0367*/ 0x1808029aU,
-/*0368*/ 0x0008029bU,
-/*0369*/ 0x0808029bU,
-/*036a*/ 0x1010029bU,
-/*036b*/ 0x0010029cU,
-/*036c*/ 0x1010029cU,
-/*036d*/ 0x0008029dU,
-/*036e*/ 0x0808029dU,
-/*036f*/ 0x1008029dU,
-/*0370*/ 0x1808029dU,
-/*0371*/ 0x0010029eU,
-/*0372*/ 0x1010029eU,
-/*0373*/ 0x0010029fU,
-/*0374*/ 0x1008029fU,
-/*0375*/ 0x1808029fU,
-/*0376*/ 0x000802a0U,
-/*0377*/ 0x080802a0U,
-/*0378*/ 0x100802a0U,
-/*0379*/ 0x001002a1U,
-/*037a*/ 0x101002a1U,
-/*037b*/ 0x001002a2U,
-/*037c*/ 0x100802a2U,
-/*037d*/ 0x180802a2U,
-/*037e*/ 0x000802a3U,
-/*037f*/ 0x080802a3U,
-/*0380*/ 0x101002a3U,
-/*0381*/ 0x001002a4U,
-/*0382*/ 0x101002a4U,
-/*0383*/ 0x000802a5U,
-/*0384*/ 0x080802a5U,
-/*0385*/ 0x100802a5U,
-/*0386*/ 0x180802a5U,
-/*0387*/ 0x001002a6U,
-/*0388*/ 0x101002a6U,
-/*0389*/ 0x001002a7U,
-/*038a*/ 0x100802a7U,
-/*038b*/ 0x180802a7U,
-/*038c*/ 0x000802a8U,
-/*038d*/ 0x080802a8U,
-/*038e*/ 0x100802a8U,
-/*038f*/ 0x001002a9U,
-/*0390*/ 0x101002a9U,
-/*0391*/ 0x001002aaU,
-/*0392*/ 0x100802aaU,
-/*0393*/ 0x180802aaU,
-/*0394*/ 0x000802abU,
-/*0395*/ 0x080802abU,
-/*0396*/ 0x101002abU,
-/*0397*/ 0x001002acU,
-/*0398*/ 0x101002acU,
-/*0399*/ 0x000802adU,
-/*039a*/ 0x080802adU,
-/*039b*/ 0x100802adU,
-/*039c*/ 0x180802adU,
-/*039d*/ 0x001002aeU,
-/*039e*/ 0x101002aeU,
-/*039f*/ 0x001002afU,
-/*03a0*/ 0x100802afU,
-/*03a1*/ 0x180802afU,
-/*03a2*/ 0x000802b0U,
-/*03a3*/ 0x080802b0U,
-/*03a4*/ 0x100802b0U,
-/*03a5*/ 0x001002b1U,
-/*03a6*/ 0x101002b1U,
-/*03a7*/ 0x001002b2U,
-/*03a8*/ 0x100802b2U,
-/*03a9*/ 0x180802b2U,
-/*03aa*/ 0x000802b3U,
-/*03ab*/ 0x080802b3U,
-/*03ac*/ 0x101002b3U,
-/*03ad*/ 0x001002b4U,
-/*03ae*/ 0x101002b4U,
-/*03af*/ 0x000802b5U,
-/*03b0*/ 0x080802b5U,
-/*03b1*/ 0x100802b5U,
-/*03b2*/ 0x180802b5U,
-/*03b3*/ 0x001002b6U,
-/*03b4*/ 0x101002b6U,
-/*03b5*/ 0x001002b7U,
-/*03b6*/ 0x100802b7U,
-/*03b7*/ 0x180802b7U,
-/*03b8*/ 0x000802b8U,
-/*03b9*/ 0x080802b8U,
-/*03ba*/ 0x100802b8U,
-/*03bb*/ 0x180202b8U,
-/*03bc*/ 0x000302b9U,
-/*03bd*/ 0x080a02b9U,
-/*03be*/ 0x000a02baU,
-/*03bf*/ 0x100a02baU,
-/*03c0*/ 0x000502bbU,
-/*03c1*/ 0x080802bbU,
-/*03c2*/ 0x100802bbU,
-/*03c3*/ 0x180802bbU,
-/*03c4*/ 0x000602bcU,
-/*03c5*/ 0x080602bcU,
-/*03c6*/ 0x001102bdU,
-/*03c7*/ 0x180802bdU,
-/*03c8*/ 0x000402beU,
-/*03c9*/ 0x080602beU,
-/*03ca*/ 0x100802beU,
-/*03cb*/ 0x180802beU,
-/*03cc*/ 0x000802bfU,
-/*03cd*/ 0x080802bfU,
-/*03ce*/ 0x100802bfU,
-/*03cf*/ 0x180802bfU,
-/*03d0*/ 0x000802c0U,
-/*03d1*/ 0x080602c0U,
-/*03d2*/ 0x100602c0U,
-/*03d3*/ 0x001102c1U,
-/*03d4*/ 0x180802c1U,
-/*03d5*/ 0x000402c2U,
-/*03d6*/ 0x080602c2U,
-/*03d7*/ 0x100802c2U,
-/*03d8*/ 0x180802c2U,
-/*03d9*/ 0x000802c3U,
-/*03da*/ 0x080802c3U,
-/*03db*/ 0x100802c3U,
-/*03dc*/ 0x180802c3U,
-/*03dd*/ 0x000802c4U,
-/*03de*/ 0x080602c4U,
-/*03df*/ 0x100602c4U,
-/*03e0*/ 0x001102c5U,
-/*03e1*/ 0x180802c5U,
-/*03e2*/ 0x000402c6U,
-/*03e3*/ 0x080602c6U,
-/*03e4*/ 0x100802c6U,
-/*03e5*/ 0x180802c6U,
-/*03e6*/ 0x000802c7U,
-/*03e7*/ 0x080802c7U,
-/*03e8*/ 0x100402c7U,
-/*03e9*/ 0x180402c7U,
-/*03ea*/ 0x000402c8U,
-/*03eb*/ 0x080402c8U,
-/*03ec*/ 0x100402c8U,
-/*03ed*/ 0x180402c8U,
-/*03ee*/ 0x000402c9U,
-/*03ef*/ 0x080402c9U,
-/*03f0*/ 0x100402c9U,
-/*03f1*/ 0x180402c9U,
-/*03f2*/ 0x000402caU,
-/*03f3*/ 0x080402caU,
-/*03f4*/ 0x100402caU,
-/*03f5*/ 0x180402caU,
-/*03f6*/ 0x000402cbU,
-/*03f7*/ 0x080402cbU,
-/*03f8*/ 0x100402cbU,
-/*03f9*/ 0x180402cbU,
-/*03fa*/ 0x000402ccU,
-/*03fb*/ 0x080402ccU,
-/*03fc*/ 0x001702cdU,
-/*03fd*/ 0x001602ceU,
-/*03fe*/ 0x001702cfU,
-/*03ff*/ 0x002002d0U,
-/*0400*/ 0x002002d1U,
-/*0401*/ 0x002002d2U,
-/*0402*/ 0x002002d3U,
-/*0403*/ 0x002002d4U,
-/*0404*/ 0x002002d5U,
-/*0405*/ 0x002002d6U,
-/*0406*/ 0x002002d7U,
-/*0407*/ 0x002002d8U,
-/*0408*/ 0x000202d9U,
-/*0409*/ 0x080502d9U,
-/*040a*/ 0x100502d9U,
-/*040b*/ 0x180102d9U,
-/*040c*/ 0x000502daU,
-/*040d*/ 0x080502daU,
-/*040e*/ 0x100502daU,
-/*040f*/ 0x180502daU,
-/*0410*/ 0x000502dbU,
-/*0411*/ 0x080502dbU,
-/*0412*/ 0x100502dbU,
-/*0413*/ 0x180502dbU,
-/*0414*/ 0x000502dcU,
-/*0415*/ 0x080502dcU,
-/*0416*/ 0x100502dcU,
-/*0417*/ 0x180502dcU,
-/*0418*/ 0x000502ddU,
-/*0419*/ 0x080502ddU,
-/*041a*/ 0x100502ddU,
-/*041b*/ 0x180502ddU,
-/*041c*/ 0x000502deU,
-/*041d*/ 0x080502deU,
-/*041e*/ 0x100502deU,
-/*041f*/ 0x180502deU,
-/*0420*/ 0x000502dfU,
-/*0421*/ 0x080502dfU,
-/*0422*/ 0x100102dfU,
-/*0423*/ 0x180202dfU,
-/*0424*/ 0x000202e0U,
-/*0425*/ 0x080202e0U,
-/*0426*/ 0x100202e0U,
-/*0427*/ 0x180102e0U,
-/*0428*/ 0x000802e1U,
-/*0429*/ 0x081502e1U,
-/*042a*/ 0x002002e2U,
-/*042b*/ 0x001502e3U,
-/*042c*/ 0x002002e4U,
-/*042d*/ 0x001502e5U,
-/*042e*/ 0x002002e6U,
-/*042f*/ 0x000702e7U,
-/*0430*/ 0x080102e7U,
-/*0431*/ 0x100202e7U,
-/*0432*/ 0x180602e7U,
-/*0433*/ 0x000102e8U,
-/*0434*/ 0x080102e8U,
-/*0435*/ 0x002002e9U,
-/*0436*/ 0x000202eaU,
-/*0437*/ 0x002002ebU,
-/*0438*/ 0x002002ecU,
-/*0439*/ 0x000c02edU,
-/*043a*/ 0x100c02edU,
-/*043b*/ 0x002002eeU,
-/*043c*/ 0x000302efU,
-/*043d*/ 0x002002f0U,
-/*043e*/ 0x000302f1U,
-/*043f*/ 0x002002f2U,
-/*0440*/ 0x000302f3U,
-/*0441*/ 0x002002f4U,
-/*0442*/ 0x000302f5U,
-/*0443*/ 0x002002f6U,
-/*0444*/ 0x000302f7U,
-/*0445*/ 0x002002f8U,
-/*0446*/ 0x000302f9U,
-/*0447*/ 0x002002faU,
-/*0448*/ 0x000302fbU,
-/*0449*/ 0x002002fcU,
-/*044a*/ 0x000302fdU,
-/*044b*/ 0x002002feU,
-/*044c*/ 0x000302ffU,
-/*044d*/ 0x00200300U,
-/*044e*/ 0x00030301U,
-/*044f*/ 0x08030301U,
-/*0450*/ 0x10020301U,
-/*0451*/ 0x18020301U,
-/*0452*/ 0x00200302U,
-/*0453*/ 0x00200303U,
-/*0454*/ 0x00200304U,
-/*0455*/ 0x00200305U,
-/*0456*/ 0x00040306U,
-/*0457*/ 0x001e0307U,
-/*0458*/ 0x001e0308U,
-/*0459*/ 0x001e0309U,
-/*045a*/ 0x001e030aU,
-/*045b*/ 0x001e030bU,
-/*045c*/ 0x001e030cU,
-/*045d*/ 0x001e030dU,
-/*045e*/ 0x001e030eU,
-/*045f*/ 0x0004030fU,
-/*0460*/ 0x0801030fU,
-/*0461*/ 0x1010030fU,
-/*0462*/ 0x00100310U,
-/*0463*/ 0x10100310U,
-/*0464*/ 0x00040311U,
-/*0465*/ 0x08010311U,
-/*0466*/ 0x10080311U,
-/*0467*/ 0x18040311U,
-/*0468*/ 0x00010312U,
-/*0469*/ 0x08080312U,
-/*046a*/ 0x10040312U,
-/*046b*/ 0x18010312U,
-/*046c*/ 0x00080313U,
-/*046d*/ 0x08040313U,
-/*046e*/ 0x10010313U,
-/*046f*/ 0x18080313U,
-/*0470*/ 0x00040314U,
-/*0471*/ 0x08010314U,
-/*0472*/ 0x10080314U,
-/*0473*/ 0x18040314U,
-/*0474*/ 0x00010315U,
-/*0475*/ 0x08080315U,
-/*0476*/ 0x10040315U,
-/*0477*/ 0x18010315U,
-/*0478*/ 0x00080316U,
-/*0479*/ 0x08040316U,
-/*047a*/ 0x10010316U,
-/*047b*/ 0x18080316U,
-/*047c*/ 0x00080317U,
-/*047d*/ 0x00010318U,
-/*047e*/ 0x08050318U,
-/*047f*/ 0x10010318U,
-/*0480*/ 0x18020318U,
-/*0481*/ 0x00010319U,
-/*0482*/ 0x08010319U,
-/*0483*/ 0x10010319U,
-/*0484*/ 0x18010319U,
-/*0485*/ 0x0001031aU,
-/*0486*/ 0x0801031aU,
-/*0487*/ 0x1001031aU,
-/*0488*/ 0x1801031aU,
-/*0489*/ 0x0001031bU,
-/*048a*/ 0x0801031bU,
-/*048b*/ 0x1001031bU,
-/*048c*/ 0x1801031bU,
-/*048d*/ 0x0001031cU,
-/*048e*/ 0x0801031cU,
-/*048f*/ 0x1001031cU,
-/*0490*/ 0x1801031cU,
-/*0491*/ 0x0008031dU,
-/*0492*/ 0x0808031dU,
-/*0493*/ 0x1008031dU,
-/*0494*/ 0x1808031dU,
- }
-};
-
-#endif /* RZG_DDR_REGDEF_H */
diff --git a/drivers/renesas/rzg/ddr/ddr_b/init_dram_tbl_g2m.h b/drivers/renesas/rzg/ddr/ddr_b/init_dram_tbl_g2m.h
deleted file mode 100644
index e10162a..0000000
--- a/drivers/renesas/rzg/ddr/ddr_b/init_dram_tbl_g2m.h
+++ /dev/null
@@ -1,472 +0,0 @@
-/*
- * Copyright (c) 2020U, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef RZG_INIT_DRAM_TABLE_G2M_H
-#define RZG_INIT_DRAM_TABLE_G2M_H
-
-#define DDR_PHY_SLICE_REGSET_OFS_G2M 0x0800U
-#define DDR_PHY_ADR_V_REGSET_OFS_G2M 0x0a00U
-#define DDR_PHY_ADR_I_REGSET_OFS_G2M 0x0a80U
-#define DDR_PHY_ADR_G_REGSET_OFS_G2M 0x0b80U
-#define DDR_PI_REGSET_OFS_G2M 0x0200U
-
-#define DDR_PHY_SLICE_REGSET_SIZE_G2M 0x80U
-#define DDR_PHY_ADR_V_REGSET_SIZE_G2M 0x80U
-#define DDR_PHY_ADR_I_REGSET_SIZE_G2M 0x80U
-#define DDR_PHY_ADR_G_REGSET_SIZE_G2M 0x80U
-#define DDR_PI_REGSET_SIZE_G2M 0x100U
-
-#define DDR_PHY_SLICE_REGSET_NUM_G2M 89
-#define DDR_PHY_ADR_V_REGSET_NUM_G2M 37
-#define DDR_PHY_ADR_I_REGSET_NUM_G2M 37
-#define DDR_PHY_ADR_G_REGSET_NUM_G2M 64
-#define DDR_PI_REGSET_NUM_G2M 202
-
-static const uint32_t DDR_PHY_SLICE_REGSET_G2M[DDR_PHY_SLICE_REGSET_NUM_G2M] = {
- /*0800*/ 0x76543210U,
- /*0801*/ 0x0004f008U,
- /*0802*/ 0x00000000U,
- /*0803*/ 0x00000000U,
- /*0804*/ 0x00010000U,
- /*0805*/ 0x036e6e0eU,
- /*0806*/ 0x026e6e0eU,
- /*0807*/ 0x00010300U,
- /*0808*/ 0x04000100U,
- /*0809*/ 0x00000300U,
- /*080a*/ 0x001700c0U,
- /*080b*/ 0x00b00201U,
- /*080c*/ 0x00030020U,
- /*080d*/ 0x00000000U,
- /*080e*/ 0x00000000U,
- /*080f*/ 0x00000000U,
- /*0810*/ 0x00000000U,
- /*0811*/ 0x00000000U,
- /*0812*/ 0x00000000U,
- /*0813*/ 0x00000000U,
- /*0814*/ 0x09000000U,
- /*0815*/ 0x04080000U,
- /*0816*/ 0x04080400U,
- /*0817*/ 0x00000000U,
- /*0818*/ 0x32103210U,
- /*0819*/ 0x00800708U,
- /*081a*/ 0x000f000cU,
- /*081b*/ 0x00000100U,
- /*081c*/ 0x55aa55aaU,
- /*081d*/ 0x33cc33ccU,
- /*081e*/ 0x0ff00ff0U,
- /*081f*/ 0x0f0ff0f0U,
- /*0820*/ 0x00018e38U,
- /*0821*/ 0x00000000U,
- /*0822*/ 0x00000000U,
- /*0823*/ 0x00000000U,
- /*0824*/ 0x00000000U,
- /*0825*/ 0x00000000U,
- /*0826*/ 0x00000000U,
- /*0827*/ 0x00000000U,
- /*0828*/ 0x00000000U,
- /*0829*/ 0x00000000U,
- /*082a*/ 0x00000000U,
- /*082b*/ 0x00000000U,
- /*082c*/ 0x00000000U,
- /*082d*/ 0x00000000U,
- /*082e*/ 0x00000000U,
- /*082f*/ 0x00000000U,
- /*0830*/ 0x00000000U,
- /*0831*/ 0x00000000U,
- /*0832*/ 0x00000000U,
- /*0833*/ 0x00200000U,
- /*0834*/ 0x08200820U,
- /*0835*/ 0x08200820U,
- /*0836*/ 0x08200820U,
- /*0837*/ 0x08200820U,
- /*0838*/ 0x08200820U,
- /*0839*/ 0x00000820U,
- /*083a*/ 0x03000300U,
- /*083b*/ 0x03000300U,
- /*083c*/ 0x03000300U,
- /*083d*/ 0x03000300U,
- /*083e*/ 0x00000300U,
- /*083f*/ 0x00000000U,
- /*0840*/ 0x00000000U,
- /*0841*/ 0x00000000U,
- /*0842*/ 0x00000000U,
- /*0843*/ 0x00a00000U,
- /*0844*/ 0x00a000a0U,
- /*0845*/ 0x00a000a0U,
- /*0846*/ 0x00a000a0U,
- /*0847*/ 0x00a000a0U,
- /*0848*/ 0x00a000a0U,
- /*0849*/ 0x00a000a0U,
- /*084a*/ 0x00a000a0U,
- /*084b*/ 0x00a000a0U,
- /*084c*/ 0x010900a0U,
- /*084d*/ 0x02000104U,
- /*084e*/ 0x00000000U,
- /*084f*/ 0x00010000U,
- /*0850*/ 0x00000200U,
- /*0851*/ 0x4041a151U,
- /*0852*/ 0xc00141a0U,
- /*0853*/ 0x0e0100c0U,
- /*0854*/ 0x0010000cU,
- /*0855*/ 0x0c064208U,
- /*0856*/ 0x000f0c18U,
- /*0857*/ 0x00e00140U,
- /*0858*/ 0x00000c20U
-};
-
-static const uint32_t DDR_PHY_ADR_V_REGSET_G2M[DDR_PHY_ADR_V_REGSET_NUM_G2M] = {
- /*0a00*/ 0x00000000U,
- /*0a01*/ 0x00000000U,
- /*0a02*/ 0x00000000U,
- /*0a03*/ 0x00000000U,
- /*0a04*/ 0x00000000U,
- /*0a05*/ 0x00000000U,
- /*0a06*/ 0x00000002U,
- /*0a07*/ 0x00000000U,
- /*0a08*/ 0x00000000U,
- /*0a09*/ 0x00000000U,
- /*0a0a*/ 0x00400320U,
- /*0a0b*/ 0x00000040U,
- /*0a0c*/ 0x00dcba98U,
- /*0a0d*/ 0x00000000U,
- /*0a0e*/ 0x00dcba98U,
- /*0a0f*/ 0x01000000U,
- /*0a10*/ 0x00020003U,
- /*0a11*/ 0x00000000U,
- /*0a12*/ 0x00000000U,
- /*0a13*/ 0x00000000U,
- /*0a14*/ 0x0000002aU,
- /*0a15*/ 0x00000015U,
- /*0a16*/ 0x00000015U,
- /*0a17*/ 0x0000002aU,
- /*0a18*/ 0x00000033U,
- /*0a19*/ 0x0000000cU,
- /*0a1a*/ 0x0000000cU,
- /*0a1b*/ 0x00000033U,
- /*0a1c*/ 0x0a418820U,
- /*0a1d*/ 0x003f0000U,
- /*0a1e*/ 0x0000003fU,
- /*0a1f*/ 0x0002c06eU,
- /*0a20*/ 0x02c002c0U,
- /*0a21*/ 0x02c002c0U,
- /*0a22*/ 0x000002c0U,
- /*0a23*/ 0x42080010U,
- /*0a24*/ 0x00000003U
-};
-
-static const uint32_t DDR_PHY_ADR_I_REGSET_G2M[DDR_PHY_ADR_I_REGSET_NUM_G2M] = {
- /*0a80*/ 0x04040404U,
- /*0a81*/ 0x00000404U,
- /*0a82*/ 0x00000000U,
- /*0a83*/ 0x00000000U,
- /*0a84*/ 0x00000000U,
- /*0a85*/ 0x00000000U,
- /*0a86*/ 0x00000002U,
- /*0a87*/ 0x00000000U,
- /*0a88*/ 0x00000000U,
- /*0a89*/ 0x00000000U,
- /*0a8a*/ 0x00400320U,
- /*0a8b*/ 0x00000040U,
- /*0a8c*/ 0x00000000U,
- /*0a8d*/ 0x00000000U,
- /*0a8e*/ 0x00000000U,
- /*0a8f*/ 0x01000000U,
- /*0a90*/ 0x00020003U,
- /*0a91*/ 0x00000000U,
- /*0a92*/ 0x00000000U,
- /*0a93*/ 0x00000000U,
- /*0a94*/ 0x0000002aU,
- /*0a95*/ 0x00000015U,
- /*0a96*/ 0x00000015U,
- /*0a97*/ 0x0000002aU,
- /*0a98*/ 0x00000033U,
- /*0a99*/ 0x0000000cU,
- /*0a9a*/ 0x0000000cU,
- /*0a9b*/ 0x00000033U,
- /*0a9c*/ 0x00000000U,
- /*0a9d*/ 0x00000000U,
- /*0a9e*/ 0x00000000U,
- /*0a9f*/ 0x0002c06eU,
- /*0aa0*/ 0x02c002c0U,
- /*0aa1*/ 0x02c002c0U,
- /*0aa2*/ 0x000002c0U,
- /*0aa3*/ 0x42080010U,
- /*0aa4*/ 0x00000003U
-};
-
-static const uint32_t DDR_PHY_ADR_G_REGSET_G2M[DDR_PHY_ADR_G_REGSET_NUM_G2M] = {
- /*0b80*/ 0x00000001U,
- /*0b81*/ 0x00000000U,
- /*0b82*/ 0x00000005U,
- /*0b83*/ 0x04000f00U,
- /*0b84*/ 0x00020080U,
- /*0b85*/ 0x00020055U,
- /*0b86*/ 0x00000000U,
- /*0b87*/ 0x00000000U,
- /*0b88*/ 0x00000000U,
- /*0b89*/ 0x00000050U,
- /*0b8a*/ 0x00000000U,
- /*0b8b*/ 0x01010100U,
- /*0b8c*/ 0x00000600U,
- /*0b8d*/ 0x50640000U,
- /*0b8e*/ 0x01421142U,
- /*0b8f*/ 0x00000142U,
- /*0b90*/ 0x00000000U,
- /*0b91*/ 0x000f1600U,
- /*0b92*/ 0x0f160f16U,
- /*0b93*/ 0x0f160f16U,
- /*0b94*/ 0x00000003U,
- /*0b95*/ 0x0002c000U,
- /*0b96*/ 0x02c002c0U,
- /*0b97*/ 0x000002c0U,
- /*0b98*/ 0x03421342U,
- /*0b99*/ 0x00000342U,
- /*0b9a*/ 0x00000000U,
- /*0b9b*/ 0x00000000U,
- /*0b9c*/ 0x05020000U,
- /*0b9d*/ 0x00000000U,
- /*0b9e*/ 0x00027f6eU,
- /*0b9f*/ 0x047f027fU,
- /*0ba0*/ 0x00027f6eU,
- /*0ba1*/ 0x00047f6eU,
- /*0ba2*/ 0x0003554fU,
- /*0ba3*/ 0x0001554fU,
- /*0ba4*/ 0x0001554fU,
- /*0ba5*/ 0x0001554fU,
- /*0ba6*/ 0x0001554fU,
- /*0ba7*/ 0x00003feeU,
- /*0ba8*/ 0x0001554fU,
- /*0ba9*/ 0x00003feeU,
- /*0baa*/ 0x0001554fU,
- /*0bab*/ 0x00027f6eU,
- /*0bac*/ 0x0001554fU,
- /*0bad*/ 0x00000000U,
- /*0bae*/ 0x00000000U,
- /*0baf*/ 0x00000000U,
- /*0bb0*/ 0x65000000U,
- /*0bb1*/ 0x00000000U,
- /*0bb2*/ 0x00000000U,
- /*0bb3*/ 0x00000201U,
- /*0bb4*/ 0x00000000U,
- /*0bb5*/ 0x00000000U,
- /*0bb6*/ 0x00000000U,
- /*0bb7*/ 0x00000000U,
- /*0bb8*/ 0x00000000U,
- /*0bb9*/ 0x00000000U,
- /*0bba*/ 0x00000000U,
- /*0bbb*/ 0x00000000U,
- /*0bbc*/ 0x06e40000U,
- /*0bbd*/ 0x00000000U,
- /*0bbe*/ 0x00000000U,
- /*0bbf*/ 0x00010000U
-};
-
-static const uint32_t DDR_PI_REGSET_G2M[DDR_PI_REGSET_NUM_G2M] = {
- /*0200*/ 0x00000b00U,
- /*0201*/ 0x00000100U,
- /*0202*/ 0x00000000U,
- /*0203*/ 0x0000ffffU,
- /*0204*/ 0x00000000U,
- /*0205*/ 0x0000ffffU,
- /*0206*/ 0x00000000U,
- /*0207*/ 0x304cffffU,
- /*0208*/ 0x00000200U,
- /*0209*/ 0x00000200U,
- /*020a*/ 0x00000200U,
- /*020b*/ 0x00000200U,
- /*020c*/ 0x0000304cU,
- /*020d*/ 0x00000200U,
- /*020e*/ 0x00000200U,
- /*020f*/ 0x00000200U,
- /*0210*/ 0x00000200U,
- /*0211*/ 0x0000304cU,
- /*0212*/ 0x00000200U,
- /*0213*/ 0x00000200U,
- /*0214*/ 0x00000200U,
- /*0215*/ 0x00000200U,
- /*0216*/ 0x00010000U,
- /*0217*/ 0x00000003U,
- /*0218*/ 0x01000001U,
- /*0219*/ 0x00000000U,
- /*021a*/ 0x00000000U,
- /*021b*/ 0x00000000U,
- /*021c*/ 0x00000000U,
- /*021d*/ 0x00000000U,
- /*021e*/ 0x00000000U,
- /*021f*/ 0x00000000U,
- /*0220*/ 0x00000000U,
- /*0221*/ 0x00000000U,
- /*0222*/ 0x00000000U,
- /*0223*/ 0x00000000U,
- /*0224*/ 0x00000000U,
- /*0225*/ 0x00000000U,
- /*0226*/ 0x00000000U,
- /*0227*/ 0x00000000U,
- /*0228*/ 0x00000000U,
- /*0229*/ 0x0f000101U,
- /*022a*/ 0x08492d25U,
- /*022b*/ 0x0e0c0004U,
- /*022c*/ 0x000e5000U,
- /*022d*/ 0x00000250U,
- /*022e*/ 0x00460003U,
- /*022f*/ 0x182600cfU,
- /*0230*/ 0x182600cfU,
- /*0231*/ 0x00000005U,
- /*0232*/ 0x00000000U,
- /*0233*/ 0x00000000U,
- /*0234*/ 0x00000000U,
- /*0235*/ 0x00000000U,
- /*0236*/ 0x00000000U,
- /*0237*/ 0x00000000U,
- /*0238*/ 0x00000000U,
- /*0239*/ 0x01000000U,
- /*023a*/ 0x00040404U,
- /*023b*/ 0x01280a00U,
- /*023c*/ 0x00000000U,
- /*023d*/ 0x000f0000U,
- /*023e*/ 0x00001803U,
- /*023f*/ 0x00000000U,
- /*0240*/ 0x00000000U,
- /*0241*/ 0x00060002U,
- /*0242*/ 0x00010001U,
- /*0243*/ 0x01000101U,
- /*0244*/ 0x04020201U,
- /*0245*/ 0x00080804U,
- /*0246*/ 0x00000000U,
- /*0247*/ 0x08030000U,
- /*0248*/ 0x15150408U,
- /*0249*/ 0x00000000U,
- /*024a*/ 0x00000000U,
- /*024b*/ 0x00000000U,
- /*024c*/ 0x000f0f00U,
- /*024d*/ 0x0000001eU,
- /*024e*/ 0x00000000U,
- /*024f*/ 0x01000300U,
- /*0250*/ 0x00000000U,
- /*0251*/ 0x00000000U,
- /*0252*/ 0x01000000U,
- /*0253*/ 0x00010101U,
- /*0254*/ 0x000e0e0eU,
- /*0255*/ 0x000c0c0cU,
- /*0256*/ 0x02060601U,
- /*0257*/ 0x00000000U,
- /*0258*/ 0x00000003U,
- /*0259*/ 0x00181703U,
- /*025a*/ 0x00280006U,
- /*025b*/ 0x00280016U,
- /*025c*/ 0x00000016U,
- /*025d*/ 0x00000000U,
- /*025e*/ 0x00000000U,
- /*025f*/ 0x00000000U,
- /*0260*/ 0x140a0000U,
- /*0261*/ 0x0005010aU,
- /*0262*/ 0x03018d03U,
- /*0263*/ 0x000a018dU,
- /*0264*/ 0x00060100U,
- /*0265*/ 0x01000006U,
- /*0266*/ 0x018e018eU,
- /*0267*/ 0x018e0100U,
- /*0268*/ 0x1111018eU,
- /*0269*/ 0x10010204U,
- /*026a*/ 0x09090650U,
- /*026b*/ 0x20110202U,
- /*026c*/ 0x00201000U,
- /*026d*/ 0x00201000U,
- /*026e*/ 0x04041000U,
- /*026f*/ 0x18020100U,
- /*0270*/ 0x00010118U,
- /*0271*/ 0x004b004aU,
- /*0272*/ 0x050f0000U,
- /*0273*/ 0x0c01021eU,
- /*0274*/ 0x34000000U,
- /*0275*/ 0x00000000U,
- /*0276*/ 0x00000000U,
- /*0277*/ 0x00000000U,
- /*0278*/ 0x0000d400U,
- /*0279*/ 0x0031002eU,
- /*027a*/ 0x00111136U,
- /*027b*/ 0x002e00d4U,
- /*027c*/ 0x11360031U,
- /*027d*/ 0x0000d411U,
- /*027e*/ 0x0031002eU,
- /*027f*/ 0x00111136U,
- /*0280*/ 0x002e00d4U,
- /*0281*/ 0x11360031U,
- /*0282*/ 0x0000d411U,
- /*0283*/ 0x0031002eU,
- /*0284*/ 0x00111136U,
- /*0285*/ 0x002e00d4U,
- /*0286*/ 0x11360031U,
- /*0287*/ 0x00d40011U,
- /*0288*/ 0x0031002eU,
- /*0289*/ 0x00111136U,
- /*028a*/ 0x002e00d4U,
- /*028b*/ 0x11360031U,
- /*028c*/ 0x0000d411U,
- /*028d*/ 0x0031002eU,
- /*028e*/ 0x00111136U,
- /*028f*/ 0x002e00d4U,
- /*0290*/ 0x11360031U,
- /*0291*/ 0x0000d411U,
- /*0292*/ 0x0031002eU,
- /*0293*/ 0x00111136U,
- /*0294*/ 0x002e00d4U,
- /*0295*/ 0x11360031U,
- /*0296*/ 0x02000011U,
- /*0297*/ 0x018d018dU,
- /*0298*/ 0x0c08018dU,
- /*0299*/ 0x1f121d22U,
- /*029a*/ 0x4301b344U,
- /*029b*/ 0x10172006U,
- /*029c*/ 0x1d220c10U,
- /*029d*/ 0x00001f12U,
- /*029e*/ 0x4301b344U,
- /*029f*/ 0x10172006U,
- /*02a0*/ 0x1d220c10U,
- /*02a1*/ 0x00001f12U,
- /*02a2*/ 0x4301b344U,
- /*02a3*/ 0x10172006U,
- /*02a4*/ 0x02000210U,
- /*02a5*/ 0x02000200U,
- /*02a6*/ 0x02000200U,
- /*02a7*/ 0x02000200U,
- /*02a8*/ 0x02000200U,
- /*02a9*/ 0x00000000U,
- /*02aa*/ 0x00000000U,
- /*02ab*/ 0x00000000U,
- /*02ac*/ 0x00000000U,
- /*02ad*/ 0x00000000U,
- /*02ae*/ 0x00000000U,
- /*02af*/ 0x00000000U,
- /*02b0*/ 0x00000000U,
- /*02b1*/ 0x00000000U,
- /*02b2*/ 0x00000000U,
- /*02b3*/ 0x00000000U,
- /*02b4*/ 0x00000000U,
- /*02b5*/ 0x00000400U,
- /*02b6*/ 0x15141312U,
- /*02b7*/ 0x11100f0eU,
- /*02b8*/ 0x080b0c0dU,
- /*02b9*/ 0x05040a09U,
- /*02ba*/ 0x01000706U,
- /*02bb*/ 0x00000302U,
- /*02bc*/ 0x01030201U,
- /*02bd*/ 0x00304c00U,
- /*02be*/ 0x0001e2f8U,
- /*02bf*/ 0x0000304cU,
- /*02c0*/ 0x0001e2f8U,
- /*02c1*/ 0x0000304cU,
- /*02c2*/ 0x0001e2f8U,
- /*02c3*/ 0x08000000U,
- /*02c4*/ 0x00000100U,
- /*02c5*/ 0x00000000U,
- /*02c6*/ 0x00000000U,
- /*02c7*/ 0x00000000U,
- /*02c8*/ 0x00000000U,
- /*02c9*/ 0x00000002U
-};
-
-#endif /* RZG_INIT_DRAM_TABLE_G2M_H */
diff --git a/drivers/renesas/rzg/ddr/dram_sub_func.h b/drivers/renesas/rzg/ddr/dram_sub_func.h
deleted file mode 100644
index 7affb61..0000000
--- a/drivers/renesas/rzg/ddr/dram_sub_func.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef DRAM_SUB_FUNC_H
-#define DRAM_SUB_FUNC_H
-
-#define DRAM_UPDATE_STATUS_ERR -1
-#define DRAM_BOOT_STATUS_COLD 0
-#define DRAM_BOOT_STATUS_WARM 1
-
-#endif /* DRAM_SUB_FUNC_H */
diff --git a/drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.c b/drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.c
new file mode 100644
index 0000000..663df50
--- /dev/null
+++ b/drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.c
@@ -0,0 +1,700 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <lib/mmio.h>
+
+#include "pfc_init_g2e.h"
+#include "rcar_def.h"
+
+#include "../pfc_regs.h"
+
+/* PFC */
+#define GPSR0_SDA4 BIT(17)
+#define GPSR0_SCL4 BIT(16)
+#define GPSR0_D15 BIT(15)
+#define GPSR0_D14 BIT(14)
+#define GPSR0_D13 BIT(13)
+#define GPSR0_D12 BIT(12)
+#define GPSR0_D11 BIT(11)
+#define GPSR0_D10 BIT(10)
+#define GPSR0_D9 BIT(9)
+#define GPSR0_D8 BIT(8)
+#define GPSR0_D7 BIT(7)
+#define GPSR0_D6 BIT(6)
+#define GPSR0_D5 BIT(5)
+#define GPSR0_D4 BIT(4)
+#define GPSR0_D3 BIT(3)
+#define GPSR0_D2 BIT(2)
+#define GPSR0_D1 BIT(1)
+#define GPSR0_D0 BIT(0)
+#define GPSR1_WE0 BIT(22)
+#define GPSR1_CS0 BIT(21)
+#define GPSR1_CLKOUT BIT(20)
+#define GPSR1_A19 BIT(19)
+#define GPSR1_A18 BIT(18)
+#define GPSR1_A17 BIT(17)
+#define GPSR1_A16 BIT(16)
+#define GPSR1_A15 BIT(15)
+#define GPSR1_A14 BIT(14)
+#define GPSR1_A13 BIT(13)
+#define GPSR1_A12 BIT(12)
+#define GPSR1_A11 BIT(11)
+#define GPSR1_A10 BIT(10)
+#define GPSR1_A9 BIT(9)
+#define GPSR1_A8 BIT(8)
+#define GPSR1_A7 BIT(7)
+#define GPSR1_A6 BIT(6)
+#define GPSR1_A5 BIT(5)
+#define GPSR1_A4 BIT(4)
+#define GPSR1_A3 BIT(3)
+#define GPSR1_A2 BIT(2)
+#define GPSR1_A1 BIT(1)
+#define GPSR1_A0 BIT(0)
+#define GPSR2_BIT27_REVERSED BIT(27)
+#define GPSR2_BIT26_REVERSED BIT(26)
+#define GPSR2_EX_WAIT0 BIT(25)
+#define GPSR2_RD_WR BIT(24)
+#define GPSR2_RD BIT(23)
+#define GPSR2_BS BIT(22)
+#define GPSR2_AVB_PHY_INT BIT(21)
+#define GPSR2_AVB_TXCREFCLK BIT(20)
+#define GPSR2_AVB_RD3 BIT(19)
+#define GPSR2_AVB_RD2 BIT(18)
+#define GPSR2_AVB_RD1 BIT(17)
+#define GPSR2_AVB_RD0 BIT(16)
+#define GPSR2_AVB_RXC BIT(15)
+#define GPSR2_AVB_RX_CTL BIT(14)
+#define GPSR2_RPC_RESET BIT(13)
+#define GPSR2_RPC_RPC_INT BIT(12)
+#define GPSR2_QSPI1_SSL BIT(11)
+#define GPSR2_QSPI1_IO3 BIT(10)
+#define GPSR2_QSPI1_IO2 BIT(9)
+#define GPSR2_QSPI1_MISO_IO1 BIT(8)
+#define GPSR2_QSPI1_MOSI_IO0 BIT(7)
+#define GPSR2_QSPI1_SPCLK BIT(6)
+#define GPSR2_QSPI0_SSL BIT(5)
+#define GPSR2_QSPI0_IO3 BIT(4)
+#define GPSR2_QSPI0_IO2 BIT(3)
+#define GPSR2_QSPI0_MISO_IO1 BIT(2)
+#define GPSR2_QSPI0_MOSI_IO0 BIT(1)
+#define GPSR2_QSPI0_SPCLK BIT(0)
+#define GPSR3_SD1_WP BIT(15)
+#define GPSR3_SD1_CD BIT(14)
+#define GPSR3_SD0_WP BIT(13)
+#define GPSR3_SD0_CD BIT(12)
+#define GPSR3_SD1_DAT3 BIT(11)
+#define GPSR3_SD1_DAT2 BIT(10)
+#define GPSR3_SD1_DAT1 BIT(9)
+#define GPSR3_SD1_DAT0 BIT(8)
+#define GPSR3_SD1_CMD BIT(7)
+#define GPSR3_SD1_CLK BIT(6)
+#define GPSR3_SD0_DAT3 BIT(5)
+#define GPSR3_SD0_DAT2 BIT(4)
+#define GPSR3_SD0_DAT1 BIT(3)
+#define GPSR3_SD0_DAT0 BIT(2)
+#define GPSR3_SD0_CMD BIT(1)
+#define GPSR3_SD0_CLK BIT(0)
+#define GPSR4_SD3_DS BIT(10)
+#define GPSR4_SD3_DAT7 BIT(9)
+#define GPSR4_SD3_DAT6 BIT(8)
+#define GPSR4_SD3_DAT5 BIT(7)
+#define GPSR4_SD3_DAT4 BIT(6)
+#define GPSR4_SD3_DAT3 BIT(5)
+#define GPSR4_SD3_DAT2 BIT(4)
+#define GPSR4_SD3_DAT1 BIT(3)
+#define GPSR4_SD3_DAT0 BIT(2)
+#define GPSR4_SD3_CMD BIT(1)
+#define GPSR4_SD3_CLK BIT(0)
+#define GPSR5_MLB_DAT BIT(19)
+#define GPSR5_MLB_SIG BIT(18)
+#define GPSR5_MLB_CLK BIT(17)
+#define GPSR5_SSI_SDATA9 BIT(16)
+#define GPSR5_MSIOF0_SS2 BIT(15)
+#define GPSR5_MSIOF0_SS1 BIT(14)
+#define GPSR5_MSIOF0_SYNC BIT(13)
+#define GPSR5_MSIOF0_TXD BIT(12)
+#define GPSR5_MSIOF0_RXD BIT(11)
+#define GPSR5_MSIOF0_SCK BIT(10)
+#define GPSR5_RX2_A BIT(9)
+#define GPSR5_TX2_A BIT(8)
+#define GPSR5_SCK2_A BIT(7)
+#define GPSR5_TX1 BIT(6)
+#define GPSR5_RX1 BIT(5)
+#define GPSR5_RTS0_A BIT(4)
+#define GPSR5_CTS0_A BIT(3)
+#define GPSR5_TX0_A BIT(2)
+#define GPSR5_RX0_A BIT(1)
+#define GPSR5_SCK0_A BIT(0)
+#define GPSR6_USB30_PWEN BIT(17)
+#define GPSR6_SSI_SDATA6 BIT(16)
+#define GPSR6_SSI_WS6 BIT(15)
+#define GPSR6_SSI_SCK6 BIT(14)
+#define GPSR6_SSI_SDATA5 BIT(13)
+#define GPSR6_SSI_WS5 BIT(12)
+#define GPSR6_SSI_SCK5 BIT(11)
+#define GPSR6_SSI_SDATA4 BIT(10)
+#define GPSR6_USB30_OVC BIT(9)
+#define GPSR6_AUDIO_CLKA BIT(8)
+#define GPSR6_SSI_SDATA3 BIT(7)
+#define GPSR6_SSI_WS349 BIT(6)
+#define GPSR6_SSI_SCK349 BIT(5)
+#define GPSR6_SSI_SDATA2 BIT(4)
+#define GPSR6_SSI_SDATA1 BIT(3)
+#define GPSR6_SSI_SDATA0 BIT(2)
+#define GPSR6_SSI_WS01239 BIT(1)
+#define GPSR6_SSI_SCK01239 BIT(0)
+
+#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
+
+#define POCCTRL0_MASK (0x0007F000U)
+#define POC_SD3_DS_33V BIT(29)
+#define POC_SD3_DAT7_33V BIT(28)
+#define POC_SD3_DAT6_33V BIT(27)
+#define POC_SD3_DAT5_33V BIT(26)
+#define POC_SD3_DAT4_33V BIT(25)
+#define POC_SD3_DAT3_33V BIT(24)
+#define POC_SD3_DAT2_33V BIT(23)
+#define POC_SD3_DAT1_33V BIT(22)
+#define POC_SD3_DAT0_33V BIT(21)
+#define POC_SD3_CMD_33V BIT(20)
+#define POC_SD3_CLK_33V BIT(19)
+#define POC_SD1_DAT3_33V BIT(11)
+#define POC_SD1_DAT2_33V BIT(10)
+#define POC_SD1_DAT1_33V BIT(9)
+#define POC_SD1_DAT0_33V BIT(8)
+#define POC_SD1_CMD_33V BIT(7)
+#define POC_SD1_CLK_33V BIT(6)
+#define POC_SD0_DAT3_33V BIT(5)
+#define POC_SD0_DAT2_33V BIT(4)
+#define POC_SD0_DAT1_33V BIT(3)
+#define POC_SD0_DAT0_33V BIT(2)
+#define POC_SD0_CMD_33V BIT(1)
+#define POC_SD0_CLK_33V BIT(0)
+
+#define POCCTRL2_MASK (0xFFFFFFFEU)
+#define POC2_VREF_33V BIT(0)
+
+#define MOD_SEL0_ADGB_A ((uint32_t)0U << 29U)
+#define MOD_SEL0_ADGB_B ((uint32_t)1U << 29U)
+#define MOD_SEL0_ADGB_C ((uint32_t)2U << 29U)
+#define MOD_SEL0_DRIF0_A ((uint32_t)0U << 28U)
+#define MOD_SEL0_DRIF0_B ((uint32_t)1U << 28U)
+#define MOD_SEL0_FM_A ((uint32_t)0U << 26U)
+#define MOD_SEL0_FM_B ((uint32_t)1U << 26U)
+#define MOD_SEL0_FM_C ((uint32_t)2U << 26U)
+#define MOD_SEL0_FSO_A ((uint32_t)0U << 25U)
+#define MOD_SEL0_FSO_B ((uint32_t)1U << 25U)
+#define MOD_SEL0_HSCIF0_A ((uint32_t)0U << 24U)
+#define MOD_SEL0_HSCIF0_B ((uint32_t)1U << 24U)
+#define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 23U)
+#define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 23U)
+#define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 22U)
+#define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 22U)
+#define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U)
+#define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U)
+#define MOD_SEL0_I2C1_C ((uint32_t)2U << 20U)
+#define MOD_SEL0_I2C1_D ((uint32_t)3U << 20U)
+#define MOD_SEL0_I2C2_A ((uint32_t)0U << 17U)
+#define MOD_SEL0_I2C2_B ((uint32_t)1U << 17U)
+#define MOD_SEL0_I2C2_C ((uint32_t)2U << 17U)
+#define MOD_SEL0_I2C2_D ((uint32_t)3U << 17U)
+#define MOD_SEL0_I2C2_E ((uint32_t)4U << 17U)
+#define MOD_SEL0_NDFC_A ((uint32_t)0U << 16U)
+#define MOD_SEL0_NDFC_B ((uint32_t)1U << 16U)
+#define MOD_SEL0_PWM0_A ((uint32_t)0U << 15U)
+#define MOD_SEL0_PWM0_B ((uint32_t)1U << 15U)
+#define MOD_SEL0_PWM1_A ((uint32_t)0U << 14U)
+#define MOD_SEL0_PWM1_B ((uint32_t)1U << 14U)
+#define MOD_SEL0_PWM2_A ((uint32_t)0U << 12U)
+#define MOD_SEL0_PWM2_B ((uint32_t)1U << 12U)
+#define MOD_SEL0_PWM2_C ((uint32_t)2U << 12U)
+#define MOD_SEL0_PWM3_A ((uint32_t)0U << 10U)
+#define MOD_SEL0_PWM3_B ((uint32_t)1U << 10U)
+#define MOD_SEL0_PWM3_C ((uint32_t)2U << 10U)
+#define MOD_SEL0_PWM4_A ((uint32_t)0U << 9U)
+#define MOD_SEL0_PWM4_B ((uint32_t)1U << 9U)
+#define MOD_SEL0_PWM5_A ((uint32_t)0U << 8U)
+#define MOD_SEL0_PWM5_B ((uint32_t)1U << 8U)
+#define MOD_SEL0_PWM6_A ((uint32_t)0U << 7U)
+#define MOD_SEL0_PWM6_B ((uint32_t)1U << 7U)
+#define MOD_SEL0_REMOCON_A ((uint32_t)0U << 5U)
+#define MOD_SEL0_REMOCON_B ((uint32_t)1U << 5U)
+#define MOD_SEL0_REMOCON_C ((uint32_t)2U << 5U)
+#define MOD_SEL0_SCIF_A ((uint32_t)0U << 4U)
+#define MOD_SEL0_SCIF_B ((uint32_t)1U << 4U)
+#define MOD_SEL0_SCIF0_A ((uint32_t)0U << 3U)
+#define MOD_SEL0_SCIF0_B ((uint32_t)1U << 3U)
+#define MOD_SEL0_SCIF2_A ((uint32_t)0U << 2U)
+#define MOD_SEL0_SCIF2_B ((uint32_t)1U << 2U)
+#define MOD_SEL0_SPEED_PULSE_IF_A ((uint32_t)0U << 0U)
+#define MOD_SEL0_SPEED_PULSE_IF_B ((uint32_t)1U << 0U)
+#define MOD_SEL0_SPEED_PULSE_IF_C ((uint32_t)2U << 0U)
+#define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 31U)
+#define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 31U)
+#define MOD_SEL1_SSI2_A ((uint32_t)0U << 30U)
+#define MOD_SEL1_SSI2_B ((uint32_t)1U << 30U)
+#define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 29U)
+#define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 29U)
+#define MOD_SEL1_USB20_CH0_A ((uint32_t)0U << 28U)
+#define MOD_SEL1_USB20_CH0_B ((uint32_t)1U << 28U)
+#define MOD_SEL1_DRIF2_A ((uint32_t)0U << 26U)
+#define MOD_SEL1_DRIF2_B ((uint32_t)1U << 26U)
+#define MOD_SEL1_DRIF3_A ((uint32_t)0U << 25U)
+#define MOD_SEL1_DRIF3_B ((uint32_t)1U << 25U)
+#define MOD_SEL1_HSCIF3_A ((uint32_t)0U << 22U)
+#define MOD_SEL1_HSCIF3_B ((uint32_t)1U << 22U)
+#define MOD_SEL1_HSCIF3_C ((uint32_t)2U << 22U)
+#define MOD_SEL1_HSCIF3_D ((uint32_t)3U << 22U)
+#define MOD_SEL1_HSCIF3_E ((uint32_t)4U << 22U)
+#define MOD_SEL1_HSCIF4_A ((uint32_t)0U << 19U)
+#define MOD_SEL1_HSCIF4_B ((uint32_t)1U << 19U)
+#define MOD_SEL1_HSCIF4_C ((uint32_t)2U << 19U)
+#define MOD_SEL1_HSCIF4_D ((uint32_t)3U << 19U)
+#define MOD_SEL1_HSCIF4_E ((uint32_t)4U << 19U)
+#define MOD_SEL1_I2C6_A ((uint32_t)0U << 18U)
+#define MOD_SEL1_I2C6_B ((uint32_t)1U << 18U)
+#define MOD_SEL1_I2C7_A ((uint32_t)0U << 17U)
+#define MOD_SEL1_I2C7_B ((uint32_t)1U << 17U)
+#define MOD_SEL1_MSIOF2_A ((uint32_t)0U << 16U)
+#define MOD_SEL1_MSIOF2_B ((uint32_t)1U << 16U)
+#define MOD_SEL1_MSIOF3_A ((uint32_t)0U << 15U)
+#define MOD_SEL1_MSIOF3_B ((uint32_t)1U << 15U)
+#define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
+#define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
+#define MOD_SEL1_SCIF3_C ((uint32_t)2U << 13U)
+#define MOD_SEL1_SCIF4_A ((uint32_t)0U << 11U)
+#define MOD_SEL1_SCIF4_B ((uint32_t)1U << 11U)
+#define MOD_SEL1_SCIF4_C ((uint32_t)2U << 11U)
+#define MOD_SEL1_SCIF5_A ((uint32_t)0U << 9U)
+#define MOD_SEL1_SCIF5_B ((uint32_t)1U << 9U)
+#define MOD_SEL1_SCIF5_C ((uint32_t)2U << 9U)
+#define MOD_SEL1_VIN4_A ((uint32_t)0U << 8U)
+#define MOD_SEL1_VIN4_B ((uint32_t)1U << 8U)
+#define MOD_SEL1_VIN5_A ((uint32_t)0U << 7U)
+#define MOD_SEL1_VIN5_B ((uint32_t)1U << 7U)
+#define MOD_SEL1_ADGC_A ((uint32_t)0U << 5U)
+#define MOD_SEL1_ADGC_B ((uint32_t)1U << 5U)
+#define MOD_SEL1_ADGC_C ((uint32_t)2U << 5U)
+#define MOD_SEL1_SSI9_A ((uint32_t)0U << 4U)
+#define MOD_SEL1_SSI9_B ((uint32_t)1U << 4U)
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+ mmio_write_32(PFC_PMMR, ~data);
+ mmio_write_32((uintptr_t)addr, data);
+}
+
+void pfc_init_g2e(void)
+{
+ uint32_t reg;
+
+ /* initialize module select */
+ pfc_reg_write(PFC_MOD_SEL0,
+ MOD_SEL0_ADGB_A |
+ MOD_SEL0_DRIF0_A |
+ MOD_SEL0_FM_A |
+ MOD_SEL0_FSO_A |
+ MOD_SEL0_HSCIF0_A |
+ MOD_SEL0_HSCIF1_A |
+ MOD_SEL0_HSCIF2_A |
+ MOD_SEL0_I2C1_A |
+ MOD_SEL0_I2C2_A |
+ MOD_SEL0_NDFC_A |
+ MOD_SEL0_PWM0_A |
+ MOD_SEL0_PWM1_A |
+ MOD_SEL0_PWM2_A |
+ MOD_SEL0_PWM3_A |
+ MOD_SEL0_PWM4_A |
+ MOD_SEL0_PWM5_A |
+ MOD_SEL0_PWM6_A |
+ MOD_SEL0_REMOCON_A |
+ MOD_SEL0_SCIF_A |
+ MOD_SEL0_SCIF0_A |
+ MOD_SEL0_SCIF2_A |
+ MOD_SEL0_SPEED_PULSE_IF_A);
+
+ pfc_reg_write(PFC_MOD_SEL1,
+ MOD_SEL1_SIMCARD_A |
+ MOD_SEL1_SSI2_A |
+ MOD_SEL1_TIMER_TMU_A |
+ MOD_SEL1_USB20_CH0_B |
+ MOD_SEL1_DRIF2_A |
+ MOD_SEL1_DRIF3_A |
+ MOD_SEL1_HSCIF3_C |
+ MOD_SEL1_HSCIF4_B |
+ MOD_SEL1_I2C6_A |
+ MOD_SEL1_I2C7_A |
+ MOD_SEL1_MSIOF2_A |
+ MOD_SEL1_MSIOF3_A |
+ MOD_SEL1_SCIF3_A |
+ MOD_SEL1_SCIF4_A |
+ MOD_SEL1_SCIF5_A |
+ MOD_SEL1_VIN4_A |
+ MOD_SEL1_VIN5_A |
+ MOD_SEL1_ADGC_A |
+ MOD_SEL1_SSI9_A);
+
+ /* initialize peripheral function select */
+ pfc_reg_write(PFC_IPSR0,
+ IPSR_28_FUNC(2) | /* HRX4_B */
+ IPSR_24_FUNC(2) | /* HTX4_B */
+ IPSR_20_FUNC(0) | /* QSPI1_SPCLK */
+ IPSR_16_FUNC(0) | /* QSPI0_IO3 */
+ IPSR_12_FUNC(0) | /* QSPI0_IO2 */
+ IPSR_8_FUNC(0) | /* QSPI0_MISO/IO1 */
+ IPSR_4_FUNC(0) | /* QSPI0_MOSI/IO0 */
+ IPSR_0_FUNC(0)); /* QSPI0_SPCLK */
+
+ pfc_reg_write(PFC_IPSR1,
+ IPSR_28_FUNC(0) | /* AVB_RD2 */
+ IPSR_24_FUNC(0) | /* AVB_RD1 */
+ IPSR_20_FUNC(0) | /* AVB_RD0 */
+ IPSR_16_FUNC(0) | /* RPC_RESET# */
+ IPSR_12_FUNC(0) | /* RPC_INT# */
+ IPSR_8_FUNC(0) | /* QSPI1_SSL */
+ IPSR_4_FUNC(2) | /* HRX3_C */
+ IPSR_0_FUNC(2)); /* HTX3_C */
+
+ pfc_reg_write(PFC_IPSR2,
+ IPSR_28_FUNC(1) | /* IRQ0 */
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(2) | /* AVB_LINK */
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(0) | /* AVB_MDC */
+ IPSR_4_FUNC(0) | /* AVB_MDIO */
+ IPSR_0_FUNC(0)); /* AVB_TXCREFCLK */
+
+ pfc_reg_write(PFC_IPSR3,
+ IPSR_28_FUNC(5) | /* DU_HSYNC */
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(5) | /* DU_DG4 */
+ IPSR_8_FUNC(5) | /* DU_DOTCLKOUT0 */
+ IPSR_4_FUNC(5) | /* DU_DISP */
+ IPSR_0_FUNC(1)); /* IRQ1 */
+
+ pfc_reg_write(PFC_IPSR4,
+ IPSR_28_FUNC(5) | /* DU_DB5 */
+ IPSR_24_FUNC(5) | /* DU_DB4 */
+ IPSR_20_FUNC(5) | /* DU_DB3 */
+ IPSR_16_FUNC(5) | /* DU_DB2 */
+ IPSR_12_FUNC(5) | /* DU_DG6 */
+ IPSR_8_FUNC(5) | /* DU_VSYNC */
+ IPSR_4_FUNC(5) | /* DU_DG5 */
+ IPSR_0_FUNC(5)); /* DU_DG7 */
+
+ pfc_reg_write(PFC_IPSR5,
+ IPSR_28_FUNC(5) | /* DU_DR3 */
+ IPSR_24_FUNC(5) | /* DU_DB7 */
+ IPSR_20_FUNC(5) | /* DU_DR2 */
+ IPSR_16_FUNC(5) | /* DU_DR1 */
+ IPSR_12_FUNC(5) | /* DU_DR0 */
+ IPSR_8_FUNC(5) | /* DU_DB1 */
+ IPSR_4_FUNC(5) | /* DU_DB0 */
+ IPSR_0_FUNC(5)); /* DU_DB6 */
+
+ pfc_reg_write(PFC_IPSR6,
+ IPSR_28_FUNC(5) | /* DU_DG1 */
+ IPSR_24_FUNC(5) | /* DU_DG0 */
+ IPSR_20_FUNC(5) | /* DU_DR7 */
+ IPSR_16_FUNC(1) | /* CANFD1_RX */
+ IPSR_12_FUNC(5) | /* DU_DR6 */
+ IPSR_8_FUNC(5) | /* DU_DR5 */
+ IPSR_4_FUNC(1) | /* CANFD1_TX */
+ IPSR_0_FUNC(5)); /* DU_DR4 */
+
+ pfc_reg_write(PFC_IPSR7,
+ IPSR_28_FUNC(0) | /* SD0_CLK */
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(5) | /* DU_DOTCLKIN0 */
+ IPSR_16_FUNC(5) | /* DU_DG3 */
+ IPSR_12_FUNC(1) | /* CAN_CLK */
+ IPSR_8_FUNC(1) | /* CANFD0_RX */
+ IPSR_4_FUNC(1) | /* CANFD0_TX */
+ IPSR_0_FUNC(5)); /* DU_DG2 */
+
+ pfc_reg_write(PFC_IPSR8,
+ IPSR_28_FUNC(0) | /* SD1_DAT0 */
+ IPSR_24_FUNC(0) | /* SD1_CMD */
+ IPSR_20_FUNC(0) | /* SD1_CLK */
+ IPSR_16_FUNC(0) | /* SD0_DAT3 */
+ IPSR_12_FUNC(0) | /* SD0_DAT2 */
+ IPSR_8_FUNC(0) | /* SD0_DAT1 */
+ IPSR_4_FUNC(0) | /* SD0_DAT0 */
+ IPSR_0_FUNC(0)); /* SD0_CMD */
+
+ pfc_reg_write(PFC_IPSR9,
+ IPSR_28_FUNC(0) | /* SD3_DAT2 */
+ IPSR_24_FUNC(0) | /* SD3_DAT1 */
+ IPSR_20_FUNC(0) | /* SD3_DAT0 */
+ IPSR_16_FUNC(0) | /* SD3_CMD */
+ IPSR_12_FUNC(0) | /* SD3_CLK */
+ IPSR_8_FUNC(0) | /* SD1_DAT3 */
+ IPSR_4_FUNC(0) | /* SD1_DAT2 */
+ IPSR_0_FUNC(0)); /* SD1_DAT1 */
+
+ pfc_reg_write(PFC_IPSR10,
+ IPSR_24_FUNC(0) | /* SD0_CD */
+ IPSR_20_FUNC(0) | /* SD3_DS */
+ IPSR_16_FUNC(0) | /* SD3_DAT7 */
+ IPSR_12_FUNC(0) | /* SD3_DAT6 */
+ IPSR_8_FUNC(0) | /* SD3_DAT5 */
+ IPSR_4_FUNC(0) | /* SD3_DAT4 */
+ IPSR_0_FUNC(0)); /* SD3_DAT3 */
+
+ pfc_reg_write(PFC_IPSR11,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(8) | /* USB0_ID */
+ IPSR_20_FUNC(2) | /* AUDIO_CLKOUT1_A */
+ IPSR_16_FUNC(0) | /* CTS0#_A */
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(0) | /* SD1_WP */
+ IPSR_0_FUNC(0)); /* SD1_CD */
+
+ pfc_reg_write(PFC_IPSR12,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) | /* RX2_A */
+ IPSR_8_FUNC(0) | /* TX2_A */
+ IPSR_4_FUNC(0) | /* SCK2_A */
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR13,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(4) | /* SDA1_B */
+ IPSR_12_FUNC(4) | /* SCL1_B */
+ IPSR_8_FUNC(0) | /* SSI_SDATA9 */
+ IPSR_4_FUNC(1) | /* HTX2_A */
+ IPSR_0_FUNC(1)); /* HRX2_A */
+
+ pfc_reg_write(PFC_IPSR14,
+ IPSR_28_FUNC(0) | /* SSI_SCK5 */
+ IPSR_24_FUNC(0) | /* SSI_SDATA4 */
+ IPSR_20_FUNC(0) | /* SSI_SDATA3 */
+ IPSR_16_FUNC(0) | /* SSI_WS349 */
+ IPSR_12_FUNC(0) | /* SSI_SCK349 */
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(0) | /* SSI_SDATA1 */
+ IPSR_0_FUNC(0));/* SSI_SDATA0 */
+
+ pfc_reg_write(PFC_IPSR15,
+ IPSR_28_FUNC(0) | /* USB30_OVC */
+ IPSR_24_FUNC(0) | /* USB30_PWEN */
+ IPSR_20_FUNC(0) | /* AUDIO_CLKA */
+ IPSR_16_FUNC(1) | /* HRTS2#_A */
+ IPSR_12_FUNC(1) | /* HCTS2#_A */
+ IPSR_8_FUNC(3) | /* TPU0TO1 */
+ IPSR_4_FUNC(3) | /* TPU0TO0 */
+ IPSR_0_FUNC(0)); /* SSI_WS5 */
+
+ /* initialize GPIO/peripheral function select */
+ pfc_reg_write(PFC_GPSR0,
+ GPSR0_SCL4 |
+ GPSR0_D15 |
+ GPSR0_D14 |
+ GPSR0_D13 |
+ GPSR0_D12 |
+ GPSR0_D11 |
+ GPSR0_D10 |
+ GPSR0_D9 |
+ GPSR0_D8 |
+ GPSR0_D7 |
+ GPSR0_D6 |
+ GPSR0_D5 |
+ GPSR0_D4 |
+ GPSR0_D3 |
+ GPSR0_D2 |
+ GPSR0_D1 |
+ GPSR0_D0);
+
+ pfc_reg_write(PFC_GPSR1,
+ GPSR1_WE0 |
+ GPSR1_CS0 |
+ GPSR1_A19 |
+ GPSR1_A18 |
+ GPSR1_A17 |
+ GPSR1_A16 |
+ GPSR1_A15 |
+ GPSR1_A14 |
+ GPSR1_A13 |
+ GPSR1_A12 |
+ GPSR1_A11 |
+ GPSR1_A10 |
+ GPSR1_A9 |
+ GPSR1_A8 |
+ GPSR1_A4 |
+ GPSR1_A3 |
+ GPSR1_A2 |
+ GPSR1_A1 |
+ GPSR1_A0);
+
+ pfc_reg_write(PFC_GPSR2,
+ GPSR2_BIT27_REVERSED |
+ GPSR2_BIT26_REVERSED |
+ GPSR2_AVB_PHY_INT |
+ GPSR2_AVB_TXCREFCLK |
+ GPSR2_AVB_RD3 |
+ GPSR2_AVB_RD2 |
+ GPSR2_AVB_RD1 |
+ GPSR2_AVB_RD0 |
+ GPSR2_AVB_RXC |
+ GPSR2_AVB_RX_CTL |
+ GPSR2_RPC_RESET |
+ GPSR2_RPC_RPC_INT |
+ GPSR2_QSPI1_IO3 |
+ GPSR2_QSPI1_IO2 |
+ GPSR2_QSPI1_MISO_IO1 |
+ GPSR2_QSPI1_MOSI_IO0 |
+ GPSR2_QSPI0_SSL |
+ GPSR2_QSPI0_IO3 |
+ GPSR2_QSPI0_IO2 |
+ GPSR2_QSPI0_MISO_IO1 |
+ GPSR2_QSPI0_MOSI_IO0 |
+ GPSR2_QSPI0_SPCLK);
+
+ pfc_reg_write(PFC_GPSR3,
+ GPSR3_SD0_CD |
+ GPSR3_SD1_DAT3 |
+ GPSR3_SD1_DAT2 |
+ GPSR3_SD1_DAT1 |
+ GPSR3_SD1_DAT0 |
+ GPSR3_SD1_CMD |
+ GPSR3_SD1_CLK |
+ GPSR3_SD0_DAT3 |
+ GPSR3_SD0_DAT2 |
+ GPSR3_SD0_DAT1 |
+ GPSR3_SD0_DAT0 |
+ GPSR3_SD0_CMD |
+ GPSR3_SD0_CLK);
+
+ pfc_reg_write(PFC_GPSR4,
+ GPSR4_SD3_DAT3 |
+ GPSR4_SD3_DAT2 |
+ GPSR4_SD3_DAT1 |
+ GPSR4_SD3_DAT0 |
+ GPSR4_SD3_CMD |
+ GPSR4_SD3_CLK);
+
+ pfc_reg_write(PFC_GPSR5,
+ GPSR5_MLB_SIG |
+ GPSR5_MLB_CLK |
+ GPSR5_SSI_SDATA9 |
+ GPSR5_MSIOF0_SS2 |
+ GPSR5_MSIOF0_SS1 |
+ GPSR5_MSIOF0_SYNC |
+ GPSR5_MSIOF0_TXD |
+ GPSR5_MSIOF0_RXD |
+ GPSR5_MSIOF0_SCK |
+ GPSR5_RX2_A |
+ GPSR5_TX2_A |
+ GPSR5_RTS0_A |
+ GPSR5_SCK0_A);
+
+ pfc_reg_write(PFC_GPSR6,
+ GPSR6_USB30_PWEN |
+ GPSR6_SSI_SDATA6 |
+ GPSR6_SSI_WS6 |
+ GPSR6_SSI_SCK6 |
+ GPSR6_SSI_SDATA5 |
+ GPSR6_SSI_SCK5 |
+ GPSR6_SSI_SDATA4 |
+ GPSR6_USB30_OVC |
+ GPSR6_AUDIO_CLKA |
+ GPSR6_SSI_SDATA3 |
+ GPSR6_SSI_WS349 |
+ GPSR6_SSI_SCK349 |
+ GPSR6_SSI_SDATA0 |
+ GPSR6_SSI_WS01239 |
+ GPSR6_SSI_SCK01239);
+
+ /* initialize POC control */
+ reg = mmio_read_32(PFC_POCCTRL0);
+ reg = (reg & POCCTRL0_MASK) |
+ POC_SD1_DAT3_33V |
+ POC_SD1_DAT2_33V |
+ POC_SD1_DAT1_33V |
+ POC_SD1_DAT0_33V |
+ POC_SD1_CMD_33V |
+ POC_SD1_CLK_33V |
+ POC_SD0_DAT3_33V |
+ POC_SD0_DAT2_33V |
+ POC_SD0_DAT1_33V |
+ POC_SD0_DAT0_33V |
+ POC_SD0_CMD_33V |
+ POC_SD0_CLK_33V;
+ pfc_reg_write(PFC_POCCTRL0, reg);
+
+ reg = mmio_read_32(PFC_POCCTRL2);
+ reg = ((reg & POCCTRL2_MASK) & ~POC2_VREF_33V);
+ pfc_reg_write(PFC_POCCTRL2, reg);
+
+ /* initialize LSI pin pull-up/down control */
+ pfc_reg_write(PFC_PUD0, 0x00080000U);
+ pfc_reg_write(PFC_PUD1, 0xCE398464U);
+ pfc_reg_write(PFC_PUD2, 0xA4C380F4U);
+ pfc_reg_write(PFC_PUD3, 0x0000079FU);
+ pfc_reg_write(PFC_PUD4, 0xFFF0FFFFU);
+ pfc_reg_write(PFC_PUD5, 0x40000000U);
+
+ /* initialize LSI pin pull-enable register */
+ pfc_reg_write(PFC_PUEN0, 0x00000000U);
+ pfc_reg_write(PFC_PUEN1, 0x00300000U);
+ pfc_reg_write(PFC_PUEN2, 0x00400074U);
+ pfc_reg_write(PFC_PUEN3, 0x00000000U);
+ pfc_reg_write(PFC_PUEN4, 0x07900600U);
+ pfc_reg_write(PFC_PUEN5, 0x00000000U);
+
+ /* initialize positive/negative logic select */
+ mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+
+ /* initialize general IO/interrupt switching */
+ mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+
+ /* initialize general output register */
+ mmio_write_32(GPIO_OUTDT0, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT2, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT3, 0x00006000U);
+ mmio_write_32(GPIO_OUTDT5, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT6, 0x00000000U);
+
+ /* initialize general input/output switching */
+ mmio_write_32(GPIO_INOUTSEL0, 0x00020000U);
+ mmio_write_32(GPIO_INOUTSEL1, 0x00100000U);
+ mmio_write_32(GPIO_INOUTSEL2, 0x03000000U);
+ mmio_write_32(GPIO_INOUTSEL3, 0x0000E000U);
+ mmio_write_32(GPIO_INOUTSEL4, 0x00000440U);
+ mmio_write_32(GPIO_INOUTSEL5, 0x00080000U);
+ mmio_write_32(GPIO_INOUTSEL6, 0x00000010U);
+}
diff --git a/drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.h b/drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.h
new file mode 100644
index 0000000..677591a
--- /dev/null
+++ b/drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PFC_INIT_G2E_H
+#define PFC_INIT_G2E_H
+
+void pfc_init_g2e(void);
+
+#endif /* PFC_INIT_G2E_H */
diff --git a/drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.c b/drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.c
new file mode 100644
index 0000000..90a1c99
--- /dev/null
+++ b/drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.c
@@ -0,0 +1,1310 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <lib/mmio.h>
+
+#include "pfc_init_g2h.h"
+#include "rcar_def.h"
+#include "../pfc_regs.h"
+
+#define GPSR0_D15 BIT(15)
+#define GPSR0_D14 BIT(14)
+#define GPSR0_D13 BIT(13)
+#define GPSR0_D12 BIT(12)
+#define GPSR0_D11 BIT(11)
+#define GPSR0_D10 BIT(10)
+#define GPSR0_D9 BIT(9)
+#define GPSR0_D8 BIT(8)
+#define GPSR0_D7 BIT(7)
+#define GPSR0_D6 BIT(6)
+#define GPSR0_D5 BIT(5)
+#define GPSR0_D4 BIT(4)
+#define GPSR0_D3 BIT(3)
+#define GPSR0_D2 BIT(2)
+#define GPSR0_D1 BIT(1)
+#define GPSR0_D0 BIT(0)
+#define GPSR1_CLKOUT BIT(28)
+#define GPSR1_EX_WAIT0_A BIT(27)
+#define GPSR1_WE1 BIT(26)
+#define GPSR1_WE0 BIT(25)
+#define GPSR1_RD_WR BIT(24)
+#define GPSR1_RD BIT(23)
+#define GPSR1_BS BIT(22)
+#define GPSR1_CS1_A26 BIT(21)
+#define GPSR1_CS0 BIT(20)
+#define GPSR1_A19 BIT(19)
+#define GPSR1_A18 BIT(18)
+#define GPSR1_A17 BIT(17)
+#define GPSR1_A16 BIT(16)
+#define GPSR1_A15 BIT(15)
+#define GPSR1_A14 BIT(14)
+#define GPSR1_A13 BIT(13)
+#define GPSR1_A12 BIT(12)
+#define GPSR1_A11 BIT(11)
+#define GPSR1_A10 BIT(10)
+#define GPSR1_A9 BIT(9)
+#define GPSR1_A8 BIT(8)
+#define GPSR1_A7 BIT(7)
+#define GPSR1_A6 BIT(6)
+#define GPSR1_A5 BIT(5)
+#define GPSR1_A4 BIT(4)
+#define GPSR1_A3 BIT(3)
+#define GPSR1_A2 BIT(2)
+#define GPSR1_A1 BIT(1)
+#define GPSR1_A0 BIT(0)
+#define GPSR2_AVB_AVTP_CAPTURE_A BIT(14)
+#define GPSR2_AVB_AVTP_MATCH_A BIT(13)
+#define GPSR2_AVB_LINK BIT(12)
+#define GPSR2_AVB_PHY_INT BIT(11)
+#define GPSR2_AVB_MAGIC BIT(10)
+#define GPSR2_AVB_MDC BIT(9)
+#define GPSR2_PWM2_A BIT(8)
+#define GPSR2_PWM1_A BIT(7)
+#define GPSR2_PWM0 BIT(6)
+#define GPSR2_IRQ5 BIT(5)
+#define GPSR2_IRQ4 BIT(4)
+#define GPSR2_IRQ3 BIT(3)
+#define GPSR2_IRQ2 BIT(2)
+#define GPSR2_IRQ1 BIT(1)
+#define GPSR2_IRQ0 BIT(0)
+#define GPSR3_SD1_WP BIT(15)
+#define GPSR3_SD1_CD BIT(14)
+#define GPSR3_SD0_WP BIT(13)
+#define GPSR3_SD0_CD BIT(12)
+#define GPSR3_SD1_DAT3 BIT(11)
+#define GPSR3_SD1_DAT2 BIT(10)
+#define GPSR3_SD1_DAT1 BIT(9)
+#define GPSR3_SD1_DAT0 BIT(8)
+#define GPSR3_SD1_CMD BIT(7)
+#define GPSR3_SD1_CLK BIT(6)
+#define GPSR3_SD0_DAT3 BIT(5)
+#define GPSR3_SD0_DAT2 BIT(4)
+#define GPSR3_SD0_DAT1 BIT(3)
+#define GPSR3_SD0_DAT0 BIT(2)
+#define GPSR3_SD0_CMD BIT(1)
+#define GPSR3_SD0_CLK BIT(0)
+#define GPSR4_SD3_DS BIT(17)
+#define GPSR4_SD3_DAT7 BIT(16)
+#define GPSR4_SD3_DAT6 BIT(15)
+#define GPSR4_SD3_DAT5 BIT(14)
+#define GPSR4_SD3_DAT4 BIT(13)
+#define GPSR4_SD3_DAT3 BIT(12)
+#define GPSR4_SD3_DAT2 BIT(11)
+#define GPSR4_SD3_DAT1 BIT(10)
+#define GPSR4_SD3_DAT0 BIT(9)
+#define GPSR4_SD3_CMD BIT(8)
+#define GPSR4_SD3_CLK BIT(7)
+#define GPSR4_SD2_DS BIT(6)
+#define GPSR4_SD2_DAT3 BIT(5)
+#define GPSR4_SD2_DAT2 BIT(4)
+#define GPSR4_SD2_DAT1 BIT(3)
+#define GPSR4_SD2_DAT0 BIT(2)
+#define GPSR4_SD2_CMD BIT(1)
+#define GPSR4_SD2_CLK BIT(0)
+#define GPSR5_MLB_DAT BIT(25)
+#define GPSR5_MLB_SIG BIT(24)
+#define GPSR5_MLB_CLK BIT(23)
+#define GPSR5_MSIOF0_RXD BIT(22)
+#define GPSR5_MSIOF0_SS2 BIT(21)
+#define GPSR5_MSIOF0_TXD BIT(20)
+#define GPSR5_MSIOF0_SS1 BIT(19)
+#define GPSR5_MSIOF0_SYNC BIT(18)
+#define GPSR5_MSIOF0_SCK BIT(17)
+#define GPSR5_HRTS0 BIT(16)
+#define GPSR5_HCTS0 BIT(15)
+#define GPSR5_HTX0 BIT(14)
+#define GPSR5_HRX0 BIT(13)
+#define GPSR5_HSCK0 BIT(12)
+#define GPSR5_RX2_A BIT(11)
+#define GPSR5_TX2_A BIT(10)
+#define GPSR5_SCK2 BIT(9)
+#define GPSR5_RTS1 BIT(8)
+#define GPSR5_CTS1 BIT(7)
+#define GPSR5_TX1_A BIT(6)
+#define GPSR5_RX1_A BIT(5)
+#define GPSR5_RTS0 BIT(4)
+#define GPSR5_CTS0 BIT(3)
+#define GPSR5_TX0 BIT(2)
+#define GPSR5_RX0 BIT(1)
+#define GPSR5_SCK0 BIT(0)
+#define GPSR6_USB31_OVC BIT(31)
+#define GPSR6_USB31_PWEN BIT(30)
+#define GPSR6_USB30_OVC BIT(29)
+#define GPSR6_USB30_PWEN BIT(28)
+#define GPSR6_USB1_OVC BIT(27)
+#define GPSR6_USB1_PWEN BIT(26)
+#define GPSR6_USB0_OVC BIT(25)
+#define GPSR6_USB0_PWEN BIT(24)
+#define GPSR6_AUDIO_CLKB_B BIT(23)
+#define GPSR6_AUDIO_CLKA_A BIT(22)
+#define GPSR6_SSI_SDATA9_A BIT(21)
+#define GPSR6_SSI_SDATA8 BIT(20)
+#define GPSR6_SSI_SDATA7 BIT(19)
+#define GPSR6_SSI_WS78 BIT(18)
+#define GPSR6_SSI_SCK78 BIT(17)
+#define GPSR6_SSI_SDATA6 BIT(16)
+#define GPSR6_SSI_WS6 BIT(15)
+#define GPSR6_SSI_SCK6 BIT(14)
+#define GPSR6_SSI_SDATA5 BIT(13)
+#define GPSR6_SSI_WS5 BIT(12)
+#define GPSR6_SSI_SCK5 BIT(11)
+#define GPSR6_SSI_SDATA4 BIT(10)
+#define GPSR6_SSI_WS4 BIT(9)
+#define GPSR6_SSI_SCK4 BIT(8)
+#define GPSR6_SSI_SDATA3 BIT(7)
+#define GPSR6_SSI_WS34 BIT(6)
+#define GPSR6_SSI_SCK34 BIT(5)
+#define GPSR6_SSI_SDATA2_A BIT(4)
+#define GPSR6_SSI_SDATA1_A BIT(3)
+#define GPSR6_SSI_SDATA0 BIT(2)
+#define GPSR6_SSI_WS0129 BIT(1)
+#define GPSR6_SSI_SCK0129 BIT(0)
+#define GPSR7_AVS2 BIT(1)
+#define GPSR7_AVS1 BIT(0)
+
+#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
+
+#define POC_SD3_DS_33V BIT(29)
+#define POC_SD3_DAT7_33V BIT(28)
+#define POC_SD3_DAT6_33V BIT(27)
+#define POC_SD3_DAT5_33V BIT(26)
+#define POC_SD3_DAT4_33V BIT(25)
+#define POC_SD3_DAT3_33V BIT(24)
+#define POC_SD3_DAT2_33V BIT(23)
+#define POC_SD3_DAT1_33V BIT(22)
+#define POC_SD3_DAT0_33V BIT(21)
+#define POC_SD3_CMD_33V BIT(20)
+#define POC_SD3_CLK_33V BIT(19)
+#define POC_SD2_DS_33V BIT(18)
+#define POC_SD2_DAT3_33V BIT(17)
+#define POC_SD2_DAT2_33V BIT(16)
+#define POC_SD2_DAT1_33V BIT(15)
+#define POC_SD2_DAT0_33V BIT(14)
+#define POC_SD2_CMD_33V BIT(13)
+#define POC_SD2_CLK_33V BIT(12)
+#define POC_SD1_DAT3_33V BIT(11)
+#define POC_SD1_DAT2_33V BIT(10)
+#define POC_SD1_DAT1_33V BIT(9)
+#define POC_SD1_DAT0_33V BIT(8)
+#define POC_SD1_CMD_33V BIT(7)
+#define POC_SD1_CLK_33V BIT(6)
+#define POC_SD0_DAT3_33V BIT(5)
+#define POC_SD0_DAT2_33V BIT(4)
+#define POC_SD0_DAT1_33V BIT(3)
+#define POC_SD0_DAT0_33V BIT(2)
+#define POC_SD0_CMD_33V BIT(1)
+#define POC_SD0_CLK_33V BIT(0)
+
+#define DRVCTRL0_MASK (0xCCCCCCCCU)
+#define DRVCTRL1_MASK (0xCCCCCCC8U)
+#define DRVCTRL2_MASK (0x88888888U)
+#define DRVCTRL3_MASK (0x88888888U)
+#define DRVCTRL4_MASK (0x88888888U)
+#define DRVCTRL5_MASK (0x88888888U)
+#define DRVCTRL6_MASK (0x88888888U)
+#define DRVCTRL7_MASK (0x88888888U)
+#define DRVCTRL8_MASK (0x88888888U)
+#define DRVCTRL9_MASK (0x88888888U)
+#define DRVCTRL10_MASK (0x88888888U)
+#define DRVCTRL11_MASK (0x888888CCU)
+#define DRVCTRL12_MASK (0xCCCFFFCFU)
+#define DRVCTRL13_MASK (0xCC888888U)
+#define DRVCTRL14_MASK (0x88888888U)
+#define DRVCTRL15_MASK (0x88888888U)
+#define DRVCTRL16_MASK (0x88888888U)
+#define DRVCTRL17_MASK (0x88888888U)
+#define DRVCTRL18_MASK (0x88888888U)
+#define DRVCTRL19_MASK (0x88888888U)
+#define DRVCTRL20_MASK (0x88888888U)
+#define DRVCTRL21_MASK (0x88888888U)
+#define DRVCTRL22_MASK (0x88888888U)
+#define DRVCTRL23_MASK (0x88888888U)
+#define DRVCTRL24_MASK (0x8888888FU)
+
+#define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL11_GP7_02(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL11_GP7_03(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U)
+
+#define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U)
+#define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U)
+#define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U)
+#define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U)
+#define MOD_SEL0_MSIOF3_E ((uint32_t)4U << 29U)
+#define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U)
+#define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U)
+#define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U)
+#define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U)
+#define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U)
+#define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U)
+#define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U)
+#define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U)
+#define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U)
+#define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U)
+#define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U)
+#define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U)
+#define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U)
+#define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U)
+#define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U)
+#define MOD_SEL0_I2C2_A ((uint32_t)0U << 21U)
+#define MOD_SEL0_I2C2_B ((uint32_t)1U << 21U)
+#define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U)
+#define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U)
+#define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 19U)
+#define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 19U)
+#define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 17U)
+#define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 17U)
+#define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 17U)
+#define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 17U)
+#define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 16U)
+#define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 16U)
+#define MOD_SEL0_FSO_A ((uint32_t)0U << 15U)
+#define MOD_SEL0_FSO_B ((uint32_t)1U << 15U)
+#define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 13U)
+#define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 13U)
+#define MOD_SEL0_HSCIF2_C ((uint32_t)2U << 13U)
+#define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 12U)
+#define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 12U)
+#define MOD_SEL0_DRIF3_A ((uint32_t)0U << 11U)
+#define MOD_SEL0_DRIF3_B ((uint32_t)1U << 11U)
+#define MOD_SEL0_DRIF2_A ((uint32_t)0U << 10U)
+#define MOD_SEL0_DRIF2_B ((uint32_t)1U << 10U)
+#define MOD_SEL0_DRIF1_A ((uint32_t)0U << 8U)
+#define MOD_SEL0_DRIF1_B ((uint32_t)1U << 8U)
+#define MOD_SEL0_DRIF1_C ((uint32_t)2U << 8U)
+#define MOD_SEL0_DRIF0_A ((uint32_t)0U << 6U)
+#define MOD_SEL0_DRIF0_B ((uint32_t)1U << 6U)
+#define MOD_SEL0_DRIF0_C ((uint32_t)2U << 6U)
+#define MOD_SEL0_CANFD0_A ((uint32_t)0U << 5U)
+#define MOD_SEL0_CANFD0_B ((uint32_t)1U << 5U)
+#define MOD_SEL0_ADG_A_A ((uint32_t)0U << 3U)
+#define MOD_SEL0_ADG_A_B ((uint32_t)1U << 3U)
+#define MOD_SEL0_ADG_A_C ((uint32_t)2U << 3U)
+#define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U)
+#define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U)
+#define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U)
+#define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U)
+#define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U)
+#define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U)
+#define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U)
+#define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U)
+#define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U)
+#define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U)
+#define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U)
+#define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U)
+#define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U)
+#define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U)
+#define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U)
+#define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U)
+#define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U)
+#define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U)
+#define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U)
+#define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U)
+#define MOD_SEL1_SSI_A ((uint32_t)0U << 20U)
+#define MOD_SEL1_SSI_B ((uint32_t)1U << 20U)
+#define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U)
+#define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U)
+#define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U)
+#define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U)
+#define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U)
+#define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U)
+#define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U)
+#define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U)
+#define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U)
+#define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U)
+#define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U)
+#define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
+#define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
+#define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U)
+#define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U)
+#define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U)
+#define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U)
+#define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U)
+#define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U)
+#define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U)
+#define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U)
+#define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U)
+#define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U)
+#define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U)
+#define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U)
+#define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U)
+#define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U)
+#define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U)
+#define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U)
+#define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U)
+#define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U)
+#define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U)
+#define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U)
+#define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U)
+#define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U)
+#define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U)
+#define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U)
+#define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U)
+#define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U)
+#define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U)
+#define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U)
+#define MOD_SEL2_FM_A ((uint32_t)0U << 27U)
+#define MOD_SEL2_FM_B ((uint32_t)1U << 27U)
+#define MOD_SEL2_FM_C ((uint32_t)2U << 27U)
+#define MOD_SEL2_FM_D ((uint32_t)3U << 27U)
+#define MOD_SEL2_SCIF5_A ((uint32_t)0U << 26U)
+#define MOD_SEL2_SCIF5_B ((uint32_t)1U << 26U)
+#define MOD_SEL2_I2C6_A ((uint32_t)0U << 23U)
+#define MOD_SEL2_I2C6_B ((uint32_t)1U << 23U)
+#define MOD_SEL2_I2C6_C ((uint32_t)2U << 23U)
+#define MOD_SEL2_NDF_A ((uint32_t)0U << 22U)
+#define MOD_SEL2_NDF_B ((uint32_t)1U << 22U)
+#define MOD_SEL2_SSI2_A ((uint32_t)0U << 21U)
+#define MOD_SEL2_SSI2_B ((uint32_t)1U << 21U)
+#define MOD_SEL2_SSI9_A ((uint32_t)0U << 20U)
+#define MOD_SEL2_SSI9_B ((uint32_t)1U << 20U)
+#define MOD_SEL2_TIMER_TMU2_A ((uint32_t)0U << 19U)
+#define MOD_SEL2_TIMER_TMU2_B ((uint32_t)1U << 19U)
+#define MOD_SEL2_ADG_B_A ((uint32_t)0U << 18U)
+#define MOD_SEL2_ADG_B_B ((uint32_t)1U << 18U)
+#define MOD_SEL2_ADG_C_A ((uint32_t)0U << 17U)
+#define MOD_SEL2_ADG_C_B ((uint32_t)1U << 17U)
+#define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U)
+#define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U)
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+ mmio_write_32(PFC_PMMR, ~data);
+ mmio_write_32((uintptr_t)addr, data);
+}
+
+void pfc_init_g2h(void)
+{
+ uint32_t reg;
+
+ /* initialize module select */
+ pfc_reg_write(PFC_MOD_SEL0,
+ MOD_SEL0_MSIOF3_A |
+ MOD_SEL0_MSIOF2_A |
+ MOD_SEL0_MSIOF1_A |
+ MOD_SEL0_LBSC_A |
+ MOD_SEL0_IEBUS_A |
+ MOD_SEL0_I2C2_A |
+ MOD_SEL0_I2C1_A |
+ MOD_SEL0_HSCIF4_A |
+ MOD_SEL0_HSCIF3_A |
+ MOD_SEL0_HSCIF1_A |
+ MOD_SEL0_FSO_A |
+ MOD_SEL0_HSCIF2_A |
+ MOD_SEL0_ETHERAVB_A |
+ MOD_SEL0_DRIF3_A |
+ MOD_SEL0_DRIF2_A |
+ MOD_SEL0_DRIF1_A |
+ MOD_SEL0_DRIF0_A |
+ MOD_SEL0_CANFD0_A |
+ MOD_SEL0_ADG_A_A);
+
+ pfc_reg_write(PFC_MOD_SEL1,
+ MOD_SEL1_TSIF1_A |
+ MOD_SEL1_TSIF0_A |
+ MOD_SEL1_TIMER_TMU_A |
+ MOD_SEL1_SSP1_1_A |
+ MOD_SEL1_SSP1_0_A |
+ MOD_SEL1_SSI_A |
+ MOD_SEL1_SPEED_PULSE_IF_A |
+ MOD_SEL1_SIMCARD_A |
+ MOD_SEL1_SDHI2_A |
+ MOD_SEL1_SCIF4_A |
+ MOD_SEL1_SCIF3_A |
+ MOD_SEL1_SCIF2_A |
+ MOD_SEL1_SCIF1_A |
+ MOD_SEL1_SCIF_A |
+ MOD_SEL1_REMOCON_A |
+ MOD_SEL1_RCAN0_A |
+ MOD_SEL1_PWM6_A |
+ MOD_SEL1_PWM5_A |
+ MOD_SEL1_PWM4_A |
+ MOD_SEL1_PWM3_A |
+ MOD_SEL1_PWM2_A |
+ MOD_SEL1_PWM1_A);
+
+ pfc_reg_write(PFC_MOD_SEL2,
+ MOD_SEL2_I2C_5_B |
+ MOD_SEL2_I2C_3_B |
+ MOD_SEL2_I2C_0_B |
+ MOD_SEL2_FM_A |
+ MOD_SEL2_SCIF5_A |
+ MOD_SEL2_I2C6_A |
+ MOD_SEL2_NDF_A |
+ MOD_SEL2_SSI2_A |
+ MOD_SEL2_SSI9_A |
+ MOD_SEL2_TIMER_TMU2_A |
+ MOD_SEL2_ADG_B_A |
+ MOD_SEL2_ADG_C_A |
+ MOD_SEL2_VIN4_A);
+
+ /* initialize peripheral function select */
+ pfc_reg_write(PFC_IPSR0,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR1,
+ IPSR_28_FUNC(6) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(3) |
+ IPSR_8_FUNC(3) |
+ IPSR_4_FUNC(3) |
+ IPSR_0_FUNC(3));
+
+ pfc_reg_write(PFC_IPSR2,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(6) |
+ IPSR_20_FUNC(6) |
+ IPSR_16_FUNC(6) |
+ IPSR_12_FUNC(6) |
+ IPSR_8_FUNC(6) |
+ IPSR_4_FUNC(6) |
+ IPSR_0_FUNC(6));
+
+ pfc_reg_write(PFC_IPSR3,
+ IPSR_28_FUNC(6) |
+ IPSR_24_FUNC(6) |
+ IPSR_20_FUNC(6) |
+ IPSR_16_FUNC(6) |
+ IPSR_12_FUNC(6) |
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR4,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(6) |
+ IPSR_4_FUNC(6) |
+ IPSR_0_FUNC(6));
+
+ pfc_reg_write(PFC_IPSR5,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(6) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR6,
+ IPSR_28_FUNC(6) |
+ IPSR_24_FUNC(6) |
+ IPSR_20_FUNC(6) |
+ IPSR_16_FUNC(6) |
+ IPSR_12_FUNC(6) |
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR7,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(6) |
+ IPSR_4_FUNC(6) |
+ IPSR_0_FUNC(6));
+
+ pfc_reg_write(PFC_IPSR8,
+ IPSR_28_FUNC(1) |
+ IPSR_24_FUNC(1) |
+ IPSR_20_FUNC(1) |
+ IPSR_16_FUNC(1) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR9,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR10,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR11,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(4) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR12,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(4) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR13,
+ IPSR_28_FUNC(8) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(3) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR14,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(3) |
+ IPSR_0_FUNC(8));
+
+ pfc_reg_write(PFC_IPSR15,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR16,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR17,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(1) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR18,
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ /* initialize GPIO/peripheral function select */
+ pfc_reg_write(PFC_GPSR0,
+ GPSR0_D15 |
+ GPSR0_D14 |
+ GPSR0_D13 |
+ GPSR0_D12 |
+ GPSR0_D11 |
+ GPSR0_D10 |
+ GPSR0_D9 |
+ GPSR0_D8 |
+ GPSR0_D7 |
+ GPSR0_D6 |
+ GPSR0_D5 |
+ GPSR0_D4 |
+ GPSR0_D3 |
+ GPSR0_D2 |
+ GPSR0_D0);
+
+ pfc_reg_write(PFC_GPSR1,
+ GPSR1_CLKOUT |
+ GPSR1_EX_WAIT0_A |
+ GPSR1_WE1 |
+ GPSR1_RD |
+ GPSR1_RD_WR |
+ GPSR1_CS0 |
+ GPSR1_A19 |
+ GPSR1_A18 |
+ GPSR1_A17 |
+ GPSR1_A16 |
+ GPSR1_A15 |
+ GPSR1_A14 |
+ GPSR1_A13 |
+ GPSR1_A12 |
+ GPSR1_A7 |
+ GPSR1_A6 |
+ GPSR1_A5 |
+ GPSR1_A4 |
+ GPSR1_A3 |
+ GPSR1_A2 |
+ GPSR1_A1 |
+ GPSR1_A0);
+
+ pfc_reg_write(PFC_GPSR2,
+ GPSR2_AVB_AVTP_CAPTURE_A |
+ GPSR2_AVB_AVTP_MATCH_A |
+ GPSR2_AVB_LINK |
+ GPSR2_AVB_PHY_INT |
+ GPSR2_AVB_MDC |
+ GPSR2_PWM2_A |
+ GPSR2_PWM1_A |
+ GPSR2_IRQ4 |
+ GPSR2_IRQ3 |
+ GPSR2_IRQ2 |
+ GPSR2_IRQ1 |
+ GPSR2_IRQ0);
+
+ pfc_reg_write(PFC_GPSR3,
+ GPSR3_SD0_CD |
+ GPSR3_SD1_DAT3 |
+ GPSR3_SD1_DAT2 |
+ GPSR3_SD1_DAT1 |
+ GPSR3_SD1_DAT0 |
+ GPSR3_SD0_DAT3 |
+ GPSR3_SD0_DAT2 |
+ GPSR3_SD0_DAT1 |
+ GPSR3_SD0_DAT0 |
+ GPSR3_SD0_CMD |
+ GPSR3_SD0_CLK);
+
+ pfc_reg_write(PFC_GPSR4,
+ GPSR4_SD3_DS |
+ GPSR4_SD3_DAT7 |
+ GPSR4_SD3_DAT6 |
+ GPSR4_SD3_DAT5 |
+ GPSR4_SD3_DAT4 |
+ GPSR4_SD3_DAT3 |
+ GPSR4_SD3_DAT2 |
+ GPSR4_SD3_DAT1 |
+ GPSR4_SD3_DAT0 |
+ GPSR4_SD3_CMD |
+ GPSR4_SD3_CLK |
+ GPSR4_SD2_DAT3 |
+ GPSR4_SD2_DAT2 |
+ GPSR4_SD2_DAT1 |
+ GPSR4_SD2_DAT0 |
+ GPSR4_SD2_CMD |
+ GPSR4_SD2_CLK);
+
+ pfc_reg_write(PFC_GPSR5,
+ GPSR5_MSIOF0_RXD |
+ GPSR5_MSIOF0_TXD |
+ GPSR5_MSIOF0_SYNC |
+ GPSR5_MSIOF0_SCK |
+ GPSR5_RX2_A |
+ GPSR5_TX2_A |
+ GPSR5_RTS1 |
+ GPSR5_CTS1 |
+ GPSR5_TX1_A |
+ GPSR5_RX1_A |
+ GPSR5_RTS0 |
+ GPSR5_SCK0);
+
+ pfc_reg_write(PFC_GPSR6,
+ GPSR6_AUDIO_CLKB_B |
+ GPSR6_AUDIO_CLKA_A |
+ GPSR6_SSI_WS6 |
+ GPSR6_SSI_SCK6 |
+ GPSR6_SSI_SDATA4 |
+ GPSR6_SSI_WS4 |
+ GPSR6_SSI_SCK4 |
+ GPSR6_SSI_SDATA1_A |
+ GPSR6_SSI_SDATA0 |
+ GPSR6_SSI_WS0129 |
+ GPSR6_SSI_SCK0129);
+
+ pfc_reg_write(PFC_GPSR7,
+ GPSR7_AVS2 |
+ GPSR7_AVS1);
+
+ /* initialize POC control register */
+ pfc_reg_write(PFC_POCCTRL0,
+ POC_SD0_DAT3_33V |
+ POC_SD0_DAT2_33V |
+ POC_SD0_DAT1_33V |
+ POC_SD0_DAT0_33V |
+ POC_SD0_CMD_33V |
+ POC_SD0_CLK_33V);
+
+ /* initialize DRV control register */
+ reg = mmio_read_32(PFC_DRVCTRL0);
+ reg = (reg & DRVCTRL0_MASK) |
+ DRVCTRL0_QSPI0_SPCLK(3) |
+ DRVCTRL0_QSPI0_MOSI_IO0(3) |
+ DRVCTRL0_QSPI0_MISO_IO1(3) |
+ DRVCTRL0_QSPI0_IO2(3) |
+ DRVCTRL0_QSPI0_IO3(3) |
+ DRVCTRL0_QSPI0_SSL(3) |
+ DRVCTRL0_QSPI1_SPCLK(3) |
+ DRVCTRL0_QSPI1_MOSI_IO0(3);
+ pfc_reg_write(PFC_DRVCTRL0, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL1);
+ reg = (reg & DRVCTRL1_MASK) |
+ DRVCTRL1_QSPI1_MISO_IO1(3) |
+ DRVCTRL1_QSPI1_IO2(3) |
+ DRVCTRL1_QSPI1_IO3(3) |
+ DRVCTRL1_QSPI1_SS(3) |
+ DRVCTRL1_RPC_INT(3) |
+ DRVCTRL1_RPC_WP(3) |
+ DRVCTRL1_RPC_RESET(3) |
+ DRVCTRL1_AVB_RX_CTL(7);
+ pfc_reg_write(PFC_DRVCTRL1, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL2);
+ reg = (reg & DRVCTRL2_MASK) |
+ DRVCTRL2_AVB_RXC(7) |
+ DRVCTRL2_AVB_RD0(7) |
+ DRVCTRL2_AVB_RD1(7) |
+ DRVCTRL2_AVB_RD2(7) |
+ DRVCTRL2_AVB_RD3(7) |
+ DRVCTRL2_AVB_TX_CTL(3) |
+ DRVCTRL2_AVB_TXC(3) |
+ DRVCTRL2_AVB_TD0(3);
+ pfc_reg_write(PFC_DRVCTRL2, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL3);
+ reg = (reg & DRVCTRL3_MASK) |
+ DRVCTRL3_AVB_TD1(3) |
+ DRVCTRL3_AVB_TD2(3) |
+ DRVCTRL3_AVB_TD3(3) |
+ DRVCTRL3_AVB_TXCREFCLK(7) |
+ DRVCTRL3_AVB_MDIO(7) |
+ DRVCTRL3_AVB_MDC(7) |
+ DRVCTRL3_AVB_MAGIC(7) |
+ DRVCTRL3_AVB_PHY_INT(7);
+ pfc_reg_write(PFC_DRVCTRL3, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL4);
+ reg = (reg & DRVCTRL4_MASK) |
+ DRVCTRL4_AVB_LINK(7) |
+ DRVCTRL4_AVB_AVTP_MATCH(7) |
+ DRVCTRL4_AVB_AVTP_CAPTURE(7) |
+ DRVCTRL4_IRQ0(7) |
+ DRVCTRL4_IRQ1(7) |
+ DRVCTRL4_IRQ2(7) |
+ DRVCTRL4_IRQ3(7) |
+ DRVCTRL4_IRQ4(7);
+ pfc_reg_write(PFC_DRVCTRL4, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL5);
+ reg = (reg & DRVCTRL5_MASK) |
+ DRVCTRL5_IRQ5(7) |
+ DRVCTRL5_PWM0(7) |
+ DRVCTRL5_PWM1(7) |
+ DRVCTRL5_PWM2(7) |
+ DRVCTRL5_A0(3) |
+ DRVCTRL5_A1(3) |
+ DRVCTRL5_A2(3) |
+ DRVCTRL5_A3(3);
+ pfc_reg_write(PFC_DRVCTRL5, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL6);
+ reg = (reg & DRVCTRL6_MASK) |
+ DRVCTRL6_A4(3) |
+ DRVCTRL6_A5(3) |
+ DRVCTRL6_A6(3) |
+ DRVCTRL6_A7(3) |
+ DRVCTRL6_A8(7) |
+ DRVCTRL6_A9(7) |
+ DRVCTRL6_A10(7) |
+ DRVCTRL6_A11(7);
+ pfc_reg_write(PFC_DRVCTRL6, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL7);
+ reg = (reg & DRVCTRL7_MASK) |
+ DRVCTRL7_A12(3) |
+ DRVCTRL7_A13(3) |
+ DRVCTRL7_A14(3) |
+ DRVCTRL7_A15(3) |
+ DRVCTRL7_A16(3) |
+ DRVCTRL7_A17(3) |
+ DRVCTRL7_A18(3) |
+ DRVCTRL7_A19(3);
+ pfc_reg_write(PFC_DRVCTRL7, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL8);
+ reg = (reg & DRVCTRL8_MASK) |
+ DRVCTRL8_CLKOUT(7) |
+ DRVCTRL8_CS0(7) |
+ DRVCTRL8_CS1_A2(7) |
+ DRVCTRL8_BS(7) |
+ DRVCTRL8_RD(7) |
+ DRVCTRL8_RD_W(7) |
+ DRVCTRL8_WE0(7) |
+ DRVCTRL8_WE1(7);
+ pfc_reg_write(PFC_DRVCTRL8, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL9);
+ reg = (reg & DRVCTRL9_MASK) |
+ DRVCTRL9_EX_WAIT0(7) |
+ DRVCTRL9_PRESETOU(7) |
+ DRVCTRL9_D0(7) |
+ DRVCTRL9_D1(7) |
+ DRVCTRL9_D2(7) |
+ DRVCTRL9_D3(7) |
+ DRVCTRL9_D4(7) |
+ DRVCTRL9_D5(7);
+ pfc_reg_write(PFC_DRVCTRL9, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL10);
+ reg = (reg & DRVCTRL10_MASK) |
+ DRVCTRL10_D6(7) |
+ DRVCTRL10_D7(7) |
+ DRVCTRL10_D8(3) |
+ DRVCTRL10_D9(3) |
+ DRVCTRL10_D10(3) |
+ DRVCTRL10_D11(3) |
+ DRVCTRL10_D12(3) |
+ DRVCTRL10_D13(3);
+ pfc_reg_write(PFC_DRVCTRL10, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL11);
+ reg = (reg & DRVCTRL11_MASK) |
+ DRVCTRL11_D14(3) |
+ DRVCTRL11_D15(3) |
+ DRVCTRL11_AVS1(7) |
+ DRVCTRL11_AVS2(7) |
+ DRVCTRL11_GP7_02(7) |
+ DRVCTRL11_GP7_03(7) |
+ DRVCTRL11_DU_DOTCLKIN0(3) |
+ DRVCTRL11_DU_DOTCLKIN1(3);
+ pfc_reg_write(PFC_DRVCTRL11, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL12);
+ reg = (reg & DRVCTRL12_MASK) |
+ DRVCTRL12_DU_DOTCLKIN2(3) |
+ DRVCTRL12_DU_DOTCLKIN3(3) |
+ DRVCTRL12_DU_FSCLKST(3) |
+ DRVCTRL12_DU_TMS(3);
+ pfc_reg_write(PFC_DRVCTRL12, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL13);
+ reg = (reg & DRVCTRL13_MASK) |
+ DRVCTRL13_TDO(3) |
+ DRVCTRL13_ASEBRK(3) |
+ DRVCTRL13_SD0_CLK(7) |
+ DRVCTRL13_SD0_CMD(7) |
+ DRVCTRL13_SD0_DAT0(7) |
+ DRVCTRL13_SD0_DAT1(7) |
+ DRVCTRL13_SD0_DAT2(7) |
+ DRVCTRL13_SD0_DAT3(7);
+ pfc_reg_write(PFC_DRVCTRL13, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL14);
+ reg = (reg & DRVCTRL14_MASK) |
+ DRVCTRL14_SD1_CLK(7) |
+ DRVCTRL14_SD1_CMD(7) |
+ DRVCTRL14_SD1_DAT0(5) |
+ DRVCTRL14_SD1_DAT1(5) |
+ DRVCTRL14_SD1_DAT2(5) |
+ DRVCTRL14_SD1_DAT3(5) |
+ DRVCTRL14_SD2_CLK(5) |
+ DRVCTRL14_SD2_CMD(5);
+ pfc_reg_write(PFC_DRVCTRL14, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL15);
+ reg = (reg & DRVCTRL15_MASK) |
+ DRVCTRL15_SD2_DAT0(5) |
+ DRVCTRL15_SD2_DAT1(5) |
+ DRVCTRL15_SD2_DAT2(5) |
+ DRVCTRL15_SD2_DAT3(5) |
+ DRVCTRL15_SD2_DS(5) |
+ DRVCTRL15_SD3_CLK(7) |
+ DRVCTRL15_SD3_CMD(7) |
+ DRVCTRL15_SD3_DAT0(7);
+ pfc_reg_write(PFC_DRVCTRL15, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL16);
+ reg = (reg & DRVCTRL16_MASK) |
+ DRVCTRL16_SD3_DAT1(7) |
+ DRVCTRL16_SD3_DAT2(7) |
+ DRVCTRL16_SD3_DAT3(7) |
+ DRVCTRL16_SD3_DAT4(7) |
+ DRVCTRL16_SD3_DAT5(7) |
+ DRVCTRL16_SD3_DAT6(7) |
+ DRVCTRL16_SD3_DAT7(7) |
+ DRVCTRL16_SD3_DS(7);
+ pfc_reg_write(PFC_DRVCTRL16, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL17);
+ reg = (reg & DRVCTRL17_MASK) |
+ DRVCTRL17_SD0_CD(7) |
+ DRVCTRL17_SD0_WP(7) |
+ DRVCTRL17_SD1_CD(7) |
+ DRVCTRL17_SD1_WP(7) |
+ DRVCTRL17_SCK0(7) |
+ DRVCTRL17_RX0(7) |
+ DRVCTRL17_TX0(7) |
+ DRVCTRL17_CTS0(7);
+ pfc_reg_write(PFC_DRVCTRL17, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL18);
+ reg = (reg & DRVCTRL18_MASK) |
+ DRVCTRL18_RTS0_TANS(7) |
+ DRVCTRL18_RX1(7) |
+ DRVCTRL18_TX1(7) |
+ DRVCTRL18_CTS1(7) |
+ DRVCTRL18_RTS1_TANS(7) |
+ DRVCTRL18_SCK2(7) |
+ DRVCTRL18_TX2(7) |
+ DRVCTRL18_RX2(7);
+ pfc_reg_write(PFC_DRVCTRL18, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL19);
+ reg = (reg & DRVCTRL19_MASK) |
+ DRVCTRL19_HSCK0(7) |
+ DRVCTRL19_HRX0(7) |
+ DRVCTRL19_HTX0(7) |
+ DRVCTRL19_HCTS0(7) |
+ DRVCTRL19_HRTS0(7) |
+ DRVCTRL19_MSIOF0_SCK(7) |
+ DRVCTRL19_MSIOF0_SYNC(7) |
+ DRVCTRL19_MSIOF0_SS1(7);
+ pfc_reg_write(PFC_DRVCTRL19, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL20);
+ reg = (reg & DRVCTRL20_MASK) |
+ DRVCTRL20_MSIOF0_TXD(7) |
+ DRVCTRL20_MSIOF0_SS2(7) |
+ DRVCTRL20_MSIOF0_RXD(7) |
+ DRVCTRL20_MLB_CLK(7) |
+ DRVCTRL20_MLB_SIG(7) |
+ DRVCTRL20_MLB_DAT(7) |
+ DRVCTRL20_MLB_REF(7) |
+ DRVCTRL20_SSI_SCK0129(7);
+ pfc_reg_write(PFC_DRVCTRL20, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL21);
+ reg = (reg & DRVCTRL21_MASK) |
+ DRVCTRL21_SSI_WS0129(7) |
+ DRVCTRL21_SSI_SDATA0(7) |
+ DRVCTRL21_SSI_SDATA1(7) |
+ DRVCTRL21_SSI_SDATA2(7) |
+ DRVCTRL21_SSI_SCK34(7) |
+ DRVCTRL21_SSI_WS34(7) |
+ DRVCTRL21_SSI_SDATA3(7) |
+ DRVCTRL21_SSI_SCK4(7);
+ pfc_reg_write(PFC_DRVCTRL21, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL22);
+ reg = (reg & DRVCTRL22_MASK) |
+ DRVCTRL22_SSI_WS4(7) |
+ DRVCTRL22_SSI_SDATA4(7) |
+ DRVCTRL22_SSI_SCK5(7) |
+ DRVCTRL22_SSI_WS5(7) |
+ DRVCTRL22_SSI_SDATA5(7) |
+ DRVCTRL22_SSI_SCK6(7) |
+ DRVCTRL22_SSI_WS6(7) |
+ DRVCTRL22_SSI_SDATA6(7);
+ pfc_reg_write(PFC_DRVCTRL22, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL23);
+ reg = (reg & DRVCTRL23_MASK) |
+ DRVCTRL23_SSI_SCK78(7) |
+ DRVCTRL23_SSI_WS78(7) |
+ DRVCTRL23_SSI_SDATA7(7) |
+ DRVCTRL23_SSI_SDATA8(7) |
+ DRVCTRL23_SSI_SDATA9(7) |
+ DRVCTRL23_AUDIO_CLKA(7) |
+ DRVCTRL23_AUDIO_CLKB(7) |
+ DRVCTRL23_USB0_PWEN(7);
+ pfc_reg_write(PFC_DRVCTRL23, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL24);
+ reg = (reg & DRVCTRL24_MASK) |
+ DRVCTRL24_USB0_OVC(7) |
+ DRVCTRL24_USB1_PWEN(7) |
+ DRVCTRL24_USB1_OVC(7) |
+ DRVCTRL24_USB30_PWEN(7) |
+ DRVCTRL24_USB30_OVC(7) |
+ DRVCTRL24_USB31_PWEN(7) |
+ DRVCTRL24_USB31_OVC(7);
+ pfc_reg_write(PFC_DRVCTRL24, reg);
+
+ /* initialize LSI pin pull-up/down control */
+ pfc_reg_write(PFC_PUD0, 0x00005FBFU);
+ pfc_reg_write(PFC_PUD1, 0x00300EFEU);
+ pfc_reg_write(PFC_PUD2, 0x330001E6U);
+ pfc_reg_write(PFC_PUD3, 0x000002E0U);
+ pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
+ pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
+ pfc_reg_write(PFC_PUD6, 0x00000055U);
+
+ /* initialize LSI pin pull-enable register */
+ pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
+ pfc_reg_write(PFC_PUEN1, 0x00100234U);
+ pfc_reg_write(PFC_PUEN2, 0x000004C4U);
+ pfc_reg_write(PFC_PUEN3, 0x00000200U);
+ pfc_reg_write(PFC_PUEN4, 0x3E000000U);
+ pfc_reg_write(PFC_PUEN5, 0x1F000805U);
+ pfc_reg_write(PFC_PUEN6, 0x00000006U);
+
+ /* initialize positive/negative logic select */
+ mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG7, 0x00000000U);
+
+ /* initialize general IO/interrupt switching */
+ mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
+
+ /* initialize general output register */
+ mmio_write_32(GPIO_OUTDT0, 0x00000001U);
+ mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT2, 0x00000400U);
+ mmio_write_32(GPIO_OUTDT3, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT4, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT5, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT6, 0x00003800U);
+ mmio_write_32(GPIO_OUTDT7, 0x00000003U);
+
+ /* initialize general input/output switching */
+ mmio_write_32(GPIO_INOUTSEL0, 0x00000001U);
+ mmio_write_32(GPIO_INOUTSEL1, 0x00100B00U);
+ mmio_write_32(GPIO_INOUTSEL2, 0x00000418U);
+ mmio_write_32(GPIO_INOUTSEL3, 0x00002000U);
+ mmio_write_32(GPIO_INOUTSEL4, 0x00000040U);
+ mmio_write_32(GPIO_INOUTSEL5, 0x00000208U);
+ mmio_write_32(GPIO_INOUTSEL6, 0x00013F00U);
+ mmio_write_32(GPIO_INOUTSEL7, 0x00000003U);
+}
diff --git a/drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.h b/drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.h
new file mode 100644
index 0000000..5efce45
--- /dev/null
+++ b/drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PFC_INIT_G2H_H
+#define PFC_INIT_G2H_H
+
+void pfc_init_g2h(void);
+
+#endif /* PFC_INIT_G2H_H */
diff --git a/drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.c b/drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.c
new file mode 100644
index 0000000..c951e0a
--- /dev/null
+++ b/drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.c
@@ -0,0 +1,1306 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <lib/mmio.h>
+
+#include "pfc_init_g2n.h"
+#include "rcar_def.h"
+#include "../pfc_regs.h"
+
+#define GPSR0_D15 BIT(15)
+#define GPSR0_D14 BIT(14)
+#define GPSR0_D13 BIT(13)
+#define GPSR0_D12 BIT(12)
+#define GPSR0_D11 BIT(11)
+#define GPSR0_D10 BIT(10)
+#define GPSR0_D9 BIT(9)
+#define GPSR0_D8 BIT(8)
+#define GPSR0_D7 BIT(7)
+#define GPSR0_D6 BIT(6)
+#define GPSR0_D5 BIT(5)
+#define GPSR0_D4 BIT(4)
+#define GPSR0_D3 BIT(3)
+#define GPSR0_D2 BIT(2)
+#define GPSR0_D1 BIT(1)
+#define GPSR0_D0 BIT(0)
+#define GPSR1_CLKOUT BIT(28)
+#define GPSR1_EX_WAIT0_A BIT(27)
+#define GPSR1_WE1 BIT(26)
+#define GPSR1_WE0 BIT(25)
+#define GPSR1_RD_WR BIT(24)
+#define GPSR1_RD BIT(23)
+#define GPSR1_BS BIT(22)
+#define GPSR1_CS1_A26 BIT(21)
+#define GPSR1_CS0 BIT(20)
+#define GPSR1_A19 BIT(19)
+#define GPSR1_A18 BIT(18)
+#define GPSR1_A17 BIT(17)
+#define GPSR1_A16 BIT(16)
+#define GPSR1_A15 BIT(15)
+#define GPSR1_A14 BIT(14)
+#define GPSR1_A13 BIT(13)
+#define GPSR1_A12 BIT(12)
+#define GPSR1_A11 BIT(11)
+#define GPSR1_A10 BIT(10)
+#define GPSR1_A9 BIT(9)
+#define GPSR1_A8 BIT(8)
+#define GPSR1_A7 BIT(7)
+#define GPSR1_A6 BIT(6)
+#define GPSR1_A5 BIT(5)
+#define GPSR1_A4 BIT(4)
+#define GPSR1_A3 BIT(3)
+#define GPSR1_A2 BIT(2)
+#define GPSR1_A1 BIT(1)
+#define GPSR1_A0 BIT(0)
+#define GPSR2_AVB_AVTP_CAPTURE_A BIT(14)
+#define GPSR2_AVB_AVTP_MATCH_A BIT(13)
+#define GPSR2_AVB_LINK BIT(12)
+#define GPSR2_AVB_PHY_INT BIT(11)
+#define GPSR2_AVB_MAGIC BIT(10)
+#define GPSR2_AVB_MDC BIT(9)
+#define GPSR2_PWM2_A BIT(8)
+#define GPSR2_PWM1_A BIT(7)
+#define GPSR2_PWM0 BIT(6)
+#define GPSR2_IRQ5 BIT(5)
+#define GPSR2_IRQ4 BIT(4)
+#define GPSR2_IRQ3 BIT(3)
+#define GPSR2_IRQ2 BIT(2)
+#define GPSR2_IRQ1 BIT(1)
+#define GPSR2_IRQ0 BIT(0)
+#define GPSR3_SD1_WP BIT(15)
+#define GPSR3_SD1_CD BIT(14)
+#define GPSR3_SD0_WP BIT(13)
+#define GPSR3_SD0_CD BIT(12)
+#define GPSR3_SD1_DAT3 BIT(11)
+#define GPSR3_SD1_DAT2 BIT(10)
+#define GPSR3_SD1_DAT1 BIT(9)
+#define GPSR3_SD1_DAT0 BIT(8)
+#define GPSR3_SD1_CMD BIT(7)
+#define GPSR3_SD1_CLK BIT(6)
+#define GPSR3_SD0_DAT3 BIT(5)
+#define GPSR3_SD0_DAT2 BIT(4)
+#define GPSR3_SD0_DAT1 BIT(3)
+#define GPSR3_SD0_DAT0 BIT(2)
+#define GPSR3_SD0_CMD BIT(1)
+#define GPSR3_SD0_CLK BIT(0)
+#define GPSR4_SD3_DS BIT(17)
+#define GPSR4_SD3_DAT7 BIT(16)
+#define GPSR4_SD3_DAT6 BIT(15)
+#define GPSR4_SD3_DAT5 BIT(14)
+#define GPSR4_SD3_DAT4 BIT(13)
+#define GPSR4_SD3_DAT3 BIT(12)
+#define GPSR4_SD3_DAT2 BIT(11)
+#define GPSR4_SD3_DAT1 BIT(10)
+#define GPSR4_SD3_DAT0 BIT(9)
+#define GPSR4_SD3_CMD BIT(8)
+#define GPSR4_SD3_CLK BIT(7)
+#define GPSR4_SD2_DS BIT(6)
+#define GPSR4_SD2_DAT3 BIT(5)
+#define GPSR4_SD2_DAT2 BIT(4)
+#define GPSR4_SD2_DAT1 BIT(3)
+#define GPSR4_SD2_DAT0 BIT(2)
+#define GPSR4_SD2_CMD BIT(1)
+#define GPSR4_SD2_CLK BIT(0)
+#define GPSR5_MLB_DAT BIT(25)
+#define GPSR5_MLB_SIG BIT(24)
+#define GPSR5_MLB_CLK BIT(23)
+#define GPSR5_MSIOF0_RXD BIT(22)
+#define GPSR5_MSIOF0_SS2 BIT(21)
+#define GPSR5_MSIOF0_TXD BIT(20)
+#define GPSR5_MSIOF0_SS1 BIT(19)
+#define GPSR5_MSIOF0_SYNC BIT(18)
+#define GPSR5_MSIOF0_SCK BIT(17)
+#define GPSR5_HRTS0 BIT(16)
+#define GPSR5_HCTS0 BIT(15)
+#define GPSR5_HTX0 BIT(14)
+#define GPSR5_HRX0 BIT(13)
+#define GPSR5_HSCK0 BIT(12)
+#define GPSR5_RX2_A BIT(11)
+#define GPSR5_TX2_A BIT(10)
+#define GPSR5_SCK2 BIT(9)
+#define GPSR5_RTS1 BIT(8)
+#define GPSR5_CTS1 BIT(7)
+#define GPSR5_TX1_A BIT(6)
+#define GPSR5_RX1_A BIT(5)
+#define GPSR5_RTS0 BIT(4)
+#define GPSR5_CTS0 BIT(3)
+#define GPSR5_TX0 BIT(2)
+#define GPSR5_RX0 BIT(1)
+#define GPSR5_SCK0 BIT(0)
+#define GPSR6_USB31_OVC BIT(31)
+#define GPSR6_USB31_PWEN BIT(30)
+#define GPSR6_USB30_OVC BIT(29)
+#define GPSR6_USB30_PWEN BIT(28)
+#define GPSR6_USB1_OVC BIT(27)
+#define GPSR6_USB1_PWEN BIT(26)
+#define GPSR6_USB0_OVC BIT(25)
+#define GPSR6_USB0_PWEN BIT(24)
+#define GPSR6_AUDIO_CLKB_B BIT(23)
+#define GPSR6_AUDIO_CLKA_A BIT(22)
+#define GPSR6_SSI_SDATA9_A BIT(21)
+#define GPSR6_SSI_SDATA8 BIT(20)
+#define GPSR6_SSI_SDATA7 BIT(19)
+#define GPSR6_SSI_WS78 BIT(18)
+#define GPSR6_SSI_SCK78 BIT(17)
+#define GPSR6_SSI_SDATA6 BIT(16)
+#define GPSR6_SSI_WS6 BIT(15)
+#define GPSR6_SSI_SCK6 BIT(14)
+#define GPSR6_SSI_SDATA5 BIT(13)
+#define GPSR6_SSI_WS5 BIT(12)
+#define GPSR6_SSI_SCK5 BIT(11)
+#define GPSR6_SSI_SDATA4 BIT(10)
+#define GPSR6_SSI_WS4 BIT(9)
+#define GPSR6_SSI_SCK4 BIT(8)
+#define GPSR6_SSI_SDATA3 BIT(7)
+#define GPSR6_SSI_WS34 BIT(6)
+#define GPSR6_SSI_SCK34 BIT(5)
+#define GPSR6_SSI_SDATA2_A BIT(4)
+#define GPSR6_SSI_SDATA1_A BIT(3)
+#define GPSR6_SSI_SDATA0 BIT(2)
+#define GPSR6_SSI_WS0129 BIT(1)
+#define GPSR6_SSI_SCK0129 BIT(0)
+#define GPSR7_AVS2 BIT(1)
+#define GPSR7_AVS1 BIT(0)
+
+#define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
+#define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
+#define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
+#define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
+#define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
+#define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
+#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
+#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
+
+#define POC_SD3_DS_33V BIT(29)
+#define POC_SD3_DAT7_33V BIT(28)
+#define POC_SD3_DAT6_33V BIT(27)
+#define POC_SD3_DAT5_33V BIT(26)
+#define POC_SD3_DAT4_33V BIT(25)
+#define POC_SD3_DAT3_33V BIT(24)
+#define POC_SD3_DAT2_33V BIT(23)
+#define POC_SD3_DAT1_33V BIT(22)
+#define POC_SD3_DAT0_33V BIT(21)
+#define POC_SD3_CMD_33V BIT(20)
+#define POC_SD3_CLK_33V BIT(19)
+#define POC_SD2_DS_33V BIT(18)
+#define POC_SD2_DAT3_33V BIT(17)
+#define POC_SD2_DAT2_33V BIT(16)
+#define POC_SD2_DAT1_33V BIT(15)
+#define POC_SD2_DAT0_33V BIT(14)
+#define POC_SD2_CMD_33V BIT(13)
+#define POC_SD2_CLK_33V BIT(12)
+#define POC_SD1_DAT3_33V BIT(11)
+#define POC_SD1_DAT2_33V BIT(10)
+#define POC_SD1_DAT1_33V BIT(9)
+#define POC_SD1_DAT0_33V BIT(8)
+#define POC_SD1_CMD_33V BIT(7)
+#define POC_SD1_CLK_33V BIT(6)
+#define POC_SD0_DAT3_33V BIT(5)
+#define POC_SD0_DAT2_33V BIT(4)
+#define POC_SD0_DAT1_33V BIT(3)
+#define POC_SD0_DAT0_33V BIT(2)
+#define POC_SD0_CMD_33V BIT(1)
+#define POC_SD0_CLK_33V BIT(0)
+
+#define DRVCTRL0_MASK (0xCCCCCCCCU)
+#define DRVCTRL1_MASK (0xCCCCCCC8U)
+#define DRVCTRL2_MASK (0x88888888U)
+#define DRVCTRL3_MASK (0x88888888U)
+#define DRVCTRL4_MASK (0x88888888U)
+#define DRVCTRL5_MASK (0x88888888U)
+#define DRVCTRL6_MASK (0x88888888U)
+#define DRVCTRL7_MASK (0x88888888U)
+#define DRVCTRL8_MASK (0x88888888U)
+#define DRVCTRL9_MASK (0x88888888U)
+#define DRVCTRL10_MASK (0x88888888U)
+#define DRVCTRL11_MASK (0x888888CCU)
+#define DRVCTRL12_MASK (0xCCCFFFCFU)
+#define DRVCTRL13_MASK (0xCC888888U)
+#define DRVCTRL14_MASK (0x88888888U)
+#define DRVCTRL15_MASK (0x88888888U)
+#define DRVCTRL16_MASK (0x88888888U)
+#define DRVCTRL17_MASK (0x88888888U)
+#define DRVCTRL18_MASK (0x88888888U)
+#define DRVCTRL19_MASK (0x88888888U)
+#define DRVCTRL20_MASK (0x88888888U)
+#define DRVCTRL21_MASK (0x88888888U)
+#define DRVCTRL22_MASK (0x88888888U)
+#define DRVCTRL23_MASK (0x88888888U)
+#define DRVCTRL24_MASK (0x8888888FU)
+
+#define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL0_QSPI0_MISO_IO1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL0_QSPI0_IO2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL0_QSPI0_IO3(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL0_QSPI0_SSL(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL0_QSPI1_SPCLK(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL0_QSPI1_MOSI_IO0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL1_QSPI1_MISO_IO1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL1_QSPI1_IO2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL1_QSPI1_IO3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL1_QSPI1_SS(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL1_RPC_INT(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL1_RPC_WP(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL1_RPC_RESET(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL1_AVB_RX_CTL(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL2_AVB_RXC(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL2_AVB_RD0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL2_AVB_RD1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL2_AVB_RD2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL2_AVB_RD3(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL2_AVB_TX_CTL(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL2_AVB_TXC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL2_AVB_TD0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL3_AVB_TD1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL3_AVB_TD2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL3_AVB_TD3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL3_AVB_TXCREFCLK(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL3_AVB_MDIO(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL3_AVB_MDC(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL3_AVB_MAGIC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL3_AVB_PHY_INT(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL4_AVB_LINK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL4_AVB_AVTP_MATCH(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL4_AVB_AVTP_CAPTURE(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL4_IRQ0(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL4_IRQ1(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL4_IRQ2(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL4_IRQ3(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL4_IRQ4(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL5_IRQ5(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL5_PWM0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL5_PWM1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL5_PWM2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL5_A0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL5_A1(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL5_A2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL5_A3(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL6_A4(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL6_A5(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL6_A6(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL6_A7(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL6_A8(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL6_A9(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL6_A10(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL6_A11(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL7_A12(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL7_A13(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL7_A14(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL7_A15(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL7_A16(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL7_A17(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL7_A18(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL7_A19(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL8_CLKOUT(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL8_CS0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL8_CS1_A2(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL8_BS(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL8_RD(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL8_RD_W(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL8_WE0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL8_WE1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL9_EX_WAIT0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL9_PRESETOU(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL9_D0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL9_D1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL9_D2(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL9_D3(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL9_D4(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL9_D5(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL10_D6(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL10_D7(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL10_D8(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL10_D9(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL10_D10(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL10_D11(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL10_D12(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL10_D13(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL11_D14(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL11_GP7_02(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL11_GP7_03(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL12_DU_DOTCLKIN3(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL12_DU_FSCLKST(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL12_DU_TMS(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL13_TDO(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL13_ASEBRK(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL13_SD0_CLK(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL13_SD0_CMD(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL13_SD0_DAT0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL13_SD0_DAT1(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL13_SD0_DAT2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL13_SD0_DAT3(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL14_SD1_CLK(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL14_SD1_CMD(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL14_SD1_DAT0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL14_SD1_DAT1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL14_SD1_DAT2(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL14_SD1_DAT3(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL14_SD2_CLK(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL14_SD2_CMD(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL15_SD2_DAT0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL15_SD2_DAT1(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL15_SD2_DAT2(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL15_SD2_DAT3(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL15_SD2_DS(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL15_SD3_CLK(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL15_SD3_CMD(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL15_SD3_DAT0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL16_SD3_DAT1(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL16_SD3_DAT2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL16_SD3_DAT3(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL16_SD3_DAT4(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL16_SD3_DAT5(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL16_SD3_DAT6(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL16_SD3_DAT7(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL16_SD3_DS(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL17_SD0_CD(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL17_SD0_WP(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL17_SD1_CD(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL17_SD1_WP(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL17_SCK0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL17_RX0(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL17_TX0(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL17_CTS0(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL18_RTS0_TANS(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL18_RX1(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL18_TX1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL18_CTS1(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL18_RTS1_TANS(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL18_SCK2(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL18_TX2(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL18_RX2(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL19_HSCK0(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL19_HRX0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL19_HTX0(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL19_HCTS0(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL19_HRTS0(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL19_MSIOF0_SCK(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL19_MSIOF0_SYNC(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL19_MSIOF0_SS1(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL20_MSIOF0_TXD(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL20_MSIOF0_SS2(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL20_MSIOF0_RXD(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL20_MLB_CLK(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL20_MLB_SIG(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL20_MLB_DAT(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL20_MLB_REF(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL20_SSI_SCK0129(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL21_SSI_WS0129(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL21_SSI_SDATA0(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL21_SSI_SDATA1(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL21_SSI_SDATA2(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL21_SSI_SCK34(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL21_SSI_WS34(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL21_SSI_SDATA3(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL21_SSI_SCK4(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL22_SSI_WS4(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL22_SSI_SDATA4(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL22_SSI_SCK5(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL22_SSI_WS5(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL22_SSI_SDATA5(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL22_SSI_SCK6(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL22_SSI_WS6(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL22_SSI_SDATA6(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL23_SSI_SCK78(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL23_SSI_WS78(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL23_SSI_SDATA7(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL23_SSI_SDATA8(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL23_SSI_SDATA9(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL23_AUDIO_CLKA(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL23_AUDIO_CLKB(x) ((uint32_t)(x) << 4U)
+#define DRVCTRL23_USB0_PWEN(x) ((uint32_t)(x) << 0U)
+#define DRVCTRL24_USB0_OVC(x) ((uint32_t)(x) << 28U)
+#define DRVCTRL24_USB1_PWEN(x) ((uint32_t)(x) << 24U)
+#define DRVCTRL24_USB1_OVC(x) ((uint32_t)(x) << 20U)
+#define DRVCTRL24_USB30_PWEN(x) ((uint32_t)(x) << 16U)
+#define DRVCTRL24_USB30_OVC(x) ((uint32_t)(x) << 12U)
+#define DRVCTRL24_USB31_PWEN(x) ((uint32_t)(x) << 8U)
+#define DRVCTRL24_USB31_OVC(x) ((uint32_t)(x) << 4U)
+
+#define MOD_SEL0_MSIOF3_A ((uint32_t)0U << 29U)
+#define MOD_SEL0_MSIOF3_B ((uint32_t)1U << 29U)
+#define MOD_SEL0_MSIOF3_C ((uint32_t)2U << 29U)
+#define MOD_SEL0_MSIOF3_D ((uint32_t)3U << 29U)
+#define MOD_SEL0_MSIOF3_E ((uint32_t)4U << 29U)
+#define MOD_SEL0_MSIOF2_A ((uint32_t)0U << 27U)
+#define MOD_SEL0_MSIOF2_B ((uint32_t)1U << 27U)
+#define MOD_SEL0_MSIOF2_C ((uint32_t)2U << 27U)
+#define MOD_SEL0_MSIOF2_D ((uint32_t)3U << 27U)
+#define MOD_SEL0_MSIOF1_A ((uint32_t)0U << 24U)
+#define MOD_SEL0_MSIOF1_B ((uint32_t)1U << 24U)
+#define MOD_SEL0_MSIOF1_C ((uint32_t)2U << 24U)
+#define MOD_SEL0_MSIOF1_D ((uint32_t)3U << 24U)
+#define MOD_SEL0_MSIOF1_E ((uint32_t)4U << 24U)
+#define MOD_SEL0_MSIOF1_F ((uint32_t)5U << 24U)
+#define MOD_SEL0_MSIOF1_G ((uint32_t)6U << 24U)
+#define MOD_SEL0_LBSC_A ((uint32_t)0U << 23U)
+#define MOD_SEL0_LBSC_B ((uint32_t)1U << 23U)
+#define MOD_SEL0_IEBUS_A ((uint32_t)0U << 22U)
+#define MOD_SEL0_IEBUS_B ((uint32_t)1U << 22U)
+#define MOD_SEL0_I2C2_A ((uint32_t)0U << 21U)
+#define MOD_SEL0_I2C2_B ((uint32_t)1U << 21U)
+#define MOD_SEL0_I2C1_A ((uint32_t)0U << 20U)
+#define MOD_SEL0_I2C1_B ((uint32_t)1U << 20U)
+#define MOD_SEL0_HSCIF4_A ((uint32_t)0U << 19U)
+#define MOD_SEL0_HSCIF4_B ((uint32_t)1U << 19U)
+#define MOD_SEL0_HSCIF3_A ((uint32_t)0U << 17U)
+#define MOD_SEL0_HSCIF3_B ((uint32_t)1U << 17U)
+#define MOD_SEL0_HSCIF3_C ((uint32_t)2U << 17U)
+#define MOD_SEL0_HSCIF3_D ((uint32_t)3U << 17U)
+#define MOD_SEL0_HSCIF1_A ((uint32_t)0U << 16U)
+#define MOD_SEL0_HSCIF1_B ((uint32_t)1U << 16U)
+#define MOD_SEL0_FSO_A ((uint32_t)0U << 15U)
+#define MOD_SEL0_FSO_B ((uint32_t)1U << 15U)
+#define MOD_SEL0_HSCIF2_A ((uint32_t)0U << 13U)
+#define MOD_SEL0_HSCIF2_B ((uint32_t)1U << 13U)
+#define MOD_SEL0_HSCIF2_C ((uint32_t)2U << 13U)
+#define MOD_SEL0_ETHERAVB_A ((uint32_t)0U << 12U)
+#define MOD_SEL0_ETHERAVB_B ((uint32_t)1U << 12U)
+#define MOD_SEL0_DRIF3_A ((uint32_t)0U << 11U)
+#define MOD_SEL0_DRIF3_B ((uint32_t)1U << 11U)
+#define MOD_SEL0_DRIF2_A ((uint32_t)0U << 10U)
+#define MOD_SEL0_DRIF2_B ((uint32_t)1U << 10U)
+#define MOD_SEL0_DRIF1_A ((uint32_t)0U << 8U)
+#define MOD_SEL0_DRIF1_B ((uint32_t)1U << 8U)
+#define MOD_SEL0_DRIF1_C ((uint32_t)2U << 8U)
+#define MOD_SEL0_DRIF0_A ((uint32_t)0U << 6U)
+#define MOD_SEL0_DRIF0_B ((uint32_t)1U << 6U)
+#define MOD_SEL0_DRIF0_C ((uint32_t)2U << 6U)
+#define MOD_SEL0_CANFD0_A ((uint32_t)0U << 5U)
+#define MOD_SEL0_CANFD0_B ((uint32_t)1U << 5U)
+#define MOD_SEL0_ADG_A_A ((uint32_t)0U << 3U)
+#define MOD_SEL0_ADG_A_B ((uint32_t)1U << 3U)
+#define MOD_SEL0_ADG_A_C ((uint32_t)2U << 3U)
+#define MOD_SEL1_TSIF1_A ((uint32_t)0U << 30U)
+#define MOD_SEL1_TSIF1_B ((uint32_t)1U << 30U)
+#define MOD_SEL1_TSIF1_C ((uint32_t)2U << 30U)
+#define MOD_SEL1_TSIF1_D ((uint32_t)3U << 30U)
+#define MOD_SEL1_TSIF0_A ((uint32_t)0U << 27U)
+#define MOD_SEL1_TSIF0_B ((uint32_t)1U << 27U)
+#define MOD_SEL1_TSIF0_C ((uint32_t)2U << 27U)
+#define MOD_SEL1_TSIF0_D ((uint32_t)3U << 27U)
+#define MOD_SEL1_TSIF0_E ((uint32_t)4U << 27U)
+#define MOD_SEL1_TIMER_TMU_A ((uint32_t)0U << 26U)
+#define MOD_SEL1_TIMER_TMU_B ((uint32_t)1U << 26U)
+#define MOD_SEL1_SSP1_1_A ((uint32_t)0U << 24U)
+#define MOD_SEL1_SSP1_1_B ((uint32_t)1U << 24U)
+#define MOD_SEL1_SSP1_1_C ((uint32_t)2U << 24U)
+#define MOD_SEL1_SSP1_1_D ((uint32_t)3U << 24U)
+#define MOD_SEL1_SSP1_0_A ((uint32_t)0U << 21U)
+#define MOD_SEL1_SSP1_0_B ((uint32_t)1U << 21U)
+#define MOD_SEL1_SSP1_0_C ((uint32_t)2U << 21U)
+#define MOD_SEL1_SSP1_0_D ((uint32_t)3U << 21U)
+#define MOD_SEL1_SSP1_0_E ((uint32_t)4U << 21U)
+#define MOD_SEL1_SSI_A ((uint32_t)0U << 20U)
+#define MOD_SEL1_SSI_B ((uint32_t)1U << 20U)
+#define MOD_SEL1_SPEED_PULSE_IF_A ((uint32_t)0U << 19U)
+#define MOD_SEL1_SPEED_PULSE_IF_B ((uint32_t)1U << 19U)
+#define MOD_SEL1_SIMCARD_A ((uint32_t)0U << 17U)
+#define MOD_SEL1_SIMCARD_B ((uint32_t)1U << 17U)
+#define MOD_SEL1_SIMCARD_C ((uint32_t)2U << 17U)
+#define MOD_SEL1_SIMCARD_D ((uint32_t)3U << 17U)
+#define MOD_SEL1_SDHI2_A ((uint32_t)0U << 16U)
+#define MOD_SEL1_SDHI2_B ((uint32_t)1U << 16U)
+#define MOD_SEL1_SCIF4_A ((uint32_t)0U << 14U)
+#define MOD_SEL1_SCIF4_B ((uint32_t)1U << 14U)
+#define MOD_SEL1_SCIF4_C ((uint32_t)2U << 14U)
+#define MOD_SEL1_SCIF3_A ((uint32_t)0U << 13U)
+#define MOD_SEL1_SCIF3_B ((uint32_t)1U << 13U)
+#define MOD_SEL1_SCIF2_A ((uint32_t)0U << 12U)
+#define MOD_SEL1_SCIF2_B ((uint32_t)1U << 12U)
+#define MOD_SEL1_SCIF1_A ((uint32_t)0U << 11U)
+#define MOD_SEL1_SCIF1_B ((uint32_t)1U << 11U)
+#define MOD_SEL1_SCIF_A ((uint32_t)0U << 10U)
+#define MOD_SEL1_SCIF_B ((uint32_t)1U << 10U)
+#define MOD_SEL1_REMOCON_A ((uint32_t)0U << 9U)
+#define MOD_SEL1_REMOCON_B ((uint32_t)1U << 9U)
+#define MOD_SEL1_RCAN0_A ((uint32_t)0U << 6U)
+#define MOD_SEL1_RCAN0_B ((uint32_t)1U << 6U)
+#define MOD_SEL1_PWM6_A ((uint32_t)0U << 5U)
+#define MOD_SEL1_PWM6_B ((uint32_t)1U << 5U)
+#define MOD_SEL1_PWM5_A ((uint32_t)0U << 4U)
+#define MOD_SEL1_PWM5_B ((uint32_t)1U << 4U)
+#define MOD_SEL1_PWM4_A ((uint32_t)0U << 3U)
+#define MOD_SEL1_PWM4_B ((uint32_t)1U << 3U)
+#define MOD_SEL1_PWM3_A ((uint32_t)0U << 2U)
+#define MOD_SEL1_PWM3_B ((uint32_t)1U << 2U)
+#define MOD_SEL1_PWM2_A ((uint32_t)0U << 1U)
+#define MOD_SEL1_PWM2_B ((uint32_t)1U << 1U)
+#define MOD_SEL1_PWM1_A ((uint32_t)0U << 0U)
+#define MOD_SEL1_PWM1_B ((uint32_t)1U << 0U)
+#define MOD_SEL2_I2C_5_A ((uint32_t)0U << 31U)
+#define MOD_SEL2_I2C_5_B ((uint32_t)1U << 31U)
+#define MOD_SEL2_I2C_3_A ((uint32_t)0U << 30U)
+#define MOD_SEL2_I2C_3_B ((uint32_t)1U << 30U)
+#define MOD_SEL2_I2C_0_A ((uint32_t)0U << 29U)
+#define MOD_SEL2_I2C_0_B ((uint32_t)1U << 29U)
+#define MOD_SEL2_FM_A ((uint32_t)0U << 27U)
+#define MOD_SEL2_FM_B ((uint32_t)1U << 27U)
+#define MOD_SEL2_FM_C ((uint32_t)2U << 27U)
+#define MOD_SEL2_FM_D ((uint32_t)3U << 27U)
+#define MOD_SEL2_SCIF5_A ((uint32_t)0U << 26U)
+#define MOD_SEL2_SCIF5_B ((uint32_t)1U << 26U)
+#define MOD_SEL2_I2C6_A ((uint32_t)0U << 23U)
+#define MOD_SEL2_I2C6_B ((uint32_t)1U << 23U)
+#define MOD_SEL2_I2C6_C ((uint32_t)2U << 23U)
+#define MOD_SEL2_NDF_A ((uint32_t)0U << 22U)
+#define MOD_SEL2_NDF_B ((uint32_t)1U << 22U)
+#define MOD_SEL2_SSI2_A ((uint32_t)0U << 21U)
+#define MOD_SEL2_SSI2_B ((uint32_t)1U << 21U)
+#define MOD_SEL2_SSI9_A ((uint32_t)0U << 20U)
+#define MOD_SEL2_SSI9_B ((uint32_t)1U << 20U)
+#define MOD_SEL2_TIMER_TMU2_A ((uint32_t)0U << 19U)
+#define MOD_SEL2_TIMER_TMU2_B ((uint32_t)1U << 19U)
+#define MOD_SEL2_ADG_B_A ((uint32_t)0U << 18U)
+#define MOD_SEL2_ADG_B_B ((uint32_t)1U << 18U)
+#define MOD_SEL2_ADG_C_A ((uint32_t)0U << 17U)
+#define MOD_SEL2_ADG_C_B ((uint32_t)1U << 17U)
+#define MOD_SEL2_VIN4_A ((uint32_t)0U << 0U)
+#define MOD_SEL2_VIN4_B ((uint32_t)1U << 0U)
+
+static void pfc_reg_write(uint32_t addr, uint32_t data)
+{
+ mmio_write_32(PFC_PMMR, ~data);
+ mmio_write_32((uintptr_t)addr, data);
+}
+
+void pfc_init_g2n(void)
+{
+ uint32_t reg;
+
+ /* initialize module select */
+ pfc_reg_write(PFC_MOD_SEL0,
+ MOD_SEL0_MSIOF3_A |
+ MOD_SEL0_MSIOF2_A |
+ MOD_SEL0_MSIOF1_A |
+ MOD_SEL0_LBSC_A |
+ MOD_SEL0_IEBUS_A |
+ MOD_SEL0_I2C2_A |
+ MOD_SEL0_I2C1_A |
+ MOD_SEL0_HSCIF4_A |
+ MOD_SEL0_HSCIF3_A |
+ MOD_SEL0_HSCIF1_A |
+ MOD_SEL0_FSO_A |
+ MOD_SEL0_HSCIF2_A |
+ MOD_SEL0_ETHERAVB_A |
+ MOD_SEL0_DRIF3_A |
+ MOD_SEL0_DRIF2_A |
+ MOD_SEL0_DRIF1_A |
+ MOD_SEL0_DRIF0_A |
+ MOD_SEL0_CANFD0_A |
+ MOD_SEL0_ADG_A_A);
+
+ pfc_reg_write(PFC_MOD_SEL1,
+ MOD_SEL1_TSIF1_A |
+ MOD_SEL1_TSIF0_A |
+ MOD_SEL1_TIMER_TMU_A |
+ MOD_SEL1_SSP1_1_A |
+ MOD_SEL1_SSP1_0_A |
+ MOD_SEL1_SSI_A |
+ MOD_SEL1_SPEED_PULSE_IF_A |
+ MOD_SEL1_SIMCARD_A |
+ MOD_SEL1_SDHI2_A |
+ MOD_SEL1_SCIF4_A |
+ MOD_SEL1_SCIF3_A |
+ MOD_SEL1_SCIF2_A |
+ MOD_SEL1_SCIF1_A |
+ MOD_SEL1_SCIF_A |
+ MOD_SEL1_REMOCON_A |
+ MOD_SEL1_RCAN0_A |
+ MOD_SEL1_PWM6_A |
+ MOD_SEL1_PWM5_A |
+ MOD_SEL1_PWM4_A |
+ MOD_SEL1_PWM3_A |
+ MOD_SEL1_PWM2_A |
+ MOD_SEL1_PWM1_A);
+
+ pfc_reg_write(PFC_MOD_SEL2,
+ MOD_SEL2_I2C_5_B |
+ MOD_SEL2_I2C_3_B |
+ MOD_SEL2_I2C_0_B |
+ MOD_SEL2_FM_A |
+ MOD_SEL2_SCIF5_A |
+ MOD_SEL2_I2C6_A |
+ MOD_SEL2_NDF_A |
+ MOD_SEL2_SSI2_A |
+ MOD_SEL2_SSI9_A |
+ MOD_SEL2_TIMER_TMU2_A |
+ MOD_SEL2_ADG_B_A |
+ MOD_SEL2_ADG_C_A |
+ MOD_SEL2_VIN4_A);
+
+ /* initialize peripheral function select */
+ pfc_reg_write(PFC_IPSR0,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR1,
+ IPSR_28_FUNC(6) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(3) |
+ IPSR_8_FUNC(3) |
+ IPSR_4_FUNC(3) |
+ IPSR_0_FUNC(3));
+
+ pfc_reg_write(PFC_IPSR2,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(6) |
+ IPSR_20_FUNC(6) |
+ IPSR_16_FUNC(6) |
+ IPSR_12_FUNC(6) |
+ IPSR_8_FUNC(6) |
+ IPSR_4_FUNC(6) |
+ IPSR_0_FUNC(6));
+
+ pfc_reg_write(PFC_IPSR3,
+ IPSR_28_FUNC(6) |
+ IPSR_24_FUNC(6) |
+ IPSR_20_FUNC(6) |
+ IPSR_16_FUNC(6) |
+ IPSR_12_FUNC(6) |
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR4,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(6) |
+ IPSR_4_FUNC(6) |
+ IPSR_0_FUNC(6));
+
+ pfc_reg_write(PFC_IPSR5,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(6) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR6,
+ IPSR_28_FUNC(6) |
+ IPSR_24_FUNC(6) |
+ IPSR_20_FUNC(6) |
+ IPSR_16_FUNC(6) |
+ IPSR_12_FUNC(6) |
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR7,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(6) |
+ IPSR_4_FUNC(6) |
+ IPSR_0_FUNC(6));
+
+ pfc_reg_write(PFC_IPSR8,
+ IPSR_28_FUNC(1) |
+ IPSR_24_FUNC(1) |
+ IPSR_20_FUNC(1) |
+ IPSR_16_FUNC(1) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR9,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR10,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR11,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(4) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR12,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(4) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR13,
+ IPSR_28_FUNC(8) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(3) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR14,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(3) |
+ IPSR_0_FUNC(8));
+
+ pfc_reg_write(PFC_IPSR15,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR16,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(0) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR17,
+ IPSR_28_FUNC(0) |
+ IPSR_24_FUNC(0) |
+ IPSR_20_FUNC(0) |
+ IPSR_16_FUNC(0) |
+ IPSR_12_FUNC(0) |
+ IPSR_8_FUNC(0) |
+ IPSR_4_FUNC(1) |
+ IPSR_0_FUNC(0));
+
+ pfc_reg_write(PFC_IPSR18, IPSR_4_FUNC(0) | IPSR_0_FUNC(0));
+
+ /* initialize GPIO/peripheral function select */
+ pfc_reg_write(PFC_GPSR0,
+ GPSR0_D15 |
+ GPSR0_D14 |
+ GPSR0_D13 |
+ GPSR0_D12 |
+ GPSR0_D11 |
+ GPSR0_D10 |
+ GPSR0_D9 |
+ GPSR0_D8 |
+ GPSR0_D7 |
+ GPSR0_D6 |
+ GPSR0_D5 |
+ GPSR0_D4 |
+ GPSR0_D3 |
+ GPSR0_D2 |
+ GPSR0_D0);
+
+ pfc_reg_write(PFC_GPSR1,
+ GPSR1_CLKOUT |
+ GPSR1_EX_WAIT0_A |
+ GPSR1_WE1 |
+ GPSR1_RD |
+ GPSR1_RD_WR |
+ GPSR1_CS0 |
+ GPSR1_A19 |
+ GPSR1_A18 |
+ GPSR1_A17 |
+ GPSR1_A16 |
+ GPSR1_A15 |
+ GPSR1_A14 |
+ GPSR1_A13 |
+ GPSR1_A12 |
+ GPSR1_A7 |
+ GPSR1_A6 |
+ GPSR1_A5 |
+ GPSR1_A4 |
+ GPSR1_A3 |
+ GPSR1_A2 |
+ GPSR1_A1 |
+ GPSR1_A0);
+
+ pfc_reg_write(PFC_GPSR2,
+ GPSR2_AVB_AVTP_CAPTURE_A |
+ GPSR2_AVB_AVTP_MATCH_A |
+ GPSR2_AVB_LINK |
+ GPSR2_AVB_PHY_INT |
+ GPSR2_AVB_MDC |
+ GPSR2_PWM2_A |
+ GPSR2_PWM1_A |
+ GPSR2_IRQ4 |
+ GPSR2_IRQ3 |
+ GPSR2_IRQ2 |
+ GPSR2_IRQ1 |
+ GPSR2_IRQ0);
+
+ pfc_reg_write(PFC_GPSR3,
+ GPSR3_SD0_CD |
+ GPSR3_SD1_DAT3 |
+ GPSR3_SD1_DAT2 |
+ GPSR3_SD1_DAT1 |
+ GPSR3_SD1_DAT0 |
+ GPSR3_SD0_DAT3 |
+ GPSR3_SD0_DAT2 |
+ GPSR3_SD0_DAT1 |
+ GPSR3_SD0_DAT0 |
+ GPSR3_SD0_CMD |
+ GPSR3_SD0_CLK);
+
+ pfc_reg_write(PFC_GPSR4,
+ GPSR4_SD3_DS |
+ GPSR4_SD3_DAT7 |
+ GPSR4_SD3_DAT6 |
+ GPSR4_SD3_DAT5 |
+ GPSR4_SD3_DAT4 |
+ GPSR4_SD3_DAT3 |
+ GPSR4_SD3_DAT2 |
+ GPSR4_SD3_DAT1 |
+ GPSR4_SD3_DAT0 |
+ GPSR4_SD3_CMD |
+ GPSR4_SD3_CLK |
+ GPSR4_SD2_DAT3 |
+ GPSR4_SD2_DAT2 |
+ GPSR4_SD2_DAT1 |
+ GPSR4_SD2_DAT0 |
+ GPSR4_SD2_CMD |
+ GPSR4_SD2_CLK);
+
+ pfc_reg_write(PFC_GPSR5,
+ GPSR5_MSIOF0_RXD |
+ GPSR5_MSIOF0_TXD |
+ GPSR5_MSIOF0_SYNC |
+ GPSR5_MSIOF0_SCK |
+ GPSR5_RX2_A |
+ GPSR5_TX2_A |
+ GPSR5_RTS1 |
+ GPSR5_CTS1 |
+ GPSR5_TX1_A |
+ GPSR5_RX1_A |
+ GPSR5_RTS0 |
+ GPSR5_SCK0);
+
+ pfc_reg_write(PFC_GPSR6,
+ GPSR6_AUDIO_CLKB_B |
+ GPSR6_AUDIO_CLKA_A |
+ GPSR6_SSI_WS6 |
+ GPSR6_SSI_SCK6 |
+ GPSR6_SSI_SDATA4 |
+ GPSR6_SSI_WS4 |
+ GPSR6_SSI_SCK4 |
+ GPSR6_SSI_SDATA1_A |
+ GPSR6_SSI_SDATA0 |
+ GPSR6_SSI_WS0129 |
+ GPSR6_SSI_SCK0129);
+
+ pfc_reg_write(PFC_GPSR7, GPSR7_AVS2 | GPSR7_AVS1);
+
+ /* initialize POC control register */
+ pfc_reg_write(PFC_POCCTRL0,
+ POC_SD0_DAT3_33V |
+ POC_SD0_DAT2_33V |
+ POC_SD0_DAT1_33V |
+ POC_SD0_DAT0_33V |
+ POC_SD0_CMD_33V |
+ POC_SD0_CLK_33V);
+
+ /* initialize DRV control register */
+ reg = mmio_read_32(PFC_DRVCTRL0);
+ reg = (reg & DRVCTRL0_MASK) |
+ DRVCTRL0_QSPI0_SPCLK(3) |
+ DRVCTRL0_QSPI0_MOSI_IO0(3) |
+ DRVCTRL0_QSPI0_MISO_IO1(3) |
+ DRVCTRL0_QSPI0_IO2(3) |
+ DRVCTRL0_QSPI0_IO3(3) |
+ DRVCTRL0_QSPI0_SSL(3) |
+ DRVCTRL0_QSPI1_SPCLK(3) |
+ DRVCTRL0_QSPI1_MOSI_IO0(3);
+ pfc_reg_write(PFC_DRVCTRL0, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL1);
+ reg = (reg & DRVCTRL1_MASK) |
+ DRVCTRL1_QSPI1_MISO_IO1(3) |
+ DRVCTRL1_QSPI1_IO2(3) |
+ DRVCTRL1_QSPI1_IO3(3) |
+ DRVCTRL1_QSPI1_SS(3) |
+ DRVCTRL1_RPC_INT(3) |
+ DRVCTRL1_RPC_WP(3) |
+ DRVCTRL1_RPC_RESET(3) |
+ DRVCTRL1_AVB_RX_CTL(7);
+ pfc_reg_write(PFC_DRVCTRL1, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL2);
+ reg = (reg & DRVCTRL2_MASK) |
+ DRVCTRL2_AVB_RXC(7) |
+ DRVCTRL2_AVB_RD0(7) |
+ DRVCTRL2_AVB_RD1(7) |
+ DRVCTRL2_AVB_RD2(7) |
+ DRVCTRL2_AVB_RD3(7) |
+ DRVCTRL2_AVB_TX_CTL(3) |
+ DRVCTRL2_AVB_TXC(3) |
+ DRVCTRL2_AVB_TD0(3);
+ pfc_reg_write(PFC_DRVCTRL2, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL3);
+ reg = (reg & DRVCTRL3_MASK) |
+ DRVCTRL3_AVB_TD1(3) |
+ DRVCTRL3_AVB_TD2(3) |
+ DRVCTRL3_AVB_TD3(3) |
+ DRVCTRL3_AVB_TXCREFCLK(7) |
+ DRVCTRL3_AVB_MDIO(7) |
+ DRVCTRL3_AVB_MDC(7) |
+ DRVCTRL3_AVB_MAGIC(7) |
+ DRVCTRL3_AVB_PHY_INT(7);
+ pfc_reg_write(PFC_DRVCTRL3, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL4);
+ reg = (reg & DRVCTRL4_MASK) |
+ DRVCTRL4_AVB_LINK(7) |
+ DRVCTRL4_AVB_AVTP_MATCH(7) |
+ DRVCTRL4_AVB_AVTP_CAPTURE(7) |
+ DRVCTRL4_IRQ0(7) |
+ DRVCTRL4_IRQ1(7) |
+ DRVCTRL4_IRQ2(7) |
+ DRVCTRL4_IRQ3(7) |
+ DRVCTRL4_IRQ4(7);
+ pfc_reg_write(PFC_DRVCTRL4, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL5);
+ reg = (reg & DRVCTRL5_MASK) |
+ DRVCTRL5_IRQ5(7) |
+ DRVCTRL5_PWM0(7) |
+ DRVCTRL5_PWM1(7) |
+ DRVCTRL5_PWM2(7) |
+ DRVCTRL5_A0(3) |
+ DRVCTRL5_A1(3) |
+ DRVCTRL5_A2(3) |
+ DRVCTRL5_A3(3);
+ pfc_reg_write(PFC_DRVCTRL5, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL6);
+ reg = (reg & DRVCTRL6_MASK) |
+ DRVCTRL6_A4(3) |
+ DRVCTRL6_A5(3) |
+ DRVCTRL6_A6(3) |
+ DRVCTRL6_A7(3) |
+ DRVCTRL6_A8(7) |
+ DRVCTRL6_A9(7) |
+ DRVCTRL6_A10(7) |
+ DRVCTRL6_A11(7);
+ pfc_reg_write(PFC_DRVCTRL6, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL7);
+ reg = (reg & DRVCTRL7_MASK) |
+ DRVCTRL7_A12(3) |
+ DRVCTRL7_A13(3) |
+ DRVCTRL7_A14(3) |
+ DRVCTRL7_A15(3) |
+ DRVCTRL7_A16(3) |
+ DRVCTRL7_A17(3) |
+ DRVCTRL7_A18(3) |
+ DRVCTRL7_A19(3);
+ pfc_reg_write(PFC_DRVCTRL7, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL8);
+ reg = (reg & DRVCTRL8_MASK) |
+ DRVCTRL8_CLKOUT(7) |
+ DRVCTRL8_CS0(7) |
+ DRVCTRL8_CS1_A2(7) |
+ DRVCTRL8_BS(7) |
+ DRVCTRL8_RD(7) |
+ DRVCTRL8_RD_W(7) |
+ DRVCTRL8_WE0(7) |
+ DRVCTRL8_WE1(7);
+ pfc_reg_write(PFC_DRVCTRL8, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL9);
+ reg = (reg & DRVCTRL9_MASK) |
+ DRVCTRL9_EX_WAIT0(7) |
+ DRVCTRL9_PRESETOU(7) |
+ DRVCTRL9_D0(7) |
+ DRVCTRL9_D1(7) |
+ DRVCTRL9_D2(7) |
+ DRVCTRL9_D3(7) |
+ DRVCTRL9_D4(7) |
+ DRVCTRL9_D5(7);
+ pfc_reg_write(PFC_DRVCTRL9, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL10);
+ reg = (reg & DRVCTRL10_MASK) |
+ DRVCTRL10_D6(7) |
+ DRVCTRL10_D7(7) |
+ DRVCTRL10_D8(3) |
+ DRVCTRL10_D9(3) |
+ DRVCTRL10_D10(3) |
+ DRVCTRL10_D11(3) |
+ DRVCTRL10_D12(3) |
+ DRVCTRL10_D13(3);
+ pfc_reg_write(PFC_DRVCTRL10, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL11);
+ reg = (reg & DRVCTRL11_MASK) |
+ DRVCTRL11_D14(3) |
+ DRVCTRL11_D15(3) |
+ DRVCTRL11_AVS1(7) |
+ DRVCTRL11_AVS2(7) |
+ DRVCTRL11_GP7_02(7) |
+ DRVCTRL11_GP7_03(7) |
+ DRVCTRL11_DU_DOTCLKIN0(3) |
+ DRVCTRL11_DU_DOTCLKIN1(3);
+ pfc_reg_write(PFC_DRVCTRL11, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL12);
+ reg = (reg & DRVCTRL12_MASK) |
+ DRVCTRL12_DU_DOTCLKIN2(3) |
+ DRVCTRL12_DU_DOTCLKIN3(3) |
+ DRVCTRL12_DU_FSCLKST(3) |
+ DRVCTRL12_DU_TMS(3);
+ pfc_reg_write(PFC_DRVCTRL12, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL13);
+ reg = (reg & DRVCTRL13_MASK) |
+ DRVCTRL13_TDO(3) |
+ DRVCTRL13_ASEBRK(3) |
+ DRVCTRL13_SD0_CLK(7) |
+ DRVCTRL13_SD0_CMD(7) |
+ DRVCTRL13_SD0_DAT0(7) |
+ DRVCTRL13_SD0_DAT1(7) |
+ DRVCTRL13_SD0_DAT2(7) |
+ DRVCTRL13_SD0_DAT3(7);
+ pfc_reg_write(PFC_DRVCTRL13, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL14);
+ reg = (reg & DRVCTRL14_MASK) |
+ DRVCTRL14_SD1_CLK(7) |
+ DRVCTRL14_SD1_CMD(7) |
+ DRVCTRL14_SD1_DAT0(5) |
+ DRVCTRL14_SD1_DAT1(5) |
+ DRVCTRL14_SD1_DAT2(5) |
+ DRVCTRL14_SD1_DAT3(5) |
+ DRVCTRL14_SD2_CLK(5) |
+ DRVCTRL14_SD2_CMD(5);
+ pfc_reg_write(PFC_DRVCTRL14, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL15);
+ reg = (reg & DRVCTRL15_MASK) |
+ DRVCTRL15_SD2_DAT0(5) |
+ DRVCTRL15_SD2_DAT1(5) |
+ DRVCTRL15_SD2_DAT2(5) |
+ DRVCTRL15_SD2_DAT3(5) |
+ DRVCTRL15_SD2_DS(5) |
+ DRVCTRL15_SD3_CLK(7) |
+ DRVCTRL15_SD3_CMD(7) |
+ DRVCTRL15_SD3_DAT0(7);
+ pfc_reg_write(PFC_DRVCTRL15, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL16);
+ reg = (reg & DRVCTRL16_MASK) |
+ DRVCTRL16_SD3_DAT1(7) |
+ DRVCTRL16_SD3_DAT2(7) |
+ DRVCTRL16_SD3_DAT3(7) |
+ DRVCTRL16_SD3_DAT4(7) |
+ DRVCTRL16_SD3_DAT5(7) |
+ DRVCTRL16_SD3_DAT6(7) |
+ DRVCTRL16_SD3_DAT7(7) |
+ DRVCTRL16_SD3_DS(7);
+ pfc_reg_write(PFC_DRVCTRL16, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL17);
+ reg = (reg & DRVCTRL17_MASK) |
+ DRVCTRL17_SD0_CD(7) |
+ DRVCTRL17_SD0_WP(7) |
+ DRVCTRL17_SD1_CD(7) |
+ DRVCTRL17_SD1_WP(7) |
+ DRVCTRL17_SCK0(7) |
+ DRVCTRL17_RX0(7) |
+ DRVCTRL17_TX0(7) |
+ DRVCTRL17_CTS0(7);
+ pfc_reg_write(PFC_DRVCTRL17, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL18);
+ reg = (reg & DRVCTRL18_MASK) |
+ DRVCTRL18_RTS0_TANS(7) |
+ DRVCTRL18_RX1(7) |
+ DRVCTRL18_TX1(7) |
+ DRVCTRL18_CTS1(7) |
+ DRVCTRL18_RTS1_TANS(7) |
+ DRVCTRL18_SCK2(7) |
+ DRVCTRL18_TX2(7) |
+ DRVCTRL18_RX2(7);
+ pfc_reg_write(PFC_DRVCTRL18, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL19);
+ reg = (reg & DRVCTRL19_MASK) |
+ DRVCTRL19_HSCK0(7) |
+ DRVCTRL19_HRX0(7) |
+ DRVCTRL19_HTX0(7) |
+ DRVCTRL19_HCTS0(7) |
+ DRVCTRL19_HRTS0(7) |
+ DRVCTRL19_MSIOF0_SCK(7) |
+ DRVCTRL19_MSIOF0_SYNC(7) |
+ DRVCTRL19_MSIOF0_SS1(7);
+ pfc_reg_write(PFC_DRVCTRL19, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL20);
+ reg = (reg & DRVCTRL20_MASK) |
+ DRVCTRL20_MSIOF0_TXD(7) |
+ DRVCTRL20_MSIOF0_SS2(7) |
+ DRVCTRL20_MSIOF0_RXD(7) |
+ DRVCTRL20_MLB_CLK(7) |
+ DRVCTRL20_MLB_SIG(7) |
+ DRVCTRL20_MLB_DAT(7) |
+ DRVCTRL20_MLB_REF(7) |
+ DRVCTRL20_SSI_SCK0129(7);
+ pfc_reg_write(PFC_DRVCTRL20, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL21);
+ reg = (reg & DRVCTRL21_MASK) |
+ DRVCTRL21_SSI_WS0129(7) |
+ DRVCTRL21_SSI_SDATA0(7) |
+ DRVCTRL21_SSI_SDATA1(7) |
+ DRVCTRL21_SSI_SDATA2(7) |
+ DRVCTRL21_SSI_SCK34(7) |
+ DRVCTRL21_SSI_WS34(7) |
+ DRVCTRL21_SSI_SDATA3(7) |
+ DRVCTRL21_SSI_SCK4(7);
+ pfc_reg_write(PFC_DRVCTRL21, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL22);
+ reg = (reg & DRVCTRL22_MASK) |
+ DRVCTRL22_SSI_WS4(7) |
+ DRVCTRL22_SSI_SDATA4(7) |
+ DRVCTRL22_SSI_SCK5(7) |
+ DRVCTRL22_SSI_WS5(7) |
+ DRVCTRL22_SSI_SDATA5(7) |
+ DRVCTRL22_SSI_SCK6(7) |
+ DRVCTRL22_SSI_WS6(7) |
+ DRVCTRL22_SSI_SDATA6(7);
+ pfc_reg_write(PFC_DRVCTRL22, reg);
+
+ reg = mmio_read_32(PFC_DRVCTRL23);
+ reg = (reg & DRVCTRL23_MASK) |
+ DRVCTRL23_SSI_SCK78(7) |
+ DRVCTRL23_SSI_WS78(7) |
+ DRVCTRL23_SSI_SDATA7(7) |
+ DRVCTRL23_SSI_SDATA8(7) |
+ DRVCTRL23_SSI_SDATA9(7) |
+ DRVCTRL23_AUDIO_CLKA(7) |
+ DRVCTRL23_AUDIO_CLKB(7) |
+ DRVCTRL23_USB0_PWEN(7);
+
+ pfc_reg_write(PFC_DRVCTRL23, reg);
+ reg = mmio_read_32(PFC_DRVCTRL24);
+ reg = (reg & DRVCTRL24_MASK) |
+ DRVCTRL24_USB0_OVC(7) |
+ DRVCTRL24_USB1_PWEN(7) |
+ DRVCTRL24_USB1_OVC(7) |
+ DRVCTRL24_USB30_PWEN(7) |
+ DRVCTRL24_USB30_OVC(7) |
+ DRVCTRL24_USB31_PWEN(7) |
+ DRVCTRL24_USB31_OVC(7);
+ pfc_reg_write(PFC_DRVCTRL24, reg);
+
+ /* initialize LSI pin pull-up/down control */
+ pfc_reg_write(PFC_PUD0, 0x00005FBFU);
+ pfc_reg_write(PFC_PUD1, 0x00300EFEU);
+ pfc_reg_write(PFC_PUD2, 0x330001E6U);
+ pfc_reg_write(PFC_PUD3, 0x000002E0U);
+ pfc_reg_write(PFC_PUD4, 0xFFFFFF00U);
+ pfc_reg_write(PFC_PUD5, 0x7F5FFF87U);
+ pfc_reg_write(PFC_PUD6, 0x00000055U);
+
+ /* initialize LSI pin pull-enable register */
+ pfc_reg_write(PFC_PUEN0, 0x00000FFFU);
+ pfc_reg_write(PFC_PUEN1, 0x00100234U);
+ pfc_reg_write(PFC_PUEN2, 0x000004C4U);
+ pfc_reg_write(PFC_PUEN3, 0x00000200U);
+ pfc_reg_write(PFC_PUEN4, 0x3E000000U);
+ pfc_reg_write(PFC_PUEN5, 0x1F000805U);
+ pfc_reg_write(PFC_PUEN6, 0x00000006U);
+
+ /* initialize positive/negative logic select */
+ mmio_write_32(GPIO_POSNEG0, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG1, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG2, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG3, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG4, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG5, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG6, 0x00000000U);
+ mmio_write_32(GPIO_POSNEG7, 0x00000000U);
+
+ /* initialize general IO/interrupt switching */
+ mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL1, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL2, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL3, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
+ mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
+
+ /* initialize general output register */
+ mmio_write_32(GPIO_OUTDT0, 0x00000001U);
+ mmio_write_32(GPIO_OUTDT1, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT2, 0x00000400U);
+ mmio_write_32(GPIO_OUTDT3, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT4, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT5, 0x00000000U);
+ mmio_write_32(GPIO_OUTDT6, 0x00003800U);
+ mmio_write_32(GPIO_OUTDT7, 0x00000003U);
+
+ /* initialize general input/output switching */
+ mmio_write_32(GPIO_INOUTSEL0, 0x00000001U);
+ mmio_write_32(GPIO_INOUTSEL1, 0x00100B00U);
+ mmio_write_32(GPIO_INOUTSEL2, 0x00000418U);
+ mmio_write_32(GPIO_INOUTSEL3, 0x00002000U);
+ mmio_write_32(GPIO_INOUTSEL4, 0x00000040U);
+ mmio_write_32(GPIO_INOUTSEL5, 0x00000208U);
+ mmio_write_32(GPIO_INOUTSEL6, 0x00013F00U);
+ mmio_write_32(GPIO_INOUTSEL7, 0x00000003U);
+}
diff --git a/drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.h b/drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.h
new file mode 100644
index 0000000..f0616b6
--- /dev/null
+++ b/drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PFC_INIT_G2N_H
+#define PFC_INIT_G2N_H
+
+void pfc_init_g2n(void);
+
+#endif /* PFC_INIT_G2N_H */
diff --git a/drivers/renesas/rzg/pfc/pfc.mk b/drivers/renesas/rzg/pfc/pfc.mk
index 5cae658..15d0e8d 100644
--- a/drivers/renesas/rzg/pfc/pfc.mk
+++ b/drivers/renesas/rzg/pfc/pfc.mk
@@ -1,20 +1,41 @@
#
-# Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+# Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
ifeq (${RCAR_LSI},${RCAR_AUTO})
BL2_SOURCES += drivers/renesas/rzg/pfc/G2M/pfc_init_g2m.c
+ BL2_SOURCES += drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.c
+ BL2_SOURCES += drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.c
+ BL2_SOURCES += drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.c
else ifdef RCAR_LSI_CUT_COMPAT
ifeq (${RCAR_LSI},${RZ_G2M})
BL2_SOURCES += drivers/renesas/rzg/pfc/G2M/pfc_init_g2m.c
endif
+ ifeq (${RCAR_LSI},${RZ_G2H})
+ BL2_SOURCES += drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.c
+ endif
+ ifeq (${RCAR_LSI},${RZ_G2N})
+ BL2_SOURCES += drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.c
+ endif
+ ifeq (${RCAR_LSI},${RZ_G2E})
+ BL2_SOURCES += drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.c
+ endif
else
ifeq (${RCAR_LSI},${RZ_G2M})
BL2_SOURCES += drivers/renesas/rzg/pfc/G2M/pfc_init_g2m.c
endif
+ ifeq (${RCAR_LSI},${RZ_G2H})
+ BL2_SOURCES += drivers/renesas/rzg/pfc/G2H/pfc_init_g2h.c
+ endif
+ ifeq (${RCAR_LSI},${RZ_G2N})
+ BL2_SOURCES += drivers/renesas/rzg/pfc/G2N/pfc_init_g2n.c
+ endif
+ ifeq (${RCAR_LSI},${RZ_G2E})
+ BL2_SOURCES += drivers/renesas/rzg/pfc/G2E/pfc_init_g2e.c
+ endif
endif
BL2_SOURCES += drivers/renesas/rzg/pfc/pfc_init.c
diff --git a/drivers/renesas/rzg/pfc/pfc_init.c b/drivers/renesas/rzg/pfc/pfc_init.c
index f51992d..762450c 100644
--- a/drivers/renesas/rzg/pfc/pfc_init.c
+++ b/drivers/renesas/rzg/pfc/pfc_init.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,11 +9,23 @@
#include <lib/mmio.h>
#if RCAR_LSI == RCAR_AUTO
+#include "G2E/pfc_init_g2e.h"
+#include "G2H/pfc_init_g2h.h"
#include "G2M/pfc_init_g2m.h"
+#include "G2N/pfc_init_g2n.h"
#endif /* RCAR_LSI == RCAR_AUTO */
+#if (RCAR_LSI == RZ_G2E)
+#include "G2E/pfc_init_g2e.h"
+#endif /* RCAR_LSI == RZ_G2N */
+#if (RCAR_LSI == RZ_G2H)
+#include "G2H/pfc_init_g2h.h"
+#endif /* RCAR_LSI == RZ_G2H */
#if (RCAR_LSI == RZ_G2M)
#include "G2M/pfc_init_g2m.h"
#endif /* RCAR_LSI == RZ_G2M */
+#if (RCAR_LSI == RZ_G2N)
+#include "G2N/pfc_init_g2n.h"
+#endif /* RCAR_LSI == RZ_G2N */
#include "rcar_def.h"
#define PRR_PRODUCT_ERR(reg) \
@@ -40,6 +52,15 @@
case PRR_PRODUCT_M3:
pfc_init_g2m();
break;
+ case PRR_PRODUCT_H3:
+ pfc_init_g2h();
+ break;
+ case PRR_PRODUCT_M3N:
+ pfc_init_g2n();
+ break;
+ case PRR_PRODUCT_E3:
+ pfc_init_g2e();
+ break;
default:
PRR_PRODUCT_ERR(reg);
break;
@@ -54,6 +75,27 @@
pfc_init_g2m();
#endif /* RCAR_LSI != RZ_G2M */
break;
+ case PRR_PRODUCT_H3:
+#if (RCAR_LSI != RZ_G2H)
+ PRR_PRODUCT_ERR(reg);
+#else /* RCAR_LSI != RZ_G2H */
+ pfc_init_g2h();
+#endif /* RCAR_LSI != RZ_G2H */
+ break;
+ case PRR_PRODUCT_M3N:
+#if RCAR_LSI != RZ_G2N
+ PRR_PRODUCT_ERR(reg);
+#else
+ pfc_init_g2n();
+#endif /* RCAR_LSI != RZ_G2N */
+ break;
+ case PRR_PRODUCT_E3:
+#if RCAR_LSI != RZ_G2E
+ PRR_PRODUCT_ERR(reg);
+#else
+ pfc_init_g2e();
+#endif
+ break;
default:
PRR_PRODUCT_ERR(reg);
break;
@@ -65,6 +107,21 @@
PRR_PRODUCT_ERR(reg);
}
pfc_init_m3();
+#elif (RCAR_LSI == RZ_G2H)
+ if ((reg & PRR_PRODUCT_MASK) != PRR_PRODUCT_H3) {
+ PRR_PRODUCT_ERR(reg);
+ }
+ pfc_init_g2h();
+#elif (RCAR_LSI == RZ_G2N) /* G2N */
+ if ((reg & PRR_PRODUCT_MASK) != PRR_PRODUCT_M3N) {
+ PRR_PRODUCT_ERR(reg);
+ }
+ pfc_init_g2n();
+#elif (RCAR_LSI == RZ_G2E)
+ if ((reg & PRR_PRODUCT_MASK) != PRR_PRODUCT_E3) {
+ PRR_PRODUCT_ERR(reg);
+ }
+ pfc_init_g2e();
#else /* RCAR_LSI == RZ_G2M */
#error "Don't have PFC initialize routine(unknown)."
#endif /* RCAR_LSI == RZ_G2M */
diff --git a/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.c b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.c
new file mode 100644
index 0000000..14ccc21
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include "qos_init_g2e_v10.h"
+#include "../qos_common.h"
+#include "../qos_reg.h"
+
+#define RCAR_QOS_VERSION "rev.0.05"
+
+#define REF_ARS_ARBSTOPCYCLE_G2E (((SL_INIT_SSLOTCLK_G2E) - 5U) << 16U)
+
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_g2e_v10_mstat390.h"
+#else
+#include "qos_init_g2e_v10_mstat780.h"
+#endif /* RCAR_REF_INT == RCAR_REF_DEFAULT */
+#endif /* RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT */
+
+static const struct rcar_gen3_dbsc_qos_settings g2e_qos[] = {
+ /* BUFCAM settings */
+ { DBSC_DBCAM0CNF1, 0x00043218U },
+ { DBSC_DBCAM0CNF2, 0x000000F4U },
+ { DBSC_DBSCHCNT0, 0x000F0037U },
+ { DBSC_DBSCHSZ0, 0x00000001U },
+ { DBSC_DBSCHRW0, 0x22421111U },
+
+ /* DDR3 */
+ { DBSC_SCFCTST2, 0x012F1123U },
+
+ /* QoS Settings */
+ { DBSC_DBSCHQOS00, 0x00000F00U },
+ { DBSC_DBSCHQOS01, 0x00000B00U },
+ { DBSC_DBSCHQOS02, 0x00000000U },
+ { DBSC_DBSCHQOS03, 0x00000000U },
+ { DBSC_DBSCHQOS40, 0x00000300U },
+ { DBSC_DBSCHQOS41, 0x000002F0U },
+ { DBSC_DBSCHQOS42, 0x00000200U },
+ { DBSC_DBSCHQOS43, 0x00000100U },
+ { DBSC_DBSCHQOS90, 0x00000100U },
+ { DBSC_DBSCHQOS91, 0x000000F0U },
+ { DBSC_DBSCHQOS92, 0x000000A0U },
+ { DBSC_DBSCHQOS93, 0x00000040U },
+ { DBSC_DBSCHQOS130, 0x00000100U },
+ { DBSC_DBSCHQOS131, 0x000000F0U },
+ { DBSC_DBSCHQOS132, 0x000000A0U },
+ { DBSC_DBSCHQOS133, 0x00000040U },
+ { DBSC_DBSCHQOS140, 0x000000C0U },
+ { DBSC_DBSCHQOS141, 0x000000B0U },
+ { DBSC_DBSCHQOS142, 0x00000080U },
+ { DBSC_DBSCHQOS143, 0x00000040U },
+ { DBSC_DBSCHQOS150, 0x00000040U },
+ { DBSC_DBSCHQOS151, 0x00000030U },
+ { DBSC_DBSCHQOS152, 0x00000020U },
+ { DBSC_DBSCHQOS153, 0x00000010U },
+};
+
+void qos_init_g2e_v10(void)
+{
+ rzg_qos_dbsc_setting(g2e_qos, ARRAY_SIZE(g2e_qos), true);
+
+ /* DRAM Split Address mapping */
+#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
+#if RCAR_LSI == RCAR_RZ_G2E
+#error "Don't set DRAM Split 4ch(G2E)"
+#else
+ ERROR("DRAM Split 4ch not supported.(G2E)");
+ panic();
+#endif
+#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH)
+#if RCAR_LSI == RCAR_RZ_G2E
+#error "Don't set DRAM Split 2ch(G2E)"
+#else
+ ERROR("DRAM Split 2ch not supported.(G2E)");
+ panic();
+#endif
+#else
+ NOTICE("BL2: DRAM Split is OFF\n");
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+ NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+ NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
+#else
+ NOTICE("BL2: DRAM refresh interval 7.8 usec\n");
+#endif
+
+ mmio_write_32(QOSCTRL_RAS, 0x00000020U);
+ mmio_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
+ mmio_write_32(QOSCTRL_DANT, 0x00100804U);
+ mmio_write_32(QOSCTRL_FSS, 0x0000000AU);
+ mmio_write_32(QOSCTRL_INSFC, 0x06330001U);
+ mmio_write_32(QOSCTRL_EARLYR, 0x00000000U);
+ mmio_write_32(QOSCTRL_RACNT0, 0x00010003U);
+
+ mmio_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT |
+ SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK_G2E);
+ mmio_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_G2E);
+
+ /* QOSBW SRAM setting */
+ uint32_t i;
+
+ for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+ mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]);
+ mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+ mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]);
+ mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]);
+ }
+
+ /* RT bus Leaf setting */
+ mmio_write_32(RT_ACT0, 0x00000000U);
+ mmio_write_32(RT_ACT1, 0x00000000U);
+
+ /* CCI bus Leaf setting */
+ mmio_write_32(CPU_ACT0, 0x00000003U);
+ mmio_write_32(CPU_ACT1, 0x00000003U);
+
+ mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+ mmio_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+ NOTICE("BL2: QoS is None\n");
+
+ mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif
+}
diff --git a/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.h b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.h
new file mode 100644
index 0000000..d27de1b
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2E_V10_H
+#define QOS_INIT_G2E_V10_H
+
+void qos_init_g2e_v10(void);
+
+#endif /* QOS_INIT_G2E_V10_H */
diff --git a/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10_mstat390.h b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10_mstat390.h
new file mode 100644
index 0000000..63b08c4
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10_mstat390.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2E_V10_MSTAT390_H
+#define QOS_INIT_G2E_V10_MSTAT390_H
+
+static uint64_t mstat_fix[] = {
+ /* 0x0000, */ 0x0000000000000000UL,
+ /* 0x0008, */ 0x0000000000000000UL,
+ /* 0x0010, */ 0x0000000000000000UL,
+ /* 0x0018, */ 0x0000000000000000UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0000000000000000UL,
+ /* 0x0030, */ 0x001008620000FFFFUL,
+ /* 0x0038, */ 0x001008620000FFFFUL,
+ /* 0x0040, */ 0x0000000000000000UL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x0000000000000000UL,
+ /* 0x0058, */ 0x001415260000FFFFUL,
+ /* 0x0060, */ 0x001415260000FFFFUL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x0000000000000000UL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x001414930000FFFFUL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00a0, */ 0x000C08380000FFFFUL,
+ /* 0x00a8, */ 0x000C04110000FFFFUL,
+ /* 0x00b0, */ 0x000C04150000FFFFUL,
+ /* 0x00b8, */ 0x0000000000000000UL,
+ /* 0x00c0, */ 0x000C08380000FFFFUL,
+ /* 0x00c8, */ 0x000C04110000FFFFUL,
+ /* 0x00d0, */ 0x000C04150000FFFFUL,
+ /* 0x00d8, */ 0x0000000000000000UL,
+ /* 0x00e0, */ 0x0000000000000000UL,
+ /* 0x00e8, */ 0x0000000000000000UL,
+ /* 0x00f0, */ 0x0000000000000000UL,
+ /* 0x00f8, */ 0x000C084F0000FFFFUL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x0000000000000000UL,
+ /* 0x0118, */ 0x000C21E40000FFFFUL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x001008530000FFFFUL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x00100C960000FFFFUL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x001008530000FFFFUL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x0010042A0000FFFFUL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x00101D8D0000FFFFUL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01a0, */ 0x001008530000FFFFUL,
+ /* 0x01a8, */ 0x0000000000000000UL,
+ /* 0x01b0, */ 0x0000000000000000UL,
+ /* 0x01b8, */ 0x0000000000000000UL,
+ /* 0x01c0, */ 0x000C04010000FFFFUL,
+ /* 0x01c8, */ 0x000C04010000FFFFUL,
+ /* 0x01d0, */ 0x0000000000000000UL,
+ /* 0x01d8, */ 0x0000000000000000UL,
+ /* 0x01e0, */ 0x0000000000000000UL,
+ /* 0x01e8, */ 0x0000000000000000UL,
+ /* 0x01f0, */ 0x0000000000000000UL,
+ /* 0x01f8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x0000000000000000UL,
+ /* 0x0210, */ 0x0000000000000000UL,
+ /* 0x0218, */ 0x0000000000000000UL,
+ /* 0x0220, */ 0x0000000000000000UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x0000000000000000UL,
+ /* 0x0238, */ 0x0000000000000000UL,
+ /* 0x0240, */ 0x0000000000000000UL,
+ /* 0x0248, */ 0x0000000000000000UL,
+ /* 0x0250, */ 0x0000000000000000UL,
+ /* 0x0258, */ 0x0000000000000000UL,
+ /* 0x0260, */ 0x0000000000000000UL,
+ /* 0x0268, */ 0x001410040000FFFFUL,
+ /* 0x0270, */ 0x001404020000FFFFUL,
+ /* 0x0278, */ 0x0000000000000000UL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x001410040000FFFFUL,
+ /* 0x0298, */ 0x001404020000FFFFUL,
+ /* 0x02a0, */ 0x000C04090000FFFFUL,
+ /* 0x02a8, */ 0x000C04090000FFFFUL,
+ /* 0x02b0, */ 0x0000000000000000UL,
+ /* 0x02b8, */ 0x0000000000000000UL,
+ /* 0x02c0, */ 0x0000000000000000UL,
+ /* 0x02c8, */ 0x0000000000000000UL,
+ /* 0x02d0, */ 0x000C04090000FFFFUL,
+ /* 0x02d8, */ 0x000C04090000FFFFUL,
+ /* 0x02e0, */ 0x0000000000000000UL,
+ /* 0x02e8, */ 0x0000000000000000UL,
+ /* 0x02f0, */ 0x0000000000000000UL,
+ /* 0x02f8, */ 0x0000000000000000UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0000000000000000UL,
+ /* 0x0310, */ 0x0000000000000000UL,
+ /* 0x0318, */ 0x0000000000000000UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+ /* 0x0358, */ 0x0000000000000000UL,
+ /* 0x0360, */ 0x0000000000000000UL,
+ /* 0x0368, */ 0x0000000000000000UL,
+ /* 0x0370, */ 0x000C04020000FFFFUL,
+ /* 0x0378, */ 0x000C04020000FFFFUL,
+ /* 0x0380, */ 0x000C04090000FFFFUL,
+ /* 0x0388, */ 0x000C04090000FFFFUL,
+ /* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+ /* 0x0000, */ 0x0000000000000000UL,
+ /* 0x0008, */ 0x0000000000000000UL,
+ /* 0x0010, */ 0x0000000000000000UL,
+ /* 0x0018, */ 0x0000000000000000UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0012001005F03401UL,
+ /* 0x0030, */ 0x0000000000000000UL,
+ /* 0x0038, */ 0x0000000000000000UL,
+ /* 0x0040, */ 0x0000000000000000UL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x0000000000000000UL,
+ /* 0x0058, */ 0x0000000000000000UL,
+ /* 0x0060, */ 0x0000000000000000UL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x0000000000000000UL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x0000000000000000UL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00a0, */ 0x0000000000000000UL,
+ /* 0x00a8, */ 0x0000000000000000UL,
+ /* 0x00b0, */ 0x0000000000000000UL,
+ /* 0x00b8, */ 0x0000000000000000UL,
+ /* 0x00c0, */ 0x0000000000000000UL,
+ /* 0x00c8, */ 0x0000000000000000UL,
+ /* 0x00d0, */ 0x0000000000000000UL,
+ /* 0x00d8, */ 0x0000000000000000UL,
+ /* 0x00e0, */ 0x0000000000000000UL,
+ /* 0x00e8, */ 0x0000000000000000UL,
+ /* 0x00f0, */ 0x0000000000000000UL,
+ /* 0x00f8, */ 0x0000000000000000UL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x0000000000000000UL,
+ /* 0x0118, */ 0x0000000000000000UL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x0000000000000000UL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x0000000000000000UL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x0000000000000000UL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x0000000000000000UL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x0000000000000000UL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01a0, */ 0x0000000000000000UL,
+ /* 0x01a8, */ 0x0000000000000000UL,
+ /* 0x01b0, */ 0x0000000000000000UL,
+ /* 0x01b8, */ 0x0000000000000000UL,
+ /* 0x01c0, */ 0x0021060005FFFC01UL,
+ /* 0x01c8, */ 0x0021060005FFFC01UL,
+ /* 0x01d0, */ 0x0000000000000000UL,
+ /* 0x01d8, */ 0x0000000000000000UL,
+ /* 0x01e0, */ 0x0000000000000000UL,
+ /* 0x01e8, */ 0x0000000000000000UL,
+ /* 0x01f0, */ 0x0000000000000000UL,
+ /* 0x01f8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x0000000000000000UL,
+ /* 0x0210, */ 0x0000000000000000UL,
+ /* 0x0218, */ 0x0011010005F79801UL,
+ /* 0x0220, */ 0x0011010005F79801UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x0011010005F79801UL,
+ /* 0x0238, */ 0x0011010005F79801UL,
+ /* 0x0240, */ 0x0012010005F79801UL,
+ /* 0x0248, */ 0x0011010005F79801UL,
+ /* 0x0250, */ 0x0012010005F79801UL,
+ /* 0x0258, */ 0x0011010005F79801UL,
+ /* 0x0260, */ 0x0000000000000000UL,
+ /* 0x0268, */ 0x0000000000000000UL,
+ /* 0x0270, */ 0x0000000000000000UL,
+ /* 0x0278, */ 0x0000000000000000UL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x0000000000000000UL,
+ /* 0x0298, */ 0x0000000000000000UL,
+ /* 0x02a0, */ 0x0000000000000000UL,
+ /* 0x02a8, */ 0x0000000000000000UL,
+ /* 0x02b0, */ 0x0000000000000000UL,
+ /* 0x02b8, */ 0x0000000000000000UL,
+ /* 0x02c0, */ 0x0000000000000000UL,
+ /* 0x02c8, */ 0x0000000000000000UL,
+ /* 0x02d0, */ 0x0000000000000000UL,
+ /* 0x02d8, */ 0x0000000000000000UL,
+ /* 0x02e0, */ 0x0000000000000000UL,
+ /* 0x02e8, */ 0x0000000000000000UL,
+ /* 0x02f0, */ 0x0011060005FFFC01UL,
+ /* 0x02f8, */ 0x0011060005FFFC01UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0000000000000000UL,
+ /* 0x0310, */ 0x0000000000000000UL,
+ /* 0x0318, */ 0x0012001005F03401UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+ /* 0x0358, */ 0x0012060005FFFC01UL,
+ /* 0x0360, */ 0x0012060005FFFC01UL,
+ /* 0x0368, */ 0x0012001005F03401UL,
+ /* 0x0370, */ 0x0000000000000000UL,
+ /* 0x0378, */ 0x0000000000000000UL,
+ /* 0x0380, */ 0x0000000000000000UL,
+ /* 0x0388, */ 0x0000000000000000UL,
+ /* 0x0390, */ 0x0012001005F03401UL,
+};
+#endif /* QOS_INIT_G2E_V10_MSTAT390_H */
diff --git a/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10_mstat780.h b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10_mstat780.h
new file mode 100644
index 0000000..3b888ea
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10_mstat780.h
@@ -0,0 +1,246 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2E_V10_MSTAT780_H
+#define QOS_INIT_G2E_V10_MSTAT780_H
+
+static uint64_t mstat_fix[] = {
+ /* 0x0000, */ 0x0000000000000000UL,
+ /* 0x0008, */ 0x0000000000000000UL,
+ /* 0x0010, */ 0x0000000000000000UL,
+ /* 0x0018, */ 0x0000000000000000UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0000000000000000UL,
+ /* 0x0030, */ 0x001010C40000FFFFUL,
+ /* 0x0038, */ 0x001010C40000FFFFUL,
+ /* 0x0040, */ 0x0000000000000000UL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x0000000000000000UL,
+ /* 0x0058, */ 0x00142A4B0000FFFFUL,
+ /* 0x0060, */ 0x00142A4B0000FFFFUL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x0000000000000000UL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x001429260000FFFFUL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00a0, */ 0x000C10700000FFFFUL,
+ /* 0x00a8, */ 0x000C08210000FFFFUL,
+ /* 0x00b0, */ 0x000C082A0000FFFFUL,
+ /* 0x00b8, */ 0x0000000000000000UL,
+ /* 0x00c0, */ 0x000C10700000FFFFUL,
+ /* 0x00c8, */ 0x000C08210000FFFFUL,
+ /* 0x00d0, */ 0x000C082A0000FFFFUL,
+ /* 0x00d8, */ 0x0000000000000000UL,
+ /* 0x00e0, */ 0x0000000000000000UL,
+ /* 0x00e8, */ 0x0000000000000000UL,
+ /* 0x00f0, */ 0x00102CAF0000FFFFUL,
+ /* 0x00f8, */ 0x000C0C9D0000FFFFUL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x00100CAF0000FFFFUL,
+ /* 0x0118, */ 0x000C43C80000FFFFUL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x00100CA50000FFFFUL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x0010152C0000FFFFUL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x00100CA50000FFFFUL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x001008530000FFFFUL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x001037190000FFFFUL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01a0, */ 0x00100CA50000FFFFUL,
+ /* 0x01a8, */ 0x0000000000000000UL,
+ /* 0x01b0, */ 0x0000000000000000UL,
+ /* 0x01b8, */ 0x0000000000000000UL,
+ /* 0x01c0, */ 0x000C04010000FFFFUL,
+ /* 0x01c8, */ 0x000C04010000FFFFUL,
+ /* 0x01d0, */ 0x0000000000000000UL,
+ /* 0x01d8, */ 0x0000000000000000UL,
+ /* 0x01e0, */ 0x0000000000000000UL,
+ /* 0x01e8, */ 0x000C04040000FFFFUL,
+ /* 0x01f0, */ 0x000C08110000FFFFUL,
+ /* 0x01f8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x000C04110000FFFFUL,
+ /* 0x0210, */ 0x000C08110000FFFFUL,
+ /* 0x0218, */ 0x0000000000000000UL,
+ /* 0x0220, */ 0x0000000000000000UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x0000000000000000UL,
+ /* 0x0238, */ 0x0000000000000000UL,
+ /* 0x0240, */ 0x0000000000000000UL,
+ /* 0x0248, */ 0x0000000000000000UL,
+ /* 0x0250, */ 0x0000000000000000UL,
+ /* 0x0258, */ 0x0000000000000000UL,
+ /* 0x0260, */ 0x000C18530000FFFFUL,
+ /* 0x0268, */ 0x00141C070000FFFFUL,
+ /* 0x0270, */ 0x001404040000FFFFUL,
+ /* 0x0278, */ 0x000C0C210000FFFFUL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x00141C070000FFFFUL,
+ /* 0x0298, */ 0x001404040000FFFFUL,
+ /* 0x02a0, */ 0x000C04110000FFFFUL,
+ /* 0x02a8, */ 0x000C04110000FFFFUL,
+ /* 0x02b0, */ 0x0000000000000000UL,
+ /* 0x02b8, */ 0x000C04040000FFFFUL,
+ /* 0x02c0, */ 0x0000000000000000UL,
+ /* 0x02c8, */ 0x0000000000000000UL,
+ /* 0x02d0, */ 0x000C04110000FFFFUL,
+ /* 0x02d8, */ 0x000C04110000FFFFUL,
+ /* 0x02e0, */ 0x0000000000000000UL,
+ /* 0x02e8, */ 0x000C04040000FFFFUL,
+ /* 0x02f0, */ 0x0000000000000000UL,
+ /* 0x02f8, */ 0x0000000000000000UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0000000000000000UL,
+ /* 0x0310, */ 0x0000000000000000UL,
+ /* 0x0318, */ 0x0000000000000000UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+ /* 0x0358, */ 0x0000000000000000UL,
+ /* 0x0360, */ 0x0000000000000000UL,
+ /* 0x0368, */ 0x0000000000000000UL,
+ /* 0x0370, */ 0x000C04040000FFFFUL,
+ /* 0x0378, */ 0x000C04040000FFFFUL,
+ /* 0x0380, */ 0x000C04110000FFFFUL,
+ /* 0x0388, */ 0x000C04110000FFFFUL,
+ /* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+ /* 0x0000, */ 0x0000000000000000UL,
+ /* 0x0008, */ 0x0000000000000000UL,
+ /* 0x0010, */ 0x0000000000000000UL,
+ /* 0x0018, */ 0x0000000000000000UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0012001002F03401UL,
+ /* 0x0030, */ 0x0000000000000000UL,
+ /* 0x0038, */ 0x0000000000000000UL,
+ /* 0x0040, */ 0x0000000000000000UL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x0000000000000000UL,
+ /* 0x0058, */ 0x0000000000000000UL,
+ /* 0x0060, */ 0x0000000000000000UL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x0000000000000000UL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x0000000000000000UL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00a0, */ 0x0000000000000000UL,
+ /* 0x00a8, */ 0x0000000000000000UL,
+ /* 0x00b0, */ 0x0000000000000000UL,
+ /* 0x00b8, */ 0x0000000000000000UL,
+ /* 0x00c0, */ 0x0000000000000000UL,
+ /* 0x00c8, */ 0x0000000000000000UL,
+ /* 0x00d0, */ 0x0000000000000000UL,
+ /* 0x00d8, */ 0x0000000000000000UL,
+ /* 0x00e0, */ 0x0000000000000000UL,
+ /* 0x00e8, */ 0x0000000000000000UL,
+ /* 0x00f0, */ 0x0000000000000000UL,
+ /* 0x00f8, */ 0x0000000000000000UL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x0000000000000000UL,
+ /* 0x0118, */ 0x0000000000000000UL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x0000000000000000UL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x0000000000000000UL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x0000000000000000UL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x0000000000000000UL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x0000000000000000UL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01a0, */ 0x0000000000000000UL,
+ /* 0x01a8, */ 0x0000000000000000UL,
+ /* 0x01b0, */ 0x0000000000000000UL,
+ /* 0x01b8, */ 0x0000000000000000UL,
+ /* 0x01c0, */ 0x0021060002FFFC01UL,
+ /* 0x01c8, */ 0x0021060002FFFC01UL,
+ /* 0x01d0, */ 0x0000000000000000UL,
+ /* 0x01d8, */ 0x0000000000000000UL,
+ /* 0x01e0, */ 0x0000000000000000UL,
+ /* 0x01e8, */ 0x0000000000000000UL,
+ /* 0x01f0, */ 0x0021010002F3CC01UL,
+ /* 0x01f8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x0000000000000000UL,
+ /* 0x0210, */ 0x0021010002F3CC01UL,
+ /* 0x0218, */ 0x0011010002F3CC01UL,
+ /* 0x0220, */ 0x0011010002F3CC01UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x0011010002F3CC01UL,
+ /* 0x0238, */ 0x0011010002F3CC01UL,
+ /* 0x0240, */ 0x0012010002F3CC01UL,
+ /* 0x0248, */ 0x0011010002F3CC01UL,
+ /* 0x0250, */ 0x0012010002F3CC01UL,
+ /* 0x0258, */ 0x0011010002F3CC01UL,
+ /* 0x0260, */ 0x0000000000000000UL,
+ /* 0x0268, */ 0x0000000000000000UL,
+ /* 0x0270, */ 0x0000000000000000UL,
+ /* 0x0278, */ 0x0000000000000000UL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x0000000000000000UL,
+ /* 0x0298, */ 0x0000000000000000UL,
+ /* 0x02a0, */ 0x0000000000000000UL,
+ /* 0x02a8, */ 0x0000000000000000UL,
+ /* 0x02b0, */ 0x0000000000000000UL,
+ /* 0x02b8, */ 0x0000000000000000UL,
+ /* 0x02c0, */ 0x0000000000000000UL,
+ /* 0x02c8, */ 0x0000000000000000UL,
+ /* 0x02d0, */ 0x0000000000000000UL,
+ /* 0x02d8, */ 0x0000000000000000UL,
+ /* 0x02e0, */ 0x0000000000000000UL,
+ /* 0x02e8, */ 0x0000000000000000UL,
+ /* 0x02f0, */ 0x0011060002FFFC01UL,
+ /* 0x02f8, */ 0x0011060002FFFC01UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0000000000000000UL,
+ /* 0x0310, */ 0x0000000000000000UL,
+ /* 0x0318, */ 0x0012001002F03401UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+ /* 0x0358, */ 0x0012060002FFFC01UL,
+ /* 0x0360, */ 0x0012060002FFFC01UL,
+ /* 0x0368, */ 0x0012001002F03401UL,
+ /* 0x0370, */ 0x0000000000000000UL,
+ /* 0x0378, */ 0x0000000000000000UL,
+ /* 0x0380, */ 0x0000000000000000UL,
+ /* 0x0388, */ 0x0000000000000000UL,
+ /* 0x0390, */ 0x0012001002F03401UL,
+};
+
+#endif /* QOS_INIT_G2E_V10_MSTAT780_H */
diff --git a/drivers/renesas/rzg/qos/G2H/qos_init_g2h_mstat195.h b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_mstat195.h
new file mode 100644
index 0000000..7bb34aa
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_mstat195.h
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2H_MSTAT195_H
+#define QOS_INIT_G2H_MSTAT195_H
+
+static uint64_t mstat_fix[] = {
+ /* 0x0000, */ 0x0000000000000000UL,
+ /* 0x0008, */ 0x0000000000000000UL,
+ /* 0x0010, */ 0x0000000000000000UL,
+ /* 0x0018, */ 0x0000000000000000UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0000000000000000UL,
+ /* 0x0030, */ 0x001004040000FFFFUL,
+ /* 0x0038, */ 0x001008070000FFFFUL,
+ /* 0x0040, */ 0x001410070000FFFFUL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x001404010000FFFFUL,
+ /* 0x0058, */ 0x0014100D0000FFFFUL,
+ /* 0x0060, */ 0x0014100D0000FFFFUL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x001404010000FFFFUL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x001410070000FFFFUL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00a0, */ 0x000C04020000FFFFUL,
+ /* 0x00a8, */ 0x000C04010000FFFFUL,
+ /* 0x00b0, */ 0x000C04010000FFFFUL,
+ /* 0x00b8, */ 0x0000000000000000UL,
+ /* 0x00c0, */ 0x000C04020000FFFFUL,
+ /* 0x00c8, */ 0x000C04010000FFFFUL,
+ /* 0x00d0, */ 0x000C04010000FFFFUL,
+ /* 0x00d8, */ 0x001024090000FFFFUL,
+ /* 0x00e0, */ 0x00100C090000FFFFUL,
+ /* 0x00e8, */ 0x0000000000000000UL,
+ /* 0x00f0, */ 0x001024090000FFFFUL,
+ /* 0x00f8, */ 0x000C100D0000FFFFUL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x00100C090000FFFFUL,
+ /* 0x0118, */ 0x000C1C1B0000FFFFUL,
+ /* 0x0120, */ 0x000C1C1B0000FFFFUL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x00100C0B0000FFFFUL,
+ /* 0x0140, */ 0x00100C0B0000FFFFUL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x0010100D0000FFFFUL,
+ /* 0x0158, */ 0x0010100D0000FFFFUL,
+ /* 0x0160, */ 0x00100C0B0000FFFFUL,
+ /* 0x0168, */ 0x00100C0B0000FFFFUL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x001008060000FFFFUL,
+ /* 0x0180, */ 0x001008060000FFFFUL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x00102C2C0000FFFFUL,
+ /* 0x0198, */ 0x00102C2C0000FFFFUL,
+ /* 0x01a0, */ 0x00100C0B0000FFFFUL,
+ /* 0x01a8, */ 0x00100C0B0000FFFFUL,
+ /* 0x01b0, */ 0x0000000000000000UL,
+ /* 0x01b8, */ 0x0000000000000000UL,
+ /* 0x01c0, */ 0x000C04010000FFFFUL,
+ /* 0x01c8, */ 0x000C04010000FFFFUL,
+ /* 0x01d0, */ 0x000C04010000FFFFUL,
+ /* 0x01d8, */ 0x000C04010000FFFFUL,
+ /* 0x01e0, */ 0x0000000000000000UL,
+ /* 0x01e8, */ 0x000C04010000FFFFUL,
+ /* 0x01f0, */ 0x000C04010000FFFFUL,
+ /* 0x01f8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x000C04010000FFFFUL,
+ /* 0x0210, */ 0x000C04010000FFFFUL,
+ /* 0x0218, */ 0x0000000000000000UL,
+ /* 0x0220, */ 0x0000000000000000UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x0000000000000000UL,
+ /* 0x0238, */ 0x0000000000000000UL,
+ /* 0x0240, */ 0x0000000000000000UL,
+ /* 0x0248, */ 0x0000000000000000UL,
+ /* 0x0250, */ 0x0000000000000000UL,
+ /* 0x0258, */ 0x0000000000000000UL,
+ /* 0x0260, */ 0x000C08020000FFFFUL,
+ /* 0x0268, */ 0x001408010000FFFFUL,
+ /* 0x0270, */ 0x001404010000FFFFUL,
+ /* 0x0278, */ 0x000C04010000FFFFUL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x001408010000FFFFUL,
+ /* 0x0298, */ 0x001404010000FFFFUL,
+ /* 0x02a0, */ 0x000C04010000FFFFUL,
+ /* 0x02a8, */ 0x000C04010000FFFFUL,
+ /* 0x02b0, */ 0x001408010000FFFFUL,
+ /* 0x02b8, */ 0x000C04010000FFFFUL,
+ /* 0x02c0, */ 0x0000000000000000UL,
+ /* 0x02c8, */ 0x0000000000000000UL,
+ /* 0x02d0, */ 0x000C04010000FFFFUL,
+ /* 0x02d8, */ 0x000C04010000FFFFUL,
+ /* 0x02e0, */ 0x001408010000FFFFUL,
+ /* 0x02e8, */ 0x000C04010000FFFFUL,
+ /* 0x02f0, */ 0x0000000000000000UL,
+ /* 0x02f8, */ 0x0000000000000000UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0000000000000000UL,
+ /* 0x0310, */ 0x0000000000000000UL,
+ /* 0x0318, */ 0x0000000000000000UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+ /* 0x0358, */ 0x0000000000000000UL,
+ /* 0x0360, */ 0x0000000000000000UL,
+ /* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+ /* 0x0000, */ 0x001200600BDFFC01UL,
+ /* 0x0008, */ 0x001200600BDFFC01UL,
+ /* 0x0010, */ 0x001200600BDFFC01UL,
+ /* 0x0018, */ 0x001200600BDFFC01UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x001200100BD0FC01UL,
+ /* 0x0030, */ 0x0000000000000000UL,
+ /* 0x0038, */ 0x0000000000000000UL,
+ /* 0x0040, */ 0x0000000000000000UL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x0000000000000000UL,
+ /* 0x0058, */ 0x0000000000000000UL,
+ /* 0x0060, */ 0x0000000000000000UL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x0000000000000000UL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x0000000000000000UL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00a0, */ 0x0000000000000000UL,
+ /* 0x00a8, */ 0x0000000000000000UL,
+ /* 0x00b0, */ 0x0000000000000000UL,
+ /* 0x00b8, */ 0x0000000000000000UL,
+ /* 0x00c0, */ 0x0000000000000000UL,
+ /* 0x00c8, */ 0x0000000000000000UL,
+ /* 0x00d0, */ 0x0000000000000000UL,
+ /* 0x00d8, */ 0x0000000000000000UL,
+ /* 0x00e0, */ 0x0000000000000000UL,
+ /* 0x00e8, */ 0x0000000000000000UL,
+ /* 0x00f0, */ 0x0000000000000000UL,
+ /* 0x00f8, */ 0x0000000000000000UL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x0000000000000000UL,
+ /* 0x0118, */ 0x0000000000000000UL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x0000000000000000UL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x0000000000000000UL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x0000000000000000UL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x0000000000000000UL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x0000000000000000UL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01a0, */ 0x0000000000000000UL,
+ /* 0x01a8, */ 0x0000000000000000UL,
+ /* 0x01b0, */ 0x0000000000000000UL,
+ /* 0x01b8, */ 0x0000000000000000UL,
+ /* 0x01c0, */ 0x002100600BDFFC01UL,
+ /* 0x01c8, */ 0x002100600BDFFC01UL,
+ /* 0x01d0, */ 0x002100600BDFFC01UL,
+ /* 0x01d8, */ 0x002100600BDFFC01UL,
+ /* 0x01e0, */ 0x0000000000000000UL,
+ /* 0x01e8, */ 0x0000000000000000UL,
+ /* 0x01f0, */ 0x002100100BDF2401UL,
+ /* 0x01f8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x0000000000000000UL,
+ /* 0x0210, */ 0x002100100BDF2401UL,
+ /* 0x0218, */ 0x001100100BDF2401UL,
+ /* 0x0220, */ 0x001100100BDF2401UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x001100100BDF2401UL,
+ /* 0x0238, */ 0x001100100BDF2401UL,
+ /* 0x0240, */ 0x001200100BDF2401UL,
+ /* 0x0248, */ 0x001100100BDF2401UL,
+ /* 0x0250, */ 0x001200100BDF2401UL,
+ /* 0x0258, */ 0x001100100BDF2401UL,
+ /* 0x0260, */ 0x0000000000000000UL,
+ /* 0x0268, */ 0x0000000000000000UL,
+ /* 0x0270, */ 0x0000000000000000UL,
+ /* 0x0278, */ 0x0000000000000000UL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x0000000000000000UL,
+ /* 0x0298, */ 0x0000000000000000UL,
+ /* 0x02a0, */ 0x0000000000000000UL,
+ /* 0x02a8, */ 0x0000000000000000UL,
+ /* 0x02b0, */ 0x0000000000000000UL,
+ /* 0x02b8, */ 0x0000000000000000UL,
+ /* 0x02c0, */ 0x0000000000000000UL,
+ /* 0x02c8, */ 0x0000000000000000UL,
+ /* 0x02d0, */ 0x0000000000000000UL,
+ /* 0x02d8, */ 0x0000000000000000UL,
+ /* 0x02e0, */ 0x0000000000000000UL,
+ /* 0x02e8, */ 0x0000000000000000UL,
+ /* 0x02f0, */ 0x001100600BDFFC01UL,
+ /* 0x02f8, */ 0x001100600BDFFC01UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x001100600BDFFC01UL,
+ /* 0x0310, */ 0x001100600BDFFC01UL,
+ /* 0x0318, */ 0x001200100BD03401UL,
+ /* 0x0320, */ 0x001100600BDFFC01UL,
+ /* 0x0328, */ 0x001100600BDFFC01UL,
+ /* 0x0330, */ 0x001100600BDFFC01UL,
+ /* 0x0338, */ 0x001100600BDFFC01UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+ /* 0x0358, */ 0x0000000000000000UL,
+ /* 0x0360, */ 0x0000000000000000UL,
+ /* 0x0368, */ 0x001200100BD0FC01UL,
+};
+
+#endif /* QOS_INIT_G2H_MSTAT195_H */
diff --git a/drivers/renesas/rzg/qos/G2H/qos_init_g2h_mstat390.h b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_mstat390.h
new file mode 100644
index 0000000..9696a40
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_mstat390.h
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2H_MSTAT390_H
+#define QOS_INIT_G2H_MSTAT390_H
+
+static uint64_t mstat_fix[] = {
+ /* 0x0000, */ 0x0000000000000000UL,
+ /* 0x0008, */ 0x0000000000000000UL,
+ /* 0x0010, */ 0x0000000000000000UL,
+ /* 0x0018, */ 0x0000000000000000UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0000000000000000UL,
+ /* 0x0030, */ 0x001008070000FFFFUL,
+ /* 0x0038, */ 0x0010100D0000FFFFUL,
+ /* 0x0040, */ 0x00141C0E0000FFFFUL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x001408010000FFFFUL,
+ /* 0x0058, */ 0x00141C190000FFFFUL,
+ /* 0x0060, */ 0x00141C190000FFFFUL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x001408010000FFFFUL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x00141C0E0000FFFFUL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00a0, */ 0x000C08040000FFFFUL,
+ /* 0x00a8, */ 0x000C04020000FFFFUL,
+ /* 0x00b0, */ 0x000C04020000FFFFUL,
+ /* 0x00b8, */ 0x0000000000000000UL,
+ /* 0x00c0, */ 0x000C08040000FFFFUL,
+ /* 0x00c8, */ 0x000C04020000FFFFUL,
+ /* 0x00d0, */ 0x000C04020000FFFFUL,
+ /* 0x00d8, */ 0x001044110000FFFFUL,
+ /* 0x00e0, */ 0x001014110000FFFFUL,
+ /* 0x00e8, */ 0x0000000000000000UL,
+ /* 0x00f0, */ 0x001044110000FFFFUL,
+ /* 0x00f8, */ 0x000C1C1A0000FFFFUL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x001014110000FFFFUL,
+ /* 0x0118, */ 0x000C38360000FFFFUL,
+ /* 0x0120, */ 0x000C38360000FFFFUL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x001018150000FFFFUL,
+ /* 0x0140, */ 0x001018150000FFFFUL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x00101C190000FFFFUL,
+ /* 0x0158, */ 0x00101C190000FFFFUL,
+ /* 0x0160, */ 0x001018150000FFFFUL,
+ /* 0x0168, */ 0x001018150000FFFFUL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x00100C0B0000FFFFUL,
+ /* 0x0180, */ 0x00100C0B0000FFFFUL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x001058570000FFFFUL,
+ /* 0x0198, */ 0x001058570000FFFFUL,
+ /* 0x01a0, */ 0x001018150000FFFFUL,
+ /* 0x01a8, */ 0x001018150000FFFFUL,
+ /* 0x01b0, */ 0x0000000000000000UL,
+ /* 0x01b8, */ 0x0000000000000000UL,
+ /* 0x01c0, */ 0x000C04010000FFFFUL,
+ /* 0x01c8, */ 0x000C04010000FFFFUL,
+ /* 0x01d0, */ 0x000C04010000FFFFUL,
+ /* 0x01d8, */ 0x000C04010000FFFFUL,
+ /* 0x01e0, */ 0x0000000000000000UL,
+ /* 0x01e8, */ 0x000C04010000FFFFUL,
+ /* 0x01f0, */ 0x000C04010000FFFFUL,
+ /* 0x01f8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x000C04010000FFFFUL,
+ /* 0x0210, */ 0x000C04010000FFFFUL,
+ /* 0x0218, */ 0x0000000000000000UL,
+ /* 0x0220, */ 0x0000000000000000UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x0000000000000000UL,
+ /* 0x0238, */ 0x0000000000000000UL,
+ /* 0x0240, */ 0x0000000000000000UL,
+ /* 0x0248, */ 0x0000000000000000UL,
+ /* 0x0250, */ 0x0000000000000000UL,
+ /* 0x0258, */ 0x0000000000000000UL,
+ /* 0x0260, */ 0x000C0C030000FFFFUL,
+ /* 0x0268, */ 0x001410010000FFFFUL,
+ /* 0x0270, */ 0x001404010000FFFFUL,
+ /* 0x0278, */ 0x000C08020000FFFFUL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x001410010000FFFFUL,
+ /* 0x0298, */ 0x001404010000FFFFUL,
+ /* 0x02a0, */ 0x000C04010000FFFFUL,
+ /* 0x02a8, */ 0x000C04010000FFFFUL,
+ /* 0x02b0, */ 0x00140C010000FFFFUL,
+ /* 0x02b8, */ 0x000C04010000FFFFUL,
+ /* 0x02c0, */ 0x0000000000000000UL,
+ /* 0x02c8, */ 0x0000000000000000UL,
+ /* 0x02d0, */ 0x000C04010000FFFFUL,
+ /* 0x02d8, */ 0x000C04010000FFFFUL,
+ /* 0x02e0, */ 0x00140C010000FFFFUL,
+ /* 0x02e8, */ 0x000C04010000FFFFUL,
+ /* 0x02f0, */ 0x0000000000000000UL,
+ /* 0x02f8, */ 0x0000000000000000UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0000000000000000UL,
+ /* 0x0310, */ 0x0000000000000000UL,
+ /* 0x0318, */ 0x0000000000000000UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+ /* 0x0358, */ 0x0000000000000000UL,
+ /* 0x0360, */ 0x0000000000000000UL,
+ /* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+ /* 0x0000, */ 0x0012006005EFFC01UL,
+ /* 0x0008, */ 0x0012006005EFFC01UL,
+ /* 0x0010, */ 0x0012006005EFFC01UL,
+ /* 0x0018, */ 0x0012006005EFFC01UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0012001005E0FC01UL,
+ /* 0x0030, */ 0x0000000000000000UL,
+ /* 0x0038, */ 0x0000000000000000UL,
+ /* 0x0040, */ 0x0000000000000000UL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x0000000000000000UL,
+ /* 0x0058, */ 0x0000000000000000UL,
+ /* 0x0060, */ 0x0000000000000000UL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x0000000000000000UL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x0000000000000000UL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00a0, */ 0x0000000000000000UL,
+ /* 0x00a8, */ 0x0000000000000000UL,
+ /* 0x00b0, */ 0x0000000000000000UL,
+ /* 0x00b8, */ 0x0000000000000000UL,
+ /* 0x00c0, */ 0x0000000000000000UL,
+ /* 0x00c8, */ 0x0000000000000000UL,
+ /* 0x00d0, */ 0x0000000000000000UL,
+ /* 0x00d8, */ 0x0000000000000000UL,
+ /* 0x00e0, */ 0x0000000000000000UL,
+ /* 0x00e8, */ 0x0000000000000000UL,
+ /* 0x00f0, */ 0x0000000000000000UL,
+ /* 0x00f8, */ 0x0000000000000000UL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x0000000000000000UL,
+ /* 0x0118, */ 0x0000000000000000UL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x0000000000000000UL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x0000000000000000UL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x0000000000000000UL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x0000000000000000UL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x0000000000000000UL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01a0, */ 0x0000000000000000UL,
+ /* 0x01a8, */ 0x0000000000000000UL,
+ /* 0x01b0, */ 0x0000000000000000UL,
+ /* 0x01b8, */ 0x0000000000000000UL,
+ /* 0x01c0, */ 0x0021006005EFFC01UL,
+ /* 0x01c8, */ 0x0021006005EFFC01UL,
+ /* 0x01d0, */ 0x0021006005EFFC01UL,
+ /* 0x01d8, */ 0x0021006005EFFC01UL,
+ /* 0x01e0, */ 0x0000000000000000UL,
+ /* 0x01e8, */ 0x0000000000000000UL,
+ /* 0x01f0, */ 0x0021001005E79401UL,
+ /* 0x01f8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x0000000000000000UL,
+ /* 0x0210, */ 0x0021001005E79401UL,
+ /* 0x0218, */ 0x0011001005E79401UL,
+ /* 0x0220, */ 0x0011001005E79401UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x0011001005E79401UL,
+ /* 0x0238, */ 0x0011001005E79401UL,
+ /* 0x0240, */ 0x0012001005E79401UL,
+ /* 0x0248, */ 0x0011001005E79401UL,
+ /* 0x0250, */ 0x0012001005E79401UL,
+ /* 0x0258, */ 0x0011001005E79401UL,
+ /* 0x0260, */ 0x0000000000000000UL,
+ /* 0x0268, */ 0x0000000000000000UL,
+ /* 0x0270, */ 0x0000000000000000UL,
+ /* 0x0278, */ 0x0000000000000000UL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x0000000000000000UL,
+ /* 0x0298, */ 0x0000000000000000UL,
+ /* 0x02a0, */ 0x0000000000000000UL,
+ /* 0x02a8, */ 0x0000000000000000UL,
+ /* 0x02b0, */ 0x0000000000000000UL,
+ /* 0x02b8, */ 0x0000000000000000UL,
+ /* 0x02c0, */ 0x0000000000000000UL,
+ /* 0x02c8, */ 0x0000000000000000UL,
+ /* 0x02d0, */ 0x0000000000000000UL,
+ /* 0x02d8, */ 0x0000000000000000UL,
+ /* 0x02e0, */ 0x0000000000000000UL,
+ /* 0x02e8, */ 0x0000000000000000UL,
+ /* 0x02f0, */ 0x0011006005EFFC01UL,
+ /* 0x02f8, */ 0x0011006005EFFC01UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0011006005EFFC01UL,
+ /* 0x0310, */ 0x0011006005EFFC01UL,
+ /* 0x0318, */ 0x0012001005E03401UL,
+ /* 0x0320, */ 0x0011006005EFFC01UL,
+ /* 0x0328, */ 0x0011006005EFFC01UL,
+ /* 0x0330, */ 0x0011006005EFFC01UL,
+ /* 0x0338, */ 0x0011006005EFFC01UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+ /* 0x0358, */ 0x0000000000000000UL,
+ /* 0x0360, */ 0x0000000000000000UL,
+ /* 0x0368, */ 0x0012001005E0FC01UL,
+};
+
+#endif /* QOS_INIT_G2H_MSTAT390_H */
diff --git a/drivers/renesas/rzg/qos/G2H/qos_init_g2h_qoswt195.h b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_qoswt195.h
new file mode 100644
index 0000000..044f246
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_qoswt195.h
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2H_QOSWT195_H
+#define QOS_INIT_G2H_QOSWT195_H
+
+static uint64_t qoswt_fix[] = {
+ /* 0x0000, */ 0x0000000000000000UL,
+ /* 0x0008, */ 0x0000000000000000UL,
+ /* 0x0010, */ 0x0000000000000000UL,
+ /* 0x0018, */ 0x0000000000000000UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0000000000000000UL,
+ /* 0x0030, */ 0x001004040000C010UL,
+ /* 0x0038, */ 0x001008070000C010UL,
+ /* 0x0040, */ 0x001410070000FFF0UL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x0000000000000000UL,
+ /* 0x0058, */ 0x0014100D0000C010UL,
+ /* 0x0060, */ 0x0014100D0000C010UL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x0000000000000000UL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x001410070000FFF0UL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00a0, */ 0x0000000000000000UL,
+ /* 0x00a8, */ 0x0000000000000000UL,
+ /* 0x00b0, */ 0x0000000000000000UL,
+ /* 0x00b8, */ 0x0000000000000000UL,
+ /* 0x00c0, */ 0x0000000000000000UL,
+ /* 0x00c8, */ 0x0000000000000000UL,
+ /* 0x00d0, */ 0x0000000000000000UL,
+ /* 0x00d8, */ 0x0000000000000000UL,
+ /* 0x00e0, */ 0x0000000000000000UL,
+ /* 0x00e8, */ 0x0000000000000000UL,
+ /* 0x00f0, */ 0x0000000000000000UL,
+ /* 0x00f8, */ 0x0000000000000000UL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x0000000000000000UL,
+ /* 0x0118, */ 0x0000000000000000UL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x0000000000000000UL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x0000000000000000UL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x0000000000000000UL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x0000000000000000UL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x0000000000000000UL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01a0, */ 0x0000000000000000UL,
+ /* 0x01a8, */ 0x0000000000000000UL,
+ /* 0x01b0, */ 0x0000000000000000UL,
+ /* 0x01b8, */ 0x0000000000000000UL,
+ /* 0x01c0, */ 0x0000000000000000UL,
+ /* 0x01c8, */ 0x0000000000000000UL,
+ /* 0x01d0, */ 0x0000000000000000UL,
+ /* 0x01d8, */ 0x0000000000000000UL,
+ /* 0x01e0, */ 0x0000000000000000UL,
+ /* 0x01e8, */ 0x0000000000000000UL,
+ /* 0x01f0, */ 0x0000000000000000UL,
+ /* 0x01f8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x0000000000000000UL,
+ /* 0x0210, */ 0x0000000000000000UL,
+ /* 0x0218, */ 0x0000000000000000UL,
+ /* 0x0220, */ 0x0000000000000000UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x0000000000000000UL,
+ /* 0x0238, */ 0x0000000000000000UL,
+ /* 0x0240, */ 0x0000000000000000UL,
+ /* 0x0248, */ 0x0000000000000000UL,
+ /* 0x0250, */ 0x0000000000000000UL,
+ /* 0x0258, */ 0x0000000000000000UL,
+ /* 0x0260, */ 0x000C08020000FFF0UL,
+ /* 0x0268, */ 0x001408010000FFF0UL,
+ /* 0x0270, */ 0x001404010000FFF0UL,
+ /* 0x0278, */ 0x000C04010000FFF0UL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x001408010000FFF0UL,
+ /* 0x0298, */ 0x001404010000FFF0UL,
+ /* 0x02a0, */ 0x0000000000000000UL,
+ /* 0x02a8, */ 0x0000000000000000UL,
+ /* 0x02b0, */ 0x0000000000000000UL,
+ /* 0x02b8, */ 0x0000000000000000UL,
+ /* 0x02c0, */ 0x0000000000000000UL,
+ /* 0x02c8, */ 0x0000000000000000UL,
+ /* 0x02d0, */ 0x0000000000000000UL,
+ /* 0x02d8, */ 0x0000000000000000UL,
+ /* 0x02e0, */ 0x0000000000000000UL,
+ /* 0x02e8, */ 0x0000000000000000UL,
+ /* 0x02f0, */ 0x0000000000000000UL,
+ /* 0x02f8, */ 0x0000000000000000UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0000000000000000UL,
+ /* 0x0310, */ 0x0000000000000000UL,
+ /* 0x0318, */ 0x0000000000000000UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+ /* 0x0358, */ 0x0000000000000000UL,
+ /* 0x0360, */ 0x0000000000000000UL,
+ /* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t qoswt_be[] = {
+ /* 0x0000, */ 0x0000000000000000UL,
+ /* 0x0008, */ 0x0000000000000000UL,
+ /* 0x0010, */ 0x0000000000000000UL,
+ /* 0x0018, */ 0x0000000000000000UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0000000000000000UL,
+ /* 0x0030, */ 0x0000000000000000UL,
+ /* 0x0038, */ 0x0000000000000000UL,
+ /* 0x0040, */ 0x0000000000000000UL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x0000000000000000UL,
+ /* 0x0058, */ 0x0000000000000000UL,
+ /* 0x0060, */ 0x0000000000000000UL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x0000000000000000UL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x0000000000000000UL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00a0, */ 0x0000000000000000UL,
+ /* 0x00a8, */ 0x0000000000000000UL,
+ /* 0x00b0, */ 0x0000000000000000UL,
+ /* 0x00b8, */ 0x0000000000000000UL,
+ /* 0x00c0, */ 0x0000000000000000UL,
+ /* 0x00c8, */ 0x0000000000000000UL,
+ /* 0x00d0, */ 0x0000000000000000UL,
+ /* 0x00d8, */ 0x0000000000000000UL,
+ /* 0x00e0, */ 0x0000000000000000UL,
+ /* 0x00e8, */ 0x0000000000000000UL,
+ /* 0x00f0, */ 0x0000000000000000UL,
+ /* 0x00f8, */ 0x0000000000000000UL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x0000000000000000UL,
+ /* 0x0118, */ 0x0000000000000000UL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x0000000000000000UL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x0000000000000000UL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x0000000000000000UL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x0000000000000000UL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x0000000000000000UL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01a0, */ 0x0000000000000000UL,
+ /* 0x01a8, */ 0x0000000000000000UL,
+ /* 0x01b0, */ 0x0000000000000000UL,
+ /* 0x01b8, */ 0x0000000000000000UL,
+ /* 0x01c0, */ 0x0000000000000000UL,
+ /* 0x01c8, */ 0x0000000000000000UL,
+ /* 0x01d0, */ 0x0000000000000000UL,
+ /* 0x01d8, */ 0x0000000000000000UL,
+ /* 0x01e0, */ 0x0000000000000000UL,
+ /* 0x01e8, */ 0x0000000000000000UL,
+ /* 0x01f0, */ 0x0000000000000000UL,
+ /* 0x01f8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x0000000000000000UL,
+ /* 0x0210, */ 0x0000000000000000UL,
+ /* 0x0218, */ 0x0000000000000000UL,
+ /* 0x0220, */ 0x0000000000000000UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x0000000000000000UL,
+ /* 0x0238, */ 0x0000000000000000UL,
+ /* 0x0240, */ 0x0000000000000000UL,
+ /* 0x0248, */ 0x0000000000000000UL,
+ /* 0x0250, */ 0x0000000000000000UL,
+ /* 0x0258, */ 0x0000000000000000UL,
+ /* 0x0260, */ 0x0000000000000000UL,
+ /* 0x0268, */ 0x0000000000000000UL,
+ /* 0x0270, */ 0x0000000000000000UL,
+ /* 0x0278, */ 0x0000000000000000UL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x0000000000000000UL,
+ /* 0x0298, */ 0x0000000000000000UL,
+ /* 0x02a0, */ 0x0000000000000000UL,
+ /* 0x02a8, */ 0x0000000000000000UL,
+ /* 0x02b0, */ 0x0000000000000000UL,
+ /* 0x02b8, */ 0x0000000000000000UL,
+ /* 0x02c0, */ 0x0000000000000000UL,
+ /* 0x02c8, */ 0x0000000000000000UL,
+ /* 0x02d0, */ 0x0000000000000000UL,
+ /* 0x02d8, */ 0x0000000000000000UL,
+ /* 0x02e0, */ 0x0000000000000000UL,
+ /* 0x02e8, */ 0x0000000000000000UL,
+ /* 0x02f0, */ 0x0000000000000000UL,
+ /* 0x02f8, */ 0x0000000000000000UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0000000000000000UL,
+ /* 0x0310, */ 0x0000000000000000UL,
+ /* 0x0318, */ 0x0000000000000000UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+ /* 0x0358, */ 0x0000000000000000UL,
+ /* 0x0360, */ 0x0000000000000000UL,
+ /* 0x0368, */ 0x0000000000000000UL,
+};
+
+#endif /* QOS_INIT_G2H_QOSWT195_H */
diff --git a/drivers/renesas/rzg/qos/G2H/qos_init_g2h_qoswt390.h b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_qoswt390.h
new file mode 100644
index 0000000..2ae07ab
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_qoswt390.h
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2H_QOSWT390_H
+#define QOS_INIT_G2H_QOSWT390_H
+
+static uint64_t qoswt_fix[] = {
+ /* 0x0000, */ 0x0000000000000000UL,
+ /* 0x0008, */ 0x0000000000000000UL,
+ /* 0x0010, */ 0x0000000000000000UL,
+ /* 0x0018, */ 0x0000000000000000UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0000000000000000UL,
+ /* 0x0030, */ 0x001008070000C010UL,
+ /* 0x0038, */ 0x0010100D0000C010UL,
+ /* 0x0040, */ 0x00141C0E0000FFF0UL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x0000000000000000UL,
+ /* 0x0058, */ 0x00141C190000C010UL,
+ /* 0x0060, */ 0x00141C190000C010UL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x0000000000000000UL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x00141C0E0000FFF0UL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00a0, */ 0x0000000000000000UL,
+ /* 0x00a8, */ 0x0000000000000000UL,
+ /* 0x00b0, */ 0x0000000000000000UL,
+ /* 0x00b8, */ 0x0000000000000000UL,
+ /* 0x00c0, */ 0x0000000000000000UL,
+ /* 0x00c8, */ 0x0000000000000000UL,
+ /* 0x00d0, */ 0x0000000000000000UL,
+ /* 0x00d8, */ 0x0000000000000000UL,
+ /* 0x00e0, */ 0x0000000000000000UL,
+ /* 0x00e8, */ 0x0000000000000000UL,
+ /* 0x00f0, */ 0x0000000000000000UL,
+ /* 0x00f8, */ 0x0000000000000000UL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x0000000000000000UL,
+ /* 0x0118, */ 0x0000000000000000UL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x0000000000000000UL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x0000000000000000UL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x0000000000000000UL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x0000000000000000UL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x0000000000000000UL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01a0, */ 0x0000000000000000UL,
+ /* 0x01a8, */ 0x0000000000000000UL,
+ /* 0x01b0, */ 0x0000000000000000UL,
+ /* 0x01b8, */ 0x0000000000000000UL,
+ /* 0x01c0, */ 0x0000000000000000UL,
+ /* 0x01c8, */ 0x0000000000000000UL,
+ /* 0x01d0, */ 0x0000000000000000UL,
+ /* 0x01d8, */ 0x0000000000000000UL,
+ /* 0x01e0, */ 0x0000000000000000UL,
+ /* 0x01e8, */ 0x0000000000000000UL,
+ /* 0x01f0, */ 0x0000000000000000UL,
+ /* 0x01f8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x0000000000000000UL,
+ /* 0x0210, */ 0x0000000000000000UL,
+ /* 0x0218, */ 0x0000000000000000UL,
+ /* 0x0220, */ 0x0000000000000000UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x0000000000000000UL,
+ /* 0x0238, */ 0x0000000000000000UL,
+ /* 0x0240, */ 0x0000000000000000UL,
+ /* 0x0248, */ 0x0000000000000000UL,
+ /* 0x0250, */ 0x0000000000000000UL,
+ /* 0x0258, */ 0x0000000000000000UL,
+ /* 0x0260, */ 0x000C0C030000FFF0UL,
+ /* 0x0268, */ 0x001410010000FFF0UL,
+ /* 0x0270, */ 0x001404010000FFF0UL,
+ /* 0x0278, */ 0x000C08020000FFF0UL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x001410010000FFF0UL,
+ /* 0x0298, */ 0x001404010000FFF0UL,
+ /* 0x02a0, */ 0x0000000000000000UL,
+ /* 0x02a8, */ 0x0000000000000000UL,
+ /* 0x02b0, */ 0x0000000000000000UL,
+ /* 0x02b8, */ 0x0000000000000000UL,
+ /* 0x02c0, */ 0x0000000000000000UL,
+ /* 0x02c8, */ 0x0000000000000000UL,
+ /* 0x02d0, */ 0x0000000000000000UL,
+ /* 0x02d8, */ 0x0000000000000000UL,
+ /* 0x02e0, */ 0x0000000000000000UL,
+ /* 0x02e8, */ 0x0000000000000000UL,
+ /* 0x02f0, */ 0x0000000000000000UL,
+ /* 0x02f8, */ 0x0000000000000000UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0000000000000000UL,
+ /* 0x0310, */ 0x0000000000000000UL,
+ /* 0x0318, */ 0x0000000000000000UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+ /* 0x0358, */ 0x0000000000000000UL,
+ /* 0x0360, */ 0x0000000000000000UL,
+ /* 0x0368, */ 0x0000000000000000UL,
+};
+
+static uint64_t qoswt_be[] = {
+ /* 0x0000, */ 0x0000000000000000UL,
+ /* 0x0008, */ 0x0000000000000000UL,
+ /* 0x0010, */ 0x0000000000000000UL,
+ /* 0x0018, */ 0x0000000000000000UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0000000000000000UL,
+ /* 0x0030, */ 0x0000000000000000UL,
+ /* 0x0038, */ 0x0000000000000000UL,
+ /* 0x0040, */ 0x0000000000000000UL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x0000000000000000UL,
+ /* 0x0058, */ 0x0000000000000000UL,
+ /* 0x0060, */ 0x0000000000000000UL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x0000000000000000UL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x0000000000000000UL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00a0, */ 0x0000000000000000UL,
+ /* 0x00a8, */ 0x0000000000000000UL,
+ /* 0x00b0, */ 0x0000000000000000UL,
+ /* 0x00b8, */ 0x0000000000000000UL,
+ /* 0x00c0, */ 0x0000000000000000UL,
+ /* 0x00c8, */ 0x0000000000000000UL,
+ /* 0x00d0, */ 0x0000000000000000UL,
+ /* 0x00d8, */ 0x0000000000000000UL,
+ /* 0x00e0, */ 0x0000000000000000UL,
+ /* 0x00e8, */ 0x0000000000000000UL,
+ /* 0x00f0, */ 0x0000000000000000UL,
+ /* 0x00f8, */ 0x0000000000000000UL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x0000000000000000UL,
+ /* 0x0118, */ 0x0000000000000000UL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x0000000000000000UL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x0000000000000000UL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x0000000000000000UL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x0000000000000000UL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x0000000000000000UL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01a0, */ 0x0000000000000000UL,
+ /* 0x01a8, */ 0x0000000000000000UL,
+ /* 0x01b0, */ 0x0000000000000000UL,
+ /* 0x01b8, */ 0x0000000000000000UL,
+ /* 0x01c0, */ 0x0000000000000000UL,
+ /* 0x01c8, */ 0x0000000000000000UL,
+ /* 0x01d0, */ 0x0000000000000000UL,
+ /* 0x01d8, */ 0x0000000000000000UL,
+ /* 0x01e0, */ 0x0000000000000000UL,
+ /* 0x01e8, */ 0x0000000000000000UL,
+ /* 0x01f0, */ 0x0000000000000000UL,
+ /* 0x01f8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x0000000000000000UL,
+ /* 0x0210, */ 0x0000000000000000UL,
+ /* 0x0218, */ 0x0000000000000000UL,
+ /* 0x0220, */ 0x0000000000000000UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x0000000000000000UL,
+ /* 0x0238, */ 0x0000000000000000UL,
+ /* 0x0240, */ 0x0000000000000000UL,
+ /* 0x0248, */ 0x0000000000000000UL,
+ /* 0x0250, */ 0x0000000000000000UL,
+ /* 0x0258, */ 0x0000000000000000UL,
+ /* 0x0260, */ 0x0000000000000000UL,
+ /* 0x0268, */ 0x0000000000000000UL,
+ /* 0x0270, */ 0x0000000000000000UL,
+ /* 0x0278, */ 0x0000000000000000UL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x0000000000000000UL,
+ /* 0x0298, */ 0x0000000000000000UL,
+ /* 0x02a0, */ 0x0000000000000000UL,
+ /* 0x02a8, */ 0x0000000000000000UL,
+ /* 0x02b0, */ 0x0000000000000000UL,
+ /* 0x02b8, */ 0x0000000000000000UL,
+ /* 0x02c0, */ 0x0000000000000000UL,
+ /* 0x02c8, */ 0x0000000000000000UL,
+ /* 0x02d0, */ 0x0000000000000000UL,
+ /* 0x02d8, */ 0x0000000000000000UL,
+ /* 0x02e0, */ 0x0000000000000000UL,
+ /* 0x02e8, */ 0x0000000000000000UL,
+ /* 0x02f0, */ 0x0000000000000000UL,
+ /* 0x02f8, */ 0x0000000000000000UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0000000000000000UL,
+ /* 0x0310, */ 0x0000000000000000UL,
+ /* 0x0318, */ 0x0000000000000000UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+ /* 0x0358, */ 0x0000000000000000UL,
+ /* 0x0360, */ 0x0000000000000000UL,
+ /* 0x0368, */ 0x0000000000000000UL,
+};
+
+#endif /* QOS_INIT_G2H_QOSWT390_H */
diff --git a/drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.c b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.c
new file mode 100644
index 0000000..7f466c8
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include "qos_init_g2h_v30.h"
+#include "../qos_common.h"
+#include "../qos_reg.h"
+
+#define RCAR_QOS_VERSION "rev.0.07"
+
+#define QOSWT_TIME_BANK0 20000000U /* unit:ns */
+#define QOSWT_WTEN_ENABLE 0x1U
+
+#define QOSCTRL_REF_ARS_ARBSTOPCYCLE_G2H (SL_INIT_SSLOTCLK_G2H - 0x5U)
+
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
+#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
+ (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define QOSWT_WTREF_SLOT1_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
+ (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+
+#define QOSWT_WTSET0_REQ_SSLOT0 5U
+#define WT_BASE_SUB_SLOT_NUM0 12U
+#define QOSWT_WTSET0_PERIOD0_G2H ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_G2H) - 1U)
+#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
+
+#define QOSWT_WTSET1_PERIOD1_G2H (QOSWT_WTSET0_PERIOD0_G2H)
+#define QOSWT_WTSET1_SSLOT1 (QOSWT_WTSET0_SSLOT0)
+#define QOSWT_WTSET1_SLOTSLOT1 (QOSWT_WTSET0_SLOTSLOT0)
+
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_g2h_mstat195.h"
+#else
+#include "qos_init_g2h_mstat390.h"
+#endif /* RCAR_REF_INT == RCAR_REF_DEFAULT */
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_g2h_qoswt195.h"
+#else
+#include "qos_init_g2h_qoswt390.h"
+#endif /* RCAR_REF_INT == RCAR_REF_DEFAULT */
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+#endif /* RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT */
+
+static const struct rcar_gen3_dbsc_qos_settings g2h_v30_qos[] = {
+ /* BUFCAM settings */
+ { DBSC_DBCAM0CNF1, 0x00043218U },
+ { DBSC_DBCAM0CNF2, 0x000000F4U },
+ { DBSC_DBCAM0CNF3, 0x00000000U },
+ { DBSC_DBSCHCNT0, 0x000F0037U },
+ { DBSC_DBSCHSZ0, 0x00000001U },
+ { DBSC_DBSCHRW0, 0x22421111U },
+
+ /* DDR3 */
+ { DBSC_SCFCTST2, 0x012F1123U },
+
+ /* QoS Settings */
+ { DBSC_DBSCHQOS00, 0x00000F00U },
+ { DBSC_DBSCHQOS01, 0x00000B00U },
+ { DBSC_DBSCHQOS02, 0x00000000U },
+ { DBSC_DBSCHQOS03, 0x00000000U },
+ { DBSC_DBSCHQOS40, 0x00000300U },
+ { DBSC_DBSCHQOS41, 0x000002F0U },
+ { DBSC_DBSCHQOS42, 0x00000200U },
+ { DBSC_DBSCHQOS43, 0x00000100U },
+ { DBSC_DBSCHQOS90, 0x00000100U },
+ { DBSC_DBSCHQOS91, 0x000000F0U },
+ { DBSC_DBSCHQOS92, 0x000000A0U },
+ { DBSC_DBSCHQOS93, 0x00000040U },
+ { DBSC_DBSCHQOS120, 0x00000040U },
+ { DBSC_DBSCHQOS121, 0x00000030U },
+ { DBSC_DBSCHQOS122, 0x00000020U },
+ { DBSC_DBSCHQOS123, 0x00000010U },
+ { DBSC_DBSCHQOS130, 0x00000100U },
+ { DBSC_DBSCHQOS131, 0x000000F0U },
+ { DBSC_DBSCHQOS132, 0x000000A0U },
+ { DBSC_DBSCHQOS133, 0x00000040U },
+ { DBSC_DBSCHQOS140, 0x000000C0U },
+ { DBSC_DBSCHQOS141, 0x000000B0U },
+ { DBSC_DBSCHQOS142, 0x00000080U },
+ { DBSC_DBSCHQOS143, 0x00000040U },
+ { DBSC_DBSCHQOS150, 0x00000040U },
+ { DBSC_DBSCHQOS151, 0x00000030U },
+ { DBSC_DBSCHQOS152, 0x00000020U },
+ { DBSC_DBSCHQOS153, 0x00000010U },
+};
+
+void qos_init_g2h_v30(void)
+{
+ unsigned int split_area;
+
+ rzg_qos_dbsc_setting(g2h_v30_qos, ARRAY_SIZE(g2h_v30_qos), true);
+
+ /* use 1(2GB) for RCAR_DRAM_LPDDR4_MEMCONF for G2H */
+ split_area = 0x1CU;
+
+ /* DRAM split address mapping */
+#if (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH)
+#if RCAR_LSI == RZ_G2H
+#error "Don't set DRAM Split 4ch(G2H)"
+#else /* RCAR_LSI == RZ_G2H */
+ ERROR("DRAM split 4ch not supported.(G2H)");
+ panic();
+#endif /* RCAR_LSI == RZ_G2H */
+#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH) || \
+ (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_AUTO)
+ NOTICE("BL2: DRAM Split is 2ch(DDR %x)\n", (int)qos_init_ddr_phyvalid);
+
+ mmio_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
+ mmio_write_32(AXI_ADSPLCR1, ADSPLCR0_ADRMODE_DEFAULT |
+ ADSPLCR0_SPLITSEL(0xFFU) | ADSPLCR0_AREA(split_area) |
+ ADSPLCR0_SWP);
+ mmio_write_32(AXI_ADSPLCR2, 0x00001004U);
+ mmio_write_32(AXI_ADSPLCR3, 0x00000000U);
+#else /* RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH */
+ mmio_write_32(AXI_ADSPLCR0, ADSPLCR0_AREA(split_area));
+ NOTICE("BL2: DRAM Split is OFF(DDR %x)\n", (int)qos_init_ddr_phyvalid);
+#endif /* RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH */
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+ NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+ NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
+#else
+ NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ NOTICE("BL2: Periodic Write DQ Training\n");
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ mmio_write_32(QOSCTRL_RAS, 0x00000044U);
+ mmio_write_64(QOSCTRL_DANN, 0x0404020002020201UL);
+ mmio_write_32(QOSCTRL_DANT, 0x0020100AU);
+ mmio_write_32(QOSCTRL_FSS, 0x0000000AU);
+ mmio_write_32(QOSCTRL_INSFC, 0x06330001U);
+ mmio_write_32(QOSCTRL_RACNT0, 0x00010003U);
+
+ /* GPU Boost Mode */
+ mmio_write_32(QOSCTRL_STATGEN0, 0x00000001U);
+
+ mmio_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT |
+ SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK_G2H);
+ mmio_write_32(QOSCTRL_REF_ARS, ((QOSCTRL_REF_ARS_ARBSTOPCYCLE_G2H << 16)));
+
+ uint32_t i;
+
+ for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+ mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]);
+ mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+ mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]);
+ mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]);
+ }
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
+ mmio_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8U, qoswt_fix[i]);
+ mmio_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8U, qoswt_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
+ mmio_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8U, qoswt_be[i]);
+ mmio_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8U, qoswt_be[i]);
+ }
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ /* AXI setting */
+ mmio_write_32(AXI_MMCR, 0x00010008U);
+ mmio_write_32(AXI_TR3CR, 0x00010000U);
+ mmio_write_32(AXI_TR4CR, 0x00010000U);
+
+ /* RT bus Leaf setting */
+ mmio_write_32(RT_ACT0, 0x00000000U);
+ mmio_write_32(RT_ACT1, 0x00000000U);
+
+ /* CCI bus Leaf setting */
+ mmio_write_32(CPU_ACT0, 0x00000003U);
+ mmio_write_32(CPU_ACT1, 0x00000003U);
+ mmio_write_32(CPU_ACT2, 0x00000003U);
+ mmio_write_32(CPU_ACT3, 0x00000003U);
+
+ mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ /* re-write training setting */
+ mmio_write_32(QOSWT_WTREF,
+ ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
+ mmio_write_32(QOSWT_WTSET0,
+ ((QOSWT_WTSET0_PERIOD0_G2H << 16) |
+ (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
+ mmio_write_32(QOSWT_WTSET1,
+ ((QOSWT_WTSET1_PERIOD1_G2H << 16) |
+ (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
+
+ mmio_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ mmio_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+ NOTICE("BL2: QoS is None\n");
+
+ mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.h b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.h
new file mode 100644
index 0000000..acd9627
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2H_V30_H
+#define QOS_INIT_G2H_V30_H
+
+void qos_init_g2h_v30(void);
+
+#endif /* QOS_INIT_G2H_V30_H */
diff --git a/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.c b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.c
new file mode 100644
index 0000000..00b0948
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.c
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include "qos_init_g2n_v10.h"
+
+#include "../qos_common.h"
+#include "../qos_reg.h"
+
+#define RCAR_QOS_VERSION "rev.0.09"
+
+#define REF_ARS_ARBSTOPCYCLE_G2N (((SL_INIT_SSLOTCLK_G2N) - 5U) << 16U)
+
+#define QOSWT_TIME_BANK0 20000000U /* unit:ns */
+
+#define QOSWT_WTEN_ENABLE 0x1U
+
+#define OSWT_WTREF_SLOT0_EN_REQ1_SLOT 3U
+#define OSWT_WTREF_SLOT0_EN_REQ2_SLOT 9U
+#define QOSWT_WTREF_SLOT0_EN ((0x1U << OSWT_WTREF_SLOT0_EN_REQ1_SLOT) | \
+ (0x1U << OSWT_WTREF_SLOT0_EN_REQ2_SLOT))
+#define QOSWT_WTREF_SLOT1_EN QOSWT_WTREF_SLOT0_EN
+
+#define QOSWT_WTSET0_REQ_SSLOT0 5U
+#define WT_BASE_SUB_SLOT_NUM0 12U
+#define QOSWT_WTSET0_PERIOD0_G2N ((QOSWT_TIME_BANK0 / QOSWT_WTSET0_CYCLE_G2N) - 1U)
+#define QOSWT_WTSET0_SSLOT0 (QOSWT_WTSET0_REQ_SSLOT0 - 1U)
+#define QOSWT_WTSET0_SLOTSLOT0 (WT_BASE_SUB_SLOT_NUM0 - 1U)
+
+#define QOSWT_WTSET1_PERIOD1_G2N QOSWT_WTSET0_PERIOD0_G2N
+#define QOSWT_WTSET1_SSLOT1 QOSWT_WTSET0_SSLOT0
+#define QOSWT_WTSET1_SLOTSLOT1 QOSWT_WTSET0_SLOTSLOT0
+
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_g2n_v10_mstat195.h"
+#else
+#include "qos_init_g2n_v10_mstat390.h"
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+#include "qos_init_g2n_v10_qoswt195.h"
+#else
+#include "qos_init_g2n_v10_qoswt390.h"
+#endif
+
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+#endif
+
+static const struct rcar_gen3_dbsc_qos_settings g2n_v10_qos[] = {
+ /* BUFCAM settings */
+ { DBSC_DBCAM0CNF1, 0x00043218U },
+ { DBSC_DBCAM0CNF2, 0x000000F4U },
+ { DBSC_DBSCHCNT0, 0x000F0037U },
+ { DBSC_DBSCHSZ0, 0x00000001U },
+ { DBSC_DBSCHRW0, 0x22421111U },
+
+ /* DDR3 */
+ { DBSC_SCFCTST2, 0x012F1123U },
+
+ /* QoS Settings */
+ { DBSC_DBSCHQOS00, 0x00000F00U },
+ { DBSC_DBSCHQOS01, 0x00000B00U },
+ { DBSC_DBSCHQOS02, 0x00000000U },
+ { DBSC_DBSCHQOS03, 0x00000000U },
+ { DBSC_DBSCHQOS40, 0x00000300U },
+ { DBSC_DBSCHQOS41, 0x000002F0U },
+ { DBSC_DBSCHQOS42, 0x00000200U },
+ { DBSC_DBSCHQOS43, 0x00000100U },
+ { DBSC_DBSCHQOS90, 0x00000100U },
+ { DBSC_DBSCHQOS91, 0x000000F0U },
+ { DBSC_DBSCHQOS92, 0x000000A0U },
+ { DBSC_DBSCHQOS93, 0x00000040U },
+ { DBSC_DBSCHQOS130, 0x00000100U },
+ { DBSC_DBSCHQOS131, 0x000000F0U },
+ { DBSC_DBSCHQOS132, 0x000000A0U },
+ { DBSC_DBSCHQOS133, 0x00000040U },
+ { DBSC_DBSCHQOS140, 0x000000C0U },
+ { DBSC_DBSCHQOS141, 0x000000B0U },
+ { DBSC_DBSCHQOS142, 0x00000080U },
+ { DBSC_DBSCHQOS143, 0x00000040U },
+ { DBSC_DBSCHQOS150, 0x00000040U },
+ { DBSC_DBSCHQOS151, 0x00000030U },
+ { DBSC_DBSCHQOS152, 0x00000020U },
+ { DBSC_DBSCHQOS153, 0x00000010U },
+};
+
+void qos_init_g2n_v10(void)
+{
+ rzg_qos_dbsc_setting(g2n_v10_qos, ARRAY_SIZE(g2n_v10_qos), true);
+
+ /* DRAM Split Address mapping */
+#if RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_4CH
+#if RCAR_LSI == RZ_G2N
+#error "Don't set DRAM Split 4ch(G2N)"
+#else
+ ERROR("DRAM Split 4ch not supported.(G2N)");
+ panic();
+#endif
+#elif (RCAR_DRAM_SPLIT == RCAR_DRAM_SPLIT_2CH)
+#if RCAR_LSI == RZ_G2N
+#error "Don't set DRAM Split 2ch(G2N)"
+#else
+ ERROR("DRAM Split 2ch not supported.(G2N)");
+ panic();
+#endif
+#else
+ NOTICE("BL2: DRAM Split is OFF\n");
+#endif
+
+#if !(RCAR_QOS_TYPE == RCAR_QOS_NONE)
+#if RCAR_QOS_TYPE == RCAR_QOS_TYPE_DEFAULT
+ NOTICE("BL2: QoS is default setting(%s)\n", RCAR_QOS_VERSION);
+#endif
+
+#if RCAR_REF_INT == RCAR_REF_DEFAULT
+ NOTICE("BL2: DRAM refresh interval 1.95 usec\n");
+#else
+ NOTICE("BL2: DRAM refresh interval 3.9 usec\n");
+#endif
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ NOTICE("BL2: Periodic Write DQ Training\n");
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ mmio_write_32(QOSCTRL_RAS, 0x00000028U);
+ mmio_write_64(QOSCTRL_DANN, 0x0402000002020201UL);
+ mmio_write_32(QOSCTRL_DANT, 0x00100804U);
+ mmio_write_32(QOSCTRL_FSS, 0x0000000AU);
+ mmio_write_32(QOSCTRL_INSFC, 0x06330001U);
+ mmio_write_32(QOSCTRL_EARLYR, 0x00000001U);
+ mmio_write_32(QOSCTRL_RACNT0, 0x00010003U);
+
+ mmio_write_32(QOSCTRL_SL_INIT, SL_INIT_REFFSSLOT |
+ SL_INIT_SLOTSSLOT | SL_INIT_SSLOTCLK_G2N);
+ mmio_write_32(QOSCTRL_REF_ARS, REF_ARS_ARBSTOPCYCLE_G2N);
+
+ uint32_t i;
+
+ for (i = 0U; i < ARRAY_SIZE(mstat_fix); i++) {
+ mmio_write_64(QOSBW_FIX_QOS_BANK0 + i * 8U, mstat_fix[i]);
+ mmio_write_64(QOSBW_FIX_QOS_BANK1 + i * 8U, mstat_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(mstat_be); i++) {
+ mmio_write_64(QOSBW_BE_QOS_BANK0 + i * 8U, mstat_be[i]);
+ mmio_write_64(QOSBW_BE_QOS_BANK1 + i * 8U, mstat_be[i]);
+ }
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ for (i = 0U; i < ARRAY_SIZE(qoswt_fix); i++) {
+ mmio_write_64(QOSWT_FIX_WTQOS_BANK0 + i * 8U, qoswt_fix[i]);
+ mmio_write_64(QOSWT_FIX_WTQOS_BANK1 + i * 8U, qoswt_fix[i]);
+ }
+ for (i = 0U; i < ARRAY_SIZE(qoswt_be); i++) {
+ mmio_write_64(QOSWT_BE_WTQOS_BANK0 + i * 8U, qoswt_be[i]);
+ mmio_write_64(QOSWT_BE_WTQOS_BANK1 + i * 8U, qoswt_be[i]);
+ }
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ /* RT bus Leaf setting */
+ mmio_write_32(RT_ACT0, 0x00000000U);
+ mmio_write_32(RT_ACT1, 0x00000000U);
+
+ /* CCI bus Leaf setting */
+ mmio_write_32(CPU_ACT0, 0x00000003U);
+ mmio_write_32(CPU_ACT1, 0x00000003U);
+
+ mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
+
+#if RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE
+ /* re-write training setting */
+ mmio_write_32(QOSWT_WTREF, ((QOSWT_WTREF_SLOT1_EN << 16) | QOSWT_WTREF_SLOT0_EN));
+ mmio_write_32(QOSWT_WTSET0, ((QOSWT_WTSET0_PERIOD0_G2N << 16) |
+ (QOSWT_WTSET0_SSLOT0 << 8) | QOSWT_WTSET0_SLOTSLOT0));
+ mmio_write_32(QOSWT_WTSET1, ((QOSWT_WTSET1_PERIOD1_G2N << 16) |
+ (QOSWT_WTSET1_SSLOT1 << 8) | QOSWT_WTSET1_SLOTSLOT1));
+
+ mmio_write_32(QOSWT_WTEN, QOSWT_WTEN_ENABLE);
+#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
+
+ mmio_write_32(QOSCTRL_STATQC, 0x00000001U);
+#else
+ NOTICE("BL2: QoS is None\n");
+
+ mmio_write_32(QOSCTRL_RAEN, 0x00000001U);
+#endif /* !(RCAR_QOS_TYPE == RCAR_QOS_NONE) */
+}
diff --git a/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.h b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.h
new file mode 100644
index 0000000..c7f02d9
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2N_V10_H
+#define QOS_INIT_G2N_V10_H
+
+void qos_init_g2n_v10(void);
+
+#endif /* QOS_INIT_G2N_V10_H */
diff --git a/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_mstat195.h b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_mstat195.h
new file mode 100644
index 0000000..6e304b0
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_mstat195.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2N_MSTAT195_H
+#define QOS_INIT_G2N_MSTAT195_H
+
+static uint64_t mstat_fix[] = {
+ /* 0x0000, */ 0x0000000000000000UL,
+ /* 0x0008, */ 0x0000000000000000UL,
+ /* 0x0010, */ 0x0000000000000000UL,
+ /* 0x0018, */ 0x0000000000000000UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0000000000000000UL,
+ /* 0x0030, */ 0x001004320000FFFFUL,
+ /* 0x0038, */ 0x001004320000FFFFUL,
+ /* 0x0040, */ 0x00140C5D0000FFFFUL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x001404040000FFFFUL,
+ /* 0x0058, */ 0x00140C940000FFFFUL,
+ /* 0x0060, */ 0x00140C940000FFFFUL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x001404040000FFFFUL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x0014041F0000FFFFUL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00a0, */ 0x000C041D0000FFFFUL,
+ /* 0x00a8, */ 0x000C04090000FFFFUL,
+ /* 0x00b0, */ 0x000C040B0000FFFFUL,
+ /* 0x00b8, */ 0x0000000000000000UL,
+ /* 0x00c0, */ 0x000C041D0000FFFFUL,
+ /* 0x00c8, */ 0x000C04090000FFFFUL,
+ /* 0x00d0, */ 0x000C040B0000FFFFUL,
+ /* 0x00d8, */ 0x0000000000000000UL,
+ /* 0x00e0, */ 0x0000000000000000UL,
+ /* 0x00e8, */ 0x0000000000000000UL,
+ /* 0x00f0, */ 0x0000000000000000UL,
+ /* 0x00f8, */ 0x000C084F0000FFFFUL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x0000000000000000UL,
+ /* 0x0118, */ 0x000C21E60000FFFFUL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x00100CA50000FFFFUL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x001010C90000FFFFUL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x00100CA50000FFFFUL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x001008530000FFFFUL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x00101D9D0000FFFFUL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01a0, */ 0x00100CA50000FFFFUL,
+ /* 0x01a8, */ 0x0000000000000000UL,
+ /* 0x01b0, */ 0x0000000000000000UL,
+ /* 0x01b8, */ 0x0000000000000000UL,
+ /* 0x01c0, */ 0x000C04010000FFFFUL,
+ /* 0x01c8, */ 0x000C04010000FFFFUL,
+ /* 0x01d0, */ 0x0000000000000000UL,
+ /* 0x01d8, */ 0x0000000000000000UL,
+ /* 0x01e0, */ 0x0000000000000000UL,
+ /* 0x01e8, */ 0x0000000000000000UL,
+ /* 0x01f0, */ 0x0000000000000000UL,
+ /* 0x01f8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x0000000000000000UL,
+ /* 0x0210, */ 0x0000000000000000UL,
+ /* 0x0218, */ 0x0000000000000000UL,
+ /* 0x0220, */ 0x0000000000000000UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x0000000000000000UL,
+ /* 0x0238, */ 0x0000000000000000UL,
+ /* 0x0240, */ 0x0000000000000000UL,
+ /* 0x0248, */ 0x0000000000000000UL,
+ /* 0x0250, */ 0x0000000000000000UL,
+ /* 0x0258, */ 0x0000000000000000UL,
+ /* 0x0260, */ 0x0000000000000000UL,
+ /* 0x0268, */ 0x001408020000FFFFUL,
+ /* 0x0270, */ 0x001404010000FFFFUL,
+ /* 0x0278, */ 0x0000000000000000UL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x001408020000FFFFUL,
+ /* 0x0298, */ 0x001404010000FFFFUL,
+ /* 0x02a0, */ 0x000C04050000FFFFUL,
+ /* 0x02a8, */ 0x000C04050000FFFFUL,
+ /* 0x02b0, */ 0x0000000000000000UL,
+ /* 0x02b8, */ 0x0000000000000000UL,
+ /* 0x02c0, */ 0x0000000000000000UL,
+ /* 0x02c8, */ 0x0000000000000000UL,
+ /* 0x02d0, */ 0x000C04050000FFFFUL,
+ /* 0x02d8, */ 0x000C04050000FFFFUL,
+ /* 0x02e0, */ 0x0000000000000000UL,
+ /* 0x02e8, */ 0x0000000000000000UL,
+ /* 0x02f0, */ 0x0000000000000000UL,
+ /* 0x02f8, */ 0x0000000000000000UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0000000000000000UL,
+ /* 0x0310, */ 0x0000000000000000UL,
+ /* 0x0318, */ 0x0000000000000000UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+ /* 0x0358, */ 0x0000000000000000UL,
+ /* 0x0360, */ 0x0000000000000000UL,
+ /* 0x0368, */ 0x0000000000000000UL,
+ /* 0x0370, */ 0x0000000000000000UL,
+ /* 0x0378, */ 0x0000000000000000UL,
+ /* 0x0380, */ 0x000C04050000FFFFUL,
+ /* 0x0388, */ 0x000C04050000FFFFUL,
+ /* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+ /* 0x0000, */ 0x0000000000000000UL,
+ /* 0x0008, */ 0x0000000000000000UL,
+ /* 0x0010, */ 0x0000000000000000UL,
+ /* 0x0018, */ 0x0000000000000000UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x001200100BD03401UL,
+ /* 0x0030, */ 0x0000000000000000UL,
+ /* 0x0038, */ 0x0000000000000000UL,
+ /* 0x0040, */ 0x0000000000000000UL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x0000000000000000UL,
+ /* 0x0058, */ 0x0000000000000000UL,
+ /* 0x0060, */ 0x0000000000000000UL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x0000000000000000UL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x0000000000000000UL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00a0, */ 0x0000000000000000UL,
+ /* 0x00a8, */ 0x0000000000000000UL,
+ /* 0x00b0, */ 0x0000000000000000UL,
+ /* 0x00b8, */ 0x0000000000000000UL,
+ /* 0x00c0, */ 0x0000000000000000UL,
+ /* 0x00c8, */ 0x0000000000000000UL,
+ /* 0x00d0, */ 0x0000000000000000UL,
+ /* 0x00d8, */ 0x0000000000000000UL,
+ /* 0x00e0, */ 0x0000000000000000UL,
+ /* 0x00e8, */ 0x0000000000000000UL,
+ /* 0x00f0, */ 0x0000000000000000UL,
+ /* 0x00f8, */ 0x0000000000000000UL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x0000000000000000UL,
+ /* 0x0118, */ 0x0000000000000000UL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x0000000000000000UL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x0000000000000000UL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x0000000000000000UL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x0000000000000000UL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x0000000000000000UL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01a0, */ 0x0000000000000000UL,
+ /* 0x01a8, */ 0x0000000000000000UL,
+ /* 0x01b0, */ 0x0000000000000000UL,
+ /* 0x01b8, */ 0x0000000000000000UL,
+ /* 0x01c0, */ 0x002106000BDFFC01UL,
+ /* 0x01c8, */ 0x002106000BDFFC01UL,
+ /* 0x01d0, */ 0x0000000000000000UL,
+ /* 0x01d8, */ 0x0000000000000000UL,
+ /* 0x01e0, */ 0x0000000000000000UL,
+ /* 0x01e8, */ 0x0000000000000000UL,
+ /* 0x01f0, */ 0x0000000000000000UL,
+ /* 0x01f8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x0000000000000000UL,
+ /* 0x0210, */ 0x0000000000000000UL,
+ /* 0x0218, */ 0x001101000BDF2401UL,
+ /* 0x0220, */ 0x001101000BDF2401UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x001101000BDF2401UL,
+ /* 0x0238, */ 0x001101000BDF2401UL,
+ /* 0x0240, */ 0x001201000BDF2401UL,
+ /* 0x0248, */ 0x001101000BDF2401UL,
+ /* 0x0250, */ 0x001201000BDF2401UL,
+ /* 0x0258, */ 0x001101000BDF2401UL,
+ /* 0x0260, */ 0x0000000000000000UL,
+ /* 0x0268, */ 0x0000000000000000UL,
+ /* 0x0270, */ 0x0000000000000000UL,
+ /* 0x0278, */ 0x0000000000000000UL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x0000000000000000UL,
+ /* 0x0298, */ 0x0000000000000000UL,
+ /* 0x02a0, */ 0x0000000000000000UL,
+ /* 0x02a8, */ 0x0000000000000000UL,
+ /* 0x02b0, */ 0x0000000000000000UL,
+ /* 0x02b8, */ 0x0000000000000000UL,
+ /* 0x02c0, */ 0x0000000000000000UL,
+ /* 0x02c8, */ 0x0000000000000000UL,
+ /* 0x02d0, */ 0x0000000000000000UL,
+ /* 0x02d8, */ 0x0000000000000000UL,
+ /* 0x02e0, */ 0x0000000000000000UL,
+ /* 0x02e8, */ 0x0000000000000000UL,
+ /* 0x02f0, */ 0x001106000BDFFC01UL,
+ /* 0x02f8, */ 0x001106000BDFFC01UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0000000000000000UL,
+ /* 0x0310, */ 0x0000000000000000UL,
+ /* 0x0318, */ 0x001200100BD03401UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+ /* 0x0358, */ 0x001206000BDFFC01UL,
+ /* 0x0360, */ 0x001206000BDFFC01UL,
+ /* 0x0368, */ 0x001200100BD03401UL,
+ /* 0x0370, */ 0x0000000000000000UL,
+ /* 0x0378, */ 0x0000000000000000UL,
+ /* 0x0380, */ 0x0000000000000000UL,
+ /* 0x0388, */ 0x0000000000000000UL,
+ /* 0x0390, */ 0x001200100BD03401UL,
+};
+#endif /* QOS_INIT_G2N_MSTAT195_H */
diff --git a/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_mstat390.h b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_mstat390.h
new file mode 100644
index 0000000..4632413
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_mstat390.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2N_MSTAT390_H
+#define QOS_INIT_G2N_MSTAT390_H
+
+static uint64_t mstat_fix[] = {
+ /* 0x0000, */ 0x0000000000000000UL,
+ /* 0x0008, */ 0x0000000000000000UL,
+ /* 0x0010, */ 0x0000000000000000UL,
+ /* 0x0018, */ 0x0000000000000000UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0000000000000000UL,
+ /* 0x0030, */ 0x001008630000FFFFUL,
+ /* 0x0038, */ 0x001008630000FFFFUL,
+ /* 0x0040, */ 0x001418BA0000FFFFUL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x001404070000FFFFUL,
+ /* 0x0058, */ 0x001415270000FFFFUL,
+ /* 0x0060, */ 0x001415270000FFFFUL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x001404070000FFFFUL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x0014083E0000FFFFUL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00a0, */ 0x000C08390000FFFFUL,
+ /* 0x00a8, */ 0x000C04110000FFFFUL,
+ /* 0x00b0, */ 0x000C04150000FFFFUL,
+ /* 0x00b8, */ 0x0000000000000000UL,
+ /* 0x00c0, */ 0x000C08390000FFFFUL,
+ /* 0x00c8, */ 0x000C04110000FFFFUL,
+ /* 0x00d0, */ 0x000C04150000FFFFUL,
+ /* 0x00d8, */ 0x0000000000000000UL,
+ /* 0x00e0, */ 0x0000000000000000UL,
+ /* 0x00e8, */ 0x0000000000000000UL,
+ /* 0x00f0, */ 0x001045080000FFFFUL,
+ /* 0x00f8, */ 0x000C0C9E0000FFFFUL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x001015080000FFFFUL,
+ /* 0x0118, */ 0x000C43CB0000FFFFUL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x0010194A0000FFFFUL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x00101D910000FFFFUL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x0010194A0000FFFFUL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x00100CA50000FFFFUL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x001037390000FFFFUL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01a0, */ 0x0010194A0000FFFFUL,
+ /* 0x01a8, */ 0x0000000000000000UL,
+ /* 0x01b0, */ 0x0000000000000000UL,
+ /* 0x01b8, */ 0x0000000000000000UL,
+ /* 0x01c0, */ 0x000C04010000FFFFUL,
+ /* 0x01c8, */ 0x000C04010000FFFFUL,
+ /* 0x01d0, */ 0x0000000000000000UL,
+ /* 0x01d8, */ 0x0000000000000000UL,
+ /* 0x01e0, */ 0x0000000000000000UL,
+ /* 0x01e8, */ 0x000C04020000FFFFUL,
+ /* 0x01f0, */ 0x000C04090000FFFFUL,
+ /* 0x01f8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x000C04090000FFFFUL,
+ /* 0x0210, */ 0x000C04090000FFFFUL,
+ /* 0x0218, */ 0x0000000000000000UL,
+ /* 0x0220, */ 0x0000000000000000UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x0000000000000000UL,
+ /* 0x0238, */ 0x0000000000000000UL,
+ /* 0x0240, */ 0x0000000000000000UL,
+ /* 0x0248, */ 0x0000000000000000UL,
+ /* 0x0250, */ 0x0000000000000000UL,
+ /* 0x0258, */ 0x0000000000000000UL,
+ /* 0x0260, */ 0x000C0C2A0000FFFFUL,
+ /* 0x0268, */ 0x001410040000FFFFUL,
+ /* 0x0270, */ 0x001404020000FFFFUL,
+ /* 0x0278, */ 0x000C08110000FFFFUL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x001410040000FFFFUL,
+ /* 0x0298, */ 0x001404020000FFFFUL,
+ /* 0x02a0, */ 0x000C04090000FFFFUL,
+ /* 0x02a8, */ 0x000C04090000FFFFUL,
+ /* 0x02b0, */ 0x00140C090000FFFFUL,
+ /* 0x02b8, */ 0x000C04020000FFFFUL,
+ /* 0x02c0, */ 0x0000000000000000UL,
+ /* 0x02c8, */ 0x0000000000000000UL,
+ /* 0x02d0, */ 0x000C04090000FFFFUL,
+ /* 0x02d8, */ 0x000C04090000FFFFUL,
+ /* 0x02e0, */ 0x00140C090000FFFFUL,
+ /* 0x02e8, */ 0x000C04020000FFFFUL,
+ /* 0x02f0, */ 0x0000000000000000UL,
+ /* 0x02f8, */ 0x0000000000000000UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0000000000000000UL,
+ /* 0x0310, */ 0x0000000000000000UL,
+ /* 0x0318, */ 0x0000000000000000UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+ /* 0x0358, */ 0x0000000000000000UL,
+ /* 0x0360, */ 0x0000000000000000UL,
+ /* 0x0368, */ 0x0000000000000000UL,
+ /* 0x0370, */ 0x000C04020000FFFFUL,
+ /* 0x0378, */ 0x000C04020000FFFFUL,
+ /* 0x0380, */ 0x000C04090000FFFFUL,
+ /* 0x0388, */ 0x000C04090000FFFFUL,
+ /* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t mstat_be[] = {
+ /* 0x0000, */ 0x0000000000000000UL,
+ /* 0x0008, */ 0x0000000000000000UL,
+ /* 0x0010, */ 0x0000000000000000UL,
+ /* 0x0018, */ 0x0000000000000000UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0012001005E03401UL,
+ /* 0x0030, */ 0x0000000000000000UL,
+ /* 0x0038, */ 0x0000000000000000UL,
+ /* 0x0040, */ 0x0000000000000000UL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x0000000000000000UL,
+ /* 0x0058, */ 0x0000000000000000UL,
+ /* 0x0060, */ 0x0000000000000000UL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x0000000000000000UL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x0000000000000000UL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00a0, */ 0x0000000000000000UL,
+ /* 0x00a8, */ 0x0000000000000000UL,
+ /* 0x00b0, */ 0x0000000000000000UL,
+ /* 0x00b8, */ 0x0000000000000000UL,
+ /* 0x00c0, */ 0x0000000000000000UL,
+ /* 0x00c8, */ 0x0000000000000000UL,
+ /* 0x00d0, */ 0x0000000000000000UL,
+ /* 0x00d8, */ 0x0000000000000000UL,
+ /* 0x00e0, */ 0x0000000000000000UL,
+ /* 0x00e8, */ 0x0000000000000000UL,
+ /* 0x00f0, */ 0x0000000000000000UL,
+ /* 0x00f8, */ 0x0000000000000000UL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x0000000000000000UL,
+ /* 0x0118, */ 0x0000000000000000UL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x0000000000000000UL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x0000000000000000UL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x0000000000000000UL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x0000000000000000UL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x0000000000000000UL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01a0, */ 0x0000000000000000UL,
+ /* 0x01a8, */ 0x0000000000000000UL,
+ /* 0x01b0, */ 0x0000000000000000UL,
+ /* 0x01b8, */ 0x0000000000000000UL,
+ /* 0x01c0, */ 0x0021060005EFFC01UL,
+ /* 0x01c8, */ 0x0021060005EFFC01UL,
+ /* 0x01d0, */ 0x0000000000000000UL,
+ /* 0x01d8, */ 0x0000000000000000UL,
+ /* 0x01e0, */ 0x0000000000000000UL,
+ /* 0x01e8, */ 0x0000000000000000UL,
+ /* 0x01f0, */ 0x0021010005E79401UL,
+ /* 0x01f8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x0000000000000000UL,
+ /* 0x0210, */ 0x0021010005E79401UL,
+ /* 0x0218, */ 0x0011010005E79401UL,
+ /* 0x0220, */ 0x0011010005E79401UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x0011010005E79401UL,
+ /* 0x0238, */ 0x0011010005E79401UL,
+ /* 0x0240, */ 0x0012010005E79401UL,
+ /* 0x0248, */ 0x0011010005E79401UL,
+ /* 0x0250, */ 0x0012010005E79401UL,
+ /* 0x0258, */ 0x0011010005E79401UL,
+ /* 0x0260, */ 0x0000000000000000UL,
+ /* 0x0268, */ 0x0000000000000000UL,
+ /* 0x0270, */ 0x0000000000000000UL,
+ /* 0x0278, */ 0x0000000000000000UL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x0000000000000000UL,
+ /* 0x0298, */ 0x0000000000000000UL,
+ /* 0x02a0, */ 0x0000000000000000UL,
+ /* 0x02a8, */ 0x0000000000000000UL,
+ /* 0x02b0, */ 0x0000000000000000UL,
+ /* 0x02b8, */ 0x0000000000000000UL,
+ /* 0x02c0, */ 0x0000000000000000UL,
+ /* 0x02c8, */ 0x0000000000000000UL,
+ /* 0x02d0, */ 0x0000000000000000UL,
+ /* 0x02d8, */ 0x0000000000000000UL,
+ /* 0x02e0, */ 0x0000000000000000UL,
+ /* 0x02e8, */ 0x0000000000000000UL,
+ /* 0x02f0, */ 0x0011060005EFFC01UL,
+ /* 0x02f8, */ 0x0011060005EFFC01UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0000000000000000UL,
+ /* 0x0310, */ 0x0000000000000000UL,
+ /* 0x0318, */ 0x0012001005E03401UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+ /* 0x0358, */ 0x0012060005EFFC01UL,
+ /* 0x0360, */ 0x0012060005EFFC01UL,
+ /* 0x0368, */ 0x0012001005E03401UL,
+ /* 0x0370, */ 0x0000000000000000UL,
+ /* 0x0378, */ 0x0000000000000000UL,
+ /* 0x0380, */ 0x0000000000000000UL,
+ /* 0x0388, */ 0x0000000000000000UL,
+ /* 0x0390, */ 0x0012001005E03401UL,
+};
+#endif /* QOS_INIT_G2N_MSTAT390_H */
diff --git a/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_qoswt195.h b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_qoswt195.h
new file mode 100644
index 0000000..eea1fce
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_qoswt195.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2N_QOSWT195_H
+#define QOS_INIT_G2N_QOSWT195_H
+
+static uint64_t qoswt_fix[] = {
+ /* 0x0000, */ 0x0000000000000000UL,
+ /* 0x0008, */ 0x0000000000000000UL,
+ /* 0x0010, */ 0x0000000000000000UL,
+ /* 0x0018, */ 0x0000000000000000UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0000000000000000UL,
+ /* 0x0030, */ 0x001004320000C010UL,
+ /* 0x0038, */ 0x001004320000C010UL,
+ /* 0x0040, */ 0x00140C5D0000FFF0UL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x0000000000000000UL,
+ /* 0x0058, */ 0x00140C940000C010UL,
+ /* 0x0060, */ 0x00140C940000C010UL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x0000000000000000UL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x0014041F0000FFF0UL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00a0, */ 0x0000000000000000UL,
+ /* 0x00a8, */ 0x0000000000000000UL,
+ /* 0x00b0, */ 0x0000000000000000UL,
+ /* 0x00b8, */ 0x0000000000000000UL,
+ /* 0x00c0, */ 0x0000000000000000UL,
+ /* 0x00c8, */ 0x0000000000000000UL,
+ /* 0x00d0, */ 0x0000000000000000UL,
+ /* 0x00d8, */ 0x0000000000000000UL,
+ /* 0x00e0, */ 0x0000000000000000UL,
+ /* 0x00e8, */ 0x0000000000000000UL,
+ /* 0x00f0, */ 0x0000000000000000UL,
+ /* 0x00f8, */ 0x0000000000000000UL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x0000000000000000UL,
+ /* 0x0118, */ 0x0000000000000000UL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x0000000000000000UL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x0000000000000000UL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x0000000000000000UL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x0000000000000000UL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x0000000000000000UL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01a0, */ 0x0000000000000000UL,
+ /* 0x01a8, */ 0x0000000000000000UL,
+ /* 0x01b0, */ 0x0000000000000000UL,
+ /* 0x01b8, */ 0x0000000000000000UL,
+ /* 0x01c0, */ 0x0000000000000000UL,
+ /* 0x01c8, */ 0x0000000000000000UL,
+ /* 0x01d0, */ 0x0000000000000000UL,
+ /* 0x01d8, */ 0x0000000000000000UL,
+ /* 0x01e0, */ 0x0000000000000000UL,
+ /* 0x01e8, */ 0x0000000000000000UL,
+ /* 0x01f0, */ 0x0000000000000000UL,
+ /* 0x01f8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x0000000000000000UL,
+ /* 0x0210, */ 0x0000000000000000UL,
+ /* 0x0218, */ 0x0000000000000000UL,
+ /* 0x0220, */ 0x0000000000000000UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x0000000000000000UL,
+ /* 0x0238, */ 0x0000000000000000UL,
+ /* 0x0240, */ 0x0000000000000000UL,
+ /* 0x0248, */ 0x0000000000000000UL,
+ /* 0x0250, */ 0x0000000000000000UL,
+ /* 0x0258, */ 0x0000000000000000UL,
+ /* 0x0260, */ 0x000C08150000FFF0UL,
+ /* 0x0268, */ 0x001408020000FFF0UL,
+ /* 0x0270, */ 0x001404010000FFF0UL,
+ /* 0x0278, */ 0x000C04090000FFF0UL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x001408020000FFF0UL,
+ /* 0x0298, */ 0x001404010000FFF0UL,
+ /* 0x02a0, */ 0x0000000000000000UL,
+ /* 0x02a8, */ 0x0000000000000000UL,
+ /* 0x02b0, */ 0x0000000000000000UL,
+ /* 0x02b8, */ 0x0000000000000000UL,
+ /* 0x02c0, */ 0x0000000000000000UL,
+ /* 0x02c8, */ 0x0000000000000000UL,
+ /* 0x02d0, */ 0x0000000000000000UL,
+ /* 0x02d8, */ 0x0000000000000000UL,
+ /* 0x02e0, */ 0x0000000000000000UL,
+ /* 0x02e8, */ 0x0000000000000000UL,
+ /* 0x02f0, */ 0x0000000000000000UL,
+ /* 0x02f8, */ 0x0000000000000000UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0000000000000000UL,
+ /* 0x0310, */ 0x0000000000000000UL,
+ /* 0x0318, */ 0x0000000000000000UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+ /* 0x0358, */ 0x0000000000000000UL,
+ /* 0x0360, */ 0x0000000000000000UL,
+ /* 0x0368, */ 0x0000000000000000UL,
+ /* 0x0370, */ 0x0000000000000000UL,
+ /* 0x0378, */ 0x0000000000000000UL,
+ /* 0x0380, */ 0x0000000000000000UL,
+ /* 0x0388, */ 0x0000000000000000UL,
+ /* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t qoswt_be[] = {
+ /* 0x0000, */ 0x0000000000000000UL,
+ /* 0x0008, */ 0x0000000000000000UL,
+ /* 0x0010, */ 0x0000000000000000UL,
+ /* 0x0018, */ 0x0000000000000000UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0000000000000000UL,
+ /* 0x0030, */ 0x0000000000000000UL,
+ /* 0x0038, */ 0x0000000000000000UL,
+ /* 0x0040, */ 0x0000000000000000UL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x0000000000000000UL,
+ /* 0x0058, */ 0x0000000000000000UL,
+ /* 0x0060, */ 0x0000000000000000UL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x0000000000000000UL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x0000000000000000UL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00a0, */ 0x0000000000000000UL,
+ /* 0x00a8, */ 0x0000000000000000UL,
+ /* 0x00b0, */ 0x0000000000000000UL,
+ /* 0x00b8, */ 0x0000000000000000UL,
+ /* 0x00c0, */ 0x0000000000000000UL,
+ /* 0x00c8, */ 0x0000000000000000UL,
+ /* 0x00d0, */ 0x0000000000000000UL,
+ /* 0x00d8, */ 0x0000000000000000UL,
+ /* 0x00e0, */ 0x0000000000000000UL,
+ /* 0x00e8, */ 0x0000000000000000UL,
+ /* 0x00f0, */ 0x0000000000000000UL,
+ /* 0x00f8, */ 0x0000000000000000UL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x0000000000000000UL,
+ /* 0x0118, */ 0x0000000000000000UL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x0000000000000000UL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x0000000000000000UL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x0000000000000000UL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x0000000000000000UL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x0000000000000000UL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01a0, */ 0x0000000000000000UL,
+ /* 0x01a8, */ 0x0000000000000000UL,
+ /* 0x01b0, */ 0x0000000000000000UL,
+ /* 0x01b8, */ 0x0000000000000000UL,
+ /* 0x01c0, */ 0x0000000000000000UL,
+ /* 0x01c8, */ 0x0000000000000000UL,
+ /* 0x01d0, */ 0x0000000000000000UL,
+ /* 0x01d8, */ 0x0000000000000000UL,
+ /* 0x01e0, */ 0x0000000000000000UL,
+ /* 0x01e8, */ 0x0000000000000000UL,
+ /* 0x01f0, */ 0x0000000000000000UL,
+ /* 0x01f8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x0000000000000000UL,
+ /* 0x0210, */ 0x0000000000000000UL,
+ /* 0x0218, */ 0x0000000000000000UL,
+ /* 0x0220, */ 0x0000000000000000UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x0000000000000000UL,
+ /* 0x0238, */ 0x0000000000000000UL,
+ /* 0x0240, */ 0x0000000000000000UL,
+ /* 0x0248, */ 0x0000000000000000UL,
+ /* 0x0250, */ 0x0000000000000000UL,
+ /* 0x0258, */ 0x0000000000000000UL,
+ /* 0x0260, */ 0x0000000000000000UL,
+ /* 0x0268, */ 0x0000000000000000UL,
+ /* 0x0270, */ 0x0000000000000000UL,
+ /* 0x0278, */ 0x0000000000000000UL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x0000000000000000UL,
+ /* 0x0298, */ 0x0000000000000000UL,
+ /* 0x02a0, */ 0x0000000000000000UL,
+ /* 0x02a8, */ 0x0000000000000000UL,
+ /* 0x02b0, */ 0x0000000000000000UL,
+ /* 0x02b8, */ 0x0000000000000000UL,
+ /* 0x02c0, */ 0x0000000000000000UL,
+ /* 0x02c8, */ 0x0000000000000000UL,
+ /* 0x02d0, */ 0x0000000000000000UL,
+ /* 0x02d8, */ 0x0000000000000000UL,
+ /* 0x02e0, */ 0x0000000000000000UL,
+ /* 0x02e8, */ 0x0000000000000000UL,
+ /* 0x02f0, */ 0x0000000000000000UL,
+ /* 0x02f8, */ 0x0000000000000000UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0000000000000000UL,
+ /* 0x0310, */ 0x0000000000000000UL,
+ /* 0x0318, */ 0x0000000000000000UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+ /* 0x0358, */ 0x0000000000000000UL,
+ /* 0x0360, */ 0x0000000000000000UL,
+ /* 0x0368, */ 0x0000000000000000UL,
+ /* 0x0370, */ 0x0000000000000000UL,
+ /* 0x0378, */ 0x0000000000000000UL,
+ /* 0x0380, */ 0x0000000000000000UL,
+ /* 0x0388, */ 0x0000000000000000UL,
+ /* 0x0390, */ 0x0000000000000000UL,
+};
+#endif /* QOS_INIT_G2N_QOSWT195_H */
diff --git a/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_qoswt390.h b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_qoswt390.h
new file mode 100644
index 0000000..7043303
--- /dev/null
+++ b/drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10_qoswt390.h
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QOS_INIT_G2N_QOSWT390_H
+#define QOS_INIT_G2N_QOSWT390_H
+
+static uint64_t qoswt_fix[] = {
+ /* 0x0000, */ 0x0000000000000000UL,
+ /* 0x0008, */ 0x0000000000000000UL,
+ /* 0x0010, */ 0x0000000000000000UL,
+ /* 0x0018, */ 0x0000000000000000UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0000000000000000UL,
+ /* 0x0030, */ 0x001008630000C010UL,
+ /* 0x0038, */ 0x001008630000C010UL,
+ /* 0x0040, */ 0x001418BA0000FFF0UL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x0000000000000000UL,
+ /* 0x0058, */ 0x001415270000C010UL,
+ /* 0x0060, */ 0x001415270000C010UL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x0000000000000000UL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x0014083E0000FFF0UL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00a0, */ 0x0000000000000000UL,
+ /* 0x00a8, */ 0x0000000000000000UL,
+ /* 0x00b0, */ 0x0000000000000000UL,
+ /* 0x00b8, */ 0x0000000000000000UL,
+ /* 0x00c0, */ 0x0000000000000000UL,
+ /* 0x00c8, */ 0x0000000000000000UL,
+ /* 0x00d0, */ 0x0000000000000000UL,
+ /* 0x00d8, */ 0x0000000000000000UL,
+ /* 0x00e0, */ 0x0000000000000000UL,
+ /* 0x00e8, */ 0x0000000000000000UL,
+ /* 0x00f0, */ 0x0000000000000000UL,
+ /* 0x00f8, */ 0x0000000000000000UL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x0000000000000000UL,
+ /* 0x0118, */ 0x0000000000000000UL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x0000000000000000UL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x0000000000000000UL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x0000000000000000UL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x0000000000000000UL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x0000000000000000UL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01a0, */ 0x0000000000000000UL,
+ /* 0x01a8, */ 0x0000000000000000UL,
+ /* 0x01b0, */ 0x0000000000000000UL,
+ /* 0x01b8, */ 0x0000000000000000UL,
+ /* 0x01c0, */ 0x0000000000000000UL,
+ /* 0x01c8, */ 0x0000000000000000UL,
+ /* 0x01d0, */ 0x0000000000000000UL,
+ /* 0x01d8, */ 0x0000000000000000UL,
+ /* 0x01e0, */ 0x0000000000000000UL,
+ /* 0x01e8, */ 0x0000000000000000UL,
+ /* 0x01f0, */ 0x0000000000000000UL,
+ /* 0x01f8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x0000000000000000UL,
+ /* 0x0210, */ 0x0000000000000000UL,
+ /* 0x0218, */ 0x0000000000000000UL,
+ /* 0x0220, */ 0x0000000000000000UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x0000000000000000UL,
+ /* 0x0238, */ 0x0000000000000000UL,
+ /* 0x0240, */ 0x0000000000000000UL,
+ /* 0x0248, */ 0x0000000000000000UL,
+ /* 0x0250, */ 0x0000000000000000UL,
+ /* 0x0258, */ 0x0000000000000000UL,
+ /* 0x0260, */ 0x000C0C2A0000FFF0UL,
+ /* 0x0268, */ 0x001410040000FFF0UL,
+ /* 0x0270, */ 0x001404020000FFF0UL,
+ /* 0x0278, */ 0x000C08110000FFF0UL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x001410040000FFF0UL,
+ /* 0x0298, */ 0x001404020000FFF0UL,
+ /* 0x02a0, */ 0x0000000000000000UL,
+ /* 0x02a8, */ 0x0000000000000000UL,
+ /* 0x02b0, */ 0x0000000000000000UL,
+ /* 0x02b8, */ 0x0000000000000000UL,
+ /* 0x02c0, */ 0x0000000000000000UL,
+ /* 0x02c8, */ 0x0000000000000000UL,
+ /* 0x02d0, */ 0x0000000000000000UL,
+ /* 0x02d8, */ 0x0000000000000000UL,
+ /* 0x02e0, */ 0x0000000000000000UL,
+ /* 0x02e8, */ 0x0000000000000000UL,
+ /* 0x02f0, */ 0x0000000000000000UL,
+ /* 0x02f8, */ 0x0000000000000000UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0000000000000000UL,
+ /* 0x0310, */ 0x0000000000000000UL,
+ /* 0x0318, */ 0x0000000000000000UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+ /* 0x0358, */ 0x0000000000000000UL,
+ /* 0x0360, */ 0x0000000000000000UL,
+ /* 0x0368, */ 0x0000000000000000UL,
+ /* 0x0370, */ 0x0000000000000000UL,
+ /* 0x0378, */ 0x0000000000000000UL,
+ /* 0x0380, */ 0x0000000000000000UL,
+ /* 0x0388, */ 0x0000000000000000UL,
+ /* 0x0390, */ 0x0000000000000000UL,
+};
+
+static uint64_t qoswt_be[] = {
+ /* 0x0000, */ 0x0000000000000000UL,
+ /* 0x0008, */ 0x0000000000000000UL,
+ /* 0x0010, */ 0x0000000000000000UL,
+ /* 0x0018, */ 0x0000000000000000UL,
+ /* 0x0020, */ 0x0000000000000000UL,
+ /* 0x0028, */ 0x0000000000000000UL,
+ /* 0x0030, */ 0x0000000000000000UL,
+ /* 0x0038, */ 0x0000000000000000UL,
+ /* 0x0040, */ 0x0000000000000000UL,
+ /* 0x0048, */ 0x0000000000000000UL,
+ /* 0x0050, */ 0x0000000000000000UL,
+ /* 0x0058, */ 0x0000000000000000UL,
+ /* 0x0060, */ 0x0000000000000000UL,
+ /* 0x0068, */ 0x0000000000000000UL,
+ /* 0x0070, */ 0x0000000000000000UL,
+ /* 0x0078, */ 0x0000000000000000UL,
+ /* 0x0080, */ 0x0000000000000000UL,
+ /* 0x0088, */ 0x0000000000000000UL,
+ /* 0x0090, */ 0x0000000000000000UL,
+ /* 0x0098, */ 0x0000000000000000UL,
+ /* 0x00a0, */ 0x0000000000000000UL,
+ /* 0x00a8, */ 0x0000000000000000UL,
+ /* 0x00b0, */ 0x0000000000000000UL,
+ /* 0x00b8, */ 0x0000000000000000UL,
+ /* 0x00c0, */ 0x0000000000000000UL,
+ /* 0x00c8, */ 0x0000000000000000UL,
+ /* 0x00d0, */ 0x0000000000000000UL,
+ /* 0x00d8, */ 0x0000000000000000UL,
+ /* 0x00e0, */ 0x0000000000000000UL,
+ /* 0x00e8, */ 0x0000000000000000UL,
+ /* 0x00f0, */ 0x0000000000000000UL,
+ /* 0x00f8, */ 0x0000000000000000UL,
+ /* 0x0100, */ 0x0000000000000000UL,
+ /* 0x0108, */ 0x0000000000000000UL,
+ /* 0x0110, */ 0x0000000000000000UL,
+ /* 0x0118, */ 0x0000000000000000UL,
+ /* 0x0120, */ 0x0000000000000000UL,
+ /* 0x0128, */ 0x0000000000000000UL,
+ /* 0x0130, */ 0x0000000000000000UL,
+ /* 0x0138, */ 0x0000000000000000UL,
+ /* 0x0140, */ 0x0000000000000000UL,
+ /* 0x0148, */ 0x0000000000000000UL,
+ /* 0x0150, */ 0x0000000000000000UL,
+ /* 0x0158, */ 0x0000000000000000UL,
+ /* 0x0160, */ 0x0000000000000000UL,
+ /* 0x0168, */ 0x0000000000000000UL,
+ /* 0x0170, */ 0x0000000000000000UL,
+ /* 0x0178, */ 0x0000000000000000UL,
+ /* 0x0180, */ 0x0000000000000000UL,
+ /* 0x0188, */ 0x0000000000000000UL,
+ /* 0x0190, */ 0x0000000000000000UL,
+ /* 0x0198, */ 0x0000000000000000UL,
+ /* 0x01a0, */ 0x0000000000000000UL,
+ /* 0x01a8, */ 0x0000000000000000UL,
+ /* 0x01b0, */ 0x0000000000000000UL,
+ /* 0x01b8, */ 0x0000000000000000UL,
+ /* 0x01c0, */ 0x0000000000000000UL,
+ /* 0x01c8, */ 0x0000000000000000UL,
+ /* 0x01d0, */ 0x0000000000000000UL,
+ /* 0x01d8, */ 0x0000000000000000UL,
+ /* 0x01e0, */ 0x0000000000000000UL,
+ /* 0x01e8, */ 0x0000000000000000UL,
+ /* 0x01f0, */ 0x0000000000000000UL,
+ /* 0x01f8, */ 0x0000000000000000UL,
+ /* 0x0200, */ 0x0000000000000000UL,
+ /* 0x0208, */ 0x0000000000000000UL,
+ /* 0x0210, */ 0x0000000000000000UL,
+ /* 0x0218, */ 0x0000000000000000UL,
+ /* 0x0220, */ 0x0000000000000000UL,
+ /* 0x0228, */ 0x0000000000000000UL,
+ /* 0x0230, */ 0x0000000000000000UL,
+ /* 0x0238, */ 0x0000000000000000UL,
+ /* 0x0240, */ 0x0000000000000000UL,
+ /* 0x0248, */ 0x0000000000000000UL,
+ /* 0x0250, */ 0x0000000000000000UL,
+ /* 0x0258, */ 0x0000000000000000UL,
+ /* 0x0260, */ 0x0000000000000000UL,
+ /* 0x0268, */ 0x0000000000000000UL,
+ /* 0x0270, */ 0x0000000000000000UL,
+ /* 0x0278, */ 0x0000000000000000UL,
+ /* 0x0280, */ 0x0000000000000000UL,
+ /* 0x0288, */ 0x0000000000000000UL,
+ /* 0x0290, */ 0x0000000000000000UL,
+ /* 0x0298, */ 0x0000000000000000UL,
+ /* 0x02a0, */ 0x0000000000000000UL,
+ /* 0x02a8, */ 0x0000000000000000UL,
+ /* 0x02b0, */ 0x0000000000000000UL,
+ /* 0x02b8, */ 0x0000000000000000UL,
+ /* 0x02c0, */ 0x0000000000000000UL,
+ /* 0x02c8, */ 0x0000000000000000UL,
+ /* 0x02d0, */ 0x0000000000000000UL,
+ /* 0x02d8, */ 0x0000000000000000UL,
+ /* 0x02e0, */ 0x0000000000000000UL,
+ /* 0x02e8, */ 0x0000000000000000UL,
+ /* 0x02f0, */ 0x0000000000000000UL,
+ /* 0x02f8, */ 0x0000000000000000UL,
+ /* 0x0300, */ 0x0000000000000000UL,
+ /* 0x0308, */ 0x0000000000000000UL,
+ /* 0x0310, */ 0x0000000000000000UL,
+ /* 0x0318, */ 0x0000000000000000UL,
+ /* 0x0320, */ 0x0000000000000000UL,
+ /* 0x0328, */ 0x0000000000000000UL,
+ /* 0x0330, */ 0x0000000000000000UL,
+ /* 0x0338, */ 0x0000000000000000UL,
+ /* 0x0340, */ 0x0000000000000000UL,
+ /* 0x0348, */ 0x0000000000000000UL,
+ /* 0x0350, */ 0x0000000000000000UL,
+ /* 0x0358, */ 0x0000000000000000UL,
+ /* 0x0360, */ 0x0000000000000000UL,
+ /* 0x0368, */ 0x0000000000000000UL,
+ /* 0x0370, */ 0x0000000000000000UL,
+ /* 0x0378, */ 0x0000000000000000UL,
+ /* 0x0380, */ 0x0000000000000000UL,
+ /* 0x0388, */ 0x0000000000000000UL,
+ /* 0x0390, */ 0x0000000000000000UL,
+};
+#endif /* QOS_INIT_G2N_QOSWT390_H */
diff --git a/drivers/renesas/rzg/qos/qos.mk b/drivers/renesas/rzg/qos/qos.mk
index f06c685..f05d126 100644
--- a/drivers/renesas/rzg/qos/qos.mk
+++ b/drivers/renesas/rzg/qos/qos.mk
@@ -1,19 +1,31 @@
#
-# Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+# Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
ifeq (${RCAR_LSI},${RCAR_AUTO})
+ BL2_SOURCES += drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.c
+ BL2_SOURCES += drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.c
BL2_SOURCES += drivers/renesas/rzg/qos/G2M/qos_init_g2m_v10.c
BL2_SOURCES += drivers/renesas/rzg/qos/G2M/qos_init_g2m_v11.c
BL2_SOURCES += drivers/renesas/rzg/qos/G2M/qos_init_g2m_v30.c
+ BL2_SOURCES += drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.c
else ifeq (${RCAR_LSI_CUT_COMPAT},1)
ifeq (${RCAR_LSI},${RZ_G2M})
BL2_SOURCES += drivers/renesas/rzg/qos/G2M/qos_init_g2m_v10.c
BL2_SOURCES += drivers/renesas/rzg/qos/G2M/qos_init_g2m_v11.c
BL2_SOURCES += drivers/renesas/rzg/qos/G2M/qos_init_g2m_v30.c
endif
+ ifeq (${RCAR_LSI},${RZ_G2H})
+ BL2_SOURCES += drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.c
+ endif
+ ifeq (${RCAR_LSI},${RZ_G2N})
+ BL2_SOURCES += drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.c
+ endif
+ ifeq (${RCAR_LSI},${RZ_G2E})
+ BL2_SOURCES += drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.c
+ endif
else
ifeq (${RCAR_LSI},${RZ_G2M})
ifeq (${LSI_CUT},10)
@@ -29,6 +41,20 @@
BL2_SOURCES += drivers/renesas/rzg/qos/G2M/qos_init_g2m_v30.c
endif
endif
+ ifeq (${RCAR_LSI},${RZ_G2H})
+ BL2_SOURCES += drivers/renesas/rzg/qos/G2H/qos_init_g2h_v30.c
+ endif
+ ifeq (${RCAR_LSI},${RZ_G2N})
+ ifeq (${LSI_CUT},10)
+ BL2_SOURCES += drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.c
+ else
+# LSI_CUT 10 or later
+ BL2_SOURCES += drivers/renesas/rzg/qos/G2N/qos_init_g2n_v10.c
+ endif
+ endif
+ ifeq (${RCAR_LSI},${RZ_G2E})
+ BL2_SOURCES += drivers/renesas/rzg/qos/G2E/qos_init_g2e_v10.c
+ endif
endif
BL2_SOURCES += drivers/renesas/rzg/qos/qos_init.c
diff --git a/drivers/renesas/rzg/qos/qos_common.h b/drivers/renesas/rzg/qos/qos_common.h
index 6e0cf0e..535bf4c 100644
--- a/drivers/renesas/rzg/qos/qos_common.h
+++ b/drivers/renesas/rzg/qos/qos_common.h
@@ -37,6 +37,44 @@
((SUB_SLOT_CYCLE_G2M_30 * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
#endif
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2N)
+/* define used for G2N */
+#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
+#define SUB_SLOT_CYCLE_G2N 0x7EU /* 126 */
+#else /* REF 3.9usec */
+#define SUB_SLOT_CYCLE_G2N 0xFCU /* 252 */
+#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
+
+#define SL_INIT_SSLOTCLK_G2N (SUB_SLOT_CYCLE_G2N - 1U)
+#define QOSWT_WTSET0_CYCLE_G2N /* unit:ns */ \
+ ((SUB_SLOT_CYCLE_G2N * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
+#endif /* (RCAR_LSI == RZ_G2N) */
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2H)
+/* define used for G2H */
+#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 1.95usec */
+#define SUB_SLOT_CYCLE_G2H 0x7EU /* 126 */
+#else /* REF 3.9usec */
+#define SUB_SLOT_CYCLE_G2H 0xFCU /* 252 */
+#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
+
+#define SL_INIT_SSLOTCLK_G2H (SUB_SLOT_CYCLE_G2H - 1U)
+#define QOSWT_WTSET0_CYCLE_G2H /* unit:ns */ \
+ ((SUB_SLOT_CYCLE_G2H * BASE_SUB_SLOT_NUM * 1000U) / OPERATING_FREQ)
+#endif
+
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2E)
+/* define used for G2E */
+#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 3.9usec */
+#define SUB_SLOT_CYCLE_G2E 0xAFU /* 175 */
+#else /* REF 7.8usec */
+#define SUB_SLOT_CYCLE_G2E 0x15EU /* 350 */
+#endif /* (RCAR_REF_INT == RCAR_REF_DEFAULT) */
+
+#define OPERATING_FREQ_G2E 266U /* MHz */
+#define SL_INIT_SSLOTCLK_G2E (SUB_SLOT_CYCLE_G2E - 1U)
+#endif
+
#define OPERATING_FREQ 400U /* MHz */
#define BASE_SUB_SLOT_NUM 0x6U
#define SUB_SLOT_CYCLE 0x7EU /* 126 */
diff --git a/drivers/renesas/rzg/qos/qos_init.c b/drivers/renesas/rzg/qos/qos_init.c
index 2d5aece..e527a61 100644
--- a/drivers/renesas/rzg/qos/qos_init.c
+++ b/drivers/renesas/rzg/qos/qos_init.c
@@ -10,23 +10,37 @@
#include <lib/mmio.h>
#if RCAR_LSI == RCAR_AUTO
+#include "G2E/qos_init_g2e_v10.h"
+#include "G2H/qos_init_g2h_v30.h"
#include "G2M/qos_init_g2m_v10.h"
#include "G2M/qos_init_g2m_v11.h"
#include "G2M/qos_init_g2m_v30.h"
+#include "G2N/qos_init_g2n_v10.h"
#endif /* RCAR_LSI == RCAR_AUTO */
#if (RCAR_LSI == RZ_G2M)
#include "G2M/qos_init_g2m_v10.h"
#include "G2M/qos_init_g2m_v11.h"
#include "G2M/qos_init_g2m_v30.h"
#endif /* RCAR_LSI == RZ_G2M */
+#if RCAR_LSI == RZ_G2H
+#include "G2H/qos_init_g2h_v30.h"
+#endif /* RCAR_LSI == RZ_G2H */
+#if RCAR_LSI == RZ_G2N
+#include "G2N/qos_init_g2n_v10.h"
+#endif /* RCAR_LSI == RZ_G2N */
+#if RCAR_LSI == RZ_G2E
+#include "G2E/qos_init_g2e_v10.h"
+#endif /* RCAR_LSI == RZ_G2E */
#include "qos_common.h"
#include "qos_init.h"
#include "qos_reg.h"
#include "rcar_def.h"
+#if (RCAR_LSI != RZ_G2E)
#define DRAM_CH_CNT 0x04U
uint32_t qos_init_ddr_ch;
uint8_t qos_init_ddr_phyvalid;
+#endif /* RCAR_LSI != RZ_G2E */
#define PRR_PRODUCT_ERR(reg) \
{ \
@@ -45,15 +59,17 @@
void rzg_qos_init(void)
{
uint32_t reg;
+#if (RCAR_LSI != RZ_G2E)
uint32_t i;
qos_init_ddr_ch = 0U;
- qos_init_ddr_phyvalid = rzg_get_boardcnf_phyvalid();
+ qos_init_ddr_phyvalid = get_boardcnf_phyvalid();
for (i = 0U; i < DRAM_CH_CNT; i++) {
if ((qos_init_ddr_phyvalid & (1U << i))) {
qos_init_ddr_ch++;
}
}
+#endif /* RCAR_LSI != RZ_G2E */
reg = mmio_read_32(PRR);
#if (RCAR_LSI == RCAR_AUTO) || RCAR_LSI_CUT_COMPAT
@@ -76,6 +92,42 @@
PRR_PRODUCT_ERR(reg);
#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2M) */
break;
+ case PRR_PRODUCT_H3:
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2H)
+ switch (reg & PRR_CUT_MASK) {
+ case PRR_PRODUCT_30:
+ default:
+ qos_init_g2h_v30();
+ break;
+ }
+#else
+ PRR_PRODUCT_ERR(reg);
+#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2H) */
+ break;
+ case PRR_PRODUCT_M3N:
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2N)
+ switch (reg & PRR_CUT_MASK) {
+ case PRR_PRODUCT_10:
+ default:
+ qos_init_g2n_v10();
+ break;
+ }
+#else
+ PRR_PRODUCT_ERR(reg);
+#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2N) */
+ break;
+ case PRR_PRODUCT_E3:
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2E)
+ switch (reg & PRR_CUT_MASK) {
+ case PRR_PRODUCT_10:
+ default:
+ qos_init_g2e_v10();
+ break;
+ }
+#else
+ PRR_PRODUCT_ERR(reg);
+#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2E) */
+ break;
default:
PRR_PRODUCT_ERR(reg);
break;
@@ -111,12 +163,31 @@
}
qos_init_g2m_v30();
#endif /* RCAR_LSI_CUT == RCAR_CUT_10 */
+#elif (RCAR_LSI == RZ_G2H)
+ /* G2H Cut 30 or later */
+ if ((reg & PRR_PRODUCT_MASK) != PRR_PRODUCT_H3) {
+ PRR_PRODUCT_ERR(reg);
+ }
+ qos_init_g2h_v30();
+#elif (RCAR_LSI == RZ_G2N)
+ /* G2N Cut 10 or later */
+ if ((reg & (PRR_PRODUCT_MASK)) != PRR_PRODUCT_M3N) {
+ PRR_PRODUCT_ERR(reg);
+ }
+ qos_init_g2n_v10();
+#elif RCAR_LSI == RZ_G2E
+ /* G2E Cut 10 or later */
+ if ((reg & (PRR_PRODUCT_MASK)) != PRR_PRODUCT_E3) {
+ PRR_PRODUCT_ERR(reg);
+ }
+ qos_init_g2e_v10();
#else /* (RCAR_LSI == RZ_G2M) */
#error "Don't have QoS initialize routine(Unknown chip)."
#endif /* (RCAR_LSI == RZ_G2M) */
#endif /* RCAR_LSI == RCAR_AUTO || RCAR_LSI_CUT_COMPAT */
}
+#if (RCAR_LSI != RZ_G2E)
uint32_t get_refperiod(void)
{
uint32_t refperiod = QOSWT_WTSET0_CYCLE;
@@ -140,6 +211,21 @@
}
break;
#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2M) */
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2H)
+ case PRR_PRODUCT_H3:
+ switch (reg & PRR_CUT_MASK) {
+ case PRR_PRODUCT_30:
+ default:
+ refperiod = REFPERIOD_CYCLE;
+ break;
+ }
+ break;
+#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2H) */
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2N)
+ case PRR_PRODUCT_M3N:
+ refperiod = REFPERIOD_CYCLE;
+ break;
+#endif /* (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RZ_G2N) */
default:
break;
}
@@ -150,9 +236,15 @@
/* G2M Cut 11|13|30 or later */
refperiod = REFPERIOD_CYCLE;
#endif /* RCAR_LSI_CUT == RCAR_CUT_10 */
+#elif RCAR_LSI == RZ_G2N
+ refperiod = REFPERIOD_CYCLE;
+#elif RCAR_LSI == RZ_G2H
+ /* G2H Cut 30 or later */
+ refperiod = REFPERIOD_CYCLE;
#endif /* RCAR_LSI == RCAR_AUTO || RCAR_LSI_CUT_COMPAT */
return refperiod;
}
+#endif /* RCAR_LSI != RZ_G2E */
void rzg_qos_dbsc_setting(const struct rcar_gen3_dbsc_qos_settings *qos,
unsigned int qos_size, bool dbsc_wren)
diff --git a/drivers/renesas/rzg/qos/qos_init.h b/drivers/renesas/rzg/qos/qos_init.h
index 10f60e7..3d62744 100644
--- a/drivers/renesas/rzg/qos/qos_init.h
+++ b/drivers/renesas/rzg/qos/qos_init.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,6 +8,6 @@
#define RZG_QOS_INIT_H
void rzg_qos_init(void);
-uint8_t rzg_get_boardcnf_phyvalid(void);
+uint8_t get_boardcnf_phyvalid(void);
#endif /* RZG_QOS_INIT_H */
diff --git a/drivers/scmi-msg/common.h b/drivers/scmi-msg/common.h
index ef5953b..62f3087 100644
--- a/drivers/scmi-msg/common.h
+++ b/drivers/scmi-msg/common.h
@@ -13,6 +13,7 @@
#include "base.h"
#include "clock.h"
+#include "power_domain.h"
#include "reset_domain.h"
#define SCMI_VERSION 0x20000U
@@ -111,6 +112,13 @@
scmi_msg_handler_t scmi_msg_get_rstd_handler(struct scmi_msg *msg);
/*
+ * scmi_msg_get_pd_handler - Return a handler for a power domain message
+ * @msg - message to process
+ * Return a function handler for the message or NULL
+ */
+scmi_msg_handler_t scmi_msg_get_pd_handler(struct scmi_msg *msg);
+
+/*
* Process Read, process and write response for input SCMI message
*
* @msg: SCMI message context
diff --git a/drivers/scmi-msg/entry.c b/drivers/scmi-msg/entry.c
index ea3efa2..3537fbe 100644
--- a/drivers/scmi-msg/entry.c
+++ b/drivers/scmi-msg/entry.c
@@ -11,6 +11,31 @@
#include "common.h"
+#pragma weak scmi_msg_get_clock_handler
+#pragma weak scmi_msg_get_rstd_handler
+#pragma weak scmi_msg_get_pd_handler
+#pragma weak scmi_msg_get_voltage_handler
+
+scmi_msg_handler_t scmi_msg_get_clock_handler(struct scmi_msg *msg __unused)
+{
+ return NULL;
+}
+
+scmi_msg_handler_t scmi_msg_get_rstd_handler(struct scmi_msg *msg __unused)
+{
+ return NULL;
+}
+
+scmi_msg_handler_t scmi_msg_get_pd_handler(struct scmi_msg *msg __unused)
+{
+ return NULL;
+}
+
+scmi_msg_handler_t scmi_msg_get_voltage_handler(struct scmi_msg *msg __unused)
+{
+ return NULL;
+}
+
void scmi_status_response(struct scmi_msg *msg, int32_t status)
{
assert(msg->out && msg->out_size >= sizeof(int32_t));
@@ -47,6 +72,9 @@
case SCMI_PROTOCOL_ID_RESET_DOMAIN:
handler = scmi_msg_get_rstd_handler(msg);
break;
+ case SCMI_PROTOCOL_ID_POWER_DOMAIN:
+ handler = scmi_msg_get_pd_handler(msg);
+ break;
default:
break;
}
diff --git a/drivers/scmi-msg/power_domain.c b/drivers/scmi-msg/power_domain.c
new file mode 100644
index 0000000..c4e1289
--- /dev/null
+++ b/drivers/scmi-msg/power_domain.c
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2015-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2020, Linaro Limited
+ */
+#include <cdefs.h>
+#include <string.h>
+
+#include <drivers/scmi-msg.h>
+#include <drivers/scmi.h>
+#include <lib/utils_def.h>
+
+#include "common.h"
+
+#pragma weak plat_scmi_pd_count
+#pragma weak plat_scmi_pd_get_name
+#pragma weak plat_scmi_pd_get_state
+#pragma weak plat_scmi_pd_set_state
+#pragma weak plat_scmi_pd_statistics
+#pragma weak plat_scmi_pd_get_attributes
+
+static bool message_id_is_supported(size_t message_id);
+
+size_t plat_scmi_pd_count(unsigned int agent_id __unused)
+{
+ return 0U;
+}
+
+const char *plat_scmi_pd_get_name(unsigned int agent_id __unused,
+ unsigned int pd_id __unused)
+{
+ return NULL;
+}
+
+unsigned int plat_scmi_pd_statistics(unsigned int agent_id __unused,
+ unsigned long *pd_id __unused)
+{
+ return 0U;
+}
+
+unsigned int plat_scmi_pd_get_attributes(unsigned int agent_id __unused,
+ unsigned int pd_id __unused)
+{
+ return 0U;
+}
+
+unsigned int plat_scmi_pd_get_state(unsigned int agent_id __unused,
+ unsigned int pd_id __unused)
+{
+ return 0U;
+}
+
+int32_t plat_scmi_pd_set_state(unsigned int agent_id __unused,
+ unsigned int flags __unused,
+ unsigned int pd_id __unused,
+ unsigned int state __unused)
+{
+ return SCMI_NOT_SUPPORTED;
+}
+
+static void report_version(struct scmi_msg *msg)
+{
+ struct scmi_protocol_version_p2a return_values = {
+ .status = SCMI_SUCCESS,
+ .version = SCMI_PROTOCOL_VERSION_PD,
+ };
+
+ if (msg->in_size != 0) {
+ scmi_status_response(msg, SCMI_PROTOCOL_ERROR);
+ return;
+ }
+
+ scmi_write_response(msg, &return_values, sizeof(return_values));
+}
+
+static void report_attributes(struct scmi_msg *msg)
+{
+ unsigned long addr = 0UL;
+ unsigned int len;
+
+ struct scmi_protocol_attributes_p2a_pd return_values = {
+ .status = SCMI_SUCCESS,
+ };
+
+ if (msg->in_size != 0) {
+ scmi_status_response(msg, SCMI_PROTOCOL_ERROR);
+ return;
+ }
+
+ return_values.attributes = plat_scmi_pd_count(msg->agent_id);
+ len = plat_scmi_pd_statistics(msg->agent_id, &addr);
+ if (len != 0U) {
+ return_values.statistics_addr_low = (unsigned int)addr;
+ return_values.statistics_addr_high = (uint32_t)(addr >> 32);
+ return_values.statistics_len = len;
+ }
+
+ scmi_write_response(msg, &return_values, sizeof(return_values));
+}
+
+static void report_message_attributes(struct scmi_msg *msg)
+{
+ struct scmi_protocol_message_attributes_a2p *in_args = (void *)msg->in;
+ struct scmi_protocol_message_attributes_p2a return_values = {
+ .status = SCMI_SUCCESS,
+ /* For this protocol, attributes shall be zero */
+ .attributes = 0U,
+ };
+
+ if (msg->in_size != sizeof(*in_args)) {
+ scmi_status_response(msg, SCMI_PROTOCOL_ERROR);
+ return;
+ }
+
+ if (!message_id_is_supported(in_args->message_id)) {
+ scmi_status_response(msg, SCMI_NOT_FOUND);
+ return;
+ }
+
+ scmi_write_response(msg, &return_values, sizeof(return_values));
+}
+
+static void scmi_pd_attributes(struct scmi_msg *msg)
+{
+ const struct scmi_pd_attributes_a2p *in_args = (void *)msg->in;
+ struct scmi_pd_attributes_p2a return_values = {
+ .status = SCMI_SUCCESS,
+ };
+ const char *name = NULL;
+ unsigned int pd_id = 0U;
+
+ if (msg->in_size != sizeof(*in_args)) {
+ scmi_status_response(msg, SCMI_PROTOCOL_ERROR);
+ return;
+ }
+
+ pd_id = SPECULATION_SAFE_VALUE(in_args->pd_id);
+
+ if (pd_id >= plat_scmi_pd_count(msg->agent_id)) {
+ scmi_status_response(msg, SCMI_INVALID_PARAMETERS);
+ return;
+ }
+
+ name = plat_scmi_pd_get_name(msg->agent_id, pd_id);
+ if (name == NULL) {
+ scmi_status_response(msg, SCMI_NOT_FOUND);
+ return;
+ }
+
+ COPY_NAME_IDENTIFIER(return_values.pd_name, name);
+
+ return_values.attributes = plat_scmi_pd_get_attributes(msg->agent_id, pd_id);
+
+ scmi_write_response(msg, &return_values, sizeof(return_values));
+}
+
+static void scmi_pd_state_get(struct scmi_msg *msg)
+{
+ const struct scmi_pd_state_get_a2p *in_args = (void *)msg->in;
+ unsigned int state = 0U;
+ struct scmi_pd_state_get_p2a return_values = {
+ .status = SCMI_SUCCESS,
+ };
+ unsigned int pd_id = 0U;
+
+ if (msg->in_size != sizeof(*in_args)) {
+ scmi_status_response(msg, SCMI_PROTOCOL_ERROR);
+ return;
+ }
+
+ pd_id = SPECULATION_SAFE_VALUE(in_args->pd_id);
+
+ if (pd_id >= plat_scmi_pd_count(msg->agent_id)) {
+ scmi_status_response(msg, SCMI_INVALID_PARAMETERS);
+ return;
+ }
+
+ state = plat_scmi_pd_get_state(msg->agent_id, pd_id);
+
+ return_values.power_state = state;
+
+ scmi_write_response(msg, &return_values, sizeof(return_values));
+}
+
+static void scmi_pd_state_set(struct scmi_msg *msg)
+{
+ const struct scmi_pd_state_set_a2p *in_args = (void *)msg->in;
+ unsigned int flags = 0U;
+ int32_t status = 0;
+ unsigned int pd_id = 0U;
+ unsigned int state = 0U;
+
+ if (msg->in_size != sizeof(*in_args)) {
+ scmi_status_response(msg, SCMI_PROTOCOL_ERROR);
+ return;
+ }
+
+ pd_id = SPECULATION_SAFE_VALUE(in_args->pd_id);
+
+ if (pd_id >= plat_scmi_pd_count(msg->agent_id)) {
+ scmi_status_response(msg, SCMI_INVALID_PARAMETERS);
+ return;
+ }
+
+ flags = SPECULATION_SAFE_VALUE(in_args->flags);
+ state = SPECULATION_SAFE_VALUE(in_args->power_state);
+
+ status = plat_scmi_pd_set_state(msg->agent_id, flags, pd_id, state);
+
+ scmi_status_response(msg, status);
+}
+
+static const scmi_msg_handler_t scmi_pd_handler_table[] = {
+ [SCMI_PROTOCOL_VERSION] = report_version,
+ [SCMI_PROTOCOL_ATTRIBUTES] = report_attributes,
+ [SCMI_PROTOCOL_MESSAGE_ATTRIBUTES] = report_message_attributes,
+ [SCMI_PD_ATTRIBUTES] = scmi_pd_attributes,
+ [SCMI_PD_STATE_SET] = scmi_pd_state_set,
+ [SCMI_PD_STATE_GET] = scmi_pd_state_get,
+};
+
+static bool message_id_is_supported(size_t message_id)
+{
+ return (message_id < ARRAY_SIZE(scmi_pd_handler_table)) &&
+ (scmi_pd_handler_table[message_id] != NULL);
+}
+
+scmi_msg_handler_t scmi_msg_get_pd_handler(struct scmi_msg *msg)
+{
+ const size_t array_size = ARRAY_SIZE(scmi_pd_handler_table);
+ unsigned int message_id = SPECULATION_SAFE_VALUE(msg->message_id);
+
+ if (message_id >= array_size) {
+ VERBOSE("pd handle not found %u", msg->message_id);
+ return NULL;
+ }
+
+ return scmi_pd_handler_table[message_id];
+}
diff --git a/drivers/scmi-msg/power_domain.h b/drivers/scmi-msg/power_domain.h
new file mode 100644
index 0000000..48551fd
--- /dev/null
+++ b/drivers/scmi-msg/power_domain.h
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright 2021 NXP
+ */
+
+#ifndef SCMI_MSG_PD_H
+#define SCMI_MSG_PD_H
+
+#include <stdint.h>
+
+#include <lib/utils_def.h>
+
+#define SCMI_PROTOCOL_VERSION_PD 0x21000U
+
+/*
+ * Identifiers of the SCMI POWER DOMAIN Protocol commands
+ */
+enum scmi_pd_command_id {
+ SCMI_PD_ATTRIBUTES = 0x003,
+ SCMI_PD_STATE_SET = 0x004,
+ SCMI_PD_STATE_GET = 0x005,
+};
+
+/* Protocol attributes */
+struct scmi_pd_attributes_a2p {
+ uint32_t pd_id;
+};
+
+struct scmi_protocol_attributes_p2a_pd {
+ int32_t status;
+ uint32_t attributes;
+ uint32_t statistics_addr_low;
+ uint32_t statistics_addr_high;
+ uint32_t statistics_len;
+};
+
+#define SCMI_PD_NAME_LENGTH_MAX 16U
+
+struct scmi_pd_attributes_p2a {
+ int32_t status;
+ uint32_t attributes;
+ char pd_name[SCMI_PD_NAME_LENGTH_MAX];
+};
+
+/*
+ * Power Domain State Get
+ */
+
+struct scmi_pd_state_get_a2p {
+ uint32_t pd_id;
+};
+
+struct scmi_pd_state_get_p2a {
+ int32_t status;
+ uint32_t power_state;
+};
+
+/*
+ * Power domain State Set
+ */
+
+struct scmi_pd_state_set_a2p {
+ uint32_t flags;
+ uint32_t pd_id;
+ uint32_t power_state;
+};
+
+struct scmi_pd_state_set_p2a {
+ int32_t status;
+};
+
+#endif /* SCMI_MSG_PD_H */
diff --git a/drivers/scmi-msg/smt.c b/drivers/scmi-msg/smt.c
index b08ee06..9b079c7 100644
--- a/drivers/scmi-msg/smt.c
+++ b/drivers/scmi-msg/smt.c
@@ -44,12 +44,12 @@
assert_scmi_message_max_length_fits_in_smt_buffer_slot);
/* Flag set in smt_header::status when SMT does not contain pending message */
-#define SMT_STATUS_FREE BIT(0)
+#define SMT_STATUS_FREE BIT_32(0)
/* Flag set in smt_header::status when SMT reports an error */
-#define SMT_STATUS_ERROR BIT(1)
+#define SMT_STATUS_ERROR BIT_32(1)
/* Flag set in smt_header::flags when SMT uses interrupts */
-#define SMT_FLAG_INTR_ENABLED BIT(1)
+#define SMT_FLAG_INTR_ENABLED BIT_32(1)
/* Bit fields packed in smt_header::message_header */
#define SMT_MSG_ID_MASK GENMASK_32(7, 0)
@@ -133,7 +133,7 @@
sizeof(smt_hdr->message_header);
if (in_payload_size > SCMI_PLAYLOAD_MAX) {
- VERBOSE("SCMI payload too big %u", in_payload_size);
+ VERBOSE("SCMI payload too big %zu", in_payload_size);
goto out;
}
diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c
index 564bd87..6ada96a 100644
--- a/drivers/st/clk/stm32mp1_clk.c
+++ b/drivers/st/clk/stm32mp1_clk.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@@ -1737,7 +1737,7 @@
void *fdt;
if (fdt_get_address(&fdt) == 0) {
- return false;
+ return -FDT_ERR_NOTFOUND;
}
/* Check status field to disable security */
diff --git a/drivers/st/fmc/stm32_fmc2_nand.c b/drivers/st/fmc/stm32_fmc2_nand.c
index a58a243..453069b 100644
--- a/drivers/st/fmc/stm32_fmc2_nand.c
+++ b/drivers/st/fmc/stm32_fmc2_nand.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@@ -200,9 +200,6 @@
if ((twait < NAND_TCS_MIN) && (tset_mem < (NAND_TCS_MIN - twait))) {
tset_mem = NAND_TCS_MIN - twait;
}
- if ((twait < NAND_TALS_MIN) && (tset_mem < (NAND_TALS_MIN - twait))) {
- tset_mem = NAND_TALS_MIN - twait;
- }
if ((twait > thiz) && ((twait - thiz) < NAND_TDS_MIN) &&
(tset_mem < (NAND_TDS_MIN - (twait - thiz)))) {
tset_mem = NAND_TDS_MIN - (twait - thiz);
@@ -244,12 +241,6 @@
if ((twait < NAND_TCS_MIN) && (tset_att < (NAND_TCS_MIN - twait))) {
tset_att = NAND_TCS_MIN - twait;
}
- if ((twait < NAND_TCLS_MIN) && (tset_att < (NAND_TCLS_MIN - twait))) {
- tset_att = NAND_TCLS_MIN - twait;
- }
- if ((twait < NAND_TALS_MIN) && (tset_att < (NAND_TALS_MIN - twait))) {
- tset_att = NAND_TALS_MIN - twait;
- }
if ((thold_mem < NAND_TRHW_MIN) &&
(tset_att < (NAND_TRHW_MIN - thold_mem))) {
tset_att = NAND_TRHW_MIN - thold_mem;
diff --git a/drivers/st/io/io_mmc.c b/drivers/st/io/io_mmc.c
index 0ed7154..2bf88e6 100644
--- a/drivers/st/io/io_mmc.c
+++ b/drivers/st/io/io_mmc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -29,6 +29,7 @@
static io_type_t device_type_mmc(void);
static signed long long seek_offset;
+static size_t (*_read_blocks)(int lba, uintptr_t buf, size_t size);
static const io_dev_connector_t mmc_dev_connector = {
.dev_open = mmc_dev_open
@@ -60,9 +61,15 @@
/* Open a connection to the mmc device */
static int mmc_dev_open(const uintptr_t init_params, io_dev_info_t **dev_info)
{
+ struct io_mmc_dev_spec *device_spec =
+ (struct io_mmc_dev_spec *)init_params;
+
assert(dev_info != NULL);
*dev_info = (io_dev_info_t *)&mmc_dev_info;
+ _read_blocks = !device_spec->use_boot_part ?
+ mmc_read_blocks : mmc_boot_part_read_blocks;
+
return 0;
}
@@ -100,8 +107,8 @@
uint8_t retries;
for (retries = 0U; retries < 3U; retries++) {
- *length_read = mmc_read_blocks(seek_offset / MMC_BLOCK_SIZE,
- buffer, length);
+ *length_read = _read_blocks(seek_offset / MMC_BLOCK_SIZE,
+ buffer, length);
if (*length_read == length) {
return 0;
diff --git a/drivers/st/io/io_stm32image.c b/drivers/st/io/io_stm32image.c
index 3e377cd..9fa0c50 100644
--- a/drivers/st/io/io_stm32image.c
+++ b/drivers/st/io/io_stm32image.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -246,10 +246,11 @@
static int stm32image_partition_read(io_entity_t *entity, uintptr_t buffer,
size_t length, size_t *length_read)
{
- int result;
+ int result = -EINVAL;
uint8_t *local_buffer;
boot_api_image_header_t *header =
(boot_api_image_header_t *)first_lba_buffer;
+ size_t hdr_sz = sizeof(boot_api_image_header_t);
assert(entity != NULL);
assert(buffer != 0U);
@@ -286,16 +287,13 @@
}
/* Part of image already loaded with the header */
- memcpy(local_buffer, (uint8_t *)first_lba_buffer +
- sizeof(boot_api_image_header_t),
- MAX_LBA_SIZE - sizeof(boot_api_image_header_t));
- local_buffer += MAX_LBA_SIZE - sizeof(boot_api_image_header_t);
+ memcpy(local_buffer, (uint8_t *)first_lba_buffer + hdr_sz,
+ MAX_LBA_SIZE - hdr_sz);
+ local_buffer += MAX_LBA_SIZE - hdr_sz;
offset = MAX_LBA_SIZE;
/* New image length to be read */
- local_length = round_up(length -
- ((MAX_LBA_SIZE) -
- sizeof(boot_api_image_header_t)),
+ local_length = round_up(length - ((MAX_LBA_SIZE) - hdr_sz),
stm32image_dev.lba_size);
if ((header->load_address != 0U) &&
@@ -326,7 +324,7 @@
local_length, length_read);
/* Adding part of size already read from header */
- *length_read += MAX_LBA_SIZE - sizeof(boot_api_image_header_t);
+ *length_read += MAX_LBA_SIZE - hdr_sz;
if (result != 0) {
ERROR("%s: io_read (%i)\n", __func__, result);
@@ -348,6 +346,9 @@
return result;
}
+ inv_dcache_range(round_up((uintptr_t)(local_buffer + length - hdr_sz),
+ CACHE_WRITEBACK_GRANULE), *length_read - length + hdr_sz);
+
io_close(backend_handle);
}
diff --git a/drivers/st/pmic/stm32mp_pmic.c b/drivers/st/pmic/stm32mp_pmic.c
index b2bb482..be410a1 100644
--- a/drivers/st/pmic/stm32mp_pmic.c
+++ b/drivers/st/pmic/stm32mp_pmic.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -121,6 +121,9 @@
}
regulators_node = fdt_subnode_offset(fdt, pmic_node, "regulators");
+ if (regulators_node < 0) {
+ return -ENOENT;
+ }
fdt_for_each_subnode(regulator_node, fdt, regulators_node) {
const fdt32_t *cuint;
@@ -204,6 +207,7 @@
i2c->i2c_base_addr = i2c_info.base;
i2c->dt_status = i2c_info.status;
i2c->clock = i2c_info.clock;
+ i2c->i2c_state = I2C_STATE_RESET;
i2c_init.own_address1 = pmic_i2c_addr;
i2c_init.addressing_mode = I2C_ADDRESSINGMODE_7BIT;
i2c_init.dual_address_mode = I2C_DUALADDRESS_DISABLE;
diff --git a/fdts/arm_fpga.dts b/fdts/arm_fpga.dts
index 6a966fd..b7b4f0e 100644
--- a/fdts/arm_fpga.dts
+++ b/fdts/arm_fpga.dts
@@ -28,7 +28,7 @@
bootargs = "console=ttyAMA0,38400n8 earlycon";
/* Allow to upload a generous 100MB initrd payload. */
linux,initrd-start = <0x0 0x84000000>;
- linux,initrd-end = <0x0 0x85400000>;
+ linux,initrd-end = <0x0 0x8a400000>;
};
/* /cpus node will be added by BL31 at runtime. */
diff --git a/fdts/fvp-base-gicv2-psci-aarch32.dts b/fdts/fvp-base-gicv2-psci-aarch32.dts
index 591ec58..3a921f4 100644
--- a/fdts/fvp-base-gicv2-psci-aarch32.dts
+++ b/fdts/fvp-base-gicv2-psci-aarch32.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,6 +11,7 @@
#define AFF
#define REG_32
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "fvp-defs.dtsi"
/memreserve/ 0x80000000 0x00010000;
@@ -100,10 +101,14 @@
timer {
compatible = "arm,armv8-timer";
- interrupts = <1 13 0xff01>,
- <1 14 0xff01>,
- <1 11 0xff01>,
- <1 10 0xff01>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <100000000>;
};
diff --git a/fdts/fvp-base-gicv2-psci.dts b/fdts/fvp-base-gicv2-psci.dts
index 4b3942e..e99719e 100644
--- a/fdts/fvp-base-gicv2-psci.dts
+++ b/fdts/fvp-base-gicv2-psci.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,6 +10,7 @@
#define AFF
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "fvp-defs.dtsi"
/memreserve/ 0x80000000 0x00010000;
@@ -99,10 +100,14 @@
timer {
compatible = "arm,armv8-timer";
- interrupts = <1 13 0xff01>,
- <1 14 0xff01>,
- <1 11 0xff01>,
- <1 10 0xff01>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <100000000>;
};
diff --git a/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi b/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi
index 1a1bd12..85988e9 100644
--- a/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi
+++ b/fdts/fvp-base-gicv3-psci-aarch32-common.dtsi
@@ -1,9 +1,11 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
/memreserve/ 0x80000000 0x00010000;
/ {
@@ -100,10 +102,14 @@
timer {
compatible = "arm,armv8-timer";
- interrupts = <1 13 0xff01>,
- <1 14 0xff01>,
- <1 11 0xff01>,
- <1 10 0xff01>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <100000000>;
};
diff --git a/fdts/fvp-base-gicv3-psci-common.dtsi b/fdts/fvp-base-gicv3-psci-common.dtsi
index 192f574..b6753de 100644
--- a/fdts/fvp-base-gicv3-psci-common.dtsi
+++ b/fdts/fvp-base-gicv3-psci-common.dtsi
@@ -1,9 +1,10 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <services/sdei_flags.h>
#define LEVEL 0
@@ -161,10 +162,14 @@
timer {
compatible = "arm,armv8-timer";
- interrupts = <1 13 0xff01>,
- <1 14 0xff01>,
- <1 11 0xff01>,
- <1 10 0xff01>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <100000000>;
};
diff --git a/fdts/fvp-foundation-gicv2-psci.dts b/fdts/fvp-foundation-gicv2-psci.dts
index 95a800e..5a82c46 100644
--- a/fdts/fvp-foundation-gicv2-psci.dts
+++ b/fdts/fvp-foundation-gicv2-psci.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,6 +11,7 @@
#define AFF
#define CLUSTER_COUNT 1
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "fvp-defs.dtsi"
/memreserve/ 0x80000000 0x00010000;
@@ -100,10 +101,14 @@
timer {
compatible = "arm,armv8-timer";
- interrupts = <1 13 0xff01>,
- <1 14 0xff01>,
- <1 11 0xff01>,
- <1 10 0xff01>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <100000000>;
};
diff --git a/fdts/fvp-foundation-gicv3-psci.dts b/fdts/fvp-foundation-gicv3-psci.dts
index c295dc1..e1249d4 100644
--- a/fdts/fvp-foundation-gicv3-psci.dts
+++ b/fdts/fvp-foundation-gicv3-psci.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,6 +11,7 @@
#define AFF
#define CLUSTER_COUNT 1
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "fvp-defs.dtsi"
/memreserve/ 0x80000000 0x00010000;
@@ -109,10 +110,14 @@
timer {
compatible = "arm,armv8-timer";
- interrupts = <1 13 0xff01>,
- <1 14 0xff01>,
- <1 11 0xff01>,
- <1 10 0xff01>;
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <100000000>;
};
diff --git a/fdts/juno-ethosn.dtsi b/fdts/juno-ethosn.dtsi
new file mode 100644
index 0000000..87ab378
--- /dev/null
+++ b/fdts/juno-ethosn.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ ethosn: ethosn@6f300000 {
+ compatible = "ethosn";
+ reg = <0 0x6f300000 0 0x00100000>;
+ status = "okay";
+
+ /*
+ * Single-core NPU. For multi-core NPU, additional core nodes
+ * and reg values must be added.
+ */
+ core0 {
+ compatible = "ethosn-core";
+ status = "okay";
+ };
+ };
+};
diff --git a/fdts/juno.dts b/fdts/juno.dts
new file mode 100644
index 0000000..56fe167
--- /dev/null
+++ b/fdts/juno.dts
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/ {
+
+};
+
+#if ARM_ETHOSN_NPU_DRIVER
+ #include "juno-ethosn.dtsi"
+#endif
diff --git a/fdts/morello-fvp.dts b/fdts/morello-fvp.dts
index dda73f1..55c87bf 100644
--- a/fdts/morello-fvp.dts
+++ b/fdts/morello-fvp.dts
@@ -27,33 +27,52 @@
cpus {
#address-cells = <2>;
#size-cells = <0>;
- cpu0@0 {
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+ core1 {
+ cpu = <&CPU1>;
+ };
+ };
+ cluster1 {
+ core0 {
+ cpu = <&CPU2>;
+ };
+ core1 {
+ cpu = <&CPU3>;
+ };
+ };
+ };
+ CPU0: cpu0@0 {
compatible = "arm,armv8";
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
};
- cpu1@100 {
+ CPU1: cpu1@100 {
compatible = "arm,armv8";
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
};
- cpu2@10000 {
+ CPU2: cpu2@10000 {
compatible = "arm,armv8";
reg = <0x0 0x10000>;
device_type = "cpu";
enable-method = "psci";
- clocks = <&scmi_dvfs 0>;
+ clocks = <&scmi_dvfs 1>;
};
- cpu3@10100 {
+ CPU3: cpu3@10100 {
compatible = "arm,armv8";
reg = <0x0 0x10100>;
device_type = "cpu";
enable-method = "psci";
- clocks = <&scmi_dvfs 0>;
+ clocks = <&scmi_dvfs 1>;
};
};
@@ -92,6 +111,12 @@
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
};
+ virtio_p9@1c1a0000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0x1c1a0000 0x0 0x200>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
ethernet@1d100000 {
compatible = "smsc,lan91c111";
reg = <0x0 0x1d100000 0x0 0x10000>;
diff --git a/fdts/stm32mp15-pinctrl.dtsi b/fdts/stm32mp15-pinctrl.dtsi
index d3d1744..058cde2 100644
--- a/fdts/stm32mp15-pinctrl.dtsi
+++ b/fdts/stm32mp15-pinctrl.dtsi
@@ -31,6 +31,16 @@
};
};
+ i2c2_pins_a: i2c2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */
+ <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
+ };
+
qspi_clk_pins_a: qspi-clk-0 {
pins {
pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */
@@ -166,6 +176,15 @@
};
};
+ sdmmc2_d47_pins_d: sdmmc2-d47-3 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
+ };
+ };
+
uart4_pins_a: uart4-0 {
pins1 {
pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
diff --git a/fdts/stm32mp151.dtsi b/fdts/stm32mp151.dtsi
index 8f175a6..c350c66 100644
--- a/fdts/stm32mp151.dtsi
+++ b/fdts/stm32mp151.dtsi
@@ -121,6 +121,21 @@
status = "disabled";
};
+ i2c2: i2c@40013000 {
+ compatible = "st,stm32mp15-i2c";
+ reg = <0x40013000 0x400>;
+ interrupt-names = "event", "error";
+ interrupts = <&exti 22 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc I2C2_K>;
+ resets = <&rcc I2C2_R>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ st,syscfg-fmp = <&syscfg 0x4 0x2>;
+ wakeup-source;
+ status = "disabled";
+ };
+
uart7: serial@40018000 {
compatible = "st,stm32h7-uart";
reg = <0x40018000 0x400>;
diff --git a/fdts/stm32mp157c-odyssey-som.dtsi b/fdts/stm32mp157c-odyssey-som.dtsi
new file mode 100644
index 0000000..6bed339
--- /dev/null
+++ b/fdts/stm32mp157c-odyssey-som.dtsi
@@ -0,0 +1,325 @@
+/*
+ * Copyright (C) 2019, STMicroelectronics. All Rights Reserved.
+ * Copyright (C) 2021, Grzegorz Szymaszek.
+ *
+ * SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+ */
+
+#include "stm32mp157.dtsi"
+#include "stm32mp15xc.dtsi"
+#include "stm32mp15-pinctrl.dtsi"
+#include "stm32mp15xxac-pinctrl.dtsi"
+#include <dt-bindings/clock/stm32mp1-clksrc.h>
+#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
+
+/ {
+ memory@c0000000 {
+ device_type = "memory";
+ reg = <0xc0000000 0x20000000>;
+ };
+
+ vin: vin {
+ compatible = "regulator-fixed";
+ regulator-name = "vin";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+};
+
+&bsec {
+ board_id: board_id@ec {
+ reg = <0xec 0x4>;
+ st,non-secure-otp;
+ };
+};
+
+&clk_hse {
+ st,digbypass;
+};
+
+&cpu0 {
+ cpu-supply = <&vddcore>;
+};
+
+&cpu1 {
+ cpu-supply = <&vddcore>;
+};
+
+&cryp1 {
+ status = "okay";
+};
+
+&hash1 {
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ clock-frequency = <400000>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+
+ pmic: stpmic@33 {
+ compatible = "st,stpmic1";
+ reg = <0x33>;
+ interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ status = "okay";
+
+ regulators {
+ compatible = "st,stpmic1-regulators";
+ buck1-supply = <&vin>;
+ buck2-supply = <&vin>;
+ buck3-supply = <&vin>;
+ buck4-supply = <&vin>;
+ ldo1-supply = <&v3v3>;
+ ldo2-supply = <&vin>;
+ ldo3-supply = <&vdd_ddr>;
+ ldo4-supply = <&vin>;
+ ldo5-supply = <&vin>;
+ ldo6-supply = <&v3v3>;
+ vref_ddr-supply = <&vin>;
+ boost-supply = <&vin>;
+ pwr_sw1-supply = <&bst_out>;
+ pwr_sw2-supply = <&bst_out>;
+
+ vddcore: buck1 {
+ regulator-name = "vddcore";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd_ddr: buck2 {
+ regulator-name = "vdd_ddr";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ vdd: buck3 {
+ regulator-name = "vdd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ st,mask-reset;
+ regulator-initial-mode = <0>;
+ regulator-over-current-protection;
+ };
+
+ v3v3: buck4 {
+ regulator-name = "v3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ regulator-initial-mode = <0>;
+ };
+
+ v1v8_audio: ldo1 {
+ regulator-name = "v1v8_audio";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ v3v3_hdmi: ldo2 {
+ regulator-name = "v3v3_hdmi";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vtt_ddr: ldo3 {
+ regulator-name = "vtt_ddr";
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <750000>;
+ regulator-always-on;
+ regulator-over-current-protection;
+ };
+
+ vdd_usb: ldo4 {
+ regulator-name = "vdd_usb";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vdda: ldo5 {
+ regulator-name = "vdda";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ regulator-boot-on;
+ };
+
+ v1v2_hdmi: ldo6 {
+ regulator-name = "v1v2_hdmi";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ vref_ddr: vref_ddr {
+ regulator-name = "vref_ddr";
+ regulator-always-on;
+ regulator-over-current-protection;
+ };
+
+ bst_out: boost {
+ regulator-name = "bst_out";
+ };
+
+ vbus_otg: pwr_sw1 {
+ regulator-name = "vbus_otg";
+ };
+
+ vbus_sw: pwr_sw2 {
+ regulator-name = "vbus_sw";
+ regulator-active-discharge = <1>;
+ };
+ };
+
+ pmic_watchdog: watchdog {
+ compatible = "st,stpmic1-wdt";
+ status = "disabled";
+ };
+ };
+};
+
+&iwdg2 {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+&pwr_regulators {
+ vdd-supply = <&vdd>;
+ vdd_3v3_usbfs-supply = <&vdd_usb>;
+};
+
+&rcc {
+ secure-status = "disabled";
+ st,clksrc = <
+ CLK_MPU_PLL1P
+ CLK_AXI_PLL2P
+ CLK_MCU_PLL3P
+ CLK_PLL12_HSE
+ CLK_PLL3_HSE
+ CLK_PLL4_HSE
+ CLK_RTC_LSE
+ CLK_MCO1_DISABLED
+ CLK_MCO2_DISABLED
+ >;
+
+ st,clkdiv = <
+ 1 /*MPU*/
+ 0 /*AXI*/
+ 0 /*MCU*/
+ 1 /*APB1*/
+ 1 /*APB2*/
+ 1 /*APB3*/
+ 1 /*APB4*/
+ 2 /*APB5*/
+ 23 /*RTC*/
+ 0 /*MCO1*/
+ 0 /*MCO2*/
+ >;
+
+ st,pkcs = <
+ CLK_CKPER_HSE
+ CLK_FMC_ACLK
+ CLK_QSPI_ACLK
+ CLK_ETH_PLL4P
+ CLK_SDMMC12_PLL4P
+ CLK_DSI_DSIPLL
+ CLK_STGEN_HSE
+ CLK_USBPHY_HSE
+ CLK_SPI2S1_PLL3Q
+ CLK_SPI2S23_PLL3Q
+ CLK_SPI45_HSI
+ CLK_SPI6_HSI
+ CLK_I2C46_HSI
+ CLK_SDMMC3_PLL4P
+ CLK_USBO_USBPHY
+ CLK_ADC_CKPER
+ CLK_CEC_LSE
+ CLK_I2C12_HSI
+ CLK_I2C35_HSI
+ CLK_UART1_HSI
+ CLK_UART24_HSI
+ CLK_UART35_HSI
+ CLK_UART6_HSI
+ CLK_UART78_HSI
+ CLK_SPDIF_PLL4P
+ CLK_FDCAN_PLL4R
+ CLK_SAI1_PLL3Q
+ CLK_SAI2_PLL3Q
+ CLK_SAI3_PLL3Q
+ CLK_SAI4_PLL3Q
+ CLK_RNG1_LSI
+ CLK_RNG2_LSI
+ CLK_LPTIM1_PCLK1
+ CLK_LPTIM23_PCLK3
+ CLK_LPTIM45_LSE
+ >;
+
+ /* VCO = 1300.0 MHz => P = 650 (CPU) */
+ pll1: st,pll@0 {
+ compatible = "st,stm32mp1-pll";
+ reg = <0>;
+ cfg = <2 80 0 0 0 PQR(1,0,0)>;
+ frac = <0x800>;
+ };
+
+ /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
+ pll2: st,pll@1 {
+ compatible = "st,stm32mp1-pll";
+ reg = <1>;
+ cfg = <2 65 1 0 0 PQR(1,1,1)>;
+ frac = <0x1400>;
+ };
+
+ /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
+ pll3: st,pll@2 {
+ compatible = "st,stm32mp1-pll";
+ reg = <2>;
+ cfg = <1 33 1 16 36 PQR(1,1,1)>;
+ frac = <0x1a04>;
+ };
+
+ /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
+ pll4: st,pll@3 {
+ compatible = "st,stm32mp1-pll";
+ reg = <3>;
+ cfg = <3 98 5 7 7 PQR(1,1,1)>;
+ };
+};
+
+&rng1 {
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sdmmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_d>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ st,neg-edge;
+ bus-width = <8>;
+ vmmc-supply = <&v3v3>;
+ vqmmc-supply = <&vdd>;
+ mmc-ddr-3_3v;
+ status = "okay";
+};
diff --git a/fdts/stm32mp157c-odyssey.dts b/fdts/stm32mp157c-odyssey.dts
new file mode 100644
index 0000000..03800f9
--- /dev/null
+++ b/fdts/stm32mp157c-odyssey.dts
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2019, STMicroelectronics. All Rights Reserved.
+ * Copyright (C) 2021, Grzegorz Szymaszek.
+ *
+ * SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+ */
+
+/dts-v1/;
+
+#include "stm32mp157c-odyssey-som.dtsi"
+
+/ {
+ model = "Seeed Studio Odyssey-STM32MP157C Board";
+ compatible = "seeed,stm32mp157c-odyssey",
+ "seeed,stm32mp157c-odyssey-som", "st,stm32mp157";
+
+ aliases {
+ serial0 = &uart4;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&sdmmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_b4_pins_a>;
+ disable-wp;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&v3v3>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_a>;
+ status = "okay";
+};
diff --git a/fdts/tc.dts b/fdts/tc.dts
new file mode 100644
index 0000000..f66d556
--- /dev/null
+++ b/fdts/tc.dts
@@ -0,0 +1,443 @@
+/*
+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/ {
+ compatible = "arm,tc";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &soc_uart0;
+ };
+
+ chosen {
+ bootargs = "console=ttyAMA0 debug user_debug=31 earlycon=pl011,0x7ff80000 loglevel=9 androidboot.hardware=total_compute androidboot.boot_devices=1c050000.mmci ip=dhcp androidboot.selinux=permissive allow_mismatched_32bit_el0";
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+ core1 {
+ cpu = <&CPU1>;
+ };
+ core2 {
+ cpu = <&CPU2>;
+ };
+ core3 {
+ cpu = <&CPU3>;
+ };
+ core4 {
+ cpu = <&CPU4>;
+ };
+ core5 {
+ cpu = <&CPU5>;
+ };
+ core6 {
+ cpu = <&CPU6>;
+ };
+ core7 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+
+ /*
+ * The timings below are just to demonstrate working cpuidle.
+ * These values may be inaccurate.
+ */
+ idle-states {
+ entry-method = "arm,psci";
+
+ CPU_SLEEP_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x0010000>;
+ local-timer-stop;
+ entry-latency-us = <300>;
+ exit-latency-us = <1200>;
+ min-residency-us = <2000>;
+ };
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x1010000>;
+ local-timer-stop;
+ entry-latency-us = <400>;
+ exit-latency-us = <1200>;
+ min-residency-us = <2500>;
+ };
+ };
+
+ CPU0:cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <406>;
+ };
+
+ CPU1:cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x100>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <406>;
+ };
+
+ CPU2:cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x200>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <406>;
+ };
+
+ CPU3:cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x300>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <406>;
+ };
+
+ CPU4:cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x400>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 1>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <912>;
+ };
+
+ CPU5:cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x500>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 1>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <912>;
+ };
+
+ CPU6:cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x600>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 1>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <912>;
+ };
+
+ CPU7:cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x700>;
+ enable-method = "psci";
+ clocks = <&scmi_dvfs 2>;
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ capacity-dmips-mhz = <1024>;
+ };
+
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x7d000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ optee@0xfce00000 {
+ reg = <0x00000000 0xfce00000 0 0x00200000>;
+ no-map;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
+ sram: sram@6000000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x06000000 0x0 0x8000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x06000000 0x8000>;
+
+ cpu_scp_scmi_mem: scp-shmem@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x80>;
+ };
+ };
+
+ mbox_db_rx: mhu@45010000 {
+ compatible = "arm,mhuv2-rx","arm,primecell";
+ reg = <0x0 0x45010000 0x0 0x1000>;
+ clocks = <&soc_refclk100mhz>;
+ clock-names = "apb_pclk";
+ #mbox-cells = <2>;
+ interrupts = <0 317 4>;
+ interrupt-names = "mhu_rx";
+ mhu-protocol = "doorbell";
+ arm,mhuv2-protocols = <0 1>;
+ };
+
+ mbox_db_tx: mhu@45000000 {
+ compatible = "arm,mhuv2-tx","arm,primecell";
+ reg = <0x0 0x45000000 0x0 0x1000>;
+ clocks = <&soc_refclk100mhz>;
+ clock-names = "apb_pclk";
+ #mbox-cells = <2>;
+ interrupt-names = "mhu_tx";
+ mhu-protocol = "doorbell";
+ arm,mhuv2-protocols = <0 1>;
+ };
+
+ scmi {
+ compatible = "arm,scmi";
+ mbox-names = "tx", "rx";
+ mboxes = <&mbox_db_tx 0 0 &mbox_db_rx 0 0 >;
+ shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_dvfs: protocol@13 {
+ reg = <0x13>;
+ #clock-cells = <1>;
+ };
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+ };
+
+ gic: interrupt-controller@2c010000 {
+ compatible = "arm,gic-600", "arm,gic-v3";
+ #address-cells = <2>;
+ #interrupt-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ interrupt-controller;
+ reg = <0x0 0x30000000 0 0x10000>, /* GICD */
+ <0x0 0x30080000 0 0x200000>; /* GICR */
+ interrupts = <0x1 0x9 0x4>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <0x1 13 0x8>,
+ <0x1 14 0x8>,
+ <0x1 11 0x8>,
+ <0x1 10 0x8>;
+ };
+
+ soc_refclk100mhz: refclk100mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ clock-output-names = "apb_pclk";
+ };
+
+ soc_refclk60mhz: refclk60mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <60000000>;
+ clock-output-names = "iofpga_clk";
+ };
+
+ soc_uartclk: uartclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ clock-output-names = "uartclk";
+ };
+
+ soc_uart0: uart@7ff80000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0x7ff80000 0x0 0x1000>;
+ interrupts = <0x0 116 0x4>;
+ clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "okay";
+ };
+
+ vencoder {
+ compatible = "drm,virtual-encoder";
+
+ port {
+ vencoder_in: endpoint {
+ remote-endpoint = <&dp_pl0_out0>;
+ };
+ };
+
+ display-timings {
+ panel-timing {
+ clock-frequency = <25175000>;
+ hactive = <640>;
+ vactive = <480>;
+ hfront-porch = <16>;
+ hback-porch = <48>;
+ hsync-len = <96>;
+ vfront-porch = <10>;
+ vback-porch = <33>;
+ vsync-len = <2>;
+ };
+ };
+
+ };
+
+ hdlcd: hdlcd@7ff60000 {
+ compatible = "arm,hdlcd";
+ reg = <0x0 0x7ff60000 0x0 0x1000>;
+ interrupts = <0x0 117 0x4>;
+ clocks = <&fake_hdlcd_clk>;
+ clock-names = "pxlclk";
+ status = "disabled";
+
+ port {
+ hdlcd_out: endpoint {
+ remote-endpoint = <&vencoder_in>;
+ };
+ };
+ };
+
+ fake_hdlcd_clk: fake-hdlcd-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25175000>;
+ clock-output-names = "pxlclk";
+ };
+
+ ethernet@18000000 {
+ compatible = "smsc,lan91c111";
+ reg = <0x0 0x18000000 0x0 0x10000>;
+ interrupts = <0 109 4>;
+ };
+
+ kmi@1c060000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x0 0x001c060000 0x0 0x1000>;
+ interrupts = <0 197 4>;
+ clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
+ clock-names = "KMIREFCLK", "apb_pclk";
+ };
+
+ kmi@1c070000 {
+ compatible = "arm,pl050", "arm,primecell";
+ reg = <0x0 0x001c070000 0x0 0x1000>;
+ interrupts = <0 103 4>;
+ clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
+ clock-names = "KMIREFCLK", "apb_pclk";
+ };
+
+ bp_clock24mhz: clock24mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "bp:clock24mhz";
+ };
+
+ virtio_block@1c130000 {
+ compatible = "virtio,mmio";
+ reg = <0x0 0x1c130000 0x0 0x200>;
+ interrupts = <0 204 4>;
+ };
+
+ sysreg: sysreg@1c010000 {
+ compatible = "arm,vexpress-sysreg";
+ reg = <0x0 0x001c010000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ fixed_3v3: v2m-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ mmci@1c050000 {
+ compatible = "arm,pl180", "arm,primecell";
+ reg = <0x0 0x001c050000 0x0 0x1000>;
+ interrupts = <0 107 0x4>,
+ <0 108 0x4>;
+ cd-gpios = <&sysreg 0 0>;
+ wp-gpios = <&sysreg 1 0>;
+ bus-width = <8>;
+ max-frequency = <12000000>;
+ vmmc-supply = <&fixed_3v3>;
+ clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
+ clock-names = "mclk", "apb_pclk";
+ };
+
+ dp0: display@2cc00000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "arm,mali-d71";
+ reg = <0 0x2cc00000 0 0x20000>;
+ interrupts = <0 69 4>;
+ interrupt-names = "DPU";
+ clocks = <&scmi_clk 0>;
+ clock-names = "aclk";
+ pl0: pipeline@0 {
+ reg = <0>;
+ clocks = <&scmi_clk 1>;
+ clock-names = "pxclk";
+ pl_id = <0>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ dp_pl0_out0: endpoint {
+ remote-endpoint = <&vencoder_in>;
+ };
+ };
+ };
+ };
+
+ pl1: pipeline@1 {
+ reg = <1>;
+ clocks = <&scmi_clk 2>;
+ clock-names = "pxclk";
+ pl_id = <1>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ };
+ };
+ };
+ };
+
+};
diff --git a/fdts/tc0.dts b/fdts/tc0.dts
deleted file mode 100644
index 2d7611c..0000000
--- a/fdts/tc0.dts
+++ /dev/null
@@ -1,445 +0,0 @@
-/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-
-/ {
- compatible = "arm,tc0";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- serial0 = &soc_uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu-map {
- cluster0 {
- core0 {
- cpu = <&CPU0>;
- };
- core1 {
- cpu = <&CPU1>;
- };
- core2 {
- cpu = <&CPU2>;
- };
- core3 {
- cpu = <&CPU3>;
- };
- core4 {
- cpu = <&CPU4>;
- };
- core5 {
- cpu = <&CPU5>;
- };
- core6 {
- cpu = <&CPU6>;
- };
- core7 {
- cpu = <&CPU7>;
- };
- };
- };
-
- /*
- * The timings below are just to demonstrate working cpuidle.
- * These values may be inaccurate.
- */
- idle-states {
- entry-method = "arm,psci";
-
- CPU_SLEEP_0: cpu-sleep-0 {
- compatible = "arm,idle-state";
- arm,psci-suspend-param = <0x0010000>;
- local-timer-stop;
- entry-latency-us = <300>;
- exit-latency-us = <1200>;
- min-residency-us = <2000>;
- };
- CLUSTER_SLEEP_0: cluster-sleep-0 {
- compatible = "arm,idle-state";
- arm,psci-suspend-param = <0x1010000>;
- local-timer-stop;
- entry-latency-us = <400>;
- exit-latency-us = <1200>;
- min-residency-us = <2500>;
- };
- };
-
- CPU0:cpu@0 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 0>;
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- };
-
- CPU1:cpu@100 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x100>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 0>;
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- };
-
- CPU2:cpu@200 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x200>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 0>;
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- };
-
- CPU3:cpu@300 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x300>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 0>;
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- };
-
- CPU4:cpu@400 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x400>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 1>;
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- };
-
- CPU5:cpu@500 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x500>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 1>;
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- };
-
- CPU6:cpu@600 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x600>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 1>;
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- };
-
- CPU7:cpu@700 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x700>;
- enable-method = "psci";
- clocks = <&scmi_dvfs 1>;
- cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
- };
-
- };
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x0 0x80000000 0x0 0x7d000000>;
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- optee@0xfce00000 {
- reg = <0x00000000 0xfce00000 0 0x00200000>;
- no-map;
- };
- };
-
- psci {
- compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
- method = "smc";
- };
-
- sram: sram@6000000 {
- compatible = "mmio-sram";
- reg = <0x0 0x06000000 0x0 0x8000>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x0 0x06000000 0x8000>;
-
- cpu_scp_scmi_mem: scp-shmem@0 {
- compatible = "arm,scmi-shmem";
- reg = <0x0 0x80>;
- };
- };
-
- mbox_db_rx: mhu@45010000 {
- compatible = "arm,mhuv2","arm,primecell";
- reg = <0x0 0x45010000 0x0 0x1000>;
- clocks = <&soc_refclk100mhz>;
- clock-names = "apb_pclk";
- #mbox-cells = <1>;
- interrupts = <0 317 4>;
- interrupt-names = "mhu_rx";
- mhu-protocol = "doorbell";
- };
-
- mbox_db_tx: mhu@45000000 {
- compatible = "arm,mhuv2","arm,primecell";
- reg = <0x0 0x45000000 0x0 0x1000>;
- clocks = <&soc_refclk100mhz>;
- clock-names = "apb_pclk";
- #mbox-cells = <1>;
- interrupt-names = "mhu_tx";
- mhu-protocol = "doorbell";
- };
-
- scmi {
- compatible = "arm,scmi";
- method = "mailbox-doorbell";
- mbox-names = "tx", "rx";
- mboxes = <&mbox_db_tx 0 &mbox_db_rx 0>;
- shmem = <&cpu_scp_scmi_mem &cpu_scp_scmi_mem>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- scmi_dvfs: protocol@13 {
- reg = <0x13>;
- #clock-cells = <1>;
- };
-
- scmi_clk: protocol@14 {
- reg = <0x14>;
- #clock-cells = <1>;
- };
- };
-
- gic: interrupt-controller@2c010000 {
- compatible = "arm,gic-600", "arm,gic-v3";
- #address-cells = <2>;
- #interrupt-cells = <3>;
- #size-cells = <2>;
- ranges;
- interrupt-controller;
- reg = <0x0 0x30000000 0 0x10000>, /* GICD */
- <0x0 0x30140000 0 0x200000>; /* GICR */
- interrupts = <0x1 0x9 0x4>;
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <0x1 13 0x8>,
- <0x1 14 0x8>,
- <0x1 11 0x8>,
- <0x1 10 0x8>;
- };
-
- soc_refclk100mhz: refclk100mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- clock-output-names = "apb_pclk";
- };
-
- soc_refclk60mhz: refclk60mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <60000000>;
- clock-output-names = "iofpga_clk";
- };
-
- soc_uartclk: uartclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <50000000>;
- clock-output-names = "uartclk";
- };
-
- soc_uart0: uart@7ff80000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0x0 0x7ff80000 0x0 0x1000>;
- interrupts = <0x0 116 0x4>;
- clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
- clock-names = "uartclk", "apb_pclk";
- status = "okay";
- };
-
- vencoder {
- compatible = "drm,virtual-encoder";
-
- port {
- vencoder_in: endpoint {
- remote-endpoint = <&dp_pl0_out0>;
- };
- };
-
- display-timings {
- panel-timing {
- clock-frequency = <25175000>;
- hactive = <640>;
- vactive = <480>;
- hfront-porch = <16>;
- hback-porch = <48>;
- hsync-len = <96>;
- vfront-porch = <10>;
- vback-porch = <33>;
- vsync-len = <2>;
- };
- };
-
- };
-
- hdlcd: hdlcd@7ff60000 {
- compatible = "arm,hdlcd";
- reg = <0x0 0x7ff60000 0x0 0x1000>;
- interrupts = <0x0 117 0x4>;
- clocks = <&fake_hdlcd_clk>;
- clock-names = "pxlclk";
- status = "disabled";
-
- port {
- hdlcd_out: endpoint {
- remote-endpoint = <&vencoder_in>;
- };
- };
- };
-
- fake_hdlcd_clk: fake-hdlcd-clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25175000>;
- clock-output-names = "pxlclk";
- };
-
- ethernet@18000000 {
- compatible = "smsc,lan91c111";
- reg = <0x0 0x18000000 0x0 0x10000>;
- interrupts = <0 109 4>;
- };
-
- kmi@1c060000 {
- compatible = "arm,pl050", "arm,primecell";
- reg = <0x0 0x001c060000 0x0 0x1000>;
- interrupts = <0 197 4>;
- clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
- clock-names = "KMIREFCLK", "apb_pclk";
- };
-
- kmi@1c070000 {
- compatible = "arm,pl050", "arm,primecell";
- reg = <0x0 0x001c070000 0x0 0x1000>;
- interrupts = <0 103 4>;
- clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
- clock-names = "KMIREFCLK", "apb_pclk";
- };
-
- bp_clock24mhz: clock24mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <24000000>;
- clock-output-names = "bp:clock24mhz";
- };
-
- virtio_block@1c130000 {
- compatible = "virtio,mmio";
- reg = <0x0 0x1c130000 0x0 0x200>;
- interrupts = <0 204 4>;
- };
-
- sysreg: sysreg@1c010000 {
- compatible = "arm,vexpress-sysreg";
- reg = <0x0 0x001c010000 0x0 0x1000>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- fixed_3v3: v2m-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- };
-
- mmci@1c050000 {
- compatible = "arm,pl180", "arm,primecell";
- reg = <0x0 0x001c050000 0x0 0x1000>;
- interrupts = <0 107 0x4>,
- <0 108 0x4>;
- cd-gpios = <&sysreg 0 0>;
- wp-gpios = <&sysreg 1 0>;
- bus-width = <8>;
- max-frequency = <12000000>;
- vmmc-supply = <&fixed_3v3>;
- clocks = <&bp_clock24mhz>, <&bp_clock24mhz>;
- clock-names = "mclk", "apb_pclk";
- };
-
- dp0: display@2cc00000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "arm,mali-d71";
- reg = <0 0x2cc00000 0 0x20000>;
- interrupts = <0 69 4>;
- interrupt-names = "DPU";
- clocks = <&scmi_clk 0>;
- clock-names = "aclk";
- pl0: pipeline@0 {
- reg = <0>;
- clocks = <&scmi_clk 1>;
- clock-names = "pxclk";
- pl_id = <0>;
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- dp_pl0_out0: endpoint {
- remote-endpoint = <&vencoder_in>;
- };
- };
- };
- };
-
- pl1: pipeline@1 {
- reg = <1>;
- clocks = <&scmi_clk 2>;
- clock-names = "pxclk";
- pl_id = <1>;
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- };
- };
- };
- };
-
- ffa {
- compatible = "arm,ffa";
- conduit = "smc";
- mem_share_buffer = "tx";
- };
-
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "ffa";
- };
- };
-};
diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h
index c30073b..54ec009 100644
--- a/include/arch/aarch32/arch.h
+++ b/include/arch/aarch32/arch.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -116,6 +116,9 @@
#define ID_PFR0_AMU_SHIFT U(20)
#define ID_PFR0_AMU_LENGTH U(4)
#define ID_PFR0_AMU_MASK U(0xf)
+#define ID_PFR0_AMU_NOT_SUPPORTED U(0x0)
+#define ID_PFR0_AMU_V1 U(0x1)
+#define ID_PFR0_AMU_V1P1 U(0x2)
#define ID_PFR0_DIT_SHIFT U(24)
#define ID_PFR0_DIT_LENGTH U(4)
@@ -653,7 +656,7 @@
#define PAR_ADDR_MASK (BIT_64(40) - ULL(1)) /* 40-bits-wide page address */
/*******************************************************************************
- * Definitions for system register interface to AMU for ARMv8.4 onwards
+ * Definitions for system register interface to AMU for FEAT_AMUv1
******************************************************************************/
#define AMCR p15, 0, c13, c2, 0
#define AMCFGR p15, 0, c13, c2, 1
@@ -712,6 +715,9 @@
#define AMEVTYPER1E p15, 0, c13, c15, 6
#define AMEVTYPER1F p15, 0, c13, c15, 7
+/* AMCR definitions */
+#define AMCR_CG1RZ_BIT (ULL(1) << 17)
+
/* AMCFGR definitions */
#define AMCFGR_NCG_SHIFT U(28)
#define AMCFGR_NCG_MASK U(0xf)
diff --git a/include/arch/aarch32/arch_helpers.h b/include/arch/aarch32/arch_helpers.h
index 82efb18..726baf5 100644
--- a/include/arch/aarch32/arch_helpers.h
+++ b/include/arch/aarch32/arch_helpers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -303,6 +303,7 @@
/* Coproc registers for 32bit AMU support */
DEFINE_COPROCR_READ_FUNC(amcfgr, AMCFGR)
DEFINE_COPROCR_READ_FUNC(amcgcr, AMCGCR)
+DEFINE_COPROCR_RW_FUNCS(amcr, AMCR)
DEFINE_COPROCR_RW_FUNCS(amcntenset0, AMCNTENSET0)
DEFINE_COPROCR_RW_FUNCS(amcntenset1, AMCNTENSET1)
diff --git a/include/arch/aarch32/asm_macros.S b/include/arch/aarch32/asm_macros.S
index f75da0c..483f9fe 100644
--- a/include/arch/aarch32/asm_macros.S
+++ b/include/arch/aarch32/asm_macros.S
@@ -107,12 +107,12 @@
#else
/*
- * Macro for mitigating against speculative execution beyond ERET.
- * If possible use Speculation Barrier instruction defined in ARMv8.5
+ * Macro for mitigating against speculative execution beyond ERET. Uses the
+ * speculation barrier instruction introduced by FEAT_SB, if it's enabled.
*/
.macro exception_return
eret
-#if ARM_ARCH_AT_LEAST(8, 5)
+#if ENABLE_FEAT_SB
sb
#else
dsb nsh
diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S
index 580dd95..7fff4c7 100644
--- a/include/arch/aarch32/el3_common_macros.S
+++ b/include/arch/aarch32/el3_common_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,6 +10,9 @@
#include <arch.h>
#include <asm_macros.S>
#include <assert_macros.S>
+#include <lib/xlat_tables/xlat_tables_defs.h>
+
+#define PAGE_START_MASK ~(PAGE_SIZE_MASK)
/*
* Helper macro to initialise EL3 registers we care about.
@@ -199,11 +202,18 @@
*
* _exception_vectors:
* Address of the exception vectors to program in the VBAR_EL3 register.
+ *
+ * _pie_fixup_size:
+ * Size of memory region to fixup Global Descriptor Table (GDT).
+ *
+ * A non-zero value is expected when firmware needs GDT to be fixed-up.
+ *
* -----------------------------------------------------------------------------
*/
.macro el3_entrypoint_common \
_init_sctlr, _warm_boot_mailbox, _secondary_cold_boot, \
- _init_memory, _init_c_runtime, _exception_vectors
+ _init_memory, _init_c_runtime, _exception_vectors, \
+ _pie_fixup_size
/* Make sure we are in Secure Mode */
#if ENABLE_ASSERTIONS
@@ -259,6 +269,27 @@
bxne r0
.endif /* _warm_boot_mailbox */
+ .if \_pie_fixup_size
+#if ENABLE_PIE
+ /*
+ * ------------------------------------------------------------
+ * If PIE is enabled fixup the Global descriptor Table only
+ * once during primary core cold boot path.
+ *
+ * Compile time base address, required for fixup, is calculated
+ * using "pie_fixup" label present within first page.
+ * ------------------------------------------------------------
+ */
+ pie_fixup:
+ ldr r0, =pie_fixup
+ ldr r1, =PAGE_START_MASK
+ and r0, r0, r1
+ mov_imm r1, \_pie_fixup_size
+ add r1, r1, r0
+ bl fixup_gdt_reloc
+#endif /* ENABLE_PIE */
+ .endif /* _pie_fixup_size */
+
/* ---------------------------------------------------------------------
* Set the exception vectors (VBAR/MVBAR).
* ---------------------------------------------------------------------
@@ -339,12 +370,14 @@
*/
mov r7, r12
ldr r0, =__BSS_START__
- ldr r1, =__BSS_SIZE__
+ ldr r1, =__BSS_END__
+ sub r1, r1, r0
bl zeromem
#if USE_COHERENT_MEM
ldr r0, =__COHERENT_RAM_START__
- ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__
+ ldr r1, =__COHERENT_RAM_END_UNALIGNED__
+ sub r1, r1, r0
bl zeromem
#endif
@@ -358,7 +391,8 @@
*/
ldr r0, =__DATA_RAM_START__
ldr r1, =__DATA_ROM_START__
- ldr r2, =__DATA_SIZE__
+ ldr r2, =__DATA_RAM_END__
+ sub r2, r2, r0
bl memcpy4
#endif
.endif /* _init_c_runtime */
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 2cdc7b2..c12dbc4 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -161,12 +161,16 @@
#define ID_AA64PFR0_EL3_SHIFT U(12)
#define ID_AA64PFR0_AMU_SHIFT U(44)
#define ID_AA64PFR0_AMU_MASK ULL(0xf)
+#define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0)
+#define ID_AA64PFR0_AMU_V1 U(0x1)
+#define ID_AA64PFR0_AMU_V1P1 U(0x2)
#define ID_AA64PFR0_ELX_MASK ULL(0xf)
#define ID_AA64PFR0_GIC_SHIFT U(24)
#define ID_AA64PFR0_GIC_WIDTH U(4)
#define ID_AA64PFR0_GIC_MASK ULL(0xf)
#define ID_AA64PFR0_SVE_SHIFT U(32)
#define ID_AA64PFR0_SVE_MASK ULL(0xf)
+#define ID_AA64PFR0_SVE_LENGTH U(4)
#define ID_AA64PFR0_SEL2_SHIFT U(36)
#define ID_AA64PFR0_SEL2_MASK ULL(0xf)
#define ID_AA64PFR0_MPAM_SHIFT U(40)
@@ -259,6 +263,9 @@
#define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2)
#define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3)
+#define ID_AA64MMFR1_EL1_VHE_SHIFT U(8)
+#define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf)
+
/* ID_AA64MMFR2_EL1 definitions */
#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
@@ -386,7 +393,8 @@
#define SCTLR_ATA0_BIT (ULL(1) << 42)
#define SCTLR_ATA_BIT (ULL(1) << 43)
-#define SCTLR_DSSBS_BIT (ULL(1) << 44)
+#define SCTLR_DSSBS_SHIFT U(44)
+#define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT)
#define SCTLR_TWEDEn_BIT (ULL(1) << 45)
#define SCTLR_TWEDEL_SHIFT U(46)
#define SCTLR_TWEDEL_MASK ULL(0xf)
@@ -406,9 +414,10 @@
#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
#define SCR_TWEDEL_SHIFT U(30)
#define SCR_TWEDEL_MASK ULL(0xf)
+#define SCR_AMVOFFEN_BIT (UL(1) << 35)
#define SCR_TWEDEn_BIT (UL(1) << 29)
-#define SCR_ECVEN_BIT (UL(1) << 28)
-#define SCR_FGTEN_BIT (UL(1) << 27)
+#define SCR_ECVEN_BIT (UL(1) << 28)
+#define SCR_FGTEN_BIT (UL(1) << 27)
#define SCR_ATA_BIT (UL(1) << 26)
#define SCR_FIEN_BIT (UL(1) << 21)
#define SCR_EEL2_BIT (UL(1) << 18)
@@ -430,8 +439,16 @@
#define SCR_RESET_VAL SCR_RES1_BITS
/* MDCR_EL3 definitions */
+#define MDCR_EnPMSN_BIT (ULL(1) << 36)
+#define MDCR_MPMX_BIT (ULL(1) << 35)
+#define MDCR_MCCD_BIT (ULL(1) << 34)
#define MDCR_MTPME_BIT (ULL(1) << 28)
+#define MDCR_TDCC_BIT (ULL(1) << 27)
#define MDCR_SCCD_BIT (ULL(1) << 23)
+#define MDCR_EPMAD_BIT (ULL(1) << 21)
+#define MDCR_EDAD_BIT (ULL(1) << 20)
+#define MDCR_TTRF_BIT (ULL(1) << 19)
+#define MDCR_STE_BIT (ULL(1) << 18)
#define MDCR_SPME_BIT (ULL(1) << 17)
#define MDCR_SDD_BIT (ULL(1) << 16)
#define MDCR_SPD32(x) ((x) << 14)
@@ -479,6 +496,7 @@
#define VTTBR_BADDR_SHIFT U(0)
/* HCR definitions */
+#define HCR_AMVOFFEN_BIT (ULL(1) << 51)
#define HCR_API_BIT (ULL(1) << 41)
#define HCR_APK_BIT (ULL(1) << 40)
#define HCR_E2H_BIT (ULL(1) << 34)
@@ -516,7 +534,7 @@
#define TTA_BIT (U(1) << 20)
#define TFP_BIT (U(1) << 10)
#define CPTR_EZ_BIT (U(1) << 8)
-#define CPTR_EL3_RESET_VAL U(0x0)
+#define CPTR_EL3_RESET_VAL (TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT & ~(CPTR_EZ_BIT))
/* CPTR_EL2 definitions */
#define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
@@ -556,8 +574,16 @@
#define SPSR_EL_SHIFT U(2)
#define SPSR_EL_WIDTH U(2)
-#define SPSR_SSBS_BIT_AARCH64 BIT_64(12)
-#define SPSR_SSBS_BIT_AARCH32 BIT_64(23)
+#define SPSR_SSBS_SHIFT_AARCH64 U(12)
+#define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64)
+#define SPSR_SSBS_SHIFT_AARCH32 U(23)
+#define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32)
+
+#define SPSR_PAN_BIT BIT_64(22)
+
+#define SPSR_DIT_BIT BIT(24)
+
+#define SPSR_TCO_BIT_AARCH64 BIT_64(25)
#define DISABLE_ALL_EXCEPTIONS \
(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
@@ -721,13 +747,13 @@
#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
/* Physical timer control register bit fields shifts and masks */
-#define CNTP_CTL_ENABLE_SHIFT U(0)
-#define CNTP_CTL_IMASK_SHIFT U(1)
-#define CNTP_CTL_ISTATUS_SHIFT U(2)
+#define CNTP_CTL_ENABLE_SHIFT U(0)
+#define CNTP_CTL_IMASK_SHIFT U(1)
+#define CNTP_CTL_ISTATUS_SHIFT U(2)
-#define CNTP_CTL_ENABLE_MASK U(1)
-#define CNTP_CTL_IMASK_MASK U(1)
-#define CNTP_CTL_ISTATUS_MASK U(1)
+#define CNTP_CTL_ENABLE_MASK U(1)
+#define CNTP_CTL_IMASK_MASK U(1)
+#define CNTP_CTL_ISTATUS_MASK U(1)
/* Physical timer control macros */
#define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT)
@@ -913,7 +939,7 @@
#define MPAM3_EL3 S3_6_C10_C5_0
/*******************************************************************************
- * Definitions for system register interface to AMU for ARMv8.4 onwards
+ * Definitions for system register interface to AMU for FEAT_AMUv1
******************************************************************************/
#define AMCR_EL0 S3_3_C13_C2_0
#define AMCFGR_EL0 S3_3_C13_C2_1
@@ -992,6 +1018,50 @@
#define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17)
/*******************************************************************************
+ * Definitions for system register interface to AMU for FEAT_AMUv1p1
+ ******************************************************************************/
+
+/* Definition for register defining which virtual offsets are implemented. */
+#define AMCG1IDR_EL0 S3_3_C13_C2_6
+#define AMCG1IDR_CTR_MASK ULL(0xffff)
+#define AMCG1IDR_CTR_SHIFT U(0)
+#define AMCG1IDR_VOFF_MASK ULL(0xffff)
+#define AMCG1IDR_VOFF_SHIFT U(16)
+
+/* New bit added to AMCR_EL0 */
+#define AMCR_CG1RZ_BIT (ULL(0x1) << 17)
+
+/*
+ * Definitions for virtual offset registers for architected activity monitor
+ * event counters.
+ * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist.
+ */
+#define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0
+#define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2
+#define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3
+
+/*
+ * Definitions for virtual offset registers for auxiliary activity monitor event
+ * counters.
+ */
+#define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0
+#define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1
+#define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2
+#define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3
+#define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4
+#define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5
+#define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6
+#define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7
+#define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0
+#define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1
+#define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2
+#define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3
+#define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4
+#define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5
+#define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6
+#define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7
+
+/*******************************************************************************
* RAS system registers
******************************************************************************/
#define DISR_EL1 S3_0_C12_C1_1
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 671b3dc..dc0b7f3 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,6 +17,18 @@
return true;
}
+static inline bool is_armv8_1_pan_present(void)
+{
+ return ((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_PAN_SHIFT) &
+ ID_AA64MMFR1_EL1_PAN_MASK) != 0U;
+}
+
+static inline bool is_armv8_1_vhe_present(void)
+{
+ return ((read_id_aa64mmfr1_el1() >> ID_AA64MMFR1_EL1_VHE_SHIFT) &
+ ID_AA64MMFR1_EL1_VHE_MASK) != 0U;
+}
+
static inline bool is_armv8_2_ttcnp_present(void)
{
return ((read_id_aa64mmfr2_el1() >> ID_AA64MMFR2_EL1_CNP_SHIFT) &
@@ -82,6 +94,12 @@
ID_AA64ISAR0_RNDR_MASK);
}
+static inline bool is_armv8_6_feat_amuv1p1_present(void)
+{
+ return (((read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT) &
+ ID_AA64PFR0_AMU_MASK) >= ID_AA64PFR0_AMU_V1P1);
+}
+
/*
* Return MPAM version:
*
diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h
index 7fafafc..a41b325 100644
--- a/include/arch/aarch64/arch_helpers.h
+++ b/include/arch/aarch64/arch_helpers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -260,6 +260,9 @@
DEFINE_SYSREG_RW_FUNCS(elr_el1)
DEFINE_SYSREG_RW_FUNCS(elr_el2)
DEFINE_SYSREG_RW_FUNCS(elr_el3)
+DEFINE_SYSREG_RW_FUNCS(mdccsr_el0)
+DEFINE_SYSREG_RW_FUNCS(dbgdtrrx_el0)
+DEFINE_SYSREG_RW_FUNCS(dbgdtrtx_el0)
DEFINE_SYSOP_FUNC(wfi)
DEFINE_SYSOP_FUNC(wfe)
@@ -485,6 +488,8 @@
DEFINE_RENAME_SYSREG_READ_FUNC(amcfgr_el0, AMCFGR_EL0)
DEFINE_RENAME_SYSREG_READ_FUNC(amcgcr_el0, AMCGCR_EL0)
+DEFINE_RENAME_SYSREG_READ_FUNC(amcg1idr_el0, AMCG1IDR_EL0)
+DEFINE_RENAME_SYSREG_RW_FUNCS(amcr_el0, AMCR_EL0)
DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0)
DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0)
DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0)
diff --git a/include/arch/aarch64/asm_macros.S b/include/arch/aarch64/asm_macros.S
index cbb9f0b..7706cd8 100644
--- a/include/arch/aarch64/asm_macros.S
+++ b/include/arch/aarch64/asm_macros.S
@@ -10,10 +10,6 @@
#include <common/asm_macros_common.S>
#include <lib/spinlock.h>
-#if ENABLE_BTI && !ARM_ARCH_AT_LEAST(8, 5)
-#error Branch Target Identification requires ARM_ARCH_MINOR >= 5
-#endif
-
/*
* TLBI instruction with type specifier that implements the workaround for
* errata 813419 of Cortex-A57 or errata 1286807 of Cortex-A76.
@@ -219,12 +215,12 @@
.endm
/*
- * Macro for mitigating against speculative execution beyond ERET.
- * If possible use Speculation Barrier instruction defined in ARMv8.5
+ * Macro for mitigating against speculative execution beyond ERET. Uses the
+ * speculation barrier instruction introduced by FEAT_SB, if it's enabled.
*/
.macro exception_return
eret
-#if ARM_ARCH_AT_LEAST(8, 5)
+#if ENABLE_FEAT_SB
sb
#else
dsb nsh
diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S
index f759983..9734335 100644
--- a/include/arch/aarch64/el3_common_macros.S
+++ b/include/arch/aarch64/el3_common_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -113,8 +113,13 @@
*
* MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is
* prohibited in Secure state. This bit is RES0 in versions of the
- * architecture earlier than ARMv8.5, setting it to 1 doesn't have any
- * effect on them.
+ * architecture with FEAT_PMUv3p5 not implemented, setting it to 1
+ * doesn't have any effect on them.
+ *
+ * MDCR_EL3.MCCD: Set to one so that cycle counting by PMCCNTR_EL0 is
+ * prohibited in EL3. This bit is RES0 in versions of the
+ * architecture with FEAT_PMUv3p7 not implemented, setting it to 1
+ * doesn't have any effect on them.
*
* MDCR_EL3.SPME: Set to zero so that event counting by the programmable
* counters PMEVCNTR<n>_EL0 is prohibited in Secure state. If ARMv8.2
@@ -124,9 +129,9 @@
* ---------------------------------------------------------------------
*/
mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \
- MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT) & \
- ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | MDCR_TDA_BIT | \
- MDCR_TPM_BIT))
+ MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT | \
+ MDCR_MCCD_BIT) & ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | \
+ MDCR_TDA_BIT | MDCR_TPM_BIT))
msr mdcr_el3, x0
@@ -180,7 +185,14 @@
* CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers
* by Advanced SIMD, floating-point or SVE instructions (if implemented)
* do not trap to EL3.
+ *
+ * CPTR_EL3.TAM: Set to one so that Activity Monitor access is
+ * trapped to EL3 by default.
+ *
+ * CPTR_EL3.EZ: Set to zero so that all SVE functionality is trapped
+ * to EL3 by default.
*/
+
mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT))
msr cptr_el3, x0
diff --git a/include/common/bl_common.h b/include/common/bl_common.h
index 77fb1f6..e33840c 100644
--- a/include/common/bl_common.h
+++ b/include/common/bl_common.h
@@ -106,6 +106,10 @@
IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE);
IMPORT_SYM(uintptr_t, __RO_END__, BL_CODE_END);
#endif
+#if SEPARATE_NOBITS_REGION
+IMPORT_SYM(uintptr_t, __NOBITS_START__, BL_NOBITS_BASE);
+IMPORT_SYM(uintptr_t, __NOBITS_END__, BL_NOBITS_END);
+#endif
IMPORT_SYM(uintptr_t, __RW_END__, BL_END);
#if defined(IMAGE_BL1)
diff --git a/include/common/bl_common.ld.h b/include/common/bl_common.ld.h
index ab3391a..5147e37 100644
--- a/include/common/bl_common.ld.h
+++ b/include/common/bl_common.ld.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -105,10 +105,18 @@
* .rela.dyn needs to come after .data for the read-elf utility to parse
* this section correctly.
*/
+#if __aarch64__
+#define RELA_DYN_NAME .rela.dyn
+#define RELOC_SECTIONS_PATTERN *(.rela*)
+#else
+#define RELA_DYN_NAME .rel.dyn
+#define RELOC_SECTIONS_PATTERN *(.rel*)
+#endif
+
#define RELA_SECTION \
- .rela.dyn : ALIGN(STRUCT_ALIGN) { \
+ RELA_DYN_NAME : ALIGN(STRUCT_ALIGN) { \
__RELA_START__ = .; \
- *(.rela*) \
+ RELOC_SECTIONS_PATTERN \
__RELA_END__ = .; \
}
diff --git a/include/common/debug.h b/include/common/debug.h
index ed0e8bf..a7ca0d7 100644
--- a/include/common/debug.h
+++ b/include/common/debug.h
@@ -61,8 +61,10 @@
#if LOG_LEVEL >= LOG_LEVEL_ERROR
# define ERROR(...) tf_log(LOG_MARKER_ERROR __VA_ARGS__)
+# define ERROR_NL() tf_log_newline(LOG_MARKER_ERROR)
#else
# define ERROR(...) no_tf_log(LOG_MARKER_ERROR __VA_ARGS__)
+# define ERROR_NL()
#endif
#if LOG_LEVEL >= LOG_LEVEL_NOTICE
@@ -109,6 +111,7 @@
void __dead2 __stack_chk_fail(void);
void tf_log(const char *fmt, ...) __printflike(1, 2);
+void tf_log_newline(const char log_fmt[2]);
void tf_log_set_max_level(unsigned int log_level);
#endif /* __ASSEMBLER__ */
diff --git a/include/common/fdt_wrappers.h b/include/common/fdt_wrappers.h
index a571092..e8b3933 100644
--- a/include/common/fdt_wrappers.h
+++ b/include/common/fdt_wrappers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,6 +24,8 @@
unsigned int cells, uint32_t *value);
int fdtw_read_string(const void *dtb, int node, const char *prop,
char *str, size_t size);
+int fdtw_read_uuid(const void *dtb, int node, const char *prop,
+ unsigned int length, uint8_t *uuid);
int fdtw_write_inplace_cells(void *dtb, int node, const char *prop,
unsigned int cells, void *value);
int fdtw_read_bytes(const void *dtb, int node, const char *prop,
diff --git a/include/common/tbbr/cot_def.h b/include/common/tbbr/cot_def.h
index 6ce7f80..800ad07 100644
--- a/include/common/tbbr/cot_def.h
+++ b/include/common/tbbr/cot_def.h
@@ -7,6 +7,10 @@
#ifndef COT_DEF_H
#define COT_DEF_H
+#ifdef MBEDTLS_CONFIG_FILE
+#include MBEDTLS_CONFIG_FILE
+#endif
+
/* TBBR CoT definitions */
#if defined(SPD_spmd)
#define COT_MAX_VERIFIED_PARAMS 8
diff --git a/include/common/tbbr/tbbr_img_def.h b/include/common/tbbr/tbbr_img_def.h
index bd125e6..e1c8c29 100644
--- a/include/common/tbbr/tbbr_img_def.h
+++ b/include/common/tbbr/tbbr_img_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,9 +21,17 @@
#define SP_PKG7_ID (MAX_IMAGE_IDS + 8)
#define SP_PKG8_ID (MAX_IMAGE_IDS + 9)
#define MAX_SP_IDS U(8)
-#define MAX_NUMBER_IDS (MAX_IMAGE_IDS + MAX_SP_IDS + U(2))
+#define MAX_IMG_IDS_WITH_SPMDS (MAX_IMAGE_IDS + MAX_SP_IDS + U(2))
#else
-#define MAX_NUMBER_IDS MAX_IMAGE_IDS
+#define MAX_IMG_IDS_WITH_SPMDS MAX_IMAGE_IDS
+#endif
+
+#ifdef PLAT_TBBR_IMG_DEF
+#include <plat_tbbr_img_def.h>
+#endif
+
+#ifndef MAX_NUMBER_IDS
+#define MAX_NUMBER_IDS MAX_IMG_IDS_WITH_SPMDS
#endif
#endif /* TBBR_IMG_DEF_H */
diff --git a/include/common/tf_crc32.h b/include/common/tf_crc32.h
new file mode 100644
index 0000000..38c56a5
--- /dev/null
+++ b/include/common/tf_crc32.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TF_CRC32_H
+#define TF_CRC32_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+/* compute CRC using Arm intrinsic function */
+uint32_t tf_crc32(uint32_t crc, const unsigned char *buf, size_t size);
+
+#endif /* TF_CRC32_H */
diff --git a/include/common/uuid.h b/include/common/uuid.h
new file mode 100644
index 0000000..5651d0d
--- /dev/null
+++ b/include/common/uuid.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef UUID_H
+#define UUID_H
+
+#define UUID_BYTES_LENGTH 16
+#define UUID_STRING_LENGTH 36
+
+int read_uuid(uint8_t *dest, char *uuid);
+
+#endif /* UUID_H */
diff --git a/include/drivers/arm/css/scmi.h b/include/drivers/arm/css/scmi.h
index e8a2863..adce7a6 100644
--- a/include/drivers/arm/css/scmi.h
+++ b/include/drivers/arm/css/scmi.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,7 +16,7 @@
/* Supported SCMI Protocol Versions */
#define SCMI_AP_CORE_PROTO_VER MAKE_SCMI_VERSION(1, 0)
-#define SCMI_PWR_DMN_PROTO_VER MAKE_SCMI_VERSION(1, 0)
+#define SCMI_PWR_DMN_PROTO_VER MAKE_SCMI_VERSION(2, 0)
#define SCMI_SYS_PWR_PROTO_VER MAKE_SCMI_VERSION(1, 0)
#define GET_SCMI_MAJOR_VER(ver) (((ver) >> 16) & 0xffff)
diff --git a/include/drivers/arm/dcc.h b/include/drivers/arm/dcc.h
new file mode 100644
index 0000000..1f1fd03
--- /dev/null
+++ b/include/drivers/arm/dcc.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2021, Xilinx Inc.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DCC_H
+#define DCC_H
+
+#include <stdint.h>
+#include <drivers/console.h>
+
+/*
+ * Initialize a new dcc console instance and register it with the console
+ * framework.
+ */
+int console_dcc_register(void);
+
+#endif /* DCC */
diff --git a/include/drivers/arm/ethosn.h b/include/drivers/arm/ethosn.h
new file mode 100644
index 0000000..6de2abb
--- /dev/null
+++ b/include/drivers/arm/ethosn.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef ETHOSN_H
+#define ETHOSN_H
+
+#include <lib/smccc.h>
+
+/* Function numbers */
+#define ETHOSN_FNUM_VERSION U(0x50)
+#define ETHOSN_FNUM_IS_SEC U(0x51)
+#define ETHOSN_FNUM_HARD_RESET U(0x52)
+#define ETHOSN_FNUM_SOFT_RESET U(0x53)
+/* 0x54-0x5F reserved for future use */
+
+/* SMC64 function IDs */
+#define ETHOSN_FID_64(func_num) U(0xC2000000 | func_num)
+#define ETHOSN_FID_VERSION_64 ETHOSN_FID_64(ETHOSN_FNUM_VERSION)
+#define ETHOSN_FID_IS_SEC_64 ETHOSN_FID_64(ETHOSN_FNUM_IS_SEC)
+#define ETHOSN_FID_HARD_RESET_64 ETHOSN_FID_64(ETHOSN_FNUM_HARD_RESET)
+#define ETHOSN_FID_SOFT_RESET_64 ETHOSN_FID_64(ETHOSN_FNUM_SOFT_RESET)
+
+/* SMC32 function IDs */
+#define ETHOSN_FID_32(func_num) U(0x82000000 | func_num)
+#define ETHOSN_FID_VERSION_32 ETHOSN_FID_32(ETHOSN_FNUM_VERSION)
+#define ETHOSN_FID_IS_SEC_32 ETHOSN_FID_32(ETHOSN_FNUM_IS_SEC)
+#define ETHOSN_FID_HARD_RESET_32 ETHOSN_FID_32(ETHOSN_FNUM_HARD_RESET)
+#define ETHOSN_FID_SOFT_RESET_32 ETHOSN_FID_32(ETHOSN_FNUM_SOFT_RESET)
+
+#define ETHOSN_NUM_SMC_CALLS 8
+
+/* Macro to identify function calls */
+#define ETHOSN_FID_MASK U(0xFFF0)
+#define ETHOSN_FID_VALUE U(0x50)
+#define is_ethosn_fid(_fid) (((_fid) & ETHOSN_FID_MASK) == ETHOSN_FID_VALUE)
+
+/* Service version */
+#define ETHOSN_VERSION_MAJOR U(0)
+#define ETHOSN_VERSION_MINOR U(1)
+
+/* Return codes for function calls */
+#define ETHOSN_SUCCESS 0
+#define ETHOSN_NOT_SUPPORTED -1
+/* -2 Reserved for NOT_REQUIRED */
+/* -3 Reserved for INVALID_PARAMETER */
+#define ETHOSN_FAILURE -4
+#define ETHOSN_CORE_IDX_OUT_OF_RANGE -5
+
+uintptr_t ethosn_smc_handler(uint32_t smc_fid,
+ u_register_t core_idx,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *cookie,
+ void *handle,
+ u_register_t flags);
+
+#endif /* ETHOSN_H */
diff --git a/include/drivers/arm/tzc400.h b/include/drivers/arm/tzc400.h
index 32aeb03..5f8a48f 100644
--- a/include/drivers/arm/tzc400.h
+++ b/include/drivers/arm/tzc400.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -65,8 +65,8 @@
#define FAIL_CONTROL_NS_SECURE U(0)
#define FAIL_CONTROL_NS_NONSECURE U(1)
#define FAIL_CONTROL_PRIV_SHIFT 20
-#define FAIL_CONTROL_PRIV_PRIV U(0)
-#define FAIL_CONTROL_PRIV_UNPRIV U(1)
+#define FAIL_CONTROL_PRIV_UNPRIV U(0)
+#define FAIL_CONTROL_PRIV_PRIV U(1)
/*
* FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific.
@@ -80,11 +80,8 @@
/* Filter enable bits in a TZC */
#define TZC_400_REGION_ATTR_F_EN_MASK U(0xf)
-#define TZC_400_REGION_ATTR_FILTER_BIT(x) \
- ((U(1) << (x)) << TZC_REGION_ATTR_F_EN_SHIFT)
-#define TZC_400_REGION_ATTR_FILTER_BIT_ALL \
- (TZC_400_REGION_ATTR_F_EN_MASK << \
- TZC_REGION_ATTR_F_EN_SHIFT)
+#define TZC_400_REGION_ATTR_FILTER_BIT(x) (U(1) << (x))
+#define TZC_400_REGION_ATTR_FILTER_BIT_ALL TZC_400_REGION_ATTR_F_EN_MASK
/*
* All TZC region configuration registers are placed one after another. It
@@ -93,6 +90,8 @@
#define TZC_400_REGION_SIZE U(0x20)
#define TZC_400_ACTION_OFF U(0x4)
+#define FILTER_OFFSET U(0x10)
+
#ifndef __ASSEMBLER__
#include <cdefs.h>
@@ -113,6 +112,7 @@
void tzc400_set_action(unsigned int action);
void tzc400_enable_filters(void);
void tzc400_disable_filters(void);
+int tzc400_it_handler(void);
static inline void tzc_init(uintptr_t base)
{
diff --git a/include/drivers/brcm/i2c/i2c.h b/include/drivers/brcm/i2c/i2c.h
new file mode 100644
index 0000000..24d42e2
--- /dev/null
+++ b/include/drivers/brcm/i2c/i2c.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2016 - 2021, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef I2C_H
+#define I2C_H
+
+#include <stdint.h>
+
+#define I2C_SPEED_100KHz 100000
+#define I2C_SPEED_400KHz 400000
+#define I2C_SPEED_DEFAULT I2C_SPEED_100KHz
+
+/*
+ * Function Name: i2c_probe
+ *
+ * Description:
+ * This function probes the I2C bus for the existence of the specified
+ * device.
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ * devaddr - Device Address
+ *
+ * Return:
+ * 0 on success, or -1 on failure.
+ */
+int i2c_probe(uint32_t bus_id, uint8_t devaddr);
+
+/*
+ * Function Name: i2c_init
+ *
+ * Description:
+ * This function initializes the SMBUS.
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ * speed - I2C bus speed in Hz
+ *
+ * Return:
+ * 0 on success, or -1 on failure.
+ */
+int i2c_init(uint32_t bus_id, int speed);
+
+/*
+ * Function Name: i2c_set_bus_speed
+ *
+ * Description:
+ * This function configures the SMBUS speed
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ * speed - I2C bus speed in Hz
+ *
+ * Return:
+ * 0 on success, or -1 on failure.
+ */
+int i2c_set_bus_speed(uint32_t bus_id, uint32_t speed);
+
+/*
+ * Function Name: i2c_get_bus_speed
+ *
+ * Description:
+ * This function returns the SMBUS speed.
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ *
+ * Return:
+ * Bus speed in Hz, 0 on failure
+ */
+uint32_t i2c_get_bus_speed(uint32_t bus_id);
+
+/*
+ * Function Name: i2c_recv_byte
+ *
+ * Description:
+ * This function reads I2C data from a device without specifying
+ * a command regsiter.
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ * devaddr - Device Address
+ * value - Data Read
+ *
+ * Return:
+ * 0 on success, or -1 on failure.
+ */
+int i2c_recv_byte(uint32_t bus_id, uint8_t devaddr, uint8_t *value);
+
+/*
+ * Function Name: i2c_send_byte
+ *
+ * Description:
+ * This function send I2C data to a device without specifying
+ * a command regsiter.
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ * devaddr - Device Address
+ * value - Data Send
+ *
+ * Return:
+ * 0 on success, or -1 on failure.
+ */
+int i2c_send_byte(uint32_t bus_id, uint8_t devaddr, uint8_t value);
+
+/*
+ * Function Name: i2c_read
+ *
+ * Description:
+ * This function reads I2C data from a device with a designated
+ * command register
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ * devaddr - Device Address
+ * addr - Register Offset
+ * alen - Address Length, 1 for byte, 2 for word (not supported)
+ * buffer - Data Buffer
+ * len - Data Length in bytes
+ *
+ * Return:
+ * 0 on success, or -1 on failure.
+ */
+int i2c_read(uint32_t bus_id,
+ uint8_t devaddr,
+ uint32_t addr,
+ int alen,
+ uint8_t *buffer,
+ int len);
+
+/*
+ * Function Name: i2c_write
+ *
+ * Description:
+ * This function write I2C data to a device with a designated
+ * command register
+ *
+ * Parameters:
+ * bus_id - I2C bus ID
+ * devaddr - Device Address
+ * addr - Register Offset
+ * alen - Address Length, 1 for byte, 2 for word (not supported)
+ * buffer - Data Buffer
+ * len - Data Length in bytes
+ *
+ * Return:
+ * 0 on success, or -1 on failure.
+ */
+int i2c_write(uint32_t bus_id,
+ uint8_t devaddr,
+ uint32_t addr,
+ int alen,
+ uint8_t *buffer,
+ int len);
+
+
+#endif /* I2C_H */
diff --git a/include/drivers/brcm/i2c/i2c_regs.h b/include/drivers/brcm/i2c/i2c_regs.h
new file mode 100644
index 0000000..74ea824
--- /dev/null
+++ b/include/drivers/brcm/i2c/i2c_regs.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2016 - 2021, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef I2C_REGS
+#define I2C_REGS
+
+/* SMBUS Config register */
+#define SMB_CFG_REG 0x0U
+
+#define SMB_CFG_RST_MASK 0x80000000U
+#define SMB_CFG_RST_SHIFT 31U
+
+#define SMB_CFG_SMBEN_MASK 0x40000000U
+#define SMB_CFG_SMBEN_SHIFT 30U
+
+#define SMB_CFG_BITBANGEN_MASK 0x20000000U
+#define SMB_CFG_BITBANGEN_SHIFT 29U
+
+#define SMB_CFG_EN_NIC_SMBADDR0_MASK 0x10000000U
+#define SMB_CFG_EN_NIC_SMBADDR0_SHIFT 28U
+
+#define SMB_CFG_PROMISCMODE_MASK 0x08000000U
+#define SMB_CFG_PROMISCMODE_SHIFT 27U
+
+#define SMB_CFG_TSTMPCNTEN_MASK 0x04000000U
+#define SMB_CFG_TSTMPCNTEN_SHIFT 26U
+
+#define SMB_CFG_MSTRRTRYCNT_MASK 0x000F0000U
+#define SMB_CFG_MSTRRTRYCNT_SHIFT 16U
+
+/* SMBUS Timing config register */
+#define SMB_TIMGCFG_REG 0x4U
+
+#define SMB_TIMGCFG_MODE400_MASK 0x80000000U
+#define SMB_TIMGCFG_MODE400_SHIFT 31U
+
+#define SMB_TIMGCFG_RNDSLVSTR_MASK 0x7F000000U
+#define SMB_TIMGCFG_RNDSLVSTR_SHIFT 24U
+
+#define SMB_TIMGCFG_PERSLVSTR_MASK 0x00FF0000U
+#define SMB_TIMGCFG_PERSLVSTR_SHIFT 16U
+
+#define SMB_TIMGCFG_IDLTIME_MASK 0x0000FF00U
+#define SMB_TIMGCFG_IDLTIME_SHIFT 8U
+
+/* SMBUS Slave address register */
+#define SMB_ADDR_REG 0x8U
+
+#define SMB_EN_NIC_SMBADDR3_MASK 0x80000000U
+#define SMB_EN_NIC_SMBADDR3_SHIFT 31U
+
+#define SMB_NIC_SMBADDR3_MASK 0x7F000000U
+#define SMB_NIC_SMBADDR3_SHIFT 24U
+
+#define SMB_EN_NIC_SMBADDR2_MASK 0x00800000U
+#define SMB_EN_NIC_SMBADDR2_SHIFT 23U
+
+#define SMB_NIC_SMBADDR2_MASK 0x007F0000U
+#define SMB_NIC_SMBADDR2_SHIFT 16U
+
+#define SMB_EN_NIC_SMBADDR1_MASK 0x00008000U
+#define SMB_EN_NIC_SMBADDR1_SHIFT 15U
+
+#define SMB_NIC_SMBADDR1_MASK 0x00007F00U
+#define SMB_NIC_SMBADDR1_SHIFT 8U
+
+#define SMB_EN_NIC_SMBADDR0_MASK 0x00000080U
+#define SMB_EN_NIC_SMBADDR0_SHIFT 7U
+
+#define SMB_NIC_SMBADDR0_MASK 0x0000007FU
+#define SMB_NIC_SMBADDR0_SHIFT 0U
+
+/* SMBUS Master FIFO control register */
+#define SMB_MSTRFIFOCTL_REG 0xCU
+
+#define SMB_MSTRRXFIFOFLSH_MASK 0x80000000U
+#define SMB_MSTRRXFIFOFLSH_SHIFT 31U
+
+#define SMB_MSTRTXFIFOFLSH_MASK 0x40000000U
+#define SMB_MSTRTXFIFOFLSH_SHIFT 30U
+
+#define SMB_MSTRRXPKTCNT_MASK 0x007F0000U
+#define SMB_MSTRRXPKTCNT_SHIFT 16U
+
+#define SMB_MSTRRXFIFOTHR_MASK 0x00003F00U
+#define SMB_MSTRRXFIFOTHR_SHIFT 8U
+
+/* SMBUS Slave FIFO control register */
+#define SMB_SLVFIFOCTL_REG 0x10U
+
+#define SMB_SLVRXFIFOFLSH_MASK 0x80000000U
+#define SMB_SLVRXFIFOFLSH_SHIFT 31U
+
+#define SMB_SLVTXFIFOFLSH_MASK 0x40000000U
+#define SMB_SLVTXFIFOFLSH_SHIFT 30U
+
+#define SMB_SLVRXPKTCNT_MASK 0x007F0000U
+#define SMB_SLVRXPKTCNT_SHIFT 16U
+
+#define SMB_SLVRXFIFOTHR_MASK 0x00003F00U
+#define SMB_SLVRXFIFOTHR_SHIFT 8U
+
+/* SMBUS Bit-bang mode control register */
+#define SMB_BITBANGCTL_REG 0x14U
+
+#define SMB_SMBCLKIN_MASK 0x80000000U
+#define SMB_SMBCLKIN_SHIFT 31U
+
+#define SMB_SMBCLKOUTEN_MASK 0x40000000U
+#define SMB_SMBCLKOUTEN_SHIFT 30U
+
+#define SMB_SMBDATAIN_MASK 0x20000000U
+#define SMB_SMBDATAIN_SHIFT 29U
+
+#define SMB_SMBDATAOUTEN_MASK 0x10000000U
+#define SMB_SMBDATAOUTEN_SHIFT 28U
+
+/* SMBUS Master command register */
+#define SMB_MSTRCMD_REG 0x30U
+
+#define SMB_MSTRSTARTBUSYCMD_MASK 0x80000000U
+#define SMB_MSTRSTARTBUSYCMD_SHIFT 31U
+
+#define SMB_MSTRABORT_MASK 0x40000000U
+#define SMB_MSTRABORT_SHIFT 30U
+
+#define SMB_MSTRSTS_MASK 0x0E000000U
+#define SMB_MSTRSTS_SHIFT 25U
+
+#define SMB_MSTRSMBUSPROTO_MASK 0x00001E00U
+#define SMB_MSTRSMBUSPROTO_SHIFT 9U
+
+#define SMB_MSTRPEC_MASK 0x00000100U
+#define SMB_MSTRPEC_SHIFT 8U
+
+#define SMB_MSTRRDBYTECNT_MASK 0x000000FFU
+#define SMB_MSTRRDBYTECNT_SHIFT 0U
+
+/* SMBUS Slave command register */
+#define SMB_SLVCMD_REG 0x34U
+
+#define SMB_SLVSTARTBUSYCMD_MASK 0x80000000U
+#define SMB_SLVSTARTBUSYCMD_SHIFT 31U
+
+#define SMB_SLVABORT_MASK 0x40000000U
+#define SMB_SLVABORT_SHIFT 30U
+
+#define SMB_SLVSTS_MASK 0x03800000U
+#define SMB_SLVSTS_SHIFT 23U
+
+#define SMB_SLVPEC_MASK 0x00000100U
+#define SMB_SLVPEC_SHIFT 8U
+
+/* SMBUS Event enable register */
+#define SMB_EVTEN_REG 0x38U
+
+#define SMB_MSTRRXFIFOFULLEN_MASK 0x80000000U
+#define SMB_MSTRRXFIFOFULLEN_SHIFT 31U
+
+#define SMB_MSTRRXFIFOTHRHITEN_MASK 0x40000000U
+#define SMB_MSTRRXFIFOTHRHITEN_SHIFT 30U
+
+#define SMB_MSTRRXEVTEN_MASK 0x20000000U
+#define SMB_MSTRRXEVTEN_SHIFT 29U
+
+#define SMB_MSTRSTARTBUSYEN_MASK 0x10000000U
+#define SMB_MSTRSTARTBUSYEN_SHIFT 28U
+
+#define SMB_MSTRTXUNDEN_MASK 0x08000000U
+#define SMB_MSTRTXUNDEN_SHIFT 27U
+
+#define SMB_SLVRXFIFOFULLEN_MASK 0x04000000U
+#define SMB_SLVRXFIFOFULLEN_SHIFT 26U
+
+#define SMB_SLVRXFIFOTHRHITEN_MASK 0x02000000U
+#define SMB_SLVRXFIFOTHRHITEN_SHIFT 25U
+
+#define SMB_SLVRXEVTEN_MASK 0x01000000U
+#define SMB_SLVRXEVTEN_SHIFT 24U
+
+#define SMB_SLVSTARTBUSYEN_MASK 0x00800000U
+#define SMB_SLVSTARTBUSYEN_SHIFT 23U
+
+#define SMB_SLVTXUNDEN_MASK 0x00400000U
+#define SMB_SLVTXUNDEN_SHIFT 22U
+
+#define SMB_SLVRDEVTEN_MASK 0x00200000U
+#define SMB_SLVRDEVTEN_SHIFT 21U
+
+/* SMBUS Event status register */
+#define SMB_EVTSTS_REG 0x3CU
+
+#define SMB_MSTRRXFIFOFULLSTS_MASK 0x80000000U
+#define SMB_MSTRRXFIFOFULLSTS_SHIFT 31U
+
+#define SMB_MSTRRXFIFOTHRHITSTS_MASK 0x40000000U
+#define SMB_MSTRRXFIFOTHRHITSTS_SHIFT 30U
+
+#define SMB_MSTRRXEVTSTS_MASK 0x20000000U
+#define SMB_MSTRRXEVTSTS_SHIFT 29U
+
+#define SMB_MSTRSTARTBUSYSTS_MASK 0x10000000U
+#define SMB_MSTRSTARTBUSYSTS_SHIFT 28U
+
+#define SMB_MSTRTXUNDSTS_MASK 0x08000000U
+#define SMB_MSTRTXUNDSTS_SHIFT 27U
+
+#define SMB_SLVRXFIFOFULLSTS_MASK 0x04000000U
+#define SMB_SLVRXFIFOFULLSTS_SHIFT 26U
+
+#define SMB_SLVRXFIFOTHRHITSTS_MASK 0x02000000U
+#define SMB_SLVRXFIFOTHRHITSTS_SHIFT 25U
+
+#define SMB_SLVRXEVTSTS_MASK 0x01000000U
+#define SMB_SLVRXEVTSTS_SHIFT 24U
+
+#define SMB_SLVSTARTBUSYSTS_MASK 0x00800000U
+#define SMB_SLVSTARTBUSYSTS_SHIFT 23U
+
+#define SMB_SLVTXUNDSTS_MASK 0x00400000U
+#define SMB_SLVTXUNDSTS_SHIFT 22U
+
+#define SMB_SLVRDEVTSTS_MASK 0x00200000U
+#define SMB_SLVRDEVTSTS_SHIFT 21U
+
+/* SMBUS Master data write register */
+#define SMB_MSTRDATAWR_REG 0x40U
+
+#define SMB_MSTRWRSTS_MASK 0x80000000U
+#define SMB_MSTRWRSTS_SHIFT 31U
+
+#define SMB_MSTRWRDATA_MASK 0x000000FFU
+#define SMB_MSTRWRDATA_SHIFT 0U
+
+/* SMBUS Master data read register */
+#define SMB_MSTRDATARD_REG 0x44U
+
+#define SMB_MSTRRDSTS_MASK 0xC0000000U
+#define SMB_MSTRRDSTS_SHIFT 30U
+
+#define SMB_MSTRRDPECERR_MASK 0x20000000U
+#define SMB_MSTRRDPECERR_SHIFT 29U
+
+#define SMB_MSTRRDDATA_MASK 0x000000FFU
+#define SMB_MSTRRDDATA_SHIFT 0U
+
+/* SMBUS Slave data write register */
+#define SMB_SLVDATAWR_REG 0x48U
+
+#define SMB_SLVWRSTS_MASK 0x80000000U
+#define SMB_SLVWRSTS_SHIFT 31U
+
+#define SMB_SLVWRDATA_MASK 0x000000FFU
+#define SMB_SLVWRDATA_SHIFT 0U
+
+/* SMBUS Slave data read register */
+#define SMB_SLVDATARD_REG 0x4CU
+
+#define SMB_SLVRDSTS_MASK 0xC0000000U
+#define SMB_SLVRDSTS_SHIFT 30U
+
+#define SMB_SLVRDERRSTS_MASK 0x30000000U
+#define SMB_SLVRDERRSTS_SHIFT 28U
+
+#define SMB_SLVRDDATA_MASK 0x000000FFU
+#define SMB_SLVRDDATA_SHIFT 0U
+
+#endif /* I2C_REGS */
diff --git a/include/drivers/brcm/mdio/mdio.h b/include/drivers/brcm/mdio/mdio.h
new file mode 100644
index 0000000..b27c7b3
--- /dev/null
+++ b/include/drivers/brcm/mdio/mdio.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2016 - 2021, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MDIO_H
+#define MDIO_H
+
+#define CMIC_MIIM_PARAM (PLAT_CMIC_MIIM_BASE + 0x23cU)
+#define MDIO_PARAM_MIIM_CYCLE 29U
+#define MDIO_PARAM_INTERNAL_SEL 25U
+#define MDIO_PARAM_BUSID 22U
+#define MDIO_PARAM_BUSID_MASK 0x7U
+#define MDIO_PARAM_C45_SEL 21U
+#define MDIO_PARAM_PHYID 16U
+#define MDIO_PARAM_PHYID_MASK 0x1FU
+#define MDIO_PARAM_DATA 0U
+#define MDIO_PARAM_DATA_MASK 0xFFFFU
+#define CMIC_MIIM_READ_DATA (PLAT_CMIC_MIIM_BASE + 0x240U)
+#define MDIO_READ_DATA_MASK 0xffffU
+#define CMIC_MIIM_ADDRESS (PLAT_CMIC_MIIM_BASE + 0x244U)
+#define CMIC_MIIM_CTRL (PLAT_CMIC_MIIM_BASE + 0x248U)
+#define MDIO_CTRL_WRITE_OP 0x1U
+#define MDIO_CTRL_READ_OP 0x2U
+#define CMIC_MIIM_STAT (PLAT_CMIC_MIIM_BASE + 0x24cU)
+#define MDIO_STAT_DONE 1U
+
+int mdio_write(uint16_t busid, uint16_t phyid, uint32_t reg, uint16_t val);
+int mdio_read(uint16_t busid, uint16_t phyid, uint32_t reg);
+#endif /* MDIO_H */
diff --git a/include/drivers/brcm/usbh_xhci_regs.h b/include/drivers/brcm/usbh_xhci_regs.h
new file mode 100644
index 0000000..93dec7b
--- /dev/null
+++ b/include/drivers/brcm/usbh_xhci_regs.h
@@ -0,0 +1,4809 @@
+/*
+ * Copyright (c) 2017 - 2021, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef USBH_XHCI_REGS_H
+#define USBH_XHCI_REGS_H
+
+#include <lib/mmio.h>
+#include <platform_def.h>
+
+#define XHCI_LEN (8096U)
+
+#define XHC_CPLIVER_OFFSET 0x000U
+#define XHC_SPARAMS1_OFFSET 0x004U
+#define XHC_SPARAMS2_OFFSET 0x008U
+#define XHC_SPARAMS3_OFFSET 0x00cU
+#define XHC_CPARAMS1_OFFSET 0x010U
+#define XHC_DBOFF_OFFSET 0x014U
+#define XHC_RTOFF_OFFSET 0x018U
+#define XHC_CPARAMS2_OFFSET 0x01cU
+#define XHC_USBCMD_OFFSET 0x020U
+#define XHC_USBSTS_OFFSET 0x024U
+#define XHC_PAGESIZE_OFFSET 0x028U
+#define XHC_DNCTRL_OFFSET 0x034U
+#define XHC_CRCRL_OFFSET 0x038U
+#define XHC_CRCRH_OFFSET 0x03cU
+#define XHC_DCBAAPL_OFFSET 0x050U
+#define XHC_DCBAAPH_OFFSET 0x054U
+#define XHC_CONFIG_OFFSET 0x058U
+#define XHC_PORTSC1_OFFSET 0x420U
+#define XHC_PORTPM1_OFFSET 0x424U
+#define XHC_PORTLC1_OFFSET 0x428U
+#define XHC_PORTSC2_OFFSET 0x430U
+#define XHC_PORTPM2_OFFSET 0x434U
+#define XHC_PORTLC2_OFFSET 0x43cU
+#define XHC_PORTSC3_OFFSET 0x440U
+#define XHC_PORTPM3_OFFSET 0x444U
+#define XHC_PORTLI3_OFFSET 0x44cU
+#define XHC_MFINDEX_OFFSET 0x4a0U
+#define XHC_IMAN0_OFFSET 0x4c0U
+#define XHC_IMOD0_OFFSET 0x4c4U
+#define XHC_ERSTSZ0_OFFSET 0x4c8U
+#define XHC_ERSTBAL0_OFFSET 0x4d0U
+#define XHC_ERSTBAH0_OFFSET 0x4d4U
+#define XHC_ERDPL0_OFFSET 0x4d8U
+#define XHC_ERDPH0_OFFSET 0x4dcU
+#define XHC_IMAN1_OFFSET 0x4e0U
+#define XHC_IMOD1_OFFSET 0x4e4U
+#define XHC_ERSTSZ1_OFFSET 0x4e8U
+#define XHC_ERSTBAL1_OFFSET 0x4f0U
+#define XHC_ERSTBAH1_OFFSET 0x4f4U
+#define XHC_ERDPL1_OFFSET 0x4f8U
+#define XHC_ERDPH1_OFFSET 0x4fcU
+#define XHC_DBLCMD_OFFSET 0x8c0U
+#define XHC_DBLDVX1_OFFSET 0x8c4U
+#define XHC_DBLDVX2_OFFSET 0x8c8U
+#define XHC_DBLDVX3_OFFSET 0x8ccU
+#define XHC_DBLDVX4_OFFSET 0x8d0U
+#define XHC_DBLDVX5_OFFSET 0x8d4U
+#define XHC_DBLDVX6_OFFSET 0x8d8U
+#define XHC_DBLDVX7_OFFSET 0x8dcU
+#define XHC_DBLDVX8_OFFSET 0x8e0U
+#define XHC_DBLDVX9_OFFSET 0x8e4U
+#define XHC_DBLDVX10_OFFSET 0x8e8U
+#define XHC_DBLDVX11_OFFSET 0x8ecU
+#define XHC_DBLDVX12_OFFSET 0x8f0U
+#define XHC_DBLDVX13_OFFSET 0x8f4U
+#define XHC_DBLDVX14_OFFSET 0x8f8U
+#define XHC_DBLDVX15_OFFSET 0x8fcU
+#define XHC_DBLDVX16_OFFSET 0x900U
+#define XHC_ECHSPT3_OFFSET 0x940U
+#define XHC_PNSTR3_OFFSET 0x944U
+#define XHC_PSUM3_OFFSET 0x948U
+#define XHC_PTSLTYP3_OFFSET 0x94cU
+#define XHC_ECHSPT2_OFFSET 0x950U
+#define XHC_PNSTR2_OFFSET 0x954U
+#define XHC_PSUM2_OFFSET 0x958U
+#define XHC_PTSLTYP2_OFFSET 0x95cU
+#define XHC_ECHRSVP_OFFSET 0x960U
+#define XHC_ECHRSVI_OFFSET 0x968U
+#define XHC_ECHRSVM_OFFSET 0xae8U
+#define XHC_ECHRSVD_OFFSET 0xaf8U
+#define XHC_ECHRSVO_OFFSET 0xb38U
+#define XHC_ECHCTT_OFFSET 0xbf0U
+#define XHC_CTTMTS0_OFFSET 0xbf8U
+#define XHC_CTTMTS1_OFFSET 0xbfcU
+#define XHC_ECHBIU_OFFSET 0xc00U
+#define XHC_BIUSPC_OFFSET 0xc04U
+#define XHC_AXIWRA_OFFSET 0xc08U
+#define XHC_AXIRDA_OFFSET 0xc0cU
+#define XHC_AXILPM_OFFSET 0xc10U
+#define XHC_AXIQOS_OFFSET 0xc14U
+#define XHC_ECHCSR_OFFSET 0xc20U
+#define XHC_CSRSPC_OFFSET 0xc24U
+#define XHC_ECHAIU_OFFSET 0xc30U
+#define XHC_AIUDMA_OFFSET 0xc34U
+#define XHC_AIUFLA_OFFSET 0xc38U
+#define XHC_AIUCFG_OFFSET 0xc3cU
+#define XHC_ECHFSC_OFFSET 0xc40U
+#define XHC_FSCPOC_OFFSET 0xc54U
+#define XHC_FSCGOC_OFFSET 0xc58U
+#define XHC_FSCNOC_OFFSET 0xc5cU
+#define XHC_FSCAIC_OFFSET 0xc60U
+#define XHC_FSCPIC_OFFSET 0xc64U
+#define XHC_FSCGIC_OFFSET 0xc68U
+#define XHC_FSCNIC_OFFSET 0xc6cU
+#define XHC_ECHPRT_OFFSET 0xc70U
+#define XHC_PRTHSC_OFFSET 0xc78U
+#define XHC_PRTHSR_OFFSET 0xc7cU
+#define XHC_ECHRHS_OFFSET 0xc80U
+#define XHC_RHSDES_OFFSET 0xc84U
+#define XHC_RHSHSC0_OFFSET 0xc90U
+#define XHC_RHSHSR0_OFFSET 0xc94U
+#define XHC_RHSHSC1_OFFSET 0xc98U
+#define XHC_RHSHSR1_OFFSET 0xc9cU
+#define XHC_RHSHSC2_OFFSET 0xca0U
+#define XHC_RHSHSR2_OFFSET 0xca4U
+#define XHC_RHSHSC3_OFFSET 0xca8U
+#define XHC_RHSHSR3_OFFSET 0xcacU
+#define XHC_ECHSSP_OFFSET 0xcb0U
+#define XHC_SSPVER_OFFSET 0xcb4U
+#define XHC_SSPMGN_OFFSET 0xcb8U
+#define XHC_ECHFSC2_OFFSET 0xcc0U
+#define XHC_FSC2POC_OFFSET 0xcd4U
+#define XHC_FSC2GOC_OFFSET 0xcd8U
+#define XHC_FSC2NOC_OFFSET 0xcdcU
+#define XHC_FSC2AIC_OFFSET 0xce0U
+#define XHC_FSC2PIC_OFFSET 0xce4U
+#define XHC_FSC2GIC_OFFSET 0xce8U
+#define XHC_FSC2NIC_OFFSET 0xcecU
+#define XHC_ECHPRT2_OFFSET 0xcf0U
+#define XHC_PRT2HSC_OFFSET 0xcf8U
+#define XHC_PRT2HSR_OFFSET 0xcfcU
+#define XHC_ECHRH2_OFFSET 0xd00U
+#define XHC_RH2DES_OFFSET 0xd04U
+#define XHC_RH2HSC0_OFFSET 0xd10U
+#define XHC_RH2HSR0_OFFSET 0xd14U
+#define XHC_RH2HSC1_OFFSET 0xd18U
+#define XHC_RH2HSR1_OFFSET 0xd1cU
+#define XHC_RH2HSC2_OFFSET 0xd20U
+#define XHC_RH2HSR2_OFFSET 0xd24U
+#define XHC_RH2HSC3_OFFSET 0xd28U
+#define XHC_RH2HSR3_OFFSET 0xd2cU
+#define XHC_ECHU2P_OFFSET 0xd30U
+#define XHC_U2PVER_OFFSET 0xd34U
+#define XHC_U2PMGN_OFFSET 0xd38U
+#define XHC_ECHRSV2_OFFSET 0xd40U
+#define XHC_ECHIRA_OFFSET 0xf90U
+#define XHC_IRAADR_OFFSET 0xf98U
+#define XHC_IRADAT_OFFSET 0xf9cU
+#define XHC_ECHHST_OFFSET 0xfa0U
+#define XHC_HSTDBG_OFFSET 0xfa4U
+#define XHC_HSTNPL_OFFSET 0xfa8U
+#define XHC_HSTNPH_OFFSET 0xfacU
+#define XHC_ECHRBV_OFFSET 0xfb0U
+#define XHC_RBVPDT_OFFSET 0xfb4U
+#define XHC_RBVMGN_OFFSET 0xfbcU
+
+#define XHC_CPLIVER_BASE 0x000U
+#define XHC_CPLIVER__IVH_L 31U
+#define XHC_CPLIVER__IVH_R 24U
+#define XHC_CPLIVER__IVH_WIDTH 8U
+#define XHC_CPLIVER__IVH_RESETVALUE 0x01U
+#define XHC_CPLIVER__IVL_L 23U
+#define XHC_CPLIVER__IVL_R 16U
+#define XHC_CPLIVER__IVL_WIDTH 8U
+#define XHC_CPLIVER__IVL_RESETVALUE 0x10U
+#define XHC_CPLIVER__reserved_L 15U
+#define XHC_CPLIVER__reserved_R 8U
+#define XHC_CPLIVER__reserved_WIDTH 8U
+#define XHC_CPLIVER__reserved_RESETVALUE 0x00U
+#define XHC_CPLIVER__CPL_L 7U
+#define XHC_CPLIVER__CPL_R 0U
+#define XHC_CPLIVER__CPL_WIDTH 8U
+#define XHC_CPLIVER__CPL_RESETVALUE 0x00U
+#define XHC_CPLIVER_WIDTH 32U
+#define XHC_CPLIVER__WIDTH 32U
+#define XHC_CPLIVER_ALL_L 31U
+#define XHC_CPLIVER_ALL_R 0U
+#define XHC_CPLIVER__ALL_L 31U
+#define XHC_CPLIVER__ALL_R 0U
+#define XHC_CPLIVER_DATAMASK 0xffffffffU
+#define XHC_CPLIVER_RDWRMASK 0x00000000U
+#define XHC_CPLIVER_RESETVALUE 0x01100000U
+
+#define XHC_SPARAMS1_OFFSET 0x004U
+#define XHC_SPARAMS1_BASE 0x004U
+#define XHC_SPARAMS1__NPTS_L 31U
+#define XHC_SPARAMS1__NPTS_R 24U
+#define XHC_SPARAMS1__NPTS_WIDTH 8U
+#define XHC_SPARAMS1__NPTS_RESETVALUE 0x00U
+#define XHC_SPARAMS1__reserved_L 23U
+#define XHC_SPARAMS1__reserved_R 19U
+#define XHC_SPARAMS1__reserved_WIDTH 5U
+#define XHC_SPARAMS1__reserved_RESETVALUE 0x0U
+#define XHC_SPARAMS1__MITS_L 18U
+#define XHC_SPARAMS1__MITS_R 8U
+#define XHC_SPARAMS1__MITS_WIDTH 11U
+#define XHC_SPARAMS1__MITS_RESETVALUE 0x1U
+#define XHC_SPARAMS1__MSLS_L 7U
+#define XHC_SPARAMS1__MSLS_R 0U
+#define XHC_SPARAMS1__MSLS_WIDTH 8U
+#define XHC_SPARAMS1__MSLS_RESETVALUE 0x00U
+#define XHC_SPARAMS1_WIDTH 32U
+#define XHC_SPARAMS1__WIDTH 32U
+#define XHC_SPARAMS1_ALL_L 31U
+#define XHC_SPARAMS1_ALL_R 0U
+#define XHC_SPARAMS1__ALL_L 31U
+#define XHC_SPARAMS1__ALL_R 0U
+#define XHC_SPARAMS1_DATAMASK 0xffffffffU
+#define XHC_SPARAMS1_RDWRMASK 0x00000000U
+#define XHC_SPARAMS1_RESETVALUE 0x00000100U
+
+#define XHC_SPARAMS2_OFFSET 0x008U
+#define XHC_SPARAMS2_BASE 0x008U
+#define XHC_SPARAMS2__MSPBSL_L 31U
+#define XHC_SPARAMS2__MSPBSL_R 27U
+#define XHC_SPARAMS2__MSPBSL_WIDTH 5U
+#define XHC_SPARAMS2__MSPBSL_RESETVALUE 0x0U
+#define XHC_SPARAMS2__SPR 26U
+#define XHC_SPARAMS2__SPR_L 26U
+#define XHC_SPARAMS2__SPR_R 26U
+#define XHC_SPARAMS2__SPR_WIDTH 1U
+#define XHC_SPARAMS2__SPR_RESETVALUE 0x1U
+#define XHC_SPARAMS2__MSPBSH_L 25U
+#define XHC_SPARAMS2__MSPBSH_R 21U
+#define XHC_SPARAMS2__MSPBSH_WIDTH 5U
+#define XHC_SPARAMS2__MSPBSH_RESETVALUE 0x0U
+#define XHC_SPARAMS2__reserved_L 20U
+#define XHC_SPARAMS2__reserved_R 8U
+#define XHC_SPARAMS2__reserved_WIDTH 13U
+#define XHC_SPARAMS2__reserved_RESETVALUE 0x0U
+#define XHC_SPARAMS2__MERST_L 7U
+#define XHC_SPARAMS2__MERST_R 4U
+#define XHC_SPARAMS2__MERST_WIDTH 4U
+#define XHC_SPARAMS2__MERST_RESETVALUE 0x0U
+#define XHC_SPARAMS2__IST_L 3U
+#define XHC_SPARAMS2__IST_R 0U
+#define XHC_SPARAMS2__IST_WIDTH 4U
+#define XHC_SPARAMS2__IST_RESETVALUE 0x0U
+#define XHC_SPARAMS2_WIDTH 32U
+#define XHC_SPARAMS2__WIDTH 32U
+#define XHC_SPARAMS2_ALL_L 31U
+#define XHC_SPARAMS2_ALL_R 0U
+#define XHC_SPARAMS2__ALL_L 31U
+#define XHC_SPARAMS2__ALL_R 0U
+#define XHC_SPARAMS2_DATAMASK 0xffffffffU
+#define XHC_SPARAMS2_RDWRMASK 0x00000000U
+#define XHC_SPARAMS2_RESETVALUE 0x04000000U
+
+#define XHC_SPARAMS3_OFFSET 0x00cU
+#define XHC_SPARAMS3_BASE 0x00cU
+#define XHC_SPARAMS3__U2L_L 31U
+#define XHC_SPARAMS3__U2L_R 16U
+#define XHC_SPARAMS3__U2L_WIDTH 16U
+#define XHC_SPARAMS3__U2L_RESETVALUE 0x0000U
+#define XHC_SPARAMS3__reserved_L 15U
+#define XHC_SPARAMS3__reserved_R 8U
+#define XHC_SPARAMS3__reserved_WIDTH 8U
+#define XHC_SPARAMS3__reserved_RESETVALUE 0x00U
+#define XHC_SPARAMS3__U1L_L 7U
+#define XHC_SPARAMS3__U1L_R 0U
+#define XHC_SPARAMS3__U1L_WIDTH 8U
+#define XHC_SPARAMS3__U1L_RESETVALUE 0x00U
+#define XHC_SPARAMS3_WIDTH 32U
+#define XHC_SPARAMS3__WIDTH 32U
+#define XHC_SPARAMS3_ALL_L 31U
+#define XHC_SPARAMS3_ALL_R 0U
+#define XHC_SPARAMS3__ALL_L 31U
+#define XHC_SPARAMS3__ALL_R 0U
+#define XHC_SPARAMS3_DATAMASK 0xffffffffU
+#define XHC_SPARAMS3_RDWRMASK 0x00000000U
+#define XHC_SPARAMS3_RESETVALUE 0x00000000U
+
+#define XHC_CPARAMS1_OFFSET 0x010U
+#define XHC_CPARAMS1_BASE 0x010U
+#define XHC_CPARAMS1__XECP_L 31U
+#define XHC_CPARAMS1__XECP_R 16U
+#define XHC_CPARAMS1__XECP_WIDTH 16U
+#define XHC_CPARAMS1__XECP_RESETVALUE 0x0000U
+#define XHC_CPARAMS1__MPSA_L 15U
+#define XHC_CPARAMS1__MPSA_R 12U
+#define XHC_CPARAMS1__MPSA_WIDTH 4U
+#define XHC_CPARAMS1__MPSA_RESETVALUE 0x0U
+#define XHC_CPARAMS1__CFC 11U
+#define XHC_CPARAMS1__CFC_L 11U
+#define XHC_CPARAMS1__CFC_R 11U
+#define XHC_CPARAMS1__CFC_WIDTH 1U
+#define XHC_CPARAMS1__CFC_RESETVALUE 0x0U
+#define XHC_CPARAMS1__SEC 10U
+#define XHC_CPARAMS1__SEC_L 10U
+#define XHC_CPARAMS1__SEC_R 10U
+#define XHC_CPARAMS1__SEC_WIDTH 1U
+#define XHC_CPARAMS1__SEC_RESETVALUE 0x0U
+#define XHC_CPARAMS1__SPC 9U
+#define XHC_CPARAMS1__SPC_L 9U
+#define XHC_CPARAMS1__SPC_R 9U
+#define XHC_CPARAMS1__SPC_WIDTH 1U
+#define XHC_CPARAMS1__SPC_RESETVALUE 0x0U
+#define XHC_CPARAMS1__PAE 8U
+#define XHC_CPARAMS1__PAE_L 8U
+#define XHC_CPARAMS1__PAE_R 8U
+#define XHC_CPARAMS1__PAE_WIDTH 1U
+#define XHC_CPARAMS1__PAE_RESETVALUE 0x1U
+#define XHC_CPARAMS1__NSS 7U
+#define XHC_CPARAMS1__NSS_L 7U
+#define XHC_CPARAMS1__NSS_R 7U
+#define XHC_CPARAMS1__NSS_WIDTH 1U
+#define XHC_CPARAMS1__NSS_RESETVALUE 0x0U
+#define XHC_CPARAMS1__LTC 6U
+#define XHC_CPARAMS1__LTC_L 6U
+#define XHC_CPARAMS1__LTC_R 6U
+#define XHC_CPARAMS1__LTC_WIDTH 1U
+#define XHC_CPARAMS1__LTC_RESETVALUE 0x1U
+#define XHC_CPARAMS1__LRC 5U
+#define XHC_CPARAMS1__LRC_L 5U
+#define XHC_CPARAMS1__LRC_R 5U
+#define XHC_CPARAMS1__LRC_WIDTH 1U
+#define XHC_CPARAMS1__LRC_RESETVALUE 0x0U
+#define XHC_CPARAMS1__PIND 4U
+#define XHC_CPARAMS1__PIND_L 4U
+#define XHC_CPARAMS1__PIND_R 4U
+#define XHC_CPARAMS1__PIND_WIDTH 1U
+#define XHC_CPARAMS1__PIND_RESETVALUE 0x0U
+
+#define XHC_CPARAMS1__PPC_L 3U
+#define XHC_CPARAMS1__PPC_R 3U
+#define XHC_CPARAMS1__PPC_WIDTH 1U
+#define XHC_CPARAMS1__PPC_RESETVALUE 0x0U
+#define XHC_CPARAMS1__CSZ 2U
+#define XHC_CPARAMS1__CSZ_L 2U
+#define XHC_CPARAMS1__CSZ_R 2U
+#define XHC_CPARAMS1__CSZ_WIDTH 1U
+#define XHC_CPARAMS1__CSZ_RESETVALUE 0x1U
+#define XHC_CPARAMS1__BNC 1U
+#define XHC_CPARAMS1__BNC_L 1U
+#define XHC_CPARAMS1__BNC_R 1U
+#define XHC_CPARAMS1__BNC_WIDTH 1U
+#define XHC_CPARAMS1__BNC_RESETVALUE 0x0U
+#define XHC_CPARAMS1__AC64 0U
+#define XHC_CPARAMS1__AC64_L 0U
+#define XHC_CPARAMS1__AC64_R 0U
+#define XHC_CPARAMS1__AC64_WIDTH 1U
+#define XHC_CPARAMS1__AC64_RESETVALUE 0x0U
+#define XHC_CPARAMS1_WIDTH 32U
+#define XHC_CPARAMS1__WIDTH 32U
+#define XHC_CPARAMS1_ALL_L 31U
+#define XHC_CPARAMS1_ALL_R 0U
+#define XHC_CPARAMS1__ALL_L 31U
+#define XHC_CPARAMS1__ALL_R 0U
+#define XHC_CPARAMS1_DATAMASK 0xffffffffU
+#define XHC_CPARAMS1_RDWRMASK 0x00000000U
+#define XHC_CPARAMS1_RESETVALUE 0x00000144U
+
+#define XHC_DBOFF_OFFSET 0x014U
+#define XHC_DBOFF_BASE 0x014U
+#define XHC_DBOFF__DBO_L 15U
+#define XHC_DBOFF__DBO_R 2U
+#define XHC_DBOFF__DBO_WIDTH 14U
+#define XHC_DBOFF__DBO_RESETVALUE 0x0U
+#define XHC_DBOFF__reserved_L 1U
+#define XHC_DBOFF__reserved_R 0U
+#define XHC_DBOFF__reserved_WIDTH 2U
+#define XHC_DBOFF__reserved_RESETVALUE 0x0U
+#define XHC_DBOFF__RESERVED_L 31U
+#define XHC_DBOFF__RESERVED_R 16U
+#define XHC_DBOFF_WIDTH 16U
+#define XHC_DBOFF__WIDTH 16U
+#define XHC_DBOFF_ALL_L 15U
+#define XHC_DBOFF_ALL_R 0U
+#define XHC_DBOFF__ALL_L 15U
+#define XHC_DBOFF__ALL_R 0U
+#define XHC_DBOFF_DATAMASK 0x0000ffffU
+#define XHC_DBOFF_RDWRMASK 0xffff0000U
+#define XHC_DBOFF_RESETVALUE 0x0000U
+
+#define XHC_RTOFF_OFFSET 0x018U
+#define XHC_RTOFF_BASE 0x018U
+#define XHC_RTOFF__RTO_L 15U
+#define XHC_RTOFF__RTO_R 5U
+#define XHC_RTOFF__RTO_WIDTH 11U
+#define XHC_RTOFF__RTO_RESETVALUE 0x0U
+#define XHC_RTOFF__reserved_L 4U
+#define XHC_RTOFF__reserved_R 0U
+#define XHC_RTOFF__reserved_WIDTH 5U
+#define XHC_RTOFF__reserved_RESETVALUE 0x0U
+#define XHC_RTOFF__RESERVED_L 31U
+#define XHC_RTOFF__RESERVED_R 16U
+#define XHC_RTOFF_WIDTH 16U
+#define XHC_RTOFF__WIDTH 16U
+#define XHC_RTOFF_ALL_L 15U
+#define XHC_RTOFF_ALL_R 0U
+#define XHC_RTOFF__ALL_L 15U
+#define XHC_RTOFF__ALL_R 0U
+#define XHC_RTOFF_DATAMASK 0x0000ffffU
+#define XHC_RTOFF_RDWRMASK 0xffff0000U
+#define XHC_RTOFF_RESETVALUE 0x0000U
+
+#define XHC_CPARAMS2_OFFSET 0x01cU
+#define XHC_CPARAMS2_BASE 0x01cU
+#define XHC_CPARAMS2__reserved_L 31U
+#define XHC_CPARAMS2__reserved_R 6U
+#define XHC_CPARAMS2__reserved_WIDTH 26U
+#define XHC_CPARAMS2__reserved_RESETVALUE 0x0U
+#define XHC_CPARAMS2__CIC 5U
+#define XHC_CPARAMS2__CIC_L 5U
+#define XHC_CPARAMS2__CIC_R 5U
+#define XHC_CPARAMS2__CIC_WIDTH 1U
+#define XHC_CPARAMS2__CIC_RESETVALUE 0x0U
+#define XHC_CPARAMS2__LEC 4U
+#define XHC_CPARAMS2__LEC_L 4U
+#define XHC_CPARAMS2__LEC_R 4U
+#define XHC_CPARAMS2__LEC_WIDTH 1U
+#define XHC_CPARAMS2__LEC_RESETVALUE 0x0U
+#define XHC_CPARAMS2__CTC 3U
+#define XHC_CPARAMS2__CTC_L 3U
+#define XHC_CPARAMS2__CTC_R 3U
+#define XHC_CPARAMS2__CTC_WIDTH 1U
+#define XHC_CPARAMS2__CTC_RESETVALUE 0x0U
+#define XHC_CPARAMS2__FSC 2U
+#define XHC_CPARAMS2__FSC_L 2U
+#define XHC_CPARAMS2__FSC_R 2U
+#define XHC_CPARAMS2__FSC_WIDTH 1U
+#define XHC_CPARAMS2__FSC_RESETVALUE 0x0U
+#define XHC_CPARAMS2__CMC 1U
+#define XHC_CPARAMS2__CMC_L 1U
+#define XHC_CPARAMS2__CMC_R 1U
+#define XHC_CPARAMS2__CMC_WIDTH 1U
+#define XHC_CPARAMS2__CMC_RESETVALUE 0x0U
+#define XHC_CPARAMS2__U3C 0U
+#define XHC_CPARAMS2__U3C_L 0U
+#define XHC_CPARAMS2__U3C_R 0U
+#define XHC_CPARAMS2__U3C_WIDTH 1U
+#define XHC_CPARAMS2__U3C_RESETVALUE 0x0U
+#define XHC_CPARAMS2_WIDTH 32U
+#define XHC_CPARAMS2__WIDTH 32U
+#define XHC_CPARAMS2_ALL_L 31U
+#define XHC_CPARAMS2_ALL_R 0U
+#define XHC_CPARAMS2__ALL_L 31U
+#define XHC_CPARAMS2__ALL_R 0U
+#define XHC_CPARAMS2_DATAMASK 0xffffffffU
+#define XHC_CPARAMS2_RDWRMASK 0x00000000U
+#define XHC_CPARAMS2_RESETVALUE 0x00000000U
+
+#define XHC_USBCMD_OFFSET 0x020U
+#define XHC_USBCMD_BASE 0x020U
+#define XHC_USBCMD__CME 13U
+#define XHC_USBCMD__CME_L 13U
+#define XHC_USBCMD__CME_R 13U
+#define XHC_USBCMD__CME_WIDTH 1U
+#define XHC_USBCMD__CME_RESETVALUE 0x0U
+#define XHC_USBCMD__SPE 12U
+#define XHC_USBCMD__SPE_L 12U
+#define XHC_USBCMD__SPE_R 12U
+#define XHC_USBCMD__SPE_WIDTH 1U
+#define XHC_USBCMD__SPE_RESETVALUE 0x0U
+#define XHC_USBCMD__EU3S 11U
+#define XHC_USBCMD__EU3S_L 11U
+#define XHC_USBCMD__EU3S_R 11U
+#define XHC_USBCMD__EU3S_WIDTH 1U
+#define XHC_USBCMD__EU3S_RESETVALUE 0x0U
+#define XHC_USBCMD__EWE 10U
+#define XHC_USBCMD__EWE_L 10U
+#define XHC_USBCMD__EWE_R 10U
+#define XHC_USBCMD__EWE_WIDTH 1U
+#define XHC_USBCMD__EWE_RESETVALUE 0x0U
+#define XHC_USBCMD__CRS 9U
+#define XHC_USBCMD__CRS_L 9U
+#define XHC_USBCMD__CRS_R 9U
+#define XHC_USBCMD__CRS_WIDTH 1U
+#define XHC_USBCMD__CRS_RESETVALUE 0x0U
+#define XHC_USBCMD__CSS 8U
+#define XHC_USBCMD__CSS_L 8U
+#define XHC_USBCMD__CSS_R 8U
+#define XHC_USBCMD__CSS_WIDTH 1U
+#define XHC_USBCMD__CSS_RESETVALUE 0x0U
+#define XHC_USBCMD__LRST 7U
+#define XHC_USBCMD__LRST_L 7U
+#define XHC_USBCMD__LRST_R 7U
+#define XHC_USBCMD__LRST_WIDTH 1U
+#define XHC_USBCMD__LRST_RESETVALUE 0x0U
+#define XHC_USBCMD__reserved_L 6U
+#define XHC_USBCMD__reserved_R 4U
+#define XHC_USBCMD__reserved_WIDTH 3U
+#define XHC_USBCMD__reserved_RESETVALUE 0x0U
+#define XHC_USBCMD__HSEE 3U
+#define XHC_USBCMD__HSEE_L 3U
+#define XHC_USBCMD__HSEE_R 3U
+#define XHC_USBCMD__HSEE_WIDTH 1U
+#define XHC_USBCMD__HSEE_RESETVALUE 0x0U
+#define XHC_USBCMD__INTE 2U
+#define XHC_USBCMD__INTE_L 2U
+#define XHC_USBCMD__INTE_R 2U
+#define XHC_USBCMD__INTE_WIDTH 1U
+#define XHC_USBCMD__INTE_RESETVALUE 0x0U
+#define XHC_USBCMD__RST 1U
+#define XHC_USBCMD__RST_L 1U
+#define XHC_USBCMD__RST_R 1U
+#define XHC_USBCMD__RST_WIDTH 1U
+#define XHC_USBCMD__RST_RESETVALUE 0x0U
+#define XHC_USBCMD__RS 0U
+#define XHC_USBCMD__RS_L 0U
+#define XHC_USBCMD__RS_R 0U
+#define XHC_USBCMD__RS_WIDTH 1U
+#define XHC_USBCMD__RS_RESETVALUE 0x0U
+#define XHC_USBCMD__RESERVED_L 31U
+#define XHC_USBCMD__RESERVED_R 14U
+#define XHC_USBCMD_WIDTH 14U
+#define XHC_USBCMD__WIDTH 14U
+#define XHC_USBCMD_ALL_L 13U
+#define XHC_USBCMD_ALL_R 0U
+#define XHC_USBCMD__ALL_L 13U
+#define XHC_USBCMD__ALL_R 0U
+#define XHC_USBCMD_DATAMASK 0x00003fffU
+#define XHC_USBCMD_RDWRMASK 0xffffc000U
+#define XHC_USBCMD_RESETVALUE 0x0000U
+
+#define XHC_USBSTS_OFFSET 0x024U
+#define XHC_USBSTS_BASE 0x024U
+#define XHC_USBSTS__CE 12U
+#define XHC_USBSTS__CE_L 12U
+#define XHC_USBSTS__CE_R 12U
+#define XHC_USBSTS__CE_WIDTH 1U
+#define XHC_USBSTS__CE_RESETVALUE 0x0U
+#define XHC_USBSTS__CNR 11U
+#define XHC_USBSTS__CNR_L 11U
+#define XHC_USBSTS__CNR_R 11U
+#define XHC_USBSTS__CNR_WIDTH 1U
+#define XHC_USBSTS__CNR_RESETVALUE 0x1U
+
+#define XHC_USBSTS__SRE 10U
+#define XHC_USBSTS__SRE_L 10U
+#define XHC_USBSTS__SRE_R 10U
+#define XHC_USBSTS__SRE_WIDTH 1U
+#define XHC_USBSTS__SRE_RESETVALUE 0x0U
+#define XHC_USBSTS__RSS 9U
+#define XHC_USBSTS__RSS_L 9U
+#define XHC_USBSTS__RSS_R 9U
+#define XHC_USBSTS__RSS_WIDTH 1U
+#define XHC_USBSTS__RSS_RESETVALUE 0x0U
+#define XHC_USBSTS__SSS 8U
+#define XHC_USBSTS__SSS_L 8U
+#define XHC_USBSTS__SSS_R 8U
+#define XHC_USBSTS__SSS_WIDTH 1U
+#define XHC_USBSTS__SSS_RESETVALUE 0x0U
+#define XHC_USBSTS__PCD 4U
+#define XHC_USBSTS__PCD_L 4U
+#define XHC_USBSTS__PCD_R 4U
+#define XHC_USBSTS__PCD_WIDTH 1U
+#define XHC_USBSTS__PCD_RESETVALUE 0x0U
+#define XHC_USBSTS__EINT 3U
+#define XHC_USBSTS__EINT_L 3U
+#define XHC_USBSTS__EINT_R 3U
+#define XHC_USBSTS__EINT_WIDTH 1U
+#define XHC_USBSTS__EINT_RESETVALUE 0x0U
+#define XHC_USBSTS__HSE 2U
+#define XHC_USBSTS__HSE_L 2U
+#define XHC_USBSTS__HSE_R 2U
+#define XHC_USBSTS__HSE_WIDTH 1U
+#define XHC_USBSTS__HSE_RESETVALUE 0x0U
+#define XHC_USBSTS__reserved 1U
+#define XHC_USBSTS__reserved_L 1U
+#define XHC_USBSTS__reserved_R 1U
+#define XHC_USBSTS__reserved_WIDTH 1U
+#define XHC_USBSTS__reserved_RESETVALUE 0x0U
+
+#define XHC_USBSTS__CH_L 0U
+#define XHC_USBSTS__CH_R 0U
+#define XHC_USBSTS__CH_WIDTH 1U
+#define XHC_USBSTS__CH_RESETVALUE 0x1U
+#define XHC_USBSTS__RESERVED_L 31U
+#define XHC_USBSTS__RESERVED_R 13U
+#define XHC_USBSTS_WIDTH 13U
+#define XHC_USBSTS__WIDTH 13U
+#define XHC_USBSTS_ALL_L 12U
+#define XHC_USBSTS_ALL_R 0U
+#define XHC_USBSTS__ALL_L 12U
+#define XHC_USBSTS__ALL_R 0U
+#define XHC_USBSTS_DATAMASK 0x00001f1fU
+#define XHC_USBSTS_RDWRMASK 0xffffe0e0U
+#define XHC_USBSTS_RESETVALUE 0x0801U
+
+#define XHC_PAGESIZE_OFFSET 0x028U
+#define XHC_PAGESIZE_BASE 0x028U
+#define XHC_PAGESIZE__reserved_L 31U
+#define XHC_PAGESIZE__reserved_R 16U
+#define XHC_PAGESIZE__reserved_WIDTH 16U
+#define XHC_PAGESIZE__reserved_RESETVALUE 0x0000U
+#define XHC_PAGESIZE__PS_L 15U
+#define XHC_PAGESIZE__PS_R 0U
+#define XHC_PAGESIZE__PS_WIDTH 16U
+#define XHC_PAGESIZE__PS_RESETVALUE 0x0000U
+#define XHC_PAGESIZE_WIDTH 32U
+#define XHC_PAGESIZE__WIDTH 32U
+#define XHC_PAGESIZE_ALL_L 31U
+#define XHC_PAGESIZE_ALL_R 0U
+#define XHC_PAGESIZE__ALL_L 31U
+#define XHC_PAGESIZE__ALL_R 0U
+#define XHC_PAGESIZE_DATAMASK 0xffffffffU
+#define XHC_PAGESIZE_RDWRMASK 0x00000000U
+#define XHC_PAGESIZE_RESETVALUE 0x00000000U
+
+#define XHC_DNCTRL_OFFSET 0x034U
+#define XHC_DNCTRL_BASE 0x034U
+#define XHC_DNCTRL__reserved_L 31U
+#define XHC_DNCTRL__reserved_R 16U
+#define XHC_DNCTRL__reserved_WIDTH 16U
+#define XHC_DNCTRL__reserved_RESETVALUE 0x0000U
+#define XHC_DNCTRL__DNE_L 15U
+#define XHC_DNCTRL__DNE_R 0U
+#define XHC_DNCTRL__DNE_WIDTH 16U
+#define XHC_DNCTRL__DNE_RESETVALUE 0x0000U
+#define XHC_DNCTRL_WIDTH 32U
+#define XHC_DNCTRL__WIDTH 32U
+#define XHC_DNCTRL_ALL_L 31U
+#define XHC_DNCTRL_ALL_R 0U
+#define XHC_DNCTRL__ALL_L 31U
+#define XHC_DNCTRL__ALL_R 0U
+#define XHC_DNCTRL_DATAMASK 0xffffffffU
+#define XHC_DNCTRL_RDWRMASK 0x00000000U
+#define XHC_DNCTRL_RESETVALUE 0x00000000U
+
+#define XHC_CRCRL_OFFSET 0x038U
+#define XHC_CRCRL_BASE 0x038U
+#define XHC_CRCRL__CRPL_L 31U
+#define XHC_CRCRL__CRPL_R 6U
+#define XHC_CRCRL__CRPL_WIDTH 26U
+#define XHC_CRCRL__CRPL_RESETVALUE 0x0U
+#define XHC_CRCRL__reserved_L 5U
+#define XHC_CRCRL__reserved_R 4U
+#define XHC_CRCRL__reserved_WIDTH 2U
+#define XHC_CRCRL__reserved_RESETVALUE 0x0U
+#define XHC_CRCRL__CRR 3U
+#define XHC_CRCRL__CRR_L 3U
+#define XHC_CRCRL__CRR_R 3U
+#define XHC_CRCRL__CRR_WIDTH 1U
+#define XHC_CRCRL__CRR_RESETVALUE 0x0U
+#define XHC_CRCRL__CA 2U
+#define XHC_CRCRL__CA_L 2U
+#define XHC_CRCRL__CA_R 2U
+#define XHC_CRCRL__CA_WIDTH 1U
+#define XHC_CRCRL__CA_RESETVALUE 0x0U
+#define XHC_CRCRL__CS 1U
+#define XHC_CRCRL__CS_L 1U
+#define XHC_CRCRL__CS_R 1U
+#define XHC_CRCRL__CS_WIDTH 1U
+#define XHC_CRCRL__CS_RESETVALUE 0x0U
+#define XHC_CRCRL__RCS 0U
+#define XHC_CRCRL__RCS_L 0U
+#define XHC_CRCRL__RCS_R 0U
+#define XHC_CRCRL__RCS_WIDTH 1U
+#define XHC_CRCRL__RCS_RESETVALUE 0x0U
+#define XHC_CRCRL_WIDTH 32U
+#define XHC_CRCRL__WIDTH 32U
+#define XHC_CRCRL_ALL_L 31U
+#define XHC_CRCRL_ALL_R 0U
+#define XHC_CRCRL__ALL_L 31U
+#define XHC_CRCRL__ALL_R 0U
+#define XHC_CRCRL_DATAMASK 0xffffffffU
+#define XHC_CRCRL_RDWRMASK 0x00000000U
+#define XHC_CRCRL_RESETVALUE 0x00000000U
+
+#define XHC_CRCRH_OFFSET 0x03cU
+#define XHC_CRCRH_BASE 0x03cU
+#define XHC_CRCRH__CRPH_L 31U
+#define XHC_CRCRH__CRPH_R 0U
+#define XHC_CRCRH__CRPH_WIDTH 32U
+#define XHC_CRCRH__CRPH_RESETVALUE 0x00000000U
+#define XHC_CRCRH_WIDTH 32U
+#define XHC_CRCRH__WIDTH 32U
+#define XHC_CRCRH_ALL_L 31U
+#define XHC_CRCRH_ALL_R 0U
+#define XHC_CRCRH__ALL_L 31U
+#define XHC_CRCRH__ALL_R 0U
+#define XHC_CRCRH_DATAMASK 0xffffffffU
+#define XHC_CRCRH_RDWRMASK 0x00000000U
+#define XHC_CRCRH_RESETVALUE 0x00000000U
+
+#define XHC_DCBAAPL_OFFSET 0x050U
+#define XHC_DCBAAPL_BASE 0x050U
+#define XHC_DCBAAPL__DCAL_L 31U
+#define XHC_DCBAAPL__DCAL_R 6U
+#define XHC_DCBAAPL__DCAL_WIDTH 26U
+#define XHC_DCBAAPL__DCAL_RESETVALUE 0x0U
+
+#define XHC_DCBAAPL__reserved_L 5U
+#define XHC_DCBAAPL__reserved_R 0U
+#define XHC_DCBAAPL__reserved_WIDTH 6U
+#define XHC_DCBAAPL__reserved_RESETVALUE 0x0U
+#define XHC_DCBAAPL_WIDTH 32U
+#define XHC_DCBAAPL__WIDTH 32U
+#define XHC_DCBAAPL_ALL_L 31U
+#define XHC_DCBAAPL_ALL_R 0U
+#define XHC_DCBAAPL__ALL_L 31U
+#define XHC_DCBAAPL__ALL_R 0U
+#define XHC_DCBAAPL_DATAMASK 0xffffffffU
+#define XHC_DCBAAPL_RDWRMASK 0x00000000U
+#define XHC_DCBAAPL_RESETVALUE 0x00000000U
+
+#define XHC_DCBAAPH_OFFSET 0x054U
+#define XHC_DCBAAPH_BASE 0x054U
+#define XHC_DCBAAPH__DCAH_L 31U
+#define XHC_DCBAAPH__DCAH_R 0U
+#define XHC_DCBAAPH__DCAH_WIDTH 32U
+#define XHC_DCBAAPH__DCAH_RESETVALUE 0x00000000U
+#define XHC_DCBAAPH_WIDTH 32U
+#define XHC_DCBAAPH__WIDTH 32U
+#define XHC_DCBAAPH_ALL_L 31U
+#define XHC_DCBAAPH_ALL_R 0U
+#define XHC_DCBAAPH__ALL_L 31U
+#define XHC_DCBAAPH__ALL_R 0U
+#define XHC_DCBAAPH_DATAMASK 0xffffffffU
+#define XHC_DCBAAPH_RDWRMASK 0x00000000U
+#define XHC_DCBAAPH_RESETVALUE 0x00000000U
+
+#define XHC_CONFIG_OFFSET 0x058U
+#define XHC_CONFIG_BASE 0x058U
+#define XHC_CONFIG__reserved_L 31U
+#define XHC_CONFIG__reserved_R 10U
+#define XHC_CONFIG__reserved_WIDTH 22U
+#define XHC_CONFIG__reserved_RESETVALUE 0x0U
+#define XHC_CONFIG__CIE 9U
+#define XHC_CONFIG__CIE_L 9U
+#define XHC_CONFIG__CIE_R 9U
+#define XHC_CONFIG__CIE_WIDTH 1U
+#define XHC_CONFIG__CIE_RESETVALUE 0x0U
+#define XHC_CONFIG__U3E 8U
+#define XHC_CONFIG__U3E_L 8U
+#define XHC_CONFIG__U3E_R 8U
+#define XHC_CONFIG__U3E_WIDTH 1U
+#define XHC_CONFIG__U3E_RESETVALUE 0x0U
+#define XHC_CONFIG__MSE_L 7U
+#define XHC_CONFIG__MSE_R 0U
+#define XHC_CONFIG__MSE_WIDTH 8U
+#define XHC_CONFIG__MSE_RESETVALUE 0x00U
+#define XHC_CONFIG_WIDTH 32U
+#define XHC_CONFIG__WIDTH 32U
+#define XHC_CONFIG_ALL_L 31U
+#define XHC_CONFIG_ALL_R 0U
+#define XHC_CONFIG__ALL_L 31U
+#define XHC_CONFIG__ALL_R 0U
+#define XHC_CONFIG_DATAMASK 0xffffffffU
+#define XHC_CONFIG_RDWRMASK 0x00000000U
+#define XHC_CONFIG_RESETVALUE 0x00000000U
+
+#define XHC_PORTSC1_OFFSET 0x420U
+#define XHC_PORTSC1_BASE 0x420U
+
+#define XHC_PORTSC1__WPR_L 31U
+#define XHC_PORTSC1__WPR_R 31U
+#define XHC_PORTSC1__WPR_WIDTH 1U
+#define XHC_PORTSC1__WPR_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__DNR_L 30U
+#define XHC_PORTSC1__DNR_R 30U
+#define XHC_PORTSC1__DNR_WIDTH 1U
+#define XHC_PORTSC1__DNR_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__WOE_L 27U
+#define XHC_PORTSC1__WOE_R 27U
+#define XHC_PORTSC1__WOE_WIDTH 1U
+#define XHC_PORTSC1__WOE_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__WDE_L 26U
+#define XHC_PORTSC1__WDE_R 26U
+#define XHC_PORTSC1__WDE_WIDTH 1U
+#define XHC_PORTSC1__WDE_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__WCE_L 25U
+#define XHC_PORTSC1__WCE_R 25U
+#define XHC_PORTSC1__WCE_WIDTH 1U
+#define XHC_PORTSC1__WCE_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__CAS_L 24U
+#define XHC_PORTSC1__CAS_R 24U
+#define XHC_PORTSC1__CAS_WIDTH 1U
+#define XHC_PORTSC1__CAS_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__CEC_L 23U
+#define XHC_PORTSC1__CEC_R 23U
+#define XHC_PORTSC1__CEC_WIDTH 1U
+#define XHC_PORTSC1__CEC_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__PLC_L 22U
+#define XHC_PORTSC1__PLC_R 22U
+#define XHC_PORTSC1__PLC_WIDTH 1U
+#define XHC_PORTSC1__PLC_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__PRC_L 21U
+#define XHC_PORTSC1__PRC_R 21U
+#define XHC_PORTSC1__PRC_WIDTH 1U
+#define XHC_PORTSC1__PRC_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__OCC_L 20U
+#define XHC_PORTSC1__OCC_R 20U
+#define XHC_PORTSC1__OCC_WIDTH 1U
+#define XHC_PORTSC1__OCC_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__WRC_L 19U
+#define XHC_PORTSC1__WRC_R 19U
+#define XHC_PORTSC1__WRC_WIDTH 1U
+#define XHC_PORTSC1__WRC_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__PEC_L 18U
+#define XHC_PORTSC1__PEC_R 18U
+#define XHC_PORTSC1__PEC_WIDTH 1U
+#define XHC_PORTSC1__PEC_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__CSC_L 17U
+#define XHC_PORTSC1__CSC_R 17U
+#define XHC_PORTSC1__CSC_WIDTH 1U
+#define XHC_PORTSC1__CSC_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__LWS_L 16U
+#define XHC_PORTSC1__LWS_R 16U
+#define XHC_PORTSC1__LWS_WIDTH 1U
+#define XHC_PORTSC1__LWS_RESETVALUE 0x0U
+#define XHC_PORTSC1__PIC_L 15U
+#define XHC_PORTSC1__PIC_R 14U
+#define XHC_PORTSC1__PIC_WIDTH 2U
+#define XHC_PORTSC1__PIC_RESETVALUE 0x0U
+#define XHC_PORTSC1__PS_L 13U
+#define XHC_PORTSC1__PS_R 10U
+#define XHC_PORTSC1__PS_WIDTH 4U
+#define XHC_PORTSC1__PS_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__PP_L 9U
+#define XHC_PORTSC1__PP_R 9U
+#define XHC_PORTSC1__PP_WIDTH 1U
+#define XHC_PORTSC1__PP_RESETVALUE 0x0U
+#define XHC_PORTSC1__PLS_L 8U
+#define XHC_PORTSC1__PLS_R 5U
+#define XHC_PORTSC1__PLS_WIDTH 4U
+#define XHC_PORTSC1__PLS_RESETVALUE 0x5U
+
+#define XHC_PORTSC1__PRST_L 4U
+#define XHC_PORTSC1__PRST_R 4U
+#define XHC_PORTSC1__PRST_WIDTH 1U
+#define XHC_PORTSC1__PRST_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__OCA_L 3U
+#define XHC_PORTSC1__OCA_R 3U
+#define XHC_PORTSC1__OCA_WIDTH 1U
+#define XHC_PORTSC1__OCA_RESETVALUE 0x0U
+#define XHC_PORTSC1__reserved 2U
+#define XHC_PORTSC1__reserved_L 2U
+#define XHC_PORTSC1__reserved_R 2U
+#define XHC_PORTSC1__reserved_WIDTH 1U
+#define XHC_PORTSC1__reserved_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__PED_L 1U
+#define XHC_PORTSC1__PED_R 1U
+#define XHC_PORTSC1__PED_WIDTH 1U
+#define XHC_PORTSC1__PED_RESETVALUE 0x0U
+
+#define XHC_PORTSC1__CCS_L 0U
+#define XHC_PORTSC1__CCS_R 0U
+#define XHC_PORTSC1__CCS_WIDTH 1U
+#define XHC_PORTSC1__CCS_RESETVALUE 0x0U
+#define XHC_PORTSC1__RESERVED_L 29U
+#define XHC_PORTSC1__RESERVED_R 28U
+#define XHC_PORTSC1_WIDTH 32U
+#define XHC_PORTSC1__WIDTH 32U
+#define XHC_PORTSC1_ALL_L 31U
+#define XHC_PORTSC1_ALL_R 0U
+#define XHC_PORTSC1__ALL_L 31U
+#define XHC_PORTSC1__ALL_R 0U
+#define XHC_PORTSC1_DATAMASK 0xcfffffffU
+#define XHC_PORTSC1_RDWRMASK 0x30000000U
+#define XHC_PORTSC1_RESETVALUE 0x000000a0U
+
+#define XHC_PORTPM1_OFFSET 0x424U
+#define XHC_PORTPM1_BASE 0x424U
+#define XHC_PORTPM1__reserved_L 31U
+#define XHC_PORTPM1__reserved_R 17U
+#define XHC_PORTPM1__reserved_WIDTH 15U
+#define XHC_PORTPM1__reserved_RESETVALUE 0x0U
+#define XHC_PORTPM1__FLA 16U
+#define XHC_PORTPM1__FLA_L 16U
+#define XHC_PORTPM1__FLA_R 16U
+#define XHC_PORTPM1__FLA_WIDTH 1U
+#define XHC_PORTPM1__FLA_RESETVALUE 0x0U
+#define XHC_PORTPM1__U2T_L 15U
+#define XHC_PORTPM1__U2T_R 8U
+#define XHC_PORTPM1__U2T_WIDTH 8U
+#define XHC_PORTPM1__U2T_RESETVALUE 0x00U
+#define XHC_PORTPM1__U1T_L 7U
+#define XHC_PORTPM1__U1T_R 0U
+#define XHC_PORTPM1__U1T_WIDTH 8U
+#define XHC_PORTPM1__U1T_RESETVALUE 0x00U
+#define XHC_PORTPM1_WIDTH 32U
+#define XHC_PORTPM1__WIDTH 32U
+#define XHC_PORTPM1_ALL_L 31U
+#define XHC_PORTPM1_ALL_R 0U
+#define XHC_PORTPM1__ALL_L 31U
+#define XHC_PORTPM1__ALL_R 0U
+#define XHC_PORTPM1_DATAMASK 0xffffffffU
+#define XHC_PORTPM1_RDWRMASK 0x00000000U
+#define XHC_PORTPM1_RESETVALUE 0x00000000U
+
+#define XHC_PORTLC1_OFFSET 0x428U
+#define XHC_PORTLC1_BASE 0x428U
+#define XHC_PORTLC1__reserved_L 31U
+#define XHC_PORTLC1__reserved_R 0U
+#define XHC_PORTLC1__reserved_WIDTH 32U
+#define XHC_PORTLC1__reserved_RESETVALUE 0x00000000U
+#define XHC_PORTLC1_WIDTH 32U
+#define XHC_PORTLC1__WIDTH 32U
+#define XHC_PORTLC1_ALL_L 31U
+#define XHC_PORTLC1_ALL_R 0U
+#define XHC_PORTLC1__ALL_L 31U
+#define XHC_PORTLC1__ALL_R 0U
+#define XHC_PORTLC1_DATAMASK 0xffffffffU
+#define XHC_PORTLC1_RDWRMASK 0x00000000U
+#define XHC_PORTLC1_RESETVALUE 0x00000000U
+
+#define XHC_PORTSC2_OFFSET 0x430U
+#define XHC_PORTSC2_BASE 0x430U
+#define XHC_PORTSC2__WPR 31U
+#define XHC_PORTSC2__WPR_L 31U
+#define XHC_PORTSC2__WPR_R 31U
+#define XHC_PORTSC2__WPR_WIDTH 1U
+#define XHC_PORTSC2__WPR_RESETVALUE 0x0U
+#define XHC_PORTSC2__DNR 30U
+#define XHC_PORTSC2__DNR_L 30U
+#define XHC_PORTSC2__DNR_R 30U
+#define XHC_PORTSC2__DNR_WIDTH 1U
+#define XHC_PORTSC2__DNR_RESETVALUE 0x0U
+#define XHC_PORTSC2__WOE 27U
+#define XHC_PORTSC2__WOE_L 27U
+#define XHC_PORTSC2__WOE_R 27U
+#define XHC_PORTSC2__WOE_WIDTH 1U
+#define XHC_PORTSC2__WOE_RESETVALUE 0x0U
+#define XHC_PORTSC2__WDE 26U
+#define XHC_PORTSC2__WDE_L 26U
+#define XHC_PORTSC2__WDE_R 26U
+#define XHC_PORTSC2__WDE_WIDTH 1U
+#define XHC_PORTSC2__WDE_RESETVALUE 0x0U
+#define XHC_PORTSC2__WCE 25U
+#define XHC_PORTSC2__WCE_L 25U
+#define XHC_PORTSC2__WCE_R 25U
+#define XHC_PORTSC2__WCE_WIDTH 1U
+#define XHC_PORTSC2__WCE_RESETVALUE 0x0U
+#define XHC_PORTSC2__CAS 24U
+#define XHC_PORTSC2__CAS_L 24U
+#define XHC_PORTSC2__CAS_R 24U
+#define XHC_PORTSC2__CAS_WIDTH 1U
+#define XHC_PORTSC2__CAS_RESETVALUE 0x0U
+#define XHC_PORTSC2__CEC 23U
+#define XHC_PORTSC2__CEC_L 23U
+#define XHC_PORTSC2__CEC_R 23U
+#define XHC_PORTSC2__CEC_WIDTH 1U
+#define XHC_PORTSC2__CEC_RESETVALUE 0x0U
+#define XHC_PORTSC2__PLC 22U
+#define XHC_PORTSC2__PLC_L 22U
+#define XHC_PORTSC2__PLC_R 22U
+#define XHC_PORTSC2__PLC_WIDTH 1U
+#define XHC_PORTSC2__PLC_RESETVALUE 0x0U
+#define XHC_PORTSC2__PRC 21U
+#define XHC_PORTSC2__PRC_L 21U
+#define XHC_PORTSC2__PRC_R 21U
+#define XHC_PORTSC2__PRC_WIDTH 1U
+#define XHC_PORTSC2__PRC_RESETVALUE 0x0U
+#define XHC_PORTSC2__OCC 20U
+#define XHC_PORTSC2__OCC_L 20U
+#define XHC_PORTSC2__OCC_R 20U
+#define XHC_PORTSC2__OCC_WIDTH 1U
+#define XHC_PORTSC2__OCC_RESETVALUE 0x0U
+#define XHC_PORTSC2__WRC 19U
+#define XHC_PORTSC2__WRC_L 19U
+#define XHC_PORTSC2__WRC_R 19U
+#define XHC_PORTSC2__WRC_WIDTH 1U
+#define XHC_PORTSC2__WRC_RESETVALUE 0x0U
+#define XHC_PORTSC2__PEC 18U
+#define XHC_PORTSC2__PEC_L 18U
+#define XHC_PORTSC2__PEC_R 18U
+#define XHC_PORTSC2__PEC_WIDTH 1U
+#define XHC_PORTSC2__PEC_RESETVALUE 0x0U
+#define XHC_PORTSC2__CSC 17U
+#define XHC_PORTSC2__CSC_L 17U
+#define XHC_PORTSC2__CSC_R 17U
+#define XHC_PORTSC2__CSC_WIDTH 1U
+#define XHC_PORTSC2__CSC_RESETVALUE 0x0U
+#define XHC_PORTSC2__LWS 16U
+#define XHC_PORTSC2__LWS_L 16U
+#define XHC_PORTSC2__LWS_R 16U
+#define XHC_PORTSC2__LWS_WIDTH 1U
+#define XHC_PORTSC2__LWS_RESETVALUE 0x0U
+#define XHC_PORTSC2__PIC_L 15U
+#define XHC_PORTSC2__PIC_R 14U
+#define XHC_PORTSC2__PIC_WIDTH 2U
+#define XHC_PORTSC2__PIC_RESETVALUE 0x0U
+#define XHC_PORTSC2__PS_L 13U
+#define XHC_PORTSC2__PS_R 10U
+#define XHC_PORTSC2__PS_WIDTH 4U
+#define XHC_PORTSC2__PS_RESETVALUE 0x0U
+#define XHC_PORTSC2__PP 9U
+#define XHC_PORTSC2__PP_L 9U
+#define XHC_PORTSC2__PP_R 9U
+#define XHC_PORTSC2__PP_WIDTH 1U
+#define XHC_PORTSC2__PP_RESETVALUE 0x0U
+#define XHC_PORTSC2__PLS_L 8U
+#define XHC_PORTSC2__PLS_R 5U
+#define XHC_PORTSC2__PLS_WIDTH 4U
+#define XHC_PORTSC2__PLS_RESETVALUE 0x5U
+
+#define XHC_PORTSC2__PRST_L 4U
+#define XHC_PORTSC2__PRST_R 4U
+#define XHC_PORTSC2__PRST_WIDTH 1U
+#define XHC_PORTSC2__PRST_RESETVALUE 0x0U
+#define XHC_PORTSC2__OCA 3U
+#define XHC_PORTSC2__OCA_L 3U
+#define XHC_PORTSC2__OCA_R 3U
+#define XHC_PORTSC2__OCA_WIDTH 1U
+#define XHC_PORTSC2__OCA_RESETVALUE 0x0U
+#define XHC_PORTSC2__reserved 2U
+#define XHC_PORTSC2__reserved_L 2U
+#define XHC_PORTSC2__reserved_R 2U
+#define XHC_PORTSC2__reserved_WIDTH 1U
+#define XHC_PORTSC2__reserved_RESETVALUE 0x0U
+#define XHC_PORTSC2__PED 1U
+#define XHC_PORTSC2__PED_L 1U
+#define XHC_PORTSC2__PED_R 1U
+#define XHC_PORTSC2__PED_WIDTH 1U
+#define XHC_PORTSC2__PED_RESETVALUE 0x0U
+#define XHC_PORTSC2__CCS 0U
+#define XHC_PORTSC2__CCS_L 0U
+#define XHC_PORTSC2__CCS_R 0U
+#define XHC_PORTSC2__CCS_WIDTH 1U
+#define XHC_PORTSC2__CCS_RESETVALUE 0x0U
+#define XHC_PORTSC2__RESERVED_L 29U
+#define XHC_PORTSC2__RESERVED_R 28U
+#define XHC_PORTSC2_WIDTH 32U
+#define XHC_PORTSC2__WIDTH 32U
+#define XHC_PORTSC2_ALL_L 31U
+#define XHC_PORTSC2_ALL_R 0U
+#define XHC_PORTSC2__ALL_L 31U
+#define XHC_PORTSC2__ALL_R 0U
+#define XHC_PORTSC2_DATAMASK 0xcfffffffU
+#define XHC_PORTSC2_RDWRMASK 0x30000000U
+#define XHC_PORTSC2_RESETVALUE 0x000000a0U
+
+#define XHC_PORTPM2_OFFSET 0x434U
+#define XHC_PORTPM2_BASE 0x434U
+#define XHC_PORTPM2__PTC_L 31U
+#define XHC_PORTPM2__PTC_R 28U
+#define XHC_PORTPM2__PTC_WIDTH 4U
+#define XHC_PORTPM2__PTC_RESETVALUE 0x0U
+#define XHC_PORTPM2__reserved_L 27U
+#define XHC_PORTPM2__reserved_R 17U
+#define XHC_PORTPM2__reserved_WIDTH 11U
+#define XHC_PORTPM2__reserved_RESETVALUE 0x0U
+#define XHC_PORTPM2__HLE 16U
+#define XHC_PORTPM2__HLE_L 16U
+#define XHC_PORTPM2__HLE_R 16U
+#define XHC_PORTPM2__HLE_WIDTH 1U
+#define XHC_PORTPM2__HLE_RESETVALUE 0x0U
+#define XHC_PORTPM2__L1DS_L 15U
+#define XHC_PORTPM2__L1DS_R 8U
+#define XHC_PORTPM2__L1DS_WIDTH 8U
+#define XHC_PORTPM2__L1DS_RESETVALUE 0x00U
+#define XHC_PORTPM2__BESL_L 7U
+#define XHC_PORTPM2__BESL_R 4U
+#define XHC_PORTPM2__BESL_WIDTH 4U
+#define XHC_PORTPM2__BESL_RESETVALUE 0x0U
+#define XHC_PORTPM2__RWE 3U
+#define XHC_PORTPM2__RWE_L 3U
+#define XHC_PORTPM2__RWE_R 3U
+#define XHC_PORTPM2__RWE_WIDTH 1U
+#define XHC_PORTPM2__RWE_RESETVALUE 0x0U
+#define XHC_PORTPM2__L1S_L 2U
+#define XHC_PORTPM2__L1S_R 0U
+#define XHC_PORTPM2__L1S_WIDTH 3U
+#define XHC_PORTPM2__L1S_RESETVALUE 0x0U
+#define XHC_PORTPM2_WIDTH 32U
+#define XHC_PORTPM2__WIDTH 32U
+#define XHC_PORTPM2_ALL_L 31U
+#define XHC_PORTPM2_ALL_R 0U
+#define XHC_PORTPM2__ALL_L 31U
+#define XHC_PORTPM2__ALL_R 0U
+#define XHC_PORTPM2_DATAMASK 0xffffffffU
+#define XHC_PORTPM2_RDWRMASK 0x00000000U
+#define XHC_PORTPM2_RESETVALUE 0x00000000U
+
+#define XHC_PORTLC2_OFFSET 0x43cU
+#define XHC_PORTLC2_BASE 0x43cU
+#define XHC_PORTLC2__reserved_L 31U
+#define XHC_PORTLC2__reserved_R 14U
+#define XHC_PORTLC2__reserved_WIDTH 18U
+#define XHC_PORTLC2__reserved_RESETVALUE 0x0U
+#define XHC_PORTLC2__BESLD_L 13U
+#define XHC_PORTLC2__BESLD_R 10U
+#define XHC_PORTLC2__BESLD_WIDTH 4U
+#define XHC_PORTLC2__BESLD_RESETVALUE 0x0U
+#define XHC_PORTLC2__L1T_L 9U
+#define XHC_PORTLC2__L1T_R 2U
+#define XHC_PORTLC2__L1T_WIDTH 8U
+#define XHC_PORTLC2__L1T_RESETVALUE 0x00U
+#define XHC_PORTLC2__HIRDM_L 1U
+#define XHC_PORTLC2__HIRDM_R 0U
+#define XHC_PORTLC2__HIRDM_WIDTH 2U
+#define XHC_PORTLC2__HIRDM_RESETVALUE 0x0U
+#define XHC_PORTLC2_WIDTH 32U
+#define XHC_PORTLC2__WIDTH 32U
+#define XHC_PORTLC2_ALL_L 31U
+#define XHC_PORTLC2_ALL_R 0U
+#define XHC_PORTLC2__ALL_L 31U
+#define XHC_PORTLC2__ALL_R 0U
+#define XHC_PORTLC2_DATAMASK 0xffffffffU
+#define XHC_PORTLC2_RDWRMASK 0x00000000U
+#define XHC_PORTLC2_RESETVALUE 0x00000000U
+
+#define XHC_PORTSC3_OFFSET 0x440U
+#define XHC_PORTSC3_BASE 0x440U
+#define XHC_PORTSC3__WPR 31U
+#define XHC_PORTSC3__WPR_L 31U
+#define XHC_PORTSC3__WPR_R 31U
+#define XHC_PORTSC3__WPR_WIDTH 1U
+#define XHC_PORTSC3__WPR_RESETVALUE 0x0U
+#define XHC_PORTSC3__DNR 30U
+#define XHC_PORTSC3__DNR_L 30U
+#define XHC_PORTSC3__DNR_R 30U
+#define XHC_PORTSC3__DNR_WIDTH 1U
+#define XHC_PORTSC3__DNR_RESETVALUE 0x0U
+#define XHC_PORTSC3__WOE 27U
+#define XHC_PORTSC3__WOE_L 27U
+#define XHC_PORTSC3__WOE_R 27U
+#define XHC_PORTSC3__WOE_WIDTH 1U
+#define XHC_PORTSC3__WOE_RESETVALUE 0x0U
+#define XHC_PORTSC3__WDE 26U
+#define XHC_PORTSC3__WDE_L 26U
+#define XHC_PORTSC3__WDE_R 26U
+#define XHC_PORTSC3__WDE_WIDTH 1U
+#define XHC_PORTSC3__WDE_RESETVALUE 0x0U
+#define XHC_PORTSC3__WCE 25U
+#define XHC_PORTSC3__WCE_L 25U
+#define XHC_PORTSC3__WCE_R 25U
+#define XHC_PORTSC3__WCE_WIDTH 1U
+#define XHC_PORTSC3__WCE_RESETVALUE 0x0U
+#define XHC_PORTSC3__CAS 24U
+#define XHC_PORTSC3__CAS_L 24U
+#define XHC_PORTSC3__CAS_R 24U
+#define XHC_PORTSC3__CAS_WIDTH 1U
+#define XHC_PORTSC3__CAS_RESETVALUE 0x0U
+#define XHC_PORTSC3__CEC 23U
+#define XHC_PORTSC3__CEC_L 23U
+#define XHC_PORTSC3__CEC_R 23U
+#define XHC_PORTSC3__CEC_WIDTH 1U
+#define XHC_PORTSC3__CEC_RESETVALUE 0x0U
+#define XHC_PORTSC3__PLC 22U
+#define XHC_PORTSC3__PLC_L 22U
+#define XHC_PORTSC3__PLC_R 22U
+#define XHC_PORTSC3__PLC_WIDTH 1U
+#define XHC_PORTSC3__PLC_RESETVALUE 0x0U
+#define XHC_PORTSC3__PRC 21U
+#define XHC_PORTSC3__PRC_L 21U
+#define XHC_PORTSC3__PRC_R 21U
+#define XHC_PORTSC3__PRC_WIDTH 1U
+#define XHC_PORTSC3__PRC_RESETVALUE 0x0U
+#define XHC_PORTSC3__OCC 20U
+#define XHC_PORTSC3__OCC_L 20U
+#define XHC_PORTSC3__OCC_R 20U
+#define XHC_PORTSC3__OCC_WIDTH 1U
+#define XHC_PORTSC3__OCC_RESETVALUE 0x0U
+#define XHC_PORTSC3__WRC 19U
+#define XHC_PORTSC3__WRC_L 19U
+#define XHC_PORTSC3__WRC_R 19U
+#define XHC_PORTSC3__WRC_WIDTH 1U
+#define XHC_PORTSC3__WRC_RESETVALUE 0x0U
+#define XHC_PORTSC3__PEC 18U
+#define XHC_PORTSC3__PEC_L 18U
+#define XHC_PORTSC3__PEC_R 18U
+#define XHC_PORTSC3__PEC_WIDTH 1U
+#define XHC_PORTSC3__PEC_RESETVALUE 0x0U
+#define XHC_PORTSC3__CSC 17U
+#define XHC_PORTSC3__CSC_L 17U
+#define XHC_PORTSC3__CSC_R 17U
+#define XHC_PORTSC3__CSC_WIDTH 1U
+#define XHC_PORTSC3__CSC_RESETVALUE 0x0U
+#define XHC_PORTSC3__LWS 16U
+#define XHC_PORTSC3__LWS_L 16U
+#define XHC_PORTSC3__LWS_R 16U
+#define XHC_PORTSC3__LWS_WIDTH 1U
+#define XHC_PORTSC3__LWS_RESETVALUE 0x0U
+#define XHC_PORTSC3__PIC_L 15U
+#define XHC_PORTSC3__PIC_R 14U
+#define XHC_PORTSC3__PIC_WIDTH 2U
+#define XHC_PORTSC3__PIC_RESETVALUE 0x0U
+#define XHC_PORTSC3__PS_L 13U
+#define XHC_PORTSC3__PS_R 10U
+#define XHC_PORTSC3__PS_WIDTH 4U
+#define XHC_PORTSC3__PS_RESETVALUE 0x0U
+#define XHC_PORTSC3__PP 9U
+#define XHC_PORTSC3__PP_L 9U
+#define XHC_PORTSC3__PP_R 9U
+#define XHC_PORTSC3__PP_WIDTH 1U
+#define XHC_PORTSC3__PP_RESETVALUE 0x0U
+#define XHC_PORTSC3__PLS_L 8U
+#define XHC_PORTSC3__PLS_R 5U
+#define XHC_PORTSC3__PLS_WIDTH 4U
+#define XHC_PORTSC3__PLS_RESETVALUE 0x5U
+#define XHC_PORTSC3__PR 4U
+#define XHC_PORTSC3__PR_L 4U
+#define XHC_PORTSC3__PR_R 4U
+#define XHC_PORTSC3__PR_WIDTH 1U
+#define XHC_PORTSC3__PR_RESETVALUE 0x0U
+#define XHC_PORTSC3__OCA 3U
+#define XHC_PORTSC3__OCA_L 3U
+#define XHC_PORTSC3__OCA_R 3U
+#define XHC_PORTSC3__OCA_WIDTH 1U
+#define XHC_PORTSC3__OCA_RESETVALUE 0x0U
+#define XHC_PORTSC3__reserved 2U
+#define XHC_PORTSC3__reserved_L 2U
+#define XHC_PORTSC3__reserved_R 2U
+#define XHC_PORTSC3__reserved_WIDTH 1U
+#define XHC_PORTSC3__reserved_RESETVALUE 0x0U
+#define XHC_PORTSC3__PED 1U
+#define XHC_PORTSC3__PED_L 1U
+#define XHC_PORTSC3__PED_R 1U
+#define XHC_PORTSC3__PED_WIDTH 1U
+#define XHC_PORTSC3__PED_RESETVALUE 0x0U
+#define XHC_PORTSC3__CCS 0U
+#define XHC_PORTSC3__CCS_L 0U
+#define XHC_PORTSC3__CCS_R 0U
+#define XHC_PORTSC3__CCS_WIDTH 1U
+#define XHC_PORTSC3__CCS_RESETVALUE 0x0U
+#define XHC_PORTSC3__RESERVED_L 29U
+#define XHC_PORTSC3__RESERVED_R 28U
+#define XHC_PORTSC3_WIDTH 32U
+#define XHC_PORTSC3__WIDTH 32U
+#define XHC_PORTSC3_ALL_L 31U
+#define XHC_PORTSC3_ALL_R 0U
+#define XHC_PORTSC3__ALL_L 31U
+#define XHC_PORTSC3__ALL_R 0U
+#define XHC_PORTSC3_DATAMASK 0xcfffffffU
+#define XHC_PORTSC3_RDWRMASK 0x30000000U
+#define XHC_PORTSC3_RESETVALUE 0x000000a0U
+
+#define XHC_PORTPM3_OFFSET 0x444U
+#define XHC_PORTPM3_BASE 0x444U
+#define XHC_PORTPM3__PTC_L 31U
+#define XHC_PORTPM3__PTC_R 28U
+#define XHC_PORTPM3__PTC_WIDTH 4U
+#define XHC_PORTPM3__PTC_RESETVALUE 0x0U
+#define XHC_PORTPM3__reserved_L 27U
+#define XHC_PORTPM3__reserved_R 17U
+#define XHC_PORTPM3__reserved_WIDTH 11U
+#define XHC_PORTPM3__reserved_RESETVALUE 0x0U
+#define XHC_PORTPM3__HLE 16U
+#define XHC_PORTPM3__HLE_L 16U
+#define XHC_PORTPM3__HLE_R 16U
+#define XHC_PORTPM3__HLE_WIDTH 1U
+#define XHC_PORTPM3__HLE_RESETVALUE 0x0U
+#define XHC_PORTPM3__L1DS_L 15U
+#define XHC_PORTPM3__L1DS_R 8U
+#define XHC_PORTPM3__L1DS_WIDTH 8U
+#define XHC_PORTPM3__L1DS_RESETVALUE 0x00U
+#define XHC_PORTPM3__BESL_L 7U
+#define XHC_PORTPM3__BESL_R 4U
+#define XHC_PORTPM3__BESL_WIDTH 4U
+#define XHC_PORTPM3__BESL_RESETVALUE 0x0U
+#define XHC_PORTPM3__RWE 3U
+#define XHC_PORTPM3__RWE_L 3U
+#define XHC_PORTPM3__RWE_R 3U
+#define XHC_PORTPM3__RWE_WIDTH 1U
+#define XHC_PORTPM3__RWE_RESETVALUE 0x0U
+#define XHC_PORTPM3__L1S_L 2U
+#define XHC_PORTPM3__L1S_R 0U
+#define XHC_PORTPM3__L1S_WIDTH 3U
+#define XHC_PORTPM3__L1S_RESETVALUE 0x0U
+#define XHC_PORTPM3_WIDTH 32U
+#define XHC_PORTPM3__WIDTH 32U
+#define XHC_PORTPM3_ALL_L 31U
+#define XHC_PORTPM3_ALL_R 0U
+#define XHC_PORTPM3__ALL_L 31U
+#define XHC_PORTPM3__ALL_R 0U
+#define XHC_PORTPM3_DATAMASK 0xffffffffU
+#define XHC_PORTPM3_RDWRMASK 0x00000000U
+#define XHC_PORTPM3_RESETVALUE 0x00000000U
+
+#define XHC_PORTLI3_OFFSET 0x44cU
+#define XHC_PORTLI3_BASE 0x44cU
+#define XHC_PORTLI3__reserved_L 31U
+#define XHC_PORTLI3__reserved_R 0U
+#define XHC_PORTLI3__reserved_WIDTH 32U
+#define XHC_PORTLI3__reserved_RESETVALUE 0x00000000U
+#define XHC_PORTLI3_WIDTH 32U
+#define XHC_PORTLI3__WIDTH 32U
+#define XHC_PORTLI3_ALL_L 31U
+#define XHC_PORTLI3_ALL_R 0U
+#define XHC_PORTLI3__ALL_L 31U
+#define XHC_PORTLI3__ALL_R 0U
+#define XHC_PORTLI3_DATAMASK 0xffffffffU
+#define XHC_PORTLI3_RDWRMASK 0x00000000U
+#define XHC_PORTLI3_RESETVALUE 0x00000000U
+
+#define XHC_MFINDEX_OFFSET 0x4a0U
+#define XHC_MFINDEX_BASE 0x4a0U
+#define XHC_MFINDEX__reserved_L 31U
+#define XHC_MFINDEX__reserved_R 14U
+#define XHC_MFINDEX__reserved_WIDTH 18U
+#define XHC_MFINDEX__reserved_RESETVALUE 0x0U
+#define XHC_MFINDEX__MFI_L 13U
+#define XHC_MFINDEX__MFI_R 0U
+#define XHC_MFINDEX__MFI_WIDTH 14U
+#define XHC_MFINDEX__MFI_RESETVALUE 0x0U
+#define XHC_MFINDEX_WIDTH 32U
+#define XHC_MFINDEX__WIDTH 32U
+#define XHC_MFINDEX_ALL_L 31U
+#define XHC_MFINDEX_ALL_R 0U
+#define XHC_MFINDEX__ALL_L 31U
+#define XHC_MFINDEX__ALL_R 0U
+#define XHC_MFINDEX_DATAMASK 0xffffffffU
+#define XHC_MFINDEX_RDWRMASK 0x00000000U
+#define XHC_MFINDEX_RESETVALUE 0x00000000U
+
+#define XHC_IMAN0_OFFSET 0x4c0U
+#define XHC_IMAN0_BASE 0x4c0U
+#define XHC_IMAN0__reserved_L 31U
+#define XHC_IMAN0__reserved_R 2U
+#define XHC_IMAN0__reserved_WIDTH 30U
+#define XHC_IMAN0__reserved_RESETVALUE 0x0U
+#define XHC_IMAN0__IE 1U
+#define XHC_IMAN0__IE_L 1U
+#define XHC_IMAN0__IE_R 1U
+#define XHC_IMAN0__IE_WIDTH 1U
+#define XHC_IMAN0__IE_RESETVALUE 0x0U
+#define XHC_IMAN0__IP 0U
+#define XHC_IMAN0__IP_L 0U
+#define XHC_IMAN0__IP_R 0U
+#define XHC_IMAN0__IP_WIDTH 1U
+#define XHC_IMAN0__IP_RESETVALUE 0x0U
+#define XHC_IMAN0_WIDTH 32U
+#define XHC_IMAN0__WIDTH 32U
+#define XHC_IMAN0_ALL_L 31U
+#define XHC_IMAN0_ALL_R 0U
+#define XHC_IMAN0__ALL_L 31U
+#define XHC_IMAN0__ALL_R 0U
+#define XHC_IMAN0_DATAMASK 0xffffffffU
+#define XHC_IMAN0_RDWRMASK 0x00000000U
+#define XHC_IMAN0_RESETVALUE 0x00000000U
+
+#define XHC_IMOD0_OFFSET 0x4c4U
+#define XHC_IMOD0_BASE 0x4c4U
+#define XHC_IMOD0__IMODC_L 31U
+#define XHC_IMOD0__IMODC_R 16U
+#define XHC_IMOD0__IMODC_WIDTH 16U
+#define XHC_IMOD0__IMODC_RESETVALUE 0x0000U
+#define XHC_IMOD0__IMODI_L 15U
+#define XHC_IMOD0__IMODI_R 0U
+#define XHC_IMOD0__IMODI_WIDTH 16U
+#define XHC_IMOD0__IMODI_RESETVALUE 0x4000U
+#define XHC_IMOD0_WIDTH 32U
+#define XHC_IMOD0__WIDTH 32U
+#define XHC_IMOD0_ALL_L 31U
+#define XHC_IMOD0_ALL_R 0U
+#define XHC_IMOD0__ALL_L 31U
+#define XHC_IMOD0__ALL_R 0U
+#define XHC_IMOD0_DATAMASK 0xffffffffU
+#define XHC_IMOD0_RDWRMASK 0x00000000U
+#define XHC_IMOD0_RESETVALUE 0x00004000U
+
+#define XHC_ERSTSZ0_OFFSET 0x4c8U
+#define XHC_ERSTSZ0_BASE 0x4c8U
+#define XHC_ERSTSZ0__reserved_L 31U
+#define XHC_ERSTSZ0__reserved_R 16U
+#define XHC_ERSTSZ0__reserved_WIDTH 16U
+#define XHC_ERSTSZ0__reserved_RESETVALUE 0x0000U
+#define XHC_ERSTSZ0__TSZ_L 15U
+#define XHC_ERSTSZ0__TSZ_R 0U
+#define XHC_ERSTSZ0__TSZ_WIDTH 16U
+#define XHC_ERSTSZ0__TSZ_RESETVALUE 0x0000U
+#define XHC_ERSTSZ0_WIDTH 32U
+#define XHC_ERSTSZ0__WIDTH 32U
+#define XHC_ERSTSZ0_ALL_L 31U
+#define XHC_ERSTSZ0_ALL_R 0U
+#define XHC_ERSTSZ0__ALL_L 31U
+#define XHC_ERSTSZ0__ALL_R 0U
+#define XHC_ERSTSZ0_DATAMASK 0xffffffffU
+#define XHC_ERSTSZ0_RDWRMASK 0x00000000U
+#define XHC_ERSTSZ0_RESETVALUE 0x00000000U
+
+#define XHC_ERSTBAL0_OFFSET 0x4d0U
+#define XHC_ERSTBAL0_BASE 0x4d0U
+#define XHC_ERSTBAL0__BAL_L 31U
+#define XHC_ERSTBAL0__BAL_R 4U
+#define XHC_ERSTBAL0__BAL_WIDTH 28U
+#define XHC_ERSTBAL0__BAL_RESETVALUE 0x0000000U
+#define XHC_ERSTBAL0__reserved_L 3U
+#define XHC_ERSTBAL0__reserved_R 0U
+#define XHC_ERSTBAL0__reserved_WIDTH 4U
+#define XHC_ERSTBAL0__reserved_RESETVALUE 0x0U
+#define XHC_ERSTBAL0_WIDTH 32U
+#define XHC_ERSTBAL0__WIDTH 32U
+#define XHC_ERSTBAL0_ALL_L 31U
+#define XHC_ERSTBAL0_ALL_R 0U
+#define XHC_ERSTBAL0__ALL_L 31U
+#define XHC_ERSTBAL0__ALL_R 0U
+#define XHC_ERSTBAL0_DATAMASK 0xffffffffU
+#define XHC_ERSTBAL0_RDWRMASK 0x00000000U
+#define XHC_ERSTBAL0_RESETVALUE 0x00000000U
+
+#define XHC_ERSTBAH0_OFFSET 0x4d4U
+#define XHC_ERSTBAH0_BASE 0x4d4U
+#define XHC_ERSTBAH0__BAH_L 31U
+#define XHC_ERSTBAH0__BAH_R 0U
+#define XHC_ERSTBAH0__BAH_WIDTH 32U
+#define XHC_ERSTBAH0__BAH_RESETVALUE 0x00000000U
+#define XHC_ERSTBAH0_WIDTH 32U
+#define XHC_ERSTBAH0__WIDTH 32U
+#define XHC_ERSTBAH0_ALL_L 31U
+#define XHC_ERSTBAH0_ALL_R 0U
+#define XHC_ERSTBAH0__ALL_L 31U
+#define XHC_ERSTBAH0__ALL_R 0U
+#define XHC_ERSTBAH0_DATAMASK 0xffffffffU
+#define XHC_ERSTBAH0_RDWRMASK 0x00000000U
+#define XHC_ERSTBAH0_RESETVALUE 0x00000000U
+
+#define XHC_ERDPL0_OFFSET 0x4d8U
+#define XHC_ERDPL0_BASE 0x4d8U
+#define XHC_ERDPL0__DPL_L 31U
+#define XHC_ERDPL0__DPL_R 4U
+#define XHC_ERDPL0__DPL_WIDTH 28U
+#define XHC_ERDPL0__DPL_RESETVALUE 0x0000000U
+#define XHC_ERDPL0__EHB 3U
+#define XHC_ERDPL0__EHB_L 3U
+#define XHC_ERDPL0__EHB_R 3U
+#define XHC_ERDPL0__EHB_WIDTH 1U
+#define XHC_ERDPL0__EHB_RESETVALUE 0x0U
+#define XHC_ERDPL0__DESI_L 2U
+#define XHC_ERDPL0__DESI_R 0U
+#define XHC_ERDPL0__DESI_WIDTH 3U
+#define XHC_ERDPL0__DESI_RESETVALUE 0x0U
+#define XHC_ERDPL0_WIDTH 32U
+#define XHC_ERDPL0__WIDTH 32U
+#define XHC_ERDPL0_ALL_L 31U
+#define XHC_ERDPL0_ALL_R 0U
+#define XHC_ERDPL0__ALL_L 31U
+#define XHC_ERDPL0__ALL_R 0U
+#define XHC_ERDPL0_DATAMASK 0xffffffffU
+#define XHC_ERDPL0_RDWRMASK 0x00000000U
+#define XHC_ERDPL0_RESETVALUE 0x00000000U
+
+#define XHC_ERDPH0_OFFSET 0x4dcU
+#define XHC_ERDPH0_BASE 0x4dcU
+#define XHC_ERDPH0__DPH_L 31U
+#define XHC_ERDPH0__DPH_R 0U
+#define XHC_ERDPH0__DPH_WIDTH 32U
+#define XHC_ERDPH0__DPH_RESETVALUE 0x00000000U
+#define XHC_ERDPH0_WIDTH 32U
+#define XHC_ERDPH0__WIDTH 32U
+#define XHC_ERDPH0_ALL_L 31U
+#define XHC_ERDPH0_ALL_R 0U
+#define XHC_ERDPH0__ALL_L 31U
+#define XHC_ERDPH0__ALL_R 0U
+#define XHC_ERDPH0_DATAMASK 0xffffffffU
+#define XHC_ERDPH0_RDWRMASK 0x00000000U
+#define XHC_ERDPH0_RESETVALUE 0x00000000U
+
+#define XHC_IMAN1_OFFSET 0x4e0U
+#define XHC_IMAN1_BASE 0x4e0U
+#define XHC_IMAN1__reserved_L 31U
+#define XHC_IMAN1__reserved_R 2U
+#define XHC_IMAN1__reserved_WIDTH 30U
+#define XHC_IMAN1__reserved_RESETVALUE 0x0U
+#define XHC_IMAN1__IE 1U
+#define XHC_IMAN1__IE_L 1U
+#define XHC_IMAN1__IE_R 1U
+#define XHC_IMAN1__IE_WIDTH 1U
+#define XHC_IMAN1__IE_RESETVALUE 0x0U
+#define XHC_IMAN1__IP 0U
+#define XHC_IMAN1__IP_L 0U
+#define XHC_IMAN1__IP_R 0U
+#define XHC_IMAN1__IP_WIDTH 1U
+#define XHC_IMAN1__IP_RESETVALUE 0x0U
+#define XHC_IMAN1_WIDTH 32U
+#define XHC_IMAN1__WIDTH 32U
+#define XHC_IMAN1_ALL_L 31U
+#define XHC_IMAN1_ALL_R 0U
+#define XHC_IMAN1__ALL_L 31U
+#define XHC_IMAN1__ALL_R 0U
+#define XHC_IMAN1_DATAMASK 0xffffffffU
+#define XHC_IMAN1_RDWRMASK 0x00000000U
+#define XHC_IMAN1_RESETVALUE 0x00000000U
+
+#define XHC_IMOD1_OFFSET 0x4e4U
+#define XHC_IMOD1_BASE 0x4e4U
+#define XHC_IMOD1__IMODC_L 31U
+#define XHC_IMOD1__IMODC_R 16U
+#define XHC_IMOD1__IMODC_WIDTH 16U
+#define XHC_IMOD1__IMODC_RESETVALUE 0x0000U
+#define XHC_IMOD1__IMODI_L 15U
+#define XHC_IMOD1__IMODI_R 0U
+#define XHC_IMOD1__IMODI_WIDTH 16U
+#define XHC_IMOD1__IMODI_RESETVALUE 0x4000U
+#define XHC_IMOD1_WIDTH 32U
+#define XHC_IMOD1__WIDTH 32U
+#define XHC_IMOD1_ALL_L 31U
+#define XHC_IMOD1_ALL_R 0U
+#define XHC_IMOD1__ALL_L 31U
+#define XHC_IMOD1__ALL_R 0U
+#define XHC_IMOD1_DATAMASK 0xffffffffU
+#define XHC_IMOD1_RDWRMASK 0x00000000U
+#define XHC_IMOD1_RESETVALUE 0x00004000U
+
+#define XHC_ERSTSZ1_OFFSET 0x4e8U
+#define XHC_ERSTSZ1_BASE 0x4e8U
+#define XHC_ERSTSZ1__reserved_L 31U
+#define XHC_ERSTSZ1__reserved_R 16U
+#define XHC_ERSTSZ1__reserved_WIDTH 16U
+#define XHC_ERSTSZ1__reserved_RESETVALUE 0x0000U
+#define XHC_ERSTSZ1__TSZ_L 15U
+#define XHC_ERSTSZ1__TSZ_R 0U
+#define XHC_ERSTSZ1__TSZ_WIDTH 16U
+#define XHC_ERSTSZ1__TSZ_RESETVALUE 0x0000U
+#define XHC_ERSTSZ1_WIDTH 32U
+#define XHC_ERSTSZ1__WIDTH 32U
+#define XHC_ERSTSZ1_ALL_L 31U
+#define XHC_ERSTSZ1_ALL_R 0U
+#define XHC_ERSTSZ1__ALL_L 31U
+#define XHC_ERSTSZ1__ALL_R 0U
+#define XHC_ERSTSZ1_DATAMASK 0xffffffffU
+#define XHC_ERSTSZ1_RDWRMASK 0x00000000U
+#define XHC_ERSTSZ1_RESETVALUE 0x00000000U
+
+#define XHC_ERSTBAL1_OFFSET 0x4f0U
+#define XHC_ERSTBAL1_BASE 0x4f0U
+#define XHC_ERSTBAL1__BAL_L 31U
+#define XHC_ERSTBAL1__BAL_R 4U
+#define XHC_ERSTBAL1__BAL_WIDTH 28U
+#define XHC_ERSTBAL1__BAL_RESETVALUE 0x0000000U
+#define XHC_ERSTBAL1__reserved_L 3U
+#define XHC_ERSTBAL1__reserved_R 0U
+#define XHC_ERSTBAL1__reserved_WIDTH 4U
+#define XHC_ERSTBAL1__reserved_RESETVALUE 0x0U
+#define XHC_ERSTBAL1_WIDTH 32U
+#define XHC_ERSTBAL1__WIDTH 32U
+#define XHC_ERSTBAL1_ALL_L 31U
+#define XHC_ERSTBAL1_ALL_R 0U
+#define XHC_ERSTBAL1__ALL_L 31U
+#define XHC_ERSTBAL1__ALL_R 0U
+#define XHC_ERSTBAL1_DATAMASK 0xffffffffU
+#define XHC_ERSTBAL1_RDWRMASK 0x00000000U
+#define XHC_ERSTBAL1_RESETVALUE 0x00000000U
+
+#define XHC_ERSTBAH1_OFFSET 0x4f4U
+#define XHC_ERSTBAH1_BASE 0x4f4U
+#define XHC_ERSTBAH1__BAH_L 31U
+#define XHC_ERSTBAH1__BAH_R 0U
+#define XHC_ERSTBAH1__BAH_WIDTH 32U
+#define XHC_ERSTBAH1__BAH_RESETVALUE 0x00000000U
+#define XHC_ERSTBAH1_WIDTH 32U
+#define XHC_ERSTBAH1__WIDTH 32U
+#define XHC_ERSTBAH1_ALL_L 31U
+#define XHC_ERSTBAH1_ALL_R 0U
+#define XHC_ERSTBAH1__ALL_L 31U
+#define XHC_ERSTBAH1__ALL_R 0U
+#define XHC_ERSTBAH1_DATAMASK 0xffffffffU
+#define XHC_ERSTBAH1_RDWRMASK 0x00000000U
+#define XHC_ERSTBAH1_RESETVALUE 0x00000000U
+
+#define XHC_ERDPL1_OFFSET 0x4f8U
+#define XHC_ERDPL1_BASE 0x4f8U
+#define XHC_ERDPL1__DPL_L 31U
+#define XHC_ERDPL1__DPL_R 4U
+#define XHC_ERDPL1__DPL_WIDTH 28U
+#define XHC_ERDPL1__DPL_RESETVALUE 0x0000000U
+#define XHC_ERDPL1__EHB 3U
+#define XHC_ERDPL1__EHB_L 3U
+#define XHC_ERDPL1__EHB_R 3U
+#define XHC_ERDPL1__EHB_WIDTH 1U
+#define XHC_ERDPL1__EHB_RESETVALUE 0x0U
+#define XHC_ERDPL1__DESI_L 2U
+#define XHC_ERDPL1__DESI_R 0U
+#define XHC_ERDPL1__DESI_WIDTH 3U
+#define XHC_ERDPL1__DESI_RESETVALUE 0x0U
+#define XHC_ERDPL1_WIDTH 32U
+#define XHC_ERDPL1__WIDTH 32U
+#define XHC_ERDPL1_ALL_L 31U
+#define XHC_ERDPL1_ALL_R 0U
+#define XHC_ERDPL1__ALL_L 31U
+#define XHC_ERDPL1__ALL_R 0U
+#define XHC_ERDPL1_DATAMASK 0xffffffffU
+#define XHC_ERDPL1_RDWRMASK 0x00000000U
+#define XHC_ERDPL1_RESETVALUE 0x00000000U
+
+#define XHC_ERDPH1_OFFSET 0x4fcU
+#define XHC_ERDPH1_BASE 0x4fcU
+#define XHC_ERDPH1__DPH_L 31U
+#define XHC_ERDPH1__DPH_R 0U
+#define XHC_ERDPH1__DPH_WIDTH 32U
+#define XHC_ERDPH1__DPH_RESETVALUE 0x00000000U
+#define XHC_ERDPH1_WIDTH 32U
+#define XHC_ERDPH1__WIDTH 32U
+#define XHC_ERDPH1_ALL_L 31U
+#define XHC_ERDPH1_ALL_R 0U
+#define XHC_ERDPH1__ALL_L 31U
+#define XHC_ERDPH1__ALL_R 0U
+#define XHC_ERDPH1_DATAMASK 0xffffffffU
+#define XHC_ERDPH1_RDWRMASK 0x00000000U
+#define XHC_ERDPH1_RESETVALUE 0x00000000U
+
+#define XHC_DBLCMD_OFFSET 0x8c0U
+#define XHC_DBLCMD_BASE 0x8c0U
+#define XHC_DBLCMD__SID_L 31U
+#define XHC_DBLCMD__SID_R 16U
+#define XHC_DBLCMD__SID_WIDTH 16U
+#define XHC_DBLCMD__SID_RESETVALUE 0x0000U
+#define XHC_DBLCMD__reserved_L 15U
+#define XHC_DBLCMD__reserved_R 8U
+#define XHC_DBLCMD__reserved_WIDTH 8U
+#define XHC_DBLCMD__reserved_RESETVALUE 0x00U
+#define XHC_DBLCMD__TGT_L 7U
+#define XHC_DBLCMD__TGT_R 0U
+#define XHC_DBLCMD__TGT_WIDTH 8U
+#define XHC_DBLCMD__TGT_RESETVALUE 0x00U
+#define XHC_DBLCMD_WIDTH 32U
+#define XHC_DBLCMD__WIDTH 32U
+#define XHC_DBLCMD_ALL_L 31U
+#define XHC_DBLCMD_ALL_R 0U
+#define XHC_DBLCMD__ALL_L 31U
+#define XHC_DBLCMD__ALL_R 0U
+#define XHC_DBLCMD_DATAMASK 0xffffffffU
+#define XHC_DBLCMD_RDWRMASK 0x00000000U
+#define XHC_DBLCMD_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX1_OFFSET 0x8c4U
+#define XHC_DBLDVX1_BASE 0x8c4U
+#define XHC_DBLDVX1__SID_L 31U
+#define XHC_DBLDVX1__SID_R 16U
+#define XHC_DBLDVX1__SID_WIDTH 16U
+#define XHC_DBLDVX1__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX1__reserved_L 15U
+#define XHC_DBLDVX1__reserved_R 8U
+#define XHC_DBLDVX1__reserved_WIDTH 8U
+#define XHC_DBLDVX1__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX1__TGT_L 7U
+#define XHC_DBLDVX1__TGT_R 0U
+#define XHC_DBLDVX1__TGT_WIDTH 8U
+#define XHC_DBLDVX1__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX1_WIDTH 32U
+#define XHC_DBLDVX1__WIDTH 32U
+#define XHC_DBLDVX1_ALL_L 31U
+#define XHC_DBLDVX1_ALL_R 0U
+#define XHC_DBLDVX1__ALL_L 31U
+#define XHC_DBLDVX1__ALL_R 0U
+#define XHC_DBLDVX1_DATAMASK 0xffffffffU
+#define XHC_DBLDVX1_RDWRMASK 0x00000000U
+#define XHC_DBLDVX1_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX2_OFFSET 0x8c8U
+#define XHC_DBLDVX2_BASE 0x8c8U
+#define XHC_DBLDVX2__SID_L 31U
+#define XHC_DBLDVX2__SID_R 16U
+#define XHC_DBLDVX2__SID_WIDTH 16U
+#define XHC_DBLDVX2__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX2__reserved_L 15U
+#define XHC_DBLDVX2__reserved_R 8U
+#define XHC_DBLDVX2__reserved_WIDTH 8U
+#define XHC_DBLDVX2__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX2__TGT_L 7U
+#define XHC_DBLDVX2__TGT_R 0U
+#define XHC_DBLDVX2__TGT_WIDTH 8U
+#define XHC_DBLDVX2__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX2_WIDTH 32U
+#define XHC_DBLDVX2__WIDTH 32U
+#define XHC_DBLDVX2_ALL_L 31U
+#define XHC_DBLDVX2_ALL_R 0U
+#define XHC_DBLDVX2__ALL_L 31U
+#define XHC_DBLDVX2__ALL_R 0U
+#define XHC_DBLDVX2_DATAMASK 0xffffffffU
+#define XHC_DBLDVX2_RDWRMASK 0x00000000U
+#define XHC_DBLDVX2_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX3_OFFSET 0x8ccU
+#define XHC_DBLDVX3_BASE 0x8ccU
+#define XHC_DBLDVX3__SID_L 31U
+#define XHC_DBLDVX3__SID_R 16U
+#define XHC_DBLDVX3__SID_WIDTH 16U
+#define XHC_DBLDVX3__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX3__reserved_L 15U
+#define XHC_DBLDVX3__reserved_R 8U
+#define XHC_DBLDVX3__reserved_WIDTH 8U
+#define XHC_DBLDVX3__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX3__TGT_L 7U
+#define XHC_DBLDVX3__TGT_R 0U
+#define XHC_DBLDVX3__TGT_WIDTH 8U
+#define XHC_DBLDVX3__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX3_WIDTH 32U
+#define XHC_DBLDVX3__WIDTH 32U
+#define XHC_DBLDVX3_ALL_L 31U
+#define XHC_DBLDVX3_ALL_R 0U
+#define XHC_DBLDVX3__ALL_L 31U
+#define XHC_DBLDVX3__ALL_R 0U
+#define XHC_DBLDVX3_DATAMASK 0xffffffffU
+#define XHC_DBLDVX3_RDWRMASK 0x00000000U
+#define XHC_DBLDVX3_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX4_OFFSET 0x8d0U
+#define XHC_DBLDVX4_BASE 0x8d0U
+#define XHC_DBLDVX4__SID_L 31U
+#define XHC_DBLDVX4__SID_R 16U
+#define XHC_DBLDVX4__SID_WIDTH 16U
+#define XHC_DBLDVX4__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX4__reserved_L 15U
+#define XHC_DBLDVX4__reserved_R 8U
+#define XHC_DBLDVX4__reserved_WIDTH 8U
+#define XHC_DBLDVX4__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX4__TGT_L 7U
+#define XHC_DBLDVX4__TGT_R 0U
+#define XHC_DBLDVX4__TGT_WIDTH 8U
+#define XHC_DBLDVX4__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX4_WIDTH 32U
+#define XHC_DBLDVX4__WIDTH 32U
+#define XHC_DBLDVX4_ALL_L 31U
+#define XHC_DBLDVX4_ALL_R 0U
+#define XHC_DBLDVX4__ALL_L 31U
+#define XHC_DBLDVX4__ALL_R 0U
+#define XHC_DBLDVX4_DATAMASK 0xffffffffU
+#define XHC_DBLDVX4_RDWRMASK 0x00000000U
+#define XHC_DBLDVX4_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX5_OFFSET 0x8d4U
+#define XHC_DBLDVX5_BASE 0x8d4U
+#define XHC_DBLDVX5__SID_L 31U
+#define XHC_DBLDVX5__SID_R 16U
+#define XHC_DBLDVX5__SID_WIDTH 16U
+#define XHC_DBLDVX5__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX5__reserved_L 15U
+#define XHC_DBLDVX5__reserved_R 8U
+#define XHC_DBLDVX5__reserved_WIDTH 8U
+#define XHC_DBLDVX5__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX5__TGT_L 7U
+#define XHC_DBLDVX5__TGT_R 0U
+#define XHC_DBLDVX5__TGT_WIDTH 8U
+#define XHC_DBLDVX5__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX5_WIDTH 32U
+#define XHC_DBLDVX5__WIDTH 32U
+#define XHC_DBLDVX5_ALL_L 31U
+#define XHC_DBLDVX5_ALL_R 0U
+#define XHC_DBLDVX5__ALL_L 31U
+#define XHC_DBLDVX5__ALL_R 0U
+#define XHC_DBLDVX5_DATAMASK 0xffffffffU
+#define XHC_DBLDVX5_RDWRMASK 0x00000000U
+#define XHC_DBLDVX5_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX6_OFFSET 0x8d8U
+#define XHC_DBLDVX6_BASE 0x8d8U
+#define XHC_DBLDVX6__SID_L 31U
+#define XHC_DBLDVX6__SID_R 16U
+#define XHC_DBLDVX6__SID_WIDTH 16U
+#define XHC_DBLDVX6__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX6__reserved_L 15U
+#define XHC_DBLDVX6__reserved_R 8U
+#define XHC_DBLDVX6__reserved_WIDTH 8U
+#define XHC_DBLDVX6__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX6__TGT_L 7U
+#define XHC_DBLDVX6__TGT_R 0U
+#define XHC_DBLDVX6__TGT_WIDTH 8U
+#define XHC_DBLDVX6__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX6_WIDTH 32U
+#define XHC_DBLDVX6__WIDTH 32U
+#define XHC_DBLDVX6_ALL_L 31U
+#define XHC_DBLDVX6_ALL_R 0U
+#define XHC_DBLDVX6__ALL_L 31U
+#define XHC_DBLDVX6__ALL_R 0U
+#define XHC_DBLDVX6_DATAMASK 0xffffffffU
+#define XHC_DBLDVX6_RDWRMASK 0x00000000U
+#define XHC_DBLDVX6_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX7_OFFSET 0x8dcU
+#define XHC_DBLDVX7_BASE 0x8dcU
+#define XHC_DBLDVX7__SID_L 31U
+#define XHC_DBLDVX7__SID_R 16U
+#define XHC_DBLDVX7__SID_WIDTH 16U
+#define XHC_DBLDVX7__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX7__reserved_L 15U
+#define XHC_DBLDVX7__reserved_R 8U
+#define XHC_DBLDVX7__reserved_WIDTH 8U
+#define XHC_DBLDVX7__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX7__TGT_L 7U
+#define XHC_DBLDVX7__TGT_R 0U
+#define XHC_DBLDVX7__TGT_WIDTH 8U
+#define XHC_DBLDVX7__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX7_WIDTH 32U
+#define XHC_DBLDVX7__WIDTH 32U
+#define XHC_DBLDVX7_ALL_L 31U
+#define XHC_DBLDVX7_ALL_R 0U
+#define XHC_DBLDVX7__ALL_L 31U
+#define XHC_DBLDVX7__ALL_R 0U
+#define XHC_DBLDVX7_DATAMASK 0xffffffffU
+#define XHC_DBLDVX7_RDWRMASK 0x00000000U
+#define XHC_DBLDVX7_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX8_OFFSET 0x8e0U
+#define XHC_DBLDVX8_BASE 0x8e0U
+#define XHC_DBLDVX8__SID_L 31U
+#define XHC_DBLDVX8__SID_R 16U
+#define XHC_DBLDVX8__SID_WIDTH 16U
+#define XHC_DBLDVX8__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX8__reserved_L 15U
+#define XHC_DBLDVX8__reserved_R 8U
+#define XHC_DBLDVX8__reserved_WIDTH 8U
+#define XHC_DBLDVX8__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX8__TGT_L 7U
+#define XHC_DBLDVX8__TGT_R 0U
+#define XHC_DBLDVX8__TGT_WIDTH 8U
+#define XHC_DBLDVX8__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX8_WIDTH 32U
+#define XHC_DBLDVX8__WIDTH 32U
+#define XHC_DBLDVX8_ALL_L 31U
+#define XHC_DBLDVX8_ALL_R 0U
+#define XHC_DBLDVX8__ALL_L 31U
+#define XHC_DBLDVX8__ALL_R 0U
+#define XHC_DBLDVX8_DATAMASK 0xffffffffU
+#define XHC_DBLDVX8_RDWRMASK 0x00000000U
+#define XHC_DBLDVX8_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX9_OFFSET 0x8e4U
+#define XHC_DBLDVX9_BASE 0x8e4U
+#define XHC_DBLDVX9__SID_L 31U
+#define XHC_DBLDVX9__SID_R 16U
+#define XHC_DBLDVX9__SID_WIDTH 16U
+#define XHC_DBLDVX9__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX9__reserved_L 15U
+#define XHC_DBLDVX9__reserved_R 8U
+#define XHC_DBLDVX9__reserved_WIDTH 8U
+#define XHC_DBLDVX9__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX9__TGT_L 7U
+#define XHC_DBLDVX9__TGT_R 0U
+#define XHC_DBLDVX9__TGT_WIDTH 8U
+#define XHC_DBLDVX9__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX9_WIDTH 32U
+#define XHC_DBLDVX9__WIDTH 32U
+#define XHC_DBLDVX9_ALL_L 31U
+#define XHC_DBLDVX9_ALL_R 0U
+#define XHC_DBLDVX9__ALL_L 31U
+#define XHC_DBLDVX9__ALL_R 0U
+#define XHC_DBLDVX9_DATAMASK 0xffffffffU
+#define XHC_DBLDVX9_RDWRMASK 0x00000000U
+#define XHC_DBLDVX9_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX10_OFFSET 0x8e8U
+#define XHC_DBLDVX10_BASE 0x8e8U
+#define XHC_DBLDVX10__SID_L 31U
+#define XHC_DBLDVX10__SID_R 16U
+#define XHC_DBLDVX10__SID_WIDTH 16U
+#define XHC_DBLDVX10__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX10__reserved_L 15U
+#define XHC_DBLDVX10__reserved_R 8U
+#define XHC_DBLDVX10__reserved_WIDTH 8U
+#define XHC_DBLDVX10__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX10__TGT_L 7U
+#define XHC_DBLDVX10__TGT_R 0U
+#define XHC_DBLDVX10__TGT_WIDTH 8U
+#define XHC_DBLDVX10__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX10_WIDTH 32U
+#define XHC_DBLDVX10__WIDTH 32U
+#define XHC_DBLDVX10_ALL_L 31U
+#define XHC_DBLDVX10_ALL_R 0U
+#define XHC_DBLDVX10__ALL_L 31U
+#define XHC_DBLDVX10__ALL_R 0U
+#define XHC_DBLDVX10_DATAMASK 0xffffffffU
+#define XHC_DBLDVX10_RDWRMASK 0x00000000U
+#define XHC_DBLDVX10_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX11_OFFSET 0x8ecU
+#define XHC_DBLDVX11_BASE 0x8ecU
+#define XHC_DBLDVX11__SID_L 31U
+#define XHC_DBLDVX11__SID_R 16U
+#define XHC_DBLDVX11__SID_WIDTH 16U
+#define XHC_DBLDVX11__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX11__reserved_L 15U
+#define XHC_DBLDVX11__reserved_R 8U
+#define XHC_DBLDVX11__reserved_WIDTH 8U
+#define XHC_DBLDVX11__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX11__TGT_L 7U
+#define XHC_DBLDVX11__TGT_R 0U
+#define XHC_DBLDVX11__TGT_WIDTH 8U
+#define XHC_DBLDVX11__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX11_WIDTH 32U
+#define XHC_DBLDVX11__WIDTH 32U
+#define XHC_DBLDVX11_ALL_L 31U
+#define XHC_DBLDVX11_ALL_R 0U
+#define XHC_DBLDVX11__ALL_L 31U
+#define XHC_DBLDVX11__ALL_R 0U
+#define XHC_DBLDVX11_DATAMASK 0xffffffffU
+#define XHC_DBLDVX11_RDWRMASK 0x00000000U
+#define XHC_DBLDVX11_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX12_OFFSET 0x8f0U
+#define XHC_DBLDVX12_BASE 0x8f0U
+#define XHC_DBLDVX12__SID_L 31U
+#define XHC_DBLDVX12__SID_R 16U
+#define XHC_DBLDVX12__SID_WIDTH 16U
+#define XHC_DBLDVX12__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX12__reserved_L 15U
+#define XHC_DBLDVX12__reserved_R 8U
+#define XHC_DBLDVX12__reserved_WIDTH 8U
+#define XHC_DBLDVX12__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX12__TGT_L 7U
+#define XHC_DBLDVX12__TGT_R 0U
+#define XHC_DBLDVX12__TGT_WIDTH 8U
+#define XHC_DBLDVX12__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX12_WIDTH 32U
+#define XHC_DBLDVX12__WIDTH 32U
+#define XHC_DBLDVX12_ALL_L 31U
+#define XHC_DBLDVX12_ALL_R 0U
+#define XHC_DBLDVX12__ALL_L 31U
+#define XHC_DBLDVX12__ALL_R 0U
+#define XHC_DBLDVX12_DATAMASK 0xffffffffU
+#define XHC_DBLDVX12_RDWRMASK 0x00000000U
+#define XHC_DBLDVX12_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX13_OFFSET 0x8f4U
+#define XHC_DBLDVX13_BASE 0x8f4U
+#define XHC_DBLDVX13__SID_L 31U
+#define XHC_DBLDVX13__SID_R 16U
+#define XHC_DBLDVX13__SID_WIDTH 16U
+#define XHC_DBLDVX13__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX13__reserved_L 15U
+#define XHC_DBLDVX13__reserved_R 8U
+#define XHC_DBLDVX13__reserved_WIDTH 8U
+#define XHC_DBLDVX13__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX13__TGT_L 7U
+#define XHC_DBLDVX13__TGT_R 0U
+#define XHC_DBLDVX13__TGT_WIDTH 8U
+#define XHC_DBLDVX13__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX13_WIDTH 32U
+#define XHC_DBLDVX13__WIDTH 32U
+#define XHC_DBLDVX13_ALL_L 31U
+#define XHC_DBLDVX13_ALL_R 0U
+#define XHC_DBLDVX13__ALL_L 31U
+#define XHC_DBLDVX13__ALL_R 0U
+#define XHC_DBLDVX13_DATAMASK 0xffffffffU
+#define XHC_DBLDVX13_RDWRMASK 0x00000000U
+#define XHC_DBLDVX13_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX14_OFFSET 0x8f8U
+#define XHC_DBLDVX14_BASE 0x8f8U
+#define XHC_DBLDVX14__SID_L 31U
+#define XHC_DBLDVX14__SID_R 16U
+#define XHC_DBLDVX14__SID_WIDTH 16U
+#define XHC_DBLDVX14__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX14__reserved_L 15U
+#define XHC_DBLDVX14__reserved_R 8U
+#define XHC_DBLDVX14__reserved_WIDTH 8U
+#define XHC_DBLDVX14__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX14__TGT_L 7U
+#define XHC_DBLDVX14__TGT_R 0U
+#define XHC_DBLDVX14__TGT_WIDTH 8U
+#define XHC_DBLDVX14__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX14_WIDTH 32U
+#define XHC_DBLDVX14__WIDTH 32U
+#define XHC_DBLDVX14_ALL_L 31U
+#define XHC_DBLDVX14_ALL_R 0U
+#define XHC_DBLDVX14__ALL_L 31U
+#define XHC_DBLDVX14__ALL_R 0U
+#define XHC_DBLDVX14_DATAMASK 0xffffffffU
+#define XHC_DBLDVX14_RDWRMASK 0x00000000U
+#define XHC_DBLDVX14_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX15_OFFSET 0x8fcU
+#define XHC_DBLDVX15_BASE 0x8fcU
+#define XHC_DBLDVX15__SID_L 31U
+#define XHC_DBLDVX15__SID_R 16U
+#define XHC_DBLDVX15__SID_WIDTH 16U
+#define XHC_DBLDVX15__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX15__reserved_L 15U
+#define XHC_DBLDVX15__reserved_R 8U
+#define XHC_DBLDVX15__reserved_WIDTH 8U
+#define XHC_DBLDVX15__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX15__TGT_L 7U
+#define XHC_DBLDVX15__TGT_R 0U
+#define XHC_DBLDVX15__TGT_WIDTH 8U
+#define XHC_DBLDVX15__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX15_WIDTH 32U
+#define XHC_DBLDVX15__WIDTH 32U
+#define XHC_DBLDVX15_ALL_L 31U
+#define XHC_DBLDVX15_ALL_R 0U
+#define XHC_DBLDVX15__ALL_L 31U
+#define XHC_DBLDVX15__ALL_R 0U
+#define XHC_DBLDVX15_DATAMASK 0xffffffffU
+#define XHC_DBLDVX15_RDWRMASK 0x00000000U
+#define XHC_DBLDVX15_RESETVALUE 0x00000000U
+
+#define XHC_DBLDVX16_OFFSET 0x900U
+#define XHC_DBLDVX16_BASE 0x900U
+#define XHC_DBLDVX16__SID_L 31U
+#define XHC_DBLDVX16__SID_R 16U
+#define XHC_DBLDVX16__SID_WIDTH 16U
+#define XHC_DBLDVX16__SID_RESETVALUE 0x0000U
+#define XHC_DBLDVX16__reserved_L 15U
+#define XHC_DBLDVX16__reserved_R 8U
+#define XHC_DBLDVX16__reserved_WIDTH 8U
+#define XHC_DBLDVX16__reserved_RESETVALUE 0x00U
+#define XHC_DBLDVX16__TGT_L 7U
+#define XHC_DBLDVX16__TGT_R 0U
+#define XHC_DBLDVX16__TGT_WIDTH 8U
+#define XHC_DBLDVX16__TGT_RESETVALUE 0x00U
+#define XHC_DBLDVX16_WIDTH 32U
+#define XHC_DBLDVX16__WIDTH 32U
+#define XHC_DBLDVX16_ALL_L 31U
+#define XHC_DBLDVX16_ALL_R 0U
+#define XHC_DBLDVX16__ALL_L 31U
+#define XHC_DBLDVX16__ALL_R 0U
+#define XHC_DBLDVX16_DATAMASK 0xffffffffU
+#define XHC_DBLDVX16_RDWRMASK 0x00000000U
+#define XHC_DBLDVX16_RESETVALUE 0x00000000U
+
+#define XHC_ECHSPT3_OFFSET 0x940U
+#define XHC_ECHSPT3_BASE 0x940U
+#define XHC_ECHSPT3__RMAJ_L 31U
+#define XHC_ECHSPT3__RMAJ_R 24U
+#define XHC_ECHSPT3__RMAJ_WIDTH 8U
+#define XHC_ECHSPT3__RMAJ_RESETVALUE 0x00U
+#define XHC_ECHSPT3__RMIN_L 23U
+#define XHC_ECHSPT3__RMIN_R 16U
+#define XHC_ECHSPT3__RMIN_WIDTH 8U
+#define XHC_ECHSPT3__RMIN_RESETVALUE 0x00U
+#define XHC_ECHSPT3__NCP_L 15U
+#define XHC_ECHSPT3__NCP_R 8U
+#define XHC_ECHSPT3__NCP_WIDTH 8U
+#define XHC_ECHSPT3__NCP_RESETVALUE 0x00U
+#define XHC_ECHSPT3__CID_L 7U
+#define XHC_ECHSPT3__CID_R 0U
+#define XHC_ECHSPT3__CID_WIDTH 8U
+#define XHC_ECHSPT3__CID_RESETVALUE 0x02U
+#define XHC_ECHSPT3_WIDTH 32U
+#define XHC_ECHSPT3__WIDTH 32U
+#define XHC_ECHSPT3_ALL_L 31U
+#define XHC_ECHSPT3_ALL_R 0U
+#define XHC_ECHSPT3__ALL_L 31U
+#define XHC_ECHSPT3__ALL_R 0U
+#define XHC_ECHSPT3_DATAMASK 0xffffffffU
+#define XHC_ECHSPT3_RDWRMASK 0x00000000U
+#define XHC_ECHSPT3_RESETVALUE 0x00000002U
+
+#define XHC_PNSTR3_OFFSET 0x944U
+#define XHC_PNSTR3_BASE 0x944U
+#define XHC_PNSTR3__STR_L 31U
+#define XHC_PNSTR3__STR_R 0U
+#define XHC_PNSTR3__STR_WIDTH 32U
+#define XHC_PNSTR3__STR_RESETVALUE 0x20425355U
+#define XHC_PNSTR3_WIDTH 32U
+#define XHC_PNSTR3__WIDTH 32U
+#define XHC_PNSTR3_ALL_L 31U
+#define XHC_PNSTR3_ALL_R 0U
+#define XHC_PNSTR3__ALL_L 31U
+#define XHC_PNSTR3__ALL_R 0U
+#define XHC_PNSTR3_DATAMASK 0xffffffffU
+#define XHC_PNSTR3_RDWRMASK 0x00000000U
+#define XHC_PNSTR3_RESETVALUE 0x20425355U
+
+#define XHC_PSUM3_OFFSET 0x948U
+#define XHC_PSUM3_BASE 0x948U
+#define XHC_PSUM3__PSIC_L 31U
+#define XHC_PSUM3__PSIC_R 28U
+#define XHC_PSUM3__PSIC_WIDTH 4U
+#define XHC_PSUM3__PSIC_RESETVALUE 0x0U
+#define XHC_PSUM3__MHD_L 27U
+#define XHC_PSUM3__MHD_R 25U
+#define XHC_PSUM3__MHD_WIDTH 3U
+#define XHC_PSUM3__MHD_RESETVALUE 0x0U
+#define XHC_PSUM3__BLC 20U
+#define XHC_PSUM3__BLC_L 20U
+#define XHC_PSUM3__BLC_R 20U
+#define XHC_PSUM3__BLC_WIDTH 1U
+#define XHC_PSUM3__BLC_RESETVALUE 0x0U
+#define XHC_PSUM3__HLC 19U
+#define XHC_PSUM3__HLC_L 19U
+#define XHC_PSUM3__HLC_R 19U
+#define XHC_PSUM3__HLC_WIDTH 1U
+#define XHC_PSUM3__HLC_RESETVALUE 0x1U
+#define XHC_PSUM3__IHI 18U
+#define XHC_PSUM3__IHI_L 18U
+#define XHC_PSUM3__IHI_R 18U
+#define XHC_PSUM3__IHI_WIDTH 1U
+#define XHC_PSUM3__IHI_RESETVALUE 0x0U
+#define XHC_PSUM3__HSO 17U
+#define XHC_PSUM3__HSO_L 17U
+#define XHC_PSUM3__HSO_R 17U
+#define XHC_PSUM3__HSO_WIDTH 1U
+#define XHC_PSUM3__HSO_RESETVALUE 0x0U
+#define XHC_PSUM3__reserved 16U
+#define XHC_PSUM3__reserved_L 16U
+#define XHC_PSUM3__reserved_R 16U
+#define XHC_PSUM3__reserved_WIDTH 1U
+#define XHC_PSUM3__reserved_RESETVALUE 0x0U
+#define XHC_PSUM3__CPC_L 15U
+#define XHC_PSUM3__CPC_R 8U
+#define XHC_PSUM3__CPC_WIDTH 8U
+#define XHC_PSUM3__CPC_RESETVALUE 0x00U
+#define XHC_PSUM3__CPO_L 7U
+#define XHC_PSUM3__CPO_R 0U
+#define XHC_PSUM3__CPO_WIDTH 8U
+#define XHC_PSUM3__CPO_RESETVALUE 0x00U
+#define XHC_PSUM3__RESERVED_L 24U
+#define XHC_PSUM3__RESERVED_R 21U
+#define XHC_PSUM3_WIDTH 32U
+#define XHC_PSUM3__WIDTH 32U
+#define XHC_PSUM3_ALL_L 31U
+#define XHC_PSUM3_ALL_R 0U
+#define XHC_PSUM3__ALL_L 31U
+#define XHC_PSUM3__ALL_R 0U
+#define XHC_PSUM3_DATAMASK 0xfe1fffffU
+#define XHC_PSUM3_RDWRMASK 0x01e00000U
+#define XHC_PSUM3_RESETVALUE 0x00080000U
+
+#define XHC_PTSLTYP3_OFFSET 0x94cU
+#define XHC_PTSLTYP3_BASE 0x94cU
+#define XHC_PTSLTYP3__reserved_L 31U
+#define XHC_PTSLTYP3__reserved_R 5U
+#define XHC_PTSLTYP3__reserved_WIDTH 27U
+#define XHC_PTSLTYP3__reserved_RESETVALUE 0x0U
+#define XHC_PTSLTYP3__PST_L 4U
+#define XHC_PTSLTYP3__PST_R 0U
+#define XHC_PTSLTYP3__PST_WIDTH 5U
+#define XHC_PTSLTYP3__PST_RESETVALUE 0x0U
+#define XHC_PTSLTYP3_WIDTH 32U
+#define XHC_PTSLTYP3__WIDTH 32U
+#define XHC_PTSLTYP3_ALL_L 31U
+#define XHC_PTSLTYP3_ALL_R 0U
+#define XHC_PTSLTYP3__ALL_L 31U
+#define XHC_PTSLTYP3__ALL_R 0U
+#define XHC_PTSLTYP3_DATAMASK 0xffffffffU
+#define XHC_PTSLTYP3_RDWRMASK 0x00000000U
+#define XHC_PTSLTYP3_RESETVALUE 0x00000000U
+
+#define XHC_ECHSPT2_OFFSET 0x950U
+#define XHC_ECHSPT2_BASE 0x950U
+#define XHC_ECHSPT2__RMAJ_L 31U
+#define XHC_ECHSPT2__RMAJ_R 24U
+#define XHC_ECHSPT2__RMAJ_WIDTH 8U
+#define XHC_ECHSPT2__RMAJ_RESETVALUE 0x00U
+#define XHC_ECHSPT2__RMIN_L 23U
+#define XHC_ECHSPT2__RMIN_R 16U
+#define XHC_ECHSPT2__RMIN_WIDTH 8U
+#define XHC_ECHSPT2__RMIN_RESETVALUE 0x00U
+#define XHC_ECHSPT2__NCP_L 15U
+#define XHC_ECHSPT2__NCP_R 8U
+#define XHC_ECHSPT2__NCP_WIDTH 8U
+#define XHC_ECHSPT2__NCP_RESETVALUE 0x00U
+#define XHC_ECHSPT2__CID_L 7U
+#define XHC_ECHSPT2__CID_R 0U
+#define XHC_ECHSPT2__CID_WIDTH 8U
+#define XHC_ECHSPT2__CID_RESETVALUE 0x02U
+#define XHC_ECHSPT2_WIDTH 32U
+#define XHC_ECHSPT2__WIDTH 32U
+#define XHC_ECHSPT2_ALL_L 31U
+#define XHC_ECHSPT2_ALL_R 0U
+#define XHC_ECHSPT2__ALL_L 31U
+#define XHC_ECHSPT2__ALL_R 0U
+#define XHC_ECHSPT2_DATAMASK 0xffffffffU
+#define XHC_ECHSPT2_RDWRMASK 0x00000000U
+#define XHC_ECHSPT2_RESETVALUE 0x00000002U
+
+#define XHC_PNSTR2_OFFSET 0x954U
+#define XHC_PNSTR2_BASE 0x954U
+#define XHC_PNSTR2__STR_L 31U
+#define XHC_PNSTR2__STR_R 0U
+#define XHC_PNSTR2__STR_WIDTH 32U
+#define XHC_PNSTR2__STR_RESETVALUE 0x20425355U
+#define XHC_PNSTR2_WIDTH 32U
+#define XHC_PNSTR2__WIDTH 32U
+#define XHC_PNSTR2_ALL_L 31U
+#define XHC_PNSTR2_ALL_R 0U
+#define XHC_PNSTR2__ALL_L 31U
+#define XHC_PNSTR2__ALL_R 0U
+#define XHC_PNSTR2_DATAMASK 0xffffffffU
+#define XHC_PNSTR2_RDWRMASK 0x00000000U
+#define XHC_PNSTR2_RESETVALUE 0x20425355U
+
+#define XHC_PSUM2_OFFSET 0x958U
+#define XHC_PSUM2_BASE 0x958U
+#define XHC_PSUM2__PSIC_L 31U
+#define XHC_PSUM2__PSIC_R 28U
+#define XHC_PSUM2__PSIC_WIDTH 4U
+#define XHC_PSUM2__PSIC_RESETVALUE 0x0U
+#define XHC_PSUM2__MHD_L 27U
+#define XHC_PSUM2__MHD_R 25U
+#define XHC_PSUM2__MHD_WIDTH 3U
+#define XHC_PSUM2__MHD_RESETVALUE 0x0U
+#define XHC_PSUM2__BLC 20U
+#define XHC_PSUM2__BLC_L 20U
+#define XHC_PSUM2__BLC_R 20U
+#define XHC_PSUM2__BLC_WIDTH 1U
+#define XHC_PSUM2__BLC_RESETVALUE 0x0U
+#define XHC_PSUM2__HLC 19U
+#define XHC_PSUM2__HLC_L 19U
+#define XHC_PSUM2__HLC_R 19U
+#define XHC_PSUM2__HLC_WIDTH 1U
+#define XHC_PSUM2__HLC_RESETVALUE 0x1U
+#define XHC_PSUM2__IHI 18U
+#define XHC_PSUM2__IHI_L 18U
+#define XHC_PSUM2__IHI_R 18U
+#define XHC_PSUM2__IHI_WIDTH 1U
+#define XHC_PSUM2__IHI_RESETVALUE 0x0U
+#define XHC_PSUM2__HSO 17U
+#define XHC_PSUM2__HSO_L 17U
+#define XHC_PSUM2__HSO_R 17U
+#define XHC_PSUM2__HSO_WIDTH 1U
+#define XHC_PSUM2__HSO_RESETVALUE 0x0U
+#define XHC_PSUM2__reserved 16U
+#define XHC_PSUM2__reserved_L 16U
+#define XHC_PSUM2__reserved_R 16U
+#define XHC_PSUM2__reserved_WIDTH 1U
+#define XHC_PSUM2__reserved_RESETVALUE 0x0U
+#define XHC_PSUM2__CPC_L 15U
+#define XHC_PSUM2__CPC_R 8U
+#define XHC_PSUM2__CPC_WIDTH 8U
+#define XHC_PSUM2__CPC_RESETVALUE 0x00U
+#define XHC_PSUM2__CPO_L 7U
+#define XHC_PSUM2__CPO_R 0U
+#define XHC_PSUM2__CPO_WIDTH 8U
+#define XHC_PSUM2__CPO_RESETVALUE 0x00U
+#define XHC_PSUM2__RESERVED_L 24U
+#define XHC_PSUM2__RESERVED_R 21U
+#define XHC_PSUM2_WIDTH 32U
+#define XHC_PSUM2__WIDTH 32U
+#define XHC_PSUM2_ALL_L 31U
+#define XHC_PSUM2_ALL_R 0U
+#define XHC_PSUM2__ALL_L 31U
+#define XHC_PSUM2__ALL_R 0U
+#define XHC_PSUM2_DATAMASK 0xfe1fffffU
+#define XHC_PSUM2_RDWRMASK 0x01e00000U
+#define XHC_PSUM2_RESETVALUE 0x00080000U
+
+#define XHC_PTSLTYP2_OFFSET 0x95cU
+#define XHC_PTSLTYP2_BASE 0x95cU
+#define XHC_PTSLTYP2__reserved_L 31U
+#define XHC_PTSLTYP2__reserved_R 5U
+#define XHC_PTSLTYP2__reserved_WIDTH 27U
+#define XHC_PTSLTYP2__reserved_RESETVALUE 0x0U
+#define XHC_PTSLTYP2__PST_L 4U
+#define XHC_PTSLTYP2__PST_R 0U
+#define XHC_PTSLTYP2__PST_WIDTH 5U
+#define XHC_PTSLTYP2__PST_RESETVALUE 0x0U
+#define XHC_PTSLTYP2_WIDTH 32U
+#define XHC_PTSLTYP2__WIDTH 32U
+#define XHC_PTSLTYP2_ALL_L 31U
+#define XHC_PTSLTYP2_ALL_R 0U
+#define XHC_PTSLTYP2__ALL_L 31U
+#define XHC_PTSLTYP2__ALL_R 0U
+#define XHC_PTSLTYP2_DATAMASK 0xffffffffU
+#define XHC_PTSLTYP2_RDWRMASK 0x00000000U
+#define XHC_PTSLTYP2_RESETVALUE 0x00000000U
+
+#define XHC_ECHRSVP_OFFSET 0x960U
+#define XHC_ECHRSVP_BASE 0x960U
+#define XHC_ECHRSVP__reserved_L 31U
+#define XHC_ECHRSVP__reserved_R 16U
+#define XHC_ECHRSVP__reserved_WIDTH 16U
+#define XHC_ECHRSVP__reserved_RESETVALUE 0x0000U
+#define XHC_ECHRSVP__NCP_L 15U
+#define XHC_ECHRSVP__NCP_R 8U
+#define XHC_ECHRSVP__NCP_WIDTH 8U
+#define XHC_ECHRSVP__NCP_RESETVALUE 0x00U
+#define XHC_ECHRSVP__CID_L 7U
+#define XHC_ECHRSVP__CID_R 0U
+#define XHC_ECHRSVP__CID_WIDTH 8U
+#define XHC_ECHRSVP__CID_RESETVALUE 0xffU
+#define XHC_ECHRSVP_WIDTH 32U
+#define XHC_ECHRSVP__WIDTH 32U
+#define XHC_ECHRSVP_ALL_L 31U
+#define XHC_ECHRSVP_ALL_R 0U
+#define XHC_ECHRSVP__ALL_L 31U
+#define XHC_ECHRSVP__ALL_R 0U
+#define XHC_ECHRSVP_DATAMASK 0xffffffffU
+#define XHC_ECHRSVP_RDWRMASK 0x00000000U
+#define XHC_ECHRSVP_RESETVALUE 0x000000ffU
+
+#define XHC_ECHRSVI_OFFSET 0x968U
+#define XHC_ECHRSVI_BASE 0x968U
+#define XHC_ECHRSVI__reserved_L 31U
+#define XHC_ECHRSVI__reserved_R 16U
+#define XHC_ECHRSVI__reserved_WIDTH 16U
+#define XHC_ECHRSVI__reserved_RESETVALUE 0x0000U
+#define XHC_ECHRSVI__NCP_L 15U
+#define XHC_ECHRSVI__NCP_R 8U
+#define XHC_ECHRSVI__NCP_WIDTH 8U
+#define XHC_ECHRSVI__NCP_RESETVALUE 0x00U
+#define XHC_ECHRSVI__CID_L 7U
+#define XHC_ECHRSVI__CID_R 0U
+#define XHC_ECHRSVI__CID_WIDTH 8U
+#define XHC_ECHRSVI__CID_RESETVALUE 0xffU
+#define XHC_ECHRSVI_WIDTH 32U
+#define XHC_ECHRSVI__WIDTH 32U
+#define XHC_ECHRSVI_ALL_L 31U
+#define XHC_ECHRSVI_ALL_R 0U
+#define XHC_ECHRSVI__ALL_L 31U
+#define XHC_ECHRSVI__ALL_R 0U
+#define XHC_ECHRSVI_DATAMASK 0xffffffffU
+#define XHC_ECHRSVI_RDWRMASK 0x00000000U
+#define XHC_ECHRSVI_RESETVALUE 0x000000ffU
+
+#define XHC_ECHRSVM_OFFSET 0xae8U
+#define XHC_ECHRSVM_BASE 0xae8U
+#define XHC_ECHRSVM__reserved_L 31U
+#define XHC_ECHRSVM__reserved_R 16U
+#define XHC_ECHRSVM__reserved_WIDTH 16U
+#define XHC_ECHRSVM__reserved_RESETVALUE 0x0000U
+#define XHC_ECHRSVM__NCP_L 15U
+#define XHC_ECHRSVM__NCP_R 8U
+#define XHC_ECHRSVM__NCP_WIDTH 8U
+#define XHC_ECHRSVM__NCP_RESETVALUE 0x00U
+#define XHC_ECHRSVM__CID_L 7U
+#define XHC_ECHRSVM__CID_R 0U
+#define XHC_ECHRSVM__CID_WIDTH 8U
+#define XHC_ECHRSVM__CID_RESETVALUE 0xffU
+#define XHC_ECHRSVM_WIDTH 32U
+#define XHC_ECHRSVM__WIDTH 32U
+#define XHC_ECHRSVM_ALL_L 31U
+#define XHC_ECHRSVM_ALL_R 0U
+#define XHC_ECHRSVM__ALL_L 31U
+#define XHC_ECHRSVM__ALL_R 0U
+#define XHC_ECHRSVM_DATAMASK 0xffffffffU
+#define XHC_ECHRSVM_RDWRMASK 0x00000000U
+#define XHC_ECHRSVM_RESETVALUE 0x000000ffU
+
+#define XHC_ECHRSVD_OFFSET 0xaf8U
+#define XHC_ECHRSVD_BASE 0xaf8U
+#define XHC_ECHRSVD__reserved_L 31U
+#define XHC_ECHRSVD__reserved_R 16U
+#define XHC_ECHRSVD__reserved_WIDTH 16U
+#define XHC_ECHRSVD__reserved_RESETVALUE 0x0000U
+#define XHC_ECHRSVD__NCP_L 15U
+#define XHC_ECHRSVD__NCP_R 8U
+#define XHC_ECHRSVD__NCP_WIDTH 8U
+#define XHC_ECHRSVD__NCP_RESETVALUE 0x00U
+#define XHC_ECHRSVD__CID_L 7U
+#define XHC_ECHRSVD__CID_R 0U
+#define XHC_ECHRSVD__CID_WIDTH 8U
+#define XHC_ECHRSVD__CID_RESETVALUE 0xffU
+#define XHC_ECHRSVD_WIDTH 32U
+#define XHC_ECHRSVD__WIDTH 32U
+#define XHC_ECHRSVD_ALL_L 31U
+#define XHC_ECHRSVD_ALL_R 0U
+#define XHC_ECHRSVD__ALL_L 31U
+#define XHC_ECHRSVD__ALL_R 0U
+#define XHC_ECHRSVD_DATAMASK 0xffffffffU
+#define XHC_ECHRSVD_RDWRMASK 0x00000000U
+#define XHC_ECHRSVD_RESETVALUE 0x000000ffU
+
+#define XHC_ECHRSVO_OFFSET 0xb38U
+#define XHC_ECHRSVO_BASE 0xb38U
+#define XHC_ECHRSVO__reserved_L 31U
+#define XHC_ECHRSVO__reserved_R 16U
+#define XHC_ECHRSVO__reserved_WIDTH 16U
+#define XHC_ECHRSVO__reserved_RESETVALUE 0x0000U
+#define XHC_ECHRSVO__NCP_L 15U
+#define XHC_ECHRSVO__NCP_R 8U
+#define XHC_ECHRSVO__NCP_WIDTH 8U
+#define XHC_ECHRSVO__NCP_RESETVALUE 0x00U
+#define XHC_ECHRSVO__CID_L 7U
+#define XHC_ECHRSVO__CID_R 0U
+#define XHC_ECHRSVO__CID_WIDTH 8U
+#define XHC_ECHRSVO__CID_RESETVALUE 0xffU
+#define XHC_ECHRSVO_WIDTH 32U
+#define XHC_ECHRSVO__WIDTH 32U
+#define XHC_ECHRSVO_ALL_L 31U
+#define XHC_ECHRSVO_ALL_R 0U
+#define XHC_ECHRSVO__ALL_L 31U
+#define XHC_ECHRSVO__ALL_R 0U
+#define XHC_ECHRSVO_DATAMASK 0xffffffffU
+#define XHC_ECHRSVO_RDWRMASK 0x00000000U
+#define XHC_ECHRSVO_RESETVALUE 0x000000ffU
+
+#define XHC_ECHCTT_OFFSET 0xbf0U
+#define XHC_ECHCTT_BASE 0xbf0U
+#define XHC_ECHCTT__reserved_L 31U
+#define XHC_ECHCTT__reserved_R 16U
+#define XHC_ECHCTT__reserved_WIDTH 16U
+#define XHC_ECHCTT__reserved_RESETVALUE 0x0000U
+#define XHC_ECHCTT__NCP_L 15U
+#define XHC_ECHCTT__NCP_R 8U
+#define XHC_ECHCTT__NCP_WIDTH 8U
+#define XHC_ECHCTT__NCP_RESETVALUE 0x04U
+#define XHC_ECHCTT__CID_L 7U
+#define XHC_ECHCTT__CID_R 0U
+#define XHC_ECHCTT__CID_WIDTH 8U
+#define XHC_ECHCTT__CID_RESETVALUE 0xe0U
+#define XHC_ECHCTT_WIDTH 32U
+#define XHC_ECHCTT__WIDTH 32U
+#define XHC_ECHCTT_ALL_L 31U
+#define XHC_ECHCTT_ALL_R 0U
+#define XHC_ECHCTT__ALL_L 31U
+#define XHC_ECHCTT__ALL_R 0U
+#define XHC_ECHCTT_DATAMASK 0xffffffffU
+#define XHC_ECHCTT_RDWRMASK 0x00000000U
+#define XHC_ECHCTT_RESETVALUE 0x000004e0U
+
+#define XHC_CTTMTS0_OFFSET 0xbf8U
+#define XHC_CTTMTS0_BASE 0xbf8U
+#define XHC_CTTMTS0__DCM 31U
+#define XHC_CTTMTS0__DCM_L 31U
+#define XHC_CTTMTS0__DCM_R 31U
+#define XHC_CTTMTS0__DCM_WIDTH 1U
+#define XHC_CTTMTS0__DCM_RESETVALUE 0x0U
+#define XHC_CTTMTS0__reserved_L 30U
+#define XHC_CTTMTS0__reserved_R 10U
+#define XHC_CTTMTS0__reserved_WIDTH 21U
+#define XHC_CTTMTS0__reserved_RESETVALUE 0x0U
+#define XHC_CTTMTS0__SLA_L 9U
+#define XHC_CTTMTS0__SLA_R 0U
+#define XHC_CTTMTS0__SLA_WIDTH 10U
+#define XHC_CTTMTS0__SLA_RESETVALUE 0x0U
+#define XHC_CTTMTS0_WIDTH 32U
+#define XHC_CTTMTS0__WIDTH 32U
+#define XHC_CTTMTS0_ALL_L 31U
+#define XHC_CTTMTS0_ALL_R 0U
+#define XHC_CTTMTS0__ALL_L 31U
+#define XHC_CTTMTS0__ALL_R 0U
+#define XHC_CTTMTS0_DATAMASK 0xffffffffU
+#define XHC_CTTMTS0_RDWRMASK 0x00000000U
+#define XHC_CTTMTS0_RESETVALUE 0x00000000U
+
+#define XHC_CTTMTS1_OFFSET 0xbfcU
+#define XHC_CTTMTS1_BASE 0xbfcU
+#define XHC_CTTMTS1__TXF_L 25U
+#define XHC_CTTMTS1__TXF_R 16U
+#define XHC_CTTMTS1__TXF_WIDTH 10U
+#define XHC_CTTMTS1__TXF_RESETVALUE 0x0U
+#define XHC_CTTMTS1__reserved_L 15U
+#define XHC_CTTMTS1__reserved_R 10U
+#define XHC_CTTMTS1__reserved_WIDTH 6U
+#define XHC_CTTMTS1__reserved_RESETVALUE 0x0U
+#define XHC_CTTMTS1__RXF_L 9U
+#define XHC_CTTMTS1__RXF_R 0U
+#define XHC_CTTMTS1__RXF_WIDTH 10U
+#define XHC_CTTMTS1__RXF_RESETVALUE 0x0U
+#define XHC_CTTMTS1__RESERVED_L 31U
+#define XHC_CTTMTS1__RESERVED_R 26U
+#define XHC_CTTMTS1_WIDTH 26U
+#define XHC_CTTMTS1__WIDTH 26U
+#define XHC_CTTMTS1_ALL_L 25U
+#define XHC_CTTMTS1_ALL_R 0U
+#define XHC_CTTMTS1__ALL_L 25U
+#define XHC_CTTMTS1__ALL_R 0U
+#define XHC_CTTMTS1_DATAMASK 0x03ffffffU
+#define XHC_CTTMTS1_RDWRMASK 0xfc000000U
+#define XHC_CTTMTS1_RESETVALUE 0x0000000U
+
+#define XHC_ECHBIU_OFFSET 0xc00U
+#define XHC_ECHBIU_BASE 0xc00U
+#define XHC_ECHBIU__CLK_L 31U
+#define XHC_ECHBIU__CLK_R 21U
+#define XHC_ECHBIU__CLK_WIDTH 11U
+#define XHC_ECHBIU__CLK_RESETVALUE 0x0U
+#define XHC_ECHBIU__reserved_L 20U
+#define XHC_ECHBIU__reserved_R 19U
+#define XHC_ECHBIU__reserved_WIDTH 2U
+#define XHC_ECHBIU__reserved_RESETVALUE 0x0U
+#define XHC_ECHBIU__WID_L 18U
+#define XHC_ECHBIU__WID_R 16U
+#define XHC_ECHBIU__WID_WIDTH 3U
+#define XHC_ECHBIU__WID_RESETVALUE 0x0U
+#define XHC_ECHBIU__NCP_L 15U
+#define XHC_ECHBIU__NCP_R 8U
+#define XHC_ECHBIU__NCP_WIDTH 8U
+#define XHC_ECHBIU__NCP_RESETVALUE 0x08U
+#define XHC_ECHBIU__CID_L 7U
+#define XHC_ECHBIU__CID_R 0U
+#define XHC_ECHBIU__CID_WIDTH 8U
+#define XHC_ECHBIU__CID_RESETVALUE 0xc0U
+#define XHC_ECHBIU_WIDTH 32U
+#define XHC_ECHBIU__WIDTH 32U
+#define XHC_ECHBIU_ALL_L 31U
+#define XHC_ECHBIU_ALL_R 0U
+#define XHC_ECHBIU__ALL_L 31U
+#define XHC_ECHBIU__ALL_R 0U
+#define XHC_ECHBIU_DATAMASK 0xffffffffU
+#define XHC_ECHBIU_RDWRMASK 0x00000000U
+#define XHC_ECHBIU_RESETVALUE 0x000008c0U
+
+#define XHC_BIUSPC_OFFSET 0xc04U
+#define XHC_BIUSPC_BASE 0xc04U
+#define XHC_BIUSPC__MAJ_L 31U
+#define XHC_BIUSPC__MAJ_R 28U
+#define XHC_BIUSPC__MAJ_WIDTH 4U
+#define XHC_BIUSPC__MAJ_RESETVALUE 0x0U
+#define XHC_BIUSPC__MIN_L 27U
+#define XHC_BIUSPC__MIN_R 24U
+#define XHC_BIUSPC__MIN_WIDTH 4U
+#define XHC_BIUSPC__MIN_RESETVALUE 0x0U
+#define XHC_BIUSPC__RLS_L 23U
+#define XHC_BIUSPC__RLS_R 20U
+#define XHC_BIUSPC__RLS_WIDTH 4U
+#define XHC_BIUSPC__RLS_RESETVALUE 0x0U
+#define XHC_BIUSPC__reserved_L 19U
+#define XHC_BIUSPC__reserved_R 4U
+#define XHC_BIUSPC__reserved_WIDTH 16U
+#define XHC_BIUSPC__reserved_RESETVALUE 0x0000U
+#define XHC_BIUSPC__SPI_L 3U
+#define XHC_BIUSPC__SPI_R 2U
+#define XHC_BIUSPC__SPI_WIDTH 2U
+#define XHC_BIUSPC__SPI_RESETVALUE 0x3U
+#define XHC_BIUSPC__TYP_L 1U
+#define XHC_BIUSPC__TYP_R 0U
+#define XHC_BIUSPC__TYP_WIDTH 2U
+#define XHC_BIUSPC__TYP_RESETVALUE 0x0U
+#define XHC_BIUSPC_WIDTH 32U
+#define XHC_BIUSPC__WIDTH 32U
+#define XHC_BIUSPC_ALL_L 31U
+#define XHC_BIUSPC_ALL_R 0U
+#define XHC_BIUSPC__ALL_L 31U
+#define XHC_BIUSPC__ALL_R 0U
+#define XHC_BIUSPC_DATAMASK 0xffffffffU
+#define XHC_BIUSPC_RDWRMASK 0x00000000U
+#define XHC_BIUSPC_RESETVALUE 0x0000000cU
+
+#define XHC_AXIWRA_OFFSET 0xc08U
+#define XHC_AXIWRA_BASE 0xc08U
+#define XHC_AXIWRA__WTS_L 31U
+#define XHC_AXIWRA__WTS_R 28U
+#define XHC_AXIWRA__WTS_WIDTH 4U
+#define XHC_AXIWRA__WTS_RESETVALUE 0x2U
+#define XHC_AXIWRA__WUA_L 24U
+#define XHC_AXIWRA__WUA_R 16U
+#define XHC_AXIWRA__WUA_WIDTH 9U
+#define XHC_AXIWRA__WUA_RESETVALUE 0x0U
+#define XHC_AXIWRA__reserved_L 15U
+#define XHC_AXIWRA__reserved_R 10U
+#define XHC_AXIWRA__reserved_WIDTH 6U
+#define XHC_AXIWRA__reserved_RESETVALUE 0x0U
+#define XHC_AXIWRA__BYP 9U
+#define XHC_AXIWRA__BYP_L 9U
+#define XHC_AXIWRA__BYP_R 9U
+#define XHC_AXIWRA__BYP_WIDTH 1U
+#define XHC_AXIWRA__BYP_RESETVALUE 0x0U
+#define XHC_AXIWRA__WSA_L 8U
+#define XHC_AXIWRA__WSA_R 0U
+#define XHC_AXIWRA__WSA_WIDTH 9U
+#define XHC_AXIWRA__WSA_RESETVALUE 0x0U
+#define XHC_AXIWRA__RESERVED_L 27U
+#define XHC_AXIWRA__RESERVED_R 25U
+#define XHC_AXIWRA_WIDTH 32U
+#define XHC_AXIWRA__WIDTH 32U
+#define XHC_AXIWRA_ALL_L 31U
+#define XHC_AXIWRA_ALL_R 0U
+#define XHC_AXIWRA__ALL_L 31U
+#define XHC_AXIWRA__ALL_R 0U
+#define XHC_AXIWRA_DATAMASK 0xf1ffffffU
+#define XHC_AXIWRA_RDWRMASK 0x0e000000U
+#define XHC_AXIWRA_RESETVALUE 0x20000000U
+
+#define XHC_AXIRDA_OFFSET 0xc0cU
+#define XHC_AXIRDA_BASE 0xc0cU
+#define XHC_AXIRDA__RTS_L 31U
+#define XHC_AXIRDA__RTS_R 28U
+#define XHC_AXIRDA__RTS_WIDTH 4U
+#define XHC_AXIRDA__RTS_RESETVALUE 0x2U
+#define XHC_AXIRDA__RFPC 27U
+#define XHC_AXIRDA__RFPC_L 27U
+#define XHC_AXIRDA__RFPC_R 27U
+#define XHC_AXIRDA__RFPC_WIDTH 1U
+#define XHC_AXIRDA__RFPC_RESETVALUE 0x0U
+#define XHC_AXIRDA__RUA_L 24U
+#define XHC_AXIRDA__RUA_R 16U
+#define XHC_AXIRDA__RUA_WIDTH 9U
+#define XHC_AXIRDA__RUA_RESETVALUE 0x0U
+#define XHC_AXIRDA__reserved_L 15U
+#define XHC_AXIRDA__reserved_R 9U
+#define XHC_AXIRDA__reserved_WIDTH 7U
+#define XHC_AXIRDA__reserved_RESETVALUE 0x0U
+#define XHC_AXIRDA__RSA_L 8U
+#define XHC_AXIRDA__RSA_R 0U
+#define XHC_AXIRDA__RSA_WIDTH 9U
+#define XHC_AXIRDA__RSA_RESETVALUE 0x0U
+#define XHC_AXIRDA__RESERVED_L 26U
+#define XHC_AXIRDA__RESERVED_R 25U
+#define XHC_AXIRDA_WIDTH 32U
+#define XHC_AXIRDA__WIDTH 32U
+#define XHC_AXIRDA_ALL_L 31U
+#define XHC_AXIRDA_ALL_R 0U
+#define XHC_AXIRDA__ALL_L 31U
+#define XHC_AXIRDA__ALL_R 0U
+#define XHC_AXIRDA_DATAMASK 0xf9ffffffU
+#define XHC_AXIRDA_RDWRMASK 0x06000000U
+#define XHC_AXIRDA_RESETVALUE 0x20000000U
+
+#define XHC_AXILPM_OFFSET 0xc10U
+#define XHC_AXILPM_BASE 0xc10U
+#define XHC_AXILPM__ENB 31U
+#define XHC_AXILPM__ENB_L 31U
+#define XHC_AXILPM__ENB_R 31U
+#define XHC_AXILPM__ENB_WIDTH 1U
+#define XHC_AXILPM__ENB_RESETVALUE 0x0U
+#define XHC_AXILPM__reserved_L 30U
+#define XHC_AXILPM__reserved_R 3U
+#define XHC_AXILPM__reserved_WIDTH 28U
+#define XHC_AXILPM__reserved_RESETVALUE 0x0000000U
+#define XHC_AXILPM__ITT_L 2U
+#define XHC_AXILPM__ITT_R 0U
+#define XHC_AXILPM__ITT_WIDTH 3U
+#define XHC_AXILPM__ITT_RESETVALUE 0x0U
+#define XHC_AXILPM_WIDTH 32U
+#define XHC_AXILPM__WIDTH 32U
+#define XHC_AXILPM_ALL_L 31U
+#define XHC_AXILPM_ALL_R 0U
+#define XHC_AXILPM__ALL_L 31U
+#define XHC_AXILPM__ALL_R 0U
+#define XHC_AXILPM_DATAMASK 0xffffffffU
+#define XHC_AXILPM_RDWRMASK 0x00000000U
+#define XHC_AXILPM_RESETVALUE 0x00000000U
+
+#define XHC_AXIQOS_OFFSET 0xc14U
+#define XHC_AXIQOS_BASE 0xc14U
+#define XHC_AXIQOS__WQOS3_L 31U
+#define XHC_AXIQOS__WQOS3_R 28U
+#define XHC_AXIQOS__WQOS3_WIDTH 4U
+#define XHC_AXIQOS__WQOS3_RESETVALUE 0x0U
+#define XHC_AXIQOS__WQOS2_L 27U
+#define XHC_AXIQOS__WQOS2_R 24U
+#define XHC_AXIQOS__WQOS2_WIDTH 4U
+#define XHC_AXIQOS__WQOS2_RESETVALUE 0x0U
+#define XHC_AXIQOS__WQOS1_L 23U
+#define XHC_AXIQOS__WQOS1_R 20U
+#define XHC_AXIQOS__WQOS1_WIDTH 4U
+#define XHC_AXIQOS__WQOS1_RESETVALUE 0x0U
+#define XHC_AXIQOS__WQOS0_L 19U
+#define XHC_AXIQOS__WQOS0_R 16U
+#define XHC_AXIQOS__WQOS0_WIDTH 4U
+#define XHC_AXIQOS__WQOS0_RESETVALUE 0x0U
+#define XHC_AXIQOS__RQOS3_L 15U
+#define XHC_AXIQOS__RQOS3_R 12U
+#define XHC_AXIQOS__RQOS3_WIDTH 4U
+#define XHC_AXIQOS__RQOS3_RESETVALUE 0x0U
+#define XHC_AXIQOS__RQOS2_L 11U
+#define XHC_AXIQOS__RQOS2_R 8U
+#define XHC_AXIQOS__RQOS2_WIDTH 4U
+#define XHC_AXIQOS__RQOS2_RESETVALUE 0x0U
+#define XHC_AXIQOS__RQOS1_L 7U
+#define XHC_AXIQOS__RQOS1_R 4U
+#define XHC_AXIQOS__RQOS1_WIDTH 4U
+#define XHC_AXIQOS__RQOS1_RESETVALUE 0x0U
+#define XHC_AXIQOS__RQOS0_L 3U
+#define XHC_AXIQOS__RQOS0_R 0U
+#define XHC_AXIQOS__RQOS0_WIDTH 4U
+#define XHC_AXIQOS__RQOS0_RESETVALUE 0x0U
+#define XHC_AXIQOS_WIDTH 32U
+#define XHC_AXIQOS__WIDTH 32U
+#define XHC_AXIQOS_ALL_L 31U
+#define XHC_AXIQOS_ALL_R 0U
+#define XHC_AXIQOS__ALL_L 31U
+#define XHC_AXIQOS__ALL_R 0U
+#define XHC_AXIQOS_DATAMASK 0xffffffffU
+#define XHC_AXIQOS_RDWRMASK 0x00000000U
+#define XHC_AXIQOS_RESETVALUE 0x00000000U
+
+#define XHC_ECHCSR_OFFSET 0xc20U
+#define XHC_ECHCSR_BASE 0xc20U
+#define XHC_ECHCSR__CLK_L 31U
+#define XHC_ECHCSR__CLK_R 21U
+#define XHC_ECHCSR__CLK_WIDTH 11U
+#define XHC_ECHCSR__CLK_RESETVALUE 0x0U
+#define XHC_ECHCSR__reserved_L 20U
+#define XHC_ECHCSR__reserved_R 19U
+#define XHC_ECHCSR__reserved_WIDTH 2U
+#define XHC_ECHCSR__reserved_RESETVALUE 0x0U
+#define XHC_ECHCSR__WID_L 18U
+#define XHC_ECHCSR__WID_R 16U
+#define XHC_ECHCSR__WID_WIDTH 3U
+#define XHC_ECHCSR__WID_RESETVALUE 0x0U
+#define XHC_ECHCSR__NCP_L 15U
+#define XHC_ECHCSR__NCP_R 8U
+#define XHC_ECHCSR__NCP_WIDTH 8U
+#define XHC_ECHCSR__NCP_RESETVALUE 0x04U
+#define XHC_ECHCSR__CID_L 7U
+#define XHC_ECHCSR__CID_R 0U
+#define XHC_ECHCSR__CID_WIDTH 8U
+#define XHC_ECHCSR__CID_RESETVALUE 0xc1U
+#define XHC_ECHCSR_WIDTH 32U
+#define XHC_ECHCSR__WIDTH 32U
+#define XHC_ECHCSR_ALL_L 31U
+#define XHC_ECHCSR_ALL_R 0U
+#define XHC_ECHCSR__ALL_L 31U
+#define XHC_ECHCSR__ALL_R 0U
+#define XHC_ECHCSR_DATAMASK 0xffffffffU
+#define XHC_ECHCSR_RDWRMASK 0x00000000U
+#define XHC_ECHCSR_RESETVALUE 0x000004c1U
+
+#define XHC_CSRSPC_OFFSET 0xc24U
+#define XHC_CSRSPC_BASE 0xc24U
+#define XHC_CSRSPC__MAJ_L 31U
+#define XHC_CSRSPC__MAJ_R 28U
+#define XHC_CSRSPC__MAJ_WIDTH 4U
+#define XHC_CSRSPC__MAJ_RESETVALUE 0x0U
+#define XHC_CSRSPC__MIN_L 27U
+#define XHC_CSRSPC__MIN_R 24U
+#define XHC_CSRSPC__MIN_WIDTH 4U
+#define XHC_CSRSPC__MIN_RESETVALUE 0x0U
+#define XHC_CSRSPC__RLS_L 23U
+#define XHC_CSRSPC__RLS_R 20U
+#define XHC_CSRSPC__RLS_WIDTH 4U
+#define XHC_CSRSPC__RLS_RESETVALUE 0x0U
+#define XHC_CSRSPC__reserved_L 19U
+#define XHC_CSRSPC__reserved_R 3U
+#define XHC_CSRSPC__reserved_WIDTH 17U
+#define XHC_CSRSPC__reserved_RESETVALUE 0x0U
+#define XHC_CSRSPC__ASP 2U
+#define XHC_CSRSPC__ASP_L 2U
+#define XHC_CSRSPC__ASP_R 2U
+#define XHC_CSRSPC__ASP_WIDTH 1U
+#define XHC_CSRSPC__ASP_RESETVALUE 0x0U
+#define XHC_CSRSPC__TYP_L 1U
+#define XHC_CSRSPC__TYP_R 0U
+#define XHC_CSRSPC__TYP_WIDTH 2U
+#define XHC_CSRSPC__TYP_RESETVALUE 0x0U
+#define XHC_CSRSPC_WIDTH 32U
+#define XHC_CSRSPC__WIDTH 32U
+#define XHC_CSRSPC_ALL_L 31U
+#define XHC_CSRSPC_ALL_R 0U
+#define XHC_CSRSPC__ALL_L 31U
+#define XHC_CSRSPC__ALL_R 0U
+#define XHC_CSRSPC_DATAMASK 0xffffffffU
+#define XHC_CSRSPC_RDWRMASK 0x00000000U
+#define XHC_CSRSPC_RESETVALUE 0x00000000U
+
+#define XHC_ECHAIU_OFFSET 0xc30U
+#define XHC_ECHAIU_BASE 0xc30U
+#define XHC_ECHAIU__DMA_L 31U
+#define XHC_ECHAIU__DMA_R 30U
+#define XHC_ECHAIU__DMA_WIDTH 2U
+#define XHC_ECHAIU__DMA_RESETVALUE 0x1U
+#define XHC_ECHAIU__PBRS_L 29U
+#define XHC_ECHAIU__PBRS_R 28U
+#define XHC_ECHAIU__PBRS_WIDTH 2U
+#define XHC_ECHAIU__PBRS_RESETVALUE 0x0U
+#define XHC_ECHAIU__PBR2_L 27U
+#define XHC_ECHAIU__PBR2_R 26U
+#define XHC_ECHAIU__PBR2_WIDTH 2U
+#define XHC_ECHAIU__PBR2_RESETVALUE 0x0U
+#define XHC_ECHAIU__SCHS_L 25U
+#define XHC_ECHAIU__SCHS_R 24U
+#define XHC_ECHAIU__SCHS_WIDTH 2U
+#define XHC_ECHAIU__SCHS_RESETVALUE 0x0U
+#define XHC_ECHAIU__SCH2_L 23U
+#define XHC_ECHAIU__SCH2_R 22U
+#define XHC_ECHAIU__SCH2_WIDTH 2U
+#define XHC_ECHAIU__SCH2_RESETVALUE 0x0U
+#define XHC_ECHAIU__CHMS_L 21U
+#define XHC_ECHAIU__CHMS_R 20U
+#define XHC_ECHAIU__CHMS_WIDTH 2U
+#define XHC_ECHAIU__CHMS_RESETVALUE 0x3U
+#define XHC_ECHAIU__CHM2_L 19U
+#define XHC_ECHAIU__CHM2_R 18U
+#define XHC_ECHAIU__CHM2_WIDTH 2U
+#define XHC_ECHAIU__CHM2_RESETVALUE 0x0U
+#define XHC_ECHAIU__reserved_L 17U
+#define XHC_ECHAIU__reserved_R 16U
+#define XHC_ECHAIU__reserved_WIDTH 2U
+#define XHC_ECHAIU__reserved_RESETVALUE 0x0U
+#define XHC_ECHAIU__NCP_L 15U
+#define XHC_ECHAIU__NCP_R 8U
+#define XHC_ECHAIU__NCP_WIDTH 8U
+#define XHC_ECHAIU__NCP_RESETVALUE 0x04U
+#define XHC_ECHAIU__CID_L 7U
+#define XHC_ECHAIU__CID_R 0U
+#define XHC_ECHAIU__CID_WIDTH 8U
+#define XHC_ECHAIU__CID_RESETVALUE 0xc2U
+#define XHC_ECHAIU_WIDTH 32U
+#define XHC_ECHAIU__WIDTH 32U
+#define XHC_ECHAIU_ALL_L 31U
+#define XHC_ECHAIU_ALL_R 0U
+#define XHC_ECHAIU__ALL_L 31U
+#define XHC_ECHAIU__ALL_R 0U
+#define XHC_ECHAIU_DATAMASK 0xffffffffU
+#define XHC_ECHAIU_RDWRMASK 0x00000000U
+#define XHC_ECHAIU_RESETVALUE 0x403004c2U
+
+#define XHC_AIUDMA_OFFSET 0xc34U
+#define XHC_AIUDMA_BASE 0xc34U
+#define XHC_AIUDMA__WRMB_L 31U
+#define XHC_AIUDMA__WRMB_R 28U
+#define XHC_AIUDMA__WRMB_WIDTH 4U
+#define XHC_AIUDMA__WRMB_RESETVALUE 0x0U
+#define XHC_AIUDMA__WRD_L 27U
+#define XHC_AIUDMA__WRD_R 26U
+#define XHC_AIUDMA__WRD_WIDTH 2U
+#define XHC_AIUDMA__WRD_RESETVALUE 0x0U
+#define XHC_AIUDMA__WED_L 25U
+#define XHC_AIUDMA__WED_R 24U
+#define XHC_AIUDMA__WED_WIDTH 2U
+#define XHC_AIUDMA__WED_RESETVALUE 0x0U
+#define XHC_AIUDMA__WMS_L 23U
+#define XHC_AIUDMA__WMS_R 22U
+#define XHC_AIUDMA__WMS_WIDTH 2U
+#define XHC_AIUDMA__WMS_RESETVALUE 0x0U
+#define XHC_AIUDMA__WMI_L 21U
+#define XHC_AIUDMA__WMI_R 20U
+#define XHC_AIUDMA__WMI_WIDTH 2U
+#define XHC_AIUDMA__WMI_RESETVALUE 0x0U
+#define XHC_AIUDMA__WPF_L 19U
+#define XHC_AIUDMA__WPF_R 16U
+#define XHC_AIUDMA__WPF_WIDTH 4U
+#define XHC_AIUDMA__WPF_RESETVALUE 0x6U
+#define XHC_AIUDMA__RRMB_L 15U
+#define XHC_AIUDMA__RRMB_R 12U
+#define XHC_AIUDMA__RRMB_WIDTH 4U
+#define XHC_AIUDMA__RRMB_RESETVALUE 0x0U
+#define XHC_AIUDMA__RTD_L 11U
+#define XHC_AIUDMA__RTD_R 10U
+#define XHC_AIUDMA__RTD_WIDTH 2U
+#define XHC_AIUDMA__RTD_RESETVALUE 0x0U
+#define XHC_AIUDMA__RTF_L 9U
+#define XHC_AIUDMA__RTF_R 8U
+#define XHC_AIUDMA__RTF_WIDTH 2U
+#define XHC_AIUDMA__RTF_RESETVALUE 0x0U
+#define XHC_AIUDMA__RM_S_L 7U
+#define XHC_AIUDMA__RM_S_R 6U
+#define XHC_AIUDMA__RM_S_WIDTH 2U
+#define XHC_AIUDMA__RM_S_RESETVALUE 0x0U
+#define XHC_AIUDMA__TFBS_L 5U
+#define XHC_AIUDMA__TFBS_R 3U
+#define XHC_AIUDMA__TFBS_WIDTH 3U
+#define XHC_AIUDMA__TFBS_RESETVALUE 0x0U
+#define XHC_AIUDMA__reserved_L 2U
+#define XHC_AIUDMA__reserved_R 0U
+#define XHC_AIUDMA__reserved_WIDTH 3U
+#define XHC_AIUDMA__reserved_RESETVALUE 0x0U
+#define XHC_AIUDMA_WIDTH 32U
+#define XHC_AIUDMA__WIDTH 32U
+#define XHC_AIUDMA_ALL_L 31U
+#define XHC_AIUDMA_ALL_R 0U
+#define XHC_AIUDMA__ALL_L 31U
+#define XHC_AIUDMA__ALL_R 0U
+#define XHC_AIUDMA_DATAMASK 0xffffffffU
+#define XHC_AIUDMA_RDWRMASK 0x00000000U
+#define XHC_AIUDMA_RESETVALUE 0x00060000U
+
+#define XHC_AIUFLA_OFFSET 0xc38U
+#define XHC_AIUFLA_BASE 0xc38U
+#define XHC_AIUFLA__ACLK_L 31U
+#define XHC_AIUFLA__ACLK_R 23U
+#define XHC_AIUFLA__ACLK_WIDTH 9U
+#define XHC_AIUFLA__ACLK_RESETVALUE 0x0U
+#define XHC_AIUFLA__MFLV_L 22U
+#define XHC_AIUFLA__MFLV_R 7U
+#define XHC_AIUFLA__MFLV_WIDTH 16U
+#define XHC_AIUFLA__MFLV_RESETVALUE 0x0000U
+#define XHC_AIUFLA__NFC 6U
+#define XHC_AIUFLA__NFC_L 6U
+#define XHC_AIUFLA__NFC_R 6U
+#define XHC_AIUFLA__NFC_WIDTH 1U
+#define XHC_AIUFLA__NFC_RESETVALUE 0x1U
+#define XHC_AIUFLA__FLADJ_L 5U
+#define XHC_AIUFLA__FLADJ_R 0U
+#define XHC_AIUFLA__FLADJ_WIDTH 6U
+#define XHC_AIUFLA__FLADJ_RESETVALUE 0x20U
+#define XHC_AIUFLA_WIDTH 32U
+#define XHC_AIUFLA__WIDTH 32U
+#define XHC_AIUFLA_ALL_L 31U
+#define XHC_AIUFLA_ALL_R 0U
+#define XHC_AIUFLA__ALL_L 31U
+#define XHC_AIUFLA__ALL_R 0U
+#define XHC_AIUFLA_DATAMASK 0xffffffffU
+#define XHC_AIUFLA_RDWRMASK 0x00000000U
+#define XHC_AIUFLA_RESETVALUE 0x00000060U
+
+#define XHC_AIUCFG_OFFSET 0xc3cU
+#define XHC_AIUCFG_BASE 0xc3cU
+#define XHC_AIUCFG__ISO_L 30U
+#define XHC_AIUCFG__ISO_R 28U
+#define XHC_AIUCFG__ISO_WIDTH 3U
+#define XHC_AIUCFG__ISO_RESETVALUE 0x0U
+#define XHC_AIUCFG__EPC_L 26U
+#define XHC_AIUCFG__EPC_R 24U
+#define XHC_AIUCFG__EPC_WIDTH 3U
+#define XHC_AIUCFG__EPC_RESETVALUE 0x5U
+#define XHC_AIUCFG__PTQ_L 22U
+#define XHC_AIUCFG__PTQ_R 20U
+#define XHC_AIUCFG__PTQ_WIDTH 3U
+#define XHC_AIUCFG__PTQ_RESETVALUE 0x3U
+#define XHC_AIUCFG__NTQ_L 18U
+#define XHC_AIUCFG__NTQ_R 16U
+#define XHC_AIUCFG__NTQ_WIDTH 3U
+#define XHC_AIUCFG__NTQ_RESETVALUE 0x3U
+#define XHC_AIUCFG__HID 15U
+#define XHC_AIUCFG__HID_L 15U
+#define XHC_AIUCFG__HID_R 15U
+#define XHC_AIUCFG__HID_WIDTH 1U
+#define XHC_AIUCFG__HID_RESETVALUE 0x0U
+#define XHC_AIUCFG__EPS_L 14U
+#define XHC_AIUCFG__EPS_R 12U
+#define XHC_AIUCFG__EPS_WIDTH 3U
+#define XHC_AIUCFG__EPS_RESETVALUE 0x0U
+#define XHC_AIUCFG__reserved_L 11U
+#define XHC_AIUCFG__reserved_R 9U
+#define XHC_AIUCFG__reserved_WIDTH 3U
+#define XHC_AIUCFG__reserved_RESETVALUE 0x0U
+#define XHC_AIUCFG__PEP2_L 8U
+#define XHC_AIUCFG__PEP2_R 6U
+#define XHC_AIUCFG__PEP2_WIDTH 3U
+#define XHC_AIUCFG__PEP2_RESETVALUE 0x4U
+#define XHC_AIUCFG__MELADJ_L 5U
+#define XHC_AIUCFG__MELADJ_R 0U
+#define XHC_AIUCFG__MELADJ_WIDTH 6U
+#define XHC_AIUCFG__MELADJ_RESETVALUE 0x0U
+#define XHC_AIUCFG__RESERVED_0 31U
+#define XHC_AIUCFG__RESERVED_0_L 31U
+#define XHC_AIUCFG__RESERVED_0_R 31U
+#define XHC_AIUCFG__RESERVED_1 27U
+#define XHC_AIUCFG__RESERVED_1_L 27U
+#define XHC_AIUCFG__RESERVED_1_R 27U
+#define XHC_AIUCFG__RESERVED_2 23U
+#define XHC_AIUCFG__RESERVED_2_L 23U
+#define XHC_AIUCFG__RESERVED_2_R 23U
+#define XHC_AIUCFG__RESERVED_3 19U
+#define XHC_AIUCFG__RESERVED_3_L 19U
+#define XHC_AIUCFG__RESERVED_3_R 19U
+#define XHC_AIUCFG_WIDTH 31U
+#define XHC_AIUCFG__WIDTH 31U
+#define XHC_AIUCFG_ALL_L 30U
+#define XHC_AIUCFG_ALL_R 0U
+#define XHC_AIUCFG__ALL_L 30U
+#define XHC_AIUCFG__ALL_R 0U
+#define XHC_AIUCFG_DATAMASK 0x7777ffffU
+#define XHC_AIUCFG_RDWRMASK 0x88880000U
+#define XHC_AIUCFG_RESETVALUE 0x05330100U
+
+#define XHC_ECHFSC_OFFSET 0xc40U
+#define XHC_ECHFSC_BASE 0xc40U
+#define XHC_ECHFSC__reserved_L 31U
+#define XHC_ECHFSC__reserved_R 24U
+#define XHC_ECHFSC__reserved_WIDTH 8U
+#define XHC_ECHFSC__reserved_RESETVALUE 0x00U
+#define XHC_ECHFSC__WRMB_L 23U
+#define XHC_ECHFSC__WRMB_R 20U
+#define XHC_ECHFSC__WRMB_WIDTH 4U
+#define XHC_ECHFSC__WRMB_RESETVALUE 0x0U
+#define XHC_ECHFSC__RRMB_L 19U
+#define XHC_ECHFSC__RRMB_R 16U
+#define XHC_ECHFSC__RRMB_WIDTH 4U
+#define XHC_ECHFSC__RRMB_RESETVALUE 0x0U
+#define XHC_ECHFSC__NCP_L 15U
+#define XHC_ECHFSC__NCP_R 8U
+#define XHC_ECHFSC__NCP_WIDTH 8U
+#define XHC_ECHFSC__NCP_RESETVALUE 0x50U
+#define XHC_ECHFSC__CID_L 7U
+#define XHC_ECHFSC__CID_R 0U
+#define XHC_ECHFSC__CID_WIDTH 8U
+#define XHC_ECHFSC__CID_RESETVALUE 0xc3U
+#define XHC_ECHFSC_WIDTH 32U
+#define XHC_ECHFSC__WIDTH 32U
+#define XHC_ECHFSC_ALL_L 31U
+#define XHC_ECHFSC_ALL_R 0U
+#define XHC_ECHFSC__ALL_L 31U
+#define XHC_ECHFSC__ALL_R 0U
+#define XHC_ECHFSC_DATAMASK 0xffffffffU
+#define XHC_ECHFSC_RDWRMASK 0x00000000U
+#define XHC_ECHFSC_RESETVALUE 0x000050c3U
+
+#define XHC_FSCPOC_OFFSET 0xc54U
+#define XHC_FSCPOC_BASE 0xc54U
+#define XHC_FSCPOC__NCS_L 31U
+#define XHC_FSCPOC__NCS_R 28U
+#define XHC_FSCPOC__NCS_WIDTH 4U
+#define XHC_FSCPOC__NCS_RESETVALUE 0x0U
+#define XHC_FSCPOC__FSIZ_L 22U
+#define XHC_FSCPOC__FSIZ_R 18U
+#define XHC_FSCPOC__FSIZ_WIDTH 5U
+#define XHC_FSCPOC__FSIZ_RESETVALUE 0x0U
+#define XHC_FSCPOC__PSIZ_L 16U
+#define XHC_FSCPOC__PSIZ_R 12U
+#define XHC_FSCPOC__PSIZ_WIDTH 5U
+#define XHC_FSCPOC__PSIZ_RESETVALUE 0x0U
+#define XHC_FSCPOC__reserved_L 11U
+#define XHC_FSCPOC__reserved_R 5U
+#define XHC_FSCPOC__reserved_WIDTH 7U
+#define XHC_FSCPOC__reserved_RESETVALUE 0x0U
+#define XHC_FSCPOC__TSIZ_L 4U
+#define XHC_FSCPOC__TSIZ_R 0U
+#define XHC_FSCPOC__TSIZ_WIDTH 5U
+#define XHC_FSCPOC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSCPOC__RESERVED_L 27U
+#define XHC_FSCPOC__RESERVED_R 23U
+#define XHC_FSCPOC_WIDTH 32U
+#define XHC_FSCPOC__WIDTH 32U
+#define XHC_FSCPOC_ALL_L 31U
+#define XHC_FSCPOC_ALL_R 0U
+#define XHC_FSCPOC__ALL_L 31U
+#define XHC_FSCPOC__ALL_R 0U
+#define XHC_FSCPOC_DATAMASK 0xf07dffffU
+#define XHC_FSCPOC_RDWRMASK 0x0f820000U
+#define XHC_FSCPOC_RESETVALUE 0x00000000U
+
+#define XHC_FSCGOC_OFFSET 0xc58U
+#define XHC_FSCGOC_BASE 0xc58U
+#define XHC_FSCGOC__NCS_L 31U
+#define XHC_FSCGOC__NCS_R 28U
+#define XHC_FSCGOC__NCS_WIDTH 4U
+#define XHC_FSCGOC__NCS_RESETVALUE 0x0U
+#define XHC_FSCGOC__FSIZ_L 22U
+#define XHC_FSCGOC__FSIZ_R 18U
+#define XHC_FSCGOC__FSIZ_WIDTH 5U
+#define XHC_FSCGOC__FSIZ_RESETVALUE 0x0U
+#define XHC_FSCGOC__PSIZ_L 16U
+#define XHC_FSCGOC__PSIZ_R 12U
+#define XHC_FSCGOC__PSIZ_WIDTH 5U
+#define XHC_FSCGOC__PSIZ_RESETVALUE 0x0U
+#define XHC_FSCGOC__reserved_L 11U
+#define XHC_FSCGOC__reserved_R 5U
+#define XHC_FSCGOC__reserved_WIDTH 7U
+#define XHC_FSCGOC__reserved_RESETVALUE 0x0U
+#define XHC_FSCGOC__TSIZ_L 4U
+#define XHC_FSCGOC__TSIZ_R 0U
+#define XHC_FSCGOC__TSIZ_WIDTH 5U
+#define XHC_FSCGOC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSCGOC__RESERVED_L 27U
+#define XHC_FSCGOC__RESERVED_R 23U
+#define XHC_FSCGOC_WIDTH 32U
+#define XHC_FSCGOC__WIDTH 32U
+#define XHC_FSCGOC_ALL_L 31U
+#define XHC_FSCGOC_ALL_R 0U
+#define XHC_FSCGOC__ALL_L 31U
+#define XHC_FSCGOC__ALL_R 0U
+#define XHC_FSCGOC_DATAMASK 0xf07dffffU
+#define XHC_FSCGOC_RDWRMASK 0x0f820000U
+#define XHC_FSCGOC_RESETVALUE 0x00000000U
+
+#define XHC_FSCNOC_OFFSET 0xc5cU
+#define XHC_FSCNOC_BASE 0xc5cU
+#define XHC_FSCNOC__NCS_L 31U
+#define XHC_FSCNOC__NCS_R 28U
+#define XHC_FSCNOC__NCS_WIDTH 4U
+#define XHC_FSCNOC__NCS_RESETVALUE 0x0U
+#define XHC_FSCNOC__FSIZ_L 22U
+#define XHC_FSCNOC__FSIZ_R 18U
+#define XHC_FSCNOC__FSIZ_WIDTH 5U
+#define XHC_FSCNOC__FSIZ_RESETVALUE 0x0U
+#define XHC_FSCNOC__PSIZ_L 16U
+#define XHC_FSCNOC__PSIZ_R 12U
+#define XHC_FSCNOC__PSIZ_WIDTH 5U
+#define XHC_FSCNOC__PSIZ_RESETVALUE 0x0U
+#define XHC_FSCNOC__reserved_L 11U
+#define XHC_FSCNOC__reserved_R 5U
+#define XHC_FSCNOC__reserved_WIDTH 7U
+#define XHC_FSCNOC__reserved_RESETVALUE 0x0U
+#define XHC_FSCNOC__TSIZ_L 4U
+#define XHC_FSCNOC__TSIZ_R 0U
+#define XHC_FSCNOC__TSIZ_WIDTH 5U
+#define XHC_FSCNOC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSCNOC__RESERVED_L 27U
+#define XHC_FSCNOC__RESERVED_R 23U
+#define XHC_FSCNOC_WIDTH 32U
+#define XHC_FSCNOC__WIDTH 32U
+#define XHC_FSCNOC_ALL_L 31U
+#define XHC_FSCNOC_ALL_R 0U
+#define XHC_FSCNOC__ALL_L 31U
+#define XHC_FSCNOC__ALL_R 0U
+#define XHC_FSCNOC_DATAMASK 0xf07dffffU
+#define XHC_FSCNOC_RDWRMASK 0x0f820000U
+#define XHC_FSCNOC_RESETVALUE 0x00000000U
+
+#define XHC_FSCAIC_OFFSET 0xc60U
+#define XHC_FSCAIC_BASE 0xc60U
+#define XHC_FSCAIC__FSIZ_L 22U
+#define XHC_FSCAIC__FSIZ_R 18U
+#define XHC_FSCAIC__FSIZ_WIDTH 5U
+#define XHC_FSCAIC__FSIZ_RESETVALUE 0x0U
+#define XHC_FSCAIC__PSIZ_L 16U
+#define XHC_FSCAIC__PSIZ_R 12U
+#define XHC_FSCAIC__PSIZ_WIDTH 5U
+#define XHC_FSCAIC__PSIZ_RESETVALUE 0x0U
+#define XHC_FSCAIC__reserved_L 11U
+#define XHC_FSCAIC__reserved_R 0U
+#define XHC_FSCAIC__reserved_WIDTH 12U
+#define XHC_FSCAIC__reserved_RESETVALUE 0x000U
+#define XHC_FSCAIC__RESERVED_L 31U
+#define XHC_FSCAIC__RESERVED_R 23U
+#define XHC_FSCAIC_WIDTH 23U
+#define XHC_FSCAIC__WIDTH 23U
+#define XHC_FSCAIC_ALL_L 22U
+#define XHC_FSCAIC_ALL_R 0U
+#define XHC_FSCAIC__ALL_L 22U
+#define XHC_FSCAIC__ALL_R 0U
+#define XHC_FSCAIC_DATAMASK 0x007dffffU
+#define XHC_FSCAIC_RDWRMASK 0xff820000U
+#define XHC_FSCAIC_RESETVALUE 0x000000U
+
+#define XHC_FSCPIC_OFFSET 0xc64U
+#define XHC_FSCPIC_BASE 0xc64U
+#define XHC_FSCPIC__NCS_L 31U
+#define XHC_FSCPIC__NCS_R 28U
+#define XHC_FSCPIC__NCS_WIDTH 4U
+#define XHC_FSCPIC__NCS_RESETVALUE 0x0U
+#define XHC_FSCPIC__reserved_L 27U
+#define XHC_FSCPIC__reserved_R 5U
+#define XHC_FSCPIC__reserved_WIDTH 23U
+#define XHC_FSCPIC__reserved_RESETVALUE 0x0U
+#define XHC_FSCPIC__TSIZ_L 4U
+#define XHC_FSCPIC__TSIZ_R 0U
+#define XHC_FSCPIC__TSIZ_WIDTH 5U
+#define XHC_FSCPIC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSCPIC_WIDTH 32U
+#define XHC_FSCPIC__WIDTH 32U
+#define XHC_FSCPIC_ALL_L 31U
+#define XHC_FSCPIC_ALL_R 0U
+#define XHC_FSCPIC__ALL_L 31U
+#define XHC_FSCPIC__ALL_R 0U
+#define XHC_FSCPIC_DATAMASK 0xffffffffU
+#define XHC_FSCPIC_RDWRMASK 0x00000000U
+#define XHC_FSCPIC_RESETVALUE 0x00000000U
+
+#define XHC_FSCGIC_OFFSET 0xc68U
+#define XHC_FSCGIC_BASE 0xc68U
+#define XHC_FSCGIC__NCS_L 31U
+#define XHC_FSCGIC__NCS_R 28U
+#define XHC_FSCGIC__NCS_WIDTH 4U
+#define XHC_FSCGIC__NCS_RESETVALUE 0x0U
+#define XHC_FSCGIC__reserved_L 27U
+#define XHC_FSCGIC__reserved_R 5U
+#define XHC_FSCGIC__reserved_WIDTH 23U
+#define XHC_FSCGIC__reserved_RESETVALUE 0x0U
+#define XHC_FSCGIC__TSIZ_L 4U
+#define XHC_FSCGIC__TSIZ_R 0U
+#define XHC_FSCGIC__TSIZ_WIDTH 5U
+#define XHC_FSCGIC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSCGIC_WIDTH 32U
+#define XHC_FSCGIC__WIDTH 32U
+#define XHC_FSCGIC_ALL_L 31U
+#define XHC_FSCGIC_ALL_R 0U
+#define XHC_FSCGIC__ALL_L 31U
+#define XHC_FSCGIC__ALL_R 0U
+#define XHC_FSCGIC_DATAMASK 0xffffffffU
+#define XHC_FSCGIC_RDWRMASK 0x00000000U
+#define XHC_FSCGIC_RESETVALUE 0x00000000U
+
+#define XHC_FSCNIC_OFFSET 0xc6cU
+#define XHC_FSCNIC_BASE 0xc6cU
+#define XHC_FSCNIC__NCS_L 31U
+#define XHC_FSCNIC__NCS_R 28U
+#define XHC_FSCNIC__NCS_WIDTH 4U
+#define XHC_FSCNIC__NCS_RESETVALUE 0x0U
+#define XHC_FSCNIC__reserved_L 27U
+#define XHC_FSCNIC__reserved_R 5U
+#define XHC_FSCNIC__reserved_WIDTH 23U
+#define XHC_FSCNIC__reserved_RESETVALUE 0x0U
+#define XHC_FSCNIC__TSIZ_L 4U
+#define XHC_FSCNIC__TSIZ_R 0U
+#define XHC_FSCNIC__TSIZ_WIDTH 5U
+#define XHC_FSCNIC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSCNIC_WIDTH 32U
+#define XHC_FSCNIC__WIDTH 32U
+#define XHC_FSCNIC_ALL_L 31U
+#define XHC_FSCNIC_ALL_R 0U
+#define XHC_FSCNIC__ALL_L 31U
+#define XHC_FSCNIC__ALL_R 0U
+#define XHC_FSCNIC_DATAMASK 0xffffffffU
+#define XHC_FSCNIC_RDWRMASK 0x00000000U
+#define XHC_FSCNIC_RESETVALUE 0x00000000U
+
+#define XHC_ECHPRT_OFFSET 0xc70U
+#define XHC_ECHPRT_BASE 0xc70U
+#define XHC_ECHPRT__TDP 31U
+#define XHC_ECHPRT__TDP_L 31U
+#define XHC_ECHPRT__TDP_R 31U
+#define XHC_ECHPRT__TDP_WIDTH 1U
+#define XHC_ECHPRT__TDP_RESETVALUE 0x0U
+#define XHC_ECHPRT__RDP 30U
+#define XHC_ECHPRT__RDP_L 30U
+#define XHC_ECHPRT__RDP_R 30U
+#define XHC_ECHPRT__RDP_WIDTH 1U
+#define XHC_ECHPRT__RDP_RESETVALUE 0x0U
+#define XHC_ECHPRT__reserved_L 29U
+#define XHC_ECHPRT__reserved_R 25U
+#define XHC_ECHPRT__reserved_WIDTH 5U
+#define XHC_ECHPRT__reserved_RESETVALUE 0x0U
+#define XHC_ECHPRT__MFT_L 24U
+#define XHC_ECHPRT__MFT_R 17U
+#define XHC_ECHPRT__MFT_WIDTH 8U
+#define XHC_ECHPRT__MFT_RESETVALUE 0x7dU
+#define XHC_ECHPRT__HST 16U
+#define XHC_ECHPRT__HST_L 16U
+#define XHC_ECHPRT__HST_R 16U
+#define XHC_ECHPRT__HST_WIDTH 1U
+#define XHC_ECHPRT__HST_RESETVALUE 0x0U
+#define XHC_ECHPRT__NCP_L 15U
+#define XHC_ECHPRT__NCP_R 8U
+#define XHC_ECHPRT__NCP_WIDTH 8U
+#define XHC_ECHPRT__NCP_RESETVALUE 0x04U
+#define XHC_ECHPRT__CID_L 7U
+#define XHC_ECHPRT__CID_R 0U
+#define XHC_ECHPRT__CID_WIDTH 8U
+#define XHC_ECHPRT__CID_RESETVALUE 0xc4U
+#define XHC_ECHPRT_WIDTH 32U
+#define XHC_ECHPRT__WIDTH 32U
+#define XHC_ECHPRT_ALL_L 31U
+#define XHC_ECHPRT_ALL_R 0U
+#define XHC_ECHPRT__ALL_L 31U
+#define XHC_ECHPRT__ALL_R 0U
+#define XHC_ECHPRT_DATAMASK 0xffffffffU
+#define XHC_ECHPRT_RDWRMASK 0x00000000U
+#define XHC_ECHPRT_RESETVALUE 0x00fa04c4U
+
+#define XHC_PRTHSC_OFFSET 0xc78U
+#define XHC_PRTHSC_BASE 0xc78U
+#define XHC_PRTHSC__TMR_L 31U
+#define XHC_PRTHSC__TMR_R 16U
+#define XHC_PRTHSC__TMR_WIDTH 16U
+#define XHC_PRTHSC__TMR_RESETVALUE 0x0000U
+#define XHC_PRTHSC__RSL_L 7U
+#define XHC_PRTHSC__RSL_R 6U
+#define XHC_PRTHSC__RSL_WIDTH 2U
+#define XHC_PRTHSC__RSL_RESETVALUE 0x0U
+#define XHC_PRTHSC__AS_M_L 5U
+#define XHC_PRTHSC__AS_M_R 4U
+#define XHC_PRTHSC__AS_M_WIDTH 2U
+#define XHC_PRTHSC__AS_M_RESETVALUE 0x0U
+#define XHC_PRTHSC__CMD_L 3U
+#define XHC_PRTHSC__CMD_R 2U
+#define XHC_PRTHSC__CMD_WIDTH 2U
+#define XHC_PRTHSC__CMD_RESETVALUE 0x0U
+#define XHC_PRTHSC__reserved 1U
+#define XHC_PRTHSC__reserved_L 1U
+#define XHC_PRTHSC__reserved_R 1U
+#define XHC_PRTHSC__reserved_WIDTH 1U
+#define XHC_PRTHSC__reserved_RESETVALUE 0x0U
+#define XHC_PRTHSC__STB 0U
+#define XHC_PRTHSC__STB_L 0U
+#define XHC_PRTHSC__STB_R 0U
+#define XHC_PRTHSC__STB_WIDTH 1U
+#define XHC_PRTHSC__STB_RESETVALUE 0x0U
+#define XHC_PRTHSC__RESERVED_L 15U
+#define XHC_PRTHSC__RESERVED_R 8U
+#define XHC_PRTHSC_WIDTH 32U
+#define XHC_PRTHSC__WIDTH 32U
+#define XHC_PRTHSC_ALL_L 31U
+#define XHC_PRTHSC_ALL_R 0U
+#define XHC_PRTHSC__ALL_L 31U
+#define XHC_PRTHSC__ALL_R 0U
+#define XHC_PRTHSC_DATAMASK 0xffff00ffU
+#define XHC_PRTHSC_RDWRMASK 0x0000ff00U
+#define XHC_PRTHSC_RESETVALUE 0x00000000U
+
+#define XHC_PRTHSR_OFFSET 0xc7cU
+#define XHC_PRTHSR_BASE 0xc7cU
+#define XHC_PRTHSR__RDLY_L 31U
+#define XHC_PRTHSR__RDLY_R 24U
+#define XHC_PRTHSR__RDLY_WIDTH 8U
+#define XHC_PRTHSR__RDLY_RESETVALUE 0x00U
+#define XHC_PRTHSR__TDPP_L 23U
+#define XHC_PRTHSR__TDPP_R 16U
+#define XHC_PRTHSR__TDPP_WIDTH 8U
+#define XHC_PRTHSR__TDPP_RESETVALUE 0x00U
+#define XHC_PRTHSR__RDPP_L 15U
+#define XHC_PRTHSR__RDPP_R 8U
+#define XHC_PRTHSR__RDPP_WIDTH 8U
+#define XHC_PRTHSR__RDPP_RESETVALUE 0x00U
+#define XHC_PRTHSR__TRTY_L 7U
+#define XHC_PRTHSR__TRTY_R 0U
+#define XHC_PRTHSR__TRTY_WIDTH 8U
+#define XHC_PRTHSR__TRTY_RESETVALUE 0x00U
+#define XHC_PRTHSR_WIDTH 32U
+#define XHC_PRTHSR__WIDTH 32U
+#define XHC_PRTHSR_ALL_L 31U
+#define XHC_PRTHSR_ALL_R 0U
+#define XHC_PRTHSR__ALL_L 31U
+#define XHC_PRTHSR__ALL_R 0U
+#define XHC_PRTHSR_DATAMASK 0xffffffffU
+#define XHC_PRTHSR_RDWRMASK 0x00000000U
+#define XHC_PRTHSR_RESETVALUE 0x00000000U
+
+#define XHC_ECHRHS_OFFSET 0xc80U
+#define XHC_ECHRHS_BASE 0xc80U
+#define XHC_ECHRHS__RPO_L 30U
+#define XHC_ECHRHS__RPO_R 24U
+#define XHC_ECHRHS__RPO_WIDTH 7U
+#define XHC_ECHRHS__RPO_RESETVALUE 0x0U
+#define XHC_ECHRHS__reserved_L 23U
+#define XHC_ECHRHS__reserved_R 22U
+#define XHC_ECHRHS__reserved_WIDTH 2U
+#define XHC_ECHRHS__reserved_RESETVALUE 0x0U
+#define XHC_ECHRHS__RPN_L 21U
+#define XHC_ECHRHS__RPN_R 20U
+#define XHC_ECHRHS__RPN_WIDTH 2U
+#define XHC_ECHRHS__RPN_RESETVALUE 0x0U
+#define XHC_ECHRHS__DNR_L 19U
+#define XHC_ECHRHS__DNR_R 16U
+#define XHC_ECHRHS__DNR_WIDTH 4U
+#define XHC_ECHRHS__DNR_RESETVALUE 0x0U
+#define XHC_ECHRHS__NCP_L 15U
+#define XHC_ECHRHS__NCP_R 8U
+#define XHC_ECHRHS__NCP_WIDTH 8U
+#define XHC_ECHRHS__NCP_RESETVALUE 0x0cU
+#define XHC_ECHRHS__CID_L 7U
+#define XHC_ECHRHS__CID_R 0U
+#define XHC_ECHRHS__CID_WIDTH 8U
+#define XHC_ECHRHS__CID_RESETVALUE 0xc8U
+#define XHC_ECHRHS__RESERVED 31U
+#define XHC_ECHRHS__RESERVED_L 31U
+#define XHC_ECHRHS__RESERVED_R 31U
+#define XHC_ECHRHS_WIDTH 31U
+#define XHC_ECHRHS__WIDTH 31U
+#define XHC_ECHRHS_ALL_L 30U
+#define XHC_ECHRHS_ALL_R 0U
+#define XHC_ECHRHS__ALL_L 30U
+#define XHC_ECHRHS__ALL_R 0U
+#define XHC_ECHRHS_DATAMASK 0x7fffffffU
+#define XHC_ECHRHS_RDWRMASK 0x80000000U
+#define XHC_ECHRHS_RESETVALUE 0x00000cc8U
+
+#define XHC_RHSDES_OFFSET 0xc84U
+#define XHC_RHSDES_BASE 0xc84U
+#define XHC_RHSDES__PIS3_L 31U
+#define XHC_RHSDES__PIS3_R 30U
+#define XHC_RHSDES__PIS3_WIDTH 2U
+#define XHC_RHSDES__PIS3_RESETVALUE 0x0U
+#define XHC_RHSDES__HIST3 24U
+#define XHC_RHSDES__HIST3_L 24U
+#define XHC_RHSDES__HIST3_R 24U
+#define XHC_RHSDES__HIST3_WIDTH 1U
+#define XHC_RHSDES__HIST3_RESETVALUE 0x0U
+#define XHC_RHSDES__PIS2_L 23U
+#define XHC_RHSDES__PIS2_R 22U
+#define XHC_RHSDES__PIS2_WIDTH 2U
+#define XHC_RHSDES__PIS2_RESETVALUE 0x0U
+#define XHC_RHSDES__HIST2 16U
+#define XHC_RHSDES__HIST2_L 16U
+#define XHC_RHSDES__HIST2_R 16U
+#define XHC_RHSDES__HIST2_WIDTH 1U
+#define XHC_RHSDES__HIST2_RESETVALUE 0x0U
+#define XHC_RHSDES__PIS1_L 15U
+#define XHC_RHSDES__PIS1_R 14U
+#define XHC_RHSDES__PIS1_WIDTH 2U
+#define XHC_RHSDES__PIS1_RESETVALUE 0x0U
+#define XHC_RHSDES__HIST1 8U
+#define XHC_RHSDES__HIST1_L 8U
+#define XHC_RHSDES__HIST1_R 8U
+#define XHC_RHSDES__HIST1_WIDTH 1U
+#define XHC_RHSDES__HIST1_RESETVALUE 0x0U
+#define XHC_RHSDES__PIS0_L 7U
+#define XHC_RHSDES__PIS0_R 6U
+#define XHC_RHSDES__PIS0_WIDTH 2U
+#define XHC_RHSDES__PIS0_RESETVALUE 0x0U
+#define XHC_RHSDES__reserved_L 5U
+#define XHC_RHSDES__reserved_R 1U
+#define XHC_RHSDES__reserved_WIDTH 5U
+#define XHC_RHSDES__reserved_RESETVALUE 0x0U
+#define XHC_RHSDES__HIST0 0U
+#define XHC_RHSDES__HIST0_L 0U
+#define XHC_RHSDES__HIST0_R 0U
+#define XHC_RHSDES__HIST0_WIDTH 1U
+#define XHC_RHSDES__HIST0_RESETVALUE 0x0U
+#define XHC_RHSDES__RESERVED_0_L 29U
+#define XHC_RHSDES__RESERVED_0_R 25U
+#define XHC_RHSDES__RESERVED_1_L 21U
+#define XHC_RHSDES__RESERVED_1_R 17U
+#define XHC_RHSDES__RESERVED_2_L 13U
+#define XHC_RHSDES__RESERVED_2_R 9U
+#define XHC_RHSDES__RESERVED_L 29U
+#define XHC_RHSDES__RESERVED_R 25U
+#define XHC_RHSDES_WIDTH 32U
+#define XHC_RHSDES__WIDTH 32U
+#define XHC_RHSDES_ALL_L 31U
+#define XHC_RHSDES_ALL_R 0U
+#define XHC_RHSDES__ALL_L 31U
+#define XHC_RHSDES__ALL_R 0U
+#define XHC_RHSDES_DATAMASK 0xc1c1c1ffU
+#define XHC_RHSDES_RDWRMASK 0x3e3e3e00U
+#define XHC_RHSDES_RESETVALUE 0x00000000U
+
+#define XHC_RHSHSC0_OFFSET 0xc90U
+#define XHC_RHSHSC0_BASE 0xc90U
+#define XHC_RHSHSC0__TMR_L 31U
+#define XHC_RHSHSC0__TMR_R 16U
+#define XHC_RHSHSC0__TMR_WIDTH 16U
+#define XHC_RHSHSC0__TMR_RESETVALUE 0x0000U
+#define XHC_RHSHSC0__RSL_L 7U
+#define XHC_RHSHSC0__RSL_R 6U
+#define XHC_RHSHSC0__RSL_WIDTH 2U
+#define XHC_RHSHSC0__RSL_RESETVALUE 0x0U
+#define XHC_RHSHSC0__AS_M_L 5U
+#define XHC_RHSHSC0__AS_M_R 4U
+#define XHC_RHSHSC0__AS_M_WIDTH 2U
+#define XHC_RHSHSC0__AS_M_RESETVALUE 0x0U
+#define XHC_RHSHSC0__CMD_L 3U
+#define XHC_RHSHSC0__CMD_R 2U
+#define XHC_RHSHSC0__CMD_WIDTH 2U
+#define XHC_RHSHSC0__CMD_RESETVALUE 0x0U
+#define XHC_RHSHSC0__reserved 1U
+#define XHC_RHSHSC0__reserved_L 1U
+#define XHC_RHSHSC0__reserved_R 1U
+#define XHC_RHSHSC0__reserved_WIDTH 1U
+#define XHC_RHSHSC0__reserved_RESETVALUE 0x0U
+#define XHC_RHSHSC0__STB 0U
+#define XHC_RHSHSC0__STB_L 0U
+#define XHC_RHSHSC0__STB_R 0U
+#define XHC_RHSHSC0__STB_WIDTH 1U
+#define XHC_RHSHSC0__STB_RESETVALUE 0x0U
+#define XHC_RHSHSC0__RESERVED_L 15U
+#define XHC_RHSHSC0__RESERVED_R 8U
+#define XHC_RHSHSC0_WIDTH 32U
+#define XHC_RHSHSC0__WIDTH 32U
+#define XHC_RHSHSC0_ALL_L 31U
+#define XHC_RHSHSC0_ALL_R 0U
+#define XHC_RHSHSC0__ALL_L 31U
+#define XHC_RHSHSC0__ALL_R 0U
+#define XHC_RHSHSC0_DATAMASK 0xffff00ffU
+#define XHC_RHSHSC0_RDWRMASK 0x0000ff00U
+#define XHC_RHSHSC0_RESETVALUE 0x00000000U
+
+#define XHC_RHSHSR0_OFFSET 0xc94U
+#define XHC_RHSHSR0_BASE 0xc94U
+#define XHC_RHSHSR0__C2U_L 31U
+#define XHC_RHSHSR0__C2U_R 24U
+#define XHC_RHSHSR0__C2U_WIDTH 8U
+#define XHC_RHSHSR0__C2U_RESETVALUE 0x00U
+#define XHC_RHSHSR0__C1U_L 23U
+#define XHC_RHSHSR0__C1U_R 16U
+#define XHC_RHSHSR0__C1U_WIDTH 8U
+#define XHC_RHSHSR0__C1U_RESETVALUE 0x00U
+#define XHC_RHSHSR0__RCV_L 15U
+#define XHC_RHSHSR0__RCV_R 8U
+#define XHC_RHSHSR0__RCV_WIDTH 8U
+#define XHC_RHSHSR0__RCV_RESETVALUE 0x00U
+#define XHC_RHSHSR0__RTY_L 7U
+#define XHC_RHSHSR0__RTY_R 0U
+#define XHC_RHSHSR0__RTY_WIDTH 8U
+#define XHC_RHSHSR0__RTY_RESETVALUE 0x00U
+#define XHC_RHSHSR0_WIDTH 32U
+#define XHC_RHSHSR0__WIDTH 32U
+#define XHC_RHSHSR0_ALL_L 31U
+#define XHC_RHSHSR0_ALL_R 0U
+#define XHC_RHSHSR0__ALL_L 31U
+#define XHC_RHSHSR0__ALL_R 0U
+#define XHC_RHSHSR0_DATAMASK 0xffffffffU
+#define XHC_RHSHSR0_RDWRMASK 0x00000000U
+#define XHC_RHSHSR0_RESETVALUE 0x00000000U
+
+#define XHC_RHSHSC1_OFFSET 0xc98U
+#define XHC_RHSHSC1_BASE 0xc98U
+#define XHC_RHSHSC1__TMR_L 31U
+#define XHC_RHSHSC1__TMR_R 16U
+#define XHC_RHSHSC1__TMR_WIDTH 16U
+#define XHC_RHSHSC1__TMR_RESETVALUE 0x0000U
+#define XHC_RHSHSC1__RSL_L 7U
+#define XHC_RHSHSC1__RSL_R 6U
+#define XHC_RHSHSC1__RSL_WIDTH 2U
+#define XHC_RHSHSC1__RSL_RESETVALUE 0x0U
+#define XHC_RHSHSC1__AS_M_L 5U
+#define XHC_RHSHSC1__AS_M_R 4U
+#define XHC_RHSHSC1__AS_M_WIDTH 2U
+#define XHC_RHSHSC1__AS_M_RESETVALUE 0x0U
+#define XHC_RHSHSC1__CMD_L 3U
+#define XHC_RHSHSC1__CMD_R 2U
+#define XHC_RHSHSC1__CMD_WIDTH 2U
+#define XHC_RHSHSC1__CMD_RESETVALUE 0x0U
+#define XHC_RHSHSC1__reserved 1U
+#define XHC_RHSHSC1__reserved_L 1U
+#define XHC_RHSHSC1__reserved_R 1U
+#define XHC_RHSHSC1__reserved_WIDTH 1U
+#define XHC_RHSHSC1__reserved_RESETVALUE 0x0U
+#define XHC_RHSHSC1__STB 0U
+#define XHC_RHSHSC1__STB_L 0U
+#define XHC_RHSHSC1__STB_R 0U
+#define XHC_RHSHSC1__STB_WIDTH 1U
+#define XHC_RHSHSC1__STB_RESETVALUE 0x0U
+#define XHC_RHSHSC1__RESERVED_L 15U
+#define XHC_RHSHSC1__RESERVED_R 8U
+#define XHC_RHSHSC1_WIDTH 32U
+#define XHC_RHSHSC1__WIDTH 32U
+#define XHC_RHSHSC1_ALL_L 31U
+#define XHC_RHSHSC1_ALL_R 0U
+#define XHC_RHSHSC1__ALL_L 31U
+#define XHC_RHSHSC1__ALL_R 0U
+#define XHC_RHSHSC1_DATAMASK 0xffff00ffU
+#define XHC_RHSHSC1_RDWRMASK 0x0000ff00U
+#define XHC_RHSHSC1_RESETVALUE 0x00000000U
+
+#define XHC_RHSHSR1_OFFSET 0xc9cU
+#define XHC_RHSHSR1_BASE 0xc9cU
+#define XHC_RHSHSR1__C2U_L 31U
+#define XHC_RHSHSR1__C2U_R 24U
+#define XHC_RHSHSR1__C2U_WIDTH 8U
+#define XHC_RHSHSR1__C2U_RESETVALUE 0x00U
+#define XHC_RHSHSR1__C1U_L 23U
+#define XHC_RHSHSR1__C1U_R 16U
+#define XHC_RHSHSR1__C1U_WIDTH 8U
+#define XHC_RHSHSR1__C1U_RESETVALUE 0x00U
+#define XHC_RHSHSR1__RCV_L 15U
+#define XHC_RHSHSR1__RCV_R 8U
+#define XHC_RHSHSR1__RCV_WIDTH 8U
+#define XHC_RHSHSR1__RCV_RESETVALUE 0x00U
+#define XHC_RHSHSR1__RTY_L 7U
+#define XHC_RHSHSR1__RTY_R 0U
+#define XHC_RHSHSR1__RTY_WIDTH 8U
+#define XHC_RHSHSR1__RTY_RESETVALUE 0x00U
+#define XHC_RHSHSR1_WIDTH 32U
+#define XHC_RHSHSR1__WIDTH 32U
+#define XHC_RHSHSR1_ALL_L 31U
+#define XHC_RHSHSR1_ALL_R 0U
+#define XHC_RHSHSR1__ALL_L 31U
+#define XHC_RHSHSR1__ALL_R 0U
+#define XHC_RHSHSR1_DATAMASK 0xffffffffU
+#define XHC_RHSHSR1_RDWRMASK 0x00000000U
+#define XHC_RHSHSR1_RESETVALUE 0x00000000U
+
+#define XHC_RHSHSC2_OFFSET 0xca0U
+#define XHC_RHSHSC2_BASE 0xca0U
+#define XHC_RHSHSC2__TMR_L 31U
+#define XHC_RHSHSC2__TMR_R 16U
+#define XHC_RHSHSC2__TMR_WIDTH 16U
+#define XHC_RHSHSC2__TMR_RESETVALUE 0x0000U
+#define XHC_RHSHSC2__RSL_L 7U
+#define XHC_RHSHSC2__RSL_R 6U
+#define XHC_RHSHSC2__RSL_WIDTH 2U
+#define XHC_RHSHSC2__RSL_RESETVALUE 0x0U
+#define XHC_RHSHSC2__AS_M_L 5U
+#define XHC_RHSHSC2__AS_M_R 4U
+#define XHC_RHSHSC2__AS_M_WIDTH 2U
+#define XHC_RHSHSC2__AS_M_RESETVALUE 0x0U
+#define XHC_RHSHSC2__CMD_L 3U
+#define XHC_RHSHSC2__CMD_R 2U
+#define XHC_RHSHSC2__CMD_WIDTH 2U
+#define XHC_RHSHSC2__CMD_RESETVALUE 0x0U
+#define XHC_RHSHSC2__reserved 1U
+#define XHC_RHSHSC2__reserved_L 1U
+#define XHC_RHSHSC2__reserved_R 1U
+#define XHC_RHSHSC2__reserved_WIDTH 1U
+#define XHC_RHSHSC2__reserved_RESETVALUE 0x0U
+#define XHC_RHSHSC2__STB 0U
+#define XHC_RHSHSC2__STB_L 0U
+#define XHC_RHSHSC2__STB_R 0U
+#define XHC_RHSHSC2__STB_WIDTH 1U
+#define XHC_RHSHSC2__STB_RESETVALUE 0x0U
+#define XHC_RHSHSC2__RESERVED_L 15U
+#define XHC_RHSHSC2__RESERVED_R 8U
+#define XHC_RHSHSC2_WIDTH 32U
+#define XHC_RHSHSC2__WIDTH 32U
+#define XHC_RHSHSC2_ALL_L 31U
+#define XHC_RHSHSC2_ALL_R 0U
+#define XHC_RHSHSC2__ALL_L 31U
+#define XHC_RHSHSC2__ALL_R 0U
+#define XHC_RHSHSC2_DATAMASK 0xffff00ffU
+#define XHC_RHSHSC2_RDWRMASK 0x0000ff00U
+#define XHC_RHSHSC2_RESETVALUE 0x00000000U
+
+#define XHC_RHSHSR2_OFFSET 0xca4U
+#define XHC_RHSHSR2_BASE 0xca4U
+#define XHC_RHSHSR2__C2U_L 31U
+#define XHC_RHSHSR2__C2U_R 24U
+#define XHC_RHSHSR2__C2U_WIDTH 8U
+#define XHC_RHSHSR2__C2U_RESETVALUE 0x00U
+#define XHC_RHSHSR2__C1U_L 23U
+#define XHC_RHSHSR2__C1U_R 16U
+#define XHC_RHSHSR2__C1U_WIDTH 8U
+#define XHC_RHSHSR2__C1U_RESETVALUE 0x00U
+#define XHC_RHSHSR2__RCV_L 15U
+#define XHC_RHSHSR2__RCV_R 8U
+#define XHC_RHSHSR2__RCV_WIDTH 8U
+#define XHC_RHSHSR2__RCV_RESETVALUE 0x00U
+#define XHC_RHSHSR2__RTY_L 7U
+#define XHC_RHSHSR2__RTY_R 0U
+#define XHC_RHSHSR2__RTY_WIDTH 8U
+#define XHC_RHSHSR2__RTY_RESETVALUE 0x00U
+#define XHC_RHSHSR2_WIDTH 32U
+#define XHC_RHSHSR2__WIDTH 32U
+#define XHC_RHSHSR2_ALL_L 31U
+#define XHC_RHSHSR2_ALL_R 0U
+#define XHC_RHSHSR2__ALL_L 31U
+#define XHC_RHSHSR2__ALL_R 0U
+#define XHC_RHSHSR2_DATAMASK 0xffffffffU
+#define XHC_RHSHSR2_RDWRMASK 0x00000000U
+#define XHC_RHSHSR2_RESETVALUE 0x00000000U
+
+#define XHC_RHSHSC3_OFFSET 0xca8U
+#define XHC_RHSHSC3_BASE 0xca8U
+#define XHC_RHSHSC3__TMR_L 31U
+#define XHC_RHSHSC3__TMR_R 16U
+#define XHC_RHSHSC3__TMR_WIDTH 16U
+#define XHC_RHSHSC3__TMR_RESETVALUE 0x0000U
+#define XHC_RHSHSC3__RSL_L 7U
+#define XHC_RHSHSC3__RSL_R 6U
+#define XHC_RHSHSC3__RSL_WIDTH 2U
+#define XHC_RHSHSC3__RSL_RESETVALUE 0x0U
+#define XHC_RHSHSC3__AS_M_L 5U
+#define XHC_RHSHSC3__AS_M_R 4U
+#define XHC_RHSHSC3__AS_M_WIDTH 2U
+#define XHC_RHSHSC3__AS_M_RESETVALUE 0x0U
+#define XHC_RHSHSC3__CMD_L 3U
+#define XHC_RHSHSC3__CMD_R 2U
+#define XHC_RHSHSC3__CMD_WIDTH 2U
+#define XHC_RHSHSC3__CMD_RESETVALUE 0x0U
+#define XHC_RHSHSC3__reserved 1U
+#define XHC_RHSHSC3__reserved_L 1U
+#define XHC_RHSHSC3__reserved_R 1U
+#define XHC_RHSHSC3__reserved_WIDTH 1U
+#define XHC_RHSHSC3__reserved_RESETVALUE 0x0U
+#define XHC_RHSHSC3__STB 0U
+#define XHC_RHSHSC3__STB_L 0U
+#define XHC_RHSHSC3__STB_R 0U
+#define XHC_RHSHSC3__STB_WIDTH 1U
+#define XHC_RHSHSC3__STB_RESETVALUE 0x0U
+#define XHC_RHSHSC3__RESERVED_L 15U
+#define XHC_RHSHSC3__RESERVED_R 8U
+#define XHC_RHSHSC3_WIDTH 32U
+#define XHC_RHSHSC3__WIDTH 32U
+#define XHC_RHSHSC3_ALL_L 31U
+#define XHC_RHSHSC3_ALL_R 0U
+#define XHC_RHSHSC3__ALL_L 31U
+#define XHC_RHSHSC3__ALL_R 0U
+#define XHC_RHSHSC3_DATAMASK 0xffff00ffU
+#define XHC_RHSHSC3_RDWRMASK 0x0000ff00U
+#define XHC_RHSHSC3_RESETVALUE 0x00000000U
+
+#define XHC_RHSHSR3_OFFSET 0xcacU
+#define XHC_RHSHSR3_BASE 0xcacU
+#define XHC_RHSHSR3__C2U_L 31U
+#define XHC_RHSHSR3__C2U_R 24U
+#define XHC_RHSHSR3__C2U_WIDTH 8U
+#define XHC_RHSHSR3__C2U_RESETVALUE 0x00U
+#define XHC_RHSHSR3__C1U_L 23U
+#define XHC_RHSHSR3__C1U_R 16U
+#define XHC_RHSHSR3__C1U_WIDTH 8U
+#define XHC_RHSHSR3__C1U_RESETVALUE 0x00U
+#define XHC_RHSHSR3__RCV_L 15U
+#define XHC_RHSHSR3__RCV_R 8U
+#define XHC_RHSHSR3__RCV_WIDTH 8U
+#define XHC_RHSHSR3__RCV_RESETVALUE 0x00U
+#define XHC_RHSHSR3__RTY_L 7U
+#define XHC_RHSHSR3__RTY_R 0U
+#define XHC_RHSHSR3__RTY_WIDTH 8U
+#define XHC_RHSHSR3__RTY_RESETVALUE 0x00U
+#define XHC_RHSHSR3_WIDTH 32U
+#define XHC_RHSHSR3__WIDTH 32U
+#define XHC_RHSHSR3_ALL_L 31U
+#define XHC_RHSHSR3_ALL_R 0U
+#define XHC_RHSHSR3__ALL_L 31U
+#define XHC_RHSHSR3__ALL_R 0U
+#define XHC_RHSHSR3_DATAMASK 0xffffffffU
+#define XHC_RHSHSR3_RDWRMASK 0x00000000U
+#define XHC_RHSHSR3_RESETVALUE 0x00000000U
+
+#define XHC_ECHSSP_OFFSET 0xcb0U
+#define XHC_ECHSSP_BASE 0xcb0U
+#define XHC_ECHSSP__reserved_L 31U
+#define XHC_ECHSSP__reserved_R 16U
+#define XHC_ECHSSP__reserved_WIDTH 16U
+#define XHC_ECHSSP__reserved_RESETVALUE 0x0000U
+#define XHC_ECHSSP__NCP_L 15U
+#define XHC_ECHSSP__NCP_R 8U
+#define XHC_ECHSSP__NCP_WIDTH 8U
+#define XHC_ECHSSP__NCP_RESETVALUE 0x04U
+#define XHC_ECHSSP__CID_L 7U
+#define XHC_ECHSSP__CID_R 0U
+#define XHC_ECHSSP__CID_WIDTH 8U
+#define XHC_ECHSSP__CID_RESETVALUE 0xc6U
+#define XHC_ECHSSP_WIDTH 32U
+#define XHC_ECHSSP__WIDTH 32U
+#define XHC_ECHSSP_ALL_L 31U
+#define XHC_ECHSSP_ALL_R 0U
+#define XHC_ECHSSP__ALL_L 31U
+#define XHC_ECHSSP__ALL_R 0U
+#define XHC_ECHSSP_DATAMASK 0xffffffffU
+#define XHC_ECHSSP_RDWRMASK 0x00000000U
+#define XHC_ECHSSP_RESETVALUE 0x000004c6U
+
+#define XHC_SSPVER_OFFSET 0xcb4U
+#define XHC_SSPVER_BASE 0xcb4U
+#define XHC_SSPVER__MAJ_L 31U
+#define XHC_SSPVER__MAJ_R 28U
+#define XHC_SSPVER__MAJ_WIDTH 4U
+#define XHC_SSPVER__MAJ_RESETVALUE 0x0U
+#define XHC_SSPVER__MIN_L 27U
+#define XHC_SSPVER__MIN_R 24U
+#define XHC_SSPVER__MIN_WIDTH 4U
+#define XHC_SSPVER__MIN_RESETVALUE 0x0U
+#define XHC_SSPVER__RLS_L 23U
+#define XHC_SSPVER__RLS_R 20U
+#define XHC_SSPVER__RLS_WIDTH 4U
+#define XHC_SSPVER__RLS_RESETVALUE 0x0U
+#define XHC_SSPVER__reserved_L 19U
+#define XHC_SSPVER__reserved_R 0U
+#define XHC_SSPVER__reserved_WIDTH 20U
+#define XHC_SSPVER__reserved_RESETVALUE 0x00000U
+#define XHC_SSPVER_WIDTH 32U
+#define XHC_SSPVER__WIDTH 32U
+#define XHC_SSPVER_ALL_L 31U
+#define XHC_SSPVER_ALL_R 0U
+#define XHC_SSPVER__ALL_L 31U
+#define XHC_SSPVER__ALL_R 0U
+#define XHC_SSPVER_DATAMASK 0xffffffffU
+#define XHC_SSPVER_RDWRMASK 0x00000000U
+#define XHC_SSPVER_RESETVALUE 0x00000000U
+
+#define XHC_SSPMGN_OFFSET 0xcb8U
+#define XHC_SSPMGN_BASE 0xcb8U
+#define XHC_SSPMGN__MGN_L 31U
+#define XHC_SSPMGN__MGN_R 0U
+#define XHC_SSPMGN__MGN_WIDTH 32U
+#define XHC_SSPMGN__MGN_RESETVALUE 0x4b535040U
+#define XHC_SSPMGN_WIDTH 32U
+#define XHC_SSPMGN__WIDTH 32U
+#define XHC_SSPMGN_ALL_L 31U
+#define XHC_SSPMGN_ALL_R 0U
+#define XHC_SSPMGN__ALL_L 31U
+#define XHC_SSPMGN__ALL_R 0U
+#define XHC_SSPMGN_DATAMASK 0xffffffffU
+#define XHC_SSPMGN_RDWRMASK 0x00000000U
+#define XHC_SSPMGN_RESETVALUE 0x4b535040U
+
+#define XHC_ECHFSC2_OFFSET 0xcc0U
+#define XHC_ECHFSC2_BASE 0xcc0U
+#define XHC_ECHFSC2__reserved_L 31U
+#define XHC_ECHFSC2__reserved_R 16U
+#define XHC_ECHFSC2__reserved_WIDTH 16U
+#define XHC_ECHFSC2__reserved_RESETVALUE 0x0000U
+#define XHC_ECHFSC2__NCP_L 15U
+#define XHC_ECHFSC2__NCP_R 8U
+#define XHC_ECHFSC2__NCP_WIDTH 8U
+#define XHC_ECHFSC2__NCP_RESETVALUE 0x50U
+#define XHC_ECHFSC2__CID_L 7U
+#define XHC_ECHFSC2__CID_R 0U
+#define XHC_ECHFSC2__CID_WIDTH 8U
+#define XHC_ECHFSC2__CID_RESETVALUE 0xc7U
+#define XHC_ECHFSC2_WIDTH 32U
+#define XHC_ECHFSC2__WIDTH 32U
+#define XHC_ECHFSC2_ALL_L 31U
+#define XHC_ECHFSC2_ALL_R 0U
+#define XHC_ECHFSC2__ALL_L 31U
+#define XHC_ECHFSC2__ALL_R 0U
+#define XHC_ECHFSC2_DATAMASK 0xffffffffU
+#define XHC_ECHFSC2_RDWRMASK 0x00000000U
+#define XHC_ECHFSC2_RESETVALUE 0x000050c7U
+
+#define XHC_FSC2POC_OFFSET 0xcd4U
+#define XHC_FSC2POC_BASE 0xcd4U
+#define XHC_FSC2POC__NCS_L 31U
+#define XHC_FSC2POC__NCS_R 28U
+#define XHC_FSC2POC__NCS_WIDTH 4U
+#define XHC_FSC2POC__NCS_RESETVALUE 0x0U
+#define XHC_FSC2POC__FSIZ_L 22U
+#define XHC_FSC2POC__FSIZ_R 18U
+#define XHC_FSC2POC__FSIZ_WIDTH 5U
+#define XHC_FSC2POC__FSIZ_RESETVALUE 0x0U
+#define XHC_FSC2POC__PSIZ_L 16U
+#define XHC_FSC2POC__PSIZ_R 12U
+#define XHC_FSC2POC__PSIZ_WIDTH 5U
+#define XHC_FSC2POC__PSIZ_RESETVALUE 0x0U
+#define XHC_FSC2POC__reserved_L 11U
+#define XHC_FSC2POC__reserved_R 5U
+#define XHC_FSC2POC__reserved_WIDTH 7U
+#define XHC_FSC2POC__reserved_RESETVALUE 0x0U
+#define XHC_FSC2POC__TSIZ_L 4U
+#define XHC_FSC2POC__TSIZ_R 0U
+#define XHC_FSC2POC__TSIZ_WIDTH 5U
+#define XHC_FSC2POC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSC2POC__RESERVED_L 27U
+#define XHC_FSC2POC__RESERVED_R 23U
+#define XHC_FSC2POC_WIDTH 32U
+#define XHC_FSC2POC__WIDTH 32U
+#define XHC_FSC2POC_ALL_L 31U
+#define XHC_FSC2POC_ALL_R 0U
+#define XHC_FSC2POC__ALL_L 31U
+#define XHC_FSC2POC__ALL_R 0U
+#define XHC_FSC2POC_DATAMASK 0xf07dffffU
+#define XHC_FSC2POC_RDWRMASK 0x0f820000U
+#define XHC_FSC2POC_RESETVALUE 0x00000000U
+
+#define XHC_FSC2GOC_OFFSET 0xcd8U
+#define XHC_FSC2GOC_BASE 0xcd8U
+#define XHC_FSC2GOC__NCS_L 31U
+#define XHC_FSC2GOC__NCS_R 28U
+#define XHC_FSC2GOC__NCS_WIDTH 4U
+#define XHC_FSC2GOC__NCS_RESETVALUE 0x0U
+#define XHC_FSC2GOC__FSIZ_L 22U
+#define XHC_FSC2GOC__FSIZ_R 18U
+#define XHC_FSC2GOC__FSIZ_WIDTH 5U
+#define XHC_FSC2GOC__FSIZ_RESETVALUE 0x0U
+#define XHC_FSC2GOC__PSIZ_L 16U
+#define XHC_FSC2GOC__PSIZ_R 12U
+#define XHC_FSC2GOC__PSIZ_WIDTH 5U
+#define XHC_FSC2GOC__PSIZ_RESETVALUE 0x0U
+#define XHC_FSC2GOC__reserved_L 11U
+#define XHC_FSC2GOC__reserved_R 5U
+#define XHC_FSC2GOC__reserved_WIDTH 7U
+#define XHC_FSC2GOC__reserved_RESETVALUE 0x0U
+#define XHC_FSC2GOC__TSIZ_L 4U
+#define XHC_FSC2GOC__TSIZ_R 0U
+#define XHC_FSC2GOC__TSIZ_WIDTH 5U
+#define XHC_FSC2GOC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSC2GOC__RESERVED_L 27U
+#define XHC_FSC2GOC__RESERVED_R 23U
+#define XHC_FSC2GOC_WIDTH 32U
+#define XHC_FSC2GOC__WIDTH 32U
+#define XHC_FSC2GOC_ALL_L 31U
+#define XHC_FSC2GOC_ALL_R 0U
+#define XHC_FSC2GOC__ALL_L 31U
+#define XHC_FSC2GOC__ALL_R 0U
+#define XHC_FSC2GOC_DATAMASK 0xf07dffffU
+#define XHC_FSC2GOC_RDWRMASK 0x0f820000U
+#define XHC_FSC2GOC_RESETVALUE 0x00000000U
+
+#define XHC_FSC2NOC_OFFSET 0xcdcU
+#define XHC_FSC2NOC_BASE 0xcdcU
+#define XHC_FSC2NOC__NCS_L 31U
+#define XHC_FSC2NOC__NCS_R 28U
+#define XHC_FSC2NOC__NCS_WIDTH 4U
+#define XHC_FSC2NOC__NCS_RESETVALUE 0x0U
+#define XHC_FSC2NOC__FSIZ_L 22U
+#define XHC_FSC2NOC__FSIZ_R 18U
+#define XHC_FSC2NOC__FSIZ_WIDTH 5U
+#define XHC_FSC2NOC__FSIZ_RESETVALUE 0x0U
+#define XHC_FSC2NOC__PSIZ_L 16U
+#define XHC_FSC2NOC__PSIZ_R 12U
+#define XHC_FSC2NOC__PSIZ_WIDTH 5U
+#define XHC_FSC2NOC__PSIZ_RESETVALUE 0x0U
+#define XHC_FSC2NOC__reserved_L 11U
+#define XHC_FSC2NOC__reserved_R 5U
+#define XHC_FSC2NOC__reserved_WIDTH 7U
+#define XHC_FSC2NOC__reserved_RESETVALUE 0x0U
+#define XHC_FSC2NOC__TSIZ_L 4U
+#define XHC_FSC2NOC__TSIZ_R 0U
+#define XHC_FSC2NOC__TSIZ_WIDTH 5U
+#define XHC_FSC2NOC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSC2NOC__RESERVED_L 27U
+#define XHC_FSC2NOC__RESERVED_R 23U
+#define XHC_FSC2NOC_WIDTH 32U
+#define XHC_FSC2NOC__WIDTH 32U
+#define XHC_FSC2NOC_ALL_L 31U
+#define XHC_FSC2NOC_ALL_R 0U
+#define XHC_FSC2NOC__ALL_L 31U
+#define XHC_FSC2NOC__ALL_R 0U
+#define XHC_FSC2NOC_DATAMASK 0xf07dffffU
+#define XHC_FSC2NOC_RDWRMASK 0x0f820000U
+#define XHC_FSC2NOC_RESETVALUE 0x00000000U
+
+#define XHC_FSC2AIC_OFFSET 0xce0U
+#define XHC_FSC2AIC_BASE 0xce0U
+#define XHC_FSC2AIC__FSIZ_L 22U
+#define XHC_FSC2AIC__FSIZ_R 18U
+#define XHC_FSC2AIC__FSIZ_WIDTH 5U
+#define XHC_FSC2AIC__FSIZ_RESETVALUE 0x0U
+#define XHC_FSC2AIC__PSIZ_L 16U
+#define XHC_FSC2AIC__PSIZ_R 12U
+#define XHC_FSC2AIC__PSIZ_WIDTH 5U
+#define XHC_FSC2AIC__PSIZ_RESETVALUE 0x0U
+#define XHC_FSC2AIC__reserved_L 11U
+#define XHC_FSC2AIC__reserved_R 0U
+#define XHC_FSC2AIC__reserved_WIDTH 12U
+#define XHC_FSC2AIC__reserved_RESETVALUE 0x000U
+#define XHC_FSC2AIC__RESERVED_L 31U
+#define XHC_FSC2AIC__RESERVED_R 23U
+#define XHC_FSC2AIC_WIDTH 23U
+#define XHC_FSC2AIC__WIDTH 23U
+#define XHC_FSC2AIC_ALL_L 22U
+#define XHC_FSC2AIC_ALL_R 0U
+#define XHC_FSC2AIC__ALL_L 22U
+#define XHC_FSC2AIC__ALL_R 0U
+#define XHC_FSC2AIC_DATAMASK 0x007dffffU
+#define XHC_FSC2AIC_RDWRMASK 0xff820000U
+#define XHC_FSC2AIC_RESETVALUE 0x000000U
+
+#define XHC_FSC2PIC_OFFSET 0xce4U
+#define XHC_FSC2PIC_BASE 0xce4U
+#define XHC_FSC2PIC__NCS_L 31U
+#define XHC_FSC2PIC__NCS_R 28U
+#define XHC_FSC2PIC__NCS_WIDTH 4U
+#define XHC_FSC2PIC__NCS_RESETVALUE 0x0U
+#define XHC_FSC2PIC__reserved_L 27U
+#define XHC_FSC2PIC__reserved_R 5U
+#define XHC_FSC2PIC__reserved_WIDTH 23U
+#define XHC_FSC2PIC__reserved_RESETVALUE 0x0U
+#define XHC_FSC2PIC__TSIZ_L 4U
+#define XHC_FSC2PIC__TSIZ_R 0U
+#define XHC_FSC2PIC__TSIZ_WIDTH 5U
+#define XHC_FSC2PIC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSC2PIC_WIDTH 32U
+#define XHC_FSC2PIC__WIDTH 32U
+#define XHC_FSC2PIC_ALL_L 31U
+#define XHC_FSC2PIC_ALL_R 0U
+#define XHC_FSC2PIC__ALL_L 31U
+#define XHC_FSC2PIC__ALL_R 0U
+#define XHC_FSC2PIC_DATAMASK 0xffffffffU
+#define XHC_FSC2PIC_RDWRMASK 0x00000000U
+#define XHC_FSC2PIC_RESETVALUE 0x00000000U
+
+#define XHC_FSC2GIC_OFFSET 0xce8U
+#define XHC_FSC2GIC_BASE 0xce8U
+#define XHC_FSC2GIC__NCS_L 31U
+#define XHC_FSC2GIC__NCS_R 28U
+#define XHC_FSC2GIC__NCS_WIDTH 4U
+#define XHC_FSC2GIC__NCS_RESETVALUE 0x0U
+#define XHC_FSC2GIC__reserved_L 27U
+#define XHC_FSC2GIC__reserved_R 5U
+#define XHC_FSC2GIC__reserved_WIDTH 23U
+#define XHC_FSC2GIC__reserved_RESETVALUE 0x0U
+#define XHC_FSC2GIC__TSIZ_L 4U
+#define XHC_FSC2GIC__TSIZ_R 0U
+#define XHC_FSC2GIC__TSIZ_WIDTH 5U
+#define XHC_FSC2GIC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSC2GIC_WIDTH 32U
+#define XHC_FSC2GIC__WIDTH 32U
+#define XHC_FSC2GIC_ALL_L 31U
+#define XHC_FSC2GIC_ALL_R 0U
+#define XHC_FSC2GIC__ALL_L 31U
+#define XHC_FSC2GIC__ALL_R 0U
+#define XHC_FSC2GIC_DATAMASK 0xffffffffU
+#define XHC_FSC2GIC_RDWRMASK 0x00000000U
+#define XHC_FSC2GIC_RESETVALUE 0x00000000U
+
+#define XHC_FSC2NIC_OFFSET 0xcecU
+#define XHC_FSC2NIC_BASE 0xcecU
+#define XHC_FSC2NIC__NCS_L 31U
+#define XHC_FSC2NIC__NCS_R 28U
+#define XHC_FSC2NIC__NCS_WIDTH 4U
+#define XHC_FSC2NIC__NCS_RESETVALUE 0x0U
+#define XHC_FSC2NIC__reserved_L 27U
+#define XHC_FSC2NIC__reserved_R 5U
+#define XHC_FSC2NIC__reserved_WIDTH 23U
+#define XHC_FSC2NIC__reserved_RESETVALUE 0x0U
+#define XHC_FSC2NIC__TSIZ_L 4U
+#define XHC_FSC2NIC__TSIZ_R 0U
+#define XHC_FSC2NIC__TSIZ_WIDTH 5U
+#define XHC_FSC2NIC__TSIZ_RESETVALUE 0x0U
+#define XHC_FSC2NIC_WIDTH 32U
+#define XHC_FSC2NIC__WIDTH 32U
+#define XHC_FSC2NIC_ALL_L 31U
+#define XHC_FSC2NIC_ALL_R 0U
+#define XHC_FSC2NIC__ALL_L 31U
+#define XHC_FSC2NIC__ALL_R 0U
+#define XHC_FSC2NIC_DATAMASK 0xffffffffU
+#define XHC_FSC2NIC_RDWRMASK 0x00000000U
+#define XHC_FSC2NIC_RESETVALUE 0x00000000U
+
+#define XHC_ECHPRT2_OFFSET 0xcf0U
+#define XHC_ECHPRT2_BASE 0xcf0U
+#define XHC_ECHPRT2__HDP 31U
+#define XHC_ECHPRT2__HDP_L 31U
+#define XHC_ECHPRT2__HDP_R 31U
+#define XHC_ECHPRT2__HDP_WIDTH 1U
+#define XHC_ECHPRT2__HDP_RESETVALUE 0x0U
+#define XHC_ECHPRT2__FDP 30U
+#define XHC_ECHPRT2__FDP_L 30U
+#define XHC_ECHPRT2__FDP_R 30U
+#define XHC_ECHPRT2__FDP_WIDTH 1U
+#define XHC_ECHPRT2__FDP_RESETVALUE 0x0U
+#define XHC_ECHPRT2__reserved_L 29U
+#define XHC_ECHPRT2__reserved_R 17U
+#define XHC_ECHPRT2__reserved_WIDTH 13U
+#define XHC_ECHPRT2__reserved_RESETVALUE 0x0U
+#define XHC_ECHPRT2__HST 16U
+#define XHC_ECHPRT2__HST_L 16U
+#define XHC_ECHPRT2__HST_R 16U
+#define XHC_ECHPRT2__HST_WIDTH 1U
+#define XHC_ECHPRT2__HST_RESETVALUE 0x0U
+#define XHC_ECHPRT2__NCP_L 15U
+#define XHC_ECHPRT2__NCP_R 8U
+#define XHC_ECHPRT2__NCP_WIDTH 8U
+#define XHC_ECHPRT2__NCP_RESETVALUE 0x04U
+#define XHC_ECHPRT2__CID_L 7U
+#define XHC_ECHPRT2__CID_R 0U
+#define XHC_ECHPRT2__CID_WIDTH 8U
+#define XHC_ECHPRT2__CID_RESETVALUE 0xc8U
+#define XHC_ECHPRT2_WIDTH 32U
+#define XHC_ECHPRT2__WIDTH 32U
+#define XHC_ECHPRT2_ALL_L 31U
+#define XHC_ECHPRT2_ALL_R 0U
+#define XHC_ECHPRT2__ALL_L 31U
+#define XHC_ECHPRT2__ALL_R 0U
+#define XHC_ECHPRT2_DATAMASK 0xffffffffU
+#define XHC_ECHPRT2_RDWRMASK 0x00000000U
+#define XHC_ECHPRT2_RESETVALUE 0x000004c8U
+
+#define XHC_PRT2HSC_OFFSET 0xcf8U
+#define XHC_PRT2HSC_BASE 0xcf8U
+#define XHC_PRT2HSC__TMR_L 31U
+#define XHC_PRT2HSC__TMR_R 16U
+#define XHC_PRT2HSC__TMR_WIDTH 16U
+#define XHC_PRT2HSC__TMR_RESETVALUE 0x0000U
+#define XHC_PRT2HSC__RSL_L 7U
+#define XHC_PRT2HSC__RSL_R 6U
+#define XHC_PRT2HSC__RSL_WIDTH 2U
+#define XHC_PRT2HSC__RSL_RESETVALUE 0x0U
+#define XHC_PRT2HSC__AS_M_L 5U
+#define XHC_PRT2HSC__AS_M_R 4U
+#define XHC_PRT2HSC__AS_M_WIDTH 2U
+#define XHC_PRT2HSC__AS_M_RESETVALUE 0x0U
+#define XHC_PRT2HSC__CMD_L 3U
+#define XHC_PRT2HSC__CMD_R 2U
+#define XHC_PRT2HSC__CMD_WIDTH 2U
+#define XHC_PRT2HSC__CMD_RESETVALUE 0x0U
+#define XHC_PRT2HSC__reserved 1U
+#define XHC_PRT2HSC__reserved_L 1U
+#define XHC_PRT2HSC__reserved_R 1U
+#define XHC_PRT2HSC__reserved_WIDTH 1U
+#define XHC_PRT2HSC__reserved_RESETVALUE 0x0U
+#define XHC_PRT2HSC__STB 0U
+#define XHC_PRT2HSC__STB_L 0U
+#define XHC_PRT2HSC__STB_R 0U
+#define XHC_PRT2HSC__STB_WIDTH 1U
+#define XHC_PRT2HSC__STB_RESETVALUE 0x0U
+#define XHC_PRT2HSC__RESERVED_L 15U
+#define XHC_PRT2HSC__RESERVED_R 8U
+#define XHC_PRT2HSC_WIDTH 32U
+#define XHC_PRT2HSC__WIDTH 32U
+#define XHC_PRT2HSC_ALL_L 31U
+#define XHC_PRT2HSC_ALL_R 0U
+#define XHC_PRT2HSC__ALL_L 31U
+#define XHC_PRT2HSC__ALL_R 0U
+#define XHC_PRT2HSC_DATAMASK 0xffff00ffU
+#define XHC_PRT2HSC_RDWRMASK 0x0000ff00U
+#define XHC_PRT2HSC_RESETVALUE 0x00000000U
+
+#define XHC_PRT2HSR_OFFSET 0xcfcU
+#define XHC_PRT2HSR_BASE 0xcfcU
+#define XHC_PRT2HSR__RNAK_L 31U
+#define XHC_PRT2HSR__RNAK_R 24U
+#define XHC_PRT2HSR__RNAK_WIDTH 8U
+#define XHC_PRT2HSR__RNAK_RESETVALUE 0x00U
+#define XHC_PRT2HSR__HSTX_L 23U
+#define XHC_PRT2HSR__HSTX_R 16U
+#define XHC_PRT2HSR__HSTX_WIDTH 8U
+#define XHC_PRT2HSR__HSTX_RESETVALUE 0x00U
+#define XHC_PRT2HSR__HSRX_L 15U
+#define XHC_PRT2HSR__HSRX_R 8U
+#define XHC_PRT2HSR__HSRX_WIDTH 8U
+#define XHC_PRT2HSR__HSRX_RESETVALUE 0x00U
+#define XHC_PRT2HSR__SPLT_L 7U
+#define XHC_PRT2HSR__SPLT_R 0U
+#define XHC_PRT2HSR__SPLT_WIDTH 8U
+#define XHC_PRT2HSR__SPLT_RESETVALUE 0x00U
+#define XHC_PRT2HSR_WIDTH 32U
+#define XHC_PRT2HSR__WIDTH 32U
+#define XHC_PRT2HSR_ALL_L 31U
+#define XHC_PRT2HSR_ALL_R 0U
+#define XHC_PRT2HSR__ALL_L 31U
+#define XHC_PRT2HSR__ALL_R 0U
+#define XHC_PRT2HSR_DATAMASK 0xffffffffU
+#define XHC_PRT2HSR_RDWRMASK 0x00000000U
+#define XHC_PRT2HSR_RESETVALUE 0x00000000U
+
+#define XHC_ECHRH2_OFFSET 0xd00U
+#define XHC_ECHRH2_BASE 0xd00U
+#define XHC_ECHRH2__MTT 31U
+#define XHC_ECHRH2__MTT_L 31U
+#define XHC_ECHRH2__MTT_R 31U
+#define XHC_ECHRH2__MTT_WIDTH 1U
+#define XHC_ECHRH2__MTT_RESETVALUE 0x0U
+#define XHC_ECHRH2__RPO_L 30U
+#define XHC_ECHRH2__RPO_R 24U
+#define XHC_ECHRH2__RPO_WIDTH 7U
+#define XHC_ECHRH2__RPO_RESETVALUE 0x0U
+#define XHC_ECHRH2__reserved_L 23U
+#define XHC_ECHRH2__reserved_R 22U
+#define XHC_ECHRH2__reserved_WIDTH 2U
+#define XHC_ECHRH2__reserved_RESETVALUE 0x0U
+#define XHC_ECHRH2__RPN_L 21U
+#define XHC_ECHRH2__RPN_R 20U
+#define XHC_ECHRH2__RPN_WIDTH 2U
+#define XHC_ECHRH2__RPN_RESETVALUE 0x0U
+#define XHC_ECHRH2__DNR_L 19U
+#define XHC_ECHRH2__DNR_R 16U
+#define XHC_ECHRH2__DNR_WIDTH 4U
+#define XHC_ECHRH2__DNR_RESETVALUE 0x0U
+#define XHC_ECHRH2__NCP_L 15U
+#define XHC_ECHRH2__NCP_R 8U
+#define XHC_ECHRH2__NCP_WIDTH 8U
+#define XHC_ECHRH2__NCP_RESETVALUE 0x0cU
+#define XHC_ECHRH2__CID_L 7U
+#define XHC_ECHRH2__CID_R 0U
+#define XHC_ECHRH2__CID_WIDTH 8U
+#define XHC_ECHRH2__CID_RESETVALUE 0xc9U
+#define XHC_ECHRH2_WIDTH 32U
+#define XHC_ECHRH2__WIDTH 32U
+#define XHC_ECHRH2_ALL_L 31U
+#define XHC_ECHRH2_ALL_R 0U
+#define XHC_ECHRH2__ALL_L 31U
+#define XHC_ECHRH2__ALL_R 0U
+#define XHC_ECHRH2_DATAMASK 0xffffffffU
+#define XHC_ECHRH2_RDWRMASK 0x00000000U
+#define XHC_ECHRH2_RESETVALUE 0x00000cc9U
+
+#define XHC_RH2DES_OFFSET 0xd04U
+#define XHC_RH2DES_BASE 0xd04U
+#define XHC_RH2DES__PIS3_L 31U
+#define XHC_RH2DES__PIS3_R 30U
+#define XHC_RH2DES__PIS3_WIDTH 2U
+#define XHC_RH2DES__PIS3_RESETVALUE 0x0U
+#define XHC_RH2DES__HIST3 24U
+#define XHC_RH2DES__HIST3_L 24U
+#define XHC_RH2DES__HIST3_R 24U
+#define XHC_RH2DES__HIST3_WIDTH 1U
+#define XHC_RH2DES__HIST3_RESETVALUE 0x0U
+#define XHC_RH2DES__PIS2_L 23U
+#define XHC_RH2DES__PIS2_R 22U
+#define XHC_RH2DES__PIS2_WIDTH 2U
+#define XHC_RH2DES__PIS2_RESETVALUE 0x0U
+#define XHC_RH2DES__HIST2 16U
+#define XHC_RH2DES__HIST2_L 16U
+#define XHC_RH2DES__HIST2_R 16U
+#define XHC_RH2DES__HIST2_WIDTH 1U
+#define XHC_RH2DES__HIST2_RESETVALUE 0x0U
+#define XHC_RH2DES__PIS1_L 15U
+#define XHC_RH2DES__PIS1_R 14U
+#define XHC_RH2DES__PIS1_WIDTH 2U
+#define XHC_RH2DES__PIS1_RESETVALUE 0x0U
+#define XHC_RH2DES__HIST1 8U
+#define XHC_RH2DES__HIST1_L 8U
+#define XHC_RH2DES__HIST1_R 8U
+#define XHC_RH2DES__HIST1_WIDTH 1U
+#define XHC_RH2DES__HIST1_RESETVALUE 0x0U
+#define XHC_RH2DES__PIS0_L 7U
+#define XHC_RH2DES__PIS0_R 6U
+#define XHC_RH2DES__PIS0_WIDTH 2U
+#define XHC_RH2DES__PIS0_RESETVALUE 0x0U
+#define XHC_RH2DES__reserved_L 5U
+#define XHC_RH2DES__reserved_R 1U
+#define XHC_RH2DES__reserved_WIDTH 5U
+#define XHC_RH2DES__reserved_RESETVALUE 0x0U
+#define XHC_RH2DES__HIST0 0U
+#define XHC_RH2DES__HIST0_L 0U
+#define XHC_RH2DES__HIST0_R 0U
+#define XHC_RH2DES__HIST0_WIDTH 1U
+#define XHC_RH2DES__HIST0_RESETVALUE 0x0U
+#define XHC_RH2DES__RESERVED_0_L 29U
+#define XHC_RH2DES__RESERVED_0_R 25U
+#define XHC_RH2DES__RESERVED_1_L 21U
+#define XHC_RH2DES__RESERVED_1_R 17U
+#define XHC_RH2DES__RESERVED_2_L 13U
+#define XHC_RH2DES__RESERVED_2_R 9U
+#define XHC_RH2DES__RESERVED_L 29U
+#define XHC_RH2DES__RESERVED_R 25U
+#define XHC_RH2DES_WIDTH 32U
+#define XHC_RH2DES__WIDTH 32U
+#define XHC_RH2DES_ALL_L 31U
+#define XHC_RH2DES_ALL_R 0U
+#define XHC_RH2DES__ALL_L 31U
+#define XHC_RH2DES__ALL_R 0U
+#define XHC_RH2DES_DATAMASK 0xc1c1c1ffU
+#define XHC_RH2DES_RDWRMASK 0x3e3e3e00U
+#define XHC_RH2DES_RESETVALUE 0x00000000U
+
+#define XHC_RH2HSC0_OFFSET 0xd10U
+#define XHC_RH2HSC0_BASE 0xd10U
+#define XHC_RH2HSC0__TMR_L 31U
+#define XHC_RH2HSC0__TMR_R 16U
+#define XHC_RH2HSC0__TMR_WIDTH 16U
+#define XHC_RH2HSC0__TMR_RESETVALUE 0x0000U
+#define XHC_RH2HSC0__RSL_L 7U
+#define XHC_RH2HSC0__RSL_R 6U
+#define XHC_RH2HSC0__RSL_WIDTH 2U
+#define XHC_RH2HSC0__RSL_RESETVALUE 0x0U
+#define XHC_RH2HSC0__AS_M_L 5U
+#define XHC_RH2HSC0__AS_M_R 4U
+#define XHC_RH2HSC0__AS_M_WIDTH 2U
+#define XHC_RH2HSC0__AS_M_RESETVALUE 0x0U
+#define XHC_RH2HSC0__CMD_L 3U
+#define XHC_RH2HSC0__CMD_R 2U
+#define XHC_RH2HSC0__CMD_WIDTH 2U
+#define XHC_RH2HSC0__CMD_RESETVALUE 0x0U
+#define XHC_RH2HSC0__reserved 1U
+#define XHC_RH2HSC0__reserved_L 1U
+#define XHC_RH2HSC0__reserved_R 1U
+#define XHC_RH2HSC0__reserved_WIDTH 1U
+#define XHC_RH2HSC0__reserved_RESETVALUE 0x0U
+#define XHC_RH2HSC0__STB 0U
+#define XHC_RH2HSC0__STB_L 0U
+#define XHC_RH2HSC0__STB_R 0U
+#define XHC_RH2HSC0__STB_WIDTH 1U
+#define XHC_RH2HSC0__STB_RESETVALUE 0x0U
+#define XHC_RH2HSC0__RESERVED_L 15U
+#define XHC_RH2HSC0__RESERVED_R 8U
+#define XHC_RH2HSC0_WIDTH 32U
+#define XHC_RH2HSC0__WIDTH 32U
+#define XHC_RH2HSC0_ALL_L 31U
+#define XHC_RH2HSC0_ALL_R 0U
+#define XHC_RH2HSC0__ALL_L 31U
+#define XHC_RH2HSC0__ALL_R 0U
+#define XHC_RH2HSC0_DATAMASK 0xffff00ffU
+#define XHC_RH2HSC0_RDWRMASK 0x0000ff00U
+#define XHC_RH2HSC0_RESETVALUE 0x00000000U
+
+#define XHC_RH2HSR0_OFFSET 0xd14U
+#define XHC_RH2HSR0_BASE 0xd14U
+#define XHC_RH2HSR0__C2U_L 31U
+#define XHC_RH2HSR0__C2U_R 24U
+#define XHC_RH2HSR0__C2U_WIDTH 8U
+#define XHC_RH2HSR0__C2U_RESETVALUE 0x00U
+#define XHC_RH2HSR0__C1U_L 23U
+#define XHC_RH2HSR0__C1U_R 16U
+#define XHC_RH2HSR0__C1U_WIDTH 8U
+#define XHC_RH2HSR0__C1U_RESETVALUE 0x00U
+#define XHC_RH2HSR0__reserved_L 15U
+#define XHC_RH2HSR0__reserved_R 8U
+#define XHC_RH2HSR0__reserved_WIDTH 8U
+#define XHC_RH2HSR0__reserved_RESETVALUE 0x00U
+#define XHC_RH2HSR0__RTY_L 7U
+#define XHC_RH2HSR0__RTY_R 0U
+#define XHC_RH2HSR0__RTY_WIDTH 8U
+#define XHC_RH2HSR0__RTY_RESETVALUE 0x00U
+#define XHC_RH2HSR0_WIDTH 32U
+#define XHC_RH2HSR0__WIDTH 32U
+#define XHC_RH2HSR0_ALL_L 31U
+#define XHC_RH2HSR0_ALL_R 0U
+#define XHC_RH2HSR0__ALL_L 31U
+#define XHC_RH2HSR0__ALL_R 0U
+#define XHC_RH2HSR0_DATAMASK 0xffffffffU
+#define XHC_RH2HSR0_RDWRMASK 0x00000000U
+#define XHC_RH2HSR0_RESETVALUE 0x00000000U
+
+#define XHC_RH2HSC1_OFFSET 0xd18U
+#define XHC_RH2HSC1_BASE 0xd18U
+#define XHC_RH2HSC1__TMR_L 31U
+#define XHC_RH2HSC1__TMR_R 16U
+#define XHC_RH2HSC1__TMR_WIDTH 16U
+#define XHC_RH2HSC1__TMR_RESETVALUE 0x0000U
+#define XHC_RH2HSC1__RSL_L 7U
+#define XHC_RH2HSC1__RSL_R 6U
+#define XHC_RH2HSC1__RSL_WIDTH 2U
+#define XHC_RH2HSC1__RSL_RESETVALUE 0x0U
+#define XHC_RH2HSC1__AS_M_L 5U
+#define XHC_RH2HSC1__AS_M_R 4U
+#define XHC_RH2HSC1__AS_M_WIDTH 2U
+#define XHC_RH2HSC1__AS_M_RESETVALUE 0x0U
+#define XHC_RH2HSC1__CMD_L 3U
+#define XHC_RH2HSC1__CMD_R 2U
+#define XHC_RH2HSC1__CMD_WIDTH 2U
+#define XHC_RH2HSC1__CMD_RESETVALUE 0x0U
+#define XHC_RH2HSC1__reserved 1U
+#define XHC_RH2HSC1__reserved_L 1U
+#define XHC_RH2HSC1__reserved_R 1U
+#define XHC_RH2HSC1__reserved_WIDTH 1U
+#define XHC_RH2HSC1__reserved_RESETVALUE 0x0U
+#define XHC_RH2HSC1__STB 0U
+#define XHC_RH2HSC1__STB_L 0U
+#define XHC_RH2HSC1__STB_R 0U
+#define XHC_RH2HSC1__STB_WIDTH 1U
+#define XHC_RH2HSC1__STB_RESETVALUE 0x0U
+#define XHC_RH2HSC1__RESERVED_L 15U
+#define XHC_RH2HSC1__RESERVED_R 8U
+#define XHC_RH2HSC1_WIDTH 32U
+#define XHC_RH2HSC1__WIDTH 32U
+#define XHC_RH2HSC1_ALL_L 31U
+#define XHC_RH2HSC1_ALL_R 0U
+#define XHC_RH2HSC1__ALL_L 31U
+#define XHC_RH2HSC1__ALL_R 0U
+#define XHC_RH2HSC1_DATAMASK 0xffff00ffU
+#define XHC_RH2HSC1_RDWRMASK 0x0000ff00U
+#define XHC_RH2HSC1_RESETVALUE 0x00000000U
+
+#define XHC_RH2HSR1_OFFSET 0xd1cU
+#define XHC_RH2HSR1_BASE 0xd1cU
+#define XHC_RH2HSR1__C2U_L 31U
+#define XHC_RH2HSR1__C2U_R 24U
+#define XHC_RH2HSR1__C2U_WIDTH 8U
+#define XHC_RH2HSR1__C2U_RESETVALUE 0x00U
+#define XHC_RH2HSR1__C1U_L 23U
+#define XHC_RH2HSR1__C1U_R 16U
+#define XHC_RH2HSR1__C1U_WIDTH 8U
+#define XHC_RH2HSR1__C1U_RESETVALUE 0x00U
+#define XHC_RH2HSR1__reserved_L 15U
+#define XHC_RH2HSR1__reserved_R 8U
+#define XHC_RH2HSR1__reserved_WIDTH 8U
+#define XHC_RH2HSR1__reserved_RESETVALUE 0x00U
+#define XHC_RH2HSR1__RTY_L 7U
+#define XHC_RH2HSR1__RTY_R 0U
+#define XHC_RH2HSR1__RTY_WIDTH 8U
+#define XHC_RH2HSR1__RTY_RESETVALUE 0x00U
+#define XHC_RH2HSR1_WIDTH 32U
+#define XHC_RH2HSR1__WIDTH 32U
+#define XHC_RH2HSR1_ALL_L 31U
+#define XHC_RH2HSR1_ALL_R 0U
+#define XHC_RH2HSR1__ALL_L 31U
+#define XHC_RH2HSR1__ALL_R 0U
+#define XHC_RH2HSR1_DATAMASK 0xffffffffU
+#define XHC_RH2HSR1_RDWRMASK 0x00000000U
+#define XHC_RH2HSR1_RESETVALUE 0x00000000U
+
+#define XHC_RH2HSC2_OFFSET 0xd20U
+#define XHC_RH2HSC2_BASE 0xd20U
+#define XHC_RH2HSC2__TMR_L 31U
+#define XHC_RH2HSC2__TMR_R 16U
+#define XHC_RH2HSC2__TMR_WIDTH 16U
+#define XHC_RH2HSC2__TMR_RESETVALUE 0x0000U
+#define XHC_RH2HSC2__RSL_L 7U
+#define XHC_RH2HSC2__RSL_R 6U
+#define XHC_RH2HSC2__RSL_WIDTH 2U
+#define XHC_RH2HSC2__RSL_RESETVALUE 0x0U
+#define XHC_RH2HSC2__AS_M_L 5U
+#define XHC_RH2HSC2__AS_M_R 4U
+#define XHC_RH2HSC2__AS_M_WIDTH 2U
+#define XHC_RH2HSC2__AS_M_RESETVALUE 0x0U
+#define XHC_RH2HSC2__CMD_L 3U
+#define XHC_RH2HSC2__CMD_R 2U
+#define XHC_RH2HSC2__CMD_WIDTH 2U
+#define XHC_RH2HSC2__CMD_RESETVALUE 0x0U
+#define XHC_RH2HSC2__reserved 1U
+#define XHC_RH2HSC2__reserved_L 1U
+#define XHC_RH2HSC2__reserved_R 1U
+#define XHC_RH2HSC2__reserved_WIDTH 1U
+#define XHC_RH2HSC2__reserved_RESETVALUE 0x0U
+#define XHC_RH2HSC2__STB 0U
+#define XHC_RH2HSC2__STB_L 0U
+#define XHC_RH2HSC2__STB_R 0U
+#define XHC_RH2HSC2__STB_WIDTH 1U
+#define XHC_RH2HSC2__STB_RESETVALUE 0x0U
+#define XHC_RH2HSC2__RESERVED_L 15U
+#define XHC_RH2HSC2__RESERVED_R 8U
+#define XHC_RH2HSC2_WIDTH 32U
+#define XHC_RH2HSC2__WIDTH 32U
+#define XHC_RH2HSC2_ALL_L 31U
+#define XHC_RH2HSC2_ALL_R 0U
+#define XHC_RH2HSC2__ALL_L 31U
+#define XHC_RH2HSC2__ALL_R 0U
+#define XHC_RH2HSC2_DATAMASK 0xffff00ffU
+#define XHC_RH2HSC2_RDWRMASK 0x0000ff00U
+#define XHC_RH2HSC2_RESETVALUE 0x00000000U
+
+#define XHC_RH2HSR2_OFFSET 0xd24U
+#define XHC_RH2HSR2_BASE 0xd24U
+#define XHC_RH2HSR2__C2U_L 31U
+#define XHC_RH2HSR2__C2U_R 24U
+#define XHC_RH2HSR2__C2U_WIDTH 8U
+#define XHC_RH2HSR2__C2U_RESETVALUE 0x00U
+#define XHC_RH2HSR2__C1U_L 23U
+#define XHC_RH2HSR2__C1U_R 16U
+#define XHC_RH2HSR2__C1U_WIDTH 8U
+#define XHC_RH2HSR2__C1U_RESETVALUE 0x00U
+#define XHC_RH2HSR2__reserved_L 15U
+#define XHC_RH2HSR2__reserved_R 8U
+#define XHC_RH2HSR2__reserved_WIDTH 8U
+#define XHC_RH2HSR2__reserved_RESETVALUE 0x00U
+#define XHC_RH2HSR2__RTY_L 7U
+#define XHC_RH2HSR2__RTY_R 0U
+#define XHC_RH2HSR2__RTY_WIDTH 8U
+#define XHC_RH2HSR2__RTY_RESETVALUE 0x00U
+#define XHC_RH2HSR2_WIDTH 32U
+#define XHC_RH2HSR2__WIDTH 32U
+#define XHC_RH2HSR2_ALL_L 31U
+#define XHC_RH2HSR2_ALL_R 0U
+#define XHC_RH2HSR2__ALL_L 31U
+#define XHC_RH2HSR2__ALL_R 0U
+#define XHC_RH2HSR2_DATAMASK 0xffffffffU
+#define XHC_RH2HSR2_RDWRMASK 0x00000000U
+#define XHC_RH2HSR2_RESETVALUE 0x00000000U
+
+#define XHC_RH2HSC3_OFFSET 0xd28U
+#define XHC_RH2HSC3_BASE 0xd28U
+#define XHC_RH2HSC3__TMR_L 31U
+#define XHC_RH2HSC3__TMR_R 16U
+#define XHC_RH2HSC3__TMR_WIDTH 16U
+#define XHC_RH2HSC3__TMR_RESETVALUE 0x0000U
+#define XHC_RH2HSC3__RSL_L 7U
+#define XHC_RH2HSC3__RSL_R 6U
+#define XHC_RH2HSC3__RSL_WIDTH 2U
+#define XHC_RH2HSC3__RSL_RESETVALUE 0x0U
+#define XHC_RH2HSC3__AS_M_L 5U
+#define XHC_RH2HSC3__AS_M_R 4U
+#define XHC_RH2HSC3__AS_M_WIDTH 2U
+#define XHC_RH2HSC3__AS_M_RESETVALUE 0x0U
+#define XHC_RH2HSC3__CMD_L 3U
+#define XHC_RH2HSC3__CMD_R 2U
+#define XHC_RH2HSC3__CMD_WIDTH 2U
+#define XHC_RH2HSC3__CMD_RESETVALUE 0x0U
+#define XHC_RH2HSC3__reserved 1U
+#define XHC_RH2HSC3__reserved_L 1U
+#define XHC_RH2HSC3__reserved_R 1U
+#define XHC_RH2HSC3__reserved_WIDTH 1U
+#define XHC_RH2HSC3__reserved_RESETVALUE 0x0U
+#define XHC_RH2HSC3__STB 0U
+#define XHC_RH2HSC3__STB_L 0U
+#define XHC_RH2HSC3__STB_R 0U
+#define XHC_RH2HSC3__STB_WIDTH 1U
+#define XHC_RH2HSC3__STB_RESETVALUE 0x0U
+#define XHC_RH2HSC3__RESERVED_L 15U
+#define XHC_RH2HSC3__RESERVED_R 8U
+#define XHC_RH2HSC3_WIDTH 32U
+#define XHC_RH2HSC3__WIDTH 32U
+#define XHC_RH2HSC3_ALL_L 31U
+#define XHC_RH2HSC3_ALL_R 0U
+#define XHC_RH2HSC3__ALL_L 31U
+#define XHC_RH2HSC3__ALL_R 0U
+#define XHC_RH2HSC3_DATAMASK 0xffff00ffU
+#define XHC_RH2HSC3_RDWRMASK 0x0000ff00U
+#define XHC_RH2HSC3_RESETVALUE 0x00000000U
+
+#define XHC_RH2HSR3_OFFSET 0xd2cU
+#define XHC_RH2HSR3_BASE 0xd2cU
+#define XHC_RH2HSR3__C2U_L 31U
+#define XHC_RH2HSR3__C2U_R 24U
+#define XHC_RH2HSR3__C2U_WIDTH 8U
+#define XHC_RH2HSR3__C2U_RESETVALUE 0x00U
+#define XHC_RH2HSR3__C1U_L 23U
+#define XHC_RH2HSR3__C1U_R 16U
+#define XHC_RH2HSR3__C1U_WIDTH 8U
+#define XHC_RH2HSR3__C1U_RESETVALUE 0x00U
+#define XHC_RH2HSR3__reserved_L 15U
+#define XHC_RH2HSR3__reserved_R 8U
+#define XHC_RH2HSR3__reserved_WIDTH 8U
+#define XHC_RH2HSR3__reserved_RESETVALUE 0x00U
+#define XHC_RH2HSR3__RTY_L 7U
+#define XHC_RH2HSR3__RTY_R 0U
+#define XHC_RH2HSR3__RTY_WIDTH 8U
+#define XHC_RH2HSR3__RTY_RESETVALUE 0x00U
+#define XHC_RH2HSR3_WIDTH 32U
+#define XHC_RH2HSR3__WIDTH 32U
+#define XHC_RH2HSR3_ALL_L 31U
+#define XHC_RH2HSR3_ALL_R 0U
+#define XHC_RH2HSR3__ALL_L 31U
+#define XHC_RH2HSR3__ALL_R 0U
+#define XHC_RH2HSR3_DATAMASK 0xffffffffU
+#define XHC_RH2HSR3_RDWRMASK 0x00000000U
+#define XHC_RH2HSR3_RESETVALUE 0x00000000U
+
+#define XHC_ECHU2P_OFFSET 0xd30U
+#define XHC_ECHU2P_BASE 0xd30U
+#define XHC_ECHU2P__reserved_L 31U
+#define XHC_ECHU2P__reserved_R 16U
+#define XHC_ECHU2P__reserved_WIDTH 16U
+#define XHC_ECHU2P__reserved_RESETVALUE 0x0000U
+#define XHC_ECHU2P__NCP_L 15U
+#define XHC_ECHU2P__NCP_R 8U
+#define XHC_ECHU2P__NCP_WIDTH 8U
+#define XHC_ECHU2P__NCP_RESETVALUE 0x04U
+#define XHC_ECHU2P__CID_L 7U
+#define XHC_ECHU2P__CID_R 0U
+#define XHC_ECHU2P__CID_WIDTH 8U
+#define XHC_ECHU2P__CID_RESETVALUE 0xcaU
+#define XHC_ECHU2P_WIDTH 32U
+#define XHC_ECHU2P__WIDTH 32U
+#define XHC_ECHU2P_ALL_L 31U
+#define XHC_ECHU2P_ALL_R 0U
+#define XHC_ECHU2P__ALL_L 31U
+#define XHC_ECHU2P__ALL_R 0U
+#define XHC_ECHU2P_DATAMASK 0xffffffffU
+#define XHC_ECHU2P_RDWRMASK 0x00000000U
+#define XHC_ECHU2P_RESETVALUE 0x000004caU
+
+#define XHC_U2PVER_OFFSET 0xd34U
+#define XHC_U2PVER_BASE 0xd34U
+#define XHC_U2PVER__MAJ_L 31U
+#define XHC_U2PVER__MAJ_R 28U
+#define XHC_U2PVER__MAJ_WIDTH 4U
+#define XHC_U2PVER__MAJ_RESETVALUE 0x0U
+#define XHC_U2PVER__MIN_L 27U
+#define XHC_U2PVER__MIN_R 24U
+#define XHC_U2PVER__MIN_WIDTH 4U
+#define XHC_U2PVER__MIN_RESETVALUE 0x0U
+#define XHC_U2PVER__RLS_L 23U
+#define XHC_U2PVER__RLS_R 20U
+#define XHC_U2PVER__RLS_WIDTH 4U
+#define XHC_U2PVER__RLS_RESETVALUE 0x0U
+#define XHC_U2PVER__reserved_L 19U
+#define XHC_U2PVER__reserved_R 0U
+#define XHC_U2PVER__reserved_WIDTH 20U
+#define XHC_U2PVER__reserved_RESETVALUE 0x00000U
+#define XHC_U2PVER_WIDTH 32U
+#define XHC_U2PVER__WIDTH 32U
+#define XHC_U2PVER_ALL_L 31U
+#define XHC_U2PVER_ALL_R 0U
+#define XHC_U2PVER__ALL_L 31U
+#define XHC_U2PVER__ALL_R 0U
+#define XHC_U2PVER_DATAMASK 0xffffffffU
+#define XHC_U2PVER_RDWRMASK 0x00000000U
+#define XHC_U2PVER_RESETVALUE 0x00000000U
+
+#define XHC_U2PMGN_OFFSET 0xd38U
+#define XHC_U2PMGN_BASE 0xd38U
+#define XHC_U2PMGN__MGN_L 31U
+#define XHC_U2PMGN__MGN_R 0U
+#define XHC_U2PMGN__MGN_WIDTH 32U
+#define XHC_U2PMGN__MGN_RESETVALUE 0x4b534b4dU
+#define XHC_U2PMGN_WIDTH 32U
+#define XHC_U2PMGN__WIDTH 32U
+#define XHC_U2PMGN_ALL_L 31U
+#define XHC_U2PMGN_ALL_R 0U
+#define XHC_U2PMGN__ALL_L 31U
+#define XHC_U2PMGN__ALL_R 0U
+#define XHC_U2PMGN_DATAMASK 0xffffffffU
+#define XHC_U2PMGN_RDWRMASK 0x00000000U
+#define XHC_U2PMGN_RESETVALUE 0x4b534b4dU
+
+#define XHC_ECHRSV2_OFFSET 0xd40U
+#define XHC_ECHRSV2_BASE 0xd40U
+#define XHC_ECHRSV2__reserved_L 31U
+#define XHC_ECHRSV2__reserved_R 16U
+#define XHC_ECHRSV2__reserved_WIDTH 16U
+#define XHC_ECHRSV2__reserved_RESETVALUE 0x0000U
+#define XHC_ECHRSV2__NCP_L 15U
+#define XHC_ECHRSV2__NCP_R 8U
+#define XHC_ECHRSV2__NCP_WIDTH 8U
+#define XHC_ECHRSV2__NCP_RESETVALUE 0x00U
+#define XHC_ECHRSV2__CID_L 7U
+#define XHC_ECHRSV2__CID_R 0U
+#define XHC_ECHRSV2__CID_WIDTH 8U
+#define XHC_ECHRSV2__CID_RESETVALUE 0xffU
+#define XHC_ECHRSV2_WIDTH 32U
+#define XHC_ECHRSV2__WIDTH 32U
+#define XHC_ECHRSV2_ALL_L 31U
+#define XHC_ECHRSV2_ALL_R 0U
+#define XHC_ECHRSV2__ALL_L 31U
+#define XHC_ECHRSV2__ALL_R 0U
+#define XHC_ECHRSV2_DATAMASK 0xffffffffU
+#define XHC_ECHRSV2_RDWRMASK 0x00000000U
+#define XHC_ECHRSV2_RESETVALUE 0x000000ffU
+
+#define XHC_ECHIRA_OFFSET 0xf90U
+#define XHC_ECHIRA_BASE 0xf90U
+#define XHC_ECHIRA__reserved_L 31U
+#define XHC_ECHIRA__reserved_R 16U
+#define XHC_ECHIRA__reserved_WIDTH 16U
+#define XHC_ECHIRA__reserved_RESETVALUE 0x0000U
+#define XHC_ECHIRA__NCP_L 15U
+#define XHC_ECHIRA__NCP_R 8U
+#define XHC_ECHIRA__NCP_WIDTH 8U
+#define XHC_ECHIRA__NCP_RESETVALUE 0x04U
+#define XHC_ECHIRA__CID_L 7U
+#define XHC_ECHIRA__CID_R 0U
+#define XHC_ECHIRA__CID_WIDTH 8U
+#define XHC_ECHIRA__CID_RESETVALUE 0xfdU
+#define XHC_ECHIRA_WIDTH 32U
+#define XHC_ECHIRA__WIDTH 32U
+#define XHC_ECHIRA_ALL_L 31U
+#define XHC_ECHIRA_ALL_R 0U
+#define XHC_ECHIRA__ALL_L 31U
+#define XHC_ECHIRA__ALL_R 0U
+#define XHC_ECHIRA_DATAMASK 0xffffffffU
+#define XHC_ECHIRA_RDWRMASK 0x00000000U
+#define XHC_ECHIRA_RESETVALUE 0x000004fdU
+
+#define XHC_IRAADR_OFFSET 0xf98U
+#define XHC_IRAADR_BASE 0xf98U
+#define XHC_IRAADR__ADR_L 23U
+#define XHC_IRAADR__ADR_R 2U
+#define XHC_IRAADR__ADR_WIDTH 22U
+#define XHC_IRAADR__ADR_RESETVALUE 0x0U
+#define XHC_IRAADR__reserved 1U
+#define XHC_IRAADR__reserved_L 1U
+#define XHC_IRAADR__reserved_R 1U
+#define XHC_IRAADR__reserved_WIDTH 1U
+#define XHC_IRAADR__reserved_RESETVALUE 0x0U
+#define XHC_IRAADR__MOD 0U
+#define XHC_IRAADR__MOD_L 0U
+#define XHC_IRAADR__MOD_R 0U
+#define XHC_IRAADR__MOD_WIDTH 1U
+#define XHC_IRAADR__MOD_RESETVALUE 0x0U
+#define XHC_IRAADR__RESERVED_L 31U
+#define XHC_IRAADR__RESERVED_R 24U
+#define XHC_IRAADR_WIDTH 24U
+#define XHC_IRAADR__WIDTH 24U
+#define XHC_IRAADR_ALL_L 23U
+#define XHC_IRAADR_ALL_R 0U
+#define XHC_IRAADR__ALL_L 23U
+#define XHC_IRAADR__ALL_R 0U
+#define XHC_IRAADR_DATAMASK 0x00ffffffU
+#define XHC_IRAADR_RDWRMASK 0xff000000U
+#define XHC_IRAADR_RESETVALUE 0x000000U
+
+#define XHC_IRADAT_OFFSET 0xf9cU
+#define XHC_IRADAT_BASE 0xf9cU
+#define XHC_IRADAT__DAT_L 31U
+#define XHC_IRADAT__DAT_R 0U
+#define XHC_IRADAT__DAT_WIDTH 32U
+#define XHC_IRADAT__DAT_RESETVALUE 0x00000000U
+#define XHC_IRADAT_WIDTH 32U
+#define XHC_IRADAT__WIDTH 32U
+#define XHC_IRADAT_ALL_L 31U
+#define XHC_IRADAT_ALL_R 0U
+#define XHC_IRADAT__ALL_L 31U
+#define XHC_IRADAT__ALL_R 0U
+#define XHC_IRADAT_DATAMASK 0xffffffffU
+#define XHC_IRADAT_RDWRMASK 0x00000000U
+#define XHC_IRADAT_RESETVALUE 0x00000000U
+
+
+#define XHC_ECHHST_OFFSET 0xfa0U
+#define XHC_ECHHST_BASE 0xfa0U
+#define XHC_ECHHST__CCC 31U
+#define XHC_ECHHST__CCC_L 31U
+#define XHC_ECHHST__CCC_R 31U
+#define XHC_ECHHST__CCC_WIDTH 1U
+#define XHC_ECHHST__CCC_RESETVALUE 0x1U
+#define XHC_ECHHST__PME 30U
+#define XHC_ECHHST__PME_L 30U
+#define XHC_ECHHST__PME_R 30U
+#define XHC_ECHHST__PME_WIDTH 1U
+#define XHC_ECHHST__PME_RESETVALUE 0x0U
+#define XHC_ECHHST__AUX_L 29U
+#define XHC_ECHHST__AUX_R 24U
+#define XHC_ECHHST__AUX_WIDTH 6U
+#define XHC_ECHHST__AUX_RESETVALUE 0x0U
+#define XHC_ECHHST__IRA 20U
+#define XHC_ECHHST__IRA_L 20U
+#define XHC_ECHHST__IRA_R 20U
+#define XHC_ECHHST__IRA_WIDTH 1U
+#define XHC_ECHHST__IRA_RESETVALUE 0x0U
+#define XHC_ECHHST__ULS 19U
+#define XHC_ECHHST__ULS_L 19U
+#define XHC_ECHHST__ULS_R 19U
+#define XHC_ECHHST__ULS_WIDTH 1U
+#define XHC_ECHHST__ULS_RESETVALUE 0x0U
+#define XHC_ECHHST__reserved 18U
+#define XHC_ECHHST__reserved_L 18U
+#define XHC_ECHHST__reserved_R 18U
+#define XHC_ECHHST__reserved_WIDTH 1U
+#define XHC_ECHHST__reserved_RESETVALUE 0x0U
+#define XHC_ECHHST__TEDA 17U
+#define XHC_ECHHST__TEDA_L 17U
+#define XHC_ECHHST__TEDA_R 17U
+#define XHC_ECHHST__TEDA_WIDTH 1U
+#define XHC_ECHHST__TEDA_RESETVALUE 0x0U
+#define XHC_ECHHST__FSW 16U
+#define XHC_ECHHST__FSW_L 16U
+#define XHC_ECHHST__FSW_R 16U
+#define XHC_ECHHST__FSW_WIDTH 1U
+#define XHC_ECHHST__FSW_RESETVALUE 0x1U
+#define XHC_ECHHST__NCP_L 15U
+#define XHC_ECHHST__NCP_R 8U
+#define XHC_ECHHST__NCP_WIDTH 8U
+#define XHC_ECHHST__NCP_RESETVALUE 0x04U
+#define XHC_ECHHST__CID_L 7U
+#define XHC_ECHHST__CID_R 0U
+#define XHC_ECHHST__CID_WIDTH 8U
+#define XHC_ECHHST__CID_RESETVALUE 0xfcU
+#define XHC_ECHHST__RESERVED_L 23U
+#define XHC_ECHHST__RESERVED_R 21U
+#define XHC_ECHHST_WIDTH 32U
+#define XHC_ECHHST__WIDTH 32U
+#define XHC_ECHHST_ALL_L 31U
+#define XHC_ECHHST_ALL_R 0U
+#define XHC_ECHHST__ALL_L 31U
+#define XHC_ECHHST__ALL_R 0U
+#define XHC_ECHHST_DATAMASK 0xff1fffffU
+#define XHC_ECHHST_RDWRMASK 0x00e00000U
+#define XHC_ECHHST_RESETVALUE 0x800104fcU
+
+#define XHC_HSTDBG_OFFSET 0xfa4U
+#define XHC_HSTDBG_BASE 0xfa4U
+#define XHC_HSTDBG__ETE 31U
+#define XHC_HSTDBG__ETE_L 31U
+#define XHC_HSTDBG__ETE_R 31U
+#define XHC_HSTDBG__ETE_WIDTH 1U
+#define XHC_HSTDBG__ETE_RESETVALUE 0x0U
+#define XHC_HSTDBG__reserved_L 30U
+#define XHC_HSTDBG__reserved_R 16U
+#define XHC_HSTDBG__reserved_WIDTH 15U
+#define XHC_HSTDBG__reserved_RESETVALUE 0x0U
+#define XHC_HSTDBG__OUTP_L 15U
+#define XHC_HSTDBG__OUTP_R 8U
+#define XHC_HSTDBG__OUTP_WIDTH 8U
+#define XHC_HSTDBG__OUTP_RESETVALUE 0x00U
+#define XHC_HSTDBG__INP_L 7U
+#define XHC_HSTDBG__INP_R 0U
+#define XHC_HSTDBG__INP_WIDTH 8U
+#define XHC_HSTDBG__INP_RESETVALUE 0x00U
+#define XHC_HSTDBG_WIDTH 32U
+#define XHC_HSTDBG__WIDTH 32U
+#define XHC_HSTDBG_ALL_L 31U
+#define XHC_HSTDBG_ALL_R 0U
+#define XHC_HSTDBG__ALL_L 31U
+#define XHC_HSTDBG__ALL_R 0U
+#define XHC_HSTDBG_DATAMASK 0xffffffffU
+#define XHC_HSTDBG_RDWRMASK 0x00000000U
+#define XHC_HSTDBG_RESETVALUE 0x00000000U
+
+#define XHC_HSTNPL_OFFSET 0xfa8U
+#define XHC_HSTNPL_BASE 0xfa8U
+#define XHC_HSTNPL__NPL_L 31U
+#define XHC_HSTNPL__NPL_R 9U
+#define XHC_HSTNPL__NPL_WIDTH 23U
+#define XHC_HSTNPL__NPL_RESETVALUE 0x0U
+#define XHC_HSTNPL__reserved_L 8U
+#define XHC_HSTNPL__reserved_R 0U
+#define XHC_HSTNPL__reserved_WIDTH 9U
+#define XHC_HSTNPL__reserved_RESETVALUE 0x0U
+#define XHC_HSTNPL_WIDTH 32U
+#define XHC_HSTNPL__WIDTH 32U
+#define XHC_HSTNPL_ALL_L 31U
+#define XHC_HSTNPL_ALL_R 0U
+#define XHC_HSTNPL__ALL_L 31U
+#define XHC_HSTNPL__ALL_R 0U
+#define XHC_HSTNPL_DATAMASK 0xffffffffU
+#define XHC_HSTNPL_RDWRMASK 0x00000000U
+#define XHC_HSTNPL_RESETVALUE 0x00000000U
+
+#define XHC_HSTNPH_OFFSET 0xfacU
+#define XHC_HSTNPH_BASE 0xfacU
+#define XHC_HSTNPH__NPH_L 31U
+#define XHC_HSTNPH__NPH_R 0U
+#define XHC_HSTNPH__NPH_WIDTH 32U
+#define XHC_HSTNPH__NPH_RESETVALUE 0x00000000U
+#define XHC_HSTNPH_WIDTH 32U
+#define XHC_HSTNPH__WIDTH 32U
+#define XHC_HSTNPH_ALL_L 31U
+#define XHC_HSTNPH_ALL_R 0U
+#define XHC_HSTNPH__ALL_L 31U
+#define XHC_HSTNPH__ALL_R 0U
+#define XHC_HSTNPH_DATAMASK 0xffffffffU
+#define XHC_HSTNPH_RDWRMASK 0x00000000U
+#define XHC_HSTNPH_RESETVALUE 0x00000000U
+
+#define XHC_ECHRBV_OFFSET 0xfb0U
+#define XHC_ECHRBV_BASE 0xfb0U
+#define XHC_ECHRBV__MAJ_L 31U
+#define XHC_ECHRBV__MAJ_R 28U
+#define XHC_ECHRBV__MAJ_WIDTH 4U
+#define XHC_ECHRBV__MAJ_RESETVALUE 0x0U
+#define XHC_ECHRBV__MIN_L 27U
+#define XHC_ECHRBV__MIN_R 24U
+#define XHC_ECHRBV__MIN_WIDTH 4U
+#define XHC_ECHRBV__MIN_RESETVALUE 0x0U
+#define XHC_ECHRBV__RLS_L 23U
+#define XHC_ECHRBV__RLS_R 16U
+#define XHC_ECHRBV__RLS_WIDTH 8U
+#define XHC_ECHRBV__RLS_RESETVALUE 0x00U
+#define XHC_ECHRBV__NCP_L 15U
+#define XHC_ECHRBV__NCP_R 8U
+#define XHC_ECHRBV__NCP_WIDTH 8U
+#define XHC_ECHRBV__NCP_RESETVALUE 0x00U
+#define XHC_ECHRBV__CID_L 7U
+#define XHC_ECHRBV__CID_R 0U
+#define XHC_ECHRBV__CID_WIDTH 8U
+#define XHC_ECHRBV__CID_RESETVALUE 0xfeU
+#define XHC_ECHRBV_WIDTH 32U
+#define XHC_ECHRBV__WIDTH 32U
+#define XHC_ECHRBV_ALL_L 31U
+#define XHC_ECHRBV_ALL_R 0U
+#define XHC_ECHRBV__ALL_L 31U
+#define XHC_ECHRBV__ALL_R 0U
+#define XHC_ECHRBV_DATAMASK 0xffffffffU
+#define XHC_ECHRBV_RDWRMASK 0x00000000U
+#define XHC_ECHRBV_RESETVALUE 0x000000feU
+
+#define XHC_RBVPDT_OFFSET 0xfb4U
+#define XHC_RBVPDT_BASE 0xfb4U
+#define XHC_RBVPDT__VDR_L 31U
+#define XHC_RBVPDT__VDR_R 16U
+#define XHC_RBVPDT__VDR_WIDTH 16U
+#define XHC_RBVPDT__VDR_RESETVALUE 0x0a5cU
+#define XHC_RBVPDT__PDT_L 15U
+#define XHC_RBVPDT__PDT_R 0U
+#define XHC_RBVPDT__PDT_WIDTH 16U
+#define XHC_RBVPDT__PDT_RESETVALUE 0x0000U
+#define XHC_RBVPDT_WIDTH 32U
+#define XHC_RBVPDT__WIDTH 32U
+#define XHC_RBVPDT_ALL_L 31U
+#define XHC_RBVPDT_ALL_R 0U
+#define XHC_RBVPDT__ALL_L 31U
+#define XHC_RBVPDT__ALL_R 0U
+#define XHC_RBVPDT_DATAMASK 0xffffffffU
+#define XHC_RBVPDT_RDWRMASK 0x00000000U
+#define XHC_RBVPDT_RESETVALUE 0x0a5c0000U
+
+#define XHC_RBVMGN_OFFSET 0xfbcU
+#define XHC_RBVMGN_BASE 0xfbcU
+#define XHC_RBVMGN__MGN_L 31U
+#define XHC_RBVMGN__MGN_R 0U
+#define XHC_RBVMGN__MGN_WIDTH 32U
+#define XHC_RBVMGN__MGN_RESETVALUE 0x52535354U
+#define XHC_RBVMGN_WIDTH 32U
+#define XHC_RBVMGN__WIDTH 32U
+#define XHC_RBVMGN_ALL_L 31U
+#define XHC_RBVMGN_ALL_R 0U
+#define XHC_RBVMGN__ALL_L 31U
+#define XHC_RBVMGN__ALL_R 0U
+#define XHC_RBVMGN_DATAMASK 0xffffffffU
+#define XHC_RBVMGN_RDWRMASK 0x00000000U
+#define XHC_RBVMGN_RESETVALUE 0x52535354U
+
+/* PORTSC field defines */
+#define XHC_PORTSC__PS_LINK_STATE_U0 0U
+#define XHC_PORTSC__PS_LINK_STATE_U1 1U
+#define XHC_PORTSC__PS_LINK_STATE_U2 2U
+#define XHC_PORTSC__PS_LINK_STATE_U3 3U
+#define XHC_PORTSC__PS_LINK_STATE_DISABLED 4U
+#define XHC_PORTSC__PS_LINK_STATE_RX_DETECT 5U
+#define XHC_PORTSC__PS_LINK_STATE_INACTIVE 6U
+#define XHC_PORTSC__PS_LINK_STATE_POLLING 7U
+#define XHC_PORTSC__PS_LINK_STATE_RECOVERY 8U
+#define XHC_PORTSC__PS_LINK_STATE_HOT_RESET 9U
+#define XHC_PORTSC__PS_LINK_STATE_COMPLIANCE 10U
+#define XHC_PORTSC__PS_LINK_STATE_TEST 11U
+#define XHC_PORTSC__PS_LINK_STATE_RESUME 15U
+
+#define XHC_PORTSC__PS_SPEED_UNDEFINED 0U
+#define XHC_PORTSC__PS_FS 1U
+#define XHC_PORTSC__PS_LS 2U
+#define XHC_PORTSC__PS_HS 3U
+#define XHC_PORTSC__PS_SS 4U
+
+/* macros and inline functions */
+
+/* write 64bit ptr 'p' to destination 'd' with offset 'v' */
+inline void WRITE64_REG_PTRL(uint32_t r, uint32_t *p)
+{
+ uint32_t *ptr = (uint32_t *) (uint64_t) (XHC_BASE + r);
+
+ *ptr = (uint32_t) ((uint64_t) p & (uint64_t) 0xffffffffU);
+}
+
+inline void WRITE64_REG_PTRH(uint32_t r, uint32_t *p)
+{
+ uint32_t *ptr = (uint32_t *) (uint64_t) (XHC_BASE + r);
+
+ *ptr = (uint32_t) ((uint64_t) p >> 32U);
+}
+
+#define XHC_REG_RD(addr) mmio_read_32(XHC_BASE + addr)
+
+#define XHC_REG_WR(addr, val) mmio_write_32(XHC_BASE+addr, val)
+
+#endif /* USBH_XHCI_REGS_H */
+
diff --git a/include/drivers/fwu/fwu.h b/include/drivers/fwu/fwu.h
new file mode 100644
index 0000000..ae06da9
--- /dev/null
+++ b/include/drivers/fwu/fwu.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FWU_H
+#define FWU_H
+
+#include <stdbool.h>
+
+void fwu_init(void);
+bool fwu_is_trial_run_state(void);
+
+#endif /* FWU_H */
diff --git a/include/drivers/fwu/fwu_metadata.h b/include/drivers/fwu/fwu_metadata.h
new file mode 100644
index 0000000..2e88de5
--- /dev/null
+++ b/include/drivers/fwu/fwu_metadata.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * FWU metadata information as per the specification section 4.1:
+ * https://developer.arm.com/documentation/den0118/a/
+ *
+ */
+
+#ifndef FWU_METADATA_H
+#define FWU_METADATA_H
+
+#include <stdint.h>
+#include <tools_share/uuid.h>
+
+/* Properties of image in a bank */
+struct fwu_image_properties {
+
+ /* UUID of the image in this bank */
+ uuid_t img_uuid;
+
+ /* [0]: bit describing the image acceptance status –
+ * 1 means the image is accepted
+ * [31:1]: MBZ
+ */
+ uint32_t accepted;
+
+ /* reserved (MBZ) */
+ uint32_t reserved;
+
+} __packed;
+
+/* Image entry information */
+struct fwu_image_entry {
+
+ /* UUID identifying the image type */
+ uuid_t img_type_uuid;
+
+ /* UUID of the storage volume where the image is located */
+ uuid_t location_uuid;
+
+ /* Properties of images with img_type_uuid in the different FW banks */
+ struct fwu_image_properties img_props[NR_OF_FW_BANKS];
+
+} __packed;
+
+/*
+ * FWU metadata filled by the updater and consumed by TF-A for
+ * various purposes as below:
+ * 1. Get active FW bank.
+ * 2. Rollback to previous working FW bank.
+ * 3. Get properties of all images present in all banks.
+ */
+struct fwu_metadata {
+
+ /* Metadata CRC value */
+ uint32_t crc_32;
+
+ /* Metadata version */
+ uint32_t version;
+
+ /* Bank index with which device boots */
+ uint32_t active_index;
+
+ /* Previous bank index with which device booted successfully */
+ uint32_t previous_active_index;
+
+ /* Image entry information */
+ struct fwu_image_entry img_entry[NR_OF_IMAGES_IN_FW_BANK];
+
+} __packed;
+
+#endif /* FWU_METADATA_H */
diff --git a/include/drivers/io/io_mtd.h b/include/drivers/io/io_mtd.h
index 1395ff6..2b5d9b1 100644
--- a/include/drivers/io/io_mtd.h
+++ b/include/drivers/io/io_mtd.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -44,11 +44,22 @@
* Return 0 on success, a negative error code otherwise.
*/
int (*write)(unsigned int offset, uintptr_t buffer, size_t length);
+
+ /*
+ * Look for an offset to be added to the given offset.
+ *
+ * @base: Base address of the area.
+ * @offset: Offset in bytes to start read operation.
+ * @extra_offset: [out] Offset to be added to the previous offset.
+ * Return 0 on success, a negative error code otherwise.
+ */
+ int (*seek)(uintptr_t base, unsigned int offset, size_t *extra_offset);
} io_mtd_ops_t;
typedef struct io_mtd_dev_spec {
unsigned long long device_size;
unsigned int erase_size;
+ size_t offset;
io_mtd_ops_t ops;
} io_mtd_dev_spec_t;
diff --git a/include/drivers/marvell/mochi/cp110_setup.h b/include/drivers/marvell/mochi/cp110_setup.h
index 11dc4e0..4a69257 100644
--- a/include/drivers/marvell/mochi/cp110_setup.h
+++ b/include/drivers/marvell/mochi/cp110_setup.h
@@ -31,6 +31,9 @@
#define MAX_STREAM_ID_PER_CP (0x10)
#define STREAM_ID_BASE (0x40)
+#define MVEBU_SECUREBOOT_CTRL_REG (MVEBU_RFU_BASE + 0x4730)
+#define MVEBU_SECUREBOOT_EN_MASK BIT(0)
+
static inline uint32_t cp110_device_id_get(uintptr_t base)
{
/* Returns:
@@ -50,6 +53,12 @@
MVEBU_DEVICE_REV_OFFSET;
}
+static inline uint32_t is_secure(void)
+{
+ return !!(mmio_read_32(MVEBU_SECUREBOOT_CTRL_REG) &
+ MVEBU_SECUREBOOT_EN_MASK);
+}
+
void cp110_init(uintptr_t cp110_base, uint32_t stream_id);
void cp110_ble_init(uintptr_t cp110_base);
void cp110_amb_init(uintptr_t base);
diff --git a/include/drivers/mmc.h b/include/drivers/mmc.h
index 7611f01..834a80f 100644
--- a/include/drivers/mmc.h
+++ b/include/drivers/mmc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -60,10 +60,16 @@
#define CMD_EXTCSD_PARTITION_CONFIG 179
#define CMD_EXTCSD_BUS_WIDTH 183
#define CMD_EXTCSD_HS_TIMING 185
+#define CMD_EXTCSD_PART_SWITCH_TIME 199
#define CMD_EXTCSD_SEC_CNT 212
+#define EXT_CSD_PART_CONFIG_ACC_MASK GENMASK(2, 0)
#define PART_CFG_BOOT_PARTITION1_ENABLE (U(1) << 3)
-#define PART_CFG_PARTITION1_ACCESS (U(1) << 0)
+#define PART_CFG_BOOT_PARTITION1_ACCESS (U(1) << 0)
+#define PART_CFG_BOOT_PART_EN_MASK GENMASK(5, 3)
+#define PART_CFG_BOOT_PART_EN_SHIFT 3
+#define PART_CFG_CURRENT_BOOT_PARTITION(x) (((x) & PART_CFG_BOOT_PART_EN_MASK) >> \
+ PART_CFG_BOOT_PART_EN_SHIFT)
/* Values in EXT CSD register */
#define MMC_BUS_WIDTH_1 U(0)
@@ -230,6 +236,7 @@
size_t mmc_rpmb_read_blocks(int lba, uintptr_t buf, size_t size);
size_t mmc_rpmb_write_blocks(int lba, const uintptr_t buf, size_t size);
size_t mmc_rpmb_erase_blocks(int lba, size_t size);
+size_t mmc_boot_part_read_blocks(int lba, uintptr_t buf, size_t size);
int mmc_init(const struct mmc_ops *ops_ptr, unsigned int clk,
unsigned int width, unsigned int flags,
struct mmc_device_info *device_info);
diff --git a/include/drivers/nand.h b/include/drivers/nand.h
index 1dbb008..1b78ad4 100644
--- a/include/drivers/nand.h
+++ b/include/drivers/nand.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -46,6 +46,16 @@
size_t *length_read);
/*
+ * Look for an extra offset to be added in case of bad blocks
+ *
+ * @base: Base address of the area
+ * @offset: Byte offset to read from in device
+ * @extra_offset: [out] Extra offset to be added if bad blocks are found
+ * Return: 0 on success, a negative errno on failure
+ */
+int nand_seek_bb(uintptr_t base, unsigned int offset, size_t *extra_offset);
+
+/*
* Get NAND device instance
*
* Return: NAND device instance reference
diff --git a/include/drivers/nxp/auth/csf_hdr_parser/csf_hdr.h b/include/drivers/nxp/auth/csf_hdr_parser/csf_hdr.h
new file mode 100644
index 0000000..ae56d3b
--- /dev/null
+++ b/include/drivers/nxp/auth/csf_hdr_parser/csf_hdr.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright 2017-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef CSF_HDR_H
+#define CSF_HDR_H
+
+#include "caam.h"
+#include "hash.h"
+#include "rsa.h"
+
+/* Barker code size in bytes */
+#define CSF_BARKER_LEN 4 /* barker code length in ESBC uboot client */
+ /* header */
+
+#ifdef CSF_HDR_CH3
+struct csf_hdr {
+ uint8_t barker[CSF_BARKER_LEN]; /* 0x00 Barker code */
+ uint32_t srk_tbl_off; /* 0x04 SRK Table Offset */
+
+ struct {
+ uint8_t num_srk; /* 0x08 No. of keys */
+ uint8_t srk_sel; /* Key no. to be used */
+ uint8_t reserve; /* 0x0a rseerved */
+ } len_kr;
+ uint8_t ie_flag;
+
+ uint32_t uid_flag;
+
+ uint32_t psign; /* 0x10 signature offset */
+ uint32_t sign_len; /* 0x14 length of signature */
+
+ union {
+ struct {
+ uint32_t sg_table_offset; /* 0x18 SG Table Offset */
+ uint32_t sg_entries; /* 0x1c no of entries in SG */
+ } sg_isbc;
+ uint64_t img_addr; /* 64 bit pointer to ESBC Image */
+ };
+
+ union {
+ struct {
+ uint32_t img_size; /* ESBC client img size in bytes */
+ uint32_t ie_key_sel;
+ } img;
+ uint64_t entry_point; /* 0x20-0x24 ESBC entry point */
+ };
+
+ uint32_t fsl_uid_0; /* 0x28 Freescale unique id 0 */
+ uint32_t fsl_uid_1; /* 0x2c Freescale unique id 1 */
+ uint32_t oem_uid_0; /* 0x30 OEM unique id 0 */
+ uint32_t oem_uid_1; /* 0x34 OEM unique id 1 */
+ uint32_t oem_uid_2; /* 0x38 OEM unique id 2 */
+ uint32_t oem_uid_3; /* 0x3c OEM unique id 3 */
+ uint32_t oem_uid_4; /* 0x40 OEM unique id 4 */
+
+ uint32_t reserved[3]; /* 0x44 - 0x4f */
+};
+
+/* Srk table and key revocation check */
+#define UNREVOCABLE_KEY 8
+#define REVOC_KEY_ALIGN 7
+#define MAX_KEY_ENTRIES 8
+
+#else
+
+/* CSF header for Chassis 2 */
+struct csf_hdr {
+ uint8_t barker[CSF_BARKER_LEN]; /* barker code */
+ union {
+ uint32_t pkey; /* public key offset */
+ uint32_t srk_tbl_off;
+ };
+
+ union {
+ uint32_t key_len; /* pub key length in bytes */
+ struct {
+ uint32_t srk_table_flag:8;
+ uint32_t srk_sel:8;
+ uint32_t num_srk:16;
+ } len_kr;
+ };
+
+ uint32_t psign; /* signature offset */
+ uint32_t sign_len; /* length of the signature in bytes */
+
+ /* SG Table used by ISBC header */
+ union {
+ struct {
+ uint32_t sg_table_offset; /* 0x14 SG Table Offset */
+ uint32_t sg_entries; /* no of entries in SG table */
+ } sg_isbc;
+ struct {
+ uint32_t reserved1; /* Reserved field */
+ uint32_t img_size; /* ESBC img size in bytes */
+ } img;
+ };
+
+ uint32_t entry_point; /* ESBC client entry point */
+ uint32_t reserved2; /* Scatter gather flag */
+ uint32_t uid_flag;
+ uint32_t fsl_uid_0;
+ uint32_t oem_uid_0;
+ uint32_t reserved3[2];
+ uint32_t fsl_uid_1;
+ uint32_t oem_uid_1;
+
+ /* The entries below aren't present in ISBC header */
+ uint64_t img_addr; /* 64 bit pointer to ESBC Image */
+ uint32_t ie_flag;
+ uint32_t ie_key_sel;
+};
+
+/* Srk table and key revocation check */
+#define UNREVOCABLE_KEY 4
+#define REVOC_KEY_ALIGN 3
+#define MAX_KEY_ENTRIES 4
+
+#endif
+
+struct srk_table {
+ uint32_t key_len;
+ uint8_t pkey[2 * RSA_4K_KEY_SZ_BYTES];
+};
+
+/*
+ * This struct contains the following fields
+ * length of the segment
+ * Destination Target ID
+ * source address
+ * destination address
+ */
+struct sg_table {
+ uint32_t len; /* Length of Image */
+ uint32_t res1;
+ union {
+ uint64_t src_addr; /* SRC Address of Image */
+ struct {
+ uint32_t src_addr;
+ uint32_t dst_addr;
+ } img;
+ };
+};
+
+int validate_esbc_header(void *img_hdr, void **img_key, uint32_t *key_len,
+ void **img_sign, uint32_t *sign_len,
+ enum sig_alg *algo);
+
+int calc_img_hash(struct csf_hdr *hdr, void *img_addr, uint32_t img_size,
+ uint8_t *img_hash, uint32_t *hash_len);
+
+#endif
diff --git a/include/drivers/nxp/console/plat_console.h b/include/drivers/nxp/console/plat_console.h
new file mode 100644
index 0000000..8b1b23a
--- /dev/null
+++ b/include/drivers/nxp/console/plat_console.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PLAT_CONSOLE_H
+#define PLAT_CONSOLE_H
+
+#include <stdint.h>
+#include <drivers/console.h>
+
+#if (NXP_CONSOLE == NS16550)
+/*
+ * NXP specific UART - 16550 configuration
+ *
+ * Initialize a NXP 16550 console instance and register it with the console
+ * framework. The |console| pointer must point to storage that will be valid
+ * for the lifetime of the console, such as a global or static local variable.
+ * Its contents will be reinitialized from scratch.
+ * When |clock| has a value of 0, the UART will *not* be initialised. This
+ * means the UART should already be enabled and the baudrate and clock setup
+ * should have been done already, either by platform specific code or by
+ * previous firmware stages. The |baud| parameter will be ignored in this
+ * case as well.
+ */
+int nxp_console_16550_register(uintptr_t baseaddr, uint32_t clock,
+ uint32_t baud, console_t *console);
+#endif
+/*
+ * Function to initialize platform's console
+ * and register with console framework
+ */
+void plat_console_init(uintptr_t nxp_console_addr, uint32_t uart_clk_div,
+ uint32_t baud);
+
+#endif
diff --git a/include/drivers/nxp/crypto/caam/caam.h b/include/drivers/nxp/crypto/caam/caam.h
new file mode 100644
index 0000000..4984b54
--- /dev/null
+++ b/include/drivers/nxp/crypto/caam/caam.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2017-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef CAAM_H
+#define CAAM_H
+
+#include "caam_io.h"
+#include "sec_jr_driver.h"
+
+
+/* Job ring 3 is reserved for usage by sec firmware */
+#define DEFAULT_JR 3
+
+#if defined(CONFIG_CHASSIS_3_2) || defined(CONFIG_CHASSIS_2)
+#define CAAM_JR0_OFFSET 0x10000
+#define CAAM_JR1_OFFSET 0x20000
+#define CAAM_JR2_OFFSET 0x30000
+#define CAAM_JR3_OFFSET 0x40000
+#endif
+
+enum sig_alg {
+ RSA,
+ ECC
+};
+
+/* This function does basic SEC Initialization */
+int sec_init(uintptr_t nxp_caam_addr);
+int config_sec_block(void);
+uintptr_t get_caam_addr(void);
+
+/* This function is used to submit jobs to JR */
+int run_descriptor_jr(struct job_descriptor *desc);
+
+/* This function is used to instatiate the HW RNG is already not instantiated */
+int hw_rng_instantiate(void);
+
+/* This function is used to return random bytes of byte_len from HW RNG */
+int get_rand_bytes_hw(uint8_t *bytes, int byte_len);
+
+/* This function is used to set the hw unique key from HW CAAM */
+int get_hw_unq_key_blob_hw(uint8_t *hw_key, int size);
+
+/* This function is used to fetch random number from
+ * CAAM of length either of 4 bytes or 8 bytes depending
+ * rngWidth value.
+ */
+unsigned long long get_random(int rngWidth);
+
+#endif /* CAAM_H */
diff --git a/include/drivers/nxp/crypto/caam/caam_io.h b/include/drivers/nxp/crypto/caam/caam_io.h
new file mode 100644
index 0000000..b68f836
--- /dev/null
+++ b/include/drivers/nxp/crypto/caam/caam_io.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef CAAM_IO_H
+#define CAAM_IO_H
+
+#include <endian.h>
+#include <lib/mmio.h>
+
+typedef unsigned long long phys_addr_t;
+typedef unsigned long long phys_size_t;
+
+/* Return higher 32 bits of physical address */
+#define PHYS_ADDR_HI(phys_addr) \
+ (uint32_t)(((uint64_t)phys_addr) >> 32)
+
+/* Return lower 32 bits of physical address */
+#define PHYS_ADDR_LO(phys_addr) \
+ (uint32_t)(((uint64_t)phys_addr) & 0xFFFFFFFF)
+
+#ifdef NXP_SEC_BE
+#define sec_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
+#define sec_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
+#define sec_in64(addr) ( \
+ ((uint64_t)sec_in32((uintptr_t)(addr)) << 32) | \
+ (sec_in32(((uintptr_t)(addr)) + 4)))
+#define sec_out64(addr, val) ({ \
+ sec_out32(((uintptr_t)(addr)), (uint32_t)((val) >> 32)); \
+ sec_out32(((uintptr_t)(addr)) + 4, (uint32_t)(val)); })
+#elif defined(NXP_SEC_LE)
+#define sec_in32(a) mmio_read_32((uintptr_t)(a))
+#define sec_out32(a, v) mmio_write_32((uintptr_t)(a), (v))
+#define sec_in64(addr) ( \
+ ((uint64_t)sec_in32((uintptr_t)(addr) + 4) << 32) | \
+ (sec_in32((uintptr_t)(addr))))
+#define sec_out64(addr, val) ({ \
+ sec_out32(((uintptr_t)(addr)) + 4, (uint32_t)((val) >> 32)); \
+ sec_out32(((uintptr_t)(addr)), (uint32_t)(val)); })
+#else
+#error Please define CCSR SEC register endianness
+#endif
+
+static inline void *ptov(phys_addr_t *ptr)
+{
+ return (void *)ptr;
+}
+
+static inline phys_addr_t *vtop(void *ptr)
+{
+ return (phys_addr_t *)ptr;
+}
+#endif /* CAAM_IO_H */
diff --git a/include/drivers/nxp/crypto/caam/hash.h b/include/drivers/nxp/crypto/caam/hash.h
new file mode 100644
index 0000000..9136dca
--- /dev/null
+++ b/include/drivers/nxp/crypto/caam/hash.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2017-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __HASH_H__
+#define __HASH_H__
+
+#include <stdbool.h>
+
+/* List of hash algorithms */
+enum hash_algo {
+ SHA1 = 0,
+ SHA256
+};
+
+/* number of bytes in the SHA256-256 digest */
+#define SHA256_DIGEST_SIZE 32
+
+/*
+ * number of words in the digest - Digest is kept internally
+ * as 8 32-bit words
+ */
+#define _SHA256_DIGEST_LENGTH 8
+
+/*
+ * block length - A block, treated as a sequence of
+ * 32-bit words
+ */
+#define SHA256_BLOCK_LENGTH 16
+
+/* number of bytes in the block */
+#define SHA256_DATA_SIZE 64
+
+#define MAX_SG 12
+
+struct sg_entry {
+#if defined(NXP_SEC_LE)
+ uint32_t addr_lo; /* Memory Address - lo */
+ uint32_t addr_hi; /* Memory Address of start of buffer - hi */
+#else
+ uint32_t addr_hi; /* Memory Address of start of buffer - hi */
+ uint32_t addr_lo; /* Memory Address - lo */
+#endif
+
+ uint32_t len_flag; /* Length of the data in the frame */
+#define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF
+#define SG_ENTRY_EXTENSION_BIT 0x80000000
+#define SG_ENTRY_FINAL_BIT 0x40000000
+ uint32_t bpid_offset;
+#define SG_ENTRY_BPID_MASK 0x00FF0000
+#define SG_ENTRY_BPID_SHIFT 16
+#define SG_ENTRY_OFFSET_MASK 0x00001FFF
+#define SG_ENTRY_OFFSET_SHIFT 0
+};
+
+/*
+ * SHA256-256 context
+ * contain the following fields
+ * State
+ * count low
+ * count high
+ * block data buffer
+ * index to the buffer
+ */
+struct hash_ctx {
+ struct sg_entry sg_tbl[MAX_SG];
+ uint32_t hash_desc[64];
+ uint8_t hash[SHA256_DIGEST_SIZE];
+ uint32_t sg_num;
+ uint32_t len;
+ uint8_t *data;
+ enum hash_algo algo;
+ bool active;
+};
+
+int hash_init(enum hash_algo algo, void **ctx);
+int hash_update(enum hash_algo algo, void *context, void *data_ptr,
+ unsigned int data_len);
+int hash_final(enum hash_algo algo, void *context, void *hash_ptr,
+ unsigned int hash_len);
+
+#endif
diff --git a/include/drivers/nxp/crypto/caam/jobdesc.h b/include/drivers/nxp/crypto/caam/jobdesc.h
new file mode 100644
index 0000000..efef228
--- /dev/null
+++ b/include/drivers/nxp/crypto/caam/jobdesc.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2017-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __JOBDESC_H
+#define __JOBDESC_H
+
+#include <rsa.h>
+
+#define DESC_LEN_MASK 0x7f
+#define DESC_START_SHIFT 16
+
+#define KEY_BLOB_SIZE 32
+#define MAC_SIZE 16
+
+#define KEY_IDNFR_SZ_BYTES 16
+#define CLASS_SHIFT 25
+#define CLASS_2 (0x02 << CLASS_SHIFT)
+
+#define CMD_SHIFT 27
+#define CMD_OPERATION (U(0x10) << CMD_SHIFT)
+
+#define OP_TYPE_SHIFT 24
+#define OP_TYPE_ENCAP_PROTOCOL (0x07 << OP_TYPE_SHIFT)
+
+/* Assuming OP_TYPE = OP_TYPE_UNI_PROTOCOL */
+#define OP_PCLID_SHIFT 16
+#define OP_PCLID_BLOB (0x0d << OP_PCLID_SHIFT)
+
+#define BLOB_PROTO_INFO 0x00000002
+
+uint32_t desc_length(uint32_t *desc);
+
+int cnstr_rng_jobdesc(uint32_t *desc, uint32_t state_handle,
+ uint32_t *add_inp, uint32_t add_ip_len,
+ uint8_t *out_data, uint32_t len);
+
+int cnstr_rng_instantiate_jobdesc(uint32_t *desc);
+
+/* Construct descriptor to generate hw key blob */
+int cnstr_hw_encap_blob_jobdesc(uint32_t *desc,
+ uint8_t *key_idnfr, uint32_t key_sz,
+ uint32_t key_class, uint8_t *plain_txt,
+ uint32_t in_sz, uint8_t *enc_blob,
+ uint32_t out_sz, uint32_t operation);
+
+void cnstr_hash_jobdesc(uint32_t *desc, uint8_t *msg, uint32_t msgsz,
+ uint8_t *digest);
+
+void cnstr_jobdesc_pkha_rsaexp(uint32_t *desc,
+ struct pk_in_params *pkin, uint8_t *out,
+ uint32_t out_siz);
+#endif
diff --git a/include/drivers/nxp/crypto/caam/jr_driver_config.h b/include/drivers/nxp/crypto/caam/jr_driver_config.h
new file mode 100644
index 0000000..1b3c447
--- /dev/null
+++ b/include/drivers/nxp/crypto/caam/jr_driver_config.h
@@ -0,0 +1,205 @@
+/*
+ * Copyright 2017-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _JR_DRIVER_CONFIG_H_
+#define _JR_DRIVER_CONFIG_H_
+
+/* Helper defines */
+
+ /* Define used for setting a flag on */
+#define ON 1
+ /* Define used for setting a flag off */
+#define OFF 0
+
+ /* SEC is configured to start work in polling mode, */
+#define SEC_STARTUP_POLLING_MODE 0
+/*
+ * SEC is configured to start work in interrupt mode,
+ * when configured for NAPI notification style.
+ */
+#define SEC_STARTUP_INTERRUPT_MODE 1
+
+/*
+ * SEC driver will use ONLY interrupts to receive notifications
+ * for processed packets from SEC engine hardware.
+ */
+#define SEC_NOTIFICATION_TYPE_IRQ 1
+/*
+ * SEC driver will use ONLY polling to receive notifications
+ * for processed packets from SEC engine hardware.
+ */
+#define SEC_NOTIFICATION_TYPE_POLL 2
+
+/*
+ * Determines how SEC user space driver will receive notifications
+ * for processed packets from SEC engine.
+ * Valid values are: #SEC_NOTIFICATION_TYPE_POLL, #SEC_NOTIFICATION_TYPE_IRQ
+ */
+#define SEC_NOTIFICATION_TYPE SEC_NOTIFICATION_TYPE_POLL
+
+ /* Maximum number of job rings supported by SEC hardware */
+#define MAX_SEC_JOB_RINGS 1
+
+/*
+ * Size of cryptographic context that is used directly in communicating
+ * with SEC device.
+ * SEC device works only with physical addresses. This is the maximum size
+ * for a SEC descriptor ( = 64 words).
+ */
+
+#define SEC_CRYPTO_DESCRIPTOR_SIZE 256
+
+/*
+ * Size of job descriptor submitted to SEC device for each packet to be
+ * processed.
+ * Job descriptor contains 3 DMA address pointers:
+ * - to shared descriptor, to input buffer and to output buffer.
+ * The job descriptor contains other SEC specific commands as well:
+ * - HEADER command, SEQ IN PTR command SEQ OUT PTR command and opaque
+ * data, each measuring 4 bytes.
+ * Job descriptor size, depending on physical address representation:
+ * - 32 bit - size is 28 bytes - cacheline-aligned size is 64 bytes
+ * - 36 bit - size is 40 bytes - cacheline-aligned size is 64 bytes
+ * @note: Job descriptor must be cacheline-aligned to ensure efficient memory
+ * access.
+ * @note: If other format is used for job descriptor, then the size must be
+ * revised.
+ */
+
+#define SEC_JOB_DESCRIPTOR_SIZE 64
+
+/*
+ * Size of one entry in the input ring of a job ring.
+ * Input ring contains pointers to job descriptors.
+ * The memory used for an input ring and output ring must be physically
+ * contiguous.
+ */
+
+#define SEC_JOB_INPUT_RING_ENTRY_SIZE sizeof(phys_addr_t)
+
+/*
+ * Size of one entry in the output ring of a job ring.
+ * Output ring entry is a pointer to a job descriptor followed by a 4 byte
+ * status word.
+ * The memory used for an input ring and output ring must be physically
+ * contiguous.
+ * @note If desired to use also the optional SEQ OUT indication in output
+ * ring entries, then 4 more bytes must be added to the size.
+ */
+
+#define SEC_JOB_OUTPUT_RING_ENTRY_SIZE (SEC_JOB_INPUT_RING_ENTRY_SIZE + 4)
+
+ /* DMA memory required for an input ring of a job ring. */
+#define SEC_DMA_MEM_INPUT_RING_SIZE \
+ ((SEC_JOB_INPUT_RING_ENTRY_SIZE) * (SEC_JOB_RING_SIZE))
+
+/*
+ * DMA memory required for an output ring of a job ring.
+ * Required extra 4 byte for status word per each entry.
+ */
+#define SEC_DMA_MEM_OUTPUT_RING_SIZE \
+ ((SEC_JOB_OUTPUT_RING_ENTRY_SIZE) * (SEC_JOB_RING_SIZE))
+
+ /* DMA memory required for descriptors of a job ring. */
+#define SEC_DMA_MEM_DESCRIPTORS \
+ ((SEC_CRYPTO_DESCRIPTOR_SIZE)*(SEC_JOB_RING_SIZE))
+
+ /* DMA memory required for a job ring, including both input output rings. */
+#define SEC_DMA_MEM_JOB_RING_SIZE \
+ ((SEC_DMA_MEM_INPUT_RING_SIZE) + \
+ (SEC_DMA_MEM_OUTPUT_RING_SIZE))
+
+/*
+ * When calling sec_init() UA will provide an area of virtual memory
+ * of size #SEC_DMA_MEMORY_SIZE to be used internally by the driver
+ * to allocate data (like SEC descriptors) that needs to be passed to
+ * SEC device in physical addressing and later on retrieved from SEC device.
+ * At initialization the UA provides specialized ptov/vtop functions/macros to
+ * translate addresses allocated from this memory area.
+ */
+#define SEC_DMA_MEMORY_SIZE \
+ ((SEC_DMA_MEM_JOB_RING_SIZE) * (MAX_SEC_JOB_RINGS))
+
+/*
+ * SEC DEVICE related configuration.
+
+ * Enable/Disable logging support at compile time.
+ * Valid values:
+ * ON - enable logging
+ * OFF - disable logging
+ * The messages are logged at stdout.
+ */
+
+#define SEC_DRIVER_LOGGING OFF
+
+/*
+ * Configure logging level at compile time.
+ * Valid values:
+ * SEC_DRIVER_LOG_ERROR - log only errors
+ * SEC_DRIVER_LOG_INFO - log errors and info messages
+ * SEC_DRIVER_LOG_DEBUG - log errors, info and debug messages
+ */
+
+#define SEC_DRIVER_LOGGING_LEVEL SEC_DRIVER_LOG_DEBUG
+
+/*
+ * SEC JOB RING related configuration.
+
+ * Configure the size of the JOB RING.
+ * The maximum size of the ring is hardware limited to 1024.
+ * However the number of packets in flight in a time interval of
+ * 1ms can be calculated
+ * from the traffic rate (Mbps) and packet size.
+ * Here it was considered a packet size of 40 bytes.
+ * @note Round up to nearest power of 2 for optimized update
+ * of producer/consumer indexes of each job ring
+ * \todo Should set to 750, according to the calculation above, but
+ * the JR size must be power of 2, thus the next closest value must
+ * be chosen (i.e. 512 since 1024 is not available)
+ * For firmware choose this to be 16
+ */
+
+#define SEC_JOB_RING_SIZE 16
+
+/*
+ * Interrupt coalescing related configuration.
+ * NOTE: SEC hardware enabled interrupt
+ * coalescing is not supported on SEC version 3.1!
+ * SEC version 4.4 has support for interrupt
+ * coalescing.
+ */
+
+#if SEC_NOTIFICATION_TYPE != SEC_NOTIFICATION_TYPE_POLL
+
+#define SEC_INT_COALESCING_ENABLE ON
+/*
+ * Interrupt Coalescing Descriptor Count Threshold.
+ * While interrupt coalescing is enabled (ICEN=1), this value determines
+ * how many Descriptors are completed before raising an interrupt.
+ * Valid values for this field are from 0 to 255.
+ * Note that a value of 1 functionally defeats the advantages of interrupt
+ * coalescing since the threshold value is reached each time that a
+ * Job Descriptor is completed. A value of 0 is treated in the same
+ * manner as a value of 1.
+ *
+ */
+#define SEC_INTERRUPT_COALESCING_DESCRIPTOR_COUNT_THRESH 10
+
+/*
+ * Interrupt Coalescing Timer Threshold.
+ * While interrupt coalescing is enabled (ICEN=1), this value determines the
+ * maximum amount of time after processing a Descriptor before raising an
+ * interrupt.
+ * The threshold value is represented in units equal to 64 CAAM interface
+ * clocks. Valid values for this field are from 1 to 65535.
+ * A value of 0 results in behavior identical to that when interrupt
+ * coalescing is disabled.
+ */
+#define SEC_INTERRUPT_COALESCING_TIMER_THRESH 100
+#endif /* SEC_NOTIFICATION_TYPE_POLL */
+
+#endif /* _JR_DRIVER_CONFIG_H_ */
diff --git a/include/drivers/nxp/crypto/caam/rsa.h b/include/drivers/nxp/crypto/caam/rsa.h
new file mode 100644
index 0000000..dd9ecdc
--- /dev/null
+++ b/include/drivers/nxp/crypto/caam/rsa.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2017-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _RSA_H__
+#define _RSA_H__
+
+/* RSA key size defines */
+#define RSA_4K_KEY_SZ 4096
+#define RSA_4K_KEY_SZ_BYTES (RSA_4K_KEY_SZ/8)
+#define RSA_2K_KEY_SZ 2048
+#define RSA_2K_KEY_SZ_BYTES (RSA_2K_KEY_SZ/8)
+#define RSA_1K_KEY_SZ 1024
+#define RSA_1K_KEY_SZ_BYTES (RSA_1K_KEY_SZ/8)
+
+#define SHA256_BYTES (256/8)
+
+struct pk_in_params {
+ uint8_t *e;
+ uint32_t e_siz;
+ uint8_t *n;
+ uint32_t n_siz;
+ uint8_t *a;
+ uint32_t a_siz;
+ uint8_t *b;
+ uint32_t b_siz;
+};
+
+struct rsa_context {
+ struct pk_in_params pkin;
+};
+
+int rsa_verify_signature(void *hash_ptr, unsigned int hash_len,
+ void *sig_ptr, unsigned int sig_len,
+ void *pk_ptr, unsigned int pk_len);
+
+#endif
diff --git a/include/drivers/nxp/crypto/caam/sec_hw_specific.h b/include/drivers/nxp/crypto/caam/sec_hw_specific.h
new file mode 100644
index 0000000..a4fc022
--- /dev/null
+++ b/include/drivers/nxp/crypto/caam/sec_hw_specific.h
@@ -0,0 +1,506 @@
+/*
+ * Copyright 2017-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _SEC_HW_SPECIFIC_H_
+#define _SEC_HW_SPECIFIC_H_
+
+#include "caam.h"
+#include "sec_jr_driver.h"
+
+ /* DEFINES AND MACROS */
+
+/* Used to retry resetting a job ring in SEC hardware. */
+#define SEC_TIMEOUT 100000
+
+/*
+ * Offset to the registers of a job ring.
+ *Is different for each job ring.
+ */
+#define CHAN_BASE(jr) ((phys_addr_t)(jr)->register_base_addr)
+
+#define unlikely(x) __builtin_expect(!!(x), 0)
+
+#define SEC_JOB_RING_IS_FULL(pi, ci, ring_max_size, ring_threshold) \
+ ((((pi) + 1 + ((ring_max_size) - (ring_threshold))) & \
+ (ring_max_size - 1)) == ((ci)))
+
+#define SEC_CIRCULAR_COUNTER(x, max) (((x) + 1) & (max - 1))
+
+ /* Struct representing various job ring registers */
+struct jobring_regs {
+#ifdef NXP_SEC_BE
+ unsigned int irba_h;
+ unsigned int irba_l;
+#else
+ unsigned int irba_l;
+ unsigned int irba_h;
+#endif
+ unsigned int rsvd1;
+ unsigned int irs;
+ unsigned int rsvd2;
+ unsigned int irsa;
+ unsigned int rsvd3;
+ unsigned int irja;
+#ifdef NXP_SEC_BE
+ unsigned int orba_h;
+ unsigned int orba_l;
+#else
+ unsigned int orba_l;
+ unsigned int orba_h;
+#endif
+ unsigned int rsvd4;
+ unsigned int ors;
+ unsigned int rsvd5;
+ unsigned int orjr;
+ unsigned int rsvd6;
+ unsigned int orsf;
+ unsigned int rsvd7;
+ unsigned int jrsta;
+ unsigned int rsvd8;
+ unsigned int jrint;
+ unsigned int jrcfg0;
+ unsigned int jrcfg1;
+ unsigned int rsvd9;
+ unsigned int irri;
+ unsigned int rsvd10;
+ unsigned int orwi;
+ unsigned int rsvd11;
+ unsigned int jrcr;
+};
+
+ /* Offsets representing common SEC Registers */
+#define SEC_REG_MCFGR_OFFSET 0x0004
+#define SEC_REG_SCFGR_OFFSET 0x000C
+#define SEC_REG_JR0ICIDR_MS_OFFSET 0x0010
+#define SEC_REG_JR0ICIDR_LS_OFFSET 0x0014
+#define SEC_REG_JR1ICIDR_MS_OFFSET 0x0018
+#define SEC_REG_JR1ICIDR_LS_OFFSET 0x001C
+#define SEC_REG_JR2ICIDR_MS_OFFSET 0x0020
+#define SEC_REG_JR2ICIDR_LS_OFFSET 0x0024
+#define SEC_REG_JR3ICIDR_MS_OFFSET 0x0028
+#define SEC_REG_JR3ICIDR_LS_OFFSET 0x002C
+#define SEC_REG_JRSTARTR_OFFSET 0x005C
+#define SEC_REG_CTPR_MS_OFFSET 0x0FA8
+
+ /* Offsets representing various RNG registers */
+#define RNG_REG_RTMCTL_OFFSET 0x0600
+#define RNG_REG_RTSDCTL_OFFSET 0x0610
+#define RNG_REG_RTFRQMIN_OFFSET 0x0618
+#define RNG_REG_RTFRQMAX_OFFSET 0x061C
+#define RNG_REG_RDSTA_OFFSET 0x06C0
+#define ALG_AAI_SH_SHIFT 4
+
+ /* SEC Registers Bitmasks */
+#define MCFGR_PS_SHIFT 16
+#define MCFGR_AWCACHE_SHIFT 8
+#define MCFGR_AWCACHE_MASK (0xF << MCFGR_AWCACHE_SHIFT)
+#define MCFGR_ARCACHE_SHIFT 12
+#define MCFGR_ARCACHE_MASK (0xF << MCFGR_ARCACHE_SHIFT)
+
+#define SCFGR_RNGSH0 0x00000200
+#define SCFGR_VIRT_EN 0x00008000
+
+#define JRICID_MS_LICID 0x80000000
+#define JRICID_MS_LAMTD 0x00020000
+#define JRICID_MS_AMTDT 0x00010000
+#define JRICID_MS_TZ 0x00008000
+#define JRICID_LS_SDID_MASK 0x00000FFF
+#define JRICID_LS_NSEQID_MASK 0x0FFF0000
+#define JRICID_LS_NSEQID_SHIFT 16
+#define JRICID_LS_SEQID_MASK 0x00000FFF
+
+#define JRSTARTR_STARTJR0 0x00000001
+#define JRSTARTR_STARTJR1 0x00000002
+#define JRSTARTR_STARTJR2 0x00000004
+#define JRSTARTR_STARTJR3 0x00000008
+
+#define CTPR_VIRT_EN_POR 0x00000002
+#define CTPR_VIRT_EN_INC 0x00000001
+
+ /* RNG RDSTA bitmask */
+#define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001
+#define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */
+ /* use von Neumann data in both entropy shifter and statistical checker */
+#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0
+ /* use raw data in both entropy shifter and statistical checker */
+#define RTMCTL_SAMP_MODE_RAW_ES_SC 1
+ /* use von Neumann data in entropy shifter, raw data in statistical checker */
+#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2
+ /* invalid combination */
+#define RTMCTL_SAMP_MODE_INVALID 3
+#define RTSDCTL_ENT_DLY_MIN 3200
+#define RTSDCTL_ENT_DLY_MAX 12800
+#define RTSDCTL_ENT_DLY_SHIFT 16
+#define RTSDCTL_ENT_DLY_MASK (U(0xffff) << RTSDCTL_ENT_DLY_SHIFT)
+#define RTFRQMAX_DISABLE (1 << 20)
+
+ /* Constants for error handling on job ring */
+#define JR_REG_JRINT_ERR_TYPE_SHIFT 8
+#define JR_REG_JRINT_ERR_ORWI_SHIFT 16
+#define JR_REG_JRINIT_JRE_SHIFT 1
+
+#define JRINT_JRE (1 << JR_REG_JRINIT_JRE_SHIFT)
+#define JRINT_ERR_WRITE_STATUS (1 << JR_REG_JRINT_ERR_TYPE_SHIFT)
+#define JRINT_ERR_BAD_INPUT_BASE (3 << JR_REG_JRINT_ERR_TYPE_SHIFT)
+#define JRINT_ERR_BAD_OUTPUT_BASE (4 << JR_REG_JRINT_ERR_TYPE_SHIFT)
+#define JRINT_ERR_WRITE_2_IRBA (5 << JR_REG_JRINT_ERR_TYPE_SHIFT)
+#define JRINT_ERR_WRITE_2_ORBA (6 << JR_REG_JRINT_ERR_TYPE_SHIFT)
+#define JRINT_ERR_RES_B4_HALT (7 << JR_REG_JRINT_ERR_TYPE_SHIFT)
+#define JRINT_ERR_REM_TOO_MANY (8 << JR_REG_JRINT_ERR_TYPE_SHIFT)
+#define JRINT_ERR_ADD_TOO_MANY (9 << JR_REG_JRINT_ERR_TYPE_SHIFT)
+#define JRINT_ERR_HALT_MASK 0x0C
+#define JRINT_ERR_HALT_INPROGRESS 0x04
+#define JRINT_ERR_HALT_COMPLETE 0x08
+
+#define JR_REG_JRCR_VAL_RESET 0x00000001
+
+#define JR_REG_JRCFG_LO_ICTT_SHIFT 0x10
+#define JR_REG_JRCFG_LO_ICDCT_SHIFT 0x08
+#define JR_REG_JRCFG_LO_ICEN_EN 0x02
+#define JR_REG_JRCFG_LO_IMSK_EN 0x01
+
+ /* Constants for Descriptor Processing errors */
+#define SEC_HW_ERR_SSRC_NO_SRC 0x00
+#define SEC_HW_ERR_SSRC_CCB_ERR 0x02
+#define SEC_HW_ERR_SSRC_JMP_HALT_U 0x03
+#define SEC_HW_ERR_SSRC_DECO 0x04
+#define SEC_HW_ERR_SSRC_JR 0x06
+#define SEC_HW_ERR_SSRC_JMP_HALT_COND 0x07
+
+#define SEC_HW_ERR_DECO_HFN_THRESHOLD 0xF1
+#define SEC_HW_ERR_CCB_ICV_CHECK_FAIL 0x0A
+
+ /* Macros for extracting error codes for the job ring */
+
+#define JR_REG_JRINT_ERR_TYPE_EXTRACT(value) \
+ ((value) & 0x00000F00)
+
+#define JR_REG_JRINT_ERR_ORWI_EXTRACT(value) \
+ (((value) & 0x3FFF0000) >> \
+ JR_REG_JRINT_ERR_ORWI_SHIFT)
+
+#define JR_REG_JRINT_JRE_EXTRACT(value) \
+ ((value) & JRINT_JRE)
+
+ /* Macros for manipulating JR registers */
+typedef union {
+ uint64_t m_whole;
+ struct {
+#ifdef NXP_SEC_BE
+ uint32_t high;
+ uint32_t low;
+#else
+ uint32_t low;
+ uint32_t high;
+#endif
+ } m_halves;
+} ptr_addr_t;
+
+#if defined(CONFIG_PHYS_64BIT)
+#define sec_read_addr(a) sec_in64((a))
+#define sec_write_addr(a, v) sec_out64((a), (v))
+#else
+#define sec_read_addr(a) sec_in32((a))
+#define sec_write_addr(a, v) sec_out32((a), (v))
+#endif
+
+#define JR_REG(name, jr) (CHAN_BASE(jr) + JR_REG_##name##_OFFSET)
+#define JR_REG_LO(name, jr) (CHAN_BASE(jr) + JR_REG_##name##_OFFSET_LO)
+
+#define GET_JR_REG(name, jr) (sec_in32(JR_REG(name, (jr))))
+#define GET_JR_REG_LO(name, jr) (sec_in32(JR_REG_LO(name, (jr))))
+
+#define SET_JR_REG(name, jr, val) \
+ (sec_out32(JR_REG(name, (jr)), (val)))
+
+#define SET_JR_REG_LO(name, jr, val) \
+ (sec_out32(JR_REG_LO(name, (jr)), (val)))
+
+ /* STRUCTURES AND OTHER TYPEDEFS */
+ /* Lists the possible states for a job ring. */
+typedef enum sec_job_ring_state_e {
+ SEC_JOB_RING_STATE_STARTED, /* Job ring is initialized */
+ SEC_JOB_RING_STATE_RESET, /* Job ring reset is in progres */
+} sec_job_ring_state_t;
+
+struct sec_job_ring_t {
+ /*
+ * Consumer index for job ring (jobs array).
+ * @note: cidx and pidx are accessed from
+ * different threads.
+ * Place the cidx and pidx inside the structure
+ * so that they lay on different cachelines, to
+ * avoid false sharing between threads when the
+ * threads run on different cores!
+ */
+ uint32_t cidx;
+
+ /* Producer index for job ring (jobs array) */
+ uint32_t pidx;
+
+ /* Ring of input descriptors. Size of array is power of 2 to allow
+ * fast update of producer/consumer indexes with bitwise operations.
+ */
+ phys_addr_t *input_ring;
+
+ /* Ring of output descriptors. */
+ struct sec_outring_entry *output_ring;
+
+ /* The file descriptor used for polling for interrupts notifications */
+ uint32_t irq_fd;
+
+ /* Model used by SEC Driver to receive notifications from SEC.
+ * Can be either of the three:
+ * #SEC_NOTIFICATION_TYPE_IRQ or
+ * #SEC_NOTIFICATION_TYPE_POLL
+ */
+ uint32_t jr_mode;
+ /* Base address for SEC's register memory for this job ring. */
+ void *register_base_addr;
+ /* notifies if coelescing is enabled for the job ring */
+ uint8_t coalescing_en;
+ /* The state of this job ring */
+ sec_job_ring_state_t jr_state;
+};
+
+ /* Forward structure declaration */
+typedef struct sec_job_ring_t sec_job_ring_t;
+
+struct sec_outring_entry {
+ phys_addr_t desc; /* Pointer to completed descriptor */
+ uint32_t status; /* Status for completed descriptor */
+} __packed;
+
+ /* Lists the states possible for the SEC user space driver. */
+typedef enum sec_driver_state_e {
+ SEC_DRIVER_STATE_IDLE, /*< Driver not initialized */
+ SEC_DRIVER_STATE_STARTED, /*< Driver initialized and */
+ SEC_DRIVER_STATE_RELEASE, /*< Driver release is in progress */
+} sec_driver_state_t;
+
+ /* Union describing the possible error codes that */
+ /* can be set in the descriptor status word */
+
+union hw_error_code {
+ uint32_t error;
+ union {
+ struct {
+ uint32_t ssrc:4;
+ uint32_t ssed_val:28;
+ } __packed value;
+ struct {
+ uint32_t ssrc:4;
+ uint32_t res:28;
+ } __packed no_status_src;
+ struct {
+ uint32_t ssrc:4;
+ uint32_t jmp:1;
+ uint32_t res:11;
+ uint32_t desc_idx:8;
+ uint32_t cha_id:4;
+ uint32_t err_id:4;
+ } __packed ccb_status_src;
+ struct {
+ uint32_t ssrc:4;
+ uint32_t jmp:1;
+ uint32_t res:11;
+ uint32_t desc_idx:8;
+ uint32_t offset:8;
+ } __packed jmp_halt_user_src;
+ struct {
+ uint32_t ssrc:4;
+ uint32_t jmp:1;
+ uint32_t res:11;
+ uint32_t desc_idx:8;
+ uint32_t desc_err:8;
+ } __packed deco_src;
+ struct {
+ uint32_t ssrc:4;
+ uint32_t res:17;
+ uint32_t naddr:3;
+ uint32_t desc_err:8;
+ } __packed jr_src;
+ struct {
+ uint32_t ssrc:4;
+ uint32_t jmp:1;
+ uint32_t res:11;
+ uint32_t desc_idx:8;
+ uint32_t cond:8;
+ } __packed jmp_halt_cond_src;
+ } __packed error_desc;
+} __packed;
+
+ /* FUNCTION PROTOTYPES */
+
+/*
+ * @brief Initialize a job ring/channel in SEC device.
+ * Write configuration register/s to properly initialize a job ring.
+ *
+ * @param [in] job_ring The job ring
+ *
+ * @retval 0 for success
+ * @retval other for error
+ */
+int hw_reset_job_ring(sec_job_ring_t *job_ring);
+
+/*
+ * @brief Reset a job ring/channel in SEC device.
+ * Write configuration register/s to reset a job ring.
+ *
+ * @param [in] job_ring The job ring
+ *
+ * @retval 0 for success
+ * @retval -1 in case job ring reset failed
+ */
+int hw_shutdown_job_ring(sec_job_ring_t *job_ring);
+
+/*
+ * @brief Handle a job ring/channel error in SEC device.
+ * Identify the error type and clear error bits if required.
+ *
+ * @param [in] job_ring The job ring
+ * @param [in] sec_error_code error code as first read from SEC engine
+ */
+
+void hw_handle_job_ring_error(sec_job_ring_t *job_ring,
+ uint32_t sec_error_code);
+/*
+ * @brief Handle a job ring error in the device.
+ * Identify the error type and printout a explanatory
+ * messages.
+ *
+ * @param [in] job_ring The job ring
+ *
+ */
+
+int hw_job_ring_error(sec_job_ring_t *job_ring);
+
+/* @brief Set interrupt coalescing parameters on the Job Ring.
+ * @param [in] job_ring The job ring
+ * @param [in] irq_coalesing_timer
+ * Interrupt coalescing timer threshold.
+ * This value determines the maximum
+ * amount of time after processing a descriptor
+ * before raising an interrupt.
+ * @param [in] irq_coalescing_count
+ * Interrupt coalescing count threshold.
+ * This value determines how many descriptors
+ * are completed before raising an interrupt.
+ */
+
+int hw_job_ring_set_coalescing_param(sec_job_ring_t *job_ring,
+ uint16_t irq_coalescing_timer,
+ uint8_t irq_coalescing_count);
+
+/* @brief Enable interrupt coalescing on a job ring
+ * @param [in] job_ring The job ring
+ */
+
+int hw_job_ring_enable_coalescing(sec_job_ring_t *job_ring);
+
+/*
+ * @brief Disable interrupt coalescing on a job ring
+ * @param [in] job_ring The job ring
+ */
+
+int hw_job_ring_disable_coalescing(sec_job_ring_t *job_ring);
+
+/*
+ * @brief Poll the HW for already processed jobs in the JR
+ * and notify the available jobs to UA.
+ *
+ * @param [in] job_ring The job ring to poll.
+ * @param [in] limit The maximum number of jobs to notify.
+ * If set to negative value, all available
+ * jobs are notified.
+ *
+ * @retval >=0 for No of jobs notified to UA.
+ * @retval -1 for error
+ */
+
+int hw_poll_job_ring(struct sec_job_ring_t *job_ring, int32_t limit);
+
+/* @brief Poll the HW for already processed jobs in the JR
+ * and silently discard the available jobs or notify them to UA
+ * with indicated error code.
+
+ * @param [in,out] job_ring The job ring to poll.
+ * @param [in] do_notify Can be #TRUE or #FALSE.
+ * Indicates if descriptors to be discarded
+ * or notified to UA with given error_code.
+ * @param [in] error_code The detailed SEC error code.
+ * @param [out] notified_descs Number of notified descriptors.
+ * Can be NULL if do_notify is #FALSE
+ */
+void hw_flush_job_ring(struct sec_job_ring_t *job_ring,
+ uint32_t do_notify,
+ uint32_t error_code, uint32_t *notified_descs);
+
+/*
+ * @brief Flush job rings of any processed descs.
+ * The processed descs are silently dropped,
+ * WITHOUT being notified to UA.
+ */
+void flush_job_rings(void);
+
+/*
+ * @brief Handle desc that generated error in SEC engine.
+ * Identify the exact type of error and handle the error.
+ * Depending on the error type, the job ring could be reset.
+ * All descs that are submitted for processing on this job ring
+ * are notified to User Application with error status and detailed error code.
+
+ * @param [in] job_ring Job ring
+ * @param [in] sec_error_code Error code read from job ring's Channel
+ * Status Register
+ * @param [out] notified_descs Number of notified descs. Can be NULL if
+ * do_notify is #FALSE
+ * @param [out] do_driver_shutdown If set to #TRUE, then UA is returned code
+ * #SEC_PROCESSING_ERROR
+ * which is indication that UA must call
+ * sec_release() after this.
+ */
+void sec_handle_desc_error(struct sec_job_ring_t *job_ring,
+ uint32_t sec_error_code,
+ uint32_t *notified_descs,
+ uint32_t *do_driver_shutdown);
+
+/*
+ * @brief Release the software and hardware resources tied to a job ring.
+ * @param [in] job_ring The job ring
+ * @retval 0 for success
+ * @retval -1 for error
+ */
+int shutdown_job_ring(struct sec_job_ring_t *job_ring);
+
+/*
+ * @brief Enable irqs on associated job ring.
+ * @param [in] job_ring The job ring
+ * @retval 0 for success
+ * @retval -1 for error
+ */
+int jr_enable_irqs(struct sec_job_ring_t *job_ring);
+
+/*
+ * @brief Disable irqs on associated job ring.
+ * @param [in] job_ring The job ring
+ * @retval 0 for success
+ * @retval -1 for error
+ */
+int jr_disable_irqs(struct sec_job_ring_t *job_ring);
+
+ /*
+ * IRJA - Input Ring Jobs Added Register shows
+ * how many new jobs were added to the Input Ring.
+ */
+static inline void hw_enqueue_desc_on_job_ring(struct jobring_regs *regs,
+ int num)
+{
+ sec_out32(®s->irja, num);
+}
+
+#endif /* _SEC_HW_SPECIFIC_H_ */
diff --git a/include/drivers/nxp/crypto/caam/sec_jr_driver.h b/include/drivers/nxp/crypto/caam/sec_jr_driver.h
new file mode 100644
index 0000000..57e0fa0
--- /dev/null
+++ b/include/drivers/nxp/crypto/caam/sec_jr_driver.h
@@ -0,0 +1,178 @@
+/*
+ * Copyright 2017-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _JR_DRIVER_H_
+#define _JR_DRIVER_H_
+
+#include "jr_driver_config.h"
+
+/* The maximum size of a SEC descriptor, in WORDs (32 bits). */
+#define MAX_DESC_SIZE_WORDS 64
+
+#define CAAM_TIMEOUT 200000 /* ms */
+
+/* Return codes for JR user space driver APIs */
+typedef enum sec_return_code_e {
+ SEC_SUCCESS = 0,
+ SEC_INVALID_INPUT_PARAM,
+ SEC_OUT_OF_MEMORY,
+ SEC_DESCRIPTOR_IN_FLIGHT,
+ SEC_LAST_DESCRIPTOR_IN_FLIGHT,
+ SEC_PROCESSING_ERROR,
+ SEC_DESC_PROCESSING_ERROR,
+ SEC_JR_IS_FULL,
+ SEC_DRIVER_RELEASE_IN_PROGRESS,
+ SEC_DRIVER_ALREADY_INITIALIZED,
+ SEC_DRIVER_NOT_INITIALIZED,
+ SEC_JOB_RING_RESET_IN_PROGRESS,
+ SEC_RESET_ENGINE_FAILED,
+ SEC_ENABLE_IRQS_FAILED,
+ SEC_DISABLE_IRQS_FAILED,
+ SEC_RETURN_CODE_MAX_VALUE,
+} sec_return_code_t;
+
+/* STRUCTURES AND OTHER TYPEDEFS */
+
+/*
+ * @brief Function called by JR User Space driver to notify every processed
+ * descriptor.
+ *
+ * Callback provided by the User Application.
+ * Callback is invoked by JR User Space driver for each descriptor processed by
+ * SEC
+ * @param [in] status Status word indicating processing result for
+ * this descriptor.
+ * @param [in] arg Opaque data passed by User Application
+ * It is opaque from JR driver's point of view.
+ * @param [in] job_ring The job ring handle on which the processed
+ * descriptor word was enqueued
+ */
+typedef void (*user_callback) (uint32_t *desc, uint32_t status,
+ void *arg, void *job_ring);
+
+/*
+ * Structure encompassing a job descriptor which is to be processed
+ * by SEC. User should also initialise this structure with the callback
+ * function pointer which will be called by driver after recieving proccessed
+ * descriptor from SEC. User data is also passed in this data structure which
+ * will be sent as an argument to the user callback function.
+ */
+struct job_descriptor {
+ uint32_t desc[MAX_DESC_SIZE_WORDS];
+ void *arg;
+ user_callback callback;
+};
+
+/*
+ * @brief Initialize the JR User Space driver.
+ * This function will handle initialization of sec library
+ * along with registering platform specific callbacks,
+ * as well as local data initialization.
+ * Call once during application startup.
+ * @note Global SEC initialization is done in SEC kernel driver.
+ * @note The hardware IDs of the initialized Job Rings are opaque to the UA.
+ * The exact Job Rings used by this library are decided between SEC user
+ * space driver and SEC kernel driver. A static partitioning of Job Rings is
+ * assumed, configured in DTS(device tree specification) file.
+ * @param [in] platform_cb Registering the platform specific
+ * callbacks with driver
+ * @retval ::0 for successful execution
+ * @retval ::-1 failure
+ */
+int sec_jr_lib_init(void);
+
+/*
+ * @brief Initialize the software and hardware resources tied to a job ring.
+ * @param [in] jr_mode; Model to be used by SEC Driver to receive
+ * notifications from SEC. Can be either
+ * SEC_NOTIFICATION_TYPE_IRQ or
+ * SEC_NOTIFICATION_TYPE_POLL
+ * @param [in] irq_coalescing_timer This value determines the maximum
+ * amount of time after processing a
+ * descriptor before raising an interrupt.
+ * @param [in] irq_coalescing_count This value determines how many
+ * descriptors are completed before
+ * raising an interrupt.
+ * @param [in] reg_base_addr The job ring base address register
+ * @param [in] irq_id The job ring interrupt identification number.
+ * @retval job_ring_handle for successful job ring configuration
+ * @retval NULL on error
+ */
+void *init_job_ring(uint8_t jr_mode,
+ uint16_t irq_coalescing_timer,
+ uint8_t irq_coalescing_count,
+ void *reg_base_addr, uint32_t irq_id);
+
+/*
+ * @brief Release the resources used by the JR User Space driver.
+ * Reset and release SEC's job rings indicated by the User Application at
+ * init_job_ring() and free any memory allocated internally.
+ * Call once during application tear down.
+ * @note In case there are any descriptors in-flight (descriptors received by
+ * JR driver for processing and for which no response was yet provided to UA),
+ * the descriptors are discarded without any notifications to User Application.
+ * @retval ::0 is returned for a successful execution
+ * @retval ::-1 is returned if JR driver release is in progress
+ */
+int sec_release(void);
+
+/*
+ * @brief Submit a descriptor for SEC processing.
+ * This function creates a "job" which is meant to instruct SEC HW
+ * to perform the processing on the input buffer. The "job" is enqueued
+ * in the Job Ring associated. The function will return after the "job"
+ * enqueue is finished. The function will not wait for SEC to
+ * start or/and finish the "job" processing.
+ * After the processing is finished the SEC HW writes the processing result
+ * to the provided output buffer.
+ * The Caller must poll JR driver using jr_dequeue()
+ * to receive notifications of the processing completion
+ * status. The notifications are received by caller by means of callback
+ * (see ::user_callback).
+ * @param [in] job_ring_handle The handle of the job ring on which
+ * descriptor is to be enqueued
+ * @param [in] job_descriptor The job descriptor structure of type
+ * struct job_descriptor. This structure
+ * should be filled with job descriptor along
+ * with callback function to be called after
+ * processing of descriptor and some
+ * opaque data passed to be passed to the
+ * callback function
+ *
+ * @retval ::0 is returned for successful execution
+ * @retval ::-1 is returned if there is some enqueue failure
+ */
+int enq_jr_desc(void *job_ring_handle, struct job_descriptor *jobdescr);
+
+/*
+ * @brief Polls for available descriptors processed by SEC on a specific
+ * Job Ring
+ * This function polls the SEC Job Rings and delivers processed descriptors
+ * Each processed descriptor has a user_callback registered.
+ * This user_callback is invoked for each processed descriptor.
+ * The polling is stopped when "limit" descriptors are notified or when
+ * there are no more descriptors to notify.
+ * @note The dequeue_jr() API cannot be called from within a user_callback
+ * function
+ * @param [in] job_ring_handle The Job Ring handle.
+ * @param [in] limit This value represents the maximum number
+ * of processed descriptors that can be
+ * notified API call on this Job Ring.
+ * Note that fewer descriptors may be notified
+ * if enough processed descriptors are not
+ * available.
+ * If limit has a negative value, then all
+ * ready descriptors will be notified.
+ *
+ * @retval :: >=0 is returned where retval is the total
+ * Number of descriptors notified
+ * during this function call.
+ * @retval :: -1 is returned in case of some error
+ */
+int dequeue_jr(void *job_ring_handle, int32_t limit);
+
+#endif /* _JR_DRIVER_H_ */
diff --git a/include/drivers/nxp/csu/csu.h b/include/drivers/nxp/csu/csu.h
new file mode 100644
index 0000000..3a43e45
--- /dev/null
+++ b/include/drivers/nxp/csu/csu.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef CSU_H
+#define CSU_H
+
+#define CSU_SEC_ACCESS_REG_OFFSET (0x0021CU)
+
+/* Macros defining access permissions to configure
+ * the regions controlled by Central Security Unit.
+ */
+enum csu_cslx_access {
+ CSU_NS_SUP_R = (0x8U),
+ CSU_NS_SUP_W = (0x80U),
+ CSU_NS_SUP_RW = (0x88U),
+ CSU_NS_USER_R = (0x4U),
+ CSU_NS_USER_W = (0x40U),
+ CSU_NS_USER_RW = (0x44U),
+ CSU_S_SUP_R = (0x2U),
+ CSU_S_SUP_W = (0x20U),
+ CSU_S_SUP_RW = (0x22U),
+ CSU_S_USER_R = (0x1U),
+ CSU_S_USER_W = (0x10U),
+ CSU_S_USER_RW = (0x11U),
+ CSU_ALL_RW = (0xffU),
+};
+
+struct csu_ns_dev_st {
+ uintptr_t ind;
+ uint32_t val;
+};
+
+void enable_layerscape_ns_access(struct csu_ns_dev_st *csu_ns_dev,
+ uint32_t num, uintptr_t nxp_csu_addr);
+
+#endif
diff --git a/include/drivers/nxp/dcfg/dcfg.h b/include/drivers/nxp/dcfg/dcfg.h
new file mode 100644
index 0000000..524450a
--- /dev/null
+++ b/include/drivers/nxp/dcfg/dcfg.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DCFG_H
+#define DCFG_H
+
+#include <endian.h>
+
+#if defined(CONFIG_CHASSIS_2)
+#include <dcfg_lsch2.h>
+#elif defined(CONFIG_CHASSIS_3_2)
+#include <dcfg_lsch3.h>
+#endif
+
+#ifdef NXP_GUR_BE
+#define gur_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
+#define gur_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
+#elif defined(NXP_GUR_LE)
+#define gur_in32(a) mmio_read_32((uintptr_t)(a))
+#define gur_out32(a, v) mmio_write_32((uintptr_t)(a), v)
+#else
+#error Please define CCSR GUR register endianness
+#endif
+
+typedef struct {
+ union {
+ uint32_t val;
+ struct {
+ uint32_t min_ver:4;
+ uint32_t maj_ver:4;
+#if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2)
+ uint32_t personality:6;
+ uint32_t rsv1:2;
+#elif defined(CONFIG_CHASSIS_2)
+ uint32_t personality:8;
+
+#endif
+#if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2)
+ uint32_t dev_id:6;
+ uint32_t rsv2:2;
+ uint32_t family:4;
+#elif defined(CONFIG_CHASSIS_2)
+ uint32_t dev_id:12;
+#endif
+ uint32_t mfr_id;
+ } __packed bf;
+ struct {
+ uint32_t maj_min:8;
+ uint32_t version; /* SoC version without major and minor info */
+ } __packed bf_ver;
+ } __packed svr_reg;
+ bool sec_enabled;
+ bool is_populated;
+} soc_info_t;
+
+typedef struct {
+ bool is_populated;
+ uint8_t ocram_present;
+ uint8_t ddrc1_present;
+#if defined(CONFIG_CHASSIS_3) || defined(CONFIG_CHASSIS_3_2)
+ uint8_t ddrc2_present;
+#endif
+} devdisr5_info_t;
+
+typedef struct {
+ uint32_t porsr1;
+ uintptr_t g_nxp_dcfg_addr;
+ unsigned long nxp_sysclk_freq;
+ unsigned long nxp_ddrclk_freq;
+ unsigned int nxp_plat_clk_divider;
+} dcfg_init_info_t;
+
+
+struct sysinfo {
+ unsigned long freq_platform;
+ unsigned long freq_ddr_pll0;
+ unsigned long freq_ddr_pll1;
+};
+
+int get_clocks(struct sysinfo *sys);
+
+/* Read the PORSR1 register */
+uint32_t read_reg_porsr1(void);
+
+/*******************************************************************************
+ * Returns true if secur eboot is enabled on board
+ * mode = 0 (development mode - sb_en = 1)
+ * mode = 1 (production mode - ITS = 1)
+ ******************************************************************************/
+bool check_boot_mode_secure(uint32_t *mode);
+
+const soc_info_t *get_soc_info();
+const devdisr5_info_t *get_devdisr5_info();
+
+void dcfg_init(dcfg_init_info_t *dcfg_init_data);
+bool is_sec_enabled(void);
+
+void error_handler(int error_code);
+#endif /* DCFG_H */
diff --git a/include/drivers/nxp/dcfg/dcfg_lsch2.h b/include/drivers/nxp/dcfg/dcfg_lsch2.h
new file mode 100644
index 0000000..1e56729
--- /dev/null
+++ b/include/drivers/nxp/dcfg/dcfg_lsch2.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2020-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DCFG_LSCH2_H
+#define DCFG_LSCH2_H
+
+/* dcfg block register offsets and bitfields */
+#define DCFG_PORSR1_OFFSET 0x00
+#define DCFG_DEVDISR1_OFFSET 0x070
+#define DCFG_DEVDISR4_OFFSET 0x07C
+#define DCFG_DEVDISR5_OFFSET 0x080
+#define DCFG_COREDISR_OFFSET 0x094
+#define RCWSR0_OFFSET 0x100
+#define RCWSR5_OFFSET 0x118
+#define DCFG_BOOTLOCPTRL_OFFSET 0x400
+#define DCFG_BOOTLOCPTRH_OFFSET 0x404
+#define DCFG_COREDISABLEDSR_OFFSET 0x990
+#define DCFG_SCRATCH4_OFFSET 0x20C
+#define DCFG_SVR_OFFSET 0x0A4
+#define DCFG_BRR_OFFSET 0x0E4
+
+#define DCFG_RSTCR_OFFSET 0x0B0
+#define RSTCR_RESET_REQ 0x2
+
+#define DCFG_RSTRQSR1_OFFSET 0x0C8
+#define DCFG_RSTRQMR1_OFFSET 0x0C0
+
+/* DCFG DCSR Macros */
+#define DCFG_DCSR_PORCR1_OFFSET 0x0
+
+#define SVR_MFR_ID_MASK 0xF0000000
+#define SVR_MFR_ID_SHIFT 28
+#define SVR_DEV_ID_MASK 0xFFF0000
+#define SVR_DEV_ID_SHIFT 16
+#define SVR_PERSONALITY_MASK 0xFF00
+#define SVR_PERSONALITY_SHIFT 8
+#define SVR_SEC_MASK 0x100
+#define SVR_SEC_SHIFT 8
+#define SVR_MAJ_VER_MASK 0xF0
+#define SVR_MAJ_VER_SHIFT 4
+#define SVR_MIN_VER_MASK 0xF
+
+#define DISR5_DDRC1_MASK 0x1
+#define DISR5_OCRAM_MASK 0x40
+
+/* DCFG regsiters bit masks */
+#define RCWSR0_SYS_PLL_RAT_SHIFT 25
+#define RCWSR0_SYS_PLL_RAT_MASK 0x1f
+#define RCWSR0_MEM_PLL_RAT_SHIFT 16
+#define RCWSR0_MEM_PLL_RAT_MASK 0x3f
+#define RCWSR0_MEM2_PLL_RAT_SHIFT 18
+#define RCWSR0_MEM2_PLL_RAT_MASK 0x3f
+
+#define RCWSR_SB_EN_OFFSET RCWSR5_OFFSET
+#define RCWSR_SBEN_MASK 0x1
+#define RCWSR_SBEN_SHIFT 21
+
+/* RCW SRC NAND */
+#define RCW_SRC_NAND_MASK (0x100)
+#define RCW_SRC_NAND_VAL (0x100)
+#define NAND_RESERVED_MASK (0xFC)
+#define NAND_RESERVED_1 (0x0)
+#define NAND_RESERVED_2 (0x80)
+
+/* RCW SRC NOR */
+#define RCW_SRC_NOR_MASK (0x1F0)
+#define NOR_8B_VAL (0x10)
+#define NOR_16B_VAL (0x20)
+#define SD_VAL (0x40)
+#define QSPI_VAL1 (0x44)
+#define QSPI_VAL2 (0x45)
+
+#endif /* DCFG_LSCH2_H */
diff --git a/include/drivers/nxp/dcfg/dcfg_lsch3.h b/include/drivers/nxp/dcfg/dcfg_lsch3.h
new file mode 100644
index 0000000..40f02c1
--- /dev/null
+++ b/include/drivers/nxp/dcfg/dcfg_lsch3.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2020-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DCFG_LSCH3_H
+#define DCFG_LSCH3_H
+
+/* dcfg block register offsets and bitfields */
+#define DCFG_PORSR1_OFFSET 0x00
+
+#define DCFG_DEVDISR1_OFFSET 0x70
+#define DCFG_DEVDISR1_SEC (1 << 22)
+
+#define DCFG_DEVDISR2_OFFSET 0x74
+
+#define DCFG_DEVDISR3_OFFSET 0x78
+#define DCFG_DEVDISR3_QBMAIN (1 << 12)
+
+#define DCFG_DEVDISR4_OFFSET 0x7C
+#define DCFG_DEVDISR4_SPI_QSPI (1 << 4 | 1 << 5)
+
+#define DCFG_DEVDISR5_OFFSET 0x80
+#define DISR5_DDRC1_MASK 0x1
+#define DISR5_DDRC2_MASK 0x2
+#define DISR5_OCRAM_MASK 0x1000
+#define DEVDISR5_MASK_ALL_MEM 0x00001003
+#define DEVDISR5_MASK_DDR 0x00000003
+#define DEVDISR5_MASK_DBG 0x00000400
+
+#define DCFG_DEVDISR6_OFFSET 0x84
+//#define DEVDISR6_MASK 0x00000001
+
+#define DCFG_COREDISR_OFFSET 0x94
+
+#define DCFG_SVR_OFFSET 0x0A4
+#define SVR_MFR_ID_MASK 0xF0000000
+#define SVR_MFR_ID_SHIFT 28
+#define SVR_FAMILY_MASK 0xF000000
+#define SVR_FAMILY_SHIFT 24
+#define SVR_DEV_ID_MASK 0x3F0000
+#define SVR_DEV_ID_SHIFT 16
+#define SVR_PERSONALITY_MASK 0x3E00
+#define SVR_PERSONALITY_SHIFT 9
+#define SVR_SEC_MASK 0x100
+#define SVR_SEC_SHIFT 8
+#define SVR_MAJ_VER_MASK 0xF0
+#define SVR_MAJ_VER_SHIFT 4
+#define SVR_MIN_VER_MASK 0xF
+
+#define RCWSR0_OFFSET 0x100
+#define RCWSR0_SYS_PLL_RAT_SHIFT 2
+#define RCWSR0_SYS_PLL_RAT_MASK 0x1f
+#define RCWSR0_MEM_PLL_RAT_SHIFT 10
+#define RCWSR0_MEM_PLL_RAT_MASK 0x3f
+#define RCWSR0_MEM2_PLL_RAT_SHIFT 18
+#define RCWSR0_MEM2_PLL_RAT_MASK 0x3f
+
+#define RCWSR5_OFFSET 0x110
+#define RCWSR9_OFFSET 0x120
+#define RCWSR_SB_EN_OFFSET RCWSR9_OFFSET
+#define RCWSR_SBEN_MASK 0x1
+#define RCWSR_SBEN_SHIFT 10
+
+#define RCW_SR27_OFFSET 0x168
+/* DCFG register to dump error code */
+#define DCFG_SCRATCH4_OFFSET 0x20C
+#define DCFG_SCRATCHRW5_OFFSET 0x210
+#define DCFG_SCRATCHRW6_OFFSET 0x214
+#define DCFG_SCRATCHRW7_OFFSET 0x218
+#define DCFG_BOOTLOCPTRL_OFFSET 0x400
+#define DCFG_BOOTLOCPTRH_OFFSET 0x404
+#define DCFG_COREDISABLEDSR_OFFSET 0x990
+
+#endif /* DCFG_LSCH3_H */
diff --git a/include/drivers/nxp/dcfg/scfg.h b/include/drivers/nxp/dcfg/scfg.h
new file mode 100644
index 0000000..b6e3df5
--- /dev/null
+++ b/include/drivers/nxp/dcfg/scfg.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2020-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef SCFG_H
+#define SCFG_H
+
+#ifdef CONFIG_CHASSIS_2
+
+/* SCFG register offsets */
+#define SCFG_CORE0_SFT_RST_OFFSET 0x0130
+#define SCFG_SNPCNFGCR_OFFSET 0x01A4
+#define SCFG_CORESRENCR_OFFSET 0x0204
+#define SCFG_RVBAR0_0_OFFSET 0x0220
+#define SCFG_RVBAR0_1_OFFSET 0x0224
+#define SCFG_COREBCR_OFFSET 0x0680
+#define SCFG_RETREQCR_OFFSET 0x0424
+
+#define SCFG_COREPMCR_OFFSET 0x042C
+#define COREPMCR_WFIL2 0x1
+
+#define SCFG_GIC400_ADDR_ALIGN_OFFSET 0x0188
+#define SCFG_BOOTLOCPTRH_OFFSET 0x0600
+#define SCFG_BOOTLOCPTRL_OFFSET 0x0604
+#define SCFG_SCRATCHRW2_OFFSET 0x0608
+#define SCFG_SCRATCHRW3_OFFSET 0x060C
+
+/* SCFG bit fields */
+#define SCFG_SNPCNFGCR_SECRDSNP 0x80000000
+#define SCFG_SNPCNFGCR_SECWRSNP 0x40000000
+#endif /* CONFIG_CHASSIS_2 */
+
+#ifndef __ASSEMBLER__
+#include <endian.h>
+#include <lib/mmio.h>
+
+#ifdef NXP_SCFG_BE
+#define scfg_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
+#define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
+#define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v)
+#define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v)
+#define scfg_clrsetbits32(a, clear, set) \
+ mmio_clrsetbits_32((uintptr_t)(a), clear, set)
+#elif defined(NXP_GUR_LE)
+#define scfg_in32(a) mmio_read_32((uintptr_t)(a))
+#define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), v)
+#define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v)
+#define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v)
+#define scfg_clrsetbits32(a, clear, set) \
+ mmio_clrsetbits_32((uintptr_t)(a), clear, set)
+#else
+#error Please define CCSR SCFG register endianness
+#endif
+#endif /* __ASSEMBLER__ */
+
+#endif /* SCFG_H */
diff --git a/include/drivers/nxp/ddr/ddr.h b/include/drivers/nxp/ddr/ddr.h
new file mode 100644
index 0000000..0ef2870
--- /dev/null
+++ b/include/drivers/nxp/ddr/ddr.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DDR_H
+#define DDR_H
+
+#include "ddr_io.h"
+#include "dimm.h"
+#include "immap.h"
+
+#ifndef DDRC_NUM_CS
+#define DDRC_NUM_CS 4
+#endif
+
+/*
+ * This is irrespective of what is the number of DDR controller,
+ * number of DIMM used. This is set to maximum
+ * Max controllers = 2
+ * Max num of DIMM per controlle = 2
+ * MAX NUM CS = 4
+ * Not to be changed.
+ */
+#define MAX_DDRC_NUM 2
+#define MAX_DIMM_NUM 2
+#define MAX_CS_NUM 4
+
+#include "opts.h"
+#include "regs.h"
+#include "utility.h"
+
+#ifdef DDR_DEBUG
+#define debug(...) INFO(__VA_ARGS__)
+#else
+#define debug(...) VERBOSE(__VA_ARGS__)
+#endif
+
+#ifndef DDRC_NUM_DIMM
+#define DDRC_NUM_DIMM 1
+#endif
+
+#define CONFIG_CS_PER_SLOT \
+ (DDRC_NUM_CS / DDRC_NUM_DIMM)
+
+/* Record of register values computed */
+struct ddr_cfg_regs {
+ struct {
+ unsigned int bnds;
+ unsigned int config;
+ unsigned int config_2;
+ } cs[MAX_CS_NUM];
+ unsigned int dec[10];
+ unsigned int timing_cfg[10];
+ unsigned int sdram_cfg[3];
+ unsigned int sdram_mode[16];
+ unsigned int md_cntl;
+ unsigned int interval;
+ unsigned int data_init;
+ unsigned int clk_cntl;
+ unsigned int init_addr;
+ unsigned int init_ext_addr;
+ unsigned int zq_cntl;
+ unsigned int wrlvl_cntl[3];
+ unsigned int ddr_sr_cntr;
+ unsigned int sdram_rcw[6];
+ unsigned int dq_map[4];
+ unsigned int eor;
+ unsigned int cdr[2];
+ unsigned int err_disable;
+ unsigned int err_int_en;
+ unsigned int tx_cfg[4];
+ unsigned int debug[64];
+};
+
+struct ddr_conf {
+ int dimm_in_use[MAX_DIMM_NUM];
+ int cs_in_use; /* bitmask, bit 0 for cs0, bit 1 for cs1, etc. */
+ int cs_on_dimm[MAX_DIMM_NUM]; /* bitmask */
+ unsigned long long cs_base_addr[MAX_CS_NUM];
+ unsigned long long cs_size[MAX_CS_NUM];
+ unsigned long long base_addr;
+ unsigned long long total_mem;
+};
+
+struct ddr_info {
+ unsigned long clk;
+ unsigned long long mem_base;
+ unsigned int num_ctlrs;
+ unsigned int dimm_on_ctlr;
+ struct dimm_params dimm;
+ struct memctl_opt opt;
+ struct ddr_conf conf;
+ struct ddr_cfg_regs ddr_reg;
+ struct ccsr_ddr *ddr[MAX_DDRC_NUM];
+ uint16_t *phy[MAX_DDRC_NUM];
+ int *spd_addr;
+ unsigned int ip_rev;
+ uintptr_t phy_gen2_fw_img_buf;
+ void *img_loadr;
+ int warm_boot_flag;
+};
+
+struct rc_timing {
+ unsigned int speed_bin;
+ unsigned int clk_adj;
+ unsigned int wrlvl;
+};
+
+struct board_timing {
+ unsigned int rc;
+ struct rc_timing const *p;
+ unsigned int add1;
+ unsigned int add2;
+};
+
+enum warm_boot {
+ DDR_COLD_BOOT = 0,
+ DDR_WARM_BOOT = 1,
+ DDR_WRM_BOOT_NT_SUPPORTED = -1,
+};
+
+int disable_unused_ddrc(struct ddr_info *priv, int mask,
+ uintptr_t nxp_ccn_hn_f0_addr);
+int ddr_board_options(struct ddr_info *priv);
+int compute_ddrc(const unsigned long clk,
+ const struct memctl_opt *popts,
+ const struct ddr_conf *conf,
+ struct ddr_cfg_regs *ddr,
+ const struct dimm_params *dimm_params,
+ const unsigned int ip_rev);
+int compute_ddr_phy(struct ddr_info *priv);
+int ddrc_set_regs(const unsigned long clk,
+ const struct ddr_cfg_regs *regs,
+ const struct ccsr_ddr *ddr,
+ int twopass);
+int cal_board_params(struct ddr_info *priv,
+ const struct board_timing *dimm,
+ int len);
+/* return bit mask of used DIMM(s) */
+int ddr_get_ddr_params(struct dimm_params *pdimm, struct ddr_conf *conf);
+long long dram_init(struct ddr_info *priv
+#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
+ , uintptr_t nxp_ccn_hn_f0_addr
+#endif
+ );
+long long board_static_ddr(struct ddr_info *info);
+
+#endif /* DDR_H */
diff --git a/include/drivers/nxp/ddr/ddr_io.h b/include/drivers/nxp/ddr/ddr_io.h
new file mode 100644
index 0000000..fbd7e97
--- /dev/null
+++ b/include/drivers/nxp/ddr/ddr_io.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DDR_IO_H
+#define DDR_IO_H
+
+#include <endian.h>
+
+#include <lib/mmio.h>
+
+#define min(a, b) (((a) > (b)) ? (b) : (a))
+
+#define max(a, b) (((a) > (b)) ? (a) : (b))
+
+/* macro for memory barrier */
+#define mb() asm volatile("dsb sy" : : : "memory")
+
+#ifdef NXP_DDR_BE
+#define ddr_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
+#define ddr_out32(a, v) mmio_write_32((uintptr_t)(a),\
+ bswap32(v))
+#elif defined(NXP_DDR_LE)
+#define ddr_in32(a) mmio_read_32((uintptr_t)(a))
+#define ddr_out32(a, v) mmio_write_32((uintptr_t)(a), v)
+#else
+#error Please define CCSR DDR register endianness
+#endif
+
+#define ddr_setbits32(a, v) ddr_out32((a), ddr_in32(a) | (v))
+#define ddr_clrbits32(a, v) ddr_out32((a), ddr_in32(a) & ~(v))
+#define ddr_clrsetbits32(a, c, s) ddr_out32((a), (ddr_in32(a) & ~(c)) \
+ | (s))
+
+#endif /* DDR_IO_H */
diff --git a/include/drivers/nxp/ddr/dimm.h b/include/drivers/nxp/ddr/dimm.h
new file mode 100644
index 0000000..fcae179
--- /dev/null
+++ b/include/drivers/nxp/ddr/dimm.h
@@ -0,0 +1,330 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DIMM_H
+#define DIMM_H
+
+#define SPD_MEMTYPE_DDR4 0x0C
+
+#define DDR4_SPD_MODULETYPE_MASK 0x0f
+#define DDR4_SPD_MODULETYPE_EXT 0x00
+#define DDR4_SPD_RDIMM 0x01
+#define DDR4_SPD_UDIMM 0x02
+#define DDR4_SPD_SO_DIMM 0x03
+#define DDR4_SPD_LRDIMM 0x04
+#define DDR4_SPD_MINI_RDIMM 0x05
+#define DDR4_SPD_MINI_UDIMM 0x06
+#define DDR4_SPD_72B_SO_RDIMM 0x08
+#define DDR4_SPD_72B_SO_UDIMM 0x09
+#define DDR4_SPD_16B_SO_DIMM 0x0c
+#define DDR4_SPD_32B_SO_DIMM 0x0d
+
+#define SPD_SPA0_ADDRESS 0x36
+#define SPD_SPA1_ADDRESS 0x37
+
+#define spd_to_ps(mtb, ftb) \
+ ((mtb) * pdimm->mtb_ps + ((ftb) * pdimm->ftb_10th_ps) / 10)
+
+#ifdef DDR_DEBUG
+#define dump_spd(spd, len) { \
+ register int i; \
+ register unsigned char *buf = (void *)(spd); \
+ \
+ for (i = 0; i < (len); i++) { \
+ print_uint(i); \
+ puts("\t: 0x"); \
+ print_hex(buf[i]); \
+ puts("\n"); \
+ } \
+}
+#else
+#define dump_spd(spd, len) {}
+#endif
+
+/* From JEEC Standard No. 21-C release 23A */
+struct ddr4_spd {
+ /* General Section: Bytes 0-127 */
+ unsigned char info_size_crc; /* 0 # bytes */
+ unsigned char spd_rev; /* 1 Total # bytes of SPD */
+ unsigned char mem_type; /* 2 Key Byte / mem type */
+ unsigned char module_type; /* 3 Key Byte / Module Type */
+ unsigned char density_banks; /* 4 Density and Banks */
+ unsigned char addressing; /* 5 Addressing */
+ unsigned char package_type; /* 6 Package type */
+ unsigned char opt_feature; /* 7 Optional features */
+ unsigned char thermal_ref; /* 8 Thermal and refresh */
+ unsigned char oth_opt_features; /* 9 Other optional features */
+ unsigned char res_10; /* 10 Reserved */
+ unsigned char module_vdd; /* 11 Module nominal voltage */
+ unsigned char organization; /* 12 Module Organization */
+ unsigned char bus_width; /* 13 Module Memory Bus Width */
+ unsigned char therm_sensor; /* 14 Module Thermal Sensor */
+ unsigned char ext_type; /* 15 Extended module type */
+ unsigned char res_16;
+ unsigned char timebases; /* 17 MTb and FTB */
+ unsigned char tck_min; /* 18 tCKAVGmin */
+ unsigned char tck_max; /* 19 TCKAVGmax */
+ unsigned char caslat_b1; /* 20 CAS latencies, 1st byte */
+ unsigned char caslat_b2; /* 21 CAS latencies, 2nd byte */
+ unsigned char caslat_b3; /* 22 CAS latencies, 3rd byte */
+ unsigned char caslat_b4; /* 23 CAS latencies, 4th byte */
+ unsigned char taa_min; /* 24 Min CAS Latency Time */
+ unsigned char trcd_min; /* 25 Min RAS# to CAS# Delay Time */
+ unsigned char trp_min; /* 26 Min Row Precharge Delay Time */
+ unsigned char tras_trc_ext; /* 27 Upper Nibbles for tRAS and tRC */
+ unsigned char tras_min_lsb; /* 28 tRASmin, lsb */
+ unsigned char trc_min_lsb; /* 29 tRCmin, lsb */
+ unsigned char trfc1_min_lsb; /* 30 Min Refresh Recovery Delay Time */
+ unsigned char trfc1_min_msb; /* 31 Min Refresh Recovery Delay Time */
+ unsigned char trfc2_min_lsb; /* 32 Min Refresh Recovery Delay Time */
+ unsigned char trfc2_min_msb; /* 33 Min Refresh Recovery Delay Time */
+ unsigned char trfc4_min_lsb; /* 34 Min Refresh Recovery Delay Time */
+ unsigned char trfc4_min_msb; /* 35 Min Refresh Recovery Delay Time */
+ unsigned char tfaw_msb; /* 36 Upper Nibble for tFAW */
+ unsigned char tfaw_min; /* 37 tFAW, lsb */
+ unsigned char trrds_min; /* 38 tRRD_Smin, MTB */
+ unsigned char trrdl_min; /* 39 tRRD_Lmin, MTB */
+ unsigned char tccdl_min; /* 40 tCCS_Lmin, MTB */
+ unsigned char res_41[60-41]; /* 41 Rserved */
+ unsigned char mapping[78-60]; /* 60~77 Connector to SDRAM bit map */
+ unsigned char res_78[117-78]; /* 78~116, Reserved */
+ signed char fine_tccdl_min; /* 117 Fine offset for tCCD_Lmin */
+ signed char fine_trrdl_min; /* 118 Fine offset for tRRD_Lmin */
+ signed char fine_trrds_min; /* 119 Fine offset for tRRD_Smin */
+ signed char fine_trc_min; /* 120 Fine offset for tRCmin */
+ signed char fine_trp_min; /* 121 Fine offset for tRPmin */
+ signed char fine_trcd_min; /* 122 Fine offset for tRCDmin */
+ signed char fine_taa_min; /* 123 Fine offset for tAAmin */
+ signed char fine_tck_max; /* 124 Fine offset for tCKAVGmax */
+ signed char fine_tck_min; /* 125 Fine offset for tCKAVGmin */
+ /* CRC: Bytes 126-127 */
+ unsigned char crc[2]; /* 126-127 SPD CRC */
+
+ /* Module-Specific Section: Bytes 128-255 */
+ union {
+ struct {
+ /* 128 (Unbuffered) Module Nominal Height */
+ unsigned char mod_height;
+ /* 129 (Unbuffered) Module Maximum Thickness */
+ unsigned char mod_thickness;
+ /* 130 (Unbuffered) Reference Raw Card Used */
+ unsigned char ref_raw_card;
+ /* 131 (Unbuffered) Address Mapping from
+ * Edge Connector to DRAM
+ */
+ unsigned char addr_mapping;
+ /* 132~253 (Unbuffered) Reserved */
+ unsigned char res_132[254-132];
+ /* 254~255 CRC */
+ unsigned char crc[2];
+ } unbuffered;
+ struct {
+ /* 128 (Registered) Module Nominal Height */
+ unsigned char mod_height;
+ /* 129 (Registered) Module Maximum Thickness */
+ unsigned char mod_thickness;
+ /* 130 (Registered) Reference Raw Card Used */
+ unsigned char ref_raw_card;
+ /* 131 DIMM Module Attributes */
+ unsigned char modu_attr;
+ /* 132 RDIMM Thermal Heat Spreader Solution */
+ unsigned char thermal;
+ /* 133 Register Manufacturer ID Code, LSB */
+ unsigned char reg_id_lo;
+ /* 134 Register Manufacturer ID Code, MSB */
+ unsigned char reg_id_hi;
+ /* 135 Register Revision Number */
+ unsigned char reg_rev;
+ /* 136 Address mapping from register to DRAM */
+ unsigned char reg_map;
+ unsigned char ca_stren;
+ unsigned char clk_stren;
+ /* 139~253 Reserved */
+ unsigned char res_139[254-139];
+ /* 254~255 CRC */
+ unsigned char crc[2];
+ } registered;
+ struct {
+ /* 128 (Loadreduced) Module Nominal Height */
+ unsigned char mod_height;
+ /* 129 (Loadreduced) Module Maximum Thickness */
+ unsigned char mod_thickness;
+ /* 130 (Loadreduced) Reference Raw Card Used */
+ unsigned char ref_raw_card;
+ /* 131 DIMM Module Attributes */
+ unsigned char modu_attr;
+ /* 132 RDIMM Thermal Heat Spreader Solution */
+ unsigned char thermal;
+ /* 133 Register Manufacturer ID Code, LSB */
+ unsigned char reg_id_lo;
+ /* 134 Register Manufacturer ID Code, MSB */
+ unsigned char reg_id_hi;
+ /* 135 Register Revision Number */
+ unsigned char reg_rev;
+ /* 136 Address mapping from register to DRAM */
+ unsigned char reg_map;
+ /* 137 Register Output Drive Strength for CMD/Add*/
+ unsigned char reg_drv;
+ /* 138 Register Output Drive Strength for CK */
+ unsigned char reg_drv_ck;
+ /* 139 Data Buffer Revision Number */
+ unsigned char data_buf_rev;
+ /* 140 DRAM VrefDQ for Package Rank 0 */
+ unsigned char vrefqe_r0;
+ /* 141 DRAM VrefDQ for Package Rank 1 */
+ unsigned char vrefqe_r1;
+ /* 142 DRAM VrefDQ for Package Rank 2 */
+ unsigned char vrefqe_r2;
+ /* 143 DRAM VrefDQ for Package Rank 3 */
+ unsigned char vrefqe_r3;
+ /* 144 Data Buffer VrefDQ for DRAM Interface */
+ unsigned char data_intf;
+ /*
+ * 145 Data Buffer MDQ Drive Strength and RTT
+ * for data rate <= 1866
+ */
+ unsigned char data_drv_1866;
+ /*
+ * 146 Data Buffer MDQ Drive Strength and RTT
+ * for 1866 < data rate <= 2400
+ */
+ unsigned char data_drv_2400;
+ /*
+ * 147 Data Buffer MDQ Drive Strength and RTT
+ * for 2400 < data rate <= 3200
+ */
+ unsigned char data_drv_3200;
+ /* 148 DRAM Drive Strength */
+ unsigned char dram_drv;
+ /*
+ * 149 DRAM ODT (RTT_WR, RTT_NOM)
+ * for data rate <= 1866
+ */
+ unsigned char dram_odt_1866;
+ /*
+ * 150 DRAM ODT (RTT_WR, RTT_NOM)
+ * for 1866 < data rate <= 2400
+ */
+ unsigned char dram_odt_2400;
+ /*
+ * 151 DRAM ODT (RTT_WR, RTT_NOM)
+ * for 2400 < data rate <= 3200
+ */
+ unsigned char dram_odt_3200;
+ /*
+ * 152 DRAM ODT (RTT_PARK)
+ * for data rate <= 1866
+ */
+ unsigned char dram_odt_park_1866;
+ /*
+ * 153 DRAM ODT (RTT_PARK)
+ * for 1866 < data rate <= 2400
+ */
+ unsigned char dram_odt_park_2400;
+ /*
+ * 154 DRAM ODT (RTT_PARK)
+ * for 2400 < data rate <= 3200
+ */
+ unsigned char dram_odt_park_3200;
+ unsigned char res_155[254-155]; /* Reserved */
+ /* 254~255 CRC */
+ unsigned char crc[2];
+ } loadreduced;
+ unsigned char uc[128]; /* 128-255 Module-Specific Section */
+ } mod_section;
+
+ unsigned char res_256[320-256]; /* 256~319 Reserved */
+
+ /* Module supplier's data: Byte 320~383 */
+ unsigned char mmid_lsb; /* 320 Module MfgID Code LSB */
+ unsigned char mmid_msb; /* 321 Module MfgID Code MSB */
+ unsigned char mloc; /* 322 Mfg Location */
+ unsigned char mdate[2]; /* 323~324 Mfg Date */
+ unsigned char sernum[4]; /* 325~328 Module Serial Number */
+ unsigned char mpart[20]; /* 329~348 Mfg's Module Part Number */
+ unsigned char mrev; /* 349 Module Revision Code */
+ unsigned char dmid_lsb; /* 350 DRAM MfgID Code LSB */
+ unsigned char dmid_msb; /* 351 DRAM MfgID Code MSB */
+ unsigned char stepping; /* 352 DRAM stepping */
+ unsigned char msd[29]; /* 353~381 Mfg's Specific Data */
+ unsigned char res_382[2]; /* 382~383 Reserved */
+};
+
+/* Parameters for a DDR dimm computed from the SPD */
+struct dimm_params {
+ /* DIMM organization parameters */
+ char mpart[19]; /* guaranteed null terminated */
+
+ unsigned int n_ranks;
+ unsigned int die_density;
+ unsigned long long rank_density;
+ unsigned long long capacity;
+ unsigned int primary_sdram_width;
+ unsigned int ec_sdram_width;
+ unsigned int rdimm;
+ unsigned int package_3ds; /* number of dies in 3DS */
+ unsigned int device_width; /* x4, x8, x16 components */
+ unsigned int rc;
+
+ /* SDRAM device parameters */
+ unsigned int n_row_addr;
+ unsigned int n_col_addr;
+ unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */
+ unsigned int bank_addr_bits;
+ unsigned int bank_group_bits;
+ unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */
+
+ /* mirrored DIMMs */
+ unsigned int mirrored_dimm; /* only for ddr3 */
+
+ /* DIMM timing parameters */
+
+ int mtb_ps; /* medium timebase ps */
+ int ftb_10th_ps; /* fine timebase, in 1/10 ps */
+ int taa_ps; /* minimum CAS latency time */
+ int tfaw_ps; /* four active window delay */
+
+ /*
+ * SDRAM clock periods
+ * The range for these are 1000-10000 so a short should be sufficient
+ */
+ int tckmin_x_ps;
+ int tckmax_ps;
+
+ /* SPD-defined CAS latencies */
+ unsigned int caslat_x;
+
+ /* basic timing parameters */
+ int trcd_ps;
+ int trp_ps;
+ int tras_ps;
+
+ int trfc1_ps;
+ int trfc2_ps;
+ int trfc4_ps;
+ int trrds_ps;
+ int trrdl_ps;
+ int tccdl_ps;
+ int trfc_slr_ps;
+
+ int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */
+ int twr_ps; /* 15ns for all speed bins */
+
+ unsigned int refresh_rate_ps;
+ unsigned int extended_op_srt;
+
+ /* RDIMM */
+ unsigned char rcw[16]; /* Register Control Word 0-15 */
+ unsigned int dq_mapping[18];
+ unsigned int dq_mapping_ors;
+};
+
+int read_spd(unsigned char chip, void *buf, int len);
+int crc16(unsigned char *ptr, int count);
+int cal_dimm_params(const struct ddr4_spd *spd, struct dimm_params *pdimm);
+
+#endif /* DIMM_H */
diff --git a/include/drivers/nxp/ddr/fsl-mmdc/fsl_mmdc.h b/include/drivers/nxp/ddr/fsl-mmdc/fsl_mmdc.h
new file mode 100644
index 0000000..31db552
--- /dev/null
+++ b/include/drivers/nxp/ddr/fsl-mmdc/fsl_mmdc.h
@@ -0,0 +1,173 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef FSL_MMDC_H
+#define FSL_MMDC_H
+
+/* PHY Write Leveling Configuration and Error Status Register (MPWLGCR) */
+#define MPWLGCR_HW_WL_EN (1 << 0)
+
+/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
+#define MPPDCMPR2_MPR_COMPARE_EN (1 << 0)
+
+
+/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
+#define AUTO_RD_DQS_GATING_CALIBRATION_EN (1 << 28)
+
+/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
+#define MPRDDLHWCTL_AUTO_RD_CALIBRATION_EN (1 << 4)
+
+/* MMDC Core Power Saving Control and Status Register (MMDC_MAPSR) */
+#define MMDC_MAPSR_PWR_SAV_CTRL_STAT 0x00001067
+
+/* MMDC Core Refresh Control Register (MMDC_MDREF) */
+#define MDREF_START_REFRESH (1 << 0)
+
+/* MMDC Core Special Command Register (MDSCR) */
+#define CMD_ADDR_MSB_MR_OP(x) (x << 24)
+#define CMD_ADDR_LSB_MR_ADDR(x) (x << 16)
+#define MDSCR_DISABLE_CFG_REQ (0 << 15)
+#define MDSCR_ENABLE_CON_REQ (1 << 15)
+#define MDSCR_CON_ACK (1 << 14)
+#define MDSCR_WL_EN (1 << 9)
+#define CMD_NORMAL (0 << 4)
+#define CMD_PRECHARGE (1 << 4)
+#define CMD_AUTO_REFRESH (2 << 4)
+#define CMD_LOAD_MODE_REG (3 << 4)
+#define CMD_ZQ_CALIBRATION (4 << 4)
+#define CMD_PRECHARGE_BANK_OPEN (5 << 4)
+#define CMD_MRR (6 << 4)
+#define CMD_BANK_ADDR_0 0x0
+#define CMD_BANK_ADDR_1 0x1
+#define CMD_BANK_ADDR_2 0x2
+#define CMD_BANK_ADDR_3 0x3
+#define CMD_BANK_ADDR_4 0x4
+#define CMD_BANK_ADDR_5 0x5
+#define CMD_BANK_ADDR_6 0x6
+#define CMD_BANK_ADDR_7 0x7
+
+/* MMDC Core Control Register (MDCTL) */
+#define MDCTL_SDE0 (U(1) << 31)
+#define MDCTL_SDE1 (1 << 30)
+
+/* MMDC PHY ZQ HW control register (MMDC_MPZQHWCTRL) */
+#define MPZQHWCTRL_ZQ_HW_FORCE (1 << 16)
+
+/* MMDC PHY Measure Unit Register (MMDC_MPMUR0) */
+#define MMDC_MPMUR0_FRC_MSR (1 << 11)
+
+/* MMDC PHY Read delay-lines Configuration Register (MMDC_MPRDDLCTL) */
+/* default 64 for a quarter cycle delay */
+#define MMDC_MPRDDLCTL_DEFAULT_DELAY 0x40404040
+
+/* MMDC Registers */
+struct mmdc_regs {
+ unsigned int mdctl;
+ unsigned int mdpdc;
+ unsigned int mdotc;
+ unsigned int mdcfg0;
+ unsigned int mdcfg1;
+ unsigned int mdcfg2;
+ unsigned int mdmisc;
+ unsigned int mdscr;
+ unsigned int mdref;
+ unsigned int res1[2];
+ unsigned int mdrwd;
+ unsigned int mdor;
+ unsigned int mdmrr;
+ unsigned int mdcfg3lp;
+ unsigned int mdmr4;
+ unsigned int mdasp;
+ unsigned int res2[239];
+ unsigned int maarcr;
+ unsigned int mapsr;
+ unsigned int maexidr0;
+ unsigned int maexidr1;
+ unsigned int madpcr0;
+ unsigned int madpcr1;
+ unsigned int madpsr0;
+ unsigned int madpsr1;
+ unsigned int madpsr2;
+ unsigned int madpsr3;
+ unsigned int madpsr4;
+ unsigned int madpsr5;
+ unsigned int masbs0;
+ unsigned int masbs1;
+ unsigned int res3[2];
+ unsigned int magenp;
+ unsigned int res4[239];
+ unsigned int mpzqhwctrl;
+ unsigned int mpzqswctrl;
+ unsigned int mpwlgcr;
+ unsigned int mpwldectrl0;
+ unsigned int mpwldectrl1;
+ unsigned int mpwldlst;
+ unsigned int mpodtctrl;
+ unsigned int mprddqby0dl;
+ unsigned int mprddqby1dl;
+ unsigned int mprddqby2dl;
+ unsigned int mprddqby3dl;
+ unsigned int mpwrdqby0dl;
+ unsigned int mpwrdqby1dl;
+ unsigned int mpwrdqby2dl;
+ unsigned int mpwrdqby3dl;
+ unsigned int mpdgctrl0;
+ unsigned int mpdgctrl1;
+ unsigned int mpdgdlst0;
+ unsigned int mprddlctl;
+ unsigned int mprddlst;
+ unsigned int mpwrdlctl;
+ unsigned int mpwrdlst;
+ unsigned int mpsdctrl;
+ unsigned int mpzqlp2ctl;
+ unsigned int mprddlhwctl;
+ unsigned int mpwrdlhwctl;
+ unsigned int mprddlhwst0;
+ unsigned int mprddlhwst1;
+ unsigned int mpwrdlhwst0;
+ unsigned int mpwrdlhwst1;
+ unsigned int mpwlhwerr;
+ unsigned int mpdghwst0;
+ unsigned int mpdghwst1;
+ unsigned int mpdghwst2;
+ unsigned int mpdghwst3;
+ unsigned int mppdcmpr1;
+ unsigned int mppdcmpr2;
+ unsigned int mpswdar0;
+ unsigned int mpswdrdr0;
+ unsigned int mpswdrdr1;
+ unsigned int mpswdrdr2;
+ unsigned int mpswdrdr3;
+ unsigned int mpswdrdr4;
+ unsigned int mpswdrdr5;
+ unsigned int mpswdrdr6;
+ unsigned int mpswdrdr7;
+ unsigned int mpmur0;
+ unsigned int mpwrcadl;
+ unsigned int mpdccr;
+};
+
+struct fsl_mmdc_info {
+ unsigned int mdctl;
+ unsigned int mdpdc;
+ unsigned int mdotc;
+ unsigned int mdcfg0;
+ unsigned int mdcfg1;
+ unsigned int mdcfg2;
+ unsigned int mdmisc;
+ unsigned int mdref;
+ unsigned int mdrwd;
+ unsigned int mdor;
+ unsigned int mdasp;
+ unsigned int mpodtctrl;
+ unsigned int mpzqhwctrl;
+ unsigned int mprddlctl;
+};
+
+void mmdc_init(const struct fsl_mmdc_info *priv, uintptr_t nxp_ddr_addr);
+
+#endif /* FSL_MMDC_H */
diff --git a/include/drivers/nxp/ddr/immap.h b/include/drivers/nxp/ddr/immap.h
new file mode 100644
index 0000000..83b4de6
--- /dev/null
+++ b/include/drivers/nxp/ddr/immap.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DDR_IMMAP_H
+#define DDR_IMMAP_H
+
+#define DDR_DBUS_64 0
+#define DDR_DBUS_32 1
+#define DDR_DBUS_16 2
+
+/*
+ * DDRC register file for DDRC 5.0 and above
+ */
+struct ccsr_ddr {
+ struct {
+ unsigned int a; /* 0x0, 0x8, 0x10, 0x18 */
+ unsigned int res; /* 0x4, 0xc, 0x14, 0x1c */
+ } bnds[4];
+ unsigned char res_20[0x40 - 0x20];
+ unsigned int dec[10]; /* 0x40 */
+ unsigned char res_68[0x80 - 0x68];
+ unsigned int csn_cfg[4]; /* 0x80, 0x84, 0x88, 0x8c */
+ unsigned char res_90[48];
+ unsigned int csn_cfg_2[4]; /* 0xc0, 0xc4, 0xc8, 0xcc */
+ unsigned char res_d0[48];
+ unsigned int timing_cfg_3; /* SDRAM Timing Configuration 3 */
+ unsigned int timing_cfg_0; /* SDRAM Timing Configuration 0 */
+ unsigned int timing_cfg_1; /* SDRAM Timing Configuration 1 */
+ unsigned int timing_cfg_2; /* SDRAM Timing Configuration 2 */
+ unsigned int sdram_cfg; /* SDRAM Control Configuration */
+ unsigned int sdram_cfg_2; /* SDRAM Control Configuration 2 */
+ unsigned int sdram_mode; /* SDRAM Mode Configuration */
+ unsigned int sdram_mode_2; /* SDRAM Mode Configuration 2 */
+ unsigned int sdram_md_cntl; /* SDRAM Mode Control */
+ unsigned int sdram_interval; /* SDRAM Interval Configuration */
+ unsigned int sdram_data_init; /* SDRAM Data initialization */
+ unsigned char res_12c[4];
+ unsigned int sdram_clk_cntl; /* SDRAM Clock Control */
+ unsigned char res_134[20];
+ unsigned int init_addr; /* training init addr */
+ unsigned int init_ext_addr; /* training init extended addr */
+ unsigned char res_150[16];
+ unsigned int timing_cfg_4; /* SDRAM Timing Configuration 4 */
+ unsigned int timing_cfg_5; /* SDRAM Timing Configuration 5 */
+ unsigned int timing_cfg_6; /* SDRAM Timing Configuration 6 */
+ unsigned int timing_cfg_7; /* SDRAM Timing Configuration 7 */
+ unsigned int zq_cntl; /* ZQ calibration control*/
+ unsigned int wrlvl_cntl; /* write leveling control*/
+ unsigned char reg_178[4];
+ unsigned int ddr_sr_cntr; /* self refresh counter */
+ unsigned int ddr_sdram_rcw_1; /* Control Words 1 */
+ unsigned int ddr_sdram_rcw_2; /* Control Words 2 */
+ unsigned char reg_188[8];
+ unsigned int ddr_wrlvl_cntl_2; /* write leveling control 2 */
+ unsigned int ddr_wrlvl_cntl_3; /* write leveling control 3 */
+ unsigned char res_198[0x1a0-0x198];
+ unsigned int ddr_sdram_rcw_3;
+ unsigned int ddr_sdram_rcw_4;
+ unsigned int ddr_sdram_rcw_5;
+ unsigned int ddr_sdram_rcw_6;
+ unsigned char res_1b0[0x200-0x1b0];
+ unsigned int sdram_mode_3; /* SDRAM Mode Configuration 3 */
+ unsigned int sdram_mode_4; /* SDRAM Mode Configuration 4 */
+ unsigned int sdram_mode_5; /* SDRAM Mode Configuration 5 */
+ unsigned int sdram_mode_6; /* SDRAM Mode Configuration 6 */
+ unsigned int sdram_mode_7; /* SDRAM Mode Configuration 7 */
+ unsigned int sdram_mode_8; /* SDRAM Mode Configuration 8 */
+ unsigned char res_218[0x220-0x218];
+ unsigned int sdram_mode_9; /* SDRAM Mode Configuration 9 */
+ unsigned int sdram_mode_10; /* SDRAM Mode Configuration 10 */
+ unsigned int sdram_mode_11; /* SDRAM Mode Configuration 11 */
+ unsigned int sdram_mode_12; /* SDRAM Mode Configuration 12 */
+ unsigned int sdram_mode_13; /* SDRAM Mode Configuration 13 */
+ unsigned int sdram_mode_14; /* SDRAM Mode Configuration 14 */
+ unsigned int sdram_mode_15; /* SDRAM Mode Configuration 15 */
+ unsigned int sdram_mode_16; /* SDRAM Mode Configuration 16 */
+ unsigned char res_240[0x250-0x240];
+ unsigned int timing_cfg_8; /* SDRAM Timing Configuration 8 */
+ unsigned int timing_cfg_9; /* SDRAM Timing Configuration 9 */
+ unsigned int timing_cfg_10; /* SDRAM Timing COnfigurtion 10 */
+ unsigned char res_258[0x260-0x25c];
+ unsigned int sdram_cfg_3;
+ unsigned char res_264[0x270-0x264];
+ unsigned int sdram_md_cntl_2;
+ unsigned char res_274[0x400-0x274];
+ unsigned int dq_map[4];
+ unsigned char res_410[0x800-0x410];
+ unsigned int tx_cfg[4];
+ unsigned char res_810[0xb20-0x810];
+ unsigned int ddr_dsr1; /* Debug Status 1 */
+ unsigned int ddr_dsr2; /* Debug Status 2 */
+ unsigned int ddr_cdr1; /* Control Driver 1 */
+ unsigned int ddr_cdr2; /* Control Driver 2 */
+ unsigned char res_b30[200];
+ unsigned int ip_rev1; /* IP Block Revision 1 */
+ unsigned int ip_rev2; /* IP Block Revision 2 */
+ unsigned int eor; /* Enhanced Optimization Register */
+ unsigned char res_c04[252];
+ unsigned int mtcr; /* Memory Test Control Register */
+ unsigned char res_d04[28];
+ unsigned int mtp[10]; /* Memory Test Patterns */
+ unsigned char res_d48[184];
+ unsigned int data_err_inject_hi; /* Data Path Err Injection Mask Hi*/
+ unsigned int data_err_inject_lo;/* Data Path Err Injection Mask Lo*/
+ unsigned int ecc_err_inject; /* Data Path Err Injection Mask ECC */
+ unsigned char res_e0c[20];
+ unsigned int capture_data_hi; /* Data Path Read Capture High */
+ unsigned int capture_data_lo; /* Data Path Read Capture Low */
+ unsigned int capture_ecc; /* Data Path Read Capture ECC */
+ unsigned char res_e2c[20];
+ unsigned int err_detect; /* Error Detect */
+ unsigned int err_disable; /* Error Disable */
+ unsigned int err_int_en;
+ unsigned int capture_attributes; /* Error Attrs Capture */
+ unsigned int capture_address; /* Error Addr Capture */
+ unsigned int capture_ext_address; /* Error Extended Addr Capture */
+ unsigned int err_sbe; /* Single-Bit ECC Error Management */
+ unsigned char res_e5c[164];
+ unsigned int debug[64]; /* debug_1 to debug_64 */
+};
+#endif /* DDR_IMMAP_H */
diff --git a/include/drivers/nxp/ddr/opts.h b/include/drivers/nxp/ddr/opts.h
new file mode 100644
index 0000000..f32891b
--- /dev/null
+++ b/include/drivers/nxp/ddr/opts.h
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DDR_OPTS_H
+#define DDR_OPTS_H
+
+#define SDRAM_TYPE_DDR4 5 /* sdram_cfg register */
+
+#define DDR_BC4 4 /* burst chop */
+#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
+#define DDR_BL8 8 /* burst length 8 */
+
+#define DDR4_RTT_OFF 0
+#define DDR4_RTT_60_OHM 1 /* RZQ/4 */
+#define DDR4_RTT_120_OHM 2 /* RZQ/2 */
+#define DDR4_RTT_40_OHM 3 /* RZQ/6 */
+#define DDR4_RTT_240_OHM 4 /* RZQ/1 */
+#define DDR4_RTT_48_OHM 5 /* RZQ/5 */
+#define DDR4_RTT_80_OHM 6 /* RZQ/3 */
+#define DDR4_RTT_34_OHM 7 /* RZQ/7 */
+#define DDR4_RTT_WR_OFF 0
+#define DDR4_RTT_WR_120_OHM 1
+#define DDR4_RTT_WR_240_OHM 2
+#define DDR4_RTT_WR_HZ 3
+#define DDR4_RTT_WR_80_OHM 4
+#define DDR_ODT_NEVER 0x0
+#define DDR_ODT_CS 0x1
+#define DDR_ODT_ALL_OTHER_CS 0x2
+#define DDR_ODT_OTHER_DIMM 0x3
+#define DDR_ODT_ALL 0x4
+#define DDR_ODT_SAME_DIMM 0x5
+#define DDR_ODT_CS_AND_OTHER_DIMM 0x6
+#define DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7
+#define DDR_BA_INTLV_CS01 0x40
+#define DDR_BA_INTLV_CS0123 0x64
+#define DDR_BA_NONE 0
+#define DDR_256B_INTLV 0x8
+
+struct memctl_opt {
+ int rdimm;
+ unsigned int dbw_cap_shift;
+ struct local_opts_s {
+ unsigned int auto_precharge;
+ unsigned int odt_rd_cfg;
+ unsigned int odt_wr_cfg;
+ unsigned int odt_rtt_norm;
+ unsigned int odt_rtt_wr;
+ } cs_odt[DDRC_NUM_CS];
+ int ctlr_intlv;
+ unsigned int ctlr_intlv_mode;
+ unsigned int ba_intlv;
+ int addr_hash;
+ int ecc_mode;
+ int ctlr_init_ecc;
+ int self_refresh_in_sleep;
+ int self_refresh_irq_en;
+ int dynamic_power;
+ /* memory data width 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */
+ unsigned int data_bus_dimm;
+ unsigned int data_bus_used; /* on individual board */
+ unsigned int burst_length; /* BC4, OTF and BL8 */
+ int otf_burst_chop_en;
+ int mirrored_dimm;
+ int quad_rank_present;
+ int output_driver_impedance;
+ int ap_en;
+ int x4_en;
+
+ int caslat_override;
+ unsigned int caslat_override_value;
+ int addt_lat_override;
+ unsigned int addt_lat_override_value;
+
+ unsigned int clk_adj;
+ unsigned int cpo_sample;
+ unsigned int wr_data_delay;
+
+ unsigned int cswl_override;
+ unsigned int wrlvl_override;
+ unsigned int wrlvl_sample;
+ unsigned int wrlvl_start;
+ unsigned int wrlvl_ctl_2;
+ unsigned int wrlvl_ctl_3;
+
+ int half_strength_drive_en;
+ int twot_en;
+ int threet_en;
+ unsigned int bstopre;
+ unsigned int tfaw_ps;
+
+ int rtt_override;
+ unsigned int rtt_override_value;
+ unsigned int rtt_wr_override_value;
+ unsigned int rtt_park;
+
+ int auto_self_refresh_en;
+ unsigned int sr_it;
+ unsigned int ddr_cdr1;
+ unsigned int ddr_cdr2;
+
+ unsigned int trwt_override;
+ unsigned int trwt;
+ unsigned int twrt;
+ unsigned int trrt;
+ unsigned int twwt;
+
+ unsigned int vref_phy;
+ unsigned int vref_dimm;
+ unsigned int odt;
+ unsigned int phy_tx_impedance;
+ unsigned int phy_atx_impedance;
+ unsigned int skip2d;
+};
+
+#endif /* DDR_OPTS_H */
diff --git a/include/drivers/nxp/ddr/regs.h b/include/drivers/nxp/ddr/regs.h
new file mode 100644
index 0000000..e85fd8f
--- /dev/null
+++ b/include/drivers/nxp/ddr/regs.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DDR_REG_H
+#define DDR_REG_H
+
+#define SDRAM_CS_CONFIG_EN 0x80000000
+
+/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration
+ */
+#define SDRAM_CFG_MEM_EN 0x80000000
+#define SDRAM_CFG_SREN 0x40000000
+#define SDRAM_CFG_ECC_EN 0x20000000
+#define SDRAM_CFG_RD_EN 0x10000000
+#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
+#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
+#define SDRAM_CFG_DYN_PWR 0x00200000
+#define SDRAM_CFG_DBW_MASK 0x00180000
+#define SDRAM_CFG_DBW_SHIFT 19
+#define SDRAM_CFG_32_BW 0x00080000
+#define SDRAM_CFG_16_BW 0x00100000
+#define SDRAM_CFG_8_BW 0x00180000
+#define SDRAM_CFG_8_BE 0x00040000
+#define SDRAM_CFG_2T_EN 0x00008000
+#define SDRAM_CFG_MEM_HLT 0x00000002
+#define SDRAM_CFG_BI 0x00000001
+
+#define SDRAM_CFG2_FRC_SR 0x80000000
+#define SDRAM_CFG2_FRC_SR_CLEAR ~(SDRAM_CFG2_FRC_SR)
+#define SDRAM_CFG2_D_INIT 0x00000010
+#define SDRAM_CFG2_AP_EN 0x00000020
+#define SDRAM_CFG2_ODT_ONLY_READ 2
+
+#define SDRAM_CFG3_DDRC_RST 0x80000000
+
+#define SDRAM_INTERVAL_REFINT 0xFFFF0000
+#define SDRAM_INTERVAL_REFINT_CLEAR ~(SDRAM_INTERVAL_REFINT)
+#define SDRAM_INTERVAL_BSTOPRE 0x3FFF
+
+/* DDR_MD_CNTL */
+#define MD_CNTL_MD_EN 0x80000000
+#define MD_CNTL_CS_SEL(x) (((x) & 0x7) << 28)
+#define MD_CNTL_MD_SEL(x) (((x) & 0xf) << 24)
+#define MD_CNTL_CKE(x) (((x) & 0x3) << 20)
+
+/* DDR_CDR1 */
+#define DDR_CDR1_DHC_EN 0x80000000
+#define DDR_CDR1_ODT_SHIFT 17
+#define DDR_CDR1_ODT_MASK 0x6
+#define DDR_CDR2_ODT_MASK 0x1
+#define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT)
+#define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
+#define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8))
+#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
+#define DDR_CDR2_VREF_RANGE_2 0x00000040
+#define DDR_CDR_ODT_OFF 0x0
+#define DDR_CDR_ODT_100ohm 0x1
+#define DDR_CDR_ODT_120OHM 0x2
+#define DDR_CDR_ODT_80ohm 0x3
+#define DDR_CDR_ODT_60ohm 0x4
+#define DDR_CDR_ODT_40ohm 0x5
+#define DDR_CDR_ODT_50ohm 0x6
+#define DDR_CDR_ODT_30ohm 0x7
+
+
+/* DDR ERR_DISABLE */
+#define DDR_ERR_DISABLE_APED (1 << 8) /* Address parity error disable */
+#define DDR_ERR_DISABLE_SBED (1 << 2) /* Address parity error disable */
+#define DDR_ERR_DISABLE_MBED (1 << 3) /* Address parity error disable */
+
+/* Mode Registers */
+#define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */
+#define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */
+
+/* DDR DSR2 register */
+#define DDR_DSR_2_PHY_INIT_CMPLT 0x4
+
+/* SDRAM TIMING_CFG_10 register */
+#define DDR_TIMING_CFG_10_T_STAB 0x7FFF
+
+/* DEBUG 2 register */
+#define DDR_DBG_2_MEM_IDLE 0x00000002
+
+/* DEBUG 26 register */
+#define DDR_DEBUG_26_BIT_6 (0x1 << 6)
+#define DDR_DEBUG_26_BIT_7 (0x1 << 7)
+#define DDR_DEBUG_26_BIT_12 (0x1 << 12)
+#define DDR_DEBUG_26_BIT_13 (0x1 << 13)
+#define DDR_DEBUG_26_BIT_14 (0x1 << 14)
+#define DDR_DEBUG_26_BIT_15 (0x1 << 15)
+#define DDR_DEBUG_26_BIT_16 (0x1 << 16)
+#define DDR_DEBUG_26_BIT_17 (0x1 << 17)
+#define DDR_DEBUG_26_BIT_18 (0x1 << 18)
+#define DDR_DEBUG_26_BIT_19 (0x1 << 19)
+#define DDR_DEBUG_26_BIT_24 (0x1 << 24)
+#define DDR_DEBUG_26_BIT_25 (0x1 << 25)
+
+#define DDR_DEBUG_26_BIT_24_CLEAR ~(DDR_DEBUG_26_BIT_24)
+
+/* DEBUG_29 register */
+#define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */
+
+#define DDR_INIT_ADDR_EXT_UIA (1 << 31)
+
+#endif /* DDR_REG_H */
diff --git a/include/drivers/nxp/ddr/utility.h b/include/drivers/nxp/ddr/utility.h
new file mode 100644
index 0000000..2e22ad5
--- /dev/null
+++ b/include/drivers/nxp/ddr/utility.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef UTILITY_H
+#define UTILITY_H
+
+#include <dcfg.h>
+
+#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
+#define CCN_HN_F_SAM_CTL 0x8
+#define CCN_HN_F_REGION_SIZE 0x10000
+#endif
+
+unsigned long get_ddr_freq(struct sysinfo *sys, int ctrl_num);
+unsigned int get_memory_clk_ps(unsigned long clk);
+unsigned int picos_to_mclk(unsigned long data_rate, unsigned int picos);
+unsigned int get_ddrc_version(const struct ccsr_ddr *ddr);
+void print_ddr_info(struct ccsr_ddr *ddr);
+
+#endif
diff --git a/include/drivers/nxp/flexspi/flash_info.h b/include/drivers/nxp/flexspi/flash_info.h
new file mode 100644
index 0000000..6df79c9
--- /dev/null
+++ b/include/drivers/nxp/flexspi/flash_info.h
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright 2020 NXP
+ */
+
+/**
+ * @Flash info
+ *
+ */
+#ifndef FLASH_INFO_H
+#define FLASH_INFO_H
+
+#define SZ_16M_BYTES 0x1000000U
+
+#if defined(CONFIG_MT25QU512A)
+#define F_SECTOR_64K 0x10000U
+#define F_PAGE_256 0x100U
+#define F_SECTOR_4K 0x1000U
+#define F_FLASH_SIZE_BYTES 0x4000000U
+#define F_SECTOR_ERASE_SZ F_SECTOR_64K
+#ifdef CONFIG_FSPI_4K_ERASE
+#define F_SECTOR_ERASE_SZ F_SECTOR_4K
+#endif
+
+#elif defined(CONFIG_MX25U25645G)
+#define F_SECTOR_64K 0x10000U
+#define F_PAGE_256 0x100U
+#define F_SECTOR_4K 0x1000U
+#define F_FLASH_SIZE_BYTES 0x2000000U
+#define F_SECTOR_ERASE_SZ F_SECTOR_64K
+#ifdef CONFIG_FSPI_4K_ERASE
+#define F_SECTOR_ERASE_SZ F_SECTOR_4K
+#endif
+
+#elif defined(CONFIG_MX25U51245G)
+#define F_SECTOR_64K 0x10000U
+#define F_PAGE_256 0x100U
+#define F_SECTOR_4K 0x1000U
+#define F_FLASH_SIZE_BYTES 0x4000000U
+#define F_SECTOR_ERASE_SZ F_SECTOR_64K
+#ifdef CONFIG_FSPI_4K_ERASE
+#define F_SECTOR_ERASE_SZ F_SECTOR_4K
+#endif
+
+#elif defined(CONFIG_MT35XU512A)
+#define F_SECTOR_128K 0x20000U
+#define F_SECTOR_32K 0x8000U
+#define F_PAGE_256 0x100U
+#define F_SECTOR_4K 0x1000U
+#define F_FLASH_SIZE_BYTES 0x4000000U
+#define F_SECTOR_ERASE_SZ F_SECTOR_128K
+#ifdef CONFIG_FSPI_4K_ERASE
+#define F_SECTOR_ERASE_SZ F_SECTOR_4K
+#endif
+
+#ifdef NXP_WARM_BOOT
+#define FLASH_WR_COMP_WAIT_BY_NOP_COUNT 0x20000
+#endif
+
+#endif
+#endif /* FLASH_INFO_H */
diff --git a/include/drivers/nxp/flexspi/fspi_api.h b/include/drivers/nxp/flexspi/fspi_api.h
new file mode 100644
index 0000000..d0de543
--- /dev/null
+++ b/include/drivers/nxp/flexspi/fspi_api.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+
+/*!
+ * @file fspi_api.h
+ * @brief This file contains the FlexSPI/FSPI API to communicate
+ * to attached Slave device.
+ * @addtogroup FSPI_API
+ * @{
+ */
+
+#ifndef FSPI_API_H
+#define FSPI_API_H
+
+#if DEBUG_FLEXSPI
+#define SZ_57M 0x3900000u
+#endif
+
+/*!
+ * Basic set of APIs.
+ */
+
+/*!
+ * @details AHB read/IP Read, decision to be internal to API
+ * Minimum Read size = 1Byte
+ * @param[in] src_off source offset from where data to read from flash
+ * @param[out] des Destination location where data needs to be copied
+ * @param[in] len length in Bytes,where 1-word=4-bytes/32-bits
+ *
+ * @return XSPI_SUCCESS or error code
+ */
+int xspi_read(uint32_t src_off, uint32_t *des, uint32_t len);
+/*!
+ * @details Sector erase, Minimum size
+ * 256KB(0x40000)/128KB(0x20000)/64K(0x10000)/4K(0x1000)
+ * depending upon flash, Calls xspi_wren() internally
+ * @param[out] erase_offset Destination erase location on flash which
+ * has to be erased, needs to be multiple of 0x40000/0x20000/0x10000
+ * @param[in] erase_len length in bytes in Hex like 0x100000 for 1MB, minimum
+ * erase size is 1 sector(0x40000/0x20000/0x10000)
+ *
+ * @return XSPI_SUCCESS or error code
+ */
+int xspi_sector_erase(uint32_t erase_offset, uint32_t erase_len);
+/*!
+ * @details IP write, For writing data to flash, calls xspi_wren() internally.
+ * Single/multiple page write can start @any offset, but performance will be low
+ * due to ERRATA
+ * @param[out] dst_off Destination location on flash where data needs to
+ * be written
+ * @param[in] src source offset from where data to be read
+ * @param[in] len length in bytes,where 1-word=4-bytes/32-bits
+ *
+ * @return XSPI_SUCCESS or error code
+ */
+int xspi_write(uint32_t dst_off, void *src, uint32_t len);
+/*!
+ * @details fspi_init, Init function.
+ * @param[in] uint32_t base_reg_addr
+ * @param[in] uint32_t flash_start_addr
+ *
+ * @return XSPI_SUCCESS or error code
+ */
+int fspi_init(uint32_t base_reg_addr, uint32_t flash_start_addr);
+/*!
+ * @details is_flash_busy, Check if any erase or write or lock is
+ * pending on flash/slave
+ * @param[in] void
+ *
+ * @return TRUE/FLASE
+ */
+bool is_flash_busy(void);
+
+/*!
+ * Advanced set of APIs.
+ */
+
+/*!
+ * @details Write enable, to be used by advance users only.
+ * Step 1 for sending write commands to flash.
+ * @param[in] dst_off destination offset where data will be written
+ *
+ * @return XSPI_SUCCESS or error code
+ */
+int xspi_wren(uint32_t dst_off);
+/*!
+ * @details AHB read, meaning direct memory mapped access to flash,
+ * Minimum Read size = 1Byte
+ * @param[in] src_off source offset from where data to read from flash,
+ * needs to be word aligned
+ * @param[out] des Destination location where data needs to be copied
+ * @param[in] len length in Bytes,where 1-word=4-bytes/32-bits
+ *
+ * @return XSPI_SUCCESS or error code
+ */
+int xspi_ahb_read(uint32_t src_off, uint32_t *des, uint32_t len);
+/*!
+ * @details IP read, READ via RX buffer from flash, minimum READ size = 1Byte
+ * @param[in] src_off source offset from where data to be read from flash
+ * @param[out] des Destination location where data needs to be copied
+ * @param[in] len length in Bytes,where 1-word=4-bytes/32-bits
+ *
+ * @return XSPI_SUCCESS or error code
+ */
+int xspi_ip_read(uint32_t src_off, uint32_t *des, uint32_t len);
+/*!
+ * @details CHIP erase, Erase complete chip in one go
+ *
+ * @return XSPI_SUCCESS or error code
+ */
+int xspi_bulk_erase(void);
+
+/*!
+ * Add test cases to confirm flash read/erase/write functionality.
+ */
+void fspi_test(uint32_t fspi_test_addr, uint32_t size, int extra);
+#endif /* FSPI_API_H */
diff --git a/include/drivers/nxp/flexspi/xspi_error_codes.h b/include/drivers/nxp/flexspi/xspi_error_codes.h
new file mode 100644
index 0000000..18b31eb
--- /dev/null
+++ b/include/drivers/nxp/flexspi/xspi_error_codes.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/* error codes */
+#ifndef XSPI_ERROR_CODES_H
+#define XSPI_ERROR_CODES_H
+
+#include <errno.h>
+
+typedef enum {
+ XSPI_SUCCESS = 0,
+ XSPI_READ_FAIL = ELAST + 1,
+ XSPI_ERASE_FAIL,
+ XSPI_IP_READ_FAIL,
+ XSPI_AHB_READ_FAIL,
+ XSPI_IP_WRITE_FAIL,
+ XSPI_AHB_WRITE_FAIL,
+ XSPI_BLOCK_TIMEOUT,
+ XSPI_UNALIGN_ADDR,
+ XSPI_UNALIGN_SIZE,
+} XSPI_STATUS_CODES;
+#undef ELAST
+#define ELAST XSPI_STATUS_CODES.XSPI_UNALIGN_SIZE
+#endif
diff --git a/include/drivers/nxp/gic/gicv2/plat_gic.h b/include/drivers/nxp/gic/gicv2/plat_gic.h
new file mode 100644
index 0000000..ff34744
--- /dev/null
+++ b/include/drivers/nxp/gic/gicv2/plat_gic.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PLAT_GICV2_H
+#define PLAT_GICV2_H
+
+#include <drivers/arm/gicv2.h>
+
+ /* register offsets */
+#define GICD_CTLR_OFFSET 0x0
+#define GICD_CPENDSGIR3_OFFSET 0xF1C
+#define GICD_SPENDSGIR3_OFFSET 0xF2C
+#define GICD_SGIR_OFFSET 0xF00
+#define GICD_IGROUPR0_OFFSET 0x080
+#define GICD_TYPER_OFFSET 0x0004
+#define GICD_ISENABLER0_OFFSET 0x0100
+#define GICD_ICENABLER0_OFFSET 0x0180
+#define GICD_IPRIORITYR3_OFFSET 0x040C
+#define GICD_ISENABLERn_OFFSET 0x0100
+#define GICD_ISACTIVER0_OFFSET 0x300
+
+#define GICC_CTLR_OFFSET 0x0
+#define GICC_PMR_OFFSET 0x0004
+#define GICC_IAR_OFFSET 0x000C
+#define GICC_DIR_OFFSET 0x1000
+#define GICC_EOIR_OFFSET 0x0010
+
+ /* bitfield masks */
+#define GICC_CTLR_EN_GRP0 0x1
+#define GICC_CTLR_EN_GRP1 0x2
+#define GICC_CTLR_EOImodeS_MASK 0x200
+#define GICC_CTLR_DIS_BYPASS 0x60
+#define GICC_CTLR_CBPR_MASK 0x10
+#define GICC_CTLR_FIQ_EN_MASK 0x8
+#define GICC_CTLR_ACKCTL_MASK 0x4
+#define GICC_PMR_FILTER 0xFF
+
+#define GICD_CTLR_EN_GRP0 0x1
+#define GICD_CTLR_EN_GRP1 0x2
+#define GICD_IGROUP0_SGI15 0x8000
+#define GICD_ISENABLE0_SGI15 0x8000
+#define GICD_ICENABLE0_SGI15 0x8000
+#define GICD_ISACTIVER0_SGI15 0x8000
+#define GICD_CPENDSGIR_CLR_MASK 0xFF000000
+#define GICD_IPRIORITY_SGI15_MASK 0xFF000000
+#define GICD_SPENDSGIR3_SGI15_MASK 0xFF000000
+#define GICD_SPENDSGIR3_SGI15_OFFSET 0x18
+
+#ifndef __ASSEMBLER__
+
+/* GIC common API's */
+void plat_ls_gic_driver_init(const uintptr_t nxp_gicd_addr,
+ const uintptr_t nxp_gicc_addr,
+ uint8_t plat_core_count,
+ interrupt_prop_t *ls_interrupt_props,
+ uint8_t ls_interrupt_prop_count,
+ uint32_t *target_mask_array);
+void plat_ls_gic_init(void);
+void plat_ls_gic_cpuif_enable(void);
+void plat_ls_gic_cpuif_disable(void);
+void plat_ls_gic_redistif_on(void);
+void plat_ls_gic_redistif_off(void);
+void plat_gic_pcpu_init(void);
+/* GIC utility functions */
+void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base);
+#endif
+
+#endif /* PLAT_GICV2_H */
diff --git a/include/drivers/nxp/gic/gicv3/plat_gic.h b/include/drivers/nxp/gic/gicv3/plat_gic.h
new file mode 100644
index 0000000..f4e12de
--- /dev/null
+++ b/include/drivers/nxp/gic/gicv3/plat_gic.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PLAT_GICV3_H
+#define PLAT_GICV3_H
+
+#include <drivers/arm/gicv3.h>
+
+ /* offset between redistributors */
+#define GIC_RD_OFFSET 0x00020000
+ /* offset between SGI's */
+#define GIC_SGI_OFFSET 0x00020000
+ /* offset from rd base to sgi base */
+#define GIC_RD_2_SGI_OFFSET 0x00010000
+
+ /* register offsets */
+#define GICD_CTLR_OFFSET 0x0
+#define GICD_CLR_SPI_SR 0x58
+#define GICD_IGROUPR_2 0x88
+#define GICD_ISENABLER_2 0x108
+#define GICD_ICENABLER_2 0x188
+#define GICD_ICPENDR_2 0x288
+#define GICD_ICACTIVER_2 0x388
+#define GICD_IPRIORITYR_22 0x458
+#define GICD_ICFGR_5 0xC14
+#define GICD_IGRPMODR_2 0xD08
+
+#define GICD_IROUTER60_OFFSET 0x61e0
+#define GICD_IROUTER76_OFFSET 0x6260
+#define GICD_IROUTER89_OFFSET 0x62C8
+#define GICD_IROUTER112_OFFSET 0x6380
+#define GICD_IROUTER113_OFFSET 0x6388
+
+#define GICR_ICENABLER0_OFFSET 0x180
+#define GICR_CTLR_OFFSET 0x0
+#define GICR_IGROUPR0_OFFSET 0x80
+#define GICR_IGRPMODR0_OFFSET 0xD00
+#define GICR_IPRIORITYR3_OFFSET 0x40C
+#define GICR_ICPENDR0_OFFSET 0x280
+#define GICR_ISENABLER0_OFFSET 0x100
+#define GICR_TYPER_OFFSET 0x8
+#define GICR_WAKER_OFFSET 0x14
+#define GICR_ICACTIVER0_OFFSET 0x380
+#define GICR_ICFGR0_OFFSET 0xC00
+
+ /* bitfield masks */
+#define GICD_CTLR_EN_GRP_MASK 0x7
+#define GICD_CTLR_EN_GRP_1NS 0x2
+#define GICD_CTLR_EN_GRP_1S 0x4
+#define GICD_CTLR_EN_GRP_0 0x1
+#define GICD_CTLR_ARE_S_MASK 0x10
+#define GICD_CTLR_RWP 0x80000000
+
+#define GICR_ICENABLER0_SGI15 0x00008000
+#define GICR_CTLR_RWP 0x8
+#define GICR_CTLR_DPG0_MASK 0x2000000
+#define GICR_IGROUPR0_SGI15 0x00008000
+#define GICR_IGRPMODR0_SGI15 0x00008000
+#define GICR_ISENABLER0_SGI15 0x00008000
+#define GICR_IPRIORITYR3_SGI15_MASK 0xFF000000
+#define GICR_ICPENDR0_SGI15 0x8000
+
+#define GIC_SPI_89_MASK 0x02000000
+#define GIC_SPI89_PRIORITY_MASK 0xFF00
+#define GIC_IRM_SPI89 0x80000000
+
+#define GICD_IROUTER_VALUE 0x100
+#define GICR_WAKER_SLEEP_BIT 0x2
+#define GICR_WAKER_ASLEEP (1 << 2 | 1 << 1)
+
+#define ICC_SRE_EL3_SRE 0x1
+#define ICC_IGRPEN0_EL1_EN 0x1
+#define ICC_CTLR_EL3_CBPR_EL1S 0x1
+#define ICC_CTLR_EL3_RM 0x20
+#define ICC_CTLR_EL3_EOIMODE_EL3 0x4
+#define ICC_CTLR_EL3_PMHE 0x40
+#define ICC_PMR_EL1_P_FILTER 0xFF
+#define ICC_IAR0_EL1_SGI15 0xF
+#define ICC_SGI0R_EL1_INTID 0x0F000000
+#define ICC_IAR0_INTID_SPI_89 0x59
+
+#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
+#define ICC_PMR_EL1 S3_0_C4_C6_0
+#define ICC_SRE_EL3 S3_6_C12_C12_5
+#define ICC_CTLR_EL3 S3_6_C12_C12_4
+#define ICC_SRE_EL2 S3_4_C12_C9_5
+#define ICC_CTLR_EL1 S3_0_C12_C12_4
+
+#ifndef __ASSEMBLER__
+
+/* GIC common API's */
+typedef unsigned int (*my_core_pos_fn)(void);
+
+void plat_ls_gic_driver_init(const uintptr_t nxp_gicd_addr,
+ const uintptr_t nxp_gicr_addr,
+ uint8_t plat_core_count,
+ interrupt_prop_t *ls_interrupt_props,
+ uint8_t ls_interrupt_prop_count,
+ uintptr_t *target_mask_array,
+ mpidr_hash_fn mpidr_to_core_pos);
+//void plat_ls_gic_driver_init(void);
+void plat_ls_gic_init(void);
+void plat_ls_gic_cpuif_enable(void);
+void plat_ls_gic_cpuif_disable(void);
+void plat_ls_gic_redistif_on(void);
+void plat_ls_gic_redistif_off(void);
+void plat_gic_pcpu_init(void);
+#endif
+
+#endif /* PLAT_GICV3_H */
diff --git a/include/drivers/nxp/gpio/nxp_gpio.h b/include/drivers/nxp/gpio/nxp_gpio.h
new file mode 100644
index 0000000..df75840
--- /dev/null
+++ b/include/drivers/nxp/gpio/nxp_gpio.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PLAT_GPIO_H
+#define PLAT_GPIO_H
+
+#include <endian.h>
+#include <lib/mmio.h>
+
+/* GPIO Register offset */
+#define GPIO_SEL_MASK 0x7F
+#define GPIO_BIT_MASK 0x1F
+#define GPDIR_REG_OFFSET 0x0
+#define GPDAT_REG_OFFSET 0x8
+
+#define GPIO_ID_BASE_ADDR_SHIFT 5U
+#define GPIO_BITS_PER_BASE_REG 32U
+
+#define GPIO_0 0
+#define GPIO_1 1
+#define GPIO_2 2
+#define GPIO_3 3
+
+#define GPIO_SUCCESS 0x0
+#define GPIO_FAILURE 0x1
+
+#ifdef NXP_GPIO_BE
+#define gpio_read32(a) bswap32(mmio_read_32((uintptr_t)(a)))
+#define gpio_write32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
+#elif defined(NXP_GPIO_LE)
+#define gpio_read32(a) mmio_read_32((uintptr_t)(a))
+#define gpio_write32(a, v) mmio_write_32((uintptr_t)(a), (v))
+#else
+#error Please define GPIO register endianness
+#endif
+
+typedef struct {
+ uintptr_t gpio1_base_addr;
+ uintptr_t gpio2_base_addr;
+ uintptr_t gpio3_base_addr;
+ uintptr_t gpio4_base_addr;
+} gpio_init_info_t;
+
+void gpio_init(gpio_init_info_t *gpio_init_data);
+uint32_t *select_gpio_n_bitnum(uint32_t povdd_gpio, uint32_t *bit_num);
+int clr_gpio_bit(uint32_t *gpio_base_addr, uint32_t bit_num);
+int set_gpio_bit(uint32_t *gpio_base_addr, uint32_t bit_num);
+
+#endif /* PLAT_GPIO_H */
diff --git a/include/drivers/nxp/i2c/i2c.h b/include/drivers/nxp/i2c/i2c.h
new file mode 100644
index 0000000..85e6eb4
--- /dev/null
+++ b/include/drivers/nxp/i2c/i2c.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2016-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+
+#ifndef I2C_H
+#define I2C_H
+
+#include <lib/mmio.h>
+
+#define I2C_TIMEOUT 1000 /* ms */
+
+#define I2C_FD_CONSERV 0x7e
+#define I2C_CR_DIS (1 << 7)
+#define I2C_CR_EN (0 << 7)
+#define I2C_CR_MA (1 << 5)
+#define I2C_CR_TX (1 << 4)
+#define I2C_CR_TX_NAK (1 << 3)
+#define I2C_CR_RSTA (1 << 2)
+#define I2C_SR_BB (1 << 5)
+#define I2C_SR_IDLE (0 << 5)
+#define I2C_SR_AL (1 << 4)
+#define I2C_SR_IF (1 << 1)
+#define I2C_SR_RX_NAK (1 << 0)
+#define I2C_SR_RST (I2C_SR_AL | I2C_SR_IF)
+
+#define I2C_GLITCH_EN 0x8
+
+#define i2c_in(a) mmio_read_8((uintptr_t)(a))
+#define i2c_out(a, v) mmio_write_8((uintptr_t)(a), (v))
+
+struct ls_i2c {
+ unsigned char ad; /* I2c Bus Address Register */
+ unsigned char fd; /* I2c Bus Frequency Dividor Register */
+ unsigned char cr; /* I2c Bus Control Register */
+ unsigned char sr; /* I2c Bus Status Register */
+ unsigned char dr; /* I2C Bus Data I/O Register */
+ unsigned char ic; /* I2C Bus Interrupt Config Register */
+ unsigned char dbg; /* I2C Bus Debug Register */
+};
+
+void i2c_init(uintptr_t nxp_i2c_addr);
+int i2c_read(unsigned char chip, int addr, int alen,
+ unsigned char *buf, int len);
+int i2c_write(unsigned char chip, int addr, int alen,
+ const unsigned char *buf, int len);
+int i2c_probe_chip(unsigned char chip);
+
+#endif /* I2C_H */
diff --git a/include/drivers/nxp/interconnect/ls_interconnect.h b/include/drivers/nxp/interconnect/ls_interconnect.h
new file mode 100644
index 0000000..777089c
--- /dev/null
+++ b/include/drivers/nxp/interconnect/ls_interconnect.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2020-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef LS_INTERCONNECT_H
+#define LS_INTERCONNECT_H
+
+#if (INTERCONNECT == CCI400)
+#define CCI_TERMINATE_BARRIER_TX 0x8
+#endif
+
+/* Interconnect CCI/CCN functions */
+void plat_ls_interconnect_enter_coherency(unsigned int num_clusters);
+void plat_ls_interconnect_exit_coherency(void);
+
+#endif
diff --git a/include/drivers/nxp/pmu/pmu.h b/include/drivers/nxp/pmu/pmu.h
new file mode 100644
index 0000000..28199e8
--- /dev/null
+++ b/include/drivers/nxp/pmu/pmu.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PMU_H
+#define PMU_H
+
+/* PMU Registers' OFFSET */
+#define PMU_PCPW20SR_OFFSET 0x830
+#define PMU_CLL2FLUSHSETR_OFFSET 0x1110
+#define PMU_CLSL2FLUSHCLRR_OFFSET 0x1114
+#define PMU_CLL2FLUSHSR_OFFSET 0x1118
+#define PMU_POWMGTCSR_VAL (1 << 20)
+
+/* PMU Registers */
+#define CORE_TIMEBASE_ENBL_OFFSET 0x8A0
+#define CLUST_TIMER_BASE_ENBL_OFFSET 0x18A0
+
+#define PMU_IDLE_CLUSTER_MASK 0x2
+#define PMU_FLUSH_CLUSTER_MASK 0x2
+#define PMU_IDLE_CORE_MASK 0xfe
+
+/* pmu register offsets and bitmaps */
+#define PMU_POWMGTDCR0_OFFSET 0xC20
+#define PMU_POWMGTCSR_OFFSET 0x4000
+#define PMU_CLAINACTSETR_OFFSET 0x1100
+#define PMU_CLAINACTCLRR_OFFSET 0x1104
+#define PMU_CLSINACTSETR_OFFSET 0x1108
+#define PMU_CLSINACTCLRR_OFFSET 0x110C
+#define PMU_CLL2FLUSHSETR_OFFSET 0x1110
+#define PMU_CLL2FLUSHCLRR_OFFSET 0x1114
+#define PMU_IPPDEXPCR0_OFFSET 0x4040
+#define PMU_IPPDEXPCR1_OFFSET 0x4044
+#define PMU_IPPDEXPCR2_OFFSET 0x4048
+#define PMU_IPPDEXPCR3_OFFSET 0x404C
+#define PMU_IPPDEXPCR4_OFFSET 0x4050
+#define PMU_IPPDEXPCR5_OFFSET 0x4054
+#define PMU_IPPDEXPCR6_OFFSET 0x4058
+#define PMU_IPSTPCR0_OFFSET 0x4120
+#define PMU_IPSTPCR1_OFFSET 0x4124
+#define PMU_IPSTPCR2_OFFSET 0x4128
+#define PMU_IPSTPCR3_OFFSET 0x412C
+#define PMU_IPSTPCR4_OFFSET 0x4130
+#define PMU_IPSTPCR5_OFFSET 0x4134
+#define PMU_IPSTPCR6_OFFSET 0x4138
+#define PMU_IPSTPACKSR0_OFFSET 0x4140
+#define PMU_IPSTPACKSR1_OFFSET 0x4144
+#define PMU_IPSTPACKSR2_OFFSET 0x4148
+#define PMU_IPSTPACKSR3_OFFSET 0x414C
+#define PMU_IPSTPACKSR4_OFFSET 0x4150
+#define PMU_IPSTPACKSR5_OFFSET 0x4154
+#define PMU_IPSTPACKSR6_OFFSET 0x4158
+
+#define CLAINACT_DISABLE_ACP 0xFF
+#define CLSINACT_DISABLE_SKY 0xFF
+#define POWMGTDCR_STP_OV_EN 0x1
+#define POWMGTCSR_LPM20_REQ 0x00100000
+
+/* Used by PMU */
+#define DEVDISR1_MASK 0x024F3504
+#define DEVDISR2_MASK 0x0003FFFF
+#define DEVDISR3_MASK 0x0000303F
+#define DEVDISR4_MASK 0x0000FFFF
+#define DEVDISR5_MASK 0x00F07603
+#define DEVDISR6_MASK 0x00000001
+
+#ifndef __ASSEMBLER__
+void enable_timer_base_to_cluster(uintptr_t nxp_pmu_addr);
+void enable_core_tb(uintptr_t nxp_pmu_addr);
+#endif /* __ASSEMBLER__ */
+
+#endif
diff --git a/include/drivers/nxp/qspi/qspi.h b/include/drivers/nxp/qspi/qspi.h
new file mode 100644
index 0000000..db11c3b
--- /dev/null
+++ b/include/drivers/nxp/qspi/qspi.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef QSPI_H
+#define QSPI_H
+
+#include <endian.h>
+#include <lib/mmio.h>
+
+#define CHS_QSPI_MCR 0x01550000
+#define CHS_QSPI_64LE 0xC
+
+#ifdef NXP_QSPI_BE
+#define qspi_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
+#define qspi_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
+#elif defined(NXP_QSPI_LE)
+#define qspi_in32(a) mmio_read_32((uintptr_t)(a))
+#define qspi_out32(a, v) mmio_write_32((uintptr_t)(a), (v))
+#else
+#error Please define CCSR QSPI register endianness
+#endif
+
+int qspi_io_setup(uintptr_t nxp_qspi_flash_addr,
+ size_t nxp_qspi_flash_size,
+ uintptr_t fip_offset);
+#endif /* __QSPI_H__ */
diff --git a/include/drivers/nxp/sd/sd_mmc.h b/include/drivers/nxp/sd/sd_mmc.h
new file mode 100644
index 0000000..32b41f1
--- /dev/null
+++ b/include/drivers/nxp/sd/sd_mmc.h
@@ -0,0 +1,337 @@
+/*
+ * Copyright (c) 2015, 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef SD_MMC_H
+#define SD_MMC_H
+
+#include <lib/mmio.h>
+
+/* operating freq */
+#define CARD_IDENTIFICATION_FREQ 400000
+#define SD_SS_25MHZ 20000000
+#define SD_HS_50MHZ 40000000
+#define MMC_SS_20MHZ 15000000
+#define MMC_HS_26MHZ 20000000
+#define MMC_HS_52MHZ 40000000
+
+/* Need to check this value ? */
+#define MAX_PLATFORM_CLOCK 800000000
+
+/* eSDHC system control register defines */
+#define ESDHC_SYSCTL_DTOCV(t) (((t) & 0xF) << 16)
+#define ESDHC_SYSCTL_SDCLKFS(f) (((f) & 0xFF) << 8)
+#define ESDHC_SYSCTL_DVS(d) (((d) & 0xF) << 4)
+#define ESDHC_SYSCTL_SDCLKEN (0x00000008)
+#define ESDHC_SYSCTL_RSTA (0x01000000)
+
+/* Data timeout counter value. SDHC_CLK x 227 */
+#define TIMEOUT_COUNTER_SDCLK_2_27 0xE
+#define ESDHC_SYSCTL_INITA 0x08000000
+
+/* eSDHC interrupt status enable register defines */
+#define ESDHC_IRQSTATEN_CINS 0x00000040
+#define ESDHC_IRQSTATEN_BWR 0x00000010
+
+/* eSDHC interrupt status register defines */
+#define ESDHC_IRQSTAT_DMAE (0x10000000)
+#define ESDHC_IRQSTAT_AC12E (0x01000000)
+#define ESDHC_IRQSTAT_DEBE (0x00400000)
+#define ESDHC_IRQSTAT_DCE (0x00200000)
+#define ESDHC_IRQSTAT_DTOE (0x00100000)
+#define ESDHC_IRQSTAT_CIE (0x00080000)
+#define ESDHC_IRQSTAT_CEBE (0x00040000)
+#define ESDHC_IRQSTAT_CCE (0x00020000)
+#define ESDHC_IRQSTAT_CTOE (0x00010000)
+#define ESDHC_IRQSTAT_CINT (0x00000100)
+#define ESDHC_IRQSTAT_CRM (0x00000080)
+#define ESDHC_IRQSTAT_CINS (0x00000040)
+#define ESDHC_IRQSTAT_BRR (0x00000020)
+#define ESDHC_IRQSTAT_BWR (0x00000010)
+#define ESDHC_IRQSTAT_DINT (0x00000008)
+#define ESDHC_IRQSTAT_BGE (0x00000004)
+#define ESDHC_IRQSTAT_TC (0x00000002)
+#define ESDHC_IRQSTAT_CC (0x00000001)
+#define ESDHC_IRQSTAT_CMD_ERR (ESDHC_IRQSTAT_CIE |\
+ ESDHC_IRQSTAT_CEBE |\
+ ESDHC_IRQSTAT_CCE)
+#define ESDHC_IRQSTAT_DATA_ERR (ESDHC_IRQSTAT_DEBE |\
+ ESDHC_IRQSTAT_DCE |\
+ ESDHC_IRQSTAT_DTOE)
+#define ESDHC_IRQSTAT_CLEAR_ALL (0xFFFFFFFF)
+
+/* eSDHC present state register defines */
+#define ESDHC_PRSSTAT_CLSL 0x00800000
+#define ESDHC_PRSSTAT_WPSPL 0x00080000
+#define ESDHC_PRSSTAT_CDPL 0x00040000
+#define ESDHC_PRSSTAT_CINS 0x00010000
+#define ESDHC_PRSSTAT_BREN 0x00000800
+#define ESDHC_PRSSTAT_BWEN 0x00000400
+#define ESDHC_PRSSTAT_RTA 0x00000200
+#define ESDHC_PRSSTAT_WTA 0x00000100
+#define ESDHC_PRSSTAT_SDOFF 0x00000080
+#define ESDHC_PRSSTAT_PEROFF 0x00000040
+#define ESDHC_PRSSTAT_HCKOFF 0x00000020
+#define ESDHC_PRSSTAT_IPGOFF 0x00000010
+#define ESDHC_PRSSTAT_DLA 0x00000004
+#define ESDHC_PRSSTAT_CDIHB 0x00000002
+#define ESDHC_PRSSTAT_CIHB 0x00000001
+
+/* eSDHC protocol control register defines */
+#define ESDHC_PROCTL_EMODE_LE 0x00000020
+#define ESDHC_PROCTL_DTW_1BIT 0x00000000
+#define ESDHC_PROCTL_DTW_4BIT 0x00000002
+#define ESDHC_PROCTL_DTW_8BIT 0x00000004
+
+/* Watermark Level Register (WML) */
+#define ESDHC_WML_RD_WML(w) ((w) & 0x7F)
+#define ESDHC_WML_WR_WML(w) (((w) & 0x7F) << 16)
+#define ESDHC_WML_RD_BRST(w) (((w) & 0xF) << 8)
+#define ESDHC_WML_WR_BRST(w) (((w) & 0xF) << 24)
+#define ESDHC_WML_WR_BRST_MASK (0x0F000000)
+#define ESDHC_WML_RD_BRST_MASK (0x00000F00)
+#define ESDHC_WML_RD_WML_MASK (0x0000007F)
+#define ESDHC_WML_WR_WML_MASK (0x007F0000)
+#define WML_512_BYTES (0x0)
+#define BURST_128_BYTES (0x0)
+
+/* eSDHC control register define */
+#define ESDHC_DCR_SNOOP 0x00000040
+
+/* ESDHC Block attributes register */
+#define ESDHC_BLKATTR_BLKCNT(c) (((c) & 0xffff) << 16)
+#define ESDHC_BLKATTR_BLKSZE(s) ((s) & 0xfff)
+
+/* Transfer Type Register */
+#define ESDHC_XFERTYP_CMD(c) (((c) & 0x3F) << 24)
+#define ESDHC_XFERTYP_CMDTYP_NORMAL (0x0)
+#define ESDHC_XFERTYP_CMDTYP_SUSPEND (0x00400000)
+#define ESDHC_XFERTYP_CMDTYP_RESUME (0x00800000)
+#define ESDHC_XFERTYP_CMDTYP_ABORT (0x00C00000)
+#define ESDHC_XFERTYP_DPSEL (0x00200000)
+#define ESDHC_XFERTYP_CICEN (0x00100000)
+#define ESDHC_XFERTYP_CCCEN (0x00080000)
+#define ESDHC_XFERTYP_RSPTYP_NONE (0x0)
+#define ESDHC_XFERTYP_RSPTYP_136 (0x00010000)
+#define ESDHC_XFERTYP_RSPTYP_48 (0x00020000)
+#define ESDHC_XFERTYP_RSPTYP_48_BUSY (0x00030000)
+#define ESDHC_XFERTYP_MSBSEL (0x00000020)
+#define ESDHC_XFERTYP_DTDSEL (0x00000010)
+#define ESDHC_XFERTYP_AC12EN (0x00000004)
+#define ESDHC_XFERTYP_BCEN (0x00000002)
+#define ESDHC_XFERTYP_DMAEN (0x00000001)
+
+#define MMC_VDD_HIGH_VOLTAGE 0x00000100
+
+/* command index */
+#define CMD0 0
+#define CMD1 1
+#define CMD2 2
+#define CMD3 3
+#define CMD5 5
+#define CMD6 6
+#define CMD7 7
+#define CMD8 8
+#define CMD9 9
+#define CMD12 12
+#define CMD13 13
+#define CMD14 14
+#define CMD16 16
+#define CMD17 17
+#define CMD18 18
+#define CMD19 19
+#define CMD24 24
+#define CMD41 41
+#define CMD42 42
+#define CMD51 51
+#define CMD55 55
+#define CMD56 56
+#define ACMD6 CMD6
+#define ACMD13 CMD13
+#define ACMD41 CMD41
+#define ACMD42 CMD42
+#define ACMD51 CMD51
+
+/* commands abbreviations */
+#define CMD_GO_IDLE_STATE CMD0
+#define CMD_MMC_SEND_OP_COND CMD1
+#define CMD_ALL_SEND_CID CMD2
+#define CMD_SEND_RELATIVE_ADDR CMD3
+#define CMD_SET_DSR CMD4
+#define CMD_SWITCH_FUNC CMD6
+#define CMD_SELECT_CARD CMD7
+#define CMD_DESELECT_CARD CMD7
+#define CMD_SEND_IF_COND CMD8
+#define CMD_MMC_SEND_EXT_CSD CMD8
+#define CMD_SEND_CSD CMD9
+#define CMD_SEND_CID CMD10
+#define CMD_STOP_TRANSMISSION CMD12
+#define CMD_SEND_STATUS CMD13
+#define CMD_BUS_TEST_R CMD14
+#define CMD_GO_INACTIVE_STATE CMD15
+#define CMD_SET_BLOCKLEN CMD16
+#define CMD_READ_SINGLE_BLOCK CMD17
+#define CMD_READ_MULTIPLE_BLOCK CMD18
+#define CMD_WRITE_SINGLE_BLOCK CMD24
+#define CMD_BUS_TEST_W CMD19
+#define CMD_APP_CMD CMD55
+#define CMD_GEN_CMD CMD56
+#define CMD_SET_BUS_WIDTH ACMD6
+#define CMD_SD_STATUS ACMD13
+#define CMD_SD_SEND_OP_COND ACMD41
+#define CMD_SET_CLR_CARD_DETECT ACMD42
+#define CMD_SEND_SCR ACMD51
+
+/* MMC card spec version */
+#define MMC_CARD_VERSION_1_2 0
+#define MMC_CARD_VERSION_1_4 1
+#define MMC_CARD_VERSION_2_X 2
+#define MMC_CARD_VERSION_3_X 3
+#define MMC_CARD_VERSION_4_X 4
+
+/* SD Card Spec Version */
+/* May need to add version 3 here? */
+#define SD_CARD_VERSION_1_0 0
+#define SD_CARD_VERSION_1_10 1
+#define SD_CARD_VERSION_2_0 2
+
+/* card types */
+#define MMC_CARD 0
+#define SD_CARD 1
+#define NOT_SD_CARD MMC_CARD
+
+/* Card rca */
+#define SD_MMC_CARD_RCA 0x1
+#define BLOCK_LEN_512 512
+
+/* card state */
+#define STATE_IDLE 0
+#define STATE_READY 1
+#define STATE_IDENT 2
+#define STATE_STBY 3
+#define STATE_TRAN 4
+#define STATE_DATA 5
+#define STATE_RCV 6
+#define STATE_PRG 7
+#define STATE_DIS 8
+
+/* Card OCR register */
+/* VDD voltage window 1,65 to 1.95 */
+#define MMC_OCR_VDD_165_195 0x00000080
+/* VDD voltage window 2.7-2.8 */
+#define MMC_OCR_VDD_FF8 0x00FF8000
+#define MMC_OCR_CCS 0x40000000/* Card Capacity */
+#define MMC_OCR_BUSY 0x80000000/* busy bit */
+#define SD_OCR_HCS 0x40000000/* High capacity host */
+#define MMC_OCR_SECTOR_MODE 0x40000000/* Access Mode as Sector */
+
+/* mmc Switch function */
+#define SET_EXT_CSD_HS_TIMING 0x03B90100/* set High speed */
+
+/* check supports switching or not */
+#define SD_SWITCH_FUNC_CHECK_MODE 0x00FFFFF1
+#define SD_SWITCH_FUNC_SWITCH_MODE 0x80FFFFF1/* switch */
+#define SD_SWITCH_FUNC_HIGH_SPEED 0x02/* HIGH SPEED FUNC */
+#define SWITCH_ERROR 0x00000080
+
+/* errors in sending commands */
+#define RESP_TIMEOUT 0x1
+#define COMMAND_ERROR 0x2
+/* error in response */
+#define R1_ERROR (1 << 19)
+#define R1_CURRENT_STATE(x) (((x) & 0x00001E00) >> 9)
+
+/* Host Controller Capabilities */
+#define ESDHC_HOSTCAPBLT_DMAS (0x00400000)
+
+
+/* SD/MMC memory map */
+struct esdhc_regs {
+ uint32_t dsaddr; /* dma system address */
+ uint32_t blkattr; /* Block attributes */
+ uint32_t cmdarg; /* Command argument */
+ uint32_t xfertyp; /* Command transfer type */
+ uint32_t cmdrsp[4]; /* Command response0,1,2,3 */
+ uint32_t datport; /* Data buffer access port */
+ uint32_t prsstat; /* Present state */
+ uint32_t proctl; /* Protocol control */
+ uint32_t sysctl; /* System control */
+ uint32_t irqstat; /* Interrupt status */
+ uint32_t irqstaten; /* Interrupt status enable */
+ uint32_t irqsigen; /* Interrupt signal enable */
+ uint32_t autoc12err; /* Auto CMD12 status */
+ uint32_t hostcapblt; /* Host controller capabilities */
+ uint32_t wml; /* Watermark level */
+ uint32_t res1[2];
+ uint32_t fevt; /* Force event */
+ uint32_t res2;
+ uint32_t adsaddrl;
+ uint32_t adsaddrh;
+ uint32_t res3[39];
+ uint32_t hostver; /* Host controller version */
+ uint32_t res4;
+ uint32_t dmaerr; /* DMA error address */
+ uint32_t dmaerrh; /* DMA error address high */
+ uint32_t dmaerrattr; /* DMA error atrribute */
+ uint32_t res5;
+ uint32_t hostcapblt2;/* Host controller capabilities2 */
+ uint32_t res6[2];
+ uint32_t tcr; /* Tuning control */
+ uint32_t res7[7];
+ uint32_t dirctrl; /* Direction control */
+ uint32_t ccr; /* Clock control */
+ uint32_t res8[177];
+ uint32_t ctl; /* Control register */
+};
+
+/* SD/MMC card attributes */
+struct card_attributes {
+ uint32_t type; /* sd or mmc card */
+ uint32_t version; /* version */
+ uint32_t block_len; /* block length */
+ uint32_t bus_freq; /* sdhc bus frequency */
+ uint16_t rca; /* relative card address */
+ uint8_t is_high_capacity; /* high capacity */
+};
+
+struct mmc {
+ struct esdhc_regs *esdhc_regs;
+ struct card_attributes card;
+
+ uint32_t block_len;
+ uint32_t voltages_caps; /* supported voltaes */
+ uint32_t dma_support; /* DMA support */
+};
+
+enum cntrl_num {
+ SDHC1 = 0,
+ SDHC2
+};
+
+int sd_emmc_init(uintptr_t *block_dev_spec,
+ uintptr_t nxp_esdhc_addr,
+ size_t nxp_sd_block_offset,
+ size_t nxp_sd_block_size,
+ bool card_detect);
+
+int esdhc_emmc_init(struct mmc *mmc, bool card_detect);
+int esdhc_read(struct mmc *mmc, uint32_t src_offset, uintptr_t dst,
+ size_t size);
+int esdhc_write(struct mmc *mmc, uintptr_t src, uint32_t dst_offset,
+ size_t size);
+
+#ifdef NXP_ESDHC_BE
+#define esdhc_in32(a) bswap32(mmio_read_32((uintptr_t)(a)))
+#define esdhc_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
+#elif defined(NXP_ESDHC_LE)
+#define esdhc_in32(a) mmio_read_32((uintptr_t)(a))
+#define esdhc_out32(a, v) mmio_write_32((uintptr_t)(a), (v))
+#else
+#error Please define CCSR ESDHC register endianness
+#endif
+
+#endif /*SD_MMC_H*/
diff --git a/include/drivers/nxp/sec_mon/snvs.h b/include/drivers/nxp/sec_mon/snvs.h
new file mode 100644
index 0000000..4455383
--- /dev/null
+++ b/include/drivers/nxp/sec_mon/snvs.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef SNVS_H
+#define SNVS_H
+
+
+#ifndef __ASSEMBLER__
+
+#include <endian.h>
+#include <stdbool.h>
+
+#include <lib/mmio.h>
+
+struct snvs_regs {
+ uint32_t reserved1;
+ uint32_t hp_com; /* 0x04 SNVS_HP Command Register */
+ uint32_t reserved2[3];
+ uint32_t hp_stat; /* 0x14 SNVS_HP Status Register */
+};
+
+#ifdef NXP_SNVS_BE
+#define snvs_read32(a) bswap32(mmio_read_32((uintptr_t)(a)))
+#define snvs_write32(a, v) mmio_write_32((uintptr_t)(a), bswap32((v)))
+#elif defined(NXP_SNVS_LE)
+#define snvs_read32(a) mmio_read_32((uintptr_t)(a))
+#define snvs_write32(a, v) mmio_write_32((uintptr_t)(a), (v))
+#else
+#error Please define CCSR SNVS register endianness
+#endif
+
+void snvs_init(uintptr_t nxp_snvs_addr);
+uint32_t get_snvs_state(void);
+void transition_snvs_non_secure(void);
+void transition_snvs_soft_fail(void);
+uint32_t transition_snvs_trusted(void);
+uint32_t transition_snvs_secure(void);
+
+uint32_t snvs_read_lp_gpr_bit(uint32_t offset, uint32_t bit_pos);
+void snvs_write_lp_gpr_bit(uint32_t offset, uint32_t bit_pos, bool flag_val);
+
+void snvs_disable_zeroize_lp_gpr(void);
+
+#if defined(NXP_NV_SW_MAINT_LAST_EXEC_DATA) && defined(NXP_COINED_BB)
+uint32_t snvs_read_app_data(void);
+uint32_t snvs_read_app_data_bit(uint32_t bit_pos);
+void snvs_clear_app_data(void);
+void snvs_write_app_data_bit(uint32_t bit_pos);
+#endif
+
+#endif /* __ASSEMBLER__ */
+
+/* SSM_ST field in SNVS status reg */
+#define HPSTS_CHECK_SSM_ST 0x900 /* SNVS is in check state */
+#define HPSTS_NON_SECURE_SSM_ST 0xb00 /* SNVS is in non secure state */
+#define HPSTS_TRUST_SSM_ST 0xd00 /* SNVS is in trusted state */
+#define HPSTS_SECURE_SSM_ST 0xf00 /* SNVS is in secure state */
+#define HPSTS_SOFT_FAIL_SSM_ST 0x300 /* SNVS is in soft fail state */
+#define HPSTS_MASK_SSM_ST 0xf00 /* SSM_ST field mask in SNVS reg */
+
+/* SNVS register bits */
+#define HPCOM_SW_SV 0x100 /* Security Violation bit */
+#define HPCOM_SW_FSV 0x200 /* Fatal Security Violation bit */
+#define HPCOM_SSM_ST 0x1 /* SSM_ST field in SNVS command reg */
+#define HPCOM_SSM_ST_DIS 0x2 /* Disable Secure to Trusted State */
+#define HPCOM_SSM_SFNS_DIS 0x4 /* Disable Soft Fail to Non-Secure */
+
+#define NXP_LP_GPR0_OFFSET 0x90
+#define NXP_LPCR_OFFSET 0x38
+#define NXP_GPR_Z_DIS_BIT 24
+
+#ifdef NXP_COINED_BB
+
+#ifndef NXP_APP_DATA_LP_GPR_OFFSET
+#define NXP_APP_DATA_LP_GPR_OFFSET NXP_LP_GPR0_OFFSET
+#endif
+
+#define NXP_LPGPR_ZEROTH_BIT 0
+
+#endif /* NXP_COINED_BB */
+
+#endif /* SNVS_H */
diff --git a/include/drivers/nxp/sfp/fuse_prov.h b/include/drivers/nxp/sfp/fuse_prov.h
new file mode 100644
index 0000000..e015318
--- /dev/null
+++ b/include/drivers/nxp/sfp/fuse_prov.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#if !defined(FUSE_PROV_H) && defined(POLICY_FUSE_PROVISION)
+#define FUSE_PROV_H
+
+#include <endian.h>
+#include <lib/mmio.h>
+
+#define MASK_NONE U(0xFFFFFFFF)
+#define ERROR_WRITE U(0xA)
+#define ERROR_ALREADY_BLOWN U(0xB)
+
+/* Flag bit shifts */
+#define FLAG_POVDD_SHIFT U(0)
+#define FLAG_SYSCFG_SHIFT U(1)
+#define FLAG_SRKH_SHIFT U(2)
+#define FLAG_MC_SHIFT U(3)
+#define FLAG_DCV0_SHIFT U(4)
+#define FLAG_DCV1_SHIFT U(5)
+#define FLAG_DRV0_SHIFT U(6)
+#define FLAG_DRV1_SHIFT U(7)
+#define FLAG_OUID0_SHIFT U(8)
+#define FLAG_OUID1_SHIFT U(9)
+#define FLAG_OUID2_SHIFT U(10)
+#define FLAG_OUID3_SHIFT U(11)
+#define FLAG_OUID4_SHIFT U(12)
+#define FLAG_DBG_LVL_SHIFT U(13)
+#define FLAG_OTPMK_SHIFT U(16)
+#define FLAG_OUID_MASK U(0x1F)
+#define FLAG_DEBUG_MASK U(0xF)
+#define FLAG_OTPMK_MASK U(0xF)
+
+/* OTPMK flag values */
+#define PROG_OTPMK_MIN U(0x0)
+#define PROG_OTPMK_RANDOM U(0x1)
+#define PROG_OTPMK_USER U(0x2)
+#define PROG_OTPMK_RANDOM_MIN U(0x5)
+#define PROG_OTPMK_USER_MIN U(0x6)
+#define PROG_NO_OTPMK U(0x8)
+
+#define OTPMK_MIM_BITS_MASK U(0xF0000000)
+
+/* System configuration bit shifts */
+#define SCB_WP_SHIFT U(0)
+#define SCB_ITS_SHIFT U(2)
+#define SCB_NSEC_SHIFT U(4)
+#define SCB_ZD_SHIFT U(5)
+#define SCB_K0_SHIFT U(15)
+#define SCB_K1_SHIFT U(14)
+#define SCB_K2_SHIFT U(13)
+#define SCB_K3_SHIFT U(12)
+#define SCB_K4_SHIFT U(11)
+#define SCB_K5_SHIFT U(10)
+#define SCB_K6_SHIFT U(9)
+#define SCB_FR0_SHIFT U(30)
+#define SCB_FR1_SHIFT U(31)
+
+/* Fuse Header Structure */
+struct fuse_hdr_t {
+ uint8_t barker[4]; /* 0x00 Barker code */
+ uint32_t flags; /* 0x04 Script flags */
+ uint32_t povdd_gpio; /* 0x08 GPIO for POVDD */
+ uint32_t otpmk[8]; /* 0x0C-0x2B OTPMK */
+ uint32_t srkh[8]; /* 0x2C-0x4B SRKH */
+ uint32_t oem_uid[5]; /* 0x4C-0x5F OEM unique id's */
+ uint32_t dcv[2]; /* 0x60-0x67 Debug Challenge */
+ uint32_t drv[2]; /* 0x68-0x6F Debug Response */
+ uint32_t ospr1; /* 0x70 OSPR1 */
+ uint32_t sc; /* 0x74 OSPR0 (System Configuration) */
+ uint32_t reserved[2]; /* 0x78-0x7F Reserved */
+};
+
+/* Function to do fuse provisioning */
+int provision_fuses(unsigned long long fuse_scr_addr,
+ bool en_povdd_status);
+
+#define EFUSE_POWERUP_DELAY_mSec U(25)
+#endif /* FUSE_PROV_H */
diff --git a/include/drivers/nxp/sfp/sfp.h b/include/drivers/nxp/sfp/sfp.h
new file mode 100644
index 0000000..2cb4c7d
--- /dev/null
+++ b/include/drivers/nxp/sfp/sfp.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef SFP_H
+#define SFP_H
+
+#include <endian.h>
+#include <lib/mmio.h>
+
+/* SFP Configuration Register Offsets */
+#define SFP_INGR_OFFSET U(0x20)
+#define SFP_SVHESR_OFFSET U(0x24)
+#define SFP_SFPCR_OFFSET U(0x28)
+#define SFP_VER_OFFSET U(0x38)
+
+/* SFP Hamming register masks for OTPMK and DRV */
+#define SFP_SVHESR_DRV_MASK U(0x7F)
+#define SFP_SVHESR_OTPMK_MASK U(0x7FC00)
+
+/* SFP commands */
+#define SFP_INGR_READFB_CMD U(0x1)
+#define SFP_INGR_PROGFB_CMD U(0x2)
+#define SFP_INGR_ERROR_MASK U(0x100)
+
+/* SFPCR Masks */
+#define SFP_SFPCR_WD U(0x80000000)
+#define SFP_SFPCR_WDL U(0x40000000)
+
+/* SFPCR Masks */
+#define SFP_SFPCR_WD U(0x80000000)
+#define SFP_SFPCR_WDL U(0x40000000)
+
+#define SFP_FUSE_REGS_OFFSET U(0x200)
+
+#ifdef NXP_SFP_VER_3_4
+#define OSPR0_SC_MASK U(0xC000FE35)
+#elif defined(NXP_SFP_VER_3_2)
+#define OSPR0_SC_MASK U(0x0000E035)
+#endif
+
+#if defined(NXP_SFP_VER_3_4)
+#define OSPR_KEY_REVOC_SHIFT U(9)
+#define OSPR_KEY_REVOC_MASK U(0x0000fe00)
+#elif defined(NXP_SFP_VER_3_2)
+#define OSPR_KEY_REVOC_SHIFT U(13)
+#define OSPR_KEY_REVOC_MASK U(0x0000e000)
+#endif /* NXP_SFP_VER_3_4 */
+
+#define OSPR1_MC_MASK U(0xFFFF0000)
+#define OSPR1_DBG_LVL_MASK U(0x00000007)
+
+#define OSPR_ITS_MASK U(0x00000004)
+#define OSPR_WP_MASK U(0x00000001)
+
+#define MAX_OEM_UID U(5)
+#define SRK_HASH_SIZE U(32)
+
+/* SFP CCSR Register Map */
+struct sfp_ccsr_regs_t {
+ uint32_t ospr; /* 0x200 OSPR0 */
+ uint32_t ospr1; /* 0x204 OSPR1 */
+ uint32_t dcv[2]; /* 0x208 Debug Challenge Value */
+ uint32_t drv[2]; /* 0x210 Debug Response Value */
+ uint32_t fswpr; /* 0x218 FSL Section Write Protect */
+ uint32_t fsl_uid[2]; /* 0x21c FSL UID 0 */
+ uint32_t isbcr; /* 0x224 ISBC Configuration */
+ uint32_t fsspr[3]; /* 0x228 FSL Scratch Pad */
+ uint32_t otpmk[8]; /* 0x234 OTPMK */
+ uint32_t srk_hash[SRK_HASH_SIZE/sizeof(uint32_t)];
+ /* 0x254 Super Root Key Hash */
+ uint32_t oem_uid[MAX_OEM_UID]; /* 0x274 OEM UID 0 */
+};
+
+uintptr_t get_sfp_addr(void);
+void sfp_init(uintptr_t nxp_sfp_addr);
+uint32_t *get_sfp_srk_hash(void);
+int sfp_check_its(void);
+int sfp_check_oem_wp(void);
+uint32_t get_key_revoc(void);
+void set_sfp_wr_disable(void);
+int sfp_program_fuses(void);
+
+uint32_t sfp_read_oem_uid(uint8_t oem_uid);
+uint32_t sfp_write_oem_uid(uint8_t oem_uid, uint32_t sfp_val);
+
+#ifdef NXP_SFP_BE
+#define sfp_read32(a) bswap32(mmio_read_32((uintptr_t)(a)))
+#define sfp_write32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v))
+#elif defined(NXP_SFP_LE)
+#define sfp_read32(a) mmio_read_32((uintptr_t)(a))
+#define sfp_write32(a, v) mmio_write_32((uintptr_t)(a), (v))
+#else
+#error Please define CCSR SFP register endianness
+#endif
+
+#endif/* SFP_H */
diff --git a/include/drivers/nxp/sfp/sfp_error_codes.h b/include/drivers/nxp/sfp/sfp_error_codes.h
new file mode 100644
index 0000000..7be7a27
--- /dev/null
+++ b/include/drivers/nxp/sfp/sfp_error_codes.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef SFP_ERROR_CODES_H
+#define SFP_ERROR_CODES_H
+
+ /* Error codes */
+#define ERROR_FUSE_BARKER 0x1
+#define ERROR_READFB_CMD 0x2
+#define ERROR_PROGFB_CMD 0x3
+#define ERROR_SRKH_ALREADY_BLOWN 0x4
+#define ERROR_SRKH_WRITE 0x5
+#define ERROR_OEMUID_ALREADY_BLOWN 0x6
+#define ERROR_OEMUID_WRITE 0x7
+#define ERROR_DCV_ALREADY_BLOWN 0x8
+#define ERROR_DCV_WRITE 0x9
+#define ERROR_DRV_ALREADY_BLOWN 0xa
+#define ERROR_DRV_HAMMING_ERROR 0xb
+#define ERROR_DRV_WRITE 0x18
+#define ERROR_OTPMK_ALREADY_BLOWN 0xc
+#define ERROR_OTPMK_HAMMING_ERROR 0xd
+#define ERROR_OTPMK_USER_MIN 0xe
+#define ERROR_OSPR1_ALREADY_BLOWN 0xf
+#define ERROR_OSPR1_WRITE 0x10
+#define ERROR_SC_ALREADY_BLOWN 0x11
+#define ERROR_SC_WRITE 0x12
+#define ERROR_POVDD_GPIO_FAIL 0x13
+#define ERROR_GPIO_SET_FAIL 0x14
+#define ERROR_GPIO_RESET_FAIL 0x15
+#define ERROR_OTPMK_SEC_DISABLED 0x16
+#define ERROR_OTPMK_SEC_ERROR 0x17
+#define ERROR_OTPMK_WRITE 0x19
+#define PLAT_ERROR_ENABLE_POVDD 0x20
+#define PLAT_ERROR_DISABLE_POVDD 0x21
+
+#endif /* SFP_ERROR_CODES_H */
diff --git a/include/drivers/nxp/smmu/nxp_smmu.h b/include/drivers/nxp/smmu/nxp_smmu.h
new file mode 100644
index 0000000..d64c33b
--- /dev/null
+++ b/include/drivers/nxp/smmu/nxp_smmu.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef NXP_SMMU_H
+#define NXP_SMMU_H
+
+#define SMMU_SCR0 (0x0)
+#define SMMU_NSCR0 (0x400)
+
+#define SCR0_CLIENTPD_MASK 0x00000001
+#define SCR0_USFCFG_MASK 0x00000400
+
+static inline void bypass_smmu(uintptr_t smmu_base_addr)
+{
+ uint32_t val;
+
+ val = (mmio_read_32(smmu_base_addr + SMMU_SCR0) | SCR0_CLIENTPD_MASK) &
+ ~(SCR0_USFCFG_MASK);
+ mmio_write_32((smmu_base_addr + SMMU_SCR0), val);
+
+ val = (mmio_read_32(smmu_base_addr + SMMU_NSCR0) | SCR0_CLIENTPD_MASK) &
+ ~(SCR0_USFCFG_MASK);
+ mmio_write_32((smmu_base_addr + SMMU_NSCR0), val);
+}
+
+#endif
diff --git a/include/drivers/nxp/timer/nxp_timer.h b/include/drivers/nxp/timer/nxp_timer.h
new file mode 100644
index 0000000..280e5b2
--- /dev/null
+++ b/include/drivers/nxp/timer/nxp_timer.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#
+#ifndef NXP_TIMER_H
+#define NXP_TIMER_H
+
+ /* System Counter Offset and Bit Mask */
+#define SYS_COUNTER_CNTCR_OFFSET 0x0
+#define SYS_COUNTER_CNTCR_EN 0x00000001
+#define CNTCR_EN_MASK 0x1
+
+#ifndef __ASSEMBLER__
+uint64_t get_timer_val(uint64_t start);
+
+#ifdef IMAGE_BL31
+void ls_configure_sys_timer(uintptr_t ls_sys_timctl_base,
+ uint8_t ls_config_cntacr,
+ uint8_t plat_ls_ns_timer_frame_id);
+void enable_init_timer(void);
+#endif
+
+/*
+ * Initialise the nxp on-chip free rolling usec counter as the delay
+ * timer.
+ */
+void delay_timer_init(uintptr_t nxp_timer_addr);
+void ls_bl31_timer_init(uintptr_t nxp_timer_addr);
+#endif /* __ASSEMBLER__ */
+
+#endif /* NXP_TIMER_H */
diff --git a/include/drivers/nxp/tzc/plat_tzc400.h b/include/drivers/nxp/tzc/plat_tzc400.h
new file mode 100644
index 0000000..1b8e3a4
--- /dev/null
+++ b/include/drivers/nxp/tzc/plat_tzc400.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#if !defined(PLAT_TZC400_H) && defined(IMAGE_BL2)
+#define PLAT_TZC400_H
+
+#include <tzc400.h>
+
+/* Structure to configure TZC Regions' boundaries and attributes. */
+struct tzc400_reg {
+ uint8_t reg_filter_en;
+ unsigned long long start_addr;
+ unsigned long long end_addr;
+ unsigned int sec_attr;
+ unsigned int nsaid_permissions;
+};
+
+#define TZC_REGION_NS_NONE 0x00000000U
+
+/* NXP Platforms do not support NS Access ID (NSAID) based non-secure access.
+ * Supports only non secure through generic NS ACCESS ID
+ */
+#define TZC_NS_ACCESS_ID 0xFFFFFFFFU
+
+/* Number of DRAM regions to be configured
+ * for the platform can be over-written.
+ *
+ * Array tzc400_reg_list too, needs be over-written
+ * if there is any changes to default DRAM region
+ * configuration.
+ */
+#ifndef MAX_NUM_TZC_REGION
+/* 3 regions:
+ * Region 0(default),
+ * Region 1 (DRAM0, Secure Memory),
+ * Region 2 (DRAM0, Shared memory)
+ */
+#define MAX_NUM_TZC_REGION NUM_DRAM_REGIONS + 3
+#define DEFAULT_TZASC_CONFIG 1
+#endif
+
+void mem_access_setup(uintptr_t base, uint32_t total_regions,
+ struct tzc400_reg *tzc400_reg_list);
+int populate_tzc400_reg_list(struct tzc400_reg *tzc400_reg_list,
+ int dram_idx, int list_idx,
+ uint64_t dram_start_addr,
+ uint64_t dram_size,
+ uint32_t secure_dram_sz,
+ uint32_t shrd_dram_sz);
+
+#endif /* PLAT_TZC400_H */
diff --git a/include/drivers/rambus/trng_ip_76.h b/include/drivers/rambus/trng_ip_76.h
new file mode 100644
index 0000000..6de8fc7
--- /dev/null
+++ b/include/drivers/rambus/trng_ip_76.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2020, Marvell Technology Group Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+
+#ifndef __TRNG_IP_76_H__
+#define __TRNG_IP_76_H__
+
+#include <stdbool.h>
+#include <stdint.h>
+
+int32_t eip76_rng_read_rand_buf(void *data, bool wait);
+int32_t eip76_rng_probe(uintptr_t base_addr);
+int32_t eip76_rng_get_random(uint8_t *data, uint32_t len);
+
+#endif /* __TRNG_IP_76_H__ */
diff --git a/include/drivers/st/io_mmc.h b/include/drivers/st/io_mmc.h
index b35b4b5..6179e89 100644
--- a/include/drivers/st/io_mmc.h
+++ b/include/drivers/st/io_mmc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,6 +9,10 @@
#include <drivers/io/io_driver.h>
+struct io_mmc_dev_spec {
+ bool use_boot_part;
+};
+
int register_io_dev_mmc(const io_dev_connector_t **dev_con);
#endif /* IO_MMC_H */
diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h
index aa9158c..803cd9c 100644
--- a/include/dt-bindings/interrupt-controller/arm-gic.h
+++ b/include/dt-bindings/interrupt-controller/arm-gic.h
@@ -1,21 +1,26 @@
-/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
/*
+ * Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
* This header provides constants for the ARM GIC.
*/
#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
+#include <dt-bindings/interrupt-controller/irq.h>
+
/* interrupt specifier cell 0 */
#define GIC_SPI 0
#define GIC_PPI 1
-#define IRQ_TYPE_NONE 0
-#define IRQ_TYPE_EDGE_RISING 1
-#define IRQ_TYPE_EDGE_FALLING 2
-#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
-#define IRQ_TYPE_LEVEL_HIGH 4
-#define IRQ_TYPE_LEVEL_LOW 8
+/*
+ * Interrupt specifier cell 2.
+ * The flags in irq.h are valid, plus those below.
+ */
+#define GIC_CPU_MASK_RAW(x) ((x) << 8)
+#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
#endif
diff --git a/include/dt-bindings/interrupt-controller/irq.h b/include/dt-bindings/interrupt-controller/irq.h
new file mode 100644
index 0000000..94e7f95
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/irq.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: MIT
+ *
+ * This header provides constants for most IRQ bindings.
+ *
+ * Most IRQ bindings include a flags cell as part of the IRQ specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
+
+#define IRQ_TYPE_NONE 0
+#define IRQ_TYPE_EDGE_RISING 1
+#define IRQ_TYPE_EDGE_FALLING 2
+#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
+#define IRQ_TYPE_LEVEL_HIGH 4
+#define IRQ_TYPE_LEVEL_LOW 8
+
+#endif
diff --git a/include/export/common/tbbr/tbbr_img_def_exp.h b/include/export/common/tbbr/tbbr_img_def_exp.h
index 18f0125..2623c75 100644
--- a/include/export/common/tbbr/tbbr_img_def_exp.h
+++ b/include/export/common/tbbr/tbbr_img_def_exp.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -91,7 +91,17 @@
/* FW_CONFIG */
#define FW_CONFIG_ID U(31)
+/*
+ * Primary FWU metadata image ID
+ */
+#define FWU_METADATA_IMAGE_ID U(32)
+
+/*
+ * Backup FWU metadata image ID
+ */
+#define BKUP_FWU_METADATA_IMAGE_ID U(33)
+
/* Max Images */
-#define MAX_IMAGE_IDS U(32)
+#define MAX_IMAGE_IDS U(34)
#endif /* ARM_TRUSTED_FIRMWARE_EXPORT_COMMON_TBBR_TBBR_IMG_DEF_EXP_H */
diff --git a/include/lib/cpus/aarch64/cortex_a510.h b/include/lib/cpus/aarch64/cortex_a510.h
new file mode 100644
index 0000000..6a4cfdf
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_a510.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_A510_H
+#define CORTEX_A510_H
+
+#define CORTEX_A510_MIDR U(0x410FD460)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A510_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* CORTEX_A510_H */
diff --git a/include/lib/cpus/aarch64/cortex_a710.h b/include/lib/cpus/aarch64/cortex_a710.h
new file mode 100644
index 0000000..8b011aa
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_a710.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_A710_H
+#define CORTEX_A710_H
+
+#define CORTEX_A710_MIDR U(0x410FD470)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A710_CPUECTLR_EL1 S3_0_C15_C1_4
+#define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A710_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+/*******************************************************************************
+ * CPU Auxiliary Control register specific definitions.
+ ******************************************************************************/
+#define CORTEX_A710_CPUACTLR_EL1 S3_0_C15_C1_0
+#define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
+
+#endif /* CORTEX_A710_H */
diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h
index 0a42a5d..5753e90 100644
--- a/include/lib/cpus/aarch64/cortex_a77.h
+++ b/include/lib/cpus/aarch64/cortex_a77.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,6 +24,12 @@
#define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
+/*******************************************************************************
+ * CPU Auxiliary Control register specific definitions.
+ ******************************************************************************/
+#define CORTEX_A77_ACTLR2_EL1 S3_0_C15_C1_1
+#define CORTEX_A77_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
+
#define CORTEX_A77_CPUPSELR_EL3 S3_6_C15_C8_0
#define CORTEX_A77_CPUPCR_EL3 S3_6_C15_C8_1
#define CORTEX_A77_CPUPOR_EL3 S3_6_C15_C8_2
diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h
index caa5120..4bc49f3 100644
--- a/include/lib/cpus/aarch64/cortex_a78.h
+++ b/include/lib/cpus/aarch64/cortex_a78.h
@@ -30,6 +30,7 @@
#define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1
#define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
+#define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
/*******************************************************************************
* CPU Activity Monitor Unit register specific definitions.
diff --git a/include/lib/cpus/aarch64/cortex_a78_ae.h b/include/lib/cpus/aarch64/cortex_a78_ae.h
index 24ae7ee..0c8adcf 100644
--- a/include/lib/cpus/aarch64/cortex_a78_ae.h
+++ b/include/lib/cpus/aarch64/cortex_a78_ae.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,4 +12,10 @@
#define CORTEX_A78_AE_MIDR U(0x410FD420)
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ ******************************************************************************/
+#define CORTEX_A78_AE_CPUECTLR_EL1 CORTEX_A78_CPUECTLR_EL1
+#define CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 CORTEX_A78_CPUECTLR_EL1_BIT_8
+
#endif /* CORTEX_A78_AE_H */
diff --git a/include/lib/cpus/aarch64/cortex_a78c.h b/include/lib/cpus/aarch64/cortex_a78c.h
new file mode 100644
index 0000000..adb13bc
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_a78c.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_A78C_H
+#define CORTEX_A78C_H
+
+
+#define CORTEX_A78C_MIDR U(0x410FD4B1)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ ******************************************************************************/
+#define CORTEX_A78C_CPUECTLR_EL1 S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A78C_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
+
+#endif /* CORTEX_A78C_H */
diff --git a/include/lib/cpus/aarch64/cortex_demeter.h b/include/lib/cpus/aarch64/cortex_demeter.h
new file mode 100644
index 0000000..9dd0987
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_demeter.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_DEMETER_H
+#define CORTEX_DEMETER_H
+
+#define CORTEX_DEMETER_MIDR U(0x410FD4F0)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_DEMETER_CPUECTLR_EL1 S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_DEMETER_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* CORTEX_DEMETER_H */
diff --git a/include/lib/cpus/aarch64/cortex_klein.h b/include/lib/cpus/aarch64/cortex_klein.h
deleted file mode 100644
index 729b3bf..0000000
--- a/include/lib/cpus/aarch64/cortex_klein.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (c) 2020, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef CORTEX_KLEIN_H
-#define CORTEX_KLEIN_H
-
-#define CORTEX_KLEIN_MIDR U(0x410FD460)
-
-/*******************************************************************************
- * CPU Extended Control register specific definitions
- ******************************************************************************/
-#define CORTEX_KLEIN_CPUECTLR_EL1 S3_0_C15_C1_4
-
-/*******************************************************************************
- * CPU Power Control register specific definitions
- ******************************************************************************/
-#define CORTEX_KLEIN_CPUPWRCTLR_EL1 S3_0_C15_C2_7
-#define CORTEX_KLEIN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
-
-#endif /* CORTEX_KLEIN_H */
diff --git a/include/lib/cpus/aarch64/cortex_makalu.h b/include/lib/cpus/aarch64/cortex_makalu.h
new file mode 100644
index 0000000..4e0dc86
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_makalu.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_MAKALU_H
+#define CORTEX_MAKALU_H
+
+#define CORTEX_MAKALU_MIDR U(0x410FD4D0)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_MAKALU_CPUECTLR_EL1 S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_MAKALU_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_MAKALU_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* CORTEX_MAKALU_H */
diff --git a/include/lib/cpus/aarch64/cortex_makalu_elp_arm.h b/include/lib/cpus/aarch64/cortex_makalu_elp_arm.h
new file mode 100644
index 0000000..a0d788e
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_makalu_elp_arm.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_MAKALU_ELP_ARM_H
+#define CORTEX_MAKALU_ELP_ARM_H
+
+#define CORTEX_MAKALU_ELP_ARM_MIDR U(0x410FD4E0)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_MAKALU_ELP_ARM_CPUECTLR_EL1 S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* CORTEX_MAKALU_ELP_ARM_H */
diff --git a/include/lib/cpus/aarch64/cortex_matterhorn.h b/include/lib/cpus/aarch64/cortex_matterhorn.h
deleted file mode 100644
index 0185533..0000000
--- a/include/lib/cpus/aarch64/cortex_matterhorn.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (c) 2020, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef CORTEX_MATTERHORN_H
-#define CORTEX_MATTERHORN_H
-
-#define CORTEX_MATTERHORN_MIDR U(0x410FD470)
-
-/*******************************************************************************
- * CPU Extended Control register specific definitions
- ******************************************************************************/
-#define CORTEX_MATTERHORN_CPUECTLR_EL1 S3_0_C15_C1_4
-
-/*******************************************************************************
- * CPU Power Control register specific definitions
- ******************************************************************************/
-#define CORTEX_MATTERHORN_CPUPWRCTLR_EL1 S3_0_C15_C2_7
-#define CORTEX_MATTERHORN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
-
-#endif /* CORTEX_MATTERHORN_H */
diff --git a/include/lib/cpus/aarch64/cortex_x2.h b/include/lib/cpus/aarch64/cortex_x2.h
new file mode 100644
index 0000000..9ce1223
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_x2.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_X2_H
+#define CORTEX_X2_H
+
+#define CORTEX_X2_MIDR U(0x410FD480)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_X2_CPUECTLR_EL1 S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_X2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* CORTEX_X2_H */
diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h
index 7cbd8c1..948f965 100644
--- a/include/lib/cpus/aarch64/neoverse_n2.h
+++ b/include/lib/cpus/aarch64/neoverse_n2.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,11 +21,24 @@
******************************************************************************/
#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4
#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
+#define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
/*******************************************************************************
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
+#define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0
+#define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
+
+/*******************************************************************************
+ * CPU Auxiliary Control register 2 specific definitions.
+ ******************************************************************************/
#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1
#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
+/*******************************************************************************
+ * CPU Auxiliary Control register 5 specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0
+#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
+
#endif /* NEOVERSE_N2_H */
diff --git a/include/lib/cpus/aarch64/neoverse_v1.h b/include/lib/cpus/aarch64/neoverse_v1.h
index 650eb4d..cfb26ab 100644
--- a/include/lib/cpus/aarch64/neoverse_v1.h
+++ b/include/lib/cpus/aarch64/neoverse_v1.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,6 +13,8 @@
* CPU Extended Control register specific definitions.
******************************************************************************/
#define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4
+#define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
+#define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
/*******************************************************************************
* CPU Power Control register specific definitions
@@ -20,4 +22,11 @@
#define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
#define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+/*******************************************************************************
+ * CPU Auxiliary Control register specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_V1_ACTLR2_EL1 S3_0_C15_C1_1
+#define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
+#define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28)
+
#endif /* NEOVERSE_V1_H */
diff --git a/include/lib/cpus/aarch64/qemu_max.h b/include/lib/cpus/aarch64/qemu_max.h
new file mode 100644
index 0000000..14da170
--- /dev/null
+++ b/include/lib/cpus/aarch64/qemu_max.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef QEMU_MAX_H
+#define QEMU_MAX_H
+
+#include <lib/utils_def.h>
+
+/*
+ * QEMU MAX midr for revision 0
+ * 00 - Reserved for software use
+ * 0 - Variant
+ * F - Architectural features identified in ID_* registers
+ * 051 - 'Q', in a 12-bit field.
+ * 0 - Revision
+ */
+#define QEMU_MAX_MIDR U(0x000F0510)
+
+#endif /* QEMU_MAX_H */
diff --git a/include/lib/el3_runtime/aarch64/context.h b/include/lib/el3_runtime/aarch64/context.h
index 3135fb4..d449a65 100644
--- a/include/lib/el3_runtime/aarch64/context.h
+++ b/include/lib/el3_runtime/aarch64/context.h
@@ -61,7 +61,9 @@
#define CTX_ELR_EL3 U(0x20)
#define CTX_PMCR_EL0 U(0x28)
#define CTX_IS_IN_EL3 U(0x30)
-#define CTX_EL3STATE_END U(0x40) /* Align to the next 16 byte boundary */
+#define CTX_CPTR_EL3 U(0x38)
+#define CTX_ZCR_EL3 U(0x40)
+#define CTX_EL3STATE_END U(0x50) /* Align to the next 16 byte boundary */
/*******************************************************************************
* Constants that allow assembler code to access members of and the
@@ -160,86 +162,74 @@
#define CTX_AFSR1_EL2 U(0x10)
#define CTX_AMAIR_EL2 U(0x18)
#define CTX_CNTHCTL_EL2 U(0x20)
-#define CTX_CNTHP_CTL_EL2 U(0x28)
-#define CTX_CNTHP_CVAL_EL2 U(0x30)
-#define CTX_CNTHP_TVAL_EL2 U(0x38)
-#define CTX_CNTVOFF_EL2 U(0x40)
-#define CTX_CPTR_EL2 U(0x48)
-#define CTX_DBGVCR32_EL2 U(0x50)
-#define CTX_ELR_EL2 U(0x58)
-#define CTX_ESR_EL2 U(0x60)
-#define CTX_FAR_EL2 U(0x68)
-#define CTX_HACR_EL2 U(0x70)
-#define CTX_HCR_EL2 U(0x78)
-#define CTX_HPFAR_EL2 U(0x80)
-#define CTX_HSTR_EL2 U(0x88)
-#define CTX_ICC_SRE_EL2 U(0x90)
-#define CTX_ICH_HCR_EL2 U(0x98)
-#define CTX_ICH_VMCR_EL2 U(0xa0)
-#define CTX_MAIR_EL2 U(0xa8)
-#define CTX_MDCR_EL2 U(0xb0)
-#define CTX_PMSCR_EL2 U(0xb8)
-#define CTX_SCTLR_EL2 U(0xc0)
-#define CTX_SPSR_EL2 U(0xc8)
-#define CTX_SP_EL2 U(0xd0)
-#define CTX_TCR_EL2 U(0xd8)
-#define CTX_TPIDR_EL2 U(0xe0)
-#define CTX_TTBR0_EL2 U(0xe8)
-#define CTX_VBAR_EL2 U(0xf0)
-#define CTX_VMPIDR_EL2 U(0xf8)
-#define CTX_VPIDR_EL2 U(0x100)
-#define CTX_VTCR_EL2 U(0x108)
-#define CTX_VTTBR_EL2 U(0x110)
+#define CTX_CNTVOFF_EL2 U(0x28)
+#define CTX_CPTR_EL2 U(0x30)
+#define CTX_DBGVCR32_EL2 U(0x38)
+#define CTX_ELR_EL2 U(0x40)
+#define CTX_ESR_EL2 U(0x48)
+#define CTX_FAR_EL2 U(0x50)
+#define CTX_HACR_EL2 U(0x58)
+#define CTX_HCR_EL2 U(0x60)
+#define CTX_HPFAR_EL2 U(0x68)
+#define CTX_HSTR_EL2 U(0x70)
+#define CTX_ICC_SRE_EL2 U(0x78)
+#define CTX_ICH_HCR_EL2 U(0x80)
+#define CTX_ICH_VMCR_EL2 U(0x88)
+#define CTX_MAIR_EL2 U(0x90)
+#define CTX_MDCR_EL2 U(0x98)
+#define CTX_PMSCR_EL2 U(0xa0)
+#define CTX_SCTLR_EL2 U(0xa8)
+#define CTX_SPSR_EL2 U(0xb0)
+#define CTX_SP_EL2 U(0xb8)
+#define CTX_TCR_EL2 U(0xc0)
+#define CTX_TPIDR_EL2 U(0xc8)
+#define CTX_TTBR0_EL2 U(0xd0)
+#define CTX_VBAR_EL2 U(0xd8)
+#define CTX_VMPIDR_EL2 U(0xe0)
+#define CTX_VPIDR_EL2 U(0xe8)
+#define CTX_VTCR_EL2 U(0xf0)
+#define CTX_VTTBR_EL2 U(0xf8)
// Only if MTE registers in use
-#define CTX_TFSR_EL2 U(0x118)
+#define CTX_TFSR_EL2 U(0x100)
// Only if ENABLE_MPAM_FOR_LOWER_ELS==1
-#define CTX_MPAM2_EL2 U(0x120)
-#define CTX_MPAMHCR_EL2 U(0x128)
-#define CTX_MPAMVPM0_EL2 U(0x130)
-#define CTX_MPAMVPM1_EL2 U(0x138)
-#define CTX_MPAMVPM2_EL2 U(0x140)
-#define CTX_MPAMVPM3_EL2 U(0x148)
-#define CTX_MPAMVPM4_EL2 U(0x150)
-#define CTX_MPAMVPM5_EL2 U(0x158)
-#define CTX_MPAMVPM6_EL2 U(0x160)
-#define CTX_MPAMVPM7_EL2 U(0x168)
-#define CTX_MPAMVPMV_EL2 U(0x170)
+#define CTX_MPAM2_EL2 U(0x108)
+#define CTX_MPAMHCR_EL2 U(0x110)
+#define CTX_MPAMVPM0_EL2 U(0x118)
+#define CTX_MPAMVPM1_EL2 U(0x120)
+#define CTX_MPAMVPM2_EL2 U(0x128)
+#define CTX_MPAMVPM3_EL2 U(0x130)
+#define CTX_MPAMVPM4_EL2 U(0x138)
+#define CTX_MPAMVPM5_EL2 U(0x140)
+#define CTX_MPAMVPM6_EL2 U(0x148)
+#define CTX_MPAMVPM7_EL2 U(0x150)
+#define CTX_MPAMVPMV_EL2 U(0x158)
// Starting with Armv8.6
-#define CTX_HAFGRTR_EL2 U(0x178)
-#define CTX_HDFGRTR_EL2 U(0x180)
-#define CTX_HDFGWTR_EL2 U(0x188)
-#define CTX_HFGITR_EL2 U(0x190)
-#define CTX_HFGRTR_EL2 U(0x198)
-#define CTX_HFGWTR_EL2 U(0x1a0)
-#define CTX_CNTPOFF_EL2 U(0x1a8)
+#define CTX_HAFGRTR_EL2 U(0x160)
+#define CTX_HDFGRTR_EL2 U(0x168)
+#define CTX_HDFGWTR_EL2 U(0x170)
+#define CTX_HFGITR_EL2 U(0x178)
+#define CTX_HFGRTR_EL2 U(0x180)
+#define CTX_HFGWTR_EL2 U(0x188)
+#define CTX_CNTPOFF_EL2 U(0x190)
// Starting with Armv8.4
-#define CTX_CNTHPS_CTL_EL2 U(0x1b0)
-#define CTX_CNTHPS_CVAL_EL2 U(0x1b8)
-#define CTX_CNTHPS_TVAL_EL2 U(0x1c0)
-#define CTX_CNTHVS_CTL_EL2 U(0x1c8)
-#define CTX_CNTHVS_CVAL_EL2 U(0x1d0)
-#define CTX_CNTHVS_TVAL_EL2 U(0x1d8)
-#define CTX_CNTHV_CTL_EL2 U(0x1e0)
-#define CTX_CNTHV_CVAL_EL2 U(0x1e8)
-#define CTX_CNTHV_TVAL_EL2 U(0x1f0)
-#define CTX_CONTEXTIDR_EL2 U(0x1f8)
-#define CTX_SDER32_EL2 U(0x200)
-#define CTX_TTBR1_EL2 U(0x208)
-#define CTX_VDISR_EL2 U(0x210)
-#define CTX_VNCR_EL2 U(0x218)
-#define CTX_VSESR_EL2 U(0x220)
-#define CTX_VSTCR_EL2 U(0x228)
-#define CTX_VSTTBR_EL2 U(0x230)
-#define CTX_TRFCR_EL2 U(0x238)
+#define CTX_CONTEXTIDR_EL2 U(0x198)
+#define CTX_SDER32_EL2 U(0x1a0)
+#define CTX_TTBR1_EL2 U(0x1a8)
+#define CTX_VDISR_EL2 U(0x1b0)
+#define CTX_VNCR_EL2 U(0x1b8)
+#define CTX_VSESR_EL2 U(0x1c0)
+#define CTX_VSTCR_EL2 U(0x1c8)
+#define CTX_VSTTBR_EL2 U(0x1d0)
+#define CTX_TRFCR_EL2 U(0x1d8)
// Starting with Armv8.5
-#define CTX_SCXTNUM_EL2 U(0x240)
+#define CTX_SCXTNUM_EL2 U(0x1e0)
/* Align to the next 16 byte boundary */
-#define CTX_EL2_SYSREGS_END U(0x250)
+#define CTX_EL2_SYSREGS_END U(0x1f0)
#endif /* CTX_INCLUDE_EL2_REGS */
diff --git a/include/lib/el3_runtime/cpu_data.h b/include/lib/el3_runtime/cpu_data.h
index 5426135..3d57a5c 100644
--- a/include/lib/el3_runtime/cpu_data.h
+++ b/include/lib/el3_runtime/cpu_data.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -125,7 +125,7 @@
#if ENABLE_PAUTH
CASSERT(CPU_DATA_APIAKEY_OFFSET == __builtin_offsetof
(cpu_data_t, apiakey),
- assert_cpu_data_crash_stack_offset_mismatch);
+ assert_cpu_data_pauth_stack_offset_mismatch);
#endif
#if CRASH_REPORTING
diff --git a/include/lib/extensions/amu.h b/include/lib/extensions/amu.h
index dcbdd5a..3a254c9 100644
--- a/include/lib/extensions/amu.h
+++ b/include/lib/extensions/amu.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,6 +13,7 @@
#include <lib/cassert.h>
#include <lib/utils_def.h>
+#include <context.h>
#include <platform_def.h>
/* All group 0 counters */
@@ -66,19 +67,35 @@
struct amu_ctx {
uint64_t group0_cnts[AMU_GROUP0_NR_COUNTERS];
+#if __aarch64__
+ /* Architected event counter 1 does not have an offset register. */
+ uint64_t group0_voffsets[AMU_GROUP0_NR_COUNTERS-1];
+#endif
#if AMU_GROUP1_NR_COUNTERS
uint64_t group1_cnts[AMU_GROUP1_NR_COUNTERS];
+#if __aarch64__
+ uint64_t group1_voffsets[AMU_GROUP1_NR_COUNTERS];
+#endif
#endif
};
-bool amu_supported(void);
+unsigned int amu_get_version(void);
+#if __aarch64__
+void amu_enable(bool el2_unused, cpu_context_t *ctx);
+#else
void amu_enable(bool el2_unused);
+#endif
/* Group 0 configuration helpers */
uint64_t amu_group0_cnt_read(unsigned int idx);
void amu_group0_cnt_write(unsigned int idx, uint64_t val);
+#if __aarch64__
+uint64_t amu_group0_voffset_read(unsigned int idx);
+void amu_group0_voffset_write(unsigned int idx, uint64_t val);
+#endif
+
#if AMU_GROUP1_NR_COUNTERS
bool amu_group1_supported(void);
@@ -86,6 +103,12 @@
uint64_t amu_group1_cnt_read(unsigned int idx);
void amu_group1_cnt_write(unsigned int idx, uint64_t val);
void amu_group1_set_evtype(unsigned int idx, unsigned int val);
+
+#if __aarch64__
+uint64_t amu_group1_voffset_read(unsigned int idx);
+void amu_group1_voffset_write(unsigned int idx, uint64_t val);
+#endif
+
#endif
#endif /* AMU_H */
diff --git a/include/lib/extensions/amu_private.h b/include/lib/extensions/amu_private.h
index 30ce59d..3b4b47c 100644
--- a/include/lib/extensions/amu_private.h
+++ b/include/lib/extensions/amu_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,4 +16,12 @@
void amu_group1_cnt_write_internal(unsigned int idx, uint64_t val);
void amu_group1_set_evtype_internal(unsigned int idx, unsigned int val);
+#if __aarch64__
+uint64_t amu_group0_voffset_read_internal(unsigned int idx);
+void amu_group0_voffset_write_internal(unsigned int idx, uint64_t val);
+
+uint64_t amu_group1_voffset_read_internal(unsigned int idx);
+void amu_group1_voffset_write_internal(unsigned int idx, uint64_t val);
+#endif
+
#endif /* AMU_PRIVATE_H */
diff --git a/include/lib/extensions/mpam.h b/include/lib/extensions/mpam.h
index ac8c00a..414adcb 100644
--- a/include/lib/extensions/mpam.h
+++ b/include/lib/extensions/mpam.h
@@ -9,7 +9,6 @@
#include <stdbool.h>
-bool mpam_supported(void);
void mpam_enable(bool el2_unused);
#endif /* MPAM_H */
diff --git a/include/lib/extensions/sve.h b/include/lib/extensions/sve.h
index 83df177..c85e08c 100644
--- a/include/lib/extensions/sve.h
+++ b/include/lib/extensions/sve.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,9 +7,8 @@
#ifndef SVE_H
#define SVE_H
-#include <stdbool.h>
+#include <context.h>
-bool sve_supported(void);
-void sve_enable(bool el2_unused);
+void sve_enable(cpu_context_t *context);
#endif /* SVE_H */
diff --git a/include/lib/libc/arm_acle.h b/include/lib/libc/arm_acle.h
new file mode 100644
index 0000000..eb08552
--- /dev/null
+++ b/include/lib/libc/arm_acle.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2021 ARM Limited
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * The definitions below are a subset of what we would normally get by using
+ * the compiler's version of arm_acle.h. We can't use that directly because
+ * we specify -nostdinc in the Makefiles.
+ *
+ * We just define the functions we need so far.
+ */
+
+#ifndef ARM_ACLE_H
+#define ARM_ACLE_H
+
+#if !defined(__aarch64__) || defined(__clang__)
+# define __crc32b __builtin_arm_crc32b
+# define __crc32w __builtin_arm_crc32w
+#else
+# define __crc32b __builtin_aarch64_crc32b
+# define __crc32w __builtin_aarch64_crc32w
+#endif
+
+#endif /* ARM_ACLE_H */
diff --git a/include/lib/smccc.h b/include/lib/smccc.h
index 470317d..deaeb1d 100644
--- a/include/lib/smccc.h
+++ b/include/lib/smccc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -51,6 +51,23 @@
FUNCID_OEN_MASK)
/*******************************************************************************
+ * SMCCC_ARCH_SOC_ID SoC version & revision bit definition
+ ******************************************************************************/
+#define SOC_ID_JEP_106_BANK_IDX_MASK GENMASK_32(30, 24)
+#define SOC_ID_JEP_106_BANK_IDX_SHIFT U(24)
+#define SOC_ID_JEP_106_ID_CODE_MASK GENMASK_32(23, 16)
+#define SOC_ID_JEP_106_ID_CODE_SHIFT U(16)
+#define SOC_ID_IMPL_DEF_MASK GENMASK_32(15, 0)
+#define SOC_ID_IMPL_DEF_SHIFT U(0)
+#define SOC_ID_SET_JEP_106(bkid, mfid) ((((bkid) << SOC_ID_JEP_106_BANK_IDX_SHIFT) & \
+ SOC_ID_JEP_106_BANK_IDX_MASK) | \
+ (((mfid) << SOC_ID_JEP_106_ID_CODE_SHIFT) & \
+ SOC_ID_JEP_106_ID_CODE_MASK))
+
+#define SOC_ID_REV_MASK GENMASK_32(30, 0)
+#define SOC_ID_REV_SHIFT U(0)
+
+/*******************************************************************************
* Owning entity number definitions inside the function id as per the SMC
* calling convention
******************************************************************************/
diff --git a/include/lib/utils_def.h b/include/lib/utils_def.h
index 2d0e9c0..7a7012d 100644
--- a/include/lib/utils_def.h
+++ b/include/lib/utils_def.h
@@ -163,4 +163,9 @@
*/
#define MHZ_TICKS_PER_SEC U(1000000)
+/*
+ * Ticks elapsed in one second with a signal of 1 KHz
+ */
+#define KHZ_TICKS_PER_SEC U(1000)
+
#endif /* UTILS_DEF_H */
diff --git a/include/plat/arm/board/common/board_css_def.h b/include/plat/arm/board/common/board_css_def.h
index b79e0d5..1963bf0 100644
--- a/include/plat/arm/board/common/board_css_def.h
+++ b/include/plat/arm/board/common/board_css_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -44,8 +44,18 @@
#define MAX_IO_HANDLES 4
/* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE
-#define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+#if ARM_GPT_SUPPORT
+/*
+ * Offset of the FIP in the GPT image. BL1 component uses this option
+ * as it does not load the partition table to get the FIP base
+ * address. At sector 34 by default (i.e. after reserved sectors 0-33)
+ * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400
+ */
+#define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400
+#endif /* ARM_GPT_SUPPORT */
#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 00746c6..ae80628 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -465,12 +465,16 @@
* BL32 specific defines for EL3 runtime in AArch32 mode
******************************************************************************/
# if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME
+/* Ensure Position Independent support (PIE) is enabled for this config.*/
+# if !ENABLE_PIE
+# error "BL32 must be a PIE if RESET_TO_SP_MIN=1."
+#endif
/*
- * SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding
- * the page reserved for fw_configs) to BL32
+ * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely
+ * used for building BL32 and not used for loading BL32.
*/
-# define BL32_BASE ARM_FW_CONFIGS_LIMIT
-# define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
+# define BL32_BASE 0x0
+# define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE
# else
/* Put BL32 below BL2 in the Trusted SRAM.*/
# define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
diff --git a/include/plat/arm/common/arm_sip_svc.h b/include/plat/arm/common/arm_sip_svc.h
index 85fdb28..2eeed95 100644
--- a/include/plat/arm/common/arm_sip_svc.h
+++ b/include/plat/arm/common/arm_sip_svc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019,2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -25,6 +25,12 @@
/* DEBUGFS_SMC_32 0x82000030U */
/* DEBUGFS_SMC_64 0xC2000030U */
+/*
+ * Arm Ethos-N NPU SiP SMC function IDs
+ * 0xC2000050-0xC200005F
+ * 0x82000050-0x8200005F
+ */
+
/* ARM SiP Service Calls version numbers */
#define ARM_SIP_SVC_VERSION_MAJOR U(0x0)
#define ARM_SIP_SVC_VERSION_MINOR U(0x2)
diff --git a/include/plat/arm/common/fconf_ethosn_getter.h b/include/plat/arm/common/fconf_ethosn_getter.h
new file mode 100644
index 0000000..0fd1f02
--- /dev/null
+++ b/include/plat/arm/common/fconf_ethosn_getter.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FCONF_ETHOSN_GETTER_H
+#define FCONF_ETHOSN_GETTER_H
+
+#include <assert.h>
+
+#include <lib/fconf/fconf.h>
+
+#define hw_config__ethosn_config_getter(prop) ethosn_config.prop
+#define hw_config__ethosn_core_addr_getter(idx) __extension__ ({ \
+ assert(idx < ethosn_config.num_cores); \
+ ethosn_config.core_addr[idx]; \
+})
+
+#define ETHOSN_STATUS_DISABLED U(0)
+#define ETHOSN_STATUS_ENABLED U(1)
+
+#define ETHOSN_CORE_NUM_MAX U(64)
+
+struct ethosn_config_t {
+ uint8_t status;
+ uint32_t num_cores;
+ uint64_t core_addr[ETHOSN_CORE_NUM_MAX];
+};
+
+int fconf_populate_arm_ethosn(uintptr_t config);
+
+extern struct ethosn_config_t ethosn_config;
+
+#endif /* FCONF_ETHOSN_GETTER_H */
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index 95fc18e..0a19d8b 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -152,6 +152,11 @@
/* IO storage utility functions */
int arm_io_setup(void);
+/* Set image specification in IO block policy */
+int arm_set_image_source(unsigned int image_id, const char *part_name,
+ uintptr_t *dev_handle, uintptr_t *image_spec);
+void arm_set_fip_addr(uint32_t active_fw_bank_idx);
+
/* Security utility functions */
void arm_tzc400_setup(uintptr_t tzc_base,
const arm_tzc_regions_info_t *tzc_regions);
diff --git a/include/plat/arm/common/smccc_def.h b/include/plat/arm/common/smccc_def.h
index 6e698e5..0f4e573 100644
--- a/include/plat/arm/common/smccc_def.h
+++ b/include/plat/arm/common/smccc_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,7 +9,5 @@
/* Defines used to retrieve ARM SOC revision */
#define ARM_SOC_CONTINUATION_CODE U(0x4)
#define ARM_SOC_IDENTIFICATION_CODE U(0x3B)
-#define ARM_SOC_CONTINUATION_SHIFT U(24)
-#define ARM_SOC_IDENTIFICATION_SHIFT U(16)
#endif /* SMCCC_DEF_H */
diff --git a/include/plat/arm/css/common/css_def.h b/include/plat/arm/css/common/css_def.h
index d599352..dde174c 100644
--- a/include/plat/arm/css/common/css_def.h
+++ b/include/plat/arm/css/common/css_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -137,6 +137,8 @@
#define SSC_DBGCFG_SET 0x14
#define SSC_DBGCFG_CLR 0x18
+#define SPNIDEN_INT_CLR_SHIFT 4
+#define SPNIDEN_SEL_SET_SHIFT 5
#define SPIDEN_INT_CLR_SHIFT 6
#define SPIDEN_SEL_SET_SHIFT 7
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index 1def86e..434835e 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -16,6 +16,7 @@
#if TRNG_SUPPORT
#include "plat_trng.h"
#endif
+#include <drivers/fwu/fwu_metadata.h>
/*******************************************************************************
* Forward declarations
@@ -140,6 +141,8 @@
void plat_sdei_handle_masked_trigger(uint64_t mpidr, unsigned int intr);
#endif
+void plat_default_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
+ void *handle, uint64_t flags);
void plat_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
void *handle, uint64_t flags);
@@ -349,4 +352,12 @@
*/
int32_t plat_is_smccc_feature_available(u_register_t fid);
+/*******************************************************************************
+ * FWU platform specific functions
+ ******************************************************************************/
+int plat_fwu_set_metadata_image_source(unsigned int image_id,
+ uintptr_t *dev_handle,
+ uintptr_t *image_spec);
+void plat_fwu_set_images_source(struct fwu_metadata *metadata);
+
#endif /* PLATFORM_H */
diff --git a/include/plat/marvell/armada/a3k/common/plat_marvell.h b/include/plat/marvell/armada/a3k/common/plat_marvell.h
index ea7cdcd..cb31481 100644
--- a/include/plat/marvell/armada/a3k/common/plat_marvell.h
+++ b/include/plat/marvell/armada/a3k/common/plat_marvell.h
@@ -100,4 +100,6 @@
const mmap_region_t *plat_marvell_get_mmap(void);
+uint32_t get_ref_clk(void);
+
#endif /* PLAT_MARVELL_H */
diff --git a/include/plat/marvell/armada/a8k/common/efuse_def.h b/include/plat/marvell/armada/a8k/common/efuse_def.h
new file mode 100644
index 0000000..ff1d4a3
--- /dev/null
+++ b/include/plat/marvell/armada/a8k/common/efuse_def.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2021 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#ifndef EFUSE_DEF_H
+#define EFUSE_DEF_H
+
+#include <platform_def.h>
+
+#define MVEBU_AP_EFUSE_SRV_CTRL_REG (MVEBU_AP_GEN_MGMT_BASE + 0x8)
+#define EFUSE_SRV_CTRL_LD_SELECT_OFFS 6
+#define EFUSE_SRV_CTRL_LD_SELECT_MASK (1 << EFUSE_SRV_CTRL_LD_SELECT_OFFS)
+
+#define MVEBU_AP_LD_EFUSE_BASE (MVEBU_AP_GEN_MGMT_BASE + 0xF00)
+/* Bits [31:0] - 32 data bits total */
+#define MVEBU_AP_LDX_31_0_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE)
+/* Bits [62:32] - 31 data bits total 32nd bit is parity for bits [62:0]*/
+#define MVEBU_AP_LDX_62_32_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x4)
+/* Bits [94:63] - 32 data bits total */
+#define MVEBU_AP_LDX_94_63_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x8)
+/* Bits [125:95] - 31 data bits total, 32nd bit is parity for bits [125:63] */
+#define MVEBU_AP_LDX_125_95_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0xC)
+/* Bits [157:126] - 32 data bits total */
+#define MVEBU_AP_LDX_126_157_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x10)
+/* Bits [188:158] - 31 data bits total, 32nd bit is parity for bits [188:126] */
+#define MVEBU_AP_LDX_188_158_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x14)
+/* Bits [220:189] - 32 data bits total */
+#define MVEBU_AP_LDX_220_189_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x18)
+
+#endif /* EFUSE_DEF_H */
diff --git a/include/services/ffa_svc.h b/include/services/ffa_svc.h
index 0513eab..ab36d9e 100644
--- a/include/services/ffa_svc.h
+++ b/include/services/ffa_svc.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,7 +22,7 @@
/* The macros below are used to identify FFA calls from the SMC function ID */
#define FFA_FNUM_MIN_VALUE U(0x60)
-#define FFA_FNUM_MAX_VALUE U(0x7f)
+#define FFA_FNUM_MAX_VALUE U(0x87)
#define is_ffa_fid(fid) __extension__ ({ \
__typeof__(fid) _fid = (fid); \
((GET_SMC_NUM(_fid) >= FFA_FNUM_MIN_VALUE) && \
@@ -32,7 +32,7 @@
#define FFA_VERSION_MAJOR U(1)
#define FFA_VERSION_MAJOR_SHIFT 16
#define FFA_VERSION_MAJOR_MASK U(0x7FFF)
-#define FFA_VERSION_MINOR U(0)
+#define FFA_VERSION_MINOR U(1)
#define FFA_VERSION_MINOR_SHIFT 0
#define FFA_VERSION_MINOR_MASK U(0xFFFF)
#define FFA_VERSION_BIT31_MASK U(0x1u << 31)
@@ -61,30 +61,44 @@
((func_num) << FUNCID_NUM_SHIFT))
/* FFA function numbers */
-#define FFA_FNUM_ERROR U(0x60)
-#define FFA_FNUM_SUCCESS U(0x61)
-#define FFA_FNUM_INTERRUPT U(0x62)
-#define FFA_FNUM_VERSION U(0x63)
-#define FFA_FNUM_FEATURES U(0x64)
-#define FFA_FNUM_RX_RELEASE U(0x65)
-#define FFA_FNUM_RXTX_MAP U(0x66)
-#define FFA_FNUM_RXTX_UNMAP U(0x67)
-#define FFA_FNUM_PARTITION_INFO_GET U(0x68)
-#define FFA_FNUM_ID_GET U(0x69)
-#define FFA_FNUM_MSG_POLL U(0x6A)
-#define FFA_FNUM_MSG_WAIT U(0x6B)
-#define FFA_FNUM_MSG_YIELD U(0x6C)
-#define FFA_FNUM_MSG_RUN U(0x6D)
-#define FFA_FNUM_MSG_SEND U(0x6E)
-#define FFA_FNUM_MSG_SEND_DIRECT_REQ U(0x6F)
-#define FFA_FNUM_MSG_SEND_DIRECT_RESP U(0x70)
-#define FFA_FNUM_MEM_DONATE U(0x71)
-#define FFA_FNUM_MEM_LEND U(0x72)
-#define FFA_FNUM_MEM_SHARE U(0x73)
-#define FFA_FNUM_MEM_RETRIEVE_REQ U(0x74)
-#define FFA_FNUM_MEM_RETRIEVE_RESP U(0x75)
-#define FFA_FNUM_MEM_RELINQUISH U(0x76)
-#define FFA_FNUM_MEM_RECLAIM U(0x77)
+#define FFA_FNUM_ERROR U(0x60)
+#define FFA_FNUM_SUCCESS U(0x61)
+#define FFA_FNUM_INTERRUPT U(0x62)
+#define FFA_FNUM_VERSION U(0x63)
+#define FFA_FNUM_FEATURES U(0x64)
+#define FFA_FNUM_RX_RELEASE U(0x65)
+#define FFA_FNUM_RXTX_MAP U(0x66)
+#define FFA_FNUM_RXTX_UNMAP U(0x67)
+#define FFA_FNUM_PARTITION_INFO_GET U(0x68)
+#define FFA_FNUM_ID_GET U(0x69)
+#define FFA_FNUM_MSG_POLL U(0x6A) /* Legacy FF-A v1.0 */
+#define FFA_FNUM_MSG_WAIT U(0x6B)
+#define FFA_FNUM_MSG_YIELD U(0x6C)
+#define FFA_FNUM_MSG_RUN U(0x6D)
+#define FFA_FNUM_MSG_SEND U(0x6E) /* Legacy FF-A v1.0 */
+#define FFA_FNUM_MSG_SEND_DIRECT_REQ U(0x6F)
+#define FFA_FNUM_MSG_SEND_DIRECT_RESP U(0x70)
+#define FFA_FNUM_MEM_DONATE U(0x71)
+#define FFA_FNUM_MEM_LEND U(0x72)
+#define FFA_FNUM_MEM_SHARE U(0x73)
+#define FFA_FNUM_MEM_RETRIEVE_REQ U(0x74)
+#define FFA_FNUM_MEM_RETRIEVE_RESP U(0x75)
+#define FFA_FNUM_MEM_RELINQUISH U(0x76)
+#define FFA_FNUM_MEM_RECLAIM U(0x77)
+#define FFA_FNUM_NORMAL_WORLD_RESUME U(0x7C)
+
+/* FF-A v1.1 */
+#define FFA_FNUM_NOTIFICATION_BITMAP_CREATE U(0x7D)
+#define FFA_FNUM_NOTIFICATION_BITMAP_DESTROY U(0x7E)
+#define FFA_FNUM_NOTIFICATION_BIND U(0x7F)
+#define FFA_FNUM_NOTIFICATION_UNBIND U(0x80)
+#define FFA_FNUM_NOTIFICATION_SET U(0x81)
+#define FFA_FNUM_NOTIFICATION_GET U(0x82)
+#define FFA_FNUM_NOTIFICATION_INFO_GET U(0x83)
+#define FFA_FNUM_RX_ACQUIRE U(0x84)
+#define FFA_FNUM_SPM_ID_GET U(0x85)
+#define FFA_FNUM_MSG_SEND2 U(0x86)
+#define FFA_FNUM_SECONDARY_EP_REGISTER U(0x87)
/* FFA SMC32 FIDs */
#define FFA_ERROR FFA_FID(SMC_32, FFA_FNUM_ERROR)
@@ -114,8 +128,10 @@
#define FFA_MEM_RETRIEVE_RESP FFA_FID(SMC_32, FFA_FNUM_MEM_RETRIEVE_RESP)
#define FFA_MEM_RELINQUISH FFA_FID(SMC_32, FFA_FNUM_MEM_RELINQUISH)
#define FFA_MEM_RECLAIM FFA_FID(SMC_32, FFA_FNUM_MEM_RECLAIM)
+#define FFA_SPM_ID_GET FFA_FID(SMC_32, FFA_FNUM_SPM_ID_GET)
/* FFA SMC64 FIDs */
+#define FFA_ERROR_SMC64 FFA_FID(SMC_64, FFA_FNUM_ERROR)
#define FFA_SUCCESS_SMC64 FFA_FID(SMC_64, FFA_FNUM_SUCCESS)
#define FFA_RXTX_MAP_SMC64 FFA_FID(SMC_64, FFA_FNUM_RXTX_MAP)
#define FFA_MSG_SEND_DIRECT_REQ_SMC64 \
@@ -127,6 +143,8 @@
#define FFA_MEM_SHARE_SMC64 FFA_FID(SMC_64, FFA_FNUM_MEM_SHARE)
#define FFA_MEM_RETRIEVE_REQ_SMC64 \
FFA_FID(SMC_64, FFA_FNUM_MEM_RETRIEVE_REQ)
+#define FFA_SECONDARY_EP_REGISTER_SMC64 \
+ FFA_FID(SMC_64, FFA_FNUM_SECONDARY_EP_REGISTER)
/*
* Reserve a special value for traffic targeted to the Hypervisor or SPM.
diff --git a/include/services/pci_svc.h b/include/services/pci_svc.h
new file mode 100644
index 0000000..664a742
--- /dev/null
+++ b/include/services/pci_svc.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PCI_SVC_H
+#define PCI_SVC_H
+
+#include <lib/utils_def.h>
+
+/* SMCCC PCI platform functions */
+#define SMC_PCI_VERSION U(0x84000130)
+#define SMC_PCI_FEATURES U(0x84000131)
+#define SMC_PCI_READ U(0x84000132)
+#define SMC_PCI_WRITE U(0x84000133)
+#define SMC_PCI_SEG_INFO U(0x84000134)
+
+#define is_pci_fid(_fid) (((_fid) >= SMC_PCI_VERSION) && \
+ ((_fid) <= SMC_PCI_SEG_INFO))
+
+uint64_t pci_smc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
+ u_register_t x3, u_register_t x4, void *cookie,
+ void *handle, u_register_t flags);
+
+#define PCI_ADDR_FUN(dev) ((dev) & U(0x7))
+#define PCI_ADDR_DEV(dev) (((dev) >> U(3)) & U(0x001F))
+#define PCI_ADDR_BUS(dev) (((dev) >> U(8)) & U(0x00FF))
+#define PCI_ADDR_SEG(dev) (((dev) >> U(16)) & U(0xFFFF))
+#define PCI_OFFSET_MASK U(0xFFF)
+typedef union {
+ struct {
+ uint16_t minor;
+ uint16_t major;
+ } __packed;
+ uint32_t val;
+} pcie_version;
+
+/*
+ * platforms are responsible for providing implementations of these
+ * three functions in a manner which conforms to the Arm PCI Configuration
+ * Space Access Firmware Interface (DEN0115) and the PCIe specification's
+ * sections on PCI configuration access. See the rpi4_pci_svc.c example.
+ */
+uint32_t pci_read_config(uint32_t addr, uint32_t off, uint32_t sz, uint32_t *val);
+uint32_t pci_write_config(uint32_t addr, uint32_t off, uint32_t sz, uint32_t val);
+uint32_t pci_get_bus_for_seg(uint32_t seg, uint32_t *bus_range, uint32_t *nseg);
+
+/* Return codes for Arm PCI Config Space Access Firmware SMC calls */
+#define SMC_PCI_CALL_SUCCESS U(0)
+#define SMC_PCI_CALL_NOT_SUPPORTED -1
+#define SMC_PCI_CALL_INVAL_PARAM -2
+#define SMC_PCI_CALL_NOT_IMPL -3
+
+#define SMC_PCI_SZ_8BIT U(1)
+#define SMC_PCI_SZ_16BIT U(2)
+#define SMC_PCI_SZ_32BIT U(4)
+
+#endif /* PCI_SVC_H */
diff --git a/include/tools_share/firmware_image_package.h b/include/tools_share/firmware_image_package.h
index bcde04f..dc65cc6 100644
--- a/include/tools_share/firmware_image_package.h
+++ b/include/tools_share/firmware_image_package.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -82,6 +82,10 @@
#define UUID_FW_CONFIG \
{{0x58, 0x07, 0xe1, 0x6a}, {0x84, 0x59}, {0x47, 0xbe}, 0x8e, 0xd5, {0x64, 0x8e, 0x8d, 0xdd, 0xab, 0x0e} }
+#ifdef PLAT_DEF_FIP_UUID
+#include <plat_def_fip_uuid.h>
+#endif
+
typedef struct fip_toc_header {
uint32_t name;
uint32_t serial_number;
diff --git a/include/tools_share/tbbr_oid.h b/include/tools_share/tbbr_oid.h
index c789f79..52b43ab 100644
--- a/include/tools_share/tbbr_oid.h
+++ b/include/tools_share/tbbr_oid.h
@@ -160,4 +160,7 @@
#define SP_PKG7_HASH_OID "1.3.6.1.4.1.4128.2100.1307"
#define SP_PKG8_HASH_OID "1.3.6.1.4.1.4128.2100.1308"
+#ifdef PLAT_DEF_OID
+#include <platform_oid.h>
+#endif
#endif /* TBBR_OID_H */
diff --git a/include/tools_share/uuid.h b/include/tools_share/uuid.h
index 36be9ed..2ced3a3 100644
--- a/include/tools_share/uuid.h
+++ b/include/tools_share/uuid.h
@@ -56,9 +56,16 @@
uint8_t node[_UUID_NODE_LEN];
};
+struct efi_guid {
+ uint32_t time_low;
+ uint16_t time_mid;
+ uint16_t time_hi_and_version;
+ uint8_t clock_seq_and_node[8];
+};
+
union uuid_helper_t {
struct uuid uuid_struct;
- uint32_t word[4];
+ struct efi_guid efi_guid;
};
/* XXX namespace pollution? */
diff --git a/lib/aarch32/misc_helpers.S b/lib/aarch32/misc_helpers.S
index e9734ac..8b16f93 100644
--- a/lib/aarch32/misc_helpers.S
+++ b/lib/aarch32/misc_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,6 +7,8 @@
#include <arch.h>
#include <asm_macros.S>
#include <assert_macros.S>
+#include <common/bl_common.h>
+#include <lib/xlat_tables/xlat_tables_defs.h>
.globl smc
.globl zeromem
@@ -14,6 +16,9 @@
.globl memcpy4
.globl disable_mmu_icache_secure
.globl disable_mmu_secure
+ .globl fixup_gdt_reloc
+
+#define PAGE_START_MASK ~(PAGE_SIZE_MASK)
func smc
/*
@@ -187,3 +192,124 @@
ldr r1, =(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
b do_disable_mmu
endfunc disable_mmu_icache_secure
+
+/* ---------------------------------------------------------------------------
+ * Helper to fixup Global Descriptor table (GDT) and dynamic relocations
+ * (.rel.dyn) at runtime.
+ *
+ * This function is meant to be used when the firmware is compiled with -fpie
+ * and linked with -pie options. We rely on the linker script exporting
+ * appropriate markers for start and end of the section. For GOT, we
+ * expect __GOT_START__ and __GOT_END__. Similarly for .rela.dyn, we expect
+ * __RELA_START__ and __RELA_END__.
+ *
+ * The function takes the limits of the memory to apply fixups to as
+ * arguments (which is usually the limits of the relocable BL image).
+ * r0 - the start of the fixup region
+ * r1 - the limit of the fixup region
+ * These addresses have to be 4KB page aligned.
+ * ---------------------------------------------------------------------------
+ */
+
+/* Relocation codes */
+#define R_ARM_RELATIVE 23
+
+func fixup_gdt_reloc
+ mov r6, r0
+ mov r7, r1
+
+#if ENABLE_ASSERTIONS
+ /* Test if the limits are 4K aligned */
+ orr r0, r0, r1
+ mov r1, #(PAGE_SIZE_MASK)
+ tst r0, r1
+ ASM_ASSERT(eq)
+#endif
+ /*
+ * Calculate the offset based on return address in lr.
+ * Assume that this function is called within a page at the start of
+ * fixup region.
+ */
+ ldr r1, =PAGE_START_MASK
+ and r2, lr, r1
+ subs r0, r2, r6 /* Diff(S) = Current Address - Compiled Address */
+ beq 3f /* Diff(S) = 0. No relocation needed */
+
+ ldr r1, =__GOT_START__
+ add r1, r1, r0
+ ldr r2, =__GOT_END__
+ add r2, r2, r0
+
+ /*
+ * GOT is an array of 32_bit addresses which must be fixed up as
+ * new_addr = old_addr + Diff(S).
+ * The new_addr is the address currently the binary is executing from
+ * and old_addr is the address at compile time.
+ */
+1: ldr r3, [r1]
+
+ /* Skip adding offset if address is < lower limit */
+ cmp r3, r6
+ blo 2f
+
+ /* Skip adding offset if address is > upper limit */
+ cmp r3, r7
+ bhi 2f
+ add r3, r3, r0
+ str r3, [r1]
+
+2: add r1, r1, #4
+ cmp r1, r2
+ blo 1b
+
+ /* Starting dynamic relocations. Use ldr to get RELA_START and END */
+3: ldr r1, =__RELA_START__
+ add r1, r1, r0
+ ldr r2, =__RELA_END__
+ add r2, r2, r0
+
+ /*
+ * According to ELF-32 specification, the RELA data structure is as
+ * follows:
+ * typedef struct {
+ * Elf32_Addr r_offset;
+ * Elf32_Xword r_info;
+ * } Elf32_Rela;
+ *
+ * r_offset is address of reference
+ * r_info is symbol index and type of relocation (in this case
+ * code 23 which corresponds to R_ARM_RELATIVE).
+ *
+ * Size of Elf32_Rela structure is 8 bytes.
+ */
+
+ /* Skip R_ARM_NONE entry with code 0 */
+1: ldr r3, [r1, #4]
+ ands r3, r3, #0xff
+ beq 2f
+
+#if ENABLE_ASSERTIONS
+ /* Assert that the relocation type is R_ARM_RELATIVE */
+ cmp r3, #R_ARM_RELATIVE
+ ASM_ASSERT(eq)
+#endif
+ ldr r3, [r1] /* r_offset */
+ add r3, r0, r3 /* Diff(S) + r_offset */
+ ldr r4, [r3]
+
+ /* Skip adding offset if address is < lower limit */
+ cmp r4, r6
+ blo 2f
+
+ /* Skip adding offset if address is >= upper limit */
+ cmp r4, r7
+ bhs 2f
+
+ add r4, r0, r4
+ str r4, [r3]
+
+2: add r1, r1, #8
+ cmp r1, r2
+ blo 1b
+ bx lr
+endfunc fixup_gdt_reloc
diff --git a/lib/cpus/aarch32/cpu_helpers.S b/lib/cpus/aarch32/cpu_helpers.S
index 9b5d787..6ed800c 100644
--- a/lib/cpus/aarch32/cpu_helpers.S
+++ b/lib/cpus/aarch32/cpu_helpers.S
@@ -78,6 +78,10 @@
mov r1, #CPU_PWR_DWN_OPS
add r1, r1, r2, lsl #2
ldr r1, [r0, r1]
+#if ENABLE_ASSERTIONS
+ cmp r1, #0
+ ASM_ASSERT(ne)
+#endif
bx r1
endfunc prepare_cpu_pwr_dwn
@@ -146,6 +150,10 @@
/* Subtract the increment and offset to get the cpu-ops pointer */
sub r0, r4, #(CPU_OPS_SIZE + CPU_MIDR)
+#if ENABLE_ASSERTIONS
+ cmp r0, #0
+ ASM_ASSERT(ne)
+#endif
error_exit:
bx lr
endfunc get_cpu_ops_ptr
@@ -224,7 +232,15 @@
* function. If it's non-NULL, jump to the function in turn.
*/
bl _cpu_data
+#if ENABLE_ASSERTIONS
+ cmp r0, #0
+ ASM_ASSERT(ne)
+#endif
ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR]
+#if ENABLE_ASSERTIONS
+ cmp r1, #0
+ ASM_ASSERT(ne)
+#endif
ldr r0, [r1, #CPU_ERRATA_FUNC]
cmp r0, #0
beq 1f
diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S
new file mode 100644
index 0000000..3310322
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_a510.S
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_a510.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex A510 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Cortex A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func cortex_a510_core_pwr_dwn
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ mrs x0, CORTEX_A510_CPUPWRCTLR_EL1
+ orr x0, x0, #CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ msr CORTEX_A510_CPUPWRCTLR_EL1, x0
+ isb
+ ret
+endfunc cortex_a510_core_pwr_dwn
+
+ /*
+ * Errata printing function for Cortex A510. Must follow AAPCS.
+ */
+#if REPORT_ERRATA
+func cortex_a510_errata_report
+ ret
+endfunc cortex_a510_errata_report
+#endif
+
+func cortex_a510_reset_func
+ /* Disable speculative loads */
+ msr SSBS, xzr
+ isb
+ ret
+endfunc cortex_a510_reset_func
+
+ /* ---------------------------------------------
+ * This function provides Cortex-A510 specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.cortex_a510_regs, "aS"
+cortex_a510_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func cortex_a510_cpu_reg_dump
+ adr x6, cortex_a510_regs
+ mrs x8, CORTEX_A510_CPUECTLR_EL1
+ ret
+endfunc cortex_a510_cpu_reg_dump
+
+declare_cpu_ops cortex_a510, CORTEX_A510_MIDR, \
+ cortex_a510_reset_func, \
+ cortex_a510_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S
new file mode 100644
index 0000000..75b7647
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_a710.S
@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_a710.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+/* --------------------------------------------------
+ * Errata Workaround for Cortex-A710 Erratum 1987031.
+ * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. It is still
+ * open.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_a710_1987031_wa
+ /* Check revision. */
+ mov x17, x30
+ bl check_errata_1987031
+ cbz x0, 1f
+
+ /* Apply instruction patching sequence */
+ ldr x0,=0x6
+ msr S3_6_c15_c8_0,x0
+ ldr x0,=0xF3A08002
+ msr S3_6_c15_c8_2,x0
+ ldr x0,=0xFFF0F7FE
+ msr S3_6_c15_c8_3,x0
+ ldr x0,=0x40000001003ff
+ msr S3_6_c15_c8_1,x0
+ ldr x0,=0x7
+ msr S3_6_c15_c8_0,x0
+ ldr x0,=0xBF200000
+ msr S3_6_c15_c8_2,x0
+ ldr x0,=0xFFEF0000
+ msr S3_6_c15_c8_3,x0
+ ldr x0,=0x40000001003f3
+ msr S3_6_c15_c8_1,x0
+ isb
+1:
+ ret x17
+endfunc errata_a710_1987031_wa
+
+func check_errata_1987031
+ /* Applies to r0p0, r1p0 and r2p0 */
+ mov x1, #0x20
+ b cpu_rev_var_ls
+endfunc check_errata_1987031
+
+/* --------------------------------------------------
+ * Errata Workaround for Cortex-A710 Erratum 2081180.
+ * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710.
+ * It is still open.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_a710_2081180_wa
+ /* Check revision. */
+ mov x17, x30
+ bl check_errata_2081180
+ cbz x0, 1f
+
+ /* Apply instruction patching sequence */
+ ldr x0,=0x3
+ msr S3_6_c15_c8_0,x0
+ ldr x0,=0xF3A08002
+ msr S3_6_c15_c8_2,x0
+ ldr x0,=0xFFF0F7FE
+ msr S3_6_c15_c8_3,x0
+ ldr x0,=0x10002001003FF
+ msr S3_6_c15_c8_1,x0
+ ldr x0,=0x4
+ msr S3_6_c15_c8_0,x0
+ ldr x0,=0xBF200000
+ msr S3_6_c15_c8_2,x0
+ ldr x0,=0xFFEF0000
+ msr S3_6_c15_c8_3,x0
+ ldr x0,=0x10002001003F3
+ msr S3_6_c15_c8_1,x0
+ isb
+1:
+ ret x17
+endfunc errata_a710_2081180_wa
+
+func check_errata_2081180
+ /* Applies to r0p0, r1p0 and r2p0 */
+ mov x1, #0x20
+ b cpu_rev_var_ls
+endfunc check_errata_2081180
+
+/* ---------------------------------------------------------------------
+ * Errata Workaround for Cortex-A710 Erratum 2055002.
+ * This applies to revision r1p0, r2p0 of Cortex-A710 and is still open.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * ---------------------------------------------------------------------
+ */
+func errata_a710_2055002_wa
+ /* Compare x0 against revision r2p0 */
+ mov x17, x30
+ bl check_errata_2055002
+ cbz x0, 1f
+ mrs x1, CORTEX_A710_CPUACTLR_EL1
+ orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_46
+ msr CORTEX_A710_CPUACTLR_EL1, x1
+1:
+ ret x17
+endfunc errata_a710_2055002_wa
+
+func check_errata_2055002
+ /* Applies to r1p0, r2p0 */
+ mov x1, #0x20
+ b cpu_rev_var_ls
+endfunc check_errata_2055002
+
+/* -------------------------------------------------------------
+ * Errata Workaround for Cortex-A710 Erratum 2017096.
+ * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * -------------------------------------------------------------
+ */
+func errata_a710_2017096_wa
+ /* Compare x0 against revision r0p0 to r2p0 */
+ mov x17, x30
+ bl check_errata_2017096
+ cbz x0, 1f
+ mrs x1, CORTEX_A710_CPUECTLR_EL1
+ orr x1, x1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT
+ msr CORTEX_A710_CPUECTLR_EL1, x1
+
+1:
+ ret x17
+endfunc errata_a710_2017096_wa
+
+func check_errata_2017096
+ /* Applies to r0p0, r1p0, r2p0 */
+ mov x1, #0x20
+ b cpu_rev_var_ls
+endfunc check_errata_2017096
+
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func cortex_a710_core_pwr_dwn
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ mrs x0, CORTEX_A710_CPUPWRCTLR_EL1
+ orr x0, x0, #CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ msr CORTEX_A710_CPUPWRCTLR_EL1, x0
+ isb
+ ret
+endfunc cortex_a710_core_pwr_dwn
+
+#if REPORT_ERRATA
+ /*
+ * Errata printing function for Cortex-A710. Must follow AAPCS.
+ */
+func cortex_a710_errata_report
+ stp x8, x30, [sp, #-16]!
+
+ bl cpu_get_rev_var
+ mov x8, x0
+
+ /*
+ * Report all errata. The revision-variant information is passed to
+ * checking functions of each errata.
+ */
+ report_errata ERRATA_A710_1987031, cortex_a710, 1987031
+ report_errata ERRATA_A710_2081180, cortex_a710, 2081180
+ report_errata ERRATA_A710_2055002, cortex_a710, 2055002
+ report_errata ERRATA_A710_2017096, cortex_a710, 2017096
+
+ ldp x8, x30, [sp], #16
+ ret
+endfunc cortex_a710_errata_report
+#endif
+
+func cortex_a710_reset_func
+ mov x19, x30
+
+ /* Disable speculative loads */
+ msr SSBS, xzr
+
+ bl cpu_get_rev_var
+ mov x18, x0
+
+#if ERRATA_A710_1987031
+ mov x0, x18
+ bl errata_a710_1987031_wa
+#endif
+
+#if ERRATA_A710_2081180
+ mov x0, x18
+ bl errata_a710_2081180_wa
+#endif
+
+#if ERRATA_A710_2055002
+ mov x0, x18
+ bl errata_a710_2055002_wa
+#endif
+
+#if ERRATA_A710_2017096
+ mov x0, x18
+ bl errata_a710_2017096_wa
+#endif
+ isb
+ ret x19
+endfunc cortex_a710_reset_func
+
+ /* ---------------------------------------------
+ * This function provides Cortex-A710 specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.cortex_a710_regs, "aS"
+cortex_a710_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func cortex_a710_cpu_reg_dump
+ adr x6, cortex_a710_regs
+ mrs x8, CORTEX_A710_CPUECTLR_EL1
+ ret
+endfunc cortex_a710_cpu_reg_dump
+
+declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \
+ cortex_a710_reset_func, \
+ cortex_a710_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S
index e3a6f5f..8c8f4d3 100644
--- a/lib/cpus/aarch64/cortex_a77.S
+++ b/lib/cpus/aarch64/cortex_a77.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -114,6 +114,86 @@
b cpu_rev_var_ls
endfunc check_errata_1925769
+ /* --------------------------------------------------
+ * Errata Workaround for Cortex A77 Errata #1946167.
+ * This applies to revision <= r1p1 of Cortex A77.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_a77_1946167_wa
+ /* Compare x0 against revision <= r1p1 */
+ mov x17, x30
+ bl check_errata_1946167
+ cbz x0, 1f
+
+ ldr x0,=0x4
+ msr CORTEX_A77_CPUPSELR_EL3,x0
+ ldr x0,=0x10E3900002
+ msr CORTEX_A77_CPUPOR_EL3,x0
+ ldr x0,=0x10FFF00083
+ msr CORTEX_A77_CPUPMR_EL3,x0
+ ldr x0,=0x2001003FF
+ msr CORTEX_A77_CPUPCR_EL3,x0
+
+ ldr x0,=0x5
+ msr CORTEX_A77_CPUPSELR_EL3,x0
+ ldr x0,=0x10E3800082
+ msr CORTEX_A77_CPUPOR_EL3,x0
+ ldr x0,=0x10FFF00083
+ msr CORTEX_A77_CPUPMR_EL3,x0
+ ldr x0,=0x2001003FF
+ msr CORTEX_A77_CPUPCR_EL3,x0
+
+ ldr x0,=0x6
+ msr CORTEX_A77_CPUPSELR_EL3,x0
+ ldr x0,=0x10E3800200
+ msr CORTEX_A77_CPUPOR_EL3,x0
+ ldr x0,=0x10FFF003E0
+ msr CORTEX_A77_CPUPMR_EL3,x0
+ ldr x0,=0x2001003FF
+ msr CORTEX_A77_CPUPCR_EL3,x0
+
+ isb
+1:
+ ret x17
+endfunc errata_a77_1946167_wa
+
+func check_errata_1946167
+ /* Applies to everything <= r1p1 */
+ mov x1, #0x11
+ b cpu_rev_var_ls
+endfunc check_errata_1946167
+
+ /* --------------------------------------------------
+ * Errata Workaround for Cortex A77 Errata #1791578.
+ * This applies to revisions r0p0, r1p0, and r1p1 and is still open.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_a77_1791578_wa
+ /* Check workaround compatibility. */
+ mov x17, x30
+ bl check_errata_1791578
+ cbz x0, 1f
+
+ /* Set bit 2 in ACTLR2_EL1 */
+ mrs x1, CORTEX_A77_ACTLR2_EL1
+ orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_2
+ msr CORTEX_A77_ACTLR2_EL1, x1
+ isb
+1:
+ ret x17
+endfunc errata_a77_1791578_wa
+
+func check_errata_1791578
+ /* Applies to r0p0, r1p0, and r1p1 right now */
+ mov x1, #0x11
+ b cpu_rev_var_ls
+endfunc check_errata_1791578
+
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A77.
* Shall clobber: x0-x19
@@ -134,6 +214,16 @@
bl errata_a77_1925769_wa
#endif
+#if ERRATA_A77_1946167
+ mov x0, x18
+ bl errata_a77_1946167_wa
+#endif
+
+#if ERRATA_A77_1791578
+ mov x0, x18
+ bl errata_a77_1791578_wa
+#endif
+
ret x19
endfunc cortex_a77_reset_func
@@ -169,6 +259,8 @@
*/
report_errata ERRATA_A77_1508412, cortex_a77, 1508412
report_errata ERRATA_A77_1925769, cortex_a77, 1925769
+ report_errata ERRATA_A77_1946167, cortex_a77, 1946167
+ report_errata ERRATA_A77_1791578, cortex_a77, 1791578
ldp x8, x30, [sp], #16
ret
diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S
index f61726b..3a74571 100644
--- a/lib/cpus/aarch64/cortex_a78.S
+++ b/lib/cpus/aarch64/cortex_a78.S
@@ -44,13 +44,13 @@
b cpu_rev_var_ls
endfunc check_errata_1688305
- /* --------------------------------------------------
- * Errata Workaround for Cortex A78 Errata #1941498.
- * This applies to revisions r0p0, r1p0, and r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
+/* --------------------------------------------------
+ * Errata Workaround for Cortex A78 Errata #1941498.
+ * This applies to revisions r0p0, r1p0, and r1p1.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
func errata_a78_1941498_wa
/* Compare x0 against revision <= r1p1 */
mov x17, x30
@@ -72,16 +72,16 @@
b cpu_rev_var_ls
endfunc check_errata_1941498
- /* --------------------------------------------------
- * Errata Workaround for A78 Erratum 1951500.
- * This applies to revisions r1p0 and r1p1 of A78.
- * The issue also exists in r0p0 but there is no fix
- * in that revision.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
+/* --------------------------------------------------
+ * Errata Workaround for A78 Erratum 1951500.
+ * This applies to revisions r1p0 and r1p1 of A78.
+ * The issue also exists in r0p0 but there is no fix
+ * in that revision.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
func errata_a78_1951500_wa
/* Compare x0 against revisions r1p0 - r1p1 */
mov x17, x30
@@ -126,6 +126,78 @@
b cpu_rev_var_range
endfunc check_errata_1951500
+/* --------------------------------------------------
+ * Errata Workaround for Cortex A78 Errata #1821534.
+ * This applies to revisions r0p0 and r1p0.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_a78_1821534_wa
+ /* Check revision. */
+ mov x17, x30
+ bl check_errata_1821534
+ cbz x0, 1f
+
+ /* Set bit 2 in ACTLR2_EL1 */
+ mrs x1, CORTEX_A78_ACTLR2_EL1
+ orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_2
+ msr CORTEX_A78_ACTLR2_EL1, x1
+ isb
+1:
+ ret x17
+endfunc errata_a78_1821534_wa
+
+func check_errata_1821534
+ /* Applies to r0p0 and r1p0 */
+ mov x1, #0x10
+ b cpu_rev_var_ls
+endfunc check_errata_1821534
+
+/* --------------------------------------------------
+ * Errata Workaround for Cortex A78 Errata 1952683.
+ * This applies to revision r0p0.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_a78_1952683_wa
+ /* Check revision. */
+ mov x17, x30
+ bl check_errata_1952683
+ cbz x0, 1f
+
+ ldr x0,=0x5
+ msr S3_6_c15_c8_0,x0
+ ldr x0,=0xEEE10A10
+ msr S3_6_c15_c8_2,x0
+ ldr x0,=0xFFEF0FFF
+ msr S3_6_c15_c8_3,x0
+ ldr x0,=0x0010F000
+ msr S3_6_c15_c8_4,x0
+ ldr x0,=0x0010F000
+ msr S3_6_c15_c8_5,x0
+ ldr x0,=0x40000080023ff
+ msr S3_6_c15_c8_1,x0
+ ldr x0,=0x6
+ msr S3_6_c15_c8_0,x0
+ ldr x0,=0xEE640F34
+ msr S3_6_c15_c8_2,x0
+ ldr x0,=0xFFEF0FFF
+ msr S3_6_c15_c8_3,x0
+ ldr x0,=0x40000080023ff
+ msr S3_6_c15_c8_1,x0
+ isb
+1:
+ ret x17
+endfunc errata_a78_1952683_wa
+
+func check_errata_1952683
+ /* Applies to r0p0 only */
+ mov x1, #0x00
+ b cpu_rev_var_ls
+endfunc check_errata_1952683
+
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A78
* -------------------------------------------------
@@ -150,6 +222,16 @@
bl errata_a78_1951500_wa
#endif
+#if ERRATA_A78_1821534
+ mov x0, x18
+ bl errata_a78_1821534_wa
+#endif
+
+#if ERRATA_A78_1952683
+ mov x0, x18
+ bl errata_a78_1952683_wa
+#endif
+
#if ENABLE_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
@@ -207,6 +289,8 @@
report_errata ERRATA_A78_1688305, cortex_a78, 1688305
report_errata ERRATA_A78_1941498, cortex_a78, 1941498
report_errata ERRATA_A78_1951500, cortex_a78, 1951500
+ report_errata ERRATA_A78_1821534, cortex_a78, 1821534
+ report_errata ERRATA_A78_1952683, cortex_a78, 1952683
ldp x8, x30, [sp], #16
ret
diff --git a/lib/cpus/aarch64/cortex_a78_ae.S b/lib/cpus/aarch64/cortex_a78_ae.S
index 9aff9ac..421c174 100644
--- a/lib/cpus/aarch64/cortex_a78_ae.S
+++ b/lib/cpus/aarch64/cortex_a78_ae.S
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,12 +17,108 @@
#error "cortex_a78_ae must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
+/* --------------------------------------------------
+ * Errata Workaround for A78 AE Erratum 1941500.
+ * This applies to revisions r0p0 and r0p1 of A78 AE.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_a78_ae_1941500_wa
+ /* Compare x0 against revisions r0p0 - r0p1 */
+ mov x17, x30
+ bl check_errata_1941500
+ cbz x0, 1f
+
+ /* Set bit 8 in ECTLR_EL1 */
+ mrs x0, CORTEX_A78_AE_CPUECTLR_EL1
+ bic x0, x0, #CORTEX_A78_AE_CPUECTLR_EL1_BIT_8
+ msr CORTEX_A78_AE_CPUECTLR_EL1, x0
+ isb
+1:
+ ret x17
+endfunc errata_a78_ae_1941500_wa
+
+func check_errata_1941500
+ /* Applies to revisions r0p0 and r0p1. */
+ mov x1, #CPU_REV(0, 0)
+ mov x2, #CPU_REV(0, 1)
+ b cpu_rev_var_range
+endfunc check_errata_1941500
+
+/* --------------------------------------------------
+ * Errata Workaround for A78 AE Erratum 1951502.
+ * This applies to revisions r0p0 and r0p1 of A78 AE.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_a78_ae_1951502_wa
+ /* Compare x0 against revisions r0p0 - r0p1 */
+ mov x17, x30
+ bl check_errata_1951502
+ cbz x0, 1f
+
+ msr S3_6_c15_c8_0, xzr
+ ldr x0, =0x10E3900002
+ msr S3_6_c15_c8_2, x0
+ ldr x0, =0x10FFF00083
+ msr S3_6_c15_c8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_c15_c8_1, x0
+
+ mov x0, #1
+ msr S3_6_c15_c8_0, x0
+ ldr x0, =0x10E3800082
+ msr S3_6_c15_c8_2, x0
+ ldr x0, =0x10FFF00083
+ msr S3_6_c15_c8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_c15_c8_1, x0
+
+ mov x0, #2
+ msr S3_6_c15_c8_0, x0
+ ldr x0, =0x10E3800200
+ msr S3_6_c15_c8_2, x0
+ ldr x0, =0x10FFF003E0
+ msr S3_6_c15_c8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_c15_c8_1, x0
+
+ isb
+1:
+ ret x17
+endfunc errata_a78_ae_1951502_wa
+
+func check_errata_1951502
+ /* Applies to revisions r0p0 and r0p1. */
+ mov x1, #CPU_REV(0, 0)
+ mov x2, #CPU_REV(0, 1)
+ b cpu_rev_var_range
+endfunc check_errata_1951502
+
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A78-AE
* -------------------------------------------------
*/
-#if ENABLE_AMU
func cortex_a78_ae_reset_func
+ mov x19, x30
+ bl cpu_get_rev_var
+ mov x18, x0
+
+#if ERRATA_A78_AE_1941500
+ mov x0, x18
+ bl errata_a78_ae_1941500_wa
+#endif
+
+#if ERRATA_A78_AE_1951502
+ mov x0, x18
+ bl errata_a78_ae_1951502_wa
+#endif
+
+#if ENABLE_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, actlr_el3
bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
@@ -39,11 +136,12 @@
/* Enable group1 counters */
mov x0, #CORTEX_A78_AMU_GROUP1_MASK
msr CPUAMCNTENSET1_EL0, x0
+#endif
+
isb
- ret
+ ret x19
endfunc cortex_a78_ae_reset_func
-#endif
/* -------------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -66,6 +164,19 @@
*/
#if REPORT_ERRATA
func cortex_a78_ae_errata_report
+ stp x8, x30, [sp, #-16]!
+
+ bl cpu_get_rev_var
+ mov x8, x0
+
+ /*
+ * Report all errata. The revision-variant information is passed to
+ * checking functions of each errata.
+ */
+ report_errata ERRATA_A78_AE_1941500, cortex_a78_ae, 1941500
+ report_errata ERRATA_A78_AE_1951502, cortex_a78_ae, 1951502
+
+ ldp x8, x30, [sp], #16
ret
endfunc cortex_a78_ae_errata_report
#endif
@@ -89,12 +200,6 @@
ret
endfunc cortex_a78_ae_cpu_reg_dump
-#if ENABLE_AMU
-#define A78_AE_RESET_FUNC cortex_a78_ae_reset_func
-#else
-#define A78_AE_RESET_FUNC CPU_NO_RESET_FUNC
-#endif
-
declare_cpu_ops cortex_a78_ae, CORTEX_A78_AE_MIDR, \
- A78_AE_RESET_FUNC, \
+ cortex_a78_ae_reset_func, \
cortex_a78_ae_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S
new file mode 100644
index 0000000..1b170fe
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_a78c.S
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_a78c.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func cortex_a78c_core_pwr_dwn
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1
+ orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
+ msr CORTEX_A78C_CPUPWRCTLR_EL1, x0
+ isb
+ ret
+endfunc cortex_a78c_core_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Cortex A78C. Must follow AAPCS.
+ */
+func cortex_a78c_errata_report
+ ret
+endfunc cortex_a78c_errata_report
+#endif
+
+ /* ---------------------------------------------
+ * This function provides cortex_a78c specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.cortex_a78c_regs, "aS"
+cortex_a78c_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func cortex_a78c_cpu_reg_dump
+ adr x6, cortex_a78c_regs
+ mrs x8, CORTEX_A78C_CPUECTLR_EL1
+ ret
+endfunc cortex_a78c_cpu_reg_dump
+
+declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \
+ CPU_NO_RESET_FUNC, \
+ cortex_a78c_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_demeter.S b/lib/cpus/aarch64/cortex_demeter.S
new file mode 100644
index 0000000..9ad8b86
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_demeter.S
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_demeter.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex Demeter must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Cortex Demeter supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func cortex_demeter_core_pwr_dwn
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ mrs x0, CORTEX_DEMETER_CPUPWRCTLR_EL1
+ orr x0, x0, #CORTEX_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ msr CORTEX_DEMETER_CPUPWRCTLR_EL1, x0
+ isb
+ ret
+endfunc cortex_demeter_core_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Cortex Demeter. Must follow AAPCS.
+ */
+func cortex_demeter_errata_report
+ ret
+endfunc cortex_demeter_errata_report
+#endif
+
+func cortex_demeter_reset_func
+ /* Disable speculative loads */
+ msr SSBS, xzr
+ isb
+ ret
+endfunc cortex_demeter_reset_func
+
+ /* ---------------------------------------------
+ * This function provides Cortex Demeter-
+ * specific register information for crash
+ * reporting. It needs to return with x6
+ * pointing to a list of register names in ascii
+ * and x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.cortex_demeter_regs, "aS"
+cortex_demeter_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func cortex_demeter_cpu_reg_dump
+ adr x6, cortex_demeter_regs
+ mrs x8, CORTEX_DEMETER_CPUECTLR_EL1
+ ret
+endfunc cortex_demeter_cpu_reg_dump
+
+declare_cpu_ops cortex_demeter, CORTEX_DEMETER_MIDR, \
+ cortex_demeter_reset_func, \
+ cortex_demeter_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_klein.S b/lib/cpus/aarch64/cortex_klein.S
deleted file mode 100644
index d3a8ab4..0000000
--- a/lib/cpus/aarch64/cortex_klein.S
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2020, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/bl_common.h>
-#include <cortex_klein.h>
-#include <cpu_macros.S>
-#include <plat_macros.S>
-
-/* Hardware handled coherency */
-#if HW_ASSISTED_COHERENCY == 0
-#error "Cortex Klein must be compiled with HW_ASSISTED_COHERENCY enabled"
-#endif
-
-/* 64-bit only core */
-#if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Cortex Klein supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
-#endif
-
- /* ----------------------------------------------------
- * HW will do the cache maintenance while powering down
- * ----------------------------------------------------
- */
-func cortex_klein_core_pwr_dwn
- /* ---------------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------------
- */
- mrs x0, CORTEX_KLEIN_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_KLEIN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_KLEIN_CPUPWRCTLR_EL1, x0
- isb
- ret
-endfunc cortex_klein_core_pwr_dwn
-
- /*
- * Errata printing function for Cortex Klein. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func cortex_klein_errata_report
- ret
-endfunc cortex_klein_errata_report
-#endif
-
-func cortex_klein_reset_func
- /* Disable speculative loads */
- msr SSBS, xzr
- isb
- ret
-endfunc cortex_klein_reset_func
-
- /* ---------------------------------------------
- * This function provides Cortex-Klein specific
- * register information for crash reporting.
- * It needs to return with x6 pointing to
- * a list of register names in ascii and
- * x8 - x15 having values of registers to be
- * reported.
- * ---------------------------------------------
- */
-.section .rodata.cortex_klein_regs, "aS"
-cortex_klein_regs: /* The ascii list of register names to be reported */
- .asciz "cpuectlr_el1", ""
-
-func cortex_klein_cpu_reg_dump
- adr x6, cortex_klein_regs
- mrs x8, CORTEX_KLEIN_CPUECTLR_EL1
- ret
-endfunc cortex_klein_cpu_reg_dump
-
-declare_cpu_ops cortex_klein, CORTEX_KLEIN_MIDR, \
- cortex_klein_reset_func, \
- cortex_klein_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_makalu.S b/lib/cpus/aarch64/cortex_makalu.S
new file mode 100644
index 0000000..98c7d6d
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_makalu.S
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_makalu.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex Makalu must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Cortex Makalu supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+func cortex_makalu_reset_func
+ /* Disable speculative loads */
+ msr SSBS, xzr
+ isb
+ ret
+endfunc cortex_makalu_reset_func
+
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func cortex_makalu_core_pwr_dwn
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ mrs x0, CORTEX_MAKALU_CPUPWRCTLR_EL1
+ orr x0, x0, #CORTEX_MAKALU_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ msr CORTEX_MAKALU_CPUPWRCTLR_EL1, x0
+ isb
+ ret
+endfunc cortex_makalu_core_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Cortex Makalu. Must follow AAPCS.
+ */
+func cortex_makalu_errata_report
+ ret
+endfunc cortex_makalu_errata_report
+#endif
+
+ /* ---------------------------------------------
+ * This function provides Cortex Makalu-specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.cortex_makalu_regs, "aS"
+cortex_makalu_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func cortex_makalu_cpu_reg_dump
+ adr x6, cortex_makalu_regs
+ mrs x8, CORTEX_MAKALU_CPUECTLR_EL1
+ ret
+endfunc cortex_makalu_cpu_reg_dump
+
+declare_cpu_ops cortex_makalu, CORTEX_MAKALU_MIDR, \
+ cortex_makalu_reset_func, \
+ cortex_makalu_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_makalu_elp_arm.S b/lib/cpus/aarch64/cortex_makalu_elp_arm.S
new file mode 100644
index 0000000..fbbf205
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_makalu_elp_arm.S
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_makalu_elp_arm.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex Makalu ELP must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Cortex Makalu ELP supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func cortex_makalu_elp_arm_core_pwr_dwn
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ mrs x0, CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1
+ orr x0, x0, #CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ msr CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1, x0
+ isb
+ ret
+endfunc cortex_makalu_elp_arm_core_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for Cortex Makalu ELP. Must follow AAPCS.
+ */
+func cortex_makalu_elp_arm_errata_report
+ ret
+endfunc cortex_makalu_elp_arm_errata_report
+#endif
+
+func cortex_makalu_elp_arm_reset_func
+ /* Disable speculative loads */
+ msr SSBS, xzr
+ isb
+ ret
+endfunc cortex_makalu_elp_arm_reset_func
+
+ /* ---------------------------------------------
+ * This function provides Cortex Makalu ELP-
+ * specific register information for crash
+ * reporting. It needs to return with x6
+ * pointing to a list of register names in ascii
+ * and x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.cortex_makalu_elp_arm_regs, "aS"
+cortex_makalu_elp_arm_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func cortex_makalu_elp_arm_cpu_reg_dump
+ adr x6, cortex_makalu_elp_arm_regs
+ mrs x8, CORTEX_MAKALU_ELP_ARM_CPUECTLR_EL1
+ ret
+endfunc cortex_makalu_elp_arm_cpu_reg_dump
+
+declare_cpu_ops cortex_makalu_elp_arm, CORTEX_MAKALU_ELP_ARM_MIDR, \
+ cortex_makalu_elp_arm_reset_func, \
+ cortex_makalu_elp_arm_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_matterhorn.S b/lib/cpus/aarch64/cortex_matterhorn.S
deleted file mode 100644
index 4156f3c..0000000
--- a/lib/cpus/aarch64/cortex_matterhorn.S
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2020, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/bl_common.h>
-#include <cortex_matterhorn.h>
-#include <cpu_macros.S>
-#include <plat_macros.S>
-
-/* Hardware handled coherency */
-#if HW_ASSISTED_COHERENCY == 0
-#error "Cortex Matterhorn must be compiled with HW_ASSISTED_COHERENCY enabled"
-#endif
-
-/* 64-bit only core */
-#if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Cortex Matterhorn supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
-#endif
-
- /* ----------------------------------------------------
- * HW will do the cache maintenance while powering down
- * ----------------------------------------------------
- */
-func cortex_matterhorn_core_pwr_dwn
- /* ---------------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------------
- */
- mrs x0, CORTEX_MATTERHORN_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_MATTERHORN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_MATTERHORN_CPUPWRCTLR_EL1, x0
- isb
- ret
-endfunc cortex_matterhorn_core_pwr_dwn
-
- /*
- * Errata printing function for Cortex Matterhorn. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func cortex_matterhorn_errata_report
- ret
-endfunc cortex_matterhorn_errata_report
-#endif
-
-func cortex_matterhorn_reset_func
- /* Disable speculative loads */
- msr SSBS, xzr
- isb
- ret
-endfunc cortex_matterhorn_reset_func
-
- /* ---------------------------------------------
- * This function provides Cortex-Matterhorn specific
- * register information for crash reporting.
- * It needs to return with x6 pointing to
- * a list of register names in ascii and
- * x8 - x15 having values of registers to be
- * reported.
- * ---------------------------------------------
- */
-.section .rodata.cortex_matterhorn_regs, "aS"
-cortex_matterhorn_regs: /* The ascii list of register names to be reported */
- .asciz "cpuectlr_el1", ""
-
-func cortex_matterhorn_cpu_reg_dump
- adr x6, cortex_matterhorn_regs
- mrs x8, CORTEX_MATTERHORN_CPUECTLR_EL1
- ret
-endfunc cortex_matterhorn_cpu_reg_dump
-
-declare_cpu_ops cortex_matterhorn, CORTEX_MATTERHORN_MIDR, \
- cortex_matterhorn_reset_func, \
- cortex_matterhorn_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S
new file mode 100644
index 0000000..87a9bdf
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_x2.S
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_x2.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func cortex_x2_core_pwr_dwn
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ mrs x0, CORTEX_X2_CPUPWRCTLR_EL1
+ orr x0, x0, #CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ msr CORTEX_X2_CPUPWRCTLR_EL1, x0
+ isb
+ ret
+endfunc cortex_x2_core_pwr_dwn
+
+ /*
+ * Errata printing function for Cortex X2. Must follow AAPCS.
+ */
+#if REPORT_ERRATA
+func cortex_x2_errata_report
+ ret
+endfunc cortex_x2_errata_report
+#endif
+
+func cortex_x2_reset_func
+ /* Disable speculative loads */
+ msr SSBS, xzr
+ isb
+ ret
+endfunc cortex_x2_reset_func
+
+ /* ---------------------------------------------
+ * This function provides Cortex X2 specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.cortex_x2_regs, "aS"
+cortex_x2_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func cortex_x2_cpu_reg_dump
+ adr x6, cortex_x2_regs
+ mrs x8, CORTEX_X2_CPUECTLR_EL1
+ ret
+endfunc cortex_x2_cpu_reg_dump
+
+declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \
+ cortex_x2_reset_func, \
+ cortex_x2_core_pwr_dwn
diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S
index 730b09b..bd8f85f 100644
--- a/lib/cpus/aarch64/cpu_helpers.S
+++ b/lib/cpus/aarch64/cpu_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -144,7 +144,7 @@
* If cpu_ops for the MIDR_EL1 cannot be found and
* SUPPORT_UNKNOWN_MPID is enabled, it will try to look for a
* default cpu_ops with an MIDR value of 0.
- * (Implementation number 0x0 should be reseverd for software use
+ * (Implementation number 0x0 should be reserved for software use
* and therefore no clashes should happen with that default value).
*
* Return :
diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S
index 8d646cb..9e7bbf7 100644
--- a/lib/cpus/aarch64/neoverse_n2.S
+++ b/lib/cpus/aarch64/neoverse_n2.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,11 +19,177 @@
#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
- /* -------------------------------------------------
+/* --------------------------------------------------
+ * Errata Workaround for Neoverse N2 Erratum 2002655.
+ * This applies to revision r0p0 of Neoverse N2. it is still open.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_n2_2002655_wa
+ /* Check revision. */
+ mov x17, x30
+ bl check_errata_2002655
+ cbz x0, 1f
+
+ /* Apply instruction patching sequence */
+ ldr x0,=0x6
+ msr S3_6_c15_c8_0,x0
+ ldr x0,=0xF3A08002
+ msr S3_6_c15_c8_2,x0
+ ldr x0,=0xFFF0F7FE
+ msr S3_6_c15_c8_3,x0
+ ldr x0,=0x40000001003ff
+ msr S3_6_c15_c8_1,x0
+ ldr x0,=0x7
+ msr S3_6_c15_c8_0,x0
+ ldr x0,=0xBF200000
+ msr S3_6_c15_c8_2,x0
+ ldr x0,=0xFFEF0000
+ msr S3_6_c15_c8_3,x0
+ ldr x0,=0x40000001003f3
+ msr S3_6_c15_c8_1,x0
+ isb
+1:
+ ret x17
+endfunc errata_n2_2002655_wa
+
+func check_errata_2002655
+ /* Applies to r0p0 */
+ mov x1, #0x00
+ b cpu_rev_var_ls
+endfunc check_errata_2002655
+
+/* ---------------------------------------------------------------
+ * Errata Workaround for Neoverse N2 Erratum 2067956.
+ * This applies to revision r0p0 of Neoverse N2 and is still open.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * ---------------------------------------------------------------
+ */
+func errata_n2_2067956_wa
+ /* Compare x0 against revision r0p0 */
+ mov x17, x30
+ bl check_errata_2067956
+ cbz x0, 1f
+ mrs x1, NEOVERSE_N2_CPUACTLR_EL1
+ orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46
+ msr NEOVERSE_N2_CPUACTLR_EL1, x1
+1:
+ ret x17
+endfunc errata_n2_2067956_wa
+
+func check_errata_2067956
+ /* Applies to r0p0 */
+ mov x1, #0x00
+ b cpu_rev_var_ls
+endfunc check_errata_2067956
+
+/* ---------------------------------------------------------------
+ * Errata Workaround for Neoverse N2 Erratum 2025414.
+ * This applies to revision r0p0 of Neoverse N2 and is still open.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * ---------------------------------------------------------------
+ */
+func errata_n2_2025414_wa
+ /* Compare x0 against revision r0p0 */
+ mov x17, x30
+ bl check_errata_2025414
+ cbz x0, 1f
+ mrs x1, NEOVERSE_N2_CPUECTLR_EL1
+ orr x1, x1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT
+ msr NEOVERSE_N2_CPUECTLR_EL1, x1
+
+1:
+ ret x17
+endfunc errata_n2_2025414_wa
+
+func check_errata_2025414
+ /* Applies to r0p0 */
+ mov x1, #0x00
+ b cpu_rev_var_ls
+endfunc check_errata_2025414
+
+/* ---------------------------------------------------------------
+ * Errata Workaround for Neoverse N2 Erratum 2189731.
+ * This applies to revision r0p0 of Neoverse N2 and is still open.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * ---------------------------------------------------------------
+ */
+func errata_n2_2189731_wa
+ /* Compare x0 against revision r0p0 */
+ mov x17, x30
+ bl check_errata_2189731
+ cbz x0, 1f
+ mrs x1, NEOVERSE_N2_CPUACTLR5_EL1
+ orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44
+ msr NEOVERSE_N2_CPUACTLR5_EL1, x1
+
+1:
+ ret x17
+endfunc errata_n2_2189731_wa
+
+func check_errata_2189731
+ /* Applies to r0p0 */
+ mov x1, #0x00
+ b cpu_rev_var_ls
+endfunc check_errata_2189731
+
+/* --------------------------------------------------
+ * Errata Workaround for Neoverse N2 Erratum 2138956.
+ * This applies to revision r0p0 of Neoverse N2. it is still open.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_n2_2138956_wa
+ /* Check revision. */
+ mov x17, x30
+ bl check_errata_2138956
+ cbz x0, 1f
+
+ /* Apply instruction patching sequence */
+ ldr x0,=0x3
+ msr S3_6_c15_c8_0,x0
+ ldr x0,=0xF3A08002
+ msr S3_6_c15_c8_2,x0
+ ldr x0,=0xFFF0F7FE
+ msr S3_6_c15_c8_3,x0
+ ldr x0,=0x10002001003FF
+ msr S3_6_c15_c8_1,x0
+ ldr x0,=0x4
+ msr S3_6_c15_c8_0,x0
+ ldr x0,=0xBF200000
+ msr S3_6_c15_c8_2,x0
+ ldr x0,=0xFFEF0000
+ msr S3_6_c15_c8_3,x0
+ ldr x0,=0x10002001003F3
+ msr S3_6_c15_c8_1,x0
+ isb
+1:
+ ret x17
+endfunc errata_n2_2138956_wa
+
+func check_errata_2138956
+ /* Applies to r0p0 */
+ mov x1, #0x00
+ b cpu_rev_var_ls
+endfunc check_errata_2138956
+
+ /* -------------------------------------------
* The CPU Ops reset function for Neoverse N2.
- * -------------------------------------------------
+ * -------------------------------------------
*/
func neoverse_n2_reset_func
+ mov x19, x30
+
/* Check if the PE implements SSBS */
mrs x0, id_aa64pfr1_el1
tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
@@ -37,6 +203,27 @@
orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2
msr NEOVERSE_N2_CPUACTLR2_EL1, x0
+#if ERRATA_N2_2067956
+ mov x0, x18
+ bl errata_n2_2067956_wa
+#endif
+
+#if ERRATA_N2_2025414
+ mov x0, x18
+ bl errata_n2_2025414_wa
+#endif
+
+#if ERRATA_N2_2189731
+ mov x0, x18
+ bl errata_n2_2189731_wa
+#endif
+
+
+#if ERRATA_N2_2138956
+ mov x0, x18
+ bl errata_n2_2138956_wa
+#endif
+
#if ENABLE_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
mrs x0, cptr_el3
@@ -53,20 +240,28 @@
#if NEOVERSE_Nx_EXTERNAL_LLC
/* Some systems may have External LLC, core needs to be made aware */
- mrs x0, NEOVERSE_N2_CPUECTLR_EL1
- orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT
- msr NEOVERSE_N2_CPUECTLR_EL1, x0
+ mrs x0, NEOVERSE_N2_CPUECTLR_EL1
+ orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT
+ msr NEOVERSE_N2_CPUECTLR_EL1, x0
+#endif
+
+ bl cpu_get_rev_var
+ mov x18, x0
+
+#if ERRATA_N2_2002655
+ mov x0, x18
+ bl errata_n2_2002655_wa
#endif
isb
- ret
+ ret x19
endfunc neoverse_n2_reset_func
func neoverse_n2_core_pwr_dwn
- /* ---------------------------------------------
+ /* ---------------------------------------------------
* Enable CPU power down bit in power control register
* No need to do cache maintenance here.
- * ---------------------------------------------
+ * ---------------------------------------------------
*/
mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1
orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT
@@ -80,7 +275,22 @@
* Errata printing function for Neoverse N2 cores. Must follow AAPCS.
*/
func neoverse_n2_errata_report
- /* No errata reported for Neoverse N2 cores */
+ stp x8, x30, [sp, #-16]!
+
+ bl cpu_get_rev_var
+ mov x8, x0
+
+ /*
+ * Report all errata. The revision-variant information is passed to
+ * checking functions of each errata.
+ */
+ report_errata ERRATA_N2_2002655, neoverse_n2, 2002655
+ report_errata ERRATA_N2_2067956, neoverse_n2, 2067956
+ report_errata ERRATA_N2_2025414, neoverse_n2, 2025414
+ report_errata ERRATA_N2_2189731, neoverse_n2, 2189731
+ report_errata ERRATA_N2_2138956, neoverse_n2, 2138956
+
+ ldp x8, x30, [sp], #16
ret
endfunc neoverse_n2_errata_report
#endif
diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S
index 7336294..0bcf52a 100644
--- a/lib/cpus/aarch64/neoverse_v1.S
+++ b/lib/cpus/aarch64/neoverse_v1.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,6 +21,244 @@
#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
+ /* --------------------------------------------------
+ * Errata Workaround for Neoverse V1 Errata #1774420.
+ * This applies to revisions r0p0 and r1p0, fixed in r1p1.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_neoverse_v1_1774420_wa
+ /* Check workaround compatibility. */
+ mov x17, x30
+ bl check_errata_1774420
+ cbz x0, 1f
+
+ /* Set bit 53 in CPUECTLR_EL1 */
+ mrs x1, NEOVERSE_V1_CPUECTLR_EL1
+ orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_53
+ msr NEOVERSE_V1_CPUECTLR_EL1, x1
+ isb
+1:
+ ret x17
+endfunc errata_neoverse_v1_1774420_wa
+
+func check_errata_1774420
+ /* Applies to r0p0 and r1p0. */
+ mov x1, #0x10
+ b cpu_rev_var_ls
+endfunc check_errata_1774420
+
+ /* --------------------------------------------------
+ * Errata Workaround for Neoverse V1 Errata #1791573.
+ * This applies to revisions r0p0 and r1p0, fixed in r1p1.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_neoverse_v1_1791573_wa
+ /* Check workaround compatibility. */
+ mov x17, x30
+ bl check_errata_1791573
+ cbz x0, 1f
+
+ /* Set bit 2 in ACTLR2_EL1 */
+ mrs x1, NEOVERSE_V1_ACTLR2_EL1
+ orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_2
+ msr NEOVERSE_V1_ACTLR2_EL1, x1
+ isb
+1:
+ ret x17
+endfunc errata_neoverse_v1_1791573_wa
+
+func check_errata_1791573
+ /* Applies to r0p0 and r1p0. */
+ mov x1, #0x10
+ b cpu_rev_var_ls
+endfunc check_errata_1791573
+
+ /* --------------------------------------------------
+ * Errata Workaround for Neoverse V1 Errata #1852267.
+ * This applies to revisions r0p0 and r1p0, fixed in r1p1.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_neoverse_v1_1852267_wa
+ /* Check workaround compatibility. */
+ mov x17, x30
+ bl check_errata_1852267
+ cbz x0, 1f
+
+ /* Set bit 28 in ACTLR2_EL1 */
+ mrs x1, NEOVERSE_V1_ACTLR2_EL1
+ orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_28
+ msr NEOVERSE_V1_ACTLR2_EL1, x1
+ isb
+1:
+ ret x17
+endfunc errata_neoverse_v1_1852267_wa
+
+func check_errata_1852267
+ /* Applies to r0p0 and r1p0. */
+ mov x1, #0x10
+ b cpu_rev_var_ls
+endfunc check_errata_1852267
+
+ /* --------------------------------------------------
+ * Errata Workaround for Neoverse V1 Errata #1925756.
+ * This applies to revisions <= r1p1.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_neoverse_v1_1925756_wa
+ /* Check workaround compatibility. */
+ mov x17, x30
+ bl check_errata_1925756
+ cbz x0, 1f
+
+ /* Set bit 8 in CPUECTLR_EL1 */
+ mrs x1, NEOVERSE_V1_CPUECTLR_EL1
+ orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_8
+ msr NEOVERSE_V1_CPUECTLR_EL1, x1
+ isb
+1:
+ ret x17
+endfunc errata_neoverse_v1_1925756_wa
+
+func check_errata_1925756
+ /* Applies to <= r1p1. */
+ mov x1, #0x11
+ b cpu_rev_var_ls
+endfunc check_errata_1925756
+
+ /* --------------------------------------------------
+ * Errata Workaround for Neoverse V1 Erratum #1940577
+ * This applies to revisions r1p0 - r1p1 and is open.
+ * It also exists in r0p0 but there is no fix in that
+ * revision.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_neoverse_v1_1940577_wa
+ /* Compare x0 against revisions r1p0 - r1p1 */
+ mov x17, x30
+ bl check_errata_1940577
+ cbz x0, 1f
+
+ mov x0, #0
+ msr S3_6_C15_C8_0, x0
+ ldr x0, =0x10E3900002
+ msr S3_6_C15_C8_2, x0
+ ldr x0, =0x10FFF00083
+ msr S3_6_C15_C8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_C15_C8_1, x0
+
+ mov x0, #1
+ msr S3_6_C15_C8_0, x0
+ ldr x0, =0x10E3800082
+ msr S3_6_C15_C8_2, x0
+ ldr x0, =0x10FFF00083
+ msr S3_6_C15_C8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_C15_C8_1, x0
+
+ mov x0, #2
+ msr S3_6_C15_C8_0, x0
+ ldr x0, =0x10E3800200
+ msr S3_6_C15_C8_2, x0
+ ldr x0, =0x10FFF003E0
+ msr S3_6_C15_C8_3, x0
+ ldr x0, =0x2001003FF
+ msr S3_6_C15_C8_1, x0
+
+ isb
+1:
+ ret x17
+endfunc errata_neoverse_v1_1940577_wa
+
+func check_errata_1940577
+ /* Applies to revisions r1p0 - r1p1. */
+ mov x1, #0x10
+ mov x2, #0x11
+ b cpu_rev_var_range
+endfunc check_errata_1940577
+
+ /* --------------------------------------------------
+ * Errata Workaround for Neoverse V1 Errata #1966096
+ * This applies to revisions r1p0 - r1p1 and is open.
+ * It also exists in r0p0 but there is no workaround
+ * for that revision.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_neoverse_v1_1966096_wa
+ /* Check workaround compatibility. */
+ mov x17, x30
+ bl check_errata_1966096
+ cbz x0, 1f
+
+ /* Apply the workaround. */
+ mov x0, #0x3
+ msr S3_6_C15_C8_0, x0
+ ldr x0, =0xEE010F12
+ msr S3_6_C15_C8_2, x0
+ ldr x0, =0xFFFF0FFF
+ msr S3_6_C15_C8_3, x0
+ ldr x0, =0x80000000003FF
+ msr S3_6_C15_C8_1, x0
+ isb
+
+1:
+ ret x17
+endfunc errata_neoverse_v1_1966096_wa
+
+func check_errata_1966096
+ mov x1, #0x10
+ mov x2, #0x11
+ b cpu_rev_var_range
+endfunc check_errata_1966096
+
+ /* --------------------------------------------------
+ * Errata Workaround for Neoverse V1 Errata #2139242.
+ * This applies to revisions r0p0, r1p0, and r1p1, it
+ * is still open.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------
+ */
+func errata_neoverse_v1_2139242_wa
+ /* Check workaround compatibility. */
+ mov x17, x30
+ bl check_errata_2139242
+ cbz x0, 1f
+
+ /* Apply the workaround. */
+ mov x0, #0x3
+ msr S3_6_C15_C8_0, x0
+ ldr x0, =0xEE720F14
+ msr S3_6_C15_C8_2, x0
+ ldr x0, =0xFFFF0FDF
+ msr S3_6_C15_C8_3, x0
+ ldr x0, =0x40000005003FF
+ msr S3_6_C15_C8_1, x0
+ isb
+
+1:
+ ret x17
+endfunc errata_neoverse_v1_2139242_wa
+
+func check_errata_2139242
+ /* Applies to r0p0, r1p0, r1p1 */
+ mov x1, #0x11
+ b cpu_rev_var_ls
+endfunc check_errata_2139242
+
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
@@ -42,6 +280,24 @@
*/
#if REPORT_ERRATA
func neoverse_v1_errata_report
+ stp x8, x30, [sp, #-16]!
+
+ bl cpu_get_rev_var
+ mov x8, x0
+
+ /*
+ * Report all errata. The revision-variant information is passed to
+ * checking functions of each errata.
+ */
+ report_errata ERRATA_V1_1774420, neoverse_v1, 1774420
+ report_errata ERRATA_V1_1791573, neoverse_v1, 1791573
+ report_errata ERRATA_V1_1852267, neoverse_v1, 1852267
+ report_errata ERRATA_V1_1925756, neoverse_v1, 1925756
+ report_errata ERRATA_V1_1940577, neoverse_v1, 1940577
+ report_errata ERRATA_V1_1966096, neoverse_v1, 1966096
+ report_errata ERRATA_V1_2139242, neoverse_v1, 2139242
+
+ ldp x8, x30, [sp], #16
ret
endfunc neoverse_v1_errata_report
#endif
@@ -51,8 +307,43 @@
/* Disable speculative loads */
msr SSBS, xzr
-
isb
+
+#if ERRATA_V1_1774420
+ mov x0, x18
+ bl errata_neoverse_v1_1774420_wa
+#endif
+
+#if ERRATA_V1_1791573
+ mov x0, x18
+ bl errata_neoverse_v1_1791573_wa
+#endif
+
+#if ERRATA_V1_1852267
+ mov x0, x18
+ bl errata_neoverse_v1_1852267_wa
+#endif
+
+#if ERRATA_V1_1925756
+ mov x0, x18
+ bl errata_neoverse_v1_1925756_wa
+#endif
+
+#if ERRATA_V1_1940577
+ mov x0, x18
+ bl errata_neoverse_v1_1940577_wa
+#endif
+
+#if ERRATA_V1_1966096
+ mov x0, x18
+ bl errata_neoverse_v1_1966096_wa
+#endif
+
+#if ERRATA_V1_2139242
+ mov x0, x18
+ bl errata_neoverse_v1_2139242_wa
+#endif
+
ret x19
endfunc neoverse_v1_reset_func
diff --git a/lib/cpus/aarch64/qemu_max.S b/lib/cpus/aarch64/qemu_max.S
new file mode 100644
index 0000000..8948fda
--- /dev/null
+++ b/lib/cpus/aarch64/qemu_max.S
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch.h>
+#include <asm_macros.S>
+#include <cpu_macros.S>
+#include <qemu_max.h>
+
+func qemu_max_core_pwr_dwn
+ /* ---------------------------------------------
+ * Disable the Data Cache.
+ * ---------------------------------------------
+ */
+ mrs x1, sctlr_el3
+ bic x1, x1, #SCTLR_C_BIT
+ msr sctlr_el3, x1
+ isb
+
+ /* ---------------------------------------------
+ * Flush L1 cache to L2.
+ * ---------------------------------------------
+ */
+ mov x18, lr
+ mov x0, #DCCISW
+ bl dcsw_op_level1
+ mov lr, x18
+ ret
+endfunc qemu_max_core_pwr_dwn
+
+func qemu_max_cluster_pwr_dwn
+ /* ---------------------------------------------
+ * Disable the Data Cache.
+ * ---------------------------------------------
+ */
+ mrs x1, sctlr_el3
+ bic x1, x1, #SCTLR_C_BIT
+ msr sctlr_el3, x1
+ isb
+
+ /* ---------------------------------------------
+ * Flush all caches to PoC.
+ * ---------------------------------------------
+ */
+ mov x0, #DCCISW
+ b dcsw_op_all
+endfunc qemu_max_cluster_pwr_dwn
+
+#if REPORT_ERRATA
+/*
+ * Errata printing function for QEMU "max". Must follow AAPCS.
+ */
+func qemu_max_errata_report
+ ret
+endfunc qemu_max_errata_report
+#endif
+
+ /* ---------------------------------------------
+ * This function provides cpu specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.qemu_max_regs, "aS"
+qemu_max_regs: /* The ascii list of register names to be reported */
+ .asciz "" /* no registers to report */
+
+func qemu_max_cpu_reg_dump
+ adr x6, qemu_max_regs
+ ret
+endfunc qemu_max_cpu_reg_dump
+
+
+/* cpu_ops for QEMU MAX */
+declare_cpu_ops qemu_max, QEMU_MAX_MIDR, CPU_NO_RESET_FUNC, \
+ qemu_max_core_pwr_dwn, \
+ qemu_max_cluster_pwr_dwn
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 64a4b4d..6103a5a 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -1,6 +1,6 @@
#
# Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
-# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
+# Copyright (c) 2020-2021, NVIDIA Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -290,6 +290,14 @@
# only to revision <= r1p1 of the Cortex A77 cpu.
ERRATA_A77_1925769 ?=0
+# Flag to apply erratum 1946167 workaround during reset. This erratum applies
+# only to revision <= r1p1 of the Cortex A77 cpu.
+ERRATA_A77_1946167 ?=0
+
+# Flag to apply erratum 1791578 workaround during reset. This erratum applies
+# to revisions r0p0, r1p0, and r1p1, it is still open.
+ERRATA_A77_1791578 ?=0
+
# Flag to apply erratum 1688305 workaround during reset. This erratum applies
# to revisions r0p0 - r1p0 of the A78 cpu.
ERRATA_A78_1688305 ?=0
@@ -303,6 +311,22 @@
# well but there is no workaround for that revision.
ERRATA_A78_1951500 ?=0
+# Flag to apply erratum 1941500 workaround during reset. This erratum applies
+# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
+ERRATA_A78_AE_1941500 ?=0
+
+# Flag to apply erratum 1951502 workaround during reset. This erratum applies
+# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
+ERRATA_A78_AE_1951502 ?=0
+
+# Flag to apply erratum 1821534 workaround during reset. This erratum applies
+# to revisions r0p0 and r1p0 of the A78 cpu.
+ERRATA_A78_1821534 ?=0
+
+# Flag to apply erratum 1952683 workaround during reset. This erratum applies
+# to revision r0p0 of the A78 cpu and was fixed in the revision r1p0.
+ERRATA_A78_1952683 ?=0
+
# Flag to apply T32 CLREX workaround during reset. This erratum applies
# only to r0p0 and r1p0 of the Neoverse N1 cpu.
ERRATA_N1_1043202 ?=0
@@ -360,6 +384,71 @@
# exists in revisions r0p0, r1p0, and r2p0 as well but there is no workaround.
ERRATA_N1_1946160 ?=0
+# Flag to apply erratum 2002655 workaround during reset. This erratum applies
+# to revisions r0p0 of the Neoverse-N2 cpu, it is still open.
+ERRATA_N2_2002655 ?=0
+
+# Flag to apply erratum 1774420 workaround during reset. This erratum applies
+# to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1.
+ERRATA_V1_1774420 ?=0
+
+# Flag to apply erratum 1791573 workaround during reset. This erratum applies
+# to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1.
+ERRATA_V1_1791573 ?=0
+
+# Flag to apply erratum 1852267 workaround during reset. This erratum applies
+# to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1.
+ERRATA_V1_1852267 ?=0
+
+# Flag to apply erratum 1925756 workaround during reset. This needs to be
+# enabled for r0p0, r1p0, and r1p1 of the Neoverse V1 core, it is still open.
+ERRATA_V1_1925756 ?=0
+
+# Flag to apply erratum 1940577 workaround during reset. This erratum applies
+# to revisions r1p0 and r1p1 of the Neoverse V1 cpu.
+ERRATA_V1_1940577 ?=0
+
+# Flag to apply erratum 1966096 workaround during reset. This erratum applies
+# to revisions r1p0 and r1p1 of the Neoverse V1 CPU and is open. This issue
+# exists in r0p0 as well but there is no workaround for that revision.
+ERRATA_V1_1966096 ?=0
+
+# Flag to apply erratum 2139242 workaround during reset. This erratum applies
+# to revisions r0p0, r1p0, and r1p1 of the Neoverse V1 cpu and is still open.
+ERRATA_V1_2139242 ?=0
+
+# Flag to apply erratum 1987031 workaround during reset. This erratum applies
+# to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
+ERRATA_A710_1987031 ?=0
+
+# Flag to apply erratum 2081180 workaround during reset. This erratum applies
+# to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
+ERRATA_A710_2081180 ?=0
+
+# Flag to apply erratum 2067956 workaround during reset. This erratum applies
+# to revision r0p0 of the Neoverse N2 cpu and is still open.
+ERRATA_N2_2067956 ?=0
+
+# Flag to apply erratum 2025414 workaround during reset. This erratum applies
+# to revision r0p0 of the Neoverse N2 cpu and is still open.
+ERRATA_N2_2025414 ?=0
+
+# Flag to apply erratum 2189731 workaround during reset. This erratum applies
+# to revision r0p0 of the Neoverse N2 cpu and is still open.
+ERRATA_N2_2189731 ?=0
+
+# Flag to apply erratum 2138956 workaround during reset. This erratum applies
+# to revision r0p0 of the Neoverse N2 cpu and is still open.
+ERRATA_N2_2138956 ?=0
+
+# Flag to apply erratum 2055002 workaround during reset. This erratum applies
+# to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open.
+ERRATA_A710_2055002 ?=0
+
+# Flag to apply erratum 2017096 workaround during reset. This erratum applies
+# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
+ERRATA_A710_2017096 ?=0
+
# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
# Applying the workaround results in higher DSU power consumption on idle.
ERRATA_DSU_798953 ?=0
@@ -585,6 +674,14 @@
$(eval $(call assert_boolean,ERRATA_A77_1925769))
$(eval $(call add_define,ERRATA_A77_1925769))
+# Process ERRATA_A77_1946167 flag
+$(eval $(call assert_boolean,ERRATA_A77_1946167))
+$(eval $(call add_define,ERRATA_A77_1946167))
+
+# Process ERRATA_A77_1791578 flag
+$(eval $(call assert_boolean,ERRATA_A77_1791578))
+$(eval $(call add_define,ERRATA_A77_1791578))
+
# Process ERRATA_A78_1688305 flag
$(eval $(call assert_boolean,ERRATA_A78_1688305))
$(eval $(call add_define,ERRATA_A78_1688305))
@@ -597,6 +694,22 @@
$(eval $(call assert_boolean,ERRATA_A78_1951500))
$(eval $(call add_define,ERRATA_A78_1951500))
+# Process ERRATA_A78_AE_1941500 flag
+$(eval $(call assert_boolean,ERRATA_A78_AE_1941500))
+$(eval $(call add_define,ERRATA_A78_AE_1941500))
+
+# Process ERRATA_A78_AE_1951502 flag
+$(eval $(call assert_boolean,ERRATA_A78_AE_1951502))
+$(eval $(call add_define,ERRATA_A78_AE_1951502))
+
+# Process ERRATA_A78_1821534 flag
+$(eval $(call assert_boolean,ERRATA_A78_1821534))
+$(eval $(call add_define,ERRATA_A78_1821534))
+
+# Process ERRATA_A78_1952683 flag
+$(eval $(call assert_boolean,ERRATA_A78_1952683))
+$(eval $(call add_define,ERRATA_A78_1952683))
+
# Process ERRATA_N1_1043202 flag
$(eval $(call assert_boolean,ERRATA_N1_1043202))
$(eval $(call add_define,ERRATA_N1_1043202))
@@ -653,6 +766,70 @@
$(eval $(call assert_boolean,ERRATA_N1_1946160))
$(eval $(call add_define,ERRATA_N1_1946160))
+# Process ERRATA_N2_2002655 flag
+$(eval $(call assert_boolean,ERRATA_N2_2002655))
+$(eval $(call add_define,ERRATA_N2_2002655))
+
+# Process ERRATA_V1_1774420 flag
+$(eval $(call assert_boolean,ERRATA_V1_1774420))
+$(eval $(call add_define,ERRATA_V1_1774420))
+
+# Process ERRATA_V1_1791573 flag
+$(eval $(call assert_boolean,ERRATA_V1_1791573))
+$(eval $(call add_define,ERRATA_V1_1791573))
+
+# Process ERRATA_V1_1852267 flag
+$(eval $(call assert_boolean,ERRATA_V1_1852267))
+$(eval $(call add_define,ERRATA_V1_1852267))
+
+# Process ERRATA_V1_1925756 flag
+$(eval $(call assert_boolean,ERRATA_V1_1925756))
+$(eval $(call add_define,ERRATA_V1_1925756))
+
+# Process ERRATA_V1_1940577 flag
+$(eval $(call assert_boolean,ERRATA_V1_1940577))
+$(eval $(call add_define,ERRATA_V1_1940577))
+
+# Process ERRATA_V1_1966096 flag
+$(eval $(call assert_boolean,ERRATA_V1_1966096))
+$(eval $(call add_define,ERRATA_V1_1966096))
+
+# Process ERRATA_V1_2139242 flag
+$(eval $(call assert_boolean,ERRATA_V1_2139242))
+$(eval $(call add_define,ERRATA_V1_2139242))
+
+# Process ERRATA_A710_1987031 flag
+$(eval $(call assert_boolean,ERRATA_A710_1987031))
+$(eval $(call add_define,ERRATA_A710_1987031))
+
+# Process ERRATA_A710_2081180 flag
+$(eval $(call assert_boolean,ERRATA_A710_2081180))
+$(eval $(call add_define,ERRATA_A710_2081180))
+
+# Process ERRATA_N2_2067956 flag
+$(eval $(call assert_boolean,ERRATA_N2_2067956))
+$(eval $(call add_define,ERRATA_N2_2067956))
+
+# Process ERRATA_N2_2025414 flag
+$(eval $(call assert_boolean,ERRATA_N2_2025414))
+$(eval $(call add_define,ERRATA_N2_2025414))
+
+# Process ERRATA_N2_2189731 flag
+$(eval $(call assert_boolean,ERRATA_N2_2189731))
+$(eval $(call add_define,ERRATA_N2_2189731))
+
+# Process ERRATA_N2_2138956 flag
+$(eval $(call assert_boolean,ERRATA_N2_2138956))
+$(eval $(call add_define,ERRATA_N2_2138956))
+
+# Process ERRATA_A710_2055002 flag
+$(eval $(call assert_boolean,ERRATA_A710_2055002))
+$(eval $(call add_define,ERRATA_A710_2055002))
+
+# Process ERRATA_A710_2017096 flag
+$(eval $(call assert_boolean,ERRATA_A710_2017096))
+$(eval $(call add_define,ERRATA_A710_2017096))
+
# Process ERRATA_DSU_798953 flag
$(eval $(call assert_boolean,ERRATA_DSU_798953))
$(eval $(call add_define,ERRATA_DSU_798953))
diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c
index 2443001..81d793b 100644
--- a/lib/el3_runtime/aarch32/context_mgmt.c
+++ b/lib/el3_runtime/aarch32/context_mgmt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -49,7 +49,7 @@
*
* To prepare the register state for entry call cm_prepare_el3_exit() and
* el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to
- * cm_e1_sysreg_context_restore().
+ * cm_el1_sysregs_context_restore().
******************************************************************************/
void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
{
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 75e214d..40e7ddf 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -30,7 +30,7 @@
/* -----------------------------------------------------
* The following function strictly follows the AArch64
- * PCS to use x9-x17 (temporary caller-saved registers)
+ * PCS to use x9-x16 (temporary caller-saved registers)
* to save EL2 system register context. It assumes that
* 'x0' is pointing to a 'el2_sys_regs' structure where
* the register context will be saved.
@@ -43,7 +43,6 @@
* ICH_LR<n>_EL2
* -----------------------------------------------------
*/
-
func el2_sysregs_context_save
mrs x9, actlr_el2
mrs x10, afsr0_el2
@@ -54,185 +53,153 @@
stp x11, x12, [x0, #CTX_AFSR1_EL2]
mrs x13, cnthctl_el2
- mrs x14, cnthp_ctl_el2
+ mrs x14, cntvoff_el2
stp x13, x14, [x0, #CTX_CNTHCTL_EL2]
- mrs x15, cnthp_cval_el2
- mrs x16, cnthp_tval_el2
- stp x15, x16, [x0, #CTX_CNTHP_CVAL_EL2]
+ mrs x15, cptr_el2
+ str x15, [x0, #CTX_CPTR_EL2]
- mrs x17, cntvoff_el2
- mrs x9, cptr_el2
- stp x17, x9, [x0, #CTX_CNTVOFF_EL2]
-
- mrs x11, elr_el2
#if CTX_INCLUDE_AARCH32_REGS
- mrs x10, dbgvcr32_el2
- stp x10, x11, [x0, #CTX_DBGVCR32_EL2]
-#else
- str x11, [x0, #CTX_ELR_EL2]
+ mrs x16, dbgvcr32_el2
+ str x16, [x0, #CTX_DBGVCR32_EL2]
#endif
- mrs x14, esr_el2
- mrs x15, far_el2
- stp x14, x15, [x0, #CTX_ESR_EL2]
+ mrs x9, elr_el2
+ mrs x10, esr_el2
+ stp x9, x10, [x0, #CTX_ELR_EL2]
- mrs x16, hacr_el2
- mrs x17, hcr_el2
- stp x16, x17, [x0, #CTX_HACR_EL2]
+ mrs x11, far_el2
+ mrs x12, hacr_el2
+ stp x11, x12, [x0, #CTX_FAR_EL2]
- mrs x9, hpfar_el2
- mrs x10, hstr_el2
- stp x9, x10, [x0, #CTX_HPFAR_EL2]
+ mrs x13, hcr_el2
+ mrs x14, hpfar_el2
+ stp x13, x14, [x0, #CTX_HCR_EL2]
- mrs x11, ICC_SRE_EL2
- mrs x12, ICH_HCR_EL2
- stp x11, x12, [x0, #CTX_ICC_SRE_EL2]
+ mrs x15, hstr_el2
+ mrs x16, ICC_SRE_EL2
+ stp x15, x16, [x0, #CTX_HSTR_EL2]
- mrs x13, ICH_VMCR_EL2
- mrs x14, mair_el2
- stp x13, x14, [x0, #CTX_ICH_VMCR_EL2]
+ mrs x9, ICH_HCR_EL2
+ mrs x10, ICH_VMCR_EL2
+ stp x9, x10, [x0, #CTX_ICH_HCR_EL2]
- mrs x15, mdcr_el2
+ mrs x11, mair_el2
+ mrs x12, mdcr_el2
+ stp x11, x12, [x0, #CTX_MAIR_EL2]
+
#if ENABLE_SPE_FOR_LOWER_ELS
- mrs x16, PMSCR_EL2
- stp x15, x16, [x0, #CTX_MDCR_EL2]
-#else
- str x15, [x0, #CTX_MDCR_EL2]
+ mrs x13, PMSCR_EL2
+ str x13, [x0, #CTX_PMSCR_EL2]
#endif
+ mrs x14, sctlr_el2
+ str x14, [x0, #CTX_SCTLR_EL2]
- mrs x17, sctlr_el2
- mrs x9, spsr_el2
- stp x17, x9, [x0, #CTX_SCTLR_EL2]
+ mrs x15, spsr_el2
+ mrs x16, sp_el2
+ stp x15, x16, [x0, #CTX_SPSR_EL2]
- mrs x10, sp_el2
- mrs x11, tcr_el2
- stp x10, x11, [x0, #CTX_SP_EL2]
+ mrs x9, tcr_el2
+ mrs x10, tpidr_el2
+ stp x9, x10, [x0, #CTX_TCR_EL2]
- mrs x12, tpidr_el2
- mrs x13, ttbr0_el2
- stp x12, x13, [x0, #CTX_TPIDR_EL2]
+ mrs x11, ttbr0_el2
+ mrs x12, vbar_el2
+ stp x11, x12, [x0, #CTX_TTBR0_EL2]
- mrs x14, vbar_el2
- mrs x15, vmpidr_el2
- stp x14, x15, [x0, #CTX_VBAR_EL2]
+ mrs x13, vmpidr_el2
+ mrs x14, vpidr_el2
+ stp x13, x14, [x0, #CTX_VMPIDR_EL2]
- mrs x16, vpidr_el2
- mrs x17, vtcr_el2
- stp x16, x17, [x0, #CTX_VPIDR_EL2]
-
- mrs x9, vttbr_el2
- str x9, [x0, #CTX_VTTBR_EL2]
+ mrs x15, vtcr_el2
+ mrs x16, vttbr_el2
+ stp x15, x16, [x0, #CTX_VTCR_EL2]
#if CTX_INCLUDE_MTE_REGS
- mrs x10, TFSR_EL2
- str x10, [x0, #CTX_TFSR_EL2]
+ mrs x9, TFSR_EL2
+ str x9, [x0, #CTX_TFSR_EL2]
#endif
#if ENABLE_MPAM_FOR_LOWER_ELS
- mrs x9, MPAM2_EL2
- mrs x10, MPAMHCR_EL2
- stp x9, x10, [x0, #CTX_MPAM2_EL2]
+ mrs x10, MPAM2_EL2
+ str x10, [x0, #CTX_MPAM2_EL2]
- mrs x11, MPAMVPM0_EL2
- mrs x12, MPAMVPM1_EL2
- stp x11, x12, [x0, #CTX_MPAMVPM0_EL2]
+ mrs x11, MPAMHCR_EL2
+ mrs x12, MPAMVPM0_EL2
+ stp x11, x12, [x0, #CTX_MPAMHCR_EL2]
- mrs x13, MPAMVPM2_EL2
- mrs x14, MPAMVPM3_EL2
- stp x13, x14, [x0, #CTX_MPAMVPM2_EL2]
+ mrs x13, MPAMVPM1_EL2
+ mrs x14, MPAMVPM2_EL2
+ stp x13, x14, [x0, #CTX_MPAMVPM1_EL2]
- mrs x15, MPAMVPM4_EL2
- mrs x16, MPAMVPM5_EL2
- stp x15, x16, [x0, #CTX_MPAMVPM4_EL2]
+ mrs x15, MPAMVPM3_EL2
+ mrs x16, MPAMVPM4_EL2
+ stp x15, x16, [x0, #CTX_MPAMVPM3_EL2]
- mrs x17, MPAMVPM6_EL2
- mrs x9, MPAMVPM7_EL2
- stp x17, x9, [x0, #CTX_MPAMVPM6_EL2]
+ mrs x9, MPAMVPM5_EL2
+ mrs x10, MPAMVPM6_EL2
+ stp x9, x10, [x0, #CTX_MPAMVPM5_EL2]
- mrs x10, MPAMVPMV_EL2
- str x10, [x0, #CTX_MPAMVPMV_EL2]
+ mrs x11, MPAMVPM7_EL2
+ mrs x12, MPAMVPMV_EL2
+ stp x11, x12, [x0, #CTX_MPAMVPM7_EL2]
#endif
-
#if ARM_ARCH_AT_LEAST(8, 6)
- mrs x11, HAFGRTR_EL2
- mrs x12, HDFGRTR_EL2
- stp x11, x12, [x0, #CTX_HAFGRTR_EL2]
+ mrs x13, HAFGRTR_EL2
+ mrs x14, HDFGRTR_EL2
+ stp x13, x14, [x0, #CTX_HAFGRTR_EL2]
- mrs x13, HDFGWTR_EL2
- mrs x14, HFGITR_EL2
- stp x13, x14, [x0, #CTX_HDFGWTR_EL2]
+ mrs x15, HDFGWTR_EL2
+ mrs x16, HFGITR_EL2
+ stp x15, x16, [x0, #CTX_HDFGWTR_EL2]
- mrs x15, HFGRTR_EL2
- mrs x16, HFGWTR_EL2
- stp x15, x16, [x0, #CTX_HFGRTR_EL2]
+ mrs x9, HFGRTR_EL2
+ mrs x10, HFGWTR_EL2
+ stp x9, x10, [x0, #CTX_HFGRTR_EL2]
- mrs x17, CNTPOFF_EL2
- str x17, [x0, #CTX_CNTPOFF_EL2]
+ mrs x11, CNTPOFF_EL2
+ str x11, [x0, #CTX_CNTPOFF_EL2]
#endif
#if ARM_ARCH_AT_LEAST(8, 4)
- mrs x9, cnthps_ctl_el2
- mrs x10, cnthps_cval_el2
- stp x9, x10, [x0, #CTX_CNTHPS_CTL_EL2]
-
- mrs x11, cnthps_tval_el2
- mrs x12, cnthvs_ctl_el2
- stp x11, x12, [x0, #CTX_CNTHPS_TVAL_EL2]
-
- mrs x13, cnthvs_cval_el2
- mrs x14, cnthvs_tval_el2
- stp x13, x14, [x0, #CTX_CNTHVS_CVAL_EL2]
-
- mrs x15, cnthv_ctl_el2
- mrs x16, cnthv_cval_el2
- stp x15, x16, [x0, #CTX_CNTHV_CTL_EL2]
-
- mrs x17, cnthv_tval_el2
- mrs x9, contextidr_el2
- stp x17, x9, [x0, #CTX_CNTHV_TVAL_EL2]
+ mrs x12, contextidr_el2
+ str x12, [x0, #CTX_CONTEXTIDR_EL2]
#if CTX_INCLUDE_AARCH32_REGS
- mrs x10, sder32_el2
- str x10, [x0, #CTX_SDER32_EL2]
+ mrs x13, sder32_el2
+ str x13, [x0, #CTX_SDER32_EL2]
#endif
-
- mrs x11, ttbr1_el2
- str x11, [x0, #CTX_TTBR1_EL2]
-
- mrs x12, vdisr_el2
- str x12, [x0, #CTX_VDISR_EL2]
+ mrs x14, ttbr1_el2
+ mrs x15, vdisr_el2
+ stp x14, x15, [x0, #CTX_TTBR1_EL2]
#if CTX_INCLUDE_NEVE_REGS
- mrs x13, vncr_el2
- str x13, [x0, #CTX_VNCR_EL2]
+ mrs x16, vncr_el2
+ str x16, [x0, #CTX_VNCR_EL2]
#endif
- mrs x14, vsesr_el2
- str x14, [x0, #CTX_VSESR_EL2]
+ mrs x9, vsesr_el2
+ mrs x10, vstcr_el2
+ stp x9, x10, [x0, #CTX_VSESR_EL2]
- mrs x15, vstcr_el2
- str x15, [x0, #CTX_VSTCR_EL2]
-
- mrs x16, vsttbr_el2
- str x16, [x0, #CTX_VSTTBR_EL2]
-
- mrs x17, TRFCR_EL2
- str x17, [x0, #CTX_TRFCR_EL2]
+ mrs x11, vsttbr_el2
+ mrs x12, TRFCR_EL2
+ stp x11, x12, [x0, #CTX_VSTTBR_EL2]
#endif
#if ARM_ARCH_AT_LEAST(8, 5)
- mrs x9, scxtnum_el2
- str x9, [x0, #CTX_SCXTNUM_EL2]
+ mrs x13, scxtnum_el2
+ str x13, [x0, #CTX_SCXTNUM_EL2]
#endif
ret
endfunc el2_sysregs_context_save
+
/* -----------------------------------------------------
* The following function strictly follows the AArch64
- * PCS to use x9-x17 (temporary caller-saved registers)
+ * PCS to use x9-x16 (temporary caller-saved registers)
* to restore EL2 system register context. It assumes
* that 'x0' is pointing to a 'el2_sys_regs' structure
* from where the register context will be restored
@@ -246,7 +213,6 @@
* -----------------------------------------------------
*/
func el2_sysregs_context_restore
-
ldp x9, x10, [x0, #CTX_ACTLR_EL2]
msr actlr_el2, x9
msr afsr0_el2, x10
@@ -257,74 +223,66 @@
ldp x13, x14, [x0, #CTX_CNTHCTL_EL2]
msr cnthctl_el2, x13
- msr cnthp_ctl_el2, x14
+ msr cntvoff_el2, x14
- ldp x15, x16, [x0, #CTX_CNTHP_CVAL_EL2]
- msr cnthp_cval_el2, x15
- msr cnthp_tval_el2, x16
-
- ldp x17, x9, [x0, #CTX_CNTVOFF_EL2]
- msr cntvoff_el2, x17
- msr cptr_el2, x9
+ ldr x15, [x0, #CTX_CPTR_EL2]
+ msr cptr_el2, x15
#if CTX_INCLUDE_AARCH32_REGS
- ldp x10, x11, [x0, #CTX_DBGVCR32_EL2]
- msr dbgvcr32_el2, x10
-#else
- ldr x11, [x0, #CTX_ELR_EL2]
+ ldr x16, [x0, #CTX_DBGVCR32_EL2]
+ msr dbgvcr32_el2, x16
#endif
- msr elr_el2, x11
- ldp x14, x15, [x0, #CTX_ESR_EL2]
- msr esr_el2, x14
- msr far_el2, x15
+ ldp x9, x10, [x0, #CTX_ELR_EL2]
+ msr elr_el2, x9
+ msr esr_el2, x10
- ldp x16, x17, [x0, #CTX_HACR_EL2]
- msr hacr_el2, x16
- msr hcr_el2, x17
+ ldp x11, x12, [x0, #CTX_FAR_EL2]
+ msr far_el2, x11
+ msr hacr_el2, x12
- ldp x9, x10, [x0, #CTX_HPFAR_EL2]
- msr hpfar_el2, x9
- msr hstr_el2, x10
+ ldp x13, x14, [x0, #CTX_HCR_EL2]
+ msr hcr_el2, x13
+ msr hpfar_el2, x14
- ldp x11, x12, [x0, #CTX_ICC_SRE_EL2]
- msr ICC_SRE_EL2, x11
- msr ICH_HCR_EL2, x12
+ ldp x15, x16, [x0, #CTX_HSTR_EL2]
+ msr hstr_el2, x15
+ msr ICC_SRE_EL2, x16
- ldp x13, x14, [x0, #CTX_ICH_VMCR_EL2]
- msr ICH_VMCR_EL2, x13
- msr mair_el2, x14
+ ldp x9, x10, [x0, #CTX_ICH_HCR_EL2]
+ msr ICH_HCR_EL2, x9
+ msr ICH_VMCR_EL2, x10
+
+ ldp x11, x12, [x0, #CTX_MAIR_EL2]
+ msr mair_el2, x11
+ msr mdcr_el2, x12
#if ENABLE_SPE_FOR_LOWER_ELS
- ldp x15, x16, [x0, #CTX_MDCR_EL2]
- msr PMSCR_EL2, x16
-#else
- ldr x15, [x0, #CTX_MDCR_EL2]
+ ldr x13, [x0, #CTX_PMSCR_EL2]
+ msr PMSCR_EL2, x13
#endif
- msr mdcr_el2, x15
+ ldr x14, [x0, #CTX_SCTLR_EL2]
+ msr sctlr_el2, x14
- ldp x17, x9, [x0, #CTX_SCTLR_EL2]
- msr sctlr_el2, x17
- msr spsr_el2, x9
+ ldp x15, x16, [x0, #CTX_SPSR_EL2]
+ msr spsr_el2, x15
+ msr sp_el2, x16
- ldp x10, x11, [x0, #CTX_SP_EL2]
- msr sp_el2, x10
- msr tcr_el2, x11
+ ldp x9, x10, [x0, #CTX_TCR_EL2]
+ msr tcr_el2, x9
+ msr tpidr_el2, x10
- ldp x12, x13, [x0, #CTX_TPIDR_EL2]
- msr tpidr_el2, x12
- msr ttbr0_el2, x13
+ ldp x11, x12, [x0, #CTX_TTBR0_EL2]
+ msr ttbr0_el2, x11
+ msr vbar_el2, x12
- ldp x13, x14, [x0, #CTX_VBAR_EL2]
- msr vbar_el2, x13
- msr vmpidr_el2, x14
+ ldp x13, x14, [x0, #CTX_VMPIDR_EL2]
+ msr vmpidr_el2, x13
+ msr vpidr_el2, x14
- ldp x15, x16, [x0, #CTX_VPIDR_EL2]
- msr vpidr_el2, x15
- msr vtcr_el2, x16
-
- ldr x17, [x0, #CTX_VTTBR_EL2]
- msr vttbr_el2, x17
+ ldp x15, x16, [x0, #CTX_VTCR_EL2]
+ msr vtcr_el2, x15
+ msr vttbr_el2, x16
#if CTX_INCLUDE_MTE_REGS
ldr x9, [x0, #CTX_TFSR_EL2]
@@ -332,100 +290,76 @@
#endif
#if ENABLE_MPAM_FOR_LOWER_ELS
- ldp x10, x11, [x0, #CTX_MPAM2_EL2]
+ ldr x10, [x0, #CTX_MPAM2_EL2]
msr MPAM2_EL2, x10
+
+ ldp x11, x12, [x0, #CTX_MPAMHCR_EL2]
msr MPAMHCR_EL2, x11
-
- ldp x12, x13, [x0, #CTX_MPAMVPM0_EL2]
msr MPAMVPM0_EL2, x12
+
+ ldp x13, x14, [x0, #CTX_MPAMVPM1_EL2]
msr MPAMVPM1_EL2, x13
-
- ldp x14, x15, [x0, #CTX_MPAMVPM2_EL2]
msr MPAMVPM2_EL2, x14
+
+ ldp x15, x16, [x0, #CTX_MPAMVPM3_EL2]
msr MPAMVPM3_EL2, x15
-
- ldp x16, x17, [x0, #CTX_MPAMVPM4_EL2]
msr MPAMVPM4_EL2, x16
- msr MPAMVPM5_EL2, x17
- ldp x9, x10, [x0, #CTX_MPAMVPM6_EL2]
- msr MPAMVPM6_EL2, x9
- msr MPAMVPM7_EL2, x10
+ ldp x9, x10, [x0, #CTX_MPAMVPM5_EL2]
+ msr MPAMVPM5_EL2, x9
+ msr MPAMVPM6_EL2, x10
- ldr x11, [x0, #CTX_MPAMVPMV_EL2]
- msr MPAMVPMV_EL2, x11
+ ldp x11, x12, [x0, #CTX_MPAMVPM7_EL2]
+ msr MPAMVPM7_EL2, x11
+ msr MPAMVPMV_EL2, x12
#endif
#if ARM_ARCH_AT_LEAST(8, 6)
- ldp x12, x13, [x0, #CTX_HAFGRTR_EL2]
- msr HAFGRTR_EL2, x12
- msr HDFGRTR_EL2, x13
+ ldp x13, x14, [x0, #CTX_HAFGRTR_EL2]
+ msr HAFGRTR_EL2, x13
+ msr HDFGRTR_EL2, x14
- ldp x14, x15, [x0, #CTX_HDFGWTR_EL2]
- msr HDFGWTR_EL2, x14
- msr HFGITR_EL2, x15
+ ldp x15, x16, [x0, #CTX_HDFGWTR_EL2]
+ msr HDFGWTR_EL2, x15
+ msr HFGITR_EL2, x16
- ldp x16, x17, [x0, #CTX_HFGRTR_EL2]
- msr HFGRTR_EL2, x16
- msr HFGWTR_EL2, x17
+ ldp x9, x10, [x0, #CTX_HFGRTR_EL2]
+ msr HFGRTR_EL2, x9
+ msr HFGWTR_EL2, x10
- ldr x9, [x0, #CTX_CNTPOFF_EL2]
- msr CNTPOFF_EL2, x9
+ ldr x11, [x0, #CTX_CNTPOFF_EL2]
+ msr CNTPOFF_EL2, x11
#endif
#if ARM_ARCH_AT_LEAST(8, 4)
- ldp x10, x11, [x0, #CTX_CNTHPS_CTL_EL2]
- msr cnthps_ctl_el2, x10
- msr cnthps_cval_el2, x11
-
- ldp x12, x13, [x0, #CTX_CNTHPS_TVAL_EL2]
- msr cnthps_tval_el2, x12
- msr cnthvs_ctl_el2, x13
-
- ldp x14, x15, [x0, #CTX_CNTHVS_CVAL_EL2]
- msr cnthvs_cval_el2, x14
- msr cnthvs_tval_el2, x15
-
- ldp x16, x17, [x0, #CTX_CNTHV_CTL_EL2]
- msr cnthv_ctl_el2, x16
- msr cnthv_cval_el2, x17
-
- ldp x9, x10, [x0, #CTX_CNTHV_TVAL_EL2]
- msr cnthv_tval_el2, x9
- msr contextidr_el2, x10
+ ldr x12, [x0, #CTX_CONTEXTIDR_EL2]
+ msr contextidr_el2, x12
#if CTX_INCLUDE_AARCH32_REGS
- ldr x11, [x0, #CTX_SDER32_EL2]
- msr sder32_el2, x11
+ ldr x13, [x0, #CTX_SDER32_EL2]
+ msr sder32_el2, x13
#endif
-
- ldr x12, [x0, #CTX_TTBR1_EL2]
- msr ttbr1_el2, x12
-
- ldr x13, [x0, #CTX_VDISR_EL2]
- msr vdisr_el2, x13
+ ldp x14, x15, [x0, #CTX_TTBR1_EL2]
+ msr ttbr1_el2, x14
+ msr vdisr_el2, x15
#if CTX_INCLUDE_NEVE_REGS
- ldr x14, [x0, #CTX_VNCR_EL2]
- msr vncr_el2, x14
+ ldr x16, [x0, #CTX_VNCR_EL2]
+ msr vncr_el2, x16
#endif
- ldr x15, [x0, #CTX_VSESR_EL2]
- msr vsesr_el2, x15
+ ldp x9, x10, [x0, #CTX_VSESR_EL2]
+ msr vsesr_el2, x9
+ msr vstcr_el2, x10
- ldr x16, [x0, #CTX_VSTCR_EL2]
- msr vstcr_el2, x16
-
- ldr x17, [x0, #CTX_VSTTBR_EL2]
- msr vsttbr_el2, x17
-
- ldr x9, [x0, #CTX_TRFCR_EL2]
- msr TRFCR_EL2, x9
+ ldp x11, x12, [x0, #CTX_VSTTBR_EL2]
+ msr vsttbr_el2, x11
+ msr TRFCR_EL2, x12
#endif
#if ARM_ARCH_AT_LEAST(8, 5)
- ldr x10, [x0, #CTX_SCXTNUM_EL2]
- msr scxtnum_el2, x10
+ ldr x13, [x0, #CTX_SCXTNUM_EL2]
+ msr scxtnum_el2, x13
#endif
ret
@@ -763,13 +697,14 @@
str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
/* ----------------------------------------------------------
- * Check if earlier initialization MDCR_EL3.SCCD to 1 failed,
- * meaning that ARMv8-PMU is not implemented and PMCR_EL0
- * should be saved in non-secure context.
+ * Check if earlier initialization MDCR_EL3.SCCD/MCCD to 1
+ * failed, meaning that FEAT_PMUv3p5/7 is not implemented and
+ * PMCR_EL0 should be saved in non-secure context.
* ----------------------------------------------------------
*/
+ mov_imm x10, (MDCR_SCCD_BIT | MDCR_MCCD_BIT)
mrs x9, mdcr_el3
- tst x9, #MDCR_SCCD_BIT
+ tst x9, x10
bne 1f
/* Secure Cycle Counter is not disabled */
@@ -858,13 +793,14 @@
/* ----------------------------------------------------------
* Back to Non-secure state.
- * Check if earlier initialization MDCR_EL3.SCCD to 1 failed,
- * meaning that ARMv8-PMU is not implemented and PMCR_EL0
- * should be restored from non-secure context.
+ * Check if earlier initialization MDCR_EL3.SCCD/MCCD to 1
+ * failed, meaning that FEAT_PMUv3p5/7 is not implemented and
+ * PMCR_EL0 should be restored from non-secure context.
* ----------------------------------------------------------
*/
+ mov_imm x1, (MDCR_SCCD_BIT | MDCR_MCCD_BIT)
mrs x0, mdcr_el3
- tst x0, #MDCR_SCCD_BIT
+ tst x0, x1
bne 2f
ldr x0, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
msr pmcr_el0, x0
@@ -965,6 +901,24 @@
msr spsr_el3, x16
msr elr_el3, x17
+#if IMAGE_BL31
+ /* ----------------------------------------------------------
+ * Restore CPTR_EL3.
+ * ZCR is only restored if SVE is supported and enabled.
+ * Synchronization is required before zcr_el3 is addressed.
+ * ----------------------------------------------------------
+ */
+ ldp x19, x20, [sp, #CTX_EL3STATE_OFFSET + CTX_CPTR_EL3]
+ msr cptr_el3, x19
+
+ ands x19, x19, #CPTR_EZ_BIT
+ beq sve_not_enabled
+
+ isb
+ msr S3_6_C1_C2_0, x20 /* zcr_el3 */
+sve_not_enabled:
+#endif
+
#if IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639
/* ----------------------------------------------------------
* Restore mitigation state as it was on entry to EL3
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 72d463b..7c6f953 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -25,6 +25,7 @@
#include <lib/extensions/twed.h>
#include <lib/utils.h>
+static void enable_extensions_secure(cpu_context_t *ctx);
/*******************************************************************************
* Context management library initialisation routine. This library is used by
@@ -60,7 +61,7 @@
*
* To prepare the register state for entry call cm_prepare_el3_exit() and
* el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to
- * cm_e1_sysreg_context_restore().
+ * cm_el1_sysregs_context_restore().
******************************************************************************/
void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
{
@@ -180,6 +181,12 @@
scr_el3 |= get_scr_el3_from_routing_model(security_state);
#endif
+ /* Save the initialized value of CPTR_EL3 register */
+ write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3());
+ if (security_state == SECURE) {
+ enable_extensions_secure(ctx);
+ }
+
/*
* SCR_EL3.HCE: Enable HVC instructions if next execution state is
* AArch64 and next EL is EL2, or if next execution state is AArch32 and
@@ -217,6 +224,16 @@
}
/*
+ * FEAT_AMUv1p1 virtual offset registers are only accessible from EL3
+ * and EL2, when clear, this bit traps accesses from EL2 so we set it
+ * to 1 when EL2 is present.
+ */
+ if (is_armv8_6_feat_amuv1p1_present() &&
+ (el_implemented(2) != EL_IMPL_NONE)) {
+ scr_el3 |= SCR_AMVOFFEN_BIT;
+ }
+
+ /*
* Initialise SCTLR_EL1 to the reset value corresponding to the target
* execution state setting all fields rather than relying of the hw.
* Some fields have architecturally UNKNOWN reset values and these are
@@ -276,7 +293,7 @@
/*
* Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2
- * and other EL2 registers are set up by cm_prepare_ns_entry() as they
+ * and other EL2 registers are set up by cm_prepare_el3_exit() as they
* are not part of the stored cpu_context.
*/
write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx);
@@ -313,7 +330,7 @@
* When EL2 is implemented but unused `el2_unused` is non-zero, otherwise
* it is zero.
******************************************************************************/
-static void enable_extensions_nonsecure(bool el2_unused)
+static void enable_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx)
{
#if IMAGE_BL31
#if ENABLE_SPE_FOR_LOWER_ELS
@@ -321,11 +338,11 @@
#endif
#if ENABLE_AMU
- amu_enable(el2_unused);
+ amu_enable(el2_unused, ctx);
#endif
#if ENABLE_SVE_FOR_NS
- sve_enable(el2_unused);
+ sve_enable(ctx);
#endif
#if ENABLE_MPAM_FOR_LOWER_ELS
@@ -335,6 +352,18 @@
}
/*******************************************************************************
+ * Enable architecture extensions on first entry to Secure world.
+ ******************************************************************************/
+static void enable_extensions_secure(cpu_context_t *ctx)
+{
+#if IMAGE_BL31
+#if ENABLE_SVE_FOR_SWD
+ sve_enable(ctx);
+#endif
+#endif
+}
+
+/*******************************************************************************
* The following function initializes the cpu_context for a CPU specified by
* its `cpu_idx` for first use, and sets the initial entrypoint state as
* specified by the entry_point_info structure.
@@ -568,7 +597,7 @@
write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL &
~(CNTHP_CTL_ENABLE_BIT));
}
- enable_extensions_nonsecure(el2_unused);
+ enable_extensions_nonsecure(el2_unused, ctx);
}
cm_el1_sysregs_context_restore(security_state);
diff --git a/lib/extensions/amu/aarch32/amu.c b/lib/extensions/amu/aarch32/amu.c
index 0f75f07..ed56ddd 100644
--- a/lib/extensions/amu/aarch32/amu.c
+++ b/lib/extensions/amu/aarch32/amu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -18,13 +18,17 @@
static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
-/* Check if AMUv1 for Armv8.4 or 8.6 is implemented */
-bool amu_supported(void)
+/*
+ * Get AMU version value from pfr0.
+ * Return values
+ * ID_PFR0_AMU_V1: FEAT_AMUv1 supported (introduced in ARM v8.4)
+ * ID_PFR0_AMU_V1P1: FEAT_AMUv1p1 supported (introduced in ARM v8.6)
+ * ID_PFR0_AMU_NOT_SUPPORTED: not supported
+ */
+unsigned int amu_get_version(void)
{
- uint32_t features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT;
-
- features &= ID_PFR0_AMU_MASK;
- return ((features == 1U) || (features == 2U));
+ return (unsigned int)(read_id_pfr0() >> ID_PFR0_AMU_SHIFT) &
+ ID_PFR0_AMU_MASK;
}
#if AMU_GROUP1_NR_COUNTERS
@@ -43,7 +47,7 @@
*/
void amu_enable(bool el2_unused)
{
- if (!amu_supported()) {
+ if (amu_get_version() == ID_PFR0_AMU_NOT_SUPPORTED) {
return;
}
@@ -87,12 +91,31 @@
/* Enable group 1 counters */
write_amcntenset1(AMU_GROUP1_COUNTERS_MASK);
#endif
+
+ /* Initialize FEAT_AMUv1p1 features if present. */
+ if (amu_get_version() < ID_PFR0_AMU_V1P1) {
+ return;
+ }
+
+#if AMU_RESTRICT_COUNTERS
+ /*
+ * FEAT_AMUv1p1 adds a register field to restrict access to group 1
+ * counters at all but the highest implemented EL. This is controlled
+ * with the AMU_RESTRICT_COUNTERS compile time flag, when set, system
+ * register reads at lower ELs return zero. Reads from the memory
+ * mapped view are unaffected.
+ */
+ VERBOSE("AMU group 1 counter access restricted.\n");
+ write_amcr(read_amcr() | AMCR_CG1RZ_BIT);
+#else
+ write_amcr(read_amcr() & ~AMCR_CG1RZ_BIT);
+#endif
}
/* Read the group 0 counter identified by the given `idx`. */
uint64_t amu_group0_cnt_read(unsigned int idx)
{
- assert(amu_supported());
+ assert(amu_get_version() != ID_PFR0_AMU_NOT_SUPPORTED);
assert(idx < AMU_GROUP0_NR_COUNTERS);
return amu_group0_cnt_read_internal(idx);
@@ -101,7 +124,7 @@
/* Write the group 0 counter identified by the given `idx` with `val` */
void amu_group0_cnt_write(unsigned int idx, uint64_t val)
{
- assert(amu_supported());
+ assert(amu_get_version() != ID_PFR0_AMU_NOT_SUPPORTED);
assert(idx < AMU_GROUP0_NR_COUNTERS);
amu_group0_cnt_write_internal(idx, val);
@@ -112,7 +135,7 @@
/* Read the group 1 counter identified by the given `idx` */
uint64_t amu_group1_cnt_read(unsigned int idx)
{
- assert(amu_supported());
+ assert(amu_get_version() != ID_PFR0_AMU_NOT_SUPPORTED);
assert(amu_group1_supported());
assert(idx < AMU_GROUP1_NR_COUNTERS);
@@ -122,7 +145,7 @@
/* Write the group 1 counter identified by the given `idx` with `val` */
void amu_group1_cnt_write(unsigned int idx, uint64_t val)
{
- assert(amu_supported());
+ assert(amu_get_version() != ID_PFR0_AMU_NOT_SUPPORTED);
assert(amu_group1_supported());
assert(idx < AMU_GROUP1_NR_COUNTERS);
@@ -136,7 +159,7 @@
*/
void amu_group1_set_evtype(unsigned int idx, unsigned int val)
{
- assert(amu_supported());
+ assert(amu_get_version() != ID_PFR0_AMU_NOT_SUPPORTED);
assert(amu_group1_supported());
assert(idx < AMU_GROUP1_NR_COUNTERS);
@@ -150,7 +173,7 @@
struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
unsigned int i;
- if (!amu_supported()) {
+ if (amu_get_version() == ID_PFR0_AMU_NOT_SUPPORTED) {
return (void *)-1;
}
@@ -197,7 +220,7 @@
struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
unsigned int i;
- if (!amu_supported()) {
+ if (amu_get_version() == ID_PFR0_AMU_NOT_SUPPORTED) {
return (void *)-1;
}
diff --git a/lib/extensions/amu/aarch32/amu_helpers.S b/lib/extensions/amu/aarch32/amu_helpers.S
index effb8e5..d387341 100644
--- a/lib/extensions/amu/aarch32/amu_helpers.S
+++ b/lib/extensions/amu/aarch32/amu_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -75,13 +75,13 @@
1:
stcopr16 r2, r3, AMEVCNTR00 /* index 0 */
- bx lr
+ bx lr
stcopr16 r2, r3, AMEVCNTR01 /* index 1 */
- bx lr
+ bx lr
stcopr16 r2, r3, AMEVCNTR02 /* index 2 */
- bx lr
+ bx lr
stcopr16 r2, r3, AMEVCNTR03 /* index 3 */
- bx lr
+ bx lr
endfunc amu_group0_cnt_write_internal
/*
@@ -169,37 +169,37 @@
bx r1
1:
- stcopr16 r2, r3, AMEVCNTR10 /* index 0 */
+ stcopr16 r2, r3, AMEVCNTR10 /* index 0 */
bx lr
- stcopr16 r2, r3, AMEVCNTR11 /* index 1 */
+ stcopr16 r2, r3, AMEVCNTR11 /* index 1 */
bx lr
- stcopr16 r2, r3, AMEVCNTR12 /* index 2 */
+ stcopr16 r2, r3, AMEVCNTR12 /* index 2 */
bx lr
- stcopr16 r2, r3, AMEVCNTR13 /* index 3 */
+ stcopr16 r2, r3, AMEVCNTR13 /* index 3 */
bx lr
- stcopr16 r2, r3, AMEVCNTR14 /* index 4 */
+ stcopr16 r2, r3, AMEVCNTR14 /* index 4 */
bx lr
- stcopr16 r2, r3, AMEVCNTR15 /* index 5 */
+ stcopr16 r2, r3, AMEVCNTR15 /* index 5 */
bx lr
- stcopr16 r2, r3, AMEVCNTR16 /* index 6 */
+ stcopr16 r2, r3, AMEVCNTR16 /* index 6 */
bx lr
- stcopr16 r2, r3, AMEVCNTR17 /* index 7 */
+ stcopr16 r2, r3, AMEVCNTR17 /* index 7 */
bx lr
- stcopr16 r2, r3, AMEVCNTR18 /* index 8 */
+ stcopr16 r2, r3, AMEVCNTR18 /* index 8 */
bx lr
- stcopr16 r2, r3, AMEVCNTR19 /* index 9 */
+ stcopr16 r2, r3, AMEVCNTR19 /* index 9 */
bx lr
- stcopr16 r2, r3, AMEVCNTR1A /* index 10 */
+ stcopr16 r2, r3, AMEVCNTR1A /* index 10 */
bx lr
- stcopr16 r2, r3, AMEVCNTR1B /* index 11 */
+ stcopr16 r2, r3, AMEVCNTR1B /* index 11 */
bx lr
- stcopr16 r2, r3, AMEVCNTR1C /* index 12 */
+ stcopr16 r2, r3, AMEVCNTR1C /* index 12 */
bx lr
- stcopr16 r2, r3, AMEVCNTR1D /* index 13 */
+ stcopr16 r2, r3, AMEVCNTR1D /* index 13 */
bx lr
- stcopr16 r2, r3, AMEVCNTR1E /* index 14 */
+ stcopr16 r2, r3, AMEVCNTR1E /* index 14 */
bx lr
- stcopr16 r2, r3, AMEVCNTR1F /* index 15 */
+ stcopr16 r2, r3, AMEVCNTR1F /* index 15 */
bx lr
endfunc amu_group1_cnt_write_internal
@@ -234,36 +234,36 @@
bx r2
1:
- stcopr r1, AMEVTYPER10 /* index 0 */
+ stcopr r1, AMEVTYPER10 /* index 0 */
bx lr
- stcopr r1, AMEVTYPER11 /* index 1 */
+ stcopr r1, AMEVTYPER11 /* index 1 */
bx lr
- stcopr r1, AMEVTYPER12 /* index 2 */
+ stcopr r1, AMEVTYPER12 /* index 2 */
bx lr
- stcopr r1, AMEVTYPER13 /* index 3 */
+ stcopr r1, AMEVTYPER13 /* index 3 */
bx lr
- stcopr r1, AMEVTYPER14 /* index 4 */
+ stcopr r1, AMEVTYPER14 /* index 4 */
bx lr
- stcopr r1, AMEVTYPER15 /* index 5 */
+ stcopr r1, AMEVTYPER15 /* index 5 */
bx lr
- stcopr r1, AMEVTYPER16 /* index 6 */
+ stcopr r1, AMEVTYPER16 /* index 6 */
bx lr
- stcopr r1, AMEVTYPER17 /* index 7 */
+ stcopr r1, AMEVTYPER17 /* index 7 */
bx lr
- stcopr r1, AMEVTYPER18 /* index 8 */
+ stcopr r1, AMEVTYPER18 /* index 8 */
bx lr
- stcopr r1, AMEVTYPER19 /* index 9 */
+ stcopr r1, AMEVTYPER19 /* index 9 */
bx lr
- stcopr r1, AMEVTYPER1A /* index 10 */
+ stcopr r1, AMEVTYPER1A /* index 10 */
bx lr
- stcopr r1, AMEVTYPER1B /* index 11 */
+ stcopr r1, AMEVTYPER1B /* index 11 */
bx lr
- stcopr r1, AMEVTYPER1C /* index 12 */
+ stcopr r1, AMEVTYPER1C /* index 12 */
bx lr
- stcopr r1, AMEVTYPER1D /* index 13 */
+ stcopr r1, AMEVTYPER1D /* index 13 */
bx lr
- stcopr r1, AMEVTYPER1E /* index 14 */
+ stcopr r1, AMEVTYPER1E /* index 14 */
bx lr
- stcopr r1, AMEVTYPER1F /* index 15 */
+ stcopr r1, AMEVTYPER1F /* index 15 */
bx lr
endfunc amu_group1_set_evtype_internal
diff --git a/lib/extensions/amu/aarch64/amu.c b/lib/extensions/amu/aarch64/amu.c
index 4997363..295c0d5 100644
--- a/lib/extensions/amu/aarch64/amu.c
+++ b/lib/extensions/amu/aarch64/amu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,6 +8,7 @@
#include <stdbool.h>
#include <arch.h>
+#include <arch_features.h>
#include <arch_helpers.h>
#include <lib/el3_runtime/pubsub_events.h>
@@ -18,13 +19,17 @@
static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
-/* Check if AMUv1 for Armv8.4 or 8.6 is implemented */
-bool amu_supported(void)
+/*
+ * Get AMU version value from aa64pfr0.
+ * Return values
+ * ID_AA64PFR0_AMU_V1: FEAT_AMUv1 supported (introduced in ARM v8.4)
+ * ID_AA64PFR0_AMU_V1P1: FEAT_AMUv1p1 supported (introduced in ARM v8.6)
+ * ID_AA64PFR0_AMU_NOT_SUPPORTED: not supported
+ */
+unsigned int amu_get_version(void)
{
- uint64_t features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT;
-
- features &= ID_AA64PFR0_AMU_MASK;
- return ((features == 1U) || (features == 2U));
+ return (unsigned int)(read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT) &
+ ID_AA64PFR0_AMU_MASK;
}
#if AMU_GROUP1_NR_COUNTERS
@@ -41,11 +46,12 @@
* Enable counters. This function is meant to be invoked
* by the context management library before exiting from EL3.
*/
-void amu_enable(bool el2_unused)
+void amu_enable(bool el2_unused, cpu_context_t *ctx)
{
uint64_t v;
+ unsigned int amu_version = amu_get_version();
- if (!amu_supported()) {
+ if (amu_version == ID_AA64PFR0_AMU_NOT_SUPPORTED) {
return;
}
@@ -82,12 +88,13 @@
}
/*
- * CPTR_EL3.TAM: Set to zero so that any accesses to
+ * Retrieve and update the CPTR_EL3 value from the context mentioned
+ * in 'ctx'. Set CPTR_EL3.TAM to zero so that any accesses to
* the Activity Monitor registers do not trap to EL3.
*/
- v = read_cptr_el3();
+ v = read_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3);
v &= ~TAM_BIT;
- write_cptr_el3(v);
+ write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, v);
/* Enable group 0 counters */
write_amcntenset0_el0(AMU_GROUP0_COUNTERS_MASK);
@@ -96,12 +103,36 @@
/* Enable group 1 counters */
write_amcntenset1_el0(AMU_GROUP1_COUNTERS_MASK);
#endif
+
+ /* Initialize FEAT_AMUv1p1 features if present. */
+ if (amu_version < ID_AA64PFR0_AMU_V1P1) {
+ return;
+ }
+
+ if (el2_unused) {
+ /* Make sure virtual offsets are disabled if EL2 not used. */
+ write_hcr_el2(read_hcr_el2() & ~HCR_AMVOFFEN_BIT);
+ }
+
+#if AMU_RESTRICT_COUNTERS
+ /*
+ * FEAT_AMUv1p1 adds a register field to restrict access to group 1
+ * counters at all but the highest implemented EL. This is controlled
+ * with the AMU_RESTRICT_COUNTERS compile time flag, when set, system
+ * register reads at lower ELs return zero. Reads from the memory
+ * mapped view are unaffected.
+ */
+ VERBOSE("AMU group 1 counter access restricted.\n");
+ write_amcr_el0(read_amcr_el0() | AMCR_CG1RZ_BIT);
+#else
+ write_amcr_el0(read_amcr_el0() & ~AMCR_CG1RZ_BIT);
+#endif
}
/* Read the group 0 counter identified by the given `idx`. */
uint64_t amu_group0_cnt_read(unsigned int idx)
{
- assert(amu_supported());
+ assert(amu_get_version() != ID_AA64PFR0_AMU_NOT_SUPPORTED);
assert(idx < AMU_GROUP0_NR_COUNTERS);
return amu_group0_cnt_read_internal(idx);
@@ -110,18 +141,49 @@
/* Write the group 0 counter identified by the given `idx` with `val` */
void amu_group0_cnt_write(unsigned int idx, uint64_t val)
{
- assert(amu_supported());
+ assert(amu_get_version() != ID_AA64PFR0_AMU_NOT_SUPPORTED);
assert(idx < AMU_GROUP0_NR_COUNTERS);
amu_group0_cnt_write_internal(idx, val);
isb();
}
+/*
+ * Read the group 0 offset register for a given index. Index must be 0, 2,
+ * or 3, the register for 1 does not exist.
+ *
+ * Using this function requires FEAT_AMUv1p1 support.
+ */
+uint64_t amu_group0_voffset_read(unsigned int idx)
+{
+ assert(amu_get_version() >= ID_AA64PFR0_AMU_V1P1);
+ assert(idx < AMU_GROUP0_NR_COUNTERS);
+ assert(idx != 1U);
+
+ return amu_group0_voffset_read_internal(idx);
+}
+
+/*
+ * Write the group 0 offset register for a given index. Index must be 0, 2, or
+ * 3, the register for 1 does not exist.
+ *
+ * Using this function requires FEAT_AMUv1p1 support.
+ */
+void amu_group0_voffset_write(unsigned int idx, uint64_t val)
+{
+ assert(amu_get_version() >= ID_AA64PFR0_AMU_V1P1);
+ assert(idx < AMU_GROUP0_NR_COUNTERS);
+ assert(idx != 1U);
+
+ amu_group0_voffset_write_internal(idx, val);
+ isb();
+}
+
#if AMU_GROUP1_NR_COUNTERS
/* Read the group 1 counter identified by the given `idx` */
-uint64_t amu_group1_cnt_read(unsigned int idx)
+uint64_t amu_group1_cnt_read(unsigned int idx)
{
- assert(amu_supported());
+ assert(amu_get_version() != ID_AA64PFR0_AMU_NOT_SUPPORTED);
assert(amu_group1_supported());
assert(idx < AMU_GROUP1_NR_COUNTERS);
@@ -129,9 +191,9 @@
}
/* Write the group 1 counter identified by the given `idx` with `val` */
-void amu_group1_cnt_write(unsigned int idx, uint64_t val)
+void amu_group1_cnt_write(unsigned int idx, uint64_t val)
{
- assert(amu_supported());
+ assert(amu_get_version() != ID_AA64PFR0_AMU_NOT_SUPPORTED);
assert(amu_group1_supported());
assert(idx < AMU_GROUP1_NR_COUNTERS);
@@ -140,12 +202,45 @@
}
/*
+ * Read the group 1 offset register for a given index.
+ *
+ * Using this function requires FEAT_AMUv1p1 support.
+ */
+uint64_t amu_group1_voffset_read(unsigned int idx)
+{
+ assert(amu_get_version() >= ID_AA64PFR0_AMU_V1P1);
+ assert(amu_group1_supported());
+ assert(idx < AMU_GROUP1_NR_COUNTERS);
+ assert(((read_amcg1idr_el0() >> AMCG1IDR_VOFF_SHIFT) &
+ (1ULL << idx)) != 0ULL);
+
+ return amu_group1_voffset_read_internal(idx);
+}
+
+/*
+ * Write the group 1 offset register for a given index.
+ *
+ * Using this function requires FEAT_AMUv1p1 support.
+ */
+void amu_group1_voffset_write(unsigned int idx, uint64_t val)
+{
+ assert(amu_get_version() >= ID_AA64PFR0_AMU_V1P1);
+ assert(amu_group1_supported());
+ assert(idx < AMU_GROUP1_NR_COUNTERS);
+ assert(((read_amcg1idr_el0() >> AMCG1IDR_VOFF_SHIFT) &
+ (1ULL << idx)) != 0ULL);
+
+ amu_group1_voffset_write_internal(idx, val);
+ isb();
+}
+
+/*
* Program the event type register for the given `idx` with
* the event number `val`
*/
void amu_group1_set_evtype(unsigned int idx, unsigned int val)
{
- assert(amu_supported());
+ assert(amu_get_version() != ID_AA64PFR0_AMU_NOT_SUPPORTED);
assert(amu_group1_supported());
assert(idx < AMU_GROUP1_NR_COUNTERS);
@@ -159,7 +254,7 @@
struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
unsigned int i;
- if (!amu_supported()) {
+ if (amu_get_version() == ID_AA64PFR0_AMU_NOT_SUPPORTED) {
return (void *)-1;
}
@@ -190,13 +285,37 @@
ctx->group0_cnts[i] = amu_group0_cnt_read(i);
}
+ /* Save group 0 virtual offsets if supported and enabled. */
+ if ((amu_get_version() >= ID_AA64PFR0_AMU_V1P1) &&
+ ((read_hcr_el2() & HCR_AMVOFFEN_BIT) != 0ULL)) {
+ /* Not using a loop because count is fixed and index 1 DNE. */
+ ctx->group0_voffsets[0U] = amu_group0_voffset_read(0U);
+ ctx->group0_voffsets[1U] = amu_group0_voffset_read(2U);
+ ctx->group0_voffsets[2U] = amu_group0_voffset_read(3U);
+ }
+
#if AMU_GROUP1_NR_COUNTERS
/* Save group 1 counters */
for (i = 0U; i < AMU_GROUP1_NR_COUNTERS; i++) {
- if ((AMU_GROUP1_COUNTERS_MASK & (1U << i)) != 0U) {
+ if ((AMU_GROUP1_COUNTERS_MASK & (1UL << i)) != 0U) {
ctx->group1_cnts[i] = amu_group1_cnt_read(i);
}
}
+
+ /* Save group 1 virtual offsets if supported and enabled. */
+ if ((amu_get_version() >= ID_AA64PFR0_AMU_V1P1) &&
+ ((read_hcr_el2() & HCR_AMVOFFEN_BIT) != 0ULL)) {
+ u_register_t amcg1idr = read_amcg1idr_el0() >>
+ AMCG1IDR_VOFF_SHIFT;
+ amcg1idr = amcg1idr & AMU_GROUP1_COUNTERS_MASK;
+
+ for (i = 0U; i < AMU_GROUP1_NR_COUNTERS; i++) {
+ if (((amcg1idr >> i) & 1ULL) != 0ULL) {
+ ctx->group1_voffsets[i] =
+ amu_group1_voffset_read(i);
+ }
+ }
+ }
#endif
return (void *)0;
}
@@ -206,7 +325,7 @@
struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
unsigned int i;
- if (!amu_supported()) {
+ if (amu_get_version() == ID_AA64PFR0_AMU_NOT_SUPPORTED) {
return (void *)-1;
}
@@ -227,17 +346,41 @@
amu_group0_cnt_write(i, ctx->group0_cnts[i]);
}
+ /* Restore group 0 virtual offsets if supported and enabled. */
+ if ((amu_get_version() >= ID_AA64PFR0_AMU_V1P1) &&
+ ((read_hcr_el2() & HCR_AMVOFFEN_BIT) != 0ULL)) {
+ /* Not using a loop because count is fixed and index 1 DNE. */
+ amu_group0_voffset_write(0U, ctx->group0_voffsets[0U]);
+ amu_group0_voffset_write(2U, ctx->group0_voffsets[1U]);
+ amu_group0_voffset_write(3U, ctx->group0_voffsets[2U]);
+ }
+
/* Restore group 0 counter configuration */
write_amcntenset0_el0(AMU_GROUP0_COUNTERS_MASK);
#if AMU_GROUP1_NR_COUNTERS
/* Restore group 1 counters */
for (i = 0U; i < AMU_GROUP1_NR_COUNTERS; i++) {
- if ((AMU_GROUP1_COUNTERS_MASK & (1U << i)) != 0U) {
+ if ((AMU_GROUP1_COUNTERS_MASK & (1UL << i)) != 0U) {
amu_group1_cnt_write(i, ctx->group1_cnts[i]);
}
}
+ /* Restore group 1 virtual offsets if supported and enabled. */
+ if ((amu_get_version() >= ID_AA64PFR0_AMU_V1P1) &&
+ ((read_hcr_el2() & HCR_AMVOFFEN_BIT) != 0ULL)) {
+ u_register_t amcg1idr = read_amcg1idr_el0() >>
+ AMCG1IDR_VOFF_SHIFT;
+ amcg1idr = amcg1idr & AMU_GROUP1_COUNTERS_MASK;
+
+ for (i = 0U; i < AMU_GROUP1_NR_COUNTERS; i++) {
+ if (((amcg1idr >> i) & 1ULL) != 0ULL) {
+ amu_group1_voffset_write(i,
+ ctx->group1_voffsets[i]);
+ }
+ }
+ }
+
/* Restore group 1 counter configuration */
write_amcntenset1_el0(AMU_GROUP1_COUNTERS_MASK);
#endif
diff --git a/lib/extensions/amu/aarch64/amu_helpers.S b/lib/extensions/amu/aarch64/amu_helpers.S
index 89007a3..9989abd 100644
--- a/lib/extensions/amu/aarch64/amu_helpers.S
+++ b/lib/extensions/amu/aarch64/amu_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,6 +14,12 @@
.globl amu_group1_cnt_write_internal
.globl amu_group1_set_evtype_internal
+ /* FEAT_AMUv1p1 virtualisation offset register functions */
+ .globl amu_group0_voffset_read_internal
+ .globl amu_group0_voffset_write_internal
+ .globl amu_group1_voffset_read_internal
+ .globl amu_group1_voffset_write_internal
+
/*
* uint64_t amu_group0_cnt_read_internal(int idx);
*
@@ -211,3 +217,169 @@
write AMEVTYPER1E_EL0 /* index 14 */
write AMEVTYPER1F_EL0 /* index 15 */
endfunc amu_group1_set_evtype_internal
+
+/*
+ * Accessor functions for virtual offset registers added with FEAT_AMUv1p1
+ */
+
+/*
+ * uint64_t amu_group0_voffset_read_internal(int idx);
+ *
+ * Given `idx`, read the corresponding AMU virtual offset register
+ * and return it in `x0`.
+ */
+func amu_group0_voffset_read_internal
+ adr x1, 1f
+#if ENABLE_ASSERTIONS
+ /*
+ * It can be dangerous to call this function with an
+ * out of bounds index. Ensure `idx` is valid.
+ */
+ tst x0, #~3
+ ASM_ASSERT(eq)
+ /* Make sure idx != 1 since AMEVCNTVOFF01_EL2 does not exist */
+ cmp x0, #1
+ ASM_ASSERT(ne)
+#endif
+ /*
+ * Given `idx` calculate address of mrs/ret instruction pair
+ * in the table below.
+ */
+ add x1, x1, x0, lsl #3 /* each mrs/ret sequence is 8 bytes */
+#if ENABLE_BTI
+ add x1, x1, x0, lsl #2 /* + "bti j" instruction */
+#endif
+ br x1
+
+1: read AMEVCNTVOFF00_EL2 /* index 0 */
+ .skip 8 /* AMEVCNTVOFF01_EL2 does not exist */
+#if ENABLE_BTI
+ .skip 4
+#endif
+ read AMEVCNTVOFF02_EL2 /* index 2 */
+ read AMEVCNTVOFF03_EL2 /* index 3 */
+endfunc amu_group0_voffset_read_internal
+
+/*
+ * void amu_group0_voffset_write_internal(int idx, uint64_t val);
+ *
+ * Given `idx`, write `val` to the corresponding AMU virtual offset register.
+ */
+func amu_group0_voffset_write_internal
+ adr x2, 1f
+#if ENABLE_ASSERTIONS
+ /*
+ * It can be dangerous to call this function with an
+ * out of bounds index. Ensure `idx` is valid.
+ */
+ tst x0, #~3
+ ASM_ASSERT(eq)
+ /* Make sure idx != 1 since AMEVCNTVOFF01_EL2 does not exist */
+ cmp x0, #1
+ ASM_ASSERT(ne)
+#endif
+ /*
+ * Given `idx` calculate address of mrs/ret instruction pair
+ * in the table below.
+ */
+ add x2, x2, x0, lsl #3 /* each msr/ret sequence is 8 bytes */
+#if ENABLE_BTI
+ add x2, x2, x0, lsl #2 /* + "bti j" instruction */
+#endif
+ br x2
+
+1: write AMEVCNTVOFF00_EL2 /* index 0 */
+ .skip 8 /* AMEVCNTVOFF01_EL2 does not exist */
+#if ENABLE_BTI
+ .skip 4
+#endif
+ write AMEVCNTVOFF02_EL2 /* index 2 */
+ write AMEVCNTVOFF03_EL2 /* index 3 */
+endfunc amu_group0_voffset_write_internal
+
+/*
+ * uint64_t amu_group1_voffset_read_internal(int idx);
+ *
+ * Given `idx`, read the corresponding AMU virtual offset register
+ * and return it in `x0`.
+ */
+func amu_group1_voffset_read_internal
+ adr x1, 1f
+#if ENABLE_ASSERTIONS
+ /*
+ * It can be dangerous to call this function with an
+ * out of bounds index. Ensure `idx` is valid.
+ */
+ tst x0, #~0xF
+ ASM_ASSERT(eq)
+#endif
+ /*
+ * Given `idx` calculate address of mrs/ret instruction pair
+ * in the table below.
+ */
+ add x1, x1, x0, lsl #3 /* each mrs/ret sequence is 8 bytes */
+#if ENABLE_BTI
+ add x1, x1, x0, lsl #2 /* + "bti j" instruction */
+#endif
+ br x1
+
+1: read AMEVCNTVOFF10_EL2 /* index 0 */
+ read AMEVCNTVOFF11_EL2 /* index 1 */
+ read AMEVCNTVOFF12_EL2 /* index 2 */
+ read AMEVCNTVOFF13_EL2 /* index 3 */
+ read AMEVCNTVOFF14_EL2 /* index 4 */
+ read AMEVCNTVOFF15_EL2 /* index 5 */
+ read AMEVCNTVOFF16_EL2 /* index 6 */
+ read AMEVCNTVOFF17_EL2 /* index 7 */
+ read AMEVCNTVOFF18_EL2 /* index 8 */
+ read AMEVCNTVOFF19_EL2 /* index 9 */
+ read AMEVCNTVOFF1A_EL2 /* index 10 */
+ read AMEVCNTVOFF1B_EL2 /* index 11 */
+ read AMEVCNTVOFF1C_EL2 /* index 12 */
+ read AMEVCNTVOFF1D_EL2 /* index 13 */
+ read AMEVCNTVOFF1E_EL2 /* index 14 */
+ read AMEVCNTVOFF1F_EL2 /* index 15 */
+endfunc amu_group1_voffset_read_internal
+
+/*
+ * void amu_group1_voffset_write_internal(int idx, uint64_t val);
+ *
+ * Given `idx`, write `val` to the corresponding AMU virtual offset register.
+ */
+func amu_group1_voffset_write_internal
+ adr x2, 1f
+#if ENABLE_ASSERTIONS
+ /*
+ * It can be dangerous to call this function with an
+ * out of bounds index. Ensure `idx` is valid.
+ */
+ tst x0, #~0xF
+ ASM_ASSERT(eq)
+#endif
+ /*
+ * Given `idx` calculate address of mrs/ret instruction pair
+ * in the table below.
+ */
+ add x2, x2, x0, lsl #3 /* each msr/ret sequence is 8 bytes */
+#if ENABLE_BTI
+ add x2, x2, x0, lsl #2 /* + "bti j" instruction */
+#endif
+ br x2
+
+1: write AMEVCNTVOFF10_EL2 /* index 0 */
+ write AMEVCNTVOFF11_EL2 /* index 1 */
+ write AMEVCNTVOFF12_EL2 /* index 2 */
+ write AMEVCNTVOFF13_EL2 /* index 3 */
+ write AMEVCNTVOFF14_EL2 /* index 4 */
+ write AMEVCNTVOFF15_EL2 /* index 5 */
+ write AMEVCNTVOFF16_EL2 /* index 6 */
+ write AMEVCNTVOFF17_EL2 /* index 7 */
+ write AMEVCNTVOFF18_EL2 /* index 8 */
+ write AMEVCNTVOFF19_EL2 /* index 9 */
+ write AMEVCNTVOFF1A_EL2 /* index 10 */
+ write AMEVCNTVOFF1B_EL2 /* index 11 */
+ write AMEVCNTVOFF1C_EL2 /* index 12 */
+ write AMEVCNTVOFF1D_EL2 /* index 13 */
+ write AMEVCNTVOFF1E_EL2 /* index 14 */
+ write AMEVCNTVOFF1F_EL2 /* index 15 */
+endfunc amu_group1_voffset_write_internal
diff --git a/lib/extensions/ras/ras_common.c b/lib/extensions/ras/ras_common.c
index 36f9a95..622879e 100644
--- a/lib/extensions/ras/ras_common.c
+++ b/lib/extensions/ras/ras_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -139,7 +139,7 @@
assert(ras_interrupt_mappings.num_intrs > 0UL);
start = 0;
- end = (int) ras_interrupt_mappings.num_intrs;
+ end = (int)ras_interrupt_mappings.num_intrs - 1;
while (start <= end) {
mid = ((end + start) / 2);
if (intr_raw == ras_inrs[mid].intr_number) {
diff --git a/lib/extensions/sve/sve.c b/lib/extensions/sve/sve.c
index fa4ac77..2702c30 100644
--- a/lib/extensions/sve/sve.c
+++ b/lib/extensions/sve/sve.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,7 +11,13 @@
#include <lib/el3_runtime/pubsub.h>
#include <lib/extensions/sve.h>
-bool sve_supported(void)
+/*
+ * Converts SVE vector size restriction in bytes to LEN according to ZCR_EL3 documentation.
+ * VECTOR_SIZE = (LEN+1) * 128
+ */
+#define CONVERT_SVE_LENGTH(x) (((x / 128) - 1))
+
+static bool sve_supported(void)
{
uint64_t features;
@@ -19,113 +25,21 @@
return (features & ID_AA64PFR0_SVE_MASK) == 1U;
}
-static void *disable_sve_hook(const void *arg)
+void sve_enable(cpu_context_t *context)
{
- uint64_t cptr;
+ u_register_t cptr_el3;
- if (!sve_supported())
- return (void *)-1;
-
- /*
- * Disable SVE, SIMD and FP access for the Secure world.
- * As the SIMD/FP registers are part of the SVE Z-registers, any
- * use of SIMD/FP functionality will corrupt the SVE registers.
- * Therefore it is necessary to prevent use of SIMD/FP support
- * in the Secure world as well as SVE functionality.
- */
- cptr = read_cptr_el3();
- cptr = (cptr | TFP_BIT) & ~(CPTR_EZ_BIT);
- write_cptr_el3(cptr);
-
- /*
- * No explicit ISB required here as ERET to switch to Secure
- * world covers it
- */
- return (void *)0;
-}
-
-static void *enable_sve_hook(const void *arg)
-{
- uint64_t cptr;
-
- if (!sve_supported())
- return (void *)-1;
-
- /*
- * Enable SVE, SIMD and FP access for the Non-secure world.
- */
- cptr = read_cptr_el3();
- cptr = (cptr | CPTR_EZ_BIT) & ~(TFP_BIT);
- write_cptr_el3(cptr);
-
- /*
- * No explicit ISB required here as ERET to switch to Non-secure
- * world covers it
- */
- return (void *)0;
-}
-
-void sve_enable(bool el2_unused)
-{
- uint64_t cptr;
-
- if (!sve_supported())
+ if (!sve_supported()) {
return;
-
-#if CTX_INCLUDE_FPREGS
- /*
- * CTX_INCLUDE_FPREGS is not supported on SVE enabled systems.
- */
- assert(0);
-#endif
- /*
- * Update CPTR_EL3 to enable access to SVE functionality for the
- * Non-secure world.
- * NOTE - assumed that CPTR_EL3.TFP is set to allow access to
- * the SIMD, floating-point and SVE support.
- *
- * CPTR_EL3.EZ: Set to 1 to enable access to SVE functionality
- * in the Non-secure world.
- */
- cptr = read_cptr_el3();
- cptr |= CPTR_EZ_BIT;
- write_cptr_el3(cptr);
-
- /*
- * Need explicit ISB here to guarantee that update to ZCR_ELx
- * and CPTR_EL2.TZ do not result in trap to EL3.
- */
- isb();
-
- /*
- * Ensure lower ELs have access to full vector length.
- */
- write_zcr_el3(ZCR_EL3_LEN_MASK);
-
- if (el2_unused) {
- /*
- * Update CPTR_EL2 to enable access to SVE functionality
- * for Non-secure world, EL2 and Non-secure EL1 and EL0.
- * NOTE - assumed that CPTR_EL2.TFP is set to allow
- * access to the SIMD, floating-point and SVE support.
- *
- * CPTR_EL2.TZ: Set to 0 to enable access to SVE support
- * for EL2 and Non-secure EL1 and EL0.
- */
- cptr = read_cptr_el2();
- cptr &= ~(CPTR_EL2_TZ_BIT);
- write_cptr_el2(cptr);
-
- /*
- * Ensure lower ELs have access to full vector length.
- */
- write_zcr_el2(ZCR_EL2_LEN_MASK);
}
- /*
- * No explicit ISB required here as ERET to switch to
- * Non-secure world covers it.
- */
-}
-SUBSCRIBE_TO_EVENT(cm_exited_normal_world, disable_sve_hook);
-SUBSCRIBE_TO_EVENT(cm_entering_normal_world, enable_sve_hook);
+ cptr_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3);
+
+ /* Enable access to SVE functionality for all ELs. */
+ cptr_el3 = (cptr_el3 | CPTR_EZ_BIT) & ~(TFP_BIT);
+ write_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3, cptr_el3);
+
+ /* Restrict maximum SVE vector length (SVE_VECTOR_LENGTH+1) * 128. */
+ write_ctx_reg(get_el3state_ctx(context), CTX_ZCR_EL3,
+ (ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(512)));
+}
diff --git a/lib/libc/memset.c b/lib/libc/memset.c
index f9dd4c5..17f798c 100644
--- a/lib/libc/memset.c
+++ b/lib/libc/memset.c
@@ -10,19 +10,20 @@
void *memset(void *dst, int val, size_t count)
{
- char *ptr = dst;
+ uint8_t *ptr = dst;
uint64_t *ptr64;
uint64_t fill = (unsigned char)val;
/* Simplify code below by making sure we write at least one byte. */
- if (count == 0) {
+ if (count == 0U) {
return dst;
}
/* Handle the first part, until the pointer becomes 64-bit aligned. */
- while (((uintptr_t)ptr & 7)) {
- *ptr++ = val;
- if (--count == 0) {
+ while (((uintptr_t)ptr & 7U) != 0U) {
+ *ptr = (uint8_t)val;
+ ptr++;
+ if (--count == 0U) {
return dst;
}
}
@@ -33,15 +34,17 @@
fill |= fill << 32;
/* Use 64-bit writes for as long as possible. */
- ptr64 = (void *)ptr;
- for (; count >= 8; count -= 8) {
- *ptr64++ = fill;
+ ptr64 = (uint64_t *)ptr;
+ for (; count >= 8U; count -= 8) {
+ *ptr64 = fill;
+ ptr64++;
}
/* Handle the remaining part byte-per-byte. */
- ptr = (void *)ptr64;
- while (count--) {
- *ptr++ = val;
+ ptr = (uint8_t *)ptr64;
+ while (count-- > 0U) {
+ *ptr = (uint8_t)val;
+ ptr++;
}
return dst;
diff --git a/lib/zlib/tf_gunzip.c b/lib/zlib/tf_gunzip.c
index fd56dfc..3ac80bc 100644
--- a/lib/zlib/tf_gunzip.c
+++ b/lib/zlib/tf_gunzip.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,6 +9,7 @@
#include <string.h>
#include <common/debug.h>
+#include <common/tf_crc32.h>
#include <lib/utils.h>
#include <tf_gunzip.h>
@@ -100,3 +101,15 @@
return ret;
}
+
+/* Wrapper function to calculate CRC
+ * @crc: previous accumulated CRC
+ * @buf: buffer base address
+ * @size: size of the buffer
+ *
+ * Return calculated CRC32 value
+ */
+uint32_t tf_crc32(uint32_t crc, const unsigned char *buf, size_t size)
+{
+ return (uint32_t)crc32((unsigned long)crc, buf, size);
+}
diff --git a/licenses/LICENSE.MIT b/licenses/LICENSE.MIT
new file mode 100644
index 0000000..8aa2645
--- /dev/null
+++ b/licenses/LICENSE.MIT
@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) [year] [fullname]
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index e94f3c3..72f84b5 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -212,6 +212,9 @@
# True Random Number firmware Interface
TRNG_SUPPORT := 0
+# SMCCC PCI support
+SMC_PCI_SUPPORT := 0
+
# Whether code and read-only data should be put on separate memory pages. The
# platform Makefile is free to override this value.
SEPARATE_CODE_AND_RODATA := 0
@@ -291,17 +294,20 @@
# Include Memory Tagging Extension registers in cpu context. This must be set
# to 1 if the platform wants to use this feature in the Secure world and MTE is
# enabled at ELX.
-CTX_INCLUDE_MTE_REGS := 0
+CTX_INCLUDE_MTE_REGS := 0
ENABLE_AMU := 0
+AMU_RESTRICT_COUNTERS := 0
-# By default, enable Scalable Vector Extension if implemented for Non-secure
+# By default, enable Scalable Vector Extension if implemented only for Non-secure
# lower ELs
# Note SVE is only supported on AArch64 - therefore do not enable in AArch32
ifneq (${ARCH},aarch32)
ENABLE_SVE_FOR_NS := 1
+ ENABLE_SVE_FOR_SWD := 0
else
override ENABLE_SVE_FOR_NS := 0
+ override ENABLE_SVE_FOR_SWD := 0
endif
SANITIZE_UB := off
@@ -338,3 +344,14 @@
# Build option to use the SP804 timer instead of the generic one
USE_SP804_TIMER := 0
+
+# Build option to define number of firmware banks, used in firmware update
+# metadata structure.
+NR_OF_FW_BANKS := 2
+
+# Build option to define number of images in firmware bank, used in firmware
+# update metadata structure.
+NR_OF_IMAGES_IN_FW_BANK := 1
+
+# Disable Firmware update support by default
+PSA_FWU_SUPPORT := 0
diff --git a/make_helpers/tbbr/tbbr_tools.mk b/make_helpers/tbbr/tbbr_tools.mk
index 853ad11..f7cced4 100644
--- a/make_helpers/tbbr/tbbr_tools.mk
+++ b/make_helpers/tbbr/tbbr_tools.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -33,7 +33,7 @@
#
# Certificate generation tool default parameters
-TRUSTED_KEY_CERT := ${BUILD_PLAT}/trusted_key.crt
+TRUSTED_KEY_CERT ?= ${BUILD_PLAT}/trusted_key.crt
FWU_CERT := ${BUILD_PLAT}/fwu_cert.crt
# Default non-volatile counter values (overridable by the platform)
diff --git a/package-lock.json b/package-lock.json
new file mode 100644
index 0000000..61caf57
--- /dev/null
+++ b/package-lock.json
@@ -0,0 +1,2070 @@
+{
+ "requires": true,
+ "lockfileVersion": 1,
+ "dependencies": {
+ "@babel/code-frame": {
+ "version": "7.12.13",
+ "resolved": "https://registry.npmjs.org/@babel/code-frame/-/code-frame-7.12.13.tgz",
+ "integrity": "sha512-HV1Cm0Q3ZrpCR93tkWOYiuYIgLxZXZFVG2VgK+MBWjUqZTundupbfx2aXarXuw5Ko5aMcjtJgbSs4vUGBS5v6g==",
+ "dev": true,
+ "requires": {
+ "@babel/highlight": "^7.12.13"
+ }
+ },
+ "@babel/helper-validator-identifier": {
+ "version": "7.14.0",
+ "resolved": "https://registry.npmjs.org/@babel/helper-validator-identifier/-/helper-validator-identifier-7.14.0.tgz",
+ "integrity": "sha512-V3ts7zMSu5lfiwWDVWzRDGIN+lnCEUdaXgtVHJgLb1rGaA6jMrtB9EmE7L18foXJIE8Un/A/h6NJfGQp/e1J4A==",
+ "dev": true
+ },
+ "@babel/highlight": {
+ "version": "7.14.0",
+ "resolved": "https://registry.npmjs.org/@babel/highlight/-/highlight-7.14.0.tgz",
+ "integrity": "sha512-YSCOwxvTYEIMSGaBQb5kDDsCopDdiUGsqpatp3fOlI4+2HQSkTmEVWnVuySdAC5EWCqSWWTv0ib63RjR7dTBdg==",
+ "dev": true,
+ "requires": {
+ "@babel/helper-validator-identifier": "^7.14.0",
+ "chalk": "^2.0.0",
+ "js-tokens": "^4.0.0"
+ },
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+ "dev": true
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+ "dev": true
+ }
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+}
diff --git a/package.json b/package.json
new file mode 100644
index 0000000..ebd5d55
--- /dev/null
+++ b/package.json
@@ -0,0 +1,13 @@
+{
+ "private": true,
+ "scripts": {
+ "postinstall": "husky install"
+ },
+ "devDependencies": {
+ "@commitlint/cli": "^11.0.0",
+ "@commitlint/config-conventional": "^11.0.0",
+ "commitizen": "^4.2.4",
+ "cz-conventional-changelog": "^3.3.0",
+ "husky": "^5.0.4"
+ }
+}
diff --git a/plat/allwinner/common/allwinner-common.mk b/plat/allwinner/common/allwinner-common.mk
index 901d888..61ae9b6 100644
--- a/plat/allwinner/common/allwinner-common.mk
+++ b/plat/allwinner/common/allwinner-common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -20,8 +20,6 @@
${AW_PLAT}/common/sunxi_common.c
BL31_SOURCES += drivers/allwinner/axp/common.c \
- drivers/allwinner/sunxi_msgbox.c \
- drivers/arm/css/scpi/css_scpi.c \
${GICV2_SOURCES} \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
@@ -29,12 +27,40 @@
plat/common/plat_gicv2.c \
plat/common/plat_psci_common.c \
${AW_PLAT}/common/sunxi_bl31_setup.c \
- ${AW_PLAT}/common/sunxi_cpu_ops.c \
${AW_PLAT}/common/sunxi_pm.c \
${AW_PLAT}/${PLAT}/sunxi_power.c \
${AW_PLAT}/common/sunxi_security.c \
${AW_PLAT}/common/sunxi_topology.c
+# By default, attempt to use SCPI to the ARISC management processor. If SCPI
+# is not enabled or SCP firmware is not loaded, fall back to a simpler native
+# implementation that does not support CPU or system suspend.
+#
+# If SCP firmware will always be present (or absent), the unused implementation
+# can be compiled out.
+SUNXI_PSCI_USE_NATIVE ?= 1
+SUNXI_PSCI_USE_SCPI ?= 1
+
+$(eval $(call assert_boolean,SUNXI_PSCI_USE_NATIVE))
+$(eval $(call assert_boolean,SUNXI_PSCI_USE_SCPI))
+$(eval $(call add_define,SUNXI_PSCI_USE_NATIVE))
+$(eval $(call add_define,SUNXI_PSCI_USE_SCPI))
+
+ifeq (${SUNXI_PSCI_USE_NATIVE}${SUNXI_PSCI_USE_SCPI},00)
+$(error "At least one of SCPI or native PSCI ops must be enabled")
+endif
+
+ifeq (${SUNXI_PSCI_USE_NATIVE},1)
+BL31_SOURCES += ${AW_PLAT}/common/sunxi_cpu_ops.c \
+ ${AW_PLAT}/common/sunxi_native_pm.c
+endif
+
+ifeq (${SUNXI_PSCI_USE_SCPI},1)
+BL31_SOURCES += drivers/allwinner/sunxi_msgbox.c \
+ drivers/arm/css/scpi/css_scpi.c \
+ ${AW_PLAT}/common/sunxi_scpi_pm.c
+endif
+
# The bootloader is guaranteed to only run on CPU 0 by the boot ROM.
COLD_BOOT_SINGLE_CPU := 1
@@ -59,9 +85,6 @@
# Allow mapping read-only data as execute-never.
SEPARATE_CODE_AND_RODATA := 1
-# Put NOBITS memory in SRAM A1, overwriting U-Boot's SPL.
-SEPARATE_NOBITS_REGION := 1
-
# BL31 gets loaded alongside BL33 (U-Boot) by U-Boot's SPL
RESET_TO_BL31 := 1
diff --git a/plat/allwinner/common/include/platform_def.h b/plat/allwinner/common/include/platform_def.h
index 93720ff..49951e0 100644
--- a/plat/allwinner/common/include/platform_def.h
+++ b/plat/allwinner/common/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,20 +13,37 @@
#include <sunxi_mmap.h>
-#define BL31_BASE (SUNXI_SRAM_A2_BASE + 0x4000)
+#ifdef SUNXI_BL31_IN_DRAM
+
+#define BL31_BASE SUNXI_DRAM_BASE
+#define BL31_LIMIT (SUNXI_DRAM_BASE + 0x40000)
+
+#define MAX_XLAT_TABLES 4
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+
+#define SUNXI_BL33_VIRT_BASE PRELOADED_BL33_BASE
+
+#else /* !SUNXI_BL31_IN_DRAM */
+
+#define BL31_BASE (SUNXI_SRAM_A2_BASE + \
+ SUNXI_SRAM_A2_BL31_OFFSET)
#define BL31_LIMIT (SUNXI_SRAM_A2_BASE + \
SUNXI_SRAM_A2_SIZE - SUNXI_SCP_SIZE)
-/* The SCP firmware is allocated the last 16KiB of SRAM A2. */
-#define SUNXI_SCP_BASE BL31_LIMIT
-#define SUNXI_SCP_SIZE 0x4000
-
/* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */
#define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000)
#define BL31_NOBITS_LIMIT (SUNXI_SRAM_A1_BASE + SUNXI_SRAM_A1_SIZE)
-/* How much memory to reserve as secure for BL32, if configured */
-#define SUNXI_DRAM_SEC_SIZE (32U << 20)
+#define MAX_XLAT_TABLES 1
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 28)
+
+#define SUNXI_BL33_VIRT_BASE SUNXI_DRAM_VIRT_BASE
+
+/* The SCP firmware is allocated the last 16KiB of SRAM A2. */
+#define SUNXI_SCP_BASE BL31_LIMIT
+#define SUNXI_SCP_SIZE 0x4000
+
+#endif /* SUNXI_BL31_IN_DRAM */
/* How much DRAM to map (to map BL33, for fetching the DTB from U-Boot) */
#define SUNXI_DRAM_MAP_SIZE (64U << 20)
@@ -34,8 +51,8 @@
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
-#define MAX_MMAP_REGIONS (3 + PLATFORM_MMAP_REGIONS)
-#define MAX_XLAT_TABLES 1
+#define MAX_STATIC_MMAP_REGIONS 3
+#define MAX_MMAP_REGIONS (5 + MAX_STATIC_MMAP_REGIONS)
#define PLAT_CSS_SCP_COM_SHARED_MEM_BASE \
(SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE - 0x200)
@@ -50,13 +67,11 @@
PLATFORM_CORE_COUNT)
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 28)
#define PLATFORM_CLUSTER_COUNT U(1)
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
PLATFORM_MAX_CPUS_PER_CLUSTER)
#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
-#define PLATFORM_MMAP_REGIONS 5
#define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT)
#ifndef SPD_none
diff --git a/plat/allwinner/common/include/sunxi_def.h b/plat/allwinner/common/include/sunxi_def.h
index 73c4453..ec50887 100644
--- a/plat/allwinner/common/include/sunxi_def.h
+++ b/plat/allwinner/common/include/sunxi_def.h
@@ -17,5 +17,7 @@
#define SUNXI_SOC_A64 0x1689
#define SUNXI_SOC_H5 0x1718
#define SUNXI_SOC_H6 0x1728
+#define SUNXI_SOC_H616 0x1823
+#define SUNXI_SOC_R329 0x1851
#endif /* SUNXI_DEF_H */
diff --git a/plat/allwinner/common/include/sunxi_private.h b/plat/allwinner/common/include/sunxi_private.h
index dcf3dc9..6cf4670 100644
--- a/plat/allwinner/common/include/sunxi_private.h
+++ b/plat/allwinner/common/include/sunxi_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,13 +7,32 @@
#ifndef SUNXI_PRIVATE_H
#define SUNXI_PRIVATE_H
+#include <lib/psci/psci.h>
+
void sunxi_configure_mmu_el3(int flags);
void sunxi_cpu_on(u_register_t mpidr);
-void sunxi_cpu_off(u_register_t mpidr);
-void sunxi_disable_secondary_cpus(u_register_t primary_mpidr);
+void sunxi_cpu_power_off_others(void);
+void sunxi_cpu_power_off_self(void);
void sunxi_power_down(void);
+#if SUNXI_PSCI_USE_NATIVE
+void sunxi_set_native_psci_ops(const plat_psci_ops_t **psci_ops);
+#else
+static inline void sunxi_set_native_psci_ops(const plat_psci_ops_t **psci_ops)
+{
+}
+#endif
+#if SUNXI_PSCI_USE_SCPI
+int sunxi_set_scpi_psci_ops(const plat_psci_ops_t **psci_ops);
+#else
+static inline int sunxi_set_scpi_psci_ops(const plat_psci_ops_t **psci_ops)
+{
+ return -1;
+}
+#endif
+int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint);
+
int sunxi_pmic_setup(uint16_t socid, const void *fdt);
void sunxi_security_setup(void);
@@ -22,4 +41,12 @@
int sunxi_init_platform_r_twi(uint16_t socid, bool use_rsb);
void sunxi_execute_arisc_code(uint32_t *code, size_t size, uint16_t param);
+#ifdef SUNXI_BL31_IN_DRAM
+void sunxi_prepare_dtb(void *fdt);
+#else
+static inline void sunxi_prepare_dtb(void *fdt)
+{
+}
+#endif
+
#endif /* SUNXI_PRIVATE_H */
diff --git a/plat/allwinner/common/sunxi_bl31_setup.c b/plat/allwinner/common/sunxi_bl31_setup.c
index b619b18..14049e8 100644
--- a/plat/allwinner/common/sunxi_bl31_setup.c
+++ b/plat/allwinner/common/sunxi_bl31_setup.c
@@ -13,6 +13,8 @@
#include <arch.h>
#include <arch_helpers.h>
#include <common/debug.h>
+#include <common/fdt_fixup.h>
+#include <common/fdt_wrappers.h>
#include <drivers/arm/gicv2.h>
#include <drivers/console.h>
#include <drivers/generic_delay_timer.h>
@@ -52,7 +54,7 @@
uint64_t *u_boot_base;
int i;
- u_boot_base = (void *)(SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE);
+ u_boot_base = (void *)SUNXI_BL33_VIRT_BASE;
for (i = 0; i < 2048 / sizeof(uint64_t); i++) {
uint32_t *dtb_base;
@@ -123,6 +125,12 @@
case SUNXI_SOC_H6:
soc_name = "H6";
break;
+ case SUNXI_SOC_H616:
+ soc_name = "H616";
+ break;
+ case SUNXI_SOC_R329:
+ soc_name = "R329";
+ break;
default:
soc_name = "unknown";
break;
@@ -172,6 +180,8 @@
sunxi_pmic_setup(soc_id, fdt);
+ sunxi_prepare_dtb(fdt);
+
INFO("BL31: Platform setup done\n");
}
diff --git a/plat/allwinner/common/sunxi_common.c b/plat/allwinner/common/sunxi_common.c
index 5b536a0..82410b1 100644
--- a/plat/allwinner/common/sunxi_common.c
+++ b/plat/allwinner/common/sunxi_common.c
@@ -1,36 +1,26 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <errno.h>
-#include <platform_def.h>
-
-#include <arch_helpers.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
-#include <plat/common/platform.h>
#include <sunxi_def.h>
#include <sunxi_mmap.h>
#include <sunxi_private.h>
-static const mmap_region_t sunxi_mmap[PLATFORM_MMAP_REGIONS + 1] = {
+static const mmap_region_t sunxi_mmap[MAX_STATIC_MMAP_REGIONS + 1] = {
MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE,
- MT_RW_DATA | MT_SECURE),
- MAP_REGION_FLAT(SUNXI_SCP_BASE, SUNXI_SCP_SIZE,
MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE,
MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER),
- MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE,
- MT_RW_DATA | MT_SECURE),
- MAP_REGION(PRELOADED_BL33_BASE,
- SUNXI_DRAM_VIRT_BASE + SUNXI_DRAM_SEC_SIZE,
- SUNXI_DRAM_MAP_SIZE,
- MT_RO_DATA | MT_NS),
+ MAP_REGION(PRELOADED_BL33_BASE, SUNXI_BL33_VIRT_BASE,
+ SUNXI_DRAM_MAP_SIZE, MT_RW_DATA | MT_NS),
{},
};
@@ -44,12 +34,24 @@
mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
BL_CODE_END - BL_CODE_BASE,
MT_CODE | MT_SECURE);
+ mmap_add_region(BL_CODE_END, BL_CODE_END,
+ BL_END - BL_CODE_END,
+ MT_RW_DATA | MT_SECURE);
+#if SEPARATE_CODE_AND_RODATA
mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE,
BL_RO_DATA_END - BL_RO_DATA_BASE,
MT_RO_DATA | MT_SECURE);
+#endif
+#if SEPARATE_NOBITS_REGION
+ mmap_add_region(BL_NOBITS_BASE, BL_NOBITS_BASE,
+ BL_NOBITS_END - BL_NOBITS_BASE,
+ MT_RW_DATA | MT_SECURE);
+#endif
+#if USE_COHERENT_MEM
mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER);
+#endif
mmap_add(sunxi_mmap);
init_xlat_tables();
@@ -116,6 +118,7 @@
device_bit = BIT(6);
break;
case SUNXI_SOC_H6:
+ case SUNXI_SOC_H616:
pin_func = use_rsb ? 0x22 : 0x33;
device_bit = BIT(16);
reset_offset = use_rsb ? 0x1bc : 0x19c;
@@ -130,7 +133,7 @@
}
/* un-gate R_PIO clock */
- if (socid != SUNXI_SOC_H6)
+ if (socid != SUNXI_SOC_H6 && socid != SUNXI_SOC_H616)
mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, BIT(0));
/* switch pins PL0 and PL1 to the desired function */
@@ -143,7 +146,7 @@
mmio_clrsetbits_32(SUNXI_R_PIO_BASE + 0x1c, 0x0fU, 0x5U);
/* un-gate clock */
- if (socid != SUNXI_SOC_H6)
+ if (socid != SUNXI_SOC_H6 && socid != SUNXI_SOC_H616)
mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, device_bit);
else
mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, BIT(0));
@@ -154,50 +157,3 @@
return 0;
}
-
-/* This lock synchronises access to the arisc management processor. */
-DEFINE_BAKERY_LOCK(arisc_lock);
-
-/*
- * Tell the "arisc" SCP core (an OpenRISC core) to execute some code.
- * We don't have any service running there, so we place some OpenRISC code
- * in SRAM, put the address of that into the reset vector and release the
- * arisc reset line. The SCP will execute that code and pull the line up again.
- */
-void sunxi_execute_arisc_code(uint32_t *code, size_t size, uint16_t param)
-{
- uintptr_t arisc_reset_vec = SUNXI_SRAM_A2_BASE + 0x100;
-
- do {
- bakery_lock_get(&arisc_lock);
- /* Wait until the arisc is in reset state. */
- if (!(mmio_read_32(SUNXI_R_CPUCFG_BASE) & BIT(0)))
- break;
-
- bakery_lock_release(&arisc_lock);
- } while (1);
-
- /* Patch up the code to feed in an input parameter. */
- code[0] = (code[0] & ~0xffff) | param;
- clean_dcache_range((uintptr_t)code, size);
-
- /*
- * The OpenRISC unconditional branch has opcode 0, the branch offset
- * is in the lower 26 bits, containing the distance to the target,
- * in instruction granularity (32 bits).
- */
- mmio_write_32(arisc_reset_vec, ((uintptr_t)code - arisc_reset_vec) / 4);
- clean_dcache_range(arisc_reset_vec, 4);
-
- /* De-assert the arisc reset line to let it run. */
- mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0));
-
- /*
- * We release the lock here, although the arisc is still busy.
- * But as long as it runs, the reset line is high, so other users
- * won't leave the loop above.
- * Once it has finished, the code is supposed to clear the reset line,
- * to signal this to other users.
- */
- bakery_lock_release(&arisc_lock);
-}
diff --git a/plat/allwinner/common/sunxi_cpu_ops.c b/plat/allwinner/common/sunxi_cpu_ops.c
index 6e29b69..46e7090 100644
--- a/plat/allwinner/common/sunxi_cpu_ops.c
+++ b/plat/allwinner/common/sunxi_cpu_ops.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,7 +15,6 @@
#include <lib/utils_def.h>
#include <plat/common/platform.h>
-#include <core_off_arisc.h>
#include <sunxi_cpucfg.h>
#include <sunxi_mmap.h>
#include <sunxi_private.h>
@@ -43,9 +42,11 @@
mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xe0);
mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x80);
mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x00);
+ udelay(1);
}
-void sunxi_cpu_off(u_register_t mpidr)
+/* We can't turn ourself off like this, but it works for other cores. */
+static void sunxi_cpu_off(u_register_t mpidr)
{
unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr);
unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
@@ -54,31 +55,13 @@
/* Deassert DBGPWRDUP */
mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
-
- /* We can't turn ourself off like this, but it works for other cores. */
- if (read_mpidr() != mpidr) {
- /* Activate the core output clamps, but not for core 0. */
- if (core != 0)
- mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster),
- BIT(core));
- /* Assert CPU power-on reset */
- mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
- /* Remove power from the CPU */
- sunxi_cpu_disable_power(cluster, core);
-
- return;
- }
-
- /* Simplifies assembly, all SoCs so far are single cluster anyway. */
- assert(cluster == 0);
-
- /*
- * If we are supposed to turn ourself off, tell the arisc SCP
- * to do that work for us. The code expects the core mask to be
- * patched into the first instruction.
- */
- sunxi_execute_arisc_code(arisc_core_off, sizeof(arisc_core_off),
- BIT_32(core));
+ /* Activate the core output clamps, but not for core 0. */
+ if (core != 0)
+ mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core));
+ /* Assert CPU power-on reset */
+ mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
+ /* Remove power from the CPU */
+ sunxi_cpu_disable_power(cluster, core);
}
void sunxi_cpu_on(u_register_t mpidr)
@@ -93,7 +76,8 @@
/* Assert CPU power-on reset */
mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
/* Set CPU to start in AArch64 mode */
- mmio_setbits_32(SUNXI_CPUCFG_CLS_CTRL_REG0(cluster), BIT(24 + core));
+ mmio_setbits_32(SUNXI_AA64nAA32_REG(cluster),
+ BIT(SUNXI_AA64nAA32_OFFSET + core));
/* Apply power to the CPU */
sunxi_cpu_enable_power(cluster, core);
/* Release the core output clamps */
@@ -106,8 +90,9 @@
mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
}
-void sunxi_disable_secondary_cpus(u_register_t primary_mpidr)
+void sunxi_cpu_power_off_others(void)
{
+ u_register_t self = read_mpidr();
unsigned int cluster;
unsigned int core;
@@ -116,7 +101,7 @@
u_register_t mpidr = (cluster << MPIDR_AFF1_SHIFT) |
(core << MPIDR_AFF0_SHIFT) |
BIT(31);
- if (mpidr != primary_mpidr)
+ if (mpidr != self)
sunxi_cpu_off(mpidr);
}
}
diff --git a/plat/allwinner/common/sunxi_native_pm.c b/plat/allwinner/common/sunxi_native_pm.c
new file mode 100644
index 0000000..148f50e
--- /dev/null
+++ b/plat/allwinner/common/sunxi_native_pm.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/arm/gicv2.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/psci/psci.h>
+
+#include <sunxi_mmap.h>
+#include <sunxi_private.h>
+
+#define SUNXI_WDOG0_CTRL_REG (SUNXI_R_WDOG_BASE + 0x0010)
+#define SUNXI_WDOG0_CFG_REG (SUNXI_R_WDOG_BASE + 0x0014)
+#define SUNXI_WDOG0_MODE_REG (SUNXI_R_WDOG_BASE + 0x0018)
+
+static int sunxi_pwr_domain_on(u_register_t mpidr)
+{
+ sunxi_cpu_on(mpidr);
+
+ return PSCI_E_SUCCESS;
+}
+
+static void sunxi_pwr_domain_off(const psci_power_state_t *target_state)
+{
+ gicv2_cpuif_disable();
+
+ sunxi_cpu_power_off_self();
+}
+
+static void sunxi_pwr_domain_on_finish(const psci_power_state_t *target_state)
+{
+ gicv2_pcpu_distif_init();
+ gicv2_cpuif_enable();
+}
+
+static void __dead2 sunxi_system_off(void)
+{
+ gicv2_cpuif_disable();
+
+ /* Attempt to power down the board (may not return) */
+ sunxi_power_down();
+
+ /* Turn off all CPUs */
+ sunxi_cpu_power_off_others();
+ sunxi_cpu_power_off_self();
+ psci_power_down_wfi();
+}
+
+static void __dead2 sunxi_system_reset(void)
+{
+ gicv2_cpuif_disable();
+
+ /* Reset the whole system when the watchdog times out */
+ mmio_write_32(SUNXI_WDOG0_CFG_REG, 1);
+ /* Enable the watchdog with the shortest timeout (0.5 seconds) */
+ mmio_write_32(SUNXI_WDOG0_MODE_REG, (0 << 4) | 1);
+ /* Wait for twice the watchdog timeout before panicking */
+ mdelay(1000);
+
+ ERROR("PSCI: System reset failed\n");
+ panic();
+}
+
+static const plat_psci_ops_t sunxi_native_psci_ops = {
+ .pwr_domain_on = sunxi_pwr_domain_on,
+ .pwr_domain_off = sunxi_pwr_domain_off,
+ .pwr_domain_on_finish = sunxi_pwr_domain_on_finish,
+ .system_off = sunxi_system_off,
+ .system_reset = sunxi_system_reset,
+ .validate_ns_entrypoint = sunxi_validate_ns_entrypoint,
+};
+
+void sunxi_set_native_psci_ops(const plat_psci_ops_t **psci_ops)
+{
+ *psci_ops = &sunxi_native_psci_ops;
+}
diff --git a/plat/allwinner/common/sunxi_pm.c b/plat/allwinner/common/sunxi_pm.c
index aa80c52..eb1b7e7 100644
--- a/plat/allwinner/common/sunxi_pm.c
+++ b/plat/allwinner/common/sunxi_pm.c
@@ -8,203 +8,14 @@
#include <platform_def.h>
-#include <arch_helpers.h>
#include <common/debug.h>
-#include <drivers/arm/css/css_scpi.h>
-#include <drivers/arm/gicv2.h>
-#include <drivers/delay_timer.h>
#include <lib/mmio.h>
#include <lib/psci/psci.h>
-#include <plat/common/platform.h>
#include <sunxi_cpucfg.h>
-#include <sunxi_def.h>
-#include <sunxi_mmap.h>
#include <sunxi_private.h>
-#define SUNXI_WDOG0_CTRL_REG (SUNXI_R_WDOG_BASE + 0x0010)
-#define SUNXI_WDOG0_CFG_REG (SUNXI_R_WDOG_BASE + 0x0014)
-#define SUNXI_WDOG0_MODE_REG (SUNXI_R_WDOG_BASE + 0x0018)
-
-#define CPU_PWR_LVL MPIDR_AFFLVL0
-#define CLUSTER_PWR_LVL MPIDR_AFFLVL1
-#define SYSTEM_PWR_LVL MPIDR_AFFLVL2
-
-#define CPU_PWR_STATE(state) \
- ((state)->pwr_domain_state[CPU_PWR_LVL])
-#define CLUSTER_PWR_STATE(state) \
- ((state)->pwr_domain_state[CLUSTER_PWR_LVL])
-#define SYSTEM_PWR_STATE(state) \
- ((state)->pwr_domain_state[SYSTEM_PWR_LVL])
-
-/*
- * The addresses for the SCP exception vectors are defined in the or1k
- * architecture specification.
- */
-#define OR1K_VEC_FIRST 0x01
-#define OR1K_VEC_LAST 0x0e
-#define OR1K_VEC_ADDR(n) (0x100 * (n))
-
-/*
- * This magic value is the little-endian representation of the or1k
- * instruction "l.mfspr r2, r0, 0x12", which is guaranteed to be the
- * first instruction in the SCP firmware.
- */
-#define SCP_FIRMWARE_MAGIC 0xb4400012
-
-static bool scpi_available;
-
-static inline scpi_power_state_t scpi_map_state(plat_local_state_t psci_state)
-{
- if (is_local_state_run(psci_state))
- return scpi_power_on;
- if (is_local_state_retn(psci_state))
- return scpi_power_retention;
- return scpi_power_off;
-}
-
-static void sunxi_cpu_standby(plat_local_state_t cpu_state)
-{
- u_register_t scr = read_scr_el3();
-
- assert(is_local_state_retn(cpu_state));
-
- write_scr_el3(scr | SCR_IRQ_BIT);
- wfi();
- write_scr_el3(scr);
-}
-
-static int sunxi_pwr_domain_on(u_register_t mpidr)
-{
- if (scpi_available) {
- scpi_set_css_power_state(mpidr,
- scpi_power_on,
- scpi_power_on,
- scpi_power_on);
- } else {
- sunxi_cpu_on(mpidr);
- }
-
- return PSCI_E_SUCCESS;
-}
-
-static void sunxi_pwr_domain_off(const psci_power_state_t *target_state)
-{
- plat_local_state_t cpu_pwr_state = CPU_PWR_STATE(target_state);
- plat_local_state_t cluster_pwr_state = CLUSTER_PWR_STATE(target_state);
- plat_local_state_t system_pwr_state = SYSTEM_PWR_STATE(target_state);
-
- if (is_local_state_off(cpu_pwr_state))
- gicv2_cpuif_disable();
-
- if (scpi_available) {
- scpi_set_css_power_state(read_mpidr(),
- scpi_map_state(cpu_pwr_state),
- scpi_map_state(cluster_pwr_state),
- scpi_map_state(system_pwr_state));
- }
-}
-
-static void __dead2 sunxi_pwr_down_wfi(const psci_power_state_t *target_state)
-{
- sunxi_cpu_off(read_mpidr());
-
- while (1)
- wfi();
-}
-
-static void sunxi_pwr_domain_on_finish(const psci_power_state_t *target_state)
-{
- if (is_local_state_off(SYSTEM_PWR_STATE(target_state)))
- gicv2_distif_init();
- if (is_local_state_off(CPU_PWR_STATE(target_state))) {
- gicv2_pcpu_distif_init();
- gicv2_cpuif_enable();
- }
-}
-
-static void __dead2 sunxi_system_off(void)
-{
- gicv2_cpuif_disable();
-
- if (scpi_available) {
- /* Send the power down request to the SCP */
- uint32_t ret = scpi_sys_power_state(scpi_system_shutdown);
-
- if (ret != SCP_OK)
- ERROR("PSCI: SCPI %s failed: %d\n", "shutdown", ret);
- }
-
- /* Turn off all secondary CPUs */
- sunxi_disable_secondary_cpus(read_mpidr());
-
- sunxi_power_down();
-
- udelay(1000);
- ERROR("PSCI: Cannot turn off system, halting\n");
- wfi();
- panic();
-}
-
-static void __dead2 sunxi_system_reset(void)
-{
- gicv2_cpuif_disable();
-
- if (scpi_available) {
- /* Send the system reset request to the SCP */
- uint32_t ret = scpi_sys_power_state(scpi_system_reboot);
-
- if (ret != SCP_OK)
- ERROR("PSCI: SCPI %s failed: %d\n", "reboot", ret);
- }
-
- /* Reset the whole system when the watchdog times out */
- mmio_write_32(SUNXI_WDOG0_CFG_REG, 1);
- /* Enable the watchdog with the shortest timeout (0.5 seconds) */
- mmio_write_32(SUNXI_WDOG0_MODE_REG, (0 << 4) | 1);
- /* Wait for twice the watchdog timeout before panicking */
- mdelay(1000);
-
- ERROR("PSCI: System reset failed\n");
- wfi();
- panic();
-}
-
-static int sunxi_validate_power_state(unsigned int power_state,
- psci_power_state_t *req_state)
-{
- unsigned int power_level = psci_get_pstate_pwrlvl(power_state);
- unsigned int type = psci_get_pstate_type(power_state);
-
- assert(req_state != NULL);
-
- if (power_level > PLAT_MAX_PWR_LVL)
- return PSCI_E_INVALID_PARAMS;
-
- if (type == PSTATE_TYPE_STANDBY) {
- /* Only one retention power state is supported. */
- if (psci_get_pstate_id(power_state) > 0)
- return PSCI_E_INVALID_PARAMS;
- /* The SoC cannot be suspended without losing state */
- if (power_level == SYSTEM_PWR_LVL)
- return PSCI_E_INVALID_PARAMS;
- for (unsigned int i = 0; i <= power_level; ++i)
- req_state->pwr_domain_state[i] = PLAT_MAX_RET_STATE;
- } else {
- /* Only one off power state is supported. */
- if (psci_get_pstate_id(power_state) > 0)
- return PSCI_E_INVALID_PARAMS;
- for (unsigned int i = 0; i <= power_level; ++i)
- req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
- }
- /* Higher power domain levels should all remain running */
- for (unsigned int i = power_level + 1; i <= PLAT_MAX_PWR_LVL; ++i)
- req_state->pwr_domain_state[i] = PSCI_LOCAL_STATE_RUN;
-
- return PSCI_E_SUCCESS;
-}
-
-static int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint)
+int sunxi_validate_ns_entrypoint(uintptr_t ns_entrypoint)
{
/* The non-secure entry point must be in DRAM */
if (ns_entrypoint < SUNXI_DRAM_BASE) {
@@ -214,25 +25,6 @@
return PSCI_E_SUCCESS;
}
-static void sunxi_get_sys_suspend_power_state(psci_power_state_t *req_state)
-{
- assert(req_state);
-
- for (unsigned int i = 0; i <= PLAT_MAX_PWR_LVL; ++i)
- req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
-}
-
-static plat_psci_ops_t sunxi_psci_ops = {
- .cpu_standby = sunxi_cpu_standby,
- .pwr_domain_on = sunxi_pwr_domain_on,
- .pwr_domain_off = sunxi_pwr_domain_off,
- .pwr_domain_on_finish = sunxi_pwr_domain_on_finish,
- .system_off = sunxi_system_off,
- .system_reset = sunxi_system_reset,
- .validate_power_state = sunxi_validate_power_state,
- .validate_ns_entrypoint = sunxi_validate_ns_entrypoint,
-};
-
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
const plat_psci_ops_t **psci_ops)
{
@@ -246,36 +38,12 @@
sec_entrypoint >> 32);
}
- /* Check for a valid SCP firmware, and boot the SCP if found. */
- if (mmio_read_32(SUNXI_SCP_BASE) == SCP_FIRMWARE_MAGIC) {
- /* Program SCP exception vectors to the firmware entrypoint. */
- for (unsigned int i = OR1K_VEC_FIRST; i <= OR1K_VEC_LAST; ++i) {
- uint32_t vector = SUNXI_SRAM_A2_BASE + OR1K_VEC_ADDR(i);
- uint32_t offset = SUNXI_SCP_BASE - vector;
-
- mmio_write_32(vector, offset >> 2);
- clean_dcache_range(vector, sizeof(uint32_t));
- }
- /* Take the SCP out of reset. */
- mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0));
- /* Wait for the SCP firmware to boot. */
- if (scpi_wait_ready() == 0)
- scpi_available = true;
- }
-
- NOTICE("PSCI: System suspend is %s\n",
- scpi_available ? "available via SCPI" : "unavailable");
- if (scpi_available) {
- /* Suspend is only available via SCPI. */
- sunxi_psci_ops.pwr_domain_suspend = sunxi_pwr_domain_off;
- sunxi_psci_ops.pwr_domain_suspend_finish = sunxi_pwr_domain_on_finish;
- sunxi_psci_ops.get_sys_suspend_power_state = sunxi_get_sys_suspend_power_state;
+ if (sunxi_set_scpi_psci_ops(psci_ops) == 0) {
+ INFO("PSCI: Suspend is available via SCPI\n");
} else {
- /* This is only needed when SCPI is unavailable. */
- sunxi_psci_ops.pwr_domain_pwr_down_wfi = sunxi_pwr_down_wfi;
+ INFO("PSCI: Suspend is unavailable\n");
+ sunxi_set_native_psci_ops(psci_ops);
}
- *psci_ops = &sunxi_psci_ops;
-
return 0;
}
diff --git a/plat/allwinner/common/sunxi_scpi_pm.c b/plat/allwinner/common/sunxi_scpi_pm.c
new file mode 100644
index 0000000..eb37daa
--- /dev/null
+++ b/plat/allwinner/common/sunxi_scpi_pm.c
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <platform_def.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/arm/css/css_scpi.h>
+#include <drivers/arm/gicv2.h>
+#include <lib/mmio.h>
+#include <lib/psci/psci.h>
+
+#include <sunxi_mmap.h>
+#include <sunxi_private.h>
+
+/*
+ * The addresses for the SCP exception vectors are defined in the or1k
+ * architecture specification.
+ */
+#define OR1K_VEC_FIRST 0x01
+#define OR1K_VEC_LAST 0x0e
+#define OR1K_VEC_ADDR(n) (0x100 * (n))
+
+/*
+ * This magic value is the little-endian representation of the or1k
+ * instruction "l.mfspr r2, r0, 0x12", which is guaranteed to be the
+ * first instruction in the SCP firmware.
+ */
+#define SCP_FIRMWARE_MAGIC 0xb4400012
+
+#define CPU_PWR_LVL MPIDR_AFFLVL0
+#define CLUSTER_PWR_LVL MPIDR_AFFLVL1
+#define SYSTEM_PWR_LVL MPIDR_AFFLVL2
+
+#define CPU_PWR_STATE(state) \
+ ((state)->pwr_domain_state[CPU_PWR_LVL])
+#define CLUSTER_PWR_STATE(state) \
+ ((state)->pwr_domain_state[CLUSTER_PWR_LVL])
+#define SYSTEM_PWR_STATE(state) \
+ ((state)->pwr_domain_state[SYSTEM_PWR_LVL])
+
+static inline scpi_power_state_t scpi_map_state(plat_local_state_t psci_state)
+{
+ if (is_local_state_run(psci_state)) {
+ return scpi_power_on;
+ }
+ if (is_local_state_retn(psci_state)) {
+ return scpi_power_retention;
+ }
+ return scpi_power_off;
+}
+
+static void sunxi_cpu_standby(plat_local_state_t cpu_state)
+{
+ u_register_t scr = read_scr_el3();
+
+ assert(is_local_state_retn(cpu_state));
+
+ write_scr_el3(scr | SCR_IRQ_BIT);
+ wfi();
+ write_scr_el3(scr);
+}
+
+static int sunxi_pwr_domain_on(u_register_t mpidr)
+{
+ scpi_set_css_power_state(mpidr,
+ scpi_power_on,
+ scpi_power_on,
+ scpi_power_on);
+
+ return PSCI_E_SUCCESS;
+}
+
+static void sunxi_pwr_domain_off(const psci_power_state_t *target_state)
+{
+ plat_local_state_t cpu_pwr_state = CPU_PWR_STATE(target_state);
+ plat_local_state_t cluster_pwr_state = CLUSTER_PWR_STATE(target_state);
+ plat_local_state_t system_pwr_state = SYSTEM_PWR_STATE(target_state);
+
+ if (is_local_state_off(cpu_pwr_state)) {
+ gicv2_cpuif_disable();
+ }
+
+ scpi_set_css_power_state(read_mpidr(),
+ scpi_map_state(cpu_pwr_state),
+ scpi_map_state(cluster_pwr_state),
+ scpi_map_state(system_pwr_state));
+}
+
+static void sunxi_pwr_domain_on_finish(const psci_power_state_t *target_state)
+{
+ if (is_local_state_off(SYSTEM_PWR_STATE(target_state))) {
+ gicv2_distif_init();
+ }
+ if (is_local_state_off(CPU_PWR_STATE(target_state))) {
+ gicv2_pcpu_distif_init();
+ gicv2_cpuif_enable();
+ }
+}
+
+static void __dead2 sunxi_system_off(void)
+{
+ uint32_t ret;
+
+ gicv2_cpuif_disable();
+
+ /* Send the power down request to the SCP. */
+ ret = scpi_sys_power_state(scpi_system_shutdown);
+ if (ret != SCP_OK) {
+ ERROR("PSCI: SCPI %s failed: %d\n", "shutdown", ret);
+ }
+
+ psci_power_down_wfi();
+}
+
+static void __dead2 sunxi_system_reset(void)
+{
+ uint32_t ret;
+
+ gicv2_cpuif_disable();
+
+ /* Send the system reset request to the SCP. */
+ ret = scpi_sys_power_state(scpi_system_reboot);
+ if (ret != SCP_OK) {
+ ERROR("PSCI: SCPI %s failed: %d\n", "reboot", ret);
+ }
+
+ psci_power_down_wfi();
+}
+
+static int sunxi_validate_power_state(unsigned int power_state,
+ psci_power_state_t *req_state)
+{
+ unsigned int power_level = psci_get_pstate_pwrlvl(power_state);
+ unsigned int type = psci_get_pstate_type(power_state);
+
+ assert(req_state != NULL);
+
+ if (power_level > PLAT_MAX_PWR_LVL) {
+ return PSCI_E_INVALID_PARAMS;
+ }
+
+ if (type == PSTATE_TYPE_STANDBY) {
+ /* Only one retention power state is supported. */
+ if (psci_get_pstate_id(power_state) > 0) {
+ return PSCI_E_INVALID_PARAMS;
+ }
+ /* The SoC cannot be suspended without losing state */
+ if (power_level == SYSTEM_PWR_LVL) {
+ return PSCI_E_INVALID_PARAMS;
+ }
+ for (unsigned int i = 0; i <= power_level; ++i) {
+ req_state->pwr_domain_state[i] = PLAT_MAX_RET_STATE;
+ }
+ } else {
+ /* Only one off power state is supported. */
+ if (psci_get_pstate_id(power_state) > 0) {
+ return PSCI_E_INVALID_PARAMS;
+ }
+ for (unsigned int i = 0; i <= power_level; ++i) {
+ req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
+ }
+ }
+ /* Higher power domain levels should all remain running */
+ for (unsigned int i = power_level + 1; i <= PLAT_MAX_PWR_LVL; ++i) {
+ req_state->pwr_domain_state[i] = PSCI_LOCAL_STATE_RUN;
+ }
+
+ return PSCI_E_SUCCESS;
+}
+
+static void sunxi_get_sys_suspend_power_state(psci_power_state_t *req_state)
+{
+ assert(req_state != NULL);
+
+ for (unsigned int i = 0; i <= PLAT_MAX_PWR_LVL; ++i) {
+ req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
+ }
+}
+
+static const plat_psci_ops_t sunxi_scpi_psci_ops = {
+ .cpu_standby = sunxi_cpu_standby,
+ .pwr_domain_on = sunxi_pwr_domain_on,
+ .pwr_domain_off = sunxi_pwr_domain_off,
+ .pwr_domain_suspend = sunxi_pwr_domain_off,
+ .pwr_domain_on_finish = sunxi_pwr_domain_on_finish,
+ .pwr_domain_suspend_finish = sunxi_pwr_domain_on_finish,
+ .system_off = sunxi_system_off,
+ .system_reset = sunxi_system_reset,
+ .validate_power_state = sunxi_validate_power_state,
+ .validate_ns_entrypoint = sunxi_validate_ns_entrypoint,
+ .get_sys_suspend_power_state = sunxi_get_sys_suspend_power_state,
+};
+
+int sunxi_set_scpi_psci_ops(const plat_psci_ops_t **psci_ops)
+{
+ *psci_ops = &sunxi_scpi_psci_ops;
+
+ /* Check for a valid SCP firmware. */
+ if (mmio_read_32(SUNXI_SCP_BASE) != SCP_FIRMWARE_MAGIC) {
+ return -1;
+ }
+
+ /* Program SCP exception vectors to the firmware entrypoint. */
+ for (unsigned int i = OR1K_VEC_FIRST; i <= OR1K_VEC_LAST; ++i) {
+ uint32_t vector = SUNXI_SRAM_A2_BASE + OR1K_VEC_ADDR(i);
+ uint32_t offset = SUNXI_SCP_BASE - vector;
+
+ mmio_write_32(vector, offset >> 2);
+ }
+
+ /* Take the SCP out of reset. */
+ mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0));
+
+ /* Wait for the SCP firmware to boot. */
+ return scpi_wait_ready();
+}
diff --git a/plat/allwinner/sun50i_a64/include/sunxi_cpucfg.h b/plat/allwinner/sun50i_a64/include/sunxi_cpucfg.h
index c3eeadb..aed3585 100644
--- a/plat/allwinner/sun50i_a64/include/sunxi_cpucfg.h
+++ b/plat/allwinner/sun50i_a64/include/sunxi_cpucfg.h
@@ -33,4 +33,7 @@
#define SUNXI_R_CPUCFG_SS_ENTRY_REG (SUNXI_R_CPUCFG_BASE + 0x01a8)
#define SUNXI_R_CPUCFG_HP_FLAG_REG (SUNXI_R_CPUCFG_BASE + 0x01ac)
+#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_CLS_CTRL_REG0
+#define SUNXI_AA64nAA32_OFFSET 24
+
#endif /* SUNXI_CPUCFG_H */
diff --git a/plat/allwinner/sun50i_a64/include/sunxi_mmap.h b/plat/allwinner/sun50i_a64/include/sunxi_mmap.h
index 6c847d3..6d10921 100644
--- a/plat/allwinner/sun50i_a64/include/sunxi_mmap.h
+++ b/plat/allwinner/sun50i_a64/include/sunxi_mmap.h
@@ -15,6 +15,7 @@
#define SUNXI_SRAM_A1_BASE 0x00010000
#define SUNXI_SRAM_A1_SIZE 0x00008000
#define SUNXI_SRAM_A2_BASE 0x00040000
+#define SUNXI_SRAM_A2_BL31_OFFSET 0x00004000
#define SUNXI_SRAM_A2_SIZE 0x00014000
#define SUNXI_SRAM_C_BASE 0x00018000
#define SUNXI_SRAM_C_SIZE 0x0001c000
diff --git a/plat/allwinner/sun50i_a64/platform.mk b/plat/allwinner/sun50i_a64/platform.mk
index f6d5aa9..e3c7c52 100644
--- a/plat/allwinner/sun50i_a64/platform.mk
+++ b/plat/allwinner/sun50i_a64/platform.mk
@@ -9,3 +9,9 @@
BL31_SOURCES += drivers/allwinner/axp/axp803.c \
drivers/allwinner/sunxi_rsb.c
+
+FDT_ASSUME_MASK := "(ASSUME_LATEST | ASSUME_NO_ROLLBACK | ASSUME_LIBFDT_ORDER)"
+$(eval $(call add_define,FDT_ASSUME_MASK))
+
+# Put NOBITS memory in SRAM A1, overwriting U-Boot's SPL.
+SEPARATE_NOBITS_REGION := 1
diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c
index 80a69c3..a35b9dd 100644
--- a/plat/allwinner/sun50i_a64/sunxi_power.c
+++ b/plat/allwinner/sun50i_a64/sunxi_power.c
@@ -14,6 +14,7 @@
#include <drivers/allwinner/sunxi_rsb.h>
#include <lib/mmio.h>
+#include <core_off_arisc.h>
#include <sunxi_def.h>
#include <sunxi_mmap.h>
#include <sunxi_private.h>
@@ -205,3 +206,54 @@
}
}
+
+/* This lock synchronises access to the arisc management processor. */
+static DEFINE_BAKERY_LOCK(arisc_lock);
+
+/*
+ * If we are supposed to turn ourself off, tell the arisc SCP to do that
+ * work for us. Without any SCPI provider running there, we place some
+ * OpenRISC code into SRAM, put the address of that into the reset vector
+ * and release the arisc reset line. The SCP will wait for the core to enter
+ * WFI, then execute that code and pull the line up again.
+ * The code expects the core mask to be patched into the first instruction.
+ */
+void sunxi_cpu_power_off_self(void)
+{
+ u_register_t mpidr = read_mpidr();
+ unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
+ uintptr_t arisc_reset_vec = SUNXI_SRAM_A2_BASE + 0x100;
+ uint32_t *code = arisc_core_off;
+
+ do {
+ bakery_lock_get(&arisc_lock);
+ /* Wait until the arisc is in reset state. */
+ if (!(mmio_read_32(SUNXI_R_CPUCFG_BASE) & BIT(0)))
+ break;
+
+ bakery_lock_release(&arisc_lock);
+ } while (1);
+
+ /* Patch up the code to feed in an input parameter. */
+ code[0] = (code[0] & ~0xffff) | BIT_32(core);
+ clean_dcache_range((uintptr_t)code, sizeof(arisc_core_off));
+
+ /*
+ * The OpenRISC unconditional branch has opcode 0, the branch offset
+ * is in the lower 26 bits, containing the distance to the target,
+ * in instruction granularity (32 bits).
+ */
+ mmio_write_32(arisc_reset_vec, ((uintptr_t)code - arisc_reset_vec) / 4);
+
+ /* De-assert the arisc reset line to let it run. */
+ mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0));
+
+ /*
+ * We release the lock here, although the arisc is still busy.
+ * But as long as it runs, the reset line is high, so other users
+ * won't leave the loop above.
+ * Once it has finished, the code is supposed to clear the reset line,
+ * to signal this to other users.
+ */
+ bakery_lock_release(&arisc_lock);
+}
diff --git a/plat/allwinner/sun50i_h6/include/core_off_arisc.h b/plat/allwinner/sun50i_h6/include/core_off_arisc.h
deleted file mode 100644
index 63a5d8d..0000000
--- a/plat/allwinner/sun50i_h6/include/core_off_arisc.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-static uint32_t arisc_core_off[] = {
- 0x18600000, /* l.movhi r3, <corenr> */
- 0x18000000, /* l.movhi r0, 0x0 */
- 0x19a00901, /* l.movhi r13, 0x901 */
- 0x84ad0080, /* l.lwz r5, 0x80(r13) */
- 0xe0a51803, /* l.and r5, r5, r3 */
- 0xe4050000, /* l.sfeq r5, r0 */
- 0x13fffffd, /* l.bf -12 */
- 0xb8c30050, /* l.srli r6, r3, 16 */
-
- 0xbc060001, /* l.sfeqi r6, 1 */
- 0x10000005, /* l.bf +20 */
- 0x19a00700, /* l.movhi r13, 0x700 */
- 0x84ad0444, /* l.lwz r5, 0x0444(r13) */
- 0xe0a53004, /* l.or r5, r5, r6 */
- 0xd40d2c44, /* l.sw 0x0444(r13), r5 */
-
- 0x84ad0440, /* l.lwz r5, 0x0440(r13) */
- 0xacc6ffff, /* l.xori r6, r6, -1 */
- 0xe0a53003, /* l.and r5, r5, r6 */
- 0xd40d2c40, /* l.sw 0x0440(r13), r5 */
-
- 0xe0c3000f, /* l.ff1 r6, r3 */
- 0x9cc6ffef, /* l.addi r6, r6, -17 */
- 0xb8c60002, /* l.slli r6, r6, 2 */
- 0xe0c66800, /* l.add r6, r6, r13 */
- 0xa8a000ff, /* l.ori r5, r0, 0xff */
- 0xd4062c50, /* l.sw 0x0450(r6), r5 */
-
- 0xd40d0400, /* l.sw 0x0400(r13), r0 */
- 0x03ffffff, /* l.j -1 */
- 0x15000000, /* l.nop */
-};
diff --git a/plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h b/plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h
index 556fb97..5bfda5d 100644
--- a/plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h
+++ b/plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,4 +24,12 @@
#define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \
(c) * 0x10 + (n) * 4)
+#define SUNXI_CPUIDLE_EN_REG (SUNXI_R_CPUCFG_BASE + 0x0100)
+#define SUNXI_CORE_CLOSE_REG (SUNXI_R_CPUCFG_BASE + 0x0104)
+#define SUNXI_PWR_SW_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0140)
+#define SUNXI_CONFIG_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0144)
+
+#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_CLS_CTRL_REG0
+#define SUNXI_AA64nAA32_OFFSET 24
+
#endif /* SUNXI_CPUCFG_H */
diff --git a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
index 2d7b098..58216d8 100644
--- a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
+++ b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h
@@ -15,6 +15,7 @@
#define SUNXI_SRAM_A1_BASE 0x00020000
#define SUNXI_SRAM_A1_SIZE 0x00008000
#define SUNXI_SRAM_A2_BASE 0x00100000
+#define SUNXI_SRAM_A2_BL31_OFFSET 0x00004000
#define SUNXI_SRAM_A2_SIZE 0x00018000
#define SUNXI_SRAM_C_BASE 0x00028000
#define SUNXI_SRAM_C_SIZE 0x0001e000
diff --git a/plat/allwinner/sun50i_h6/platform.mk b/plat/allwinner/sun50i_h6/platform.mk
index 1c98919..e13e8cb 100644
--- a/plat/allwinner/sun50i_h6/platform.mk
+++ b/plat/allwinner/sun50i_h6/platform.mk
@@ -9,3 +9,6 @@
BL31_SOURCES += drivers/allwinner/axp/axp805.c \
drivers/allwinner/sunxi_rsb.c
+
+# Put NOBITS memory in SRAM A1, overwriting U-Boot's SPL.
+SEPARATE_NOBITS_REGION := 1
diff --git a/plat/allwinner/sun50i_h6/sunxi_power.c b/plat/allwinner/sun50i_h6/sunxi_power.c
index a7865a5..d298e6b 100644
--- a/plat/allwinner/sun50i_h6/sunxi_power.c
+++ b/plat/allwinner/sun50i_h6/sunxi_power.c
@@ -10,7 +10,9 @@
#include <common/debug.h>
#include <drivers/allwinner/axp.h>
#include <drivers/allwinner/sunxi_rsb.h>
+#include <lib/mmio.h>
+#include <sunxi_cpucfg.h>
#include <sunxi_def.h>
#include <sunxi_mmap.h>
#include <sunxi_private.h>
@@ -102,3 +104,16 @@
break;
}
}
+
+void sunxi_cpu_power_off_self(void)
+{
+ u_register_t mpidr = read_mpidr();
+ unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
+
+ /* Enable the CPUIDLE hardware (only really needs to be done once). */
+ mmio_write_32(SUNXI_CPUIDLE_EN_REG, 0x16aa0000);
+ mmio_write_32(SUNXI_CPUIDLE_EN_REG, 0xaa160001);
+
+ /* Trigger power off for this core. */
+ mmio_write_32(SUNXI_CORE_CLOSE_REG, BIT_32(core));
+}
diff --git a/plat/allwinner/sun50i_h616/include/sunxi_ccu.h b/plat/allwinner/sun50i_h616/include/sunxi_ccu.h
new file mode 100644
index 0000000..85fbb90
--- /dev/null
+++ b/plat/allwinner/sun50i_h616/include/sunxi_ccu.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SUNXI_CCU_H
+#define SUNXI_CCU_H
+
+#define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0x0f00)
+
+#define SUNXI_R_PRCM_SEC_SWITCH_REG (SUNXI_R_PRCM_BASE + 0x0290)
+
+#endif /* SUNXI_CCU_H */
diff --git a/plat/allwinner/sun50i_h616/include/sunxi_cpucfg.h b/plat/allwinner/sun50i_h616/include/sunxi_cpucfg.h
new file mode 100644
index 0000000..dab663b
--- /dev/null
+++ b/plat/allwinner/sun50i_h616/include/sunxi_cpucfg.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2017-2020, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SUNXI_CPUCFG_H
+#define SUNXI_CPUCFG_H
+
+#include <sunxi_mmap.h>
+
+/* c = cluster, n = core */
+#define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0010 + (c) * 0x10)
+#define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_CPUCFG_BASE + 0x0014 + (c) * 0x10)
+#define SUNXI_CPUCFG_CACHE_CFG_REG (SUNXI_CPUCFG_BASE + 0x0024)
+#define SUNXI_CPUCFG_DBG_REG0 (SUNXI_CPUCFG_BASE + 0x00c0)
+
+#define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_CPUCFG_BASE + 0x0000 + (c) * 4)
+#define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8)
+#define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8)
+
+#define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4)
+#define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4)
+#define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \
+ (c) * 0x10 + (n) * 4)
+
+#define SUNXI_CPUIDLE_EN_REG (SUNXI_R_CPUCFG_BASE + 0x0100)
+#define SUNXI_CORE_CLOSE_REG (SUNXI_R_CPUCFG_BASE + 0x0104)
+#define SUNXI_PWR_SW_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0140)
+#define SUNXI_CONFIG_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0144)
+
+#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_CLS_CTRL_REG0
+#define SUNXI_AA64nAA32_OFFSET 24
+
+#endif /* SUNXI_CPUCFG_H */
diff --git a/plat/allwinner/sun50i_h616/include/sunxi_mmap.h b/plat/allwinner/sun50i_h616/include/sunxi_mmap.h
new file mode 100644
index 0000000..3b4f4a0
--- /dev/null
+++ b/plat/allwinner/sun50i_h616/include/sunxi_mmap.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SUNXI_MMAP_H
+#define SUNXI_MMAP_H
+
+/* Memory regions */
+#define SUNXI_ROM_BASE 0x00000000
+#define SUNXI_ROM_SIZE 0x00010000
+#define SUNXI_SRAM_BASE 0x00020000
+#define SUNXI_SRAM_SIZE 0x00038000
+#define SUNXI_SRAM_A1_BASE 0x00020000
+#define SUNXI_SRAM_A1_SIZE 0x00008000
+#define SUNXI_SRAM_C_BASE 0x00028000
+#define SUNXI_SRAM_C_SIZE 0x00030000
+#define SUNXI_DEV_BASE 0x01000000
+#define SUNXI_DEV_SIZE 0x09000000
+#define SUNXI_DRAM_BASE 0x40000000
+#define SUNXI_DRAM_VIRT_BASE SUNXI_DRAM_BASE
+
+/* Memory-mapped devices */
+#define SUNXI_SYSCON_BASE 0x03000000
+#define SUNXI_CCU_BASE 0x03001000
+#define SUNXI_DMA_BASE 0x03002000
+#define SUNXI_SID_BASE 0x03006000
+#define SUNXI_SPC_BASE 0x03008000
+#define SUNXI_WDOG_BASE 0x030090a0
+#define SUNXI_PIO_BASE 0x0300b000
+#define SUNXI_GICD_BASE 0x03021000
+#define SUNXI_GICC_BASE 0x03022000
+#define SUNXI_UART0_BASE 0x05000000
+#define SUNXI_SPI0_BASE 0x05010000
+#define SUNXI_R_CPUCFG_BASE 0x07000400
+#define SUNXI_R_PRCM_BASE 0x07010000
+//#define SUNXI_R_WDOG_BASE 0x07020400
+#define SUNXI_R_WDOG_BASE SUNXI_WDOG_BASE
+#define SUNXI_R_PIO_BASE 0x07022000
+#define SUNXI_R_UART_BASE 0x07080000
+#define SUNXI_R_I2C_BASE 0x07081400
+#define SUNXI_R_RSB_BASE 0x07083000
+#define SUNXI_CPUCFG_BASE 0x09010000
+
+#endif /* SUNXI_MMAP_H */
diff --git a/plat/allwinner/sun50i_h616/include/sunxi_spc.h b/plat/allwinner/sun50i_h616/include/sunxi_spc.h
new file mode 100644
index 0000000..0f5965b
--- /dev/null
+++ b/plat/allwinner/sun50i_h616/include/sunxi_spc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SUNXI_SPC_H
+#define SUNXI_SPC_H
+
+#define SUNXI_SPC_NUM_PORTS 14
+
+#define SUNXI_SPC_DECPORT_STA_REG(p) (SUNXI_SPC_BASE + 0x0000 + 0x10 * (p))
+#define SUNXI_SPC_DECPORT_SET_REG(p) (SUNXI_SPC_BASE + 0x0004 + 0x10 * (p))
+#define SUNXI_SPC_DECPORT_CLR_REG(p) (SUNXI_SPC_BASE + 0x0008 + 0x10 * (p))
+
+#endif /* SUNXI_SPC_H */
diff --git a/plat/allwinner/sun50i_h616/platform.mk b/plat/allwinner/sun50i_h616/platform.mk
new file mode 100644
index 0000000..fc09af7
--- /dev/null
+++ b/plat/allwinner/sun50i_h616/platform.mk
@@ -0,0 +1,24 @@
+#
+# Copyright (c) 2017-2020, ARM Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Without a management processor there is no SCPI support.
+SUNXI_PSCI_USE_SCPI := 0
+SUNXI_PSCI_USE_NATIVE := 1
+
+# The differences between the platforms are covered by the include files.
+include plat/allwinner/common/allwinner-common.mk
+
+# the above could be overwritten on the command line
+ifeq (${SUNXI_PSCI_USE_SCPI}, 1)
+ $(error "H616 does not support SCPI PSCI ops")
+endif
+
+BL31_SOURCES += drivers/allwinner/axp/axp805.c \
+ drivers/allwinner/sunxi_rsb.c \
+ common/fdt_fixup.c \
+ ${AW_PLAT}/${PLAT}/prepare_dtb.c
+
+$(eval $(call add_define,SUNXI_BL31_IN_DRAM))
diff --git a/plat/allwinner/sun50i_h616/prepare_dtb.c b/plat/allwinner/sun50i_h616/prepare_dtb.c
new file mode 100644
index 0000000..e94b0b4
--- /dev/null
+++ b/plat/allwinner/sun50i_h616/prepare_dtb.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2021, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <libfdt.h>
+
+#include <common/debug.h>
+#include <common/fdt_fixup.h>
+#include <common/fdt_wrappers.h>
+
+#include <sunxi_private.h>
+
+void sunxi_prepare_dtb(void *fdt)
+{
+ int ret;
+
+ if (fdt == NULL || fdt_check_header(fdt) != 0) {
+ return;
+ }
+ ret = fdt_open_into(fdt, fdt, 0x100000);
+ if (ret < 0) {
+ ERROR("Preparing devicetree at %p: error %d\n", fdt, ret);
+ return;
+ }
+
+ /* Reserve memory used by Trusted Firmware. */
+ if (fdt_add_reserved_memory(fdt, "tf-a@40000000", BL31_BASE,
+ BL31_LIMIT - BL31_BASE)) {
+ WARN("Failed to add reserved memory nodes to DT.\n");
+ return;
+ }
+
+ ret = fdt_pack(fdt);
+ if (ret < 0) {
+ ERROR("Failed to pack devicetree at %p: error %d\n",
+ fdt, ret);
+ } else {
+ clean_dcache_range((uintptr_t)fdt, fdt_blob_size(fdt));
+ INFO("Changed devicetree to reserve BL31 memory.\n");
+ }
+}
diff --git a/plat/allwinner/sun50i_h616/sunxi_power.c b/plat/allwinner/sun50i_h616/sunxi_power.c
new file mode 100644
index 0000000..dd6ebba
--- /dev/null
+++ b/plat/allwinner/sun50i_h616/sunxi_power.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2017-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2018, Icenowy Zheng <icenowy@aosc.io>
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+#include <string.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/allwinner/axp.h>
+#include <drivers/allwinner/sunxi_rsb.h>
+#include <lib/mmio.h>
+
+#include <sunxi_cpucfg.h>
+#include <sunxi_def.h>
+#include <sunxi_mmap.h>
+#include <sunxi_private.h>
+
+#define AXP305_I2C_ADDR 0x36
+#define AXP305_HW_ADDR 0x745
+#define AXP305_RT_ADDR 0x3a
+
+static enum pmic_type {
+ UNKNOWN,
+ AXP305,
+} pmic;
+
+int axp_read(uint8_t reg)
+{
+ return rsb_read(AXP305_RT_ADDR, reg);
+}
+
+int axp_write(uint8_t reg, uint8_t val)
+{
+ return rsb_write(AXP305_RT_ADDR, reg, val);
+}
+
+static int rsb_init(void)
+{
+ int ret;
+
+ ret = rsb_init_controller();
+ if (ret)
+ return ret;
+
+ /* Switch to the recommended 3 MHz bus clock. */
+ ret = rsb_set_bus_speed(SUNXI_OSC24M_CLK_IN_HZ, 3000000);
+ if (ret)
+ return ret;
+
+ /* Initiate an I2C transaction to switch the PMIC to RSB mode. */
+ ret = rsb_set_device_mode(AXP20X_MODE_RSB << 16 | AXP20X_MODE_REG << 8);
+ if (ret)
+ return ret;
+
+ /* Associate the 8-bit runtime address with the 12-bit bus address. */
+ ret = rsb_assign_runtime_address(AXP305_HW_ADDR, AXP305_RT_ADDR);
+ if (ret)
+ return ret;
+
+ return axp_check_id();
+}
+
+int sunxi_pmic_setup(uint16_t socid, const void *fdt)
+{
+ int ret;
+
+ INFO("PMIC: Probing AXP305 on RSB\n");
+
+ ret = sunxi_init_platform_r_twi(socid, true);
+ if (ret) {
+ INFO("Could not init platform bus: %d\n", ret);
+ return ret;
+ }
+
+ ret = rsb_init();
+ if (ret) {
+ INFO("Could not init RSB: %d\n", ret);
+ return ret;
+ }
+
+ pmic = AXP305;
+ axp_setup_regulators(fdt);
+
+ /* Switch the PMIC back to I2C mode. */
+ ret = axp_write(AXP20X_MODE_REG, AXP20X_MODE_I2C);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+void sunxi_power_down(void)
+{
+ switch (pmic) {
+ case AXP305:
+ /* Re-initialise after rich OS might have used it. */
+ sunxi_init_platform_r_twi(SUNXI_SOC_H616, true);
+ rsb_init();
+ axp_power_off();
+ break;
+ default:
+ break;
+ }
+}
+
+void sunxi_cpu_power_off_self(void)
+{
+ u_register_t mpidr = read_mpidr();
+ unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
+
+ /* Enable the CPUIDLE hardware (only really needs to be done once). */
+ mmio_write_32(SUNXI_CPUIDLE_EN_REG, 0x16aa0000);
+ mmio_write_32(SUNXI_CPUIDLE_EN_REG, 0xaa160001);
+
+ /* Trigger power off for this core. */
+ mmio_write_32(SUNXI_CORE_CLOSE_REG, BIT_32(core));
+}
diff --git a/plat/allwinner/sun50i_r329/include/sunxi_ccu.h b/plat/allwinner/sun50i_r329/include/sunxi_ccu.h
new file mode 100644
index 0000000..0e6b543
--- /dev/null
+++ b/plat/allwinner/sun50i_r329/include/sunxi_ccu.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2021 Sipeed
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SUNXI_CCU_H
+#define SUNXI_CCU_H
+
+#define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0x0f00)
+
+#define SUNXI_R_PRCM_SEC_SWITCH_REG (SUNXI_R_PRCM_BASE + 0x0290)
+
+#endif /* SUNXI_CCU_H */
diff --git a/plat/allwinner/sun50i_r329/include/sunxi_cpucfg.h b/plat/allwinner/sun50i_r329/include/sunxi_cpucfg.h
new file mode 100644
index 0000000..9478f32
--- /dev/null
+++ b/plat/allwinner/sun50i_r329/include/sunxi_cpucfg.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2021 Sipeed
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SUNXI_CPUCFG_H
+#define SUNXI_CPUCFG_H
+
+#include <sunxi_mmap.h>
+
+/* c = cluster, n = core */
+#define SUNXI_CPUCFG_CLS_CTRL_REG0(c) (SUNXI_C0_CPUXCFG_BASE + 0x0010)
+#define SUNXI_CPUCFG_CLS_CTRL_REG1(c) (SUNXI_C0_CPUXCFG_BASE + 0x0014)
+#define SUNXI_CPUCFG_CACHE_CFG_REG (SUNXI_C0_CPUXCFG_BASE + 0x0024)
+#define SUNXI_CPUCFG_DBG_REG0 (SUNXI_C0_CPUXCFG_BASE + 0x00c0)
+
+#define SUNXI_CPUCFG_RST_CTRL_REG(c) (SUNXI_C0_CPUXCFG_BASE + 0x0000)
+#define SUNXI_CPUCFG_GEN_CTRL_REG0(c) (SUNXI_CPUCFG_BASE + 0x0000)
+#define SUNXI_CPUCFG_RVBAR_LO_REG(n) (SUNXI_CPUCFG_BASE + 0x0040 + (n) * 8)
+#define SUNXI_CPUCFG_RVBAR_HI_REG(n) (SUNXI_CPUCFG_BASE + 0x0044 + (n) * 8)
+
+#define SUNXI_POWERON_RST_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0040 + (c) * 4)
+#define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_CPUCFG_BASE + 0x0044 + (c) * 4)
+#define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_CPUCFG_BASE + 0x0050 + \
+ (c) * 0x10 + (n) * 4)
+
+#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_GEN_CTRL_REG0
+#define SUNXI_AA64nAA32_OFFSET 4
+
+#endif /* SUNXI_CPUCFG_H */
diff --git a/plat/allwinner/sun50i_r329/include/sunxi_mmap.h b/plat/allwinner/sun50i_r329/include/sunxi_mmap.h
new file mode 100644
index 0000000..a4469b5
--- /dev/null
+++ b/plat/allwinner/sun50i_r329/include/sunxi_mmap.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SUNXI_MMAP_H
+#define SUNXI_MMAP_H
+
+/* Memory regions */
+#define SUNXI_ROM_BASE 0x00000000
+#define SUNXI_ROM_SIZE 0x00010000
+/*
+ * In fact all SRAM from 0x100000 is SRAM A2. However as it's too big for
+ * firmware, and the user manual gives a tip on a 2*64K/27*64K partition,
+ * only use the first 2*64K for firmwares now, with the SPL using the first
+ * 64K and BL3-1 using the second one.
+ *
+ * Only the used 2*64K SRAM is defined here, to prevent a gaint translation
+ * table to be generated.
+ */
+#define SUNXI_SRAM_BASE 0x00100000
+#define SUNXI_SRAM_SIZE 0x00020000
+#define SUNXI_SRAM_A1_BASE 0x00100000
+#define SUNXI_SRAM_A1_SIZE 0x00010000
+#define SUNXI_SRAM_A2_BASE 0x00110000
+#define SUNXI_SRAM_A2_BL31_OFFSET 0x00000000
+#define SUNXI_SRAM_A2_SIZE 0x00010000
+#define SUNXI_DEV_BASE 0x01000000
+#define SUNXI_DEV_SIZE 0x09000000
+#define SUNXI_DRAM_BASE 0x40000000
+#define SUNXI_DRAM_VIRT_BASE 0x0a000000
+
+/* Memory-mapped devices */
+#define SUNXI_WDOG_BASE 0x020000a0
+#define SUNXI_R_WDOG_BASE SUNXI_WDOG_BASE
+#define SUNXI_PIO_BASE 0x02000400
+#define SUNXI_SPC_BASE 0x02000800
+#define SUNXI_CCU_BASE 0x02001000
+#define SUNXI_UART0_BASE 0x02500000
+#define SUNXI_SYSCON_BASE 0x03000000
+#define SUNXI_DMA_BASE 0x03002000
+#define SUNXI_SID_BASE 0x03006000
+#define SUNXI_GICD_BASE 0x03021000
+#define SUNXI_GICC_BASE 0x03022000
+#define SUNXI_SPI0_BASE 0x04025000
+#define SUNXI_R_CPUCFG_BASE 0x07000400
+#define SUNXI_R_PRCM_BASE 0x07010000
+#define SUNXI_R_PIO_BASE 0x07022000
+#define SUNXI_R_UART_BASE 0x07080000
+#define SUNXI_R_I2C_BASE 0x07081400
+#define SUNXI_CPUCFG_BASE 0x08100000
+#define SUNXI_C0_CPUXCFG_BASE 0x09010000
+
+#endif /* SUNXI_MMAP_H */
diff --git a/plat/allwinner/sun50i_r329/include/sunxi_spc.h b/plat/allwinner/sun50i_r329/include/sunxi_spc.h
new file mode 100644
index 0000000..2c87bca
--- /dev/null
+++ b/plat/allwinner/sun50i_r329/include/sunxi_spc.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2021 Sipeed
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SUNXI_SPC_H
+#define SUNXI_SPC_H
+
+/* Get by REing stock ATF and checking initialization loop boundary */
+#define SUNXI_SPC_NUM_PORTS 11
+
+#define SUNXI_SPC_DECPORT_STA_REG(p) (SUNXI_SPC_BASE + 0x0000 + 0x10 * (p))
+#define SUNXI_SPC_DECPORT_SET_REG(p) (SUNXI_SPC_BASE + 0x0004 + 0x10 * (p))
+#define SUNXI_SPC_DECPORT_CLR_REG(p) (SUNXI_SPC_BASE + 0x0008 + 0x10 * (p))
+
+#endif /* SUNXI_SPC_H */
diff --git a/plat/allwinner/sun50i_r329/platform.mk b/plat/allwinner/sun50i_r329/platform.mk
new file mode 100644
index 0000000..05d7cde
--- /dev/null
+++ b/plat/allwinner/sun50i_r329/platform.mk
@@ -0,0 +1,20 @@
+#
+# Copyright (c) 2021 Sipeed
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Without a management processor there is no SCPI support.
+SUNXI_PSCI_USE_SCPI := 0
+SUNXI_PSCI_USE_NATIVE := 1
+
+# The differences between the platforms are covered by the include files.
+include plat/allwinner/common/allwinner-common.mk
+
+# the above could be overwritten on the command line
+ifeq (${SUNXI_PSCI_USE_SCPI}, 1)
+ $(error "R329 does not support SCPI PSCI ops")
+endif
+
+# Put NOBITS memory in the first 64K of SRAM A2, overwriting U-Boot's SPL.
+SEPARATE_NOBITS_REGION := 1
diff --git a/plat/allwinner/sun50i_r329/sunxi_power.c b/plat/allwinner/sun50i_r329/sunxi_power.c
new file mode 100644
index 0000000..96a24d5
--- /dev/null
+++ b/plat/allwinner/sun50i_r329/sunxi_power.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2021 Sipeed
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform_def.h>
+
+#include <sunxi_mmap.h>
+#include <sunxi_cpucfg.h>
+#include <sunxi_private.h>
+
+int sunxi_pmic_setup(uint16_t socid, const void *fdt)
+{
+ /* Currently known hardware has no PMIC */
+
+ return 0;
+}
+
+void sunxi_power_down(void)
+{
+}
+
+void sunxi_cpu_power_off_self(void)
+{
+ /* TODO: It's still unknown whether CPUIDLE exists on R329 */
+}
diff --git a/plat/arm/board/a5ds/include/platform_def.h b/plat/arm/board/a5ds/include/platform_def.h
index 792a754..9f3df1e 100644
--- a/plat/arm/board/a5ds/include/platform_def.h
+++ b/plat/arm/board/a5ds/include/platform_def.h
@@ -315,8 +315,8 @@
#define MAX_IO_HANDLES 4
/* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FIP_BASE BOOT_BASE
-#define PLAT_ARM_FIP_MAX_SIZE (BOOT_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_FLASH_IMAGE_BASE BOOT_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (BOOT_SIZE - V2M_FLASH_BLOCK_SIZE)
#define PLAT_ARM_NVM_BASE BOOT_BASE
#define PLAT_ARM_NVM_SIZE (BOOT_SIZE - V2M_FLASH_BLOCK_SIZE)
diff --git a/plat/arm/board/arm_fpga/platform.mk b/plat/arm/board/arm_fpga/platform.mk
index 3ac1c01..f80ea2f 100644
--- a/plat/arm/board/arm_fpga/platform.mk
+++ b/plat/arm/board/arm_fpga/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2020, Arm Limited. All rights reserved.
+# Copyright (c) 2021, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -32,6 +32,8 @@
FPGA_PRELOADED_CMD_LINE := 0x1000
$(eval $(call add_define,FPGA_PRELOADED_CMD_LINE))
+ENABLE_AMU := 1
+
# Treating this as a memory-constrained port for now
USE_COHERENT_MEM := 0
@@ -67,8 +69,11 @@
lib/cpus/aarch64/cortex_a78_ae.S \
lib/cpus/aarch64/cortex_a65.S \
lib/cpus/aarch64/cortex_a65ae.S \
- lib/cpus/aarch64/cortex_klein.S \
- lib/cpus/aarch64/cortex_matterhorn.S
+ lib/cpus/aarch64/cortex_a510.S \
+ lib/cpus/aarch64/cortex_a710.S \
+ lib/cpus/aarch64/cortex_makalu.S \
+ lib/cpus/aarch64/cortex_makalu_elp_arm.S \
+ lib/cpus/aarch64/cortex_a78c.S
# AArch64/AArch32 cores
FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
diff --git a/plat/arm/board/common/board_common.mk b/plat/arm/board/common/board_common.mk
index 6db0c00..5cdf1bf 100644
--- a/plat/arm/board/common/board_common.mk
+++ b/plat/arm/board/common/board_common.mk
@@ -33,7 +33,7 @@
$(warning Development keys support for FVP is deprecated. Use `regs` \
option instead)
else
- $(error "Unsupported ARM_ROTPK_LOCATION value")
+$(error "Unsupported ARM_ROTPK_LOCATION value")
endif
$(eval $(call add_define,ARM_ROTPK_LOCATION_ID))
diff --git a/plat/arm/board/common/rotpk/arm_dev_rotpk.S b/plat/arm/board/common/rotpk/arm_dev_rotpk.S
index 80f2192..38f91fe 100644
--- a/plat/arm/board/common/rotpk/arm_dev_rotpk.S
+++ b/plat/arm/board/common/rotpk/arm_dev_rotpk.S
@@ -1,10 +1,17 @@
/*
- * Copyright (c) 2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2021, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+/* diphda platform provides custom values for the macros defined in
+ * arm_def.h , so only platform_def.h needs to be included
+ */
+#if !defined(TARGET_PLATFORM_FVP) && !defined(TARGET_PLATFORM_FPGA)
#include "plat/arm/common/arm_def.h"
+#else
+#include <platform_def.h>
+#endif
.global arm_rotpk_header
.global arm_rotpk_header_end
diff --git a/plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c b/plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c
new file mode 100644
index 0000000..916c868
--- /dev/null
+++ b/plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/desc_image_load.h>
+
+#include <platform_def.h>
+
+/*******************************************************************************
+ * Following descriptor provides BL image/ep information that gets used
+ * by BL2 to load the images and also subset of this information is
+ * passed to next BL image. The image loading sequence is managed by
+ * populating the images in required loading order. The image execution
+ * sequence is managed by populating the `next_handoff_image_id` with
+ * the next executable image id.
+ ******************************************************************************/
+static bl_mem_params_node_t bl2_mem_params_descs[] = {
+
+ /* Fill BL31 related information */
+ {
+ .image_id = BL31_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t,
+ SECURE | EXECUTABLE | EP_FIRST_EXE),
+ .ep_info.pc = BL31_BASE,
+ .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+ DISABLE_ALL_EXCEPTIONS),
+ .ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL,
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
+ .image_info.image_base = BL31_BASE,
+ .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
+
+ .next_handoff_image_id = BL32_IMAGE_ID,
+ },
+
+ /* Fill BL32 related information */
+ {
+ .image_id = BL32_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
+ .ep_info.pc = BL32_BASE,
+ .ep_info.args.arg0 = DIPHDA_TOS_FW_CONFIG_BASE,
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, 0),
+ .image_info.image_base = BL32_BASE,
+ .image_info.image_max_size = BL32_LIMIT - BL32_BASE,
+
+ .next_handoff_image_id = BL33_IMAGE_ID,
+ },
+
+ /* Fill TOS_FW_CONFIG related information */
+ {
+ .image_id = TOS_FW_CONFIG_ID,
+ .image_info.image_base = DIPHDA_TOS_FW_CONFIG_BASE,
+ .image_info.image_max_size = DIPHDA_TOS_FW_CONFIG_LIMIT - \
+ DIPHDA_TOS_FW_CONFIG_BASE,
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
+ VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+ VERSION_2, image_info_t, 0),
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+
+ /* Fill BL33 related information */
+ {
+ .image_id = BL33_IMAGE_ID,
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
+ .ep_info.pc = PLAT_ARM_NS_IMAGE_BASE,
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, 0),
+ .image_info.image_base = PLAT_ARM_NS_IMAGE_BASE,
+ .image_info.image_max_size = ARM_DRAM1_BASE + ARM_DRAM1_SIZE
+ - PLAT_ARM_NS_IMAGE_BASE,
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+};
+
+REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
diff --git a/plat/arm/board/diphda/common/diphda_err.c b/plat/arm/board/diphda/common/diphda_err.c
new file mode 100644
index 0000000..89a3b82
--- /dev/null
+++ b/plat/arm/board/diphda/common/diphda_err.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/*
+ * diphda error handler
+ */
+void __dead2 plat_arm_error_handler(int err)
+{
+ while (1) {
+ wfi();
+ }
+}
diff --git a/plat/arm/board/diphda/common/diphda_helpers.S b/plat/arm/board/diphda/common/diphda_helpers.S
new file mode 100644
index 0000000..c9d2a88
--- /dev/null
+++ b/plat/arm/board/diphda/common/diphda_helpers.S
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <platform_def.h>
+
+ .globl plat_secondary_cold_boot_setup
+ .globl plat_get_my_entrypoint
+ .globl plat_is_my_cpu_primary
+ .globl plat_arm_calc_core_pos
+
+ /* --------------------------------------------------------------------
+ * void plat_secondary_cold_boot_setup (void);
+ *
+ * For AArch32, cold-booting secondary CPUs is not yet
+ * implemented and they panic.
+ * --------------------------------------------------------------------
+ */
+func plat_secondary_cold_boot_setup
+cb_panic:
+ b cb_panic
+endfunc plat_secondary_cold_boot_setup
+
+ /* ---------------------------------------------------------------------
+ * unsigned long plat_get_my_entrypoint (void);
+ *
+ * Main job of this routine is to distinguish between a cold and warm
+ * boot. On diphda, this information can be queried from the power
+ * controller. The Power Control SYS Status Register (PSYSR) indicates
+ * the wake-up reason for the CPU.
+ *
+ * For a cold boot, return 0.
+ * For a warm boot, Not yet supported.
+ *
+ * TODO: PSYSR is a common register and should be
+ * accessed using locks. Since it is not possible
+ * to use locks immediately after a cold reset
+ * we are relying on the fact that after a cold
+ * reset all cpus will read the same WK field
+ * ---------------------------------------------------------------------
+ */
+func plat_get_my_entrypoint
+ /* TODO support warm boot */
+ /* Cold reset */
+ mov x0, #0
+ ret
+endfunc plat_get_my_entrypoint
+
+ /* -----------------------------------------------------
+ * unsigned int plat_is_my_cpu_primary (void);
+ *
+ * Find out whether the current CPU is the primary
+ * CPU.
+ * -----------------------------------------------------
+ */
+func plat_is_my_cpu_primary
+ mrs x0, mpidr_el1
+ mov_imm x1, MPIDR_AFFINITY_MASK
+ and x0, x0, x1
+ cmp x0, #DIPHDA_PRIMARY_CPU
+ cset w0, eq
+ ret
+endfunc plat_is_my_cpu_primary
diff --git a/plat/arm/board/diphda/common/diphda_plat.c b/plat/arm/board/diphda/common/diphda_plat.c
new file mode 100644
index 0000000..28d15a5
--- /dev/null
+++ b/plat/arm/board/diphda/common/diphda_plat.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <common/bl_common.h>
+
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+/*
+ * Table of regions to map using the MMU.
+ * Replace or extend the below regions as required
+ */
+
+const mmap_region_t plat_arm_mmap[] = {
+ ARM_MAP_SHARED_RAM,
+ ARM_MAP_NS_SHARED_RAM,
+ ARM_MAP_NS_DRAM1,
+ DIPHDA_MAP_DEVICE,
+ DIPHDA_EXTERNAL_FLASH,
+ {0}
+};
+
+/* diphda only has one always-on power domain and there
+ * is no power control present
+ */
+void __init plat_arm_pwrc_setup(void)
+{
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+ /* Returning the Generic Timer Frequency */
+ return SYS_COUNTER_FREQ_IN_TICKS;
+}
+
+
+/*
+ * Helper function to initialize ARM interconnect driver.
+ */
+void plat_arm_interconnect_init(void)
+{
+}
+
+/*
+ * Helper function to place current master into coherency
+ */
+void plat_arm_interconnect_enter_coherency(void)
+{
+}
+
+/*
+ * Helper function to remove current master from coherency
+ */
+void plat_arm_interconnect_exit_coherency(void)
+{
+}
+
+/*
+ * This function is invoked during Mbed TLS library initialisation to get a heap
+ * The function simply returns the default allocated heap.
+ */
+
+#if TRUSTED_BOARD_BOOT
+int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
+{
+ assert(heap_addr != NULL);
+ assert(heap_size != NULL);
+
+ return arm_get_mbedtls_heap(heap_addr, heap_size);
+}
+#endif
diff --git a/plat/arm/board/diphda/common/diphda_pm.c b/plat/arm/board/diphda/common/diphda_pm.c
new file mode 100644
index 0000000..12b322e
--- /dev/null
+++ b/plat/arm/board/diphda/common/diphda_pm.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/psci/psci.h>
+#include <plat/arm/common/plat_arm.h>
+
+/*******************************************************************************
+ * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
+ * platform layer will take care of registering the handlers with PSCI.
+ ******************************************************************************/
+plat_psci_ops_t plat_arm_psci_pm_ops = {
+ /* dummy struct */
+ .validate_ns_entrypoint = NULL
+};
+
+const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
+{
+ return ops;
+}
diff --git a/plat/arm/board/diphda/common/diphda_security.c b/plat/arm/board/diphda/common/diphda_security.c
new file mode 100644
index 0000000..bf172af
--- /dev/null
+++ b/plat/arm/board/diphda/common/diphda_security.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*
+ * We assume that all security programming is done by the primary core.
+ */
+void plat_arm_security_setup(void)
+{
+ /*
+ * If the platform had additional peripheral specific security
+ * configurations, those would be configured here.
+ */
+}
diff --git a/plat/arm/board/diphda/common/diphda_stack_protector.c b/plat/arm/board/diphda/common/diphda_stack_protector.c
new file mode 100644
index 0000000..6228b63
--- /dev/null
+++ b/plat/arm/board/diphda/common/diphda_stack_protector.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <arch_helpers.h>
+#include <plat/common/platform.h>
+
+static uint32_t plat_generate_random_number(void)
+{
+ uintptr_t return_addr = (uintptr_t)__builtin_return_address(0U);
+ uintptr_t frame_addr = (uintptr_t)__builtin_frame_address(0U);
+ uint64_t cntpct = read_cntpct_el0();
+
+ /* Generate 32-bit pattern: saving the 2 least significant bytes
+ * in random_lo and random_hi
+ */
+ uint16_t random_lo = (uint16_t)(
+ (((uint64_t)return_addr) << 13) ^ frame_addr ^ cntpct
+ );
+
+ uint16_t random_hi = (uint16_t)(
+ (((uint64_t)frame_addr) << 15) ^ return_addr ^ cntpct
+ );
+
+ return (((uint32_t)random_hi) << 16) | random_lo;
+}
+
+u_register_t plat_get_stack_protector_canary(void)
+{
+ return plat_generate_random_number(); /* a 32-bit pattern returned */
+}
diff --git a/plat/arm/board/diphda/common/diphda_topology.c b/plat/arm/board/diphda/common/diphda_topology.c
new file mode 100644
index 0000000..9dfd05d
--- /dev/null
+++ b/plat/arm/board/diphda/common/diphda_topology.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+
+/* The diphda power domain tree descriptor */
+static unsigned char diphda_power_domain_tree_desc[PLAT_ARM_CLUSTER_COUNT
+ + 2];
+/*******************************************************************************
+ * This function dynamically constructs the topology according to
+ * CLUSTER_COUNT and returns it.
+ ******************************************************************************/
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+ int i;
+
+ /*
+ * The highest level is the system level. The next level is constituted
+ * by clusters and then cores in clusters.
+ */
+ diphda_power_domain_tree_desc[0] = 1;
+ diphda_power_domain_tree_desc[1] = PLAT_ARM_CLUSTER_COUNT;
+
+ for (i = 0; i < PLAT_ARM_CLUSTER_COUNT; i++)
+ diphda_power_domain_tree_desc[i + 2] = PLATFORM_CORE_COUNT;
+
+ return diphda_power_domain_tree_desc;
+}
+
+/******************************************************************************
+ * This function implements a part of the critical interface between the PSCI
+ * generic layer and the platform that allows the former to query the platform
+ * to convert an MPIDR to a unique linear index. An error code (-1) is
+ * returned in case the MPIDR is invalid.
+ *****************************************************************************/
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+ return plat_arm_calc_core_pos(mpidr);
+}
diff --git a/plat/arm/board/diphda/common/diphda_trusted_boot.c b/plat/arm/board/diphda/common/diphda_trusted_boot.c
new file mode 100644
index 0000000..ddb41fa
--- /dev/null
+++ b/plat/arm/board/diphda/common/diphda_trusted_boot.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/*
+ * Return the ROTPK hash in the following ASN.1 structure in DER format:
+ *
+ * AlgorithmIdentifier ::= SEQUENCE {
+ * algorithm OBJECT IDENTIFIER,
+ * parameters ANY DEFINED BY algorithm OPTIONAL
+ * }
+ *
+ * DigestInfo ::= SEQUENCE {
+ * digestAlgorithm AlgorithmIdentifier,
+ * digest OCTET STRING
+ * }
+ *
+ * The function returns 0 on success. Any other value is treated as error by the
+ * Trusted Board Boot. The function also reports extra information related
+ * to the ROTPK in the flags parameter: ROTPK_IS_HASH, ROTPK_NOT_DEPLOYED.
+ *
+ * Refer to the TF-A porting-guide document for more details.
+ */
+int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
+ unsigned int *flags)
+{
+ return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
+}
+
+/*
+ * STUB overriding the non-volatile counter reading.
+ * NV counters are not implemented at this stage of development.
+ * Return: 0 = success
+ */
+int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr)
+{
+ *nv_ctr = DIPHDA_FW_NVCTR_VAL;
+ return 0;
+}
+
+/*
+ * STUB overriding the non-volatile counter updating.
+ * NV counters are not implemented at this stage of development.
+ * Return: 0 = success
+ */
+int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr)
+{
+ return 0;
+}
diff --git a/plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts b/plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts
new file mode 100644
index 0000000..536bdc3
--- /dev/null
+++ b/plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/dts-v1/;
+
+/ {
+ compatible = "arm,ffa-core-manifest-1.0";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ /*
+ * BL32 image details needed by SPMC
+ *
+ * Note:
+ * binary_size: size of BL32 + TOS_FW_CONFIG
+ */
+
+ attribute {
+ spmc_id = <0x8000>;
+ maj_ver = <0x1>;
+ min_ver = <0x1>;
+ exec_state = <0x0>;
+ load_address = <0x0 0x2002000>;
+ entrypoint = <0x0 0x2002000>;
+ binary_size = <0xae000>;
+ };
+
+};
diff --git a/plat/arm/board/diphda/common/include/platform_def.h b/plat/arm/board/diphda/common/include/platform_def.h
new file mode 100644
index 0000000..37fd71b
--- /dev/null
+++ b/plat/arm/board/diphda/common/include/platform_def.h
@@ -0,0 +1,416 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <common/tbbr/tbbr_img_def.h>
+#include <lib/utils_def.h>
+#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <plat/arm/board/common/v2m_def.h>
+#include <plat/arm/common/arm_spm_def.h>
+#include <plat/arm/common/smccc_def.h>
+#include <plat/common/common_def.h>
+#include <plat/arm/soc/common/soc_css_def.h>
+
+#define ARM_ROTPK_HEADER_LEN 19
+#define ARM_ROTPK_HASH_LEN 32
+
+/* Special value used to verify platform parameters from BL2 to BL31 */
+#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978)
+
+/* PL011 UART related constants */
+#ifdef V2M_IOFPGA_UART0_CLK_IN_HZ
+#undef V2M_IOFPGA_UART0_CLK_IN_HZ
+#endif
+
+#ifdef V2M_IOFPGA_UART1_CLK_IN_HZ
+#undef V2M_IOFPGA_UART1_CLK_IN_HZ
+#endif
+
+#define V2M_IOFPGA_UART0_CLK_IN_HZ 50000000
+#define V2M_IOFPGA_UART1_CLK_IN_HZ 50000000
+
+/* Core/Cluster/Thread counts for diphda */
+#define DIPHDA_CLUSTER_COUNT U(1)
+#define DIPHDA_MAX_CPUS_PER_CLUSTER U(4)
+#define DIPHDA_MAX_PE_PER_CPU U(1)
+#define DIPHDA_PRIMARY_CPU U(0)
+
+#define PLAT_ARM_CLUSTER_COUNT DIPHDA_CLUSTER_COUNT
+
+#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \
+ DIPHDA_MAX_CPUS_PER_CLUSTER * \
+ DIPHDA_MAX_PE_PER_CPU)
+
+/* UART related constants */
+#define PLAT_ARM_BOOT_UART_BASE 0x1a510000
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
+#define PLAT_ARM_RUN_UART_BASE 0x1a520000
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ V2M_IOFPGA_UART1_CLK_IN_HZ
+#define ARM_CONSOLE_BAUDRATE 115200
+#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
+#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
+
+/* Memory related constants */
+
+/* SRAM (CVM) memory layout
+ *
+ * <ARM_TRUSTED_SRAM_BASE>
+ *
+ * partition size: sizeof(meminfo_t) = 16 bytes
+ *
+ * content: memory info area used by the next BL
+ *
+ * <ARM_FW_CONFIG_BASE>
+ *
+ * partition size: 4080 bytes
+ *
+ * <ARM_BL2_MEM_DESC_BASE>
+ *
+ * partition size: 4 KB
+ *
+ * content:
+ *
+ * Area where BL2 copies the images descriptors
+ *
+ * <ARM_BL_RAM_BASE> = <BL32_BASE>
+ *
+ * partition size: 688 KB
+ *
+ * content:
+ *
+ * BL32 (optee-os)
+ *
+ * <DIPHDA_TOS_FW_CONFIG_BASE> = 0x20ae000
+ *
+ * partition size: 8 KB
+ *
+ * content:
+ *
+ * BL32 config (TOS_FW_CONFIG)
+ *
+ * <BL31_BASE>
+ *
+ * partition size: 140 KB
+ *
+ * content:
+ *
+ * BL31
+ *
+ * <BL2_SIGNATURE_BASE>
+ *
+ * partition size: 4 KB
+ *
+ * content:
+ *
+ * MCUBOOT data needed to verify TF-A BL2
+ *
+ * <BL2_BASE>
+ *
+ * partition size: 176 KB
+ *
+ * content:
+ *
+ * BL2
+ *
+ * <ARM_NS_SHARED_RAM_BASE> = <ARM_TRUSTED_SRAM_BASE> + 1 MB
+ *
+ * partition size: 3 MB
+ *
+ * content:
+ *
+ * BL33 (u-boot)
+ */
+
+/* DDR memory */
+#define ARM_DRAM1_BASE UL(0x80000000)
+#define ARM_DRAM1_SIZE UL(0x80000000)
+#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
+ ARM_DRAM1_SIZE - 1)
+
+/* DRAM1 and DRAM2 are the same for diphda */
+#define ARM_DRAM2_BASE ARM_DRAM1_BASE
+#define ARM_DRAM2_SIZE ARM_DRAM1_SIZE
+#define ARM_DRAM2_END ARM_DRAM1_END
+
+#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
+#define ARM_NS_DRAM1_SIZE ARM_DRAM1_SIZE
+#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
+ ARM_NS_DRAM1_SIZE - 1)
+
+/* The first 8 KB of Trusted SRAM are used as shared memory */
+#define ARM_TRUSTED_SRAM_BASE UL(0x02000000)
+#define ARM_SHARED_RAM_SIZE UL(0x00002000) /* 8 KB */
+#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE
+
+/* The remaining Trusted SRAM is used to load the BL images */
+
+#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00100000) /* 1 MB */
+
+#define PLAT_ARM_MAX_BL2_SIZE UL(0x0002d000) /* 180 KB */
+
+#define PLAT_ARM_MAX_BL31_SIZE UL(0x00023000) /* 140 KB */
+
+#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \
+ ARM_SHARED_RAM_SIZE)
+#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
+ ARM_SHARED_RAM_SIZE)
+
+#define BL2_SIGNATURE_SIZE UL(0x00001000) /* 4 KB */
+#define BL2_SIGNATURE_BASE (BL2_LIMIT - \
+ PLAT_ARM_MAX_BL2_SIZE)
+#define BL2_BASE (BL2_LIMIT - \
+ PLAT_ARM_MAX_BL2_SIZE + \
+ BL2_SIGNATURE_SIZE)
+#define BL2_LIMIT (ARM_BL_RAM_BASE + \
+ ARM_BL_RAM_SIZE)
+
+#define BL31_BASE (BL2_SIGNATURE_BASE - \
+ PLAT_ARM_MAX_BL31_SIZE)
+#define BL31_LIMIT BL2_SIGNATURE_BASE
+
+#define DIPHDA_TOS_FW_CONFIG_BASE (BL31_BASE - \
+ DIPHDA_TOS_FW_CONFIG_SIZE)
+#define DIPHDA_TOS_FW_CONFIG_SIZE UL(0x00002000) /* 8 KB */
+#define DIPHDA_TOS_FW_CONFIG_LIMIT BL31_BASE
+
+#define BL32_BASE ARM_BL_RAM_BASE
+#define PLAT_ARM_MAX_BL32_SIZE (DIPHDA_TOS_FW_CONFIG_BASE - \
+ BL32_BASE) /* 688 KB */
+#define BL32_LIMIT (BL32_BASE + \
+ PLAT_ARM_MAX_BL32_SIZE)
+
+/* SPD_spmd settings */
+
+#define PLAT_ARM_SPMC_BASE BL32_BASE
+#define PLAT_ARM_SPMC_SIZE PLAT_ARM_MAX_BL32_SIZE
+
+/* NS memory */
+
+/* The last 3 MB of the SRAM is allocated to the non secure area */
+#define ARM_NS_SHARED_RAM_BASE (ARM_TRUSTED_SRAM_BASE + \
+ PLAT_ARM_TRUSTED_SRAM_SIZE)
+#define ARM_NS_SHARED_RAM_SIZE UL(0x00300000) /* 3 MB */
+
+/* end of the definition of SRAM memory layout */
+
+/* NOR Flash */
+
+#define PLAT_ARM_FIP_BASE UL(0x08131000)
+#define PLAT_ARM_FIP_MAX_SIZE UL(0x1ff000) /* 1.996 MB */
+
+#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
+#define PLAT_ARM_NVM_SIZE UL(0x02000000) /* 32 MB */
+
+#define PLAT_ARM_FLASH_IMAGE_BASE PLAT_ARM_FIP_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE PLAT_ARM_FIP_MAX_SIZE
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ */
+#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT)
+#define ARM_CACHE_WRITEBACK_SHIFT 6
+
+/*
+ * Define FW_CONFIG area base and limit. Leave enough space for BL2 meminfo.
+ * FW_CONFIG is intended to host the device tree. Currently, This area is not
+ * used because diphda platform doesn't use a device tree at TF-A level.
+ */
+#define ARM_FW_CONFIG_BASE (ARM_SHARED_RAM_BASE \
+ + sizeof(meminfo_t))
+#define ARM_FW_CONFIG_LIMIT (ARM_SHARED_RAM_BASE \
+ + (ARM_SHARED_RAM_SIZE >> 1))
+
+/*
+ * Boot parameters passed from BL2 to BL31/BL32 are stored here
+ */
+#define ARM_BL2_MEM_DESC_BASE ARM_FW_CONFIG_LIMIT
+#define ARM_BL2_MEM_DESC_LIMIT ARM_BL_RAM_BASE
+
+/*
+ * The max number of regions like RO(code), coherent and data required by
+ * different BL stages which need to be mapped in the MMU.
+ */
+#define ARM_BL_REGIONS 3
+#define PLAT_ARM_MMAP_ENTRIES 8
+#define MAX_XLAT_TABLES 5
+#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
+ ARM_BL_REGIONS)
+#define MAX_IO_DEVICES 2
+#define MAX_IO_HANDLES 3
+#define MAX_IO_BLOCK_DEVICES 1
+
+/* GIC related constants */
+#define PLAT_ARM_GICD_BASE 0x1C010000
+#define PLAT_ARM_GICC_BASE 0x1C02F000
+
+/* MHUv2 Secure Channel receiver and sender */
+#define PLAT_SDK700_MHU0_SEND 0x1B800000
+#define PLAT_SDK700_MHU0_RECV 0x1B810000
+
+/* Timer/watchdog related constants */
+#define ARM_SYS_CNTCTL_BASE UL(0x1a200000)
+#define ARM_SYS_CNTREAD_BASE UL(0x1a210000)
+#define ARM_SYS_TIMCTL_BASE UL(0x1a220000)
+
+#define SYS_COUNTER_FREQ_IN_TICKS UL(50000000) /* 50MHz */
+
+#define DIPHDA_IRQ_TZ_WDOG 32
+#define DIPHDA_IRQ_SEC_SYS_TIMER 34
+
+#define PLAT_MAX_PWR_LVL 2
+/*
+ * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
+ * power levels have a 1:1 mapping with the MPIDR affinity levels.
+ */
+#define ARM_PWR_LVL0 MPIDR_AFFLVL0
+#define ARM_PWR_LVL1 MPIDR_AFFLVL1
+#define ARM_PWR_LVL2 MPIDR_AFFLVL2
+
+/*
+ * Macros for local power states in ARM platforms encoded by State-ID field
+ * within the power-state parameter.
+ */
+/* Local power state for power domains in Run state. */
+#define ARM_LOCAL_STATE_RUN U(0)
+/* Local power state for retention. Valid only for CPU power domains */
+#define ARM_LOCAL_STATE_RET U(1)
+/* Local power state for OFF/power-down. Valid for CPU and cluster
+ * power domains
+ */
+#define ARM_LOCAL_STATE_OFF U(2)
+
+#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
+#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
+
+#define PLAT_ARM_NS_IMAGE_BASE (ARM_NS_SHARED_RAM_BASE)
+
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+
+/*
+ * This macro defines the deepest retention state possible. A higher state
+ * ID will represent an invalid or a power down state.
+ */
+#define PLAT_MAX_RET_STATE 1
+
+/*
+ * This macro defines the deepest power down states possible. Any state ID
+ * higher than this is invalid.
+ */
+#define PLAT_MAX_OFF_STATE 2
+
+#define PLATFORM_STACK_SIZE UL(0x440)
+
+#define DIPHDA_EXTERNAL_FLASH MAP_REGION_FLAT( \
+ PLAT_ARM_NVM_BASE, \
+ PLAT_ARM_NVM_SIZE, \
+ MT_DEVICE | MT_RO | MT_SECURE)
+
+#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
+ ARM_SHARED_RAM_BASE, \
+ ARM_SHARED_RAM_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
+#define ARM_MAP_NS_SHARED_RAM MAP_REGION_FLAT( \
+ ARM_NS_SHARED_RAM_BASE, \
+ ARM_NS_SHARED_RAM_SIZE, \
+ MT_MEMORY | MT_RW | MT_NS)
+
+#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
+ ARM_NS_DRAM1_BASE, \
+ ARM_NS_DRAM1_SIZE, \
+ MT_MEMORY | MT_RW | MT_NS)
+
+#define ARM_MAP_BL_RO MAP_REGION_FLAT( \
+ BL_CODE_BASE, \
+ BL_CODE_END \
+ - BL_CODE_BASE, \
+ MT_CODE | MT_SECURE), \
+ MAP_REGION_FLAT( \
+ BL_RO_DATA_BASE, \
+ BL_RO_DATA_END \
+ - BL_RO_DATA_BASE, \
+ MT_RO_DATA | MT_SECURE)
+#if USE_COHERENT_MEM
+#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
+ BL_COHERENT_RAM_BASE, \
+ BL_COHERENT_RAM_END \
+ - BL_COHERENT_RAM_BASE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+#endif
+
+/*
+ * Map the region for the optional device tree configuration with read and
+ * write permissions
+ */
+#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT( \
+ ARM_FW_CONFIG_BASE, \
+ (ARM_FW_CONFIG_LIMIT- \
+ ARM_FW_CONFIG_BASE), \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
+#define DIPHDA_DEVICE_BASE (0x1A000000)
+#define DIPHDA_DEVICE_SIZE (0x26000000)
+#define DIPHDA_MAP_DEVICE MAP_REGION_FLAT( \
+ DIPHDA_DEVICE_BASE, \
+ DIPHDA_DEVICE_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define ARM_IRQ_SEC_PHY_TIMER 29
+
+#define ARM_IRQ_SEC_SGI_0 8
+#define ARM_IRQ_SEC_SGI_1 9
+#define ARM_IRQ_SEC_SGI_2 10
+#define ARM_IRQ_SEC_SGI_3 11
+#define ARM_IRQ_SEC_SGI_4 12
+#define ARM_IRQ_SEC_SGI_5 13
+#define ARM_IRQ_SEC_SGI_6 14
+#define ARM_IRQ_SEC_SGI_7 15
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define ARM_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_LEVEL), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_EDGE)
+
+#define ARM_G0_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \
+ GIC_INTR_CFG_EDGE)
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
+ ARM_G1S_IRQ_PROPS(grp), \
+ INTR_PROP_DESC(DIPHDA_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \
+ (grp), GIC_INTR_CFG_LEVEL), \
+ INTR_PROP_DESC(DIPHDA_IRQ_SEC_SYS_TIMER, \
+ GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL)
+
+#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/diphda/include/plat_macros.S b/plat/arm/board/diphda/include/plat_macros.S
new file mode 100644
index 0000000..4de8f95
--- /dev/null
+++ b/plat/arm/board/diphda/include/plat_macros.S
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef PLAT_MACROS_S
+#define PLAT_MACROS_S
+
+#include <css_macros.S>
+
+/* ---------------------------------------------
+ * The below required platform porting macro
+ * prints out relevant platform registers
+ * whenever an unhandled exception is taken in
+ * BL31.
+ * ---------------------------------------------
+ */
+ .macro plat_crash_print_regs
+ css_print_gic_regs
+ .endm
+
+#endif /* PLAT_MACROS_S */
diff --git a/plat/arm/board/diphda/platform.mk b/plat/arm/board/diphda/platform.mk
new file mode 100644
index 0000000..8b89cee
--- /dev/null
+++ b/plat/arm/board/diphda/platform.mk
@@ -0,0 +1,83 @@
+#
+# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Making sure the diphda platform type is specified
+ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),)
+ $(error TARGET_PLATFORM must be fpga or fvp)
+endif
+
+DIPHDA_CPU_LIBS +=lib/cpus/aarch64/cortex_a35.S
+
+PLAT_INCLUDES := -Iplat/arm/board/diphda/common/include \
+ -Iplat/arm/board/diphda/include \
+ -Iinclude/plat/arm/common \
+ -Iinclude/plat/arm/css/common/aarch64
+
+
+DIPHDA_FW_NVCTR_VAL := 255
+TFW_NVCTR_VAL := ${DIPHDA_FW_NVCTR_VAL}
+NTFW_NVCTR_VAL := ${DIPHDA_FW_NVCTR_VAL}
+
+override NEED_BL1 := no
+
+override NEED_BL2 := yes
+FIP_BL2_ARGS := tb-fw
+
+override NEED_BL2U := no
+override NEED_BL31 := yes
+NEED_BL32 := yes
+override NEED_BL33 := yes
+
+# Include GICv2 driver files
+include drivers/arm/gic/v2/gicv2.mk
+
+DIPHDA_GIC_SOURCES := ${GICV2_SOURCES} \
+ plat/common/plat_gicv2.c \
+ plat/arm/common/arm_gicv2.c
+
+
+BL2_SOURCES += plat/arm/board/diphda/common/diphda_security.c \
+ plat/arm/board/diphda/common/diphda_err.c \
+ plat/arm/board/diphda/common/diphda_trusted_boot.c \
+ lib/utils/mem_region.c \
+ plat/arm/board/diphda/common/diphda_helpers.S \
+ plat/arm/board/diphda/common/diphda_plat.c \
+ plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c \
+ ${DIPHDA_CPU_LIBS} \
+
+
+BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \
+ lib/utils/mem_region.c \
+ plat/arm/board/diphda/common/diphda_helpers.S \
+ plat/arm/board/diphda/common/diphda_topology.c \
+ plat/arm/board/diphda/common/diphda_security.c \
+ plat/arm/board/diphda/common/diphda_plat.c \
+ plat/arm/board/diphda/common/diphda_pm.c \
+ ${DIPHDA_CPU_LIBS} \
+ ${DIPHDA_GIC_SOURCES}
+
+ifneq (${ENABLE_STACK_PROTECTOR},0)
+ ifneq (${ENABLE_STACK_PROTECTOR},none)
+ DIPHDA_SECURITY_SOURCES := plat/arm/board/diphda/common/diphda_stack_protector.c
+ BL2_SOURCES += ${DIPHDA_SECURITY_SOURCES}
+ BL31_SOURCES += ${DIPHDA_SECURITY_SOURCES}
+ endif
+endif
+
+FDT_SOURCES += plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts
+DIPHDA_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/diphda_spmc_manifest.dtb
+
+# Add the SPMC manifest to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${DIPHDA_TOS_FW_CONFIG},--tos-fw-config,${DIPHDA_TOS_FW_CONFIG}))
+
+# Adding TARGET_PLATFORM as a GCC define (-D option)
+$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM})))
+
+# Adding DIPHDA_FW_NVCTR_VAL as a GCC define (-D option)
+$(eval $(call add_define,DIPHDA_FW_NVCTR_VAL))
+
+include plat/arm/common/arm_common.mk
+include plat/arm/board/common/board_common.mk
diff --git a/plat/arm/board/fvp/fdts/fvp_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
index 9fb566b..cad888f 100644
--- a/plat/arm/board/fvp/fdts/fvp_fw_config.dts
+++ b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
@@ -36,16 +36,21 @@
id = <SOC_FW_CONFIG_ID>;
};
+/* If required, SPD should enable loading of trusted OS fw config */
+#if defined(SPD_tspd) || defined(SPD_spmd)
tos_fw-config {
load-address = <0x0 0x04001500>;
max-size = <0xB00>;
id = <TOS_FW_CONFIG_ID>;
};
+#endif
+#if !defined(SPD_spmd)
nt_fw-config {
load-address = <0x0 0x80000000>;
max-size = <0x200>;
id = <NT_FW_CONFIG_ID>;
};
+#endif
};
};
diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
index f4805db..21a6073 100644
--- a/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
+++ b/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -20,7 +20,7 @@
attribute {
spmc_id = <0x8000>;
maj_ver = <0x1>;
- min_ver = <0x0>;
+ min_ver = <0x1>;
exec_state = <0x0>;
load_address = <0x0 0x6000000>;
entrypoint = <0x0 0x6000000>;
@@ -47,7 +47,14 @@
is_ffa_partition;
debug_name = "cactus-tertiary";
load_address = <0x7200000>;
- vcpu_count = <8>;
+ vcpu_count = <1>;
+ mem_size = <1048576>;
+ };
+ vm4 {
+ is_ffa_partition;
+ debug_name = "ivy";
+ load_address = <0x7600000>;
+ vcpu_count = <1>;
mem_size = <1048576>;
};
};
diff --git a/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts b/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
index 57d6792..041dade 100644
--- a/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
+++ b/plat/arm/board/fvp/fdts/fvp_spmc_optee_sp_manifest.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -20,7 +20,7 @@
attribute {
spmc_id = <0x8000>;
maj_ver = <0x1>;
- min_ver = <0x0>;
+ min_ver = <0x1>;
exec_state = <0x0>;
load_address = <0x0 0x6000000>;
entrypoint = <0x0 0x6000000>;
@@ -33,7 +33,6 @@
is_ffa_partition;
debug_name = "op-tee";
load_address = <0x6280000>;
- smc_whitelist = <0xbe000000>;
vcpu_count = <8>;
mem_size = <1048576>;
};
diff --git a/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
index fe154e9..62ab27c 100644
--- a/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
+++ b/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2020-2021, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -48,26 +48,26 @@
arm-io_policies {
fip-handles {
compatible = "arm,io-fip-handle";
- scp_bl2_uuid = <0x9766fd3d 0x89bee849 0xae5d78a1 0x40608213>;
- bl31_uuid = <0x47d4086d 0x4cfe9846 0x9b952950 0xcbbd5a00>;
- bl32_uuid = <0x05d0e189 0x53dc1347 0x8d2b500a 0x4b7a3e38>;
- bl32_extra1_uuid = <0x0b70c28b 0x2a5a7840 0x9f650a56 0x82738288>;
- bl32_extra2_uuid = <0x8ea87bb1 0xcfa23f4d 0x85fde7bb 0xa50220d9>;
- bl33_uuid = <0xd6d0eea7 0xfcead54b 0x97829934 0xf234b6e4>;
- hw_cfg_uuid = <0x08b8f1d9 0xc9cf9349 0xa9626fbc 0x6b7265cc>;
- soc_fw_cfg_uuid = <0x9979814b 0x0376fb46 0x8c8e8d26 0x7f7859e0>;
- tos_fw_cfg_uuid = <0x26257c1a 0xdbc67f47 0x8d96c4c4 0xb0248021>;
- nt_fw_cfg_uuid = <0x28da9815 0x93e87e44 0xac661aaf 0x801550f9>;
- t_key_cert_uuid = <0x827ee890 0xf860e411 0xa1b477a7 0x21b4f94c>;
- scp_fw_key_uuid = <0x024221a1 0xf860e411 0x8d9bf33c 0x0e15a014>;
- soc_fw_key_uuid = <0x8ab8becc 0xf960e411 0x9ad0eb48 0x22d8dcf8>;
- tos_fw_key_cert_uuid = <0x9477d603 0xfb60e411 0x85ddb710 0x5b8cee04>;
- nt_fw_key_cert_uuid = <0x8ad5832a 0xfb60e411 0x8aafdf30 0xbbc49859>;
- scp_fw_content_cert_uuid = <0x44be6f04 0x5e63e411 0xb28b73d8 0xeaae9656>;
- soc_fw_content_cert_uuid = <0xe2b20c20 0x5e63e411 0x9ce8abcc 0xf92bb666>;
- tos_fw_content_cert_uuid = <0xa49f4411 0x5e63e411 0x87283f05 0x722af33d>;
- nt_fw_content_cert_uuid = <0x8ec4c1f3 0x5d63e411 0xa7a987ee 0x40b23fa7>;
- sp_content_cert_uuid = <0x776dfd44 0x86974c3b 0x91ebc13e 0x025a2a6f>;
+ scp_bl2_uuid = "9766fd3d-89be-e849-ae5d-78a140608213";
+ bl31_uuid = "47d4086d-4cfe-9846-9b95-2950cbbd5a00";
+ bl32_uuid = "05d0e189-53dc-1347-8d2b-500a4b7a3e38";
+ bl32_extra1_uuid = "0b70c29b-2a5a-7840-9f65-0a5682738288";
+ bl32_extra2_uuid = "8ea87bb1-cfa2-3f4d-85fd-e7bba50220d9";
+ bl33_uuid = "d6d0eea7-fcea-d54b-9782-9934f234b6e4";
+ hw_cfg_uuid = "08b8f1d9-c9cf-9349-a962-6fbc6b7265cc";
+ soc_fw_cfg_uuid = "9979814b-0376-fb46-8c8e-8d267f7859e0";
+ tos_fw_cfg_uuid = "26257c1a-dbc6-7f47-8d96-c4c4b0248021";
+ nt_fw_cfg_uuid = "28da9815-93e8-7e44-ac66-1aaf801550f9";
+ t_key_cert_uuid = "827ee890-f860-e411-a1b4-777a21b4f94c";
+ scp_fw_key_uuid = "024221a1-f860-e411-8d9b-f33c0e15a014";
+ soc_fw_key_uuid = "8ab8becc-f960-e411-9ad0-eb4822d8dcf8";
+ tos_fw_key_cert_uuid = "9477d603-fb60-e411-85dd-b7105b8cee04";
+ nt_fw_key_cert_uuid = "8ad5832a-fb60-e411-8aaf-df30bbc49859";
+ scp_fw_content_cert_uuid = "44be6f04-5e63-e411-b28b-73d8eaae9656";
+ soc_fw_content_cert_uuid = "e2b20c20-5e63-e411-9ce8-abccf92bb666";
+ tos_fw_content_cert_uuid = "a49f4411-5e63-e411-8728-3f05722af33d";
+ nt_fw_content_cert_uuid = "8ec4c1f3-5d63-e411-a7a9-87ee40b23fa7";
+ sp_content_cert_uuid = "776dfd44-8697-4c3b-91eb-c13e025a2a6f";
};
};
#endif /* ARM_IO_IN_DTB */
@@ -76,25 +76,32 @@
compatible = "arm,sp";
#ifdef OPTEE_SP_FW_CONFIG
op-tee {
- uuid = <0x486178e0 0xe7f811e3 0xbc5e0002 0xa5d5c51b>;
+ uuid = "486178e0-e7f8-11e3-bc5e-0002a5d5c51b";
load-address = <0x6280000>;
};
#else
cactus-primary {
- uuid = <0xb4b5671e 0x4a904fe1 0xb81ffb13 0xdae1dacb>;
+ uuid = "b4b5671e-4a90-4fe1-b81f-fb13dae1dacb";
load-address = <0x7000000>;
owner = "SiP";
};
cactus-secondary {
- uuid = <0xd1582309 0xf02347b9 0x827c4464 0xf5578fc8>;
+ uuid = "d1582309-f023-47b9-827c-4464f5578fc8";
load-address = <0x7100000>;
owner = "Plat";
};
cactus-tertiary {
- uuid = <0x79b55c73 0x1d8c44b9 0x859361e1 0x770ad8d2>;
+ uuid = "79b55c73-1d8c-44b9-8593-61e1770ad8d2";
load-address = <0x7200000>;
+ owner = "Plat";
+ };
+
+ ivy {
+ uuid = "eaba83d8-baaf-4eaf-8144-f7fdcbe544a7";
+ load-address = <0x7600000>;
+ owner = "Plat";
};
#endif
};
diff --git a/plat/arm/board/fvp/fdts/optee_sp_manifest.dts b/plat/arm/board/fvp/fdts/optee_sp_manifest.dts
index 928d0d3..07235b0 100644
--- a/plat/arm/board/fvp/fdts/optee_sp_manifest.dts
+++ b/plat/arm/board/fvp/fdts/optee_sp_manifest.dts
@@ -25,7 +25,7 @@
entrypoint-offset = <0x1000>;
xlat-granule = <0>; /* 4KiB */
boot-order = <0>;
- messaging-method = <0>; /* Direct messaging only */
+ messaging-method = <3>; /* Direct messaging only */
run-time-model = <1>; /* Run to completion */
/* Boot protocol */
diff --git a/plat/arm/board/fvp/fvp_bl1_setup.c b/plat/arm/board/fvp/fvp_bl1_setup.c
index e713bbc..06ee037 100644
--- a/plat/arm/board/fvp/fvp_bl1_setup.c
+++ b/plat/arm/board/fvp/fvp_bl1_setup.c
@@ -1,15 +1,17 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
+#include <errno.h>
#include <bl1/bl1.h>
#include <common/tbbr/tbbr_img_def.h>
#include <drivers/arm/smmu_v3.h>
#include <drivers/arm/sp805.h>
+#include <lib/mmio.h>
#include <plat/arm/common/arm_config.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/arm/common/arm_def.h>
@@ -61,6 +63,12 @@
__dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved)
{
+ uint32_t nv_flags = mmio_read_32(V2M_SYS_NVFLAGS_ADDR);
+
+ /* Clear the NV flags register. */
+ mmio_write_32((V2M_SYSREGS_BASE + V2M_SYS_NVFLAGSCLR),
+ nv_flags);
+
/* Setup the watchdog to reset the system as soon as possible */
sp805_refresh(ARM_SP805_TWDG_BASE, 1U);
@@ -124,3 +132,15 @@
return 0;
}
#endif /* MEASURED_BOOT */
+
+/*******************************************************************************
+ * The following function checks if Firmware update is needed by checking error
+ * reported in NV flag.
+ ******************************************************************************/
+bool plat_arm_bl1_fwu_needed(void)
+{
+ int32_t nv_flags = (int32_t)mmio_read_32(V2M_SYS_NVFLAGS_ADDR);
+
+ /* if image load/authentication failed */
+ return ((nv_flags == -EAUTH) || (nv_flags == -ENOENT));
+}
diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index 52686fa..9d3c031 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -72,14 +72,11 @@
* Table of memory regions for various BL stages to map using the MMU.
* This doesn't include Trusted SRAM as setup_page_tables() already takes care
* of mapping it.
- *
- * The flash needs to be mapped as writable in order to erase the FIP's Table of
- * Contents in case of unrecoverable error (see plat_error_handler()).
*/
#ifdef IMAGE_BL1
const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
- V2M_MAP_FLASH0_RW,
+ V2M_MAP_FLASH0_RO,
V2M_MAP_IOFPGA,
MAP_DEVICE0,
#if FVP_INTERCONNECT_DRIVER == FVP_CCN
@@ -483,9 +480,9 @@
int32_t plat_get_soc_version(void)
{
return (int32_t)
- ((ARM_SOC_IDENTIFICATION_CODE << ARM_SOC_IDENTIFICATION_SHIFT)
- | (ARM_SOC_CONTINUATION_CODE << ARM_SOC_CONTINUATION_SHIFT)
- | FVP_SOC_ID);
+ (SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE,
+ ARM_SOC_IDENTIFICATION_CODE) |
+ (FVP_SOC_ID & SOC_ID_IMPL_DEF_MASK));
}
/* Get SOC revision */
@@ -494,6 +491,6 @@
unsigned int sys_id;
sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
- return (int32_t)((sys_id >> V2M_SYS_ID_REV_SHIFT) &
- V2M_SYS_ID_REV_MASK);
+ return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) &
+ V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK);
}
diff --git a/plat/arm/board/fvp/fvp_err.c b/plat/arm/board/fvp/fvp_err.c
index c9b2090..1f9f0dd 100644
--- a/plat/arm/board/fvp/fvp_err.c
+++ b/plat/arm/board/fvp/fvp_err.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,6 +9,7 @@
#include <common/debug.h>
#include <drivers/arm/sp805.h>
#include <drivers/cfi/v2m_flash.h>
+#include <lib/mmio.h>
#include <plat/arm/common/plat_arm.h>
#include <platform_def.h>
@@ -17,25 +18,8 @@
*/
__dead2 void plat_arm_error_handler(int err)
{
- int ret;
-
- switch (err) {
- case -ENOENT:
- case -EAUTH:
- /* Image load or authentication error. Erase the ToC */
- INFO("Erasing FIP ToC from flash...\n");
- (void)nor_unlock(PLAT_ARM_FIP_BASE);
- ret = nor_word_program(PLAT_ARM_FIP_BASE, 0);
- if (ret != 0) {
- ERROR("Cannot erase ToC\n");
- } else {
- INFO("Done\n");
- }
- break;
- default:
- /* Unexpected error */
- break;
- }
+ /* Propagate the err code in the NV-flags register */
+ mmio_write_32(V2M_SYS_NVFLAGS_ADDR, (uint32_t)err);
console_flush();
diff --git a/plat/arm/board/fvp/fvp_io_storage.c b/plat/arm/board/fvp/fvp_io_storage.c
index 109d321..4eef51c 100644
--- a/plat/arm/board/fvp/fvp_io_storage.c
+++ b/plat/arm/board/fvp/fvp_io_storage.c
@@ -20,6 +20,10 @@
#define BL32_IMAGE_NAME "bl32.bin"
#define BL33_IMAGE_NAME "bl33.bin"
#define TB_FW_CONFIG_NAME "fvp_tb_fw_config.dtb"
+#define SOC_FW_CONFIG_NAME "fvp_soc_fw_config.dtb"
+#define TOS_FW_CONFIG_NAME "fvp_tsp_fw_config.dtb"
+#define NT_FW_CONFIG_NAME "fvp_nt_fw_config.dtb"
+#define FW_CONFIG_NAME "fvp_fw_config.dtb"
#define HW_CONFIG_NAME "hw_config.dtb"
#if TRUSTED_BOARD_BOOT
@@ -58,6 +62,22 @@
.path = TB_FW_CONFIG_NAME,
.mode = FOPEN_MODE_RB
},
+ [SOC_FW_CONFIG_ID] = {
+ .path = SOC_FW_CONFIG_NAME,
+ .mode = FOPEN_MODE_RB
+ },
+ [TOS_FW_CONFIG_ID] = {
+ .path = TOS_FW_CONFIG_NAME,
+ .mode = FOPEN_MODE_RB
+ },
+ [NT_FW_CONFIG_ID] = {
+ .path = NT_FW_CONFIG_NAME,
+ .mode = FOPEN_MODE_RB
+ },
+ [FW_CONFIG_ID] = {
+ .path = FW_CONFIG_NAME,
+ .mode = FOPEN_MODE_RB
+ },
[HW_CONFIG_ID] = {
.path = HW_CONFIG_NAME,
.mode = FOPEN_MODE_RB
diff --git a/plat/arm/board/fvp/fvp_measured_boot.c b/plat/arm/board/fvp/fvp_measured_boot.c
index b145aae..5dcadba 100644
--- a/plat/arm/board/fvp/fvp_measured_boot.c
+++ b/plat/arm/board/fvp/fvp_measured_boot.c
@@ -15,12 +15,10 @@
{ BL32_EXTRA1_IMAGE_ID, BL32_EXTRA1_IMAGE_STRING, PCR_0 },
{ BL32_EXTRA2_IMAGE_ID, BL32_EXTRA2_IMAGE_STRING, PCR_0 },
{ BL33_IMAGE_ID, BL33_STRING, PCR_0 },
- { GPT_IMAGE_ID, GPT_IMAGE_STRING, PCR_0 },
{ HW_CONFIG_ID, HW_CONFIG_STRING, PCR_0 },
{ NT_FW_CONFIG_ID, NT_FW_CONFIG_STRING, PCR_0 },
{ SCP_BL2_IMAGE_ID, SCP_BL2_IMAGE_STRING, PCR_0 },
{ SOC_FW_CONFIG_ID, SOC_FW_CONFIG_STRING, PCR_0 },
- { STM32_IMAGE_ID, STM32_IMAGE_STRING, PCR_0 },
{ TOS_FW_CONFIG_ID, TOS_FW_CONFIG_STRING, PCR_0 },
{ INVALID_ID, NULL, (unsigned int)(-1) } /* Terminator */
};
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 8defcf8..8b25a54 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -115,7 +115,7 @@
#if USE_ROMLIB
#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000)
#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000)
-#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x6000)
+#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x5000)
#else
#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0)
#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0)
@@ -150,12 +150,18 @@
#endif /* RESET_TO_BL31 */
#ifndef __aarch64__
+#if RESET_TO_SP_MIN
+/* Size of Trusted SRAM - the first 4KB of shared memory */
+#define PLAT_ARM_MAX_BL32_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
+ ARM_SHARED_RAM_SIZE)
+#else
/*
* Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is
* calculated using the current SP_MIN PROGBITS debug size plus the sizes of
* BL2 and BL1-RW
*/
# define PLAT_ARM_MAX_BL32_SIZE UL(0x3B000)
+#endif /* RESET_TO_SP_MIN */
#endif
/*
@@ -185,8 +191,18 @@
#define MAX_IO_HANDLES 4
/* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE
-#define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+#if ARM_GPT_SUPPORT
+/*
+ * Offset of the FIP in the GPT image. BL1 component uses this option
+ * as it does not load the partition table to get the FIP base
+ * address. At sector 34 by default (i.e. after reserved sectors 0-33)
+ * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400
+ */
+#define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400
+#endif /* ARM_GPT_SUPPORT */
#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 6c09d72..3c70eed 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -131,10 +131,14 @@
lib/cpus/aarch64/neoverse_e1.S \
lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/cortex_a78_ae.S \
- lib/cpus/aarch64/cortex_klein.S \
- lib/cpus/aarch64/cortex_matterhorn.S \
+ lib/cpus/aarch64/cortex_a510.S \
+ lib/cpus/aarch64/cortex_a710.S \
+ lib/cpus/aarch64/cortex_makalu.S \
+ lib/cpus/aarch64/cortex_makalu_elp_arm.S \
+ lib/cpus/aarch64/cortex_demeter.S \
lib/cpus/aarch64/cortex_a65.S \
- lib/cpus/aarch64/cortex_a65ae.S
+ lib/cpus/aarch64/cortex_a65ae.S \
+ lib/cpus/aarch64/cortex_a78c.S
endif
# AArch64/AArch32 cores
FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
diff --git a/plat/arm/board/fvp_ve/include/platform_def.h b/plat/arm/board/fvp_ve/include/platform_def.h
index 3f2fcee..bd8ef6a 100644
--- a/plat/arm/board/fvp_ve/include/platform_def.h
+++ b/plat/arm/board/fvp_ve/include/platform_def.h
@@ -303,8 +303,8 @@
#define MAX_IO_HANDLES 4
/* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FIP_BASE V2M_FLASH1_BASE
-#define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH1_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE)
#define PLAT_ARM_NVM_BASE V2M_FLASH1_BASE
#define PLAT_ARM_NVM_SIZE (V2M_FLASH1_SIZE - V2M_FLASH_BLOCK_SIZE)
diff --git a/plat/arm/board/juno/fdts/juno_fw_config.dts b/plat/arm/board/juno/fdts/juno_fw_config.dts
index c0538f8..4b88efe 100644
--- a/plat/arm/board/juno/fdts/juno_fw_config.dts
+++ b/plat/arm/board/juno/fdts/juno_fw_config.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,5 +17,11 @@
max-size = <0x200>;
id = <TB_FW_CONFIG_ID>;
};
+
+ hw-config {
+ load-address = <0x0 0x82000000>;
+ max-size = <0x8000>;
+ id = <HW_CONFIG_ID>;
+ };
};
};
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index 91c3ae7..5299a7b 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -53,6 +53,14 @@
#define PLAT_ARM_DRAM2_BASE ULL(0x880000000)
#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
+#define PLAT_HW_CONFIG_DTB_BASE ULL(0x82000000)
+#define PLAT_HW_CONFIG_DTB_SIZE ULL(0x00008000) /* 32KB */
+
+#define ARM_DTB_DRAM_NS MAP_REGION_FLAT( \
+ PLAT_HW_CONFIG_DTB_BASE, \
+ PLAT_HW_CONFIG_DTB_SIZE, \
+ MT_MEMORY | MT_RO | MT_NS)
+
/* virtual address used by dynamic mem_protect for chunk_base */
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
@@ -108,7 +116,7 @@
#ifdef IMAGE_BL31
# define PLAT_ARM_MMAP_ENTRIES 7
-# define MAX_XLAT_TABLES 3
+# define MAX_XLAT_TABLES 5
#endif
#ifdef IMAGE_BL32
diff --git a/plat/arm/board/juno/juno_bl1_setup.c b/plat/arm/board/juno/juno_bl1_setup.c
index 2234055..a9d5cc3 100644
--- a/plat/arm/board/juno/juno_bl1_setup.c
+++ b/plat/arm/board/juno/juno_bl1_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -62,11 +62,11 @@
******************************************************************************/
bool plat_arm_bl1_fwu_needed(void)
{
- const int32_t *nv_flags_ptr = (const int32_t *)V2M_SYS_NVFLAGS_ADDR;
+ int32_t nv_flags = (int32_t)mmio_read_32(V2M_SYS_NVFLAGS_ADDR);
/* Check if TOC is invalid or watchdog reset happened. */
- return (!arm_io_is_toc_valid() || (((*nv_flags_ptr == -EAUTH) ||
- (*nv_flags_ptr == -ENOENT)) && is_watchdog_reset()));
+ return (!arm_io_is_toc_valid() || (((nv_flags == -EAUTH) ||
+ (nv_flags == -ENOENT)) && is_watchdog_reset()));
}
/*******************************************************************************
@@ -86,13 +86,11 @@
******************************************************************************/
__dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved)
{
- unsigned int *nv_flags_clr = (unsigned int *)
- (V2M_SYSREGS_BASE + V2M_SYS_NVFLAGSCLR);
- unsigned int *nv_flags_ptr = (unsigned int *)
- (V2M_SYSREGS_BASE + V2M_SYS_NVFLAGS);
+ uint32_t nv_flags = mmio_read_32(V2M_SYS_NVFLAGS_ADDR);
/* Clear the NV flags register. */
- *nv_flags_clr = *nv_flags_ptr;
+ mmio_write_32((V2M_SYSREGS_BASE + V2M_SYS_NVFLAGSCLR),
+ nv_flags);
/* Setup the watchdog to reset the system as soon as possible */
sp805_refresh(ARM_SP805_TWDG_BASE, 1U);
diff --git a/plat/arm/board/juno/juno_bl2_setup.c b/plat/arm/board/juno/juno_bl2_setup.c
index 95ef77c..849acd6 100644
--- a/plat/arm/board/juno/juno_bl2_setup.c
+++ b/plat/arm/board/juno/juno_bl2_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017,2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,6 +8,9 @@
#include <common/bl_common.h>
#include <common/desc_image_load.h>
+#include <lib/fconf/fconf.h>
+#include <lib/fconf/fconf_dyn_cfg_getter.h>
+
#include <plat/arm/common/plat_arm.h>
#if JUNO_AARCH32_EL3_RUNTIME
@@ -30,4 +33,41 @@
return err;
}
+
+#else
+
+/*******************************************************************************
+ * This function returns the list of executable images
+ ******************************************************************************/
+struct bl_params *plat_get_next_bl_params(void)
+{
+ struct bl_params *arm_bl_params = arm_get_next_bl_params();
+
+#if __aarch64__
+ const struct dyn_cfg_dtb_info_t *fw_config_info;
+ bl_mem_params_node_t *param_node;
+ uintptr_t fw_config_base = 0U;
+ entry_point_info_t *ep_info;
+
+ /* Get BL31 image node */
+ param_node = get_bl_mem_params_node(BL31_IMAGE_ID);
+ assert(param_node != NULL);
+
+ /* Get fw_config load address */
+ fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, FW_CONFIG_ID);
+ assert(fw_config_info != NULL);
+
+ fw_config_base = fw_config_info->config_addr;
+ assert(fw_config_base != 0U);
+
+ /*
+ * Get the entry point info of BL31 image and override
+ * arg1 of entry point info with fw_config base address
+ */
+ ep_info = ¶m_node->ep_info;
+ ep_info->args.arg1 = (uint32_t)fw_config_base;
+#endif /* __aarch64__ */
+
+ return arm_bl_params;
+}
#endif /* JUNO_AARCH32_EL3_RUNTIME */
diff --git a/plat/arm/board/juno/juno_bl31_setup.c b/plat/arm/board/juno/juno_bl31_setup.c
new file mode 100644
index 0000000..7a0a6d9
--- /dev/null
+++ b/plat/arm/board/juno/juno_bl31_setup.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <common/debug.h>
+#include <lib/fconf/fconf.h>
+#include <lib/fconf/fconf_dyn_cfg_getter.h>
+
+#include <plat/arm/common/plat_arm.h>
+
+void __init bl31_early_platform_setup2(u_register_t arg0,
+ u_register_t arg1, u_register_t arg2, u_register_t arg3)
+{
+ const struct dyn_cfg_dtb_info_t *soc_fw_config_info;
+
+ INFO("BL31 FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1);
+
+ /* Fill the properties struct with the info from the config dtb */
+ fconf_populate("FW_CONFIG", arg1);
+
+ soc_fw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, SOC_FW_CONFIG_ID);
+ if (soc_fw_config_info != NULL) {
+ arg1 = soc_fw_config_info->config_addr;
+ }
+
+ arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+
+ /*
+ * Initialize Interconnect for this cluster during cold boot.
+ * No need for locks as no other CPU is active.
+ */
+ plat_arm_interconnect_init();
+
+ /*
+ * Enable Interconnect coherency for the primary CPU's cluster.
+ * Earlier bootloader stages might already do this (e.g. Trusted
+ * Firmware's BL1 does it) but we can't assume so. There is no harm in
+ * executing this code twice anyway.
+ * Platform specific PSCI code will enable coherency for other
+ * clusters.
+ */
+ plat_arm_interconnect_enter_coherency();
+}
+
+void __init bl31_plat_arch_setup(void)
+{
+ arm_bl31_plat_arch_setup();
+
+ /* HW_CONFIG was also loaded by BL2 */
+ const struct dyn_cfg_dtb_info_t *hw_config_info;
+
+ hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID);
+ assert(hw_config_info != NULL);
+
+ fconf_populate("HW_CONFIG", hw_config_info->config_addr);
+}
diff --git a/plat/arm/board/juno/juno_common.c b/plat/arm/board/juno/juno_common.c
index da4918c..038f604 100644
--- a/plat/arm/board/juno/juno_common.c
+++ b/plat/arm/board/juno/juno_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -75,6 +75,7 @@
ARM_V2M_MAP_MEM_PROTECT,
#endif
SOC_CSS_MAP_DEVICE,
+ ARM_DTB_DRAM_NS,
{0}
};
#endif
@@ -117,9 +118,9 @@
int32_t plat_get_soc_version(void)
{
return (int32_t)
- ((ARM_SOC_IDENTIFICATION_CODE << ARM_SOC_IDENTIFICATION_SHIFT)
- | (ARM_SOC_CONTINUATION_CODE << ARM_SOC_CONTINUATION_SHIFT)
- | JUNO_SOC_ID);
+ (SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE,
+ ARM_SOC_IDENTIFICATION_CODE) |
+ (JUNO_SOC_ID & SOC_ID_IMPL_DEF_MASK));
}
/* Get SOC revision */
@@ -128,6 +129,6 @@
unsigned int sys_id;
sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
- return (int32_t)((sys_id >> V2M_SYS_ID_REV_SHIFT) &
- V2M_SYS_ID_REV_MASK);
+ return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) &
+ V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK);
}
diff --git a/plat/arm/board/juno/juno_decl.h b/plat/arm/board/juno/juno_decl.h
deleted file mode 100644
index 21e56c0..0000000
--- a/plat/arm/board/juno/juno_decl.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef JUNO_DECL_H
-#define JUNO_DECL_H
-
-bool juno_getentropy(uint64_t *buf);
-
-#endif /* JUNO_DECL_H */
diff --git a/plat/arm/board/juno/juno_err.c b/plat/arm/board/juno/juno_err.c
index 60699cc..02d751e 100644
--- a/plat/arm/board/juno/juno_err.c
+++ b/plat/arm/board/juno/juno_err.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,10 +16,8 @@
*/
void __dead2 plat_arm_error_handler(int err)
{
- uint32_t *flags_ptr = (uint32_t *)V2M_SYS_NVFLAGS_ADDR;
-
/* Propagate the err code in the NV-flags register */
- *flags_ptr = err;
+ mmio_write_32(V2M_SYS_NVFLAGS_ADDR, (uint32_t)err);
/* Setup the watchdog to reset the system as soon as possible */
sp805_refresh(ARM_SP805_TWDG_BASE, 1U);
diff --git a/plat/arm/board/juno/juno_security.c b/plat/arm/board/juno/juno_security.c
index 1e64c02..654a7f1 100644
--- a/plat/arm/board/juno/juno_security.c
+++ b/plat/arm/board/juno/juno_security.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -115,6 +115,14 @@
/* Drive SPIDEN LOW to disable invasive debug of secure state. */
mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_CLR,
1U << SPIDEN_INT_CLR_SHIFT);
+
+ /* Set internal drive selection for SPNIDEN. */
+ mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_SET,
+ 1U << SPNIDEN_SEL_SET_SHIFT);
+
+ /* Drive SPNIDEN LOW to disable non-invasive debug of secure state. */
+ mmio_write_32(SSC_REG_BASE + SSC_DBGCFG_CLR,
+ 1U << SPNIDEN_INT_CLR_SHIFT);
#endif
}
diff --git a/plat/arm/board/juno/juno_stack_protector.c b/plat/arm/board/juno/juno_stack_protector.c
index 8c51f57..3924af8 100644
--- a/plat/arm/board/juno/juno_stack_protector.c
+++ b/plat/arm/board/juno/juno_stack_protector.c
@@ -7,15 +7,14 @@
#include <arch_helpers.h>
#include <common/debug.h>
#include <lib/utils.h>
+#include <plat/common/plat_trng.h>
#include <platform_def.h>
-#include "juno_decl.h"
-
u_register_t plat_get_stack_protector_canary(void)
{
uint64_t entropy;
- if (!juno_getentropy(&entropy)) {
+ if (!plat_get_entropy(&entropy)) {
ERROR("Not enough entropy to initialize canary value\n");
panic();
}
diff --git a/plat/arm/board/juno/juno_trng.c b/plat/arm/board/juno/juno_trng.c
index b38e49f..09552a6 100644
--- a/plat/arm/board/juno/juno_trng.c
+++ b/plat/arm/board/juno/juno_trng.c
@@ -4,6 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <arm_acle.h>
#include <assert.h>
#include <stdbool.h>
#include <stdint.h>
@@ -13,7 +14,11 @@
#include <lib/utils_def.h>
#include <platform_def.h>
-#include "juno_decl.h"
+#include <lib/smccc.h>
+#include <services/trng_svc.h>
+#include <smccc_helpers.h>
+
+#include <plat/common/platform.h>
#define NSAMPLE_CLOCKS 1 /* min 1 cycle, max 231 cycles */
#define NRETRIES 5
@@ -35,18 +40,24 @@
return false; /* No output data available. */
}
+DEFINE_SVC_UUID2(_plat_trng_uuid,
+ 0x23523c58, 0x7448, 0x4083, 0x9d, 0x16,
+ 0xe3, 0xfa, 0xb9, 0xf1, 0x73, 0xbc
+);
+uuid_t plat_trng_uuid;
+
+static uint32_t crc_value = ~0U;
+
/*
- * This function fills `buf` with 8 bytes of entropy.
- * It uses the Trusted Entropy Source peripheral on Juno.
- * Returns 'true' when the buffer has been filled with entropy
- * successfully, or 'false' otherwise.
+ * Uses the Trusted Entropy Source peripheral on Juno to return 8 bytes of
+ * entropy. Returns 'true' when done successfully, 'false' otherwise.
*/
-bool juno_getentropy(uint64_t *buf)
+bool plat_get_entropy(uint64_t *out)
{
uint64_t ret;
- assert(buf);
- assert(!check_uptr_overflow((uintptr_t)buf, sizeof(*buf)));
+ assert(out);
+ assert(!check_uptr_overflow((uintptr_t)out, sizeof(*out)));
if (!juno_trng_initialized) {
/* Disable interrupt mode. */
@@ -69,14 +80,14 @@
return false;
}
- /* XOR each two 32-bit registers together, combine the pairs */
- ret = mmio_read_32(TRNG_BASE + 0);
- ret ^= mmio_read_32(TRNG_BASE + 4);
- ret <<= 32;
+ /* CRC each two 32-bit registers together, combine the pairs */
+ crc_value = __crc32w(crc_value, mmio_read_32(TRNG_BASE + 0));
+ crc_value = __crc32w(crc_value, mmio_read_32(TRNG_BASE + 4));
+ ret = (uint64_t)crc_value << 32;
- ret |= mmio_read_32(TRNG_BASE + 8);
- ret ^= mmio_read_32(TRNG_BASE + 12);
- *buf = ret;
+ crc_value = __crc32w(crc_value, mmio_read_32(TRNG_BASE + 8));
+ crc_value = __crc32w(crc_value, mmio_read_32(TRNG_BASE + 12));
+ *out = ret | crc_value;
/* Acknowledge current cycle, clear output registers. */
mmio_write_32(TRNG_BASE + TRNG_STATUS, 1);
@@ -85,3 +96,13 @@
return true;
}
+
+void plat_entropy_setup(void)
+{
+ uint64_t dummy;
+
+ plat_trng_uuid = _plat_trng_uuid;
+
+ /* Initialise the entropy source and trigger RNG generation */
+ plat_get_entropy(&dummy);
+}
diff --git a/plat/arm/board/juno/platform.mk b/plat/arm/board/juno/platform.mk
index 61cfb61..92fbf35 100644
--- a/plat/arm/board/juno/platform.mk
+++ b/plat/arm/board/juno/platform.mk
@@ -44,6 +44,8 @@
$(eval $(call add_define,JUNO_TZMP1))
endif
+TRNG_SUPPORT := 1
+
ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1)
# Include BL32 in FIP
NEED_BL32 := yes
@@ -81,6 +83,10 @@
lib/cpus/aarch64/cortex_a57.S \
lib/cpus/aarch64/cortex_a72.S \
lib/utils/mem_region.c \
+ common/fdt_wrappers.c \
+ lib/fconf/fconf.c \
+ lib/fconf/fconf_dyn_cfg_getter.c \
+ plat/arm/board/juno/juno_bl31_setup.c \
plat/arm/board/juno/juno_pm.c \
plat/arm/board/juno/juno_topology.c \
plat/arm/common/arm_nor_psci_mem_protect.c \
@@ -164,17 +170,27 @@
endif
endif
+BL1_CPPFLAGS += -march=armv8-a+crc
+BL2_CPPFLAGS += -march=armv8-a+crc
+BL2U_CPPFLAGS += -march=armv8-a+crc
+BL31_CPPFLAGS += -march=armv8-a+crc
+BL32_CPPFLAGS += -march=armv8-a+crc
+
# Add the FDT_SOURCES and options for Dynamic Config
FDT_SOURCES += plat/arm/board/juno/fdts/${PLAT}_fw_config.dts \
- plat/arm/board/juno/fdts/${PLAT}_tb_fw_config.dts
+ plat/arm/board/juno/fdts/${PLAT}_tb_fw_config.dts \
+ fdts/${PLAT}.dts
FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
+HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb
# Add the FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
# Add the TB_FW_CONFIG to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
+# Add the HW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${HW_CONFIG},--hw-config,${HW_CONFIG}))
include plat/arm/board/common/board_common.mk
include plat/arm/common/arm_common.mk
diff --git a/plat/arm/board/rde1edge/include/platform_def.h b/plat/arm/board/rde1edge/include/platform_def.h
index c39fe2b..a9b30a4 100644
--- a/plat/arm/board/rde1edge/include/platform_def.h
+++ b/plat/arm/board/rde1edge/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,6 +9,7 @@
#include <lib/utils_def.h>
+#include <sgi_sdei.h>
#include <sgi_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(2)
diff --git a/plat/arm/board/rde1edge/platform.mk b/plat/arm/board/rde1edge/platform.mk
index 53074f4..0f9dd49 100644
--- a/plat/arm/board/rde1edge/platform.mk
+++ b/plat/arm/board/rde1edge/platform.mk
@@ -58,4 +58,9 @@
${CSS_SGI_CHIP_COUNT}.")
endif
+ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
+ $(error "CSS_SGI_PLATFORM_VARIANT for RD-E1-Edge should always be 0, \
+ currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
+endif
+
override CTX_INCLUDE_AARCH32_REGS := 0
diff --git a/plat/arm/board/rde1edge/rde1edge_security.c b/plat/arm/board/rde1edge/rde1edge_security.c
index 2123e09..35f81d1 100644
--- a/plat/arm/board/rde1edge/rde1edge_security.c
+++ b/plat/arm/board/rde1edge/rde1edge_security.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,7 +7,7 @@
#include <platform_def.h>
#include <common/debug.h>
-#include <drivers/arm/tzc_dmc620.h>
+#include <sgi_dmc620_tzc_regions.h>
uintptr_t rde1edge_dmc_base[] = {
RDE1EDGE_DMC620_BASE0,
@@ -20,11 +20,7 @@
};
static const tzc_dmc620_acc_addr_data_t rde1edge_acc_addr_data[] = {
- {
- .region_base = ARM_AP_TZC_DRAM1_BASE,
- .region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
- .sec_attr = TZC_DMC620_REGION_S_RDWR
- }
+ CSS_SGI_DMC620_TZC_REGIONS_DEF
};
static const tzc_dmc620_config_data_t rde1edge_plat_config_data = {
diff --git a/plat/arm/board/rdn1edge/include/platform_def.h b/plat/arm/board/rdn1edge/include/platform_def.h
index b167c46..a61b0d5 100644
--- a/plat/arm/board/rdn1edge/include/platform_def.h
+++ b/plat/arm/board/rdn1edge/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,6 +9,7 @@
#include <lib/utils_def.h>
+#include <sgi_sdei.h>
#include <sgi_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(2)
diff --git a/plat/arm/board/rdn1edge/platform.mk b/plat/arm/board/rdn1edge/platform.mk
index d65854f..22ab312 100644
--- a/plat/arm/board/rdn1edge/platform.mk
+++ b/plat/arm/board/rdn1edge/platform.mk
@@ -65,4 +65,9 @@
set to ${CSS_SGI_CHIP_COUNT}.")
endif
+ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
+ $(error "CSS_SGI_PLATFORM_VARIANT for RD-N1-Edge should always be 0, \
+ currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
+endif
+
override CTX_INCLUDE_AARCH32_REGS := 0
diff --git a/plat/arm/board/rdn1edge/rdn1edge_security.c b/plat/arm/board/rdn1edge/rdn1edge_security.c
index ffa8935..4943532 100644
--- a/plat/arm/board/rdn1edge/rdn1edge_security.c
+++ b/plat/arm/board/rdn1edge/rdn1edge_security.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,7 +7,7 @@
#include <platform_def.h>
#include <common/debug.h>
-#include <drivers/arm/tzc_dmc620.h>
+#include <sgi_dmc620_tzc_regions.h>
uintptr_t rdn1edge_dmc_base[] = {
RDN1EDGE_DMC620_BASE0,
@@ -20,11 +20,7 @@
};
static const tzc_dmc620_acc_addr_data_t rdn1edge_acc_addr_data[] = {
- {
- .region_base = ARM_AP_TZC_DRAM1_BASE,
- .region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
- .sec_attr = TZC_DMC620_REGION_S_RDWR
- }
+ CSS_SGI_DMC620_TZC_REGIONS_DEF
};
static const tzc_dmc620_config_data_t rdn1edge_plat_config_data = {
diff --git a/plat/arm/board/rdn2/include/platform_def.h b/plat/arm/board/rdn2/include/platform_def.h
index 3f753f7..194814f 100644
--- a/plat/arm/board/rdn2/include/platform_def.h
+++ b/plat/arm/board/rdn2/include/platform_def.h
@@ -11,7 +11,12 @@
#include <sgi_soc_platform_def_v2.h>
+#if (CSS_SGI_PLATFORM_VARIANT == 1)
+#define PLAT_ARM_CLUSTER_COUNT U(8)
+#else
#define PLAT_ARM_CLUSTER_COUNT U(16)
+#endif
+
#define CSS_SGI_MAX_CPUS_PER_CLUSTER U(1)
#define CSS_SGI_MAX_PE_PER_CPU U(1)
@@ -26,7 +31,12 @@
#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
#define TZC400_OFFSET UL(0x1000000)
+
+#if (CSS_SGI_PLATFORM_VARIANT == 1)
+#define TZC400_COUNT U(2)
+#else
#define TZC400_COUNT U(8)
+#endif
#define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \
(n * TZC400_OFFSET))
@@ -34,6 +44,8 @@
#define TZC_NSAID_ALL_AP U(0)
#define TZC_NSAID_PCI U(1)
#define TZC_NSAID_HDLCD0 U(2)
+#define TZC_NSAID_DMA U(5)
+#define TZC_NSAID_DMA2 U(8)
#define TZC_NSAID_CLCD U(7)
#define TZC_NSAID_AP U(9)
#define TZC_NSAID_VIRTIO U(15)
@@ -42,6 +54,8 @@
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \
+ (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DMA)) | \
+ (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DMA2)) | \
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
@@ -60,6 +74,11 @@
/* GIC related constants */
#define PLAT_ARM_GICD_BASE UL(0x30000000)
#define PLAT_ARM_GICC_BASE UL(0x2C000000)
+
+#if (CSS_SGI_PLATFORM_VARIANT == 1)
+#define PLAT_ARM_GICR_BASE UL(0x30100000)
+#else
#define PLAT_ARM_GICR_BASE UL(0x301C0000)
+#endif
#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/rdn2/platform.mk b/plat/arm/board/rdn2/platform.mk
index 03771dc..794f897 100644
--- a/plat/arm/board/rdn2/platform.mk
+++ b/plat/arm/board/rdn2/platform.mk
@@ -58,3 +58,10 @@
override CTX_INCLUDE_AARCH32_REGS := 0
override ENABLE_AMU := 1
+
+RD_N2_VARIANTS := 0 1
+ifneq ($(CSS_SGI_PLATFORM_VARIANT),\
+ $(filter $(CSS_SGI_PLATFORM_VARIANT),$(RD_N2_VARIANTS)))
+ $(error "CSS_SGI_PLATFORM_VARIANT for RD-N2 should be 0 or 1, currently set \
+ to ${CSS_SGI_PLATFORM_VARIANT}.")
+endif
diff --git a/plat/arm/board/rdn2/rdn2_topology.c b/plat/arm/board/rdn2/rdn2_topology.c
index 5c2e287..cad6c37 100644
--- a/plat/arm/board/rdn2/rdn2_topology.c
+++ b/plat/arm/board/rdn2/rdn2_topology.c
@@ -20,6 +20,7 @@
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
+#if (CSS_SGI_PLATFORM_VARIANT == 0)
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
@@ -28,6 +29,7 @@
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
CSS_SGI_MAX_CPUS_PER_CLUSTER,
+#endif
};
/*******************************************************************************
@@ -51,6 +53,7 @@
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
+#if (CSS_SGI_PLATFORM_VARIANT == 0)
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
@@ -59,4 +62,5 @@
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xE)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF)),
+#endif
};
diff --git a/plat/arm/board/rdv1/platform.mk b/plat/arm/board/rdv1/platform.mk
index 2ffd139..1ae85de 100644
--- a/plat/arm/board/rdv1/platform.mk
+++ b/plat/arm/board/rdv1/platform.mk
@@ -58,3 +58,8 @@
override CTX_INCLUDE_AARCH32_REGS := 0
override ENABLE_AMU := 1
+
+ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
+ $(error "CSS_SGI_PLATFORM_VARIANT for RD-V1 should always be 0, \
+ currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
+endif
diff --git a/plat/arm/board/rdv1mc/include/platform_def.h b/plat/arm/board/rdv1mc/include/platform_def.h
index 112b210..12ce806 100644
--- a/plat/arm/board/rdv1mc/include/platform_def.h
+++ b/plat/arm/board/rdv1mc/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -20,6 +20,29 @@
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
+/* TZC Related Constants */
+#define PLAT_ARM_TZC_BASE UL(0x21830000)
+#define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \
+ (n * TZC400_OFFSET))
+#define TZC400_OFFSET UL(0x1000000)
+#define TZC400_COUNT U(8)
+#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
+
+#define TZC_NSAID_ALL_AP U(0)
+#define TZC_NSAID_PCI U(1)
+#define TZC_NSAID_HDLCD0 U(2)
+#define TZC_NSAID_CLCD U(7)
+#define TZC_NSAID_AP U(9)
+#define TZC_NSAID_VIRTIO U(15)
+
+#define PLAT_ARM_TZC_NS_DEV_ACCESS \
+ (TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \
+ (TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \
+ (TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \
+ (TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \
+ (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \
+ (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
+
/* Virtual address used by dynamic mem_protect for chunk_base */
#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000)
diff --git a/plat/arm/board/rdv1mc/platform.mk b/plat/arm/board/rdv1mc/platform.mk
index 5072841..df0b09a 100644
--- a/plat/arm/board/rdv1mc/platform.mk
+++ b/plat/arm/board/rdv1mc/platform.mk
@@ -1,4 +1,4 @@
-# Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -23,6 +23,8 @@
BL2_SOURCES += ${RDV1MC_BASE}/rdv1mc_plat.c \
${RDV1MC_BASE}/rdv1mc_security.c \
${RDV1MC_BASE}/rdv1mc_err.c \
+ drivers/arm/tzc/tzc400.c \
+ plat/arm/common/arm_tzc400.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
@@ -66,3 +68,9 @@
$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
override CTX_INCLUDE_AARCH32_REGS := 0
+override ENABLE_AMU := 1
+
+ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
+ $(error "CSS_SGI_PLATFORM_VARIANT for RD-V1-MC should always be 0, \
+ currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
+endif
diff --git a/plat/arm/board/rdv1mc/rdv1mc_security.c b/plat/arm/board/rdv1mc/rdv1mc_security.c
index 541f800..adc0bf8 100644
--- a/plat/arm/board/rdv1mc/rdv1mc_security.c
+++ b/plat/arm/board/rdv1mc/rdv1mc_security.c
@@ -1,10 +1,64 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <common/debug.h>
+#include <plat/arm/common/plat_arm.h>
+#include <platform_def.h>
+
+/* TZC memory regions for the first chip */
+static const arm_tzc_regions_info_t tzc_regions[] = {
+ ARM_TZC_REGIONS_DEF,
+ {}
+};
+
+#if CSS_SGI_CHIP_COUNT > 1
+static const arm_tzc_regions_info_t tzc_regions_mc[][CSS_SGI_CHIP_COUNT - 1] = {
+ {
+ /* TZC memory regions for second chip */
+ SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(1),
+ {}
+ },
+#if CSS_SGI_CHIP_COUNT > 2
+ {
+ /* TZC memory regions for third chip */
+ SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(2),
+ {}
+ },
+#endif
+#if CSS_SGI_CHIP_COUNT > 3
+ {
+ /* TZC memory regions for fourth chip */
+ SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(3),
+ {}
+ },
+#endif
+};
+#endif /* CSS_SGI_CHIP_COUNT */
+
/* Initialize the secure environment */
void plat_arm_security_setup(void)
{
+ unsigned int i;
+
+ INFO("Configuring TrustZone Controller for Chip 0\n");
+
+ for (i = 0; i < TZC400_COUNT; i++) {
+ arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
+ }
+
+#if CSS_SGI_CHIP_COUNT > 1
+ unsigned int j;
+
+ for (i = 1; i < CSS_SGI_CHIP_COUNT; i++) {
+ INFO("Configuring TrustZone Controller for Chip %u\n", i);
+
+ for (j = 0; j < TZC400_COUNT; j++) {
+ arm_tzc400_setup(CSS_SGI_REMOTE_CHIP_MEM_OFFSET(i)
+ + TZC400_BASE(j), tzc_regions_mc[i-1]);
+ }
+ }
+#endif
}
diff --git a/plat/arm/board/sgi575/include/platform_def.h b/plat/arm/board/sgi575/include/platform_def.h
index c929334..72d5f7c 100644
--- a/plat/arm/board/sgi575/include/platform_def.h
+++ b/plat/arm/board/sgi575/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,6 +9,7 @@
#include <lib/utils_def.h>
+#include <sgi_sdei.h>
#include <sgi_soc_platform_def.h>
#define PLAT_ARM_CLUSTER_COUNT U(2)
diff --git a/plat/arm/board/sgi575/platform.mk b/plat/arm/board/sgi575/platform.mk
index 89abcfe..0761b77 100644
--- a/plat/arm/board/sgi575/platform.mk
+++ b/plat/arm/board/sgi575/platform.mk
@@ -58,3 +58,8 @@
$(error "Chip count for SGI575 should be 1, currently set to \
${CSS_SGI_CHIP_COUNT}.")
endif
+
+ifneq ($(CSS_SGI_PLATFORM_VARIANT),0)
+ $(error "CSS_SGI_PLATFORM_VARIANT for SGI575 should always be 0,\
+ currently set to ${CSS_SGI_PLATFORM_VARIANT}.")
+endif
diff --git a/plat/arm/board/sgi575/sgi575_security.c b/plat/arm/board/sgi575/sgi575_security.c
index 440f18d..17d07d1 100644
--- a/plat/arm/board/sgi575/sgi575_security.c
+++ b/plat/arm/board/sgi575/sgi575_security.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,8 +7,7 @@
#include <platform_def.h>
#include <common/debug.h>
-#include <drivers/arm/tzc_dmc620.h>
-#include <plat/arm/common/plat_arm.h>
+#include <sgi_dmc620_tzc_regions.h>
uintptr_t sgi575_dmc_base[] = {
SGI575_DMC620_BASE0,
@@ -21,11 +20,7 @@
};
static const tzc_dmc620_acc_addr_data_t sgi575_acc_addr_data[] = {
- {
- .region_base = ARM_AP_TZC_DRAM1_BASE,
- .region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
- .sec_attr = TZC_DMC620_REGION_S_RDWR
- }
+ CSS_SGI_DMC620_TZC_REGIONS_DEF
};
static const tzc_dmc620_config_data_t sgi575_plat_config_data = {
diff --git a/plat/arm/board/sgm775/platform.mk b/plat/arm/board/sgm775/platform.mk
index a649939..f8df1a7 100644
--- a/plat/arm/board/sgm775/platform.mk
+++ b/plat/arm/board/sgm775/platform.mk
@@ -4,6 +4,8 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+$(warning Platform ${PLAT} is deprecated. Some of the features might not work as expected)
+
include plat/arm/css/sgm/sgm-common.mk
SGM775_BASE= plat/arm/board/sgm775
diff --git a/plat/arm/board/tc0/fdts/tc0_fw_config.dts b/plat/arm/board/tc/fdts/tc_fw_config.dts
similarity index 100%
rename from plat/arm/board/tc0/fdts/tc0_fw_config.dts
rename to plat/arm/board/tc/fdts/tc_fw_config.dts
diff --git a/plat/arm/board/tc/fdts/tc_spmc_manifest.dts b/plat/arm/board/tc/fdts/tc_spmc_manifest.dts
new file mode 100644
index 0000000..a8592f6
--- /dev/null
+++ b/plat/arm/board/tc/fdts/tc_spmc_manifest.dts
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/dts-v1/;
+
+/ {
+ compatible = "arm,ffa-core-manifest-1.0";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ attribute {
+ spmc_id = <0x8000>;
+ maj_ver = <0x1>;
+ min_ver = <0x1>;
+ exec_state = <0x0>;
+ load_address = <0x0 0xfd000000>;
+ entrypoint = <0x0 0xfd000000>;
+ binary_size = <0x80000>;
+ };
+
+ hypervisor {
+ compatible = "hafnium,hafnium";
+ vm1 {
+ is_ffa_partition;
+ debug_name = "cactus-primary";
+ load_address = <0xfe000000>;
+ vcpu_count = <8>;
+ mem_size = <1048576>;
+ };
+ vm2 {
+ is_ffa_partition;
+ debug_name = "cactus-secondary";
+ load_address = <0xfe100000>;
+ vcpu_count = <8>;
+ mem_size = <1048576>;
+ };
+ vm3 {
+ is_ffa_partition;
+ debug_name = "cactus-tertiary";
+ load_address = <0xfe200000>;
+ vcpu_count = <1>;
+ mem_size = <1048576>;
+ };
+ };
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ CPU0:cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ /*
+ * SPMC (Hafnium) requires secondary cpu nodes are declared in
+ * descending order
+ */
+ CPU7:cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x700>;
+ enable-method = "psci";
+ };
+
+ CPU6:cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x600>;
+ enable-method = "psci";
+ };
+
+ CPU5:cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ };
+
+ CPU4:cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ };
+
+ CPU3:cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ };
+
+ CPU2:cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ };
+
+ CPU1:cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ };
+ };
+
+ /* 32MB of TC_TZC_DRAM1_BASE */
+ memory@fd000000 {
+ device_type = "memory";
+ reg = <0x0 0xfd000000 0x2000000>;
+ };
+};
diff --git a/plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts b/plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts
new file mode 100644
index 0000000..34b4e74
--- /dev/null
+++ b/plat/arm/board/tc/fdts/tc_spmc_optee_sp_manifest.dts
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/dts-v1/;
+
+/ {
+ compatible = "arm,ffa-core-manifest-1.0";
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ attribute {
+ spmc_id = <0x8000>;
+ maj_ver = <0x1>;
+ min_ver = <0x1>;
+ exec_state = <0x0>;
+ load_address = <0x0 0xfd000000>;
+ entrypoint = <0x0 0xfd000000>;
+ binary_size = <0x80000>;
+ };
+
+ hypervisor {
+ compatible = "hafnium,hafnium";
+ vm1 {
+ is_ffa_partition;
+ debug_name = "op-tee";
+ load_address = <0xfd280000>;
+ vcpu_count = <8>;
+#ifdef TS_SP_FW_CONFIG
+ mem_size = <26738688>; /* 25MB TZC DRAM */
+#else
+ mem_size = <30928896>; /* 29MB TZC DRAM */
+#endif
+ };
+#ifdef TS_SP_FW_CONFIG
+ vm2 {
+ is_ffa_partition;
+ debug_name = "secure-storage";
+ load_address = <0xfee00000>;
+ vcpu_count = <1>;
+ mem_size = <2097152>; /* 2MB TZC DRAM */
+ };
+ vm3 {
+ is_ffa_partition;
+ debug_name = "crypto";
+ load_address = <0xfec00000>;
+ vcpu_count = <1>;
+ mem_size = <2097152>; /* 2MB TZC DRAM */
+ };
+#endif
+ };
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ CPU0:cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ /*
+ * SPMC (Hafnium) requires secondary cpu nodes are declared in
+ * descending order
+ */
+ CPU7:cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x700>;
+ enable-method = "psci";
+ };
+
+ CPU6:cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x600>;
+ enable-method = "psci";
+ };
+
+ CPU5:cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ };
+
+ CPU4:cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ };
+
+ CPU3:cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ };
+
+ CPU2:cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ };
+
+ CPU1:cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ };
+ };
+
+ /* 32MB of TC_TZC_DRAM1_BASE */
+ memory@fd000000 {
+ device_type = "memory";
+ reg = <0x0 0xfd000000 0x2000000>;
+ };
+};
diff --git a/plat/arm/board/tc/fdts/tc_tb_fw_config.dts b/plat/arm/board/tc/fdts/tc_tb_fw_config.dts
new file mode 100644
index 0000000..28ed7ae
--- /dev/null
+++ b/plat/arm/board/tc/fdts/tc_tb_fw_config.dts
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+/ {
+ tb_fw-config {
+ compatible = "arm,tb_fw";
+
+ /* Disable authentication for development */
+ disable_auth = <0x0>;
+ /*
+ * The following two entries are placeholders for Mbed TLS
+ * heap information. The default values don't matter since
+ * they will be overwritten by BL1.
+ * In case of having shared Mbed TLS heap between BL1 and BL2,
+ * BL1 will populate these two properties with the respective
+ * info about the shared heap. This info will be available for
+ * BL2 in order to locate and re-use the heap.
+ */
+ mbedtls_heap_addr = <0x0 0x0>;
+ mbedtls_heap_size = <0x0>;
+ };
+
+ secure-partitions {
+ compatible = "arm,sp";
+#ifdef TS_SP_FW_CONFIG
+ secure-storage {
+ uuid = "dc1eef48-b17a-4ccf-ac8b-dfcff7711b14";
+ load-address = <0xfee00000>;
+ };
+ crypto {
+ uuid = "d9df52d5-16a2-4bb2-9aa4-d26d3b84e8c0";
+ load-address = <0xfec00000>;
+ };
+#endif
+#if OPTEE_SP_FW_CONFIG
+ op-tee {
+ uuid = "486178e0-e7f8-11e3-bc5e-0002a5d5c51b";
+ load-address = <0xfd280000>;
+ };
+#else
+ cactus-primary {
+ uuid = "b4b5671e-4a90-4fe1-b81f-fb13dae1dacb";
+ load-address = <0xfe000000>;
+ owner = "SiP";
+ };
+
+ cactus-secondary {
+ uuid = "d1582309-f023-47b9-827c-4464f5578fc8";
+ load-address = <0xfe100000>;
+ owner = "Plat";
+ };
+
+ cactus-tertiary {
+ uuid = "79b55c73-1d8c-44b9-8593-61e1770ad8d2";
+ load-address = <0xfe200000>;
+ };
+#endif
+ };
+};
diff --git a/plat/arm/board/tc0/include/plat_macros.S b/plat/arm/board/tc/include/plat_macros.S
similarity index 100%
rename from plat/arm/board/tc0/include/plat_macros.S
rename to plat/arm/board/tc/include/plat_macros.S
diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h
new file mode 100644
index 0000000..c8edd2f
--- /dev/null
+++ b/plat/arm/board/tc/include/platform_def.h
@@ -0,0 +1,266 @@
+/*
+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <lib/utils_def.h>
+#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <plat/arm/board/common/board_css_def.h>
+#include <plat/arm/board/common/v2m_def.h>
+#include <plat/arm/common/arm_def.h>
+#include <plat/arm/common/arm_spm_def.h>
+#include <plat/arm/css/common/css_def.h>
+#include <plat/arm/soc/common/soc_css_def.h>
+#include <plat/common/common_def.h>
+
+#define PLATFORM_CORE_COUNT 8
+
+#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */
+
+/*
+ * The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC,
+ * its base is ARM_AP_TZC_DRAM1_BASE.
+ *
+ * Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for:
+ * - BL32_BASE when SPD_spmd is enabled
+ * - Region to load Trusted OS
+ */
+#define TC_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \
+ TC_TZC_DRAM1_SIZE)
+#define TC_TZC_DRAM1_SIZE UL(0x02000000) /* 32 MB */
+#define TC_TZC_DRAM1_END (TC_TZC_DRAM1_BASE + \
+ TC_TZC_DRAM1_SIZE - 1)
+
+#define TC_NS_DRAM1_BASE ARM_DRAM1_BASE
+#define TC_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
+ ARM_TZC_DRAM1_SIZE - \
+ TC_TZC_DRAM1_SIZE)
+#define TC_NS_DRAM1_END (TC_NS_DRAM1_BASE + \
+ TC_NS_DRAM1_SIZE - 1)
+
+/*
+ * Mappings for TC DRAM1 (non-secure) and TC TZC DRAM1 (secure)
+ */
+#define TC_MAP_NS_DRAM1 MAP_REGION_FLAT( \
+ TC_NS_DRAM1_BASE, \
+ TC_NS_DRAM1_SIZE, \
+ MT_MEMORY | MT_RW | MT_NS)
+
+
+#define TC_MAP_TZC_DRAM1 MAP_REGION_FLAT( \
+ TC_TZC_DRAM1_BASE, \
+ TC_TZC_DRAM1_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+/*
+ * Max size of SPMC is 2MB for tc. With SPMD enabled this value corresponds to
+ * max size of BL32 image.
+ */
+#if defined(SPD_spmd)
+#define PLAT_ARM_SPMC_BASE TC_TZC_DRAM1_BASE
+#define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */
+#endif
+
+/*
+ * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
+ * plat_arm_mmap array defined for each BL stage.
+ */
+#if defined(IMAGE_BL31)
+# if SPM_MM
+# define PLAT_ARM_MMAP_ENTRIES 9
+# define MAX_XLAT_TABLES 7
+# define PLAT_SP_IMAGE_MMAP_REGIONS 7
+# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10
+# else
+# define PLAT_ARM_MMAP_ENTRIES 8
+# define MAX_XLAT_TABLES 8
+# endif
+#elif defined(IMAGE_BL32)
+# define PLAT_ARM_MMAP_ENTRIES 8
+# define MAX_XLAT_TABLES 5
+#elif !USE_ROMLIB
+# define PLAT_ARM_MMAP_ENTRIES 11
+# define MAX_XLAT_TABLES 7
+#else
+# define PLAT_ARM_MMAP_ENTRIES 12
+# define MAX_XLAT_TABLES 6
+#endif
+
+/*
+ * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
+ * plus a little space for growth.
+ */
+#define PLAT_ARM_MAX_BL1_RW_SIZE 0xC000
+
+/*
+ * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
+ */
+
+#if USE_ROMLIB
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000
+#else
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0
+#endif
+
+/*
+ * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
+ * little space for growth.
+ */
+#if TRUSTED_BOARD_BOOT
+# define PLAT_ARM_MAX_BL2_SIZE 0x20000
+#else
+# define PLAT_ARM_MAX_BL2_SIZE 0x14000
+#endif
+
+/*
+ * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
+ * calculated using the current BL31 PROGBITS debug size plus the sizes of
+ * BL2 and BL1-RW
+ */
+#define PLAT_ARM_MAX_BL31_SIZE 0x3B000
+
+/*
+ * Size of cacheable stacks
+ */
+#if defined(IMAGE_BL1)
+# if TRUSTED_BOARD_BOOT
+# define PLATFORM_STACK_SIZE 0x1000
+# else
+# define PLATFORM_STACK_SIZE 0x440
+# endif
+#elif defined(IMAGE_BL2)
+# if TRUSTED_BOARD_BOOT
+# define PLATFORM_STACK_SIZE 0x1000
+# else
+# define PLATFORM_STACK_SIZE 0x400
+# endif
+#elif defined(IMAGE_BL2U)
+# define PLATFORM_STACK_SIZE 0x400
+#elif defined(IMAGE_BL31)
+# if SPM_MM
+# define PLATFORM_STACK_SIZE 0x500
+# else
+# define PLATFORM_STACK_SIZE 0x400
+# endif
+#elif defined(IMAGE_BL32)
+# define PLATFORM_STACK_SIZE 0x440
+#endif
+
+
+#define TC_DEVICE_BASE 0x21000000
+#define TC_DEVICE_SIZE 0x5f000000
+
+// TC_MAP_DEVICE covers different peripherals
+// available to the platform
+#define TC_MAP_DEVICE MAP_REGION_FLAT( \
+ TC_DEVICE_BASE, \
+ TC_DEVICE_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+
+#define TC_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
+ V2M_FLASH0_SIZE, \
+ MT_DEVICE | MT_RO | MT_SECURE)
+
+#define PLAT_ARM_NSTIMER_FRAME_ID 0
+
+#define PLAT_ARM_TRUSTED_ROM_BASE 0x0
+#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 /* 512KB */
+
+#define PLAT_ARM_NSRAM_BASE 0x06000000
+#define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */
+
+#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
+#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
+
+#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
+#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
+
+#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
+ PLAT_SP_IMAGE_NS_BUF_SIZE)
+
+/*******************************************************************************
+ * Memprotect definitions
+ ******************************************************************************/
+/* PSCI memory protect definitions:
+ * This variable is stored in a non-secure flash because some ARM reference
+ * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT
+ * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions.
+ */
+#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
+ V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+/*Secure Watchdog Constants */
+#define SBSA_SECURE_WDOG_BASE UL(0x2A480000)
+#define SBSA_SECURE_WDOG_TIMEOUT UL(100)
+
+#define PLAT_ARM_SCMI_CHANNEL_COUNT 1
+
+#define PLAT_ARM_CLUSTER_COUNT U(1)
+#define PLAT_MAX_CPUS_PER_CLUSTER U(8)
+#define PLAT_MAX_PE_PER_CPU U(1)
+
+#define PLAT_CSS_MHU_BASE UL(0x45400000)
+#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
+
+#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
+#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
+
+/*
+ * Physical and virtual address space limits for MMU in AARCH64
+ */
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
+
+/* GIC related constants */
+#define PLAT_ARM_GICD_BASE UL(0x30000000)
+#define PLAT_ARM_GICC_BASE UL(0x2C000000)
+#define PLAT_ARM_GICR_BASE UL(0x30080000)
+
+/*
+ * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current
+ * SCP_BL2 size plus a little space for growth.
+ */
+#define PLAT_CSS_MAX_SCP_BL2_SIZE 0x20000
+
+/*
+ * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current
+ * SCP_BL2U size plus a little space for growth.
+ */
+#define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x20000
+
+/* TZC Related Constants */
+#define PLAT_ARM_TZC_BASE UL(0x25000000)
+#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
+
+#define TZC400_OFFSET UL(0x1000000)
+#define TZC400_COUNT 4
+
+#define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \
+ (n * TZC400_OFFSET))
+
+#define TZC_NSAID_DEFAULT U(0)
+
+#define PLAT_ARM_TZC_NS_DEV_ACCESS \
+ (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT))
+
+/*
+ * The first region below, TC_TZC_DRAM1_BASE (0xfd000000) to
+ * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 48 MB of DRAM as
+ * secure. The second region gives non secure access to rest of DRAM.
+ */
+#define TC_TZC_REGIONS_DEF \
+ {TC_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END, \
+ TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS}, \
+ {TC_NS_DRAM1_BASE, TC_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
+ PLAT_ARM_TZC_NS_DEV_ACCESS}
+
+/* virtual address used by dynamic mem_protect for chunk_base */
+#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/tc/include/tc_helpers.S b/plat/arm/board/tc/include/tc_helpers.S
new file mode 100644
index 0000000..5f54856
--- /dev/null
+++ b/plat/arm/board/tc/include/tc_helpers.S
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <platform_def.h>
+#include <cpu_macros.S>
+
+ .globl plat_arm_calc_core_pos
+ .globl plat_reset_handler
+
+ /* ---------------------------------------------------------------------
+ * unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
+ *
+ * Function to calculate the core position on TC.
+ *
+ * (ClusterId * PLAT_MAX_CPUS_PER_CLUSTER * PLAT_MAX_PE_PER_CPU) +
+ * (CPUId * PLAT_MAX_PE_PER_CPU) +
+ * ThreadId
+ *
+ * which can be simplified as:
+ *
+ * ((ClusterId * PLAT_MAX_CPUS_PER_CLUSTER + CPUId) * PLAT_MAX_PE_PER_CPU)
+ * + ThreadId
+ * ---------------------------------------------------------------------
+ */
+func plat_arm_calc_core_pos
+ /*
+ * Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it
+ * look as if in a multi-threaded implementation.
+ */
+ tst x0, #MPIDR_MT_MASK
+ lsl x3, x0, #MPIDR_AFFINITY_BITS
+ csel x3, x3, x0, eq
+
+ /* Extract individual affinity fields from MPIDR */
+ ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
+ ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
+ ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
+
+ /* Compute linear position */
+ mov x4, #PLAT_MAX_CPUS_PER_CLUSTER
+ madd x1, x2, x4, x1
+ mov x5, #PLAT_MAX_PE_PER_CPU
+ madd x0, x1, x5, x0
+ ret
+endfunc plat_arm_calc_core_pos
+
+ /* -----------------------------------------------------
+ * void plat_reset_handler(void);
+ *
+ * Determine the CPU MIDR and disable power down bit for
+ * that CPU.
+ * -----------------------------------------------------
+ */
+func plat_reset_handler
+ ret
+endfunc plat_reset_handler
diff --git a/plat/arm/board/tc/include/tc_plat.h b/plat/arm/board/tc/include/tc_plat.h
new file mode 100644
index 0000000..28c0308
--- /dev/null
+++ b/plat/arm/board/tc/include/tc_plat.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TC_PLAT_H
+#define TC_PLAT_H
+
+void tc_bl31_common_platform_setup(void);
+
+#endif /* TC_PLAT_H */
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
new file mode 100644
index 0000000..8db764c
--- /dev/null
+++ b/plat/arm/board/tc/platform.mk
@@ -0,0 +1,137 @@
+# Copyright (c) 2021, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifeq ($(filter ${TARGET_PLATFORM}, 0 1),)
+ $(error TARGET_PLATFORM must be 0 or 1)
+endif
+
+CSS_LOAD_SCP_IMAGES := 1
+
+CSS_USE_SCMI_SDS_DRIVER := 1
+
+RAS_EXTENSION := 0
+
+SDEI_SUPPORT := 0
+
+EL3_EXCEPTION_HANDLING := 0
+
+HANDLE_EA_EL3_FIRST := 0
+
+# System coherency is managed in hardware
+HW_ASSISTED_COHERENCY := 1
+
+# When building for systems with hardware-assisted coherency, there's no need to
+# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
+USE_COHERENT_MEM := 0
+
+GIC_ENABLE_V4_EXTN := 1
+
+# GIC-600 configuration
+GICV3_SUPPORT_GIC600 := 1
+
+
+# Include GICv3 driver files
+include drivers/arm/gic/v3/gicv3.mk
+
+ENT_GIC_SOURCES := ${GICV3_SOURCES} \
+ plat/common/plat_gicv3.c \
+ plat/arm/common/arm_gicv3.c
+
+override NEED_BL2U := no
+
+override ARM_PLAT_MT := 1
+
+TC_BASE = plat/arm/board/tc
+
+PLAT_INCLUDES += -I${TC_BASE}/include/
+
+# Common CPU libraries
+TC_CPU_SOURCES := lib/cpus/aarch64/cortex_a510.S
+
+# CPU libraries for TARGET_PLATFORM=0
+ifeq (${TARGET_PLATFORM}, 0)
+TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a710.S \
+ lib/cpus/aarch64/cortex_x2.S
+endif
+
+# CPU libraries for TARGET_PLATFORM=1
+ifeq (${TARGET_PLATFORM}, 1)
+TC_CPU_SOURCES += lib/cpus/aarch64/cortex_makalu.S \
+ lib/cpus/aarch64/cortex_makalu_elp_arm.S
+endif
+
+INTERCONNECT_SOURCES := ${TC_BASE}/tc_interconnect.c
+
+PLAT_BL_COMMON_SOURCES += ${TC_BASE}/tc_plat.c \
+ ${TC_BASE}/include/tc_helpers.S
+
+BL1_SOURCES += ${INTERCONNECT_SOURCES} \
+ ${TC_CPU_SOURCES} \
+ ${TC_BASE}/tc_trusted_boot.c \
+ ${TC_BASE}/tc_err.c \
+ drivers/arm/sbsa/sbsa.c
+
+
+BL2_SOURCES += ${TC_BASE}/tc_security.c \
+ ${TC_BASE}/tc_err.c \
+ ${TC_BASE}/tc_trusted_boot.c \
+ lib/utils/mem_region.c \
+ drivers/arm/tzc/tzc400.c \
+ plat/arm/common/arm_tzc400.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c
+
+BL31_SOURCES += ${INTERCONNECT_SOURCES} \
+ ${TC_CPU_SOURCES} \
+ ${ENT_GIC_SOURCES} \
+ ${TC_BASE}/tc_bl31_setup.c \
+ ${TC_BASE}/tc_topology.c \
+ drivers/cfi/v2m/v2m_flash.c \
+ lib/utils/mem_region.c \
+ plat/arm/common/arm_nor_psci_mem_protect.c
+
+# Add the FDT_SOURCES and options for Dynamic Config
+FDT_SOURCES += ${TC_BASE}/fdts/${PLAT}_fw_config.dts \
+ ${TC_BASE}/fdts/${PLAT}_tb_fw_config.dts
+FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
+TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
+
+# Add the FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
+# Add the TB_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
+
+ifeq (${SPD},spmd)
+ifeq ($(ARM_SPMC_MANIFEST_DTS),)
+ARM_SPMC_MANIFEST_DTS := ${TC_BASE}/fdts/${PLAT}_spmc_manifest.dts
+endif
+
+FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS}
+TC_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb
+
+# Add the TOS_FW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${TC_TOS_FW_CONFIG},--tos-fw-config,${TC_TOS_FW_CONFIG}))
+endif
+
+#Device tree
+TC_HW_CONFIG_DTS := fdts/tc.dts
+TC_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb
+FDT_SOURCES += ${TC_HW_CONFIG_DTS}
+$(eval TC_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(TC_HW_CONFIG_DTS)))
+
+# Add the HW_CONFIG to FIP and specify the same to certtool
+$(eval $(call TOOL_ADD_PAYLOAD,${TC_HW_CONFIG},--hw-config,${TC_HW_CONFIG}))
+
+override CTX_INCLUDE_AARCH32_REGS := 0
+
+override CTX_INCLUDE_PAUTH_REGS := 1
+
+override ENABLE_SPE_FOR_LOWER_ELS := 0
+
+override ENABLE_AMU := 1
+
+include plat/arm/common/arm_common.mk
+include plat/arm/css/common/css_common.mk
+include plat/arm/soc/common/soc_css.mk
+include plat/arm/board/common/board_common.mk
diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c
new file mode 100644
index 0000000..ecec26c
--- /dev/null
+++ b/plat/arm/board/tc/tc_bl31_setup.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <libfdt.h>
+#include <tc_plat.h>
+
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <drivers/arm/css/css_mhu_doorbell.h>
+#include <drivers/arm/css/scmi.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+
+static scmi_channel_plat_info_t tc_scmi_plat_info[] = {
+ {
+ .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
+ .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
+ .db_preserve_mask = 0xfffffffe,
+ .db_modify_mask = 0x1,
+ .ring_doorbell = &mhuv2_ring_doorbell,
+ }
+};
+
+void bl31_platform_setup(void)
+{
+ tc_bl31_common_platform_setup();
+}
+
+scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id)
+{
+
+ return &tc_scmi_plat_info[channel_id];
+
+}
+
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
+{
+ arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+}
+
+void tc_bl31_common_platform_setup(void)
+{
+ arm_bl31_platform_setup();
+}
+
+const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
+{
+ return css_scmi_override_pm_ops(ops);
+}
diff --git a/plat/arm/board/tc/tc_err.c b/plat/arm/board/tc/tc_err.c
new file mode 100644
index 0000000..9ed7e92
--- /dev/null
+++ b/plat/arm/board/tc/tc_err.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+
+/*
+ * tc error handler
+ */
+void __dead2 plat_arm_error_handler(int err)
+{
+ while (true) {
+ wfi();
+ }
+}
diff --git a/plat/arm/board/tc0/tc0_interconnect.c b/plat/arm/board/tc/tc_interconnect.c
similarity index 100%
rename from plat/arm/board/tc0/tc0_interconnect.c
rename to plat/arm/board/tc/tc_interconnect.c
diff --git a/plat/arm/board/tc/tc_plat.c b/plat/arm/board/tc/tc_plat.c
new file mode 100644
index 0000000..3863a0a
--- /dev/null
+++ b/plat/arm/board/tc/tc_plat.c
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <platform_def.h>
+
+#include <plat/common/platform.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <drivers/arm/ccn.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+#include <drivers/arm/sbsa.h>
+
+#if SPM_MM
+#include <services/spm_mm_partition.h>
+#endif
+
+/*
+ * Table of regions for different BL stages to map using the MMU.
+ * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
+ * arm_configure_mmu_elx() will give the available subset of that.
+ */
+#if IMAGE_BL1
+const mmap_region_t plat_arm_mmap[] = {
+ ARM_MAP_SHARED_RAM,
+ TC_FLASH0_RO,
+ TC_MAP_DEVICE,
+ {0}
+};
+#endif
+#if IMAGE_BL2
+const mmap_region_t plat_arm_mmap[] = {
+ ARM_MAP_SHARED_RAM,
+ TC_FLASH0_RO,
+ TC_MAP_DEVICE,
+ TC_MAP_NS_DRAM1,
+#if defined(SPD_spmd)
+ TC_MAP_TZC_DRAM1,
+#endif
+#if ARM_BL31_IN_DRAM
+ ARM_MAP_BL31_SEC_DRAM,
+#endif
+#if SPM_MM
+ ARM_SP_IMAGE_MMAP,
+#endif
+#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
+ ARM_MAP_BL1_RW,
+#endif
+#ifdef SPD_opteed
+ ARM_MAP_OPTEE_CORE_MEM,
+ ARM_OPTEE_PAGEABLE_LOAD_MEM,
+#endif
+ {0}
+};
+#endif
+#if IMAGE_BL31
+const mmap_region_t plat_arm_mmap[] = {
+ ARM_MAP_SHARED_RAM,
+ V2M_MAP_IOFPGA,
+ TC_MAP_DEVICE,
+#if SPM_MM
+ ARM_SPM_BUF_EL3_MMAP,
+#endif
+ {0}
+};
+
+#if SPM_MM && defined(IMAGE_BL31)
+const mmap_region_t plat_arm_secure_partition_mmap[] = {
+ PLAT_ARM_SECURE_MAP_DEVICE,
+ ARM_SP_IMAGE_MMAP,
+ ARM_SP_IMAGE_NS_BUF_MMAP,
+ ARM_SP_CPER_BUF_MMAP,
+ ARM_SP_IMAGE_RW_MMAP,
+ ARM_SPM_BUF_EL0_MMAP,
+ {0}
+};
+#endif /* SPM_MM && defined(IMAGE_BL31) */
+#endif
+
+ARM_CASSERT_MMAP
+
+#if SPM_MM && defined(IMAGE_BL31)
+/*
+ * Boot information passed to a secure partition during initialisation. Linear
+ * indices in MP information will be filled at runtime.
+ */
+static spm_mm_mp_info_t sp_mp_info[] = {
+ [0] = {0x81000000, 0},
+ [1] = {0x81000100, 0},
+ [2] = {0x81000200, 0},
+ [3] = {0x81000300, 0},
+ [4] = {0x81010000, 0},
+ [5] = {0x81010100, 0},
+ [6] = {0x81010200, 0},
+ [7] = {0x81010300, 0},
+};
+
+const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
+ .h.type = PARAM_SP_IMAGE_BOOT_INFO,
+ .h.version = VERSION_1,
+ .h.size = sizeof(spm_mm_boot_info_t),
+ .h.attr = 0,
+ .sp_mem_base = ARM_SP_IMAGE_BASE,
+ .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
+ .sp_image_base = ARM_SP_IMAGE_BASE,
+ .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
+ .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
+ .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
+ .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
+ .sp_image_size = ARM_SP_IMAGE_SIZE,
+ .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
+ .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
+ .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
+ .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
+ .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
+ .num_cpus = PLATFORM_CORE_COUNT,
+ .mp_info = &sp_mp_info[0],
+};
+
+const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
+{
+ return plat_arm_secure_partition_mmap;
+}
+
+const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
+ void *cookie)
+{
+ return &plat_arm_secure_partition_boot_info;
+}
+#endif /* SPM_MM && defined(IMAGE_BL31) */
+
+#if TRUSTED_BOARD_BOOT
+int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
+{
+ assert(heap_addr != NULL);
+ assert(heap_size != NULL);
+
+ return arm_get_mbedtls_heap(heap_addr, heap_size);
+}
+#endif
+
+void plat_arm_secure_wdt_start(void)
+{
+ sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
+}
+
+void plat_arm_secure_wdt_stop(void)
+{
+ sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
+}
diff --git a/plat/arm/board/tc/tc_security.c b/plat/arm/board/tc/tc_security.c
new file mode 100644
index 0000000..6a34501
--- /dev/null
+++ b/plat/arm/board/tc/tc_security.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+#include <platform_def.h>
+
+static const arm_tzc_regions_info_t tzc_regions[] = {
+ TC_TZC_REGIONS_DEF,
+ {}
+};
+
+/* Initialize the secure environment */
+void plat_arm_security_setup(void)
+{
+ unsigned int i;
+
+ for (i = 0U; i < TZC400_COUNT; i++) {
+ arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
+ }
+}
diff --git a/plat/arm/board/tc/tc_topology.c b/plat/arm/board/tc/tc_topology.c
new file mode 100644
index 0000000..9e18da6
--- /dev/null
+++ b/plat/arm/board/tc/tc_topology.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/arm/common/plat_arm.h>
+#include <plat/arm/css/common/css_pm.h>
+
+/******************************************************************************
+ * The power domain tree descriptor.
+ ******************************************************************************/
+const unsigned char tc_pd_tree_desc[] = {
+ PLAT_ARM_CLUSTER_COUNT,
+ PLAT_MAX_CPUS_PER_CLUSTER,
+};
+
+/*******************************************************************************
+ * This function returns the topology tree information.
+ ******************************************************************************/
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+ return tc_pd_tree_desc;
+}
+
+/*******************************************************************************
+ * The array mapping platform core position (implemented by plat_my_core_pos())
+ * to the SCMI power domain ID implemented by SCP.
+ ******************************************************************************/
+const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
+};
+
+/*******************************************************************************
+ * This function returns the core count within the cluster corresponding to
+ * `mpidr`.
+ ******************************************************************************/
+unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
+{
+ return PLAT_MAX_CPUS_PER_CLUSTER;
+}
+
+#if ARM_PLAT_MT
+/******************************************************************************
+ * Return the number of PE's supported by the CPU.
+ *****************************************************************************/
+unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr)
+{
+ return PLAT_MAX_PE_PER_CPU;
+}
+#endif
diff --git a/plat/arm/board/tc0/tc0_trusted_boot.c b/plat/arm/board/tc/tc_trusted_boot.c
similarity index 100%
rename from plat/arm/board/tc0/tc0_trusted_boot.c
rename to plat/arm/board/tc/tc_trusted_boot.c
diff --git a/plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts b/plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts
deleted file mode 100644
index 2f459b0..0000000
--- a/plat/arm/board/tc0/fdts/tc0_spmc_manifest.dts
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-/dts-v1/;
-
-/ {
- compatible = "arm,ffa-core-manifest-1.0";
- #address-cells = <2>;
- #size-cells = <1>;
-
- attribute {
- spmc_id = <0x8000>;
- maj_ver = <0x1>;
- min_ver = <0x0>;
- exec_state = <0x0>;
- load_address = <0x0 0xfd000000>;
- entrypoint = <0x0 0xfd000000>;
- binary_size = <0x80000>;
- };
-
- hypervisor {
- compatible = "hafnium,hafnium";
- vm1 {
- is_ffa_partition;
- debug_name = "cactus-primary";
- load_address = <0xfe000000>;
- vcpu_count = <8>;
- mem_size = <1048576>;
- };
- vm2 {
- is_ffa_partition;
- debug_name = "cactus-secondary";
- load_address = <0xfe100000>;
- vcpu_count = <8>;
- mem_size = <1048576>;
- };
- vm3 {
- is_ffa_partition;
- debug_name = "cactus-tertiary";
- load_address = <0xfe200000>;
- vcpu_count = <8>;
- mem_size = <1048576>;
- };
- };
-
- cpus {
- #address-cells = <0x2>;
- #size-cells = <0x0>;
-
- CPU0:cpu@0 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x0>;
- enable-method = "psci";
- };
-
- /*
- * SPMC (Hafnium) requires secondary cpu nodes are declared in
- * descending order
- */
- CPU7:cpu@700 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x700>;
- enable-method = "psci";
- };
-
- CPU6:cpu@600 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x600>;
- enable-method = "psci";
- };
-
- CPU5:cpu@500 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x500>;
- enable-method = "psci";
- };
-
- CPU4:cpu@400 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x400>;
- enable-method = "psci";
- };
-
- CPU3:cpu@300 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x300>;
- enable-method = "psci";
- };
-
- CPU2:cpu@200 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x200>;
- enable-method = "psci";
- };
-
- CPU1:cpu@100 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x100>;
- enable-method = "psci";
- };
- };
-
- /* 32MB of TC0_TZC_DRAM1_BASE */
- memory@fd000000 {
- device_type = "memory";
- reg = <0x0 0xfd000000 0x2000000>;
- };
-};
diff --git a/plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts b/plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts
deleted file mode 100644
index 221039c..0000000
--- a/plat/arm/board/tc0/fdts/tc0_spmc_optee_sp_manifest.dts
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-/dts-v1/;
-
-/ {
- compatible = "arm,ffa-core-manifest-1.0";
- #address-cells = <2>;
- #size-cells = <1>;
-
- attribute {
- spmc_id = <0x8000>;
- maj_ver = <0x1>;
- min_ver = <0x0>;
- exec_state = <0x0>;
- load_address = <0x0 0xfd000000>;
- entrypoint = <0x0 0xfd000000>;
- binary_size = <0x80000>;
- };
-
- hypervisor {
- compatible = "hafnium,hafnium";
- vm1 {
- is_ffa_partition;
- debug_name = "op-tee";
- load_address = <0xfd280000>;
- vcpu_count = <8>;
- mem_size = <30928896>; /* 32MB TZC DRAM - SPMC region */
- };
- };
-
- cpus {
- #address-cells = <0x2>;
- #size-cells = <0x0>;
-
- CPU0:cpu@0 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x0>;
- enable-method = "psci";
- };
-
- /*
- * SPMC (Hafnium) requires secondary cpu nodes are declared in
- * descending order
- */
- CPU7:cpu@700 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x700>;
- enable-method = "psci";
- };
-
- CPU6:cpu@600 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x600>;
- enable-method = "psci";
- };
-
- CPU5:cpu@500 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x500>;
- enable-method = "psci";
- };
-
- CPU4:cpu@400 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x400>;
- enable-method = "psci";
- };
-
- CPU3:cpu@300 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x300>;
- enable-method = "psci";
- };
-
- CPU2:cpu@200 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x200>;
- enable-method = "psci";
- };
-
- CPU1:cpu@100 {
- device_type = "cpu";
- compatible = "arm,armv8";
- reg = <0x0 0x100>;
- enable-method = "psci";
- };
- };
-
- /* 32MB of TC0_TZC_DRAM1_BASE */
- memory@fd000000 {
- device_type = "memory";
- reg = <0x0 0xfd000000 0x2000000>;
- };
-};
diff --git a/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts b/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts
deleted file mode 100644
index de5f95d..0000000
--- a/plat/arm/board/tc0/fdts/tc0_tb_fw_config.dts
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-
-/ {
- tb_fw-config {
- compatible = "arm,tb_fw";
-
- /* Disable authentication for development */
- disable_auth = <0x0>;
- /*
- * The following two entries are placeholders for Mbed TLS
- * heap information. The default values don't matter since
- * they will be overwritten by BL1.
- * In case of having shared Mbed TLS heap between BL1 and BL2,
- * BL1 will populate these two properties with the respective
- * info about the shared heap. This info will be available for
- * BL2 in order to locate and re-use the heap.
- */
- mbedtls_heap_addr = <0x0 0x0>;
- mbedtls_heap_size = <0x0>;
- };
-
- secure-partitions {
- compatible = "arm,sp";
-#if OPTEE_SP_FW_CONFIG
- op-tee {
- uuid = <0x486178e0 0xe7f811e3 0xbc5e0002 0xa5d5c51b>;
- load-address = <0xfd280000>;
- };
-#else
- cactus-primary {
- uuid = <0xb4b5671e 0x4a904fe1 0xb81ffb13 0xdae1dacb>;
- load-address = <0xfe000000>;
- owner = "SiP";
- };
-
- cactus-secondary {
- uuid = <0xd1582309 0xf02347b9 0x827c4464 0xf5578fc8>;
- load-address = <0xfe100000>;
- owner = "Plat";
- };
-
- cactus-tertiary {
- uuid = <0x79b55c73 0x1d8c44b9 0x859361e1 0x770ad8d2>;
- load-address = <0xfe200000>;
- };
-#endif
- };
-};
diff --git a/plat/arm/board/tc0/include/platform_def.h b/plat/arm/board/tc0/include/platform_def.h
deleted file mode 100644
index 30b5ab7..0000000
--- a/plat/arm/board/tc0/include/platform_def.h
+++ /dev/null
@@ -1,266 +0,0 @@
-/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_DEF_H
-#define PLATFORM_DEF_H
-
-#include <lib/utils_def.h>
-#include <lib/xlat_tables/xlat_tables_defs.h>
-#include <plat/arm/board/common/board_css_def.h>
-#include <plat/arm/board/common/v2m_def.h>
-#include <plat/arm/common/arm_def.h>
-#include <plat/arm/common/arm_spm_def.h>
-#include <plat/arm/css/common/css_def.h>
-#include <plat/arm/soc/common/soc_css_def.h>
-#include <plat/common/common_def.h>
-
-#define PLATFORM_CORE_COUNT 8
-
-#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */
-
-/*
- * The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC,
- * its base is ARM_AP_TZC_DRAM1_BASE.
- *
- * Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for:
- * - BL32_BASE when SPD_spmd is enabled
- * - Region to load Trusted OS
- */
-#define TC0_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \
- TC0_TZC_DRAM1_SIZE)
-#define TC0_TZC_DRAM1_SIZE UL(0x02000000) /* 32 MB */
-#define TC0_TZC_DRAM1_END (TC0_TZC_DRAM1_BASE + \
- TC0_TZC_DRAM1_SIZE - 1)
-
-#define TC0_NS_DRAM1_BASE ARM_DRAM1_BASE
-#define TC0_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
- ARM_TZC_DRAM1_SIZE - \
- TC0_TZC_DRAM1_SIZE)
-#define TC0_NS_DRAM1_END (TC0_NS_DRAM1_BASE + \
- TC0_NS_DRAM1_SIZE - 1)
-
-/*
- * Mappings for TC0 DRAM1 (non-secure) and TC0 TZC DRAM1 (secure)
- */
-#define TC0_MAP_NS_DRAM1 MAP_REGION_FLAT( \
- TC0_NS_DRAM1_BASE, \
- TC0_NS_DRAM1_SIZE, \
- MT_MEMORY | MT_RW | MT_NS)
-
-
-#define TC0_MAP_TZC_DRAM1 MAP_REGION_FLAT( \
- TC0_TZC_DRAM1_BASE, \
- TC0_TZC_DRAM1_SIZE, \
- MT_MEMORY | MT_RW | MT_SECURE)
-/*
- * Max size of SPMC is 2MB for tc0. With SPMD enabled this value corresponds to
- * max size of BL32 image.
- */
-#if defined(SPD_spmd)
-#define PLAT_ARM_SPMC_BASE TC0_TZC_DRAM1_BASE
-#define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */
-#endif
-
-/*
- * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
- * plat_arm_mmap array defined for each BL stage.
- */
-#if defined(IMAGE_BL31)
-# if SPM_MM
-# define PLAT_ARM_MMAP_ENTRIES 9
-# define MAX_XLAT_TABLES 7
-# define PLAT_SP_IMAGE_MMAP_REGIONS 7
-# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10
-# else
-# define PLAT_ARM_MMAP_ENTRIES 8
-# define MAX_XLAT_TABLES 8
-# endif
-#elif defined(IMAGE_BL32)
-# define PLAT_ARM_MMAP_ENTRIES 8
-# define MAX_XLAT_TABLES 5
-#elif !USE_ROMLIB
-# define PLAT_ARM_MMAP_ENTRIES 11
-# define MAX_XLAT_TABLES 7
-#else
-# define PLAT_ARM_MMAP_ENTRIES 12
-# define MAX_XLAT_TABLES 6
-#endif
-
-/*
- * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
- * plus a little space for growth.
- */
-#define PLAT_ARM_MAX_BL1_RW_SIZE 0xC000
-
-/*
- * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page
- */
-
-#if USE_ROMLIB
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000
-#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000
-#else
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0
-#define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0
-#endif
-
-/*
- * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
- * little space for growth.
- */
-#if TRUSTED_BOARD_BOOT
-# define PLAT_ARM_MAX_BL2_SIZE 0x20000
-#else
-# define PLAT_ARM_MAX_BL2_SIZE 0x14000
-#endif
-
-/*
- * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
- * calculated using the current BL31 PROGBITS debug size plus the sizes of
- * BL2 and BL1-RW
- */
-#define PLAT_ARM_MAX_BL31_SIZE 0x3B000
-
-/*
- * Size of cacheable stacks
- */
-#if defined(IMAGE_BL1)
-# if TRUSTED_BOARD_BOOT
-# define PLATFORM_STACK_SIZE 0x1000
-# else
-# define PLATFORM_STACK_SIZE 0x440
-# endif
-#elif defined(IMAGE_BL2)
-# if TRUSTED_BOARD_BOOT
-# define PLATFORM_STACK_SIZE 0x1000
-# else
-# define PLATFORM_STACK_SIZE 0x400
-# endif
-#elif defined(IMAGE_BL2U)
-# define PLATFORM_STACK_SIZE 0x400
-#elif defined(IMAGE_BL31)
-# if SPM_MM
-# define PLATFORM_STACK_SIZE 0x500
-# else
-# define PLATFORM_STACK_SIZE 0x400
-# endif
-#elif defined(IMAGE_BL32)
-# define PLATFORM_STACK_SIZE 0x440
-#endif
-
-
-#define TC0_DEVICE_BASE 0x21000000
-#define TC0_DEVICE_SIZE 0x5f000000
-
-// TC0_MAP_DEVICE covers different peripherals
-// available to the platform
-#define TC0_MAP_DEVICE MAP_REGION_FLAT( \
- TC0_DEVICE_BASE, \
- TC0_DEVICE_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-
-#define TC0_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
- V2M_FLASH0_SIZE, \
- MT_DEVICE | MT_RO | MT_SECURE)
-
-#define PLAT_ARM_NSTIMER_FRAME_ID 0
-
-#define PLAT_ARM_TRUSTED_ROM_BASE 0x0
-#define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 /* 512KB */
-
-#define PLAT_ARM_NSRAM_BASE 0x06000000
-#define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */
-
-#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
-#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
-
-#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
-#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
-
-#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
- PLAT_SP_IMAGE_NS_BUF_SIZE)
-
-/*******************************************************************************
- * Memprotect definitions
- ******************************************************************************/
-/* PSCI memory protect definitions:
- * This variable is stored in a non-secure flash because some ARM reference
- * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT
- * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions.
- */
-#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
- V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-
-/*Secure Watchdog Constants */
-#define SBSA_SECURE_WDOG_BASE UL(0x2A480000)
-#define SBSA_SECURE_WDOG_TIMEOUT UL(100)
-
-#define PLAT_ARM_SCMI_CHANNEL_COUNT 1
-
-#define PLAT_ARM_CLUSTER_COUNT U(1)
-#define PLAT_MAX_CPUS_PER_CLUSTER U(8)
-#define PLAT_MAX_PE_PER_CPU U(1)
-
-#define PLAT_CSS_MHU_BASE UL(0x45400000)
-#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
-
-#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
-#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
-
-/*
- * Physical and virtual address space limits for MMU in AARCH64
- */
-#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36)
-
-/* GIC related constants */
-#define PLAT_ARM_GICD_BASE UL(0x30000000)
-#define PLAT_ARM_GICC_BASE UL(0x2C000000)
-#define PLAT_ARM_GICR_BASE UL(0x30140000)
-
-/*
- * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current
- * SCP_BL2 size plus a little space for growth.
- */
-#define PLAT_CSS_MAX_SCP_BL2_SIZE 0x20000
-
-/*
- * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current
- * SCP_BL2U size plus a little space for growth.
- */
-#define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x20000
-
-/* TZC Related Constants */
-#define PLAT_ARM_TZC_BASE UL(0x25000000)
-#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
-
-#define TZC400_OFFSET UL(0x1000000)
-#define TZC400_COUNT 4
-
-#define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \
- (n * TZC400_OFFSET))
-
-#define TZC_NSAID_DEFAULT U(0)
-
-#define PLAT_ARM_TZC_NS_DEV_ACCESS \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT))
-
-/*
- * The first region below, TC0_TZC_DRAM1_BASE (0xfd000000) to
- * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 48 MB of DRAM as
- * secure. The second region gives non secure access to rest of DRAM.
- */
-#define TC0_TZC_REGIONS_DEF \
- {TC0_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END, \
- TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS}, \
- {TC0_NS_DRAM1_BASE, TC0_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
- PLAT_ARM_TZC_NS_DEV_ACCESS}
-
-/* virtual address used by dynamic mem_protect for chunk_base */
-#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
-
-#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/tc0/include/tc0_helpers.S b/plat/arm/board/tc0/include/tc0_helpers.S
deleted file mode 100644
index 90623a2..0000000
--- a/plat/arm/board/tc0/include/tc0_helpers.S
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <platform_def.h>
-#include <cpu_macros.S>
-
- .globl plat_arm_calc_core_pos
- .globl plat_reset_handler
-
- /* ---------------------------------------------------------------------
- * unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
- *
- * Function to calculate the core position on TC0.
- *
- * (ClusterId * PLAT_MAX_CPUS_PER_CLUSTER * PLAT_MAX_PE_PER_CPU) +
- * (CPUId * PLAT_MAX_PE_PER_CPU) +
- * ThreadId
- *
- * which can be simplified as:
- *
- * ((ClusterId * PLAT_MAX_CPUS_PER_CLUSTER + CPUId) * PLAT_MAX_PE_PER_CPU)
- * + ThreadId
- * ---------------------------------------------------------------------
- */
-func plat_arm_calc_core_pos
- /*
- * Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it
- * look as if in a multi-threaded implementation.
- */
- tst x0, #MPIDR_MT_MASK
- lsl x3, x0, #MPIDR_AFFINITY_BITS
- csel x3, x3, x0, eq
-
- /* Extract individual affinity fields from MPIDR */
- ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
- ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
- ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
-
- /* Compute linear position */
- mov x4, #PLAT_MAX_CPUS_PER_CLUSTER
- madd x1, x2, x4, x1
- mov x5, #PLAT_MAX_PE_PER_CPU
- madd x0, x1, x5, x0
- ret
-endfunc plat_arm_calc_core_pos
-
- /* -----------------------------------------------------
- * void plat_reset_handler(void);
- *
- * Determine the CPU MIDR and disable power down bit for
- * that CPU.
- * -----------------------------------------------------
- */
-func plat_reset_handler
- ret
-endfunc plat_reset_handler
diff --git a/plat/arm/board/tc0/include/tc0_plat.h b/plat/arm/board/tc0/include/tc0_plat.h
deleted file mode 100644
index f0cb431..0000000
--- a/plat/arm/board/tc0/include/tc0_plat.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef tc0_bl31_common_platform_setup_PLAT_H
-#define tc0_bl31_common_platform_setup_PLAT_H
-
-void tc0_bl31_common_platform_setup(void);
-
-#endif /* tc0_bl31_common_platform_setup_PLAT_H */
diff --git a/plat/arm/board/tc0/platform.mk b/plat/arm/board/tc0/platform.mk
deleted file mode 100644
index 393d09c..0000000
--- a/plat/arm/board/tc0/platform.mk
+++ /dev/null
@@ -1,119 +0,0 @@
-# Copyright (c) 2020, Arm Limited. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-CSS_LOAD_SCP_IMAGES := 1
-
-CSS_USE_SCMI_SDS_DRIVER := 1
-
-RAS_EXTENSION := 0
-
-SDEI_SUPPORT := 0
-
-EL3_EXCEPTION_HANDLING := 0
-
-HANDLE_EA_EL3_FIRST := 0
-
-# System coherency is managed in hardware
-HW_ASSISTED_COHERENCY := 1
-
-# When building for systems with hardware-assisted coherency, there's no need to
-# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
-USE_COHERENT_MEM := 0
-
-GIC_ENABLE_V4_EXTN := 1
-
-# GIC-600 configuration
-GICV3_SUPPORT_GIC600 := 1
-
-
-# Include GICv3 driver files
-include drivers/arm/gic/v3/gicv3.mk
-
-ENT_GIC_SOURCES := ${GICV3_SOURCES} \
- plat/common/plat_gicv3.c \
- plat/arm/common/arm_gicv3.c
-
-override NEED_BL2U := no
-
-override ARM_PLAT_MT := 1
-
-TC0_BASE = plat/arm/board/tc0
-
-PLAT_INCLUDES += -I${TC0_BASE}/include/
-
-TC0_CPU_SOURCES := lib/cpus/aarch64/cortex_klein.S \
- lib/cpus/aarch64/cortex_matterhorn.S
-
-INTERCONNECT_SOURCES := ${TC0_BASE}/tc0_interconnect.c
-
-PLAT_BL_COMMON_SOURCES += ${TC0_BASE}/tc0_plat.c \
- ${TC0_BASE}/include/tc0_helpers.S
-
-BL1_SOURCES += ${INTERCONNECT_SOURCES} \
- ${TC0_CPU_SOURCES} \
- ${TC0_BASE}/tc0_trusted_boot.c \
- ${TC0_BASE}/tc0_err.c \
- drivers/arm/sbsa/sbsa.c
-
-
-BL2_SOURCES += ${TC0_BASE}/tc0_security.c \
- ${TC0_BASE}/tc0_err.c \
- ${TC0_BASE}/tc0_trusted_boot.c \
- lib/utils/mem_region.c \
- drivers/arm/tzc/tzc400.c \
- plat/arm/common/arm_tzc400.c \
- plat/arm/common/arm_nor_psci_mem_protect.c
-
-BL31_SOURCES += ${INTERCONNECT_SOURCES} \
- ${TC0_CPU_SOURCES} \
- ${ENT_GIC_SOURCES} \
- ${TC0_BASE}/tc0_bl31_setup.c \
- ${TC0_BASE}/tc0_topology.c \
- drivers/cfi/v2m/v2m_flash.c \
- lib/utils/mem_region.c \
- plat/arm/common/arm_nor_psci_mem_protect.c
-
-# Add the FDT_SOURCES and options for Dynamic Config
-FDT_SOURCES += ${TC0_BASE}/fdts/${PLAT}_fw_config.dts \
- ${TC0_BASE}/fdts/${PLAT}_tb_fw_config.dts
-FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
-TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
-
-# Add the FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
-# Add the TB_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
-
-ifeq (${SPD},spmd)
-ifeq ($(ARM_SPMC_MANIFEST_DTS),)
-ARM_SPMC_MANIFEST_DTS := ${TC0_BASE}/fdts/${PLAT}_spmc_manifest.dts
-endif
-
-FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS}
-TC0_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb
-
-# Add the TOS_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${TC0_TOS_FW_CONFIG},--tos-fw-config,${TC0_TOS_FW_CONFIG}))
-endif
-
-#Device tree
-TC0_HW_CONFIG_DTS := fdts/tc0.dts
-TC0_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb
-FDT_SOURCES += ${TC0_HW_CONFIG_DTS}
-$(eval TC0_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(TC0_HW_CONFIG_DTS)))
-
-# Add the HW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${TC0_HW_CONFIG},--hw-config,${TC0_HW_CONFIG}))
-
-override CTX_INCLUDE_AARCH32_REGS := 0
-
-override CTX_INCLUDE_PAUTH_REGS := 1
-
-override ENABLE_SPE_FOR_LOWER_ELS := 0
-
-include plat/arm/common/arm_common.mk
-include plat/arm/css/common/css_common.mk
-include plat/arm/soc/common/soc_css.mk
-include plat/arm/board/common/board_common.mk
diff --git a/plat/arm/board/tc0/tc0_bl31_setup.c b/plat/arm/board/tc0/tc0_bl31_setup.c
deleted file mode 100644
index b91b11c..0000000
--- a/plat/arm/board/tc0/tc0_bl31_setup.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include <libfdt.h>
-#include <tc0_plat.h>
-
-#include <common/bl_common.h>
-#include <common/debug.h>
-#include <drivers/arm/css/css_mhu_doorbell.h>
-#include <drivers/arm/css/scmi.h>
-#include <plat/arm/common/plat_arm.h>
-#include <plat/common/platform.h>
-
-static scmi_channel_plat_info_t tc0_scmi_plat_info[] = {
- {
- .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
- .db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
- .db_preserve_mask = 0xfffffffe,
- .db_modify_mask = 0x1,
- .ring_doorbell = &mhuv2_ring_doorbell,
- }
-};
-
-void bl31_platform_setup(void)
-{
- tc0_bl31_common_platform_setup();
-}
-
-scmi_channel_plat_info_t *plat_css_get_scmi_info(int channel_id)
-{
-
- return &tc0_scmi_plat_info[channel_id];
-
-}
-
-void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
- u_register_t arg2, u_register_t arg3)
-{
- arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
-}
-
-void tc0_bl31_common_platform_setup(void)
-{
- arm_bl31_platform_setup();
-}
-
-const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
-{
- return css_scmi_override_pm_ops(ops);
-}
diff --git a/plat/arm/board/tc0/tc0_err.c b/plat/arm/board/tc0/tc0_err.c
deleted file mode 100644
index 83f2e9f..0000000
--- a/plat/arm/board/tc0/tc0_err.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * tc0 error handler
- */
-void __dead2 plat_arm_error_handler(int err)
-{
- while (true) {
- wfi();
- }
-}
diff --git a/plat/arm/board/tc0/tc0_plat.c b/plat/arm/board/tc0/tc0_plat.c
deleted file mode 100644
index b5698c0..0000000
--- a/plat/arm/board/tc0/tc0_plat.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include <platform_def.h>
-
-#include <plat/common/platform.h>
-#include <common/bl_common.h>
-#include <common/debug.h>
-#include <drivers/arm/ccn.h>
-#include <plat/arm/common/plat_arm.h>
-#include <plat/common/platform.h>
-#include <drivers/arm/sbsa.h>
-
-#if SPM_MM
-#include <services/spm_mm_partition.h>
-#endif
-
-/*
- * Table of regions for different BL stages to map using the MMU.
- * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
- * arm_configure_mmu_elx() will give the available subset of that.
- */
-#if IMAGE_BL1
-const mmap_region_t plat_arm_mmap[] = {
- ARM_MAP_SHARED_RAM,
- TC0_FLASH0_RO,
- TC0_MAP_DEVICE,
- {0}
-};
-#endif
-#if IMAGE_BL2
-const mmap_region_t plat_arm_mmap[] = {
- ARM_MAP_SHARED_RAM,
- TC0_FLASH0_RO,
- TC0_MAP_DEVICE,
- TC0_MAP_NS_DRAM1,
-#if defined(SPD_spmd)
- TC0_MAP_TZC_DRAM1,
-#endif
-#if ARM_BL31_IN_DRAM
- ARM_MAP_BL31_SEC_DRAM,
-#endif
-#if SPM_MM
- ARM_SP_IMAGE_MMAP,
-#endif
-#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
- ARM_MAP_BL1_RW,
-#endif
-#ifdef SPD_opteed
- ARM_MAP_OPTEE_CORE_MEM,
- ARM_OPTEE_PAGEABLE_LOAD_MEM,
-#endif
- {0}
-};
-#endif
-#if IMAGE_BL31
-const mmap_region_t plat_arm_mmap[] = {
- ARM_MAP_SHARED_RAM,
- V2M_MAP_IOFPGA,
- TC0_MAP_DEVICE,
-#if SPM_MM
- ARM_SPM_BUF_EL3_MMAP,
-#endif
- {0}
-};
-
-#if SPM_MM && defined(IMAGE_BL31)
-const mmap_region_t plat_arm_secure_partition_mmap[] = {
- PLAT_ARM_SECURE_MAP_DEVICE,
- ARM_SP_IMAGE_MMAP,
- ARM_SP_IMAGE_NS_BUF_MMAP,
- ARM_SP_CPER_BUF_MMAP,
- ARM_SP_IMAGE_RW_MMAP,
- ARM_SPM_BUF_EL0_MMAP,
- {0}
-};
-#endif /* SPM_MM && defined(IMAGE_BL31) */
-#endif
-
-ARM_CASSERT_MMAP
-
-#if SPM_MM && defined(IMAGE_BL31)
-/*
- * Boot information passed to a secure partition during initialisation. Linear
- * indices in MP information will be filled at runtime.
- */
-static spm_mm_mp_info_t sp_mp_info[] = {
- [0] = {0x81000000, 0},
- [1] = {0x81000100, 0},
- [2] = {0x81000200, 0},
- [3] = {0x81000300, 0},
- [4] = {0x81010000, 0},
- [5] = {0x81010100, 0},
- [6] = {0x81010200, 0},
- [7] = {0x81010300, 0},
-};
-
-const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
- .h.type = PARAM_SP_IMAGE_BOOT_INFO,
- .h.version = VERSION_1,
- .h.size = sizeof(spm_mm_boot_info_t),
- .h.attr = 0,
- .sp_mem_base = ARM_SP_IMAGE_BASE,
- .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
- .sp_image_base = ARM_SP_IMAGE_BASE,
- .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
- .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
- .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
- .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
- .sp_image_size = ARM_SP_IMAGE_SIZE,
- .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
- .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
- .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
- .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
- .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
- .num_cpus = PLATFORM_CORE_COUNT,
- .mp_info = &sp_mp_info[0],
-};
-
-const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
-{
- return plat_arm_secure_partition_mmap;
-}
-
-const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
- void *cookie)
-{
- return &plat_arm_secure_partition_boot_info;
-}
-#endif /* SPM_MM && defined(IMAGE_BL31) */
-
-#if TRUSTED_BOARD_BOOT
-int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
-{
- assert(heap_addr != NULL);
- assert(heap_size != NULL);
-
- return arm_get_mbedtls_heap(heap_addr, heap_size);
-}
-#endif
-
-void plat_arm_secure_wdt_start(void)
-{
- sbsa_wdog_start(SBSA_SECURE_WDOG_BASE, SBSA_SECURE_WDOG_TIMEOUT);
-}
-
-void plat_arm_secure_wdt_stop(void)
-{
- sbsa_wdog_stop(SBSA_SECURE_WDOG_BASE);
-}
diff --git a/plat/arm/board/tc0/tc0_security.c b/plat/arm/board/tc0/tc0_security.c
deleted file mode 100644
index f543762..0000000
--- a/plat/arm/board/tc0/tc0_security.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-#include <platform_def.h>
-
-static const arm_tzc_regions_info_t tzc_regions[] = {
- TC0_TZC_REGIONS_DEF,
- {}
-};
-
-/* Initialize the secure environment */
-void plat_arm_security_setup(void)
-{
- unsigned int i;
-
- for (i = 0U; i < TZC400_COUNT; i++) {
- arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
- }
-}
diff --git a/plat/arm/board/tc0/tc0_topology.c b/plat/arm/board/tc0/tc0_topology.c
deleted file mode 100644
index 8cfc3b5..0000000
--- a/plat/arm/board/tc0/tc0_topology.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-#include <plat/arm/css/common/css_pm.h>
-
-/******************************************************************************
- * The power domain tree descriptor.
- ******************************************************************************/
-const unsigned char tc0_pd_tree_desc[] = {
- PLAT_ARM_CLUSTER_COUNT,
- PLAT_MAX_CPUS_PER_CLUSTER,
-};
-
-/*******************************************************************************
- * This function returns the topology tree information.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
- return tc0_pd_tree_desc;
-}
-
-/*******************************************************************************
- * The array mapping platform core position (implemented by plat_my_core_pos())
- * to the SCMI power domain ID implemented by SCP.
- ******************************************************************************/
-const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
-};
-
-/*******************************************************************************
- * This function returns the core count within the cluster corresponding to
- * `mpidr`.
- ******************************************************************************/
-unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
-{
- return PLAT_MAX_CPUS_PER_CLUSTER;
-}
-
-#if ARM_PLAT_MT
-/******************************************************************************
- * Return the number of PE's supported by the CPU.
- *****************************************************************************/
-unsigned int plat_arm_get_cpu_pe_count(u_register_t mpidr)
-{
- return PLAT_MAX_PE_PER_CPU;
-}
-#endif
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index c90e93c..26af383 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,6 +14,7 @@
#include <common/debug.h>
#include <common/desc_image_load.h>
#include <drivers/generic_delay_timer.h>
+#include <drivers/partition/partition.h>
#include <lib/fconf/fconf.h>
#include <lib/fconf/fconf_dyn_cfg_getter.h>
#ifdef SPD_opteed
@@ -70,6 +71,12 @@
/* Initialise the IO layer and register platform IO devices */
plat_arm_io_setup();
+
+ /* Load partition table */
+#if ARM_GPT_SUPPORT
+ partition_init(GPT_IMAGE_ID);
+#endif /* ARM_GPT_SUPPORT */
+
}
void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
@@ -86,6 +93,11 @@
void bl2_plat_preload_setup(void)
{
arm_bl2_dyn_cfg_init();
+
+#if ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT
+ /* Always use the FIP from bank 0 */
+ arm_set_fip_addr(0U);
+#endif /* ARM_GPT_SUPPORT && !PSA_FWU_SUPPORT */
}
/*
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index 81ef6e7..b819888 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -148,27 +148,6 @@
bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
-#if defined(SPD_spmd) && !(ARM_LINUX_KERNEL_AS_BL33)
- /*
- * Hafnium in normal world expects its manifest address in x0, which
- * is loaded at base of DRAM.
- */
- bl33_image_ep_info.args.arg0 = (u_register_t)ARM_DRAM1_BASE;
-#endif
-
-# if ARM_LINUX_KERNEL_AS_BL33
- /*
- * According to the file ``Documentation/arm64/booting.txt`` of the
- * Linux kernel tree, Linux expects the physical address of the device
- * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
- * must be 0.
- */
- bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
- bl33_image_ep_info.args.arg1 = 0U;
- bl33_image_ep_info.args.arg2 = 0U;
- bl33_image_ep_info.args.arg3 = 0U;
-# endif
-
#else /* RESET_TO_BL31 */
/*
@@ -206,6 +185,27 @@
if (bl33_image_ep_info.pc == 0U)
panic();
#endif /* RESET_TO_BL31 */
+
+# if ARM_LINUX_KERNEL_AS_BL33
+ /*
+ * According to the file ``Documentation/arm64/booting.txt`` of the
+ * Linux kernel tree, Linux expects the physical address of the device
+ * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
+ * must be 0.
+ */
+ bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
+ bl33_image_ep_info.args.arg1 = 0U;
+ bl33_image_ep_info.args.arg2 = 0U;
+ bl33_image_ep_info.args.arg3 = 0U;
+# endif
+
+#if defined(SPD_spmd)
+ /*
+ * Hafnium in normal world expects its manifest address in x0, In CI
+ * configuration manifest is preloaded at 0x80000000(start of DRAM).
+ */
+ bl33_image_ep_info.args.arg0 = (u_register_t)ARM_DRAM1_BASE;
+#endif
}
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c
index 7d9fd6c..946b732 100644
--- a/plat/arm/common/arm_common.c
+++ b/plat/arm/common/arm_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -151,10 +151,10 @@
*/
mmio_write_32(ARM_SYS_TIMCTL_BASE + CNTCTLBASE_CNTFRQ, freq_val);
-#if defined(PLAT_juno) || defined(PLAT_n1sdp)
+#if defined(PLAT_juno) || defined(PLAT_n1sdp) || defined(PLAT_morello)
/*
* Initialize CNTFRQ register in Non-secure CNTBase frame.
- * This is only required for Juno and N1SDP, because they do not
+ * This is required for Juno, N1SDP and Morello because they do not
* follow ARM ARM in that the value updated in CNTFRQ is not
* reflected in CNTBASEN_CNTFRQ. Hence update the value manually.
*/
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 74afc53..4d5e8b4 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -86,11 +86,7 @@
$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
ifeq (${ARM_LINUX_KERNEL_AS_BL33},1)
- ifeq (${ARCH},aarch64)
- ifneq (${RESET_TO_BL31},1)
- $(error "ARM_LINUX_KERNEL_AS_BL33 is only available if RESET_TO_BL31=1.")
- endif
- else
+ ifneq (${ARCH},aarch64)
ifneq (${RESET_TO_SP_MIN},1)
$(error "ARM_LINUX_KERNEL_AS_BL33 is only available if RESET_TO_SP_MIN=1.")
endif
@@ -104,6 +100,11 @@
$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
endif
+# Arm Ethos-N NPU SiP service
+ARM_ETHOSN_NPU_DRIVER := 0
+$(eval $(call assert_boolean,ARM_ETHOSN_NPU_DRIVER))
+$(eval $(call add_define,ARM_ETHOSN_NPU_DRIVER))
+
# Use an implementation of SHA-256 with a smaller memory footprint but reduced
# speed.
$(eval $(call add_define,MBEDTLS_SHA256_SMALLER))
@@ -153,9 +154,9 @@
$(eval $(call assert_boolean,ARM_CRYPTOCELL_INTEG))
$(eval $(call add_define,ARM_CRYPTOCELL_INTEG))
-# Enable PIE support for RESET_TO_BL31 case
-ifeq (${RESET_TO_BL31},1)
- ENABLE_PIE := 1
+# Enable PIE support for RESET_TO_BL31/RESET_TO_SP_MIN case
+ifneq ($(filter 1,${RESET_TO_BL31} ${RESET_TO_SP_MIN}),)
+ ENABLE_PIE := 1
endif
# CryptoCell integration relies on coherent buffers for passing data from
@@ -166,6 +167,36 @@
endif
endif
+# Disable GPT parser support, use FIP image by default
+ARM_GPT_SUPPORT := 0
+$(eval $(call assert_boolean,ARM_GPT_SUPPORT))
+$(eval $(call add_define,ARM_GPT_SUPPORT))
+
+# Include necessary sources to parse GPT image
+ifeq (${ARM_GPT_SUPPORT}, 1)
+ BL2_SOURCES += drivers/partition/gpt.c \
+ drivers/partition/partition.c
+endif
+
+# Enable CRC instructions via extension for ARMv8-A CPUs.
+# For ARMv8.1-A, and onwards CRC instructions are default enabled.
+# Enable HW computed CRC support unconditionally in BL2 component.
+ifeq (${ARM_ARCH_MINOR},0)
+ BL2_CPPFLAGS += -march=armv8-a+crc
+endif
+
+ifeq ($(PSA_FWU_SUPPORT),1)
+ # GPT support is recommended as per PSA FWU specification hence
+ # PSA FWU implementation is tightly coupled with GPT support,
+ # and it does not support other formats.
+ ifneq ($(ARM_GPT_SUPPORT),1)
+ $(error For PSA_FWU_SUPPORT, ARM_GPT_SUPPORT must be enabled)
+ endif
+ FWU_MK := drivers/fwu/fwu.mk
+ $(info Including ${FWU_MK})
+ include ${FWU_MK}
+endif
+
ifeq (${ARCH}, aarch64)
PLAT_INCLUDES += -Iinclude/plat/arm/common/aarch64
endif
@@ -211,6 +242,7 @@
drivers/io/io_storage.c \
plat/arm/common/arm_bl2_setup.c \
plat/arm/common/arm_err.c \
+ common/tf_crc32.c \
${ARM_IO_SOURCES}
# Firmware Configuration Framework sources
@@ -221,7 +253,8 @@
DYN_CFG_SOURCES += plat/arm/common/arm_dyn_cfg.c \
plat/arm/common/arm_dyn_cfg_helpers.c \
- common/fdt_wrappers.c
+ common/fdt_wrappers.c \
+ common/uuid.c
BL1_SOURCES += ${DYN_CFG_SOURCES}
BL2_SOURCES += ${DYN_CFG_SOURCES}
@@ -235,8 +268,10 @@
ifeq (${JUNO_AARCH32_EL3_RUNTIME},1)
BL2_SOURCES += plat/arm/common/aarch32/arm_bl2_mem_params_desc.c
else
+ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),)
BL2_SOURCES += plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c
endif
+endif
BL2_SOURCES += plat/arm/common/arm_image_load.c \
common/desc_image_load.c
ifeq (${SPD},opteed)
@@ -252,14 +287,26 @@
plat/arm/common/arm_topology.c \
plat/common/plat_psci_common.c
-ifeq (${ENABLE_PMF}, 1)
+ifneq ($(filter 1,${ENABLE_PMF} ${ARM_ETHOSN_NPU_DRIVER}),)
+ARM_SVC_HANDLER_SRCS :=
+
+ifeq (${ENABLE_PMF},1)
+ARM_SVC_HANDLER_SRCS += lib/pmf/pmf_smc.c
+endif
+
+ifeq (${ARM_ETHOSN_NPU_DRIVER},1)
+ARM_SVC_HANDLER_SRCS += plat/arm/common/fconf/fconf_ethosn_getter.c \
+ drivers/delay_timer/delay_timer.c \
+ drivers/arm/ethosn/ethosn_smc.c
+endif
+
ifeq (${ARCH}, aarch64)
BL31_SOURCES += plat/arm/common/aarch64/execution_state_switch.c\
plat/arm/common/arm_sip_svc.c \
- lib/pmf/pmf_smc.c
+ ${ARM_SVC_HANDLER_SRCS}
else
BL32_SOURCES += plat/arm/common/arm_sip_svc.c \
- lib/pmf/pmf_smc.c
+ ${ARM_SVC_HANDLER_SRCS}
endif
endif
@@ -289,6 +336,7 @@
ifeq (${SPD},spmd)
BL31_SOURCES += plat/common/plat_spmd_manifest.c \
common/fdt_wrappers.c \
+ common/uuid.c \
${LIBFDT_SRCS}
endif
diff --git a/plat/arm/common/arm_dyn_cfg.c b/plat/arm/common/arm_dyn_cfg.c
index 6b3a611..30473be 100644
--- a/plat/arm/common/arm_dyn_cfg.c
+++ b/plat/arm/common/arm_dyn_cfg.c
@@ -208,10 +208,7 @@
HW_CONFIG_ID,
SOC_FW_CONFIG_ID,
NT_FW_CONFIG_ID,
-#if defined(SPD_tspd) || defined(SPD_spmd)
- /* tos_fw_config is only present for TSPD/SPMD */
TOS_FW_CONFIG_ID
-#endif
};
const struct dyn_cfg_dtb_info_t *dtb_info;
diff --git a/plat/arm/common/arm_image_load.c b/plat/arm/common/arm_image_load.c
index ed7f1f5..ebf6dff 100644
--- a/plat/arm/common/arm_image_load.c
+++ b/plat/arm/common/arm_image_load.c
@@ -38,38 +38,36 @@
******************************************************************************/
static void plat_add_sp_images_load_info(struct bl_load_info *load_info)
{
- bl_load_info_node_t *node_info = load_info->head;
- unsigned int index = 0;
+ bl_load_info_node_t *curr_node = load_info->head;
+ bl_load_info_node_t *prev_node;
- if (sp_mem_params_descs[index].image_id == 0) {
+ /* Shortcut for empty SP list */
+ if (sp_mem_params_descs[0].image_id == 0) {
ERROR("No Secure Partition Image available\n");
return;
}
/* Traverse through the bl images list */
do {
- node_info = node_info->next_load_info;
- } while (node_info->next_load_info != NULL);
+ curr_node = curr_node->next_load_info;
+ } while (curr_node->next_load_info != NULL);
- for (; index < MAX_SP_IDS; index++) {
+ prev_node = curr_node;
+
+ for (unsigned int index = 0; index < MAX_SP_IDS; index++) {
+ if (sp_mem_params_descs[index].image_id == 0) {
+ return;
+ }
+ curr_node = &sp_mem_params_descs[index].load_node_mem;
/* Populate the image information */
- node_info->image_id = sp_mem_params_descs[index].image_id;
- node_info->image_info = &sp_mem_params_descs[index].image_info;
+ curr_node->image_id = sp_mem_params_descs[index].image_id;
+ curr_node->image_info = &sp_mem_params_descs[index].image_info;
- if ((index + 1U) == MAX_SP_IDS) {
- INFO("Reached Max number of SPs\n");
- return;
- }
-
- if (sp_mem_params_descs[index + 1U].image_id == 0) {
- return;
- }
-
- node_info->next_load_info =
- &sp_mem_params_descs[index + 1U].load_node_mem;
- node_info = node_info->next_load_info;
-
+ prev_node->next_load_info = curr_node;
+ prev_node = curr_node;
}
+
+ INFO("Reached Max number of SPs\n");
}
#endif
diff --git a/plat/arm/common/arm_io_storage.c b/plat/arm/common/arm_io_storage.c
index 34b4101..387086a 100644
--- a/plat/arm/common/arm_io_storage.c
+++ b/plat/arm/common/arm_io_storage.c
@@ -1,14 +1,16 @@
/*
- * Copyright (c) 2015-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
+#include <drivers/fwu/fwu_metadata.h>
#include <drivers/io/io_driver.h>
#include <drivers/io/io_fip.h>
#include <drivers/io/io_memmap.h>
#include <drivers/io/io_storage.h>
+#include <drivers/partition/partition.h>
#include <lib/utils.h>
#include <plat/arm/common/arm_fconf_getter.h>
@@ -23,6 +25,13 @@
static const io_dev_connector_t *memmap_dev_con;
uintptr_t memmap_dev_handle;
+#if ARM_GPT_SUPPORT
+/* fip partition names */
+static const char * const fip_part_names[] = {"FIP_A", "FIP_B"};
+CASSERT(sizeof(fip_part_names)/sizeof(char *) == NR_OF_FW_BANKS,
+ assert_fip_partition_names_missing);
+#endif /* ARM_GPT_SUPPORT */
+
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak plat_arm_io_setup
#pragma weak plat_arm_get_alt_image_source
@@ -136,3 +145,106 @@
{
return (io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID) == 0);
}
+
+#if ARM_GPT_SUPPORT
+/******************************************************************************
+ * Retrieve partition entry details such as offset and length, and set these
+ * details in the I/O policy of the requested image.
+ *
+ * @image_id: image id whose I/O policy to be updated
+ *
+ * @part_name: partition name whose details to be retrieved
+ *
+ * Returns 0 on success, error otherwise
+ * Alongside, returns device handle and image specification of requested
+ * image.
+ ******************************************************************************/
+int arm_set_image_source(unsigned int image_id, const char *part_name,
+ uintptr_t *dev_handle, uintptr_t *image_spec)
+{
+ const partition_entry_t *entry = get_partition_entry(part_name);
+
+ if (entry == NULL) {
+ ERROR("Unable to find the %s partition\n", part_name);
+ return -ENOENT;
+ }
+
+ struct plat_io_policy *policy = FCONF_GET_PROPERTY(arm,
+ io_policies,
+ image_id);
+
+ assert(policy != NULL);
+ assert(policy->image_spec != 0UL);
+
+ io_block_spec_t *spec = (io_block_spec_t *)policy->image_spec;
+ /* set offset and length of the image */
+ spec->offset = PLAT_ARM_FLASH_IMAGE_BASE + entry->start;
+ spec->length = entry->length;
+
+ *dev_handle = *(policy->dev_handle);
+ *image_spec = policy->image_spec;
+
+ return 0;
+}
+
+/*******************************************************************************
+ * Set the source offset and length of the FIP image in its I/O policy.
+ *
+ * @active_fw_bank_idx: active firmware bank index gathered from FWU metadata.
+ ******************************************************************************/
+void arm_set_fip_addr(uint32_t active_fw_bank_idx)
+{
+ uintptr_t dev_handle __unused;
+ uintptr_t image_spec __unused;
+
+ assert(active_fw_bank_idx < NR_OF_FW_BANKS);
+
+ INFO("Booting with partition %s\n", fip_part_names[active_fw_bank_idx]);
+
+ int result = arm_set_image_source(FIP_IMAGE_ID,
+ fip_part_names[active_fw_bank_idx],
+ &dev_handle,
+ &image_spec);
+ if (result != 0) {
+ panic();
+ }
+}
+#endif /* ARM_GPT_SUPPORT */
+
+#if PSA_FWU_SUPPORT
+/*******************************************************************************
+ * Read the FIP partition of the GPT image corresponding to the active firmware
+ * bank to get its offset and length, and update these details in the I/O policy
+ * of the FIP image.
+ ******************************************************************************/
+void plat_fwu_set_images_source(struct fwu_metadata *metadata)
+{
+ arm_set_fip_addr(metadata->active_index);
+}
+
+/*******************************************************************************
+ * Read the requested FWU metadata partition of the GPT image to get its offset
+ * and length, and update these details in the I/O policy of the requested FWU
+ * metadata image.
+ ******************************************************************************/
+int plat_fwu_set_metadata_image_source(unsigned int image_id,
+ uintptr_t *dev_handle,
+ uintptr_t *image_spec)
+{
+ int result = -1;
+
+ if (image_id == FWU_METADATA_IMAGE_ID) {
+ result = arm_set_image_source(FWU_METADATA_IMAGE_ID,
+ "FWU-Metadata",
+ dev_handle,
+ image_spec);
+ } else if (image_id == BKUP_FWU_METADATA_IMAGE_ID) {
+ result = arm_set_image_source(BKUP_FWU_METADATA_IMAGE_ID,
+ "Bkup-FWU-Metadata",
+ dev_handle,
+ image_spec);
+ }
+
+ return result;
+}
+#endif /* PSA_FWU_SUPPORT */
diff --git a/plat/arm/common/arm_sip_svc.c b/plat/arm/common/arm_sip_svc.c
index 9f5d455..6456c78 100644
--- a/plat/arm/common/arm_sip_svc.c
+++ b/plat/arm/common/arm_sip_svc.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019,2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,6 +8,7 @@
#include <common/debug.h>
#include <common/runtime_svc.h>
+#include <drivers/arm/ethosn.h>
#include <lib/debugfs.h>
#include <lib/pmf/pmf.h>
#include <plat/arm/common/arm_sip_svc.h>
@@ -50,6 +51,8 @@
{
int call_count = 0;
+#if ENABLE_PMF
+
/*
* Dispatch PMF calls to PMF SMC handler and return its return
* value
@@ -59,6 +62,8 @@
handle, flags);
}
+#endif /* ENABLE_PMF */
+
#if USE_DEBUGFS
if (is_debugfs_fid(smc_fid)) {
@@ -68,6 +73,15 @@
#endif /* USE_DEBUGFS */
+#if ARM_ETHOSN_NPU_DRIVER
+
+ if (is_ethosn_fid(smc_fid)) {
+ return ethosn_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
+ handle, flags);
+ }
+
+#endif /* ARM_ETHOSN_NPU_DRIVER */
+
switch (smc_fid) {
case ARM_SIP_SVC_EXE_STATE_SWITCH: {
/* Execution state can be switched only if EL3 is AArch64 */
@@ -92,6 +106,11 @@
/* PMF calls */
call_count += PMF_NUM_SMC_CALLS;
+#if ARM_ETHOSN_NPU_DRIVER
+ /* ETHOSN calls */
+ call_count += ETHOSN_NUM_SMC_CALLS;
+#endif /* ARM_ETHOSN_NPU_DRIVER */
+
/* State switch call */
call_count += 1;
diff --git a/plat/arm/common/fconf/arm_fconf_io.c b/plat/arm/common/fconf/arm_fconf_io.c
index 48286c2..86fd6d5 100644
--- a/plat/arm/common/fconf/arm_fconf_io.c
+++ b/plat/arm/common/fconf/arm_fconf_io.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,6 +9,7 @@
#include <common/debug.h>
#include <common/fdt_wrappers.h>
#include <drivers/io/io_storage.h>
+#include <drivers/partition/partition.h>
#include <lib/object_pool.h>
#include <libfdt.h>
#include <tools_share/firmware_image_package.h>
@@ -17,11 +18,40 @@
#include <plat/arm/common/arm_fconf_io_storage.h>
#include <platform_def.h>
-const io_block_spec_t fip_block_spec = {
- .offset = PLAT_ARM_FIP_BASE,
- .length = PLAT_ARM_FIP_MAX_SIZE
+#if PSA_FWU_SUPPORT
+/* metadata entry details */
+static io_block_spec_t fwu_metadata_spec;
+#endif /* PSA_FWU_SUPPORT */
+
+io_block_spec_t fip_block_spec = {
+/*
+ * This is fixed FIP address used by BL1, BL2 loads partition table
+ * to get FIP address.
+ */
+#if ARM_GPT_SUPPORT
+ .offset = PLAT_ARM_FLASH_IMAGE_BASE + PLAT_ARM_FIP_OFFSET_IN_GPT,
+#else
+ .offset = PLAT_ARM_FLASH_IMAGE_BASE,
+#endif /* ARM_GPT_SUPPORT */
+ .length = PLAT_ARM_FLASH_IMAGE_MAX_SIZE
};
+#if ARM_GPT_SUPPORT
+static const io_block_spec_t gpt_spec = {
+ .offset = PLAT_ARM_FLASH_IMAGE_BASE,
+ /*
+ * PLAT_PARTITION_BLOCK_SIZE = 512
+ * PLAT_PARTITION_MAX_ENTRIES = 128
+ * each sector has 4 partition entries, and there are
+ * 2 reserved sectors i.e. protective MBR and primary
+ * GPT header hence length gets calculated as,
+ * length = 512 * (128/4 + 2)
+ */
+ .length = PLAT_PARTITION_BLOCK_SIZE *
+ (PLAT_PARTITION_MAX_ENTRIES / 4 + 2),
+};
+#endif /* ARM_GPT_SUPPORT */
+
const io_uuid_spec_t arm_uuid_spec[MAX_NUMBER_IDS] = {
[BL2_IMAGE_ID] = {UUID_TRUSTED_BOOT_FIRMWARE_BL2},
[TB_FW_CONFIG_ID] = {UUID_TB_FW_CONFIG},
@@ -60,6 +90,27 @@
/* By default, ARM platforms load images from the FIP */
struct plat_io_policy policies[MAX_NUMBER_IDS] = {
+#if ARM_GPT_SUPPORT
+ [GPT_IMAGE_ID] = {
+ &memmap_dev_handle,
+ (uintptr_t)&gpt_spec,
+ open_memmap
+ },
+#endif /* ARM_GPT_SUPPORT */
+#if PSA_FWU_SUPPORT
+ [FWU_METADATA_IMAGE_ID] = {
+ &memmap_dev_handle,
+ /* filled runtime from partition information */
+ (uintptr_t)&fwu_metadata_spec,
+ open_memmap
+ },
+ [BKUP_FWU_METADATA_IMAGE_ID] = {
+ &memmap_dev_handle,
+ /* filled runtime from partition information */
+ (uintptr_t)&fwu_metadata_spec,
+ open_memmap
+ },
+#endif /* PSA_FWU_SUPPORT */
[FIP_IMAGE_ID] = {
&memmap_dev_handle,
(uintptr_t)&fip_block_spec,
@@ -249,7 +300,6 @@
{
int err, node;
unsigned int i;
- unsigned int j;
union uuid_helper_t uuid_helper;
io_uuid_spec_t *uuid_ptr;
@@ -268,26 +318,26 @@
/* Locate the uuid cells and read the value for all the load info uuid */
for (i = 0; i < FCONF_ARM_IO_UUID_NUMBER; i++) {
uuid_ptr = pool_alloc(&fconf_arm_uuids_pool);
- err = fdt_read_uint32_array(dtb, node, load_info[i].name,
- 4, uuid_helper.word);
+ err = fdtw_read_uuid(dtb, node, load_info[i].name, 16,
+ (uint8_t *)&uuid_helper);
if (err < 0) {
WARN("FCONF: Read cell failed for %s\n", load_info[i].name);
return err;
}
- /* Convert uuid from big endian to little endian */
- for (j = 0U; j < 4U; j++) {
- uuid_helper.word[j] =
- ((uuid_helper.word[j] >> 24U) & 0xff) |
- ((uuid_helper.word[j] << 8U) & 0xff0000) |
- ((uuid_helper.word[j] >> 8U) & 0xff00) |
- ((uuid_helper.word[j] << 24U) & 0xff000000);
- }
-
- VERBOSE("FCONF: arm-io_policies.%s cell found with value = 0x%x 0x%x 0x%x 0x%x\n",
+ VERBOSE("FCONF: arm-io_policies.%s cell found with value = "
+ "%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x\n",
load_info[i].name,
- uuid_helper.word[0], uuid_helper.word[1],
- uuid_helper.word[2], uuid_helper.word[3]);
+ uuid_helper.uuid_struct.time_low[0], uuid_helper.uuid_struct.time_low[1],
+ uuid_helper.uuid_struct.time_low[2], uuid_helper.uuid_struct.time_low[3],
+ uuid_helper.uuid_struct.time_mid[0], uuid_helper.uuid_struct.time_mid[1],
+ uuid_helper.uuid_struct.time_hi_and_version[0],
+ uuid_helper.uuid_struct.time_hi_and_version[1],
+ uuid_helper.uuid_struct.clock_seq_hi_and_reserved,
+ uuid_helper.uuid_struct.clock_seq_low,
+ uuid_helper.uuid_struct.node[0], uuid_helper.uuid_struct.node[1],
+ uuid_helper.uuid_struct.node[2], uuid_helper.uuid_struct.node[3],
+ uuid_helper.uuid_struct.node[4], uuid_helper.uuid_struct.node[5]);
uuid_ptr->uuid = uuid_helper.uuid_struct;
policies[load_info[i].image_id].image_spec = (uintptr_t)uuid_ptr;
diff --git a/plat/arm/common/fconf/arm_fconf_sp.c b/plat/arm/common/fconf/arm_fconf_sp.c
index 7950e7f..552393c 100644
--- a/plat/arm/common/fconf/arm_fconf_sp.c
+++ b/plat/arm/common/fconf/arm_fconf_sp.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -37,7 +37,6 @@
const unsigned int plat_start = SP_PKG5_ID;
unsigned int plat_index = plat_start;
const unsigned int plat_end = plat_start + MAX_SP_IDS / 2;
- unsigned int j;
/* As libfdt use void *, we can't avoid this cast */
const void *dtb = (void *)config;
@@ -59,29 +58,28 @@
}
/* Read UUID */
- err = fdt_read_uint32_array(dtb, sp_node, "uuid", 4,
- uuid_helper.word);
+ err = fdtw_read_uuid(dtb, sp_node, "uuid", 16,
+ (uint8_t *)&uuid_helper);
if (err < 0) {
ERROR("FCONF: cannot read SP uuid\n");
return -1;
}
- /* Convert uuid from big endian to little endian */
- for (j = 0U; j < 4U; j++) {
- uuid_helper.word[j] =
- ((uuid_helper.word[j] >> 24U) & 0xff) |
- ((uuid_helper.word[j] << 8U) & 0xff0000) |
- ((uuid_helper.word[j] >> 8U) & 0xff00) |
- ((uuid_helper.word[j] << 24U) & 0xff000000);
- }
-
arm_sp.uuids[index] = uuid_helper;
- VERBOSE("FCONF: %s UUID %x-%x-%x-%x load_addr=%lx\n",
+ VERBOSE("FCONF: %s UUID"
+ " %02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x"
+ " load_addr=%lx\n",
__func__,
- uuid_helper.word[0],
- uuid_helper.word[1],
- uuid_helper.word[2],
- uuid_helper.word[3],
+ uuid_helper.uuid_struct.time_low[0], uuid_helper.uuid_struct.time_low[1],
+ uuid_helper.uuid_struct.time_low[2], uuid_helper.uuid_struct.time_low[3],
+ uuid_helper.uuid_struct.time_mid[0], uuid_helper.uuid_struct.time_mid[1],
+ uuid_helper.uuid_struct.time_hi_and_version[0],
+ uuid_helper.uuid_struct.time_hi_and_version[1],
+ uuid_helper.uuid_struct.clock_seq_hi_and_reserved,
+ uuid_helper.uuid_struct.clock_seq_low,
+ uuid_helper.uuid_struct.node[0], uuid_helper.uuid_struct.node[1],
+ uuid_helper.uuid_struct.node[2], uuid_helper.uuid_struct.node[3],
+ uuid_helper.uuid_struct.node[4], uuid_helper.uuid_struct.node[5],
arm_sp.load_addr[index]);
/* Read Load address */
diff --git a/plat/arm/common/fconf/fconf_ethosn_getter.c b/plat/arm/common/fconf/fconf_ethosn_getter.c
new file mode 100644
index 0000000..1ba9f3a
--- /dev/null
+++ b/plat/arm/common/fconf/fconf_ethosn_getter.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2021, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <common/fdt_wrappers.h>
+#include <libfdt.h>
+#include <plat/arm/common/fconf_ethosn_getter.h>
+
+struct ethosn_config_t ethosn_config;
+
+static uint8_t fdt_node_get_status(const void *fdt, int node)
+{
+ int len;
+ uint8_t status = ETHOSN_STATUS_DISABLED;
+ const char *node_status;
+
+ node_status = fdt_getprop(fdt, node, "status", &len);
+ if (node_status == NULL ||
+ (len == 5 && /* Includes null character */
+ strncmp(node_status, "okay", 4U) == 0)) {
+ status = ETHOSN_STATUS_ENABLED;
+ }
+
+ return status;
+}
+
+int fconf_populate_ethosn_config(uintptr_t config)
+{
+ int ethosn_node;
+ int sub_node;
+ uint8_t ethosn_status;
+ uint32_t core_count = 0U;
+ uint32_t core_addr_idx = 0U;
+ const void *hw_conf_dtb = (const void *)config;
+
+ /* Find offset to node with 'ethosn' compatible property */
+ ethosn_node = fdt_node_offset_by_compatible(hw_conf_dtb, -1, "ethosn");
+ if (ethosn_node < 0) {
+ ERROR("FCONF: Can't find 'ethosn' compatible node in dtb\n");
+ return ethosn_node;
+ }
+
+ /* If the Arm Ethos-N NPU is disabled the core check can be skipped */
+ ethosn_status = fdt_node_get_status(hw_conf_dtb, ethosn_node);
+ if (ethosn_status == ETHOSN_STATUS_DISABLED) {
+ return 0;
+ }
+
+ fdt_for_each_subnode(sub_node, hw_conf_dtb, ethosn_node) {
+ int err;
+ uintptr_t addr;
+ uint8_t status;
+
+ /* Check that the sub node is "ethosn-core" compatible */
+ if (fdt_node_check_compatible(hw_conf_dtb, sub_node,
+ "ethosn-core") != 0) {
+ /* Ignore incompatible sub node */
+ continue;
+ }
+
+ /* Including disabled cores */
+ if (core_addr_idx >= ETHOSN_CORE_NUM_MAX) {
+ ERROR("FCONF: Reached max number of Arm Ethos-N NPU cores\n");
+ return -1;
+ }
+
+ status = fdt_node_get_status(hw_conf_dtb, ethosn_node);
+ if (status == ETHOSN_STATUS_DISABLED) {
+ ++core_addr_idx;
+ continue;
+ }
+
+ err = fdt_get_reg_props_by_index(hw_conf_dtb, ethosn_node,
+ core_addr_idx, &addr, NULL);
+ if (err < 0) {
+ ERROR("FCONF: Failed to read reg property for Arm Ethos-N NPU core %u\n",
+ core_addr_idx);
+ return err;
+ }
+
+ ethosn_config.core_addr[core_count++] = addr;
+ ++core_addr_idx;
+ }
+
+ if ((sub_node < 0) && (sub_node != -FDT_ERR_NOTFOUND)) {
+ ERROR("FCONF: Failed to parse sub nodes\n");
+ return sub_node;
+ }
+
+ /* The Arm Ethos-N NPU can't be used if no cores were found */
+ if (core_count == 0) {
+ ERROR("FCONF: No Arm Ethos-N NPU cores found\n");
+ return -1;
+ }
+
+ ethosn_config.num_cores = core_count;
+ ethosn_config.status = ethosn_status;
+
+ return 0;
+}
+
+FCONF_REGISTER_POPULATOR(HW_CONFIG, ethosn_config, fconf_populate_ethosn_config);
diff --git a/plat/arm/common/sp_min/arm_sp_min_setup.c b/plat/arm/common/sp_min/arm_sp_min_setup.c
index 270093c..f15c137 100644
--- a/plat/arm/common/sp_min/arm_sp_min_setup.c
+++ b/plat/arm/common/sp_min/arm_sp_min_setup.c
@@ -32,7 +32,9 @@
* Check that BL32_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page
* is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2.
*/
+#if !RESET_TO_SP_MIN
CASSERT(BL32_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl32_base_overflows);
+#endif
/*******************************************************************************
* Return a pointer to the 'entry_point_info' structure of the next image for the
diff --git a/plat/arm/css/sgi/include/sgi_base_platform_def.h b/plat/arm/css/sgi/include/sgi_base_platform_def.h
index b805746..d795f25 100644
--- a/plat/arm/css/sgi/include/sgi_base_platform_def.h
+++ b/plat/arm/css/sgi/include/sgi_base_platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -26,14 +26,17 @@
/*
* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
- * plat_arm_mmap array defined for each BL stage.
+ * plat_arm_mmap array defined for each BL stage. In addition to that, on
+ * multi-chip platforms, address regions on each of the remote chips are
+ * also mapped. In BL31, for instance, three address regions on the remote
+ * chips are accessed - secure ram, css device and soc device regions.
*/
#if defined(IMAGE_BL31)
# if SPM_MM
-# define PLAT_ARM_MMAP_ENTRIES 9
-# define MAX_XLAT_TABLES 7
-# define PLAT_SP_IMAGE_MMAP_REGIONS 7
-# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10
+# define PLAT_ARM_MMAP_ENTRIES (9 + ((CSS_SGI_CHIP_COUNT - 1) * 3))
+# define MAX_XLAT_TABLES (7 + ((CSS_SGI_CHIP_COUNT - 1) * 3))
+# define PLAT_SP_IMAGE_MMAP_REGIONS 9
+# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 11
# else
# define PLAT_ARM_MMAP_ENTRIES (5 + ((CSS_SGI_CHIP_COUNT - 1) * 3))
# define MAX_XLAT_TABLES (6 + ((CSS_SGI_CHIP_COUNT - 1) * 3))
@@ -41,6 +44,17 @@
#elif defined(IMAGE_BL32)
# define PLAT_ARM_MMAP_ENTRIES 8
# define MAX_XLAT_TABLES 5
+#elif defined(IMAGE_BL2)
+# define PLAT_ARM_MMAP_ENTRIES (11 + (CSS_SGI_CHIP_COUNT - 1))
+
+/*
+ * MAX_XLAT_TABLES entries need to be doubled because when the address width
+ * exceeds 40 bits an additional level of translation is required. In case of
+ * multichip platforms peripherals also fall into address space with width
+ * > 40 bits
+ *
+ */
+# define MAX_XLAT_TABLES (7 + ((CSS_SGI_CHIP_COUNT - 1) * 2))
#elif !USE_ROMLIB
# define PLAT_ARM_MMAP_ENTRIES 11
# define MAX_XLAT_TABLES 7
@@ -69,12 +83,17 @@
/*
* PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
- * little space for growth.
+ * little space for growth. Additional 8KiB space is added per chip in
+ * order to accommodate the additional level of translation required for "TZC"
+ * peripheral access which lies in >4TB address space.
+ *
*/
#if TRUSTED_BOARD_BOOT
-# define PLAT_ARM_MAX_BL2_SIZE 0x1D000
+# define PLAT_ARM_MAX_BL2_SIZE (0x1D000 + ((CSS_SGI_CHIP_COUNT - 1) * \
+ 0x2000))
#else
-# define PLAT_ARM_MAX_BL2_SIZE 0x14000
+# define PLAT_ARM_MAX_BL2_SIZE (0x14000 + ((CSS_SGI_CHIP_COUNT - 1) * \
+ 0x2000))
#endif
/*
@@ -165,48 +184,36 @@
#define PLAT_SP_PRI PLAT_RAS_PRI
-#if RAS_EXTENSION
-/* Allocate 128KB for CPER buffers */
-#define PLAT_SP_BUF_BASE ULL(0x20000)
-
-#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
- PLAT_SP_IMAGE_NS_BUF_SIZE + \
- PLAT_SP_BUF_BASE)
-
-/* Platform specific SMC FID's used for RAS */
-#define SP_DMC_ERROR_INJECT_EVENT_AARCH64 0xC4000042
-#define SP_DMC_ERROR_INJECT_EVENT_AARCH32 0x84000042
-
-#define SP_DMC_ERROR_OVERFLOW_EVENT_AARCH64 0xC4000043
-#define SP_DMC_ERROR_OVERFLOW_EVENT_AARCH32 0x84000043
-
-#define SP_DMC_ERROR_ECC_EVENT_AARCH64 0xC4000044
-#define SP_DMC_ERROR_ECC_EVENT_AARCH32 0x84000044
-
-/* ARM SDEI dynamic shared event numbers */
-#define SGI_SDEI_DS_EVENT_0 804
-#define SGI_SDEI_DS_EVENT_1 805
-
-#define PLAT_ARM_PRIVATE_SDEI_EVENTS \
- SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \
- SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_0, SDEI_MAPF_CRITICAL), \
- SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_1, SDEI_MAPF_CRITICAL),
-#define PLAT_ARM_SHARED_SDEI_EVENTS
-
-#define ARM_SP_CPER_BUF_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
- PLAT_SP_IMAGE_NS_BUF_SIZE)
-#define ARM_SP_CPER_BUF_SIZE ULL(0x20000)
-#define ARM_SP_CPER_BUF_MMAP MAP_REGION2( \
- ARM_SP_CPER_BUF_BASE, \
- ARM_SP_CPER_BUF_BASE, \
- ARM_SP_CPER_BUF_SIZE, \
- MT_RW_DATA | MT_NS | MT_USER, \
+#if SPM_MM && RAS_EXTENSION
+/*
+ * CPER buffer memory of 128KB is reserved and it is placed adjacent to the
+ * memory shared between EL3 and S-EL0.
+ */
+#define CSS_SGI_SP_CPER_BUF_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
+ PLAT_SP_IMAGE_NS_BUF_SIZE)
+#define CSS_SGI_SP_CPER_BUF_SIZE ULL(0x20000)
+#define CSS_SGI_SP_CPER_BUF_MMAP MAP_REGION2( \
+ CSS_SGI_SP_CPER_BUF_BASE, \
+ CSS_SGI_SP_CPER_BUF_BASE, \
+ CSS_SGI_SP_CPER_BUF_SIZE, \
+ MT_RW_DATA | MT_NS | MT_USER, \
PAGE_SIZE)
-#else
+/*
+ * Secure partition stack follows right after the memory space reserved for
+ * CPER buffer memory.
+ */
+#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
+ PLAT_SP_IMAGE_NS_BUF_SIZE + \
+ CSS_SGI_SP_CPER_BUF_SIZE)
+#elif SPM_MM
+/*
+ * Secure partition stack follows right after the memory region that is shared
+ * between EL3 and S-EL0.
+ */
#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
PLAT_SP_IMAGE_NS_BUF_SIZE)
-#endif /* RAS_EXTENSION */
+#endif /* SPM_MM && RAS_EXTENSION */
/* Platform ID address */
#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
@@ -238,4 +245,17 @@
/* Number of SCMI channels on the platform */
#define PLAT_ARM_SCMI_CHANNEL_COUNT CSS_SGI_CHIP_COUNT
+/*
+ * Mapping definition of the TrustZone Controller for ARM SGI/RD platforms
+ * where both the DRAM regions are marked for non-secure access. This applies
+ * to multi-chip platforms.
+ */
+#define SGI_PLAT_TZC_NS_REMOTE_REGIONS_DEF(n) \
+ {CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_BASE, \
+ CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_END, \
+ ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}, \
+ {CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_BASE, \
+ CSS_SGI_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_END, \
+ ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}
+
#endif /* SGI_BASE_PLATFORM_DEF_H */
diff --git a/plat/arm/css/sgi/include/sgi_dmc620_tzc_regions.h b/plat/arm/css/sgi/include/sgi_dmc620_tzc_regions.h
new file mode 100644
index 0000000..e939163
--- /dev/null
+++ b/plat/arm/css/sgi/include/sgi_dmc620_tzc_regions.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SGI_DMC620_TZC_REGIONS_H
+#define SGI_DMC620_TZC_REGIONS_H
+
+#include <drivers/arm/tzc_dmc620.h>
+
+#if SPM_MM
+#define CSS_SGI_DMC620_TZC_REGIONS_DEF \
+ { \
+ .region_base = ARM_AP_TZC_DRAM1_BASE, \
+ .region_top = PLAT_SP_IMAGE_NS_BUF_BASE - 1, \
+ .sec_attr = TZC_DMC620_REGION_S_RDWR \
+ }, { \
+ .region_base = PLAT_SP_IMAGE_NS_BUF_BASE, \
+ .region_top = PLAT_ARM_SP_IMAGE_STACK_BASE - 1, \
+ .sec_attr = TZC_DMC620_REGION_S_NS_RDWR \
+ }, { \
+ .region_base = PLAT_ARM_SP_IMAGE_STACK_BASE, \
+ .region_top = ARM_AP_TZC_DRAM1_END, \
+ .sec_attr = TZC_DMC620_REGION_S_RDWR \
+ }
+#else
+#define CSS_SGI_DMC620_TZC_REGIONS_DEF \
+ { \
+ .region_base = ARM_AP_TZC_DRAM1_BASE, \
+ .region_top = ARM_AP_TZC_DRAM1_END, \
+ .sec_attr = TZC_DMC620_REGION_S_RDWR \
+ }
+#endif /* SPM_MM */
+
+#endif /* SGI_DMC620_TZC_REGIONS_H */
diff --git a/plat/arm/css/sgi/include/sgi_ras.h b/plat/arm/css/sgi/include/sgi_ras.h
index a449eae..e69a684 100644
--- a/plat/arm/css/sgi/include/sgi_ras.h
+++ b/plat/arm/css/sgi/include/sgi_ras.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,7 +12,6 @@
* id used with Standalone MM code
*/
struct sgi_ras_ev_map {
- int ras_ev_num; /* RAS Event number */
int sdei_ev_num; /* SDEI Event number */
int intr; /* Physical intr number */
};
diff --git a/plat/arm/css/sgi/include/sgi_sdei.h b/plat/arm/css/sgi/include/sgi_sdei.h
new file mode 100644
index 0000000..f380122
--- /dev/null
+++ b/plat/arm/css/sgi/include/sgi_sdei.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SGI_SDEI_H
+#define SGI_SDEI_H
+
+#if SDEI_SUPPORT
+
+/* ARM SDEI dynamic shared event numbers */
+#define SGI_SDEI_DS_EVENT_0 U(804)
+#define SGI_SDEI_DS_EVENT_1 U(805)
+
+#define PLAT_ARM_PRIVATE_SDEI_EVENTS \
+ SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \
+ SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_0, SDEI_MAPF_CRITICAL), \
+ SDEI_EXPLICIT_EVENT(SGI_SDEI_DS_EVENT_1, SDEI_MAPF_CRITICAL),
+
+#define PLAT_ARM_SHARED_SDEI_EVENTS
+
+#endif /* SDEI_SUPPORT */
+
+#endif /* SGI_SDEI_H */
diff --git a/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h b/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h
index 03f1073..bebc597 100644
--- a/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h
+++ b/plat/arm/css/sgi/include/sgi_soc_css_def_v2.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -70,6 +70,18 @@
SOC_PLATFORM_PERIPH_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE)
+#if SPM_MM
+/*
+ * Memory map definition for the platform peripheral memory region that is
+ * accessible from S-EL0 (with secure user mode access).
+ */
+#define SOC_PLATFORM_PERIPH_MAP_DEVICE_USER \
+ MAP_REGION_FLAT( \
+ SOC_PLATFORM_PERIPH_BASE, \
+ SOC_PLATFORM_PERIPH_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
+#endif
+
#define SOC_SYSTEM_PERIPH_MAP_DEVICE MAP_REGION_FLAT( \
SOC_SYSTEM_PERIPH_BASE, \
SOC_SYSTEM_PERIPH_SIZE, \
@@ -172,8 +184,18 @@
#define MAX_IO_HANDLES U(4)
/* Reserve the last block of flash for PSCI MEM PROTECT flag */
-#define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE
-#define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE
+#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+#if ARM_GPT_SUPPORT
+/*
+ * Offset of the FIP in the GPT image. BL1 component uses this option
+ * as it does not load the partition table to get the FIP base
+ * address. At sector 34 by default (i.e. after reserved sectors 0-33)
+ * Offset = 34 * 512(sector size) = 17408 i.e. 0x4400
+ */
+#define PLAT_ARM_FIP_OFFSET_IN_GPT 0x4400
+#endif /* ARM_GPT_SUPPORT */
#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
diff --git a/plat/arm/css/sgi/include/sgi_soc_platform_def.h b/plat/arm/css/sgi/include/sgi_soc_platform_def.h
index d7a839a..405d62f 100644
--- a/plat/arm/css/sgi/include/sgi_soc_platform_def.h
+++ b/plat/arm/css/sgi/include/sgi_soc_platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,4 +12,22 @@
#include <plat/arm/board/common/v2m_def.h>
#include <plat/arm/soc/common/soc_css_def.h>
+/* Map the System registers to access from S-EL0 */
+#define CSS_SYSTEMREG_DEVICE_BASE (0x1C010000)
+#define CSS_SYSTEMREG_DEVICE_SIZE (0x00010000)
+#define PLAT_ARM_SECURE_MAP_SYSTEMREG MAP_REGION_FLAT( \
+ CSS_SYSTEMREG_DEVICE_BASE, \
+ CSS_SYSTEMREG_DEVICE_SIZE, \
+ (MT_DEVICE | MT_RW | \
+ MT_SECURE | MT_USER))
+
+/* Map the NOR2 Flash to access from S-EL0 */
+#define CSS_NOR2_FLASH_DEVICE_BASE (0x10000000)
+#define CSS_NOR2_FLASH_DEVICE_SIZE (0x04000000)
+#define PLAT_ARM_SECURE_MAP_NOR2 MAP_REGION_FLAT( \
+ CSS_NOR2_FLASH_DEVICE_BASE, \
+ CSS_NOR2_FLASH_DEVICE_SIZE, \
+ (MT_DEVICE | MT_RW | \
+ MT_SECURE | MT_USER))
+
#endif /* SGI_SOC_PLATFORM_DEF_H */
diff --git a/plat/arm/css/sgi/include/sgi_soc_platform_def_v2.h b/plat/arm/css/sgi/include/sgi_soc_platform_def_v2.h
index cb747c3..20dd682 100644
--- a/plat/arm/css/sgi/include/sgi_soc_platform_def_v2.h
+++ b/plat/arm/css/sgi/include/sgi_soc_platform_def_v2.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,4 +10,22 @@
#include <sgi_base_platform_def.h>
#include <sgi_soc_css_def_v2.h>
+/* Map the System registers to access from S-EL0 */
+#define CSS_SYSTEMREG_DEVICE_BASE (0x0C010000)
+#define CSS_SYSTEMREG_DEVICE_SIZE (0x00010000)
+#define PLAT_ARM_SECURE_MAP_SYSTEMREG MAP_REGION_FLAT( \
+ CSS_SYSTEMREG_DEVICE_BASE, \
+ CSS_SYSTEMREG_DEVICE_SIZE, \
+ (MT_DEVICE | MT_RW | \
+ MT_SECURE | MT_USER))
+
+/* Map the NOR2 Flash to access from S-EL0 */
+#define CSS_NOR2_FLASH_DEVICE_BASE (0x001054000000)
+#define CSS_NOR2_FLASH_DEVICE_SIZE (0x000004000000)
+#define PLAT_ARM_SECURE_MAP_NOR2 MAP_REGION_FLAT( \
+ CSS_NOR2_FLASH_DEVICE_BASE, \
+ CSS_NOR2_FLASH_DEVICE_SIZE, \
+ (MT_DEVICE | MT_RW | \
+ MT_SECURE | MT_USER))
+
#endif /* SGI_SOC_PLATFORM_DEF_V2_H */
diff --git a/plat/arm/css/sgi/include/sgi_variant.h b/plat/arm/css/sgi/include/sgi_variant.h
index ecf6d93..0062b97 100644
--- a/plat/arm/css/sgi/include/sgi_variant.h
+++ b/plat/arm/css/sgi/include/sgi_variant.h
@@ -20,6 +20,9 @@
/* SID Version values for RD-N2 */
#define RD_N2_SID_VER_PART_NUM 0x07B7
+/* SID Version values for RD-N2 variants */
+#define RD_N2_CFG1_SID_VER_PART_NUM 0x07B6
+
/* Structure containing SGI platform variant information */
typedef struct sgi_platform_info {
unsigned int platform_id; /* Part Number of the platform */
diff --git a/plat/arm/css/sgi/sgi-common.mk b/plat/arm/css/sgi/sgi-common.mk
index 615f53d..8baf4ee 100644
--- a/plat/arm/css/sgi/sgi-common.mk
+++ b/plat/arm/css/sgi/sgi-common.mk
@@ -18,6 +18,8 @@
CSS_SGI_CHIP_COUNT := 1
+CSS_SGI_PLATFORM_VARIANT := 0
+
INTERCONNECT_SOURCES := ${CSS_ENT_BASE}/sgi_interconnect.c
PLAT_INCLUDES += -I${CSS_ENT_BASE}/include
@@ -57,10 +59,14 @@
$(eval $(call add_define,CSS_SGI_CHIP_COUNT))
+$(eval $(call add_define,CSS_SGI_PLATFORM_VARIANT))
+
override CSS_LOAD_SCP_IMAGES := 0
override NEED_BL2U := no
override ARM_BL31_IN_DRAM := 1
override ARM_PLAT_MT := 1
+override PSCI_EXTENDED_STATE_ID := 1
+override ARM_RECOM_STATE_ID_ENC := 1
# System coherency is managed in hardware
HW_ASSISTED_COHERENCY := 1
diff --git a/plat/arm/css/sgi/sgi_bl31_setup.c b/plat/arm/css/sgi/sgi_bl31_setup.c
index 36c3fbb..541689b 100644
--- a/plat/arm/css/sgi/sgi_bl31_setup.c
+++ b/plat/arm/css/sgi/sgi_bl31_setup.c
@@ -28,7 +28,7 @@
.ring_doorbell = &mhu_ring_doorbell,
};
-static scmi_channel_plat_info_t rd_n1e1_edge_scmi_plat_info[] = {
+static scmi_channel_plat_info_t plat_rd_scmi_info[] = {
{
.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
.db_reg_addr = PLAT_CSS_MHU_BASE + SENDER_REG_SET(0),
@@ -75,10 +75,11 @@
{
if (sgi_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM ||
sgi_plat_info.platform_id == RD_V1_SID_VER_PART_NUM ||
- sgi_plat_info.platform_id == RD_N2_SID_VER_PART_NUM) {
- if (channel_id >= ARRAY_SIZE(rd_n1e1_edge_scmi_plat_info))
+ sgi_plat_info.platform_id == RD_N2_SID_VER_PART_NUM ||
+ sgi_plat_info.platform_id == RD_N2_CFG1_SID_VER_PART_NUM) {
+ if (channel_id >= ARRAY_SIZE(plat_rd_scmi_info))
panic();
- return &rd_n1e1_edge_scmi_plat_info[channel_id];
+ return &plat_rd_scmi_info[channel_id];
}
else if (sgi_plat_info.platform_id == SGI575_SSC_VER_PART_NUM)
return &sgi575_scmi_plat_info;
diff --git a/plat/arm/css/sgi/sgi_plat.c b/plat/arm/css/sgi/sgi_plat.c
index 39eb89e..20c52e9 100644
--- a/plat/arm/css/sgi/sgi_plat.c
+++ b/plat/arm/css/sgi/sgi_plat.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -49,6 +49,15 @@
CSS_SGI_MAP_DEVICE,
SOC_CSS_MAP_DEVICE,
ARM_MAP_NS_DRAM1,
+#if CSS_SGI_CHIP_COUNT > 1
+ CSS_SGI_MAP_DEVICE_REMOTE_CHIP(1),
+#endif
+#if CSS_SGI_CHIP_COUNT > 2
+ CSS_SGI_MAP_DEVICE_REMOTE_CHIP(2),
+#endif
+#if CSS_SGI_CHIP_COUNT > 3
+ CSS_SGI_MAP_DEVICE_REMOTE_CHIP(3),
+#endif
#if ARM_BL31_IN_DRAM
ARM_MAP_BL31_SEC_DRAM,
#endif
@@ -78,10 +87,14 @@
#if SPM_MM && defined(IMAGE_BL31)
const mmap_region_t plat_arm_secure_partition_mmap[] = {
+ PLAT_ARM_SECURE_MAP_SYSTEMREG,
+ PLAT_ARM_SECURE_MAP_NOR2,
PLAT_ARM_SECURE_MAP_DEVICE,
ARM_SP_IMAGE_MMAP,
ARM_SP_IMAGE_NS_BUF_MMAP,
- ARM_SP_CPER_BUF_MMAP,
+#if RAS_EXTENSION
+ CSS_SGI_SP_CPER_BUF_MMAP,
+#endif
ARM_SP_IMAGE_RW_MMAP,
ARM_SPM_BUF_EL0_MMAP,
{0}
diff --git a/plat/arm/css/sgi/sgi_plat_v2.c b/plat/arm/css/sgi/sgi_plat_v2.c
index a770255..131cdf2 100644
--- a/plat/arm/css/sgi/sgi_plat_v2.c
+++ b/plat/arm/css/sgi/sgi_plat_v2.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,6 +12,10 @@
#include <plat/common/platform.h>
#include <drivers/arm/sbsa.h>
+#if SPM_MM
+#include <services/spm_mm_partition.h>
+#endif
+
/*
* Table of regions for different BL stages to map using the MMU.
*/
@@ -41,6 +45,9 @@
#if ARM_BL31_IN_DRAM
ARM_MAP_BL31_SEC_DRAM,
#endif
+#if SPM_MM
+ ARM_SP_IMAGE_MMAP,
+#endif
#if TRUSTED_BOARD_BOOT && !BL2_AT_EL3
ARM_MAP_BL1_RW,
#endif
@@ -57,13 +64,86 @@
CSS_SGI_MAP_DEVICE,
SOC_PLATFORM_PERIPH_MAP_DEVICE,
SOC_SYSTEM_PERIPH_MAP_DEVICE,
+#if SPM_MM
+ ARM_SPM_BUF_EL3_MMAP,
+#endif
{0}
};
+#if SPM_MM && defined(IMAGE_BL31)
+const mmap_region_t plat_arm_secure_partition_mmap[] = {
+ PLAT_ARM_SECURE_MAP_SYSTEMREG,
+ PLAT_ARM_SECURE_MAP_NOR2,
+ SOC_PLATFORM_PERIPH_MAP_DEVICE_USER,
+ ARM_SP_IMAGE_MMAP,
+ ARM_SP_IMAGE_NS_BUF_MMAP,
+ ARM_SP_IMAGE_RW_MMAP,
+ ARM_SPM_BUF_EL0_MMAP,
+ {0}
+};
+#endif /* SPM_MM && defined(IMAGE_BL31) */
#endif
ARM_CASSERT_MMAP
+#if SPM_MM && defined(IMAGE_BL31)
+/*
+ * Boot information passed to a secure partition during initialisation. Linear
+ * indices in MP information will be filled at runtime.
+ */
+static spm_mm_mp_info_t sp_mp_info[] = {
+ [0] = {0x81000000, 0},
+ [1] = {0x81010000, 0},
+ [2] = {0x81020000, 0},
+ [3] = {0x81030000, 0},
+ [4] = {0x81040000, 0},
+ [5] = {0x81050000, 0},
+ [6] = {0x81060000, 0},
+ [7] = {0x81070000, 0},
+ [8] = {0x81080000, 0},
+ [9] = {0x81090000, 0},
+ [10] = {0x810a0000, 0},
+ [11] = {0x810b0000, 0},
+ [12] = {0x810c0000, 0},
+ [13] = {0x810d0000, 0},
+ [14] = {0x810e0000, 0},
+ [15] = {0x810f0000, 0},
+};
+
+const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
+ .h.type = PARAM_SP_IMAGE_BOOT_INFO,
+ .h.version = VERSION_1,
+ .h.size = sizeof(spm_mm_boot_info_t),
+ .h.attr = 0,
+ .sp_mem_base = ARM_SP_IMAGE_BASE,
+ .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
+ .sp_image_base = ARM_SP_IMAGE_BASE,
+ .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
+ .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
+ .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
+ .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
+ .sp_image_size = ARM_SP_IMAGE_SIZE,
+ .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
+ .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
+ .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
+ .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
+ .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
+ .num_cpus = PLATFORM_CORE_COUNT,
+ .mp_info = &sp_mp_info[0],
+};
+
+const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
+{
+ return plat_arm_secure_partition_mmap;
+}
+
+const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
+ void *cookie)
+{
+ return &plat_arm_secure_partition_boot_info;
+}
+#endif /* SPM_MM && defined(IMAGE_BL31) */
+
#if TRUSTED_BOARD_BOOT
int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
{
diff --git a/plat/arm/css/sgi/sgi_ras.c b/plat/arm/css/sgi/sgi_ras.c
index a04972d..4f03ac4 100644
--- a/plat/arm/css/sgi/sgi_ras.c
+++ b/plat/arm/css/sgi/sgi_ras.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -20,44 +20,51 @@
static int sgi_ras_intr_handler(const struct err_record_info *err_rec,
int probe_data,
const struct err_handler_data *const data);
-struct efi_guid {
- uint32_t data1;
- uint16_t data2;
- uint16_t data3;
- uint8_t data4[8];
-};
-
typedef struct mm_communicate_header {
struct efi_guid header_guid;
size_t message_len;
uint8_t data[8];
} mm_communicate_header_t;
+/*
+ * GUID to indicate that the MM communication message is intended for DMC-620
+ * MM driver.
+ */
+const struct efi_guid dmc620_ecc_event_guid = {
+ 0x5ef0afd5, 0xe01a, 0x4c30,
+ {0x86, 0x19, 0x45, 0x46, 0x26, 0x91, 0x80, 0x98}
+};
+
struct sgi_ras_ev_map sgi575_ras_map[] = {
- /* DMC620 error overflow interrupt*/
- {SP_DMC_ERROR_OVERFLOW_EVENT_AARCH64, SGI_SDEI_DS_EVENT_1, 33},
+ /* DMC 0 error ECC error interrupt*/
+ {SGI_SDEI_DS_EVENT_0, 35},
- /* DMC620 error ECC error interrupt*/
- {SP_DMC_ERROR_ECC_EVENT_AARCH64, SGI_SDEI_DS_EVENT_0, 35},
+ /* DMC 1 error ECC error interrupt*/
+ {SGI_SDEI_DS_EVENT_1, 39},
};
#define SGI575_RAS_MAP_SIZE ARRAY_SIZE(sgi575_ras_map)
struct err_record_info sgi_err_records[] = {
{
+ /* DMC 0 error record info */
.handler = &sgi_ras_intr_handler,
+ .aux_data = (void *)0,
+ }, {
+ /* DMC 1 error record info */
+ .handler = &sgi_ras_intr_handler,
+ .aux_data = (void *)1,
},
};
struct ras_interrupt sgi_ras_interrupts[] = {
{
- .intr_number = 33,
- .err_record = &sgi_err_records[0],
- },
- {
.intr_number = 35,
.err_record = &sgi_err_records[0],
+ }, {
+ .intr_number = 39,
+ .err_record = &sgi_err_records[1],
}
};
@@ -138,9 +145,10 @@
*/
header = (void *) PLAT_SPM_BUF_BASE;
memset(header, 0, sizeof(*header));
- memcpy(&header->data, &ras_map->ras_ev_num,
- sizeof(ras_map->ras_ev_num));
- header->message_len = 4;
+ memcpy(&header->data, &err_rec->aux_data, sizeof(err_rec->aux_data));
+ header->message_len = sizeof(err_rec->aux_data);
+ memcpy(&header->header_guid, (void *) &dmc620_ecc_event_guid,
+ sizeof(const struct efi_guid));
spm_mm_sp_call(MM_COMMUNICATE_AARCH64, (uint64_t)header, 0,
plat_my_core_pos());
diff --git a/plat/brcm/board/common/board_common.mk b/plat/brcm/board/common/board_common.mk
index 3069f91..3b3e92d 100644
--- a/plat/brcm/board/common/board_common.mk
+++ b/plat/brcm/board/common/board_common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015 - 2020, Broadcom
+# Copyright (c) 2015 - 2021, Broadcom
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -36,6 +36,10 @@
DRIVER_SPI_ENABLE := 0
endif
+ifeq (${DRIVER_I2C_ENABLE},)
+DRIVER_I2C_ENABLE := 0
+endif
+
# By default, Trusted Watchdog is always enabled unless SPIN_ON_BL1_EXIT is set
ifeq (${BRCM_DISABLE_TRUSTED_WDOG},)
BRCM_DISABLE_TRUSTED_WDOG := 0
@@ -114,7 +118,8 @@
PLAT_INCLUDES += -Iplat/brcm/board/common \
-Iinclude/drivers/brcm \
- -Iinclude/drivers/brcm/emmc
+ -Iinclude/drivers/brcm/emmc \
+ -Iinclude/drivers/brcm/mdio
PLAT_BL_COMMON_SOURCES += plat/brcm/common/brcm_common.c \
plat/brcm/board/common/cmn_sec.c \
@@ -181,6 +186,12 @@
drivers/brcm/spi_flash.c
endif
+ifeq (${DRIVER_I2C_ENABLE},1)
+$(eval $(call add_define,DRIVER_I2C_ENABLE))
+BL2_SOURCES += drivers/brcm/i2c/i2c.c
+PLAT_INCLUDES += -Iinclude/drivers/brcm/i2c
+endif
+
ifeq (${DRIVER_OCOTP_ENABLE},1)
$(eval $(call add_define,DRIVER_OCOTP_ENABLE))
BL2_SOURCES += drivers/brcm/ocotp.c
diff --git a/plat/brcm/board/stingray/driver/sr_usb.h b/plat/brcm/board/stingray/driver/sr_usb.h
new file mode 100644
index 0000000..5033683
--- /dev/null
+++ b/plat/brcm/board/stingray/driver/sr_usb.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2019 - 2021, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SR_USB_H
+#define SR_USB_H
+
+#define CDRU_PM_RESET_N_R BIT(CDRU_MISC_RESET_CONTROL__CDRU_PM_RESET_N_R)
+#define CDRU_USBSS_RESET_N BIT(CDRU_MISC_RESET_CONTROL__CDRU_USBSS_RESET_N)
+#define CDRU_MISC_CLK_USBSS \
+ BIT(CDRU_MISC_CLK_ENABLE_CONTROL__CDRU_USBSS_CLK_EN_R)
+
+#define RESCAL_I_RSTB BIT(26)
+#define RESCAL_I_PWRDNB BIT(27)
+
+#define DRDU3_U3PHY_CTRL 0x68500014
+#define PHY_RESET BIT(1)
+#define POR_RESET BIT(28)
+#define MDIO_RESET BIT(29)
+
+#define DRDU3_PWR_CTRL 0x6850002c
+#define POWER_CTRL_OVRD BIT(2)
+
+#define USB3H_U3PHY_CTRL 0x68510014
+#define USB3H_U3SOFT_RST_N BIT(30)
+
+#define USB3H_PWR_CTRL 0x68510028
+
+#define USB3_PHY_MDIO_BLOCK_BASE_REG 0x1f
+#define BDC_AXI_SOFT_RST_N_OFFSET 0
+#define XHC_AXI_SOFT_RST_N_OFFSET 1
+#define MDIO_BUS_ID 3
+#define USB3H_PHY_ID 5
+#define USB3DRD_PHY_ID 2
+
+#define USB3_PHY_RXPMD_BLOCK_BASE 0x8020
+#define USB3_PHY_RXPMD_REG1 0x1
+#define USB3_PHY_RXPMD_REG2 0x2
+#define USB3_PHY_RXPMD_REG5 0x5
+#define USB3_PHY_RXPMD_REG7 0x7
+
+#define USB3_PHY_TXPMD_BLOCK_BASE 0x8040
+#define USB3_PHY_TXPMD_REG1 0x1
+#define USB3_PHY_TXPMD_REG2 0x2
+
+#define USB3_PHY_ANA_BLOCK_BASE 0x8090
+#define USB3_PHY_ANA_REG0 0x0
+#define USB3_PHY_ANA_REG1 0x1
+#define USB3_PHY_ANA_REG2 0x2
+#define USB3_PHY_ANA_REG5 0x5
+#define USB3_PHY_ANA_REG8 0x8
+#define USB3_PHY_ANA_REG11 0xb
+
+#define USB3_PHY_AEQ_BLOCK_BASE 0x80e0
+#define USB3_PHY_AEQ_REG1 0x1
+#define USB3_PHY_AEQ_REG3 0x3
+
+#ifdef USB_DMA_COHERENT
+#define DRDU3_U3XHC_SOFT_RST_N BIT(31)
+#define DRDU3_U3BDC_SOFT_RST_N BIT(30)
+
+#define DRDU3_SOFT_RESET_CTRL 0x68500030
+#define DRDU3_XHC_AXI_SOFT_RST_N BIT(1)
+#define DRDU3_BDC_AXI_SOFT_RST_N BIT(0)
+
+#define DRDU2_PHY_CTRL 0x6852000c
+#define DRDU2_U2SOFT_RST_N BIT(29)
+
+#define USB3H_SOFT_RESET_CTRL 0x6851002c
+#define USB3H_XHC_AXI_SOFT_RST_N BIT(1)
+
+#define DRDU2_SOFT_RESET_CTRL 0x68520020
+#define DRDU2_BDC_AXI_SOFT_RST_N BIT(0)
+
+#define DRD2U3H_XHC_REGS_AXIWRA 0x68511c08
+#define DRD2U3H_XHC_REGS_AXIRDA 0x68511c0c
+#define DRDU2D_BDC_REGS_AXIWRA 0x68521c08
+#define DRDU2D_BDC_REGS_AXIRDA 0x68521c0c
+#define DRDU3H_XHC_REGS_AXIWRA 0x68501c08
+#define DRDU3H_XHC_REGS_AXIRDA 0x68501c0c
+#define DRDU3D_BDC_REGS_AXIWRA 0x68502c08
+#define DRDU3D_BDC_REGS_AXIRDA 0x68502c0c
+/* cacheable write-back, allocate on both reads and writes */
+#define USBAXI_AWCACHE 0xf
+#define USBAXI_ARCACHE 0xf
+/* non-secure */
+#define USBAXI_AWPROT 0x8
+#define USBAXI_ARPROT 0x8
+#define USBAXIWR_SA_VAL ((USBAXI_AWCACHE << 4 | USBAXI_AWPROT) << 0)
+#define USBAXIWR_SA_MASK ((0xf << 4 | 0xf) << 0)
+#define USBAXIWR_UA_VAL ((USBAXI_AWCACHE << 4 | USBAXI_AWPROT) << 16)
+#define USBAXIWR_UA_MASK ((0xf << 4 | 0xf) << 0)
+#define USBAXIRD_SA_VAL ((USBAXI_ARCACHE << 4 | USBAXI_ARPROT) << 0)
+#define USBAXIRD_SA_MASK ((0xf << 4 | 0xf) << 0)
+#define USBAXIRD_UA_VAL ((USBAXI_ARCACHE << 4 | USBAXI_ARPROT) << 16)
+#define USBAXIRD_UA_MASK ((0xf << 4 | 0xf) << 0)
+#endif /* USB_DMA_COHERENT */
+
+#define ICFG_DRDU3_SID_CTRL 0x6850001c
+#define ICFG_USB3H_SID_CTRL 0x6851001c
+#define ICFG_DRDU2_SID_CTRL 0x68520010
+#define ICFG_USB_SID_SHIFT 5
+#define ICFG_USB_SID_AWADDR_OFFSET 0x0
+#define ICFG_USB_SID_ARADDR_OFFSET 0x4
+
+#define USBIC_GPV_BASE 0x68600000
+#define USBIC_GPV_SECURITY0 (USBIC_GPV_BASE + 0x8)
+#define USBIC_GPV_SECURITY0_FIELD BIT(0)
+#define USBIC_GPV_SECURITY1 (USBIC_GPV_BASE + 0xc)
+#define USBIC_GPV_SECURITY1_FIELD (BIT(0) | BIT(1))
+#define USBIC_GPV_SECURITY2 (USBIC_GPV_BASE + 0x10)
+#define USBIC_GPV_SECURITY2_FIELD (BIT(0) | BIT(1))
+#define USBIC_GPV_SECURITY4 (USBIC_GPV_BASE + 0x18)
+#define USBIC_GPV_SECURITY4_FIELD BIT(0)
+#define USBIC_GPV_SECURITY10 (USBIC_GPV_BASE + 0x30)
+#define USBIC_GPV_SECURITY10_FIELD (0x7 << 0)
+
+#define USBSS_TZPCDECPROT_BASE 0x68540800
+#define USBSS_TZPCDECPROT0set (USBSS_TZPCDECPROT_BASE + 0x4)
+#define USBSS_TZPCDECPROT0clr (USBSS_TZPCDECPROT_BASE + 0x8)
+#define DECPROT0_USBSS_DRD2U3H BIT(3)
+#define DECPROT0_USBSS_DRDU2H BIT(2)
+#define DECPROT0_USBSS_DRDU3D BIT(1)
+#define DECPROT0_USBSS_DRDU2D BIT(0)
+#define USBSS_TZPCDECPROT0 \
+ (DECPROT0_USBSS_DRD2U3H | \
+ DECPROT0_USBSS_DRDU2H | \
+ DECPROT0_USBSS_DRDU3D | \
+ DECPROT0_USBSS_DRDU2D)
+
+int32_t usb_device_init(unsigned int);
+
+#endif /* SR_USB_H */
diff --git a/plat/brcm/board/stingray/driver/usb.c b/plat/brcm/board/stingray/driver/usb.c
new file mode 100644
index 0000000..4a84141
--- /dev/null
+++ b/plat/brcm/board/stingray/driver/usb.c
@@ -0,0 +1,296 @@
+/*
+ * Copyright (c) 2019 - 2021, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include <mdio.h>
+#include <platform_usb.h>
+#include <sr_utils.h>
+#include "sr_usb.h"
+#include <usbh_xhci_regs.h>
+
+static uint32_t usb_func = USB3_DRD | USB3H_USB2DRD;
+
+static void usb_pm_rescal_init(void)
+{
+ uint32_t data;
+ uint32_t try;
+
+ mmio_setbits_32(CDRU_MISC_RESET_CONTROL, CDRU_PM_RESET_N_R);
+ /* release reset */
+ mmio_setbits_32(CDRU_CHIP_TOP_SPARE_REG0, RESCAL_I_RSTB);
+ udelay(10U);
+ /* power up */
+ mmio_setbits_32(CDRU_CHIP_TOP_SPARE_REG0,
+ RESCAL_I_RSTB | RESCAL_I_PWRDNB);
+ try = 1000U;
+ do {
+ udelay(1U);
+ data = mmio_read_32(CDRU_CHIP_TOP_SPARE_REG1);
+ try--;
+ } while ((data & RESCAL_I_PWRDNB) == 0x0U && (try != 0U));
+
+ if (try == 0U) {
+ ERROR("CDRU_CHIP_TOP_SPARE_REG1: 0x%x\n", data);
+ }
+
+ INFO("USB and PM Rescal Init done..\n");
+}
+
+const unsigned int xhc_portsc_reg_offset[MAX_USB_PORTS] = {
+ XHC_PORTSC1_OFFSET,
+ XHC_PORTSC2_OFFSET,
+ XHC_PORTSC3_OFFSET,
+};
+
+static void usb3h_usb2drd_init(void)
+{
+ uint32_t val;
+
+ INFO("USB3H + USB 2DRD init\n");
+ mmio_clrbits_32(USB3H_U3PHY_CTRL, POR_RESET);
+ val = mmio_read_32(USB3H_PWR_CTRL);
+ val &= ~(0x3U << POWER_CTRL_OVRD);
+ val |= (1U << POWER_CTRL_OVRD);
+ mmio_write_32(USB3H_PWR_CTRL, val);
+ mmio_setbits_32(USB3H_U3PHY_CTRL, PHY_RESET);
+ /* Phy to come out of reset */
+ udelay(2U);
+ mmio_clrbits_32(USB3H_U3PHY_CTRL, MDIO_RESET);
+
+ /* MDIO in reset */
+ udelay(2U);
+ mmio_setbits_32(USB3H_U3PHY_CTRL, MDIO_RESET);
+
+ /* After MDIO reset release */
+ udelay(2U);
+
+ /* USB 3.0 phy Analog Block Initialization */
+ mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG,
+ USB3_PHY_ANA_BLOCK_BASE);
+ mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_ANA_REG0, 0x4646U);
+ mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_ANA_REG1, 0x80c9U);
+ mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_ANA_REG2, 0x88a6U);
+ mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_ANA_REG5, 0x7c12U);
+ mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_ANA_REG8, 0x1d07U);
+ mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_ANA_REG11, 0x25cU);
+
+ /* USB 3.0 phy RXPMD Block initialization*/
+ mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG,
+ USB3_PHY_RXPMD_BLOCK_BASE);
+ mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_RXPMD_REG1, 0x4052U);
+ mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_RXPMD_REG2, 0x4cU);
+ mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_RXPMD_REG5, 0x7U);
+ mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_RXPMD_REG7, 0x173U);
+
+ /* USB 3.0 phy AEQ Block initialization*/
+ mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG,
+ USB3_PHY_AEQ_BLOCK_BASE);
+ mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_AEQ_REG1, 0x3000U);
+ mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_AEQ_REG3, 0x2c70U);
+
+ /* USB 3.0 phy TXPMD Block initialization*/
+ mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG,
+ USB3_PHY_TXPMD_BLOCK_BASE);
+ mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_TXPMD_REG1, 0x100fU);
+ mdio_write(MDIO_BUS_ID, USB3H_PHY_ID, USB3_PHY_TXPMD_REG2, 0x238cU);
+}
+
+static void usb3drd_init(void)
+{
+ uint32_t val;
+
+ INFO("USB3DRD init\n");
+ mmio_clrbits_32(DRDU3_U3PHY_CTRL, POR_RESET);
+ val = mmio_read_32(DRDU3_PWR_CTRL);
+ val &= ~(0x3U << POWER_CTRL_OVRD);
+ val |= (1U << POWER_CTRL_OVRD);
+ mmio_write_32(DRDU3_PWR_CTRL, val);
+ mmio_setbits_32(DRDU3_U3PHY_CTRL, PHY_RESET);
+ /* Phy to come out of reset */
+ udelay(2U);
+ mmio_clrbits_32(DRDU3_U3PHY_CTRL, MDIO_RESET);
+
+ /* MDIO in reset */
+ udelay(2U);
+ mmio_setbits_32(DRDU3_U3PHY_CTRL, MDIO_RESET);
+
+ /* After MDIO reset release */
+ udelay(2U);
+
+ /* USB 3.0 DRD phy Analog Block Initialization */
+ mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG,
+ USB3_PHY_ANA_BLOCK_BASE);
+ mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_ANA_REG0, 0x4646U);
+ mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_ANA_REG1, 0x80c9U);
+ mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_ANA_REG2, 0x88a6U);
+ mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_ANA_REG5, 0x7c12U);
+ mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_ANA_REG8, 0x1d07U);
+ mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_ANA_REG11, 0x25cU);
+
+ /* USB 3.0 DRD phy RXPMD Block initialization*/
+ mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG,
+ USB3_PHY_RXPMD_BLOCK_BASE);
+ mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_RXPMD_REG1, 0x4052U);
+ mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_RXPMD_REG2, 0x4cU);
+ mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_RXPMD_REG5, 0x7U);
+ mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_RXPMD_REG7, 0x173U);
+
+ /* USB 3.0 DRD phy AEQ Block initialization*/
+ mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG,
+ USB3_PHY_AEQ_BLOCK_BASE);
+ mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_AEQ_REG1, 0x3000U);
+ mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_AEQ_REG3, 0x2c70U);
+
+ /* USB 3.0 DRD phy TXPMD Block initialization*/
+ mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_MDIO_BLOCK_BASE_REG,
+ USB3_PHY_TXPMD_BLOCK_BASE);
+ mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_TXPMD_REG1, 0x100fU);
+ mdio_write(MDIO_BUS_ID, USB3DRD_PHY_ID, USB3_PHY_TXPMD_REG2, 0x238cU);
+}
+
+static void usb3_phy_init(void)
+{
+ usb_pm_rescal_init();
+
+ if ((usb_func & USB3H_USB2DRD) != 0U) {
+ usb3h_usb2drd_init();
+ }
+
+ if ((usb_func & USB3_DRD) != 0U) {
+ usb3drd_init();
+ }
+}
+
+#ifdef USB_DMA_COHERENT
+void usb_enable_coherence(void)
+{
+ if (usb_func & USB3H_USB2DRD) {
+ mmio_setbits_32(USB3H_SOFT_RESET_CTRL,
+ USB3H_XHC_AXI_SOFT_RST_N);
+ mmio_setbits_32(DRDU2_SOFT_RESET_CTRL,
+ DRDU2_BDC_AXI_SOFT_RST_N);
+ mmio_setbits_32(USB3H_U3PHY_CTRL, USB3H_U3SOFT_RST_N);
+ mmio_setbits_32(DRDU2_PHY_CTRL, DRDU2_U2SOFT_RST_N);
+
+ mmio_clrsetbits_32(DRD2U3H_XHC_REGS_AXIWRA,
+ (USBAXIWR_UA_MASK | USBAXIWR_SA_MASK),
+ (USBAXIWR_UA_VAL | USBAXIWR_SA_VAL));
+
+ mmio_clrsetbits_32(DRD2U3H_XHC_REGS_AXIRDA,
+ (USBAXIRD_UA_MASK | USBAXIRD_SA_MASK),
+ (USBAXIRD_UA_VAL | USBAXIRD_SA_VAL));
+
+ mmio_clrsetbits_32(DRDU2D_BDC_REGS_AXIWRA,
+ (USBAXIWR_UA_MASK | USBAXIWR_SA_MASK),
+ (USBAXIWR_UA_VAL | USBAXIWR_SA_VAL));
+
+ mmio_clrsetbits_32(DRDU2D_BDC_REGS_AXIRDA,
+ (USBAXIRD_UA_MASK | USBAXIRD_SA_MASK),
+ (USBAXIRD_UA_VAL | USBAXIRD_SA_VAL));
+
+ }
+
+ if (usb_func & USB3_DRD) {
+ mmio_setbits_32(DRDU3_SOFT_RESET_CTRL,
+ (DRDU3_XHC_AXI_SOFT_RST_N |
+ DRDU3_BDC_AXI_SOFT_RST_N));
+ mmio_setbits_32(DRDU3_U3PHY_CTRL,
+ (DRDU3_U3XHC_SOFT_RST_N |
+ DRDU3_U3BDC_SOFT_RST_N));
+
+ mmio_clrsetbits_32(DRDU3H_XHC_REGS_AXIWRA,
+ (USBAXIWR_UA_MASK | USBAXIWR_SA_MASK),
+ (USBAXIWR_UA_VAL | USBAXIWR_SA_VAL));
+
+ mmio_clrsetbits_32(DRDU3H_XHC_REGS_AXIRDA,
+ (USBAXIRD_UA_MASK | USBAXIRD_SA_MASK),
+ (USBAXIRD_UA_VAL | USBAXIRD_SA_VAL));
+
+ mmio_clrsetbits_32(DRDU3D_BDC_REGS_AXIWRA,
+ (USBAXIWR_UA_MASK | USBAXIWR_SA_MASK),
+ (USBAXIWR_UA_VAL | USBAXIWR_SA_VAL));
+
+ mmio_clrsetbits_32(DRDU3D_BDC_REGS_AXIRDA,
+ (USBAXIRD_UA_MASK | USBAXIRD_SA_MASK),
+ (USBAXIRD_UA_VAL | USBAXIRD_SA_VAL));
+ }
+}
+#endif
+
+void xhci_phy_init(void)
+{
+ uint32_t val;
+
+ INFO("usb init start\n");
+ mmio_setbits_32(CDRU_MISC_CLK_ENABLE_CONTROL,
+ CDRU_MISC_CLK_USBSS);
+
+ mmio_setbits_32(CDRU_MISC_RESET_CONTROL, CDRU_USBSS_RESET_N);
+
+ if (usb_func & USB3_DRD) {
+ VERBOSE(" - configure stream_id = 0x6800 for DRDU3\n");
+ val = SR_SID_VAL(0x3U, 0x1U, 0x0U) << ICFG_USB_SID_SHIFT;
+ mmio_write_32(ICFG_DRDU3_SID_CTRL + ICFG_USB_SID_AWADDR_OFFSET,
+ val);
+ mmio_write_32(ICFG_DRDU3_SID_CTRL + ICFG_USB_SID_ARADDR_OFFSET,
+ val);
+
+ /*
+ * DRDU3 Device USB Space, DRDU3 Host USB Space,
+ * DRDU3 SS Config
+ */
+ mmio_setbits_32(USBIC_GPV_SECURITY10,
+ USBIC_GPV_SECURITY10_FIELD);
+ }
+
+ if (usb_func & USB3H_USB2DRD) {
+ VERBOSE(" - configure stream_id = 0x6801 for USB3H\n");
+ val = SR_SID_VAL(0x3U, 0x1U, 0x1U) << ICFG_USB_SID_SHIFT;
+ mmio_write_32(ICFG_USB3H_SID_CTRL + ICFG_USB_SID_AWADDR_OFFSET,
+ val);
+ mmio_write_32(ICFG_USB3H_SID_CTRL + ICFG_USB_SID_ARADDR_OFFSET,
+ val);
+
+ VERBOSE(" - configure stream_id = 0x6802 for DRDU2\n");
+ val = SR_SID_VAL(0x3U, 0x1U, 0x2U) << ICFG_USB_SID_SHIFT;
+ mmio_write_32(ICFG_DRDU2_SID_CTRL + ICFG_USB_SID_AWADDR_OFFSET,
+ val);
+ mmio_write_32(ICFG_DRDU2_SID_CTRL + ICFG_USB_SID_ARADDR_OFFSET,
+ val);
+
+ /* DRDU2 APB Bridge:DRDU2 USB Device, USB3H SS Config */
+ mmio_setbits_32(USBIC_GPV_SECURITY1, USBIC_GPV_SECURITY1_FIELD);
+
+ /*
+ * USB3H APB Bridge:DRDU2 Host + USB3 Host USB Space,
+ * USB3H SS Config
+ */
+ mmio_setbits_32(USBIC_GPV_SECURITY2, USBIC_GPV_SECURITY2_FIELD);
+ }
+
+ /* Configure Host masters as non-Secure */
+ mmio_setbits_32(USBSS_TZPCDECPROT0set, USBSS_TZPCDECPROT0);
+
+ /* CCN Slave on USBIC */
+ mmio_setbits_32(USBIC_GPV_SECURITY0, USBIC_GPV_SECURITY0_FIELD);
+
+ /* SLAVE_8:IDM Register Space */
+ mmio_setbits_32(USBIC_GPV_SECURITY4, USBIC_GPV_SECURITY4_FIELD);
+
+ usb3_phy_init();
+#ifdef USB_DMA_COHERENT
+ usb_enable_coherence();
+#endif
+
+ usb_device_init(usb_func);
+
+ INFO("PLAT USB: init done.\n");
+}
diff --git a/plat/brcm/board/stingray/driver/usb_phy.c b/plat/brcm/board/stingray/driver/usb_phy.c
new file mode 100644
index 0000000..54c98e1
--- /dev/null
+++ b/plat/brcm/board/stingray/driver/usb_phy.c
@@ -0,0 +1,601 @@
+/*
+ * Copyright (c) 2019 - 2021, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform_usb.h>
+#include <usb_phy.h>
+
+#define USB_PHY_ALREADY_STARTED (-2)
+#define USB_MAX_DEVICES 2
+#define USB3H_USB2DRD_PHY 0
+#define USB3_DRD_PHY 1
+
+/* Common bit fields for all the USB2 phy */
+#define USB2_PHY_ISO DRDU2_U2PHY_ISO
+#define USB2_AFE_PLL_PWRDWNB DRDU2_U2AFE_PLL_PWRDWNB
+#define USB2_AFE_BG_PWRDWNB DRDU2_U2AFE_BG_PWRDWNB
+#define USB2_AFE_LDO_PWRDWNB DRDU2_U2AFE_LDO_PWRDWNB
+#define USB2_CTRL_CORERDY DRDU2_U2CTRL_CORERDY
+
+#define USB2_PHY_PCTL_MASK DRDU2_U2PHY_PCTL_MASK
+#define USB2_PHY_PCTL_OFFSET DRDU2_U2PHY_PCTL_OFFSET
+#define USB2_PHY_PCTL_VAL U2PHY_PCTL_VAL
+
+#define USB2_PLL_RESETB DRDU2_U2PLL_RESETB
+#define USB2_PHY_RESETB DRDU2_U2PHY_RESETB
+
+static usb_phy_port_t usb_phy_port[2U][MAX_NR_PORTS];
+
+static usb_phy_t usb_phy_info[2U] = {
+ {DRDU2_U2PLL_NDIV_FRAC, USB3H_PIPE_CTRL, 0U, USB3H_DRDU2_PHY},
+ {0U, 0U, DRDU3_PIPE_CTRL, DRDU3_PHY}
+};
+
+typedef struct {
+ void *pcd_id;
+} usb_platform_dev;
+
+/* index 0: USB3H + USB2 DRD, 1: USB3 DRD */
+static usb_platform_dev xhci_devices_configs[USB_MAX_DEVICES] = {
+ {&usb_phy_info[0U]},
+ {&usb_phy_info[1U]}
+};
+
+static int32_t pll_lock_check(uint32_t address, uint32_t bit)
+{
+ uint32_t retry;
+ uint32_t data;
+
+ retry = PLL_LOCK_RETRY_COUNT;
+ do {
+ data = mmio_read_32(address);
+ if ((data & bit) != 0U) {
+ return 0;
+ }
+ udelay(1);
+ } while (--retry != 0);
+
+ ERROR("%s(): FAIL (0x%08x)\n", __func__, address);
+ return -1;
+}
+
+/*
+ * USB2 PHY using external FSM bringup sequence
+ * Total #3 USB2 phys. All phys has the same
+ * bringup sequence. Register bit fields for
+ * some of the PHY's are different.
+ * Bit fields which are different are passed using
+ * struct u2_phy_ext_fsm with bit-fields and register addr.
+ */
+
+static void u2_phy_ext_fsm_power_on(struct u2_phy_ext_fsm *u2_phy)
+{
+ mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_PHY_ISO);
+ /* Delay as per external FSM spec */
+ udelay(10U);
+
+ mmio_setbits_32(u2_phy->phy_ctrl_reg, u2_phy->phy_iddq);
+ /* Delay as per external FSM spec */
+ udelay(10U);
+
+ mmio_clrbits_32(u2_phy->phy_ctrl_reg,
+ (USB2_AFE_BG_PWRDWNB |
+ USB2_AFE_PLL_PWRDWNB |
+ USB2_AFE_LDO_PWRDWNB |
+ USB2_CTRL_CORERDY));
+
+ mmio_clrsetbits_32(u2_phy->phy_ctrl_reg,
+ (USB2_PHY_PCTL_MASK << USB2_PHY_PCTL_OFFSET),
+ (USB2_PHY_PCTL_VAL << USB2_PHY_PCTL_OFFSET));
+ /* Delay as per external FSM spec */
+ udelay(160U);
+
+ mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_CTRL_CORERDY);
+ /* Delay as per external FSM spec */
+ udelay(50U);
+
+ mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_AFE_BG_PWRDWNB);
+ /* Delay as per external FSM spec */
+ udelay(200U);
+
+ mmio_setbits_32(u2_phy->pwr_ctrl_reg, u2_phy->pwr_onin);
+ mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_AFE_LDO_PWRDWNB);
+ /* Delay as per external FSM spec */
+ udelay(10U);
+
+ mmio_setbits_32(u2_phy->pwr_ctrl_reg, u2_phy->pwr_okin);
+ /* Delay as per external FSM spec */
+ udelay(10U);
+
+ mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_AFE_PLL_PWRDWNB);
+ /* Delay as per external FSM spec */
+ udelay(10U);
+
+ mmio_clrbits_32(u2_phy->phy_ctrl_reg, USB2_PHY_ISO);
+ /* Delay as per external FSM spec */
+ udelay(10U);
+ mmio_clrbits_32(u2_phy->phy_ctrl_reg, u2_phy->phy_iddq);
+ /* Delay as per external FSM spec */
+ udelay(1U);
+
+ mmio_setbits_32(u2_phy->pll_ctrl_reg, USB2_PLL_RESETB);
+ mmio_setbits_32(u2_phy->phy_ctrl_reg, USB2_PHY_RESETB);
+
+}
+
+static int32_t usb3h_u2_phy_power_on(uint32_t base)
+{
+ int32_t status;
+ struct u2_phy_ext_fsm u2_phy;
+
+ u2_phy.pll_ctrl_reg = base + USB3H_U2PLL_CTRL;
+ u2_phy.phy_ctrl_reg = base + USB3H_U2PHY_CTRL;
+ u2_phy.phy_iddq = USB3H_U2PHY_IDDQ;
+ u2_phy.pwr_ctrl_reg = base + USB3H_PWR_CTRL;
+ u2_phy.pwr_okin = USB3H_PWR_CTRL_U2PHY_DFE_SWITCH_PWROKIN;
+ u2_phy.pwr_onin = USB3H_PWR_CTRL_U2PHY_DFE_SWITCH_PWRONIN;
+
+ u2_phy_ext_fsm_power_on(&u2_phy);
+
+ status = pll_lock_check(base + USB3H_U2PLL_CTRL, USB3H_U2PLL_LOCK);
+ if (status != 0) {
+ /* re-try by toggling the PLL reset */
+ mmio_clrbits_32(base + USB3H_U2PLL_CTRL,
+ (uint32_t)USB3H_U2PLL_RESETB);
+ mmio_setbits_32(base + USB3H_U2PLL_CTRL, USB3H_U2PLL_RESETB);
+ status = pll_lock_check(base + USB3H_U2PLL_CTRL,
+ USB3H_U2PLL_LOCK);
+ if (status != 0)
+ ERROR("%s() re-try PLL lock FAIL (0x%08x)\n", __func__,
+ base + USB3H_U2PLL_CTRL);
+ }
+
+ mmio_clrsetbits_32(base + USB3H_U2PHY_CTRL,
+ (USB3H_U2PHY_PCTL_MASK << USB3H_U2PHY_PCTL_OFFSET),
+ (U2PHY_PCTL_NON_DRV_LOW << USB3H_U2PHY_PCTL_OFFSET));
+ return status;
+}
+
+static int32_t usb3h_u3_phy_power_on(uint32_t base)
+{
+ int32_t status;
+
+ /* Set pctl with mode and soft reset */
+ mmio_clrsetbits_32(base + USB3H_U3PHY_CTRL,
+ (USB3H_U3PHY_PCTL_MASK << USB3H_U3PHY_PCTL_OFFSET),
+ (U3PHY_PCTL_VAL << USB3H_U3PHY_PCTL_OFFSET));
+
+ mmio_clrbits_32(base + USB3H_U3PHY_PLL_CTRL,
+ (uint32_t) USB3H_U3SSPLL_SUSPEND_EN);
+ mmio_setbits_32(base + USB3H_U3PHY_PLL_CTRL, USB3H_U3PLL_SEQ_START);
+ mmio_setbits_32(base + USB3H_U3PHY_PLL_CTRL, USB3H_U3PLL_RESETB);
+
+ /* Time to stabilize the PLL Control */
+ mdelay(1U);
+
+ status = pll_lock_check(base + USB3H_U3PHY_PLL_CTRL,
+ USB3H_U3PLL_SS_LOCK);
+
+ return status;
+}
+
+static int32_t drdu3_u2_phy_power_on(uint32_t base)
+{
+ int32_t status;
+ struct u2_phy_ext_fsm u2_phy;
+
+ u2_phy.pll_ctrl_reg = base + DRDU3_U2PLL_CTRL;
+ u2_phy.phy_ctrl_reg = base + DRDU3_U2PHY_CTRL;
+ u2_phy.phy_iddq = DRDU3_U2PHY_IDDQ;
+ u2_phy.pwr_ctrl_reg = base + DRDU3_PWR_CTRL;
+ u2_phy.pwr_okin = DRDU3_U2PHY_DFE_SWITCH_PWROKIN;
+ u2_phy.pwr_onin = DRDU3_U2PHY_DFE_SWITCH_PWRONIN;
+
+ u2_phy_ext_fsm_power_on(&u2_phy);
+
+ status = pll_lock_check(base + DRDU3_U2PLL_CTRL, DRDU3_U2PLL_LOCK);
+ if (status != 0) {
+ /* re-try by toggling the PLL reset */
+ mmio_clrbits_32(base + DRDU3_U2PLL_CTRL,
+ (uint32_t)DRDU2_U2PLL_RESETB);
+ mmio_setbits_32(base + DRDU3_U2PLL_CTRL, DRDU3_U2PLL_RESETB);
+
+ status = pll_lock_check(base + DRDU3_U2PLL_CTRL,
+ DRDU3_U2PLL_LOCK);
+ if (status != 0) {
+ ERROR("%s() re-try PLL lock FAIL (0x%08x)\n", __func__,
+ base + DRDU3_U2PLL_CTRL);
+ }
+ }
+ mmio_clrsetbits_32(base + DRDU3_U2PHY_CTRL,
+ (DRDU3_U2PHY_PCTL_MASK << DRDU3_U2PHY_PCTL_OFFSET),
+ (U2PHY_PCTL_NON_DRV_LOW << DRDU3_U2PHY_PCTL_OFFSET));
+
+ return status;
+}
+
+static int32_t drdu3_u3_phy_power_on(uint32_t base)
+{
+ int32_t status;
+
+ /* Set pctl with mode and soft reset */
+ mmio_clrsetbits_32(base + DRDU3_U3PHY_CTRL,
+ (DRDU3_U3PHY_PCTL_MASK << DRDU3_U3PHY_PCTL_OFFSET),
+ (U3PHY_PCTL_VAL << DRDU3_U3PHY_PCTL_OFFSET));
+
+ mmio_clrbits_32(base + DRDU3_U3PHY_PLL_CTRL,
+ (uint32_t) DRDU3_U3SSPLL_SUSPEND_EN);
+ mmio_setbits_32(base + DRDU3_U3PHY_PLL_CTRL, DRDU3_U3PLL_SEQ_START);
+ mmio_setbits_32(base + DRDU3_U3PHY_PLL_CTRL, DRDU3_U3PLL_RESETB);
+
+ /* Time to stabilize the PLL Control */
+ mdelay(1U);
+
+ status = pll_lock_check(base + DRDU3_U3PHY_PLL_CTRL,
+ DRDU3_U3PLL_SS_LOCK);
+
+ return status;
+}
+
+static int32_t drdu2_u2_phy_power_on(uint32_t base)
+{
+ int32_t status;
+ struct u2_phy_ext_fsm u2_phy;
+
+ u2_phy.pll_ctrl_reg = base + DRDU2_U2PLL_CTRL;
+ u2_phy.phy_ctrl_reg = base + DRDU2_PHY_CTRL;
+ u2_phy.phy_iddq = DRDU2_U2IDDQ;
+ u2_phy.pwr_ctrl_reg = base + DRDU2_PWR_CTRL;
+ u2_phy.pwr_okin = DRDU2_U2PHY_DFE_SWITCH_PWROKIN_I;
+ u2_phy.pwr_onin = DRDU2_U2PHY_DFE_SWITCH_PWRONIN_I;
+
+ u2_phy_ext_fsm_power_on(&u2_phy);
+
+ status = pll_lock_check(base + DRDU2_U2PLL_CTRL, DRDU2_U2PLL_LOCK);
+ if (status != 0) {
+ /* re-try by toggling the PLL reset */
+ mmio_clrbits_32(base + DRDU2_U2PLL_CTRL,
+ (uint32_t)DRDU2_U2PLL_RESETB);
+ mmio_setbits_32(base + DRDU2_U2PLL_CTRL, DRDU2_U2PLL_RESETB);
+
+ status = pll_lock_check(base + DRDU2_U2PLL_CTRL,
+ DRDU2_U2PLL_LOCK);
+ if (status != 0)
+ ERROR("%s() re-try PLL lock FAIL (0x%08x)\n", __func__,
+ base + DRDU2_U2PLL_CTRL);
+ }
+ mmio_clrsetbits_32(base + DRDU2_PHY_CTRL,
+ (DRDU2_U2PHY_PCTL_MASK << DRDU2_U2PHY_PCTL_OFFSET),
+ (U2PHY_PCTL_NON_DRV_LOW << DRDU2_U2PHY_PCTL_OFFSET));
+
+ return status;
+}
+
+void u3h_u2drd_phy_reset(usb_phy_port_t *phy_port)
+{
+ usb_phy_t *phy = phy_port->p;
+
+ switch (phy_port->port_id) {
+ case USB3HS_PORT:
+ mmio_clrbits_32(phy->usb3hreg + USB3H_U2PHY_CTRL,
+ (uint32_t) USB3H_U2CTRL_CORERDY);
+ mmio_setbits_32(phy->usb3hreg + USB3H_U2PHY_CTRL,
+ USB3H_U2CTRL_CORERDY);
+ break;
+ case DRDU2_PORT:
+ mmio_clrbits_32(phy->drdu2reg + DRDU2_PHY_CTRL,
+ (uint32_t) DRDU2_U2CTRL_CORERDY);
+ mmio_setbits_32(phy->drdu2reg + DRDU2_PHY_CTRL,
+ DRDU2_U2CTRL_CORERDY);
+ break;
+ }
+}
+
+void u3drd_phy_reset(usb_phy_port_t *phy_port)
+{
+ usb_phy_t *phy = phy_port->p;
+
+ if (phy_port->port_id == DRD3HS_PORT) {
+ mmio_clrbits_32(phy->drdu3reg + DRDU3_U2PHY_CTRL,
+ (uint32_t) DRDU3_U2CTRL_CORERDY);
+ mmio_setbits_32(phy->drdu3reg + DRDU3_U2PHY_CTRL,
+ DRDU3_U2CTRL_CORERDY);
+ }
+}
+
+static int32_t u3h_u2drd_phy_power_on(usb_phy_port_t *phy_port)
+{
+ usb_phy_t *phy = phy_port->p;
+ int32_t status;
+
+ switch (phy_port->port_id) {
+ case USB3SS_PORT:
+ mmio_clrbits_32(phy->usb3hreg + USB3H_PHY_PWR_CTRL,
+ (uint32_t) USB3H_DISABLE_USB30_P0);
+ status = usb3h_u3_phy_power_on(phy->usb3hreg);
+ if (status != 0) {
+ goto err_usb3h_phy_on;
+ }
+ break;
+ case USB3HS_PORT:
+ mmio_clrbits_32(phy->usb3hreg + USB3H_PHY_PWR_CTRL,
+ (uint32_t) USB3H_DISABLE_EUSB_P1);
+ mmio_setbits_32(AXI_DEBUG_CTRL,
+ AXI_DBG_CTRL_SSPHY_DRD_MODE_DISABLE);
+ mmio_setbits_32(USB3H_DEBUG_CTRL,
+ USB3H_DBG_CTRL_SSPHY_DRD_MODE_DISABLE);
+
+ mmio_clrbits_32(phy->usb3hreg + USB3H_PWR_CTRL,
+ USB3H_PWR_CTRL_U2PHY_DFE_SWITCH_PWRONIN);
+ /* Delay as per external FSM spec */
+ udelay(10U);
+ mmio_clrbits_32(phy->usb3hreg + USB3H_PWR_CTRL,
+ USB3H_PWR_CTRL_U2PHY_DFE_SWITCH_PWROKIN);
+ status = usb3h_u2_phy_power_on(phy->usb3hreg);
+ if (status != 0) {
+ goto err_usb3h_phy_on;
+ }
+ break;
+ case DRDU2_PORT:
+ mmio_clrbits_32(phy->usb3hreg + USB3H_PHY_PWR_CTRL,
+ (uint32_t) USB3H_DISABLE_EUSB_P0);
+ mmio_setbits_32(AXI_DEBUG_CTRL,
+ AXI_DBG_CTRL_SSPHY_DRD_MODE_DISABLE);
+ mmio_setbits_32(USB3H_DEBUG_CTRL,
+ USB3H_DBG_CTRL_SSPHY_DRD_MODE_DISABLE);
+
+ mmio_clrbits_32(phy->usb3hreg + DRDU2_PWR_CTRL,
+ DRDU2_U2PHY_DFE_SWITCH_PWRONIN_I);
+ /* Delay as per external FSM spec */
+ udelay(10U);
+ mmio_clrbits_32(phy->usb3hreg + DRDU2_PWR_CTRL,
+ DRDU2_U2PHY_DFE_SWITCH_PWROKIN_I);
+
+ status = drdu2_u2_phy_power_on(phy->drdu2reg);
+ if (status != 0) {
+ mmio_setbits_32(phy->usb3hreg + USB3H_PHY_PWR_CTRL,
+ USB3H_DISABLE_EUSB_P0);
+ goto err_drdu2_phy_on;
+ }
+ break;
+ }
+
+ /* Device Mode */
+ if (phy_port->port_id == DRDU2_PORT) {
+ mmio_write_32(phy->drdu2reg + DRDU2_SOFT_RESET_CTRL,
+ DRDU2_BDC_AXI_SOFT_RST_N);
+ mmio_setbits_32(phy->drdu2reg + DRDU2_PHY_CTRL,
+ DRDU2_U2SOFT_RST_N);
+ }
+ /* Host Mode */
+ mmio_write_32(phy->usb3hreg + USB3H_SOFT_RESET_CTRL,
+ USB3H_XHC_AXI_SOFT_RST_N);
+ mmio_setbits_32(phy->usb3hreg + USB3H_U3PHY_CTRL, USB3H_U3SOFT_RST_N);
+
+ return 0U;
+ err_usb3h_phy_on:mmio_setbits_32(phy->usb3hreg + USB3H_PHY_PWR_CTRL,
+ (USB3H_DISABLE_EUSB_P1 |
+ USB3H_DISABLE_USB30_P0));
+ err_drdu2_phy_on:
+
+ return status;
+}
+
+static int32_t u3drd_phy_power_on(usb_phy_port_t *phy_port)
+{
+ usb_phy_t *phy = phy_port->p;
+ int32_t status;
+
+ switch (phy_port->port_id) {
+ case DRD3SS_PORT:
+ mmio_clrbits_32(phy->drdu3reg + DRDU3_PHY_PWR_CTRL,
+ (uint32_t) DRDU3_DISABLE_USB30_P0);
+
+ status = drdu3_u3_phy_power_on(phy->drdu3reg);
+ if (status != 0) {
+ goto err_drdu3_phy_on;
+ }
+ break;
+ case DRD3HS_PORT:
+ mmio_clrbits_32(phy->drdu3reg + DRDU3_PHY_PWR_CTRL,
+ (uint32_t) DRDU3_DISABLE_EUSB_P0);
+ mmio_setbits_32(AXI_DEBUG_CTRL,
+ AXI_DBG_CTRL_SSPHY_DRD_MODE_DISABLE);
+ mmio_setbits_32(USB3H_DEBUG_CTRL,
+ USB3H_DBG_CTRL_SSPHY_DRD_MODE_DISABLE);
+
+ mmio_clrbits_32(phy->drdu3reg + DRDU3_PWR_CTRL,
+ DRDU3_U2PHY_DFE_SWITCH_PWRONIN);
+ /* Delay as per external FSM spec */
+ udelay(10U);
+ mmio_clrbits_32(phy->drdu3reg + DRDU3_PWR_CTRL,
+ DRDU3_U2PHY_DFE_SWITCH_PWROKIN);
+
+ status = drdu3_u2_phy_power_on(phy->drdu3reg);
+ if (status != 0) {
+ goto err_drdu3_phy_on;
+ }
+
+ /* Host Mode */
+ mmio_setbits_32(phy->drdu3reg + DRDU3_SOFT_RESET_CTRL,
+ DRDU3_XHC_AXI_SOFT_RST_N);
+ mmio_setbits_32(phy->drdu3reg + DRDU3_U3PHY_CTRL,
+ DRDU3_U3XHC_SOFT_RST_N);
+ /* Device Mode */
+ mmio_setbits_32(phy->drdu3reg + DRDU3_SOFT_RESET_CTRL,
+ DRDU3_BDC_AXI_SOFT_RST_N);
+ mmio_setbits_32(phy->drdu3reg + DRDU3_U3PHY_CTRL,
+ DRDU3_U3BDC_SOFT_RST_N);
+ break;
+ }
+
+ return 0U;
+ err_drdu3_phy_on:mmio_setbits_32(phy->drdu3reg + DRDU3_PHY_PWR_CTRL,
+ (DRDU3_DISABLE_EUSB_P0 |
+ DRDU3_DISABLE_USB30_P0));
+
+ return status;
+}
+
+static void u3h_u2drd_phy_power_off(usb_phy_port_t *phy_port)
+{
+ usb_phy_t *p = phy_port->p;
+
+ switch (phy_port->port_id) {
+ case USB3SS_PORT:
+ mmio_setbits_32(p->usb3hreg + USB3H_PHY_PWR_CTRL,
+ USB3H_DISABLE_USB30_P0);
+ break;
+ case USB3HS_PORT:
+ mmio_setbits_32(p->usb3hreg + USB3H_PHY_PWR_CTRL,
+ USB3H_DISABLE_EUSB_P1);
+ break;
+ case DRDU2_PORT:
+ mmio_setbits_32(p->usb3hreg + USB3H_PHY_PWR_CTRL,
+ USB3H_DISABLE_EUSB_P0);
+ break;
+ }
+}
+
+static void u3drd_phy_power_off(usb_phy_port_t *phy_port)
+{
+ usb_phy_t *p = phy_port->p;
+
+ switch (phy_port->port_id) {
+ case DRD3SS_PORT:
+ mmio_setbits_32(p->drdu3reg + DRDU3_PHY_PWR_CTRL,
+ DRDU3_DISABLE_USB30_P0);
+ break;
+ case DRD3HS_PORT:
+ mmio_setbits_32(p->drdu3reg + DRDU3_PHY_PWR_CTRL,
+ DRDU3_DISABLE_EUSB_P0);
+ break;
+ }
+}
+
+int32_t usb_info_fill(usb_phy_t *phy_info)
+{
+ int32_t index;
+
+ if (phy_info->initialized != 0U) {
+ return USB_PHY_ALREADY_STARTED;
+ }
+
+ if (phy_info->phy_id == USB3H_DRDU2_PHY) {
+ phy_info->phy_port = usb_phy_port[USB3H_DRDU2_PHY - 1U];
+ phy_info->ports_enabled = 0x7U;
+ } else {
+ phy_info->phy_port = usb_phy_port[DRDU3_PHY - 1U];
+ phy_info->ports_enabled = 0x3U;
+ }
+
+ for (index = MAX_NR_PORTS - 1U; index > -1; index--) {
+ phy_info->phy_port[index].enabled = (phy_info->ports_enabled
+ >> index) & 0x1U;
+ phy_info->phy_port[index].p = phy_info;
+ phy_info->phy_port[index].port_id = index;
+ }
+
+ return 0U;
+}
+
+int32_t usb_phy_init(usb_platform_dev *device)
+{
+ int32_t status;
+ usb_phy_t *phy_info;
+ uint32_t index;
+
+ phy_info = (usb_phy_t *)device->pcd_id;
+
+ status = usb_info_fill(phy_info);
+ if (status != 0) {
+ return (status == USB_PHY_ALREADY_STARTED) ? 0 : status;
+ }
+
+ for (index = 0U; index < MAX_NR_PORTS; index++) {
+ if (phy_info->phy_port[index].enabled != 0U) {
+ switch (phy_info->phy_id) {
+ case USB3H_DRDU2_PHY:
+ status =
+ u3h_u2drd_phy_power_on(&phy_info->
+ phy_port[index]);
+ break;
+ default:
+ status =
+ u3drd_phy_power_on(&phy_info->
+ phy_port[index]);
+ }
+ }
+ }
+
+ phy_info->initialized = !status;
+ return status;
+}
+
+void usb_phy_shutdown(usb_platform_dev *device)
+{
+ usb_phy_t *phy_info;
+ uint32_t index;
+
+ phy_info = (usb_phy_t *)device->pcd_id;
+
+ phy_info->initialized = 0U;
+
+ for (index = 0U; index < MAX_NR_PORTS; index++) {
+ if (phy_info->phy_port[index].enabled != 0U) {
+ switch (phy_info->phy_id) {
+ case USB3H_DRDU2_PHY:
+ u3h_u2drd_phy_power_off(&phy_info->
+ phy_port[index]);
+ break;
+ case DRDU3_PHY:
+ u3drd_phy_power_off(&phy_info->phy_port[index]);
+ break;
+ default:
+ INFO("%s: invalid phy id 0x%x\n", __func__,
+ phy_info->phy_id);
+ }
+ }
+ }
+}
+
+int32_t usb_xhci_init(usb_platform_dev *device)
+{
+ int32_t status;
+
+ status = usb_phy_init(device);
+ if (status == USB_PHY_ALREADY_STARTED) {
+ status = 0U;
+ }
+
+ return status;
+}
+
+int32_t usb_device_init(unsigned int usb_func)
+{
+ int32_t status;
+ int32_t devices_initialized = 0U;
+
+ if ((usb_func & USB3H_USB2DRD) != 0U) {
+ status = usb_xhci_init(
+ &xhci_devices_configs[USB3H_USB2DRD_PHY]);
+ if (status == 0) {
+ devices_initialized++;
+ } else {
+ ERROR("%s(): USB3H_USB2DRD init failure\n", __func__);
+ }
+ }
+
+ if ((usb_func & USB3_DRD) != 0U) {
+ status = usb_xhci_init(&xhci_devices_configs[USB3_DRD_PHY]);
+ if (status == 0) {
+ devices_initialized++;
+ } else {
+ ERROR("%s(): USB3_DRD init failure\n", __func__);
+ }
+ }
+
+ return devices_initialized;
+}
diff --git a/plat/brcm/board/stingray/include/platform_usb.h b/plat/brcm/board/stingray/include/platform_usb.h
new file mode 100644
index 0000000..5b5309f
--- /dev/null
+++ b/plat/brcm/board/stingray/include/platform_usb.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2019 - 2021, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_USB_H
+#define PLATFORM_USB_H
+
+#include <platform_def.h>
+
+#define USB3_DRD BIT(0U)
+#define USB3H_USB2DRD BIT(1U)
+
+extern const unsigned int xhc_portsc_reg_offset[MAX_USB_PORTS];
+
+void xhci_phy_init(void);
+
+#endif /* PLATFORM_USB_H */
diff --git a/plat/brcm/board/stingray/include/sr_def.h b/plat/brcm/board/stingray/include/sr_def.h
index be0dee1..277836e 100644
--- a/plat/brcm/board/stingray/include/sr_def.h
+++ b/plat/brcm/board/stingray/include/sr_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2020, Broadcom
+ * Copyright (c) 2016-2021, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -193,6 +193,11 @@
#define PLAT_CHIP_REV_GET (mmio_read_32(ICFG_CHIP_REVISION_ID))
/*******************************************************************************
+ * CMIC MII (MDIO) related constant
+ ******************************************************************************/
+#define PLAT_CMIC_MIIM_BASE 0x68920000U
+
+/*******************************************************************************
* Timers related constants
******************************************************************************/
/* ChipcommonG_tim0_TIM_TIMER1Load 0x68930000 */
diff --git a/plat/brcm/board/stingray/include/usb_phy.h b/plat/brcm/board/stingray/include/usb_phy.h
new file mode 100644
index 0000000..7d83182
--- /dev/null
+++ b/plat/brcm/board/stingray/include/usb_phy.h
@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 2017 - 2021, Broadcom
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef USB_PHY_H
+#define USB_PHY_H
+
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include <platform_def.h>
+
+#define DRDU2_U2PLL_NDIV_FRAC_OFFSET 0x0U
+
+#define DRDU2_U2PLL_NDIV_INT 0x4U
+
+#define DRDU2_U2PLL_CTRL 0x8U
+#define DRDU2_U2PLL_LOCK BIT(6U)
+#define DRDU2_U2PLL_RESETB BIT(5U)
+#define DRDU2_U2PLL_PDIV_MASK 0xFU
+#define DRDU2_U2PLL_PDIV_OFFSET 1U
+#define DRDU2_U2PLL_SUSPEND_EN BIT(0U)
+
+#define DRDU2_PHY_CTRL 0x0CU
+#define DRDU2_U2IDDQ BIT(30U)
+#define DRDU2_U2SOFT_RST_N BIT(29U)
+#define DRDU2_U2PHY_ON_FLAG BIT(22U)
+#define DRDU2_U2PHY_PCTL_MASK 0xFFFFU
+#define DRDU2_U2PHY_PCTL_OFFSET 6U
+#define DRDU2_U2PHY_RESETB BIT(5U)
+#define DRDU2_U2PHY_ISO BIT(4U)
+#define DRDU2_U2AFE_BG_PWRDWNB BIT(3U)
+#define DRDU2_U2AFE_PLL_PWRDWNB BIT(2U)
+#define DRDU2_U2AFE_LDO_PWRDWNB BIT(1U)
+#define DRDU2_U2CTRL_CORERDY BIT(0U)
+
+#define DRDU2_STRAP_CTRL 0x18U
+#define DRDU2_FORCE_HOST_MODE BIT(5U)
+#define DRDU2_FORCE_DEVICE_MODE BIT(4U)
+#define BDC_USB_STP_SPD_MASK 0x7U
+#define BDC_USB_STP_SPD_OFFSET 0U
+
+#define DRDU2_PWR_CTRL 0x1CU
+#define DRDU2_U2PHY_DFE_SWITCH_PWROKIN_I BIT(2U)
+#define DRDU2_U2PHY_DFE_SWITCH_PWRONIN_I BIT(1U)
+
+#define DRDU2_SOFT_RESET_CTRL 0x20U
+#define DRDU2_BDC_AXI_SOFT_RST_N BIT(0U)
+
+#define USB3H_U2PLL_NDIV_FRAC 0x4U
+
+#define USB3H_U2PLL_NDIV_INT 0x8U
+
+#define USB3H_U2PLL_CTRL 0xCU
+#define USB3H_U2PLL_LOCK BIT(6U)
+#define USB3H_U2PLL_RESETB BIT(5U)
+#define USB3H_U2PLL_PDIV_MASK 0xFU
+#define USB3H_U2PLL_PDIV_OFFSET 1U
+
+#define USB3H_U2PHY_CTRL 0x10U
+#define USB3H_U2PHY_ON_FLAG 22U
+#define USB3H_U2PHY_PCTL_MASK 0xFFFFU
+#define USB3H_U2PHY_PCTL_OFFSET 6U
+#define USB3H_U2PHY_IDDQ BIT(29U)
+#define USB3H_U2PHY_RESETB BIT(5U)
+#define USB3H_U2PHY_ISO BIT(4U)
+#define USB3H_U2AFE_BG_PWRDWNB BIT(3U)
+#define USB3H_U2AFE_PLL_PWRDWNB BIT(2U)
+#define USB3H_U2AFE_LDO_PWRDWNB BIT(1U)
+#define USB3H_U2CTRL_CORERDY BIT(0U)
+
+#define USB3H_U3PHY_CTRL 0x14U
+#define USB3H_U3SOFT_RST_N BIT(30U)
+#define USB3H_U3MDIO_RESETB_I BIT(29U)
+#define USB3H_U3POR_RESET_I BIT(28U)
+#define USB3H_U3PHY_PCTL_MASK 0xFFFFU
+#define USB3H_U3PHY_PCTL_OFFSET 2U
+#define USB3H_U3PHY_RESETB BIT(1U)
+
+#define USB3H_U3PHY_PLL_CTRL 0x18U
+#define USB3H_U3PLL_REFCLK_MASK 0x7U
+#define USB3H_U3PLL_REFCLK_OFFSET 4U
+#define USB3H_U3PLL_SS_LOCK BIT(3U)
+#define USB3H_U3PLL_SEQ_START BIT(2U)
+#define USB3H_U3SSPLL_SUSPEND_EN BIT(1U)
+#define USB3H_U3PLL_RESETB BIT(0U)
+
+#define USB3H_PWR_CTRL 0x28U
+#define USB3H_PWR_CTRL_OVERRIDE_I_R 4U
+#define USB3H_PWR_CTRL_U2PHY_DFE_SWITCH_PWROKIN BIT(11U)
+#define USB3H_PWR_CTRL_U2PHY_DFE_SWITCH_PWRONIN BIT(10U)
+
+#define USB3H_SOFT_RESET_CTRL 0x2CU
+#define USB3H_XHC_AXI_SOFT_RST_N BIT(1U)
+
+#define USB3H_PHY_PWR_CTRL 0x38U
+#define USB3H_DISABLE_USB30_P0 BIT(2U)
+#define USB3H_DISABLE_EUSB_P1 BIT(1U)
+#define USB3H_DISABLE_EUSB_P0 BIT(0U)
+
+
+#define DRDU3_U2PLL_NDIV_FRAC 0x4U
+
+#define DRDU3_U2PLL_NDIV_INT 0x8U
+
+#define DRDU3_U2PLL_CTRL 0xCU
+#define DRDU3_U2PLL_LOCK BIT(6U)
+#define DRDU3_U2PLL_RESETB BIT(5U)
+#define DRDU3_U2PLL_PDIV_MASK 0xFU
+#define DRDU3_U2PLL_PDIV_OFFSET 1U
+
+#define DRDU3_U2PHY_CTRL 0x10U
+#define DRDU3_U2PHY_IDDQ BIT(29U)
+#define DRDU3_U2PHY_ON_FLAG BIT(22U)
+#define DRDU3_U2PHY_PCTL_MASK 0xFFFFU
+#define DRDU3_U2PHY_PCTL_OFFSET 6U
+#define DRDU3_U2PHY_RESETB BIT(5U)
+#define DRDU3_U2PHY_ISO BIT(4U)
+#define DRDU3_U2AFE_BG_PWRDWNB BIT(3U)
+#define DRDU3_U2AFE_PLL_PWRDWNB BIT(2U)
+#define DRDU3_U2AFE_LDO_PWRDWNB BIT(1U)
+#define DRDU3_U2CTRL_CORERDY BIT(0U)
+
+#define DRDU3_U3PHY_CTRL 0x14U
+#define DRDU3_U3XHC_SOFT_RST_N BIT(31U)
+#define DRDU3_U3BDC_SOFT_RST_N BIT(30U)
+#define DRDU3_U3MDIO_RESETB_I BIT(29U)
+#define DRDU3_U3POR_RESET_I BIT(28U)
+#define DRDU3_U3PHY_PCTL_MASK 0xFFFFU
+#define DRDU3_U3PHY_PCTL_OFFSET 2U
+#define DRDU3_U3PHY_RESETB BIT(1U)
+
+#define DRDU3_U3PHY_PLL_CTRL 0x18U
+#define DRDU3_U3PLL_REFCLK_MASK 0x7U
+#define DRDU3_U3PLL_REFCLK_OFFSET 4U
+#define DRDU3_U3PLL_SS_LOCK BIT(3U)
+#define DRDU3_U3PLL_SEQ_START BIT(2U)
+#define DRDU3_U3SSPLL_SUSPEND_EN BIT(1U)
+#define DRDU3_U3PLL_RESETB BIT(0U)
+
+#define DRDU3_STRAP_CTRL 0x28U
+#define BDC_USB_STP_SPD_MASK 0x7U
+#define BDC_USB_STP_SPD_OFFSET 0U
+#define BDC_USB_STP_SPD_SS 0x0U
+#define BDC_USB_STP_SPD_HS 0x2U
+
+#define DRDU3_PWR_CTRL 0x2cU
+#define DRDU3_U2PHY_DFE_SWITCH_PWROKIN BIT(12U)
+#define DRDU3_U2PHY_DFE_SWITCH_PWRONIN BIT(11U)
+#define DRDU3_PWR_CTRL_OVERRIDE_I_R 4U
+
+#define DRDU3_SOFT_RESET_CTRL 0x30U
+#define DRDU3_XHC_AXI_SOFT_RST_N BIT(1U)
+#define DRDU3_BDC_AXI_SOFT_RST_N BIT(0U)
+
+#define DRDU3_PHY_PWR_CTRL 0x3cU
+#define DRDU3_DISABLE_USB30_P0 BIT(2U)
+#define DRDU3_DISABLE_EUSB_P1 BIT(1U)
+#define DRDU3_DISABLE_EUSB_P0 BIT(0U)
+
+#define PLL_REFCLK_PAD 0x0U
+#define PLL_REFCLK_25MHZ 0x1U
+#define PLL_REFCLK_96MHZ 0x2U
+#define PLL_REFCLK_INTERNAL 0x3U
+/* USB PLL lock time out for 10 ms */
+#define PLL_LOCK_RETRY_COUNT 10000U
+
+
+#define U2PLL_NDIV_INT_VAL 0x13U
+#define U2PLL_NDIV_FRAC_VAL 0x1005U
+#define U2PLL_PDIV_VAL 0x1U
+/*
+ * Using external FSM
+ * BIT-3:2: device mode; mode is not effect
+ * BIT-1: soft reset active low
+ */
+#define U2PHY_PCTL_VAL 0x0003U
+/* Non-driving signal low */
+#define U2PHY_PCTL_NON_DRV_LOW 0x0002U
+#define U3PHY_PCTL_VAL 0x0006U
+
+#define MAX_NR_PORTS 3U
+
+#define USB3H_DRDU2_PHY 1U
+#define DRDU3_PHY 2U
+
+#define USB_HOST_MODE 1U
+#define USB_DEV_MODE 2U
+
+#define USB3SS_PORT 0U
+#define DRDU2_PORT 1U
+#define USB3HS_PORT 2U
+
+#define DRD3SS_PORT 0U
+#define DRD3HS_PORT 1U
+
+#define SR_USB_PHY_COUNT 2U
+
+#define DRDU3_PIPE_CTRL 0x68500000U
+#define DRDU3H_XHC_REGS_CPLIVER 0x68501000U
+#define USB3H_PIPE_CTRL 0x68510000U
+#define DRD2U3H_XHC_REGS_CPLIVER 0x68511000U
+#define DRDU2_U2PLL_NDIV_FRAC 0x68520000U
+
+#define AXI_DEBUG_CTRL 0x68500038U
+#define AXI_DBG_CTRL_SSPHY_DRD_MODE_DISABLE BIT(12U)
+
+#define USB3H_DEBUG_CTRL 0x68510034U
+#define USB3H_DBG_CTRL_SSPHY_DRD_MODE_DISABLE BIT(7U)
+
+typedef struct _usb_phy_port usb_phy_port_t;
+
+typedef struct {
+ uint32_t drdu2reg;
+ uint32_t usb3hreg;
+ uint32_t drdu3reg;
+ uint32_t phy_id;
+ uint32_t ports_enabled;
+ uint32_t initialized;
+ usb_phy_port_t *phy_port;
+} usb_phy_t;
+
+struct _usb_phy_port {
+ uint32_t port_id;
+ uint32_t mode;
+ uint32_t enabled;
+ usb_phy_t *p;
+};
+
+struct u2_phy_ext_fsm {
+ uint32_t pll_ctrl_reg;
+ uint32_t phy_ctrl_reg;
+ uint32_t phy_iddq;
+ uint32_t pwr_ctrl_reg;
+ uint32_t pwr_okin;
+ uint32_t pwr_onin;
+};
+
+#endif /* USB_PHY_H */
diff --git a/plat/brcm/board/stingray/platform.mk b/plat/brcm/board/stingray/platform.mk
index c5509bb..aa2fe86 100644
--- a/plat/brcm/board/stingray/platform.mk
+++ b/plat/brcm/board/stingray/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2019-2020, Broadcom
+# Copyright (c) 2019-2021, Broadcom
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -73,6 +73,12 @@
BOARD_CFG := bcm958742t
endif
+# Use USB
+ifeq (${USE_USB},yes)
+$(info Using USB)
+$(eval $(call add_define,USE_USB))
+endif
+
# Use PAXB
ifeq (${USE_PAXB},yes)
$(info Using PAXB)
@@ -190,17 +196,22 @@
plat/${SOC_DIR}/src/tz_sec.c \
drivers/arm/tzc/tzc400.c \
plat/${SOC_DIR}/driver/plat_emmc.c \
- plat/${SOC_DIR}/src/topology.c
+ plat/${SOC_DIR}/src/topology.c \
+ drivers/brcm/mdio/mdio.c
ifeq (${USE_CHIMP},yes)
PLAT_BL_COMMON_SOURCES += drivers/brcm/chimp.c
endif
+ifeq (${USE_USB},yes)
+PLAT_BL_COMMON_SOURCES += plat/${SOC_DIR}/driver/usb.c \
+ plat/${SOC_DIR}/driver/usb_phy.c
+endif
+
BL2_SOURCES += plat/${SOC_DIR}/driver/ihost_pll_config.c \
plat/${SOC_DIR}/src/bl2_setup.c \
plat/${SOC_DIR}/driver/swreg.c
-
ifeq (${USE_DDR},yes)
PLAT_INCLUDES += -Iplat/${SOC_DIR}/driver/ddr/soc/include
else
diff --git a/plat/brcm/board/stingray/src/bl31_setup.c b/plat/brcm/board/stingray/src/bl31_setup.c
index a2a274d..04df6a0 100644
--- a/plat/brcm/board/stingray/src/bl31_setup.c
+++ b/plat/brcm/board/stingray/src/bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015 - 2020, Broadcom
+ * Copyright (c) 2015 - 2021, Broadcom
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -28,6 +28,9 @@
#include <paxb.h>
#include <paxc.h>
#include <platform_def.h>
+#ifdef USE_USB
+#include <platform_usb.h>
+#endif
#include <sdio.h>
#include <sr_utils.h>
#include <timer_sync.h>
diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c
index ba4c366..345fec3 100644
--- a/plat/common/aarch64/plat_common.c
+++ b/plat/common/aarch64/plat_common.c
@@ -28,7 +28,7 @@
#pragma weak plat_sdei_validate_entry_point
#endif
-#pragma weak plat_ea_handler
+#pragma weak plat_ea_handler = plat_default_ea_handler
void bl31_plat_runtime_setup(void)
{
@@ -79,7 +79,7 @@
#endif /* !ENABLE_BACKTRACE */
/* RAS functions common to AArch64 ARM platforms */
-void plat_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
+void plat_default_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
void *handle, uint64_t flags)
{
#if RAS_EXTENSION
@@ -90,6 +90,7 @@
#endif
unsigned int level = (unsigned int)GET_EL(read_spsr_el3());
+ ERROR_NL();
ERROR("Unhandled External Abort received on 0x%lx from %s\n",
read_mpidr_el1(), get_el_str(level));
ERROR("exception reason=%u syndrome=0x%llx\n", ea_reason, syndrome);
diff --git a/plat/hisilicon/hikey/hikey_bl1_setup.c b/plat/hisilicon/hikey/hikey_bl1_setup.c
index 86e4fd6..01c48ec 100644
--- a/plat/hisilicon/hikey/hikey_bl1_setup.c
+++ b/plat/hisilicon/hikey/hikey_bl1_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,6 +27,7 @@
/* Data structure which holds the extents of the trusted RAM for BL1 */
static meminfo_t bl1_tzram_layout;
static console_t console;
+static struct mmc_device_info mmc_info;
enum {
BOOT_NORMAL = 0,
@@ -78,7 +79,6 @@
void bl1_platform_setup(void)
{
dw_mmc_params_t params;
- struct mmc_device_info info;
assert((HIKEY_BL1_MMC_DESC_BASE >= SRAM_BASE) &&
((SRAM_BASE + SRAM_SIZE) >=
@@ -99,8 +99,8 @@
params.clk_rate = 24 * 1000 * 1000;
params.bus_width = MMC_BUS_WIDTH_8;
params.flags = MMC_FLAG_CMD23;
- info.mmc_dev_type = MMC_IS_EMMC;
- dw_mmc_init(¶ms, &info);
+ mmc_info.mmc_dev_type = MMC_IS_EMMC;
+ dw_mmc_init(¶ms, &mmc_info);
hikey_io_setup();
}
diff --git a/plat/hisilicon/hikey/hikey_bl2_setup.c b/plat/hisilicon/hikey/hikey_bl2_setup.c
index feb7f8a..a90f12c 100644
--- a/plat/hisilicon/hikey/hikey_bl2_setup.c
+++ b/plat/hisilicon/hikey/hikey_bl2_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -33,6 +33,7 @@
static meminfo_t bl2_el3_tzram_layout;
static console_t console;
+static struct mmc_device_info mmc_info;
enum {
BOOT_MODE_RECOVERY = 0,
@@ -290,7 +291,6 @@
void bl2_platform_setup(void)
{
dw_mmc_params_t params;
- struct mmc_device_info info;
hikey_sp804_init();
hikey_gpio_init();
@@ -322,8 +322,8 @@
params.clk_rate = 24 * 1000 * 1000;
params.bus_width = MMC_BUS_WIDTH_8;
params.flags = MMC_FLAG_CMD23;
- info.mmc_dev_type = MMC_IS_EMMC;
- dw_mmc_init(¶ms, &info);
+ mmc_info.mmc_dev_type = MMC_IS_EMMC;
+ dw_mmc_init(¶ms, &mmc_info);
hikey_io_setup();
}
diff --git a/plat/hisilicon/poplar/bl1_plat_setup.c b/plat/hisilicon/poplar/bl1_plat_setup.c
index 047ba62..acc1f0e 100644
--- a/plat/hisilicon/poplar/bl1_plat_setup.c
+++ b/plat/hisilicon/poplar/bl1_plat_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -30,6 +30,10 @@
static meminfo_t bl2_tzram_layout;
static console_t console;
+#if !POPLAR_RECOVERY
+static struct mmc_device_info mmc_info;
+#endif
+
/*
* Cannot use default weak implementation in bl1_main.c because BL1 RW data is
* not at the top of the secure memory.
@@ -90,7 +94,6 @@
{
int i;
#if !POPLAR_RECOVERY
- struct mmc_device_info info;
dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE);
#endif
@@ -103,8 +106,8 @@
#if !POPLAR_RECOVERY
/* SoC-specific emmc register are initialized/configured by bootrom */
INFO("BL1: initializing emmc\n");
- info.mmc_dev_type = MMC_IS_EMMC;
- dw_mmc_init(¶ms, &info);
+ mmc_info.mmc_dev_type = MMC_IS_EMMC;
+ dw_mmc_init(¶ms, &mmc_info);
#endif
plat_io_setup();
diff --git a/plat/hisilicon/poplar/bl2_plat_setup.c b/plat/hisilicon/poplar/bl2_plat_setup.c
index 482935c..ee46772 100644
--- a/plat/hisilicon/poplar/bl2_plat_setup.c
+++ b/plat/hisilicon/poplar/bl2_plat_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -26,6 +26,9 @@
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
static console_t console;
+#if !POPLAR_RECOVERY
+static struct mmc_device_info mmc_info;
+#endif
/*******************************************************************************
* Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
@@ -171,8 +174,6 @@
{
struct meminfo *mem_layout = (struct meminfo *)arg1;
#if !POPLAR_RECOVERY
- struct mmc_device_info info;
-
dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE);
#endif
@@ -187,8 +188,8 @@
#if !POPLAR_RECOVERY
/* SoC-specific emmc register are initialized/configured by bootrom */
INFO("BL2: initializing emmc\n");
- info.mmc_dev_type = MMC_IS_EMMC;
- dw_mmc_init(¶ms, &info);
+ mmc_info.mmc_dev_type = MMC_IS_EMMC;
+ dw_mmc_init(¶ms, &mmc_info);
#endif
plat_io_setup();
diff --git a/plat/imx/common/imx_sip_handler.c b/plat/imx/common/imx_sip_handler.c
index f9f5577..d4b3425 100644
--- a/plat/imx/common/imx_sip_handler.c
+++ b/plat/imx/common/imx_sip_handler.c
@@ -14,6 +14,7 @@
#include <common/runtime_svc.h>
#include <imx_sip_svc.h>
#include <lib/el3_runtime/context_mgmt.h>
+#include <lib/mmio.h>
#include <sci/sci.h>
#if defined(PLAT_imx8qm) || defined(PLAT_imx8qx)
@@ -145,6 +146,37 @@
#endif /* defined(PLAT_imx8qm) || defined(PLAT_imx8qx) */
+#if defined(PLAT_imx8mm) || defined(PLAT_imx8mq)
+int imx_src_handler(uint32_t smc_fid,
+ u_register_t x1,
+ u_register_t x2,
+ u_register_t x3,
+ void *handle)
+{
+ uint32_t val;
+
+ switch (x1) {
+ case IMX_SIP_SRC_SET_SECONDARY_BOOT:
+ if (x2 != 0U) {
+ mmio_setbits_32(IMX_SRC_BASE + SRC_GPR10_OFFSET,
+ SRC_GPR10_PERSIST_SECONDARY_BOOT);
+ } else {
+ mmio_clrbits_32(IMX_SRC_BASE + SRC_GPR10_OFFSET,
+ SRC_GPR10_PERSIST_SECONDARY_BOOT);
+ }
+ break;
+ case IMX_SIP_SRC_IS_SECONDARY_BOOT:
+ val = mmio_read_32(IMX_SRC_BASE + SRC_GPR10_OFFSET);
+ return !!(val & SRC_GPR10_PERSIST_SECONDARY_BOOT);
+ default:
+ return SMC_UNK;
+
+ };
+
+ return 0;
+}
+#endif /* defined(PLAT_imx8mm) || defined(PLAT_imx8mq) */
+
static uint64_t imx_get_commit_hash(u_register_t x2,
u_register_t x3,
u_register_t x4)
diff --git a/plat/imx/common/imx_sip_svc.c b/plat/imx/common/imx_sip_svc.c
index 20e1479..fd54820 100644
--- a/plat/imx/common/imx_sip_svc.c
+++ b/plat/imx/common/imx_sip_svc.c
@@ -48,6 +48,11 @@
case IMX_SIP_MISC_SET_TEMP:
SMC_RET1(handle, imx_misc_set_temp_handler(smc_fid, x1, x2, x3, x4));
#endif
+#if defined(PLAT_imx8mm) || defined(PLAT_imx8mq)
+ case IMX_SIP_SRC:
+ SMC_RET1(handle, imx_src_handler(smc_fid, x1, x2, x3, handle));
+ break;
+#endif
case IMX_SIP_BUILDINFO:
SMC_RET1(handle, imx_buildinfo_handler(smc_fid, x1, x2, x3, x4));
default:
diff --git a/plat/imx/common/include/imx_sip_svc.h b/plat/imx/common/include/imx_sip_svc.h
index 0a2d750..6c7a760 100644
--- a/plat/imx/common/include/imx_sip_svc.h
+++ b/plat/imx/common/include/imx_sip_svc.h
@@ -17,6 +17,10 @@
#define IMX_SIP_BUILDINFO 0xC2000003
#define IMX_SIP_BUILDINFO_GET_COMMITHASH 0x00
+#define IMX_SIP_SRC 0xC2000005
+#define IMX_SIP_SRC_SET_SECONDARY_BOOT 0x10
+#define IMX_SIP_SRC_IS_SECONDARY_BOOT 0x11
+
#define IMX_SIP_GET_SOC_INFO 0xC2000006
#define IMX_SIP_WAKEUP_SRC 0xC2000009
@@ -38,6 +42,11 @@
u_register_t x2, u_register_t x3);
#endif
+#if defined(PLAT_imx8mm) || defined(PLAT_imx8mq)
+int imx_src_handler(uint32_t smc_fid, u_register_t x1,
+ u_register_t x2, u_register_t x3, void *handle);
+#endif
+
#if (defined(PLAT_imx8qm) || defined(PLAT_imx8qx))
int imx_cpufreq_handler(uint32_t smc_fid, u_register_t x1,
u_register_t x2, u_register_t x3);
diff --git a/plat/imx/imx7/picopi/picopi_bl2_el3_setup.c b/plat/imx/imx7/picopi/picopi_bl2_el3_setup.c
index 3cf5c36..2df96ae 100644
--- a/plat/imx/imx7/picopi/picopi_bl2_el3_setup.c
+++ b/plat/imx/imx7/picopi/picopi_bl2_el3_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -43,6 +43,8 @@
IOMUXC_SW_PAD_CTL_PAD_SD3_SLEW_SLOW | \
IOMUXC_SW_PAD_CTL_PAD_SD3_DSE_3_X6)
+static struct mmc_device_info mmc_info;
+
static void picopi_setup_pinmux(void)
{
/* Configure UART5 TX */
@@ -93,14 +95,13 @@
static void picopi_usdhc_setup(void)
{
imx_usdhc_params_t params;
- struct mmc_device_info info;
zeromem(¶ms, sizeof(imx_usdhc_params_t));
params.reg_base = PLAT_PICOPI_BOOT_MMC_BASE;
params.clk_rate = 25000000;
params.bus_width = MMC_BUS_WIDTH_8;
- info.mmc_dev_type = MMC_IS_EMMC;
- imx_usdhc_init(¶ms, &info);
+ mmc_info.mmc_dev_type = MMC_IS_EMMC;
+ imx_usdhc_init(¶ms, &mmc_info);
}
static void picopi_setup_usb_clocks(void)
diff --git a/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
index 935a411..ec13ade 100644
--- a/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
+++ b/plat/imx/imx7/warp7/warp7_bl2_el3_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -69,6 +69,8 @@
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_EN | \
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_1_X4)
+static struct mmc_device_info mmc_info;
+
static void warp7_setup_pinmux(void)
{
/* Configure UART1 TX */
@@ -99,14 +101,13 @@
static void warp7_usdhc_setup(void)
{
imx_usdhc_params_t params;
- struct mmc_device_info info;
zeromem(¶ms, sizeof(imx_usdhc_params_t));
params.reg_base = PLAT_WARP7_BOOT_MMC_BASE;
params.clk_rate = 25000000;
params.bus_width = MMC_BUS_WIDTH_8;
- info.mmc_dev_type = MMC_IS_EMMC;
- imx_usdhc_init(¶ms, &info);
+ mmc_info.mmc_dev_type = MMC_IS_EMMC;
+ imx_usdhc_init(¶ms, &mmc_info);
}
static void warp7_setup_usb_clocks(void)
diff --git a/plat/imx/imx8m/imx8m_psci_common.c b/plat/imx/imx8m/imx8m_psci_common.c
index dbb772d..9dfd311 100644
--- a/plat/imx/imx8m/imx8m_psci_common.c
+++ b/plat/imx/imx8m/imx8m_psci_common.c
@@ -152,19 +152,45 @@
req_state->pwr_domain_state[i] = PLAT_STOP_OFF_STATE;
}
-void __dead2 imx_system_reset(void)
+static void __dead2 imx_wdog_restart(bool external_reset)
{
uintptr_t wdog_base = IMX_WDOG_BASE;
unsigned int val;
- /* WDOG_B reset */
val = mmio_read_16(wdog_base);
-#ifdef IMX_WDOG_B_RESET
- val = (val & 0x00FF) | WDOG_WCR_WDZST | WDOG_WCR_WDE |
- WDOG_WCR_WDT | WDOG_WCR_SRS;
-#else
- val = (val & 0x00FF) | WDOG_WCR_WDZST | WDOG_WCR_SRS;
-#endif
+ /*
+ * Common watchdog init flags, for additional details check
+ * 6.6.4.1 Watchdog Control Register (WDOGx_WCR)
+ *
+ * Initial bit selection:
+ * WDOG_WCR_WDE - Enable the watchdog.
+ *
+ * 0x000E mask is used to keep previous values (that could be set
+ * in SPL) of WDBG and WDE/WDT (both are write-one once-only bits).
+ */
+ val = (val & 0x000E) | WDOG_WCR_WDE;
+ if (external_reset) {
+ /*
+ * To assert WDOG_B (external reset) we have
+ * to set WDA bit 0 (already set in previous step).
+ * SRS bits are required to be set to 1 (no effect on the
+ * system).
+ */
+ val |= WDOG_WCR_SRS;
+ } else {
+ /*
+ * To assert Software Reset Signal (internal reset) we have
+ * to set SRS bit to 0 (already set in previous step).
+ * SRE bit is required to be set to 1 when used in
+ * conjunction with the Software Reset Signal before
+ * SRS asserton, otherwise SRS bit will just automatically
+ * reset to 1.
+ *
+ * Also we set WDA to 1 (no effect on system).
+ */
+ val |= WDOG_WCR_SRE | WDOG_WCR_WDA;
+ }
+
mmio_write_16(wdog_base, val);
mmio_write_16(wdog_base + WDOG_WSR, 0x5555);
@@ -173,6 +199,27 @@
;
}
+void __dead2 imx_system_reset(void)
+{
+#ifdef IMX_WDOG_B_RESET
+ imx_wdog_restart(true);
+#else
+ imx_wdog_restart(false);
+#endif
+}
+
+int imx_system_reset2(int is_vendor, int reset_type, u_register_t cookie)
+{
+ imx_wdog_restart(false);
+
+ /*
+ * imx_wdog_restart cannot return (as it's a __dead function),
+ * however imx_system_reset2 has to return some value according
+ * to PSCI v1.1 spec.
+ */
+ return 0;
+}
+
void __dead2 imx_system_off(void)
{
mmio_write_32(IMX_SNVS_BASE + SNVS_LPCR, SNVS_LPCR_SRTC_ENV |
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl2_el3_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl2_el3_setup.c
new file mode 100644
index 0000000..937774c
--- /dev/null
+++ b/plat/imx/imx8m/imx8mm/imx8mm_bl2_el3_setup.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2017-2021 NXP
+ * Copyright 2021 Arm
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <arch_helpers.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <common/desc_image_load.h>
+#include <context.h>
+#include <drivers/console.h>
+#include <drivers/generic_delay_timer.h>
+#include <drivers/mmc.h>
+#include <lib/mmio.h>
+#include <lib/optee_utils.h>
+#include <lib/utils.h>
+#include <stdbool.h>
+#include <tbbr_img_def.h>
+
+#include <imx_aipstz.h>
+#include <imx_csu.h>
+#include <imx_uart.h>
+#include <imx_usdhc.h>
+#include <plat/common/platform.h>
+
+#include "imx8mm_private.h"
+#include "platform_def.h"
+
+static const struct aipstz_cfg aipstz[] = {
+ {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
+ {0},
+};
+
+static void imx8mm_usdhc_setup(void)
+{
+ imx_usdhc_params_t params;
+ struct mmc_device_info info;
+
+ params.reg_base = PLAT_IMX8MM_BOOT_MMC_BASE;
+ /*
+ The imx8mm SD Card Speed modes for USDHC2
+ +--------------+--------------------+--------------+--------------+
+ |Bus Speed Mode|Max. Clock Frequency|Max. Bus Speed|Signal Voltage|
+ +--------------+--------------------+--------------+--------------+
+ |Default Speed | 25 MHz | 12.5 MB/s | 3.3V |
+ |High Speed | 50 MHz | 25 MB/s | 3.3V |
+ +--------------+--------------------+--------------+--------------+
+
+ We pick 50 Mhz here for High Speed access.
+ */
+ params.clk_rate = 50000000;
+ params.bus_width = MMC_BUS_WIDTH_1;
+ params.flags = 0;
+ info.mmc_dev_type = MMC_IS_SD;
+ info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
+ imx_usdhc_init(¶ms, &info);
+}
+
+void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
+ u_register_t arg3, u_register_t arg4)
+{
+ int i;
+ static console_t console;
+
+ /* enable CSU NS access permission */
+ for (i = 0; i < MAX_CSU_NUM; i++) {
+ mmio_write_32(IMX_CSU_BASE + i * 4, CSU_CSL_OPEN_ACCESS);
+ }
+
+ /* config the aips access permission */
+ imx_aipstz_init(aipstz);
+
+ console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
+ IMX_CONSOLE_BAUDRATE, &console);
+
+ generic_delay_timer_init();
+
+ /* select the CKIL source to 32K OSC */
+ mmio_write_32(0x30360124, 0x1);
+
+ imx8mm_usdhc_setup();
+
+ /* Open handles to a FIP image */
+ plat_imx8mm_io_setup();
+}
+
+void bl2_el3_plat_arch_setup(void)
+{
+}
+
+void bl2_platform_setup(void)
+{
+}
+
+int bl2_plat_handle_post_image_load(unsigned int image_id)
+{
+ int err = 0;
+ bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
+ bl_mem_params_node_t *pager_mem_params = NULL;
+ bl_mem_params_node_t *paged_mem_params = NULL;
+
+ assert(bl_mem_params);
+
+ switch (image_id) {
+ case BL32_IMAGE_ID:
+ pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
+ assert(pager_mem_params);
+
+ paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
+ assert(paged_mem_params);
+
+ err = parse_optee_header(&bl_mem_params->ep_info,
+ &pager_mem_params->image_info,
+ &paged_mem_params->image_info);
+ if (err != 0) {
+ WARN("OPTEE header parse error.\n");
+ }
+
+ break;
+ default:
+ /* Do nothing in default case */
+ break;
+ }
+
+ return err;
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+ return COUNTER_FREQUENCY;
+}
+
+void bl2_plat_runtime_setup(void)
+{
+ return;
+}
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl2_mem_params_desc.c b/plat/imx/imx8m/imx8mm/imx8mm_bl2_mem_params_desc.c
new file mode 100644
index 0000000..e44345d
--- /dev/null
+++ b/plat/imx/imx8m/imx8mm/imx8mm_bl2_mem_params_desc.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <common/desc_image_load.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+static bl_mem_params_node_t bl2_mem_params_descs[] = {
+ {
+ .image_id = BL31_IMAGE_ID,
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+ entry_point_info_t,
+ SECURE | EXECUTABLE | EP_FIRST_EXE),
+ .ep_info.pc = BL31_BASE,
+ .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+ DISABLE_ALL_EXCEPTIONS),
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t,
+ IMAGE_ATTRIB_PLAT_SETUP),
+ .image_info.image_base = BL31_BASE,
+ .image_info.image_max_size = BL31_LIMIT - BL31_BASE,
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+ {
+ .image_id = BL32_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+ entry_point_info_t,
+ SECURE | EXECUTABLE),
+ .ep_info.pc = BL32_BASE,
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
+ image_info_t, 0),
+
+ .image_info.image_base = BL32_BASE,
+ .image_info.image_max_size = BL32_SIZE,
+
+ .next_handoff_image_id = BL33_IMAGE_ID,
+ },
+ {
+ .image_id = BL32_EXTRA1_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+ entry_point_info_t,
+ SECURE | NON_EXECUTABLE),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
+ image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
+ .image_info.image_base = BL32_BASE,
+ .image_info.image_max_size = BL32_SIZE,
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+ {
+ /* This is a zero sized image so we don't set base or size */
+ .image_id = BL32_EXTRA2_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t,
+ SECURE | NON_EXECUTABLE),
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t,
+ IMAGE_ATTRIB_SKIP_LOADING),
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ },
+ {
+ .image_id = BL33_IMAGE_ID,
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
+ entry_point_info_t,
+ NON_SECURE | EXECUTABLE),
+ # ifdef PRELOADED_BL33_BASE
+ .ep_info.pc = PLAT_NS_IMAGE_OFFSET,
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t,
+ IMAGE_ATTRIB_SKIP_LOADING),
+ # else
+ .ep_info.pc = PLAT_NS_IMAGE_OFFSET,
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, 0),
+ .image_info.image_base = PLAT_NS_IMAGE_OFFSET,
+ .image_info.image_max_size = PLAT_NS_IMAGE_SIZE,
+ # endif /* PRELOADED_BL33_BASE */
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ }
+};
+
+REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs);
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_image_load.c b/plat/imx/imx8m/imx8mm/imx8mm_image_load.c
new file mode 100644
index 0000000..3a03069
--- /dev/null
+++ b/plat/imx/imx8m/imx8mm/imx8mm_image_load.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/bl_common.h>
+#include <common/desc_image_load.h>
+
+#include <platform_def.h>
+#include <plat/common/platform.h>
+
+void plat_flush_next_bl_params(void)
+{
+ flush_bl_params_desc();
+}
+
+bl_load_info_t *plat_get_bl_image_load_info(void)
+{
+ return get_bl_load_info_from_mem_params_desc();
+}
+
+bl_params_t *plat_get_next_bl_params(void)
+{
+ return get_next_bl_params_from_mem_params_desc();
+}
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_io_storage.c b/plat/imx/imx8m/imx8mm/imx8mm_io_storage.c
new file mode 100644
index 0000000..ff6687e
--- /dev/null
+++ b/plat/imx/imx8m/imx8mm/imx8mm_io_storage.c
@@ -0,0 +1,300 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <drivers/io/io_block.h>
+#include <drivers/io/io_driver.h>
+#include <drivers/io/io_fip.h>
+#include <drivers/io/io_driver.h>
+#include <drivers/io/io_memmap.h>
+#include <drivers/mmc.h>
+#include <lib/utils_def.h>
+#include <tbbr_img_def.h>
+#include <tools_share/firmware_image_package.h>
+
+#include <platform_def.h>
+
+static const io_dev_connector_t *fip_dev_con;
+static uintptr_t fip_dev_handle;
+
+#ifndef IMX8MM_FIP_MMAP
+static const io_dev_connector_t *mmc_dev_con;
+static uintptr_t mmc_dev_handle;
+
+static const io_block_spec_t mmc_fip_spec = {
+ .offset = IMX8MM_FIP_MMC_BASE,
+ .length = IMX8MM_FIP_SIZE
+};
+
+static const io_block_dev_spec_t mmc_dev_spec = {
+ /* It's used as temp buffer in block driver. */
+ .buffer = {
+ .offset = IMX8MM_FIP_BASE,
+ /* do we need a new value? */
+ .length = IMX8MM_FIP_SIZE
+ },
+ .ops = {
+ .read = mmc_read_blocks,
+ .write = mmc_write_blocks,
+ },
+ .block_size = MMC_BLOCK_SIZE,
+};
+
+static int open_mmc(const uintptr_t spec);
+
+#else
+static const io_dev_connector_t *memmap_dev_con;
+static uintptr_t memmap_dev_handle;
+
+static const io_block_spec_t fip_block_spec = {
+ .offset = IMX8MM_FIP_BASE,
+ .length = IMX8MM_FIP_SIZE
+};
+static int open_memmap(const uintptr_t spec);
+#endif
+
+static int open_fip(const uintptr_t spec);
+
+static const io_uuid_spec_t bl31_uuid_spec = {
+ .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
+};
+
+static const io_uuid_spec_t bl32_uuid_spec = {
+ .uuid = UUID_SECURE_PAYLOAD_BL32,
+};
+
+static const io_uuid_spec_t bl32_extra1_uuid_spec = {
+ .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1,
+};
+
+static const io_uuid_spec_t bl32_extra2_uuid_spec = {
+ .uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2,
+};
+
+static const io_uuid_spec_t bl33_uuid_spec = {
+ .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
+};
+
+#if TRUSTED_BOARD_BOOT
+static const io_uuid_spec_t tb_fw_cert_uuid_spec = {
+ .uuid = UUID_TRUSTED_BOOT_FW_CERT,
+};
+
+static const io_uuid_spec_t trusted_key_cert_uuid_spec = {
+ .uuid = UUID_TRUSTED_KEY_CERT,
+};
+
+static const io_uuid_spec_t soc_fw_key_cert_uuid_spec = {
+ .uuid = UUID_SOC_FW_KEY_CERT,
+};
+
+static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = {
+ .uuid = UUID_TRUSTED_OS_FW_KEY_CERT,
+};
+
+static const io_uuid_spec_t tos_fw_cert_uuid_spec = {
+ .uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT,
+};
+
+static const io_uuid_spec_t soc_fw_content_cert_uuid_spec = {
+ .uuid = UUID_SOC_FW_CONTENT_CERT,
+};
+
+static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = {
+ .uuid = UUID_NON_TRUSTED_FW_KEY_CERT,
+};
+
+static const io_uuid_spec_t nt_fw_cert_uuid_spec = {
+ .uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT,
+};
+#endif /* TRUSTED_BOARD_BOOT */
+
+struct plat_io_policy {
+ uintptr_t *dev_handle;
+ uintptr_t image_spec;
+ int (*check)(const uintptr_t spec);
+};
+
+static const struct plat_io_policy policies[] = {
+#ifndef IMX8MM_FIP_MMAP
+ [FIP_IMAGE_ID] = {
+ &mmc_dev_handle,
+ (uintptr_t)&mmc_fip_spec,
+ open_mmc
+ },
+#else
+ [FIP_IMAGE_ID] = {
+ &memmap_dev_handle,
+ (uintptr_t)&fip_block_spec,
+ open_memmap
+ },
+#endif
+ [BL31_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&bl31_uuid_spec,
+ open_fip
+ },
+ [BL32_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&bl32_uuid_spec,
+ open_fip
+ },
+ [BL32_EXTRA1_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&bl32_extra1_uuid_spec,
+ open_fip
+ },
+ [BL32_EXTRA2_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&bl32_extra2_uuid_spec,
+ open_fip
+ },
+ [BL33_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&bl33_uuid_spec,
+ open_fip
+ },
+#if TRUSTED_BOARD_BOOT
+ [TRUSTED_BOOT_FW_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&tb_fw_cert_uuid_spec,
+ open_fip
+ },
+ [SOC_FW_KEY_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&soc_fw_key_cert_uuid_spec,
+ open_fip
+ },
+ [TRUSTED_KEY_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&trusted_key_cert_uuid_spec,
+ open_fip
+ },
+ [TRUSTED_OS_FW_KEY_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&tos_fw_key_cert_uuid_spec,
+ open_fip
+ },
+ [NON_TRUSTED_FW_KEY_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&nt_fw_key_cert_uuid_spec,
+ open_fip
+ },
+ [SOC_FW_CONTENT_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&soc_fw_content_cert_uuid_spec,
+ open_fip
+ },
+ [TRUSTED_OS_FW_CONTENT_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&tos_fw_cert_uuid_spec,
+ open_fip
+ },
+ [NON_TRUSTED_FW_CONTENT_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&nt_fw_cert_uuid_spec,
+ open_fip
+ },
+#endif /* TRUSTED_BOARD_BOOT */
+};
+
+static int open_fip(const uintptr_t spec)
+{
+ int result;
+ uintptr_t local_image_handle;
+
+ /* See if a Firmware Image Package is available */
+ result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
+ if (result == 0) {
+ result = io_open(fip_dev_handle, spec, &local_image_handle);
+ if (result == 0) {
+ VERBOSE("Using FIP\n");
+ io_close(local_image_handle);
+ }
+ }
+ return result;
+}
+
+#ifndef IMX8MM_FIP_MMAP
+static int open_mmc(const uintptr_t spec)
+{
+ int result;
+ uintptr_t local_handle;
+
+ result = io_dev_init(mmc_dev_handle, (uintptr_t)NULL);
+ if (result == 0) {
+ result = io_open(mmc_dev_handle, spec, &local_handle);
+ if (result == 0) {
+ io_close(local_handle);
+ }
+ }
+ return result;
+}
+#else
+static int open_memmap(const uintptr_t spec)
+{
+ int result;
+ uintptr_t local_image_handle;
+
+ result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL);
+ if (result == 0) {
+ result = io_open(memmap_dev_handle, spec, &local_image_handle);
+ if (result == 0) {
+ VERBOSE("Using Memmap\n");
+ io_close(local_image_handle);
+ }
+ }
+ return result;
+}
+#endif
+
+int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
+ uintptr_t *image_spec)
+{
+ int result;
+ const struct plat_io_policy *policy;
+
+ assert(image_id < ARRAY_SIZE(policies));
+
+ policy = &policies[image_id];
+ result = policy->check(policy->image_spec);
+ assert(result == 0);
+
+ *image_spec = policy->image_spec;
+ *dev_handle = *policy->dev_handle;
+
+ return result;
+}
+
+void plat_imx8mm_io_setup(void)
+{
+ int result __unused;
+
+#ifndef IMX8MM_FIP_MMAP
+ result = register_io_dev_block(&mmc_dev_con);
+ assert(result == 0);
+
+ result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_dev_spec,
+ &mmc_dev_handle);
+ assert(result == 0);
+
+#else
+ result = register_io_dev_memmap(&memmap_dev_con);
+ assert(result == 0);
+
+ result = io_dev_open(memmap_dev_con, (uintptr_t)NULL,
+ &memmap_dev_handle);
+ assert(result == 0);
+#endif
+
+ result = register_io_dev_fip(&fip_dev_con);
+ assert(result == 0);
+
+ result = io_dev_open(fip_dev_con, (uintptr_t)NULL,
+ &fip_dev_handle);
+ assert(result == 0);
+}
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_psci.c b/plat/imx/imx8m/imx8mm/imx8mm_psci.c
index e558724..815d3a2 100644
--- a/plat/imx/imx8m/imx8mm/imx8mm_psci.c
+++ b/plat/imx/imx8m/imx8mm/imx8mm_psci.c
@@ -28,6 +28,7 @@
.pwr_domain_pwr_down_wfi = imx_pwr_domain_pwr_down_wfi,
.get_sys_suspend_power_state = imx_get_sys_suspend_power_state,
.system_reset = imx_system_reset,
+ .system_reset2 = imx_system_reset2,
.system_off = imx_system_off,
};
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_rotpk.S b/plat/imx/imx8m/imx8mm/imx8mm_rotpk.S
new file mode 100644
index 0000000..544ee8a
--- /dev/null
+++ b/plat/imx/imx8m/imx8mm/imx8mm_rotpk.S
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+ .global imx8mm_rotpk_hash
+ .global imx8mm_rotpk_hash_end
+imx8mm_rotpk_hash:
+ /* DER header */
+ .byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48
+ .byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20
+ /* SHA256 */
+ .incbin ROTPK_HASH
+imx8mm_rotpk_hash_end:
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_trusted_boot.c b/plat/imx/imx8m/imx8mm/imx8mm_trusted_boot.c
new file mode 100644
index 0000000..a4384d7
--- /dev/null
+++ b/plat/imx/imx8m/imx8mm/imx8mm_trusted_boot.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <plat/common/platform.h>
+
+extern char imx8mm_rotpk_hash[], imx8mm_rotpk_hash_end[];
+
+int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
+ unsigned int *flags)
+{
+ *key_ptr = imx8mm_rotpk_hash;
+ *key_len = imx8mm_rotpk_hash_end - imx8mm_rotpk_hash;
+ *flags = ROTPK_IS_HASH;
+
+ return 0;
+}
+
+int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr)
+{
+ *nv_ctr = 0;
+
+ return 0;
+}
+
+int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr)
+{
+ return 1;
+}
+
+int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
+{
+ return get_mbedtls_heap_helper(heap_addr, heap_size);
+}
diff --git a/plat/imx/imx8m/imx8mm/include/imx8mm_private.h b/plat/imx/imx8m/imx8mm/include/imx8mm_private.h
new file mode 100644
index 0000000..52d13f0
--- /dev/null
+++ b/plat/imx/imx8m/imx8mm/include/imx8mm_private.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef IMX8MM_PRIVATE_H
+#define IMX8MM_PRIVATE_H
+
+/*******************************************************************************
+ * Function and variable prototypes
+ ******************************************************************************/
+void plat_imx8mm_io_setup(void);
+
+#endif /* IMX8MM_PRIVATE_H */
diff --git a/plat/imx/imx8m/imx8mm/include/platform_def.h b/plat/imx/imx8m/imx8mm/include/platform_def.h
index 1041459..940d22b 100644
--- a/plat/imx/imx8m/imx8mm/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mm/include/platform_def.h
@@ -1,9 +1,11 @@
/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <common/tbbr/tbbr_img_def.h>
+
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
#define PLATFORM_LINKER_ARCH aarch64
@@ -34,11 +36,27 @@
#define PLAT_SDEI_NORMAL_PRI 0x20
#define PLAT_SDEI_SGI_PRIVATE U(9)
+#if defined(NEED_BL2)
+#define BL2_BASE U(0x920000)
+#define BL2_LIMIT U(0x940000)
+#define BL31_BASE U(0x900000)
+#define BL31_LIMIT U(0x920000)
+#define IMX8MM_FIP_BASE U(0x40310000)
+#define IMX8MM_FIP_SIZE U(0x000300000)
+#define IMX8MM_FIP_LIMIT U(FIP_BASE + FIP_SIZE)
+
+/* Define FIP image location on eMMC */
+#define IMX8MM_FIP_MMC_BASE U(0x100000)
+
+#define PLAT_IMX8MM_BOOT_MMC_BASE U(0x30B50000) /* SD */
+#else
#define BL31_BASE U(0x920000)
#define BL31_LIMIT U(0x940000)
+#endif
/* non-secure uboot base */
#define PLAT_NS_IMAGE_OFFSET U(0x40200000)
+#define PLAT_NS_IMAGE_SIZE U(0x00200000)
/* GICv3 base address */
#define PLAT_GICD_BASE U(0x38800000)
@@ -106,6 +124,8 @@
#define SRC_OTG1PHY_SCR U(0x20)
#define SRC_OTG2PHY_SCR U(0x24)
#define SRC_GPR1_OFFSET U(0x74)
+#define SRC_GPR10_OFFSET U(0x98)
+#define SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30)
#define SNVS_LPCR U(0x38)
#define SNVS_LPCR_SRTC_ENV BIT(0)
@@ -127,3 +147,7 @@
#define COUNTER_FREQUENCY 8000000 /* 8MHz */
#define IMX_WDOG_B_RESET
+
+#define MAX_IO_HANDLES 3U
+#define MAX_IO_DEVICES 2U
+#define MAX_IO_BLOCK_DEVICES 1U
diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk
index ac636fa..1863233 100644
--- a/plat/imx/imx8m/imx8mm/platform.mk
+++ b/plat/imx/imx8m/imx8mm/platform.mk
@@ -6,7 +6,9 @@
PLAT_INCLUDES := -Iplat/imx/common/include \
-Iplat/imx/imx8m/include \
- -Iplat/imx/imx8m/imx8mm/include
+ -Iplat/imx/imx8m/imx8mm/include \
+ -Idrivers/imx/usdhc \
+ -Iinclude/common/tbbr
# Include GICv3 driver files
include drivers/arm/gic/v3/gicv3.mk
@@ -39,6 +41,94 @@
drivers/delay_timer/generic_delay_timer.c \
${IMX_GIC_SOURCES}
+ifeq (${NEED_BL2},yes)
+BL2_SOURCES += common/desc_image_load.c \
+ plat/imx/common/imx8_helpers.S \
+ plat/imx/common/imx_uart_console.S \
+ plat/imx/imx8m/imx8mm/imx8mm_bl2_el3_setup.c \
+ plat/imx/imx8m/imx8mm/gpc.c \
+ plat/imx/imx8m/imx_aipstz.c \
+ plat/common/plat_psci_common.c \
+ lib/xlat_tables/aarch64/xlat_tables.c \
+ lib/xlat_tables/xlat_tables_common.c \
+ lib/cpus/aarch64/cortex_a53.S \
+ drivers/delay_timer/delay_timer.c \
+ drivers/delay_timer/generic_delay_timer.c \
+ ${PLAT_GIC_SOURCES} \
+ ${PLAT_DRAM_SOURCES} \
+ drivers/mmc/mmc.c \
+ drivers/io/io_block.c \
+ drivers/io/io_fip.c \
+ drivers/io/io_memmap.c \
+ drivers/io/io_storage.c \
+ drivers/imx/usdhc/imx_usdhc.c \
+ plat/imx/imx8m/imx8mm/imx8mm_bl2_mem_params_desc.c \
+ plat/imx/imx8m/imx8mm/imx8mm_io_storage.c \
+ plat/imx/imx8m/imx8mm/imx8mm_image_load.c \
+ lib/optee/optee_utils.c
+endif
+
+# Add the build options to pack BLx images and kernel device tree
+# in the FIP if the platform requires.
+ifneq ($(BL2),)
+RESET_TO_BL31 := 0
+$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert))
+endif
+ifneq ($(BL32_EXTRA1),)
+$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1))
+endif
+ifneq ($(BL32_EXTRA2),)
+$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2))
+endif
+ifneq ($(HW_CONFIG),)
+$(eval $(call TOOL_ADD_IMG,HW_CONFIG,--hw-config))
+endif
+
+ifeq (${NEED_BL2},yes)
+$(eval $(call add_define,NEED_BL2))
+LOAD_IMAGE_V2 := 1
+# Non-TF Boot ROM
+BL2_AT_EL3 := 1
+endif
+
+ifneq (${TRUSTED_BOARD_BOOT},0)
+
+include drivers/auth/mbedtls/mbedtls_crypto.mk
+include drivers/auth/mbedtls/mbedtls_x509.mk
+
+AUTH_SOURCES := drivers/auth/auth_mod.c \
+ drivers/auth/crypto_mod.c \
+ drivers/auth/img_parser_mod.c \
+ drivers/auth/tbbr/tbbr_cot_common.c \
+ drivers/auth/tbbr/tbbr_cot_bl2.c
+
+BL2_SOURCES += ${AUTH_SOURCES} \
+ plat/common/tbbr/plat_tbbr.c \
+ plat/imx/imx8m/imx8mm/imx8mm_trusted_boot.c \
+ plat/imx/imx8m/imx8mm/imx8mm_rotpk.S
+
+ROT_KEY = $(BUILD_PLAT)/rot_key.pem
+ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin
+
+$(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
+$(eval $(call MAKE_LIB_DIRS))
+
+$(BUILD_PLAT)/bl2/imx8mm_rotpk.o: $(ROTPK_HASH)
+
+certificates: $(ROT_KEY)
+
+$(ROT_KEY): | $(BUILD_PLAT)
+ @echo " OPENSSL $@"
+ @if [ ! -f $(ROT_KEY) ]; then \
+ openssl genrsa 2048 > $@ 2>/dev/null; \
+ fi
+
+$(ROTPK_HASH): $(ROT_KEY)
+ @echo " OPENSSL $@"
+ $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+ openssl dgst -sha256 -binary > $@ 2>/dev/null
+endif
+
USE_COHERENT_MEM := 1
RESET_TO_BL31 := 1
A53_DISABLE_NON_TEMPORAL_HINT := 0
diff --git a/plat/imx/imx8m/imx8mn/include/platform_def.h b/plat/imx/imx8m/imx8mn/include/platform_def.h
index 2444e66..9c46d8d 100644
--- a/plat/imx/imx8m/imx8mn/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mn/include/platform_def.h
@@ -34,6 +34,11 @@
#define PLAT_WAIT_RET_STATE U(1)
#define PLAT_STOP_OFF_STATE U(3)
+#define PLAT_PRI_BITS U(3)
+#define PLAT_SDEI_CRITICAL_PRI 0x10
+#define PLAT_SDEI_NORMAL_PRI 0x20
+#define PLAT_SDEI_SGI_PRIVATE U(9)
+
#define BL31_BASE U(0x960000)
#define BL31_LIMIT U(0x980000)
diff --git a/plat/imx/imx8m/imx8mn/platform.mk b/plat/imx/imx8m/imx8mn/platform.mk
index 8c4ad1c..2087089 100644
--- a/plat/imx/imx8m/imx8mn/platform.mk
+++ b/plat/imx/imx8m/imx8mn/platform.mk
@@ -31,6 +31,8 @@
plat/imx/common/imx_sip_handler.c \
plat/imx/common/imx_sip_svc.c \
plat/imx/common/imx_uart_console.S \
+ plat/imx/common/imx_ehf.c \
+ plat/imx/common/imx_sdei.c \
lib/cpus/aarch64/cortex_a53.S \
drivers/arm/tzc/tzc380.c \
drivers/delay_timer/delay_timer.c \
@@ -54,3 +56,6 @@
IMX_BOOT_UART_BASE ?= 0x30890000
$(eval $(call add_define,IMX_BOOT_UART_BASE))
+
+EL3_EXCEPTION_HANDLING := 1
+SDEI_SUPPORT := 1
diff --git a/plat/imx/imx8m/imx8mp/include/platform_def.h b/plat/imx/imx8m/imx8mp/include/platform_def.h
index 644adc7..832bed1 100644
--- a/plat/imx/imx8m/imx8mp/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mp/include/platform_def.h
@@ -37,6 +37,11 @@
#define BL31_BASE U(0x960000)
#define BL31_LIMIT U(0x980000)
+#define PLAT_PRI_BITS U(3)
+#define PLAT_SDEI_CRITICAL_PRI 0x10
+#define PLAT_SDEI_NORMAL_PRI 0x20
+#define PLAT_SDEI_SGI_PRIVATE U(9)
+
/* non-secure uboot base */
#define PLAT_NS_IMAGE_OFFSET U(0x40200000)
diff --git a/plat/imx/imx8m/imx8mp/platform.mk b/plat/imx/imx8m/imx8mp/platform.mk
index 1d11e3d..6be2f98 100644
--- a/plat/imx/imx8m/imx8mp/platform.mk
+++ b/plat/imx/imx8m/imx8mp/platform.mk
@@ -28,6 +28,8 @@
plat/imx/imx8m/imx8mp/imx8mp_psci.c \
plat/imx/imx8m/imx8mp/gpc.c \
plat/imx/common/imx8_topology.c \
+ plat/imx/common/imx_ehf.c \
+ plat/imx/common/imx_sdei.c \
plat/imx/common/imx_sip_handler.c \
plat/imx/common/imx_sip_svc.c \
plat/imx/common/imx_uart_console.S \
@@ -54,3 +56,6 @@
IMX_BOOT_UART_BASE ?= 0x30890000
$(eval $(call add_define,IMX_BOOT_UART_BASE))
+
+EL3_EXCEPTION_HANDLING := 1
+SDEI_SUPPORT := 1
diff --git a/plat/imx/imx8m/imx8mq/imx8mq_psci.c b/plat/imx/imx8m/imx8mq/imx8mq_psci.c
index 04e191f..662017d 100644
--- a/plat/imx/imx8m/imx8mq/imx8mq_psci.c
+++ b/plat/imx/imx8m/imx8mq/imx8mq_psci.c
@@ -117,6 +117,7 @@
.pwr_domain_pwr_down_wfi = imx_pwr_domain_pwr_down_wfi,
.get_sys_suspend_power_state = imx_get_sys_suspend_power_state,
.system_reset = imx_system_reset,
+ .system_reset2 = imx_system_reset2,
.system_off = imx_system_off,
};
diff --git a/plat/imx/imx8m/imx8mq/include/platform_def.h b/plat/imx/imx8m/imx8mq/include/platform_def.h
index 9db3a13..6d6a865 100644
--- a/plat/imx/imx8m/imx8mq/include/platform_def.h
+++ b/plat/imx/imx8m/imx8mq/include/platform_def.h
@@ -103,6 +103,8 @@
#define SRC_OTG1PHY_SCR U(0x20)
#define SRC_OTG2PHY_SCR U(0x24)
#define SRC_GPR1_OFFSET U(0x74)
+#define SRC_GPR10_OFFSET U(0x98)
+#define SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30)
#define SNVS_LPCR U(0x38)
#define SNVS_LPCR_SRTC_ENV BIT(0)
diff --git a/plat/imx/imx8m/include/gpc.h b/plat/imx/imx8m/include/gpc.h
index 075da91..29b8ecf 100644
--- a/plat/imx/imx8m/include/gpc.h
+++ b/plat/imx/imx8m/include/gpc.h
@@ -32,7 +32,7 @@
.pwr_req = name##_PWR_REQ, \
.pgc_offset = name##_PGC, \
.need_sync = false, \
- .always_on = true, \
+ .always_on = (on), \
}
#define IMX_MIX_DOMAIN(name, on) \
@@ -42,7 +42,7 @@
.adb400_sync = name##_ADB400_SYNC, \
.adb400_ack = name##_ADB400_ACK, \
.need_sync = true, \
- .always_on = true, \
+ .always_on = (on), \
}
struct imx_pwr_domain {
diff --git a/plat/imx/imx8m/include/imx8m_psci.h b/plat/imx/imx8m/include/imx8m_psci.h
index c33d25e..7d14d11 100644
--- a/plat/imx/imx8m/include/imx8m_psci.h
+++ b/plat/imx/imx8m/include/imx8m_psci.h
@@ -19,5 +19,6 @@
void imx_domain_suspend(const psci_power_state_t *target_state);
void imx_domain_suspend_finish(const psci_power_state_t *target_state);
void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state);
+int imx_system_reset2(int is_vendor, int reset_type, u_register_t cookie);
#endif /* IMX8M_PSCI_H */
diff --git a/plat/intel/soc/agilex/bl2_plat_setup.c b/plat/intel/soc/agilex/bl2_plat_setup.c
index f002947..b6b3e16 100644
--- a/plat/intel/soc/agilex/bl2_plat_setup.c
+++ b/plat/intel/soc/agilex/bl2_plat_setup.c
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2021, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -29,6 +29,7 @@
#include "socfpga_system_manager.h"
#include "wdt/watchdog.h"
+static struct mmc_device_info mmc_info;
const mmap_region_t agilex_plat_mmap[] = {
MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
@@ -87,7 +88,6 @@
void bl2_el3_plat_arch_setup(void)
{
- struct mmc_device_info info;
const mmap_region_t bl_regions[] = {
MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE,
MT_MEMORY | MT_RW | MT_SECURE),
@@ -110,12 +110,12 @@
dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk());
- info.mmc_dev_type = MMC_IS_SD;
- info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
+ mmc_info.mmc_dev_type = MMC_IS_SD;
+ mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
switch (boot_source) {
case BOOT_SOURCE_SDMMC:
- dw_mmc_init(¶ms, &info);
+ dw_mmc_init(¶ms, &mmc_info);
socfpga_io_setup(boot_source);
break;
diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c
index 721a690..ecf1f01 100644
--- a/plat/intel/soc/stratix10/bl2_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl2_plat_setup.c
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2021, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,6 +27,7 @@
#include "s10_pinmux.h"
#include "wdt/watchdog.h"
+static struct mmc_device_info mmc_info;
const mmap_region_t plat_stratix10_mmap[] = {
MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
@@ -83,7 +84,6 @@
void bl2_el3_plat_arch_setup(void)
{
- struct mmc_device_info info;
const mmap_region_t bl_regions[] = {
MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE,
MT_MEMORY | MT_RW | MT_SECURE),
@@ -106,12 +106,12 @@
dw_mmc_params_t params = EMMC_INIT_PARAMS(0x100000, get_mmc_clk());
- info.mmc_dev_type = MMC_IS_SD;
- info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
+ mmc_info.mmc_dev_type = MMC_IS_SD;
+ mmc_info.ocr_voltage = OCR_3_3_3_4 | OCR_3_2_3_3;
switch (boot_source) {
case BOOT_SOURCE_SDMMC:
- dw_mmc_init(¶ms, &info);
+ dw_mmc_init(¶ms, &mmc_info);
socfpga_io_setup(boot_source);
break;
diff --git a/plat/marvell/armada/a3k/a3700/board/pm_src.c b/plat/marvell/armada/a3k/a3700/board/pm_src.c
index d6eca5d..247f73b 100644
--- a/plat/marvell/armada/a3k/a3700/board/pm_src.c
+++ b/plat/marvell/armada/a3k/a3700/board/pm_src.c
@@ -8,7 +8,7 @@
#include <a3700_pm.h>
#include <plat_marvell.h>
-/* This struct provides the PM wake up src configuration */
+/* This struct provides the PM wake up src configuration for A3720 Development Board */
static struct pm_wake_up_src_config wake_up_src_cfg = {
.wake_up_src_num = 3,
.wake_up_src[0] = {
diff --git a/plat/marvell/armada/a3k/common/a3700_common.mk b/plat/marvell/armada/a3k/common/a3700_common.mk
index 8775e89..0a89742 100644
--- a/plat/marvell/armada/a3k/common/a3700_common.mk
+++ b/plat/marvell/armada/a3k/common/a3700_common.mk
@@ -38,13 +38,12 @@
-I$/drivers/arm/gic/common/
PLAT_BL_COMMON_SOURCES := $(PLAT_COMMON_BASE)/aarch64/a3700_common.c \
+ $(PLAT_COMMON_BASE)/aarch64/a3700_clock.S \
$(MARVELL_DRV_BASE)/uart/a3700_console.S
BL1_SOURCES += $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \
lib/cpus/aarch64/cortex_a53.S
-BL31_PORTING_SOURCES := $(PLAT_FAMILY_BASE)/$(PLAT)/board/pm_src.c
-
MARVELL_DRV := $(MARVELL_DRV_BASE)/comphy/phy-comphy-3700.c
BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
@@ -61,7 +60,6 @@
$(MARVELL_COMMON_BASE)/marvell_gicv3.c \
$(MARVELL_GIC_SOURCES) \
drivers/arm/cci/cci.c \
- $(BL31_PORTING_SOURCES) \
$(PLAT_COMMON_BASE)/a3700_sip_svc.c \
$(MARVELL_DRV)
@@ -69,47 +67,52 @@
BL31_SOURCES += $(PLAT_COMMON_BASE)/cm3_system_reset.c
endif
+ifeq ($(A3720_DB_PM_WAKEUP_SRC),1)
+BL31_SOURCES += $(PLAT_FAMILY_BASE)/$(PLAT)/board/pm_src.c
+endif
+
ifdef WTP
$(if $(wildcard $(value WTP)/*),,$(error "'WTP=$(value WTP)' was specified, but '$(value WTP)' directory does not exist"))
-$(if $(shell test -s "$(value WTP)/branch.txt" || git -C $(value WTP) rev-parse --show-cdup 2>&1),$(error "'WTP=$(value WTP)' was specified, but '$(value WTP)' does not contain valid Marvell a3700_utils release tarball nor git repository"))
+$(if $(shell git -C $(value WTP) rev-parse --show-cdup 2>&1),$(error "'WTP=$(value WTP)' was specified, but '$(value WTP)' does not contain valid A3700-utils-marvell git repository"))
-DOIMAGEPATH := $(WTP)
-DOIMAGETOOL := $(DOIMAGEPATH)/wtptp/src/TBB_Linux/release/TBB_linux
+TBB := $(WTP)/wtptp/src/TBB_Linux/release/TBB_linux
BUILD_UART := uart-images
UART_IMAGE := $(BUILD_UART).tgz.bin
ifeq ($(MARVELL_SECURE_BOOT),1)
-DOIMAGE_CFG := $(BUILD_PLAT)/atf-tim.txt
-DOIMAGEUART_CFG := $(BUILD_PLAT)/$(BUILD_UART)/atf-tim.txt
-IMAGESPATH := $(DOIMAGEPATH)/tim/trusted
-TIMNCFG := $(BUILD_PLAT)/atf-timN.txt
-TIMNUARTCFG := $(BUILD_PLAT)/$(BUILD_UART)/atf-timN.txt
-TIMNSIG := $(IMAGESPATH)/timnsign.txt
-TIM2IMGARGS := -i $(DOIMAGE_CFG) -n $(TIMNCFG)
-TIMN_IMAGE := $$(grep "Image Filename:" -m 1 $(TIMNCFG) | cut -c 17-)
+TIM_CFG := $(BUILD_PLAT)/atf-tim.txt
+TIM_UART_CFG := $(BUILD_PLAT)/$(BUILD_UART)/atf-tim.txt
+IMAGESPATH := $(WTP)/tim/trusted
+TIMN_CFG := $(BUILD_PLAT)/atf-timN.txt
+TIMN_UART_CFG := $(BUILD_PLAT)/$(BUILD_UART)/atf-timN.txt
+TIMN_SIG := $(IMAGESPATH)/timnsign.txt
+TIM2IMGARGS := -i $(TIM_CFG) -n $(TIMN_CFG)
+TIMN_UART_IMAGE := $$(grep "Image Filename:" -m 1 $(TIMN_UART_CFG) | cut -c 17-)
else #MARVELL_SECURE_BOOT
-DOIMAGE_CFG := $(BUILD_PLAT)/atf-ntim.txt
-DOIMAGEUART_CFG := $(BUILD_PLAT)/$(BUILD_UART)/atf-ntim.txt
-IMAGESPATH := $(DOIMAGEPATH)/tim/untrusted
-TIM2IMGARGS := -i $(DOIMAGE_CFG)
+TIM_CFG := $(BUILD_PLAT)/atf-ntim.txt
+TIM_UART_CFG := $(BUILD_PLAT)/$(BUILD_UART)/atf-ntim.txt
+IMAGESPATH := $(WTP)/tim/untrusted
+TIM2IMGARGS := -i $(TIM_CFG)
endif #MARVELL_SECURE_BOOT
-TIMBUILD := $(DOIMAGEPATH)/script/buildtim.sh
-TIM2IMG := $(DOIMAGEPATH)/script/tim2img.pl
-TIMDDRTOOL := $(DOIMAGEPATH)/tim/ddr/ddr_tool
+TIM_UART_IMAGE := $$(grep "Image Filename:" -m 1 $(TIM_UART_CFG) | cut -c 17-)
+
+TIMBUILD := $(WTP)/script/buildtim.sh
+TIM2IMG := $(WTP)/script/tim2img.pl
+TIMDDRTOOL := $(WTP)/tim/ddr/ddr_tool
$(TIMBUILD): $(TIMDDRTOOL)
# WTMI_IMG is used to specify the customized RTOS image running over
# Service CPU (CM3 processor). By the default, it points to a
# baremetal binary of fuse programming in A3700_utils.
-WTMI_IMG := $(DOIMAGEPATH)/wtmi/fuse/build/fuse.bin
+WTMI_IMG := $(WTP)/wtmi/fuse/build/fuse.bin
# WTMI_MULTI_IMG is composed of CM3 RTOS image (WTMI_IMG)
# and sys-init image.
-WTMI_MULTI_IMG := $(DOIMAGEPATH)/wtmi/build/wtmi.bin
+WTMI_MULTI_IMG := $(WTP)/wtmi/build/wtmi.bin
WTMI_ENC_IMG := wtmi-enc.bin
@@ -122,16 +125,21 @@
BOOTDEV ?= SPINOR
PARTNUM ?= 0
-TIM_IMAGE := $$(grep "Image Filename:" -m 1 $(DOIMAGE_CFG) | cut -c 17-)
-TIMBLDARGS := $(MARVELL_SECURE_BOOT) $(BOOTDEV) $(IMAGESPATH) $(DOIMAGEPATH) $(CLOCKSPRESET) \
- $(DDR_TOPOLOGY) $(PARTNUM) $(DEBUG) $(DOIMAGE_CFG) $(TIMNCFG) $(TIMNSIG) 1
-TIMBLDUARTARGS := $(MARVELL_SECURE_BOOT) UART $(IMAGESPATH) $(DOIMAGEPATH) $(CLOCKSPRESET) \
- $(DDR_TOPOLOGY) 0 0 $(DOIMAGEUART_CFG) $(TIMNUARTCFG) $(TIMNSIG) 0
+TIMBLDARGS := $(MARVELL_SECURE_BOOT) $(BOOTDEV) $(IMAGESPATH) $(WTP) $(CLOCKSPRESET) \
+ $(DDR_TOPOLOGY) $(PARTNUM) $(DEBUG) $(TIM_CFG) $(TIMN_CFG) $(TIMN_SIG) 1
+TIMBLDUARTARGS := $(MARVELL_SECURE_BOOT) UART $(IMAGESPATH) $(WTP) $(CLOCKSPRESET) \
+ $(DDR_TOPOLOGY) 0 0 $(TIM_UART_CFG) $(TIMN_UART_CFG) $(TIMN_SIG) 0
+
+UART_IMAGES := $(BUILD_UART)/$(TIM_UART_IMAGE)
+ifeq ($(MARVELL_SECURE_BOOT),1)
+UART_IMAGES += $(BUILD_UART)/$(TIMN_UART_IMAGE)
+endif
+UART_IMAGES += $(BUILD_UART)/wtmi_h.bin $(BUILD_UART)/boot-image_h.bin
CRYPTOPP_LIBDIR ?= $(CRYPTOPP_PATH)
CRYPTOPP_INCDIR ?= $(CRYPTOPP_PATH)
-$(DOIMAGETOOL): FORCE
+$(TBB): FORCE
$(if $(CRYPTOPP_LIBDIR),,$(error "Platform '$(PLAT)' for WTP image tool requires CRYPTOPP_PATH or CRYPTOPP_LIBDIR. Please set CRYPTOPP_PATH or CRYPTOPP_LIBDIR to point to the right directory"))
$(if $(CRYPTOPP_INCDIR),,$(error "Platform '$(PLAT)' for WTP image tool requires CRYPTOPP_PATH or CRYPTOPP_INCDIR. Please set CRYPTOPP_PATH or CRYPTOPP_INCDIR to point to the right directory"))
$(if $(wildcard $(CRYPTOPP_LIBDIR)/*),,$(error "Either 'CRYPTOPP_PATH' or 'CRYPTOPP_LIB' was set to '$(CRYPTOPP_LIBDIR)', but '$(CRYPTOPP_LIBDIR)' does not exist"))
@@ -139,10 +147,10 @@
ifdef CRYPTOPP_PATH
$(Q)$(MAKE) --no-print-directory -C $(CRYPTOPP_PATH) -f GNUmakefile
endif
- $(Q)$(MAKE) --no-print-directory -C $(DOIMAGEPATH)/wtptp/src/TBB_Linux -f TBB_linux.mak LIBDIR=$(CRYPTOPP_LIBDIR) INCDIR=$(CRYPTOPP_INCDIR)
+ $(Q)$(MAKE) --no-print-directory -C $(WTP)/wtptp/src/TBB_Linux -f TBB_linux.mak LIBDIR=$(CRYPTOPP_LIBDIR) INCDIR=$(CRYPTOPP_INCDIR)
$(WTMI_MULTI_IMG): FORCE
- $(Q)$(MAKE) --no-print-directory -C $(DOIMAGEPATH) WTMI_IMG=$(WTMI_IMG) DDR_TOPOLOGY=$(DDR_TOPOLOGY) CLOCKSPRESET=$(CLOCKSPRESET) WTMI
+ $(Q)$(MAKE) --no-print-directory -C $(WTP) WTMI_IMG=$(WTMI_IMG) DDR_TOPOLOGY=$(DDR_TOPOLOGY) CLOCKSPRESET=$(CLOCKSPRESET) WTMI
$(BUILD_PLAT)/wtmi.bin: $(WTMI_MULTI_IMG)
$(Q)cp -a $(WTMI_MULTI_IMG) $(BUILD_PLAT)/wtmi.bin
@@ -150,40 +158,40 @@
$(TIMDDRTOOL): FORCE
$(if $(value MV_DDR_PATH),,$(error "Platform '${PLAT}' for ddr tool requires MV_DDR_PATH. Please set MV_DDR_PATH to point to the right directory"))
$(if $(wildcard $(value MV_DDR_PATH)/*),,$(error "'MV_DDR_PATH=$(value MV_DDR_PATH)' was specified, but '$(value MV_DDR_PATH)' directory does not exist"))
- $(if $(shell test -s "$(value MV_DDR_PATH)/branch.txt" || git -C $(value MV_DDR_PATH) rev-parse --show-cdup 2>&1),$(error "'MV_DDR_PATH=$(value MV_DDR_PATH)' was specified, but '$(value MV_DDR_PATH)' does not contain valid Marvell mv_ddr release tarball nor git repository"))
- $(Q)$(MAKE) --no-print-directory -C $(DOIMAGEPATH) MV_DDR_PATH=$(MV_DDR_PATH) DDR_TOPOLOGY=$(DDR_TOPOLOGY) mv_ddr
+ $(if $(shell git -C $(value MV_DDR_PATH) rev-parse --show-cdup 2>&1),$(error "'MV_DDR_PATH=$(value MV_DDR_PATH)' was specified, but '$(value MV_DDR_PATH)' does not contain valid mv-ddr-marvell git repository"))
+ $(Q)$(MAKE) --no-print-directory -C $(WTP) MV_DDR_PATH=$(MV_DDR_PATH) DDR_TOPOLOGY=$(DDR_TOPOLOGY) mv_ddr
-$(BUILD_PLAT)/$(UART_IMAGE): $(BUILD_PLAT)/$(BOOT_IMAGE) $(BUILD_PLAT)/wtmi.bin $(DOIMAGETOOL) $(TIMBUILD) $(TIMDDRTOOL)
+$(BUILD_PLAT)/$(UART_IMAGE): $(BUILD_PLAT)/$(BOOT_IMAGE) $(BUILD_PLAT)/wtmi.bin $(TBB) $(TIMBUILD) $(TIMDDRTOOL)
@$(ECHO_BLANK_LINE)
@echo "Building uart images"
$(Q)mkdir -p $(BUILD_PLAT)/$(BUILD_UART)
$(Q)cp -a $(BUILD_PLAT)/wtmi.bin $(BUILD_PLAT)/$(BUILD_UART)/wtmi.bin
$(Q)cp -a $(BUILD_PLAT)/$(BOOT_IMAGE) $(BUILD_PLAT)/$(BUILD_UART)/$(BOOT_IMAGE)
$(Q)cd $(BUILD_PLAT)/$(BUILD_UART) && $(TIMBUILD) $(TIMBLDUARTARGS)
- $(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(DOIMAGEUART_CFG)
- $(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(DOIMAGEUART_CFG)
+ $(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(TIM_UART_CFG)
+ $(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(TIM_UART_CFG)
ifeq ($(MARVELL_SECURE_BOOT),1)
- $(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(TIMNUARTCFG)
- $(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(TIMNUARTCFG)
+ $(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(TIMN_UART_CFG)
+ $(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(TIMN_UART_CFG)
endif
- $(Q)cd $(BUILD_PLAT)/$(BUILD_UART) && $(DOIMAGETOOL) -r $(DOIMAGEUART_CFG) -v -D
+ $(Q)cd $(BUILD_PLAT)/$(BUILD_UART) && $(TBB) -r $(TIM_UART_CFG) -v -D
ifeq ($(MARVELL_SECURE_BOOT),1)
- $(Q)cd $(BUILD_PLAT)/$(BUILD_UART) && $(DOIMAGETOOL) -r $(TIMNUARTCFG)
+ $(Q)cd $(BUILD_PLAT)/$(BUILD_UART) && $(TBB) -r $(TIMN_UART_CFG)
endif
- $(Q)tar czf $(BUILD_PLAT)/$(UART_IMAGE) -C $(BUILD_PLAT) $(BUILD_UART)/$(TIM_IMAGE) $(BUILD_UART)/wtmi_h.bin $(BUILD_UART)/boot-image_h.bin
+ $(Q)tar czf $(BUILD_PLAT)/$(UART_IMAGE) -C $(BUILD_PLAT) $(UART_IMAGES)
@$(ECHO_BLANK_LINE)
@echo "Built $@ successfully"
@$(ECHO_BLANK_LINE)
-$(BUILD_PLAT)/$(FLASH_IMAGE): $(BUILD_PLAT)/$(BOOT_IMAGE) $(BUILD_PLAT)/wtmi.bin $(DOIMAGETOOL) $(TIMBUILD) $(TIMDDRTOOL) $(TIM2IMG)
+$(BUILD_PLAT)/$(FLASH_IMAGE): $(BUILD_PLAT)/$(BOOT_IMAGE) $(BUILD_PLAT)/wtmi.bin $(TBB) $(TIMBUILD) $(TIMDDRTOOL) $(TIM2IMG)
@$(ECHO_BLANK_LINE)
@echo "Building flash image"
$(Q)cd $(BUILD_PLAT) && $(TIMBUILD) $(TIMBLDARGS)
- $(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(DOIMAGE_CFG)
- $(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(DOIMAGE_CFG)
+ $(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(TIM_CFG)
+ $(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(TIM_CFG)
ifeq ($(MARVELL_SECURE_BOOT),1)
- $(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(TIMNCFG)
- $(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(TIMNCFG)
+ $(Q)sed -i 's|WTMI_IMG|wtmi.bin|1' $(TIMN_CFG)
+ $(Q)sed -i 's|BOOT_IMAGE|$(BOOT_IMAGE)|1' $(TIMN_CFG)
@$(ECHO_BLANK_LINE)
@echo "=======================================================";
@echo " Secure boot. Encrypting wtmi and boot-image";
@@ -201,11 +209,11 @@
-K `cat $(IMAGESPATH)/aes-256.txt` -nosalt \
-iv `cat $(IMAGESPATH)/iv.txt` -p
endif
- $(Q)cd $(BUILD_PLAT) && $(DOIMAGETOOL) -r $(DOIMAGE_CFG) -v -D
+ $(Q)cd $(BUILD_PLAT) && $(TBB) -r $(TIM_CFG) -v -D
ifeq ($(MARVELL_SECURE_BOOT),1)
- $(Q)cd $(BUILD_PLAT) && $(DOIMAGETOOL) -r $(TIMNCFG)
- $(Q)sed -i 's|wtmi.bin|$(WTMI_ENC_IMG)|1' $(TIMNCFG)
- $(Q)sed -i 's|$(BOOT_IMAGE)|$(BOOT_ENC_IMAGE)|1' $(TIMNCFG)
+ $(Q)cd $(BUILD_PLAT) && $(TBB) -r $(TIMN_CFG)
+ $(Q)sed -i 's|wtmi.bin|$(WTMI_ENC_IMG)|1' $(TIMN_CFG)
+ $(Q)sed -i 's|$(BOOT_IMAGE)|$(BOOT_ENC_IMAGE)|1' $(TIMN_CFG)
endif
$(Q)cd $(BUILD_PLAT) && $(TIM2IMG) $(TIM2IMGARGS) -o $(BUILD_PLAT)/$(FLASH_IMAGE)
@$(ECHO_BLANK_LINE)
@@ -216,8 +224,8 @@
.PHONY: mrvl_clean
mrvl_clean:
- -$(Q)$(MAKE) --no-print-directory -C $(DOIMAGEPATH) MV_DDR_PATH=$(MV_DDR_PATH) clean
- -$(Q)$(MAKE) --no-print-directory -C $(DOIMAGEPATH)/wtptp/src/TBB_Linux -f TBB_linux.mak clean
+ -$(Q)$(MAKE) --no-print-directory -C $(WTP) MV_DDR_PATH=$(MV_DDR_PATH) clean
+ -$(Q)$(MAKE) --no-print-directory -C $(WTP)/wtptp/src/TBB_Linux -f TBB_linux.mak clean
ifdef CRYPTOPP_PATH
-$(Q)$(MAKE) --no-print-directory -C $(CRYPTOPP_PATH) -f GNUmakefile clean
endif
diff --git a/plat/marvell/armada/a3k/common/a3700_ea.c b/plat/marvell/armada/a3k/common/a3700_ea.c
index dd46beb..3a4f720 100644
--- a/plat/marvell/armada/a3k/common/a3700_ea.c
+++ b/plat/marvell/armada/a3k/common/a3700_ea.c
@@ -7,17 +7,15 @@
#include <common/bl_common.h>
#include <common/debug.h>
#include <arch_helpers.h>
+#include <plat/common/platform.h>
#define ADVK_SERROR_SYNDROME 0xbf000002
void plat_ea_handler(unsigned int ea_reason, uint64_t syndrome, void *cookie,
void *handle, uint64_t flags)
{
- if (syndrome != ADVK_SERROR_SYNDROME) {
- ERROR("Unhandled External Abort received on 0x%lx at EL3!\n",
- read_mpidr_el1());
- ERROR(" exception reason=%u syndrome=0x%llx\n", ea_reason,
- syndrome);
- panic();
- }
+ if (syndrome == ADVK_SERROR_SYNDROME)
+ return;
+
+ plat_default_ea_handler(ea_reason, syndrome, cookie, handle, flags);
}
diff --git a/plat/marvell/armada/a3k/common/aarch64/a3700_clock.S b/plat/marvell/armada/a3k/common/aarch64/a3700_clock.S
new file mode 100644
index 0000000..f79516f
--- /dev/null
+++ b/plat/marvell/armada/a3k/common/aarch64/a3700_clock.S
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <asm_macros.S>
+#include <platform_def.h>
+
+/*
+ * Below address in used only for reading, therefore no problem with concurrent
+ * Linux access.
+ */
+#define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8)
+ #define MVEBU_XTAL_MODE_MASK BIT(9)
+
+ /* -----------------------------------------------------
+ * uint32_t get_ref_clk (void);
+ *
+ * returns reference clock in MHz (25 or 40)
+ * -----------------------------------------------------
+ */
+.globl get_ref_clk
+func get_ref_clk
+ mov_imm x0, MVEBU_TEST_PIN_LATCH_N
+ ldr w0, [x0]
+ tst w0, #MVEBU_XTAL_MODE_MASK
+ bne 40
+ mov w0, #25
+ ret
+40:
+ mov w0, #40
+ ret
+endfunc get_ref_clk
diff --git a/plat/marvell/armada/a3k/common/include/platform_def.h b/plat/marvell/armada/a3k/common/include/platform_def.h
index 057ee2e..f19d96b 100644
--- a/plat/marvell/armada/a3k/common/include/platform_def.h
+++ b/plat/marvell/armada/a3k/common/include/platform_def.h
@@ -163,14 +163,7 @@
/*
* PL011 related constants
*/
-#define PLAT_MARVELL_BOOT_UART_BASE (MVEBU_REGS_BASE + 0x12000)
-#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 25804800
-
-#define PLAT_MARVELL_CRASH_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
-#define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
-
-#define PLAT_MARVELL_BL31_RUN_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
-#define PLAT_MARVELL_BL31_RUN_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
+#define PLAT_MARVELL_UART_BASE (MVEBU_REGS_BASE + 0x12000)
/* Required platform porting definitions */
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
diff --git a/plat/marvell/armada/a3k/common/io_addr_dec.c b/plat/marvell/armada/a3k/common/io_addr_dec.c
index b27633c..fea7f81 100644
--- a/plat/marvell/armada/a3k/common/io_addr_dec.c
+++ b/plat/marvell/armada/a3k/common/io_addr_dec.c
@@ -67,17 +67,14 @@
mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base,
win_id, dec_win->win_offset), ctrl);
- INFO("set_io_addr_dec %d result: ctrl(0x%x) base(0x%x)",
+ INFO("set_io_addr_dec %d result: ctrl(0x%x) base(0x%x) remap(0x%x)\n",
win_id, mmio_read_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base,
win_id, dec_win->win_offset)),
mmio_read_32(MVEBU_DEC_WIN_BASE_REG(dec_win->dec_reg_base,
- win_id, dec_win->win_offset)));
- if (win_id < dec_win->max_remap)
- INFO(" remap(%x)\n",
- mmio_read_32(MVEBU_DEC_WIN_REMAP_REG(dec_win->dec_reg_base,
- win_id, dec_win->win_offset)));
- else
- INFO("\n");
+ win_id, dec_win->win_offset)),
+ (win_id < dec_win->max_remap) ?
+ mmio_read_32(MVEBU_DEC_WIN_REMAP_REG(dec_win->dec_reg_base,
+ win_id, dec_win->win_offset)) : 0);
}
/* Set io decode window */
@@ -167,12 +164,11 @@
ERROR("Failed to set IO address decode\n");
return -1;
}
- INFO("Set IO decode window successfully, base(0x%x)",
- io_dec_win->dec_reg_base);
- INFO(" win_attr(%x) max_dram_win(%d) max_remap(%d)",
+ INFO("Set IO decode window successfully, base(0x%x)"
+ " win_attr(%x) max_dram_win(%d) max_remap(%d)"
+ " win_offset(%d)\n", io_dec_win->dec_reg_base,
io_dec_win->win_attr, io_dec_win->max_dram_win,
- io_dec_win->max_remap);
- INFO(" win_offset(%d)\n", io_dec_win->win_offset);
+ io_dec_win->max_remap, io_dec_win->win_offset);
}
return 0;
diff --git a/plat/marvell/armada/a3k/common/plat_pm.c b/plat/marvell/armada/a3k/common/plat_pm.c
index 2bae37e..e2d15ab 100644
--- a/plat/marvell/armada/a3k/common/plat_pm.c
+++ b/plat/marvell/armada/a3k/common/plat_pm.c
@@ -590,6 +590,13 @@
return NULL;
}
+#pragma weak mv_wake_up_src_config_get
+struct pm_wake_up_src_config *mv_wake_up_src_config_get(void)
+{
+ static struct pm_wake_up_src_config wake_up_src_cfg = {};
+ return &wake_up_src_cfg;
+}
+
static void a3700_set_wake_up_source(void)
{
struct pm_wake_up_src_config *wake_up_src;
diff --git a/plat/marvell/armada/a8k/a80x0/board/dram_port.c b/plat/marvell/armada/a8k/a80x0/board/dram_port.c
index 381c871..47bc0a8 100644
--- a/plat/marvell/armada/a8k/a80x0/board/dram_port.c
+++ b/plat/marvell/armada/a8k/a80x0/board/dram_port.c
@@ -138,7 +138,7 @@
i2c_init((void *)MVEBU_CP0_I2C_BASE);
/* select SPD memory page 0 to access DRAM configuration */
- i2c_write(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 1);
+ i2c_write(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 0);
/* read data from spd */
i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes,
diff --git a/plat/marvell/armada/a8k/a80x0_mcbin/board/dram_port.c b/plat/marvell/armada/a8k/a80x0_mcbin/board/dram_port.c
index 50a68b3..85c931c 100644
--- a/plat/marvell/armada/a8k/a80x0_mcbin/board/dram_port.c
+++ b/plat/marvell/armada/a8k/a80x0_mcbin/board/dram_port.c
@@ -123,7 +123,7 @@
/* initialize the i2c */
i2c_init((void *)MVEBU_CP0_I2C_BASE);
/* select SPD memory page 0 to access DRAM configuration */
- i2c_write(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 1);
+ i2c_write(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 0);
/* read data from spd */
i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes,
sizeof(tm->spd_data.all_bytes));
diff --git a/plat/marvell/armada/a8k/a80x0_puzzle/board/dram_port.c b/plat/marvell/armada/a8k/a80x0_puzzle/board/dram_port.c
index 3879c98..1d8e9d2 100644
--- a/plat/marvell/armada/a8k/a80x0_puzzle/board/dram_port.c
+++ b/plat/marvell/armada/a8k/a80x0_puzzle/board/dram_port.c
@@ -132,7 +132,7 @@
/* initialize the MVEBU_AP_I2C_BASE I2C bus */
i2c_init((void *)MVEBU_AP_I2C_BASE);
/* select SPD memory page 0 to access DRAM configuration */
- i2c_write(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 1);
+ i2c_write(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 0);
/* read data from spd */
i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes,
sizeof(tm->spd_data.all_bytes));
diff --git a/plat/marvell/armada/a8k/a80x0_puzzle/board/system_power.c b/plat/marvell/armada/a8k/a80x0_puzzle/board/system_power.c
index 5147dd5..eb00874 100644
--- a/plat/marvell/armada/a8k/a80x0_puzzle/board/system_power.c
+++ b/plat/marvell/armada/a8k/a80x0_puzzle/board/system_power.c
@@ -41,8 +41,8 @@
len = sizeof(system_off_now);
system_off_now[len - 1] = add_xor_checksum(system_off_now, len);
- console_16550_register(PLAT_MARVELL_BOOT_UART_BASE + 0x100,
- PLAT_MARVELL_BOOT_UART_CLK_IN_HZ, 115200, &console);
+ console_16550_register(PLAT_MARVELL_UART_BASE + 0x100,
+ PLAT_MARVELL_UART_CLK_IN_HZ, 115200, &console);
/* Send system_off_now to console */
for (i = 0; i < len; i++) {
diff --git a/plat/marvell/armada/a8k/common/a8k_common.mk b/plat/marvell/armada/a8k/common/a8k_common.mk
index 63cfce2..30e6280 100644
--- a/plat/marvell/armada/a8k/common/a8k_common.mk
+++ b/plat/marvell/armada/a8k/common/a8k_common.mk
@@ -10,13 +10,14 @@
MARVELL_DRV_BASE := drivers/marvell
MARVELL_COMMON_BASE := plat/marvell/armada/common
-MARVELL_SVC_TEST := 0
+MARVELL_SVC_TEST := 0
$(eval $(call add_define,MARVELL_SVC_TEST))
ERRATA_A72_859971 := 1
# Enable MSS support for a8k family
MSS_SUPPORT := 1
+$(eval $(call add_define,MSS_SUPPORT))
# Disable EL3 cache for power management
BL31_CACHE_DISABLE := 0
@@ -79,16 +80,19 @@
drivers/arm/gic/v2/gicv2_helpers.c \
plat/common/plat_gicv2.c
-PLAT_INCLUDES := -I$(BOARD_DIR) \
+PLAT_INCLUDES += -I$(BOARD_DIR) \
-I$(BOARD_DIR)/board \
+ -I$(CURDIR)/drivers/marvell \
-I$(PLAT_COMMON_BASE)/include \
-I$(PLAT_INCLUDE_BASE)/common
PLAT_BL_COMMON_SOURCES := $(PLAT_COMMON_BASE)/aarch64/a8k_common.c \
drivers/ti/uart/aarch64/16550_console.S
+ifndef BLE_PORTING_SOURCES
BLE_PORTING_SOURCES := $(BOARD_DIR)/board/dram_port.c \
$(BOARD_DIR)/board/marvell_plat_config.c
+endif
MARVELL_MOCHI_DRV += $(MARVELL_DRV_BASE)/mochi/cp110_setup.c
@@ -112,11 +116,20 @@
$(MARVELL_DRV_BASE)/amb_adec.c \
$(MARVELL_DRV_BASE)/ccu.c \
$(MARVELL_DRV_BASE)/cache_llc.c \
- $(MARVELL_DRV_BASE)/comphy/phy-comphy-cp110.c \
- $(MARVELL_DRV_BASE)/mc_trustzone/mc_trustzone.c \
- $(MARVELL_DRV_BASE)/mg_conf_cm3/mg_conf_cm3.c
+ $(MARVELL_DRV_BASE)/comphy/phy-comphy-cp110.c \
+ $(MARVELL_DRV_BASE)/mc_trustzone/mc_trustzone.c \
+ $(MARVELL_DRV_BASE)/secure_dfx_access/armada_thermal.c \
+ $(MARVELL_DRV_BASE)/secure_dfx_access/misc_dfx.c \
+ $(MARVELL_DRV_BASE)/ddr_phy_access.c \
+ drivers/rambus/trng_ip_76.c
+ifeq (${MSS_SUPPORT}, 1)
+MARVELL_DRV += $(MARVELL_DRV_BASE)/mg_conf_cm3/mg_conf_cm3.c
+endif
+
+ifndef BL31_PORTING_SOURCES
BL31_PORTING_SOURCES := $(BOARD_DIR)/board/marvell_plat_config.c
+endif
ifeq ($(SYSTEM_POWER_SUPPORT),1)
BL31_PORTING_SOURCES += $(BOARD_DIR)/board/system_power.c
@@ -138,6 +151,8 @@
# Add trace functionality for PM
BL31_SOURCES += $(PLAT_COMMON_BASE)/plat_pm_trace.c
+
+ifeq (${MSS_SUPPORT}, 1)
# Force builds with BL2 image on a80x0 platforms
ifndef SCP_BL2
$(error "Error: SCP_BL2 image is mandatory for a8k family")
@@ -145,6 +160,7 @@
# MSS (SCP) build
include $(PLAT_COMMON_BASE)/mss/mss_a8k.mk
+endif
# BLE (ROM context execution code, AKA binary extension)
BLE_PATH ?= $(PLAT_COMMON_BASE)/ble
diff --git a/plat/marvell/armada/a8k/common/ble/ble.mk b/plat/marvell/armada/a8k/common/ble/ble.mk
index 78c62a0..87e2ce0 100644
--- a/plat/marvell/armada/a8k/common/ble/ble.mk
+++ b/plat/marvell/armada/a8k/common/ble/ble.mk
@@ -3,8 +3,6 @@
# SPDX-License-Identifier: BSD-3-Clause
# https://spdx.org/licenses
-MV_DDR_PATH ?= drivers/marvell/mv_ddr
-
MV_DDR_LIB = $(BUILD_PLAT)/ble/mv_ddr_lib.a
LIBC_LIB = $(BUILD_PLAT)/lib/libc.a
BLE_LIBS = $(MV_DDR_LIB) $(LIBC_LIB)
@@ -13,18 +11,24 @@
BLE_SOURCES += $(BLE_PATH)/ble_main.c \
$(BLE_PATH)/ble_mem.S \
drivers/delay_timer/delay_timer.c \
+ drivers/marvell/iob.c \
$(PLAT_MARVELL)/common/aarch64/marvell_helpers.S \
$(PLAT_MARVELL)/common/plat_delay_timer.c \
$(PLAT_MARVELL)/common/marvell_console.c
-PLAT_INCLUDES += -I$(MV_DDR_PATH) \
- -I$(CURDIR)/include \
+MV_DDR_INCLUDES := -I$(CURDIR)/include \
-I$(CURDIR)/include/arch/aarch64 \
-I$(CURDIR)/include/lib/libc \
- -I$(CURDIR)/include/lib/libc/aarch64 \
- -I$(CURDIR)/drivers/marvell
+ -I$(CURDIR)/include/lib/libc/aarch64
BLE_LINKERFILE := $(BLE_PATH)/ble.ld.S
+BLE_OBJS := $(addprefix $(BUILD_PLAT)/ble/,$(call SOURCES_TO_OBJS,$(BLE_SOURCES)))
+$(BLE_OBJS): PLAT_INCLUDES += -I$(MV_DDR_PATH)
+$(BLE_OBJS): $(MV_DDR_LIB)
+
$(MV_DDR_LIB): FORCE
- @+make -C $(MV_DDR_PATH) --no-print-directory PLAT_INCLUDES="$(PLAT_INCLUDES)" PLATFORM=$(PLAT) ARCH=AARCH64 OBJ_DIR=$(BUILD_PLAT)/ble
+ $(if $(value MV_DDR_PATH),,$(error "Platform '$(PLAT)' for BLE requires MV_DDR_PATH. Please set MV_DDR_PATH to point to the right directory"))
+ $(if $(wildcard $(value MV_DDR_PATH)/*),,$(error "'MV_DDR_PATH=$(value MV_DDR_PATH)' was specified, but '$(value MV_DDR_PATH)' directory does not exist"))
+ $(if $(shell git -C $(value MV_DDR_PATH) rev-parse --show-cdup 2>&1),$(error "'MV_DDR_PATH=$(value MV_DDR_PATH)' was specified, but '$(value MV_DDR_PATH)' does not contain valid mv-ddr-marvell git repository"))
+ @+make -C $(MV_DDR_PATH) --no-print-directory PLAT_INCLUDES="$(MV_DDR_INCLUDES)" PLATFORM=$(PLAT) ARCH=AARCH64 OBJ_DIR=$(BUILD_PLAT)/ble
diff --git a/plat/marvell/armada/a8k/common/include/a8k_plat_def.h b/plat/marvell/armada/a8k/common/include/a8k_plat_def.h
index de80315..3a0fd4b 100644
--- a/plat/marvell/armada/a8k/common/include/a8k_plat_def.h
+++ b/plat/marvell/armada/a8k/common/include/a8k_plat_def.h
@@ -64,7 +64,8 @@
#define MVEBU_AP_GPIO_DATA_IN (MVEBU_AP_GPIO_REGS + 0x10)
#define MVEBU_AP_I2C_BASE (MVEBU_REGS_BASE + 0x511000)
#define MVEBU_CP0_I2C_BASE (MVEBU_CP_REGS_BASE(0) + 0x701000)
-#define MVEBU_AP_EXT_TSEN_BASE (MVEBU_RFU_BASE + 0x8084)
+#define MVEBU_AP_GEN_MGMT_BASE (MVEBU_RFU_BASE + 0x8000)
+#define MVEBU_AP_EXT_TSEN_BASE (MVEBU_AP_GEN_MGMT_BASE + 0x84)
#define MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap, win) (MVEBU_REGS_BASE_AP(ap) + \
0x20080 + ((win) * 0x8))
diff --git a/plat/marvell/armada/a8k/common/include/platform_def.h b/plat/marvell/armada/a8k/common/include/platform_def.h
index 7d85059..45860ba 100644
--- a/plat/marvell/armada/a8k/common/include/platform_def.h
+++ b/plat/marvell/armada/a8k/common/include/platform_def.h
@@ -168,14 +168,8 @@
/*
* PL011 related constants
*/
-#define PLAT_MARVELL_BOOT_UART_BASE (MVEBU_REGS_BASE + 0x512000)
-#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 200000000
-
-#define PLAT_MARVELL_CRASH_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
-#define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
-
-#define PLAT_MARVELL_BL31_RUN_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
-#define PLAT_MARVELL_BL31_RUN_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
+#define PLAT_MARVELL_UART_BASE (MVEBU_REGS_BASE + 0x512000)
+#define PLAT_MARVELL_UART_CLK_IN_HZ 200000000
/* Recovery image enable */
#define PLAT_RECOVERY_IMAGE_ENABLE 0
diff --git a/plat/marvell/armada/a8k/common/mss/mss_a8k.mk b/plat/marvell/armada/a8k/common/mss/mss_a8k.mk
index d8d4921..315fc87 100644
--- a/plat/marvell/armada/a8k/common/mss/mss_a8k.mk
+++ b/plat/marvell/armada/a8k/common/mss/mss_a8k.mk
@@ -11,7 +11,8 @@
BL2_SOURCES += $(A8K_MSS_SOURCE)/mss_bl2_setup.c \
$(MARVELL_MOCHI_DRV)
-BL31_SOURCES += $(A8K_MSS_SOURCE)/mss_pm_ipc.c
+BL31_SOURCES += $(A8K_MSS_SOURCE)/mss_pm_ipc.c \
+ $(A8K_MSS_SOURCE)/mss_bl31_setup.c
PLAT_INCLUDES += -I$(A8K_MSS_SOURCE)
diff --git a/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c b/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
index b919cb3..dee2d5b 100644
--- a/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
+++ b/plat/marvell/armada/a8k/common/mss/mss_bl2_setup.c
@@ -16,7 +16,7 @@
#include <armada_common.h>
#include <marvell_plat_priv.h> /* timer functionality */
-
+#include "mss_defs.h"
#include "mss_scp_bootloader.h"
/* MSS windows configuration */
@@ -121,12 +121,17 @@
uintptr_t bl2_plat_get_cp_mss_regs(int ap_idx, int cp_idx)
{
- return MVEBU_CP_REGS_BASE(cp_idx) + 0x280000;
+ return MVEBU_CP_REGS_BASE(cp_idx) + MSS_CP_REGS_OFFSET;
+}
+
+uintptr_t bl2_plat_get_cp_mss_sram(int ap_idx, int cp_idx)
+{
+ return MVEBU_CP_REGS_BASE(cp_idx) + MSS_CP_SRAM_OFFSET;
}
uintptr_t bl2_plat_get_ap_mss_regs(int ap_idx)
{
- return MVEBU_REGS_BASE + 0x580000;
+ return MVEBU_REGS_BASE + MSS_AP_REGS_OFFSET;
}
uint32_t bl2_plat_get_cp_count(int ap_idx)
diff --git a/plat/marvell/armada/a8k/common/mss/mss_bl31_setup.c b/plat/marvell/armada/a8k/common/mss/mss_bl31_setup.c
new file mode 100644
index 0000000..52a8929
--- /dev/null
+++ b/plat/marvell/armada/a8k/common/mss/mss_bl31_setup.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2021 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <platform_def.h>
+
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include <armada_common.h>
+
+#include "mss_defs.h"
+
+void mss_start_cp_cm3(int cp)
+{
+ uint32_t magic;
+ uintptr_t sram = MVEBU_CP_REGS_BASE(cp) + MSS_CP_SRAM_OFFSET;
+ uintptr_t regs = MVEBU_CP_REGS_BASE(cp) + MSS_CP_REGS_OFFSET;
+
+ magic = mmio_read_32(sram);
+
+ /* Make sure the FW was loaded */
+ if (magic != MSS_FW_READY_MAGIC) {
+ return;
+ }
+
+ NOTICE("Starting CP%d MSS CPU\n", cp);
+ /* remove the magic */
+ mmio_write_32(sram, 0);
+ /* Release M3 from reset */
+ mmio_write_32(MSS_M3_RSTCR(regs),
+ (MSS_M3_RSTCR_RST_OFF << MSS_M3_RSTCR_RST_OFFSET));
+}
diff --git a/plat/marvell/armada/a8k/common/mss/mss_defs.h b/plat/marvell/armada/a8k/common/mss/mss_defs.h
new file mode 100644
index 0000000..6956461
--- /dev/null
+++ b/plat/marvell/armada/a8k/common/mss/mss_defs.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2021 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#ifndef MSS_DEFS_H
+#define MSS_DEFS_H
+
+#define MSS_DMA_SRCBR(base) (base + 0xC0)
+#define MSS_DMA_DSTBR(base) (base + 0xC4)
+#define MSS_DMA_CTRLR(base) (base + 0xC8)
+#define MSS_M3_RSTCR(base) (base + 0xFC)
+
+#define MSS_DMA_CTRLR_SIZE_OFFSET (0)
+#define MSS_DMA_CTRLR_REQ_OFFSET (15)
+#define MSS_DMA_CTRLR_REQ_SET (1)
+#define MSS_DMA_CTRLR_ACK_OFFSET (12)
+#define MSS_DMA_CTRLR_ACK_MASK (0x1)
+#define MSS_DMA_CTRLR_ACK_READY (1)
+#define MSS_M3_RSTCR_RST_OFFSET (0)
+#define MSS_M3_RSTCR_RST_OFF (1)
+
+#define MSS_FW_READY_MAGIC 0x46575144 /* FWRD */
+
+#define MSS_AP_REGS_OFFSET 0x00580000
+#define MSS_CP_SRAM_OFFSET 0x00220000
+#define MSS_CP_REGS_OFFSET 0x00280000
+
+void mss_start_cp_cm3(int cp);
+
+#endif /* MSS_DEFS_H */
diff --git a/plat/marvell/armada/a8k/common/plat_bl31_setup.c b/plat/marvell/armada/a8k/common/plat_bl31_setup.c
index 552c9b2..db85cce 100644
--- a/plat/marvell/armada/a8k/common/plat_bl31_setup.c
+++ b/plat/marvell/armada/a8k/common/plat_bl31_setup.c
@@ -16,8 +16,11 @@
#include <marvell_pm.h>
#include <mc_trustzone/mc_trustzone.h>
#include <plat_marvell.h>
+#if MSS_SUPPORT
#include <mss_ipc_drv.h>
#include <mss_mem.h>
+#include <mss_defs.h>
+#endif
/* In Armada-8k family AP806/AP807, CP0 connected to PIDI
* and CP1 connected to IHB via MCI #0
@@ -51,6 +54,7 @@
mmio_write_32(MVEBU_CP_MPP_REGS(0, 4), reg | 0x2200000);
}
+#if MSS_SUPPORT
void marvell_bl31_mss_init(void)
{
struct mss_pm_ctrl_block *mss_pm_crtl =
@@ -70,6 +74,7 @@
if (mss_pm_crtl->ipc_state == IPC_INITIALIZED)
mv_pm_ipc_init(mss_pm_crtl->ipc_base_address | MVEBU_REGS_BASE);
}
+#endif
_Bool is_pm_fw_running(void)
{
@@ -120,16 +125,22 @@
STREAM_ID_BASE + (cp * MAX_STREAM_ID_PER_CP));
marvell_bl31_mpp_init(cp);
+
+#if MSS_SUPPORT
+ /* Release CP MSS CPU from reset once the CP init is done */
+ mss_start_cp_cm3(cp);
+#endif
}
for (cp = 1; cp < CP_COUNT; cp++)
mci_link_tune(cp - 1);
+#if MSS_SUPPORT
/* initialize IPC between MSS and ATF */
if (mailbox[MBOX_IDX_MAGIC] != MVEBU_MAILBOX_MAGIC_NUM ||
mailbox[MBOX_IDX_SUSPEND_MAGIC] != MVEBU_MAILBOX_SUSPEND_STATE)
marvell_bl31_mss_init();
-
+#endif
/* Configure GPIO */
marvell_gpio_config();
diff --git a/plat/marvell/armada/a8k/common/plat_ble_setup.c b/plat/marvell/armada/a8k/common/plat_ble_setup.c
index e4e09fb..9c5ee15 100644
--- a/plat/marvell/armada/a8k/common/plat_ble_setup.c
+++ b/plat/marvell/armada/a8k/common/plat_ble_setup.c
@@ -14,6 +14,7 @@
#include <drivers/marvell/mochi/cp110_setup.h>
#include <armada_common.h>
+#include <efuse_def.h>
#include <mv_ddr_if.h>
#include <mvebu_def.h>
#include <plat_marvell.h>
@@ -27,7 +28,6 @@
#define MMAP_RESTORE_SAVED 1
/* SAR clock settings */
-#define MVEBU_AP_GEN_MGMT_BASE (MVEBU_RFU_BASE + 0x8000)
#define MVEBU_AP_SAR_REG_BASE(r) (MVEBU_AP_GEN_MGMT_BASE + 0x200 +\
((r) << 2))
@@ -82,11 +82,6 @@
(0x1 << AVS_SOFT_RESET_OFFSET) | \
(0x1 << AVS_ENABLE_OFFSET))
-#define MVEBU_AP_EFUSE_SRV_CTRL_REG (MVEBU_AP_GEN_MGMT_BASE + 0x8)
-#define EFUSE_SRV_CTRL_LD_SELECT_OFFS 6
-#define EFUSE_SRV_CTRL_LD_SEL_USER_MASK (1 << EFUSE_SRV_CTRL_LD_SELECT_OFFS)
-
-
/*
* - Identification information in the LD-0 eFuse:
* DRO: LD0[74:65] - Not used by the SW
@@ -96,14 +91,7 @@
* Cluster 1 PWR: LD0[193] - if set to 1, power down CPU Cluster-1
* resulting in 2 CPUs active only (7020)
*/
-#define MVEBU_AP_LD_EFUSE_BASE (MVEBU_AP_GEN_MGMT_BASE + 0xF00)
-/* Bits [94:63] - 32 data bits total */
-#define MVEBU_AP_LD0_94_63_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x8)
-/* Bits [125:95] - 31 data bits total, 32nd bit is parity for bits [125:63] */
-#define MVEBU_AP_LD0_125_95_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0xC)
-/* Bits [220:189] - 32 data bits total */
-#define MVEBU_AP_LD0_220_189_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x18)
-/* Offsets for the above 2 fields combined into single 64-bit value [125:63] */
+/* Offsets for 2 efuse fields combined into single 64-bit value [125:63] */
#define EFUSE_AP_LD0_DRO_OFFS 2 /* LD0[74:65] */
#define EFUSE_AP_LD0_DRO_MASK 0x3FF
#define EFUSE_AP_LD0_REVID_OFFS 12 /* LD0[78:75] */
@@ -376,20 +364,20 @@
uint8_t avs_data_bits, min_sw_ver, svc_fields;
unsigned int ap_type;
- /* Set access to LD0 */
+ /* Get test EERPOM data */
avs_workpoint = avs_update_from_eeprom(0);
if (avs_workpoint)
goto set_aws_wp;
/* Set access to LD0 */
reg_val = mmio_read_32(MVEBU_AP_EFUSE_SRV_CTRL_REG);
- reg_val &= ~EFUSE_SRV_CTRL_LD_SELECT_OFFS;
+ reg_val &= ~EFUSE_SRV_CTRL_LD_SELECT_MASK;
mmio_write_32(MVEBU_AP_EFUSE_SRV_CTRL_REG, reg_val);
/* Obtain the value of LD0[125:63] */
- efuse = mmio_read_32(MVEBU_AP_LD0_125_95_EFUSE_OFFS);
+ efuse = mmio_read_32(MVEBU_AP_LDX_125_95_EFUSE_OFFS);
efuse <<= 32;
- efuse |= mmio_read_32(MVEBU_AP_LD0_94_63_EFUSE_OFFS);
+ efuse |= mmio_read_32(MVEBU_AP_LDX_94_63_EFUSE_OFFS);
/* SW Revision:
* Starting from SW revision 1 the SVC flow is supported.
@@ -452,7 +440,7 @@
perr[i] = 1; /* register the error */
}
- single_cluster = mmio_read_32(MVEBU_AP_LD0_220_189_EFUSE_OFFS);
+ single_cluster = mmio_read_32(MVEBU_AP_LDX_220_189_EFUSE_OFFS);
single_cluster = (single_cluster >> EFUSE_AP_LD0_CLUSTER_DOWN_OFFS) & 1;
device_id = cp110_device_id_get(MVEBU_CP_REGS_BASE(0));
@@ -720,7 +708,7 @@
int ble_plat_setup(int *skip)
{
- int ret;
+ int ret, cp;
unsigned int freq_mode;
/* Power down unused CPUs */
@@ -745,6 +733,10 @@
/* Do required CP-110 setups for BLE stage */
cp110_ble_init(MVEBU_CP_REGS_BASE(0));
+ /* Config address for each cp other than cp0 */
+ for (cp = 1; cp < CP_COUNT; cp++)
+ update_cp110_default_win(cp);
+
/* Setup AVS */
ble_plat_svc_config();
diff --git a/plat/marvell/armada/a8k/common/plat_pm.c b/plat/marvell/armada/a8k/common/plat_pm.c
index 96e95c2..9ea9276 100644
--- a/plat/marvell/armada/a8k/common/plat_pm.c
+++ b/plat/marvell/armada/a8k/common/plat_pm.c
@@ -18,7 +18,9 @@
#include <armada_common.h>
#include <marvell_pm.h>
+#if MSS_SUPPORT
#include <mss_pm_ipc.h>
+#endif
#include <plat_marvell.h>
#include <plat_pm_trace.h>
@@ -396,6 +398,7 @@
/* Power up CPU (CPUs 1-3 are powered off at start of BLE) */
plat_marvell_cpu_powerup(mpidr);
+#if MSS_SUPPORT
if (is_pm_fw_running()) {
unsigned int target =
((mpidr & 0xFF) + (((mpidr >> 8) & 0xFF) * 2));
@@ -417,11 +420,12 @@
/* trace message */
PM_TRACE(TRACE_PWR_DOMAIN_ON | target);
- } else {
+ } else
+#endif
+ {
/* proprietary CPU ON exection flow */
plat_marvell_cpu_on(mpidr);
}
-
return 0;
}
@@ -441,6 +445,7 @@
*/
static void a8k_pwr_domain_off(const psci_power_state_t *target_state)
{
+#if MSS_SUPPORT
if (is_pm_fw_running()) {
unsigned int idx = plat_my_core_pos();
@@ -466,6 +471,7 @@
} else {
INFO("%s: is not supported without SCP\n", __func__);
}
+#endif
}
/* Get PM config to power off the SoC */
@@ -586,6 +592,7 @@
*/
static void a8k_pwr_domain_suspend(const psci_power_state_t *target_state)
{
+#if MSS_SUPPORT
if (is_pm_fw_running()) {
unsigned int idx;
@@ -610,7 +617,9 @@
/* trace message */
PM_TRACE(TRACE_PWR_DOMAIN_SUSPEND);
- } else {
+ } else
+#endif
+ {
uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE;
INFO("Suspending to RAM\n");
diff --git a/plat/marvell/armada/a8k/common/plat_pm_trace.c b/plat/marvell/armada/a8k/common/plat_pm_trace.c
index f589ff3..e02a893 100644
--- a/plat/marvell/armada/a8k/common/plat_pm_trace.c
+++ b/plat/marvell/armada/a8k/common/plat_pm_trace.c
@@ -8,10 +8,11 @@
#include <lib/mmio.h>
#include <plat/common/platform.h>
+#if MSS_SUPPORT
#include <mss_mem.h>
-#include <plat_pm_trace.h>
#ifdef PM_TRACE_ENABLE
+#include <plat_pm_trace.h>
/* core trace APIs */
core_trace_func funcTbl[PLATFORM_CORE_COUNT] = {
@@ -90,3 +91,4 @@
AP_MSS_ATF_TRACE_SIZE_MASK));
}
#endif /* PM_TRACE_ENABLE */
+#endif /* MSS_SUPPORT */
diff --git a/plat/marvell/armada/common/aarch64/marvell_helpers.S b/plat/marvell/armada/common/aarch64/marvell_helpers.S
index b798f17..3038ec0 100644
--- a/plat/marvell/armada/common/aarch64/marvell_helpers.S
+++ b/plat/marvell/armada/common/aarch64/marvell_helpers.S
@@ -63,8 +63,16 @@
* ---------------------------------------------
*/
func plat_crash_console_init
- mov_imm x0, PLAT_MARVELL_CRASH_UART_BASE
- mov_imm x1, PLAT_MARVELL_CRASH_UART_CLK_IN_HZ
+#ifdef PLAT_a3700
+ mov x1, x30
+ bl get_ref_clk
+ mov x30, x1
+ mov_imm x1, 1000000
+ mul x1, x0, x1
+#else
+ mov_imm x1, PLAT_MARVELL_UART_CLK_IN_HZ
+#endif
+ mov_imm x0, PLAT_MARVELL_UART_BASE
mov_imm x2, MARVELL_CONSOLE_BAUDRATE
#ifdef PLAT_a3700
b console_a3700_core_init
@@ -81,7 +89,7 @@
* ---------------------------------------------
*/
func plat_crash_console_putc
- mov_imm x1, PLAT_MARVELL_CRASH_UART_BASE
+ mov_imm x1, PLAT_MARVELL_UART_BASE
#ifdef PLAT_a3700
b console_a3700_core_putc
@@ -99,7 +107,7 @@
* ---------------------------------------------
*/
func plat_crash_console_flush
- mov_imm x0, PLAT_MARVELL_CRASH_UART_BASE
+ mov_imm x0, PLAT_MARVELL_UART_BASE
#ifdef PLAT_a3700
b console_a3700_core_flush
#else
diff --git a/plat/marvell/armada/common/marvell_common.mk b/plat/marvell/armada/common/marvell_common.mk
index 04eb51c..f0e6edf 100644
--- a/plat/marvell/armada/common/marvell_common.mk
+++ b/plat/marvell/armada/common/marvell_common.mk
@@ -6,10 +6,6 @@
MARVELL_PLAT_BASE := plat/marvell/armada
MARVELL_PLAT_INCLUDE_BASE := include/plat/marvell/armada
-include plat/marvell/version.mk
-
-VERSION_STRING +=(Marvell-${SUBVERSION})
-
SEPARATE_CODE_AND_RODATA := 1
# flag to switch from PLL to ARO
diff --git a/plat/marvell/armada/common/marvell_console.c b/plat/marvell/armada/common/marvell_console.c
index c84b004..ef54bff 100644
--- a/plat/marvell/armada/common/marvell_console.c
+++ b/plat/marvell/armada/common/marvell_console.c
@@ -14,6 +14,7 @@
#ifdef PLAT_a3700
#include <drivers/marvell/uart/a3700_console.h>
+#define PLAT_MARVELL_UART_CLK_IN_HZ (get_ref_clk() * 1000000)
#define console_marvell_register console_a3700_register
#else
#include <drivers/ti/uart/uart_16550.h>
@@ -31,8 +32,8 @@
void marvell_console_boot_init(void)
{
int rc =
- console_marvell_register(PLAT_MARVELL_BOOT_UART_BASE,
- PLAT_MARVELL_BOOT_UART_CLK_IN_HZ,
+ console_marvell_register(PLAT_MARVELL_UART_BASE,
+ PLAT_MARVELL_UART_CLK_IN_HZ,
MARVELL_CONSOLE_BAUDRATE,
&marvell_boot_console);
if (rc == 0) {
@@ -58,8 +59,8 @@
void marvell_console_runtime_init(void)
{
int rc =
- console_marvell_register(PLAT_MARVELL_BOOT_UART_BASE,
- PLAT_MARVELL_BOOT_UART_CLK_IN_HZ,
+ console_marvell_register(PLAT_MARVELL_UART_BASE,
+ PLAT_MARVELL_UART_CLK_IN_HZ,
MARVELL_CONSOLE_BAUDRATE,
&marvell_runtime_console);
if (rc == 0)
diff --git a/plat/marvell/armada/common/mrvl_sip_svc.c b/plat/marvell/armada/common/mrvl_sip_svc.c
index 0291024..c4c5c0e 100644
--- a/plat/marvell/armada/common/mrvl_sip_svc.c
+++ b/plat/marvell/armada/common/mrvl_sip_svc.c
@@ -9,12 +9,15 @@
#include <common/runtime_svc.h>
#include <drivers/marvell/cache_llc.h>
#include <drivers/marvell/mochi/ap_setup.h>
+#include <drivers/rambus/trng_ip_76.h>
#include <lib/smccc.h>
#include <marvell_plat_priv.h>
#include <plat_marvell.h>
#include "comphy/phy-comphy-cp110.h"
+#include "secure_dfx_access/dfx.h"
+#include "ddr_phy_access.h"
#include <stdbool.h>
/* #define DEBUG_COMPHY */
@@ -36,11 +39,20 @@
#define MV_SIP_LLC_ENABLE 0x82000011
#define MV_SIP_PMU_IRQ_ENABLE 0x82000012
#define MV_SIP_PMU_IRQ_DISABLE 0x82000013
+#define MV_SIP_DFX 0x82000014
+#define MV_SIP_DDR_PHY_WRITE 0x82000015
+#define MV_SIP_DDR_PHY_READ 0x82000016
+
+/* TRNG */
+#define MV_SIP_RNG_64 0xC200FF11
#define MAX_LANE_NR 6
#define MVEBU_COMPHY_OFFSET 0x441000
#define MVEBU_CP_BASE_MASK (~0xffffff)
+/* Common PHY register */
+#define COMPHY_TRX_TRAIN_CTRL_REG_0_OFFS 0x120a2c
+
/* This macro is used to identify COMPHY related calls from SMC function ID */
#define is_comphy_fid(fid) \
((fid) >= MV_SIP_COMPHY_POWER_ON && (fid) <= MV_SIP_COMPHY_DIG_RESET)
@@ -67,7 +79,7 @@
void *handle,
u_register_t flags)
{
- u_register_t ret;
+ u_register_t ret, read, x5 = x1;
int i;
debug("%s: got SMC (0x%x) x1 0x%lx, x2 0x%lx, x3 0x%lx\n",
@@ -81,6 +93,7 @@
SMC_RET1(handle, SMC_UNK);
}
+ x5 = x1 + COMPHY_TRX_TRAIN_CTRL_REG_0_OFFS;
x1 += MVEBU_COMPHY_OFFSET;
if (x2 >= MAX_LANE_NR) {
@@ -95,7 +108,7 @@
/* Comphy related FID's */
case MV_SIP_COMPHY_POWER_ON:
/* x1: comphy_base, x2: comphy_index, x3: comphy_mode */
- ret = mvebu_cp110_comphy_power_on(x1, x2, x3);
+ ret = mvebu_cp110_comphy_power_on(x1, x2, x3, x5);
SMC_RET1(handle, ret);
case MV_SIP_COMPHY_POWER_OFF:
/* x1: comphy_base, x2: comphy_index */
@@ -131,7 +144,33 @@
mvebu_pmu_interrupt_disable();
SMC_RET1(handle, 0);
#endif
+ case MV_SIP_DFX:
+ if (x1 >= MV_SIP_DFX_THERMAL_INIT &&
+ x1 <= MV_SIP_DFX_THERMAL_SEL_CHANNEL) {
+ ret = mvebu_dfx_thermal_handle(x1, &read, x2, x3);
+ SMC_RET2(handle, ret, read);
+ }
+ if (x1 >= MV_SIP_DFX_SREAD && x1 <= MV_SIP_DFX_SWRITE) {
+ ret = mvebu_dfx_misc_handle(x1, &read, x2, x3);
+ SMC_RET2(handle, ret, read);
+ }
+ SMC_RET1(handle, SMC_UNK);
+ case MV_SIP_DDR_PHY_WRITE:
+ ret = mvebu_ddr_phy_write(x1, x2);
+ SMC_RET1(handle, ret);
+ case MV_SIP_DDR_PHY_READ:
+ read = 0;
+ ret = mvebu_ddr_phy_read(x1, (uint16_t *)&read);
+ SMC_RET2(handle, ret, read);
+ case MV_SIP_RNG_64:
+ if ((x1 % 2 + 1) > sizeof(read)/4) {
+ ERROR("%s: Maximum %ld random bytes per SMC call\n",
+ __func__, sizeof(read));
+ SMC_RET1(handle, SMC_UNK);
+ }
+ ret = eip76_rng_get_random((uint8_t *)&read, 4 * (x1 % 2 + 1));
+ SMC_RET2(handle, ret, read);
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
SMC_RET1(handle, SMC_UNK);
diff --git a/plat/marvell/armada/common/mss/mss_scp_bl2_format.h b/plat/marvell/armada/common/mss/mss_scp_bl2_format.h
index 74dddc6..90913b0 100644
--- a/plat/marvell/armada/common/mss/mss_scp_bl2_format.h
+++ b/plat/marvell/armada/common/mss/mss_scp_bl2_format.h
@@ -13,6 +13,7 @@
#define HEADER_VERSION 0x1
#define MSS_IDRAM_SIZE 0x10000 /* 64KB */
+#define MSS_SRAM_SIZE 0x8000 /* 32KB */
/* Types definitions */
typedef struct file_header {
diff --git a/plat/marvell/armada/common/mss/mss_scp_bootloader.c b/plat/marvell/armada/common/mss/mss_scp_bootloader.c
index adf570e..fbede1b 100644
--- a/plat/marvell/armada/common/mss/mss_scp_bootloader.c
+++ b/plat/marvell/armada/common/mss/mss_scp_bootloader.c
@@ -19,25 +19,14 @@
#include <mss_scp_bootloader.h>
#include <mss_ipc_drv.h>
#include <mss_mem.h>
+#include <mss_defs.h>
#include <mss_scp_bl2_format.h>
-#define MSS_DMA_SRCBR(base) (base + 0xC0)
-#define MSS_DMA_DSTBR(base) (base + 0xC4)
-#define MSS_DMA_CTRLR(base) (base + 0xC8)
-#define MSS_M3_RSTCR(base) (base + 0xFC)
-
-#define MSS_DMA_CTRLR_SIZE_OFFSET (0)
-#define MSS_DMA_CTRLR_REQ_OFFSET (15)
-#define MSS_DMA_CTRLR_REQ_SET (1)
-#define MSS_DMA_CTRLR_ACK_OFFSET (12)
-#define MSS_DMA_CTRLR_ACK_MASK (0x1)
-#define MSS_DMA_CTRLR_ACK_READY (1)
-#define MSS_M3_RSTCR_RST_OFFSET (0)
-#define MSS_M3_RSTCR_RST_OFF (1)
-
#define MSS_DMA_TIMEOUT 1000
#define MSS_EXTERNAL_SPACE 0x50000000
#define MSS_EXTERNAL_ADDR_MASK 0xfffffff
+#define MSS_INTERNAL_SPACE 0x40000000
+#define MSS_INTERNAL_ADDR_MASK 0x00ffffff
#define DMA_SIZE 128
@@ -60,60 +49,118 @@
return 0;
}
-static int mss_image_load(uint32_t src_addr, uint32_t size, uintptr_t mss_regs)
+static int mss_iram_dma_load(uint32_t src_addr, uint32_t size,
+ uintptr_t mss_regs)
{
uint32_t i, loop_num, timeout;
+ /* load image to MSS RAM using DMA */
+ loop_num = (size / DMA_SIZE) + !!(size % DMA_SIZE);
+ for (i = 0; i < loop_num; i++) {
+ /* write source address */
+ mmio_write_32(MSS_DMA_SRCBR(mss_regs),
+ src_addr + (i * DMA_SIZE));
+ /* write destination address */
+ mmio_write_32(MSS_DMA_DSTBR(mss_regs), (i * DMA_SIZE));
+ /* make sure DMA data is ready before triggering it */
+ dsb();
+ /* set the DMA control register */
+ mmio_write_32(MSS_DMA_CTRLR(mss_regs),
+ ((MSS_DMA_CTRLR_REQ_SET <<
+ MSS_DMA_CTRLR_REQ_OFFSET) |
+ (DMA_SIZE << MSS_DMA_CTRLR_SIZE_OFFSET)));
+ /* Poll DMA_ACK at MSS_DMACTLR until it is ready */
+ timeout = MSS_DMA_TIMEOUT;
+ while (timeout > 0U) {
+ if (((mmio_read_32(MSS_DMA_CTRLR(mss_regs)) >>
+ MSS_DMA_CTRLR_ACK_OFFSET) &
+ MSS_DMA_CTRLR_ACK_MASK)
+ == MSS_DMA_CTRLR_ACK_READY) {
+ break;
+ }
+ udelay(50);
+ timeout--;
+ }
+ if (timeout == 0) {
+ ERROR("\nMSS DMA failed (timeout)\n");
+ return 1;
+ }
+ }
+ return 0;
+}
+
+static int mss_image_load(uint32_t src_addr, uint32_t size,
+ uintptr_t mss_regs, uintptr_t sram)
+{
+ uint32_t chunks = 1; /* !sram case */
+ uint32_t chunk_num;
+ int ret;
+
/* Check if the img size is not bigger than ID-RAM size of MSS CM3 */
if (size > MSS_IDRAM_SIZE) {
ERROR("image is too big to fit into MSS CM3 memory\n");
return 1;
}
- NOTICE("Loading MSS image from addr. 0x%x Size 0x%x to MSS at 0x%lx\n",
- src_addr, size, mss_regs);
- /* load image to MSS RAM using DMA */
- loop_num = (size / DMA_SIZE) + (((size & (DMA_SIZE - 1)) == 0) ? 0 : 1);
+ /* The CPx MSS DMA cannot access DRAM directly in secure boot mode
+ * Copy the MSS FW image to MSS SRAM by the CPU first, then run
+ * MSS DMA for SRAM to IRAM copy
+ */
+ if (sram != 0) {
+ chunks = size / MSS_SRAM_SIZE + !!(size % MSS_SRAM_SIZE);
+ }
- for (i = 0; i < loop_num; i++) {
- /* write destination and source addresses */
- mmio_write_32(MSS_DMA_SRCBR(mss_regs),
- MSS_EXTERNAL_SPACE |
- ((src_addr & MSS_EXTERNAL_ADDR_MASK) +
- (i * DMA_SIZE)));
- mmio_write_32(MSS_DMA_DSTBR(mss_regs), (i * DMA_SIZE));
+ NOTICE("%s Loading MSS FW from addr. 0x%x Size 0x%x to MSS at 0x%lx\n",
+ sram == 0 ? "" : "SECURELY", src_addr, size, mss_regs);
+ for (chunk_num = 0; chunk_num < chunks; chunk_num++) {
+ size_t chunk_size = size;
+ uint32_t img_src = MSS_EXTERNAL_SPACE | /* no SRAM */
+ (src_addr & MSS_EXTERNAL_ADDR_MASK);
- dsb(); /* make sure DMA data is ready before triggering it */
+ if (sram != 0) {
+ uintptr_t chunk_source =
+ src_addr + MSS_SRAM_SIZE * chunk_num;
- /* set the DMA control register */
- mmio_write_32(MSS_DMA_CTRLR(mss_regs), ((MSS_DMA_CTRLR_REQ_SET
- << MSS_DMA_CTRLR_REQ_OFFSET) |
- (DMA_SIZE << MSS_DMA_CTRLR_SIZE_OFFSET)));
+ if (chunk_num != (size / MSS_SRAM_SIZE)) {
+ chunk_size = MSS_SRAM_SIZE;
+ } else {
+ chunk_size = size % MSS_SRAM_SIZE;
+ }
- /* Poll DMA_ACK at MSS_DMACTLR until it is ready */
- timeout = MSS_DMA_TIMEOUT;
- while (timeout) {
- if ((mmio_read_32(MSS_DMA_CTRLR(mss_regs)) >>
- MSS_DMA_CTRLR_ACK_OFFSET & MSS_DMA_CTRLR_ACK_MASK)
- == MSS_DMA_CTRLR_ACK_READY) {
+ if (chunk_size == 0) {
break;
}
- udelay(50);
- timeout--;
+ VERBOSE("Chunk %d -> SRAM 0x%lx from 0x%lx SZ 0x%lx\n",
+ chunk_num, sram, chunk_source, chunk_size);
+ memcpy((void *)sram, (void *)chunk_source, chunk_size);
+ dsb();
+ img_src = MSS_INTERNAL_SPACE |
+ (sram & MSS_INTERNAL_ADDR_MASK);
}
- if (timeout == 0) {
- ERROR("\nDMA failed to load MSS image\n");
- return 1;
+ ret = mss_iram_dma_load(img_src, chunk_size, mss_regs);
+ if (ret != 0) {
+ ERROR("MSS FW chunk %d load failed\n", chunk_num);
+ return ret;
}
}
bl2_plat_configure_mss_windows(mss_regs);
- /* Release M3 from reset */
- mmio_write_32(MSS_M3_RSTCR(mss_regs), (MSS_M3_RSTCR_RST_OFF <<
- MSS_M3_RSTCR_RST_OFFSET));
+ if (sram != 0) {
+ /* Wipe the MSS SRAM after using it as copy buffer */
+ memset((void *)sram, 0, MSS_SRAM_SIZE);
+ NOTICE("CP MSS startup is postponed\n");
+ /* FW loaded, but CPU startup postponed until final CP setup */
+ mmio_write_32(sram, MSS_FW_READY_MAGIC);
+ dsb();
+ } else {
+ /* Release M3 from reset */
+ mmio_write_32(MSS_M3_RSTCR(mss_regs),
+ (MSS_M3_RSTCR_RST_OFF <<
+ MSS_M3_RSTCR_RST_OFFSET));
+ }
NOTICE("Done\n");
@@ -162,7 +209,7 @@
VERBOSE("Send info about the SCP_BL2 image to be transferred to SCP\n");
ret = mss_image_load(single_img, image_size,
- bl2_plat_get_ap_mss_regs(ap_idx));
+ bl2_plat_get_ap_mss_regs(ap_idx), 0);
if (ret != 0) {
ERROR("SCP Image load failed\n");
return -1;
@@ -218,6 +265,8 @@
cp_index, ap_idx);
ret = mss_image_load(single_img, image_size,
bl2_plat_get_cp_mss_regs(
+ ap_idx, cp_index),
+ bl2_plat_get_cp_mss_sram(
ap_idx, cp_index));
if (ret != 0) {
ERROR("SCP Image load failed\n");
diff --git a/plat/marvell/armada/common/mss/mss_scp_bootloader.h b/plat/marvell/armada/common/mss/mss_scp_bootloader.h
index 4950d24..d65354a 100644
--- a/plat/marvell/armada/common/mss/mss_scp_bootloader.h
+++ b/plat/marvell/armada/common/mss/mss_scp_bootloader.h
@@ -10,6 +10,7 @@
int scp_bootloader_transfer(void *image, unsigned int image_size);
uintptr_t bl2_plat_get_cp_mss_regs(int ap_idx, int cp_idx);
+uintptr_t bl2_plat_get_cp_mss_sram(int ap_idx, int cp_idx);
uintptr_t bl2_plat_get_ap_mss_regs(int ap_idx);
uint32_t bl2_plat_get_cp_count(int ap_idx);
uint32_t bl2_plat_get_ap_count(void);
diff --git a/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c b/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c
index 0befadf..82ce07b 100644
--- a/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c
+++ b/plat/marvell/octeontx/otx2/t91/t9130/board/dram_port.c
@@ -149,7 +149,7 @@
i2c_init((void *)MVEBU_CP0_I2C_BASE);
/* select SPD memory page 0 to access DRAM configuration */
- i2c_write(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 1);
+ i2c_write(I2C_SPD_P0_ADDR, 0x0, 1, tm->spd_data.all_bytes, 0);
/* read data from spd */
i2c_read(I2C_SPD_ADDR, 0x0, 1, tm->spd_data.all_bytes,
diff --git a/plat/marvell/octeontx/otx2/t91/t9130/board/marvell_plat_config.c b/plat/marvell/octeontx/otx2/t91/t9130/board/marvell_plat_config.c
index 7debd65..fbacf54 100644
--- a/plat/marvell/octeontx/otx2/t91/t9130/board/marvell_plat_config.c
+++ b/plat/marvell/octeontx/otx2/t91/t9130/board/marvell_plat_config.c
@@ -46,15 +46,19 @@
*****************************************************************************
*/
struct addr_map_win io_win_memory_map[] = {
+#if (CP_COUNT > 1)
+ /* SB (MCi0) internal regs */
+ {0x00000000f4000000, 0x2000000, MCI_0_TID},
+#if (CP_COUNT > 2)
+ /* SB (MCi1) internal regs */
+ {0x00000000f6000000, 0x2000000, MCI_1_TID},
+#endif
+#endif
#ifndef IMAGE_BLE
/* SB (MCi0) PCIe0-2 on CP1 */
{0x00000000e2000000, 0x3000000, MCI_0_TID},
/* SB (MCi1) PCIe0-2 on CP2 */
{0x00000000e5000000, 0x3000000, MCI_1_TID},
- /* SB (MCi0) internal regs */
- {0x00000000f4000000, 0x2000000, MCI_0_TID},
- /* SB (MCi1) internal regs */
- {0x00000000f6000000, 0x2000000, MCI_1_TID},
/* MCI 0 indirect window */
{MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID},
/* MCI 1 indirect window */
diff --git a/plat/marvell/octeontx/otx2/t91/t9130_cex7_eval/board/marvell_plat_config.c b/plat/marvell/octeontx/otx2/t91/t9130_cex7_eval/board/marvell_plat_config.c
new file mode 100644
index 0000000..5bae8eb
--- /dev/null
+++ b/plat/marvell/octeontx/otx2/t91/t9130_cex7_eval/board/marvell_plat_config.c
@@ -0,0 +1,224 @@
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ * Copyright (C) 2021 Semihalf.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <armada_common.h>
+#include <mvebu_def.h>
+
+/*
+ * If bootrom is currently at BLE there's no need to include the memory
+ * maps structure at this point
+ */
+#ifndef IMAGE_BLE
+
+/*****************************************************************************
+ * AMB Configuration
+ *****************************************************************************
+ */
+struct addr_map_win amb_memory_map_cp0[] = {
+ /* CP0 SPI1 CS0 Direct Mode access */
+ {0xef00, 0x1000000, AMB_SPI1_CS0_ID},
+};
+
+struct addr_map_win amb_memory_map_cp1[] = {
+ /* CP1 SPI1 CS0 Direct Mode access */
+ {0xe800, 0x1000000, AMB_SPI1_CS0_ID},
+};
+
+int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size,
+ uintptr_t base)
+{
+ switch (base) {
+ case MVEBU_CP_REGS_BASE(0):
+ *win = amb_memory_map_cp0;
+ *size = ARRAY_SIZE(amb_memory_map_cp0);
+ return 0;
+ case MVEBU_CP_REGS_BASE(1):
+ *win = amb_memory_map_cp1;
+ *size = ARRAY_SIZE(amb_memory_map_cp1);
+ return 0;
+ case MVEBU_CP_REGS_BASE(2):
+ default:
+ *size = 0;
+ *win = 0;
+ return 1;
+ }
+}
+#endif
+
+/*****************************************************************************
+ * IO WIN Configuration
+ *****************************************************************************
+ */
+struct addr_map_win io_win_memory_map[] = {
+#if (CP_COUNT > 1)
+ /* SB (MCi0) internal regs */
+ {0x00000000f4000000, 0x2000000, MCI_0_TID},
+ /* SB (MCi0) PCIe0-2 on CP1 */
+ {0x00000000e2000000, 0x7000000, MCI_0_TID},
+ /*
+ * Due to lack of sufficient number of IO windows registers,
+ * below CP1 PCIE configuration must be performed in the
+ * later firmware stages. It should replace the MCI 0 indirect
+ * window, which becomes no longer needed.
+ */
+ /* {0x0000000890000000, 0x30000000, MCI_0_TID}, */
+#if (CP_COUNT > 2)
+ /* SB (MCi1) internal regs */
+ {0x00000000f6000000, 0x2000000, MCI_1_TID},
+ /* SB (MCi1) PCIe0-2 on CP2 */
+ {0x00000000e9000000, 0x6000000, MCI_1_TID},
+ /*
+ * Due to lack of sufficient number of IO windows registers,
+ * below CP2 PCIE configuration must be performed in the
+ * later firmware stages. It should replace the MCI 1 indirect
+ * window, which becomes no longer needed.
+ */
+ /* {0x00000008c0000000, 0x30000000, MCI_1_TID}, */
+#endif
+#endif
+#ifndef IMAGE_BLE
+ /* MCI 0 indirect window */
+ {MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID},
+ /* MCI 1 indirect window */
+ {MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID},
+#endif
+};
+
+/* Global Control Register - window default target */
+uint32_t marvell_get_io_win_gcr_target(int ap_index)
+{
+ /*
+ * PIDI == iMCIP AP to SB internal MoChi connection.
+ * In other words CP0
+ */
+ return PIDI_TID;
+}
+
+int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win,
+ uint32_t *size)
+{
+ *win = io_win_memory_map;
+ if (*win == NULL)
+ *size = 0;
+ else
+ *size = ARRAY_SIZE(io_win_memory_map);
+
+ return 0;
+}
+
+#ifndef IMAGE_BLE
+/*****************************************************************************
+ * IOB Configuration
+ *****************************************************************************
+ */
+struct addr_map_win iob_memory_map_cp0[] = {
+ /* SPI1_CS0 (RUNIT) window */
+ {0x00000000ef000000, 0x1000000, RUNIT_TID},
+ /* PEX2_X1 window */
+ {0x00000000e1000000, 0x1000000, PEX2_TID},
+ /* PEX1_X1 window */
+ {0x00000000e0000000, 0x1000000, PEX1_TID},
+ /* PEX0_X4 window */
+ {0x00000000c0000000, 0x20000000, PEX0_TID},
+ {0x0000000800000000, 0x90000000, PEX0_TID},
+};
+
+struct addr_map_win iob_memory_map_cp1[] = {
+ /* SPI1_CS0 (RUNIT) window */
+ {0x00000000e8000000, 0x1000000, RUNIT_TID},
+ /* PEX2_X1 window */
+ {0x00000000e6000000, 0x2000000, PEX2_TID},
+ {0x00000008b0000000, 0x10000000, PEX2_TID},
+ /* PEX1_X1 window */
+ {0x00000000e4000000, 0x2000000, PEX1_TID},
+ {0x00000008a0000000, 0x10000000, PEX1_TID},
+ /* PEX0_X2 window */
+ {0x00000000e2000000, 0x2000000, PEX0_TID},
+ {0x0000000890000000, 0x10000000, PEX0_TID},
+};
+
+struct addr_map_win iob_memory_map_cp2[] = {
+
+ /* PEX2_X1 window */
+ {0x00000000ed000000, 0x2000000, PEX2_TID},
+ {0x00000008e0000000, 0x10000000, PEX2_TID},
+ /* PEX1_X1 window */
+ {0x00000000eb000000, 0x2000000, PEX1_TID},
+ {0x00000008d0000000, 0x10000000, PEX1_TID},
+ /* PEX0_X1 window */
+ {0x00000000e9000000, 0x2000000, PEX0_TID},
+ {0x00000008c0000000, 0x10000000, PEX0_TID},
+};
+
+int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size,
+ uintptr_t base)
+{
+ switch (base) {
+ case MVEBU_CP_REGS_BASE(0):
+ *win = iob_memory_map_cp0;
+ *size = ARRAY_SIZE(iob_memory_map_cp0);
+ return 0;
+ case MVEBU_CP_REGS_BASE(1):
+ *win = iob_memory_map_cp1;
+ *size = ARRAY_SIZE(iob_memory_map_cp1);
+ return 0;
+ case MVEBU_CP_REGS_BASE(2):
+ *win = iob_memory_map_cp2;
+ *size = ARRAY_SIZE(iob_memory_map_cp2);
+ return 0;
+ default:
+ *size = 0;
+ *win = 0;
+ return 1;
+ }
+}
+#endif
+
+/*****************************************************************************
+ * CCU Configuration
+ *****************************************************************************
+ */
+struct addr_map_win ccu_memory_map[] = { /* IO window */
+#ifdef IMAGE_BLE
+ {0x00000000f2000000, 0x6000000, IO_0_TID}, /* IO window */
+#else
+#if LLC_SRAM
+ {PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID},
+#endif
+ {0x00000000f2000000, 0xe000000, IO_0_TID}, /* IO window */
+ {0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
+ {0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */
+ {0x0000002000000000, 0x70e000000, IO_0_TID}, /* IO for CV-OS */
+#endif
+};
+
+uint32_t marvell_get_ccu_gcr_target(int ap)
+{
+ return DRAM_0_TID;
+}
+
+int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win,
+ uint32_t *size)
+{
+ *win = ccu_memory_map;
+ *size = ARRAY_SIZE(ccu_memory_map);
+
+ return 0;
+}
+
+#ifdef IMAGE_BLE
+/*****************************************************************************
+ * SKIP IMAGE Configuration
+ *****************************************************************************
+ */
+void *plat_get_skip_image_data(void)
+{
+ /* No recovery button on CN-9130 board? */
+ return NULL;
+}
+#endif
diff --git a/plat/marvell/octeontx/otx2/t91/t9130_cex7_eval/platform.mk b/plat/marvell/octeontx/otx2/t91/t9130_cex7_eval/platform.mk
new file mode 100644
index 0000000..ee55455
--- /dev/null
+++ b/plat/marvell/octeontx/otx2/t91/t9130_cex7_eval/platform.mk
@@ -0,0 +1,33 @@
+#
+# Copyright (C) 2018 Marvell International Ltd.
+# Copyright (C) 2021 Semihalf.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+# https://spdx.org/licenses
+#
+
+PCI_EP_SUPPORT := 0
+
+CP_NUM := 1
+$(eval $(call add_define,CP_NUM))
+
+DOIMAGE_SEC := tools/doimage/secure/sec_img_7K.cfg
+
+MARVELL_MOCHI_DRV := drivers/marvell/mochi/ap807_setup.c
+
+BOARD_DIR := $(shell dirname $(lastword $(MAKEFILE_LIST)))
+
+#
+# CN913X CEx7 Evaluation Board shares the DRAM connectivity
+# and SerDes settings with the CN913X DB - reuse relevant
+# board-specific files.
+#
+T9130_DIR := $(BOARD_DIR)/../t9130
+PLAT_INCLUDES := -I$(T9130_DIR) \
+ -I$(T9130_DIR)/board
+BLE_PORTING_SOURCES := $(T9130_DIR)/board/dram_port.c \
+ $(BOARD_DIR)/board/marvell_plat_config.c
+
+include plat/marvell/armada/a8k/common/a8k_common.mk
+
+include plat/marvell/armada/common/marvell_common.mk
diff --git a/plat/marvell/version.mk b/plat/marvell/version.mk
deleted file mode 100644
index bb22255..0000000
--- a/plat/marvell/version.mk
+++ /dev/null
@@ -1 +0,0 @@
-SUBVERSION = devel-18.12.2
diff --git a/plat/mediatek/mt8192/plat_mt_gic.c b/plat/mediatek/common/drivers/gic600/mt_gic_v3.c
similarity index 100%
rename from plat/mediatek/mt8192/plat_mt_gic.c
rename to plat/mediatek/common/drivers/gic600/mt_gic_v3.c
diff --git a/plat/mediatek/mt8192/include/mt_gic_v3.h b/plat/mediatek/common/drivers/gic600/mt_gic_v3.h
similarity index 100%
rename from plat/mediatek/mt8192/include/mt_gic_v3.h
rename to plat/mediatek/common/drivers/gic600/mt_gic_v3.h
diff --git a/plat/mediatek/common/drivers/gpio/mtgpio_common.c b/plat/mediatek/common/drivers/gpio/mtgpio_common.c
new file mode 100644
index 0000000..89977a5
--- /dev/null
+++ b/plat/mediatek/common/drivers/gpio/mtgpio_common.c
@@ -0,0 +1,298 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <drivers/gpio.h>
+#include <lib/mmio.h>
+#include <mtgpio.h>
+#include <platform_def.h>
+
+/******************************************************************************
+ *Macro Definition
+ ******************************************************************************/
+#define GPIO_MODE_BITS 4
+#define MAX_GPIO_MODE_PER_REG 8
+#define MAX_GPIO_REG_BITS 32
+#define DIR_BASE (GPIO_BASE + 0x000)
+#define DOUT_BASE (GPIO_BASE + 0x100)
+#define DIN_BASE (GPIO_BASE + 0x200)
+#define MODE_BASE (GPIO_BASE + 0x300)
+#define SET 0x4
+#define CLR 0x8
+
+static void mt_set_gpio_dir_chip(uint32_t pin, int dir)
+{
+ uint32_t pos, bit;
+
+ assert(pin < MAX_GPIO_PIN);
+ assert(dir < MT_GPIO_DIR_MAX);
+
+ pos = pin / MAX_GPIO_REG_BITS;
+ bit = pin % MAX_GPIO_REG_BITS;
+
+ if (dir == MT_GPIO_DIR_IN) {
+ mmio_write_32(DIR_BASE + 0x10U * pos + CLR, 1U << bit);
+ } else {
+ mmio_write_32(DIR_BASE + 0x10U * pos + SET, 1U << bit);
+ }
+}
+
+static int mt_get_gpio_dir_chip(uint32_t pin)
+{
+ uint32_t pos, bit;
+ uint32_t reg;
+
+ assert(pin < MAX_GPIO_PIN);
+
+ pos = pin / MAX_GPIO_REG_BITS;
+ bit = pin % MAX_GPIO_REG_BITS;
+
+ reg = mmio_read_32(DIR_BASE + 0x10U * pos);
+ return (((reg & (1U << bit)) != 0U) ? MT_GPIO_DIR_OUT : MT_GPIO_DIR_IN);
+}
+
+static void mt_set_gpio_out_chip(uint32_t pin, int output)
+{
+ uint32_t pos, bit;
+
+ assert(pin < MAX_GPIO_PIN);
+ assert(output < MT_GPIO_OUT_MAX);
+
+ pos = pin / MAX_GPIO_REG_BITS;
+ bit = pin % MAX_GPIO_REG_BITS;
+
+ if (output == MT_GPIO_OUT_ZERO) {
+ mmio_write_32(DOUT_BASE + 0x10U * pos + CLR, 1U << bit);
+ } else {
+ mmio_write_32(DOUT_BASE + 0x10U * pos + SET, 1U << bit);
+ }
+}
+
+static int mt_get_gpio_in_chip(uint32_t pin)
+{
+ uint32_t pos, bit;
+ uint32_t reg;
+
+ assert(pin < MAX_GPIO_PIN);
+
+ pos = pin / MAX_GPIO_REG_BITS;
+ bit = pin % MAX_GPIO_REG_BITS;
+
+ reg = mmio_read_32(DIN_BASE + 0x10U * pos);
+ return (((reg & (1U << bit)) != 0U) ? 1 : 0);
+}
+
+static void mt_gpio_set_spec_pull_pupd(uint32_t pin, int enable,
+ int select)
+{
+ uintptr_t reg1;
+ uintptr_t reg2;
+ struct mt_pin_info gpio_info;
+
+ gpio_info = mt_pin_infos[pin];
+ uint32_t bit = gpio_info.bit;
+
+ reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+ reg2 = reg1 + (gpio_info.base & 0xf0);
+ if (enable == MT_GPIO_PULL_ENABLE) {
+ mmio_write_32(reg2 + SET, (1U << bit));
+ if (select == MT_GPIO_PULL_DOWN) {
+ mmio_write_32(reg1 + SET, (1U << bit));
+ } else {
+ mmio_write_32(reg1 + CLR, (1U << bit));
+ }
+ } else {
+ mmio_write_32(reg2 + CLR, (1U << bit));
+ mmio_write_32((reg2 + 0x010U) + CLR, (1U << bit));
+ }
+}
+
+static void mt_gpio_set_pull_pu_pd(uint32_t pin, int enable,
+ int select)
+{
+ uintptr_t reg1;
+ uintptr_t reg2;
+ struct mt_pin_info gpio_info;
+
+ gpio_info = mt_pin_infos[pin];
+ uint32_t bit = gpio_info.bit;
+
+ reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+ reg2 = reg1 - (gpio_info.base & 0xf0);
+
+ if (enable == MT_GPIO_PULL_ENABLE) {
+ if (select == MT_GPIO_PULL_DOWN) {
+ mmio_write_32(reg1 + CLR, (1U << bit));
+ mmio_write_32(reg2 + SET, (1U << bit));
+ } else {
+ mmio_write_32(reg2 + CLR, (1U << bit));
+ mmio_write_32(reg1 + SET, (1U << bit));
+ }
+ } else {
+ mmio_write_32(reg1 + CLR, (1U << bit));
+ mmio_write_32(reg2 + CLR, (1U << bit));
+ }
+}
+
+static void mt_gpio_set_pull_chip(uint32_t pin, int enable,
+ int select)
+{
+ struct mt_pin_info gpio_info;
+
+ gpio_info = mt_pin_infos[pin];
+ if (gpio_info.flag) {
+ mt_gpio_set_spec_pull_pupd(pin, enable, select);
+ } else {
+ mt_gpio_set_pull_pu_pd(pin, enable, select);
+ }
+}
+
+static int mt_gpio_get_spec_pull_pupd(uint32_t pin)
+{
+ uintptr_t reg1;
+ uintptr_t reg2;
+ uint32_t r0;
+ uint32_t r1;
+
+ struct mt_pin_info gpio_info;
+
+ gpio_info = mt_pin_infos[pin];
+ uint32_t bit = gpio_info.bit;
+
+ reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+ reg2 = reg1 + (gpio_info.base & 0xf0);
+
+ r0 = (mmio_read_32(reg2) >> bit) & 1U;
+ r1 = (mmio_read_32(reg2 + 0x010) >> bit) & 1U;
+ if (r0 == 0U && r1 == 0U) {
+ return MT_GPIO_PULL_NONE;
+ } else {
+ if (mmio_read_32(reg1) & (1U << bit)) {
+ return MT_GPIO_PULL_DOWN;
+ } else {
+ return MT_GPIO_PULL_UP;
+ }
+ }
+}
+
+static int mt_gpio_get_pull_pu_pd(uint32_t pin)
+{
+ uintptr_t reg1;
+ uintptr_t reg2;
+ uint32_t pu;
+ uint32_t pd;
+
+ struct mt_pin_info gpio_info;
+
+ gpio_info = mt_pin_infos[pin];
+ uint32_t bit = gpio_info.bit;
+
+ reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+ reg2 = reg1 - (gpio_info.base & 0xf0);
+ pu = (mmio_read_32(reg1) >> bit) & 1U;
+ pd = (mmio_read_32(reg2) >> bit) & 1U;
+ if (pu == 1U) {
+ return MT_GPIO_PULL_UP;
+ } else if (pd == 1U) {
+ return MT_GPIO_PULL_DOWN;
+ } else {
+ return MT_GPIO_PULL_NONE;
+ }
+}
+
+static int mt_gpio_get_pull_chip(uint32_t pin)
+{
+ struct mt_pin_info gpio_info;
+
+ gpio_info = mt_pin_infos[pin];
+ if (gpio_info.flag) {
+ return mt_gpio_get_spec_pull_pupd(pin);
+ } else {
+ return mt_gpio_get_pull_pu_pd(pin);
+ }
+}
+
+static void mt_set_gpio_pull_select_chip(uint32_t pin, int sel)
+{
+ assert(pin < MAX_GPIO_PIN);
+
+ if (sel == MT_GPIO_PULL_NONE) {
+ mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_DISABLE, MT_GPIO_PULL_DOWN);
+ } else if (sel == MT_GPIO_PULL_UP) {
+ mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_ENABLE, MT_GPIO_PULL_UP);
+ } else if (sel == MT_GPIO_PULL_DOWN) {
+ mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_ENABLE, MT_GPIO_PULL_DOWN);
+ }
+}
+
+/* get pull-up or pull-down, regardless of resistor value */
+static int mt_get_gpio_pull_select_chip(uint32_t pin)
+{
+ assert(pin < MAX_GPIO_PIN);
+
+ return mt_gpio_get_pull_chip(pin);
+}
+
+static void mt_set_gpio_dir(int gpio, int direction)
+{
+ mt_set_gpio_dir_chip((uint32_t)gpio, direction);
+}
+
+static int mt_get_gpio_dir(int gpio)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ return mt_get_gpio_dir_chip(pin);
+}
+
+static void mt_set_gpio_pull(int gpio, int pull)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ mt_set_gpio_pull_select_chip(pin, pull);
+}
+
+static int mt_get_gpio_pull(int gpio)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ return mt_get_gpio_pull_select_chip(pin);
+}
+
+static void mt_set_gpio_out(int gpio, int value)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ mt_set_gpio_out_chip(pin, value);
+}
+
+static int mt_get_gpio_in(int gpio)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ return mt_get_gpio_in_chip(pin);
+}
+
+const gpio_ops_t mtgpio_ops = {
+ .get_direction = mt_get_gpio_dir,
+ .set_direction = mt_set_gpio_dir,
+ .get_value = mt_get_gpio_in,
+ .set_value = mt_set_gpio_out,
+ .set_pull = mt_set_gpio_pull,
+ .get_pull = mt_get_gpio_pull,
+};
+
+void mt_gpio_init(void)
+{
+ gpio_init(&mtgpio_ops);
+}
diff --git a/plat/mediatek/common/drivers/gpio/mtgpio_common.h b/plat/mediatek/common/drivers/gpio/mtgpio_common.h
new file mode 100644
index 0000000..bf51055
--- /dev/null
+++ b/plat/mediatek/common/drivers/gpio/mtgpio_common.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_GPIO_COMMON_H
+#define MT_GPIO_COMMON_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <plat/common/common_def.h>
+
+/* Error Code No. */
+#define RSUCCESS 0
+#define ERACCESS 1
+#define ERINVAL 2
+#define ERWRAPPER 3
+#define MAX_GPIO_PIN MT_GPIO_BASE_MAX
+
+/* GPIO MODE CONTROL VALUE*/
+typedef enum {
+ GPIO_MODE_UNSUPPORTED = -1,
+ GPIO_MODE_GPIO = 0,
+ GPIO_MODE_00 = 0,
+ GPIO_MODE_01,
+ GPIO_MODE_02,
+ GPIO_MODE_03,
+ GPIO_MODE_04,
+ GPIO_MODE_05,
+ GPIO_MODE_06,
+ GPIO_MODE_07,
+
+ GPIO_MODE_MAX,
+ GPIO_MODE_DEFAULT = GPIO_MODE_00,
+} GPIO_MODE;
+
+/* GPIO DIRECTION */
+typedef enum {
+ MT_GPIO_DIR_UNSUPPORTED = -1,
+ MT_GPIO_DIR_OUT = 0,
+ MT_GPIO_DIR_IN = 1,
+ MT_GPIO_DIR_MAX,
+ MT_GPIO_DIR_DEFAULT = MT_GPIO_DIR_IN,
+} GPIO_DIR;
+
+/* GPIO PULL ENABLE*/
+typedef enum {
+ MT_GPIO_PULL_EN_UNSUPPORTED = -1,
+ MT_GPIO_PULL_DISABLE = 0,
+ MT_GPIO_PULL_ENABLE = 1,
+ MT_GPIO_PULL_ENABLE_R0 = 2,
+ MT_GPIO_PULL_ENABLE_R1 = 3,
+ MT_GPIO_PULL_ENABLE_R0R1 = 4,
+
+ MT_GPIO_PULL_EN_MAX,
+ MT_GPIO_PULL_EN_DEFAULT = MT_GPIO_PULL_ENABLE,
+} GPIO_PULL_EN;
+
+/* GPIO PULL-UP/PULL-DOWN*/
+typedef enum {
+ MT_GPIO_PULL_UNSUPPORTED = -1,
+ MT_GPIO_PULL_NONE = 0,
+ MT_GPIO_PULL_UP = 1,
+ MT_GPIO_PULL_DOWN = 2,
+ MT_GPIO_PULL_MAX,
+ MT_GPIO_PULL_DEFAULT = MT_GPIO_PULL_DOWN
+} GPIO_PULL;
+
+/* GPIO OUTPUT */
+typedef enum {
+ MT_GPIO_OUT_UNSUPPORTED = -1,
+ MT_GPIO_OUT_ZERO = 0,
+ MT_GPIO_OUT_ONE = 1,
+
+ MT_GPIO_OUT_MAX,
+ MT_GPIO_OUT_DEFAULT = MT_GPIO_OUT_ZERO,
+ MT_GPIO_DATA_OUT_DEFAULT = MT_GPIO_OUT_ZERO, /*compatible with DCT*/
+} GPIO_OUT;
+
+/* GPIO INPUT */
+typedef enum {
+ MT_GPIO_IN_UNSUPPORTED = -1,
+ MT_GPIO_IN_ZERO = 0,
+ MT_GPIO_IN_ONE = 1,
+
+ MT_GPIO_IN_MAX,
+} GPIO_IN;
+
+#define PIN(_id, _flag, _bit, _base, _offset) { \
+ .id = _id, \
+ .flag = _flag, \
+ .bit = _bit, \
+ .base = _base, \
+ .offset = _offset, \
+ }
+
+struct mt_pin_info {
+ uint8_t id;
+ uint8_t flag;
+ uint8_t bit;
+ uint16_t base;
+ uint16_t offset;
+};
+
+void mt_gpio_init(void);
+uintptr_t mt_gpio_find_reg_addr(uint32_t pin);
+#endif /* MT_GPIO_COMMON_H */
diff --git a/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init_v2.c b/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init_v2.c
index fca6913..d9a79c4 100644
--- a/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init_v2.c
+++ b/plat/mediatek/common/drivers/pmic_wrap/pmic_wrap_init_v2.c
@@ -26,12 +26,30 @@
while (retry != 0) {
udelay(WAIT_IDLE_POLLING_DELAY_US);
reg_rdata = mmio_read_32((uintptr_t)wacs_register);
- if (GET_WACS_FSM(reg_rdata) == SWINF_FSM_IDLE) {
+ /* if last read command timeout,clear vldclr bit
+ * read command state machine:FSM_REQ-->wfdle-->WFVLDCLR;
+ * write:FSM_REQ-->idle
+ */
+ switch (GET_WACS_FSM(reg_rdata)) {
+ case SWINF_FSM_WFVLDCLR:
+ mmio_write_32((uintptr_t)&mtk_pwrap->wacs2_vldclr, 0x1);
+ INFO("WACS_FSM = SWINF_FSM_WFVLDCLR\n");
+ break;
+ case SWINF_FSM_WFDLE:
+ INFO("WACS_FSM = SWINF_FSM_WFDLE\n");
+ break;
+ case SWINF_FSM_REQ:
+ INFO("WACS_FSM = SWINF_FSM_REQ\n");
+ break;
+ case SWINF_FSM_IDLE:
+ goto done;
+ default:
break;
}
retry--;
};
+done:
if (retry == 0) {
/* timeout */
return E_PWR_WAIT_IDLE_TIMEOUT;
diff --git a/plat/mediatek/mt8192/drivers/rtc/rtc.c b/plat/mediatek/common/drivers/rtc/rtc_mt6359p.c
similarity index 100%
rename from plat/mediatek/mt8192/drivers/rtc/rtc.c
rename to plat/mediatek/common/drivers/rtc/rtc_mt6359p.c
diff --git a/plat/mediatek/common/drivers/rtc/rtc_mt6359p.h b/plat/mediatek/common/drivers/rtc/rtc_mt6359p.h
new file mode 100644
index 0000000..04726e3
--- /dev/null
+++ b/plat/mediatek/common/drivers/rtc/rtc_mt6359p.h
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RTC_MT6359P_H
+#define RTC_MT6359P_H
+
+/* RTC registers */
+enum {
+ RTC_BBPU = 0x0588,
+ RTC_IRQ_STA = 0x058A,
+ RTC_IRQ_EN = 0x058C,
+ RTC_CII_EN = 0x058E
+};
+
+enum {
+ RTC_AL_SEC = 0x05A0,
+ RTC_AL_MIN = 0x05A2,
+ RTC_AL_HOU = 0x05A4,
+ RTC_AL_DOM = 0x05A6,
+ RTC_AL_DOW = 0x05A8,
+ RTC_AL_MTH = 0x05AA,
+ RTC_AL_YEA = 0x05AC,
+ RTC_AL_MASK = 0x0590
+};
+
+enum {
+ RTC_OSC32CON = 0x05AE,
+ RTC_CON = 0x05C4,
+ RTC_WRTGR = 0x05C2
+};
+
+enum {
+ RTC_POWERKEY1 = 0x05B0,
+ RTC_POWERKEY2 = 0x05B2
+};
+
+enum {
+ RTC_POWERKEY1_KEY = 0xA357,
+ RTC_POWERKEY2_KEY = 0x67D2
+};
+
+enum {
+ RTC_PDN1 = 0x05B4,
+ RTC_PDN2 = 0x05B6,
+ RTC_SPAR0 = 0x05B8,
+ RTC_SPAR1 = 0x05BA,
+ RTC_PROT = 0x05BC,
+ RTC_DIFF = 0x05BE,
+ RTC_CALI = 0x05C0
+};
+
+enum {
+ RTC_OSC32CON_UNLOCK1 = 0x1A57,
+ RTC_OSC32CON_UNLOCK2 = 0x2B68
+};
+
+enum {
+ RTC_LPD_EN = 0x0406,
+ RTC_LPD_RST = 0x040E
+};
+
+enum {
+ RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13,
+ RTC_LPD_OPT_EOSC_LPD = 1U << 13,
+ RTC_LPD_OPT_XOSC_LPD = 2U << 13,
+ RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13,
+};
+
+#define RTC_LPD_OPT_MASK (3U << 13)
+
+enum {
+ RTC_PROT_UNLOCK1 = 0x586A,
+ RTC_PROT_UNLOCK2 = 0x9136
+};
+
+enum {
+ RTC_BBPU_PWREN = 1U << 0,
+ RTC_BBPU_SPAR_SW = 1U << 1,
+ RTC_BBPU_RESET_SPAR = 1U << 2,
+ RTC_BBPU_RESET_ALARM = 1U << 3,
+ RTC_BBPU_CLRPKY = 1U << 4,
+ RTC_BBPU_RELOAD = 1U << 5,
+ RTC_BBPU_CBUSY = 1U << 6
+};
+
+enum {
+ RTC_AL_MASK_SEC = 1U << 0,
+ RTC_AL_MASK_MIN = 1U << 1,
+ RTC_AL_MASK_HOU = 1U << 2,
+ RTC_AL_MASK_DOM = 1U << 3,
+ RTC_AL_MASK_DOW = 1U << 4,
+ RTC_AL_MASK_MTH = 1U << 5,
+ RTC_AL_MASK_YEA = 1U << 6
+};
+
+enum {
+ RTC_BBPU_AUTO_PDN_SEL = 1U << 6,
+ RTC_BBPU_2SEC_CK_SEL = 1U << 7,
+ RTC_BBPU_2SEC_EN = 1U << 8,
+ RTC_BBPU_2SEC_MODE = 0x3 << 9,
+ RTC_BBPU_2SEC_STAT_CLEAR = 1U << 11,
+ RTC_BBPU_2SEC_STAT_STA = 1U << 12
+};
+
+enum {
+ RTC_BBPU_KEY = 0x43 << 8
+};
+
+enum {
+ RTC_EMBCK_SRC_SEL = 1 << 8,
+ RTC_EMBCK_SEL_MODE = 3 << 6,
+ RTC_XOSC32_ENB = 1 << 5,
+ RTC_REG_XOSC32_ENB = 1 << 15
+};
+
+enum {
+ RTC_K_EOSC_RSV_0 = 1 << 8,
+ RTC_K_EOSC_RSV_1 = 1 << 9,
+ RTC_K_EOSC_RSV_2 = 1 << 10
+};
+
+enum {
+ RTC_RG_EOSC_CALI_TD_1SEC = 3 << 5,
+ RTC_RG_EOSC_CALI_TD_2SEC = 4 << 5,
+ RTC_RG_EOSC_CALI_TD_4SEC = 5 << 5,
+ RTC_RG_EOSC_CALI_TD_8SEC = 6 << 5,
+ RTC_RG_EOSC_CALI_TD_16SEC = 7 << 5,
+ RTC_RG_EOSC_CALI_TD_MASK = 7 << 5
+};
+
+/* PMIC TOP Register Definition */
+enum {
+ PMIC_RG_TOP_CON = 0x0020,
+ PMIC_RG_TOP_CKPDN_CON1 = 0x0112,
+ PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114,
+ PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116,
+ PMIC_RG_TOP_CKSEL_CON0 = 0x0118,
+ PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A,
+ PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C
+};
+
+/* PMIC SCK Register Definition */
+enum {
+ PMIC_RG_SCK_TOP_CKPDN_CON0 = 0x0514,
+ PMIC_RG_SCK_TOP_CKPDN_CON0_SET = 0x0516,
+ PMIC_RG_SCK_TOP_CKPDN_CON0_CLR = 0x0518,
+ PMIC_RG_EOSC_CALI_CON0 = 0x53A
+};
+
+enum {
+ PMIC_EOSC_CALI_START_ADDR = 0x53A
+};
+
+enum {
+ PMIC_EOSC_CALI_START_MASK = 0x1,
+ PMIC_EOSC_CALI_START_SHIFT = 0
+};
+
+/* PMIC DCXO Register Definition */
+enum {
+ PMIC_RG_DCXO_CW00 = 0x0788,
+ PMIC_RG_DCXO_CW02 = 0x0790,
+ PMIC_RG_DCXO_CW08 = 0x079C,
+ PMIC_RG_DCXO_CW09 = 0x079E,
+ PMIC_RG_DCXO_CW09_CLR = 0x07A2,
+ PMIC_RG_DCXO_CW10 = 0x07A4,
+ PMIC_RG_DCXO_CW12 = 0x07A8,
+ PMIC_RG_DCXO_CW13 = 0x07AA,
+ PMIC_RG_DCXO_CW15 = 0x07AE,
+ PMIC_RG_DCXO_CW19 = 0x07B6,
+};
+
+enum {
+ PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK = 0x1,
+ PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT = 1,
+ PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK = 0x1,
+ PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT = 3,
+ PMIC_RG_RTC_EOSC32_CK_PDN_MASK = 0x1,
+ PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT = 2,
+ PMIC_RG_EOSC_CALI_TD_MASK = 0x7,
+ PMIC_RG_EOSC_CALI_TD_SHIFT = 5,
+ PMIC_RG_XO_EN32K_MAN_MASK = 0x1,
+ PMIC_RG_XO_EN32K_MAN_SHIFT = 0
+};
+
+/* external API */
+uint16_t RTC_Read(uint32_t addr);
+void RTC_Write(uint32_t addr, uint16_t data);
+int32_t rtc_busy_wait(void);
+int32_t RTC_Write_Trigger(void);
+int32_t Writeif_unlock(void);
+void rtc_power_off_sequence(void);
+
+#endif /* RTC_MT6359P_H */
diff --git a/plat/mediatek/mt8192/drivers/timer/mt_timer.c b/plat/mediatek/common/drivers/timer/mt_timer.c
similarity index 100%
rename from plat/mediatek/mt8192/drivers/timer/mt_timer.c
rename to plat/mediatek/common/drivers/timer/mt_timer.c
diff --git a/plat/mediatek/mt8192/drivers/timer/mt_timer.h b/plat/mediatek/common/drivers/timer/mt_timer.h
similarity index 100%
rename from plat/mediatek/mt8192/drivers/timer/mt_timer.h
rename to plat/mediatek/common/drivers/timer/mt_timer.h
diff --git a/plat/mediatek/mt8192/drivers/uart/uart.h b/plat/mediatek/common/drivers/uart/uart.h
similarity index 100%
rename from plat/mediatek/mt8192/drivers/uart/uart.h
rename to plat/mediatek/common/drivers/uart/uart.h
diff --git a/plat/mediatek/common/lpm/mt_lp_rm.c b/plat/mediatek/common/lpm/mt_lp_rm.c
new file mode 100644
index 0000000..f3148fe
--- /dev/null
+++ b/plat/mediatek/common/lpm/mt_lp_rm.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mt_lp_rm.h>
+#include <stddef.h>
+
+struct platform_mt_resource_manager {
+ unsigned int count;
+ struct mt_resource_manager *plat_rm;
+};
+
+static struct platform_mt_resource_manager plat_mt_rm;
+
+int mt_lp_rm_register(struct mt_resource_manager *rm)
+{
+ unsigned int i;
+ struct mt_resource_constraint *const *rc;
+
+ if ((rm == NULL) || (rm->consts == NULL) ||
+ (plat_mt_rm.plat_rm != NULL)) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ for (i = 0U, rc = rm->consts; *rc != NULL; i++, rc++) {
+ if ((*rc)->init != NULL) {
+ (*rc)->init();
+ }
+ }
+
+ plat_mt_rm.plat_rm = rm;
+ plat_mt_rm.count = i;
+
+ return MT_RM_STATUS_OK;
+}
+
+int mt_lp_rm_reset_constraint(int idx, unsigned int cpuid, int stateid)
+{
+ struct mt_resource_constraint const *rc = NULL;
+
+ if ((plat_mt_rm.plat_rm == NULL) || (idx < 0) ||
+ (idx >= plat_mt_rm.count)) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ rc = plat_mt_rm.plat_rm->consts[idx];
+
+ if ((rc == NULL) || (rc->reset == NULL)) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ return rc->reset(cpuid, stateid);
+}
+
+int mt_lp_rm_find_and_run_constraint(int idx, unsigned int cpuid,
+ int stateid, void *priv)
+{
+ int i, res = MT_RM_STATUS_BAD;
+ struct mt_resource_constraint *const *rc;
+ struct mt_resource_manager *rm = plat_mt_rm.plat_rm;
+
+ if ((rm == NULL) || (idx < 0) || (idx >= plat_mt_rm.count)) {
+ return res;
+ }
+
+ /* If subsys clk/mtcmos is on, add block-resource-off flag */
+ if (rm->update != NULL) {
+ res = rm->update(rm->consts, stateid, priv);
+ if (res != 0) {
+ return res;
+ }
+ }
+
+ for (i = idx, rc = (rm->consts + idx); *rc != NULL; i++, rc++) {
+ if (((*rc)->is_valid != NULL) &&
+ ((*rc)->is_valid(cpuid, stateid))) {
+ if (((*rc)->run != NULL) &&
+ ((*rc)->run(cpuid, stateid) == 0)) {
+ res = i;
+ break;
+ }
+ }
+ }
+
+ return res;
+}
+
+int mt_lp_rm_do_update(int stateid, int type, void const *p)
+{
+ int res = MT_RM_STATUS_BAD;
+ struct mt_resource_constraint *const *rc;
+ struct mt_resource_manager *rm = plat_mt_rm.plat_rm;
+
+ if (rm == NULL) {
+ return res;
+ }
+
+ for (rc = rm->consts; *rc != NULL; rc++) {
+ if ((*rc)->update != NULL) {
+ res = (*rc)->update(stateid, type, p);
+ if (res != MT_RM_STATUS_OK) {
+ break;
+ }
+ }
+ }
+
+ return res;
+}
diff --git a/plat/mediatek/common/lpm/mt_lp_rm.h b/plat/mediatek/common/lpm/mt_lp_rm.h
new file mode 100644
index 0000000..39759f1
--- /dev/null
+++ b/plat/mediatek/common/lpm/mt_lp_rm.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_LP_RM_H
+#define MT_LP_RM_H
+
+#include <stdbool.h>
+
+#define MT_RM_STATUS_OK 0
+#define MT_RM_STATUS_BAD -1
+
+enum PLAT_MT_LPM_RC_TYPE {
+ PLAT_RC_UPDATE_CONDITION,
+ PLAT_RC_UPDATE_REMAIN_IRQS
+};
+
+struct mt_resource_constraint {
+ int level;
+ int (*init)(void);
+ bool (*is_valid)(unsigned int cpu, int stateid);
+ int (*update)(int stateid, int type, const void *p);
+ int (*run)(unsigned int cpu, int stateid);
+ int (*reset)(unsigned int cpu, int stateid);
+ unsigned int (*allow)(int stateid);
+};
+
+struct mt_resource_manager {
+ int (*update)(struct mt_resource_constraint **con,
+ int stateid, void *priv);
+ struct mt_resource_constraint **consts;
+};
+
+extern int mt_lp_rm_register(struct mt_resource_manager *rm);
+extern int mt_lp_rm_find_and_run_constraint(int idx, unsigned int cpuid,
+ int stateid, void *priv);
+extern int mt_lp_rm_reset_constraint(int constraint_id, unsigned int cpuid,
+ int stateid);
+extern int mt_lp_rm_do_update(int stateid, int type, void const *p);
+#endif /* MT_LP_RM_H */
diff --git a/plat/mediatek/common/mtk_cirq.c b/plat/mediatek/common/mtk_cirq.c
new file mode 100644
index 0000000..de37986
--- /dev/null
+++ b/plat/mediatek/common/mtk_cirq.c
@@ -0,0 +1,551 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/arm/gic_common.h>
+#include <lib/mmio.h>
+
+#include <mt_gic_v3.h>
+#include <mtk_cirq.h>
+
+static struct cirq_events cirq_all_events = {
+ .spi_start = CIRQ_SPI_START,
+};
+static uint32_t already_cloned;
+/*
+ * mt_irq_mask_restore: restore all interrupts
+ * @mask: pointer to struct mtk_irq_mask for storing the original mask value.
+ * Return 0 for success; return negative values for failure.
+ * (This is ONLY used for the idle current measurement by the factory mode.)
+ */
+int mt_irq_mask_restore(struct mtk_irq_mask *mask)
+{
+ if (mask == NULL) {
+ return -1;
+ }
+ if (mask->header != IRQ_MASK_HEADER) {
+ return -1;
+ }
+ if (mask->footer != IRQ_MASK_FOOTER) {
+ return -1;
+ }
+
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x4),
+ mask->mask1);
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x8),
+ mask->mask2);
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0xc),
+ mask->mask3);
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x10),
+ mask->mask4);
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x14),
+ mask->mask5);
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x18),
+ mask->mask6);
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x1c),
+ mask->mask7);
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x20),
+ mask->mask8);
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x24),
+ mask->mask9);
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x28),
+ mask->mask10);
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x2c),
+ mask->mask11);
+ mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x30),
+ mask->mask12);
+ /* make sure dist changes happen */
+ dsb();
+
+ return 0;
+}
+
+/*
+ * mt_irq_mask_all: disable all interrupts
+ * @mask: pointer to struct mtk_irq_mask for storing the original mask value.
+ * Return 0 for success; return negative values for failure.
+ * (This is ONLY used for the idle current measurement by the factory mode.)
+ */
+int mt_irq_mask_all(struct mtk_irq_mask *mask)
+{
+ if (mask != NULL) {
+ /* for SPI */
+ mask->mask1 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0x4));
+ mask->mask2 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0x8));
+ mask->mask3 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0xc));
+ mask->mask4 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0x10));
+ mask->mask5 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0x14));
+ mask->mask6 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0x18));
+ mask->mask7 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0x1c));
+ mask->mask8 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0x20));
+ mask->mask9 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0x24));
+ mask->mask10 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0x28));
+ mask->mask11 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0x2c));
+ mask->mask12 = mmio_read_32((BASE_GICD_BASE +
+ GICD_ISENABLER + 0x30));
+
+ /* for SPI */
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x4),
+ 0xFFFFFFFF);
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x8),
+ 0xFFFFFFFF);
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0xC),
+ 0xFFFFFFFF);
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x10),
+ 0xFFFFFFFF);
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x14),
+ 0xFFFFFFFF);
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x18),
+ 0xFFFFFFFF);
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x1C),
+ 0xFFFFFFFF);
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x20),
+ 0xFFFFFFFF);
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x24),
+ 0xFFFFFFFF);
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x28),
+ 0xFFFFFFFF);
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x2c),
+ 0xFFFFFFFF);
+ mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x30),
+ 0xFFFFFFFF);
+ /* make sure distributor changes happen */
+ dsb();
+
+ mask->header = IRQ_MASK_HEADER;
+ mask->footer = IRQ_MASK_FOOTER;
+
+ return 0;
+ } else {
+ return -1;
+ }
+}
+
+static uint32_t mt_irq_get_pol(uint32_t irq)
+{
+#ifdef CIRQ_WITH_POLARITY
+ uint32_t reg;
+ uint32_t base = INT_POL_CTL0;
+
+ if (irq < 32U) {
+ return 0;
+ }
+
+ reg = ((irq - 32U) / 32U);
+
+ return mmio_read_32(base + reg * 4U);
+#else
+ return 0;
+#endif
+}
+
+unsigned int mt_irq_get_sens(unsigned int irq)
+{
+ unsigned int config;
+
+ /*
+ * 2'b10 edge
+ * 2'b01 level
+ */
+ config = mmio_read_32(MT_GIC_BASE + GICD_ICFGR + (irq / 16U) * 4U);
+ config = (config >> (irq % 16U) * 2U) & 0x3;
+
+ return config;
+}
+
+static void collect_all_wakeup_events(void)
+{
+ unsigned int i;
+ uint32_t gic_irq;
+ uint32_t cirq;
+ uint32_t cirq_reg;
+ uint32_t cirq_offset;
+ uint32_t mask;
+ uint32_t pol_mask;
+ uint32_t irq_offset;
+ uint32_t irq_mask;
+
+ if ((cirq_all_events.wakeup_events == NULL) ||
+ cirq_all_events.num_of_events == 0U) {
+ return;
+ }
+
+ for (i = 0U; i < cirq_all_events.num_of_events; i++) {
+ if (cirq_all_events.wakeup_events[i] > 0U) {
+ gic_irq = cirq_all_events.wakeup_events[i];
+ cirq = gic_irq - cirq_all_events.spi_start - 32U;
+ cirq_reg = cirq / 32U;
+ cirq_offset = cirq % 32U;
+ mask = 0x1 << cirq_offset;
+ irq_offset = gic_irq % 32U;
+ irq_mask = 0x1 << irq_offset;
+ /*
+ * CIRQ default masks all
+ */
+ cirq_all_events.table[cirq_reg].mask |= mask;
+ /*
+ * CIRQ default pol is low
+ */
+ pol_mask = mt_irq_get_pol(
+ cirq_all_events.wakeup_events[i])
+ & irq_mask;
+ /*
+ * 0 means rising
+ */
+ if (pol_mask == 0U) {
+ cirq_all_events.table[cirq_reg].pol |= mask;
+ }
+ /*
+ * CIRQ could monitor edge/level trigger
+ * cirq register (0: edge, 1: level)
+ */
+ if (mt_irq_get_sens(cirq_all_events.wakeup_events[i])
+ == SENS_EDGE) {
+ cirq_all_events.table[cirq_reg].sen |= mask;
+ }
+
+ cirq_all_events.table[cirq_reg].used = 1U;
+ cirq_all_events.table[cirq_reg].reg_num = cirq_reg;
+ }
+ }
+}
+
+/*
+ * mt_cirq_set_pol: Set the polarity for the specified SYS_CIRQ number.
+ * @cirq_num: the SYS_CIRQ number to set
+ * @pol: polarity to set
+ * @return:
+ * 0: set pol success
+ * -1: cirq num is out of range
+ */
+#ifdef CIRQ_WITH_POLARITY
+static int mt_cirq_set_pol(uint32_t cirq_num, uint32_t pol)
+{
+ uint32_t base;
+ uint32_t bit = 1U << (cirq_num % 32U);
+
+ if (cirq_num >= CIRQ_IRQ_NUM) {
+ return -1;
+ }
+
+ if (pol == MT_CIRQ_POL_NEG) {
+ base = (cirq_num / 32U) * 4U + CIRQ_POL_CLR_BASE;
+ } else if (pol == MT_CIRQ_POL_POS) {
+ base = (cirq_num / 32U) * 4U + CIRQ_POL_SET_BASE;
+ } else {
+ return -1;
+ }
+
+ mmio_write_32(base, bit);
+ return 0;
+}
+#endif
+
+/*
+ * mt_cirq_mask: Mask the specified SYS_CIRQ.
+ * @cirq_num: the SYS_CIRQ number to mask
+ * @return:
+ * 0: mask success
+ * -1: cirq num is out of range
+ */
+static int mt_cirq_mask(uint32_t cirq_num)
+{
+ uint32_t bit = 1U << (cirq_num % 32U);
+
+ if (cirq_num >= CIRQ_IRQ_NUM) {
+ return -1;
+ }
+
+ mmio_write_32((cirq_num / 32U) * 4U + CIRQ_MASK_SET_BASE, bit);
+
+ return 0;
+}
+
+/*
+ * mt_cirq_unmask: Unmask the specified SYS_CIRQ.
+ * @cirq_num: the SYS_CIRQ number to unmask
+ * @return:
+ * 0: umask success
+ * -1: cirq num is out of range
+ */
+static int mt_cirq_unmask(uint32_t cirq_num)
+{
+ uint32_t bit = 1U << (cirq_num % 32U);
+
+ if (cirq_num >= CIRQ_IRQ_NUM) {
+ return -1;
+ }
+
+ mmio_write_32((cirq_num / 32U) * 4U + CIRQ_MASK_CLR_BASE, bit);
+
+ return 0;
+}
+
+uint32_t mt_irq_get_en(uint32_t irq)
+{
+ uint32_t addr, st, val;
+
+ addr = BASE_GICD_BASE + GICD_ISENABLER + (irq / 32U) * 4U;
+ st = mmio_read_32(addr);
+
+ val = (st >> (irq % 32U)) & 1U;
+
+ return val;
+}
+
+static void __cirq_fast_clone(void)
+{
+ struct cirq_reg *reg;
+ unsigned int i;
+
+ for (i = 0U; i < CIRQ_REG_NUM ; ++i) {
+ uint32_t cirq_bit;
+
+ reg = &cirq_all_events.table[i];
+
+ if (reg->used == 0U) {
+ continue;
+ }
+
+ mmio_write_32(CIRQ_SENS_CLR_BASE + (reg->reg_num * 4U),
+ reg->sen);
+
+ for (cirq_bit = 0U; cirq_bit < 32U; ++cirq_bit) {
+ uint32_t val, cirq_id;
+ uint32_t gic_id;
+#ifdef CIRQ_WITH_POLARITY
+ uint32_t gic_bit, pol;
+#endif
+ uint32_t en;
+
+ val = ((1U << cirq_bit) & reg->mask);
+
+ if (val == 0U) {
+ continue;
+ }
+
+ cirq_id = (reg->reg_num << 5U) + cirq_bit;
+ gic_id = CIRQ_TO_IRQ_NUM(cirq_id);
+#ifdef CIRQ_WITH_POLARITY
+ gic_bit = (0x1U << ((gic_id - 32U) % 32U));
+ pol = mt_irq_get_pol(gic_id) & gic_bit;
+ if (pol != 0U) {
+ mt_cirq_set_pol(cirq_id, MT_CIRQ_POL_NEG);
+ } else {
+ mt_cirq_set_pol(cirq_id, MT_CIRQ_POL_POS);
+ }
+#endif
+ en = mt_irq_get_en(gic_id);
+ if (en == 1U) {
+ mt_cirq_unmask(cirq_id);
+ } else {
+ mt_cirq_mask(cirq_id);
+ }
+ }
+ }
+}
+
+static void cirq_fast_clone(void)
+{
+ if (already_cloned == 0U) {
+ collect_all_wakeup_events();
+ already_cloned = 1U;
+ }
+ __cirq_fast_clone();
+}
+
+void set_wakeup_sources(uint32_t *list, uint32_t num_of_events)
+{
+ cirq_all_events.num_of_events = num_of_events;
+ cirq_all_events.wakeup_events = list;
+}
+/*
+ * mt_cirq_clone_gic: Copy the setting from GIC to SYS_CIRQ
+ */
+void mt_cirq_clone_gic(void)
+{
+ cirq_fast_clone();
+}
+
+uint32_t mt_irq_get_pending_vec(uint32_t start_irq)
+{
+ uint32_t base = 0U;
+ uint32_t pending_vec = 0U;
+ uint32_t reg = start_irq / 32U;
+ uint32_t LSB_num, MSB_num;
+ uint32_t LSB_vec, MSB_vec;
+
+ base = BASE_GICD_BASE;
+
+ /* if start_irq is not aligned 32, do some assembling */
+ MSB_num = start_irq % 32U;
+ if (MSB_num != 0U) {
+ LSB_num = 32U - MSB_num;
+ LSB_vec = mmio_read_32(base + GICD_ISPENDR +
+ reg * 4U) >> MSB_num;
+ MSB_vec = mmio_read_32(base + GICD_ISPENDR +
+ (reg + 1U) * 4U) << LSB_num;
+ pending_vec = MSB_vec | LSB_vec;
+ } else {
+ pending_vec = mmio_read_32(base + GICD_ISPENDR + reg * 4);
+ }
+
+ return pending_vec;
+}
+
+static int mt_cirq_get_mask_vec(unsigned int i)
+{
+ return mmio_read_32((i * 4U) + CIRQ_MASK_BASE);
+}
+
+/*
+ * mt_cirq_ack_all: Ack all the interrupt on SYS_CIRQ
+ */
+void mt_cirq_ack_all(void)
+{
+ uint32_t ack_vec, pend_vec, mask_vec;
+ unsigned int i;
+
+ for (i = 0; i < CIRQ_CTRL_REG_NUM; i++) {
+ /*
+ * if a irq is pending & not masked, don't ack it
+ * , since cirq start irq might not be 32 aligned with gic,
+ * need an exotic API to get proper vector of pending irq
+ */
+ pend_vec = mt_irq_get_pending_vec(CIRQ_SPI_START
+ + (i + 1U) * 32U);
+ mask_vec = mt_cirq_get_mask_vec(i);
+ /* those should be acked are: "not (pending & not masked)",
+ */
+ ack_vec = (~pend_vec) | mask_vec;
+ mmio_write_32(CIRQ_ACK_BASE + (i * 4U), ack_vec);
+ }
+
+ /*
+ * make sure all cirq setting take effect
+ * before doing other things
+ */
+ dsb();
+}
+/*
+ * mt_cirq_enable: Enable SYS_CIRQ
+ */
+void mt_cirq_enable(void)
+{
+ uint32_t st;
+
+ /* level only */
+ mt_cirq_ack_all();
+
+ st = mmio_read_32(CIRQ_CON);
+ /*
+ * CIRQ could monitor edge/level trigger
+ */
+ st |= (CIRQ_CON_EN << CIRQ_CON_EN_BITS);
+
+ mmio_write_32(CIRQ_CON, (st & CIRQ_CON_BITS_MASK));
+}
+
+/*
+ * mt_cirq_disable: Disable SYS_CIRQ
+ */
+void mt_cirq_disable(void)
+{
+ uint32_t st;
+
+ st = mmio_read_32(CIRQ_CON);
+ st &= ~(CIRQ_CON_EN << CIRQ_CON_EN_BITS);
+ mmio_write_32(CIRQ_CON, (st & CIRQ_CON_BITS_MASK));
+}
+
+void mt_irq_unmask_for_sleep_ex(uint32_t irq)
+{
+ uint32_t mask;
+
+ mask = 1U << (irq % 32U);
+
+ mmio_write_32(BASE_GICD_BASE + GICD_ISENABLER +
+ ((irq / 32U) * 4U), mask);
+}
+
+void mt_cirq_mask_all(void)
+{
+ unsigned int i;
+
+ for (i = 0U; i < CIRQ_CTRL_REG_NUM; i++) {
+ mmio_write_32(CIRQ_MASK_SET_BASE + (i * 4U), 0xFFFFFFFF);
+ }
+ dsb();
+}
+
+static void cirq_fast_sw_flush(void)
+{
+ struct cirq_reg *reg;
+ unsigned int i;
+
+ for (i = 0U; i < CIRQ_REG_NUM ; ++i) {
+ uint32_t cirq_bit;
+
+ reg = &cirq_all_events.table[i];
+
+ if (reg->used == 0U) {
+ continue;
+ }
+
+ reg->pending = mmio_read_32(CIRQ_STA_BASE +
+ (reg->reg_num << 2U));
+ reg->pending &= reg->mask;
+
+ for (cirq_bit = 0U; cirq_bit < 32U; ++cirq_bit) {
+ uint32_t val, cirq_id;
+
+ val = (1U << cirq_bit) & reg->pending;
+ if (val == 0U) {
+ continue;
+ }
+
+ cirq_id = (reg->reg_num << 5U) + cirq_bit;
+ mt_irq_set_pending(CIRQ_TO_IRQ_NUM(cirq_id));
+ if (CIRQ_TO_IRQ_NUM(cirq_id) == MD_WDT_IRQ_BIT_ID) {
+ INFO("Set MD_WDT_IRQ pending in %s\n",
+ __func__);
+ }
+ }
+ }
+}
+
+/*
+ * mt_cirq_disable: Flush interrupt from SYS_CIRQ to GIC
+ */
+void mt_cirq_flush(void)
+{
+ cirq_fast_sw_flush();
+ mt_cirq_mask_all();
+ mt_cirq_ack_all();
+}
+
+void mt_cirq_sw_reset(void)
+{
+#ifdef CIRQ_NEED_SW_RESET
+ uint32_t st;
+
+ st = mmio_read_32(CIRQ_CON);
+ st |= (CIRQ_SW_RESET << CIRQ_CON_SW_RST_BITS);
+ mmio_write_32(CIRQ_CON, st);
+#endif
+}
diff --git a/plat/mediatek/common/mtk_cirq.h b/plat/mediatek/common/mtk_cirq.h
new file mode 100644
index 0000000..6e63bb8
--- /dev/null
+++ b/plat/mediatek/common/mtk_cirq.h
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_MT_CIRQ_H
+#define PLAT_MT_CIRQ_H
+
+#include <stdint.h>
+#include <platform_def.h>
+
+enum {
+ IRQ_MASK_HEADER = 0xF1F1F1F1,
+ IRQ_MASK_FOOTER = 0xF2F2F2F2
+};
+
+struct mtk_irq_mask {
+ uint32_t header; /* for error checking */
+ uint32_t mask0;
+ uint32_t mask1;
+ uint32_t mask2;
+ uint32_t mask3;
+ uint32_t mask4;
+ uint32_t mask5;
+ uint32_t mask6;
+ uint32_t mask7;
+ uint32_t mask8;
+ uint32_t mask9;
+ uint32_t mask10;
+ uint32_t mask11;
+ uint32_t mask12;
+ uint32_t footer; /* for error checking */
+};
+
+/*
+ * Define hardware register
+ */
+#define CIRQ_STA_BASE (SYS_CIRQ_BASE + U(0x000))
+#define CIRQ_ACK_BASE (SYS_CIRQ_BASE + U(0x080))
+#define CIRQ_MASK_BASE (SYS_CIRQ_BASE + U(0x100))
+#define CIRQ_MASK_SET_BASE (SYS_CIRQ_BASE + U(0x180))
+#define CIRQ_MASK_CLR_BASE (SYS_CIRQ_BASE + U(0x200))
+#define CIRQ_SENS_BASE (SYS_CIRQ_BASE + U(0x280))
+#define CIRQ_SENS_SET_BASE (SYS_CIRQ_BASE + U(0x300))
+#define CIRQ_SENS_CLR_BASE (SYS_CIRQ_BASE + U(0x380))
+#define CIRQ_POL_BASE (SYS_CIRQ_BASE + U(0x400))
+#define CIRQ_POL_SET_BASE (SYS_CIRQ_BASE + U(0x480))
+#define CIRQ_POL_CLR_BASE (SYS_CIRQ_BASE + U(0x500))
+#define CIRQ_CON (SYS_CIRQ_BASE + U(0x600))
+
+/*
+ * Register placement
+ */
+#define CIRQ_CON_EN_BITS U(0)
+#define CIRQ_CON_EDGE_ONLY_BITS U(1)
+#define CIRQ_CON_FLUSH_BITS U(2)
+#define CIRQ_CON_SW_RST_BITS U(20)
+#define CIRQ_CON_EVENT_BITS U(31)
+#define CIRQ_CON_BITS_MASK U(0x7)
+
+/*
+ * Register setting
+ */
+#define CIRQ_CON_EN U(0x1)
+#define CIRQ_CON_EDGE_ONLY U(0x1)
+#define CIRQ_CON_FLUSH U(0x1)
+#define CIRQ_SW_RESET U(0x1)
+
+/*
+ * Define constant
+ */
+#define CIRQ_CTRL_REG_NUM ((CIRQ_IRQ_NUM + 31U) / 32U)
+
+#define MT_CIRQ_POL_NEG U(0)
+#define MT_CIRQ_POL_POS U(1)
+
+#define IRQ_TO_CIRQ_NUM(irq) ((irq) - (32U + CIRQ_SPI_START))
+#define CIRQ_TO_IRQ_NUM(cirq) ((cirq) + (32U + CIRQ_SPI_START))
+
+/* GIC sensitive */
+#define SENS_EDGE U(0x2)
+#define SENS_LEVEL U(0x1)
+
+
+/*
+ * Define function prototypes.
+ */
+int mt_cirq_test(void);
+void mt_cirq_dump_reg(void);
+int mt_irq_mask_restore(struct mtk_irq_mask *mask);
+int mt_irq_mask_all(struct mtk_irq_mask *mask);
+void mt_cirq_clone_gic(void);
+void mt_cirq_enable(void);
+void mt_cirq_flush(void);
+void mt_cirq_disable(void);
+void mt_irq_unmask_for_sleep_ex(uint32_t irq);
+void set_wakeup_sources(uint32_t *list, uint32_t num_of_events);
+void mt_cirq_sw_reset(void);
+
+struct cirq_reg {
+ uint32_t reg_num;
+ uint32_t used;
+ uint32_t mask;
+ uint32_t pol;
+ uint32_t sen;
+ uint32_t pending;
+ uint32_t the_link;
+};
+
+struct cirq_events {
+ uint32_t num_reg;
+ uint32_t spi_start;
+ uint32_t num_of_events;
+ uint32_t *wakeup_events;
+ struct cirq_reg table[CIRQ_REG_NUM];
+ uint32_t dist_base;
+ uint32_t cirq_base;
+ uint32_t used_reg_head;
+};
+
+#endif /* PLAT_MT_CIRQ_H */
diff --git a/plat/mediatek/common/mtk_plat_common.c b/plat/mediatek/common/mtk_plat_common.c
index f57e435..142b5c9 100644
--- a/plat/mediatek/common/mtk_plat_common.c
+++ b/plat/mediatek/common/mtk_plat_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -139,9 +139,9 @@
int32_t plat_get_soc_version(void)
{
- uint32_t manfid = (JEDEC_MTK_BKID << 24U) | (JEDEC_MTK_MFID << 16U);
+ uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_MTK_BKID, JEDEC_MTK_MFID);
- return (int32_t)(manfid | (SOC_CHIP_ID & 0xFFFFU));
+ return (int32_t)(manfid | (SOC_CHIP_ID & SOC_ID_IMPL_DEF_MASK));
}
int32_t plat_get_soc_revision(void)
diff --git a/plat/mediatek/common/mtk_sip_svc.h b/plat/mediatek/common/mtk_sip_svc.h
index cd4096e..74b17b6 100644
--- a/plat/mediatek/common/mtk_sip_svc.h
+++ b/plat/mediatek/common/mtk_sip_svc.h
@@ -31,6 +31,14 @@
#define MTK_SIP_KERNEL_BOOT_AARCH32 0x82000200
#define MTK_SIP_KERNEL_BOOT_AARCH64 0xC2000200
+/* VCORE */
+#define MTK_SIP_VCORE_CONTROL_ARCH32 0x82000506
+#define MTK_SIP_VCORE_CONTROL_ARCH64 0xC2000506
+
+/* APUSYS SMC call */
+#define MTK_SIP_APUSYS_CONTROL_AARCH32 0x8200051E
+#define MTK_SIP_APUSYS_CONTROL_AARCH64 0xC200051E
+
/* Mediatek SiP Calls error code */
enum {
MTK_SIP_E_SUCCESS = 0,
diff --git a/plat/mediatek/mt8183/drivers/uart/uart.h b/plat/mediatek/mt8183/drivers/uart/uart.h
deleted file mode 100644
index 062ce3a..0000000
--- a/plat/mediatek/mt8183/drivers/uart/uart.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __UART_H__
-#define __UART_H__
-
-#include <platform_def.h>
-
-/* UART HW information */
-#define HW_SUPPORT_UART_PORTS 2
-#define DRV_SUPPORT_UART_PORTS 2
-
-/* console UART clock cg */
-#define UART_CLOCK_GATE_SET (INFRACFG_AO_BASE + 0x80)
-#define UART_CLOCK_GATE_CLR (INFRACFG_AO_BASE + 0x84)
-#define UART_CLOCK_GATE_STA (INFRACFG_AO_BASE + 0x90)
-#define UART0_CLOCK_GATE_BIT (1U<<22)
-#define UART1_CLOCK_GATE_BIT (1U<<23)
-
-/* UART registers */
-#define UART_RBR(_baseaddr) (_baseaddr + 0x0)
-#define UART_THR(_baseaddr) (_baseaddr + 0x0)
-#define UART_IER(_baseaddr) (_baseaddr + 0x4)
-#define UART_IIR(_baseaddr) (_baseaddr + 0x8)
-#define UART_FCR(_baseaddr) (_baseaddr + 0x8)
-#define UART_LCR(_baseaddr) (_baseaddr + 0xc)
-#define UART_MCR(_baseaddr) (_baseaddr + 0x10)
-#define UART_LSR(_baseaddr) (_baseaddr + 0x14)
-#define UART_MSR(_baseaddr) (_baseaddr + 0x18)
-#define UART_SCR(_baseaddr) (_baseaddr + 0x1c)
-#define UART_DLL(_baseaddr) (_baseaddr + 0x0)
-#define UART_DLH(_baseaddr) (_baseaddr + 0x4)
-#define UART_EFR(_baseaddr) (_baseaddr + 0x8)
-#define UART_XON1(_baseaddr) (_baseaddr + 0x10)
-#define UART_XON2(_baseaddr) (_baseaddr + 0x14)
-#define UART_XOFF1(_baseaddr) (_baseaddr + 0x18)
-#define UART_XOFF2(_baseaddr) (_baseaddr + 0x1c)
-#define UART_AUTOBAUD(_baseaddr) (_baseaddr + 0x20)
-#define UART_HIGHSPEED(_baseaddr) (_baseaddr + 0x24)
-#define UART_SAMPLE_COUNT(_baseaddr) (_baseaddr + 0x28)
-#define UART_SAMPLE_POINT(_baseaddr) (_baseaddr + 0x2c)
-#define UART_AUTOBAUD_REG(_baseaddr) (_baseaddr + 0x30)
-#define UART_RATE_FIX_REG(_baseaddr) (_baseaddr + 0x34)
-#define UART_AUTO_BAUDSAMPLE(_baseaddr) (_baseaddr + 0x38)
-#define UART_GUARD(_baseaddr) (_baseaddr + 0x3c)
-#define UART_ESCAPE_DAT(_baseaddr) (_baseaddr + 0x40)
-#define UART_ESCAPE_EN(_baseaddr) (_baseaddr + 0x44)
-#define UART_SLEEP_EN(_baseaddr) (_baseaddr + 0x48)
-#define UART_DMA_EN(_baseaddr) (_baseaddr + 0x4c)
-#define UART_RXTRI_AD(_baseaddr) (_baseaddr + 0x50)
-#define UART_FRACDIV_L(_baseaddr) (_baseaddr + 0x54)
-#define UART_FRACDIV_M(_baseaddr) (_baseaddr + 0x58)
-#define UART_FCR_RD(_baseaddr) (_baseaddr + 0x5C)
-#define UART_USB_RX_SEL(_baseaddr) (_baseaddr + 0xB0)
-#define UART_SLEEP_REQ(_baseaddr) (_baseaddr + 0xB4)
-#define UART_SLEEP_ACK(_baseaddr) (_baseaddr + 0xB8)
-#define UART_SPM_SEL(_baseaddr) (_baseaddr + 0xBC)
-#define UART_LCR_DLAB 0x0080
-#define UART_LCR_MODE_B 0x00bf
-
-enum uart_port_ID {
- UART_PORT0 = 0,
- UART_PORT1
-};
-
-struct mt_uart_register {
- unsigned int dll;
- unsigned int dlh;
- unsigned int ier;
- unsigned int lcr;
- unsigned int mcr;
- unsigned int fcr;
- unsigned int lsr;
- unsigned int scr;
- unsigned int efr;
- unsigned int highspeed;
- unsigned int sample_count;
- unsigned int sample_point;
- unsigned int fracdiv_l;
- unsigned int fracdiv_m;
- unsigned int escape_en;
- unsigned int guard;
- unsigned int rx_sel;
-};
-
-struct mt_uart {
- unsigned long base;
- struct mt_uart_register registers;
-};
-
-/* external API */
-void mt_uart_save(void);
-void mt_uart_restore(void);
-void mt_console_uart_cg(int on);
-uint32_t mt_console_uart_cg_status(void);
-
-#endif /* __UART_H__ */
diff --git a/plat/mediatek/mt8183/platform.mk b/plat/mediatek/mt8183/platform.mk
index 07da1af..1615cf9 100644
--- a/plat/mediatek/mt8183/platform.mk
+++ b/plat/mediatek/mt8183/platform.mk
@@ -8,6 +8,7 @@
MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
+ -I${MTK_PLAT}/common/drivers/uart/ \
-I${MTK_PLAT_SOC}/drivers/ \
-I${MTK_PLAT_SOC}/drivers/emi_mpu/ \
-I${MTK_PLAT_SOC}/drivers/devapc/ \
@@ -19,7 +20,6 @@
-I${MTK_PLAT_SOC}/drivers/spm/ \
-I${MTK_PLAT_SOC}/drivers/sspm/ \
-I${MTK_PLAT_SOC}/drivers/rtc/ \
- -I${MTK_PLAT_SOC}/drivers/uart/ \
-I${MTK_PLAT_SOC}/include/
PLAT_BL_COMMON_SOURCES := lib/xlat_tables/aarch64/xlat_tables.c \
diff --git a/plat/mediatek/mt8192/aarch64/platform_common.c b/plat/mediatek/mt8192/aarch64/platform_common.c
index eb1bb44..fc98871 100644
--- a/plat/mediatek/mt8192/aarch64/platform_common.c
+++ b/plat/mediatek/mt8192/aarch64/platform_common.c
@@ -19,6 +19,16 @@
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(MTK_MCDI_SRAM_BASE, MTK_MCDI_SRAM_MAP_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(APUSYS_SCTRL_REVISER_BASE, APUSYS_SCTRL_REVISER_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(APUSYS_APU_S_S_4_BASE, APUSYS_APU_S_S_4_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(APUSYS_APC_AO_WRAPPER_BASE, APUSYS_APC_AO_WRAPPER_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(APUSYS_NOC_DAPC_AO_BASE, APUSYS_NOC_DAPC_AO_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
{ 0 }
};
diff --git a/plat/mediatek/mt8192/bl31_plat_setup.c b/plat/mediatek/mt8192/bl31_plat_setup.c
index 9de4a2e..c3cb9a5 100644
--- a/plat/mediatek/mt8192/bl31_plat_setup.c
+++ b/plat/mediatek/mt8192/bl31_plat_setup.c
@@ -16,9 +16,11 @@
#include <lib/coreboot.h>
/* Platform Includes */
+#include <devapc/devapc.h>
#include <emi_mpu/emi_mpu.h>
#include <gpio/mtgpio.h>
#include <mt_gic_v3.h>
+#include <mt_spm.h>
#include <mt_timer.h>
#include <mtk_dcm.h>
#include <plat_params.h>
@@ -93,13 +95,17 @@
/* MPU Init */
emi_mpu_init();
+ /* DAPC Init */
+ devapc_init();
+
/* Initialize the GIC driver, CPU and distributor interfaces */
mt_gic_driver_init();
mt_gic_init();
- plat_mt8192_gpio_init();
+ mt_gpio_init();
mt_systimer_init();
generic_delay_timer_init();
+ spm_boot_init();
}
/*******************************************************************************
diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.c b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.c
new file mode 100644
index 0000000..782aa5f
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/console.h>
+#include <lib/mmio.h>
+#include <mtk_apusys.h>
+#include <plat/common/platform.h>
+
+uint64_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
+ uint32_t *ret1)
+{
+ uint32_t request_ops;
+
+ request_ops = (uint32_t)x1;
+ INFO("[APUSYS] ops=0x%x\n", request_ops);
+
+ switch (request_ops) {
+ case MTK_SIP_APU_START_MCU:
+ /* setup addr[33:32] in reviser */
+ mmio_write_32(REVISER_SECUREFW_CTXT, 0U);
+ mmio_write_32(REVISER_USDRFW_CTXT, 0U);
+
+ /* setup secure sideband */
+ mmio_write_32(AO_SEC_FW,
+ (SEC_FW_NON_SECURE << SEC_FW_SHIFT_NS) |
+ (0U << SEC_FW_DOMAIN_SHIFT));
+
+ /* setup boot address */
+ mmio_write_32(AO_MD32_BOOT_CTRL, 0U);
+
+ /* setup pre-define region */
+ mmio_write_32(AO_MD32_PRE_DEFINE,
+ (PRE_DEFINE_CACHE_TCM << PRE_DEFINE_SHIFT_0G) |
+ (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_1G) |
+ (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_2G) |
+ (PRE_DEFINE_CACHE << PRE_DEFINE_SHIFT_3G));
+
+ /* release runstall */
+ mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_RUN);
+
+ INFO("[APUSYS] reviser_ctxt=%x,%x\n",
+ mmio_read_32(REVISER_SECUREFW_CTXT),
+ mmio_read_32(REVISER_USDRFW_CTXT));
+ INFO("[APUSYS]fw=0x%08x,boot=0x%08x,def=0x%08x,sys=0x%08x\n",
+ mmio_read_32(AO_SEC_FW),
+ mmio_read_32(AO_MD32_BOOT_CTRL),
+ mmio_read_32(AO_MD32_PRE_DEFINE),
+ mmio_read_32(AO_MD32_SYS_CTRL));
+ break;
+ case MTK_SIP_APU_STOP_MCU:
+ /* hold runstall */
+ mmio_write_32(AO_MD32_SYS_CTRL, SYS_CTRL_STALL);
+
+ INFO("[APUSYS] md32_boot_ctrl=0x%08x,runstall=0x%08x\n",
+ mmio_read_32(AO_MD32_BOOT_CTRL),
+ mmio_read_32(AO_MD32_SYS_CTRL));
+ break;
+ default:
+ ERROR("%s, unknown request_ops = %x\n", __func__, request_ops);
+ break;
+ }
+
+ return 0UL;
+}
diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.h b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.h
new file mode 100644
index 0000000..95fac4a
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __MTK_APUSYS_H__
+#define __MTK_APUSYS_H__
+
+#include <stdint.h>
+
+/* setup the SMC command ops */
+#define MTK_SIP_APU_START_MCU 0x00U
+#define MTK_SIP_APU_STOP_MCU 0x01U
+
+/* AO Register */
+#define AO_MD32_PRE_DEFINE (APUSYS_APU_S_S_4_BASE + 0x00)
+#define AO_MD32_BOOT_CTRL (APUSYS_APU_S_S_4_BASE + 0x04)
+#define AO_MD32_SYS_CTRL (APUSYS_APU_S_S_4_BASE + 0x08)
+#define AO_SEC_FW (APUSYS_APU_S_S_4_BASE + 0x10)
+
+#define PRE_DEFINE_CACHE_TCM 0x3U
+#define PRE_DEFINE_CACHE 0x2U
+#define PRE_DEFINE_SHIFT_0G 0U
+#define PRE_DEFINE_SHIFT_1G 2U
+#define PRE_DEFINE_SHIFT_2G 4U
+#define PRE_DEFINE_SHIFT_3G 6U
+
+#define SEC_FW_NON_SECURE 1U
+#define SEC_FW_SHIFT_NS 4U
+#define SEC_FW_DOMAIN_SHIFT 0U
+
+#define SYS_CTRL_RUN 0U
+#define SYS_CTRL_STALL 1U
+
+/* Reviser Register */
+#define REVISER_SECUREFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x300)
+#define REVISER_USDRFW_CTXT (APUSYS_SCTRL_REVISER_BASE + 0x304)
+
+uint64_t apusys_kernel_ctrl(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t x4,
+ uint32_t *ret1);
+#endif /* __MTK_APUSYS_H__ */
diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.c b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.c
new file mode 100644
index 0000000..245d512
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.c
@@ -0,0 +1,571 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <mtk_apusys_apc.h>
+#include <mtk_apusys_apc_def.h>
+#include <mtk_plat_common.h>
+#include <platform_def.h>
+
+static const struct APC_DOM_16 APUSYS_NOC_DAPC_AO[] = {
+/* 0~3 */
+APUSYS_APC_AO_ATTR("slv07-0",
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+APUSYS_APC_AO_ATTR("slv07-1",
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+APUSYS_APC_AO_ATTR("slv07-2",
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+APUSYS_APC_AO_ATTR("slv07-3",
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+
+/* 16~18 */
+APUSYS_APC_AO_ATTR("slv01-0",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("slv01-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("slv01-2",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 19~21 */
+APUSYS_APC_AO_ATTR("slv00-0",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("slv00-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("slv00-2",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 22~26 */
+APUSYS_APC_AO_ATTR("slv02-0",
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+APUSYS_APC_AO_ATTR("slv02-1",
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+APUSYS_APC_AO_ATTR("slv02-2",
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+APUSYS_APC_AO_ATTR("slv02-3",
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+APUSYS_APC_AO_ATTR("slv02-4",
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION,
+ NO_PROTECTION, NO_PROTECTION, NO_PROTECTION, NO_PROTECTION),
+};
+
+static int32_t set_slave_noc_dapc(uint32_t slave,
+ enum APUSYS_APC_DOMAIN_ID domain_id,
+ enum APUSYS_APC_PERM_TYPE perm)
+{
+ uint32_t apc_register_index;
+ uint32_t apc_set_index;
+ uintptr_t base;
+ uint32_t clr_bit;
+ uint32_t set_bit;
+ int32_t ret;
+
+ if (perm >= PERM_NUM) {
+ ERROR("[NOC_DAPC] perm type:0x%x is not supported!\n", perm);
+ ret = APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED;
+ goto exit;
+ }
+
+ apc_register_index = slave / APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM;
+ apc_set_index = slave % APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM;
+
+ clr_bit = 0xFFFFFFFF ^ (0x3U << (apc_set_index * 2));
+ set_bit = perm << (apc_set_index * 2);
+
+ if ((slave < APUSYS_NOC_DAPC_AO_SLAVE_NUM) &&
+ (domain_id < APUSYS_NOC_DAPC_AO_DOM_NUM)) {
+ base = APUSYS_NOC_DAPC_AO_BASE +
+ (domain_id * 0x40) + (apc_register_index * 4);
+ apuapc_writel(apuapc_readl(base) & clr_bit, base);
+ apuapc_writel(apuapc_readl(base) | set_bit, base);
+ ret = APUSYS_APC_OK;
+ } else {
+ ERROR("[NOC_DAPC] %s: %s, %s:0x%x, %s:0x%x\n",
+ __func__, "out of boundary",
+ "slave", slave,
+ "domain_id", domain_id);
+ ret = APUSYS_APC_ERR_OUT_OF_BOUNDARY;
+ }
+
+exit:
+ return ret;
+}
+
+static void dump_apusys_noc_dapc(void)
+{
+ uint32_t reg_num;
+ uint32_t d, i;
+
+ reg_num = APUSYS_NOC_DAPC_AO_SLAVE_NUM /
+ APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM;
+ for (d = 0U; d < APUSYS_NOC_DAPC_AO_DOM_NUM; d++) {
+ for (i = 0U; i <= reg_num; i++) {
+ INFO("[NOCDAPC] D%d_APC_%d: 0x%x\n", d, i,
+ apuapc_readl(APUSYS_NOC_DAPC_AO_BASE +
+ (d * 0x40) + (i * 4)));
+ }
+ }
+
+ INFO("[NOCDAPC] APC_CON: 0x%x\n", apuapc_readl(APUSYS_NOC_DAPC_CON));
+}
+
+static const struct APC_DOM_16 APUSYS_AO_Devices[] = {
+
+/* 0 */
+APUSYS_APC_AO_ATTR("apusys_ao-0",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apusys_ao-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apusys_ao-2",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apusys_ao-3",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apusys_ao-4",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apusys_ao-5",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("md32_apb_s-0",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("md32_apb_s-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("md32_apb_s-2",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("md32_debug_apb",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 10 */
+APUSYS_APC_AO_ATTR("apu_conn_config",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_sctrl_reviser",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_sema_stimer",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_emi_config",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_adl",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_edma_lite0",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_edma_lite1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_edma0",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_edma0",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_dapc_ao",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 20 */
+APUSYS_APC_AO_ATTR("apu_dapc",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("infra_bcrm",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apb_dbg_ctl",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("noc_dapc",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_noc_bcrm",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_noc_config",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("vpu_core0_config-0",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("vpu_core0_config-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("vpu_core1_config-0",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("vpu_core1_config-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 30 */
+APUSYS_APC_AO_ATTR("mdla0_apb-0",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("mdla0_apb-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("mdla0_apb-2",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("mdla0_apb-3",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_iommu0_r0",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_iommu0_r1",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_iommu0_r2",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_iommu0_r3",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_iommu0_r4",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("apu_rsi2_config",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 40 */
+APUSYS_APC_AO_ATTR("apu_ssc2_config",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("vp6_core0_debug_apb",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+APUSYS_APC_AO_ATTR("vp6_core1_debug_apb",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+};
+
+static int32_t set_slave_apc(uint32_t slave,
+ enum APUSYS_APC_DOMAIN_ID domain_id,
+ enum APUSYS_APC_PERM_TYPE perm)
+{
+ uint32_t apc_register_index;
+ uint32_t apc_set_index;
+ uintptr_t base;
+ uint32_t clr_bit;
+ uint32_t set_bit;
+ int32_t ret;
+
+ if (perm >= PERM_NUM) {
+ ERROR("[APUAPC] perm type:0x%x is not supported!\n", perm);
+ ret = APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED;
+ goto exit;
+ }
+
+ apc_register_index = slave / APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM;
+ apc_set_index = slave % APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM;
+
+ clr_bit = 0xFFFFFFFF ^ (0x3U << (apc_set_index * 2));
+ set_bit = perm << (apc_set_index * 2);
+
+ if ((slave < APUSYS_APC_SYS0_AO_SLAVE_NUM) &&
+ (domain_id < APUSYS_APC_SYS0_AO_DOM_NUM)) {
+ base = APUSYS_APC_AO_BASE +
+ (domain_id * 0x40) + (apc_register_index * 4);
+ apuapc_writel(apuapc_readl(base) & clr_bit, base);
+ apuapc_writel(apuapc_readl(base) | set_bit, base);
+ ret = APUSYS_APC_OK;
+ } else {
+ ERROR("[APUAPC] %s: %s, %s:0x%x, %s:0x%x\n",
+ __func__, "out of boundary",
+ "slave", slave,
+ "domain_id", domain_id);
+ ret = APUSYS_APC_ERR_OUT_OF_BOUNDARY;
+ }
+
+exit:
+ return ret;
+}
+
+static void dump_apusys_ao_apc(void)
+{
+ uint32_t reg_num;
+ uint32_t d, i;
+
+ reg_num = APUSYS_APC_SYS0_AO_SLAVE_NUM /
+ APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM;
+ for (d = 0U; d < APUSYS_APC_SYS0_AO_DOM_NUM; d++) {
+ for (i = 0U; i <= reg_num; i++) {
+ INFO("[APUAPC] D%d_APC_%d: 0x%x\n", d, i,
+ apuapc_readl(APUSYS_APC_AO_BASE +
+ (d * 0x40) + (i * 4)));
+ }
+ }
+ INFO("[APUAPC] APC_CON: 0x%x\n", apuapc_readl(APUSYS_APC_CON));
+}
+
+static int32_t set_apusys_noc_dapc(void)
+{
+ int32_t ret = 0;
+ uint32_t i;
+ uint32_t index;
+
+ for (i = 0U; i < ARRAY_SIZE(APUSYS_NOC_DAPC_AO); i++) {
+ if (i < APUSYS_NOC_DAPC_GAP_BOUNDARY) {
+ index = i;
+ } else {
+ index = i + APUSYS_NOC_DAPC_JUMP_GAP;
+ }
+ ret += set_slave_noc_dapc(index, DOMAIN_0,
+ APUSYS_NOC_DAPC_AO[i].d0_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_1,
+ APUSYS_NOC_DAPC_AO[i].d1_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_2,
+ APUSYS_NOC_DAPC_AO[i].d2_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_3,
+ APUSYS_NOC_DAPC_AO[i].d3_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_4,
+ APUSYS_NOC_DAPC_AO[i].d4_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_5,
+ APUSYS_NOC_DAPC_AO[i].d5_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_6,
+ APUSYS_NOC_DAPC_AO[i].d6_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_7,
+ APUSYS_NOC_DAPC_AO[i].d7_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_8,
+ APUSYS_NOC_DAPC_AO[i].d8_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_9,
+ APUSYS_NOC_DAPC_AO[i].d9_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_10,
+ APUSYS_NOC_DAPC_AO[i].d10_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_11,
+ APUSYS_NOC_DAPC_AO[i].d11_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_12,
+ APUSYS_NOC_DAPC_AO[i].d12_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_13,
+ APUSYS_NOC_DAPC_AO[i].d13_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_14,
+ APUSYS_NOC_DAPC_AO[i].d14_permission);
+ ret += set_slave_noc_dapc(index, DOMAIN_15,
+ APUSYS_NOC_DAPC_AO[i].d15_permission);
+ }
+
+ return ret;
+}
+
+static int32_t set_apusys_ao_apc(void)
+{
+ int32_t ret = 0;
+ uint32_t i;
+
+ for (i = 0U; i < ARRAY_SIZE(APUSYS_AO_Devices); i++) {
+ ret += set_slave_apc(i, DOMAIN_0,
+ APUSYS_AO_Devices[i].d0_permission);
+ ret += set_slave_apc(i, DOMAIN_1,
+ APUSYS_AO_Devices[i].d1_permission);
+ ret += set_slave_apc(i, DOMAIN_2,
+ APUSYS_AO_Devices[i].d2_permission);
+ ret += set_slave_apc(i, DOMAIN_3,
+ APUSYS_AO_Devices[i].d3_permission);
+ ret += set_slave_apc(i, DOMAIN_4,
+ APUSYS_AO_Devices[i].d4_permission);
+ ret += set_slave_apc(i, DOMAIN_5,
+ APUSYS_AO_Devices[i].d5_permission);
+ ret += set_slave_apc(i, DOMAIN_6,
+ APUSYS_AO_Devices[i].d6_permission);
+ ret += set_slave_apc(i, DOMAIN_7,
+ APUSYS_AO_Devices[i].d7_permission);
+ ret += set_slave_apc(i, DOMAIN_8,
+ APUSYS_AO_Devices[i].d8_permission);
+ ret += set_slave_apc(i, DOMAIN_9,
+ APUSYS_AO_Devices[i].d9_permission);
+ ret += set_slave_apc(i, DOMAIN_10,
+ APUSYS_AO_Devices[i].d10_permission);
+ ret += set_slave_apc(i, DOMAIN_11,
+ APUSYS_AO_Devices[i].d11_permission);
+ ret += set_slave_apc(i, DOMAIN_12,
+ APUSYS_AO_Devices[i].d12_permission);
+ ret += set_slave_apc(i, DOMAIN_13,
+ APUSYS_AO_Devices[i].d13_permission);
+ ret += set_slave_apc(i, DOMAIN_14,
+ APUSYS_AO_Devices[i].d14_permission);
+ ret += set_slave_apc(i, DOMAIN_15,
+ APUSYS_AO_Devices[i].d15_permission);
+ }
+
+ return ret;
+}
+
+static void set_apusys_apc_lock(void)
+{
+ uint32_t set_bit = 1U << APUSYS_APC_SYS0_LOCK_BIT_APU_SCTRL_REVISER;
+
+ /* Lock apu_sctrl_reviser */
+ set_bit = set_bit | (1U << APUSYS_APC_SYS0_LOCK_BIT_APUSYS_AO_5);
+ apuapc_writel(set_bit, APUSYS_SYS0_APC_LOCK_0);
+}
+
+void set_apusys_apc(void)
+{
+ int32_t ret = 0;
+
+ /* Check violation status */
+ INFO("[APUAPC] vio %d\n", apuapc_readl(APUSYS_APC_CON) & 0x80000000);
+
+ /* Initial Permission */
+ ret = set_apusys_ao_apc();
+ INFO("[APUAPC] %s - %s!\n", "set_apusys_ao_apc",
+ ret ? "FAILED" : "SUCCESS");
+
+ /* Lock */
+ set_apusys_apc_lock();
+
+ /* Initial NoC Permission */
+ ret = set_apusys_noc_dapc();
+ INFO("[APUAPC] %s - %s!\n", "set_apusys_noc_dapc",
+ ret ? "FAILED" : "SUCCESS");
+
+ /* Dump Permission */
+ dump_apusys_ao_apc();
+ dump_apusys_noc_dapc();
+
+ INFO("[APUAPC] %s done\n", __func__);
+}
diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.h b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.h
new file mode 100644
index 0000000..ff7a9fa
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __MTK_APUSYS_APC_H__
+#define __MTK_APUSYS_APC_H__
+
+void set_apusys_apc(void);
+
+#endif /* __MTK_APUSYS_APC_H__ */
diff --git a/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc_def.h b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc_def.h
new file mode 100644
index 0000000..b392d6a
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/apusys/mtk_apusys_apc_def.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __MTK_APUSYS_APC_DEF_H__
+#define __MTK_APUSYS_APC_DEF_H__
+
+#include <lib/mmio.h>
+
+enum APUSYS_APC_ERR_STATUS {
+ APUSYS_APC_OK = 0x0,
+
+ APUSYS_APC_ERR_GENERIC = 0x1000,
+ APUSYS_APC_ERR_INVALID_CMD = 0x1001,
+ APUSYS_APC_ERR_SLAVE_TYPE_NOT_SUPPORTED = 0x1002,
+ APUSYS_APC_ERR_SLAVE_IDX_NOT_SUPPORTED = 0x1003,
+ APUSYS_APC_ERR_DOMAIN_NOT_SUPPORTED = 0x1004,
+ APUSYS_APC_ERR_PERMISSION_NOT_SUPPORTED = 0x1005,
+ APUSYS_APC_ERR_OUT_OF_BOUNDARY = 0x1006,
+ APUSYS_APC_ERR_REQ_TYPE_NOT_SUPPORTED = 0x1007,
+};
+
+enum APUSYS_APC_PERM_TYPE {
+ NO_PROTECTION = 0U,
+ SEC_RW_ONLY = 1U,
+ SEC_RW_NS_R = 2U,
+ FORBIDDEN = 3U,
+ PERM_NUM = 4U,
+};
+
+enum APUSYS_APC_DOMAIN_ID {
+ DOMAIN_0 = 0U,
+ DOMAIN_1 = 1U,
+ DOMAIN_2 = 2U,
+ DOMAIN_3 = 3U,
+ DOMAIN_4 = 4U,
+ DOMAIN_5 = 5U,
+ DOMAIN_6 = 6U,
+ DOMAIN_7 = 7U,
+ DOMAIN_8 = 8U,
+ DOMAIN_9 = 9U,
+ DOMAIN_10 = 10U,
+ DOMAIN_11 = 11U,
+ DOMAIN_12 = 12U,
+ DOMAIN_13 = 13U,
+ DOMAIN_14 = 14U,
+ DOMAIN_15 = 15U,
+};
+
+struct APC_DOM_16 {
+ unsigned char d0_permission;
+ unsigned char d1_permission;
+ unsigned char d2_permission;
+ unsigned char d3_permission;
+ unsigned char d4_permission;
+ unsigned char d5_permission;
+ unsigned char d6_permission;
+ unsigned char d7_permission;
+ unsigned char d8_permission;
+ unsigned char d9_permission;
+ unsigned char d10_permission;
+ unsigned char d11_permission;
+ unsigned char d12_permission;
+ unsigned char d13_permission;
+ unsigned char d14_permission;
+ unsigned char d15_permission;
+};
+
+#define APUSYS_APC_AO_ATTR(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \
+ PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \
+ PERM_ATTR6, PERM_ATTR7, PERM_ATTR8, PERM_ATTR9, \
+ PERM_ATTR10, PERM_ATTR11, PERM_ATTR12, PERM_ATTR13, \
+ PERM_ATTR14, PERM_ATTR15) \
+ {(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \
+ (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, \
+ (unsigned char)PERM_ATTR4, (unsigned char)PERM_ATTR5, \
+ (unsigned char)PERM_ATTR6, (unsigned char)PERM_ATTR7, \
+ (unsigned char)PERM_ATTR8, (unsigned char)PERM_ATTR9, \
+ (unsigned char)PERM_ATTR10, (unsigned char)PERM_ATTR11, \
+ (unsigned char)PERM_ATTR12, (unsigned char)PERM_ATTR13, \
+ (unsigned char)PERM_ATTR14, (unsigned char)PERM_ATTR15}
+
+#define apuapc_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL)
+#define apuapc_readl(REG) mmio_read_32((uintptr_t)REG)
+
+/* APUSYS APC AO Registers */
+#define APUSYS_APC_AO_BASE APUSYS_APC_AO_WRAPPER_BASE
+#define APUSYS_APC_CON (APUSYS_APC_AO_BASE + 0x00F00)
+#define APUSYS_SYS0_APC_LOCK_0 (APUSYS_APC_AO_BASE + 0x00700)
+
+/* APUSYS NOC_DPAC_AO Registers */
+#define APUSYS_NOC_DAPC_CON (APUSYS_NOC_DAPC_AO_BASE + 0x00F00)
+
+#define APUSYS_NOC_DAPC_GAP_BOUNDARY 4U
+#define APUSYS_NOC_DAPC_JUMP_GAP 12U
+
+#define APUSYS_APC_SYS0_AO_SLAVE_NUM_IN_1_DOM 16U
+#define APUSYS_APC_SYS0_AO_DOM_NUM 16U
+#define APUSYS_APC_SYS0_AO_SLAVE_NUM 59U
+
+#define APUSYS_APC_SYS0_LOCK_BIT_APU_SCTRL_REVISER 11U
+#define APUSYS_APC_SYS0_LOCK_BIT_APUSYS_AO_5 5U
+
+#define APUSYS_NOC_DAPC_AO_SLAVE_NUM_IN_1_DOM 16U
+#define APUSYS_NOC_DAPC_AO_DOM_NUM 16U
+#define APUSYS_NOC_DAPC_AO_SLAVE_NUM 27U
+
+#endif /* __MTK_APUSYS_APC_DEF_H__ */
diff --git a/plat/mediatek/mt8192/drivers/devapc/devapc.c b/plat/mediatek/mt8192/drivers/devapc/devapc.c
new file mode 100644
index 0000000..b11f272
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/devapc/devapc.c
@@ -0,0 +1,2847 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <drivers/console.h>
+#include <lib/mmio.h>
+
+#include <devapc.h>
+#include <mtk_apusys_apc.h>
+
+/* Infra_ao */
+static const struct APC_INFRA_PERI_DOM_16 INFRA_AO_SYS0_Devices[] = {
+
+/* 0 */
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-2",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-3",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-4",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-5",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-6",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-7",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MFG_S_S-8",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("APU_S_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 10 */
+DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-2",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-3",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-4",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("APU_S_S-5",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-1",
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-2",
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-3",
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("MCUSYS_CFGREG_APB_S-4",
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 20 */
+DAPC_INFRA_AO_SYS0_ATTR("L3C_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("L3C_S-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS0_ATTR("PCIE_AXI_S",
+ NO_PROTECTION, NO_PROTECTION, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+};
+
+static const struct APC_INFRA_PERI_DOM_4 INFRA_AO_SYS1_Devices[] = {
+
+/* 0 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-2",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-3",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-4",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-5",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-6",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-7",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-8",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-9",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 10 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-10",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-11",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-12",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-13",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-14",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-15",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-16",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-17",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-18",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-19",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 20 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-20",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-21",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-22",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-23",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-24",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-25",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-26",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-27",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-28",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-29",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 30 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-30",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-31",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-32",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-33",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-34",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-35",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-36",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-37",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-38",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-39",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 40 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-100",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-101",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-102",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-103",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-104",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-105",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-106",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-107",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-108",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-109",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 50 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-110",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-111",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-112",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-113",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-114",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-115",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-116",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-117",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-118",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-119",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 60 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-120",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-121",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-122",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-123",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-124",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-125",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-126",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-127",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-128",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-129",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 70 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-130",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-131",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-132",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-133",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-134",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-135",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-136",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-137",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-138",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-139",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 80 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-140",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-141",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-142",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-143",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-200",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-201",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-202",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-203",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-204",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-205",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 90 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-206",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-207",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-300",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-301",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-302",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-303",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-304",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-305",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-306",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-307",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 100 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-400",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-401",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-402",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-403",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-404",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-405",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-406",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-407",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-408",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-409",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 110 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-410",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-411",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-412",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-413",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-414",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-415",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-416",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-417",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-418",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-419",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 120 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-420",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-421",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-422",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-423",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-424",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-425",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-426",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-427",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-428",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-429",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 130 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-430",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-431",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-432",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-433",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-434",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-435",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-436",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-437",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-438",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-439",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 140 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-440",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-441",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-442",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-443",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-444",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-445",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-446",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-447",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-448",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-449",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 150 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-450",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-451",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-452",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-453",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-454",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-455",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-456",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-457",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-458",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-459",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 160 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-460",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-461",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-462",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-463",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-464",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-465",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-466",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-467",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-468",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-469",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 170 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-470",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-471",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-472",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-473",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-474",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-475",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-476",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-477",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-478",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-479",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 180 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-480",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-481",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-482",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-483",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-484",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-485",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-486",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-487",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-488",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-489",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 190 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-490",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-491",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-492",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-493",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-494",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-495",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-496",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-497",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-498",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-499",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 200 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-500",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-501",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-502",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-503",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-504",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-505",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-506",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-507",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-508",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-509",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 210 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-510",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-511",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-512",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-513",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-514",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-515",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-516",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-517",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-518",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-519",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 220 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-520",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-521",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-522",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-523",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-524",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-525",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-526",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-527",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-528",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-529",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 230 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-530",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-531",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-532",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-533",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-534",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-535",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-536",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-537",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-538",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-539",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 240 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-540",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-541",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-542",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-543",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-544",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-545",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-546",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-547",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-548",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-549",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 250 */
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-550",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-551",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-552",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-553",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-554",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS1_ATTR("MM_S_S-555",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+};
+
+static const struct APC_INFRA_PERI_DOM_4 INFRA_AO_SYS2_Devices[] = {
+
+/* 0 */
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-556",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-557",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-558",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-559",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-560",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-561",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-562",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-563",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-564",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-565",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 10 */
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-566",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-567",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-568",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-569",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-570",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-571",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-572",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-573",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-574",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-575",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 20 */
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-576",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-577",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-578",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-579",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-580",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-581",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-582",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-583",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-584",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-585",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 30 */
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-586",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-587",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-588",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-589",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-590",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-591",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-592",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-593",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-594",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-595",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 40 */
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-600",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-601",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-602",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-603",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-604",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-605",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-606",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-607",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-608",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-609",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 50 */
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-610",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-611",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-700",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-701",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-702",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-703",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-704",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-705",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-706",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-707",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 60 */
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-708",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-709",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-710",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-711",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-712",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-713",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-714",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-715",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-716",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_INFRA_AO_SYS2_ATTR("MM_S_S-717",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+};
+
+/* Peri_ao */
+static const struct APC_INFRA_PERI_DOM_16 PERI_AO_SYS0_Devices[] = {
+
+/* 0 */
+DAPC_PERI_AO_SYS0_ATTR("SPM_APB_S",
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SPM_APB_S-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SPM_APB_S-2",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SPM_APB_S-3",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SPM_APB_S-4",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("APMIXEDSYS_APB_S",
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, NO_PROTECTION,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("APMIXEDSYS_APB_S-1",
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("TOPCKGEN_APB_S",
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, NO_PROTECTION,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("INFRACFG_AO_APB_S",
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("INFRACFG_AO_MEM_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 10 */
+DAPC_PERI_AO_SYS0_ATTR("PERICFG_AO_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("GPIO_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, NO_PROTECTION,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("TOPRGU_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("RESERVED_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEVICE_APC_INFRA_AO_APB_S",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("BCRM_INFRA_AO_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEBUG_CTRL_INFRA_AO_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEVICE_APC_PERI_AO_APB_S",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("BCRM_PERI_AO_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEBUG_CTRL_PERI_AO_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 20 */
+DAPC_PERI_AO_SYS0_ATTR("AP_CIRQ_EINT_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PMIC_WRAP_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEVICE_APC_AO_MM_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("KP_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("TOP_MISC_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DVFSRC_APB_S",
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("MBIST_AO_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DPMAIF_AO_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEVICE_MPU_AO_APB_S",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SYS_TIMER_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 30 */
+DAPC_PERI_AO_SYS0_ATTR("MODEM_TEMP_SHARE_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEVICE_APC_AO_MD_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PMIF1_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PMICSPI_MST_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("TIA_APB_S",
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("TOPCKGEN_INFRA_CFG_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRM_DEBUG_TOP_APB_S",
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-2",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 40 */
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-3",
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-4",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-5",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-6",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-7",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-8",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-9",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PWR_MD32_S-10",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("AUDIO_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("AUDIO_S-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 50 */
+DAPC_PERI_AO_SYS0_ATTR("SSUSB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SSUSB_S-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SSUSB_S-2",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("UFS_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("UFS_S-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("UFS_S-2",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("UFS_S-3",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEBUGSYS_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S0_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S0_APB_S-1",
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 60 */
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S1_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_MD32_S1_APB_S-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("NOR_AXI_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("PCIE_AHB_S",
+ NO_PROTECTION, NO_PROTECTION, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP0_APB_S",
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP1_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP2_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP3_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP4_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP5_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 70 */
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH0_TOP6_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP0_APB_S",
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP1_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP2_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP3_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP4_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP5_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH1_TOP6_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP0_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP1_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 80 */
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP2_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP3_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP4_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP5_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH2_TOP6_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP0_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP1_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP2_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP3_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP4_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 90 */
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP5_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DRAMC_CH3_TOP6_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("CCIF2_AP_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("CCIF2_MD_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("CCIF3_AP_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("CCIF3_MD_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("CCIF4_AP_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("CCIF4_MD_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("INFRA_BUS_TRACE_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("CCIF5_AP_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 100 */
+DAPC_PERI_AO_SYS0_ATTR("CCIF5_MD_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SSC_INFRA_APB0_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SSC_INFRA_APB1_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("SSC_INFRA_APB2_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS0_ATTR("DEVICE_MPU_ACP_APB_S",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+};
+
+static const struct APC_INFRA_PERI_DOM_8 PERI_AO_SYS1_Devices[] = {
+
+/* 0 */
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-2",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-3",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-4",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-5",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-6",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-7",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-8",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-9",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 10 */
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-10",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-11",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-12",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-13",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-14",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-15",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-16",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-17",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-18",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-19",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 20 */
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-20",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-21",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("TINSYS_S-22",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-2",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-3",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-4",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-5",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-6",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 30 */
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-7",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-8",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-9",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-10",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-11",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-12",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-13",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-14",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-15",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-16",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 40 */
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-17",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-18",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-19",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-20",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-21",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-22",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-23",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-24",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-25",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-26",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 50 */
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-27",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-28",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-29",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-30",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-31",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-32",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-33",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-34",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-35",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-36",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 60 */
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-37",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-38",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-39",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-40",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-41",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO_SYS1_ATTR("MD_AP_S-42",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+};
+
+static const struct APC_INFRA_PERI_DOM_4 PERI_AO_SYS2_Devices[] = {
+
+/* 0 */
+DAPC_PERI_AO_SYS2_ATTR("CONN_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+};
+
+/* Peri_ao2 */
+static const struct APC_INFRA_PERI_DOM_16 PERI_AO2_SYS0_Devices[] = {
+
+/* 0 */
+DAPC_PERI_AO2_SYS0_ATTR("EFUSE_DEBUG_AO_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("APXGPT_APB_S",
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("SEJ_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("AES_TOP0_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("SECURITY_AO_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEVICE_APC_PERI_AO2_APB_S",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BCRM_PERI_AO2_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEBUG_CTRL_PERI_AO2_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("SPMI_MST_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEBUG_CTRL_FMEM_AO_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 10 */
+DAPC_PERI_AO2_SYS0_ATTR("BCRM_FMEM_AO_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEVICE_APC_FMEM_AO_APB_S",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("PWM_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("GCE_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("GCE_APB_S-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("GCE_APB_S-2",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("GCE_APB_S-3",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DPMAIF_PDN_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DPMAIF_PDN_APB_S-1",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DPMAIF_PDN_APB_S-2",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 20 */
+DAPC_PERI_AO2_SYS0_ATTR("DPMAIF_PDN_APB_S-3",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB0_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB1_S",
+ NO_PROTECTION, FORBIDDEN, SEC_RW_NS_R, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB2_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB3_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB4_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB5_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB6_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB7_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB8_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 30 */
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB9_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB10_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB11_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB12_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB13_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB14_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_APB15_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB0_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB1_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB2_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 40 */
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB3_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB4_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB5_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB6_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_WEST_APB7_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB0_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB1_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB2_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB3_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB4_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 50 */
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB5_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB6_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB7_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB8_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB9_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB10_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB11_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB12_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB13_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB14_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 60 */
+DAPC_PERI_AO2_SYS0_ATTR("BND_NORTH_APB15_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB0_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB1_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB2_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB3_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB4_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB5_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB6_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB7_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB8_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 70 */
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB9_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB10_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB11_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB12_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB13_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB14_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_SOUTH_APB15_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB0_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB1_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB2_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 80 */
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB3_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB4_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB5_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB6_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BND_EAST_NORTH_APB7_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("SYS_CIRQ_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("EFUSE_DEBUG_PDN_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEVICE_APC_INFRA_PDN_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEBUG_TRACKER_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("CCIF0_AP_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 90 */
+DAPC_PERI_AO2_SYS0_ATTR("CCIF0_MD_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("CCIF1_AP_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("CCIF1_MD_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("MBIST_PDN_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("INFRACFG_PDN_APB_S",
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("TRNG_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DX_CC_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("CQ_DMA_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("SRAMROM_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("INFRACFG_MEM_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 100 */
+DAPC_PERI_AO2_SYS0_ATTR("RESERVED_DVFS_PROC_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("SYS_CIRQ1_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("SYS_CIRQ2_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEBUG_TRACKER_APB1_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("EMI_APB_S",
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("EMI_MPU_APB_S",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEVICE_MPU_PDN_APB_S",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("APDMA_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEBUG_TRACKER_APB2_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BCRM_INFRA_PDN_APB_S",
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 110 */
+DAPC_PERI_AO2_SYS0_ATTR("BCRM_PERI_PDN_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BCRM_PERI_PDN2_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEVICE_APC_PERI_PDN_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("DEVICE_APC_PERI_PDN2_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_AO2_SYS0_ATTR("BCRM_FMEM_PDN_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+};
+
+/* Peri_par_ao */
+static const struct APC_INFRA_PERI_DOM_16 PERI_PAR_AO_SYS0_Devices[] = {
+
+/* 0 */
+DAPC_PERI_PAR_AO_SYS0_ATTR("AUXADC_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("UART0_APB_S",
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("UART1_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("UART2_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB4_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI0_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("PTP_THERM_CTRL_APB_S",
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("BTIF_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("DISP_PWM_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI1_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 10 */
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI2_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI3_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB0_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB1_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI4_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI5_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB2_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("IIC_P2P_REMAP_APB3_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI6_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("SPI7_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+/* 20 */
+DAPC_PERI_PAR_AO_SYS0_ATTR("BCRM_PERI_PAR_PDN_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("DEVICE_APC_PERI_PAR_PDN_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("PTP_THERM_CTRL2_APB_S",
+ NO_PROTECTION, FORBIDDEN, NO_PROTECTION, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("NOR_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("DEVICE_APC_PERI_PAR_AO_APB_S",
+ SEC_RW_ONLY, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("DEBUG_CTRL_PERI_PAR_AO_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+DAPC_PERI_PAR_AO_SYS0_ATTR("BCRM_PERI_PAR_AO_APB_S",
+ NO_PROTECTION, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN),
+
+};
+
+static void set_module_apc(enum DEVAPC_SLAVE_TYPE slave_type,
+ uint32_t module, enum DOMAIN_ID domain_id,
+ enum DEVAPC_PERM_TYPE perm)
+{
+ uint32_t apc_register_index;
+ uint32_t apc_set_index;
+ uintptr_t base = 0, reg;
+ uint32_t clr_bit;
+ uint32_t set_bit;
+
+ apc_register_index = module / MOD_NO_IN_1_DEVAPC;
+ apc_set_index = module % MOD_NO_IN_1_DEVAPC;
+
+ clr_bit = (0x3U << (apc_set_index * 2));
+ set_bit = (uint32_t)perm << (apc_set_index * 2);
+
+ /* infra_ao */
+ if ((slave_type == SLAVE_TYPE_INFRA_AO_SYS0) &&
+ (module < SLAVE_NUM_INFRA_AO_SYS0) &&
+ (domain_id < (uint32_t)DOM_NUM_INFRA_AO_SYS0)) {
+ base = DEVAPC_INFRA_AO_SYS0_D0_APC_0;
+
+ } else if ((slave_type == SLAVE_TYPE_INFRA_AO_SYS1) &&
+ (module < SLAVE_NUM_INFRA_AO_SYS1) &&
+ (domain_id < (uint32_t)DOM_NUM_INFRA_AO_SYS1)) {
+ base = DEVAPC_INFRA_AO_SYS1_D0_APC_0;
+
+ } else if ((slave_type == SLAVE_TYPE_INFRA_AO_SYS2) &&
+ (module < SLAVE_NUM_INFRA_AO_SYS2) &&
+ (domain_id < (uint32_t)DOM_NUM_INFRA_AO_SYS2)) {
+ base = DEVAPC_INFRA_AO_SYS2_D0_APC_0;
+ /* peri_ao */
+ } else if ((slave_type == SLAVE_TYPE_PERI_AO_SYS0) &&
+ (module < SLAVE_NUM_PERI_AO_SYS0) &&
+ (domain_id < (uint32_t)DOM_NUM_PERI_AO_SYS0)) {
+ base = DEVAPC_PERI_AO_SYS0_D0_APC_0;
+
+ } else if ((slave_type == SLAVE_TYPE_PERI_AO_SYS1) &&
+ (module < SLAVE_NUM_PERI_AO_SYS1) &&
+ (domain_id <= (uint32_t)DOM_NUM_PERI_AO_SYS1)) {
+ base = DEVAPC_PERI_AO_SYS1_D0_APC_0;
+
+ } else if ((slave_type == SLAVE_TYPE_PERI_AO_SYS2) &&
+ (module < SLAVE_NUM_PERI_AO_SYS2) &&
+ (domain_id < (uint32_t)DOM_NUM_PERI_AO_SYS2)) {
+ base = DEVAPC_PERI_AO_SYS2_D0_APC_0;
+ /* peri_ao2 */
+ } else if ((slave_type == SLAVE_TYPE_PERI_AO2_SYS0) &&
+ (module < SLAVE_NUM_PERI_AO2_SYS0) &&
+ (domain_id < (uint32_t)DOM_NUM_PERI_AO2_SYS0)) {
+ base = DEVAPC_PERI_AO2_SYS0_D0_APC_0;
+
+ /* peri_par_ao */
+ } else if ((slave_type == SLAVE_TYPE_PERI_PAR_AO_SYS0) &&
+ (module < SLAVE_NUM_PERI_PAR_AO_SYS0) &&
+ (domain_id < (uint32_t)DOM_NUM_PERI_PAR_AO_SYS0)) {
+ base = DEVAPC_PERI_PAR_AO_SYS0_D0_APC_0;
+
+ } else {
+ ERROR("[DEVAPC] %s: %s, %s:0x%x, %s:0x%x, %s:0x%x\n",
+ __func__, "out of boundary",
+ "slave_type", slave_type,
+ "module", module,
+ "domain_id", domain_id);
+ }
+
+ if (base != 0U) {
+ reg = base + domain_id * 0x40 + apc_register_index * 4;
+ mmio_clrsetbits_32(reg, clr_bit, set_bit);
+ }
+}
+
+static void dump_infra_ao_apc(void)
+{
+ int reg_num;
+ int d, i;
+
+ reg_num = (SLAVE_NUM_INFRA_AO_SYS0 - 1) / MOD_NO_IN_1_DEVAPC;
+ for (d = 0; d < DOM_NUM_INFRA_AO_SYS0; d++) {
+ for (i = 0; i <= reg_num; i++) {
+ INFO("[DEVAPC] (INFRA_AO_SYS0)D%d_APC_%d: 0x%x\n",
+ d, i, devapc_readl(
+ DEVAPC_INFRA_AO_SYS0_D0_APC_0 +
+ d * 0x40 + i * 4)
+ );
+ }
+ }
+
+ reg_num = (SLAVE_NUM_INFRA_AO_SYS1 - 1) / MOD_NO_IN_1_DEVAPC;
+ for (d = 0; d < DOM_NUM_INFRA_AO_SYS1; d++) {
+ for (i = 0; i <= reg_num; i++) {
+ INFO("[DEVAPC] (INFRA_AO_SYS1)D%d_APC_%d: 0x%x\n",
+ d, i, devapc_readl(
+ DEVAPC_INFRA_AO_SYS1_D0_APC_0 +
+ d * 0x40 + i * 4)
+ );
+ }
+ }
+
+ reg_num = (SLAVE_NUM_INFRA_AO_SYS2 - 1) / MOD_NO_IN_1_DEVAPC;
+ for (d = 0; d < DOM_NUM_INFRA_AO_SYS2; d++) {
+ for (i = 0; i <= reg_num; i++) {
+ INFO("[DEVAPC] (INFRA_AO_SYS2)D%d_APC_%d: 0x%x\n",
+ d, i, devapc_readl(
+ DEVAPC_INFRA_AO_SYS2_D0_APC_0 +
+ d * 0x40 + i * 4)
+ );
+ }
+ }
+
+ INFO("[DEVAPC] (INFRA_AO)MAS_SEC_0: 0x%x\n",
+ devapc_readl(DEVAPC_INFRA_AO_MAS_SEC_0));
+}
+
+static void dump_peri_ao_apc(void)
+{
+ int reg_num;
+ int d, i;
+
+ reg_num = (SLAVE_NUM_PERI_AO_SYS0 - 1) / MOD_NO_IN_1_DEVAPC;
+ for (d = 0; d < DOM_NUM_PERI_AO_SYS0; d++) {
+ for (i = 0; i <= reg_num; i++) {
+ INFO("[DEVAPC] (PERI_AO_SYS0)D%d_APC_%d: 0x%x\n",
+ d, i, devapc_readl(
+ DEVAPC_PERI_AO_SYS0_D0_APC_0 +
+ d * 0x40 + i * 4)
+ );
+ }
+ }
+
+ reg_num = (SLAVE_NUM_PERI_AO_SYS1 - 1) / MOD_NO_IN_1_DEVAPC;
+ for (d = 0; d < DOM_NUM_PERI_AO_SYS1; d++) {
+ for (i = 0; i <= reg_num; i++) {
+ INFO("[DEVAPC] (PERI_AO_SYS1)D%d_APC_%d: 0x%x\n",
+ d, i, devapc_readl(
+ DEVAPC_PERI_AO_SYS1_D0_APC_0 +
+ d * 0x40 + i * 4)
+ );
+ }
+ }
+
+ reg_num = (SLAVE_NUM_PERI_AO_SYS2 - 1) / MOD_NO_IN_1_DEVAPC;
+ for (d = 0; d < DOM_NUM_PERI_AO_SYS2; d++) {
+ for (i = 0; i <= reg_num; i++) {
+ INFO("[DEVAPC] (PERI_AO_SYS2)D%d_APC_%d: 0x%x\n",
+ d, i, devapc_readl(
+ DEVAPC_PERI_AO_SYS2_D0_APC_0 +
+ d * 0x40 + i * 4)
+ );
+ }
+ }
+
+ INFO("[DEVAPC] (PERI_AO)MAS_SEC_0: 0x%x\n",
+ devapc_readl(DEVAPC_PERI_AO_MAS_SEC_0));
+}
+
+static void dump_peri_ao2_apc(void)
+{
+ int reg_num;
+ int d, i;
+
+ reg_num = (SLAVE_NUM_PERI_AO2_SYS0 - 1) / MOD_NO_IN_1_DEVAPC;
+ for (d = 0; d < DOM_NUM_PERI_AO2_SYS0; d++) {
+ for (i = 0; i <= reg_num; i++) {
+ INFO("[DEVAPC] (PERI_AO2_SYS0)D%d_APC_%d: 0x%x\n",
+ d, i, devapc_readl(
+ DEVAPC_PERI_AO2_SYS0_D0_APC_0 +
+ d * 0x40 + i * 4)
+ );
+ }
+ }
+}
+
+static void dump_peri_par_ao_apc(void)
+{
+ int reg_num;
+ int d, i;
+
+ reg_num = (SLAVE_NUM_PERI_PAR_AO_SYS0 - 1) / MOD_NO_IN_1_DEVAPC;
+ for (d = 0; d < DOM_NUM_PERI_PAR_AO_SYS0; d++) {
+ for (i = 0; i <= reg_num; i++) {
+ INFO("[DEVAPC] (PERI_PAR_AO_SYS0)D%d_APC_%d: 0x%x\n",
+ d, i, devapc_readl(
+ DEVAPC_PERI_PAR_AO_SYS0_D0_APC_0 +
+ d * 0x40 + i * 4)
+ );
+ }
+ }
+
+ INFO("[DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x%x\n",
+ devapc_readl(DEVAPC_PERI_PAR_AO_MAS_SEC_0));
+}
+
+static void set_infra_ao_apc(void)
+{
+ uint32_t infra_ao_size;
+ uint32_t i;
+
+ infra_ao_size = ARRAY_SIZE(INFRA_AO_SYS0_Devices);
+
+ for (i = 0; i < infra_ao_size; i++) {
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_0,
+ INFRA_AO_SYS0_Devices[i].d0_permission); /* APMCU */
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_1,
+ INFRA_AO_SYS0_Devices[i].d1_permission);
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_2,
+ INFRA_AO_SYS0_Devices[i].d2_permission);
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_3,
+ INFRA_AO_SYS0_Devices[i].d3_permission);
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_4,
+ INFRA_AO_SYS0_Devices[i].d4_permission);
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_5,
+ INFRA_AO_SYS0_Devices[i].d5_permission);
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_6,
+ INFRA_AO_SYS0_Devices[i].d6_permission);
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_7,
+ INFRA_AO_SYS0_Devices[i].d7_permission);
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_8,
+ INFRA_AO_SYS0_Devices[i].d8_permission);
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_9,
+ INFRA_AO_SYS0_Devices[i].d9_permission);
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_10,
+ INFRA_AO_SYS0_Devices[i].d10_permission);
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_11,
+ INFRA_AO_SYS0_Devices[i].d11_permission);
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_12,
+ INFRA_AO_SYS0_Devices[i].d12_permission);
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_13,
+ INFRA_AO_SYS0_Devices[i].d13_permission);
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_14,
+ INFRA_AO_SYS0_Devices[i].d14_permission);
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS0, i, DOMAIN_15,
+ INFRA_AO_SYS0_Devices[i].d15_permission);
+ }
+
+ infra_ao_size = ARRAY_SIZE(INFRA_AO_SYS1_Devices);
+
+ for (i = 0; i < infra_ao_size; i++) {
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS1, i, DOMAIN_0,
+ INFRA_AO_SYS1_Devices[i].d0_permission); /* APMCU */
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS1, i, DOMAIN_1,
+ INFRA_AO_SYS1_Devices[i].d1_permission);
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS1, i, DOMAIN_2,
+ INFRA_AO_SYS1_Devices[i].d2_permission);
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS1, i, DOMAIN_3,
+ INFRA_AO_SYS1_Devices[i].d3_permission);
+ }
+
+ infra_ao_size = ARRAY_SIZE(INFRA_AO_SYS2_Devices);
+
+ for (i = 0; i < infra_ao_size; i++) {
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS2, i, DOMAIN_0,
+ INFRA_AO_SYS2_Devices[i].d0_permission); /* APMCU */
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS2, i, DOMAIN_1,
+ INFRA_AO_SYS2_Devices[i].d1_permission);
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS2, i, DOMAIN_2,
+ INFRA_AO_SYS2_Devices[i].d2_permission);
+ set_module_apc(SLAVE_TYPE_INFRA_AO_SYS2, i, DOMAIN_3,
+ INFRA_AO_SYS2_Devices[i].d3_permission);
+ }
+}
+
+static void set_peri_ao_apc(void)
+{
+ uint32_t peri_ao_size;
+ uint32_t i;
+
+ peri_ao_size = ARRAY_SIZE(PERI_AO_SYS0_Devices);
+
+ for (i = 0; i < peri_ao_size; i++) {
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_0,
+ PERI_AO_SYS0_Devices[i].d0_permission); /* APMCU */
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_1,
+ PERI_AO_SYS0_Devices[i].d1_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_2,
+ PERI_AO_SYS0_Devices[i].d2_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_3,
+ PERI_AO_SYS0_Devices[i].d3_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_4,
+ PERI_AO_SYS0_Devices[i].d4_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_5,
+ PERI_AO_SYS0_Devices[i].d5_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_6,
+ PERI_AO_SYS0_Devices[i].d6_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_7,
+ PERI_AO_SYS0_Devices[i].d7_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_8,
+ PERI_AO_SYS0_Devices[i].d8_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_9,
+ PERI_AO_SYS0_Devices[i].d9_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_10,
+ PERI_AO_SYS0_Devices[i].d10_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_11,
+ PERI_AO_SYS0_Devices[i].d11_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_12,
+ PERI_AO_SYS0_Devices[i].d12_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_13,
+ PERI_AO_SYS0_Devices[i].d13_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_14,
+ PERI_AO_SYS0_Devices[i].d14_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, i, DOMAIN_15,
+ PERI_AO_SYS0_Devices[i].d15_permission);
+ }
+
+ peri_ao_size = ARRAY_SIZE(PERI_AO_SYS1_Devices);
+
+ for (i = 0; i < peri_ao_size; i++) {
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_0,
+ PERI_AO_SYS1_Devices[i].d0_permission); /* APMCU */
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_1,
+ PERI_AO_SYS1_Devices[i].d1_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_2,
+ PERI_AO_SYS1_Devices[i].d2_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_3,
+ PERI_AO_SYS1_Devices[i].d3_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_4,
+ PERI_AO_SYS1_Devices[i].d4_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_5,
+ PERI_AO_SYS1_Devices[i].d5_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_6,
+ PERI_AO_SYS1_Devices[i].d6_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS1, i, DOMAIN_7,
+ PERI_AO_SYS1_Devices[i].d7_permission);
+ }
+
+ peri_ao_size = ARRAY_SIZE(PERI_AO_SYS2_Devices);
+
+ for (i = 0; i < peri_ao_size; i++) {
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS2, i, DOMAIN_0,
+ PERI_AO_SYS2_Devices[i].d0_permission); /* APMCU */
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS2, i, DOMAIN_1,
+ PERI_AO_SYS2_Devices[i].d1_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS2, i, DOMAIN_2,
+ PERI_AO_SYS2_Devices[i].d2_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS2, i, DOMAIN_3,
+ PERI_AO_SYS2_Devices[i].d3_permission);
+ }
+}
+
+static void set_peri_ao2_apc(void)
+{
+ uint32_t peri_ao2_size;
+ uint32_t i;
+
+ peri_ao2_size = ARRAY_SIZE(PERI_AO2_SYS0_Devices);
+
+ for (i = 0; i < peri_ao2_size; i++) {
+ set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_0,
+ PERI_AO2_SYS0_Devices[i].d0_permission); /* APMCU */
+ set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_1,
+ PERI_AO2_SYS0_Devices[i].d1_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_2,
+ PERI_AO2_SYS0_Devices[i].d2_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_3,
+ PERI_AO2_SYS0_Devices[i].d3_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_4,
+ PERI_AO2_SYS0_Devices[i].d4_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_5,
+ PERI_AO2_SYS0_Devices[i].d5_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_6,
+ PERI_AO2_SYS0_Devices[i].d6_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_7,
+ PERI_AO2_SYS0_Devices[i].d7_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_8,
+ PERI_AO2_SYS0_Devices[i].d8_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_9,
+ PERI_AO2_SYS0_Devices[i].d9_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_10,
+ PERI_AO2_SYS0_Devices[i].d10_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_11,
+ PERI_AO2_SYS0_Devices[i].d11_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_12,
+ PERI_AO2_SYS0_Devices[i].d12_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_13,
+ PERI_AO2_SYS0_Devices[i].d13_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_14,
+ PERI_AO2_SYS0_Devices[i].d14_permission);
+ set_module_apc(SLAVE_TYPE_PERI_AO2_SYS0, i, DOMAIN_15,
+ PERI_AO2_SYS0_Devices[i].d15_permission);
+ }
+}
+
+static void set_peri_par_ao_apc(void)
+{
+ uint32_t peri_par_ao_size;
+ uint32_t i;
+
+ peri_par_ao_size = ARRAY_SIZE(PERI_PAR_AO_SYS0_Devices);
+
+ for (i = 0; i < peri_par_ao_size; i++) {
+ set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_0,
+ PERI_PAR_AO_SYS0_Devices[i].d0_permission); /* APMCU */
+ set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_1,
+ PERI_PAR_AO_SYS0_Devices[i].d1_permission);
+ set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_2,
+ PERI_PAR_AO_SYS0_Devices[i].d2_permission);
+ set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_3,
+ PERI_PAR_AO_SYS0_Devices[i].d3_permission);
+ set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_4,
+ PERI_PAR_AO_SYS0_Devices[i].d4_permission);
+ set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_5,
+ PERI_PAR_AO_SYS0_Devices[i].d5_permission);
+ set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_6,
+ PERI_PAR_AO_SYS0_Devices[i].d6_permission);
+ set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_7,
+ PERI_PAR_AO_SYS0_Devices[i].d7_permission);
+ set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_8,
+ PERI_PAR_AO_SYS0_Devices[i].d8_permission);
+ set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_9,
+ PERI_PAR_AO_SYS0_Devices[i].d9_permission);
+ set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_10,
+ PERI_PAR_AO_SYS0_Devices[i].d10_permission);
+ set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_11,
+ PERI_PAR_AO_SYS0_Devices[i].d11_permission);
+ set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_12,
+ PERI_PAR_AO_SYS0_Devices[i].d12_permission);
+ set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_13,
+ PERI_PAR_AO_SYS0_Devices[i].d13_permission);
+ set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_14,
+ PERI_PAR_AO_SYS0_Devices[i].d14_permission);
+ set_module_apc(SLAVE_TYPE_PERI_PAR_AO_SYS0, i, DOMAIN_15,
+ PERI_PAR_AO_SYS0_Devices[i].d15_permission);
+ }
+}
+
+static void set_extra_apc(void)
+{
+#ifdef MTK_DEBUGSYS_LOCK
+ /* Block debugsys to avoid privilege escalation (user load only) */
+ set_module_apc(SLAVE_TYPE_PERI_AO_SYS0, DEVAPC_DEBUGSYS_INDEX,
+ DOMAIN_0, SEC_RW_NS_R);
+#endif
+}
+
+void devapc_init(void)
+{
+ /* Initial Permission */
+ set_infra_ao_apc();
+ set_peri_ao_apc();
+ set_peri_ao2_apc();
+ set_peri_par_ao_apc();
+
+ /* Extra Permission */
+ set_extra_apc();
+
+ /* Dump Permission */
+ dump_infra_ao_apc();
+ dump_peri_ao_apc();
+ dump_peri_ao2_apc();
+ dump_peri_par_ao_apc();
+
+ /* Setup APUSYS Permission */
+ set_apusys_apc();
+
+ INFO("[DEVAPC] %s done\n", __func__);
+}
diff --git a/plat/mediatek/mt8192/drivers/devapc/devapc.h b/plat/mediatek/mt8192/drivers/devapc/devapc.h
new file mode 100644
index 0000000..9033a0f
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/devapc/devapc.h
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef DEVAPC_H
+#define DEVAPC_H
+
+#include <stdint.h>
+#include <platform_def.h>
+
+/******************************************************************************
+ * FUNCTION DEFINITION
+ ******************************************************************************/
+void devapc_init(void);
+
+/******************************************************************************
+ * STRUCTURE DEFINITION
+ ******************************************************************************/
+enum DEVAPC_PERM_TYPE {
+ NO_PROTECTION = 0,
+ SEC_RW_ONLY,
+ SEC_RW_NS_R,
+ FORBIDDEN,
+ PERM_NUM,
+};
+
+enum DOMAIN_ID {
+ DOMAIN_0 = 0,
+ DOMAIN_1,
+ DOMAIN_2,
+ DOMAIN_3,
+ DOMAIN_4,
+ DOMAIN_5,
+ DOMAIN_6,
+ DOMAIN_7,
+ DOMAIN_8,
+ DOMAIN_9,
+ DOMAIN_10,
+ DOMAIN_11,
+ DOMAIN_12,
+ DOMAIN_13,
+ DOMAIN_14,
+ DOMAIN_15,
+};
+
+/* Slave Type */
+enum DEVAPC_SLAVE_TYPE_SIMPLE {
+ SLAVE_TYPE_INFRA = 0,
+ SLAVE_TYPE_PERI,
+ SLAVE_TYPE_PERI2,
+ SLAVE_TYPE_PERI_PAR,
+};
+
+enum DEVAPC_SYS_INDEX {
+ DEVAPC_SYS0 = 0,
+ DEVAPC_SYS1,
+ DEVAPC_SYS2,
+};
+
+enum DEVAPC_SLAVE_TYPE {
+ SLAVE_TYPE_INFRA_AO_SYS0 = 0,
+ SLAVE_TYPE_INFRA_AO_SYS1,
+ SLAVE_TYPE_INFRA_AO_SYS2,
+ SLAVE_TYPE_PERI_AO_SYS0,
+ SLAVE_TYPE_PERI_AO_SYS1,
+ SLAVE_TYPE_PERI_AO_SYS2,
+ SLAVE_TYPE_PERI_AO2_SYS0,
+ SLAVE_TYPE_PERI_PAR_AO_SYS0,
+};
+
+/* Slave Num */
+enum DEVAPC_SLAVE_NUM {
+ SLAVE_NUM_INFRA_AO_SYS0 = 23,
+ SLAVE_NUM_INFRA_AO_SYS1 = 256,
+ SLAVE_NUM_INFRA_AO_SYS2 = 70,
+ SLAVE_NUM_PERI_AO_SYS0 = 105,
+ SLAVE_NUM_PERI_AO_SYS1 = 66,
+ SLAVE_NUM_PERI_AO_SYS2 = 1,
+ SLAVE_NUM_PERI_AO2_SYS0 = 115,
+ SLAVE_NUM_PERI_PAR_AO_SYS0 = 27,
+};
+
+enum DEVAPC_SYS_DOM_NUM {
+ DOM_NUM_INFRA_AO_SYS0 = 16,
+ DOM_NUM_INFRA_AO_SYS1 = 4,
+ DOM_NUM_INFRA_AO_SYS2 = 4,
+ DOM_NUM_PERI_AO_SYS0 = 16,
+ DOM_NUM_PERI_AO_SYS1 = 8,
+ DOM_NUM_PERI_AO_SYS2 = 4,
+ DOM_NUM_PERI_AO2_SYS0 = 16,
+ DOM_NUM_PERI_PAR_AO_SYS0 = 16,
+};
+
+enum DEVAPC_CFG_INDEX {
+ DEVAPC_DEBUGSYS_INDEX = 57,
+};
+
+struct APC_INFRA_PERI_DOM_16 {
+ unsigned char d0_permission;
+ unsigned char d1_permission;
+ unsigned char d2_permission;
+ unsigned char d3_permission;
+ unsigned char d4_permission;
+ unsigned char d5_permission;
+ unsigned char d6_permission;
+ unsigned char d7_permission;
+ unsigned char d8_permission;
+ unsigned char d9_permission;
+ unsigned char d10_permission;
+ unsigned char d11_permission;
+ unsigned char d12_permission;
+ unsigned char d13_permission;
+ unsigned char d14_permission;
+ unsigned char d15_permission;
+};
+
+struct APC_INFRA_PERI_DOM_8 {
+ unsigned char d0_permission;
+ unsigned char d1_permission;
+ unsigned char d2_permission;
+ unsigned char d3_permission;
+ unsigned char d4_permission;
+ unsigned char d5_permission;
+ unsigned char d6_permission;
+ unsigned char d7_permission;
+};
+
+struct APC_INFRA_PERI_DOM_4 {
+ unsigned char d0_permission;
+ unsigned char d1_permission;
+ unsigned char d2_permission;
+ unsigned char d3_permission;
+};
+
+#define DAPC_INFRA_AO_SYS0_ATTR(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \
+ PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \
+ PERM_ATTR6, PERM_ATTR7, PERM_ATTR8, PERM_ATTR9, \
+ PERM_ATTR10, PERM_ATTR11, PERM_ATTR12, PERM_ATTR13, \
+ PERM_ATTR14, PERM_ATTR15) \
+ {(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \
+ (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, \
+ (unsigned char)PERM_ATTR4, (unsigned char)PERM_ATTR5, \
+ (unsigned char)PERM_ATTR6, (unsigned char)PERM_ATTR7, \
+ (unsigned char)PERM_ATTR8, (unsigned char)PERM_ATTR9, \
+ (unsigned char)PERM_ATTR10, (unsigned char)PERM_ATTR11, \
+ (unsigned char)PERM_ATTR12, (unsigned char)PERM_ATTR13, \
+ (unsigned char)PERM_ATTR14, (unsigned char)PERM_ATTR15}
+
+#define DAPC_INFRA_AO_SYS1_ATTR(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \
+ PERM_ATTR2, PERM_ATTR3) \
+ {(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \
+ (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3}
+
+#define DAPC_PERI_AO_SYS1_ATTR(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \
+ PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \
+ PERM_ATTR6, PERM_ATTR7) \
+ {(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \
+ (unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, \
+ (unsigned char)PERM_ATTR4, (unsigned char)PERM_ATTR5, \
+ (unsigned char)PERM_ATTR6, (unsigned char)PERM_ATTR7}
+
+#define DAPC_INFRA_AO_SYS2_ATTR(...) DAPC_INFRA_AO_SYS1_ATTR(__VA_ARGS__)
+#define DAPC_PERI_AO_SYS0_ATTR(...) DAPC_INFRA_AO_SYS0_ATTR(__VA_ARGS__)
+#define DAPC_PERI_AO_SYS2_ATTR(...) DAPC_INFRA_AO_SYS1_ATTR(__VA_ARGS__)
+#define DAPC_PERI_AO2_SYS0_ATTR(...) DAPC_INFRA_AO_SYS0_ATTR(__VA_ARGS__)
+#define DAPC_PERI_PAR_AO_SYS0_ATTR(...) DAPC_INFRA_AO_SYS0_ATTR(__VA_ARGS__)
+
+/******************************************************************************
+ * UTILITY DEFINITION
+ ******************************************************************************/
+#define devapc_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL)
+#define devapc_readl(REG) mmio_read_32((uintptr_t)REG)
+
+/******************************************************************************/
+/* Device APC AO for INFRA AO */
+#define DEVAPC_INFRA_AO_SYS0_D0_APC_0 (DEVAPC_INFRA_AO_BASE + 0x0000)
+#define DEVAPC_INFRA_AO_SYS1_D0_APC_0 (DEVAPC_INFRA_AO_BASE + 0x1000)
+#define DEVAPC_INFRA_AO_SYS2_D0_APC_0 (DEVAPC_INFRA_AO_BASE + 0x2000)
+
+#define DEVAPC_INFRA_AO_MAS_SEC_0 (DEVAPC_INFRA_AO_BASE + 0x0A00)
+
+/******************************************************************************/
+/* Device APC AO for PERI AO */
+#define DEVAPC_PERI_AO_SYS0_D0_APC_0 (DEVAPC_PERI_AO_BASE + 0x0000)
+#define DEVAPC_PERI_AO_SYS1_D0_APC_0 (DEVAPC_PERI_AO_BASE + 0x1000)
+#define DEVAPC_PERI_AO_SYS2_D0_APC_0 (DEVAPC_PERI_AO_BASE + 0x2000)
+
+#define DEVAPC_PERI_AO_MAS_SEC_0 (DEVAPC_PERI_AO_BASE + 0x0A00)
+
+/******************************************************************************/
+/* Device APC AO for PERI AO2 */
+#define DEVAPC_PERI_AO2_SYS0_D0_APC_0 (DEVAPC_PERI_AO2_BASE + 0x0000)
+
+/******************************************************************************/
+/* Device APC AO for PERI PAR AO */
+#define DEVAPC_PERI_PAR_AO_SYS0_D0_APC_0 (DEVAPC_PERI_PAR_AO_BASE + 0x0000)
+
+#define DEVAPC_PERI_PAR_AO_MAS_SEC_0 (DEVAPC_PERI_PAR_AO_BASE + 0x0A00)
+
+/******************************************************************************/
+
+
+/******************************************************************************
+ * Variable DEFINITION
+ ******************************************************************************/
+#define MOD_NO_IN_1_DEVAPC 16
+
+#endif /* DEVAPC_H */
+
diff --git a/plat/mediatek/mt8192/drivers/dfd/plat_dfd.c b/plat/mediatek/mt8192/drivers/dfd/plat_dfd.c
new file mode 100644
index 0000000..69c395e
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/dfd/plat_dfd.c
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <mtk_sip_svc.h>
+#include <plat_dfd.h>
+
+static bool dfd_enabled;
+static uint64_t dfd_base_addr;
+static uint64_t dfd_chain_length;
+static uint64_t dfd_cache_dump;
+
+static void dfd_setup(uint64_t base_addr, uint64_t chain_length,
+ uint64_t cache_dump)
+{
+ /* bit[0]: rg_rw_dfd_internal_dump_en -> 1 */
+ /* bit[2]: rg_rw_dfd_clock_stop_en -> 1 */
+ sync_writel(DFD_INTERNAL_CTL, 0x5);
+
+ /* bit[13]: xreset_b_update_disable */
+ mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 13);
+
+ /*
+ * bit[10:3]: DFD trigger selection mask
+ * bit[3]: rg_rw_dfd_trigger_sel[0] = 1(enable wdt trigger)
+ * bit[4]: rg_rw_dfd_trigger_sel[1] = 1(enable HW trigger)
+ * bit[5]: rg_rw_dfd_trigger_sel[2] = 1(enable SW trigger)
+ * bit[6]: rg_rw_dfd_trigger_sel[3] = 1(enable SW non-security trigger)
+ * bit[7]: rg_rw_dfd_trigger_sel[4] = 1(enable timer trigger)
+ */
+ mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 3);
+
+ /* bit[20:19]: rg_dfd_armpll_div_mux_sel switch to PLL2 for DFD */
+ mmio_setbits_32(DFD_INTERNAL_CTL, 0x3 << 19);
+
+ /*
+ * bit[0]: rg_rw_dfd_auto_power_on = 1
+ * bit[2:1]: rg_rw_dfd_auto_power_on_dely = 1(10us)
+ * bit[4:2]: rg_rw_dfd_power_on_wait_time = 1(20us)
+ */
+ mmio_write_32(DFD_INTERNAL_PWR_ON, 0xB);
+
+ /* longest scan chain length */
+ mmio_write_32(DFD_CHAIN_LENGTH0, chain_length);
+
+ /* bit[1:0]: rg_rw_dfd_shift_clock_ratio */
+ mmio_write_32(DFD_INTERNAL_SHIFT_CLK_RATIO, 0x0);
+
+ /* rg_dfd_test_so_over_64 */
+ mmio_write_32(DFD_INTERNAL_TEST_SO_OVER_64, 0x1);
+
+ /* DFD3.0 */
+ mmio_write_32(DFD_TEST_SI_0, DFD_TEST_SI_0_CACHE_DIS_VAL);
+ mmio_write_32(DFD_TEST_SI_1, DFD_TEST_SI_1_VAL);
+ mmio_write_32(DFD_TEST_SI_2, DFD_TEST_SI_2_VAL);
+ mmio_write_32(DFD_TEST_SI_3, DFD_TEST_SI_3_VAL);
+
+ /* for iLDO feature */
+ sync_writel(DFD_POWER_CTL, 0xF9);
+
+ /* set base address */
+ mmio_write_32(DFD_O_SET_BASEADDR_REG, base_addr >> 24);
+
+ /*
+ * disable sleep protect of DFD
+ * 10001220[8]: protect_en_reg[8]
+ * 10001a3c[2]: infra_mcu_pwr_ctl_mask[2]
+ */
+ mmio_clrbits_32(DFD_O_PROTECT_EN_REG, 1 << 8);
+ mmio_clrbits_32(DFD_O_INTRF_MCU_PWR_CTL_MASK, 1 << 2);
+
+ /* clean DFD trigger status */
+ sync_writel(DFD_CLEAN_STATUS, 0x1);
+ sync_writel(DFD_CLEAN_STATUS, 0x0);
+
+ /* DFD-3.0 */
+ sync_writel(DFD_V30_CTL, 0x1);
+
+ /* setup global variables for suspend and resume */
+ dfd_enabled = true;
+ dfd_base_addr = base_addr;
+ dfd_chain_length = chain_length;
+ dfd_cache_dump = cache_dump;
+
+ if ((cache_dump & DFD_CACHE_DUMP_ENABLE) != 0UL) {
+ /* DFD3.5 */
+ mmio_write_32(DFD_TEST_SI_0, DFD_TEST_SI_0_CACHE_EN_VAL);
+ sync_writel(DFD_V35_ENALBE, 0x1);
+ sync_writel(DFD_V35_TAP_NUMBER, 0xB);
+ sync_writel(DFD_V35_TAP_EN, DFD_V35_TAP_EN_VAL);
+ sync_writel(DFD_V35_SEQ0_0, DFD_V35_SEQ0_0_VAL);
+
+ if (cache_dump & DFD_PARITY_ERR_TRIGGER) {
+ sync_writel(DFD_HW_TRIGGER_MASK, 0xC);
+ mmio_setbits_32(DFD_INTERNAL_CTL, 0x1 << 4);
+ }
+ }
+ dsbsy();
+}
+
+void dfd_resume(void)
+{
+ if (dfd_enabled == true) {
+ dfd_setup(dfd_base_addr, dfd_chain_length, dfd_cache_dump);
+ }
+}
+
+uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1,
+ uint64_t arg2, uint64_t arg3)
+{
+ uint64_t ret = 0L;
+
+ switch (arg0) {
+ case PLAT_MTK_DFD_SETUP_MAGIC:
+ dfd_setup(arg1, arg2, arg3);
+ break;
+ case PLAT_MTK_DFD_READ_MAGIC:
+ /* only allow to access DFD register base + 0x200 */
+ if (arg1 <= 0x200) {
+ ret = mmio_read_32(MISC1_CFG_BASE + arg1);
+ }
+ break;
+ case PLAT_MTK_DFD_WRITE_MAGIC:
+ /* only allow to access DFD register base + 0x200 */
+ if (arg1 <= 0x200) {
+ sync_writel(MISC1_CFG_BASE + arg1, arg2);
+ }
+ break;
+ default:
+ ret = MTK_SIP_E_INVALID_PARAM;
+ break;
+ }
+
+ return ret;
+}
diff --git a/plat/mediatek/mt8192/drivers/dfd/plat_dfd.h b/plat/mediatek/mt8192/drivers/dfd/plat_dfd.h
new file mode 100644
index 0000000..7f0f4b5
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/dfd/plat_dfd.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_DFD_H
+#define PLAT_DFD_H
+
+#include <arch_helpers.h>
+#include <lib/mmio.h>
+#include <platform_def.h>
+
+#define sync_writel(addr, val) do { mmio_write_32((addr), (val)); \
+ dsbsy(); \
+ } while (0)
+
+#define PLAT_MTK_DFD_SETUP_MAGIC (0x99716150)
+#define PLAT_MTK_DFD_READ_MAGIC (0x99716151)
+#define PLAT_MTK_DFD_WRITE_MAGIC (0x99716152)
+
+#define MCU_BIU_BASE (MCUCFG_BASE)
+#define MISC1_CFG_BASE (MCU_BIU_BASE + 0xE040)
+#define DFD_INTERNAL_CTL (MISC1_CFG_BASE + 0x00)
+#define DFD_INTERNAL_PWR_ON (MISC1_CFG_BASE + 0x08)
+#define DFD_CHAIN_LENGTH0 (MISC1_CFG_BASE + 0x0C)
+#define DFD_INTERNAL_SHIFT_CLK_RATIO (MISC1_CFG_BASE + 0x10)
+#define DFD_CHAIN_LENGTH1 (MISC1_CFG_BASE + 0x1C)
+#define DFD_CHAIN_LENGTH2 (MISC1_CFG_BASE + 0x20)
+#define DFD_CHAIN_LENGTH3 (MISC1_CFG_BASE + 0x24)
+#define DFD_INTERNAL_TEST_SO_0 (MISC1_CFG_BASE + 0x28)
+#define DFD_INTERNAL_NUM_OF_TEST_SO_GROUP (MISC1_CFG_BASE + 0x30)
+#define DFD_INTERNAL_TEST_SO_OVER_64 (MISC1_CFG_BASE + 0x34)
+#define DFD_V30_CTL (MISC1_CFG_BASE + 0x48)
+#define DFD_V30_BASE_ADDR (MISC1_CFG_BASE + 0x4C)
+#define DFD_POWER_CTL (MISC1_CFG_BASE + 0x50)
+#define DFD_TEST_SI_0 (MISC1_CFG_BASE + 0x58)
+#define DFD_TEST_SI_1 (MISC1_CFG_BASE + 0x5C)
+#define DFD_CLEAN_STATUS (MISC1_CFG_BASE + 0x60)
+#define DFD_TEST_SI_2 (MISC1_CFG_BASE + 0x1D8)
+#define DFD_TEST_SI_3 (MISC1_CFG_BASE + 0x1DC)
+#define DFD_HW_TRIGGER_MASK (MISC1_CFG_BASE + 0xBC)
+
+#define DFD_V35_ENALBE (MCU_BIU_BASE + 0xE0A8)
+#define DFD_V35_TAP_NUMBER (MCU_BIU_BASE + 0xE0AC)
+#define DFD_V35_TAP_EN (MCU_BIU_BASE + 0xE0B0)
+#define DFD_V35_CTL (MCU_BIU_BASE + 0xE0B4)
+#define DFD_V35_SEQ0_0 (MCU_BIU_BASE + 0xE0C0)
+#define DFD_V35_SEQ0_1 (MCU_BIU_BASE + 0xE0C4)
+
+#define DFD_O_PROTECT_EN_REG (0x10001220)
+#define DFD_O_INTRF_MCU_PWR_CTL_MASK (0x10001A3C)
+#define DFD_O_SET_BASEADDR_REG (0x10043034)
+
+#define DFD_CACHE_DUMP_ENABLE 1U
+#define DFD_PARITY_ERR_TRIGGER 2U
+
+#define DFD_TEST_SI_0_CACHE_DIS_VAL (0x1E000202)
+#define DFD_TEST_SI_0_CACHE_EN_VAL (0x1E000002)
+#define DFD_TEST_SI_1_VAL (0x20408100)
+#define DFD_TEST_SI_2_VAL (0x10101000)
+#define DFD_TEST_SI_3_VAL (0x00000010)
+#define DFD_V35_TAP_EN_VAL (0x43FF)
+#define DFD_V35_SEQ0_0_VAL (0x63668820)
+
+void dfd_resume(void);
+uint64_t dfd_smc_dispatcher(uint64_t arg0, uint64_t arg1,
+ uint64_t arg2, uint64_t arg3);
+
+#endif /* PLAT_DFD_H */
diff --git a/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.c b/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.c
index d5d7e2e..26bed29 100644
--- a/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.c
+++ b/plat/mediatek/mt8192/drivers/emi_mpu/emi_mpu.c
@@ -91,30 +91,52 @@
void emi_mpu_init(void)
{
- /* Set permission */
struct emi_region_info_t region_info;
- /* PCE-e protect address(TODO) */
- region_info.start = 0x80000000ULL;
- region_info.end = 0x83FF0000ULL;
+ /* reserve region 0 for future use */
+
+ /* PCI-e protect address(64MB) */
+ region_info.start = 0xC0000000ULL;
+ region_info.end = 0xC3FF0000ULL;
region_info.region = 1;
SET_ACCESS_PERMISSION(region_info.apc, 1,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
- FORBIDDEN, FORBIDDEN, NO_PROT,
- NO_PROT /*FORBIDDEN*/);
+ FORBIDDEN, FORBIDDEN, NO_PROT, NO_PROT);
+ emi_mpu_set_protection(®ion_info);
+
+ /* SCP protect address */
+ region_info.start = 0x50000000ULL;
+ region_info.end = 0x513F0000ULL;
+ region_info.region = 2;
+ SET_ACCESS_PERMISSION(region_info.apc, 1,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ NO_PROT, FORBIDDEN, FORBIDDEN, NO_PROT);
+ emi_mpu_set_protection(®ion_info);
+
+ /* DSP protect address */
+ region_info.start = 0x40000000ULL; /* dram base addr */
+ region_info.end = 0x1FFFF0000ULL;
+ region_info.region = 3;
+ SET_ACCESS_PERMISSION(region_info.apc, 1,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROT);
emi_mpu_set_protection(®ion_info);
/* Forbidden All */
region_info.start = 0x40000000ULL; /* dram base addr */
region_info.end = 0x1FFFF0000ULL;
- region_info.region = 2;
+ region_info.region = 4;
SET_ACCESS_PERMISSION(region_info.apc, 1,
- NO_PROT, NO_PROT, NO_PROT, NO_PROT,
- NO_PROT, NO_PROT, NO_PROT, NO_PROT,
- NO_PROT, NO_PROT, NO_PROT, NO_PROT,
- NO_PROT, FORBIDDEN, NO_PROT, NO_PROT);
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, FORBIDDEN,
+ FORBIDDEN, FORBIDDEN, FORBIDDEN, NO_PROT);
emi_mpu_set_protection(®ion_info);
dump_emi_mpu_regions();
diff --git a/plat/mediatek/mt8192/drivers/gpio/mtgpio.c b/plat/mediatek/mt8192/drivers/gpio/mtgpio.c
index e07b75a..c78332d 100644
--- a/plat/mediatek/mt8192/drivers/gpio/mtgpio.c
+++ b/plat/mediatek/mt8192/drivers/gpio/mtgpio.c
@@ -5,94 +5,17 @@
*/
#include <assert.h>
-#include <common/debug.h>
-#include <drivers/delay_timer.h>
-#include <drivers/gpio.h>
-#include <lib/mmio.h>
#include <mtgpio.h>
#include <platform_def.h>
-/******************************************************************************
- *Macro Definition
- ******************************************************************************/
-#define GPIO_MODE_BITS 4
-#define MAX_GPIO_MODE_PER_REG 8
-#define MAX_GPIO_REG_BITS 32
-#define DIR_BASE (GPIO_BASE + 0x000)
-#define DOUT_BASE (GPIO_BASE + 0x100)
-#define DIN_BASE (GPIO_BASE + 0x200)
-#define MODE_BASE (GPIO_BASE + 0x300)
-#define SET 0x4
-#define CLR 0x8
-
-static void mt_set_gpio_dir_chip(uint32_t pin, int dir)
-{
- uint32_t pos, bit;
-
- assert(pin < MAX_GPIO_PIN);
- assert(dir < MT_GPIO_DIR_MAX);
-
- pos = pin / MAX_GPIO_REG_BITS;
- bit = pin % MAX_GPIO_REG_BITS;
-
- if (dir == MT_GPIO_DIR_IN) {
- mmio_write_32(DIR_BASE + 0x10U * pos + CLR, 1U << bit);
- } else {
- mmio_write_32(DIR_BASE + 0x10U * pos + SET, 1U << bit);
- }
-}
-
-static int mt_get_gpio_dir_chip(uint32_t pin)
-{
- uint32_t pos, bit;
- uint32_t reg;
-
- assert(pin < MAX_GPIO_PIN);
-
- pos = pin / MAX_GPIO_REG_BITS;
- bit = pin % MAX_GPIO_REG_BITS;
-
- reg = mmio_read_32(DIR_BASE + 0x10U * pos);
- return (((reg & (1U << bit)) != 0U) ? MT_GPIO_DIR_OUT : MT_GPIO_DIR_IN);
-}
-
-static void mt_set_gpio_out_chip(uint32_t pin, int output)
-{
- uint32_t pos, bit;
-
- assert(pin < MAX_GPIO_PIN);
- assert(output < MT_GPIO_OUT_MAX);
-
- pos = pin / MAX_GPIO_REG_BITS;
- bit = pin % MAX_GPIO_REG_BITS;
-
- if (output == MT_GPIO_OUT_ZERO) {
- mmio_write_32(DOUT_BASE + 0x10U * pos + CLR, 1U << bit);
- } else {
- mmio_write_32(DOUT_BASE + 0x10U * pos + SET, 1U << bit);
- }
-}
-
-static int mt_get_gpio_in_chip(uint32_t pin)
-{
- uint32_t pos, bit;
- uint32_t reg;
-
- assert(pin < MAX_GPIO_PIN);
-
- pos = pin / MAX_GPIO_REG_BITS;
- bit = pin % MAX_GPIO_REG_BITS;
-
- reg = mmio_read_32(DIN_BASE + 0x10U * pos);
- return (((reg & (1U << bit)) != 0U) ? 1 : 0);
-}
-
-static uintptr_t mt_gpio_find_reg_addr(uint32_t pin)
+uintptr_t mt_gpio_find_reg_addr(uint32_t pin)
{
uintptr_t reg_addr = 0U;
struct mt_pin_info gpio_info;
- gpio_info = mt8192_pin_infos[pin];
+ assert(pin < MAX_GPIO_PIN);
+
+ gpio_info = mt_pin_infos[pin];
switch (gpio_info.base & 0x0f) {
case 0:
@@ -128,213 +51,3 @@
return reg_addr;
}
-
-static void mt_gpio_set_spec_pull_pupd(uint32_t pin, int enable,
- int select)
-{
- uintptr_t reg1;
- uintptr_t reg2;
- struct mt_pin_info gpio_info;
-
- gpio_info = mt8192_pin_infos[pin];
- uint32_t bit = gpio_info.bit;
-
- reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
- reg2 = reg1 + (gpio_info.base & 0xf0);
- if (enable == MT_GPIO_PULL_ENABLE) {
- mmio_write_32(reg2 + SET, (1U << bit));
- if (select == MT_GPIO_PULL_DOWN) {
- mmio_write_32(reg1 + SET, (1U << bit));
- } else {
- mmio_write_32(reg1 + CLR, (1U << bit));
- }
- } else {
- mmio_write_32(reg2 + CLR, (1U << bit));
- mmio_write_32((reg2 + 0x010U) + CLR, (1U << bit));
- }
-}
-
-static void mt_gpio_set_pull_pu_pd(uint32_t pin, int enable,
- int select)
-{
- uintptr_t reg1;
- uintptr_t reg2;
- struct mt_pin_info gpio_info;
-
- gpio_info = mt8192_pin_infos[pin];
- uint32_t bit = gpio_info.bit;
-
- reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
- reg2 = reg1 - (gpio_info.base & 0xf0);
-
- if (enable == MT_GPIO_PULL_ENABLE) {
- if (select == MT_GPIO_PULL_DOWN) {
- mmio_write_32(reg1 + CLR, (1U << bit));
- mmio_write_32(reg2 + SET, (1U << bit));
- } else {
- mmio_write_32(reg2 + CLR, (1U << bit));
- mmio_write_32(reg1 + SET, (1U << bit));
- }
- } else {
- mmio_write_32(reg1 + CLR, (1U << bit));
- mmio_write_32(reg2 + CLR, (1U << bit));
- }
-}
-
-static void mt_gpio_set_pull_chip(uint32_t pin, int enable,
- int select)
-{
- struct mt_pin_info gpio_info;
-
- gpio_info = mt8192_pin_infos[pin];
- if (gpio_info.flag) {
- mt_gpio_set_spec_pull_pupd(pin, enable, select);
- } else {
- mt_gpio_set_pull_pu_pd(pin, enable, select);
- }
-}
-
-static int mt_gpio_get_spec_pull_pupd(uint32_t pin)
-{
- uintptr_t reg1;
- uintptr_t reg2;
- uint32_t r0;
- uint32_t r1;
-
- struct mt_pin_info gpio_info;
-
- gpio_info = mt8192_pin_infos[pin];
- uint32_t bit = gpio_info.bit;
-
- reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
- reg2 = reg1 + (gpio_info.base & 0xf0);
-
- r0 = (mmio_read_32(reg2) >> bit) & 1U;
- r1 = (mmio_read_32(reg2 + 0x010) >> bit) & 1U;
- if (r0 == 0U && r1 == 0U) {
- return MT_GPIO_PULL_NONE;
- } else {
- if (mmio_read_32(reg1) & (1U << bit)) {
- return MT_GPIO_PULL_DOWN;
- } else {
- return MT_GPIO_PULL_UP;
- }
- }
-}
-
-static int mt_gpio_get_pull_pu_pd(uint32_t pin)
-{
- uintptr_t reg1;
- uintptr_t reg2;
- uint32_t pu;
- uint32_t pd;
-
- struct mt_pin_info gpio_info;
-
- gpio_info = mt8192_pin_infos[pin];
- uint32_t bit = gpio_info.bit;
-
- reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
- reg2 = reg1 - (gpio_info.base & 0xf0);
- pu = (mmio_read_32(reg1) >> bit) & 1U;
- pd = (mmio_read_32(reg2) >> bit) & 1U;
- if (pu == 1U) {
- return MT_GPIO_PULL_UP;
- } else if (pd == 1U) {
- return MT_GPIO_PULL_DOWN;
- } else {
- return MT_GPIO_PULL_NONE;
- }
-}
-
-static int mt_gpio_get_pull_chip(uint32_t pin)
-{
- struct mt_pin_info gpio_info;
-
- gpio_info = mt8192_pin_infos[pin];
- if (gpio_info.flag) {
- return mt_gpio_get_spec_pull_pupd(pin);
- } else {
- return mt_gpio_get_pull_pu_pd(pin);
- }
-}
-
-static void mt_set_gpio_pull_select_chip(uint32_t pin, int sel)
-{
- assert(pin < MAX_GPIO_PIN);
-
- if (sel == MT_GPIO_PULL_NONE) {
- mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_DISABLE, MT_GPIO_PULL_DOWN);
- } else if (sel == MT_GPIO_PULL_UP) {
- mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_ENABLE, MT_GPIO_PULL_UP);
- } else if (sel == MT_GPIO_PULL_DOWN) {
- mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_ENABLE, MT_GPIO_PULL_DOWN);
- }
-}
-
-/* get pull-up or pull-down, regardless of resistor value */
-static int mt_get_gpio_pull_select_chip(uint32_t pin)
-{
- assert(pin < MAX_GPIO_PIN);
-
- return mt_gpio_get_pull_chip(pin);
-}
-
-static void mt_set_gpio_dir(int gpio, int direction)
-{
- mt_set_gpio_dir_chip((uint32_t)gpio, direction);
-}
-
-static int mt_get_gpio_dir(int gpio)
-{
- uint32_t pin;
-
- pin = (uint32_t)gpio;
- return mt_get_gpio_dir_chip(pin);
-}
-
-static void mt_set_gpio_pull(int gpio, int pull)
-{
- uint32_t pin;
-
- pin = (uint32_t)gpio;
- mt_set_gpio_pull_select_chip(pin, pull);
-}
-
-static int mt_get_gpio_pull(int gpio)
-{
- uint32_t pin;
-
- pin = (uint32_t)gpio;
- return mt_get_gpio_pull_select_chip(pin);
-}
-
-static void mt_set_gpio_out(int gpio, int value)
-{
- uint32_t pin;
-
- pin = (uint32_t)gpio;
- mt_set_gpio_out_chip(pin, value);
-}
-
-static int mt_get_gpio_in(int gpio)
-{
- uint32_t pin;
-
- pin = (uint32_t)gpio;
- return mt_get_gpio_in_chip(pin);
-}
-
-const gpio_ops_t mtgpio_ops = {
- .get_direction = mt_get_gpio_dir,
- .set_direction = mt_set_gpio_dir,
- .get_value = mt_get_gpio_in,
- .set_value = mt_set_gpio_out,
- .set_pull = mt_set_gpio_pull,
- .get_pull = mt_get_gpio_pull,
-};
-
-void plat_mt8192_gpio_init(void)
-{
- gpio_init(&mtgpio_ops);
-}
diff --git a/plat/mediatek/mt8192/drivers/gpio/mtgpio.h b/plat/mediatek/mt8192/drivers/gpio/mtgpio.h
index ca0c964..d3aa24d 100644
--- a/plat/mediatek/mt8192/drivers/gpio/mtgpio.h
+++ b/plat/mediatek/mt8192/drivers/gpio/mtgpio.h
@@ -7,17 +7,7 @@
#ifndef MT_GPIO_H
#define MT_GPIO_H
-#include <stdbool.h>
-#include <stdint.h>
-
-#include <plat/common/common_def.h>
-
-/* Error Code No. */
-#define RSUCCESS 0
-#define ERACCESS 1
-#define ERINVAL 2
-#define ERWRAPPER 3
-#define MAX_GPIO_PIN MT_GPIO_BASE_MAX
+#include <mtgpio_common.h>
/* Enumeration for GPIO pin */
typedef enum GPIO_PIN {
@@ -54,110 +44,7 @@
MT_GPIO_BASE_MAX
} GPIO_PIN;
-/* GPIO MODE CONTROL VALUE*/
-typedef enum {
- GPIO_MODE_UNSUPPORTED = -1,
- GPIO_MODE_GPIO = 0,
- GPIO_MODE_00 = 0,
- GPIO_MODE_01,
- GPIO_MODE_02,
- GPIO_MODE_03,
- GPIO_MODE_04,
- GPIO_MODE_05,
- GPIO_MODE_06,
- GPIO_MODE_07,
-
- GPIO_MODE_MAX,
- GPIO_MODE_DEFAULT = GPIO_MODE_00,
-} GPIO_MODE;
-
-/* GPIO DIRECTION */
-typedef enum {
- MT_GPIO_DIR_UNSUPPORTED = -1,
- MT_GPIO_DIR_OUT = 0,
- MT_GPIO_DIR_IN = 1,
- MT_GPIO_DIR_MAX,
- MT_GPIO_DIR_DEFAULT = MT_GPIO_DIR_IN,
-} GPIO_DIR;
-
-/* GPIO PULL ENABLE*/
-typedef enum {
- MT_GPIO_PULL_EN_UNSUPPORTED = -1,
- MT_GPIO_PULL_DISABLE = 0,
- MT_GPIO_PULL_ENABLE = 1,
- MT_GPIO_PULL_ENABLE_R0 = 2,
- MT_GPIO_PULL_ENABLE_R1 = 3,
- MT_GPIO_PULL_ENABLE_R0R1 = 4,
-
- MT_GPIO_PULL_EN_MAX,
- MT_GPIO_PULL_EN_DEFAULT = MT_GPIO_PULL_ENABLE,
-} GPIO_PULL_EN;
-
-/* GPIO PULL-UP/PULL-DOWN*/
-typedef enum {
- MT_GPIO_PULL_UNSUPPORTED = -1,
- MT_GPIO_PULL_NONE = 0,
- MT_GPIO_PULL_UP = 1,
- MT_GPIO_PULL_DOWN = 2,
- MT_GPIO_PULL_MAX,
- MT_GPIO_PULL_DEFAULT = MT_GPIO_PULL_DOWN
-} GPIO_PULL;
-
-/* GPIO OUTPUT */
-typedef enum {
- MT_GPIO_OUT_UNSUPPORTED = -1,
- MT_GPIO_OUT_ZERO = 0,
- MT_GPIO_OUT_ONE = 1,
-
- MT_GPIO_OUT_MAX,
- MT_GPIO_OUT_DEFAULT = MT_GPIO_OUT_ZERO,
- MT_GPIO_DATA_OUT_DEFAULT = MT_GPIO_OUT_ZERO, /*compatible with DCT*/
-} GPIO_OUT;
-
-/* GPIO INPUT */
-typedef enum {
- MT_GPIO_IN_UNSUPPORTED = -1,
- MT_GPIO_IN_ZERO = 0,
- MT_GPIO_IN_ONE = 1,
-
- MT_GPIO_IN_MAX,
-} GPIO_IN;
-
-typedef struct {
- uint32_t val;
- uint32_t set;
- uint32_t rst;
- uint32_t _align1;
-} VAL_REGS;
-
-typedef struct {
- VAL_REGS dir[7];
- uint8_t rsv00[144];
- VAL_REGS dout[7];
- uint8_t rsv01[144];
- VAL_REGS din[7];
- uint8_t rsv02[144];
- VAL_REGS mode[28];
-} GPIO_REGS;
-
-
-#define PIN(_id, _flag, _bit, _base, _offset) { \
- .id = _id, \
- .flag = _flag, \
- .bit = _bit, \
- .base = _base, \
- .offset = _offset, \
- }
-
-struct mt_pin_info {
- uint8_t id;
- uint8_t flag;
- uint8_t bit;
- uint16_t base;
- uint16_t offset;
-};
-
-static const struct mt_pin_info mt8192_pin_infos[] = {
+static const struct mt_pin_info mt_pin_infos[] = {
PIN(0, 0, 9, 0x23, 0xb0),
PIN(1, 0, 10, 0x23, 0xb0),
PIN(2, 0, 11, 0x23, 0xb0),
@@ -379,6 +266,4 @@
PIN(218, 0, 1, 0x14, 0x50),
PIN(219, 0, 2, 0x14, 0x50),
};
-
-void plat_mt8192_gpio_init(void);
#endif /* MT_GPIO_H */
diff --git a/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm.c b/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm.c
index d6d4af7..b483c36 100644
--- a/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm.c
+++ b/plat/mediatek/mt8192/drivers/mcdi/mt_cpu_pm.c
@@ -12,6 +12,8 @@
#include <lib/spinlock.h>
#include <mt_cpu_pm_cpc.h>
+#include <mt_lp_irqremain.h>
+#include <mt_lp_rm.h>
#include <mt_mcdi.h>
#include <plat_mtk_lpm.h>
#include <plat_pm.h>
@@ -73,27 +75,49 @@
static int pwr_mcusys_pwron_finished(unsigned int cpu,
const psci_power_state_t *state)
{
+ int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS];
+
if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) {
return -1;
}
+ mt_lp_rm_reset_constraint(plat_mt_lp_cpu_rc, cpu, state_id);
+ mt_lp_irqremain_release();
+
return 0;
}
static int pwr_mcusys_pwrdwn(unsigned int cpu, const psci_power_state_t *state)
{
+ int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS];
+
if (!IS_MCUSYS_OFF_STATE(state)) {
goto mt_pwr_mcusysoff_break;
}
- if (mcdi_try_init() != 0) { /* not ready to process mcusys-off */
+ if (mcdi_try_init() != 0) {
goto mt_pwr_mcusysoff_break;
}
+ if (mtk_cpc_mcusys_off_prepare() != CPC_SUCCESS) {
+ goto mt_pwr_mcusysoff_break;
+ }
+
+ plat_mt_lp_cpu_rc =
+ mt_lp_rm_find_and_run_constraint(0, cpu, state_id, NULL);
+
+ if (plat_mt_lp_cpu_rc < 0) {
+ goto mt_pwr_mcusysoff_reflect;
+ }
+
+ mt_lp_irqremain_aquire();
+
return 0;
-mt_pwr_mcusysoff_break:
+mt_pwr_mcusysoff_reflect:
+ mtk_cpc_mcusys_off_reflect();
+mt_pwr_mcusysoff_break:
plat_mt_lp_cpu_rc = -1;
return -1;
@@ -119,5 +143,7 @@
INFO("MCDI init done.\n");
}
+ mt_lp_irqremain_init();
+
return &plat_pm;
}
diff --git a/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.c b/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.c
new file mode 100644
index 0000000..e74d3e7
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.c
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mt_lp_rm.h>
+#include <mt_lp_irqremain.h>
+#include <mtk_cirq.h>
+#include <plat_mtk_lpm.h>
+
+#define EDMA0_IRQ_ID U(448)
+#define MDLA_IRQ_ID U(446)
+#define MALI4_IRQ_ID U(399)
+#define MALI3_IRQ_ID U(398)
+#define MALI2_IRQ_ID U(397)
+#define MALI1_IRQ_ID U(396)
+#define MALI0_IRQ_ID U(395)
+#define VPU_CORE1_IRQ_ID U(453)
+#define VPU_CORE0_IRQ_ID U(452)
+#define MD_WDT_IRQ_ID U(110)
+#define KEYPAD_IRQ_ID U(106)
+
+#define MD_WDT_WAKESRC 0x2000000
+#define KEYPAD_WAKESRC 0x4
+
+static struct mt_irqremain remain_irqs;
+
+int mt_lp_irqremain_submit(void)
+{
+ if (remain_irqs.count == 0) {
+ return -1;
+ }
+
+ set_wakeup_sources(remain_irqs.irqs, remain_irqs.count);
+ mt_lp_rm_do_update(-1, PLAT_RC_UPDATE_REMAIN_IRQS, &remain_irqs);
+
+ return 0;
+}
+
+int mt_lp_irqremain_aquire(void)
+{
+ if (remain_irqs.count == 0) {
+ return -1;
+ }
+
+ mt_cirq_sw_reset();
+ mt_cirq_clone_gic();
+ mt_cirq_enable();
+
+ return 0;
+}
+
+int mt_lp_irqremain_release(void)
+{
+ if (remain_irqs.count == 0) {
+ return -1;
+ }
+
+ mt_cirq_flush();
+ mt_cirq_disable();
+
+ return 0;
+}
+
+void mt_lp_irqremain_init(void)
+{
+ uint32_t idx;
+
+ remain_irqs.count = 0;
+
+ /* level edma0 */
+ idx = remain_irqs.count;
+ remain_irqs.irqs[idx] = EDMA0_IRQ_ID;
+ remain_irqs.wakeupsrc_cat[idx] = 0;
+ remain_irqs.wakeupsrc[idx] = 0;
+ remain_irqs.count++;
+
+ /* level mdla */
+ idx = remain_irqs.count;
+ remain_irqs.irqs[idx] = MDLA_IRQ_ID;
+ remain_irqs.wakeupsrc_cat[idx] = 0;
+ remain_irqs.wakeupsrc[idx] = 0;
+ remain_irqs.count++;
+
+ /* level mali4 */
+ idx = remain_irqs.count;
+ remain_irqs.irqs[idx] = MALI4_IRQ_ID;
+ remain_irqs.wakeupsrc_cat[idx] = 0;
+ remain_irqs.wakeupsrc[idx] = 0;
+ remain_irqs.count++;
+
+ /* level mali3 */
+ idx = remain_irqs.count;
+ remain_irqs.irqs[idx] = MALI3_IRQ_ID;
+ remain_irqs.wakeupsrc_cat[idx] = 0;
+ remain_irqs.wakeupsrc[idx] = 0;
+ remain_irqs.count++;
+
+ /* level mali2 */
+ idx = remain_irqs.count;
+ remain_irqs.irqs[idx] = MALI2_IRQ_ID;
+ remain_irqs.wakeupsrc_cat[idx] = 0;
+ remain_irqs.wakeupsrc[idx] = 0;
+ remain_irqs.count++;
+
+ /* level mali1 */
+ idx = remain_irqs.count;
+ remain_irqs.irqs[idx] = MALI1_IRQ_ID;
+ remain_irqs.wakeupsrc_cat[idx] = 0;
+ remain_irqs.wakeupsrc[idx] = 0;
+ remain_irqs.count++;
+
+ /* level mali0 */
+ idx = remain_irqs.count;
+ remain_irqs.irqs[idx] = MALI0_IRQ_ID;
+ remain_irqs.wakeupsrc_cat[idx] = 0;
+ remain_irqs.wakeupsrc[idx] = 0;
+ remain_irqs.count++;
+
+ /* level vpu core1 */
+ idx = remain_irqs.count;
+ remain_irqs.irqs[idx] = VPU_CORE1_IRQ_ID;
+ remain_irqs.wakeupsrc_cat[idx] = 0;
+ remain_irqs.wakeupsrc[idx] = 0;
+ remain_irqs.count++;
+
+ /* level vpu core0 */
+ idx = remain_irqs.count;
+ remain_irqs.irqs[idx] = VPU_CORE0_IRQ_ID;
+ remain_irqs.wakeupsrc_cat[idx] = 0;
+ remain_irqs.wakeupsrc[idx] = 0;
+ remain_irqs.count++;
+
+ /* edge mdwdt */
+ idx = remain_irqs.count;
+ remain_irqs.irqs[idx] = MD_WDT_IRQ_ID;
+ remain_irqs.wakeupsrc_cat[idx] = 0;
+ remain_irqs.wakeupsrc[idx] = MD_WDT_WAKESRC;
+ remain_irqs.count++;
+
+ /* edge keypad */
+ idx = remain_irqs.count;
+ remain_irqs.irqs[idx] = KEYPAD_IRQ_ID;
+ remain_irqs.wakeupsrc_cat[idx] = 0;
+ remain_irqs.wakeupsrc[idx] = KEYPAD_WAKESRC;
+ remain_irqs.count++;
+
+ mt_lp_irqremain_submit();
+}
diff --git a/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.h b/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.h
new file mode 100644
index 0000000..cbed967
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/mcdi/mt_lp_irqremain.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_LP_IRQREMAIN_H
+#define MT_LP_IRQREMAIN_H
+
+extern int mt_lp_irqremain_submit(void);
+extern int mt_lp_irqremain_aquire(void);
+extern int mt_lp_irqremain_release(void);
+extern void mt_lp_irqremain_init(void);
+#endif /* MT_LP_IRQREMAIN_H */
diff --git a/plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.c b/plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.c
index df74122..1635b67 100644
--- a/plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.c
+++ b/plat/mediatek/mt8192/drivers/mcdi/mt_mcdi.c
@@ -5,6 +5,7 @@
*/
#include <cdefs.h>
+#include <common/debug.h>
#include <lib/mmio.h>
#include <lib/utils_def.h>
@@ -144,5 +145,7 @@
mcdi_init_status = MCDI_INIT_DONE;
}
+ INFO("mcdi ready for mcusys-off-idle and system suspend\n");
+
return (mcdi_init_status == MCDI_INIT_DONE) ? 0 : mcdi_init_status;
}
diff --git a/plat/mediatek/mt8192/drivers/rtc/rtc.h b/plat/mediatek/mt8192/drivers/rtc/rtc.h
deleted file mode 100644
index 419bfe4..0000000
--- a/plat/mediatek/mt8192/drivers/rtc/rtc.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef RTC_H
-#define RTC_H
-
-/* RTC registers */
-enum {
- RTC_BBPU = 0x0588,
- RTC_IRQ_STA = 0x058A,
- RTC_IRQ_EN = 0x058C,
- RTC_CII_EN = 0x058E
-};
-
-enum {
- RTC_AL_SEC = 0x05A0,
- RTC_AL_MIN = 0x05A2,
- RTC_AL_HOU = 0x05A4,
- RTC_AL_DOM = 0x05A6,
- RTC_AL_DOW = 0x05A8,
- RTC_AL_MTH = 0x05AA,
- RTC_AL_YEA = 0x05AC,
- RTC_AL_MASK = 0x0590
-};
-
-enum {
- RTC_OSC32CON = 0x05AE,
- RTC_CON = 0x05C4,
- RTC_WRTGR = 0x05C2
-};
-
-enum {
- RTC_POWERKEY1 = 0x05B0,
- RTC_POWERKEY2 = 0x05B2
-};
-
-enum {
- RTC_POWERKEY1_KEY = 0xA357,
- RTC_POWERKEY2_KEY = 0x67D2
-};
-
-enum {
- RTC_PDN1 = 0x05B4,
- RTC_PDN2 = 0x05B6,
- RTC_SPAR0 = 0x05B8,
- RTC_SPAR1 = 0x05BA,
- RTC_PROT = 0x05BC,
- RTC_DIFF = 0x05BE,
- RTC_CALI = 0x05C0
-};
-
-enum {
- RTC_OSC32CON_UNLOCK1 = 0x1A57,
- RTC_OSC32CON_UNLOCK2 = 0x2B68
-};
-
-enum {
- RTC_LPD_EN = 0x0406,
- RTC_LPD_RST = 0x040E
-};
-
-enum {
- RTC_LPD_OPT_XOSC_AND_EOSC_LPD = 0U << 13,
- RTC_LPD_OPT_EOSC_LPD = 1U << 13,
- RTC_LPD_OPT_XOSC_LPD = 2U << 13,
- RTC_LPD_OPT_F32K_CK_ALIVE = 3U << 13,
-};
-
-#define RTC_LPD_OPT_MASK (3U << 13)
-
-enum {
- RTC_PROT_UNLOCK1 = 0x586A,
- RTC_PROT_UNLOCK2 = 0x9136
-};
-
-enum {
- RTC_BBPU_PWREN = 1U << 0,
- RTC_BBPU_SPAR_SW = 1U << 1,
- RTC_BBPU_RESET_SPAR = 1U << 2,
- RTC_BBPU_RESET_ALARM = 1U << 3,
- RTC_BBPU_CLRPKY = 1U << 4,
- RTC_BBPU_RELOAD = 1U << 5,
- RTC_BBPU_CBUSY = 1U << 6
-};
-
-enum {
- RTC_AL_MASK_SEC = 1U << 0,
- RTC_AL_MASK_MIN = 1U << 1,
- RTC_AL_MASK_HOU = 1U << 2,
- RTC_AL_MASK_DOM = 1U << 3,
- RTC_AL_MASK_DOW = 1U << 4,
- RTC_AL_MASK_MTH = 1U << 5,
- RTC_AL_MASK_YEA = 1U << 6
-};
-
-enum {
- RTC_BBPU_AUTO_PDN_SEL = 1U << 6,
- RTC_BBPU_2SEC_CK_SEL = 1U << 7,
- RTC_BBPU_2SEC_EN = 1U << 8,
- RTC_BBPU_2SEC_MODE = 0x3 << 9,
- RTC_BBPU_2SEC_STAT_CLEAR = 1U << 11,
- RTC_BBPU_2SEC_STAT_STA = 1U << 12
-};
-
-enum {
- RTC_BBPU_KEY = 0x43 << 8
-};
-
-enum {
- RTC_EMBCK_SRC_SEL = 1 << 8,
- RTC_EMBCK_SEL_MODE = 3 << 6,
- RTC_XOSC32_ENB = 1 << 5,
- RTC_REG_XOSC32_ENB = 1 << 15
-};
-
-enum {
- RTC_K_EOSC_RSV_0 = 1 << 8,
- RTC_K_EOSC_RSV_1 = 1 << 9,
- RTC_K_EOSC_RSV_2 = 1 << 10
-};
-
-enum {
- RTC_RG_EOSC_CALI_TD_1SEC = 3 << 5,
- RTC_RG_EOSC_CALI_TD_2SEC = 4 << 5,
- RTC_RG_EOSC_CALI_TD_4SEC = 5 << 5,
- RTC_RG_EOSC_CALI_TD_8SEC = 6 << 5,
- RTC_RG_EOSC_CALI_TD_16SEC = 7 << 5,
- RTC_RG_EOSC_CALI_TD_MASK = 7 << 5
-};
-
-/* PMIC TOP Register Definition */
-enum {
- PMIC_RG_TOP_CON = 0x0020,
- PMIC_RG_TOP_CKPDN_CON1 = 0x0112,
- PMIC_RG_TOP_CKPDN_CON1_SET = 0x0114,
- PMIC_RG_TOP_CKPDN_CON1_CLR = 0x0116,
- PMIC_RG_TOP_CKSEL_CON0 = 0x0118,
- PMIC_RG_TOP_CKSEL_CON0_SET = 0x011A,
- PMIC_RG_TOP_CKSEL_CON0_CLR = 0x011C
-};
-
-/* PMIC SCK Register Definition */
-enum {
- PMIC_RG_SCK_TOP_CKPDN_CON0 = 0x0514,
- PMIC_RG_SCK_TOP_CKPDN_CON0_SET = 0x0516,
- PMIC_RG_SCK_TOP_CKPDN_CON0_CLR = 0x0518,
- PMIC_RG_EOSC_CALI_CON0 = 0x53A
-};
-
-enum {
- PMIC_EOSC_CALI_START_ADDR = 0x53A
-};
-
-enum {
- PMIC_EOSC_CALI_START_MASK = 0x1,
- PMIC_EOSC_CALI_START_SHIFT = 0
-};
-
-/* PMIC DCXO Register Definition */
-enum {
- PMIC_RG_DCXO_CW00 = 0x0788,
- PMIC_RG_DCXO_CW02 = 0x0790,
- PMIC_RG_DCXO_CW08 = 0x079C,
- PMIC_RG_DCXO_CW09 = 0x079E,
- PMIC_RG_DCXO_CW09_CLR = 0x07A2,
- PMIC_RG_DCXO_CW10 = 0x07A4,
- PMIC_RG_DCXO_CW12 = 0x07A8,
- PMIC_RG_DCXO_CW13 = 0x07AA,
- PMIC_RG_DCXO_CW15 = 0x07AE,
- PMIC_RG_DCXO_CW19 = 0x07B6,
-};
-
-enum {
- PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK = 0x1,
- PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT = 1,
- PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK = 0x1,
- PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT = 3,
- PMIC_RG_RTC_EOSC32_CK_PDN_MASK = 0x1,
- PMIC_RG_RTC_EOSC32_CK_PDN_SHIFT = 2,
- PMIC_RG_EOSC_CALI_TD_MASK = 0x7,
- PMIC_RG_EOSC_CALI_TD_SHIFT = 5,
- PMIC_RG_XO_EN32K_MAN_MASK = 0x1,
- PMIC_RG_XO_EN32K_MAN_SHIFT = 0
-};
-
-/* external API */
-uint16_t RTC_Read(uint32_t addr);
-void RTC_Write(uint32_t addr, uint16_t data);
-int32_t rtc_busy_wait(void);
-int32_t RTC_Write_Trigger(void);
-int32_t Writeif_unlock(void);
-void rtc_power_off_sequence(void);
-
-#endif /* RTC_H */
diff --git a/plat/mediatek/mt8192/drivers/spm/build.mk b/plat/mediatek/mt8192/drivers/spm/build.mk
new file mode 100644
index 0000000..4153603
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/build.mk
@@ -0,0 +1,68 @@
+#
+# Copyright (c) 2020, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Enable or disable spm feature
+MT_SPM_FEATURE_SUPPORT = yes
+
+# Enable or disable cirq restore
+MT_SPM_CIRQ_FEATURE_SUPPORT = yes
+
+# sspm notifier support
+MT_SPM_SSPM_NOTIFIER_SUPPORT = yes
+
+CUR_SPM_FOLDER = ${MTK_PLAT_SOC}/drivers/spm
+
+# spm common files
+PLAT_SPM_SOURCE_FILES_COMMON += \
+ ${CUR_SPM_FOLDER}/mt_spm.c \
+ ${CUR_SPM_FOLDER}/mt_spm_conservation.c \
+ ${CUR_SPM_FOLDER}/mt_spm_internal.c \
+ ${CUR_SPM_FOLDER}/mt_spm_pmic_wrap.c \
+ ${CUR_SPM_FOLDER}/mt_spm_vcorefs.c
+
+# spm platform dependcy files
+PLAT_SPM_SOURCE_FILES += \
+ ${CUR_SPM_FOLDER}/constraints/mt_spm_rc_bus26m.c \
+ ${CUR_SPM_FOLDER}/constraints/mt_spm_rc_cpu_buck_ldo.c \
+ ${CUR_SPM_FOLDER}/constraints/mt_spm_rc_dram.c \
+ ${CUR_SPM_FOLDER}/constraints/mt_spm_rc_syspll.c \
+ ${CUR_SPM_FOLDER}/mt_spm_cond.c \
+ ${CUR_SPM_FOLDER}/mt_spm_suspend.c \
+ ${CUR_SPM_FOLDER}/mt_spm_idle.c
+
+ifeq (${MT_SPM_FEATURE_SUPPORT}, no)
+PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_SPM_UNSUPPORT
+BL31_MT_LPM_PLAT_SPM_SOURCE_FILES += ${PLAT_SPM_SOURCE_FILES_COMMON}
+else
+BL31_MT_LPM_PLAT_SPM_SOURCE_FILES += \
+ ${PLAT_SPM_SOURCE_FILES_COMMON} \
+ ${PLAT_SPM_SOURCE_FILES}
+endif
+
+ifeq (${MT_SPM_CIRQ_FEATURE_SUPPORT}, no)
+PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_CIRQ_UNSUPPORT
+endif
+
+ifeq (${MT_SPM_SSPM_NOTIFIER_SUPPORT}, no)
+PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+else
+BL31_MT_LPM_PLAT_SPM_SOURCE_FILES += \
+ ${CUR_SPM_FOLDER}/notifier/mt_spm_sspm_notifier.c
+endif
+
+$(info --------------------------------------)
+$(info SPM build flags: ${PLAT_SPM_DEBUG_CFLAGS})
+$(info SPM build files: ${BL31_MT_LPM_PLAT_SPM_SOURCE_FILES})
+$(info --------------------------------------)
+
+# Common makefile for platform.mk
+PLAT_INCLUDES += \
+ ${PLAT_SPM_DEBUG_CFLAGS} \
+ -I${CUR_SPM_FOLDER}/ \
+ -I${CUR_SPM_FOLDER}/constraints/ \
+ -I${CUR_SPM_FOLDER}/notifier/
+
+PLAT_BL_COMMON_SOURCES += ${BL31_MT_LPM_PLAT_SPM_SOURCE_FILES}
diff --git a/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c
new file mode 100644
index 0000000..f66b8ec
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_bus26m.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+
+#include <mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+#include <plat_pm.h>
+#include <plat_mtk_lpm.h>
+
+#ifndef ATF_PLAT_CIRQ_UNSUPPORT
+#include <mt_gic_v3.h>
+#include <mtk_cirq.h>
+#endif
+
+#define CONSTRAINT_BUS26M_ALLOW \
+ (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
+ MT_RM_CONSTRAINT_ALLOW_VCORE_LP | \
+ MT_RM_CONSTRAINT_ALLOW_LVTS_STATE | \
+ MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF)
+
+#define CONSTRAINT_BUS26M_PCM_FLAG \
+ (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_SRAM_SLEEP_CTRL | \
+ SPM_FLAG_ENABLE_TIA_WORKAROUND | \
+ SPM_FLAG_ENABLE_LVTS_WORKAROUND | \
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
+
+#define CONSTRAINT_BUS26M_PCM_FLAG1 \
+ (SPM_FLAG1_DISABLE_MD26M_CK_OFF)
+
+#define CONSTRAINT_BUS26M_RESOURCE_REQ 0U
+
+static unsigned int bus26m_ext_opand;
+static struct mt_irqremain *refer2remain_irq;
+static struct mt_spm_cond_tables cond_bus26m = {
+ .name = "bus26m",
+ .table_cg = {
+ 0x07CBF1FC, /* MTCMOS1 */
+ 0x0A0D8856, /* INFRA0 */
+ 0x03AF9A00, /* INFRA1 */
+ 0x86000650, /* INFRA2 */
+ 0xC800C000, /* INFRA3 */
+ 0x00000000, /* INFRA4 */
+ 0x4000007C, /* INFRA5 */
+ 0x280E0800, /* MMSYS0 */
+ 0x00000001, /* MMSYS1 */
+ 0x00000000, /* MMSYS2 */
+ },
+ .table_pll = (PLL_BIT_UNIVPLL | PLL_BIT_MFGPLL |
+ PLL_BIT_MSDCPLL | PLL_BIT_TVDPLL |
+ PLL_BIT_MMPLL),
+};
+
+static struct mt_spm_cond_tables cond_bus26m_res = {
+ .table_cg = { 0U },
+ .table_pll = 0U,
+};
+
+static struct constraint_status status = {
+ .id = MT_RM_CONSTRAINT_ID_BUS26M,
+ .valid = (MT_SPM_RC_VALID_SW |
+ MT_SPM_RC_VALID_COND_LATCH),
+ .cond_block = 0U,
+ .enter_cnt = 0U,
+ .cond_res = &cond_bus26m_res,
+};
+
+/*
+ * Cirq will take the place of gic when gic is off.
+ * However, cirq cannot work if 26m clk is turned off when system idle/suspend.
+ * Therefore, we need to set irq pending for specific wakeup source.
+ */
+#ifdef ATF_PLAT_CIRQ_UNSUPPORT
+#define do_irqs_delivery()
+#else
+static void mt_spm_irq_remain_dump(struct mt_irqremain *irqs,
+ unsigned int irq_index,
+ struct wake_status *wakeup)
+{
+ INFO("[SPM] r12 = 0x%08x(0x%08x), flag = 0x%08x 0x%08x 0x%08x\n",
+ wakeup->tr.comm.r12, wakeup->md32pcm_wakeup_sta,
+ wakeup->tr.comm.debug_flag, wakeup->tr.comm.b_sw_flag0,
+ wakeup->tr.comm.b_sw_flag1);
+
+ INFO("irq:%u(0x%08x) set pending\n",
+ irqs->wakeupsrc[irq_index], irqs->irqs[irq_index]);
+}
+
+static void do_irqs_delivery(void)
+{
+ unsigned int idx;
+ int res = 0;
+ struct wake_status *wakeup = NULL;
+ struct mt_irqremain *irqs = refer2remain_irq;
+
+ res = spm_conservation_get_result(&wakeup);
+
+ if ((res != 0) && (irqs == NULL)) {
+ return;
+ }
+
+ for (idx = 0U; idx < irqs->count; ++idx) {
+ if (((wakeup->tr.comm.r12 & irqs->wakeupsrc[idx]) != 0U) ||
+ ((wakeup->raw_sta & irqs->wakeupsrc[idx]) != 0U)) {
+ if ((irqs->wakeupsrc_cat[idx] &
+ MT_IRQ_REMAIN_CAT_LOG) != 0U) {
+ mt_spm_irq_remain_dump(irqs, idx, wakeup);
+ }
+
+ mt_irq_set_pending(irqs->irqs[idx]);
+ }
+ }
+}
+#endif
+
+static void spm_bus26m_conduct(struct spm_lp_scen *spm_lp,
+ unsigned int *resource_req)
+{
+ spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG;
+ spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG1;
+ *resource_req |= CONSTRAINT_BUS26M_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id)
+{
+ (void)cpu;
+ (void)state_id;
+
+ return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
+}
+
+int spm_update_rc_bus26m(int state_id, int type, const void *val)
+{
+ const struct mt_spm_cond_tables *tlb;
+ const struct mt_spm_cond_tables *tlb_check;
+ int res = MT_RM_STATUS_OK;
+
+ if (val == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ if (type == PLAT_RC_UPDATE_CONDITION) {
+ tlb = (const struct mt_spm_cond_tables *)val;
+ tlb_check = (const struct mt_spm_cond_tables *)&cond_bus26m;
+
+ status.cond_block =
+ mt_spm_cond_check(state_id, tlb, tlb_check,
+ ((status.valid &
+ MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
+ &cond_bus26m_res : NULL);
+ } else if (type == PLAT_RC_UPDATE_REMAIN_IRQS) {
+ refer2remain_irq = (struct mt_irqremain *)val;
+ } else {
+ res = MT_RM_STATUS_BAD;
+ }
+
+ return res;
+}
+
+unsigned int spm_allow_rc_bus26m(int state_id)
+{
+ (void)state_id;
+
+ return CONSTRAINT_BUS26M_ALLOW;
+}
+
+int spm_run_rc_bus26m(unsigned int cpu, int state_id)
+{
+ (void)cpu;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, CONSTRAINT_BUS26M_ALLOW |
+ (IS_PLAT_SUSPEND_ID(state_id) ?
+ MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
+#endif
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_enter(state_id,
+ (MT_SPM_EX_OP_SET_WDT |
+ MT_SPM_EX_OP_HW_S1_DETECT |
+ bus26m_ext_opand),
+ CONSTRAINT_BUS26M_RESOURCE_REQ);
+ } else {
+ mt_spm_idle_generic_enter(state_id, MT_SPM_EX_OP_HW_S1_DETECT,
+ spm_bus26m_conduct);
+ }
+
+ return 0;
+}
+
+int spm_reset_rc_bus26m(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+
+ (void)cpu;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
+#endif
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ ext_op |= (bus26m_ext_opand | MT_SPM_EX_OP_SET_WDT);
+ mt_spm_suspend_resume(state_id, ext_op, NULL);
+ bus26m_ext_opand = 0U;
+ } else {
+ mt_spm_idle_generic_resume(state_id, ext_op, NULL);
+ status.enter_cnt++;
+ }
+
+ do_irqs_delivery();
+
+ return 0;
+}
diff --git a/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c
new file mode 100644
index 0000000..9618f3b
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+#include <plat_pm.h>
+
+#define CONSTRAINT_CPU_BUCK_PCM_FLAG \
+ (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_SRAM_SLEEP_CTRL | \
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
+
+#define CONSTRAINT_CPU_BUCK_PCM_FLAG1 0U
+
+#define CONSTRAINT_CPU_BUCK_RESOURCE_REQ \
+ (MT_SPM_DRAM_S1 | \
+ MT_SPM_DRAM_S0 | \
+ MT_SPM_SYSPLL | \
+ MT_SPM_INFRA | \
+ MT_SPM_26M | \
+ MT_SPM_XO_FPM)
+
+
+static unsigned int cpubuckldo_status = MT_SPM_RC_VALID_SW;
+static unsigned int cpubuckldo_enter_cnt;
+
+static void spm_cpu_bcuk_ldo_conduct(struct spm_lp_scen *spm_lp,
+ unsigned int *resource_req)
+{
+ spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG;
+ spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG1;
+ *resource_req |= CONSTRAINT_CPU_BUCK_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+ (void)cpu;
+ (void)state_id;
+
+ return IS_MT_RM_RC_READY(cpubuckldo_status);
+}
+
+unsigned int spm_allow_rc_cpu_buck_ldo(int state_id)
+{
+ (void)state_id;
+
+ return MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF;
+}
+
+int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+ (void)cpu;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER,
+ (IS_PLAT_SUSPEND_ID(state_id) ?
+ MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
+#endif
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_enter(state_id,
+ MT_SPM_EX_OP_SET_WDT,
+ CONSTRAINT_CPU_BUCK_RESOURCE_REQ);
+ } else {
+ mt_spm_idle_generic_enter(state_id, 0U,
+ spm_cpu_bcuk_ldo_conduct);
+ }
+
+ cpubuckldo_enter_cnt++;
+
+ return 0;
+}
+
+int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+ (void)cpu;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
+#endif
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_resume(state_id, MT_SPM_EX_OP_SET_WDT, NULL);
+ } else {
+ mt_spm_idle_generic_resume(state_id, 0U, NULL);
+ }
+
+ return 0;
+}
diff --git a/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_dram.c b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_dram.c
new file mode 100644
index 0000000..34293c4
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_dram.c
@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+
+#include <mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_suspend.h>
+#include <plat_pm.h>
+#include <plat_mtk_lpm.h>
+
+#define CONSTRAINT_DRAM_ALLOW \
+ (MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
+ MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF)
+
+#define CONSTRAINT_DRAM_PCM_FLAG \
+ (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_SRAM_SLEEP_CTRL | \
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
+
+#define CONSTRAINT_DRAM_PCM_FLAG1 0U
+
+#define CONSTRAINT_DRAM_RESOURCE_REQ \
+ (MT_SPM_SYSPLL | \
+ MT_SPM_INFRA | \
+ MT_SPM_26M)
+
+static struct mt_spm_cond_tables cond_dram = {
+ .name = "dram",
+ .table_cg = {
+ 0x078BF1FC, /* MTCMOS1 */
+ 0x080D8856, /* INFRA0 */
+ 0x03AF9A00, /* INFRA1 */
+ 0x86000640, /* INFRA2 */
+ 0xC800C000, /* INFRA3 */
+ 0x00000000, /* INFRA4 */
+ 0x00000000, /* INFRA5 */
+ 0x200C0000, /* MMSYS0 */
+ 0x00000000, /* MMSYS1 */
+ 0x00000000, /* MMSYS2 */
+ },
+ .table_pll = 0U,
+};
+
+static struct mt_spm_cond_tables cond_dram_res = {
+ .table_cg = { 0U },
+ .table_pll = 0U,
+};
+
+static struct constraint_status status = {
+ .id = MT_RM_CONSTRAINT_ID_DRAM,
+ .valid = (MT_SPM_RC_VALID_SW |
+ MT_SPM_RC_VALID_COND_LATCH |
+ MT_SPM_RC_VALID_XSOC_BBLPM),
+ .cond_block = 0U,
+ .enter_cnt = 0U,
+ .cond_res = &cond_dram_res,
+};
+
+static void spm_dram_conduct(struct spm_lp_scen *spm_lp,
+ unsigned int *resource_req)
+{
+ spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG;
+ spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG1;
+ *resource_req |= CONSTRAINT_DRAM_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_dram(unsigned int cpu, int state_id)
+{
+ (void)cpu;
+ (void)state_id;
+
+ return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
+}
+
+int spm_update_rc_dram(int state_id, int type, const void *val)
+{
+ const struct mt_spm_cond_tables *tlb;
+ const struct mt_spm_cond_tables *tlb_check;
+ int res = MT_RM_STATUS_OK;
+
+ if (val == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ if (type == PLAT_RC_UPDATE_CONDITION) {
+ tlb = (const struct mt_spm_cond_tables *)val;
+ tlb_check = (const struct mt_spm_cond_tables *)&cond_dram;
+ status.cond_block =
+ mt_spm_cond_check(state_id, tlb, tlb_check,
+ ((status.valid &
+ MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
+ &cond_dram_res : NULL);
+ } else {
+ res = MT_RM_STATUS_BAD;
+ }
+
+ return res;
+}
+
+unsigned int spm_allow_rc_dram(int state_id)
+{
+ (void)state_id;
+
+ return CONSTRAINT_DRAM_ALLOW;
+}
+
+int spm_run_rc_dram(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+ unsigned int allows = CONSTRAINT_DRAM_ALLOW;
+
+ (void)cpu;
+
+ if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+ ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+ allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+ }
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows |
+ (IS_PLAT_SUSPEND_ID(state_id) ?
+ MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
+#else
+ (void)allows;
+#endif
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_enter(state_id,
+ (MT_SPM_EX_OP_SET_WDT |
+ MT_SPM_EX_OP_HW_S1_DETECT),
+ CONSTRAINT_DRAM_RESOURCE_REQ);
+ } else {
+ mt_spm_idle_generic_enter(state_id, ext_op, spm_dram_conduct);
+ }
+
+ return 0;
+}
+
+int spm_reset_rc_dram(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+ unsigned int allows = CONSTRAINT_DRAM_ALLOW;
+
+ (void)cpu;
+
+ if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+ ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+ allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+ }
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
+#else
+ (void)allows;
+#endif
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_resume(state_id,
+ (MT_SPM_EX_OP_SET_WDT |
+ MT_SPM_EX_OP_HW_S1_DETECT),
+ NULL);
+ } else {
+ mt_spm_idle_generic_resume(state_id, ext_op, NULL);
+ status.enter_cnt++;
+ }
+
+ return 0;
+}
diff --git a/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_internal.h b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_internal.h
new file mode 100644
index 0000000..aeb778a
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_internal.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RC_INTERNAL_H
+#define MT_SPM_RC_INTERNAL_H
+
+#include <stdbool.h>
+
+#define SPM_FLAG_SRAM_SLEEP_CTRL \
+ (SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
+ SPM_FLAG_DISABLE_SYSRAM_SLEEP | \
+ SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP | \
+ SPM_FLAG_DISABLE_SRAM_EVENT)
+
+/* cpu buck/ldo constraint function */
+bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+unsigned int spm_allow_rc_cpu_buck_ldo(int state_id);
+int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+
+/* spm resource dram constraint function */
+bool spm_is_valid_rc_dram(unsigned int cpu, int state_id);
+int spm_update_rc_dram(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_dram(int state_id);
+int spm_run_rc_dram(unsigned int cpu, int state_id);
+int spm_reset_rc_dram(unsigned int cpu, int state_id);
+
+/* spm resource syspll constraint function */
+bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id);
+int spm_update_rc_syspll(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_syspll(int state_id);
+int spm_run_rc_syspll(unsigned int cpu, int state_id);
+int spm_reset_rc_syspll(unsigned int cpu, int state_id);
+
+/* spm resource bus26m constraint function */
+bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id);
+int spm_update_rc_bus26m(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_bus26m(int state_id);
+int spm_run_rc_bus26m(unsigned int cpu, int state_id);
+int spm_reset_rc_bus26m(unsigned int cpu, int state_id);
+#endif /* MT_SPM_RC_INTERNAL_H */
diff --git a/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_syspll.c b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_syspll.c
new file mode 100644
index 0000000..8d76d63
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/constraints/mt_spm_rc_syspll.c
@@ -0,0 +1,192 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+
+#include <mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_suspend.h>
+#include <plat_pm.h>
+#include <plat_mtk_lpm.h>
+
+#define CONSTRAINT_SYSPLL_ALLOW \
+ (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
+ MT_RM_CONSTRAINT_ALLOW_VCORE_LP)
+
+#define CONSTRAINT_SYSPLL_PCM_FLAG \
+ (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_SRAM_SLEEP_CTRL | \
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
+ SPM_FLAG_ENABLE_6315_CTRL | \
+ SPM_FLAG_USE_SRCCLKENO2)
+
+#define CONSTRAINT_SYSPLL_PCM_FLAG1 0U
+#define CONSTRAINT_SYSPLL_RESOURCE_REQ \
+ (MT_SPM_26M)
+
+static struct mt_spm_cond_tables cond_syspll = {
+ .name = "syspll",
+ .table_cg = {
+ 0x078BF1FC, /* MTCMOS1 */
+ 0x080D8856, /* INFRA0 */
+ 0x03AF9A00, /* INFRA1 */
+ 0x86000640, /* INFRA2 */
+ 0xC800C000, /* INFRA3 */
+ 0x00000000, /* INFRA4 */
+ 0x0000007C, /* INFRA5 */
+ 0x280E0800, /* MMSYS0 */
+ 0x00000001, /* MMSYS1 */
+ 0x00000000, /* MMSYS2 */
+ },
+ .table_pll = 0U,
+};
+
+static struct mt_spm_cond_tables cond_syspll_res = {
+ .table_cg = { 0U },
+ .table_pll = 0U,
+};
+
+static struct constraint_status status = {
+ .id = MT_RM_CONSTRAINT_ID_SYSPLL,
+ .valid = (MT_SPM_RC_VALID_SW |
+ MT_SPM_RC_VALID_COND_LATCH |
+ MT_SPM_RC_VALID_XSOC_BBLPM),
+ .cond_block = 0U,
+ .enter_cnt = 0U,
+ .cond_res = &cond_syspll_res,
+};
+
+static void spm_syspll_conduct(struct spm_lp_scen *spm_lp,
+ unsigned int *resource_req)
+{
+ spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG;
+ spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG1;
+ *resource_req |= CONSTRAINT_SYSPLL_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id)
+{
+ (void)cpu;
+ (void)state_id;
+
+ return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
+}
+
+int spm_update_rc_syspll(int state_id, int type, const void *val)
+{
+ const struct mt_spm_cond_tables *tlb;
+ const struct mt_spm_cond_tables *tlb_check;
+ int res = MT_RM_STATUS_OK;
+
+ if (val == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ if (type == PLAT_RC_UPDATE_CONDITION) {
+ tlb = (const struct mt_spm_cond_tables *)val;
+ tlb_check = (const struct mt_spm_cond_tables *)&cond_syspll;
+
+ status.cond_block =
+ mt_spm_cond_check(state_id, tlb, tlb_check,
+ ((status.valid &
+ MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
+ &cond_syspll_res : NULL);
+ } else {
+ res = MT_RM_STATUS_BAD;
+ }
+
+ return res;
+}
+
+unsigned int spm_allow_rc_syspll(int state_id)
+{
+ (void)state_id;
+
+ return CONSTRAINT_SYSPLL_ALLOW;
+}
+
+int spm_run_rc_syspll(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+ unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
+
+ (void)cpu;
+
+ if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+ ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+ allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+ }
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows |
+ (IS_PLAT_SUSPEND_ID(state_id) ?
+ MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
+#else
+ (void)allows;
+#endif
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_enter(state_id,
+ (MT_SPM_EX_OP_SET_WDT |
+ MT_SPM_EX_OP_HW_S1_DETECT |
+ MT_SPM_EX_OP_SET_SUSPEND_MODE),
+ CONSTRAINT_SYSPLL_RESOURCE_REQ);
+ } else {
+ mt_spm_idle_generic_enter(state_id, ext_op, spm_syspll_conduct);
+ }
+
+ return 0;
+}
+
+int spm_reset_rc_syspll(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+ unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
+
+ (void)cpu;
+
+ if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+ ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+ allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+ }
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
+#else
+ (void)allows;
+#endif
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_resume(state_id,
+ (MT_SPM_EX_OP_SET_SUSPEND_MODE |
+ MT_SPM_EX_OP_SET_WDT |
+ MT_SPM_EX_OP_HW_S1_DETECT),
+ NULL);
+ } else {
+ mt_spm_idle_generic_resume(state_id, ext_op, NULL);
+ status.enter_cnt++;
+ }
+
+ return 0;
+}
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm.c b/plat/mediatek/mt8192/drivers/spm/mt_spm.c
new file mode 100644
index 0000000..f4505b6
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+#include <string.h>
+#include <common/debug.h>
+#include <lib/bakery_lock.h>
+#include <lib/mmio.h>
+#include <mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_pmic_wrap.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_suspend.h>
+#include <mtk_plat_common.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+#include <platform_def.h>
+#include <sleep_def.h>
+
+#ifdef MT_SPM_USING_BAKERY_LOCK
+DEFINE_BAKERY_LOCK(spm_lock);
+#define plat_spm_lock_init() bakery_lock_init(&spm_lock)
+#else
+spinlock_t spm_lock;
+#define plat_spm_lock_init()
+#endif
+
+/* CLK_SCP_CFG_0 */
+#define CLK_SCP_CFG_0 (TOPCKGEN_BASE + 0x200)
+#define SPM_CK_CONTROL_EN 0x3FF
+
+/* CLK_SCP_CFG_1 */
+#define CLK_SCP_CFG_1 (TOPCKGEN_BASE + 0x210)
+#define CLK_SCP_CFG_1_MASK 0x100C
+#define CLK_SCP_CFG_1_SPM 0x3
+
+struct mt_resource_constraint plat_constraint_bus26m = {
+ .is_valid = spm_is_valid_rc_bus26m,
+ .update = spm_update_rc_bus26m,
+ .allow = spm_allow_rc_bus26m,
+ .run = spm_run_rc_bus26m,
+ .reset = spm_reset_rc_bus26m,
+};
+
+struct mt_resource_constraint plat_constraint_syspll = {
+ .is_valid = spm_is_valid_rc_syspll,
+ .update = spm_update_rc_syspll,
+ .allow = spm_allow_rc_syspll,
+ .run = spm_run_rc_syspll,
+ .reset = spm_reset_rc_syspll,
+};
+
+struct mt_resource_constraint plat_constraint_dram = {
+ .is_valid = spm_is_valid_rc_dram,
+ .update = spm_update_rc_dram,
+ .allow = spm_allow_rc_dram,
+ .run = spm_run_rc_dram,
+ .reset = spm_reset_rc_dram,
+};
+
+struct mt_resource_constraint plat_constraint_cpu = {
+ .is_valid = spm_is_valid_rc_cpu_buck_ldo,
+ .update = NULL,
+ .allow = spm_allow_rc_cpu_buck_ldo,
+ .run = spm_run_rc_cpu_buck_ldo,
+ .reset = spm_reset_rc_cpu_buck_ldo,
+};
+
+struct mt_resource_constraint *plat_constraints[] = {
+ &plat_constraint_bus26m,
+ &plat_constraint_syspll,
+ &plat_constraint_dram,
+ &plat_constraint_cpu,
+ NULL,
+};
+
+struct mt_resource_manager plat_mt8192_rm = {
+ .update = mt_spm_cond_update,
+ .consts = plat_constraints,
+};
+
+void spm_boot_init(void)
+{
+ /* switch ck_off/axi_26m control to SPM */
+ mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_CONTROL_EN);
+ mmio_clrsetbits_32(CLK_SCP_CFG_1, CLK_SCP_CFG_1_MASK,
+ CLK_SCP_CFG_1_SPM);
+
+ plat_spm_lock_init();
+ mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
+ mt_lp_rm_register(&plat_mt8192_rm);
+ mt_spm_idle_generic_init();
+ mt_spm_suspend_init();
+}
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm.h b/plat/mediatek/mt8192/drivers/spm/mt_spm.h
new file mode 100644
index 0000000..b147fe2
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_H
+#define MT_SPM_H
+
+#include <lib/bakery_lock.h>
+#include <lib/spinlock.h>
+
+#include <plat_mtk_lpm.h>
+
+/*
+ * ARM v8.2, the cache will turn off automatically when cpu
+ * power down. So, there is no doubt to use the spin_lock here
+ */
+#if !HW_ASSISTED_COHERENCY
+#define MT_SPM_USING_BAKERY_LOCK
+#endif
+
+#ifdef MT_SPM_USING_BAKERY_LOCK
+DECLARE_BAKERY_LOCK(spm_lock);
+#define plat_spm_lock() bakery_lock_get(&spm_lock)
+#define plat_spm_unlock() bakery_lock_release(&spm_lock)
+#else
+extern spinlock_t spm_lock;
+#define plat_spm_lock() spin_lock(&spm_lock)
+#define plat_spm_unlock() spin_unlock(&spm_lock)
+#endif
+
+#define MT_SPM_USING_SRCLKEN_RC
+
+/* spm extern operand definition */
+#define MT_SPM_EX_OP_CLR_26M_RECORD (1U << 0)
+#define MT_SPM_EX_OP_SET_WDT (1U << 1)
+#define MT_SPM_EX_OP_NON_GENERIC_RESOURCE_REQ (1U << 2)
+#define MT_SPM_EX_OP_SET_SUSPEND_MODE (1U << 3)
+#define MT_SPM_EX_OP_SET_IS_ADSP (1U << 4)
+#define MT_SPM_EX_OP_SRCLKEN_RC_BBLPM (1U << 5)
+#define MT_SPM_EX_OP_HW_S1_DETECT (1U << 6)
+
+typedef enum {
+ WR_NONE = 0,
+ WR_UART_BUSY = 1,
+ WR_ABORT = 2,
+ WR_PCM_TIMER = 3,
+ WR_WAKE_SRC = 4,
+ WR_DVFSRC = 5,
+ WR_TWAM = 6,
+ WR_PMSR = 7,
+ WR_SPM_ACK_CHK = 8,
+ WR_UNKNOWN = 9,
+} wake_reason_t;
+
+static inline void spm_lock_get(void)
+{
+ plat_spm_lock();
+}
+
+static inline void spm_lock_release(void)
+{
+ plat_spm_unlock();
+}
+
+extern void spm_boot_init(void);
+#endif /* MT_SPM_H */
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c
new file mode 100644
index 0000000..2d67fdf
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.c
@@ -0,0 +1,219 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+#include <platform_def.h>
+
+#define MT_LP_TZ_INFRA_REG(ofs) (INFRACFG_AO_BASE + ofs)
+#define MT_LP_TZ_MM_REG(ofs) (MMSYS_BASE + ofs)
+#define MT_LP_TZ_SPM_REG(ofs) (SPM_BASE + ofs)
+#define MT_LP_TZ_TOPCK_REG(ofs) (TOPCKGEN_BASE + ofs)
+#define MT_LP_TZ_APMIXEDSYS(ofs) (APMIXEDSYS + ofs)
+
+#define SPM_PWR_STATUS MT_LP_TZ_SPM_REG(0x016C)
+#define SPM_PWR_STATUS_2ND MT_LP_TZ_SPM_REG(0x0170)
+#define INFRA_SW_CG0 MT_LP_TZ_INFRA_REG(0x0094)
+#define INFRA_SW_CG1 MT_LP_TZ_INFRA_REG(0x0090)
+#define INFRA_SW_CG2 MT_LP_TZ_INFRA_REG(0x00AC)
+#define INFRA_SW_CG3 MT_LP_TZ_INFRA_REG(0x00C8)
+#define INFRA_SW_CG4 MT_LP_TZ_INFRA_REG(0x00D8)
+#define INFRA_SW_CG5 MT_LP_TZ_INFRA_REG(0x00E8)
+#define MMSYS_CG_CON0 MT_LP_TZ_MM_REG(0x100)
+#define MMSYS_CG_CON1 MT_LP_TZ_MM_REG(0x110)
+#define MMSYS_CG_CON2 MT_LP_TZ_MM_REG(0x1A0)
+
+/***********************************************************
+ * Check clkmux registers
+ ***********************************************************/
+#define CLK_CFG(id) MT_LP_TZ_TOPCK_REG(0x20 + id * 0x10)
+#define PDN_CHECK BIT(7)
+#define CLK_CHECK BIT(31)
+
+enum {
+ CLKMUX_DISP = 0,
+ CLKMUX_MDP = 1,
+ CLKMUX_IMG1 = 2,
+ CLKMUX_IMG2 = 3,
+ NF_CLKMUX,
+};
+
+static bool is_clkmux_pdn(unsigned int clkmux_id)
+{
+ unsigned int reg, val, idx;
+
+ if ((clkmux_id & CLK_CHECK) != 0U) {
+ clkmux_id = (clkmux_id & ~CLK_CHECK);
+ reg = clkmux_id / 4U;
+ val = mmio_read_32(CLK_CFG(reg));
+ idx = clkmux_id % 4U;
+ val = (val >> (idx * 8U)) & PDN_CHECK;
+ return (val != 0U);
+ }
+
+ return false;
+}
+
+static struct mt_spm_cond_tables spm_cond_t;
+
+struct idle_cond_info {
+ unsigned int subsys_mask;
+ uintptr_t addr;
+ bool bBitflip;
+ unsigned int clkmux_id;
+};
+
+#define IDLE_CG(mask, addr, bitflip, clkmux) \
+ {mask, (uintptr_t)addr, bitflip, clkmux}
+
+static struct idle_cond_info idle_cg_info[PLAT_SPM_COND_MAX] = {
+ IDLE_CG(0xffffffff, SPM_PWR_STATUS, false, 0U),
+ IDLE_CG(0x00000200, INFRA_SW_CG0, true, 0U),
+ IDLE_CG(0x00000200, INFRA_SW_CG1, true, 0U),
+ IDLE_CG(0x00000200, INFRA_SW_CG2, true, 0U),
+ IDLE_CG(0x00000200, INFRA_SW_CG3, true, 0U),
+ IDLE_CG(0x00000200, INFRA_SW_CG4, true, 0U),
+ IDLE_CG(0x00000200, INFRA_SW_CG5, true, 0U),
+ IDLE_CG(0x00100000, MMSYS_CG_CON0, true, (CLK_CHECK | CLKMUX_DISP)),
+ IDLE_CG(0x00100000, MMSYS_CG_CON1, true, (CLK_CHECK | CLKMUX_DISP)),
+ IDLE_CG(0x00100000, MMSYS_CG_CON2, true, (CLK_CHECK | CLKMUX_DISP)),
+};
+
+/***********************************************************
+ * Check pll idle condition
+ ***********************************************************/
+#define PLL_MFGPLL MT_LP_TZ_APMIXEDSYS(0x268)
+#define PLL_MMPLL MT_LP_TZ_APMIXEDSYS(0x360)
+#define PLL_UNIVPLL MT_LP_TZ_APMIXEDSYS(0x308)
+#define PLL_MSDCPLL MT_LP_TZ_APMIXEDSYS(0x350)
+#define PLL_TVDPLL MT_LP_TZ_APMIXEDSYS(0x380)
+
+unsigned int mt_spm_cond_check(int state_id,
+ const struct mt_spm_cond_tables *src,
+ const struct mt_spm_cond_tables *dest,
+ struct mt_spm_cond_tables *res)
+{
+ unsigned int blocked = 0U, i;
+ bool is_system_suspend = IS_PLAT_SUSPEND_ID(state_id);
+
+ if ((src == NULL) || (dest == NULL)) {
+ return SPM_COND_CHECK_FAIL;
+ }
+
+ for (i = 0U; i < PLAT_SPM_COND_MAX; i++) {
+ if (res != NULL) {
+ res->table_cg[i] =
+ (src->table_cg[i] & dest->table_cg[i]);
+
+ if (is_system_suspend && (res->table_cg[i] != 0U)) {
+ INFO("suspend: %s block[%u](0x%lx) = 0x%08x\n",
+ dest->name, i, idle_cg_info[i].addr,
+ res->table_cg[i]);
+ }
+
+ if (res->table_cg[i] != 0U) {
+ blocked |= (1U << i);
+ }
+ } else if ((src->table_cg[i] & dest->table_cg[i]) != 0U) {
+ blocked |= (1U << i);
+ break;
+ }
+ }
+
+ if (res != NULL) {
+ res->table_pll = (src->table_pll & dest->table_pll);
+
+ if (res->table_pll != 0U) {
+ blocked |=
+ (res->table_pll << SPM_COND_BLOCKED_PLL_IDX) |
+ SPM_COND_CHECK_BLOCKED_PLL;
+ }
+ } else if ((src->table_pll & dest->table_pll) != 0U) {
+ blocked |= SPM_COND_CHECK_BLOCKED_PLL;
+ }
+
+ if (is_system_suspend && (blocked != 0U)) {
+ INFO("suspend: %s total blocked = 0x%08x\n",
+ dest->name, blocked);
+ }
+
+ return blocked;
+}
+
+#define IS_MT_SPM_PWR_OFF(mask) \
+ (((mmio_read_32(SPM_PWR_STATUS) & mask) == 0U) && \
+ ((mmio_read_32(SPM_PWR_STATUS_2ND) & mask) == 0U))
+
+int mt_spm_cond_update(struct mt_resource_constraint **con,
+ int stateid, void *priv)
+{
+ int res;
+ uint32_t i;
+ struct mt_resource_constraint *const *rc;
+
+ /* read all cg state */
+ for (i = 0U; i < PLAT_SPM_COND_MAX; i++) {
+ spm_cond_t.table_cg[i] = 0U;
+
+ /* check mtcmos, if off set idle_value and clk to 0 disable */
+ if (IS_MT_SPM_PWR_OFF(idle_cg_info[i].subsys_mask)) {
+ continue;
+ }
+
+ /* check clkmux */
+ if (is_clkmux_pdn(idle_cg_info[i].clkmux_id)) {
+ continue;
+ }
+
+ spm_cond_t.table_cg[i] = idle_cg_info[i].bBitflip ?
+ ~mmio_read_32(idle_cg_info[i].addr) :
+ mmio_read_32(idle_cg_info[i].addr);
+ }
+
+ spm_cond_t.table_pll = 0U;
+ if ((mmio_read_32(PLL_MFGPLL) & 0x1) != 0U) {
+ spm_cond_t.table_pll |= PLL_BIT_MFGPLL;
+ }
+
+ if ((mmio_read_32(PLL_MMPLL) & 0x1) != 0U) {
+ spm_cond_t.table_pll |= PLL_BIT_MMPLL;
+ }
+
+ if ((mmio_read_32(PLL_UNIVPLL) & 0x1) != 0U) {
+ spm_cond_t.table_pll |= PLL_BIT_UNIVPLL;
+ }
+
+ if ((mmio_read_32(PLL_MSDCPLL) & 0x1) != 0U) {
+ spm_cond_t.table_pll |= PLL_BIT_MSDCPLL;
+ }
+
+ if ((mmio_read_32(PLL_TVDPLL) & 0x1) != 0U) {
+ spm_cond_t.table_pll |= PLL_BIT_TVDPLL;
+ }
+
+ spm_cond_t.priv = priv;
+ for (rc = con; *rc != NULL; rc++) {
+ if (((*rc)->update) == NULL) {
+ continue;
+ }
+
+ res = (*rc)->update(stateid, PLAT_RC_UPDATE_CONDITION,
+ (void const *)&spm_cond_t);
+ if (res != MT_RM_STATUS_OK) {
+ break;
+ }
+ }
+
+ return 0;
+}
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h
new file mode 100644
index 0000000..91ebdd9
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_cond.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_CONDIT_H
+#define MT_SPM_CONDIT_H
+
+#include <mt_lp_rm.h>
+
+enum PLAT_SPM_COND {
+ PLAT_SPM_COND_MTCMOS1 = 0,
+ PLAT_SPM_COND_CG_INFRA_0,
+ PLAT_SPM_COND_CG_INFRA_1,
+ PLAT_SPM_COND_CG_INFRA_2,
+ PLAT_SPM_COND_CG_INFRA_3,
+ PLAT_SPM_COND_CG_INFRA_4,
+ PLAT_SPM_COND_CG_INFRA_5,
+ PLAT_SPM_COND_CG_MMSYS_0,
+ PLAT_SPM_COND_CG_MMSYS_1,
+ PLAT_SPM_COND_CG_MMSYS_2,
+ PLAT_SPM_COND_MAX,
+};
+
+#define PLL_BIT_UNIVPLL BIT(0)
+#define PLL_BIT_MFGPLL BIT(1)
+#define PLL_BIT_MSDCPLL BIT(2)
+#define PLL_BIT_TVDPLL BIT(3)
+#define PLL_BIT_MMPLL BIT(4)
+
+/* Definition about SPM_COND_CHECK_BLOCKED
+ * bit [00 ~ 15]: cg blocking index
+ * bit [16 ~ 29]: pll blocking index
+ * bit [30] : pll blocking information
+ * bit [31] : idle condition check fail
+ */
+#define SPM_COND_BLOCKED_CG_IDX U(0)
+#define SPM_COND_BLOCKED_PLL_IDX U(16)
+#define SPM_COND_CHECK_BLOCKED_PLL BIT(30)
+#define SPM_COND_CHECK_FAIL BIT(31)
+
+struct mt_spm_cond_tables {
+ char *name;
+ unsigned int table_cg[PLAT_SPM_COND_MAX];
+ unsigned int table_pll;
+ void *priv;
+};
+
+extern unsigned int mt_spm_cond_check(int state_id,
+ const struct mt_spm_cond_tables *src,
+ const struct mt_spm_cond_tables *dest,
+ struct mt_spm_cond_tables *res);
+extern int mt_spm_cond_update(struct mt_resource_constraint **con,
+ int stateid, void *priv);
+#endif /* MT_SPM_CONDIT_H */
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_conservation.c b/plat/mediatek/mt8192/drivers/spm/mt_spm_conservation.c
new file mode 100644
index 0000000..f9e6654
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_conservation.c
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include <mt_spm.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_vcorefs.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+struct wake_status spm_wakesta; /* record last wakesta */
+
+static int go_to_spm_before_wfi(int state_id, unsigned int ext_opand,
+ struct spm_lp_scen *spm_lp,
+ unsigned int resource_req)
+{
+ int ret = 0;
+ struct pwr_ctrl *pwrctrl;
+ uint32_t cpu = plat_my_core_pos();
+
+ pwrctrl = spm_lp->pwrctrl;
+
+ __spm_set_cpu_status(cpu);
+ __spm_set_power_control(pwrctrl);
+ __spm_set_wakeup_event(pwrctrl);
+ __spm_sync_vcore_dvfs_power_control(pwrctrl, __spm_vcorefs.pwrctrl);
+ __spm_set_pcm_flags(pwrctrl);
+ __spm_src_req_update(pwrctrl, resource_req);
+
+ if ((ext_opand & MT_SPM_EX_OP_SET_WDT) != 0U) {
+ __spm_set_pcm_wdt(1);
+ }
+
+ if ((ext_opand & MT_SPM_EX_OP_SRCLKEN_RC_BBLPM) != 0U) {
+ __spm_xo_soc_bblpm(1);
+ }
+
+ if ((ext_opand & MT_SPM_EX_OP_HW_S1_DETECT) != 0U) {
+ spm_hw_s1_state_monitor_resume();
+ }
+
+ /* Disable auto resume by PCM in system suspend stage */
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ __spm_disable_pcm_timer();
+ __spm_set_pcm_wdt(0);
+ }
+
+ __spm_send_cpu_wakeup_event();
+
+ INFO("cpu%d: wakesrc = 0x%x, settle = 0x%x, sec = %u\n",
+ cpu, pwrctrl->wake_src, mmio_read_32(SPM_CLK_SETTLE),
+ mmio_read_32(PCM_TIMER_VAL) / 32768);
+ INFO("sw_flag = 0x%x 0x%x, req = 0x%x, pwr = 0x%x 0x%x\n",
+ pwrctrl->pcm_flags, pwrctrl->pcm_flags1,
+ mmio_read_32(SPM_SRC_REQ), mmio_read_32(PWR_STATUS),
+ mmio_read_32(PWR_STATUS_2ND));
+
+ return ret;
+}
+
+static void go_to_spm_after_wfi(int state_id, unsigned int ext_opand,
+ struct spm_lp_scen *spm_lp,
+ struct wake_status **status)
+{
+ unsigned int ext_status = 0U;
+
+ /* system watchdog will be resumed at kernel stage */
+ if ((ext_opand & MT_SPM_EX_OP_SET_WDT) != 0U) {
+ __spm_set_pcm_wdt(0);
+ }
+
+ if ((ext_opand & MT_SPM_EX_OP_SRCLKEN_RC_BBLPM) != 0U) {
+ __spm_xo_soc_bblpm(0);
+ }
+
+ if ((ext_opand & MT_SPM_EX_OP_HW_S1_DETECT) != 0U) {
+ spm_hw_s1_state_monitor_pause(&ext_status);
+ }
+
+ __spm_ext_int_wakeup_req_clr();
+ __spm_get_wakeup_status(&spm_wakesta, ext_status);
+
+ if (status != NULL) {
+ *status = &spm_wakesta;
+ }
+
+ __spm_clean_after_wakeup();
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ __spm_output_wake_reason(state_id, &spm_wakesta);
+ }
+}
+
+int spm_conservation(int state_id, unsigned int ext_opand,
+ struct spm_lp_scen *spm_lp, unsigned int resource_req)
+{
+ if (spm_lp == NULL) {
+ return -1;
+ }
+
+ spm_lock_get();
+ go_to_spm_before_wfi(state_id, ext_opand, spm_lp, resource_req);
+ spm_lock_release();
+
+ return 0;
+}
+
+void spm_conservation_finish(int state_id, unsigned int ext_opand,
+ struct spm_lp_scen *spm_lp,
+ struct wake_status **status)
+{
+ spm_lock_get();
+ go_to_spm_after_wfi(state_id, ext_opand, spm_lp, status);
+ spm_lock_release();
+}
+
+int spm_conservation_get_result(struct wake_status **res)
+{
+ if (res == NULL) {
+ return -1;
+ }
+
+ *res = &spm_wakesta;
+
+ return 0;
+}
+
+#define GPIO_BANK (GPIO_BASE + 0x6F0)
+#define TRAP_UFS_FIRST BIT(11) /* bit 11, 0: UFS, 1: eMMC */
+
+void spm_conservation_pwrctrl_init(struct pwr_ctrl *pwrctrl)
+{
+ if (pwrctrl == NULL) {
+ return;
+ }
+
+ /* For ufs, emmc storage type */
+ if ((mmio_read_32(GPIO_BANK) & TRAP_UFS_FIRST) != 0U) {
+ /* If eMMC is used, mask UFS req */
+ pwrctrl->reg_ufs_srcclkena_mask_b = 0;
+ pwrctrl->reg_ufs_infra_req_mask_b = 0;
+ pwrctrl->reg_ufs_apsrc_req_mask_b = 0;
+ pwrctrl->reg_ufs_vrf18_req_mask_b = 0;
+ pwrctrl->reg_ufs_ddr_en_mask_b = 0;
+ }
+}
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_conservation.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_conservation.h
new file mode 100644
index 0000000..c5e97db
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_conservation.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_CONSERVATION_H
+#define MT_SPM_CONSERVATION_H
+
+#include <mt_spm_internal.h>
+
+extern int spm_conservation(int state_id, unsigned int ext_opand,
+ struct spm_lp_scen *spm_lp,
+ unsigned int resource_req);
+extern void spm_conservation_finish(int state_id, unsigned int ext_opand,
+ struct spm_lp_scen *spm_lp,
+ struct wake_status **status);
+extern int spm_conservation_get_result(struct wake_status **res);
+extern void spm_conservation_pwrctrl_init(struct pwr_ctrl *pwrctrl);
+#endif /* MT_SPM_CONSERVATION_H */
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_constraint.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_constraint.h
new file mode 100644
index 0000000..a3409f7
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_constraint.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_CONSTRAINT_H
+#define MT_SPM_CONSTRAINT_H
+
+#include <mt_lp_rm.h>
+
+#define MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF (1U << 0)
+#define MT_RM_CONSTRAINT_ALLOW_DRAM_S0 (1U << 1)
+#define MT_RM_CONSTRAINT_ALLOW_DRAM_S1 (1U << 2)
+#define MT_RM_CONSTRAINT_ALLOW_VCORE_LP (1U << 3)
+#define MT_RM_CONSTRAINT_ALLOW_INFRA_PDN (1U << 4)
+#define MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF (1U << 5)
+#define MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND (1U << 6)
+#define MT_RM_CONSTRAINT_ALLOW_BBLPM (1U << 7)
+#define MT_RM_CONSTRAINT_ALLOW_XO_UFS (1U << 8)
+#define MT_RM_CONSTRAINT_ALLOW_GPS_STATE (1U << 9)
+#define MT_RM_CONSTRAINT_ALLOW_LVTS_STATE (1U << 10)
+
+#define MT_SPM_RC_INVALID 0x0
+#define MT_SPM_RC_VALID_SW (1U << 0)
+#define MT_SPM_RC_VALID_FW (1U << 1)
+#define MT_SPM_RC_VALID_RESIDNECY (1U << 2)
+#define MT_SPM_RC_VALID_COND_CHECK (1U << 3)
+#define MT_SPM_RC_VALID_COND_LATCH (1U << 4)
+#define MT_SPM_RC_VALID_UFS_H8 (1U << 5)
+#define MT_SPM_RC_VALID_FLIGHTMODE (1U << 6)
+#define MT_SPM_RC_VALID_XSOC_BBLPM (1U << 7)
+#define MT_SPM_RC_VALID_TRACE_EVENT (1U << 8)
+
+#define MT_SPM_RC_VALID (MT_SPM_RC_VALID_SW)
+
+#define IS_MT_RM_RC_READY(status) \
+ ((status & MT_SPM_RC_VALID) == MT_SPM_RC_VALID)
+
+#define MT_SPM_RC_BBLPM_MODE \
+ (MT_SPM_RC_VALID_UFS_H8 | \
+ MT_SPM_RC_VALID_FLIGHTMODE | \
+ MT_SPM_RC_VALID_XSOC_BBLPM)
+
+#define IS_MT_SPM_RC_BBLPM_MODE(st) \
+ ((st & (MT_SPM_RC_BBLPM_MODE)) == MT_SPM_RC_BBLPM_MODE)
+
+struct constraint_status {
+ uint16_t id;
+ uint16_t valid;
+ uint32_t cond_block;
+ uint32_t enter_cnt;
+ struct mt_spm_cond_tables *cond_res;
+};
+
+enum MT_SPM_RM_RC_TYPE {
+ MT_RM_CONSTRAINT_ID_BUS26M,
+ MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_RM_CONSTRAINT_ID_DRAM,
+ MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO,
+ MT_RM_CONSTRAINT_ID_ALL,
+};
+#endif /* MT_SPM_CONSTRAINT_H */
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_idle.c b/plat/mediatek/mt8192/drivers/spm/mt_spm_idle.c
new file mode 100644
index 0000000..3540ec2
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_idle.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include <mt_spm.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <plat_pm.h>
+
+#define __WAKE_SRC_FOR_IDLE_COMMON__ \
+ (R12_PCM_TIMER | \
+ R12_KP_IRQ_B | \
+ R12_APWDT_EVENT_B | \
+ R12_APXGPT1_EVENT_B | \
+ R12_CONN2AP_SPM_WAKEUP_B | \
+ R12_EINT_EVENT_B | \
+ R12_CONN_WDT_IRQ_B | \
+ R12_CCIF0_EVENT_B | \
+ R12_SSPM2SPM_WAKEUP_B | \
+ R12_SCP2SPM_WAKEUP_B | \
+ R12_ADSP2SPM_WAKEUP_B | \
+ R12_USBX_CDSC_B | \
+ R12_USBX_POWERDWN_B | \
+ R12_SYS_TIMER_EVENT_B | \
+ R12_EINT_EVENT_SECURE_B | \
+ R12_CCIF1_EVENT_B | \
+ R12_AFE_IRQ_MCU_B | \
+ R12_SYS_CIRQ_IRQ_B | \
+ R12_MD2AP_PEER_EVENT_B | \
+ R12_MD1_WDT_B | \
+ R12_CLDMA_EVENT_B | \
+ R12_REG_CPU_WAKEUP | \
+ R12_APUSYS_WAKE_HOST_B | \
+ R12_PCIE_BRIDGE_IRQ | \
+ R12_PCIE_IRQ)
+
+#if defined(CFG_MICROTRUST_TEE_SUPPORT)
+#define WAKE_SRC_FOR_IDLE (__WAKE_SRC_FOR_IDLE_COMMON__)
+#else
+#define WAKE_SRC_FOR_IDLE \
+ (__WAKE_SRC_FOR_IDLE_COMMON__ | \
+ R12_SEJ_EVENT_B)
+#endif
+
+static struct pwr_ctrl idle_spm_pwr = {
+ .timer_val = 0x28000,
+ .wake_src = WAKE_SRC_FOR_IDLE,
+
+ /* Auto-gen Start */
+
+ /* SPM_AP_STANDBY_CON */
+ .reg_wfi_op = 0,
+ .reg_wfi_type = 0,
+ .reg_mp0_cputop_idle_mask = 0,
+ .reg_mp1_cputop_idle_mask = 0,
+ .reg_mcusys_idle_mask = 0,
+ .reg_md_apsrc_1_sel = 0,
+ .reg_md_apsrc_0_sel = 0,
+ .reg_conn_apsrc_sel = 0,
+
+ /* SPM_SRC6_MASK */
+ .reg_dpmaif_srcclkena_mask_b = 1,
+ .reg_dpmaif_infra_req_mask_b = 1,
+ .reg_dpmaif_apsrc_req_mask_b = 1,
+ .reg_dpmaif_vrf18_req_mask_b = 1,
+ .reg_dpmaif_ddr_en_mask_b = 1,
+
+ /* SPM_SRC_REQ */
+ .reg_spm_apsrc_req = 1,
+ .reg_spm_f26m_req = 1,
+ .reg_spm_infra_req = 1,
+ .reg_spm_vrf18_req = 1,
+ .reg_spm_ddr_en_req = 1,
+ .reg_spm_dvfs_req = 0,
+ .reg_spm_sw_mailbox_req = 0,
+ .reg_spm_sspm_mailbox_req = 0,
+ .reg_spm_adsp_mailbox_req = 0,
+ .reg_spm_scp_mailbox_req = 0,
+
+ /* SPM_SRC_MASK */
+ .reg_md_srcclkena_0_mask_b = 1,
+ .reg_md_srcclkena2infra_req_0_mask_b = 0,
+ .reg_md_apsrc2infra_req_0_mask_b = 1,
+ .reg_md_apsrc_req_0_mask_b = 1,
+ .reg_md_vrf18_req_0_mask_b = 1,
+ .reg_md_ddr_en_0_mask_b = 1,
+ .reg_md_srcclkena_1_mask_b = 0,
+ .reg_md_srcclkena2infra_req_1_mask_b = 0,
+ .reg_md_apsrc2infra_req_1_mask_b = 0,
+ .reg_md_apsrc_req_1_mask_b = 0,
+ .reg_md_vrf18_req_1_mask_b = 0,
+ .reg_md_ddr_en_1_mask_b = 0,
+ .reg_conn_srcclkena_mask_b = 1,
+ .reg_conn_srcclkenb_mask_b = 0,
+ .reg_conn_infra_req_mask_b = 1,
+ .reg_conn_apsrc_req_mask_b = 1,
+ .reg_conn_vrf18_req_mask_b = 1,
+ .reg_conn_ddr_en_mask_b = 1,
+ .reg_conn_vfe28_mask_b = 0,
+ .reg_srcclkeni0_srcclkena_mask_b = 1,
+ .reg_srcclkeni0_infra_req_mask_b = 1,
+ .reg_srcclkeni1_srcclkena_mask_b = 0,
+ .reg_srcclkeni1_infra_req_mask_b = 0,
+ .reg_srcclkeni2_srcclkena_mask_b = 0,
+ .reg_srcclkeni2_infra_req_mask_b = 0,
+ .reg_infrasys_apsrc_req_mask_b = 0,
+ .reg_infrasys_ddr_en_mask_b = 1,
+ .reg_md32_srcclkena_mask_b = 1,
+ .reg_md32_infra_req_mask_b = 1,
+ .reg_md32_apsrc_req_mask_b = 1,
+ .reg_md32_vrf18_req_mask_b = 1,
+ .reg_md32_ddr_en_mask_b = 1,
+
+ /* SPM_SRC2_MASK */
+ .reg_scp_srcclkena_mask_b = 1,
+ .reg_scp_infra_req_mask_b = 1,
+ .reg_scp_apsrc_req_mask_b = 1,
+ .reg_scp_vrf18_req_mask_b = 1,
+ .reg_scp_ddr_en_mask_b = 1,
+ .reg_audio_dsp_srcclkena_mask_b = 1,
+ .reg_audio_dsp_infra_req_mask_b = 1,
+ .reg_audio_dsp_apsrc_req_mask_b = 1,
+ .reg_audio_dsp_vrf18_req_mask_b = 1,
+ .reg_audio_dsp_ddr_en_mask_b = 1,
+ .reg_ufs_srcclkena_mask_b = 1,
+ .reg_ufs_infra_req_mask_b = 1,
+ .reg_ufs_apsrc_req_mask_b = 1,
+ .reg_ufs_vrf18_req_mask_b = 1,
+ .reg_ufs_ddr_en_mask_b = 1,
+ .reg_disp0_apsrc_req_mask_b = 1,
+ .reg_disp0_ddr_en_mask_b = 1,
+ .reg_disp1_apsrc_req_mask_b = 1,
+ .reg_disp1_ddr_en_mask_b = 1,
+ .reg_gce_infra_req_mask_b = 1,
+ .reg_gce_apsrc_req_mask_b = 1,
+ .reg_gce_vrf18_req_mask_b = 1,
+ .reg_gce_ddr_en_mask_b = 1,
+ .reg_apu_srcclkena_mask_b = 1,
+ .reg_apu_infra_req_mask_b = 1,
+ .reg_apu_apsrc_req_mask_b = 1,
+ .reg_apu_vrf18_req_mask_b = 1,
+ .reg_apu_ddr_en_mask_b = 1,
+ .reg_cg_check_srcclkena_mask_b = 0,
+ .reg_cg_check_apsrc_req_mask_b = 0,
+ .reg_cg_check_vrf18_req_mask_b = 0,
+ .reg_cg_check_ddr_en_mask_b = 0,
+
+ /* SPM_SRC3_MASK */
+ .reg_dvfsrc_event_trigger_mask_b = 1,
+ .reg_sw2spm_int0_mask_b = 0,
+ .reg_sw2spm_int1_mask_b = 0,
+ .reg_sw2spm_int2_mask_b = 0,
+ .reg_sw2spm_int3_mask_b = 0,
+ .reg_sc_adsp2spm_wakeup_mask_b = 0,
+ .reg_sc_sspm2spm_wakeup_mask_b = 0,
+ .reg_sc_scp2spm_wakeup_mask_b = 0,
+ .reg_csyspwrreq_mask = 1,
+ .reg_spm_srcclkena_reserved_mask_b = 0,
+ .reg_spm_infra_req_reserved_mask_b = 0,
+ .reg_spm_apsrc_req_reserved_mask_b = 0,
+ .reg_spm_vrf18_req_reserved_mask_b = 0,
+ .reg_spm_ddr_en_reserved_mask_b = 0,
+ .reg_mcupm_srcclkena_mask_b = 1,
+ .reg_mcupm_infra_req_mask_b = 1,
+ .reg_mcupm_apsrc_req_mask_b = 1,
+ .reg_mcupm_vrf18_req_mask_b = 1,
+ .reg_mcupm_ddr_en_mask_b = 1,
+ .reg_msdc0_srcclkena_mask_b = 1,
+ .reg_msdc0_infra_req_mask_b = 1,
+ .reg_msdc0_apsrc_req_mask_b = 1,
+ .reg_msdc0_vrf18_req_mask_b = 1,
+ .reg_msdc0_ddr_en_mask_b = 1,
+ .reg_msdc1_srcclkena_mask_b = 1,
+ .reg_msdc1_infra_req_mask_b = 1,
+ .reg_msdc1_apsrc_req_mask_b = 1,
+ .reg_msdc1_vrf18_req_mask_b = 1,
+ .reg_msdc1_ddr_en_mask_b = 1,
+
+ /* SPM_SRC4_MASK */
+ .ccif_event_mask_b = 0xFFF,
+ .reg_bak_psri_srcclkena_mask_b = 0,
+ .reg_bak_psri_infra_req_mask_b = 0,
+ .reg_bak_psri_apsrc_req_mask_b = 0,
+ .reg_bak_psri_vrf18_req_mask_b = 0,
+ .reg_bak_psri_ddr_en_mask_b = 0,
+ .reg_dramc0_md32_infra_req_mask_b = 1,
+ .reg_dramc0_md32_vrf18_req_mask_b = 0,
+ .reg_dramc1_md32_infra_req_mask_b = 1,
+ .reg_dramc1_md32_vrf18_req_mask_b = 0,
+ .reg_conn_srcclkenb2pwrap_mask_b = 0,
+ .reg_dramc0_md32_wakeup_mask = 1,
+ .reg_dramc1_md32_wakeup_mask = 1,
+
+ /* SPM_SRC5_MASK */
+ .reg_mcusys_merge_apsrc_req_mask_b = 0x11,
+ .reg_mcusys_merge_ddr_en_mask_b = 0x11,
+ .reg_msdc2_srcclkena_mask_b = 1,
+ .reg_msdc2_infra_req_mask_b = 1,
+ .reg_msdc2_apsrc_req_mask_b = 1,
+ .reg_msdc2_vrf18_req_mask_b = 1,
+ .reg_msdc2_ddr_en_mask_b = 1,
+ .reg_pcie_srcclkena_mask_b = 1,
+ .reg_pcie_infra_req_mask_b = 1,
+ .reg_pcie_apsrc_req_mask_b = 1,
+ .reg_pcie_vrf18_req_mask_b = 1,
+ .reg_pcie_ddr_en_mask_b = 1,
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ .reg_wakeup_event_mask = 0x01282202,
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ .reg_ext_wakeup_event_mask = 0xFFFFFFFF,
+
+ /* Auto-gen End */
+};
+
+struct spm_lp_scen idle_spm_lp = {
+ .pwrctrl = &idle_spm_pwr,
+};
+
+int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand,
+ spm_idle_conduct fn)
+{
+ unsigned int src_req = 0;
+
+ if (fn != NULL) {
+ fn(&idle_spm_lp, &src_req);
+ }
+
+ return spm_conservation(state_id, ext_opand, &idle_spm_lp, src_req);
+}
+void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
+ struct wake_status **status)
+{
+ spm_conservation_finish(state_id, ext_opand, &idle_spm_lp, status);
+}
+
+void mt_spm_idle_generic_init(void)
+{
+ spm_conservation_pwrctrl_init(idle_spm_lp.pwrctrl);
+}
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_idle.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_idle.h
new file mode 100644
index 0000000..3d42cf1
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_idle.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_IDLE_H
+#define MT_SPM_IDLE_H
+
+typedef void (*spm_idle_conduct)(struct spm_lp_scen *spm_lp,
+ unsigned int *resource_req);
+int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand,
+ spm_idle_conduct fn);
+void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
+ struct wake_status **status);
+void mt_spm_idle_generic_init(void);
+#endif /* MT_SPM_IDLE_H */
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_internal.c b/plat/mediatek/mt8192/drivers/spm/mt_spm_internal.c
new file mode 100644
index 0000000..40be027
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_internal.c
@@ -0,0 +1,588 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+
+#include <assert.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include <mt_spm.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_pmic_wrap.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <platform_def.h>
+#include <plat_pm.h>
+
+/**************************************
+ * Define and Declare
+ **************************************/
+#define ROOT_CORE_ADDR_OFFSET 0x20000000
+#define SPM_WAKEUP_EVENT_MASK_CLEAN_MASK 0xefffffff
+#define SPM_INIT_DONE_US 20
+
+static unsigned int mt_spm_bblpm_cnt;
+
+const char *wakeup_src_str[32] = {
+ [0] = "R12_PCM_TIMER",
+ [1] = "R12_RESERVED_DEBUG_B",
+ [2] = "R12_KP_IRQ_B",
+ [3] = "R12_APWDT_EVENT_B",
+ [4] = "R12_APXGPT1_EVENT_B",
+ [5] = "R12_CONN2AP_SPM_WAKEUP_B",
+ [6] = "R12_EINT_EVENT_B",
+ [7] = "R12_CONN_WDT_IRQ_B",
+ [8] = "R12_CCIF0_EVENT_B",
+ [9] = "R12_LOWBATTERY_IRQ_B",
+ [10] = "R12_SC_SSPM2SPM_WAKEUP_B",
+ [11] = "R12_SC_SCP2SPM_WAKEUP_B",
+ [12] = "R12_SC_ADSP2SPM_WAKEUP_B",
+ [13] = "R12_PCM_WDT_WAKEUP_B",
+ [14] = "R12_USB_CDSC_B",
+ [15] = "R12_USB_POWERDWN_B",
+ [16] = "R12_SYS_TIMER_EVENT_B",
+ [17] = "R12_EINT_EVENT_SECURE_B",
+ [18] = "R12_CCIF1_EVENT_B",
+ [19] = "R12_UART0_IRQ_B",
+ [20] = "R12_AFE_IRQ_MCU_B",
+ [21] = "R12_THERM_CTRL_EVENT_B",
+ [22] = "R12_SYS_CIRQ_IRQ_B",
+ [23] = "R12_MD2AP_PEER_EVENT_B",
+ [24] = "R12_CSYSPWREQ_B",
+ [25] = "R12_MD1_WDT_B",
+ [26] = "R12_AP2AP_PEER_WAKEUPEVENT_B",
+ [27] = "R12_SEJ_EVENT_B",
+ [28] = "R12_SPM_CPU_WAKEUPEVENT_B",
+ [29] = "R12_APUSYS",
+ [30] = "R12_PCIE_BRIDGE_IRQ",
+ [31] = "R12_PCIE_IRQ",
+};
+
+/**************************************
+ * Function and API
+ **************************************/
+
+wake_reason_t __spm_output_wake_reason(int state_id,
+ const struct wake_status *wakesta)
+{
+ uint32_t i, bk_vtcxo_dur, spm_26m_off_pct = 0U;
+ wake_reason_t wr = WR_UNKNOWN;
+
+ if (wakesta == NULL) {
+ return WR_UNKNOWN;
+ }
+
+ if (wakesta->abort != 0U) {
+ ERROR("spmfw flow is aborted: 0x%x, timer_out = %u\n",
+ wakesta->abort, wakesta->timer_out);
+ } else {
+ for (i = 0U; i < 32U; i++) {
+ if ((wakesta->r12 & (1U << i)) != 0U) {
+ INFO("wake up by %s, timer_out = %u\n",
+ wakeup_src_str[i], wakesta->timer_out);
+ wr = WR_WAKE_SRC;
+ break;
+ }
+ }
+ }
+
+ INFO("r12 = 0x%x, r12_ext = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n",
+ wakesta->r12, wakesta->r12_ext, wakesta->r13, wakesta->debug_flag,
+ wakesta->debug_flag1);
+ INFO("raw_sta = 0x%x 0x%x 0x%x, idle_sta = 0x%x, cg_check_sta = 0x%x\n",
+ wakesta->raw_sta, wakesta->md32pcm_wakeup_sta,
+ wakesta->md32pcm_event_sta, wakesta->idle_sta,
+ wakesta->cg_check_sta);
+ INFO("req_sta = 0x%x 0x%x 0x%x 0x%x 0x%x, isr = 0x%x\n",
+ wakesta->req_sta0, wakesta->req_sta1, wakesta->req_sta2,
+ wakesta->req_sta3, wakesta->req_sta4, wakesta->isr);
+ INFO("rt_req_sta0 = 0x%x, rt_req_sta1 = 0x%x, rt_req_sta2 = 0x%x\n",
+ wakesta->rt_req_sta0, wakesta->rt_req_sta1, wakesta->rt_req_sta2);
+ INFO("rt_req_sta3 = 0x%x, dram_sw_con_3 = 0x%x, raw_ext_sta = 0x%x\n",
+ wakesta->rt_req_sta3, wakesta->rt_req_sta4, wakesta->raw_ext_sta);
+ INFO("wake_misc = 0x%x, pcm_flag = 0x%x 0x%x 0x%x 0x%x, req = 0x%x\n",
+ wakesta->wake_misc, wakesta->sw_flag0, wakesta->sw_flag1,
+ wakesta->b_sw_flag0, wakesta->b_sw_flag1, wakesta->src_req);
+ INFO("clk_settle = 0x%x, wlk_cntcv_l = 0x%x, wlk_cntcv_h = 0x%x\n",
+ wakesta->clk_settle, mmio_read_32(SYS_TIMER_VALUE_L),
+ mmio_read_32(SYS_TIMER_VALUE_H));
+
+ if (wakesta->timer_out != 0U) {
+ bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR);
+ spm_26m_off_pct = (100 * bk_vtcxo_dur) / wakesta->timer_out;
+ INFO("spm_26m_off_pct = %u\n", spm_26m_off_pct);
+ }
+
+ return wr;
+}
+
+void __spm_set_cpu_status(unsigned int cpu)
+{
+ uint32_t root_core_addr;
+
+ if (cpu < 8U) {
+ mmio_write_32(ROOT_CPUTOP_ADDR, (1U << cpu));
+ root_core_addr = SPM_CPU0_PWR_CON + (cpu * 0x4);
+ root_core_addr += ROOT_CORE_ADDR_OFFSET;
+ mmio_write_32(ROOT_CORE_ADDR, root_core_addr);
+ /* Notify MCUPM that preferred cpu wakeup */
+ mmio_write_32(MCUPM_MBOX_WAKEUP_CPU, cpu);
+ } else {
+ ERROR("%s: error cpu number %d\n", __func__, cpu);
+ }
+}
+
+void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
+ unsigned int resource_usage)
+{
+ uint8_t apsrc_req = ((resource_usage & MT_SPM_DRAM_S0) != 0U) ?
+ 1 : pwrctrl->reg_spm_apsrc_req;
+ uint8_t ddr_en_req = ((resource_usage & MT_SPM_DRAM_S1) != 0U) ?
+ 1 : pwrctrl->reg_spm_ddr_en_req;
+ uint8_t vrf18_req = ((resource_usage & MT_SPM_SYSPLL) != 0U) ?
+ 1 : pwrctrl->reg_spm_vrf18_req;
+ uint8_t infra_req = ((resource_usage & MT_SPM_INFRA) != 0U) ?
+ 1 : pwrctrl->reg_spm_infra_req;
+ uint8_t f26m_req = ((resource_usage &
+ (MT_SPM_26M | MT_SPM_XO_FPM)) != 0U) ?
+ 1 : pwrctrl->reg_spm_f26m_req;
+
+ mmio_write_32(SPM_SRC_REQ,
+ ((apsrc_req & 0x1) << 0) |
+ ((f26m_req & 0x1) << 1) |
+ ((infra_req & 0x1) << 3) |
+ ((vrf18_req & 0x1) << 4) |
+ ((ddr_en_req & 0x1) << 7) |
+ ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
+ ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
+ ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
+ ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
+ ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
+}
+
+void __spm_set_power_control(const struct pwr_ctrl *pwrctrl)
+{
+ /* Auto-gen Start */
+
+ /* SPM_AP_STANDBY_CON */
+ mmio_write_32(SPM_AP_STANDBY_CON,
+ ((pwrctrl->reg_wfi_op & 0x1) << 0) |
+ ((pwrctrl->reg_wfi_type & 0x1) << 1) |
+ ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
+ ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
+ ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
+ ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
+ ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
+ ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
+
+ /* SPM_SRC6_MASK */
+ mmio_write_32(SPM_SRC6_MASK,
+ ((pwrctrl->reg_dpmaif_srcclkena_mask_b & 0x1) << 0) |
+ ((pwrctrl->reg_dpmaif_infra_req_mask_b & 0x1) << 1) |
+ ((pwrctrl->reg_dpmaif_apsrc_req_mask_b & 0x1) << 2) |
+ ((pwrctrl->reg_dpmaif_vrf18_req_mask_b & 0x1) << 3) |
+ ((pwrctrl->reg_dpmaif_ddr_en_mask_b & 0x1) << 4));
+
+ /* SPM_SRC_REQ */
+ mmio_write_32(SPM_SRC_REQ,
+ ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
+ ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
+ ((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
+ ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
+ ((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) |
+ ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
+ ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
+ ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
+ ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
+ ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
+
+ /* SPM_SRC_MASK */
+ mmio_write_32(SPM_SRC_MASK,
+ ((pwrctrl->reg_md_srcclkena_0_mask_b & 0x1) << 0) |
+ ((pwrctrl->reg_md_srcclkena2infra_req_0_mask_b & 0x1) << 1) |
+ ((pwrctrl->reg_md_apsrc2infra_req_0_mask_b & 0x1) << 2) |
+ ((pwrctrl->reg_md_apsrc_req_0_mask_b & 0x1) << 3) |
+ ((pwrctrl->reg_md_vrf18_req_0_mask_b & 0x1) << 4) |
+ ((pwrctrl->reg_md_ddr_en_0_mask_b & 0x1) << 5) |
+ ((pwrctrl->reg_md_srcclkena_1_mask_b & 0x1) << 6) |
+ ((pwrctrl->reg_md_srcclkena2infra_req_1_mask_b & 0x1) << 7) |
+ ((pwrctrl->reg_md_apsrc2infra_req_1_mask_b & 0x1) << 8) |
+ ((pwrctrl->reg_md_apsrc_req_1_mask_b & 0x1) << 9) |
+ ((pwrctrl->reg_md_vrf18_req_1_mask_b & 0x1) << 10) |
+ ((pwrctrl->reg_md_ddr_en_1_mask_b & 0x1) << 11) |
+ ((pwrctrl->reg_conn_srcclkena_mask_b & 0x1) << 12) |
+ ((pwrctrl->reg_conn_srcclkenb_mask_b & 0x1) << 13) |
+ ((pwrctrl->reg_conn_infra_req_mask_b & 0x1) << 14) |
+ ((pwrctrl->reg_conn_apsrc_req_mask_b & 0x1) << 15) |
+ ((pwrctrl->reg_conn_vrf18_req_mask_b & 0x1) << 16) |
+ ((pwrctrl->reg_conn_ddr_en_mask_b & 0x1) << 17) |
+ ((pwrctrl->reg_conn_vfe28_mask_b & 0x1) << 18) |
+ ((pwrctrl->reg_srcclkeni0_srcclkena_mask_b & 0x1) << 19) |
+ ((pwrctrl->reg_srcclkeni0_infra_req_mask_b & 0x1) << 20) |
+ ((pwrctrl->reg_srcclkeni1_srcclkena_mask_b & 0x1) << 21) |
+ ((pwrctrl->reg_srcclkeni1_infra_req_mask_b & 0x1) << 22) |
+ ((pwrctrl->reg_srcclkeni2_srcclkena_mask_b & 0x1) << 23) |
+ ((pwrctrl->reg_srcclkeni2_infra_req_mask_b & 0x1) << 24) |
+ ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 25) |
+ ((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 26) |
+ ((pwrctrl->reg_md32_srcclkena_mask_b & 0x1) << 27) |
+ ((pwrctrl->reg_md32_infra_req_mask_b & 0x1) << 28) |
+ ((pwrctrl->reg_md32_apsrc_req_mask_b & 0x1) << 29) |
+ ((pwrctrl->reg_md32_vrf18_req_mask_b & 0x1) << 30) |
+ ((pwrctrl->reg_md32_ddr_en_mask_b & 0x1) << 31));
+
+ /* SPM_SRC2_MASK */
+ mmio_write_32(SPM_SRC2_MASK,
+ ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 0) |
+ ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 1) |
+ ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 2) |
+ ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 3) |
+ ((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 4) |
+ ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 5) |
+ ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 6) |
+ ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 7) |
+ ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 8) |
+ ((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 9) |
+ ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 10) |
+ ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 11) |
+ ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 12) |
+ ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 13) |
+ ((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 14) |
+ ((pwrctrl->reg_disp0_apsrc_req_mask_b & 0x1) << 15) |
+ ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 16) |
+ ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 17) |
+ ((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 18) |
+ ((pwrctrl->reg_gce_infra_req_mask_b & 0x1) << 19) |
+ ((pwrctrl->reg_gce_apsrc_req_mask_b & 0x1) << 20) |
+ ((pwrctrl->reg_gce_vrf18_req_mask_b & 0x1) << 21) |
+ ((pwrctrl->reg_gce_ddr_en_mask_b & 0x1) << 22) |
+ ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 23) |
+ ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 24) |
+ ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 25) |
+ ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 26) |
+ ((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 27) |
+ ((pwrctrl->reg_cg_check_srcclkena_mask_b & 0x1) << 28) |
+ ((pwrctrl->reg_cg_check_apsrc_req_mask_b & 0x1) << 29) |
+ ((pwrctrl->reg_cg_check_vrf18_req_mask_b & 0x1) << 30) |
+ ((pwrctrl->reg_cg_check_ddr_en_mask_b & 0x1) << 31));
+
+ /* SPM_SRC3_MASK */
+ mmio_write_32(SPM_SRC3_MASK,
+ ((pwrctrl->reg_dvfsrc_event_trigger_mask_b & 0x1) << 0) |
+ ((pwrctrl->reg_sw2spm_int0_mask_b & 0x1) << 1) |
+ ((pwrctrl->reg_sw2spm_int1_mask_b & 0x1) << 2) |
+ ((pwrctrl->reg_sw2spm_int2_mask_b & 0x1) << 3) |
+ ((pwrctrl->reg_sw2spm_int3_mask_b & 0x1) << 4) |
+ ((pwrctrl->reg_sc_adsp2spm_wakeup_mask_b & 0x1) << 5) |
+ ((pwrctrl->reg_sc_sspm2spm_wakeup_mask_b & 0xf) << 6) |
+ ((pwrctrl->reg_sc_scp2spm_wakeup_mask_b & 0x1) << 10) |
+ ((pwrctrl->reg_csyspwrreq_mask & 0x1) << 11) |
+ ((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 12) |
+ ((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 13) |
+ ((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 14) |
+ ((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 15) |
+ ((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 16) |
+ ((pwrctrl->reg_mcupm_srcclkena_mask_b & 0x1) << 17) |
+ ((pwrctrl->reg_mcupm_infra_req_mask_b & 0x1) << 18) |
+ ((pwrctrl->reg_mcupm_apsrc_req_mask_b & 0x1) << 19) |
+ ((pwrctrl->reg_mcupm_vrf18_req_mask_b & 0x1) << 20) |
+ ((pwrctrl->reg_mcupm_ddr_en_mask_b & 0x1) << 21) |
+ ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 22) |
+ ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 23) |
+ ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 24) |
+ ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 25) |
+ ((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 26) |
+ ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 27) |
+ ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 28) |
+ ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 29) |
+ ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 30) |
+ ((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 31));
+
+ /* SPM_SRC4_MASK */
+ mmio_write_32(SPM_SRC4_MASK,
+ ((pwrctrl->ccif_event_mask_b & 0xffff) << 0) |
+ ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 16) |
+ ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 17) |
+ ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 18) |
+ ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 19) |
+ ((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 20) |
+ ((pwrctrl->reg_dramc0_md32_infra_req_mask_b & 0x1) << 21) |
+ ((pwrctrl->reg_dramc0_md32_vrf18_req_mask_b & 0x1) << 22) |
+ ((pwrctrl->reg_dramc1_md32_infra_req_mask_b & 0x1) << 23) |
+ ((pwrctrl->reg_dramc1_md32_vrf18_req_mask_b & 0x1) << 24) |
+ ((pwrctrl->reg_conn_srcclkenb2pwrap_mask_b & 0x1) << 25) |
+ ((pwrctrl->reg_dramc0_md32_wakeup_mask & 0x1) << 26) |
+ ((pwrctrl->reg_dramc1_md32_wakeup_mask & 0x1) << 27));
+
+ /* SPM_SRC5_MASK */
+ mmio_write_32(SPM_SRC5_MASK,
+ ((pwrctrl->reg_mcusys_merge_apsrc_req_mask_b & 0x1ff) << 0) |
+ ((pwrctrl->reg_mcusys_merge_ddr_en_mask_b & 0x1ff) << 9) |
+ ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 18) |
+ ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 19) |
+ ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 20) |
+ ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 21) |
+ ((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 22) |
+ ((pwrctrl->reg_pcie_srcclkena_mask_b & 0x1) << 23) |
+ ((pwrctrl->reg_pcie_infra_req_mask_b & 0x1) << 24) |
+ ((pwrctrl->reg_pcie_apsrc_req_mask_b & 0x1) << 25) |
+ ((pwrctrl->reg_pcie_vrf18_req_mask_b & 0x1) << 26) |
+ ((pwrctrl->reg_pcie_ddr_en_mask_b & 0x1) << 27));
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ mmio_write_32(SPM_WAKEUP_EVENT_MASK,
+ ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK,
+ ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
+
+ /* Auto-gen End */
+}
+
+void __spm_disable_pcm_timer(void)
+{
+ mmio_clrsetbits_32(PCM_CON1, RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
+}
+
+void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
+{
+ uint32_t val, mask;
+
+ /* toggle event counter clear */
+ mmio_setbits_32(PCM_CON1,
+ SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB);
+
+ /* toggle for reset SYS TIMER start point */
+ mmio_setbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
+
+ if (pwrctrl->timer_val_cust == 0U) {
+ val = pwrctrl->timer_val;
+ } else {
+ val = pwrctrl->timer_val_cust;
+ }
+
+ mmio_write_32(PCM_TIMER_VAL, val);
+ mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB);
+
+ /* unmask AP wakeup source */
+ if (pwrctrl->wake_src_cust == 0U) {
+ mask = pwrctrl->wake_src;
+ } else {
+ mask = pwrctrl->wake_src_cust;
+ }
+
+ if (pwrctrl->reg_csyspwrreq_mask != 0U) {
+ mask &= ~R12_CSYSPWREQ_B;
+ }
+
+ mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask);
+
+ /* unmask SPM ISR (keep TWAM setting) */
+ mmio_setbits_32(SPM_IRQ_MASK, ISRM_RET_IRQ_AUX);
+
+ /* toggle event counter clear */
+ mmio_clrsetbits_32(PCM_CON1, SPM_EVENT_COUNTER_CLR_LSB,
+ SPM_REGWR_CFG_KEY);
+ /* toggle for reset SYS TIMER start point */
+ mmio_clrbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
+}
+
+void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl)
+{
+ /* set PCM flags and data */
+ if (pwrctrl->pcm_flags_cust_clr != 0U) {
+ pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
+ }
+
+ if (pwrctrl->pcm_flags_cust_set != 0U) {
+ pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set;
+ }
+
+ if (pwrctrl->pcm_flags1_cust_clr != 0U) {
+ pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
+ }
+
+ if (pwrctrl->pcm_flags1_cust_set != 0U) {
+ pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
+ }
+
+ mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags);
+ mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1);
+ mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags);
+ mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1);
+}
+
+void __spm_get_wakeup_status(struct wake_status *wakesta,
+ unsigned int ext_status)
+{
+ wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
+ wakesta->tr.comm.timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
+ wakesta->tr.comm.r13 = mmio_read_32(PCM_REG13_DATA);
+ wakesta->tr.comm.req_sta0 = mmio_read_32(SRC_REQ_STA_0);
+ wakesta->tr.comm.req_sta1 = mmio_read_32(SRC_REQ_STA_1);
+ wakesta->tr.comm.req_sta2 = mmio_read_32(SRC_REQ_STA_2);
+ wakesta->tr.comm.req_sta3 = mmio_read_32(SRC_REQ_STA_3);
+ wakesta->tr.comm.req_sta4 = mmio_read_32(SRC_REQ_STA_4);
+ wakesta->tr.comm.debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
+ wakesta->tr.comm.debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
+
+ if ((ext_status & SPM_INTERNAL_STATUS_HW_S1) != 0U) {
+ wakesta->tr.comm.debug_flag |= (SPM_DBG_DEBUG_IDX_DDREN_WAKE |
+ SPM_DBG_DEBUG_IDX_DDREN_SLEEP);
+ mmio_write_32(PCM_WDT_LATCH_SPARE_0,
+ wakesta->tr.comm.debug_flag);
+ }
+
+ wakesta->tr.comm.b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
+ wakesta->tr.comm.b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
+
+ /* record below spm info for debug */
+ wakesta->r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
+ wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_STA);
+ wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA);
+ wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA);
+ wakesta->md32pcm_wakeup_sta = mmio_read_32(MD32PCM_WAKEUP_STA);
+ wakesta->md32pcm_event_sta = mmio_read_32(MD32PCM_EVENT_STA);
+ wakesta->src_req = mmio_read_32(SPM_SRC_REQ);
+
+ /* backup of SPM_WAKEUP_MISC */
+ wakesta->wake_misc = mmio_read_32(SPM_BK_WAKE_MISC);
+
+ /* get sleep time, backup of PCM_TIMER_OUT */
+ wakesta->timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
+
+ /* get other SYS and co-clock status */
+ wakesta->r13 = mmio_read_32(PCM_REG13_DATA);
+ wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA);
+ wakesta->req_sta0 = mmio_read_32(SRC_REQ_STA_0);
+ wakesta->req_sta1 = mmio_read_32(SRC_REQ_STA_1);
+ wakesta->req_sta2 = mmio_read_32(SRC_REQ_STA_2);
+ wakesta->req_sta3 = mmio_read_32(SRC_REQ_STA_3);
+ wakesta->req_sta4 = mmio_read_32(SRC_REQ_STA_4);
+
+ /* get HW CG check status */
+ wakesta->cg_check_sta = mmio_read_32(SPM_CG_CHECK_STA);
+
+ /* get debug flag for PCM execution check */
+ wakesta->debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
+ wakesta->debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
+
+ /* get backup SW flag status */
+ wakesta->b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
+ wakesta->b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
+
+ wakesta->rt_req_sta0 = mmio_read_32(SPM_SW_RSV_2);
+ wakesta->rt_req_sta1 = mmio_read_32(SPM_SW_RSV_3);
+ wakesta->rt_req_sta2 = mmio_read_32(SPM_SW_RSV_4);
+ wakesta->rt_req_sta3 = mmio_read_32(SPM_SW_RSV_5);
+ wakesta->rt_req_sta4 = mmio_read_32(SPM_SW_RSV_6);
+
+ /* get ISR status */
+ wakesta->isr = mmio_read_32(SPM_IRQ_STA);
+
+ /* get SW flag status */
+ wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0);
+ wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1);
+
+ /* get CLK SETTLE */
+ wakesta->clk_settle = mmio_read_32(SPM_CLK_SETTLE);
+
+ /* check abort */
+ wakesta->abort = (wakesta->debug_flag & DEBUG_ABORT_MASK) |
+ (wakesta->debug_flag1 & DEBUG_ABORT_MASK_1);
+}
+
+void __spm_clean_after_wakeup(void)
+{
+ mmio_write_32(SPM_BK_WAKE_EVENT,
+ mmio_read_32(SPM_WAKEUP_STA) |
+ mmio_read_32(SPM_BK_WAKE_EVENT));
+ mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0);
+
+ /*
+ * clean wakeup event raw status (for edge trigger event)
+ * bit[28] for cpu wake up event
+ */
+ mmio_write_32(SPM_WAKEUP_EVENT_MASK, SPM_WAKEUP_EVENT_MASK_CLEAN_MASK);
+
+ /* clean ISR status (except TWAM) */
+ mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM);
+ mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM);
+ mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL);
+}
+
+void __spm_set_pcm_wdt(int en)
+{
+ mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB,
+ SPM_REGWR_CFG_KEY);
+
+ if (en == 1) {
+ mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB,
+ SPM_REGWR_CFG_KEY);
+
+ if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) {
+ mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX);
+ }
+
+ mmio_write_32(PCM_WDT_VAL,
+ mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
+ mmio_setbits_32(PCM_CON1,
+ SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB);
+ }
+}
+
+void __spm_send_cpu_wakeup_event(void)
+{
+ /* SPM will clear SPM_CPU_WAKEUP_EVENT */
+ mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1);
+}
+
+void __spm_ext_int_wakeup_req_clr(void)
+{
+ mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, mmio_read_32(ROOT_CPUTOP_ADDR));
+
+ /* Clear spm2mcupm wakeup interrupt status */
+ mmio_write_32(SPM2MCUPM_CON, 0);
+}
+
+void __spm_xo_soc_bblpm(int en)
+{
+ if (en == 1) {
+ mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
+ RC_SW_SRCLKEN_FPM, RC_SW_SRCLKEN_RC);
+ assert(mt_spm_bblpm_cnt == 0);
+ mt_spm_bblpm_cnt += 1;
+ } else {
+ mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
+ RC_SW_SRCLKEN_RC, RC_SW_SRCLKEN_FPM);
+ mt_spm_bblpm_cnt -= 1;
+ }
+}
+
+void __spm_hw_s1_state_monitor(int en, unsigned int *status)
+{
+ unsigned int reg;
+
+ reg = mmio_read_32(SPM_ACK_CHK_CON_3);
+
+ if (en == 1) {
+ reg &= ~SPM_ACK_CHK_3_CON_CLR_ALL;
+ mmio_write_32(SPM_ACK_CHK_CON_3, reg);
+ reg |= SPM_ACK_CHK_3_CON_EN;
+ mmio_write_32(SPM_ACK_CHK_CON_3, reg);
+ } else {
+ if (((reg & SPM_ACK_CHK_3_CON_RESULT) != 0U) &&
+ (status != NULL)) {
+ *status |= SPM_INTERNAL_STATUS_HW_S1;
+ }
+
+ mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN,
+ SPM_ACK_CHK_3_CON_HW_MODE_TRIG |
+ SPM_ACK_CHK_3_CON_CLR_ALL);
+ }
+}
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_internal.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_internal.h
new file mode 100644
index 0000000..1d0f783
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_internal.h
@@ -0,0 +1,637 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_INTERNAL_H
+#define MT_SPM_INTERNAL_H
+
+#include "mt_spm.h"
+
+/**************************************
+ * Config and Parameter
+ **************************************/
+#define POWER_ON_VAL0_DEF 0x0000F100
+#define POWER_ON_VAL1_DEF 0x80015860
+#define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */
+#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT)
+
+/**************************************
+ * Define and Declare
+ **************************************/
+/* PCM_PWR_IO_EN */
+#define PCM_PWRIO_EN_R0 (1U << 0)
+#define PCM_PWRIO_EN_R7 (1U << 7)
+#define PCM_RF_SYNC_R0 (1U << 16)
+#define PCM_RF_SYNC_R6 (1U << 22)
+#define PCM_RF_SYNC_R7 (1U << 23)
+
+/* SPM_SWINT */
+#define PCM_SW_INT0 (1U << 0)
+#define PCM_SW_INT1 (1U << 1)
+#define PCM_SW_INT2 (1U << 2)
+#define PCM_SW_INT3 (1U << 3)
+#define PCM_SW_INT4 (1U << 4)
+#define PCM_SW_INT5 (1U << 5)
+#define PCM_SW_INT6 (1U << 6)
+#define PCM_SW_INT7 (1U << 7)
+#define PCM_SW_INT8 (1U << 8)
+#define PCM_SW_INT9 (1U << 9)
+#define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \
+ PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \
+ PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \
+ PCM_SW_INT0)
+
+/* SPM_AP_STANDBY_CON */
+#define WFI_OP_AND 1
+#define WFI_OP_OR 0
+
+/* SPM_IRQ_MASK */
+#define ISRM_TWAM (1U << 2)
+#define ISRM_PCM_RETURN (1U << 3)
+#define ISRM_RET_IRQ0 (1U << 8)
+#define ISRM_RET_IRQ1 (1U << 9)
+#define ISRM_RET_IRQ2 (1U << 10)
+#define ISRM_RET_IRQ3 (1U << 11)
+#define ISRM_RET_IRQ4 (1U << 12)
+#define ISRM_RET_IRQ5 (1U << 13)
+#define ISRM_RET_IRQ6 (1U << 14)
+#define ISRM_RET_IRQ7 (1U << 15)
+#define ISRM_RET_IRQ8 (1U << 16)
+#define ISRM_RET_IRQ9 (1U << 17)
+#define ISRM_RET_IRQ_AUX ((ISRM_RET_IRQ9) | (ISRM_RET_IRQ8) | \
+ (ISRM_RET_IRQ7) | (ISRM_RET_IRQ6) | \
+ (ISRM_RET_IRQ5) | (ISRM_RET_IRQ4) | \
+ (ISRM_RET_IRQ3) | (ISRM_RET_IRQ2) | \
+ (ISRM_RET_IRQ1))
+#define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX)
+#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM)
+
+/* SPM_IRQ_STA */
+#define ISRS_TWAM (1U << 2)
+#define ISRS_PCM_RETURN (1U << 3)
+#define ISRC_TWAM ISRS_TWAM
+#define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN
+#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM)
+
+/* SPM_WAKEUP_MISC */
+#define WAKE_MISC_GIC_WAKEUP 0x3FF
+#define WAKE_MISC_DVFSRC_IRQ DVFSRC_IRQ_LSB
+#define WAKE_MISC_REG_CPU_WAKEUP SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB
+#define WAKE_MISC_PCM_TIMER_EVENT PCM_TIMER_EVENT_LSB
+#define WAKE_MISC_PMIC_OUT_B ((1U << 19) | (1U << 20))
+#define WAKE_MISC_TWAM_IRQ_B TWAM_IRQ_B_LSB
+#define WAKE_MISC_PMSR_IRQ_B_SET0 PMSR_IRQ_B_SET0_LSB
+#define WAKE_MISC_PMSR_IRQ_B_SET1 PMSR_IRQ_B_SET1_LSB
+#define WAKE_MISC_PMSR_IRQ_B_SET2 PMSR_IRQ_B_SET2_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0 SPM_ACK_CHK_WAKEUP_0_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1 SPM_ACK_CHK_WAKEUP_1_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2 SPM_ACK_CHK_WAKEUP_2_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3 SPM_ACK_CHK_WAKEUP_3_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL SPM_ACK_CHK_WAKEUP_ALL_LSB
+#define WAKE_MISC_PMIC_IRQ_ACK PMIC_IRQ_ACK_LSB
+#define WAKE_MISC_PMIC_SCP_IRQ PMIC_SCP_IRQ_LSB
+
+/* ABORT MASK for DEBUG FOORTPRINT */
+#define DEBUG_ABORT_MASK \
+ (SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC | \
+ SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN)
+
+#define DEBUG_ABORT_MASK_1 \
+ (SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT | \
+ SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT | \
+ SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT | \
+ SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT | \
+ SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT | \
+ SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT | \
+ SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT)
+
+#define MCUPM_MBOX_WAKEUP_CPU 0x0C55FD10
+
+struct pwr_ctrl {
+ uint32_t pcm_flags;
+ uint32_t pcm_flags_cust;
+ uint32_t pcm_flags_cust_set;
+ uint32_t pcm_flags_cust_clr;
+ uint32_t pcm_flags1;
+ uint32_t pcm_flags1_cust;
+ uint32_t pcm_flags1_cust_set;
+ uint32_t pcm_flags1_cust_clr;
+ uint32_t timer_val;
+ uint32_t timer_val_cust;
+ uint32_t timer_val_ramp_en;
+ uint32_t timer_val_ramp_en_sec;
+ uint32_t wake_src;
+ uint32_t wake_src_cust;
+ uint32_t wakelock_timer_val;
+ uint8_t wdt_disable;
+
+ /* Auto-gen Start */
+
+ /* SPM_CLK_CON */
+ uint8_t reg_srcclken0_ctl;
+ uint8_t reg_srcclken1_ctl;
+ uint8_t reg_spm_lock_infra_dcm;
+ uint8_t reg_srcclken_mask;
+ uint8_t reg_md1_c32rm_en;
+ uint8_t reg_md2_c32rm_en;
+ uint8_t reg_clksq0_sel_ctrl;
+ uint8_t reg_clksq1_sel_ctrl;
+ uint8_t reg_srcclken0_en;
+ uint8_t reg_srcclken1_en;
+ uint32_t reg_sysclk0_src_mask_b;
+ uint32_t reg_sysclk1_src_mask_b;
+
+ /* SPM_AP_STANDBY_CON */
+ uint8_t reg_wfi_op;
+ uint8_t reg_wfi_type;
+ uint8_t reg_mp0_cputop_idle_mask;
+ uint8_t reg_mp1_cputop_idle_mask;
+ uint8_t reg_mcusys_idle_mask;
+ uint8_t reg_md_apsrc_1_sel;
+ uint8_t reg_md_apsrc_0_sel;
+ uint8_t reg_conn_apsrc_sel;
+
+ /* SPM_SRC6_MASK */
+ uint8_t reg_dpmaif_srcclkena_mask_b;
+ uint8_t reg_dpmaif_infra_req_mask_b;
+ uint8_t reg_dpmaif_apsrc_req_mask_b;
+ uint8_t reg_dpmaif_vrf18_req_mask_b;
+ uint8_t reg_dpmaif_ddr_en_mask_b;
+ /* SPM_SRC_REQ */
+ uint8_t reg_spm_apsrc_req;
+ uint8_t reg_spm_f26m_req;
+ uint8_t reg_spm_infra_req;
+ uint8_t reg_spm_vrf18_req;
+ uint8_t reg_spm_ddr_en_req;
+ uint8_t reg_spm_dvfs_req;
+ uint8_t reg_spm_sw_mailbox_req;
+ uint8_t reg_spm_sspm_mailbox_req;
+ uint8_t reg_spm_adsp_mailbox_req;
+ uint8_t reg_spm_scp_mailbox_req;
+
+ /* SPM_SRC_MASK */
+ uint8_t reg_md_srcclkena_0_mask_b;
+ uint8_t reg_md_srcclkena2infra_req_0_mask_b;
+ uint8_t reg_md_apsrc2infra_req_0_mask_b;
+ uint8_t reg_md_apsrc_req_0_mask_b;
+ uint8_t reg_md_vrf18_req_0_mask_b;
+ uint8_t reg_md_ddr_en_0_mask_b;
+ uint8_t reg_md_srcclkena_1_mask_b;
+ uint8_t reg_md_srcclkena2infra_req_1_mask_b;
+ uint8_t reg_md_apsrc2infra_req_1_mask_b;
+ uint8_t reg_md_apsrc_req_1_mask_b;
+ uint8_t reg_md_vrf18_req_1_mask_b;
+ uint8_t reg_md_ddr_en_1_mask_b;
+ uint8_t reg_conn_srcclkena_mask_b;
+ uint8_t reg_conn_srcclkenb_mask_b;
+ uint8_t reg_conn_infra_req_mask_b;
+ uint8_t reg_conn_apsrc_req_mask_b;
+ uint8_t reg_conn_vrf18_req_mask_b;
+ uint8_t reg_conn_ddr_en_mask_b;
+ uint8_t reg_conn_vfe28_mask_b;
+ uint8_t reg_srcclkeni0_srcclkena_mask_b;
+ uint8_t reg_srcclkeni0_infra_req_mask_b;
+ uint8_t reg_srcclkeni1_srcclkena_mask_b;
+ uint8_t reg_srcclkeni1_infra_req_mask_b;
+ uint8_t reg_srcclkeni2_srcclkena_mask_b;
+ uint8_t reg_srcclkeni2_infra_req_mask_b;
+ uint8_t reg_infrasys_apsrc_req_mask_b;
+ uint8_t reg_infrasys_ddr_en_mask_b;
+ uint8_t reg_md32_srcclkena_mask_b;
+ uint8_t reg_md32_infra_req_mask_b;
+ uint8_t reg_md32_apsrc_req_mask_b;
+ uint8_t reg_md32_vrf18_req_mask_b;
+ uint8_t reg_md32_ddr_en_mask_b;
+
+ /* SPM_SRC2_MASK */
+ uint8_t reg_scp_srcclkena_mask_b;
+ uint8_t reg_scp_infra_req_mask_b;
+ uint8_t reg_scp_apsrc_req_mask_b;
+ uint8_t reg_scp_vrf18_req_mask_b;
+ uint8_t reg_scp_ddr_en_mask_b;
+ uint8_t reg_audio_dsp_srcclkena_mask_b;
+ uint8_t reg_audio_dsp_infra_req_mask_b;
+ uint8_t reg_audio_dsp_apsrc_req_mask_b;
+ uint8_t reg_audio_dsp_vrf18_req_mask_b;
+ uint8_t reg_audio_dsp_ddr_en_mask_b;
+ uint8_t reg_ufs_srcclkena_mask_b;
+ uint8_t reg_ufs_infra_req_mask_b;
+ uint8_t reg_ufs_apsrc_req_mask_b;
+ uint8_t reg_ufs_vrf18_req_mask_b;
+ uint8_t reg_ufs_ddr_en_mask_b;
+ uint8_t reg_disp0_apsrc_req_mask_b;
+ uint8_t reg_disp0_ddr_en_mask_b;
+ uint8_t reg_disp1_apsrc_req_mask_b;
+ uint8_t reg_disp1_ddr_en_mask_b;
+ uint8_t reg_gce_infra_req_mask_b;
+ uint8_t reg_gce_apsrc_req_mask_b;
+ uint8_t reg_gce_vrf18_req_mask_b;
+ uint8_t reg_gce_ddr_en_mask_b;
+ uint8_t reg_apu_srcclkena_mask_b;
+ uint8_t reg_apu_infra_req_mask_b;
+ uint8_t reg_apu_apsrc_req_mask_b;
+ uint8_t reg_apu_vrf18_req_mask_b;
+ uint8_t reg_apu_ddr_en_mask_b;
+ uint8_t reg_cg_check_srcclkena_mask_b;
+ uint8_t reg_cg_check_apsrc_req_mask_b;
+ uint8_t reg_cg_check_vrf18_req_mask_b;
+ uint8_t reg_cg_check_ddr_en_mask_b;
+
+ /* SPM_SRC3_MASK */
+ uint8_t reg_dvfsrc_event_trigger_mask_b;
+ uint8_t reg_sw2spm_int0_mask_b;
+ uint8_t reg_sw2spm_int1_mask_b;
+ uint8_t reg_sw2spm_int2_mask_b;
+ uint8_t reg_sw2spm_int3_mask_b;
+ uint8_t reg_sc_adsp2spm_wakeup_mask_b;
+ uint8_t reg_sc_sspm2spm_wakeup_mask_b;
+ uint8_t reg_sc_scp2spm_wakeup_mask_b;
+ uint8_t reg_csyspwrreq_mask;
+ uint8_t reg_spm_srcclkena_reserved_mask_b;
+ uint8_t reg_spm_infra_req_reserved_mask_b;
+ uint8_t reg_spm_apsrc_req_reserved_mask_b;
+ uint8_t reg_spm_vrf18_req_reserved_mask_b;
+ uint8_t reg_spm_ddr_en_reserved_mask_b;
+ uint8_t reg_mcupm_srcclkena_mask_b;
+ uint8_t reg_mcupm_infra_req_mask_b;
+ uint8_t reg_mcupm_apsrc_req_mask_b;
+ uint8_t reg_mcupm_vrf18_req_mask_b;
+ uint8_t reg_mcupm_ddr_en_mask_b;
+ uint8_t reg_msdc0_srcclkena_mask_b;
+ uint8_t reg_msdc0_infra_req_mask_b;
+ uint8_t reg_msdc0_apsrc_req_mask_b;
+ uint8_t reg_msdc0_vrf18_req_mask_b;
+ uint8_t reg_msdc0_ddr_en_mask_b;
+ uint8_t reg_msdc1_srcclkena_mask_b;
+ uint8_t reg_msdc1_infra_req_mask_b;
+ uint8_t reg_msdc1_apsrc_req_mask_b;
+ uint8_t reg_msdc1_vrf18_req_mask_b;
+ uint8_t reg_msdc1_ddr_en_mask_b;
+
+ /* SPM_SRC4_MASK */
+ uint32_t ccif_event_mask_b;
+ uint8_t reg_bak_psri_srcclkena_mask_b;
+ uint8_t reg_bak_psri_infra_req_mask_b;
+ uint8_t reg_bak_psri_apsrc_req_mask_b;
+ uint8_t reg_bak_psri_vrf18_req_mask_b;
+ uint8_t reg_bak_psri_ddr_en_mask_b;
+ uint8_t reg_dramc0_md32_infra_req_mask_b;
+ uint8_t reg_dramc0_md32_vrf18_req_mask_b;
+ uint8_t reg_dramc1_md32_infra_req_mask_b;
+ uint8_t reg_dramc1_md32_vrf18_req_mask_b;
+ uint8_t reg_conn_srcclkenb2pwrap_mask_b;
+ uint8_t reg_dramc0_md32_wakeup_mask;
+ uint8_t reg_dramc1_md32_wakeup_mask;
+
+ /* SPM_SRC5_MASK */
+ uint32_t reg_mcusys_merge_apsrc_req_mask_b;
+ uint32_t reg_mcusys_merge_ddr_en_mask_b;
+ uint8_t reg_msdc2_srcclkena_mask_b;
+ uint8_t reg_msdc2_infra_req_mask_b;
+ uint8_t reg_msdc2_apsrc_req_mask_b;
+ uint8_t reg_msdc2_vrf18_req_mask_b;
+ uint8_t reg_msdc2_ddr_en_mask_b;
+ uint8_t reg_pcie_srcclkena_mask_b;
+ uint8_t reg_pcie_infra_req_mask_b;
+ uint8_t reg_pcie_apsrc_req_mask_b;
+ uint8_t reg_pcie_vrf18_req_mask_b;
+ uint8_t reg_pcie_ddr_en_mask_b;
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ uint32_t reg_wakeup_event_mask;
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ uint32_t reg_ext_wakeup_event_mask;
+
+ /* Auto-gen End */
+};
+
+/* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */
+enum pwr_ctrl_enum {
+ PW_PCM_FLAGS,
+ PW_PCM_FLAGS_CUST,
+ PW_PCM_FLAGS_CUST_SET,
+ PW_PCM_FLAGS_CUST_CLR,
+ PW_PCM_FLAGS1,
+ PW_PCM_FLAGS1_CUST,
+ PW_PCM_FLAGS1_CUST_SET,
+ PW_PCM_FLAGS1_CUST_CLR,
+ PW_TIMER_VAL,
+ PW_TIMER_VAL_CUST,
+ PW_TIMER_VAL_RAMP_EN,
+ PW_TIMER_VAL_RAMP_EN_SEC,
+ PW_WAKE_SRC,
+ PW_WAKE_SRC_CUST,
+ PW_WAKELOCK_TIMER_VAL,
+ PW_WDT_DISABLE,
+
+ /* SPM_CLK_CON */
+ PW_REG_SRCCLKEN0_CTL,
+ PW_REG_SRCCLKEN1_CTL,
+ PW_REG_SPM_LOCK_INFRA_DCM,
+ PW_REG_SRCCLKEN_MASK,
+ PW_REG_MD1_C32RM_EN,
+ PW_REG_MD2_C32RM_EN,
+ PW_REG_CLKSQ0_SEL_CTRL,
+ PW_REG_CLKSQ1_SEL_CTRL,
+ PW_REG_SRCCLKEN0_EN,
+ PW_REG_SRCCLKEN1_EN,
+ PW_REG_SYSCLK0_SRC_MASK_B,
+ PW_REG_SYSCLK1_SRC_MASK_B,
+
+ /* SPM_AP_STANDBY_CON */
+ PW_REG_WFI_OP,
+ PW_REG_WFI_TYPE,
+ PW_REG_MP0_CPUTOP_IDLE_MASK,
+ PW_REG_MP1_CPUTOP_IDLE_MASK,
+ PW_REG_MCUSYS_IDLE_MASK,
+ PW_REG_MD_APSRC_1_SEL,
+ PW_REG_MD_APSRC_0_SEL,
+ PW_REG_CONN_APSRC_SEL,
+
+ /* SPM_SRC6_MASK */
+ PW_REG_DPMAIF_SRCCLKENA_MASK_B,
+ PW_REG_DPMAIF_INFRA_REQ_MASK_B,
+ PW_REG_DPMAIF_APSRC_REQ_MASK_B,
+ PW_REG_DPMAIF_VRF18_REQ_MASK_B,
+ PW_REG_DPMAIF_DDR_EN_MASK_B,
+
+ /* SPM_SRC_REQ */
+ PW_REG_SPM_APSRC_REQ,
+ PW_REG_SPM_F26M_REQ,
+ PW_REG_SPM_INFRA_REQ,
+ PW_REG_SPM_VRF18_REQ,
+ PW_REG_SPM_DDR_EN_REQ,
+ PW_REG_SPM_DVFS_REQ,
+ PW_REG_SPM_SW_MAILBOX_REQ,
+ PW_REG_SPM_SSPM_MAILBOX_REQ,
+ PW_REG_SPM_ADSP_MAILBOX_REQ,
+ PW_REG_SPM_SCP_MAILBOX_REQ,
+
+ /* SPM_SRC_MASK */
+ PW_REG_MD_SRCCLKENA_0_MASK_B,
+ PW_REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B,
+ PW_REG_MD_APSRC2INFRA_REQ_0_MASK_B,
+ PW_REG_MD_APSRC_REQ_0_MASK_B,
+ PW_REG_MD_VRF18_REQ_0_MASK_B,
+ PW_REG_MD_DDR_EN_0_MASK_B,
+ PW_REG_MD_SRCCLKENA_1_MASK_B,
+ PW_REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B,
+ PW_REG_MD_APSRC2INFRA_REQ_1_MASK_B,
+ PW_REG_MD_APSRC_REQ_1_MASK_B,
+ PW_REG_MD_VRF18_REQ_1_MASK_B,
+ PW_REG_MD_DDR_EN_1_MASK_B,
+ PW_REG_CONN_SRCCLKENA_MASK_B,
+ PW_REG_CONN_SRCCLKENB_MASK_B,
+ PW_REG_CONN_INFRA_REQ_MASK_B,
+ PW_REG_CONN_APSRC_REQ_MASK_B,
+ PW_REG_CONN_VRF18_REQ_MASK_B,
+ PW_REG_CONN_DDR_EN_MASK_B,
+ PW_REG_CONN_VFE28_MASK_B,
+ PW_REG_SRCCLKENI0_SRCCLKENA_MASK_B,
+ PW_REG_SRCCLKENI0_INFRA_REQ_MASK_B,
+ PW_REG_SRCCLKENI1_SRCCLKENA_MASK_B,
+ PW_REG_SRCCLKENI1_INFRA_REQ_MASK_B,
+ PW_REG_SRCCLKENI2_SRCCLKENA_MASK_B,
+ PW_REG_SRCCLKENI2_INFRA_REQ_MASK_B,
+ PW_REG_INFRASYS_APSRC_REQ_MASK_B,
+ PW_REG_INFRASYS_DDR_EN_MASK_B,
+ PW_REG_MD32_SRCCLKENA_MASK_B,
+ PW_REG_MD32_INFRA_REQ_MASK_B,
+ PW_REG_MD32_APSRC_REQ_MASK_B,
+ PW_REG_MD32_VRF18_REQ_MASK_B,
+ PW_REG_MD32_DDR_EN_MASK_B,
+
+ /* SPM_SRC2_MASK */
+ PW_REG_SCP_SRCCLKENA_MASK_B,
+ PW_REG_SCP_INFRA_REQ_MASK_B,
+ PW_REG_SCP_APSRC_REQ_MASK_B,
+ PW_REG_SCP_VRF18_REQ_MASK_B,
+ PW_REG_SCP_DDR_EN_MASK_B,
+ PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B,
+ PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B,
+ PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B,
+ PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B,
+ PW_REG_AUDIO_DSP_DDR_EN_MASK_B,
+ PW_REG_UFS_SRCCLKENA_MASK_B,
+ PW_REG_UFS_INFRA_REQ_MASK_B,
+ PW_REG_UFS_APSRC_REQ_MASK_B,
+ PW_REG_UFS_VRF18_REQ_MASK_B,
+ PW_REG_UFS_DDR_EN_MASK_B,
+ PW_REG_DISP0_APSRC_REQ_MASK_B,
+ PW_REG_DISP0_DDR_EN_MASK_B,
+ PW_REG_DISP1_APSRC_REQ_MASK_B,
+ PW_REG_DISP1_DDR_EN_MASK_B,
+ PW_REG_GCE_INFRA_REQ_MASK_B,
+ PW_REG_GCE_APSRC_REQ_MASK_B,
+ PW_REG_GCE_VRF18_REQ_MASK_B,
+ PW_REG_GCE_DDR_EN_MASK_B,
+ PW_REG_APU_SRCCLKENA_MASK_B,
+ PW_REG_APU_INFRA_REQ_MASK_B,
+ PW_REG_APU_APSRC_REQ_MASK_B,
+ PW_REG_APU_VRF18_REQ_MASK_B,
+ PW_REG_APU_DDR_EN_MASK_B,
+ PW_REG_CG_CHECK_SRCCLKENA_MASK_B,
+ PW_REG_CG_CHECK_APSRC_REQ_MASK_B,
+ PW_REG_CG_CHECK_VRF18_REQ_MASK_B,
+ PW_REG_CG_CHECK_DDR_EN_MASK_B,
+
+ /* SPM_SRC3_MASK */
+ PW_REG_DVFSRC_EVENT_TRIGGER_MASK_B,
+ PW_REG_SW2SPM_INT0_MASK_B,
+ PW_REG_SW2SPM_INT1_MASK_B,
+ PW_REG_SW2SPM_INT2_MASK_B,
+ PW_REG_SW2SPM_INT3_MASK_B,
+ PW_REG_SC_ADSP2SPM_WAKEUP_MASK_B,
+ PW_REG_SC_SSPM2SPM_WAKEUP_MASK_B,
+ PW_REG_SC_SCP2SPM_WAKEUP_MASK_B,
+ PW_REG_CSYSPWRREQ_MASK,
+ PW_REG_SPM_SRCCLKENA_RESERVED_MASK_B,
+ PW_REG_SPM_INFRA_REQ_RESERVED_MASK_B,
+ PW_REG_SPM_APSRC_REQ_RESERVED_MASK_B,
+ PW_REG_SPM_VRF18_REQ_RESERVED_MASK_B,
+ PW_REG_SPM_DDR_EN_RESERVED_MASK_B,
+ PW_REG_MCUPM_SRCCLKENA_MASK_B,
+ PW_REG_MCUPM_INFRA_REQ_MASK_B,
+ PW_REG_MCUPM_APSRC_REQ_MASK_B,
+ PW_REG_MCUPM_VRF18_REQ_MASK_B,
+ PW_REG_MCUPM_DDR_EN_MASK_B,
+ PW_REG_MSDC0_SRCCLKENA_MASK_B,
+ PW_REG_MSDC0_INFRA_REQ_MASK_B,
+ PW_REG_MSDC0_APSRC_REQ_MASK_B,
+ PW_REG_MSDC0_VRF18_REQ_MASK_B,
+ PW_REG_MSDC0_DDR_EN_MASK_B,
+ PW_REG_MSDC1_SRCCLKENA_MASK_B,
+ PW_REG_MSDC1_INFRA_REQ_MASK_B,
+ PW_REG_MSDC1_APSRC_REQ_MASK_B,
+ PW_REG_MSDC1_VRF18_REQ_MASK_B,
+ PW_REG_MSDC1_DDR_EN_MASK_B,
+
+ /* SPM_SRC4_MASK */
+ PW_CCIF_EVENT_MASK_B,
+ PW_REG_BAK_PSRI_SRCCLKENA_MASK_B,
+ PW_REG_BAK_PSRI_INFRA_REQ_MASK_B,
+ PW_REG_BAK_PSRI_APSRC_REQ_MASK_B,
+ PW_REG_BAK_PSRI_VRF18_REQ_MASK_B,
+ PW_REG_BAK_PSRI_DDR_EN_MASK_B,
+ PW_REG_DRAMC0_MD32_INFRA_REQ_MASK_B,
+ PW_REG_DRAMC0_MD32_VRF18_REQ_MASK_B,
+ PW_REG_DRAMC1_MD32_INFRA_REQ_MASK_B,
+ PW_REG_DRAMC1_MD32_VRF18_REQ_MASK_B,
+ PW_REG_CONN_SRCCLKENB2PWRAP_MASK_B,
+ PW_REG_DRAMC0_MD32_WAKEUP_MASK,
+ PW_REG_DRAMC1_MD32_WAKEUP_MASK,
+
+ /* SPM_SRC5_MASK */
+ PW_REG_MCUSYS_MERGE_APSRC_REQ_MASK_B,
+ PW_REG_MCUSYS_MERGE_DDR_EN_MASK_B,
+ PW_REG_MSDC2_SRCCLKENA_MASK_B,
+ PW_REG_MSDC2_INFRA_REQ_MASK_B,
+ PW_REG_MSDC2_APSRC_REQ_MASK_B,
+ PW_REG_MSDC2_VRF18_REQ_MASK_B,
+ PW_REG_MSDC2_DDR_EN_MASK_B,
+ PW_REG_PCIE_SRCCLKENA_MASK_B,
+ PW_REG_PCIE_INFRA_REQ_MASK_B,
+ PW_REG_PCIE_APSRC_REQ_MASK_B,
+ PW_REG_PCIE_VRF18_REQ_MASK_B,
+ PW_REG_PCIE_DDR_EN_MASK_B,
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ PW_REG_WAKEUP_EVENT_MASK,
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ PW_REG_EXT_WAKEUP_EVENT_MASK,
+
+ PW_MAX_COUNT,
+};
+
+#define SPM_INTERNAL_STATUS_HW_S1 (1U << 0)
+#define SPM_ACK_CHK_3_SEL_HW_S1 0x00350098
+#define SPM_ACK_CHK_3_HW_S1_CNT 1
+#define SPM_ACK_CHK_3_CON_HW_MODE_TRIG 0x800
+#define SPM_ACK_CHK_3_CON_EN 0x110
+#define SPM_ACK_CHK_3_CON_CLR_ALL 0x2
+#define SPM_ACK_CHK_3_CON_RESULT 0x8000
+
+struct wake_status_trace_comm {
+ uint32_t debug_flag; /* PCM_WDT_LATCH_SPARE_0 */
+ uint32_t debug_flag1; /* PCM_WDT_LATCH_SPARE_1 */
+ uint32_t timer_out; /* SPM_SW_RSV_6*/
+ uint32_t b_sw_flag0; /* SPM_SW_RSV_7 */
+ uint32_t b_sw_flag1; /* SPM_SW_RSV_7 */
+ uint32_t r12; /* SPM_SW_RSV_0 */
+ uint32_t r13; /* PCM_REG13_DATA */
+ uint32_t req_sta0; /* SRC_REQ_STA_0 */
+ uint32_t req_sta1; /* SRC_REQ_STA_1 */
+ uint32_t req_sta2; /* SRC_REQ_STA_2 */
+ uint32_t req_sta3; /* SRC_REQ_STA_3 */
+ uint32_t req_sta4; /* SRC_REQ_STA_4 */
+};
+
+struct wake_status_trace {
+ struct wake_status_trace_comm comm;
+};
+
+struct wake_status {
+ struct wake_status_trace tr;
+ uint32_t r12; /* SPM_BK_WAKE_EVENT */
+ uint32_t r12_ext; /* SPM_WAKEUP_EXT_STA */
+ uint32_t raw_sta; /* SPM_WAKEUP_STA */
+ uint32_t raw_ext_sta; /* SPM_WAKEUP_EXT_STA */
+ uint32_t md32pcm_wakeup_sta; /* MD32CPM_WAKEUP_STA */
+ uint32_t md32pcm_event_sta; /* MD32PCM_EVENT_STA */
+ uint32_t wake_misc; /* SPM_BK_WAKE_MISC */
+ uint32_t timer_out; /* SPM_BK_PCM_TIMER */
+ uint32_t r13; /* PCM_REG13_DATA */
+ uint32_t idle_sta; /* SUBSYS_IDLE_STA */
+ uint32_t req_sta0; /* SRC_REQ_STA_0 */
+ uint32_t req_sta1; /* SRC_REQ_STA_1 */
+ uint32_t req_sta2; /* SRC_REQ_STA_2 */
+ uint32_t req_sta3; /* SRC_REQ_STA_3 */
+ uint32_t req_sta4; /* SRC_REQ_STA_4 */
+ uint32_t cg_check_sta; /* SPM_CG_CHECK_STA */
+ uint32_t debug_flag; /* PCM_WDT_LATCH_SPARE_0 */
+ uint32_t debug_flag1; /* PCM_WDT_LATCH_SPARE_1 */
+ uint32_t b_sw_flag0; /* SPM_SW_RSV_7 */
+ uint32_t b_sw_flag1; /* SPM_SW_RSV_8 */
+ uint32_t isr; /* SPM_IRQ_STA */
+ uint32_t sw_flag0; /* SPM_SW_FLAG_0 */
+ uint32_t sw_flag1; /* SPM_SW_FLAG_1 */
+ uint32_t clk_settle; /* SPM_CLK_SETTLE */
+ uint32_t src_req; /* SPM_SRC_REQ */
+ uint32_t log_index;
+ uint32_t abort;
+ uint32_t rt_req_sta0; /* SPM_SW_RSV_2 */
+ uint32_t rt_req_sta1; /* SPM_SW_RSV_3 */
+ uint32_t rt_req_sta2; /* SPM_SW_RSV_4 */
+ uint32_t rt_req_sta3; /* SPM_SW_RSV_5 */
+ uint32_t rt_req_sta4; /* SPM_SW_RSV_6 */
+ uint32_t mcupm_req_sta;
+};
+
+struct spm_lp_scen {
+ struct pcm_desc *pcmdesc;
+ struct pwr_ctrl *pwrctrl;
+};
+
+extern struct spm_lp_scen __spm_vcorefs;
+extern void __spm_set_cpu_status(unsigned int cpu);
+extern void __spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc);
+extern void __spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc);
+extern void __spm_init_pcm_register(void);
+extern void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
+ unsigned int resource_usage);
+extern void __spm_set_power_control(const struct pwr_ctrl *pwrctrl);
+extern void __spm_disable_pcm_timer(void);
+extern void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl);
+extern void __spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl);
+extern void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl);
+extern void __spm_send_cpu_wakeup_event(void);
+extern void __spm_get_wakeup_status(struct wake_status *wakesta,
+ unsigned int ext_status);
+extern void __spm_clean_after_wakeup(void);
+extern wake_reason_t
+__spm_output_wake_reason(int state_id, const struct wake_status *wakesta);
+extern void
+__spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl,
+ const struct pwr_ctrl *src_pwr_ctrl);
+extern void __spm_set_pcm_wdt(int en);
+extern uint32_t _spm_get_wake_period(int pwake_time, wake_reason_t last_wr);
+extern void __spm_set_fw_resume_option(struct pwr_ctrl *pwrctrl);
+extern void __spm_ext_int_wakeup_req_clr(void);
+extern void __spm_xo_soc_bblpm(int en);
+
+static inline void set_pwrctrl_pcm_flags(struct pwr_ctrl *pwrctrl,
+ uint32_t flags)
+{
+ if (pwrctrl->pcm_flags_cust == 0U) {
+ pwrctrl->pcm_flags = flags;
+ } else {
+ pwrctrl->pcm_flags = pwrctrl->pcm_flags_cust;
+ }
+}
+
+static inline void set_pwrctrl_pcm_flags1(struct pwr_ctrl *pwrctrl,
+ uint32_t flags)
+{
+ if (pwrctrl->pcm_flags1_cust == 0U) {
+ pwrctrl->pcm_flags1 = flags;
+ } else {
+ pwrctrl->pcm_flags1 = pwrctrl->pcm_flags1_cust;
+ }
+}
+
+extern void __spm_hw_s1_state_monitor(int en, unsigned int *status);
+
+static inline void spm_hw_s1_state_monitor_resume(void)
+{
+ __spm_hw_s1_state_monitor(1, NULL);
+}
+
+static inline void spm_hw_s1_state_monitor_pause(unsigned int *status)
+{
+ __spm_hw_s1_state_monitor(0, status);
+}
+#endif /* MT_SPM_INTERNAL_H */
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_pmic_wrap.c b/plat/mediatek/mt8192/drivers/spm/mt_spm_pmic_wrap.c
new file mode 100644
index 0000000..4e5f6a0
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_pmic_wrap.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include <mt_spm.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_pmic_wrap.h>
+#include <mt_spm_reg.h>
+#include <plat_pm.h>
+#include <platform_def.h>
+
+/* PMIC_WRAP MT6359 */
+#define VCORE_BASE_UV 40000
+#define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625)
+#define PMIC_VAL_TO_VOLT(pmic) (((pmic) * 625) + VCORE_BASE_UV)
+
+#define NR_PMIC_WRAP_CMD (NR_IDX_ALL)
+#define SPM_DATA_SHIFT 16
+
+#define BUCK_VGPU11_ELR0 0x15B4
+#define TOP_SPI_CON0 0x0456
+#define BUCK_TOP_CON1 0x1443
+#define TOP_CON 0x0013
+#define TOP_DIG_WPK 0x03a9
+#define TOP_CON_LOCK 0x03a8
+#define TOP_CLK_CON0 0x0134
+
+struct pmic_wrap_cmd {
+ unsigned long cmd_addr;
+ unsigned long cmd_wdata;
+};
+
+struct pmic_wrap_setting {
+ enum pmic_wrap_phase_id phase;
+ struct pmic_wrap_cmd addr[NR_PMIC_WRAP_CMD];
+ struct {
+ struct {
+ unsigned long cmd_addr;
+ unsigned long cmd_wdata;
+ } _[NR_PMIC_WRAP_CMD];
+ const int nr_idx;
+ } set[NR_PMIC_WRAP_PHASE];
+};
+
+static struct pmic_wrap_setting pw = {
+ .phase = NR_PMIC_WRAP_PHASE, /* invalid setting for init */
+ .addr = { {0UL, 0UL} },
+ .set[PMIC_WRAP_PHASE_ALLINONE] = {
+ ._[CMD_0] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(72500),},
+ ._[CMD_1] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(65000),},
+ ._[CMD_2] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(60000),},
+ ._[CMD_3] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(57500),},
+ ._[CMD_4] = {TOP_SPI_CON0, 0x1,},
+ ._[CMD_5] = {TOP_SPI_CON0, 0x0,},
+ ._[CMD_6] = {BUCK_TOP_CON1, 0x0,},
+ ._[CMD_7] = {BUCK_TOP_CON1, 0xf,},
+ ._[CMD_8] = {TOP_CON, 0x3,},
+ ._[CMD_9] = {TOP_CON, 0x0,},
+ ._[CMD_10] = {TOP_DIG_WPK, 0x63,},
+ ._[CMD_11] = {TOP_CON_LOCK, 0x15,},
+ ._[CMD_12] = {TOP_DIG_WPK, 0x0,},
+ ._[CMD_13] = {TOP_CON_LOCK, 0x0,},
+ ._[CMD_14] = {TOP_CLK_CON0, 0x40,},
+ ._[CMD_15] = {TOP_CLK_CON0, 0x0,},
+ .nr_idx = NR_IDX_ALL,
+ },
+};
+
+void _mt_spm_pmic_table_init(void)
+{
+ struct pmic_wrap_cmd pwrap_cmd_default[NR_PMIC_WRAP_CMD] = {
+ {(uint32_t)SPM_DVFS_CMD0, (uint32_t)SPM_DVFS_CMD0,},
+ {(uint32_t)SPM_DVFS_CMD1, (uint32_t)SPM_DVFS_CMD1,},
+ {(uint32_t)SPM_DVFS_CMD2, (uint32_t)SPM_DVFS_CMD2,},
+ {(uint32_t)SPM_DVFS_CMD3, (uint32_t)SPM_DVFS_CMD3,},
+ {(uint32_t)SPM_DVFS_CMD4, (uint32_t)SPM_DVFS_CMD4,},
+ {(uint32_t)SPM_DVFS_CMD5, (uint32_t)SPM_DVFS_CMD5,},
+ {(uint32_t)SPM_DVFS_CMD6, (uint32_t)SPM_DVFS_CMD6,},
+ {(uint32_t)SPM_DVFS_CMD7, (uint32_t)SPM_DVFS_CMD7,},
+ {(uint32_t)SPM_DVFS_CMD8, (uint32_t)SPM_DVFS_CMD8,},
+ {(uint32_t)SPM_DVFS_CMD9, (uint32_t)SPM_DVFS_CMD9,},
+ {(uint32_t)SPM_DVFS_CMD10, (uint32_t)SPM_DVFS_CMD10,},
+ {(uint32_t)SPM_DVFS_CMD11, (uint32_t)SPM_DVFS_CMD11,},
+ {(uint32_t)SPM_DVFS_CMD12, (uint32_t)SPM_DVFS_CMD12,},
+ {(uint32_t)SPM_DVFS_CMD13, (uint32_t)SPM_DVFS_CMD13,},
+ {(uint32_t)SPM_DVFS_CMD14, (uint32_t)SPM_DVFS_CMD14,},
+ {(uint32_t)SPM_DVFS_CMD15, (uint32_t)SPM_DVFS_CMD15,},
+ };
+
+ memcpy(pw.addr, pwrap_cmd_default, sizeof(pwrap_cmd_default));
+}
+
+void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase)
+{
+ uint32_t idx, addr, data;
+
+ if (phase >= NR_PMIC_WRAP_PHASE) {
+ return;
+ }
+
+ if (pw.phase == phase) {
+ return;
+ }
+
+ if (pw.addr[0].cmd_addr == 0UL) {
+ _mt_spm_pmic_table_init();
+ }
+
+ pw.phase = phase;
+ mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
+
+ for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) {
+ addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
+ data = pw.set[phase]._[idx].cmd_wdata;
+ mmio_write_32(pw.addr[idx].cmd_addr, addr | data);
+ }
+}
+
+void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx,
+ uint32_t cmd_wdata)
+{
+ uint32_t addr;
+
+ if (phase >= NR_PMIC_WRAP_PHASE) {
+ return;
+ }
+
+ if (idx >= pw.set[phase].nr_idx) {
+ return;
+ }
+
+ pw.set[phase]._[idx].cmd_wdata = cmd_wdata;
+ mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
+
+ if (pw.phase == phase) {
+ addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
+ mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata);
+ }
+}
+
+uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, uint32_t idx)
+{
+ if (phase >= NR_PMIC_WRAP_PHASE) {
+ return 0UL;
+ }
+
+ if (idx >= pw.set[phase].nr_idx) {
+ return 0UL;
+ }
+
+ return pw.set[phase]._[idx].cmd_wdata;
+}
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_pmic_wrap.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_pmic_wrap.h
new file mode 100644
index 0000000..6e20916
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_pmic_wrap.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/****************************************************************
+ * Auto generated by DE, please DO NOT modify this file directly.
+ *****************************************************************/
+#ifndef MT_SPM_PMIC_WRAP_H
+#define MT_SPM_PMIC_WRAP_H
+
+enum pmic_wrap_phase_id {
+ PMIC_WRAP_PHASE_ALLINONE,
+ NR_PMIC_WRAP_PHASE,
+};
+
+/* IDX mapping, PMIC_WRAP_PHASE_ALLINONE */
+enum {
+ CMD_0, /* 0x0 */
+ CMD_1, /* 0x1 */
+ CMD_2, /* 0x2 */
+ CMD_3, /* 0x3 */
+ CMD_4, /* 0x4 */
+ CMD_5, /* 0x5 */
+ CMD_6, /* 0x6 */
+ CMD_7, /* 0x7 */
+ CMD_8, /* 0x8 */
+ CMD_9, /* 0x9 */
+ CMD_10, /* 0xA */
+ CMD_11, /* 0xB */
+ CMD_12, /* 0xC */
+ CMD_13, /* 0xD */
+ CMD_14, /* 0xE */
+ CMD_15, /* 0xF */
+ NR_IDX_ALL,
+};
+
+/* APIs */
+extern void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase);
+extern void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase,
+ uint32_t idx, uint32_t cmd_wdata);
+extern uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase,
+ uint32_t idx);
+#endif /* MT_SPM_PMIC_WRAP_H */
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_reg.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_reg.h
new file mode 100644
index 0000000..fba011d
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_reg.h
@@ -0,0 +1,2919 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/****************************************************************
+ * Auto generated by DE, please DO NOT modify this file directly.
+ *****************************************************************/
+#ifndef MT_SPM_REG
+#define MT_SPM_REG
+
+#include "pcm_def.h"
+#include <platform_def.h>
+#include "sleep_def.h"
+
+/**************************************
+ * Define and Declare
+ **************************************/
+#define POWERON_CONFIG_EN (SPM_BASE + 0x000)
+#define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004)
+#define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008)
+#define SPM_CLK_CON (SPM_BASE + 0x00C)
+#define SPM_CLK_SETTLE (SPM_BASE + 0x010)
+#define SPM_AP_STANDBY_CON (SPM_BASE + 0x014)
+#define PCM_CON0 (SPM_BASE + 0x018)
+#define PCM_CON1 (SPM_BASE + 0x01C)
+#define SPM_POWER_ON_VAL2 (SPM_BASE + 0x020)
+#define SPM_POWER_ON_VAL3 (SPM_BASE + 0x024)
+#define PCM_REG_DATA_INI (SPM_BASE + 0x028)
+#define PCM_PWR_IO_EN (SPM_BASE + 0x02C)
+#define PCM_TIMER_VAL (SPM_BASE + 0x030)
+#define PCM_WDT_VAL (SPM_BASE + 0x034)
+#define SPM_SRC6_MASK (SPM_BASE + 0x038)
+#define SPM_SW_RST_CON (SPM_BASE + 0x040)
+#define SPM_SW_RST_CON_SET (SPM_BASE + 0x044)
+#define SPM_SW_RST_CON_CLR (SPM_BASE + 0x048)
+#define VS1_PSR_MASK_B (SPM_BASE + 0x04C)
+#define VS2_PSR_MASK_B (SPM_BASE + 0x050)
+#define MD32_CLK_CON (SPM_BASE + 0x084)
+#define SPM_SRAM_RSV_CON (SPM_BASE + 0x088)
+#define SPM_SWINT (SPM_BASE + 0x08C)
+#define SPM_SWINT_SET (SPM_BASE + 0x090)
+#define SPM_SWINT_CLR (SPM_BASE + 0x094)
+#define SPM_SCP_MAILBOX (SPM_BASE + 0x098)
+#define SCP_SPM_MAILBOX (SPM_BASE + 0x09C)
+#define SPM_TWAM_CON (SPM_BASE + 0x0A0)
+#define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x0A4)
+#define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x0A8)
+#define SPM_SCP_IRQ (SPM_BASE + 0x0AC)
+#define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x0B0)
+#define SPM_IRQ_MASK (SPM_BASE + 0x0B4)
+#define SPM_SRC_REQ (SPM_BASE + 0x0B8)
+#define SPM_SRC_MASK (SPM_BASE + 0x0BC)
+#define SPM_SRC2_MASK (SPM_BASE + 0x0C0)
+#define SPM_SRC3_MASK (SPM_BASE + 0x0C4)
+#define SPM_SRC4_MASK (SPM_BASE + 0x0C8)
+#define SPM_SRC5_MASK (SPM_BASE + 0x0CC)
+#define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x0D0)
+#define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x0D4)
+#define SPM_TWAM_EVENT_CLEAR (SPM_BASE + 0x0D8)
+#define SCP_CLK_CON (SPM_BASE + 0x0DC)
+#define PCM_DEBUG_CON (SPM_BASE + 0x0E0)
+#define AHB_BUS_CON (SPM_BASE + 0x0E4)
+#define DDR_EN_DBC_CON0 (SPM_BASE + 0x0E8)
+#define DDR_EN_DBC_CON1 (SPM_BASE + 0x0EC)
+#define SPM_RESOURCE_ACK_CON0 (SPM_BASE + 0x0F0)
+#define SPM_RESOURCE_ACK_CON1 (SPM_BASE + 0x0F4)
+#define SPM_RESOURCE_ACK_CON2 (SPM_BASE + 0x0F8)
+#define SPM_RESOURCE_ACK_CON3 (SPM_BASE + 0x0FC)
+#define PCM_REG0_DATA (SPM_BASE + 0x100)
+#define PCM_REG2_DATA (SPM_BASE + 0x104)
+#define PCM_REG6_DATA (SPM_BASE + 0x108)
+#define PCM_REG7_DATA (SPM_BASE + 0x10C)
+#define PCM_REG13_DATA (SPM_BASE + 0x110)
+#define SRC_REQ_STA_0 (SPM_BASE + 0x114)
+#define SRC_REQ_STA_1 (SPM_BASE + 0x118)
+#define SRC_REQ_STA_2 (SPM_BASE + 0x11C)
+#define PCM_TIMER_OUT (SPM_BASE + 0x120)
+#define PCM_WDT_OUT (SPM_BASE + 0x124)
+#define SPM_IRQ_STA (SPM_BASE + 0x128)
+#define SRC_REQ_STA_4 (SPM_BASE + 0x12C)
+#define MD32PCM_WAKEUP_STA (SPM_BASE + 0x130)
+#define MD32PCM_EVENT_STA (SPM_BASE + 0x134)
+#define SPM_WAKEUP_STA (SPM_BASE + 0x138)
+#define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x13C)
+#define SPM_WAKEUP_MISC (SPM_BASE + 0x140)
+#define MM_DVFS_HALT (SPM_BASE + 0x144)
+#define BUS_PROTECT_RDY (SPM_BASE + 0x150)
+#define BUS_PROTECT1_RDY (SPM_BASE + 0x154)
+#define BUS_PROTECT2_RDY (SPM_BASE + 0x158)
+#define BUS_PROTECT3_RDY (SPM_BASE + 0x15C)
+#define SUBSYS_IDLE_STA (SPM_BASE + 0x160)
+#define PCM_STA (SPM_BASE + 0x164)
+#define SRC_REQ_STA_3 (SPM_BASE + 0x168)
+#define PWR_STATUS (SPM_BASE + 0x16C)
+#define PWR_STATUS_2ND (SPM_BASE + 0x170)
+#define CPU_PWR_STATUS (SPM_BASE + 0x174)
+#define OTHER_PWR_STATUS (SPM_BASE + 0x178)
+#define SPM_VTCXO_EVENT_COUNT_STA (SPM_BASE + 0x17C)
+#define SPM_INFRA_EVENT_COUNT_STA (SPM_BASE + 0x180)
+#define SPM_VRF18_EVENT_COUNT_STA (SPM_BASE + 0x184)
+#define SPM_APSRC_EVENT_COUNT_STA (SPM_BASE + 0x188)
+#define SPM_DDREN_EVENT_COUNT_STA (SPM_BASE + 0x18C)
+#define MD32PCM_STA (SPM_BASE + 0x190)
+#define MD32PCM_PC (SPM_BASE + 0x194)
+#define DVFSRC_EVENT_STA (SPM_BASE + 0x1A4)
+#define BUS_PROTECT4_RDY (SPM_BASE + 0x1A8)
+#define BUS_PROTECT5_RDY (SPM_BASE + 0x1AC)
+#define BUS_PROTECT6_RDY (SPM_BASE + 0x1B0)
+#define BUS_PROTECT7_RDY (SPM_BASE + 0x1B4)
+#define BUS_PROTECT8_RDY (SPM_BASE + 0x1B8)
+#define SPM_TWAM_LAST_STA0 (SPM_BASE + 0x1D0)
+#define SPM_TWAM_LAST_STA1 (SPM_BASE + 0x1D4)
+#define SPM_TWAM_LAST_STA2 (SPM_BASE + 0x1D8)
+#define SPM_TWAM_LAST_STA3 (SPM_BASE + 0x1DC)
+#define SPM_TWAM_CURR_STA0 (SPM_BASE + 0x1E0)
+#define SPM_TWAM_CURR_STA1 (SPM_BASE + 0x1E4)
+#define SPM_TWAM_CURR_STA2 (SPM_BASE + 0x1E8)
+#define SPM_TWAM_CURR_STA3 (SPM_BASE + 0x1EC)
+#define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x1F0)
+#define SPM_CG_CHECK_STA (SPM_BASE + 0x1F4)
+#define SPM_DVFS_STA (SPM_BASE + 0x1F8)
+#define SPM_DVFS_OPP_STA (SPM_BASE + 0x1FC)
+#define SPM_MCUSYS_PWR_CON (SPM_BASE + 0x200)
+#define SPM_CPUTOP_PWR_CON (SPM_BASE + 0x204)
+#define SPM_CPU0_PWR_CON (SPM_BASE + 0x208)
+#define SPM_CPU1_PWR_CON (SPM_BASE + 0x20C)
+#define SPM_CPU2_PWR_CON (SPM_BASE + 0x210)
+#define SPM_CPU3_PWR_CON (SPM_BASE + 0x214)
+#define SPM_CPU4_PWR_CON (SPM_BASE + 0x218)
+#define SPM_CPU5_PWR_CON (SPM_BASE + 0x21C)
+#define SPM_CPU6_PWR_CON (SPM_BASE + 0x220)
+#define SPM_CPU7_PWR_CON (SPM_BASE + 0x224)
+#define ARMPLL_CLK_CON (SPM_BASE + 0x22C)
+#define MCUSYS_IDLE_STA (SPM_BASE + 0x230)
+#define GIC_WAKEUP_STA (SPM_BASE + 0x234)
+#define CPU_SPARE_CON (SPM_BASE + 0x238)
+#define CPU_SPARE_CON_SET (SPM_BASE + 0x23C)
+#define CPU_SPARE_CON_CLR (SPM_BASE + 0x240)
+#define ARMPLL_CLK_SEL (SPM_BASE + 0x244)
+#define EXT_INT_WAKEUP_REQ (SPM_BASE + 0x248)
+#define EXT_INT_WAKEUP_REQ_SET (SPM_BASE + 0x24C)
+#define EXT_INT_WAKEUP_REQ_CLR (SPM_BASE + 0x250)
+#define MP0_CPU0_IRQ_MASK (SPM_BASE + 0x260)
+#define MP0_CPU1_IRQ_MASK (SPM_BASE + 0x264)
+#define MP0_CPU2_IRQ_MASK (SPM_BASE + 0x268)
+#define MP0_CPU3_IRQ_MASK (SPM_BASE + 0x26C)
+#define MP1_CPU0_IRQ_MASK (SPM_BASE + 0x270)
+#define MP1_CPU1_IRQ_MASK (SPM_BASE + 0x274)
+#define MP1_CPU2_IRQ_MASK (SPM_BASE + 0x278)
+#define MP1_CPU3_IRQ_MASK (SPM_BASE + 0x27C)
+#define MP0_CPU0_WFI_EN (SPM_BASE + 0x280)
+#define MP0_CPU1_WFI_EN (SPM_BASE + 0x284)
+#define MP0_CPU2_WFI_EN (SPM_BASE + 0x288)
+#define MP0_CPU3_WFI_EN (SPM_BASE + 0x28C)
+#define MP0_CPU4_WFI_EN (SPM_BASE + 0x290)
+#define MP0_CPU5_WFI_EN (SPM_BASE + 0x294)
+#define MP0_CPU6_WFI_EN (SPM_BASE + 0x298)
+#define MP0_CPU7_WFI_EN (SPM_BASE + 0x29C)
+#define ROOT_CPUTOP_ADDR (SPM_BASE + 0x2A0)
+#define ROOT_CORE_ADDR (SPM_BASE + 0x2A4)
+#define SPM2SW_MAILBOX_0 (SPM_BASE + 0x2D0)
+#define SPM2SW_MAILBOX_1 (SPM_BASE + 0x2D4)
+#define SPM2SW_MAILBOX_2 (SPM_BASE + 0x2D8)
+#define SPM2SW_MAILBOX_3 (SPM_BASE + 0x2DC)
+#define SW2SPM_INT (SPM_BASE + 0x2E0)
+#define SW2SPM_INT_SET (SPM_BASE + 0x2E4)
+#define SW2SPM_INT_CLR (SPM_BASE + 0x2E8)
+#define SW2SPM_MAILBOX_0 (SPM_BASE + 0x2EC)
+#define SW2SPM_MAILBOX_1 (SPM_BASE + 0x2F0)
+#define SW2SPM_MAILBOX_2 (SPM_BASE + 0x2F4)
+#define SW2SPM_MAILBOX_3 (SPM_BASE + 0x2F8)
+#define SW2SPM_CFG (SPM_BASE + 0x2FC)
+#define MD1_PWR_CON (SPM_BASE + 0x300)
+#define CONN_PWR_CON (SPM_BASE + 0x304)
+#define MFG0_PWR_CON (SPM_BASE + 0x308)
+#define MFG1_PWR_CON (SPM_BASE + 0x30C)
+#define MFG2_PWR_CON (SPM_BASE + 0x310)
+#define MFG3_PWR_CON (SPM_BASE + 0x314)
+#define MFG4_PWR_CON (SPM_BASE + 0x318)
+#define MFG5_PWR_CON (SPM_BASE + 0x31C)
+#define MFG6_PWR_CON (SPM_BASE + 0x320)
+#define IFR_PWR_CON (SPM_BASE + 0x324)
+#define IFR_SUB_PWR_CON (SPM_BASE + 0x328)
+#define DPY_PWR_CON (SPM_BASE + 0x32C)
+#define ISP_PWR_CON (SPM_BASE + 0x330)
+#define ISP2_PWR_CON (SPM_BASE + 0x334)
+#define IPE_PWR_CON (SPM_BASE + 0x338)
+#define VDE_PWR_CON (SPM_BASE + 0x33C)
+#define VDE2_PWR_CON (SPM_BASE + 0x340)
+#define VEN_PWR_CON (SPM_BASE + 0x344)
+#define VEN_CORE1_PWR_CON (SPM_BASE + 0x348)
+#define MDP_PWR_CON (SPM_BASE + 0x34C)
+#define DIS_PWR_CON (SPM_BASE + 0x350)
+#define AUDIO_PWR_CON (SPM_BASE + 0x354)
+#define ADSP_PWR_CON (SPM_BASE + 0x358)
+#define CAM_PWR_CON (SPM_BASE + 0x35C)
+#define CAM_RAWA_PWR_CON (SPM_BASE + 0x360)
+#define CAM_RAWB_PWR_CON (SPM_BASE + 0x364)
+#define CAM_RAWC_PWR_CON (SPM_BASE + 0x368)
+#define SYSRAM_CON (SPM_BASE + 0x36C)
+#define SYSROM_CON (SPM_BASE + 0x370)
+#define SSPM_SRAM_CON (SPM_BASE + 0x374)
+#define SCP_SRAM_CON (SPM_BASE + 0x378)
+#define DPY_SHU_SRAM_CON (SPM_BASE + 0x37C)
+#define UFS_SRAM_CON (SPM_BASE + 0x380)
+#define DEVAPC_IFR_SRAM_CON (SPM_BASE + 0x384)
+#define DEVAPC_SUBIFR_SRAM_CON (SPM_BASE + 0x388)
+#define DEVAPC_ACP_SRAM_CON (SPM_BASE + 0x38C)
+#define USB_SRAM_CON (SPM_BASE + 0x390)
+#define DUMMY_SRAM_CON (SPM_BASE + 0x394)
+#define MD_EXT_BUCK_ISO_CON (SPM_BASE + 0x398)
+#define EXT_BUCK_ISO (SPM_BASE + 0x39C)
+#define DXCC_SRAM_CON (SPM_BASE + 0x3A0)
+#define MSDC_SRAM_CON (SPM_BASE + 0x3A4)
+#define DEBUGTOP_SRAM_CON (SPM_BASE + 0x3A8)
+#define DP_TX_PWR_CON (SPM_BASE + 0x3AC)
+#define DPMAIF_SRAM_CON (SPM_BASE + 0x3B0)
+#define DPY_SHU2_SRAM_CON (SPM_BASE + 0x3B4)
+#define DRAMC_MCU2_SRAM_CON (SPM_BASE + 0x3B8)
+#define DRAMC_MCU_SRAM_CON (SPM_BASE + 0x3BC)
+#define MCUPM_SRAM_CON (SPM_BASE + 0x3C0)
+#define DPY2_PWR_CON (SPM_BASE + 0x3C4)
+#define PERI_PWR_CON (SPM_BASE + 0x3C8)
+#define SPM_MEM_CK_SEL (SPM_BASE + 0x400)
+#define SPM_BUS_PROTECT_MASK_B (SPM_BASE + 0x404)
+#define SPM_BUS_PROTECT1_MASK_B (SPM_BASE + 0x408)
+#define SPM_BUS_PROTECT2_MASK_B (SPM_BASE + 0x40C)
+#define SPM_BUS_PROTECT3_MASK_B (SPM_BASE + 0x410)
+#define SPM_BUS_PROTECT4_MASK_B (SPM_BASE + 0x414)
+#define SPM_EMI_BW_MODE (SPM_BASE + 0x418)
+#define AP2MD_PEER_WAKEUP (SPM_BASE + 0x41C)
+#define ULPOSC_CON (SPM_BASE + 0x420)
+#define SPM2MM_CON (SPM_BASE + 0x424)
+#define SPM_BUS_PROTECT5_MASK_B (SPM_BASE + 0x428)
+#define SPM2MCUPM_CON (SPM_BASE + 0x42C)
+#define AP_MDSRC_REQ (SPM_BASE + 0x430)
+#define SPM2EMI_ENTER_ULPM (SPM_BASE + 0x434)
+#define SPM2MD_DVFS_CON (SPM_BASE + 0x438)
+#define MD2SPM_DVFS_CON (SPM_BASE + 0x43C)
+#define SPM_BUS_PROTECT6_MASK_B (SPM_BASE + 0x440)
+#define SPM_BUS_PROTECT7_MASK_B (SPM_BASE + 0x444)
+#define SPM_BUS_PROTECT8_MASK_B (SPM_BASE + 0x448)
+#define SPM_PLL_CON (SPM_BASE + 0x44C)
+#define CPU_DVFS_REQ (SPM_BASE + 0x450)
+#define SPM_DRAM_MCU_SW_CON_0 (SPM_BASE + 0x454)
+#define SPM_DRAM_MCU_SW_CON_1 (SPM_BASE + 0x458)
+#define SPM_DRAM_MCU_SW_CON_2 (SPM_BASE + 0x45C)
+#define SPM_DRAM_MCU_SW_CON_3 (SPM_BASE + 0x460)
+#define SPM_DRAM_MCU_SW_CON_4 (SPM_BASE + 0x464)
+#define SPM_DRAM_MCU_STA_0 (SPM_BASE + 0x468)
+#define SPM_DRAM_MCU_STA_1 (SPM_BASE + 0x46C)
+#define SPM_DRAM_MCU_STA_2 (SPM_BASE + 0x470)
+#define SPM_DRAM_MCU_SW_SEL_0 (SPM_BASE + 0x474)
+#define RELAY_DVFS_LEVEL (SPM_BASE + 0x478)
+#define DRAMC_DPY_CLK_SW_CON_0 (SPM_BASE + 0x480)
+#define DRAMC_DPY_CLK_SW_CON_1 (SPM_BASE + 0x484)
+#define DRAMC_DPY_CLK_SW_CON_2 (SPM_BASE + 0x488)
+#define DRAMC_DPY_CLK_SW_CON_3 (SPM_BASE + 0x48C)
+#define DRAMC_DPY_CLK_SW_SEL_0 (SPM_BASE + 0x490)
+#define DRAMC_DPY_CLK_SW_SEL_1 (SPM_BASE + 0x494)
+#define DRAMC_DPY_CLK_SW_SEL_2 (SPM_BASE + 0x498)
+#define DRAMC_DPY_CLK_SW_SEL_3 (SPM_BASE + 0x49C)
+#define DRAMC_DPY_CLK_SPM_CON (SPM_BASE + 0x4A0)
+#define SPM_DVFS_LEVEL (SPM_BASE + 0x4A4)
+#define SPM_CIRQ_CON (SPM_BASE + 0x4A8)
+#define SPM_DVFS_MISC (SPM_BASE + 0x4AC)
+#define SPM_VS1_VS2_RC_CON (SPM_BASE + 0x4B0)
+#define RG_MODULE_SW_CG_0_MASK_REQ_0 (SPM_BASE + 0x4B4)
+#define RG_MODULE_SW_CG_0_MASK_REQ_1 (SPM_BASE + 0x4B8)
+#define RG_MODULE_SW_CG_0_MASK_REQ_2 (SPM_BASE + 0x4BC)
+#define RG_MODULE_SW_CG_1_MASK_REQ_0 (SPM_BASE + 0x4C0)
+#define RG_MODULE_SW_CG_1_MASK_REQ_1 (SPM_BASE + 0x4C4)
+#define RG_MODULE_SW_CG_1_MASK_REQ_2 (SPM_BASE + 0x4C8)
+#define RG_MODULE_SW_CG_2_MASK_REQ_0 (SPM_BASE + 0x4CC)
+#define RG_MODULE_SW_CG_2_MASK_REQ_1 (SPM_BASE + 0x4D0)
+#define RG_MODULE_SW_CG_2_MASK_REQ_2 (SPM_BASE + 0x4D4)
+#define RG_MODULE_SW_CG_3_MASK_REQ_0 (SPM_BASE + 0x4D8)
+#define RG_MODULE_SW_CG_3_MASK_REQ_1 (SPM_BASE + 0x4DC)
+#define RG_MODULE_SW_CG_3_MASK_REQ_2 (SPM_BASE + 0x4E0)
+#define PWR_STATUS_MASK_REQ_0 (SPM_BASE + 0x4E4)
+#define PWR_STATUS_MASK_REQ_1 (SPM_BASE + 0x4E8)
+#define PWR_STATUS_MASK_REQ_2 (SPM_BASE + 0x4EC)
+#define SPM_CG_CHECK_CON (SPM_BASE + 0x4F0)
+#define SPM_SRC_RDY_STA (SPM_BASE + 0x4F4)
+#define SPM_DVS_DFS_LEVEL (SPM_BASE + 0x4F8)
+#define SPM_FORCE_DVFS (SPM_BASE + 0x4FC)
+#define SRCLKEN_RC_CFG (SPM_BASE + 0x500)
+#define RC_CENTRAL_CFG1 (SPM_BASE + 0x504)
+#define RC_CENTRAL_CFG2 (SPM_BASE + 0x508)
+#define RC_CMD_ARB_CFG (SPM_BASE + 0x50C)
+#define RC_PMIC_RCEN_ADDR (SPM_BASE + 0x510)
+#define RC_PMIC_RCEN_SET_CLR_ADDR (SPM_BASE + 0x514)
+#define RC_DCXO_FPM_CFG (SPM_BASE + 0x518)
+#define RC_CENTRAL_CFG3 (SPM_BASE + 0x51C)
+#define RC_M00_SRCLKEN_CFG (SPM_BASE + 0x520)
+#define RC_M01_SRCLKEN_CFG (SPM_BASE + 0x524)
+#define RC_M02_SRCLKEN_CFG (SPM_BASE + 0x528)
+#define RC_M03_SRCLKEN_CFG (SPM_BASE + 0x52C)
+#define RC_M04_SRCLKEN_CFG (SPM_BASE + 0x530)
+#define RC_M05_SRCLKEN_CFG (SPM_BASE + 0x534)
+#define RC_M06_SRCLKEN_CFG (SPM_BASE + 0x538)
+#define RC_M07_SRCLKEN_CFG (SPM_BASE + 0x53C)
+#define RC_M08_SRCLKEN_CFG (SPM_BASE + 0x540)
+#define RC_M09_SRCLKEN_CFG (SPM_BASE + 0x544)
+#define RC_M10_SRCLKEN_CFG (SPM_BASE + 0x548)
+#define RC_M11_SRCLKEN_CFG (SPM_BASE + 0x54C)
+#define RC_M12_SRCLKEN_CFG (SPM_BASE + 0x550)
+#define RC_SRCLKEN_SW_CON_CFG (SPM_BASE + 0x554)
+#define RC_CENTRAL_CFG4 (SPM_BASE + 0x558)
+#define RC_PROTOCOL_CHK_CFG (SPM_BASE + 0x560)
+#define RC_DEBUG_CFG (SPM_BASE + 0x564)
+#define RC_MISC_0 (SPM_BASE + 0x5B4)
+#define RC_SPM_CTRL (SPM_BASE + 0x5B8)
+#define SUBSYS_INTF_CFG (SPM_BASE + 0x5BC)
+#define PCM_WDT_LATCH_25 (SPM_BASE + 0x5C0)
+#define PCM_WDT_LATCH_26 (SPM_BASE + 0x5C4)
+#define PCM_WDT_LATCH_27 (SPM_BASE + 0x5C8)
+#define PCM_WDT_LATCH_28 (SPM_BASE + 0x5CC)
+#define PCM_WDT_LATCH_29 (SPM_BASE + 0x5D0)
+#define PCM_WDT_LATCH_30 (SPM_BASE + 0x5D4)
+#define PCM_WDT_LATCH_31 (SPM_BASE + 0x5D8)
+#define PCM_WDT_LATCH_32 (SPM_BASE + 0x5DC)
+#define PCM_WDT_LATCH_33 (SPM_BASE + 0x5E0)
+#define PCM_WDT_LATCH_34 (SPM_BASE + 0x5E4)
+#define PCM_WDT_LATCH_35 (SPM_BASE + 0x5EC)
+#define PCM_WDT_LATCH_36 (SPM_BASE + 0x5F0)
+#define PCM_WDT_LATCH_37 (SPM_BASE + 0x5F4)
+#define PCM_WDT_LATCH_38 (SPM_BASE + 0x5F8)
+#define PCM_WDT_LATCH_39 (SPM_BASE + 0x5FC)
+#define SPM_SW_FLAG_0 (SPM_BASE + 0x600)
+#define SPM_SW_DEBUG_0 (SPM_BASE + 0x604)
+#define SPM_SW_FLAG_1 (SPM_BASE + 0x608)
+#define SPM_SW_DEBUG_1 (SPM_BASE + 0x60C)
+#define SPM_SW_RSV_0 (SPM_BASE + 0x610)
+#define SPM_SW_RSV_1 (SPM_BASE + 0x614)
+#define SPM_SW_RSV_2 (SPM_BASE + 0x618)
+#define SPM_SW_RSV_3 (SPM_BASE + 0x61C)
+#define SPM_SW_RSV_4 (SPM_BASE + 0x620)
+#define SPM_SW_RSV_5 (SPM_BASE + 0x624)
+#define SPM_SW_RSV_6 (SPM_BASE + 0x628)
+#define SPM_SW_RSV_7 (SPM_BASE + 0x62C)
+#define SPM_SW_RSV_8 (SPM_BASE + 0x630)
+#define SPM_BK_WAKE_EVENT (SPM_BASE + 0x634)
+#define SPM_BK_VTCXO_DUR (SPM_BASE + 0x638)
+#define SPM_BK_WAKE_MISC (SPM_BASE + 0x63C)
+#define SPM_BK_PCM_TIMER (SPM_BASE + 0x640)
+#define SPM_RSV_CON_0 (SPM_BASE + 0x650)
+#define SPM_RSV_CON_1 (SPM_BASE + 0x654)
+#define SPM_RSV_STA_0 (SPM_BASE + 0x658)
+#define SPM_RSV_STA_1 (SPM_BASE + 0x65C)
+#define SPM_SPARE_CON (SPM_BASE + 0x660)
+#define SPM_SPARE_CON_SET (SPM_BASE + 0x664)
+#define SPM_SPARE_CON_CLR (SPM_BASE + 0x668)
+#define SPM_CROSS_WAKE_M00_REQ (SPM_BASE + 0x66C)
+#define SPM_CROSS_WAKE_M01_REQ (SPM_BASE + 0x670)
+#define SPM_CROSS_WAKE_M02_REQ (SPM_BASE + 0x674)
+#define SPM_CROSS_WAKE_M03_REQ (SPM_BASE + 0x678)
+#define SCP_VCORE_LEVEL (SPM_BASE + 0x67C)
+#define SC_MM_CK_SEL_CON (SPM_BASE + 0x680)
+#define SPARE_ACK_MASK (SPM_BASE + 0x684)
+#define SPM_CROSS_WAKE_M04_REQ (SPM_BASE + 0x688)
+#define SPM_DV_CON_0 (SPM_BASE + 0x68C)
+#define SPM_DV_CON_1 (SPM_BASE + 0x690)
+#define SPM_DV_STA (SPM_BASE + 0x694)
+#define CONN_XOWCN_DEBUG_EN (SPM_BASE + 0x698)
+#define SPM_SEMA_M0 (SPM_BASE + 0x69C)
+#define SPM_SEMA_M1 (SPM_BASE + 0x6A0)
+#define SPM_SEMA_M2 (SPM_BASE + 0x6A4)
+#define SPM_SEMA_M3 (SPM_BASE + 0x6A8)
+#define SPM_SEMA_M4 (SPM_BASE + 0x6AC)
+#define SPM_SEMA_M5 (SPM_BASE + 0x6B0)
+#define SPM_SEMA_M6 (SPM_BASE + 0x6B4)
+#define SPM_SEMA_M7 (SPM_BASE + 0x6B8)
+#define SPM2ADSP_MAILBOX (SPM_BASE + 0x6BC)
+#define ADSP2SPM_MAILBOX (SPM_BASE + 0x6C0)
+#define SPM_ADSP_IRQ (SPM_BASE + 0x6C4)
+#define SPM_MD32_IRQ (SPM_BASE + 0x6C8)
+#define SPM2PMCU_MAILBOX_0 (SPM_BASE + 0x6CC)
+#define SPM2PMCU_MAILBOX_1 (SPM_BASE + 0x6D0)
+#define SPM2PMCU_MAILBOX_2 (SPM_BASE + 0x6D4)
+#define SPM2PMCU_MAILBOX_3 (SPM_BASE + 0x6D8)
+#define PMCU2SPM_MAILBOX_0 (SPM_BASE + 0x6DC)
+#define PMCU2SPM_MAILBOX_1 (SPM_BASE + 0x6E0)
+#define PMCU2SPM_MAILBOX_2 (SPM_BASE + 0x6E4)
+#define PMCU2SPM_MAILBOX_3 (SPM_BASE + 0x6E8)
+#define UFS_PSRI_SW (SPM_BASE + 0x6EC)
+#define UFS_PSRI_SW_SET (SPM_BASE + 0x6F0)
+#define UFS_PSRI_SW_CLR (SPM_BASE + 0x6F4)
+#define SPM_AP_SEMA (SPM_BASE + 0x6F8)
+#define SPM_SPM_SEMA (SPM_BASE + 0x6FC)
+#define SPM_DVFS_CON (SPM_BASE + 0x700)
+#define SPM_DVFS_CON_STA (SPM_BASE + 0x704)
+#define SPM_PMIC_SPMI_CON (SPM_BASE + 0x708)
+#define SPM_DVFS_CMD0 (SPM_BASE + 0x710)
+#define SPM_DVFS_CMD1 (SPM_BASE + 0x714)
+#define SPM_DVFS_CMD2 (SPM_BASE + 0x718)
+#define SPM_DVFS_CMD3 (SPM_BASE + 0x71C)
+#define SPM_DVFS_CMD4 (SPM_BASE + 0x720)
+#define SPM_DVFS_CMD5 (SPM_BASE + 0x724)
+#define SPM_DVFS_CMD6 (SPM_BASE + 0x728)
+#define SPM_DVFS_CMD7 (SPM_BASE + 0x72C)
+#define SPM_DVFS_CMD8 (SPM_BASE + 0x730)
+#define SPM_DVFS_CMD9 (SPM_BASE + 0x734)
+#define SPM_DVFS_CMD10 (SPM_BASE + 0x738)
+#define SPM_DVFS_CMD11 (SPM_BASE + 0x73C)
+#define SPM_DVFS_CMD12 (SPM_BASE + 0x740)
+#define SPM_DVFS_CMD13 (SPM_BASE + 0x744)
+#define SPM_DVFS_CMD14 (SPM_BASE + 0x748)
+#define SPM_DVFS_CMD15 (SPM_BASE + 0x74C)
+#define SPM_DVFS_CMD16 (SPM_BASE + 0x750)
+#define SPM_DVFS_CMD17 (SPM_BASE + 0x754)
+#define SPM_DVFS_CMD18 (SPM_BASE + 0x758)
+#define SPM_DVFS_CMD19 (SPM_BASE + 0x75C)
+#define SPM_DVFS_CMD20 (SPM_BASE + 0x760)
+#define SPM_DVFS_CMD21 (SPM_BASE + 0x764)
+#define SPM_DVFS_CMD22 (SPM_BASE + 0x768)
+#define SPM_DVFS_CMD23 (SPM_BASE + 0x76C)
+#define SYS_TIMER_VALUE_L (SPM_BASE + 0x770)
+#define SYS_TIMER_VALUE_H (SPM_BASE + 0x774)
+#define SYS_TIMER_START_L (SPM_BASE + 0x778)
+#define SYS_TIMER_START_H (SPM_BASE + 0x77C)
+#define SYS_TIMER_LATCH_L_00 (SPM_BASE + 0x780)
+#define SYS_TIMER_LATCH_H_00 (SPM_BASE + 0x784)
+#define SYS_TIMER_LATCH_L_01 (SPM_BASE + 0x788)
+#define SYS_TIMER_LATCH_H_01 (SPM_BASE + 0x78C)
+#define SYS_TIMER_LATCH_L_02 (SPM_BASE + 0x790)
+#define SYS_TIMER_LATCH_H_02 (SPM_BASE + 0x794)
+#define SYS_TIMER_LATCH_L_03 (SPM_BASE + 0x798)
+#define SYS_TIMER_LATCH_H_03 (SPM_BASE + 0x79C)
+#define SYS_TIMER_LATCH_L_04 (SPM_BASE + 0x7A0)
+#define SYS_TIMER_LATCH_H_04 (SPM_BASE + 0x7A4)
+#define SYS_TIMER_LATCH_L_05 (SPM_BASE + 0x7A8)
+#define SYS_TIMER_LATCH_H_05 (SPM_BASE + 0x7AC)
+#define SYS_TIMER_LATCH_L_06 (SPM_BASE + 0x7B0)
+#define SYS_TIMER_LATCH_H_06 (SPM_BASE + 0x7B4)
+#define SYS_TIMER_LATCH_L_07 (SPM_BASE + 0x7B8)
+#define SYS_TIMER_LATCH_H_07 (SPM_BASE + 0x7BC)
+#define SYS_TIMER_LATCH_L_08 (SPM_BASE + 0x7C0)
+#define SYS_TIMER_LATCH_H_08 (SPM_BASE + 0x7C4)
+#define SYS_TIMER_LATCH_L_09 (SPM_BASE + 0x7C8)
+#define SYS_TIMER_LATCH_H_09 (SPM_BASE + 0x7CC)
+#define SYS_TIMER_LATCH_L_10 (SPM_BASE + 0x7D0)
+#define SYS_TIMER_LATCH_H_10 (SPM_BASE + 0x7D4)
+#define SYS_TIMER_LATCH_L_11 (SPM_BASE + 0x7D8)
+#define SYS_TIMER_LATCH_H_11 (SPM_BASE + 0x7DC)
+#define SYS_TIMER_LATCH_L_12 (SPM_BASE + 0x7E0)
+#define SYS_TIMER_LATCH_H_12 (SPM_BASE + 0x7E4)
+#define SYS_TIMER_LATCH_L_13 (SPM_BASE + 0x7E8)
+#define SYS_TIMER_LATCH_H_13 (SPM_BASE + 0x7EC)
+#define SYS_TIMER_LATCH_L_14 (SPM_BASE + 0x7F0)
+#define SYS_TIMER_LATCH_H_14 (SPM_BASE + 0x7F4)
+#define SYS_TIMER_LATCH_L_15 (SPM_BASE + 0x7F8)
+#define SYS_TIMER_LATCH_H_15 (SPM_BASE + 0x7FC)
+#define PCM_WDT_LATCH_0 (SPM_BASE + 0x800)
+#define PCM_WDT_LATCH_1 (SPM_BASE + 0x804)
+#define PCM_WDT_LATCH_2 (SPM_BASE + 0x808)
+#define PCM_WDT_LATCH_3 (SPM_BASE + 0x80C)
+#define PCM_WDT_LATCH_4 (SPM_BASE + 0x810)
+#define PCM_WDT_LATCH_5 (SPM_BASE + 0x814)
+#define PCM_WDT_LATCH_6 (SPM_BASE + 0x818)
+#define PCM_WDT_LATCH_7 (SPM_BASE + 0x81C)
+#define PCM_WDT_LATCH_8 (SPM_BASE + 0x820)
+#define PCM_WDT_LATCH_9 (SPM_BASE + 0x824)
+#define PCM_WDT_LATCH_10 (SPM_BASE + 0x828)
+#define PCM_WDT_LATCH_11 (SPM_BASE + 0x82C)
+#define PCM_WDT_LATCH_12 (SPM_BASE + 0x830)
+#define PCM_WDT_LATCH_13 (SPM_BASE + 0x834)
+#define PCM_WDT_LATCH_14 (SPM_BASE + 0x838)
+#define PCM_WDT_LATCH_15 (SPM_BASE + 0x83C)
+#define PCM_WDT_LATCH_16 (SPM_BASE + 0x840)
+#define PCM_WDT_LATCH_17 (SPM_BASE + 0x844)
+#define PCM_WDT_LATCH_18 (SPM_BASE + 0x848)
+#define PCM_WDT_LATCH_SPARE_0 (SPM_BASE + 0x84C)
+#define PCM_WDT_LATCH_SPARE_1 (SPM_BASE + 0x850)
+#define PCM_WDT_LATCH_SPARE_2 (SPM_BASE + 0x854)
+#define PCM_WDT_LATCH_CONN_0 (SPM_BASE + 0x870)
+#define PCM_WDT_LATCH_CONN_1 (SPM_BASE + 0x874)
+#define PCM_WDT_LATCH_CONN_2 (SPM_BASE + 0x878)
+#define DRAMC_GATING_ERR_LATCH_CH0_0 (SPM_BASE + 0x8A0)
+#define DRAMC_GATING_ERR_LATCH_CH0_1 (SPM_BASE + 0x8A4)
+#define DRAMC_GATING_ERR_LATCH_CH0_2 (SPM_BASE + 0x8A8)
+#define DRAMC_GATING_ERR_LATCH_CH0_3 (SPM_BASE + 0x8AC)
+#define DRAMC_GATING_ERR_LATCH_CH0_4 (SPM_BASE + 0x8B0)
+#define DRAMC_GATING_ERR_LATCH_CH0_5 (SPM_BASE + 0x8B4)
+#define DRAMC_GATING_ERR_LATCH_CH0_6 (SPM_BASE + 0x8B8)
+#define DRAMC_GATING_ERR_LATCH_SPARE_0 (SPM_BASE + 0x8F4)
+#define SPM_ACK_CHK_CON_0 (SPM_BASE + 0x900)
+#define SPM_ACK_CHK_PC_0 (SPM_BASE + 0x904)
+#define SPM_ACK_CHK_SEL_0 (SPM_BASE + 0x908)
+#define SPM_ACK_CHK_TIMER_0 (SPM_BASE + 0x90C)
+#define SPM_ACK_CHK_STA_0 (SPM_BASE + 0x910)
+#define SPM_ACK_CHK_SWINT_0 (SPM_BASE + 0x914)
+#define SPM_ACK_CHK_CON_1 (SPM_BASE + 0x920)
+#define SPM_ACK_CHK_PC_1 (SPM_BASE + 0x924)
+#define SPM_ACK_CHK_SEL_1 (SPM_BASE + 0x928)
+#define SPM_ACK_CHK_TIMER_1 (SPM_BASE + 0x92C)
+#define SPM_ACK_CHK_STA_1 (SPM_BASE + 0x930)
+#define SPM_ACK_CHK_SWINT_1 (SPM_BASE + 0x934)
+#define SPM_ACK_CHK_CON_2 (SPM_BASE + 0x940)
+#define SPM_ACK_CHK_PC_2 (SPM_BASE + 0x944)
+#define SPM_ACK_CHK_SEL_2 (SPM_BASE + 0x948)
+#define SPM_ACK_CHK_TIMER_2 (SPM_BASE + 0x94C)
+#define SPM_ACK_CHK_STA_2 (SPM_BASE + 0x950)
+#define SPM_ACK_CHK_SWINT_2 (SPM_BASE + 0x954)
+#define SPM_ACK_CHK_CON_3 (SPM_BASE + 0x960)
+#define SPM_ACK_CHK_PC_3 (SPM_BASE + 0x964)
+#define SPM_ACK_CHK_SEL_3 (SPM_BASE + 0x968)
+#define SPM_ACK_CHK_TIMER_3 (SPM_BASE + 0x96C)
+#define SPM_ACK_CHK_STA_3 (SPM_BASE + 0x970)
+#define SPM_ACK_CHK_SWINT_3 (SPM_BASE + 0x974)
+#define SPM_COUNTER_0 (SPM_BASE + 0x978)
+#define SPM_COUNTER_1 (SPM_BASE + 0x97C)
+#define SPM_COUNTER_2 (SPM_BASE + 0x980)
+#define SYS_TIMER_CON (SPM_BASE + 0x98C)
+#define RC_FSM_STA_0 (SPM_BASE + 0xE00)
+#define RC_CMD_STA_0 (SPM_BASE + 0xE04)
+#define RC_CMD_STA_1 (SPM_BASE + 0xE08)
+#define RC_SPI_STA_0 (SPM_BASE + 0xE0C)
+#define RC_PI_PO_STA_0 (SPM_BASE + 0xE10)
+#define RC_M00_REQ_STA_0 (SPM_BASE + 0xE14)
+#define RC_M01_REQ_STA_0 (SPM_BASE + 0xE1C)
+#define RC_M02_REQ_STA_0 (SPM_BASE + 0xE20)
+#define RC_M03_REQ_STA_0 (SPM_BASE + 0xE24)
+#define RC_M04_REQ_STA_0 (SPM_BASE + 0xE28)
+#define RC_M05_REQ_STA_0 (SPM_BASE + 0xE2C)
+#define RC_M06_REQ_STA_0 (SPM_BASE + 0xE30)
+#define RC_M07_REQ_STA_0 (SPM_BASE + 0xE34)
+#define RC_M08_REQ_STA_0 (SPM_BASE + 0xE38)
+#define RC_M09_REQ_STA_0 (SPM_BASE + 0xE3C)
+#define RC_M10_REQ_STA_0 (SPM_BASE + 0xE40)
+#define RC_M11_REQ_STA_0 (SPM_BASE + 0xE44)
+#define RC_M12_REQ_STA_0 (SPM_BASE + 0xE48)
+#define RC_DEBUG_STA_0 (SPM_BASE + 0xE4C)
+#define RC_DEBUG_TRACE_0_LSB (SPM_BASE + 0xE50)
+#define RC_DEBUG_TRACE_0_MSB (SPM_BASE + 0xE54)
+#define RC_DEBUG_TRACE_1_LSB (SPM_BASE + 0xE5C)
+#define RC_DEBUG_TRACE_1_MSB (SPM_BASE + 0xE60)
+#define RC_DEBUG_TRACE_2_LSB (SPM_BASE + 0xE64)
+#define RC_DEBUG_TRACE_2_MSB (SPM_BASE + 0xE6C)
+#define RC_DEBUG_TRACE_3_LSB (SPM_BASE + 0xE70)
+#define RC_DEBUG_TRACE_3_MSB (SPM_BASE + 0xE74)
+#define RC_DEBUG_TRACE_4_LSB (SPM_BASE + 0xE78)
+#define RC_DEBUG_TRACE_4_MSB (SPM_BASE + 0xE7C)
+#define RC_DEBUG_TRACE_5_LSB (SPM_BASE + 0xE80)
+#define RC_DEBUG_TRACE_5_MSB (SPM_BASE + 0xE84)
+#define RC_DEBUG_TRACE_6_LSB (SPM_BASE + 0xE88)
+#define RC_DEBUG_TRACE_6_MSB (SPM_BASE + 0xE8C)
+#define RC_DEBUG_TRACE_7_LSB (SPM_BASE + 0xE90)
+#define RC_DEBUG_TRACE_7_MSB (SPM_BASE + 0xE94)
+#define RC_SYS_TIMER_LATCH_0_LSB (SPM_BASE + 0xE98)
+#define RC_SYS_TIMER_LATCH_0_MSB (SPM_BASE + 0xE9C)
+#define RC_SYS_TIMER_LATCH_1_LSB (SPM_BASE + 0xEA0)
+#define RC_SYS_TIMER_LATCH_1_MSB (SPM_BASE + 0xEA4)
+#define RC_SYS_TIMER_LATCH_2_LSB (SPM_BASE + 0xEA8)
+#define RC_SYS_TIMER_LATCH_2_MSB (SPM_BASE + 0xEAC)
+#define RC_SYS_TIMER_LATCH_3_LSB (SPM_BASE + 0xEB0)
+#define RC_SYS_TIMER_LATCH_3_MSB (SPM_BASE + 0xEB4)
+#define RC_SYS_TIMER_LATCH_4_LSB (SPM_BASE + 0xEB8)
+#define RC_SYS_TIMER_LATCH_4_MSB (SPM_BASE + 0xEBC)
+#define RC_SYS_TIMER_LATCH_5_LSB (SPM_BASE + 0xEC0)
+#define RC_SYS_TIMER_LATCH_5_MSB (SPM_BASE + 0xEC4)
+#define RC_SYS_TIMER_LATCH_6_LSB (SPM_BASE + 0xEC8)
+#define RC_SYS_TIMER_LATCH_6_MSB (SPM_BASE + 0xECC)
+#define RC_SYS_TIMER_LATCH_7_LSB (SPM_BASE + 0xED0)
+#define RC_SYS_TIMER_LATCH_7_MSB (SPM_BASE + 0xED4)
+#define PCM_WDT_LATCH_19 (SPM_BASE + 0xED8)
+#define PCM_WDT_LATCH_20 (SPM_BASE + 0xEDC)
+#define PCM_WDT_LATCH_21 (SPM_BASE + 0xEE0)
+#define PCM_WDT_LATCH_22 (SPM_BASE + 0xEE4)
+#define PCM_WDT_LATCH_23 (SPM_BASE + 0xEE8)
+#define PCM_WDT_LATCH_24 (SPM_BASE + 0xEEC)
+#define PMSR_LAST_DAT (SPM_BASE + 0xF00)
+#define PMSR_LAST_CNT (SPM_BASE + 0xF04)
+#define PMSR_LAST_ACK (SPM_BASE + 0xF08)
+#define SPM_PMSR_SEL_CON0 (SPM_BASE + 0xF10)
+#define SPM_PMSR_SEL_CON1 (SPM_BASE + 0xF14)
+#define SPM_PMSR_SEL_CON2 (SPM_BASE + 0xF18)
+#define SPM_PMSR_SEL_CON3 (SPM_BASE + 0xF1C)
+#define SPM_PMSR_SEL_CON4 (SPM_BASE + 0xF20)
+#define SPM_PMSR_SEL_CON5 (SPM_BASE + 0xF24)
+#define SPM_PMSR_SEL_CON6 (SPM_BASE + 0xF28)
+#define SPM_PMSR_SEL_CON7 (SPM_BASE + 0xF2C)
+#define SPM_PMSR_SEL_CON8 (SPM_BASE + 0xF30)
+#define SPM_PMSR_SEL_CON9 (SPM_BASE + 0xF34)
+#define SPM_PMSR_SEL_CON10 (SPM_BASE + 0xF3C)
+#define SPM_PMSR_SEL_CON11 (SPM_BASE + 0xF40)
+#define SPM_PMSR_TIEMR_STA0 (SPM_BASE + 0xFB8)
+#define SPM_PMSR_TIEMR_STA1 (SPM_BASE + 0xFBC)
+#define SPM_PMSR_TIEMR_STA2 (SPM_BASE + 0xFC0)
+#define SPM_PMSR_GENERAL_CON0 (SPM_BASE + 0xFC4)
+#define SPM_PMSR_GENERAL_CON1 (SPM_BASE + 0xFC8)
+#define SPM_PMSR_GENERAL_CON2 (SPM_BASE + 0xFCC)
+#define SPM_PMSR_GENERAL_CON3 (SPM_BASE + 0xFD0)
+#define SPM_PMSR_GENERAL_CON4 (SPM_BASE + 0xFD4)
+#define SPM_PMSR_GENERAL_CON5 (SPM_BASE + 0xFD8)
+#define SPM_PMSR_SW_RESET (SPM_BASE + 0xFDC)
+#define SPM_PMSR_MON_CON0 (SPM_BASE + 0xFE0)
+#define SPM_PMSR_MON_CON1 (SPM_BASE + 0xFE4)
+#define SPM_PMSR_MON_CON2 (SPM_BASE + 0xFE8)
+#define SPM_PMSR_LEN_CON0 (SPM_BASE + 0xFEC)
+#define SPM_PMSR_LEN_CON1 (SPM_BASE + 0xFF0)
+#define SPM_PMSR_LEN_CON2 (SPM_BASE + 0xFF4)
+
+/* POWERON_CONFIG_EN (0x10006000+0x000) */
+#define BCLK_CG_EN_LSB (1U << 0) /* 1b */
+#define PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* SPM_POWER_ON_VAL0 (0x10006000+0x004) */
+#define POWER_ON_VAL0_LSB (1U << 0) /* 32b */
+/* SPM_POWER_ON_VAL1 (0x10006000+0x008) */
+#define POWER_ON_VAL1_LSB (1U << 0) /* 32b */
+/* SPM_CLK_CON (0x10006000+0x00C) */
+#define REG_SRCCLKEN0_CTL_LSB (1U << 0) /* 2b */
+#define REG_SRCCLKEN1_CTL_LSB (1U << 2) /* 2b */
+#define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */
+#define REG_SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */
+#define REG_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */
+#define REG_MD1_C32RM_EN_LSB (1U << 9) /* 1b */
+#define REG_MD2_C32RM_EN_LSB (1U << 10) /* 1b */
+#define REG_CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */
+#define REG_CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */
+#define REG_SRCCLKEN0_EN_LSB (1U << 13) /* 1b */
+#define REG_SRCCLKEN1_EN_LSB (1U << 14) /* 1b */
+#define SCP_DCM_EN_LSB (1U << 15) /* 1b */
+#define REG_SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 8b */
+#define REG_SYSCLK1_SRC_MASK_B_LSB (1U << 24) /* 8b */
+/* SPM_CLK_SETTLE (0x10006000+0x010) */
+#define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */
+/* SPM_AP_STANDBY_CON (0x10006000+0x014) */
+#define REG_WFI_OP_LSB (1U << 0) /* 1b */
+#define REG_WFI_TYPE_LSB (1U << 1) /* 1b */
+#define REG_MP0_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */
+#define REG_MP1_CPUTOP_IDLE_MASK_LSB (1U << 3) /* 1b */
+#define REG_MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */
+#define REG_MD_APSRC_1_SEL_LSB (1U << 25) /* 1b */
+#define REG_MD_APSRC_0_SEL_LSB (1U << 26) /* 1b */
+#define REG_CONN_APSRC_SEL_LSB (1U << 29) /* 1b */
+/* PCM_CON0 (0x10006000+0x018) */
+#define PCM_CK_EN_LSB (1U << 2) /* 1b */
+#define RG_EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */
+#define PCM_CK_FROM_CKSYS_LSB (1U << 4) /* 1b */
+#define PCM_SW_RESET_LSB (1U << 15) /* 1b */
+#define PCM_CON0_PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* PCM_CON1 (0x10006000+0x01C) */
+#define RG_IM_SLAVE_LSB (1U << 0) /* 1b */
+#define RG_IM_SLEEP_LSB (1U << 1) /* 1b */
+#define REG_SPM_SRAM_CTRL_MUX_LSB (1U << 2) /* 1b */
+#define RG_AHBMIF_APBEN_LSB (1U << 3) /* 1b */
+#define RG_IM_PDN_LSB (1U << 4) /* 1b */
+#define RG_PCM_TIMER_EN_LSB (1U << 5) /* 1b */
+#define SPM_EVENT_COUNTER_CLR_LSB (1U << 6) /* 1b */
+#define RG_DIS_MIF_PROT_LSB (1U << 7) /* 1b */
+#define RG_PCM_WDT_EN_LSB (1U << 8) /* 1b */
+#define RG_PCM_WDT_WAKE_LSB (1U << 9) /* 1b */
+#define REG_SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */
+#define REG_SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */
+#define REG_EVENT_LOCK_EN_LSB (1U << 12) /* 1b */
+#define REG_SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */
+#define REG_MD32_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */
+#define RG_PCM_IRQ_MSK_LSB (1U << 15) /* 1b */
+#define PCM_CON1_PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* SPM_POWER_ON_VAL2 (0x10006000+0x020) */
+#define POWER_ON_VAL2_LSB (1U << 0) /* 32b */
+/* SPM_POWER_ON_VAL3 (0x10006000+0x024) */
+#define POWER_ON_VAL3_LSB (1U << 0) /* 32b */
+/* PCM_REG_DATA_INI (0x10006000+0x028) */
+#define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */
+/* PCM_PWR_IO_EN (0x10006000+0x02C) */
+#define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */
+#define RG_RF_SYNC_EN_LSB (1U << 16) /* 8b */
+/* PCM_TIMER_VAL (0x10006000+0x030) */
+#define REG_PCM_TIMER_VAL_LSB (1U << 0) /* 32b */
+/* PCM_WDT_VAL (0x10006000+0x034) */
+#define RG_PCM_WDT_VAL_LSB (1U << 0) /* 32b */
+/* SPM_SRC6_MASK (0x10006000+0x038) */
+#define REG_DPMAIF_SRCCLKENA_MASK_B_LSB (1U << 0) /* 1b */
+#define REG_DPMAIF_INFRA_REQ_MASK_B_LSB (1U << 1) /* 1b */
+#define REG_DPMAIF_APSRC_REQ_MASK_B_LSB (1U << 2) /* 1b */
+#define REG_DPMAIF_VRF18_REQ_MASK_B_LSB (1U << 3) /* 1b */
+#define REG_DPMAIF_DDR_EN_MASK_B_LSB (1U << 4) /* 1b */
+/* SPM_SW_RST_CON (0x10006000+0x040) */
+#define SPM_SW_RST_CON_LSB (1U << 0) /* 16b */
+#define SPM_SW_RST_CON_PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* SPM_SW_RST_CON_SET (0x10006000+0x044) */
+#define SPM_SW_RST_CON_SET_LSB (1U << 0) /* 16b */
+#define SPM_SW_RST_CON_SET_PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* SPM_SW_RST_CON_CLR (0x10006000+0x048) */
+#define SPM_SW_RST_CON_CLR_LSB (1U << 0) /* 16b */
+#define SPM_SW_RST_CON_CLR_PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* VS1_PSR_MASK_B (0x10006000+0x04C) */
+#define VS1_OPP0_PSR_MASK_B_LSB (1U << 0) /* 8b */
+#define VS1_OPP1_PSR_MASK_B_LSB (1U << 8) /* 8b */
+/* VS2_PSR_MASK_B (0x10006000+0x050) */
+#define VS2_OPP0_PSR_MASK_B_LSB (1U << 0) /* 8b */
+#define VS2_OPP1_PSR_MASK_B_LSB (1U << 8) /* 8b */
+#define VS2_OPP2_PSR_MASK_B_LSB (1U << 16) /* 8b */
+/* MD32_CLK_CON (0x10006000+0x084) */
+#define REG_MD32_26M_CK_SEL_LSB (1U << 0) /* 1b */
+#define REG_MD32_DCM_EN_LSB (1U << 1) /* 1b */
+/* SPM_SRAM_RSV_CON (0x10006000+0x088) */
+#define SPM_SRAM_SLEEP_B_ECO_EN_LSB (1U << 0) /* 1b */
+/* SPM_SWINT (0x10006000+0x08C) */
+#define SPM_SWINT_LSB (1U << 0) /* 32b */
+/* SPM_SWINT_SET (0x10006000+0x090) */
+#define SPM_SWINT_SET_LSB (1U << 0) /* 32b */
+/* SPM_SWINT_CLR (0x10006000+0x094) */
+#define SPM_SWINT_CLR_LSB (1U << 0) /* 32b */
+/* SPM_SCP_MAILBOX (0x10006000+0x098) */
+#define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */
+/* SCP_SPM_MAILBOX (0x10006000+0x09C) */
+#define SCP_SPM_MAILBOX_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CON (0x10006000+0x0A0) */
+#define REG_TWAM_ENABLE_LSB (1U << 0) /* 1b */
+#define REG_TWAM_SPEED_MODE_EN_LSB (1U << 1) /* 1b */
+#define REG_TWAM_SW_RST_LSB (1U << 2) /* 1b */
+#define REG_TWAM_IRQ_MASK_LSB (1U << 3) /* 1b */
+#define REG_TWAM_MON_TYPE_0_LSB (1U << 4) /* 2b */
+#define REG_TWAM_MON_TYPE_1_LSB (1U << 6) /* 2b */
+#define REG_TWAM_MON_TYPE_2_LSB (1U << 8) /* 2b */
+#define REG_TWAM_MON_TYPE_3_LSB (1U << 10) /* 2b */
+/* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */
+#define REG_TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */
+#define REG_TWAM_SIG_SEL_0_LSB (1U << 0) /* 7b */
+#define REG_TWAM_SIG_SEL_1_LSB (1U << 8) /* 7b */
+#define REG_TWAM_SIG_SEL_2_LSB (1U << 16) /* 7b */
+#define REG_TWAM_SIG_SEL_3_LSB (1U << 24) /* 7b */
+/* SPM_SCP_IRQ (0x10006000+0x0AC) */
+#define SC_SPM2SCP_WAKEUP_LSB (1U << 0) /* 1b */
+#define SC_SCP2SPM_WAKEUP_LSB (1U << 4) /* 1b */
+/* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */
+#define REG_CPU_WAKEUP_LSB (1U << 0) /* 1b */
+/* SPM_IRQ_MASK (0x10006000+0x0B4) */
+#define REG_SPM_IRQ_MASK_LSB (1U << 0) /* 32b */
+/* SPM_SRC_REQ (0x10006000+0x0B8) */
+#define REG_SPM_APSRC_REQ_LSB (1U << 0) /* 1b */
+#define REG_SPM_F26M_REQ_LSB (1U << 1) /* 1b */
+#define REG_SPM_INFRA_REQ_LSB (1U << 3) /* 1b */
+#define REG_SPM_VRF18_REQ_LSB (1U << 4) /* 1b */
+#define REG_SPM_DDR_EN_REQ_LSB (1U << 7) /* 1b */
+#define REG_SPM_DVFS_REQ_LSB (1U << 8) /* 1b */
+#define REG_SPM_SW_MAILBOX_REQ_LSB (1U << 9) /* 1b */
+#define REG_SPM_SSPM_MAILBOX_REQ_LSB (1U << 10) /* 1b */
+#define REG_SPM_ADSP_MAILBOX_REQ_LSB (1U << 11) /* 1b */
+#define REG_SPM_SCP_MAILBOX_REQ_LSB (1U << 12) /* 1b */
+/* SPM_SRC_MASK (0x10006000+0x0BC) */
+#define REG_MD_SRCCLKENA_0_MASK_B_LSB (1U << 0) /* 1b */
+#define REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B_LSB (1U << 1) /* 1b */
+#define REG_MD_APSRC2INFRA_REQ_0_MASK_B_LSB (1U << 2) /* 1b */
+#define REG_MD_APSRC_REQ_0_MASK_B_LSB (1U << 3) /* 1b */
+#define REG_MD_VRF18_REQ_0_MASK_B_LSB (1U << 4) /* 1b */
+#define REG_MD_DDR_EN_0_MASK_B_LSB (1U << 5) /* 1b */
+#define REG_MD_SRCCLKENA_1_MASK_B_LSB (1U << 6) /* 1b */
+#define REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B_LSB (1U << 7) /* 1b */
+#define REG_MD_APSRC2INFRA_REQ_1_MASK_B_LSB (1U << 8) /* 1b */
+#define REG_MD_APSRC_REQ_1_MASK_B_LSB (1U << 9) /* 1b */
+#define REG_MD_VRF18_REQ_1_MASK_B_LSB (1U << 10) /* 1b */
+#define REG_MD_DDR_EN_1_MASK_B_LSB (1U << 11) /* 1b */
+#define REG_CONN_SRCCLKENA_MASK_B_LSB (1U << 12) /* 1b */
+#define REG_CONN_SRCCLKENB_MASK_B_LSB (1U << 13) /* 1b */
+#define REG_CONN_INFRA_REQ_MASK_B_LSB (1U << 14) /* 1b */
+#define REG_CONN_APSRC_REQ_MASK_B_LSB (1U << 15) /* 1b */
+#define REG_CONN_VRF18_REQ_MASK_B_LSB (1U << 16) /* 1b */
+#define REG_CONN_DDR_EN_MASK_B_LSB (1U << 17) /* 1b */
+#define REG_CONN_VFE28_MASK_B_LSB (1U << 18) /* 1b */
+#define REG_SRCCLKENI0_SRCCLKENA_MASK_B_LSB (1U << 19) /* 1b */
+#define REG_SRCCLKENI0_INFRA_REQ_MASK_B_LSB (1U << 20) /* 1b */
+#define REG_SRCCLKENI1_SRCCLKENA_MASK_B_LSB (1U << 21) /* 1b */
+#define REG_SRCCLKENI1_INFRA_REQ_MASK_B_LSB (1U << 22) /* 1b */
+#define REG_SRCCLKENI2_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */
+#define REG_SRCCLKENI2_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */
+#define REG_INFRASYS_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */
+#define REG_INFRASYS_DDR_EN_MASK_B_LSB (1U << 26) /* 1b */
+#define REG_MD32_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */
+#define REG_MD32_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */
+#define REG_MD32_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */
+#define REG_MD32_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */
+#define REG_MD32_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */
+/* SPM_SRC2_MASK (0x10006000+0x0C0) */
+#define REG_SCP_SRCCLKENA_MASK_B_LSB (1U << 0) /* 1b */
+#define REG_SCP_INFRA_REQ_MASK_B_LSB (1U << 1) /* 1b */
+#define REG_SCP_APSRC_REQ_MASK_B_LSB (1U << 2) /* 1b */
+#define REG_SCP_VRF18_REQ_MASK_B_LSB (1U << 3) /* 1b */
+#define REG_SCP_DDR_EN_MASK_B_LSB (1U << 4) /* 1b */
+#define REG_AUDIO_DSP_SRCCLKENA_MASK_B_LSB (1U << 5) /* 1b */
+#define REG_AUDIO_DSP_INFRA_REQ_MASK_B_LSB (1U << 6) /* 1b */
+#define REG_AUDIO_DSP_APSRC_REQ_MASK_B_LSB (1U << 7) /* 1b */
+#define REG_AUDIO_DSP_VRF18_REQ_MASK_B_LSB (1U << 8) /* 1b */
+#define REG_AUDIO_DSP_DDR_EN_MASK_B_LSB (1U << 9) /* 1b */
+#define REG_UFS_SRCCLKENA_MASK_B_LSB (1U << 10) /* 1b */
+#define REG_UFS_INFRA_REQ_MASK_B_LSB (1U << 11) /* 1b */
+#define REG_UFS_APSRC_REQ_MASK_B_LSB (1U << 12) /* 1b */
+#define REG_UFS_VRF18_REQ_MASK_B_LSB (1U << 13) /* 1b */
+#define REG_UFS_DDR_EN_MASK_B_LSB (1U << 14) /* 1b */
+#define REG_DISP0_APSRC_REQ_MASK_B_LSB (1U << 15) /* 1b */
+#define REG_DISP0_DDR_EN_MASK_B_LSB (1U << 16) /* 1b */
+#define REG_DISP1_APSRC_REQ_MASK_B_LSB (1U << 17) /* 1b */
+#define REG_DISP1_DDR_EN_MASK_B_LSB (1U << 18) /* 1b */
+#define REG_GCE_INFRA_REQ_MASK_B_LSB (1U << 19) /* 1b */
+#define REG_GCE_APSRC_REQ_MASK_B_LSB (1U << 20) /* 1b */
+#define REG_GCE_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */
+#define REG_GCE_DDR_EN_MASK_B_LSB (1U << 22) /* 1b */
+#define REG_APU_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */
+#define REG_APU_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */
+#define REG_APU_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */
+#define REG_APU_VRF18_REQ_MASK_B_LSB (1U << 26) /* 1b */
+#define REG_APU_DDR_EN_MASK_B_LSB (1U << 27) /* 1b */
+#define REG_CG_CHECK_SRCCLKENA_MASK_B_LSB (1U << 28) /* 1b */
+#define REG_CG_CHECK_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */
+#define REG_CG_CHECK_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */
+#define REG_CG_CHECK_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */
+/* SPM_SRC3_MASK (0x10006000+0x0C4) */
+#define REG_DVFSRC_EVENT_TRIGGER_MASK_B_LSB (1U << 0) /* 1b */
+#define REG_SW2SPM_INT0_MASK_B_LSB (1U << 1) /* 1b */
+#define REG_SW2SPM_INT1_MASK_B_LSB (1U << 2) /* 1b */
+#define REG_SW2SPM_INT2_MASK_B_LSB (1U << 3) /* 1b */
+#define REG_SW2SPM_INT3_MASK_B_LSB (1U << 4) /* 1b */
+#define REG_SC_ADSP2SPM_WAKEUP_MASK_B_LSB (1U << 5) /* 1b */
+#define REG_SC_SSPM2SPM_WAKEUP_MASK_B_LSB (1U << 6) /* 4b */
+#define REG_SC_SCP2SPM_WAKEUP_MASK_B_LSB (1U << 10) /* 1b */
+#define REG_CSYSPWRREQ_MASK_LSB (1U << 11) /* 1b */
+#define REG_SPM_SRCCLKENA_RESERVED_MASK_B_LSB (1U << 12) /* 1b */
+#define REG_SPM_INFRA_REQ_RESERVED_MASK_B_LSB (1U << 13) /* 1b */
+#define REG_SPM_APSRC_REQ_RESERVED_MASK_B_LSB (1U << 14) /* 1b */
+#define REG_SPM_VRF18_REQ_RESERVED_MASK_B_LSB (1U << 15) /* 1b */
+#define REG_SPM_DDR_EN_RESERVED_MASK_B_LSB (1U << 16) /* 1b */
+#define REG_MCUPM_SRCCLKENA_MASK_B_LSB (1U << 17) /* 1b */
+#define REG_MCUPM_INFRA_REQ_MASK_B_LSB (1U << 18) /* 1b */
+#define REG_MCUPM_APSRC_REQ_MASK_B_LSB (1U << 19) /* 1b */
+#define REG_MCUPM_VRF18_REQ_MASK_B_LSB (1U << 20) /* 1b */
+#define REG_MCUPM_DDR_EN_MASK_B_LSB (1U << 21) /* 1b */
+#define REG_MSDC0_SRCCLKENA_MASK_B_LSB (1U << 22) /* 1b */
+#define REG_MSDC0_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */
+#define REG_MSDC0_APSRC_REQ_MASK_B_LSB (1U << 24) /* 1b */
+#define REG_MSDC0_VRF18_REQ_MASK_B_LSB (1U << 25) /* 1b */
+#define REG_MSDC0_DDR_EN_MASK_B_LSB (1U << 26) /* 1b */
+#define REG_MSDC1_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */
+#define REG_MSDC1_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */
+#define REG_MSDC1_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */
+#define REG_MSDC1_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */
+#define REG_MSDC1_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */
+/* SPM_SRC4_MASK (0x10006000+0x0C8) */
+#define CCIF_EVENT_MASK_B_LSB (1U << 0) /* 16b */
+#define REG_BAK_PSRI_SRCCLKENA_MASK_B_LSB (1U << 16) /* 1b */
+#define REG_BAK_PSRI_INFRA_REQ_MASK_B_LSB (1U << 17) /* 1b */
+#define REG_BAK_PSRI_APSRC_REQ_MASK_B_LSB (1U << 18) /* 1b */
+#define REG_BAK_PSRI_VRF18_REQ_MASK_B_LSB (1U << 19) /* 1b */
+#define REG_BAK_PSRI_DDR_EN_MASK_B_LSB (1U << 20) /* 1b */
+#define REG_DRAMC0_MD32_INFRA_REQ_MASK_B_LSB (1U << 21) /* 1b */
+#define REG_DRAMC0_MD32_VRF18_REQ_MASK_B_LSB (1U << 22) /* 1b */
+#define REG_DRAMC1_MD32_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */
+#define REG_DRAMC1_MD32_VRF18_REQ_MASK_B_LSB (1U << 24) /* 1b */
+#define REG_CONN_SRCCLKENB2PWRAP_MASK_B_LSB (1U << 25) /* 1b */
+#define REG_DRAMC0_MD32_WAKEUP_MASK_LSB (1U << 26) /* 1b */
+#define REG_DRAMC1_MD32_WAKEUP_MASK_LSB (1U << 27) /* 1b */
+/* SPM_SRC5_MASK (0x10006000+0x0CC) */
+#define REG_MCUSYS_MERGE_APSRC_REQ_MASK_B_LSB (1U << 0) /* 9b */
+#define REG_MCUSYS_MERGE_DDR_EN_MASK_B_LSB (1U << 9) /* 9b */
+#define REG_MSDC2_SRCCLKENA_MASK_B_LSB (1U << 18) /* 1b */
+#define REG_MSDC2_INFRA_REQ_MASK_B_LSB (1U << 19) /* 1b */
+#define REG_MSDC2_APSRC_REQ_MASK_B_LSB (1U << 20) /* 1b */
+#define REG_MSDC2_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */
+#define REG_MSDC2_DDR_EN_MASK_B_LSB (1U << 22) /* 1b */
+#define REG_PCIE_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */
+#define REG_PCIE_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */
+#define REG_PCIE_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */
+#define REG_PCIE_VRF18_REQ_MASK_B_LSB (1U << 26) /* 1b */
+#define REG_PCIE_DDR_EN_MASK_B_LSB (1U << 27) /* 1b */
+/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0D0) */
+#define REG_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */
+/* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0D4) */
+#define REG_EXT_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_EVENT_CLEAR (0x10006000+0x0D8) */
+#define SPM_TWAM_EVENT_CLEAR_LSB (1U << 0) /* 1b */
+/* SCP_CLK_CON (0x10006000+0x0DC) */
+#define REG_SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */
+#define REG_SCP_DCM_EN_LSB (1U << 1) /* 1b */
+#define SCP_SECURE_V_REQ_MASK_LSB (1U << 2) /* 1b */
+#define SCP_SLP_REQ_LSB (1U << 3) /* 1b */
+#define SCP_SLP_ACK_LSB (1U << 4) /* 1b */
+/* PCM_DEBUG_CON (0x10006000+0x0E0) */
+#define PCM_DEBUG_OUT_ENABLE_LSB (1U << 0) /* 1b */
+/* AHB_BUS_CON (0x10006000+0x0E4) */
+#define AHB_HADDR_EXT_LSB (1U << 0) /* 2b */
+#define REG_AHB_LOCK_LSB (1U << 8) /* 1b */
+/* DDR_EN_DBC_CON0 (0x10006000+0x0E8) */
+#define REG_ALL_DDR_EN_DBC_LEN_LSB (1U << 0) /* 10b */
+#define REG_MD_DDR_EN_0_DBC_LEN_LSB (1U << 10) /* 10b */
+#define REG_HW_S1_DBC_LEN_LSB (1U << 20) /* 10b */
+/* DDR_EN_DBC_CON1 (0x10006000+0x0EC) */
+#define REG_ALL_DDR_EN_DBC_EN_LSB (1U << 0) /* 1b */
+#define REG_MD_DDR_EN_0_DBC_EN_LSB (1U << 1) /* 1b */
+#define REG_HW_S1_DBC_EN_LSB (1U << 2) /* 1b */
+/* SPM_RESOURCE_ACK_CON0 (0x10006000+0x0F0) */
+#define REG_MD_SRCCLKENA_ACK_0_MASK_LSB (1U << 0) /* 1b */
+#define REG_MD_INFRA_ACK_0_MASK_LSB (1U << 1) /* 1b */
+#define REG_MD_APSRC_ACK_0_MASK_LSB (1U << 2) /* 1b */
+#define REG_MD_VRF18_ACK_0_MASK_LSB (1U << 3) /* 1b */
+#define REG_MD_DDR_EN_ACK_0_MASK_LSB (1U << 4) /* 1b */
+#define REG_MD_SRCCLKENA_ACK_1_MASK_LSB (1U << 5) /* 1b */
+#define REG_MD_INFRA_ACK_1_MASK_LSB (1U << 6) /* 1b */
+#define REG_MD_APSRC_ACK_1_MASK_LSB (1U << 7) /* 1b */
+#define REG_MD_VRF18_ACK_1_MASK_LSB (1U << 8) /* 1b */
+#define REG_MD_DDR_EN_ACK_1_MASK_LSB (1U << 9) /* 1b */
+#define REG_CONN_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */
+#define REG_CONN_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */
+#define REG_CONN_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */
+#define REG_CONN_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */
+#define REG_CONN_DDR_EN_ACK_MASK_LSB (1U << 14) /* 1b */
+#define REG_MD32_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */
+#define REG_MD32_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */
+#define REG_MD32_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */
+#define REG_MD32_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */
+#define REG_MD32_DDR_EN_ACK_MASK_LSB (1U << 19) /* 1b */
+#define REG_SCP_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */
+#define REG_SCP_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */
+#define REG_SCP_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */
+#define REG_SCP_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */
+#define REG_SCP_DDR_EN_ACK_MASK_LSB (1U << 24) /* 1b */
+#define REG_AUDIO_DSP_SRCCLKENA_ACK_MASK_LSB (1U << 25) /* 1b */
+#define REG_AUDIO_DSP_INFRA_ACK_MASK_LSB (1U << 26) /* 1b */
+#define REG_AUDIO_DSP_APSRC_ACK_MASK_LSB (1U << 27) /* 1b */
+#define REG_AUDIO_DSP_VRF18_ACK_MASK_LSB (1U << 28) /* 1b */
+#define REG_AUDIO_DSP_DDR_EN_ACK_MASK_LSB (1U << 29) /* 1b */
+#define REG_DISP0_DDR_EN_ACK_MASK_LSB (1U << 30) /* 1b */
+#define REG_DISP1_APSRC_ACK_MASK_LSB (1U << 31) /* 1b */
+/* SPM_RESOURCE_ACK_CON1 (0x10006000+0x0F4) */
+#define REG_UFS_SRCCLKENA_ACK_MASK_LSB (1U << 0) /* 1b */
+#define REG_UFS_INFRA_ACK_MASK_LSB (1U << 1) /* 1b */
+#define REG_UFS_APSRC_ACK_MASK_LSB (1U << 2) /* 1b */
+#define REG_UFS_VRF18_ACK_MASK_LSB (1U << 3) /* 1b */
+#define REG_UFS_DDR_EN_ACK_MASK_LSB (1U << 4) /* 1b */
+#define REG_APU_SRCCLKENA_ACK_MASK_LSB (1U << 5) /* 1b */
+#define REG_APU_INFRA_ACK_MASK_LSB (1U << 6) /* 1b */
+#define REG_APU_APSRC_ACK_MASK_LSB (1U << 7) /* 1b */
+#define REG_APU_VRF18_ACK_MASK_LSB (1U << 8) /* 1b */
+#define REG_APU_DDR_EN_ACK_MASK_LSB (1U << 9) /* 1b */
+#define REG_MCUPM_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */
+#define REG_MCUPM_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */
+#define REG_MCUPM_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */
+#define REG_MCUPM_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */
+#define REG_MCUPM_DDR_EN_ACK_MASK_LSB (1U << 14) /* 1b */
+#define REG_MSDC0_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */
+#define REG_MSDC0_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */
+#define REG_MSDC0_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */
+#define REG_MSDC0_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */
+#define REG_MSDC0_DDR_EN_ACK_MASK_LSB (1U << 19) /* 1b */
+#define REG_MSDC1_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */
+#define REG_MSDC1_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */
+#define REG_MSDC1_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */
+#define REG_MSDC1_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */
+#define REG_MSDC1_DDR_EN_ACK_MASK_LSB (1U << 24) /* 1b */
+#define REG_DISP0_APSRC_ACK_MASK_LSB (1U << 25) /* 1b */
+#define REG_DISP1_DDR_EN_ACK_MASK_LSB (1U << 26) /* 1b */
+#define REG_GCE_INFRA_ACK_MASK_LSB (1U << 27) /* 1b */
+#define REG_GCE_APSRC_ACK_MASK_LSB (1U << 28) /* 1b */
+#define REG_GCE_VRF18_ACK_MASK_LSB (1U << 29) /* 1b */
+#define REG_GCE_DDR_EN_ACK_MASK_LSB (1U << 30) /* 1b */
+/* SPM_RESOURCE_ACK_CON2 (0x10006000+0x0F8) */
+#define SPM_F26M_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */
+#define SPM_INFRA_ACK_WAIT_CYCLE_LSB (1U << 8) /* 8b */
+#define SPM_APSRC_ACK_WAIT_CYCLE_LSB (1U << 16) /* 8b */
+#define SPM_VRF18_ACK_WAIT_CYCLE_LSB (1U << 24) /* 8b */
+/* SPM_RESOURCE_ACK_CON3 (0x10006000+0x0FC) */
+#define SPM_DDR_EN_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */
+#define REG_BAK_PSRI_SRCCLKENA_ACK_MASK_LSB (1U << 8) /* 1b */
+#define REG_BAK_PSRI_INFRA_ACK_MASK_LSB (1U << 9) /* 1b */
+#define REG_BAK_PSRI_APSRC_ACK_MASK_LSB (1U << 10) /* 1b */
+#define REG_BAK_PSRI_VRF18_ACK_MASK_LSB (1U << 11) /* 1b */
+#define REG_BAK_PSRI_DDR_EN_ACK_MASK_LSB (1U << 12) /* 1b */
+#define REG_MSDC2_SRCCLKENA_ACK_MASK_LSB (1U << 13) /* 1b */
+#define REG_MSDC2_INFRA_ACK_MASK_LSB (1U << 14) /* 1b */
+#define REG_MSDC2_APSRC_ACK_MASK_LSB (1U << 15) /* 1b */
+#define REG_MSDC2_VRF18_ACK_MASK_LSB (1U << 16) /* 1b */
+#define REG_MSDC2_DDR_EN_ACK_MASK_LSB (1U << 17) /* 1b */
+#define REG_PCIE_SRCCLKENA_ACK_MASK_LSB (1U << 18) /* 1b */
+#define REG_PCIE_INFRA_ACK_MASK_LSB (1U << 19) /* 1b */
+#define REG_PCIE_APSRC_ACK_MASK_LSB (1U << 20) /* 1b */
+#define REG_PCIE_VRF18_ACK_MASK_LSB (1U << 21) /* 1b */
+#define REG_PCIE_DDR_EN_ACK_MASK_LSB (1U << 22) /* 1b */
+#define REG_DPMAIF_SRCCLKENA_ACK_MASK_LSB (1U << 23) /* 1b */
+#define REG_DPMAIF_INFRA_ACK_MASK_LSB (1U << 24) /* 1b */
+#define REG_DPMAIF_APSRC_ACK_MASK_LSB (1U << 25) /* 1b */
+#define REG_DPMAIF_VRF18_ACK_MASK_LSB (1U << 26) /* 1b */
+#define REG_DPMAIF_DDR_EN_ACK_MASK_LSB (1U << 27) /* 1b */
+/* PCM_REG0_DATA (0x10006000+0x100) */
+#define PCM_REG0_RF_LSB (1U << 0) /* 32b */
+/* PCM_REG2_DATA (0x10006000+0x104) */
+#define PCM_REG2_RF_LSB (1U << 0) /* 32b */
+/* PCM_REG6_DATA (0x10006000+0x108) */
+#define PCM_REG6_RF_LSB (1U << 0) /* 32b */
+/* PCM_REG7_DATA (0x10006000+0x10C) */
+#define PCM_REG7_RF_LSB (1U << 0) /* 32b */
+/* PCM_REG13_DATA (0x10006000+0x110) */
+#define PCM_REG13_RF_LSB (1U << 0) /* 32b */
+/* SRC_REQ_STA_0 (0x10006000+0x114) */
+#define MD_SRCCLKENA_0_LSB (1U << 0) /* 1b */
+#define MD_SRCCLKENA2INFRA_REQ_0_LSB (1U << 1) /* 1b */
+#define MD_APSRC2INFRA_REQ_0_LSB (1U << 2) /* 1b */
+#define MD_APSRC_REQ_0_LSB (1U << 3) /* 1b */
+#define MD_VRF18_REQ_0_LSB (1U << 4) /* 1b */
+#define MD_DDR_EN_0_LSB (1U << 5) /* 1b */
+#define MD_SRCCLKENA_1_LSB (1U << 6) /* 1b */
+#define MD_SRCCLKENA2INFRA_REQ_1_LSB (1U << 7) /* 1b */
+#define MD_APSRC2INFRA_REQ_1_LSB (1U << 8) /* 1b */
+#define MD_APSRC_REQ_1_LSB (1U << 9) /* 1b */
+#define MD_VRF18_REQ_1_LSB (1U << 10) /* 1b */
+#define MD_DDR_EN_1_LSB (1U << 11) /* 1b */
+#define CONN_SRCCLKENA_LSB (1U << 12) /* 1b */
+#define CONN_SRCCLKENB_LSB (1U << 13) /* 1b */
+#define CONN_INFRA_REQ_LSB (1U << 14) /* 1b */
+#define CONN_APSRC_REQ_LSB (1U << 15) /* 1b */
+#define CONN_VRF18_REQ_LSB (1U << 16) /* 1b */
+#define CONN_DDR_EN_LSB (1U << 17) /* 1b */
+#define SRCCLKENI_LSB (1U << 18) /* 3b */
+#define MD32_SRCCLKENA_LSB (1U << 21) /* 1b */
+#define MD32_INFRA_REQ_LSB (1U << 22) /* 1b */
+#define MD32_APSRC_REQ_LSB (1U << 23) /* 1b */
+#define MD32_VRF18_REQ_LSB (1U << 24) /* 1b */
+#define MD32_DDR_EN_LSB (1U << 25) /* 1b */
+#define DISP0_APSRC_REQ_LSB (1U << 26) /* 1b */
+#define DISP0_DDR_EN_LSB (1U << 27) /* 1b */
+#define DISP1_APSRC_REQ_LSB (1U << 28) /* 1b */
+#define DISP1_DDR_EN_LSB (1U << 29) /* 1b */
+#define DVFSRC_EVENT_TRIGGER_LSB (1U << 30) /* 1b */
+/* SRC_REQ_STA_1 (0x10006000+0x118) */
+#define SCP_SRCCLKENA_LSB (1U << 0) /* 1b */
+#define SCP_INFRA_REQ_LSB (1U << 1) /* 1b */
+#define SCP_APSRC_REQ_LSB (1U << 2) /* 1b */
+#define SCP_VRF18_REQ_LSB (1U << 3) /* 1b */
+#define SCP_DDR_EN_LSB (1U << 4) /* 1b */
+#define AUDIO_DSP_SRCCLKENA_LSB (1U << 5) /* 1b */
+#define AUDIO_DSP_INFRA_REQ_LSB (1U << 6) /* 1b */
+#define AUDIO_DSP_APSRC_REQ_LSB (1U << 7) /* 1b */
+#define AUDIO_DSP_VRF18_REQ_LSB (1U << 8) /* 1b */
+#define AUDIO_DSP_DDR_EN_LSB (1U << 9) /* 1b */
+#define UFS_SRCCLKENA_LSB (1U << 10) /* 1b */
+#define UFS_INFRA_REQ_LSB (1U << 11) /* 1b */
+#define UFS_APSRC_REQ_LSB (1U << 12) /* 1b */
+#define UFS_VRF18_REQ_LSB (1U << 13) /* 1b */
+#define UFS_DDR_EN_LSB (1U << 14) /* 1b */
+#define GCE_INFRA_REQ_LSB (1U << 15) /* 1b */
+#define GCE_APSRC_REQ_LSB (1U << 16) /* 1b */
+#define GCE_VRF18_REQ_LSB (1U << 17) /* 1b */
+#define GCE_DDR_EN_LSB (1U << 18) /* 1b */
+#define INFRASYS_APSRC_REQ_LSB (1U << 19) /* 1b */
+#define INFRASYS_DDR_EN_LSB (1U << 20) /* 1b */
+#define MSDC0_SRCCLKENA_LSB (1U << 21) /* 1b */
+#define MSDC0_INFRA_REQ_LSB (1U << 22) /* 1b */
+#define MSDC0_APSRC_REQ_LSB (1U << 23) /* 1b */
+#define MSDC0_VRF18_REQ_LSB (1U << 24) /* 1b */
+#define MSDC0_DDR_EN_LSB (1U << 25) /* 1b */
+#define MSDC1_SRCCLKENA_LSB (1U << 26) /* 1b */
+#define MSDC1_INFRA_REQ_LSB (1U << 27) /* 1b */
+#define MSDC1_APSRC_REQ_LSB (1U << 28) /* 1b */
+#define MSDC1_VRF18_REQ_LSB (1U << 29) /* 1b */
+#define MSDC1_DDR_EN_LSB (1U << 30) /* 1b */
+/* SRC_REQ_STA_2 (0x10006000+0x11C) */
+#define MCUSYS_MERGE_DDR_EN_LSB (1U << 0) /* 9b */
+#define EMI_SELF_REFRESH_CH_LSB (1U << 9) /* 2b */
+#define SW2SPM_INT_LSB (1U << 11) /* 4b */
+#define SC_ADSP2SPM_WAKEUP_LSB (1U << 15) /* 1b */
+#define SC_SSPM2SPM_WAKEUP_LSB (1U << 16) /* 4b */
+#define SRC_REQ_STA_2_SC_SCP2SPM_WAKEUP_LSB (1U << 20) /* 1b */
+#define SPM_SRCCLKENA_RESERVED_LSB (1U << 21) /* 1b */
+#define SPM_INFRA_REQ_RESERVED_LSB (1U << 22) /* 1b */
+#define SPM_APSRC_REQ_RESERVED_LSB (1U << 23) /* 1b */
+#define SPM_VRF18_REQ_RESERVED_LSB (1U << 24) /* 1b */
+#define SPM_DDR_EN_RESERVED_LSB (1U << 25) /* 1b */
+#define MCUPM_SRCCLKENA_LSB (1U << 26) /* 1b */
+#define MCUPM_INFRA_REQ_LSB (1U << 27) /* 1b */
+#define MCUPM_APSRC_REQ_LSB (1U << 28) /* 1b */
+#define MCUPM_VRF18_REQ_LSB (1U << 29) /* 1b */
+#define MCUPM_DDR_EN_LSB (1U << 30) /* 1b */
+/* PCM_TIMER_OUT (0x10006000+0x120) */
+#define PCM_TIMER_LSB (1U << 0) /* 32b */
+/* PCM_WDT_OUT (0x10006000+0x124) */
+#define PCM_WDT_TIMER_VAL_OUT_LSB (1U << 0) /* 32b */
+/* SPM_IRQ_STA (0x10006000+0x128) */
+#define TWAM_IRQ_LSB (1U << 2) /* 1b */
+#define PCM_IRQ_LSB (1U << 3) /* 1b */
+/* SRC_REQ_STA_4 (0x10006000+0x12C) */
+#define APU_SRCCLKENA_LSB (1U << 0) /* 1b */
+#define APU_INFRA_REQ_LSB (1U << 1) /* 1b */
+#define APU_APSRC_REQ_LSB (1U << 2) /* 1b */
+#define APU_VRF18_REQ_LSB (1U << 3) /* 1b */
+#define APU_DDR_EN_LSB (1U << 4) /* 1b */
+#define BAK_PSRI_SRCCLKENA_LSB (1U << 5) /* 1b */
+#define BAK_PSRI_INFRA_REQ_LSB (1U << 6) /* 1b */
+#define BAK_PSRI_APSRC_REQ_LSB (1U << 7) /* 1b */
+#define BAK_PSRI_VRF18_REQ_LSB (1U << 8) /* 1b */
+#define BAK_PSRI_DDR_EN_LSB (1U << 9) /* 1b */
+#define MSDC2_SRCCLKENA_LSB (1U << 10) /* 1b */
+#define MSDC2_INFRA_REQ_LSB (1U << 11) /* 1b */
+#define MSDC2_APSRC_REQ_LSB (1U << 12) /* 1b */
+#define MSDC2_VRF18_REQ_LSB (1U << 13) /* 1b */
+#define MSDC2_DDR_EN_LSB (1U << 14) /* 1b */
+#define PCIE_SRCCLKENA_LSB (1U << 15) /* 1b */
+#define PCIE_INFRA_REQ_LSB (1U << 16) /* 1b */
+#define PCIE_APSRC_REQ_LSB (1U << 17) /* 1b */
+#define PCIE_VRF18_REQ_LSB (1U << 18) /* 1b */
+#define PCIE_DDR_EN_LSB (1U << 19) /* 1b */
+#define DPMAIF_SRCCLKENA_LSB (1U << 20) /* 1b */
+#define DPMAIF_INFRA_REQ_LSB (1U << 21) /* 1b */
+#define DPMAIF_APSRC_REQ_LSB (1U << 22) /* 1b */
+#define DPMAIF_VRF18_REQ_LSB (1U << 23) /* 1b */
+#define DPMAIF_DDR_EN_LSB (1U << 24) /* 1b */
+/* MD32PCM_WAKEUP_STA (0x10006000+0x130) */
+#define MD32PCM_WAKEUP_STA_LSB (1U << 0) /* 32b */
+/* MD32PCM_EVENT_STA (0x10006000+0x134) */
+#define MD32PCM_EVENT_STA_LSB (1U << 0) /* 32b */
+/* SPM_WAKEUP_STA (0x10006000+0x138) */
+#define F32K_WAKEUP_EVENT_L_LSB (1U << 0) /* 16b */
+#define ASYN_WAKEUP_EVENT_L_LSB (1U << 16) /* 16b */
+/* SPM_WAKEUP_EXT_STA (0x10006000+0x13C) */
+#define EXT_WAKEUP_EVENT_LSB (1U << 0) /* 32b */
+/* SPM_WAKEUP_MISC (0x10006000+0x140) */
+#define GIC_WAKEUP_LSB (1U << 0) /* 10b */
+#define DVFSRC_IRQ_LSB (1U << 16) /* 1b */
+#define SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB (1U << 17) /* 1b */
+#define PCM_TIMER_EVENT_LSB (1U << 18) /* 1b */
+#define PMIC_EINT_OUT_B_LSB (1U << 19) /* 2b */
+#define TWAM_IRQ_B_LSB (1U << 21) /* 1b */
+#define PMSR_IRQ_B_SET0_LSB (1U << 22) /* 1b */
+#define PMSR_IRQ_B_SET1_LSB (1U << 23) /* 1b */
+#define PMSR_IRQ_B_SET2_LSB (1U << 24) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_0_LSB (1U << 25) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_1_LSB (1U << 26) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_2_LSB (1U << 27) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_3_LSB (1U << 28) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_ALL_LSB (1U << 29) /* 1b */
+#define PMIC_IRQ_ACK_LSB (1U << 30) /* 1b */
+#define PMIC_SCP_IRQ_LSB (1U << 31) /* 1b */
+/* MM_DVFS_HALT (0x10006000+0x144) */
+#define MM_DVFS_HALT_LSB (1U << 0) /* 5b */
+/* BUS_PROTECT_RDY (0x10006000+0x150) */
+#define PROTECT_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT1_RDY (0x10006000+0x154) */
+#define PROTECT1_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT2_RDY (0x10006000+0x158) */
+#define PROTECT2_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT3_RDY (0x10006000+0x15C) */
+#define PROTECT3_READY_LSB (1U << 0) /* 32b */
+/* SUBSYS_IDLE_STA (0x10006000+0x160) */
+#define SUBSYS_IDLE_SIGNALS_LSB (1U << 0) /* 32b */
+/* PCM_STA (0x10006000+0x164) */
+#define PCM_CK_SEL_O_LSB (1U << 0) /* 4b */
+#define EXT_SRC_STA_LSB (1U << 4) /* 3b */
+/* SRC_REQ_STA_3 (0x10006000+0x168) */
+#define CCIF_EVENT_RAW_STATUS_LSB (1U << 0) /* 16b */
+#define F26M_STATE_LSB (1U << 16) /* 1b */
+#define INFRA_STATE_LSB (1U << 17) /* 1b */
+#define APSRC_STATE_LSB (1U << 18) /* 1b */
+#define VRF18_STATE_LSB (1U << 19) /* 1b */
+#define DDR_EN_STATE_LSB (1U << 20) /* 1b */
+#define DVFS_STATE_LSB (1U << 21) /* 1b */
+#define SW_MAILBOX_STATE_LSB (1U << 22) /* 1b */
+#define SSPM_MAILBOX_STATE_LSB (1U << 23) /* 1b */
+#define ADSP_MAILBOX_STATE_LSB (1U << 24) /* 1b */
+#define SCP_MAILBOX_STATE_LSB (1U << 25) /* 1b */
+/* PWR_STATUS (0x10006000+0x16C) */
+#define PWR_STATUS_LSB (1U << 0) /* 32b */
+/* PWR_STATUS_2ND (0x10006000+0x170) */
+#define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */
+/* CPU_PWR_STATUS (0x10006000+0x174) */
+#define MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 1) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 3) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 4) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 5) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 6) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 7) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 8) /* 1b */
+#define MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 9) /* 1b */
+/* OTHER_PWR_STATUS (0x10006000+0x178) */
+#define OTHER_PWR_STATUS_LSB (1U << 0) /* 32b */
+/* SPM_VTCXO_EVENT_COUNT_STA (0x10006000+0x17C) */
+#define SPM_VTCXO_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_VTCXO_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* SPM_INFRA_EVENT_COUNT_STA (0x10006000+0x180) */
+#define SPM_INFRA_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_INFRA_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* SPM_VRF18_EVENT_COUNT_STA (0x10006000+0x184) */
+#define SPM_VRF18_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_VRF18_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* SPM_APSRC_EVENT_COUNT_STA (0x10006000+0x188) */
+#define SPM_APSRC_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_APSRC_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* SPM_DDREN_EVENT_COUNT_STA (0x10006000+0x18C) */
+#define SPM_DDREN_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_DDREN_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* MD32PCM_STA (0x10006000+0x190) */
+#define MD32PCM_HALT_LSB (1U << 0) /* 1b */
+#define MD32PCM_GATED_LSB (1U << 1) /* 1b */
+/* MD32PCM_PC (0x10006000+0x194) */
+#define MON_PC_LSB (1U << 0) /* 32b */
+/* DVFSRC_EVENT_STA (0x10006000+0x1A4) */
+#define DVFSRC_EVENT_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT4_RDY (0x10006000+0x1A8) */
+#define PROTECT4_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT5_RDY (0x10006000+0x1AC) */
+#define PROTECT5_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT6_RDY (0x10006000+0x1B0) */
+#define PROTECT6_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT7_RDY (0x10006000+0x1B4) */
+#define PROTECT7_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT8_RDY (0x10006000+0x1B8) */
+#define PROTECT8_READY_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_LAST_STA0 (0x10006000+0x1D0) */
+#define LAST_IDLE_CNT_0_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_LAST_STA1 (0x10006000+0x1D4) */
+#define LAST_IDLE_CNT_1_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_LAST_STA2 (0x10006000+0x1D8) */
+#define LAST_IDLE_CNT_2_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_LAST_STA3 (0x10006000+0x1DC) */
+#define LAST_IDLE_CNT_3_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA0 (0x10006000+0x1E0) */
+#define CURRENT_IDLE_CNT_0_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA1 (0x10006000+0x1E4) */
+#define CURRENT_IDLE_CNT_1_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA2 (0x10006000+0x1E8) */
+#define CURRENT_IDLE_CNT_2_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA3 (0x10006000+0x1EC) */
+#define CURRENT_IDLE_CNT_3_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_TIMER_OUT (0x10006000+0x1F0) */
+#define TWAM_TIMER_LSB (1U << 0) /* 32b */
+/* SPM_CG_CHECK_STA (0x10006000+0x1F4) */
+#define SPM_CG_CHECK_SLEEP_REQ_0_LSB (1U << 0) /* 1b */
+#define SPM_CG_CHECK_SLEEP_REQ_1_LSB (1U << 1) /* 1b */
+#define SPM_CG_CHECK_SLEEP_REQ_2_LSB (1U << 2) /* 1b */
+/* SPM_DVFS_STA (0x10006000+0x1F8) */
+#define TARGET_DVFS_LEVEL_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_OPP_STA (0x10006000+0x1FC) */
+#define TARGET_DVFS_OPP_LSB (1U << 0) /* 5b */
+#define CURRENT_DVFS_OPP_LSB (1U << 5) /* 5b */
+#define RELAY_DVFS_OPP_LSB (1U << 10) /* 5b */
+/* SPM_MCUSYS_PWR_CON (0x10006000+0x200) */
+#define MCUSYS_SPMC_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MCUSYS_SPMC_PWR_ON_LSB (1U << 2) /* 1b */
+#define MCUSYS_SPMC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MCUSYS_SPMC_RESETPWRON_CONFIG_LSB (1U << 5) /* 1b */
+#define MCUSYS_SPMC_DORMANT_EN_LSB (1U << 6) /* 1b */
+#define MCUSYS_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */
+#define SPM_MCUSYS_PWR_CON_MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 31) /* 1b */
+/* SPM_CPUTOP_PWR_CON (0x10006000+0x204) */
+#define MP0_SPMC_PWR_RST_B_CPUTOP_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPUTOP_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_PWR_CLK_DIS_CPUTOP_LSB (1U << 4) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPUTOP_LSB (1U << 5) /* 1b */
+#define MP0_SPMC_DORMANT_EN_CPUTOP_LSB (1U << 6) /* 1b */
+#define MP0_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */
+#define MP0_VSRAM_EXT_OFF_LSB (1U << 8) /* 1b */
+#define SPM_CPUTOP_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 31) /* 1b */
+/* SPM_CPU0_PWR_CON (0x10006000+0x208) */
+#define MP0_SPMC_PWR_RST_B_CPU0_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU0_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU0_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU0_LSB (1U << 7) /* 1b */
+#define SPM_CPU0_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 31) /* 1b */
+/* SPM_CPU1_PWR_CON (0x10006000+0x20C) */
+#define MP0_SPMC_PWR_RST_B_CPU1_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU1_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU1_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU1_LSB (1U << 7) /* 1b */
+#define SPM_CPU1_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 31) /* 1b */
+/* SPM_CPU2_PWR_CON (0x10006000+0x210) */
+#define MP0_SPMC_PWR_RST_B_CPU2_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU2_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU2_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU2_LSB (1U << 7) /* 1b */
+#define SPM_CPU2_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 31) /* 1b */
+/* SPM_CPU3_PWR_CON (0x10006000+0x214) */
+#define MP0_SPMC_PWR_RST_B_CPU3_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU3_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU3_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU3_LSB (1U << 7) /* 1b */
+#define SPM_CPU3_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 31) /* 1b */
+/* SPM_CPU4_PWR_CON (0x10006000+0x218) */
+#define MP0_SPMC_PWR_RST_B_CPU4_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU4_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU4_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU4_LSB (1U << 7) /* 1b */
+#define SPM_CPU4_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 31) /* 1b */
+/* SPM_CPU5_PWR_CON (0x10006000+0x21C) */
+#define MP0_SPMC_PWR_RST_B_CPU5_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU5_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU5_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU5_LSB (1U << 7) /* 1b */
+#define SPM_CPU5_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 31) /* 1b */
+/* SPM_CPU6_PWR_CON (0x10006000+0x220) */
+#define MP0_SPMC_PWR_RST_B_CPU6_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU6_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU6_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU6_LSB (1U << 7) /* 1b */
+#define SPM_CPU6_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 31) /* 1b */
+/* SPM_CPU7_PWR_CON (0x10006000+0x224) */
+#define MP0_SPMC_PWR_RST_B_CPU7_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU7_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU7_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU7_LSB (1U << 7) /* 1b */
+#define SPM_CPU7_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 31) /* 1b */
+/* ARMPLL_CLK_CON (0x10006000+0x22C) */
+#define SC_ARM_FHC_PAUSE_LSB (1U << 0) /* 6b */
+#define SC_ARM_CK_OFF_LSB (1U << 6) /* 6b */
+#define SC_ARMPLL_OFF_LSB (1U << 12) /* 1b */
+#define SC_ARMBPLL_OFF_LSB (1U << 13) /* 1b */
+#define SC_ARMBPLL1_OFF_LSB (1U << 14) /* 1b */
+#define SC_ARMBPLL2_OFF_LSB (1U << 15) /* 1b */
+#define SC_ARMBPLL3_OFF_LSB (1U << 16) /* 1b */
+#define SC_CCIPLL_CKOFF_LSB (1U << 17) /* 1b */
+#define SC_ARMDDS_OFF_LSB (1U << 18) /* 1b */
+#define SC_ARMBPLL_S_OFF_LSB (1U << 19) /* 1b */
+#define SC_ARMBPLL1_S_OFF_LSB (1U << 20) /* 1b */
+#define SC_ARMBPLL2_S_OFF_LSB (1U << 21) /* 1b */
+#define SC_ARMBPLL3_S_OFF_LSB (1U << 22) /* 1b */
+#define SC_CCIPLL_PWROFF_LSB (1U << 23) /* 1b */
+#define SC_ARMPLLOUT_OFF_LSB (1U << 24) /* 1b */
+#define SC_ARMBPLLOUT_OFF_LSB (1U << 25) /* 1b */
+#define SC_ARMBPLLOUT1_OFF_LSB (1U << 26) /* 1b */
+#define SC_ARMBPLLOUT2_OFF_LSB (1U << 27) /* 1b */
+#define SC_ARMBPLLOUT3_OFF_LSB (1U << 28) /* 1b */
+#define SC_CCIPLL_OUT_OFF_LSB (1U << 29) /* 1b */
+/* MCUSYS_IDLE_STA (0x10006000+0x230) */
+#define ARMBUS_IDLE_TO_26M_LSB (1U << 0) /* 1b */
+#define MP0_CLUSTER_IDLE_TO_PWR_OFF_LSB (1U << 1) /* 1b */
+#define MCUSYS_DDR_EN_0_LSB (1U << 2) /* 1b */
+#define MCUSYS_DDR_EN_1_LSB (1U << 3) /* 1b */
+#define MCUSYS_DDR_EN_2_LSB (1U << 4) /* 1b */
+#define MCUSYS_DDR_EN_3_LSB (1U << 5) /* 1b */
+#define MCUSYS_DDR_EN_4_LSB (1U << 6) /* 1b */
+#define MCUSYS_DDR_EN_5_LSB (1U << 7) /* 1b */
+#define MCUSYS_DDR_EN_6_LSB (1U << 8) /* 1b */
+#define MCUSYS_DDR_EN_7_LSB (1U << 9) /* 1b */
+#define MP0_CPU_IDLE_TO_PWR_OFF_LSB (1U << 16) /* 8b */
+#define WFI_AF_SEL_LSB (1U << 24) /* 8b */
+/* GIC_WAKEUP_STA (0x10006000+0x234) */
+#define GIC_WAKEUP_STA_GIC_WAKEUP_LSB (1U << 10) /* 10b */
+/* CPU_SPARE_CON (0x10006000+0x238) */
+#define CPU_SPARE_CON_LSB (1U << 0) /* 32b */
+/* CPU_SPARE_CON_SET (0x10006000+0x23C) */
+#define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */
+/* CPU_SPARE_CON_CLR (0x10006000+0x240) */
+#define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */
+/* ARMPLL_CLK_SEL (0x10006000+0x244) */
+#define ARMPLL_CLK_SEL_LSB (1U << 0) /* 15b */
+/* EXT_INT_WAKEUP_REQ (0x10006000+0x248) */
+#define EXT_INT_WAKEUP_REQ_LSB (1U << 0) /* 10b */
+/* EXT_INT_WAKEUP_REQ_SET (0x10006000+0x24C) */
+#define EXT_INT_WAKEUP_REQ_SET_LSB (1U << 0) /* 10b */
+/* EXT_INT_WAKEUP_REQ_CLR (0x10006000+0x250) */
+#define EXT_INT_WAKEUP_REQ_CLR_LSB (1U << 0) /* 10b */
+/* MP0_CPU0_IRQ_MASK (0x10006000+0x260) */
+#define MP0_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU0_AUX_LSB (1U << 8) /* 11b */
+/* MP0_CPU1_IRQ_MASK (0x10006000+0x264) */
+#define MP0_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU1_AUX_LSB (1U << 8) /* 11b */
+/* MP0_CPU2_IRQ_MASK (0x10006000+0x268) */
+#define MP0_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU2_AUX_LSB (1U << 8) /* 11b */
+/* MP0_CPU3_IRQ_MASK (0x10006000+0x26C) */
+#define MP0_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU3_AUX_LSB (1U << 8) /* 11b */
+/* MP1_CPU0_IRQ_MASK (0x10006000+0x270) */
+#define MP1_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU0_AUX_LSB (1U << 8) /* 11b */
+/* MP1_CPU1_IRQ_MASK (0x10006000+0x274) */
+#define MP1_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU1_AUX_LSB (1U << 8) /* 11b */
+/* MP1_CPU2_IRQ_MASK (0x10006000+0x278) */
+#define MP1_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU2_AUX_LSB (1U << 8) /* 11b */
+/* MP1_CPU3_IRQ_MASK (0x10006000+0x27C) */
+#define MP1_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU3_AUX_LSB (1U << 8) /* 11b */
+/* MP0_CPU0_WFI_EN (0x10006000+0x280) */
+#define MP0_CPU0_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU1_WFI_EN (0x10006000+0x284) */
+#define MP0_CPU1_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU2_WFI_EN (0x10006000+0x288) */
+#define MP0_CPU2_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU3_WFI_EN (0x10006000+0x28C) */
+#define MP0_CPU3_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU4_WFI_EN (0x10006000+0x290) */
+#define MP0_CPU4_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU5_WFI_EN (0x10006000+0x294) */
+#define MP0_CPU5_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU6_WFI_EN (0x10006000+0x298) */
+#define MP0_CPU6_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU7_WFI_EN (0x10006000+0x29C) */
+#define MP0_CPU7_WFI_EN_LSB (1U << 0) /* 1b */
+/* ROOT_CPUTOP_ADDR (0x10006000+0x2A0) */
+#define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */
+/* ROOT_CORE_ADDR (0x10006000+0x2A4) */
+#define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */
+/* SPM2SW_MAILBOX_0 (0x10006000+0x2D0) */
+#define SPM2SW_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* SPM2SW_MAILBOX_1 (0x10006000+0x2D4) */
+#define SPM2SW_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* SPM2SW_MAILBOX_2 (0x10006000+0x2D8) */
+#define SPM2SW_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* SPM2SW_MAILBOX_3 (0x10006000+0x2DC) */
+#define SPM2SW_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* SW2SPM_INT (0x10006000+0x2E0) */
+#define SW2SPM_INT_SW2SPM_INT_LSB (1U << 0) /* 4b */
+/* SW2SPM_INT_SET (0x10006000+0x2E4) */
+#define SW2SPM_INT_SET_LSB (1U << 0) /* 4b */
+/* SW2SPM_INT_CLR (0x10006000+0x2E8) */
+#define SW2SPM_INT_CLR_LSB (1U << 0) /* 4b */
+/* SW2SPM_MAILBOX_0 (0x10006000+0x2EC) */
+#define SW2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* SW2SPM_MAILBOX_1 (0x10006000+0x2F0) */
+#define SW2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* SW2SPM_MAILBOX_2 (0x10006000+0x2F4) */
+#define SW2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* SW2SPM_MAILBOX_3 (0x10006000+0x2F8) */
+#define SW2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* SW2SPM_CFG (0x10006000+0x2FC) */
+#define SWU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */
+/* MD1_PWR_CON (0x10006000+0x300) */
+#define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MD1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MD1_PWR_ON_LSB (1U << 2) /* 1b */
+#define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MD1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* CONN_PWR_CON (0x10006000+0x304) */
+#define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CONN_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CONN_PWR_ON_LSB (1U << 2) /* 1b */
+#define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+/* MFG0_PWR_CON (0x10006000+0x308) */
+#define MFG0_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG0_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG0_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG0_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG0_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG0_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG1_PWR_CON (0x10006000+0x30C) */
+#define MFG1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG1_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG1_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG2_PWR_CON (0x10006000+0x310) */
+#define MFG2_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG2_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG2_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG2_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG3_PWR_CON (0x10006000+0x314) */
+#define MFG3_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG3_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG3_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG3_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG3_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG3_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG4_PWR_CON (0x10006000+0x318) */
+#define MFG4_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG4_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG4_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG4_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG4_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG4_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG4_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG5_PWR_CON (0x10006000+0x31C) */
+#define MFG5_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG5_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG5_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG5_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG5_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG5_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG5_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG6_PWR_CON (0x10006000+0x320) */
+#define MFG6_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG6_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG6_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG6_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG6_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG6_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG6_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* IFR_PWR_CON (0x10006000+0x324) */
+#define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define IFR_PWR_ISO_LSB (1U << 1) /* 1b */
+#define IFR_PWR_ON_LSB (1U << 2) /* 1b */
+#define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define IFR_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* IFR_SUB_PWR_CON (0x10006000+0x328) */
+#define IFR_SUB_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define IFR_SUB_PWR_ISO_LSB (1U << 1) /* 1b */
+#define IFR_SUB_PWR_ON_LSB (1U << 2) /* 1b */
+#define IFR_SUB_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define IFR_SUB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define IFR_SUB_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_IFR_SUB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* DPY_PWR_CON (0x10006000+0x32C) */
+#define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DPY_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DPY_PWR_ON_LSB (1U << 2) /* 1b */
+#define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define DPY_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* ISP_PWR_CON (0x10006000+0x330) */
+#define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define ISP_PWR_ISO_LSB (1U << 1) /* 1b */
+#define ISP_PWR_ON_LSB (1U << 2) /* 1b */
+#define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define ISP_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* ISP2_PWR_CON (0x10006000+0x334) */
+#define ISP2_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define ISP2_PWR_ISO_LSB (1U << 1) /* 1b */
+#define ISP2_PWR_ON_LSB (1U << 2) /* 1b */
+#define ISP2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define ISP2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define ISP2_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_ISP2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* IPE_PWR_CON (0x10006000+0x338) */
+#define IPE_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define IPE_PWR_ISO_LSB (1U << 1) /* 1b */
+#define IPE_PWR_ON_LSB (1U << 2) /* 1b */
+#define IPE_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define IPE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define IPE_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_IPE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* VDE_PWR_CON (0x10006000+0x33C) */
+#define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VDE_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VDE_PWR_ON_LSB (1U << 2) /* 1b */
+#define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VDE_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* VDE2_PWR_CON (0x10006000+0x340) */
+#define VDE2_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VDE2_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VDE2_PWR_ON_LSB (1U << 2) /* 1b */
+#define VDE2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define VDE2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VDE2_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_VDE2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* VEN_PWR_CON (0x10006000+0x344) */
+#define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VEN_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VEN_PWR_ON_LSB (1U << 2) /* 1b */
+#define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VEN_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* VEN_CORE1_PWR_CON (0x10006000+0x348) */
+#define VEN_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VEN_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VEN_CORE1_PWR_ON_LSB (1U << 2) /* 1b */
+#define VEN_CORE1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define VEN_CORE1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VEN_CORE1_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_VEN_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MDP_PWR_CON (0x10006000+0x34C) */
+#define MDP_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MDP_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MDP_PWR_ON_LSB (1U << 2) /* 1b */
+#define MDP_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MDP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MDP_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MDP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* DIS_PWR_CON (0x10006000+0x350) */
+#define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DIS_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DIS_PWR_ON_LSB (1U << 2) /* 1b */
+#define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define DIS_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* AUDIO_PWR_CON (0x10006000+0x354) */
+#define AUDIO_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define AUDIO_PWR_ISO_LSB (1U << 1) /* 1b */
+#define AUDIO_PWR_ON_LSB (1U << 2) /* 1b */
+#define AUDIO_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define AUDIO_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define AUDIO_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_AUDIO_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* ADSP_PWR_CON (0x10006000+0x358) */
+#define ADSP_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define ADSP_PWR_ISO_LSB (1U << 1) /* 1b */
+#define ADSP_PWR_ON_LSB (1U << 2) /* 1b */
+#define ADSP_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define ADSP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define ADSP_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define ADSP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define ADSP_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define ADSP_SRAM_SLEEP_B_LSB (1U << 9) /* 1b */
+#define SC_ADSP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+#define SC_ADSP_SRAM_SLEEP_B_ACK_LSB (1U << 13) /* 1b */
+/* CAM_PWR_CON (0x10006000+0x35C) */
+#define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CAM_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CAM_PWR_ON_LSB (1U << 2) /* 1b */
+#define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define CAM_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* CAM_RAWA_PWR_CON (0x10006000+0x360) */
+#define CAM_RAWA_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CAM_RAWA_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CAM_RAWA_PWR_ON_LSB (1U << 2) /* 1b */
+#define CAM_RAWA_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CAM_RAWA_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define CAM_RAWA_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_CAM_RAWA_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* CAM_RAWB_PWR_CON (0x10006000+0x364) */
+#define CAM_RAWB_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CAM_RAWB_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CAM_RAWB_PWR_ON_LSB (1U << 2) /* 1b */
+#define CAM_RAWB_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CAM_RAWB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define CAM_RAWB_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_CAM_RAWB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* CAM_RAWC_PWR_CON (0x10006000+0x368) */
+#define CAM_RAWC_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CAM_RAWC_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CAM_RAWC_PWR_ON_LSB (1U << 2) /* 1b */
+#define CAM_RAWC_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CAM_RAWC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define CAM_RAWC_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_CAM_RAWC_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* SYSRAM_CON (0x10006000+0x36C) */
+#define SYSRAM_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define SYSRAM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define SYSRAM_SRAM_SLEEP_B_LSB (1U << 4) /* 4b */
+#define SYSRAM_SRAM_PDN_LSB (1U << 16) /* 4b */
+/* SYSROM_CON (0x10006000+0x370) */
+#define SYSROM_SRAM_PDN_LSB (1U << 0) /* 6b */
+/* SSPM_SRAM_CON (0x10006000+0x374) */
+#define SSPM_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define SSPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define SSPM_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define SSPM_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* SCP_SRAM_CON (0x10006000+0x378) */
+#define SCP_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define SCP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define SCP_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* DPY_SHU_SRAM_CON (0x10006000+0x37C) */
+#define DPY_SHU_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DPY_SHU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DPY_SHU_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */
+#define DPY_SHU_SRAM_PDN_LSB (1U << 16) /* 2b */
+/* UFS_SRAM_CON (0x10006000+0x380) */
+#define UFS_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define UFS_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define UFS_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */
+#define UFS_SRAM_PDN_LSB (1U << 16) /* 5b */
+/* DEVAPC_IFR_SRAM_CON (0x10006000+0x384) */
+#define DEVAPC_IFR_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DEVAPC_IFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DEVAPC_IFR_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */
+#define DEVAPC_IFR_SRAM_PDN_LSB (1U << 16) /* 6b */
+/* DEVAPC_SUBIFR_SRAM_CON (0x10006000+0x388) */
+#define DEVAPC_SUBIFR_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DEVAPC_SUBIFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DEVAPC_SUBIFR_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */
+#define DEVAPC_SUBIFR_SRAM_PDN_LSB (1U << 16) /* 6b */
+/* DEVAPC_ACP_SRAM_CON (0x10006000+0x38C) */
+#define DEVAPC_ACP_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DEVAPC_ACP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DEVAPC_ACP_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */
+#define DEVAPC_ACP_SRAM_PDN_LSB (1U << 16) /* 6b */
+/* USB_SRAM_CON (0x10006000+0x390) */
+#define USB_SRAM_PDN_LSB (1U << 0) /* 7b */
+/* DUMMY_SRAM_CON (0x10006000+0x394) */
+#define DUMMY_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DUMMY_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DUMMY_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */
+#define DUMMY_SRAM_PDN_LSB (1U << 16) /* 8b */
+/* MD_EXT_BUCK_ISO_CON (0x10006000+0x398) */
+#define VMODEM_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */
+#define VMD_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */
+/* EXT_BUCK_ISO (0x10006000+0x39C) */
+#define VIMVO_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */
+#define GPU_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */
+#define ADSP_EXT_BUCK_ISO_LSB (1U << 2) /* 1b */
+#define IPU_EXT_BUCK_ISO_LSB (1U << 5) /* 3b */
+/* DXCC_SRAM_CON (0x10006000+0x3A0) */
+#define DXCC_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DXCC_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DXCC_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define DXCC_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* MSDC_SRAM_CON (0x10006000+0x3A4) */
+#define MSDC_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MSDC_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MSDC_PWR_ON_LSB (1U << 2) /* 1b */
+#define MSDC_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MSDC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MSDC_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MSDC_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MSDC_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MSDC_SRAM_SLEEP_B_LSB (1U << 9) /* 1b */
+#define SC_MSDC_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+#define SC_MSDC_SRAM_SLEEP_B_ACK_LSB (1U << 13) /* 1b */
+/* DEBUGTOP_SRAM_CON (0x10006000+0x3A8) */
+#define DEBUGTOP_SRAM_PDN_LSB (1U << 0) /* 1b */
+/* DP_TX_PWR_CON (0x10006000+0x3AC) */
+#define DP_TX_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DP_TX_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DP_TX_PWR_ON_LSB (1U << 2) /* 1b */
+#define DP_TX_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DP_TX_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define DP_TX_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_DP_TX_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* DPMAIF_SRAM_CON (0x10006000+0x3B0) */
+#define DPMAIF_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DPMAIF_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DPMAIF_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define DPMAIF_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* DPY_SHU2_SRAM_CON (0x10006000+0x3B4) */
+#define DPY_SHU2_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DPY_SHU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DPY_SHU2_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */
+#define DPY_SHU2_SRAM_PDN_LSB (1U << 16) /* 2b */
+/* DRAMC_MCU2_SRAM_CON (0x10006000+0x3B8) */
+#define DRAMC_MCU2_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DRAMC_MCU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DRAMC_MCU2_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define DRAMC_MCU2_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* DRAMC_MCU_SRAM_CON (0x10006000+0x3BC) */
+#define DRAMC_MCU_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DRAMC_MCU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DRAMC_MCU_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define DRAMC_MCU_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* MCUPM_SRAM_CON (0x10006000+0x3C0) */
+#define MCUPM_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MCUPM_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MCUPM_PWR_ON_LSB (1U << 2) /* 1b */
+#define MCUPM_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MCUPM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MCUPM_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define MCUPM_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define MCUPM_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define MCUPM_SRAM_SLEEP_B_LSB (1U << 9) /* 1b */
+#define SC_MCUPM_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+#define SC_MCUPM_SRAM_SLEEP_B_ACK_LSB (1U << 13) /* 1b */
+/* DPY2_PWR_CON (0x10006000+0x3C4) */
+#define DPY2_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DPY2_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DPY2_PWR_ON_LSB (1U << 2) /* 1b */
+#define DPY2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DPY2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define DPY2_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_DPY2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* PERI_PWR_CON (0x10006000+0x3C8) */
+#define PERI_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define PERI_PWR_ISO_LSB (1U << 1) /* 1b */
+#define PERI_PWR_ON_LSB (1U << 2) /* 1b */
+#define PERI_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define PERI_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define PERI_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_PERI_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* SPM_MEM_CK_SEL (0x10006000+0x400) */
+#define SC_MEM_CK_SEL_LSB (1U << 0) /* 1b */
+#define SPM2CKSYS_MEM_CK_MUX_UPDATE_LSB (1U << 1) /* 1b */
+/* SPM_BUS_PROTECT_MASK_B (0x10006000+0X404) */
+#define SPM_BUS_PROTECT_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT1_MASK_B (0x10006000+0x408) */
+#define SPM_BUS_PROTECT1_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT2_MASK_B (0x10006000+0x40C) */
+#define SPM_BUS_PROTECT2_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT3_MASK_B (0x10006000+0x410) */
+#define SPM_BUS_PROTECT3_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT4_MASK_B (0x10006000+0x414) */
+#define SPM_BUS_PROTECT4_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_EMI_BW_MODE (0x10006000+0x418) */
+#define EMI_BW_MODE_LSB (1U << 0) /* 1b */
+#define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */
+#define EMI_BW_MODE_2_LSB (1U << 2) /* 1b */
+#define EMI_BOOST_MODE_2_LSB (1U << 3) /* 1b */
+/* AP2MD_PEER_WAKEUP (0x10006000+0x41C) */
+#define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */
+/* ULPOSC_CON (0x10006000+0x420) */
+#define ULPOSC_EN_LSB (1U << 0) /* 1b */
+#define ULPOSC_RST_LSB (1U << 1) /* 1b */
+#define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */
+#define ULPOSC_CLK_SEL_LSB (1U << 3) /* 1b */
+/* SPM2MM_CON (0x10006000+0x424) */
+#define SPM2MM_FORCE_ULTRA_LSB (1U << 0) /* 1b */
+#define SPM2MM_DBL_OSTD_ACT_LSB (1U << 1) /* 1b */
+#define SPM2MM_ULTRAREQ_LSB (1U << 2) /* 1b */
+#define SPM2MD_ULTRAREQ_LSB (1U << 3) /* 1b */
+#define SPM2ISP_ULTRAREQ_LSB (1U << 4) /* 1b */
+#define MM2SPM_FORCE_ULTRA_ACK_D2T_LSB (1U << 16) /* 1b */
+#define MM2SPM_DBL_OSTD_ACT_ACK_D2T_LSB (1U << 17) /* 1b */
+#define SPM2ISP_ULTRAACK_D2T_LSB (1U << 18) /* 1b */
+#define SPM2MM_ULTRAACK_D2T_LSB (1U << 19) /* 1b */
+#define SPM2MD_ULTRAACK_D2T_LSB (1U << 20) /* 1b */
+/* SPM_BUS_PROTECT5_MASK_B (0x10006000+0x428) */
+#define SPM_BUS_PROTECT5_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM2MCUPM_CON (0x10006000+0x42C) */
+#define SPM2MCUPM_SW_RST_B_LSB (1U << 0) /* 1b */
+#define SPM2MCUPM_SW_INT_LSB (1U << 1) /* 1b */
+/* AP_MDSRC_REQ (0x10006000+0x430) */
+#define AP_MDSMSRC_REQ_LSB (1U << 0) /* 1b */
+#define AP_L1SMSRC_REQ_LSB (1U << 1) /* 1b */
+#define AP_MD2SRC_REQ_LSB (1U << 2) /* 1b */
+#define AP_MDSMSRC_ACK_LSB (1U << 4) /* 1b */
+#define AP_L1SMSRC_ACK_LSB (1U << 5) /* 1b */
+#define AP_MD2SRC_ACK_LSB (1U << 6) /* 1b */
+/* SPM2EMI_ENTER_ULPM (0x10006000+0x434) */
+#define SPM2EMI_ENTER_ULPM_LSB (1U << 0) /* 1b */
+/* SPM2MD_DVFS_CON (0x10006000+0x438) */
+#define SPM2MD_DVFS_CON_LSB (1U << 0) /* 32b */
+/* MD2SPM_DVFS_CON (0x10006000+0x43C) */
+#define MD2SPM_DVFS_CON_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT6_MASK_B (0x10006000+0X440) */
+#define SPM_BUS_PROTECT6_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT7_MASK_B (0x10006000+0x444) */
+#define SPM_BUS_PROTECT7_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT8_MASK_B (0x10006000+0x448) */
+#define SPM_BUS_PROTECT8_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_PLL_CON (0x10006000+0x44C) */
+#define SC_MAINPLLOUT_OFF_LSB (1U << 0) /* 1b */
+#define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */
+#define SC_MAINPLL_OFF_LSB (1U << 4) /* 1b */
+#define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */
+#define SC_MAINPLL_S_OFF_LSB (1U << 8) /* 1b */
+#define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */
+#define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */
+#define SC_MD32K_CK_OFF_LSB (1U << 17) /* 1b */
+#define SC_CKSQ1_OFF_LSB (1U << 18) /* 1b */
+#define SC_AXI_MEM_CK_OFF_LSB (1U << 19) /* 1b */
+/* CPU_DVFS_REQ (0x10006000+0x450) */
+#define CPU_DVFS_REQ_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_SW_CON_0 (0x10006000+0x454) */
+#define SW_DDR_PST_REQ_LSB (1U << 0) /* 2b */
+#define SW_DDR_PST_ABORT_REQ_LSB (1U << 2) /* 2b */
+/* SPM_DRAM_MCU_SW_CON_1 (0x10006000+0x458) */
+#define SW_DDR_PST_CH0_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_SW_CON_2 (0x10006000+0x45C) */
+#define SW_DDR_PST_CH1_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_SW_CON_3 (0x10006000+0x460) */
+#define SW_DDR_RESERVED_CH0_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_SW_CON_4 (0x10006000+0x464) */
+#define SW_DDR_RESERVED_CH1_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_STA_0 (0x10006000+0x468) */
+#define SC_DDR_PST_ACK_LSB (1U << 0) /* 2b */
+#define SC_DDR_PST_ABORT_ACK_LSB (1U << 2) /* 2b */
+/* SPM_DRAM_MCU_STA_1 (0x10006000+0x46C) */
+#define SC_DDR_CUR_PST_STA_CH0_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_STA_2 (0x10006000+0x470) */
+#define SC_DDR_CUR_PST_STA_CH1_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_SW_SEL_0 (0x10006000+0x474) */
+#define SW_DDR_PST_REQ_SEL_LSB (1U << 0) /* 2b */
+#define SW_DDR_PST_SEL_LSB (1U << 2) /* 2b */
+#define SW_DDR_PST_ABORT_REQ_SEL_LSB (1U << 4) /* 2b */
+#define SW_DDR_RESERVED_SEL_LSB (1U << 6) /* 2b */
+#define SW_DDR_PST_ACK_SEL_LSB (1U << 8) /* 2b */
+#define SW_DDR_PST_ABORT_ACK_SEL_LSB (1U << 10) /* 2b */
+/* RELAY_DVFS_LEVEL (0x10006000+0x478) */
+#define RELAY_DVFS_LEVEL_LSB (1U << 0) /* 32b */
+/* DRAMC_DPY_CLK_SW_CON_0 (0x10006000+0x480) */
+#define SW_PHYPLL_EN_LSB (1U << 0) /* 2b */
+#define SW_DPY_VREF_EN_LSB (1U << 2) /* 2b */
+#define SW_DPY_DLL_CK_EN_LSB (1U << 4) /* 2b */
+#define SW_DPY_DLL_EN_LSB (1U << 6) /* 2b */
+#define SW_DPY_2ND_DLL_EN_LSB (1U << 8) /* 2b */
+#define SW_MEM_CK_OFF_LSB (1U << 10) /* 2b */
+#define SW_DMSUS_OFF_LSB (1U << 12) /* 2b */
+#define SW_DPY_MODE_SW_LSB (1U << 14) /* 2b */
+#define SW_EMI_CLK_OFF_LSB (1U << 16) /* 2b */
+#define SW_DDRPHY_FB_CK_EN_LSB (1U << 18) /* 2b */
+#define SW_DR_GATE_RETRY_EN_LSB (1U << 20) /* 2b */
+#define SW_DPHY_PRECAL_UP_LSB (1U << 24) /* 2b */
+#define SW_DPY_BCLK_ENABLE_LSB (1U << 26) /* 2b */
+#define SW_TX_TRACKING_DIS_LSB (1U << 28) /* 2b */
+#define SW_DPHY_RXDLY_TRACKING_EN_LSB (1U << 30) /* 2b */
+/* DRAMC_DPY_CLK_SW_CON_1 (0x10006000+0x484) */
+#define SW_SHU_RESTORE_LSB (1U << 0) /* 2b */
+#define SW_DMYRD_MOD_LSB (1U << 2) /* 2b */
+#define SW_DMYRD_INTV_LSB (1U << 4) /* 2b */
+#define SW_DMYRD_EN_LSB (1U << 6) /* 2b */
+#define SW_DRS_DIS_REQ_LSB (1U << 8) /* 2b */
+#define SW_DR_SRAM_LOAD_LSB (1U << 10) /* 2b */
+#define SW_DR_SRAM_RESTORE_LSB (1U << 12) /* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_LATCH_LSB (1U << 14) /* 2b */
+#define SW_TX_TRACK_RETRY_EN_LSB (1U << 16) /* 2b */
+#define SW_DPY_MIDPI_EN_LSB (1U << 18) /* 2b */
+#define SW_DPY_PI_RESETB_EN_LSB (1U << 20) /* 2b */
+#define SW_DPY_MCK8X_EN_LSB (1U << 22) /* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_CH0_LSB (1U << 24) /* 4b */
+#define SW_DR_SHU_LEVEL_SRAM_CH1_LSB (1U << 28) /* 4b */
+/* DRAMC_DPY_CLK_SW_CON_2 (0x10006000+0x488) */
+#define SW_DR_SHU_LEVEL_LSB (1U << 0) /* 2b */
+#define SW_DR_SHU_EN_LSB (1U << 2) /* 1b */
+#define SW_DR_SHORT_QUEUE_LSB (1U << 3) /* 1b */
+#define SW_PHYPLL_MODE_SW_LSB (1U << 4) /* 1b */
+#define SW_PHYPLL2_MODE_SW_LSB (1U << 5) /* 1b */
+#define SW_PHYPLL_SHU_EN_LSB (1U << 6) /* 1b */
+#define SW_PHYPLL2_SHU_EN_LSB (1U << 7) /* 1b */
+#define SW_DR_RESERVED_0_LSB (1U << 24) /* 2b */
+#define SW_DR_RESERVED_1_LSB (1U << 26) /* 2b */
+#define SW_DR_RESERVED_2_LSB (1U << 28) /* 2b */
+#define SW_DR_RESERVED_3_LSB (1U << 30) /* 2b */
+/* DRAMC_DPY_CLK_SW_CON_3 (0x10006000+0x48C) */
+#define SC_DR_SHU_EN_ACK_LSB (1U << 0) /* 4b */
+#define SC_EMI_CLK_OFF_ACK_LSB (1U << 4) /* 4b */
+#define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 8) /* 4b */
+#define SC_DRAMC_DFS_STA_LSB (1U << 12) /* 4b */
+#define SC_DRS_DIS_ACK_LSB (1U << 16) /* 4b */
+#define SC_DR_SRAM_LOAD_ACK_LSB (1U << 20) /* 4b */
+#define SC_DR_SRAM_PLL_LOAD_ACK_LSB (1U << 24) /* 4b */
+#define SC_DR_SRAM_RESTORE_ACK_LSB (1U << 28) /* 4b */
+/* DRAMC_DPY_CLK_SW_SEL_0 (0x10006000+0x490) */
+#define SW_PHYPLL_EN_SEL_LSB (1U << 0) /* 2b */
+#define SW_DPY_VREF_EN_SEL_LSB (1U << 2) /* 2b */
+#define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 4) /* 2b */
+#define SW_DPY_DLL_EN_SEL_LSB (1U << 6) /* 2b */
+#define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 8) /* 2b */
+#define SW_MEM_CK_OFF_SEL_LSB (1U << 10) /* 2b */
+#define SW_DMSUS_OFF_SEL_LSB (1U << 12) /* 2b */
+#define SW_DPY_MODE_SW_SEL_LSB (1U << 14) /* 2b */
+#define SW_EMI_CLK_OFF_SEL_LSB (1U << 16) /* 2b */
+#define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 18) /* 2b */
+#define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 20) /* 2b */
+#define SW_DPHY_PRECAL_UP_SEL_LSB (1U << 24) /* 2b */
+#define SW_DPY_BCLK_ENABLE_SEL_LSB (1U << 26) /* 2b */
+#define SW_TX_TRACKING_DIS_SEL_LSB (1U << 28) /* 2b */
+#define SW_DPHY_RXDLY_TRACKING_EN_SEL_LSB (1U << 30) /* 2b */
+/* DRAMC_DPY_CLK_SW_SEL_1 (0x10006000+0x494) */
+#define SW_SHU_RESTORE_SEL_LSB (1U << 0) /* 2b */
+#define SW_DMYRD_MOD_SEL_LSB (1U << 2) /* 2b */
+#define SW_DMYRD_INTV_SEL_LSB (1U << 4) /* 2b */
+#define SW_DMYRD_EN_SEL_LSB (1U << 6) /* 2b */
+#define SW_DRS_DIS_REQ_SEL_LSB (1U << 8) /* 2b */
+#define SW_DR_SRAM_LOAD_SEL_LSB (1U << 10) /* 2b */
+#define SW_DR_SRAM_RESTORE_SEL_LSB (1U << 12) /* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_LATCH_SEL_LSB (1U << 14) /* 2b */
+#define SW_TX_TRACK_RETRY_EN_SEL_LSB (1U << 16) /* 2b */
+#define SW_DPY_MIDPI_EN_SEL_LSB (1U << 18) /* 2b */
+#define SW_DPY_PI_RESETB_EN_SEL_LSB (1U << 20) /* 2b */
+#define SW_DPY_MCK8X_EN_SEL_LSB (1U << 22) /* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_SEL_LSB (1U << 24) /* 2b */
+/* DRAMC_DPY_CLK_SW_SEL_2 (0x10006000+0x498) */
+#define SW_DR_SHU_LEVEL_SEL_LSB (1U << 0) /* 1b */
+#define SW_DR_SHU_EN_SEL_LSB (1U << 2) /* 1b */
+#define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 3) /* 1b */
+#define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 4) /* 1b */
+#define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 5) /* 1b */
+#define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 6) /* 1b */
+#define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 7) /* 1b */
+#define SW_DR_RESERVED_0_SEL_LSB (1U << 24) /* 2b */
+#define SW_DR_RESERVED_1_SEL_LSB (1U << 26) /* 2b */
+#define SW_DR_RESERVED_2_SEL_LSB (1U << 28) /* 2b */
+#define SW_DR_RESERVED_3_SEL_LSB (1U << 30) /* 2b */
+/* DRAMC_DPY_CLK_SW_SEL_3 (0x10006000+0x49C) */
+#define SC_DR_SHU_EN_ACK_SEL_LSB (1U << 0) /* 4b */
+#define SC_EMI_CLK_OFF_ACK_SEL_LSB (1U << 4) /* 4b */
+#define SC_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 8) /* 4b */
+#define SC_DRAMC_DFS_STA_SEL_LSB (1U << 12) /* 4b */
+#define SC_DRS_DIS_ACK_SEL_LSB (1U << 16) /* 4b */
+#define SC_DR_SRAM_LOAD_ACK_SEL_LSB (1U << 20) /* 4b */
+#define SC_DR_SRAM_PLL_LOAD_ACK_SEL_LSB (1U << 24) /* 4b */
+#define SC_DR_SRAM_RESTORE_ACK_SEL_LSB (1U << 28) /* 4b */
+/* DRAMC_DPY_CLK_SPM_CON (0x10006000+0x4A0) */
+#define SC_DMYRD_EN_MOD_SEL_PCM_LSB (1U << 0) /* 1b */
+#define SC_DMYRD_INTV_SEL_PCM_LSB (1U << 1) /* 1b */
+#define SC_DMYRD_EN_PCM_LSB (1U << 2) /* 1b */
+#define SC_DRS_DIS_REQ_PCM_LSB (1U << 3) /* 1b */
+#define SC_DR_SHU_LEVEL_SRAM_PCM_LSB (1U << 4) /* 4b */
+#define SC_DR_GATE_RETRY_EN_PCM_LSB (1U << 8) /* 1b */
+#define SC_DR_SHORT_QUEUE_PCM_LSB (1U << 9) /* 1b */
+#define SC_DPY_MIDPI_EN_PCM_LSB (1U << 10) /* 1b */
+#define SC_DPY_PI_RESETB_EN_PCM_LSB (1U << 11) /* 1b */
+#define SC_DPY_MCK8X_EN_PCM_LSB (1U << 12) /* 1b */
+#define SC_DR_RESERVED_0_PCM_LSB (1U << 13) /* 1b */
+#define SC_DR_RESERVED_1_PCM_LSB (1U << 14) /* 1b */
+#define SC_DR_RESERVED_2_PCM_LSB (1U << 15) /* 1b */
+#define SC_DR_RESERVED_3_PCM_LSB (1U << 16) /* 1b */
+#define SC_DMDRAMCSHU_ACK_ALL_LSB (1U << 24) /* 1b */
+#define SC_EMI_CLK_OFF_ACK_ALL_LSB (1U << 25) /* 1b */
+#define SC_DR_SHORT_QUEUE_ACK_ALL_LSB (1U << 26) /* 1b */
+#define SC_DRAMC_DFS_STA_ALL_LSB (1U << 27) /* 1b */
+#define SC_DRS_DIS_ACK_ALL_LSB (1U << 28) /* 1b */
+#define SC_DR_SRAM_LOAD_ACK_ALL_LSB (1U << 29) /* 1b */
+#define SC_DR_SRAM_PLL_LOAD_ACK_ALL_LSB (1U << 30) /* 1b */
+#define SC_DR_SRAM_RESTORE_ACK_ALL_LSB (1U << 31) /* 1b */
+/* SPM_DVFS_LEVEL (0x10006000+0x4A4) */
+#define SPM_DVFS_LEVEL_LSB (1U << 0) /* 32b */
+/* SPM_CIRQ_CON (0x10006000+0x4A8) */
+#define CIRQ_CLK_SEL_LSB (1U << 0) /* 1b */
+/* SPM_DVFS_MISC (0x10006000+0x4AC) */
+#define MSDC_DVFS_REQUEST_LSB (1U << 0) /* 1b */
+#define SPM2EMI_SLP_PROT_EN_LSB (1U << 1) /* 1b */
+#define SPM_DVFS_FORCE_ENABLE_LSB (1U << 2) /* 1b */
+#define FORCE_DVFS_WAKE_LSB (1U << 3) /* 1b */
+#define SPM_DVFSRC_ENABLE_LSB (1U << 4) /* 1b */
+#define SPM_DVFS_DONE_LSB (1U << 5) /* 1b */
+#define DVFSRC_IRQ_WAKEUP_EVENT_MASK_LSB (1U << 6) /* 1b */
+#define SPM2RC_EVENT_ABORT_LSB (1U << 7) /* 1b */
+#define EMI_SLP_IDLE_LSB (1U << 14) /* 1b */
+#define SDIO_READY_TO_SPM_LSB (1U << 15) /* 1b */
+/* SPM_VS1_VS2_RC_CON (0x10006000+0x4B0) */
+#define VS1_INIT_LEVEL_LSB (1U << 0) /* 2b */
+#define VS1_INIT_LSB (1U << 2) /* 1b */
+#define VS1_CURR_LEVEL_LSB (1U << 3) /* 2b */
+#define VS1_NEXT_LEVEL_LSB (1U << 5) /* 2b */
+#define VS1_VOTE_LEVEL_LSB (1U << 7) /* 2b */
+#define VS1_TRIGGER_LSB (1U << 9) /* 1b */
+#define VS2_INIT_LEVEL_LSB (1U << 10) /* 3b */
+#define VS2_INIT_LSB (1U << 13) /* 1b */
+#define VS2_CURR_LEVEL_LSB (1U << 14) /* 3b */
+#define VS2_NEXT_LEVEL_LSB (1U << 17) /* 3b */
+#define VS2_VOTE_LEVEL_LSB (1U << 20) /* 3b */
+#define VS2_TRIGGER_LSB (1U << 23) /* 1b */
+#define VS1_FORCE_LSB (1U << 24) /* 1b */
+#define VS2_FORCE_LSB (1U << 25) /* 1b */
+#define VS1_VOTE_LEVEL_FORCE_LSB (1U << 26) /* 2b */
+#define VS2_VOTE_LEVEL_FORCE_LSB (1U << 28) /* 3b */
+/* RG_MODULE_SW_CG_0_MASK_REQ_0 (0x10006000+0x4B4) */
+#define RG_MODULE_SW_CG_0_MASK_REQ_0_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_0_MASK_REQ_1 (0x10006000+0x4B8) */
+#define RG_MODULE_SW_CG_0_MASK_REQ_1_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_0_MASK_REQ_2 (0x10006000+0x4BC) */
+#define RG_MODULE_SW_CG_0_MASK_REQ_2_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_1_MASK_REQ_0 (0x10006000+0x4C0) */
+#define RG_MODULE_SW_CG_1_MASK_REQ_0_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_1_MASK_REQ_1 (0x10006000+0x4C4) */
+#define RG_MODULE_SW_CG_1_MASK_REQ_1_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_1_MASK_REQ_2 (0x10006000+0x4C8) */
+#define RG_MODULE_SW_CG_1_MASK_REQ_2_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_2_MASK_REQ_0 (0x10006000+0x4CC) */
+#define RG_MODULE_SW_CG_2_MASK_REQ_0_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_2_MASK_REQ_1 (0x10006000+0x4D0) */
+#define RG_MODULE_SW_CG_2_MASK_REQ_1_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_2_MASK_REQ_2 (0x10006000+0x4D4) */
+#define RG_MODULE_SW_CG_2_MASK_REQ_2_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_3_MASK_REQ_0 (0x10006000+0x4D8) */
+#define RG_MODULE_SW_CG_3_MASK_REQ_0_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_3_MASK_REQ_1 (0x10006000+0x4DC) */
+#define RG_MODULE_SW_CG_3_MASK_REQ_1_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_3_MASK_REQ_2 (0x10006000+0x4E0) */
+#define RG_MODULE_SW_CG_3_MASK_REQ_2_LSB (1U << 0) /* 32b */
+/* PWR_STATUS_MASK_REQ_0 (0x10006000+0x4E4) */
+#define PWR_STATUS_MASK_REQ_0_LSB (1U << 0) /* 32b */
+/* PWR_STATUS_MASK_REQ_1 (0x10006000+0x4E8) */
+#define PWR_STATUS_MASK_REQ_1_LSB (1U << 0) /* 32b */
+/* PWR_STATUS_MASK_REQ_2 (0x10006000+0x4EC) */
+#define PWR_STATUS_MASK_REQ_2_LSB (1U << 0) /* 32b */
+/* SPM_CG_CHECK_CON (0x10006000+0x4F0) */
+#define APMIXEDSYS_BUSY_MASK_REQ_0_LSB (1U << 0) /* 5b */
+#define APMIXEDSYS_BUSY_MASK_REQ_1_LSB (1U << 8) /* 5b */
+#define APMIXEDSYS_BUSY_MASK_REQ_2_LSB (1U << 16) /* 5b */
+#define AUDIOSYS_BUSY_MASK_REQ_0_LSB (1U << 24) /* 1b */
+#define AUDIOSYS_BUSY_MASK_REQ_1_LSB (1U << 25) /* 1b */
+#define AUDIOSYS_BUSY_MASK_REQ_2_LSB (1U << 26) /* 1b */
+#define SSUSB_BUSY_MASK_REQ_0_LSB (1U << 27) /* 1b */
+#define SSUSB_BUSY_MASK_REQ_1_LSB (1U << 28) /* 1b */
+#define SSUSB_BUSY_MASK_REQ_2_LSB (1U << 29) /* 1b */
+/* SPM_SRC_RDY_STA (0x10006000+0x4F4) */
+#define SPM_INFRA_INTERNAL_ACK_LSB (1U << 0) /* 1b */
+#define SPM_VRF18_INTERNAL_ACK_LSB (1U << 1) /* 1b */
+/* SPM_DVS_DFS_LEVEL (0x10006000+0x4F8) */
+#define SPM_DFS_LEVEL_LSB (1U << 0) /* 16b */
+#define SPM_DVS_LEVEL_LSB (1U << 16) /* 16b */
+/* SPM_FORCE_DVFS (0x10006000+0x4FC) */
+#define FORCE_DVFS_LEVEL_LSB (1U << 0) /* 32b */
+/* SRCLKEN_RC_CFG (0x10006000+0x500) */
+#define SRCLKEN_RC_CFG_LSB (1U << 0) /* 32b */
+/* RC_CENTRAL_CFG1 (0x10006000+0x504) */
+#define RC_CENTRAL_CFG1_LSB (1U << 0) /* 32b */
+/* RC_CENTRAL_CFG2 (0x10006000+0x508) */
+#define RC_CENTRAL_CFG2_LSB (1U << 0) /* 32b */
+/* RC_CMD_ARB_CFG (0x10006000+0x50C) */
+#define RC_CMD_ARB_CFG_LSB (1U << 0) /* 32b */
+/* RC_PMIC_RCEN_ADDR (0x10006000+0x510) */
+#define RC_PMIC_RCEN_ADDR_LSB (1U << 0) /* 16b */
+#define RC_PMIC_RCEN_RESERVE_LSB (1U << 16) /* 16b */
+/* RC_PMIC_RCEN_SET_CLR_ADDR (0x10006000+0x514) */
+#define RC_PMIC_RCEN_SET_ADDR_LSB (1U << 0) /* 16b */
+#define RC_PMIC_RCEN_CLR_ADDR_LSB (1U << 16) /* 16b */
+/* RC_DCXO_FPM_CFG (0x10006000+0x518) */
+#define RC_DCXO_FPM_CFG_LSB (1U << 0) /* 32b */
+/* RC_CENTRAL_CFG3 (0x10006000+0x51C) */
+#define RC_CENTRAL_CFG3_LSB (1U << 0) /* 32b */
+/* RC_M00_SRCLKEN_CFG (0x10006000+0x520) */
+#define RC_M00_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+#define RC_SW_SRCLKEN_RC (1U << 3) /* 1b */
+#define RC_SW_SRCLKEN_FPM (1U << 4) /* 1b */
+/* RC_M01_SRCLKEN_CFG (0x10006000+0x524) */
+#define RC_M01_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M02_SRCLKEN_CFG (0x10006000+0x528) */
+#define RC_M02_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M03_SRCLKEN_CFG (0x10006000+0x52C) */
+#define RC_M03_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M04_SRCLKEN_CFG (0x10006000+0x530) */
+#define RC_M04_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M05_SRCLKEN_CFG (0x10006000+0x534) */
+#define RC_M05_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M06_SRCLKEN_CFG (0x10006000+0x538) */
+#define RC_M06_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M07_SRCLKEN_CFG (0x10006000+0x53C) */
+#define RC_M07_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M08_SRCLKEN_CFG (0x10006000+0x540) */
+#define RC_M08_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M09_SRCLKEN_CFG (0x10006000+0x544) */
+#define RC_M09_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M10_SRCLKEN_CFG (0x10006000+0x548) */
+#define RC_M10_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M11_SRCLKEN_CFG (0x10006000+0x54C) */
+#define RC_M11_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M12_SRCLKEN_CFG (0x10006000+0x550) */
+#define RC_M12_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_SRCLKEN_SW_CON_CFG (0x10006000+0x554) */
+#define RC_SRCLKEN_SW_CON_CFG_LSB (1U << 0) /* 32b */
+/* RC_CENTRAL_CFG4 (0x10006000+0x558) */
+#define RC_CENTRAL_CFG4_LSB (1U << 0) /* 32b */
+/* RC_PROTOCOL_CHK_CFG (0x10006000+0x560) */
+#define RC_PROTOCOL_CHK_CFG_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_CFG (0x10006000+0x564) */
+#define RC_DEBUG_CFG_LSB (1U << 0) /* 32b */
+/* RC_MISC_0 (0x10006000+0x5B4) */
+#define SRCCLKENO_LSB (1U << 0) /* 2b */
+#define PCM_SRCCLKENO_LSB (1U << 3) /* 2b */
+#define RC_VREQ_LSB (1U << 5) /* 1b */
+#define RC_SPM_SRCCLKENO_0_ACK_LSB (1U << 6) /* 1b */
+/* RC_SPM_CTRL (0x10006000+0x5B8) */
+#define SPM_AP_26M_RDY_LSB (1U << 0) /* 1b */
+#define KEEP_RC_SPI_ACTIVE_LSB (1U << 1) /* 1b */
+#define SPM2RC_DMY_CTRL_LSB (1U << 2) /* 6b */
+/* SUBSYS_INTF_CFG (0x10006000+0x5BC) */
+#define SRCLKEN_FPM_MASK_B_LSB (1U << 0) /* 13b */
+#define SRCLKEN_BBLPM_MASK_B_LSB (1U << 16) /* 13b */
+/* PCM_WDT_LATCH_25 (0x10006000+0x5C0) */
+#define PCM_WDT_LATCH_25_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_26 (0x10006000+0x5C4) */
+#define PCM_WDT_LATCH_26_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_27 (0x10006000+0x5C8) */
+#define PCM_WDT_LATCH_27_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_28 (0x10006000+0x5CC) */
+#define PCM_WDT_LATCH_28_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_29 (0x10006000+0x5D0) */
+#define PCM_WDT_LATCH_29_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_30 (0x10006000+0x5D4) */
+#define PCM_WDT_LATCH_30_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_31 (0x10006000+0x5D8) */
+#define PCM_WDT_LATCH_31_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_32 (0x10006000+0x5DC) */
+#define PCM_WDT_LATCH_32_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_33 (0x10006000+0x5E0) */
+#define PCM_WDT_LATCH_33_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_34 (0x10006000+0x5E4) */
+#define PCM_WDT_LATCH_34_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_35 (0x10006000+0x5EC) */
+#define PCM_WDT_LATCH_35_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_36 (0x10006000+0x5F0) */
+#define PCM_WDT_LATCH_36_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_37 (0x10006000+0x5F4) */
+#define PCM_WDT_LATCH_37_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_38 (0x10006000+0x5F8) */
+#define PCM_WDT_LATCH_38_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_39 (0x10006000+0x5FC) */
+#define PCM_WDT_LATCH_39_LSB (1U << 0) /* 32b */
+/* SPM_SW_FLAG_0 (0x10006000+0x600) */
+#define SPM_SW_FLAG_LSB (1U << 0) /* 32b */
+/* SPM_SW_DEBUG_0 (0x10006000+0x604) */
+#define SPM_SW_DEBUG_0_LSB (1U << 0) /* 32b */
+/* SPM_SW_FLAG_1 (0x10006000+0x608) */
+#define SPM_SW_FLAG_1_LSB (1U << 0) /* 32b */
+/* SPM_SW_DEBUG_1 (0x10006000+0x60C) */
+#define SPM_SW_DEBUG_1_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_0 (0x10006000+0x610) */
+#define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_1 (0x10006000+0x614) */
+#define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_2 (0x10006000+0x618) */
+#define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_3 (0x10006000+0x61C) */
+#define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_4 (0x10006000+0x620) */
+#define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_5 (0x10006000+0x624) */
+#define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_6 (0x10006000+0x628) */
+#define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_7 (0x10006000+0x62C) */
+#define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_8 (0x10006000+0x630) */
+#define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */
+/* SPM_BK_WAKE_EVENT (0x10006000+0x634) */
+#define SPM_BK_WAKE_EVENT_LSB (1U << 0) /* 32b */
+/* SPM_BK_VTCXO_DUR (0x10006000+0x638) */
+#define SPM_BK_VTCXO_DUR_LSB (1U << 0) /* 32b */
+/* SPM_BK_WAKE_MISC (0x10006000+0x63C) */
+#define SPM_BK_WAKE_MISC_LSB (1U << 0) /* 32b */
+/* SPM_BK_PCM_TIMER (0x10006000+0x640) */
+#define SPM_BK_PCM_TIMER_LSB (1U << 0) /* 32b */
+/* SPM_RSV_CON_0 (0x10006000+0x650) */
+#define SPM_RSV_CON_0_LSB (1U << 0) /* 32b */
+/* SPM_RSV_CON_1 (0x10006000+0x654) */
+#define SPM_RSV_CON_1_LSB (1U << 0) /* 32b */
+/* SPM_RSV_STA_0 (0x10006000+0x658) */
+#define SPM_RSV_STA_0_LSB (1U << 0) /* 32b */
+/* SPM_RSV_STA_1 (0x10006000+0x65C) */
+#define SPM_RSV_STA_1_LSB (1U << 0) /* 32b */
+/* SPM_SPARE_CON (0x10006000+0x660) */
+#define SPM_SPARE_CON_LSB (1U << 0) /* 32b */
+/* SPM_SPARE_CON_SET (0x10006000+0x664) */
+#define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */
+/* SPM_SPARE_CON_CLR (0x10006000+0x668) */
+#define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */
+/* SPM_CROSS_WAKE_M00_REQ (0x10006000+0x66C) */
+#define SPM_CROSS_WAKE_M00_REQ_LSB (1U << 0) /* 5b */
+#define SPM_CROSS_WAKE_M00_CHK_LSB (1U << 8) /* 5b */
+/* SPM_CROSS_WAKE_M01_REQ (0x10006000+0x670) */
+#define SPM_CROSS_WAKE_M01_REQ_LSB (1U << 0) /* 5b */
+#define SPM_CROSS_WAKE_M01_CHK_LSB (1U << 8) /* 5b */
+/* SPM_CROSS_WAKE_M02_REQ (0x10006000+0x674) */
+#define SPM_CROSS_WAKE_M02_REQ_LSB (1U << 0) /* 5b */
+#define SPM_CROSS_WAKE_M02_CHK_LSB (1U << 8) /* 5b */
+/* SPM_CROSS_WAKE_M03_REQ (0x10006000+0x678) */
+#define SPM_CROSS_WAKE_M03_REQ_LSB (1U << 0) /* 5b */
+#define SPM_CROSS_WAKE_M03_CHK_LSB (1U << 8) /* 5b */
+/* SCP_VCORE_LEVEL (0x10006000+0x67C) */
+#define SCP_VCORE_LEVEL_LSB (1U << 0) /* 16b */
+/* SC_MM_CK_SEL_CON (0x10006000+0x680) */
+#define SC_MM_CK_SEL_LSB (1U << 0) /* 4b */
+#define SC_MM_CK_SEL_EN_LSB (1U << 4) /* 1b */
+/* SPARE_ACK_MASK (0x10006000+0x684) */
+#define SPARE_ACK_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_CROSS_WAKE_M04_REQ (0x10006000+0x688) */
+#define SPM_CROSS_WAKE_M04_REQ_LSB (1U << 0) /* 5b */
+#define SPM_CROSS_WAKE_M04_CHK_LSB (1U << 8) /* 5b */
+/* SPM_DV_CON_0 (0x10006000+0x68C) */
+#define SPM_DV_CON_0_LSB (1U << 0) /* 32b */
+/* SPM_DV_CON_1 (0x10006000+0x690) */
+#define SPM_DV_CON_1_LSB (1U << 0) /* 32b */
+/* SPM_DV_STA (0x10006000+0x694) */
+#define SPM_DV_STA_LSB (1U << 0) /* 32b */
+/* CONN_XOWCN_DEBUG_EN (0x10006000+0x698) */
+#define CONN_XOWCN_DEBUG_EN_LSB (1U << 0) /* 1b */
+/* SPM_SEMA_M0 (0x10006000+0x69C) */
+#define SPM_SEMA_M0_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M1 (0x10006000+0x6A0) */
+#define SPM_SEMA_M1_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M2 (0x10006000+0x6A4) */
+#define SPM_SEMA_M2_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M3 (0x10006000+0x6A8) */
+#define SPM_SEMA_M3_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M4 (0x10006000+0x6AC) */
+#define SPM_SEMA_M4_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M5 (0x10006000+0x6B0) */
+#define SPM_SEMA_M5_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M6 (0x10006000+0x6B4) */
+#define SPM_SEMA_M6_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M7 (0x10006000+0x6B8) */
+#define SPM_SEMA_M7_LSB (1U << 0) /* 8b */
+/* SPM2ADSP_MAILBOX (0x10006000+0x6BC) */
+#define SPM2ADSP_MAILBOX_LSB (1U << 0) /* 32b */
+/* ADSP2SPM_MAILBOX (0x10006000+0x6C0) */
+#define ADSP2SPM_MAILBOX_LSB (1U << 0) /* 32b */
+/* SPM_ADSP_IRQ (0x10006000+0x6C4) */
+#define SC_SPM2ADSP_WAKEUP_LSB (1U << 0) /* 1b */
+#define SPM_ADSP_IRQ_SC_ADSP2SPM_WAKEUP_LSB (1U << 4) /* 1b */
+/* SPM_MD32_IRQ (0x10006000+0x6C8) */
+#define SC_SPM2SSPM_WAKEUP_LSB (1U << 0) /* 4b */
+#define SPM_MD32_IRQ_SC_SSPM2SPM_WAKEUP_LSB (1U << 4) /* 4b */
+/* SPM2PMCU_MAILBOX_0 (0x10006000+0x6CC) */
+#define SPM2PMCU_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* SPM2PMCU_MAILBOX_1 (0x10006000+0x6D0) */
+#define SPM2PMCU_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* SPM2PMCU_MAILBOX_2 (0x10006000+0x6D4) */
+#define SPM2PMCU_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* SPM2PMCU_MAILBOX_3 (0x10006000+0x6D8) */
+#define SPM2PMCU_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_MAILBOX_0 (0x10006000+0x6DC) */
+#define PMCU2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_MAILBOX_1 (0x10006000+0x6E0) */
+#define PMCU2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_MAILBOX_2 (0x10006000+0x6E4) */
+#define PMCU2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_MAILBOX_3 (0x10006000+0x6E8) */
+#define PMCU2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* UFS_PSRI_SW (0x10006000+0x6EC) */
+#define UFS_PSRI_SW_LSB (1U << 0) /* 1b */
+/* UFS_PSRI_SW_SET (0x10006000+0x6F0) */
+#define UFS_PSRI_SW_SET_LSB (1U << 0) /* 1b */
+/* UFS_PSRI_SW_CLR (0x10006000+0x6F4) */
+#define UFS_PSRI_SW_CLR_LSB (1U << 0) /* 1b */
+/* SPM_AP_SEMA (0x10006000+0x6F8) */
+#define SPM_AP_SEMA_LSB (1U << 0) /* 1b */
+/* SPM_SPM_SEMA (0x10006000+0x6FC) */
+#define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */
+/* SPM_DVFS_CON (0x10006000+0x700) */
+#define SPM_DVFS_CON_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CON_STA (0x10006000+0x704) */
+#define SPM_DVFS_CON_STA_LSB (1U << 0) /* 32b */
+/* SPM_PMIC_SPMI_CON (0x10006000+0x708) */
+#define SPM_PMIC_SPMI_CMD_LSB (1U << 0) /* 2b */
+#define SPM_PMIC_SPMI_SLAVEID_LSB (1U << 2) /* 4b */
+#define SPM_PMIC_SPMI_PMIFID_LSB (1U << 6) /* 1b */
+#define SPM_PMIC_SPMI_DBCNT_LSB (1U << 7) /* 1b */
+/* SPM_DVFS_CMD0 (0x10006000+0x710) */
+#define SPM_DVFS_CMD0_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD1 (0x10006000+0x714) */
+#define SPM_DVFS_CMD1_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD2 (0x10006000+0x718) */
+#define SPM_DVFS_CMD2_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD3 (0x10006000+0x71C) */
+#define SPM_DVFS_CMD3_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD4 (0x10006000+0x720) */
+#define SPM_DVFS_CMD4_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD5 (0x10006000+0x724) */
+#define SPM_DVFS_CMD5_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD6 (0x10006000+0x728) */
+#define SPM_DVFS_CMD6_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD7 (0x10006000+0x72C) */
+#define SPM_DVFS_CMD7_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD8 (0x10006000+0x730) */
+#define SPM_DVFS_CMD8_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD9 (0x10006000+0x734) */
+#define SPM_DVFS_CMD9_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD10 (0x10006000+0x738) */
+#define SPM_DVFS_CMD10_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD11 (0x10006000+0x73C) */
+#define SPM_DVFS_CMD11_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD12 (0x10006000+0x740) */
+#define SPM_DVFS_CMD12_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD13 (0x10006000+0x744) */
+#define SPM_DVFS_CMD13_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD14 (0x10006000+0x748) */
+#define SPM_DVFS_CMD14_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD15 (0x10006000+0x74C) */
+#define SPM_DVFS_CMD15_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD16 (0x10006000+0x750) */
+#define SPM_DVFS_CMD16_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD17 (0x10006000+0x754) */
+#define SPM_DVFS_CMD17_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD18 (0x10006000+0x758) */
+#define SPM_DVFS_CMD18_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD19 (0x10006000+0x75C) */
+#define SPM_DVFS_CMD19_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD20 (0x10006000+0x760) */
+#define SPM_DVFS_CMD20_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD21 (0x10006000+0x764) */
+#define SPM_DVFS_CMD21_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD22 (0x10006000+0x768) */
+#define SPM_DVFS_CMD22_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD23 (0x10006000+0x76C) */
+#define SPM_DVFS_CMD23_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_VALUE_L (0x10006000+0x770) */
+#define SYS_TIMER_VALUE_L_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_VALUE_H (0x10006000+0x774) */
+#define SYS_TIMER_VALUE_H_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_START_L (0x10006000+0x778) */
+#define SYS_TIMER_START_L_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_START_H (0x10006000+0x77C) */
+#define SYS_TIMER_START_H_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_00 (0x10006000+0x780) */
+#define SYS_TIMER_LATCH_L_00_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_00 (0x10006000+0x784) */
+#define SYS_TIMER_LATCH_H_00_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_01 (0x10006000+0x788) */
+#define SYS_TIMER_LATCH_L_01_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_01 (0x10006000+0x78C) */
+#define SYS_TIMER_LATCH_H_01_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_02 (0x10006000+0x790) */
+#define SYS_TIMER_LATCH_L_02_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_02 (0x10006000+0x794) */
+#define SYS_TIMER_LATCH_H_02_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_03 (0x10006000+0x798) */
+#define SYS_TIMER_LATCH_L_03_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_03 (0x10006000+0x79C) */
+#define SYS_TIMER_LATCH_H_03_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_04 (0x10006000+0x7A0) */
+#define SYS_TIMER_LATCH_L_04_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_04 (0x10006000+0x7A4) */
+#define SYS_TIMER_LATCH_H_04_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_05 (0x10006000+0x7A8) */
+#define SYS_TIMER_LATCH_L_05_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_05 (0x10006000+0x7AC) */
+#define SYS_TIMER_LATCH_H_05_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_06 (0x10006000+0x7B0) */
+#define SYS_TIMER_LATCH_L_06_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_06 (0x10006000+0x7B4) */
+#define SYS_TIMER_LATCH_H_06_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_07 (0x10006000+0x7B8) */
+#define SYS_TIMER_LATCH_L_07_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_07 (0x10006000+0x7BC) */
+#define SYS_TIMER_LATCH_H_07_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_08 (0x10006000+0x7C0) */
+#define SYS_TIMER_LATCH_L_08_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_08 (0x10006000+0x7C4) */
+#define SYS_TIMER_LATCH_H_08_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_09 (0x10006000+0x7C8) */
+#define SYS_TIMER_LATCH_L_09_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_09 (0x10006000+0x7CC) */
+#define SYS_TIMER_LATCH_H_09_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_10 (0x10006000+0x7D0) */
+#define SYS_TIMER_LATCH_L_10_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_10 (0x10006000+0x7D4) */
+#define SYS_TIMER_LATCH_H_10_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_11 (0x10006000+0x7D8) */
+#define SYS_TIMER_LATCH_L_11_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_11 (0x10006000+0x7DC) */
+#define SYS_TIMER_LATCH_H_11_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_12 (0x10006000+0x7E0) */
+#define SYS_TIMER_LATCH_L_12_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_12 (0x10006000+0x7E4) */
+#define SYS_TIMER_LATCH_H_12_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_13 (0x10006000+0x7E8) */
+#define SYS_TIMER_LATCH_L_13_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_13 (0x10006000+0x7EC) */
+#define SYS_TIMER_LATCH_H_13_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_14 (0x10006000+0x7F0) */
+#define SYS_TIMER_LATCH_L_14_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_14 (0x10006000+0x7F4) */
+#define SYS_TIMER_LATCH_H_14_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_15 (0x10006000+0x7F8) */
+#define SYS_TIMER_LATCH_L_15_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_15 (0x10006000+0x7FC) */
+#define SYS_TIMER_LATCH_H_15_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_0 (0x10006000+0x800) */
+#define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_1 (0x10006000+0x804) */
+#define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_2 (0x10006000+0x808) */
+#define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_3 (0x10006000+0x80C) */
+#define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_4 (0x10006000+0x810) */
+#define PCM_WDT_LATCH_4_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_5 (0x10006000+0x814) */
+#define PCM_WDT_LATCH_5_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_6 (0x10006000+0x818) */
+#define PCM_WDT_LATCH_6_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_7 (0x10006000+0x81C) */
+#define PCM_WDT_LATCH_7_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_8 (0x10006000+0x820) */
+#define PCM_WDT_LATCH_8_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_9 (0x10006000+0x824) */
+#define PCM_WDT_LATCH_9_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_10 (0x10006000+0x828) */
+#define PCM_WDT_LATCH_10_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_11 (0x10006000+0x82C) */
+#define PCM_WDT_LATCH_11_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_12 (0x10006000+0x830) */
+#define PCM_WDT_LATCH_12_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_13 (0x10006000+0x834) */
+#define PCM_WDT_LATCH_13_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_14 (0x10006000+0x838) */
+#define PCM_WDT_LATCH_14_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_15 (0x10006000+0x83C) */
+#define PCM_WDT_LATCH_15_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_16 (0x10006000+0x840) */
+#define PCM_WDT_LATCH_16_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_17 (0x10006000+0x844) */
+#define PCM_WDT_LATCH_17_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_18 (0x10006000+0x848) */
+#define PCM_WDT_LATCH_18_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_SPARE_0 (0x10006000+0x84C) */
+#define PCM_WDT_LATCH_SPARE_0_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_SPARE_1 (0x10006000+0x850) */
+#define PCM_WDT_LATCH_SPARE_1_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_SPARE_2 (0x10006000+0x854) */
+#define PCM_WDT_LATCH_SPARE_2_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_CONN_0 (0x10006000+0x870) */
+#define PCM_WDT_LATCH_CONN_0_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_CONN_1 (0x10006000+0x874) */
+#define PCM_WDT_LATCH_CONN_1_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_CONN_2 (0x10006000+0x878) */
+#define PCM_WDT_LATCH_CONN_2_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_0 (0x10006000+0x8A0) */
+#define DRAMC_GATING_ERR_LATCH_CH0_0_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_1 (0x10006000+0x8A4) */
+#define DRAMC_GATING_ERR_LATCH_CH0_1_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_2 (0x10006000+0x8A8) */
+#define DRAMC_GATING_ERR_LATCH_CH0_2_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_3 (0x10006000+0x8AC) */
+#define DRAMC_GATING_ERR_LATCH_CH0_3_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_4 (0x10006000+0x8B0) */
+#define DRAMC_GATING_ERR_LATCH_CH0_4_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_5 (0x10006000+0x8B4) */
+#define DRAMC_GATING_ERR_LATCH_CH0_5_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_6 (0x10006000+0x8B8) */
+#define DRAMC_GATING_ERR_LATCH_CH0_6_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_SPARE_0 (0x10006000+0x8F4) */
+#define DRAMC_GATING_ERR_LATCH_SPARE_0_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON_0 (0x10006000+0x900) */
+#define SPM_ACK_CHK_SW_EN_0_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_0_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_0_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_0_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN_0_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_0_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN_0_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_0_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN_0_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE_0_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL_0_LSB (1U << 15) /* 1b */
+/* SPM_ACK_CHK_PC_0 (0x10006000+0x904) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_0_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_0_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL_0 (0x10006000+0x908) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_0_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_0_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_0_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_0_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER_0 (0x10006000+0x90C) */
+#define SPM_ACK_CHK_TIMER_VAL_0_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER_0_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA_0 (0x10006000+0x910) */
+#define SPM_ACK_CHK_STA_0_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_SWINT_0 (0x10006000+0x914) */
+#define SPM_ACK_CHK_SWINT_EN_0_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON_1 (0x10006000+0x920) */
+#define SPM_ACK_CHK_SW_EN_1_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_1_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_1_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_1_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN_1_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_1_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN_1_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_1_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN_1_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE_1_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL_1_LSB (1U << 15) /* 1b */
+/* SPM_ACK_CHK_PC_1 (0x10006000+0x924) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_1_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_1_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL_1 (0x10006000+0x928) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_1_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_1_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_1_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_1_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER_1 (0x10006000+0x92C) */
+#define SPM_ACK_CHK_TIMER_VAL_1_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER_1_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA_1 (0x10006000+0x930) */
+#define SPM_ACK_CHK_STA_1_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_SWINT_1 (0x10006000+0x934) */
+#define SPM_ACK_CHK_SWINT_EN_1_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON_2 (0x10006000+0x940) */
+#define SPM_ACK_CHK_SW_EN_2_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_2_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_2_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_2_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN_2_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_2_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN_2_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_2_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN_2_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE_2_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL_2_LSB (1U << 15) /* 1b */
+/* SPM_ACK_CHK_PC_2 (0x10006000+0x944) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_2_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_2_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL_2 (0x10006000+0x948) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_2_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_2_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_2_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_2_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER_2 (0x10006000+0x94C) */
+#define SPM_ACK_CHK_TIMER_VAL_2_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER_2_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA_2 (0x10006000+0x950) */
+#define SPM_ACK_CHK_STA_2_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_SWINT_2 (0x10006000+0x954) */
+#define SPM_ACK_CHK_SWINT_EN_2_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON_3 (0x10006000+0x960) */
+#define SPM_ACK_CHK_SW_EN_3_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_3_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_3_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_3_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN_3_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_3_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN_3_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_3_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN_3_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE_3_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL_3_LSB (1U << 15) /* 1b */
+/* SPM_ACK_CHK_PC_3 (0x10006000+0x964) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_3_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_3_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL_3 (0x10006000+0x968) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_3_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_3_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_3_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_3_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER_3 (0x10006000+0x96C) */
+#define SPM_ACK_CHK_TIMER_VAL_3_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER_3_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA_3 (0x10006000+0x970) */
+#define SPM_ACK_CHK_STA_3_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_SWINT_3 (0x10006000+0x974) */
+#define SPM_ACK_CHK_SWINT_EN_3_LSB (1U << 0) /* 32b */
+/* SPM_COUNTER_0 (0x10006000+0x978) */
+#define SPM_COUNTER_VAL_0_LSB (1U << 0) /* 14b */
+#define SPM_COUNTER_OUT_0_LSB (1U << 14) /* 14b */
+#define SPM_COUNTER_EN_0_LSB (1U << 28) /* 1b */
+#define SPM_COUNTER_CLR_0_LSB (1U << 29) /* 1b */
+#define SPM_COUNTER_TIMEOUT_0_LSB (1U << 30) /* 1b */
+#define SPM_COUNTER_WAKEUP_EN_0_LSB (1U << 31) /* 1b */
+/* SPM_COUNTER_1 (0x10006000+0x97C) */
+#define SPM_COUNTER_VAL_1_LSB (1U << 0) /* 14b */
+#define SPM_COUNTER_OUT_1_LSB (1U << 14) /* 14b */
+#define SPM_COUNTER_EN_1_LSB (1U << 28) /* 1b */
+#define SPM_COUNTER_CLR_1_LSB (1U << 29) /* 1b */
+#define SPM_COUNTER_TIMEOUT_1_LSB (1U << 30) /* 1b */
+#define SPM_COUNTER_WAKEUP_EN_1_LSB (1U << 31) /* 1b */
+/* SPM_COUNTER_2 (0x10006000+0x980) */
+#define SPM_COUNTER_VAL_2_LSB (1U << 0) /* 14b */
+#define SPM_COUNTER_OUT_2_LSB (1U << 14) /* 14b */
+#define SPM_COUNTER_EN_2_LSB (1U << 28) /* 1b */
+#define SPM_COUNTER_CLR_2_LSB (1U << 29) /* 1b */
+#define SPM_COUNTER_TIMEOUT_2_LSB (1U << 30) /* 1b */
+#define SPM_COUNTER_WAKEUP_EN_2_LSB (1U << 31) /* 1b */
+/* SYS_TIMER_CON (0x10006000+0x98C) */
+#define SYS_TIMER_START_EN_LSB (1U << 0) /* 1b */
+#define SYS_TIMER_LATCH_EN_LSB (1U << 1) /* 1b */
+#define SYS_TIMER_ID_LSB (1U << 8) /* 8b */
+#define SYS_TIMER_VALID_LSB (1U << 31) /* 1b */
+/* RC_FSM_STA_0 (0x10006000+0xE00) */
+#define RC_FSM_STA_0_LSB (1U << 0) /* 32b */
+/* RC_CMD_STA_0 (0x10006000+0xE04) */
+#define RC_CMD_STA_0_LSB (1U << 0) /* 32b */
+/* RC_CMD_STA_1 (0x10006000+0xE08) */
+#define RC_CMD_STA_1_LSB (1U << 0) /* 32b */
+/* RC_SPI_STA_0 (0x10006000+0xE0C) */
+#define RC_SPI_STA_0_LSB (1U << 0) /* 32b */
+/* RC_PI_PO_STA_0 (0x10006000+0xE10) */
+#define RC_PI_PO_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M00_REQ_STA_0 (0x10006000+0xE14) */
+#define RC_M00_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M01_REQ_STA_0 (0x10006000+0xE1C) */
+#define RC_M01_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M02_REQ_STA_0 (0x10006000+0xE20) */
+#define RC_M02_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M03_REQ_STA_0 (0x10006000+0xE24) */
+#define RC_M03_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M04_REQ_STA_0 (0x10006000+0xE28) */
+#define RC_M04_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M05_REQ_STA_0 (0x10006000+0xE2C) */
+#define RC_M05_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M06_REQ_STA_0 (0x10006000+0xE30) */
+#define RC_M06_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M07_REQ_STA_0 (0x10006000+0xE34) */
+#define RC_M07_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M08_REQ_STA_0 (0x10006000+0xE38) */
+#define RC_M08_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M09_REQ_STA_0 (0x10006000+0xE3C) */
+#define RC_M09_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M10_REQ_STA_0 (0x10006000+0xE40) */
+#define RC_M10_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M11_REQ_STA_0 (0x10006000+0xE44) */
+#define RC_M11_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M12_REQ_STA_0 (0x10006000+0xE48) */
+#define RC_M12_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_STA_0 (0x10006000+0xE4C) */
+#define RC_DEBUG_STA_0_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_0_LSB (0x10006000+0xE50) */
+#define RO_PMRC_TRACE_00_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_0_MSB (0x10006000+0xE54) */
+#define RO_PMRC_TRACE_00_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_1_LSB (0x10006000+0xE5C) */
+#define RO_PMRC_TRACE_01_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_1_MSB (0x10006000+0xE60) */
+#define RO_PMRC_TRACE_01_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_2_LSB (0x10006000+0xE64) */
+#define RO_PMRC_TRACE_02_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_2_MSB (0x10006000+0xE6C) */
+#define RO_PMRC_TRACE_02_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_3_LSB (0x10006000+0xE70) */
+#define RO_PMRC_TRACE_03_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_3_MSB (0x10006000+0xE74) */
+#define RO_PMRC_TRACE_03_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_4_LSB (0x10006000+0xE78) */
+#define RO_PMRC_TRACE_04_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_4_MSB (0x10006000+0xE7C) */
+#define RO_PMRC_TRACE_04_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_5_LSB (0x10006000+0xE80) */
+#define RO_PMRC_TRACE_05_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_5_MSB (0x10006000+0xE84) */
+#define RO_PMRC_TRACE_05_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_6_LSB (0x10006000+0xE88) */
+#define RO_PMRC_TRACE_06_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_6_MSB (0x10006000+0xE8C) */
+#define RO_PMRC_TRACE_06_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_7_LSB (0x10006000+0xE90) */
+#define RO_PMRC_TRACE_07_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_7_MSB (0x10006000+0xE94) */
+#define RO_PMRC_TRACE_07_MSB_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_0_LSB (0x10006000+0xE98) */
+#define RC_SYS_TIMER_LATCH_L_00_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_0_MSB (0x10006000+0xE9C) */
+#define RC_SYS_TIMER_LATCH_H_00_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_1_LSB (0x10006000+0xEA0) */
+#define RC_SYS_TIMER_LATCH_L_01_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_1_MSB (0x10006000+0xEA4) */
+#define RC_SYS_TIMER_LATCH_H_01_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_2_LSB (0x10006000+0xEA8) */
+#define RC_SYS_TIMER_LATCH_L_02_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_2_MSB (0x10006000+0xEAC) */
+#define RC_SYS_TIMER_LATCH_H_02_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_3_LSB (0x10006000+0xEB0) */
+#define RC_SYS_TIMER_LATCH_L_03_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_3_MSB (0x10006000+0xEB4) */
+#define RC_SYS_TIMER_LATCH_H_03_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_4_LSB (0x10006000+0xEB8) */
+#define RC_SYS_TIMER_LATCH_L_04_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_4_MSB (0x10006000+0xEBC) */
+#define RC_SYS_TIMER_LATCH_H_04_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_5_LSB (0x10006000+0xEC0) */
+#define RC_SYS_TIMER_LATCH_L_05_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_5_MSB (0x10006000+0xEC4) */
+#define RC_SYS_TIMER_LATCH_H_05_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_6_LSB (0x10006000+0xEC8) */
+#define RC_SYS_TIMER_LATCH_L_06_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_6_MSB (0x10006000+0xECC) */
+#define RC_SYS_TIMER_LATCH_H_06_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_7_LSB (0x10006000+0xED0) */
+#define RC_SYS_TIMER_LATCH_L_07_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_7_MSB (0x10006000+0xED4) */
+#define RC_SYS_TIMER_LATCH_H_07_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_19 (0x10006000+0xED8) */
+#define PCM_WDT_LATCH_19_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_20 (0x10006000+0xEDC) */
+#define PCM_WDT_LATCH_20_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_21 (0x10006000+0xEE0) */
+#define PCM_WDT_LATCH_21_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_22 (0x10006000+0xEE4) */
+#define PCM_WDT_LATCH_22_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_23 (0x10006000+0xEE8) */
+#define PCM_WDT_LATCH_23_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_24 (0x10006000+0xEEC) */
+#define PCM_WDT_LATCH_24_LSB (1U << 0) /* 32b */
+/* PMSR_LAST_DAT (0x10006000+0xF00) */
+#define PMSR_LAST_DAT_LSB (1U << 0) /* 32b */
+/* PMSR_LAST_CNT (0x10006000+0xF04) */
+#define PMSR_LAST_CMD_LSB (1U << 0) /* 30b */
+#define PMSR_LAST_REQ_LSB (1U << 30) /* 1b */
+/* PMSR_LAST_ACK (0x10006000+0xF08) */
+#define PMSR_LAST_ACK_LSB (1U << 0) /* 1b */
+/* SPM_PMSR_SEL_CON0 (0x10006000+0xF10) */
+#define REG_PMSR_SIG_SEL_0_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_1_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_2_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_3_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON1 (0x10006000+0xF14) */
+#define REG_PMSR_SIG_SEL_4_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_5_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_6_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_7_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON2 (0x10006000+0xF18) */
+#define REG_PMSR_SIG_SEL_8_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_9_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_10_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_11_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON3 (0x10006000+0xF1C) */
+#define REG_PMSR_SIG_SEL_12_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_13_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_14_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_15_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON4 (0x10006000+0xF20) */
+#define REG_PMSR_SIG_SEL_16_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_17_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_18_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_19_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON5 (0x10006000+0xF24) */
+#define REG_PMSR_SIG_SEL_20_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_21_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_22_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_23_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON6 (0x10006000+0xF28) */
+#define REG_PMSR_SIG_SEL_24_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_25_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_26_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_27_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON7 (0x10006000+0xF2C) */
+#define REG_PMSR_SIG_SEL_28_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_29_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_30_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_31_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON8 (0x10006000+0xF30) */
+#define REG_PMSR_SIG_SEL_32_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_33_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_34_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_35_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON9 (0x10006000+0xF34) */
+#define REG_PMSR_SIG_SEL_36_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_37_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_38_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_39_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON10 (0x10006000+0xF3C) */
+#define REG_PMSR_SIG_SEL_40_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_41_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_42_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_43_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON11 (0x10006000+0xF40) */
+#define REG_PMSR_SIG_SEL_44_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_45_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_46_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_47_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_TIEMR_STA0 (0x10006000+0xFB8) */
+#define PMSR_TIMER_SET0_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_TIEMR_STA1 (0x10006000+0xFBC) */
+#define PMSR_TIMER_SET1_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_TIEMR_STA2 (0x10006000+0xFC0) */
+#define PMSR_TIMER_SET2_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_GENERAL_CON0 (0x10006000+0xFC4) */
+#define PMSR_ENABLE_SET0_LSB (1U << 0) /* 1b */
+#define PMSR_ENABLE_SET1_LSB (1U << 1) /* 1b */
+#define PMSR_ENABLE_SET2_LSB (1U << 2) /* 1b */
+#define PMSR_IRQ_CLR_SET0_LSB (1U << 3) /* 1b */
+#define PMSR_IRQ_CLR_SET1_LSB (1U << 4) /* 1b */
+#define PMSR_IRQ_CLR_SET2_LSB (1U << 5) /* 1b */
+#define PMSR_SPEED_MODE_EN_SET0_LSB (1U << 6) /* 1b */
+#define PMSR_SPEED_MODE_EN_SET1_LSB (1U << 7) /* 1b */
+#define PMSR_SPEED_MODE_EN_SET2_LSB (1U << 8) /* 1b */
+#define PMSR_EVENT_CLR_SET0_LSB (1U << 9) /* 1b */
+#define PMSR_EVENT_CLR_SET1_LSB (1U << 10) /* 1b */
+#define PMSR_EVENT_CLR_SET2_LSB (1U << 11) /* 1b */
+#define REG_PMSR_IRQ_MASK_SET0_LSB (1U << 12) /* 1b */
+#define REG_PMSR_IRQ_MASK_SET1_LSB (1U << 13) /* 1b */
+#define REG_PMSR_IRQ_MASK_SET2_LSB (1U << 14) /* 1b */
+#define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET0_LSB (1U << 15) /* 1b */
+#define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET1_LSB (1U << 16) /* 1b */
+#define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET2_LSB (1U << 17) /* 1b */
+#define PMSR_GEN_SW_RST_EN_LSB (1U << 18) /* 1b */
+#define PMSR_MODULE_ENABLE_LSB (1U << 19) /* 1b */
+#define PMSR_MODE_LSB (1U << 20) /* 2b */
+#define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET0_LSB (1U << 29) /* 1b */
+#define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET1_LSB (1U << 30) /* 1b */
+#define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET2_LSB (1U << 31) /* 1b */
+/* SPM_PMSR_GENERAL_CON1 (0x10006000+0xFC8) */
+#define PMSR_COUNTER_THRES_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_GENERAL_CON2 (0x10006000+0xFCC) */
+#define PMSR_DEBUG_IN_0_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_GENERAL_CON3 (0x10006000+0xFD0) */
+#define PMSR_DEBUG_IN_1_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_GENERAL_CON4 (0x10006000+0xFD4) */
+#define PMSR_DEBUG_IN_2_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_GENERAL_CON5 (0x10006000+0xFD8) */
+#define PMSR_DEBUG_IN_3_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_SW_RESET (0x10006000+0xFDC) */
+#define PMSR_SW_RST_EN_SET0_LSB (1U << 0) /* 1b */
+#define PMSR_SW_RST_EN_SET1_LSB (1U << 1) /* 1b */
+#define PMSR_SW_RST_EN_SET2_LSB (1U << 2) /* 1b */
+/* SPM_PMSR_MON_CON0 (0x10006000+0xFE0) */
+#define REG_PMSR_MON_TYPE_0_LSB (1U << 0) /* 2b */
+#define REG_PMSR_MON_TYPE_1_LSB (1U << 2) /* 2b */
+#define REG_PMSR_MON_TYPE_2_LSB (1U << 4) /* 2b */
+#define REG_PMSR_MON_TYPE_3_LSB (1U << 6) /* 2b */
+#define REG_PMSR_MON_TYPE_4_LSB (1U << 8) /* 2b */
+#define REG_PMSR_MON_TYPE_5_LSB (1U << 10) /* 2b */
+#define REG_PMSR_MON_TYPE_6_LSB (1U << 12) /* 2b */
+#define REG_PMSR_MON_TYPE_7_LSB (1U << 14) /* 2b */
+#define REG_PMSR_MON_TYPE_8_LSB (1U << 16) /* 2b */
+#define REG_PMSR_MON_TYPE_9_LSB (1U << 18) /* 2b */
+#define REG_PMSR_MON_TYPE_10_LSB (1U << 20) /* 2b */
+#define REG_PMSR_MON_TYPE_11_LSB (1U << 22) /* 2b */
+#define REG_PMSR_MON_TYPE_12_LSB (1U << 24) /* 2b */
+#define REG_PMSR_MON_TYPE_13_LSB (1U << 26) /* 2b */
+#define REG_PMSR_MON_TYPE_14_LSB (1U << 28) /* 2b */
+#define REG_PMSR_MON_TYPE_15_LSB (1U << 30) /* 2b */
+/* SPM_PMSR_MON_CON1 (0x10006000+0xFE4) */
+#define REG_PMSR_MON_TYPE_16_LSB (1U << 0) /* 2b */
+#define REG_PMSR_MON_TYPE_17_LSB (1U << 2) /* 2b */
+#define REG_PMSR_MON_TYPE_18_LSB (1U << 4) /* 2b */
+#define REG_PMSR_MON_TYPE_19_LSB (1U << 6) /* 2b */
+#define REG_PMSR_MON_TYPE_20_LSB (1U << 8) /* 2b */
+#define REG_PMSR_MON_TYPE_21_LSB (1U << 10) /* 2b */
+#define REG_PMSR_MON_TYPE_22_LSB (1U << 12) /* 2b */
+#define REG_PMSR_MON_TYPE_23_LSB (1U << 14) /* 2b */
+#define REG_PMSR_MON_TYPE_24_LSB (1U << 16) /* 2b */
+#define REG_PMSR_MON_TYPE_25_LSB (1U << 18) /* 2b */
+#define REG_PMSR_MON_TYPE_26_LSB (1U << 20) /* 2b */
+#define REG_PMSR_MON_TYPE_27_LSB (1U << 22) /* 2b */
+#define REG_PMSR_MON_TYPE_28_LSB (1U << 24) /* 2b */
+#define REG_PMSR_MON_TYPE_29_LSB (1U << 26) /* 2b */
+#define REG_PMSR_MON_TYPE_30_LSB (1U << 28) /* 2b */
+#define REG_PMSR_MON_TYPE_31_LSB (1U << 30) /* 2b */
+/* SPM_PMSR_MON_CON2 (0x10006000+0xFE8) */
+#define REG_PMSR_MON_TYPE_32_LSB (1U << 0) /* 2b */
+#define REG_PMSR_MON_TYPE_33_LSB (1U << 2) /* 2b */
+#define REG_PMSR_MON_TYPE_34_LSB (1U << 4) /* 2b */
+#define REG_PMSR_MON_TYPE_35_LSB (1U << 6) /* 2b */
+#define REG_PMSR_MON_TYPE_36_LSB (1U << 8) /* 2b */
+#define REG_PMSR_MON_TYPE_37_LSB (1U << 10) /* 2b */
+#define REG_PMSR_MON_TYPE_38_LSB (1U << 12) /* 2b */
+#define REG_PMSR_MON_TYPE_39_LSB (1U << 14) /* 2b */
+#define REG_PMSR_MON_TYPE_40_LSB (1U << 16) /* 2b */
+#define REG_PMSR_MON_TYPE_41_LSB (1U << 18) /* 2b */
+#define REG_PMSR_MON_TYPE_42_LSB (1U << 20) /* 2b */
+#define REG_PMSR_MON_TYPE_43_LSB (1U << 22) /* 2b */
+#define REG_PMSR_MON_TYPE_44_LSB (1U << 24) /* 2b */
+#define REG_PMSR_MON_TYPE_45_LSB (1U << 26) /* 2b */
+#define REG_PMSR_MON_TYPE_46_LSB (1U << 28) /* 2b */
+#define REG_PMSR_MON_TYPE_47_LSB (1U << 30) /* 2b */
+/* SPM_PMSR_LEN_CON0 (0x10006000+0xFEC) */
+#define REG_PMSR_WINDOW_LEN_SET0_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_LEN_CON1 (0x10006000+0xFF0) */
+#define REG_PMSR_WINDOW_LEN_SET1_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_LEN_CON2 (0x10006000+0xFF4) */
+#define REG_PMSR_WINDOW_LEN_SET2_LSB (1U << 0) /* 32b */
+
+#define SPM_PROJECT_CODE 0xb16
+#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16)
+#endif /* MT_SPM_REG */
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_resource_req.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_resource_req.h
new file mode 100644
index 0000000..30194eb
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_resource_req.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RESOURCE_REQ_H
+#define MT_SPM_RESOURCE_REQ_H
+
+/* SPM resource request internal bit */
+#define MT_SPM_BIT_XO_FPM 0
+#define MT_SPM_BIT_26M 1
+#define MT_SPM_BIT_INFRA 2
+#define MT_SPM_BIT_SYSPLL 3
+#define MT_SPM_BIT_DRAM_S0 4
+#define MT_SPM_BIT_DRAM_S1 5
+
+/* SPM resource request internal bit_mask */
+#define MT_SPM_XO_FPM BIT(MT_SPM_BIT_XO_FPM)
+#define MT_SPM_26M BIT(MT_SPM_BIT_26M)
+#define MT_SPM_INFRA BIT(MT_SPM_BIT_INFRA)
+#define MT_SPM_SYSPLL BIT(MT_SPM_BIT_SYSPLL)
+#define MT_SPM_DRAM_S0 BIT(MT_SPM_BIT_DRAM_S0)
+#define MT_SPM_DRAM_S1 BIT(MT_SPM_BIT_DRAM_S1)
+#endif /* MT_SPM_RESOURCE_REQ_H */
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_suspend.c b/plat/mediatek/mt8192/drivers/spm/mt_spm_suspend.c
new file mode 100644
index 0000000..3eb73d4
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_suspend.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <mt_spm.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_suspend.h>
+#include <plat_pm.h>
+#include <uart.h>
+
+#define SPM_SUSPEND_SLEEP_PCM_FLAG \
+ (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
+ SPM_FLAG_USE_SRCCLKENO2 | \
+ SPM_FLAG_ENABLE_MD_MUMTAS | \
+ SPM_FLAG_SRAM_SLEEP_CTRL)
+
+#define SPM_SUSPEND_SLEEP_PCM_FLAG1 \
+ (SPM_FLAG1_DISABLE_MD26M_CK_OFF)
+
+#define SPM_SUSPEND_PCM_FLAG \
+ (SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_ENABLE_TIA_WORKAROUND | \
+ SPM_FLAG_ENABLE_MD_MUMTAS | \
+ SPM_FLAG_SRAM_SLEEP_CTRL)
+
+#define SPM_SUSPEND_PCM_FLAG1 \
+ (SPM_FLAG1_DISABLE_MD26M_CK_OFF)
+
+#define __WAKE_SRC_FOR_SUSPEND_COMMON__ \
+ (R12_PCM_TIMER | \
+ R12_KP_IRQ_B | \
+ R12_APWDT_EVENT_B | \
+ R12_APXGPT1_EVENT_B | \
+ R12_CONN2AP_SPM_WAKEUP_B | \
+ R12_EINT_EVENT_B | \
+ R12_CONN_WDT_IRQ_B | \
+ R12_CCIF0_EVENT_B | \
+ R12_SSPM2SPM_WAKEUP_B | \
+ R12_SCP2SPM_WAKEUP_B | \
+ R12_ADSP2SPM_WAKEUP_B | \
+ R12_USBX_CDSC_B | \
+ R12_USBX_POWERDWN_B | \
+ R12_SYS_TIMER_EVENT_B | \
+ R12_EINT_EVENT_SECURE_B | \
+ R12_CCIF1_EVENT_B | \
+ R12_SYS_CIRQ_IRQ_B | \
+ R12_MD2AP_PEER_EVENT_B | \
+ R12_MD1_WDT_B | \
+ R12_CLDMA_EVENT_B | \
+ R12_REG_CPU_WAKEUP | \
+ R12_APUSYS_WAKE_HOST_B | \
+ R12_PCIE_BRIDGE_IRQ | \
+ R12_PCIE_IRQ)
+
+#if defined(CFG_MICROTRUST_TEE_SUPPORT)
+#define WAKE_SRC_FOR_SUSPEND (__WAKE_SRC_FOR_SUSPEND_COMMON__)
+#else
+#define WAKE_SRC_FOR_SUSPEND \
+ (__WAKE_SRC_FOR_SUSPEND_COMMON__ | \
+ R12_SEJ_EVENT_B)
+#endif
+
+static struct pwr_ctrl suspend_ctrl = {
+ .wake_src = WAKE_SRC_FOR_SUSPEND,
+ .pcm_flags = SPM_SUSPEND_PCM_FLAG | SPM_FLAG_DISABLE_INFRA_PDN,
+ .pcm_flags1 = SPM_SUSPEND_PCM_FLAG1,
+
+ /* Auto-gen Start */
+
+ /* SPM_AP_STANDBY_CON */
+ .reg_wfi_op = 0,
+ .reg_wfi_type = 0,
+ .reg_mp0_cputop_idle_mask = 0,
+ .reg_mp1_cputop_idle_mask = 0,
+ .reg_mcusys_idle_mask = 0,
+ .reg_md_apsrc_1_sel = 0,
+ .reg_md_apsrc_0_sel = 0,
+ .reg_conn_apsrc_sel = 0,
+
+ /* SPM_SRC6_MASK */
+ .reg_dpmaif_srcclkena_mask_b = 1,
+ .reg_dpmaif_infra_req_mask_b = 1,
+ .reg_dpmaif_apsrc_req_mask_b = 1,
+ .reg_dpmaif_vrf18_req_mask_b = 1,
+ .reg_dpmaif_ddr_en_mask_b = 1,
+
+ /* SPM_SRC_REQ */
+ .reg_spm_apsrc_req = 0,
+ .reg_spm_f26m_req = 0,
+ .reg_spm_infra_req = 0,
+ .reg_spm_vrf18_req = 0,
+ .reg_spm_ddr_en_req = 0,
+ .reg_spm_dvfs_req = 0,
+ .reg_spm_sw_mailbox_req = 0,
+ .reg_spm_sspm_mailbox_req = 0,
+ .reg_spm_adsp_mailbox_req = 0,
+ .reg_spm_scp_mailbox_req = 0,
+
+ /* SPM_SRC_MASK */
+ .reg_md_srcclkena_0_mask_b = 1,
+ .reg_md_srcclkena2infra_req_0_mask_b = 0,
+ .reg_md_apsrc2infra_req_0_mask_b = 1,
+ .reg_md_apsrc_req_0_mask_b = 1,
+ .reg_md_vrf18_req_0_mask_b = 1,
+ .reg_md_ddr_en_0_mask_b = 1,
+ .reg_md_srcclkena_1_mask_b = 0,
+ .reg_md_srcclkena2infra_req_1_mask_b = 0,
+ .reg_md_apsrc2infra_req_1_mask_b = 0,
+ .reg_md_apsrc_req_1_mask_b = 0,
+ .reg_md_vrf18_req_1_mask_b = 0,
+ .reg_md_ddr_en_1_mask_b = 0,
+ .reg_conn_srcclkena_mask_b = 1,
+ .reg_conn_srcclkenb_mask_b = 0,
+ .reg_conn_infra_req_mask_b = 1,
+ .reg_conn_apsrc_req_mask_b = 1,
+ .reg_conn_vrf18_req_mask_b = 1,
+ .reg_conn_ddr_en_mask_b = 1,
+ .reg_conn_vfe28_mask_b = 0,
+ .reg_srcclkeni0_srcclkena_mask_b = 1,
+ .reg_srcclkeni0_infra_req_mask_b = 1,
+ .reg_srcclkeni1_srcclkena_mask_b = 0,
+ .reg_srcclkeni1_infra_req_mask_b = 0,
+ .reg_srcclkeni2_srcclkena_mask_b = 0,
+ .reg_srcclkeni2_infra_req_mask_b = 0,
+ .reg_infrasys_apsrc_req_mask_b = 0,
+ .reg_infrasys_ddr_en_mask_b = 1,
+ .reg_md32_srcclkena_mask_b = 1,
+ .reg_md32_infra_req_mask_b = 1,
+ .reg_md32_apsrc_req_mask_b = 1,
+ .reg_md32_vrf18_req_mask_b = 1,
+ .reg_md32_ddr_en_mask_b = 1,
+
+ /* SPM_SRC2_MASK */
+ .reg_scp_srcclkena_mask_b = 1,
+ .reg_scp_infra_req_mask_b = 1,
+ .reg_scp_apsrc_req_mask_b = 1,
+ .reg_scp_vrf18_req_mask_b = 1,
+ .reg_scp_ddr_en_mask_b = 1,
+ .reg_audio_dsp_srcclkena_mask_b = 1,
+ .reg_audio_dsp_infra_req_mask_b = 1,
+ .reg_audio_dsp_apsrc_req_mask_b = 1,
+ .reg_audio_dsp_vrf18_req_mask_b = 1,
+ .reg_audio_dsp_ddr_en_mask_b = 1,
+ .reg_ufs_srcclkena_mask_b = 1,
+ .reg_ufs_infra_req_mask_b = 1,
+ .reg_ufs_apsrc_req_mask_b = 1,
+ .reg_ufs_vrf18_req_mask_b = 1,
+ .reg_ufs_ddr_en_mask_b = 1,
+ .reg_disp0_apsrc_req_mask_b = 1,
+ .reg_disp0_ddr_en_mask_b = 1,
+ .reg_disp1_apsrc_req_mask_b = 1,
+ .reg_disp1_ddr_en_mask_b = 1,
+ .reg_gce_infra_req_mask_b = 1,
+ .reg_gce_apsrc_req_mask_b = 1,
+ .reg_gce_vrf18_req_mask_b = 1,
+ .reg_gce_ddr_en_mask_b = 1,
+ .reg_apu_srcclkena_mask_b = 1,
+ .reg_apu_infra_req_mask_b = 1,
+ .reg_apu_apsrc_req_mask_b = 1,
+ .reg_apu_vrf18_req_mask_b = 1,
+ .reg_apu_ddr_en_mask_b = 1,
+ .reg_cg_check_srcclkena_mask_b = 0,
+ .reg_cg_check_apsrc_req_mask_b = 0,
+ .reg_cg_check_vrf18_req_mask_b = 0,
+ .reg_cg_check_ddr_en_mask_b = 0,
+
+ /* SPM_SRC3_MASK */
+ .reg_dvfsrc_event_trigger_mask_b = 1,
+ .reg_sw2spm_int0_mask_b = 0,
+ .reg_sw2spm_int1_mask_b = 0,
+ .reg_sw2spm_int2_mask_b = 0,
+ .reg_sw2spm_int3_mask_b = 0,
+ .reg_sc_adsp2spm_wakeup_mask_b = 0,
+ .reg_sc_sspm2spm_wakeup_mask_b = 0,
+ .reg_sc_scp2spm_wakeup_mask_b = 0,
+ .reg_csyspwrreq_mask = 1,
+ .reg_spm_srcclkena_reserved_mask_b = 0,
+ .reg_spm_infra_req_reserved_mask_b = 0,
+ .reg_spm_apsrc_req_reserved_mask_b = 0,
+ .reg_spm_vrf18_req_reserved_mask_b = 0,
+ .reg_spm_ddr_en_reserved_mask_b = 0,
+ .reg_mcupm_srcclkena_mask_b = 1,
+ .reg_mcupm_infra_req_mask_b = 1,
+ .reg_mcupm_apsrc_req_mask_b = 1,
+ .reg_mcupm_vrf18_req_mask_b = 1,
+ .reg_mcupm_ddr_en_mask_b = 1,
+ .reg_msdc0_srcclkena_mask_b = 1,
+ .reg_msdc0_infra_req_mask_b = 1,
+ .reg_msdc0_apsrc_req_mask_b = 1,
+ .reg_msdc0_vrf18_req_mask_b = 1,
+ .reg_msdc0_ddr_en_mask_b = 1,
+ .reg_msdc1_srcclkena_mask_b = 1,
+ .reg_msdc1_infra_req_mask_b = 1,
+ .reg_msdc1_apsrc_req_mask_b = 1,
+ .reg_msdc1_vrf18_req_mask_b = 1,
+ .reg_msdc1_ddr_en_mask_b = 1,
+
+ /* SPM_SRC4_MASK */
+ .ccif_event_mask_b = 0xFFF,
+ .reg_bak_psri_srcclkena_mask_b = 0,
+ .reg_bak_psri_infra_req_mask_b = 0,
+ .reg_bak_psri_apsrc_req_mask_b = 0,
+ .reg_bak_psri_vrf18_req_mask_b = 0,
+ .reg_bak_psri_ddr_en_mask_b = 0,
+ .reg_dramc0_md32_infra_req_mask_b = 1,
+ .reg_dramc0_md32_vrf18_req_mask_b = 0,
+ .reg_dramc1_md32_infra_req_mask_b = 1,
+ .reg_dramc1_md32_vrf18_req_mask_b = 0,
+ .reg_conn_srcclkenb2pwrap_mask_b = 0,
+ .reg_dramc0_md32_wakeup_mask = 1,
+ .reg_dramc1_md32_wakeup_mask = 1,
+
+ /* SPM_SRC5_MASK */
+ .reg_mcusys_merge_apsrc_req_mask_b = 0x11,
+ .reg_mcusys_merge_ddr_en_mask_b = 0x11,
+ .reg_msdc2_srcclkena_mask_b = 1,
+ .reg_msdc2_infra_req_mask_b = 1,
+ .reg_msdc2_apsrc_req_mask_b = 1,
+ .reg_msdc2_vrf18_req_mask_b = 1,
+ .reg_msdc2_ddr_en_mask_b = 1,
+ .reg_pcie_srcclkena_mask_b = 1,
+ .reg_pcie_infra_req_mask_b = 1,
+ .reg_pcie_apsrc_req_mask_b = 1,
+ .reg_pcie_vrf18_req_mask_b = 1,
+ .reg_pcie_ddr_en_mask_b = 1,
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ .reg_wakeup_event_mask = 0x01382202,
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ .reg_ext_wakeup_event_mask = 0xFFFFFFFF,
+
+ /* Auto-gen End */
+};
+
+struct spm_lp_scen __spm_suspend = {
+ .pwrctrl = &suspend_ctrl,
+};
+
+int mt_spm_suspend_mode_set(int mode)
+{
+ if (mode == MT_SPM_SUSPEND_SLEEP) {
+ suspend_ctrl.pcm_flags = SPM_SUSPEND_SLEEP_PCM_FLAG;
+ suspend_ctrl.pcm_flags1 = SPM_SUSPEND_SLEEP_PCM_FLAG1;
+ } else {
+ suspend_ctrl.pcm_flags = SPM_SUSPEND_PCM_FLAG;
+ suspend_ctrl.pcm_flags1 = SPM_SUSPEND_PCM_FLAG1;
+ }
+
+ return 0;
+}
+
+int mt_spm_suspend_enter(int state_id, unsigned int ext_opand,
+ unsigned int resource_req)
+{
+ /* If FMAudio / ADSP is active, change to sleep suspend mode */
+ if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
+ mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SLEEP);
+ }
+
+ /* Notify MCUPM that device is going suspend flow */
+ mmio_write_32(MCUPM_MBOX_OFFSET_PDN, MCUPM_POWER_DOWN);
+
+ /* Notify UART to sleep */
+ mt_uart_save();
+
+ return spm_conservation(state_id, ext_opand,
+ &__spm_suspend, resource_req);
+}
+
+void mt_spm_suspend_resume(int state_id, unsigned int ext_opand,
+ struct wake_status **status)
+{
+ spm_conservation_finish(state_id, ext_opand, &__spm_suspend, status);
+
+ /* Notify UART to wakeup */
+ mt_uart_restore();
+
+ /* Notify MCUPM that device leave suspend */
+ mmio_write_32(MCUPM_MBOX_OFFSET_PDN, 0);
+
+ /* If FMAudio / ADSP is active, change back to suspend mode */
+ if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
+ mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SYSTEM_PDN);
+ }
+}
+
+void mt_spm_suspend_init(void)
+{
+ spm_conservation_pwrctrl_init(__spm_suspend.pwrctrl);
+}
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_suspend.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_suspend.h
new file mode 100644
index 0000000..08bbad2
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_suspend.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_SUSPEND_H
+#define MT_SPM_SUSPEND_H
+
+#include <mt_spm_internal.h>
+
+#define MCUPM_MBOX_OFFSET_PDN 0x0C55FDA8
+#define MCUPM_POWER_DOWN 0x4D50444E
+
+enum MT_SPM_SUSPEND_MODE {
+ MT_SPM_SUSPEND_SYSTEM_PDN,
+ MT_SPM_SUSPEND_SLEEP,
+};
+
+extern int mt_spm_suspend_mode_set(int mode);
+extern int mt_spm_suspend_enter(int state_id, unsigned int ext_opand,
+ unsigned int reosuce_req);
+extern void mt_spm_suspend_resume(int state_id, unsigned int ext_opand,
+ struct wake_status **status);
+extern void mt_spm_suspend_init(void);
+#endif /* MT_SPM_SUSPEND_H */
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_vcorefs.c b/plat/mediatek/mt8192/drivers/spm/mt_spm_vcorefs.c
new file mode 100644
index 0000000..f74ea80
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_vcorefs.c
@@ -0,0 +1,405 @@
+/*
+ * Copyright(C)2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <plat/common/platform.h>
+#include <lib/utils_def.h>
+
+#include <mtk_sip_svc.h>
+#include <plat_pm.h>
+#include <platform_def.h>
+
+#include "mt_spm.h"
+#include "mt_spm_internal.h"
+#include "mt_spm_reg.h"
+#include "mt_spm_vcorefs.h"
+#include "mt_spm_pmic_wrap.h"
+
+#define VCORE_CT_ENABLE (1U << 5)
+#define SW_REQ5_INIT_VAL (6U << 12)
+#define V_VMODE_SHIFT 0
+#define VCORE_HV 105
+#define VCORE_LV 95
+#define PMIC_STEP_UV 6250
+
+static const struct reg_config dvfsrc_init_configs[] = {
+ /* Setup opp table */
+ { DVFSRC_LEVEL_LABEL_0_1, 0x50436053 },
+ { DVFSRC_LEVEL_LABEL_2_3, 0x40335042 },
+ { DVFSRC_LEVEL_LABEL_4_5, 0x40314032 },
+ { DVFSRC_LEVEL_LABEL_6_7, 0x30223023 },
+ { DVFSRC_LEVEL_LABEL_8_9, 0x20133021 },
+ { DVFSRC_LEVEL_LABEL_10_11, 0x20112012 },
+ { DVFSRC_LEVEL_LABEL_12_13, 0x10032010 },
+ { DVFSRC_LEVEL_LABEL_14_15, 0x10011002 },
+ { DVFSRC_LEVEL_LABEL_16_17, 0x00131000 },
+ { DVFSRC_LEVEL_LABEL_18_19, 0x00110012 },
+ { DVFSRC_LEVEL_LABEL_20_21, 0x00000010 },
+
+ /* Setup hw emi qos policy */
+ { DVFSRC_DDR_REQUEST, 0x00004321 },
+ { DVFSRC_DDR_REQUEST3, 0x00000065 },
+
+ /* Setup up for PCIe */
+ { DVFSRC_PCIE_VCORE_REQ, 0x0A298001 },
+
+ /* Setup up HRT QOS policy */
+ { DVFSRC_HRT_BW_BASE, 0x00000004 },
+ { DVFSRC_HRT_REQ_UNIT, 0x0000001E },
+ { DVFSRC_HRT_HIGH_3, 0x18A618A6 },
+ { DVFSRC_HRT_HIGH_2, 0x18A61183 },
+ { DVFSRC_HRT_HIGH_1, 0x0D690B80 },
+ { DVFSRC_HRT_HIGH, 0x070804B0 },
+ { DVFSRC_HRT_LOW_3, 0x18A518A5 },
+ { DVFSRC_HRT_LOW_2, 0x18A51182 },
+ { DVFSRC_HRT_LOW_1, 0x0D680B7F },
+ { DVFSRC_HRT_LOW, 0x070704AF },
+ { DVFSRC_HRT_REQUEST, 0x66654321 },
+ /* Setup up SRT QOS policy */
+ { DVFSRC_QOS_EN, 0x0011007C },
+ { DVFSRC_DDR_QOS0, 0x00000019 },
+ { DVFSRC_DDR_QOS1, 0x00000026 },
+ { DVFSRC_DDR_QOS2, 0x00000033 },
+ { DVFSRC_DDR_QOS3, 0x0000003B },
+ { DVFSRC_DDR_QOS4, 0x0000004C },
+ { DVFSRC_DDR_QOS5, 0x00000066 },
+ { DVFSRC_DDR_QOS6, 0x00000066 },
+ { DVFSRC_DDR_REQUEST5, 0x54321000 },
+ { DVFSRC_DDR_REQUEST7, 0x66000000 },
+ /* Setup up hifi request policy */
+ { DVFSRC_DDR_REQUEST6, 0x66543210 },
+ /* Setup up hw request vcore policy */
+ { DVFSRC_VCORE_USER_REQ, 0x00010A29 },
+
+ /* Setup misc*/
+ { DVFSRC_TIMEOUT_NEXTREQ, 0x00000015 },
+ { DVFSRC_RSRV_5, 0x00000001 },
+ { DVFSRC_INT_EN, 0x00000002 },
+ /* Init opp and enable dvfsrc*/
+ { DVFSRC_CURRENT_FORCE, 0x00000001 },
+ { DVFSRC_BASIC_CONTROL, 0x0298444B },
+ { DVFSRC_BASIC_CONTROL, 0x0298054B },
+ { DVFSRC_CURRENT_FORCE, 0x00000000 },
+};
+
+static struct pwr_ctrl vcorefs_ctrl = {
+ .wake_src = R12_REG_CPU_WAKEUP,
+
+ /* default VCORE DVFS is disabled */
+ .pcm_flags = (SPM_FLAG_RUN_COMMON_SCENARIO |
+ SPM_FLAG_DISABLE_VCORE_DVS |
+ SPM_FLAG_DISABLE_VCORE_DFS),
+
+ /* Auto-gen Start */
+
+ /* SPM_AP_STANDBY_CON */
+ .reg_wfi_op = 0,
+ .reg_wfi_type = 0,
+ .reg_mp0_cputop_idle_mask = 0,
+ .reg_mp1_cputop_idle_mask = 0,
+ .reg_mcusys_idle_mask = 0,
+ .reg_md_apsrc_1_sel = 0,
+ .reg_md_apsrc_0_sel = 0,
+ .reg_conn_apsrc_sel = 0,
+
+ /* SPM_SRC_REQ */
+ .reg_spm_apsrc_req = 0,
+ .reg_spm_f26m_req = 0,
+ .reg_spm_infra_req = 0,
+ .reg_spm_vrf18_req = 0,
+ .reg_spm_ddr_en_req = 1,
+ .reg_spm_dvfs_req = 0,
+ .reg_spm_sw_mailbox_req = 0,
+ .reg_spm_sspm_mailbox_req = 0,
+ .reg_spm_adsp_mailbox_req = 0,
+ .reg_spm_scp_mailbox_req = 0,
+
+ /* SPM_SRC6_MASK */
+ .reg_dpmaif_srcclkena_mask_b = 1,
+ .reg_dpmaif_infra_req_mask_b = 1,
+ .reg_dpmaif_apsrc_req_mask_b = 1,
+ .reg_dpmaif_vrf18_req_mask_b = 1,
+ .reg_dpmaif_ddr_en_mask_b = 1,
+
+ /* SPM_SRC_MASK */
+ .reg_md_srcclkena_0_mask_b = 1,
+ .reg_md_srcclkena2infra_req_0_mask_b = 0,
+ .reg_md_apsrc2infra_req_0_mask_b = 1,
+ .reg_md_apsrc_req_0_mask_b = 1,
+ .reg_md_vrf18_req_0_mask_b = 1,
+ .reg_md_ddr_en_0_mask_b = 1,
+ .reg_md_srcclkena_1_mask_b = 0,
+ .reg_md_srcclkena2infra_req_1_mask_b = 0,
+ .reg_md_apsrc2infra_req_1_mask_b = 0,
+ .reg_md_apsrc_req_1_mask_b = 0,
+ .reg_md_vrf18_req_1_mask_b = 0,
+ .reg_md_ddr_en_1_mask_b = 0,
+ .reg_conn_srcclkena_mask_b = 1,
+ .reg_conn_srcclkenb_mask_b = 0,
+ .reg_conn_infra_req_mask_b = 1,
+ .reg_conn_apsrc_req_mask_b = 1,
+ .reg_conn_vrf18_req_mask_b = 1,
+ .reg_conn_ddr_en_mask_b = 1,
+ .reg_conn_vfe28_mask_b = 0,
+ .reg_srcclkeni0_srcclkena_mask_b = 1,
+ .reg_srcclkeni0_infra_req_mask_b = 1,
+ .reg_srcclkeni1_srcclkena_mask_b = 0,
+ .reg_srcclkeni1_infra_req_mask_b = 0,
+ .reg_srcclkeni2_srcclkena_mask_b = 0,
+ .reg_srcclkeni2_infra_req_mask_b = 0,
+ .reg_infrasys_apsrc_req_mask_b = 0,
+ .reg_infrasys_ddr_en_mask_b = 1,
+ .reg_md32_srcclkena_mask_b = 1,
+ .reg_md32_infra_req_mask_b = 1,
+ .reg_md32_apsrc_req_mask_b = 1,
+ .reg_md32_vrf18_req_mask_b = 1,
+ .reg_md32_ddr_en_mask_b = 1,
+
+ /* SPM_SRC2_MASK */
+ .reg_scp_srcclkena_mask_b = 1,
+ .reg_scp_infra_req_mask_b = 1,
+ .reg_scp_apsrc_req_mask_b = 1,
+ .reg_scp_vrf18_req_mask_b = 1,
+ .reg_scp_ddr_en_mask_b = 1,
+ .reg_audio_dsp_srcclkena_mask_b = 1,
+ .reg_audio_dsp_infra_req_mask_b = 1,
+ .reg_audio_dsp_apsrc_req_mask_b = 1,
+ .reg_audio_dsp_vrf18_req_mask_b = 1,
+ .reg_audio_dsp_ddr_en_mask_b = 1,
+ .reg_ufs_srcclkena_mask_b = 1,
+ .reg_ufs_infra_req_mask_b = 1,
+ .reg_ufs_apsrc_req_mask_b = 1,
+ .reg_ufs_vrf18_req_mask_b = 1,
+ .reg_ufs_ddr_en_mask_b = 1,
+ .reg_disp0_apsrc_req_mask_b = 1,
+ .reg_disp0_ddr_en_mask_b = 1,
+ .reg_disp1_apsrc_req_mask_b = 1,
+ .reg_disp1_ddr_en_mask_b = 1,
+ .reg_gce_infra_req_mask_b = 1,
+ .reg_gce_apsrc_req_mask_b = 1,
+ .reg_gce_vrf18_req_mask_b = 1,
+ .reg_gce_ddr_en_mask_b = 1,
+ .reg_apu_srcclkena_mask_b = 1,
+ .reg_apu_infra_req_mask_b = 1,
+ .reg_apu_apsrc_req_mask_b = 1,
+ .reg_apu_vrf18_req_mask_b = 1,
+ .reg_apu_ddr_en_mask_b = 1,
+ .reg_cg_check_srcclkena_mask_b = 0,
+ .reg_cg_check_apsrc_req_mask_b = 0,
+ .reg_cg_check_vrf18_req_mask_b = 0,
+ .reg_cg_check_ddr_en_mask_b = 0,
+
+ /* SPM_SRC3_MASK */
+ .reg_dvfsrc_event_trigger_mask_b = 1,
+ .reg_sw2spm_int0_mask_b = 0,
+ .reg_sw2spm_int1_mask_b = 0,
+ .reg_sw2spm_int2_mask_b = 0,
+ .reg_sw2spm_int3_mask_b = 0,
+ .reg_sc_adsp2spm_wakeup_mask_b = 0,
+ .reg_sc_sspm2spm_wakeup_mask_b = 0,
+ .reg_sc_scp2spm_wakeup_mask_b = 0,
+ .reg_csyspwrreq_mask = 1,
+ .reg_spm_srcclkena_reserved_mask_b = 0,
+ .reg_spm_infra_req_reserved_mask_b = 0,
+ .reg_spm_apsrc_req_reserved_mask_b = 0,
+ .reg_spm_vrf18_req_reserved_mask_b = 0,
+ .reg_spm_ddr_en_reserved_mask_b = 0,
+ .reg_mcupm_srcclkena_mask_b = 1,
+ .reg_mcupm_infra_req_mask_b = 1,
+ .reg_mcupm_apsrc_req_mask_b = 1,
+ .reg_mcupm_vrf18_req_mask_b = 1,
+ .reg_mcupm_ddr_en_mask_b = 1,
+ .reg_msdc0_srcclkena_mask_b = 1,
+ .reg_msdc0_infra_req_mask_b = 1,
+ .reg_msdc0_apsrc_req_mask_b = 1,
+ .reg_msdc0_vrf18_req_mask_b = 1,
+ .reg_msdc0_ddr_en_mask_b = 1,
+ .reg_msdc1_srcclkena_mask_b = 1,
+ .reg_msdc1_infra_req_mask_b = 1,
+ .reg_msdc1_apsrc_req_mask_b = 1,
+ .reg_msdc1_vrf18_req_mask_b = 1,
+ .reg_msdc1_ddr_en_mask_b = 1,
+
+ /* SPM_SRC4_MASK */
+ .ccif_event_mask_b = 0xFFF,
+ .reg_bak_psri_srcclkena_mask_b = 0,
+ .reg_bak_psri_infra_req_mask_b = 0,
+ .reg_bak_psri_apsrc_req_mask_b = 0,
+ .reg_bak_psri_vrf18_req_mask_b = 0,
+ .reg_bak_psri_ddr_en_mask_b = 0,
+ .reg_dramc0_md32_infra_req_mask_b = 1,
+ .reg_dramc0_md32_vrf18_req_mask_b = 0,
+ .reg_dramc1_md32_infra_req_mask_b = 1,
+ .reg_dramc1_md32_vrf18_req_mask_b = 0,
+ .reg_conn_srcclkenb2pwrap_mask_b = 0,
+ .reg_dramc0_md32_wakeup_mask = 1,
+ .reg_dramc1_md32_wakeup_mask = 1,
+
+ /* SPM_SRC5_MASK */
+ .reg_mcusys_merge_apsrc_req_mask_b = 0x11,
+ .reg_mcusys_merge_ddr_en_mask_b = 0x11,
+ .reg_msdc2_srcclkena_mask_b = 1,
+ .reg_msdc2_infra_req_mask_b = 1,
+ .reg_msdc2_apsrc_req_mask_b = 1,
+ .reg_msdc2_vrf18_req_mask_b = 1,
+ .reg_msdc2_ddr_en_mask_b = 1,
+ .reg_pcie_srcclkena_mask_b = 1,
+ .reg_pcie_infra_req_mask_b = 1,
+ .reg_pcie_apsrc_req_mask_b = 1,
+ .reg_pcie_vrf18_req_mask_b = 1,
+ .reg_pcie_ddr_en_mask_b = 1,
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ .reg_wakeup_event_mask = 0xEFFFFFFF,
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ .reg_ext_wakeup_event_mask = 0xFFFFFFFF,
+
+ /* Auto-gen End */
+};
+
+struct spm_lp_scen __spm_vcorefs = {
+ .pwrctrl = &vcorefs_ctrl,
+};
+
+static void spm_vcorefs_pwarp_cmd(uint64_t cmd, uint64_t val)
+{
+ if (cmd < NR_IDX_ALL) {
+ mt_spm_pmic_wrap_set_cmd(PMIC_WRAP_PHASE_ALLINONE, cmd, val);
+ } else {
+ INFO("cmd out of range!\n");
+ }
+}
+
+void spm_dvfsfw_init(uint64_t boot_up_opp, uint64_t dram_issue)
+{
+ mmio_clrsetbits_32(SPM_DVFS_MISC, SPM_DVFS_FORCE_ENABLE_LSB,
+ SPM_DVFSRC_ENABLE_LSB);
+
+ mmio_write_32(SPM_DVFS_LEVEL, 0x00000001);
+ mmio_write_32(SPM_DVS_DFS_LEVEL, 0x00010001);
+}
+
+void __spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl,
+ const struct pwr_ctrl *src_pwr_ctrl)
+{
+ uint32_t dvfs_mask = SPM_FLAG_DISABLE_VCORE_DVS |
+ SPM_FLAG_DISABLE_VCORE_DFS |
+ SPM_FLAG_ENABLE_VOLTAGE_BIN;
+
+ dest_pwr_ctrl->pcm_flags = (dest_pwr_ctrl->pcm_flags & (~dvfs_mask)) |
+ (src_pwr_ctrl->pcm_flags & dvfs_mask);
+
+ if (dest_pwr_ctrl->pcm_flags_cust > 0U) {
+ dest_pwr_ctrl->pcm_flags_cust =
+ (dest_pwr_ctrl->pcm_flags_cust & (~dvfs_mask)) |
+ (src_pwr_ctrl->pcm_flags & dvfs_mask);
+ }
+}
+
+static void spm_go_to_vcorefs(void)
+{
+ __spm_set_power_control(__spm_vcorefs.pwrctrl);
+ __spm_set_wakeup_event(__spm_vcorefs.pwrctrl);
+ __spm_set_pcm_flags(__spm_vcorefs.pwrctrl);
+ __spm_send_cpu_wakeup_event();
+}
+
+static void dvfsrc_init(void)
+{
+ uint32_t i;
+
+ for (i = 0U; i < ARRAY_SIZE(dvfsrc_init_configs); i++) {
+ mmio_write_32(dvfsrc_init_configs[i].offset,
+ dvfsrc_init_configs[i].val);
+ }
+}
+
+static uint32_t spm_vcorefs_get_efuse_data(void)
+{
+ return mmio_read_32(VCORE_VB_EFUSE);
+}
+
+static uint32_t is_rising_need(void)
+{
+ return ((spm_vcorefs_get_efuse_data() & 0xF) == 11U) ? 1U : 0U;
+}
+
+static void spm_vcorefs_vcore_setting(uint64_t flag)
+{
+ uint32_t dvfs_v_mode, dvfsrc_rsrv, i;
+ uint32_t opp_uv[] = {725000U, 650000U, 600000U, 575000U};
+
+ dvfsrc_rsrv = mmio_read_32(DVFSRC_RSRV_4);
+
+ dvfs_v_mode = (dvfsrc_rsrv >> V_VMODE_SHIFT) & 0x3;
+
+ if (is_rising_need() != 0U) {
+ opp_uv[2] = 625000U;
+ opp_uv[3] = 600000U;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(opp_uv); i++) {
+ if (dvfs_v_mode == 3U) {
+ /* LV */
+ opp_uv[i] = round_down((opp_uv[i] * VCORE_LV) / 100U,
+ PMIC_STEP_UV);
+ } else if (dvfs_v_mode == 1U) {
+ /* HV */
+ opp_uv[i] = round_up((opp_uv[i] * VCORE_HV) / 100U,
+ PMIC_STEP_UV);
+ }
+ spm_vcorefs_pwarp_cmd(i, __vcore_uv_to_pmic(opp_uv[i]));
+ }
+}
+
+uint64_t spm_vcorefs_args(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t *x4)
+{
+ uint64_t cmd = x1;
+ uint64_t spm_flags;
+
+ switch (cmd) {
+ case VCOREFS_SMC_CMD_INIT:
+ /* vcore_dvfs init + kick */
+ mmio_write_32(DVFSRC_SW_REQ5, SW_REQ5_INIT_VAL);
+ spm_dvfsfw_init(0ULL, 0ULL);
+ spm_vcorefs_vcore_setting(x3 & 0xF);
+ spm_flags = SPM_FLAG_RUN_COMMON_SCENARIO;
+ if ((x2 & 0x1) > 0U) {
+ spm_flags |= SPM_FLAG_DISABLE_VCORE_DVS;
+ }
+
+ if ((x2 & 0x2) > 0U) {
+ spm_flags |= SPM_FLAG_DISABLE_VCORE_DFS;
+ }
+
+ if ((mmio_read_32(DVFSRC_RSRV_4) & VCORE_CT_ENABLE) > 0U) {
+ spm_flags |= SPM_FLAG_ENABLE_VOLTAGE_BIN;
+ }
+
+ set_pwrctrl_pcm_flags(__spm_vcorefs.pwrctrl, spm_flags);
+ spm_go_to_vcorefs();
+ dvfsrc_init();
+
+ *x4 = 0U;
+ mmio_write_32(DVFSRC_SW_REQ5, 0U);
+ break;
+ case VCOREFS_SMC_CMD_KICK:
+ mmio_write_32(DVFSRC_SW_REQ5, 0U);
+ break;
+ default:
+ break;
+ }
+
+ return 0ULL;
+}
diff --git a/plat/mediatek/mt8192/drivers/spm/mt_spm_vcorefs.h b/plat/mediatek/mt8192/drivers/spm/mt_spm_vcorefs.h
new file mode 100644
index 0000000..f4e0c48
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/mt_spm_vcorefs.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright(C)2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_VCOREFS_H
+#define MT_SPM_VCOREFS_H
+
+uint64_t spm_vcorefs_args(uint64_t x1, uint64_t x2, uint64_t x3, uint64_t *x4);
+
+enum vcorefs_smc_cmd {
+ VCOREFS_SMC_CMD_0,
+ VCOREFS_SMC_CMD_1,
+ VCOREFS_SMC_CMD_2,
+ VCOREFS_SMC_CMD_3,
+ VCOREFS_SMC_CMD_4,
+ /* check spmfw status */
+ VCOREFS_SMC_CMD_5,
+
+ /* get spmfw type */
+ VCOREFS_SMC_CMD_6,
+
+ /* get spm reg status */
+ VCOREFS_SMC_CMD_7,
+
+ NUM_VCOREFS_SMC_CMD,
+};
+
+enum vcorefs_smc_cmd_new {
+ VCOREFS_SMC_CMD_INIT = 0,
+ VCOREFS_SMC_CMD_KICK = 1,
+};
+
+#define _VCORE_BASE_UV 400000
+#define _VCORE_STEP_UV 6250
+
+/* PMIC */
+#define __vcore_pmic_to_uv(pmic) \
+ (((pmic) * _VCORE_STEP_UV) + _VCORE_BASE_UV)
+
+#define __vcore_uv_to_pmic(uv) /* pmic >= uv */ \
+ ((((uv) - _VCORE_BASE_UV) + (_VCORE_STEP_UV - 1)) / _VCORE_STEP_UV)
+
+struct reg_config {
+ uint32_t offset;
+ uint32_t val;
+};
+
+#define DVFSRC_BASIC_CONTROL (DVFSRC_BASE + 0x0)
+#define DVFSRC_SW_REQ5 (DVFSRC_BASE + 0x14)
+#define DVFSRC_INT_EN (DVFSRC_BASE + 0xC8)
+#define DVFSRC_MD_TURBO (DVFSRC_BASE + 0xDC)
+#define DVFSRC_PCIE_VCORE_REQ (DVFSRC_BASE + 0xE0)
+#define DVFSRC_VCORE_USER_REQ (DVFSRC_BASE + 0xE4)
+#define DVFSRC_TIMEOUT_NEXTREQ (DVFSRC_BASE + 0xF8)
+#define DVFSRC_LEVEL_LABEL_0_1 (DVFSRC_BASE + 0x100)
+#define DVFSRC_LEVEL_LABEL_2_3 (DVFSRC_BASE + 0x104)
+#define DVFSRC_LEVEL_LABEL_4_5 (DVFSRC_BASE + 0x108)
+#define DVFSRC_LEVEL_LABEL_6_7 (DVFSRC_BASE + 0x10C)
+#define DVFSRC_LEVEL_LABEL_8_9 (DVFSRC_BASE + 0x110)
+#define DVFSRC_LEVEL_LABEL_10_11 (DVFSRC_BASE + 0x114)
+#define DVFSRC_LEVEL_LABEL_12_13 (DVFSRC_BASE + 0x118)
+#define DVFSRC_LEVEL_LABEL_14_15 (DVFSRC_BASE + 0x11C)
+#define DVFSRC_QOS_EN (DVFSRC_BASE + 0x280)
+#define DVFSRC_HRT_BW_BASE (DVFSRC_BASE + 0x294)
+#define DVFSRC_RSRV_4 (DVFSRC_BASE + 0x610)
+#define DVFSRC_RSRV_5 (DVFSRC_BASE + 0x614)
+#define DVFSRC_DDR_REQUEST (DVFSRC_BASE + 0xA00)
+#define DVFSRC_DDR_REQUEST2 (DVFSRC_BASE + 0xA04)
+#define DVFSRC_DDR_REQUEST3 (DVFSRC_BASE + 0xA08)
+#define DVFSRC_DDR_REQUEST4 (DVFSRC_BASE + 0xA0C)
+#define DVFSRC_DDR_REQUEST5 (DVFSRC_BASE + 0xA10)
+#define DVFSRC_DDR_REQUEST6 (DVFSRC_BASE + 0xA14)
+#define DVFSRC_DDR_REQUEST7 (DVFSRC_BASE + 0xA18)
+#define DVFSRC_DDR_QOS0 (DVFSRC_BASE + 0xA34)
+#define DVFSRC_DDR_QOS1 (DVFSRC_BASE + 0xA38)
+#define DVFSRC_DDR_QOS2 (DVFSRC_BASE + 0xA3C)
+#define DVFSRC_DDR_QOS3 (DVFSRC_BASE + 0xA40)
+#define DVFSRC_DDR_QOS4 (DVFSRC_BASE + 0xA44)
+#define DVFSRC_HRT_REQ_UNIT (DVFSRC_BASE + 0xA60)
+#define DVFSRC_HRT_REQUEST (DVFSRC_BASE + 0xAC4)
+#define DVFSRC_HRT_HIGH_2 (DVFSRC_BASE + 0xAC8)
+#define DVFSRC_HRT_HIGH_1 (DVFSRC_BASE + 0xACC)
+#define DVFSRC_HRT_HIGH (DVFSRC_BASE + 0xAD0)
+#define DVFSRC_HRT_LOW_2 (DVFSRC_BASE + 0xAD4)
+#define DVFSRC_HRT_LOW_1 (DVFSRC_BASE + 0xAD8)
+#define DVFSRC_HRT_LOW (DVFSRC_BASE + 0xADC)
+#define DVFSRC_DDR_ADD_REQUEST (DVFSRC_BASE + 0xAE0)
+#define DVFSRC_LAST (DVFSRC_BASE + 0xAE4)
+#define DVFSRC_LAST_L (DVFSRC_BASE + 0xAE8)
+#define DVFSRC_MD_SCENARIO (DVFSRC_BASE + 0xAEC)
+#define DVFSRC_RECORD_0_0 (DVFSRC_BASE + 0xAF0)
+#define DVFSRC_RECORD_0_1 (DVFSRC_BASE + 0xAF4)
+#define DVFSRC_RECORD_0_2 (DVFSRC_BASE + 0xAF8)
+#define DVFSRC_RECORD_0_3 (DVFSRC_BASE + 0xAFC)
+#define DVFSRC_RECORD_0_4 (DVFSRC_BASE + 0xB00)
+#define DVFSRC_RECORD_0_5 (DVFSRC_BASE + 0xB04)
+#define DVFSRC_RECORD_0_6 (DVFSRC_BASE + 0xB08)
+#define DVFSRC_RECORD_0_7 (DVFSRC_BASE + 0xB0C)
+#define DVFSRC_RECORD_0_L_0 (DVFSRC_BASE + 0xBF0)
+#define DVFSRC_RECORD_0_L_1 (DVFSRC_BASE + 0xBF4)
+#define DVFSRC_RECORD_0_L_2 (DVFSRC_BASE + 0xBF8)
+#define DVFSRC_RECORD_0_L_3 (DVFSRC_BASE + 0xBFC)
+#define DVFSRC_RECORD_0_L_4 (DVFSRC_BASE + 0xC00)
+#define DVFSRC_RECORD_0_L_5 (DVFSRC_BASE + 0xC04)
+#define DVFSRC_RECORD_0_L_6 (DVFSRC_BASE + 0xC08)
+#define DVFSRC_RECORD_0_L_7 (DVFSRC_BASE + 0xC0C)
+#define DVFSRC_EMI_REQUEST8 (DVFSRC_BASE + 0xCF0)
+#define DVFSRC_DDR_REQUEST8 (DVFSRC_BASE + 0xCF4)
+#define DVFSRC_EMI_HRT_2 (DVFSRC_BASE + 0xCF8)
+#define DVFSRC_EMI_HRT2_2 (DVFSRC_BASE + 0xCFC)
+#define DVFSRC_EMI_HRT3_2 (DVFSRC_BASE + 0xD00)
+#define DVFSRC_EMI_QOS5 (DVFSRC_BASE + 0xD04)
+#define DVFSRC_EMI_QOS6 (DVFSRC_BASE + 0xD08)
+#define DVFSRC_DDR_HRT_2 (DVFSRC_BASE + 0xD0C)
+#define DVFSRC_DDR_HRT2_2 (DVFSRC_BASE + 0xD10)
+#define DVFSRC_DDR_HRT3_2 (DVFSRC_BASE + 0xD14)
+#define DVFSRC_DDR_QOS5 (DVFSRC_BASE + 0xD18)
+#define DVFSRC_DDR_QOS6 (DVFSRC_BASE + 0xD1C)
+#define DVFSRC_HRT_HIGH_3 (DVFSRC_BASE + 0xD38)
+#define DVFSRC_HRT_LOW_3 (DVFSRC_BASE + 0xD3C)
+#define DVFSRC_LEVEL_LABEL_16_17 (DVFSRC_BASE + 0xD4C)
+#define DVFSRC_LEVEL_LABEL_18_19 (DVFSRC_BASE + 0xD50)
+#define DVFSRC_LEVEL_LABEL_20_21 (DVFSRC_BASE + 0xD54)
+#define DVFSRC_LEVEL_LABEL_22_23 (DVFSRC_BASE + 0xD58)
+#define DVFSRC_LEVEL_LABEL_24_25 (DVFSRC_BASE + 0xD5C)
+#define DVFSRC_LEVEL_LABEL_26_27 (DVFSRC_BASE + 0xD60)
+#define DVFSRC_LEVEL_LABEL_28_29 (DVFSRC_BASE + 0xD64)
+#define DVFSRC_LEVEL_LABEL_30_31 (DVFSRC_BASE + 0xD68)
+#define DVFSRC_CURRENT_FORCE (DVFSRC_BASE + 0xD6C)
+
+#define VCORE_VB_EFUSE (0x11C105E8)
+
+#endif /* MT_SPM_VCOREFS_H */
diff --git a/plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_notifier.h b/plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_notifier.h
new file mode 100644
index 0000000..66be7ee
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_notifier.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_SSPM_NOTIFIER_H
+#define MT_SPM_SSPM_NOTIFIER_H
+
+enum MT_SPM_SSPM_NOTIFY_ID {
+ MT_SPM_NOTIFY_LP_ENTER,
+ MT_SPM_NOTIFY_LP_LEAVE,
+};
+
+int mt_spm_sspm_notify(int type, unsigned int lp_mode);
+
+static inline int mt_spm_sspm_notify_u32(int type, unsigned int lp_mode)
+{
+ return mt_spm_sspm_notify(type, lp_mode);
+}
+#endif /* MT_SPM_SSPM_NOTIFIER_H */
diff --git a/plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_sspm_intc.h b/plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_sspm_intc.h
new file mode 100644
index 0000000..452ae90
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_sspm_intc.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_SSPM_INTC_H
+#define MT_SPM_SSPM_INTC_H
+
+#include <mt_spm_reg.h>
+
+#define MT_SPM_SSPM_INTC_SEL_0 0x10
+#define MT_SPM_SSPM_INTC_SEL_1 0x20
+#define MT_SPM_SSPM_INTC_SEL_2 0x40
+#define MT_SPM_SSPM_INTC_SEL_3 0x80
+
+#define MT_SPM_SSPM_INTC_TRIGGER(id, sg) \
+ (((0x10 << id) | (sg << id)) & 0xff)
+
+#define MT_SPM_SSPM_INTC0_HIGH MT_SPM_SSPM_INTC_TRIGGER(0, 1)
+#define MT_SPM_SSPM_INTC0_LOW MT_SPM_SSPM_INTC_TRIGGER(0, 0)
+#define MT_SPM_SSPM_INTC1_HIGH MT_SPM_SSPM_INTC_TRIGGER(1, 1)
+#define MT_SPM_SSPM_INTC1_LOW MT_SPM_SSPM_INTC_TRIGGER(1, 0)
+#define MT_SPM_SSPM_INTC2_HIGH MT_SPM_SSPM_INTC_TRIGGER(2, 1)
+#define MT_SPM_SSPM_INTC2_LOW MT_SPM_SSPM_INTC_TRIGGER(2, 0)
+#define MT_SPM_SSPM_INTC3_HIGH MT_SPM_SSPM_INTC_TRIGGER(3, 1)
+#define MT_SPM_SSPM_INTC3_LOW MT_SPM_SSPM_INTC_TRIGGER(3, 0)
+
+#define DO_SPM_SSPM_LP_SUSPEND() \
+ mmio_write_32(SPM_MD32_IRQ, MT_SPM_SSPM_INTC0_HIGH)
+#define DO_SPM_SSPM_LP_RESUME() \
+ mmio_write_32(SPM_MD32_IRQ, MT_SPM_SSPM_INTC0_LOW)
+#endif /* MT_SPM_SSPM_INTC_H */
diff --git a/plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_sspm_notifier.c b/plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_sspm_notifier.c
new file mode 100644
index 0000000..e0ba037
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/notifier/mt_spm_sspm_notifier.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+
+#include <lib/mmio.h>
+
+#include <mt_spm_notifier.h>
+#include <mt_spm_sspm_intc.h>
+
+#define MT_SPM_SSPM_MBOX_OFF(x) (SSPM_MBOX_BASE + x)
+#define MT_SPM_MBOX(slot) MT_SPM_SSPM_MBOX_OFF((slot << 2UL))
+
+#define SSPM_MBOX_SPM_LP_LOOKUP1 MT_SPM_MBOX(0)
+#define SSPM_MBOX_SPM_LP_LOOKUP2 MT_SPM_MBOX(1)
+#define SSPM_MBOX_SPM_LP1 MT_SPM_MBOX(2)
+#define SSPM_MBOX_SPM_LP2 MT_SPM_MBOX(3)
+
+#define MCUPM_MBOX_OFFSET_LP 0x0C55FDA4
+#define MCUPM_MBOX_ENTER_LP 0x454e0000
+#define MCUPM_MBOX_LEAVE_LP 0x4c450000
+#define MCUPM_MBOX_SLEEP_MASK 0x0000FFFF
+
+int mt_spm_sspm_notify(int type, unsigned int lp_mode)
+{
+ switch (type) {
+ case MT_SPM_NOTIFY_LP_ENTER:
+ mmio_write_32(SSPM_MBOX_SPM_LP1, lp_mode);
+ mmio_write_32(MCUPM_MBOX_OFFSET_LP, MCUPM_MBOX_ENTER_LP |
+ (lp_mode & MCUPM_MBOX_SLEEP_MASK));
+ DO_SPM_SSPM_LP_SUSPEND();
+ break;
+ case MT_SPM_NOTIFY_LP_LEAVE:
+ mmio_write_32(SSPM_MBOX_SPM_LP1, lp_mode);
+ mmio_write_32(MCUPM_MBOX_OFFSET_LP, MCUPM_MBOX_LEAVE_LP |
+ (lp_mode & MCUPM_MBOX_SLEEP_MASK));
+ DO_SPM_SSPM_LP_RESUME();
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
diff --git a/plat/mediatek/mt8192/drivers/spm/pcm_def.h b/plat/mediatek/mt8192/drivers/spm/pcm_def.h
new file mode 100644
index 0000000..ab46b86
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/pcm_def.h
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PCM_DEF_H
+#define PCM_DEF_H
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+
+/* --- R0 Define --- */
+#define R0_SC_26M_CK_OFF (1U << 0)
+#define R0_SC_TX_TRACK_RETRY_EN (1U << 1)
+#define R0_SC_MEM_CK_OFF (1U << 2)
+#define R0_SC_AXI_CK_OFF (1U << 3)
+#define R0_SC_DR_SRAM_LOAD (1U << 4)
+#define R0_SC_MD26M_CK_OFF (1U << 5)
+#define R0_SC_DPY_MODE_SW (1U << 6)
+#define R0_SC_DMSUS_OFF (1U << 7)
+#define R0_SC_DPY_2ND_DLL_EN (1U << 8)
+#define R0_SC_DR_SRAM_RESTORE (1U << 9)
+#define R0_SC_MPLLOUT_OFF (1U << 10)
+#define R0_SC_TX_TRACKING_DIS (1U << 11)
+#define R0_SC_DPY_DLL_EN (1U << 12)
+#define R0_SC_DPY_DLL_CK_EN (1U << 13)
+#define R0_SC_DPY_VREF_EN (1U << 14)
+#define R0_SC_PHYPLL_EN (1U << 15)
+#define R0_SC_DDRPHY_FB_CK_EN (1U << 16)
+#define R0_SC_DPY_BCLK_ENABLE (1U << 17)
+#define R0_SC_MPLL_OFF (1U << 18)
+#define R0_SC_SHU_RESTORE (1U << 19)
+#define R0_SC_CKSQ0_OFF (1U << 20)
+#define R0_SC_DR_SHU_LEVEL_SRAM_LATCH (1U << 21)
+#define R0_SC_DR_SHU_EN (1U << 22)
+#define R0_SC_DPHY_PRECAL_UP (1U << 23)
+#define R0_SC_MPLL_S_OFF (1U << 24)
+#define R0_SC_DPHY_RXDLY_TRACKING_EN (1U << 25)
+#define R0_SC_PHYPLL_SHU_EN (1U << 26)
+#define R0_SC_PHYPLL2_SHU_EN (1U << 27)
+#define R0_SC_PHYPLL_MODE_SW (1U << 28)
+#define R0_SC_PHYPLL2_MODE_SW (1U << 29)
+#define R0_SC_DR_SHU_LEVEL0 (1U << 30)
+#define R0_SC_DR_SHU_LEVEL1 (1U << 31)
+/* --- R7 Define --- */
+#define R7_PWRAP_SLEEP_REQ (1U << 0)
+#define R7_EMI_CLK_OFF_REQ (1U << 1)
+#define R7_PCM_BUS_PROTECT_REQ (1U << 2)
+#define R7_SPM_CK_UPDATE (1U << 3)
+#define R7_SPM_CK_SEL0 (1U << 4)
+#define R7_SPM_CK_SEL1 (1U << 5)
+#define R7_SPM_LEAVE_DEEPIDLE_REQ (1U << 6)
+#define R7_SC_FHC_PAUSE_MPLL (1U << 7)
+#define R7_SC_26M_CK_SEL (1U << 8)
+#define R7_PCM_TIMER_SET (1U << 9)
+#define R7_PCM_TIMER_CLR (1U << 10)
+#define R7_SPM_LEAVE_SUSPEND_REQ (1U << 11)
+#define R7_CSYSPWRUPACK (1U << 12)
+#define R7_PCM_IM_SLP_EN (1U << 13)
+#define R7_SRCCLKENO0 (1U << 14)
+#define R7_FORCE_DDR_EN_WAKE (1U << 15)
+#define R7_SPM_APSRC_INTERNAL_ACK (1U << 16)
+#define R7_CPU_SYS_TIMER_CLK_SEL (1U << 17)
+#define R7_SC_AXI_DCM_DIS (1U << 18)
+#define R7_SC_FHC_PAUSE_MEM (1U << 19)
+#define R7_SC_FHC_PAUSE_MAIN (1U << 20)
+#define R7_SRCCLKENO1 (1U << 21)
+#define R7_PCM_WDT_KICK_P (1U << 22)
+#define R7_SPM2EMI_S1_MODE_ASYNC (1U << 23)
+#define R7_SC_DDR_PST_REQ_PCM (1U << 24)
+#define R7_SC_DDR_PST_ABORT_REQ_PCM (1U << 25)
+#define R7_PMIC_IRQ_REQ_EN (1U << 26)
+#define R7_FORCE_F26M_WAKE (1U << 27)
+#define R7_FORCE_APSRC_WAKE (1U << 28)
+#define R7_FORCE_INFRA_WAKE (1U << 29)
+#define R7_FORCE_VRF18_WAKE (1U << 30)
+#define R7_SPM_DDR_EN_INTERNAL_ACK (1U << 31)
+/* --- R12 Define --- */
+#define R12_PCM_TIMER (1U << 0)
+#define R12_TWAM_IRQ_B (1U << 1)
+#define R12_KP_IRQ_B (1U << 2)
+#define R12_APWDT_EVENT_B (1U << 3)
+#define R12_APXGPT1_EVENT_B (1U << 4)
+#define R12_CONN2AP_SPM_WAKEUP_B (1U << 5)
+#define R12_EINT_EVENT_B (1U << 6)
+#define R12_CONN_WDT_IRQ_B (1U << 7)
+#define R12_CCIF0_EVENT_B (1U << 8)
+#define R12_LOWBATTERY_IRQ_B (1U << 9)
+#define R12_SSPM2SPM_WAKEUP_B (1U << 10)
+#define R12_SCP2SPM_WAKEUP_B (1U << 11)
+#define R12_ADSP2SPM_WAKEUP_B (1U << 12)
+#define R12_PCM_WDT_WAKEUP_B (1U << 13)
+#define R12_USBX_CDSC_B (1U << 14)
+#define R12_USBX_POWERDWN_B (1U << 15)
+#define R12_SYS_TIMER_EVENT_B (1U << 16)
+#define R12_EINT_EVENT_SECURE_B (1U << 17)
+#define R12_CCIF1_EVENT_B (1U << 18)
+#define R12_UART0_IRQ_B (1U << 19)
+#define R12_AFE_IRQ_MCU_B (1U << 20)
+#define R12_THERM_CTRL_EVENT_B (1U << 21)
+#define R12_SYS_CIRQ_IRQ_B (1U << 22)
+#define R12_MD2AP_PEER_EVENT_B (1U << 23)
+#define R12_CSYSPWREQ_B (1U << 24)
+#define R12_MD1_WDT_B (1U << 25)
+#define R12_CLDMA_EVENT_B (1U << 26)
+#define R12_SEJ_EVENT_B (1U << 27)
+#define R12_REG_CPU_WAKEUP (1U << 28)
+#define R12_APUSYS_WAKE_HOST_B (1U << 29)
+#define R12_PCIE_BRIDGE_IRQ (1U << 30)
+#define R12_PCIE_IRQ (1U << 31)
+/* --- R12ext Define --- */
+#define R12EXT_26M_WAKE (1U << 0)
+#define R12EXT_26M_SLEEP (1U << 1)
+#define R12EXT_INFRA_WAKE (1U << 2)
+#define R12EXT_INFRA_SLEEP (1U << 3)
+#define R12EXT_APSRC_WAKE (1U << 4)
+#define R12EXT_APSRC_SLEEP (1U << 5)
+#define R12EXT_VRF18_WAKE (1U << 6)
+#define R12EXT_VRF18_SLEEP (1U << 7)
+#define R12EXT_DVFS_WAKE (1U << 8)
+#define R12EXT_DDREN_WAKE (1U << 9)
+#define R12EXT_DDREN_SLEEP (1U << 10)
+#define R12EXT_MCU_PM_WFI (1U << 11)
+#define R12EXT_SSPM_IDLE (1U << 12)
+#define R12EXT_CONN_SRCCLKENB (1U << 13)
+#define R12EXT_DRAMC_SSPM_WFI_MERGE (1U << 14)
+#define R12EXT_SW_MAILBOX_WAKE (1U << 15)
+#define R12EXT_SSPM_MAILBOX_WAKE (1U << 16)
+#define R12EXT_ADSP_MAILBOX_WAKE (1U << 17)
+#define R12EXT_SCP_MAILBOX_WAKE (1U << 18)
+#define R12EXT_SPM_LEAVE_SUSPEND_ACK (1U << 19)
+#define R12EXT_SPM_LEAVE_DEEPIDLE_ACK (1U << 20)
+#define R12EXT_VS1_TRIGGER (1U << 21)
+#define R12EXT_VS2_TRIGGER (1U << 22)
+#define R12EXT_COROSS_REQ_APU (1U << 23)
+#define R12EXT_CROSS_REQ_L3 (1U << 24)
+#define R12EXT_DDR_PST_ACK (1U << 25)
+#define R12EXT_BIT26 (1U << 26)
+#define R12EXT_BIT27 (1U << 27)
+#define R12EXT_BIT28 (1U << 28)
+#define R12EXT_BIT29 (1U << 29)
+#define R12EXT_BIT30 (1U << 30)
+#define R12EXT_BIT31 (1U << 31)
+/* --- R13 Define --- */
+#define R13_SRCCLKENI0 (1U << 0)
+#define R13_SRCCLKENI1 (1U << 1)
+#define R13_MD_SRCCLKENA_0 (1U << 2)
+#define R13_MD_APSRC_REQ_0 (1U << 3)
+#define R13_CONN_DDR_EN (1U << 4)
+#define R13_MD_SRCCLKENA_1 (1U << 5)
+#define R13_SSPM_SRCCLKENA (1U << 6)
+#define R13_SSPM_APSRC_REQ (1U << 7)
+#define R13_MD1_STATE (1U << 8)
+#define R13_BIT9 (1U << 9)
+#define R13_MM_STATE (1U << 10)
+#define R13_SSPM_STATE (1U << 11)
+#define R13_MD_DDR_EN_0 (1U << 12)
+#define R13_CONN_STATE (1U << 13)
+#define R13_CONN_SRCCLKENA (1U << 14)
+#define R13_CONN_APSRC_REQ (1U << 15)
+#define R13_SC_DDR_PST_ACK_ALL (1U << 16)
+#define R13_SC_DDR_PST_ABORT_ACK_ALL (1U << 17)
+#define R13_SCP_STATE (1U << 18)
+#define R13_CSYSPWRUPREQ (1U << 19)
+#define R13_PWRAP_SLEEP_ACK (1U << 20)
+#define R13_SC_EMI_CLK_OFF_ACK_ALL (1U << 21)
+#define R13_AUDIO_DSP_STATE (1U << 22)
+#define R13_SC_DMDRAMCSHU_ACK_ALL (1U << 23)
+#define R13_CONN_SRCCLKENB (1U << 24)
+#define R13_SC_DR_SRAM_LOAD_ACK_ALL (1U << 25)
+#define R13_SUBSYS_IDLE_SIGNALS0 (1U << 26)
+#define R13_DVFS_STATE (1U << 27)
+#define R13_SC_DR_SRAM_PLL_LOAD_ACK_ALL (1U << 28)
+#define R13_SC_DR_SRAM_RESTORE_ACK_ALL (1U << 29)
+#define R13_MD_VRF18_REQ_0 (1U << 30)
+#define R13_DDR_EN_STATE (1U << 31)
+#endif /* PCM_DEF_H */
diff --git a/plat/mediatek/mt8192/drivers/spm/sleep_def.h b/plat/mediatek/mt8192/drivers/spm/sleep_def.h
new file mode 100644
index 0000000..6c5cbed
--- /dev/null
+++ b/plat/mediatek/mt8192/drivers/spm/sleep_def.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SLEEP_DEF_H
+#define SLEEP_DEF_H
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+
+/* --- SPM Flag Define --- */
+#define SPM_FLAG_DISABLE_CPU_PDN (1U << 0)
+#define SPM_FLAG_DISABLE_INFRA_PDN (1U << 1)
+#define SPM_FLAG_DISABLE_DDRPHY_PDN (1U << 2)
+#define SPM_FLAG_DISABLE_VCORE_DVS (1U << 3)
+#define SPM_FLAG_DISABLE_VCORE_DFS (1U << 4)
+#define SPM_FLAG_DISABLE_COMMON_SCENARIO (1U << 5)
+#define SPM_FLAG_DISABLE_BUS_CLK_OFF (1U << 6)
+#define SPM_FLAG_DISABLE_ARMPLL_OFF (1U << 7)
+#define SPM_FLAG_KEEP_CSYSPWRACK_HIGH (1U << 8)
+#define SPM_FLAG_ENABLE_LVTS_WORKAROUND (1U << 9)
+#define SPM_FLAG_RUN_COMMON_SCENARIO (1U << 10)
+#define SPM_FLAG_RESERVED_BIT11 (1U << 11)
+#define SPM_FLAG_ENABLE_SPM_DBG_WDT_DUMP (1U << 12)
+#define SPM_FLAG_USE_SRCCLKENO2 (1U << 13)
+#define SPM_FLAG_ENABLE_6315_CTRL (1U << 14)
+#define SPM_FLAG_ENABLE_TIA_WORKAROUND (1U << 15)
+#define SPM_FLAG_DISABLE_SYSRAM_SLEEP (1U << 16)
+#define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP (1U << 17)
+#define SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP (1U << 18)
+#define SPM_FLAG_ENABLE_MD_MUMTAS (1U << 19)
+#define SPM_FLAG_ENABLE_VOLTAGE_BIN (1U << 20)
+#define SPM_FLAG_RESERVED_BIT21 (1U << 21)
+#define SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP (1U << 22)
+#define SPM_FLAG_DISABLE_SRAM_EVENT (1U << 23)
+#define SPM_FLAG_RESERVED_BIT24 (1U << 24)
+#define SPM_FLAG_RESERVED_BIT25 (1U << 25)
+#define SPM_FLAG_RESERVED_BIT26 (1U << 26)
+#define SPM_FLAG_VTCXO_STATE (1U << 27)
+#define SPM_FLAG_INFRA_STATE (1U << 28)
+#define SPM_FLAG_APSRC_STATE (1U << 29)
+#define SPM_FLAG_VRF18_STATE (1U << 30)
+#define SPM_FLAG_DDREN_STATE (1U << 31)
+/* --- SPM Flag1 Define --- */
+#define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M (1U << 0)
+#define SPM_FLAG1_DISABLE_SYSPLL_OFF (1U << 1)
+#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH (1U << 2)
+#define SPM_FLAG1_DISABLE_ULPOSC_OFF (1U << 3)
+#define SPM_FLAG1_FW_SET_ULPOSC_ON (1U << 4)
+#define SPM_FLAG1_RESERVED_BIT5 (1U << 5)
+#define SPM_FLAG1_ENABLE_REKICK (1U << 6)
+#define SPM_FLAG1_DISABLE_MD26M_CK_OFF (1U << 7)
+#define SPM_FLAG1_RESERVED_BIT8 (1U << 8)
+#define SPM_FLAG1_RESERVED_BIT9 (1U << 9)
+#define SPM_FLAG1_DISABLE_SRCLKEN_LOW (1U << 10)
+#define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH (1U << 11)
+#define SPM_FLAG1_RESERVED_BIT12 (1U << 12)
+#define SPM_FLAG1_RESERVED_BIT13 (1U << 13)
+#define SPM_FLAG1_RESERVED_BIT14 (1U << 14)
+#define SPM_FLAG1_RESERVED_BIT15 (1U << 15)
+#define SPM_FLAG1_RESERVED_BIT16 (1U << 16)
+#define SPM_FLAG1_RESERVED_BIT17 (1U << 17)
+#define SPM_FLAG1_RESERVED_BIT18 (1U << 18)
+#define SPM_FLAG1_RESERVED_BIT19 (1U << 19)
+#define SPM_FLAG1_DISABLE_DEVAPC_SRAM_SLEEP (1U << 20)
+#define SPM_FLAG1_RESERVED_BIT21 (1U << 21)
+#define SPM_FLAG1_ENABLE_VS1_VOTER (1U << 22)
+#define SPM_FLAG1_ENABLE_VS2_VOTER (1U << 23)
+#define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CONTROL (1U << 24)
+#define SPM_FLAG1_RESERVED_BIT25 (1U << 25)
+#define SPM_FLAG1_RESERVED_BIT26 (1U << 26)
+#define SPM_FLAG1_RESERVED_BIT27 (1U << 27)
+#define SPM_FLAG1_RESERVED_BIT28 (1U << 28)
+#define SPM_FLAG1_RESERVED_BIT29 (1U << 29)
+#define SPM_FLAG1_RESERVED_BIT30 (1U << 30)
+#define SPM_FLAG1_DISABLE_CPUEB_OFF (1U << 31)
+/* --- SPM DEBUG Define --- */
+#define SPM_DBG_DEBUG_IDX_26M_WAKE (1U << 0)
+#define SPM_DBG_DEBUG_IDX_26M_SLEEP (1U << 1)
+#define SPM_DBG_DEBUG_IDX_INFRA_WAKE (1U << 2)
+#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP (1U << 3)
+#define SPM_DBG_DEBUG_IDX_APSRC_WAKE (1U << 4)
+#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP (1U << 5)
+#define SPM_DBG_DEBUG_IDX_VRF18_WAKE (1U << 6)
+#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP (1U << 7)
+#define SPM_DBG_DEBUG_IDX_DDREN_WAKE (1U << 8)
+#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP (1U << 9)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC (1U << 10)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_STATE (1U << 11)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_STATE (1U << 12)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN (1U << 13)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_STATE (1U << 14)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_SLP (1U << 15)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_ON (1U << 16)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_SLP (1U << 17)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_ON (1U << 18)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP (1U << 19)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_ON (1U << 20)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_SLP (1U << 21)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_ON (1U << 22)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P575V (1U << 23)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P600V (1U << 24)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P650V (1U << 25)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P725V (1U << 26)
+#define SPM_DBG_DEBUG_IDX_SPM_GO_WAKEUP_NOW (1U << 27)
+#define SPM_DBG_DEBUG_IDX_VTCXO_STATE (1U << 28)
+#define SPM_DBG_DEBUG_IDX_INFRA_STATE (1U << 29)
+#define SPM_DBG_DEBUG_IDX_VRR18_STATE (1U << 30)
+#define SPM_DBG_DEBUG_IDX_APSRC_STATE (1U << 31)
+/* --- SPM DEBUG1 Define --- */
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_LP (1U << 0)
+#define SPM_DBG1_DEBUG_IDX_VCORE_DVFS_START (1U << 1)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_OFF (1U << 2)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_ON (1U << 3)
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_VCORE_DVFS (1U << 4)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_OFF (1U << 5)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_ON (1U << 6)
+#define SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT (1U << 7)
+#define SPM_DBG1_RESERVED_BIT8 (1U << 8)
+#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_OFF (1U << 9)
+#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_ON (1U << 10)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_ULPOSC (1U << 11)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_26M (1U << 12)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_32K (1U << 13)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_26M (1U << 14)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_OFF (1U << 15)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_ON (1U << 16)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_LOW (1U << 17)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_HIGH (1U << 18)
+#define SPM_DBG1_RESERVED_BIT19 (1U << 19)
+#define SPM_DBG1_DEBUG_IDX_ULPOSC_IS_OFF_BUT_SHOULD_ON (1U << 20)
+#define SPM_DBG1_DEBUG_IDX_6315_LOW (1U << 21)
+#define SPM_DBG1_DEBUG_IDX_6315_HIGH (1U << 22)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT (1U << 23)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT (1U << 24)
+#define SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT (1U << 25)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT (1U << 26)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT (1U << 27)
+#define SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT (1U << 28)
+#define SPM_DBG1_RESERVED_BIT29 (1U << 29)
+#define SPM_DBG1_RESERVED_BIT30 (1U << 30)
+#define SPM_DBG1_DEBUG_DISABLE_CPUEB_OFF (1U << 31)
+
+ /* Macro and Inline */
+#define is_cpu_pdn(flags) (((flags) & SPM_FLAG_DISABLE_CPU_PDN) == 0U)
+#define is_infra_pdn(flags) (((flags) & SPM_FLAG_DISABLE_INFRA_PDN) == 0U)
+#define is_ddrphy_pdn(flags) (((flags) & SPM_FLAG_DISABLE_DDRPHY_PDN) == 0U)
+#endif /* SLEEP_DEF_H */
diff --git a/plat/mediatek/mt8192/include/plat_mt_cirq.h b/plat/mediatek/mt8192/include/plat_mt_cirq.h
deleted file mode 100644
index bb8b457..0000000
--- a/plat/mediatek/mt8192/include/plat_mt_cirq.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLAT_MT_CIRQ_H
-#define PLAT_MT_CIRQ_H
-
-#include <stdint.h>
-
-enum {
- IRQ_MASK_HEADER = 0xF1F1F1F1,
- IRQ_MASK_FOOTER = 0xF2F2F2F2
-};
-
-struct mtk_irq_mask {
- uint32_t header; /* for error checking */
- uint32_t mask0;
- uint32_t mask1;
- uint32_t mask2;
- uint32_t mask3;
- uint32_t mask4;
- uint32_t mask5;
- uint32_t mask6;
- uint32_t mask7;
- uint32_t mask8;
- uint32_t mask9;
- uint32_t mask10;
- uint32_t mask11;
- uint32_t mask12;
- uint32_t footer; /* for error checking */
-};
-
-/*
- * Define hardware register
- */
-
-#define SYS_CIRQ_BASE U(0x10204000)
-#define CIRQ_REG_NUM U(14)
-#define CIRQ_IRQ_NUM U(439)
-#define CIRQ_SPI_START U(64)
-#define MD_WDT_IRQ_BIT_ID U(110)
-
-#define CIRQ_STA_BASE (SYS_CIRQ_BASE + U(0x000))
-#define CIRQ_ACK_BASE (SYS_CIRQ_BASE + U(0x080))
-#define CIRQ_MASK_BASE (SYS_CIRQ_BASE + U(0x100))
-#define CIRQ_MASK_SET_BASE (SYS_CIRQ_BASE + U(0x180))
-#define CIRQ_MASK_CLR_BASE (SYS_CIRQ_BASE + U(0x200))
-#define CIRQ_SENS_BASE (SYS_CIRQ_BASE + U(0x280))
-#define CIRQ_SENS_SET_BASE (SYS_CIRQ_BASE + U(0x300))
-#define CIRQ_SENS_CLR_BASE (SYS_CIRQ_BASE + U(0x380))
-#define CIRQ_POL_BASE (SYS_CIRQ_BASE + U(0x400))
-#define CIRQ_POL_SET_BASE (SYS_CIRQ_BASE + U(0x480))
-#define CIRQ_POL_CLR_BASE (SYS_CIRQ_BASE + U(0x500))
-#define CIRQ_CON (SYS_CIRQ_BASE + U(0x600))
-
-/*
- * Register placement
- */
-#define CIRQ_CON_EN_BITS U(0)
-#define CIRQ_CON_EDGE_ONLY_BITS U(1)
-#define CIRQ_CON_FLUSH_BITS U(2)
-#define CIRQ_CON_SW_RST_BITS U(20)
-#define CIRQ_CON_EVENT_BITS U(31)
-#define CIRQ_CON_BITS_MASK U(0x7)
-
-/*
- * Register setting
- */
-#define CIRQ_CON_EN U(0x1)
-#define CIRQ_CON_EDGE_ONLY U(0x1)
-#define CIRQ_CON_FLUSH U(0x1)
-#define CIRQ_SW_RESET U(0x1)
-
-/*
- * Define constant
- */
-#define CIRQ_CTRL_REG_NUM ((CIRQ_IRQ_NUM + 31U) / 32U)
-
-#define MT_CIRQ_POL_NEG U(0)
-#define MT_CIRQ_POL_POS U(1)
-
-#define IRQ_TO_CIRQ_NUM(irq) ((irq) - (32U + CIRQ_SPI_START))
-#define CIRQ_TO_IRQ_NUM(cirq) ((cirq) + (32U + CIRQ_SPI_START))
-
-/* GIC sensitive */
-#define SENS_EDGE U(0x2)
-#define SENS_LEVEL U(0x1)
-
-
-/*
- * Define function prototypes.
- */
-int mt_cirq_test(void);
-void mt_cirq_dump_reg(void);
-int mt_irq_mask_restore(struct mtk_irq_mask *mask);
-int mt_irq_mask_all(struct mtk_irq_mask *mask);
-void mt_cirq_clone_gic(void);
-void mt_cirq_enable(void);
-void mt_cirq_flush(void);
-void mt_cirq_disable(void);
-void mt_irq_unmask_for_sleep_ex(uint32_t irq);
-void set_wakeup_sources(uint32_t *list, uint32_t num_of_events);
-void mt_cirq_sw_reset(void);
-
-struct cirq_reg {
- uint32_t reg_num;
- uint32_t used;
- uint32_t mask;
- uint32_t pol;
- uint32_t sen;
- uint32_t pending;
- uint32_t the_link;
-};
-
-struct cirq_events {
- uint32_t num_reg;
- uint32_t spi_start;
- uint32_t num_of_events;
- uint32_t *wakeup_events;
- struct cirq_reg table[CIRQ_REG_NUM];
- uint32_t dist_base;
- uint32_t cirq_base;
- uint32_t used_reg_head;
-};
-
-#endif /* PLAT_MT_CIRQ_H */
diff --git a/plat/mediatek/mt8192/include/plat_mtk_lpm.h b/plat/mediatek/mt8192/include/plat_mtk_lpm.h
index 8ba8b93..deaac97 100644
--- a/plat/mediatek/mt8192/include/plat_mtk_lpm.h
+++ b/plat/mediatek/mt8192/include/plat_mtk_lpm.h
@@ -10,7 +10,7 @@
#include <lib/psci/psci.h>
#include <lib/utils_def.h>
-#define MT_IRQ_REMAIN_MAX U(8)
+#define MT_IRQ_REMAIN_MAX U(32)
#define MT_IRQ_REMAIN_CAT_LOG BIT(31)
struct mt_irqremain {
diff --git a/plat/mediatek/mt8192/include/plat_sip_calls.h b/plat/mediatek/mt8192/include/plat_sip_calls.h
index 0e42322..f68a4ea 100644
--- a/plat/mediatek/mt8192/include/plat_sip_calls.h
+++ b/plat/mediatek/mt8192/include/plat_sip_calls.h
@@ -10,6 +10,10 @@
/*******************************************************************************
* Plat SiP function constants
******************************************************************************/
-#define MTK_PLAT_SIP_NUM_CALLS 0
+#define MTK_PLAT_SIP_NUM_CALLS 2
+
+/* DFD */
+#define MTK_SIP_KERNEL_DFD_AARCH32 0x82000205
+#define MTK_SIP_KERNEL_DFD_AARCH64 0xC2000205
#endif /* PLAT_SIP_CALLS_H */
diff --git a/plat/mediatek/mt8192/include/platform_def.h b/plat/mediatek/mt8192/include/platform_def.h
index 3e44414..ec377b5 100644
--- a/plat/mediatek/mt8192/include/platform_def.h
+++ b/plat/mediatek/mt8192/include/platform_def.h
@@ -26,21 +26,40 @@
#define MTK_MCDI_SRAM_BASE 0x11B000
#define MTK_MCDI_SRAM_MAP_SIZE 0x1000
-#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
-#define GPIO_BASE (IO_PHYS + 0x00005000)
-#define SPM_BASE (IO_PHYS + 0x00006000)
-#define PMIC_WRAP_BASE (IO_PHYS + 0x00026000)
-#define EMI_BASE (IO_PHYS + 0x00219000)
-#define EMI_MPU_BASE (IO_PHYS + 0x00226000)
-#define IOCFG_RM_BASE (IO_PHYS + 0x01C20000)
-#define IOCFG_BM_BASE (IO_PHYS + 0x01D10000)
-#define IOCFG_BL_BASE (IO_PHYS + 0x01D30000)
-#define IOCFG_BR_BASE (IO_PHYS + 0x01D40000)
-#define IOCFG_LM_BASE (IO_PHYS + 0x01E20000)
-#define IOCFG_LB_BASE (IO_PHYS + 0x01E70000)
-#define IOCFG_RT_BASE (IO_PHYS + 0x01EA0000)
-#define IOCFG_LT_BASE (IO_PHYS + 0x01F20000)
-#define IOCFG_TL_BASE (IO_PHYS + 0x01F30000)
+#define APUSYS_BASE 0x19000000
+#define APUSYS_SCTRL_REVISER_BASE 0x19021000
+#define APUSYS_SCTRL_REVISER_SIZE 0x1000
+#define APUSYS_APU_S_S_4_BASE 0x190F2000
+#define APUSYS_APU_S_S_4_SIZE 0x1000
+#define APUSYS_APC_AO_WRAPPER_BASE 0x190F8000
+#define APUSYS_APC_AO_WRAPPER_SIZE 0x1000
+#define APUSYS_NOC_DAPC_AO_BASE 0x190FC000
+#define APUSYS_NOC_DAPC_AO_SIZE 0x1000
+
+#define TOPCKGEN_BASE (IO_PHYS + 0x00000000)
+#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
+#define GPIO_BASE (IO_PHYS + 0x00005000)
+#define SPM_BASE (IO_PHYS + 0x00006000)
+#define APMIXEDSYS (IO_PHYS + 0x0000C000)
+#define DVFSRC_BASE (IO_PHYS + 0x00012000)
+#define PMIC_WRAP_BASE (IO_PHYS + 0x00026000)
+#define DEVAPC_INFRA_AO_BASE (IO_PHYS + 0x00030000)
+#define DEVAPC_PERI_AO_BASE (IO_PHYS + 0x00034000)
+#define DEVAPC_PERI_AO2_BASE (IO_PHYS + 0x00038000)
+#define DEVAPC_PERI_PAR_AO_BASE (IO_PHYS + 0x0003C000)
+#define EMI_BASE (IO_PHYS + 0x00219000)
+#define EMI_MPU_BASE (IO_PHYS + 0x00226000)
+#define SSPM_MBOX_BASE (IO_PHYS + 0x00480000)
+#define IOCFG_RM_BASE (IO_PHYS + 0x01C20000)
+#define IOCFG_BM_BASE (IO_PHYS + 0x01D10000)
+#define IOCFG_BL_BASE (IO_PHYS + 0x01D30000)
+#define IOCFG_BR_BASE (IO_PHYS + 0x01D40000)
+#define IOCFG_LM_BASE (IO_PHYS + 0x01E20000)
+#define IOCFG_LB_BASE (IO_PHYS + 0x01E70000)
+#define IOCFG_RT_BASE (IO_PHYS + 0x01EA0000)
+#define IOCFG_LT_BASE (IO_PHYS + 0x01F20000)
+#define IOCFG_TL_BASE (IO_PHYS + 0x01F30000)
+#define MMSYS_BASE (IO_PHYS + 0x04000000)
/*******************************************************************************
* UART related constants
******************************************************************************/
@@ -56,13 +75,19 @@
#define SYS_COUNTER_FREQ_IN_MHZ 13
/*******************************************************************************
- * GIC-400 & interrupt handling related constants
+ * GIC-600 & interrupt handling related constants
******************************************************************************/
/* Base MTK_platform compatible GIC memory map */
#define BASE_GICD_BASE MT_GIC_BASE
#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
+#define SYS_CIRQ_BASE (IO_PHYS + 0x204000)
+#define CIRQ_REG_NUM 14
+#define CIRQ_IRQ_NUM 439
+#define CIRQ_SPI_START 64
+#define MD_WDT_IRQ_BIT_ID 110
+
/*******************************************************************************
* Platform binary types for linking
******************************************************************************/
diff --git a/plat/mediatek/mt8192/include/rtc.h b/plat/mediatek/mt8192/include/rtc.h
new file mode 100644
index 0000000..a9c7bc8
--- /dev/null
+++ b/plat/mediatek/mt8192/include/rtc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RTC_H
+#define RTC_H
+
+#include <rtc_mt6359p.h>
+
+#endif /* RTC_H */
diff --git a/plat/mediatek/mt8192/plat_mt_cirq.c b/plat/mediatek/mt8192/plat_mt_cirq.c
deleted file mode 100644
index 9002b7e..0000000
--- a/plat/mediatek/mt8192/plat_mt_cirq.c
+++ /dev/null
@@ -1,552 +0,0 @@
-/*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch_helpers.h>
-#include <common/debug.h>
-#include <drivers/arm/gic_common.h>
-#include <lib/mmio.h>
-
-#include <mt_gic_v3.h>
-#include <plat_mt_cirq.h>
-#include <platform_def.h>
-
-static struct cirq_events cirq_all_events = {
- .spi_start = CIRQ_SPI_START,
-};
-static uint32_t already_cloned;
-/*
- * mt_irq_mask_restore: restore all interrupts
- * @mask: pointer to struct mtk_irq_mask for storing the original mask value.
- * Return 0 for success; return negative values for failure.
- * (This is ONLY used for the idle current measurement by the factory mode.)
- */
-int mt_irq_mask_restore(struct mtk_irq_mask *mask)
-{
- if (mask == NULL) {
- return -1;
- }
- if (mask->header != IRQ_MASK_HEADER) {
- return -1;
- }
- if (mask->footer != IRQ_MASK_FOOTER) {
- return -1;
- }
-
- mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x4),
- mask->mask1);
- mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x8),
- mask->mask2);
- mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0xc),
- mask->mask3);
- mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x10),
- mask->mask4);
- mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x14),
- mask->mask5);
- mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x18),
- mask->mask6);
- mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x1c),
- mask->mask7);
- mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x20),
- mask->mask8);
- mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x24),
- mask->mask9);
- mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x28),
- mask->mask10);
- mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x2c),
- mask->mask11);
- mmio_write_32((BASE_GICD_BASE + GICD_ISENABLER + 0x30),
- mask->mask12);
- /* make sure dist changes happen */
- dsb();
-
- return 0;
-}
-
-/*
- * mt_irq_mask_all: disable all interrupts
- * @mask: pointer to struct mtk_irq_mask for storing the original mask value.
- * Return 0 for success; return negative values for failure.
- * (This is ONLY used for the idle current measurement by the factory mode.)
- */
-int mt_irq_mask_all(struct mtk_irq_mask *mask)
-{
- if (mask != NULL) {
- /* for SPI */
- mask->mask1 = mmio_read_32((BASE_GICD_BASE +
- GICD_ISENABLER + 0x4));
- mask->mask2 = mmio_read_32((BASE_GICD_BASE +
- GICD_ISENABLER + 0x8));
- mask->mask3 = mmio_read_32((BASE_GICD_BASE +
- GICD_ISENABLER + 0xc));
- mask->mask4 = mmio_read_32((BASE_GICD_BASE +
- GICD_ISENABLER + 0x10));
- mask->mask5 = mmio_read_32((BASE_GICD_BASE +
- GICD_ISENABLER + 0x14));
- mask->mask6 = mmio_read_32((BASE_GICD_BASE +
- GICD_ISENABLER + 0x18));
- mask->mask7 = mmio_read_32((BASE_GICD_BASE +
- GICD_ISENABLER + 0x1c));
- mask->mask8 = mmio_read_32((BASE_GICD_BASE +
- GICD_ISENABLER + 0x20));
- mask->mask9 = mmio_read_32((BASE_GICD_BASE +
- GICD_ISENABLER + 0x24));
- mask->mask10 = mmio_read_32((BASE_GICD_BASE +
- GICD_ISENABLER + 0x28));
- mask->mask11 = mmio_read_32((BASE_GICD_BASE +
- GICD_ISENABLER + 0x2c));
- mask->mask12 = mmio_read_32((BASE_GICD_BASE +
- GICD_ISENABLER + 0x30));
-
- /* for SPI */
- mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x4),
- 0xFFFFFFFF);
- mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x8),
- 0xFFFFFFFF);
- mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0xC),
- 0xFFFFFFFF);
- mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x10),
- 0xFFFFFFFF);
- mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x14),
- 0xFFFFFFFF);
- mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x18),
- 0xFFFFFFFF);
- mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x1C),
- 0xFFFFFFFF);
- mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x20),
- 0xFFFFFFFF);
- mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x24),
- 0xFFFFFFFF);
- mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x28),
- 0xFFFFFFFF);
- mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x2c),
- 0xFFFFFFFF);
- mmio_write_32((BASE_GICD_BASE + GICD_ICENABLER + 0x30),
- 0xFFFFFFFF);
- /* make sure distributor changes happen */
- dsb();
-
- mask->header = IRQ_MASK_HEADER;
- mask->footer = IRQ_MASK_FOOTER;
-
- return 0;
- } else {
- return -1;
- }
-}
-
-static uint32_t mt_irq_get_pol(uint32_t irq)
-{
-#ifdef CIRQ_WITH_POLARITY
- uint32_t reg;
- uint32_t base = INT_POL_CTL0;
-
- if (irq < 32U) {
- return 0;
- }
-
- reg = ((irq - 32U) / 32U);
-
- return mmio_read_32(base + reg * 4U);
-#else
- return 0;
-#endif
-}
-
-unsigned int mt_irq_get_sens(unsigned int irq)
-{
- unsigned int config;
-
- /*
- * 2'b10 edge
- * 2'b01 level
- */
- config = mmio_read_32(MT_GIC_BASE + GICD_ICFGR + (irq / 16U) * 4U);
- config = (config >> (irq % 16U) * 2U) & 0x3;
-
- return config;
-}
-
-static void collect_all_wakeup_events(void)
-{
- unsigned int i;
- uint32_t gic_irq;
- uint32_t cirq;
- uint32_t cirq_reg;
- uint32_t cirq_offset;
- uint32_t mask;
- uint32_t pol_mask;
- uint32_t irq_offset;
- uint32_t irq_mask;
-
- if ((cirq_all_events.wakeup_events == NULL) ||
- cirq_all_events.num_of_events == 0U) {
- return;
- }
-
- for (i = 0U; i < cirq_all_events.num_of_events; i++) {
- if (cirq_all_events.wakeup_events[i] > 0U) {
- gic_irq = cirq_all_events.wakeup_events[i];
- cirq = gic_irq - cirq_all_events.spi_start - 32U;
- cirq_reg = cirq / 32U;
- cirq_offset = cirq % 32U;
- mask = 0x1 << cirq_offset;
- irq_offset = gic_irq % 32U;
- irq_mask = 0x1 << irq_offset;
- /*
- * CIRQ default masks all
- */
- cirq_all_events.table[cirq_reg].mask |= mask;
- /*
- * CIRQ default pol is low
- */
- pol_mask = mt_irq_get_pol(
- cirq_all_events.wakeup_events[i])
- & irq_mask;
- /*
- * 0 means rising
- */
- if (pol_mask == 0U) {
- cirq_all_events.table[cirq_reg].pol |= mask;
- }
- /*
- * CIRQ could monitor edge/level trigger
- * cirq register (0: edge, 1: level)
- */
- if (mt_irq_get_sens(cirq_all_events.wakeup_events[i])
- == SENS_EDGE) {
- cirq_all_events.table[cirq_reg].sen |= mask;
- }
-
- cirq_all_events.table[cirq_reg].used = 1U;
- cirq_all_events.table[cirq_reg].reg_num = cirq_reg;
- }
- }
-}
-
-/*
- * mt_cirq_set_pol: Set the polarity for the specified SYS_CIRQ number.
- * @cirq_num: the SYS_CIRQ number to set
- * @pol: polarity to set
- * @return:
- * 0: set pol success
- * -1: cirq num is out of range
- */
-#ifdef CIRQ_WITH_POLARITY
-static int mt_cirq_set_pol(uint32_t cirq_num, uint32_t pol)
-{
- uint32_t base;
- uint32_t bit = 1U << (cirq_num % 32U);
-
- if (cirq_num >= CIRQ_IRQ_NUM) {
- return -1;
- }
-
- if (pol == MT_CIRQ_POL_NEG) {
- base = (cirq_num / 32U) * 4U + CIRQ_POL_CLR_BASE;
- } else if (pol == MT_CIRQ_POL_POS) {
- base = (cirq_num / 32U) * 4U + CIRQ_POL_SET_BASE;
- } else {
- return -1;
- }
-
- mmio_write_32(base, bit);
- return 0;
-}
-#endif
-
-/*
- * mt_cirq_mask: Mask the specified SYS_CIRQ.
- * @cirq_num: the SYS_CIRQ number to mask
- * @return:
- * 0: mask success
- * -1: cirq num is out of range
- */
-static int mt_cirq_mask(uint32_t cirq_num)
-{
- uint32_t bit = 1U << (cirq_num % 32U);
-
- if (cirq_num >= CIRQ_IRQ_NUM) {
- return -1;
- }
-
- mmio_write_32((cirq_num / 32U) * 4U + CIRQ_MASK_SET_BASE, bit);
-
- return 0;
-}
-
-/*
- * mt_cirq_unmask: Unmask the specified SYS_CIRQ.
- * @cirq_num: the SYS_CIRQ number to unmask
- * @return:
- * 0: umask success
- * -1: cirq num is out of range
- */
-static int mt_cirq_unmask(uint32_t cirq_num)
-{
- uint32_t bit = 1U << (cirq_num % 32U);
-
- if (cirq_num >= CIRQ_IRQ_NUM) {
- return -1;
- }
-
- mmio_write_32((cirq_num / 32U) * 4U + CIRQ_MASK_CLR_BASE, bit);
-
- return 0;
-}
-
-uint32_t mt_irq_get_en(uint32_t irq)
-{
- uint32_t addr, st, val;
-
- addr = BASE_GICD_BASE + GICD_ISENABLER + (irq / 32U) * 4U;
- st = mmio_read_32(addr);
-
- val = (st >> (irq % 32U)) & 1U;
-
- return val;
-}
-
-static void __cirq_fast_clone(void)
-{
- struct cirq_reg *reg;
- unsigned int i;
-
- for (i = 0U; i < CIRQ_REG_NUM ; ++i) {
- uint32_t cirq_bit;
-
- reg = &cirq_all_events.table[i];
-
- if (reg->used == 0U) {
- continue;
- }
-
- mmio_write_32(CIRQ_SENS_CLR_BASE + (reg->reg_num * 4U),
- reg->sen);
-
- for (cirq_bit = 0U; cirq_bit < 32U; ++cirq_bit) {
- uint32_t val, cirq_id;
- uint32_t gic_id;
-#ifdef CIRQ_WITH_POLARITY
- uint32_t gic_bit, pol;
-#endif
- uint32_t en;
-
- val = ((1U << cirq_bit) & reg->mask);
-
- if (val == 0U) {
- continue;
- }
-
- cirq_id = (reg->reg_num << 5U) + cirq_bit;
- gic_id = CIRQ_TO_IRQ_NUM(cirq_id);
-#ifdef CIRQ_WITH_POLARITY
- gic_bit = (0x1U << ((gic_id - 32U) % 32U));
- pol = mt_irq_get_pol(gic_id) & gic_bit;
- if (pol != 0U) {
- mt_cirq_set_pol(cirq_id, MT_CIRQ_POL_NEG);
- } else {
- mt_cirq_set_pol(cirq_id, MT_CIRQ_POL_POS);
- }
-#endif
- en = mt_irq_get_en(gic_id);
- if (en == 1U) {
- mt_cirq_unmask(cirq_id);
- } else {
- mt_cirq_mask(cirq_id);
- }
- }
- }
-}
-
-static void cirq_fast_clone(void)
-{
- if (already_cloned == 0U) {
- collect_all_wakeup_events();
- already_cloned = 1U;
- }
- __cirq_fast_clone();
-}
-
-void set_wakeup_sources(uint32_t *list, uint32_t num_of_events)
-{
- cirq_all_events.num_of_events = num_of_events;
- cirq_all_events.wakeup_events = list;
-}
-/*
- * mt_cirq_clone_gic: Copy the setting from GIC to SYS_CIRQ
- */
-void mt_cirq_clone_gic(void)
-{
- cirq_fast_clone();
-}
-
-uint32_t mt_irq_get_pending_vec(uint32_t start_irq)
-{
- uint32_t base = 0U;
- uint32_t pending_vec = 0U;
- uint32_t reg = start_irq / 32U;
- uint32_t LSB_num, MSB_num;
- uint32_t LSB_vec, MSB_vec;
-
- base = BASE_GICD_BASE;
-
- /* if start_irq is not aligned 32, do some assembling */
- MSB_num = start_irq % 32U;
- if (MSB_num != 0U) {
- LSB_num = 32U - MSB_num;
- LSB_vec = mmio_read_32(base + GICD_ISPENDR +
- reg * 4U) >> MSB_num;
- MSB_vec = mmio_read_32(base + GICD_ISPENDR +
- (reg + 1U) * 4U) << LSB_num;
- pending_vec = MSB_vec | LSB_vec;
- } else {
- pending_vec = mmio_read_32(base + GICD_ISPENDR + reg * 4);
- }
-
- return pending_vec;
-}
-
-static int mt_cirq_get_mask_vec(unsigned int i)
-{
- return mmio_read_32((i * 4U) + CIRQ_MASK_BASE);
-}
-
-/*
- * mt_cirq_ack_all: Ack all the interrupt on SYS_CIRQ
- */
-void mt_cirq_ack_all(void)
-{
- uint32_t ack_vec, pend_vec, mask_vec;
- unsigned int i;
-
- for (i = 0; i < CIRQ_CTRL_REG_NUM; i++) {
- /*
- * if a irq is pending & not masked, don't ack it
- * , since cirq start irq might not be 32 aligned with gic,
- * need an exotic API to get proper vector of pending irq
- */
- pend_vec = mt_irq_get_pending_vec(CIRQ_SPI_START
- + (i + 1U) * 32U);
- mask_vec = mt_cirq_get_mask_vec(i);
- /* those should be acked are: "not (pending & not masked)",
- */
- ack_vec = (~pend_vec) | mask_vec;
- mmio_write_32(CIRQ_ACK_BASE + (i * 4U), ack_vec);
- }
-
- /*
- * make sure all cirq setting take effect
- * before doing other things
- */
- dsb();
-}
-/*
- * mt_cirq_enable: Enable SYS_CIRQ
- */
-void mt_cirq_enable(void)
-{
- uint32_t st;
-
- /* level only */
- mt_cirq_ack_all();
-
- st = mmio_read_32(CIRQ_CON);
- /*
- * CIRQ could monitor edge/level trigger
- */
- st |= (CIRQ_CON_EN << CIRQ_CON_EN_BITS);
-
- mmio_write_32(CIRQ_CON, (st & CIRQ_CON_BITS_MASK));
-}
-
-/*
- * mt_cirq_disable: Disable SYS_CIRQ
- */
-void mt_cirq_disable(void)
-{
- uint32_t st;
-
- st = mmio_read_32(CIRQ_CON);
- st &= ~(CIRQ_CON_EN << CIRQ_CON_EN_BITS);
- mmio_write_32(CIRQ_CON, (st & CIRQ_CON_BITS_MASK));
-}
-
-void mt_irq_unmask_for_sleep_ex(uint32_t irq)
-{
- uint32_t mask;
-
- mask = 1U << (irq % 32U);
-
- mmio_write_32(BASE_GICD_BASE + GICD_ISENABLER +
- ((irq / 32U) * 4U), mask);
-}
-
-void mt_cirq_mask_all(void)
-{
- unsigned int i;
-
- for (i = 0U; i < CIRQ_CTRL_REG_NUM; i++) {
- mmio_write_32(CIRQ_MASK_SET_BASE + (i * 4U), 0xFFFFFFFF);
- }
- dsb();
-}
-
-static void cirq_fast_sw_flush(void)
-{
- struct cirq_reg *reg;
- unsigned int i;
-
- for (i = 0U; i < CIRQ_REG_NUM ; ++i) {
- uint32_t cirq_bit;
-
- reg = &cirq_all_events.table[i];
-
- if (reg->used == 0U) {
- continue;
- }
-
- reg->pending = mmio_read_32(CIRQ_STA_BASE +
- (reg->reg_num << 2U));
- reg->pending &= reg->mask;
-
- for (cirq_bit = 0U; cirq_bit < 32U; ++cirq_bit) {
- uint32_t val, cirq_id;
-
- val = (1U << cirq_bit) & reg->pending;
- if (val == 0U) {
- continue;
- }
-
- cirq_id = (reg->reg_num << 5U) + cirq_bit;
- mt_irq_set_pending(CIRQ_TO_IRQ_NUM(cirq_id));
- if (CIRQ_TO_IRQ_NUM(cirq_id) == MD_WDT_IRQ_BIT_ID) {
- INFO("Set MD_WDT_IRQ pending in %s\n",
- __func__);
- }
- }
- }
-}
-
-/*
- * mt_cirq_disable: Flush interrupt from SYS_CIRQ to GIC
- */
-void mt_cirq_flush(void)
-{
- cirq_fast_sw_flush();
- mt_cirq_mask_all();
- mt_cirq_ack_all();
-}
-
-void mt_cirq_sw_reset(void)
-{
-#ifdef CIRQ_NEED_SW_RESET
- uint32_t st;
-
- st = mmio_read_32(CIRQ_CON);
- st |= (CIRQ_SW_RESET << CIRQ_CON_SW_RST_BITS);
- mmio_write_32(CIRQ_CON, st);
-#endif
-}
diff --git a/plat/mediatek/mt8192/plat_pm.c b/plat/mediatek/mt8192/plat_pm.c
index 6a74c02..018e418 100644
--- a/plat/mediatek/mt8192/plat_pm.c
+++ b/plat/mediatek/mt8192/plat_pm.c
@@ -17,6 +17,7 @@
#include <mtk_ptp3_common.h>
#include <mtspmc.h>
#include <plat/common/platform.h>
+#include <plat_dfd.h>
#include <plat_mtk_lpm.h>
#include <plat_params.h>
#include <plat_pm.h>
@@ -87,11 +88,6 @@
coordinate_cluster_pwron();
- /* Enable the GIC CPU interface */
- gicv3_rdistif_on(cpu);
- gicv3_cpuif_enable(cpu);
- mt_gic_rdistif_init();
-
/*
* If mcusys does power down before then restore
* all CPUs' GIC Redistributors
@@ -99,6 +95,9 @@
if (IS_MCUSYS_OFF_STATE(state)) {
mt_gic_rdistif_restore_all();
} else {
+ gicv3_rdistif_on(cpu);
+ gicv3_cpuif_enable(cpu);
+ mt_gic_rdistif_init();
mt_gic_rdistif_restore();
}
@@ -170,6 +169,8 @@
mt_gic_distif_restore();
gic_sgi_restore_all();
+ dfd_resume();
+
plat_mt_pm_invoke_no_check(pwr_mcusys_on_finished, cpu, state);
}
diff --git a/plat/mediatek/mt8192/plat_sip_calls.c b/plat/mediatek/mt8192/plat_sip_calls.c
index f97684f..353faf8 100644
--- a/plat/mediatek/mt8192/plat_sip_calls.c
+++ b/plat/mediatek/mt8192/plat_sip_calls.c
@@ -6,6 +6,11 @@
#include <common/debug.h>
#include <common/runtime_svc.h>
+#include <mtk_apusys.h>
+#include <mtk_sip_svc.h>
+#include <mt_spm_vcorefs.h>
+#include <plat_dfd.h>
+#include "plat_sip_calls.h"
uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
u_register_t x1,
@@ -16,8 +21,25 @@
void *handle,
u_register_t flags)
{
+ uint64_t ret;
+ uint32_t rnd_val0 = 0U;
switch (smc_fid) {
+ case MTK_SIP_VCORE_CONTROL_ARCH32:
+ case MTK_SIP_VCORE_CONTROL_ARCH64:
+ ret = spm_vcorefs_args(x1, x2, x3, (uint64_t *)&x4);
+ SMC_RET2(handle, ret, x4);
+ break;
+ case MTK_SIP_APUSYS_CONTROL_AARCH32:
+ case MTK_SIP_APUSYS_CONTROL_AARCH64:
+ ret = apusys_kernel_ctrl(x1, x2, x3, x4, &rnd_val0);
+ SMC_RET2(handle, ret, rnd_val0);
+ break;
+ case MTK_SIP_KERNEL_DFD_AARCH32:
+ case MTK_SIP_KERNEL_DFD_AARCH64:
+ ret = dfd_smc_dispatcher(x1, x2, x3, x4);
+ SMC_RET1(handle, ret);
+ break;
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
break;
diff --git a/plat/mediatek/mt8192/platform.mk b/plat/mediatek/mt8192/platform.mk
index a5e7ee2..cbdaadd 100644
--- a/plat/mediatek/mt8192/platform.mk
+++ b/plat/mediatek/mt8192/platform.mk
@@ -8,18 +8,24 @@
MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
+ -I${MTK_PLAT}/common/drivers/gic600/ \
+ -I${MTK_PLAT}/common/drivers/gpio/ \
+ -I${MTK_PLAT}/common/drivers/rtc/ \
+ -I${MTK_PLAT}/common/drivers/timer/ \
+ -I${MTK_PLAT}/common/drivers/uart/ \
+ -I${MTK_PLAT}/common/lpm/ \
-I${MTK_PLAT_SOC}/include/ \
-I${MTK_PLAT_SOC}/drivers/ \
+ -I${MTK_PLAT_SOC}/drivers/apusys/ \
-I${MTK_PLAT_SOC}/drivers/dcm \
+ -I${MTK_PLAT_SOC}/drivers/devapc \
+ -I${MTK_PLAT_SOC}/drivers/dfd \
-I${MTK_PLAT_SOC}/drivers/emi_mpu/ \
-I${MTK_PLAT_SOC}/drivers/gpio/ \
-I${MTK_PLAT_SOC}/drivers/mcdi/ \
-I${MTK_PLAT_SOC}/drivers/pmic/ \
-I${MTK_PLAT_SOC}/drivers/ptp3/ \
- -I${MTK_PLAT_SOC}/drivers/rtc/ \
- -I${MTK_PLAT_SOC}/drivers/spmc/ \
- -I${MTK_PLAT_SOC}/drivers/timer/ \
- -I${MTK_PLAT_SOC}/drivers/uart/
+ -I${MTK_PLAT_SOC}/drivers/spmc/
GICV3_SUPPORT_GIC600 := 1
include drivers/arm/gic/v3/gicv3.mk
@@ -39,9 +45,15 @@
lib/cpus/aarch64/cortex_a55.S \
lib/cpus/aarch64/cortex_a76.S \
plat/common/plat_gicv3.c \
+ ${MTK_PLAT}/common/drivers/gic600/mt_gic_v3.c \
+ ${MTK_PLAT}/common/drivers/gpio/mtgpio_common.c \
${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init_v2.c \
${MTK_PLAT}/common/drivers/rtc/rtc_common.c \
+ ${MTK_PLAT}/common/drivers/rtc/rtc_mt6359p.c \
+ ${MTK_PLAT}/common/drivers/timer/mt_timer.c \
${MTK_PLAT}/common/drivers/uart/uart.c \
+ ${MTK_PLAT}/common/lpm/mt_lp_rm.c \
+ ${MTK_PLAT}/common/mtk_cirq.c \
${MTK_PLAT}/common/mtk_plat_common.c \
${MTK_PLAT}/common/mtk_sip_svc.c \
${MTK_PLAT}/common/params_setup.c \
@@ -49,22 +61,26 @@
${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
${MTK_PLAT_SOC}/bl31_plat_setup.c \
${MTK_PLAT_SOC}/drivers/pmic/pmic.c \
- ${MTK_PLAT_SOC}/drivers/rtc/rtc.c \
${MTK_PLAT_SOC}/plat_pm.c \
${MTK_PLAT_SOC}/plat_topology.c \
- ${MTK_PLAT_SOC}/plat_mt_gic.c \
- ${MTK_PLAT_SOC}/plat_mt_cirq.c \
${MTK_PLAT_SOC}/plat_sip_calls.c \
+ ${MTK_PLAT_SOC}/drivers/apusys/mtk_apusys.c \
+ ${MTK_PLAT_SOC}/drivers/apusys/mtk_apusys_apc.c \
${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c \
${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c \
+ ${MTK_PLAT_SOC}/drivers/devapc/devapc.c \
+ ${MTK_PLAT_SOC}/drivers/dfd/plat_dfd.c \
${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c \
${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c \
+ ${MTK_PLAT_SOC}/drivers/mcdi/mt_lp_irqremain.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_mcdi.c \
${MTK_PLAT_SOC}/drivers/ptp3/mtk_ptp3_main.c \
- ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \
- ${MTK_PLAT_SOC}/drivers/timer/mt_timer.c
+ ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c
+
+# Build SPM drivers
+include ${MTK_PLAT_SOC}/drivers/spm/build.mk
# Configs for A76 and A55
HW_ASSISTED_COHERENCY := 1
diff --git a/plat/mediatek/mt8195/aarch64/plat_helpers.S b/plat/mediatek/mt8195/aarch64/plat_helpers.S
new file mode 100644
index 0000000..a973f4d
--- /dev/null
+++ b/plat/mediatek/mt8195/aarch64/plat_helpers.S
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <platform_def.h>
+
+ .globl plat_is_my_cpu_primary
+ .globl plat_my_core_pos
+ .globl plat_mediatek_calc_core_pos
+
+func plat_is_my_cpu_primary
+ mrs x0, mpidr_el1
+ and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
+ cmp x0, #PLAT_PRIMARY_CPU
+ cset x0, eq
+ ret
+endfunc plat_is_my_cpu_primary
+
+ /* -----------------------------------------------------
+ * unsigned int plat_my_core_pos(void)
+ * This function uses the plat_mediatek_calc_core_pos()
+ * definition to get the index of the calling CPU.
+ * -----------------------------------------------------
+ */
+func plat_my_core_pos
+ mrs x0, mpidr_el1
+ b plat_mediatek_calc_core_pos
+endfunc plat_my_core_pos
+
+ /* -----------------------------------------------------
+ * unsigned int plat_mediatek_calc_core_pos(u_register_t mpidr);
+ *
+ * In ARMv8.2, AFF2 is cluster id, AFF1 is core id and
+ * AFF0 is thread id. There is only one cluster in ARMv8.2
+ * and one thread in current implementation.
+ *
+ * With this function: CorePos = CoreID (AFF1)
+ * we do it with x0 = (x0 >> 8) & 0xff
+ * -----------------------------------------------------
+ */
+func plat_mediatek_calc_core_pos
+ mov x1, #MPIDR_AFFLVL_MASK
+ and x0, x1, x0, lsr #MPIDR_AFF1_SHIFT
+ ret
+endfunc plat_mediatek_calc_core_pos
diff --git a/plat/mediatek/mt8195/aarch64/platform_common.c b/plat/mediatek/mt8195/aarch64/platform_common.c
new file mode 100644
index 0000000..4792746
--- /dev/null
+++ b/plat/mediatek/mt8195/aarch64/platform_common.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/xlat_tables/xlat_tables_v2.h>
+
+#include <platform_def.h>
+
+/* Table of regions to map using the MMU. */
+const mmap_region_t plat_mmap[] = {
+ /* for TF text, RO, RW */
+ MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(MTK_MCDI_SRAM_BASE, MTK_MCDI_SRAM_MAP_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(DP_SEC_BASE, DP_SEC_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(eDP_SEC_BASE, eDP_SEC_SIZE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+ { 0 }
+};
+
+/*******************************************************************************
+ * Macro generating the code for the function setting up the pagetables as per
+ * the platform memory map & initialize the mmu, for the given exception level
+ ******************************************************************************/
+void plat_configure_mmu_el3(uintptr_t total_base,
+ uintptr_t total_size,
+ uintptr_t ro_start,
+ uintptr_t ro_limit)
+{
+ mmap_add_region(total_base, total_base, total_size,
+ MT_RW_DATA | MT_SECURE);
+ mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
+ MT_CODE | MT_SECURE);
+ mmap_add(plat_mmap);
+ init_xlat_tables();
+ enable_mmu_el3(0);
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+ return SYS_COUNTER_FREQ_IN_TICKS;
+}
diff --git a/plat/mediatek/mt8195/bl31_plat_setup.c b/plat/mediatek/mt8195/bl31_plat_setup.c
new file mode 100644
index 0000000..8745454
--- /dev/null
+++ b/plat/mediatek/mt8195/bl31_plat_setup.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* System Includes */
+#include <assert.h>
+
+/* Project Includes */
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <common/desc_image_load.h>
+#include <drivers/generic_delay_timer.h>
+#include <drivers/ti/uart/uart_16550.h>
+#include <lib/coreboot.h>
+
+/* Platform Includes */
+#include <mt_gic_v3.h>
+#include <mt_spm.h>
+#include <mt_timer.h>
+#include <mtk_dcm.h>
+#include <mtgpio.h>
+#include <plat_params.h>
+#include <plat_private.h>
+
+static entry_point_info_t bl32_ep_info;
+static entry_point_info_t bl33_ep_info;
+
+/*******************************************************************************
+ * Return a pointer to the 'entry_point_info' structure of the next image for
+ * the security state specified. BL33 corresponds to the non-secure image type
+ * while BL32 corresponds to the secure image type. A NULL pointer is returned
+ * if the image does not exist.
+ ******************************************************************************/
+entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
+{
+ entry_point_info_t *next_image_info;
+
+ next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
+ assert(next_image_info->h.type == PARAM_EP);
+
+ /* None of the images on this platform can have 0x0 as the entrypoint */
+ if (next_image_info->pc) {
+ return next_image_info;
+ } else {
+ return NULL;
+ }
+}
+
+/*******************************************************************************
+ * Perform any BL31 early platform setup. Here is an opportunity to copy
+ * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
+ * are lost (potentially). This needs to be done before the MMU is initialized
+ * so that the memory layout can be used while creating page tables.
+ * BL2 has flushed this information to memory, so we are guaranteed to pick up
+ * good data.
+ ******************************************************************************/
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
+{
+ static console_t console;
+
+ params_early_setup(arg1);
+
+#if COREBOOT
+ if (coreboot_serial.type) {
+ console_16550_register(coreboot_serial.baseaddr,
+ coreboot_serial.input_hertz,
+ coreboot_serial.baud,
+ &console);
+ }
+#else
+ console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console);
+#endif
+
+ NOTICE("MT8195 bl31_setup\n");
+
+ bl31_params_parse_helper(arg0, &bl32_ep_info, &bl33_ep_info);
+}
+
+
+/*******************************************************************************
+ * Perform any BL31 platform setup code
+ ******************************************************************************/
+void bl31_platform_setup(void)
+{
+ /* Set dcm on */
+ if (!dcm_set_default()) {
+ ERROR("Failed to set default dcm on!!\n");
+ }
+
+ /* Initialize the GIC driver, CPU and distributor interfaces */
+ mt_gic_driver_init();
+ mt_gic_init();
+
+ mt_gpio_init();
+ mt_systimer_init();
+ generic_delay_timer_init();
+ spm_boot_init();
+}
+
+/*******************************************************************************
+ * Perform the very early platform specific architectural setup here. At the
+ * moment this is only intializes the mmu in a quick and dirty way.
+ ******************************************************************************/
+void bl31_plat_arch_setup(void)
+{
+ plat_configure_mmu_el3(BL31_START,
+ BL31_END - BL31_START,
+ BL_CODE_BASE,
+ BL_CODE_END);
+}
diff --git a/plat/mediatek/mt8195/drivers/dcm/mtk_dcm.c b/plat/mediatek/mt8195/drivers/dcm/mtk_dcm.c
new file mode 100644
index 0000000..aed0833
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/dcm/mtk_dcm.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mtk_dcm.h>
+#include <mtk_dcm_utils.h>
+
+static void dcm_armcore(bool mode)
+{
+ dcm_mp_cpusys_top_bus_pll_div_dcm(mode);
+ dcm_mp_cpusys_top_cpu_pll_div_0_dcm(mode);
+ dcm_mp_cpusys_top_cpu_pll_div_1_dcm(mode);
+}
+
+static void dcm_mcusys(bool on)
+{
+ dcm_mp_cpusys_top_adb_dcm(on);
+ dcm_mp_cpusys_top_apb_dcm(on);
+ dcm_mp_cpusys_top_cpubiu_dcm(on);
+ dcm_mp_cpusys_top_misc_dcm(on);
+ dcm_mp_cpusys_top_mp0_qdcm(on);
+ dcm_cpccfg_reg_emi_wfifo(on);
+ dcm_mp_cpusys_top_last_cor_idle_dcm(on);
+}
+
+static void dcm_stall(bool on)
+{
+ dcm_mp_cpusys_top_core_stall_dcm(on);
+ dcm_mp_cpusys_top_fcm_stall_dcm(on);
+}
+
+static bool check_dcm_state(void)
+{
+ bool ret = true;
+
+ ret &= dcm_mp_cpusys_top_bus_pll_div_dcm_is_on();
+ ret &= dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on();
+ ret &= dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on();
+
+ ret &= dcm_mp_cpusys_top_adb_dcm_is_on();
+ ret &= dcm_mp_cpusys_top_apb_dcm_is_on();
+ ret &= dcm_mp_cpusys_top_cpubiu_dcm_is_on();
+ ret &= dcm_mp_cpusys_top_misc_dcm_is_on();
+ ret &= dcm_mp_cpusys_top_mp0_qdcm_is_on();
+ ret &= dcm_cpccfg_reg_emi_wfifo_is_on();
+ ret &= dcm_mp_cpusys_top_last_cor_idle_dcm_is_on();
+
+ ret &= dcm_mp_cpusys_top_core_stall_dcm_is_on();
+ ret &= dcm_mp_cpusys_top_fcm_stall_dcm_is_on();
+
+ return ret;
+}
+
+bool dcm_set_default(void)
+{
+ dcm_armcore(true);
+ dcm_mcusys(true);
+ dcm_stall(true);
+
+ return check_dcm_state();
+}
diff --git a/plat/mediatek/mt8195/drivers/dcm/mtk_dcm.h b/plat/mediatek/mt8195/drivers/dcm/mtk_dcm.h
new file mode 100644
index 0000000..cb65b85
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/dcm/mtk_dcm.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTK_DCM_H
+#define MTK_DCM_H
+
+#include <stdbool.h>
+
+bool dcm_set_default(void);
+
+#endif /* #ifndef MTK_DCM_H */
diff --git a/plat/mediatek/mt8195/drivers/dcm/mtk_dcm_utils.c b/plat/mediatek/mt8195/drivers/dcm/mtk_dcm_utils.c
new file mode 100644
index 0000000..a1a3720
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/dcm/mtk_dcm_utils.c
@@ -0,0 +1,483 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include <mtk_dcm_utils.h>
+
+#define MP_CPUSYS_TOP_ADB_DCM_REG0_MASK (BIT(17))
+#define MP_CPUSYS_TOP_ADB_DCM_REG1_MASK (BIT(15) | \
+ BIT(16) | \
+ BIT(17) | \
+ BIT(18) | \
+ BIT(21))
+#define MP_CPUSYS_TOP_ADB_DCM_REG2_MASK (BIT(15) | \
+ BIT(16) | \
+ BIT(17) | \
+ BIT(18))
+#define MP_CPUSYS_TOP_ADB_DCM_REG0_ON (BIT(17))
+#define MP_CPUSYS_TOP_ADB_DCM_REG1_ON (BIT(15) | \
+ BIT(16) | \
+ BIT(17) | \
+ BIT(18) | \
+ BIT(21))
+#define MP_CPUSYS_TOP_ADB_DCM_REG2_ON (BIT(15) | \
+ BIT(16) | \
+ BIT(17) | \
+ BIT(18))
+#define MP_CPUSYS_TOP_ADB_DCM_REG0_OFF ((0x0 << 17))
+#define MP_CPUSYS_TOP_ADB_DCM_REG1_OFF ((0x0 << 15) | \
+ (0x0 << 16) | \
+ (0x0 << 17) | \
+ (0x0 << 18) | \
+ (0x0 << 21))
+#define MP_CPUSYS_TOP_ADB_DCM_REG2_OFF ((0x0 << 15) | \
+ (0x0 << 16) | \
+ (0x0 << 17) | \
+ (0x0 << 18))
+
+bool dcm_mp_cpusys_top_adb_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0) &
+ MP_CPUSYS_TOP_ADB_DCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG0_ON);
+ ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4) &
+ MP_CPUSYS_TOP_ADB_DCM_REG1_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG1_ON);
+ ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) &
+ MP_CPUSYS_TOP_ADB_DCM_REG2_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_ADB_DCM_REG2_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_adb_dcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_adb_dcm'" */
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0,
+ MP_CPUSYS_TOP_ADB_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_ADB_DCM_REG0_ON);
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4,
+ MP_CPUSYS_TOP_ADB_DCM_REG1_MASK,
+ MP_CPUSYS_TOP_ADB_DCM_REG1_ON);
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0,
+ MP_CPUSYS_TOP_ADB_DCM_REG2_MASK,
+ MP_CPUSYS_TOP_ADB_DCM_REG2_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_adb_dcm'" */
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG0,
+ MP_CPUSYS_TOP_ADB_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_ADB_DCM_REG0_OFF);
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_ADB_DCM_CFG4,
+ MP_CPUSYS_TOP_ADB_DCM_REG1_MASK,
+ MP_CPUSYS_TOP_ADB_DCM_REG1_OFF);
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0,
+ MP_CPUSYS_TOP_ADB_DCM_REG2_MASK,
+ MP_CPUSYS_TOP_ADB_DCM_REG2_OFF);
+ }
+}
+
+#define MP_CPUSYS_TOP_APB_DCM_REG0_MASK (BIT(5))
+#define MP_CPUSYS_TOP_APB_DCM_REG1_MASK (BIT(8))
+#define MP_CPUSYS_TOP_APB_DCM_REG2_MASK (BIT(16))
+#define MP_CPUSYS_TOP_APB_DCM_REG0_ON (BIT(5))
+#define MP_CPUSYS_TOP_APB_DCM_REG1_ON (BIT(8))
+#define MP_CPUSYS_TOP_APB_DCM_REG2_ON (BIT(16))
+#define MP_CPUSYS_TOP_APB_DCM_REG0_OFF ((0x0 << 5))
+#define MP_CPUSYS_TOP_APB_DCM_REG1_OFF ((0x0 << 8))
+#define MP_CPUSYS_TOP_APB_DCM_REG2_OFF ((0x0 << 16))
+
+bool dcm_mp_cpusys_top_apb_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
+ MP_CPUSYS_TOP_APB_DCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG0_ON);
+ ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0) &
+ MP_CPUSYS_TOP_APB_DCM_REG1_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG1_ON);
+ ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG0) &
+ MP_CPUSYS_TOP_APB_DCM_REG2_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_APB_DCM_REG2_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_apb_dcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_apb_dcm'" */
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
+ MP_CPUSYS_TOP_APB_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_APB_DCM_REG0_ON);
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0,
+ MP_CPUSYS_TOP_APB_DCM_REG1_MASK,
+ MP_CPUSYS_TOP_APB_DCM_REG1_ON);
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0,
+ MP_CPUSYS_TOP_APB_DCM_REG2_MASK,
+ MP_CPUSYS_TOP_APB_DCM_REG2_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_apb_dcm'" */
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
+ MP_CPUSYS_TOP_APB_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_APB_DCM_REG0_OFF);
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MCUSYS_DCM_CFG0,
+ MP_CPUSYS_TOP_APB_DCM_REG1_MASK,
+ MP_CPUSYS_TOP_APB_DCM_REG1_OFF);
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0,
+ MP_CPUSYS_TOP_APB_DCM_REG2_MASK,
+ MP_CPUSYS_TOP_APB_DCM_REG2_OFF);
+ }
+}
+
+#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK (BIT(11) | \
+ BIT(24) | \
+ BIT(25))
+#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON (BIT(11) | \
+ BIT(24) | \
+ BIT(25))
+#define MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF ((0x0 << 11) | \
+ (0x0 << 24) | \
+ (0x0 << 25))
+
+bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG) &
+ MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_bus_pll_div_dcm'" */
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG,
+ MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_bus_pll_div_dcm'" */
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG,
+ MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_BUS_PLL_DIV_DCM_REG0_OFF);
+ }
+}
+
+#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK (BIT(0))
+#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON (BIT(0))
+#define MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF ((0x0 << 0))
+
+bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG7) &
+ MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_core_stall_dcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_core_stall_dcm'" */
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7,
+ MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_core_stall_dcm'" */
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7,
+ MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_CORE_STALL_DCM_REG0_OFF);
+ }
+}
+
+#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK ((0xffff << 0))
+#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON ((0xffff << 0))
+#define MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF ((0x0 << 0))
+
+bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(MP_CPUSYS_TOP_MCSIC_DCM0) &
+ MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_cpubiu_dcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpubiu_dcm'" */
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MCSIC_DCM0,
+ MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_CPUBIU_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpubiu_dcm'" */
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MCSIC_DCM0,
+ MP_CPUSYS_TOP_CPUBIU_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_CPUBIU_DCM_REG0_OFF);
+ }
+}
+
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK (BIT(24) | \
+ BIT(25))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON (BIT(24) | \
+ BIT(25))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF ((0x0 << 24) | \
+ (0x0 << 25))
+
+bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0) &
+ MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_0_dcm'" */
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG0,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_0_DCM_REG0_OFF);
+ }
+}
+
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK (BIT(24) | \
+ BIT(25))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON (BIT(24) | \
+ BIT(25))
+#define MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF ((0x0 << 24) | \
+ (0x0 << 25))
+
+bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1) &
+ MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_cpu_pll_div_1_dcm'" */
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_CPU_PLLDIV_CFG1,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_CPU_PLL_DIV_1_DCM_REG0_OFF);
+ }
+}
+
+#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK (BIT(4))
+#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON (BIT(4))
+#define MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF ((0x0 << 4))
+
+bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG7) &
+ MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_fcm_stall_dcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_fcm_stall_dcm'" */
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7,
+ MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_fcm_stall_dcm'" */
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG7,
+ MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_FCM_STALL_DCM_REG0_OFF);
+ }
+}
+
+#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK ((0x1U << 31))
+#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON ((0x1U << 31))
+#define MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF ((0x0U << 31))
+
+bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG) &
+ MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_last_cor_idle_dcm'" */
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG,
+ MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_last_cor_idle_dcm'" */
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_BUS_PLLDIV_CFG,
+ MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_LAST_COR_IDLE_DCM_REG0_OFF);
+ }
+}
+
+#define MP_CPUSYS_TOP_MISC_DCM_REG0_MASK (BIT(1) | \
+ BIT(4))
+#define MP_CPUSYS_TOP_MISC_DCM_REG0_ON (BIT(1) | \
+ BIT(4))
+#define MP_CPUSYS_TOP_MISC_DCM_REG0_OFF ((0x0 << 1) | \
+ (0x0 << 4))
+
+bool dcm_mp_cpusys_top_misc_dcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
+ MP_CPUSYS_TOP_MISC_DCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_MISC_DCM_REG0_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_misc_dcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_misc_dcm'" */
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
+ MP_CPUSYS_TOP_MISC_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_MISC_DCM_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_misc_dcm'" */
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
+ MP_CPUSYS_TOP_MISC_DCM_REG0_MASK,
+ MP_CPUSYS_TOP_MISC_DCM_REG0_OFF);
+ }
+}
+
+#define MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK (BIT(3))
+#define MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK (BIT(0) | \
+ BIT(1) | \
+ BIT(2) | \
+ BIT(3))
+#define MP_CPUSYS_TOP_MP0_QDCM_REG0_ON (BIT(3))
+#define MP_CPUSYS_TOP_MP0_QDCM_REG1_ON (BIT(0) | \
+ BIT(1) | \
+ BIT(2) | \
+ BIT(3))
+#define MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF ((0x0 << 3))
+#define MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF ((0x0 << 0) | \
+ (0x0 << 1) | \
+ (0x0 << 2) | \
+ (0x0 << 3))
+
+bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) &
+ MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_MP0_QDCM_REG0_ON);
+ ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP0_DCM_CFG0) &
+ MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK) ==
+ (unsigned int) MP_CPUSYS_TOP_MP0_QDCM_REG1_ON);
+
+ return ret;
+}
+
+void dcm_mp_cpusys_top_mp0_qdcm(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'mp_cpusys_top_mp0_qdcm'" */
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
+ MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK,
+ MP_CPUSYS_TOP_MP0_QDCM_REG0_ON);
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0,
+ MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK,
+ MP_CPUSYS_TOP_MP0_QDCM_REG1_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'mp_cpusys_top_mp0_qdcm'" */
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0,
+ MP_CPUSYS_TOP_MP0_QDCM_REG0_MASK,
+ MP_CPUSYS_TOP_MP0_QDCM_REG0_OFF);
+ mmio_clrsetbits_32(MP_CPUSYS_TOP_MP0_DCM_CFG0,
+ MP_CPUSYS_TOP_MP0_QDCM_REG1_MASK,
+ MP_CPUSYS_TOP_MP0_QDCM_REG1_OFF);
+ }
+}
+
+#define CPCCFG_REG_EMI_WFIFO_REG0_MASK (BIT(0) | \
+ BIT(1) | \
+ BIT(2) | \
+ BIT(3))
+#define CPCCFG_REG_EMI_WFIFO_REG0_ON (BIT(0) | \
+ BIT(1) | \
+ BIT(2) | \
+ BIT(3))
+#define CPCCFG_REG_EMI_WFIFO_REG0_OFF ((0x0 << 0) | \
+ (0x0 << 1) | \
+ (0x0 << 2) | \
+ (0x0 << 3))
+
+bool dcm_cpccfg_reg_emi_wfifo_is_on(void)
+{
+ bool ret = true;
+
+ ret &= ((mmio_read_32(CPCCFG_REG_EMI_WFIFO) &
+ CPCCFG_REG_EMI_WFIFO_REG0_MASK) ==
+ (unsigned int) CPCCFG_REG_EMI_WFIFO_REG0_ON);
+
+ return ret;
+}
+
+void dcm_cpccfg_reg_emi_wfifo(bool on)
+{
+ if (on) {
+ /* TINFO = "Turn ON DCM 'cpccfg_reg_emi_wfifo'" */
+ mmio_clrsetbits_32(CPCCFG_REG_EMI_WFIFO,
+ CPCCFG_REG_EMI_WFIFO_REG0_MASK,
+ CPCCFG_REG_EMI_WFIFO_REG0_ON);
+ } else {
+ /* TINFO = "Turn OFF DCM 'cpccfg_reg_emi_wfifo'" */
+ mmio_clrsetbits_32(CPCCFG_REG_EMI_WFIFO,
+ CPCCFG_REG_EMI_WFIFO_REG0_MASK,
+ CPCCFG_REG_EMI_WFIFO_REG0_OFF);
+ }
+}
diff --git a/plat/mediatek/mt8195/drivers/dcm/mtk_dcm_utils.h b/plat/mediatek/mt8195/drivers/dcm/mtk_dcm_utils.h
new file mode 100644
index 0000000..e5743af
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/dcm/mtk_dcm_utils.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTK_DCM_UTILS_H
+#define MTK_DCM_UTILS_H
+
+#include <stdbool.h>
+
+#include <mtk_dcm.h>
+#include <platform_def.h>
+
+/* Base */
+#define MP_CPUSYS_TOP_BASE (MCUCFG_BASE + 0x8000)
+#define CPCCFG_REG_BASE (MCUCFG_BASE + 0xA800)
+
+/* Register Definition */
+#define MP_CPUSYS_TOP_CPU_PLLDIV_CFG0 (MP_CPUSYS_TOP_BASE + 0x22a0)
+#define MP_CPUSYS_TOP_CPU_PLLDIV_CFG1 (MP_CPUSYS_TOP_BASE + 0x22a4)
+#define MP_CPUSYS_TOP_BUS_PLLDIV_CFG (MP_CPUSYS_TOP_BASE + 0x22e0)
+#define MP_CPUSYS_TOP_MCSIC_DCM0 (MP_CPUSYS_TOP_BASE + 0x2440)
+#define MP_CPUSYS_TOP_MP_ADB_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2500)
+#define MP_CPUSYS_TOP_MP_ADB_DCM_CFG4 (MP_CPUSYS_TOP_BASE + 0x2510)
+#define MP_CPUSYS_TOP_MP_MISC_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2518)
+#define MP_CPUSYS_TOP_MCUSYS_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x25c0)
+#define CPCCFG_REG_EMI_WFIFO (CPCCFG_REG_BASE + 0x100)
+#define MP_CPUSYS_TOP_MP0_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x4880)
+#define MP_CPUSYS_TOP_MP0_DCM_CFG7 (MP_CPUSYS_TOP_BASE + 0x489c)
+
+/* MP_CPUSYS_TOP */
+bool dcm_mp_cpusys_top_adb_dcm_is_on(void);
+void dcm_mp_cpusys_top_adb_dcm(bool on);
+bool dcm_mp_cpusys_top_apb_dcm_is_on(void);
+void dcm_mp_cpusys_top_apb_dcm(bool on);
+bool dcm_mp_cpusys_top_bus_pll_div_dcm_is_on(void);
+void dcm_mp_cpusys_top_bus_pll_div_dcm(bool on);
+bool dcm_mp_cpusys_top_core_stall_dcm_is_on(void);
+void dcm_mp_cpusys_top_core_stall_dcm(bool on);
+bool dcm_mp_cpusys_top_cpubiu_dcm_is_on(void);
+void dcm_mp_cpusys_top_cpubiu_dcm(bool on);
+bool dcm_mp_cpusys_top_cpu_pll_div_0_dcm_is_on(void);
+void dcm_mp_cpusys_top_cpu_pll_div_0_dcm(bool on);
+bool dcm_mp_cpusys_top_cpu_pll_div_1_dcm_is_on(void);
+void dcm_mp_cpusys_top_cpu_pll_div_1_dcm(bool on);
+bool dcm_mp_cpusys_top_fcm_stall_dcm_is_on(void);
+void dcm_mp_cpusys_top_fcm_stall_dcm(bool on);
+bool dcm_mp_cpusys_top_last_cor_idle_dcm_is_on(void);
+void dcm_mp_cpusys_top_last_cor_idle_dcm(bool on);
+bool dcm_mp_cpusys_top_misc_dcm_is_on(void);
+void dcm_mp_cpusys_top_misc_dcm(bool on);
+bool dcm_mp_cpusys_top_mp0_qdcm_is_on(void);
+void dcm_mp_cpusys_top_mp0_qdcm(bool on);
+/* CPCCFG_REG */
+bool dcm_cpccfg_reg_emi_wfifo_is_on(void);
+void dcm_cpccfg_reg_emi_wfifo(bool on);
+
+#endif
diff --git a/plat/mediatek/mt8195/drivers/dp/mt_dp.c b/plat/mediatek/mt8195/drivers/dp/mt_dp.c
new file mode 100644
index 0000000..7ab2194
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/dp/mt_dp.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <mt_dp.h>
+#include <mtk_sip_svc.h>
+#include <platform_def.h>
+
+static uint32_t dp_write_sec_reg(uint32_t is_edp, uint32_t offset,
+ uint32_t value, uint32_t mask)
+{
+ uint32_t reg = (is_edp != 0U) ? eDP_SEC_BASE : DP_SEC_BASE;
+
+ mmio_clrsetbits_32(reg + offset, mask, value);
+
+ return mmio_read_32(reg + offset);
+}
+
+int32_t dp_secure_handler(uint64_t cmd, uint64_t para, uint32_t *val)
+{
+ int32_t ret = 0L;
+ uint32_t is_edp = 0UL;
+ uint32_t regval = 0UL;
+ uint32_t regmsk = 0UL;
+ uint32_t fldmask = 0UL;
+
+ if ((cmd > DP_ATF_CMD_COUNT) || (val == NULL)) {
+ INFO("dp_secure_handler error cmd 0x%llx\n", cmd);
+ return MTK_SIP_E_INVALID_PARAM;
+ }
+
+ switch (cmd) {
+ case DP_ATF_DP_VIDEO_UNMUTE:
+ INFO("[%s] DP_ATF_DP_VIDEO_UNMUTE\n", __func__);
+ is_edp = DP_ATF_TYPE_DP;
+ ret = MTK_SIP_E_SUCCESS;
+ break;
+ case DP_ATF_EDP_VIDEO_UNMUTE:
+ INFO("[%s] DP_ATF_EDP_VIDEO_UNMUTE\n", __func__);
+ is_edp = DP_ATF_TYPE_EDP;
+ ret = MTK_SIP_E_SUCCESS;
+ break;
+ default:
+ ret = MTK_SIP_E_INVALID_PARAM;
+ break;
+ }
+
+ if (ret == MTK_SIP_E_SUCCESS) {
+ regmsk = (VIDEO_MUTE_SEL_SECURE_FLDMASK |
+ VIDEO_MUTE_SW_SECURE_FLDMASK);
+ if (para > 0U) {
+ fldmask = VIDEO_MUTE_SW_SECURE_FLDMASK;
+ } else {
+ fldmask = 0;
+ }
+
+ regval = (VIDEO_MUTE_SEL_SECURE_FLDMASK | fldmask);
+ *val = dp_write_sec_reg(is_edp, DP_TX_SECURE_REG11,
+ regval, regmsk);
+ }
+
+ return ret;
+}
diff --git a/plat/mediatek/mt8195/drivers/dp/mt_dp.h b/plat/mediatek/mt8195/drivers/dp/mt_dp.h
new file mode 100644
index 0000000..8157598
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/dp/mt_dp.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_DP_H
+#define MT_DP_H
+
+#define DP_TX_SECURE_REG11 (0x2c)
+
+#define VIDEO_MUTE_SEL_SECURE_FLDMASK (0x10)
+#define VIDEO_MUTE_SW_SECURE_FLDMASK (0x8)
+
+enum DP_ATF_HW_TYPE {
+ DP_ATF_TYPE_DP = 0,
+ DP_ATF_TYPE_EDP = 1
+};
+
+enum DP_ATF_CMD {
+ DP_ATF_DP_VIDEO_UNMUTE = 0x20,
+ DP_ATF_EDP_VIDEO_UNMUTE,
+ DP_ATF_CMD_COUNT
+};
+
+int32_t dp_secure_handler(uint64_t cmd, uint64_t para, uint32_t *val);
+
+#endif
diff --git a/plat/mediatek/mt8195/drivers/gpio/mtgpio.c b/plat/mediatek/mt8195/drivers/gpio/mtgpio.c
new file mode 100644
index 0000000..daab84c
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/gpio/mtgpio.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <mtgpio.h>
+#include <platform_def.h>
+
+uintptr_t mt_gpio_find_reg_addr(uint32_t pin)
+{
+ uintptr_t reg_addr = 0U;
+ struct mt_pin_info gpio_info;
+
+ assert(pin < MAX_GPIO_PIN);
+
+ gpio_info = mt_pin_infos[pin];
+
+ switch (gpio_info.base & 0x0f) {
+ case 0:
+ reg_addr = IOCFG_BM_BASE;
+ break;
+ case 1:
+ reg_addr = IOCFG_BL_BASE;
+ break;
+ case 2:
+ reg_addr = IOCFG_BR_BASE;
+ break;
+ case 3:
+ reg_addr = IOCFG_LM_BASE;
+ break;
+ case 4:
+ reg_addr = IOCFG_RB_BASE;
+ break;
+ case 5:
+ reg_addr = IOCFG_TL_BASE;
+ break;
+ default:
+ break;
+ }
+
+ return reg_addr;
+}
diff --git a/plat/mediatek/mt8195/drivers/gpio/mtgpio.h b/plat/mediatek/mt8195/drivers/gpio/mtgpio.h
new file mode 100644
index 0000000..88b4706
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/gpio/mtgpio.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_GPIO_H
+#define MT_GPIO_H
+
+#include <mtgpio_common.h>
+
+/* Enumeration for GPIO pin */
+typedef enum GPIO_PIN {
+ GPIO_UNSUPPORTED = -1,
+
+ GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7,
+ GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, GPIO14, GPIO15,
+ GPIO16, GPIO17, GPIO18, GPIO19, GPIO20, GPIO21, GPIO22, GPIO23,
+ GPIO24, GPIO25, GPIO26, GPIO27, GPIO28, GPIO29, GPIO30, GPIO31,
+ GPIO32, GPIO33, GPIO34, GPIO35, GPIO36, GPIO37, GPIO38, GPIO39,
+ GPIO40, GPIO41, GPIO42, GPIO43, GPIO44, GPIO45, GPIO46, GPIO47,
+ GPIO48, GPIO49, GPIO50, GPIO51, GPIO52, GPIO53, GPIO54, GPIO55,
+ GPIO56, GPIO57, GPIO58, GPIO59, GPIO60, GPIO61, GPIO62, GPIO63,
+ GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70, GPIO71,
+ GPIO72, GPIO73, GPIO74, GPIO75, GPIO76, GPIO77, GPIO78, GPIO79,
+ GPIO80, GPIO81, GPIO82, GPIO83, GPIO84, GPIO85, GPIO86, GPIO87,
+ GPIO88, GPIO89, GPIO90, GPIO91, GPIO92, GPIO93, GPIO94, GPIO95,
+ GPIO96, GPIO97, GPIO98, GPIO99, GPIO100, GPIO101, GPIO102, GPIO103,
+ GPIO104, GPIO105, GPIO106, GPIO107, GPIO108, GPIO109, GPIO110, GPIO111,
+ GPIO112, GPIO113, GPIO114, GPIO115, GPIO116, GPIO117, GPIO118, GPIO119,
+ GPIO120, GPIO121, GPIO122, GPIO123, GPIO124, GPIO125, GPIO126, GPIO127,
+ GPIO128, GPIO129, GPIO130, GPIO131, GPIO132, GPIO133, GPIO134, GPIO135,
+ GPIO136, GPIO137, GPIO138, GPIO139, GPIO140, GPIO141, GPIO142, GPIO143,
+ MT_GPIO_BASE_MAX
+} GPIO_PIN;
+
+static const struct mt_pin_info mt_pin_infos[] = {
+ PIN(0, 1, 0, 0x23, 0x60),
+ PIN(1, 1, 1, 0x23, 0x60),
+ PIN(2, 1, 2, 0x23, 0x60),
+ PIN(3, 1, 3, 0x23, 0x60),
+ PIN(4, 1, 4, 0x23, 0x60),
+ PIN(5, 1, 5, 0x23, 0x60),
+ PIN(6, 0, 6, 0x23, 0x70),
+ PIN(7, 0, 7, 0x23, 0x70),
+ PIN(8, 0, 13, 0x23, 0x70),
+ PIN(9, 0, 8, 0x23, 0x70),
+ PIN(10, 0, 14, 0x23, 0x70),
+ PIN(11, 0, 9, 0x23, 0x70),
+ PIN(12, 0, 15, 0x23, 0x70),
+ PIN(13, 0, 10, 0x23, 0x70),
+ PIN(14, 0, 16, 0x23, 0x70),
+ PIN(15, 0, 11, 0x23, 0x70),
+ PIN(16, 0, 17, 0x23, 0x70),
+ PIN(17, 0, 12, 0x23, 0x70),
+ PIN(18, 0, 5, 0x10, 0x60),
+ PIN(19, 0, 12, 0x10, 0x60),
+ PIN(20, 0, 11, 0x10, 0x60),
+ PIN(21, 0, 10, 0x10, 0x60),
+ PIN(22, 0, 0, 0x10, 0x60),
+ PIN(23, 0, 1, 0x10, 0x60),
+ PIN(24, 0, 2, 0x10, 0x60),
+ PIN(25, 0, 4, 0x10, 0x60),
+ PIN(26, 0, 3, 0x10, 0x60),
+ PIN(27, 0, 6, 0x10, 0x60),
+ PIN(28, 0, 7, 0x10, 0x60),
+ PIN(29, 0, 8, 0x10, 0x60),
+ PIN(30, 0, 9, 0x10, 0x60),
+ PIN(31, 0, 13, 0x21, 0xa0),
+ PIN(32, 0, 12, 0x21, 0xa0),
+ PIN(33, 0, 11, 0x21, 0xa0),
+ PIN(34, 0, 14, 0x21, 0xa0),
+ PIN(35, 0, 15, 0x21, 0xa0),
+ PIN(36, 0, 3, 0x21, 0xb0),
+ PIN(37, 0, 6, 0x21, 0xb0),
+ PIN(38, 0, 4, 0x21, 0xb0),
+ PIN(39, 0, 5, 0x21, 0xb0),
+ PIN(40, 0, 8, 0x21, 0xb0),
+ PIN(41, 0, 7, 0x21, 0xb0),
+ PIN(42, 0, 10, 0x21, 0xb0),
+ PIN(43, 0, 9, 0x21, 0xb0),
+ PIN(44, 0, 20, 0x21, 0xb0),
+ PIN(45, 0, 21, 0x21, 0xb0),
+ PIN(46, 0, 18, 0x21, 0xa0),
+ PIN(47, 0, 16, 0x21, 0xa0),
+ PIN(48, 0, 19, 0x21, 0xa0),
+ PIN(49, 0, 17, 0x21, 0xa0),
+ PIN(50, 0, 25, 0x21, 0xa0),
+ PIN(51, 0, 20, 0x21, 0xa0),
+ PIN(52, 0, 26, 0x21, 0xa0),
+ PIN(53, 0, 21, 0x21, 0xa0),
+ PIN(54, 0, 22, 0x21, 0xa0),
+ PIN(55, 0, 23, 0x21, 0xa0),
+ PIN(56, 0, 24, 0x21, 0xa0),
+ PIN(57, 0, 29, 0x21, 0xa0),
+ PIN(58, 0, 27, 0x21, 0xa0),
+ PIN(59, 0, 30, 0x21, 0xa0),
+ PIN(60, 0, 28, 0x21, 0xa0),
+ PIN(61, 0, 8, 0x21, 0xa0),
+ PIN(62, 0, 7, 0x21, 0xa0),
+ PIN(63, 0, 10, 0x21, 0xa0),
+ PIN(64, 0, 9, 0x21, 0xa0),
+ PIN(65, 0, 1, 0x21, 0xb0),
+ PIN(66, 0, 31, 0x21, 0xa0),
+ PIN(67, 0, 0, 0x21, 0xb0),
+ PIN(68, 0, 2, 0x21, 0xb0),
+ PIN(69, 0, 0, 0x21, 0xa0),
+ PIN(70, 0, 6, 0x21, 0xa0),
+ PIN(71, 0, 4, 0x21, 0xa0),
+ PIN(72, 0, 5, 0x21, 0xa0),
+ PIN(73, 0, 1, 0x21, 0xa0),
+ PIN(74, 0, 2, 0x21, 0xa0),
+ PIN(75, 0, 3, 0x21, 0xa0),
+ PIN(76, 0, 11, 0x21, 0xb0),
+ PIN(77, 1, 1, 0x22, 0x60),
+ PIN(78, 1, 2, 0x22, 0x60),
+ PIN(79, 1, 9, 0x22, 0x60),
+ PIN(80, 1, 10, 0x22, 0x60),
+ PIN(81, 1, 11, 0x22, 0x60),
+ PIN(82, 1, 12, 0x22, 0x60),
+ PIN(83, 1, 13, 0x22, 0x60),
+ PIN(84, 1, 14, 0x22, 0x60),
+ PIN(85, 1, 15, 0x22, 0x60),
+ PIN(86, 1, 16, 0x22, 0x60),
+ PIN(87, 1, 3, 0x22, 0x60),
+ PIN(88, 1, 4, 0x22, 0x60),
+ PIN(89, 1, 5, 0x22, 0x60),
+ PIN(90, 1, 6, 0x22, 0x60),
+ PIN(91, 1, 7, 0x22, 0x60),
+ PIN(92, 1, 8, 0x22, 0x60),
+ PIN(93, 1, 18, 0x22, 0x60),
+ PIN(94, 1, 19, 0x22, 0x60),
+ PIN(95, 1, 17, 0x22, 0x60),
+ PIN(96, 1, 0, 0x22, 0x60),
+ PIN(97, 0, 20, 0x22, 0x70),
+ PIN(98, 0, 28, 0x22, 0x70),
+ PIN(99, 0, 27, 0x22, 0x70),
+ PIN(100, 0, 30, 0x22, 0x70),
+ PIN(101, 0, 29, 0x22, 0x70),
+ PIN(102, 0, 0, 0x22, 0x70),
+ PIN(103, 0, 31, 0x22, 0x70),
+ PIN(104, 1, 25, 0x22, 0x60),
+ PIN(105, 1, 26, 0x22, 0x60),
+ PIN(106, 1, 23, 0x22, 0x60),
+ PIN(107, 1, 24, 0x22, 0x60),
+ PIN(108, 0, 22, 0x22, 0x70),
+ PIN(109, 0, 21, 0x22, 0x70),
+ PIN(110, 1, 1, 0x14, 0x20),
+ PIN(111, 1, 0, 0x14, 0x20),
+ PIN(112, 1, 2, 0x14, 0x20),
+ PIN(113, 1, 3, 0x14, 0x20),
+ PIN(114, 1, 4, 0x14, 0x20),
+ PIN(115, 1, 5, 0x14, 0x20),
+ PIN(116, 1, 9, 0x25, 0x50),
+ PIN(117, 1, 8, 0x25, 0x50),
+ PIN(118, 1, 7, 0x25, 0x50),
+ PIN(119, 1, 6, 0x25, 0x50),
+ PIN(120, 1, 11, 0x25, 0x50),
+ PIN(121, 1, 1, 0x25, 0x50),
+ PIN(122, 1, 0, 0x25, 0x50),
+ PIN(123, 1, 5, 0x25, 0x50),
+ PIN(124, 1, 4, 0x25, 0x50),
+ PIN(125, 1, 3, 0x25, 0x50),
+ PIN(126, 1, 2, 0x25, 0x50),
+ PIN(127, 1, 10, 0x25, 0x50),
+ PIN(128, 0, 3, 0x22, 0x70),
+ PIN(129, 0, 1, 0x22, 0x70),
+ PIN(130, 0, 4, 0x22, 0x70),
+ PIN(131, 0, 2, 0x22, 0x70),
+ PIN(132, 0, 13, 0x25, 0x60),
+ PIN(133, 0, 12, 0x25, 0x60),
+ PIN(134, 0, 15, 0x25, 0x60),
+ PIN(135, 0, 14, 0x25, 0x60),
+ PIN(136, 0, 13, 0x21, 0xb0),
+ PIN(137, 0, 12, 0x21, 0xb0),
+ PIN(138, 0, 15, 0x21, 0xb0),
+ PIN(139, 0, 14, 0x21, 0xb0),
+ PIN(140, 0, 17, 0x21, 0xb0),
+ PIN(141, 0, 16, 0x21, 0xb0),
+ PIN(142, 0, 19, 0x21, 0xb0),
+ PIN(143, 0, 18, 0x21, 0xb0),
+};
+#endif /* MT_GPIO_H */
diff --git a/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm.c b/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm.c
new file mode 100644
index 0000000..5a80d95
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm.c
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stdint.h>
+
+#include <arch_helpers.h>
+#include <lib/psci/psci.h>
+#include <lib/spinlock.h>
+
+#include <mt_cpu_pm_cpc.h>
+#include <mt_lp_irqremain.h>
+#include <mt_lp_rm.h>
+#include <mt_mcdi.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+
+DEFINE_SYSREG_RW_FUNCS(dbgprcr_el1);
+
+static int plat_mt_lp_cpu_rc;
+
+static int pwr_state_prompt(unsigned int cpu, const psci_power_state_t *state)
+{
+ return 0;
+}
+
+static int pwr_state_reflect(unsigned int cpu, const psci_power_state_t *state)
+{
+ mtk_cpc_core_on_hint_clr(cpu);
+
+ if (IS_SYSTEM_SUSPEND_STATE(state)) {
+ mtk_cpc_time_sync();
+ }
+
+ return 0;
+}
+
+static int pwr_cpu_pwron(unsigned int cpu, const psci_power_state_t *state)
+{
+ return 0;
+}
+
+static int pwr_cpu_pwrdwn(unsigned int cpu, const psci_power_state_t *state)
+{
+ /* clear DBGPRCR.CORENPDRQ to allow CPU power down */
+ write_dbgprcr_el1(0ULL);
+
+ return 0;
+}
+
+static int pwr_cluster_pwron(unsigned int cpu, const psci_power_state_t *state)
+{
+ return 0;
+}
+
+static int pwr_cluster_pwrdwn(unsigned int cpu, const psci_power_state_t *state)
+{
+ return 0;
+}
+
+static int pwr_mcusys_pwron(unsigned int cpu, const psci_power_state_t *state)
+{
+ if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) {
+ return -1;
+ }
+
+ mtk_cpc_mcusys_off_reflect();
+
+ return 0;
+}
+
+static int pwr_mcusys_pwron_finished(unsigned int cpu,
+ const psci_power_state_t *state)
+{
+ int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS];
+
+ if (!IS_MCUSYS_OFF_STATE(state) || (plat_mt_lp_cpu_rc < 0)) {
+ return -1;
+ }
+
+ mt_lp_rm_reset_constraint(plat_mt_lp_cpu_rc, cpu, state_id);
+ mt_lp_irqremain_release();
+
+ return 0;
+}
+
+static int pwr_mcusys_pwrdwn(unsigned int cpu, const psci_power_state_t *state)
+{
+ int state_id = state->pwr_domain_state[MTK_AFFLVL_MCUSYS];
+
+ if (!IS_MCUSYS_OFF_STATE(state)) {
+ goto mt_pwr_mcusysoff_break;
+ }
+
+ if (mcdi_try_init() != 0) {
+ goto mt_pwr_mcusysoff_break;
+ }
+
+ if (mtk_cpc_mcusys_off_prepare() != CPC_SUCCESS) {
+ goto mt_pwr_mcusysoff_break;
+ }
+
+ plat_mt_lp_cpu_rc =
+ mt_lp_rm_find_and_run_constraint(0, cpu, state_id, NULL);
+
+ if (plat_mt_lp_cpu_rc < 0) {
+ goto mt_pwr_mcusysoff_reflect;
+ }
+
+ mt_lp_irqremain_aquire();
+
+ return 0;
+
+mt_pwr_mcusysoff_reflect:
+ mtk_cpc_mcusys_off_reflect();
+
+mt_pwr_mcusysoff_break:
+
+ plat_mt_lp_cpu_rc = -1;
+
+ return -1;
+}
+
+static const struct mt_lpm_tz plat_pm = {
+ .pwr_prompt = pwr_state_prompt,
+ .pwr_reflect = pwr_state_reflect,
+ .pwr_cpu_on = pwr_cpu_pwron,
+ .pwr_cpu_dwn = pwr_cpu_pwrdwn,
+ .pwr_cluster_on = pwr_cluster_pwron,
+ .pwr_cluster_dwn = pwr_cluster_pwrdwn,
+ .pwr_mcusys_dwn = pwr_mcusys_pwrdwn,
+ .pwr_mcusys_on = pwr_mcusys_pwron,
+ .pwr_mcusys_on_finished = pwr_mcusys_pwron_finished
+};
+
+const struct mt_lpm_tz *mt_plat_cpu_pm_init(void)
+{
+ mtk_cpc_init();
+
+ if (mcdi_try_init() == 0) {
+ INFO("MCDI init done.\n");
+ }
+
+ mt_lp_irqremain_init();
+
+ return &plat_pm;
+}
diff --git a/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm_cpc.c b/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm_cpc.c
new file mode 100644
index 0000000..f8c51a1
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm_cpc.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+
+#include <drivers/delay_timer.h>
+
+#include <mt_cpu_pm_cpc.h>
+#include <mt_timer.h>
+
+struct mtk_cpc_dev {
+ int auto_off;
+ unsigned int auto_thres_tick;
+};
+
+static struct mtk_cpc_dev cpc;
+
+static int mtk_cpc_last_core_prot(uint32_t prot_req,
+ uint32_t resp_reg, uint32_t resp_ofs)
+{
+ uint32_t sta, retry;
+
+ retry = 0U;
+
+ while (retry++ < RETRY_CNT_MAX) {
+
+ mmio_write_32(CPC_MCUSYS_LAST_CORE_REQ, prot_req);
+
+ udelay(1U);
+
+ sta = (mmio_read_32(resp_reg) >> resp_ofs) & CPC_PROT_RESP_MASK;
+
+ if (sta == PROT_SUCCESS) {
+ return CPC_SUCCESS;
+ } else if (sta == PROT_GIVEUP) {
+ return CPC_ERR_FAIL;
+ }
+ }
+
+ return CPC_ERR_TIMEOUT;
+}
+
+int mtk_cpu_pm_mcusys_prot_aquire(void)
+{
+ return mtk_cpc_last_core_prot(
+ MCUSYS_PROT_SET,
+ CPC_MCUSYS_LAST_CORE_RESP,
+ MCUSYS_RESP_OFS);
+}
+
+void mtk_cpu_pm_mcusys_prot_release(void)
+{
+ mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, MCUSYS_PROT_CLR);
+}
+
+int mtk_cpu_pm_cluster_prot_aquire(unsigned int cluster)
+{
+ return mtk_cpc_last_core_prot(
+ CPUSYS_PROT_SET,
+ CPC_MCUSYS_MP_LAST_CORE_RESP,
+ CPUSYS_RESP_OFS);
+}
+
+void mtk_cpu_pm_cluster_prot_release(unsigned int cluster)
+{
+ mmio_write_32(CPC_MCUSYS_PWR_ON_MASK, CPUSYS_PROT_CLR);
+}
+
+static void mtk_cpc_cluster_cnt_backup(void)
+{
+ uint32_t backup_cnt;
+ uint32_t curr_cnt;
+ uint32_t cnt_mask = GENMASK(14, 0);
+ uint32_t clr_mask = GENMASK(1, 0);
+
+ /* Single Cluster */
+ backup_cnt = mmio_read_32(CPC_CLUSTER_CNT_BACKUP);
+ curr_cnt = mmio_read_32(CPC_MCUSYS_CLUSTER_COUNTER);
+
+ /* Get off count if dormant count is 0 */
+ if ((curr_cnt & cnt_mask) == 0U) {
+ curr_cnt = (curr_cnt >> 16) & cnt_mask;
+ } else {
+ curr_cnt = curr_cnt & cnt_mask;
+ }
+
+ mmio_write_32(CPC_CLUSTER_CNT_BACKUP, backup_cnt + curr_cnt);
+ mmio_write_32(CPC_MCUSYS_CLUSTER_COUNTER_CLR, clr_mask);
+}
+
+static inline void mtk_cpc_mcusys_off_en(void)
+{
+ mmio_write_32(CPC_MCUSYS_PWR_CTRL, 1U);
+}
+
+static inline void mtk_cpc_mcusys_off_dis(void)
+{
+ mmio_write_32(CPC_MCUSYS_PWR_CTRL, 0U);
+}
+
+void mtk_cpc_mcusys_off_reflect(void)
+{
+ mtk_cpc_mcusys_off_dis();
+ mtk_cpu_pm_mcusys_prot_release();
+}
+
+int mtk_cpc_mcusys_off_prepare(void)
+{
+ if (mtk_cpu_pm_mcusys_prot_aquire() != CPC_SUCCESS) {
+ return CPC_ERR_FAIL;
+ }
+
+ mtk_cpc_cluster_cnt_backup();
+ mtk_cpc_mcusys_off_en();
+
+ return CPC_SUCCESS;
+}
+
+void mtk_cpc_core_on_hint_set(unsigned int cpu)
+{
+ mmio_write_32(CPC_MCUSYS_CPU_ON_SW_HINT_SET, BIT(cpu));
+}
+
+void mtk_cpc_core_on_hint_clr(unsigned int cpu)
+{
+ mmio_write_32(CPC_MCUSYS_CPU_ON_SW_HINT_CLR, BIT(cpu));
+}
+
+static void mtk_cpc_dump_timestamp(void)
+{
+ uint32_t id;
+
+ for (id = 0U; id < CPC_TRACE_ID_NUM; id++) {
+ mmio_write_32(CPC_MCUSYS_TRACE_SEL, id);
+
+ memcpy((void *)(uintptr_t)CPC_TRACE_SRAM(id),
+ (const void *)(uintptr_t)CPC_MCUSYS_TRACE_DATA,
+ CPC_TRACE_SIZE);
+ }
+}
+
+void mtk_cpc_time_sync(void)
+{
+ uint64_t kt;
+ uint32_t systime_l, systime_h;
+
+ kt = sched_clock();
+ systime_l = mmio_read_32(CNTSYS_L_REG);
+ systime_h = mmio_read_32(CNTSYS_H_REG);
+
+ /* sync kernel timer to cpc */
+ mmio_write_32(CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE, (uint32_t)kt);
+ mmio_write_32(CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE, (uint32_t)(kt >> 32));
+ /* sync system timer to cpc */
+ mmio_write_32(CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE, systime_l);
+ mmio_write_32(CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE, systime_h);
+}
+
+static void mtk_cpc_config(uint32_t cfg, uint32_t data)
+{
+ uint32_t val;
+ uint32_t reg = 0U;
+
+ switch (cfg) {
+ case CPC_SMC_CONFIG_PROF:
+ reg = CPC_MCUSYS_CPC_DBG_SETTING;
+ val = mmio_read_32(reg);
+ val = (data != 0U) ? (val | CPC_PROF_EN) : (val & ~CPC_PROF_EN);
+ break;
+ case CPC_SMC_CONFIG_AUTO_OFF:
+ reg = CPC_MCUSYS_CPC_FLOW_CTRL_CFG;
+ val = mmio_read_32(reg);
+ if (data != 0U) {
+ val |= CPC_AUTO_OFF_EN;
+ cpc.auto_off = 1;
+ } else {
+ val &= ~CPC_AUTO_OFF_EN;
+ cpc.auto_off = 0;
+ }
+ break;
+ case CPC_SMC_CONFIG_AUTO_OFF_THRES:
+ reg = CPC_MCUSYS_CPC_OFF_THRES;
+ cpc.auto_thres_tick = us_to_ticks(data);
+ val = cpc.auto_thres_tick;
+ break;
+ case CPC_SMC_CONFIG_CNT_CLR:
+ reg = CPC_MCUSYS_CLUSTER_COUNTER_CLR;
+ val = GENMASK(1, 0); /* clr_mask */
+ break;
+ case CPC_SMC_CONFIG_TIME_SYNC:
+ mtk_cpc_time_sync();
+ break;
+ default:
+ break;
+ }
+
+ if (reg != 0U) {
+ mmio_write_32(reg, val);
+ }
+}
+
+static uint32_t mtk_cpc_read_config(uint32_t cfg)
+{
+ uint32_t res = 0U;
+
+ switch (cfg) {
+ case CPC_SMC_CONFIG_PROF:
+ res = (mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING) & CPC_PROF_EN) ?
+ 1U : 0U;
+ break;
+ case CPC_SMC_CONFIG_AUTO_OFF:
+ res = cpc.auto_off;
+ break;
+ case CPC_SMC_CONFIG_AUTO_OFF_THRES:
+ res = ticks_to_us(cpc.auto_thres_tick);
+ break;
+ case CPC_SMC_CONFIG_CNT_CLR:
+ break;
+ default:
+ break;
+ }
+
+ return res;
+}
+
+uint64_t mtk_cpc_handler(uint64_t act, uint64_t arg1, uint64_t arg2)
+{
+ uint64_t res = 0ULL;
+
+ switch (act) {
+ case CPC_SMC_EVENT_DUMP_TRACE_DATA:
+ mtk_cpc_dump_timestamp();
+ break;
+ case CPC_SMC_EVENT_GIC_DPG_SET:
+ /* isolated_status = x2; */
+ break;
+ case CPC_SMC_EVENT_CPC_CONFIG:
+ mtk_cpc_config((uint32_t)arg1, (uint32_t)arg2);
+ break;
+ case CPC_SMC_EVENT_READ_CONFIG:
+ res = mtk_cpc_read_config((uint32_t)arg1);
+ break;
+ default:
+ break;
+ }
+
+ return res;
+}
+
+void mtk_cpc_init(void)
+{
+ mmio_write_32(CPC_MCUSYS_CPC_DBG_SETTING,
+ mmio_read_32(CPC_MCUSYS_CPC_DBG_SETTING)
+ | CPC_DBG_EN
+ | CPC_CALC_EN);
+
+ cpc.auto_off = 1;
+ cpc.auto_thres_tick = us_to_ticks(8000);
+
+ mmio_write_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG,
+ mmio_read_32(CPC_MCUSYS_CPC_FLOW_CTRL_CFG)
+ | CPC_OFF_PRE_EN
+ | (cpc.auto_off ? CPC_AUTO_OFF_EN : 0U));
+
+ mmio_write_32(CPC_MCUSYS_CPC_OFF_THRES, cpc.auto_thres_tick);
+}
diff --git a/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm_cpc.h b/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm_cpc.h
new file mode 100644
index 0000000..19dd6a2
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/mcdi/mt_cpu_pm_cpc.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_CPU_PM_CPC_H
+#define MT_CPU_PM_CPC_H
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include <mcucfg.h>
+#include <platform_def.h>
+
+#define NEED_CPUSYS_PROT_WORKAROUND 1
+
+/* system sram registers */
+#define CPUIDLE_SRAM_REG(r) (uint32_t)(MTK_MCDI_SRAM_BASE + (r))
+
+/* db dump */
+#define CPC_TRACE_SIZE U(0x20)
+#define CPC_TRACE_ID_NUM U(10)
+#define CPC_TRACE_SRAM(id) (CPUIDLE_SRAM_REG(0x10) + (id) * CPC_TRACE_SIZE)
+
+/* buckup off count */
+#define CPC_CLUSTER_CNT_BACKUP CPUIDLE_SRAM_REG(0x1F0)
+#define CPC_MCUSYS_CNT CPUIDLE_SRAM_REG(0x1F4)
+
+/* CPC_MCUSYS_CPC_FLOW_CTRL_CFG(0xA814): debug setting */
+#define CPC_PWR_ON_SEQ_DIS BIT(1)
+#define CPC_PWR_ON_PRIORITY BIT(2)
+#define CPC_AUTO_OFF_EN BIT(5)
+#define CPC_DORMANT_WAIT_EN BIT(14)
+#define CPC_CTRL_EN BIT(16)
+#define CPC_OFF_PRE_EN BIT(29)
+
+/* CPC_MCUSYS_LAST_CORE_REQ(0xA818) : last core protection */
+#define CPUSYS_PROT_SET BIT(0)
+#define MCUSYS_PROT_SET BIT(8)
+#define CPUSYS_PROT_CLR BIT(8)
+#define MCUSYS_PROT_CLR BIT(9)
+
+#define CPC_PROT_RESP_MASK U(0x3)
+#define CPUSYS_RESP_OFS U(16)
+#define MCUSYS_RESP_OFS U(30)
+
+#define cpusys_resp(r) (((r) >> CPUSYS_RESP_OFS) & CPC_PROT_RESP_MASK)
+#define mcusys_resp(r) (((r) >> MCUSYS_RESP_OFS) & CPC_PROT_RESP_MASK)
+
+#define RETRY_CNT_MAX U(1000)
+
+#define PROT_RETRY U(0)
+#define PROT_SUCCESS U(1)
+#define PROT_GIVEUP U(2)
+
+/* CPC_MCUSYS_CPC_DBG_SETTING(0xAB00): debug setting */
+#define CPC_PROF_EN BIT(0)
+#define CPC_DBG_EN BIT(1)
+#define CPC_FREEZE BIT(2)
+#define CPC_CALC_EN BIT(3)
+
+enum {
+ CPC_SUCCESS = 0,
+
+ CPC_ERR_FAIL,
+ CPC_ERR_TIMEOUT,
+
+ NF_CPC_ERR
+};
+
+enum {
+ CPC_SMC_EVENT_DUMP_TRACE_DATA,
+ CPC_SMC_EVENT_GIC_DPG_SET,
+ CPC_SMC_EVENT_CPC_CONFIG,
+ CPC_SMC_EVENT_READ_CONFIG,
+
+ NF_CPC_SMC_EVENT
+};
+
+enum {
+ CPC_SMC_CONFIG_PROF,
+ CPC_SMC_CONFIG_AUTO_OFF,
+ CPC_SMC_CONFIG_AUTO_OFF_THRES,
+ CPC_SMC_CONFIG_CNT_CLR,
+ CPC_SMC_CONFIG_TIME_SYNC,
+
+ NF_CPC_SMC_CONFIG
+};
+
+#define us_to_ticks(us) ((us) * 13)
+#define ticks_to_us(tick) ((tick) / 13)
+
+int mtk_cpu_pm_cluster_prot_aquire(unsigned int cluster);
+void mtk_cpu_pm_cluster_prot_release(unsigned int cluster);
+
+void mtk_cpc_mcusys_off_reflect(void);
+int mtk_cpc_mcusys_off_prepare(void);
+
+void mtk_cpc_core_on_hint_set(unsigned int cpu);
+void mtk_cpc_core_on_hint_clr(unsigned int cpu);
+void mtk_cpc_time_sync(void);
+
+uint64_t mtk_cpc_handler(uint64_t act, uint64_t arg1, uint64_t arg2);
+void mtk_cpc_init(void);
+
+#endif /* MT_CPU_PM_CPC_H */
diff --git a/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.c b/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.c
new file mode 100644
index 0000000..4147184
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mt_lp_rm.h>
+#include <mt_lp_irqremain.h>
+#include <mtk_cirq.h>
+#include <plat_mtk_lpm.h>
+
+
+#define KEYPAD_IRQ_ID U(138)
+
+#define KEYPAD_WAKESRC 0x4
+
+static struct mt_irqremain remain_irqs;
+
+int mt_lp_irqremain_submit(void)
+{
+ if (remain_irqs.count == 0) {
+ return -1;
+ }
+
+ set_wakeup_sources(remain_irqs.irqs, remain_irqs.count);
+ mt_lp_rm_do_update(-1, PLAT_RC_UPDATE_REMAIN_IRQS, &remain_irqs);
+
+ return 0;
+}
+
+int mt_lp_irqremain_aquire(void)
+{
+ if (remain_irqs.count == 0) {
+ return -1;
+ }
+
+ mt_cirq_sw_reset();
+ mt_cirq_clone_gic();
+ mt_cirq_enable();
+
+ return 0;
+}
+
+int mt_lp_irqremain_release(void)
+{
+ if (remain_irqs.count == 0) {
+ return -1;
+ }
+
+ mt_cirq_flush();
+ mt_cirq_disable();
+
+ return 0;
+}
+
+void mt_lp_irqremain_init(void)
+{
+ uint32_t idx;
+
+ remain_irqs.count = 0;
+
+ /*edge keypad*/
+ idx = remain_irqs.count;
+ remain_irqs.irqs[idx] = KEYPAD_IRQ_ID;
+ remain_irqs.wakeupsrc_cat[idx] = 0;
+ remain_irqs.wakeupsrc[idx] = KEYPAD_WAKESRC;
+ remain_irqs.count++;
+
+ mt_lp_irqremain_submit();
+}
diff --git a/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.h b/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.h
new file mode 100644
index 0000000..b86e17e
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/mcdi/mt_lp_irqremain.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_LP_IRQREMAIN_H
+#define MT_LP_IRQREMAIN_H
+
+extern int mt_lp_irqremain_submit(void);
+extern int mt_lp_irqremain_aquire(void);
+extern int mt_lp_irqremain_release(void);
+extern void mt_lp_irqremain_init(void);
+#endif /* MT_LP_IRQREMAIN_H */
diff --git a/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.c b/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.c
new file mode 100644
index 0000000..c14e83b
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <cdefs.h>
+#include <common/debug.h>
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+#include <mt_mcdi.h>
+
+/* Read/Write */
+#define APMCU_MCUPM_MBOX_AP_READY U(0)
+#define APMCU_MCUPM_MBOX_RESERVED_1 U(1)
+#define APMCU_MCUPM_MBOX_RESERVED_2 U(2)
+#define APMCU_MCUPM_MBOX_RESERVED_3 U(3)
+#define APMCU_MCUPM_MBOX_PWR_CTRL_EN U(4)
+#define APMCU_MCUPM_MBOX_L3_CACHE_MODE U(5)
+#define APMCU_MCUPM_MBOX_BUCK_MODE U(6)
+#define APMCU_MCUPM_MBOX_ARMPLL_MODE U(7)
+/* Read only */
+#define APMCU_MCUPM_MBOX_TASK_STA U(8)
+#define APMCU_MCUPM_MBOX_RESERVED_9 U(9)
+#define APMCU_MCUPM_MBOX_RESERVED_10 U(10)
+#define APMCU_MCUPM_MBOX_RESERVED_11 U(11)
+
+/* CPC mode - Read/Write */
+#define APMCU_MCUPM_MBOX_WAKEUP_CPU U(12)
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_PWR_CTRL_EN */
+#define MCUPM_MCUSYS_CTRL BIT(0)
+#define MCUPM_BUCK_CTRL BIT(1)
+#define MCUPM_ARMPLL_CTRL BIT(2)
+#define MCUPM_CM_CTRL BIT(3)
+#define MCUPM_PWR_CTRL_MASK GENMASK(3, 0)
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_BUCK_MODE */
+#define MCUPM_BUCK_NORMAL_MODE U(0) /* default */
+#define MCUPM_BUCK_LP_MODE U(1)
+#define MCUPM_BUCK_OFF_MODE U(2)
+#define NF_MCUPM_BUCK_MODE U(3)
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_ARMPLL_MODE */
+#define MCUPM_ARMPLL_ON U(0) /* default */
+#define MCUPM_ARMPLL_GATING U(1)
+#define MCUPM_ARMPLL_OFF U(2)
+#define NF_MCUPM_ARMPLL_MODE U(3)
+
+/* Mbox Slot: APMCU_MCUPM_MBOX_TASK_STA */
+#define MCUPM_TASK_UNINIT U(0)
+#define MCUPM_TASK_INIT U(1)
+#define MCUPM_TASK_INIT_FINISH U(2)
+#define MCUPM_TASK_WAIT U(3)
+#define MCUPM_TASK_RUN U(4)
+#define MCUPM_TASK_PAUSE U(5)
+
+#define SSPM_MBOX_3_BASE U(0x0c55fce0)
+
+#define MCDI_NOT_INIT 0
+#define MCDI_INIT_1 1
+#define MCDI_INIT_2 2
+#define MCDI_INIT_DONE 3
+
+static int mcdi_init_status __section("tzfw_coherent_mem");
+
+static inline uint32_t mcdi_mbox_read(uint32_t id)
+{
+ return mmio_read_32(SSPM_MBOX_3_BASE + (id << 2));
+}
+
+static inline void mcdi_mbox_write(uint32_t id, uint32_t val)
+{
+ mmio_write_32(SSPM_MBOX_3_BASE + (id << 2), val);
+}
+
+static void mtk_mcupm_pwr_ctrl_setting(uint32_t dev)
+{
+ mcdi_mbox_write(APMCU_MCUPM_MBOX_PWR_CTRL_EN, dev);
+}
+
+static void mtk_set_mcupm_pll_mode(uint32_t mode)
+{
+ if (mode < NF_MCUPM_ARMPLL_MODE) {
+ mcdi_mbox_write(APMCU_MCUPM_MBOX_ARMPLL_MODE, mode);
+ }
+}
+
+static void mtk_set_mcupm_buck_mode(uint32_t mode)
+{
+ if (mode < NF_MCUPM_BUCK_MODE) {
+ mcdi_mbox_write(APMCU_MCUPM_MBOX_BUCK_MODE, mode);
+ }
+}
+
+static int mtk_mcupm_is_ready(void)
+{
+ unsigned int sta = mcdi_mbox_read(APMCU_MCUPM_MBOX_TASK_STA);
+
+ return (sta == MCUPM_TASK_WAIT) || (sta == MCUPM_TASK_INIT_FINISH);
+}
+
+static int mcdi_init_1(void)
+{
+ unsigned int sta = mcdi_mbox_read(APMCU_MCUPM_MBOX_TASK_STA);
+
+ if (sta != MCUPM_TASK_INIT) {
+ return -1;
+ }
+
+ mtk_set_mcupm_pll_mode(MCUPM_ARMPLL_OFF);
+ mtk_set_mcupm_buck_mode(MCUPM_BUCK_OFF_MODE);
+
+ mtk_mcupm_pwr_ctrl_setting(
+ MCUPM_MCUSYS_CTRL |
+ MCUPM_BUCK_CTRL |
+ MCUPM_ARMPLL_CTRL);
+
+ mcdi_mbox_write(APMCU_MCUPM_MBOX_AP_READY, 1);
+
+ return 0;
+}
+
+static int mcdi_init_2(void)
+{
+ return mtk_mcupm_is_ready() ? 0 : -1;
+}
+
+int mcdi_try_init(void)
+{
+ if (mcdi_init_status == MCDI_INIT_DONE) {
+ return 0;
+ }
+
+ if (mcdi_init_status == MCDI_NOT_INIT) {
+ mcdi_init_status = MCDI_INIT_1;
+ }
+
+ if (mcdi_init_status == MCDI_INIT_1 && mcdi_init_1() == 0) {
+ mcdi_init_status = MCDI_INIT_2;
+ }
+
+ if (mcdi_init_status == MCDI_INIT_2 && mcdi_init_2() == 0) {
+ mcdi_init_status = MCDI_INIT_DONE;
+ }
+
+ INFO("mcdi ready for mcusys-off-idle and system suspend\n");
+
+ return (mcdi_init_status == MCDI_INIT_DONE) ? 0 : mcdi_init_status;
+}
diff --git a/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.h b/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.h
new file mode 100644
index 0000000..f3545aa
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/mcdi/mt_mcdi.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_MCDI_H
+#define MT_MCDI_H
+
+int mcdi_try_init(void);
+
+#endif /* MT_MCDI_H */
diff --git a/plat/mediatek/mt8195/drivers/pmic/pmic.c b/plat/mediatek/mt8195/drivers/pmic/pmic.c
new file mode 100644
index 0000000..cca4413
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/pmic/pmic.c
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <pmic.h>
+#include <pmic_wrap_init.h>
+
+void pmic_power_off(void)
+{
+ pwrap_write(PMIC_PWRHOLD, 0x0);
+}
diff --git a/plat/mediatek/mt8195/drivers/pmic/pmic.h b/plat/mediatek/mt8195/drivers/pmic/pmic.h
new file mode 100644
index 0000000..aac22af
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/pmic/pmic.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_H
+#define PMIC_H
+
+#define PMIC_PWRHOLD 0xa08
+
+/* external API */
+void pmic_power_off(void);
+
+#endif /* PMIC_H */
diff --git a/plat/mediatek/mt8195/drivers/pmic/pmic_wrap_init.h b/plat/mediatek/mt8195/drivers/pmic/pmic_wrap_init.h
new file mode 100644
index 0000000..39e78f5
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/pmic/pmic_wrap_init.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PMIC_WRAP_INIT_H
+#define PMIC_WRAP_INIT_H
+
+#include <stdint.h>
+
+#include "platform_def.h"
+
+/* external API */
+int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
+int32_t pwrap_write(uint32_t adr, uint32_t wdata);
+
+static struct mt8195_pmic_wrap_regs *const mtk_pwrap = (void *)PMIC_WRAP_BASE;
+
+/* PMIC_WRAP registers */
+struct mt8195_pmic_wrap_regs {
+ uint32_t init_done;
+ uint32_t reserved[543];
+ uint32_t wacs2_cmd;
+ uint32_t wacs2_wdata;
+ uint32_t reserved1[3];
+ uint32_t wacs2_rdata;
+ uint32_t reserved2[3];
+ uint32_t wacs2_vldclr;
+ uint32_t wacs2_sta;
+};
+
+#define GET_WACS_FSM(x) ((x >> 1) & 0x7)
+
+/* macro for SWINF_FSM */
+#define SWINF_FSM_IDLE (0x00)
+#define SWINF_FSM_REQ (0x02)
+#define SWINF_FSM_WFDLE (0x04)
+#define SWINF_FSM_WFVLDCLR (0x06)
+#define SWINF_INIT_DONE (0x01)
+
+/* timeout setting */
+#define PWRAP_READ_US 1000
+#define PWRAP_WAIT_IDLE_US 1000
+
+/* error information flag */
+enum pwrap_errno {
+ E_PWR_INVALID_ARG = 1,
+ E_PWR_INVALID_RW = 2,
+ E_PWR_INVALID_ADDR = 3,
+ E_PWR_INVALID_WDAT = 4,
+ E_PWR_INVALID_OP_MANUAL = 5,
+ E_PWR_NOT_IDLE_STATE = 6,
+ E_PWR_NOT_INIT_DONE = 7,
+ E_PWR_NOT_INIT_DONE_READ = 8,
+ E_PWR_WAIT_IDLE_TIMEOUT = 9,
+ E_PWR_WAIT_IDLE_TIMEOUT_READ = 10,
+ E_PWR_INIT_SIDLY_FAIL = 11,
+ E_PWR_RESET_TIMEOUT = 12,
+ E_PWR_TIMEOUT = 13,
+ E_PWR_INIT_RESET_SPI = 20,
+ E_PWR_INIT_SIDLY = 21,
+ E_PWR_INIT_REG_CLOCK = 22,
+ E_PWR_INIT_ENABLE_PMIC = 23,
+ E_PWR_INIT_DIO = 24,
+ E_PWR_INIT_CIPHER = 25,
+ E_PWR_INIT_WRITE_TEST = 26,
+ E_PWR_INIT_ENABLE_CRC = 27,
+ E_PWR_INIT_ENABLE_DEWRAP = 28,
+ E_PWR_INIT_ENABLE_EVENT = 29,
+ E_PWR_READ_TEST_FAIL = 30,
+ E_PWR_WRITE_TEST_FAIL = 31,
+ E_PWR_SWITCH_DIO = 32
+};
+
+#endif /* PMIC_WRAP_INIT_H */
diff --git a/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_common.h b/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_common.h
new file mode 100644
index 0000000..341cf86
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_common.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTK_PTP3_COMMON_H
+#define MTK_PTP3_COMMON_H
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+
+/************************************************
+ * CPU info
+ ************************************************/
+#define NR_PTP3_CFG_CPU U(8)
+#define PTP3_CFG_CPU_START_ID_L U(0)
+#define PTP3_CFG_CPU_START_ID_B U(4)
+#define PTP3_CFG_CPU_END_ID U(7)
+
+#define NR_PTP3_CFG1_DATA U(2)
+#define PTP3_CFG1_MASK 0x3000
+
+#define NR_PTP3_CFG2_DATA U(5)
+
+#define PTP3_CFG3_MASK1 0x1180
+#define PTP3_CFG3_MASK2 0x35C0
+#define PTP3_CFG3_MASK3 0x3DC0
+
+/************************************************
+ * register read/write
+ ************************************************/
+#define ptp3_write(addr, val) mmio_write_32((uintptr_t)addr, val)
+#define ptp3_clrsetbits(addr, clear, set) \
+ mmio_clrsetbits_32((uintptr_t)addr, clear, set)
+
+/************************************************
+ * config enum
+ ************************************************/
+enum PTP3_CFG {
+ PTP3_CFG_ADDR,
+ PTP3_CFG_VALUE,
+ NR_PTP3_CFG,
+};
+
+/************************************
+ * prototype
+ ************************************/
+extern void ptp3_core_init(unsigned int core);
+extern void ptp3_core_unInit(unsigned int core);
+
+#endif /* MTK_PTP3_COMMON_H */
diff --git a/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_main.c b/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_main.c
new file mode 100644
index 0000000..540cb33
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/ptp3/mtk_ptp3_main.c
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved. \
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <mtk_ptp3_common.h>
+
+#define PTP3_CORE_OFT(core) (0x800 * (core))
+
+/************************************************
+ * Central control
+ ************************************************/
+static unsigned int ptp3_cfg1[NR_PTP3_CFG1_DATA][NR_PTP3_CFG] = {
+ {0x0C53A2A0, 0x1000},
+ {0x0C53A2A4, 0x1000}
+};
+
+static unsigned int ptp3_cfg2[NR_PTP3_CFG2_DATA][NR_PTP3_CFG] = {
+ {0x0C530404, 0x3A1000},
+ {0x0C530428, 0x13E0408},
+ {0x0C530434, 0xB22800},
+ {0x0C53043C, 0x750},
+ {0x0C530440, 0x0222c4cc}
+};
+
+static unsigned int ptp3_cfg3[NR_PTP3_CFG] = {0x0C530400, 0x2D80};
+static unsigned int ptp3_cfg3_ext[NR_PTP3_CFG] = {0x0C530400, 0xC00};
+
+static void ptp3_init(unsigned int core)
+{
+ unsigned int i, addr, value;
+
+ if (core < PTP3_CFG_CPU_START_ID_B) {
+ ptp3_clrsetbits(ptp3_cfg1[0][PTP3_CFG_ADDR], PTP3_CFG1_MASK,
+ ptp3_cfg1[0][PTP3_CFG_VALUE]);
+ } else {
+ ptp3_clrsetbits(ptp3_cfg1[1][PTP3_CFG_ADDR], PTP3_CFG1_MASK,
+ ptp3_cfg1[1][PTP3_CFG_VALUE]);
+ }
+
+ if (core < PTP3_CFG_CPU_START_ID_B) {
+ for (i = 0; i < NR_PTP3_CFG2_DATA; i++) {
+ addr = ptp3_cfg2[i][PTP3_CFG_ADDR] +
+ PTP3_CORE_OFT(core);
+ value = ptp3_cfg2[i][PTP3_CFG_VALUE];
+
+ ptp3_write(addr, value);
+ }
+ } else {
+ for (i = 0; i < NR_PTP3_CFG2_DATA; i++) {
+ addr = ptp3_cfg2[i][PTP3_CFG_ADDR] +
+ PTP3_CORE_OFT(core);
+
+ if (i == 2) {
+ value = ptp3_cfg2[i][PTP3_CFG_VALUE] + 0x5E0;
+ } else {
+ value = ptp3_cfg2[i][PTP3_CFG_VALUE];
+ }
+ ptp3_write(addr, value);
+ }
+ }
+
+ if (core < PTP3_CFG_CPU_START_ID_B) {
+ addr = ptp3_cfg3[PTP3_CFG_ADDR] + PTP3_CORE_OFT(core);
+ value = ptp3_cfg3[PTP3_CFG_VALUE];
+
+ ptp3_write(addr, value & PTP3_CFG3_MASK1);
+ ptp3_write(addr, value & PTP3_CFG3_MASK2);
+ ptp3_write(addr, value & PTP3_CFG3_MASK3);
+ } else {
+ addr = ptp3_cfg3_ext[PTP3_CFG_ADDR] + PTP3_CORE_OFT(core);
+ value = ptp3_cfg3_ext[PTP3_CFG_VALUE];
+
+ ptp3_write(addr, value & PTP3_CFG3_MASK1);
+ ptp3_write(addr, value & PTP3_CFG3_MASK2);
+ ptp3_write(addr, value & PTP3_CFG3_MASK3);
+ }
+}
+
+void pdp_proc_ARM_write(unsigned int pdp_n)
+{
+ unsigned long v = 0;
+
+ dsb();
+ __asm__ volatile ("mrs %0, S3_6_C15_C2_0" : "=r" (v));
+ v |= (UL(0x0) << 52);
+ v |= (UL(0x1) << 53);
+ v |= (UL(0x0) << 54);
+ v |= (UL(0x0) << 48);
+ v |= (UL(0x1) << 49);
+ __asm__ volatile ("msr S3_6_C15_C2_0, %0" : : "r" (v));
+ dsb();
+}
+
+void pdp_init(unsigned int pdp_cpu, unsigned int en)
+{
+ if ((pdp_cpu >= PTP3_CFG_CPU_START_ID_B) &&
+ (pdp_cpu < NR_PTP3_CFG_CPU)) {
+ pdp_proc_ARM_write(pdp_cpu);
+ }
+}
+
+static void dt_proc_ARM_write(unsigned int dt_n)
+{
+ unsigned long v = 0;
+
+ dsb();
+ __asm__ volatile ("mrs %0, S3_6_C15_C2_0" : "=r" (v));
+ v |= (UL(0x0) << 33);
+ v |= (UL(0x0) << 32);
+ __asm__ volatile ("msr S3_6_C15_C2_0, %0" : : "r" (v));
+ dsb();
+}
+
+void dt_init(unsigned int dt_cpu, unsigned int en)
+{
+ if ((dt_cpu >= PTP3_CFG_CPU_START_ID_B) &&
+ (dt_cpu < NR_PTP3_CFG_CPU)) {
+ dt_proc_ARM_write(dt_cpu);
+ }
+}
+void ptp3_core_init(unsigned int core)
+{
+ /* init for ptp3 */
+ ptp3_init(core);
+ /* init for pdp */
+ pdp_init(core, 1);
+ /* init for dt */
+ dt_init(core, 1);
+}
+
+void ptp3_core_unInit(unsigned int core)
+{
+ /* TBD */
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/build.mk b/plat/mediatek/mt8195/drivers/spm/build.mk
new file mode 100644
index 0000000..d1ee092
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/build.mk
@@ -0,0 +1,67 @@
+#
+# Copyright (c) 2021, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Enable or disable spm feature
+MT_SPM_FEATURE_SUPPORT = yes
+
+# Enable or disable cirq restore
+MT_SPM_CIRQ_FEATURE_SUPPORT = yes
+
+# sspm notifier support
+MT_SPM_SSPM_NOTIFIER_SUPPORT = yes
+
+CUR_SPM_FOLDER = ${MTK_PLAT_SOC}/drivers/spm
+
+# spm common files
+PLAT_SPM_SOURCE_FILES_COMMON += \
+ ${CUR_SPM_FOLDER}/mt_spm.c \
+ ${CUR_SPM_FOLDER}/mt_spm_conservation.c \
+ ${CUR_SPM_FOLDER}/mt_spm_internal.c \
+ ${CUR_SPM_FOLDER}/mt_spm_pmic_wrap.c
+
+# spm platform dependcy files
+PLAT_SPM_SOURCE_FILES += \
+ ${CUR_SPM_FOLDER}/constraints/mt_spm_rc_bus26m.c \
+ ${CUR_SPM_FOLDER}/constraints/mt_spm_rc_cpu_buck_ldo.c \
+ ${CUR_SPM_FOLDER}/constraints/mt_spm_rc_dram.c \
+ ${CUR_SPM_FOLDER}/constraints/mt_spm_rc_syspll.c \
+ ${CUR_SPM_FOLDER}/mt_spm_cond.c \
+ ${CUR_SPM_FOLDER}/mt_spm_suspend.c \
+ ${CUR_SPM_FOLDER}/mt_spm_idle.c
+
+ifeq (${MT_SPM_FEATURE_SUPPORT}, no)
+PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_SPM_UNSUPPORT
+BL31_MT_LPM_PLAT_SPM_SOURCE_FILES += ${PLAT_SPM_SOURCE_FILES_COMMON}
+else
+BL31_MT_LPM_PLAT_SPM_SOURCE_FILES += \
+ ${PLAT_SPM_SOURCE_FILES_COMMON} \
+ ${PLAT_SPM_SOURCE_FILES}
+endif
+
+ifeq (${MT_SPM_CIRQ_FEATURE_SUPPORT}, no)
+PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_CIRQ_UNSUPPORT
+endif
+
+ifeq (${MT_SPM_SSPM_NOTIFIER_SUPPORT}, no)
+PLAT_SPM_DEBUG_CFLAGS += -DATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+else
+BL31_MT_LPM_PLAT_SPM_SOURCE_FILES += \
+ ${CUR_SPM_FOLDER}/notifier/mt_spm_sspm_notifier.c
+endif
+
+$(info --------------------------------------)
+$(info SPM build flags: ${PLAT_SPM_DEBUG_CFLAGS})
+$(info SPM build files: ${BL31_MT_LPM_PLAT_SPM_SOURCE_FILES})
+$(info --------------------------------------)
+
+# Common makefile for platform.mk
+PLAT_INCLUDES += \
+ ${PLAT_SPM_DEBUG_CFLAGS} \
+ -I${CUR_SPM_FOLDER}/ \
+ -I${CUR_SPM_FOLDER}/constraints/ \
+ -I${CUR_SPM_FOLDER}/notifier/
+
+PLAT_BL_COMMON_SOURCES += ${BL31_MT_LPM_PLAT_SPM_SOURCE_FILES}
diff --git a/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_bus26m.c b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_bus26m.c
new file mode 100644
index 0000000..d2ad282
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_bus26m.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+
+#include <mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+#include <plat_pm.h>
+#include <plat_mtk_lpm.h>
+
+#ifndef ATF_PLAT_CIRQ_UNSUPPORT
+#include <mt_gic_v3.h>
+#include <mtk_cirq.h>
+#endif
+
+#define CONSTRAINT_BUS26M_ALLOW \
+ (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
+ MT_RM_CONSTRAINT_ALLOW_VCORE_LP | \
+ MT_RM_CONSTRAINT_ALLOW_LVTS_STATE | \
+ MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF)
+
+#define CONSTRAINT_BUS26M_PCM_FLAG \
+ (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_SRAM_SLEEP_CTRL | \
+ SPM_FLAG_ENABLE_TIA_WORKAROUND | \
+ SPM_FLAG_ENABLE_LVTS_WORKAROUND | \
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
+
+#define CONSTRAINT_BUS26M_PCM_FLAG1 0U
+
+#define CONSTRAINT_BUS26M_RESOURCE_REQ 0U
+
+static unsigned int bus26m_ext_opand;
+static struct mt_irqremain *refer2remain_irq;
+static struct mt_spm_cond_tables cond_bus26m = {
+ .name = "bus26m",
+ .table_cg = {
+ 0xFFFFD408, /* MTCMOS1 */
+ 0x2284C802, /* INFRA0 */
+ 0x27AF8000, /* INFRA1 */
+ 0x86040650, /* INFRA2 */
+ 0x30038020, /* INFRA3 */
+ 0x80000000, /* INFRA4 */
+ 0x00080ABB, /* PERI0 */
+ 0x00004000, /* VPPSYS0_0 */
+ 0x08803000, /* VPPSYS0_1 */
+ 0x00000000, /* VPPSYS0_2 */
+ 0x80005555, /* VPPSYS1_0 */
+ 0x00009008, /* VPPSYS1_1 */
+ 0x60060000, /* VDOSYS0_0 */
+ 0x00000000, /* VDOSYS0_1 */
+ 0x201E01F8, /* VDOSYS1_0 */
+ 0x00800000, /* VDOSYS1_1 */
+ 0x00000000, /* VDOSYS1_2 */
+ 0x00000080, /* I2C */
+ },
+ .table_pll = (PLL_BIT_UNIVPLL |
+ PLL_BIT_MFGPLL |
+ PLL_BIT_MSDCPLL |
+ PLL_BIT_TVDPLL |
+ PLL_BIT_MMPLL),
+};
+
+static struct mt_spm_cond_tables cond_bus26m_res = {
+ .table_cg = { 0U },
+ .table_pll = 0U,
+};
+
+static struct constraint_status status = {
+ .id = MT_RM_CONSTRAINT_ID_BUS26M,
+ .valid = (MT_SPM_RC_VALID_SW |
+ MT_SPM_RC_VALID_COND_LATCH),
+ .cond_block = 0U,
+ .enter_cnt = 0U,
+ .cond_res = &cond_bus26m_res,
+};
+
+/*
+ * Cirq will take the place of gic when gic is off.
+ * However, cirq cannot work if 26m clk is turned off when system idle/suspend.
+ * Therefore, we need to set irq pending for specific wakeup source.
+ */
+#ifdef ATF_PLAT_CIRQ_UNSUPPORT
+#define do_irqs_delivery()
+#else
+static void mt_spm_irq_remain_dump(struct mt_irqremain *irqs,
+ unsigned int irq_index,
+ struct wake_status *wakeup)
+{
+ INFO("[SPM] r12 = 0x%08x(0x%08x), flag = 0x%08x 0x%08x 0x%08x\n",
+ wakeup->tr.comm.r12, wakeup->md32pcm_wakeup_sta,
+ wakeup->tr.comm.debug_flag, wakeup->tr.comm.b_sw_flag0,
+ wakeup->tr.comm.b_sw_flag1);
+
+ INFO("irq:%u(0x%08x) set pending\n",
+ irqs->wakeupsrc[irq_index], irqs->irqs[irq_index]);
+}
+
+static void do_irqs_delivery(void)
+{
+ unsigned int idx;
+ int res = 0;
+ struct wake_status *wakeup = NULL;
+ struct mt_irqremain *irqs = refer2remain_irq;
+
+ res = spm_conservation_get_result(&wakeup);
+
+ if ((res != 0) && (irqs == NULL)) {
+ return;
+ }
+
+ for (idx = 0U; idx < irqs->count; ++idx) {
+ if (((wakeup->tr.comm.r12 & irqs->wakeupsrc[idx]) != 0U) ||
+ ((wakeup->raw_sta & irqs->wakeupsrc[idx]) != 0U)) {
+ if ((irqs->wakeupsrc_cat[idx] &
+ MT_IRQ_REMAIN_CAT_LOG) != 0U) {
+ mt_spm_irq_remain_dump(irqs, idx, wakeup);
+ }
+
+ mt_irq_set_pending(irqs->irqs[idx]);
+ }
+ }
+}
+#endif
+
+static void spm_bus26m_conduct(struct spm_lp_scen *spm_lp,
+ unsigned int *resource_req)
+{
+ spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG;
+ spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_BUS26M_PCM_FLAG1;
+ *resource_req |= CONSTRAINT_BUS26M_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id)
+{
+ (void)cpu;
+ (void)state_id;
+
+ return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
+}
+
+int spm_update_rc_bus26m(int state_id, int type, const void *val)
+{
+ const struct mt_spm_cond_tables *tlb;
+ const struct mt_spm_cond_tables *tlb_check;
+ int res = MT_RM_STATUS_OK;
+
+ if (val == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ if (type == PLAT_RC_UPDATE_CONDITION) {
+ tlb = (const struct mt_spm_cond_tables *)val;
+ tlb_check = (const struct mt_spm_cond_tables *)&cond_bus26m;
+
+ status.cond_block =
+ mt_spm_cond_check(state_id, tlb, tlb_check,
+ ((status.valid &
+ MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
+ &cond_bus26m_res : NULL);
+ } else if (type == PLAT_RC_UPDATE_REMAIN_IRQS) {
+ refer2remain_irq = (struct mt_irqremain *)val;
+ } else {
+ res = MT_RM_STATUS_BAD;
+ }
+
+ return res;
+}
+
+unsigned int spm_allow_rc_bus26m(int state_id)
+{
+ (void)state_id;
+
+ return CONSTRAINT_BUS26M_ALLOW;
+}
+
+int spm_run_rc_bus26m(unsigned int cpu, int state_id)
+{
+ (void)cpu;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, CONSTRAINT_BUS26M_ALLOW |
+ (IS_PLAT_SUSPEND_ID(state_id) ?
+ MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
+#endif
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_enter(state_id,
+ (MT_SPM_EX_OP_SET_WDT |
+ MT_SPM_EX_OP_HW_S1_DETECT |
+ MT_SPM_EX_OP_SET_SUSPEND_MODE |
+ bus26m_ext_opand),
+ CONSTRAINT_BUS26M_RESOURCE_REQ);
+ } else {
+ mt_spm_idle_generic_enter(state_id, MT_SPM_EX_OP_HW_S1_DETECT,
+ spm_bus26m_conduct);
+ }
+
+ return 0;
+}
+
+int spm_reset_rc_bus26m(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+
+ (void)cpu;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
+#endif
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ ext_op |= (bus26m_ext_opand | MT_SPM_EX_OP_SET_WDT);
+ mt_spm_suspend_resume(state_id, ext_op, NULL);
+ bus26m_ext_opand = 0U;
+ } else {
+ mt_spm_idle_generic_resume(state_id, ext_op, NULL);
+ status.enter_cnt++;
+ }
+
+ do_irqs_delivery();
+
+ return 0;
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c
new file mode 100644
index 0000000..cf71350
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_cpu_buck_ldo.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_suspend.h>
+#include <plat_pm.h>
+
+#define CONSTRAINT_CPU_BUCK_PCM_FLAG \
+ (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_SRAM_SLEEP_CTRL | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP |\
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH)
+
+#define CONSTRAINT_CPU_BUCK_PCM_FLAG1 0U
+
+#define CONSTRAINT_CPU_BUCK_RESOURCE_REQ \
+ (MT_SPM_DRAM_S1 | \
+ MT_SPM_DRAM_S0 | \
+ MT_SPM_SYSPLL | \
+ MT_SPM_INFRA | \
+ MT_SPM_26M | \
+ MT_SPM_XO_FPM)
+
+
+static unsigned int cpubuckldo_status = MT_SPM_RC_VALID_SW;
+static unsigned int cpubuckldo_enter_cnt;
+
+static void spm_cpu_bcuk_ldo_conduct(struct spm_lp_scen *spm_lp,
+ unsigned int *resource_req)
+{
+ spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG;
+ spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_CPU_BUCK_PCM_FLAG1;
+ *resource_req |= CONSTRAINT_CPU_BUCK_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+ (void)cpu;
+ (void)state_id;
+
+ return IS_MT_RM_RC_READY(cpubuckldo_status);
+}
+
+unsigned int spm_allow_rc_cpu_buck_ldo(int state_id)
+{
+ (void)state_id;
+
+ return MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF;
+}
+
+int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+ (void)cpu;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER,
+ (IS_PLAT_SUSPEND_ID(state_id) ?
+ MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
+#endif
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_enter(state_id,
+ MT_SPM_EX_OP_SET_SUSPEND_MODE |
+ MT_SPM_EX_OP_SET_WDT,
+ CONSTRAINT_CPU_BUCK_RESOURCE_REQ);
+ } else {
+ mt_spm_idle_generic_enter(state_id, 0U,
+ spm_cpu_bcuk_ldo_conduct);
+ }
+
+ cpubuckldo_enter_cnt++;
+
+ return 0;
+}
+
+int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id)
+{
+ (void)cpu;
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, 0U);
+#endif
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_resume(state_id, MT_SPM_EX_OP_SET_WDT, NULL);
+ } else {
+ mt_spm_idle_generic_resume(state_id, 0U, NULL);
+ }
+
+ return 0;
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_dram.c b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_dram.c
new file mode 100644
index 0000000..bd24ddd
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_dram.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+
+#include <mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_suspend.h>
+#include <plat_pm.h>
+#include <plat_mtk_lpm.h>
+
+#define CONSTRAINT_DRAM_ALLOW \
+ (MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
+ MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF)
+
+#define CONSTRAINT_DRAM_PCM_FLAG \
+ (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_SRAM_SLEEP_CTRL | \
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP)
+
+#define CONSTRAINT_DRAM_PCM_FLAG1 0U
+
+#define CONSTRAINT_DRAM_RESOURCE_REQ \
+ (MT_SPM_SYSPLL | \
+ MT_SPM_INFRA | \
+ MT_SPM_26M)
+
+static struct mt_spm_cond_tables cond_dram = {
+ .name = "dram",
+ .table_cg = {
+ 0xFFFDD008, /* MTCMOS1 */
+ 0x20040802, /* INFRA0 */
+ 0x27AF8000, /* INFRA1 */
+ 0x86040640, /* INFRA2 */
+ 0x00000000, /* INFRA3 */
+ 0x80000000, /* INFRA4 */
+ 0x00000000, /* PERI0 */
+ 0x00004000, /* VPPSYS0_0 */
+ 0x08803000, /* VPPSYS0_1 */
+ 0x00000000, /* VPPSYS0_2 */
+ 0x80005555, /* VPPSYS1_0 */
+ 0x00009008, /* VPPSYS1_1 */
+ 0x60060000, /* VDOSYS0_0 */
+ 0x00000000, /* VDOSYS0_1 */
+ 0x201E01F8, /* VDOSYS1_0 */
+ 0x00800000, /* VDOSYS1_1 */
+ 0x00000000, /* VDOSYS1_2 */
+ 0x00000080, /* I2C */
+ },
+ .table_pll = 0U,
+};
+
+static struct mt_spm_cond_tables cond_dram_res = {
+ .table_cg = { 0U },
+ .table_pll = 0U,
+};
+
+static struct constraint_status status = {
+ .id = MT_RM_CONSTRAINT_ID_DRAM,
+ .valid = (MT_SPM_RC_VALID_SW |
+ MT_SPM_RC_VALID_COND_LATCH |
+ MT_SPM_RC_VALID_XSOC_BBLPM),
+ .cond_block = 0U,
+ .enter_cnt = 0U,
+ .cond_res = &cond_dram_res,
+};
+
+static void spm_dram_conduct(struct spm_lp_scen *spm_lp,
+ unsigned int *resource_req)
+{
+ spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG;
+ spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_DRAM_PCM_FLAG1;
+ *resource_req |= CONSTRAINT_DRAM_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_dram(unsigned int cpu, int state_id)
+{
+ (void)cpu;
+ (void)state_id;
+
+ return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
+}
+
+int spm_update_rc_dram(int state_id, int type, const void *val)
+{
+ const struct mt_spm_cond_tables *tlb;
+ const struct mt_spm_cond_tables *tlb_check;
+ int res = MT_RM_STATUS_OK;
+
+ if (val == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ if (type == PLAT_RC_UPDATE_CONDITION) {
+ tlb = (const struct mt_spm_cond_tables *)val;
+ tlb_check = (const struct mt_spm_cond_tables *)&cond_dram;
+ status.cond_block =
+ mt_spm_cond_check(state_id, tlb, tlb_check,
+ ((status.valid &
+ MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
+ &cond_dram_res : NULL);
+ } else {
+ res = MT_RM_STATUS_BAD;
+ }
+
+ return res;
+}
+
+unsigned int spm_allow_rc_dram(int state_id)
+{
+ (void)state_id;
+
+ return CONSTRAINT_DRAM_ALLOW;
+}
+
+int spm_run_rc_dram(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+ unsigned int allows = CONSTRAINT_DRAM_ALLOW;
+
+ (void)cpu;
+
+ if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+ ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+ allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+ }
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows |
+ (IS_PLAT_SUSPEND_ID(state_id) ?
+ MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
+#else
+ (void)allows;
+#endif
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_enter(state_id,
+ (MT_SPM_EX_OP_SET_WDT |
+ MT_SPM_EX_OP_SET_SUSPEND_MODE |
+ MT_SPM_EX_OP_HW_S1_DETECT),
+ CONSTRAINT_DRAM_RESOURCE_REQ);
+ } else {
+ mt_spm_idle_generic_enter(state_id, ext_op, spm_dram_conduct);
+ }
+
+ return 0;
+}
+
+int spm_reset_rc_dram(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+ unsigned int allows = CONSTRAINT_DRAM_ALLOW;
+
+ (void)cpu;
+
+ if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+ ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+ allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+ }
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
+#else
+ (void)allows;
+#endif
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_resume(state_id,
+ (MT_SPM_EX_OP_SET_WDT |
+ MT_SPM_EX_OP_HW_S1_DETECT),
+ NULL);
+ } else {
+ mt_spm_idle_generic_resume(state_id, ext_op, NULL);
+ status.enter_cnt++;
+ }
+
+ return 0;
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_internal.h b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_internal.h
new file mode 100644
index 0000000..9e74ace
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_internal.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RC_INTERNAL_H
+#define MT_SPM_RC_INTERNAL_H
+
+#include <stdbool.h>
+
+#define SPM_FLAG_SRAM_SLEEP_CTRL \
+ (SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
+ SPM_FLAG_DISABLE_SYSRAM_SLEEP)
+
+/* cpu buck/ldo constraint function */
+bool spm_is_valid_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+unsigned int spm_allow_rc_cpu_buck_ldo(int state_id);
+int spm_run_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+int spm_reset_rc_cpu_buck_ldo(unsigned int cpu, int state_id);
+
+/* spm resource dram constraint function */
+bool spm_is_valid_rc_dram(unsigned int cpu, int state_id);
+int spm_update_rc_dram(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_dram(int state_id);
+int spm_run_rc_dram(unsigned int cpu, int state_id);
+int spm_reset_rc_dram(unsigned int cpu, int state_id);
+
+/* spm resource syspll constraint function */
+bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id);
+int spm_update_rc_syspll(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_syspll(int state_id);
+int spm_run_rc_syspll(unsigned int cpu, int state_id);
+int spm_reset_rc_syspll(unsigned int cpu, int state_id);
+
+/* spm resource bus26m constraint function */
+bool spm_is_valid_rc_bus26m(unsigned int cpu, int state_id);
+int spm_update_rc_bus26m(int state_id, int type, const void *val);
+unsigned int spm_allow_rc_bus26m(int state_id);
+int spm_run_rc_bus26m(unsigned int cpu, int state_id);
+int spm_reset_rc_bus26m(unsigned int cpu, int state_id);
+#endif /* MT_SPM_RC_INTERNAL_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_syspll.c b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_syspll.c
new file mode 100644
index 0000000..662f85e
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/constraints/mt_spm_rc_syspll.c
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+
+#include <mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_notifier.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_suspend.h>
+#include <plat_pm.h>
+#include <plat_mtk_lpm.h>
+
+#define CONSTRAINT_SYSPLL_ALLOW \
+ (MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S0 | \
+ MT_RM_CONSTRAINT_ALLOW_DRAM_S1 | \
+ MT_RM_CONSTRAINT_ALLOW_VCORE_LP)
+
+#define CONSTRAINT_SYSPLL_PCM_FLAG \
+ (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_SRAM_SLEEP_CTRL | \
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
+ SPM_FLAG_ENABLE_6315_CTRL | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP |\
+ SPM_FLAG_USE_SRCCLKENO2)
+
+#define CONSTRAINT_SYSPLL_PCM_FLAG1 0U
+#define CONSTRAINT_SYSPLL_RESOURCE_REQ (MT_SPM_26M)
+
+static struct mt_spm_cond_tables cond_syspll = {
+ .name = "syspll",
+ .table_cg = {
+ 0xFFFFD008, /* MTCMOS1 */
+ 0x20844802, /* INFRA0 */
+ 0x27AF8000, /* INFRA1 */
+ 0x86040640, /* INFRA2 */
+ 0x30038020, /* INFRA3 */
+ 0x80000000, /* INFRA4 */
+ 0x00080A8B, /* PERI0 */
+ 0x00004000, /* VPPSYS0_0 */
+ 0x08803000, /* VPPSYS0_1 */
+ 0x00000000, /* VPPSYS0_2 */
+ 0x80005555, /* VPPSYS1_0 */
+ 0x00009008, /* VPPSYS1_1 */
+ 0x60060000, /* VDOSYS0_0 */
+ 0x00000000, /* VDOSYS0_1 */
+ 0x201E01F8, /* VDOSYS1_0 */
+ 0x00800000, /* VDOSYS1_1 */
+ 0x00000000, /* VDOSYS1_2 */
+ 0x00000080, /* I2C */
+ },
+ .table_pll = 0U,
+};
+
+static struct mt_spm_cond_tables cond_syspll_res = {
+ .table_cg = { 0U },
+ .table_pll = 0U,
+};
+
+static struct constraint_status status = {
+ .id = MT_RM_CONSTRAINT_ID_SYSPLL,
+ .valid = (MT_SPM_RC_VALID_SW |
+ MT_SPM_RC_VALID_COND_LATCH |
+ MT_SPM_RC_VALID_XSOC_BBLPM),
+ .cond_block = 0U,
+ .enter_cnt = 0U,
+ .cond_res = &cond_syspll_res,
+};
+
+static void spm_syspll_conduct(struct spm_lp_scen *spm_lp,
+ unsigned int *resource_req)
+{
+ spm_lp->pwrctrl->pcm_flags = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG;
+ spm_lp->pwrctrl->pcm_flags1 = (uint32_t)CONSTRAINT_SYSPLL_PCM_FLAG1;
+ *resource_req |= CONSTRAINT_SYSPLL_RESOURCE_REQ;
+}
+
+bool spm_is_valid_rc_syspll(unsigned int cpu, int state_id)
+{
+ (void)cpu;
+ (void)state_id;
+
+ return (status.cond_block == 0U) && IS_MT_RM_RC_READY(status.valid);
+}
+
+int spm_update_rc_syspll(int state_id, int type, const void *val)
+{
+ const struct mt_spm_cond_tables *tlb;
+ const struct mt_spm_cond_tables *tlb_check;
+ int res = MT_RM_STATUS_OK;
+
+ if (val == NULL) {
+ return MT_RM_STATUS_BAD;
+ }
+
+ if (type == PLAT_RC_UPDATE_CONDITION) {
+ tlb = (const struct mt_spm_cond_tables *)val;
+ tlb_check = (const struct mt_spm_cond_tables *)&cond_syspll;
+
+ status.cond_block =
+ mt_spm_cond_check(state_id, tlb, tlb_check,
+ ((status.valid &
+ MT_SPM_RC_VALID_COND_LATCH) != 0U) ?
+ &cond_syspll_res : NULL);
+ } else {
+ res = MT_RM_STATUS_BAD;
+ }
+
+ return res;
+}
+
+unsigned int spm_allow_rc_syspll(int state_id)
+{
+ (void)state_id;
+
+ return CONSTRAINT_SYSPLL_ALLOW;
+}
+
+int spm_run_rc_syspll(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+ unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
+
+ (void)cpu;
+
+ if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+ ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+ allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+ }
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_ENTER, allows |
+ (IS_PLAT_SUSPEND_ID(state_id) ?
+ MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND : 0U));
+#else
+ (void)allows;
+#endif
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_enter(state_id,
+ (MT_SPM_EX_OP_SET_WDT |
+ MT_SPM_EX_OP_HW_S1_DETECT |
+ MT_SPM_EX_OP_SET_SUSPEND_MODE),
+ CONSTRAINT_SYSPLL_RESOURCE_REQ);
+ } else {
+ mt_spm_idle_generic_enter(state_id, ext_op, spm_syspll_conduct);
+ }
+
+ return 0;
+}
+
+int spm_reset_rc_syspll(unsigned int cpu, int state_id)
+{
+ unsigned int ext_op = MT_SPM_EX_OP_HW_S1_DETECT;
+ unsigned int allows = CONSTRAINT_SYSPLL_ALLOW;
+
+ (void)cpu;
+
+ if (IS_MT_SPM_RC_BBLPM_MODE(status.valid)) {
+#ifdef MT_SPM_USING_SRCLKEN_RC
+ ext_op |= MT_SPM_EX_OP_SRCLKEN_RC_BBLPM;
+#else
+ allows |= MT_RM_CONSTRAINT_ALLOW_BBLPM;
+#endif
+ }
+
+#ifndef ATF_PLAT_SPM_SSPM_NOTIFIER_UNSUPPORT
+ mt_spm_sspm_notify_u32(MT_SPM_NOTIFY_LP_LEAVE, allows);
+#else
+ (void)allows;
+#endif
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ mt_spm_suspend_resume(state_id,
+ (MT_SPM_EX_OP_SET_SUSPEND_MODE |
+ MT_SPM_EX_OP_SET_WDT |
+ MT_SPM_EX_OP_HW_S1_DETECT),
+ NULL);
+ } else {
+ mt_spm_idle_generic_resume(state_id, ext_op, NULL);
+ status.enter_cnt++;
+ }
+
+ return 0;
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm.c b/plat/mediatek/mt8195/drivers/spm/mt_spm.c
new file mode 100644
index 0000000..f708bf5
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+#include <string.h>
+#include <common/debug.h>
+#include <lib/bakery_lock.h>
+#include <lib/mmio.h>
+#include <mt_lp_rm.h>
+#include <mt_spm.h>
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_pmic_wrap.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_suspend.h>
+#include <mtk_plat_common.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+#include <platform_def.h>
+#include <sleep_def.h>
+
+#ifdef MT_SPM_USING_BAKERY_LOCK
+DEFINE_BAKERY_LOCK(spm_lock);
+#define plat_spm_lock_init() bakery_lock_init(&spm_lock)
+#else
+spinlock_t spm_lock;
+#define plat_spm_lock_init()
+#endif
+
+/* CLK_SCP_CFG_0 */
+#define CLK_SCP_CFG_0 (TOPCKGEN_BASE + 0x264)
+#define SPM_CK_CONTROL_EN 0x7FF
+
+struct mt_resource_constraint plat_constraint_bus26m = {
+ .is_valid = spm_is_valid_rc_bus26m,
+ .update = spm_update_rc_bus26m,
+ .allow = spm_allow_rc_bus26m,
+ .run = spm_run_rc_bus26m,
+ .reset = spm_reset_rc_bus26m,
+};
+
+struct mt_resource_constraint plat_constraint_syspll = {
+ .is_valid = spm_is_valid_rc_syspll,
+ .update = spm_update_rc_syspll,
+ .allow = spm_allow_rc_syspll,
+ .run = spm_run_rc_syspll,
+ .reset = spm_reset_rc_syspll,
+};
+
+struct mt_resource_constraint plat_constraint_dram = {
+ .is_valid = spm_is_valid_rc_dram,
+ .update = spm_update_rc_dram,
+ .allow = spm_allow_rc_dram,
+ .run = spm_run_rc_dram,
+ .reset = spm_reset_rc_dram,
+};
+
+struct mt_resource_constraint plat_constraint_cpu = {
+ .is_valid = spm_is_valid_rc_cpu_buck_ldo,
+ .update = NULL,
+ .allow = spm_allow_rc_cpu_buck_ldo,
+ .run = spm_run_rc_cpu_buck_ldo,
+ .reset = spm_reset_rc_cpu_buck_ldo,
+};
+
+struct mt_resource_constraint *plat_constraints[] = {
+ &plat_constraint_bus26m,
+ &plat_constraint_syspll,
+ &plat_constraint_dram,
+ &plat_constraint_cpu,
+ NULL,
+};
+
+struct mt_resource_manager plat_mt8195_rm = {
+ .update = mt_spm_cond_update,
+ .consts = plat_constraints,
+};
+
+void spm_boot_init(void)
+{
+ NOTICE("MT8195 %s\n", __func__);
+ /* switch ck_off/axi_26m control to SPM */
+ mmio_setbits_32(CLK_SCP_CFG_0, SPM_CK_CONTROL_EN);
+
+ plat_spm_lock_init();
+ mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
+ mt_lp_rm_register(&plat_mt8195_rm);
+ mt_spm_idle_generic_init();
+ mt_spm_suspend_init();
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm.h b/plat/mediatek/mt8195/drivers/spm/mt_spm.h
new file mode 100644
index 0000000..bc57b61
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_H
+#define MT_SPM_H
+
+#include <lib/bakery_lock.h>
+#include <lib/spinlock.h>
+
+#include <plat_mtk_lpm.h>
+
+/*
+ * ARM v8.2, the cache will turn off automatically when cpu
+ * power down. So, there is no doubt to use the spin_lock here
+ */
+#if !HW_ASSISTED_COHERENCY
+#define MT_SPM_USING_BAKERY_LOCK
+#endif
+
+#ifdef MT_SPM_USING_BAKERY_LOCK
+DECLARE_BAKERY_LOCK(spm_lock);
+#define plat_spm_lock() bakery_lock_get(&spm_lock)
+#define plat_spm_unlock() bakery_lock_release(&spm_lock)
+#else
+extern spinlock_t spm_lock;
+#define plat_spm_lock() spin_lock(&spm_lock)
+#define plat_spm_unlock() spin_unlock(&spm_lock)
+#endif
+
+#define MT_SPM_USING_SRCLKEN_RC
+
+/* spm extern operand definition */
+#define MT_SPM_EX_OP_CLR_26M_RECORD (1U << 0)
+#define MT_SPM_EX_OP_SET_WDT (1U << 1)
+#define MT_SPM_EX_OP_NON_GENERIC_RESOURCE_REQ (1U << 2)
+#define MT_SPM_EX_OP_SET_SUSPEND_MODE (1U << 3)
+#define MT_SPM_EX_OP_SET_IS_ADSP (1U << 4)
+#define MT_SPM_EX_OP_SRCLKEN_RC_BBLPM (1U << 5)
+#define MT_SPM_EX_OP_HW_S1_DETECT (1U << 6)
+
+typedef enum {
+ WR_NONE = 0,
+ WR_UART_BUSY = 1,
+ WR_ABORT = 2,
+ WR_PCM_TIMER = 3,
+ WR_WAKE_SRC = 4,
+ WR_DVFSRC = 5,
+ WR_TWAM = 6,
+ WR_PMSR = 7,
+ WR_SPM_ACK_CHK = 8,
+ WR_UNKNOWN = 9,
+} wake_reason_t;
+
+static inline void spm_lock_get(void)
+{
+ plat_spm_lock();
+}
+
+static inline void spm_lock_release(void)
+{
+ plat_spm_unlock();
+}
+
+extern void spm_boot_init(void);
+#endif /* MT_SPM_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.c b/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.c
new file mode 100644
index 0000000..c80faf5
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.c
@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include <mt_spm_cond.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_constraint.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+#include <platform_def.h>
+
+#define MT_LP_TZ_INFRA_REG(ofs) (INFRACFG_AO_BASE + ofs)
+#define MT_LP_TZ_SPM_REG(ofs) (SPM_BASE + ofs)
+#define MT_LP_TZ_TOPCK_REG(ofs) (TOPCKGEN_BASE + ofs)
+#define MT_LP_TZ_APMIXEDSYS(ofs) (APMIXEDSYS + ofs)
+#define MT_LP_TZ_VPPSYS0_REG(ofs) (VPPSYS0_BASE + ofs)
+#define MT_LP_TZ_VPPSYS1_REG(ofs) (VPPSYS1_BASE + ofs)
+#define MT_LP_TZ_VDOSYS0_REG(ofs) (VDOSYS0_BASE + ofs)
+#define MT_LP_TZ_VDOSYS1_REG(ofs) (VDOSYS1_BASE + ofs)
+#define MT_LP_TZ_PERI_AO_REG(ofs) (PERICFG_AO_BASE + ofs)
+
+#define SPM_PWR_STATUS MT_LP_TZ_SPM_REG(0x016C)
+#define SPM_PWR_STATUS_2ND MT_LP_TZ_SPM_REG(0x0170)
+#define INFRA_SW_CG0 MT_LP_TZ_INFRA_REG(0x0094)
+#define INFRA_SW_CG1 MT_LP_TZ_INFRA_REG(0x0090)
+#define INFRA_SW_CG2 MT_LP_TZ_INFRA_REG(0x00AC)
+#define INFRA_SW_CG3 MT_LP_TZ_INFRA_REG(0x00C8)
+#define INFRA_SW_CG4 MT_LP_TZ_INFRA_REG(0x00E8)
+#define TOP_SW_I2C_CG MT_LP_TZ_TOPCK_REG(0x00BC)
+#define PERI_SW_CG0 MT_LP_TZ_PERI_AO_REG(0x0018)
+#define VPPSYS0_SW_CG0 MT_LP_TZ_VPPSYS0_REG(0x0020)
+#define VPPSYS0_SW_CG1 MT_LP_TZ_VPPSYS0_REG(0x002C)
+#define VPPSYS0_SW_CG2 MT_LP_TZ_VPPSYS0_REG(0x0038)
+#define VPPSYS1_SW_CG0 MT_LP_TZ_VPPSYS1_REG(0x0100)
+#define VPPSYS1_SW_CG1 MT_LP_TZ_VPPSYS1_REG(0x0110)
+#define VDOSYS0_SW_CG0 MT_LP_TZ_VDOSYS0_REG(0x0100)
+#define VDOSYS0_SW_CG1 MT_LP_TZ_VDOSYS0_REG(0x0110)
+#define VDOSYS1_SW_CG0 MT_LP_TZ_VDOSYS1_REG(0x0100)
+#define VDOSYS1_SW_CG1 MT_LP_TZ_VDOSYS1_REG(0x0120)
+#define VDOSYS1_SW_CG2 MT_LP_TZ_VDOSYS1_REG(0x0130)
+
+/***********************************************************
+ * Check clkmux registers
+ ***********************************************************/
+#define CLK_CFG(id) MT_LP_TZ_TOPCK_REG(0x98 + id * 0x10)
+#define PDN_CHECK BIT(7)
+#define CLK_CHECK BIT(31)
+
+enum {
+ CLKMUX_DISP = 0,
+ NF_CLKMUX,
+};
+
+static bool is_clkmux_pdn(unsigned int clkmux_id)
+{
+ unsigned int reg, val, idx;
+
+ if ((clkmux_id & CLK_CHECK) != 0U) {
+ clkmux_id = (clkmux_id & ~CLK_CHECK);
+ reg = clkmux_id / 4U;
+ val = mmio_read_32(CLK_CFG(reg));
+ idx = clkmux_id % 4U;
+ val = (val >> (idx * 8U)) & PDN_CHECK;
+ return (val != 0U);
+ }
+
+ return false;
+}
+
+static struct mt_spm_cond_tables spm_cond_t;
+
+struct idle_cond_info {
+ unsigned int subsys_mask;
+ uintptr_t addr;
+ bool bBitflip;
+ unsigned int clkmux_id;
+};
+
+#define IDLE_CG(mask, addr, bitflip, clkmux) \
+ {mask, (uintptr_t)addr, bitflip, clkmux}
+
+static struct idle_cond_info idle_cg_info[PLAT_SPM_COND_MAX] = {
+ IDLE_CG(0xffffffff, SPM_PWR_STATUS, false, 0U),
+ IDLE_CG(0xffffffff, INFRA_SW_CG0, true, 0U),
+ IDLE_CG(0xffffffff, INFRA_SW_CG1, true, 0U),
+ IDLE_CG(0xffffffff, INFRA_SW_CG2, true, 0U),
+ IDLE_CG(0xffffffff, INFRA_SW_CG3, true, 0U),
+ IDLE_CG(0xffffffff, INFRA_SW_CG4, true, 0U),
+ IDLE_CG(0xffffffff, PERI_SW_CG0, true, 0U),
+ IDLE_CG(0x00000800, VPPSYS0_SW_CG0, true, (CLK_CHECK|CLKMUX_DISP)),
+ IDLE_CG(0x00000800, VPPSYS0_SW_CG1, true, (CLK_CHECK|CLKMUX_DISP)),
+ IDLE_CG(0x00000800, VPPSYS0_SW_CG2, true, (CLK_CHECK|CLKMUX_DISP)),
+ IDLE_CG(0x00001000, VPPSYS1_SW_CG0, true, (CLK_CHECK|CLKMUX_DISP)),
+ IDLE_CG(0x00001000, VPPSYS1_SW_CG1, true, (CLK_CHECK|CLKMUX_DISP)),
+ IDLE_CG(0x00002000, VDOSYS0_SW_CG0, true, (CLK_CHECK|CLKMUX_DISP)),
+ IDLE_CG(0x00002000, VDOSYS0_SW_CG1, true, (CLK_CHECK|CLKMUX_DISP)),
+ IDLE_CG(0x00004000, VDOSYS1_SW_CG0, true, (CLK_CHECK|CLKMUX_DISP)),
+ IDLE_CG(0x00004000, VDOSYS1_SW_CG1, true, (CLK_CHECK|CLKMUX_DISP)),
+ IDLE_CG(0x00004000, VDOSYS1_SW_CG2, true, (CLK_CHECK|CLKMUX_DISP)),
+ IDLE_CG(0x00000080, TOP_SW_I2C_CG, true, (CLK_CHECK|CLKMUX_DISP)),
+};
+
+/***********************************************************
+ * Check pll idle condition
+ ***********************************************************/
+#define PLL_MFGPLL MT_LP_TZ_APMIXEDSYS(0x340)
+#define PLL_MMPLL MT_LP_TZ_APMIXEDSYS(0x0E0)
+#define PLL_UNIVPLL MT_LP_TZ_APMIXEDSYS(0x1F0)
+#define PLL_MSDCPLL MT_LP_TZ_APMIXEDSYS(0x710)
+#define PLL_TVDPLL MT_LP_TZ_APMIXEDSYS(0x380)
+
+unsigned int mt_spm_cond_check(int state_id,
+ const struct mt_spm_cond_tables *src,
+ const struct mt_spm_cond_tables *dest,
+ struct mt_spm_cond_tables *res)
+{
+ unsigned int blocked = 0U, i;
+ bool is_system_suspend = IS_PLAT_SUSPEND_ID(state_id);
+
+ if ((src == NULL) || (dest == NULL)) {
+ return SPM_COND_CHECK_FAIL;
+ }
+
+ for (i = 0U; i < PLAT_SPM_COND_MAX; i++) {
+ if (res != NULL) {
+ res->table_cg[i] =
+ (src->table_cg[i] & dest->table_cg[i]);
+
+ if (is_system_suspend && (res->table_cg[i] != 0U)) {
+ INFO("suspend: %s block[%u](0x%lx) = 0x%08x\n",
+ dest->name, i, idle_cg_info[i].addr,
+ res->table_cg[i]);
+ }
+
+ if (res->table_cg[i] != 0U) {
+ blocked |= (1U << i);
+ }
+ } else if ((src->table_cg[i] & dest->table_cg[i]) != 0U) {
+ blocked |= (1U << i);
+ break;
+ }
+ }
+
+ if (res != NULL) {
+ res->table_pll = (src->table_pll & dest->table_pll);
+
+ if (res->table_pll != 0U) {
+ blocked |=
+ (res->table_pll << SPM_COND_BLOCKED_PLL_IDX) |
+ SPM_COND_CHECK_BLOCKED_PLL;
+ }
+ } else if ((src->table_pll & dest->table_pll) != 0U) {
+ blocked |= SPM_COND_CHECK_BLOCKED_PLL;
+ }
+
+ if (is_system_suspend && (blocked != 0U)) {
+ INFO("suspend: %s blocked=0x%08x\n", dest->name, blocked);
+ }
+
+ return blocked;
+}
+
+#define IS_MT_SPM_PWR_OFF(mask) \
+ (((mmio_read_32(SPM_PWR_STATUS) & mask) == 0U) && \
+ ((mmio_read_32(SPM_PWR_STATUS_2ND) & mask) == 0U))
+
+int mt_spm_cond_update(struct mt_resource_constraint **con,
+ int stateid, void *priv)
+{
+ int res;
+ uint32_t i;
+ struct mt_resource_constraint *const *rc;
+
+ /* read all cg state */
+ for (i = 0U; i < PLAT_SPM_COND_MAX; i++) {
+ spm_cond_t.table_cg[i] = 0U;
+
+ /* check mtcmos, if off set idle_value and clk to 0 disable */
+ if (IS_MT_SPM_PWR_OFF(idle_cg_info[i].subsys_mask)) {
+ continue;
+ }
+
+ /* check clkmux */
+ if (is_clkmux_pdn(idle_cg_info[i].clkmux_id)) {
+ continue;
+ }
+
+ spm_cond_t.table_cg[i] = idle_cg_info[i].bBitflip ?
+ ~mmio_read_32(idle_cg_info[i].addr) :
+ mmio_read_32(idle_cg_info[i].addr);
+ }
+
+ spm_cond_t.table_pll = 0U;
+ if ((mmio_read_32(PLL_MFGPLL) & 0x200) != 0U) {
+ spm_cond_t.table_pll |= PLL_BIT_MFGPLL;
+ }
+
+ if ((mmio_read_32(PLL_MMPLL) & 0x200) != 0U) {
+ spm_cond_t.table_pll |= PLL_BIT_MMPLL;
+ }
+
+ if ((mmio_read_32(PLL_UNIVPLL) & 0x200) != 0U) {
+ spm_cond_t.table_pll |= PLL_BIT_UNIVPLL;
+ }
+
+ if ((mmio_read_32(PLL_MSDCPLL) & 0x200) != 0U) {
+ spm_cond_t.table_pll |= PLL_BIT_MSDCPLL;
+ }
+
+ if ((mmio_read_32(PLL_TVDPLL) & 0x200) != 0U) {
+ spm_cond_t.table_pll |= PLL_BIT_TVDPLL;
+ }
+
+ spm_cond_t.priv = priv;
+ for (rc = con; *rc != NULL; rc++) {
+ if (((*rc)->update) == NULL) {
+ continue;
+ }
+
+ res = (*rc)->update(stateid, PLAT_RC_UPDATE_CONDITION,
+ (void const *)&spm_cond_t);
+ if (res != MT_RM_STATUS_OK) {
+ break;
+ }
+ }
+
+ return 0;
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.h b/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.h
new file mode 100644
index 0000000..e471b55
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_cond.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_CONDIT_H
+#define MT_SPM_CONDIT_H
+
+#include <mt_lp_rm.h>
+
+enum PLAT_SPM_COND {
+ PLAT_SPM_COND_MTCMOS1 = 0,
+ PLAT_SPM_COND_CG_INFRA_0,
+ PLAT_SPM_COND_CG_INFRA_1,
+ PLAT_SPM_COND_CG_INFRA_2,
+ PLAT_SPM_COND_CG_INFRA_3,
+ PLAT_SPM_COND_CG_INFRA_4,
+ PLAT_SPM_COND_CG_PERI_SW_0,
+ PLAT_SPM_COND_CG_VPPSYS0_SW_CG_0,
+ PLAT_SPM_COND_CG_VPPSYS0_SW_CG_1,
+ PLAT_SPM_COND_CG_VPPSYS0_SW_CG_2,
+ PLAT_SPM_COND_CG_VPPSYS1_SW_CG_0,
+ PLAT_SPM_COND_CG_VPPSYS1_SW_CG_1,
+ PLAT_SPM_COND_CG_VDOSYS0_SW_CG_0,
+ PLAT_SPM_COND_CG_VDOSYS0_SW_CG_1,
+ PLAT_SPM_COND_CG_VDOSYS1_SW_CG_0,
+ PLAT_SPM_COND_CG_VDOSYS1_SW_CG_1,
+ PLAT_SPM_COND_CG_VDOSYS1_SW_CG_2,
+ PLAT_SPM_COND_CG_I2C_SW_CG,
+ PLAT_SPM_COND_MAX,
+};
+
+enum PLAT_SPM_COND_PLL {
+ PLAT_SPM_COND_PLL_UNIVPLL = 0,
+ PLAT_SPM_COND_PLL_MFGPLL,
+ PLAT_SPM_COND_PLL_MSDCPLL,
+ PLAT_SPM_COND_PLL_TVDPLL,
+ PLAT_SPM_COND_PLL_MMPLL,
+ PLAT_SPM_COND_PLL_MAX,
+};
+
+#define PLL_BIT_MFGPLL BIT(PLAT_SPM_COND_PLL_MFGPLL)
+#define PLL_BIT_MMPLL BIT(PLAT_SPM_COND_PLL_MMPLL)
+#define PLL_BIT_UNIVPLL BIT(PLAT_SPM_COND_PLL_UNIVPLL)
+#define PLL_BIT_MSDCPLL BIT(PLAT_SPM_COND_PLL_MSDCPLL)
+#define PLL_BIT_TVDPLL BIT(PLAT_SPM_COND_PLL_TVDPLL)
+
+/* Definition about SPM_COND_CHECK_BLOCKED
+ * bit [00 ~ 17]: cg blocking index
+ * bit [18 ~ 29]: pll blocking index
+ * bit [30] : pll blocking information
+ * bit [31] : idle condition check fail
+ */
+#define SPM_COND_BLOCKED_CG_IDX U(0)
+#define SPM_COND_BLOCKED_PLL_IDX U(18)
+#define SPM_COND_CHECK_BLOCKED_PLL BIT(30)
+#define SPM_COND_CHECK_FAIL BIT(31)
+
+struct mt_spm_cond_tables {
+ char *name;
+ unsigned int table_cg[PLAT_SPM_COND_MAX];
+ unsigned int table_pll;
+ void *priv;
+};
+
+extern unsigned int mt_spm_cond_check(int state_id,
+ const struct mt_spm_cond_tables *src,
+ const struct mt_spm_cond_tables *dest,
+ struct mt_spm_cond_tables *res);
+extern int mt_spm_cond_update(struct mt_resource_constraint **con,
+ int stateid, void *priv);
+#endif /* MT_SPM_CONDIT_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_conservation.c b/plat/mediatek/mt8195/drivers/spm/mt_spm_conservation.c
new file mode 100644
index 0000000..7f33408
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_conservation.c
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include <mt_spm.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_reg.h>
+#include <plat_mtk_lpm.h>
+#include <plat_pm.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+struct wake_status spm_wakesta; /* record last wakesta */
+
+static int go_to_spm_before_wfi(int state_id, unsigned int ext_opand,
+ struct spm_lp_scen *spm_lp,
+ unsigned int resource_req)
+{
+ int ret = 0;
+ struct pwr_ctrl *pwrctrl;
+ uint32_t cpu = plat_my_core_pos();
+
+ pwrctrl = spm_lp->pwrctrl;
+
+ __spm_set_cpu_status(cpu);
+ __spm_set_power_control(pwrctrl);
+ __spm_set_wakeup_event(pwrctrl);
+ __spm_set_pcm_flags(pwrctrl);
+ __spm_src_req_update(pwrctrl, resource_req);
+
+ if ((ext_opand & MT_SPM_EX_OP_SET_WDT) != 0U) {
+ __spm_set_pcm_wdt(1);
+ }
+
+ if ((ext_opand & MT_SPM_EX_OP_SRCLKEN_RC_BBLPM) != 0U) {
+ __spm_xo_soc_bblpm(1);
+ }
+
+ if ((ext_opand & MT_SPM_EX_OP_HW_S1_DETECT) != 0U) {
+ spm_hw_s1_state_monitor_resume();
+ }
+
+ /* Disable auto resume by PCM in system suspend stage */
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ __spm_disable_pcm_timer();
+ __spm_set_pcm_wdt(0);
+ }
+
+ __spm_send_cpu_wakeup_event();
+
+ INFO("cpu%d: wakesrc = 0x%x, settle = 0x%x, sec = %u\n",
+ cpu, pwrctrl->wake_src, mmio_read_32(SPM_CLK_SETTLE),
+ mmio_read_32(PCM_TIMER_VAL) / 32768);
+ INFO("sw_flag = 0x%x 0x%x, req = 0x%x, pwr = 0x%x 0x%x\n",
+ pwrctrl->pcm_flags, pwrctrl->pcm_flags1,
+ mmio_read_32(SPM_SRC_REQ), mmio_read_32(PWR_STATUS),
+ mmio_read_32(PWR_STATUS_2ND));
+ INFO("cpu_pwr = 0x%x 0x%x\n", mmio_read_32(CPU_PWR_STATUS),
+ mmio_read_32(CPU_PWR_STATUS_2ND));
+
+ return ret;
+}
+
+static void go_to_spm_after_wfi(int state_id, unsigned int ext_opand,
+ struct spm_lp_scen *spm_lp,
+ struct wake_status **status)
+{
+ unsigned int ext_status = 0U;
+
+ /* system watchdog will be resumed at kernel stage */
+ if ((ext_opand & MT_SPM_EX_OP_SET_WDT) != 0U) {
+ __spm_set_pcm_wdt(0);
+ }
+
+ if ((ext_opand & MT_SPM_EX_OP_SRCLKEN_RC_BBLPM) != 0U) {
+ __spm_xo_soc_bblpm(0);
+ }
+
+ if ((ext_opand & MT_SPM_EX_OP_HW_S1_DETECT) != 0U) {
+ spm_hw_s1_state_monitor_pause(&ext_status);
+ }
+
+ __spm_ext_int_wakeup_req_clr();
+ __spm_get_wakeup_status(&spm_wakesta, ext_status);
+
+ if (status != NULL) {
+ *status = &spm_wakesta;
+ }
+
+ __spm_clean_after_wakeup();
+
+ if (IS_PLAT_SUSPEND_ID(state_id)) {
+ __spm_output_wake_reason(state_id, &spm_wakesta);
+ }
+}
+
+int spm_conservation(int state_id, unsigned int ext_opand,
+ struct spm_lp_scen *spm_lp, unsigned int resource_req)
+{
+ if (spm_lp == NULL) {
+ return -1;
+ }
+
+ spm_lock_get();
+ go_to_spm_before_wfi(state_id, ext_opand, spm_lp, resource_req);
+ spm_lock_release();
+
+ return 0;
+}
+
+void spm_conservation_finish(int state_id, unsigned int ext_opand,
+ struct spm_lp_scen *spm_lp,
+ struct wake_status **status)
+{
+ spm_lock_get();
+ go_to_spm_after_wfi(state_id, ext_opand, spm_lp, status);
+ spm_lock_release();
+}
+
+int spm_conservation_get_result(struct wake_status **res)
+{
+ if (res == NULL) {
+ return -1;
+ }
+
+ *res = &spm_wakesta;
+
+ return 0;
+}
+
+#define GPIO_BANK (GPIO_BASE + 0x6F0)
+#define TRAP_UFS_FIRST BIT(11) /* bit 11, 0: UFS, 1: eMMC */
+
+void spm_conservation_pwrctrl_init(struct pwr_ctrl *pwrctrl)
+{
+ if (pwrctrl == NULL) {
+ return;
+ }
+
+ /* For ufs, emmc storage type */
+ if ((mmio_read_32(GPIO_BANK) & TRAP_UFS_FIRST) != 0U) {
+ /* If eMMC is used, mask UFS req */
+ pwrctrl->reg_ufs_srcclkena_mask_b = 0;
+ pwrctrl->reg_ufs_infra_req_mask_b = 0;
+ pwrctrl->reg_ufs_apsrc_req_mask_b = 0;
+ pwrctrl->reg_ufs_vrf18_req_mask_b = 0;
+ pwrctrl->reg_ufs_ddr_en_mask_b = 0;
+ }
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_conservation.h b/plat/mediatek/mt8195/drivers/spm/mt_spm_conservation.h
new file mode 100644
index 0000000..aa627e7
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_conservation.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_CONSERVATION_H
+#define MT_SPM_CONSERVATION_H
+
+#include <mt_spm_internal.h>
+
+extern int spm_conservation(int state_id, unsigned int ext_opand,
+ struct spm_lp_scen *spm_lp,
+ unsigned int resource_req);
+extern void spm_conservation_finish(int state_id, unsigned int ext_opand,
+ struct spm_lp_scen *spm_lp,
+ struct wake_status **status);
+extern int spm_conservation_get_result(struct wake_status **res);
+extern void spm_conservation_pwrctrl_init(struct pwr_ctrl *pwrctrl);
+#endif /* MT_SPM_CONSERVATION_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_constraint.h b/plat/mediatek/mt8195/drivers/spm/mt_spm_constraint.h
new file mode 100644
index 0000000..944c227
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_constraint.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_CONSTRAINT_H
+#define MT_SPM_CONSTRAINT_H
+
+#include <mt_lp_rm.h>
+
+#define MT_RM_CONSTRAINT_ALLOW_CPU_BUCK_OFF (1U << 0)
+#define MT_RM_CONSTRAINT_ALLOW_DRAM_S0 (1U << 1)
+#define MT_RM_CONSTRAINT_ALLOW_DRAM_S1 (1U << 2)
+#define MT_RM_CONSTRAINT_ALLOW_VCORE_LP (1U << 3)
+#define MT_RM_CONSTRAINT_ALLOW_INFRA_PDN (1U << 4)
+#define MT_RM_CONSTRAINT_ALLOW_BUS26M_OFF (1U << 5)
+#define MT_RM_CONSTRAINT_ALLOW_AP_SUSPEND (1U << 6)
+#define MT_RM_CONSTRAINT_ALLOW_BBLPM (1U << 7)
+#define MT_RM_CONSTRAINT_ALLOW_XO_UFS (1U << 8)
+#define MT_RM_CONSTRAINT_ALLOW_GPS_STATE (1U << 9)
+#define MT_RM_CONSTRAINT_ALLOW_LVTS_STATE (1U << 10)
+
+#define MT_SPM_RC_INVALID 0x0
+#define MT_SPM_RC_VALID_SW (1U << 0)
+#define MT_SPM_RC_VALID_FW (1U << 1)
+#define MT_SPM_RC_VALID_RESIDNECY (1U << 2)
+#define MT_SPM_RC_VALID_COND_CHECK (1U << 3)
+#define MT_SPM_RC_VALID_COND_LATCH (1U << 4)
+#define MT_SPM_RC_VALID_UFS_H8 (1U << 5)
+#define MT_SPM_RC_VALID_FLIGHTMODE (1U << 6)
+#define MT_SPM_RC_VALID_XSOC_BBLPM (1U << 7)
+#define MT_SPM_RC_VALID_TRACE_EVENT (1U << 8)
+
+#define MT_SPM_RC_VALID (MT_SPM_RC_VALID_SW)
+
+#define IS_MT_RM_RC_READY(status) \
+ ((status & MT_SPM_RC_VALID) == MT_SPM_RC_VALID)
+
+#define MT_SPM_RC_BBLPM_MODE \
+ (MT_SPM_RC_VALID_UFS_H8 | \
+ MT_SPM_RC_VALID_FLIGHTMODE | \
+ MT_SPM_RC_VALID_XSOC_BBLPM)
+
+#define IS_MT_SPM_RC_BBLPM_MODE(st) \
+ ((st & (MT_SPM_RC_BBLPM_MODE)) == MT_SPM_RC_BBLPM_MODE)
+
+struct constraint_status {
+ uint16_t id;
+ uint16_t valid;
+ uint32_t cond_block;
+ uint32_t enter_cnt;
+ struct mt_spm_cond_tables *cond_res;
+};
+
+enum MT_SPM_RM_RC_TYPE {
+ MT_RM_CONSTRAINT_ID_BUS26M,
+ MT_RM_CONSTRAINT_ID_SYSPLL,
+ MT_RM_CONSTRAINT_ID_DRAM,
+ MT_RM_CONSTRAINT_ID_CPU_BUCK_LDO,
+ MT_RM_CONSTRAINT_ID_ALL,
+};
+#endif /* MT_SPM_CONSTRAINT_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_idle.c b/plat/mediatek/mt8195/drivers/spm/mt_spm_idle.c
new file mode 100644
index 0000000..4bafe95
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_idle.c
@@ -0,0 +1,346 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include <mt_spm.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_idle.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <plat_pm.h>
+
+#define __WAKE_SRC_FOR_IDLE_COMMON__ \
+ (R12_PCM_TIMER | \
+ R12_KP_IRQ_B | \
+ R12_APWDT_EVENT_B | \
+ R12_APXGPT1_EVENT_B | \
+ R12_CONN2AP_SPM_WAKEUP_B | \
+ R12_EINT_EVENT_B | \
+ R12_CONN_WDT_IRQ_B | \
+ R12_CCIF0_EVENT_B | \
+ R12_SSPM2SPM_WAKEUP_B | \
+ R12_SCP2SPM_WAKEUP_B | \
+ R12_ADSP2SPM_WAKEUP_B | \
+ R12_USBX_CDSC_B | \
+ R12_USBX_POWERDWN_B | \
+ R12_SYS_TIMER_EVENT_B | \
+ R12_EINT_EVENT_SECURE_B | \
+ R12_AFE_IRQ_MCU_B | \
+ R12_SYS_CIRQ_IRQ_B | \
+ R12_MD2AP_PEER_EVENT_B | \
+ R12_MD1_WDT_B | \
+ R12_CLDMA_EVENT_B | \
+ R12_REG_CPU_WAKEUP | \
+ R12_APUSYS_WAKE_HOST_B)
+
+#if defined(CFG_MICROTRUST_TEE_SUPPORT)
+#define WAKE_SRC_FOR_IDLE (__WAKE_SRC_FOR_IDLE_COMMON__)
+#else
+#define WAKE_SRC_FOR_IDLE \
+ (__WAKE_SRC_FOR_IDLE_COMMON__ | \
+ R12_SEJ_EVENT_B)
+#endif
+
+static struct pwr_ctrl idle_spm_pwr = {
+ .wake_src = WAKE_SRC_FOR_IDLE,
+
+ /* SPM_AP_STANDBY_CON */
+ /* [0] */
+ .reg_wfi_op = 0,
+ /* [1] */
+ .reg_wfi_type = 0,
+ /* [2] */
+ .reg_mp0_cputop_idle_mask = 0,
+ /* [3] */
+ .reg_mp1_cputop_idle_mask = 0,
+ /* [4] */
+ .reg_mcusys_idle_mask = 0,
+ /* [25] */
+ .reg_md_apsrc_1_sel = 0,
+ /* [26] */
+ .reg_md_apsrc_0_sel = 0,
+ /* [29] */
+ .reg_conn_apsrc_sel = 0,
+
+ /* SPM_SRC_REQ */
+ /* [0] */
+ .reg_spm_apsrc_req = 0,
+ /* [1] */
+ .reg_spm_f26m_req = 1,
+ /* [3] */
+ .reg_spm_infra_req = 1,
+ /* [4] */
+ .reg_spm_vrf18_req = 0,
+ /* [7] FIXME: default disable HW Auto S1 */
+ .reg_spm_ddr_en_req = 1,
+ /* [8] */
+ .reg_spm_dvfs_req = 0,
+ /* [9] */
+ .reg_spm_sw_mailbox_req = 0,
+ /* [10] */
+ .reg_spm_sspm_mailbox_req = 0,
+ /* [11] */
+ .reg_spm_adsp_mailbox_req = 0,
+ /* [12] */
+ .reg_spm_scp_mailbox_req = 0,
+
+
+ /* SPM_SRC_MASK */
+ /* [0] */
+ .reg_sspm_srcclkena_0_mask_b = 1,
+ /* [1] */
+ .reg_sspm_infra_req_0_mask_b = 1,
+ /* [2] */
+ .reg_sspm_apsrc_req_0_mask_b = 1,
+ /* [3] */
+ .reg_sspm_vrf18_req_0_mask_b = 1,
+ /* [4] */
+ .reg_sspm_ddr_en_0_mask_b = 1,
+ /* [5] */
+ .reg_scp_srcclkena_mask_b = 1,
+ /* [6] */
+ .reg_scp_infra_req_mask_b = 1,
+ /* [7] */
+ .reg_scp_apsrc_req_mask_b = 1,
+ /* [8] */
+ .reg_scp_vrf18_req_mask_b = 1,
+ /* [9] */
+ .reg_scp_ddr_en_mask_b = 1,
+ /* [10] */
+ .reg_audio_dsp_srcclkena_mask_b = 1,
+ /* [11] */
+ .reg_audio_dsp_infra_req_mask_b = 1,
+ /* [12] */
+ .reg_audio_dsp_apsrc_req_mask_b = 1,
+ /* [13] */
+ .reg_audio_dsp_vrf18_req_mask_b = 1,
+ /* [14] */
+ .reg_audio_dsp_ddr_en_mask_b = 1,
+ /* [15] */
+ .reg_apu_srcclkena_mask_b = 1,
+ /* [16] */
+ .reg_apu_infra_req_mask_b = 1,
+ /* [17] */
+ .reg_apu_apsrc_req_mask_b = 1,
+ /* [18] */
+ .reg_apu_vrf18_req_mask_b = 1,
+ /* [19] */
+ .reg_apu_ddr_en_mask_b = 1,
+ /* [20] */
+ .reg_cpueb_srcclkena_mask_b = 1,
+ /* [21] */
+ .reg_cpueb_infra_req_mask_b = 1,
+ /* [22] */
+ .reg_cpueb_apsrc_req_mask_b = 1,
+ /* [23] */
+ .reg_cpueb_vrf18_req_mask_b = 1,
+ /* [24] */
+ .reg_cpueb_ddr_en_mask_b = 1,
+ /* [25] */
+ .reg_bak_psri_srcclkena_mask_b = 0,
+ /* [26] */
+ .reg_bak_psri_infra_req_mask_b = 0,
+ /* [27] */
+ .reg_bak_psri_apsrc_req_mask_b = 0,
+ /* [28] */
+ .reg_bak_psri_vrf18_req_mask_b = 0,
+ /* [29] */
+ .reg_bak_psri_ddr_en_mask_b = 0,
+
+ /* SPM_SRC2_MASK */
+ /* [0] */
+ .reg_msdc0_srcclkena_mask_b = 1,
+ /* [1] */
+ .reg_msdc0_infra_req_mask_b = 1,
+ /* [2] */
+ .reg_msdc0_apsrc_req_mask_b = 1,
+ /* [3] */
+ .reg_msdc0_vrf18_req_mask_b = 1,
+ /* [4] */
+ .reg_msdc0_ddr_en_mask_b = 1,
+ /* [5] */
+ .reg_msdc1_srcclkena_mask_b = 1,
+ /* [6] */
+ .reg_msdc1_infra_req_mask_b = 1,
+ /* [7] */
+ .reg_msdc1_apsrc_req_mask_b = 1,
+ /* [8] */
+ .reg_msdc1_vrf18_req_mask_b = 1,
+ /* [9] */
+ .reg_msdc1_ddr_en_mask_b = 1,
+ /* [10] */
+ .reg_msdc2_srcclkena_mask_b = 1,
+ /* [11] */
+ .reg_msdc2_infra_req_mask_b = 1,
+ /* [12] */
+ .reg_msdc2_apsrc_req_mask_b = 1,
+ /* [13] */
+ .reg_msdc2_vrf18_req_mask_b = 1,
+ /* [14] */
+ .reg_msdc2_ddr_en_mask_b = 1,
+ /* [15] */
+ .reg_ufs_srcclkena_mask_b = 1,
+ /* [16] */
+ .reg_ufs_infra_req_mask_b = 1,
+ /* [17] */
+ .reg_ufs_apsrc_req_mask_b = 1,
+ /* [18] */
+ .reg_ufs_vrf18_req_mask_b = 1,
+ /* [19] */
+ .reg_ufs_ddr_en_mask_b = 1,
+ /* [20] */
+ .reg_usb_srcclkena_mask_b = 1,
+ /* [21] */
+ .reg_usb_infra_req_mask_b = 1,
+ /* [22] */
+ .reg_usb_apsrc_req_mask_b = 1,
+ /* [23] */
+ .reg_usb_vrf18_req_mask_b = 1,
+ /* [24] */
+ .reg_usb_ddr_en_mask_b = 1,
+ /* [25] */
+ .reg_pextp_p0_srcclkena_mask_b = 1,
+ /* [26] */
+ .reg_pextp_p0_infra_req_mask_b = 1,
+ /* [27] */
+ .reg_pextp_p0_apsrc_req_mask_b = 1,
+ /* [28] */
+ .reg_pextp_p0_vrf18_req_mask_b = 1,
+ /* [29] */
+ .reg_pextp_p0_ddr_en_mask_b = 1,
+
+ /* SPM_SRC3_MASK */
+ /* [0] */
+ .reg_pextp_p1_srcclkena_mask_b = 1,
+ /* [1] */
+ .reg_pextp_p1_infra_req_mask_b = 1,
+ /* [2] */
+ .reg_pextp_p1_apsrc_req_mask_b = 1,
+ /* [3] */
+ .reg_pextp_p1_vrf18_req_mask_b = 1,
+ /* [4] */
+ .reg_pextp_p1_ddr_en_mask_b = 1,
+ /* [5] */
+ .reg_gce0_infra_req_mask_b = 1,
+ /* [6] */
+ .reg_gce0_apsrc_req_mask_b = 1,
+ /* [7] */
+ .reg_gce0_vrf18_req_mask_b = 1,
+ /* [8] */
+ .reg_gce0_ddr_en_mask_b = 1,
+ /* [9] */
+ .reg_gce1_infra_req_mask_b = 1,
+ /* [10] */
+ .reg_gce1_apsrc_req_mask_b = 1,
+ /* [11] */
+ .reg_gce1_vrf18_req_mask_b = 1,
+ /* [12] */
+ .reg_gce1_ddr_en_mask_b = 1,
+ /* [13] */
+ .reg_spm_srcclkena_reserved_mask_b = 1,
+ /* [14] */
+ .reg_spm_infra_req_reserved_mask_b = 1,
+ /* [15] */
+ .reg_spm_apsrc_req_reserved_mask_b = 1,
+ /* [16] */
+ .reg_spm_vrf18_req_reserved_mask_b = 1,
+ /* [17] */
+ .reg_spm_ddr_en_reserved_mask_b = 1,
+ /* [18] */
+ .reg_disp0_apsrc_req_mask_b = 1,
+ /* [19] */
+ .reg_disp0_ddr_en_mask_b = 1,
+ /* [20] */
+ .reg_disp1_apsrc_req_mask_b = 1,
+ /* [21] */
+ .reg_disp1_ddr_en_mask_b = 1,
+ /* [22] */
+ .reg_disp2_apsrc_req_mask_b = 1,
+ /* [23] */
+ .reg_disp2_ddr_en_mask_b = 1,
+ /* [24] */
+ .reg_disp3_apsrc_req_mask_b = 1,
+ /* [25] */
+ .reg_disp3_ddr_en_mask_b = 1,
+ /* [26] */
+ .reg_infrasys_apsrc_req_mask_b = 0,
+ /* [27] */
+ .reg_infrasys_ddr_en_mask_b = 1,
+
+ /* [28] */
+ .reg_cg_check_srcclkena_mask_b = 1,
+ /* [29] */
+ .reg_cg_check_apsrc_req_mask_b = 1,
+ /* [30] */
+ .reg_cg_check_vrf18_req_mask_b = 1,
+ /* [31] */
+ .reg_cg_check_ddr_en_mask_b = 1,
+
+ /* SPM_SRC4_MASK */
+ /* [8:0] */
+ .reg_mcusys_merge_apsrc_req_mask_b = 0x17,
+ /* [17:9] */
+ .reg_mcusys_merge_ddr_en_mask_b = 0x17,
+ /* [19:18] */
+ .reg_dramc_md32_infra_req_mask_b = 0,
+ /* [21:20] */
+ .reg_dramc_md32_vrf18_req_mask_b = 0,
+ /* [23:22] */
+ .reg_dramc_md32_ddr_en_mask_b = 0,
+ /* [24] */
+ .reg_dvfsrc_event_trigger_mask_b = 1,
+
+ /* SPM_WAKEUP_EVENT_MASK2 */
+ /* [3:0] */
+ .reg_sc_sw2spm_wakeup_mask_b = 0,
+ /* [4] */
+ .reg_sc_adsp2spm_wakeup_mask_b = 0,
+ /* [8:5] */
+ .reg_sc_sspm2spm_wakeup_mask_b = 0,
+ /* [9] */
+ .reg_sc_scp2spm_wakeup_mask_b = 0,
+ /* [10] */
+ .reg_csyspwrup_ack_mask = 0,
+ /* [11] */
+ .reg_csyspwrup_req_mask = 1,
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ /* [31:0] */
+ .reg_wakeup_event_mask = 0xC1282203,
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ /* [31:0] */
+ .reg_ext_wakeup_event_mask = 0xFFFFFFFF,
+};
+
+struct spm_lp_scen idle_spm_lp = {
+ .pwrctrl = &idle_spm_pwr,
+};
+
+int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand,
+ spm_idle_conduct fn)
+{
+ unsigned int src_req = 0;
+
+ if (fn != NULL) {
+ fn(&idle_spm_lp, &src_req);
+ }
+
+ return spm_conservation(state_id, ext_opand, &idle_spm_lp, src_req);
+}
+void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
+ struct wake_status **status)
+{
+ spm_conservation_finish(state_id, ext_opand, &idle_spm_lp, status);
+}
+
+void mt_spm_idle_generic_init(void)
+{
+ spm_conservation_pwrctrl_init(idle_spm_lp.pwrctrl);
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_idle.h b/plat/mediatek/mt8195/drivers/spm/mt_spm_idle.h
new file mode 100644
index 0000000..7f6fb0c
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_idle.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_IDLE_H
+#define MT_SPM_IDLE_H
+
+typedef void (*spm_idle_conduct)(struct spm_lp_scen *spm_lp,
+ unsigned int *resource_req);
+int mt_spm_idle_generic_enter(int state_id, unsigned int ext_opand,
+ spm_idle_conduct fn);
+void mt_spm_idle_generic_resume(int state_id, unsigned int ext_opand,
+ struct wake_status **status);
+void mt_spm_idle_generic_init(void);
+#endif /* MT_SPM_IDLE_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_internal.c b/plat/mediatek/mt8195/drivers/spm/mt_spm_internal.c
new file mode 100644
index 0000000..2f460e6
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_internal.c
@@ -0,0 +1,543 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+
+#include <assert.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include <mt_spm.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_pmic_wrap.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <platform_def.h>
+#include <plat_pm.h>
+
+/**************************************
+ * Define and Declare
+ **************************************/
+#define ROOT_CORE_ADDR_OFFSET 0x20000000
+#define SPM_WAKEUP_EVENT_MASK_CLEAN_MASK 0xefffffff
+#define SPM_INIT_DONE_US 20
+
+static unsigned int mt_spm_bblpm_cnt;
+
+const char *wakeup_src_str[32] = {
+ [0] = "R12_PCM_TIMER",
+ [1] = "R12_RESERVED_DEBUG_B",
+ [2] = "R12_KP_IRQ_B",
+ [3] = "R12_APWDT_EVENT_B",
+ [4] = "R12_APXGPT1_EVENT_B",
+ [5] = "R12_MSDC_WAKEUP_B",
+ [6] = "R12_EINT_EVENT_B",
+ [7] = "R12_IRRX_WAKEUP_B",
+ [8] = "R12_SBD_INTR_WAKEUP_B",
+ [9] = "R12_RESERVE0",
+ [10] = "R12_SC_SSPM2SPM_WAKEUP_B",
+ [11] = "R12_SC_SCP2SPM_WAKEUP_B",
+ [12] = "R12_SC_ADSP2SPM_WAKEUP_B",
+ [13] = "R12_WDT_WAKEUP_B",
+ [14] = "R12_USB_U2_B",
+ [15] = "R12_USB_TOP_B",
+ [16] = "R12_SYS_TIMER_EVENT_B",
+ [17] = "R12_EINT_EVENT_SECURE_B",
+ [18] = "R12_ECE_INT_HDMI_B",
+ [19] = "R12_RESERVE1",
+ [20] = "R12_AFE_IRQ_MCU_B",
+ [21] = "R12_THERM_CTRL_EVENT_B",
+ [22] = "R12_SCP_CIRQ_IRQ_B",
+ [23] = "R12_NNA2INFRA_WAKEUP_B",
+ [24] = "R12_CSYSPWREQ_B",
+ [25] = "R12_RESERVE2",
+ [26] = "R12_PCIE_WAKEUPEVENT_B",
+ [27] = "R12_SEJ_EVENT_B",
+ [28] = "R12_SPM_CPU_WAKEUPEVENT_B",
+ [29] = "R12_APUSYS",
+ [30] = "R12_RESERVE3",
+ [31] = "R12_RESERVE4",
+};
+
+/**************************************
+ * Function and API
+ **************************************/
+
+wake_reason_t __spm_output_wake_reason(int state_id,
+ const struct wake_status *wakesta)
+{
+ uint32_t i, bk_vtcxo_dur, spm_26m_off_pct = 0U;
+ wake_reason_t wr = WR_UNKNOWN;
+
+ if (wakesta == NULL) {
+ return WR_UNKNOWN;
+ }
+
+ if (wakesta->abort != 0U) {
+ ERROR("spmfw flow is aborted: 0x%x, timer_out = %u\n",
+ wakesta->abort, wakesta->timer_out);
+ } else {
+ for (i = 0U; i < 32U; i++) {
+ if ((wakesta->r12 & (1U << i)) != 0U) {
+ INFO("wake up by %s, timer_out = %u\n",
+ wakeup_src_str[i], wakesta->timer_out);
+ wr = WR_WAKE_SRC;
+ break;
+ }
+ }
+ }
+
+ INFO("r12 = 0x%x, r12_ext = 0x%x, r13 = 0x%x, debug_flag = 0x%x 0x%x\n",
+ wakesta->r12, wakesta->r12_ext, wakesta->r13, wakesta->debug_flag,
+ wakesta->debug_flag1);
+ INFO("raw_sta = 0x%x 0x%x 0x%x, idle_sta = 0x%x, cg_check_sta = 0x%x\n",
+ wakesta->raw_sta, wakesta->md32pcm_wakeup_sta,
+ wakesta->md32pcm_event_sta, wakesta->idle_sta,
+ wakesta->cg_check_sta);
+ INFO("req_sta = 0x%x 0x%x 0x%x 0x%x 0x%x, isr = 0x%x\n",
+ wakesta->req_sta0, wakesta->req_sta1, wakesta->req_sta2,
+ wakesta->req_sta3, wakesta->req_sta4, wakesta->isr);
+ INFO("rt_req_sta0 = 0x%x, rt_req_sta1 = 0x%x, rt_req_sta2 = 0x%x\n",
+ wakesta->rt_req_sta0, wakesta->rt_req_sta1, wakesta->rt_req_sta2);
+ INFO("rt_req_sta3 = 0x%x, dram_sw_con_3 = 0x%x, raw_ext_sta = 0x%x\n",
+ wakesta->rt_req_sta3, wakesta->rt_req_sta4, wakesta->raw_ext_sta);
+ INFO("wake_misc = 0x%x, pcm_flag = 0x%x 0x%x 0x%x 0x%x, req = 0x%x\n",
+ wakesta->wake_misc, wakesta->sw_flag0, wakesta->sw_flag1,
+ wakesta->b_sw_flag0, wakesta->b_sw_flag1, wakesta->src_req);
+ INFO("clk_settle = 0x%x, wlk_cntcv_l = 0x%x, wlk_cntcv_h = 0x%x\n",
+ wakesta->clk_settle, mmio_read_32(SYS_TIMER_VALUE_L),
+ mmio_read_32(SYS_TIMER_VALUE_H));
+
+ if (wakesta->timer_out != 0U) {
+ bk_vtcxo_dur = mmio_read_32(SPM_BK_VTCXO_DUR);
+ spm_26m_off_pct = (100 * bk_vtcxo_dur) / wakesta->timer_out;
+ INFO("spm_26m_off_pct = %u\n", spm_26m_off_pct);
+ }
+
+ return wr;
+}
+
+void __spm_set_cpu_status(unsigned int cpu)
+{
+ uint32_t root_core_addr;
+
+ if (cpu < 8U) {
+ mmio_write_32(ROOT_CPUTOP_ADDR, (1U << cpu));
+ root_core_addr = SPM_CPU0_PWR_CON + (cpu * 0x4);
+ root_core_addr += ROOT_CORE_ADDR_OFFSET;
+ mmio_write_32(ROOT_CORE_ADDR, root_core_addr);
+ /* Notify MCUPM that preferred cpu wakeup */
+ mmio_write_32(MCUPM_MBOX_WAKEUP_CPU, cpu);
+ } else {
+ ERROR("%s: error cpu number %d\n", __func__, cpu);
+ }
+}
+
+void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
+ unsigned int resource_usage)
+{
+ uint8_t apsrc_req = ((resource_usage & MT_SPM_DRAM_S0) != 0U) ?
+ 1 : pwrctrl->reg_spm_apsrc_req;
+ uint8_t ddr_en_req = ((resource_usage & MT_SPM_DRAM_S1) != 0U) ?
+ 1 : pwrctrl->reg_spm_ddr_en_req;
+ uint8_t vrf18_req = ((resource_usage & MT_SPM_SYSPLL) != 0U) ?
+ 1 : pwrctrl->reg_spm_vrf18_req;
+ uint8_t infra_req = ((resource_usage & MT_SPM_INFRA) != 0U) ?
+ 1 : pwrctrl->reg_spm_infra_req;
+ uint8_t f26m_req = ((resource_usage &
+ (MT_SPM_26M | MT_SPM_XO_FPM)) != 0U) ?
+ 1 : pwrctrl->reg_spm_f26m_req;
+
+ mmio_write_32(SPM_SRC_REQ,
+ ((apsrc_req & 0x1) << 0) |
+ ((f26m_req & 0x1) << 1) |
+ ((infra_req & 0x1) << 3) |
+ ((vrf18_req & 0x1) << 4) |
+ ((ddr_en_req & 0x1) << 7) |
+ ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
+ ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
+ ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
+ ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
+ ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
+}
+
+void __spm_set_power_control(const struct pwr_ctrl *pwrctrl)
+{
+ /* Auto-gen Start */
+
+ /* SPM_AP_STANDBY_CON */
+ mmio_write_32(SPM_AP_STANDBY_CON,
+ ((pwrctrl->reg_wfi_op & 0x1) << 0) |
+ ((pwrctrl->reg_wfi_type & 0x1) << 1) |
+ ((pwrctrl->reg_mp0_cputop_idle_mask & 0x1) << 2) |
+ ((pwrctrl->reg_mp1_cputop_idle_mask & 0x1) << 3) |
+ ((pwrctrl->reg_mcusys_idle_mask & 0x1) << 4) |
+ ((pwrctrl->reg_md_apsrc_1_sel & 0x1) << 25) |
+ ((pwrctrl->reg_md_apsrc_0_sel & 0x1) << 26) |
+ ((pwrctrl->reg_conn_apsrc_sel & 0x1) << 29));
+
+ /* SPM_SRC_REQ */
+ mmio_write_32(SPM_SRC_REQ,
+ ((pwrctrl->reg_spm_apsrc_req & 0x1) << 0) |
+ ((pwrctrl->reg_spm_f26m_req & 0x1) << 1) |
+ ((pwrctrl->reg_spm_infra_req & 0x1) << 3) |
+ ((pwrctrl->reg_spm_vrf18_req & 0x1) << 4) |
+ ((pwrctrl->reg_spm_ddr_en_req & 0x1) << 7) |
+ ((pwrctrl->reg_spm_dvfs_req & 0x1) << 8) |
+ ((pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 9) |
+ ((pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 10) |
+ ((pwrctrl->reg_spm_adsp_mailbox_req & 0x1) << 11) |
+ ((pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 12));
+
+ /* SPM_SRC_MASK */
+ mmio_write_32(SPM_SRC_MASK,
+ ((pwrctrl->reg_sspm_srcclkena_0_mask_b & 0x1) << 0) |
+ ((pwrctrl->reg_sspm_infra_req_0_mask_b & 0x1) << 1) |
+ ((pwrctrl->reg_sspm_apsrc_req_0_mask_b & 0x1) << 2) |
+ ((pwrctrl->reg_sspm_vrf18_req_0_mask_b & 0x1) << 3) |
+ ((pwrctrl->reg_sspm_ddr_en_0_mask_b & 0x1) << 4) |
+ ((pwrctrl->reg_scp_srcclkena_mask_b & 0x1) << 5) |
+ ((pwrctrl->reg_scp_infra_req_mask_b & 0x1) << 6) |
+ ((pwrctrl->reg_scp_apsrc_req_mask_b & 0x1) << 7) |
+ ((pwrctrl->reg_scp_vrf18_req_mask_b & 0x1) << 8) |
+ ((pwrctrl->reg_scp_ddr_en_mask_b & 0x1) << 9) |
+ ((pwrctrl->reg_audio_dsp_srcclkena_mask_b & 0x1) << 10) |
+ ((pwrctrl->reg_audio_dsp_infra_req_mask_b & 0x1) << 11) |
+ ((pwrctrl->reg_audio_dsp_apsrc_req_mask_b & 0x1) << 12) |
+ ((pwrctrl->reg_audio_dsp_vrf18_req_mask_b & 0x1) << 13) |
+ ((pwrctrl->reg_audio_dsp_ddr_en_mask_b & 0x1) << 14) |
+ ((pwrctrl->reg_apu_srcclkena_mask_b & 0x1) << 15) |
+ ((pwrctrl->reg_apu_infra_req_mask_b & 0x1) << 16) |
+ ((pwrctrl->reg_apu_apsrc_req_mask_b & 0x1) << 17) |
+ ((pwrctrl->reg_apu_vrf18_req_mask_b & 0x1) << 18) |
+ ((pwrctrl->reg_apu_ddr_en_mask_b & 0x1) << 19) |
+ ((pwrctrl->reg_cpueb_srcclkena_mask_b & 0x1) << 20) |
+ ((pwrctrl->reg_cpueb_infra_req_mask_b & 0x1) << 21) |
+ ((pwrctrl->reg_cpueb_apsrc_req_mask_b & 0x1) << 22) |
+ ((pwrctrl->reg_cpueb_vrf18_req_mask_b & 0x1) << 23) |
+ ((pwrctrl->reg_cpueb_ddr_en_mask_b & 0x1) << 24) |
+ ((pwrctrl->reg_bak_psri_srcclkena_mask_b & 0x1) << 25) |
+ ((pwrctrl->reg_bak_psri_infra_req_mask_b & 0x1) << 26) |
+ ((pwrctrl->reg_bak_psri_apsrc_req_mask_b & 0x1) << 27) |
+ ((pwrctrl->reg_bak_psri_vrf18_req_mask_b & 0x1) << 28) |
+ ((pwrctrl->reg_bak_psri_ddr_en_mask_b & 0x1) << 29));
+
+ /* SPM_SRC2_MASK */
+ mmio_write_32(SPM_SRC2_MASK,
+ ((pwrctrl->reg_msdc0_srcclkena_mask_b & 0x1) << 0) |
+ ((pwrctrl->reg_msdc0_infra_req_mask_b & 0x1) << 1) |
+ ((pwrctrl->reg_msdc0_apsrc_req_mask_b & 0x1) << 2) |
+ ((pwrctrl->reg_msdc0_vrf18_req_mask_b & 0x1) << 3) |
+ ((pwrctrl->reg_msdc0_ddr_en_mask_b & 0x1) << 4) |
+ ((pwrctrl->reg_msdc1_srcclkena_mask_b & 0x1) << 5) |
+ ((pwrctrl->reg_msdc1_infra_req_mask_b & 0x1) << 6) |
+ ((pwrctrl->reg_msdc1_apsrc_req_mask_b & 0x1) << 7) |
+ ((pwrctrl->reg_msdc1_vrf18_req_mask_b & 0x1) << 8) |
+ ((pwrctrl->reg_msdc1_ddr_en_mask_b & 0x1) << 9) |
+ ((pwrctrl->reg_msdc2_srcclkena_mask_b & 0x1) << 10) |
+ ((pwrctrl->reg_msdc2_infra_req_mask_b & 0x1) << 11) |
+ ((pwrctrl->reg_msdc2_apsrc_req_mask_b & 0x1) << 12) |
+ ((pwrctrl->reg_msdc2_vrf18_req_mask_b & 0x1) << 13) |
+ ((pwrctrl->reg_msdc2_ddr_en_mask_b & 0x1) << 14) |
+ ((pwrctrl->reg_ufs_srcclkena_mask_b & 0x1) << 15) |
+ ((pwrctrl->reg_ufs_infra_req_mask_b & 0x1) << 16) |
+ ((pwrctrl->reg_ufs_apsrc_req_mask_b & 0x1) << 17) |
+ ((pwrctrl->reg_ufs_vrf18_req_mask_b & 0x1) << 18) |
+ ((pwrctrl->reg_ufs_ddr_en_mask_b & 0x1) << 19) |
+ ((pwrctrl->reg_usb_srcclkena_mask_b & 0x1) << 20) |
+ ((pwrctrl->reg_usb_infra_req_mask_b & 0x1) << 21) |
+ ((pwrctrl->reg_usb_apsrc_req_mask_b & 0x1) << 22) |
+ ((pwrctrl->reg_usb_vrf18_req_mask_b & 0x1) << 23) |
+ ((pwrctrl->reg_usb_ddr_en_mask_b & 0x1) << 24) |
+ ((pwrctrl->reg_pextp_p0_srcclkena_mask_b & 0x1) << 25) |
+ ((pwrctrl->reg_pextp_p0_infra_req_mask_b & 0x1) << 26) |
+ ((pwrctrl->reg_pextp_p0_apsrc_req_mask_b & 0x1) << 27) |
+ ((pwrctrl->reg_pextp_p0_vrf18_req_mask_b & 0x1) << 28) |
+ ((pwrctrl->reg_pextp_p0_ddr_en_mask_b & 0x1) << 29));
+
+ /* SPM_SRC3_MASK */
+ mmio_write_32(SPM_SRC3_MASK,
+ ((pwrctrl->reg_pextp_p1_srcclkena_mask_b & 0x1) << 0) |
+ ((pwrctrl->reg_pextp_p1_infra_req_mask_b & 0x1) << 1) |
+ ((pwrctrl->reg_pextp_p1_apsrc_req_mask_b & 0x1) << 2) |
+ ((pwrctrl->reg_pextp_p1_vrf18_req_mask_b & 0x1) << 3) |
+ ((pwrctrl->reg_pextp_p1_ddr_en_mask_b & 0x1) << 4) |
+ ((pwrctrl->reg_gce0_infra_req_mask_b & 0x1) << 5) |
+ ((pwrctrl->reg_gce0_apsrc_req_mask_b & 0x1) << 6) |
+ ((pwrctrl->reg_gce0_vrf18_req_mask_b & 0x1) << 7) |
+ ((pwrctrl->reg_gce0_ddr_en_mask_b & 0x1) << 8) |
+ ((pwrctrl->reg_gce1_infra_req_mask_b & 0x1) << 9) |
+ ((pwrctrl->reg_gce1_apsrc_req_mask_b & 0x1) << 10) |
+ ((pwrctrl->reg_gce1_vrf18_req_mask_b & 0x1) << 11) |
+ ((pwrctrl->reg_gce1_ddr_en_mask_b & 0x1) << 12) |
+ ((pwrctrl->reg_spm_srcclkena_reserved_mask_b & 0x1) << 13) |
+ ((pwrctrl->reg_spm_infra_req_reserved_mask_b & 0x1) << 14) |
+ ((pwrctrl->reg_spm_apsrc_req_reserved_mask_b & 0x1) << 15) |
+ ((pwrctrl->reg_spm_vrf18_req_reserved_mask_b & 0x1) << 16) |
+ ((pwrctrl->reg_spm_ddr_en_reserved_mask_b & 0x1) << 17) |
+ ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 18) |
+ ((pwrctrl->reg_disp0_ddr_en_mask_b & 0x1) << 19) |
+ ((pwrctrl->reg_disp1_apsrc_req_mask_b & 0x1) << 20) |
+ ((pwrctrl->reg_disp1_ddr_en_mask_b & 0x1) << 21) |
+ ((pwrctrl->reg_disp2_apsrc_req_mask_b & 0x1) << 22) |
+ ((pwrctrl->reg_disp2_ddr_en_mask_b & 0x1) << 23) |
+ ((pwrctrl->reg_disp3_apsrc_req_mask_b & 0x1) << 24) |
+ ((pwrctrl->reg_disp3_ddr_en_mask_b & 0x1) << 25) |
+ ((pwrctrl->reg_infrasys_apsrc_req_mask_b & 0x1) << 26) |
+ ((pwrctrl->reg_infrasys_ddr_en_mask_b & 0x1) << 27));
+
+ /* Mask MCUSYS request since SOC HW would check it */
+ mmio_write_32(SPM_SRC4_MASK, 0x1fc0000);
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ mmio_write_32(SPM_WAKEUP_EVENT_MASK,
+ ((pwrctrl->reg_wakeup_event_mask & 0xffffffff) << 0));
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ mmio_write_32(SPM_WAKEUP_EVENT_EXT_MASK,
+ ((pwrctrl->reg_ext_wakeup_event_mask & 0xffffffff) << 0));
+
+ /* Auto-gen End */
+}
+
+void __spm_disable_pcm_timer(void)
+{
+ mmio_clrsetbits_32(PCM_CON1, RG_PCM_TIMER_EN_LSB, SPM_REGWR_CFG_KEY);
+}
+
+void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
+{
+ uint32_t val, mask;
+
+ /* toggle event counter clear */
+ mmio_setbits_32(PCM_CON1,
+ SPM_REGWR_CFG_KEY | SPM_EVENT_COUNTER_CLR_LSB);
+
+ /* toggle for reset SYS TIMER start point */
+ mmio_setbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
+
+ if (pwrctrl->timer_val_cust == 0U) {
+ val = pwrctrl->timer_val;
+ } else {
+ val = pwrctrl->timer_val_cust;
+ }
+
+ mmio_write_32(PCM_TIMER_VAL, val);
+ mmio_setbits_32(PCM_CON1, SPM_REGWR_CFG_KEY | RG_PCM_TIMER_EN_LSB);
+
+ /* unmask AP wakeup source */
+ if (pwrctrl->wake_src_cust == 0U) {
+ mask = pwrctrl->wake_src;
+ } else {
+ mask = pwrctrl->wake_src_cust;
+ }
+
+ mmio_write_32(SPM_WAKEUP_EVENT_MASK, ~mask);
+
+ /* unmask SPM ISR (keep TWAM setting) */
+ mmio_setbits_32(SPM_IRQ_MASK, ISRM_RET_IRQ_AUX);
+
+ /* toggle event counter clear */
+ mmio_clrsetbits_32(PCM_CON1, SPM_EVENT_COUNTER_CLR_LSB,
+ SPM_REGWR_CFG_KEY);
+ /* toggle for reset SYS TIMER start point */
+ mmio_clrbits_32(SYS_TIMER_CON, SYS_TIMER_START_EN_LSB);
+}
+
+void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl)
+{
+ /* set PCM flags and data */
+ if (pwrctrl->pcm_flags_cust_clr != 0U) {
+ pwrctrl->pcm_flags &= ~pwrctrl->pcm_flags_cust_clr;
+ }
+
+ if (pwrctrl->pcm_flags_cust_set != 0U) {
+ pwrctrl->pcm_flags |= pwrctrl->pcm_flags_cust_set;
+ }
+
+ if (pwrctrl->pcm_flags1_cust_clr != 0U) {
+ pwrctrl->pcm_flags1 &= ~pwrctrl->pcm_flags1_cust_clr;
+ }
+
+ if (pwrctrl->pcm_flags1_cust_set != 0U) {
+ pwrctrl->pcm_flags1 |= pwrctrl->pcm_flags1_cust_set;
+ }
+
+ mmio_write_32(SPM_SW_FLAG_0, pwrctrl->pcm_flags);
+ mmio_write_32(SPM_SW_FLAG_1, pwrctrl->pcm_flags1);
+ mmio_write_32(SPM_SW_RSV_7, pwrctrl->pcm_flags);
+ mmio_write_32(SPM_SW_RSV_8, pwrctrl->pcm_flags1);
+}
+
+void __spm_get_wakeup_status(struct wake_status *wakesta,
+ unsigned int ext_status)
+{
+ wakesta->tr.comm.r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
+ wakesta->tr.comm.timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
+ wakesta->tr.comm.r13 = mmio_read_32(PCM_REG13_DATA);
+ wakesta->tr.comm.req_sta0 = mmio_read_32(SRC_REQ_STA_0);
+ wakesta->tr.comm.req_sta1 = mmio_read_32(SRC_REQ_STA_1);
+ wakesta->tr.comm.req_sta2 = mmio_read_32(SRC_REQ_STA_2);
+ wakesta->tr.comm.req_sta3 = mmio_read_32(SRC_REQ_STA_3);
+ wakesta->tr.comm.req_sta4 = mmio_read_32(SRC_REQ_STA_4);
+ wakesta->tr.comm.debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
+ wakesta->tr.comm.debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
+
+ if ((ext_status & SPM_INTERNAL_STATUS_HW_S1) != 0U) {
+ wakesta->tr.comm.debug_flag |= (SPM_DBG_DEBUG_IDX_DDREN_WAKE |
+ SPM_DBG_DEBUG_IDX_DDREN_SLEEP);
+ mmio_write_32(PCM_WDT_LATCH_SPARE_0,
+ wakesta->tr.comm.debug_flag);
+ }
+
+ wakesta->tr.comm.b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
+ wakesta->tr.comm.b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
+
+ /* record below spm info for debug */
+ wakesta->r12 = mmio_read_32(SPM_BK_WAKE_EVENT);
+ wakesta->r12_ext = mmio_read_32(SPM_WAKEUP_STA);
+ wakesta->raw_sta = mmio_read_32(SPM_WAKEUP_STA);
+ wakesta->raw_ext_sta = mmio_read_32(SPM_WAKEUP_EXT_STA);
+ wakesta->md32pcm_wakeup_sta = mmio_read_32(MD32PCM_WAKEUP_STA);
+ wakesta->md32pcm_event_sta = mmio_read_32(MD32PCM_EVENT_STA);
+ wakesta->src_req = mmio_read_32(SPM_SRC_REQ);
+
+ /* backup of SPM_WAKEUP_MISC */
+ wakesta->wake_misc = mmio_read_32(SPM_BK_WAKE_MISC);
+
+ /* get sleep time, backup of PCM_TIMER_OUT */
+ wakesta->timer_out = mmio_read_32(SPM_BK_PCM_TIMER);
+
+ /* get other SYS and co-clock status */
+ wakesta->r13 = mmio_read_32(PCM_REG13_DATA);
+ wakesta->idle_sta = mmio_read_32(SUBSYS_IDLE_STA);
+ wakesta->req_sta0 = mmio_read_32(SRC_REQ_STA_0);
+ wakesta->req_sta1 = mmio_read_32(SRC_REQ_STA_1);
+ wakesta->req_sta2 = mmio_read_32(SRC_REQ_STA_2);
+ wakesta->req_sta3 = mmio_read_32(SRC_REQ_STA_3);
+ wakesta->req_sta4 = mmio_read_32(SRC_REQ_STA_4);
+
+ /* get HW CG check status */
+ wakesta->cg_check_sta = mmio_read_32(SPM_CG_CHECK_STA);
+
+ /* get debug flag for PCM execution check */
+ wakesta->debug_flag = mmio_read_32(PCM_WDT_LATCH_SPARE_0);
+ wakesta->debug_flag1 = mmio_read_32(PCM_WDT_LATCH_SPARE_1);
+
+ /* get backup SW flag status */
+ wakesta->b_sw_flag0 = mmio_read_32(SPM_SW_RSV_7);
+ wakesta->b_sw_flag1 = mmio_read_32(SPM_SW_RSV_8);
+
+ wakesta->rt_req_sta0 = mmio_read_32(SPM_SW_RSV_2);
+ wakesta->rt_req_sta1 = mmio_read_32(SPM_SW_RSV_3);
+ wakesta->rt_req_sta2 = mmio_read_32(SPM_SW_RSV_4);
+ wakesta->rt_req_sta3 = mmio_read_32(SPM_SW_RSV_5);
+ wakesta->rt_req_sta4 = mmio_read_32(SPM_SW_RSV_6);
+
+ /* get ISR status */
+ wakesta->isr = mmio_read_32(SPM_IRQ_STA);
+
+ /* get SW flag status */
+ wakesta->sw_flag0 = mmio_read_32(SPM_SW_FLAG_0);
+ wakesta->sw_flag1 = mmio_read_32(SPM_SW_FLAG_1);
+
+ /* get CLK SETTLE */
+ wakesta->clk_settle = mmio_read_32(SPM_CLK_SETTLE);
+
+ /* check abort */
+ wakesta->abort = (wakesta->debug_flag & DEBUG_ABORT_MASK) |
+ (wakesta->debug_flag1 & DEBUG_ABORT_MASK_1);
+}
+
+void __spm_clean_after_wakeup(void)
+{
+ mmio_write_32(SPM_BK_WAKE_EVENT,
+ mmio_read_32(SPM_WAKEUP_STA) |
+ mmio_read_32(SPM_BK_WAKE_EVENT));
+ mmio_write_32(SPM_CPU_WAKEUP_EVENT, 0);
+
+ /*
+ * clean wakeup event raw status (for edge trigger event)
+ * bit[28] for cpu wake up event
+ */
+ mmio_write_32(SPM_WAKEUP_EVENT_MASK, SPM_WAKEUP_EVENT_MASK_CLEAN_MASK);
+
+ /* clean ISR status (except TWAM) */
+ mmio_setbits_32(SPM_IRQ_MASK, ISRM_ALL_EXC_TWAM);
+ mmio_write_32(SPM_IRQ_STA, ISRC_ALL_EXC_TWAM);
+ mmio_write_32(SPM_SWINT_CLR, PCM_SW_INT_ALL);
+}
+
+void __spm_set_pcm_wdt(int en)
+{
+ mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_EN_LSB,
+ SPM_REGWR_CFG_KEY);
+
+ if (en == 1) {
+ mmio_clrsetbits_32(PCM_CON1, RG_PCM_WDT_WAKE_LSB,
+ SPM_REGWR_CFG_KEY);
+
+ if (mmio_read_32(PCM_TIMER_VAL) > PCM_TIMER_MAX) {
+ mmio_write_32(PCM_TIMER_VAL, PCM_TIMER_MAX);
+ }
+
+ mmio_write_32(PCM_WDT_VAL,
+ mmio_read_32(PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
+ mmio_setbits_32(PCM_CON1,
+ SPM_REGWR_CFG_KEY | RG_PCM_WDT_EN_LSB);
+ }
+}
+
+void __spm_send_cpu_wakeup_event(void)
+{
+ /* SPM will clear SPM_CPU_WAKEUP_EVENT */
+ mmio_write_32(SPM_CPU_WAKEUP_EVENT, 1);
+}
+
+void __spm_ext_int_wakeup_req_clr(void)
+{
+ mmio_write_32(EXT_INT_WAKEUP_REQ_CLR, mmio_read_32(ROOT_CPUTOP_ADDR));
+
+ /* Clear spm2mcupm wakeup interrupt status */
+ mmio_write_32(SPM2CPUEB_CON, 0);
+}
+
+void __spm_xo_soc_bblpm(int en)
+{
+ if (en == 1) {
+ mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
+ RC_SW_SRCLKEN_FPM, RC_SW_SRCLKEN_RC);
+ assert(mt_spm_bblpm_cnt == 0);
+ mt_spm_bblpm_cnt += 1;
+ } else {
+ mmio_clrsetbits_32(RC_M00_SRCLKEN_CFG,
+ RC_SW_SRCLKEN_RC, RC_SW_SRCLKEN_FPM);
+ mt_spm_bblpm_cnt -= 1;
+ }
+}
+
+void __spm_hw_s1_state_monitor(int en, unsigned int *status)
+{
+ unsigned int reg;
+
+ reg = mmio_read_32(SPM_ACK_CHK_CON_3);
+
+ if (en == 1) {
+ reg &= ~SPM_ACK_CHK_3_CON_CLR_ALL;
+ mmio_write_32(SPM_ACK_CHK_CON_3, reg);
+ reg |= SPM_ACK_CHK_3_CON_EN;
+ mmio_write_32(SPM_ACK_CHK_CON_3, reg);
+ } else {
+ if (((reg & SPM_ACK_CHK_3_CON_RESULT) != 0U) &&
+ (status != NULL)) {
+ *status |= SPM_INTERNAL_STATUS_HW_S1;
+ }
+
+ mmio_clrsetbits_32(SPM_ACK_CHK_CON_3, SPM_ACK_CHK_3_CON_EN,
+ SPM_ACK_CHK_3_CON_HW_MODE_TRIG |
+ SPM_ACK_CHK_3_CON_CLR_ALL);
+ }
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_internal.h b/plat/mediatek/mt8195/drivers/spm/mt_spm_internal.h
new file mode 100644
index 0000000..5ac7c91
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_internal.h
@@ -0,0 +1,583 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_INTERNAL_H
+#define MT_SPM_INTERNAL_H
+
+#include "mt_spm.h"
+
+/**************************************
+ * Config and Parameter
+ **************************************/
+#define POWER_ON_VAL0_DEF 0x0000F100
+#define POWER_ON_VAL1_DEF 0x80015860
+#define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */
+#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT)
+
+/**************************************
+ * Define and Declare
+ **************************************/
+/* PCM_PWR_IO_EN */
+#define PCM_PWRIO_EN_R0 (1U << 0)
+#define PCM_PWRIO_EN_R7 (1U << 7)
+#define PCM_RF_SYNC_R0 (1U << 16)
+#define PCM_RF_SYNC_R6 (1U << 22)
+#define PCM_RF_SYNC_R7 (1U << 23)
+
+/* SPM_SWINT */
+#define PCM_SW_INT0 (1U << 0)
+#define PCM_SW_INT1 (1U << 1)
+#define PCM_SW_INT2 (1U << 2)
+#define PCM_SW_INT3 (1U << 3)
+#define PCM_SW_INT4 (1U << 4)
+#define PCM_SW_INT5 (1U << 5)
+#define PCM_SW_INT6 (1U << 6)
+#define PCM_SW_INT7 (1U << 7)
+#define PCM_SW_INT8 (1U << 8)
+#define PCM_SW_INT9 (1U << 9)
+#define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \
+ PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \
+ PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \
+ PCM_SW_INT0)
+
+/* SPM_AP_STANDBY_CON */
+#define WFI_OP_AND 1
+#define WFI_OP_OR 0
+
+/* SPM_IRQ_MASK */
+#define ISRM_TWAM (1U << 2)
+#define ISRM_PCM_RETURN (1U << 3)
+#define ISRM_RET_IRQ0 (1U << 8)
+#define ISRM_RET_IRQ1 (1U << 9)
+#define ISRM_RET_IRQ2 (1U << 10)
+#define ISRM_RET_IRQ3 (1U << 11)
+#define ISRM_RET_IRQ4 (1U << 12)
+#define ISRM_RET_IRQ5 (1U << 13)
+#define ISRM_RET_IRQ6 (1U << 14)
+#define ISRM_RET_IRQ7 (1U << 15)
+#define ISRM_RET_IRQ8 (1U << 16)
+#define ISRM_RET_IRQ9 (1U << 17)
+#define ISRM_RET_IRQ_AUX ((ISRM_RET_IRQ9) | (ISRM_RET_IRQ8) | \
+ (ISRM_RET_IRQ7) | (ISRM_RET_IRQ6) | \
+ (ISRM_RET_IRQ5) | (ISRM_RET_IRQ4) | \
+ (ISRM_RET_IRQ3) | (ISRM_RET_IRQ2) | \
+ (ISRM_RET_IRQ1))
+#define ISRM_ALL_EXC_TWAM (ISRM_RET_IRQ_AUX)
+#define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM)
+
+/* SPM_IRQ_STA */
+#define ISRS_TWAM (1U << 2)
+#define ISRS_PCM_RETURN (1U << 3)
+#define ISRC_TWAM ISRS_TWAM
+#define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN
+#define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM)
+
+/* SPM_WAKEUP_MISC */
+#define WAKE_MISC_GIC_WAKEUP 0x3FF
+#define WAKE_MISC_DVFSRC_IRQ DVFSRC_IRQ_LSB
+#define WAKE_MISC_REG_CPU_WAKEUP SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB
+#define WAKE_MISC_PCM_TIMER_EVENT PCM_TIMER_EVENT_LSB
+#define WAKE_MISC_PMIC_OUT_B ((1U << 19) | (1U << 20))
+#define WAKE_MISC_TWAM_IRQ_B TWAM_IRQ_B_LSB
+#define WAKE_MISC_PMSR_IRQ_B_SET0 PMSR_IRQ_B_SET0_LSB
+#define WAKE_MISC_PMSR_IRQ_B_SET1 PMSR_IRQ_B_SET1_LSB
+#define WAKE_MISC_PMSR_IRQ_B_SET2 PMSR_IRQ_B_SET2_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_0 SPM_ACK_CHK_WAKEUP_0_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_1 SPM_ACK_CHK_WAKEUP_1_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_2 SPM_ACK_CHK_WAKEUP_2_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_3 SPM_ACK_CHK_WAKEUP_3_LSB
+#define WAKE_MISC_SPM_ACK_CHK_WAKEUP_ALL SPM_ACK_CHK_WAKEUP_ALL_LSB
+#define WAKE_MISC_PMIC_IRQ_ACK PMIC_IRQ_ACK_LSB
+#define WAKE_MISC_PMIC_SCP_IRQ PMIC_SCP_IRQ_LSB
+
+/* ABORT MASK for DEBUG FOORTPRINT */
+#define DEBUG_ABORT_MASK \
+ (SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC | \
+ SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN)
+
+#define DEBUG_ABORT_MASK_1 \
+ (SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT | \
+ SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT | \
+ SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT | \
+ SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT | \
+ SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT | \
+ SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT | \
+ SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT)
+
+#define MCUPM_MBOX_WAKEUP_CPU 0x0C55FD10
+
+struct pwr_ctrl {
+ uint32_t pcm_flags;
+ uint32_t pcm_flags_cust;
+ uint32_t pcm_flags_cust_set;
+ uint32_t pcm_flags_cust_clr;
+ uint32_t pcm_flags1;
+ uint32_t pcm_flags1_cust;
+ uint32_t pcm_flags1_cust_set;
+ uint32_t pcm_flags1_cust_clr;
+ uint32_t timer_val;
+ uint32_t timer_val_cust;
+ uint32_t timer_val_ramp_en;
+ uint32_t timer_val_ramp_en_sec;
+ uint32_t wake_src;
+ uint32_t wake_src_cust;
+ uint8_t wdt_disable;
+
+ /* SPM_AP_STANDBY_CON */
+ uint8_t reg_wfi_op;
+ uint8_t reg_wfi_type;
+ uint8_t reg_mp0_cputop_idle_mask;
+ uint8_t reg_mp1_cputop_idle_mask;
+ uint8_t reg_mcusys_idle_mask;
+ uint8_t reg_md_apsrc_1_sel;
+ uint8_t reg_md_apsrc_0_sel;
+ uint8_t reg_conn_apsrc_sel;
+
+ /* SPM_SRC_REQ */
+ uint8_t reg_spm_apsrc_req;
+ uint8_t reg_spm_f26m_req;
+ uint8_t reg_spm_infra_req;
+ uint8_t reg_spm_vrf18_req;
+ uint8_t reg_spm_ddr_en_req;
+ uint8_t reg_spm_dvfs_req;
+ uint8_t reg_spm_sw_mailbox_req;
+ uint8_t reg_spm_sspm_mailbox_req;
+ uint8_t reg_spm_adsp_mailbox_req;
+ uint8_t reg_spm_scp_mailbox_req;
+
+ /* SPM_SRC_MASK */
+ uint8_t reg_sspm_srcclkena_0_mask_b;
+ uint8_t reg_sspm_infra_req_0_mask_b;
+ uint8_t reg_sspm_apsrc_req_0_mask_b;
+ uint8_t reg_sspm_vrf18_req_0_mask_b;
+ uint8_t reg_sspm_ddr_en_0_mask_b;
+ uint8_t reg_scp_srcclkena_mask_b;
+ uint8_t reg_scp_infra_req_mask_b;
+ uint8_t reg_scp_apsrc_req_mask_b;
+ uint8_t reg_scp_vrf18_req_mask_b;
+ uint8_t reg_scp_ddr_en_mask_b;
+ uint8_t reg_audio_dsp_srcclkena_mask_b;
+ uint8_t reg_audio_dsp_infra_req_mask_b;
+ uint8_t reg_audio_dsp_apsrc_req_mask_b;
+ uint8_t reg_audio_dsp_vrf18_req_mask_b;
+ uint8_t reg_audio_dsp_ddr_en_mask_b;
+ uint8_t reg_apu_srcclkena_mask_b;
+ uint8_t reg_apu_infra_req_mask_b;
+ uint8_t reg_apu_apsrc_req_mask_b;
+ uint8_t reg_apu_vrf18_req_mask_b;
+ uint8_t reg_apu_ddr_en_mask_b;
+ uint8_t reg_cpueb_srcclkena_mask_b;
+ uint8_t reg_cpueb_infra_req_mask_b;
+ uint8_t reg_cpueb_apsrc_req_mask_b;
+ uint8_t reg_cpueb_vrf18_req_mask_b;
+ uint8_t reg_cpueb_ddr_en_mask_b;
+ uint8_t reg_bak_psri_srcclkena_mask_b;
+ uint8_t reg_bak_psri_infra_req_mask_b;
+ uint8_t reg_bak_psri_apsrc_req_mask_b;
+ uint8_t reg_bak_psri_vrf18_req_mask_b;
+ uint8_t reg_bak_psri_ddr_en_mask_b;
+
+ /* SPM_SRC2_MASK */
+ uint8_t reg_msdc0_srcclkena_mask_b;
+ uint8_t reg_msdc0_infra_req_mask_b;
+ uint8_t reg_msdc0_apsrc_req_mask_b;
+ uint8_t reg_msdc0_vrf18_req_mask_b;
+ uint8_t reg_msdc0_ddr_en_mask_b;
+ uint8_t reg_msdc1_srcclkena_mask_b;
+ uint8_t reg_msdc1_infra_req_mask_b;
+ uint8_t reg_msdc1_apsrc_req_mask_b;
+ uint8_t reg_msdc1_vrf18_req_mask_b;
+ uint8_t reg_msdc1_ddr_en_mask_b;
+ uint8_t reg_msdc2_srcclkena_mask_b;
+ uint8_t reg_msdc2_infra_req_mask_b;
+ uint8_t reg_msdc2_apsrc_req_mask_b;
+ uint8_t reg_msdc2_vrf18_req_mask_b;
+ uint8_t reg_msdc2_ddr_en_mask_b;
+ uint8_t reg_ufs_srcclkena_mask_b;
+ uint8_t reg_ufs_infra_req_mask_b;
+ uint8_t reg_ufs_apsrc_req_mask_b;
+ uint8_t reg_ufs_vrf18_req_mask_b;
+ uint8_t reg_ufs_ddr_en_mask_b;
+ uint8_t reg_usb_srcclkena_mask_b;
+ uint8_t reg_usb_infra_req_mask_b;
+ uint8_t reg_usb_apsrc_req_mask_b;
+ uint8_t reg_usb_vrf18_req_mask_b;
+ uint8_t reg_usb_ddr_en_mask_b;
+ uint8_t reg_pextp_p0_srcclkena_mask_b;
+ uint8_t reg_pextp_p0_infra_req_mask_b;
+ uint8_t reg_pextp_p0_apsrc_req_mask_b;
+ uint8_t reg_pextp_p0_vrf18_req_mask_b;
+ uint8_t reg_pextp_p0_ddr_en_mask_b;
+
+ /* SPM_SRC3_MASK */
+ uint8_t reg_pextp_p1_srcclkena_mask_b;
+ uint8_t reg_pextp_p1_infra_req_mask_b;
+ uint8_t reg_pextp_p1_apsrc_req_mask_b;
+ uint8_t reg_pextp_p1_vrf18_req_mask_b;
+ uint8_t reg_pextp_p1_ddr_en_mask_b;
+ uint8_t reg_gce0_infra_req_mask_b;
+ uint8_t reg_gce0_apsrc_req_mask_b;
+ uint8_t reg_gce0_vrf18_req_mask_b;
+ uint8_t reg_gce0_ddr_en_mask_b;
+ uint8_t reg_gce1_infra_req_mask_b;
+ uint8_t reg_gce1_apsrc_req_mask_b;
+ uint8_t reg_gce1_vrf18_req_mask_b;
+ uint8_t reg_gce1_ddr_en_mask_b;
+ uint8_t reg_spm_srcclkena_reserved_mask_b;
+ uint8_t reg_spm_infra_req_reserved_mask_b;
+ uint8_t reg_spm_apsrc_req_reserved_mask_b;
+ uint8_t reg_spm_vrf18_req_reserved_mask_b;
+ uint8_t reg_spm_ddr_en_reserved_mask_b;
+ uint8_t reg_disp0_apsrc_req_mask_b;
+ uint8_t reg_disp0_ddr_en_mask_b;
+ uint8_t reg_disp1_apsrc_req_mask_b;
+ uint8_t reg_disp1_ddr_en_mask_b;
+ uint8_t reg_disp2_apsrc_req_mask_b;
+ uint8_t reg_disp2_ddr_en_mask_b;
+ uint8_t reg_disp3_apsrc_req_mask_b;
+ uint8_t reg_disp3_ddr_en_mask_b;
+ uint8_t reg_infrasys_apsrc_req_mask_b;
+ uint8_t reg_infrasys_ddr_en_mask_b;
+ uint8_t reg_cg_check_srcclkena_mask_b;
+ uint8_t reg_cg_check_apsrc_req_mask_b;
+ uint8_t reg_cg_check_vrf18_req_mask_b;
+ uint8_t reg_cg_check_ddr_en_mask_b;
+
+ /* SPM_SRC4_MASK */
+ uint32_t reg_mcusys_merge_apsrc_req_mask_b;
+ uint32_t reg_mcusys_merge_ddr_en_mask_b;
+ uint8_t reg_dramc_md32_infra_req_mask_b;
+ uint8_t reg_dramc_md32_vrf18_req_mask_b;
+ uint8_t reg_dramc_md32_ddr_en_mask_b;
+ uint8_t reg_dvfsrc_event_trigger_mask_b;
+
+ /* SPM_WAKEUP_EVENT_MASK2 */
+ uint8_t reg_sc_sw2spm_wakeup_mask_b;
+ uint8_t reg_sc_adsp2spm_wakeup_mask_b;
+ uint8_t reg_sc_sspm2spm_wakeup_mask_b;
+ uint8_t reg_sc_scp2spm_wakeup_mask_b;
+ uint8_t reg_csyspwrup_ack_mask;
+ uint8_t reg_csyspwrup_req_mask;
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ uint32_t reg_wakeup_event_mask;
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ uint32_t reg_ext_wakeup_event_mask;
+};
+
+/* code gen by spm_pwr_ctrl_atf.pl, need struct pwr_ctrl */
+enum pwr_ctrl_enum {
+ PW_PCM_FLAGS,
+ PW_PCM_FLAGS_CUST,
+ PW_PCM_FLAGS_CUST_SET,
+ PW_PCM_FLAGS_CUST_CLR,
+ PW_PCM_FLAGS1,
+ PW_PCM_FLAGS1_CUST,
+ PW_PCM_FLAGS1_CUST_SET,
+ PW_PCM_FLAGS1_CUST_CLR,
+ PW_TIMER_VAL,
+ PW_TIMER_VAL_CUST,
+ PW_TIMER_VAL_RAMP_EN,
+ PW_TIMER_VAL_RAMP_EN_SEC,
+ PW_WAKE_SRC,
+ PW_WAKE_SRC_CUST,
+ PW_WAKELOCK_TIMER_VAL,
+ PW_WDT_DISABLE,
+
+ /* SPM_CLK_CON */
+ PW_REG_SRCCLKEN0_CTL,
+ PW_REG_SRCCLKEN1_CTL,
+ PW_REG_SPM_LOCK_INFRA_DCM,
+ PW_REG_SRCCLKEN_MASK,
+ PW_REG_MD1_C32RM_EN,
+ PW_REG_MD2_C32RM_EN,
+ PW_REG_CLKSQ0_SEL_CTRL,
+ PW_REG_CLKSQ1_SEL_CTRL,
+ PW_REG_SRCCLKEN0_EN,
+ PW_REG_SRCCLKEN1_EN,
+ PW_REG_SYSCLK0_SRC_MASK_B,
+ PW_REG_SYSCLK1_SRC_MASK_B,
+
+ /* SPM_AP_STANDBY_CON */
+ PW_REG_WFI_OP,
+ PW_REG_WFI_TYPE,
+ PW_REG_MP0_CPUTOP_IDLE_MASK,
+ PW_REG_MP1_CPUTOP_IDLE_MASK,
+ PW_REG_MCUSYS_IDLE_MASK,
+ PW_REG_MD_APSRC_1_SEL,
+ PW_REG_MD_APSRC_0_SEL,
+ PW_REG_CONN_APSRC_SEL,
+
+ /* SPM_SRC_REQ */
+ PW_REG_SPM_APSRC_REQ,
+ PW_REG_SPM_F26M_REQ,
+ PW_REG_SPM_INFRA_REQ,
+ PW_REG_SPM_VRF18_REQ,
+ PW_REG_SPM_DDR_EN_REQ,
+ PW_REG_SPM_DVFS_REQ,
+ PW_REG_SPM_SW_MAILBOX_REQ,
+ PW_REG_SPM_SSPM_MAILBOX_REQ,
+ PW_REG_SPM_ADSP_MAILBOX_REQ,
+ PW_REG_SPM_SCP_MAILBOX_REQ,
+
+ /* SPM_SRC_MASK */
+ PW_REG_MD_SRCCLKENA_0_MASK_B,
+ PW_REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B,
+ PW_REG_MD_APSRC2INFRA_REQ_0_MASK_B,
+ PW_REG_MD_APSRC_REQ_0_MASK_B,
+ PW_REG_MD_VRF18_REQ_0_MASK_B,
+ PW_REG_MD_DDR_EN_0_MASK_B,
+ PW_REG_MD_SRCCLKENA_1_MASK_B,
+ PW_REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B,
+ PW_REG_MD_APSRC2INFRA_REQ_1_MASK_B,
+ PW_REG_MD_APSRC_REQ_1_MASK_B,
+ PW_REG_MD_VRF18_REQ_1_MASK_B,
+ PW_REG_MD_DDR_EN_1_MASK_B,
+ PW_REG_CONN_SRCCLKENA_MASK_B,
+ PW_REG_CONN_SRCCLKENB_MASK_B,
+ PW_REG_CONN_INFRA_REQ_MASK_B,
+ PW_REG_CONN_APSRC_REQ_MASK_B,
+ PW_REG_CONN_VRF18_REQ_MASK_B,
+ PW_REG_CONN_DDR_EN_MASK_B,
+ PW_REG_CONN_VFE28_MASK_B,
+ PW_REG_SRCCLKENI0_SRCCLKENA_MASK_B,
+ PW_REG_SRCCLKENI0_INFRA_REQ_MASK_B,
+ PW_REG_SRCCLKENI1_SRCCLKENA_MASK_B,
+ PW_REG_SRCCLKENI1_INFRA_REQ_MASK_B,
+ PW_REG_SRCCLKENI2_SRCCLKENA_MASK_B,
+ PW_REG_SRCCLKENI2_INFRA_REQ_MASK_B,
+ PW_REG_INFRASYS_APSRC_REQ_MASK_B,
+ PW_REG_INFRASYS_DDR_EN_MASK_B,
+ PW_REG_MD32_SRCCLKENA_MASK_B,
+ PW_REG_MD32_INFRA_REQ_MASK_B,
+ PW_REG_MD32_APSRC_REQ_MASK_B,
+ PW_REG_MD32_VRF18_REQ_MASK_B,
+ PW_REG_MD32_DDR_EN_MASK_B,
+
+ /* SPM_SRC2_MASK */
+ PW_REG_SCP_SRCCLKENA_MASK_B,
+ PW_REG_SCP_INFRA_REQ_MASK_B,
+ PW_REG_SCP_APSRC_REQ_MASK_B,
+ PW_REG_SCP_VRF18_REQ_MASK_B,
+ PW_REG_SCP_DDR_EN_MASK_B,
+ PW_REG_AUDIO_DSP_SRCCLKENA_MASK_B,
+ PW_REG_AUDIO_DSP_INFRA_REQ_MASK_B,
+ PW_REG_AUDIO_DSP_APSRC_REQ_MASK_B,
+ PW_REG_AUDIO_DSP_VRF18_REQ_MASK_B,
+ PW_REG_AUDIO_DSP_DDR_EN_MASK_B,
+ PW_REG_UFS_SRCCLKENA_MASK_B,
+ PW_REG_UFS_INFRA_REQ_MASK_B,
+ PW_REG_UFS_APSRC_REQ_MASK_B,
+ PW_REG_UFS_VRF18_REQ_MASK_B,
+ PW_REG_UFS_DDR_EN_MASK_B,
+ PW_REG_DISP0_APSRC_REQ_MASK_B,
+ PW_REG_DISP0_DDR_EN_MASK_B,
+ PW_REG_DISP1_APSRC_REQ_MASK_B,
+ PW_REG_DISP1_DDR_EN_MASK_B,
+ PW_REG_GCE_INFRA_REQ_MASK_B,
+ PW_REG_GCE_APSRC_REQ_MASK_B,
+ PW_REG_GCE_VRF18_REQ_MASK_B,
+ PW_REG_GCE_DDR_EN_MASK_B,
+ PW_REG_APU_SRCCLKENA_MASK_B,
+ PW_REG_APU_INFRA_REQ_MASK_B,
+ PW_REG_APU_APSRC_REQ_MASK_B,
+ PW_REG_APU_VRF18_REQ_MASK_B,
+ PW_REG_APU_DDR_EN_MASK_B,
+ PW_REG_CG_CHECK_SRCCLKENA_MASK_B,
+ PW_REG_CG_CHECK_APSRC_REQ_MASK_B,
+ PW_REG_CG_CHECK_VRF18_REQ_MASK_B,
+ PW_REG_CG_CHECK_DDR_EN_MASK_B,
+
+ /* SPM_SRC3_MASK */
+ PW_REG_DVFSRC_EVENT_TRIGGER_MASK_B,
+ PW_REG_SW2SPM_INT0_MASK_B,
+ PW_REG_SW2SPM_INT1_MASK_B,
+ PW_REG_SW2SPM_INT2_MASK_B,
+ PW_REG_SW2SPM_INT3_MASK_B,
+ PW_REG_SC_ADSP2SPM_WAKEUP_MASK_B,
+ PW_REG_SC_SSPM2SPM_WAKEUP_MASK_B,
+ PW_REG_SC_SCP2SPM_WAKEUP_MASK_B,
+ PW_REG_CSYSPWRREQ_MASK,
+ PW_REG_SPM_SRCCLKENA_RESERVED_MASK_B,
+ PW_REG_SPM_INFRA_REQ_RESERVED_MASK_B,
+ PW_REG_SPM_APSRC_REQ_RESERVED_MASK_B,
+ PW_REG_SPM_VRF18_REQ_RESERVED_MASK_B,
+ PW_REG_SPM_DDR_EN_RESERVED_MASK_B,
+ PW_REG_MCUPM_SRCCLKENA_MASK_B,
+ PW_REG_MCUPM_INFRA_REQ_MASK_B,
+ PW_REG_MCUPM_APSRC_REQ_MASK_B,
+ PW_REG_MCUPM_VRF18_REQ_MASK_B,
+ PW_REG_MCUPM_DDR_EN_MASK_B,
+ PW_REG_MSDC0_SRCCLKENA_MASK_B,
+ PW_REG_MSDC0_INFRA_REQ_MASK_B,
+ PW_REG_MSDC0_APSRC_REQ_MASK_B,
+ PW_REG_MSDC0_VRF18_REQ_MASK_B,
+ PW_REG_MSDC0_DDR_EN_MASK_B,
+ PW_REG_MSDC1_SRCCLKENA_MASK_B,
+ PW_REG_MSDC1_INFRA_REQ_MASK_B,
+ PW_REG_MSDC1_APSRC_REQ_MASK_B,
+ PW_REG_MSDC1_VRF18_REQ_MASK_B,
+ PW_REG_MSDC1_DDR_EN_MASK_B,
+
+ /* SPM_SRC4_MASK */
+ PW_CCIF_EVENT_MASK_B,
+ PW_REG_BAK_PSRI_SRCCLKENA_MASK_B,
+ PW_REG_BAK_PSRI_INFRA_REQ_MASK_B,
+ PW_REG_BAK_PSRI_APSRC_REQ_MASK_B,
+ PW_REG_BAK_PSRI_VRF18_REQ_MASK_B,
+ PW_REG_BAK_PSRI_DDR_EN_MASK_B,
+ PW_REG_DRAMC0_MD32_INFRA_REQ_MASK_B,
+ PW_REG_DRAMC0_MD32_VRF18_REQ_MASK_B,
+ PW_REG_DRAMC1_MD32_INFRA_REQ_MASK_B,
+ PW_REG_DRAMC1_MD32_VRF18_REQ_MASK_B,
+ PW_REG_CONN_SRCCLKENB2PWRAP_MASK_B,
+ PW_REG_DRAMC0_MD32_WAKEUP_MASK,
+ PW_REG_DRAMC1_MD32_WAKEUP_MASK,
+
+ /* SPM_SRC5_MASK */
+ PW_REG_MCUSYS_MERGE_APSRC_REQ_MASK_B,
+ PW_REG_MCUSYS_MERGE_DDR_EN_MASK_B,
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ PW_REG_WAKEUP_EVENT_MASK,
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ PW_REG_EXT_WAKEUP_EVENT_MASK,
+
+ PW_MAX_COUNT,
+};
+
+#define SPM_INTERNAL_STATUS_HW_S1 (1U << 0)
+#define SPM_ACK_CHK_3_SEL_HW_S1 0x00350098
+#define SPM_ACK_CHK_3_HW_S1_CNT 1
+#define SPM_ACK_CHK_3_CON_HW_MODE_TRIG 0x800
+#define SPM_ACK_CHK_3_CON_EN 0x110
+#define SPM_ACK_CHK_3_CON_CLR_ALL 0x2
+#define SPM_ACK_CHK_3_CON_RESULT 0x8000
+
+struct wake_status_trace_comm {
+ uint32_t debug_flag; /* PCM_WDT_LATCH_SPARE_0 */
+ uint32_t debug_flag1; /* PCM_WDT_LATCH_SPARE_1 */
+ uint32_t timer_out; /* SPM_BK_PCM_TIMER */
+ uint32_t b_sw_flag0; /* SPM_SW_RSV_7 */
+ uint32_t b_sw_flag1; /* SPM_SW_RSV_8 */
+ uint32_t r12; /* SPM_SW_RSV_0 */
+ uint32_t r13; /* PCM_REG13_DATA */
+ uint32_t req_sta0; /* SRC_REQ_STA_0 */
+ uint32_t req_sta1; /* SRC_REQ_STA_1 */
+ uint32_t req_sta2; /* SRC_REQ_STA_2 */
+ uint32_t req_sta3; /* SRC_REQ_STA_3 */
+ uint32_t req_sta4; /* SRC_REQ_STA_4 */
+ uint32_t raw_sta; /* SPM_WAKEUP_STA */
+ uint32_t times_h; /* timestamp high bits */
+ uint32_t times_l; /* timestamp low bits */
+ uint32_t resumetime; /* timestamp low bits */
+};
+
+struct wake_status_trace {
+ struct wake_status_trace_comm comm;
+};
+
+struct wake_status {
+ struct wake_status_trace tr;
+ uint32_t r12; /* SPM_BK_WAKE_EVENT */
+ uint32_t r12_ext; /* SPM_WAKEUP_STA */
+ uint32_t raw_sta; /* SPM_WAKEUP_STA */
+ uint32_t raw_ext_sta; /* SPM_WAKEUP_EXT_STA */
+ uint32_t md32pcm_wakeup_sta; /* MD32PCM_WAKEUP_STA */
+ uint32_t md32pcm_event_sta; /* MD32PCM_EVENT_STA */
+ uint32_t src_req; /* SPM_SRC_REQ */
+ uint32_t wake_misc; /* SPM_BK_WAKE_MISC */
+ uint32_t timer_out; /* SPM_BK_PCM_TIMER */
+ uint32_t r13; /* PCM_REG13_DATA */
+ uint32_t idle_sta; /* SUBSYS_IDLE_STA */
+ uint32_t req_sta0; /* SRC_REQ_STA_0 */
+ uint32_t req_sta1; /* SRC_REQ_STA_1 */
+ uint32_t req_sta2; /* SRC_REQ_STA_2 */
+ uint32_t req_sta3; /* SRC_REQ_STA_3 */
+ uint32_t req_sta4; /* SRC_REQ_STA_4 */
+ uint32_t cg_check_sta; /* SPM_CG_CHECK_STA */
+ uint32_t debug_flag; /* PCM_WDT_LATCH_SPARE_0 */
+ uint32_t debug_flag1; /* PCM_WDT_LATCH_SPARE_1 */
+ uint32_t b_sw_flag0; /* SPM_SW_RSV_7 */
+ uint32_t b_sw_flag1; /* SPM_SW_RSV_8 */
+ uint32_t rt_req_sta0; /* SPM_SW_RSV_2 */
+ uint32_t rt_req_sta1; /* SPM_SW_RSV_3 */
+ uint32_t rt_req_sta2; /* SPM_SW_RSV_4 */
+ uint32_t rt_req_sta3; /* SPM_SW_RSV_5 */
+ uint32_t rt_req_sta4; /* SPM_SW_RSV_6 */
+ uint32_t isr; /* SPM_IRQ_STA */
+ uint32_t sw_flag0; /* SPM_SW_FLAG_0 */
+ uint32_t sw_flag1; /* SPM_SW_FLAG_1 */
+ uint32_t clk_settle; /* SPM_CLK_SETTLE */
+ uint32_t abort;
+};
+
+struct spm_lp_scen {
+ struct pcm_desc *pcmdesc;
+ struct pwr_ctrl *pwrctrl;
+};
+
+extern struct spm_lp_scen __spm_vcorefs;
+extern void __spm_set_cpu_status(unsigned int cpu);
+extern void __spm_reset_and_init_pcm(const struct pcm_desc *pcmdesc);
+extern void __spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc);
+extern void __spm_init_pcm_register(void);
+extern void __spm_src_req_update(const struct pwr_ctrl *pwrctrl,
+ unsigned int resource_usage);
+extern void __spm_set_power_control(const struct pwr_ctrl *pwrctrl);
+extern void __spm_disable_pcm_timer(void);
+extern void __spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl);
+extern void __spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl);
+extern void __spm_set_pcm_flags(struct pwr_ctrl *pwrctrl);
+extern void __spm_send_cpu_wakeup_event(void);
+extern void __spm_get_wakeup_status(struct wake_status *wakesta,
+ unsigned int ext_status);
+extern void __spm_clean_after_wakeup(void);
+extern wake_reason_t
+__spm_output_wake_reason(int state_id, const struct wake_status *wakesta);
+extern void
+__spm_sync_vcore_dvfs_power_control(struct pwr_ctrl *dest_pwr_ctrl,
+ const struct pwr_ctrl *src_pwr_ctrl);
+extern void __spm_set_pcm_wdt(int en);
+extern uint32_t _spm_get_wake_period(int pwake_time, wake_reason_t last_wr);
+extern void __spm_set_fw_resume_option(struct pwr_ctrl *pwrctrl);
+extern void __spm_ext_int_wakeup_req_clr(void);
+extern void __spm_xo_soc_bblpm(int en);
+
+static inline void set_pwrctrl_pcm_flags(struct pwr_ctrl *pwrctrl,
+ uint32_t flags)
+{
+ if (pwrctrl->pcm_flags_cust == 0U) {
+ pwrctrl->pcm_flags = flags;
+ } else {
+ pwrctrl->pcm_flags = pwrctrl->pcm_flags_cust;
+ }
+}
+
+static inline void set_pwrctrl_pcm_flags1(struct pwr_ctrl *pwrctrl,
+ uint32_t flags)
+{
+ if (pwrctrl->pcm_flags1_cust == 0U) {
+ pwrctrl->pcm_flags1 = flags;
+ } else {
+ pwrctrl->pcm_flags1 = pwrctrl->pcm_flags1_cust;
+ }
+}
+
+extern void __spm_hw_s1_state_monitor(int en, unsigned int *status);
+
+static inline void spm_hw_s1_state_monitor_resume(void)
+{
+ __spm_hw_s1_state_monitor(1, NULL);
+}
+
+static inline void spm_hw_s1_state_monitor_pause(unsigned int *status)
+{
+ __spm_hw_s1_state_monitor(0, status);
+}
+#endif /* MT_SPM_INTERNAL_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_pmic_wrap.c b/plat/mediatek/mt8195/drivers/spm/mt_spm_pmic_wrap.c
new file mode 100644
index 0000000..9da644c
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_pmic_wrap.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include <mt_spm.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_pmic_wrap.h>
+#include <mt_spm_reg.h>
+#include <plat_pm.h>
+#include <platform_def.h>
+
+/* PMIC_WRAP MT6359 */
+#define VCORE_BASE_UV 40000
+#define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 625 - 1) / 625)
+#define PMIC_VAL_TO_VOLT(pmic) (((pmic) * 625) + VCORE_BASE_UV)
+
+#define NR_PMIC_WRAP_CMD (NR_IDX_ALL)
+#define SPM_DATA_SHIFT 16
+
+#define BUCK_VGPU11_ELR0 0x15B4
+#define TOP_SPI_CON0 0x0456
+#define BUCK_TOP_CON1 0x1443
+#define TOP_CON 0x0013
+#define TOP_DIG_WPK 0x03a9
+#define TOP_CON_LOCK 0x03a8
+#define TOP_CLK_CON0 0x0134
+
+struct pmic_wrap_cmd {
+ unsigned long cmd_addr;
+ unsigned long cmd_wdata;
+};
+
+struct pmic_wrap_setting {
+ enum pmic_wrap_phase_id phase;
+ struct pmic_wrap_cmd addr[NR_PMIC_WRAP_CMD];
+ struct {
+ struct {
+ unsigned long cmd_addr;
+ unsigned long cmd_wdata;
+ } _[NR_PMIC_WRAP_CMD];
+ const int nr_idx;
+ } set[NR_PMIC_WRAP_PHASE];
+};
+
+static struct pmic_wrap_setting pw = {
+ .phase = NR_PMIC_WRAP_PHASE, /* invalid setting for init */
+ .addr = { {0UL, 0UL} },
+ .set[PMIC_WRAP_PHASE_ALLINONE] = {
+ ._[CMD_0] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(75000),},
+ ._[CMD_1] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(65000),},
+ ._[CMD_2] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(60000),},
+ ._[CMD_3] = {BUCK_VGPU11_ELR0, VOLT_TO_PMIC_VAL(55000),},
+ ._[CMD_4] = {TOP_SPI_CON0, 0x1,},
+ ._[CMD_5] = {TOP_SPI_CON0, 0x0,},
+ ._[CMD_6] = {BUCK_TOP_CON1, 0x0,},
+ ._[CMD_7] = {BUCK_TOP_CON1, 0xf,},
+ ._[CMD_8] = {TOP_CON, 0x3,},
+ ._[CMD_9] = {TOP_CON, 0x0,},
+ ._[CMD_10] = {TOP_DIG_WPK, 0x63,},
+ ._[CMD_11] = {TOP_CON_LOCK, 0x15,},
+ ._[CMD_12] = {TOP_DIG_WPK, 0x0,},
+ ._[CMD_13] = {TOP_CON_LOCK, 0x0,},
+ ._[CMD_14] = {TOP_CLK_CON0, 0x40,},
+ ._[CMD_15] = {TOP_CLK_CON0, 0x0,},
+ .nr_idx = NR_IDX_ALL,
+ },
+};
+
+void _mt_spm_pmic_table_init(void)
+{
+ struct pmic_wrap_cmd pwrap_cmd_default[NR_PMIC_WRAP_CMD] = {
+ {(uint32_t)SPM_DVFS_CMD0, (uint32_t)SPM_DVFS_CMD0,},
+ {(uint32_t)SPM_DVFS_CMD1, (uint32_t)SPM_DVFS_CMD1,},
+ {(uint32_t)SPM_DVFS_CMD2, (uint32_t)SPM_DVFS_CMD2,},
+ {(uint32_t)SPM_DVFS_CMD3, (uint32_t)SPM_DVFS_CMD3,},
+ {(uint32_t)SPM_DVFS_CMD4, (uint32_t)SPM_DVFS_CMD4,},
+ {(uint32_t)SPM_DVFS_CMD5, (uint32_t)SPM_DVFS_CMD5,},
+ {(uint32_t)SPM_DVFS_CMD6, (uint32_t)SPM_DVFS_CMD6,},
+ {(uint32_t)SPM_DVFS_CMD7, (uint32_t)SPM_DVFS_CMD7,},
+ {(uint32_t)SPM_DVFS_CMD8, (uint32_t)SPM_DVFS_CMD8,},
+ {(uint32_t)SPM_DVFS_CMD9, (uint32_t)SPM_DVFS_CMD9,},
+ {(uint32_t)SPM_DVFS_CMD10, (uint32_t)SPM_DVFS_CMD10,},
+ {(uint32_t)SPM_DVFS_CMD11, (uint32_t)SPM_DVFS_CMD11,},
+ {(uint32_t)SPM_DVFS_CMD12, (uint32_t)SPM_DVFS_CMD12,},
+ {(uint32_t)SPM_DVFS_CMD13, (uint32_t)SPM_DVFS_CMD13,},
+ {(uint32_t)SPM_DVFS_CMD14, (uint32_t)SPM_DVFS_CMD14,},
+ {(uint32_t)SPM_DVFS_CMD15, (uint32_t)SPM_DVFS_CMD15,},
+ };
+
+ memcpy(pw.addr, pwrap_cmd_default, sizeof(pwrap_cmd_default));
+}
+
+void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase)
+{
+ uint32_t idx, addr, data;
+
+ if (phase >= NR_PMIC_WRAP_PHASE) {
+ return;
+ }
+
+ if (pw.phase == phase) {
+ return;
+ }
+
+ if (pw.addr[0].cmd_addr == 0UL) {
+ _mt_spm_pmic_table_init();
+ }
+
+ pw.phase = phase;
+ mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
+
+ for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) {
+ addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
+ data = pw.set[phase]._[idx].cmd_wdata;
+ mmio_write_32(pw.addr[idx].cmd_addr, addr | data);
+ }
+}
+
+void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx,
+ uint32_t cmd_wdata)
+{
+ uint32_t addr;
+
+ if (phase >= NR_PMIC_WRAP_PHASE) {
+ return;
+ }
+
+ if (idx >= pw.set[phase].nr_idx) {
+ return;
+ }
+
+ pw.set[phase]._[idx].cmd_wdata = cmd_wdata;
+ mmio_write_32(POWERON_CONFIG_EN, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB);
+
+ if (pw.phase == phase) {
+ addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT;
+ mmio_write_32(pw.addr[idx].cmd_addr, addr | cmd_wdata);
+ }
+}
+
+uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, uint32_t idx)
+{
+ if (phase >= NR_PMIC_WRAP_PHASE) {
+ return 0UL;
+ }
+
+ if (idx >= pw.set[phase].nr_idx) {
+ return 0UL;
+ }
+
+ return pw.set[phase]._[idx].cmd_wdata;
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_pmic_wrap.h b/plat/mediatek/mt8195/drivers/spm/mt_spm_pmic_wrap.h
new file mode 100644
index 0000000..53fdda2
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_pmic_wrap.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/****************************************************************
+ * Auto generated by DE, please DO NOT modify this file directly.
+ *****************************************************************/
+#ifndef MT_SPM_PMIC_WRAP_H
+#define MT_SPM_PMIC_WRAP_H
+
+enum pmic_wrap_phase_id {
+ PMIC_WRAP_PHASE_ALLINONE,
+ NR_PMIC_WRAP_PHASE,
+};
+
+/* IDX mapping, PMIC_WRAP_PHASE_ALLINONE */
+enum {
+ CMD_0, /* 0x0 */
+ CMD_1, /* 0x1 */
+ CMD_2, /* 0x2 */
+ CMD_3, /* 0x3 */
+ CMD_4, /* 0x4 */
+ CMD_5, /* 0x5 */
+ CMD_6, /* 0x6 */
+ CMD_7, /* 0x7 */
+ CMD_8, /* 0x8 */
+ CMD_9, /* 0x9 */
+ CMD_10, /* 0xA */
+ CMD_11, /* 0xB */
+ CMD_12, /* 0xC */
+ CMD_13, /* 0xD */
+ CMD_14, /* 0xE */
+ CMD_15, /* 0xF */
+ NR_IDX_ALL,
+};
+
+/* APIs */
+extern void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase);
+extern void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase,
+ uint32_t idx, uint32_t cmd_wdata);
+extern uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase,
+ uint32_t idx);
+#endif /* MT_SPM_PMIC_WRAP_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_reg.h b/plat/mediatek/mt8195/drivers/spm/mt_spm_reg.h
new file mode 100644
index 0000000..d8b9b29
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_reg.h
@@ -0,0 +1,2859 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/****************************************************************
+ * Auto generated by DE, please DO NOT modify this file directly.
+ *****************************************************************/
+
+#ifndef MT_SPM_REG
+#define MT_SPM_REG
+
+#include "sleep_def.h"
+#include <platform_def.h>
+#include "pcm_def.h"
+
+/**************************************
+ * Define and Declare
+ **************************************/
+
+/*******Register_SPM_CFG*************************************************/
+#define POWERON_CONFIG_EN (SPM_BASE + 0x000)
+#define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004)
+#define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008)
+#define SPM_CLK_CON (SPM_BASE + 0x00C)
+#define SPM_CLK_SETTLE (SPM_BASE + 0x010)
+#define SPM_AP_STANDBY_CON (SPM_BASE + 0x014)
+#define PCM_CON0 (SPM_BASE + 0x018)
+#define PCM_CON1 (SPM_BASE + 0x01C)
+#define SPM_POWER_ON_VAL2 (SPM_BASE + 0x020)
+#define SPM_POWER_ON_VAL3 (SPM_BASE + 0x024)
+#define PCM_REG_DATA_INI (SPM_BASE + 0x028)
+#define PCM_PWR_IO_EN (SPM_BASE + 0x02C)
+#define PCM_TIMER_VAL (SPM_BASE + 0x030)
+#define PCM_WDT_VAL (SPM_BASE + 0x034)
+#define SPM_SW_RST_CON (SPM_BASE + 0x040)
+#define SPM_SW_RST_CON_SET (SPM_BASE + 0x044)
+#define SPM_SW_RST_CON_CLR (SPM_BASE + 0x048)
+#define VS1_PSR_MASK_B (SPM_BASE + 0x04C)
+#define SPM_ARBITER_EN (SPM_BASE + 0x050)
+#define SCPSYS_CLK_CON (SPM_BASE + 0x054)
+#define SPM_SRAM_RSV_CON (SPM_BASE + 0x058)
+#define SPM_SWINT (SPM_BASE + 0x05C)
+#define SPM_SWINT_SET (SPM_BASE + 0x060)
+#define SPM_SWINT_CLR (SPM_BASE + 0x064)
+#define SPM_SCP_MAILBOX (SPM_BASE + 0x068)
+#define SCP_SPM_MAILBOX (SPM_BASE + 0x06C)
+#define SPM_SCP_IRQ (SPM_BASE + 0x070)
+#define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x074)
+#define SPM_IRQ_MASK (SPM_BASE + 0x078)
+#define SPM_SRC_REQ (SPM_BASE + 0x080)
+#define SPM_SRC_MASK (SPM_BASE + 0x084)
+#define SPM_SRC2_MASK (SPM_BASE + 0x088)
+#define SPM_SRC3_MASK (SPM_BASE + 0x090)
+#define SPM_SRC4_MASK (SPM_BASE + 0x094)
+#define SPM_WAKEUP_EVENT_MASK2 (SPM_BASE + 0x098)
+#define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x09C)
+#define SPM_WAKEUP_EVENT_SENS (SPM_BASE + 0x0A0)
+#define SPM_WAKEUP_EVENT_CLEAR (SPM_BASE + 0x0A4)
+#define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x0A8)
+#define SCP_CLK_CON (SPM_BASE + 0x0AC)
+#define PCM_DEBUG_CON (SPM_BASE + 0x0B0)
+#define DDREN_DBC_CON (SPM_BASE + 0x0B4)
+#define SPM_RESOURCE_ACK_CON0 (SPM_BASE + 0x0B8)
+#define SPM_RESOURCE_ACK_CON1 (SPM_BASE + 0x0BC)
+#define SPM_RESOURCE_ACK_CON2 (SPM_BASE + 0x0C0)
+#define SPM_RESOURCE_ACK_CON3 (SPM_BASE + 0x0C4)
+#define SPM_RESOURCE_ACK_CON4 (SPM_BASE + 0x0C8)
+#define SPM_SRAM_CON (SPM_BASE + 0x0CC)
+/*******Register_SPM_STA*************************************************/
+#define PCM_REG0_DATA (SPM_BASE + 0x100)
+#define PCM_REG2_DATA (SPM_BASE + 0x104)
+#define PCM_REG6_DATA (SPM_BASE + 0x108)
+#define PCM_REG7_DATA (SPM_BASE + 0x10C)
+#define PCM_REG13_DATA (SPM_BASE + 0x110)
+#define SRC_REQ_STA_0 (SPM_BASE + 0x114)
+#define SRC_REQ_STA_1 (SPM_BASE + 0x118)
+#define SRC_REQ_STA_2 (SPM_BASE + 0x120)
+#define SRC_REQ_STA_3 (SPM_BASE + 0x124)
+#define SRC_REQ_STA_4 (SPM_BASE + 0x128)
+#define PCM_TIMER_OUT (SPM_BASE + 0x130)
+#define PCM_WDT_OUT (SPM_BASE + 0x134)
+#define SPM_IRQ_STA (SPM_BASE + 0x138)
+#define MD32PCM_WAKEUP_STA (SPM_BASE + 0x13C)
+#define MD32PCM_EVENT_STA (SPM_BASE + 0x140)
+#define SPM_WAKEUP_STA (SPM_BASE + 0x144)
+#define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x148)
+#define SPM_WAKEUP_MISC (SPM_BASE + 0x14C)
+#define MM_DVFS_HALT (SPM_BASE + 0x150)
+#define SUBSYS_IDLE_STA (SPM_BASE + 0x164)
+#define PCM_STA (SPM_BASE + 0x168)
+#define PWR_STATUS (SPM_BASE + 0x16C)
+#define PWR_STATUS_2ND (SPM_BASE + 0x170)
+#define CPU_PWR_STATUS (SPM_BASE + 0x174)
+#define CPU_PWR_STATUS_2ND (SPM_BASE + 0x178)
+#define SPM_VTCXO_EVENT_COUNT_STA (SPM_BASE + 0x17C)
+#define SPM_INFRA_EVENT_COUNT_STA (SPM_BASE + 0x180)
+#define SPM_VRF18_EVENT_COUNT_STA (SPM_BASE + 0x184)
+#define SPM_APSRC_EVENT_COUNT_STA (SPM_BASE + 0x188)
+#define SPM_DDREN_EVENT_COUNT_STA (SPM_BASE + 0x18C)
+#define MD32PCM_STA (SPM_BASE + 0x190)
+#define MD32PCM_PC (SPM_BASE + 0x194)
+#define OTHER_PWR_STATUS (SPM_BASE + 0x198)
+#define DVFSRC_EVENT_STA (SPM_BASE + 0x19C)
+#define BUS_PROTECT_RDY (SPM_BASE + 0x1A0)
+#define BUS_PROTECT1_RDY (SPM_BASE + 0x1A4)
+#define BUS_PROTECT2_RDY (SPM_BASE + 0x1A8)
+#define BUS_PROTECT3_RDY (SPM_BASE + 0x1AC)
+#define BUS_PROTECT4_RDY (SPM_BASE + 0x1B0)
+#define BUS_PROTECT5_RDY (SPM_BASE + 0x1B4)
+#define BUS_PROTECT6_RDY (SPM_BASE + 0x1B8)
+#define BUS_PROTECT7_RDY (SPM_BASE + 0x1BC)
+#define BUS_PROTECT8_RDY (SPM_BASE + 0x1C0)
+#define BUS_PROTECT9_RDY (SPM_BASE + 0x1C4)
+#define SPM_TWAM_LAST_STA0 (SPM_BASE + 0x1D0)
+#define SPM_TWAM_LAST_STA1 (SPM_BASE + 0x1D4)
+#define SPM_TWAM_LAST_STA2 (SPM_BASE + 0x1D8)
+#define SPM_TWAM_LAST_STA3 (SPM_BASE + 0x1DC)
+#define SPM_TWAM_CURR_STA0 (SPM_BASE + 0x1E0)
+#define SPM_TWAM_CURR_STA1 (SPM_BASE + 0x1E4)
+#define SPM_TWAM_CURR_STA2 (SPM_BASE + 0x1E8)
+#define SPM_TWAM_CURR_STA3 (SPM_BASE + 0x1EC)
+#define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x1F0)
+#define SPM_CG_CHECK_STA (SPM_BASE + 0x1F4)
+#define SPM_DVFS_STA (SPM_BASE + 0x1F8)
+#define SPM_DVFS_OPP_STA (SPM_BASE + 0x1FC)
+/*******Register_CPU_MT*************************************************/
+#define CPUEB_PWR_CON (SPM_BASE + 0x200)
+#define SPM_MCUSYS_PWR_CON (SPM_BASE + 0x204)
+#define SPM_CPUTOP_PWR_CON (SPM_BASE + 0x208)
+#define SPM_CPU0_PWR_CON (SPM_BASE + 0x20C)
+#define SPM_CPU1_PWR_CON (SPM_BASE + 0x210)
+#define SPM_CPU2_PWR_CON (SPM_BASE + 0x214)
+#define SPM_CPU3_PWR_CON (SPM_BASE + 0x218)
+#define SPM_CPU4_PWR_CON (SPM_BASE + 0x21C)
+#define SPM_CPU5_PWR_CON (SPM_BASE + 0x220)
+#define SPM_CPU6_PWR_CON (SPM_BASE + 0x224)
+#define SPM_CPU7_PWR_CON (SPM_BASE + 0x228)
+#define ARMPLL_CLK_CON (SPM_BASE + 0x22C)
+#define MCUSYS_IDLE_STA (SPM_BASE + 0x230)
+#define GIC_WAKEUP_STA (SPM_BASE + 0x234)
+#define CPU_SPARE_CON (SPM_BASE + 0x238)
+#define CPU_SPARE_CON_SET (SPM_BASE + 0x23C)
+#define CPU_SPARE_CON_CLR (SPM_BASE + 0x240)
+#define ARMPLL_CLK_SEL (SPM_BASE + 0x244)
+#define EXT_INT_WAKEUP_REQ (SPM_BASE + 0x248)
+#define EXT_INT_WAKEUP_REQ_SET (SPM_BASE + 0x24C)
+#define EXT_INT_WAKEUP_REQ_CLR (SPM_BASE + 0x250)
+#define CPU0_IRQ_MASK (SPM_BASE + 0x260)
+#define CPU_IRQ_MASK_SET (SPM_BASE + 0x264)
+#define CPU_IRQ_MASK_CLR (SPM_BASE + 0x268)
+#define CPU_WFI_EN (SPM_BASE + 0x280)
+#define CPU_WFI_EN_SET (SPM_BASE + 0x284)
+#define CPU_WFI_EN_CLR (SPM_BASE + 0x288)
+#define SYSRAM_CON (SPM_BASE + 0x290)
+#define SYSROM_CON (SPM_BASE + 0x294)
+#define ROOT_CPUTOP_ADDR (SPM_BASE + 0x2A0)
+#define ROOT_CORE_ADDR (SPM_BASE + 0x2A4)
+#define SPM2SW_MAILBOX_0 (SPM_BASE + 0x2D0)
+#define SPM2SW_MAILBOX_1 (SPM_BASE + 0x2D4)
+#define SPM2SW_MAILBOX_2 (SPM_BASE + 0x2D8)
+#define SPM2SW_MAILBOX_3 (SPM_BASE + 0x2DC)
+#define SW2SPM_INT (SPM_BASE + 0x2E0)
+#define SW2SPM_INT_SET (SPM_BASE + 0x2E4)
+#define SW2SPM_INT_CLR (SPM_BASE + 0x2E8)
+#define SW2SPM_MAILBOX_0 (SPM_BASE + 0x2EC)
+#define SW2SPM_MAILBOX_1 (SPM_BASE + 0x2F0)
+#define SW2SPM_MAILBOX_2 (SPM_BASE + 0x2F4)
+#define SW2SPM_MAILBOX_3 (SPM_BASE + 0x2F8)
+#define SW2SPM_CFG (SPM_BASE + 0x2FC)
+/*******Register_NONCPU_MT*************************************************/
+#define MFG0_PWR_CON (SPM_BASE + 0x300)
+#define MFG1_PWR_CON (SPM_BASE + 0x304)
+#define MFG2_PWR_CON (SPM_BASE + 0x308)
+#define MFG3_PWR_CON (SPM_BASE + 0x30C)
+#define MFG4_PWR_CON (SPM_BASE + 0x310)
+#define MFG5_PWR_CON (SPM_BASE + 0x314)
+#define MFG6_PWR_CON (SPM_BASE + 0x318)
+#define IFR_PWR_CON (SPM_BASE + 0x31C)
+#define IFR_SUB_PWR_CON (SPM_BASE + 0x320)
+#define PERI_PWR_CON (SPM_BASE + 0x324)
+#define PEXTP_MAC_TOP_P0_PWR_CON (SPM_BASE + 0x328)
+#define PEXTP_MAC_TOP_P1_PWR_CON (SPM_BASE + 0x32C)
+#define PCIE_PHY_PWR_CON (SPM_BASE + 0x330)
+#define SSUSB_PCIE_PHY_PWR_CON (SPM_BASE + 0x334)
+#define SSUSB_TOP_P1_PWR_CON (SPM_BASE + 0x338)
+#define SSUSB_TOP_P2_PWR_CON (SPM_BASE + 0x33C)
+#define SSUSB_TOP_P3_PWR_CON (SPM_BASE + 0x340)
+#define ETHER_PWR_CON (SPM_BASE + 0x344)
+#define DPY0_PWR_CON (SPM_BASE + 0x348)
+#define DPY1_PWR_CON (SPM_BASE + 0x34C)
+#define DPM0_PWR_CON (SPM_BASE + 0x350)
+#define DPM1_PWR_CON (SPM_BASE + 0x354)
+#define AUDIO_PWR_CON (SPM_BASE + 0x358)
+#define AUDIO_ASRC_PWR_CON (SPM_BASE + 0x35C)
+#define ADSP_PWR_CON (SPM_BASE + 0x360)
+#define VPPSYS0_PWR_CON (SPM_BASE + 0x364)
+#define VPPSYS1_PWR_CON (SPM_BASE + 0x368)
+#define VDOSYS0_PWR_CON (SPM_BASE + 0x36C)
+#define VDOSYS1_PWR_CON (SPM_BASE + 0x370)
+#define WPESYS_PWR_CON (SPM_BASE + 0x374)
+#define DP_TX_PWR_CON (SPM_BASE + 0x378)
+#define EDP_TX_PWR_CON (SPM_BASE + 0x37C)
+#define HDMI_TX_PWR_CON (SPM_BASE + 0x380)
+#define HDMI_RX_PWR_CON (SPM_BASE + 0x384)
+#define VDE0_PWR_CON (SPM_BASE + 0x388)
+#define VDE1_PWR_CON (SPM_BASE + 0x38C)
+#define VDE2_PWR_CON (SPM_BASE + 0x390)
+#define VEN_PWR_CON (SPM_BASE + 0x394)
+#define VEN_CORE1_PWR_CON (SPM_BASE + 0x398)
+#define CAM_PWR_CON (SPM_BASE + 0x39C)
+#define CAM_RAWA_PWR_CON (SPM_BASE + 0x3A0)
+#define CAM_RAWB_PWR_CON (SPM_BASE + 0x3A4)
+#define CAM_RAWC_PWR_CON (SPM_BASE + 0x3A8)
+#define IMG_M_PWR_CON (SPM_BASE + 0x3AC)
+#define IMG_D_PWR_CON (SPM_BASE + 0x3B0)
+#define IPE_PWR_CON (SPM_BASE + 0x3B4)
+#define NNA0_PWR_CON (SPM_BASE + 0x3B8)
+#define NNA1_PWR_CON (SPM_BASE + 0x3BC)
+#define IPNNA_PWR_CON (SPM_BASE + 0x3C0)
+#define CSI_RX_TOP_PWR_CON (SPM_BASE + 0x3C4)
+#define SSPM_SRAM_CON (SPM_BASE + 0x3C4)
+#define SCP_SRAM_CON (SPM_BASE + 0x3D0)
+#define UFS_SRAM_CON (SPM_BASE + 0x3D4)
+#define DEVAPC_IFR_SRAM_CON (SPM_BASE + 0x3D8)
+#define DEVAPC_SUBIFR_SRAM_CON (SPM_BASE + 0x3DC)
+#define DEVAPC_ACP_SRAM_CON (SPM_BASE + 0x3E0)
+#define USB_SRAM_CON (SPM_BASE + 0x3E4)
+#define DUMMY_SRAM_CO (SPM_BASE + 0x3E8)
+#define EXT_BUCK_ISO (SPM_BASE + 0x3EC)
+#define MSDC_SRAM_CON (SPM_BASE + 0x3F0)
+#define DEBUGTOP_SRAM (SPM_BASE + 0x3F4)
+#define DPMAIF_SRAM_C (SPM_BASE + 0x3F8)
+#define GCPU_SRAM_CON (SPM_BASE + 0x3FC)
+/*******Register_DIRC_IF*************************************************/
+#define SPM_MEM_CK_SEL (SPM_BASE + 0x400)
+#define SPM_BUS_PROTECT_MASK_B (SPM_BASE + 0x404)
+#define SPM_BUS_PROTECT1_MASK_B (SPM_BASE + 0x408)
+#define SPM_BUS_PROTECT2_MASK_B (SPM_BASE + 0x40C)
+#define SPM_BUS_PROTECT3_MASK_B (SPM_BASE + 0x410)
+#define SPM_BUS_PROTECT4_MASK_B (SPM_BASE + 0x414)
+#define SPM_BUS_PROTECT5_MASK_B (SPM_BASE + 0x418)
+#define SPM_BUS_PROTECT6_MASK_B (SPM_BASE + 0x41C)
+#define SPM_BUS_PROTECT7_MASK_B (SPM_BASE + 0x420)
+#define SPM_BUS_PROTECT8_MASK_B (SPM_BASE + 0x424)
+#define SPM_BUS_PROTECT9_MASK_B (SPM_BASE + 0x428)
+#define SPM_EMI_BW_MODE (SPM_BASE + 0x42C)
+#define SPM2MM_CON (SPM_BASE + 0x434)
+#define SPM2CPUEB_CON (SPM_BASE + 0x438)
+#define AP_MDSRC_REQ (SPM_BASE + 0x43C)
+#define SPM2EMI_ENTER_ULPM (SPM_BASE + 0x440)
+#define SPM_PLL_CON (SPM_BASE + 0x444)
+#define RC_SPM_CTRL (SPM_BASE + 0x448)
+#define SPM_DRAM_MCU_SW_CON_0 (SPM_BASE + 0x44C)
+#define SPM_DRAM_MCU_SW_CON_1 (SPM_BASE + 0x450)
+#define SPM_DRAM_MCU_SW_CON_2 (SPM_BASE + 0x454)
+#define SPM_DRAM_MCU_SW_CON_3 (SPM_BASE + 0x458)
+#define SPM_DRAM_MCU_SW_CON_4 (SPM_BASE + 0x45C)
+#define SPM_DRAM_MCU_STA_0 (SPM_BASE + 0x460)
+#define SPM_DRAM_MCU_STA_1 (SPM_BASE + 0x464)
+#define SPM_DRAM_MCU_STA_2 (SPM_BASE + 0x468)
+#define SPM_DRAM_MCU_SW_SEL_0 (SPM_BASE + 0x46C)
+#define RELAY_DVFS_LEVEL (SPM_BASE + 0x470)
+#define DRAMC_DPY_CLK_SW_CON_0 (SPM_BASE + 0x474)
+#define DRAMC_DPY_CLK_SW_CON_1 (SPM_BASE + 0x478)
+#define DRAMC_DPY_CLK_SW_CON_2 (SPM_BASE + 0x47C)
+#define DRAMC_DPY_CLK_SW_CON_3 (SPM_BASE + 0x480)
+#define DRAMC_DPY_CLK_SW_SEL_0 (SPM_BASE + 0x484)
+#define DRAMC_DPY_CLK_SW_SEL_1 (SPM_BASE + 0x488)
+#define DRAMC_DPY_CLK_SW_SEL_2 (SPM_BASE + 0x48C)
+#define DRAMC_DPY_CLK_SW_SEL_3 (SPM_BASE + 0x490)
+#define DRAMC_DPY_CLK_SPM_CON (SPM_BASE + 0x494)
+#define SPM_DVFS_LEVEL (SPM_BASE + 0x498)
+#define SPM_CIRQ_CON (SPM_BASE + 0x49C)
+#define SPM_DVFS_MISC (SPM_BASE + 0x4A0)
+#define RG_MODULE_SW_CG_0_MASK_REQ_0 (SPM_BASE + 0x4A4)
+#define RG_MODULE_SW_CG_0_MASK_REQ_1 (SPM_BASE + 0x4A8)
+#define RG_MODULE_SW_CG_0_MASK_REQ_2 (SPM_BASE + 0x4AC)
+#define RG_MODULE_SW_CG_1_MASK_REQ_0 (SPM_BASE + 0x4B0)
+#define RG_MODULE_SW_CG_1_MASK_REQ_1 (SPM_BASE + 0x4B4)
+#define RG_MODULE_SW_CG_1_MASK_REQ_2 (SPM_BASE + 0x4B8)
+#define RG_MODULE_SW_CG_2_MASK_REQ_0 (SPM_BASE + 0x4BC)
+#define RG_MODULE_SW_CG_2_MASK_REQ_1 (SPM_BASE + 0x4C0)
+#define RG_MODULE_SW_CG_2_MASK_REQ_2 (SPM_BASE + 0x4C4)
+#define RG_MODULE_SW_CG_3_MASK_REQ_0 (SPM_BASE + 0x4C8)
+#define RG_MODULE_SW_CG_3_MASK_REQ_1 (SPM_BASE + 0x4CC)
+#define RG_MODULE_SW_CG_3_MASK_REQ_2 (SPM_BASE + 0x4D0)
+#define PWR_STATUS_MASK_REQ_0 (SPM_BASE + 0x4D4)
+#define PWR_STATUS_MASK_REQ_1 (SPM_BASE + 0x4D8)
+#define PWR_STATUS_MASK_REQ_2 (SPM_BASE + 0x4DC)
+#define SPM_CG_CHECK_CON (SPM_BASE + 0x4E0)
+#define SPM_SRC_RDY_STA (SPM_BASE + 0x4E4)
+#define SPM_DVS_DFS_LEVEL (SPM_BASE + 0x4E8)
+#define SPM_FORCE_DVFS (SPM_BASE + 0x4EC)
+#define DRAMC_MCU_SRAM_CON (SPM_BASE + 0x4F0)
+#define DRAMC_MCU2_SRAM_CON (SPM_BASE + 0x4F4)
+#define DPY_SHU_SRAM_CON (SPM_BASE + 0x4F8)
+#define DPY_SHU2_SRAM_CON (SPM_BASE + 0x4FC)
+/*******The Others*************************************************/
+#define SRCLKEN_RC_CFG (SPM_BASE + 0x500)
+#define RC_CENTRAL_CFG1 (SPM_BASE + 0x504)
+#define RC_CENTRAL_CFG2 (SPM_BASE + 0x508)
+#define RC_CMD_ARB_CFG (SPM_BASE + 0x50C)
+#define RC_PMIC_RCEN_ADDR (SPM_BASE + 0x510)
+#define RC_PMIC_RCEN_SET_CLR_ADDR (SPM_BASE + 0x514)
+#define RC_DCXO_FPM_CFG (SPM_BASE + 0x518)
+#define RC_CENTRAL_CFG3 (SPM_BASE + 0x51C)
+#define RC_M00_SRCLKEN_CFG (SPM_BASE + 0x520)
+#define RC_M01_SRCLKEN_CFG (SPM_BASE + 0x524)
+#define RC_M02_SRCLKEN_CFG (SPM_BASE + 0x528)
+#define RC_M03_SRCLKEN_CFG (SPM_BASE + 0x52C)
+#define RC_M04_SRCLKEN_CFG (SPM_BASE + 0x530)
+#define RC_M05_SRCLKEN_CFG (SPM_BASE + 0x534)
+#define RC_M06_SRCLKEN_CFG (SPM_BASE + 0x538)
+#define RC_M07_SRCLKEN_CFG (SPM_BASE + 0x53C)
+#define RC_M08_SRCLKEN_CFG (SPM_BASE + 0x540)
+#define RC_M09_SRCLKEN_CFG (SPM_BASE + 0x544)
+#define RC_M10_SRCLKEN_CFG (SPM_BASE + 0x548)
+#define RC_M11_SRCLKEN_CFG (SPM_BASE + 0x54C)
+#define RC_M12_SRCLKEN_CFG (SPM_BASE + 0x550)
+#define RC_SRCLKEN_SW_CON_CFG (SPM_BASE + 0x554)
+#define RC_CENTRAL_CFG4 (SPM_BASE + 0x558)
+#define RC_PROTOCOL_CHK_CFG (SPM_BASE + 0x560)
+#define RC_DEBUG_CFG (SPM_BASE + 0x564)
+#define RC_MISC_0 (SPM_BASE + 0x5B4)
+
+#define SUBSYS_INTF_CFG (SPM_BASE + 0x5BC)
+#define PCM_WDT_LATCH_25 (SPM_BASE + 0x5C0)
+#define PCM_WDT_LATCH_26 (SPM_BASE + 0x5C4)
+#define PCM_WDT_LATCH_27 (SPM_BASE + 0x5C8)
+#define PCM_WDT_LATCH_28 (SPM_BASE + 0x5CC)
+#define PCM_WDT_LATCH_29 (SPM_BASE + 0x5D0)
+#define PCM_WDT_LATCH_30 (SPM_BASE + 0x5D4)
+#define PCM_WDT_LATCH_31 (SPM_BASE + 0x5D8)
+#define PCM_WDT_LATCH_32 (SPM_BASE + 0x5DC)
+#define PCM_WDT_LATCH_33 (SPM_BASE + 0x5E0)
+#define PCM_WDT_LATCH_34 (SPM_BASE + 0x5E4)
+#define PCM_WDT_LATCH_35 (SPM_BASE + 0x5EC)
+#define PCM_WDT_LATCH_36 (SPM_BASE + 0x5F0)
+#define PCM_WDT_LATCH_37 (SPM_BASE + 0x5F4)
+#define PCM_WDT_LATCH_38 (SPM_BASE + 0x5F8)
+#define PCM_WDT_LATCH_39 (SPM_BASE + 0x5FC)
+/*******Register_RSV*************************************************/
+#define SPM_SW_FLAG_0 (SPM_BASE + 0x600)
+#define SPM_SW_DEBUG_0 (SPM_BASE + 0x604)
+#define SPM_SW_FLAG_1 (SPM_BASE + 0x608)
+#define SPM_SW_DEBUG_1 (SPM_BASE + 0x60C)
+#define SPM_SW_RSV_0 (SPM_BASE + 0x610)
+#define SPM_SW_RSV_1 (SPM_BASE + 0x614)
+#define SPM_SW_RSV_2 (SPM_BASE + 0x618)
+#define SPM_SW_RSV_3 (SPM_BASE + 0x61C)
+#define SPM_SW_RSV_4 (SPM_BASE + 0x620)
+#define SPM_SW_RSV_5 (SPM_BASE + 0x624)
+#define SPM_SW_RSV_6 (SPM_BASE + 0x628)
+#define SPM_SW_RSV_7 (SPM_BASE + 0x62C)
+#define SPM_SW_RSV_8 (SPM_BASE + 0x630)
+#define SPM_BK_WAKE_EVENT (SPM_BASE + 0x634)
+#define SPM_BK_VTCXO_DUR (SPM_BASE + 0x638)
+#define SPM_BK_WAKE_MISC (SPM_BASE + 0x63C)
+#define SPM_BK_PCM_TIMER (SPM_BASE + 0x640)
+#define ULPOSC_CON (SPM_BASE + 0x644)
+#define SPM_RSV_CON_0 (SPM_BASE + 0x650)
+#define SPM_RSV_CON_1 (SPM_BASE + 0x654)
+#define SPM_RSV_STA_0 (SPM_BASE + 0x658)
+#define SPM_RSV_STA_1 (SPM_BASE + 0x65C)
+#define SPM_SPARE_CON (SPM_BASE + 0x660)
+#define SPM_SPARE_CON_SET (SPM_BASE + 0x664)
+#define SPM_SPARE_CON_CLR (SPM_BASE + 0x668)
+#define SPM_CROSS_WAKE_M00_REQ (SPM_BASE + 0x66C)
+#define SPM_CROSS_WAKE_M01_REQ (SPM_BASE + 0x670)
+#define SPM_CROSS_WAKE_M02_REQ (SPM_BASE + 0x674)
+#define SPM_CROSS_WAKE_M03_REQ (SPM_BASE + 0x678)
+#define SCP_VCORE_LEVEL (SPM_BASE + 0x67C)
+#define SC_MM_CK_SEL_CON (SPM_BASE + 0x680)
+#define SPARE_ACK_MASK (SPM_BASE + 0x684)
+#define SPM_DV_CON_0 (SPM_BASE + 0x68C)
+#define SPM_DV_CON_1 (SPM_BASE + 0x690)
+#define SPM_DV_STA (SPM_BASE + 0x694)
+#define CONN_XOWCN_DEBUG_EN (SPM_BASE + 0x698)
+#define SPM_SEMA_M0 (SPM_BASE + 0x69C)
+#define SPM_SEMA_M1 (SPM_BASE + 0x6A0)
+#define SPM_SEMA_M2 (SPM_BASE + 0x6A4)
+#define SPM_SEMA_M3 (SPM_BASE + 0x6A8)
+#define SPM_SEMA_M4 (SPM_BASE + 0x6AC)
+#define SPM_SEMA_M5 (SPM_BASE + 0x6B0)
+#define SPM_SEMA_M6 (SPM_BASE + 0x6B4)
+#define SPM_SEMA_M7 (SPM_BASE + 0x6B8)
+#define SPM2ADSP_MAILBOX (SPM_BASE + 0x6BC)
+#define ADSP2SPM_MAILBOX (SPM_BASE + 0x6C0)
+#define SPM_ADSP_IRQ (SPM_BASE + 0x6C4)
+#define SPM_MD32_IRQ (SPM_BASE + 0x6C8)
+#define SPM2PMCU_MAILBOX_0 (SPM_BASE + 0x6CC)
+#define SPM2PMCU_MAILBOX_1 (SPM_BASE + 0x6D0)
+#define SPM2PMCU_MAILBOX_2 (SPM_BASE + 0x6D4)
+#define SPM2PMCU_MAILBOX_3 (SPM_BASE + 0x6D8)
+#define PMCU2SPM_MAILBOX_0 (SPM_BASE + 0x6DC)
+#define PMCU2SPM_MAILBOX_1 (SPM_BASE + 0x6E0)
+#define PMCU2SPM_MAILBOX_2 (SPM_BASE + 0x6E4)
+#define PMCU2SPM_MAILBOX_3 (SPM_BASE + 0x6E8)
+#define UFS_PSRI_SW (SPM_BASE + 0x6EC)
+#define UFS_PSRI_SW_SET (SPM_BASE + 0x6F0)
+#define UFS_PSRI_SW_CLR (SPM_BASE + 0x6F4)
+#define SPM_AP_SEMA (SPM_BASE + 0x6F8)
+#define SPM_SPM_SEMA (SPM_BASE + 0x6FC)
+/*******Register_DVFS_TAB*************************************************/
+#define SPM_DVFS_CON (SPM_BASE + 0x700)
+#define SPM_DVFS_CON_STA (SPM_BASE + 0x704)
+#define SPM_PMIC_SPMI_CON (SPM_BASE + 0x708)
+#define SPM_DVFS_CMD0 (SPM_BASE + 0x710)
+#define SPM_DVFS_CMD1 (SPM_BASE + 0x714)
+#define SPM_DVFS_CMD2 (SPM_BASE + 0x718)
+#define SPM_DVFS_CMD3 (SPM_BASE + 0x71C)
+#define SPM_DVFS_CMD4 (SPM_BASE + 0x720)
+#define SPM_DVFS_CMD5 (SPM_BASE + 0x724)
+#define SPM_DVFS_CMD6 (SPM_BASE + 0x728)
+#define SPM_DVFS_CMD7 (SPM_BASE + 0x72C)
+#define SPM_DVFS_CMD8 (SPM_BASE + 0x730)
+#define SPM_DVFS_CMD9 (SPM_BASE + 0x734)
+#define SPM_DVFS_CMD10 (SPM_BASE + 0x738)
+#define SPM_DVFS_CMD11 (SPM_BASE + 0x73C)
+#define SPM_DVFS_CMD12 (SPM_BASE + 0x740)
+#define SPM_DVFS_CMD13 (SPM_BASE + 0x744)
+#define SPM_DVFS_CMD14 (SPM_BASE + 0x748)
+#define SPM_DVFS_CMD15 (SPM_BASE + 0x74C)
+#define SPM_DVFS_CMD16 (SPM_BASE + 0x750)
+#define SPM_DVFS_CMD17 (SPM_BASE + 0x754)
+#define SPM_DVFS_CMD18 (SPM_BASE + 0x758)
+#define SPM_DVFS_CMD19 (SPM_BASE + 0x75C)
+#define SPM_DVFS_CMD20 (SPM_BASE + 0x760)
+#define SPM_DVFS_CMD21 (SPM_BASE + 0x764)
+#define SPM_DVFS_CMD22 (SPM_BASE + 0x768)
+#define SPM_DVFS_CMD23 (SPM_BASE + 0x76C)
+#define SYS_TIMER_VALUE_L (SPM_BASE + 0x770)
+#define SYS_TIMER_VALUE_H (SPM_BASE + 0x774)
+#define SYS_TIMER_START_L (SPM_BASE + 0x778)
+#define SYS_TIMER_START_H (SPM_BASE + 0x77C)
+#define SYS_TIMER_LATCH_L_00 (SPM_BASE + 0x780)
+#define SYS_TIMER_LATCH_H_00 (SPM_BASE + 0x784)
+#define SYS_TIMER_LATCH_L_01 (SPM_BASE + 0x788)
+#define SYS_TIMER_LATCH_H_01 (SPM_BASE + 0x78C)
+#define SYS_TIMER_LATCH_L_02 (SPM_BASE + 0x790)
+#define SYS_TIMER_LATCH_H_02 (SPM_BASE + 0x794)
+#define SYS_TIMER_LATCH_L_03 (SPM_BASE + 0x798)
+#define SYS_TIMER_LATCH_H_03 (SPM_BASE + 0x79C)
+#define SYS_TIMER_LATCH_L_04 (SPM_BASE + 0x7A0)
+#define SYS_TIMER_LATCH_H_04 (SPM_BASE + 0x7A4)
+#define SYS_TIMER_LATCH_L_05 (SPM_BASE + 0x7A8)
+#define SYS_TIMER_LATCH_H_05 (SPM_BASE + 0x7AC)
+#define SYS_TIMER_LATCH_L_06 (SPM_BASE + 0x7B0)
+#define SYS_TIMER_LATCH_H_06 (SPM_BASE + 0x7B4)
+#define SYS_TIMER_LATCH_L_07 (SPM_BASE + 0x7B8)
+#define SYS_TIMER_LATCH_H_07 (SPM_BASE + 0x7BC)
+#define SYS_TIMER_LATCH_L_08 (SPM_BASE + 0x7C0)
+#define SYS_TIMER_LATCH_H_08 (SPM_BASE + 0x7C4)
+#define SYS_TIMER_LATCH_L_09 (SPM_BASE + 0x7C8)
+#define SYS_TIMER_LATCH_H_09 (SPM_BASE + 0x7CC)
+#define SYS_TIMER_LATCH_L_10 (SPM_BASE + 0x7D0)
+#define SYS_TIMER_LATCH_H_10 (SPM_BASE + 0x7D4)
+#define SYS_TIMER_LATCH_L_11 (SPM_BASE + 0x7D8)
+#define SYS_TIMER_LATCH_H_11 (SPM_BASE + 0x7DC)
+#define SYS_TIMER_LATCH_L_12 (SPM_BASE + 0x7E0)
+#define SYS_TIMER_LATCH_H_12 (SPM_BASE + 0x7E4)
+#define SYS_TIMER_LATCH_L_13 (SPM_BASE + 0x7E8)
+#define SYS_TIMER_LATCH_H_13 (SPM_BASE + 0x7EC)
+#define SYS_TIMER_LATCH_L_14 (SPM_BASE + 0x7F0)
+#define SYS_TIMER_LATCH_H_14 (SPM_BASE + 0x7F4)
+#define SYS_TIMER_LATCH_L_15 (SPM_BASE + 0x7F8)
+#define SYS_TIMER_LATCH_H_15 (SPM_BASE + 0x7FC)
+/*******Register_LAT_STA*************************************************/
+#define PCM_WDT_LATCH_0 (SPM_BASE + 0x800)
+#define PCM_WDT_LATCH_1 (SPM_BASE + 0x804)
+#define PCM_WDT_LATCH_2 (SPM_BASE + 0x808)
+#define PCM_WDT_LATCH_3 (SPM_BASE + 0x80C)
+#define PCM_WDT_LATCH_4 (SPM_BASE + 0x810)
+#define PCM_WDT_LATCH_5 (SPM_BASE + 0x814)
+#define PCM_WDT_LATCH_6 (SPM_BASE + 0x818)
+#define PCM_WDT_LATCH_7 (SPM_BASE + 0x81C)
+#define PCM_WDT_LATCH_8 (SPM_BASE + 0x820)
+#define PCM_WDT_LATCH_9 (SPM_BASE + 0x824)
+#define PCM_WDT_LATCH_10 (SPM_BASE + 0x828)
+#define PCM_WDT_LATCH_11 (SPM_BASE + 0x82C)
+#define PCM_WDT_LATCH_12 (SPM_BASE + 0x830)
+#define PCM_WDT_LATCH_13 (SPM_BASE + 0x834)
+#define PCM_WDT_LATCH_14 (SPM_BASE + 0x838)
+#define PCM_WDT_LATCH_15 (SPM_BASE + 0x83C)
+#define PCM_WDT_LATCH_16 (SPM_BASE + 0x840)
+#define PCM_WDT_LATCH_17 (SPM_BASE + 0x844)
+#define PCM_WDT_LATCH_18 (SPM_BASE + 0x848)
+#define PCM_WDT_LATCH_SPARE_0 (SPM_BASE + 0x84C)
+#define PCM_WDT_LATCH_SPARE_1 (SPM_BASE + 0x850)
+#define PCM_WDT_LATCH_SPARE_2 (SPM_BASE + 0x854)
+#define PCM_WDT_LATCH_CONN_0 (SPM_BASE + 0x870)
+#define PCM_WDT_LATCH_CONN_1 (SPM_BASE + 0x874)
+#define PCM_WDT_LATCH_CONN_2 (SPM_BASE + 0x878)
+#define DRAMC_GATING_ERR_LATCH_CH0_0 (SPM_BASE + 0x8A0)
+#define DRAMC_GATING_ERR_LATCH_CH0_1 (SPM_BASE + 0x8A4)
+#define DRAMC_GATING_ERR_LATCH_CH0_2 (SPM_BASE + 0x8A8)
+#define DRAMC_GATING_ERR_LATCH_CH0_3 (SPM_BASE + 0x8AC)
+#define DRAMC_GATING_ERR_LATCH_CH0_4 (SPM_BASE + 0x8B0)
+#define DRAMC_GATING_ERR_LATCH_CH0_5 (SPM_BASE + 0x8B4)
+#define DRAMC_GATING_ERR_LATCH_CH0_6 (SPM_BASE + 0x8B8)
+#define DRAMC_GATING_ERR_LATCH_SPARE_0 (SPM_BASE + 0x8F4)
+/*******Register_SPM_ACK_CHK*************************************************/
+#define SPM_ACK_CHK_CON_0 (SPM_BASE + 0x900)
+#define SPM_ACK_CHK_PC_0 (SPM_BASE + 0x904)
+#define SPM_ACK_CHK_SEL_0 (SPM_BASE + 0x908)
+#define SPM_ACK_CHK_TIMER_0 (SPM_BASE + 0x90C)
+#define SPM_ACK_CHK_STA_0 (SPM_BASE + 0x910)
+#define SPM_ACK_CHK_SWINT_0 (SPM_BASE + 0x914)
+#define SPM_ACK_CHK_CON_1 (SPM_BASE + 0x920)
+#define SPM_ACK_CHK_PC_1 (SPM_BASE + 0x924)
+#define SPM_ACK_CHK_SEL_1 (SPM_BASE + 0x928)
+#define SPM_ACK_CHK_TIMER_1 (SPM_BASE + 0x92C)
+#define SPM_ACK_CHK_STA_1 (SPM_BASE + 0x930)
+#define SPM_ACK_CHK_SWINT_1 (SPM_BASE + 0x934)
+#define SPM_ACK_CHK_CON_2 (SPM_BASE + 0x940)
+#define SPM_ACK_CHK_PC_2 (SPM_BASE + 0x944)
+#define SPM_ACK_CHK_SEL_2 (SPM_BASE + 0x948)
+#define SPM_ACK_CHK_TIMER_2 (SPM_BASE + 0x94C)
+#define SPM_ACK_CHK_STA_2 (SPM_BASE + 0x950)
+#define SPM_ACK_CHK_SWINT_2 (SPM_BASE + 0x954)
+#define SPM_ACK_CHK_CON_3 (SPM_BASE + 0x960)
+#define SPM_ACK_CHK_PC_3 (SPM_BASE + 0x964)
+#define SPM_ACK_CHK_SEL_3 (SPM_BASE + 0x968)
+#define SPM_ACK_CHK_TIMER_3 (SPM_BASE + 0x96C)
+#define SPM_ACK_CHK_STA_3 (SPM_BASE + 0x970)
+#define SPM_ACK_CHK_SWINT_3 (SPM_BASE + 0x974)
+#define SPM_COUNTER_0 (SPM_BASE + 0x978)
+#define SPM_COUNTER_1 (SPM_BASE + 0x97C)
+#define SPM_COUNTER_2 (SPM_BASE + 0x980)
+#define SYS_TIMER_CON (SPM_BASE + 0x98C)
+#define SPM_TWAM_CON (SPM_BASE + 0x990)
+#define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x994)
+#define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x998)
+#define SPM_TWAM_EVENT_CLEAR (SPM_BASE + 0x99C)
+/*******The OTHERS*************************************************/
+#define RC_FSM_STA_0 (SPM_BASE + 0xE00)
+#define RC_CMD_STA_0 (SPM_BASE + 0xE04)
+#define RC_CMD_STA_1 (SPM_BASE + 0xE08)
+#define RC_SPI_STA_0 (SPM_BASE + 0xE0C)
+#define RC_PI_PO_STA_0 (SPM_BASE + 0xE10)
+#define RC_M00_REQ_STA_0 (SPM_BASE + 0xE14)
+#define RC_M01_REQ_STA_0 (SPM_BASE + 0xE1C)
+#define RC_M02_REQ_STA_0 (SPM_BASE + 0xE20)
+#define RC_M03_REQ_STA_0 (SPM_BASE + 0xE24)
+#define RC_M04_REQ_STA_0 (SPM_BASE + 0xE28)
+#define RC_M05_REQ_STA_0 (SPM_BASE + 0xE2C)
+#define RC_M06_REQ_STA_0 (SPM_BASE + 0xE30)
+#define RC_M07_REQ_STA_0 (SPM_BASE + 0xE34)
+#define RC_M08_REQ_STA_0 (SPM_BASE + 0xE38)
+#define RC_M09_REQ_STA_0 (SPM_BASE + 0xE3C)
+#define RC_M10_REQ_STA_0 (SPM_BASE + 0xE40)
+#define RC_M11_REQ_STA_0 (SPM_BASE + 0xE44)
+#define RC_M12_REQ_STA_0 (SPM_BASE + 0xE48)
+#define RC_DEBUG_STA_0 (SPM_BASE + 0xE4C)
+#define RC_DEBUG_TRACE_0_LSB (SPM_BASE + 0xE50)
+#define RC_DEBUG_TRACE_0_MSB (SPM_BASE + 0xE54)
+#define RC_DEBUG_TRACE_1_LSB (SPM_BASE + 0xE5C)
+#define RC_DEBUG_TRACE_1_MSB (SPM_BASE + 0xE60)
+#define RC_DEBUG_TRACE_2_LSB (SPM_BASE + 0xE64)
+#define RC_DEBUG_TRACE_2_MSB (SPM_BASE + 0xE6C)
+#define RC_DEBUG_TRACE_3_LSB (SPM_BASE + 0xE70)
+#define RC_DEBUG_TRACE_3_MSB (SPM_BASE + 0xE74)
+#define RC_DEBUG_TRACE_4_LSB (SPM_BASE + 0xE78)
+#define RC_DEBUG_TRACE_4_MSB (SPM_BASE + 0xE7C)
+#define RC_DEBUG_TRACE_5_LSB (SPM_BASE + 0xE80)
+#define RC_DEBUG_TRACE_5_MSB (SPM_BASE + 0xE84)
+#define RC_DEBUG_TRACE_6_LSB (SPM_BASE + 0xE88)
+#define RC_DEBUG_TRACE_6_MSB (SPM_BASE + 0xE8C)
+#define RC_DEBUG_TRACE_7_LSB (SPM_BASE + 0xE90)
+#define RC_DEBUG_TRACE_7_MSB (SPM_BASE + 0xE94)
+#define RC_SYS_TIMER_LATCH_0_LSB (SPM_BASE + 0xE98)
+#define RC_SYS_TIMER_LATCH_0_MSB (SPM_BASE + 0xE9C)
+#define RC_SYS_TIMER_LATCH_1_LSB (SPM_BASE + 0xEA0)
+#define RC_SYS_TIMER_LATCH_1_MSB (SPM_BASE + 0xEA4)
+#define RC_SYS_TIMER_LATCH_2_LSB (SPM_BASE + 0xEA8)
+#define RC_SYS_TIMER_LATCH_2_MSB (SPM_BASE + 0xEAC)
+#define RC_SYS_TIMER_LATCH_3_LSB (SPM_BASE + 0xEB0)
+#define RC_SYS_TIMER_LATCH_3_MSB (SPM_BASE + 0xEB4)
+#define RC_SYS_TIMER_LATCH_4_LSB (SPM_BASE + 0xEB8)
+#define RC_SYS_TIMER_LATCH_4_MSB (SPM_BASE + 0xEBC)
+#define RC_SYS_TIMER_LATCH_5_LSB (SPM_BASE + 0xEC0)
+#define RC_SYS_TIMER_LATCH_5_MSB (SPM_BASE + 0xEC4)
+#define RC_SYS_TIMER_LATCH_6_LSB (SPM_BASE + 0xEC8)
+#define RC_SYS_TIMER_LATCH_6_MSB (SPM_BASE + 0xECC)
+#define RC_SYS_TIMER_LATCH_7_LSB (SPM_BASE + 0xED0)
+#define RC_SYS_TIMER_LATCH_7_MSB (SPM_BASE + 0xED4)
+#define PCM_WDT_LATCH_19 (SPM_BASE + 0xED8)
+#define PCM_WDT_LATCH_20 (SPM_BASE + 0xEDC)
+#define PCM_WDT_LATCH_21 (SPM_BASE + 0xEE0)
+#define PCM_WDT_LATCH_22 (SPM_BASE + 0xEE4)
+#define PCM_WDT_LATCH_23 (SPM_BASE + 0xEE8)
+#define PCM_WDT_LATCH_24 (SPM_BASE + 0xEEC)
+/*******Register_PMSR*************************************************/
+#define PMSR_LAST_DAT (SPM_BASE + 0xF00)
+#define PMSR_LAST_CNT (SPM_BASE + 0xF04)
+#define PMSR_LAST_ACK (SPM_BASE + 0xF08)
+#define SPM_PMSR_SEL_CON0 (SPM_BASE + 0xF10)
+#define SPM_PMSR_SEL_CON1 (SPM_BASE + 0xF14)
+#define SPM_PMSR_SEL_CON2 (SPM_BASE + 0xF18)
+#define SPM_PMSR_SEL_CON3 (SPM_BASE + 0xF1C)
+#define SPM_PMSR_SEL_CON4 (SPM_BASE + 0xF20)
+#define SPM_PMSR_SEL_CON5 (SPM_BASE + 0xF24)
+#define SPM_PMSR_SEL_CON6 (SPM_BASE + 0xF28)
+#define SPM_PMSR_SEL_CON7 (SPM_BASE + 0xF2C)
+#define SPM_PMSR_SEL_CON8 (SPM_BASE + 0xF30)
+#define SPM_PMSR_SEL_CON9 (SPM_BASE + 0xF34)
+#define SPM_PMSR_SEL_CON10 (SPM_BASE + 0xF3C)
+#define SPM_PMSR_SEL_CON11 (SPM_BASE + 0xF40)
+#define SPM_PMSR_TIEMR_STA0 (SPM_BASE + 0xFB8)
+#define SPM_PMSR_TIEMR_STA1 (SPM_BASE + 0xFBC)
+#define SPM_PMSR_TIEMR_STA2 (SPM_BASE + 0xFC0)
+#define SPM_PMSR_GENERAL_CON0 (SPM_BASE + 0xFC4)
+#define SPM_PMSR_GENERAL_CON1 (SPM_BASE + 0xFC8)
+#define SPM_PMSR_GENERAL_CON2 (SPM_BASE + 0xFCC)
+#define SPM_PMSR_GENERAL_CON3 (SPM_BASE + 0xFD0)
+#define SPM_PMSR_GENERAL_CON4 (SPM_BASE + 0xFD4)
+#define SPM_PMSR_GENERAL_CON5 (SPM_BASE + 0xFD8)
+#define SPM_PMSR_SW_RESET (SPM_BASE + 0xFDC)
+#define SPM_PMSR_MON_CON0 (SPM_BASE + 0xFE0)
+#define SPM_PMSR_MON_CON1 (SPM_BASE + 0xFE4)
+#define SPM_PMSR_MON_CON2 (SPM_BASE + 0xFE8)
+#define SPM_PMSR_LEN_CON0 (SPM_BASE + 0xFEC)
+#define SPM_PMSR_LEN_CON1 (SPM_BASE + 0xFF0)
+#define SPM_PMSR_LEN_CON2 (SPM_BASE + 0xFF4)
+/*******Register End*************************************************/
+
+/* POWERON_CONFIG_EN (0x10006000+0x000) */
+#define BCLK_CG_EN_LSB (1U << 0) /* 1b */
+#define PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* SPM_POWER_ON_VAL0 (0x10006000+0x004) */
+#define POWER_ON_VAL0_LSB (1U << 0) /* 32b */
+/* SPM_POWER_ON_VAL1 (0x10006000+0x008) */
+#define POWER_ON_VAL1_LSB (1U << 0) /* 32b */
+/* SPM_CLK_CON (0x10006000+0x00C) */
+#define REG_SRCCLKEN0_CTL_LSB (1U << 0) /* 2b */
+#define REG_SRCCLKEN1_CTL_LSB (1U << 2) /* 2b */
+#define SYS_SETTLE_SEL_LSB (1U << 4) /* 1b */
+#define REG_SPM_LOCK_INFRA_DCM_LSB (1U << 5) /* 1b */
+#define REG_SRCCLKEN_MASK_LSB (1U << 6) /* 3b */
+#define REG_MD1_C32RM_EN_LSB (1U << 9) /* 1b */
+#define REG_MD2_C32RM_EN_LSB (1U << 10) /* 1b */
+#define REG_CLKSQ0_SEL_CTRL_LSB (1U << 11) /* 1b */
+#define REG_CLKSQ1_SEL_CTRL_LSB (1U << 12) /* 1b */
+#define REG_SRCCLKEN0_EN_LSB (1U << 13) /* 1b */
+#define REG_SRCCLKEN1_EN_LSB (1U << 14) /* 1b */
+#define SCP_DCM_EN_LSB (1U << 15) /* 1b */
+#define REG_SYSCLK0_SRC_MASK_B_LSB (1U << 16) /* 8b */
+#define REG_SYSCLK1_SRC_MASK_B_LSB (1U << 24) /* 8b */
+/* SPM_CLK_SETTLE (0x10006000+0x010) */
+#define SYSCLK_SETTLE_LSB (1U << 0) /* 28b */
+/* SPM_AP_STANDBY_CON (0x10006000+0x014) */
+#define REG_WFI_OP_LSB (1U << 0) /* 1b */
+#define REG_WFI_TYPE_LSB (1U << 1) /* 1b */
+#define REG_MP0_CPUTOP_IDLE_MASK_LSB (1U << 2) /* 1b */
+#define REG_MP1_CPUTOP_IDLE_MASK_LSB (1U << 3) /* 1b */
+#define REG_MCUSYS_IDLE_MASK_LSB (1U << 4) /* 1b */
+#define REG_MD_APSRC_1_SEL_LSB (1U << 25) /* 1b */
+#define REG_MD_APSRC_0_SEL_LSB (1U << 26) /* 1b */
+#define REG_CONN_APSRC_SEL_LSB (1U << 29) /* 1b */
+/* PCM_CON0 (0x10006000+0x018) */
+#define PCM_CK_EN_LSB (1U << 2) /* 1b */
+#define RG_EN_IM_SLEEP_DVS_LSB (1U << 3) /* 1b */
+#define PCM_CK_FROM_CKSYS_LSB (1U << 4) /* 1b */
+#define PCM_SW_RESET_LSB (1U << 15) /* 1b */
+#define PCM_CON0_PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* PCM_CON1 (0x10006000+0x01C) */
+#define RG_IM_SLAVE_LSB (1U << 0) /* 1b */
+#define RG_IM_SLEEP_LSB (1U << 1) /* 1b */
+#define REG_SPM_SRAM_CTRL_MUX_LSB (1U << 2) /* 1b */
+#define RG_AHBMIF_APBEN_LSB (1U << 3) /* 1b */
+#define RG_IM_PDN_LSB (1U << 4) /* 1b */
+#define RG_PCM_TIMER_EN_LSB (1U << 5) /* 1b */
+#define SPM_EVENT_COUNTER_CLR_LSB (1U << 6) /* 1b */
+#define RG_DIS_MIF_PROT_LSB (1U << 7) /* 1b */
+#define RG_PCM_WDT_EN_LSB (1U << 8) /* 1b */
+#define RG_PCM_WDT_WAKE_LSB (1U << 9) /* 1b */
+#define REG_SPM_SRAM_SLEEP_B_LSB (1U << 10) /* 1b */
+#define REG_SPM_SRAM_ISOINT_B_LSB (1U << 11) /* 1b */
+#define REG_EVENT_LOCK_EN_LSB (1U << 12) /* 1b */
+#define REG_SRCCLKEN_FAST_RESP_LSB (1U << 13) /* 1b */
+#define REG_MD32_APB_INTERNAL_EN_LSB (1U << 14) /* 1b */
+#define RG_PCM_IRQ_MSK_LSB (1U << 15) /* 1b */
+#define PCM_CON1_PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* SPM_POWER_ON_VAL2 (0x10006000+0x020) */
+#define POWER_ON_VAL2_LSB (1U << 0) /* 32b */
+/* SPM_POWER_ON_VAL3 (0x10006000+0x024) */
+#define POWER_ON_VAL3_LSB (1U << 0) /* 32b */
+/* PCM_REG_DATA_INI (0x10006000+0x028) */
+#define PCM_REG_DATA_INI_LSB (1U << 0) /* 32b */
+/* PCM_PWR_IO_EN (0x10006000+0x02C) */
+#define PCM_PWR_IO_EN_LSB (1U << 0) /* 8b */
+#define RG_RF_SYNC_EN_LSB (1U << 16) /* 8b */
+/* PCM_TIMER_VAL (0x10006000+0x030) */
+#define REG_PCM_TIMER_VAL_LSB (1U << 0) /* 32b */
+/* PCM_WDT_VAL (0x10006000+0x034) */
+#define RG_PCM_WDT_VAL_LSB (1U << 0) /* 32b */
+/* SPM_SW_RST_CON (0x10006000+0x040) */
+#define SPM_SW_RST_CON_LSB (1U << 0) /* 16b */
+#define SPM_SW_RST_CON_PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* SPM_SW_RST_CON_SET (0x10006000+0x044) */
+#define SPM_SW_RST_CON_SET_LSB (1U << 0) /* 16b */
+#define SPM_SW_RST_CON_SET_PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* SPM_SW_RST_CON_CLR (0x10006000+0x048) */
+#define SPM_SW_RST_CON_CLR_LSB (1U << 0) /* 16b */
+#define SPM_SW_RST_CON_CLR_PROJECT_CODE_LSB (1U << 16) /* 16b */
+/* VS1_PSR_MASK_B (0x10006000+0x04C) */
+#define VS1_OPP0_PSR_MASK_B_LSB (1U << 0) /* 8b */
+#define VS1_OPP1_PSR_MASK_B_LSB (1U << 8) /* 8b */
+/* VS2_PSR_MASK_B (0x10006000+0x050) */
+#define VS2_OPP0_PSR_MASK_B_LSB (1U << 0) /* 8b */
+#define VS2_OPP1_PSR_MASK_B_LSB (1U << 8) /* 8b */
+#define VS2_OPP2_PSR_MASK_B_LSB (1U << 16) /* 8b */
+/* MD32_CLK_CON (0x10006000+0x084) */
+#define REG_MD32_26M_CK_SEL_LSB (1U << 0) /* 1b */
+#define REG_MD32_DCM_EN_LSB (1U << 1) /* 1b */
+/* SPM_SRAM_RSV_CON (0x10006000+0x088) */
+#define SPM_SRAM_SLEEP_B_ECO_EN_LSB (1U << 0) /* 1b */
+/* SPM_SWINT (0x10006000+0x08C) */
+#define SPM_SWINT_LSB (1U << 0) /* 32b */
+/* SPM_SWINT_SET (0x10006000+0x090) */
+#define SPM_SWINT_SET_LSB (1U << 0) /* 32b */
+/* SPM_SWINT_CLR (0x10006000+0x094) */
+#define SPM_SWINT_CLR_LSB (1U << 0) /* 32b */
+/* SPM_SCP_MAILBOX (0x10006000+0x098) */
+#define SPM_SCP_MAILBOX_LSB (1U << 0) /* 32b */
+/* SCP_SPM_MAILBOX (0x10006000+0x09C) */
+#define SCP_SPM_MAILBOX_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CON (0x10006000+0x0A0) */
+#define REG_TWAM_ENABLE_LSB (1U << 0) /* 1b */
+#define REG_TWAM_SPEED_MODE_EN_LSB (1U << 1) /* 1b */
+#define REG_TWAM_SW_RST_LSB (1U << 2) /* 1b */
+#define REG_TWAM_IRQ_MASK_LSB (1U << 3) /* 1b */
+#define REG_TWAM_MON_TYPE_0_LSB (1U << 4) /* 2b */
+#define REG_TWAM_MON_TYPE_1_LSB (1U << 6) /* 2b */
+#define REG_TWAM_MON_TYPE_2_LSB (1U << 8) /* 2b */
+#define REG_TWAM_MON_TYPE_3_LSB (1U << 10) /* 2b */
+/* SPM_TWAM_WINDOW_LEN (0x10006000+0x0A4) */
+#define REG_TWAM_WINDOW_LEN_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_IDLE_SEL (0x10006000+0x0A8) */
+#define REG_TWAM_SIG_SEL_0_LSB (1U << 0) /* 7b */
+#define REG_TWAM_SIG_SEL_1_LSB (1U << 8) /* 7b */
+#define REG_TWAM_SIG_SEL_2_LSB (1U << 16) /* 7b */
+#define REG_TWAM_SIG_SEL_3_LSB (1U << 24) /* 7b */
+/* SPM_SCP_IRQ (0x10006000+0x0AC) */
+#define SC_SPM2SCP_WAKEUP_LSB (1U << 0) /* 1b */
+#define SC_SCP2SPM_WAKEUP_LSB (1U << 4) /* 1b */
+/* SPM_CPU_WAKEUP_EVENT (0x10006000+0x0B0) */
+#define REG_CPU_WAKEUP_LSB (1U << 0) /* 1b */
+/* SPM_IRQ_MASK (0x10006000+0x0B4) */
+#define REG_SPM_IRQ_MASK_LSB (1U << 0) /* 32b */
+/* DDR_EN_DBC (0x10006000+0x0B4) */
+#define REG_ALL_DDR_EN_DBC_EN_LSB (1U << 16) /* 1b */
+/* SPM_SRC_REQ (0x10006000+0x0B8) */
+#define REG_SPM_APSRC_REQ_LSB (1U << 0) /* 1b */
+#define REG_SPM_F26M_REQ_LSB (1U << 1) /* 1b */
+#define REG_SPM_INFRA_REQ_LSB (1U << 3) /* 1b */
+#define REG_SPM_VRF18_REQ_LSB (1U << 4) /* 1b */
+#define REG_SPM_DDR_EN_REQ_LSB (1U << 7) /* 1b */
+#define REG_SPM_DVFS_REQ_LSB (1U << 8) /* 1b */
+#define REG_SPM_SW_MAILBOX_REQ_LSB (1U << 9) /* 1b */
+#define REG_SPM_SSPM_MAILBOX_REQ_LSB (1U << 10) /* 1b */
+#define REG_SPM_ADSP_MAILBOX_REQ_LSB (1U << 11) /* 1b */
+#define REG_SPM_SCP_MAILBOX_REQ_LSB (1U << 12) /* 1b */
+/* SPM_SRC_MASK (0x10006000+0x0BC) */
+#define REG_MD_SRCCLKENA_0_MASK_B_LSB (1U << 0) /* 1b */
+#define REG_MD_SRCCLKENA2INFRA_REQ_0_MASK_B_LSB (1U << 1) /* 1b */
+#define REG_MD_APSRC2INFRA_REQ_0_MASK_B_LSB (1U << 2) /* 1b */
+#define REG_MD_APSRC_REQ_0_MASK_B_LSB (1U << 3) /* 1b */
+#define REG_MD_VRF18_REQ_0_MASK_B_LSB (1U << 4) /* 1b */
+#define REG_MD_DDR_EN_0_MASK_B_LSB (1U << 5) /* 1b */
+#define REG_MD_SRCCLKENA_1_MASK_B_LSB (1U << 6) /* 1b */
+#define REG_MD_SRCCLKENA2INFRA_REQ_1_MASK_B_LSB (1U << 7) /* 1b */
+#define REG_MD_APSRC2INFRA_REQ_1_MASK_B_LSB (1U << 8) /* 1b */
+#define REG_MD_APSRC_REQ_1_MASK_B_LSB (1U << 9) /* 1b */
+#define REG_MD_VRF18_REQ_1_MASK_B_LSB (1U << 10) /* 1b */
+#define REG_MD_DDR_EN_1_MASK_B_LSB (1U << 11) /* 1b */
+#define REG_CONN_SRCCLKENA_MASK_B_LSB (1U << 12) /* 1b */
+#define REG_CONN_SRCCLKENB_MASK_B_LSB (1U << 13) /* 1b */
+#define REG_CONN_INFRA_REQ_MASK_B_LSB (1U << 14) /* 1b */
+#define REG_CONN_APSRC_REQ_MASK_B_LSB (1U << 15) /* 1b */
+#define REG_CONN_VRF18_REQ_MASK_B_LSB (1U << 16) /* 1b */
+#define REG_CONN_DDR_EN_MASK_B_LSB (1U << 17) /* 1b */
+#define REG_CONN_VFE28_MASK_B_LSB (1U << 18) /* 1b */
+#define REG_SRCCLKENI0_SRCCLKENA_MASK_B_LSB (1U << 19) /* 1b */
+#define REG_SRCCLKENI0_INFRA_REQ_MASK_B_LSB (1U << 20) /* 1b */
+#define REG_SRCCLKENI1_SRCCLKENA_MASK_B_LSB (1U << 21) /* 1b */
+#define REG_SRCCLKENI1_INFRA_REQ_MASK_B_LSB (1U << 22) /* 1b */
+#define REG_SRCCLKENI2_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */
+#define REG_SRCCLKENI2_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */
+#define REG_INFRASYS_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */
+#define REG_INFRASYS_DDR_EN_MASK_B_LSB (1U << 26) /* 1b */
+#define REG_MD32_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */
+#define REG_MD32_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */
+#define REG_MD32_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */
+#define REG_MD32_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */
+#define REG_MD32_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */
+/* SPM_SRC2_MASK (0x10006000+0x0C0) */
+#define REG_SCP_SRCCLKENA_MASK_B_LSB (1U << 0) /* 1b */
+#define REG_SCP_INFRA_REQ_MASK_B_LSB (1U << 1) /* 1b */
+#define REG_SCP_APSRC_REQ_MASK_B_LSB (1U << 2) /* 1b */
+#define REG_SCP_VRF18_REQ_MASK_B_LSB (1U << 3) /* 1b */
+#define REG_SCP_DDR_EN_MASK_B_LSB (1U << 4) /* 1b */
+#define REG_AUDIO_DSP_SRCCLKENA_MASK_B_LSB (1U << 5) /* 1b */
+#define REG_AUDIO_DSP_INFRA_REQ_MASK_B_LSB (1U << 6) /* 1b */
+#define REG_AUDIO_DSP_APSRC_REQ_MASK_B_LSB (1U << 7) /* 1b */
+#define REG_AUDIO_DSP_VRF18_REQ_MASK_B_LSB (1U << 8) /* 1b */
+#define REG_AUDIO_DSP_DDR_EN_MASK_B_LSB (1U << 9) /* 1b */
+#define REG_UFS_SRCCLKENA_MASK_B_LSB (1U << 10) /* 1b */
+#define REG_UFS_INFRA_REQ_MASK_B_LSB (1U << 11) /* 1b */
+#define REG_UFS_APSRC_REQ_MASK_B_LSB (1U << 12) /* 1b */
+#define REG_UFS_VRF18_REQ_MASK_B_LSB (1U << 13) /* 1b */
+#define REG_UFS_DDR_EN_MASK_B_LSB (1U << 14) /* 1b */
+#define REG_DISP0_APSRC_REQ_MASK_B_LSB (1U << 15) /* 1b */
+#define REG_DISP0_DDR_EN_MASK_B_LSB (1U << 16) /* 1b */
+#define REG_DISP1_APSRC_REQ_MASK_B_LSB (1U << 17) /* 1b */
+#define REG_DISP1_DDR_EN_MASK_B_LSB (1U << 18) /* 1b */
+#define REG_GCE_INFRA_REQ_MASK_B_LSB (1U << 19) /* 1b */
+#define REG_GCE_APSRC_REQ_MASK_B_LSB (1U << 20) /* 1b */
+#define REG_GCE_VRF18_REQ_MASK_B_LSB (1U << 21) /* 1b */
+#define REG_GCE_DDR_EN_MASK_B_LSB (1U << 22) /* 1b */
+#define REG_APU_SRCCLKENA_MASK_B_LSB (1U << 23) /* 1b */
+#define REG_APU_INFRA_REQ_MASK_B_LSB (1U << 24) /* 1b */
+#define REG_APU_APSRC_REQ_MASK_B_LSB (1U << 25) /* 1b */
+#define REG_APU_VRF18_REQ_MASK_B_LSB (1U << 26) /* 1b */
+#define REG_APU_DDR_EN_MASK_B_LSB (1U << 27) /* 1b */
+#define REG_CG_CHECK_SRCCLKENA_MASK_B_LSB (1U << 28) /* 1b */
+#define REG_CG_CHECK_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */
+#define REG_CG_CHECK_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */
+#define REG_CG_CHECK_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */
+/* SPM_SRC3_MASK (0x10006000+0x0C4) */
+#define REG_DVFSRC_EVENT_TRIGGER_MASK_B_LSB (1U << 0) /* 1b */
+#define REG_SW2SPM_INT0_MASK_B_LSB (1U << 1) /* 1b */
+#define REG_SW2SPM_INT1_MASK_B_LSB (1U << 2) /* 1b */
+#define REG_SW2SPM_INT2_MASK_B_LSB (1U << 3) /* 1b */
+#define REG_SW2SPM_INT3_MASK_B_LSB (1U << 4) /* 1b */
+#define REG_SC_ADSP2SPM_WAKEUP_MASK_B_LSB (1U << 5) /* 1b */
+#define REG_SC_SSPM2SPM_WAKEUP_MASK_B_LSB (1U << 6) /* 4b */
+#define REG_SC_SCP2SPM_WAKEUP_MASK_B_LSB (1U << 10) /* 1b */
+#define REG_CSYSPWRREQ_MASK_LSB (1U << 11) /* 1b */
+#define REG_SPM_SRCCLKENA_RESERVED_MASK_B_LSB (1U << 12) /* 1b */
+#define REG_SPM_INFRA_REQ_RESERVED_MASK_B_LSB (1U << 13) /* 1b */
+#define REG_SPM_APSRC_REQ_RESERVED_MASK_B_LSB (1U << 14) /* 1b */
+#define REG_SPM_VRF18_REQ_RESERVED_MASK_B_LSB (1U << 15) /* 1b */
+#define REG_SPM_DDR_EN_RESERVED_MASK_B_LSB (1U << 16) /* 1b */
+#define REG_MCUPM_SRCCLKENA_MASK_B_LSB (1U << 17) /* 1b */
+#define REG_MCUPM_INFRA_REQ_MASK_B_LSB (1U << 18) /* 1b */
+#define REG_MCUPM_APSRC_REQ_MASK_B_LSB (1U << 19) /* 1b */
+#define REG_MCUPM_VRF18_REQ_MASK_B_LSB (1U << 20) /* 1b */
+#define REG_MCUPM_DDR_EN_MASK_B_LSB (1U << 21) /* 1b */
+#define REG_MSDC0_SRCCLKENA_MASK_B_LSB (1U << 22) /* 1b */
+#define REG_MSDC0_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */
+#define REG_MSDC0_APSRC_REQ_MASK_B_LSB (1U << 24) /* 1b */
+#define REG_MSDC0_VRF18_REQ_MASK_B_LSB (1U << 25) /* 1b */
+#define REG_MSDC0_DDR_EN_MASK_B_LSB (1U << 26) /* 1b */
+#define REG_MSDC1_SRCCLKENA_MASK_B_LSB (1U << 27) /* 1b */
+#define REG_MSDC1_INFRA_REQ_MASK_B_LSB (1U << 28) /* 1b */
+#define REG_MSDC1_APSRC_REQ_MASK_B_LSB (1U << 29) /* 1b */
+#define REG_MSDC1_VRF18_REQ_MASK_B_LSB (1U << 30) /* 1b */
+#define REG_MSDC1_DDR_EN_MASK_B_LSB (1U << 31) /* 1b */
+/* SPM_SRC4_MASK (0x10006000+0x0C8) */
+#define CCIF_EVENT_MASK_B_LSB (1U << 0) /* 16b */
+#define REG_BAK_PSRI_SRCCLKENA_MASK_B_LSB (1U << 16) /* 1b */
+#define REG_BAK_PSRI_INFRA_REQ_MASK_B_LSB (1U << 17) /* 1b */
+#define REG_BAK_PSRI_APSRC_REQ_MASK_B_LSB (1U << 18) /* 1b */
+#define REG_BAK_PSRI_VRF18_REQ_MASK_B_LSB (1U << 19) /* 1b */
+#define REG_BAK_PSRI_DDR_EN_MASK_B_LSB (1U << 20) /* 1b */
+#define REG_DRAMC0_MD32_INFRA_REQ_MASK_B_LSB (1U << 21) /* 1b */
+#define REG_DRAMC0_MD32_VRF18_REQ_MASK_B_LSB (1U << 22) /* 1b */
+#define REG_DRAMC1_MD32_INFRA_REQ_MASK_B_LSB (1U << 23) /* 1b */
+#define REG_DRAMC1_MD32_VRF18_REQ_MASK_B_LSB (1U << 24) /* 1b */
+#define REG_CONN_SRCCLKENB2PWRAP_MASK_B_LSB (1U << 25) /* 1b */
+#define REG_DRAMC0_MD32_WAKEUP_MASK_LSB (1U << 26) /* 1b */
+#define REG_DRAMC1_MD32_WAKEUP_MASK_LSB (1U << 27) /* 1b */
+/* SPM_SRC5_MASK (0x10006000+0x0CC) */
+#define REG_MCUSYS_MERGE_APSRC_REQ_MASK_B_LSB (1U << 0) /* 9b */
+#define REG_MCUSYS_MERGE_DDR_EN_MASK_B_LSB (1U << 9) /* 9b */
+/* SPM_WAKEUP_EVENT_MASK (0x10006000+0x0D0) */
+#define REG_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */
+/* SPM_WAKEUP_EVENT_EXT_MASK (0x10006000+0x0D4) */
+#define REG_EXT_WAKEUP_EVENT_MASK_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_EVENT_CLEAR (0x10006000+0x0D8) */
+#define SPM_TWAM_EVENT_CLEAR_LSB (1U << 0) /* 1b */
+/* SCP_CLK_CON (0x10006000+0x0DC) */
+#define REG_SCP_26M_CK_SEL_LSB (1U << 0) /* 1b */
+#define REG_SCP_DCM_EN_LSB (1U << 1) /* 1b */
+#define SCP_SECURE_V_REQ_MASK_LSB (1U << 2) /* 1b */
+#define SCP_SLP_REQ_LSB (1U << 3) /* 1b */
+#define SCP_SLP_ACK_LSB (1U << 4) /* 1b */
+/* SPM_RESOURCE_ACK_CON0 (0x10006000+0x0F0) */
+#define REG_MD_SRCCLKENA_ACK_0_MASK_LSB (1U << 0) /* 1b */
+#define REG_MD_INFRA_ACK_0_MASK_LSB (1U << 1) /* 1b */
+#define REG_MD_APSRC_ACK_0_MASK_LSB (1U << 2) /* 1b */
+#define REG_MD_VRF18_ACK_0_MASK_LSB (1U << 3) /* 1b */
+#define REG_MD_DDR_EN_ACK_0_MASK_LSB (1U << 4) /* 1b */
+#define REG_MD_SRCCLKENA_ACK_1_MASK_LSB (1U << 5) /* 1b */
+#define REG_MD_INFRA_ACK_1_MASK_LSB (1U << 6) /* 1b */
+#define REG_MD_APSRC_ACK_1_MASK_LSB (1U << 7) /* 1b */
+#define REG_MD_VRF18_ACK_1_MASK_LSB (1U << 8) /* 1b */
+#define REG_MD_DDR_EN_ACK_1_MASK_LSB (1U << 9) /* 1b */
+#define REG_CONN_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */
+#define REG_CONN_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */
+#define REG_CONN_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */
+#define REG_CONN_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */
+#define REG_CONN_DDR_EN_ACK_MASK_LSB (1U << 14) /* 1b */
+#define REG_MD32_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */
+#define REG_MD32_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */
+#define REG_MD32_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */
+#define REG_MD32_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */
+#define REG_MD32_DDR_EN_ACK_MASK_LSB (1U << 19) /* 1b */
+#define REG_SCP_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */
+#define REG_SCP_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */
+#define REG_SCP_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */
+#define REG_SCP_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */
+#define REG_SCP_DDR_EN_ACK_MASK_LSB (1U << 24) /* 1b */
+#define REG_AUDIO_DSP_SRCCLKENA_ACK_MASK_LSB (1U << 25) /* 1b */
+#define REG_AUDIO_DSP_INFRA_ACK_MASK_LSB (1U << 26) /* 1b */
+#define REG_AUDIO_DSP_APSRC_ACK_MASK_LSB (1U << 27) /* 1b */
+#define REG_AUDIO_DSP_VRF18_ACK_MASK_LSB (1U << 28) /* 1b */
+#define REG_AUDIO_DSP_DDR_EN_ACK_MASK_LSB (1U << 29) /* 1b */
+#define REG_DISP0_DDR_EN_ACK_MASK_LSB (1U << 30) /* 1b */
+#define REG_DISP1_APSRC_ACK_MASK_LSB (1U << 31) /* 1b */
+/* SPM_RESOURCE_ACK_CON1 (0x10006000+0x0F4) */
+#define REG_UFS_SRCCLKENA_ACK_MASK_LSB (1U << 0) /* 1b */
+#define REG_UFS_INFRA_ACK_MASK_LSB (1U << 1) /* 1b */
+#define REG_UFS_APSRC_ACK_MASK_LSB (1U << 2) /* 1b */
+#define REG_UFS_VRF18_ACK_MASK_LSB (1U << 3) /* 1b */
+#define REG_UFS_DDR_EN_ACK_MASK_LSB (1U << 4) /* 1b */
+#define REG_APU_SRCCLKENA_ACK_MASK_LSB (1U << 5) /* 1b */
+#define REG_APU_INFRA_ACK_MASK_LSB (1U << 6) /* 1b */
+#define REG_APU_APSRC_ACK_MASK_LSB (1U << 7) /* 1b */
+#define REG_APU_VRF18_ACK_MASK_LSB (1U << 8) /* 1b */
+#define REG_APU_DDR_EN_ACK_MASK_LSB (1U << 9) /* 1b */
+#define REG_MCUPM_SRCCLKENA_ACK_MASK_LSB (1U << 10) /* 1b */
+#define REG_MCUPM_INFRA_ACK_MASK_LSB (1U << 11) /* 1b */
+#define REG_MCUPM_APSRC_ACK_MASK_LSB (1U << 12) /* 1b */
+#define REG_MCUPM_VRF18_ACK_MASK_LSB (1U << 13) /* 1b */
+#define REG_MCUPM_DDR_EN_ACK_MASK_LSB (1U << 14) /* 1b */
+#define REG_MSDC0_SRCCLKENA_ACK_MASK_LSB (1U << 15) /* 1b */
+#define REG_MSDC0_INFRA_ACK_MASK_LSB (1U << 16) /* 1b */
+#define REG_MSDC0_APSRC_ACK_MASK_LSB (1U << 17) /* 1b */
+#define REG_MSDC0_VRF18_ACK_MASK_LSB (1U << 18) /* 1b */
+#define REG_MSDC0_DDR_EN_ACK_MASK_LSB (1U << 19) /* 1b */
+#define REG_MSDC1_SRCCLKENA_ACK_MASK_LSB (1U << 20) /* 1b */
+#define REG_MSDC1_INFRA_ACK_MASK_LSB (1U << 21) /* 1b */
+#define REG_MSDC1_APSRC_ACK_MASK_LSB (1U << 22) /* 1b */
+#define REG_MSDC1_VRF18_ACK_MASK_LSB (1U << 23) /* 1b */
+#define REG_MSDC1_DDR_EN_ACK_MASK_LSB (1U << 24) /* 1b */
+#define REG_DISP0_APSRC_ACK_MASK_LSB (1U << 25) /* 1b */
+#define REG_DISP1_DDR_EN_ACK_MASK_LSB (1U << 26) /* 1b */
+#define REG_GCE_INFRA_ACK_MASK_LSB (1U << 27) /* 1b */
+#define REG_GCE_APSRC_ACK_MASK_LSB (1U << 28) /* 1b */
+#define REG_GCE_VRF18_ACK_MASK_LSB (1U << 29) /* 1b */
+#define REG_GCE_DDR_EN_ACK_MASK_LSB (1U << 30) /* 1b */
+/* SPM_RESOURCE_ACK_CON2 (0x10006000+0x0F8) */
+#define SPM_F26M_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */
+#define SPM_INFRA_ACK_WAIT_CYCLE_LSB (1U << 8) /* 8b */
+#define SPM_APSRC_ACK_WAIT_CYCLE_LSB (1U << 16) /* 8b */
+#define SPM_VRF18_ACK_WAIT_CYCLE_LSB (1U << 24) /* 8b */
+/* SPM_RESOURCE_ACK_CON3 (0x10006000+0x0FC) */
+#define SPM_DDR_EN_ACK_WAIT_CYCLE_LSB (1U << 0) /* 8b */
+#define REG_BAK_PSRI_SRCCLKENA_ACK_MASK_LSB (1U << 8) /* 1b */
+#define REG_BAK_PSRI_INFRA_ACK_MASK_LSB (1U << 9) /* 1b */
+#define REG_BAK_PSRI_APSRC_ACK_MASK_LSB (1U << 10) /* 1b */
+#define REG_BAK_PSRI_VRF18_ACK_MASK_LSB (1U << 11) /* 1b */
+#define REG_BAK_PSRI_DDR_EN_ACK_MASK_LSB (1U << 12) /* 1b */
+/* PCM_REG0_DATA (0x10006000+0x100) */
+#define PCM_REG0_RF_LSB (1U << 0) /* 32b */
+/* PCM_REG2_DATA (0x10006000+0x104) */
+#define PCM_REG2_RF_LSB (1U << 0) /* 32b */
+/* PCM_REG6_DATA (0x10006000+0x108) */
+#define PCM_REG6_RF_LSB (1U << 0) /* 32b */
+/* PCM_REG7_DATA (0x10006000+0x10C) */
+#define PCM_REG7_RF_LSB (1U << 0) /* 32b */
+/* PCM_REG13_DATA (0x10006000+0x110) */
+#define PCM_REG13_RF_LSB (1U << 0) /* 32b */
+/* SRC_REQ_STA_0 (0x10006000+0x114) */
+#define MD_SRCCLKENA_0_LSB (1U << 0) /* 1b */
+#define MD_SRCCLKENA2INFRA_REQ_0_LSB (1U << 1) /* 1b */
+#define MD_APSRC2INFRA_REQ_0_LSB (1U << 2) /* 1b */
+#define MD_APSRC_REQ_0_LSB (1U << 3) /* 1b */
+#define MD_VRF18_REQ_0_LSB (1U << 4) /* 1b */
+#define MD_DDR_EN_0_LSB (1U << 5) /* 1b */
+#define MD_SRCCLKENA_1_LSB (1U << 6) /* 1b */
+#define MD_SRCCLKENA2INFRA_REQ_1_LSB (1U << 7) /* 1b */
+#define MD_APSRC2INFRA_REQ_1_LSB (1U << 8) /* 1b */
+#define MD_APSRC_REQ_1_LSB (1U << 9) /* 1b */
+#define MD_VRF18_REQ_1_LSB (1U << 10) /* 1b */
+#define MD_DDR_EN_1_LSB (1U << 11) /* 1b */
+#define CONN_SRCCLKENA_LSB (1U << 12) /* 1b */
+#define CONN_SRCCLKENB_LSB (1U << 13) /* 1b */
+#define CONN_INFRA_REQ_LSB (1U << 14) /* 1b */
+#define CONN_APSRC_REQ_LSB (1U << 15) /* 1b */
+#define CONN_VRF18_REQ_LSB (1U << 16) /* 1b */
+#define CONN_DDR_EN_LSB (1U << 17) /* 1b */
+#define SRCCLKENI_LSB (1U << 18) /* 3b */
+#define MD32_SRCCLKENA_LSB (1U << 21) /* 1b */
+#define MD32_INFRA_REQ_LSB (1U << 22) /* 1b */
+#define MD32_APSRC_REQ_LSB (1U << 23) /* 1b */
+#define MD32_VRF18_REQ_LSB (1U << 24) /* 1b */
+#define MD32_DDR_EN_LSB (1U << 25) /* 1b */
+#define DISP0_APSRC_REQ_LSB (1U << 26) /* 1b */
+#define DISP0_DDR_EN_LSB (1U << 27) /* 1b */
+#define DISP1_APSRC_REQ_LSB (1U << 28) /* 1b */
+#define DISP1_DDR_EN_LSB (1U << 29) /* 1b */
+#define DVFSRC_EVENT_TRIGGER_LSB (1U << 30) /* 1b */
+/* SRC_REQ_STA_1 (0x10006000+0x118) */
+#define SCP_SRCCLKENA_LSB (1U << 0) /* 1b */
+#define SCP_INFRA_REQ_LSB (1U << 1) /* 1b */
+#define SCP_APSRC_REQ_LSB (1U << 2) /* 1b */
+#define SCP_VRF18_REQ_LSB (1U << 3) /* 1b */
+#define SCP_DDR_EN_LSB (1U << 4) /* 1b */
+#define AUDIO_DSP_SRCCLKENA_LSB (1U << 5) /* 1b */
+#define AUDIO_DSP_INFRA_REQ_LSB (1U << 6) /* 1b */
+#define AUDIO_DSP_APSRC_REQ_LSB (1U << 7) /* 1b */
+#define AUDIO_DSP_VRF18_REQ_LSB (1U << 8) /* 1b */
+#define AUDIO_DSP_DDR_EN_LSB (1U << 9) /* 1b */
+#define UFS_SRCCLKENA_LSB (1U << 10) /* 1b */
+#define UFS_INFRA_REQ_LSB (1U << 11) /* 1b */
+#define UFS_APSRC_REQ_LSB (1U << 12) /* 1b */
+#define UFS_VRF18_REQ_LSB (1U << 13) /* 1b */
+#define UFS_DDR_EN_LSB (1U << 14) /* 1b */
+#define GCE_INFRA_REQ_LSB (1U << 15) /* 1b */
+#define GCE_APSRC_REQ_LSB (1U << 16) /* 1b */
+#define GCE_VRF18_REQ_LSB (1U << 17) /* 1b */
+#define GCE_DDR_EN_LSB (1U << 18) /* 1b */
+#define INFRASYS_APSRC_REQ_LSB (1U << 19) /* 1b */
+#define INFRASYS_DDR_EN_LSB (1U << 20) /* 1b */
+#define MSDC0_SRCCLKENA_LSB (1U << 21) /* 1b */
+#define MSDC0_INFRA_REQ_LSB (1U << 22) /* 1b */
+#define MSDC0_APSRC_REQ_LSB (1U << 23) /* 1b */
+#define MSDC0_VRF18_REQ_LSB (1U << 24) /* 1b */
+#define MSDC0_DDR_EN_LSB (1U << 25) /* 1b */
+#define MSDC1_SRCCLKENA_LSB (1U << 26) /* 1b */
+#define MSDC1_INFRA_REQ_LSB (1U << 27) /* 1b */
+#define MSDC1_APSRC_REQ_LSB (1U << 28) /* 1b */
+#define MSDC1_VRF18_REQ_LSB (1U << 29) /* 1b */
+#define MSDC1_DDR_EN_LSB (1U << 30) /* 1b */
+/* SRC_REQ_STA_2 (0x10006000+0x11C) */
+#define MCUSYS_MERGE_DDR_EN_LSB (1U << 0) /* 9b */
+#define EMI_SELF_REFRESH_CH_LSB (1U << 9) /* 2b */
+#define SW2SPM_INT_LSB (1U << 11) /* 4b */
+#define SC_ADSP2SPM_WAKEUP_LSB (1U << 15) /* 1b */
+#define SC_SSPM2SPM_WAKEUP_LSB (1U << 16) /* 4b */
+#define SRC_REQ_STA_2_SC_SCP2SPM_WAKEUP_LSB (1U << 20) /* 1b */
+#define SPM_SRCCLKENA_RESERVED_LSB (1U << 21) /* 1b */
+#define SPM_INFRA_REQ_RESERVED_LSB (1U << 22) /* 1b */
+#define SPM_APSRC_REQ_RESERVED_LSB (1U << 23) /* 1b */
+#define SPM_VRF18_REQ_RESERVED_LSB (1U << 24) /* 1b */
+#define SPM_DDR_EN_RESERVED_LSB (1U << 25) /* 1b */
+#define MCUPM_SRCCLKENA_LSB (1U << 26) /* 1b */
+#define MCUPM_INFRA_REQ_LSB (1U << 27) /* 1b */
+#define MCUPM_APSRC_REQ_LSB (1U << 28) /* 1b */
+#define MCUPM_VRF18_REQ_LSB (1U << 29) /* 1b */
+#define MCUPM_DDR_EN_LSB (1U << 30) /* 1b */
+/* PCM_TIMER_OUT (0x10006000+0x120) */
+#define PCM_TIMER_LSB (1U << 0) /* 32b */
+/* PCM_WDT_OUT (0x10006000+0x124) */
+#define PCM_WDT_TIMER_VAL_OUT_LSB (1U << 0) /* 32b */
+/* SPM_IRQ_STA (0x10006000+0x128) */
+#define TWAM_IRQ_LSB (1U << 2) /* 1b */
+#define PCM_IRQ_LSB (1U << 3) /* 1b */
+/* SRC_REQ_STA_4 (0x10006000+0x12C) */
+#define APU_SRCCLKENA_LSB (1U << 0) /* 1b */
+#define APU_INFRA_REQ_LSB (1U << 1) /* 1b */
+#define APU_APSRC_REQ_LSB (1U << 2) /* 1b */
+#define APU_VRF18_REQ_LSB (1U << 3) /* 1b */
+#define APU_DDR_EN_LSB (1U << 4) /* 1b */
+#define BAK_PSRI_SRCCLKENA_LSB (1U << 5) /* 1b */
+#define BAK_PSRI_INFRA_REQ_LSB (1U << 6) /* 1b */
+#define BAK_PSRI_APSRC_REQ_LSB (1U << 7) /* 1b */
+#define BAK_PSRI_VRF18_REQ_LSB (1U << 8) /* 1b */
+#define BAK_PSRI_DDR_EN_LSB (1U << 9) /* 1b */
+/* MD32PCM_WAKEUP_STA (0x10006000+0x130) */
+#define MD32PCM_WAKEUP_STA_LSB (1U << 0) /* 32b */
+/* MD32PCM_EVENT_STA (0x10006000+0x134) */
+#define MD32PCM_EVENT_STA_LSB (1U << 0) /* 32b */
+/* SPM_WAKEUP_STA (0x10006000+0x138) */
+#define F32K_WAKEUP_EVENT_L_LSB (1U << 0) /* 16b */
+#define ASYN_WAKEUP_EVENT_L_LSB (1U << 16) /* 16b */
+/* SPM_WAKEUP_EXT_STA (0x10006000+0x13C) */
+#define EXT_WAKEUP_EVENT_LSB (1U << 0) /* 32b */
+/* SPM_WAKEUP_MISC (0x10006000+0x140) */
+#define GIC_WAKEUP_LSB (1U << 0) /* 10b */
+#define DVFSRC_IRQ_LSB (1U << 16) /* 1b */
+#define SPM_WAKEUP_MISC_REG_CPU_WAKEUP_LSB (1U << 17) /* 1b */
+#define PCM_TIMER_EVENT_LSB (1U << 18) /* 1b */
+#define PMIC_EINT_OUT_B_LSB (1U << 19) /* 2b */
+#define TWAM_IRQ_B_LSB (1U << 21) /* 1b */
+#define PMSR_IRQ_B_SET0_LSB (1U << 22) /* 1b */
+#define PMSR_IRQ_B_SET1_LSB (1U << 23) /* 1b */
+#define PMSR_IRQ_B_SET2_LSB (1U << 24) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_0_LSB (1U << 25) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_1_LSB (1U << 26) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_2_LSB (1U << 27) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_3_LSB (1U << 28) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_ALL_LSB (1U << 29) /* 1b */
+#define PMIC_IRQ_ACK_LSB (1U << 30) /* 1b */
+#define PMIC_SCP_IRQ_LSB (1U << 31) /* 1b */
+/* MM_DVFS_HALT (0x10006000+0x144) */
+#define MM_DVFS_HALT_LSB (1U << 0) /* 5b */
+/* BUS_PROTECT_RDY (0x10006000+0x150) */
+#define PROTECT_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT1_RDY (0x10006000+0x154) */
+#define PROTECT1_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT2_RDY (0x10006000+0x158) */
+#define PROTECT2_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT3_RDY (0x10006000+0x15C) */
+#define PROTECT3_READY_LSB (1U << 0) /* 32b */
+/* SUBSYS_IDLE_STA (0x10006000+0x160) */
+#define SUBSYS_IDLE_SIGNALS_LSB (1U << 0) /* 32b */
+/* PCM_STA (0x10006000+0x164) */
+#define PCM_CK_SEL_O_LSB (1U << 0) /* 4b */
+#define EXT_SRC_STA_LSB (1U << 4) /* 3b */
+/* SRC_REQ_STA_3 (0x10006000+0x168) */
+#define CCIF_EVENT_RAW_STATUS_LSB (1U << 0) /* 16b */
+#define F26M_STATE_LSB (1U << 16) /* 1b */
+#define INFRA_STATE_LSB (1U << 17) /* 1b */
+#define APSRC_STATE_LSB (1U << 18) /* 1b */
+#define VRF18_STATE_LSB (1U << 19) /* 1b */
+#define DDR_EN_STATE_LSB (1U << 20) /* 1b */
+#define DVFS_STATE_LSB (1U << 21) /* 1b */
+#define SW_MAILBOX_STATE_LSB (1U << 22) /* 1b */
+#define SSPM_MAILBOX_STATE_LSB (1U << 23) /* 1b */
+#define ADSP_MAILBOX_STATE_LSB (1U << 24) /* 1b */
+#define SCP_MAILBOX_STATE_LSB (1U << 25) /* 1b */
+/* PWR_STATUS (0x10006000+0x16C) */
+#define PWR_STATUS_LSB (1U << 0) /* 32b */
+/* PWR_STATUS_2ND (0x10006000+0x170) */
+#define PWR_STATUS_2ND_LSB (1U << 0) /* 32b */
+/* CPU_PWR_STATUS (0x10006000+0x174) */
+#define MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 1) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 3) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 4) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 5) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 6) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 7) /* 1b */
+#define MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 8) /* 1b */
+#define MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 9) /* 1b */
+/* OTHER_PWR_STATUS (0x10006000+0x178) */
+#define OTHER_PWR_STATUS_LSB (1U << 0) /* 32b */
+/* SPM_VTCXO_EVENT_COUNT_STA (0x10006000+0x17C) */
+#define SPM_VTCXO_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_VTCXO_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* SPM_INFRA_EVENT_COUNT_STA (0x10006000+0x180) */
+#define SPM_INFRA_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_INFRA_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* SPM_VRF18_EVENT_COUNT_STA (0x10006000+0x184) */
+#define SPM_VRF18_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_VRF18_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* SPM_APSRC_EVENT_COUNT_STA (0x10006000+0x188) */
+#define SPM_APSRC_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_APSRC_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* SPM_DDREN_EVENT_COUNT_STA (0x10006000+0x18C) */
+#define SPM_DDREN_SLEEP_COUNT_LSB (1U << 0) /* 16b */
+#define SPM_DDREN_WAKE_COUNT_LSB (1U << 16) /* 16b */
+/* MD32PCM_STA (0x10006000+0x190) */
+#define MD32PCM_HALT_LSB (1U << 0) /* 1b */
+#define MD32PCM_GATED_LSB (1U << 1) /* 1b */
+/* MD32PCM_PC (0x10006000+0x194) */
+#define MON_PC_LSB (1U << 0) /* 32b */
+/* DVFSRC_EVENT_STA (0x10006000+0x1A4) */
+#define DVFSRC_EVENT_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT4_RDY (0x10006000+0x1A8) */
+#define PROTECT4_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT5_RDY (0x10006000+0x1AC) */
+#define PROTECT5_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT6_RDY (0x10006000+0x1B0) */
+#define PROTECT6_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT7_RDY (0x10006000+0x1B4) */
+#define PROTECT7_READY_LSB (1U << 0) /* 32b */
+/* BUS_PROTECT8_RDY (0x10006000+0x1B8) */
+#define PROTECT8_READY_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_LAST_STA0 (0x10006000+0x1D0) */
+#define LAST_IDLE_CNT_0_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_LAST_STA1 (0x10006000+0x1D4) */
+#define LAST_IDLE_CNT_1_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_LAST_STA2 (0x10006000+0x1D8) */
+#define LAST_IDLE_CNT_2_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_LAST_STA3 (0x10006000+0x1DC) */
+#define LAST_IDLE_CNT_3_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA0 (0x10006000+0x1E0) */
+#define CURRENT_IDLE_CNT_0_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA1 (0x10006000+0x1E4) */
+#define CURRENT_IDLE_CNT_1_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA2 (0x10006000+0x1E8) */
+#define CURRENT_IDLE_CNT_2_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_CURR_STA3 (0x10006000+0x1EC) */
+#define CURRENT_IDLE_CNT_3_LSB (1U << 0) /* 32b */
+/* SPM_TWAM_TIMER_OUT (0x10006000+0x1F0) */
+#define TWAM_TIMER_LSB (1U << 0) /* 32b */
+/* SPM_CG_CHECK_STA (0x10006000+0x1F4) */
+#define SPM_CG_CHECK_SLEEP_REQ_0_LSB (1U << 0) /* 1b */
+#define SPM_CG_CHECK_SLEEP_REQ_1_LSB (1U << 1) /* 1b */
+#define SPM_CG_CHECK_SLEEP_REQ_2_LSB (1U << 2) /* 1b */
+/* SPM_DVFS_STA (0x10006000+0x1F8) */
+#define TARGET_DVFS_LEVEL_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_OPP_STA (0x10006000+0x1FC) */
+#define TARGET_DVFS_OPP_LSB (1U << 0) /* 5b */
+#define CURRENT_DVFS_OPP_LSB (1U << 5) /* 5b */
+#define RELAY_DVFS_OPP_LSB (1U << 10) /* 5b */
+/* SPM_MCUSYS_PWR_CON (0x10006000+0x200) */
+#define MCUSYS_SPMC_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MCUSYS_SPMC_PWR_ON_LSB (1U << 2) /* 1b */
+#define MCUSYS_SPMC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MCUSYS_SPMC_RESETPWRON_CONFIG_LSB (1U << 5) /* 1b */
+#define MCUSYS_SPMC_DORMANT_EN_LSB (1U << 6) /* 1b */
+#define MCUSYS_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */
+#define SPM_MCUSYS_PWR_CON_MCUSYS_SPMC_PWR_ON_ACK_LSB (1U << 31) /* 1b */
+/* SPM_CPUTOP_PWR_CON (0x10006000+0x204) */
+#define MP0_SPMC_PWR_RST_B_CPUTOP_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPUTOP_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_PWR_CLK_DIS_CPUTOP_LSB (1U << 4) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPUTOP_LSB (1U << 5) /* 1b */
+#define MP0_SPMC_DORMANT_EN_CPUTOP_LSB (1U << 6) /* 1b */
+#define MP0_VPROC_EXT_OFF_LSB (1U << 7) /* 1b */
+#define MP0_VSRAM_EXT_OFF_LSB (1U << 8) /* 1b */
+#define SPM_CPUTOP_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPUTOP_LSB (1U << 31) /* 1b */
+/* SPM_CPU0_PWR_CON (0x10006000+0x208) */
+#define MP0_SPMC_PWR_RST_B_CPU0_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU0_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU0_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU0_LSB (1U << 7) /* 1b */
+#define SPM_CPU0_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU0_LSB (1U << 31) /* 1b */
+/* SPM_CPU1_PWR_CON (0x10006000+0x20C) */
+#define MP0_SPMC_PWR_RST_B_CPU1_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU1_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU1_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU1_LSB (1U << 7) /* 1b */
+#define SPM_CPU1_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU1_LSB (1U << 31) /* 1b */
+/* SPM_CPU2_PWR_CON (0x10006000+0x210) */
+#define MP0_SPMC_PWR_RST_B_CPU2_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU2_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU2_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU2_LSB (1U << 7) /* 1b */
+#define SPM_CPU2_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU2_LSB (1U << 31) /* 1b */
+/* SPM_CPU3_PWR_CON (0x10006000+0x214) */
+#define MP0_SPMC_PWR_RST_B_CPU3_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU3_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU3_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU3_LSB (1U << 7) /* 1b */
+#define SPM_CPU3_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU3_LSB (1U << 31) /* 1b */
+/* SPM_CPU4_PWR_CON (0x10006000+0x218) */
+#define MP0_SPMC_PWR_RST_B_CPU4_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU4_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU4_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU4_LSB (1U << 7) /* 1b */
+#define SPM_CPU4_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU4_LSB (1U << 31) /* 1b */
+/* SPM_CPU5_PWR_CON (0x10006000+0x21C) */
+#define MP0_SPMC_PWR_RST_B_CPU5_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU5_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU5_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU5_LSB (1U << 7) /* 1b */
+#define SPM_CPU5_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU5_LSB (1U << 31) /* 1b */
+/* SPM_CPU6_PWR_CON (0x10006000+0x220) */
+#define MP0_SPMC_PWR_RST_B_CPU6_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU6_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU6_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU6_LSB (1U << 7) /* 1b */
+#define SPM_CPU6_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU6_LSB (1U << 31) /* 1b */
+/* SPM_CPU7_PWR_CON (0x10006000+0x224) */
+#define MP0_SPMC_PWR_RST_B_CPU7_LSB (1U << 0) /* 1b */
+#define MP0_SPMC_PWR_ON_CPU7_LSB (1U << 2) /* 1b */
+#define MP0_SPMC_RESETPWRON_CONFIG_CPU7_LSB (1U << 5) /* 1b */
+#define MP0_VPROC_EXT_OFF_CPU7_LSB (1U << 7) /* 1b */
+#define SPM_CPU7_PWR_CON_MP0_SPMC_PWR_ON_ACK_CPU7_LSB (1U << 31) /* 1b */
+/* ARMPLL_CLK_CON (0x10006000+0x22C) */
+#define SC_ARM_FHC_PAUSE_LSB (1U << 0) /* 6b */
+#define SC_ARM_CK_OFF_LSB (1U << 6) /* 6b */
+#define SC_ARMPLL_OFF_LSB (1U << 12) /* 1b */
+#define SC_ARMBPLL_OFF_LSB (1U << 13) /* 1b */
+#define SC_ARMBPLL1_OFF_LSB (1U << 14) /* 1b */
+#define SC_ARMBPLL2_OFF_LSB (1U << 15) /* 1b */
+#define SC_ARMBPLL3_OFF_LSB (1U << 16) /* 1b */
+#define SC_CCIPLL_CKOFF_LSB (1U << 17) /* 1b */
+#define SC_ARMDDS_OFF_LSB (1U << 18) /* 1b */
+#define SC_ARMBPLL_S_OFF_LSB (1U << 19) /* 1b */
+#define SC_ARMBPLL1_S_OFF_LSB (1U << 20) /* 1b */
+#define SC_ARMBPLL2_S_OFF_LSB (1U << 21) /* 1b */
+#define SC_ARMBPLL3_S_OFF_LSB (1U << 22) /* 1b */
+#define SC_CCIPLL_PWROFF_LSB (1U << 23) /* 1b */
+#define SC_ARMPLLOUT_OFF_LSB (1U << 24) /* 1b */
+#define SC_ARMBPLLOUT_OFF_LSB (1U << 25) /* 1b */
+#define SC_ARMBPLLOUT1_OFF_LSB (1U << 26) /* 1b */
+#define SC_ARMBPLLOUT2_OFF_LSB (1U << 27) /* 1b */
+#define SC_ARMBPLLOUT3_OFF_LSB (1U << 28) /* 1b */
+#define SC_CCIPLL_OUT_OFF_LSB (1U << 29) /* 1b */
+/* MCUSYS_IDLE_STA (0x10006000+0x230) */
+#define ARMBUS_IDLE_TO_26M_LSB (1U << 0) /* 1b */
+#define MP0_CLUSTER_IDLE_TO_PWR_OFF_LSB (1U << 1) /* 1b */
+#define MCUSYS_DDR_EN_0_LSB (1U << 2) /* 1b */
+#define MCUSYS_DDR_EN_1_LSB (1U << 3) /* 1b */
+#define MCUSYS_DDR_EN_2_LSB (1U << 4) /* 1b */
+#define MCUSYS_DDR_EN_3_LSB (1U << 5) /* 1b */
+#define MCUSYS_DDR_EN_4_LSB (1U << 6) /* 1b */
+#define MCUSYS_DDR_EN_5_LSB (1U << 7) /* 1b */
+#define MCUSYS_DDR_EN_6_LSB (1U << 8) /* 1b */
+#define MCUSYS_DDR_EN_7_LSB (1U << 9) /* 1b */
+#define MP0_CPU_IDLE_TO_PWR_OFF_LSB (1U << 16) /* 8b */
+#define WFI_AF_SEL_LSB (1U << 24) /* 8b */
+/* GIC_WAKEUP_STA (0x10006000+0x234) */
+#define GIC_WAKEUP_STA_GIC_WAKEUP_LSB (1U << 10) /* 10b */
+/* CPU_SPARE_CON (0x10006000+0x238) */
+#define CPU_SPARE_CON_LSB (1U << 0) /* 32b */
+/* CPU_SPARE_CON_SET (0x10006000+0x23C) */
+#define CPU_SPARE_CON_SET_LSB (1U << 0) /* 32b */
+/* CPU_SPARE_CON_CLR (0x10006000+0x240) */
+#define CPU_SPARE_CON_CLR_LSB (1U << 0) /* 32b */
+/* ARMPLL_CLK_SEL (0x10006000+0x244) */
+#define ARMPLL_CLK_SEL_LSB (1U << 0) /* 15b */
+/* EXT_INT_WAKEUP_REQ (0x10006000+0x248) */
+#define EXT_INT_WAKEUP_REQ_LSB (1U << 0) /* 10b */
+/* EXT_INT_WAKEUP_REQ_SET (0x10006000+0x24C) */
+#define EXT_INT_WAKEUP_REQ_SET_LSB (1U << 0) /* 10b */
+/* EXT_INT_WAKEUP_REQ_CLR (0x10006000+0x250) */
+#define EXT_INT_WAKEUP_REQ_CLR_LSB (1U << 0) /* 10b */
+/* MP0_CPU0_IRQ_MASK (0x10006000+0x260) */
+#define MP0_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU0_AUX_LSB (1U << 8) /* 11b */
+/* MP0_CPU1_IRQ_MASK (0x10006000+0x264) */
+#define MP0_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU1_AUX_LSB (1U << 8) /* 11b */
+/* MP0_CPU2_IRQ_MASK (0x10006000+0x268) */
+#define MP0_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU2_AUX_LSB (1U << 8) /* 11b */
+/* MP0_CPU3_IRQ_MASK (0x10006000+0x26C) */
+#define MP0_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP0_CPU3_AUX_LSB (1U << 8) /* 11b */
+/* MP1_CPU0_IRQ_MASK (0x10006000+0x270) */
+#define MP1_CPU0_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU0_AUX_LSB (1U << 8) /* 11b */
+/* MP1_CPU1_IRQ_MASK (0x10006000+0x274) */
+#define MP1_CPU1_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU1_AUX_LSB (1U << 8) /* 11b */
+/* MP1_CPU2_IRQ_MASK (0x10006000+0x278) */
+#define MP1_CPU2_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU2_AUX_LSB (1U << 8) /* 11b */
+/* MP1_CPU3_IRQ_MASK (0x10006000+0x27C) */
+#define MP1_CPU3_IRQ_MASK_LSB (1U << 0) /* 1b */
+#define MP1_CPU3_AUX_LSB (1U << 8) /* 11b */
+/* MP0_CPU0_WFI_EN (0x10006000+0x280) */
+#define MP0_CPU0_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU1_WFI_EN (0x10006000+0x284) */
+#define MP0_CPU1_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU2_WFI_EN (0x10006000+0x288) */
+#define MP0_CPU2_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU3_WFI_EN (0x10006000+0x28C) */
+#define MP0_CPU3_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU4_WFI_EN (0x10006000+0x290) */
+#define MP0_CPU4_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU5_WFI_EN (0x10006000+0x294) */
+#define MP0_CPU5_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU6_WFI_EN (0x10006000+0x298) */
+#define MP0_CPU6_WFI_EN_LSB (1U << 0) /* 1b */
+/* MP0_CPU7_WFI_EN (0x10006000+0x29C) */
+#define MP0_CPU7_WFI_EN_LSB (1U << 0) /* 1b */
+/* ROOT_CPUTOP_ADDR (0x10006000+0x2A0) */
+#define ROOT_CPUTOP_ADDR_LSB (1U << 0) /* 32b */
+/* ROOT_CORE_ADDR (0x10006000+0x2A4) */
+#define ROOT_CORE_ADDR_LSB (1U << 0) /* 32b */
+/* SPM2SW_MAILBOX_0 (0x10006000+0x2D0) */
+#define SPM2SW_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* SPM2SW_MAILBOX_1 (0x10006000+0x2D4) */
+#define SPM2SW_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* SPM2SW_MAILBOX_2 (0x10006000+0x2D8) */
+#define SPM2SW_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* SPM2SW_MAILBOX_3 (0x10006000+0x2DC) */
+#define SPM2SW_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* SW2SPM_INT (0x10006000+0x2E0) */
+#define SW2SPM_INT_SW2SPM_INT_LSB (1U << 0) /* 4b */
+/* SW2SPM_INT_SET (0x10006000+0x2E4) */
+#define SW2SPM_INT_SET_LSB (1U << 0) /* 4b */
+/* SW2SPM_INT_CLR (0x10006000+0x2E8) */
+#define SW2SPM_INT_CLR_LSB (1U << 0) /* 4b */
+/* SW2SPM_MAILBOX_0 (0x10006000+0x2EC) */
+#define SW2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* SW2SPM_MAILBOX_1 (0x10006000+0x2F0) */
+#define SW2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* SW2SPM_MAILBOX_2 (0x10006000+0x2F4) */
+#define SW2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* SW2SPM_MAILBOX_3 (0x10006000+0x2F8) */
+#define SW2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* SW2SPM_CFG (0x10006000+0x2FC) */
+#define SWU2SPM_INT_MASK_B_LSB (1U << 0) /* 4b */
+/* MD1_PWR_CON (0x10006000+0x300) */
+#define MD1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MD1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MD1_PWR_ON_LSB (1U << 2) /* 1b */
+#define MD1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MD1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MD1_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MD1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* CONN_PWR_CON (0x10006000+0x304) */
+#define CONN_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CONN_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CONN_PWR_ON_LSB (1U << 2) /* 1b */
+#define CONN_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CONN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+/* MFG0_PWR_CON (0x10006000+0x308) */
+#define MFG0_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG0_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG0_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG0_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG0_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG0_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG0_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG1_PWR_CON (0x10006000+0x30C) */
+#define MFG1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG1_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG1_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG2_PWR_CON (0x10006000+0x310) */
+#define MFG2_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG2_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG2_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG2_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG3_PWR_CON (0x10006000+0x314) */
+#define MFG3_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG3_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG3_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG3_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG3_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG3_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG3_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG4_PWR_CON (0x10006000+0x318) */
+#define MFG4_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG4_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG4_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG4_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG4_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG4_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG4_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG5_PWR_CON (0x10006000+0x31C) */
+#define MFG5_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG5_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG5_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG5_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG5_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG5_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG5_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MFG6_PWR_CON (0x10006000+0x320) */
+#define MFG6_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MFG6_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MFG6_PWR_ON_LSB (1U << 2) /* 1b */
+#define MFG6_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MFG6_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MFG6_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MFG6_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* IFR_PWR_CON (0x10006000+0x324) */
+#define IFR_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define IFR_PWR_ISO_LSB (1U << 1) /* 1b */
+#define IFR_PWR_ON_LSB (1U << 2) /* 1b */
+#define IFR_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define IFR_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define IFR_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_IFR_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* IFR_SUB_PWR_CON (0x10006000+0x328) */
+#define IFR_SUB_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define IFR_SUB_PWR_ISO_LSB (1U << 1) /* 1b */
+#define IFR_SUB_PWR_ON_LSB (1U << 2) /* 1b */
+#define IFR_SUB_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define IFR_SUB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define IFR_SUB_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_IFR_SUB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* DPY_PWR_CON (0x10006000+0x32C) */
+#define DPY_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DPY_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DPY_PWR_ON_LSB (1U << 2) /* 1b */
+#define DPY_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DPY_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define DPY_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_DPY_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* ISP_PWR_CON (0x10006000+0x330) */
+#define ISP_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define ISP_PWR_ISO_LSB (1U << 1) /* 1b */
+#define ISP_PWR_ON_LSB (1U << 2) /* 1b */
+#define ISP_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define ISP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define ISP_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_ISP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* ISP2_PWR_CON (0x10006000+0x334) */
+#define ISP2_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define ISP2_PWR_ISO_LSB (1U << 1) /* 1b */
+#define ISP2_PWR_ON_LSB (1U << 2) /* 1b */
+#define ISP2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define ISP2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define ISP2_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_ISP2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* IPE_PWR_CON (0x10006000+0x338) */
+#define IPE_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define IPE_PWR_ISO_LSB (1U << 1) /* 1b */
+#define IPE_PWR_ON_LSB (1U << 2) /* 1b */
+#define IPE_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define IPE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define IPE_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_IPE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* VDE_PWR_CON (0x10006000+0x33C) */
+#define VDE_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VDE_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VDE_PWR_ON_LSB (1U << 2) /* 1b */
+#define VDE_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define VDE_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VDE_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_VDE_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* VDE2_PWR_CON (0x10006000+0x340) */
+#define VDE2_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VDE2_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VDE2_PWR_ON_LSB (1U << 2) /* 1b */
+#define VDE2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define VDE2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VDE2_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_VDE2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* VEN_PWR_CON (0x10006000+0x344) */
+#define VEN_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VEN_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VEN_PWR_ON_LSB (1U << 2) /* 1b */
+#define VEN_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define VEN_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VEN_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_VEN_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* VEN_CORE1_PWR_CON (0x10006000+0x348) */
+#define VEN_CORE1_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define VEN_CORE1_PWR_ISO_LSB (1U << 1) /* 1b */
+#define VEN_CORE1_PWR_ON_LSB (1U << 2) /* 1b */
+#define VEN_CORE1_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define VEN_CORE1_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define VEN_CORE1_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_VEN_CORE1_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* MDP_PWR_CON (0x10006000+0x34C) */
+#define MDP_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define MDP_PWR_ISO_LSB (1U << 1) /* 1b */
+#define MDP_PWR_ON_LSB (1U << 2) /* 1b */
+#define MDP_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define MDP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define MDP_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_MDP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* DIS_PWR_CON (0x10006000+0x350) */
+#define DIS_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DIS_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DIS_PWR_ON_LSB (1U << 2) /* 1b */
+#define DIS_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DIS_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define DIS_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_DIS_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* AUDIO_PWR_CON (0x10006000+0x354) */
+#define AUDIO_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define AUDIO_PWR_ISO_LSB (1U << 1) /* 1b */
+#define AUDIO_PWR_ON_LSB (1U << 2) /* 1b */
+#define AUDIO_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define AUDIO_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define AUDIO_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_AUDIO_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* ADSP_PWR_CON (0x10006000+0x358) */
+#define ADSP_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define ADSP_PWR_ISO_LSB (1U << 1) /* 1b */
+#define ADSP_PWR_ON_LSB (1U << 2) /* 1b */
+#define ADSP_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define ADSP_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define ADSP_SRAM_CKISO_LSB (1U << 5) /* 1b */
+#define ADSP_SRAM_ISOINT_B_LSB (1U << 6) /* 1b */
+#define ADSP_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define ADSP_SRAM_SLEEP_B_LSB (1U << 9) /* 1b */
+#define SC_ADSP_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+#define SC_ADSP_SRAM_SLEEP_B_ACK_LSB (1U << 13) /* 1b */
+/* CAM_PWR_CON (0x10006000+0x35C) */
+#define CAM_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CAM_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CAM_PWR_ON_LSB (1U << 2) /* 1b */
+#define CAM_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CAM_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define CAM_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_CAM_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* CAM_RAWA_PWR_CON (0x10006000+0x360) */
+#define CAM_RAWA_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CAM_RAWA_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CAM_RAWA_PWR_ON_LSB (1U << 2) /* 1b */
+#define CAM_RAWA_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CAM_RAWA_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define CAM_RAWA_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_CAM_RAWA_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* CAM_RAWB_PWR_CON (0x10006000+0x364) */
+#define CAM_RAWB_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CAM_RAWB_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CAM_RAWB_PWR_ON_LSB (1U << 2) /* 1b */
+#define CAM_RAWB_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CAM_RAWB_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define CAM_RAWB_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_CAM_RAWB_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* CAM_RAWC_PWR_CON (0x10006000+0x368) */
+#define CAM_RAWC_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define CAM_RAWC_PWR_ISO_LSB (1U << 1) /* 1b */
+#define CAM_RAWC_PWR_ON_LSB (1U << 2) /* 1b */
+#define CAM_RAWC_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define CAM_RAWC_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define CAM_RAWC_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_CAM_RAWC_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* SYSRAM_CON (0x10006000+0x36C) */
+#define SYSRAM_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define SYSRAM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define SYSRAM_SRAM_SLEEP_B_LSB (1U << 4) /* 4b */
+#define SYSRAM_SRAM_PDN_LSB (1U << 16) /* 4b */
+/* SYSROM_CON (0x10006000+0x370) */
+#define SYSROM_SRAM_PDN_LSB (1U << 0) /* 6b */
+/* SSPM_SRAM_CON (0x10006000+0x374) */
+#define SSPM_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define SSPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define SSPM_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define SSPM_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* SCP_SRAM_CON (0x10006000+0x378) */
+#define SCP_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define SCP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define SCP_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define SCP_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* DPY_SHU_SRAM_CON (0x10006000+0x37C) */
+#define DPY_SHU_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DPY_SHU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DPY_SHU_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */
+#define DPY_SHU_SRAM_PDN_LSB (1U << 16) /* 2b */
+/* UFS_SRAM_CON (0x10006000+0x380) */
+#define UFS_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define UFS_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define UFS_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */
+#define UFS_SRAM_PDN_LSB (1U << 16) /* 5b */
+/* DEVAPC_IFR_SRAM_CON (0x10006000+0x384) */
+#define DEVAPC_IFR_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DEVAPC_IFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DEVAPC_IFR_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */
+#define DEVAPC_IFR_SRAM_PDN_LSB (1U << 16) /* 6b */
+/* DEVAPC_SUBIFR_SRAM_CON (0x10006000+0x388) */
+#define DEVAPC_SUBIFR_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DEVAPC_SUBIFR_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DEVAPC_SUBIFR_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */
+#define DEVAPC_SUBIFR_SRAM_PDN_LSB (1U << 16) /* 6b */
+/* DEVAPC_ACP_SRAM_CON (0x10006000+0x38C) */
+#define DEVAPC_ACP_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DEVAPC_ACP_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DEVAPC_ACP_SRAM_SLEEP_B_LSB (1U << 4) /* 6b */
+#define DEVAPC_ACP_SRAM_PDN_LSB (1U << 16) /* 6b */
+/* USB_SRAM_CON (0x10006000+0x390) */
+#define USB_SRAM_PDN_LSB (1U << 0) /* 7b */
+/* DUMMY_SRAM_CON (0x10006000+0x394) */
+#define DUMMY_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DUMMY_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DUMMY_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */
+#define DUMMY_SRAM_PDN_LSB (1U << 16) /* 8b */
+/* MD_EXT_BUCK_ISO_CON (0x10006000+0x398) */
+#define VMODEM_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */
+#define VMD_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */
+/* EXT_BUCK_ISO (0x10006000+0x39C) */
+#define VIMVO_EXT_BUCK_ISO_LSB (1U << 0) /* 1b */
+#define GPU_EXT_BUCK_ISO_LSB (1U << 1) /* 1b */
+#define IPU_EXT_BUCK_ISO_LSB (1U << 5) /* 3b */
+/* DXCC_SRAM_CON (0x10006000+0x3A0) */
+#define DXCC_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DXCC_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DXCC_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define DXCC_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* MSDC_SRAM_CON (0x10006000+0x3A4) */
+#define MSDC_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define MSDC_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define MSDC_SRAM_SLEEP_B_LSB (1U << 4) /* 5b */
+#define MSDC_SRAM_PDN_LSB (1U << 16) /* 5b */
+/* DEBUGTOP_SRAM_CON (0x10006000+0x3A8) */
+#define DEBUGTOP_SRAM_PDN_LSB (1U << 0) /* 1b */
+/* DP_TX_PWR_CON (0x10006000+0x3AC) */
+#define DP_TX_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DP_TX_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DP_TX_PWR_ON_LSB (1U << 2) /* 1b */
+#define DP_TX_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DP_TX_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define DP_TX_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_DP_TX_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* DPMAIF_SRAM_CON (0x10006000+0x3B0) */
+#define DPMAIF_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DPMAIF_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DPMAIF_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define DPMAIF_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* DPY_SHU2_SRAM_CON (0x10006000+0x3B4) */
+#define DPY_SHU2_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DPY_SHU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DPY_SHU2_SRAM_SLEEP_B_LSB (1U << 4) /* 2b */
+#define DPY_SHU2_SRAM_PDN_LSB (1U << 16) /* 2b */
+/* DRAMC_MCU2_SRAM_CON (0x10006000+0x3B8) */
+#define DRAMC_MCU2_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DRAMC_MCU2_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DRAMC_MCU2_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define DRAMC_MCU2_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* DRAMC_MCU_SRAM_CON (0x10006000+0x3BC) */
+#define DRAMC_MCU_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define DRAMC_MCU_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define DRAMC_MCU_SRAM_SLEEP_B_LSB (1U << 4) /* 1b */
+#define DRAMC_MCU_SRAM_PDN_LSB (1U << 16) /* 1b */
+/* MCUPM_SRAM_CON (0x10006000+0x3C0) */
+#define MCUPM_SRAM_CKISO_LSB (1U << 0) /* 1b */
+#define MCUPM_SRAM_ISOINT_B_LSB (1U << 1) /* 1b */
+#define MCUPM_SRAM_SLEEP_B_LSB (1U << 4) /* 8b */
+#define MCUPM_SRAM_PDN_LSB (1U << 16) /* 8b */
+/* DPY2_PWR_CON (0x10006000+0x3C4) */
+#define DPY2_PWR_RST_B_LSB (1U << 0) /* 1b */
+#define DPY2_PWR_ISO_LSB (1U << 1) /* 1b */
+#define DPY2_PWR_ON_LSB (1U << 2) /* 1b */
+#define DPY2_PWR_ON_2ND_LSB (1U << 3) /* 1b */
+#define DPY2_PWR_CLK_DIS_LSB (1U << 4) /* 1b */
+#define DPY2_SRAM_PDN_LSB (1U << 8) /* 1b */
+#define SC_DPY2_SRAM_PDN_ACK_LSB (1U << 12) /* 1b */
+/* SPM_MEM_CK_SEL (0x10006000+0x400) */
+#define SC_MEM_CK_SEL_LSB (1U << 0) /* 1b */
+#define SPM2CKSYS_MEM_CK_MUX_UPDATE_LSB (1U << 1) /* 1b */
+/* SPM_BUS_PROTECT_MASK_B (0x10006000+0X404) */
+#define SPM_BUS_PROTECT_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT1_MASK_B (0x10006000+0x408) */
+#define SPM_BUS_PROTECT1_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT2_MASK_B (0x10006000+0x40C) */
+#define SPM_BUS_PROTECT2_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT3_MASK_B (0x10006000+0x410) */
+#define SPM_BUS_PROTECT3_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT4_MASK_B (0x10006000+0x414) */
+#define SPM_BUS_PROTECT4_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_EMI_BW_MODE (0x10006000+0x418) */
+#define EMI_BW_MODE_LSB (1U << 0) /* 1b */
+#define EMI_BOOST_MODE_LSB (1U << 1) /* 1b */
+#define EMI_BW_MODE_2_LSB (1U << 2) /* 1b */
+#define EMI_BOOST_MODE_2_LSB (1U << 3) /* 1b */
+/* AP2MD_PEER_WAKEUP (0x10006000+0x41C) */
+#define AP2MD_PEER_WAKEUP_LSB (1U << 0) /* 1b */
+/* ULPOSC_CON (0x10006000+0x420) */
+#define ULPOSC_EN_LSB (1U << 0) /* 1b */
+#define ULPOSC_RST_LSB (1U << 1) /* 1b */
+#define ULPOSC_CG_EN_LSB (1U << 2) /* 1b */
+#define ULPOSC_CLK_SEL_LSB (1U << 3) /* 1b */
+/* SPM2MM_CON (0x10006000+0x424) */
+#define SPM2MM_FORCE_ULTRA_LSB (1U << 0) /* 1b */
+#define SPM2MM_DBL_OSTD_ACT_LSB (1U << 1) /* 1b */
+#define SPM2MM_ULTRAREQ_LSB (1U << 2) /* 1b */
+#define SPM2MD_ULTRAREQ_LSB (1U << 3) /* 1b */
+#define SPM2ISP_ULTRAREQ_LSB (1U << 4) /* 1b */
+#define MM2SPM_FORCE_ULTRA_ACK_D2T_LSB (1U << 16) /* 1b */
+#define MM2SPM_DBL_OSTD_ACT_ACK_D2T_LSB (1U << 17) /* 1b */
+#define SPM2ISP_ULTRAACK_D2T_LSB (1U << 18) /* 1b */
+#define SPM2MM_ULTRAACK_D2T_LSB (1U << 19) /* 1b */
+#define SPM2MD_ULTRAACK_D2T_LSB (1U << 20) /* 1b */
+/* SPM_BUS_PROTECT5_MASK_B (0x10006000+0x428) */
+#define SPM_BUS_PROTECT5_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM2MCUPM_CON (0x10006000+0x42C) */
+#define SPM2MCUPM_SW_RST_B_LSB (1U << 0) /* 1b */
+#define SPM2MCUPM_SW_INT_LSB (1U << 1) /* 1b */
+/* AP_MDSRC_REQ (0x10006000+0x430) */
+#define AP_MDSMSRC_REQ_LSB (1U << 0) /* 1b */
+#define AP_L1SMSRC_REQ_LSB (1U << 1) /* 1b */
+#define AP_MD2SRC_REQ_LSB (1U << 2) /* 1b */
+#define AP_MDSMSRC_ACK_LSB (1U << 4) /* 1b */
+#define AP_L1SMSRC_ACK_LSB (1U << 5) /* 1b */
+#define AP_MD2SRC_ACK_LSB (1U << 6) /* 1b */
+/* SPM2EMI_ENTER_ULPM (0x10006000+0x434) */
+#define SPM2EMI_ENTER_ULPM_LSB (1U << 0) /* 1b */
+/* SPM2MD_DVFS_CON (0x10006000+0x438) */
+#define SPM2MD_DVFS_CON_LSB (1U << 0) /* 32b */
+/* MD2SPM_DVFS_CON (0x10006000+0x43C) */
+#define MD2SPM_DVFS_CON_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT6_MASK_B (0x10006000+0X440) */
+#define SPM_BUS_PROTECT6_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT7_MASK_B (0x10006000+0x444) */
+#define SPM_BUS_PROTECT7_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_BUS_PROTECT8_MASK_B (0x10006000+0x448) */
+#define SPM_BUS_PROTECT8_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_PLL_CON (0x10006000+0x44C) */
+#define SC_MAINPLLOUT_OFF_LSB (1U << 0) /* 1b */
+#define SC_UNIPLLOUT_OFF_LSB (1U << 1) /* 1b */
+#define SC_MAINPLL_OFF_LSB (1U << 4) /* 1b */
+#define SC_UNIPLL_OFF_LSB (1U << 5) /* 1b */
+#define SC_MAINPLL_S_OFF_LSB (1U << 8) /* 1b */
+#define SC_UNIPLL_S_OFF_LSB (1U << 9) /* 1b */
+#define SC_SMI_CK_OFF_LSB (1U << 16) /* 1b */
+#define SC_MD32K_CK_OFF_LSB (1U << 17) /* 1b */
+#define SC_CKSQ1_OFF_LSB (1U << 18) /* 1b */
+#define SC_AXI_MEM_CK_OFF_LSB (1U << 19) /* 1b */
+/* CPU_DVFS_REQ (0x10006000+0x450) */
+#define CPU_DVFS_REQ_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_SW_CON_0 (0x10006000+0x454) */
+#define SW_DDR_PST_REQ_LSB (1U << 0) /* 2b */
+#define SW_DDR_PST_ABORT_REQ_LSB (1U << 2) /* 2b */
+/* SPM_DRAM_MCU_SW_CON_1 (0x10006000+0x458) */
+#define SW_DDR_PST_CH0_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_SW_CON_2 (0x10006000+0x45C) */
+#define SW_DDR_PST_CH1_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_SW_CON_3 (0x10006000+0x460) */
+#define SW_DDR_RESERVED_CH0_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_SW_CON_4 (0x10006000+0x464) */
+#define SW_DDR_RESERVED_CH1_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_STA_0 (0x10006000+0x468) */
+#define SC_DDR_PST_ACK_LSB (1U << 0) /* 2b */
+#define SC_DDR_PST_ABORT_ACK_LSB (1U << 2) /* 2b */
+/* SPM_DRAM_MCU_STA_1 (0x10006000+0x46C) */
+#define SC_DDR_CUR_PST_STA_CH0_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_STA_2 (0x10006000+0x470) */
+#define SC_DDR_CUR_PST_STA_CH1_LSB (1U << 0) /* 32b */
+/* SPM_DRAM_MCU_SW_SEL_0 (0x10006000+0x474) */
+#define SW_DDR_PST_REQ_SEL_LSB (1U << 0) /* 2b */
+#define SW_DDR_PST_SEL_LSB (1U << 2) /* 2b */
+#define SW_DDR_PST_ABORT_REQ_SEL_LSB (1U << 4) /* 2b */
+#define SW_DDR_RESERVED_SEL_LSB (1U << 6) /* 2b */
+#define SW_DDR_PST_ACK_SEL_LSB (1U << 8) /* 2b */
+#define SW_DDR_PST_ABORT_ACK_SEL_LSB (1U << 10) /* 2b */
+/* RELAY_DVFS_LEVEL (0x10006000+0x478) */
+#define RELAY_DVFS_LEVEL_LSB (1U << 0) /* 32b */
+/* DRAMC_DPY_CLK_SW_CON_0 (0x10006000+0x480) */
+#define SW_PHYPLL_EN_LSB (1U << 0) /* 2b */
+#define SW_DPY_VREF_EN_LSB (1U << 2) /* 2b */
+#define SW_DPY_DLL_CK_EN_LSB (1U << 4) /* 2b */
+#define SW_DPY_DLL_EN_LSB (1U << 6) /* 2b */
+#define SW_DPY_2ND_DLL_EN_LSB (1U << 8) /* 2b */
+#define SW_MEM_CK_OFF_LSB (1U << 10) /* 2b */
+#define SW_DMSUS_OFF_LSB (1U << 12) /* 2b */
+#define SW_DPY_MODE_SW_LSB (1U << 14) /* 2b */
+#define SW_EMI_CLK_OFF_LSB (1U << 16) /* 2b */
+#define SW_DDRPHY_FB_CK_EN_LSB (1U << 18) /* 2b */
+#define SW_DR_GATE_RETRY_EN_LSB (1U << 20) /* 2b */
+#define SW_DPHY_PRECAL_UP_LSB (1U << 24) /* 2b */
+#define SW_DPY_BCLK_ENABLE_LSB (1U << 26) /* 2b */
+#define SW_TX_TRACKING_DIS_LSB (1U << 28) /* 2b */
+#define SW_DPHY_RXDLY_TRACKING_EN_LSB (1U << 30) /* 2b */
+/* DRAMC_DPY_CLK_SW_CON_1 (0x10006000+0x484) */
+#define SW_SHU_RESTORE_LSB (1U << 0) /* 2b */
+#define SW_DMYRD_MOD_LSB (1U << 2) /* 2b */
+#define SW_DMYRD_INTV_LSB (1U << 4) /* 2b */
+#define SW_DMYRD_EN_LSB (1U << 6) /* 2b */
+#define SW_DRS_DIS_REQ_LSB (1U << 8) /* 2b */
+#define SW_DR_SRAM_LOAD_LSB (1U << 10) /* 2b */
+#define SW_DR_SRAM_RESTORE_LSB (1U << 12) /* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_LATCH_LSB (1U << 14) /* 2b */
+#define SW_TX_TRACK_RETRY_EN_LSB (1U << 16) /* 2b */
+#define SW_DPY_MIDPI_EN_LSB (1U << 18) /* 2b */
+#define SW_DPY_PI_RESETB_EN_LSB (1U << 20) /* 2b */
+#define SW_DPY_MCK8X_EN_LSB (1U << 22) /* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_CH0_LSB (1U << 24) /* 4b */
+#define SW_DR_SHU_LEVEL_SRAM_CH1_LSB (1U << 28) /* 4b */
+/* DRAMC_DPY_CLK_SW_CON_2 (0x10006000+0x488) */
+#define SW_DR_SHU_LEVEL_LSB (1U << 0) /* 2b */
+#define SW_DR_SHU_EN_LSB (1U << 2) /* 1b */
+#define SW_DR_SHORT_QUEUE_LSB (1U << 3) /* 1b */
+#define SW_PHYPLL_MODE_SW_LSB (1U << 4) /* 1b */
+#define SW_PHYPLL2_MODE_SW_LSB (1U << 5) /* 1b */
+#define SW_PHYPLL_SHU_EN_LSB (1U << 6) /* 1b */
+#define SW_PHYPLL2_SHU_EN_LSB (1U << 7) /* 1b */
+#define SW_DR_RESERVED_0_LSB (1U << 24) /* 2b */
+#define SW_DR_RESERVED_1_LSB (1U << 26) /* 2b */
+#define SW_DR_RESERVED_2_LSB (1U << 28) /* 2b */
+#define SW_DR_RESERVED_3_LSB (1U << 30) /* 2b */
+/* DRAMC_DPY_CLK_SW_CON_3 (0x10006000+0x48C) */
+#define SC_DR_SHU_EN_ACK_LSB (1U << 0) /* 4b */
+#define SC_EMI_CLK_OFF_ACK_LSB (1U << 4) /* 4b */
+#define SC_DR_SHORT_QUEUE_ACK_LSB (1U << 8) /* 4b */
+#define SC_DRAMC_DFS_STA_LSB (1U << 12) /* 4b */
+#define SC_DRS_DIS_ACK_LSB (1U << 16) /* 4b */
+#define SC_DR_SRAM_LOAD_ACK_LSB (1U << 20) /* 4b */
+#define SC_DR_SRAM_PLL_LOAD_ACK_LSB (1U << 24) /* 4b */
+#define SC_DR_SRAM_RESTORE_ACK_LSB (1U << 28) /* 4b */
+/* DRAMC_DPY_CLK_SW_SEL_0 (0x10006000+0x490) */
+#define SW_PHYPLL_EN_SEL_LSB (1U << 0) /* 2b */
+#define SW_DPY_VREF_EN_SEL_LSB (1U << 2) /* 2b */
+#define SW_DPY_DLL_CK_EN_SEL_LSB (1U << 4) /* 2b */
+#define SW_DPY_DLL_EN_SEL_LSB (1U << 6) /* 2b */
+#define SW_DPY_2ND_DLL_EN_SEL_LSB (1U << 8) /* 2b */
+#define SW_MEM_CK_OFF_SEL_LSB (1U << 10) /* 2b */
+#define SW_DMSUS_OFF_SEL_LSB (1U << 12) /* 2b */
+#define SW_DPY_MODE_SW_SEL_LSB (1U << 14) /* 2b */
+#define SW_EMI_CLK_OFF_SEL_LSB (1U << 16) /* 2b */
+#define SW_DDRPHY_FB_CK_EN_SEL_LSB (1U << 18) /* 2b */
+#define SW_DR_GATE_RETRY_EN_SEL_LSB (1U << 20) /* 2b */
+#define SW_DPHY_PRECAL_UP_SEL_LSB (1U << 24) /* 2b */
+#define SW_DPY_BCLK_ENABLE_SEL_LSB (1U << 26) /* 2b */
+#define SW_TX_TRACKING_DIS_SEL_LSB (1U << 28) /* 2b */
+#define SW_DPHY_RXDLY_TRACKING_EN_SEL_LSB (1U << 30) /* 2b */
+/* DRAMC_DPY_CLK_SW_SEL_1 (0x10006000+0x494) */
+#define SW_SHU_RESTORE_SEL_LSB (1U << 0) /* 2b */
+#define SW_DMYRD_MOD_SEL_LSB (1U << 2) /* 2b */
+#define SW_DMYRD_INTV_SEL_LSB (1U << 4) /* 2b */
+#define SW_DMYRD_EN_SEL_LSB (1U << 6) /* 2b */
+#define SW_DRS_DIS_REQ_SEL_LSB (1U << 8) /* 2b */
+#define SW_DR_SRAM_LOAD_SEL_LSB (1U << 10) /* 2b */
+#define SW_DR_SRAM_RESTORE_SEL_LSB (1U << 12) /* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_LATCH_SEL_LSB (1U << 14) /* 2b */
+#define SW_TX_TRACK_RETRY_EN_SEL_LSB (1U << 16) /* 2b */
+#define SW_DPY_MIDPI_EN_SEL_LSB (1U << 18) /* 2b */
+#define SW_DPY_PI_RESETB_EN_SEL_LSB (1U << 20) /* 2b */
+#define SW_DPY_MCK8X_EN_SEL_LSB (1U << 22) /* 2b */
+#define SW_DR_SHU_LEVEL_SRAM_SEL_LSB (1U << 24) /* 2b */
+/* DRAMC_DPY_CLK_SW_SEL_2 (0x10006000+0x498) */
+#define SW_DR_SHU_LEVEL_SEL_LSB (1U << 0) /* 1b */
+#define SW_DR_SHU_EN_SEL_LSB (1U << 2) /* 1b */
+#define SW_DR_SHORT_QUEUE_SEL_LSB (1U << 3) /* 1b */
+#define SW_PHYPLL_MODE_SW_SEL_LSB (1U << 4) /* 1b */
+#define SW_PHYPLL2_MODE_SW_SEL_LSB (1U << 5) /* 1b */
+#define SW_PHYPLL_SHU_EN_SEL_LSB (1U << 6) /* 1b */
+#define SW_PHYPLL2_SHU_EN_SEL_LSB (1U << 7) /* 1b */
+#define SW_DR_RESERVED_0_SEL_LSB (1U << 24) /* 2b */
+#define SW_DR_RESERVED_1_SEL_LSB (1U << 26) /* 2b */
+#define SW_DR_RESERVED_2_SEL_LSB (1U << 28) /* 2b */
+#define SW_DR_RESERVED_3_SEL_LSB (1U << 30) /* 2b */
+/* DRAMC_DPY_CLK_SW_SEL_3 (0x10006000+0x49C) */
+#define SC_DR_SHU_EN_ACK_SEL_LSB (1U << 0) /* 4b */
+#define SC_EMI_CLK_OFF_ACK_SEL_LSB (1U << 4) /* 4b */
+#define SC_DR_SHORT_QUEUE_ACK_SEL_LSB (1U << 8) /* 4b */
+#define SC_DRAMC_DFS_STA_SEL_LSB (1U << 12) /* 4b */
+#define SC_DRS_DIS_ACK_SEL_LSB (1U << 16) /* 4b */
+#define SC_DR_SRAM_LOAD_ACK_SEL_LSB (1U << 20) /* 4b */
+#define SC_DR_SRAM_PLL_LOAD_ACK_SEL_LSB (1U << 24) /* 4b */
+#define SC_DR_SRAM_RESTORE_ACK_SEL_LSB (1U << 28) /* 4b */
+/* DRAMC_DPY_CLK_SPM_CON (0x10006000+0x4A0) */
+#define SC_DMYRD_EN_MOD_SEL_PCM_LSB (1U << 0) /* 1b */
+#define SC_DMYRD_INTV_SEL_PCM_LSB (1U << 1) /* 1b */
+#define SC_DMYRD_EN_PCM_LSB (1U << 2) /* 1b */
+#define SC_DRS_DIS_REQ_PCM_LSB (1U << 3) /* 1b */
+#define SC_DR_SHU_LEVEL_SRAM_PCM_LSB (1U << 4) /* 4b */
+#define SC_DR_GATE_RETRY_EN_PCM_LSB (1U << 8) /* 1b */
+#define SC_DR_SHORT_QUEUE_PCM_LSB (1U << 9) /* 1b */
+#define SC_DPY_MIDPI_EN_PCM_LSB (1U << 10) /* 1b */
+#define SC_DPY_PI_RESETB_EN_PCM_LSB (1U << 11) /* 1b */
+#define SC_DPY_MCK8X_EN_PCM_LSB (1U << 12) /* 1b */
+#define SC_DR_RESERVED_0_PCM_LSB (1U << 13) /* 1b */
+#define SC_DR_RESERVED_1_PCM_LSB (1U << 14) /* 1b */
+#define SC_DR_RESERVED_2_PCM_LSB (1U << 15) /* 1b */
+#define SC_DR_RESERVED_3_PCM_LSB (1U << 16) /* 1b */
+#define SC_DMDRAMCSHU_ACK_ALL_LSB (1U << 24) /* 1b */
+#define SC_EMI_CLK_OFF_ACK_ALL_LSB (1U << 25) /* 1b */
+#define SC_DR_SHORT_QUEUE_ACK_ALL_LSB (1U << 26) /* 1b */
+#define SC_DRAMC_DFS_STA_ALL_LSB (1U << 27) /* 1b */
+#define SC_DRS_DIS_ACK_ALL_LSB (1U << 28) /* 1b */
+#define SC_DR_SRAM_LOAD_ACK_ALL_LSB (1U << 29) /* 1b */
+#define SC_DR_SRAM_PLL_LOAD_ACK_ALL_LSB (1U << 30) /* 1b */
+#define SC_DR_SRAM_RESTORE_ACK_ALL_LSB (1U << 31) /* 1b */
+/* SPM_DVFS_LEVEL (0x10006000+0x4A4) */
+#define SPM_DVFS_LEVEL_LSB (1U << 0) /* 32b */
+/* SPM_CIRQ_CON (0x10006000+0x4A8) */
+#define CIRQ_CLK_SEL_LSB (1U << 0) /* 1b */
+/* SPM_DVFS_MISC (0x10006000+0x4AC) */
+#define MSDC_DVFS_REQUEST_LSB (1U << 0) /* 1b */
+#define SPM2EMI_SLP_PROT_EN_LSB (1U << 1) /* 1b */
+#define SPM_DVFS_FORCE_ENABLE_LSB (1U << 2) /* 1b */
+#define FORCE_DVFS_WAKE_LSB (1U << 3) /* 1b */
+#define SPM_DVFSRC_ENABLE_LSB (1U << 4) /* 1b */
+#define SPM_DVFS_DONE_LSB (1U << 5) /* 1b */
+#define DVFSRC_IRQ_WAKEUP_EVENT_MASK_LSB (1U << 6) /* 1b */
+#define SPM2RC_EVENT_ABORT_LSB (1U << 7) /* 1b */
+#define EMI_SLP_IDLE_LSB (1U << 14) /* 1b */
+#define SDIO_READY_TO_SPM_LSB (1U << 15) /* 1b */
+/* SPM_VS1_VS2_RC_CON (0x10006000+0x4B0) */
+#define VS1_INIT_LEVEL_LSB (1U << 0) /* 2b */
+#define VS1_INIT_LSB (1U << 2) /* 1b */
+#define VS1_CURR_LEVEL_LSB (1U << 3) /* 2b */
+#define VS1_NEXT_LEVEL_LSB (1U << 5) /* 2b */
+#define VS1_VOTE_LEVEL_LSB (1U << 7) /* 2b */
+#define VS1_TRIGGER_LSB (1U << 9) /* 1b */
+#define VS2_INIT_LEVEL_LSB (1U << 10) /* 3b */
+#define VS2_INIT_LSB (1U << 13) /* 1b */
+#define VS2_CURR_LEVEL_LSB (1U << 14) /* 3b */
+#define VS2_NEXT_LEVEL_LSB (1U << 17) /* 3b */
+#define VS2_VOTE_LEVEL_LSB (1U << 20) /* 3b */
+#define VS2_TRIGGER_LSB (1U << 23) /* 1b */
+#define VS1_FORCE_LSB (1U << 24) /* 1b */
+#define VS2_FORCE_LSB (1U << 25) /* 1b */
+#define VS1_VOTE_LEVEL_FORCE_LSB (1U << 26) /* 2b */
+#define VS2_VOTE_LEVEL_FORCE_LSB (1U << 28) /* 3b */
+/* RG_MODULE_SW_CG_0_MASK_REQ_0 (0x10006000+0x4B4) */
+#define RG_MODULE_SW_CG_0_MASK_REQ_0_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_0_MASK_REQ_1 (0x10006000+0x4B8) */
+#define RG_MODULE_SW_CG_0_MASK_REQ_1_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_0_MASK_REQ_2 (0x10006000+0x4BC) */
+#define RG_MODULE_SW_CG_0_MASK_REQ_2_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_1_MASK_REQ_0 (0x10006000+0x4C0) */
+#define RG_MODULE_SW_CG_1_MASK_REQ_0_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_1_MASK_REQ_1 (0x10006000+0x4C4) */
+#define RG_MODULE_SW_CG_1_MASK_REQ_1_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_1_MASK_REQ_2 (0x10006000+0x4C8) */
+#define RG_MODULE_SW_CG_1_MASK_REQ_2_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_2_MASK_REQ_0 (0x10006000+0x4CC) */
+#define RG_MODULE_SW_CG_2_MASK_REQ_0_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_2_MASK_REQ_1 (0x10006000+0x4D0) */
+#define RG_MODULE_SW_CG_2_MASK_REQ_1_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_2_MASK_REQ_2 (0x10006000+0x4D4) */
+#define RG_MODULE_SW_CG_2_MASK_REQ_2_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_3_MASK_REQ_0 (0x10006000+0x4D8) */
+#define RG_MODULE_SW_CG_3_MASK_REQ_0_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_3_MASK_REQ_1 (0x10006000+0x4DC) */
+#define RG_MODULE_SW_CG_3_MASK_REQ_1_LSB (1U << 0) /* 32b */
+/* RG_MODULE_SW_CG_3_MASK_REQ_2 (0x10006000+0x4E0) */
+#define RG_MODULE_SW_CG_3_MASK_REQ_2_LSB (1U << 0) /* 32b */
+/* PWR_STATUS_MASK_REQ_0 (0x10006000+0x4E4) */
+#define PWR_STATUS_MASK_REQ_0_LSB (1U << 0) /* 32b */
+/* PWR_STATUS_MASK_REQ_1 (0x10006000+0x4E8) */
+#define PWR_STATUS_MASK_REQ_1_LSB (1U << 0) /* 32b */
+/* PWR_STATUS_MASK_REQ_2 (0x10006000+0x4EC) */
+#define PWR_STATUS_MASK_REQ_2_LSB (1U << 0) /* 32b */
+/* SPM_CG_CHECK_CON (0x10006000+0x4F0) */
+#define APMIXEDSYS_BUSY_MASK_REQ_0_LSB (1U << 0) /* 5b */
+#define APMIXEDSYS_BUSY_MASK_REQ_1_LSB (1U << 8) /* 5b */
+#define APMIXEDSYS_BUSY_MASK_REQ_2_LSB (1U << 16) /* 5b */
+#define AUDIOSYS_BUSY_MASK_REQ_0_LSB (1U << 24) /* 1b */
+#define AUDIOSYS_BUSY_MASK_REQ_1_LSB (1U << 25) /* 1b */
+#define AUDIOSYS_BUSY_MASK_REQ_2_LSB (1U << 26) /* 1b */
+#define SSUSB_BUSY_MASK_REQ_0_LSB (1U << 27) /* 1b */
+#define SSUSB_BUSY_MASK_REQ_1_LSB (1U << 28) /* 1b */
+#define SSUSB_BUSY_MASK_REQ_2_LSB (1U << 29) /* 1b */
+/* SPM_SRC_RDY_STA (0x10006000+0x4F4) */
+#define SPM_INFRA_INTERNAL_ACK_LSB (1U << 0) /* 1b */
+#define SPM_VRF18_INTERNAL_ACK_LSB (1U << 1) /* 1b */
+/* SPM_DVS_DFS_LEVEL (0x10006000+0x4F8) */
+#define SPM_DFS_LEVEL_LSB (1U << 0) /* 16b */
+#define SPM_DVS_LEVEL_LSB (1U << 16) /* 16b */
+/* SPM_FORCE_DVFS (0x10006000+0x4FC) */
+#define FORCE_DVFS_LEVEL_LSB (1U << 0) /* 32b */
+/* SRCLKEN_RC_CFG (0x10006000+0x500) */
+#define SRCLKEN_RC_CFG_LSB (1U << 0) /* 32b */
+/* RC_CENTRAL_CFG1 (0x10006000+0x504) */
+#define RC_CENTRAL_CFG1_LSB (1U << 0) /* 32b */
+/* RC_CENTRAL_CFG2 (0x10006000+0x508) */
+#define RC_CENTRAL_CFG2_LSB (1U << 0) /* 32b */
+/* RC_CMD_ARB_CFG (0x10006000+0x50C) */
+#define RC_CMD_ARB_CFG_LSB (1U << 0) /* 32b */
+/* RC_PMIC_RCEN_ADDR (0x10006000+0x510) */
+#define RC_PMIC_RCEN_ADDR_LSB (1U << 0) /* 16b */
+#define RC_PMIC_RCEN_RESERVE_LSB (1U << 16) /* 16b */
+/* RC_PMIC_RCEN_SET_CLR_ADDR (0x10006000+0x514) */
+#define RC_PMIC_RCEN_SET_ADDR_LSB (1U << 0) /* 16b */
+#define RC_PMIC_RCEN_CLR_ADDR_LSB (1U << 16) /* 16b */
+/* RC_DCXO_FPM_CFG (0x10006000+0x518) */
+#define RC_DCXO_FPM_CFG_LSB (1U << 0) /* 32b */
+/* RC_CENTRAL_CFG3 (0x10006000+0x51C) */
+#define RC_CENTRAL_CFG3_LSB (1U << 0) /* 32b */
+/* RC_M00_SRCLKEN_CFG (0x10006000+0x520) */
+#define RC_M00_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+#define RC_SW_SRCLKEN_RC (1U << 3) /* 1b */
+#define RC_SW_SRCLKEN_FPM (1U << 4) /* 1b */
+/* RC_M01_SRCLKEN_CFG (0x10006000+0x524) */
+#define RC_M01_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M02_SRCLKEN_CFG (0x10006000+0x528) */
+#define RC_M02_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M03_SRCLKEN_CFG (0x10006000+0x52C) */
+#define RC_M03_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M04_SRCLKEN_CFG (0x10006000+0x530) */
+#define RC_M04_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M05_SRCLKEN_CFG (0x10006000+0x534) */
+#define RC_M05_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M06_SRCLKEN_CFG (0x10006000+0x538) */
+#define RC_M06_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M07_SRCLKEN_CFG (0x10006000+0x53C) */
+#define RC_M07_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M08_SRCLKEN_CFG (0x10006000+0x540) */
+#define RC_M08_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M09_SRCLKEN_CFG (0x10006000+0x544) */
+#define RC_M09_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M10_SRCLKEN_CFG (0x10006000+0x548) */
+#define RC_M10_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M11_SRCLKEN_CFG (0x10006000+0x54C) */
+#define RC_M11_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_M12_SRCLKEN_CFG (0x10006000+0x550) */
+#define RC_M12_SRCLKEN_CFG_LSB (1U << 0) /* 32b */
+/* RC_SRCLKEN_SW_CON_CFG (0x10006000+0x554) */
+#define RC_SRCLKEN_SW_CON_CFG_LSB (1U << 0) /* 32b */
+/* RC_CENTRAL_CFG4 (0x10006000+0x558) */
+#define RC_CENTRAL_CFG4_LSB (1U << 0) /* 32b */
+/* RC_PROTOCOL_CHK_CFG (0x10006000+0x560) */
+#define RC_PROTOCOL_CHK_CFG_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_CFG (0x10006000+0x564) */
+#define RC_DEBUG_CFG_LSB (1U << 0) /* 32b */
+/* RC_MISC_0 (0x10006000+0x5B4) */
+#define SRCCLKENO_LSB (1U << 0) /* 2b */
+#define PCM_SRCCLKENO_LSB (1U << 3) /* 2b */
+#define RC_VREQ_LSB (1U << 5) /* 1b */
+#define RC_SPM_SRCCLKENO_0_ACK_LSB (1U << 6) /* 1b */
+/* RC_SPM_CTRL (0x10006000+0x448) */
+#define SPM_AP_26M_RDY_LSB (1U << 0) /* 1b */
+#define KEEP_RC_SPI_ACTIVE_LSB (1U << 1) /* 1b */
+#define SPM2RC_DMY_CTRL_LSB (1U << 2) /* 6b */
+/* SUBSYS_INTF_CFG (0x10006000+0x5BC) */
+#define SRCLKEN_FPM_MASK_B_LSB (1U << 0) /* 13b */
+#define SRCLKEN_BBLPM_MASK_B_LSB (1U << 16) /* 13b */
+/* PCM_WDT_LATCH_25 (0x10006000+0x5C0) */
+#define PCM_WDT_LATCH_25_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_26 (0x10006000+0x5C4) */
+#define PCM_WDT_LATCH_26_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_27 (0x10006000+0x5C8) */
+#define PCM_WDT_LATCH_27_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_28 (0x10006000+0x5CC) */
+#define PCM_WDT_LATCH_28_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_29 (0x10006000+0x5D0) */
+#define PCM_WDT_LATCH_29_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_30 (0x10006000+0x5D4) */
+#define PCM_WDT_LATCH_30_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_31 (0x10006000+0x5D8) */
+#define PCM_WDT_LATCH_31_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_32 (0x10006000+0x5DC) */
+#define PCM_WDT_LATCH_32_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_33 (0x10006000+0x5E0) */
+#define PCM_WDT_LATCH_33_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_34 (0x10006000+0x5E4) */
+#define PCM_WDT_LATCH_34_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_35 (0x10006000+0x5EC) */
+#define PCM_WDT_LATCH_35_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_36 (0x10006000+0x5F0) */
+#define PCM_WDT_LATCH_36_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_37 (0x10006000+0x5F4) */
+#define PCM_WDT_LATCH_37_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_38 (0x10006000+0x5F8) */
+#define PCM_WDT_LATCH_38_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_39 (0x10006000+0x5FC) */
+#define PCM_WDT_LATCH_39_LSB (1U << 0) /* 32b */
+/* SPM_SW_FLAG_0 (0x10006000+0x600) */
+#define SPM_SW_FLAG_LSB (1U << 0) /* 32b */
+/* SPM_SW_DEBUG_0 (0x10006000+0x604) */
+#define SPM_SW_DEBUG_0_LSB (1U << 0) /* 32b */
+/* SPM_SW_FLAG_1 (0x10006000+0x608) */
+#define SPM_SW_FLAG_1_LSB (1U << 0) /* 32b */
+/* SPM_SW_DEBUG_1 (0x10006000+0x60C) */
+#define SPM_SW_DEBUG_1_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_0 (0x10006000+0x610) */
+#define SPM_SW_RSV_0_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_1 (0x10006000+0x614) */
+#define SPM_SW_RSV_1_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_2 (0x10006000+0x618) */
+#define SPM_SW_RSV_2_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_3 (0x10006000+0x61C) */
+#define SPM_SW_RSV_3_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_4 (0x10006000+0x620) */
+#define SPM_SW_RSV_4_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_5 (0x10006000+0x624) */
+#define SPM_SW_RSV_5_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_6 (0x10006000+0x628) */
+#define SPM_SW_RSV_6_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_7 (0x10006000+0x62C) */
+#define SPM_SW_RSV_7_LSB (1U << 0) /* 32b */
+/* SPM_SW_RSV_8 (0x10006000+0x630) */
+#define SPM_SW_RSV_8_LSB (1U << 0) /* 32b */
+/* SPM_BK_WAKE_EVENT (0x10006000+0x634) */
+#define SPM_BK_WAKE_EVENT_LSB (1U << 0) /* 32b */
+/* SPM_BK_VTCXO_DUR (0x10006000+0x638) */
+#define SPM_BK_VTCXO_DUR_LSB (1U << 0) /* 32b */
+/* SPM_BK_WAKE_MISC (0x10006000+0x63C) */
+#define SPM_BK_WAKE_MISC_LSB (1U << 0) /* 32b */
+/* SPM_BK_PCM_TIMER (0x10006000+0x640) */
+#define SPM_BK_PCM_TIMER_LSB (1U << 0) /* 32b */
+/* SPM_RSV_CON_0 (0x10006000+0x650) */
+#define SPM_RSV_CON_0_LSB (1U << 0) /* 32b */
+/* SPM_RSV_CON_1 (0x10006000+0x654) */
+#define SPM_RSV_CON_1_LSB (1U << 0) /* 32b */
+/* SPM_RSV_STA_0 (0x10006000+0x658) */
+#define SPM_RSV_STA_0_LSB (1U << 0) /* 32b */
+/* SPM_RSV_STA_1 (0x10006000+0x65C) */
+#define SPM_RSV_STA_1_LSB (1U << 0) /* 32b */
+/* SPM_SPARE_CON (0x10006000+0x660) */
+#define SPM_SPARE_CON_LSB (1U << 0) /* 32b */
+/* SPM_SPARE_CON_SET (0x10006000+0x664) */
+#define SPM_SPARE_CON_SET_LSB (1U << 0) /* 32b */
+/* SPM_SPARE_CON_CLR (0x10006000+0x668) */
+#define SPM_SPARE_CON_CLR_LSB (1U << 0) /* 32b */
+/* SPM_CROSS_WAKE_M00_REQ (0x10006000+0x66C) */
+#define SPM_CROSS_WAKE_M00_REQ_LSB (1U << 0) /* 4b */
+#define SPM_CROSS_WAKE_M00_CHK_LSB (1U << 4) /* 4b */
+/* SPM_CROSS_WAKE_M01_REQ (0x10006000+0x670) */
+#define SPM_CROSS_WAKE_M01_REQ_LSB (1U << 0) /* 4b */
+#define SPM_CROSS_WAKE_M01_CHK_LSB (1U << 4) /* 4b */
+/* SPM_CROSS_WAKE_M02_REQ (0x10006000+0x674) */
+#define SPM_CROSS_WAKE_M02_REQ_LSB (1U << 0) /* 4b */
+#define SPM_CROSS_WAKE_M02_CHK_LSB (1U << 4) /* 4b */
+/* SPM_CROSS_WAKE_M03_REQ (0x10006000+0x678) */
+#define SPM_CROSS_WAKE_M03_REQ_LSB (1U << 0) /* 4b */
+#define SPM_CROSS_WAKE_M03_CHK_LSB (1U << 4) /* 4b */
+/* SCP_VCORE_LEVEL (0x10006000+0x67C) */
+#define SCP_VCORE_LEVEL_LSB (1U << 0) /* 16b */
+/* SC_MM_CK_SEL_CON (0x10006000+0x680) */
+#define SC_MM_CK_SEL_LSB (1U << 0) /* 4b */
+#define SC_MM_CK_SEL_EN_LSB (1U << 4) /* 1b */
+/* SPARE_ACK_MASK (0x10006000+0x684) */
+#define SPARE_ACK_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_DV_CON_0 (0x10006000+0x68C) */
+#define SPM_DV_CON_0_LSB (1U << 0) /* 32b */
+/* SPM_DV_CON_1 (0x10006000+0x690) */
+#define SPM_DV_CON_1_LSB (1U << 0) /* 32b */
+/* SPM_DV_STA (0x10006000+0x694) */
+#define SPM_DV_STA_LSB (1U << 0) /* 32b */
+/* CONN_XOWCN_DEBUG_EN (0x10006000+0x698) */
+#define CONN_XOWCN_DEBUG_EN_LSB (1U << 0) /* 1b */
+/* SPM_SEMA_M0 (0x10006000+0x69C) */
+#define SPM_SEMA_M0_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M1 (0x10006000+0x6A0) */
+#define SPM_SEMA_M1_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M2 (0x10006000+0x6A4) */
+#define SPM_SEMA_M2_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M3 (0x10006000+0x6A8) */
+#define SPM_SEMA_M3_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M4 (0x10006000+0x6AC) */
+#define SPM_SEMA_M4_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M5 (0x10006000+0x6B0) */
+#define SPM_SEMA_M5_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M6 (0x10006000+0x6B4) */
+#define SPM_SEMA_M6_LSB (1U << 0) /* 8b */
+/* SPM_SEMA_M7 (0x10006000+0x6B8) */
+#define SPM_SEMA_M7_LSB (1U << 0) /* 8b */
+/* SPM2ADSP_MAILBOX (0x10006000+0x6BC) */
+#define SPM2ADSP_MAILBOX_LSB (1U << 0) /* 32b */
+/* ADSP2SPM_MAILBOX (0x10006000+0x6C0) */
+#define ADSP2SPM_MAILBOX_LSB (1U << 0) /* 32b */
+/* SPM_ADSP_IRQ (0x10006000+0x6C4) */
+#define SC_SPM2ADSP_WAKEUP_LSB (1U << 0) /* 1b */
+#define SPM_ADSP_IRQ_SC_ADSP2SPM_WAKEUP_LSB (1U << 4) /* 1b */
+/* SPM_MD32_IRQ (0x10006000+0x6C8) */
+#define SC_SPM2SSPM_WAKEUP_LSB (1U << 0) /* 4b */
+#define SPM_MD32_IRQ_SC_SSPM2SPM_WAKEUP_LSB (1U << 4) /* 4b */
+/* SPM2PMCU_MAILBOX_0 (0x10006000+0x6CC) */
+#define SPM2PMCU_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* SPM2PMCU_MAILBOX_1 (0x10006000+0x6D0) */
+#define SPM2PMCU_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* SPM2PMCU_MAILBOX_2 (0x10006000+0x6D4) */
+#define SPM2PMCU_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* SPM2PMCU_MAILBOX_3 (0x10006000+0x6D8) */
+#define SPM2PMCU_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_MAILBOX_0 (0x10006000+0x6DC) */
+#define PMCU2SPM_MAILBOX_0_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_MAILBOX_1 (0x10006000+0x6E0) */
+#define PMCU2SPM_MAILBOX_1_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_MAILBOX_2 (0x10006000+0x6E4) */
+#define PMCU2SPM_MAILBOX_2_LSB (1U << 0) /* 32b */
+/* PMCU2SPM_MAILBOX_3 (0x10006000+0x6E8) */
+#define PMCU2SPM_MAILBOX_3_LSB (1U << 0) /* 32b */
+/* UFS_PSRI_SW (0x10006000+0x6EC) */
+#define UFS_PSRI_SW_LSB (1U << 0) /* 1b */
+/* UFS_PSRI_SW_SET (0x10006000+0x6F0) */
+#define UFS_PSRI_SW_SET_LSB (1U << 0) /* 1b */
+/* UFS_PSRI_SW_CLR (0x10006000+0x6F4) */
+#define UFS_PSRI_SW_CLR_LSB (1U << 0) /* 1b */
+/* SPM_AP_SEMA (0x10006000+0x6F8) */
+#define SPM_AP_SEMA_LSB (1U << 0) /* 1b */
+/* SPM_SPM_SEMA (0x10006000+0x6FC) */
+#define SPM_SPM_SEMA_LSB (1U << 0) /* 1b */
+/* SPM_DVFS_CON (0x10006000+0x700) */
+#define SPM_DVFS_CON_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CON_STA (0x10006000+0x704) */
+#define SPM_DVFS_CON_STA_LSB (1U << 0) /* 32b */
+/* SPM_PMIC_SPMI_CON (0x10006000+0x708) */
+#define SPM_PMIC_SPMI_CMD_LSB (1U << 0) /* 2b */
+#define SPM_PMIC_SPMI_SLAVEID_LSB (1U << 2) /* 4b */
+#define SPM_PMIC_SPMI_PMIFID_LSB (1U << 6) /* 1b */
+#define SPM_PMIC_SPMI_DBCNT_LSB (1U << 7) /* 1b */
+/* SPM_DVFS_CMD0 (0x10006000+0x710) */
+#define SPM_DVFS_CMD0_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD1 (0x10006000+0x714) */
+#define SPM_DVFS_CMD1_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD2 (0x10006000+0x718) */
+#define SPM_DVFS_CMD2_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD3 (0x10006000+0x71C) */
+#define SPM_DVFS_CMD3_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD4 (0x10006000+0x720) */
+#define SPM_DVFS_CMD4_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD5 (0x10006000+0x724) */
+#define SPM_DVFS_CMD5_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD6 (0x10006000+0x728) */
+#define SPM_DVFS_CMD6_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD7 (0x10006000+0x72C) */
+#define SPM_DVFS_CMD7_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD8 (0x10006000+0x730) */
+#define SPM_DVFS_CMD8_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD9 (0x10006000+0x734) */
+#define SPM_DVFS_CMD9_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD10 (0x10006000+0x738) */
+#define SPM_DVFS_CMD10_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD11 (0x10006000+0x73C) */
+#define SPM_DVFS_CMD11_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD12 (0x10006000+0x740) */
+#define SPM_DVFS_CMD12_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD13 (0x10006000+0x744) */
+#define SPM_DVFS_CMD13_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD14 (0x10006000+0x748) */
+#define SPM_DVFS_CMD14_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD15 (0x10006000+0x74C) */
+#define SPM_DVFS_CMD15_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD16 (0x10006000+0x750) */
+#define SPM_DVFS_CMD16_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD17 (0x10006000+0x754) */
+#define SPM_DVFS_CMD17_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD18 (0x10006000+0x758) */
+#define SPM_DVFS_CMD18_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD19 (0x10006000+0x75C) */
+#define SPM_DVFS_CMD19_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD20 (0x10006000+0x760) */
+#define SPM_DVFS_CMD20_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD21 (0x10006000+0x764) */
+#define SPM_DVFS_CMD21_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD22 (0x10006000+0x768) */
+#define SPM_DVFS_CMD22_LSB (1U << 0) /* 32b */
+/* SPM_DVFS_CMD23 (0x10006000+0x76C) */
+#define SPM_DVFS_CMD23_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_VALUE_L (0x10006000+0x770) */
+#define SYS_TIMER_VALUE_L_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_VALUE_H (0x10006000+0x774) */
+#define SYS_TIMER_VALUE_H_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_START_L (0x10006000+0x778) */
+#define SYS_TIMER_START_L_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_START_H (0x10006000+0x77C) */
+#define SYS_TIMER_START_H_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_00 (0x10006000+0x780) */
+#define SYS_TIMER_LATCH_L_00_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_00 (0x10006000+0x784) */
+#define SYS_TIMER_LATCH_H_00_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_01 (0x10006000+0x788) */
+#define SYS_TIMER_LATCH_L_01_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_01 (0x10006000+0x78C) */
+#define SYS_TIMER_LATCH_H_01_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_02 (0x10006000+0x790) */
+#define SYS_TIMER_LATCH_L_02_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_02 (0x10006000+0x794) */
+#define SYS_TIMER_LATCH_H_02_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_03 (0x10006000+0x798) */
+#define SYS_TIMER_LATCH_L_03_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_03 (0x10006000+0x79C) */
+#define SYS_TIMER_LATCH_H_03_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_04 (0x10006000+0x7A0) */
+#define SYS_TIMER_LATCH_L_04_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_04 (0x10006000+0x7A4) */
+#define SYS_TIMER_LATCH_H_04_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_05 (0x10006000+0x7A8) */
+#define SYS_TIMER_LATCH_L_05_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_05 (0x10006000+0x7AC) */
+#define SYS_TIMER_LATCH_H_05_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_06 (0x10006000+0x7B0) */
+#define SYS_TIMER_LATCH_L_06_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_06 (0x10006000+0x7B4) */
+#define SYS_TIMER_LATCH_H_06_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_07 (0x10006000+0x7B8) */
+#define SYS_TIMER_LATCH_L_07_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_07 (0x10006000+0x7BC) */
+#define SYS_TIMER_LATCH_H_07_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_08 (0x10006000+0x7C0) */
+#define SYS_TIMER_LATCH_L_08_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_08 (0x10006000+0x7C4) */
+#define SYS_TIMER_LATCH_H_08_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_09 (0x10006000+0x7C8) */
+#define SYS_TIMER_LATCH_L_09_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_09 (0x10006000+0x7CC) */
+#define SYS_TIMER_LATCH_H_09_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_10 (0x10006000+0x7D0) */
+#define SYS_TIMER_LATCH_L_10_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_10 (0x10006000+0x7D4) */
+#define SYS_TIMER_LATCH_H_10_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_11 (0x10006000+0x7D8) */
+#define SYS_TIMER_LATCH_L_11_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_11 (0x10006000+0x7DC) */
+#define SYS_TIMER_LATCH_H_11_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_12 (0x10006000+0x7E0) */
+#define SYS_TIMER_LATCH_L_12_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_12 (0x10006000+0x7E4) */
+#define SYS_TIMER_LATCH_H_12_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_13 (0x10006000+0x7E8) */
+#define SYS_TIMER_LATCH_L_13_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_13 (0x10006000+0x7EC) */
+#define SYS_TIMER_LATCH_H_13_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_14 (0x10006000+0x7F0) */
+#define SYS_TIMER_LATCH_L_14_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_14 (0x10006000+0x7F4) */
+#define SYS_TIMER_LATCH_H_14_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_L_15 (0x10006000+0x7F8) */
+#define SYS_TIMER_LATCH_L_15_LSB (1U << 0) /* 32b */
+/* SYS_TIMER_LATCH_H_15 (0x10006000+0x7FC) */
+#define SYS_TIMER_LATCH_H_15_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_0 (0x10006000+0x800) */
+#define PCM_WDT_LATCH_0_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_1 (0x10006000+0x804) */
+#define PCM_WDT_LATCH_1_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_2 (0x10006000+0x808) */
+#define PCM_WDT_LATCH_2_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_3 (0x10006000+0x80C) */
+#define PCM_WDT_LATCH_3_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_4 (0x10006000+0x810) */
+#define PCM_WDT_LATCH_4_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_5 (0x10006000+0x814) */
+#define PCM_WDT_LATCH_5_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_6 (0x10006000+0x818) */
+#define PCM_WDT_LATCH_6_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_7 (0x10006000+0x81C) */
+#define PCM_WDT_LATCH_7_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_8 (0x10006000+0x820) */
+#define PCM_WDT_LATCH_8_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_9 (0x10006000+0x824) */
+#define PCM_WDT_LATCH_9_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_10 (0x10006000+0x828) */
+#define PCM_WDT_LATCH_10_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_11 (0x10006000+0x82C) */
+#define PCM_WDT_LATCH_11_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_12 (0x10006000+0x830) */
+#define PCM_WDT_LATCH_12_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_13 (0x10006000+0x834) */
+#define PCM_WDT_LATCH_13_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_14 (0x10006000+0x838) */
+#define PCM_WDT_LATCH_14_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_15 (0x10006000+0x83C) */
+#define PCM_WDT_LATCH_15_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_16 (0x10006000+0x840) */
+#define PCM_WDT_LATCH_16_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_17 (0x10006000+0x844) */
+#define PCM_WDT_LATCH_17_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_18 (0x10006000+0x848) */
+#define PCM_WDT_LATCH_18_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_SPARE_0 (0x10006000+0x84C) */
+#define PCM_WDT_LATCH_SPARE_0_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_SPARE_1 (0x10006000+0x850) */
+#define PCM_WDT_LATCH_SPARE_1_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_SPARE_2 (0x10006000+0x854) */
+#define PCM_WDT_LATCH_SPARE_2_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_CONN_0 (0x10006000+0x870) */
+#define PCM_WDT_LATCH_CONN_0_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_CONN_1 (0x10006000+0x874) */
+#define PCM_WDT_LATCH_CONN_1_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_CONN_2 (0x10006000+0x878) */
+#define PCM_WDT_LATCH_CONN_2_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_0 (0x10006000+0x8A0) */
+#define DRAMC_GATING_ERR_LATCH_CH0_0_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_1 (0x10006000+0x8A4) */
+#define DRAMC_GATING_ERR_LATCH_CH0_1_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_2 (0x10006000+0x8A8) */
+#define DRAMC_GATING_ERR_LATCH_CH0_2_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_3 (0x10006000+0x8AC) */
+#define DRAMC_GATING_ERR_LATCH_CH0_3_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_4 (0x10006000+0x8B0) */
+#define DRAMC_GATING_ERR_LATCH_CH0_4_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_5 (0x10006000+0x8B4) */
+#define DRAMC_GATING_ERR_LATCH_CH0_5_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_CH0_6 (0x10006000+0x8B8) */
+#define DRAMC_GATING_ERR_LATCH_CH0_6_LSB (1U << 0) /* 32b */
+/* DRAMC_GATING_ERR_LATCH_SPARE_0 (0x10006000+0x8F4) */
+#define DRAMC_GATING_ERR_LATCH_SPARE_0_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON_0 (0x10006000+0x900) */
+#define SPM_ACK_CHK_SW_EN_0_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_0_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_0_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_0_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN_0_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_0_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN_0_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_0_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN_0_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE_0_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL_0_LSB (1U << 15) /* 1b */
+/* SPM_ACK_CHK_PC_0 (0x10006000+0x904) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_0_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_0_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL_0 (0x10006000+0x908) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_0_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_0_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_0_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_0_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER_0 (0x10006000+0x90C) */
+#define SPM_ACK_CHK_TIMER_VAL_0_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER_0_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA_0 (0x10006000+0x910) */
+#define SPM_ACK_CHK_STA_0_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_SWINT_0 (0x10006000+0x914) */
+#define SPM_ACK_CHK_SWINT_EN_0_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON_1 (0x10006000+0x920) */
+#define SPM_ACK_CHK_SW_EN_1_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_1_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_1_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_1_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN_1_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_1_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN_1_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_1_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN_1_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE_1_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL_1_LSB (1U << 15) /* 1b */
+/* SPM_ACK_CHK_PC_1 (0x10006000+0x924) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_1_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_1_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL_1 (0x10006000+0x928) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_1_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_1_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_1_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_1_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER_1 (0x10006000+0x92C) */
+#define SPM_ACK_CHK_TIMER_VAL_1_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER_1_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA_1 (0x10006000+0x930) */
+#define SPM_ACK_CHK_STA_1_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_SWINT_1 (0x10006000+0x934) */
+#define SPM_ACK_CHK_SWINT_EN_1_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON_2 (0x10006000+0x940) */
+#define SPM_ACK_CHK_SW_EN_2_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_2_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_2_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_2_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN_2_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_2_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN_2_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_2_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN_2_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE_2_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL_2_LSB (1U << 15) /* 1b */
+/* SPM_ACK_CHK_PC_2 (0x10006000+0x944) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_2_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_2_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL_2 (0x10006000+0x948) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_2_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_2_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_2_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_2_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER_2 (0x10006000+0x94C) */
+#define SPM_ACK_CHK_TIMER_VAL_2_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER_2_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA_2 (0x10006000+0x950) */
+#define SPM_ACK_CHK_STA_2_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_SWINT_2 (0x10006000+0x954) */
+#define SPM_ACK_CHK_SWINT_EN_2_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_CON_3 (0x10006000+0x960) */
+#define SPM_ACK_CHK_SW_EN_3_LSB (1U << 0) /* 1b */
+#define SPM_ACK_CHK_CLR_ALL_3_LSB (1U << 1) /* 1b */
+#define SPM_ACK_CHK_CLR_TIMER_3_LSB (1U << 2) /* 1b */
+#define SPM_ACK_CHK_CLR_IRQ_3_LSB (1U << 3) /* 1b */
+#define SPM_ACK_CHK_STA_EN_3_LSB (1U << 4) /* 1b */
+#define SPM_ACK_CHK_WAKEUP_EN_3_LSB (1U << 5) /* 1b */
+#define SPM_ACK_CHK_WDT_EN_3_LSB (1U << 6) /* 1b */
+#define SPM_ACK_CHK_LOCK_PC_TRACE_EN_3_LSB (1U << 7) /* 1b */
+#define SPM_ACK_CHK_HW_EN_3_LSB (1U << 8) /* 1b */
+#define SPM_ACK_CHK_HW_MODE_3_LSB (1U << 9) /* 3b */
+#define SPM_ACK_CHK_FAIL_3_LSB (1U << 15) /* 1b */
+/* SPM_ACK_CHK_PC_3 (0x10006000+0x964) */
+#define SPM_ACK_CHK_HW_TRIG_PC_VAL_3_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_HW_TARG_PC_VAL_3_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_SEL_3 (0x10006000+0x968) */
+#define SPM_ACK_CHK_HW_TRIG_SIGNAL_SEL_3_LSB (1U << 0) /* 5b */
+#define SPM_ACK_CHK_HW_TRIG_GROUP_SEL_3_LSB (1U << 5) /* 3b */
+#define SPM_ACK_CHK_HW_TARG_SIGNAL_SEL_3_LSB (1U << 16) /* 5b */
+#define SPM_ACK_CHK_HW_TARG_GROUP_SEL_3_LSB (1U << 21) /* 3b */
+/* SPM_ACK_CHK_TIMER_3 (0x10006000+0x96C) */
+#define SPM_ACK_CHK_TIMER_VAL_3_LSB (1U << 0) /* 16b */
+#define SPM_ACK_CHK_TIMER_3_LSB (1U << 16) /* 16b */
+/* SPM_ACK_CHK_STA_3 (0x10006000+0x970) */
+#define SPM_ACK_CHK_STA_3_LSB (1U << 0) /* 32b */
+/* SPM_ACK_CHK_SWINT_3 (0x10006000+0x974) */
+#define SPM_ACK_CHK_SWINT_EN_3_LSB (1U << 0) /* 32b */
+/* SPM_COUNTER_0 (0x10006000+0x978) */
+#define SPM_COUNTER_VAL_0_LSB (1U << 0) /* 14b */
+#define SPM_COUNTER_OUT_0_LSB (1U << 14) /* 14b */
+#define SPM_COUNTER_EN_0_LSB (1U << 28) /* 1b */
+#define SPM_COUNTER_CLR_0_LSB (1U << 29) /* 1b */
+#define SPM_COUNTER_TIMEOUT_0_LSB (1U << 30) /* 1b */
+#define SPM_COUNTER_WAKEUP_EN_0_LSB (1U << 31) /* 1b */
+/* SPM_COUNTER_1 (0x10006000+0x97C) */
+#define SPM_COUNTER_VAL_1_LSB (1U << 0) /* 14b */
+#define SPM_COUNTER_OUT_1_LSB (1U << 14) /* 14b */
+#define SPM_COUNTER_EN_1_LSB (1U << 28) /* 1b */
+#define SPM_COUNTER_CLR_1_LSB (1U << 29) /* 1b */
+#define SPM_COUNTER_TIMEOUT_1_LSB (1U << 30) /* 1b */
+#define SPM_COUNTER_WAKEUP_EN_1_LSB (1U << 31) /* 1b */
+/* SPM_COUNTER_2 (0x10006000+0x980) */
+#define SPM_COUNTER_VAL_2_LSB (1U << 0) /* 14b */
+#define SPM_COUNTER_OUT_2_LSB (1U << 14) /* 14b */
+#define SPM_COUNTER_EN_2_LSB (1U << 28) /* 1b */
+#define SPM_COUNTER_CLR_2_LSB (1U << 29) /* 1b */
+#define SPM_COUNTER_TIMEOUT_2_LSB (1U << 30) /* 1b */
+#define SPM_COUNTER_WAKEUP_EN_2_LSB (1U << 31) /* 1b */
+/* SYS_TIMER_CON (0x10006000+0x98C) */
+#define SYS_TIMER_START_EN_LSB (1U << 0) /* 1b */
+#define SYS_TIMER_LATCH_EN_LSB (1U << 1) /* 1b */
+#define SYS_TIMER_ID_LSB (1U << 8) /* 8b */
+#define SYS_TIMER_VALID_LSB (1U << 31) /* 1b */
+/* RC_FSM_STA_0 (0x10006000+0xE00) */
+#define RC_FSM_STA_0_LSB (1U << 0) /* 32b */
+/* RC_CMD_STA_0 (0x10006000+0xE04) */
+#define RC_CMD_STA_0_LSB (1U << 0) /* 32b */
+/* RC_CMD_STA_1 (0x10006000+0xE08) */
+#define RC_CMD_STA_1_LSB (1U << 0) /* 32b */
+/* RC_SPI_STA_0 (0x10006000+0xE0C) */
+#define RC_SPI_STA_0_LSB (1U << 0) /* 32b */
+/* RC_PI_PO_STA_0 (0x10006000+0xE10) */
+#define RC_PI_PO_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M00_REQ_STA_0 (0x10006000+0xE14) */
+#define RC_M00_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M01_REQ_STA_0 (0x10006000+0xE1C) */
+#define RC_M01_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M02_REQ_STA_0 (0x10006000+0xE20) */
+#define RC_M02_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M03_REQ_STA_0 (0x10006000+0xE24) */
+#define RC_M03_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M04_REQ_STA_0 (0x10006000+0xE28) */
+#define RC_M04_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M05_REQ_STA_0 (0x10006000+0xE2C) */
+#define RC_M05_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M06_REQ_STA_0 (0x10006000+0xE30) */
+#define RC_M06_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M07_REQ_STA_0 (0x10006000+0xE34) */
+#define RC_M07_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M08_REQ_STA_0 (0x10006000+0xE38) */
+#define RC_M08_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M09_REQ_STA_0 (0x10006000+0xE3C) */
+#define RC_M09_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M10_REQ_STA_0 (0x10006000+0xE40) */
+#define RC_M10_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M11_REQ_STA_0 (0x10006000+0xE44) */
+#define RC_M11_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_M12_REQ_STA_0 (0x10006000+0xE48) */
+#define RC_M12_REQ_STA_0_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_STA_0 (0x10006000+0xE4C) */
+#define RC_DEBUG_STA_0_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_0_LSB (0x10006000+0xE50) */
+#define RO_PMRC_TRACE_00_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_0_MSB (0x10006000+0xE54) */
+#define RO_PMRC_TRACE_00_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_1_LSB (0x10006000+0xE5C) */
+#define RO_PMRC_TRACE_01_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_1_MSB (0x10006000+0xE60) */
+#define RO_PMRC_TRACE_01_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_2_LSB (0x10006000+0xE64) */
+#define RO_PMRC_TRACE_02_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_2_MSB (0x10006000+0xE6C) */
+#define RO_PMRC_TRACE_02_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_3_LSB (0x10006000+0xE70) */
+#define RO_PMRC_TRACE_03_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_3_MSB (0x10006000+0xE74) */
+#define RO_PMRC_TRACE_03_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_4_LSB (0x10006000+0xE78) */
+#define RO_PMRC_TRACE_04_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_4_MSB (0x10006000+0xE7C) */
+#define RO_PMRC_TRACE_04_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_5_LSB (0x10006000+0xE80) */
+#define RO_PMRC_TRACE_05_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_5_MSB (0x10006000+0xE84) */
+#define RO_PMRC_TRACE_05_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_6_LSB (0x10006000+0xE88) */
+#define RO_PMRC_TRACE_06_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_6_MSB (0x10006000+0xE8C) */
+#define RO_PMRC_TRACE_06_MSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_7_LSB (0x10006000+0xE90) */
+#define RO_PMRC_TRACE_07_LSB_LSB (1U << 0) /* 32b */
+/* RC_DEBUG_TRACE_7_MSB (0x10006000+0xE94) */
+#define RO_PMRC_TRACE_07_MSB_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_0_LSB (0x10006000+0xE98) */
+#define RC_SYS_TIMER_LATCH_L_00_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_0_MSB (0x10006000+0xE9C) */
+#define RC_SYS_TIMER_LATCH_H_00_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_1_LSB (0x10006000+0xEA0) */
+#define RC_SYS_TIMER_LATCH_L_01_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_1_MSB (0x10006000+0xEA4) */
+#define RC_SYS_TIMER_LATCH_H_01_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_2_LSB (0x10006000+0xEA8) */
+#define RC_SYS_TIMER_LATCH_L_02_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_2_MSB (0x10006000+0xEAC) */
+#define RC_SYS_TIMER_LATCH_H_02_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_3_LSB (0x10006000+0xEB0) */
+#define RC_SYS_TIMER_LATCH_L_03_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_3_MSB (0x10006000+0xEB4) */
+#define RC_SYS_TIMER_LATCH_H_03_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_4_LSB (0x10006000+0xEB8) */
+#define RC_SYS_TIMER_LATCH_L_04_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_4_MSB (0x10006000+0xEBC) */
+#define RC_SYS_TIMER_LATCH_H_04_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_5_LSB (0x10006000+0xEC0) */
+#define RC_SYS_TIMER_LATCH_L_05_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_5_MSB (0x10006000+0xEC4) */
+#define RC_SYS_TIMER_LATCH_H_05_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_6_LSB (0x10006000+0xEC8) */
+#define RC_SYS_TIMER_LATCH_L_06_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_6_MSB (0x10006000+0xECC) */
+#define RC_SYS_TIMER_LATCH_H_06_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_7_LSB (0x10006000+0xED0) */
+#define RC_SYS_TIMER_LATCH_L_07_LSB (1U << 0) /* 32b */
+/* RC_SYS_TIMER_LATCH_7_MSB (0x10006000+0xED4) */
+#define RC_SYS_TIMER_LATCH_H_07_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_19 (0x10006000+0xED8) */
+#define PCM_WDT_LATCH_19_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_20 (0x10006000+0xEDC) */
+#define PCM_WDT_LATCH_20_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_21 (0x10006000+0xEE0) */
+#define PCM_WDT_LATCH_21_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_22 (0x10006000+0xEE4) */
+#define PCM_WDT_LATCH_22_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_23 (0x10006000+0xEE8) */
+#define PCM_WDT_LATCH_23_LSB (1U << 0) /* 32b */
+/* PCM_WDT_LATCH_24 (0x10006000+0xEEC) */
+#define PCM_WDT_LATCH_24_LSB (1U << 0) /* 32b */
+/* PMSR_LAST_DAT (0x10006000+0xF00) */
+#define PMSR_LAST_DAT_LSB (1U << 0) /* 32b */
+/* PMSR_LAST_CNT (0x10006000+0xF04) */
+#define PMSR_LAST_CMD_LSB (1U << 0) /* 30b */
+#define PMSR_LAST_REQ_LSB (1U << 30) /* 1b */
+/* PMSR_LAST_ACK (0x10006000+0xF08) */
+#define PMSR_LAST_ACK_LSB (1U << 0) /* 1b */
+/* SPM_PMSR_SEL_CON0 (0x10006000+0xF10) */
+#define REG_PMSR_SIG_SEL_0_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_1_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_2_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_3_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON1 (0x10006000+0xF14) */
+#define REG_PMSR_SIG_SEL_4_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_5_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_6_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_7_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON2 (0x10006000+0xF18) */
+#define REG_PMSR_SIG_SEL_8_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_9_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_10_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_11_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON3 (0x10006000+0xF1C) */
+#define REG_PMSR_SIG_SEL_12_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_13_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_14_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_15_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON4 (0x10006000+0xF20) */
+#define REG_PMSR_SIG_SEL_16_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_17_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_18_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_19_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON5 (0x10006000+0xF24) */
+#define REG_PMSR_SIG_SEL_20_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_21_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_22_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_23_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON6 (0x10006000+0xF28) */
+#define REG_PMSR_SIG_SEL_24_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_25_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_26_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_27_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON7 (0x10006000+0xF2C) */
+#define REG_PMSR_SIG_SEL_28_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_29_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_30_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_31_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON8 (0x10006000+0xF30) */
+#define REG_PMSR_SIG_SEL_32_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_33_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_34_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_35_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON9 (0x10006000+0xF34) */
+#define REG_PMSR_SIG_SEL_36_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_37_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_38_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_39_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON10 (0x10006000+0xF3C) */
+#define REG_PMSR_SIG_SEL_40_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_41_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_42_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_43_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_SEL_CON11 (0x10006000+0xF40) */
+#define REG_PMSR_SIG_SEL_44_LSB (1U << 0) /* 8b */
+#define REG_PMSR_SIG_SEL_45_LSB (1U << 8) /* 8b */
+#define REG_PMSR_SIG_SEL_46_LSB (1U << 16) /* 8b */
+#define REG_PMSR_SIG_SEL_47_LSB (1U << 24) /* 8b */
+/* SPM_PMSR_TIEMR_STA0 (0x10006000+0xFB8) */
+#define PMSR_TIMER_SET0_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_TIEMR_STA1 (0x10006000+0xFBC) */
+#define PMSR_TIMER_SET1_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_TIEMR_STA2 (0x10006000+0xFC0) */
+#define PMSR_TIMER_SET2_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_GENERAL_CON0 (0x10006000+0xFC4) */
+#define PMSR_ENABLE_SET0_LSB (1U << 0) /* 1b */
+#define PMSR_ENABLE_SET1_LSB (1U << 1) /* 1b */
+#define PMSR_ENABLE_SET2_LSB (1U << 2) /* 1b */
+#define PMSR_IRQ_CLR_SET0_LSB (1U << 3) /* 1b */
+#define PMSR_IRQ_CLR_SET1_LSB (1U << 4) /* 1b */
+#define PMSR_IRQ_CLR_SET2_LSB (1U << 5) /* 1b */
+#define PMSR_SPEED_MODE_EN_SET0_LSB (1U << 6) /* 1b */
+#define PMSR_SPEED_MODE_EN_SET1_LSB (1U << 7) /* 1b */
+#define PMSR_SPEED_MODE_EN_SET2_LSB (1U << 8) /* 1b */
+#define PMSR_EVENT_CLR_SET0_LSB (1U << 9) /* 1b */
+#define PMSR_EVENT_CLR_SET1_LSB (1U << 10) /* 1b */
+#define PMSR_EVENT_CLR_SET2_LSB (1U << 11) /* 1b */
+#define REG_PMSR_IRQ_MASK_SET0_LSB (1U << 12) /* 1b */
+#define REG_PMSR_IRQ_MASK_SET1_LSB (1U << 13) /* 1b */
+#define REG_PMSR_IRQ_MASK_SET2_LSB (1U << 14) /* 1b */
+#define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET0_LSB (1U << 15) /* 1b */
+#define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET1_LSB (1U << 16) /* 1b */
+#define REG_PMSR_IRQ_WAKEUP_EVENT_MASK_SET2_LSB (1U << 17) /* 1b */
+#define PMSR_GEN_SW_RST_EN_LSB (1U << 18) /* 1b */
+#define PMSR_MODULE_ENABLE_LSB (1U << 19) /* 1b */
+#define PMSR_MODE_LSB (1U << 20) /* 2b */
+#define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET0_LSB (1U << 29) /* 1b */
+#define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET1_LSB (1U << 30) /* 1b */
+#define SPM_PMSR_GENERAL_CON0_PMSR_IRQ_B_SET2_LSB (1U << 31) /* 1b */
+/* SPM_PMSR_GENERAL_CON1 (0x10006000+0xFC8) */
+#define PMSR_COUNTER_THRES_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_GENERAL_CON2 (0x10006000+0xFCC) */
+#define PMSR_DEBUG_IN_0_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_GENERAL_CON3 (0x10006000+0xFD0) */
+#define PMSR_DEBUG_IN_1_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_GENERAL_CON4 (0x10006000+0xFD4) */
+#define PMSR_DEBUG_IN_2_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_GENERAL_CON5 (0x10006000+0xFD8) */
+#define PMSR_DEBUG_IN_3_MASK_B_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_SW_RESET (0x10006000+0xFDC) */
+#define PMSR_SW_RST_EN_SET0_LSB (1U << 0) /* 1b */
+#define PMSR_SW_RST_EN_SET1_LSB (1U << 1) /* 1b */
+#define PMSR_SW_RST_EN_SET2_LSB (1U << 2) /* 1b */
+/* SPM_PMSR_MON_CON0 (0x10006000+0xFE0) */
+#define REG_PMSR_MON_TYPE_0_LSB (1U << 0) /* 2b */
+#define REG_PMSR_MON_TYPE_1_LSB (1U << 2) /* 2b */
+#define REG_PMSR_MON_TYPE_2_LSB (1U << 4) /* 2b */
+#define REG_PMSR_MON_TYPE_3_LSB (1U << 6) /* 2b */
+#define REG_PMSR_MON_TYPE_4_LSB (1U << 8) /* 2b */
+#define REG_PMSR_MON_TYPE_5_LSB (1U << 10) /* 2b */
+#define REG_PMSR_MON_TYPE_6_LSB (1U << 12) /* 2b */
+#define REG_PMSR_MON_TYPE_7_LSB (1U << 14) /* 2b */
+#define REG_PMSR_MON_TYPE_8_LSB (1U << 16) /* 2b */
+#define REG_PMSR_MON_TYPE_9_LSB (1U << 18) /* 2b */
+#define REG_PMSR_MON_TYPE_10_LSB (1U << 20) /* 2b */
+#define REG_PMSR_MON_TYPE_11_LSB (1U << 22) /* 2b */
+#define REG_PMSR_MON_TYPE_12_LSB (1U << 24) /* 2b */
+#define REG_PMSR_MON_TYPE_13_LSB (1U << 26) /* 2b */
+#define REG_PMSR_MON_TYPE_14_LSB (1U << 28) /* 2b */
+#define REG_PMSR_MON_TYPE_15_LSB (1U << 30) /* 2b */
+/* SPM_PMSR_MON_CON1 (0x10006000+0xFE4) */
+#define REG_PMSR_MON_TYPE_16_LSB (1U << 0) /* 2b */
+#define REG_PMSR_MON_TYPE_17_LSB (1U << 2) /* 2b */
+#define REG_PMSR_MON_TYPE_18_LSB (1U << 4) /* 2b */
+#define REG_PMSR_MON_TYPE_19_LSB (1U << 6) /* 2b */
+#define REG_PMSR_MON_TYPE_20_LSB (1U << 8) /* 2b */
+#define REG_PMSR_MON_TYPE_21_LSB (1U << 10) /* 2b */
+#define REG_PMSR_MON_TYPE_22_LSB (1U << 12) /* 2b */
+#define REG_PMSR_MON_TYPE_23_LSB (1U << 14) /* 2b */
+#define REG_PMSR_MON_TYPE_24_LSB (1U << 16) /* 2b */
+#define REG_PMSR_MON_TYPE_25_LSB (1U << 18) /* 2b */
+#define REG_PMSR_MON_TYPE_26_LSB (1U << 20) /* 2b */
+#define REG_PMSR_MON_TYPE_27_LSB (1U << 22) /* 2b */
+#define REG_PMSR_MON_TYPE_28_LSB (1U << 24) /* 2b */
+#define REG_PMSR_MON_TYPE_29_LSB (1U << 26) /* 2b */
+#define REG_PMSR_MON_TYPE_30_LSB (1U << 28) /* 2b */
+#define REG_PMSR_MON_TYPE_31_LSB (1U << 30) /* 2b */
+/* SPM_PMSR_MON_CON2 (0x10006000+0xFE8) */
+#define REG_PMSR_MON_TYPE_32_LSB (1U << 0) /* 2b */
+#define REG_PMSR_MON_TYPE_33_LSB (1U << 2) /* 2b */
+#define REG_PMSR_MON_TYPE_34_LSB (1U << 4) /* 2b */
+#define REG_PMSR_MON_TYPE_35_LSB (1U << 6) /* 2b */
+#define REG_PMSR_MON_TYPE_36_LSB (1U << 8) /* 2b */
+#define REG_PMSR_MON_TYPE_37_LSB (1U << 10) /* 2b */
+#define REG_PMSR_MON_TYPE_38_LSB (1U << 12) /* 2b */
+#define REG_PMSR_MON_TYPE_39_LSB (1U << 14) /* 2b */
+#define REG_PMSR_MON_TYPE_40_LSB (1U << 16) /* 2b */
+#define REG_PMSR_MON_TYPE_41_LSB (1U << 18) /* 2b */
+#define REG_PMSR_MON_TYPE_42_LSB (1U << 20) /* 2b */
+#define REG_PMSR_MON_TYPE_43_LSB (1U << 22) /* 2b */
+#define REG_PMSR_MON_TYPE_44_LSB (1U << 24) /* 2b */
+#define REG_PMSR_MON_TYPE_45_LSB (1U << 26) /* 2b */
+#define REG_PMSR_MON_TYPE_46_LSB (1U << 28) /* 2b */
+#define REG_PMSR_MON_TYPE_47_LSB (1U << 30) /* 2b */
+/* SPM_PMSR_LEN_CON0 (0x10006000+0xFEC) */
+#define REG_PMSR_WINDOW_LEN_SET0_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_LEN_CON1 (0x10006000+0xFF0) */
+#define REG_PMSR_WINDOW_LEN_SET1_LSB (1U << 0) /* 32b */
+/* SPM_PMSR_LEN_CON2 (0x10006000+0xFF4) */
+#define REG_PMSR_WINDOW_LEN_SET2_LSB (1U << 0) /* 32b */
+
+#define SPM_PROJECT_CODE 0xb16
+#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16)
+#endif
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_resource_req.h b/plat/mediatek/mt8195/drivers/spm/mt_spm_resource_req.h
new file mode 100644
index 0000000..26250ba
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_resource_req.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_RESOURCE_REQ_H
+#define MT_SPM_RESOURCE_REQ_H
+
+/* SPM resource request internal bit */
+#define MT_SPM_BIT_XO_FPM 0
+#define MT_SPM_BIT_26M 1
+#define MT_SPM_BIT_INFRA 2
+#define MT_SPM_BIT_SYSPLL 3
+#define MT_SPM_BIT_DRAM_S0 4
+#define MT_SPM_BIT_DRAM_S1 5
+
+/* SPM resource request internal bit_mask */
+#define MT_SPM_XO_FPM BIT(MT_SPM_BIT_XO_FPM)
+#define MT_SPM_26M BIT(MT_SPM_BIT_26M)
+#define MT_SPM_INFRA BIT(MT_SPM_BIT_INFRA)
+#define MT_SPM_SYSPLL BIT(MT_SPM_BIT_SYSPLL)
+#define MT_SPM_DRAM_S0 BIT(MT_SPM_BIT_DRAM_S0)
+#define MT_SPM_DRAM_S1 BIT(MT_SPM_BIT_DRAM_S1)
+#endif /* MT_SPM_RESOURCE_REQ_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_suspend.c b/plat/mediatek/mt8195/drivers/spm/mt_spm_suspend.c
new file mode 100644
index 0000000..b40fa87
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_suspend.c
@@ -0,0 +1,395 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <mt_spm.h>
+#include <mt_spm_conservation.h>
+#include <mt_spm_internal.h>
+#include <mt_spm_rc_internal.h>
+#include <mt_spm_reg.h>
+#include <mt_spm_resource_req.h>
+#include <mt_spm_suspend.h>
+#include <plat_pm.h>
+#include <uart.h>
+
+#define SPM_SUSPEND_SLEEP_PCM_FLAG \
+ (SPM_FLAG_DISABLE_INFRA_PDN | \
+ SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_KEEP_CSYSPWRACK_HIGH | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
+ SPM_FLAG_SRAM_SLEEP_CTRL)
+
+#define SPM_SUSPEND_SLEEP_PCM_FLAG1 0
+
+#define SPM_SUSPEND_PCM_FLAG \
+ (SPM_FLAG_DISABLE_VCORE_DVS | \
+ SPM_FLAG_DISABLE_VCORE_DFS | \
+ SPM_FLAG_ENABLE_TIA_WORKAROUND | \
+ SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP | \
+ SPM_FLAG_SRAM_SLEEP_CTRL)
+
+#define SPM_SUSPEND_PCM_FLAG1 0
+
+/* Suspend spm power control */
+#define __WAKE_SRC_FOR_SUSPEND_COMMON__ \
+ (R12_PCM_TIMER | \
+ R12_KP_IRQ_B | \
+ R12_APWDT_EVENT_B | \
+ R12_CONN2AP_SPM_WAKEUP_B | \
+ R12_EINT_EVENT_B | \
+ R12_CONN_WDT_IRQ_B | \
+ R12_CCIF0_EVENT_B | \
+ R12_SSPM2SPM_WAKEUP_B | \
+ R12_SCP2SPM_WAKEUP_B | \
+ R12_ADSP2SPM_WAKEUP_B | \
+ R12_USBX_CDSC_B | \
+ R12_USBX_POWERDWN_B | \
+ R12_SYS_TIMER_EVENT_B | \
+ R12_EINT_EVENT_SECURE_B | \
+ R12_SYS_CIRQ_IRQ_B | \
+ R12_MD2AP_PEER_EVENT_B | \
+ R12_MD1_WDT_B | \
+ R12_CLDMA_EVENT_B | \
+ R12_REG_CPU_WAKEUP | \
+ R12_APUSYS_WAKE_HOST_B)
+
+#if defined(CFG_MICROTRUST_TEE_SUPPORT)
+#define WAKE_SRC_FOR_SUSPEND (__WAKE_SRC_FOR_SUSPEND_COMMON__)
+#else
+#define WAKE_SRC_FOR_SUSPEND \
+ (__WAKE_SRC_FOR_SUSPEND_COMMON__ | \
+ R12_SEJ_EVENT_B)
+#endif
+
+static struct pwr_ctrl suspend_ctrl = {
+ .wake_src = WAKE_SRC_FOR_SUSPEND,
+
+ /* SPM_AP_STANDBY_CON */
+ /* [0] */
+ .reg_wfi_op = 0,
+ /* [1] */
+ .reg_wfi_type = 0,
+ /* [2] */
+ .reg_mp0_cputop_idle_mask = 0,
+ /* [3] */
+ .reg_mp1_cputop_idle_mask = 0,
+ /* [4] */
+ .reg_mcusys_idle_mask = 0,
+ /* [25] */
+ .reg_md_apsrc_1_sel = 0,
+ /* [26] */
+ .reg_md_apsrc_0_sel = 0,
+ /* [29] */
+ .reg_conn_apsrc_sel = 0,
+
+ /* SPM_SRC_REQ */
+ /* [0] */
+ .reg_spm_apsrc_req = 0,
+ /* [1] */
+ .reg_spm_f26m_req = 0,
+ /* [3] */
+ .reg_spm_infra_req = 0,
+ /* [4] */
+ .reg_spm_vrf18_req = 0,
+ /* [7] FIXME: default disable HW Auto S1*/
+ .reg_spm_ddr_en_req = 1,
+ /* [8] */
+ .reg_spm_dvfs_req = 0,
+ /* [9] */
+ .reg_spm_sw_mailbox_req = 0,
+ /* [10] */
+ .reg_spm_sspm_mailbox_req = 0,
+ /* [11] */
+ .reg_spm_adsp_mailbox_req = 0,
+ /* [12] */
+ .reg_spm_scp_mailbox_req = 0,
+
+ /* SPM_SRC_MASK */
+ /* [0] */
+ .reg_sspm_srcclkena_0_mask_b = 1,
+ /* [1] */
+ .reg_sspm_infra_req_0_mask_b = 1,
+ /* [2] */
+ .reg_sspm_apsrc_req_0_mask_b = 1,
+ /* [3] */
+ .reg_sspm_vrf18_req_0_mask_b = 1,
+ /* [4] */
+ .reg_sspm_ddr_en_0_mask_b = 1,
+ /* [5] */
+ .reg_scp_srcclkena_mask_b = 1,
+ /* [6] */
+ .reg_scp_infra_req_mask_b = 1,
+ /* [7] */
+ .reg_scp_apsrc_req_mask_b = 1,
+ /* [8] */
+ .reg_scp_vrf18_req_mask_b = 1,
+ /* [9] */
+ .reg_scp_ddr_en_mask_b = 1,
+ /* [10] */
+ .reg_audio_dsp_srcclkena_mask_b = 1,
+ /* [11] */
+ .reg_audio_dsp_infra_req_mask_b = 1,
+ /* [12] */
+ .reg_audio_dsp_apsrc_req_mask_b = 1,
+ /* [13] */
+ .reg_audio_dsp_vrf18_req_mask_b = 1,
+ /* [14] */
+ .reg_audio_dsp_ddr_en_mask_b = 1,
+ /* [15] */
+ .reg_apu_srcclkena_mask_b = 1,
+ /* [16] */
+ .reg_apu_infra_req_mask_b = 1,
+ /* [17] */
+ .reg_apu_apsrc_req_mask_b = 1,
+ /* [18] */
+ .reg_apu_vrf18_req_mask_b = 1,
+ /* [19] */
+ .reg_apu_ddr_en_mask_b = 1,
+ /* [20] */
+ .reg_cpueb_srcclkena_mask_b = 1,
+ /* [21] */
+ .reg_cpueb_infra_req_mask_b = 1,
+ /* [22] */
+ .reg_cpueb_apsrc_req_mask_b = 1,
+ /* [23] */
+ .reg_cpueb_vrf18_req_mask_b = 1,
+ /* [24] */
+ .reg_cpueb_ddr_en_mask_b = 1,
+ /* [25] */
+ .reg_bak_psri_srcclkena_mask_b = 0,
+ /* [26] */
+ .reg_bak_psri_infra_req_mask_b = 0,
+ /* [27] */
+ .reg_bak_psri_apsrc_req_mask_b = 0,
+ /* [28] */
+ .reg_bak_psri_vrf18_req_mask_b = 0,
+ /* [29] */
+ .reg_bak_psri_ddr_en_mask_b = 0,
+
+ /* SPM_SRC2_MASK */
+ /* [0] */
+ .reg_msdc0_srcclkena_mask_b = 1,
+ /* [1] */
+ .reg_msdc0_infra_req_mask_b = 1,
+ /* [2] */
+ .reg_msdc0_apsrc_req_mask_b = 1,
+ /* [3] */
+ .reg_msdc0_vrf18_req_mask_b = 1,
+ /* [4] */
+ .reg_msdc0_ddr_en_mask_b = 1,
+ /* [5] */
+ .reg_msdc1_srcclkena_mask_b = 1,
+ /* [6] */
+ .reg_msdc1_infra_req_mask_b = 1,
+ /* [7] */
+ .reg_msdc1_apsrc_req_mask_b = 1,
+ /* [8] */
+ .reg_msdc1_vrf18_req_mask_b = 1,
+ /* [9] */
+ .reg_msdc1_ddr_en_mask_b = 1,
+ /* [10] */
+ .reg_msdc2_srcclkena_mask_b = 1,
+ /* [11] */
+ .reg_msdc2_infra_req_mask_b = 1,
+ /* [12] */
+ .reg_msdc2_apsrc_req_mask_b = 1,
+ /* [13] */
+ .reg_msdc2_vrf18_req_mask_b = 1,
+ /* [14] */
+ .reg_msdc2_ddr_en_mask_b = 1,
+ /* [15] */
+ .reg_ufs_srcclkena_mask_b = 0,
+ /* [16] */
+ .reg_ufs_infra_req_mask_b = 0,
+ /* [17] */
+ .reg_ufs_apsrc_req_mask_b = 0,
+ /* [18] */
+ .reg_ufs_vrf18_req_mask_b = 0,
+ /* [19] */
+ .reg_ufs_ddr_en_mask_b = 0,
+ /* [20] */
+ .reg_usb_srcclkena_mask_b = 1,
+ /* [21] */
+ .reg_usb_infra_req_mask_b = 1,
+ /* [22] */
+ .reg_usb_apsrc_req_mask_b = 1,
+ /* [23] */
+ .reg_usb_vrf18_req_mask_b = 1,
+ /* [24] */
+ .reg_usb_ddr_en_mask_b = 1,
+ /* [25] */
+ .reg_pextp_p0_srcclkena_mask_b = 1,
+ /* [26] */
+ .reg_pextp_p0_infra_req_mask_b = 1,
+ /* [27] */
+ .reg_pextp_p0_apsrc_req_mask_b = 1,
+ /* [28] */
+ .reg_pextp_p0_vrf18_req_mask_b = 1,
+ /* [29] */
+ .reg_pextp_p0_ddr_en_mask_b = 1,
+
+ /* SPM_SRC3_MASK */
+ /* [0] */
+ .reg_pextp_p1_srcclkena_mask_b = 1,
+ /* [1] */
+ .reg_pextp_p1_infra_req_mask_b = 1,
+ /* [2] */
+ .reg_pextp_p1_apsrc_req_mask_b = 1,
+ /* [3] */
+ .reg_pextp_p1_vrf18_req_mask_b = 1,
+ /* [4] */
+ .reg_pextp_p1_ddr_en_mask_b = 1,
+ /* [5] */
+ .reg_gce0_infra_req_mask_b = 1,
+ /* [6] */
+ .reg_gce0_apsrc_req_mask_b = 1,
+ /* [7] */
+ .reg_gce0_vrf18_req_mask_b = 1,
+ /* [8] */
+ .reg_gce0_ddr_en_mask_b = 1,
+ /* [9] */
+ .reg_gce1_infra_req_mask_b = 1,
+ /* [10] */
+ .reg_gce1_apsrc_req_mask_b = 1,
+ /* [11] */
+ .reg_gce1_vrf18_req_mask_b = 1,
+ /* [12] */
+ .reg_gce1_ddr_en_mask_b = 1,
+ /* [13] */
+ .reg_spm_srcclkena_reserved_mask_b = 1,
+ /* [14] */
+ .reg_spm_infra_req_reserved_mask_b = 1,
+ /* [15] */
+ .reg_spm_apsrc_req_reserved_mask_b = 1,
+ /* [16] */
+ .reg_spm_vrf18_req_reserved_mask_b = 1,
+ /* [17] */
+ .reg_spm_ddr_en_reserved_mask_b = 1,
+ /* [18] */
+ .reg_disp0_apsrc_req_mask_b = 1,
+ /* [19] */
+ .reg_disp0_ddr_en_mask_b = 1,
+ /* [20] */
+ .reg_disp1_apsrc_req_mask_b = 1,
+ /* [21] */
+ .reg_disp1_ddr_en_mask_b = 1,
+ /* [22] */
+ .reg_disp2_apsrc_req_mask_b = 1,
+ /* [23] */
+ .reg_disp2_ddr_en_mask_b = 1,
+ /* [24] */
+ .reg_disp3_apsrc_req_mask_b = 1,
+ /* [25] */
+ .reg_disp3_ddr_en_mask_b = 1,
+ /* [26] */
+ .reg_infrasys_apsrc_req_mask_b = 0,
+ /* [27] */
+ .reg_infrasys_ddr_en_mask_b = 1,
+
+ /* [28] */
+ .reg_cg_check_srcclkena_mask_b = 1,
+ /* [29] */
+ .reg_cg_check_apsrc_req_mask_b = 1,
+ /* [30] */
+ .reg_cg_check_vrf18_req_mask_b = 1,
+ /* [31] */
+ .reg_cg_check_ddr_en_mask_b = 1,
+
+ /* SPM_SRC4_MASK */
+ /* [8:0] */
+ .reg_mcusys_merge_apsrc_req_mask_b = 0x17,
+ /* [17:9] */
+ .reg_mcusys_merge_ddr_en_mask_b = 0x17,
+ /* [19:18] */
+ .reg_dramc_md32_infra_req_mask_b = 0,
+ /* [21:20] */
+ .reg_dramc_md32_vrf18_req_mask_b = 0,
+ /* [23:22] */
+ .reg_dramc_md32_ddr_en_mask_b = 0,
+ /* [24] */
+ .reg_dvfsrc_event_trigger_mask_b = 1,
+
+ /* SPM_WAKEUP_EVENT_MASK2 */
+ /* [3:0] */
+ .reg_sc_sw2spm_wakeup_mask_b = 0,
+ /* [4] */
+ .reg_sc_adsp2spm_wakeup_mask_b = 0,
+ /* [8:5] */
+ .reg_sc_sspm2spm_wakeup_mask_b = 0,
+ /* [9] */
+ .reg_sc_scp2spm_wakeup_mask_b = 0,
+ /* [10] */
+ .reg_csyspwrup_ack_mask = 0,
+ /* [11] */
+ .reg_csyspwrup_req_mask = 1,
+
+ /* SPM_WAKEUP_EVENT_MASK */
+ /* [31:0] */
+ .reg_wakeup_event_mask = 0xC1382213,
+
+ /* SPM_WAKEUP_EVENT_EXT_MASK */
+ /* [31:0] */
+ .reg_ext_wakeup_event_mask = 0xFFFFFFFF,
+};
+
+struct spm_lp_scen __spm_suspend = {
+ .pwrctrl = &suspend_ctrl,
+};
+
+int mt_spm_suspend_mode_set(int mode)
+{
+ if (mode == MT_SPM_SUSPEND_SLEEP) {
+ suspend_ctrl.pcm_flags = SPM_SUSPEND_SLEEP_PCM_FLAG;
+ suspend_ctrl.pcm_flags1 = SPM_SUSPEND_SLEEP_PCM_FLAG1;
+ } else {
+ suspend_ctrl.pcm_flags = SPM_SUSPEND_PCM_FLAG;
+ suspend_ctrl.pcm_flags1 = SPM_SUSPEND_PCM_FLAG1;
+ }
+
+ return 0;
+}
+
+int mt_spm_suspend_enter(int state_id, unsigned int ext_opand,
+ unsigned int resource_req)
+{
+ /* If FMAudio / ADSP is active, change to sleep suspend mode */
+ if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
+ mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SLEEP);
+ }
+
+ /* Notify MCUPM that device is going suspend flow */
+ mmio_write_32(MCUPM_MBOX_OFFSET_PDN, MCUPM_POWER_DOWN);
+
+ /* Notify UART to sleep */
+ mt_uart_save();
+
+ return spm_conservation(state_id, ext_opand,
+ &__spm_suspend, resource_req);
+}
+
+void mt_spm_suspend_resume(int state_id, unsigned int ext_opand,
+ struct wake_status **status)
+{
+ spm_conservation_finish(state_id, ext_opand, &__spm_suspend, status);
+
+ /* Notify UART to wakeup */
+ mt_uart_restore();
+
+ /* Notify MCUPM that device leave suspend */
+ mmio_write_32(MCUPM_MBOX_OFFSET_PDN, 0);
+
+ /* If FMAudio / ADSP is active, change back to suspend mode */
+ if ((ext_opand & MT_SPM_EX_OP_SET_SUSPEND_MODE) != 0U) {
+ mt_spm_suspend_mode_set(MT_SPM_SUSPEND_SYSTEM_PDN);
+ }
+}
+
+void mt_spm_suspend_init(void)
+{
+ spm_conservation_pwrctrl_init(__spm_suspend.pwrctrl);
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/mt_spm_suspend.h b/plat/mediatek/mt8195/drivers/spm/mt_spm_suspend.h
new file mode 100644
index 0000000..69c5230
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/mt_spm_suspend.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_SUSPEND_H
+#define MT_SPM_SUSPEND_H
+
+#include <mt_spm_internal.h>
+
+#define MCUPM_MBOX_OFFSET_PDN 0x1031FF88
+#define MCUPM_POWER_DOWN 0x4D50444E
+
+enum MT_SPM_SUSPEND_MODE {
+ MT_SPM_SUSPEND_SYSTEM_PDN,
+ MT_SPM_SUSPEND_SLEEP,
+};
+
+extern int mt_spm_suspend_mode_set(int mode);
+extern int mt_spm_suspend_enter(int state_id, unsigned int ext_opand,
+ unsigned int reosuce_req);
+extern void mt_spm_suspend_resume(int state_id, unsigned int ext_opand,
+ struct wake_status **status);
+extern void mt_spm_suspend_init(void);
+#endif /* MT_SPM_SUSPEND_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_notifier.h b/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_notifier.h
new file mode 100644
index 0000000..ee3738d
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_notifier.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_SSPM_NOTIFIER_H
+#define MT_SPM_SSPM_NOTIFIER_H
+
+enum MT_SPM_SSPM_NOTIFY_ID {
+ MT_SPM_NOTIFY_LP_ENTER,
+ MT_SPM_NOTIFY_LP_LEAVE,
+};
+
+int mt_spm_sspm_notify(int type, unsigned int lp_mode);
+
+static inline int mt_spm_sspm_notify_u32(int type, unsigned int lp_mode)
+{
+ return mt_spm_sspm_notify(type, lp_mode);
+}
+#endif /* MT_SPM_SSPM_NOTIFIER_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_sspm_intc.h b/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_sspm_intc.h
new file mode 100644
index 0000000..6847e77
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_sspm_intc.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_SPM_SSPM_INTC_H
+#define MT_SPM_SSPM_INTC_H
+
+#include <mt_spm_reg.h>
+
+#define MT_SPM_SSPM_INTC_SEL_0 0x10
+#define MT_SPM_SSPM_INTC_SEL_1 0x20
+#define MT_SPM_SSPM_INTC_SEL_2 0x40
+#define MT_SPM_SSPM_INTC_SEL_3 0x80
+
+#define MT_SPM_SSPM_INTC_TRIGGER(id, sg) \
+ (((0x10 << id) | (sg << id)) & 0xff)
+
+#define MT_SPM_SSPM_INTC0_HIGH MT_SPM_SSPM_INTC_TRIGGER(0, 1)
+#define MT_SPM_SSPM_INTC0_LOW MT_SPM_SSPM_INTC_TRIGGER(0, 0)
+#define MT_SPM_SSPM_INTC1_HIGH MT_SPM_SSPM_INTC_TRIGGER(1, 1)
+#define MT_SPM_SSPM_INTC1_LOW MT_SPM_SSPM_INTC_TRIGGER(1, 0)
+#define MT_SPM_SSPM_INTC2_HIGH MT_SPM_SSPM_INTC_TRIGGER(2, 1)
+#define MT_SPM_SSPM_INTC2_LOW MT_SPM_SSPM_INTC_TRIGGER(2, 0)
+#define MT_SPM_SSPM_INTC3_HIGH MT_SPM_SSPM_INTC_TRIGGER(3, 1)
+#define MT_SPM_SSPM_INTC3_LOW MT_SPM_SSPM_INTC_TRIGGER(3, 0)
+
+#define DO_SPM_SSPM_LP_SUSPEND() \
+ mmio_write_32(SPM_MD32_IRQ, MT_SPM_SSPM_INTC0_HIGH)
+#define DO_SPM_SSPM_LP_RESUME() \
+ mmio_write_32(SPM_MD32_IRQ, MT_SPM_SSPM_INTC0_LOW)
+#endif /* MT_SPM_SSPM_INTC_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_sspm_notifier.c b/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_sspm_notifier.c
new file mode 100644
index 0000000..a755a38
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/notifier/mt_spm_sspm_notifier.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+
+#include <lib/mmio.h>
+
+#include <mt_spm_notifier.h>
+#include <mt_spm_sspm_intc.h>
+
+#define MT_SPM_SSPM_MBOX_OFF(x) (SSPM_MBOX_BASE + x)
+#define MT_SPM_MBOX(slot) MT_SPM_SSPM_MBOX_OFF((slot << 2UL))
+
+#define SSPM_MBOX_SPM_LP_LOOKUP1 MT_SPM_MBOX(0)
+#define SSPM_MBOX_SPM_LP_LOOKUP2 MT_SPM_MBOX(1)
+#define SSPM_MBOX_SPM_LP1 MT_SPM_MBOX(2)
+#define SSPM_MBOX_SPM_LP2 MT_SPM_MBOX(3)
+
+int mt_spm_sspm_notify(int type, unsigned int lp_mode)
+{
+ switch (type) {
+ case MT_SPM_NOTIFY_LP_ENTER:
+ mmio_write_32(SSPM_MBOX_SPM_LP1, lp_mode);
+ DO_SPM_SSPM_LP_SUSPEND();
+ break;
+ case MT_SPM_NOTIFY_LP_LEAVE:
+ mmio_write_32(SSPM_MBOX_SPM_LP1, lp_mode);
+ DO_SPM_SSPM_LP_RESUME();
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
diff --git a/plat/mediatek/mt8195/drivers/spm/pcm_def.h b/plat/mediatek/mt8195/drivers/spm/pcm_def.h
new file mode 100644
index 0000000..fa77b95
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/pcm_def.h
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PCM_DEF_H
+#define PCM_DEF_H
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+
+/* --- R0 Define --- */
+#define R0_SC_26M_CK_OFF (1U << 0)
+#define R0_SC_TX_TRACK_RETRY_EN (1U << 1)
+#define R0_SC_MEM_CK_OFF (1U << 2)
+#define R0_SC_AXI_CK_OFF (1U << 3)
+#define R0_SC_DR_SRAM_LOAD (1U << 4)
+#define R0_SC_MD26M_CK_OFF (1U << 5)
+#define R0_SC_DPY_MODE_SW (1U << 6)
+#define R0_SC_DMSUS_OFF (1U << 7)
+#define R0_SC_DPY_2ND_DLL_EN (1U << 8)
+#define R0_SC_DR_SRAM_RESTORE (1U << 9)
+#define R0_SC_MPLLOUT_OFF (1U << 10)
+#define R0_SC_TX_TRACKING_DIS (1U << 11)
+#define R0_SC_DPY_DLL_EN (1U << 12)
+#define R0_SC_DPY_DLL_CK_EN (1U << 13)
+#define R0_SC_DPY_VREF_EN (1U << 14)
+#define R0_SC_PHYPLL_EN (1U << 15)
+#define R0_SC_DDRPHY_FB_CK_EN (1U << 16)
+#define R0_SC_DPY_BCLK_ENABLE (1U << 17)
+#define R0_SC_MPLL_OFF (1U << 18)
+#define R0_SC_SHU_RESTORE (1U << 19)
+#define R0_SC_CKSQ0_OFF (1U << 20)
+#define R0_SC_DR_SHU_LEVEL_SRAM_LATCH (1U << 21)
+#define R0_SC_DR_SHU_EN (1U << 22)
+#define R0_SC_DPHY_PRECAL_UP (1U << 23)
+#define R0_SC_MPLL_S_OFF (1U << 24)
+#define R0_SC_DPHY_RXDLY_TRACKING_EN (1U << 25)
+#define R0_SC_PHYPLL_SHU_EN (1U << 26)
+#define R0_SC_PHYPLL2_SHU_EN (1U << 27)
+#define R0_SC_PHYPLL_MODE_SW (1U << 28)
+#define R0_SC_PHYPLL2_MODE_SW (1U << 29)
+#define R0_SC_DR_SHU_LEVEL0 (1U << 30)
+#define R0_SC_DR_SHU_LEVEL1 (1U << 31)
+/* --- R7 Define --- */
+#define R7_PWRAP_SLEEP_REQ (1U << 0)
+#define R7_EMI_CLK_OFF_REQ (1U << 1)
+#define R7_PCM_BUS_PROTECT_REQ (1U << 2)
+#define R7_SPM_CK_UPDATE (1U << 3)
+#define R7_SPM_CK_SEL0 (1U << 4)
+#define R7_SPM_CK_SEL1 (1U << 5)
+#define R7_SPM_LEAVE_DEEPIDLE_REQ (1U << 6)
+#define R7_SC_FHC_PAUSE_MPLL (1U << 7)
+#define R7_SC_26M_CK_SEL (1U << 8)
+#define R7_PCM_TIMER_SET (1U << 9)
+#define R7_PCM_TIMER_CLR (1U << 10)
+#define R7_SPM_LEAVE_SUSPEND_REQ (1U << 11)
+#define R7_CSYSPWRUPACK (1U << 12)
+#define R7_PCM_IM_SLP_EN (1U << 13)
+#define R7_SRCCLKENO0 (1U << 14)
+#define R7_FORCE_DDR_EN_WAKE (1U << 15)
+#define R7_SPM_APSRC_INTERNAL_ACK (1U << 16)
+#define R7_CPU_SYS_TIMER_CLK_SEL (1U << 17)
+#define R7_SC_AXI_DCM_DIS (1U << 18)
+#define R7_SC_FHC_PAUSE_MEM (1U << 19)
+#define R7_SC_FHC_PAUSE_MAIN (1U << 20)
+#define R7_SRCCLKENO1 (1U << 21)
+#define R7_PCM_WDT_KICK_P (1U << 22)
+#define R7_SPM2EMI_S1_MODE_ASYNC (1U << 23)
+#define R7_SC_DDR_PST_REQ_PCM (1U << 24)
+#define R7_SC_DDR_PST_ABORT_REQ_PCM (1U << 25)
+#define R7_PMIC_IRQ_REQ_EN (1U << 26)
+#define R7_FORCE_F26M_WAKE (1U << 27)
+#define R7_FORCE_APSRC_WAKE (1U << 28)
+#define R7_FORCE_INFRA_WAKE (1U << 29)
+#define R7_FORCE_VRF18_WAKE (1U << 30)
+#define R7_SPM_DDR_EN_INTERNAL_ACK (1U << 31)
+/* --- R12 Define --- */
+#define R12_PCM_TIMER (1U << 0)
+#define R12_TWAM_IRQ_B (1U << 1)
+#define R12_KP_IRQ_B (1U << 2)
+#define R12_APWDT_EVENT_B (1U << 3)
+#define R12_APXGPT1_EVENT_B (1U << 4)
+#define R12_CONN2AP_SPM_WAKEUP_B (1U << 5)
+#define R12_EINT_EVENT_B (1U << 6)
+#define R12_CONN_WDT_IRQ_B (1U << 7)
+#define R12_CCIF0_EVENT_B (1U << 8)
+#define R12_LOWBATTERY_IRQ_B (1U << 9)
+#define R12_SSPM2SPM_WAKEUP_B (1U << 10)
+#define R12_SCP2SPM_WAKEUP_B (1U << 11)
+#define R12_ADSP2SPM_WAKEUP_B (1U << 12)
+#define R12_PCM_WDT_WAKEUP_B (1U << 13)
+#define R12_USBX_CDSC_B (1U << 14)
+#define R12_USBX_POWERDWN_B (1U << 15)
+#define R12_SYS_TIMER_EVENT_B (1U << 16)
+#define R12_EINT_EVENT_SECURE_B (1U << 17)
+#define R12_CCIF1_EVENT_B (1U << 18)
+#define R12_UART0_IRQ_B (1U << 19)
+#define R12_AFE_IRQ_MCU_B (1U << 20)
+#define R12_THERM_CTRL_EVENT_B (1U << 21)
+#define R12_SYS_CIRQ_IRQ_B (1U << 22)
+#define R12_MD2AP_PEER_EVENT_B (1U << 23)
+#define R12_CSYSPWREQ_B (1U << 24)
+#define R12_MD1_WDT_B (1U << 25)
+#define R12_CLDMA_EVENT_B (1U << 26)
+#define R12_SEJ_EVENT_B (1U << 27)
+#define R12_REG_CPU_WAKEUP (1U << 28)
+#define R12_APUSYS_WAKE_HOST_B (1U << 29)
+#define R12_NOT_USED1 (1U << 30)
+#define R12_NOT_USED2 (1U << 31)
+/* --- R12ext Define --- */
+#define R12EXT_26M_WAKE (1U << 0)
+#define R12EXT_26M_SLEEP (1U << 1)
+#define R12EXT_INFRA_WAKE (1U << 2)
+#define R12EXT_INFRA_SLEEP (1U << 3)
+#define R12EXT_APSRC_WAKE (1U << 4)
+#define R12EXT_APSRC_SLEEP (1U << 5)
+#define R12EXT_VRF18_WAKE (1U << 6)
+#define R12EXT_VRF18_SLEEP (1U << 7)
+#define R12EXT_DVFS_WAKE (1U << 8)
+#define R12EXT_DDREN_WAKE (1U << 9)
+#define R12EXT_DDREN_SLEEP (1U << 10)
+#define R12EXT_MCU_PM_WFI (1U << 11)
+#define R12EXT_SSPM_IDLE (1U << 12)
+#define R12EXT_CONN_SRCCLKENB (1U << 13)
+#define R12EXT_DRAMC_SSPM_WFI_MERGE (1U << 14)
+#define R12EXT_SW_MAILBOX_WAKE (1U << 15)
+#define R12EXT_SSPM_MAILBOX_WAKE (1U << 16)
+#define R12EXT_ADSP_MAILBOX_WAKE (1U << 17)
+#define R12EXT_SCP_MAILBOX_WAKE (1U << 18)
+#define R12EXT_SPM_LEAVE_SUSPEND_ACK (1U << 19)
+#define R12EXT_SPM_LEAVE_DEEPIDLE_ACK (1U << 20)
+#define R12EXT_VS1_TRIGGER (1U << 21)
+#define R12EXT_VS2_TRIGGER (1U << 22)
+#define R12EXT_COROSS_REQ_APU (1U << 23)
+#define R12EXT_CROSS_REQ_L3 (1U << 24)
+#define R12EXT_DDR_PST_ACK (1U << 25)
+#define R12EXT_BIT26 (1U << 26)
+#define R12EXT_BIT27 (1U << 27)
+#define R12EXT_BIT28 (1U << 28)
+#define R12EXT_BIT29 (1U << 29)
+#define R12EXT_BIT30 (1U << 30)
+#define R12EXT_BIT31 (1U << 31)
+/* --- R13 Define --- */
+#define R13_SRCCLKENI0 (1U << 0)
+#define R13_SRCCLKENI1 (1U << 1)
+#define R13_MD_SRCCLKENA_0 (1U << 2)
+#define R13_MD_APSRC_REQ_0 (1U << 3)
+#define R13_CONN_DDR_EN (1U << 4)
+#define R13_MD_SRCCLKENA_1 (1U << 5)
+#define R13_SSPM_SRCCLKENA (1U << 6)
+#define R13_SSPM_APSRC_REQ (1U << 7)
+#define R13_MD1_STATE (1U << 8)
+#define R13_BIT9 (1U << 9)
+#define R13_MM_STATE (1U << 10)
+#define R13_SSPM_STATE (1U << 11)
+#define R13_MD_DDR_EN_0 (1U << 12)
+#define R13_CONN_STATE (1U << 13)
+#define R13_CONN_SRCCLKENA (1U << 14)
+#define R13_CONN_APSRC_REQ (1U << 15)
+#define R13_SC_DDR_PST_ACK_ALL (1U << 16)
+#define R13_SC_DDR_PST_ABORT_ACK_ALL (1U << 17)
+#define R13_SCP_STATE (1U << 18)
+#define R13_CSYSPWRUPREQ (1U << 19)
+#define R13_PWRAP_SLEEP_ACK (1U << 20)
+#define R13_SC_EMI_CLK_OFF_ACK_ALL (1U << 21)
+#define R13_AUDIO_DSP_STATE (1U << 22)
+#define R13_SC_DMDRAMCSHU_ACK_ALL (1U << 23)
+#define R13_CONN_SRCCLKENB (1U << 24)
+#define R13_SC_DR_SRAM_LOAD_ACK_ALL (1U << 25)
+#define R13_SUBSYS_IDLE_SIGNALS0 (1U << 26)
+#define R13_DVFS_STATE (1U << 27)
+#define R13_SC_DR_SRAM_PLL_LOAD_ACK_ALL (1U << 28)
+#define R13_SC_DR_SRAM_RESTORE_ACK_ALL (1U << 29)
+#define R13_MD_VRF18_REQ_0 (1U << 30)
+#define R13_DDR_EN_STATE (1U << 31)
+#endif /* PCM_DEF_H */
diff --git a/plat/mediatek/mt8195/drivers/spm/sleep_def.h b/plat/mediatek/mt8195/drivers/spm/sleep_def.h
new file mode 100644
index 0000000..2639b7e
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spm/sleep_def.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SLEEP_DEF_H
+#define SLEEP_DEF_H
+
+/*
+ * Auto generated by DE, please DO NOT modify this file directly.
+ */
+
+/* --- SPM Flag Define --- */
+#define SPM_FLAG_DISABLE_CPU_PDN (1U << 0)
+#define SPM_FLAG_DISABLE_INFRA_PDN (1U << 1)
+#define SPM_FLAG_DISABLE_DDRPHY_PDN (1U << 2)
+#define SPM_FLAG_DISABLE_VCORE_DVS (1U << 3)
+#define SPM_FLAG_DISABLE_VCORE_DFS (1U << 4)
+#define SPM_FLAG_DISABLE_COMMON_SCENARIO (1U << 5)
+#define SPM_FLAG_DISABLE_BUS_CLK_OFF (1U << 6)
+#define SPM_FLAG_DISABLE_ARMPLL_OFF (1U << 7)
+#define SPM_FLAG_KEEP_CSYSPWRACK_HIGH (1U << 8)
+#define SPM_FLAG_ENABLE_LVTS_WORKAROUND (1U << 9)
+#define SPM_FLAG_RUN_COMMON_SCENARIO (1U << 10)
+#define SPM_FLAG_RESERVED_BIT11 (1U << 11)
+#define SPM_FLAG_ENABLE_SPM_DBG_WDT_DUMP (1U << 12)
+#define SPM_FLAG_USE_SRCCLKENO2 (1U << 13)
+#define SPM_FLAG_ENABLE_6315_CTRL (1U << 14)
+#define SPM_FLAG_ENABLE_TIA_WORKAROUND (1U << 15)
+#define SPM_FLAG_DISABLE_SYSRAM_SLEEP (1U << 16)
+#define SPM_FLAG_DISABLE_SSPM_SRAM_SLEEP (1U << 17)
+#define SPM_FLAG_DISABLE_MCUPM_SRAM_SLEEP (1U << 18)
+#define SPM_FLAG_DISABLE_DRAMC_ISSUE_CMD (1U << 19)
+#define SPM_FLAG_ENABLE_VOLTAGE_BIN (1U << 20)
+#define SPM_FLAG_RESERVED_BIT21 (1U << 21)
+#define SPM_FLAG_DISABLE_DRAMC_MCU_SRAM_SLEEP (1U << 22)
+#define SPM_FLAG_DISABLE_DRAMC_MD32_BACKUP (1U << 23)
+#define SPM_FLAG_RESERVED_BIT24 (1U << 24)
+#define SPM_FLAG_RESERVED_BIT25 (1U << 25)
+#define SPM_FLAG_RESERVED_BIT26 (1U << 26)
+#define SPM_FLAG_VTCXO_STATE (1U << 27)
+#define SPM_FLAG_INFRA_STATE (1U << 28)
+#define SPM_FLAG_APSRC_STATE (1U << 29)
+#define SPM_FLAG_VRF18_STATE (1U << 30)
+#define SPM_FLAG_DDREN_STATE (1U << 31)
+/* --- SPM Flag1 Define --- */
+#define SPM_FLAG1_DISABLE_AXI_BUS_TO_26M (1U << 0)
+#define SPM_FLAG1_DISABLE_SYSPLL_OFF (1U << 1)
+#define SPM_FLAG1_DISABLE_PWRAP_CLK_SWITCH (1U << 2)
+#define SPM_FLAG1_DISABLE_ULPOSC_OFF (1U << 3)
+#define SPM_FLAG1_FW_SET_ULPOSC_ON (1U << 4)
+#define SPM_FLAG1_RESERVED_BIT5 (1U << 5)
+#define SPM_FLAG1_ENABLE_REKICK (1U << 6)
+#define SPM_FLAG1_RESERVED_BIT7 (1U << 7)
+#define SPM_FLAG1_RESERVED_BIT8 (1U << 8)
+#define SPM_FLAG1_RESERVED_BIT9 (1U << 9)
+#define SPM_FLAG1_DISABLE_SRCLKEN_LOW (1U << 10)
+#define SPM_FLAG1_DISABLE_SCP_CLK_SWITCH (1U << 11)
+#define SPM_FLAG1_RESERVED_BIT12 (1U << 12)
+#define SPM_FLAG1_RESERVED_BIT13 (1U << 13)
+#define SPM_FLAG1_RESERVED_BIT14 (1U << 14)
+#define SPM_FLAG1_RESERVED_BIT15 (1U << 15)
+#define SPM_FLAG1_RESERVED_BIT16 (1U << 16)
+#define SPM_FLAG1_RESERVED_BIT17 (1U << 17)
+#define SPM_FLAG1_RESERVED_BIT18 (1U << 18)
+#define SPM_FLAG1_RESERVED_BIT19 (1U << 19)
+#define SPM_FLAG1_DISABLE_DEVAPC_SRAM_SLEEP (1U << 20)
+#define SPM_FLAG1_RESERVED_BIT21 (1U << 21)
+#define SPM_FLAG1_ENABLE_VS1_VOTER (1U << 22)
+#define SPM_FLAG1_ENABLE_VS2_VOTER (1U << 23)
+#define SPM_FLAG1_DISABLE_SCP_VREQ_MASK_CONTROL (1U << 24)
+#define SPM_FLAG1_RESERVED_BIT25 (1U << 25)
+#define SPM_FLAG1_RESERVED_BIT26 (1U << 26)
+#define SPM_FLAG1_RESERVED_BIT27 (1U << 27)
+#define SPM_FLAG1_RESERVED_BIT28 (1U << 28)
+#define SPM_FLAG1_RESERVED_BIT29 (1U << 29)
+#define SPM_FLAG1_RESERVED_BIT30 (1U << 30)
+#define SPM_FLAG1_RESERVED_BIT31 (1U << 31)
+/* --- SPM DEBUG Define --- */
+#define SPM_DBG_DEBUG_IDX_26M_WAKE (1U << 0)
+#define SPM_DBG_DEBUG_IDX_26M_SLEEP (1U << 1)
+#define SPM_DBG_DEBUG_IDX_INFRA_WAKE (1U << 2)
+#define SPM_DBG_DEBUG_IDX_INFRA_SLEEP (1U << 3)
+#define SPM_DBG_DEBUG_IDX_APSRC_WAKE (1U << 4)
+#define SPM_DBG_DEBUG_IDX_APSRC_SLEEP (1U << 5)
+#define SPM_DBG_DEBUG_IDX_VRF18_WAKE (1U << 6)
+#define SPM_DBG_DEBUG_IDX_VRF18_SLEEP (1U << 7)
+#define SPM_DBG_DEBUG_IDX_DDREN_WAKE (1U << 8)
+#define SPM_DBG_DEBUG_IDX_DDREN_SLEEP (1U << 9)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_APSRC (1U << 10)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_STATE (1U << 11)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_STATE (1U << 12)
+#define SPM_DBG_DEBUG_IDX_DRAM_SREF_ABORT_IN_DDREN (1U << 13)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_STATE (1U << 14)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_SLP (1U << 15)
+#define SPM_DBG_DEBUG_IDX_SYSRAM_ON (1U << 16)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_SLP (1U << 17)
+#define SPM_DBG_DEBUG_IDX_MCUPM_SRAM_ON (1U << 18)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_SLP (1U << 19)
+#define SPM_DBG_DEBUG_IDX_SSPM_SRAM_ON (1U << 20)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_SLP (1U << 21)
+#define SPM_DBG_DEBUG_IDX_DRAMC_MCU_SRAM_ON (1U << 22)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P575V (1U << 23)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P600V (1U << 24)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P650V (1U << 25)
+#define SPM_DBG_DEBUG_IDX_SCP_VCORE_0P725V (1U << 26)
+#define SPM_DBG_DEBUG_IDX_SPM_GO_WAKEUP_NOW (1U << 27)
+#define SPM_DBG_DEBUG_IDX_VTCXO_STATE (1U << 28)
+#define SPM_DBG_DEBUG_IDX_INFRA_STATE (1U << 29)
+#define SPM_DBG_DEBUG_IDX_VRR18_STATE (1U << 30)
+#define SPM_DBG_DEBUG_IDX_APSRC_STATE (1U << 31)
+/* --- SPM DEBUG1 Define --- */
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_LP (1U << 0)
+#define SPM_DBG1_DEBUG_IDX_VCORE_DVFS_START (1U << 1)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_OFF (1U << 2)
+#define SPM_DBG1_DEBUG_IDX_SYSPLL_ON (1U << 3)
+#define SPM_DBG1_DEBUG_IDX_CURRENT_IS_VCORE_DVFS (1U << 4)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_OFF (1U << 5)
+#define SPM_DBG1_DEBUG_IDX_INFRA_MTCMOS_ON (1U << 6)
+#define SPM_DBG1_DEBUG_IDX_VRCXO_SLEEP_ABORT (1U << 7)
+#define SPM_DBG1_RESERVED_BIT8 (1U << 8)
+#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_OFF (1U << 9)
+#define SPM_DBG1_DEBUG_IDX_INFRA_SUB_MTCMOS_ON (1U << 10)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_ULPOSC (1U << 11)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_CLK_TO_26M (1U << 12)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_32K (1U << 13)
+#define SPM_DBG1_DEBUG_IDX_SCP_CLK_TO_26M (1U << 14)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_OFF (1U << 15)
+#define SPM_DBG1_DEBUG_IDX_BUS_CLK_ON (1U << 16)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_LOW (1U << 17)
+#define SPM_DBG1_DEBUG_IDX_SRCLKEN2_HIGH (1U << 18)
+#define SPM_DBG1_RESERVED_BIT19 (1U << 19)
+#define SPM_DBG1_DEBUG_IDX_ULPOSC_IS_OFF_BUT_SHOULD_ON (1U << 20)
+#define SPM_DBG1_DEBUG_IDX_6315_LOW (1U << 21)
+#define SPM_DBG1_DEBUG_IDX_6315_HIGH (1U << 22)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_LOW_ABORT (1U << 23)
+#define SPM_DBG1_DEBUG_IDX_PWRAP_SLEEP_ACK_HIGH_ABORT (1U << 24)
+#define SPM_DBG1_DEBUG_IDX_EMI_SLP_IDLE_ABORT (1U << 25)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_LOW_ABORT (1U << 26)
+#define SPM_DBG1_DEBUG_IDX_SCP_SLP_ACK_HIGH_ABORT (1U << 27)
+#define SPM_DBG1_DEBUG_IDX_SPM_DVFS_CMD_RDY_ABORT (1U << 28)
+#define SPM_DBG1_RESERVED_BIT29 (1U << 29)
+#define SPM_DBG1_RESERVED_BIT30 (1U << 30)
+#define SPM_DBG1_RESERVED_BIT31 (1U << 31)
+
+ /* Macro and Inline */
+#define is_cpu_pdn(flags) (((flags) & SPM_FLAG_DISABLE_CPU_PDN) == 0U)
+#define is_infra_pdn(flags) (((flags) & SPM_FLAG_DISABLE_INFRA_PDN) == 0U)
+#define is_ddrphy_pdn(flags) (((flags) & SPM_FLAG_DISABLE_DDRPHY_PDN) == 0U)
+#endif /* SLEEP_DEF_H */
diff --git a/plat/mediatek/mt8195/drivers/spmc/mtspmc.c b/plat/mediatek/mt8195/drivers/spmc/mtspmc.c
new file mode 100644
index 0000000..9b332a0
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spmc/mtspmc.c
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include <mcucfg.h>
+#include <mtspmc.h>
+#include <mtspmc_private.h>
+
+
+void mcucfg_disable_gic_wakeup(unsigned int cluster, unsigned int cpu)
+{
+ mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu));
+}
+
+void mcucfg_enable_gic_wakeup(unsigned int cluster, unsigned int cpu)
+{
+ mmio_clrbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, GIC_WAKEUP_IGNORE(cpu));
+}
+
+void mcucfg_set_bootaddr(unsigned int cluster, unsigned int cpu, uintptr_t bootaddr)
+{
+ assert(cluster == 0U);
+
+ mmio_write_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR), bootaddr);
+}
+
+uintptr_t mcucfg_get_bootaddr(unsigned int cluster, unsigned int cpu)
+{
+ assert(cluster == 0U);
+
+ return (uintptr_t)mmio_read_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR));
+}
+
+void mcucfg_init_archstate(unsigned int cluster, unsigned int cpu, bool arm64)
+{
+ uint32_t reg;
+
+ assert(cluster == 0U);
+
+ reg = per_cluster(cluster, MCUCFG_INITARCH);
+
+ if (arm64) {
+ mmio_setbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu));
+ } else {
+ mmio_clrbits_32(reg, MCUCFG_INITARCH_CPU_BIT(cpu));
+ }
+}
+
+/**
+ * Return subsystem's power state.
+ *
+ * @mask: mask to MCUCFG_CPC_SPMC_PWR_STATUS to query the power state
+ * of one subsystem.
+ * RETURNS:
+ * 0 (the subsys was powered off)
+ * 1 (the subsys was powered on)
+ */
+bool spm_get_powerstate(uint32_t mask)
+{
+ return (mmio_read_32(MCUCFG_CPC_SPMC_PWR_STATUS) & mask) != 0U;
+}
+
+bool spm_get_cluster_powerstate(unsigned int cluster)
+{
+ assert(cluster == 0U);
+
+ return spm_get_powerstate(BIT(14));
+}
+
+bool spm_get_cpu_powerstate(unsigned int cluster, unsigned int cpu)
+{
+ uint32_t mask = BIT(cpu);
+
+ assert(cluster == 0U);
+
+ return spm_get_powerstate(mask);
+}
+
+int spmc_init(void)
+{
+ INFO("SPM: enable CPC mode\n");
+
+ mmio_write_32(SPM_POWERON_CONFIG_EN, PROJECT_CODE | BCLK_CG_EN);
+
+ mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B);
+ mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B);
+ mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B);
+ mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B);
+ mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B);
+ mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B);
+ mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B);
+
+ mmio_clrbits_32(SPM_MCUSYS_PWR_CON, RESETPWRON_CONFIG);
+ mmio_clrbits_32(SPM_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG);
+ mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), RESETPWRON_CONFIG);
+
+ mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, CPC_CTRL_ENABLE);
+ mmio_setbits_32(MCUCFG_CPC_FLOW_CTRL_CFG, SSPM_CORE_PWR_ON_EN);
+
+ return 0;
+}
+
+/**
+ * Power on a core with specified cluster and core index
+ *
+ * @cluster: the cluster ID of the CPU which to be powered on
+ * @cpu: the CPU ID of the CPU which to be powered on
+ */
+void spm_poweron_cpu(unsigned int cluster, unsigned int cpu)
+{
+ uintptr_t cpu_pwr_con = per_cpu(cluster, cpu, SPM_CPU_PWR);
+
+ /* set to 0 after BIG VPROC bulk on & before B-core power on seq. */
+ if (cpu >= 4U) {
+ mmio_write_32(DREQ20_BIG_VPROC_ISO, 0U);
+ }
+
+ mmio_setbits_32(cpu_pwr_con, PWR_ON);
+
+ while (!spm_get_cpu_powerstate(cluster, cpu)) {
+ mmio_clrbits_32(cpu_pwr_con, PWR_ON);
+ mmio_setbits_32(cpu_pwr_con, PWR_ON);
+ }
+}
+
+/**
+ * Power off a core with specified cluster and core index
+ *
+ * @cluster: the cluster ID of the CPU which to be powered off
+ * @cpu: the CPU ID of the CPU which to be powered off
+ */
+void spm_poweroff_cpu(unsigned int cluster, unsigned int cpu)
+{
+ /* Set mp0_spmc_pwr_on_cpuX = 0 */
+ mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWR_ON);
+}
+
+/**
+ * Power off a cluster with specified index
+ *
+ * @cluster: the cluster index which to be powered off
+ */
+void spm_poweroff_cluster(unsigned int cluster)
+{
+ /* No need to power on/off cluster on single cluster platform */
+ assert(false);
+}
+
+/**
+ * Power on a cluster with specified index
+ *
+ * @cluster: the cluster index which to be powered on
+ */
+void spm_poweron_cluster(unsigned int cluster)
+{
+ /* No need to power on/off cluster on single cluster platform */
+ assert(false);
+}
diff --git a/plat/mediatek/mt8195/drivers/spmc/mtspmc.h b/plat/mediatek/mt8195/drivers/spmc/mtspmc.h
new file mode 100644
index 0000000..34e93d0
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spmc/mtspmc.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTSPMC_H
+#define MTSPMC_H
+
+#include <stdint.h>
+
+int spmc_init(void);
+
+void spm_poweron_cpu(unsigned int cluster, unsigned int cpu);
+void spm_poweroff_cpu(unsigned int cluster, unsigned int cpu);
+
+void spm_poweroff_cluster(unsigned int cluster);
+void spm_poweron_cluster(unsigned int cluster);
+
+bool spm_get_cpu_powerstate(unsigned int cluster, unsigned int cpu);
+bool spm_get_cluster_powerstate(unsigned int cluster);
+bool spm_get_powerstate(uint32_t mask);
+
+void mcucfg_init_archstate(unsigned int cluster, unsigned int cpu, bool arm64);
+void mcucfg_set_bootaddr(unsigned int cluster, unsigned int cpu, uintptr_t bootaddr);
+uintptr_t mcucfg_get_bootaddr(unsigned int cluster, unsigned int cpu);
+
+void mcucfg_disable_gic_wakeup(unsigned int cluster, unsigned int cpu);
+void mcucfg_enable_gic_wakeup(unsigned int cluster, unsigned int cpu);
+
+#endif /* MTSPMC_H */
diff --git a/plat/mediatek/mt8195/drivers/spmc/mtspmc_private.h b/plat/mediatek/mt8195/drivers/spmc/mtspmc_private.h
new file mode 100644
index 0000000..bf4092e
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/spmc/mtspmc_private.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MTSPMC_PRIVATE_H
+#define MTSPMC_PRIVATE_H
+
+#include <lib/utils_def.h>
+#include <platform_def.h>
+
+unsigned long read_cpuectlr(void);
+void write_cpuectlr(unsigned long cpuectlr);
+
+unsigned long read_cpupwrctlr_el1(void);
+void write_cpupwrctlr_el1(unsigned long cpuectlr);
+
+/*
+ * per_cpu/cluster helper
+ */
+struct per_cpu_reg {
+ unsigned int cluster_addr;
+ unsigned int cpu_stride;
+};
+
+#define per_cpu(cluster, cpu, reg) \
+ (reg[cluster].cluster_addr + (cpu << reg[cluster].cpu_stride))
+
+#define per_cluster(cluster, reg) (reg[cluster].cluster_addr)
+
+#define SPM_REG(ofs) (uint32_t)(SPM_BASE + (ofs))
+#define MCUCFG_REG(ofs) (uint32_t)(MCUCFG_BASE + (ofs))
+#define INFRACFG_AO_REG(ofs) (uint32_t)(INFRACFG_AO_BASE + (ofs))
+
+/* === SPMC related registers */
+#define SPM_POWERON_CONFIG_EN SPM_REG(0x000)
+/* bit-fields of SPM_POWERON_CONFIG_EN */
+#define PROJECT_CODE (U(0xb16) << 16)
+#define BCLK_CG_EN BIT(0)
+
+#define SPM_PWR_STATUS SPM_REG(0x16c)
+#define SPM_PWR_STATUS_2ND SPM_REG(0x170)
+#define SPM_CPU_PWR_STATUS SPM_REG(0x174)
+
+/* bit-fields of SPM_PWR_STATUS */
+#define MD BIT(0)
+#define CONN BIT(1)
+#define DDRPHY BIT(2)
+#define DISP BIT(3)
+#define MFG BIT(4)
+#define ISP BIT(5)
+#define INFRA BIT(6)
+#define VDEC BIT(7)
+#define MP0_CPUTOP BIT(8)
+#define MP0_CPU0 BIT(9)
+#define MP0_CPU1 BIT(10)
+#define MP0_CPU2 BIT(11)
+#define MP0_CPU3 BIT(12)
+#define MCUSYS BIT(14)
+#define MP0_CPU4 BIT(15)
+#define MP0_CPU5 BIT(16)
+#define MP0_CPU6 BIT(17)
+#define MP0_CPU7 BIT(18)
+#define VEN BIT(21)
+
+/* === SPMC related registers */
+#define SPM_MCUSYS_PWR_CON MCUCFG_REG(0xd200)
+#define SPM_MP0_CPUTOP_PWR_CON MCUCFG_REG(0xd204)
+#define SPM_MP0_CPU0_PWR_CON MCUCFG_REG(0xd208)
+#define SPM_MP0_CPU1_PWR_CON MCUCFG_REG(0xd20c)
+#define SPM_MP0_CPU2_PWR_CON MCUCFG_REG(0xd210)
+#define SPM_MP0_CPU3_PWR_CON MCUCFG_REG(0xd214)
+#define SPM_MP0_CPU4_PWR_CON MCUCFG_REG(0xd218)
+#define SPM_MP0_CPU5_PWR_CON MCUCFG_REG(0xd21c)
+#define SPM_MP0_CPU6_PWR_CON MCUCFG_REG(0xd220)
+#define SPM_MP0_CPU7_PWR_CON MCUCFG_REG(0xd224)
+
+/* bit fields of SPM_*_PWR_CON */
+#define PWR_ON_ACK BIT(31)
+#define VPROC_EXT_OFF BIT(7)
+#define DORMANT_EN BIT(6)
+#define RESETPWRON_CONFIG BIT(5)
+#define PWR_CLK_DIS BIT(4)
+#define PWR_ON BIT(2)
+#define PWR_RST_B BIT(0)
+
+/**** per_cpu registers for SPM_MP0_CPU?_PWR_CON */
+static const struct per_cpu_reg SPM_CPU_PWR[] = {
+ { .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2U }
+};
+
+/**** per_cluster registers for SPM_MP0_CPUTOP_PWR_CON */
+static const struct per_cpu_reg SPM_CLUSTER_PWR[] = {
+ { .cluster_addr = SPM_MP0_CPUTOP_PWR_CON, .cpu_stride = 0U }
+};
+
+/* === MCUCFG related registers */
+/* aa64naa32 */
+#define MCUCFG_MP0_CLUSTER_CFG5 MCUCFG_REG(0xc8e4)
+/* reset vectors */
+#define MCUCFG_MP0_CLUSTER_CFG8 MCUCFG_REG(0xc900)
+#define MCUCFG_MP0_CLUSTER_CFG10 MCUCFG_REG(0xc908)
+#define MCUCFG_MP0_CLUSTER_CFG12 MCUCFG_REG(0xc910)
+#define MCUCFG_MP0_CLUSTER_CFG14 MCUCFG_REG(0xc918)
+#define MCUCFG_MP0_CLUSTER_CFG16 MCUCFG_REG(0xc920)
+#define MCUCFG_MP0_CLUSTER_CFG18 MCUCFG_REG(0xc928)
+#define MCUCFG_MP0_CLUSTER_CFG20 MCUCFG_REG(0xc930)
+#define MCUCFG_MP0_CLUSTER_CFG22 MCUCFG_REG(0xc938)
+
+/* MCUSYS DREQ BIG VPROC ISO control */
+#define DREQ20_BIG_VPROC_ISO MCUCFG_REG(0xad8c)
+
+/**** per_cpu registers for MCUCFG_MP0_CLUSTER_CFG? */
+static const struct per_cpu_reg MCUCFG_BOOTADDR[] = {
+ { .cluster_addr = MCUCFG_MP0_CLUSTER_CFG8, .cpu_stride = 3U }
+};
+
+/**** per_cpu registers for MCUCFG_MP0_CLUSTER_CFG5 */
+static const struct per_cpu_reg MCUCFG_INITARCH[] = {
+ { .cluster_addr = MCUCFG_MP0_CLUSTER_CFG5, .cpu_stride = 0U }
+};
+
+#define MCUCFG_INITARCH_CPU_BIT(cpu) BIT(16U + cpu)
+/* === CPC control */
+#define MCUCFG_CPC_FLOW_CTRL_CFG MCUCFG_REG(0xa814)
+#define MCUCFG_CPC_SPMC_PWR_STATUS MCUCFG_REG(0xa840)
+
+/* bit fields of CPC_FLOW_CTRL_CFG */
+#define CPC_CTRL_ENABLE BIT(16)
+#define SSPM_CORE_PWR_ON_EN BIT(7) /* for cpu-hotplug */
+#define SSPM_ALL_PWR_CTRL_EN BIT(13) /* for cpu-hotplug */
+#define GIC_WAKEUP_IGNORE(cpu) BIT(21 + cpu)
+
+/* bit fields of CPC_SPMC_PWR_STATUS */
+#define CORE_SPMC_PWR_ON_ACK GENMASK(11, 0)
+
+/* === APB Module infracfg_ao */
+#define INFRA_TOPAXI_PROTECTEN INFRACFG_AO_REG(0x0220)
+#define INFRA_TOPAXI_PROTECTEN_STA0 INFRACFG_AO_REG(0x0224)
+#define INFRA_TOPAXI_PROTECTEN_STA1 INFRACFG_AO_REG(0x0228)
+#define INFRA_TOPAXI_PROTECTEN_SET INFRACFG_AO_REG(0x02a0)
+#define INFRA_TOPAXI_PROTECTEN_CLR INFRACFG_AO_REG(0x02a4)
+#define INFRA_TOPAXI_PROTECTEN_1 INFRACFG_AO_REG(0x0250)
+#define INFRA_TOPAXI_PROTECTEN_STA0_1 INFRACFG_AO_REG(0x0254)
+#define INFRA_TOPAXI_PROTECTEN_STA1_1 INFRACFG_AO_REG(0x0258)
+#define INFRA_TOPAXI_PROTECTEN_1_SET INFRACFG_AO_REG(0x02a8)
+#define INFRA_TOPAXI_PROTECTEN_1_CLR INFRACFG_AO_REG(0x02ac)
+
+/* bit fields of INFRA_TOPAXI_PROTECTEN */
+#define MP0_SPMC_PROT_STEP1_0_MASK BIT(12)
+#define MP0_SPMC_PROT_STEP1_1_MASK (BIT(26) | BIT(12))
+
+/* === SPARK */
+#define VOLTAGE_04 U(0x40)
+#define VOLTAGE_05 U(0x60)
+
+#define PTP3_CPU0_SPMC_SW_CFG MCUCFG_REG(0x200)
+#define CPU0_ILDO_CONTROL5 MCUCFG_REG(0x334)
+#define CPU0_ILDO_CONTROL8 MCUCFG_REG(0x340)
+
+/* bit fields of CPU0_ILDO_CONTROL5 */
+#define ILDO_RET_VOSEL GENMASK(7, 0)
+
+/* bit fields of PTP3_CPU_SPMC_SW_CFG */
+#define SW_SPARK_EN BIT(0)
+
+/* bit fields of CPU0_ILDO_CONTROL8 */
+#define ILDO_BYPASS_B BIT(0)
+
+static const struct per_cpu_reg MCUCFG_SPARK[] = {
+ { .cluster_addr = PTP3_CPU0_SPMC_SW_CFG, .cpu_stride = 11U }
+};
+
+static const struct per_cpu_reg ILDO_CONTROL5[] = {
+ { .cluster_addr = CPU0_ILDO_CONTROL5, .cpu_stride = 11U }
+};
+
+static const struct per_cpu_reg ILDO_CONTROL8[] = {
+ { .cluster_addr = CPU0_ILDO_CONTROL8, .cpu_stride = 11U }
+};
+
+#endif /* MTSPMC_PRIVATE_H */
diff --git a/plat/mediatek/mt8195/include/mcucfg.h b/plat/mediatek/mt8195/include/mcucfg.h
new file mode 100644
index 0000000..046cf73
--- /dev/null
+++ b/plat/mediatek/mt8195/include/mcucfg.h
@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MCUCFG_H
+#define MCUCFG_H
+
+#ifndef __ASSEMBLER__
+#include <stdint.h>
+#endif /* __ASSEMBLER__ */
+
+#include <platform_def.h>
+
+#define MCUCFG_REG(ofs) (uint32_t)(MCUCFG_BASE + (ofs))
+
+#define MP2_MISC_CONFIG_BOOT_ADDR_L(cpu) (MCUCFG_REG(0x2290) + ((cpu) * 8))
+#define MP2_MISC_CONFIG_BOOT_ADDR_H(cpu) (MCUCFG_REG(0x2294) + ((cpu) * 8))
+
+#define MP2_CPUCFG MCUCFG_REG(0x2208)
+
+#define MP2_CPU0_STANDBYWFE BIT(4)
+#define MP2_CPU1_STANDBYWFE BIT(5)
+
+#define MP0_CPUTOP_SPMC_CTL MCUCFG_REG(0x788)
+#define MP1_CPUTOP_SPMC_CTL MCUCFG_REG(0x78C)
+#define MP1_CPUTOP_SPMC_SRAM_CTL MCUCFG_REG(0x790)
+
+#define sw_spark_en BIT(0)
+#define sw_no_wait_for_q_channel BIT(1)
+#define sw_fsm_override BIT(2)
+#define sw_logic_pre1_pdb BIT(3)
+#define sw_logic_pre2_pdb BIT(4)
+#define sw_logic_pdb BIT(5)
+#define sw_iso BIT(6)
+#define sw_sram_sleepb (U(0x3F) << 7)
+#define sw_sram_isointb BIT(13)
+#define sw_clk_dis BIT(14)
+#define sw_ckiso BIT(15)
+#define sw_pd (U(0x3F) << 16)
+#define sw_hot_plug_reset BIT(22)
+#define sw_pwr_on_override_en BIT(23)
+#define sw_pwr_on BIT(24)
+#define sw_coq_dis BIT(25)
+#define logic_pdbo_all_off_ack BIT(26)
+#define logic_pdbo_all_on_ack BIT(27)
+#define logic_pre2_pdbo_all_on_ack BIT(28)
+#define logic_pre1_pdbo_all_on_ack BIT(29)
+
+
+#define CPUSYSx_CPUx_SPMC_CTL(cluster, cpu) \
+ (MCUCFG_REG(0x1c30) + cluster * 0x2000 + cpu * 4)
+
+#define CPUSYS0_CPU0_SPMC_CTL MCUCFG_REG(0x1c30)
+#define CPUSYS0_CPU1_SPMC_CTL MCUCFG_REG(0x1c34)
+#define CPUSYS0_CPU2_SPMC_CTL MCUCFG_REG(0x1c38)
+#define CPUSYS0_CPU3_SPMC_CTL MCUCFG_REG(0x1c3C)
+
+#define CPUSYS1_CPU0_SPMC_CTL MCUCFG_REG(0x3c30)
+#define CPUSYS1_CPU1_SPMC_CTL MCUCFG_REG(0x3c34)
+#define CPUSYS1_CPU2_SPMC_CTL MCUCFG_REG(0x3c38)
+#define CPUSYS1_CPU3_SPMC_CTL MCUCFG_REG(0x3c3C)
+
+#define cpu_sw_spark_en BIT(0)
+#define cpu_sw_no_wait_for_q_channel BIT(1)
+#define cpu_sw_fsm_override BIT(2)
+#define cpu_sw_logic_pre1_pdb BIT(3)
+#define cpu_sw_logic_pre2_pdb BIT(4)
+#define cpu_sw_logic_pdb BIT(5)
+#define cpu_sw_iso BIT(6)
+#define cpu_sw_sram_sleepb BIT(7)
+#define cpu_sw_sram_isointb BIT(8)
+#define cpu_sw_clk_dis BIT(9)
+#define cpu_sw_ckiso BIT(10)
+#define cpu_sw_pd (U(0x1F) << 11)
+#define cpu_sw_hot_plug_reset BIT(16)
+#define cpu_sw_powr_on_override_en BIT(17)
+#define cpu_sw_pwr_on BIT(18)
+#define cpu_spark2ldo_allswoff BIT(19)
+#define cpu_pdbo_all_on_ack BIT(20)
+#define cpu_pre2_pdbo_allon_ack BIT(21)
+#define cpu_pre1_pdbo_allon_ack BIT(22)
+
+/* CPC related registers */
+#define CPC_MCUSYS_CPC_OFF_THRES MCUCFG_REG(0xa714)
+#define CPC_MCUSYS_PWR_CTRL MCUCFG_REG(0xa804)
+#define CPC_MCUSYS_CPC_FLOW_CTRL_CFG MCUCFG_REG(0xa814)
+#define CPC_MCUSYS_LAST_CORE_REQ MCUCFG_REG(0xa818)
+#define CPC_MCUSYS_MP_LAST_CORE_RESP MCUCFG_REG(0xa81c)
+#define CPC_MCUSYS_LAST_CORE_RESP MCUCFG_REG(0xa824)
+#define CPC_MCUSYS_PWR_ON_MASK MCUCFG_REG(0xa828)
+#define CPC_MCUSYS_CPU_ON_SW_HINT_SET MCUCFG_REG(0xa8a8)
+#define CPC_MCUSYS_CPU_ON_SW_HINT_CLR MCUCFG_REG(0xa8ac)
+#define CPC_MCUSYS_CPC_DBG_SETTING MCUCFG_REG(0xab00)
+#define CPC_MCUSYS_CPC_KERNEL_TIME_L_BASE MCUCFG_REG(0xab04)
+#define CPC_MCUSYS_CPC_KERNEL_TIME_H_BASE MCUCFG_REG(0xab08)
+#define CPC_MCUSYS_CPC_SYSTEM_TIME_L_BASE MCUCFG_REG(0xab0c)
+#define CPC_MCUSYS_CPC_SYSTEM_TIME_H_BASE MCUCFG_REG(0xab10)
+#define CPC_MCUSYS_TRACE_SEL MCUCFG_REG(0xab14)
+#define CPC_MCUSYS_TRACE_DATA MCUCFG_REG(0xab20)
+#define CPC_MCUSYS_CLUSTER_COUNTER MCUCFG_REG(0xab70)
+#define CPC_MCUSYS_CLUSTER_COUNTER_CLR MCUCFG_REG(0xab74)
+
+#define SPARK2LDO MCUCFG_REG(0x2700)
+/* APB Module mcucfg */
+#define MP0_CA7_CACHE_CONFIG MCUCFG_REG(0x000)
+#define MP0_AXI_CONFIG MCUCFG_REG(0x02C)
+#define MP0_MISC_CONFIG0 MCUCFG_REG(0x030)
+#define MP0_MISC_CONFIG1 MCUCFG_REG(0x034)
+#define MP0_MISC_CONFIG2 MCUCFG_REG(0x038)
+#define MP0_MISC_CONFIG_BOOT_ADDR(cpu) (MP0_MISC_CONFIG2 + ((cpu) * 8))
+#define MP0_MISC_CONFIG3 MCUCFG_REG(0x03C)
+#define MP0_MISC_CONFIG9 MCUCFG_REG(0x054)
+#define MP0_CA7_MISC_CONFIG MCUCFG_REG(0x064)
+
+#define MP0_RW_RSVD0 MCUCFG_REG(0x06C)
+
+
+#define MP1_CA7_CACHE_CONFIG MCUCFG_REG(0x200)
+#define MP1_AXI_CONFIG MCUCFG_REG(0x22C)
+#define MP1_MISC_CONFIG0 MCUCFG_REG(0x230)
+#define MP1_MISC_CONFIG1 MCUCFG_REG(0x234)
+#define MP1_MISC_CONFIG2 MCUCFG_REG(0x238)
+#define MP1_MISC_CONFIG_BOOT_ADDR(cpu) (MP1_MISC_CONFIG2 + ((cpu) * 8))
+#define MP1_MISC_CONFIG3 MCUCFG_REG(0x23C)
+#define MP1_MISC_CONFIG9 MCUCFG_REG(0x254)
+#define MP1_CA7_MISC_CONFIG MCUCFG_REG(0x264)
+
+#define CCI_ADB400_DCM_CONFIG MCUCFG_REG(0x740)
+#define SYNC_DCM_CONFIG MCUCFG_REG(0x744)
+
+#define MP0_CLUSTER_CFG0 MCUCFG_REG(0xC8D0)
+
+#define MP0_SPMC MCUCFG_REG(0x788)
+#define MP1_SPMC MCUCFG_REG(0x78C)
+#define MP2_AXI_CONFIG MCUCFG_REG(0x220C)
+#define MP2_AXI_CONFIG_ACINACTM BIT(0)
+#define MP2_AXI_CONFIG_AINACTS BIT(4)
+
+#define MPx_AXI_CONFIG_ACINACTM BIT(4)
+#define MPx_AXI_CONFIG_AINACTS BIT(5)
+
+#define MPx_CA7_MISC_CONFIG_standbywfil2 BIT(28)
+
+#define MP0_CPU0_STANDBYWFE BIT(20)
+#define MP0_CPU1_STANDBYWFE BIT(21)
+#define MP0_CPU2_STANDBYWFE BIT(22)
+#define MP0_CPU3_STANDBYWFE BIT(23)
+
+#define MP1_CPU0_STANDBYWFE BIT(20)
+#define MP1_CPU1_STANDBYWFE BIT(21)
+#define MP1_CPU2_STANDBYWFE BIT(22)
+#define MP1_CPU3_STANDBYWFE BIT(23)
+
+#define CPUSYS0_SPARKVRETCNTRL MCUCFG_REG(0x1c00)
+#define CPUSYS0_SPARKEN MCUCFG_REG(0x1c04)
+#define CPUSYS0_AMUXSEL MCUCFG_REG(0x1c08)
+#define CPUSYS1_SPARKVRETCNTRL MCUCFG_REG(0x3c00)
+#define CPUSYS1_SPARKEN MCUCFG_REG(0x3c04)
+#define CPUSYS1_AMUXSEL MCUCFG_REG(0x3c08)
+
+#define MP2_PWR_RST_CTL MCUCFG_REG(0x2008)
+#define MP2_PTP3_CPUTOP_SPMC0 MCUCFG_REG(0x22A0)
+#define MP2_PTP3_CPUTOP_SPMC1 MCUCFG_REG(0x22A4)
+
+#define MP2_COQ MCUCFG_REG(0x22BC)
+#define MP2_COQ_SW_DIS BIT(0)
+
+#define MP2_CA15M_MON_SEL MCUCFG_REG(0x2400)
+#define MP2_CA15M_MON_L MCUCFG_REG(0x2404)
+
+#define CPUSYS2_CPU0_SPMC_CTL MCUCFG_REG(0x2430)
+#define CPUSYS2_CPU1_SPMC_CTL MCUCFG_REG(0x2438)
+#define CPUSYS2_CPU0_SPMC_STA MCUCFG_REG(0x2434)
+#define CPUSYS2_CPU1_SPMC_STA MCUCFG_REG(0x243C)
+
+#define MP0_CA7L_DBG_PWR_CTRL MCUCFG_REG(0x068)
+#define MP1_CA7L_DBG_PWR_CTRL MCUCFG_REG(0x268)
+#define BIG_DBG_PWR_CTRL MCUCFG_REG(0x75C)
+
+#define MP2_SW_RST_B BIT(0)
+#define MP2_TOPAON_APB_MASK BIT(1)
+
+#define B_SW_HOT_PLUG_RESET BIT(30)
+
+#define B_SW_PD_OFFSET 18U
+#define B_SW_PD (U(0x3f) << B_SW_PD_OFFSET)
+
+#define B_SW_SRAM_SLEEPB_OFFSET 12U
+#define B_SW_SRAM_SLEEPB (U(0x3f) << B_SW_SRAM_SLEEPB_OFFSET)
+
+#define B_SW_SRAM_ISOINTB BIT(9)
+#define B_SW_ISO BIT(8)
+#define B_SW_LOGIC_PDB BIT(7)
+#define B_SW_LOGIC_PRE2_PDB BIT(6)
+#define B_SW_LOGIC_PRE1_PDB BIT(5)
+#define B_SW_FSM_OVERRIDE BIT(4)
+#define B_SW_PWR_ON BIT(3)
+#define B_SW_PWR_ON_OVERRIDE_EN BIT(2)
+
+#define B_FSM_STATE_OUT_OFFSET (6U)
+#define B_FSM_STATE_OUT_MASK (U(0x1f) << B_FSM_STATE_OUT_OFFSET)
+#define B_SW_LOGIC_PDBO_ALL_OFF_ACK BIT(5)
+#define B_SW_LOGIC_PDBO_ALL_ON_ACK BIT(4)
+#define B_SW_LOGIC_PRE2_PDBO_ALL_ON_ACK BIT(3)
+#define B_SW_LOGIC_PRE1_PDBO_ALL_ON_ACK BIT(2)
+
+#define B_FSM_OFF (0U << B_FSM_STATE_OUT_OFFSET)
+#define B_FSM_ON (1U << B_FSM_STATE_OUT_OFFSET)
+#define B_FSM_RET (2U << B_FSM_STATE_OUT_OFFSET)
+
+#ifndef __ASSEMBLER__
+/* cpu boot mode */
+enum {
+ MP0_CPUCFG_64BIT_SHIFT = 12U,
+ MP1_CPUCFG_64BIT_SHIFT = 28U,
+ MP0_CPUCFG_64BIT = U(0xf) << MP0_CPUCFG_64BIT_SHIFT,
+ MP1_CPUCFG_64BIT = U(0xf) << MP1_CPUCFG_64BIT_SHIFT
+};
+
+enum {
+ MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0U,
+ MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4U,
+ MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8U,
+ MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12U,
+ MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16U,
+
+ MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK =
+ U(0xf) << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT,
+ MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK =
+ U(0xf) << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT,
+ MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK =
+ U(0xf) << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT,
+ MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK =
+ U(0xf) << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT,
+ MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK =
+ U(0xf) << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT
+};
+
+enum {
+ MP1_AINACTS_SHIFT = 4U,
+ MP1_AINACTS = 1U << MP1_AINACTS_SHIFT
+};
+
+enum {
+ MP1_SW_CG_GEN_SHIFT = 12U,
+ MP1_SW_CG_GEN = 1U << MP1_SW_CG_GEN_SHIFT
+};
+
+enum {
+ MP1_L2RSTDISABLE_SHIFT = 14U,
+ MP1_L2RSTDISABLE = 1U << MP1_L2RSTDISABLE_SHIFT
+};
+#endif /* __ASSEMBLER__ */
+
+#endif /* MCUCFG_H */
diff --git a/plat/mediatek/mt8195/include/plat_helpers.h b/plat/mediatek/mt8195/include/plat_helpers.h
new file mode 100644
index 0000000..ebc9fa0
--- /dev/null
+++ b/plat/mediatek/mt8195/include/plat_helpers.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __PLAT_HELPERS_H__
+#define __PLAT_HELPERS_H__
+
+unsigned int plat_mediatek_calc_core_pos(u_register_t mpidr);
+
+#endif /* __PLAT_HELPERS_H__ */
diff --git a/plat/mediatek/mt8195/include/plat_macros.S b/plat/mediatek/mt8195/include/plat_macros.S
new file mode 100644
index 0000000..39727ea
--- /dev/null
+++ b/plat/mediatek/mt8195/include/plat_macros.S
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef PLAT_MACROS_S
+#define PLAT_MACROS_S
+
+#include <platform_def.h>
+
+.section .rodata.gic_reg_name, "aS"
+gicc_regs:
+ .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
+gicd_pend_reg:
+ .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \
+ " Offset:\t\t\tvalue\n"
+newline:
+ .asciz "\n"
+spacer:
+ .asciz ":\t\t0x"
+
+.section .rodata.cci_reg_name, "aS"
+cci_iface_regs:
+ .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
+
+ /* ---------------------------------------------
+ * The below macro prints out relevant GIC
+ * registers whenever an unhandled exception
+ * is taken in BL31.
+ * Clobbers: x0 - x10, x26, x27, sp
+ * ---------------------------------------------
+ */
+ .macro plat_crash_print_regs
+ /* TODO: leave implementation to GIC owner */
+ .endm
+
+#endif /* PLAT_MACROS_S */
diff --git a/plat/mediatek/mt8195/include/plat_mtk_lpm.h b/plat/mediatek/mt8195/include/plat_mtk_lpm.h
new file mode 100644
index 0000000..347f358
--- /dev/null
+++ b/plat/mediatek/mt8195/include/plat_mtk_lpm.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_MTK_LPM_H
+#define PLAT_MTK_LPM_H
+
+#include <lib/psci/psci.h>
+#include <lib/utils_def.h>
+
+#define MT_IRQ_REMAIN_MAX U(32)
+#define MT_IRQ_REMAIN_CAT_LOG BIT(31)
+
+struct mt_irqremain {
+ unsigned int count;
+ unsigned int irqs[MT_IRQ_REMAIN_MAX];
+ unsigned int wakeupsrc_cat[MT_IRQ_REMAIN_MAX];
+ unsigned int wakeupsrc[MT_IRQ_REMAIN_MAX];
+};
+
+#define PLAT_RC_STATUS_READY BIT(0)
+#define PLAT_RC_STATUS_FEATURE_EN BIT(1)
+#define PLAT_RC_STATUS_UART_NONSLEEP BIT(31)
+
+struct mt_lpm_tz {
+ int (*pwr_prompt)(unsigned int cpu, const psci_power_state_t *state);
+ int (*pwr_reflect)(unsigned int cpu, const psci_power_state_t *state);
+
+ int (*pwr_cpu_on)(unsigned int cpu, const psci_power_state_t *state);
+ int (*pwr_cpu_dwn)(unsigned int cpu, const psci_power_state_t *state);
+
+ int (*pwr_cluster_on)(unsigned int cpu,
+ const psci_power_state_t *state);
+ int (*pwr_cluster_dwn)(unsigned int cpu,
+ const psci_power_state_t *state);
+
+ int (*pwr_mcusys_on)(unsigned int cpu, const psci_power_state_t *state);
+ int (*pwr_mcusys_on_finished)(unsigned int cpu,
+ const psci_power_state_t *state);
+ int (*pwr_mcusys_dwn)(unsigned int cpu,
+ const psci_power_state_t *state);
+};
+
+const struct mt_lpm_tz *mt_plat_cpu_pm_init(void);
+
+#endif /* PLAT_MTK_LPM_H */
diff --git a/plat/mediatek/mt8195/include/plat_pm.h b/plat/mediatek/mt8195/include/plat_pm.h
new file mode 100644
index 0000000..a2881ce
--- /dev/null
+++ b/plat/mediatek/mt8195/include/plat_pm.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_PM_H
+#define PLAT_PM_H
+
+#include <lib/utils_def.h>
+
+#define MT_PLAT_PWR_STATE_CPU U(1)
+#define MT_PLAT_PWR_STATE_CLUSTER U(2)
+#define MT_PLAT_PWR_STATE_MCUSYS U(3)
+#define MT_PLAT_PWR_STATE_SUSPEND2IDLE U(8)
+#define MT_PLAT_PWR_STATE_SYSTEM_SUSPEND U(9)
+
+#define MTK_LOCAL_STATE_RUN U(0)
+#define MTK_LOCAL_STATE_RET U(1)
+#define MTK_LOCAL_STATE_OFF U(2)
+
+#define MTK_AFFLVL_CPU U(0)
+#define MTK_AFFLVL_CLUSTER U(1)
+#define MTK_AFFLVL_MCUSYS U(2)
+#define MTK_AFFLVL_SYSTEM U(3)
+
+#define IS_CLUSTER_OFF_STATE(s) \
+ is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_CLUSTER])
+#define IS_MCUSYS_OFF_STATE(s) \
+ is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_MCUSYS])
+#define IS_SYSTEM_SUSPEND_STATE(s) \
+ is_local_state_off(s->pwr_domain_state[MTK_AFFLVL_SYSTEM])
+
+#define IS_PLAT_SUSPEND_ID(stateid)\
+ ((stateid == MT_PLAT_PWR_STATE_SUSPEND2IDLE) \
+ || (stateid == MT_PLAT_PWR_STATE_SYSTEM_SUSPEND))
+
+#endif /* PLAT_PM_H */
diff --git a/plat/mediatek/mt8195/include/plat_private.h b/plat/mediatek/mt8195/include/plat_private.h
new file mode 100644
index 0000000..7ef2b85
--- /dev/null
+++ b/plat/mediatek/mt8195/include/plat_private.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_PRIVATE_H
+#define PLAT_PRIVATE_H
+
+/*******************************************************************************
+ * Function and variable prototypes
+ ******************************************************************************/
+void plat_configure_mmu_el3(uintptr_t total_base,
+ uintptr_t total_size,
+ uintptr_t ro_start,
+ uintptr_t ro_limit);
+
+#endif /* PLAT_PRIVATE_H */
diff --git a/plat/mediatek/mt8195/include/plat_sip_calls.h b/plat/mediatek/mt8195/include/plat_sip_calls.h
new file mode 100644
index 0000000..181aec0
--- /dev/null
+++ b/plat/mediatek/mt8195/include/plat_sip_calls.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_SIP_CALLS_H
+#define PLAT_SIP_CALLS_H
+
+/*******************************************************************************
+ * Plat SiP function constants
+ ******************************************************************************/
+#define MTK_PLAT_SIP_NUM_CALLS 2
+
+/* DP/eDP */
+#define MTK_SIP_DP_CONTROL_AARCH32 0x82000523
+#define MTK_SIP_DP_CONTROL_AARCH64 0xC2000523
+
+#endif /* PLAT_SIP_CALLS_H */
diff --git a/plat/mediatek/mt8195/include/platform_def.h b/plat/mediatek/mt8195/include/platform_def.h
new file mode 100644
index 0000000..b84e73f
--- /dev/null
+++ b/plat/mediatek/mt8195/include/platform_def.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#define PLAT_PRIMARY_CPU 0x0
+
+#define MT_GIC_BASE (0x0C000000)
+#define MCUCFG_BASE (0x0C530000)
+#define IO_PHYS (0x10000000)
+
+/* Aggregate of all devices for MMU mapping */
+#define MTK_DEV_RNG0_BASE IO_PHYS
+#define MTK_DEV_RNG0_SIZE 0x10000000
+#define MTK_DEV_RNG2_BASE MT_GIC_BASE
+#define MTK_DEV_RNG2_SIZE 0x600000
+#define MTK_MCDI_SRAM_BASE 0x11B000
+#define MTK_MCDI_SRAM_MAP_SIZE 0x1000
+
+#define TOPCKGEN_BASE (IO_PHYS + 0x00000000)
+#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
+#define SPM_BASE (IO_PHYS + 0x00006000)
+#define APMIXEDSYS (IO_PHYS + 0x0000C000)
+#define SSPM_MBOX_BASE (IO_PHYS + 0x00480000)
+#define PERICFG_AO_BASE (IO_PHYS + 0x01003000)
+#define VPPSYS0_BASE (IO_PHYS + 0x04000000)
+#define VPPSYS1_BASE (IO_PHYS + 0x04f00000)
+#define VDOSYS0_BASE (IO_PHYS + 0x0C01A000)
+#define VDOSYS1_BASE (IO_PHYS + 0x0C100000)
+
+/*******************************************************************************
+ * DP/eDP related constants
+ ******************************************************************************/
+#define eDP_SEC_BASE (IO_PHYS + 0x0C504000)
+#define DP_SEC_BASE (IO_PHYS + 0x0C604000)
+#define eDP_SEC_SIZE 0x1000
+#define DP_SEC_SIZE 0x1000
+
+/*******************************************************************************
+ * GPIO related constants
+ ******************************************************************************/
+#define GPIO_BASE (IO_PHYS + 0x00005000)
+#define IOCFG_BM_BASE (IO_PHYS + 0x01D10000)
+#define IOCFG_BL_BASE (IO_PHYS + 0x01D30000)
+#define IOCFG_BR_BASE (IO_PHYS + 0x01D40000)
+#define IOCFG_LM_BASE (IO_PHYS + 0x01E20000)
+#define IOCFG_RB_BASE (IO_PHYS + 0x01EB0000)
+#define IOCFG_TL_BASE (IO_PHYS + 0x01F40000)
+
+/*******************************************************************************
+ * UART related constants
+ ******************************************************************************/
+#define UART0_BASE (IO_PHYS + 0x01001100)
+#define UART1_BASE (IO_PHYS + 0x01001200)
+
+#define UART_BAUDRATE 115200
+
+/*******************************************************************************
+ * PMIC related constants
+ ******************************************************************************/
+#define PMIC_WRAP_BASE (IO_PHYS + 0x00024000)
+
+/*******************************************************************************
+ * System counter frequency related constants
+ ******************************************************************************/
+#define SYS_COUNTER_FREQ_IN_TICKS 13000000
+#define SYS_COUNTER_FREQ_IN_MHZ 13
+
+/*******************************************************************************
+ * GIC-600 & interrupt handling related constants
+ ******************************************************************************/
+/* Base MTK_platform compatible GIC memory map */
+#define BASE_GICD_BASE MT_GIC_BASE
+#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
+
+#define SYS_CIRQ_BASE (IO_PHYS + 0x204000)
+#define CIRQ_REG_NUM 23
+#define CIRQ_IRQ_NUM 730
+#define CIRQ_SPI_START 96
+#define MD_WDT_IRQ_BIT_ID 141
+/*******************************************************************************
+ * Platform binary types for linking
+ ******************************************************************************/
+#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH aarch64
+
+/*******************************************************************************
+ * Generic platform constants
+ ******************************************************************************/
+#define PLATFORM_STACK_SIZE 0x800
+
+#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
+
+#define PLAT_MAX_PWR_LVL U(3)
+#define PLAT_MAX_RET_STATE U(1)
+#define PLAT_MAX_OFF_STATE U(9)
+
+#define PLATFORM_SYSTEM_COUNT U(1)
+#define PLATFORM_MCUSYS_COUNT U(1)
+#define PLATFORM_CLUSTER_COUNT U(1)
+#define PLATFORM_CLUSTER0_CORE_COUNT U(8)
+#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
+
+#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
+#define PLATFORM_MAX_CPUS_PER_CLUSTER U(8)
+
+#define SOC_CHIP_ID U(0x8195)
+
+/*******************************************************************************
+ * Platform memory map related constants
+ ******************************************************************************/
+#define TZRAM_BASE 0x54600000
+#define TZRAM_SIZE 0x00030000
+
+/*******************************************************************************
+ * BL31 specific defines.
+ ******************************************************************************/
+/*
+ * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
+ * present). BL31_BASE is calculated using the current BL3-1 debug size plus a
+ * little space for growth.
+ */
+#define BL31_BASE (TZRAM_BASE + 0x1000)
+#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
+
+/*******************************************************************************
+ * Platform specific page table and MMU setup constants
+ ******************************************************************************/
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+#define MAX_XLAT_TABLES 16
+#define MAX_MMAP_REGIONS 16
+
+/*******************************************************************************
+ * Declarations and constants to access the mailboxes safely. Each mailbox is
+ * aligned on the biggest cache line size in the platform. This is known only
+ * to the platform as it might have a combination of integrated and external
+ * caches. Such alignment ensures that two maiboxes do not sit on the same cache
+ * line at any cache level. They could belong to different cpus/clusters &
+ * get written while being protected by different locks causing corruption of
+ * a valid mailbox address.
+ ******************************************************************************/
+#define CACHE_WRITEBACK_SHIFT 6
+#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/mediatek/mt8195/include/rtc.h b/plat/mediatek/mt8195/include/rtc.h
new file mode 100644
index 0000000..a9c7bc8
--- /dev/null
+++ b/plat/mediatek/mt8195/include/rtc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef RTC_H
+#define RTC_H
+
+#include <rtc_mt6359p.h>
+
+#endif /* RTC_H */
diff --git a/plat/mediatek/mt8195/plat_pm.c b/plat/mediatek/mt8195/plat_pm.c
new file mode 100644
index 0000000..2beeb02
--- /dev/null
+++ b/plat/mediatek/mt8195/plat_pm.c
@@ -0,0 +1,400 @@
+/*
+ * Copyright (c) 2021, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* common headers */
+#include <assert.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/gpio.h>
+#include <lib/psci/psci.h>
+
+/* platform specific headers */
+#include <mt_gic_v3.h>
+#include <mtk_ptp3_common.h>
+#include <mtspmc.h>
+#include <plat/common/platform.h>
+#include <plat_mtk_lpm.h>
+#include <plat_params.h>
+#include <plat_pm.h>
+#include <pmic.h>
+#include <rtc.h>
+
+/*
+ * Cluster state request:
+ * [0] : The CPU requires cluster power down
+ * [1] : The CPU requires cluster power on
+ */
+#define coordinate_cluster(onoff) write_clusterpwrdn_el1(onoff)
+#define coordinate_cluster_pwron() coordinate_cluster(1)
+#define coordinate_cluster_pwroff() coordinate_cluster(0)
+
+/* platform secure entry point */
+static uintptr_t secure_entrypoint;
+/* per-CPU power state */
+static unsigned int plat_power_state[PLATFORM_CORE_COUNT];
+
+/* platform CPU power domain - ops */
+static const struct mt_lpm_tz *plat_mt_pm;
+
+#define plat_mt_pm_invoke(_name, _cpu, _state) ({ \
+ int ret = -1; \
+ if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \
+ ret = plat_mt_pm->_name(_cpu, _state); \
+ } \
+ ret; })
+
+#define plat_mt_pm_invoke_no_check(_name, _cpu, _state) ({ \
+ if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \
+ (void) plat_mt_pm->_name(_cpu, _state); \
+ } \
+ })
+
+/*
+ * Common MTK_platform operations to power on/off a
+ * CPU in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
+ */
+
+static void plat_cpu_pwrdwn_common(unsigned int cpu,
+ const psci_power_state_t *state, unsigned int req_pstate)
+{
+ assert(cpu == plat_my_core_pos());
+
+ plat_mt_pm_invoke_no_check(pwr_cpu_dwn, cpu, state);
+
+ if ((psci_get_pstate_pwrlvl(req_pstate) >= MTK_AFFLVL_CLUSTER) ||
+ (req_pstate == 0U)) { /* hotplug off */
+ coordinate_cluster_pwroff();
+ }
+
+ /* Prevent interrupts from spuriously waking up this CPU */
+ mt_gic_rdistif_save();
+ gicv3_cpuif_disable(cpu);
+ gicv3_rdistif_off(cpu);
+}
+
+static void plat_cpu_pwron_common(unsigned int cpu,
+ const psci_power_state_t *state, unsigned int req_pstate)
+{
+ assert(cpu == plat_my_core_pos());
+
+ plat_mt_pm_invoke_no_check(pwr_cpu_on, cpu, state);
+
+ coordinate_cluster_pwron();
+
+ /* PTP3 config */
+ ptp3_core_init(cpu);
+
+ /*
+ * If mcusys does power down before then restore
+ * all CPUs' GIC Redistributors
+ */
+ if (IS_MCUSYS_OFF_STATE(state)) {
+ mt_gic_rdistif_restore_all();
+ } else {
+ gicv3_rdistif_on(cpu);
+ gicv3_cpuif_enable(cpu);
+ mt_gic_rdistif_init();
+ mt_gic_rdistif_restore();
+ }
+}
+
+/*
+ * Common MTK_platform operations to power on/off a
+ * cluster in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
+ */
+
+static void plat_cluster_pwrdwn_common(unsigned int cpu,
+ const psci_power_state_t *state, unsigned int req_pstate)
+{
+ assert(cpu == plat_my_core_pos());
+
+ if (plat_mt_pm_invoke(pwr_cluster_dwn, cpu, state) != 0) {
+ coordinate_cluster_pwron();
+
+ /* TODO: return on fail.
+ * Add a 'return' here before adding any code following
+ * the if-block.
+ */
+ }
+}
+
+static void plat_cluster_pwron_common(unsigned int cpu,
+ const psci_power_state_t *state, unsigned int req_pstate)
+{
+ assert(cpu == plat_my_core_pos());
+
+ if (plat_mt_pm_invoke(pwr_cluster_on, cpu, state) != 0) {
+ /* TODO: return on fail.
+ * Add a 'return' here before adding any code following
+ * the if-block.
+ */
+ }
+}
+
+/*
+ * Common MTK_platform operations to power on/off a
+ * mcusys in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
+ */
+
+static void plat_mcusys_pwrdwn_common(unsigned int cpu,
+ const psci_power_state_t *state, unsigned int req_pstate)
+{
+ assert(cpu == plat_my_core_pos());
+
+ if (plat_mt_pm_invoke(pwr_mcusys_dwn, cpu, state) != 0) {
+ return; /* return on fail */
+ }
+
+ mt_gic_distif_save();
+ gic_sgi_save_all();
+}
+
+static void plat_mcusys_pwron_common(unsigned int cpu,
+ const psci_power_state_t *state, unsigned int req_pstate)
+{
+ assert(cpu == plat_my_core_pos());
+
+ if (plat_mt_pm_invoke(pwr_mcusys_on, cpu, state) != 0) {
+ return; /* return on fail */
+ }
+
+ mt_gic_init();
+ mt_gic_distif_restore();
+ gic_sgi_restore_all();
+
+ plat_mt_pm_invoke_no_check(pwr_mcusys_on_finished, cpu, state);
+}
+
+/*
+ * plat_psci_ops implementation
+ */
+
+static void plat_cpu_standby(plat_local_state_t cpu_state)
+{
+ uint64_t scr;
+
+ scr = read_scr_el3();
+ write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
+
+ isb();
+ dsb();
+ wfi();
+
+ write_scr_el3(scr);
+}
+
+static int plat_power_domain_on(u_register_t mpidr)
+{
+ unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
+ unsigned int cluster = 0U;
+
+ if (cpu >= PLATFORM_CORE_COUNT) {
+ return PSCI_E_INVALID_PARAMS;
+ }
+
+ if (!spm_get_cluster_powerstate(cluster)) {
+ spm_poweron_cluster(cluster);
+ }
+
+ /* init CPU reset arch as AARCH64 */
+ mcucfg_init_archstate(cluster, cpu, true);
+ mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint);
+ spm_poweron_cpu(cluster, cpu);
+
+ return PSCI_E_SUCCESS;
+}
+
+static void plat_power_domain_on_finish(const psci_power_state_t *state)
+{
+ unsigned long mpidr = read_mpidr_el1();
+ unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
+
+ assert(cpu < PLATFORM_CORE_COUNT);
+
+ /* Allow IRQs to wakeup this core in IDLE flow */
+ mcucfg_enable_gic_wakeup(0U, cpu);
+
+ if (IS_CLUSTER_OFF_STATE(state)) {
+ plat_cluster_pwron_common(cpu, state, 0U);
+ }
+
+ plat_cpu_pwron_common(cpu, state, 0U);
+}
+
+static void plat_power_domain_off(const psci_power_state_t *state)
+{
+ unsigned long mpidr = read_mpidr_el1();
+ unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
+
+ assert(cpu < PLATFORM_CORE_COUNT);
+
+ plat_cpu_pwrdwn_common(cpu, state, 0U);
+ spm_poweroff_cpu(0U, cpu);
+
+ /* prevent unintended IRQs from waking up the hot-unplugged core */
+ mcucfg_disable_gic_wakeup(0U, cpu);
+
+ if (IS_CLUSTER_OFF_STATE(state)) {
+ plat_cluster_pwrdwn_common(cpu, state, 0U);
+ }
+}
+
+static void plat_power_domain_suspend(const psci_power_state_t *state)
+{
+ unsigned int cpu = plat_my_core_pos();
+
+ assert(cpu < PLATFORM_CORE_COUNT);
+
+ plat_mt_pm_invoke_no_check(pwr_prompt, cpu, state);
+
+ /* Perform the common CPU specific operations */
+ plat_cpu_pwrdwn_common(cpu, state, plat_power_state[cpu]);
+
+ if (IS_CLUSTER_OFF_STATE(state)) {
+ /* Perform the common cluster specific operations */
+ plat_cluster_pwrdwn_common(cpu, state, plat_power_state[cpu]);
+ }
+
+ if (IS_MCUSYS_OFF_STATE(state)) {
+ /* Perform the common mcusys specific operations */
+ plat_mcusys_pwrdwn_common(cpu, state, plat_power_state[cpu]);
+ }
+}
+
+static void plat_power_domain_suspend_finish(const psci_power_state_t *state)
+{
+ unsigned int cpu = plat_my_core_pos();
+
+ assert(cpu < PLATFORM_CORE_COUNT);
+
+ if (IS_MCUSYS_OFF_STATE(state)) {
+ /* Perform the common mcusys specific operations */
+ plat_mcusys_pwron_common(cpu, state, plat_power_state[cpu]);
+ }
+
+ if (IS_CLUSTER_OFF_STATE(state)) {
+ /* Perform the common cluster specific operations */
+ plat_cluster_pwron_common(cpu, state, plat_power_state[cpu]);
+ }
+
+ /* Perform the common CPU specific operations */
+ plat_cpu_pwron_common(cpu, state, plat_power_state[cpu]);
+
+ plat_mt_pm_invoke_no_check(pwr_reflect, cpu, state);
+}
+
+static int plat_validate_power_state(unsigned int power_state,
+ psci_power_state_t *req_state)
+{
+ unsigned int pstate = psci_get_pstate_type(power_state);
+ unsigned int aff_lvl = psci_get_pstate_pwrlvl(power_state);
+ unsigned int cpu = plat_my_core_pos();
+
+ if (aff_lvl > PLAT_MAX_PWR_LVL) {
+ return PSCI_E_INVALID_PARAMS;
+ }
+
+ if (pstate == PSTATE_TYPE_STANDBY) {
+ req_state->pwr_domain_state[0] = PLAT_MAX_RET_STATE;
+ } else {
+ unsigned int i;
+ unsigned int pstate_id = psci_get_pstate_id(power_state);
+ plat_local_state_t s = MTK_LOCAL_STATE_OFF;
+
+ /* Use pstate_id to be power domain state */
+ if (pstate_id > s) {
+ s = (plat_local_state_t)pstate_id;
+ }
+
+ for (i = 0U; i <= aff_lvl; i++) {
+ req_state->pwr_domain_state[i] = s;
+ }
+ }
+
+ plat_power_state[cpu] = power_state;
+ return PSCI_E_SUCCESS;
+}
+
+static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state)
+{
+ unsigned int lv;
+ unsigned int cpu = plat_my_core_pos();
+
+ for (lv = PSCI_CPU_PWR_LVL; lv <= PLAT_MAX_PWR_LVL; lv++) {
+ req_state->pwr_domain_state[lv] = PLAT_MAX_OFF_STATE;
+ }
+
+ plat_power_state[cpu] =
+ psci_make_powerstate(
+ MT_PLAT_PWR_STATE_SYSTEM_SUSPEND,
+ PSTATE_TYPE_POWERDOWN, PLAT_MAX_PWR_LVL);
+
+ flush_dcache_range((uintptr_t)
+ &plat_power_state[cpu],
+ sizeof(plat_power_state[cpu]));
+}
+
+/*******************************************************************************
+ * MTK handlers to shutdown/reboot the system
+ ******************************************************************************/
+static void __dead2 plat_mtk_system_reset(void)
+{
+ struct bl_aux_gpio_info *gpio_reset = plat_get_mtk_gpio_reset();
+
+ INFO("MTK System Reset\n");
+
+ gpio_set_value(gpio_reset->index, gpio_reset->polarity);
+
+ wfi();
+ ERROR("MTK System Reset: operation not handled.\n");
+ panic();
+}
+
+static void __dead2 plat_mtk_system_off(void)
+{
+ INFO("MTK System Off\n");
+
+ rtc_power_off_sequence();
+ pmic_power_off();
+
+ wfi();
+ ERROR("MTK System Off: operation not handled.\n");
+ panic();
+}
+
+static const plat_psci_ops_t plat_psci_ops = {
+ .system_reset = plat_mtk_system_reset,
+ .system_off = plat_mtk_system_off,
+ .cpu_standby = plat_cpu_standby,
+ .pwr_domain_on = plat_power_domain_on,
+ .pwr_domain_on_finish = plat_power_domain_on_finish,
+ .pwr_domain_off = plat_power_domain_off,
+ .pwr_domain_suspend = plat_power_domain_suspend,
+ .pwr_domain_suspend_finish = plat_power_domain_suspend_finish,
+ .validate_power_state = plat_validate_power_state,
+ .get_sys_suspend_power_state = plat_get_sys_suspend_power_state
+};
+
+int plat_setup_psci_ops(uintptr_t sec_entrypoint,
+ const plat_psci_ops_t **psci_ops)
+{
+ *psci_ops = &plat_psci_ops;
+ secure_entrypoint = sec_entrypoint;
+
+ /*
+ * init the warm reset config for boot CPU
+ * reset arch as AARCH64
+ * reset addr as function bl31_warm_entrypoint()
+ */
+ mcucfg_init_archstate(0U, 0U, true);
+ mcucfg_set_bootaddr(0U, 0U, secure_entrypoint);
+
+ spmc_init();
+ plat_mt_pm = mt_plat_cpu_pm_init();
+
+ return 0;
+}
diff --git a/plat/mediatek/mt8195/plat_sip_calls.c b/plat/mediatek/mt8195/plat_sip_calls.c
new file mode 100644
index 0000000..99e1eb3
--- /dev/null
+++ b/plat/mediatek/mt8195/plat_sip_calls.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <common/runtime_svc.h>
+#include <mt_dp.h>
+#include <mtk_sip_svc.h>
+#include "plat_sip_calls.h"
+
+uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
+ u_register_t x1,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *cookie,
+ void *handle,
+ u_register_t flags)
+{
+ int32_t ret;
+ uint32_t ret_val;
+
+ switch (smc_fid) {
+ case MTK_SIP_DP_CONTROL_AARCH32:
+ case MTK_SIP_DP_CONTROL_AARCH64:
+ ret = dp_secure_handler(x1, x2, &ret_val);
+ SMC_RET2(handle, ret, ret_val);
+ break;
+ default:
+ ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
+ break;
+ }
+
+ SMC_RET1(handle, SMC_UNK);
+}
diff --git a/plat/mediatek/mt8195/plat_topology.c b/plat/mediatek/mt8195/plat_topology.c
new file mode 100644
index 0000000..bc95c64
--- /dev/null
+++ b/plat/mediatek/mt8195/plat_topology.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <lib/psci/psci.h>
+
+#include <plat_helpers.h>
+#include <platform_def.h>
+
+const unsigned char mtk_power_domain_tree_desc[] = {
+ /* Number of root nodes */
+ PLATFORM_SYSTEM_COUNT,
+ /* Number of children for the root node */
+ PLATFORM_MCUSYS_COUNT,
+ /* Number of children for the mcusys node */
+ PLATFORM_CLUSTER_COUNT,
+ /* Number of children for the first cluster node */
+ PLATFORM_CLUSTER0_CORE_COUNT,
+};
+
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+ return mtk_power_domain_tree_desc;
+}
+
+/*******************************************************************************
+ * This function implements a part of the critical interface between the psci
+ * generic layer and the platform that allows the former to query the platform
+ * to convert an MPIDR to a unique linear index. An error code (-1) is returned
+ * in case the MPIDR is invalid.
+ ******************************************************************************/
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+ unsigned int cluster_id, cpu_id;
+
+ if ((read_mpidr() & MPIDR_MT_MASK) != 0) {
+ /* ARMv8.2 arch */
+ if ((mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) != 0) {
+ return -1;
+ }
+ return plat_mediatek_calc_core_pos(mpidr);
+ }
+
+ mpidr &= MPIDR_AFFINITY_MASK;
+
+ if ((mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) != 0) {
+ return -1;
+ }
+
+ cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
+ cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
+
+ if (cluster_id >= PLATFORM_CLUSTER_COUNT) {
+ return -1;
+ }
+
+ /*
+ * Validate cpu_id by checking whether it represents a CPU in
+ * one of the two clusters present on the platform.
+ */
+ if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) {
+ return -1;
+ }
+
+ return (cpu_id + (cluster_id * 8));
+}
diff --git a/plat/mediatek/mt8195/platform.mk b/plat/mediatek/mt8195/platform.mk
new file mode 100644
index 0000000..f4604c4
--- /dev/null
+++ b/plat/mediatek/mt8195/platform.mk
@@ -0,0 +1,93 @@
+#
+# Copyright (c) 2021, MediaTek Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+MTK_PLAT := plat/mediatek
+MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
+
+PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
+ -I${MTK_PLAT}/common/drivers/gic600/ \
+ -I${MTK_PLAT}/common/drivers/gpio/ \
+ -I${MTK_PLAT}/common/drivers/rtc/ \
+ -I${MTK_PLAT}/common/drivers/timer/ \
+ -I${MTK_PLAT}/common/drivers/uart/ \
+ -I${MTK_PLAT}/common/lpm/ \
+ -I${MTK_PLAT_SOC}/drivers/dcm \
+ -I${MTK_PLAT_SOC}/drivers/dp/ \
+ -I${MTK_PLAT_SOC}/drivers/gpio/ \
+ -I${MTK_PLAT_SOC}/drivers/mcdi/ \
+ -I${MTK_PLAT_SOC}/drivers/pmic/ \
+ -I${MTK_PLAT_SOC}/drivers/spmc/ \
+ -I${MTK_PLAT_SOC}/drivers/ptp3/ \
+ -I${MTK_PLAT_SOC}/include/
+
+GICV3_SUPPORT_GIC600 := 1
+include drivers/arm/gic/v3/gicv3.mk
+include lib/xlat_tables_v2/xlat_tables.mk
+
+PLAT_BL_COMMON_SOURCES := ${GICV3_SOURCES} \
+ ${XLAT_TABLES_LIB_SRCS} \
+ plat/common/aarch64/crash_console_helpers.S \
+ plat/common/plat_psci_common.c
+
+
+BL31_SOURCES += common/desc_image_load.c \
+ drivers/delay_timer/delay_timer.c \
+ drivers/gpio/gpio.c \
+ drivers/delay_timer/generic_delay_timer.c \
+ drivers/ti/uart/aarch64/16550_console.S \
+ lib/bl_aux_params/bl_aux_params.c \
+ lib/cpus/aarch64/cortex_a55.S \
+ lib/cpus/aarch64/cortex_a78.S \
+ plat/common/plat_gicv3.c \
+ ${MTK_PLAT}/common/drivers/gic600/mt_gic_v3.c \
+ ${MTK_PLAT}/common/drivers/gpio/mtgpio_common.c \
+ ${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init_v2.c \
+ ${MTK_PLAT}/common/drivers/rtc/rtc_common.c \
+ ${MTK_PLAT}/common/drivers/rtc/rtc_mt6359p.c \
+ ${MTK_PLAT}/common/drivers/timer/mt_timer.c \
+ ${MTK_PLAT}/common/drivers/uart/uart.c \
+ ${MTK_PLAT}/common/lpm/mt_lp_rm.c \
+ ${MTK_PLAT}/common/mtk_cirq.c \
+ ${MTK_PLAT}/common/mtk_plat_common.c \
+ ${MTK_PLAT}/common/mtk_sip_svc.c \
+ ${MTK_PLAT}/common/params_setup.c \
+ ${MTK_PLAT_SOC}/aarch64/platform_common.c \
+ ${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
+ ${MTK_PLAT_SOC}/bl31_plat_setup.c \
+ ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c \
+ ${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c \
+ ${MTK_PLAT_SOC}/drivers/dp/mt_dp.c \
+ ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
+ ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c \
+ ${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c \
+ ${MTK_PLAT_SOC}/drivers/mcdi/mt_mcdi.c \
+ ${MTK_PLAT_SOC}/drivers/mcdi/mt_lp_irqremain.c \
+ ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
+ ${MTK_PLAT_SOC}/drivers/pmic/pmic.c \
+ ${MTK_PLAT_SOC}/drivers/ptp3/mtk_ptp3_main.c \
+ ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \
+ ${MTK_PLAT_SOC}/plat_pm.c \
+ ${MTK_PLAT_SOC}/plat_sip_calls.c \
+ ${MTK_PLAT_SOC}/plat_topology.c
+
+# Build SPM drivers
+include ${MTK_PLAT_SOC}/drivers/spm/build.mk
+
+# Configs for A78 and A55
+HW_ASSISTED_COHERENCY := 1
+USE_COHERENT_MEM := 0
+CTX_INCLUDE_AARCH32_REGS := 0
+ERRATA_A55_1530923 := 1
+
+# indicate the reset vector address can be programmed
+PROGRAMMABLE_RESET_ADDRESS := 1
+
+COLD_BOOT_SINGLE_CPU := 1
+
+MACH_MT8195 := 1
+$(eval $(call add_define,MACH_MT8195))
+
+include lib/coreboot/coreboot.mk
diff --git a/plat/nvidia/tegra/common/tegra_platform.c b/plat/nvidia/tegra/common/tegra_platform.c
index d45d988..f3aa3ea 100644
--- a/plat/nvidia/tegra/common/tegra_platform.c
+++ b/plat/nvidia/tegra/common/tegra_platform.c
@@ -1,6 +1,6 @@
/*
- * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -82,13 +82,6 @@
return (tegra_get_chipid() >> PRE_SI_PLATFORM_SHIFT) & PRE_SI_PLATFORM_MASK;
}
-bool tegra_chipid_is_t132(void)
-{
- uint32_t chip_id = ((tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK);
-
- return (chip_id == TEGRA_CHIPID_TEGRA13);
-}
-
bool tegra_chipid_is_t186(void)
{
uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK;
@@ -280,9 +273,9 @@
int32_t plat_get_soc_version(void)
{
uint32_t chip_id = ((tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK);
- uint32_t manfid = (JEDEC_NVIDIA_BKID << 24) | (JEDEC_NVIDIA_MFID << 16);
+ uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_NVIDIA_BKID, JEDEC_NVIDIA_MFID);
- return (int32_t)(manfid | (chip_id & 0xFFFF));
+ return (int32_t)(manfid | (chip_id & SOC_ID_IMPL_DEF_MASK));
}
/*
@@ -293,7 +286,8 @@
*/
int32_t plat_get_soc_revision(void)
{
- return (int32_t)((tegra_get_chipid_major() << 8) | tegra_get_chipid_minor());
+ return (int32_t)(((tegra_get_chipid_major() << 8) | tegra_get_chipid_minor()) &
+ SOC_ID_REV_MASK);
}
/*****************************************************************************
diff --git a/plat/nvidia/tegra/include/t132/tegra_def.h b/plat/nvidia/tegra/include/t132/tegra_def.h
deleted file mode 100644
index 6b87655..0000000
--- a/plat/nvidia/tegra/include/t132/tegra_def.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef TEGRA_DEF_H
-#define TEGRA_DEF_H
-
-#include <lib/utils_def.h>
-
-/*******************************************************************************
- * Platform BL31 specific defines.
- ******************************************************************************/
-#define BL31_SIZE U(0x40000)
-
-/*******************************************************************************
- * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
- * call as the `state-id` field in the 'power state' parameter.
- ******************************************************************************/
-#define PSTATE_ID_SOC_POWERDN U(0xD)
-
-/*******************************************************************************
- * Platform power states (used by PSCI framework)
- *
- * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
- * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
- ******************************************************************************/
-#define PLAT_MAX_RET_STATE U(1)
-#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
-
-/*******************************************************************************
- * Chip specific page table and MMU setup constants
- ******************************************************************************/
-#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
-
-/*******************************************************************************
- * GIC memory map
- ******************************************************************************/
-#define TEGRA_GICD_BASE U(0x50041000)
-#define TEGRA_GICC_BASE U(0x50042000)
-
-/*******************************************************************************
- * Tegra micro-seconds timer constants
- ******************************************************************************/
-#define TEGRA_TMRUS_BASE U(0x60005010)
-#define TEGRA_TMRUS_SIZE U(0x1000)
-
-/*******************************************************************************
- * Tegra Clock and Reset Controller constants
- ******************************************************************************/
-#define TEGRA_CAR_RESET_BASE U(0x60006000)
-#define TEGRA_GPU_RESET_REG_OFFSET U(0x28C)
-#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290)
-#define GPU_RESET_BIT (U(1) << 24)
-#define GPU_SET_BIT (U(1) << 24)
-
-/*******************************************************************************
- * Tegra Flow Controller constants
- ******************************************************************************/
-#define TEGRA_FLOWCTRL_BASE U(0x60007000)
-
-/*******************************************************************************
- * Tegra Secure Boot Controller constants
- ******************************************************************************/
-#define TEGRA_SB_BASE U(0x6000C200)
-
-/*******************************************************************************
- * Tegra Exception Vectors constants
- ******************************************************************************/
-#define TEGRA_EVP_BASE U(0x6000F000)
-
-/*******************************************************************************
- * Tegra Miscellaneous register constants
- ******************************************************************************/
-#define TEGRA_MISC_BASE U(0x70000000)
-#define HARDWARE_REVISION_OFFSET U(0x804)
-
-/*******************************************************************************
- * Tegra UART controller base addresses
- ******************************************************************************/
-#define TEGRA_UARTA_BASE U(0x70006000)
-#define TEGRA_UARTB_BASE U(0x70006040)
-#define TEGRA_UARTC_BASE U(0x70006200)
-#define TEGRA_UARTD_BASE U(0x70006300)
-#define TEGRA_UARTE_BASE U(0x70006400)
-
-/*******************************************************************************
- * Tegra Power Mgmt Controller constants
- ******************************************************************************/
-#define TEGRA_PMC_BASE U(0x7000E400)
-
-/*******************************************************************************
- * Tegra Memory Controller constants
- ******************************************************************************/
-#define TEGRA_MC_BASE U(0x70019000)
-
-/* Memory Controller Interrupt Status */
-#define MC_INTSTATUS 0x00U
-
-/* TZDRAM carveout configuration registers */
-#define MC_SECURITY_CFG0_0 U(0x70)
-#define MC_SECURITY_CFG1_0 U(0x74)
-#define MC_SECURITY_CFG3_0 U(0x9BC)
-
-/* Video Memory carveout configuration registers */
-#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
-#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
-#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
-#define MC_VIDEO_PROTECT_REG_CTRL U(0x650)
-#define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3)
-
-/*******************************************************************************
- * Tegra TZRAM constants
- ******************************************************************************/
-#define TEGRA_TZRAM_BASE U(0x7C010000)
-#define TEGRA_TZRAM_SIZE U(0x10000)
-
-/*******************************************************************************
- * Tegra DRAM memory base address
- ******************************************************************************/
-#define TEGRA_DRAM_BASE ULL(0x80000000)
-#define TEGRA_DRAM_END ULL(0x27FFFFFFF)
-
-#endif /* TEGRA_DEF_H */
diff --git a/plat/nvidia/tegra/include/tegra_platform.h b/plat/nvidia/tegra/include/tegra_platform.h
index b8297fd..ab51dfe 100644
--- a/plat/nvidia/tegra/include/tegra_platform.h
+++ b/plat/nvidia/tegra/include/tegra_platform.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2020-2021, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -49,7 +49,6 @@
/*
* Tegra chip ID identifiers
*/
-bool tegra_chipid_is_t132(void);
bool tegra_chipid_is_t186(void);
bool tegra_chipid_is_t210(void);
bool tegra_chipid_is_t210_b01(void);
diff --git a/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c
deleted file mode 100644
index 0e2edf0..0000000
--- a/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include <platform_def.h>
-
-#include <arch.h>
-#include <arch_helpers.h>
-#include <common/debug.h>
-#include <drivers/delay_timer.h>
-#include <denver.h>
-#include <lib/mmio.h>
-#include <lib/psci/psci.h>
-
-#include <flowctrl.h>
-#include <pmc.h>
-#include <tegra_def.h>
-#include <tegra_private.h>
-
-/*
- * Register used to clear CPU reset signals. Each CPU has two reset
- * signals: CPU reset (3:0) and Core reset (19:16)
- */
-#define CPU_CMPLX_RESET_CLR 0x344
-#define CPU_CORE_RESET_MASK 0x10001
-
-/* Clock and Reset controller registers for system clock's settings */
-#define SCLK_RATE 0x30
-#define SCLK_BURST_POLICY 0x28
-#define SCLK_BURST_POLICY_DEFAULT 0x10000000
-
-static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
-
-plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
- const plat_local_state_t *states,
- uint32_t ncpu)
-{
- plat_local_state_t target = PLAT_MAX_OFF_STATE, temp;
- uint32_t num_cpu = ncpu;
- const plat_local_state_t *local_state = states;
-
- (void)lvl;
-
- assert(ncpu != 0U);
-
- do {
- temp = *local_state;
- if ((temp < target)) {
- target = temp;
- }
- --num_cpu;
- local_state++;
- } while (num_cpu != 0U);
-
- return target;
-}
-
-int32_t tegra_soc_validate_power_state(unsigned int power_state,
- psci_power_state_t *req_state)
-{
- int state_id = psci_get_pstate_id(power_state);
- int cpu = read_mpidr() & MPIDR_CPU_MASK;
-
- /*
- * Sanity check the requested state id, power level and CPU number.
- * Currently T132 only supports SYSTEM_SUSPEND on last standing CPU
- * i.e. CPU 0
- */
- if ((state_id != PSTATE_ID_SOC_POWERDN) || (cpu != 0)) {
- ERROR("unsupported state id @ power level\n");
- return PSCI_E_INVALID_PARAMS;
- }
-
- /* Set lower power states to PLAT_MAX_OFF_STATE */
- for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
- req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
-
- /* Set the SYSTEM_SUSPEND state-id */
- req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] =
- PSTATE_ID_SOC_POWERDN;
-
- return PSCI_E_SUCCESS;
-}
-
-int tegra_soc_pwr_domain_on(u_register_t mpidr)
-{
- int cpu = mpidr & MPIDR_CPU_MASK;
- uint32_t mask = CPU_CORE_RESET_MASK << cpu;
-
- if (cpu_powergate_mask[cpu] == 0) {
-
- /* Deassert CPU reset signals */
- mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask);
-
- /* Power on CPU using PMC */
- tegra_pmc_cpu_on(cpu);
-
- /* Fill in the CPU powergate mask */
- cpu_powergate_mask[cpu] = 1;
-
- } else {
- /* Power on CPU using Flow Controller */
- tegra_fc_cpu_on(cpu);
- }
-
- return PSCI_E_SUCCESS;
-}
-
-int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
-{
- /*
- * Lock scratch registers which hold the CPU vectors
- */
- tegra_pmc_lock_cpu_vectors();
-
- return PSCI_E_SUCCESS;
-}
-
-int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
-{
- uint64_t val;
-
- tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK);
-
- /* Disable DCO operations */
- denver_disable_dco();
-
- /* Power down the CPU */
- val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
- write_actlr_el1(val | DENVER_CPU_STATE_POWER_DOWN);
-
- return PSCI_E_SUCCESS;
-}
-
-int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state)
-{
- (void)cpu_state;
- return PSCI_E_SUCCESS;
-}
-
-int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
-{
- uint64_t val;
-
-#if ENABLE_ASSERTIONS
- int cpu = read_mpidr() & MPIDR_CPU_MASK;
-
- /* SYSTEM_SUSPEND only on CPU0 */
- assert(cpu == 0);
-#endif
-
- /* Allow restarting CPU #1 using PMC on suspend exit */
- cpu_powergate_mask[1] = 0;
-
- /* Program FC to enter suspend state */
- tegra_fc_cpu_powerdn(read_mpidr());
-
- /* Disable DCO operations */
- denver_disable_dco();
-
- /* Program the suspend state ID */
- val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
- write_actlr_el1(val | target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]);
-
- return PSCI_E_SUCCESS;
-}
-
-int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state)
-{
- return PSCI_E_NOT_SUPPORTED;
-}
-
-int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
-{
- return PSCI_E_SUCCESS;
-}
-
-int tegra_soc_prepare_system_reset(void)
-{
- /*
- * Set System Clock (SCLK) to POR default so that the clock source
- * for the PMC APB clock would not be changed due to system reset.
- */
- mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY,
- SCLK_BURST_POLICY_DEFAULT);
- mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0);
-
- /* Wait 1 ms to make sure clock source/device logic is stabilized. */
- mdelay(1);
-
- /*
- * Program the PMC in order to restart the system.
- */
- tegra_pmc_system_reset();
-
- return PSCI_E_SUCCESS;
-}
-
-__dead2 void tegra_soc_prepare_system_off(void)
-{
- ERROR("Tegra System Off: operation not handled.\n");
- panic();
-}
diff --git a/plat/nvidia/tegra/soc/t132/plat_secondary.c b/plat/nvidia/tegra/soc/t132/plat_secondary.c
deleted file mode 100644
index f46ad3b..0000000
--- a/plat/nvidia/tegra/soc/t132/plat_secondary.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include <arch_helpers.h>
-#include <common/debug.h>
-#include <denver.h>
-#include <lib/mmio.h>
-#include <lib/psci/psci.h>
-#include <plat/common/platform.h>
-
-#include <pmc.h>
-#include <tegra_def.h>
-
-#define SB_CSR 0x0
-#define SB_CSR_NS_RST_VEC_WR_DIS (1 << 1)
-
-/* AARCH64 CPU reset vector */
-#define SB_AA64_RESET_LOW 0x30 /* width = 31:0 */
-#define SB_AA64_RESET_HI 0x34 /* width = 11:0 */
-
-/* AARCH32 CPU reset vector */
-#define EVP_CPU_RESET_VECTOR 0x100
-
-extern void tegra_secure_entrypoint(void);
-
-/*
- * For T132, CPUs reset to AARCH32, so the reset vector is first
- * armv8_trampoline which does a warm reset to AARCH64 and starts
- * execution at the address in SB_AA64_RESET_LOW/SB_AA64_RESET_HI.
- */
-__aligned(8) const uint32_t armv8_trampoline[] = {
- 0xE3A00003, /* mov r0, #3 */
- 0xEE0C0F50, /* mcr p15, 0, r0, c12, c0, 2 */
- 0xEAFFFFFE, /* b . */
-};
-
-/*******************************************************************************
- * Setup secondary CPU vectors
- ******************************************************************************/
-void plat_secondary_setup(void)
-{
- uint32_t val;
- uint64_t reset_addr = (uint64_t)tegra_secure_entrypoint;
-
- /*
- * For T132, CPUs reset to AARCH32, so the reset vector is first
- * armv8_trampoline, which does a warm reset to AARCH64 and starts
- * execution at the address in SCRATCH34/SCRATCH35.
- */
- INFO("Setting up T132 CPU boot\n");
-
- /* initial AARCH32 reset address */
- tegra_pmc_write_32(PMC_SECURE_SCRATCH22,
- (unsigned long)&armv8_trampoline);
-
- /* set AARCH32 exception vector (read to flush) */
- mmio_write_32(TEGRA_EVP_BASE + EVP_CPU_RESET_VECTOR,
- (unsigned long)&armv8_trampoline);
- val = mmio_read_32(TEGRA_EVP_BASE + EVP_CPU_RESET_VECTOR);
-
- /* setup secondary CPU vector */
- mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_LOW,
- (reset_addr & 0xFFFFFFFF) | 1);
- val = reset_addr >> 32;
- mmio_write_32(TEGRA_SB_BASE + SB_AA64_RESET_HI, val & 0x7FF);
-
- /* configure PMC */
- tegra_pmc_cpu_setup(reset_addr);
- tegra_pmc_lock_cpu_vectors();
-}
diff --git a/plat/nvidia/tegra/soc/t132/plat_setup.c b/plat/nvidia/tegra/soc/t132/plat_setup.c
deleted file mode 100644
index 49e8b5d..0000000
--- a/plat/nvidia/tegra/soc/t132/plat_setup.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
- * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch_helpers.h>
-#include <assert.h>
-#include <common/bl_common.h>
-#include <drivers/console.h>
-#include <lib/xlat_tables/xlat_tables_v2.h>
-#include <memctrl.h>
-#include <plat/common/platform.h>
-#include <tegra_def.h>
-#include <tegra_platform.h>
-#include <tegra_private.h>
-
-/* sets of MMIO ranges setup */
-#define MMIO_RANGE_0_ADDR 0x50000000
-#define MMIO_RANGE_1_ADDR 0x60000000
-#define MMIO_RANGE_2_ADDR 0x70000000
-#define MMIO_RANGE_SIZE 0x200000
-
-/*
- * Table of regions to map using the MMU.
- */
-static const mmap_region_t tegra_mmap[] = {
- MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE,
- MT_DEVICE | MT_RW | MT_SECURE),
- MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE,
- MT_DEVICE | MT_RW | MT_SECURE),
- MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE,
- MT_DEVICE | MT_RW | MT_SECURE),
- {0}
-};
-
-/*******************************************************************************
- * Set up the pagetables as per the platform memory map & initialize the MMU
- ******************************************************************************/
-const mmap_region_t *plat_get_mmio_map(void)
-{
- /* MMIO space */
- return tegra_mmap;
-}
-
-/*******************************************************************************
- * The Tegra power domain tree has a single system level power domain i.e. a
- * single root node. The first entry in the power domain descriptor specifies
- * the number of power domains at the highest power level.
- *******************************************************************************
- */
-const unsigned char tegra_power_domain_tree_desc[] = {
- /* No of root nodes */
- 1,
- /* No of clusters */
- PLATFORM_CLUSTER_COUNT,
- /* No of CPU cores */
- PLATFORM_CORE_COUNT,
-};
-
-/*******************************************************************************
- * This function returns the Tegra default topology tree information.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
- return tegra_power_domain_tree_desc;
-}
-
-unsigned int plat_get_syscnt_freq2(void)
-{
- return 12000000;
-}
-
-/*******************************************************************************
- * Maximum supported UART controllers
- ******************************************************************************/
-#define TEGRA132_MAX_UART_PORTS 5
-
-/*******************************************************************************
- * This variable holds the UART port base addresses
- ******************************************************************************/
-static uint32_t tegra132_uart_addresses[TEGRA132_MAX_UART_PORTS + 1] = {
- 0, /* undefined - treated as an error case */
- TEGRA_UARTA_BASE,
- TEGRA_UARTB_BASE,
- TEGRA_UARTC_BASE,
- TEGRA_UARTD_BASE,
- TEGRA_UARTE_BASE,
-};
-
-/*******************************************************************************
- * Enable console corresponding to the console ID
- ******************************************************************************/
-void plat_enable_console(int32_t id)
-{
- static console_t uart_console;
- uint32_t console_clock;
-
- if ((id > 0) && (id < TEGRA132_MAX_UART_PORTS)) {
- /*
- * Reference clock used by the FPGAs is a lot slower.
- */
- if (tegra_platform_is_fpga()) {
- console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
- } else {
- console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
- }
-
- (void)console_16550_register(tegra132_uart_addresses[id],
- console_clock,
- TEGRA_CONSOLE_BAUDRATE,
- &uart_console);
- console_set_scope(&uart_console, CONSOLE_FLAG_BOOT |
- CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
- }
-}
-
-/*******************************************************************************
- * Initialize the GIC and SGIs
- ******************************************************************************/
-void plat_gic_setup(void)
-{
- tegra_gic_setup(NULL, 0);
- tegra_gic_init();
-}
-
-/*******************************************************************************
- * Return pointer to the BL31 params from previous bootloader
- ******************************************************************************/
-struct tegra_bl31_params *plat_get_bl31_params(void)
-{
- return NULL;
-}
-
-/*******************************************************************************
- * Return pointer to the BL31 platform params from previous bootloader
- ******************************************************************************/
-plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
-{
- return NULL;
-}
-
-/*******************************************************************************
- * Handler for early platform setup
- ******************************************************************************/
-void plat_early_platform_setup(void)
-{
- plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
-
- /* Verify chip id is t132 */
- assert(tegra_chipid_is_t132());
-
- /*
- * Do initial security configuration to allow DRAM/device access.
- */
- tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
- (uint32_t)plat_params->tzdram_size);
-}
-
-/*******************************************************************************
- * Handler for late platform setup
- ******************************************************************************/
-void plat_late_platform_setup(void)
-{
- ; /* do nothing */
-}
-
-/*******************************************************************************
- * Handler to indicate support for System Suspend
- ******************************************************************************/
-bool plat_supports_system_suspend(void)
-{
- return true;
-}
-
-/*******************************************************************************
- * Platform specific runtime setup.
- ******************************************************************************/
-void plat_runtime_setup(void)
-{
- /*
- * During cold boot, it is observed that the arbitration
- * bit is set in the Memory controller leading to false
- * error interrupts in the non-secure world. To avoid
- * this, clean the interrupt status register before
- * booting into the non-secure world
- */
- tegra_memctrl_clear_pending_interrupts();
-
- /*
- * During boot, USB3 and flash media (SDMMC/SATA) devices need
- * access to IRAM. Because these clients connect to the MC and
- * do not have a direct path to the IRAM, the MC implements AHB
- * redirection during boot to allow path to IRAM. In this mode
- * accesses to a programmed memory address aperture are directed
- * to the AHB bus, allowing access to the IRAM. This mode must be
- * disabled before we jump to the non-secure world.
- */
- tegra_memctrl_disable_ahb_redirection();
-}
diff --git a/plat/nvidia/tegra/soc/t132/plat_sip_calls.c b/plat/nvidia/tegra/soc/t132/plat_sip_calls.c
deleted file mode 100644
index 90c6bb2..0000000
--- a/plat/nvidia/tegra/soc/t132/plat_sip_calls.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <errno.h>
-
-#include <arch.h>
-#include <arch_helpers.h>
-#include <common/bl_common.h>
-#include <common/debug.h>
-#include <lib/el3_runtime/context_mgmt.h>
-
-#include <tegra_private.h>
-
-#define NS_SWITCH_AARCH32 1
-#define SCR_RW_BITPOS __builtin_ctz(SCR_RW_BIT)
-
-/*******************************************************************************
- * Tegra132 SiP SMCs
- ******************************************************************************/
-#define TEGRA_SIP_AARCH_SWITCH 0x82000004
-
-/*******************************************************************************
- * SPSR settings for AARCH32/AARCH64 modes
- ******************************************************************************/
-#define SPSR32 SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE, \
- DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT)
-#define SPSR64 SPSR_64(MODE_EL2, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS)
-
-/*******************************************************************************
- * This function is responsible for handling all T132 SiP calls
- ******************************************************************************/
-int plat_sip_handler(uint32_t smc_fid,
- uint64_t x1,
- uint64_t x2,
- uint64_t x3,
- uint64_t x4,
- const void *cookie,
- void *handle,
- uint64_t flags)
-{
- switch (smc_fid) {
-
- case TEGRA_SIP_AARCH_SWITCH:
-
- /* clean up the high bits */
- x1 = (uint32_t)x1;
- x2 = (uint32_t)x2;
-
- if (!x1 || x2 > NS_SWITCH_AARCH32) {
- ERROR("%s: invalid parameters\n", __func__);
- return -EINVAL;
- }
-
- /* x1 = ns entry point */
- cm_set_elr_spsr_el3(NON_SECURE, x1,
- (x2 == NS_SWITCH_AARCH32) ? SPSR32 : SPSR64);
-
- /* switch NS world mode */
- cm_write_scr_el3_bit(NON_SECURE, SCR_RW_BITPOS, !x2);
-
- INFO("CPU switched to AARCH%s mode\n",
- (x2 == NS_SWITCH_AARCH32) ? "32" : "64");
- return 0;
-
- default:
- ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
- break;
- }
-
- return -ENOTSUP;
-}
diff --git a/plat/nvidia/tegra/soc/t132/platform_t132.mk b/plat/nvidia/tegra/soc/t132/platform_t132.mk
deleted file mode 100644
index 9534c07..0000000
--- a/plat/nvidia/tegra/soc/t132/platform_t132.mk
+++ /dev/null
@@ -1,35 +0,0 @@
-#
-# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
-# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-TZDRAM_BASE := 0xF5C00000
-$(eval $(call add_define,TZDRAM_BASE))
-
-PLATFORM_CLUSTER_COUNT := 1
-$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
-
-PLATFORM_MAX_CPUS_PER_CLUSTER := 2
-$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
-
-MAX_XLAT_TABLES := 3
-$(eval $(call add_define,MAX_XLAT_TABLES))
-
-MAX_MMAP_REGIONS := 8
-$(eval $(call add_define,MAX_MMAP_REGIONS))
-
-# platform files
-PLAT_INCLUDES += -Iplat/nvidia/tegra/include/t132
-
-BL31_SOURCES += ${TEGRA_GICv2_SOURCES} \
- drivers/ti/uart/aarch64/16550_console.S \
- lib/cpus/aarch64/denver.S \
- ${TEGRA_DRIVERS}/flowctrl/flowctrl.c \
- ${TEGRA_DRIVERS}/memctrl/memctrl_v1.c \
- ${TEGRA_DRIVERS}/pmc/pmc.c \
- ${SOC_DIR}/plat_psci_handlers.c \
- ${SOC_DIR}/plat_sip_calls.c \
- ${SOC_DIR}/plat_setup.c \
- ${SOC_DIR}/plat_secondary.c
diff --git a/plat/nvidia/tegra/soc/t194/plat_ras.c b/plat/nvidia/tegra/soc/t194/plat_ras.c
index 0c4c6fa..a322403 100644
--- a/plat/nvidia/tegra/soc/t194/plat_ras.c
+++ b/plat/nvidia/tegra/soc/t194/plat_ras.c
@@ -493,9 +493,6 @@
#if RAS_EXTENSION
tegra194_ea_handler(ea_reason, syndrome, cookie, handle, flags);
#else
- ERROR("Unhandled External Abort received on 0x%llx at EL3!\n",
- read_mpidr_el1());
- ERROR(" exception reason=%u syndrome=0x%lx\n", ea_reason, syndrome);
- panic();
+ plat_default_ea_handler(ea_reason, syndrome, cookie, handle, flags);
#endif
}
diff --git a/plat/nxp/common/aarch64/bl31_data.S b/plat/nxp/common/aarch64/bl31_data.S
new file mode 100644
index 0000000..cc91540
--- /dev/null
+++ b/plat/nxp/common/aarch64/bl31_data.S
@@ -0,0 +1,558 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <asm_macros.S>
+
+#include "bl31_data.h"
+#include "plat_psci.h"
+#include "platform_def.h"
+
+.global _getCoreData
+.global _setCoreData
+.global _getCoreState
+.global _setCoreState
+.global _init_global_data
+.global _get_global_data
+.global _set_global_data
+.global _initialize_psci
+.global _init_task_flags
+.global _set_task1_start
+.global _set_task1_done
+
+
+/* Function returns the specified data field value from the specified cpu
+ * core data area
+ * in: x0 = core mask lsb
+ * x1 = data field name/offset
+ * out: x0 = data value
+ * uses x0, x1, x2, [x13, x14, x15]
+ */
+func _getCoreData
+
+ /* generate a 0-based core number from the input mask */
+ clz x2, x0
+ mov x0, #63
+ sub x0, x0, x2
+
+ /* x0 = core number (0-based) */
+ /* x1 = field offset */
+
+ /* determine if this is bootcore or secondary core */
+ cbnz x0, 1f
+
+ /* get base address for bootcore data */
+ ldr x2, =BC_PSCI_BASE
+ add x2, x2, x1
+ b 2f
+
+1: /* get base address for secondary core data */
+
+ /* x0 = core number (0-based) */
+ /* x1 = field offset */
+
+ /* generate number of regions to offset */
+ mov x2, #SEC_REGION_SIZE
+ mul x2, x2, x0
+
+ /* x1 = field offset */
+ /* x2 = region offset */
+
+ /* generate the total offset to data element */
+ sub x1, x2, x1
+
+ /* x1 = total offset to data element */
+
+ /* get the base address */
+ ldr x2, =SECONDARY_TOP
+
+ /* apply offset to base addr */
+ sub x2, x2, x1
+2:
+ /* x2 = data element address */
+
+ dc ivac, x2
+ dsb sy
+ isb
+ /* read data */
+ ldr x0, [x2]
+
+ ret
+endfunc _getCoreData
+
+
+/* Function returns the SoC-specific state of the specified cpu
+ * in: x0 = core mask lsb
+ * out: x0 = data value
+ * uses x0, x1, x2, [x13, x14, x15]
+ */
+func _getCoreState
+
+ mov x1, #CORE_STATE_DATA
+
+ /* generate a 0-based core number from the input mask */
+ clz x2, x0
+ mov x0, #63
+ sub x0, x0, x2
+
+ /* x0 = core number (0-based) */
+ /* x1 = field offset */
+
+ /* determine if this is bootcore or secondary core */
+ cbnz x0, 1f
+
+ /* get base address for bootcore data */
+ ldr x2, =BC_PSCI_BASE
+ add x2, x2, x1
+ b 2f
+
+1: /* get base address for secondary core data */
+
+ /* x0 = core number (0-based) */
+ /* x1 = field offset */
+
+ /* generate number of regions to offset */
+ mov x2, #SEC_REGION_SIZE
+ mul x2, x2, x0
+
+ /* x1 = field offset */
+ /* x2 = region offset */
+
+ /* generate the total offset to data element */
+ sub x1, x2, x1
+
+ /* x1 = total offset to data element */
+
+ /* get the base address */
+ ldr x2, =SECONDARY_TOP
+
+ /* apply offset to base addr */
+ sub x2, x2, x1
+2:
+ /* x2 = data element address */
+
+ dc ivac, x2
+ dsb sy
+ isb
+
+ /* read data */
+ ldr x0, [x2]
+
+ ret
+endfunc _getCoreState
+
+
+/* Function writes the specified data value into the specified cpu
+ * core data area
+ * in: x0 = core mask lsb
+ * x1 = data field offset
+ * x2 = data value to write/store
+ * out: none
+ * uses x0, x1, x2, x3, [x13, x14, x15]
+ */
+func _setCoreData
+ /* x0 = core mask */
+ /* x1 = field offset */
+ /* x2 = data value */
+
+ clz x3, x0
+ mov x0, #63
+ sub x0, x0, x3
+
+ /* x0 = core number (0-based) */
+ /* x1 = field offset */
+ /* x2 = data value */
+
+ /* determine if this is bootcore or secondary core */
+ cbnz x0, 1f
+
+ /* get base address for bootcore data */
+ ldr x3, =BC_PSCI_BASE
+ add x3, x3, x1
+ b 2f
+
+1: /* get base address for secondary core data */
+
+ /* x0 = core number (0-based) */
+ /* x1 = field offset */
+ /* x2 = data value */
+
+ /* generate number of regions to offset */
+ mov x3, #SEC_REGION_SIZE
+ mul x3, x3, x0
+
+ /* x1 = field offset */
+ /* x2 = data value */
+ /* x3 = region offset */
+
+ /* generate the total offset to data element */
+ sub x1, x3, x1
+
+ /* x1 = total offset to data element */
+ /* x2 = data value */
+
+ ldr x3, =SECONDARY_TOP
+
+ /* apply offset to base addr */
+ sub x3, x3, x1
+
+2:
+ /* x2 = data value */
+ /* x3 = data element address */
+
+ str x2, [x3]
+
+ dc cvac, x3
+ dsb sy
+ isb
+ ret
+endfunc _setCoreData
+
+
+/* Function stores the specified core state
+ * in: x0 = core mask lsb
+ * x1 = data value to write/store
+ * out: none
+ * uses x0, x1, x2, x3, [x13, x14, x15]
+ */
+func _setCoreState
+ mov x2, #CORE_STATE_DATA
+
+ clz x3, x0
+ mov x0, #63
+ sub x0, x0, x3
+
+ /* x0 = core number (0-based) */
+ /* x1 = data value */
+ /* x2 = field offset */
+
+ /* determine if this is bootcore or secondary core */
+ cbnz x0, 1f
+
+ /* get base address for bootcore data */
+ ldr x3, =BC_PSCI_BASE
+ add x3, x3, x2
+ b 2f
+
+1: /* get base address for secondary core data */
+
+ /* x0 = core number (0-based) */
+ /* x1 = data value */
+ /* x2 = field offset */
+
+ /* generate number of regions to offset */
+ mov x3, #SEC_REGION_SIZE
+ mul x3, x3, x0
+
+ /* x1 = data value */
+ /* x2 = field offset */
+ /* x3 = region offset */
+
+ /* generate the total offset to data element */
+ sub x2, x3, x2
+
+ /* x1 = data value */
+ /* x2 = total offset to data element */
+
+ ldr x3, =SECONDARY_TOP
+
+ /* apply offset to base addr */
+ sub x3, x3, x2
+
+2:
+ /* x1 = data value */
+ /* x3 = data element address */
+
+ str x1, [x3]
+
+ dc civac, x3
+ dsb sy
+ isb
+ ret
+endfunc _setCoreState
+
+
+/* Function sets the task1 start
+ * in: w0 = value to set flag to
+ * out: none
+ * uses x0, x1
+ */
+func _set_task1_start
+
+ ldr x1, =SMC_TASK1_BASE
+
+ add x1, x1, #TSK_START_OFFSET
+ str w0, [x1]
+ dc cvac, x1
+ dsb sy
+ isb
+ ret
+endfunc _set_task1_start
+
+
+/* Function sets the state of the task 1 done flag
+ * in: w0 = value to set flag to
+ * out: none
+ * uses x0, x1
+ */
+func _set_task1_done
+
+ ldr x1, =SMC_TASK1_BASE
+
+ add x1, x1, #TSK_DONE_OFFSET
+ str w0, [x1]
+ dc cvac, x1
+ dsb sy
+ isb
+ ret
+endfunc _set_task1_done
+
+
+/* Function initializes the smc global data entries
+ * Note: the constant LAST_SMC_GLBL_OFFSET must reference the last entry in the
+ * smc global region
+ * in: none
+ * out: none
+ * uses x0, x1, x2
+ */
+func _init_global_data
+
+ ldr x1, =SMC_GLBL_BASE
+
+ /* x1 = SMC_GLBL_BASE */
+
+ mov x2, #LAST_SMC_GLBL_OFFSET
+ add x2, x2, x1
+1:
+ str xzr, [x1]
+ dc cvac, x1
+ cmp x2, x1
+ add x1, x1, #8
+ b.hi 1b
+
+ dsb sy
+ isb
+ ret
+endfunc _init_global_data
+
+
+/* Function gets the value of the specified global data element
+ * in: x0 = offset of data element
+ * out: x0 = requested data element
+ * uses x0, x1
+ */
+func _get_global_data
+
+ ldr x1, =SMC_GLBL_BASE
+ add x1, x1, x0
+ dc ivac, x1
+ isb
+
+ ldr x0, [x1]
+ ret
+endfunc _get_global_data
+
+
+/* Function sets the value of the specified global data element
+ * in: x0 = offset of data element
+ * x1 = value to write
+ * out: none
+ * uses x0, x1, x2
+ */
+func _set_global_data
+
+ ldr x2, =SMC_GLBL_BASE
+ add x0, x0, x2
+ str x1, [x0]
+ dc cvac, x0
+
+ dsb sy
+ isb
+ ret
+endfunc _set_global_data
+
+
+/* Function initializes the core data areas
+ * only executed by the boot core
+ * in: none
+ * out: none
+ * uses: x0, x1, x2, x3, x4, x5, x6, x7, [x13, x14, x15]
+ */
+func _initialize_psci
+ mov x7, x30
+
+ /* initialize the bootcore psci data */
+ ldr x5, =BC_PSCI_BASE
+ mov x6, #CORE_RELEASED
+
+ str x6, [x5], #8
+ dc cvac, x5
+ str xzr, [x5], #8
+ dc cvac, x5
+ str xzr, [x5], #8
+ dc cvac, x5
+ str xzr, [x5], #8
+ dc cvac, x5
+ str xzr, [x5], #8
+ dc cvac, x5
+ str xzr, [x5], #8
+ dc cvac, x5
+ str xzr, [x5], #8
+ dc cvac, x5
+ str xzr, [x5], #8
+ dc cvac, x5
+ str xzr, [x5], #8
+ dc cvac, x5
+ str xzr, [x5], #8
+ dc cvac, x5
+ str xzr, [x5], #8
+ dc cvac, x5
+ str xzr, [x5], #8
+ dc cvac, x5
+ str xzr, [x5], #8
+ dc cvac, x5
+ str xzr, [x5], #8
+ dc cvac, x5
+ str xzr, [x5], #8
+ dc cvac, x5
+ str xzr, [x5]
+ dc cvac, x5
+ dsb sy
+ isb
+
+ /* see if we have any secondary cores */
+ mov x4, #PLATFORM_CORE_COUNT
+ sub x4, x4, #1
+ cbz x4, 3f
+
+ /* initialize the secondary core's psci data */
+ ldr x5, =SECONDARY_TOP
+ /* core mask lsb for core 1 */
+ mov x3, #2
+ sub x5, x5, #SEC_REGION_SIZE
+
+ /* x3 = core1 mask lsb */
+ /* x4 = number of secondary cores */
+ /* x5 = core1 psci data base address */
+2:
+ /* set core state in x6 */
+ mov x0, x3
+ mov x6, #CORE_IN_RESET
+ bl _soc_ck_disabled
+ cbz x0, 1f
+ mov x6, #CORE_DISABLED
+1:
+ add x2, x5, #CORE_STATE_DATA
+ str x6, [x2]
+ dc cvac, x2
+ add x2, x5, #SPSR_EL3_DATA
+ str xzr, [x2]
+ dc cvac, x2
+ add x2, x5, #CNTXT_ID_DATA
+ str xzr, [x2]
+ dc cvac, x2
+ add x2, x5, #START_ADDR_DATA
+ str xzr, [x2]
+ dc cvac, x2
+ add x2, x5, #LINK_REG_DATA
+ str xzr, [x2]
+ dc cvac, x2
+ add x2, x5, #GICC_CTLR_DATA
+ str xzr, [x2]
+ dc cvac, x2
+ add x2, x5, #ABORT_FLAG_DATA
+ str xzr, [x2]
+ dc cvac, x2
+ add x2, x5, #SCTLR_DATA
+ str xzr, [x2]
+ dc cvac, x2
+ add x2, x5, #CPUECTLR_DATA
+ str xzr, [x2]
+ dc cvac, x2
+ add x2, x5, #AUX_01_DATA
+ str xzr, [x2]
+ dc cvac, x2
+ add x2, x5, #AUX_02_DATA
+ str xzr, [x2]
+ dc cvac, x2
+ add x2, x5, #AUX_03_DATA
+ str xzr, [x2]
+ dc cvac, x2
+ add x2, x5, #AUX_04_DATA
+ str xzr, [x2]
+ dc cvac, x2
+ add x2, x5, #AUX_05_DATA
+ str xzr, [x2]
+ dc cvac, x2
+ add x2, x5, #SCR_EL3_DATA
+ str xzr, [x2]
+ dc cvac, x2
+ add x2, x5, #HCR_EL2_DATA
+ str xzr, [x2]
+ dc cvac, x2
+ dsb sy
+ isb
+
+ sub x4, x4, #1
+ cbz x4, 3f
+
+ /* generate next core mask */
+ lsl x3, x3, #1
+
+ /* decrement base address to next data area */
+ sub x5, x5, #SEC_REGION_SIZE
+ b 2b
+3:
+ mov x30, x7
+ ret
+endfunc _initialize_psci
+
+
+/* Function initializes the soc init task flags
+ * in: none
+ * out: none
+ * uses x0, x1, [x13, x14, x15]
+ */
+func _init_task_flags
+
+ /* get the base address of the first task structure */
+ ldr x0, =SMC_TASK1_BASE
+
+ /* x0 = task1 base address */
+
+ str wzr, [x0, #TSK_START_OFFSET]
+ str wzr, [x0, #TSK_DONE_OFFSET]
+ str wzr, [x0, #TSK_CORE_OFFSET]
+ dc cvac, x0
+
+ /* move to task2 structure */
+ add x0, x0, #SMC_TASK_OFFSET
+
+ str wzr, [x0, #TSK_START_OFFSET]
+ str wzr, [x0, #TSK_DONE_OFFSET]
+ str wzr, [x0, #TSK_CORE_OFFSET]
+ dc cvac, x0
+
+ /* move to task3 structure */
+ add x0, x0, #SMC_TASK_OFFSET
+
+ str wzr, [x0, #TSK_START_OFFSET]
+ str wzr, [x0, #TSK_DONE_OFFSET]
+ str wzr, [x0, #TSK_CORE_OFFSET]
+ dc cvac, x0
+
+ /* move to task4 structure */
+ add x0, x0, #SMC_TASK_OFFSET
+
+ str wzr, [x0, #TSK_START_OFFSET]
+ str wzr, [x0, #TSK_DONE_OFFSET]
+ str wzr, [x0, #TSK_CORE_OFFSET]
+ dc cvac, x0
+
+ dsb sy
+ isb
+ ret
+endfunc _init_task_flags
diff --git a/plat/nxp/common/aarch64/ls_helpers.S b/plat/nxp/common/aarch64/ls_helpers.S
new file mode 100644
index 0000000..19ea9e5
--- /dev/null
+++ b/plat/nxp/common/aarch64/ls_helpers.S
@@ -0,0 +1,194 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <asm_macros.S>
+#include <drivers/console.h>
+#include <lib/cpus/aarch64/cortex_a72.h>
+
+#include <platform_def.h>
+
+
+ .globl plat_crash_console_init
+ .globl plat_crash_console_putc
+ .globl plat_crash_console_flush
+ .globl plat_core_pos
+ .globl plat_my_core_pos
+ .globl plat_core_mask
+ .globl plat_my_core_mask
+ .globl plat_core_pos_by_mpidr
+ .globl _disable_ldstr_pfetch_A53
+ .globl _disable_ldstr_pfetch_A72
+ .global _set_smmu_pagesz_64
+
+ /* int plat_crash_console_init(void)
+ * Function to initialize the crash console
+ * without a C Runtime to print crash report.
+ * Clobber list : x0 - x4
+ */
+
+ /* int plat_crash_console_init(void)
+ * Use normal console by default. Switch it to crash
+ * mode so serial consoles become active again.
+ * NOTE: This default implementation will only work for
+ * crashes that occur after a normal console (marked
+ * valid for the crash state) has been registered with
+ * the console framework. To debug crashes that occur
+ * earlier, the platform has to override these functions
+ * with an implementation that initializes a console
+ * driver with hardcoded parameters. See
+ * docs/porting-guide.rst for more information.
+ */
+func plat_crash_console_init
+ mov x3, x30
+ mov x0, #CONSOLE_FLAG_CRASH
+ bl console_switch_state
+ mov x0, #1
+ ret x3
+endfunc plat_crash_console_init
+
+ /* void plat_crash_console_putc(int character)
+ * Output through the normal console by default.
+ */
+func plat_crash_console_putc
+ b console_putc
+endfunc plat_crash_console_putc
+
+ /* void plat_crash_console_flush(void)
+ * Flush normal console by default.
+ */
+func plat_crash_console_flush
+ b console_flush
+endfunc plat_crash_console_flush
+
+/* This function implements a part of the critical interface between the psci
+ * generic layer and the platform that allows the former to query the platform
+ * to convert an MPIDR to a unique linear index. An error code (-1) is returned
+ * in case the MPIDR is invalid.
+ */
+func plat_core_pos_by_mpidr
+
+ b plat_core_pos
+
+endfunc plat_core_pos_by_mpidr
+
+#if (SYMMETRICAL_CLUSTERS)
+/* unsigned int plat_my_core_mask(void)
+ * generate a mask bit for this core
+ */
+func plat_my_core_mask
+ mrs x0, MPIDR_EL1
+ b plat_core_mask
+endfunc plat_my_core_mask
+
+/* unsigned int plat_core_mask(u_register_t mpidr)
+ * generate a lsb-based mask bit for the core specified by mpidr in x0.
+ *
+ * SoC core = ((cluster * cpu_per_cluster) + core)
+ * mask = (1 << SoC core)
+ */
+func plat_core_mask
+ mov w1, wzr
+ mov w2, wzr
+
+ /* extract cluster */
+ bfxil w1, w0, #8, #8
+ /* extract cpu # */
+ bfxil w2, w0, #0, #8
+
+ mov w0, wzr
+
+ /* error checking */
+ cmp w1, #NUMBER_OF_CLUSTERS
+ b.ge 1f
+ cmp w2, #CORES_PER_CLUSTER
+ b.ge 1f
+
+ mov w0, #CORES_PER_CLUSTER
+ mul w1, w1, w0
+ add w1, w1, w2
+ mov w2, #0x1
+ lsl w0, w2, w1
+1:
+ ret
+endfunc plat_core_mask
+
+/*
+ * unsigned int plat_my_core_pos(void)
+ * generate a linear core number for this core
+ */
+func plat_my_core_pos
+ mrs x0, MPIDR_EL1
+ b plat_core_pos
+endfunc plat_my_core_pos
+
+/*
+ * unsigned int plat_core_pos(u_register_t mpidr)
+ * Generate a linear core number for the core specified by mpidr.
+ *
+ * SoC core = ((cluster * cpu_per_cluster) + core)
+ * Returns -1 if mpidr invalid
+ */
+func plat_core_pos
+ mov w1, wzr
+ mov w2, wzr
+ bfxil w1, w0, #8, #8 /* extract cluster */
+ bfxil w2, w0, #0, #8 /* extract cpu # */
+
+ mov w0, #-1
+
+ /* error checking */
+ cmp w1, #NUMBER_OF_CLUSTERS
+ b.ge 1f
+ cmp w2, #CORES_PER_CLUSTER
+ b.ge 1f
+
+ mov w0, #CORES_PER_CLUSTER
+ mul w1, w1, w0
+ add w0, w1, w2
+1:
+ ret
+endfunc plat_core_pos
+
+#endif
+
+/* this function disables the load-store prefetch of the calling core
+ * Note: this function is for A72 cores ONLY
+ * in: none
+ * out: none
+ * uses x0
+ */
+func _disable_ldstr_pfetch_A72
+
+ mrs x0, CORTEX_A72_CPUACTLR_EL1
+ tst x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
+ b.eq 1f
+ b 2f
+
+.align 6
+1:
+ dsb sy
+ isb
+ orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
+ msr CORTEX_A72_CPUACTLR_EL1, x0
+ isb
+
+2:
+ ret
+endfunc _disable_ldstr_pfetch_A72
+
+/*
+ * Function sets the SACR pagesize to 64k
+ */
+func _set_smmu_pagesz_64
+
+ ldr x1, =NXP_SMMU_ADDR
+ ldr w0, [x1, #0x10]
+ orr w0, w0, #1 << 16 /* setting to 64K page */
+ str w0, [x1, #0x10]
+
+ ret
+endfunc _set_smmu_pagesz_64
diff --git a/plat/nxp/common/fip_handler/common/plat_def_fip_uuid.h b/plat/nxp/common/fip_handler/common/plat_def_fip_uuid.h
new file mode 100644
index 0000000..65aef14
--- /dev/null
+++ b/plat/nxp/common/fip_handler/common/plat_def_fip_uuid.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PLAT_DEF_FIP_UUID_H
+#define PLAT_DEF_FIP_UUID_H
+
+/* PHy images configs */
+#define UUID_DDR_IMEM_UDIMM_1D \
+ {{0x5b, 0xdb, 0xe3, 0x83}, {0xd1, 0x9f}, {0xc7, 0x06}, 0xd4, 0x91, {0x76, 0x4f, 0x9d, 0x23, 0x2d, 0x2d} }
+
+#define UUID_DDR_IMEM_UDIMM_2D \
+ {{0xfa, 0x0e, 0xeb, 0x21}, {0xe0, 0x7f}, {0x8e, 0x65}, 0x95, 0xd8, {0x2b, 0x94, 0xf6, 0xb8, 0x28, 0x0a} }
+
+#define UUID_DDR_DMEM_UDIMM_1D \
+ {{0xba, 0xbb, 0xfd, 0x7e}, {0x5b, 0xf0}, {0xeb, 0xb8}, 0xeb, 0x71, {0xb1, 0x85, 0x07, 0xdd, 0xe1, 0x32} }
+
+#define UUID_DDR_DMEM_UDIMM_2D \
+ {{0xb6, 0x99, 0x61, 0xda}, {0xf9, 0x92}, {0x4b, 0x9e}, 0x0c, 0x49, {0x74, 0xa5, 0xe0, 0x5c, 0xbe, 0xc3} }
+
+#define UUID_DDR_IMEM_RDIMM_1D \
+ {{0x42, 0x33, 0x66, 0x52}, {0xd8, 0x94}, {0x4d, 0xc1}, 0x91, 0xcc, {0x26, 0x8f, 0x7a, 0x67, 0xf1, 0xa2} }
+
+#define UUID_DDR_IMEM_RDIMM_2D \
+ {{0x2e, 0x95, 0x73, 0xba}, {0xb5, 0xca}, {0x7c, 0xc7}, 0xef, 0xc9, {0x5e, 0xb0, 0x42, 0xec, 0x08, 0x7a} }
+
+#define UUID_DDR_DMEM_RDIMM_1D \
+ {{0x1c, 0x51, 0x17, 0xed}, {0x30, 0x0d}, {0xae, 0xba}, 0x87, 0x03, {0x1f, 0x37, 0x85, 0xec, 0xe1, 0x44} }
+
+#define UUID_DDR_DMEM_RDIMM_2D \
+ {{0xe9, 0x0a, 0x90, 0x78}, {0x11, 0xd6}, {0x8b, 0xba}, 0x24, 0x35, {0xec, 0x10, 0x75, 0x4f, 0x56, 0xa5} }
+
+#define UUID_DDR_FW_KEY_CERT \
+ {{0xac, 0x4b, 0xb8, 0x9c}, {0x8f, 0xb9}, {0x11, 0xea}, 0xbc, 0x55, {0x02, 0x42, 0xac, 0x12, 0x00, 0x03} }
+
+#define UUID_DDR_UDIMM_FW_CONTENT_CERT \
+ {{0x2c, 0x7f, 0x52, 0x54}, {0x70, 0x92}, {0x48, 0x40}, 0x8c, 0x34, {0x87, 0x4b, 0xbf, 0xbd, 0x9d, 0x89} }
+
+#define UUID_DDR_RDIMM_FW_CONTENT_CERT \
+ {{0x94, 0xc3, 0x63, 0x30}, {0x7c, 0xf7}, {0x4f, 0x1d}, 0xaa, 0xcd, {0xb5, 0x80, 0xb2, 0xc2, 0x40, 0xa5} }
+
+#define UUID_FUSE_PROV \
+ {{0xec, 0x45, 0x90, 0x42}, {0x30, 0x0d}, {0xae, 0xba}, 0x87, 0x03, {0x1f, 0x37, 0x85, 0xec, 0xe1, 0x44} }
+
+#define UUID_FUSE_UP \
+ {{0x89, 0x46, 0xef, 0x78}, {0x11, 0xd6}, {0x8b, 0xba}, 0x24, 0x35, {0xec, 0x10, 0x75, 0x4f, 0x56, 0xa5} }
+
+#endif /* PLAT_DEF_FIP_UUID_H */
diff --git a/plat/nxp/common/fip_handler/common/plat_tbbr_img_def.h b/plat/nxp/common/fip_handler/common/plat_tbbr_img_def.h
new file mode 100644
index 0000000..9856f70
--- /dev/null
+++ b/plat/nxp/common/fip_handler/common/plat_tbbr_img_def.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef NXP_IMG_DEF_H
+#define NXP_IMG_DEF_H
+
+#include <export/common/tbbr/tbbr_img_def_exp.h>
+
+#ifdef CONFIG_DDR_FIP_IMAGE
+/* DDR FIP IMAGE ID */
+#define DDR_FIP_IMAGE_ID MAX_IMG_IDS_WITH_SPMDS
+
+#define DDR_IMEM_UDIMM_1D_IMAGE_ID MAX_IMG_IDS_WITH_SPMDS + 1
+#define DDR_IMEM_UDIMM_2D_IMAGE_ID MAX_IMG_IDS_WITH_SPMDS + 2
+
+#define DDR_DMEM_UDIMM_1D_IMAGE_ID MAX_IMG_IDS_WITH_SPMDS + 3
+#define DDR_DMEM_UDIMM_2D_IMAGE_ID MAX_IMG_IDS_WITH_SPMDS + 4
+
+#define DDR_IMEM_RDIMM_1D_IMAGE_ID MAX_IMG_IDS_WITH_SPMDS + 5
+#define DDR_IMEM_RDIMM_2D_IMAGE_ID MAX_IMG_IDS_WITH_SPMDS + 6
+
+#define DDR_DMEM_RDIMM_1D_IMAGE_ID MAX_IMG_IDS_WITH_SPMDS + 7
+#define DDR_DMEM_RDIMM_2D_IMAGE_ID MAX_IMG_IDS_WITH_SPMDS + 8
+
+#define DDR_FW_KEY_CERT_ID MAX_IMG_IDS_WITH_SPMDS + 9
+#define DDR_UDIMM_FW_CONTENT_CERT_ID MAX_IMG_IDS_WITH_SPMDS + 10
+#define DDR_RDIMM_FW_CONTENT_CERT_ID MAX_IMG_IDS_WITH_SPMDS + 11
+/* Max Images */
+#define MAX_IMG_WITH_DDR_IDS MAX_IMG_IDS_WITH_SPMDS + 12
+#else
+#define MAX_IMG_WITH_DDR_IDS MAX_IMG_IDS_WITH_SPMDS
+#endif
+
+#ifdef POLICY_FUSE_PROVISION
+/* FUSE FIP IMAGE ID */
+#define FUSE_FIP_IMAGE_ID MAX_IMG_WITH_DDR_IDS
+
+#define FUSE_PROV_IMAGE_ID MAX_IMG_WITH_DDR_IDS + 1
+
+#define FUSE_UP_IMAGE_ID MAX_IMG_WITH_DDR_IDS + 2
+
+#define MAX_IMG_WITH_FIMG_IDS MAX_IMG_WITH_DDR_IDS + 3
+#else
+#define MAX_IMG_WITH_FIMG_IDS MAX_IMG_WITH_DDR_IDS
+#endif
+
+#define MAX_NUMBER_IDS MAX_IMG_WITH_FIMG_IDS
+
+#endif /* NXP_IMG_DEF_H */
diff --git a/plat/nxp/common/fip_handler/common/platform_oid.h b/plat/nxp/common/fip_handler/common/platform_oid.h
new file mode 100644
index 0000000..bbd6041
--- /dev/null
+++ b/plat/nxp/common/fip_handler/common/platform_oid.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#define DDR_FW_CONTENT_CERT_PK_OID "1.3.6.1.4.1.4128.2200.1"
+#define DDR_IMEM_UDIMM_1D_HASH_OID "1.3.6.1.4.1.4128.2200.2"
+#define DDR_IMEM_UDIMM_2D_HASH_OID "1.3.6.1.4.1.4128.2200.3"
+#define DDR_DMEM_UDIMM_1D_HASH_OID "1.3.6.1.4.1.4128.2200.4"
+#define DDR_DMEM_UDIMM_2D_HASH_OID "1.3.6.1.4.1.4128.2200.5"
+#define DDR_IMEM_RDIMM_1D_HASH_OID "1.3.6.1.4.1.4128.2200.6"
+#define DDR_IMEM_RDIMM_2D_HASH_OID "1.3.6.1.4.1.4128.2200.7"
+#define DDR_DMEM_RDIMM_1D_HASH_OID "1.3.6.1.4.1.4128.2200.8"
+#define DDR_DMEM_RDIMM_2D_HASH_OID "1.3.6.1.4.1.4128.2200.9"
diff --git a/plat/nxp/common/fip_handler/ddr_fip/ddr_fip_io.mk b/plat/nxp/common/fip_handler/ddr_fip/ddr_fip_io.mk
new file mode 100644
index 0000000..7d673ba
--- /dev/null
+++ b/plat/nxp/common/fip_handler/ddr_fip/ddr_fip_io.mk
@@ -0,0 +1,38 @@
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-----------------------------------------------------------------------------
+ifeq (${DDR_FIP_IO_STORAGE_ADDED},)
+
+$(eval $(call add_define, PLAT_DEF_FIP_UUID))
+$(eval $(call add_define, PLAT_TBBR_IMG_DEF))
+$(eval $(call SET_NXP_MAKE_FLAG,IMG_LOADR_NEEDED,BL2))
+
+DDR_FIP_IO_STORAGE_ADDED := 1
+$(eval $(call add_define,CONFIG_DDR_FIP_IMAGE))
+
+FIP_HANDLER_PATH := ${PLAT_COMMON_PATH}/fip_handler
+FIP_HANDLER_COMMON_PATH := ${FIP_HANDLER_PATH}/common
+DDR_FIP_IO_STORAGE_PATH := ${FIP_HANDLER_PATH}/ddr_fip
+
+PLAT_INCLUDES += -I${FIP_HANDLER_COMMON_PATH}\
+ -I$(DDR_FIP_IO_STORAGE_PATH)
+
+DDR_FIP_IO_SOURCES += $(DDR_FIP_IO_STORAGE_PATH)/ddr_io_storage.c
+
+$(shell cp tools/nxp/plat_fiptool/plat_fiptool.mk ${PLAT_DIR})
+
+ifeq (${BL_COMM_DDR_FIP_IO_NEEDED},yes)
+BL_COMMON_SOURCES += ${DDR_FIP_IO_SOURCES}
+else
+ifeq (${BL2_DDR_FIP_IO_NEEDED},yes)
+BL2_SOURCES += ${DDR_FIP_IO_SOURCES}
+endif
+ifeq (${BL31_DDR_FIP_IO_NEEDED},yes)
+BL31_SOURCES += ${DDR_FIP_IO_SOURCES}
+endif
+endif
+endif
+#------------------------------------------------
diff --git a/plat/nxp/common/fip_handler/ddr_fip/ddr_io_storage.c b/plat/nxp/common/fip_handler/ddr_fip/ddr_io_storage.c
new file mode 100644
index 0000000..fc3c4a4
--- /dev/null
+++ b/plat/nxp/common/fip_handler/ddr_fip/ddr_io_storage.c
@@ -0,0 +1,232 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <assert.h>
+#include <string.h>
+
+#include <io_block.h>
+#include <io_driver.h>
+#include <io_fip.h>
+#include <io_memmap.h>
+#include <io_storage.h>
+#include <lib/utils.h>
+#include <tools_share/firmware_image_package.h>
+#include "ddr_io_storage.h"
+#include "plat_common.h"
+#include "platform_def.h"
+
+
+/* TBD - Move these defined to the platform_def.h file.
+ * Keeping them for reference here
+ */
+extern uintptr_t backend_dev_handle;
+
+static uint32_t ddr_fip;
+
+static uintptr_t ddr_fip_dev_handle;
+
+static io_block_spec_t ddr_fip_block_spec = {
+ .offset = PLAT_DDR_FIP_OFFSET,
+ .length = PLAT_DDR_FIP_MAX_SIZE
+};
+
+static const io_uuid_spec_t ddr_imem_udimm_1d_uuid_spec = {
+ .uuid = UUID_DDR_IMEM_UDIMM_1D,
+};
+
+static const io_uuid_spec_t ddr_imem_udimm_2d_uuid_spec = {
+ .uuid = UUID_DDR_IMEM_UDIMM_2D,
+};
+
+static const io_uuid_spec_t ddr_dmem_udimm_1d_uuid_spec = {
+ .uuid = UUID_DDR_DMEM_UDIMM_1D,
+};
+
+static const io_uuid_spec_t ddr_dmem_udimm_2d_uuid_spec = {
+ .uuid = UUID_DDR_DMEM_UDIMM_2D,
+};
+
+static const io_uuid_spec_t ddr_imem_rdimm_1d_uuid_spec = {
+ .uuid = UUID_DDR_IMEM_RDIMM_1D,
+};
+
+static const io_uuid_spec_t ddr_imem_rdimm_2d_uuid_spec = {
+ .uuid = UUID_DDR_IMEM_RDIMM_2D,
+};
+
+static const io_uuid_spec_t ddr_dmem_rdimm_1d_uuid_spec = {
+ .uuid = UUID_DDR_DMEM_RDIMM_1D,
+};
+
+static const io_uuid_spec_t ddr_dmem_rdimm_2d_uuid_spec = {
+ .uuid = UUID_DDR_DMEM_RDIMM_2D,
+};
+
+#if TRUSTED_BOARD_BOOT
+static const io_uuid_spec_t ddr_fw_key_cert_uuid_spec = {
+ .uuid = UUID_DDR_FW_KEY_CERT,
+};
+static const io_uuid_spec_t ddr_udimm_fw_cert_uuid_spec = {
+ .uuid = UUID_DDR_UDIMM_FW_CONTENT_CERT,
+};
+static const io_uuid_spec_t ddr_rdimm_fw_cert_uuid_spec = {
+ .uuid = UUID_DDR_RDIMM_FW_CONTENT_CERT,
+};
+#endif
+
+static int open_ddr_fip(const uintptr_t spec);
+
+struct plat_io_policy {
+ uintptr_t *dev_handle;
+ uintptr_t image_spec;
+ int (*check)(const uintptr_t spec);
+};
+
+/* By default, ARM platforms load images from the FIP */
+static const struct plat_io_policy ddr_policies[] = {
+ [DDR_FIP_IMAGE_ID - DDR_FIP_IMAGE_ID] = {
+ &backend_dev_handle,
+ (uintptr_t)&ddr_fip_block_spec,
+ NULL
+ },
+ [DDR_IMEM_UDIMM_1D_IMAGE_ID - DDR_FIP_IMAGE_ID] = {
+ &ddr_fip_dev_handle,
+ (uintptr_t)&ddr_imem_udimm_1d_uuid_spec,
+ open_ddr_fip
+ },
+ [DDR_IMEM_UDIMM_2D_IMAGE_ID - DDR_FIP_IMAGE_ID] = {
+ &ddr_fip_dev_handle,
+ (uintptr_t)&ddr_imem_udimm_2d_uuid_spec,
+ open_ddr_fip
+ },
+ [DDR_DMEM_UDIMM_1D_IMAGE_ID - DDR_FIP_IMAGE_ID] = {
+ &ddr_fip_dev_handle,
+ (uintptr_t)&ddr_dmem_udimm_1d_uuid_spec,
+ open_ddr_fip
+ },
+ [DDR_DMEM_UDIMM_2D_IMAGE_ID - DDR_FIP_IMAGE_ID] = {
+ &ddr_fip_dev_handle,
+ (uintptr_t)&ddr_dmem_udimm_2d_uuid_spec,
+ open_ddr_fip
+ },
+ [DDR_IMEM_RDIMM_1D_IMAGE_ID - DDR_FIP_IMAGE_ID] = {
+ &ddr_fip_dev_handle,
+ (uintptr_t)&ddr_imem_rdimm_1d_uuid_spec,
+ open_ddr_fip
+ },
+ [DDR_IMEM_RDIMM_2D_IMAGE_ID - DDR_FIP_IMAGE_ID] = {
+ &ddr_fip_dev_handle,
+ (uintptr_t)&ddr_imem_rdimm_2d_uuid_spec,
+ open_ddr_fip
+ },
+ [DDR_DMEM_RDIMM_1D_IMAGE_ID - DDR_FIP_IMAGE_ID] = {
+ &ddr_fip_dev_handle,
+ (uintptr_t)&ddr_dmem_rdimm_1d_uuid_spec,
+ open_ddr_fip
+ },
+ [DDR_DMEM_RDIMM_2D_IMAGE_ID - DDR_FIP_IMAGE_ID] = {
+ &ddr_fip_dev_handle,
+ (uintptr_t)&ddr_dmem_rdimm_2d_uuid_spec,
+ open_ddr_fip
+ },
+#if TRUSTED_BOARD_BOOT
+ [DDR_FW_KEY_CERT_ID - DDR_FIP_IMAGE_ID] = {
+ &ddr_fip_dev_handle,
+ (uintptr_t)&ddr_fw_key_cert_uuid_spec,
+ open_ddr_fip
+ },
+ [DDR_UDIMM_FW_CONTENT_CERT_ID - DDR_FIP_IMAGE_ID] = {
+ &ddr_fip_dev_handle,
+ (uintptr_t)&ddr_udimm_fw_cert_uuid_spec,
+ open_ddr_fip
+ },
+ [DDR_RDIMM_FW_CONTENT_CERT_ID - DDR_FIP_IMAGE_ID] = {
+ &ddr_fip_dev_handle,
+ (uintptr_t)&ddr_rdimm_fw_cert_uuid_spec,
+ open_ddr_fip
+ },
+#endif
+};
+
+static int open_ddr_fip(const uintptr_t spec)
+{
+ int result;
+ uintptr_t local_image_handle;
+
+ /* See if a Firmware Image Package is available */
+ result = io_dev_init(ddr_fip_dev_handle, (uintptr_t)DDR_FIP_IMAGE_ID);
+ if (result == 0) {
+ result = io_open(ddr_fip_dev_handle, spec, &local_image_handle);
+ if (result == 0) {
+ VERBOSE("Using FIP\n");
+ io_close(local_image_handle);
+ }
+ }
+ return result;
+}
+
+/* The image can be one of the DDR PHY images, which can be sleected via DDR
+ * policies
+ */
+int plat_get_ddr_fip_image_source(unsigned int image_id, uintptr_t *dev_handle,
+ uintptr_t *image_spec,
+ int (*check)(const uintptr_t spec))
+{
+ int result = -1;
+ const struct plat_io_policy *policy;
+
+ if (image_id >= (DDR_FIP_IMAGE_ID + ARRAY_SIZE(ddr_policies))) {
+ return result;
+ }
+
+ policy = &ddr_policies[image_id - DDR_FIP_IMAGE_ID];
+ if (image_id == DDR_FIP_IMAGE_ID) {
+ result = check(policy->image_spec);
+ } else {
+ result = policy->check(policy->image_spec);
+ }
+ if (result == 0) {
+ *image_spec = policy->image_spec;
+ *dev_handle = *(policy->dev_handle);
+ }
+ return result;
+}
+
+int ddr_fip_setup(const io_dev_connector_t *fip_dev_con, unsigned int boot_dev)
+{
+ int io_result;
+ size_t ddr_fip_offset = PLAT_DDR_FIP_OFFSET;
+
+ /* Open connections to ddr fip and cache the handles */
+ io_result = io_dev_open(fip_dev_con, (uintptr_t)&ddr_fip,
+ &ddr_fip_dev_handle);
+ assert(io_result == 0);
+
+ switch (boot_dev) {
+#if QSPI_BOOT
+ case BOOT_DEVICE_QSPI:
+ ddr_fip_offset += NXP_QSPI_FLASH_ADDR;
+ break;
+#endif
+#if NOR_BOOT
+ case BOOT_DEVICE_IFC_NOR:
+ ddr_fip_offset += NXP_NOR_FLASH_ADDR;
+ break;
+#endif
+#if FLEXSPI_NOR_BOOT
+ case BOOT_DEVICE_FLEXSPI_NOR:
+ ddr_fip_offset += NXP_FLEXSPI_FLASH_ADDR;
+ break;
+#endif
+ default:
+ break;
+ }
+
+ ddr_fip_block_spec.offset = ddr_fip_offset;
+
+ return io_result;
+}
diff --git a/plat/nxp/common/fip_handler/ddr_fip/ddr_io_storage.h b/plat/nxp/common/fip_handler/ddr_fip/ddr_io_storage.h
new file mode 100644
index 0000000..6df3902
--- /dev/null
+++ b/plat/nxp/common/fip_handler/ddr_fip/ddr_io_storage.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef DDR_IO_STORAGE_H
+#define DDR_IO_STORAGE_H
+
+#include <drivers/io/io_driver.h>
+
+#ifndef PLAT_DDR_FIP_OFFSET
+#define PLAT_DDR_FIP_OFFSET 0x800000
+#endif
+
+#ifndef PLAT_DDR_FIP_MAX_SIZE
+#define PLAT_DDR_FIP_MAX_SIZE 0x32000
+#endif
+
+int ddr_fip_setup(const io_dev_connector_t *fip_dev_con, unsigned int boot_dev);
+int plat_get_ddr_fip_image_source(unsigned int image_id, uintptr_t *dev_handle,
+ uintptr_t *image_spec,
+ int (*check)(const uintptr_t spec));
+
+#endif /* DDR_IO_STORAGE_H */
diff --git a/plat/nxp/common/fip_handler/fuse_fip/fuse.mk b/plat/nxp/common/fip_handler/fuse_fip/fuse.mk
new file mode 100644
index 0000000..d8f5ae6
--- /dev/null
+++ b/plat/nxp/common/fip_handler/fuse_fip/fuse.mk
@@ -0,0 +1,100 @@
+#
+# Copyright 2018-2020 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+
+NEED_FUSE := yes
+
+$(eval $(call add_define, PLAT_DEF_FIP_UUID))
+$(eval $(call add_define, POLICY_FUSE_PROVISION))
+$(eval $(call add_define, PLAT_TBBR_IMG_DEF))
+
+$(eval $(call SET_NXP_MAKE_FLAG,IMG_LOADR_NEEDED,BL2))
+$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
+$(eval $(call SET_NXP_MAKE_FLAG,GPIO_NEEDED,BL2))
+
+FIP_HANDLER_PATH := ${PLAT_COMMON_PATH}/fip_handler
+FIP_HANDLER_COMMON_PATH := ${FIP_HANDLER_PATH}/common
+
+FUSE_SOURCES := ${FIP_HANDLER_PATH}/fuse_fip/fuse_io_storage.c
+
+PLAT_INCLUDES += -I${FIP_HANDLER_COMMON_PATH}\
+ -I${FIP_HANDLER_PATH}/fuse_fip
+
+FUSE_FIP_NAME := fuse_fip.bin
+
+fip_fuse: ${BUILD_PLAT}/${FUSE_FIP_NAME}
+
+ifeq (${FUSE_PROV_FILE},)
+
+$(shell cp tools/nxp/plat_fiptool/plat_fiptool.mk ${PLAT_DIR})
+
+else
+ifeq (${TRUSTED_BOARD_BOOT},1)
+FUSE_PROV_FILE_SB = $(notdir ${FUSE_PROV_FILE})_prov.sb
+FUSE_FIP_ARGS += --fuse-prov ${BUILD_PLAT}/${FUSE_PROV_FILE_SB}
+FUSE_FIP_DEPS += ${BUILD_PLAT}/${FUSE_PROV_FILE_SB}
+else
+FUSE_FIP_ARGS += --fuse-prov ${FUSE_PROV_FILE}
+FUSE_FIP_DEPS += ${FUSE_PROV_FILE}
+endif
+endif
+
+ifeq (${FUSE_UP_FILE},)
+else
+ifeq (${TRUSTED_BOARD_BOOT},1)
+FUSE_UP_FILE_SB = $(notdir ${FUSE_UP_FILE})_up.sb
+FUSE_FIP_ARGS += --fuse-up ${BUILD_PLAT}/${FUSE_UP_FILE_SB}
+FUSE_FIP_DEPS += ${BUILD_PLAT}/${FUSE_UP_FILE_SB}
+else
+FUSE_FIP_ARGS += --fuse-up ${FUSE_UP_FILE}
+FUSE_FIP_DEPS += ${FUSE_UP_FILE}
+endif
+endif
+
+ifeq (${TRUSTED_BOARD_BOOT},1)
+
+ifeq (${MBEDTLS_DIR},)
+else
+ $(error Error: Trusted Board Boot with X509 certificates not supported with FUSE_PROG build option)
+endif
+
+# Path to CST directory is required to generate the CSF header
+# and prepend it to image before fip image gets generated
+ifeq (${CST_DIR},)
+ $(error Error: CST_DIR not set)
+endif
+
+ifeq (${FUSE_INPUT_FILE},)
+FUSE_INPUT_FILE := $(PLAT_DRIVERS_PATH)/auth/csf_hdr_parser/${CSF_FILE}
+endif
+
+ifeq (${FUSE_PROV_FILE},)
+else
+${BUILD_PLAT}/${FUSE_PROV_FILE_SB}: ${FUSE_PROV_FILE}
+ @echo " Generating CSF Header for $@ $<"
+ $(CST_DIR)/create_hdr_esbc --in $< --out $@ --app_off ${CSF_HDR_SZ} \
+ --app $< ${FUSE_INPUT_FILE}
+endif
+
+ifeq (${FUSE_UP_FILE},)
+else
+${BUILD_PLAT}/${FUSE_UP_FILE_SB}: ${FUSE_UP_FILE}
+ @echo " Generating CSF Header for $@ $<"
+ $(CST_DIR)/create_hdr_esbc --in $< --out $@ --app_off ${CSF_HDR_SZ} \
+ --app $< ${FUSE_INPUT_FILE}
+endif
+
+endif
+
+${BUILD_PLAT}/${FUSE_FIP_NAME}: fiptool ${FUSE_FIP_DEPS}
+ifeq (${FUSE_FIP_DEPS},)
+ $(error "Error: FUSE_PROV_FILE or/and FUSE_UP_FILE needs to point to the right file")
+endif
+ ${FIPTOOL} create ${FUSE_FIP_ARGS} $@
+ ${FIPTOOL} info $@
+ @${ECHO_BLANK_LINE}
+ @echo "Built $@ successfully"
+ @${ECHO_BLANK_LINE}
diff --git a/plat/nxp/common/fip_handler/fuse_fip/fuse_io.h b/plat/nxp/common/fip_handler/fuse_fip/fuse_io.h
new file mode 100644
index 0000000..e8775d0
--- /dev/null
+++ b/plat/nxp/common/fip_handler/fuse_fip/fuse_io.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+#ifndef FUSE_IO_H
+#define FUSE_IO_H
+
+#include <drivers/io/io_driver.h>
+
+/* Can be overridden from platform_def.h file.
+ */
+#ifndef PLAT_FUSE_FIP_OFFSET
+#define PLAT_FUSE_FIP_OFFSET 0x880000
+#endif
+#ifndef PLAT_FUSE_FIP_MAX_SIZE
+#define PLAT_FUSE_FIP_MAX_SIZE 0x80000
+#endif
+
+int fip_fuse_provisioning(uintptr_t image_buf, uint32_t size);
+int fuse_fip_setup(const io_dev_connector_t *fip_dev_con, unsigned int boot_dev);
+int plat_get_fuse_image_source(unsigned int image_id,
+ uintptr_t *dev_handle,
+ uintptr_t *image_spec,
+ int (*check)(const uintptr_t spec));
+#endif /* FUSE_IO_H */
diff --git a/plat/nxp/common/fip_handler/fuse_fip/fuse_io_storage.c b/plat/nxp/common/fip_handler/fuse_fip/fuse_io_storage.c
new file mode 100644
index 0000000..017ffcf
--- /dev/null
+++ b/plat/nxp/common/fip_handler/fuse_fip/fuse_io_storage.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <assert.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <dcfg.h>
+#include <drivers/delay_timer.h>
+#include <fuse_prov.h>
+#include <io_block.h>
+#include <io_driver.h>
+#include <io_fip.h>
+#include <io_memmap.h>
+#include <io_storage.h>
+#include <lib/utils.h>
+#include <nxp_gpio.h>
+#include <sfp.h>
+#include <sfp_error_codes.h>
+#include <tools_share/firmware_image_package.h>
+
+#include "fuse_io.h"
+#include <load_img.h>
+#include <plat/common/platform.h>
+#include "plat_common.h"
+#include "platform_def.h"
+
+extern uintptr_t backend_dev_handle;
+
+static uint32_t fuse_fip;
+
+static uintptr_t fuse_fip_dev_handle;
+
+static io_block_spec_t fuse_fip_block_spec = {
+ .offset = PLAT_FUSE_FIP_OFFSET,
+ .length = PLAT_FUSE_FIP_MAX_SIZE
+};
+
+static const io_uuid_spec_t fuse_prov_uuid_spec = {
+ .uuid = UUID_FUSE_PROV,
+};
+
+static const io_uuid_spec_t fuse_up_uuid_spec = {
+ .uuid = UUID_FUSE_UP,
+};
+
+static int open_fuse_fip(const uintptr_t spec);
+
+struct plat_io_policy {
+ uintptr_t *dev_handle;
+ uintptr_t image_spec;
+ int (*check)(const uintptr_t spec);
+};
+
+/* By default, ARM platforms load images from the FIP */
+static const struct plat_io_policy fuse_policies[] = {
+ [FUSE_FIP_IMAGE_ID - FUSE_FIP_IMAGE_ID] = {
+ &backend_dev_handle,
+ (uintptr_t)&fuse_fip_block_spec,
+ NULL
+ },
+ [FUSE_PROV_IMAGE_ID - FUSE_FIP_IMAGE_ID] = {
+ &fuse_fip_dev_handle,
+ (uintptr_t)&fuse_prov_uuid_spec,
+ open_fuse_fip
+ },
+ [FUSE_UP_IMAGE_ID - FUSE_FIP_IMAGE_ID] = {
+ &fuse_fip_dev_handle,
+ (uintptr_t)&fuse_up_uuid_spec,
+ open_fuse_fip
+ }
+};
+
+static int open_fuse_fip(const uintptr_t spec)
+{
+ int result;
+ uintptr_t local_image_handle;
+
+ /* See if a Firmware Image Package is available */
+ result = io_dev_init(fuse_fip_dev_handle, (uintptr_t)FUSE_FIP_IMAGE_ID);
+ if (result == 0) {
+ result = io_open(fuse_fip_dev_handle,
+ spec,
+ &local_image_handle);
+ if (result == 0) {
+ VERBOSE("Using FIP\n");
+ io_close(local_image_handle);
+ }
+ }
+ return result;
+}
+
+/* The image can be one of the DDR PHY images, which can be sleected via DDR
+ * policies
+ */
+int plat_get_fuse_image_source(unsigned int image_id,
+ uintptr_t *dev_handle,
+ uintptr_t *image_spec,
+ int (*check)(const uintptr_t spec))
+{
+ int result;
+ const struct plat_io_policy *policy;
+
+ assert(image_id < (FUSE_FIP_IMAGE_ID + ARRAY_SIZE(fuse_policies)));
+
+ policy = &fuse_policies[image_id - FUSE_FIP_IMAGE_ID];
+
+ if (image_id == FUSE_FIP_IMAGE_ID) {
+ result = check(policy->image_spec);
+ } else {
+ result = policy->check(policy->image_spec);
+ }
+
+ if (result == 0) {
+ *image_spec = policy->image_spec;
+ *dev_handle = *(policy->dev_handle);
+ }
+ return result;
+}
+
+int fuse_fip_setup(const io_dev_connector_t *fip_dev_con, unsigned int boot_dev)
+{
+ int io_result;
+ size_t fuse_fip_offset = PLAT_FUSE_FIP_OFFSET;
+
+ /* Open connections to fuse fip and cache the handles */
+ io_result = io_dev_open(fip_dev_con, (uintptr_t)&fuse_fip,
+ &fuse_fip_dev_handle);
+
+ assert(io_result == 0);
+
+ switch (boot_dev) {
+#if QSPI_BOOT
+ case BOOT_DEVICE_QSPI:
+ fuse_fip_offset += NXP_QSPI_FLASH_ADDR;
+ break;
+#endif
+#if NOR_BOOT
+ case BOOT_DEVICE_IFC_NOR:
+ fuse_fip_offset += NXP_NOR_FLASH_ADDR;
+ break;
+#endif
+#if FLEXSPI_NOR_BOOT
+ case BOOT_DEVICE_FLEXSPI_NOR:
+ fuse_fip_offset += NXP_FLEXSPI_FLASH_ADDR;
+ break;
+#endif
+ default:
+ break;
+ }
+
+ fuse_fip_block_spec.offset = fuse_fip_offset;
+
+ return io_result;
+}
+
+int fip_fuse_provisioning(uintptr_t image_buf, uint32_t size)
+{
+ uint32_t bit_num;
+ uint32_t *gpio_base_addr = NULL;
+ struct fuse_hdr_t *fuse_hdr = NULL;
+ uint8_t barker[] = {0x68U, 0x39U, 0x27U, 0x81U};
+ int ret = -1;
+
+ if (sfp_check_oem_wp() == 0) {
+ ret = load_img(FUSE_PROV_IMAGE_ID, &image_buf, &size);
+ if (ret != 0) {
+ ERROR("Failed to load FUSE PRIV image\n");
+ assert(ret == 0);
+ }
+ fuse_hdr = (struct fuse_hdr_t *)image_buf;
+
+ /* Check barker code */
+ if (memcmp(fuse_hdr->barker, barker, sizeof(barker)) != 0) {
+ ERROR("FUSE Barker code mismatch.\n");
+ error_handler(ERROR_FUSE_BARKER);
+ return 1;
+ }
+
+ /* Check if GPIO pin to be set for POVDD */
+ if (((fuse_hdr->flags >> FLAG_POVDD_SHIFT) & 0x1) != 0) {
+ gpio_base_addr =
+ select_gpio_n_bitnum(fuse_hdr->povdd_gpio,
+ &bit_num);
+ /*
+ * Add delay so that Efuse gets the power
+ * when GPIO is enabled.
+ */
+ ret = set_gpio_bit(gpio_base_addr, bit_num);
+ mdelay(EFUSE_POWERUP_DELAY_mSec);
+ } else {
+ ret = (board_enable_povdd() == true) ? 0 : PLAT_ERROR_ENABLE_POVDD;
+ }
+ if (ret != 0) {
+ ERROR("Error enabling board POVDD: %d\n", ret);
+ ERROR("Only SFP mirror register will be set.\n");
+ }
+
+ provision_fuses(image_buf, ret == 0);
+
+ /* Check if GPIO pin to be reset for POVDD */
+ if (((fuse_hdr->flags >> FLAG_POVDD_SHIFT) & 0x1) != 0) {
+ if (gpio_base_addr == NULL) {
+ gpio_base_addr =
+ select_gpio_n_bitnum(
+ fuse_hdr->povdd_gpio,
+ &bit_num);
+ }
+ ret = clr_gpio_bit(gpio_base_addr, bit_num);
+ } else {
+ ret = board_disable_povdd() ? 0 : PLAT_ERROR_DISABLE_POVDD;
+ }
+
+ if (ret != 0) {
+ ERROR("Error disabling board POVDD: %d\n", ret);
+ }
+ }
+ return 0;
+}
diff --git a/plat/nxp/common/img_loadr/img_loadr.mk b/plat/nxp/common/img_loadr/img_loadr.mk
new file mode 100644
index 0000000..f64b1fa
--- /dev/null
+++ b/plat/nxp/common/img_loadr/img_loadr.mk
@@ -0,0 +1,21 @@
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+IMG_LOADR_DRIVERS_PATH := ${PLAT_COMMON_PATH}/img_loadr
+
+IMG_LOADR_SOURCES := $(IMG_LOADR_DRIVERS_PATH)/load_img.c
+PLAT_INCLUDES += -I$(IMG_LOADR_DRIVERS_PATH)
+
+ifeq (${BL_COMM_IMG_LOADR_NEEDED},yes)
+BL_COMMON_SOURCES += ${IMG_LOADR_SOURCES}
+else
+ifeq (${BL2_IMG_LOADR_NEEDED},yes)
+BL2_SOURCES += ${IMG_LOADR_SOURCES}
+endif
+ifeq (${BL31_IMG_LOADR_NEEDED},yes)
+BL31_SOURCES += ${IMG_LOADR_SOURCES}
+endif
+endif
diff --git a/plat/nxp/common/img_loadr/load_img.c b/plat/nxp/common/img_loadr/load_img.c
new file mode 100644
index 0000000..c185c36
--- /dev/null
+++ b/plat/nxp/common/img_loadr/load_img.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <assert.h>
+
+#include <common/bl_common.h>
+#include <common/desc_image_load.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+
+#include "load_img.h"
+
+/******************************************************************************
+ * This function can be used to load DDR PHY/FUSE Images
+ *
+ * @param [in] image_id Image ID to be loaded
+ *
+ * @param [in,out] image_base Location at which the image should be loaded
+ * In case image is prepended by a CSF header,
+ * image_base is pointer to actual image after
+ * the header
+ *
+ * @param [in,out] image_size User should pass the maximum size of the image
+ * possible.(Buffer size starting from image_base)
+ * Actual size of the image loaded is returned
+ * back.
+ *****************************************************************************/
+int load_img(unsigned int image_id, uintptr_t *image_base,
+ uint32_t *image_size)
+{
+ int err = 0;
+
+ image_desc_t img_info = {
+ .image_id = image_id,
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
+ VERSION_2, image_info_t, 0),
+#ifdef CSF_HEADER_PREPENDED
+ .image_info.image_base = *image_base - CSF_HDR_SZ,
+ .image_info.image_max_size = *image_size + CSF_HDR_SZ,
+#else
+ .image_info.image_base = *image_base,
+ .image_info.image_max_size = *image_size,
+#endif
+ };
+
+ /* Create MMU entry for the CSF header */
+#if PLAT_XLAT_TABLES_DYNAMIC
+#ifdef CSF_HEADER_PREPENDED
+ mmap_add_dynamic_region(img_info.image_info.image_base,
+ img_info.image_info.image_base,
+ CSF_HDR_SZ,
+ MT_MEMORY | MT_RW | MT_SECURE);
+#endif
+#endif
+
+ VERBOSE("BL2: Loading IMG %d\n", image_id);
+ err = load_auth_image(image_id, &img_info.image_info);
+ if (err != 0) {
+ VERBOSE("Failed to load IMG %d\n", image_id);
+ return err;
+ }
+
+#ifdef CSF_HEADER_PREPENDED
+ *image_base = img_info.image_info.image_base + CSF_HDR_SZ;
+ *image_size = img_info.image_info.image_size - CSF_HDR_SZ;
+#if PLAT_XLAT_TABLES_DYNAMIC
+ mmap_remove_dynamic_region(img_info.image_info.image_base,
+ CSF_HDR_SZ);
+#endif
+#else
+ *image_base = img_info.image_info.image_base;
+ *image_size = img_info.image_info.image_size;
+#endif
+
+ return err;
+}
diff --git a/plat/nxp/common/img_loadr/load_img.h b/plat/nxp/common/img_loadr/load_img.h
new file mode 100644
index 0000000..6f9de32
--- /dev/null
+++ b/plat/nxp/common/img_loadr/load_img.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef LOAD_IMAGE_H
+#define LOAD_IMAGE_H
+
+int load_img(unsigned int image_id, uintptr_t *image_base,
+ uint32_t *image_size);
+
+#endif /* LOAD_IMAGE_H */
diff --git a/plat/nxp/common/include/default/ch_2/soc_default_base_addr.h b/plat/nxp/common/include/default/ch_2/soc_default_base_addr.h
new file mode 100644
index 0000000..175a796
--- /dev/null
+++ b/plat/nxp/common/include/default/ch_2/soc_default_base_addr.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef SOC_DEFAULT_BASE_ADDR_H
+#define SOC_DEFAULT_BASE_ADDR_H
+
+/* CCSR mmu_def.h */
+#define NXP_CCSR_ADDR 0x01000000
+#define NXP_CCSR_SIZE 0x0F000000
+
+#define NXP_DCSR_ADDR 0x20000000
+#define NXP_DCSR_SIZE 0x4000000
+
+/* Flex-SPI controller address */
+#define NXP_FLEXSPI_ADDR 0x020C0000
+/* QSPI Flash Start address */
+#define NXP_QSPI_FLASH_ADDR 0x40000000
+/* NOR Flash Start address */
+#define NXP_IFC_REGION_ADDR 0x60000000
+#define NXP_NOR_FLASH_ADDR NXP_IFC_REGION_ADDR
+
+/* MMU 500 soc.c*/
+#define NXP_SMMU_ADDR 0x09000000
+
+#define NXP_SNVS_ADDR 0x01E90000
+
+#define NXP_DCFG_ADDR 0x01EE0000
+#define NXP_SFP_ADDR 0x01E80000
+#define NXP_RCPM_ADDR 0x01EE2000
+#define NXP_CSU_ADDR 0x01510000
+#define NXP_SCFG_ADDR 0x01570000
+#define NXP_DCSR_ADDR 0x20000000
+#define NXP_DCSR_DCFG_ADDR (NXP_DCSR_ADDR + 0x00140000)
+#define NXP_I2C_ADDR 0x02180000
+#define NXP_ESDHC_ADDR 0x01560000
+#define NXP_UART_ADDR 0x021C0500
+#define NXP_UART1_ADDR 0x021C0600
+
+#define NXP_GPIO1_ADDR 0x02300000
+#define NXP_GPIO2_ADDR 0x02310000
+#define NXP_GPIO3_ADDR 0x02320000
+#define NXP_GPIO4_ADDR 0x02330000
+
+#define NXP_WDOG1_NS_ADDR 0x02390000
+#define NXP_WDOG2_NS_ADDR 0x023A0000
+#define NXP_WDOG1_TZ_ADDR 0x023B0000
+#define NXP_WDOG2_TZ_ADDR 0x023C0000
+
+#define NXP_TIMER_STATUS_ADDR 0x023F0000
+
+#define NXP_GICD_4K_ADDR 0x01401000
+#define NXP_GICC_4K_ADDR 0x01402000
+#define NXP_GICD_64K_ADDR 0x01410000
+#define NXP_GICC_64K_ADDR 0x01420000
+
+#define NXP_CAAM_ADDR 0x01700000
+
+#define NXP_TZC_ADDR 0x01500000
+#define NXP_DDR_ADDR 0x01080000
+
+#define NXP_TIMER_ADDR 0x02B00000
+#define NXP_CCI_ADDR 0x01180000
+#define NXP_RESET_ADDR 0x01E60000
+#define NXP_SEC_REGFILE_ADDR 0x01E88000
+#endif /* SOC_DEFAULT_BASE_ADDR_H */
diff --git a/plat/nxp/common/include/default/ch_2/soc_default_helper_macros.h b/plat/nxp/common/include/default/ch_2/soc_default_helper_macros.h
new file mode 100644
index 0000000..789b112
--- /dev/null
+++ b/plat/nxp/common/include/default/ch_2/soc_default_helper_macros.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef SOC_DEFAULT_HELPER_MACROS_H
+#define SOC_DEFAULT_HELPER_MACROS_H
+
+#ifdef NXP_OCRAM_TZPC_ADDR
+
+/* 0x1: means 4 KB
+ * 0x2: means 8 KB
+ */
+#define TZPC_BLOCK_SIZE 0x1000
+#endif
+
+/* DDR controller offsets and defines */
+#ifdef NXP_DDR_ADDR
+
+#define DDR_CFG_2_OFFSET 0x114
+#define CFG_2_FORCE_REFRESH 0x80000000
+
+#endif /* NXP_DDR_ADDR */
+
+ /* Reset block register offsets */
+#ifdef NXP_RESET_ADDR
+
+/* Register Offset */
+#define RST_RSTCR_OFFSET 0x0
+#define RST_RSTRQMR1_OFFSET 0x10
+#define RST_RSTRQSR1_OFFSET 0x18
+#define BRR_OFFSET 0x60
+
+/* helper macros */
+#define RSTRQSR1_SWRR 0x800
+#define RSTRQMR_RPTOE_MASK (1 << 19)
+
+#endif /* NXP_RESET_ADDR */
+
+/* Secure-Register-File register offsets and bit masks */
+#ifdef NXP_RST_ADDR
+/* Register Offset */
+#define CORE_HOLD_OFFSET 0x140
+#define RSTCNTL_OFFSET 0x180
+
+/* Helper macros */
+#define SW_RST_REQ_INIT 0x1
+#endif
+
+#ifdef NXP_RCPM_ADDR
+/* RCPM Register Offsets */
+#define RCPM_PCPH20SETR_OFFSET 0x0D4
+#define RCPM_PCPH20CLRR_OFFSET 0x0D8
+#define RCPM_POWMGTCSR_OFFSET 0x130
+#define RCPM_IPPDEXPCR0_OFFSET 0x140
+#define RCPM_POWMGTCSR_LPM20_REQ 0x00100000
+#endif
+
+#endif /* SOC_DEFAULT_HELPER_MACROS_H */
diff --git a/plat/nxp/common/include/default/ch_3/soc_default_base_addr.h b/plat/nxp/common/include/default/ch_3/soc_default_base_addr.h
new file mode 100644
index 0000000..e8a7645
--- /dev/null
+++ b/plat/nxp/common/include/default/ch_3/soc_default_base_addr.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef SOC_DEFAULT_BASE_ADDR_H
+#define SOC_DEFAULT_BASE_ADDR_H
+
+/* CCSR mmu_def.h */
+#define NXP_CCSR_ADDR 0x1000000
+#define NXP_CCSR_SIZE 0xF000000
+
+#define NXP_DCSR_ADDR 0x700000000
+#define NXP_DCSR_SIZE 0x40000000
+
+/* Flex-SPI controller address */
+#define NXP_FLEXSPI_ADDR 0x020C0000
+/* Flex-SPI Flash Start address */
+#define NXP_FLEXSPI_FLASH_ADDR 0x20000000
+
+/* MMU 500 soc.c*/
+#define NXP_SMMU_ADDR 0x05000000
+
+#define NXP_SNVS_ADDR 0x01E90000
+
+#define NXP_DCFG_ADDR 0x01E00000
+#define NXP_PMU_CCSR_ADDR 0x01E30000
+#define NXP_PMU_DCSR_ADDR 0x700123000
+#define NXP_PMU_ADDR NXP_PMU_CCSR_ADDR
+#define NXP_SFP_ADDR 0x01E80000
+#define NXP_SCFG_ADDR 0x01FC0000
+#define NXP_I2C_ADDR 0x02000000
+#define NXP_ESDHC_ADDR 0x02140000
+#define NXP_ESDHC2_ADDR 0x02150000
+#define NXP_UART_ADDR 0x021C0000
+#define NXP_UART1_ADDR 0x021D0000
+
+#define NXP_GPIO1_ADDR 0x02300000
+#define NXP_GPIO2_ADDR 0x02310000
+#define NXP_GPIO3_ADDR 0x02320000
+#define NXP_GPIO4_ADDR 0x02330000
+
+#define NXP_WDOG1_NS_ADDR 0x02390000
+#define NXP_WDOG2_NS_ADDR 0x023A0000
+#define NXP_WDOG1_TZ_ADDR 0x023B0000
+#define NXP_WDOG2_TZ_ADDR 0x023C0000
+
+#define NXP_TIMER_STATUS_ADDR 0x023F0000
+
+#define NXP_GICD_ADDR 0x06000000
+#define NXP_GICR_ADDR 0x06200000
+#define NXP_GICR_SGI_ADDR 0x06210000
+
+#define NXP_CAAM_ADDR 0x08000000
+
+#define NXP_TZC_ADDR 0x01100000
+#define NXP_TZC2_ADDR 0x01110000
+#define NXP_TZC3_ADDR 0x01120000
+
+#define NXP_RESET_ADDR 0x01E60000
+#define NXP_SEC_REGFILE_ADDR 0x01E88000
+#endif /* SOC_DEFAULT_BASE_ADDR_H */
diff --git a/plat/nxp/common/include/default/ch_3_2/soc_default_base_addr.h b/plat/nxp/common/include/default/ch_3_2/soc_default_base_addr.h
new file mode 100644
index 0000000..08300b0
--- /dev/null
+++ b/plat/nxp/common/include/default/ch_3_2/soc_default_base_addr.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef SOC_DEFAULT_BASE_ADDR_H
+#define SOC_DEFAULT_BASE_ADDR_H
+
+/* CCSR mmu_def.h */
+#define NXP_CCSR_ADDR 0x1000000
+#define NXP_CCSR_SIZE 0xF000000
+
+#define NXP_DCSR_ADDR 0x700000000
+#define NXP_DCSR_SIZE 0x40000000
+
+/* Flex-SPI controller address */
+#define NXP_FLEXSPI_ADDR 0x020C0000
+/* Flex-SPI Flash Start address */
+#define NXP_FLEXSPI_FLASH_ADDR 0x20000000
+
+/* MMU 500 soc.c*/
+#define NXP_SMMU_ADDR 0x05000000
+
+#define NXP_SNVS_ADDR 0x01E90000
+
+#define NXP_DCFG_ADDR 0x01E00000
+#define NXP_PMU_CCSR_ADDR 0x01E30000
+#define NXP_PMU_DCSR_ADDR 0x700123000
+#define NXP_PMU_ADDR NXP_PMU_CCSR_ADDR
+#define NXP_SFP_ADDR 0x01E80000
+#define NXP_SCFG_ADDR 0x01FC0000
+#define NXP_I2C_ADDR 0x02000000
+#define NXP_ESDHC_ADDR 0x02140000
+#define NXP_ESDHC2_ADDR 0x02150000
+#define NXP_UART_ADDR 0x021C0000
+#define NXP_UART1_ADDR 0x021D0000
+
+#define NXP_GPIO1_ADDR 0x02300000
+#define NXP_GPIO2_ADDR 0x02310000
+#define NXP_GPIO3_ADDR 0x02320000
+#define NXP_GPIO4_ADDR 0x02330000
+
+#define NXP_WDOG1_NS_ADDR 0x02390000
+#define NXP_WDOG2_NS_ADDR 0x023A0000
+#define NXP_WDOG1_TZ_ADDR 0x023B0000
+#define NXP_WDOG2_TZ_ADDR 0x023C0000
+
+#define NXP_TIMER_STATUS_ADDR 0x023F0000
+
+#define NXP_GICD_ADDR 0x06000000
+#define NXP_GICR_ADDR 0x06200000
+#define NXP_GICR_SGI_ADDR 0x06210000
+
+#define NXP_CAAM_ADDR 0x08000000
+
+#define NXP_TZC_ADDR 0x01100000
+#define NXP_TZC2_ADDR 0x01110000
+#define NXP_TZC3_ADDR 0x01120000
+
+#define NXP_TIMER_ADDR 0x023E0000
+
+#define NXP_RESET_ADDR 0x01E60000
+#define NXP_SEC_REGFILE_ADDR 0x01E88000
+#define NXP_RST_ADDR 0x01E88000
+
+#define TPMWAKEMR0_ADDR 0x700123c50
+#define TZPC_BLOCK_SIZE 0x1000
+
+#define NXP_TZC_ADDR 0x01100000
+#define NXP_TZC2_ADDR 0x01110000
+#define NXP_TZC3_ADDR 0x01120000
+#define NXP_TZC4_ADDR 0x01130000
+#define NXP_DDR_ADDR 0x01080000
+#define NXP_DDR2_ADDR 0x01090000
+
+#define NXP_OCRAM_TZPC_ADDR 0x02200000
+
+#define NXP_CCN_ADDR 0x04000000
+#define NXP_CCN_HNI_ADDR 0x04080000
+#define NXP_CCN_HN_F_0_ADDR 0x04200000
+
+#endif /* SOC_DEFAULT_BASE_ADDR_H */
diff --git a/plat/nxp/common/include/default/ch_3_2/soc_default_helper_macros.h b/plat/nxp/common/include/default/ch_3_2/soc_default_helper_macros.h
new file mode 100644
index 0000000..cdc823a
--- /dev/null
+++ b/plat/nxp/common/include/default/ch_3_2/soc_default_helper_macros.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef SOC_DEFAULT_HELPER_MACROS_H
+#define SOC_DEFAULT_HELPER_MACROS_H
+
+#ifdef NXP_OCRAM_TZPC_ADDR
+
+/* 0x1: means 4 KB
+ * 0x2: means 8 KB
+ */
+#define TZPC_BLOCK_SIZE 0x1000
+#endif
+
+/* DDR controller offsets and defines */
+#ifdef NXP_DDR_ADDR
+
+#define DDR_CFG_2_OFFSET 0x114
+#define CFG_2_FORCE_REFRESH 0x80000000
+
+#endif /* NXP_DDR_ADDR */
+
+ /* Reset block register offsets */
+#ifdef NXP_RESET_ADDR
+
+/* Register Offset */
+#define RST_RSTCR_OFFSET 0x0
+#define RST_RSTRQMR1_OFFSET 0x10
+#define RST_RSTRQSR1_OFFSET 0x18
+#define BRR_OFFSET 0x60
+
+/* helper macros */
+#define RSTRQSR1_SWRR 0x800
+#define RSTRQMR_RPTOE_MASK (1 << 19)
+
+#endif /* NXP_RESET_ADDR */
+
+/* Secure-Register-File register offsets and bit masks */
+#ifdef NXP_RST_ADDR
+/* Register Offset */
+#define CORE_HOLD_OFFSET 0x140
+#define RSTCNTL_OFFSET 0x180
+
+/* Helper macros */
+#define SW_RST_REQ_INIT 0x1
+#endif
+
+#ifdef NXP_CCN_ADDR
+#define NXP_CCN_HN_F_1_ADDR 0x04210000
+
+#define CCN_HN_F_SAM_NODEID_MASK 0x7f
+#define CCN_HN_F_SNP_DMN_CTL_OFFSET 0x200
+#define CCN_HN_F_SNP_DMN_CTL_SET_OFFSET 0x210
+#define CCN_HN_F_SNP_DMN_CTL_CLR_OFFSET 0x220
+#define CCN_HN_F_SNP_DMN_CTL_MASK 0x80a00
+#define CCN_HNF_NODE_COUNT 8
+#define CCN_HNF_OFFSET 0x10000
+
+#define SA_AUX_CTRL_REG_OFFSET 0x500
+#define NUM_HNI_NODE 2
+#define CCN_HNI_MEMORY_MAP_SIZE 0x10000
+
+#define PCIeRC_RN_I_NODE_ID_OFFSET 0x8
+#define PoS_CONTROL_REG_OFFSET 0x0
+#define POS_EARLY_WR_COMP_EN 0x20
+#define HNI_POS_EN 0x01
+#define POS_TERMINATE_BARRIERS 0x10
+#define SERIALIZE_DEV_nGnRnE_WRITES 0x200
+#define ENABLE_ERR_SIGNAL_TO_MN 0x4
+#define ENABLE_RESERVE_BIT53 0x400
+#define ENABLE_WUO 0x10
+#endif /* NXP_CCN_ADDR */
+
+#endif /* SOC_DEFAULT_HELPER_MACROS_H */
diff --git a/plat/nxp/common/include/default/plat_default_def.h b/plat/nxp/common/include/default/plat_default_def.h
new file mode 100644
index 0000000..dd5dfe0
--- /dev/null
+++ b/plat/nxp/common/include/default/plat_default_def.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PLAT_DEFAULT_DEF_H
+#define PLAT_DEFAULT_DEF_H
+
+/*
+ * Platform binary types for linking
+ */
+#ifdef __aarch64__
+#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH aarch64
+#else
+#define PLATFORM_LINKER_FORMAT "elf32-littlearm"
+#define PLATFORM_LINKER_ARCH arm
+#endif /* __aarch64__ */
+
+#define LS_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
+
+/* NXP Platforms have DRAM divided into banks.
+ * DRAM0 Bank: Maximum size of this bank is fixed to 2GB
+ * DRAM1 Bank: Greater than 2GB belongs to bank1 and size of bank1 varies from
+ * one platform to other platform.
+ * DRAMn Bank:
+ *
+ * Except a few, all the platforms have 2GB size as DRAM0 BANK.
+ * Hence common for all the platforms.
+ * For platforms where DRAM0 Size is < 2GB, it is defined in platform_def.h
+ */
+#ifndef PLAT_DEF_DRAM0_SIZE
+#define PLAT_DEF_DRAM0_SIZE 0x80000000 /* 2G */
+#endif
+
+/* This is common for all platforms where: */
+#ifndef NXP_NS_DRAM_ADDR
+#define NXP_NS_DRAM_ADDR NXP_DRAM0_ADDR
+#endif
+
+/* 64M is reserved for Secure memory
+ */
+#ifndef NXP_SECURE_DRAM_SIZE
+#define NXP_SECURE_DRAM_SIZE (64 * 1024 * 1024)
+#endif
+
+/* 2M Secure EL1 Payload Shared Memory */
+#ifndef NXP_SP_SHRD_DRAM_SIZE
+#define NXP_SP_SHRD_DRAM_SIZE (2 * 1024 * 1024)
+#endif
+
+#ifndef NXP_NS_DRAM_SIZE
+/* Non secure memory */
+#define NXP_NS_DRAM_SIZE (PLAT_DEF_DRAM0_SIZE - \
+ (NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE))
+#endif
+
+#ifndef NXP_SECURE_DRAM_ADDR
+#ifdef TEST_BL31
+#define NXP_SECURE_DRAM_ADDR 0
+#else
+#define NXP_SECURE_DRAM_ADDR (NXP_NS_DRAM_ADDR + PLAT_DEF_DRAM0_SIZE - \
+ (NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE))
+#endif
+#endif
+
+#ifndef NXP_SP_SHRD_DRAM_ADDR
+#define NXP_SP_SHRD_DRAM_ADDR (NXP_NS_DRAM_ADDR + PLAT_DEF_DRAM0_SIZE \
+ - NXP_SP_SHRD_DRAM_SIZE)
+#endif
+
+#ifndef BL31_BASE
+/* 2 MB reserved in secure memory for DDR */
+#define BL31_BASE NXP_SECURE_DRAM_ADDR
+#endif
+
+#ifndef BL31_SIZE
+#define BL31_SIZE (0x200000)
+#endif
+
+#ifndef BL31_LIMIT
+#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
+#endif
+
+/* Put BL32 in secure memory */
+#ifndef BL32_BASE
+#define BL32_BASE (NXP_SECURE_DRAM_ADDR + BL31_SIZE)
+#endif
+
+#ifndef BL32_LIMIT
+#define BL32_LIMIT (NXP_SECURE_DRAM_ADDR + \
+ NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE)
+#endif
+
+/* BL33 memory region */
+/* Hardcoded based on current address in u-boot */
+#ifndef BL33_BASE
+#define BL33_BASE 0x82000000
+#endif
+
+#ifndef BL33_LIMIT
+#define BL33_LIMIT (NXP_NS_DRAM_ADDR + NXP_NS_DRAM_SIZE)
+#endif
+
+/*
+ * FIP image defines - Offset at which FIP Image would be present
+ * Image would include Bl31 , Bl33 and Bl32 (optional)
+ */
+#ifdef POLICY_FUSE_PROVISION
+#ifndef FUSE_BUF
+#define FUSE_BUF ULL(0x81000000)
+#endif
+
+#ifndef FUSE_SZ
+#define FUSE_SZ 0x80000
+#endif
+#endif
+
+#ifndef MAX_FIP_DEVICES
+#define MAX_FIP_DEVICES 2
+#endif
+
+#ifndef PLAT_FIP_OFFSET
+#define PLAT_FIP_OFFSET 0x100000
+#endif
+
+#ifndef PLAT_FIP_MAX_SIZE
+#define PLAT_FIP_MAX_SIZE 0x400000
+#endif
+
+/* Check if this size can be determined from array size */
+#if defined(IMAGE_BL2)
+#ifndef MAX_MMAP_REGIONS
+#define MAX_MMAP_REGIONS 8
+#endif
+#ifndef MAX_XLAT_TABLES
+#define MAX_XLAT_TABLES 6
+#endif
+#elif defined(IMAGE_BL31)
+#ifndef MAX_MMAP_REGIONS
+#define MAX_MMAP_REGIONS 9
+#endif
+#ifndef MAX_XLAT_TABLES
+#define MAX_XLAT_TABLES 9
+#endif
+#elif defined(IMAGE_BL32)
+#ifndef MAX_MMAP_REGIONS
+#define MAX_MMAP_REGIONS 8
+#endif
+#ifndef MAX_XLAT_TABLES
+#define MAX_XLAT_TABLES 9
+#endif
+#endif
+
+/*
+ * ID of the secure physical generic timer interrupt used by the BL32.
+ */
+#ifndef BL32_IRQ_SEC_PHY_TIMER
+#define BL32_IRQ_SEC_PHY_TIMER 29
+#endif
+
+#endif /* PLAT_DEFAULT_DEF_H */
diff --git a/plat/nxp/common/nv_storage/nv_storage.mk b/plat/nxp/common/nv_storage/nv_storage.mk
new file mode 100644
index 0000000..dddba5f
--- /dev/null
+++ b/plat/nxp/common/nv_storage/nv_storage.mk
@@ -0,0 +1,29 @@
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# NXP Non-Volatile data flag storage used and then cleared by SW on boot-up
+
+$(eval $(call add_define,NXP_NV_SW_MAINT_LAST_EXEC_DATA))
+
+ifeq ($(NXP_COINED_BB),yes)
+$(eval $(call add_define,NXP_COINED_BB))
+# BL2 : To read the reset cause from LP SECMON GPR register
+# BL31: To write the reset cause to LP SECMON GPR register
+$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL_COMM))
+
+# BL2: DDR training data is stored on Flexspi NOR.
+ifneq (${BOOT_MODE},flexspi_nor)
+$(eval $(call SET_NXP_MAKE_FLAG,XSPI_NEEDED,BL2))
+endif
+
+else
+$(eval $(call add_define_val,DEFAULT_NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}'))
+$(eval $(call SET_NXP_MAKE_FLAG,XSPI_NEEDED,BL_COMM))
+endif
+
+NV_STORAGE_INCLUDES += -I${PLAT_COMMON_PATH}/nv_storage
+
+NV_STORAGE_SOURCES += ${PLAT_COMMON_PATH}/nv_storage/plat_nv_storage.c
diff --git a/plat/nxp/common/nv_storage/plat_nv_storage.c b/plat/nxp/common/nv_storage/plat_nv_storage.c
new file mode 100644
index 0000000..7ec4fdb
--- /dev/null
+++ b/plat/nxp/common/nv_storage/plat_nv_storage.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <common/debug.h>
+#ifndef NXP_COINED_BB
+#include <flash_info.h>
+#include <fspi.h>
+#include <fspi_api.h>
+#endif
+#include <lib/mmio.h>
+#ifdef NXP_COINED_BB
+#include <snvs.h>
+#else
+#include <xspi_error_codes.h>
+#endif
+
+#include <plat_nv_storage.h>
+
+/*This structure will be a static structure and
+ * will be populated as first step of BL2 booting-up.
+ * fspi_strorage.c . To be located in the fspi driver folder.
+ */
+
+static nv_app_data_t nv_app_data;
+
+int read_nv_app_data(void)
+{
+ int ret = 0;
+
+#ifdef NXP_COINED_BB
+ uint8_t *nv_app_data_array = (uint8_t *) &nv_app_data;
+ uint8_t offset = 0U;
+
+ ret = snvs_read_app_data();
+ do {
+ nv_app_data_array[offset] = snvs_read_app_data_bit(offset);
+ offset++;
+
+ } while (offset < APP_DATA_MAX_OFFSET);
+ snvs_clear_app_data();
+#else
+ uintptr_t nv_base_addr = NV_STORAGE_BASE_ADDR;
+
+ ret = fspi_init(NXP_FLEXSPI_ADDR, NXP_FLEXSPI_FLASH_ADDR);
+
+ if (ret != XSPI_SUCCESS) {
+ ERROR("Failed to initialized driver flexspi-nor.\n");
+ ERROR("exiting warm-reset request.\n");
+ return -ENODEV;
+ }
+
+ xspi_read(nv_base_addr,
+ (uint32_t *)&nv_app_data, sizeof(nv_app_data_t));
+ xspi_sector_erase((uint32_t) nv_base_addr,
+ F_SECTOR_ERASE_SZ);
+#endif
+ return ret;
+}
+
+int wr_nv_app_data(int data_offset,
+ uint8_t *data,
+ int data_size)
+{
+ int ret = 0;
+#ifdef NXP_COINED_BB
+#if !TRUSTED_BOARD_BOOT
+ snvs_disable_zeroize_lp_gpr();
+#endif
+ /* In case LP SecMon General purpose register,
+ * only 1 bit flags can be saved.
+ */
+ if ((data_size > 1) || (*data != DEFAULT_SET_VALUE)) {
+ ERROR("Only binary value is allowed to be written.\n");
+ ERROR("Use flash instead of SNVS GPR as NV location.\n");
+ return -ENODEV;
+ }
+ snvs_write_app_data_bit(data_offset);
+#else
+ uint8_t read_val[sizeof(nv_app_data_t)];
+ uint8_t ready_to_write_val[sizeof(nv_app_data_t)];
+ uintptr_t nv_base_addr = NV_STORAGE_BASE_ADDR;
+
+ assert((nv_base_addr + data_offset + data_size) > (nv_base_addr + F_SECTOR_ERASE_SZ));
+
+ ret = fspi_init(NXP_FLEXSPI_ADDR, NXP_FLEXSPI_FLASH_ADDR);
+
+ if (ret != XSPI_SUCCESS) {
+ ERROR("Failed to initialized driver flexspi-nor.\n");
+ ERROR("exiting warm-reset request.\n");
+ return -ENODEV;
+ }
+
+ ret = xspi_read(nv_base_addr + data_offset, (uint32_t *)read_val, data_size);
+
+ memset(ready_to_write_val, READY_TO_WRITE_VALUE, ARRAY_SIZE(ready_to_write_val));
+
+ if (memcmp(read_val, ready_to_write_val, data_size) == 0) {
+ xspi_write(nv_base_addr + data_offset, data, data_size);
+ }
+#endif
+
+ return ret;
+}
+
+const nv_app_data_t *get_nv_data(void)
+{
+ return (const nv_app_data_t *) &nv_app_data;
+}
diff --git a/plat/nxp/common/nv_storage/plat_nv_storage.h b/plat/nxp/common/nv_storage/plat_nv_storage.h
new file mode 100644
index 0000000..1f5264a
--- /dev/null
+++ b/plat/nxp/common/nv_storage/plat_nv_storage.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PLAT_NV_STRG_H
+#define PLAT_NV_STRG_H
+
+#define DEFAULT_SET_VALUE 0xA1
+#define READY_TO_WRITE_VALUE 0xFF
+
+#ifndef NV_STORAGE_BASE_ADDR
+#define NV_STORAGE_BASE_ADDR DEFAULT_NV_STORAGE_BASE_ADDR
+#endif
+
+typedef struct {
+uint8_t warm_rst_flag;
+uint8_t wdt_rst_flag;
+uint8_t dummy[2];
+} nv_app_data_t;
+
+
+/*below enum and above structure should be in-sync. */
+enum app_data_offset {
+ WARM_RESET_FLAG_OFFSET,
+ WDT_RESET_FLAG_OFFSET,
+ APP_DATA_MAX_OFFSET,
+};
+
+int read_nv_app_data(void);
+
+int wr_nv_app_data(int data_offset,
+ uint8_t *data,
+ int data_size);
+
+const nv_app_data_t *get_nv_data(void);
+
+#endif /* PLAT_NV_STRG_H */
diff --git a/plat/nxp/common/plat_make_helper/plat_common_def.mk b/plat/nxp/common/plat_make_helper/plat_common_def.mk
new file mode 100644
index 0000000..86dacf8
--- /dev/null
+++ b/plat/nxp/common/plat_make_helper/plat_common_def.mk
@@ -0,0 +1,103 @@
+# Copyright 2020-2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Include build macros, for example: SET_NXP_MAKE_FLAG
+include plat/nxp/common/plat_make_helper/plat_build_macros.mk
+
+# Adding platform specific defines
+
+$(eval $(call add_define_val,BOARD,'"${BOARD}"'))
+
+ifeq (${POVDD_ENABLE},yes)
+$(eval $(call add_define,CONFIG_POVDD_ENABLE))
+endif
+
+ifneq (${FLASH_TYPE},)
+$(eval $(call add_define,CONFIG_${FLASH_TYPE}))
+endif
+
+ifneq (${XSPI_FLASH_SZ},)
+$(eval $(call add_define_val,NXP_FLEXSPI_FLASH_SIZE,${XSPI_FLASH_SZ}))
+endif
+
+ifneq (${QSPI_FLASH_SZ},)
+$(eval $(call add_define_val,NXP_QSPI_FLASH_SIZE,${QSPI_FLASH_SZ}))
+endif
+
+ifneq (${NOR_FLASH_SZ},)
+$(eval $(call add_define_val,NXP_NOR_FLASH_SIZE,${NOR_FLASH_SZ}))
+endif
+
+
+ifneq (${FSPI_ERASE_4K},)
+$(eval $(call add_define_val,CONFIG_FSPI_ERASE_4K,${FSPI_ERASE_4K}))
+endif
+
+ifneq (${NUM_OF_DDRC},)
+$(eval $(call add_define_val,NUM_OF_DDRC,${NUM_OF_DDRC}))
+endif
+
+ifeq (${CONFIG_DDR_NODIMM},1)
+$(eval $(call add_define,CONFIG_DDR_NODIMM))
+DDRC_NUM_DIMM := 1
+endif
+
+ifneq (${DDRC_NUM_DIMM},)
+$(eval $(call add_define_val,DDRC_NUM_DIMM,${DDRC_NUM_DIMM}))
+endif
+
+ifneq (${DDRC_NUM_CS},)
+$(eval $(call add_define_val,DDRC_NUM_CS,${DDRC_NUM_CS}))
+endif
+
+ifeq (${DDR_ADDR_DEC},yes)
+$(eval $(call add_define,CONFIG_DDR_ADDR_DEC))
+endif
+
+ifeq (${DDR_ECC_EN},yes)
+$(eval $(call add_define,CONFIG_DDR_ECC_EN))
+endif
+
+ifeq (${CONFIG_STATIC_DDR},1)
+$(eval $(call add_define,CONFIG_STATIC_DDR))
+endif
+
+# Platform can control the base address for non-volatile storage.
+#$(eval $(call add_define_val,NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}'))
+
+ifeq (${WARM_BOOT},yes)
+$(eval $(call add_define_val,PHY_TRAINING_REGS_ON_FLASH,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - ${NXP_XSPI_NOR_UNIT_SIZE}'))
+endif
+
+# Selecting Boot Source for the TFA images.
+define add_boot_mode_define
+ ifeq ($(1),qspi)
+ $$(eval $$(call SET_NXP_MAKE_FLAG,QSPI_NEEDED,BL2))
+ $$(eval $$(call add_define,QSPI_BOOT))
+ else ifeq ($(1),sd)
+ $$(eval $$(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2))
+ $$(eval $$(call add_define,SD_BOOT))
+ else ifeq ($(1),emmc)
+ $$(eval $$(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2))
+ $$(eval $$(call add_define,EMMC_BOOT))
+ else ifeq ($(1),nor)
+ $$(eval $$(call SET_NXP_MAKE_FLAG,IFC_NOR_NEEDED,BL2))
+ $$(eval $$(call add_define,NOR_BOOT))
+ else ifeq ($(1),nand)
+ $$(eval $$(call SET_NXP_MAKE_FLAG,IFC_NAND_NEEDED,BL2))
+ $$(eval $$(call add_define,NAND_BOOT))
+ else ifeq ($(1),flexspi_nor)
+ $$(eval $$(call SET_NXP_MAKE_FLAG,XSPI_NEEDED,BL2))
+ $$(eval $$(call add_define,FLEXSPI_NOR_BOOT))
+ else
+ $$(error $(PLAT) Cannot Support Boot Mode: $(BOOT_MODE))
+ endif
+endef
+
+ifneq (,$(findstring $(BOOT_MODE),$(SUPPORTED_BOOT_MODE)))
+ $(eval $(call add_boot_mode_define,$(strip $(BOOT_MODE))))
+else
+ $(error $(PLAT) Un-supported Boot Mode = $(BOOT_MODE))
+endif
diff --git a/plat/nxp/common/plat_make_helper/soc_common_def.mk b/plat/nxp/common/plat_make_helper/soc_common_def.mk
new file mode 100644
index 0000000..fdd7249
--- /dev/null
+++ b/plat/nxp/common/plat_make_helper/soc_common_def.mk
@@ -0,0 +1,114 @@
+# Copyright 2020-2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Adding SoC specific defines
+
+ifneq (${CACHE_LINE},)
+$(eval $(call add_define_val,PLATFORM_CACHE_LINE_SHIFT,${CACHE_LINE}))
+$(eval CACHE_WRITEBACK_GRANULE=$(shell echo $$((1 << $(CACHE_LINE)))))
+$(eval $(call add_define_val,CACHE_WRITEBACK_GRANULE,$(CACHE_WRITEBACK_GRANULE)))
+endif
+
+ifeq (${INTERCONNECT}, "CCI400")
+$(eval $(call add_define,NXP_HAS_${INTERCONNECT}))
+ICNNCT_ID := 0x420
+$(eval $(call add_define,ICNNCT_ID))
+endif
+
+ifeq (${INTERCONNECT}, "CCN508")
+$(eval $(call add_define,NXP_HAS_CCN508))
+endif
+
+ifneq (${CHASSIS},)
+$(eval $(call add_define,CONFIG_CHASSIS_${CHASSIS}))
+endif
+
+ifneq (${PLAT_DDR_PHY},)
+$(eval $(call add_define,NXP_DDR_${PLAT_DDR_PHY}))
+endif
+
+ifneq (${PHYS_SYS},)
+$(eval $(call add_define,CONFIG_PHYS_64BIT))
+endif
+
+ifneq (${CSF_HDR_SZ},)
+$(eval $(call add_define_val,CSF_HDR_SZ,${CSF_HDR_SZ}))
+endif
+
+ifneq (${OCRAM_START_ADDR},)
+$(eval $(call add_define_val,NXP_OCRAM_ADDR,${OCRAM_START_ADDR}))
+endif
+
+ifneq (${OCRAM_SIZE},)
+$(eval $(call add_define_val,NXP_OCRAM_SIZE,${OCRAM_SIZE}))
+endif
+
+ifneq (${NXP_ROM_RSVD},)
+$(eval $(call add_define_val,NXP_ROM_RSVD,${NXP_ROM_RSVD}))
+endif
+
+ifneq (${BL2_BASE},)
+$(eval $(call add_define_val,BL2_BASE,${BL2_BASE}))
+endif
+
+ifeq (${SEC_MEM_NON_COHERENT},yes)
+$(eval $(call add_define,SEC_MEM_NON_COHERENT))
+endif
+
+ifneq (${NXP_ESDHC_ENDIANNESS},)
+$(eval $(call add_define,NXP_ESDHC_${NXP_ESDHC_ENDIANNESS}))
+endif
+
+ifneq (${NXP_SFP_VER},)
+$(eval $(call add_define,NXP_SFP_VER_${NXP_SFP_VER}))
+endif
+
+ifneq (${NXP_SFP_ENDIANNESS},)
+$(eval $(call add_define,NXP_SFP_${NXP_SFP_ENDIANNESS}))
+endif
+
+ifneq (${NXP_GPIO_ENDIANNESS},)
+$(eval $(call add_define,NXP_GPIO_${NXP_GPIO_ENDIANNESS}))
+endif
+
+ifneq (${NXP_SNVS_ENDIANNESS},)
+$(eval $(call add_define,NXP_SNVS_${NXP_SNVS_ENDIANNESS}))
+endif
+
+ifneq (${NXP_GUR_ENDIANNESS},)
+$(eval $(call add_define,NXP_GUR_${NXP_GUR_ENDIANNESS}))
+endif
+
+ifneq (${NXP_FSPI_ENDIANNESS},)
+$(eval $(call add_define,NXP_FSPI_${NXP_FSPI_ENDIANNESS}))
+endif
+
+ifneq (${NXP_SEC_ENDIANNESS},)
+$(eval $(call add_define,NXP_SEC_${NXP_SEC_ENDIANNESS}))
+endif
+
+ifneq (${NXP_DDR_ENDIANNESS},)
+$(eval $(call add_define,NXP_DDR_${NXP_DDR_ENDIANNESS}))
+endif
+
+ifneq (${NXP_QSPI_ENDIANNESS},)
+$(eval $(call add_define,NXP_QSPI_${NXP_QSPI_ENDIANNESS}))
+endif
+
+ifneq (${NXP_SCFG_ENDIANNESS},)
+$(eval $(call add_define,NXP_SCFG_${NXP_SCFG_ENDIANNESS}))
+endif
+
+ifneq (${NXP_IFC_ENDIANNESS},)
+$(eval $(call add_define,NXP_IFC_${NXP_IFC_ENDIANNESS}))
+endif
+
+ifneq (${NXP_DDR_INTLV_256B},)
+$(eval $(call add_define,NXP_DDR_INTLV_256B))
+endif
+
+ifneq (${PLAT_XLAT_TABLES_DYNAMIC},)
+$(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC))
+endif
diff --git a/plat/nxp/common/psci/aarch64/psci_utils.S b/plat/nxp/common/psci/aarch64/psci_utils.S
new file mode 100644
index 0000000..ea2abbf
--- /dev/null
+++ b/plat/nxp/common/psci/aarch64/psci_utils.S
@@ -0,0 +1,1155 @@
+
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <asm_macros.S>
+#include <assert_macros.S>
+
+#include <lib/psci/psci.h>
+
+#include <bl31_data.h>
+#include <plat_psci.h>
+
+
+#define RESET_RETRY_CNT 800
+#define PSCI_ABORT_CNT 100
+
+#if (SOC_CORE_RELEASE)
+
+.global _psci_cpu_on
+
+/*
+ * int _psci_cpu_on(u_register_t core_mask)
+ * x0 = target cpu core mask
+ *
+ * Called from C, so save the non-volatile regs
+ * save these as pairs of registers to maintain the
+ * required 16-byte alignment on the stack
+ *
+ */
+
+func _psci_cpu_on
+ stp x4, x5, [sp, #-16]!
+ stp x6, x7, [sp, #-16]!
+ stp x8, x9, [sp, #-16]!
+ stp x10, x11, [sp, #-16]!
+ stp x12, x13, [sp, #-16]!
+ stp x14, x15, [sp, #-16]!
+ stp x16, x17, [sp, #-16]!
+ stp x18, x30, [sp, #-16]!
+
+ mov x6, x0
+
+ /* x0 = core mask (lsb)
+ * x6 = core mask (lsb)
+ */
+
+ /* check if core disabled */
+ bl _soc_ck_disabled /* 0-2 */
+ cbnz w0, psci_disabled
+
+ /* check core data area to see if core cannot be turned on
+ * read the core state
+ */
+ mov x0, x6
+ bl _getCoreState /* 0-5 */
+ mov x9, x0
+
+ /* x6 = core mask (lsb)
+ * x9 = core state (from data area)
+ */
+
+ cmp x9, #CORE_DISABLED
+ mov x0, #PSCI_E_DISABLED
+ b.eq cpu_on_done
+
+ cmp x9, #CORE_PENDING
+ mov x0, #PSCI_E_ON_PENDING
+ b.eq cpu_on_done
+
+ cmp x9, #CORE_RELEASED
+ mov x0, #PSCI_E_ALREADY_ON
+ b.eq cpu_on_done
+
+8:
+ /* x6 = core mask (lsb)
+ * x9 = core state (from data area)
+ */
+
+ cmp x9, #CORE_WFE
+ b.eq core_in_wfe
+ cmp x9, #CORE_IN_RESET
+ b.eq core_in_reset
+ cmp x9, #CORE_OFF
+ b.eq core_is_off
+ cmp x9, #CORE_OFF_PENDING
+
+ /* if state == CORE_OFF_PENDING, set abort */
+ mov x0, x6
+ mov x1, #ABORT_FLAG_DATA
+ mov x2, #CORE_ABORT_OP
+ bl _setCoreData /* 0-3, [13-15] */
+
+ ldr x3, =PSCI_ABORT_CNT
+7:
+ /* watch for abort to take effect */
+ mov x0, x6
+ bl _getCoreState /* 0-5 */
+ cmp x0, #CORE_OFF
+ b.eq core_is_off
+ cmp x0, #CORE_PENDING
+ mov x0, #PSCI_E_SUCCESS
+ b.eq cpu_on_done
+
+ /* loop til finished */
+ sub x3, x3, #1
+ cbnz x3, 7b
+
+ /* if we didn't see either CORE_OFF or CORE_PENDING, then this
+ * core is in CORE_OFF_PENDING - exit with success, as the core will
+ * respond to the abort request
+ */
+ mov x0, #PSCI_E_SUCCESS
+ b cpu_on_done
+
+/* this is where we start up a core out of reset */
+core_in_reset:
+ /* see if the soc-specific module supports this op */
+ ldr x7, =SOC_CORE_RELEASE
+ cbnz x7, 3f
+
+ mov x0, #PSCI_E_NOT_SUPPORTED
+ b cpu_on_done
+
+ /* x6 = core mask (lsb) */
+3:
+ /* set core state in data area */
+ mov x0, x6
+ mov x1, #CORE_PENDING
+ bl _setCoreState /* 0-3, [13-15] */
+
+ /* release the core from reset */
+ mov x0, x6
+ bl _soc_core_release /* 0-3 */
+ mov x0, #PSCI_E_SUCCESS
+ b cpu_on_done
+
+ /* Start up the core that has been powered-down via CPU_OFF
+ */
+core_is_off:
+ /* see if the soc-specific module supports this op
+ */
+ ldr x7, =SOC_CORE_RESTART
+ cbnz x7, 2f
+
+ mov x0, #PSCI_E_NOT_SUPPORTED
+ b cpu_on_done
+
+ /* x6 = core mask (lsb) */
+2:
+ /* set core state in data area */
+ mov x0, x6
+ mov x1, #CORE_WAKEUP
+ bl _setCoreState /* 0-3, [13-15] */
+
+ /* put the core back into service */
+ mov x0, x6
+#if (SOC_CORE_RESTART)
+ bl _soc_core_restart /* 0-5 */
+#endif
+ mov x0, #PSCI_E_SUCCESS
+ b cpu_on_done
+
+/* this is where we release a core that is being held in wfe */
+core_in_wfe:
+ /* x6 = core mask (lsb) */
+
+ /* set core state in data area */
+ mov x0, x6
+ mov x1, #CORE_PENDING
+ bl _setCoreState /* 0-3, [13-15] */
+ dsb sy
+ isb
+
+ /* put the core back into service */
+ sev
+ sev
+ isb
+ mov x0, #PSCI_E_SUCCESS
+
+cpu_on_done:
+ /* restore the aarch32/64 non-volatile registers */
+ ldp x18, x30, [sp], #16
+ ldp x16, x17, [sp], #16
+ ldp x14, x15, [sp], #16
+ ldp x12, x13, [sp], #16
+ ldp x10, x11, [sp], #16
+ ldp x8, x9, [sp], #16
+ ldp x6, x7, [sp], #16
+ ldp x4, x5, [sp], #16
+ b psci_completed
+endfunc _psci_cpu_on
+
+#endif
+
+
+#if (SOC_CORE_OFF)
+
+.global _psci_cpu_prep_off
+.global _psci_cpu_off_wfi
+
+/*
+ * void _psci_cpu_prep_off(u_register_t core_mask)
+ * this function performs the SoC-specific programming prior
+ * to shutting the core down
+ * x0 = core_mask
+ *
+ * called from C, so save the non-volatile regs
+ * save these as pairs of registers to maintain the
+ * required 16-byte alignment on the stack
+ */
+
+func _psci_cpu_prep_off
+
+ stp x4, x5, [sp, #-16]!
+ stp x6, x7, [sp, #-16]!
+ stp x8, x9, [sp, #-16]!
+ stp x10, x11, [sp, #-16]!
+ stp x12, x13, [sp, #-16]!
+ stp x14, x15, [sp, #-16]!
+ stp x16, x17, [sp, #-16]!
+ stp x18, x30, [sp, #-16]!
+
+ mov x10, x0 /* x10 = core_mask */
+
+ /* the core does not return from cpu_off, so no need
+ * to save/restore non-volatile registers
+ */
+
+ /* mask interrupts by setting DAIF[7:4] to 'b1111 */
+ msr DAIFSet, #0xF
+
+ /* read cpuectlr and save current value */
+ mrs x4, CORTEX_A72_ECTLR_EL1
+ mov x1, #CPUECTLR_DATA
+ mov x2, x4
+ mov x0, x10
+ bl _setCoreData
+
+ /* remove the core from coherency */
+ bic x4, x4, #CPUECTLR_SMPEN_MASK
+ msr CORTEX_A72_ECTLR_EL1, x4
+
+ /* save scr_el3 */
+ mov x0, x10
+ mrs x4, SCR_EL3
+ mov x2, x4
+ mov x1, #SCR_EL3_DATA
+ bl _setCoreData
+
+ /* x4 = scr_el3 */
+
+ /* secure SGI (FIQ) taken to EL3, set SCR_EL3[FIQ] */
+ orr x4, x4, #SCR_FIQ_MASK
+ msr scr_el3, x4
+
+ /* x10 = core_mask */
+
+ /* prep the core for shutdown */
+ mov x0, x10
+ bl _soc_core_prep_off
+
+ /* restore the aarch32/64 non-volatile registers */
+ ldp x18, x30, [sp], #16
+ ldp x16, x17, [sp], #16
+ ldp x14, x15, [sp], #16
+ ldp x12, x13, [sp], #16
+ ldp x10, x11, [sp], #16
+ ldp x8, x9, [sp], #16
+ ldp x6, x7, [sp], #16
+ ldp x4, x5, [sp], #16
+ b psci_completed
+endfunc _psci_cpu_prep_off
+
+/*
+ * void _psci_cpu_off_wfi(u_register_t core_mask, u_register_t resume_addr)
+ * - this function shuts down the core
+ * - this function does not return!!
+ */
+
+func _psci_cpu_off_wfi
+ /* save the wakeup address */
+ mov x29, x1
+
+ /* x0 = core_mask */
+
+ /* shutdown the core */
+ bl _soc_core_entr_off
+
+ /* branch to resume execution */
+ br x29
+endfunc _psci_cpu_off_wfi
+
+#endif
+
+
+#if (SOC_CORE_RESTART)
+
+.global _psci_wakeup
+
+/*
+ * void _psci_wakeup(u_register_t core_mask)
+ * this function performs the SoC-specific programming
+ * after a core wakes up from OFF
+ * x0 = core mask
+ *
+ * called from C, so save the non-volatile regs
+ * save these as pairs of registers to maintain the
+ * required 16-byte alignment on the stack
+ */
+
+func _psci_wakeup
+
+ stp x4, x5, [sp, #-16]!
+ stp x6, x7, [sp, #-16]!
+ stp x8, x9, [sp, #-16]!
+ stp x10, x11, [sp, #-16]!
+ stp x12, x13, [sp, #-16]!
+ stp x14, x15, [sp, #-16]!
+ stp x16, x17, [sp, #-16]!
+ stp x18, x30, [sp, #-16]!
+
+ mov x4, x0 /* x4 = core mask */
+
+ /* restore scr_el3 */
+ mov x0, x4
+ mov x1, #SCR_EL3_DATA
+ bl _getCoreData
+ /* x0 = saved scr_el3 */
+ msr SCR_EL3, x0
+
+ /* x4 = core mask */
+
+ /* restore CPUECTLR */
+ mov x0, x4
+ mov x1, #CPUECTLR_DATA
+ bl _getCoreData
+ orr x0, x0, #CPUECTLR_SMPEN_MASK
+ msr CORTEX_A72_ECTLR_EL1, x0
+
+ /* x4 = core mask */
+
+ /* start the core back up */
+ mov x0, x4
+ bl _soc_core_exit_off
+
+ /* restore the aarch32/64 non-volatile registers
+ */
+ ldp x18, x30, [sp], #16
+ ldp x16, x17, [sp], #16
+ ldp x14, x15, [sp], #16
+ ldp x12, x13, [sp], #16
+ ldp x10, x11, [sp], #16
+ ldp x8, x9, [sp], #16
+ ldp x6, x7, [sp], #16
+ ldp x4, x5, [sp], #16
+ b psci_completed
+endfunc _psci_wakeup
+
+#endif
+
+
+#if (SOC_SYSTEM_RESET)
+
+.global _psci_system_reset
+
+func _psci_system_reset
+
+ /* system reset is mandatory
+ * system reset is soc-specific
+ * Note: under no circumstances do we return from this call
+ */
+ bl _soc_sys_reset
+endfunc _psci_system_reset
+
+#endif
+
+
+#if (SOC_SYSTEM_OFF)
+
+.global _psci_system_off
+
+func _psci_system_off
+
+ /* system off is mandatory
+ * system off is soc-specific
+ * Note: under no circumstances do we return from this call */
+ b _soc_sys_off
+endfunc _psci_system_off
+
+#endif
+
+
+#if (SOC_CORE_STANDBY)
+
+.global _psci_core_entr_stdby
+.global _psci_core_prep_stdby
+.global _psci_core_exit_stdby
+
+/*
+ * void _psci_core_entr_stdby(u_register_t core_mask) - this
+ * is the fast-path for simple core standby
+ */
+
+func _psci_core_entr_stdby
+ stp x4, x5, [sp, #-16]!
+ stp x6, x30, [sp, #-16]!
+
+ mov x5, x0 /* x5 = core mask */
+
+ /* save scr_el3 */
+ mov x0, x5
+ mrs x4, SCR_EL3
+ mov x2, x4
+ mov x1, #SCR_EL3_DATA
+ bl _setCoreData
+
+ /* x4 = SCR_EL3
+ * x5 = core mask
+ */
+
+ /* allow interrupts @ EL3 */
+ orr x4, x4, #(SCR_IRQ_MASK | SCR_FIQ_MASK)
+ msr SCR_EL3, x4
+
+ /* x5 = core mask */
+
+ /* put the core into standby */
+ mov x0, x5
+ bl _soc_core_entr_stdby
+
+ /* restore scr_el3 */
+ mov x0, x5
+ mov x1, #SCR_EL3_DATA
+ bl _getCoreData
+ /* x0 = saved scr_el3 */
+ msr SCR_EL3, x0
+
+ ldp x6, x30, [sp], #16
+ ldp x4, x5, [sp], #16
+ isb
+ ret
+endfunc _psci_core_entr_stdby
+
+/*
+ * void _psci_core_prep_stdby(u_register_t core_mask) - this
+ * sets up the core to enter standby state thru the normal path
+ */
+
+func _psci_core_prep_stdby
+ stp x4, x5, [sp, #-16]!
+ stp x6, x30, [sp, #-16]!
+
+ mov x5, x0
+
+ /* x5 = core mask */
+
+ /* save scr_el3 */
+ mov x0, x5
+ mrs x4, SCR_EL3
+ mov x2, x4
+ mov x1, #SCR_EL3_DATA
+ bl _setCoreData
+
+ /* allow interrupts @ EL3 */
+ orr x4, x4, #(SCR_IRQ_MASK | SCR_FIQ_MASK)
+ msr SCR_EL3, x4
+
+ /* x5 = core mask */
+
+ /* call for any SoC-specific programming */
+ mov x0, x5
+ bl _soc_core_prep_stdby
+
+ ldp x6, x30, [sp], #16
+ ldp x4, x5, [sp], #16
+ isb
+ ret
+endfunc _psci_core_prep_stdby
+
+/*
+ * void _psci_core_exit_stdby(u_register_t core_mask) - this
+ * exits the core from standby state thru the normal path
+ */
+
+func _psci_core_exit_stdby
+ stp x4, x5, [sp, #-16]!
+ stp x6, x30, [sp, #-16]!
+
+ mov x5, x0
+
+ /* x5 = core mask */
+
+ /* restore scr_el3 */
+ mov x0, x5
+ mov x1, #SCR_EL3_DATA
+ bl _getCoreData
+ /* x0 = saved scr_el3 */
+ msr SCR_EL3, x0
+
+ /* x5 = core mask */
+
+ /* perform any SoC-specific programming after standby state */
+ mov x0, x5
+ bl _soc_core_exit_stdby
+
+ ldp x6, x30, [sp], #16
+ ldp x4, x5, [sp], #16
+ isb
+ ret
+endfunc _psci_core_exit_stdby
+
+#endif
+
+
+#if (SOC_CORE_PWR_DWN)
+
+.global _psci_core_prep_pwrdn
+.global _psci_cpu_pwrdn_wfi
+.global _psci_core_exit_pwrdn
+
+/*
+ * void _psci_core_prep_pwrdn_(u_register_t core_mask)
+ * this function prepares the core for power-down
+ * x0 = core mask
+ *
+ * called from C, so save the non-volatile regs
+ * save these as pairs of registers to maintain the
+ * required 16-byte alignment on the stack
+ */
+
+func _psci_core_prep_pwrdn
+ stp x4, x5, [sp, #-16]!
+ stp x6, x7, [sp, #-16]!
+ stp x8, x9, [sp, #-16]!
+ stp x10, x11, [sp, #-16]!
+ stp x12, x13, [sp, #-16]!
+ stp x14, x15, [sp, #-16]!
+ stp x16, x17, [sp, #-16]!
+ stp x18, x30, [sp, #-16]!
+
+ mov x6, x0
+
+ /* x6 = core mask */
+
+ /* mask interrupts by setting DAIF[7:4] to 'b1111 */
+ msr DAIFSet, #0xF
+
+ /* save scr_el3 */
+ mov x0, x6
+ mrs x4, SCR_EL3
+ mov x2, x4
+ mov x1, #SCR_EL3_DATA
+ bl _setCoreData
+
+ /* allow interrupts @ EL3 */
+ orr x4, x4, #(SCR_IRQ_MASK | SCR_FIQ_MASK)
+ msr SCR_EL3, x4
+
+ /* save cpuectlr */
+ mov x0, x6
+ mov x1, #CPUECTLR_DATA
+ mrs x2, CORTEX_A72_ECTLR_EL1
+ bl _setCoreData
+
+ /* x6 = core mask */
+
+ /* SoC-specific programming for power-down */
+ mov x0, x6
+ bl _soc_core_prep_pwrdn
+
+ /* restore the aarch32/64 non-volatile registers
+ */
+ ldp x18, x30, [sp], #16
+ ldp x16, x17, [sp], #16
+ ldp x14, x15, [sp], #16
+ ldp x12, x13, [sp], #16
+ ldp x10, x11, [sp], #16
+ ldp x8, x9, [sp], #16
+ ldp x6, x7, [sp], #16
+ ldp x4, x5, [sp], #16
+ b psci_completed
+endfunc _psci_core_prep_pwrdn
+
+/*
+ * void _psci_cpu_pwrdn_wfi(u_register_t core_mask, u_register_t resume_addr)
+ * this function powers down the core
+ */
+
+func _psci_cpu_pwrdn_wfi
+ /* save the wakeup address */
+ mov x29, x1
+
+ /* x0 = core mask */
+
+ /* shutdown the core */
+ bl _soc_core_entr_pwrdn
+
+ /* branch to resume execution */
+ br x29
+endfunc _psci_cpu_pwrdn_wfi
+
+/*
+ * void _psci_core_exit_pwrdn_(u_register_t core_mask)
+ * this function cleans up after a core power-down
+ * x0 = core mask
+ *
+ * called from C, so save the non-volatile regs
+ * save these as pairs of registers to maintain the
+ * required 16-byte alignment on the stack
+ */
+
+func _psci_core_exit_pwrdn
+ stp x4, x5, [sp, #-16]!
+ stp x6, x7, [sp, #-16]!
+ stp x8, x9, [sp, #-16]!
+ stp x10, x11, [sp, #-16]!
+ stp x12, x13, [sp, #-16]!
+ stp x14, x15, [sp, #-16]!
+ stp x16, x17, [sp, #-16]!
+ stp x18, x30, [sp, #-16]!
+
+ mov x5, x0 /* x5 = core mask */
+
+ /* restore scr_el3 */
+ mov x0, x5
+ mov x1, #SCR_EL3_DATA
+ bl _getCoreData
+ /* x0 = saved scr_el3 */
+ msr SCR_EL3, x0
+
+ /* x5 = core mask */
+
+ /* restore cpuectlr */
+ mov x0, x5
+ mov x1, #CPUECTLR_DATA
+ bl _getCoreData
+ /* make sure smp is set */
+ orr x0, x0, #CPUECTLR_SMPEN_MASK
+ msr CORTEX_A72_ECTLR_EL1, x0
+
+ /* x5 = core mask */
+
+ /* SoC-specific cleanup */
+ mov x0, x5
+ bl _soc_core_exit_pwrdn
+
+ /* restore the aarch32/64 non-volatile registers
+ */
+ ldp x18, x30, [sp], #16
+ ldp x16, x17, [sp], #16
+ ldp x14, x15, [sp], #16
+ ldp x12, x13, [sp], #16
+ ldp x10, x11, [sp], #16
+ ldp x8, x9, [sp], #16
+ ldp x6, x7, [sp], #16
+ ldp x4, x5, [sp], #16
+ b psci_completed
+endfunc _psci_core_exit_pwrdn
+
+#endif
+
+#if (SOC_CLUSTER_STANDBY)
+
+.global _psci_clstr_prep_stdby
+.global _psci_clstr_exit_stdby
+
+/*
+ * void _psci_clstr_prep_stdby(u_register_t core_mask) - this
+ * sets up the clstr to enter standby state thru the normal path
+ */
+
+func _psci_clstr_prep_stdby
+ stp x4, x5, [sp, #-16]!
+ stp x6, x30, [sp, #-16]!
+
+ mov x5, x0
+
+ /* x5 = core mask */
+
+ /* save scr_el3 */
+ mov x0, x5
+ mrs x4, SCR_EL3
+ mov x2, x4
+ mov x1, #SCR_EL3_DATA
+ bl _setCoreData
+
+ /* allow interrupts @ EL3 */
+ orr x4, x4, #(SCR_IRQ_MASK | SCR_FIQ_MASK)
+ msr SCR_EL3, x4
+
+ /* x5 = core mask */
+
+ /* call for any SoC-specific programming */
+ mov x0, x5
+ bl _soc_clstr_prep_stdby
+
+ ldp x6, x30, [sp], #16
+ ldp x4, x5, [sp], #16
+ isb
+ ret
+endfunc _psci_clstr_prep_stdby
+
+/*
+ * void _psci_clstr_exit_stdby(u_register_t core_mask) - this
+ * exits the clstr from standby state thru the normal path
+ */
+
+func _psci_clstr_exit_stdby
+ stp x4, x5, [sp, #-16]!
+ stp x6, x30, [sp, #-16]!
+
+ mov x5, x0 /* x5 = core mask */
+
+ /* restore scr_el3 */
+ mov x0, x5
+ mov x1, #SCR_EL3_DATA
+ bl _getCoreData
+ /* x0 = saved scr_el3 */
+ msr SCR_EL3, x0
+
+ /* x5 = core mask */
+
+ /* perform any SoC-specific programming after standby state */
+ mov x0, x5
+ bl _soc_clstr_exit_stdby
+
+ ldp x6, x30, [sp], #16
+ ldp x4, x5, [sp], #16
+ isb
+ ret
+endfunc _psci_clstr_exit_stdby
+
+#endif
+
+#if (SOC_CLUSTER_PWR_DWN)
+
+.global _psci_clstr_prep_pwrdn
+.global _psci_clstr_exit_pwrdn
+
+/*
+ * void _psci_clstr_prep_pwrdn_(u_register_t core_mask)
+ * this function prepares the cluster+core for power-down
+ * x0 = core mask
+ *
+ * called from C, so save the non-volatile regs
+ * save these as pairs of registers to maintain the
+ * required 16-byte alignment on the stack
+ */
+
+func _psci_clstr_prep_pwrdn
+ stp x4, x5, [sp, #-16]!
+ stp x6, x7, [sp, #-16]!
+ stp x8, x9, [sp, #-16]!
+ stp x10, x11, [sp, #-16]!
+ stp x12, x13, [sp, #-16]!
+ stp x14, x15, [sp, #-16]!
+ stp x16, x17, [sp, #-16]!
+ stp x18, x30, [sp, #-16]!
+
+ mov x6, x0 /* x6 = core mask */
+
+ /* mask interrupts by setting DAIF[7:4] to 'b1111 */
+ msr DAIFSet, #0xF
+
+ /* save scr_el3 */
+ mov x0, x6
+ mrs x4, SCR_EL3
+ mov x2, x4
+ mov x1, #SCR_EL3_DATA
+ bl _setCoreData
+
+ /* allow interrupts @ EL3 */
+ orr x4, x4, #(SCR_IRQ_MASK | SCR_FIQ_MASK)
+ msr SCR_EL3, x4
+
+ /* save cpuectlr */
+ mov x0, x6
+ mov x1, #CPUECTLR_DATA
+ mrs x2, CORTEX_A72_ECTLR_EL1
+ mov x4, x2
+ bl _setCoreData
+
+ /* remove core from coherency */
+ bic x4, x4, #CPUECTLR_SMPEN_MASK
+ msr CORTEX_A72_ECTLR_EL1, x4
+
+ /* x6 = core mask */
+
+ /* SoC-specific programming for power-down */
+ mov x0, x6
+ bl _soc_clstr_prep_pwrdn
+
+ /* restore the aarch32/64 non-volatile registers
+ */
+ ldp x18, x30, [sp], #16
+ ldp x16, x17, [sp], #16
+ ldp x14, x15, [sp], #16
+ ldp x12, x13, [sp], #16
+ ldp x10, x11, [sp], #16
+ ldp x8, x9, [sp], #16
+ ldp x6, x7, [sp], #16
+ ldp x4, x5, [sp], #16
+ b psci_completed
+endfunc _psci_clstr_prep_pwrdn
+
+/*
+ * void _psci_clstr_exit_pwrdn_(u_register_t core_mask)
+ * this function cleans up after a cluster power-down
+ * x0 = core mask
+ *
+ * called from C, so save the non-volatile regs
+ * save these as pairs of registers to maintain the
+ * required 16-byte alignment on the stack
+ */
+
+func _psci_clstr_exit_pwrdn
+ stp x4, x5, [sp, #-16]!
+ stp x6, x7, [sp, #-16]!
+ stp x8, x9, [sp, #-16]!
+ stp x10, x11, [sp, #-16]!
+ stp x12, x13, [sp, #-16]!
+ stp x14, x15, [sp, #-16]!
+ stp x16, x17, [sp, #-16]!
+ stp x18, x30, [sp, #-16]!
+
+ mov x4, x0 /* x4 = core mask */
+
+ /* restore scr_el3 */
+ mov x0, x4
+ mov x1, #SCR_EL3_DATA
+ bl _getCoreData
+ /* x0 = saved scr_el3 */
+ msr SCR_EL3, x0
+
+ /* x4 = core mask */
+
+ /* restore cpuectlr */
+ mov x0, x4
+ mov x1, #CPUECTLR_DATA
+ bl _getCoreData
+ /* make sure smp is set */
+ orr x0, x0, #CPUECTLR_SMPEN_MASK
+ msr CORTEX_A72_ECTLR_EL1, x0
+
+ /* x4 = core mask */
+
+ /* SoC-specific cleanup */
+ mov x0, x4
+ bl _soc_clstr_exit_pwrdn
+
+ /* restore the aarch32/64 non-volatile registers
+ */
+ ldp x18, x30, [sp], #16
+ ldp x16, x17, [sp], #16
+ ldp x14, x15, [sp], #16
+ ldp x12, x13, [sp], #16
+ ldp x10, x11, [sp], #16
+ ldp x8, x9, [sp], #16
+ ldp x6, x7, [sp], #16
+ ldp x4, x5, [sp], #16
+ b psci_completed
+endfunc _psci_clstr_exit_pwrdn
+
+#endif
+
+#if (SOC_SYSTEM_STANDBY)
+
+.global _psci_sys_prep_stdby
+.global _psci_sys_exit_stdby
+
+/*
+ * void _psci_sys_prep_stdby(u_register_t core_mask) - this
+ * sets up the system to enter standby state thru the normal path
+ */
+
+func _psci_sys_prep_stdby
+ stp x4, x5, [sp, #-16]!
+ stp x6, x30, [sp, #-16]!
+
+ mov x5, x0 /* x5 = core mask */
+
+ /* save scr_el3 */
+ mov x0, x5
+ mrs x4, SCR_EL3
+ mov x2, x4
+ mov x1, #SCR_EL3_DATA
+ bl _setCoreData
+
+ /* allow interrupts @ EL3 */
+ orr x4, x4, #(SCR_IRQ_MASK | SCR_FIQ_MASK)
+ msr SCR_EL3, x4
+
+ /* x5 = core mask */
+
+ /* call for any SoC-specific programming */
+ mov x0, x5
+ bl _soc_sys_prep_stdby
+
+ ldp x6, x30, [sp], #16
+ ldp x4, x5, [sp], #16
+ isb
+ ret
+endfunc _psci_sys_prep_stdby
+
+/*
+ * void _psci_sys_exit_stdby(u_register_t core_mask) - this
+ * exits the system from standby state thru the normal path
+ */
+
+func _psci_sys_exit_stdby
+ stp x4, x5, [sp, #-16]!
+ stp x6, x30, [sp, #-16]!
+
+ mov x5, x0
+
+ /* x5 = core mask */
+
+ /* restore scr_el3 */
+ mov x0, x5
+ mov x1, #SCR_EL3_DATA
+ bl _getCoreData
+ /* x0 = saved scr_el3 */
+ msr SCR_EL3, x0
+
+ /* x5 = core mask */
+
+ /* perform any SoC-specific programming after standby state */
+ mov x0, x5
+ bl _soc_sys_exit_stdby
+
+ ldp x6, x30, [sp], #16
+ ldp x4, x5, [sp], #16
+ isb
+ ret
+endfunc _psci_sys_exit_stdby
+
+#endif
+
+#if (SOC_SYSTEM_PWR_DWN)
+
+.global _psci_sys_prep_pwrdn
+.global _psci_sys_pwrdn_wfi
+.global _psci_sys_exit_pwrdn
+
+/*
+ * void _psci_sys_prep_pwrdn_(u_register_t core_mask)
+ * this function prepares the system+core for power-down
+ * x0 = core mask
+ *
+ * called from C, so save the non-volatile regs
+ * save these as pairs of registers to maintain the
+ * required 16-byte alignment on the stack
+ */
+
+func _psci_sys_prep_pwrdn
+ stp x4, x5, [sp, #-16]!
+ stp x6, x7, [sp, #-16]!
+ stp x8, x9, [sp, #-16]!
+ stp x10, x11, [sp, #-16]!
+ stp x12, x13, [sp, #-16]!
+ stp x14, x15, [sp, #-16]!
+ stp x16, x17, [sp, #-16]!
+ stp x18, x30, [sp, #-16]!
+
+ mov x6, x0 /* x6 = core mask */
+
+ /* mask interrupts by setting DAIF[7:4] to 'b1111 */
+ msr DAIFSet, #0xF
+
+ /* save scr_el3 */
+ mov x0, x6
+ mrs x4, SCR_EL3
+ mov x2, x4
+ mov x1, #SCR_EL3_DATA
+ bl _setCoreData
+
+ /* allow interrupts @ EL3 */
+ orr x4, x4, #(SCR_IRQ_MASK | SCR_FIQ_MASK)
+ msr SCR_EL3, x4
+
+ /* save cpuectlr */
+ mov x0, x6
+ mov x1, #CPUECTLR_DATA
+ mrs x2, CORTEX_A72_ECTLR_EL1
+ mov x4, x2
+ bl _setCoreData
+
+ /* remove core from coherency */
+ bic x4, x4, #CPUECTLR_SMPEN_MASK
+ msr CORTEX_A72_ECTLR_EL1, x4
+
+ /* x6 = core mask */
+
+ /* SoC-specific programming for power-down */
+ mov x0, x6
+ bl _soc_sys_prep_pwrdn
+
+ /* restore the aarch32/64 non-volatile registers
+ */
+ ldp x18, x30, [sp], #16
+ ldp x16, x17, [sp], #16
+ ldp x14, x15, [sp], #16
+ ldp x12, x13, [sp], #16
+ ldp x10, x11, [sp], #16
+ ldp x8, x9, [sp], #16
+ ldp x6, x7, [sp], #16
+ ldp x4, x5, [sp], #16
+ b psci_completed
+endfunc _psci_sys_prep_pwrdn
+
+
+/*
+ * void _psci_sys_pwrdn_wfi(u_register_t core_mask, u_register_t resume_addr)
+ * this function powers down the system
+ */
+
+func _psci_sys_pwrdn_wfi
+ /* save the wakeup address */
+ mov x29, x1
+
+ /* x0 = core mask */
+
+ /* shutdown the system */
+ bl _soc_sys_pwrdn_wfi
+
+ /* branch to resume execution */
+ br x29
+endfunc _psci_sys_pwrdn_wfi
+
+/*
+ * void _psci_sys_exit_pwrdn_(u_register_t core_mask)
+ * this function cleans up after a system power-down
+ * x0 = core mask
+ *
+ * Called from C, so save the non-volatile regs
+ * save these as pairs of registers to maintain the
+ * required 16-byte alignment on the stack
+ */
+
+func _psci_sys_exit_pwrdn
+
+ stp x4, x5, [sp, #-16]!
+ stp x6, x7, [sp, #-16]!
+ stp x8, x9, [sp, #-16]!
+ stp x10, x11, [sp, #-16]!
+ stp x12, x13, [sp, #-16]!
+ stp x14, x15, [sp, #-16]!
+ stp x16, x17, [sp, #-16]!
+ stp x18, x30, [sp, #-16]!
+
+ mov x4, x0 /* x4 = core mask */
+
+ /* restore scr_el3 */
+ mov x0, x4
+ mov x1, #SCR_EL3_DATA
+ bl _getCoreData
+
+ /* x0 = saved scr_el3 */
+ msr SCR_EL3, x0
+
+ /* x4 = core mask */
+
+ /* restore cpuectlr */
+ mov x0, x4
+ mov x1, #CPUECTLR_DATA
+ bl _getCoreData
+
+ /* make sure smp is set */
+ orr x0, x0, #CPUECTLR_SMPEN_MASK
+ msr CORTEX_A72_ECTLR_EL1, x0
+
+ /* x4 = core mask */
+
+ /* SoC-specific cleanup */
+ mov x0, x4
+ bl _soc_sys_exit_pwrdn
+
+ /* restore the aarch32/64 non-volatile registers
+ */
+ ldp x18, x30, [sp], #16
+ ldp x16, x17, [sp], #16
+ ldp x14, x15, [sp], #16
+ ldp x12, x13, [sp], #16
+ ldp x10, x11, [sp], #16
+ ldp x8, x9, [sp], #16
+ ldp x6, x7, [sp], #16
+ ldp x4, x5, [sp], #16
+ b psci_completed
+endfunc _psci_sys_exit_pwrdn
+
+#endif
+
+
+/* psci std returns */
+func psci_disabled
+ ldr w0, =PSCI_E_DISABLED
+ b psci_completed
+endfunc psci_disabled
+
+
+func psci_not_present
+ ldr w0, =PSCI_E_NOT_PRESENT
+ b psci_completed
+endfunc psci_not_present
+
+
+func psci_on_pending
+ ldr w0, =PSCI_E_ON_PENDING
+ b psci_completed
+endfunc psci_on_pending
+
+
+func psci_already_on
+ ldr w0, =PSCI_E_ALREADY_ON
+ b psci_completed
+endfunc psci_already_on
+
+
+func psci_failure
+ ldr w0, =PSCI_E_INTERN_FAIL
+ b psci_completed
+endfunc psci_failure
+
+
+func psci_unimplemented
+ ldr w0, =PSCI_E_NOT_SUPPORTED
+ b psci_completed
+endfunc psci_unimplemented
+
+
+func psci_denied
+ ldr w0, =PSCI_E_DENIED
+ b psci_completed
+endfunc psci_denied
+
+
+func psci_invalid
+ ldr w0, =PSCI_E_INVALID_PARAMS
+ b psci_completed
+endfunc psci_invalid
+
+
+func psci_success
+ mov x0, #PSCI_E_SUCCESS
+endfunc psci_success
+
+
+func psci_completed
+ /* x0 = status code */
+ ret
+endfunc psci_completed
diff --git a/plat/nxp/common/psci/include/plat_psci.h b/plat/nxp/common/psci/include/plat_psci.h
new file mode 100644
index 0000000..97d4c97
--- /dev/null
+++ b/plat/nxp/common/psci/include/plat_psci.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PLAT_PSCI_H
+#define PLAT_PSCI_H
+
+ /* core abort current op */
+#define CORE_ABORT_OP 0x1
+
+ /* psci power levels - these are actually affinity levels
+ * in the psci_power_state_t array
+ */
+#define PLAT_CORE_LVL PSCI_CPU_PWR_LVL
+#define PLAT_CLSTR_LVL U(1)
+#define PLAT_SYS_LVL U(2)
+#define PLAT_MAX_LVL PLAT_SYS_LVL
+
+ /* core state */
+ /* OFF states 0x0 - 0xF */
+#define CORE_IN_RESET 0x0
+#define CORE_DISABLED 0x1
+#define CORE_OFF 0x2
+#define CORE_STANDBY 0x3
+#define CORE_PWR_DOWN 0x4
+#define CORE_WFE 0x6
+#define CORE_WFI 0x7
+#define CORE_LAST 0x8
+#define CORE_OFF_PENDING 0x9
+#define CORE_WORKING_INIT 0xA
+#define SYS_OFF_PENDING 0xB
+#define SYS_OFF 0xC
+
+ /* ON states 0x10 - 0x1F */
+#define CORE_PENDING 0x10
+#define CORE_RELEASED 0x11
+#define CORE_WAKEUP 0x12
+ /* highest off state */
+#define CORE_OFF_MAX 0xF
+ /* lowest on state */
+#define CORE_ON_MIN CORE_PENDING
+
+#define DAIF_SET_MASK 0x3C0
+#define SCTLR_I_C_M_MASK 0x00001005
+#define SCTLR_C_MASK 0x00000004
+#define SCTLR_I_MASK 0x00001000
+#define CPUACTLR_L1PCTL_MASK 0x0000E000
+#define DCSR_RCPM2_BASE 0x20170000
+#define CPUECTLR_SMPEN_MASK 0x40
+#define CPUECTLR_SMPEN_EN 0x40
+#define CPUECTLR_RET_MASK 0x7
+#define CPUECTLR_RET_SET 0x2
+#define CPUECTLR_TIMER_MASK 0x7
+#define CPUECTLR_TIMER_8TICKS 0x2
+#define SCR_IRQ_MASK 0x2
+#define SCR_FIQ_MASK 0x4
+
+/* pwr mgmt features supported in the soc-specific code:
+ * value == 0x0, the soc code does not support this feature
+ * value != 0x0, the soc code supports this feature
+ */
+#define SOC_CORE_RELEASE 0x1
+#define SOC_CORE_RESTART 0x1
+#define SOC_CORE_OFF 0x1
+#define SOC_CORE_STANDBY 0x1
+#define SOC_CORE_PWR_DWN 0x1
+#define SOC_CLUSTER_STANDBY 0x1
+#define SOC_CLUSTER_PWR_DWN 0x1
+#define SOC_SYSTEM_STANDBY 0x1
+#define SOC_SYSTEM_PWR_DWN 0x1
+#define SOC_SYSTEM_OFF 0x1
+#define SOC_SYSTEM_RESET 0x1
+#define SOC_SYSTEM_RESET2 0x1
+
+#ifndef __ASSEMBLER__
+
+void __dead2 _psci_system_reset(void);
+void __dead2 _psci_system_off(void);
+int _psci_cpu_on(u_register_t core_mask);
+void _psci_cpu_prep_off(u_register_t core_mask);
+void __dead2 _psci_cpu_off_wfi(u_register_t core_mask,
+ u_register_t wakeup_address);
+void __dead2 _psci_cpu_pwrdn_wfi(u_register_t core_mask,
+ u_register_t wakeup_address);
+void __dead2 _psci_sys_pwrdn_wfi(u_register_t core_mask,
+ u_register_t wakeup_address);
+void _psci_wakeup(u_register_t core_mask);
+void _psci_core_entr_stdby(u_register_t core_mask);
+void _psci_core_prep_stdby(u_register_t core_mask);
+void _psci_core_exit_stdby(u_register_t core_mask);
+void _psci_core_prep_pwrdn(u_register_t core_mask);
+void _psci_core_exit_pwrdn(u_register_t core_mask);
+void _psci_clstr_prep_stdby(u_register_t core_mask);
+void _psci_clstr_exit_stdby(u_register_t core_mask);
+void _psci_clstr_prep_pwrdn(u_register_t core_mask);
+void _psci_clstr_exit_pwrdn(u_register_t core_mask);
+void _psci_sys_prep_stdby(u_register_t core_mask);
+void _psci_sys_exit_stdby(u_register_t core_mask);
+void _psci_sys_prep_pwrdn(u_register_t core_mask);
+void _psci_sys_exit_pwrdn(u_register_t core_mask);
+
+#endif
+
+#endif /* __PLAT_PSCI_H__ */
diff --git a/plat/nxp/common/psci/plat_psci.c b/plat/nxp/common/psci/plat_psci.c
new file mode 100644
index 0000000..9281e97
--- /dev/null
+++ b/plat/nxp/common/psci/plat_psci.c
@@ -0,0 +1,475 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <common/debug.h>
+
+#include <plat_gic.h>
+#include <plat_common.h>
+#include <plat_psci.h>
+#ifdef NXP_WARM_BOOT
+#include <plat_warm_rst.h>
+#endif
+
+#include <platform_def.h>
+
+#if (SOC_CORE_OFF || SOC_CORE_PWR_DWN)
+static void __dead2 _no_return_wfi(void)
+{
+_bl31_dead_wfi:
+ wfi();
+ goto _bl31_dead_wfi;
+}
+#endif
+
+#if (SOC_CORE_RELEASE || SOC_CORE_PWR_DWN)
+ /* the entry for core warm boot */
+static uintptr_t warmboot_entry = (uintptr_t) NULL;
+#endif
+
+#if (SOC_CORE_RELEASE)
+static int _pwr_domain_on(u_register_t mpidr)
+{
+ int core_pos = plat_core_pos(mpidr);
+ int rc = PSCI_E_INVALID_PARAMS;
+ u_register_t core_mask;
+
+ if (core_pos >= 0 && core_pos < PLATFORM_CORE_COUNT) {
+
+ _soc_set_start_addr(warmboot_entry);
+
+ dsb();
+ isb();
+
+ core_mask = (1 << core_pos);
+ rc = _psci_cpu_on(core_mask);
+ }
+
+ return (rc);
+}
+#endif
+
+#if (SOC_CORE_OFF)
+static void _pwr_domain_off(const psci_power_state_t *target_state)
+{
+ u_register_t core_mask = plat_my_core_mask();
+ u_register_t core_state = _getCoreState(core_mask);
+
+ /* set core state in internal data */
+ core_state = CORE_OFF_PENDING;
+ _setCoreState(core_mask, core_state);
+
+ _psci_cpu_prep_off(core_mask);
+}
+#endif
+
+#if (SOC_CORE_OFF || SOC_CORE_PWR_DWN)
+static void __dead2 _pwr_down_wfi(const psci_power_state_t *target_state)
+{
+ u_register_t core_mask = plat_my_core_mask();
+ u_register_t core_state = _getCoreState(core_mask);
+
+ switch (core_state) {
+#if (SOC_CORE_OFF)
+ case CORE_OFF_PENDING:
+ /* set core state in internal data */
+ core_state = CORE_OFF;
+ _setCoreState(core_mask, core_state);
+
+ /* turn the core off */
+ _psci_cpu_off_wfi(core_mask, warmboot_entry);
+ break;
+#endif
+#if (SOC_CORE_PWR_DWN)
+ case CORE_PWR_DOWN:
+ /* power-down the core */
+ _psci_cpu_pwrdn_wfi(core_mask, warmboot_entry);
+ break;
+#endif
+#if (SOC_SYSTEM_PWR_DWN)
+ case SYS_OFF_PENDING:
+ /* set core state in internal data */
+ core_state = SYS_OFF;
+ _setCoreState(core_mask, core_state);
+
+ /* power-down the system */
+ _psci_sys_pwrdn_wfi(core_mask, warmboot_entry);
+ break;
+#endif
+ default:
+ _no_return_wfi();
+ break;
+ }
+}
+#endif
+
+#if (SOC_CORE_RELEASE || SOC_CORE_RESTART)
+static void _pwr_domain_wakeup(const psci_power_state_t *target_state)
+{
+ u_register_t core_mask = plat_my_core_mask();
+ u_register_t core_state = _getCoreState(core_mask);
+
+ switch (core_state) {
+ case CORE_PENDING: /* this core is coming out of reset */
+
+ /* soc per cpu setup */
+ soc_init_percpu();
+
+ /* gic per cpu setup */
+ plat_gic_pcpu_init();
+
+ /* set core state in internal data */
+ core_state = CORE_RELEASED;
+ _setCoreState(core_mask, core_state);
+ break;
+
+#if (SOC_CORE_RESTART)
+ case CORE_WAKEUP:
+
+ /* this core is waking up from OFF */
+ _psci_wakeup(core_mask);
+
+ /* set core state in internal data */
+ core_state = CORE_RELEASED;
+ _setCoreState(core_mask, core_state);
+
+ break;
+#endif
+ }
+}
+#endif
+
+#if (SOC_CORE_STANDBY)
+static void _pwr_cpu_standby(plat_local_state_t cpu_state)
+{
+ u_register_t core_mask = plat_my_core_mask();
+ u_register_t core_state;
+
+ if (cpu_state == PLAT_MAX_RET_STATE) {
+
+ /* set core state to standby */
+ core_state = CORE_STANDBY;
+ _setCoreState(core_mask, core_state);
+
+ _psci_core_entr_stdby(core_mask);
+
+ /* when we are here, the core is waking up
+ * set core state to released
+ */
+ core_state = CORE_RELEASED;
+ _setCoreState(core_mask, core_state);
+ }
+}
+#endif
+
+#if (SOC_CORE_PWR_DWN)
+static void _pwr_suspend(const psci_power_state_t *state)
+{
+
+ u_register_t core_mask = plat_my_core_mask();
+ u_register_t core_state;
+
+ if (state->pwr_domain_state[PLAT_MAX_LVL] == PLAT_MAX_OFF_STATE) {
+#if (SOC_SYSTEM_PWR_DWN)
+ _psci_sys_prep_pwrdn(core_mask);
+
+ /* set core state */
+ core_state = SYS_OFF_PENDING;
+ _setCoreState(core_mask, core_state);
+#endif
+ } else if (state->pwr_domain_state[PLAT_MAX_LVL]
+ == PLAT_MAX_RET_STATE) {
+#if (SOC_SYSTEM_STANDBY)
+ _psci_sys_prep_stdby(core_mask);
+
+ /* set core state */
+ core_state = CORE_STANDBY;
+ _setCoreState(core_mask, core_state);
+#endif
+ }
+
+ else if (state->pwr_domain_state[PLAT_CLSTR_LVL] ==
+ PLAT_MAX_OFF_STATE) {
+#if (SOC_CLUSTER_PWR_DWN)
+ _psci_clstr_prep_pwrdn(core_mask);
+
+ /* set core state */
+ core_state = CORE_PWR_DOWN;
+ _setCoreState(core_mask, core_state);
+#endif
+ }
+
+ else if (state->pwr_domain_state[PLAT_CLSTR_LVL] ==
+ PLAT_MAX_RET_STATE) {
+#if (SOC_CLUSTER_STANDBY)
+ _psci_clstr_prep_stdby(core_mask);
+
+ /* set core state */
+ core_state = CORE_STANDBY;
+ _setCoreState(core_mask, core_state);
+#endif
+ }
+
+ else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_OFF_STATE) {
+#if (SOC_CORE_PWR_DWN)
+ /* prep the core for power-down */
+ _psci_core_prep_pwrdn(core_mask);
+
+ /* set core state */
+ core_state = CORE_PWR_DOWN;
+ _setCoreState(core_mask, core_state);
+#endif
+ }
+
+ else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_RET_STATE) {
+#if (SOC_CORE_STANDBY)
+ _psci_core_prep_stdby(core_mask);
+
+ /* set core state */
+ core_state = CORE_STANDBY;
+ _setCoreState(core_mask, core_state);
+#endif
+ }
+
+}
+#endif
+
+#if (SOC_CORE_PWR_DWN)
+static void _pwr_suspend_finish(const psci_power_state_t *state)
+{
+
+ u_register_t core_mask = plat_my_core_mask();
+ u_register_t core_state;
+
+
+ if (state->pwr_domain_state[PLAT_MAX_LVL] == PLAT_MAX_OFF_STATE) {
+#if (SOC_SYSTEM_PWR_DWN)
+ _psci_sys_exit_pwrdn(core_mask);
+
+ /* when we are here, the core is back up
+ * set core state to released
+ */
+ core_state = CORE_RELEASED;
+ _setCoreState(core_mask, core_state);
+#endif
+ } else if (state->pwr_domain_state[PLAT_MAX_LVL]
+ == PLAT_MAX_RET_STATE) {
+#if (SOC_SYSTEM_STANDBY)
+ _psci_sys_exit_stdby(core_mask);
+
+ /* when we are here, the core is waking up
+ * set core state to released
+ */
+ core_state = CORE_RELEASED;
+ _setCoreState(core_mask, core_state);
+#endif
+ }
+
+ else if (state->pwr_domain_state[PLAT_CLSTR_LVL] ==
+ PLAT_MAX_OFF_STATE) {
+#if (SOC_CLUSTER_PWR_DWN)
+ _psci_clstr_exit_pwrdn(core_mask);
+
+ /* when we are here, the core is waking up
+ * set core state to released
+ */
+ core_state = CORE_RELEASED;
+ _setCoreState(core_mask, core_state);
+#endif
+ }
+
+ else if (state->pwr_domain_state[PLAT_CLSTR_LVL] ==
+ PLAT_MAX_RET_STATE) {
+#if (SOC_CLUSTER_STANDBY)
+ _psci_clstr_exit_stdby(core_mask);
+
+ /* when we are here, the core is waking up
+ * set core state to released
+ */
+ core_state = CORE_RELEASED;
+ _setCoreState(core_mask, core_state);
+#endif
+ }
+
+ else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_OFF_STATE) {
+#if (SOC_CORE_PWR_DWN)
+ _psci_core_exit_pwrdn(core_mask);
+
+ /* when we are here, the core is back up
+ * set core state to released
+ */
+ core_state = CORE_RELEASED;
+ _setCoreState(core_mask, core_state);
+#endif
+ }
+
+ else if (state->pwr_domain_state[PLAT_CORE_LVL] == PLAT_MAX_RET_STATE) {
+#if (SOC_CORE_STANDBY)
+ _psci_core_exit_stdby(core_mask);
+
+ /* when we are here, the core is waking up
+ * set core state to released
+ */
+ core_state = CORE_RELEASED;
+ _setCoreState(core_mask, core_state);
+#endif
+ }
+
+}
+#endif
+
+#if (SOC_CORE_STANDBY || SOC_CORE_PWR_DWN)
+
+#define PWR_STATE_TYPE_MASK 0x00010000
+#define PWR_STATE_TYPE_STNDBY 0x0
+#define PWR_STATE_TYPE_PWRDWN 0x00010000
+#define PWR_STATE_LVL_MASK 0x03000000
+#define PWR_STATE_LVL_CORE 0x0
+#define PWR_STATE_LVL_CLSTR 0x01000000
+#define PWR_STATE_LVL_SYS 0x02000000
+#define PWR_STATE_LVL_MAX 0x03000000
+
+ /* turns a requested power state into a target power state
+ * based on SoC capabilities
+ */
+static int _pwr_state_validate(uint32_t pwr_state,
+ psci_power_state_t *state)
+{
+ int stat = PSCI_E_INVALID_PARAMS;
+ int pwrdn = (pwr_state & PWR_STATE_TYPE_MASK);
+ int lvl = (pwr_state & PWR_STATE_LVL_MASK);
+
+ switch (lvl) {
+ case PWR_STATE_LVL_MAX:
+ if (pwrdn && SOC_SYSTEM_PWR_DWN)
+ state->pwr_domain_state[PLAT_MAX_LVL] =
+ PLAT_MAX_OFF_STATE;
+ else if (SOC_SYSTEM_STANDBY)
+ state->pwr_domain_state[PLAT_MAX_LVL] =
+ PLAT_MAX_RET_STATE;
+ /* intentional fall-thru condition */
+ case PWR_STATE_LVL_SYS:
+ if (pwrdn && SOC_SYSTEM_PWR_DWN)
+ state->pwr_domain_state[PLAT_SYS_LVL] =
+ PLAT_MAX_OFF_STATE;
+ else if (SOC_SYSTEM_STANDBY)
+ state->pwr_domain_state[PLAT_SYS_LVL] =
+ PLAT_MAX_RET_STATE;
+ /* intentional fall-thru condition */
+ case PWR_STATE_LVL_CLSTR:
+ if (pwrdn && SOC_CLUSTER_PWR_DWN)
+ state->pwr_domain_state[PLAT_CLSTR_LVL] =
+ PLAT_MAX_OFF_STATE;
+ else if (SOC_CLUSTER_STANDBY)
+ state->pwr_domain_state[PLAT_CLSTR_LVL] =
+ PLAT_MAX_RET_STATE;
+ /* intentional fall-thru condition */
+ case PWR_STATE_LVL_CORE:
+ stat = PSCI_E_SUCCESS;
+
+ if (pwrdn && SOC_CORE_PWR_DWN)
+ state->pwr_domain_state[PLAT_CORE_LVL] =
+ PLAT_MAX_OFF_STATE;
+ else if (SOC_CORE_STANDBY)
+ state->pwr_domain_state[PLAT_CORE_LVL] =
+ PLAT_MAX_RET_STATE;
+ break;
+ }
+ return (stat);
+}
+
+#endif
+
+#if (SOC_SYSTEM_PWR_DWN)
+static void _pwr_state_sys_suspend(psci_power_state_t *req_state)
+{
+
+ /* if we need to have per-SoC settings, then we need to
+ * extend this by calling into psci_utils.S and from there
+ * on down to the SoC.S files
+ */
+
+ req_state->pwr_domain_state[PLAT_MAX_LVL] = PLAT_MAX_OFF_STATE;
+ req_state->pwr_domain_state[PLAT_SYS_LVL] = PLAT_MAX_OFF_STATE;
+ req_state->pwr_domain_state[PLAT_CLSTR_LVL] = PLAT_MAX_OFF_STATE;
+ req_state->pwr_domain_state[PLAT_CORE_LVL] = PLAT_MAX_OFF_STATE;
+
+}
+#endif
+
+#if defined(NXP_WARM_BOOT) && (SOC_SYSTEM_RESET2)
+static int psci_system_reset2(int is_vendor,
+ int reset_type,
+ u_register_t cookie)
+{
+ int ret = 0;
+
+ INFO("Executing the sequence of warm reset.\n");
+ ret = prep_n_execute_warm_reset();
+
+ return ret;
+}
+#endif
+
+static plat_psci_ops_t _psci_pm_ops = {
+#if (SOC_SYSTEM_OFF)
+ .system_off = _psci_system_off,
+#endif
+#if (SOC_SYSTEM_RESET)
+ .system_reset = _psci_system_reset,
+#endif
+#if defined(NXP_WARM_BOOT) && (SOC_SYSTEM_RESET2)
+ .system_reset2 = psci_system_reset2,
+#endif
+#if (SOC_CORE_RELEASE || SOC_CORE_RESTART)
+ /* core released or restarted */
+ .pwr_domain_on_finish = _pwr_domain_wakeup,
+#endif
+#if (SOC_CORE_OFF)
+ /* core shutting down */
+ .pwr_domain_off = _pwr_domain_off,
+#endif
+#if (SOC_CORE_OFF || SOC_CORE_PWR_DWN)
+ .pwr_domain_pwr_down_wfi = _pwr_down_wfi,
+#endif
+#if (SOC_CORE_STANDBY || SOC_CORE_PWR_DWN)
+ /* cpu_suspend */
+ .validate_power_state = _pwr_state_validate,
+#if (SOC_CORE_STANDBY)
+ .cpu_standby = _pwr_cpu_standby,
+#endif
+#if (SOC_CORE_PWR_DWN)
+ .pwr_domain_suspend = _pwr_suspend,
+ .pwr_domain_suspend_finish = _pwr_suspend_finish,
+#endif
+#endif
+#if (SOC_SYSTEM_PWR_DWN)
+ .get_sys_suspend_power_state = _pwr_state_sys_suspend,
+#endif
+#if (SOC_CORE_RELEASE)
+ /* core executing psci_cpu_on */
+ .pwr_domain_on = _pwr_domain_on
+#endif
+};
+
+#if (SOC_CORE_RELEASE || SOC_CORE_PWR_DWN)
+int plat_setup_psci_ops(uintptr_t sec_entrypoint,
+ const plat_psci_ops_t **psci_ops)
+{
+ warmboot_entry = sec_entrypoint;
+ *psci_ops = &_psci_pm_ops;
+ return 0;
+}
+
+#else
+
+int plat_setup_psci_ops(uintptr_t sec_entrypoint,
+ const plat_psci_ops_t **psci_ops)
+{
+ *psci_ops = &_psci_pm_ops;
+ return 0;
+}
+#endif
diff --git a/plat/nxp/common/psci/psci.mk b/plat/nxp/common/psci/psci.mk
new file mode 100644
index 0000000..a2791c2
--- /dev/null
+++ b/plat/nxp/common/psci/psci.mk
@@ -0,0 +1,35 @@
+#
+# Copyright 2018-2020 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+#------------------------------------------------------------------------------
+#
+# Select the PSCI files
+#
+# -----------------------------------------------------------------------------
+
+ifeq (${ADD_PSCI},)
+
+ADD_PSCI := 1
+PLAT_PSCI_PATH := $(PLAT_COMMON_PATH)/psci
+
+PSCI_SOURCES := ${PLAT_PSCI_PATH}/plat_psci.c \
+ ${PLAT_PSCI_PATH}/$(ARCH)/psci_utils.S \
+ plat/common/plat_psci_common.c
+
+PLAT_INCLUDES += -I${PLAT_PSCI_PATH}/include
+
+ifeq (${BL_COMM_PSCI_NEEDED},yes)
+BL_COMMON_SOURCES += ${PSCI_SOURCES}
+else
+ifeq (${BL2_PSCI_NEEDED},yes)
+BL2_SOURCES += ${PSCI_SOURCES}
+endif
+ifeq (${BL31_PSCI_NEEDED},yes)
+BL31_SOURCES += ${PSCI_SOURCES}
+endif
+endif
+endif
+# -----------------------------------------------------------------------------
diff --git a/plat/nxp/common/setup/aarch64/ls_bl2_mem_params_desc.c b/plat/nxp/common/setup/aarch64/ls_bl2_mem_params_desc.c
new file mode 100644
index 0000000..7463d47
--- /dev/null
+++ b/plat/nxp/common/setup/aarch64/ls_bl2_mem_params_desc.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <common/bl_common.h>
+#include <common/desc_image_load.h>
+#ifdef CSF_HEADER_PREPENDED
+#include <csf_hdr.h>
+#endif
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+/*******************************************************************************
+ * Following descriptor provides BL image/ep information that gets used
+ * by BL2 to load the images and also subset of this information is
+ * passed to next BL image. The image loading sequence is managed by
+ * populating the images in required loading order. The image execution
+ * sequence is managed by populating the `next_handoff_image_id` with
+ * the next executable image id.
+ ******************************************************************************/
+static bl_mem_params_node_t bl2_mem_params_descs[] = {
+ /* Fill BL31 related information */
+ {
+ .image_id = BL31_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t,
+ SECURE | EXECUTABLE | EP_FIRST_EXE),
+ .ep_info.pc = BL31_BASE,
+ .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
+ DISABLE_ALL_EXCEPTIONS),
+#if DEBUG
+ .ep_info.args.arg1 = LS_BL31_PLAT_PARAM_VAL,
+#endif
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
+#ifdef CSF_HEADER_PREPENDED
+ .image_info.image_base = BL31_BASE - CSF_HDR_SZ,
+ .image_info.image_max_size = (BL31_LIMIT - BL31_BASE) +
+ CSF_HDR_SZ,
+#else
+ .image_info.image_base = BL31_BASE,
+ .image_info.image_max_size = (BL31_LIMIT - BL31_BASE),
+#endif
+
+# ifdef NXP_LOAD_BL32
+ .next_handoff_image_id = BL32_IMAGE_ID,
+# else
+ .next_handoff_image_id = BL33_IMAGE_ID,
+# endif
+ },
+# ifdef NXP_LOAD_BL32
+ /* Fill BL32 related information */
+ {
+ .image_id = BL32_IMAGE_ID,
+
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
+ .ep_info.pc = BL32_BASE,
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, 0),
+#ifdef CSF_HEADER_PREPENDED
+ .image_info.image_base = BL32_BASE - CSF_HDR_SZ,
+ .image_info.image_max_size = (BL32_LIMIT - BL32_BASE) +
+ CSF_HDR_SZ,
+#else
+ .image_info.image_base = BL32_BASE,
+ .image_info.image_max_size = (BL32_LIMIT - BL32_BASE),
+#endif
+ .next_handoff_image_id = BL33_IMAGE_ID,
+ },
+# endif /* BL32_BASE */
+
+ /* Fill BL33 related information */
+ {
+ .image_id = BL33_IMAGE_ID,
+ SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
+ VERSION_2, entry_point_info_t, NON_SECURE | EXECUTABLE),
+ .ep_info.pc = BL33_BASE,
+
+ SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
+ VERSION_2, image_info_t, 0),
+#ifdef CSF_HEADER_PREPENDED
+ .image_info.image_base = BL33_BASE - CSF_HDR_SZ,
+ .image_info.image_max_size = (BL33_LIMIT - BL33_BASE) +
+ CSF_HDR_SZ,
+#else
+ .image_info.image_base = BL33_BASE,
+ .image_info.image_max_size = BL33_LIMIT - BL33_BASE,
+#endif
+ .ep_info.spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
+ DISABLE_ALL_EXCEPTIONS),
+
+ .next_handoff_image_id = INVALID_IMAGE_ID,
+ }
+};
+
+REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs)
diff --git a/plat/nxp/common/setup/common.mk b/plat/nxp/common/setup/common.mk
new file mode 100644
index 0000000..1fcf1d0
--- /dev/null
+++ b/plat/nxp/common/setup/common.mk
@@ -0,0 +1,105 @@
+#
+# Copyright 2018-2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+
+###############################################################################
+# Flow begins in BL2 at EL3 mode
+BL2_AT_EL3 := 1
+
+# Though one core is powered up by default, there are
+# platform specific ways to release more than one core
+COLD_BOOT_SINGLE_CPU := 0
+
+PROGRAMMABLE_RESET_ADDRESS := 1
+
+USE_COHERENT_MEM := 0
+
+# Use generic OID definition (tbbr_oid.h)
+USE_TBBR_DEFS := 1
+
+PLAT_XLAT_TABLES_DYNAMIC := 0
+
+ENABLE_SVE_FOR_NS := 0
+
+ENABLE_STACK_PROTECTOR := 0
+
+ERROR_DEPRECATED := 0
+
+LS_DISABLE_TRUSTED_WDOG := 1
+
+# On ARM platforms, separate the code and read-only data sections to allow
+# mapping the former as executable and the latter as execute-never.
+SEPARATE_CODE_AND_RODATA := 1
+
+# Enable new version of image loading on ARM platforms
+LOAD_IMAGE_V2 := 1
+
+RCW := ""
+
+ifneq (${SPD},none)
+$(eval $(call add_define, NXP_LOAD_BL32))
+endif
+
+###############################################################################
+
+PLAT_TOOL_PATH := tools/nxp
+CREATE_PBL_TOOL_PATH := ${PLAT_TOOL_PATH}/create_pbl
+PLAT_SETUP_PATH := ${PLAT_PATH}/common/setup
+
+PLAT_INCLUDES += -I${PLAT_SETUP_PATH}/include \
+ -Iinclude/plat/arm/common \
+ -Iinclude/drivers/arm \
+ -Iinclude/lib \
+ -Iinclude/drivers/io \
+ -Ilib/psci
+
+# Required without TBBR.
+# To include the defines for DDR PHY Images.
+PLAT_INCLUDES += -Iinclude/common/tbbr
+
+include ${PLAT_SETUP_PATH}/core.mk
+PLAT_BL_COMMON_SOURCES += ${CPU_LIBS} \
+ plat/nxp/common/setup/ls_err.c \
+ plat/nxp/common/setup/ls_common.c
+
+ifneq (${ENABLE_STACK_PROTECTOR},0)
+PLAT_BL_COMMON_SOURCES += ${PLAT_SETUP_PATH}/ls_stack_protector.c
+endif
+
+include lib/xlat_tables_v2/xlat_tables.mk
+
+PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
+
+BL2_SOURCES += drivers/io/io_fip.c \
+ drivers/io/io_memmap.c \
+ drivers/io/io_storage.c \
+ common/desc_image_load.c \
+ plat/nxp/common/setup/ls_image_load.c \
+ plat/nxp/common/setup/ls_io_storage.c \
+ plat/nxp/common/setup/ls_bl2_el3_setup.c \
+ plat/nxp/common/setup/${ARCH}/ls_bl2_mem_params_desc.c
+
+BL31_SOURCES += plat/nxp/common/setup/ls_bl31_setup.c \
+
+ifeq (${LS_EL3_INTERRUPT_HANDLER}, yes)
+$(eval $(call add_define, LS_EL3_INTERRUPT_HANDLER))
+BL31_SOURCES += plat/nxp/common/setup/ls_interrupt_mgmt.c
+endif
+
+ifeq (${TEST_BL31}, 1)
+BL31_SOURCES += ${TEST_SOURCES}
+endif
+
+# Verify build config
+# -------------------
+
+ifneq (${LOAD_IMAGE_V2}, 1)
+ $(error Error: Layerscape needs LOAD_IMAGE_V2=1)
+else
+$(eval $(call add_define,LOAD_IMAGE_V2))
+endif
+
+include $(CREATE_PBL_TOOL_PATH)/create_pbl.mk
diff --git a/plat/nxp/common/setup/core.mk b/plat/nxp/common/setup/core.mk
new file mode 100644
index 0000000..9b81f2d
--- /dev/null
+++ b/plat/nxp/common/setup/core.mk
@@ -0,0 +1,20 @@
+# Copyright 2018-2020 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+#------------------------------------------------------------------------------
+#
+# Select the CORE files
+#
+# -----------------------------------------------------------------------------
+
+CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
+
+ifeq (,$(filter $(CORE_TYPE),a53 a55 a57 a72 a75))
+$(error "CORE_TYPE not specified or incorrect")
+else
+CPU_LIBS += lib/cpus/${ARCH}/cortex_$(CORE_TYPE).S
+endif
+
+# -----------------------------------------------------------------------------
diff --git a/plat/nxp/common/setup/include/bl31_data.h b/plat/nxp/common/setup/include/bl31_data.h
new file mode 100644
index 0000000..dd20d43
--- /dev/null
+++ b/plat/nxp/common/setup/include/bl31_data.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef BL31_DATA_H
+#define BL31_DATA_H
+
+#define SECURE_DATA_BASE NXP_OCRAM_ADDR
+#define SECURE_DATA_SIZE NXP_OCRAM_SIZE
+#define SECURE_DATA_TOP (SECURE_DATA_BASE + SECURE_DATA_SIZE)
+#define SMC_REGION_SIZE 0x80
+#define SMC_GLBL_BASE (SECURE_DATA_TOP - SMC_REGION_SIZE)
+#define BC_PSCI_DATA_SIZE 0xC0
+#define BC_PSCI_BASE (SMC_GLBL_BASE - BC_PSCI_DATA_SIZE)
+#define SECONDARY_TOP BC_PSCI_BASE
+
+#define SEC_PSCI_DATA_SIZE 0xC0
+#define SEC_REGION_SIZE SEC_PSCI_DATA_SIZE
+
+/* SMC global data */
+#define BOOTLOC_OFFSET 0x0
+#define BOOT_SVCS_OSET 0x8
+
+/* offset to prefetch disable mask */
+#define PREFETCH_DIS_OFFSET 0x10
+/* must reference last smc global entry */
+#define LAST_SMC_GLBL_OFFSET 0x18
+
+#define SMC_TASK_OFFSET 0xC
+#define TSK_START_OFFSET 0x0
+#define TSK_DONE_OFFSET 0x4
+#define TSK_CORE_OFFSET 0x8
+#define SMC_TASK1_BASE (SMC_GLBL_BASE + 32)
+#define SMC_TASK2_BASE (SMC_TASK1_BASE + SMC_TASK_OFFSET)
+#define SMC_TASK3_BASE (SMC_TASK2_BASE + SMC_TASK_OFFSET)
+#define SMC_TASK4_BASE (SMC_TASK3_BASE + SMC_TASK_OFFSET)
+
+/* psci data area offsets */
+#define CORE_STATE_DATA 0x0
+#define SPSR_EL3_DATA 0x8
+#define CNTXT_ID_DATA 0x10
+#define START_ADDR_DATA 0x18
+#define LINK_REG_DATA 0x20
+#define GICC_CTLR_DATA 0x28
+#define ABORT_FLAG_DATA 0x30
+#define SCTLR_DATA 0x38
+#define CPUECTLR_DATA 0x40
+#define AUX_01_DATA 0x48 /* usage defined per SoC */
+#define AUX_02_DATA 0x50 /* usage defined per SoC */
+#define AUX_03_DATA 0x58 /* usage defined per SoC */
+#define AUX_04_DATA 0x60 /* usage defined per SoC */
+#define AUX_05_DATA 0x68 /* usage defined per SoC */
+#define AUX_06_DATA 0x70 /* usage defined per SoC */
+#define AUX_07_DATA 0x78 /* usage defined per SoC */
+#define SCR_EL3_DATA 0x80
+#define HCR_EL2_DATA 0x88
+
+#endif /* BL31_DATA_H */
diff --git a/plat/nxp/common/setup/include/ls_interrupt_mgmt.h b/plat/nxp/common/setup/include/ls_interrupt_mgmt.h
new file mode 100644
index 0000000..7dbddfb
--- /dev/null
+++ b/plat/nxp/common/setup/include/ls_interrupt_mgmt.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef LS_EL3_INTRPT_MGMT_H
+#define LS_EL3_INTRPT_MGMT_H
+
+#include <bl31/interrupt_mgmt.h>
+
+#define MAX_INTR_EL3 128
+
+/*
+ * Register handler to specific GIC entrance
+ * for INTR_TYPE_EL3 type of interrupt
+ */
+int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler);
+
+void ls_el3_interrupt_config(void);
+
+#endif /* LS_EL3_INTRPT_MGMT_H */
diff --git a/plat/nxp/common/setup/include/mmu_def.h b/plat/nxp/common/setup/include/mmu_def.h
new file mode 100644
index 0000000..2a7771b
--- /dev/null
+++ b/plat/nxp/common/setup/include/mmu_def.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef MMU_MAP_DEF_H
+#define MMU_MAP_DEF_H
+
+#include <lib/xlat_tables/xlat_tables_defs.h>
+
+#include <platform_def.h>
+
+
+#define LS_MAP_CCSR MAP_REGION_FLAT(NXP_CCSR_ADDR, \
+ NXP_CCSR_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#ifdef NXP_DCSR_ADDR
+#define LS_MAP_DCSR MAP_REGION_FLAT(NXP_DCSR_ADDR, \
+ NXP_DCSR_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+#endif
+
+#define LS_MAP_CONSOLE MAP_REGION_FLAT(NXP_DUART1_ADDR, \
+ NXP_DUART_SIZE, \
+ MT_DEVICE | MT_RW | MT_NS)
+
+#define LS_MAP_OCRAM MAP_REGION_FLAT(NXP_OCRAM_ADDR, \
+ NXP_OCRAM_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#endif /* MMU_MAP_DEF_H */
diff --git a/plat/nxp/common/setup/include/plat_common.h b/plat/nxp/common/setup/include/plat_common.h
new file mode 100644
index 0000000..97a9cb7
--- /dev/null
+++ b/plat/nxp/common/setup/include/plat_common.h
@@ -0,0 +1,150 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PLAT_COMMON_H
+#define PLAT_COMMON_H
+
+#include <stdbool.h>
+
+#include <dcfg.h>
+#include <lib/el3_runtime/cpu_data.h>
+
+#include <platform_def.h>
+
+#ifdef IMAGE_BL31
+
+#define BL31_END (uintptr_t)(&__BL31_END__)
+
+/*******************************************************************************
+ * This structure represents the superset of information that can be passed to
+ * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be
+ * populated only if BL2 detects its presence. A pointer to a structure of this
+ * type should be passed in X0 to BL31's cold boot entrypoint.
+ *
+ * Use of this structure and the X0 parameter is not mandatory: the BL31
+ * platform code can use other mechanisms to provide the necessary information
+ * about BL32 and BL33 to the common and SPD code.
+ *
+ * BL31 image information is mandatory if this structure is used. If either of
+ * the optional BL32 and BL33 image information is not provided, this is
+ * indicated by the respective image_info pointers being zero.
+ ******************************************************************************/
+typedef struct bl31_params {
+ param_header_t h;
+ image_info_t *bl31_image_info;
+ entry_point_info_t *bl32_ep_info;
+ image_info_t *bl32_image_info;
+ entry_point_info_t *bl33_ep_info;
+ image_info_t *bl33_image_info;
+} bl31_params_t;
+
+/* BL3 utility functions */
+void ls_bl31_early_platform_setup(void *from_bl2,
+ void *plat_params_from_bl2);
+/* LS Helper functions */
+unsigned int plat_my_core_mask(void);
+unsigned int plat_core_mask(u_register_t mpidr);
+unsigned int plat_core_pos(u_register_t mpidr);
+//unsigned int plat_my_core_pos(void);
+
+/* BL31 Data API(s) */
+void _init_global_data(void);
+void _initialize_psci(void);
+uint32_t _getCoreState(u_register_t core_mask);
+void _setCoreState(u_register_t core_mask, u_register_t core_state);
+
+/* SoC defined structure and API(s) */
+void soc_runtime_setup(void);
+void soc_init(void);
+void soc_platform_setup(void);
+void soc_early_platform_setup2(void);
+#endif /* IMAGE_BL31 */
+
+#ifdef IMAGE_BL2
+void soc_early_init(void);
+void soc_mem_access(void);
+void soc_preload_setup(void);
+void soc_bl2_prepare_exit(void);
+
+/* IO storage utility functions */
+int plat_io_setup(void);
+int open_backend(const uintptr_t spec);
+
+void ls_bl2_plat_arch_setup(void);
+void ls_bl2_el3_plat_arch_setup(void);
+
+enum boot_device {
+ BOOT_DEVICE_IFC_NOR,
+ BOOT_DEVICE_IFC_NAND,
+ BOOT_DEVICE_QSPI,
+ BOOT_DEVICE_EMMC,
+ BOOT_DEVICE_SDHC2_EMMC,
+ BOOT_DEVICE_FLEXSPI_NOR,
+ BOOT_DEVICE_FLEXSPI_NAND,
+ BOOT_DEVICE_NONE
+};
+
+enum boot_device get_boot_dev(void);
+
+/* DDR Related functions */
+#if DDR_INIT
+#ifdef NXP_WARM_BOOT
+long long init_ddr(uint32_t wrm_bt_flg);
+#else
+long long init_ddr(void);
+#endif
+#endif
+
+/* Board specific weak functions */
+bool board_enable_povdd(void);
+bool board_disable_povdd(void);
+
+void mmap_add_ddr_region_dynamically(void);
+#endif /* IMAGE_BL2 */
+
+typedef struct {
+ uint64_t addr;
+ uint64_t size;
+} region_info_t;
+
+typedef struct {
+ uint64_t num_dram_regions;
+ uint64_t total_dram_size;
+ region_info_t region[NUM_DRAM_REGIONS];
+} dram_regions_info_t;
+
+dram_regions_info_t *get_dram_regions_info(void);
+
+void ls_setup_page_tables(uintptr_t total_base,
+ size_t total_size,
+ uintptr_t code_start,
+ uintptr_t code_limit,
+ uintptr_t rodata_start,
+ uintptr_t rodata_limit
+#if USE_COHERENT_MEM
+ , uintptr_t coh_start,
+ uintptr_t coh_limit
+#endif
+);
+
+/* Structure to define SoC personality */
+struct soc_type {
+ char name[10];
+ uint32_t version;
+ uint8_t num_clusters;
+ uint8_t cores_per_cluster;
+};
+void get_cluster_info(const struct soc_type *soc_list, uint8_t ps_count,
+ uint8_t *num_clusters, uint8_t *cores_per_cluster);
+
+#define SOC_ENTRY(n, v, ncl, nc) { \
+ .name = #n, \
+ .version = SVR_##v, \
+ .num_clusters = (ncl), \
+ .cores_per_cluster = (nc)}
+
+#endif /* PLAT_COMMON_H */
diff --git a/plat/nxp/common/setup/include/plat_macros.S b/plat/nxp/common/setup/include/plat_macros.S
new file mode 100644
index 0000000..69a3b08
--- /dev/null
+++ b/plat/nxp/common/setup/include/plat_macros.S
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PLAT_MACROS_S
+#define PLAT_MACROS_S
+
+ /* ---------------------------------------------
+ * The below required platform porting macro
+ * prints out relevant GIC and CCI registers
+ * whenever an unhandled exception is taken in
+ * BL31.
+ * Clobbers: x0 - x10, x16, x17, sp
+ * ---------------------------------------------
+ */
+ .macro plat_crash_print_regs
+ .endm
+
+#endif /* PLAT_MACROS_S */
diff --git a/plat/nxp/common/setup/ls_bl2_el3_setup.c b/plat/nxp/common/setup/ls_bl2_el3_setup.c
new file mode 100644
index 0000000..6428eb9
--- /dev/null
+++ b/plat/nxp/common/setup/ls_bl2_el3_setup.c
@@ -0,0 +1,300 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <assert.h>
+
+#include <common/desc_image_load.h>
+#include <dcfg.h>
+#ifdef POLICY_FUSE_PROVISION
+#include <fuse_io.h>
+#endif
+#include <mmu_def.h>
+#include <plat_common.h>
+#ifdef NXP_NV_SW_MAINT_LAST_EXEC_DATA
+#include <plat_nv_storage.h>
+#endif
+
+#pragma weak bl2_el3_early_platform_setup
+#pragma weak bl2_el3_plat_arch_setup
+#pragma weak bl2_el3_plat_prepare_exit
+
+static dram_regions_info_t dram_regions_info = {0};
+
+/*******************************************************************************
+ * Return the pointer to the 'dram_regions_info structure of the DRAM.
+ * This structure is populated after init_ddr().
+ ******************************************************************************/
+dram_regions_info_t *get_dram_regions_info(void)
+{
+ return &dram_regions_info;
+}
+
+#ifdef DDR_INIT
+static void populate_dram_regions_info(void)
+{
+ long long dram_remain_size = dram_regions_info.total_dram_size;
+ uint8_t reg_id = 0U;
+
+ dram_regions_info.region[reg_id].addr = NXP_DRAM0_ADDR;
+ dram_regions_info.region[reg_id].size =
+ dram_remain_size > NXP_DRAM0_MAX_SIZE ?
+ NXP_DRAM0_MAX_SIZE : dram_remain_size;
+
+ if (dram_regions_info.region[reg_id].size != NXP_DRAM0_SIZE) {
+ ERROR("Incorrect DRAM0 size is defined in platform_def.h\n");
+ }
+
+ dram_remain_size -= dram_regions_info.region[reg_id].size;
+ dram_regions_info.region[reg_id].size -= (NXP_SECURE_DRAM_SIZE
+ + NXP_SP_SHRD_DRAM_SIZE);
+
+ assert(dram_regions_info.region[reg_id].size > 0);
+
+ /* Reducing total dram size by 66MB */
+ dram_regions_info.total_dram_size -= (NXP_SECURE_DRAM_SIZE
+ + NXP_SP_SHRD_DRAM_SIZE);
+
+#if defined(NXP_DRAM1_ADDR) && defined(NXP_DRAM1_MAX_SIZE)
+ if (dram_remain_size > 0) {
+ reg_id++;
+ dram_regions_info.region[reg_id].addr = NXP_DRAM1_ADDR;
+ dram_regions_info.region[reg_id].size =
+ dram_remain_size > NXP_DRAM1_MAX_SIZE ?
+ NXP_DRAM1_MAX_SIZE : dram_remain_size;
+ dram_remain_size -= dram_regions_info.region[reg_id].size;
+ }
+#endif
+#if defined(NXP_DRAM2_ADDR) && defined(NXP_DRAM2_MAX_SIZE)
+ if (dram_remain_size > 0) {
+ reg_id++;
+ dram_regions_info.region[reg_id].addr = NXP_DRAM1_ADDR;
+ dram_regions_info.region[reg_id].size =
+ dram_remain_size > NXP_DRAM1_MAX_SIZE ?
+ NXP_DRAM1_MAX_SIZE : dram_remain_size;
+ dram_remain_size -= dram_regions_info.region[reg_id].size;
+ }
+#endif
+ reg_id++;
+ dram_regions_info.num_dram_regions = reg_id;
+}
+#endif
+
+#ifdef IMAGE_BL32
+/*******************************************************************************
+ * Gets SPSR for BL32 entry
+ ******************************************************************************/
+static uint32_t ls_get_spsr_for_bl32_entry(void)
+{
+ /*
+ * The Secure Payload Dispatcher service is responsible for
+ * setting the SPSR prior to entry into the BL32 image.
+ */
+ return 0U;
+}
+#endif
+
+/*******************************************************************************
+ * Gets SPSR for BL33 entry
+ ******************************************************************************/
+#ifndef AARCH32
+static uint32_t ls_get_spsr_for_bl33_entry(void)
+{
+ unsigned int mode;
+ uint32_t spsr;
+
+ /* Figure out what mode we enter the non-secure world in */
+ mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
+
+ /*
+ * TODO: Consider the possibility of specifying the SPSR in
+ * the FIP ToC and allowing the platform to have a say as
+ * well.
+ */
+ spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
+ return spsr;
+}
+#else
+/*******************************************************************************
+ * Gets SPSR for BL33 entry
+ ******************************************************************************/
+static uint32_t ls_get_spsr_for_bl33_entry(void)
+{
+ unsigned int hyp_status, mode, spsr;
+
+ hyp_status = GET_VIRT_EXT(read_id_pfr1());
+
+ mode = (hyp_status) ? MODE32_hyp : MODE32_svc;
+
+ /*
+ * TODO: Consider the possibility of specifying the SPSR in
+ * the FIP ToC and allowing the platform to have a say as
+ * well.
+ */
+ spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1,
+ SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
+ return spsr;
+}
+#endif /* AARCH32 */
+
+void bl2_el3_early_platform_setup(u_register_t arg0 __unused,
+ u_register_t arg1 __unused,
+ u_register_t arg2 __unused,
+ u_register_t arg3 __unused)
+{
+ /*
+ * SoC specific early init
+ * Any errata handling or SoC specific early initialization can
+ * be done here
+ * Set Counter Base Frequency in CNTFID0 and in cntfrq_el0.
+ * Initialize the interconnect.
+ * Enable coherency for primary CPU cluster
+ */
+ soc_early_init();
+
+ /* Initialise the IO layer and register platform IO devices */
+ plat_io_setup();
+
+ if (dram_regions_info.total_dram_size > 0) {
+ populate_dram_regions_info();
+ }
+
+#ifdef NXP_NV_SW_MAINT_LAST_EXEC_DATA
+ read_nv_app_data();
+#if DEBUG
+ const nv_app_data_t *nv_app_data = get_nv_data();
+
+ INFO("Value of warm_reset flag = 0x%x\n", nv_app_data->warm_rst_flag);
+ INFO("Value of WDT flag = 0x%x\n", nv_app_data->wdt_rst_flag);
+#endif
+#endif
+}
+
+/*******************************************************************************
+ * Perform the very early platform specific architectural setup here. At the
+ * moment this is only initializes the mmu in a quick and dirty way.
+ ******************************************************************************/
+void ls_bl2_el3_plat_arch_setup(void)
+{
+ unsigned int flags = 0U;
+ /* Initialise the IO layer and register platform IO devices */
+ ls_setup_page_tables(
+#if SEPARATE_RW_AND_NOLOAD
+ BL2_START,
+ BL2_LIMIT - BL2_START,
+#else
+ BL2_BASE,
+ (unsigned long)(&__BL2_END__) - BL2_BASE,
+#endif
+ BL_CODE_BASE,
+ BL_CODE_END,
+ BL_RO_DATA_BASE,
+ BL_RO_DATA_END
+#if USE_COHERENT_MEM
+ , BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END
+#endif
+ );
+
+ if ((dram_regions_info.region[0].addr == 0)
+ && (dram_regions_info.total_dram_size == 0)) {
+ flags = XLAT_TABLE_NC;
+ }
+
+#ifdef AARCH32
+ enable_mmu_secure(0);
+#else
+ enable_mmu_el3(flags);
+#endif
+}
+
+void bl2_el3_plat_arch_setup(void)
+{
+ ls_bl2_el3_plat_arch_setup();
+}
+
+void bl2_platform_setup(void)
+{
+ /*
+ * Perform platform setup before loading the image.
+ */
+}
+
+/* Handling image information by platform. */
+int ls_bl2_handle_post_image_load(unsigned int image_id)
+{
+ int err = 0;
+ bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
+
+ assert(bl_mem_params);
+
+ switch (image_id) {
+ case BL31_IMAGE_ID:
+ bl_mem_params->ep_info.args.arg3 =
+ (u_register_t) &dram_regions_info;
+
+ /* Pass the value of PORSR1 register in Argument 4 */
+ bl_mem_params->ep_info.args.arg4 =
+ (u_register_t)read_reg_porsr1();
+ flush_dcache_range((uintptr_t)&dram_regions_info,
+ sizeof(dram_regions_info));
+ break;
+#if defined(AARCH64) && defined(IMAGE_BL32)
+ case BL32_IMAGE_ID:
+ bl_mem_params->ep_info.spsr = ls_get_spsr_for_bl32_entry();
+ break;
+#endif
+ case BL33_IMAGE_ID:
+ /* BL33 expects to receive the primary CPU MPID (through r0) */
+ bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
+ bl_mem_params->ep_info.spsr = ls_get_spsr_for_bl33_entry();
+ break;
+ }
+
+ return err;
+}
+
+/*******************************************************************************
+ * This function can be used by the platforms to update/use image
+ * information for given `image_id`.
+ ******************************************************************************/
+int bl2_plat_handle_post_image_load(unsigned int image_id)
+{
+ return ls_bl2_handle_post_image_load(image_id);
+}
+
+void bl2_el3_plat_prepare_exit(void)
+{
+ return soc_bl2_prepare_exit();
+}
+
+/* Called to do the dynamic initialization required
+ * before loading the next image.
+ */
+void bl2_plat_preload_setup(void)
+{
+
+ soc_preload_setup();
+
+ if (dram_regions_info.total_dram_size < NXP_DRAM0_SIZE) {
+ NOTICE("ERROR: DRAM0 Size is not correctly configured.");
+ assert(false);
+ }
+
+ if ((dram_regions_info.region[0].addr == 0)
+ && (dram_regions_info.total_dram_size > 0)) {
+ populate_dram_regions_info();
+
+ mmap_add_ddr_region_dynamically();
+ }
+
+ /* setup the memory region access permissions */
+ soc_mem_access();
+
+#ifdef POLICY_FUSE_PROVISION
+ fip_fuse_provisioning((uintptr_t)FUSE_BUF, FUSE_SZ);
+#endif
+}
diff --git a/plat/nxp/common/setup/ls_bl31_setup.c b/plat/nxp/common/setup/ls_bl31_setup.c
new file mode 100644
index 0000000..6cf6ae3
--- /dev/null
+++ b/plat/nxp/common/setup/ls_bl31_setup.c
@@ -0,0 +1,210 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <assert.h>
+
+#ifdef LS_EL3_INTERRUPT_HANDLER
+#include <ls_interrupt_mgmt.h>
+#endif
+#include <mmu_def.h>
+#include <plat_common.h>
+
+/*
+ * Placeholder variables for copying the arguments that have been passed to
+ * BL31 from BL2.
+ */
+#ifdef TEST_BL31
+#define SPSR_FOR_EL2H 0x3C9
+#define SPSR_FOR_EL1H 0x3C5
+#else
+static entry_point_info_t bl31_image_ep_info;
+#endif
+
+static entry_point_info_t bl32_image_ep_info;
+static entry_point_info_t bl33_image_ep_info;
+
+static dram_regions_info_t dram_regions_info = {0};
+static uint64_t rcw_porsr1;
+
+/* Return the pointer to the 'dram_regions_info structure of the DRAM.
+ * This structure is populated after init_ddr().
+ */
+dram_regions_info_t *get_dram_regions_info(void)
+{
+ return &dram_regions_info;
+}
+
+/* Return the RCW.PORSR1 value which was passed in from BL2
+ */
+uint64_t bl31_get_porsr1(void)
+{
+ return rcw_porsr1;
+}
+
+/*
+ * Return pointer to the 'entry_point_info' structure of the next image for the
+ * security state specified:
+ * - BL33 corresponds to the non-secure image type; while
+ * - BL32 corresponds to the secure image type.
+ * - A NULL pointer is returned, if the image does not exist.
+ */
+entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
+{
+ entry_point_info_t *next_image_info;
+
+ assert(sec_state_is_valid(type));
+ next_image_info = (type == NON_SECURE)
+ ? &bl33_image_ep_info : &bl32_image_ep_info;
+
+#ifdef TEST_BL31
+ next_image_info->pc = _get_test_entry();
+ next_image_info->spsr = SPSR_FOR_EL2H;
+ next_image_info->h.attr = NON_SECURE;
+#endif
+
+ if (next_image_info->pc != 0U) {
+ return next_image_info;
+ } else {
+ return NULL;
+ }
+}
+
+/*
+ * Perform any BL31 early platform setup common to NXP platforms.
+ * - Here is an opportunity to copy parameters passed by the calling EL (S-EL1
+ * in BL2 & S-EL3 in BL1) before they are lost (potentially).
+ * - This needs to be done before the MMU is initialized so that the
+ * memory layout can be used while creating page tables.
+ * - BL2 has flushed this information to memory, in order to fetch latest data.
+ */
+
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
+{
+#ifndef TEST_BL31
+ int i = 0;
+ void *from_bl2 = (void *)arg0;
+#endif
+ soc_early_platform_setup2();
+
+#ifdef TEST_BL31
+ dram_regions_info.num_dram_regions = 2;
+ dram_regions_info.total_dram_size = 0x100000000;
+ dram_regions_info.region[0].addr = 0x80000000;
+ dram_regions_info.region[0].size = 0x80000000;
+ dram_regions_info.region[1].addr = 0x880000000;
+ dram_regions_info.region[1].size = 0x80000000;
+
+ bl33_image_ep_info.pc = _get_test_entry();
+#else
+ /*
+ * Check params passed from BL2 should not be NULL,
+ */
+ bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
+
+ assert(params_from_bl2 != NULL);
+ assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
+ assert(params_from_bl2->h.version >= VERSION_2);
+
+ bl_params_node_t *bl_params = params_from_bl2->head;
+
+ /*
+ * Copy BL33 and BL32 (if present), entry point information.
+ * They are stored in Secure RAM, in BL2's address space.
+ */
+ while (bl_params != NULL) {
+ if (bl_params->image_id == BL31_IMAGE_ID) {
+ bl31_image_ep_info = *bl_params->ep_info;
+ dram_regions_info_t *loc_dram_regions_info =
+ (dram_regions_info_t *) bl31_image_ep_info.args.arg3;
+
+ dram_regions_info.num_dram_regions =
+ loc_dram_regions_info->num_dram_regions;
+ dram_regions_info.total_dram_size =
+ loc_dram_regions_info->total_dram_size;
+ VERBOSE("Number of DRAM Regions = %llx\n",
+ dram_regions_info.num_dram_regions);
+
+ for (i = 0; i < dram_regions_info.num_dram_regions;
+ i++) {
+ dram_regions_info.region[i].addr =
+ loc_dram_regions_info->region[i].addr;
+ dram_regions_info.region[i].size =
+ loc_dram_regions_info->region[i].size;
+ VERBOSE("DRAM%d Size = %llx\n", i,
+ dram_regions_info.region[i].size);
+ }
+ rcw_porsr1 = bl31_image_ep_info.args.arg4;
+ }
+
+ if (bl_params->image_id == BL32_IMAGE_ID) {
+ bl32_image_ep_info = *bl_params->ep_info;
+ }
+
+ if (bl_params->image_id == BL33_IMAGE_ID) {
+ bl33_image_ep_info = *bl_params->ep_info;
+ }
+
+ bl_params = bl_params->next_params_info;
+ }
+#endif /* TEST_BL31 */
+
+ if (bl33_image_ep_info.pc == 0) {
+ panic();
+ }
+
+ /*
+ * perform basic initialization on the soc
+ */
+ soc_init();
+}
+
+/*******************************************************************************
+ * Perform any BL31 platform setup common to ARM standard platforms
+ ******************************************************************************/
+void bl31_platform_setup(void)
+{
+ NOTICE("Welcome to %s BL31 Phase\n", BOARD);
+ soc_platform_setup();
+
+ /* Console logs gone missing as part going to
+ * EL1 for initilizing Bl32 if present.
+ * console flush is necessary to avoid it.
+ */
+ (void)console_flush();
+}
+
+void bl31_plat_runtime_setup(void)
+{
+#ifdef LS_EL3_INTERRUPT_HANDLER
+ ls_el3_interrupt_config();
+#endif
+ soc_runtime_setup();
+}
+
+/*******************************************************************************
+ * Perform the very early platform specific architectural setup shared between
+ * ARM standard platforms. This only does basic initialization. Later
+ * architectural setup (bl31_arch_setup()) does not do anything platform
+ * specific.
+ ******************************************************************************/
+void bl31_plat_arch_setup(void)
+{
+
+ ls_setup_page_tables(BL31_BASE,
+ BL31_END - BL31_BASE,
+ BL_CODE_BASE,
+ BL_CODE_END,
+ BL_RO_DATA_BASE,
+ BL_RO_DATA_END
+#if USE_COHERENT_MEM
+ , BL_COHERENT_RAM_BASE,
+ BL_COHERENT_RAM_END
+#endif
+ );
+ enable_mmu_el3(0);
+}
diff --git a/plat/nxp/common/setup/ls_common.c b/plat/nxp/common/setup/ls_common.c
new file mode 100644
index 0000000..e7ae060
--- /dev/null
+++ b/plat/nxp/common/setup/ls_common.c
@@ -0,0 +1,264 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <assert.h>
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <mmu_def.h>
+#include <plat/common/platform.h>
+
+#include "plat_common.h"
+#include "platform_def.h"
+
+const mmap_region_t *plat_ls_get_mmap(void);
+
+/*
+ * Table of memory regions for various BL stages to map using the MMU.
+ * This doesn't include Trusted SRAM as arm_setup_page_tables() already
+ * takes care of mapping it.
+ *
+ * The flash needs to be mapped as writable in order to erase the FIP's Table of
+ * Contents in case of unrecoverable error (see plat_error_handler()).
+ */
+#ifdef IMAGE_BL2
+const mmap_region_t plat_ls_mmap[] = {
+ LS_MAP_CCSR,
+ {0}
+};
+#endif
+
+#ifdef IMAGE_BL31
+const mmap_region_t plat_ls_mmap[] = {
+ LS_MAP_CCSR,
+#ifdef NXP_DCSR_ADDR
+ LS_MAP_DCSR,
+#endif
+ LS_MAP_OCRAM,
+ {0}
+};
+#endif
+#ifdef IMAGE_BL32
+const mmap_region_t plat_ls_mmap[] = {
+ LS_MAP_CCSR,
+ LS_MAP_BL32_SEC_MEM,
+ {0}
+};
+#endif
+
+/* Weak definitions may be overridden in specific NXP SoC */
+#pragma weak plat_get_ns_image_entrypoint
+#pragma weak plat_ls_get_mmap
+
+#if defined(IMAGE_BL31) || !defined(CONFIG_DDR_FIP_IMAGE)
+static void mmap_add_ddr_regions_statically(void)
+{
+ int i = 0;
+ dram_regions_info_t *info_dram_regions = get_dram_regions_info();
+ /* MMU map for Non-Secure DRAM Regions */
+ VERBOSE("DRAM Region %d: %p - %p\n", i,
+ (void *) info_dram_regions->region[i].addr,
+ (void *) (info_dram_regions->region[i].addr
+ + info_dram_regions->region[i].size
+ - 1));
+ mmap_add_region(info_dram_regions->region[i].addr,
+ info_dram_regions->region[i].addr,
+ info_dram_regions->region[i].size,
+ MT_MEMORY | MT_RW | MT_NS);
+
+ /* MMU map for Secure DDR Region on DRAM-0 */
+ if (info_dram_regions->region[i].size >
+ (NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE)) {
+ VERBOSE("Secure DRAM Region %d: %p - %p\n", i,
+ (void *) (info_dram_regions->region[i].addr
+ + info_dram_regions->region[i].size),
+ (void *) (info_dram_regions->region[i].addr
+ + info_dram_regions->region[i].size
+ + NXP_SECURE_DRAM_SIZE
+ + NXP_SP_SHRD_DRAM_SIZE
+ - 1));
+ mmap_add_region((info_dram_regions->region[i].addr
+ + info_dram_regions->region[i].size),
+ (info_dram_regions->region[i].addr
+ + info_dram_regions->region[i].size),
+ (NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE),
+ MT_MEMORY | MT_RW | MT_SECURE);
+ }
+
+#ifdef IMAGE_BL31
+ for (i = 1; i < info_dram_regions->num_dram_regions; i++) {
+ if (info_dram_regions->region[i].size == 0)
+ break;
+ VERBOSE("DRAM Region %d: %p - %p\n", i,
+ (void *) info_dram_regions->region[i].addr,
+ (void *) (info_dram_regions->region[i].addr
+ + info_dram_regions->region[i].size
+ - 1));
+ mmap_add_region(info_dram_regions->region[i].addr,
+ info_dram_regions->region[i].addr,
+ info_dram_regions->region[i].size,
+ MT_MEMORY | MT_RW | MT_NS);
+ }
+#endif
+}
+#endif
+
+#if defined(PLAT_XLAT_TABLES_DYNAMIC)
+void mmap_add_ddr_region_dynamically(void)
+{
+ int i = 0;
+ dram_regions_info_t *info_dram_regions = get_dram_regions_info();
+ /* MMU map for Non-Secure DRAM Regions */
+ VERBOSE("DRAM Region %d: %p - %p\n", i,
+ (void *) info_dram_regions->region[i].addr,
+ (void *) (info_dram_regions->region[i].addr
+ + info_dram_regions->region[i].size
+ - 1));
+ mmap_add_dynamic_region(info_dram_regions->region[i].addr,
+ info_dram_regions->region[i].addr,
+ info_dram_regions->region[i].size,
+ MT_MEMORY | MT_RW | MT_NS);
+
+ /* MMU map for Secure DDR Region on DRAM-0 */
+ if (info_dram_regions->region[i].size >
+ (NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE)) {
+ VERBOSE("Secure DRAM Region %d: %p - %p\n", i,
+ (void *) (info_dram_regions->region[i].addr
+ + info_dram_regions->region[i].size),
+ (void *) (info_dram_regions->region[i].addr
+ + info_dram_regions->region[i].size
+ + NXP_SECURE_DRAM_SIZE
+ + NXP_SP_SHRD_DRAM_SIZE
+ - 1));
+ mmap_add_dynamic_region((info_dram_regions->region[i].addr
+ + info_dram_regions->region[i].size),
+ (info_dram_regions->region[i].addr
+ + info_dram_regions->region[i].size),
+ (NXP_SECURE_DRAM_SIZE + NXP_SP_SHRD_DRAM_SIZE),
+ MT_MEMORY | MT_RW | MT_SECURE);
+ }
+
+#ifdef IMAGE_BL31
+ for (i = 1; i < info_dram_regions->num_dram_regions; i++) {
+ if (info_dram_regions->region[i].size == 0) {
+ break;
+ }
+ VERBOSE("DRAM Region %d: %p - %p\n", i,
+ (void *) info_dram_regions->region[i].addr,
+ (void *) (info_dram_regions->region[i].addr
+ + info_dram_regions->region[i].size
+ - 1));
+ mmap_add_dynamic_region(info_dram_regions->region[i].addr,
+ info_dram_regions->region[i].addr,
+ info_dram_regions->region[i].size,
+ MT_MEMORY | MT_RW | MT_NS);
+ }
+#endif
+}
+#endif
+
+/*
+ * Set up the page tables for the generic and platform-specific memory regions.
+ * The extents of the generic memory regions are specified by the function
+ * arguments and consist of:
+ * - Trusted SRAM seen by the BL image;
+ * - Code section;
+ * - Read-only data section;
+ * - Coherent memory region, if applicable.
+ */
+void ls_setup_page_tables(uintptr_t total_base,
+ size_t total_size,
+ uintptr_t code_start,
+ uintptr_t code_limit,
+ uintptr_t rodata_start,
+ uintptr_t rodata_limit
+#if USE_COHERENT_MEM
+ ,
+ uintptr_t coh_start,
+ uintptr_t coh_limit
+#endif
+ )
+{
+ /*
+ * Map the Trusted SRAM with appropriate memory attributes.
+ * Subsequent mappings will adjust the attributes for specific regions.
+ */
+ VERBOSE("Memory seen by this BL image: %p - %p\n",
+ (void *) total_base, (void *) (total_base + total_size));
+ mmap_add_region(total_base, total_base,
+ total_size,
+ MT_MEMORY | MT_RW | MT_SECURE);
+
+ /* Re-map the code section */
+ VERBOSE("Code region: %p - %p\n",
+ (void *) code_start, (void *) code_limit);
+ mmap_add_region(code_start, code_start,
+ code_limit - code_start,
+ MT_CODE | MT_SECURE);
+
+ /* Re-map the read-only data section */
+ VERBOSE("Read-only data region: %p - %p\n",
+ (void *) rodata_start, (void *) rodata_limit);
+ mmap_add_region(rodata_start, rodata_start,
+ rodata_limit - rodata_start,
+ MT_RO_DATA | MT_SECURE);
+
+#if USE_COHERENT_MEM
+ /* Re-map the coherent memory region */
+ VERBOSE("Coherent region: %p - %p\n",
+ (void *) coh_start, (void *) coh_limit);
+ mmap_add_region(coh_start, coh_start,
+ coh_limit - coh_start,
+ MT_DEVICE | MT_RW | MT_SECURE);
+#endif
+
+ /* Now (re-)map the platform-specific memory regions */
+ mmap_add(plat_ls_get_mmap());
+
+
+#if defined(IMAGE_BL31) || !defined(CONFIG_DDR_FIP_IMAGE)
+ mmap_add_ddr_regions_statically();
+#endif
+
+ /* Create the page tables to reflect the above mappings */
+ init_xlat_tables();
+}
+
+/*******************************************************************************
+ * Returns NXP platform specific memory map regions.
+ ******************************************************************************/
+const mmap_region_t *plat_ls_get_mmap(void)
+{
+ return plat_ls_mmap;
+}
+
+/*
+ * This function get the number of clusters and cores count per cluster
+ * in the SoC.
+ */
+void get_cluster_info(const struct soc_type *soc_list, uint8_t ps_count,
+ uint8_t *num_clusters, uint8_t *cores_per_cluster)
+{
+ const soc_info_t *soc_info = get_soc_info();
+ *num_clusters = NUMBER_OF_CLUSTERS;
+ *cores_per_cluster = CORES_PER_CLUSTER;
+ unsigned int i;
+
+ for (i = 0U; i < ps_count; i++) {
+ if (soc_list[i].version == soc_info->svr_reg.bf_ver.version) {
+ *num_clusters = soc_list[i].num_clusters;
+ *cores_per_cluster = soc_list[i].cores_per_cluster;
+ break;
+ }
+ }
+
+ VERBOSE("NUM of cluster = 0x%x, Cores per cluster = 0x%x\n",
+ *num_clusters, *cores_per_cluster);
+}
diff --git a/plat/nxp/common/setup/ls_err.c b/plat/nxp/common/setup/ls_err.c
new file mode 100644
index 0000000..845cd15
--- /dev/null
+++ b/plat/nxp/common/setup/ls_err.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+
+#if TRUSTED_BOARD_BOOT
+#include <dcfg.h>
+#include <snvs.h>
+#endif
+
+#include "plat_common.h"
+
+/*
+ * Error handler
+ */
+void plat_error_handler(int err)
+{
+#if TRUSTED_BOARD_BOOT
+ uint32_t mode;
+ bool sb = check_boot_mode_secure(&mode);
+#endif
+
+ switch (err) {
+ case -ENOENT:
+ case -EAUTH:
+ printf("Authentication failure\n");
+#if TRUSTED_BOARD_BOOT
+ /* For SB production mode i.e ITS = 1 */
+ if (sb == true) {
+ if (mode == 1U) {
+ transition_snvs_soft_fail();
+ } else {
+ transition_snvs_non_secure();
+ }
+ }
+#endif
+ break;
+ default:
+ /* Unexpected error */
+ break;
+ }
+
+ /* Loop until the watchdog resets the system */
+ for (;;)
+ wfi();
+}
diff --git a/plat/nxp/common/setup/ls_image_load.c b/plat/nxp/common/setup/ls_image_load.c
new file mode 100644
index 0000000..259ab31
--- /dev/null
+++ b/plat/nxp/common/setup/ls_image_load.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <common/desc_image_load.h>
+
+/*******************************************************************************
+ * This function flushes the data structures so that they are visible
+ * in memory for the next BL image.
+ ******************************************************************************/
+void plat_flush_next_bl_params(void)
+{
+ flush_bl_params_desc();
+}
+
+/*******************************************************************************
+ * This function returns the list of loadable images.
+ ******************************************************************************/
+bl_load_info_t *plat_get_bl_image_load_info(void)
+{
+ return get_bl_load_info_from_mem_params_desc();
+}
+
+/*******************************************************************************
+ * This function returns the list of executable images.
+ ******************************************************************************/
+bl_params_t *plat_get_next_bl_params(void)
+{
+ return get_next_bl_params_from_mem_params_desc();
+}
diff --git a/plat/nxp/common/setup/ls_interrupt_mgmt.c b/plat/nxp/common/setup/ls_interrupt_mgmt.c
new file mode 100644
index 0000000..a81cb2b
--- /dev/null
+++ b/plat/nxp/common/setup/ls_interrupt_mgmt.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <bl31/interrupt_mgmt.h>
+#include <common/debug.h>
+#include <ls_interrupt_mgmt.h>
+#include <plat/common/platform.h>
+
+static interrupt_type_handler_t type_el3_interrupt_table[MAX_INTR_EL3];
+
+int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
+{
+ /* Validate 'handler' and 'id' parameters */
+ if (!handler || id >= MAX_INTR_EL3) {
+ return -EINVAL;
+ }
+
+ /* Check if a handler has already been registered */
+ if (type_el3_interrupt_table[id] != NULL) {
+ return -EALREADY;
+ }
+
+ type_el3_interrupt_table[id] = handler;
+
+ return 0;
+}
+
+static uint64_t ls_el3_interrupt_handler(uint32_t id, uint32_t flags,
+ void *handle, void *cookie)
+{
+ uint32_t intr_id;
+ interrupt_type_handler_t handler;
+
+ intr_id = plat_ic_get_pending_interrupt_id();
+
+ INFO("Interrupt recvd is %d\n", intr_id);
+
+ handler = type_el3_interrupt_table[intr_id];
+ if (handler != NULL) {
+ handler(intr_id, flags, handle, cookie);
+ }
+
+ /*
+ * Mark this interrupt as complete to avoid a interrupt storm.
+ */
+ plat_ic_end_of_interrupt(intr_id);
+
+ return 0U;
+}
+
+void ls_el3_interrupt_config(void)
+{
+ uint64_t flags = 0U;
+ uint64_t rc;
+
+ set_interrupt_rm_flag(flags, NON_SECURE);
+ rc = register_interrupt_type_handler(INTR_TYPE_EL3,
+ ls_el3_interrupt_handler, flags);
+ if (rc != 0U) {
+ panic();
+ }
+}
diff --git a/plat/nxp/common/setup/ls_io_storage.c b/plat/nxp/common/setup/ls_io_storage.c
new file mode 100644
index 0000000..0c01765
--- /dev/null
+++ b/plat/nxp/common/setup/ls_io_storage.c
@@ -0,0 +1,519 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <assert.h>
+#include <endian.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <common/tbbr/tbbr_img_def.h>
+#include <drivers/io/io_block.h>
+#include <drivers/io/io_driver.h>
+#include <drivers/io/io_fip.h>
+#include <drivers/io/io_memmap.h>
+#include <drivers/io/io_storage.h>
+#ifdef FLEXSPI_NOR_BOOT
+#include <flexspi_nor.h>
+#endif
+#if defined(QSPI_BOOT)
+#include <qspi.h>
+#endif
+#if defined(SD_BOOT) || defined(EMMC_BOOT)
+#include <sd_mmc.h>
+#endif
+#include <tools_share/firmware_image_package.h>
+
+#ifdef CONFIG_DDR_FIP_IMAGE
+#include <ddr_io_storage.h>
+#endif
+#ifdef POLICY_FUSE_PROVISION
+#include <fuse_io.h>
+#endif
+#include "plat_common.h"
+#include "platform_def.h"
+
+uint32_t fip_device;
+/* IO devices */
+uintptr_t backend_dev_handle;
+
+static const io_dev_connector_t *fip_dev_con;
+static uintptr_t fip_dev_handle;
+static const io_dev_connector_t *backend_dev_con;
+
+static io_block_spec_t fip_block_spec = {
+ .offset = PLAT_FIP_OFFSET,
+ .length = PLAT_FIP_MAX_SIZE
+};
+
+static const io_uuid_spec_t bl2_uuid_spec = {
+ .uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2,
+};
+
+static const io_uuid_spec_t fuse_bl2_uuid_spec = {
+ .uuid = UUID_SCP_FIRMWARE_SCP_BL2,
+};
+
+static const io_uuid_spec_t bl31_uuid_spec = {
+ .uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
+};
+
+static const io_uuid_spec_t bl32_uuid_spec = {
+ .uuid = UUID_SECURE_PAYLOAD_BL32,
+};
+
+static const io_uuid_spec_t bl33_uuid_spec = {
+ .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
+};
+
+static const io_uuid_spec_t tb_fw_config_uuid_spec = {
+ .uuid = UUID_TB_FW_CONFIG,
+};
+
+static const io_uuid_spec_t hw_config_uuid_spec = {
+ .uuid = UUID_HW_CONFIG,
+};
+
+#if TRUSTED_BOARD_BOOT
+static const io_uuid_spec_t tb_fw_cert_uuid_spec = {
+ .uuid = UUID_TRUSTED_BOOT_FW_CERT,
+};
+
+static const io_uuid_spec_t trusted_key_cert_uuid_spec = {
+ .uuid = UUID_TRUSTED_KEY_CERT,
+};
+
+static const io_uuid_spec_t fuse_key_cert_uuid_spec = {
+ .uuid = UUID_SCP_FW_KEY_CERT,
+};
+
+static const io_uuid_spec_t soc_fw_key_cert_uuid_spec = {
+ .uuid = UUID_SOC_FW_KEY_CERT,
+};
+
+static const io_uuid_spec_t tos_fw_key_cert_uuid_spec = {
+ .uuid = UUID_TRUSTED_OS_FW_KEY_CERT,
+};
+
+static const io_uuid_spec_t nt_fw_key_cert_uuid_spec = {
+ .uuid = UUID_NON_TRUSTED_FW_KEY_CERT,
+};
+
+static const io_uuid_spec_t fuse_cert_uuid_spec = {
+ .uuid = UUID_SCP_FW_CONTENT_CERT,
+};
+
+static const io_uuid_spec_t soc_fw_cert_uuid_spec = {
+ .uuid = UUID_SOC_FW_CONTENT_CERT,
+};
+
+static const io_uuid_spec_t tos_fw_cert_uuid_spec = {
+ .uuid = UUID_TRUSTED_OS_FW_CONTENT_CERT,
+};
+
+static const io_uuid_spec_t nt_fw_cert_uuid_spec = {
+ .uuid = UUID_NON_TRUSTED_FW_CONTENT_CERT,
+};
+#endif /* TRUSTED_BOARD_BOOT */
+
+static int open_fip(const uintptr_t spec);
+
+struct plat_io_policy {
+ uintptr_t *dev_handle;
+ uintptr_t image_spec;
+ int (*check)(const uintptr_t spec);
+};
+
+/* By default, ARM platforms load images from the FIP */
+static const struct plat_io_policy policies[] = {
+ [FIP_IMAGE_ID] = {
+ &backend_dev_handle,
+ (uintptr_t)&fip_block_spec,
+ open_backend
+ },
+ [BL2_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&bl2_uuid_spec,
+ open_fip
+ },
+ [SCP_BL2_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&fuse_bl2_uuid_spec,
+ open_fip
+ },
+ [BL31_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&bl31_uuid_spec,
+ open_fip
+ },
+ [BL32_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&bl32_uuid_spec,
+ open_fip
+ },
+ [BL33_IMAGE_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&bl33_uuid_spec,
+ open_fip
+ },
+ [TB_FW_CONFIG_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&tb_fw_config_uuid_spec,
+ open_fip
+ },
+ [HW_CONFIG_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&hw_config_uuid_spec,
+ open_fip
+ },
+#if TRUSTED_BOARD_BOOT
+ [TRUSTED_BOOT_FW_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&tb_fw_cert_uuid_spec,
+ open_fip
+ },
+ [TRUSTED_KEY_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&trusted_key_cert_uuid_spec,
+ open_fip
+ },
+ [SCP_FW_KEY_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&fuse_key_cert_uuid_spec,
+ open_fip
+ },
+ [SOC_FW_KEY_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&soc_fw_key_cert_uuid_spec,
+ open_fip
+ },
+ [TRUSTED_OS_FW_KEY_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&tos_fw_key_cert_uuid_spec,
+ open_fip
+ },
+ [NON_TRUSTED_FW_KEY_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&nt_fw_key_cert_uuid_spec,
+ open_fip
+ },
+ [SCP_FW_CONTENT_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&fuse_cert_uuid_spec,
+ open_fip
+ },
+ [SOC_FW_CONTENT_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&soc_fw_cert_uuid_spec,
+ open_fip
+ },
+ [TRUSTED_OS_FW_CONTENT_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&tos_fw_cert_uuid_spec,
+ open_fip
+ },
+ [NON_TRUSTED_FW_CONTENT_CERT_ID] = {
+ &fip_dev_handle,
+ (uintptr_t)&nt_fw_cert_uuid_spec,
+ open_fip
+ },
+#endif /* TRUSTED_BOARD_BOOT */
+};
+
+
+/* Weak definitions may be overridden in specific ARM standard platform */
+#pragma weak plat_io_setup
+
+/*
+ * Return an IO device handle and specification which can be used to access
+ */
+static int open_fip(const uintptr_t spec)
+{
+ int result;
+ uintptr_t local_image_handle;
+
+ /* See if a Firmware Image Package is available */
+ result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
+ if (result == 0) {
+ result = io_open(fip_dev_handle, spec, &local_image_handle);
+ if (result == 0) {
+ VERBOSE("Using FIP\n");
+ io_close(local_image_handle);
+ }
+ }
+ return result;
+}
+
+
+int open_backend(const uintptr_t spec)
+{
+ int result;
+ uintptr_t local_image_handle;
+
+ result = io_dev_init(backend_dev_handle, (uintptr_t)NULL);
+ if (result == 0) {
+ result = io_open(backend_dev_handle, spec, &local_image_handle);
+ if (result == 0) {
+ io_close(local_image_handle);
+ }
+ }
+ return result;
+}
+
+#if defined(SD_BOOT) || defined(EMMC_BOOT)
+static int plat_io_block_setup(size_t fip_offset, uintptr_t block_dev_spec)
+{
+ int io_result;
+
+ fip_block_spec.offset = fip_offset;
+
+ io_result = register_io_dev_block(&backend_dev_con);
+ assert(io_result == 0);
+
+ /* Open connections to devices and cache the handles */
+ io_result = io_dev_open(backend_dev_con, block_dev_spec,
+ &backend_dev_handle);
+ assert(io_result == 0);
+
+ return io_result;
+}
+#endif
+
+#if defined(FLEXSPI_NOR_BOOT) || defined(QSPI_BOOT)
+static int plat_io_memmap_setup(size_t fip_offset)
+{
+ int io_result;
+
+ fip_block_spec.offset = fip_offset;
+
+ io_result = register_io_dev_memmap(&backend_dev_con);
+ assert(io_result == 0);
+
+ /* Open connections to devices and cache the handles */
+ io_result = io_dev_open(backend_dev_con, (uintptr_t)NULL,
+ &backend_dev_handle);
+ assert(io_result == 0);
+
+ return io_result;
+}
+#endif
+
+static int ls_io_fip_setup(unsigned int boot_dev)
+{
+ int io_result;
+
+ io_result = register_io_dev_fip(&fip_dev_con);
+ assert(io_result == 0);
+
+ /* Open connections to devices and cache the handles */
+ io_result = io_dev_open(fip_dev_con, (uintptr_t)&fip_device,
+ &fip_dev_handle);
+ assert(io_result == 0);
+
+#ifdef CONFIG_DDR_FIP_IMAGE
+ /* Open connection to DDR FIP image if available */
+ io_result = ddr_fip_setup(fip_dev_con, boot_dev);
+
+ assert(io_result == 0);
+#endif
+
+#ifdef POLICY_FUSE_PROVISION
+ /* Open connection to FUSE FIP image if available */
+ io_result = fuse_fip_setup(fip_dev_con, boot_dev);
+
+ assert(io_result == 0);
+#endif
+
+ return io_result;
+}
+
+int ls_qspi_io_setup(void)
+{
+#ifdef QSPI_BOOT
+ qspi_io_setup(NXP_QSPI_FLASH_ADDR,
+ NXP_QSPI_FLASH_SIZE,
+ PLAT_FIP_OFFSET);
+ return plat_io_memmap_setup(NXP_QSPI_FLASH_ADDR + PLAT_FIP_OFFSET);
+#else
+ ERROR("QSPI driver not present. Check your BUILD\n");
+
+ /* Should never reach here */
+ assert(false);
+ return -1;
+#endif
+}
+
+int emmc_sdhc2_io_setup(void)
+{
+#if defined(EMMC_BOOT) && defined(NXP_ESDHC2_ADDR)
+ uintptr_t block_dev_spec;
+ int ret;
+
+ ret = sd_emmc_init(&block_dev_spec,
+ NXP_ESDHC2_ADDR,
+ NXP_SD_BLOCK_BUF_ADDR,
+ NXP_SD_BLOCK_BUF_SIZE,
+ false);
+ if (ret != 0) {
+ return ret;
+ }
+
+ return plat_io_block_setup(PLAT_FIP_OFFSET, block_dev_spec);
+#else
+ ERROR("EMMC driver not present. Check your BUILD\n");
+
+ /* Should never reach here */
+ assert(false);
+ return -1;
+#endif
+}
+
+int emmc_io_setup(void)
+{
+/* On the platforms which only has one ESDHC controller,
+ * eMMC-boot will use the first ESDHC controller.
+ */
+#if defined(SD_BOOT) || defined(EMMC_BOOT)
+ uintptr_t block_dev_spec;
+ int ret;
+
+ ret = sd_emmc_init(&block_dev_spec,
+ NXP_ESDHC_ADDR,
+ NXP_SD_BLOCK_BUF_ADDR,
+ NXP_SD_BLOCK_BUF_SIZE,
+ true);
+ if (ret != 0) {
+ return ret;
+ }
+
+ return plat_io_block_setup(PLAT_FIP_OFFSET, block_dev_spec);
+#else
+ ERROR("SD driver not present. Check your BUILD\n");
+
+ /* Should never reach here */
+ assert(false);
+ return -1;
+#endif
+}
+
+int ifc_nor_io_setup(void)
+{
+ ERROR("NOR driver not present. Check your BUILD\n");
+
+ /* Should never reach here */
+ assert(false);
+ return -1;
+}
+
+int ifc_nand_io_setup(void)
+{
+ ERROR("NAND driver not present. Check your BUILD\n");
+
+ /* Should never reach here */
+ assert(false);
+ return -1;
+}
+
+int ls_flexspi_nor_io_setup(void)
+{
+#ifdef FLEXSPI_NOR_BOOT
+ int ret = 0;
+
+ ret = flexspi_nor_io_setup(NXP_FLEXSPI_FLASH_ADDR,
+ NXP_FLEXSPI_FLASH_SIZE,
+ NXP_FLEXSPI_ADDR);
+
+ if (ret != 0) {
+ ERROR("FlexSPI NOR driver initialization error.\n");
+ /* Should never reach here */
+ assert(0);
+ panic();
+ return -1;
+ }
+
+ return plat_io_memmap_setup(NXP_FLEXSPI_FLASH_ADDR + PLAT_FIP_OFFSET);
+#else
+ ERROR("FlexSPI NOR driver not present. Check your BUILD\n");
+
+ /* Should never reach here */
+ assert(false);
+ return -1;
+#endif
+}
+
+static int (* const ls_io_setup_table[])(void) = {
+ [BOOT_DEVICE_IFC_NOR] = ifc_nor_io_setup,
+ [BOOT_DEVICE_IFC_NAND] = ifc_nand_io_setup,
+ [BOOT_DEVICE_QSPI] = ls_qspi_io_setup,
+ [BOOT_DEVICE_EMMC] = emmc_io_setup,
+ [BOOT_DEVICE_SDHC2_EMMC] = emmc_sdhc2_io_setup,
+ [BOOT_DEVICE_FLEXSPI_NOR] = ls_flexspi_nor_io_setup,
+ [BOOT_DEVICE_FLEXSPI_NAND] = ls_flexspi_nor_io_setup,
+};
+
+
+int plat_io_setup(void)
+{
+ int (*io_setup)(void);
+ unsigned int boot_dev = BOOT_DEVICE_NONE;
+ int ret;
+
+ boot_dev = get_boot_dev();
+ if (boot_dev == BOOT_DEVICE_NONE) {
+ ERROR("Boot Device detection failed, Check RCW_SRC\n");
+ return -EINVAL;
+ }
+
+ io_setup = ls_io_setup_table[boot_dev];
+ ret = io_setup();
+ if (ret != 0) {
+ return ret;
+ }
+
+ ret = ls_io_fip_setup(boot_dev);
+ if (ret != 0) {
+ return ret;
+ }
+
+ return 0;
+}
+
+
+/* Return an IO device handle and specification which can be used to access
+ * an image. Use this to enforce platform load policy
+ */
+int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
+ uintptr_t *image_spec)
+{
+ int result = -1;
+ const struct plat_io_policy *policy;
+
+ if (image_id < ARRAY_SIZE(policies)) {
+
+ policy = &policies[image_id];
+ result = policy->check(policy->image_spec);
+ if (result == 0) {
+ *image_spec = policy->image_spec;
+ *dev_handle = *(policy->dev_handle);
+ }
+ }
+#ifdef CONFIG_DDR_FIP_IMAGE
+ else {
+ VERBOSE("Trying alternative IO\n");
+ result = plat_get_ddr_fip_image_source(image_id, dev_handle,
+ image_spec, open_backend);
+ }
+#endif
+#ifdef POLICY_FUSE_PROVISION
+ if (result != 0) {
+ VERBOSE("Trying FUSE IO\n");
+ result = plat_get_fuse_image_source(image_id, dev_handle,
+ image_spec, open_backend);
+ }
+#endif
+
+ return result;
+}
diff --git a/plat/nxp/common/setup/ls_stack_protector.c b/plat/nxp/common/setup/ls_stack_protector.c
new file mode 100644
index 0000000..ab78f88
--- /dev/null
+++ b/plat/nxp/common/setup/ls_stack_protector.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdint.h>
+
+#include <arch_helpers.h>
+
+#include <plat/common/platform.h>
+
+#define RANDOM_CANARY_VALUE ((u_register_t) 3288484550995823360ULL)
+
+u_register_t plat_get_stack_protector_canary(void)
+{
+ /*
+ * TBD: Generate Random Number from NXP CAAM Block.
+ */
+ return RANDOM_CANARY_VALUE ^ read_cntpct_el0();
+}
diff --git a/plat/nxp/common/sip_svc/aarch64/sipsvc.S b/plat/nxp/common/sip_svc/aarch64/sipsvc.S
new file mode 100644
index 0000000..6a47cbf
--- /dev/null
+++ b/plat/nxp/common/sip_svc/aarch64/sipsvc.S
@@ -0,0 +1,152 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <asm_macros.S>
+#include <bl31_data.h>
+
+.global el2_2_aarch32
+.global prefetch_disable
+
+#define SPSR_EL3_M4 0x10
+#define SPSR_EL_MASK 0xC
+#define SPSR_EL2 0x8
+#define SCR_EL3_4_EL2_AARCH32 0x131
+#define SPSR32_EL2_LE 0x1DA
+
+#define MIDR_PARTNUM_START 4
+#define MIDR_PARTNUM_WIDTH 12
+#define MIDR_PARTNUM_A53 0xD03
+#define MIDR_PARTNUM_A57 0xD07
+#define MIDR_PARTNUM_A72 0xD08
+
+/*
+ * uint64_t el2_2_aarch32(u_register_t smc_id,
+ * u_register_t start_addr,
+ * u_register_t parm1,
+ * u_register_t parm2)
+ * this function allows changing the execution width of EL2 from Aarch64
+ * to Aarch32
+ * Note: MUST be called from EL2 @ Aarch64
+ * in: x0 = smc function id
+ * x1 = start address for EL2 @ Aarch32
+ * x2 = first parameter to pass to EL2 @ Aarch32
+ * x3 = second parameter to pass to EL2 @ Aarch32
+ * out: x0 = 0, on success
+ * x0 = -1, on failure
+ * uses x0, x1, x2, x3
+ */
+func el2_2_aarch32
+
+ /* check that caller is EL2 @ Aarch64 - err return if not */
+ mrs x0, spsr_el3
+ /* see if we were called from Aarch32 */
+ tst x0, #SPSR_EL3_M4
+ b.ne 2f
+
+ /* see if we were called from EL2 */
+ and x0, x0, SPSR_EL_MASK
+ cmp x0, SPSR_EL2
+ b.ne 2f
+
+ /* set ELR_EL3 */
+ msr elr_el3, x1
+
+ /* set scr_el3 */
+ mov x0, #SCR_EL3_4_EL2_AARCH32
+ msr scr_el3, x0
+
+ /* set sctlr_el2 */
+ ldr x1, =SCTLR_EL2_RES1
+ msr sctlr_el2, x1
+
+ /* set spsr_el3 */
+ ldr x0, =SPSR32_EL2_LE
+ msr spsr_el3, x0
+
+ /* x2 = parm 1
+ * x3 = parm2
+ */
+
+ /* set the parameters to be passed-thru to EL2 @ Aarch32 */
+ mov x1, x2
+ mov x2, x3
+
+ /* x1 = parm 1
+ * x2 = parm2
+ */
+
+ mov x0, xzr
+ /* invalidate the icache */
+ ic iallu
+ dsb sy
+ isb
+ b 1f
+2:
+ /* error return */
+ mvn x0, xzr
+ ret
+1:
+ eret
+endfunc el2_2_aarch32
+
+/*
+ * int prefetch_disable(u_register_t smc_id, u_register_t mask)
+ * this function marks cores which need to have the prefetch disabled -
+ * secondary cores have prefetch disabled when they are released from reset -
+ * the bootcore has prefetch disabled when this call is made
+ * in: x0 = function id
+ * x1 = core mask, where bit[0]=core0, bit[1]=core1, etc
+ * if a bit in the mask is set, then prefetch is disabled for that
+ * core
+ * out: x0 = SMC_SUCCESS
+ */
+func prefetch_disable
+ stp x4, x30, [sp, #-16]!
+
+ mov x3, x1
+
+ /* x1 = core prefetch disable mask */
+ /* x3 = core prefetch disable mask */
+
+ /* store the mask */
+ mov x0, #PREFETCH_DIS_OFFSET
+ bl _set_global_data
+
+ /* x3 = core prefetch disable mask */
+
+ /* see if we need to disable prefetch on THIS core */
+ bl plat_my_core_mask
+
+ /* x0 = core mask lsb */
+ /* x3 = core prefetch disable mask */
+
+ tst x3, x0
+ b.eq 1f
+
+ /* read midr_el1 */
+ mrs x1, midr_el1
+
+ /* x1 = midr_el1 */
+
+ mov x0, xzr
+ bfxil x0, x1, #MIDR_PARTNUM_START, #MIDR_PARTNUM_WIDTH
+
+ /* x0 = part number (a53, a57, a72, etc) */
+
+ /* branch on cpu-specific */
+ cmp x0, #MIDR_PARTNUM_A57
+ b.eq 1f
+ cmp x0, #MIDR_PARTNUM_A72
+ b.ne 1f
+
+ bl _disable_ldstr_pfetch_A72
+ b 1f
+1:
+ ldp x4, x30, [sp], #16
+ mov x0, xzr
+ ret
+endfunc prefetch_disable
diff --git a/plat/nxp/common/sip_svc/include/sipsvc.h b/plat/nxp/common/sip_svc/include/sipsvc.h
new file mode 100644
index 0000000..d9e61e9
--- /dev/null
+++ b/plat/nxp/common/sip_svc/include/sipsvc.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef SIPSVC_H
+#define SIPSVC_H
+
+#include <stdint.h>
+
+#define SMC_FUNC_MASK 0x0000ffff
+#define SMC32_PARAM_MASK 0xffffffff
+
+/* SMC function IDs for SiP Service queries */
+#define SIP_SVC_CALL_COUNT 0xff00
+#define SIP_SVC_UID 0xff01
+#define SIP_SVC_VERSION 0xff03
+#define SIP_SVC_PRNG 0xff10
+#define SIP_SVC_RNG 0xff11
+#define SIP_SVC_MEM_BANK 0xff12
+#define SIP_SVC_PREFETCH_DIS 0xff13
+#define SIP_SVC_HUK 0xff14
+#define SIP_SVC_ALLOW_L1L2_ERR 0xff15
+#define SIP_SVC_ALLOW_L2_CLR 0xff16
+#define SIP_SVC_2_AARCH32 0xff17
+#define SIP_SVC_PORSR1 0xff18
+
+/* Layerscape SiP Service Calls version numbers */
+#define LS_SIP_SVC_VERSION_MAJOR 0x0
+#define LS_SIP_SVC_VERSION_MINOR 0x1
+
+/* Number of Layerscape SiP Calls implemented */
+#define LS_COMMON_SIP_NUM_CALLS 10
+
+/* Parameter Type Constants */
+#define SIP_PARAM_TYPE_NONE 0x0
+#define SIP_PARAM_TYPE_VALUE_INPUT 0x1
+#define SIP_PARAM_TYPE_VALUE_OUTPUT 0x2
+#define SIP_PARAM_TYPE_VALUE_INOUT 0x3
+#define SIP_PARAM_TYPE_MEMREF_INPUT 0x5
+#define SIP_PARAM_TYPE_MEMREF_OUTPUT 0x6
+#define SIP_PARAM_TYPE_MEMREF_INOUT 0x7
+
+#define SIP_PARAM_TYPE_MASK 0xF
+
+/*
+ * The macro SIP_PARAM_TYPES can be used to construct a value that you can
+ * compare against an incoming paramTypes to check the type of all the
+ * parameters in one comparison.
+ */
+#define SIP_PARAM_TYPES(t0, t1, t2, t3) \
+ ((t0) | ((t1) << 4) | ((t2) << 8) | ((t3) << 12))
+
+/*
+ * The macro SIP_PARAM_TYPE_GET can be used to extract the type of a given
+ * parameter from paramTypes if you need more fine-grained type checking.
+ */
+#define SIP_PARAM_TYPE_GET(t, i) ((((uint32_t)(t)) >> ((i) * 4)) & 0xF)
+
+/*
+ * The macro SIP_PARAM_TYPE_SET can be used to load the type of a given
+ * parameter from paramTypes without specifying all types (SIP_PARAM_TYPES)
+ */
+#define SIP_PARAM_TYPE_SET(t, i) (((uint32_t)(t) & 0xF) << ((i) * 4))
+
+#define SIP_SVC_RNG_PARAMS (SIP_PARAM_TYPE_VALUE_INPUT, \
+ SIP_PARAM_TYPE_MEMREF_OUTPUT, \
+ SIP_PARAM_TYPE_NONE, \
+ SIP_PARAM_TYPE_NONE)
+
+/* Layerscape SiP Calls error code */
+enum {
+ LS_SIP_SUCCESS = 0,
+ LS_SIP_INVALID_PARAM = -1,
+ LS_SIP_NOT_SUPPORTED = -2,
+};
+
+#endif /* SIPSVC_H */
diff --git a/plat/nxp/common/sip_svc/sip_svc.c b/plat/nxp/common/sip_svc/sip_svc.c
new file mode 100644
index 0000000..1c8668e
--- /dev/null
+++ b/plat/nxp/common/sip_svc/sip_svc.c
@@ -0,0 +1,194 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <assert.h>
+#include <string.h>
+
+#include <caam.h>
+#include <common/runtime_svc.h>
+#include <dcfg.h>
+#include <lib/mmio.h>
+#include <tools_share/uuid.h>
+
+#include <plat_common.h>
+#include <sipsvc.h>
+
+/* Layerscape SiP Service UUID */
+DEFINE_SVC_UUID2(nxp_sip_svc_uid,
+ 0x871de4ef, 0xedfc, 0x4209, 0xa4, 0x23,
+ 0x8d, 0x23, 0x75, 0x9d, 0x3b, 0x9f);
+
+#pragma weak nxp_plat_sip_handler
+static uintptr_t nxp_plat_sip_handler(unsigned int smc_fid,
+ u_register_t x1,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *cookie,
+ void *handle,
+ u_register_t flags)
+{
+ ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
+ SMC_RET1(handle, SMC_UNK);
+}
+
+uint64_t el2_2_aarch32(u_register_t smc_id, u_register_t start_addr,
+ u_register_t parm1, u_register_t parm2);
+
+uint64_t prefetch_disable(u_register_t smc_id, u_register_t mask);
+uint64_t bl31_get_porsr1(void);
+
+static void clean_top_32b_of_param(uint32_t smc_fid,
+ u_register_t *px1,
+ u_register_t *px2,
+ u_register_t *px3,
+ u_register_t *px4)
+{
+ /* if parameters from SMC32. Clean top 32 bits */
+ if (GET_SMC_CC(smc_fid) == SMC_32) {
+ *px1 = *px1 & SMC32_PARAM_MASK;
+ *px2 = *px2 & SMC32_PARAM_MASK;
+ *px3 = *px3 & SMC32_PARAM_MASK;
+ *px4 = *px4 & SMC32_PARAM_MASK;
+ }
+}
+
+/* This function handles Layerscape defined SiP Calls */
+static uintptr_t nxp_sip_handler(unsigned int smc_fid,
+ u_register_t x1,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *cookie,
+ void *handle,
+ u_register_t flags)
+{
+ uint32_t ns;
+ uint64_t ret;
+ dram_regions_info_t *info_dram_regions;
+
+ /* if parameter is sent from SMC32. Clean top 32 bits */
+ clean_top_32b_of_param(smc_fid, &x1, &x2, &x3, &x4);
+
+ /* Determine which security state this SMC originated from */
+ ns = is_caller_non_secure(flags);
+ if (ns == 0) {
+ /* SiP SMC service secure world's call */
+ ;
+ } else {
+ /* SiP SMC service normal world's call */
+ ;
+ }
+
+ switch (smc_fid & SMC_FUNC_MASK) {
+ case SIP_SVC_RNG:
+ if (is_sec_enabled() == false) {
+ NOTICE("SEC is disabled.\n");
+ SMC_RET1(handle, SMC_UNK);
+ }
+
+ /* Return zero on failure */
+ ret = get_random((int)x1);
+ if (ret != 0) {
+ SMC_RET2(handle, SMC_OK, ret);
+ } else {
+ SMC_RET1(handle, SMC_UNK);
+ }
+ /* break is not required as SMC_RETx return */
+ case SIP_SVC_HUK:
+ if (is_sec_enabled() == false) {
+ NOTICE("SEC is disabled.\n");
+ SMC_RET1(handle, SMC_UNK);
+ }
+ ret = get_hw_unq_key_blob_hw((uint8_t *) x1, (uint32_t) x2);
+
+ if (ret == SMC_OK) {
+ SMC_RET1(handle, SMC_OK);
+ } else {
+ SMC_RET1(handle, SMC_UNK);
+ }
+ /* break is not required as SMC_RETx return */
+ case SIP_SVC_MEM_BANK:
+ VERBOSE("Handling SMC SIP_SVC_MEM_BANK.\n");
+ info_dram_regions = get_dram_regions_info();
+
+ if (x1 == -1) {
+ SMC_RET2(handle, SMC_OK,
+ info_dram_regions->total_dram_size);
+ } else if (x1 >= info_dram_regions->num_dram_regions) {
+ SMC_RET1(handle, SMC_UNK);
+ } else {
+ SMC_RET3(handle, SMC_OK,
+ info_dram_regions->region[x1].addr,
+ info_dram_regions->region[x1].size);
+ }
+ /* break is not required as SMC_RETx return */
+ case SIP_SVC_PREFETCH_DIS:
+ VERBOSE("In SIP_SVC_PREFETCH_DIS call\n");
+ ret = prefetch_disable(smc_fid, x1);
+ if (ret == SMC_OK) {
+ SMC_RET1(handle, SMC_OK);
+ } else {
+ SMC_RET1(handle, SMC_UNK);
+ }
+ /* break is not required as SMC_RETx return */
+ case SIP_SVC_2_AARCH32:
+ ret = el2_2_aarch32(smc_fid, x1, x2, x3);
+
+ /* In success case, control should not reach here. */
+ NOTICE("SMC: SIP_SVC_2_AARCH32 Failed.\n");
+ SMC_RET1(handle, SMC_UNK);
+ /* break is not required as SMC_RETx return */
+ case SIP_SVC_PORSR1:
+ ret = bl31_get_porsr1();
+ SMC_RET2(handle, SMC_OK, ret);
+ /* break is not required as SMC_RETx return */
+ default:
+ return nxp_plat_sip_handler(smc_fid, x1, x2, x3, x4,
+ cookie, handle, flags);
+ }
+}
+
+/* This function is responsible for handling all SiP calls */
+static uintptr_t sip_smc_handler(unsigned int smc_fid,
+ u_register_t x1,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *cookie,
+ void *handle,
+ u_register_t flags)
+{
+ switch (smc_fid & SMC_FUNC_MASK) {
+ case SIP_SVC_CALL_COUNT:
+ /* Return the number of Layerscape SiP Service Calls. */
+ SMC_RET1(handle, LS_COMMON_SIP_NUM_CALLS);
+ break;
+ case SIP_SVC_UID:
+ /* Return UID to the caller */
+ SMC_UUID_RET(handle, nxp_sip_svc_uid);
+ break;
+ case SIP_SVC_VERSION:
+ /* Return the version of current implementation */
+ SMC_RET2(handle, LS_SIP_SVC_VERSION_MAJOR,
+ LS_SIP_SVC_VERSION_MINOR);
+ break;
+ default:
+ return nxp_sip_handler(smc_fid, x1, x2, x3, x4,
+ cookie, handle, flags);
+ }
+}
+
+/* Define a runtime service descriptor for fast SMC calls */
+DECLARE_RT_SVC(
+ nxp_sip_svc,
+ OEN_SIP_START,
+ OEN_SIP_END,
+ SMC_TYPE_FAST,
+ NULL,
+ sip_smc_handler
+);
diff --git a/plat/nxp/common/sip_svc/sipsvc.mk b/plat/nxp/common/sip_svc/sipsvc.mk
new file mode 100644
index 0000000..c3a57de
--- /dev/null
+++ b/plat/nxp/common/sip_svc/sipsvc.mk
@@ -0,0 +1,35 @@
+#
+# Copyright 2018-2020 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+#------------------------------------------------------------------------------
+#
+# Select the SIP SVC files
+#
+# -----------------------------------------------------------------------------
+
+ifeq (${ADD_SIPSVC},)
+
+ADD_SIPSVC := 1
+
+PLAT_SIPSVC_PATH := $(PLAT_COMMON_PATH)/sip_svc
+
+SIPSVC_SOURCES := ${PLAT_SIPSVC_PATH}/sip_svc.c \
+ ${PLAT_SIPSVC_PATH}/$(ARCH)/sipsvc.S
+
+PLAT_INCLUDES += -I${PLAT_SIPSVC_PATH}/include
+
+ifeq (${BL_COMM_SIPSVC_NEEDED},yes)
+BL_COMMON_SOURCES += ${SIPSVC_SOURCES}
+else
+ifeq (${BL2_SIPSVC_NEEDED},yes)
+BL2_SOURCES += ${SIPSVC_SOURCES}
+endif
+ifeq (${BL31_SIPSVC_NEEDED},yes)
+BL31_SOURCES += ${SIPSVC_SOURCES}
+endif
+endif
+endif
+# -----------------------------------------------------------------------------
diff --git a/plat/nxp/common/soc_errata/errata.c b/plat/nxp/common/soc_errata/errata.c
new file mode 100644
index 0000000..fb1818a
--- /dev/null
+++ b/plat/nxp/common/soc_errata/errata.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <common/debug.h>
+
+#include "errata_list.h"
+
+void soc_errata(void)
+{
+#ifdef ERRATA_SOC_A050426
+ INFO("SoC workaround for Errata A050426 was applied\n");
+ erratum_a050426();
+#endif
+ /*
+ * The following DDR Erratas workaround are implemented in DDR driver,
+ * but print information here.
+ */
+#if ERRATA_DDR_A011396
+ INFO("SoC workaround for DDR Errata A011396 was applied\n");
+#endif
+#if ERRATA_DDR_A050450
+ INFO("SoC workaround for DDR Errata A050450 was applied\n");
+#endif
+}
diff --git a/plat/nxp/common/soc_errata/errata.h b/plat/nxp/common/soc_errata/errata.h
new file mode 100644
index 0000000..b543b4b
--- /dev/null
+++ b/plat/nxp/common/soc_errata/errata.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2020-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef ERRATA_H
+#define ERRATA_H
+
+void soc_errata(void);
+
+#endif /* ERRATA_H */
diff --git a/plat/nxp/common/soc_errata/errata.mk b/plat/nxp/common/soc_errata/errata.mk
new file mode 100644
index 0000000..2942615
--- /dev/null
+++ b/plat/nxp/common/soc_errata/errata.mk
@@ -0,0 +1,23 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Platform Errata Build flags.
+# These should be enabled by the platform if the erratum workaround needs to be
+# applied.
+
+ERRATA := \
+ ERRATA_SOC_A050426
+
+define enable_errata
+ $(1) ?= 0
+ ifeq ($$($(1)),1)
+ $$(eval $$(call add_define,$(1)))
+ BL2_SOURCES += $(PLAT_COMMON_PATH)/soc_errata/errata_a$(shell echo $(1)|awk -F '_A' '{print $$NF}').c
+ endif
+endef
+
+$(foreach e,$(ERRATA),$(eval $(call enable_errata,$(strip $(e)))))
+
+BL2_SOURCES += $(PLAT_COMMON_PATH)/soc_errata/errata.c
diff --git a/plat/nxp/common/soc_errata/errata_a050426.c b/plat/nxp/common/soc_errata/errata_a050426.c
new file mode 100644
index 0000000..13a0000
--- /dev/null
+++ b/plat/nxp/common/soc_errata/errata_a050426.c
@@ -0,0 +1,415 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <mmio.h>
+
+void erratum_a050426(void)
+{
+ uint32_t i, val3, val4;
+
+ /* Enable BIST to access Internal memory locations */
+ val3 = mmio_read_32(0x700117E60);
+ mmio_write_32(0x700117E60, (val3 | 0x80000001));
+ val4 = mmio_read_32(0x700117E90);
+ mmio_write_32(0x700117E90, (val4 & 0xFFDFFFFF));
+
+ /* wriop Internal Memory.*/
+ for (i = 0U; i < 4U; i++) {
+ mmio_write_32(0x706312000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706312400 + (i * 4), 0x55555555);
+ mmio_write_32(0x706312800 + (i * 4), 0x55555555);
+ mmio_write_32(0x706314000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706314400 + (i * 4), 0x55555555);
+ mmio_write_32(0x706314800 + (i * 4), 0x55555555);
+ mmio_write_32(0x706314c00 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 3U; i++) {
+ mmio_write_32(0x706316000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706320000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706320400 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 2U; i++) {
+ mmio_write_32(0x70640a000 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 3U; i++) {
+ mmio_write_32(0x706518000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706519000 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 4U; i++) {
+ mmio_write_32(0x706522000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706522800 + (i * 4), 0x55555555);
+ mmio_write_32(0x706523000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706523800 + (i * 4), 0x55555555);
+ mmio_write_32(0x706524000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706524800 + (i * 4), 0x55555555);
+ mmio_write_32(0x706608000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706608800 + (i * 4), 0x55555555);
+ mmio_write_32(0x706609000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706609800 + (i * 4), 0x55555555);
+ mmio_write_32(0x70660a000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70660a800 + (i * 4), 0x55555555);
+ mmio_write_32(0x70660b000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70660b800 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 3U; i++) {
+ mmio_write_32(0x70660c000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70660c800 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 2U; i++) {
+ mmio_write_32(0x706718000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706718800 + (i * 4), 0x55555555);
+ }
+ mmio_write_32(0x706b0a000 + (i * 4), 0x55555555);
+
+ for (i = 0U; i < 4U; i++) {
+ mmio_write_32(0x706b0e000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706b0e800 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 2U; i++) {
+ mmio_write_32(0x706b10000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706b10400 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 4U; i++) {
+ mmio_write_32(0x706b14000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706b14800 + (i * 4), 0x55555555);
+ mmio_write_32(0x706b15000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706b15800 + (i * 4), 0x55555555);
+ }
+ mmio_write_32(0x706e12000 + (i * 4), 0x55555555);
+
+ for (i = 0U; i < 4U; i++) {
+ mmio_write_32(0x706e14000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706e14800 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 2U; i++) {
+ mmio_write_32(0x706e16000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706e16400 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 3U; i++) {
+ mmio_write_32(0x706e1a000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706e1a800 + (i * 4), 0x55555555);
+ mmio_write_32(0x706e1b000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706e1b800 + (i * 4), 0x55555555);
+ mmio_write_32(0x706e1c000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706e1c800 + (i * 4), 0x55555555);
+ mmio_write_32(0x706e1e000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706e1e800 + (i * 4), 0x55555555);
+ mmio_write_32(0x706e1f000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706e1f800 + (i * 4), 0x55555555);
+ mmio_write_32(0x706e20000 + (i * 4), 0x55555555);
+ mmio_write_32(0x706e20800 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 4U; i++) {
+ mmio_write_32(0x707108000 + (i * 4), 0x55555555);
+ mmio_write_32(0x707109000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70710a000 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 2U; i++) {
+ mmio_write_32(0x70711c000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70711c800 + (i * 4), 0x55555555);
+ mmio_write_32(0x70711d000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70711d800 + (i * 4), 0x55555555);
+ mmio_write_32(0x70711e000 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 4U; i++) {
+ mmio_write_32(0x707120000 + (i * 4), 0x55555555);
+ mmio_write_32(0x707121000 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 3U; i++) {
+ mmio_write_32(0x707122000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70725a000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70725b000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70725c000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70725e000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70725e400 + (i * 4), 0x55555555);
+ mmio_write_32(0x70725e800 + (i * 4), 0x55555555);
+ mmio_write_32(0x70725ec00 + (i * 4), 0x55555555);
+ mmio_write_32(0x70725f000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70725f400 + (i * 4), 0x55555555);
+ mmio_write_32(0x707340000 + (i * 4), 0x55555555);
+ mmio_write_32(0x707346000 + (i * 4), 0x55555555);
+ mmio_write_32(0x707484000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70748a000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70748b000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70748c000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70748d000 + (i * 4), 0x55555555);
+ }
+
+ /* EDMA Internal Memory.*/
+ for (i = 0U; i < 5U; i++) {
+ mmio_write_32(0x70a208000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70a208800 + (i * 4), 0x55555555);
+ mmio_write_32(0x70a209000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70a209800 + (i * 4), 0x55555555);
+ }
+
+ /* PEX1 Internal Memory.*/
+ for (i = 0U; i < 3U; i++) {
+ mmio_write_32(0x70a508000 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 5U; i++) {
+ mmio_write_32(0x70a520000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70a528000 + (i * 4), 0x55555555);
+ }
+
+ /* PEX2 Internal Memory.*/
+ for (i = 0U; i < 3U; i++) {
+ mmio_write_32(0x70a608000 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 5U; i++) {
+ mmio_write_32(0x70a620000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70a628000 + (i * 4), 0x55555555);
+ }
+
+ /* PEX3 Internal Memory.*/
+ for (i = 0U; i < 5U; i++) {
+ mmio_write_32(0x70a708000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70a728000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70a730000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70a738000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70a748000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70a758000 + (i * 4), 0x55555555);
+ }
+
+ /* PEX4 Internal Memory.*/
+ for (i = 0U; i < 3U; i++) {
+ mmio_write_32(0x70a808000 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 5U; i++) {
+ mmio_write_32(0x70a820000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70a828000 + (i * 4), 0x55555555);
+ }
+
+ /* PEX5 Internal Memory.*/
+ for (i = 0U; i < 5U; i++) {
+ mmio_write_32(0x70aa08000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70aa28000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70aa30000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70aa38000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70aa48000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70aa58000 + (i * 4), 0x55555555);
+ }
+
+ /* PEX6 Internal Memory.*/
+ for (i = 0U; i < 3U; i++) {
+ mmio_write_32(0x70ab08000 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 5U; i++) {
+ mmio_write_32(0x70ab20000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70ab28000 + (i * 4), 0x55555555);
+ }
+
+ /* QDMA Internal Memory.*/
+ for (i = 0U; i < 5U; i++) {
+ mmio_write_32(0x70b008000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b00c000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b010000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b014000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b018000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b018400 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b01a000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b01a400 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b01c000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b01d000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b01e000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b01e800 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b01f000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b01f800 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b020000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b020400 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b020800 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b020c00 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b022000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b022400 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b024000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b024800 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b025000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b025800 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 4U; i++) {
+ mmio_write_32(0x70b026000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b026200 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 5U; i++) {
+ mmio_write_32(0x70b028000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b028800 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b029000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70b029800 + (i * 4), 0x55555555);
+ }
+
+ /* lnx1_e1000#0 Internal Memory.*/
+ for (i = 0U; i < 3U; i++) {
+ mmio_write_32(0x70c00a000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c00a200 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c00a400 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c00a600 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c00a800 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c00aa00 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c00ac00 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c00ae00 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c00b000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c00b200 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c00b400 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c00b600 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c00b800 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c00ba00 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c00bc00 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c00be00 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 5U; i++) {
+ mmio_write_32(0x70c00c000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c00c400 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c00c800 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c00cc00 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c00d000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c00d400 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c00d800 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c00dc00 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 3U; i++) {
+ mmio_write_32(0x70c00e000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c00f000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c012000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c012200 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c012400 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c012600 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c012800 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c012a00 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c012c00 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c012e00 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c013000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c013200 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c013400 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c013600 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c013800 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c013a00 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c013c00 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c013e00 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 5U; i++) {
+ mmio_write_32(0x70c014000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c014400 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c014800 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c014c00 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c015000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c015400 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c015800 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c015c00 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 3U; i++) {
+ mmio_write_32(0x70c016000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c017000 + (i * 4), 0x55555555);
+ }
+
+ /* lnx1_xfi Internal Memory.*/
+ for (i = 0U; i < 3U; i++) {
+ mmio_write_32(0x70c108000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c108200 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c10a000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c10a400 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 5U; i++) {
+ mmio_write_32(0x70c10c000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c10c400 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 3U; i++) {
+ mmio_write_32(0x70c10e000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c10e200 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c110000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c110400 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 5U; i++) {
+ mmio_write_32(0x70c112000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c112400 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 3U; i++) {
+ mmio_write_32(0x70c114000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c114200 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c116000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c116400 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 5U; i++) {
+ mmio_write_32(0x70c118000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c118400 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 3U; i++) {
+ mmio_write_32(0x70c11a000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c11a200 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c11c000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c11c400 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 5U; i++) {
+ mmio_write_32(0x70c11e000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c11e400 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 3U; i++) {
+ mmio_write_32(0x70c120000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c120200 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c122000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c122400 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 5U; i++) {
+ mmio_write_32(0x70c124000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c124400 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 3U; i++) {
+ mmio_write_32(0x70c126000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c126200 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c128000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c128400 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 5U; i++) {
+ mmio_write_32(0x70c12a000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c12a400 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 3U; i++) {
+ mmio_write_32(0x70c12c000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c12c200 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c12e000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c12e400 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 5U; i++) {
+ mmio_write_32(0x70c130000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c130400 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 3U; i++) {
+ mmio_write_32(0x70c132000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c132200 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c134000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c134400 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 5U; i++) {
+ mmio_write_32(0x70c136000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c136400 + (i * 4), 0x55555555);
+ }
+
+ /* lnx2_xfi Internal Memory.*/
+ for (i = 0U; i < 3U; i++) {
+ mmio_write_32(0x70c308000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c308200 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c30a000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c30a400 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 5U; i++) {
+ mmio_write_32(0x70c30c000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c30c400 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 3U; i++) {
+ mmio_write_32(0x70c30e000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c30e200 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c310000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c310400 + (i * 4), 0x55555555);
+ }
+ for (i = 0U; i < 5U; i++) {
+ mmio_write_32(0x70c312000 + (i * 4), 0x55555555);
+ mmio_write_32(0x70c312400 + (i * 4), 0x55555555);
+ }
+
+ /* Disable BIST */
+ mmio_write_32(0x700117E60, val3);
+ mmio_write_32(0x700117E90, val4);
+}
diff --git a/plat/nxp/common/soc_errata/errata_list.h b/plat/nxp/common/soc_errata/errata_list.h
new file mode 100644
index 0000000..74d2315
--- /dev/null
+++ b/plat/nxp/common/soc_errata/errata_list.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef ERRATA_LIST_H
+#define ERRATA_LIST_H
+
+#ifdef ERRATA_SOC_A050426
+void erratum_a050426(void);
+#endif
+
+#endif /* ERRATA_LIST_H */
diff --git a/plat/nxp/common/tbbr/csf_tbbr.c b/plat/nxp/common/tbbr/csf_tbbr.c
new file mode 100644
index 0000000..8f38f3e
--- /dev/null
+++ b/plat/nxp/common/tbbr/csf_tbbr.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ *
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+#include <csf_hdr.h>
+#include <dcfg.h>
+#include <drivers/auth/crypto_mod.h>
+#include <snvs.h>
+
+#include <plat/common/platform.h>
+#include "plat_common.h"
+
+extern bool rotpk_not_dpld;
+extern uint8_t rotpk_hash_table[MAX_KEY_ENTRIES][SHA256_BYTES];
+extern uint32_t num_rotpk_hash_entries;
+
+/*
+ * In case of secure boot, return ptr of rotpk_hash table in key_ptr and
+ * number of hashes in key_len
+ */
+int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
+ unsigned int *flags)
+{
+ uint32_t mode = 0U;
+ *flags = ROTPK_NOT_DEPLOYED;
+
+ /* ROTPK hash table must be available for secure boot */
+ if (rotpk_not_dpld == true) {
+ if (check_boot_mode_secure(&mode) == true) {
+ /* Production mode, don;t continue further */
+ if (mode == 1U) {
+ return -EAUTH;
+ }
+
+ /* For development mode, rotpk flag false
+ * indicates that SRK hash comparison might
+ * have failed. This is not fatal error.
+ * Continue in this case but transition SNVS
+ * to non-secure state
+ */
+ transition_snvs_non_secure();
+ return 0;
+ } else {
+ return 0;
+ }
+ }
+
+ /*
+ * We return the complete hash table and number of entries in
+ * table for NXP platform specific implementation.
+ * Here hash is always assume as SHA-256
+ */
+ *key_ptr = rotpk_hash_table;
+ *key_len = num_rotpk_hash_entries;
+ *flags = ROTPK_IS_HASH;
+
+ return 0;
+}
+
+int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr)
+{
+ /*
+ * No support for non-volatile counter. Update the ROT key to protect
+ * the system against rollback.
+ */
+ *nv_ctr = 0U;
+
+ return 0;
+}
+
+int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr)
+{
+ return 0;
+}
diff --git a/plat/nxp/common/tbbr/nxp_rotpk.S b/plat/nxp/common/tbbr/nxp_rotpk.S
new file mode 100644
index 0000000..8e084d1
--- /dev/null
+++ b/plat/nxp/common/tbbr/nxp_rotpk.S
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ *
+ */
+
+#ifndef _CSF_HDR_H_
+
+ .global nxp_rotpk_hash
+ .global nxp_rotpk_hash_end
+ .section .rodata.nxp_rotpk_hash, "a"
+nxp_rotpk_hash:
+ /* DER header */
+ .byte 0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86, 0x48
+ .byte 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, 0x00, 0x04, 0x20
+ /* SHA256 */
+ .incbin ROTPK_HASH
+nxp_rotpk_hash_end:
+#endif
diff --git a/plat/nxp/common/tbbr/tbbr.mk b/plat/nxp/common/tbbr/tbbr.mk
new file mode 100644
index 0000000..25852ba
--- /dev/null
+++ b/plat/nxp/common/tbbr/tbbr.mk
@@ -0,0 +1,155 @@
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# For TRUSTED_BOARD_BOOT platforms need to include this makefile
+# Following definations are to be provided by platform.mk file or
+# by user - BL33_INPUT_FILE, BL32_INPUT_FILE, BL31_INPUT_FILE
+
+ifeq ($(CHASSIS), 2)
+include $(PLAT_DRIVERS_PATH)/csu/csu.mk
+CSF_FILE := input_blx_ch${CHASSIS}
+BL2_CSF_FILE := input_bl2_ch${CHASSIS}
+else
+ifeq ($(CHASSIS), 3_2)
+CSF_FILE := input_blx_ch3
+BL2_CSF_FILE := input_bl2_ch${CHASSIS}
+PBI_CSF_FILE := input_pbi_ch${CHASSIS}
+$(eval $(call add_define, CSF_HDR_CH3))
+else
+ $(error -> CHASSIS not set!)
+endif
+endif
+
+PLAT_AUTH_PATH := $(PLAT_DRIVERS_PATH)/auth
+
+
+ifeq (${BL2_INPUT_FILE},)
+ BL2_INPUT_FILE := $(PLAT_AUTH_PATH)/csf_hdr_parser/${BL2_CSF_FILE}
+endif
+
+ifeq (${PBI_INPUT_FILE},)
+ PBI_INPUT_FILE := $(PLAT_AUTH_PATH)/csf_hdr_parser/${PBI_CSF_FILE}
+endif
+
+# If MBEDTLS_DIR is not specified, use CSF Header option
+ifeq (${MBEDTLS_DIR},)
+ # Generic image processing filters to prepend CSF header
+ ifeq (${BL33_INPUT_FILE},)
+ BL33_INPUT_FILE := $(PLAT_AUTH_PATH)/csf_hdr_parser/${CSF_FILE}
+ endif
+
+ ifeq (${BL31_INPUT_FILE},)
+ BL31_INPUT_FILE := $(PLAT_AUTH_PATH)/csf_hdr_parser/${CSF_FILE}
+ endif
+
+ ifeq (${BL32_INPUT_FILE},)
+ BL32_INPUT_FILE := $(PLAT_AUTH_PATH)/csf_hdr_parser/${CSF_FILE}
+ endif
+
+ ifeq (${FUSE_INPUT_FILE},)
+ FUSE_INPUT_FILE := $(PLAT_AUTH_PATH)/csf_hdr_parser/${CSF_FILE}
+ endif
+
+ PLAT_INCLUDES += -I$(PLAT_DRIVERS_PATH)/sfp
+ PLAT_TBBR_SOURCES += $(PLAT_AUTH_PATH)/csf_hdr_parser/cot.c \
+ $(PLAT_COMMON_PATH)/tbbr/csf_tbbr.c
+ # IMG PARSER here is CSF header parser
+ include $(PLAT_DRIVERS_PATH)/auth/csf_hdr_parser/csf_hdr.mk
+ PLAT_TBBR_SOURCES += $(CSF_HDR_SOURCES)
+
+ SCP_BL2_PRE_TOOL_FILTER := CST_SCP_BL2
+ BL31_PRE_TOOL_FILTER := CST_BL31
+ BL32_PRE_TOOL_FILTER := CST_BL32
+ BL33_PRE_TOOL_FILTER := CST_BL33
+else
+
+ ifeq (${DISABLE_FUSE_WRITE}, 1)
+ $(eval $(call add_define,DISABLE_FUSE_WRITE))
+ endif
+
+ # For Mbedtls currently crypto is not supported via CAAM
+ # enable it when that support is there
+ CAAM_INTEG := 0
+ KEY_ALG := rsa
+ KEY_SIZE := 2048
+
+ $(eval $(call add_define,MBEDTLS_X509))
+ ifeq (${PLAT_DDR_PHY},PHY_GEN2)
+ $(eval $(call add_define,PLAT_DEF_OID))
+ endif
+ include drivers/auth/mbedtls/mbedtls_x509.mk
+
+
+ PLAT_TBBR_SOURCES += $(PLAT_AUTH_PATH)/tbbr/tbbr_cot.c \
+ $(PLAT_COMMON_PATH)/tbbr/nxp_rotpk.S \
+ $(PLAT_COMMON_PATH)/tbbr/x509_tbbr.c
+
+ #ROTPK key is embedded in BL2 image
+ ifeq (${ROT_KEY},)
+ ROT_KEY = $(BUILD_PLAT)/rot_key.pem
+ endif
+
+ ifeq (${SAVE_KEYS},1)
+
+ ifeq (${TRUSTED_WORLD_KEY},)
+ TRUSTED_WORLD_KEY = ${BUILD_PLAT}/trusted.pem
+ endif
+
+ ifeq (${NON_TRUSTED_WORLD_KEY},)
+ NON_TRUSTED_WORLD_KEY = ${BUILD_PLAT}/non-trusted.pem
+ endif
+
+ ifeq (${BL31_KEY},)
+ BL31_KEY = ${BUILD_PLAT}/soc.pem
+ endif
+
+ ifeq (${BL32_KEY},)
+ BL32_KEY = ${BUILD_PLAT}/trusted_os.pem
+ endif
+
+ ifeq (${BL33_KEY},)
+ BL33_KEY = ${BUILD_PLAT}/non-trusted_os.pem
+ endif
+
+ endif
+
+ ROTPK_HASH = $(BUILD_PLAT)/rotpk_sha256.bin
+
+ $(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
+
+ $(BUILD_PLAT)/bl2/nxp_rotpk.o: $(ROTPK_HASH)
+
+ certificates: $(ROT_KEY)
+ $(ROT_KEY): | $(BUILD_PLAT)
+ @echo " OPENSSL $@"
+ @if [ ! -f $(ROT_KEY) ]; then \
+ openssl genrsa 2048 > $@ 2>/dev/null; \
+ fi
+
+ $(ROTPK_HASH): $(ROT_KEY)
+ @echo " OPENSSL $@"
+ $(Q)openssl rsa -in $< -pubout -outform DER 2>/dev/null |\
+ openssl dgst -sha256 -binary > $@ 2>/dev/null
+
+endif #MBEDTLS_DIR
+
+PLAT_INCLUDES += -Iinclude/common/tbbr
+
+# Generic files for authentication framework
+TBBR_SOURCES += drivers/auth/auth_mod.c \
+ drivers/auth/crypto_mod.c \
+ drivers/auth/img_parser_mod.c \
+ plat/common/tbbr/plat_tbbr.c \
+ ${PLAT_TBBR_SOURCES}
+
+# If CAAM_INTEG is not defined (would be scenario with MBED TLS)
+# include mbedtls_crypto
+ifeq (${CAAM_INTEG},0)
+ include drivers/auth/mbedtls/mbedtls_crypto.mk
+else
+ include $(PLAT_DRIVERS_PATH)/crypto/caam/src/auth/auth.mk
+ TBBR_SOURCES += ${AUTH_SOURCES}
+endif
diff --git a/plat/nxp/common/tbbr/x509_tbbr.c b/plat/nxp/common/tbbr/x509_tbbr.c
new file mode 100644
index 0000000..ec87674
--- /dev/null
+++ b/plat/nxp/common/tbbr/x509_tbbr.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <assert.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <lib/cassert.h>
+#include <sfp.h>
+#include <tools_share/tbbr_oid.h>
+
+#include <plat/common/platform.h>
+#include "plat_common.h"
+
+extern char nxp_rotpk_hash[], nxp_rotpk_hash_end[];
+
+int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
+ unsigned int *flags)
+{
+ *key_ptr = nxp_rotpk_hash;
+ *key_len = nxp_rotpk_hash_end - nxp_rotpk_hash;
+ *flags = ROTPK_IS_HASH;
+
+ return 0;
+}
+
+int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr)
+{
+ const char *oid;
+ uint32_t uid_num;
+ uint32_t val = 0U;
+
+ assert(cookie != NULL);
+ assert(nv_ctr != NULL);
+
+ oid = (const char *)cookie;
+ if (strcmp(oid, TRUSTED_FW_NVCOUNTER_OID) == 0) {
+ uid_num = 3U;
+ } else if (strcmp(oid, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) {
+ uid_num = 4U;
+ } else {
+ return 1;
+ }
+
+ val = sfp_read_oem_uid(uid_num);
+
+ INFO("SFP Value read is %x from UID %d\n", val, uid_num);
+ if (val == 0U) {
+ *nv_ctr = 0U;
+ } else {
+ *nv_ctr = (32U - __builtin_clz(val));
+ }
+
+ INFO("NV Counter value for UID %d is %d\n", uid_num, *nv_ctr);
+ return 0;
+
+}
+
+int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr)
+{
+ const char *oid;
+ uint32_t uid_num, sfp_val;
+
+ assert(cookie != NULL);
+
+ /* Counter values upto 32 are supported */
+ if (nv_ctr > 32U) {
+ return 1;
+ }
+
+ oid = (const char *)cookie;
+ if (strcmp(oid, TRUSTED_FW_NVCOUNTER_OID) == 0) {
+ uid_num = 3U;
+ } else if (strcmp(oid, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) {
+ uid_num = 4U;
+ } else {
+ return 1;
+ }
+ sfp_val = (1U << (nv_ctr - 1));
+
+ if (sfp_write_oem_uid(uid_num, sfp_val) == 1) {
+ /* Enable POVDD on board */
+ if (board_enable_povdd()) {
+ sfp_program_fuses();
+ }
+
+ /* Disable POVDD on board */
+ board_disable_povdd();
+ } else {
+ ERROR("Invalid OEM UID sent.\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
+{
+ return get_mbedtls_heap_helper(heap_addr, heap_size);
+}
diff --git a/plat/nxp/common/warm_reset/plat_warm_reset.c b/plat/nxp/common/warm_reset/plat_warm_reset.c
new file mode 100644
index 0000000..966a73c
--- /dev/null
+++ b/plat/nxp/common/warm_reset/plat_warm_reset.c
@@ -0,0 +1,121 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <errno.h>
+
+#include <common/debug.h>
+#include <ddr.h>
+#ifndef NXP_COINED_BB
+#include <flash_info.h>
+#include <fspi.h>
+#include <fspi_api.h>
+#endif
+#include <lib/mmio.h>
+#include <lib/psci/psci.h>
+#ifdef NXP_COINED_BB
+#include <snvs.h>
+#endif
+
+#include <plat_nv_storage.h>
+#include "plat_warm_rst.h"
+#include "platform_def.h"
+
+#if defined(IMAGE_BL2)
+
+uint32_t is_warm_boot(void)
+{
+ uint32_t ret = mmio_read_32(NXP_RESET_ADDR + RST_RSTRQSR1_OFFSET)
+ & ~(RSTRQSR1_SWRR);
+
+ const nv_app_data_t *nv_app_data = get_nv_data();
+
+ if (ret == 0U) {
+ INFO("Not a SW(Warm) triggered reset.\n");
+ return 0U;
+ }
+
+ ret = (nv_app_data->warm_rst_flag == WARM_BOOT_SUCCESS) ? 1 : 0;
+
+ if (ret != 0U) {
+ INFO("Warm Reset was triggered..\n");
+ } else {
+ INFO("Warm Reset was not triggered..\n");
+ }
+
+ return ret;
+}
+
+#endif
+
+#if defined(IMAGE_BL31)
+int prep_n_execute_warm_reset(void)
+{
+#ifdef NXP_COINED_BB
+#if !TRUSTED_BOARD_BOOT
+ snvs_disable_zeroize_lp_gpr();
+#endif
+#else
+ int ret;
+ uint8_t warm_reset = WARM_BOOT_SUCCESS;
+
+ ret = fspi_init(NXP_FLEXSPI_ADDR, NXP_FLEXSPI_FLASH_ADDR);
+
+ if (ret != 0) {
+ ERROR("Failed to initialized driver flexspi-nor.\n");
+ ERROR("exiting warm-reset request.\n");
+ return PSCI_E_INTERN_FAIL;
+ }
+
+ /* Sector starting from NV_STORAGE_BASE_ADDR is already
+ * erased for writing.
+ */
+
+#if (ERLY_WRM_RST_FLG_FLSH_UPDT)
+ ret = xspi_write((uint32_t)NV_STORAGE_BASE_ADDR,
+ &warm_reset,
+ sizeof(warm_reset));
+#else
+ /* Preparation for writing the Warm reset flag. */
+ ret = xspi_wren((uint32_t)NV_STORAGE_BASE_ADDR);
+
+ /* IP Control Register0 - SF Address to be read */
+ fspi_out32((NXP_FLEXSPI_ADDR + FSPI_IPCR0),
+ (uint32_t) NV_STORAGE_BASE_ADDR);
+
+ while ((fspi_in32(NXP_FLEXSPI_ADDR + FSPI_INTR) &
+ FSPI_INTR_IPTXWE_MASK) == 0) {
+ ;
+ }
+ /* Write TX FIFO Data Register */
+ fspi_out32(NXP_FLEXSPI_ADDR + FSPI_TFDR, (uint32_t) warm_reset);
+
+ fspi_out32(NXP_FLEXSPI_ADDR + FSPI_INTR, FSPI_INTR_IPTXWE);
+
+ /* IP Control Register1 - SEQID_WRITE operation, Size = 1 Byte */
+ fspi_out32(NXP_FLEXSPI_ADDR + FSPI_IPCR1,
+ (uint32_t)(FSPI_WRITE_SEQ_ID << FSPI_IPCR1_ISEQID_SHIFT) |
+ (uint16_t) sizeof(warm_reset));
+
+ /* Trigger XSPI-IP-Write cmd only if:
+ * - Putting DDR in-self refresh mode is successfully.
+ * to complete the writing of the warm-reset flag
+ * to flash.
+ *
+ * This code is as part of assembly.
+ */
+#endif
+#endif
+ INFO("Doing DDR Self refresh.\n");
+ _soc_sys_warm_reset();
+
+ /* Expected behaviour is to do the power cycle */
+ while (1 != 0)
+ ;
+
+ return -1;
+}
+#endif
diff --git a/plat/nxp/common/warm_reset/plat_warm_rst.h b/plat/nxp/common/warm_reset/plat_warm_rst.h
new file mode 100644
index 0000000..e0c39c5
--- /dev/null
+++ b/plat/nxp/common/warm_reset/plat_warm_rst.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PLAT_WARM_RST_H
+#define PLAT_WARM_RST_H
+
+#ifndef NXP_COINED_BB
+#define ERLY_WRM_RST_FLG_FLSH_UPDT 0
+#endif
+
+#ifndef __ASSEMBLER__
+
+#if defined(IMAGE_BL2)
+uint32_t is_warm_boot(void);
+#endif
+
+#if defined(IMAGE_BL31)
+int prep_n_execute_warm_reset(void);
+int _soc_sys_warm_reset(void);
+#endif
+
+#endif /* __ASSEMBLER__ */
+
+#endif /* PLAT_WARM_RST_H */
diff --git a/plat/nxp/common/warm_reset/warm_reset.mk b/plat/nxp/common/warm_reset/warm_reset.mk
new file mode 100644
index 0000000..236004f
--- /dev/null
+++ b/plat/nxp/common/warm_reset/warm_reset.mk
@@ -0,0 +1,20 @@
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-----------------------------------------------------------------------------
+ifeq (${WARM_RST_ADDED},)
+
+WARM_RST_ADDED := 1
+NXP_NV_SW_MAINT_LAST_EXEC_DATA := yes
+
+$(eval $(call add_define,NXP_WARM_BOOT))
+
+
+WARM_RST_INCLUDES += -I${PLAT_COMMON_PATH}/warm_reset
+WARM_RST_BL31_SOURCES += ${PLAT_SOC_PATH}/$(ARCH)/${SOC}_warm_rst.S
+
+WARM_RST_BL_COMM_SOURCES += ${PLAT_COMMON_PATH}/warm_reset/plat_warm_reset.c
+
+endif
diff --git a/plat/nxp/soc-lx2160a/aarch64/lx2160a.S b/plat/nxp/soc-lx2160a/aarch64/lx2160a.S
new file mode 100644
index 0000000..4679fc2
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/aarch64/lx2160a.S
@@ -0,0 +1,1824 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+.section .text, "ax"
+
+#include <asm_macros.S>
+
+#include <lib/psci/psci.h>
+#include <nxp_timer.h>
+#include <plat_gic.h>
+#include <pmu.h>
+
+#include <bl31_data.h>
+#include <plat_psci.h>
+#include <platform_def.h>
+
+.global soc_init_start
+.global soc_init_percpu
+.global soc_init_finish
+.global _set_platform_security
+.global _soc_set_start_addr
+
+.global _soc_core_release
+.global _soc_ck_disabled
+.global _soc_core_restart
+.global _soc_core_prep_off
+.global _soc_core_entr_off
+.global _soc_core_exit_off
+.global _soc_sys_reset
+.global _soc_sys_off
+.global _soc_core_prep_stdby
+.global _soc_core_entr_stdby
+.global _soc_core_exit_stdby
+.global _soc_core_prep_pwrdn
+.global _soc_core_entr_pwrdn
+.global _soc_core_exit_pwrdn
+.global _soc_clstr_prep_stdby
+.global _soc_clstr_exit_stdby
+.global _soc_clstr_prep_pwrdn
+.global _soc_clstr_exit_pwrdn
+.global _soc_sys_prep_stdby
+.global _soc_sys_exit_stdby
+.global _soc_sys_prep_pwrdn
+.global _soc_sys_pwrdn_wfi
+.global _soc_sys_exit_pwrdn
+
+.equ TZPC_BASE, 0x02200000
+.equ TZPCDECPROT_0_SET_BASE, 0x02200804
+.equ TZPCDECPROT_1_SET_BASE, 0x02200810
+.equ TZPCDECPROT_2_SET_BASE, 0x0220081C
+
+#define CLUSTER_3_CORES_MASK 0xC0
+#define CLUSTER_3_IN_RESET 1
+#define CLUSTER_3_NORMAL 0
+
+/* cluster 3 handling no longer based on frequency, but rather on RCW[850],
+ * which is bit 18 of RCWSR27
+ */
+#define CLUSTER_3_RCW_BIT 0x40000
+
+/* retry count for clock-stop acks */
+.equ CLOCK_RETRY_CNT, 800
+
+/* disable prefetching in the A72 core */
+#define CPUACTLR_DIS_LS_HW_PRE 0x100000000000000
+#define CPUACTLR_DIS_L2_TLB_PRE 0x200000
+
+/* Function starts the initialization tasks of the soc,
+ * using secondary cores if they are available
+ *
+ * Called from C, saving the non-volatile regs
+ * save these as pairs of registers to maintain the
+ * required 16-byte alignment on the stack
+ *
+ * in:
+ * out:
+ * uses x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11
+ */
+func soc_init_start
+ stp x4, x5, [sp, #-16]!
+ stp x6, x7, [sp, #-16]!
+ stp x8, x9, [sp, #-16]!
+ stp x10, x11, [sp, #-16]!
+ stp x12, x13, [sp, #-16]!
+ stp x18, x30, [sp, #-16]!
+
+ /* make sure the personality has been
+ * established by releasing cores that
+ * are marked "to-be-disabled" from reset
+ */
+ bl release_disabled /* 0-9 */
+
+ /* init the task flags */
+ bl _init_task_flags /* 0-1 */
+
+ /* set SCRATCHRW7 to 0x0 */
+ ldr x0, =DCFG_SCRATCHRW7_OFFSET
+ mov x1, xzr
+ bl _write_reg_dcfg
+
+1:
+ /* restore the aarch32/64 non-volatile registers */
+ ldp x18, x30, [sp], #16
+ ldp x12, x13, [sp], #16
+ ldp x10, x11, [sp], #16
+ ldp x8, x9, [sp], #16
+ ldp x6, x7, [sp], #16
+ ldp x4, x5, [sp], #16
+ ret
+endfunc soc_init_start
+
+
+/* Function performs any soc-specific initialization that is needed on
+ * a per-core basis.
+ * in: none
+ * out: none
+ * uses x0, x1, x2, x3
+ */
+func soc_init_percpu
+ stp x4, x30, [sp, #-16]!
+
+ bl plat_my_core_mask
+ mov x2, x0 /* x2 = core mask */
+
+ /* Check if this core is marked for prefetch disable
+ */
+ mov x0, #PREFETCH_DIS_OFFSET
+ bl _get_global_data /* 0-1 */
+ tst x0, x2
+ b.eq 1f
+ bl _disable_ldstr_pfetch_A72 /* 0 */
+1:
+ mov x0, #NXP_PMU_ADDR
+ bl enable_timer_base_to_cluster
+ ldp x4, x30, [sp], #16
+ ret
+endfunc soc_init_percpu
+
+
+/* Function completes the initialization tasks of the soc
+ * in:
+ * out:
+ * uses x0, x1, x2, x3, x4
+ */
+func soc_init_finish
+ stp x4, x30, [sp, #-16]!
+
+ ldp x4, x30, [sp], #16
+ ret
+endfunc soc_init_finish
+
+
+/* Function sets the security mechanisms in the SoC to implement the
+ * Platform Security Policy
+ */
+func _set_platform_security
+ mov x8, x30
+
+#if (!SUPPRESS_TZC)
+ /* initialize the tzpc */
+ bl init_tzpc
+#endif
+
+#if (!SUPPRESS_SEC)
+ /* initialize secmon */
+#ifdef NXP_SNVS_ENABLED
+ mov x0, #NXP_SNVS_ADDR
+ bl init_sec_mon
+#endif
+#endif
+
+ mov x30, x8
+ ret
+endfunc _set_platform_security
+
+
+/* Function writes a 64-bit address to bootlocptrh/l
+ * in: x0, 64-bit address to write to BOOTLOCPTRL/H
+ * uses x0, x1, x2
+ */
+func _soc_set_start_addr
+ /* Get the 64-bit base address of the dcfg block */
+ ldr x2, =NXP_DCFG_ADDR
+
+ /* write the 32-bit BOOTLOCPTRL register */
+ mov x1, x0
+ str w1, [x2, #DCFG_BOOTLOCPTRL_OFFSET]
+
+ /* write the 32-bit BOOTLOCPTRH register */
+ lsr x1, x0, #32
+ str w1, [x2, #DCFG_BOOTLOCPTRH_OFFSET]
+ ret
+endfunc _soc_set_start_addr
+
+/* Function releases a secondary core from reset
+ * in: x0 = core_mask_lsb
+ * out: none
+ * uses: x0, x1, x2, x3
+ */
+func _soc_core_release
+ mov x3, x30
+
+ ldr x1, =NXP_SEC_REGFILE_ADDR
+ /* write to CORE_HOLD to tell
+ * the bootrom that this core is
+ * expected to run.
+ */
+ str w0, [x1, #CORE_HOLD_OFFSET]
+
+ /* read-modify-write BRRL to release core */
+ mov x1, #NXP_RESET_ADDR
+ ldr w2, [x1, #BRR_OFFSET]
+
+ /* x0 = core mask */
+ orr w2, w2, w0
+ str w2, [x1, #BRR_OFFSET]
+ dsb sy
+ isb
+
+ /* send event */
+ sev
+ isb
+
+ mov x30, x3
+ ret
+endfunc _soc_core_release
+
+
+/* Function determines if a core is disabled via COREDISABLEDSR
+ * in: w0 = core_mask_lsb
+ * out: w0 = 0, core not disabled
+ * w0 != 0, core disabled
+ * uses x0, x1
+ */
+func _soc_ck_disabled
+
+ /* get base addr of dcfg block */
+ ldr x1, =NXP_DCFG_ADDR
+
+ /* read COREDISABLEDSR */
+ ldr w1, [x1, #DCFG_COREDISABLEDSR_OFFSET]
+
+ /* test core bit */
+ and w0, w1, w0
+
+ ret
+endfunc _soc_ck_disabled
+
+
+/* Part of CPU_ON
+ * Function restarts a core shutdown via _soc_core_entr_off
+ * in: x0 = core mask lsb (of the target cpu)
+ * out: x0 == 0, on success
+ * x0 != 0, on failure
+ * uses x0, x1, x2, x3, x4, x5, x6
+ */
+func _soc_core_restart
+ mov x6, x30
+ mov x4, x0
+
+ /* pgm GICD_CTLR - enable secure grp0 */
+ mov x5, #NXP_GICD_ADDR
+ ldr w2, [x5, #GICD_CTLR_OFFSET]
+ orr w2, w2, #GICD_CTLR_EN_GRP_0
+ str w2, [x5, #GICD_CTLR_OFFSET]
+ dsb sy
+ isb
+
+ /* poll on RWP til write completes */
+4:
+ ldr w2, [x5, #GICD_CTLR_OFFSET]
+ tst w2, #GICD_CTLR_RWP
+ b.ne 4b
+
+ /* x4 = core mask lsb
+ * x5 = gicd base addr
+ */
+ mov x0, x4
+ bl get_mpidr_value
+
+ /* x0 = mpidr of target core
+ * x4 = core mask lsb of target core
+ * x5 = gicd base addr
+ */
+
+ /* generate target list bit */
+ and x1, x0, #MPIDR_AFFINITY0_MASK
+ mov x2, #1
+ lsl x2, x2, x1
+
+ /* get the affinity1 field */
+ and x1, x0, #MPIDR_AFFINITY1_MASK
+ lsl x1, x1, #8
+ orr x2, x2, x1
+
+ /* insert the INTID for SGI15 */
+ orr x2, x2, #ICC_SGI0R_EL1_INTID
+
+ /* fire the SGI */
+ msr ICC_SGI0R_EL1, x2
+ dsb sy
+ isb
+
+ /* load '0' on success */
+ mov x0, xzr
+
+ mov x30, x6
+ ret
+endfunc _soc_core_restart
+
+
+/* Part of CPU_OFF
+ * Function programs SoC & GIC registers in preparation for shutting down
+ * the core
+ * in: x0 = core mask lsb
+ * out: none
+ * uses x0, x1, x2, x3, x4, x5, x6, x7
+ */
+func _soc_core_prep_off
+ mov x8, x30
+ mov x7, x0 /* x7 = core mask lsb */
+
+ mrs x1, CORTEX_A72_ECTLR_EL1
+
+ /* set smp and disable L2 snoops in cpuectlr */
+ orr x1, x1, #CPUECTLR_SMPEN_EN
+ orr x1, x1, #CPUECTLR_DISABLE_TWALK_PREFETCH
+ bic x1, x1, #CPUECTLR_INS_PREFETCH_MASK
+ bic x1, x1, #CPUECTLR_DAT_PREFETCH_MASK
+
+ /* set retention control in cpuectlr */
+ bic x1, x1, #CPUECTLR_TIMER_MASK
+ orr x1, x1, #CPUECTLR_TIMER_8TICKS
+ msr CORTEX_A72_ECTLR_EL1, x1
+
+ /* get redistributor rd base addr for this core */
+ mov x0, x7
+ bl get_gic_rd_base
+ mov x6, x0
+
+ /* get redistributor sgi base addr for this core */
+ mov x0, x7
+ bl get_gic_sgi_base
+ mov x5, x0
+
+ /* x5 = gicr sgi base addr
+ * x6 = gicr rd base addr
+ * x7 = core mask lsb
+ */
+
+ /* disable SGI 15 at redistributor - GICR_ICENABLER0 */
+ mov w3, #GICR_ICENABLER0_SGI15
+ str w3, [x5, #GICR_ICENABLER0_OFFSET]
+2:
+ /* poll on rwp bit in GICR_CTLR */
+ ldr w4, [x6, #GICR_CTLR_OFFSET]
+ tst w4, #GICR_CTLR_RWP
+ b.ne 2b
+
+ /* disable GRP1 interrupts at cpu interface */
+ msr ICC_IGRPEN1_EL3, xzr
+
+ /* disable GRP0 ints at cpu interface */
+ msr ICC_IGRPEN0_EL1, xzr
+
+ /* program the redistributor - poll on GICR_CTLR.RWP as needed */
+
+ /* define SGI 15 as Grp0 - GICR_IGROUPR0 */
+ ldr w4, [x5, #GICR_IGROUPR0_OFFSET]
+ bic w4, w4, #GICR_IGROUPR0_SGI15
+ str w4, [x5, #GICR_IGROUPR0_OFFSET]
+
+ /* define SGI 15 as Grp0 - GICR_IGRPMODR0 */
+ ldr w3, [x5, #GICR_IGRPMODR0_OFFSET]
+ bic w3, w3, #GICR_IGRPMODR0_SGI15
+ str w3, [x5, #GICR_IGRPMODR0_OFFSET]
+
+ /* set priority of SGI 15 to highest (0x0) - GICR_IPRIORITYR3 */
+ ldr w4, [x5, #GICR_IPRIORITYR3_OFFSET]
+ bic w4, w4, #GICR_IPRIORITYR3_SGI15_MASK
+ str w4, [x5, #GICR_IPRIORITYR3_OFFSET]
+
+ /* enable SGI 15 at redistributor - GICR_ISENABLER0 */
+ mov w3, #GICR_ISENABLER0_SGI15
+ str w3, [x5, #GICR_ISENABLER0_OFFSET]
+ dsb sy
+ isb
+3:
+ /* poll on rwp bit in GICR_CTLR */
+ ldr w4, [x6, #GICR_CTLR_OFFSET]
+ tst w4, #GICR_CTLR_RWP
+ b.ne 3b
+
+ /* quiesce the debug interfaces */
+ mrs x3, osdlr_el1
+ orr x3, x3, #OSDLR_EL1_DLK_LOCK
+ msr osdlr_el1, x3
+ isb
+
+ /* enable grp0 ints */
+ mov x3, #ICC_IGRPEN0_EL1_EN
+ msr ICC_IGRPEN0_EL1, x3
+
+ /* x5 = gicr sgi base addr
+ * x6 = gicr rd base addr
+ * x7 = core mask lsb
+ */
+
+ /* clear any pending interrupts */
+ mvn w1, wzr
+ str w1, [x5, #GICR_ICPENDR0_OFFSET]
+
+ /* make sure system counter is enabled */
+ ldr x3, =NXP_TIMER_ADDR
+ ldr w0, [x3, #SYS_COUNTER_CNTCR_OFFSET]
+ tst w0, #SYS_COUNTER_CNTCR_EN
+ b.ne 4f
+ orr w0, w0, #SYS_COUNTER_CNTCR_EN
+ str w0, [x3, #SYS_COUNTER_CNTCR_OFFSET]
+4:
+ /* enable the core timer and mask timer interrupt */
+ mov x1, #CNTP_CTL_EL0_EN
+ orr x1, x1, #CNTP_CTL_EL0_IMASK
+ msr cntp_ctl_el0, x1
+
+ isb
+ mov x30, x8
+ ret
+endfunc _soc_core_prep_off
+
+
+/* Part of CPU_OFF:
+ * Function performs the final steps to shutdown the core
+ * in: x0 = core mask lsb
+ * out: none
+ * uses x0, x1, x2, x3, x4, x5
+ */
+func _soc_core_entr_off
+ mov x5, x30
+ mov x4, x0
+
+1:
+ /* enter low-power state by executing wfi */
+ wfi
+
+ /* see if SGI15 woke us up */
+ mrs x2, ICC_IAR0_EL1
+ mov x3, #ICC_IAR0_EL1_SGI15
+ cmp x2, x3
+ b.ne 2f
+
+ /* deactivate the intrrupts. */
+ msr ICC_EOIR0_EL1, x2
+
+2:
+ /* check if core is turned ON */
+ mov x0, x4
+ /* Fetched the core state in x0 */
+ bl _getCoreState
+
+ cmp x0, #CORE_WAKEUP
+ b.ne 1b
+
+ /* Reached here, exited the wfi */
+
+ mov x30, x5
+ ret
+endfunc _soc_core_entr_off
+
+
+/* Part of CPU_OFF:
+ * Function starts the process of starting a core back up
+ * in: x0 = core mask lsb
+ * out: none
+ * uses x0, x1, x2, x3, x4, x5, x6
+ */
+func _soc_core_exit_off
+ mov x6, x30
+ mov x5, x0
+
+ /* disable forwarding of GRP0 ints at cpu interface */
+ msr ICC_IGRPEN0_EL1, xzr
+
+ /* get redistributor sgi base addr for this core */
+ mov x0, x5
+ bl get_gic_sgi_base
+ mov x4, x0
+
+ /* x4 = gicr sgi base addr
+ * x5 = core mask
+ */
+
+ /* disable SGI 15 at redistributor - GICR_ICENABLER0 */
+ mov w1, #GICR_ICENABLER0_SGI15
+ str w1, [x4, #GICR_ICENABLER0_OFFSET]
+
+ /* get redistributor rd base addr for this core */
+ mov x0, x5
+ bl get_gic_rd_base
+ mov x4, x0
+
+2:
+ /* poll on rwp bit in GICR_CTLR */
+ ldr w2, [x4, #GICR_CTLR_OFFSET]
+ tst w2, #GICR_CTLR_RWP
+ b.ne 2b
+
+ /* unlock the debug interfaces */
+ mrs x3, osdlr_el1
+ bic x3, x3, #OSDLR_EL1_DLK_LOCK
+ msr osdlr_el1, x3
+ isb
+
+ dsb sy
+ isb
+ mov x30, x6
+ ret
+endfunc _soc_core_exit_off
+
+
+/* Function requests a reset of the entire SOC
+ * in: none
+ * out: none
+ * uses: x0, x1, x2, x3, x4, x5, x6
+ */
+func _soc_sys_reset
+ mov x6, x30
+
+ ldr x2, =NXP_RST_ADDR
+ /* clear the RST_REQ_MSK and SW_RST_REQ */
+
+ mov w0, #0x00000000
+ str w0, [x2, #RSTCNTL_OFFSET]
+
+ /* initiate the sw reset request */
+ mov w0, #SW_RST_REQ_INIT
+ str w0, [x2, #RSTCNTL_OFFSET]
+
+ /* In case this address range is mapped as cacheable,
+ * flush the write out of the dcaches.
+ */
+ add x2, x2, #RSTCNTL_OFFSET
+ dc cvac, x2
+ dsb st
+ isb
+
+ /* Function does not return */
+ b .
+endfunc _soc_sys_reset
+
+
+/* Part of SYSTEM_OFF:
+ * Function turns off the SoC clocks
+ * Note: Function is not intended to return, and the only allowable
+ * recovery is POR
+ * in: none
+ * out: none
+ * uses x0, x1, x2, x3
+ */
+func _soc_sys_off
+
+ /* A-009810: LPM20 entry sequence might cause
+ * spurious timeout reset request
+ * workaround: MASK RESET REQ RPTOE
+ */
+ ldr x0, =NXP_RESET_ADDR
+ ldr w1, =RSTRQMR_RPTOE_MASK
+ str w1, [x0, #RST_RSTRQMR1_OFFSET]
+
+ /* disable sec, QBman, spi and qspi */
+ ldr x2, =NXP_DCFG_ADDR
+ ldr x0, =DCFG_DEVDISR1_OFFSET
+ ldr w1, =DCFG_DEVDISR1_SEC
+ str w1, [x2, x0]
+ ldr x0, =DCFG_DEVDISR3_OFFSET
+ ldr w1, =DCFG_DEVDISR3_QBMAIN
+ str w1, [x2, x0]
+ ldr x0, =DCFG_DEVDISR4_OFFSET
+ ldr w1, =DCFG_DEVDISR4_SPI_QSPI
+ str w1, [x2, x0]
+
+ /* set TPMWAKEMR0 */
+ ldr x0, =TPMWAKEMR0_ADDR
+ mov w1, #0x1
+ str w1, [x0]
+
+ /* disable icache, dcache, mmu @ EL1 */
+ mov x1, #SCTLR_I_C_M_MASK
+ mrs x0, sctlr_el1
+ bic x0, x0, x1
+ msr sctlr_el1, x0
+
+ /* disable L2 prefetches */
+ mrs x0, CORTEX_A72_ECTLR_EL1
+ bic x1, x1, #CPUECTLR_TIMER_MASK
+ orr x0, x0, #CPUECTLR_SMPEN_EN
+ orr x0, x0, #CPUECTLR_TIMER_8TICKS
+ msr CORTEX_A72_ECTLR_EL1, x0
+ isb
+
+ /* disable CCN snoop domain */
+ mov x1, #NXP_CCN_HN_F_0_ADDR
+ ldr x0, =CCN_HN_F_SNP_DMN_CTL_MASK
+ str x0, [x1, #CCN_HN_F_SNP_DMN_CTL_CLR_OFFSET]
+3:
+ ldr w2, [x1, #CCN_HN_F_SNP_DMN_CTL_OFFSET]
+ cmp w2, #0x2
+ b.ne 3b
+
+ mov x3, #NXP_PMU_ADDR
+
+4:
+ ldr w1, [x3, #PMU_PCPW20SR_OFFSET]
+ cmp w1, #PMU_IDLE_CORE_MASK
+ b.ne 4b
+
+ mov w1, #PMU_IDLE_CLUSTER_MASK
+ str w1, [x3, #PMU_CLAINACTSETR_OFFSET]
+
+1:
+ ldr w1, [x3, #PMU_PCPW20SR_OFFSET]
+ cmp w1, #PMU_IDLE_CORE_MASK
+ b.ne 1b
+
+ mov w1, #PMU_FLUSH_CLUSTER_MASK
+ str w1, [x3, #PMU_CLL2FLUSHSETR_OFFSET]
+
+2:
+ ldr w1, [x3, #PMU_CLL2FLUSHSR_OFFSET]
+ cmp w1, #PMU_FLUSH_CLUSTER_MASK
+ b.ne 2b
+
+ mov w1, #PMU_FLUSH_CLUSTER_MASK
+ str w1, [x3, #PMU_CLSL2FLUSHCLRR_OFFSET]
+
+ mov w1, #PMU_FLUSH_CLUSTER_MASK
+ str w1, [x3, #PMU_CLSINACTSETR_OFFSET]
+
+ mov x2, #DAIF_SET_MASK
+ mrs x1, spsr_el1
+ orr x1, x1, x2
+ msr spsr_el1, x1
+
+ mrs x1, spsr_el2
+ orr x1, x1, x2
+ msr spsr_el2, x1
+
+ /* force the debug interface to be quiescent */
+ mrs x0, osdlr_el1
+ orr x0, x0, #0x1
+ msr osdlr_el1, x0
+
+ /* invalidate all TLB entries at all 3 exception levels */
+ tlbi alle1
+ tlbi alle2
+ tlbi alle3
+
+ /* x3 = pmu base addr */
+
+ /* request lpm20 */
+ ldr x0, =PMU_POWMGTCSR_OFFSET
+ ldr w1, =PMU_POWMGTCSR_VAL
+ str w1, [x3, x0]
+
+5:
+ wfe
+ b.eq 5b
+endfunc _soc_sys_off
+
+
+/* Part of CPU_SUSPEND
+ * Function puts the calling core into standby state
+ * in: x0 = core mask lsb
+ * out: none
+ * uses x0
+ */
+func _soc_core_entr_stdby
+
+ dsb sy
+ isb
+ wfi
+
+ ret
+endfunc _soc_core_entr_stdby
+
+
+/* Part of CPU_SUSPEND
+ * Function performs SoC-specific programming prior to standby
+ * in: x0 = core mask lsb
+ * out: none
+ * uses x0, x1
+ */
+func _soc_core_prep_stdby
+
+ /* clear CORTEX_A72_ECTLR_EL1[2:0] */
+ mrs x1, CORTEX_A72_ECTLR_EL1
+ bic x1, x1, #CPUECTLR_TIMER_MASK
+ msr CORTEX_A72_ECTLR_EL1, x1
+
+ ret
+endfunc _soc_core_prep_stdby
+
+
+/* Part of CPU_SUSPEND
+ * Function performs any SoC-specific cleanup after standby state
+ * in: x0 = core mask lsb
+ * out: none
+ * uses none
+ */
+func _soc_core_exit_stdby
+
+ ret
+endfunc _soc_core_exit_stdby
+
+
+/* Part of CPU_SUSPEND
+ * Function performs SoC-specific programming prior to power-down
+ * in: x0 = core mask lsb
+ * out: none
+ * uses none
+ */
+func _soc_core_prep_pwrdn
+
+ /* make sure system counter is enabled */
+ ldr x2, =NXP_TIMER_ADDR
+ ldr w0, [x2, #SYS_COUNTER_CNTCR_OFFSET]
+ tst w0, #SYS_COUNTER_CNTCR_EN
+ b.ne 1f
+ orr w0, w0, #SYS_COUNTER_CNTCR_EN
+ str w0, [x2, #SYS_COUNTER_CNTCR_OFFSET]
+1:
+
+ /* enable dynamic retention control (CPUECTLR[2:0])
+ * set the SMPEN bit (CPUECTLR[6])
+ */
+ mrs x1, CORTEX_A72_ECTLR_EL1
+ bic x1, x1, #CPUECTLR_RET_MASK
+ orr x1, x1, #CPUECTLR_TIMER_8TICKS
+ orr x1, x1, #CPUECTLR_SMPEN_EN
+ msr CORTEX_A72_ECTLR_EL1, x1
+
+ isb
+ ret
+endfunc _soc_core_prep_pwrdn
+
+
+/* Part of CPU_SUSPEND
+ * Function puts the calling core into a power-down state
+ * in: x0 = core mask lsb
+ * out: none
+ * uses x0
+ */
+func _soc_core_entr_pwrdn
+
+ /* X0 = core mask lsb */
+
+ dsb sy
+ isb
+ wfi
+
+ ret
+endfunc _soc_core_entr_pwrdn
+
+
+/* Part of CPU_SUSPEND
+ * Function performs any SoC-specific cleanup after power-down state
+ * in: x0 = core mask lsb
+ * out: none
+ * uses none
+ */
+func _soc_core_exit_pwrdn
+
+ ret
+endfunc _soc_core_exit_pwrdn
+
+
+/* Part of CPU_SUSPEND
+ * Function performs SoC-specific programming prior to standby
+ * in: x0 = core mask lsb
+ * out: none
+ * uses x0, x1
+ */
+func _soc_clstr_prep_stdby
+
+ /* clear CORTEX_A72_ECTLR_EL1[2:0] */
+ mrs x1, CORTEX_A72_ECTLR_EL1
+ bic x1, x1, #CPUECTLR_TIMER_MASK
+ msr CORTEX_A72_ECTLR_EL1, x1
+
+ ret
+endfunc _soc_clstr_prep_stdby
+
+
+/* Part of CPU_SUSPEND
+ * Function performs any SoC-specific cleanup after standby state
+ * in: x0 = core mask lsb
+ * out: none
+ * uses none
+ */
+func _soc_clstr_exit_stdby
+
+ ret
+endfunc _soc_clstr_exit_stdby
+
+
+/* Part of CPU_SUSPEND
+ * Function performs SoC-specific programming prior to power-down
+ * in: x0 = core mask lsb
+ * out: none
+ * uses none
+ */
+func _soc_clstr_prep_pwrdn
+
+ /* make sure system counter is enabled */
+ ldr x2, =NXP_TIMER_ADDR
+ ldr w0, [x2, #SYS_COUNTER_CNTCR_OFFSET]
+ tst w0, #SYS_COUNTER_CNTCR_EN
+ b.ne 1f
+ orr w0, w0, #SYS_COUNTER_CNTCR_EN
+ str w0, [x2, #SYS_COUNTER_CNTCR_OFFSET]
+1:
+
+ /* enable dynamic retention control (CPUECTLR[2:0])
+ * set the SMPEN bit (CPUECTLR[6])
+ */
+ mrs x1, CORTEX_A72_ECTLR_EL1
+ bic x1, x1, #CPUECTLR_RET_MASK
+ orr x1, x1, #CPUECTLR_TIMER_8TICKS
+ orr x1, x1, #CPUECTLR_SMPEN_EN
+ msr CORTEX_A72_ECTLR_EL1, x1
+
+ isb
+ ret
+endfunc _soc_clstr_prep_pwrdn
+
+
+/* Part of CPU_SUSPEND
+ * Function performs any SoC-specific cleanup after power-down state
+ * in: x0 = core mask lsb
+ * out: none
+ * uses none
+ */
+func _soc_clstr_exit_pwrdn
+
+ ret
+endfunc _soc_clstr_exit_pwrdn
+
+
+/* Part of CPU_SUSPEND
+ * Function performs SoC-specific programming prior to standby
+ * in: x0 = core mask lsb
+ * out: none
+ * uses x0, x1
+ */
+func _soc_sys_prep_stdby
+
+ /* clear CORTEX_A72_ECTLR_EL1[2:0] */
+ mrs x1, CORTEX_A72_ECTLR_EL1
+ bic x1, x1, #CPUECTLR_TIMER_MASK
+ msr CORTEX_A72_ECTLR_EL1, x1
+ ret
+endfunc _soc_sys_prep_stdby
+
+
+/* Part of CPU_SUSPEND
+ * Function performs any SoC-specific cleanup after standby state
+ * in: x0 = core mask lsb
+ * out: none
+ * uses none
+ */
+func _soc_sys_exit_stdby
+
+ ret
+endfunc _soc_sys_exit_stdby
+
+
+/* Part of CPU_SUSPEND
+ * Function performs SoC-specific programming prior to
+ * suspend-to-power-down
+ * in: x0 = core mask lsb
+ * out: none
+ * uses x0, x1
+ */
+func _soc_sys_prep_pwrdn
+
+ mrs x1, CORTEX_A72_ECTLR_EL1
+ /* make sure the smp bit is set */
+ orr x1, x1, #CPUECTLR_SMPEN_MASK
+ /* set the retention control */
+ orr x1, x1, #CPUECTLR_RET_8CLK
+ /* disable tablewalk prefetch */
+ orr x1, x1, #CPUECTLR_DISABLE_TWALK_PREFETCH
+ msr CORTEX_A72_ECTLR_EL1, x1
+ isb
+
+ ret
+endfunc _soc_sys_prep_pwrdn
+
+
+/* Part of CPU_SUSPEND
+ * Function puts the calling core, and potentially the soc, into a
+ * low-power state
+ * in: x0 = core mask lsb
+ * out: x0 = 0, success
+ * x0 < 0, failure
+ * uses x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14,
+ * x15, x16, x17, x18, x19, x20, x21, x28
+ */
+func _soc_sys_pwrdn_wfi
+ mov x28, x30
+
+ /* disable cluster snooping in the CCN-508 */
+ ldr x1, =NXP_CCN_HN_F_0_ADDR
+ ldr x7, [x1, #CCN_HN_F_SNP_DMN_CTL_OFFSET]
+ mov x6, #CCN_HNF_NODE_COUNT
+1:
+ str x7, [x1, #CCN_HN_F_SNP_DMN_CTL_CLR_OFFSET]
+ sub x6, x6, #1
+ add x1, x1, #CCN_HNF_OFFSET
+ cbnz x6, 1b
+
+ /* x0 = core mask
+ * x7 = hnf sdcr
+ */
+
+ ldr x1, =NXP_PMU_CCSR_ADDR
+ ldr x2, =NXP_PMU_DCSR_ADDR
+
+ /* enable the stop-request-override */
+ mov x3, #PMU_POWMGTDCR0_OFFSET
+ mov x4, #POWMGTDCR_STP_OV_EN
+ str w4, [x2, x3]
+
+ /* x0 = core mask
+ * x1 = NXP_PMU_CCSR_ADDR
+ * x2 = NXP_PMU_DCSR_ADDR
+ * x7 = hnf sdcr
+ */
+
+ /* disable prefetching in the A72 core */
+ mrs x8, CORTEX_A72_CPUACTLR_EL1
+ tst x8, #CPUACTLR_DIS_LS_HW_PRE
+ b.ne 2f
+ dsb sy
+ isb
+ /* disable data prefetch */
+ orr x16, x8, #CPUACTLR_DIS_LS_HW_PRE
+ /* disable tlb prefetch */
+ orr x16, x16, #CPUACTLR_DIS_L2_TLB_PRE
+ msr CORTEX_A72_CPUACTLR_EL1, x16
+ isb
+
+ /* x0 = core mask
+ * x1 = NXP_PMU_CCSR_ADDR
+ * x2 = NXP_PMU_DCSR_ADDR
+ * x7 = hnf sdcr
+ * x8 = cpuactlr
+ */
+
+2:
+ /* save hnf-sdcr and cpuactlr to stack */
+ stp x7, x8, [sp, #-16]!
+
+ /* x0 = core mask
+ * x1 = NXP_PMU_CCSR_ADDR
+ * x2 = NXP_PMU_DCSR_ADDR
+ */
+
+ /* save the IPSTPCRn registers to stack */
+ mov x15, #PMU_IPSTPCR0_OFFSET
+ ldr w9, [x1, x15]
+ mov x16, #PMU_IPSTPCR1_OFFSET
+ ldr w10, [x1, x16]
+ mov x17, #PMU_IPSTPCR2_OFFSET
+ ldr w11, [x1, x17]
+ mov x18, #PMU_IPSTPCR3_OFFSET
+ ldr w12, [x1, x18]
+ mov x19, #PMU_IPSTPCR4_OFFSET
+ ldr w13, [x1, x19]
+ mov x20, #PMU_IPSTPCR5_OFFSET
+ ldr w14, [x1, x20]
+
+ stp x9, x10, [sp, #-16]!
+ stp x11, x12, [sp, #-16]!
+ stp x13, x14, [sp, #-16]!
+
+ /* x0 = core mask
+ * x1 = NXP_PMU_CCSR_ADDR
+ * x2 = NXP_PMU_DCSR_ADDR
+ * x15 = PMU_IPSTPCR0_OFFSET
+ * x16 = PMU_IPSTPCR1_OFFSET
+ * x17 = PMU_IPSTPCR2_OFFSET
+ * x18 = PMU_IPSTPCR3_OFFSET
+ * x19 = PMU_IPSTPCR4_OFFSET
+ * x20 = PMU_IPSTPCR5_OFFSET
+ */
+
+ /* load the full clock mask for IPSTPCR0 */
+ ldr x3, =DEVDISR1_MASK
+ /* get the exclusions */
+ mov x21, #PMU_IPPDEXPCR0_OFFSET
+ ldr w4, [x1, x21]
+ /* apply the exclusions to the mask */
+ bic w7, w3, w4
+ /* stop the clocks in IPSTPCR0 */
+ str w7, [x1, x15]
+
+ /* use same procedure for IPSTPCR1-IPSTPCR5 */
+
+ /* stop the clocks in IPSTPCR1 */
+ ldr x5, =DEVDISR2_MASK
+ mov x21, #PMU_IPPDEXPCR1_OFFSET
+ ldr w6, [x1, x21]
+ bic w8, w5, w6
+ str w8, [x1, x16]
+
+ /* stop the clocks in IPSTPCR2 */
+ ldr x3, =DEVDISR3_MASK
+ mov x21, #PMU_IPPDEXPCR2_OFFSET
+ ldr w4, [x1, x21]
+ bic w9, w3, w4
+ str w9, [x1, x17]
+
+ /* stop the clocks in IPSTPCR3 */
+ ldr x5, =DEVDISR4_MASK
+ mov x21, #PMU_IPPDEXPCR3_OFFSET
+ ldr w6, [x1, x21]
+ bic w10, w5, w6
+ str w10, [x1, x18]
+
+ /* stop the clocks in IPSTPCR4
+ * - exclude the ddr clocks as we are currently executing
+ * out of *some* memory, might be ddr
+ * - exclude the OCRAM clk so that we retain any code/data in
+ * OCRAM
+ * - may need to exclude the debug clock if we are testing
+ */
+ ldr x3, =DEVDISR5_MASK
+ mov w6, #DEVDISR5_MASK_ALL_MEM
+ bic w3, w3, w6
+
+ mov w5, #POLICY_DEBUG_ENABLE
+ cbz w5, 3f
+ mov w6, #DEVDISR5_MASK_DBG
+ bic w3, w3, w6
+3:
+ mov x21, #PMU_IPPDEXPCR4_OFFSET
+ ldr w4, [x1, x21]
+ bic w11, w3, w4
+ str w11, [x1, x19]
+
+ /* stop the clocks in IPSTPCR5 */
+ ldr x5, =DEVDISR6_MASK
+ mov x21, #PMU_IPPDEXPCR5_OFFSET
+ ldr w6, [x1, x21]
+ bic w12, w5, w6
+ str w12, [x1, x20]
+
+ /* x0 = core mask
+ * x1 = NXP_PMU_CCSR_ADDR
+ * x2 = NXP_PMU_DCSR_ADDR
+ * x7 = IPSTPCR0
+ * x8 = IPSTPCR1
+ * x9 = IPSTPCR2
+ * x10 = IPSTPCR3
+ * x11 = IPSTPCR4
+ * x12 = IPSTPCR5
+ */
+
+ /* poll until the clocks are stopped in IPSTPACKSR0 */
+ mov w4, #CLOCK_RETRY_CNT
+ mov x21, #PMU_IPSTPACKSR0_OFFSET
+4:
+ ldr w5, [x1, x21]
+ cmp w5, w7
+ b.eq 5f
+ sub w4, w4, #1
+ cbnz w4, 4b
+
+ /* poll until the clocks are stopped in IPSTPACKSR1 */
+5:
+ mov w4, #CLOCK_RETRY_CNT
+ mov x21, #PMU_IPSTPACKSR1_OFFSET
+6:
+ ldr w5, [x1, x21]
+ cmp w5, w8
+ b.eq 7f
+ sub w4, w4, #1
+ cbnz w4, 6b
+
+ /* poll until the clocks are stopped in IPSTPACKSR2 */
+7:
+ mov w4, #CLOCK_RETRY_CNT
+ mov x21, #PMU_IPSTPACKSR2_OFFSET
+8:
+ ldr w5, [x1, x21]
+ cmp w5, w9
+ b.eq 9f
+ sub w4, w4, #1
+ cbnz w4, 8b
+
+ /* poll until the clocks are stopped in IPSTPACKSR3 */
+9:
+ mov w4, #CLOCK_RETRY_CNT
+ mov x21, #PMU_IPSTPACKSR3_OFFSET
+10:
+ ldr w5, [x1, x21]
+ cmp w5, w10
+ b.eq 11f
+ sub w4, w4, #1
+ cbnz w4, 10b
+
+ /* poll until the clocks are stopped in IPSTPACKSR4 */
+11:
+ mov w4, #CLOCK_RETRY_CNT
+ mov x21, #PMU_IPSTPACKSR4_OFFSET
+12:
+ ldr w5, [x1, x21]
+ cmp w5, w11
+ b.eq 13f
+ sub w4, w4, #1
+ cbnz w4, 12b
+
+ /* poll until the clocks are stopped in IPSTPACKSR5 */
+13:
+ mov w4, #CLOCK_RETRY_CNT
+ mov x21, #PMU_IPSTPACKSR5_OFFSET
+14:
+ ldr w5, [x1, x21]
+ cmp w5, w12
+ b.eq 15f
+ sub w4, w4, #1
+ cbnz w4, 14b
+
+ /* x0 = core mask
+ * x1 = NXP_PMU_CCSR_ADDR
+ * x2 = NXP_PMU_DCSR_ADDR
+ * x7 = IPSTPCR0
+ * x8 = IPSTPCR1
+ * x9 = IPSTPCR2
+ * x10 = IPSTPCR3
+ * x11 = IPSTPCR4
+ * x12 = IPSTPCR5
+ */
+
+15:
+ mov x3, #NXP_DCFG_ADDR
+
+ /* save the devdisr registers to stack */
+ ldr w13, [x3, #DCFG_DEVDISR1_OFFSET]
+ ldr w14, [x3, #DCFG_DEVDISR2_OFFSET]
+ ldr w15, [x3, #DCFG_DEVDISR3_OFFSET]
+ ldr w16, [x3, #DCFG_DEVDISR4_OFFSET]
+ ldr w17, [x3, #DCFG_DEVDISR5_OFFSET]
+ ldr w18, [x3, #DCFG_DEVDISR6_OFFSET]
+
+ stp x13, x14, [sp, #-16]!
+ stp x15, x16, [sp, #-16]!
+ stp x17, x18, [sp, #-16]!
+
+ /* power down the IP in DEVDISR1 - corresponds to IPSTPCR0 */
+ str w7, [x3, #DCFG_DEVDISR1_OFFSET]
+
+ /* power down the IP in DEVDISR2 - corresponds to IPSTPCR1 */
+ str w8, [x3, #DCFG_DEVDISR2_OFFSET]
+
+ /* power down the IP in DEVDISR3 - corresponds to IPSTPCR2 */
+ str w9, [x3, #DCFG_DEVDISR3_OFFSET]
+
+ /* power down the IP in DEVDISR4 - corresponds to IPSTPCR3 */
+ str w10, [x3, #DCFG_DEVDISR4_OFFSET]
+
+ /* power down the IP in DEVDISR5 - corresponds to IPSTPCR4 */
+ str w11, [x3, #DCFG_DEVDISR5_OFFSET]
+
+ /* power down the IP in DEVDISR6 - corresponds to IPSTPCR5 */
+ str w12, [x3, #DCFG_DEVDISR6_OFFSET]
+
+ /* setup register values for the cache-only sequence */
+ mov x4, #NXP_DDR_ADDR
+ mov x5, #NXP_DDR2_ADDR
+ mov x6, x11
+ mov x7, x17
+ ldr x12, =PMU_CLAINACTSETR_OFFSET
+ ldr x13, =PMU_CLSINACTSETR_OFFSET
+ ldr x14, =PMU_CLAINACTCLRR_OFFSET
+ ldr x15, =PMU_CLSINACTCLRR_OFFSET
+
+ /* x0 = core mask
+ * x1 = NXP_PMU_CCSR_ADDR
+ * x2 = NXP_PMU_DCSR_ADDR
+ * x3 = NXP_DCFG_ADDR
+ * x4 = NXP_DDR_ADDR
+ * x5 = NXP_DDR2_ADDR
+ * w6 = IPSTPCR4
+ * w7 = DEVDISR5
+ * x12 = PMU_CLAINACTSETR_OFFSET
+ * x13 = PMU_CLSINACTSETR_OFFSET
+ * x14 = PMU_CLAINACTCLRR_OFFSET
+ * x15 = PMU_CLSINACTCLRR_OFFSET
+ */
+
+ mov x8, #POLICY_DEBUG_ENABLE
+ cbnz x8, 29f
+ /* force the debug interface to be quiescent */
+ mrs x9, OSDLR_EL1
+ orr x9, x9, #0x1
+ msr OSDLR_EL1, x9
+
+ /* enter the cache-only sequence */
+29:
+ bl final_pwrdown
+
+ /* when we are here, the core has come out of wfi and the
+ * ddr is back up
+ */
+
+ mov x8, #POLICY_DEBUG_ENABLE
+ cbnz x8, 30f
+ /* restart the debug interface */
+ mrs x9, OSDLR_EL1
+ mov x10, #1
+ bic x9, x9, x10
+ msr OSDLR_EL1, x9
+
+ /* get saved DEVDISR regs off stack */
+30:
+ ldp x17, x18, [sp], #16
+ ldp x15, x16, [sp], #16
+ ldp x13, x14, [sp], #16
+ /* restore DEVDISR regs */
+ str w18, [x3, #DCFG_DEVDISR6_OFFSET]
+ str w17, [x3, #DCFG_DEVDISR5_OFFSET]
+ str w16, [x3, #DCFG_DEVDISR4_OFFSET]
+ str w15, [x3, #DCFG_DEVDISR3_OFFSET]
+ str w14, [x3, #DCFG_DEVDISR2_OFFSET]
+ str w13, [x3, #DCFG_DEVDISR1_OFFSET]
+ isb
+
+ /* get saved IPSTPCRn regs off stack */
+ ldp x13, x14, [sp], #16
+ ldp x11, x12, [sp], #16
+ ldp x9, x10, [sp], #16
+
+ /* restore IPSTPCRn regs */
+ mov x15, #PMU_IPSTPCR5_OFFSET
+ str w14, [x1, x15]
+ mov x16, #PMU_IPSTPCR4_OFFSET
+ str w13, [x1, x16]
+ mov x17, #PMU_IPSTPCR3_OFFSET
+ str w12, [x1, x17]
+ mov x18, #PMU_IPSTPCR2_OFFSET
+ str w11, [x1, x18]
+ mov x19, #PMU_IPSTPCR1_OFFSET
+ str w10, [x1, x19]
+ mov x20, #PMU_IPSTPCR0_OFFSET
+ str w9, [x1, x20]
+ isb
+
+ /* poll on IPSTPACKCRn regs til IP clocks are restarted */
+ mov w4, #CLOCK_RETRY_CNT
+ mov x15, #PMU_IPSTPACKSR5_OFFSET
+16:
+ ldr w5, [x1, x15]
+ and w5, w5, w14
+ cbz w5, 17f
+ sub w4, w4, #1
+ cbnz w4, 16b
+
+17:
+ mov w4, #CLOCK_RETRY_CNT
+ mov x15, #PMU_IPSTPACKSR4_OFFSET
+18:
+ ldr w5, [x1, x15]
+ and w5, w5, w13
+ cbz w5, 19f
+ sub w4, w4, #1
+ cbnz w4, 18b
+
+19:
+ mov w4, #CLOCK_RETRY_CNT
+ mov x15, #PMU_IPSTPACKSR3_OFFSET
+20:
+ ldr w5, [x1, x15]
+ and w5, w5, w12
+ cbz w5, 21f
+ sub w4, w4, #1
+ cbnz w4, 20b
+
+21:
+ mov w4, #CLOCK_RETRY_CNT
+ mov x15, #PMU_IPSTPACKSR2_OFFSET
+22:
+ ldr w5, [x1, x15]
+ and w5, w5, w11
+ cbz w5, 23f
+ sub w4, w4, #1
+ cbnz w4, 22b
+
+23:
+ mov w4, #CLOCK_RETRY_CNT
+ mov x15, #PMU_IPSTPACKSR1_OFFSET
+24:
+ ldr w5, [x1, x15]
+ and w5, w5, w10
+ cbz w5, 25f
+ sub w4, w4, #1
+ cbnz w4, 24b
+
+25:
+ mov w4, #CLOCK_RETRY_CNT
+ mov x15, #PMU_IPSTPACKSR0_OFFSET
+26:
+ ldr w5, [x1, x15]
+ and w5, w5, w9
+ cbz w5, 27f
+ sub w4, w4, #1
+ cbnz w4, 26b
+
+27:
+ /* disable the stop-request-override */
+ mov x8, #PMU_POWMGTDCR0_OFFSET
+ mov w9, #POWMGTDCR_STP_OV_EN
+ str w9, [x2, x8]
+ isb
+
+ /* get hnf-sdcr and cpuactlr off stack */
+ ldp x7, x8, [sp], #16
+
+ /* restore cpuactlr */
+ msr CORTEX_A72_CPUACTLR_EL1, x8
+ isb
+
+ /* restore snooping in the hnf nodes */
+ ldr x9, =NXP_CCN_HN_F_0_ADDR
+ mov x6, #CCN_HNF_NODE_COUNT
+28:
+ str x7, [x9, #CCN_HN_F_SNP_DMN_CTL_SET_OFFSET]
+ sub x6, x6, #1
+ add x9, x9, #CCN_HNF_OFFSET
+ cbnz x6, 28b
+ isb
+
+ mov x30, x28
+ ret
+endfunc _soc_sys_pwrdn_wfi
+
+
+/* Part of CPU_SUSPEND
+ * Function performs any SoC-specific cleanup after power-down
+ * in: x0 = core mask lsb
+ * out: none
+ * uses x0,
+ */
+func _soc_sys_exit_pwrdn
+
+ mrs x1, CORTEX_A72_ECTLR_EL1
+ /* make sure the smp bit is set */
+ orr x1, x1, #CPUECTLR_SMPEN_MASK
+ /* clr the retention control */
+ mov x2, #CPUECTLR_RET_8CLK
+ bic x1, x1, x2
+ /* enable tablewalk prefetch */
+ mov x2, #CPUECTLR_DISABLE_TWALK_PREFETCH
+ bic x1, x1, x2
+ msr CORTEX_A72_ECTLR_EL1, x1
+ isb
+
+ ret
+endfunc _soc_sys_exit_pwrdn
+
+
+/* Function will pwrdown ddr and the final core - it will do this
+ * by loading itself into the icache and then executing from there
+ * in:
+ * x0 = core mask
+ * x1 = NXP_PMU_CCSR_ADDR
+ * x2 = NXP_PMU_DCSR_ADDR
+ * x3 = NXP_DCFG_ADDR
+ * x4 = NXP_DDR_ADDR
+ * x5 = NXP_DDR2_ADDR
+ * w6 = IPSTPCR4
+ * w7 = DEVDISR5
+ * x12 = PMU_CLAINACTSETR_OFFSET
+ * x13 = PMU_CLSINACTSETR_OFFSET
+ * x14 = PMU_CLAINACTCLRR_OFFSET
+ * x15 = PMU_CLSINACTCLRR_OFFSET
+ * out: none
+ * uses x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x13, x14, x15, x16,
+ * x17, x18
+ */
+
+/* 4Kb aligned */
+.align 12
+func final_pwrdown
+
+ mov x0, xzr
+ b touch_line_0
+start_line_0:
+ mov x0, #1
+ /* put ddr controller 1 into self-refresh */
+ ldr w8, [x4, #DDR_CFG_2_OFFSET]
+ orr w8, w8, #CFG_2_FORCE_REFRESH
+ str w8, [x4, #DDR_CFG_2_OFFSET]
+
+ /* put ddr controller 2 into self-refresh */
+ ldr w8, [x5, #DDR_CFG_2_OFFSET]
+ orr w8, w8, #CFG_2_FORCE_REFRESH
+ str w8, [x5, #DDR_CFG_2_OFFSET]
+
+ /* stop the clocks in both ddr controllers */
+ mov w10, #DEVDISR5_MASK_DDR
+ mov x16, #PMU_IPSTPCR4_OFFSET
+ orr w9, w6, w10
+ str w9, [x1, x16]
+ isb
+
+ mov x17, #PMU_IPSTPACKSR4_OFFSET
+touch_line_0:
+ cbz x0, touch_line_1
+
+start_line_1:
+ /* poll IPSTPACKSR4 until
+ * ddr controller clocks are stopped.
+ */
+1:
+ ldr w8, [x1, x17]
+ and w8, w8, w10
+ cmp w8, w10
+ b.ne 1b
+
+ /* shut down power to the ddr controllers */
+ orr w9, w7, #DEVDISR5_MASK_DDR
+ str w9, [x3, #DCFG_DEVDISR5_OFFSET]
+
+ /* disable cluster acp ports */
+ mov w8, #CLAINACT_DISABLE_ACP
+ str w8, [x1, x12]
+
+ /* disable skyros ports */
+ mov w9, #CLSINACT_DISABLE_SKY
+ str w9, [x1, x13]
+ isb
+
+touch_line_1:
+ cbz x0, touch_line_2
+
+start_line_2:
+ isb
+3:
+ wfi
+
+ /* if we are here then we are awake
+ * - bring this device back up
+ */
+
+ /* enable skyros ports */
+ mov w9, #CLSINACT_DISABLE_SKY
+ str w9, [x1, x15]
+
+ /* enable acp ports */
+ mov w8, #CLAINACT_DISABLE_ACP
+ str w8, [x1, x14]
+ isb
+
+ /* bring up the ddr controllers */
+ str w7, [x3, #DCFG_DEVDISR5_OFFSET]
+ isb
+ str w6, [x1, x16]
+ isb
+
+ nop
+touch_line_2:
+ cbz x0, touch_line_3
+
+start_line_3:
+ /* poll IPSTPACKSR4 until
+ * ddr controller clocks are running
+ */
+ mov w10, #DEVDISR5_MASK_DDR
+2:
+ ldr w8, [x1, x17]
+ and w8, w8, w10
+ cbnz w8, 2b
+
+ /* take ddr controller 2 out of self-refresh */
+ mov w8, #CFG_2_FORCE_REFRESH
+ ldr w9, [x5, #DDR_CFG_2_OFFSET]
+ bic w9, w9, w8
+ str w9, [x5, #DDR_CFG_2_OFFSET]
+
+ /* take ddr controller 1 out of self-refresh */
+ ldr w9, [x4, #DDR_CFG_2_OFFSET]
+ bic w9, w9, w8
+ str w9, [x4, #DDR_CFG_2_OFFSET]
+ isb
+
+ nop
+ nop
+ nop
+touch_line_3:
+ cbz x0, start_line_0
+
+ /* execute here after ddr is back up */
+
+ ret
+endfunc final_pwrdown
+
+/* Function returns CLUSTER_3_NORMAL if the cores of cluster 3 are
+ * to be handled normally, and it returns CLUSTER_3_IN_RESET if the cores
+ * are to be held in reset
+ * in: none
+ * out: x0 = #CLUSTER_3_NORMAL, cluster 3 treated normal
+ * x0 = #CLUSTER_3_IN_RESET, cluster 3 cores held in reset
+ * uses x0, x1, x2
+ */
+func cluster3InReset
+
+ /* default return is treat cores normal */
+ mov x0, #CLUSTER_3_NORMAL
+
+ /* read RCW_SR27 register */
+ mov x1, #NXP_DCFG_ADDR
+ ldr w2, [x1, #RCW_SR27_OFFSET]
+
+ /* test the cluster 3 bit */
+ tst w2, #CLUSTER_3_RCW_BIT
+ b.eq 1f
+
+ /* if we are here, then the bit was set */
+ mov x0, #CLUSTER_3_IN_RESET
+1:
+ ret
+endfunc cluster3InReset
+
+
+/* Function checks to see if cores which are to be disabled have been
+ * released from reset - if not, it releases them
+ * Note: there may be special handling of cluster 3 cores depending upon the
+ * sys clk frequency
+ * in: none
+ * out: none
+ * uses x0, x1, x2, x3, x4, x5, x6, x7, x8, x9
+ */
+func release_disabled
+ mov x9, x30
+
+ /* check if we need to keep cluster 3 cores in reset */
+ bl cluster3InReset /* 0-2 */
+ mov x8, x0
+
+ /* x8 = cluster 3 handling */
+
+ /* read COREDISABLESR */
+ mov x0, #NXP_DCFG_ADDR
+ ldr w4, [x0, #DCFG_COREDISABLEDSR_OFFSET]
+ cmp x8, #CLUSTER_3_IN_RESET
+ b.ne 4f
+
+ /* the cluster 3 cores are to be held in reset, so remove
+ * them from the disable mask
+ */
+ bic x4, x4, #CLUSTER_3_CORES_MASK
+4:
+ /* get the number of cpus on this device */
+ mov x6, #PLATFORM_CORE_COUNT
+
+ mov x0, #NXP_RESET_ADDR
+ ldr w5, [x0, #BRR_OFFSET]
+
+ /* load the core mask for the first core */
+ mov x7, #1
+
+ /* x4 = COREDISABLESR
+ * x5 = BRR
+ * x6 = loop count
+ * x7 = core mask bit
+ */
+2:
+ /* check if the core is to be disabled */
+ tst x4, x7
+ b.eq 1f
+
+ /* see if disabled cores have already been released from reset */
+ tst x5, x7
+ b.ne 5f
+
+ /* if core has not been released, then release it (0-3) */
+ mov x0, x7
+ bl _soc_core_release
+
+ /* record the core state in the data area (0-3) */
+ mov x0, x7
+ mov x1, #CORE_STATE_DATA
+ mov x2, #CORE_DISABLED
+ bl _setCoreData
+
+1:
+ /* see if this is a cluster 3 core */
+ mov x3, #CLUSTER_3_CORES_MASK
+ tst x3, x7
+ b.eq 5f
+
+ /* this is a cluster 3 core - see if it needs to be held in reset */
+ cmp x8, #CLUSTER_3_IN_RESET
+ b.ne 5f
+
+ /* record the core state as disabled in the data area (0-3) */
+ mov x0, x7
+ mov x1, #CORE_STATE_DATA
+ mov x2, #CORE_DISABLED
+ bl _setCoreData
+
+5:
+ /* decrement the counter */
+ subs x6, x6, #1
+ b.le 3f
+
+ /* shift the core mask to the next core */
+ lsl x7, x7, #1
+ /* continue */
+ b 2b
+3:
+ cmp x8, #CLUSTER_3_IN_RESET
+ b.ne 6f
+
+ /* we need to hold the cluster 3 cores in reset,
+ * so mark them in the COREDISR and COREDISABLEDSR registers as
+ * "disabled", and the rest of the sw stack will leave them alone
+ * thinking that they have been disabled
+ */
+ mov x0, #NXP_DCFG_ADDR
+ ldr w1, [x0, #DCFG_COREDISR_OFFSET]
+ orr w1, w1, #CLUSTER_3_CORES_MASK
+ str w1, [x0, #DCFG_COREDISR_OFFSET]
+
+ ldr w2, [x0, #DCFG_COREDISABLEDSR_OFFSET]
+ orr w2, w2, #CLUSTER_3_CORES_MASK
+ str w2, [x0, #DCFG_COREDISABLEDSR_OFFSET]
+ dsb sy
+ isb
+
+#if (PSCI_TEST)
+ /* x0 = NXP_DCFG_ADDR : read COREDISABLESR */
+ ldr w4, [x0, #DCFG_COREDISABLEDSR_OFFSET]
+ /* read COREDISR */
+ ldr w3, [x0, #DCFG_COREDISR_OFFSET]
+#endif
+
+6:
+ mov x30, x9
+ ret
+
+endfunc release_disabled
+
+
+/* Function setc up the TrustZone Address Space Controller (TZASC)
+ * in: none
+ * out: none
+ * uses x0, x1
+ */
+func init_tzpc
+
+ /* set Non Secure access for all devices protected via TZPC */
+
+ /* decode Protection-0 Set Reg */
+ ldr x1, =TZPCDECPROT_0_SET_BASE
+ /* set decode region to NS, Bits[7:0] */
+ mov w0, #0xFF
+ str w0, [x1]
+
+ /* decode Protection-1 Set Reg */
+ ldr x1, =TZPCDECPROT_1_SET_BASE
+ /* set decode region to NS, Bits[7:0] */
+ mov w0, #0xFF
+ str w0, [x1]
+
+ /* decode Protection-2 Set Reg */
+ ldr x1, =TZPCDECPROT_2_SET_BASE
+ /* set decode region to NS, Bits[7:0] */
+ mov w0, #0xFF
+ str w0, [x1]
+
+ /* entire SRAM as NS */
+ /* secure RAM region size Reg */
+ ldr x1, =TZPC_BASE
+ /* 0x00000000 = no secure region */
+ mov w0, #0x00000000
+ str w0, [x1]
+
+ ret
+endfunc init_tzpc
+
+/* write a register in the DCFG block
+ * in: x0 = offset
+ * in: w1 = value to write
+ * uses x0, x1, x2
+ */
+func _write_reg_dcfg
+ ldr x2, =NXP_DCFG_ADDR
+ str w1, [x2, x0]
+ ret
+endfunc _write_reg_dcfg
+
+
+/* read a register in the DCFG block
+ * in: x0 = offset
+ * out: w0 = value read
+ * uses x0, x1, x2
+ */
+func _read_reg_dcfg
+ ldr x2, =NXP_DCFG_ADDR
+ ldr w1, [x2, x0]
+ mov w0, w1
+ ret
+endfunc _read_reg_dcfg
+
+
+/* Function returns an mpidr value for a core, given a core_mask_lsb
+ * in: x0 = core mask lsb
+ * out: x0 = affinity2:affinity1:affinity0, where affinity is 8-bits
+ * uses x0, x1
+ */
+func get_mpidr_value
+
+ /* convert a core mask to an SoC core number */
+ clz w0, w0
+ mov w1, #31
+ sub w0, w1, w0
+
+ /* get the mpidr core number from the SoC core number */
+ mov w1, wzr
+ tst x0, #1
+ b.eq 1f
+ orr w1, w1, #1
+
+1:
+ /* extract the cluster number */
+ lsr w0, w0, #1
+ orr w0, w1, w0, lsl #8
+
+ ret
+endfunc get_mpidr_value
+
+
+/* Function returns the redistributor base address for the core specified
+ * in x1
+ * in: x0 - core mask lsb of specified core
+ * out: x0 = redistributor rd base address for specified core
+ * uses x0, x1, x2
+ */
+func get_gic_rd_base
+ clz w1, w0
+ mov w2, #0x20
+ sub w2, w2, w1
+ sub w2, w2, #1
+
+ ldr x0, =NXP_GICR_ADDR
+ mov x1, #GIC_RD_OFFSET
+
+ /* x2 = core number
+ * loop counter
+ */
+2:
+ cbz x2, 1f
+ add x0, x0, x1
+ sub x2, x2, #1
+ b 2b
+1:
+ ret
+endfunc get_gic_rd_base
+
+
+/* Function returns the redistributor base address for the core specified
+ * in x1
+ * in: x0 - core mask lsb of specified core
+ * out: x0 = redistributor sgi base address for specified core
+ * uses x0, x1, x2
+ */
+func get_gic_sgi_base
+ clz w1, w0
+ mov w2, #0x20
+ sub w2, w2, w1
+ sub w2, w2, #1
+
+ ldr x0, =NXP_GICR_SGI_ADDR
+ mov x1, #GIC_SGI_OFFSET
+
+ /* loop counter */
+2:
+ cbz x2, 1f /* x2 = core number */
+ add x0, x0, x1
+ sub x2, x2, #1
+ b 2b
+1:
+ ret
+endfunc get_gic_sgi_base
+
+/* Function writes a register in the RESET block
+ * in: x0 = offset
+ * in: w1 = value to write
+ * uses x0, x1, x2
+ */
+func _write_reg_reset
+ ldr x2, =NXP_RESET_ADDR
+ str w1, [x2, x0]
+ ret
+endfunc _write_reg_reset
+
+
+/* Function reads a register in the RESET block
+ * in: x0 = offset
+ * out: w0 = value read
+ * uses x0, x1
+ */
+func _read_reg_reset
+ ldr x1, =NXP_RESET_ADDR
+ ldr w0, [x1, x0]
+ ret
+endfunc _read_reg_reset
diff --git a/plat/nxp/soc-lx2160a/aarch64/lx2160a_helpers.S b/plat/nxp/soc-lx2160a/aarch64/lx2160a_helpers.S
new file mode 100644
index 0000000..c364dec
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/aarch64/lx2160a_helpers.S
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+
+#include <platform_def.h>
+
+.globl plat_secondary_cold_boot_setup
+.globl plat_is_my_cpu_primary
+.globl plat_reset_handler
+.globl platform_mem_init
+
+
+func platform_mem1_init
+ ret
+endfunc platform_mem1_init
+
+
+func platform_mem_init
+ ret
+endfunc platform_mem_init
+
+
+func apply_platform_errata
+
+ ret
+endfunc apply_platform_errata
+
+
+func plat_reset_handler
+ mov x29, x30
+ bl apply_platform_errata
+
+#if defined(IMAGE_BL31)
+ ldr x0, =POLICY_SMMU_PAGESZ_64K
+ cbz x0, 1f
+ /* Set the SMMU page size in the sACR register */
+ bl _set_smmu_pagesz_64
+#endif
+1:
+ mov x30, x29
+
+ ret
+endfunc plat_reset_handler
+
+
+/* void plat_secondary_cold_boot_setup (void);
+ *
+ * This function performs any platform specific actions
+ * needed for a secondary cpu after a cold reset e.g
+ * mark the cpu's presence, mechanism to place it in a
+ * holding pen etc.
+ */
+func plat_secondary_cold_boot_setup
+ /* lx2160a does not do cold boot for secondary CPU */
+cb_panic:
+ b cb_panic
+endfunc plat_secondary_cold_boot_setup
+
+
+/* unsigned int plat_is_my_cpu_primary (void);
+ *
+ * Find out whether the current cpu is the primary
+ * cpu.
+ */
+func plat_is_my_cpu_primary
+ mrs x0, mpidr_el1
+ and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
+ cmp x0, 0x0
+ cset w0, eq
+ ret
+endfunc plat_is_my_cpu_primary
diff --git a/plat/nxp/soc-lx2160a/aarch64/lx2160a_warm_rst.S b/plat/nxp/soc-lx2160a/aarch64/lx2160a_warm_rst.S
new file mode 100644
index 0000000..9dec3f2
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/aarch64/lx2160a_warm_rst.S
@@ -0,0 +1,229 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+.section .text, "ax"
+
+#include <asm_macros.S>
+
+#ifndef NXP_COINED_BB
+#include <flash_info.h>
+#include <fspi.h>
+#endif
+#include <regs.h>
+#ifdef NXP_COINED_BB
+#include <snvs.h>
+#endif
+
+#include <plat_warm_rst.h>
+#include <platform_def.h>
+
+#define SDRAM_CFG 0x110
+#define SDRAM_CFG_2 0x114
+#define SDRAM_MD_CNTL 0x120
+#define SDRAM_INTERVAL 0x124
+#define TIMING_CFG_10 0x258
+#define DEBUG_2 0xF04
+#define DEBUG_26 0xF64
+#define DDR_DSR2 0xB24
+
+#define DDR_CNTRLR_2 0x2
+#define COUNT_100 1000
+
+ .globl _soc_sys_warm_reset
+ .align 12
+
+func _soc_sys_warm_reset
+ mov x3, xzr
+ b touch_line0
+start_line0:
+ mov x3, #1
+ mov x2, #NUM_OF_DDRC
+ ldr x1, =NXP_DDR_ADDR
+1:
+ ldr w0, [x1, #SDRAM_CFG]
+ orr w0, w0, #SDRAM_CFG_MEM_HLT
+ str w0, [x1, #SDRAM_CFG]
+2:
+ ldr w0, [x1, #DEBUG_2]
+ and w0, w0, #DDR_DBG_2_MEM_IDLE
+ cbz w0, 2b
+
+ ldr w0, [x1, #DEBUG_26]
+ orr w0, w0, #DDR_DEBUG_26_BIT_12
+ orr w0, w0, #DDR_DEBUG_26_BIT_13
+ orr w0, w0, #DDR_DEBUG_26_BIT_14
+touch_line0:
+ cbz x3, touch_line1
+
+ orr w0, w0, #DDR_DEBUG_26_BIT_15
+ orr w0, w0, #DDR_DEBUG_26_BIT_16
+ str w0, [x1, #DEBUG_26]
+
+ ldr w0, [x1, #SDRAM_CFG_2]
+ orr w0, w0, #SDRAM_CFG2_FRC_SR
+ str w0, [x1, #SDRAM_CFG_2]
+
+3:
+ ldr w0, [x1, #DDR_DSR2]
+ orr w0, w0, #DDR_DSR_2_PHY_INIT_CMPLT
+ str w0, [x1, #DDR_DSR2]
+ ldr w0, [x1, #DDR_DSR2]
+ and w0, w0, #DDR_DSR_2_PHY_INIT_CMPLT
+ cbnz w0, 3b
+
+ ldr w0, [x1, #SDRAM_INTERVAL]
+ and w0, w0, #SDRAM_INTERVAL_REFINT_CLEAR
+ str w0, [x1, #SDRAM_INTERVAL]
+touch_line1:
+ cbz x3, touch_line2
+
+ ldr w0, [x1, #SDRAM_MD_CNTL]
+ orr w0, w0, #MD_CNTL_CKE(1)
+ orr w0, w0, #MD_CNTL_MD_EN
+ str w0, [x1, #SDRAM_MD_CNTL]
+
+ ldr w0, [x1, #TIMING_CFG_10]
+ orr w0, w0, #DDR_TIMING_CFG_10_T_STAB
+ str w0, [x1, #TIMING_CFG_10]
+
+ ldr w0, [x1, #SDRAM_CFG_2]
+ and w0, w0, #SDRAM_CFG2_FRC_SR_CLEAR
+ str w0, [x1, #SDRAM_CFG_2]
+
+4:
+ ldr w0, [x1, #DDR_DSR2]
+ and w0, w0, #DDR_DSR_2_PHY_INIT_CMPLT
+ cbz w0, 4b
+ nop
+touch_line2:
+ cbz x3, touch_line3
+
+ ldr w0, [x1, #DEBUG_26]
+ orr w0, w0, #DDR_DEBUG_26_BIT_25
+ and w0, w0, #DDR_DEBUG_26_BIT_24_CLEAR
+ str w0, [x1, #DEBUG_26]
+
+ cmp x2, #DDR_CNTRLR_2
+ b.ne 5f
+ ldr x1, =NXP_DDR2_ADDR
+ mov x2, xzr
+ b 1b
+
+5:
+ mov x5, xzr
+6:
+ add x5, x5, #1
+ cmp x5, #COUNT_100
+ b.ne 6b
+ nop
+touch_line3:
+ cbz x3, touch_line4
+#ifdef NXP_COINED_BB
+ ldr x1, =NXP_SNVS_ADDR
+ ldr w0, [x1, #NXP_APP_DATA_LP_GPR_OFFSET]
+
+ /* On Warm Boot is enabled, then zeroth bit
+ * of SNVS LP GPR register 0 will used
+ * to save the status of warm-reset as a cause.
+ */
+ orr w0, w0, #(1 << NXP_LPGPR_ZEROTH_BIT)
+
+ /* write back */
+ str w0, [x1, #NXP_APP_DATA_LP_GPR_OFFSET]
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+touch_line4:
+ cbz x3, touch_line6
+#elif !(ERLY_WRM_RST_FLG_FLSH_UPDT)
+ ldr x1, =NXP_FLEXSPI_ADDR
+ ldr w0, [x1, #FSPI_IPCMD]
+ orr w0, w0, #FSPI_IPCMD_TRG_MASK
+ str w0, [x1, #FSPI_IPCMD]
+7:
+ ldr w0, [x1, #FSPI_INTR]
+ and w0, w0, #FSPI_INTR_IPCMDDONE_MASK
+ cmp w0, #0
+ b.eq 7b
+
+ ldr w0, [x1, #FSPI_IPTXFCR]
+ orr w0, w0, #FSPI_IPTXFCR_CLR
+ str w0, [x1, #FSPI_IPTXFCR]
+
+ ldr w0, [x1, #FSPI_INTR]
+ orr w0, w0, #FSPI_INTR_IPCMDDONE_MASK
+ str w0, [x1, #FSPI_INTR]
+ nop
+touch_line4:
+ cbz x3, touch_line5
+ /* flexspi driver has an api
+ * is_flash_busy().
+ * Impelementation of the api will not
+ * fit-in in 1 cache line.
+ * instead a nop-cycles are introduced to
+ * simulate the wait time for flash write
+ * completion.
+ *
+ * Note: This wait time varies from flash to flash.
+ */
+
+ mov x0, #FLASH_WR_COMP_WAIT_BY_NOP_COUNT
+8:
+ sub x0, x0, #1
+ nop
+ cmp x0, #0
+ b.ne 8b
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+touch_line5:
+ cbz x3, touch_line6
+#endif
+ ldr x2, =NXP_RST_ADDR
+ /* clear the RST_REQ_MSK and SW_RST_REQ */
+ mov w0, #0x00000000
+ str w0, [x2, #RSTCNTL_OFFSET]
+
+ /* initiate the sw reset request */
+ mov w0, #SW_RST_REQ_INIT
+ str w0, [x2, #RSTCNTL_OFFSET]
+
+ /* In case this address range is mapped as cacheable,
+ * flush the write out of the dcaches.
+ */
+ add x2, x2, #RSTCNTL_OFFSET
+ dc cvac, x2
+ dsb st
+ isb
+
+ /* Function does not return */
+ b .
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+touch_line6:
+ cbz x3, start_line0
+
+endfunc _soc_sys_warm_reset
diff --git a/plat/nxp/soc-lx2160a/ddr_fip.mk b/plat/nxp/soc-lx2160a/ddr_fip.mk
new file mode 100644
index 0000000..f14a9e8
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/ddr_fip.mk
@@ -0,0 +1,97 @@
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+DDR_PHY_BIN_PATH ?= ./ddr-phy-binary/lx2160a
+
+ifeq (${DDR_IMEM_UDIMM_1D},)
+ DDR_IMEM_UDIMM_1D := ${DDR_PHY_BIN_PATH}/ddr4_pmu_train_imem.bin
+endif
+
+ifeq (${DDR_IMEM_UDIMM_2D},)
+ DDR_IMEM_UDIMM_2D := ${DDR_PHY_BIN_PATH}/ddr4_2d_pmu_train_imem.bin
+endif
+
+ifeq (${DDR_DMEM_UDIMM_1D},)
+ DDR_DMEM_UDIMM_1D := ${DDR_PHY_BIN_PATH}/ddr4_pmu_train_dmem.bin
+endif
+
+ifeq (${DDR_DMEM_UDIMM_2D},)
+ DDR_DMEM_UDIMM_2D := ${DDR_PHY_BIN_PATH}/ddr4_2d_pmu_train_dmem.bin
+endif
+
+ifeq (${DDR_IMEM_RDIMM_1D},)
+ DDR_IMEM_RDIMM_1D := ${DDR_PHY_BIN_PATH}/ddr4_rdimm_pmu_train_imem.bin
+endif
+
+ifeq (${DDR_IMEM_RDIMM_2D},)
+ DDR_IMEM_RDIMM_2D := ${DDR_PHY_BIN_PATH}/ddr4_rdimm2d_pmu_train_imem.bin
+endif
+
+ifeq (${DDR_DMEM_RDIMM_1D},)
+ DDR_DMEM_RDIMM_1D := ${DDR_PHY_BIN_PATH}/ddr4_rdimm_pmu_train_dmem.bin
+endif
+
+ifeq (${DDR_DMEM_RDIMM_2D},)
+ DDR_DMEM_RDIMM_2D := ${DDR_PHY_BIN_PATH}/ddr4_rdimm2d_pmu_train_dmem.bin
+endif
+
+$(shell mkdir -p '${BUILD_PLAT}')
+
+ifeq (${DDR_FIP_NAME},)
+ifeq (${TRUSTED_BOARD_BOOT},1)
+ DDR_FIP_NAME := ddr_fip_sec.bin
+else
+ DDR_FIP_NAME := ddr_fip.bin
+endif
+endif
+
+ifneq (${TRUSTED_BOARD_BOOT},1)
+
+DDR_FIP_ARGS += --ddr-immem-udimm-1d ${DDR_IMEM_UDIMM_1D} \
+ --ddr-immem-udimm-2d ${DDR_IMEM_UDIMM_2D} \
+ --ddr-dmmem-udimm-1d ${DDR_DMEM_UDIMM_1D} \
+ --ddr-dmmem-udimm-2d ${DDR_DMEM_UDIMM_2D} \
+ --ddr-immem-rdimm-1d ${DDR_IMEM_RDIMM_1D} \
+ --ddr-immem-rdimm-2d ${DDR_IMEM_RDIMM_2D} \
+ --ddr-dmmem-rdimm-1d ${DDR_DMEM_RDIMM_1D} \
+ --ddr-dmmem-rdimm-2d ${DDR_DMEM_RDIMM_2D}
+endif
+
+
+ifeq (${TRUSTED_BOARD_BOOT},1)
+ifeq (${MBEDTLS_DIR},)
+include plat/nxp/soc-lx2160a/ddr_sb.mk
+else
+include plat/nxp/soc-lx2160a/ddr_tbbr.mk
+
+# Variables for use with Certificate Generation Tool
+CRTTOOLPATH ?= tools/cert_create
+CRTTOOL ?= ${CRTTOOLPATH}/cert_create${BIN_EXT}
+
+ifneq (${GENERATE_COT},0)
+ddr_certificates: ${DDR_CRT_DEPS} ${CRTTOOL}
+ ${Q}${CRTTOOL} ${DDR_CRT_ARGS}
+ @${ECHO_BLANK_LINE}
+ @echo "Built $@ successfully"
+ @echo "DDR certificates can be found in ${BUILD_PLAT}"
+ @${ECHO_BLANK_LINE}
+endif
+endif
+endif
+
+# Variables for use with Firmware Image Package
+FIPTOOLPATH ?= tools/fiptool
+FIPTOOL ?= ${FIPTOOLPATH}/fiptool${BIN_EXT}
+
+${BUILD_PLAT}/${DDR_FIP_NAME}: ${DDR_FIP_DEPS} ${FIPTOOL}
+ $(eval ${CHECK_DDR_FIP_CMD})
+ ${Q}${FIPTOOL} create ${DDR_FIP_ARGS} $@
+ ${Q}${FIPTOOL} info $@
+ @${ECHO_BLANK_LINE}
+ @echo "Built $@ successfully"
+ @${ECHO_BLANK_LINE}
+
+fip_ddr: ${BUILD_PLAT}/${DDR_FIP_NAME}
diff --git a/plat/nxp/soc-lx2160a/ddr_sb.mk b/plat/nxp/soc-lx2160a/ddr_sb.mk
new file mode 100644
index 0000000..c11651e
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/ddr_sb.mk
@@ -0,0 +1,43 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+ifneq (${TRUSTED_BOARD_BOOT},0)
+
+ifeq (${GENERATE_COT},0)
+
+DDR_FIP_ARGS += --ddr-immem-udimm-1d ${DDR_IMEM_UDIMM_1D}.sb \
+ --ddr-immem-udimm-2d ${DDR_IMEM_UDIMM_2D}.sb \
+ --ddr-dmmem-udimm-1d ${DDR_DMEM_UDIMM_1D}.sb \
+ --ddr-dmmem-udimm-2d ${DDR_DMEM_UDIMM_2D}.sb \
+ --ddr-immem-rdimm-1d ${DDR_IMEM_RDIMM_1D}.sb \
+ --ddr-immem-rdimm-2d ${DDR_IMEM_RDIMM_2D}.sb \
+ --ddr-dmmem-rdimm-1d ${DDR_DMEM_RDIMM_1D}.sb \
+ --ddr-dmmem-rdimm-2d ${DDR_DMEM_RDIMM_2D}.sb
+endif
+
+UDIMM_DEPS = ${DDR_IMEM_UDIMM_1D}.sb ${DDR_IMEM_UDIMM_2D}.sb ${DDR_DMEM_UDIMM_1D}.sb ${DDR_DMEM_UDIMM_2D}.sb
+RDIMM_DEPS = ${DDR_IMEM_RDIMM_1D}.sb ${DDR_IMEM_RDIMM_2D}.sb ${DDR_DMEM_RDIMM_1D}.sb ${DDR_DMEM_RDIMM_2D}.sb
+DDR_FIP_DEPS += ${UDIMM_DEPS}
+DDR_FIP_DEPS += ${RDIMM_DEPS}
+
+# Max Size of CSF header (CSF_HDR_SZ = 0x3000).
+# Image will be appended at this offset of the header.
+# Path to CST directory is required to generate the CSF header,
+# and prepend it to image before fip image gets generated
+ifeq (${CST_DIR},)
+ $(error Error: CST_DIR not set)
+endif
+
+ifeq (${DDR_INPUT_FILE},)
+DDR_INPUT_FILE:= drivers/nxp/auth/csf_hdr_parser/${CSF_FILE}
+endif
+
+%.sb: %
+ @echo " Generating CSF Header for $@ $<"
+ $(CST_DIR)/create_hdr_esbc --in $< --out $@ --app_off ${CSF_HDR_SZ} \
+ --app $< ${DDR_INPUT_FILE}
+
+endif
diff --git a/plat/nxp/soc-lx2160a/ddr_tbbr.mk b/plat/nxp/soc-lx2160a/ddr_tbbr.mk
new file mode 100644
index 0000000..deb475b
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/ddr_tbbr.mk
@@ -0,0 +1,95 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# This file defines the keys and certificates that must be created to establish
+# a Chain of Trust for the DDR FW. These definitions include the
+# command line options passed to the cert_create and fiptool commands for DDR FW.
+# A DDR FW key is used for signing the DDR Firmware. The DDR key is authenticated
+# by the Trusted World Key. Two content certificates are created:
+# For DDR RDIMM Images [ signed by DDR FW Key]
+# For DDR UDIMM Images [ signed by DDR FW Key]
+#
+# Expected environment:
+#
+# BUILD_PLAT: output directory
+#
+# Build options added by this file:
+#
+# KEY_ALG
+# KEY_SIZE
+# TRUSTED_WORLD_KEY
+# NON_TRUSTED_WORLD_KEY
+#
+
+# Copy the tbbr.mk from PLAT_TOOL_PATH/cert_create_helper
+# to the ${PLAT_DIR}. So that cert_create is enabled
+# to create certificates for DDR
+$(shell cp ${PLAT_TOOL_PATH}/cert_create_helper/cert_create_tbbr.mk ${PLAT_DIR})
+
+# Certificate generation tool default parameters
+DDR_FW_CERT := ${BUILD_PLAT}/ddr_fw_key_cert.crt
+
+# Default non-volatile counter values (overridable by the platform)
+TFW_NVCTR_VAL ?= 0
+NTFW_NVCTR_VAL ?= 0
+
+# Pass the non-volatile counters to the cert_create tool
+$(eval $(call CERT_ADD_CMD_OPT,${TFW_NVCTR_VAL},--tfw-nvctr,DDR_))
+
+$(shell mkdir -p '${BUILD_PLAT}')
+
+ifeq (${DDR_KEY},)
+DDR_KEY=${BUILD_PLAT}/ddr.pem
+endif
+
+ifeq (${TRUSTED_KEY_CERT},)
+$(info Generating: Trusted key certificate as part of DDR cert creation)
+TRUSTED_KEY_CERT := ${BUILD_PLAT}/trusted_key.crt
+$(eval $(call TOOL_ADD_PAYLOAD,${TRUSTED_KEY_CERT},--trusted-key-cert,))
+$(eval $(call TOOL_ADD_PAYLOAD,${TRUSTED_KEY_CERT},--trusted-key-cert,,DDR_))
+else
+$(info Using: Trusted key certificate as part of DDR cert creation)
+DDR_FIP_ARGS += --trusted-key-cert ${TRUSTED_KEY_CERT}
+endif
+
+# Add the keys to the cert_create command line options (private keys are NOT
+# packed in the FIP). Developers can use their own keys by specifying the proper
+# build option in the command line when building the Trusted Firmware
+$(if ${KEY_ALG},$(eval $(call CERT_ADD_CMD_OPT,${KEY_ALG},--key-alg,DDR_)))
+$(if ${KEY_SIZE},$(eval $(call CERT_ADD_CMD_OPT,${KEY_SIZE},--key-size,DDR_)))
+$(if ${HASH_ALG},$(eval $(call CERT_ADD_CMD_OPT,${HASH_ALG},--hash-alg,DDR_)))
+$(if ${ROT_KEY},$(eval $(call CERT_ADD_CMD_OPT,${ROT_KEY},--rot-key,DDR_)))
+$(if ${TRUSTED_WORLD_KEY},$(eval $(call CERT_ADD_CMD_OPT,${TRUSTED_WORLD_KEY},--trusted-world-key,DDR_)))
+$(if ${NON_TRUSTED_WORLD_KEY},$(eval $(call CERT_ADD_CMD_OPT,${NON_TRUSTED_WORLD_KEY},--non-trusted-world-key, DDR_)))
+
+# Add the DDR CoT (key cert + img cert)
+$(if ${DDR_KEY},$(eval $(call CERT_ADD_CMD_OPT,${DDR_KEY},--ddr-fw-key,DDR_)))
+$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/ddr_fw_key.crt,--ddr-fw-key-cert,,DDR_))
+$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/ddr_udimm_fw_content.crt,--ddr-udimm-fw-cert,,DDR_))
+$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/ddr_rdimm_fw_content.crt,--ddr-rdimm-fw-cert,,DDR_))
+
+$(eval $(call TOOL_ADD_IMG,DDR_IMEM_UDIMM_1D,--ddr-immem-udimm-1d,DDR_))
+$(eval $(call TOOL_ADD_IMG,DDR_IMEM_UDIMM_2D,--ddr-immem-udimm-2d,DDR_))
+$(eval $(call TOOL_ADD_IMG,DDR_DMEM_UDIMM_1D,--ddr-dmmem-udimm-1d,DDR_))
+$(eval $(call TOOL_ADD_IMG,DDR_DMEM_UDIMM_2D,--ddr-dmmem-udimm-2d,DDR_))
+
+$(eval $(call TOOL_ADD_IMG,DDR_IMEM_RDIMM_1D,--ddr-immem-rdimm-1d,DDR_))
+$(eval $(call TOOL_ADD_IMG,DDR_IMEM_RDIMM_2D,--ddr-immem-rdimm-2d,DDR_))
+$(eval $(call TOOL_ADD_IMG,DDR_DMEM_RDIMM_1D,--ddr-dmmem-rdimm-1d,DDR_))
+$(eval $(call TOOL_ADD_IMG,DDR_DMEM_RDIMM_2D,--ddr-dmmem-rdimm-2d,DDR_))
+
+DDR_FIP_DEPS += ddr_certificates
+
+# Process TBB related flags
+ifneq (${GENERATE_COT},0)
+ # Common cert_create options
+ ifneq (${CREATE_KEYS},0)
+ $(eval DDR_CRT_ARGS += -n)
+ ifneq (${SAVE_KEYS},0)
+ $(eval DDR_CRT_ARGS += -k)
+ endif
+ endif
+endif
diff --git a/plat/nxp/soc-lx2160a/include/soc.h b/plat/nxp/soc-lx2160a/include/soc.h
new file mode 100644
index 0000000..7cc4a03
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/include/soc.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _SOC_H
+#define _SOC_H
+
+/* Chassis specific defines - common across SoC's of a particular platform */
+#include <dcfg_lsch3.h>
+#include <soc_default_base_addr.h>
+#include <soc_default_helper_macros.h>
+
+
+#define NUM_DRAM_REGIONS 3
+#define NXP_DRAM0_ADDR 0x80000000
+#define NXP_DRAM0_MAX_SIZE 0x80000000 /* 2 GB */
+
+#define NXP_DRAM1_ADDR 0x2080000000
+#define NXP_DRAM1_MAX_SIZE 0x1F80000000 /* 126 G */
+
+#define NXP_DRAM2_ADDR 0x6000000000
+#define NXP_DRAM2_MAX_SIZE 0x2000000000 /* 128G */
+
+/*DRAM0 Size defined in platform_def.h */
+#define NXP_DRAM0_SIZE PLAT_DEF_DRAM0_SIZE
+
+#define DDR_PLL_FIX
+#define NXP_DDR_PHY1_ADDR 0x01400000
+#define NXP_DDR_PHY2_ADDR 0x01600000
+
+#if defined(IMAGE_BL31)
+#define LS_SYS_TIMCTL_BASE 0x2890000
+
+#ifdef LS_SYS_TIMCTL_BASE
+#define PLAT_LS_NSTIMER_FRAME_ID 0
+#define LS_CONFIG_CNTACR 1
+#endif
+#endif
+
+/* Start: Macros used by soc.c: get_boot_dev */
+#define PORSR1_RCW_MASK 0x07800000
+#define PORSR1_RCW_SHIFT 23
+
+#define SDHC1_VAL 0x8
+#define SDHC2_VAL 0x9
+#define I2C1_VAL 0xa
+#define FLEXSPI_NAND2K_VAL 0xc
+#define FLEXSPI_NAND4K_VAL 0xd
+#define FLEXSPI_NOR 0xf
+/* End: Macros used by soc.c: get_boot_dev */
+
+/* SVR Definition (not include major and minor rev) */
+#define SVR_LX2160A 0x873601
+#define SVR_LX2120A 0x873621
+#define SVR_LX2080A 0x873603
+
+/* Number of cores in platform */
+/* Used by common code for array initialization */
+#define NUMBER_OF_CLUSTERS 8
+#define CORES_PER_CLUSTER 2
+#define PLATFORM_CORE_COUNT NUMBER_OF_CLUSTERS * CORES_PER_CLUSTER
+
+/*
+ * Required LS standard platform porting definitions
+ * for CCN-508
+ */
+#define PLAT_CLUSTER_TO_CCN_ID_MAP 11, 15, 27, 31, 12, 28, 16, 0
+#define PLAT_6CLUSTER_TO_CCN_ID_MAP 11, 15, 27, 31, 12, 28
+
+
+/* Defines required for using XLAT tables from ARM common code */
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 40)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 40)
+
+/* Clock Divisors */
+#define NXP_PLATFORM_CLK_DIVIDER 2
+#define NXP_UART_CLK_DIVIDER 4
+
+/* Start: Macros used by lx2160a.S */
+#define MPIDR_AFFINITY0_MASK 0x00FF
+#define MPIDR_AFFINITY1_MASK 0xFF00
+#define CPUECTLR_DISABLE_TWALK_PREFETCH 0x4000000000
+#define CPUECTLR_INS_PREFETCH_MASK 0x1800000000
+#define CPUECTLR_DAT_PREFETCH_MASK 0x0300000000
+#define CPUECTLR_RET_8CLK 0x2
+#define OSDLR_EL1_DLK_LOCK 0x1
+#define CNTP_CTL_EL0_EN 0x1
+#define CNTP_CTL_EL0_IMASK 0x2
+/* set to 0 if the clusters are not symmetrical */
+#define SYMMETRICAL_CLUSTERS 1
+/* End: Macros used by lx2160a.S */
+
+/* Start: Macros used by lib/psci files */
+#define SYSTEM_PWR_DOMAINS 1
+#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
+ NUMBER_OF_CLUSTERS + \
+ SYSTEM_PWR_DOMAINS)
+
+/* Power state coordination occurs at the system level */
+#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
+
+/* define retention state */
+#define PLAT_MAX_RET_STATE (PSCI_LOCAL_STATE_RUN + 1)
+
+/* define power-down state */
+#define PLAT_MAX_OFF_STATE (PLAT_MAX_RET_STATE + 1)
+/* End: Macros used by lib/psci files */
+
+/* Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ *
+ * CACHE_WRITEBACK_GRANULE is defined in soc.def
+ *
+ * One cache line needed for bakery locks on ARM platforms
+ */
+#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
+
+#ifndef WDOG_RESET_FLAG
+#define WDOG_RESET_FLAG DEFAULT_SET_VALUE
+#endif
+
+#ifndef WARM_BOOT_SUCCESS
+#define WARM_BOOT_SUCCESS DEFAULT_SET_VALUE
+#endif
+
+#ifndef __ASSEMBLER__
+
+void set_base_freq_CNTFID0(void);
+void soc_init_start(void);
+void soc_init_finish(void);
+void soc_init_percpu(void);
+void _soc_set_start_addr(unsigned long addr);
+void _set_platform_security(void);
+
+#endif
+
+#endif /* _SOC_H */
diff --git a/plat/nxp/soc-lx2160a/lx2160aqds/ddr_init.c b/plat/nxp/soc-lx2160a/lx2160aqds/ddr_init.c
new file mode 100644
index 0000000..d44733c
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2160aqds/ddr_init.c
@@ -0,0 +1,355 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <ddr.h>
+#include <lib/utils.h>
+#include <load_img.h>
+
+#include "plat_common.h"
+#include <platform_def.h>
+
+#ifdef CONFIG_STATIC_DDR
+
+const struct ddr_cfg_regs static_3200 = {
+ .cs[0].bnds = U(0x03FF),
+ .cs[1].bnds = U(0x03FF),
+ .cs[0].config = U(0x80050422),
+ .cs[1].config = U(0x80000422),
+ .cs[2].bnds = U(0x00),
+ .cs[3].bnds = U(0x00),
+ .cs[2].config = U(0x00),
+ .cs[3].config = U(0x00),
+ .timing_cfg[0] = U(0xFFAA0018),
+ .timing_cfg[1] = U(0x646A8844),
+ .timing_cfg[2] = U(0x00058022),
+ .timing_cfg[3] = U(0x13622100),
+ .timing_cfg[4] = U(0x02),
+ .timing_cfg[5] = U(0x07401400),
+ .timing_cfg[7] = U(0x3BB00000),
+ .timing_cfg[8] = U(0x0944AC00),
+ .sdram_cfg[0] = U(0x65044008),
+ .sdram_cfg[1] = U(0x00401011),
+ .sdram_cfg[2] = U(0x00),
+ .sdram_mode[0] = U(0x06010C50),
+ .sdram_mode[1] = U(0x00280400),
+ .sdram_mode[2] = U(0x00),
+ .sdram_mode[3] = U(0x00),
+ .sdram_mode[4] = U(0x00),
+ .sdram_mode[5] = U(0x00),
+ .sdram_mode[6] = U(0x00),
+ .sdram_mode[7] = U(0x00),
+ .sdram_mode[8] = U(0x0500),
+ .sdram_mode[9] = U(0x10240000),
+ .sdram_mode[10] = U(0x00),
+ .sdram_mode[11] = U(0x00),
+ .sdram_mode[12] = U(0x00),
+ .sdram_mode[13] = U(0x00),
+ .sdram_mode[14] = U(0x00),
+ .sdram_mode[15] = U(0x00),
+ .md_cntl = U(0x00),
+ .interval = U(0x30C00000),
+ .data_init = U(0xDEADBEEF),
+ .init_addr = U(0x00),
+ .zq_cntl = U(0x8A090705),
+ .sdram_rcw[0] = U(0x00),
+ .sdram_rcw[1] = U(0x00),
+ .sdram_rcw[2] = U(0x00),
+ .sdram_rcw[3] = U(0x00),
+ .sdram_rcw[4] = U(0x00),
+ .sdram_rcw[5] = U(0x00),
+ .err_disable = U(0x00),
+ .err_int_en = U(0x00),
+};
+
+const struct ddr_cfg_regs static_2900 = {
+ .cs[0].bnds = U(0x03FF),
+ .cs[1].bnds = U(0x03FF),
+ .cs[0].config = U(0x80050422),
+ .cs[1].config = U(0x80000422),
+ .cs[2].bnds = U(0x00),
+ .cs[3].bnds = U(0x00),
+ .cs[2].config = U(0x00),
+ .cs[3].config = U(0x00),
+ .timing_cfg[0] = U(0xFF990018),
+ .timing_cfg[1] = U(0x4F4A4844),
+ .timing_cfg[2] = U(0x0005601F),
+ .timing_cfg[3] = U(0x125F2100),
+ .timing_cfg[4] = U(0x02),
+ .timing_cfg[5] = U(0x07401400),
+ .timing_cfg[7] = U(0x3AA00000),
+ .timing_cfg[8] = U(0x09449B00),
+ .sdram_cfg[0] = U(0x65044008),
+ .sdram_cfg[1] = U(0x00401011),
+ .sdram_cfg[2] = U(0x00),
+ .sdram_mode[0] = U(0x06010C50),
+ .sdram_mode[1] = U(0x00280400),
+ .sdram_mode[2] = U(0x00),
+ .sdram_mode[3] = U(0x00),
+ .sdram_mode[4] = U(0x00),
+ .sdram_mode[5] = U(0x00),
+ .sdram_mode[6] = U(0x00),
+ .sdram_mode[7] = U(0x00),
+ .sdram_mode[8] = U(0x0500),
+ .sdram_mode[9] = U(0x10240000),
+ .sdram_mode[10] = U(0x00),
+ .sdram_mode[11] = U(0x00),
+ .sdram_mode[12] = U(0x00),
+ .sdram_mode[13] = U(0x00),
+ .sdram_mode[14] = U(0x00),
+ .sdram_mode[15] = U(0x00),
+ .md_cntl = U(0x00),
+ .interval = U(0x2C2E0000),
+ .data_init = U(0xDEADBEEF),
+ .init_addr = U(0x00),
+ .zq_cntl = U(0x8A090705),
+ .sdram_rcw[0] = U(0x00),
+ .sdram_rcw[1] = U(0x00),
+ .sdram_rcw[2] = U(0x00),
+ .sdram_rcw[3] = U(0x00),
+ .sdram_rcw[4] = U(0x00),
+ .sdram_rcw[5] = U(0x00),
+ .err_disable = U(0x00),
+ .err_int_en = U(0x00),
+};
+
+const struct ddr_cfg_regs static_2600 = {
+ .cs[0].bnds = U(0x03FF),
+ .cs[1].bnds = U(0x03FF),
+ .cs[0].config = U(0x80050422),
+ .cs[1].config = U(0x80000422),
+ .cs[2].bnds = U(0x00),
+ .cs[3].bnds = U(0x00),
+ .cs[2].config = U(0x00),
+ .cs[3].config = U(0x00),
+ .timing_cfg[0] = U(0xFF880018),
+ .timing_cfg[1] = U(0x2A24F444),
+ .timing_cfg[2] = U(0x007141DC),
+ .timing_cfg[3] = U(0x125B2100),
+ .timing_cfg[4] = U(0x02),
+ .timing_cfg[5] = U(0x06401400),
+ .timing_cfg[7] = U(0x28800000),
+ .timing_cfg[8] = U(0x07338A00),
+ .sdram_cfg[0] = U(0x65044008),
+ .sdram_cfg[1] = U(0x00401011),
+ .sdram_cfg[2] = U(0x00),
+ .sdram_mode[0] = U(0x06010A70),
+ .sdram_mode[1] = U(0x00200400),
+ .sdram_mode[2] = U(0x00),
+ .sdram_mode[3] = U(0x00),
+ .sdram_mode[4] = U(0x00),
+ .sdram_mode[5] = U(0x00),
+ .sdram_mode[6] = U(0x00),
+ .sdram_mode[7] = U(0x00),
+ .sdram_mode[8] = U(0x0500),
+ .sdram_mode[9] = U(0x0C240000),
+ .sdram_mode[10] = U(0x00),
+ .sdram_mode[11] = U(0x00),
+ .sdram_mode[12] = U(0x00),
+ .sdram_mode[13] = U(0x00),
+ .sdram_mode[14] = U(0x00),
+ .sdram_mode[15] = U(0x00),
+ .md_cntl = U(0x00),
+ .interval = U(0x279C0000),
+ .data_init = U(0xDEADBEEF),
+ .init_addr = U(0x00),
+ .zq_cntl = U(0x8A090705),
+ .sdram_rcw[0] = U(0x00),
+ .sdram_rcw[1] = U(0x00),
+ .sdram_rcw[2] = U(0x00),
+ .sdram_rcw[3] = U(0x00),
+ .sdram_rcw[4] = U(0x00),
+ .sdram_rcw[5] = U(0x00),
+ .err_disable = U(0x00),
+ .err_int_en = U(0x00),
+};
+
+const struct dimm_params static_dimm = {
+ .rdimm = U(0),
+ .primary_sdram_width = U(64),
+ .ec_sdram_width = U(8),
+ .n_ranks = U(2),
+ .device_width = U(8),
+ .mirrored_dimm = U(1),
+};
+
+/* Sample code using two UDIMM MT18ASF1G72AZ-2G6B1, on each DDR controller */
+unsigned long long board_static_ddr(struct ddr_info *priv)
+{
+ (void)memcpy(&priv->ddr_reg, &static_2900, sizeof(static_2900));
+ (void)memcpy(&priv->dimm, &static_dimm, sizeof(static_dimm));
+ priv->conf.cs_on_dimm[0] = 0x3;
+ ddr_board_options(priv);
+ compute_ddr_phy(priv);
+
+ return ULL(0x400000000);
+}
+
+#elif defined(CONFIG_DDR_NODIMM)
+/*
+ * Sample code to bypass reading SPD. This is a sample, not recommended
+ * for boards with slots. DDR model number: UDIMM MT18ASF1G72AZ-2G6B1.
+ */
+
+const struct dimm_params ddr_raw_timing = {
+ .n_ranks = U(2),
+ .rank_density = U(4294967296u),
+ .capacity = U(8589934592u),
+ .primary_sdram_width = U(64),
+ .ec_sdram_width = U(8),
+ .device_width = U(8),
+ .die_density = U(0x4),
+ .rdimm = U(0),
+ .mirrored_dimm = U(1),
+ .n_row_addr = U(15),
+ .n_col_addr = U(10),
+ .bank_addr_bits = U(0),
+ .bank_group_bits = U(2),
+ .edc_config = U(2),
+ .burst_lengths_bitmask = U(0x0c),
+ .tckmin_x_ps = 750,
+ .tckmax_ps = 1600,
+ .caslat_x = U(0x00FFFC00),
+ .taa_ps = 13750,
+ .trcd_ps = 13750,
+ .trp_ps = 13750,
+ .tras_ps = 32000,
+ .trc_ps = 457500,
+ .twr_ps = 15000,
+ .trfc1_ps = 260000,
+ .trfc2_ps = 160000,
+ .trfc4_ps = 110000,
+ .tfaw_ps = 21000,
+ .trrds_ps = 3000,
+ .trrdl_ps = 4900,
+ .tccdl_ps = 5000,
+ .refresh_rate_ps = U(7800000),
+};
+
+int ddr_get_ddr_params(struct dimm_params *pdimm,
+ struct ddr_conf *conf)
+{
+ static const char dimm_model[] = "Fixed DDR on board";
+
+ conf->dimm_in_use[0] = 1; /* Modify accordingly */
+ memcpy(pdimm, &ddr_raw_timing, sizeof(struct dimm_params));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+
+ /* valid DIMM mask, change accordingly, together with dimm_on_ctlr. */
+ return 0x5;
+}
+#endif /* CONFIG_DDR_NODIMM */
+
+int ddr_board_options(struct ddr_info *priv)
+{
+ struct memctl_opt *popts = &priv->opt;
+ const struct ddr_conf *conf = &priv->conf;
+
+ popts->vref_dimm = U(0x24); /* range 1, 83.4% */
+ popts->rtt_override = 0;
+ popts->rtt_park = U(240);
+ popts->otf_burst_chop_en = 0;
+ popts->burst_length = U(DDR_BL8);
+ popts->trwt_override = U(1);
+ popts->bstopre = U(0); /* auto precharge */
+ popts->addr_hash = 1;
+
+ /* Set ODT impedance on PHY side */
+ switch (conf->cs_on_dimm[1]) {
+ case 0xc: /* Two slots dual rank */
+ case 0x4: /* Two slots single rank, not valid for interleaving */
+ popts->trwt = U(0xf);
+ popts->twrt = U(0x7);
+ popts->trrt = U(0x7);
+ popts->twwt = U(0x7);
+ popts->vref_phy = U(0x6B); /* 83.6% */
+ popts->odt = U(60);
+ popts->phy_tx_impedance = U(28);
+ break;
+ case 0: /* One slot used */
+ default:
+ popts->trwt = U(0x3);
+ popts->twrt = U(0x3);
+ popts->trrt = U(0x3);
+ popts->twwt = U(0x3);
+ popts->vref_phy = U(0x60); /* 75% */
+ popts->odt = U(48);
+ popts->phy_tx_impedance = U(28);
+ break;
+ }
+
+ return 0;
+}
+
+#ifdef NXP_WARM_BOOT
+long long init_ddr(uint32_t wrm_bt_flg)
+#else
+long long init_ddr(void)
+#endif
+{
+ int spd_addr[] = {0x51U, 0x52U, 0x53U, 0x54U};
+ struct ddr_info info;
+ struct sysinfo sys;
+ long long dram_size;
+
+ zeromem(&sys, sizeof(sys));
+ if (get_clocks(&sys) == 1) {
+ ERROR("System clocks are not set.\n");
+ panic();
+ }
+ debug("platform clock %lu\n", sys.freq_platform);
+ debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
+ debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
+
+ zeromem(&info, sizeof(info));
+
+ /* Set two DDRC. Unused DDRC will be removed automatically. */
+ info.num_ctlrs = NUM_OF_DDRC;
+ info.spd_addr = spd_addr;
+ info.ddr[0] = (void *)NXP_DDR_ADDR;
+ info.ddr[1] = (void *)NXP_DDR2_ADDR;
+ info.phy[0] = (void *)NXP_DDR_PHY1_ADDR;
+ info.phy[1] = (void *)NXP_DDR_PHY2_ADDR;
+ info.clk = get_ddr_freq(&sys, 0);
+ info.img_loadr = load_img;
+ info.phy_gen2_fw_img_buf = PHY_GEN2_FW_IMAGE_BUFFER;
+ if (info.clk == 0) {
+ info.clk = get_ddr_freq(&sys, 1);
+ }
+ info.dimm_on_ctlr = DDRC_NUM_DIMM;
+
+ info.warm_boot_flag = DDR_WRM_BOOT_NT_SUPPORTED;
+#ifdef NXP_WARM_BOOT
+ info.warm_boot_flag = DDR_COLD_BOOT;
+ if (wrm_bt_flg != 0U) {
+ info.warm_boot_flag = DDR_WARM_BOOT;
+ } else {
+ info.warm_boot_flag = DDR_COLD_BOOT;
+ }
+#endif
+
+ dram_size = dram_init(&info
+#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
+ , NXP_CCN_HN_F_0_ADDR
+#endif
+ );
+
+
+ if (dram_size < 0) {
+ ERROR("DDR init failed.\n");
+ }
+
+ return dram_size;
+}
diff --git a/plat/nxp/soc-lx2160a/lx2160aqds/plat_def.h b/plat/nxp/soc-lx2160a/lx2160aqds/plat_def.h
new file mode 100644
index 0000000..f480f92
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2160aqds/plat_def.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PLAT_DEF_H
+#define PLAT_DEF_H
+
+#include <arch.h>
+#include <cortex_a72.h>
+/* Required without TBBR.
+ * To include the defines for DDR PHY
+ * Images.
+ */
+#include <tbbr_img_def.h>
+
+#include <policy.h>
+#include <soc.h>
+
+#if defined(IMAGE_BL31)
+#define LS_SYS_TIMCTL_BASE 0x2890000
+#define PLAT_LS_NSTIMER_FRAME_ID 0
+#define LS_CONFIG_CNTACR 1
+#endif
+
+#define NXP_SYSCLK_FREQ 100000000
+#define NXP_DDRCLK_FREQ 100000000
+
+/* UART related definition */
+#define NXP_CONSOLE_ADDR NXP_UART_ADDR
+#define NXP_CONSOLE_BAUDRATE 115200
+
+/* Size of cacheable stacks */
+#if defined(IMAGE_BL2)
+#if defined(TRUSTED_BOARD_BOOT)
+#define PLATFORM_STACK_SIZE 0x2000
+#else
+#define PLATFORM_STACK_SIZE 0x1000
+#endif
+#elif defined(IMAGE_BL31)
+#define PLATFORM_STACK_SIZE 0x1000
+#endif
+
+/* SD block buffer */
+#define NXP_SD_BLOCK_BUF_SIZE (0x8000)
+#define NXP_SD_BLOCK_BUF_ADDR (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \
+ - NXP_SD_BLOCK_BUF_SIZE)
+
+#ifdef SD_BOOT
+#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \
+ - NXP_SD_BLOCK_BUF_SIZE)
+#else
+#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
+#endif
+
+/* IO defines as needed by IO driver framework */
+#define MAX_IO_DEVICES 4
+#define MAX_IO_BLOCK_DEVICES 1
+#define MAX_IO_HANDLES 4
+
+#define PHY_GEN2_FW_IMAGE_BUFFER (NXP_OCRAM_ADDR + CSF_HDR_SZ)
+
+/*
+ * FIP image defines - Offset at which FIP Image would be present
+ * Image would include Bl31 , Bl33 and Bl32 (optional)
+ */
+#ifdef POLICY_FUSE_PROVISION
+#define MAX_FIP_DEVICES 3
+#endif
+
+#ifndef MAX_FIP_DEVICES
+#define MAX_FIP_DEVICES 2
+#endif
+
+/*
+ * ID of the secure physical generic timer interrupt used by the BL32.
+ */
+#define BL32_IRQ_SEC_PHY_TIMER 29
+
+#define BL31_WDOG_SEC 89
+
+#define BL31_NS_WDOG_WS1 108
+
+/*
+ * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLAT_LS_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE)
+
+/* SGI 15 and Secure watchdog interrupts assigned to Group 0 */
+#define NXP_IRQ_SEC_SGI_7 15
+
+#define PLAT_LS_G0_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(BL31_NS_WDOG_WS1, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(NXP_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL)
+#endif
diff --git a/plat/nxp/soc-lx2160a/lx2160aqds/platform.c b/plat/nxp/soc-lx2160a/lx2160aqds/platform.c
new file mode 100644
index 0000000..b00adb5
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2160aqds/platform.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <plat_common.h>
+
+#pragma weak board_enable_povdd
+#pragma weak board_disable_povdd
+
+bool board_enable_povdd(void)
+{
+#ifdef CONFIG_POVDD_ENABLE
+ return true;
+#else
+ return false;
+#endif
+}
+
+bool board_disable_povdd(void)
+{
+#ifdef CONFIG_POVDD_ENABLE
+ return true;
+#else
+ return false;
+#endif
+}
diff --git a/plat/nxp/soc-lx2160a/lx2160aqds/platform.mk b/plat/nxp/soc-lx2160a/lx2160aqds/platform.mk
new file mode 100644
index 0000000..226b22b
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2160aqds/platform.mk
@@ -0,0 +1,51 @@
+#
+# Copyright 2018-2020 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# board-specific build parameters
+
+BOOT_MODE ?= flexspi_nor
+BOARD ?= lx2160aqds
+POVDD_ENABLE := no
+NXP_COINED_BB := no
+
+ # DDR Compilation Configs
+NUM_OF_DDRC := 1
+DDRC_NUM_DIMM := 1
+DDRC_NUM_CS := 2
+DDR_ECC_EN := yes
+ #enable address decoding feature
+DDR_ADDR_DEC := yes
+APPLY_MAX_CDD := yes
+
+# DDR Errata
+ERRATA_DDR_A011396 := 1
+ERRATA_DDR_A050450 := 1
+
+ # On-Board Flash Details
+FLASH_TYPE := MT35XU512A
+XSPI_FLASH_SZ := 0x10000000
+NXP_XSPI_NOR_UNIT_SIZE := 0x20000
+BL2_BIN_XSPI_NOR_END_ADDRESS := 0x100000
+# CONFIG_FSPI_ERASE_4K is required to erase 4K sector sizes. This
+# config is enabled for future use cases.
+FSPI_ERASE_4K := 0
+
+# Platform specific features.
+WARM_BOOT := yes
+
+# Adding Platform files build files
+BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\
+ ${BOARD_PATH}/platform.c
+
+SUPPORTED_BOOT_MODE := flexspi_nor \
+ sd \
+ emmc
+
+# Adding platform board build info
+include plat/nxp/common/plat_make_helper/plat_common_def.mk
+
+# Adding SoC build info
+include plat/nxp/soc-lx2160a/soc.mk
diff --git a/plat/nxp/soc-lx2160a/lx2160aqds/platform_def.h b/plat/nxp/soc-lx2160a/lx2160aqds/platform_def.h
new file mode 100644
index 0000000..5fa774e
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2160aqds/platform_def.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include "plat_def.h"
+#include "plat_default_def.h"
+
+#endif
diff --git a/plat/nxp/soc-lx2160a/lx2160aqds/policy.h b/plat/nxp/soc-lx2160a/lx2160aqds/policy.h
new file mode 100644
index 0000000..05d23e2
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2160aqds/policy.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef POLICY_H
+#define POLICY_H
+
+/* Following defines affect the PLATFORM SECURITY POLICY */
+
+/* set this to 0x0 if the platform is not using/responding to ECC errors
+ * set this to 0x1 if ECC is being used (we have to do some init)
+ */
+#define POLICY_USING_ECC 0x0
+
+/* Set this to 0x0 to leave the default SMMU page size in sACR
+ * Set this to 0x1 to change the SMMU page size to 64K
+ */
+#define POLICY_SMMU_PAGESZ_64K 0x1
+
+/*
+ * POLICY_PERF_WRIOP = 0 : No Performance enhancement for WRIOP RN-I
+ * POLICY_PERF_WRIOP = 1 : No Performance enhancement for WRIOP RN-I = 7
+ * POLICY_PERF_WRIOP = 2 : No Performance enhancement for WRIOP RN-I = 23
+ */
+#define POLICY_PERF_WRIOP 0
+
+/*
+ * set this to '1' if the debug clocks need to remain enabled during
+ * system entry to low-power (LPM20) - this should only be necessary
+ * for testing and NEVER set for normal production
+ */
+#define POLICY_DEBUG_ENABLE 0
+
+
+#endif /* POLICY_H */
diff --git a/plat/nxp/soc-lx2160a/lx2160ardb/ddr_init.c b/plat/nxp/soc-lx2160a/lx2160ardb/ddr_init.c
new file mode 100644
index 0000000..8669b1d
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2160ardb/ddr_init.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <ddr.h>
+#include <lib/utils.h>
+#include <load_img.h>
+
+#include "plat_common.h"
+#include <platform_def.h>
+
+#ifdef CONFIG_STATIC_DDR
+const struct ddr_cfg_regs static_1600 = {
+ .cs[0].config = U(0xA8050322),
+ .cs[1].config = U(0x80000322),
+ .cs[0].bnds = U(0x3FF),
+ .cs[1].bnds = U(0x3FF),
+ .sdram_cfg[0] = U(0xE5044000),
+ .sdram_cfg[1] = U(0x401011),
+ .timing_cfg[0] = U(0xFF550018),
+ .timing_cfg[1] = U(0xBAB48C42),
+ .timing_cfg[2] = U(0x48C111),
+ .timing_cfg[3] = U(0x10C1000),
+ .timing_cfg[4] = U(0x2),
+ .timing_cfg[5] = U(0x3401400),
+ .timing_cfg[7] = U(0x13300000),
+ .timing_cfg[8] = U(0x2114600),
+ .sdram_mode[0] = U(0x6010210),
+ .sdram_mode[8] = U(0x500),
+ .sdram_mode[9] = U(0x4240000),
+ .interval = U(0x18600000),
+ .data_init = U(0xDEADBEEF),
+ .zq_cntl = U(0x8A090705),
+};
+
+const struct dimm_params static_dimm = {
+ .rdimm = U(0),
+ .primary_sdram_width = U(64),
+ .ec_sdram_width = U(8),
+ .n_ranks = U(2),
+ .device_width = U(8),
+ .mirrored_dimm = U(1),
+};
+
+/* Sample code using two UDIMM MT18ASF1G72AZ-2G6B1, on each DDR controller */
+unsigned long long board_static_ddr(struct ddr_info *priv)
+{
+ memcpy(&priv->ddr_reg, &static_1600, sizeof(static_1600));
+ memcpy(&priv->dimm, &static_dimm, sizeof(static_dimm));
+ priv->conf.cs_on_dimm[0] = 0x3;
+ ddr_board_options(priv);
+ compute_ddr_phy(priv);
+
+ return ULL(0x400000000);
+}
+
+#elif defined(CONFIG_DDR_NODIMM)
+/*
+ * Sample code to bypass reading SPD. This is a sample, not recommended
+ * for boards with slots. DDR model number: UDIMM MT18ASF1G72AZ-2G6B1.
+ */
+
+const struct dimm_params ddr_raw_timing = {
+ .n_ranks = U(2),
+ .rank_density = U(4294967296u),
+ .capacity = U(8589934592u),
+ .primary_sdram_width = U(64),
+ .ec_sdram_width = U(8),
+ .device_width = U(8),
+ .die_density = U(0x4),
+ .rdimm = U(0),
+ .mirrored_dimm = U(1),
+ .n_row_addr = U(15),
+ .n_col_addr = U(10),
+ .bank_addr_bits = U(0),
+ .bank_group_bits = U(2),
+ .edc_config = U(2),
+ .burst_lengths_bitmask = U(0x0c),
+ .tckmin_x_ps = 750,
+ .tckmax_ps = 1600,
+ .caslat_x = U(0x00FFFC00),
+ .taa_ps = 13750,
+ .trcd_ps = 13750,
+ .trp_ps = 13750,
+ .tras_ps = 32000,
+ .trc_ps = 457500,
+ .twr_ps = 15000,
+ .trfc1_ps = 260000,
+ .trfc2_ps = 160000,
+ .trfc4_ps = 110000,
+ .tfaw_ps = 21000,
+ .trrds_ps = 3000,
+ .trrdl_ps = 4900,
+ .tccdl_ps = 5000,
+ .refresh_rate_ps = U(7800000),
+};
+
+int ddr_get_ddr_params(struct dimm_params *pdimm,
+ struct ddr_conf *conf)
+{
+ static const char dimm_model[] = "Fixed DDR on board";
+
+ conf->dimm_in_use[0] = 1; /* Modify accordingly */
+ memcpy(pdimm, &ddr_raw_timing, sizeof(struct dimm_params));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+
+ /* valid DIMM mask, change accordingly, together with dimm_on_ctlr. */
+ return 0x5;
+}
+#endif /* CONFIG_DDR_NODIMM */
+
+int ddr_board_options(struct ddr_info *priv)
+{
+ struct memctl_opt *popts = &priv->opt;
+ const struct ddr_conf *conf = &priv->conf;
+
+ popts->vref_dimm = U(0x24); /* range 1, 83.4% */
+ popts->rtt_override = 0;
+ popts->rtt_park = U(240);
+ popts->otf_burst_chop_en = 0;
+ popts->burst_length = U(DDR_BL8);
+ popts->trwt_override = U(1);
+ popts->bstopre = U(0); /* auto precharge */
+ popts->addr_hash = 1;
+
+ /* Set ODT impedance on PHY side */
+ switch (conf->cs_on_dimm[1]) {
+ case 0xc: /* Two slots dual rank */
+ case 0x4: /* Two slots single rank, not valid for interleaving */
+ popts->trwt = U(0xf);
+ popts->twrt = U(0x7);
+ popts->trrt = U(0x7);
+ popts->twwt = U(0x7);
+ popts->vref_phy = U(0x6B); /* 83.6% */
+ popts->odt = U(60);
+ popts->phy_tx_impedance = U(28);
+ break;
+ case 0: /* One slot used */
+ default:
+ popts->trwt = U(0x3);
+ popts->twrt = U(0x3);
+ popts->trrt = U(0x3);
+ popts->twwt = U(0x3);
+ popts->vref_phy = U(0x60); /* 75% */
+ popts->odt = U(48);
+ popts->phy_tx_impedance = U(28);
+ break;
+ }
+
+ return 0;
+}
+
+long long init_ddr(void)
+{
+ int spd_addr[] = { 0x51, 0x52, 0x53, 0x54 };
+ struct ddr_info info;
+ struct sysinfo sys;
+ long long dram_size;
+
+ zeromem(&sys, sizeof(sys));
+ if (get_clocks(&sys) != 0) {
+ ERROR("System clocks are not set\n");
+ panic();
+ }
+ debug("platform clock %lu\n", sys.freq_platform);
+ debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
+ debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
+
+ zeromem(&info, sizeof(info));
+
+ /* Set two DDRC. Unused DDRC will be removed automatically. */
+ info.num_ctlrs = NUM_OF_DDRC;
+ info.spd_addr = spd_addr;
+ info.ddr[0] = (void *)NXP_DDR_ADDR;
+ info.ddr[1] = (void *)NXP_DDR2_ADDR;
+ info.phy[0] = (void *)NXP_DDR_PHY1_ADDR;
+ info.phy[1] = (void *)NXP_DDR_PHY2_ADDR;
+ info.clk = get_ddr_freq(&sys, 0);
+ info.img_loadr = load_img;
+ info.phy_gen2_fw_img_buf = PHY_GEN2_FW_IMAGE_BUFFER;
+ if (info.clk == 0) {
+ info.clk = get_ddr_freq(&sys, 1);
+ }
+ info.dimm_on_ctlr = DDRC_NUM_DIMM;
+
+ info.warm_boot_flag = DDR_WRM_BOOT_NT_SUPPORTED;
+
+ dram_size = dram_init(&info
+#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
+ , NXP_CCN_HN_F_0_ADDR
+#endif
+ );
+
+
+ if (dram_size < 0) {
+ ERROR("DDR init failed.\n");
+ }
+
+ return dram_size;
+}
diff --git a/plat/nxp/soc-lx2160a/lx2160ardb/plat_def.h b/plat/nxp/soc-lx2160a/lx2160ardb/plat_def.h
new file mode 100644
index 0000000..02f51e7
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2160ardb/plat_def.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PLAT_DEF_H
+#define PLAT_DEF_H
+
+#include <arch.h>
+#include <cortex_a72.h>
+/* Required without TBBR.
+ * To include the defines for DDR PHY
+ * Images.
+ */
+#include <tbbr_img_def.h>
+
+#include <policy.h>
+#include <soc.h>
+
+#if defined(IMAGE_BL31)
+#define LS_SYS_TIMCTL_BASE 0x2890000
+#define PLAT_LS_NSTIMER_FRAME_ID 0
+#define LS_CONFIG_CNTACR 1
+#endif
+
+#define NXP_SYSCLK_FREQ 100000000
+#define NXP_DDRCLK_FREQ 100000000
+
+/* UART related definition */
+#define NXP_CONSOLE_ADDR NXP_UART_ADDR
+#define NXP_CONSOLE_BAUDRATE 115200
+
+/* Size of cacheable stacks */
+#if defined(IMAGE_BL2)
+#if defined(TRUSTED_BOARD_BOOT)
+#define PLATFORM_STACK_SIZE 0x2000
+#else
+#define PLATFORM_STACK_SIZE 0x1000
+#endif
+#elif defined(IMAGE_BL31)
+#define PLATFORM_STACK_SIZE 0x1000
+#endif
+
+/* SD block buffer */
+#define NXP_SD_BLOCK_BUF_SIZE (0x8000)
+#define NXP_SD_BLOCK_BUF_ADDR (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \
+ - NXP_SD_BLOCK_BUF_SIZE)
+
+#ifdef SD_BOOT
+#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \
+ - NXP_SD_BLOCK_BUF_SIZE)
+#else
+#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
+#endif
+
+/* IO defines as needed by IO driver framework */
+#define MAX_IO_DEVICES 4
+#define MAX_IO_BLOCK_DEVICES 1
+#define MAX_IO_HANDLES 4
+
+#define PHY_GEN2_FW_IMAGE_BUFFER (NXP_OCRAM_ADDR + CSF_HDR_SZ)
+
+/*
+ * FIP image defines - Offset at which FIP Image would be present
+ * Image would include Bl31 , Bl33 and Bl32 (optional)
+ */
+#ifdef POLICY_FUSE_PROVISION
+#define MAX_FIP_DEVICES 3
+#endif
+
+#ifndef MAX_FIP_DEVICES
+#define MAX_FIP_DEVICES 2
+#endif
+
+/*
+ * ID of the secure physical generic timer interrupt used by the BL32.
+ */
+#define BL32_IRQ_SEC_PHY_TIMER 29
+
+#define BL31_WDOG_SEC 89
+
+#define BL31_NS_WDOG_WS1 108
+
+/*
+ * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLAT_LS_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE)
+
+/* SGI 15 and Secure watchdog interrupts assigned to Group 0 */
+#define NXP_IRQ_SEC_SGI_7 15
+
+#define PLAT_LS_G0_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(BL31_NS_WDOG_WS1, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(NXP_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL)
+#endif
diff --git a/plat/nxp/soc-lx2160a/lx2160ardb/platform.c b/plat/nxp/soc-lx2160a/lx2160ardb/platform.c
new file mode 100644
index 0000000..b00adb5
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2160ardb/platform.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <plat_common.h>
+
+#pragma weak board_enable_povdd
+#pragma weak board_disable_povdd
+
+bool board_enable_povdd(void)
+{
+#ifdef CONFIG_POVDD_ENABLE
+ return true;
+#else
+ return false;
+#endif
+}
+
+bool board_disable_povdd(void)
+{
+#ifdef CONFIG_POVDD_ENABLE
+ return true;
+#else
+ return false;
+#endif
+}
diff --git a/plat/nxp/soc-lx2160a/lx2160ardb/platform.mk b/plat/nxp/soc-lx2160a/lx2160ardb/platform.mk
new file mode 100644
index 0000000..ffb5fad
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2160ardb/platform.mk
@@ -0,0 +1,51 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# board-specific build parameters
+
+BOOT_MODE ?= flexspi_nor
+BOARD ?= lx2160ardb
+POVDD_ENABLE := no
+NXP_COINED_BB := no
+
+ # DDR Compilation Configs
+NUM_OF_DDRC := 2
+DDRC_NUM_DIMM := 2
+DDRC_NUM_CS := 4
+DDR_ECC_EN := yes
+ #enable address decoding feature
+DDR_ADDR_DEC := yes
+APPLY_MAX_CDD := yes
+
+# DDR Errata
+ERRATA_DDR_A011396 := 1
+ERRATA_DDR_A050450 := 1
+
+ # On-Board Flash Details
+FLASH_TYPE := MT35XU512A
+XSPI_FLASH_SZ := 0x10000000
+NXP_XSPI_NOR_UNIT_SIZE := 0x20000
+BL2_BIN_XSPI_NOR_END_ADDRESS := 0x100000
+# CONFIG_FSPI_ERASE_4K is required to erase 4K sector sizes. This
+# config is enabled for future use cases.
+FSPI_ERASE_4K := 0
+
+ # Platform specific features.
+WARM_BOOT := no
+
+ # Adding Platform files build files
+BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\
+ ${BOARD_PATH}/platform.c
+
+SUPPORTED_BOOT_MODE := flexspi_nor \
+ sd \
+ emmc
+
+# Adding platform board build info
+include plat/nxp/common/plat_make_helper/plat_common_def.mk
+
+ # Adding SoC build info
+include plat/nxp/soc-lx2160a/soc.mk
diff --git a/plat/nxp/soc-lx2160a/lx2160ardb/platform_def.h b/plat/nxp/soc-lx2160a/lx2160ardb/platform_def.h
new file mode 100644
index 0000000..6660998
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2160ardb/platform_def.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include "plat_def.h"
+#include "plat_default_def.h"
+
+#endif
diff --git a/plat/nxp/soc-lx2160a/lx2160ardb/policy.h b/plat/nxp/soc-lx2160a/lx2160ardb/policy.h
new file mode 100644
index 0000000..19ad6db
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2160ardb/policy.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef POLICY_H
+#define POLICY_H
+
+/* Following defines affect the PLATFORM SECURITY POLICY */
+
+/* set this to 0x0 if the platform is not using/responding to ECC errors
+ * set this to 0x1 if ECC is being used (we have to do some init)
+ */
+#define POLICY_USING_ECC 0x0
+
+/* Set this to 0x0 to leave the default SMMU page size in sACR
+ * Set this to 0x1 to change the SMMU page size to 64K
+ */
+#define POLICY_SMMU_PAGESZ_64K 0x1
+
+/*
+ * POLICY_PERF_WRIOP = 0 : No Performance enhancement for WRIOP RN-I
+ * POLICY_PERF_WRIOP = 1 : No Performance enhancement for WRIOP RN-I = 7
+ * POLICY_PERF_WRIOP = 2 : No Performance enhancement for WRIOP RN-I = 23
+ */
+#define POLICY_PERF_WRIOP 0
+
+/*
+ * set this to '1' if the debug clocks need to remain enabled during
+ * system entry to low-power (LPM20) - this should only be necessary
+ * for testing and NEVER set for normal production
+ */
+#define POLICY_DEBUG_ENABLE 0
+
+
+#endif /* POLICY_H */
diff --git a/plat/nxp/soc-lx2160a/lx2162aqds/ddr_init.c b/plat/nxp/soc-lx2160a/lx2162aqds/ddr_init.c
new file mode 100644
index 0000000..73bcc93
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2162aqds/ddr_init.c
@@ -0,0 +1,354 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <common/debug.h>
+#include <ddr.h>
+#include <lib/utils.h>
+#include <load_img.h>
+
+#include "plat_common.h"
+#include <platform_def.h>
+
+#ifdef CONFIG_STATIC_DDR
+
+const struct ddr_cfg_regs static_3200 = {
+ .cs[0].bnds = U(0x03FFU),
+ .cs[1].bnds = U(0x03FF),
+ .cs[0].config = U(0x80050422),
+ .cs[1].config = U(0x80000422),
+ .cs[2].bnds = U(0x00),
+ .cs[3].bnds = U(0x00),
+ .cs[2].config = U(0x00),
+ .cs[3].config = U(0x00),
+ .timing_cfg[0] = U(0xFFAA0018),
+ .timing_cfg[1] = U(0x646A8844),
+ .timing_cfg[2] = U(0x00058022),
+ .timing_cfg[3] = U(0x13622100),
+ .timing_cfg[4] = U(0x02),
+ .timing_cfg[5] = U(0x07401400),
+ .timing_cfg[7] = U(0x3BB00000),
+ .timing_cfg[8] = U(0x0944AC00),
+ .sdram_cfg[0] = U(0x65044008),
+ .sdram_cfg[1] = U(0x00401011),
+ .sdram_cfg[2] = U(0x00),
+ .sdram_mode[0] = U(0x06010C50),
+ .sdram_mode[1] = U(0x00280400),
+ .sdram_mode[2] = U(0x00),
+ .sdram_mode[3] = U(0x00),
+ .sdram_mode[4] = U(0x00),
+ .sdram_mode[5] = U(0x00),
+ .sdram_mode[6] = U(0x00),
+ .sdram_mode[7] = U(0x00),
+ .sdram_mode[8] = U(0x0500),
+ .sdram_mode[9] = U(0x10240000),
+ .sdram_mode[10] = U(0x00),
+ .sdram_mode[11] = U(0x00),
+ .sdram_mode[12] = U(0x00),
+ .sdram_mode[13] = U(0x00),
+ .sdram_mode[14] = U(0x00),
+ .sdram_mode[15] = U(0x00),
+ .md_cntl = U(0x00),
+ .interval = U(0x30C00000),
+ .data_init = U(0xDEADBEEF),
+ .init_addr = U(0x00),
+ .zq_cntl = U(0x8A090705),
+ .sdram_rcw[0] = U(0x00),
+ .sdram_rcw[1] = U(0x00),
+ .sdram_rcw[2] = U(0x00),
+ .sdram_rcw[3] = U(0x00),
+ .sdram_rcw[4] = U(0x00),
+ .sdram_rcw[5] = U(0x00),
+ .err_disable = U(0x00),
+ .err_int_en = U(0x00),
+};
+
+const struct ddr_cfg_regs static_2900 = {
+ .cs[0].bnds = U(0x03FF),
+ .cs[1].bnds = U(0x03FF),
+ .cs[0].config = U(0x80050422),
+ .cs[1].config = U(0x80000422),
+ .cs[2].bnds = U(0x00),
+ .cs[3].bnds = U(0x00),
+ .cs[2].config = U(0x00),
+ .cs[3].config = U(0x00),
+ .timing_cfg[0] = U(0xFF990018),
+ .timing_cfg[1] = U(0x4F4A4844),
+ .timing_cfg[2] = U(0x0005601F),
+ .timing_cfg[3] = U(0x125F2100),
+ .timing_cfg[4] = U(0x02),
+ .timing_cfg[5] = U(0x07401400),
+ .timing_cfg[7] = U(0x3AA00000),
+ .timing_cfg[8] = U(0x09449B00),
+ .sdram_cfg[0] = U(0x65044008),
+ .sdram_cfg[1] = U(0x00401011),
+ .sdram_cfg[2] = U(0x00),
+ .sdram_mode[0] = U(0x06010C50),
+ .sdram_mode[1] = U(0x00280400),
+ .sdram_mode[2] = U(0x00),
+ .sdram_mode[3] = U(0x00),
+ .sdram_mode[4] = U(0x00),
+ .sdram_mode[5] = U(0x00),
+ .sdram_mode[6] = U(0x00),
+ .sdram_mode[7] = U(0x00),
+ .sdram_mode[8] = U(0x0500),
+ .sdram_mode[9] = U(0x10240000),
+ .sdram_mode[10] = U(0x00),
+ .sdram_mode[11] = U(0x00),
+ .sdram_mode[12] = U(0x00),
+ .sdram_mode[13] = U(0x00),
+ .sdram_mode[14] = U(0x00),
+ .sdram_mode[15] = U(0x00),
+ .md_cntl = U(0x00),
+ .interval = U(0x2C2E0000),
+ .data_init = U(0xDEADBEEF),
+ .init_addr = U(0x00),
+ .zq_cntl = U(0x8A090705),
+ .sdram_rcw[0] = U(0x00),
+ .sdram_rcw[1] = U(0x00),
+ .sdram_rcw[2] = U(0x00),
+ .sdram_rcw[3] = U(0x00),
+ .sdram_rcw[4] = U(0x00),
+ .sdram_rcw[5] = U(0x00),
+ .err_disable = U(0x00),
+ .err_int_en = U(0x00),
+};
+
+const struct ddr_cfg_regs static_2600 = {
+ .cs[0].bnds = U(0x03FF),
+ .cs[1].bnds = U(0x03FF),
+ .cs[0].config = U(0x80050422),
+ .cs[1].config = U(0x80000422),
+ .cs[2].bnds = U(0x00),
+ .cs[3].bnds = U(0x00),
+ .cs[2].config = U(0x00),
+ .cs[3].config = U(0x00),
+ .timing_cfg[0] = U(0xFF880018),
+ .timing_cfg[1] = U(0x2A24F444),
+ .timing_cfg[2] = U(0x007141DC),
+ .timing_cfg[3] = U(0x125B2100),
+ .timing_cfg[4] = U(0x02),
+ .timing_cfg[5] = U(0x06401400),
+ .timing_cfg[7] = U(0x28800000),
+ .timing_cfg[8] = U(0x07338A00),
+ .sdram_cfg[0] = U(0x65044008),
+ .sdram_cfg[1] = U(0x00401011),
+ .sdram_cfg[2] = U(0x00),
+ .sdram_mode[0] = U(0x06010A70),
+ .sdram_mode[1] = U(0x00200400),
+ .sdram_mode[2] = U(0x00),
+ .sdram_mode[3] = U(0x00),
+ .sdram_mode[4] = U(0x00),
+ .sdram_mode[5] = U(0x00),
+ .sdram_mode[6] = U(0x00),
+ .sdram_mode[7] = U(0x00),
+ .sdram_mode[8] = U(0x0500),
+ .sdram_mode[9] = U(0x0C240000),
+ .sdram_mode[10] = U(0x00),
+ .sdram_mode[11] = U(0x00),
+ .sdram_mode[12] = U(0x00),
+ .sdram_mode[13] = U(0x00),
+ .sdram_mode[14] = U(0x00),
+ .sdram_mode[15] = U(0x00),
+ .md_cntl = U(0x00),
+ .interval = U(0x279C0000),
+ .data_init = U(0xDEADBEEF),
+ .init_addr = U(0x00),
+ .zq_cntl = U(0x8A090705),
+ .sdram_rcw[0] = U(0x00),
+ .sdram_rcw[1] = U(0x00),
+ .sdram_rcw[2] = U(0x00),
+ .sdram_rcw[3] = U(0x00),
+ .sdram_rcw[4] = U(0x00),
+ .sdram_rcw[5] = U(0x00),
+ .err_disable = U(0x00),
+ .err_int_en = U(0x00),
+};
+
+const struct dimm_params static_dimm = {
+ .rdimm = 0U,
+ .primary_sdram_width = 64U,
+ .ec_sdram_width = 8U,
+ .n_ranks = 2U,
+ .device_width = 8U,
+ .mirrored_dimm = 1U,
+};
+
+/* Sample code using two UDIMM MT18ASF1G72AZ-2G6B1, on each DDR controller */
+unsigned long long board_static_ddr(struct ddr_info *priv)
+{
+ memcpy(&priv->ddr_reg, &static_2900, sizeof(static_2900));
+ memcpy(&priv->dimm, &static_dimm, sizeof(static_dimm));
+ priv->conf.cs_on_dimm[0] = 0x3;
+ ddr_board_options(priv);
+ compute_ddr_phy(priv);
+
+ return ULL(0x400000000);
+}
+
+#elif defined(CONFIG_DDR_NODIMM)
+/*
+ * Sample code to bypass reading SPD. This is a sample, not recommended
+ * for boards with slots. DDR model number: UDIMM MT18ASF1G72AZ-2G6B1.
+ */
+struct dimm_params ddr_raw_timing = {
+ .n_ranks = 2U,
+ .rank_density = U(0x200000000),
+ .capacity = U(0x400000000),
+ .primary_sdram_width = 64U,
+ .ec_sdram_width = 8U,
+ .device_width = 8U,
+ .die_density = U(0x5),
+ .rdimm = 0U,
+ .mirrored_dimm = 1U,
+ .n_row_addr = 16U,
+ .n_col_addr = 10U,
+ .bank_addr_bits = 0U,
+ .bank_group_bits = 2U,
+ .edc_config = 2U,
+ .burst_lengths_bitmask = U(0x0c),
+ .tckmin_x_ps = 625,
+ .tckmax_ps = 1600,
+ .caslat_x = U(0x15FFFC00),
+ .taa_ps = 13750,
+ .trcd_ps = 13750,
+ .trp_ps = 13750,
+ .tras_ps = 32000,
+ .trc_ps = 457500,
+ .twr_ps = 15000,
+ .trfc1_ps = 350000,
+ .trfc2_ps = 260000,
+ .trfc4_ps = 160000,
+ .tfaw_ps = 21000,
+ .trrds_ps = 2500,
+ .trrdl_ps = 4900,
+ .tccdl_ps = 5000,
+ .refresh_rate_ps = 7800000U,
+};
+
+int ddr_get_ddr_params(struct dimm_params *pdimm,
+ struct ddr_conf *conf)
+{
+ static const char dimm_model[] = "Fixed DDR on board";
+
+ conf->dimm_in_use[0] = 1; /* Modify accordingly */
+ memcpy(pdimm, &ddr_raw_timing, sizeof(struct dimm_params));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+
+ /* valid DIMM mask, change accordingly, together with dimm_on_ctlr. */
+ return 0x5;
+}
+#endif /* CONFIG_DDR_NODIMM */
+
+int ddr_board_options(struct ddr_info *priv)
+{
+ struct memctl_opt *popts = &priv->opt;
+ const struct ddr_conf *conf = &priv->conf;
+
+ popts->vref_dimm = U(0x19); /* range 1, 83.4% */
+ popts->rtt_override = 1U;
+ popts->rtt_override_value = 0x5U; /* RTT being used as 60 ohm */
+ popts->rtt_park = 120U;
+ popts->otf_burst_chop_en = 0;
+ popts->burst_length = DDR_BL8;
+ popts->trwt_override = 1U;
+ popts->bstopre = 0U; /* auto precharge */
+ popts->addr_hash = 1;
+
+ /* Set ODT impedance on PHY side */
+ switch (conf->cs_on_dimm[1]) {
+ case 0xc: /* Two slots dual rank */
+ case 0x4: /* Two slots single rank, not valid for interleaving */
+ popts->trwt = U(0xf);
+ popts->twrt = U(0x7);
+ popts->trrt = U(0x7);
+ popts->twwt = U(0x7);
+ popts->vref_phy = U(0x6B); /* 83.6% */
+ popts->odt = 60U;
+ popts->phy_tx_impedance = 28U;
+ break;
+ case 0: /* Ont slot used */
+ default:
+ popts->trwt = U(0x3);
+ popts->twrt = U(0x3);
+ popts->trrt = U(0x3);
+ popts->twwt = U(0x3);
+ popts->vref_phy = U(0x5D); /* 72% */
+ popts->odt = 60U;
+ popts->phy_tx_impedance = 28U;
+ break;
+ }
+
+ return 0;
+}
+
+#ifdef NXP_WARM_BOOT
+long long init_ddr(uint32_t wrm_bt_flg)
+#else
+long long init_ddr(void)
+#endif
+{
+ int spd_addr[] = { 0x51, 0x52, 0x53, 0x54 };
+ struct ddr_info info;
+ struct sysinfo sys;
+ long long dram_size;
+
+ zeromem(&sys, sizeof(sys));
+ if (get_clocks(&sys) != 0) {
+ ERROR("System clocks are not set\n");
+ panic();
+ }
+ debug("platform clock %lu\n", sys.freq_platform);
+ debug("DDR PLL1 %lu\n", sys.freq_ddr_pll0);
+ debug("DDR PLL2 %lu\n", sys.freq_ddr_pll1);
+
+ zeromem(&info, sizeof(info));
+
+ /* Set two DDRC. Unused DDRC will be removed automatically. */
+ info.num_ctlrs = NUM_OF_DDRC;
+ info.spd_addr = spd_addr;
+ info.ddr[0] = (void *)NXP_DDR_ADDR;
+ info.ddr[1] = (void *)NXP_DDR2_ADDR;
+ info.phy[0] = (void *)NXP_DDR_PHY1_ADDR;
+ info.phy[1] = (void *)NXP_DDR_PHY2_ADDR;
+ info.clk = get_ddr_freq(&sys, 0);
+ info.img_loadr = load_img;
+ info.phy_gen2_fw_img_buf = PHY_GEN2_FW_IMAGE_BUFFER;
+ if (info.clk == 0) {
+ info.clk = get_ddr_freq(&sys, 1);
+ }
+ info.dimm_on_ctlr = DDRC_NUM_DIMM;
+
+ info.warm_boot_flag = DDR_WRM_BOOT_NT_SUPPORTED;
+#ifdef NXP_WARM_BOOT
+ if (wrm_bt_flg != 0) {
+ info.warm_boot_flag = DDR_WARM_BOOT;
+ } else {
+ info.warm_boot_flag = DDR_COLD_BOOT;
+ }
+#endif
+
+ dram_size = dram_init(&info
+#if defined(NXP_HAS_CCN504) || defined(NXP_HAS_CCN508)
+ , NXP_CCN_HN_F_0_ADDR
+#endif
+ );
+
+
+ if (dram_size < 0) {
+ ERROR("DDR init failed.\n");
+ }
+
+ return dram_size;
+}
diff --git a/plat/nxp/soc-lx2160a/lx2162aqds/plat_def.h b/plat/nxp/soc-lx2160a/lx2162aqds/plat_def.h
new file mode 100644
index 0000000..de2d244
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2162aqds/plat_def.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PLAT_DEF_H
+#define PLAT_DEF_H
+
+#include <arch.h>
+#include <cortex_a72.h>
+/* Required without TBBR.
+ * To include the defines for DDR PHY
+ * Images.
+ */
+#include <tbbr_img_def.h>
+
+#include <policy.h>
+#include <soc.h>
+
+#if defined(IMAGE_BL31)
+#define LS_SYS_TIMCTL_BASE 0x2890000
+#define PLAT_LS_NSTIMER_FRAME_ID 0
+#define LS_CONFIG_CNTACR 1
+#endif
+
+#define NXP_SYSCLK_FREQ 100000000
+#define NXP_DDRCLK_FREQ 100000000
+
+/* UART related definition */
+#define NXP_CONSOLE_ADDR NXP_UART_ADDR
+#define NXP_CONSOLE_BAUDRATE 115200
+
+/* Size of cacheable stacks */
+#if defined(IMAGE_BL2)
+#if defined(TRUSTED_BOARD_BOOT)
+#define PLATFORM_STACK_SIZE 0x2000
+#else
+#define PLATFORM_STACK_SIZE 0x1000
+#endif
+#elif defined(IMAGE_BL31)
+#define PLATFORM_STACK_SIZE 0x1000
+#endif
+
+/* SD block buffer */
+#define NXP_SD_BLOCK_BUF_SIZE (0x8000)
+#define NXP_SD_BLOCK_BUF_ADDR (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \
+ - NXP_SD_BLOCK_BUF_SIZE)
+
+#ifdef SD_BOOT
+#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE \
+ - NXP_SD_BLOCK_BUF_SIZE)
+#else
+#define BL2_LIMIT (NXP_OCRAM_ADDR + NXP_OCRAM_SIZE)
+#endif
+
+/* IO defines as needed by IO driver framework */
+#define MAX_IO_DEVICES 4
+#define MAX_IO_BLOCK_DEVICES 1
+#define MAX_IO_HANDLES 4
+
+#define PHY_GEN2_FW_IMAGE_BUFFER (NXP_OCRAM_ADDR + CSF_HDR_SZ)
+
+/*
+ * FIP image defines - Offset at which FIP Image would be present
+ * Image would include Bl31 , Bl33 and Bl32 (optional)
+ */
+#ifdef POLICY_FUSE_PROVISION
+#define MAX_FIP_DEVICES 3
+#endif
+
+#ifndef MAX_FIP_DEVICES
+#define MAX_FIP_DEVICES 2
+#endif
+
+/*
+ * ID of the secure physical generic timer interrupt used by the BL32.
+ */
+#define BL32_IRQ_SEC_PHY_TIMER 29
+
+#define BL31_WDOG_SEC 89
+
+#define BL31_NS_WDOG_WS1 108
+
+/*
+ * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLAT_LS_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(BL32_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE)
+
+/* SGI 15 and Secure watchdog interrupts assigned to Group 0 */
+#define NXP_IRQ_SEC_SGI_7 15
+
+#define PLAT_LS_G0_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(BL31_WDOG_SEC, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(BL31_NS_WDOG_WS1, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(NXP_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL)
+#endif
diff --git a/plat/nxp/soc-lx2160a/lx2162aqds/platform.c b/plat/nxp/soc-lx2160a/lx2162aqds/platform.c
new file mode 100644
index 0000000..7622cf0
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2162aqds/platform.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <plat_common.h>
+
+#pragma weak board_enable_povdd
+#pragma weak board_disable_povdd
+
+bool board_enable_povdd(void)
+{
+#ifdef CONFIG_POVDD_ENABLE
+ return true;
+#else
+ return false;
+#endif
+}
+
+bool board_disable_povdd(void)
+{
+#ifdef CONFIG_POVDD_ENABLE
+ return true;
+#else
+ return false;
+#endif
+}
diff --git a/plat/nxp/soc-lx2160a/lx2162aqds/platform.mk b/plat/nxp/soc-lx2160a/lx2162aqds/platform.mk
new file mode 100644
index 0000000..2b4712c
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2162aqds/platform.mk
@@ -0,0 +1,52 @@
+#
+# Copyright 2018-2020 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# board-specific build parameters
+
+BOOT_MODE ?= flexspi_nor
+BOARD ?= lx2162aqds
+POVDD_ENABLE := no
+NXP_COINED_BB := no
+
+ # DDR Compilation Configs
+NUM_OF_DDRC := 1
+DDRC_NUM_DIMM := 1
+DDRC_NUM_CS := 2
+DDR_ECC_EN := yes
+ #enable address decoding feature
+DDR_ADDR_DEC := yes
+APPLY_MAX_CDD := yes
+
+# DDR Errata
+ERRATA_DDR_A011396 := 1
+ERRATA_DDR_A050450 := 1
+
+
+# On-Board Flash Details
+FLASH_TYPE := MT35XU512A
+XSPI_FLASH_SZ := 0x10000000
+NXP_XSPI_NOR_UNIT_SIZE := 0x20000
+BL2_BIN_XSPI_NOR_END_ADDRESS := 0x100000
+# CONFIG_FSPI_ERASE_4K is required to erase 4K sector sizes. This
+# config is enabled for future use cases.
+FSPI_ERASE_4K := 0
+
+# Platform specific features.
+WARM_BOOT := yes
+
+# Adding Platform files build files
+BL2_SOURCES += ${BOARD_PATH}/ddr_init.c\
+ ${BOARD_PATH}/platform.c
+
+SUPPORTED_BOOT_MODE := flexspi_nor \
+ sd \
+ emmc
+
+# Adding platform board build info
+include plat/nxp/common/plat_make_helper/plat_common_def.mk
+
+# Adding SoC build info
+include plat/nxp/soc-lx2160a/soc.mk
diff --git a/plat/nxp/soc-lx2160a/lx2162aqds/platform_def.h b/plat/nxp/soc-lx2160a/lx2162aqds/platform_def.h
new file mode 100644
index 0000000..5fa774e
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2162aqds/platform_def.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include "plat_def.h"
+#include "plat_default_def.h"
+
+#endif
diff --git a/plat/nxp/soc-lx2160a/lx2162aqds/policy.h b/plat/nxp/soc-lx2160a/lx2162aqds/policy.h
new file mode 100644
index 0000000..1095f38
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/lx2162aqds/policy.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2018-2020 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef POLICY_H
+#define POLICY_H
+
+/* Following defines affect the PLATFORM SECURITY POLICY */
+
+/* set this to 0x0 if the platform is not using/responding to ECC errors
+ * set this to 0x1 if ECC is being used (we have to do some init)
+ */
+#define POLICY_USING_ECC 0x0
+
+/* Set this to 0x0 to leave the default SMMU page size in sACR
+ * Set this to 0x1 to change the SMMU page size to 64K
+ */
+#define POLICY_SMMU_PAGESZ_64K 0x1
+
+/*
+ * POLICY_PERF_WRIOP = 0 : No Performance enhancement for WRIOP RN-I
+ * POLICY_PERF_WRIOP = 1 : No Performance enhancement for WRIOP RN-I = 7
+ * POLICY_PERF_WRIOP = 2 : No Performance enhancement for WRIOP RN-I = 23
+ */
+#define POLICY_PERF_WRIOP 0
+
+/*
+ * set this to '1' if the debug clocks need to remain enabled during
+ * system entry to low-power (LPM20) - this should only be necessary
+ * for testing and NEVER set for normal production
+ */
+#define POLICY_DEBUG_ENABLE 0
+
+
+#endif /* POLICY_H */
diff --git a/plat/nxp/soc-lx2160a/soc.c b/plat/nxp/soc-lx2160a/soc.c
new file mode 100644
index 0000000..2209fda
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/soc.c
@@ -0,0 +1,509 @@
+/*
+ * Copyright 2018-2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <assert.h>
+
+#include <arch.h>
+#include <bl31/interrupt_mgmt.h>
+#include <caam.h>
+#include <cassert.h>
+#include <ccn.h>
+#include <common/debug.h>
+#include <dcfg.h>
+#ifdef I2C_INIT
+#include <i2c.h>
+#endif
+#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <ls_interconnect.h>
+#ifdef POLICY_FUSE_PROVISION
+#include <nxp_gpio.h>
+#endif
+#if TRUSTED_BOARD_BOOT
+#include <nxp_smmu.h>
+#endif
+#include <nxp_timer.h>
+#include <plat_console.h>
+#include <plat_gic.h>
+#include <plat_tzc400.h>
+#include <pmu.h>
+#if defined(NXP_SFP_ENABLED)
+#include <sfp.h>
+#endif
+
+#include <errata.h>
+#include <ls_interrupt_mgmt.h>
+#include "plat_common.h"
+#ifdef NXP_NV_SW_MAINT_LAST_EXEC_DATA
+#include <plat_nv_storage.h>
+#endif
+#ifdef NXP_WARM_BOOT
+#include <plat_warm_rst.h>
+#endif
+#include "platform_def.h"
+#include "soc.h"
+
+static struct soc_type soc_list[] = {
+ SOC_ENTRY(LX2160A, LX2160A, 8, 2),
+ SOC_ENTRY(LX2080A, LX2080A, 8, 1),
+ SOC_ENTRY(LX2120A, LX2120A, 6, 2),
+};
+
+static dcfg_init_info_t dcfg_init_data = {
+ .g_nxp_dcfg_addr = NXP_DCFG_ADDR,
+ .nxp_sysclk_freq = NXP_SYSCLK_FREQ,
+ .nxp_ddrclk_freq = NXP_DDRCLK_FREQ,
+ .nxp_plat_clk_divider = NXP_PLATFORM_CLK_DIVIDER,
+ };
+static const unsigned char master_to_6rn_id_map[] = {
+ PLAT_6CLUSTER_TO_CCN_ID_MAP
+};
+
+static const unsigned char master_to_rn_id_map[] = {
+ PLAT_CLUSTER_TO_CCN_ID_MAP
+};
+
+CASSERT(ARRAY_SIZE(master_to_rn_id_map) == NUMBER_OF_CLUSTERS,
+ assert_invalid_cluster_count_for_ccn_variant);
+
+static const ccn_desc_t plat_six_cluster_ccn_desc = {
+ .periphbase = NXP_CCN_ADDR,
+ .num_masters = ARRAY_SIZE(master_to_6rn_id_map),
+ .master_to_rn_id_map = master_to_6rn_id_map
+};
+
+static const ccn_desc_t plat_ccn_desc = {
+ .periphbase = NXP_CCN_ADDR,
+ .num_masters = ARRAY_SIZE(master_to_rn_id_map),
+ .master_to_rn_id_map = master_to_rn_id_map
+};
+
+/******************************************************************************
+ * Function returns the base counter frequency
+ * after reading the first entry at CNTFID0 (0x20 offset).
+ *
+ * Function is used by:
+ * 1. ARM common code for PSCI management.
+ * 2. ARM Generic Timer init.
+ *
+ *****************************************************************************/
+unsigned int plat_get_syscnt_freq2(void)
+{
+ unsigned int counter_base_frequency;
+ /*
+ * Below register specifies the base frequency of the system counter.
+ * As per NXP Board Manuals:
+ * The system counter always works with SYS_REF_CLK/4 frequency clock.
+ *
+ *
+ */
+ counter_base_frequency = mmio_read_32(NXP_TIMER_ADDR + CNTFID_OFF);
+
+ return counter_base_frequency;
+}
+
+#ifdef IMAGE_BL2
+
+#ifdef POLICY_FUSE_PROVISION
+static gpio_init_info_t gpio_init_data = {
+ .gpio1_base_addr = NXP_GPIO1_ADDR,
+ .gpio2_base_addr = NXP_GPIO2_ADDR,
+ .gpio3_base_addr = NXP_GPIO3_ADDR,
+ .gpio4_base_addr = NXP_GPIO4_ADDR,
+};
+#endif
+
+static void soc_interconnect_config(void)
+{
+ unsigned long long val = 0x0U;
+ uint8_t num_clusters, cores_per_cluster;
+
+ get_cluster_info(soc_list, ARRAY_SIZE(soc_list),
+ &num_clusters, &cores_per_cluster);
+
+ if (num_clusters == 6U) {
+ ccn_init(&plat_six_cluster_ccn_desc);
+ } else {
+ ccn_init(&plat_ccn_desc);
+ }
+
+ /*
+ * Enable Interconnect coherency for the primary CPU's cluster.
+ */
+ plat_ls_interconnect_enter_coherency(num_clusters);
+
+ val = ccn_read_node_reg(NODE_TYPE_HNI, 13, PCIeRC_RN_I_NODE_ID_OFFSET);
+ val |= (1 << 17);
+ ccn_write_node_reg(NODE_TYPE_HNI, 13, PCIeRC_RN_I_NODE_ID_OFFSET, val);
+
+ /* PCIe is Connected to RN-I 17 which is connected to HN-I 13. */
+ val = ccn_read_node_reg(NODE_TYPE_HNI, 30, PCIeRC_RN_I_NODE_ID_OFFSET);
+ val |= (1 << 17);
+ ccn_write_node_reg(NODE_TYPE_HNI, 30, PCIeRC_RN_I_NODE_ID_OFFSET, val);
+
+ val = ccn_read_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET);
+ val |= SERIALIZE_DEV_nGnRnE_WRITES;
+ ccn_write_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET, val);
+
+ val = ccn_read_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET);
+ val &= ~(ENABLE_RESERVE_BIT53);
+ val |= SERIALIZE_DEV_nGnRnE_WRITES;
+ ccn_write_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET, val);
+
+ val = ccn_read_node_reg(NODE_TYPE_HNI, 13, PoS_CONTROL_REG_OFFSET);
+ val &= ~(HNI_POS_EN);
+ ccn_write_node_reg(NODE_TYPE_HNI, 13, PoS_CONTROL_REG_OFFSET, val);
+
+ val = ccn_read_node_reg(NODE_TYPE_HNI, 30, PoS_CONTROL_REG_OFFSET);
+ val &= ~(HNI_POS_EN);
+ ccn_write_node_reg(NODE_TYPE_HNI, 30, PoS_CONTROL_REG_OFFSET, val);
+
+ val = ccn_read_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET);
+ val &= ~(POS_EARLY_WR_COMP_EN);
+ ccn_write_node_reg(NODE_TYPE_HNI, 13, SA_AUX_CTRL_REG_OFFSET, val);
+
+ val = ccn_read_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET);
+ val &= ~(POS_EARLY_WR_COMP_EN);
+ ccn_write_node_reg(NODE_TYPE_HNI, 30, SA_AUX_CTRL_REG_OFFSET, val);
+
+#if POLICY_PERF_WRIOP
+ uint16_t wriop_rni = 0U;
+
+ if (POLICY_PERF_WRIOP == 1) {
+ wriop_rni = 7U;
+ } else if (POLICY_PERF_WRIOP == 2) {
+ wriop_rni = 23U;
+ } else {
+ ERROR("Incorrect WRIOP selected.\n");
+ panic();
+ }
+
+ val = ccn_read_node_reg(NODE_TYPE_RNI, wriop_rni,
+ SA_AUX_CTRL_REG_OFFSET);
+ val |= ENABLE_WUO;
+ ccn_write_node_reg(NODE_TYPE_HNI, wriop_rni, SA_AUX_CTRL_REG_OFFSET,
+ val);
+#else
+ val = ccn_read_node_reg(NODE_TYPE_RNI, 17, SA_AUX_CTRL_REG_OFFSET);
+ val |= ENABLE_WUO;
+ ccn_write_node_reg(NODE_TYPE_RNI, 17, SA_AUX_CTRL_REG_OFFSET, val);
+#endif
+}
+
+
+void soc_preload_setup(void)
+{
+ dram_regions_info_t *info_dram_regions = get_dram_regions_info();
+#if defined(NXP_WARM_BOOT)
+ bool warm_reset = is_warm_boot();
+#endif
+ info_dram_regions->total_dram_size =
+#if defined(NXP_WARM_BOOT)
+ init_ddr(warm_reset);
+#else
+ init_ddr();
+#endif
+}
+
+/*******************************************************************************
+ * This function implements soc specific erratas
+ * This is called before DDR is initialized or MMU is enabled
+ ******************************************************************************/
+void soc_early_init(void)
+{
+ dcfg_init(&dcfg_init_data);
+#ifdef POLICY_FUSE_PROVISION
+ gpio_init(&gpio_init_data);
+ sec_init(NXP_CAAM_ADDR);
+#endif
+#if LOG_LEVEL > 0
+ /* Initialize the console to provide early debug support */
+ plat_console_init(NXP_CONSOLE_ADDR,
+ NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
+#endif
+
+ enable_timer_base_to_cluster(NXP_PMU_ADDR);
+ soc_interconnect_config();
+
+ enum boot_device dev = get_boot_dev();
+ /* Mark the buffer for SD in OCRAM as non secure.
+ * The buffer is assumed to be at end of OCRAM for
+ * the logic below to calculate TZPC programming
+ */
+ if (dev == BOOT_DEVICE_EMMC || dev == BOOT_DEVICE_SDHC2_EMMC) {
+ /* Calculate the region in OCRAM which is secure
+ * The buffer for SD needs to be marked non-secure
+ * to allow SD to do DMA operations on it
+ */
+ uint32_t secure_region = (NXP_OCRAM_SIZE
+ - NXP_SD_BLOCK_BUF_SIZE);
+ uint32_t mask = secure_region/TZPC_BLOCK_SIZE;
+
+ mmio_write_32(NXP_OCRAM_TZPC_ADDR, mask);
+
+ /* Add the entry for buffer in MMU Table */
+ mmap_add_region(NXP_SD_BLOCK_BUF_ADDR, NXP_SD_BLOCK_BUF_ADDR,
+ NXP_SD_BLOCK_BUF_SIZE,
+ MT_DEVICE | MT_RW | MT_NS);
+ }
+
+ soc_errata();
+
+#if (TRUSTED_BOARD_BOOT) || defined(POLICY_FUSE_PROVISION)
+ sfp_init(NXP_SFP_ADDR);
+#endif
+
+#if TRUSTED_BOARD_BOOT
+ uint32_t mode;
+
+ /* For secure boot disable SMMU.
+ * Later when platform security policy comes in picture,
+ * this might get modified based on the policy
+ */
+ if (check_boot_mode_secure(&mode) == true) {
+ bypass_smmu(NXP_SMMU_ADDR);
+ }
+
+ /* For Mbedtls currently crypto is not supported via CAAM
+ * enable it when that support is there. In tbbr.mk
+ * the CAAM_INTEG is set as 0.
+ */
+
+#ifndef MBEDTLS_X509
+ /* Initialize the crypto accelerator if enabled */
+ if (is_sec_enabled() == false)
+ INFO("SEC is disabled.\n");
+ else
+ sec_init(NXP_CAAM_ADDR);
+#endif
+#endif
+
+ /*
+ * Initialize system level generic timer for Layerscape Socs.
+ */
+ delay_timer_init(NXP_TIMER_ADDR);
+ i2c_init(NXP_I2C_ADDR);
+}
+
+void soc_bl2_prepare_exit(void)
+{
+#if defined(NXP_SFP_ENABLED) && defined(DISABLE_FUSE_WRITE)
+ set_sfp_wr_disable();
+#endif
+}
+
+/*****************************************************************************
+ * This function returns the boot device based on RCW_SRC
+ ****************************************************************************/
+enum boot_device get_boot_dev(void)
+{
+ enum boot_device src = BOOT_DEVICE_NONE;
+ uint32_t porsr1;
+ uint32_t rcw_src;
+
+ porsr1 = read_reg_porsr1();
+
+ rcw_src = (porsr1 & PORSR1_RCW_MASK) >> PORSR1_RCW_SHIFT;
+
+ switch (rcw_src) {
+ case FLEXSPI_NOR:
+ src = BOOT_DEVICE_FLEXSPI_NOR;
+ INFO("RCW BOOT SRC is FLEXSPI NOR\n");
+ break;
+ case FLEXSPI_NAND2K_VAL:
+ case FLEXSPI_NAND4K_VAL:
+ INFO("RCW BOOT SRC is FLEXSPI NAND\n");
+ src = BOOT_DEVICE_FLEXSPI_NAND;
+ break;
+ case SDHC1_VAL:
+ src = BOOT_DEVICE_EMMC;
+ INFO("RCW BOOT SRC is SD\n");
+ break;
+ case SDHC2_VAL:
+ src = BOOT_DEVICE_SDHC2_EMMC;
+ INFO("RCW BOOT SRC is EMMC\n");
+ break;
+ default:
+ break;
+ }
+
+ return src;
+}
+
+
+void soc_mem_access(void)
+{
+ const devdisr5_info_t *devdisr5_info = get_devdisr5_info();
+ dram_regions_info_t *info_dram_regions = get_dram_regions_info();
+ struct tzc400_reg tzc400_reg_list[MAX_NUM_TZC_REGION];
+ int dram_idx, index = 0U;
+
+ for (dram_idx = 0U; dram_idx < info_dram_regions->num_dram_regions;
+ dram_idx++) {
+ if (info_dram_regions->region[dram_idx].size == 0) {
+ ERROR("DDR init failure, or");
+ ERROR("DRAM regions not populated correctly.\n");
+ break;
+ }
+
+ index = populate_tzc400_reg_list(tzc400_reg_list,
+ dram_idx, index,
+ info_dram_regions->region[dram_idx].addr,
+ info_dram_regions->region[dram_idx].size,
+ NXP_SECURE_DRAM_SIZE, NXP_SP_SHRD_DRAM_SIZE);
+ }
+
+ if (devdisr5_info->ddrc1_present != 0) {
+ INFO("DDR Controller 1.\n");
+ mem_access_setup(NXP_TZC_ADDR, index,
+ tzc400_reg_list);
+ mem_access_setup(NXP_TZC3_ADDR, index,
+ tzc400_reg_list);
+ }
+ if (devdisr5_info->ddrc2_present != 0) {
+ INFO("DDR Controller 2.\n");
+ mem_access_setup(NXP_TZC2_ADDR, index,
+ tzc400_reg_list);
+ mem_access_setup(NXP_TZC4_ADDR, index,
+ tzc400_reg_list);
+ }
+}
+
+#else
+const unsigned char _power_domain_tree_desc[] = {1, 8, 2, 2, 2, 2, 2, 2, 2, 2};
+
+CASSERT(NUMBER_OF_CLUSTERS && NUMBER_OF_CLUSTERS <= 256,
+ assert_invalid_lx2160a_cluster_count);
+
+/******************************************************************************
+ * This function returns the SoC topology
+ ****************************************************************************/
+
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+
+ return _power_domain_tree_desc;
+}
+
+/*******************************************************************************
+ * This function returns the core count within the cluster corresponding to
+ * `mpidr`.
+ ******************************************************************************/
+unsigned int plat_ls_get_cluster_core_count(u_register_t mpidr)
+{
+ return CORES_PER_CLUSTER;
+}
+
+
+void soc_early_platform_setup2(void)
+{
+ dcfg_init(&dcfg_init_data);
+ /*
+ * Initialize system level generic timer for Socs
+ */
+ delay_timer_init(NXP_TIMER_ADDR);
+
+#if LOG_LEVEL > 0
+ /* Initialize the console to provide early debug support */
+ plat_console_init(NXP_CONSOLE_ADDR,
+ NXP_UART_CLK_DIVIDER, NXP_CONSOLE_BAUDRATE);
+#endif
+}
+
+void soc_platform_setup(void)
+{
+ /* Initialize the GIC driver, cpu and distributor interfaces */
+ static uintptr_t target_mask_array[PLATFORM_CORE_COUNT];
+ static interrupt_prop_t ls_interrupt_props[] = {
+ PLAT_LS_G1S_IRQ_PROPS(INTR_GROUP1S),
+ PLAT_LS_G0_IRQ_PROPS(INTR_GROUP0)
+ };
+
+ plat_ls_gic_driver_init(NXP_GICD_ADDR, NXP_GICR_ADDR,
+ PLATFORM_CORE_COUNT,
+ ls_interrupt_props,
+ ARRAY_SIZE(ls_interrupt_props),
+ target_mask_array,
+ plat_core_pos);
+
+ plat_ls_gic_init();
+ enable_init_timer();
+#ifdef LS_SYS_TIMCTL_BASE
+ ls_configure_sys_timer(LS_SYS_TIMCTL_BASE,
+ LS_CONFIG_CNTACR,
+ PLAT_LS_NSTIMER_FRAME_ID);
+#endif
+}
+
+/*******************************************************************************
+ * This function initializes the soc from the BL31 module
+ ******************************************************************************/
+void soc_init(void)
+{
+ uint8_t num_clusters, cores_per_cluster;
+
+ get_cluster_info(soc_list, ARRAY_SIZE(soc_list),
+ &num_clusters, &cores_per_cluster);
+
+ /* low-level init of the soc */
+ soc_init_start();
+ soc_init_percpu();
+ _init_global_data();
+ _initialize_psci();
+
+ if (ccn_get_part0_id(NXP_CCN_ADDR) != CCN_508_PART0_ID) {
+ ERROR("Unrecognized CCN variant detected.");
+ ERROR("Only CCN-508 is supported\n");
+ panic();
+ }
+
+ if (num_clusters == 6U) {
+ ccn_init(&plat_six_cluster_ccn_desc);
+ } else {
+ ccn_init(&plat_ccn_desc);
+ }
+
+ plat_ls_interconnect_enter_coherency(num_clusters);
+
+ /* Set platform security policies */
+ _set_platform_security();
+
+ /* make sure any parallel init tasks are finished */
+ soc_init_finish();
+
+ /* Initialize the crypto accelerator if enabled */
+ if (is_sec_enabled() == false) {
+ INFO("SEC is disabled.\n");
+ } else {
+ sec_init(NXP_CAAM_ADDR);
+ }
+
+}
+
+#ifdef NXP_WDOG_RESTART
+static uint64_t wdog_interrupt_handler(uint32_t id, uint32_t flags,
+ void *handle, void *cookie)
+{
+ uint8_t data = WDOG_RESET_FLAG;
+
+ wr_nv_app_data(WDT_RESET_FLAG_OFFSET,
+ (uint8_t *)&data, sizeof(data));
+
+ mmio_write_32(NXP_RST_ADDR + RSTCNTL_OFFSET, SW_RST_REQ_INIT);
+
+ return 0;
+}
+#endif
+
+void soc_runtime_setup(void)
+{
+
+#ifdef NXP_WDOG_RESTART
+ request_intr_type_el3(BL31_NS_WDOG_WS1, wdog_interrupt_handler);
+#endif
+}
+#endif
diff --git a/plat/nxp/soc-lx2160a/soc.def b/plat/nxp/soc-lx2160a/soc.def
new file mode 100644
index 0000000..24d1d13
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/soc.def
@@ -0,0 +1,111 @@
+#
+# Copyright (c) 2015, 2016 Freescale Semiconductor, Inc.
+# Copyright 2017-2020 NXP Semiconductors
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+#------------------------------------------------------------------------------
+#
+# This file contains the basic architecture definitions that drive the build
+#
+# -----------------------------------------------------------------------------
+
+CORE_TYPE := a72
+
+CACHE_LINE := 6
+
+# set to GIC400 or GIC500
+GIC := GIC500
+
+# set to CCI400 or CCN504 or CCN508
+INTERCONNECT := CCN508
+
+# indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
+CHASSIS := 3_2
+
+# TZC IP Details TZC used is TZC380 or TZC400
+TZC_ID := TZC400
+
+# CONSOLE Details available is NS16550 or PL011
+CONSOLE := PL011
+
+# Select the DDR PHY generation to be used
+PLAT_DDR_PHY := PHY_GEN2
+
+PHYS_SYS := 64
+
+# Area of OCRAM reserved by ROM code
+NXP_ROM_RSVD := 0xa000
+
+# Max Size of CSF header. Required to define BL2 TEXT LIMIT in soc.def
+# Input to CST create_hdr_esbc tool
+CSF_HDR_SZ := 0x3000
+
+NXP_SFP_VER := 3_4
+
+# In IMAGE_BL2, compile time flag for handling Cache coherency
+# with CAAM for BL2 running from OCRAM
+SEC_MEM_NON_COHERENT := yes
+
+# Defining the endianness for NXP ESDHC
+NXP_ESDHC_ENDIANNESS := LE
+
+# Defining the endianness for NXP SFP
+NXP_SFP_ENDIANNESS := LE
+
+# Defining the endianness for NXP GPIO
+NXP_GPIO_ENDIANNESS := LE
+
+# Defining the endianness for NXP SNVS
+NXP_SNVS_ENDIANNESS := LE
+
+# Defining the endianness for NXP CCSR GUR register
+NXP_GUR_ENDIANNESS := LE
+
+# Defining the endianness for NXP FSPI register
+NXP_FSPI_ENDIANNESS := LE
+
+# Defining the endianness for NXP SEC
+NXP_SEC_ENDIANNESS := LE
+
+# Defining the endianness for NXP DDR
+NXP_DDR_ENDIANNESS := LE
+
+NXP_DDR_INTLV_256B := 1
+
+# OCRAM MAP for BL2
+# Before BL2
+# 0x18000000 - 0x18009fff -> Used by ROM code
+# 0x1800a000 - 0x1800dfff -> CSF header for BL2
+# (The above area i.e 0x18000000 - 0x1800dfff is available
+# for DDR PHY images scratch pad region during BL2 run time)
+# For FlexSPI boot
+# 0x1800e000 - 0x18040000 -> Reserved for BL2 binary
+# For SD boot
+# 0x1800e000 - 0x18030000 -> Reserved for BL2 binary
+# 0x18030000 - 0x18040000 -> Reserved for SD buffer
+OCRAM_START_ADDR := 0x18000000
+OCRAM_SIZE := 0x40000
+
+# Location of BL2 on OCRAM
+BL2_BASE_ADDR := $(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) + $(CSF_HDR_SZ) )))
+# Covert to HEX to be used by create_pbl.mk
+BL2_BASE := $(shell echo "0x"$$(echo "obase=16; ${BL2_BASE_ADDR}" | bc))
+
+# BL2_HDR_LOC is at (OCRAM_ADDR + NXP_ROM_RSVD)
+# This value BL2_HDR_LOC + CSF_HDR_SZ should not overalp with BL2_BASE
+BL2_HDR_LOC_HDR ?= $(shell echo $$(( $(OCRAM_START_ADDR) + $(NXP_ROM_RSVD) )))
+# Covert to HEX to be used by create_pbl.mk
+BL2_HDR_LOC := $$(echo "obase=16; ${BL2_HDR_LOC_HDR}" | bc)
+
+# SoC ERRATAS to be enabled
+#
+# Core Errata
+ERRATA_A72_859971 := 1
+
+# SoC Errata
+ERRATA_SOC_A050426 := 1
+
+# enable dynamic memory mapping
+PLAT_XLAT_TABLES_DYNAMIC := 1
diff --git a/plat/nxp/soc-lx2160a/soc.mk b/plat/nxp/soc-lx2160a/soc.mk
new file mode 100644
index 0000000..75a3af2
--- /dev/null
+++ b/plat/nxp/soc-lx2160a/soc.mk
@@ -0,0 +1,174 @@
+#
+# Copyright 2018-2020 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+
+ # SoC-specific build parameters
+SOC := lx2160a
+PLAT_PATH := plat/nxp
+PLAT_COMMON_PATH:= plat/nxp/common
+PLAT_DRIVERS_PATH:= drivers/nxp
+PLAT_SOC_PATH := ${PLAT_PATH}/soc-${SOC}
+BOARD_PATH := ${PLAT_SOC_PATH}/${BOARD}
+
+ # get SoC-specific defnitions
+include ${PLAT_SOC_PATH}/soc.def
+include ${PLAT_COMMON_PATH}/plat_make_helper/soc_common_def.mk
+include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
+
+ # SoC-specific
+NXP_WDOG_RESTART := yes
+
+
+ # Selecting dependent module,
+ # Selecting dependent drivers, and
+ # Adding defines.
+
+ # for features enabled above.
+ifeq (${NXP_WDOG_RESTART}, yes)
+NXP_NV_SW_MAINT_LAST_EXEC_DATA := yes
+LS_EL3_INTERRUPT_HANDLER := yes
+$(eval $(call add_define, NXP_WDOG_RESTART))
+endif
+
+
+ # For Security Features
+DISABLE_FUSE_WRITE := 1
+ifeq (${TRUSTED_BOARD_BOOT}, 1)
+ifeq (${GENERATE_COT},1)
+# Save Keys to be used by DDR FIP image
+SAVE_KEYS=1
+endif
+$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
+$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
+$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
+# Used by create_pbl tool to
+# create bl2_<boot_mode>_sec.pbl image
+SECURE_BOOT := yes
+endif
+$(eval $(call SET_NXP_MAKE_FLAG,CRYPTO_NEEDED,BL_COMM))
+
+
+ # Selecting Drivers for SoC
+$(eval $(call SET_NXP_MAKE_FLAG,DCFG_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,TIMER_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,INTERCONNECT_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,GIC_NEEDED,BL31))
+$(eval $(call SET_NXP_MAKE_FLAG,CONSOLE_NEEDED,BL_COMM))
+$(eval $(call SET_NXP_MAKE_FLAG,PMU_NEEDED,BL_COMM))
+
+$(eval $(call SET_NXP_MAKE_FLAG,DDR_DRIVER_NEEDED,BL2))
+$(eval $(call SET_NXP_MAKE_FLAG,TZASC_NEEDED,BL2))
+$(eval $(call SET_NXP_MAKE_FLAG,I2C_NEEDED,BL2))
+$(eval $(call SET_NXP_MAKE_FLAG,IMG_LOADR_NEEDED,BL2))
+
+
+ # Selecting PSCI & SIP_SVC support
+$(eval $(call SET_NXP_MAKE_FLAG,PSCI_NEEDED,BL31))
+$(eval $(call SET_NXP_MAKE_FLAG,SIPSVC_NEEDED,BL31))
+
+
+ # Selecting Boot Source for the TFA images.
+ifeq (${BOOT_MODE}, flexspi_nor)
+$(eval $(call SET_NXP_MAKE_FLAG,XSPI_NEEDED,BL2))
+$(eval $(call add_define,FLEXSPI_NOR_BOOT))
+else
+ifeq (${BOOT_MODE}, sd)
+$(eval $(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2))
+$(eval $(call add_define,SD_BOOT))
+else
+ifeq (${BOOT_MODE}, emmc)
+$(eval $(call SET_NXP_MAKE_FLAG,SD_MMC_NEEDED,BL2))
+$(eval $(call add_define,EMMC_BOOT))
+else
+$(error Un-supported Boot Mode = ${BOOT_MODE})
+endif
+endif
+endif
+
+
+ # Separate DDR-FIP image to be loaded.
+$(eval $(call SET_NXP_MAKE_FLAG,DDR_FIP_IO_NEEDED,BL2))
+
+
+# Source File Addition
+# #####################
+
+PLAT_INCLUDES += -I${PLAT_COMMON_PATH}/include/default\
+ -I${BOARD_PATH}\
+ -I${PLAT_COMMON_PATH}/include/default/ch_${CHASSIS}\
+ -I${PLAT_SOC_PATH}/include\
+ -I${PLAT_COMMON_PATH}/soc_errata
+
+ifeq (${SECURE_BOOT},yes)
+include ${PLAT_COMMON_PATH}/tbbr/tbbr.mk
+endif
+
+ifeq ($(WARM_BOOT),yes)
+include ${PLAT_COMMON_PATH}/warm_reset/warm_reset.mk
+endif
+
+ifeq (${NXP_NV_SW_MAINT_LAST_EXEC_DATA}, yes)
+include ${PLAT_COMMON_PATH}/nv_storage/nv_storage.mk
+endif
+
+ifeq (${PSCI_NEEDED}, yes)
+include ${PLAT_COMMON_PATH}/psci/psci.mk
+endif
+
+ifeq (${SIPSVC_NEEDED}, yes)
+include ${PLAT_COMMON_PATH}/sip_svc/sipsvc.mk
+endif
+
+ifeq (${DDR_FIP_IO_NEEDED}, yes)
+include ${PLAT_COMMON_PATH}/fip_handler/ddr_fip/ddr_fip_io.mk
+endif
+
+ # for fuse-fip & fuse-programming
+ifeq (${FUSE_PROG}, 1)
+include ${PLAT_COMMON_PATH}/fip_handler/fuse_fip/fuse.mk
+endif
+
+ifeq (${IMG_LOADR_NEEDED},yes)
+include $(PLAT_COMMON_PATH)/img_loadr/img_loadr.mk
+endif
+
+ # Adding source files for the above selected drivers.
+include ${PLAT_DRIVERS_PATH}/drivers.mk
+
+ # Adding SoC specific files
+include ${PLAT_COMMON_PATH}/soc_errata/errata.mk
+
+PLAT_INCLUDES += ${NV_STORAGE_INCLUDES}\
+ ${WARM_RST_INCLUDES}
+
+BL31_SOURCES += ${PLAT_SOC_PATH}/$(ARCH)/${SOC}.S\
+ ${WARM_RST_BL31_SOURCES}\
+ ${PSCI_SOURCES}\
+ ${SIPSVC_SOURCES}\
+ ${PLAT_COMMON_PATH}/$(ARCH)/bl31_data.S
+
+PLAT_BL_COMMON_SOURCES += ${PLAT_COMMON_PATH}/$(ARCH)/ls_helpers.S\
+ ${PLAT_SOC_PATH}/aarch64/${SOC}_helpers.S\
+ ${NV_STORAGE_SOURCES}\
+ ${WARM_RST_BL_COMM_SOURCES}\
+ ${PLAT_SOC_PATH}/soc.c
+
+ifeq (${TEST_BL31}, 1)
+BL31_SOURCES += ${PLAT_SOC_PATH}/$(ARCH)/bootmain64.S\
+ ${PLAT_SOC_PATH}/$(ARCH)/nonboot64.S
+endif
+
+BL2_SOURCES += ${DDR_CNTLR_SOURCES}\
+ ${TBBR_SOURCES}\
+ ${FUSE_SOURCES}
+
+
+ # Adding TFA setup files
+include ${PLAT_PATH}/common/setup/common.mk
+
+
+ # Adding source files to generate separate DDR FIP image
+include ${PLAT_SOC_PATH}/ddr_fip.mk
diff --git a/plat/qemu/common/qemu_bl31_setup.c b/plat/qemu/common/qemu_bl31_setup.c
index 4d36b03..4f60eb1 100644
--- a/plat/qemu/common/qemu_bl31_setup.c
+++ b/plat/qemu/common/qemu_bl31_setup.c
@@ -7,6 +7,7 @@
#include <assert.h>
#include <common/bl_common.h>
+#include <drivers/arm/pl061_gpio.h>
#include <plat/common/platform.h>
#include "qemu_private.h"
@@ -69,9 +70,18 @@
BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
}
+static void qemu_gpio_init(void)
+{
+#ifdef SECURE_GPIO_BASE
+ pl061_gpio_init();
+ pl061_gpio_register(SECURE_GPIO_BASE, 0);
+#endif
+}
+
void bl31_platform_setup(void)
{
plat_qemu_gic_init();
+ qemu_gpio_init();
}
unsigned int plat_get_syscnt_freq2(void)
diff --git a/plat/qemu/common/qemu_pm.c b/plat/qemu/common/qemu_pm.c
index cf80009..c4ffcf9 100644
--- a/plat/qemu/common/qemu_pm.c
+++ b/plat/qemu/common/qemu_pm.c
@@ -12,6 +12,7 @@
#include <lib/psci/psci.h>
#include <lib/semihosting.h>
#include <plat/common/platform.h>
+#include <drivers/gpio.h>
#include "qemu_private.h"
@@ -201,16 +202,31 @@
/*******************************************************************************
* Platform handlers to shutdown/reboot the system
******************************************************************************/
+
static void __dead2 qemu_system_off(void)
{
+#ifdef SECURE_GPIO_BASE
+ ERROR("QEMU System Power off: with GPIO.\n");
+ gpio_set_direction(SECURE_GPIO_POWEROFF, GPIO_DIR_OUT);
+ gpio_set_value(SECURE_GPIO_POWEROFF, GPIO_LEVEL_HIGH);
+ gpio_set_value(SECURE_GPIO_POWEROFF, GPIO_LEVEL_LOW);
+#else
semihosting_exit(ADP_STOPPED_APPLICATION_EXIT, 0);
ERROR("QEMU System Off: semihosting call unexpectedly returned.\n");
+#endif
panic();
}
static void __dead2 qemu_system_reset(void)
{
+ ERROR("QEMU System Reset: with GPIO.\n");
+#ifdef SECURE_GPIO_BASE
+ gpio_set_direction(SECURE_GPIO_RESET, GPIO_DIR_OUT);
+ gpio_set_value(SECURE_GPIO_RESET, GPIO_LEVEL_HIGH);
+ gpio_set_value(SECURE_GPIO_RESET, GPIO_LEVEL_LOW);
+#else
ERROR("QEMU System Reset: operation not handled.\n");
+#endif
panic();
}
diff --git a/plat/qemu/common/qemu_spm.c b/plat/qemu/common/qemu_spm.c
index 93dd2b3..c66f47e 100644
--- a/plat/qemu/common/qemu_spm.c
+++ b/plat/qemu/common/qemu_spm.c
@@ -29,20 +29,8 @@
{0}
};
-/*
- * Boot information passed to a secure partition during initialisation.
- * Linear indices in MP information will be filled at runtime.
- */
-static spm_mm_mp_info_t sp_mp_info[] = {
- [0] = {0x80000000, 0},
- [1] = {0x80000001, 0},
- [2] = {0x80000002, 0},
- [3] = {0x80000003, 0},
- [4] = {0x80000004, 0},
- [5] = {0x80000005, 0},
- [6] = {0x80000006, 0},
- [7] = {0x80000007, 0}
-};
+/* Boot information passed to a secure partition during initialisation. */
+static spm_mm_mp_info_t sp_mp_info[PLATFORM_CORE_COUNT];
spm_mm_boot_info_t plat_qemu_secure_partition_boot_info = {
.h.type = PARAM_SP_IMAGE_BOOT_INFO,
@@ -71,6 +59,25 @@
EHF_PRI_DESC(QEMU_PRI_BITS, PLAT_SP_PRI)
};
+static void qemu_initialize_mp_info(spm_mm_mp_info_t *mp_info)
+{
+ unsigned int i, j;
+ spm_mm_mp_info_t *tmp = mp_info;
+
+ for (i = 0; i < PLATFORM_CLUSTER_COUNT; i++) {
+ for (j = 0; j < PLATFORM_MAX_CPUS_PER_CLUSTER; j++) {
+ tmp->mpidr = (0x80000000 | (i << MPIDR_AFF1_SHIFT)) + j;
+ /*
+ * Linear indices and flags will be filled
+ * in the spm_mm service.
+ */
+ tmp->linear_id = 0;
+ tmp->flags = 0;
+ tmp++;
+ }
+ }
+}
+
int dt_add_ns_buf_node(uintptr_t *base)
{
uintptr_t addr;
@@ -134,5 +141,7 @@
const spm_mm_boot_info_t *
plat_get_secure_partition_boot_info(void *cookie)
{
+ qemu_initialize_mp_info(sp_mp_info);
+
return &plat_qemu_secure_partition_boot_info;
}
diff --git a/plat/qemu/qemu/include/platform_def.h b/plat/qemu/qemu/include/platform_def.h
index e6bb1e6..c02eff9 100644
--- a/plat/qemu/qemu/include/platform_def.h
+++ b/plat/qemu/qemu/include/platform_def.h
@@ -80,8 +80,8 @@
#define SEC_ROM_BASE 0x00000000
#define SEC_ROM_SIZE 0x00020000
-#define NS_DRAM0_BASE 0x40000000
-#define NS_DRAM0_SIZE 0x3de00000
+#define NS_DRAM0_BASE ULL(0x40000000)
+#define NS_DRAM0_SIZE ULL(0xc0000000)
#define SEC_SRAM_BASE 0x0e000000
#define SEC_SRAM_SIZE 0x00060000
@@ -89,6 +89,11 @@
#define SEC_DRAM_BASE 0x0e100000
#define SEC_DRAM_SIZE 0x00f00000
+#define SECURE_GPIO_BASE 0x090b0000
+#define SECURE_GPIO_SIZE 0x00001000
+#define SECURE_GPIO_POWEROFF 0
+#define SECURE_GPIO_RESET 1
+
/* Load pageable part of OP-TEE 2MB above secure DRAM base */
#define QEMU_OPTEE_PAGEABLE_LOAD_BASE (SEC_DRAM_BASE + 0x00200000)
#define QEMU_OPTEE_PAGEABLE_LOAD_SIZE 0x00400000
@@ -210,7 +215,7 @@
#define DEVICE0_BASE 0x08000000
#define DEVICE0_SIZE 0x01000000
#define DEVICE1_BASE 0x09000000
-#define DEVICE1_SIZE 0x00041000
+#define DEVICE1_SIZE 0x00c00000
/*
* GIC related constants
diff --git a/plat/qemu/qemu/platform.mk b/plat/qemu/qemu/platform.mk
index 14bf049..a3b353f 100644
--- a/plat/qemu/qemu/platform.mk
+++ b/plat/qemu/qemu/platform.mk
@@ -107,7 +107,10 @@
ifeq (${ARM_ARCH_MAJOR},8)
BL1_SOURCES += lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
- lib/cpus/aarch64/cortex_a57.S
+ lib/cpus/aarch64/cortex_a57.S \
+ lib/cpus/aarch64/cortex_a72.S \
+ lib/cpus/aarch64/qemu_max.S \
+
else
BL1_SOURCES += lib/cpus/${ARCH}/cortex_a15.S
endif
@@ -135,9 +138,9 @@
BL2_SOURCES += drivers/io/io_encrypted.c
endif
-QEMU_GICV2_SOURCES := drivers/arm/gic/v2/gicv2_helpers.c \
- drivers/arm/gic/v2/gicv2_main.c \
- drivers/arm/gic/common/gic_common.c \
+# Include GICv2 driver files
+include drivers/arm/gic/v2/gicv2.mk
+QEMU_GICV2_SOURCES := ${GICV2_SOURCES} \
plat/common/plat_gicv2.c \
${PLAT_QEMU_COMMON_PATH}/qemu_gicv2.c
@@ -160,9 +163,13 @@
BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
+ lib/cpus/aarch64/cortex_a72.S \
+ lib/cpus/aarch64/qemu_max.S \
lib/semihosting/semihosting.c \
lib/semihosting/${ARCH}/semihosting_call.S \
plat/common/plat_psci_common.c \
+ drivers/arm/pl061/pl061_gpio.c \
+ drivers/gpio/gpio.c \
${PLAT_QEMU_COMMON_PATH}/qemu_pm.c \
${PLAT_QEMU_COMMON_PATH}/topology.c \
${PLAT_QEMU_COMMON_PATH}/aarch64/plat_helpers.S \
diff --git a/plat/qemu/qemu_sbsa/include/platform_def.h b/plat/qemu/qemu_sbsa/include/platform_def.h
index b69c2eb..d971ebe 100644
--- a/plat/qemu/qemu_sbsa/include/platform_def.h
+++ b/plat/qemu/qemu_sbsa/include/platform_def.h
@@ -171,7 +171,7 @@
#if SPM_MM && defined(IMAGE_BL31)
# define PLAT_SP_IMAGE_MMAP_REGIONS 30
-# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 20
+# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 50
#endif
/*
@@ -353,7 +353,7 @@
#define MAP_SECURE_VARSTORE MAP_REGION_FLAT( \
QEMU_SECURE_VARSTORE_BASE, \
QEMU_SECURE_VARSTORE_SIZE, \
- MT_MEMORY | MT_RW | \
+ MT_DEVICE | MT_RW | \
MT_SECURE | MT_USER)
#endif
diff --git a/plat/qemu/qemu_sbsa/platform.mk b/plat/qemu/qemu_sbsa/platform.mk
index d45f3f1..9fb30ad 100644
--- a/plat/qemu/qemu_sbsa/platform.mk
+++ b/plat/qemu/qemu_sbsa/platform.mk
@@ -48,7 +48,8 @@
${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c
BL1_SOURCES += lib/cpus/aarch64/cortex_a57.S \
- lib/cpus/aarch64/cortex_a72.S
+ lib/cpus/aarch64/cortex_a72.S \
+ lib/cpus/aarch64/qemu_max.S \
BL2_SOURCES += drivers/io/io_semihosting.c \
drivers/io/io_storage.c \
@@ -76,6 +77,7 @@
BL31_SOURCES += lib/cpus/aarch64/cortex_a57.S \
lib/cpus/aarch64/cortex_a72.S \
+ lib/cpus/aarch64/qemu_max.S \
lib/semihosting/semihosting.c \
lib/semihosting/${ARCH}/semihosting_call.S \
plat/common/plat_psci_common.c \
diff --git a/plat/qti/common/src/spmi_arb.c b/plat/qti/common/src/spmi_arb.c
index 16e85a6..4213ed1 100644
--- a/plat/qti/common/src/spmi_arb.c
+++ b/plat/qti/common/src/spmi_arb.c
@@ -10,8 +10,8 @@
#include <spmi_arb.h>
-#define REG_APID_MAP(apid) (0x0C440900U + 4U * i)
-#define NUM_APID 0x80
+#define REG_APID_MAP(apid) (0x0C440900U + sizeof(uint32_t) * apid)
+#define NUM_APID ((0x1100U - 0x900U) / sizeof(uint32_t))
#define PPID_MASK (0xfffU << 8)
diff --git a/plat/renesas/common/bl2_cpg_init.c b/plat/renesas/common/bl2_cpg_init.c
index 677a57d..ba8e53b 100644
--- a/plat/renesas/common/bl2_cpg_init.c
+++ b/plat/renesas/common/bl2_cpg_init.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,7 +13,8 @@
static void bl2_secure_cpg_init(void);
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || \
+ (RCAR_LSI == RCAR_H3N) || (RCAR_LSI == RZ_G2H)
static void bl2_realtime_cpg_init_h3(void);
static void bl2_system_cpg_init_h3(void);
#endif
@@ -23,7 +24,7 @@
static void bl2_system_cpg_init_m3(void);
#endif
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N) || (RCAR_LSI == RZ_G2N)
static void bl2_realtime_cpg_init_m3n(void);
static void bl2_system_cpg_init_m3n(void);
#endif
@@ -33,7 +34,7 @@
static void bl2_system_cpg_init_v3m(void);
#endif
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2E)
static void bl2_realtime_cpg_init_e3(void);
static void bl2_system_cpg_init_e3(void);
#endif
@@ -57,7 +58,7 @@
#if (RCAR_LSI == RCAR_D3)
reset_cr2 = 0x00000000U;
stop_cr2 = 0xFFFFFFFFU;
-#elif (RCAR_LSI == RCAR_E3)
+#elif (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2E)
reset_cr2 = 0x10000000U;
stop_cr2 = 0xEFFFFFFFU;
#else
@@ -106,7 +107,8 @@
cpg_write(SCSRSTECR11, 0x00000000U);
}
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || \
+ (RCAR_LSI == RCAR_H3N) || (RCAR_LSI == RZ_G2H)
static void bl2_realtime_cpg_init_h3(void)
{
uint32_t cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
@@ -185,7 +187,7 @@
}
#endif
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N) || (RCAR_LSI == RZ_G2N)
static void bl2_realtime_cpg_init_m3n(void)
{
/* Realtime Module Stop Control Registers */
@@ -253,7 +255,7 @@
}
#endif
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2E)
static void bl2_realtime_cpg_init_e3(void)
{
/* Realtime Module Stop Control Registers */
@@ -360,15 +362,15 @@
panic();
break;
}
-#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) || (RCAR_LSI == RZ_G2H)
bl2_realtime_cpg_init_h3();
#elif (RCAR_LSI == RCAR_M3) || (RCAR_LSI == RZ_G2M)
bl2_realtime_cpg_init_m3();
-#elif RCAR_LSI == RCAR_M3N
+#elif RCAR_LSI == RCAR_M3N || (RCAR_LSI == RZ_G2N)
bl2_realtime_cpg_init_m3n();
#elif RCAR_LSI == RCAR_V3M
bl2_realtime_cpg_init_v3m();
-#elif RCAR_LSI == RCAR_E3
+#elif RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2E
bl2_realtime_cpg_init_e3();
#elif RCAR_LSI == RCAR_D3
bl2_realtime_cpg_init_d3();
@@ -406,15 +408,15 @@
panic();
break;
}
-#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) || (RCAR_LSI == RZ_G2H)
bl2_system_cpg_init_h3();
#elif (RCAR_LSI == RCAR_M3) || (RCAR_LSI == RZ_G2M)
bl2_system_cpg_init_m3();
-#elif RCAR_LSI == RCAR_M3N
+#elif RCAR_LSI == RCAR_M3N || (RCAR_LSI == RZ_G2N)
bl2_system_cpg_init_m3n();
#elif RCAR_LSI == RCAR_V3M
bl2_system_cpg_init_v3m();
-#elif RCAR_LSI == RCAR_E3
+#elif RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2E
bl2_system_cpg_init_e3();
#elif RCAR_LSI == RCAR_D3
bl2_system_cpg_init_d3();
diff --git a/plat/renesas/common/common.mk b/plat/renesas/common/common.mk
index 984ab5b..fafce98 100644
--- a/plat/renesas/common/common.mk
+++ b/plat/renesas/common/common.mk
@@ -34,6 +34,9 @@
RCAR_V3M:=6
RCAR_AUTO:=99
RZ_G2M:=100
+RZ_G2H:=101
+RZ_G2N:=102
+RZ_G2E:=103
$(eval $(call add_define,RCAR_H3))
$(eval $(call add_define,RCAR_M3))
$(eval $(call add_define,RCAR_M3N))
@@ -43,6 +46,9 @@
$(eval $(call add_define,RCAR_V3M))
$(eval $(call add_define,RCAR_AUTO))
$(eval $(call add_define,RZ_G2M))
+$(eval $(call add_define,RZ_G2H))
+$(eval $(call add_define,RZ_G2N))
+$(eval $(call add_define,RZ_G2E))
RCAR_CUT_10:=0
RCAR_CUT_11:=1
diff --git a/plat/renesas/common/include/platform_def.h b/plat/renesas/common/include/platform_def.h
index 7378714..72c7688 100644
--- a/plat/renesas/common/include/platform_def.h
+++ b/plat/renesas/common/include/platform_def.h
@@ -151,7 +151,8 @@
* BL33
******************************************************************************/
#define BL33_BASE DRAM1_NS_BASE
-
+#define BL33_COMP_SIZE U(0x200000)
+#define BL33_COMP_BASE (BL33_BASE - BL33_COMP_SIZE)
/*******************************************************************************
* Platform specific page table and MMU setup constants
diff --git a/plat/renesas/common/include/rcar_def.h b/plat/renesas/common/include/rcar_def.h
index 6c5b295..93a65f1 100644
--- a/plat/renesas/common/include/rcar_def.h
+++ b/plat/renesas/common/include/rcar_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -120,7 +120,6 @@
/* Timer control */
#define RCAR_CNTC_BASE U(0xE6080000)
/* Reset */
-#define RCAR_CPGWPR U(0xE6150900) /* CPG write protect */
#define RCAR_MODEMR U(0xE6160060) /* Mode pin */
#define RCAR_CA57RESCNT U(0xE6160040) /* Reset control A57 */
#define RCAR_CA53RESCNT U(0xE6160044) /* Reset control A53 */
diff --git a/plat/renesas/common/include/rcar_version.h b/plat/renesas/common/include/rcar_version.h
index 67cbd71..173111d 100644
--- a/plat/renesas/common/include/rcar_version.h
+++ b/plat/renesas/common/include/rcar_version.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,7 +9,7 @@
#include <arch_helpers.h>
-#define VERSION_OF_RENESAS "2.0.6"
+#define VERSION_OF_RENESAS "3.0.0"
#define VERSION_OF_RENESAS_MAXLEN 128
extern const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN];
diff --git a/plat/renesas/common/include/registers/cpg_registers.h b/plat/renesas/common/include/registers/cpg_registers.h
index 0d698d9..5d2bb9e 100644
--- a/plat/renesas/common/include/registers/cpg_registers.h
+++ b/plat/renesas/common/include/registers/cpg_registers.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,6 +16,8 @@
#define CPG_SRCR2 (CPG_BASE + 0x00B0U)
/* CPG module stop status 2 */
#define CPG_MSTPSR2 (CPG_BASE + 0x0040U)
+/* CPG module stop status 2 */
+#define CPG_MSTPSR3 (CPG_BASE + 0x0048U)
/* CPG write protect */
#define CPG_CPGWPR (CPG_BASE + 0x0900U)
/* CPG write protect control */
@@ -24,6 +26,10 @@
#define CPG_SMSTPCR9 (CPG_BASE + 0x0994U)
/* CPG module stop status 9 */
#define CPG_MSTPSR9 (CPG_BASE + 0x09A4U)
+/* SDHI2 clock frequency control register */
+#define CPG_SD2CKCR (CPG_BASE + 0x0268U)
+/* SDHI3 clock frequency control register */
+#define CPG_SD3CKCR (CPG_BASE + 0x026CU)
/* CPG (SECURITY) registers */
diff --git a/plat/renesas/common/rcar_common.c b/plat/renesas/common/rcar_common.c
index dec7229..df4c30c 100644
--- a/plat/renesas/common/rcar_common.c
+++ b/plat/renesas/common/rcar_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2019-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -12,9 +12,8 @@
#include <plat/common/platform.h>
#include <lib/mmio.h>
+#include <cpg_registers.h>
-#define CPG_BASE 0xE6150000
-#define CPG_MSTPSR3 0x0048
#define MSTP318 (1 << 18)
#define MSTP319 (1 << 19)
#define PMSR 0x5c
@@ -31,7 +30,7 @@
int ret = 0;
/* Test if PCIECx is enabled */
- cpg = mmio_read_32(CPG_BASE + CPG_MSTPSR3);
+ cpg = mmio_read_32(CPG_MSTPSR3);
if (cpg & (MSTP318 << !controller))
return ret;
@@ -61,11 +60,7 @@
if (fixed)
return;
- ERROR("Unhandled External Abort received on 0x%lx at EL3!\n",
- read_mpidr_el1());
- ERROR(" exception reason=%u syndrome=0x%llx\n", ea_reason, syndrome);
-
- panic();
+ plat_default_ea_handler(ea_reason, syndrome, cookie, handle, flags);
}
#include <drivers/renesas/rcar/console/console.h>
diff --git a/plat/renesas/rcar/bl2_plat_setup.c b/plat/renesas/rcar/bl2_plat_setup.c
index add2a4f..41b2d11 100644
--- a/plat/renesas/rcar/bl2_plat_setup.c
+++ b/plat/renesas/rcar/bl2_plat_setup.c
@@ -15,12 +15,16 @@
#include <common/bl_common.h>
#include <common/debug.h>
#include <common/desc_image_load.h>
+#include <common/image_decompress.h>
#include <drivers/console.h>
#include <drivers/io/io_driver.h>
#include <drivers/io/io_storage.h>
#include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
#include <plat/common/platform.h>
+#if RCAR_GEN3_BL33_GZIP == 1
+#include <tf_gunzip.h>
+#endif
#include "avs_driver.h"
#include "boot_init_dram.h"
@@ -357,16 +361,29 @@
#endif
}
+#if RCAR_GEN3_BL33_GZIP == 1
+void bl2_plat_preload_setup(void)
+{
+ image_decompress_init(BL33_COMP_BASE, BL33_COMP_SIZE, gunzip);
+}
+#endif
+
int bl2_plat_handle_pre_image_load(unsigned int image_id)
{
u_register_t *boot_kind = (void *) BOOT_KIND_BASE;
bl_mem_params_node_t *bl_mem_params;
+ bl_mem_params = get_bl_mem_params_node(image_id);
+
+#if RCAR_GEN3_BL33_GZIP == 1
+ if (image_id == BL33_IMAGE_ID) {
+ image_decompress_prepare(&bl_mem_params->image_info);
+ }
+#endif
+
if (image_id != BL31_IMAGE_ID)
return 0;
- bl_mem_params = get_bl_mem_params_node(image_id);
-
if (is_ddr_backup_mode() == RCAR_COLD_BOOT)
goto cold_boot;
@@ -433,6 +450,19 @@
sizeof(entry_point_info_t));
break;
case BL33_IMAGE_ID:
+#if RCAR_GEN3_BL33_GZIP == 1
+ if ((mmio_read_32(BL33_COMP_BASE) & 0xffff) == 0x8b1f) {
+ /* decompress gzip-compressed image */
+ ret = image_decompress(&bl_mem_params->image_info);
+ if (ret != 0) {
+ return ret;
+ }
+ } else {
+ /* plain image, copy it in place */
+ memcpy((void *)BL33_BASE, (void *)BL33_COMP_BASE,
+ bl_mem_params->image_info.image_size);
+ }
+#endif
memcpy(¶ms->bl33_ep_info, &bl_mem_params->ep_info,
sizeof(entry_point_info_t));
break;
@@ -535,12 +565,75 @@
}
}
-static void bl2_advertise_dram_entries(uint64_t dram_config[8])
+static void bl2_add_rpc_node(void)
+{
+#if (RCAR_RPC_HYPERFLASH_LOCKED == 0)
+ int ret, node;
+
+ node = ret = fdt_add_subnode(fdt, 0, "soc");
+ if (ret < 0) {
+ goto err;
+ }
+
+ node = ret = fdt_add_subnode(fdt, node, "rpc@ee200000");
+ if (ret < 0) {
+ goto err;
+ }
+
+ ret = fdt_setprop_string(fdt, node, "status", "okay");
+ if (ret < 0) {
+ goto err;
+ }
+
+ return;
+err:
+ NOTICE("BL2: Cannot add RPC node to FDT (ret=%i)\n", ret);
+ panic();
+#endif
+}
+
+static void bl2_add_dram_entry(uint64_t start, uint64_t size)
{
char nodename[32] = { 0 };
- uint64_t start, size;
uint64_t fdtsize;
- int ret, node, chan;
+ int ret, node;
+
+ fdtsize = cpu_to_fdt64(size);
+
+ snprintf(nodename, sizeof(nodename), "memory@");
+ unsigned_num_print(start, 16, nodename + strlen(nodename));
+ node = ret = fdt_add_subnode(fdt, 0, nodename);
+ if (ret < 0) {
+ goto err;
+ }
+
+ ret = fdt_setprop_string(fdt, node, "device_type", "memory");
+ if (ret < 0) {
+ goto err;
+ }
+
+ ret = fdt_setprop_u64(fdt, node, "reg", start);
+ if (ret < 0) {
+ goto err;
+ }
+
+ ret = fdt_appendprop(fdt, node, "reg", &fdtsize,
+ sizeof(fdtsize));
+ if (ret < 0) {
+ goto err;
+ }
+
+ return;
+err:
+ NOTICE("BL2: Cannot add memory node [%llx - %llx] to FDT (ret=%i)\n",
+ start, start + size - 1, ret);
+ panic();
+}
+
+static void bl2_advertise_dram_entries(uint64_t dram_config[8])
+{
+ uint64_t start, size, size32;
+ int chan;
for (chan = 0; chan < 4; chan++) {
start = dram_config[2 * chan];
@@ -568,39 +661,43 @@
/*
* Channel 0 is mapped in 32bit space and the first
- * 128 MiB are reserved
+ * 128 MiB are reserved and the maximum size is 2GiB.
*/
if (chan == 0) {
- start = 0x48000000;
- size -= 0x8000000;
+ /* Limit the 32bit entry to 2 GiB - 128 MiB */
+ size32 = size - 0x8000000U;
+ if (size32 >= 0x78000000U) {
+ size32 = 0x78000000U;
+ }
+
+ /* Emit 32bit entry, up to 2 GiB - 128 MiB long. */
+ bl2_add_dram_entry(0x48000000, size32);
+
+ /*
+ * If channel 0 is less than 2 GiB long, the
+ * entire memory fits into the 32bit space entry,
+ * so move on to the next channel.
+ */
+ if (size <= 0x80000000U) {
+ continue;
+ }
+
+ /*
+ * If channel 0 is more than 2 GiB long, emit
+ * another entry which covers the rest of the
+ * memory in channel 0, in the 64bit space.
+ *
+ * Start of this new entry is at 2 GiB offset
+ * from the beginning of the 64bit channel 0
+ * address, size is 2 GiB shorter than total
+ * size of the channel.
+ */
+ start += 0x80000000U;
+ size -= 0x80000000U;
}
- fdtsize = cpu_to_fdt64(size);
-
- snprintf(nodename, sizeof(nodename), "memory@");
- unsigned_num_print(start, 16, nodename + strlen(nodename));
- node = ret = fdt_add_subnode(fdt, 0, nodename);
- if (ret < 0)
- goto err;
-
- ret = fdt_setprop_string(fdt, node, "device_type", "memory");
- if (ret < 0)
- goto err;
-
- ret = fdt_setprop_u64(fdt, node, "reg", start);
- if (ret < 0)
- goto err;
-
- ret = fdt_appendprop(fdt, node, "reg", &fdtsize,
- sizeof(fdtsize));
- if (ret < 0)
- goto err;
+ bl2_add_dram_entry(start, size);
}
-
- return;
-err:
- NOTICE("BL2: Cannot add memory node to FDT (ret=%i)\n", ret);
- panic();
}
static void bl2_advertise_dram_size(uint32_t product)
@@ -648,8 +745,13 @@
break;
case PRR_PRODUCT_M3N:
+#if (RCAR_DRAM_LPDDR4_MEMCONF == 2)
+ /* 4GB(4GBx1) */
+ dram_config[1] = 0x100000000ULL;
+#elif (RCAR_DRAM_LPDDR4_MEMCONF == 1)
/* 2GB(1GBx2) */
dram_config[1] = 0x80000000ULL;
+#endif
break;
case PRR_PRODUCT_V3M:
@@ -935,6 +1037,9 @@
/* Add platform compatible string */
bl2_populate_compatible_string(fdt);
+ /* Enable RPC if unlocked */
+ bl2_add_rpc_node();
+
/* Print DRAM layout */
bl2_advertise_dram_size(product);
diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk
index 5e4978c..670d499 100644
--- a/plat/renesas/rcar/platform.mk
+++ b/plat/renesas/rcar/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
+# Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -245,6 +245,12 @@
endif
$(eval $(call add_define,RCAR_DRAM_LPDDR4_MEMCONF))
+# Process RCAR_DRAM_MEMRANK flag
+ifndef RCAR_DRAM_MEMRANK
+RCAR_DRAM_MEMRANK :=0
+endif
+$(eval $(call add_define,RCAR_DRAM_MEMRANK))
+
# Process RCAR_DRAM_DDR3L_MEMCONF flag
ifndef RCAR_DRAM_DDR3L_MEMCONF
RCAR_DRAM_DDR3L_MEMCONF :=1
@@ -280,6 +286,11 @@
endif
$(eval $(call add_define,RCAR_SYSTEM_RESET_KEEPON_DDR))
+ifndef RCAR_GEN3_BL33_GZIP
+RCAR_GEN3_BL33_GZIP := 0
+endif
+$(eval $(call add_define,RCAR_GEN3_BL33_GZIP))
+
# RCAR_SYSTEM_RESET_KEEPON_DDR requires power control of PMIC etc.
# When executing SYSTEM_SUSPEND other than Salvator-X, Salvator-XS and Ebisu,
# processing equivalent to that implemented in PMIC_ROHM_BD9571 is necessary.
@@ -293,12 +304,12 @@
endif
endif
-include drivers/renesas/rcar/ddr/ddr.mk
+include drivers/renesas/common/ddr/ddr.mk
include drivers/renesas/rcar/qos/qos.mk
include drivers/renesas/rcar/pfc/pfc.mk
include lib/libfdt/libfdt.mk
-PLAT_INCLUDES += -Idrivers/renesas/rcar/ddr \
+PLAT_INCLUDES += -Idrivers/renesas/common/ddr \
-Idrivers/renesas/rcar/qos \
-Idrivers/renesas/rcar/board \
-Idrivers/renesas/rcar/cpld/ \
@@ -315,6 +326,13 @@
BL2_SOURCES += plat/renesas/rcar/bl2_plat_setup.c \
drivers/renesas/rcar/board/board.c
+ifeq (${RCAR_GEN3_BL33_GZIP},1)
+include lib/zlib/zlib.mk
+
+BL2_SOURCES += common/image_decompress.c \
+ $(ZLIB_SOURCES)
+endif
+
ifeq (${RCAR_GEN3_ULCB},1)
BL31_SOURCES += drivers/renesas/rcar/cpld/ulcb_cpld.c
endif
diff --git a/plat/renesas/rzg/bl2_plat_setup.c b/plat/renesas/rzg/bl2_plat_setup.c
index 13f413b..ccc2562 100644
--- a/plat/renesas/rzg/bl2_plat_setup.c
+++ b/plat/renesas/rzg/bl2_plat_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -78,12 +78,26 @@
#if RCAR_LSI == RZ_G2M
#define TARGET_PRODUCT PRR_PRODUCT_M3
#define TARGET_NAME "RZ/G2M"
+#elif RCAR_LSI == RZ_G2H
+#define TARGET_PRODUCT PRR_PRODUCT_H3
+#define TARGET_NAME "RZ/G2H"
+#elif RCAR_LSI == RZ_G2N
+#define TARGET_PRODUCT PRR_PRODUCT_M3N
+#define TARGET_NAME "RZ/G2N"
+#elif RCAR_LSI == RZ_G2E
+#define TARGET_PRODUCT PRR_PRODUCT_E3
+#define TARGET_NAME "RZ/G2E"
#elif RCAR_LSI == RCAR_AUTO
#define TARGET_NAME "RZ/G2M"
#endif /* RCAR_LSI == RZ_G2M */
+#if (RCAR_LSI == RZ_G2E)
+#define GPIO_INDT (GPIO_INDT6)
+#define GPIO_BKUP_TRG_SHIFT ((uint32_t)1U << 13U)
+#else
#define GPIO_INDT (GPIO_INDT1)
#define GPIO_BKUP_TRG_SHIFT (1U << 8U)
+#endif /* RCAR_LSI == RZ_G2E */
CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100)
< (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE),
@@ -424,6 +438,18 @@
ret = fdt_setprop_string(dt, 0, "compatible",
"hoperun,hihope-rzg2m");
break;
+ case BOARD_HIHOPE_RZ_G2H:
+ ret = fdt_setprop_string(dt, 0, "compatible",
+ "hoperun,hihope-rzg2h");
+ break;
+ case BOARD_HIHOPE_RZ_G2N:
+ ret = fdt_setprop_string(dt, 0, "compatible",
+ "hoperun,hihope-rzg2n");
+ break;
+ case BOARD_EK874_RZ_G2E:
+ ret = fdt_setprop_string(dt, 0, "compatible",
+ "si-linux,cat874");
+ break;
default:
NOTICE("BL2: Cannot set compatible string, board unsupported\n");
panic();
@@ -441,6 +467,18 @@
ret = fdt_appendprop_string(dt, 0, "compatible",
"renesas,r8a774a1");
break;
+ case PRR_PRODUCT_H3:
+ ret = fdt_appendprop_string(dt, 0, "compatible",
+ "renesas,r8a774e1");
+ break;
+ case PRR_PRODUCT_M3N:
+ ret = fdt_appendprop_string(dt, 0, "compatible",
+ "renesas,r8a774b1");
+ break;
+ case PRR_PRODUCT_E3:
+ ret = fdt_appendprop_string(dt, 0, "compatible",
+ "renesas,r8a774c0");
+ break;
default:
NOTICE("BL2: Cannot set compatible string, SoC unsupported\n");
panic();
@@ -560,6 +598,42 @@
dram_config[1] = 0x80000000ULL;
dram_config[5] = 0x80000000ULL;
break;
+ case PRR_PRODUCT_H3:
+#if (RCAR_DRAM_LPDDR4_MEMCONF == 0)
+ /* 4GB(1GBx4) */
+ dram_config[1] = 0x40000000ULL;
+ dram_config[3] = 0x40000000ULL;
+ dram_config[5] = 0x40000000ULL;
+ dram_config[7] = 0x40000000ULL;
+#elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 5) && \
+ (RCAR_DRAM_SPLIT == 2)
+ /* 4GB(2GBx2 2ch split) */
+ dram_config[1] = 0x80000000ULL;
+ dram_config[3] = 0x80000000ULL;
+#elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15)
+ /* 8GB(2GBx4: default) */
+ dram_config[1] = 0x80000000ULL;
+ dram_config[3] = 0x80000000ULL;
+ dram_config[5] = 0x80000000ULL;
+ dram_config[7] = 0x80000000ULL;
+#endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */
+ break;
+ case PRR_PRODUCT_M3N:
+ /* 4GB(4GBx1) */
+ dram_config[1] = 0x100000000ULL;
+ break;
+ case PRR_PRODUCT_E3:
+#if (RCAR_DRAM_DDR3L_MEMCONF == 0)
+ /* 1GB(512MBx2) */
+ dram_config[1] = 0x40000000ULL;
+#elif (RCAR_DRAM_DDR3L_MEMCONF == 1)
+ /* 2GB(512MBx4) */
+ dram_config[1] = 0x80000000ULL;
+#elif (RCAR_DRAM_DDR3L_MEMCONF == 2)
+ /* 4GB(1GBx4) */
+ dram_config[1] = 0x100000000ULL;
+#endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */
+ break;
default:
NOTICE("BL2: Detected invalid DRAM entries\n");
break;
@@ -578,13 +652,23 @@
const char *unknown = "unknown";
const char *cpu_ca57 = "CA57";
const char *cpu_ca53 = "CA53";
+ const char *product_g2e = "G2E";
+ const char *product_g2h = "G2H";
const char *product_g2m = "G2M";
+ const char *product_g2n = "G2N";
const char *boot_hyper80 = "HyperFlash(80MHz)";
const char *boot_qspi40 = "QSPI Flash(40MHz)";
const char *boot_qspi80 = "QSPI Flash(80MHz)";
const char *boot_emmc25x1 = "eMMC(25MHz x1)";
const char *boot_emmc50x8 = "eMMC(50MHz x8)";
+#if (RCAR_LSI == RZ_G2E)
+ uint32_t sscg;
+ const char *sscg_on = "PLL1 SSCG Clock select";
+ const char *sscg_off = "PLL1 nonSSCG Clock select";
+ const char *boot_hyper160 = "HyperFlash(150MHz)";
+#else
const char *boot_hyper160 = "HyperFlash(160MHz)";
+#endif /* RCAR_LSI == RZ_G2E */
#if RZG_LCS_STATE_DETECTION_ENABLE
uint32_t lcs;
const char *lcs_secure = "SE";
@@ -646,6 +730,15 @@
case PRR_PRODUCT_M3:
str = product_g2m;
break;
+ case PRR_PRODUCT_H3:
+ str = product_g2h;
+ break;
+ case PRR_PRODUCT_M3N:
+ str = product_g2n;
+ break;
+ case PRR_PRODUCT_E3:
+ str = product_g2e;
+ break;
default:
str = unknown;
break;
@@ -667,10 +760,22 @@
NOTICE("BL2: PRR is RZ/%s Ver.%d.%d\n", str, major, minor);
}
+#if (RCAR_LSI == RZ_G2E)
+ if (product == PRR_PRODUCT_E3) {
+ reg = mmio_read_32(RCAR_MODEMR);
+ sscg = reg & RCAR_SSCG_MASK;
+ str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off;
+ NOTICE("BL2: %s\n", str);
+ }
+#endif /* RCAR_LSI == RZ_G2E */
+
rzg_get_board_type(&type, &rev);
switch (type) {
case BOARD_HIHOPE_RZ_G2M:
+ case BOARD_HIHOPE_RZ_G2H:
+ case BOARD_HIHOPE_RZ_G2N:
+ case BOARD_EK874_RZ_G2E:
break;
default:
type = BOARD_UNKNOWN;
@@ -762,7 +867,7 @@
if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
boot_cpu == MODEMR_BOOT_CPU_CA53) {
- ret = rzg_dram_init();
+ ret = rcar_dram_init();
if (ret != 0) {
NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret);
panic();
@@ -884,6 +989,9 @@
static void bl2_init_generic_timer(void)
{
+#if RCAR_LSI == RZ_G2E
+ uint32_t reg_cntfid = EXTAL_EBISU;
+#else
uint32_t reg_cntfid;
uint32_t modemr;
uint32_t modemr_pll;
@@ -899,6 +1007,7 @@
/* Set frequency data in CNTFID0 */
reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT];
+#endif /* RCAR_LSI == RZ_G2E */
/* Update memory mapped and register based frequency */
write_cntfrq_el0((u_register_t)reg_cntfid);
diff --git a/plat/renesas/rzg/platform.mk b/plat/renesas/rzg/platform.mk
index 421cbbe..f37d7d0 100644
--- a/plat/renesas/rzg/platform.mk
+++ b/plat/renesas/rzg/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
+# Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -32,6 +32,55 @@
endif
$(eval $(call add_define,RCAR_LSI_CUT))
endif
+ else ifeq (${LSI},G2H)
+ RCAR_LSI:=${RZ_G2H}
+ ifndef LSI_CUT
+ # enable compatible function.
+ RCAR_LSI_CUT_COMPAT := 1
+ $(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
+ else
+ # disable compatible function.
+ ifeq (${LSI_CUT},30)
+ RCAR_LSI_CUT:=20
+ else
+ $(error "Error: ${LSI_CUT} is not supported.")
+ endif
+ $(eval $(call add_define,RCAR_LSI_CUT))
+ endif
+ else ifeq (${LSI},G2N)
+ RCAR_LSI:=${RZ_G2N}
+ ifndef LSI_CUT
+ # enable compatible function.
+ RCAR_LSI_CUT_COMPAT := 1
+ $(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
+ else
+ # disable compatible function.
+ ifeq (${LSI_CUT},10)
+ RCAR_LSI_CUT:=0
+ else ifeq (${LSI_CUT},11)
+ RCAR_LSI_CUT:=1
+ else
+ $(error "Error: ${LSI_CUT} is not supported.")
+ endif
+ $(eval $(call add_define,RCAR_LSI_CUT))
+ endif
+ else ifeq (${LSI},G2E)
+ RCAR_LSI:=${RZ_G2E}
+ ifndef LSI_CUT
+ # enable compatible function.
+ RCAR_LSI_CUT_COMPAT := 1
+ $(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
+ else
+ # disable compatible function.
+ ifeq (${LSI_CUT},10)
+ RCAR_LSI_CUT:=0
+ else ifeq (${LSI_CUT},11)
+ RCAR_LSI_CUT:=1
+ else
+ $(error "Error: ${LSI_CUT} is not supported.")
+ endif
+ $(eval $(call add_define,RCAR_LSI_CUT))
+ endif
else
$(error "Error: ${LSI} is not supported.")
endif
@@ -168,12 +217,15 @@
endif
$(eval $(call add_define,RCAR_SYSTEM_RESET_KEEPON_DDR))
-include drivers/renesas/rzg/ddr/ddr.mk
+RZG_SOC :=1
+$(eval $(call add_define,RZG_SOC))
+
+include drivers/renesas/common/ddr/ddr.mk
include drivers/renesas/rzg/qos/qos.mk
include drivers/renesas/rzg/pfc/pfc.mk
include lib/libfdt/libfdt.mk
-PLAT_INCLUDES += -Idrivers/renesas/rzg/ddr \
+PLAT_INCLUDES += -Idrivers/renesas/common/ddr \
-Idrivers/renesas/rzg/qos \
-Idrivers/renesas/rzg/board \
-Idrivers/renesas/common \
diff --git a/plat/rockchip/px30/platform.mk b/plat/rockchip/px30/platform.mk
index e2b4976..38db74d 100644
--- a/plat/rockchip/px30/platform.mk
+++ b/plat/rockchip/px30/platform.mk
@@ -4,6 +4,7 @@
#SPDX-License-Identifier: BSD-3-Clause
#
+include drivers/arm/gic/v2/gicv2.mk
RK_PLAT := plat/rockchip
RK_PLAT_SOC := ${RK_PLAT}/${PLAT}
@@ -24,9 +25,7 @@
-I${RK_PLAT_SOC}/drivers/soc/ \
-I${RK_PLAT_SOC}/include/
-RK_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v2/gicv2_main.c \
- drivers/arm/gic/v2/gicv2_helpers.c \
+RK_GIC_SOURCES := ${GICV2_SOURCES} \
plat/common/plat_gicv2.c \
plat/common/aarch64/crash_console_helpers.S \
${RK_PLAT}/common/rockchip_gicv2.c
diff --git a/plat/rockchip/rk3288/platform.mk b/plat/rockchip/rk3288/platform.mk
index 980fb6b..52e486d 100644
--- a/plat/rockchip/rk3288/platform.mk
+++ b/plat/rockchip/rk3288/platform.mk
@@ -4,6 +4,8 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+include drivers/arm/gic/v2/gicv2.mk
+
ARM_CORTEX_A12 := yes
ARM_ARCH_MAJOR := 7
@@ -24,9 +26,7 @@
-I${RK_PLAT_SOC}/include/ \
-I${RK_PLAT_SOC}/include/shared/ \
-RK_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v2/gicv2_main.c \
- drivers/arm/gic/v2/gicv2_helpers.c \
+RK_GIC_SOURCES := ${GICV2_SOURCES} \
plat/common/plat_gicv2.c \
${RK_PLAT}/common/rockchip_gicv2.c
diff --git a/plat/rockchip/rk3328/platform.mk b/plat/rockchip/rk3328/platform.mk
index bbf3519..e3838c4 100644
--- a/plat/rockchip/rk3328/platform.mk
+++ b/plat/rockchip/rk3328/platform.mk
@@ -4,6 +4,8 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+include drivers/arm/gic/v2/gicv2.mk
+
RK_PLAT := plat/rockchip
RK_PLAT_SOC := ${RK_PLAT}/${PLAT}
RK_PLAT_COMMON := ${RK_PLAT}/common
@@ -22,9 +24,7 @@
-I${RK_PLAT_SOC}/drivers/soc/ \
-I${RK_PLAT_SOC}/include/
-RK_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v2/gicv2_main.c \
- drivers/arm/gic/v2/gicv2_helpers.c \
+RK_GIC_SOURCES := ${GICV2_SOURCES} \
plat/common/plat_gicv2.c \
${RK_PLAT}/common/rockchip_gicv2.c
diff --git a/plat/rockchip/rk3368/platform.mk b/plat/rockchip/rk3368/platform.mk
index ce93c68..fadde40 100644
--- a/plat/rockchip/rk3368/platform.mk
+++ b/plat/rockchip/rk3368/platform.mk
@@ -4,6 +4,8 @@
# SPDX-License-Identifier: BSD-3-Clause
#
+include drivers/arm/gic/v2/gicv2.mk
+
RK_PLAT := plat/rockchip
RK_PLAT_SOC := ${RK_PLAT}/${PLAT}
RK_PLAT_COMMON := ${RK_PLAT}/common
@@ -20,9 +22,7 @@
-I${RK_PLAT_SOC}/drivers/ddr/ \
-I${RK_PLAT_SOC}/include/
-RK_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v2/gicv2_main.c \
- drivers/arm/gic/v2/gicv2_helpers.c \
+RK_GIC_SOURCES := ${GICV2_SOURCES} \
plat/common/plat_gicv2.c \
${RK_PLAT}/common/rockchip_gicv2.c
diff --git a/plat/rockchip/rk3399/drivers/dram/dram.h b/plat/rockchip/rk3399/drivers/dram/dram.h
index 0eb12cf..5572b16 100644
--- a/plat/rockchip/rk3399/drivers/dram/dram.h
+++ b/plat/rockchip/rk3399/drivers/dram/dram.h
@@ -149,7 +149,7 @@
uint32_t rx_cal_dqs[2][4];
};
-extern __sramdata struct rk3399_sdram_params sdram_config;
+extern struct rk3399_sdram_params sdram_config;
void dram_init(void);
diff --git a/plat/rockchip/rk3399/drivers/dram/suspend.c b/plat/rockchip/rk3399/drivers/dram/suspend.c
index 7f9fad1..a8b1c32 100644
--- a/plat/rockchip/rk3399/drivers/dram/suspend.c
+++ b/plat/rockchip/rk3399/drivers/dram/suspend.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -49,6 +49,7 @@
__pmusramdata uint32_t dpll_data[PLL_CON_COUNT];
__pmusramdata uint32_t cru_clksel_con6;
+__pmusramdata uint8_t pmu_enable_watchdog0;
/*
* Copy @num registers from @src to @dst
@@ -562,8 +563,14 @@
/* LPDDR4 f2 cann't do training, all training will fail */
for (ch = 0; ch < ch_count; ch++) {
- mmio_clrsetbits_32(PHY_REG(ch, 896), (0x3 << 8) | 1,
- fn << 8);
+ /*
+ * Without this disabled for LPDDR4 we end up writing 0's
+ * in place of real data in an interesting pattern.
+ */
+ if (sdram_params->dramtype != LPDDR4) {
+ mmio_clrsetbits_32(PHY_REG(ch, 896), (0x3 << 8) | 1,
+ fn << 8);
+ }
/* data_training failed */
if (data_training(ch, sdram_params, PI_FULL_TRAINING))
@@ -748,13 +755,44 @@
phy_regs->phy896[0] &= ~(0x3 << 8);
}
+__pmusramfunc void phy_dll_bypass_set(uint32_t ch, uint32_t freq)
+{
+ if (freq <= (125 * 1000 * 1000)) {
+ /* Set master mode to SW for slices*/
+ mmio_setbits_32(PHY_REG(ch, 86), 3 << 10);
+ mmio_setbits_32(PHY_REG(ch, 214), 3 << 10);
+ mmio_setbits_32(PHY_REG(ch, 342), 3 << 10);
+ mmio_setbits_32(PHY_REG(ch, 470), 3 << 10);
+ /* Set master mode to SW for address slices*/
+ mmio_setbits_32(PHY_REG(ch, 547), 3 << 18);
+ mmio_setbits_32(PHY_REG(ch, 675), 3 << 18);
+ mmio_setbits_32(PHY_REG(ch, 803), 3 << 18);
+ } else {
+ /* Clear SW master mode for slices*/
+ mmio_clrbits_32(PHY_REG(ch, 86), 3 << 10);
+ mmio_clrbits_32(PHY_REG(ch, 214), 3 << 10);
+ mmio_clrbits_32(PHY_REG(ch, 342), 3 << 10);
+ mmio_clrbits_32(PHY_REG(ch, 470), 3 << 10);
+ /* Clear SW master mode for address slices*/
+ mmio_clrbits_32(PHY_REG(ch, 547), 3 << 18);
+ mmio_clrbits_32(PHY_REG(ch, 675), 3 << 18);
+ mmio_clrbits_32(PHY_REG(ch, 803), 3 << 18);
+ }
+}
+
__pmusramfunc void dmc_resume(void)
{
struct rk3399_sdram_params *sdram_params = &sdram_config;
uint32_t channel_mask = 0;
uint32_t channel;
- pmusram_enable_watchdog();
+ /*
+ * We can't turn off the watchdog, so if we have not turned it on before
+ * we should not turn it on here.
+ */
+ if ((pmu_enable_watchdog0 & 0x1) == 0x1) {
+ pmusram_enable_watchdog();
+ }
pmu_sgrf_rst_hld_release();
restore_pmu_rsthold();
sram_secure_timer_init();
@@ -772,6 +810,13 @@
retry:
for (channel = 0; channel < sdram_params->num_channels; channel++) {
phy_pctrl_reset(channel);
+ /*
+ * Without this, LPDDR4 will write 0's in place of real data
+ * in a strange pattern.
+ */
+ if (sdram_params->dramtype == LPDDR4) {
+ phy_dll_bypass_set(channel, sdram_params->ddr_freq);
+ }
pctl_cfg(channel, sdram_params);
}
@@ -788,8 +833,12 @@
if (sdram_params->dramtype == LPDDR3)
sram_udelay(10);
- /* If traning fail, retry to do it again. */
- if (data_training(channel, sdram_params, PI_FULL_TRAINING))
+ /*
+ * Training here will always fail for LPDDR4, so skip it
+ * If traning fail, retry to do it again.
+ */
+ if (sdram_params->dramtype != LPDDR4 &&
+ data_training(channel, sdram_params, PI_FULL_TRAINING))
goto retry;
set_ddrconfig(sdram_params, channel,
diff --git a/plat/rockchip/rk3399/drivers/dram/suspend.h b/plat/rockchip/rk3399/drivers/dram/suspend.h
index b99a926..1389944 100644
--- a/plat/rockchip/rk3399/drivers/dram/suspend.h
+++ b/plat/rockchip/rk3399/drivers/dram/suspend.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,6 +7,7 @@
#ifndef SUSPEND_H
#define SUSPEND_H
+#include <stdint.h>
#include <dram.h>
#define KHz (1000)
@@ -22,5 +23,6 @@
void dmc_suspend(void);
__pmusramfunc void dmc_resume(void);
+extern __pmusramdata uint8_t pmu_enable_watchdog0;
#endif /* SUSPEND_H */
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
index faee678..3084c4f 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -1324,6 +1324,7 @@
store_wdt0[i] = mmio_read_32(WDT0_BASE + i * 4);
store_wdt1[i] = mmio_read_32(WDT1_BASE + i * 4);
}
+ pmu_enable_watchdog0 = (uint8_t) store_wdt0[0] & 0x1;
}
void wdt_register_restore(void)
diff --git a/plat/rpi/rpi4/include/rpi_hw.h b/plat/rpi/rpi4/include/rpi_hw.h
index 7185106..0430d46 100644
--- a/plat/rpi/rpi4/include/rpi_hw.h
+++ b/plat/rpi/rpi4/include/rpi_hw.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,14 +13,16 @@
* Peripherals
*/
-#define RPI_IO_BASE ULL(0xFE000000)
-#define RPI_IO_SIZE ULL(0x02000000)
+#define RPI_IO_BASE ULL(0xFC000000)
+#define RPI_IO_SIZE ULL(0x04000000)
+
+#define RPI_LEGACY_BASE (ULL(0x02000000) + RPI_IO_BASE)
/*
* ARM <-> VideoCore mailboxes
*/
#define RPI3_MBOX_OFFSET ULL(0x0000B880)
-#define RPI3_MBOX_BASE (RPI_IO_BASE + RPI3_MBOX_OFFSET)
+#define RPI3_MBOX_BASE (RPI_LEGACY_BASE + RPI3_MBOX_OFFSET)
/* VideoCore -> ARM */
#define RPI3_MBOX0_READ_OFFSET ULL(0x00000000)
#define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010)
@@ -41,7 +43,7 @@
* Power management, reset controller, watchdog.
*/
#define RPI3_IO_PM_OFFSET ULL(0x00100000)
-#define RPI3_PM_BASE (RPI_IO_BASE + RPI3_IO_PM_OFFSET)
+#define RPI3_PM_BASE (RPI_LEGACY_BASE + RPI3_IO_PM_OFFSET)
/* Registers on top of RPI3_PM_BASE. */
#define RPI3_PM_RSTC_OFFSET ULL(0x0000001C)
#define RPI3_PM_RSTS_OFFSET ULL(0x00000020)
@@ -62,7 +64,7 @@
* Hardware random number generator.
*/
#define RPI3_IO_RNG_OFFSET ULL(0x00104000)
-#define RPI3_RNG_BASE (RPI_IO_BASE + RPI3_IO_RNG_OFFSET)
+#define RPI3_RNG_BASE (RPI_LEGACY_BASE + RPI3_IO_RNG_OFFSET)
#define RPI3_RNG_CTRL_OFFSET ULL(0x00000000)
#define RPI3_RNG_STATUS_OFFSET ULL(0x00000004)
#define RPI3_RNG_DATA_OFFSET ULL(0x00000008)
@@ -82,22 +84,22 @@
* There is also a PL011 UART, multiplexed to the same pins.
*/
#define RPI4_IO_MINI_UART_OFFSET ULL(0x00215040)
-#define RPI4_MINI_UART_BASE (RPI_IO_BASE + RPI4_IO_MINI_UART_OFFSET)
+#define RPI4_MINI_UART_BASE (RPI_LEGACY_BASE + RPI4_IO_MINI_UART_OFFSET)
#define RPI4_IO_PL011_UART_OFFSET ULL(0x00201000)
-#define RPI4_PL011_UART_BASE (RPI_IO_BASE + RPI4_IO_PL011_UART_OFFSET)
+#define RPI4_PL011_UART_BASE (RPI_LEGACY_BASE + RPI4_IO_PL011_UART_OFFSET)
#define RPI4_PL011_UART_CLOCK ULL(48000000)
/*
* GPIO controller
*/
#define RPI3_IO_GPIO_OFFSET ULL(0x00200000)
-#define RPI3_GPIO_BASE (RPI_IO_BASE + RPI3_IO_GPIO_OFFSET)
+#define RPI3_GPIO_BASE (RPI_LEGACY_BASE + RPI3_IO_GPIO_OFFSET)
/*
* SDHost controller
*/
#define RPI3_IO_SDHOST_OFFSET ULL(0x00202000)
-#define RPI3_SDHOST_BASE (RPI_IO_BASE + RPI3_IO_SDHOST_OFFSET)
+#define RPI3_SDHOST_BASE (RPI_LEGACY_BASE + RPI3_IO_SDHOST_OFFSET)
/*
* GIC interrupt controller
diff --git a/plat/rpi/rpi4/platform.mk b/plat/rpi/rpi4/platform.mk
index 0744bce..528eb1d 100644
--- a/plat/rpi/rpi4/platform.mk
+++ b/plat/rpi/rpi4/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -7,6 +7,8 @@
include lib/libfdt/libfdt.mk
include lib/xlat_tables_v2/xlat_tables.mk
+include drivers/arm/gic/v2/gicv2.mk
+
PLAT_INCLUDES := -Iplat/rpi/common/include \
-Iplat/rpi/rpi4/include
@@ -18,9 +20,6 @@
BL31_SOURCES += lib/cpus/aarch64/cortex_a72.S \
plat/rpi/common/aarch64/plat_helpers.S \
plat/rpi/rpi4/aarch64/armstub8_header.S \
- drivers/arm/gic/common/gic_common.c \
- drivers/arm/gic/v2/gicv2_helpers.c \
- drivers/arm/gic/v2/gicv2_main.c \
drivers/delay_timer/delay_timer.c \
drivers/gpio/gpio.c \
drivers/rpi3/gpio/rpi3_gpio.c \
@@ -30,7 +29,8 @@
plat/common/plat_psci_common.c \
plat/rpi/common/rpi3_topology.c \
common/fdt_fixup.c \
- ${LIBFDT_SRCS}
+ ${LIBFDT_SRCS} \
+ ${GICV2_SOURCES}
# For now we only support BL31, using the kernel loaded by the GPU firmware.
RESET_TO_BL31 := 1
@@ -86,6 +86,9 @@
# Use normal memory mapping for ROM, FIP, SRAM and DRAM
RPI3_USE_UEFI_MAP := 0
+# SMCCC PCI support (should be enabled for ACPI builds)
+SMC_PCI_SUPPORT := 0
+
# Process platform flags
# ----------------------
@@ -96,6 +99,7 @@
endif
$(eval $(call add_define,RPI3_RUNTIME_UART))
$(eval $(call add_define,RPI3_USE_UEFI_MAP))
+$(eval $(call add_define,SMC_PCI_SUPPORT))
ifeq (${ARCH},aarch32)
$(error Error: AArch32 not supported on rpi4)
@@ -105,3 +109,8 @@
PLAT_BL_COMMON_SOURCES += drivers/rpi3/rng/rpi3_rng.c \
plat/rpi/common/rpi3_stack_protector.c
endif
+
+ifeq ($(SMC_PCI_SUPPORT), 1)
+BL31_SOURCES += plat/rpi/rpi4/rpi4_pci_svc.c
+endif
+
diff --git a/plat/rpi/rpi4/rpi4_bl31_setup.c b/plat/rpi/rpi4/rpi4_bl31_setup.c
index cfacd1f..5259859 100644
--- a/plat/rpi/rpi4/rpi4_bl31_setup.c
+++ b/plat/rpi/rpi4/rpi4_bl31_setup.c
@@ -201,6 +201,44 @@
enable_mmu_el3(0);
}
+/*
+ * Remove the FDT /memreserve/ entry that covers the region at the very
+ * beginning of memory (if that exists). This is where the secondaries
+ * originally spin, but we pull them out there.
+ * Having overlapping /reserved-memory and /memreserve/ regions confuses
+ * the Linux kernel, so we need to get rid of this one.
+ */
+static void remove_spintable_memreserve(void *dtb)
+{
+ uint64_t addr, size;
+ int regions = fdt_num_mem_rsv(dtb);
+ int i;
+
+ for (i = 0; i < regions; i++) {
+ if (fdt_get_mem_rsv(dtb, i, &addr, &size) != 0) {
+ return;
+ }
+ if (size == 0U) {
+ return;
+ }
+ /* We only look for the region at the beginning of DRAM. */
+ if (addr != 0U) {
+ continue;
+ }
+ /*
+ * Currently the region in the existing DTs is exactly 4K
+ * in size. Should this value ever change, there is probably
+ * a reason for that, so inform the user about this.
+ */
+ if (size == 4096U) {
+ fdt_del_mem_rsv(dtb, i);
+ return;
+ }
+ WARN("Keeping unknown /memreserve/ region at 0, size: %lld\n",
+ size);
+ }
+}
+
static void rpi4_prepare_dtb(void)
{
void *dtb = (void *)rpi4_get_dtb_address();
@@ -227,7 +265,11 @@
return;
}
- /* Reserve memory used by Trusted Firmware. */
+ /*
+ * Remove the original reserved region (used for the spintable), and
+ * replace it with a region describing the whole of Trusted Firmware.
+ */
+ remove_spintable_memreserve(dtb);
if (fdt_add_reserved_memory(dtb, "atf@0", 0, 0x80000))
WARN("Failed to add reserved memory nodes to DT.\n");
diff --git a/plat/rpi/rpi4/rpi4_pci_svc.c b/plat/rpi/rpi4/rpi4_pci_svc.c
new file mode 100644
index 0000000..7d1ca5c
--- /dev/null
+++ b/plat/rpi/rpi4/rpi4_pci_svc.c
@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * The RPi4 has a single nonstandard PCI config region. It is broken into two
+ * pieces, the root port config registers and a window to a single device's
+ * config space which can move between devices. There isn't (yet) an
+ * authoritative public document on this since the available BCM2711 reference
+ * notes that there is a PCIe root port in the memory map but doesn't describe
+ * it. Given that it's not ECAM compliant yet reasonably simple, it makes for
+ * an excellent example of the PCI SMCCC interface.
+ *
+ * The PCI SMCCC interface is described in DEN0115 availabe from:
+ * https://developer.arm.com/documentation/den0115/latest
+ */
+
+#include <assert.h>
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <common/runtime_svc.h>
+#include <lib/pmf/pmf.h>
+#include <lib/runtime_instr.h>
+#include <services/pci_svc.h>
+#include <services/sdei.h>
+#include <services/std_svc.h>
+#include <smccc_helpers.h>
+
+#include <lib/mmio.h>
+
+static spinlock_t pci_lock;
+
+#define PCIE_REG_BASE U(RPI_IO_BASE + 0x01500000)
+#define PCIE_MISC_PCIE_STATUS 0x4068
+#define PCIE_EXT_CFG_INDEX 0x9000
+/* A small window pointing at the ECAM of the device selected by CFG_INDEX */
+#define PCIE_EXT_CFG_DATA 0x8000
+#define INVALID_PCI_ADDR 0xFFFFFFFF
+
+#define PCIE_EXT_BUS_SHIFT 20
+#define PCIE_EXT_DEV_SHIFT 15
+#define PCIE_EXT_FUN_SHIFT 12
+
+
+static uint64_t pci_segment_lib_get_base(uint32_t address, uint32_t offset)
+{
+ uint64_t base;
+ uint32_t bus, dev, fun;
+ uint32_t status;
+
+ base = PCIE_REG_BASE;
+
+ offset &= PCI_OFFSET_MASK; /* Pick off the 4k register offset */
+
+ /* The root port is at the base of the PCIe register space */
+ if (address != 0U) {
+ /*
+ * The current device must be at CFG_DATA, a 4K window mapped,
+ * via CFG_INDEX, to the device we are accessing. At the same
+ * time we must avoid accesses to certain areas of the cfg
+ * space via CFG_DATA. Detect those accesses and report that
+ * the address is invalid.
+ */
+ base += PCIE_EXT_CFG_DATA;
+ bus = PCI_ADDR_BUS(address);
+ dev = PCI_ADDR_DEV(address);
+ fun = PCI_ADDR_FUN(address);
+ address = (bus << PCIE_EXT_BUS_SHIFT) |
+ (dev << PCIE_EXT_DEV_SHIFT) |
+ (fun << PCIE_EXT_FUN_SHIFT);
+
+ /* Allow only dev = 0 on root port and bus 1 */
+ if ((bus < 2U) && (dev > 0U)) {
+ return INVALID_PCI_ADDR;
+ }
+
+ /* Assure link up before reading bus 1 */
+ status = mmio_read_32(PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
+ if ((status & 0x30) != 0x30) {
+ return INVALID_PCI_ADDR;
+ }
+
+ /* Adjust which device the CFG_DATA window is pointing at */
+ mmio_write_32(PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, address);
+ }
+ return base + offset;
+}
+
+/**
+ * pci_read_config() - Performs a config space read at addr
+ * @addr: 32-bit, segment, BDF of requested function encoded per DEN0115
+ * @off: register offset of function described by @addr to read
+ * @sz: size of read (8,16,32) bits.
+ * @val: returned zero extended value read from config space
+ *
+ * sz bits of PCI config space is read at addr:offset, and the value
+ * is returned in val. Invalid segment/offset values return failure.
+ * Reads to valid functions that don't exist return INVALID_PCI_ADDR
+ * as is specified by PCI for requests that aren't completed by EPs.
+ * The boilerplate in pci_svc.c tends to do basic segment, off
+ * and sz validation. This routine should avoid duplicating those
+ * checks.
+ *
+ * This function maps directly to the PCI_READ function in DEN0115
+ * where detailed requirements may be found.
+ *
+ * Return: SMC_PCI_CALL_SUCCESS with val set
+ * SMC_PCI_CALL_INVAL_PARAM, on parameter error
+ */
+uint32_t pci_read_config(uint32_t addr, uint32_t off, uint32_t sz, uint32_t *val)
+{
+ uint32_t ret = SMC_PCI_CALL_SUCCESS;
+ uint64_t base;
+
+ spin_lock(&pci_lock);
+ base = pci_segment_lib_get_base(addr, off);
+
+ if (base == INVALID_PCI_ADDR) {
+ *val = base;
+ } else {
+ switch (sz) {
+ case SMC_PCI_SZ_8BIT:
+ *val = mmio_read_8(base);
+ break;
+ case SMC_PCI_SZ_16BIT:
+ *val = mmio_read_16(base);
+ break;
+ case SMC_PCI_SZ_32BIT:
+ *val = mmio_read_32(base);
+ break;
+ default: /* should be unreachable */
+ *val = 0;
+ ret = SMC_PCI_CALL_INVAL_PARAM;
+ }
+ }
+ spin_unlock(&pci_lock);
+ return ret;
+}
+
+/**
+ * pci_write_config() - Performs a config space write at addr
+ * @addr: 32-bit, segment, BDF of requested function encoded per DEN0115
+ * @off: register offset of function described by @addr to write
+ * @sz: size of write (8,16,32) bits.
+ * @val: value to be written
+ *
+ * sz bits of PCI config space is written at addr:offset. Invalid
+ * segment/BDF values return failure. Writes to valid functions
+ * without valid EPs are ignored, as is specified by PCI.
+ * The boilerplate in pci_svc.c tends to do basic segment, off
+ * and sz validation, so it shouldn't need to be repeated here.
+ *
+ * This function maps directly to the PCI_WRITE function in DEN0115
+ * where detailed requirements may be found.
+ *
+ * Return: SMC_PCI_CALL_SUCCESS
+ * SMC_PCI_CALL_INVAL_PARAM, on parameter error
+ */
+uint32_t pci_write_config(uint32_t addr, uint32_t off, uint32_t sz, uint32_t val)
+{
+ uint32_t ret = SMC_PCI_CALL_SUCCESS;
+ uint64_t base;
+
+ spin_lock(&pci_lock);
+ base = pci_segment_lib_get_base(addr, off);
+
+ if (base != INVALID_PCI_ADDR) {
+ switch (sz) {
+ case SMC_PCI_SZ_8BIT:
+ mmio_write_8(base, val);
+ break;
+ case SMC_PCI_SZ_16BIT:
+ mmio_write_16(base, val);
+ break;
+ case SMC_PCI_SZ_32BIT:
+ mmio_write_32(base, val);
+ break;
+ default: /* should be unreachable */
+ ret = SMC_PCI_CALL_INVAL_PARAM;
+ }
+ }
+ spin_unlock(&pci_lock);
+ return ret;
+}
+
+/**
+ * pci_get_bus_for_seg() - returns the start->end bus range for a segment
+ * @seg: segment being queried
+ * @bus_range: returned bus begin + (end << 8)
+ * @nseg: returns next segment in this machine or 0 for end
+ *
+ * pci_get_bus_for_seg is called to check if a given segment is
+ * valid on this machine. If it is valid, then its bus ranges are
+ * returned along with the next valid segment on the machine. If
+ * this is the last segment, then nseg must be 0.
+ *
+ * This function maps directly to the PCI_GET_SEG_INFO function
+ * in DEN0115 where detailed requirements may be found.
+ *
+ * Return: SMC_PCI_CALL_SUCCESS, and appropriate bus_range and nseg
+ * SMC_PCI_CALL_NOT_IMPL, if the segment is invalid
+ */
+uint32_t pci_get_bus_for_seg(uint32_t seg, uint32_t *bus_range, uint32_t *nseg)
+{
+ uint32_t ret = SMC_PCI_CALL_SUCCESS;
+ *nseg = 0U; /* only a single segment */
+ if (seg == 0U) {
+ *bus_range = 0xFF00; /* start 0, end 255 */
+ } else {
+ *bus_range = 0U;
+ ret = SMC_PCI_CALL_NOT_IMPL;
+ }
+ return ret;
+}
diff --git a/plat/ti/k3/board/generic/include/board_def.h b/plat/ti/k3/board/generic/include/board_def.h
index 0d45116..4ff687c 100644
--- a/plat/ti/k3/board/generic/include/board_def.h
+++ b/plat/ti/k3/board/generic/include/board_def.h
@@ -18,15 +18,26 @@
/*
* This RAM will be used for the bootloader including code, bss, and stacks.
* It may need to be increased if BL31 grows in size.
+ *
+ * The link addresses are determined by SEC_SRAM_BASE + offset.
+ * When ENABLE_PIE is set, the TF images can be loaded anywhere, so
+ * SEC_SRAM_BASE is really arbitrary.
+ *
+ * When ENABLE_PIE is unset, SEC_SRAM_BASE should be chosen so that
+ * it matches to the physical address where BL31 is loaded, that is,
+ * SEC_SRAM_BASE should be the base address of the RAM region.
+ *
+ * Lets make things explicit by mapping SRAM_BASE to 0x0 since ENABLE_PIE is
+ * defined as default for our platform.
*/
-#define SEC_SRAM_BASE 0x70000000 /* Base of MSMC SRAM */
-#define SEC_SRAM_SIZE 0x00020000 /* 128k */
+#define SEC_SRAM_BASE UL(0x00000000) /* PIE remapped on fly */
+#define SEC_SRAM_SIZE UL(0x00020000) /* 128k */
#define PLAT_MAX_OFF_STATE U(2)
#define PLAT_MAX_RET_STATE U(1)
-#define PLAT_PROC_START_ID 32
-#define PLAT_PROC_DEVICE_START_ID 202
-#define PLAT_CLUSTER_DEVICE_START_ID 198
+#define PLAT_PROC_START_ID U(32)
+#define PLAT_PROC_DEVICE_START_ID U(202)
+#define PLAT_CLUSTER_DEVICE_START_ID U(198)
#endif /* BOARD_DEF_H */
diff --git a/plat/ti/k3/board/lite/include/board_def.h b/plat/ti/k3/board/lite/include/board_def.h
index 7c7ea62..18b7f42 100644
--- a/plat/ti/k3/board/lite/include/board_def.h
+++ b/plat/ti/k3/board/lite/include/board_def.h
@@ -20,15 +20,26 @@
* It may need to be increased if BL31 grows in size.
* Current computation assumes data structures necessary for GIC and ARM for
* a single cluster of 4 processor.
+ *
+ * The link addresses are determined by SEC_SRAM_BASE + offset.
+ * When ENABLE_PIE is set, the TF images can be loaded anywhere, so
+ * SEC_SRAM_BASE is really arbitrary.
+ *
+ * When ENABLE_PIE is unset, SEC_SRAM_BASE should be chosen so that
+ * it matches to the physical address where BL31 is loaded, that is,
+ * SEC_SRAM_BASE should be the base address of the RAM region.
+ *
+ * Lets make things explicit by mapping SRAM_BASE to 0x0 since ENABLE_PIE is
+ * defined as default for our platform.
*/
-#define SEC_SRAM_BASE 0x70000000 /* Base of SRAM */
-#define SEC_SRAM_SIZE 0x0001a000 /* 104k */
+#define SEC_SRAM_BASE UL(0x00000000) /* PIE remapped on fly */
+#define SEC_SRAM_SIZE UL(0x0001c000) /* 112k */
#define PLAT_MAX_OFF_STATE U(2)
#define PLAT_MAX_RET_STATE U(1)
-#define PLAT_PROC_START_ID 32
-#define PLAT_PROC_DEVICE_START_ID 135
-#define PLAT_CLUSTER_DEVICE_START_ID 134
+#define PLAT_PROC_START_ID U(32)
+#define PLAT_PROC_DEVICE_START_ID U(135)
+#define PLAT_CLUSTER_DEVICE_START_ID U(134)
#endif /* BOARD_DEF_H */
diff --git a/plat/ti/k3/common/k3_bl31_setup.c b/plat/ti/k3/common/k3_bl31_setup.c
index ac4e60e..457c95d 100644
--- a/plat/ti/k3/common/k3_bl31_setup.c
+++ b/plat/ti/k3/common/k3_bl31_setup.c
@@ -101,7 +101,7 @@
void bl31_plat_arch_setup(void)
{
const mmap_region_t bl_regions[] = {
- MAP_REGION_FLAT(BL31_START, BL31_END - BL31_START, MT_MEMORY | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE),
MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_CODE | MT_RO | MT_SECURE),
MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, MT_RO_DATA | MT_RO | MT_SECURE),
#if USE_COHERENT_MEM
diff --git a/plat/ti/k3/include/platform_def.h b/plat/ti/k3/include/platform_def.h
index f12fb0b..81a383a 100644
--- a/plat/ti/k3/include/platform_def.h
+++ b/plat/ti/k3/include/platform_def.h
@@ -60,7 +60,11 @@
* used, choose the smallest value needed to map the required virtual addresses
* for each BL stage.
*/
-#define MAX_XLAT_TABLES 8
+#if USE_COHERENT_MEM
+#define MAX_XLAT_TABLES 10
+#else
+#define MAX_XLAT_TABLES 9
+#endif
/*
* Defines the maximum number of regions that are allocated by the translation
diff --git a/plat/xilinx/common/include/pm_common.h b/plat/xilinx/common/include/pm_common.h
index c0a51f0..0c24a36 100644
--- a/plat/xilinx/common/include/pm_common.h
+++ b/plat/xilinx/common/include/pm_common.h
@@ -15,6 +15,18 @@
#include <stdint.h>
#include <plat_pm_common.h>
+#if IPI_CRC_CHECK
+#define PAYLOAD_ARG_CNT 8U
+#define IPI_W0_TO_W6_SIZE 28U
+#define PAYLOAD_CRC_POS 7U
+#define CRC_INIT_VALUE 0x4F4EU
+#define CRC_ORDER 16U
+#define CRC_POLYNOM 0x8005U
+#else
+#define PAYLOAD_ARG_CNT 6U
+#endif
+#define PAYLOAD_ARG_SIZE 4U /* size in bytes */
+
/**
* pm_ipi - struct for capturing IPI-channel specific info
* @local_ipi_id Local IPI agent ID
diff --git a/plat/xilinx/common/include/pm_ipi.h b/plat/xilinx/common/include/pm_ipi.h
index 7bcf596..8c7738d 100644
--- a/plat/xilinx/common/include/pm_ipi.h
+++ b/plat/xilinx/common/include/pm_ipi.h
@@ -26,7 +26,7 @@
void pm_ipi_irq_enable(const struct pm_proc *proc);
void pm_ipi_irq_clear(const struct pm_proc *proc);
uint32_t pm_ipi_irq_status(const struct pm_proc *proc);
-#if ZYNQMP_IPI_CRC_CHECK
+#if IPI_CRC_CHECK
uint32_t calculate_crc(uint32_t payload[PAYLOAD_ARG_CNT], uint32_t buffersize);
#endif
diff --git a/plat/xilinx/common/pm_service/pm_ipi.c b/plat/xilinx/common/pm_service/pm_ipi.c
index 5dcceae..7b2c8ec 100644
--- a/plat/xilinx/common/pm_service/pm_ipi.c
+++ b/plat/xilinx/common/pm_service/pm_ipi.c
@@ -59,7 +59,7 @@
uintptr_t buffer_base = proc->ipi->buffer_base +
IPI_BUFFER_TARGET_REMOTE_OFFSET +
IPI_BUFFER_REQ_OFFSET;
-#if ZYNQMP_IPI_CRC_CHECK
+#if IPI_CRC_CHECK
payload[PAYLOAD_CRC_POS] = calculate_crc(payload, IPI_W0_TO_W6_SIZE);
#endif
@@ -137,7 +137,7 @@
unsigned int *value, size_t count)
{
size_t i;
-#if ZYNQMP_IPI_CRC_CHECK
+#if IPI_CRC_CHECK
size_t j;
unsigned int response_payload[PAYLOAD_ARG_CNT];
#endif
@@ -156,7 +156,7 @@
*value = mmio_read_32(buffer_base + (i * PAYLOAD_ARG_SIZE));
value++;
}
-#if ZYNQMP_IPI_CRC_CHECK
+#if IPI_CRC_CHECK
for (j = 0; j < PAYLOAD_ARG_CNT; j++)
response_payload[j] = mmio_read_32(buffer_base +
(j * PAYLOAD_ARG_SIZE));
@@ -181,7 +181,7 @@
void pm_ipi_buff_read_callb(unsigned int *value, size_t count)
{
size_t i;
-#if ZYNQMP_IPI_CRC_CHECK
+#if IPI_CRC_CHECK
size_t j;
unsigned int response_payload[PAYLOAD_ARG_CNT];
#endif
@@ -196,7 +196,7 @@
*value = mmio_read_32(buffer_base + (i * PAYLOAD_ARG_SIZE));
value++;
}
-#if ZYNQMP_IPI_CRC_CHECK
+#if IPI_CRC_CHECK
for (j = 0; j < PAYLOAD_ARG_CNT; j++)
response_payload[j] = mmio_read_32(buffer_base +
(j * PAYLOAD_ARG_SIZE));
@@ -262,7 +262,7 @@
return 0;
}
-#if ZYNQMP_IPI_CRC_CHECK
+#if IPI_CRC_CHECK
uint32_t calculate_crc(uint32_t *payload, uint32_t bufsize)
{
uint32_t crcinit = CRC_INIT_VALUE;
diff --git a/plat/xilinx/versal/bl31_versal_setup.c b/plat/xilinx/versal/bl31_versal_setup.c
index 5e870ff..8b8714c 100644
--- a/plat/xilinx/versal/bl31_versal_setup.c
+++ b/plat/xilinx/versal/bl31_versal_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,6 +11,7 @@
#include <bl31/bl31.h>
#include <common/bl_common.h>
#include <common/debug.h>
+#include <drivers/arm/dcc.h>
#include <drivers/arm/pl011.h>
#include <drivers/console.h>
#include <lib/mmio.h>
@@ -22,7 +23,6 @@
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
-static console_t versal_runtime_console;
/*
* Return a pointer to the 'entry_point_info' structure of the next image for
@@ -64,18 +64,26 @@
{
uint64_t atf_handoff_addr;
- /* Initialize the console to provide early debug support */
- int rc = console_pl011_register(VERSAL_UART_BASE,
- VERSAL_UART_CLOCK,
- VERSAL_UART_BAUDRATE,
- &versal_runtime_console);
- if (rc == 0) {
- panic();
+ if (VERSAL_CONSOLE_IS(pl011)) {
+ static console_t versal_runtime_console;
+ /* Initialize the console to provide early debug support */
+ int rc = console_pl011_register(VERSAL_UART_BASE,
+ VERSAL_UART_CLOCK,
+ VERSAL_UART_BAUDRATE,
+ &versal_runtime_console);
+ if (rc == 0) {
+ panic();
+ }
+
+ console_set_scope(&versal_runtime_console, CONSOLE_FLAG_BOOT |
+ CONSOLE_FLAG_RUNTIME);
+ } else if (VERSAL_CONSOLE_IS(dcc)) {
+ /* Initialize the dcc console for debug */
+ int rc = console_dcc_register();
+ if (rc == 0) {
+ panic();
+ }
}
-
- console_set_scope(&versal_runtime_console, CONSOLE_FLAG_BOOT |
- CONSOLE_FLAG_RUNTIME);
-
/* Initialize the platform config for future decision making */
versal_config_setup();
/* There are no parameters from BL2 if BL31 is a reset vector */
@@ -109,6 +117,40 @@
NOTICE("BL31: Non secure code at 0x%lx\n", bl33_image_ep_info.pc);
}
+static interrupt_type_handler_t type_el3_interrupt_handler;
+
+int request_intr_type_el3(uint32_t id, interrupt_type_handler_t handler)
+{
+ /* Validate 'handler'*/
+ if (!handler) {
+ return -EINVAL;
+ }
+
+ type_el3_interrupt_handler = handler;
+
+ return 0;
+}
+
+static uint64_t rdo_el3_interrupt_handler(uint32_t id, uint32_t flags,
+ void *handle, void *cookie)
+{
+ uint32_t intr_id;
+ interrupt_type_handler_t handler;
+
+ intr_id = plat_ic_get_pending_interrupt_id();
+ /* Currently we support one interrupt */
+ if (intr_id != PLAT_VERSAL_IPI_IRQ) {
+ WARN("Unexpected interrupt call: 0x%x\n", intr_id);
+ return 0;
+ }
+
+ handler = type_el3_interrupt_handler;
+ if (handler) {
+ return handler(intr_id, flags, handle, cookie);
+ }
+
+ return 0;
+}
void bl31_platform_setup(void)
{
/* Initialize the gic cpu and distributor interfaces */
@@ -118,6 +160,15 @@
void bl31_plat_runtime_setup(void)
{
+ uint64_t flags = 0;
+ uint64_t rc;
+
+ set_interrupt_rm_flag(flags, NON_SECURE);
+ rc = register_interrupt_type_handler(INTR_TYPE_EL3,
+ rdo_el3_interrupt_handler, flags);
+ if (rc) {
+ panic();
+ }
}
/*
diff --git a/plat/xilinx/versal/include/plat_ipi.h b/plat/xilinx/versal/include/plat_ipi.h
index 6b08f32..36a4380 100644
--- a/plat/xilinx/versal/include/plat_ipi.h
+++ b/plat/xilinx/versal/include/plat_ipi.h
@@ -31,7 +31,7 @@
#define IPI_BUFFER_APU_BASE (IPI_BUFFER_BASEADDR + 0x400U)
#define IPI_BUFFER_PMC_BASE (IPI_BUFFER_BASEADDR + 0x200U)
-#define IPI_BUFFER_TARGET_APU_OFFSET 0x0U
+#define IPI_BUFFER_TARGET_APU_OFFSET 0x80U
#define IPI_BUFFER_TARGET_PMC_OFFSET 0x40U
#define IPI_BUFFER_LOCAL_BASE IPI_BUFFER_APU_BASE
diff --git a/plat/xilinx/versal/include/plat_pm_common.h b/plat/xilinx/versal/include/plat_pm_common.h
index 2d00801..22c9d11 100644
--- a/plat/xilinx/versal/include/plat_pm_common.h
+++ b/plat/xilinx/versal/include/plat_pm_common.h
@@ -16,8 +16,8 @@
#include <stdint.h>
#include "pm_defs.h"
-#define PAYLOAD_ARG_CNT 6U
-#define PAYLOAD_ARG_SIZE 4U /* size in bytes */
+#define NON_SECURE_FLAG 1U
+#define SECURE_FLAG 0U
#define VERSAL_TZ_VERSION_MAJOR 1
#define VERSAL_TZ_VERSION_MINOR 0
diff --git a/plat/xilinx/versal/include/plat_private.h b/plat/xilinx/versal/include/plat_private.h
index e302096..d12d13a 100644
--- a/plat/xilinx/versal/include/plat_private.h
+++ b/plat/xilinx/versal/include/plat_private.h
@@ -8,6 +8,7 @@
#define PLAT_PRIVATE_H
#include <lib/xlat_tables/xlat_tables.h>
+#include <bl31/interrupt_mgmt.h>
void versal_config_setup(void);
@@ -22,5 +23,10 @@
void plat_versal_gic_resume(void);
unsigned int versal_calc_core_pos(u_register_t mpidr);
+/*
+ * Register handler to specific GIC entrance
+ * for INTR_TYPE_EL3 type of interrupt
+ */
+int request_intr_type_el3(uint32_t irq, interrupt_type_handler_t fiq_handler);
#endif /* PLAT_PRIVATE_H */
diff --git a/plat/xilinx/versal/include/platform_def.h b/plat/xilinx/versal/include/platform_def.h
index 4cdaea2..8b513ef 100644
--- a/plat/xilinx/versal/include/platform_def.h
+++ b/plat/xilinx/versal/include/platform_def.h
@@ -91,11 +91,14 @@
*/
#define PLAT_VERSAL_G1S_IRQS VERSAL_IRQ_SEC_PHY_TIMER
#define PLAT_VERSAL_G0_IRQS VERSAL_IRQ_SEC_PHY_TIMER
+#define PLAT_VERSAL_IPI_IRQ 62
#define PLAT_VERSAL_G1S_IRQ_PROPS(grp) \
INTR_PROP_DESC(VERSAL_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_LEVEL)
-#define PLAT_VERSAL_G0_IRQ_PROPS(grp)
+#define PLAT_VERSAL_G0_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(PLAT_VERSAL_IPI_IRQ, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
#endif /* PLATFORM_DEF_H */
diff --git a/plat/xilinx/versal/include/versal_def.h b/plat/xilinx/versal/include/versal_def.h
index 810e5d8..001fb04 100644
--- a/plat/xilinx/versal/include/versal_def.h
+++ b/plat/xilinx/versal/include/versal_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -67,7 +67,7 @@
#define VERSAL_UART0_BASE 0xFF000000
#define VERSAL_UART1_BASE 0xFF010000
-#if VERSAL_CONSOLE_IS(pl011)
+#if VERSAL_CONSOLE_IS(pl011) || VERSAL_CONSOLE_IS(dcc)
# define VERSAL_UART_BASE VERSAL_UART0_BASE
#elif VERSAL_CONSOLE_IS(pl011_1)
# define VERSAL_UART_BASE VERSAL_UART1_BASE
diff --git a/plat/xilinx/versal/plat_psci.c b/plat/xilinx/versal/plat_psci.c
index fda42df..fa0284c 100644
--- a/plat/xilinx/versal/plat_psci.c
+++ b/plat/xilinx/versal/plat_psci.c
@@ -33,7 +33,7 @@
/* Send request to PMC to wake up selected ACPU core */
pm_req_wakeup(proc->node_id, (versal_sec_entry & 0xFFFFFFFF) | 0x1,
- versal_sec_entry >> 32, 0);
+ versal_sec_entry >> 32, 0, SECURE_FLAG);
/* Clear power down request */
pm_client_wakeup(proc);
@@ -67,7 +67,8 @@
PM_STATE_SUSPEND_TO_RAM : PM_STATE_CPU_IDLE;
/* Send request to PMC to suspend this core */
- pm_self_suspend(proc->node_id, MAX_LATENCY, state, versal_sec_entry);
+ pm_self_suspend(proc->node_id, MAX_LATENCY, state, versal_sec_entry,
+ SECURE_FLAG);
/* APU is to be turned off */
if (target_state->pwr_domain_state[1] > PLAT_MAX_RET_STATE) {
@@ -123,7 +124,7 @@
{
/* Send the power down request to the PMC */
pm_system_shutdown(XPM_SHUTDOWN_TYPE_SHUTDOWN,
- pm_get_shutdown_scope());
+ pm_get_shutdown_scope(), SECURE_FLAG);
while (1)
wfi();
@@ -137,7 +138,7 @@
{
/* Send the system reset request to the PMC */
pm_system_shutdown(XPM_SHUTDOWN_TYPE_RESET,
- pm_get_shutdown_scope());
+ pm_get_shutdown_scope(), SECURE_FLAG);
while (1)
wfi();
@@ -168,7 +169,8 @@
* invoking CPU_on function, during which resume address will
* be set.
*/
- pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0);
+ pm_self_suspend(proc->node_id, MAX_LATENCY, PM_STATE_CPU_IDLE, 0,
+ SECURE_FLAG);
}
/**
diff --git a/plat/xilinx/versal/platform.mk b/plat/xilinx/versal/platform.mk
index 16396dc..a8b2c94 100644
--- a/plat/xilinx/versal/platform.mk
+++ b/plat/xilinx/versal/platform.mk
@@ -1,4 +1,4 @@
-# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
@@ -8,6 +8,8 @@
SEPARATE_CODE_AND_RODATA := 1
override RESET_TO_BL31 := 1
PL011_GENERIC_UART := 1
+IPI_CRC_CHECK := 0
+HARDEN_SLS_ALL := 0
ifdef VERSAL_ATF_MEM_BASE
$(eval $(call add_define,VERSAL_ATF_MEM_BASE))
@@ -31,12 +33,13 @@
$(eval $(call add_define,VERSAL_BL32_MEM_SIZE))
endif
+ifdef IPI_CRC_CHECK
+ $(eval $(call add_define,IPI_CRC_CHECK))
+endif
+
VERSAL_PLATFORM ?= silicon
$(eval $(call add_define_val,VERSAL_PLATFORM,VERSAL_PLATFORM_ID_${VERSAL_PLATFORM}))
-VERSAL_CONSOLE ?= pl011
-$(eval $(call add_define_val,VERSAL_CONSOLE,VERSAL_CONSOLE_ID_${VERSAL_CONSOLE}))
-
PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
-Iplat/xilinx/common/include/ \
-Iplat/xilinx/common/ipi_mailbox_service/ \
@@ -48,6 +51,7 @@
PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
lib/xlat_tables/aarch64/xlat_tables.c \
+ drivers/arm/dcc/dcc_console.c \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
${GICV3_SOURCES} \
@@ -59,8 +63,15 @@
plat/xilinx/versal/aarch64/versal_helpers.S \
plat/xilinx/versal/aarch64/versal_common.c
+VERSAL_CONSOLE ?= pl011
+ifeq (${VERSAL_CONSOLE}, $(filter ${VERSAL_CONSOLE},pl011 pl011_0 pl011_1 dcc))
+else
+ $(error "Please define VERSAL_CONSOLE")
+endif
+
+$(eval $(call add_define_val,VERSAL_CONSOLE,VERSAL_CONSOLE_ID_${VERSAL_CONSOLE}))
+
BL31_SOURCES += drivers/arm/cci/cci.c \
- lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a72.S \
plat/common/plat_psci_common.c \
plat/xilinx/common/ipi.c \
@@ -77,3 +88,7 @@
plat/xilinx/versal/pm_service/pm_svc_main.c \
plat/xilinx/versal/pm_service/pm_api_sys.c \
plat/xilinx/versal/pm_service/pm_client.c
+
+ifeq ($(HARDEN_SLS_ALL), 1)
+TF_CFLAGS_aarch64 += -mharden-sls=all
+endif
diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.c b/plat/xilinx/versal/pm_service/pm_api_sys.c
index 3cdd9d0..912835a 100644
--- a/plat/xilinx/versal/pm_service/pm_api_sys.c
+++ b/plat/xilinx/versal/pm_service/pm_api_sys.c
@@ -15,6 +15,8 @@
#include "pm_api_sys.h"
#include "pm_client.h"
#include "pm_defs.h"
+#include "pm_svc_main.h"
+#include "../drivers/arm/gic/v3/gicv3_private.h"
/*********************************************************************
* Target module IDs macros
@@ -22,6 +24,7 @@
#define LIBPM_MODULE_ID 0x2
#define LOADER_MODULE_ID 0x7
+#define MODE 0x80000000
/* default shutdown/reboot scope is system(2) */
static unsigned int pm_shutdown_scope = XPM_SHUTDOWN_SUBTYPE_RST_SYSTEM;
@@ -38,33 +41,33 @@
/**
* Assigning of argument values into array elements.
*/
-#define PM_PACK_PAYLOAD1(pl, mid, arg0) { \
- pl[0] = (uint32_t)((uint32_t)((arg0) & 0xFF) | (mid << 8)); \
+#define PM_PACK_PAYLOAD1(pl, mid, flag, arg0) { \
+ pl[0] = (uint32_t)((uint32_t)((arg0) & 0xFF) | (mid << 8) | ((flag) << 24)); \
}
-#define PM_PACK_PAYLOAD2(pl, mid, arg0, arg1) { \
- pl[1] = (uint32_t)(arg1); \
- PM_PACK_PAYLOAD1(pl, mid, arg0); \
+#define PM_PACK_PAYLOAD2(pl, mid, flag, arg0, arg1) { \
+ pl[1] = (uint32_t)(arg1); \
+ PM_PACK_PAYLOAD1(pl, mid, flag, arg0); \
}
-#define PM_PACK_PAYLOAD3(pl, mid, arg0, arg1, arg2) { \
- pl[2] = (uint32_t)(arg2); \
- PM_PACK_PAYLOAD2(pl, mid, arg0, arg1); \
+#define PM_PACK_PAYLOAD3(pl, mid, flag, arg0, arg1, arg2) { \
+ pl[2] = (uint32_t)(arg2); \
+ PM_PACK_PAYLOAD2(pl, mid, flag, arg0, arg1); \
}
-#define PM_PACK_PAYLOAD4(pl, mid, arg0, arg1, arg2, arg3) { \
- pl[3] = (uint32_t)(arg3); \
- PM_PACK_PAYLOAD3(pl, mid, arg0, arg1, arg2); \
+#define PM_PACK_PAYLOAD4(pl, mid, flag, arg0, arg1, arg2, arg3) { \
+ pl[3] = (uint32_t)(arg3); \
+ PM_PACK_PAYLOAD3(pl, mid, flag, arg0, arg1, arg2); \
}
-#define PM_PACK_PAYLOAD5(pl, mid, arg0, arg1, arg2, arg3, arg4) { \
+#define PM_PACK_PAYLOAD5(pl, mid, flag, arg0, arg1, arg2, arg3, arg4) { \
pl[4] = (uint32_t)(arg4); \
- PM_PACK_PAYLOAD4(pl, mid, arg0, arg1, arg2, arg3); \
+ PM_PACK_PAYLOAD4(pl, mid, flag, arg0, arg1, arg2, arg3); \
}
-#define PM_PACK_PAYLOAD6(pl, mid, arg0, arg1, arg2, arg3, arg4, arg5) { \
- pl[5] = (uint32_t)(arg5); \
- PM_PACK_PAYLOAD5(pl, mid, arg0, arg1, arg2, arg3, arg4); \
+#define PM_PACK_PAYLOAD6(pl, mid, flag, arg0, arg1, arg2, arg3, arg4, arg5) { \
+ pl[5] = (uint32_t)(arg5); \
+ PM_PACK_PAYLOAD5(pl, mid, flag, arg0, arg1, arg2, arg3, arg4); \
}
/* PM API functions */
@@ -72,15 +75,17 @@
/**
* pm_get_api_version() - Get version number of PMC PM firmware
* @version Returns 32-bit version number of PMC Power Management Firmware
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_get_api_version(unsigned int *version)
+enum pm_ret_status pm_get_api_version(unsigned int *version, uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD1(payload, LIBPM_MODULE_ID, PM_GET_API_VERSION);
+ PM_PACK_PAYLOAD1(payload, LIBPM_MODULE_ID, flag, PM_GET_API_VERSION);
return pm_ipi_send_sync(primary_proc, payload, version, 1);
}
@@ -88,15 +93,17 @@
* pm_init_finalize() - Call to notify PMC PM firmware that master has power
* management enabled and that it has finished its
* initialization
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Status returned by the PMU firmware
*/
-enum pm_ret_status pm_init_finalize(void)
+enum pm_ret_status pm_init_finalize(uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMU */
- PM_PACK_PAYLOAD1(payload, LIBPM_MODULE_ID, PM_INIT_FINALIZE);
+ PM_PACK_PAYLOAD1(payload, LIBPM_MODULE_ID, flag, PM_INIT_FINALIZE);
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
}
@@ -106,6 +113,8 @@
* @latency Requested maximum wakeup latency (not supported)
* @state Requested state
* @address Resume address
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* This is a blocking call, it will return only once PMU has responded.
* On a wakeup, resume address will be automatically set by PMU.
@@ -115,7 +124,7 @@
enum pm_ret_status pm_self_suspend(uint32_t nid,
unsigned int latency,
unsigned int state,
- uintptr_t address)
+ uintptr_t address, uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
unsigned int cpuid = plat_my_core_pos();
@@ -133,7 +142,7 @@
pm_client_suspend(proc, state);
/* Send request to the PLM */
- PM_PACK_PAYLOAD6(payload, LIBPM_MODULE_ID, PM_SELF_SUSPEND,
+ PM_PACK_PAYLOAD6(payload, LIBPM_MODULE_ID, flag, PM_SELF_SUSPEND,
proc->node_id, latency, state, address,
(address >> 32));
return pm_ipi_send_sync(proc, payload, NULL, 0);
@@ -143,13 +152,15 @@
* pm_abort_suspend() - PM call to announce that a prior suspend request
* is to be aborted.
* @reason Reason for the abort
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* Calling PU expects the PMU to abort the initiated suspend procedure.
* This is a non-blocking call without any acknowledge.
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_abort_suspend(enum pm_abort_reason reason)
+enum pm_ret_status pm_abort_suspend(enum pm_abort_reason reason, uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
@@ -160,9 +171,9 @@
pm_client_abort_suspend();
/* Send request to the PLM */
- PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_ABORT_SUSPEND, reason,
- primary_proc->node_id);
- return pm_ipi_send(primary_proc, payload);
+ PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, flag, PM_ABORT_SUSPEND,
+ reason, primary_proc->node_id);
+ return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
}
/**
@@ -172,16 +183,19 @@
* @ack Flag to specify whether acknowledge is requested
* @latency Requested wakeup latency (not supported)
* @state Requested state (not supported)
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
enum pm_ret_status pm_req_suspend(uint32_t target, uint8_t ack,
- unsigned int latency, unsigned int state)
+ unsigned int latency, unsigned int state,
+ uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMU */
- PM_PACK_PAYLOAD4(payload, LIBPM_MODULE_ID, PM_REQ_SUSPEND, target,
+ PM_PACK_PAYLOAD4(payload, LIBPM_MODULE_ID, flag, PM_REQ_SUSPEND, target,
latency, state);
if (ack == IPI_BLOCKING)
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
@@ -197,6 +211,8 @@
* 1 - resume address specified, 0 - otherwise
* @address Resume address
* @ack Flag to specify whether acknowledge requested
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* This API function is either used to power up another APU core for SMP
* (by PSCI) or to power up an entirely different PU or subsystem, such
@@ -206,12 +222,12 @@
* @return Returns status, either success or error+reason
*/
enum pm_ret_status pm_req_wakeup(uint32_t target, uint32_t set_address,
- uintptr_t address, uint8_t ack)
+ uintptr_t address, uint8_t ack, uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC to perform the wake of the PU */
- PM_PACK_PAYLOAD5(payload, LIBPM_MODULE_ID, PM_REQ_WAKEUP, target,
+ PM_PACK_PAYLOAD5(payload, LIBPM_MODULE_ID, flag, PM_REQ_WAKEUP, target,
set_address, address, ack);
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
@@ -223,16 +239,18 @@
* @capabilities Requested capabilities for the device
* @qos Required Quality of Service
* @ack Flag to specify whether acknowledge requested
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
enum pm_ret_status pm_request_device(uint32_t device_id, uint32_t capabilities,
- uint32_t qos, uint32_t ack)
+ uint32_t qos, uint32_t ack, uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD5(payload, LIBPM_MODULE_ID, PM_REQUEST_DEVICE,
+ PM_PACK_PAYLOAD5(payload, LIBPM_MODULE_ID, flag, PM_REQUEST_DEVICE,
device_id, capabilities, qos, ack);
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
@@ -241,15 +259,17 @@
/**
* pm_release_device() - Release a device
* @device_id Device ID
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_release_device(uint32_t device_id)
+enum pm_ret_status pm_release_device(uint32_t device_id, uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_RELEASE_DEVICE,
+ PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, flag, PM_RELEASE_DEVICE,
device_id);
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
@@ -261,16 +281,19 @@
* @capabilities Requested capabilities for the device
* @latency Requested maximum latency
* @qos Required Quality of Service
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
enum pm_ret_status pm_set_requirement(uint32_t device_id, uint32_t capabilities,
- uint32_t latency, uint32_t qos)
+ uint32_t latency, uint32_t qos,
+ uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD5(payload, LIBPM_MODULE_ID, PM_SET_REQUIREMENT,
+ PM_PACK_PAYLOAD5(payload, LIBPM_MODULE_ID, flag, PM_SET_REQUIREMENT,
device_id, capabilities, latency, qos);
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
@@ -280,15 +303,18 @@
* pm_get_device_status() - Get device's status
* @device_id Device ID
* @response Buffer to store device status response
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_get_device_status(uint32_t device_id, uint32_t *response)
+enum pm_ret_status pm_get_device_status(uint32_t device_id, uint32_t *response,
+ uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_GET_DEVICE_STATUS,
+ PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, flag, PM_GET_DEVICE_STATUS,
device_id);
return pm_ipi_send_sync(primary_proc, payload, response, 3);
@@ -298,15 +324,17 @@
* pm_reset_assert() - Assert/De-assert reset
* @reset Reset ID
* @assert Assert (1) or de-assert (0)
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_reset_assert(uint32_t reset, bool assert)
+enum pm_ret_status pm_reset_assert(uint32_t reset, bool assert, uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_RESET_ASSERT, reset,
+ PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, flag, PM_RESET_ASSERT, reset,
assert);
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
@@ -316,15 +344,19 @@
* pm_reset_get_status() - Get current status of a reset line
* @reset Reset ID
* @status Returns current status of selected reset ID
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_reset_get_status(uint32_t reset, uint32_t *status)
+enum pm_ret_status pm_reset_get_status(uint32_t reset, uint32_t *status,
+ uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_RESET_ASSERT, reset);
+ PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, flag, PM_RESET_ASSERT,
+ reset);
return pm_ipi_send_sync(primary_proc, payload, status, 1);
}
@@ -332,10 +364,12 @@
/**
* pm_get_callbackdata() - Read from IPI response buffer
* @data - array of PAYLOAD_ARG_CNT elements
+ * @flag - 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* Read value from ipi buffer response buffer.
*/
-void pm_get_callbackdata(uint32_t *data, size_t count)
+void pm_get_callbackdata(uint32_t *data, size_t count, uint32_t flag)
{
/* Return if interrupt is not from PMU */
if (!pm_ipi_irq_status(primary_proc))
@@ -348,15 +382,18 @@
/**
* pm_pinctrl_request() - Request a pin
* @pin Pin ID
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_pinctrl_request(uint32_t pin)
+enum pm_ret_status pm_pinctrl_request(uint32_t pin, uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_PINCTRL_REQUEST, pin);
+ PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, flag, PM_PINCTRL_REQUEST,
+ pin);
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
}
@@ -364,15 +401,18 @@
/**
* pm_pinctrl_release() - Release a pin
* @pin Pin ID
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_pinctrl_release(uint32_t pin)
+enum pm_ret_status pm_pinctrl_release(uint32_t pin, uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_PINCTRL_RELEASE, pin);
+ PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, flag, PM_PINCTRL_RELEASE,
+ pin);
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
}
@@ -381,16 +421,19 @@
* pm_pinctrl_set_function() - Set pin function
* @pin Pin ID
* @function Function ID
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_pinctrl_set_function(uint32_t pin, uint32_t function)
+enum pm_ret_status pm_pinctrl_set_function(uint32_t pin, uint32_t function,
+ uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_PINCTRL_SET_FUNCTION, pin,
- function)
+ PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, flag,
+ PM_PINCTRL_SET_FUNCTION, pin, function)
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
}
@@ -399,16 +442,19 @@
* pm_pinctrl_get_function() - Get function set on the pin
* @pin Pin ID
* @function Function set on the pin
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_pinctrl_get_function(uint32_t pin, uint32_t *function)
+enum pm_ret_status pm_pinctrl_get_function(uint32_t pin, uint32_t *function,
+ uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_PINCTRL_SET_FUNCTION,
- pin);
+ PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, flag,
+ PM_PINCTRL_SET_FUNCTION, pin);
return pm_ipi_send_sync(primary_proc, payload, function, 1);
}
@@ -418,17 +464,19 @@
* @pin Pin ID
* @param Parameter ID
* @value Parameter value
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
enum pm_ret_status pm_pinctrl_set_pin_param(uint32_t pin, uint32_t param,
- uint32_t value)
+ uint32_t value, uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD4(payload, LIBPM_MODULE_ID, PM_PINCTRL_CONFIG_PARAM_SET,
- pin, param, value);
+ PM_PACK_PAYLOAD4(payload, LIBPM_MODULE_ID, flag,
+ PM_PINCTRL_CONFIG_PARAM_SET, pin, param, value);
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
}
@@ -438,17 +486,19 @@
* @pin Pin ID
* @param Parameter ID
* @value Buffer to store parameter value
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
enum pm_ret_status pm_pinctrl_get_pin_param(uint32_t pin, uint32_t param,
- uint32_t *value)
+ uint32_t *value, uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_PINCTRL_CONFIG_PARAM_GET,
- pin, param);
+ PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, flag,
+ PM_PINCTRL_CONFIG_PARAM_GET, pin, param);
return pm_ipi_send_sync(primary_proc, payload, value, 1);
}
@@ -456,15 +506,18 @@
/**
* pm_clock_enable() - Enable the clock
* @clk_id Clock ID
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_clock_enable(uint32_t clk_id)
+enum pm_ret_status pm_clock_enable(uint32_t clk_id, uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_CLOCK_ENABLE, clk_id);
+ PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, flag, PM_CLOCK_ENABLE,
+ clk_id);
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
}
@@ -472,15 +525,18 @@
/**
* pm_clock_disable() - Disable the clock
* @clk_id Clock ID
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_clock_disable(uint32_t clk_id)
+enum pm_ret_status pm_clock_disable(uint32_t clk_id, uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_CLOCK_DISABLE, clk_id);
+ PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, flag, PM_CLOCK_DISABLE,
+ clk_id);
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
}
@@ -489,15 +545,19 @@
* pm_clock_get_state() - Get clock status
* @clk_id Clock ID
* @state: Buffer to store clock status (1: Enabled, 0:Disabled)
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_clock_get_state(uint32_t clk_id, uint32_t *state)
+enum pm_ret_status pm_clock_get_state(uint32_t clk_id, uint32_t *state,
+ uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_CLOCK_GETSTATE, clk_id);
+ PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, flag, PM_CLOCK_GETSTATE,
+ clk_id);
return pm_ipi_send_sync(primary_proc, payload, state, 1);
}
@@ -506,16 +566,19 @@
* pm_clock_set_divider() - Set divider for the clock
* @clk_id Clock ID
* @divider Divider value
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_clock_set_divider(uint32_t clk_id, uint32_t divider)
+enum pm_ret_status pm_clock_set_divider(uint32_t clk_id, uint32_t divider,
+ uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_CLOCK_SETDIVIDER, clk_id,
- divider);
+ PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, flag, PM_CLOCK_SETDIVIDER,
+ clk_id, divider);
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
}
@@ -524,15 +587,19 @@
* pm_clock_get_divider() - Get divider value for the clock
* @clk_id Clock ID
* @divider: Buffer to store clock divider value
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_clock_get_divider(uint32_t clk_id, uint32_t *divider)
+enum pm_ret_status pm_clock_get_divider(uint32_t clk_id, uint32_t *divider,
+ uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_CLOCK_GETDIVIDER, clk_id);
+ PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, flag, PM_CLOCK_GETDIVIDER,
+ clk_id);
return pm_ipi_send_sync(primary_proc, payload, divider, 1);
}
@@ -541,16 +608,19 @@
* pm_clock_set_parent() - Set parent for the clock
* @clk_id Clock ID
* @parent Parent ID
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_clock_set_parent(uint32_t clk_id, uint32_t parent)
+enum pm_ret_status pm_clock_set_parent(uint32_t clk_id, uint32_t parent,
+ uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_CLOCK_SETPARENT, clk_id,
- parent);
+ PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, flag, PM_CLOCK_SETPARENT,
+ clk_id, parent);
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
}
@@ -559,15 +629,19 @@
* pm_clock_get_parent() - Get parent value for the clock
* @clk_id Clock ID
* @parent: Buffer to store clock parent value
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_clock_get_parent(uint32_t clk_id, uint32_t *parent)
+enum pm_ret_status pm_clock_get_parent(uint32_t clk_id, uint32_t *parent,
+ uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_CLOCK_GETPARENT, clk_id);
+ PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, flag, PM_CLOCK_GETPARENT,
+ clk_id);
return pm_ipi_send_sync(primary_proc, payload, parent, 1);
}
@@ -575,15 +649,19 @@
* pm_clock_get_rate() - Get the rate value for the clock
* @clk_id Clock ID
* @rate: Buffer to store clock rate value
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_clock_get_rate(uint32_t clk_id, uint32_t *clk_rate)
+enum pm_ret_status pm_clock_get_rate(uint32_t clk_id, uint32_t *clk_rate,
+ uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_CLOCK_GETRATE, clk_id);
+ PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, flag, PM_CLOCK_GETRATE,
+ clk_id);
return pm_ipi_send_sync(primary_proc, payload, clk_rate, 2);
}
@@ -593,17 +671,19 @@
* @clk_id PLL clock ID
* @param PLL parameter ID
* @value Value to set for PLL parameter
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
enum pm_ret_status pm_pll_set_param(uint32_t clk_id, uint32_t param,
- uint32_t value)
+ uint32_t value, uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD4(payload, LIBPM_MODULE_ID, PM_PLL_SET_PARAMETER, clk_id,
- param, value);
+ PM_PACK_PAYLOAD4(payload, LIBPM_MODULE_ID, flag, PM_PLL_SET_PARAMETER,
+ clk_id, param, value);
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
}
@@ -613,17 +693,19 @@
* @clk_id PLL clock ID
* @param PLL parameter ID
* @value: Buffer to store PLL parameter value
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
enum pm_ret_status pm_pll_get_param(uint32_t clk_id, uint32_t param,
- uint32_t *value)
+ uint32_t *value, uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_PLL_GET_PARAMETER, clk_id,
- param);
+ PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, flag, PM_PLL_GET_PARAMETER,
+ clk_id, param);
return pm_ipi_send_sync(primary_proc, payload, value, 1);
}
@@ -632,16 +714,19 @@
* pm_pll_set_mode() - Set PLL mode
* @clk_id PLL clock ID
* @mode PLL mode
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_pll_set_mode(uint32_t clk_id, uint32_t mode)
+enum pm_ret_status pm_pll_set_mode(uint32_t clk_id, uint32_t mode,
+ uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_PLL_SET_MODE, clk_id,
- mode);
+ PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, flag, PM_PLL_SET_MODE,
+ clk_id, mode);
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
}
@@ -650,15 +735,19 @@
* pm_pll_get_mode() - Get PLL mode
* @clk_id PLL clock ID
* @mode: Buffer to store PLL mode
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_pll_get_mode(uint32_t clk_id, uint32_t *mode)
+enum pm_ret_status pm_pll_get_mode(uint32_t clk_id, uint32_t *mode,
+ uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_PLL_GET_MODE, clk_id);
+ PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, flag, PM_PLL_GET_MODE,
+ clk_id);
return pm_ipi_send_sync(primary_proc, payload, mode, 1);
}
@@ -668,16 +757,19 @@
* be powered down forcefully
* @target Device ID of the PU node to be forced powered down.
* @ack Flag to specify whether acknowledge is requested
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_force_powerdown(uint32_t target, uint8_t ack)
+enum pm_ret_status pm_force_powerdown(uint32_t target, uint8_t ack,
+ uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_FORCE_POWERDOWN, target,
- ack);
+ PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, flag, PM_FORCE_POWERDOWN,
+ target, ack);
if (ack == IPI_BLOCKING)
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
@@ -689,10 +781,13 @@
* pm_system_shutdown() - PM call to request a system shutdown or restart
* @type Shutdown or restart? 0=shutdown, 1=restart, 2=setscope
* @subtype Scope: 0=APU-subsystem, 1=PS, 2=system
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_system_shutdown(uint32_t type, uint32_t subtype)
+enum pm_ret_status pm_system_shutdown(uint32_t type, uint32_t subtype,
+ uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
@@ -703,8 +798,8 @@
}
/* Send request to the PMC */
- PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_SYSTEM_SHUTDOWN, type,
- subtype);
+ PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, flag, PM_SYSTEM_SHUTDOWN,
+ type, subtype);
return pm_ipi_send_non_blocking(primary_proc, payload);
}
@@ -716,11 +811,13 @@
* @arg2 Argument 2 to requested query data call
* @arg3 Argument 3 to requested query data call
* @data Returned output data
+* @flag 0 - Call from secure source
+* 1 - Call from non-secure source
*
* This function returns requested data.
*/
enum pm_ret_status pm_query_data(uint32_t qid, uint32_t arg1, uint32_t arg2,
- uint32_t arg3, uint32_t *data)
+ uint32_t arg3, uint32_t *data, uint32_t flag)
{
uint32_t ret;
uint32_t version;
@@ -728,10 +825,10 @@
uint32_t fw_api_version;
/* Send request to the PMC */
- PM_PACK_PAYLOAD5(payload, LIBPM_MODULE_ID, PM_QUERY_DATA, qid, arg1,
- arg2, arg3);
+ PM_PACK_PAYLOAD5(payload, LIBPM_MODULE_ID, flag, PM_QUERY_DATA, qid,
+ arg1, arg2, arg3);
- ret = pm_feature_check(PM_QUERY_DATA, &version);
+ ret = pm_feature_check(PM_QUERY_DATA, &version, flag);
if (PM_RET_SUCCESS == ret) {
fw_api_version = version & 0xFFFF ;
if ((2U == fw_api_version) &&
@@ -755,29 +852,42 @@
* @arg1 Argument 1 to requested IOCTL call
* @arg2 Argument 2 to requested IOCTL call
* @value Returned output value
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* This function calls IOCTL to firmware for device control and configuration.
*
* @return Returns status, either success or error+reason
*/
enum pm_ret_status pm_api_ioctl(uint32_t device_id, uint32_t ioctl_id,
- uint32_t arg1, uint32_t arg2, uint32_t *value)
+ uint32_t arg1, uint32_t arg2, uint32_t *value,
+ uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
+ int ret;
switch (ioctl_id) {
case IOCTL_SET_PLL_FRAC_MODE:
- return pm_pll_set_mode(arg1, arg2);
+ return pm_pll_set_mode(arg1, arg2, flag);
case IOCTL_GET_PLL_FRAC_MODE:
- return pm_pll_get_mode(arg1, value);
+ return pm_pll_get_mode(arg1, value, flag);
case IOCTL_SET_PLL_FRAC_DATA:
- return pm_pll_set_param(arg1, PM_PLL_PARAM_DATA, arg2);
+ return pm_pll_set_param(arg1, PM_PLL_PARAM_DATA, arg2, flag);
case IOCTL_GET_PLL_FRAC_DATA:
- return pm_pll_get_param(arg1, PM_PLL_PARAM_DATA, value);
+ return pm_pll_get_param(arg1, PM_PLL_PARAM_DATA, value, flag);
+ case IOCTL_SET_SGI:
+ /* Get the sgi number */
+ ret = pm_register_sgi(arg1);
+ if (ret) {
+ return PM_RET_ERROR_ARGS;
+ }
+ gicd_write_irouter(gicv3_driver_data->gicd_base,
+ PLAT_VERSAL_IPI_IRQ, MODE);
+ return PM_RET_SUCCESS;
default:
/* Send request to the PMC */
- PM_PACK_PAYLOAD5(payload, LIBPM_MODULE_ID, PM_IOCTL, device_id,
- ioctl_id, arg1, arg2);
+ PM_PACK_PAYLOAD5(payload, LIBPM_MODULE_ID, flag, PM_IOCTL,
+ device_id, ioctl_id, arg1, arg2);
return pm_ipi_send_sync(primary_proc, payload, value, 1);
}
}
@@ -787,32 +897,36 @@
* @target Device id of the targeted PU or subsystem
* @wkup_node Device id of the wakeup peripheral
* @enable Enable or disable the specified peripheral as wake source
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
enum pm_ret_status pm_set_wakeup_source(uint32_t target, uint32_t wkup_device,
- uint8_t enable)
+ uint8_t enable, uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
- PM_PACK_PAYLOAD4(payload, LIBPM_MODULE_ID, PM_SET_WAKEUP_SOURCE, target,
- wkup_device, enable);
- return pm_ipi_send(primary_proc, payload);
+ PM_PACK_PAYLOAD4(payload, LIBPM_MODULE_ID, flag, PM_SET_WAKEUP_SOURCE,
+ target, wkup_device, enable);
+ return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
}
/**
* pm_get_chipid() - Read silicon ID registers
* @value Buffer for return values. Must be large enough
* to hold 8 bytes.
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns silicon ID registers
*/
-enum pm_ret_status pm_get_chipid(uint32_t *value)
+enum pm_ret_status pm_get_chipid(uint32_t *value, uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD1(payload, LIBPM_MODULE_ID, PM_GET_CHIPID);
+ PM_PACK_PAYLOAD1(payload, LIBPM_MODULE_ID, flag, PM_GET_CHIPID);
return pm_ipi_send_sync(primary_proc, payload, value, 2);
}
@@ -821,10 +935,13 @@
* pm_feature_check() - Returns the supported API version if supported
* @api_id API ID to check
* @value Returned supported API version
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_feature_check(uint32_t api_id, unsigned int *version)
+enum pm_ret_status pm_feature_check(uint32_t api_id, unsigned int *version,
+ uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT], fw_api_version;
uint32_t status;
@@ -884,7 +1001,8 @@
return PM_RET_ERROR_NOFEATURE;
}
- PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, PM_FEATURE_CHECK, api_id);
+ PM_PACK_PAYLOAD2(payload, LIBPM_MODULE_ID, flag,
+ PM_FEATURE_CHECK, api_id);
status = pm_ipi_send_sync(primary_proc, payload, &fw_api_version, 1);
if (status != PM_RET_SUCCESS)
@@ -903,16 +1021,18 @@
* src: Source device of pdi(DDR, OCM, SD etc)
* address_low: lower 32-bit Linear memory space address
* address_high: higher 32-bit Linear memory space address
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_load_pdi(uint32_t src,
- uint32_t address_low, uint32_t address_high)
+enum pm_ret_status pm_load_pdi(uint32_t src, uint32_t address_low,
+ uint32_t address_high, uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMU */
- PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, PM_LOAD_PDI, src,
+ PM_PACK_PAYLOAD4(payload, LOADER_MODULE_ID, flag, PM_LOAD_PDI, src,
address_high, address_low);
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
}
@@ -925,18 +1045,20 @@
* (power, temperature and latency)
* @result Returns the operating characteristic for the requested device,
* specified by the type
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
enum pm_ret_status pm_get_op_characteristic(uint32_t device_id,
enum pm_opchar_type type,
- uint32_t *result)
+ uint32_t *result, uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_GET_OP_CHARACTERISTIC,
- device_id, type);
+ PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, flag,
+ PM_GET_OP_CHARACTERISTIC, device_id, type);
return pm_ipi_send_sync(primary_proc, payload, result, 1);
}
@@ -946,15 +1068,18 @@
* used by that CPU.
* @device_id Device ID
* @latency Latency value
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
-enum pm_ret_status pm_set_max_latency(uint32_t device_id, uint32_t latency)
+enum pm_ret_status pm_set_max_latency(uint32_t device_id, uint32_t latency,
+ uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, PM_SET_MAX_LATENCY,
+ PM_PACK_PAYLOAD3(payload, LIBPM_MODULE_ID, flag, PM_SET_MAX_LATENCY,
device_id, latency);
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
@@ -967,16 +1092,19 @@
* @event Event in question
* @wake Wake subsystem upon capturing the event if value 1
* @enable Enable the registration for value 1, disable for value 0
+ * @flag 0 - Call from secure source
+ * 1 - Call from non-secure source
*
* @return Returns status, either success or error+reason
*/
enum pm_ret_status pm_register_notifier(uint32_t device_id, uint32_t event,
- uint32_t wake, uint32_t enable)
+ uint32_t wake, uint32_t enable,
+ uint32_t flag)
{
uint32_t payload[PAYLOAD_ARG_CNT];
/* Send request to the PMC */
- PM_PACK_PAYLOAD5(payload, LIBPM_MODULE_ID, PM_REGISTER_NOTIFIER,
+ PM_PACK_PAYLOAD5(payload, LIBPM_MODULE_ID, flag, PM_REGISTER_NOTIFIER,
device_id, event, wake, enable);
return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
diff --git a/plat/xilinx/versal/pm_service/pm_api_sys.h b/plat/xilinx/versal/pm_service/pm_api_sys.h
index 84867b6..5a92704 100644
--- a/plat/xilinx/versal/pm_service/pm_api_sys.h
+++ b/plat/xilinx/versal/pm_service/pm_api_sys.h
@@ -14,67 +14,86 @@
* PM API function declarations
**********************************************************/
-enum pm_ret_status pm_get_api_version(unsigned int *version);
-enum pm_ret_status pm_init_finalize(void);
+enum pm_ret_status pm_get_api_version(unsigned int *version, uint32_t flag);
+enum pm_ret_status pm_init_finalize(uint32_t flag);
enum pm_ret_status pm_self_suspend(uint32_t nid,
unsigned int latency,
unsigned int state,
- uintptr_t address);
-enum pm_ret_status pm_abort_suspend(enum pm_abort_reason reason);
+ uintptr_t address, uint32_t flag);
+enum pm_ret_status pm_abort_suspend(enum pm_abort_reason reason, uint32_t flag);
enum pm_ret_status pm_req_suspend(uint32_t target,
uint8_t ack,
unsigned int latency,
- unsigned int state);
+ unsigned int state, uint32_t flag);
enum pm_ret_status pm_req_wakeup(uint32_t target, uint32_t set_address,
- uintptr_t address, uint8_t ack);
+ uintptr_t address, uint8_t ack, uint32_t flag);
enum pm_ret_status pm_set_wakeup_source(uint32_t target, uint32_t device_id,
- uint8_t enable);
+ uint8_t enable, uint32_t flag);
enum pm_ret_status pm_request_device(uint32_t device_id, uint32_t capabilities,
- uint32_t qos, uint32_t ack);
-enum pm_ret_status pm_release_device(uint32_t device_id);
+ uint32_t qos, uint32_t ack, uint32_t flag);
+enum pm_ret_status pm_release_device(uint32_t device_id, uint32_t flag);
enum pm_ret_status pm_set_requirement(uint32_t device_id, uint32_t capabilities,
- uint32_t latency, uint32_t qos);
-enum pm_ret_status pm_get_device_status(uint32_t device_id, uint32_t *response);
-enum pm_ret_status pm_reset_assert(uint32_t reset, bool assert);
-enum pm_ret_status pm_reset_get_status(uint32_t reset, uint32_t *status);
-void pm_get_callbackdata(uint32_t *data, size_t count);
-enum pm_ret_status pm_pinctrl_request(uint32_t pin);
-enum pm_ret_status pm_pinctrl_release(uint32_t pin);
-enum pm_ret_status pm_pinctrl_set_function(uint32_t pin, uint32_t function);
-enum pm_ret_status pm_pinctrl_get_function(uint32_t pin, uint32_t *function);
+ uint32_t latency, uint32_t qos,
+ uint32_t flag);
+enum pm_ret_status pm_get_device_status(uint32_t device_id, uint32_t *response,
+ uint32_t flag);
+enum pm_ret_status pm_reset_assert(uint32_t reset, bool assert, uint32_t flag);
+enum pm_ret_status pm_reset_get_status(uint32_t reset, uint32_t *status,
+ uint32_t flag);
+void pm_get_callbackdata(uint32_t *data, size_t count, uint32_t flag);
+enum pm_ret_status pm_pinctrl_request(uint32_t pin, uint32_t flag);
+enum pm_ret_status pm_pinctrl_release(uint32_t pin, uint32_t flag);
+enum pm_ret_status pm_pinctrl_set_function(uint32_t pin, uint32_t function,
+ uint32_t flag);
+enum pm_ret_status pm_pinctrl_get_function(uint32_t pin, uint32_t *function,
+ uint32_t flag);
enum pm_ret_status pm_pinctrl_set_pin_param(uint32_t pin, uint32_t param,
- uint32_t value);
+ uint32_t value, uint32_t flag);
enum pm_ret_status pm_pinctrl_get_pin_param(uint32_t pin, uint32_t param,
- uint32_t *value);
-enum pm_ret_status pm_clock_enable(uint32_t clk_id);
-enum pm_ret_status pm_clock_disable(uint32_t clk_id);
-enum pm_ret_status pm_clock_get_state(uint32_t clk_id, uint32_t *state);
-enum pm_ret_status pm_clock_set_divider(uint32_t clk_id, uint32_t divider);
-enum pm_ret_status pm_clock_get_divider(uint32_t clk_id, uint32_t *divider);
-enum pm_ret_status pm_clock_set_parent(uint32_t clk_id, uint32_t parent);
-enum pm_ret_status pm_clock_get_parent(uint32_t clk_id, uint32_t *parent);
-enum pm_ret_status pm_clock_get_rate(uint32_t clk_id, uint32_t *clk_rate);
+ uint32_t *value, uint32_t flag);
+enum pm_ret_status pm_clock_enable(uint32_t clk_id, uint32_t flag);
+enum pm_ret_status pm_clock_disable(uint32_t clk_id, uint32_t flag);
+enum pm_ret_status pm_clock_get_state(uint32_t clk_id, uint32_t *state,
+ uint32_t flag);
+enum pm_ret_status pm_clock_set_divider(uint32_t clk_id, uint32_t divider,
+ uint32_t flag);
+enum pm_ret_status pm_clock_get_divider(uint32_t clk_id, uint32_t *divider,
+ uint32_t flag);
+enum pm_ret_status pm_clock_set_parent(uint32_t clk_id, uint32_t parent,
+ uint32_t flag);
+enum pm_ret_status pm_clock_get_parent(uint32_t clk_id, uint32_t *parent,
+ uint32_t flag);
+enum pm_ret_status pm_clock_get_rate(uint32_t clk_id, uint32_t *clk_rate,
+ uint32_t flag);
enum pm_ret_status pm_pll_set_param(uint32_t clk_id, uint32_t param,
- uint32_t value);
+ uint32_t value, uint32_t flag);
enum pm_ret_status pm_pll_get_param(uint32_t clk_id, uint32_t param,
- uint32_t *value);
-enum pm_ret_status pm_pll_set_mode(uint32_t clk_id, uint32_t mode);
-enum pm_ret_status pm_pll_get_mode(uint32_t clk_id, uint32_t *mode);
-enum pm_ret_status pm_force_powerdown(uint32_t target, uint8_t ack);
-enum pm_ret_status pm_system_shutdown(uint32_t type, uint32_t subtype);
+ uint32_t *value, uint32_t flag);
+enum pm_ret_status pm_pll_set_mode(uint32_t clk_id, uint32_t mode,
+ uint32_t flag);
+enum pm_ret_status pm_pll_get_mode(uint32_t clk_id, uint32_t *mode,
+ uint32_t flag);
+enum pm_ret_status pm_force_powerdown(uint32_t target, uint8_t ack,
+ uint32_t flag);
+enum pm_ret_status pm_system_shutdown(uint32_t type, uint32_t subtype,
+ uint32_t flag);
enum pm_ret_status pm_api_ioctl(uint32_t device_id, uint32_t ioctl_id,
- uint32_t arg1, uint32_t arg2, uint32_t *value);
+ uint32_t arg1, uint32_t arg2, uint32_t *value,
+ uint32_t flag);
enum pm_ret_status pm_query_data(uint32_t qid, uint32_t arg1, uint32_t arg2,
- uint32_t arg3, uint32_t *data);
+ uint32_t arg3, uint32_t *data, uint32_t flag);
unsigned int pm_get_shutdown_scope(void);
-enum pm_ret_status pm_get_chipid(uint32_t *value);
-enum pm_ret_status pm_feature_check(uint32_t api_id, unsigned int *version);
+enum pm_ret_status pm_get_chipid(uint32_t *value, uint32_t flag);
+enum pm_ret_status pm_feature_check(uint32_t api_id, unsigned int *version,
+ uint32_t flag);
enum pm_ret_status pm_load_pdi(uint32_t src, uint32_t address_low,
- uint32_t address_high);
+ uint32_t address_high, uint32_t flag);
enum pm_ret_status pm_get_op_characteristic(uint32_t device_id,
enum pm_opchar_type type,
- uint32_t *result);
-enum pm_ret_status pm_set_max_latency(uint32_t device_id, uint32_t latency);
+ uint32_t *result, uint32_t flag);
+enum pm_ret_status pm_set_max_latency(uint32_t device_id, uint32_t latency,
+ uint32_t flag);
enum pm_ret_status pm_register_notifier(uint32_t device_id, uint32_t event,
- uint32_t wake, uint32_t enable);
+ uint32_t wake, uint32_t enable,
+ uint32_t flag);
#endif /* PM_API_SYS_H */
diff --git a/plat/xilinx/versal/pm_service/pm_client.c b/plat/xilinx/versal/pm_service/pm_client.c
index 9ab921e..f6c3148 100644
--- a/plat/xilinx/versal/pm_service/pm_client.c
+++ b/plat/xilinx/versal/pm_service/pm_client.c
@@ -149,7 +149,8 @@
/* Get device ID from node index */
device_id = PERIPH_DEVID(node_idx);
ret = pm_set_wakeup_source(node_id,
- device_id, 1);
+ device_id, 1,
+ SECURE_FLAG);
pm_wakeup_nodes_set[node_idx] = !ret;
}
}
diff --git a/plat/xilinx/versal/pm_service/pm_defs.h b/plat/xilinx/versal/pm_service/pm_defs.h
index 793f750..ccb2617 100644
--- a/plat/xilinx/versal/pm_service/pm_defs.h
+++ b/plat/xilinx/versal/pm_service/pm_defs.h
@@ -92,6 +92,7 @@
#define IOCTL_GET_PLL_FRAC_MODE 9
#define IOCTL_SET_PLL_FRAC_DATA 10
#define IOCTL_GET_PLL_FRAC_DATA 11
+#define IOCTL_SET_SGI 25
/* Parameter ID for PLL IOCTLs */
/* Fractional data portion for PLL */
diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.c b/plat/xilinx/versal/pm_service/pm_svc_main.c
index 2ed6d27..87ba732 100644
--- a/plat/xilinx/versal/pm_service/pm_svc_main.c
+++ b/plat/xilinx/versal/pm_service/pm_svc_main.c
@@ -13,12 +13,64 @@
#include <plat_private.h>
#include <stdbool.h>
#include <common/runtime_svc.h>
+#include <plat/common/platform.h>
#include "pm_api_sys.h"
#include "pm_client.h"
#include "pm_ipi.h"
+#include <drivers/arm/gicv3.h>
+
+#define XSCUGIC_SGIR_EL1_INITID_SHIFT 24U
+#define INVALID_SGI 0xFF
+DEFINE_RENAME_SYSREG_RW_FUNCS(icc_asgi1r_el1, S3_0_C12_C11_6)
/* pm_up = true - UP, pm_up = false - DOWN */
static bool pm_up;
+static unsigned int sgi = INVALID_SGI;
+
+static uint64_t ipi_fiq_handler(uint32_t id, uint32_t flags, void *handle,
+ void *cookie)
+{
+ int cpu;
+ unsigned int reg;
+
+ (void)plat_ic_acknowledge_interrupt();
+ cpu = plat_my_core_pos() + 1;
+
+ if (sgi != INVALID_SGI) {
+ reg = (cpu | (sgi << XSCUGIC_SGIR_EL1_INITID_SHIFT));
+ write_icc_asgi1r_el1(reg);
+ }
+
+ /* Clear FIQ */
+ plat_ic_end_of_interrupt(id);
+
+ return 0;
+}
+
+/**
+ * pm_register_sgi() - PM register the IPI interrupt
+ *
+ * @sgi - SGI number to be used for communication.
+ * @return On success, the initialization function must return 0.
+ * Any other return value will cause the framework to ignore
+ * the service
+ *
+ * Update the SGI number to be used.
+ *
+ */
+int pm_register_sgi(unsigned int sgi_num)
+{
+ if (sgi != INVALID_SGI) {
+ return -EBUSY;
+ }
+
+ if (sgi_num >= GICV3_MAX_SGI_TARGETS) {
+ return -EINVAL;
+ }
+
+ sgi = sgi_num;
+ return 0;
+}
/**
* pm_setup() - PM service setup
@@ -46,6 +98,18 @@
pm_up = true;
}
+ /*
+ * Enable IPI IRQ
+ * assume the rich OS is OK to handle callback IRQs now.
+ * Even if we were wrong, it would not enable the IRQ in
+ * the GIC.
+ */
+ pm_ipi_irq_enable(primary_proc);
+
+ ret = request_intr_type_el3(PLAT_VERSAL_IPI_IRQ, ipi_fiq_handler);
+ if (ret) {
+ WARN("BL31: registering IPI interrupt failed\n");
+ }
return ret;
}
@@ -71,6 +135,7 @@
enum pm_ret_status ret;
uint32_t pm_arg[4];
+ uint32_t security_flag = SECURE_FLAG;
/* Handle case where PM wasn't initialized properly */
if (!pm_up)
@@ -81,57 +146,67 @@
pm_arg[2] = (uint32_t)x2;
pm_arg[3] = (uint32_t)(x2 >> 32);
+ /*
+ * Mark BIT24 payload (i.e 1st bit of pm_arg[3] ) as non-secure (1)
+ * if smc called is non secure
+ */
+ if (is_caller_non_secure(flags)) {
+ security_flag = NON_SECURE_FLAG;
+ }
+
switch (smc_fid & FUNCID_NUM_MASK) {
/* PM API Functions */
case PM_SELF_SUSPEND:
ret = pm_self_suspend(pm_arg[0], pm_arg[1], pm_arg[2],
- pm_arg[3]);
+ pm_arg[3], security_flag);
SMC_RET1(handle, (uint64_t)ret);
case PM_FORCE_POWERDOWN:
- ret = pm_force_powerdown(pm_arg[0], pm_arg[1]);
+ ret = pm_force_powerdown(pm_arg[0], pm_arg[1], security_flag);
SMC_RET1(handle, (uint64_t)ret);
case PM_REQ_SUSPEND:
ret = pm_req_suspend(pm_arg[0], pm_arg[1], pm_arg[2],
- pm_arg[3]);
+ pm_arg[3], security_flag);
SMC_RET1(handle, (uint64_t)ret);
case PM_ABORT_SUSPEND:
- ret = pm_abort_suspend(pm_arg[0]);
+ ret = pm_abort_suspend(pm_arg[0], security_flag);
SMC_RET1(handle, (uint64_t)ret);
case PM_SYSTEM_SHUTDOWN:
- ret = pm_system_shutdown(pm_arg[0], pm_arg[1]);
+ ret = pm_system_shutdown(pm_arg[0], pm_arg[1], security_flag);
SMC_RET1(handle, (uint64_t)ret);
case PM_REQ_WAKEUP:
- ret = pm_req_wakeup(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]);
+ ret = pm_req_wakeup(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3],
+ security_flag);
SMC_RET1(handle, (uint64_t)ret);
case PM_SET_WAKEUP_SOURCE:
- ret = pm_set_wakeup_source(pm_arg[0], pm_arg[1], pm_arg[2]);
+ ret = pm_set_wakeup_source(pm_arg[0], pm_arg[1], pm_arg[2],
+ security_flag);
SMC_RET1(handle, (uint64_t)ret);
case PM_REQUEST_DEVICE:
ret = pm_request_device(pm_arg[0], pm_arg[1], pm_arg[2],
- pm_arg[3]);
+ pm_arg[3], security_flag);
SMC_RET1(handle, (uint64_t)ret);
case PM_RELEASE_DEVICE:
- ret = pm_release_device(pm_arg[0]);
+ ret = pm_release_device(pm_arg[0], security_flag);
SMC_RET1(handle, (uint64_t)ret);
case PM_SET_REQUIREMENT:
ret = pm_set_requirement(pm_arg[0], pm_arg[1], pm_arg[2],
- pm_arg[3]);
+ pm_arg[3], security_flag);
SMC_RET1(handle, (uint64_t)ret);
case PM_GET_API_VERSION:
{
uint32_t api_version;
- ret = pm_get_api_version(&api_version);
+ ret = pm_get_api_version(&api_version, security_flag);
SMC_RET1(handle, (uint64_t)PM_RET_SUCCESS |
((uint64_t)api_version << 32));
}
@@ -140,68 +215,72 @@
{
uint32_t buff[3];
- ret = pm_get_device_status(pm_arg[0], buff);
+ ret = pm_get_device_status(pm_arg[0], buff, security_flag);
SMC_RET2(handle, (uint64_t)ret | ((uint64_t)buff[0] << 32),
(uint64_t)buff[1] | ((uint64_t)buff[2] << 32));
}
case PM_RESET_ASSERT:
- ret = pm_reset_assert(pm_arg[0], pm_arg[1]);
+ ret = pm_reset_assert(pm_arg[0], pm_arg[1], security_flag);
SMC_RET1(handle, (uint64_t)ret);
case PM_RESET_GET_STATUS:
{
uint32_t reset_status;
- ret = pm_reset_get_status(pm_arg[0], &reset_status);
+ ret = pm_reset_get_status(pm_arg[0], &reset_status,
+ security_flag);
SMC_RET1(handle, (uint64_t)ret |
((uint64_t)reset_status << 32));
}
case PM_INIT_FINALIZE:
- ret = pm_init_finalize();
+ ret = pm_init_finalize(security_flag);
SMC_RET1(handle, (uint64_t)ret);
case PM_GET_CALLBACK_DATA:
{
uint32_t result[4] = {0};
- pm_get_callbackdata(result, ARRAY_SIZE(result));
+ pm_get_callbackdata(result, ARRAY_SIZE(result), security_flag);
SMC_RET2(handle,
(uint64_t)result[0] | ((uint64_t)result[1] << 32),
(uint64_t)result[2] | ((uint64_t)result[3] << 32));
}
case PM_PINCTRL_REQUEST:
- ret = pm_pinctrl_request(pm_arg[0]);
+ ret = pm_pinctrl_request(pm_arg[0], security_flag);
SMC_RET1(handle, (uint64_t)ret);
case PM_PINCTRL_RELEASE:
- ret = pm_pinctrl_release(pm_arg[0]);
+ ret = pm_pinctrl_release(pm_arg[0], security_flag);
SMC_RET1(handle, (uint64_t)ret);
case PM_PINCTRL_GET_FUNCTION:
{
uint32_t value = 0;
- ret = pm_pinctrl_get_function(pm_arg[0], &value);
+ ret = pm_pinctrl_get_function(pm_arg[0], &value, security_flag);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
}
case PM_PINCTRL_SET_FUNCTION:
- ret = pm_pinctrl_set_function(pm_arg[0], pm_arg[1]);
+ ret = pm_pinctrl_set_function(pm_arg[0], pm_arg[1],
+ security_flag);
SMC_RET1(handle, (uint64_t)ret);
case PM_PINCTRL_CONFIG_PARAM_GET:
{
uint32_t value;
- ret = pm_pinctrl_get_pin_param(pm_arg[0], pm_arg[1], &value);
+ ret = pm_pinctrl_get_pin_param(pm_arg[0], pm_arg[1], &value,
+ security_flag);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
}
case PM_PINCTRL_CONFIG_PARAM_SET:
- ret = pm_pinctrl_set_pin_param(pm_arg[0], pm_arg[1], pm_arg[2]);
+ ret = pm_pinctrl_set_pin_param(pm_arg[0], pm_arg[1], pm_arg[2],
+ security_flag);
SMC_RET1(handle, (uint64_t)ret);
case PM_IOCTL:
@@ -209,7 +288,7 @@
uint32_t value;
ret = pm_api_ioctl(pm_arg[0], pm_arg[1], pm_arg[2],
- pm_arg[3], &value);
+ pm_arg[3], &value, security_flag);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
}
@@ -218,49 +297,49 @@
uint32_t data[8] = { 0 };
ret = pm_query_data(pm_arg[0], pm_arg[1], pm_arg[2],
- pm_arg[3], data);
+ pm_arg[3], data, security_flag);
SMC_RET2(handle, (uint64_t)ret | ((uint64_t)data[0] << 32),
(uint64_t)data[1] | ((uint64_t)data[2] << 32));
}
case PM_CLOCK_ENABLE:
- ret = pm_clock_enable(pm_arg[0]);
+ ret = pm_clock_enable(pm_arg[0], security_flag);
SMC_RET1(handle, (uint64_t)ret);
case PM_CLOCK_DISABLE:
- ret = pm_clock_disable(pm_arg[0]);
+ ret = pm_clock_disable(pm_arg[0], security_flag);
SMC_RET1(handle, (uint64_t)ret);
case PM_CLOCK_GETSTATE:
{
uint32_t value;
- ret = pm_clock_get_state(pm_arg[0], &value);
+ ret = pm_clock_get_state(pm_arg[0], &value, security_flag);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
}
case PM_CLOCK_SETDIVIDER:
- ret = pm_clock_set_divider(pm_arg[0], pm_arg[1]);
+ ret = pm_clock_set_divider(pm_arg[0], pm_arg[1], security_flag);
SMC_RET1(handle, (uint64_t)ret);
case PM_CLOCK_GETDIVIDER:
{
uint32_t value;
- ret = pm_clock_get_divider(pm_arg[0], &value);
+ ret = pm_clock_get_divider(pm_arg[0], &value, security_flag);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
}
case PM_CLOCK_SETPARENT:
- ret = pm_clock_set_parent(pm_arg[0], pm_arg[1]);
+ ret = pm_clock_set_parent(pm_arg[0], pm_arg[1], security_flag);
SMC_RET1(handle, (uint64_t)ret);
case PM_CLOCK_GETPARENT:
{
uint32_t value;
- ret = pm_clock_get_parent(pm_arg[0], &value);
+ ret = pm_clock_get_parent(pm_arg[0], &value, security_flag);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
}
@@ -268,32 +347,34 @@
{
uint32_t rate[2] = { 0 };
- ret = pm_clock_get_rate(pm_arg[0], rate);
+ ret = pm_clock_get_rate(pm_arg[0], rate, security_flag);
SMC_RET2(handle, (uint64_t)ret | ((uint64_t)rate[0] << 32),
rate[1]);
}
case PM_PLL_SET_PARAMETER:
- ret = pm_pll_set_param(pm_arg[0], pm_arg[1], pm_arg[2]);
+ ret = pm_pll_set_param(pm_arg[0], pm_arg[1], pm_arg[2],
+ security_flag);
SMC_RET1(handle, (uint64_t)ret);
case PM_PLL_GET_PARAMETER:
{
uint32_t value;
- ret = pm_pll_get_param(pm_arg[0], pm_arg[1], &value);
+ ret = pm_pll_get_param(pm_arg[0], pm_arg[1], &value,
+ security_flag);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value << 32));
}
case PM_PLL_SET_MODE:
- ret = pm_pll_set_mode(pm_arg[0], pm_arg[1]);
+ ret = pm_pll_set_mode(pm_arg[0], pm_arg[1], security_flag);
SMC_RET1(handle, (uint64_t)ret);
case PM_PLL_GET_MODE:
{
uint32_t mode;
- ret = pm_pll_get_mode(pm_arg[0], &mode);
+ ret = pm_pll_get_mode(pm_arg[0], &mode, security_flag);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)mode << 32));
}
@@ -305,7 +386,7 @@
{
uint32_t result[2];
- ret = pm_get_chipid(result);
+ ret = pm_get_chipid(result, security_flag);
SMC_RET2(handle, (uint64_t)ret | ((uint64_t)result[0] << 32),
result[1]);
}
@@ -314,13 +395,14 @@
{
uint32_t version;
- ret = pm_feature_check(pm_arg[0], &version);
+ ret = pm_feature_check(pm_arg[0], &version, security_flag);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)version << 32));
}
case PM_LOAD_PDI:
{
- ret = pm_load_pdi(pm_arg[0], pm_arg[1], pm_arg[2]);
+ ret = pm_load_pdi(pm_arg[0], pm_arg[1], pm_arg[2],
+ security_flag);
SMC_RET1(handle, (uint64_t)ret);
}
@@ -328,19 +410,21 @@
{
uint32_t result;
- ret = pm_get_op_characteristic(pm_arg[0], pm_arg[1], &result);
+ ret = pm_get_op_characteristic(pm_arg[0], pm_arg[1], &result,
+ security_flag);
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)result << 32));
}
case PM_SET_MAX_LATENCY:
{
- ret = pm_set_max_latency(pm_arg[0], pm_arg[1]);
+ ret = pm_set_max_latency(pm_arg[0], pm_arg[1], security_flag);
SMC_RET1(handle, (uint64_t)ret);
}
case PM_REGISTER_NOTIFIER:
{
- ret = pm_register_notifier(pm_arg[0], pm_arg[1], pm_arg[2], pm_arg[3]);
+ ret = pm_register_notifier(pm_arg[0], pm_arg[1], pm_arg[2],
+ pm_arg[3], security_flag);
SMC_RET1(handle, (uint64_t)ret);
}
diff --git a/plat/xilinx/versal/pm_service/pm_svc_main.h b/plat/xilinx/versal/pm_service/pm_svc_main.h
index 71329ca..4f8dc2b 100644
--- a/plat/xilinx/versal/pm_service/pm_svc_main.h
+++ b/plat/xilinx/versal/pm_service/pm_svc_main.h
@@ -14,4 +14,5 @@
uint64_t x4, void *cookie, void *handle,
uint64_t flags);
+int pm_register_sgi(unsigned int sgi_num);
#endif /* PM_SVC_MAIN_H */
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index d6313a6..fae73cf 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -62,144 +62,151 @@
} zynqmp_devices[] = {
{
.id = 0x10,
- .name = "3EG",
+ .name = "XCZU3EG",
},
{
.id = 0x10,
.ver = 0x2c,
- .name = "3CG",
+ .name = "XCZU3CG",
},
{
.id = 0x11,
- .name = "2EG",
+ .name = "XCZU2EG",
},
{
.id = 0x11,
.ver = 0x2c,
- .name = "2CG",
+ .name = "XCZU2CG",
},
{
.id = 0x20,
- .name = "5EV",
+ .name = "XCZU5EV",
.evexists = true,
},
{
.id = 0x20,
.ver = 0x100,
- .name = "5EG",
+ .name = "XCZU5EG",
.evexists = true,
},
{
.id = 0x20,
.ver = 0x12c,
- .name = "5CG",
+ .name = "XCZU5CG",
},
{
.id = 0x21,
- .name = "4EV",
+ .name = "XCZU4EV",
.evexists = true,
},
{
.id = 0x21,
.ver = 0x100,
- .name = "4EG",
+ .name = "XCZU4EG",
.evexists = true,
},
{
.id = 0x21,
.ver = 0x12c,
- .name = "4CG",
+ .name = "XCZU4CG",
},
{
.id = 0x30,
- .name = "7EV",
+ .name = "XCZU7EV",
.evexists = true,
},
{
.id = 0x30,
.ver = 0x100,
- .name = "7EG",
+ .name = "XCZU7EG",
.evexists = true,
},
{
.id = 0x30,
.ver = 0x12c,
- .name = "7CG",
+ .name = "XCZU7CG",
},
{
.id = 0x38,
- .name = "9EG",
+ .name = "XCZU9EG",
},
{
.id = 0x38,
.ver = 0x2c,
- .name = "9CG",
+ .name = "XCZU9CG",
},
{
.id = 0x39,
- .name = "6EG",
+ .name = "XCZU6EG",
},
{
.id = 0x39,
.ver = 0x2c,
- .name = "6CG",
+ .name = "XCZU6CG",
},
{
.id = 0x40,
- .name = "11EG",
- },
- { /* For testing purpose only */
- .id = 0x50,
- .ver = 0x2c,
- .name = "15CG",
+ .name = "XCZU11EG",
},
{
.id = 0x50,
- .name = "15EG",
+ .name = "XCZU15EG",
},
{
.id = 0x58,
- .name = "19EG",
+ .name = "XCZU19EG",
},
{
.id = 0x59,
- .name = "17EG",
+ .name = "XCZU17EG",
},
{
.id = 0x60,
- .name = "28DR",
+ .name = "XCZU28DR",
},
{
.id = 0x61,
- .name = "21DR",
+ .name = "XCZU21DR",
},
{
.id = 0x62,
- .name = "29DR",
+ .name = "XCZU29DR",
},
{
.id = 0x63,
- .name = "23DR",
+ .name = "XCZU23DR",
},
{
.id = 0x64,
- .name = "27DR",
+ .name = "XCZU27DR",
},
{
.id = 0x65,
- .name = "25DR",
+ .name = "XCZU25DR",
},
{
.id = 0x66,
- .name = "39DR",
+ .name = "XCZU39DR",
+ },
+ {
+ .id = 0x7d,
+ .name = "XCZU43DR",
+ },
+ {
+ .id = 0x78,
+ .name = "XCZU46DR",
+ },
+ {
+ .id = 0x7f,
+ .name = "XCZU47DR",
},
{
.id = 0x7b,
- .name = "48DR",
+ .name = "XCZU48DR",
},
{
.id = 0x7e,
- .name = "49DR",
+ .name = "XCZU49DR",
},
};
@@ -207,6 +214,8 @@
#define ZYNQMP_PL_STATUS_MASK BIT(ZYNQMP_PL_STATUS_BIT)
#define ZYNQMP_CSU_VERSION_MASK ~(ZYNQMP_PL_STATUS_MASK)
+#define SILICON_ID_XCK26 0x4724093
+
static char *zynqmp_get_silicon_idcode_name(void)
{
uint32_t id, ver, chipid[2];
@@ -224,7 +233,7 @@
chipid[1] = mmio_read_32(EFUSE_BASEADDR + EFUSE_IPDISABLE_OFFSET);
#else
if (pm_get_chipid(chipid) != PM_RET_SUCCESS)
- return "UNKN";
+ return "XCZUUNKN";
#endif
id = chipid[0] & (ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
@@ -238,8 +247,13 @@
break;
}
- if (i >= ARRAY_SIZE(zynqmp_devices))
- return "UNKN";
+ if (i >= ARRAY_SIZE(zynqmp_devices)) {
+ if (chipid[0] == SILICON_ID_XCK26) {
+ return "XCK26";
+ } else {
+ return "XCZUUNKN";
+ }
+ }
if (!zynqmp_devices[i].evexists)
return zynqmp_devices[i].name;
@@ -315,9 +329,10 @@
break;
}
- NOTICE("ATF running on XCZU%s/%s v%d/RTL%d.%d at 0x%x\n",
- zynqmp_print_silicon_idcode(), label, zynqmp_get_ps_ver(),
- (rtl & 0xf0) >> 4, rtl & 0xf, BL31_BASE);
+ NOTICE("TF-A running on %s/%s at 0x%x\n",
+ zynqmp_print_silicon_idcode(), label, BL31_BASE);
+ VERBOSE("TF-A running on v%d/RTL%d.%d\n",
+ zynqmp_get_ps_ver(), (rtl & 0xf0) >> 4, rtl & 0xf);
}
#else
static inline void zynqmp_print_platform_name(void) { }
@@ -338,10 +353,19 @@
void zynqmp_config_setup(void)
{
+ uint64_t counter_freq;
+
/* Configure IPI data for ZynqMP */
zynqmp_ipi_config_table_init();
zynqmp_print_platform_name();
+
+ /* Configure counter frequency */
+ counter_freq = read_cntfrq_el0();
+ if (counter_freq == ZYNQMP_DEFAULT_COUNTER_FREQ) {
+ write_cntfrq_el0(plat_get_syscnt_freq2());
+ }
+
generic_delay_timer_init();
}
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S b/plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S
index 7eab337..d8439f7 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S
@@ -12,9 +12,6 @@
.globl plat_is_my_cpu_primary
.globl zynqmp_calc_core_pos
.globl plat_my_core_pos
- .globl plat_crash_console_init
- .globl plat_crash_console_putc
- .globl plat_crash_console_flush
.globl platform_mem_init
/* -----------------------------------------------------
@@ -79,45 +76,6 @@
ret
endfunc zynqmp_calc_core_pos
- /* ---------------------------------------------
- * int plat_crash_console_init(void)
- * Function to initialize the crash console
- * without a C Runtime to print crash report.
- * Clobber list : x0 - x4
- * ---------------------------------------------
- */
-func plat_crash_console_init
- mov_imm x0, ZYNQMP_CRASH_UART_BASE
- mov_imm x1, ZYNQMP_CRASH_UART_CLK_IN_HZ
- mov_imm x2, ZYNQMP_UART_BAUDRATE
- b console_cdns_core_init
-endfunc plat_crash_console_init
-
- /* ---------------------------------------------
- * int plat_crash_console_putc(int c)
- * Function to print a character on the crash
- * console without a C Runtime.
- * Clobber list : x1, x2
- * ---------------------------------------------
- */
-func plat_crash_console_putc
- mov_imm x1, ZYNQMP_CRASH_UART_BASE
- b console_cdns_core_putc
-endfunc plat_crash_console_putc
-
- /* ---------------------------------------------
- * void plat_crash_console_flush()
- * Function to force a write of all buffered
- * data that hasn't been output.
- * Out : void.
- * Clobber list : r0
- * ---------------------------------------------
- */
-func plat_crash_console_flush
- mov_imm x0, ZYNQMP_CRASH_UART_BASE
- b console_cdns_core_flush
-endfunc plat_crash_console_flush
-
/* ---------------------------------------------------------------------
* We don't need to carry out any memory initialization on ARM
* platforms. The Secure RAM is accessible straight away.
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
index d4cd7f6..47be4e1 100644
--- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
+++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -10,6 +10,7 @@
#include <bl31/bl31.h>
#include <common/bl_common.h>
#include <common/debug.h>
+#include <drivers/arm/dcc.h>
#include <drivers/console.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
@@ -19,6 +20,10 @@
#include <plat_private.h>
#include <zynqmp_def.h>
+#include <common/fdt_fixup.h>
+#include <common/fdt_wrappers.h>
+#include <libfdt.h>
+
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
@@ -62,15 +67,23 @@
u_register_t arg2, u_register_t arg3)
{
uint64_t atf_handoff_addr;
- /* Register the console to provide early debug support */
- static console_t bl31_boot_console;
- (void)console_cdns_register(ZYNQMP_UART_BASE,
- zynqmp_get_uart_clk(),
- ZYNQMP_UART_BAUDRATE,
- &bl31_boot_console);
- console_set_scope(&bl31_boot_console,
- CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT);
+ if (ZYNQMP_CONSOLE_IS(cadence)) {
+ /* Register the console to provide early debug support */
+ static console_t bl31_boot_console;
+ (void)console_cdns_register(ZYNQMP_UART_BASE,
+ zynqmp_get_uart_clk(),
+ ZYNQMP_UART_BAUDRATE,
+ &bl31_boot_console);
+ console_set_scope(&bl31_boot_console,
+ CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT);
+ } else if (ZYNQMP_CONSOLE_IS(dcc)) {
+ /* Initialize the dcc console for debug */
+ int rc = console_dcc_register();
+ if (rc == 0) {
+ panic();
+ }
+ }
/* Initialize the platform config for future decision making */
zynqmp_config_setup();
@@ -114,25 +127,6 @@
}
}
-/* Enable the test setup */
-#ifndef ZYNQMP_TESTING
-static void zynqmp_testing_setup(void) { }
-#else
-static void zynqmp_testing_setup(void)
-{
- uint32_t actlr_el3, actlr_el2;
-
- /* Enable CPU ACTLR AND L2ACTLR RW access from non-secure world */
- actlr_el3 = read_actlr_el3();
- actlr_el2 = read_actlr_el2();
-
- actlr_el3 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT;
- actlr_el2 |= ACTLR_EL3_L2ACTLR_BIT | ACTLR_EL3_CPUACTLR_BIT;
- write_actlr_el3(actlr_el3);
- write_actlr_el2(actlr_el2);
-}
-#endif
-
#if ZYNQMP_WDT_RESTART
static interrupt_type_handler_t type_el3_interrupt_table[MAX_INTR_EL3];
@@ -169,12 +163,58 @@
}
#endif
+#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
+static void prepare_dtb(void)
+{
+ void *dtb = (void *)XILINX_OF_BOARD_DTB_ADDR;
+ int ret;
+
+ /* Return if no device tree is detected */
+ if (fdt_check_header(dtb) != 0) {
+ NOTICE("Can't read DT at 0x%p\n", dtb);
+ return;
+ }
+
+ ret = fdt_open_into(dtb, dtb, XILINX_OF_BOARD_DTB_MAX_SIZE);
+ if (ret < 0) {
+ ERROR("Invalid Device Tree at %p: error %d\n", dtb, ret);
+ return;
+ }
+
+ if (dt_add_psci_node(dtb)) {
+ ERROR("Failed to add PSCI Device Tree node\n");
+ return;
+ }
+
+ if (dt_add_psci_cpu_enable_methods(dtb)) {
+ ERROR("Failed to add PSCI cpu enable methods in Device Tree\n");
+ return;
+ }
+
+ /* Reserve memory used by Trusted Firmware. */
+ if (fdt_add_reserved_memory(dtb, "tf-a", BL31_BASE, BL31_LIMIT - BL31_BASE)) {
+ WARN("Failed to add reserved memory nodes to DT.\n");
+ }
+
+ ret = fdt_pack(dtb);
+ if (ret < 0) {
+ ERROR("Failed to pack Device Tree at %p: error %d\n", dtb, ret);
+ }
+
+ clean_dcache_range((uintptr_t)dtb, fdt_blob_size(dtb));
+ INFO("Changed device tree to advertise PSCI and reserved memories.\n");
+}
+#endif
+
void bl31_platform_setup(void)
{
+#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
+ prepare_dtb();
+#endif
+
/* Initialize the gic cpu and distributor interfaces */
plat_arm_gic_driver_init();
plat_arm_gic_init();
- zynqmp_testing_setup();
}
void bl31_plat_runtime_setup(void)
@@ -202,6 +242,10 @@
const mmap_region_t bl_regions[] = {
+#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
+ MAP_REGION_FLAT(XILINX_OF_BOARD_DTB_ADDR, XILINX_OF_BOARD_DTB_MAX_SIZE,
+ MT_MEMORY | MT_RW | MT_NS),
+#endif
MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
MT_MEMORY | MT_RW | MT_SECURE),
MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
diff --git a/plat/xilinx/zynqmp/include/plat_pm_common.h b/plat/xilinx/zynqmp/include/plat_pm_common.h
index 56a747a..a57aebe 100644
--- a/plat/xilinx/zynqmp/include/plat_pm_common.h
+++ b/plat/xilinx/zynqmp/include/plat_pm_common.h
@@ -16,17 +16,6 @@
#include <common/debug.h>
#include "pm_defs.h"
-#if ZYNQMP_IPI_CRC_CHECK
-#define PAYLOAD_ARG_CNT 8U
-#define IPI_W0_TO_W6_SIZE 28U
-#define PAYLOAD_CRC_POS 7U
-#define CRC_INIT_VALUE 0x4F4EU
-#define CRC_ORDER 16U
-#define CRC_POLYNOM 0x8005U
-#else
-#define PAYLOAD_ARG_CNT 6U
-#endif
-#define PAYLOAD_ARG_SIZE 4U /* size in bytes */
#define ZYNQMP_TZ_VERSION_MAJOR 1
#define ZYNQMP_TZ_VERSION_MINOR 0
diff --git a/plat/xilinx/zynqmp/include/platform_def.h b/plat/xilinx/zynqmp/include/platform_def.h
index 2796840..0c14315 100644
--- a/plat/xilinx/zynqmp/include/platform_def.h
+++ b/plat/xilinx/zynqmp/include/platform_def.h
@@ -36,7 +36,7 @@
* little space for growth.
*/
#ifndef ZYNQMP_ATF_MEM_BASE
-#if !DEBUG && defined(SPD_none)
+#if !DEBUG && defined(SPD_none) && !SDEI_SUPPORT
# define BL31_BASE 0xfffea000
# define BL31_LIMIT 0xffffffff
#else
@@ -83,14 +83,29 @@
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
+#define XILINX_OF_BOARD_DTB_ADDR 0x100000
+#define XILINX_OF_BOARD_DTB_MAX_SIZE 0x200000
+#define PLAT_DDR_LOWMEM_MAX 0x80000000
+
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
+#if (BL31_LIMIT < PLAT_DDR_LOWMEM_MAX)
+#define MAX_MMAP_REGIONS 8
+#else
#define MAX_MMAP_REGIONS 7
+#endif
#define MAX_XLAT_TABLES 5
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
+#define ZYNQMP_SDEI_SGI_PRIVATE U(8)
+
+/* Platform macros to support exception handling framework */
+#define PLAT_PRI_BITS U(3)
+#define PLAT_SDEI_CRITICAL_PRI 0x10
+#define PLAT_SDEI_NORMAL_PRI 0x20
+
#define PLAT_ARM_GICD_BASE BASE_GICD_BASE
#define PLAT_ARM_GICC_BASE BASE_GICC_BASE
/*
@@ -102,8 +117,6 @@
#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_LEVEL), \
- INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
- GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
@@ -124,8 +137,6 @@
GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(IRQ_TTC3_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
- INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
- GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
@@ -142,6 +153,8 @@
GIC_INTR_CFG_EDGE)
#endif
-#define PLAT_ARM_G0_IRQ_PROPS(grp)
+#define PLAT_ARM_G0_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, grp, \
+ GIC_INTR_CFG_EDGE)
#endif /* PLATFORM_DEF_H */
diff --git a/plat/xilinx/zynqmp/include/zynqmp_def.h b/plat/xilinx/zynqmp/include/zynqmp_def.h
index f474630..7e58391 100644
--- a/plat/xilinx/zynqmp/include/zynqmp_def.h
+++ b/plat/xilinx/zynqmp/include/zynqmp_def.h
@@ -17,6 +17,9 @@
#define ZYNQMP_CONSOLE_IS(con) (ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE)
+/* Default counter frequency */
+#define ZYNQMP_DEFAULT_COUNTER_FREQ 0U
+
/* Firmware Image Package */
#define ZYNQMP_PRIMARY_CPU 0
diff --git a/plat/xilinx/zynqmp/plat_psci.c b/plat/xilinx/zynqmp/plat_psci.c
index f579f79..f78b88c 100644
--- a/plat/xilinx/zynqmp/plat_psci.c
+++ b/plat/xilinx/zynqmp/plat_psci.c
@@ -179,14 +179,6 @@
return PSCI_E_SUCCESS;
}
-int zynqmp_validate_ns_entrypoint(unsigned long ns_entrypoint)
-{
- VERBOSE("%s: ns_entrypoint: 0x%lx\n", __func__, ns_entrypoint);
-
- /* FIXME: Actually validate */
- return PSCI_E_SUCCESS;
-}
-
void zynqmp_get_sys_suspend_power_state(psci_power_state_t *req_state)
{
req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE;
@@ -206,7 +198,6 @@
.system_off = zynqmp_system_off,
.system_reset = zynqmp_system_reset,
.validate_power_state = zynqmp_validate_power_state,
- .validate_ns_entrypoint = zynqmp_validate_ns_entrypoint,
.get_sys_suspend_power_state = zynqmp_get_sys_suspend_power_state,
};
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index 1cd168f..d075a56 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
@@ -9,11 +9,13 @@
A53_DISABLE_NON_TEMPORAL_HINT := 0
SEPARATE_CODE_AND_RODATA := 1
ZYNQMP_WDT_RESTART := 0
-ZYNQMP_IPI_CRC_CHECK := 0
+IPI_CRC_CHECK := 0
override RESET_TO_BL31 := 1
override GICV2_G0_FOR_EL3 := 1
override WARMBOOT_ENABLE_DCACHE_EARLY := 1
+EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
+
# Do not enable SVE
ENABLE_SVE_FOR_NS := 0
@@ -41,15 +43,17 @@
$(eval $(call add_define,ZYNQMP_BL32_MEM_SIZE))
endif
-ZYNQMP_CONSOLE ?= cadence
-$(eval $(call add_define_val,ZYNQMP_CONSOLE,ZYNQMP_CONSOLE_ID_${ZYNQMP_CONSOLE}))
ifdef ZYNQMP_WDT_RESTART
$(eval $(call add_define,ZYNQMP_WDT_RESTART))
endif
ifdef ZYNQMP_IPI_CRC_CHECK
- $(eval $(call add_define,ZYNQMP_IPI_CRC_CHECK))
+ $(warning "ZYNQMP_IPI_CRC_CHECK macro is deprecated...instead please use IPI_CRC_CHECK.")
+endif
+
+ifdef IPI_CRC_CHECK
+ $(eval $(call add_define,IPI_CRC_CHECK))
endif
PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
@@ -59,11 +63,13 @@
-Iplat/xilinx/zynqmp/include/ \
-Iplat/xilinx/zynqmp/pm_service/ \
+include lib/libfdt/libfdt.mk
# Include GICv2 driver files
include drivers/arm/gic/v2/gicv2.mk
PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
lib/xlat_tables/aarch64/xlat_tables.c \
+ drivers/arm/dcc/dcc_console.c \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
${GICV2_SOURCES} \
@@ -73,14 +79,24 @@
plat/arm/common/arm_gicv2.c \
plat/common/plat_gicv2.c \
plat/xilinx/common/ipi.c \
- plat/xilinx/zynqmp/zynqmp_ipi.c \
+ plat/xilinx/zynqmp/zynqmp_ipi.c \
+ plat/common/aarch64/crash_console_helpers.S \
plat/xilinx/zynqmp/aarch64/zynqmp_helpers.S \
plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+ZYNQMP_CONSOLE ?= cadence
+ifeq (${ZYNQMP_CONSOLE}, $(filter ${ZYNQMP_CONSOLE},cadence cadence0 cadence1 dcc))
+else
+ $(error "Please define ZYNQMP_CONSOLE")
+endif
+$(eval $(call add_define_val,ZYNQMP_CONSOLE,ZYNQMP_CONSOLE_ID_${ZYNQMP_CONSOLE}))
+
BL31_SOURCES += drivers/arm/cci/cci.c \
lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
plat/common/plat_psci_common.c \
+ common/fdt_fixup.c \
+ ${LIBFDT_SRCS} \
plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c \
plat/xilinx/common/pm_service/pm_ipi.c \
plat/xilinx/common/plat_startup.c \
@@ -96,6 +112,11 @@
plat/xilinx/zynqmp/pm_service/pm_api_clock.c \
plat/xilinx/zynqmp/pm_service/pm_client.c
+ifeq (${SDEI_SUPPORT},1)
+BL31_SOURCES += plat/xilinx/zynqmp/zynqmp_ehf.c \
+ plat/xilinx/zynqmp/zynqmp_sdei.c
+endif
+
BL31_CPPFLAGS += -fno-jump-tables
ifneq (${RESET_TO_BL31},1)
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
index f165fb0..9c5af88 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
@@ -677,6 +677,10 @@
case IOCTL_AFI:
ret = pm_ioctl_afi(arg1, arg2);
break;
+ case IOCTL_SET_FEATURE_CONFIG:
+ case IOCTL_GET_FEATURE_CONFIG:
+ ret = pm_feature_config(ioctl_id, arg1, arg2, value);
+ break;
default:
ret = PM_RET_ERROR_NOTSUPPORTED;
break;
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h
index 337f732..f18dc00 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h
@@ -15,28 +15,43 @@
//ioctl id
enum {
- IOCTL_GET_RPU_OPER_MODE,
- IOCTL_SET_RPU_OPER_MODE,
- IOCTL_RPU_BOOT_ADDR_CONFIG,
- IOCTL_TCM_COMB_CONFIG,
- IOCTL_SET_TAPDELAY_BYPASS,
- IOCTL_SET_SGMII_MODE,
- IOCTL_SD_DLL_RESET,
- IOCTL_SET_SD_TAPDELAY,
+ IOCTL_GET_RPU_OPER_MODE = 0,
+ IOCTL_SET_RPU_OPER_MODE = 1,
+ IOCTL_RPU_BOOT_ADDR_CONFIG = 2,
+ IOCTL_TCM_COMB_CONFIG = 3,
+ IOCTL_SET_TAPDELAY_BYPASS = 4,
+ IOCTL_SET_SGMII_MODE = 5,
+ IOCTL_SD_DLL_RESET = 6,
+ IOCTL_SET_SD_TAPDELAY = 7,
/* Ioctl for clock driver */
- IOCTL_SET_PLL_FRAC_MODE,
- IOCTL_GET_PLL_FRAC_MODE,
- IOCTL_SET_PLL_FRAC_DATA,
- IOCTL_GET_PLL_FRAC_DATA,
- IOCTL_WRITE_GGS,
- IOCTL_READ_GGS,
- IOCTL_WRITE_PGGS,
- IOCTL_READ_PGGS,
+ IOCTL_SET_PLL_FRAC_MODE = 8,
+ IOCTL_GET_PLL_FRAC_MODE = 9,
+ IOCTL_SET_PLL_FRAC_DATA = 10,
+ IOCTL_GET_PLL_FRAC_DATA = 11,
+ IOCTL_WRITE_GGS = 12,
+ IOCTL_READ_GGS = 13,
+ IOCTL_WRITE_PGGS = 14,
+ IOCTL_READ_PGGS = 15,
/* IOCTL for ULPI reset */
- IOCTL_ULPI_RESET,
+ IOCTL_ULPI_RESET = 16,
/* Set healthy bit value */
- IOCTL_SET_BOOT_HEALTH_STATUS,
- IOCTL_AFI,
+ IOCTL_SET_BOOT_HEALTH_STATUS = 17,
+ IOCTL_AFI = 18,
+ /* Probe counter read/write */
+ IOCTL_PROBE_COUNTER_READ = 19,
+ IOCTL_PROBE_COUNTER_WRITE = 20,
+ IOCTL_OSPI_MUX_SELECT = 21,
+ /* IOCTL for USB power request */
+ IOCTL_USB_SET_STATE = 22,
+ /* IOCTL to get last reset reason */
+ IOCTL_GET_LAST_RESET_REASON = 23,
+ /* AI engine NPI ISR clear */
+ IOCTL_AIE_ISR_CLEAR = 24,
+ /* Register SGI to ATF */
+ IOCTL_REGISTER_SGI = 25,
+ /* Runtime feature configuration */
+ IOCTL_SET_FEATURE_CONFIG = 26,
+ IOCTL_GET_FEATURE_CONFIG = 27,
};
//RPU operation mode
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
index 9a53408..5d9408c 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_sys.c
@@ -209,7 +209,7 @@
/* TODO: allow passing the node ID of the affected CPU */
PM_PACK_PAYLOAD3(payload, PM_ABORT_SUSPEND, reason,
primary_proc->node_id);
- return pm_ipi_send(primary_proc, payload);
+ return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
}
/**
@@ -228,7 +228,7 @@
PM_PACK_PAYLOAD4(payload, PM_SET_WAKEUP_SOURCE, target, wkup_node,
enable);
- return pm_ipi_send(primary_proc, payload);
+ return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
}
/**
@@ -316,7 +316,7 @@
uint32_t payload[PAYLOAD_ARG_CNT];
PM_PACK_PAYLOAD2(payload, PM_RELEASE_NODE, nid);
- return pm_ipi_send(primary_proc, payload);
+ return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
}
/**
@@ -332,7 +332,7 @@
uint32_t payload[PAYLOAD_ARG_CNT];
PM_PACK_PAYLOAD3(payload, PM_SET_MAX_LATENCY, nid, latency);
- return pm_ipi_send(primary_proc, payload);
+ return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
}
/* Miscellaneous API functions */
@@ -461,7 +461,7 @@
/* Send request to the PMU */
PM_PACK_PAYLOAD3(payload, PM_RESET_ASSERT, reset, assert);
- return pm_ipi_send(primary_proc, payload);
+ return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
}
/**
@@ -1648,3 +1648,36 @@
EM_PACK_PAYLOAD1(payload, EM_SEND_ERRORS);
return pm_ipi_send_sync(primary_proc, payload, value, 1);
}
+
+/**
+ * pm_feature_config() - feature configuration at runtime
+ *
+ * This function is used to send IPI request to PMUFW to configure feature
+ * at runtime. The feature can be enable or disable as well as the feature
+ * can be configure at runtime using an IOCTL call.
+ *
+ * @ioctl_id The ioctl id for the feature configuration
+ * @config_id The config id of the feature to be configured
+ * @value The value to be configured
+ * @response Return to reference pointer
+ *
+ * @return Returns 0 on success or error value on failure
+ */
+enum pm_ret_status pm_feature_config(unsigned int ioctl_id,
+ unsigned int config_id,
+ unsigned int value,
+ unsigned int *response)
+{
+ uint32_t payload[PAYLOAD_ARG_CNT];
+
+ /* Send request to the PMU */
+ PM_PACK_PAYLOAD5(payload, PM_IOCTL, 0, ioctl_id, config_id, value);
+
+ if (ioctl_id == IOCTL_GET_FEATURE_CONFIG) {
+ return pm_ipi_send_sync(primary_proc, payload, response, 1);
+ } else if (ioctl_id == IOCTL_SET_FEATURE_CONFIG) {
+ return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
+ } else {
+ return PM_RET_ERROR_ARGS;
+ }
+}
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_sys.h b/plat/xilinx/zynqmp/pm_service/pm_api_sys.h
index b0c2652..ca07cef 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_sys.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_sys.h
@@ -202,4 +202,9 @@
enum pm_ret_status em_remove_action(unsigned int *value);
enum pm_ret_status em_send_errors(unsigned int *value);
+enum pm_ret_status pm_feature_config(unsigned int ioctl_id,
+ unsigned int config_id,
+ unsigned int value,
+ unsigned int *response);
+
#endif /* PM_API_SYS_H */
diff --git a/plat/xilinx/zynqmp/zynqmp_ehf.c b/plat/xilinx/zynqmp/zynqmp_ehf.c
new file mode 100644
index 0000000..fbf1ed0
--- /dev/null
+++ b/plat/xilinx/zynqmp/zynqmp_ehf.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) Siemens AG, 2020-2021
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform_def.h>
+
+#include <bl31/ehf.h>
+
+/*
+ * Enumeration of priority levels on ARM platforms.
+ */
+ehf_pri_desc_t zynqmp_exceptions[] = {
+ /* Critical priority SDEI */
+ EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_CRITICAL_PRI),
+
+ /* Normal priority SDEI */
+ EHF_PRI_DESC(PLAT_PRI_BITS, PLAT_SDEI_NORMAL_PRI),
+};
+
+/* Plug in ARM exceptions to Exception Handling Framework. */
+EHF_REGISTER_PRIORITIES(zynqmp_exceptions, ARRAY_SIZE(zynqmp_exceptions), PLAT_PRI_BITS);
diff --git a/plat/xilinx/zynqmp/zynqmp_sdei.c b/plat/xilinx/zynqmp/zynqmp_sdei.c
new file mode 100644
index 0000000..7e92b58
--- /dev/null
+++ b/plat/xilinx/zynqmp/zynqmp_sdei.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) Siemens AG, 2020-2021
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* SDEI configuration for ARM platforms */
+
+#include <bl31/ehf.h>
+#include <common/debug.h>
+#include <services/sdei.h>
+
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+int arm_validate_ns_entrypoint(uintptr_t entrypoint)
+{
+ return (entrypoint < BL31_BASE || entrypoint > BL31_LIMIT) ? 0 : -1;
+}
+
+/* Private event mappings */
+static sdei_ev_map_t zynqmp_sdei_private[] = {
+ SDEI_DEFINE_EVENT_0(ZYNQMP_SDEI_SGI_PRIVATE),
+};
+
+/* Shared event mappings */
+static sdei_ev_map_t zynqmp_sdei_shared[] = {
+};
+
+void plat_sdei_setup(void)
+{
+ INFO("SDEI platform setup\n");
+}
+
+/* Export ARM SDEI events */
+REGISTER_SDEI_MAP(zynqmp_sdei_private, zynqmp_sdei_shared);
diff --git a/services/spd/tspd/tspd_main.c b/services/spd/tspd/tspd_main.c
index b0cbf62..29fc238 100644
--- a/services/spd/tspd/tspd_main.c
+++ b/services/spd/tspd/tspd_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -92,6 +92,18 @@
* This function is the handler registered for S-EL1 interrupts by the TSPD. It
* validates the interrupt and upon success arranges entry into the TSP at
* 'tsp_sel1_intr_entry()' for handling the interrupt.
+ * Typically, interrupts for a specific security state get handled in the same
+ * security execption level if the execution is in the same security state. For
+ * example, if a non-secure interrupt gets fired when CPU is executing in NS-EL2
+ * it gets handled in the non-secure world.
+ * However, interrupts belonging to the opposite security state typically demand
+ * a world(context) switch. This is inline with the security principle which
+ * states a secure interrupt has to be handled in the secure world.
+ * Hence, the TSPD in EL3 expects the context(handle) for a secure interrupt to
+ * be non-secure and vice versa.
+ * However, a race condition between non-secure and secure interrupts can lead to
+ * a scenario where the above assumptions do not hold true. This is demonstrated
+ * below through Note 1.
******************************************************************************/
static uint64_t tspd_sel1_interrupt_handler(uint32_t id,
uint32_t flags,
@@ -101,6 +113,60 @@
uint32_t linear_id;
tsp_context_t *tsp_ctx;
+ /* Get a reference to this cpu's TSP context */
+ linear_id = plat_my_core_pos();
+ tsp_ctx = &tspd_sp_context[linear_id];
+
+#if TSP_NS_INTR_ASYNC_PREEMPT
+
+ /*
+ * Note 1:
+ * Under the current interrupt routing model, interrupts from other
+ * world are routed to EL3 when TSP_NS_INTR_ASYNC_PREEMPT is enabled.
+ * Consider the following scenario:
+ * 1/ A non-secure payload(like tftf) requests a secure service from
+ * TSP by invoking a yielding SMC call.
+ * 2/ Later, execution jumps to TSP in S-EL1 with the help of TSP
+ * Dispatcher in Secure Monitor(EL3).
+ * 3/ While CPU is executing TSP, a Non-secure interrupt gets fired.
+ * this demands a context switch to the non-secure world through
+ * secure monitor.
+ * 4/ Consequently, TSP in S-EL1 get asynchronously pre-empted and
+ * execution switches to secure monitor(EL3).
+ * 5/ EL3 tries to triage the (Non-secure) interrupt based on the
+ * highest pending interrupt.
+ * 6/ However, while the NS Interrupt was pending, secure timer gets
+ * fired which makes a S-EL1 interrupt to be pending.
+ * 7/ Hence, execution jumps to this companion handler of S-EL1
+ * interrupt (i.e., tspd_sel1_interrupt_handler) even though the TSP
+ * was pre-empted due to non-secure interrupt.
+ * 8/ The above sequence of events explain how TSP was pre-empted by
+ * S-EL1 interrupt indirectly in an asynchronous way.
+ * 9/ Hence, we track the TSP pre-emption by S-EL1 interrupt using a
+ * boolean variable per each core.
+ * 10/ This helps us to indicate that SMC call for TSP service was
+ * pre-empted when execution resumes in non-secure world.
+ */
+
+ /* Check the security state when the exception was generated */
+ if (get_interrupt_src_ss(flags) == NON_SECURE) {
+ /* Sanity check the pointer to this cpu's context */
+ assert(handle == cm_get_context(NON_SECURE));
+
+ /* Save the non-secure context before entering the TSP */
+ cm_el1_sysregs_context_save(NON_SECURE);
+ tsp_ctx->preempted_by_sel1_intr = false;
+ } else {
+ /* Sanity check the pointer to this cpu's context */
+ assert(handle == cm_get_context(SECURE));
+
+ /* Save the secure context before entering the TSP for S-EL1
+ * interrupt handling
+ */
+ cm_el1_sysregs_context_save(SECURE);
+ tsp_ctx->preempted_by_sel1_intr = true;
+ }
+#else
/* Check the security state when the exception was generated */
assert(get_interrupt_src_ss(flags) == NON_SECURE);
@@ -109,10 +175,8 @@
/* Save the non-secure context before entering the TSP */
cm_el1_sysregs_context_save(NON_SECURE);
+#endif
- /* Get a reference to this cpu's TSP context */
- linear_id = plat_my_core_pos();
- tsp_ctx = &tspd_sp_context[linear_id];
assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE));
/*
@@ -131,7 +195,6 @@
tsp_ctx->saved_elr_el3 = SMC_GET_EL3(&tsp_ctx->cpu_ctx,
CTX_ELR_EL3);
#if TSP_NS_INTR_ASYNC_PREEMPT
- /*Need to save the previously interrupted secure context */
memcpy(&tsp_ctx->sp_ctx, &tsp_ctx->cpu_ctx, TSPD_SP_CTX_SIZE);
#endif
}
@@ -353,7 +416,20 @@
cm_el1_sysregs_context_restore(NON_SECURE);
cm_set_next_eret_context(NON_SECURE);
+ /* Refer to Note 1 in function tspd_sel1_interrupt_handler()*/
+#if TSP_NS_INTR_ASYNC_PREEMPT
+ if (tsp_ctx->preempted_by_sel1_intr) {
+ /* Reset the flag */
+ tsp_ctx->preempted_by_sel1_intr = false;
+
+ SMC_RET1(ns_cpu_context, SMC_PREEMPTED);
+ } else {
+ SMC_RET0((uint64_t) ns_cpu_context);
+ }
+#else
SMC_RET0((uint64_t) ns_cpu_context);
+#endif
+
/*
* This function ID is used only by the SP to indicate it has
diff --git a/services/spd/tspd/tspd_private.h b/services/spd/tspd/tspd_private.h
index a81eb21..d6c03c9 100644
--- a/services/spd/tspd/tspd_private.h
+++ b/services/spd/tspd/tspd_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -188,6 +188,7 @@
uint64_t saved_tsp_args[TSP_NUM_ARGS];
#if TSP_NS_INTR_ASYNC_PREEMPT
sp_ctx_regs_t sp_ctx;
+ bool preempted_by_sel1_intr;
#endif
} tsp_context_t;
diff --git a/services/std_svc/pci_svc.c b/services/std_svc/pci_svc.c
new file mode 100644
index 0000000..a02b8a7
--- /dev/null
+++ b/services/std_svc/pci_svc.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stdint.h>
+
+#include <common/debug.h>
+#include <common/runtime_svc.h>
+#include <services/pci_svc.h>
+#include <services/std_svc.h>
+#include <smccc_helpers.h>
+
+static uint64_t validate_rw_addr_sz(uint32_t addr, uint64_t off, uint64_t sz)
+{
+ uint32_t nseg;
+ uint32_t ret;
+ uint32_t start_end_bus;
+
+ ret = pci_get_bus_for_seg(PCI_ADDR_SEG(addr), &start_end_bus, &nseg);
+
+ if (ret != SMC_PCI_CALL_SUCCESS) {
+ return SMC_PCI_CALL_INVAL_PARAM;
+ }
+ switch (sz) {
+ case SMC_PCI_SZ_8BIT:
+ case SMC_PCI_SZ_16BIT:
+ case SMC_PCI_SZ_32BIT:
+ break;
+ default:
+ return SMC_PCI_CALL_INVAL_PARAM;
+ }
+ if ((off + sz) > (PCI_OFFSET_MASK + 1U)) {
+ return SMC_PCI_CALL_INVAL_PARAM;
+ }
+ return SMC_PCI_CALL_SUCCESS;
+}
+
+uint64_t pci_smc_handler(uint32_t smc_fid,
+ u_register_t x1,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *cookie,
+ void *handle,
+ u_register_t flags)
+{
+ switch (smc_fid) {
+ case SMC_PCI_VERSION: {
+ pcie_version ver;
+
+ ver.major = 1U;
+ ver.minor = 0U;
+ SMC_RET4(handle, ver.val, 0U, 0U, 0U);
+ }
+ case SMC_PCI_FEATURES:
+ switch (x1) {
+ case SMC_PCI_VERSION:
+ case SMC_PCI_FEATURES:
+ case SMC_PCI_READ:
+ case SMC_PCI_WRITE:
+ case SMC_PCI_SEG_INFO:
+ SMC_RET1(handle, SMC_PCI_CALL_SUCCESS);
+ default:
+ SMC_RET1(handle, SMC_PCI_CALL_NOT_SUPPORTED);
+ }
+ break;
+ case SMC_PCI_READ: {
+ uint32_t ret;
+
+ if (validate_rw_addr_sz(x1, x2, x3) != SMC_PCI_CALL_SUCCESS) {
+ SMC_RET2(handle, SMC_PCI_CALL_INVAL_PARAM, 0U);
+ }
+ if (x4 != 0U) {
+ SMC_RET2(handle, SMC_PCI_CALL_INVAL_PARAM, 0U);
+ }
+ if (pci_read_config(x1, x2, x3, &ret) != 0U) {
+ SMC_RET2(handle, SMC_PCI_CALL_INVAL_PARAM, 0U);
+ } else {
+ SMC_RET2(handle, SMC_PCI_CALL_SUCCESS, ret);
+ }
+ break;
+ }
+ case SMC_PCI_WRITE: {
+ uint32_t ret;
+
+ if (validate_rw_addr_sz(x1, x2, x3) != SMC_PCI_CALL_SUCCESS) {
+ SMC_RET1(handle, SMC_PCI_CALL_INVAL_PARAM);
+ }
+ ret = pci_write_config(x1, x2, x3, x4);
+ SMC_RET1(handle, ret);
+ break;
+ }
+ case SMC_PCI_SEG_INFO: {
+ uint32_t nseg;
+ uint32_t ret;
+ uint32_t start_end_bus;
+
+ if ((x2 != 0U) || (x3 != 0U) || (x4 != 0U)) {
+ SMC_RET3(handle, SMC_PCI_CALL_INVAL_PARAM, 0U, 0U);
+ }
+ ret = pci_get_bus_for_seg(x1, &start_end_bus, &nseg);
+ SMC_RET3(handle, ret, start_end_bus, nseg);
+ break;
+ }
+ default:
+ /* should be unreachable */
+ WARN("Unimplemented PCI Service Call: 0x%x\n", smc_fid);
+ SMC_RET1(handle, SMC_PCI_CALL_NOT_SUPPORTED);
+ }
+}
diff --git a/services/std_svc/sdei/sdei_intr_mgmt.c b/services/std_svc/sdei/sdei_intr_mgmt.c
index fa1d3d2..5d176c2 100644
--- a/services/std_svc/sdei/sdei_intr_mgmt.c
+++ b/services/std_svc/sdei/sdei_intr_mgmt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,6 +8,7 @@
#include <string.h>
#include <arch_helpers.h>
+#include <arch_features.h>
#include <bl31/ehf.h>
#include <bl31/interrupt_mgmt.h>
#include <common/bl_common.h>
@@ -232,6 +233,77 @@
}
/*
+ * Prepare for ERET:
+ * - Set the ELR to the registered handler address
+ * - Set the SPSR register as described in the SDEI documentation and
+ * the AArch64.TakeException() pseudocode function in
+ * ARM DDI 0487F.c page J1-7635
+ */
+
+static void sdei_set_elr_spsr(sdei_entry_t *se, sdei_dispatch_context_t *disp_ctx)
+{
+ unsigned int client_el = sdei_client_el();
+ u_register_t sdei_spsr = SPSR_64(client_el, MODE_SP_ELX,
+ DISABLE_ALL_EXCEPTIONS);
+
+ u_register_t interrupted_pstate = disp_ctx->spsr_el3;
+
+ /* Check the SPAN bit in the client el SCTLR */
+ u_register_t client_el_sctlr;
+
+ if (client_el == MODE_EL2) {
+ client_el_sctlr = read_sctlr_el2();
+ } else {
+ client_el_sctlr = read_sctlr_el1();
+ }
+
+ /*
+ * Check whether to force the PAN bit or use the value in the
+ * interrupted EL according to the check described in
+ * TakeException. Since the client can only be Non-Secure
+ * EL2 or El1 some of the conditions in ElIsInHost() we know
+ * will always be True.
+ * When the client_el is EL2 we know that there will be a SPAN
+ * bit in SCTLR_EL2 as we have already checked for the condition
+ * HCR_EL2.E2H = 1 and HCR_EL2.TGE = 1
+ */
+ u_register_t hcr_el2 = read_hcr();
+ bool el_is_in_host = is_armv8_1_vhe_present() &&
+ (hcr_el2 & HCR_TGE_BIT) &&
+ (hcr_el2 & HCR_E2H_BIT);
+
+ if (is_armv8_1_pan_present() &&
+ ((client_el == MODE_EL1) ||
+ (client_el == MODE_EL2 && el_is_in_host)) &&
+ ((client_el_sctlr & SCTLR_SPAN_BIT) == 0U)) {
+ sdei_spsr |= SPSR_PAN_BIT;
+ } else {
+ sdei_spsr |= (interrupted_pstate & SPSR_PAN_BIT);
+ }
+
+ /* If SSBS is implemented, take the value from the client el SCTLR */
+ u_register_t ssbs_enabled = (read_id_aa64pfr1_el1()
+ >> ID_AA64PFR1_EL1_SSBS_SHIFT)
+ & ID_AA64PFR1_EL1_SSBS_MASK;
+ if (ssbs_enabled != SSBS_UNAVAILABLE) {
+ u_register_t ssbs_bit = ((client_el_sctlr & SCTLR_DSSBS_BIT)
+ >> SCTLR_DSSBS_SHIFT)
+ << SPSR_SSBS_SHIFT_AARCH64;
+ sdei_spsr |= ssbs_bit;
+ }
+
+ /* If MTE is implemented in the client el set the TCO bit */
+ if (get_armv8_5_mte_support() >= MTE_IMPLEMENTED_ELX) {
+ sdei_spsr |= SPSR_TCO_BIT_AARCH64;
+ }
+
+ /* Take the DIT field from the pstate of the interrupted el */
+ sdei_spsr |= (interrupted_pstate & SPSR_DIT_BIT);
+
+ cm_set_elr_spsr_el3(NON_SECURE, (uintptr_t) se->ep, sdei_spsr);
+}
+
+/*
* Populate the Non-secure context so that the next ERET will dispatch to the
* SDEI client.
*/
@@ -256,15 +328,8 @@
SMC_SET_GP(ctx, CTX_GPREG_X2, disp_ctx->elr_el3);
SMC_SET_GP(ctx, CTX_GPREG_X3, disp_ctx->spsr_el3);
- /*
- * Prepare for ERET:
- *
- * - Set PC to the registered handler address
- * - Set SPSR to jump to client EL with exceptions masked
- */
- cm_set_elr_spsr_el3(NON_SECURE, (uintptr_t) se->ep,
- SPSR_64(sdei_client_el(), MODE_SP_ELX,
- DISABLE_ALL_EXCEPTIONS));
+ /* Setup the elr and spsr register to prepare for ERET */
+ sdei_set_elr_spsr(se, disp_ctx);
#if DYNAMIC_WORKAROUND_CVE_2018_3639
cve_2018_3639_t *tgt_cve_2018_3639;
@@ -571,15 +636,15 @@
if (!can_sdei_state_trans(se, DO_DISPATCH))
return -1;
- /* Activate the priority corresponding to the event being dispatched */
- ehf_activate_priority(sdei_event_priority(map));
-
/*
* Prepare for NS dispatch by restoring the Non-secure context and
* marking that as active.
*/
ns_ctx = restore_and_resume_ns_context();
+ /* Activate the priority corresponding to the event being dispatched */
+ ehf_activate_priority(sdei_event_priority(map));
+
/* Dispatch event synchronously */
setup_ns_dispatch(map, se, ns_ctx, &dispatch_jmp);
begin_sdei_synchronous_dispatch(&dispatch_jmp);
diff --git a/services/std_svc/sdei/sdei_main.c b/services/std_svc/sdei/sdei_main.c
index dba5e07..5371df1 100644
--- a/services/std_svc/sdei/sdei_main.c
+++ b/services/std_svc/sdei/sdei_main.c
@@ -314,6 +314,9 @@
/* Update event registration flag */
se->reg_flags = (unsigned int) flags;
+ if (flags == SDEI_REGF_RM_PE) {
+ se->affinity = (mpidr & MPIDR_AFFINITY_MASK);
+ }
/*
* ROUTING_SET is permissible only when event composite state is
diff --git a/services/std_svc/spm_mm/spm_mm_setup.c b/services/std_svc/spm_mm/spm_mm_setup.c
index 32562c3..9d681c2 100644
--- a/services/std_svc/spm_mm/spm_mm_setup.c
+++ b/services/std_svc/spm_mm/spm_mm_setup.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -26,6 +27,10 @@
{
cpu_context_t *ctx = &(sp_ctx->cpu_ctx);
+ /* Pointer to the MP information from the platform port. */
+ const spm_mm_boot_info_t *sp_boot_info =
+ plat_get_secure_partition_boot_info(NULL);
+
/*
* Initialize CPU context
* ----------------------
@@ -36,7 +41,7 @@
SET_PARAM_HEAD(&ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE);
/* Setup entrypoint and SPSR */
- ep_info.pc = BL32_BASE;
+ ep_info.pc = sp_boot_info->sp_image_base;
ep_info.spsr = SPSR_64(MODE_EL0, MODE_SP_EL0, DISABLE_ALL_EXCEPTIONS);
/*
@@ -53,8 +58,8 @@
*
* X4 to X7 = 0
*/
- ep_info.args.arg0 = PLAT_SPM_BUF_BASE;
- ep_info.args.arg1 = PLAT_SPM_BUF_SIZE;
+ ep_info.args.arg0 = sp_boot_info->sp_shared_buf_base;
+ ep_info.args.arg1 = sp_boot_info->sp_shared_buf_size;
ep_info.args.arg2 = PLAT_SPM_COOKIE_0;
ep_info.args.arg3 = PLAT_SPM_COOKIE_1;
@@ -66,7 +71,7 @@
* implementation defined means. The value will be 0 otherwise.
*/
write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_SP_EL0,
- PLAT_SP_IMAGE_STACK_BASE + PLAT_SP_IMAGE_STACK_PCPU_SIZE);
+ sp_boot_info->sp_stack_base + sp_boot_info->sp_pcpu_stack_size);
/*
* Setup translation tables
@@ -84,10 +89,10 @@
unsigned int max_granule_mask = max_granule - 1U;
/* Base must be aligned to the max granularity */
- assert((PLAT_SP_IMAGE_NS_BUF_BASE & max_granule_mask) == 0);
+ assert((sp_boot_info->sp_ns_comm_buf_base & max_granule_mask) == 0);
/* Size must be a multiple of the max granularity */
- assert((PLAT_SP_IMAGE_NS_BUF_SIZE & max_granule_mask) == 0);
+ assert((sp_boot_info->sp_ns_comm_buf_size & max_granule_mask) == 0);
#endif /* ENABLE_ASSERTIONS */
@@ -191,16 +196,14 @@
* ----------------------------------------------------------
*/
- void *shared_buf_ptr = (void *) PLAT_SPM_BUF_BASE;
+ void *shared_buf_ptr = (void *) sp_boot_info->sp_shared_buf_base;
/* Copy the boot information into the shared buffer with the SP. */
assert((uintptr_t)shared_buf_ptr + sizeof(spm_mm_boot_info_t)
- <= (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE));
+ <= (sp_boot_info->sp_shared_buf_base + sp_boot_info->sp_shared_buf_size));
- assert(PLAT_SPM_BUF_BASE <= (UINTPTR_MAX - PLAT_SPM_BUF_SIZE + 1));
-
- const spm_mm_boot_info_t *sp_boot_info =
- plat_get_secure_partition_boot_info(NULL);
+ assert(sp_boot_info->sp_shared_buf_base <=
+ (UINTPTR_MAX - sp_boot_info->sp_shared_buf_size + 1));
assert(sp_boot_info != NULL);
@@ -234,7 +237,7 @@
assert(sp_boot_info->num_cpus <= PLATFORM_CORE_COUNT);
assert((uintptr_t)shared_buf_ptr
- <= (PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE -
+ <= (sp_boot_info->sp_shared_buf_base + sp_boot_info->sp_shared_buf_size -
(sp_boot_info->num_cpus * sizeof(*sp_mp_info))));
memcpy(shared_buf_ptr, (const void *) sp_mp_info,
diff --git a/services/std_svc/spmd/spmd_main.c b/services/std_svc/spmd/spmd_main.c
index a076be2..dda127f 100644
--- a/services/std_svc/spmd/spmd_main.c
+++ b/services/std_svc/spmd/spmd_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -108,10 +108,10 @@
cm_set_context(&(spmc_ctx->cpu_ctx), SECURE);
/* Restore the context assigned above */
- cm_el1_sysregs_context_restore(SECURE);
-
#if SPMD_SPM_AT_SEL2
cm_el2_sysregs_context_restore(SECURE);
+#else
+ cm_el1_sysregs_context_restore(SECURE);
#endif
cm_set_next_eret_context(SECURE);
@@ -119,9 +119,10 @@
rc = spmd_spm_core_enter(&spmc_ctx->c_rt_ctx);
/* Save secure state */
- cm_el1_sysregs_context_save(SECURE);
#if SPMD_SPM_AT_SEL2
cm_el2_sysregs_context_save(SECURE);
+#else
+ cm_el1_sysregs_context_save(SECURE);
#endif
return rc;
@@ -165,7 +166,6 @@
for (core_id = 0U; core_id < PLATFORM_CORE_COUNT; core_id++) {
if (core_id != linear_id) {
spm_core_context[core_id].state = SPMC_STATE_OFF;
- spm_core_context[core_id].secondary_ep.entry_point = 0UL;
}
}
@@ -348,21 +348,23 @@
unsigned int secure_state_out = (!secure_origin) ? SECURE : NON_SECURE;
/* Save incoming security state */
- cm_el1_sysregs_context_save(secure_state_in);
-#if CTX_INCLUDE_FPREGS
- fpregs_context_save(get_fpregs_ctx(cm_get_context(secure_state_in)));
-#endif
#if SPMD_SPM_AT_SEL2
+ if (secure_state_in == NON_SECURE) {
+ cm_el1_sysregs_context_save(secure_state_in);
+ }
cm_el2_sysregs_context_save(secure_state_in);
+#else
+ cm_el1_sysregs_context_save(secure_state_in);
#endif
/* Restore outgoing security state */
- cm_el1_sysregs_context_restore(secure_state_out);
-#if CTX_INCLUDE_FPREGS
- fpregs_context_restore(get_fpregs_ctx(cm_get_context(secure_state_out)));
-#endif
#if SPMD_SPM_AT_SEL2
+ if (secure_state_out == NON_SECURE) {
+ cm_el1_sysregs_context_restore(secure_state_out);
+ }
cm_el2_sysregs_context_restore(secure_state_out);
+#else
+ cm_el1_sysregs_context_restore(secure_state_out);
#endif
cm_set_next_eret_context(secure_state_out);
@@ -377,8 +379,8 @@
******************************************************************************/
static uint64_t spmd_ffa_error_return(void *handle, int error_code)
{
- SMC_RET8(handle, FFA_ERROR,
- FFA_TARGET_INFO_MBZ, error_code,
+ SMC_RET8(handle, (uint32_t) FFA_ERROR,
+ FFA_TARGET_INFO_MBZ, (uint32_t)error_code,
FFA_PARAM_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ,
FFA_PARAM_MBZ, FFA_PARAM_MBZ);
}
@@ -413,13 +415,6 @@
VERBOSE("%s %llx %llx %llx %llx %llx\n", __func__,
msg, parm1, parm2, parm3, parm4);
- switch (msg) {
- case SPMD_DIRECT_MSG_SET_ENTRY_POINT:
- return spmd_pm_secondary_core_set_ep(parm1, parm2, parm3);
- default:
- break;
- }
-
return -EINVAL;
}
@@ -436,6 +431,7 @@
void *handle,
uint64_t flags)
{
+ unsigned int linear_id = plat_my_core_pos();
spmd_spm_core_context_t *ctx = spmd_get_context();
bool secure_origin;
int32_t ret;
@@ -444,10 +440,12 @@
/* Determine which security state this SMC originated from */
secure_origin = is_caller_secure(flags);
- INFO("SPM: 0x%x 0x%llx 0x%llx 0x%llx 0x%llx 0x%llx 0x%llx 0x%llx\n",
- smc_fid, x1, x2, x3, x4, SMC_GET_GP(handle, CTX_GPREG_X5),
- SMC_GET_GP(handle, CTX_GPREG_X6),
- SMC_GET_GP(handle, CTX_GPREG_X7));
+ VERBOSE("SPM(%u): 0x%x 0x%llx 0x%llx 0x%llx 0x%llx "
+ "0x%llx 0x%llx 0x%llx\n",
+ linear_id, smc_fid, x1, x2, x3, x4,
+ SMC_GET_GP(handle, CTX_GPREG_X5),
+ SMC_GET_GP(handle, CTX_GPREG_X6),
+ SMC_GET_GP(handle, CTX_GPREG_X7));
switch (smc_fid) {
case FFA_ERROR:
@@ -477,14 +475,16 @@
(ctx->state == SPMC_STATE_RESET)) {
ret = FFA_ERROR_NOT_SUPPORTED;
} else if (!secure_origin) {
- ret = MAKE_FFA_VERSION(spmc_attrs.major_version, spmc_attrs.minor_version);
+ ret = MAKE_FFA_VERSION(spmc_attrs.major_version,
+ spmc_attrs.minor_version);
} else {
- ret = MAKE_FFA_VERSION(FFA_VERSION_MAJOR, FFA_VERSION_MINOR);
+ ret = MAKE_FFA_VERSION(FFA_VERSION_MAJOR,
+ FFA_VERSION_MINOR);
}
- SMC_RET8(handle, ret, FFA_TARGET_INFO_MBZ, FFA_TARGET_INFO_MBZ,
- FFA_PARAM_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ,
- FFA_PARAM_MBZ, FFA_PARAM_MBZ);
+ SMC_RET8(handle, (uint32_t)ret, FFA_TARGET_INFO_MBZ,
+ FFA_TARGET_INFO_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ,
+ FFA_PARAM_MBZ, FFA_PARAM_MBZ, FFA_PARAM_MBZ);
break; /* not reached */
case FFA_FEATURES:
@@ -499,7 +499,7 @@
*/
if (!is_ffa_fid(x1)) {
return spmd_ffa_error_return(handle,
- FFA_ERROR_NOT_SUPPORTED);
+ FFA_ERROR_NOT_SUPPORTED);
}
/* Forward SMC from Normal world to the SPM Core */
@@ -540,6 +540,52 @@
break; /* not reached */
+ case FFA_SECONDARY_EP_REGISTER_SMC64:
+ if (secure_origin) {
+ ret = spmd_pm_secondary_ep_register(x1);
+
+ if (ret < 0) {
+ SMC_RET8(handle, FFA_ERROR_SMC64,
+ FFA_TARGET_INFO_MBZ, ret,
+ FFA_PARAM_MBZ, FFA_PARAM_MBZ,
+ FFA_PARAM_MBZ, FFA_PARAM_MBZ,
+ FFA_PARAM_MBZ);
+ } else {
+ SMC_RET8(handle, FFA_SUCCESS_SMC64,
+ FFA_TARGET_INFO_MBZ, FFA_PARAM_MBZ,
+ FFA_PARAM_MBZ, FFA_PARAM_MBZ,
+ FFA_PARAM_MBZ, FFA_PARAM_MBZ,
+ FFA_PARAM_MBZ);
+ }
+ }
+
+ return spmd_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED);
+ break; /* Not reached */
+
+ case FFA_SPM_ID_GET:
+ if (MAKE_FFA_VERSION(1, 1) > FFA_VERSION_COMPILED) {
+ return spmd_ffa_error_return(handle,
+ FFA_ERROR_NOT_SUPPORTED);
+ }
+ /*
+ * Returns the ID of the SPMC or SPMD depending on the FF-A
+ * instance where this function is invoked
+ */
+ if (!secure_origin) {
+ SMC_RET8(handle, FFA_SUCCESS_SMC32,
+ FFA_TARGET_INFO_MBZ, spmc_attrs.spmc_id,
+ FFA_PARAM_MBZ, FFA_PARAM_MBZ,
+ FFA_PARAM_MBZ, FFA_PARAM_MBZ,
+ FFA_PARAM_MBZ);
+ }
+ SMC_RET8(handle, FFA_SUCCESS_SMC32,
+ FFA_TARGET_INFO_MBZ, SPMD_DIRECT_MSG_ENDPOINT_ID,
+ FFA_PARAM_MBZ, FFA_PARAM_MBZ,
+ FFA_PARAM_MBZ, FFA_PARAM_MBZ,
+ FFA_PARAM_MBZ);
+
+ break; /* not reached */
+
case FFA_MSG_SEND_DIRECT_REQ_SMC32:
if (secure_origin && spmd_is_spmc_message(x1)) {
ret = spmd_handle_spmc_message(x3, x4,
@@ -627,7 +673,7 @@
}
/* Fall through to forward the call to the other world */
-
+ case FFA_INTERRUPT:
case FFA_MSG_YIELD:
/* This interface must be invoked only by the Secure world */
if (!secure_origin) {
diff --git a/services/std_svc/spmd/spmd_pm.c b/services/std_svc/spmd/spmd_pm.c
index 5433e5d..074609c 100644
--- a/services/std_svc/spmd/spmd_pm.c
+++ b/services/std_svc/spmd/spmd_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,8 +7,15 @@
#include <assert.h>
#include <errno.h>
#include <lib/el3_runtime/context_mgmt.h>
+#include <lib/spinlock.h>
#include "spmd_private.h"
+static struct {
+ bool secondary_ep_locked;
+ uintptr_t secondary_ep;
+ spinlock_t lock;
+} g_spmd_pm;
+
/*******************************************************************************
* spmd_build_spmc_message
*
@@ -25,16 +32,16 @@
}
/*******************************************************************************
- * spmd_pm_secondary_core_set_ep
+ * spmd_pm_secondary_ep_register
******************************************************************************/
-int spmd_pm_secondary_core_set_ep(unsigned long long mpidr,
- uintptr_t entry_point, unsigned long long context)
+int spmd_pm_secondary_ep_register(uintptr_t entry_point)
{
- int id = plat_core_pos_by_mpidr(mpidr);
+ int ret = FFA_ERROR_INVALID_PARAMETER;
- if ((id < 0) || ((unsigned int)id >= PLATFORM_CORE_COUNT)) {
- ERROR("%s inconsistent MPIDR (%llx)\n", __func__, mpidr);
- return -EINVAL;
+ spin_lock(&g_spmd_pm.lock);
+
+ if (g_spmd_pm.secondary_ep_locked == true) {
+ goto out;
}
/*
@@ -42,27 +49,22 @@
* load_address <= entry_point < load_address + binary_size
*/
if (!spmd_check_address_in_binary_image(entry_point)) {
- ERROR("%s entry point is not within image boundaries (%llx)\n",
- __func__, mpidr);
- return -EINVAL;
+ ERROR("%s entry point is not within image boundaries\n",
+ __func__);
+ goto out;
}
- spmd_spm_core_context_t *ctx = spmd_get_context_by_mpidr(mpidr);
- spmd_pm_secondary_ep_t *secondary_ep = &ctx->secondary_ep;
- if (secondary_ep->locked) {
- ERROR("%s entry locked (%llx)\n", __func__, mpidr);
- return -EINVAL;
- }
+ g_spmd_pm.secondary_ep = entry_point;
+ g_spmd_pm.secondary_ep_locked = true;
- /* Fill new entry to corresponding secondary core id and lock it */
- secondary_ep->entry_point = entry_point;
- secondary_ep->context = context;
- secondary_ep->locked = true;
+ VERBOSE("%s %lx\n", __func__, entry_point);
- VERBOSE("%s %d %llx %lx %llx\n",
- __func__, id, mpidr, entry_point, context);
+ ret = 0;
- return 0;
+out:
+ spin_unlock(&g_spmd_pm.lock);
+
+ return ret;
}
/*******************************************************************************
@@ -82,18 +84,20 @@
assert(ctx->state != SPMC_STATE_ON);
assert(spmc_ep_info != NULL);
+ spin_lock(&g_spmd_pm.lock);
+
/*
- * TODO: this might require locking the spmc_ep_info structure,
- * or provisioning one structure per cpu
+ * Leave the possibility that the SPMC does not call
+ * FFA_SECONDARY_EP_REGISTER in which case re-use the
+ * primary core address for booting secondary cores.
*/
- if (ctx->secondary_ep.entry_point == 0UL) {
- goto exit;
+ if (g_spmd_pm.secondary_ep_locked == true) {
+ spmc_ep_info->pc = g_spmd_pm.secondary_ep;
}
- spmc_ep_info->pc = ctx->secondary_ep.entry_point;
+ spin_unlock(&g_spmd_pm.lock);
+
cm_setup_context(&ctx->cpu_ctx, spmc_ep_info);
- write_ctx_reg(get_gpregs_ctx(&ctx->cpu_ctx), CTX_GPREG_X0,
- ctx->secondary_ep.context);
/* Mark CPU as initiating ON operation */
ctx->state = SPMC_STATE_ON_PENDING;
@@ -106,7 +110,6 @@
return;
}
-exit:
ctx->state = SPMC_STATE_ON;
VERBOSE("CPU %u on!\n", linear_id);
@@ -124,10 +127,6 @@
assert(ctx != NULL);
assert(ctx->state != SPMC_STATE_OFF);
- if (ctx->secondary_ep.entry_point == 0UL) {
- goto exit;
- }
-
/* Build an SPMD to SPMC direct message request. */
spmd_build_spmc_message(get_gpregs_ctx(&ctx->cpu_ctx), PSCI_CPU_OFF);
@@ -136,9 +135,15 @@
ERROR("%s failed (%llu) on CPU%u\n", __func__, rc, linear_id);
}
- /* TODO expect FFA_DIRECT_MSG_RESP returned from SPMC */
+ /* Expect a direct message response from the SPMC. */
+ u_register_t ffa_resp_func = read_ctx_reg(get_gpregs_ctx(&ctx->cpu_ctx),
+ CTX_GPREG_X0);
+ if (ffa_resp_func != FFA_MSG_SEND_DIRECT_RESP_SMC32) {
+ ERROR("%s invalid SPMC response (%lx).\n",
+ __func__, ffa_resp_func);
+ return -EINVAL;
+ }
-exit:
ctx->state = SPMC_STATE_OFF;
VERBOSE("CPU %u off!\n", linear_id);
diff --git a/services/std_svc/spmd/spmd_private.h b/services/std_svc/spmd/spmd_private.h
index eff0dd9..6d51a58 100644
--- a/services/std_svc/spmd/spmd_private.h
+++ b/services/std_svc/spmd/spmd_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -42,12 +42,6 @@
SPMC_STATE_ON
} spmc_state_t;
-typedef struct spmd_pm_secondary_ep {
- uintptr_t entry_point;
- uintptr_t context;
- bool locked;
-} spmd_pm_secondary_ep_t;
-
/*
* Data structure used by the SPM dispatcher (SPMD) in EL3 to track context of
* the SPM core (SPMC) at the next lower EL.
@@ -56,7 +50,6 @@
uint64_t c_rt_ctx;
cpu_context_t cpu_ctx;
spmc_state_t state;
- spmd_pm_secondary_ep_t secondary_ep;
} spmd_spm_core_context_t;
/*
@@ -69,7 +62,6 @@
#define SPMC_SECURE_ID_SHIFT U(15)
#define SPMD_DIRECT_MSG_ENDPOINT_ID U(FFA_ENDPOINT_ID_MAX - 1)
-#define SPMD_DIRECT_MSG_SET_ENTRY_POINT U(1)
/* Functions used to enter/exit SPMC synchronously */
uint64_t spmd_spm_core_sync_entry(spmd_spm_core_context_t *ctx);
@@ -94,8 +86,7 @@
/* SPMC context on current CPU get helper */
spmd_spm_core_context_t *spmd_get_context(void);
-int spmd_pm_secondary_core_set_ep(unsigned long long mpidr,
- uintptr_t entry_point, unsigned long long context);
+int spmd_pm_secondary_ep_register(uintptr_t entry_point);
bool spmd_check_address_in_binary_image(uint64_t address);
#endif /* __ASSEMBLER__ */
diff --git a/services/std_svc/std_svc_setup.c b/services/std_svc/std_svc_setup.c
index 23f13ab..1917d0a 100644
--- a/services/std_svc/std_svc_setup.c
+++ b/services/std_svc/std_svc_setup.c
@@ -13,6 +13,7 @@
#include <lib/pmf/pmf.h>
#include <lib/psci/psci.h>
#include <lib/runtime_instr.h>
+#include <services/pci_svc.h>
#include <services/sdei.h>
#include <services/spm_mm_svc.h>
#include <services/spmd_svc.h>
@@ -82,6 +83,15 @@
void *handle,
u_register_t flags)
{
+ if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
+ /* 32-bit SMC function, clear top parameter bits */
+
+ x1 &= UINT32_MAX;
+ x2 &= UINT32_MAX;
+ x3 &= UINT32_MAX;
+ x4 &= UINT32_MAX;
+ }
+
/*
* Dispatch PSCI calls to PSCI SMC handler and return its return
* value
@@ -149,6 +159,13 @@
}
#endif
+#if SMC_PCI_SUPPORT
+ if (is_pci_fid(smc_fid)) {
+ return pci_smc_handler(smc_fid, x1, x2, x3, x4, cookie, handle,
+ flags);
+ }
+#endif
+
switch (smc_fid) {
case ARM_STD_SVC_CALL_COUNT:
/*
@@ -166,7 +183,7 @@
SMC_RET2(handle, STD_SVC_VERSION_MAJOR, STD_SVC_VERSION_MINOR);
default:
- WARN("Unimplemented Standard Service Call: 0x%x \n", smc_fid);
+ VERBOSE("Unimplemented Standard Service Call: 0x%x \n", smc_fid);
SMC_RET1(handle, SMC_UNK);
}
}
diff --git a/tools/cert_create/Makefile b/tools/cert_create/Makefile
index c3c8bcf..77d2007 100644
--- a/tools/cert_create/Makefile
+++ b/tools/cert_create/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -16,6 +16,12 @@
include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
include ${MAKE_HELPERS_DIRECTORY}build_env.mk
+ifneq (${PLAT},none)
+TF_PLATFORM_ROOT := ../../plat/
+include ${MAKE_HELPERS_DIRECTORY}plat_helpers.mk
+PLAT_CERT_CREATE_HELPER_MK := ${PLAT_DIR}/cert_create_tbbr.mk
+endif
+
# Common source files.
OBJECTS := src/cert.o \
src/cmd_opt.o \
@@ -33,6 +39,10 @@
$(error Unknown chain of trust ${COT})
endif
+ifneq (,$(wildcard ${PLAT_CERT_CREATE_HELPER_MK}))
+include ${PLAT_CERT_CREATE_HELPER_MK}
+endif
+
HOSTCCFLAGS := -Wall -std=c99
ifeq (${DEBUG},1)
@@ -51,7 +61,7 @@
# Make soft links and include from local directory otherwise wrong headers
# could get pulled in from firmware tree.
-INC_DIR := -I ./include -I ${PLAT_INCLUDE} -I ${OPENSSL_DIR}/include
+INC_DIR += -I ./include -I ${PLAT_INCLUDE} -I ${OPENSSL_DIR}/include
LIB_DIR := -L ${OPENSSL_DIR}/lib
LIB := -lssl -lcrypto
diff --git a/tools/cert_create/include/cert.h b/tools/cert_create/include/cert.h
index daf27a7..e63b474 100644
--- a/tools/cert_create/include/cert.h
+++ b/tools/cert_create/include/cert.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -57,11 +57,20 @@
/* Macro to register the certificates used in the CoT */
#define REGISTER_COT(_certs) \
- cert_t *certs = &_certs[0]; \
- const unsigned int num_certs = sizeof(_certs)/sizeof(_certs[0])
+ cert_t *def_certs = &_certs[0]; \
+ const unsigned int num_def_certs = sizeof(_certs)/sizeof(_certs[0])
+
+/* Macro to register the platform defined certificates used in the CoT */
+#define PLAT_REGISTER_COT(_pdef_certs) \
+ cert_t *pdef_certs = &_pdef_certs[0]; \
+ const unsigned int num_pdef_certs = sizeof(_pdef_certs)/sizeof(_pdef_certs[0])
/* Exported variables */
-extern cert_t *certs;
-extern const unsigned int num_certs;
+extern cert_t *def_certs;
+extern const unsigned int num_def_certs;
+extern cert_t *pdef_certs;
+extern const unsigned int num_pdef_certs;
+extern cert_t *certs;
+extern unsigned int num_certs;
#endif /* CERT_H */
diff --git a/tools/cert_create/include/ext.h b/tools/cert_create/include/ext.h
index 9c0b5c3..e900a6d 100644
--- a/tools/cert_create/include/ext.h
+++ b/tools/cert_create/include/ext.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -75,11 +75,20 @@
/* Macro to register the extensions used in the CoT */
#define REGISTER_EXTENSIONS(_ext) \
- ext_t *extensions = &_ext[0]; \
- const unsigned int num_extensions = sizeof(_ext)/sizeof(_ext[0])
+ ext_t *def_extensions = &_ext[0]; \
+ const unsigned int num_def_extensions = sizeof(_ext)/sizeof(_ext[0])
+
+/* Macro to register the platform defined extensions used in the CoT */
+#define PLAT_REGISTER_EXTENSIONS(_pdef_ext) \
+ ext_t *pdef_extensions = &_pdef_ext[0]; \
+ const unsigned int num_pdef_extensions = sizeof(_pdef_ext)/sizeof(_pdef_ext[0])
/* Exported variables */
-extern ext_t *extensions;
-extern const unsigned int num_extensions;
+extern ext_t *def_extensions;
+extern const unsigned int num_def_extensions;
+extern ext_t *pdef_extensions;
+extern const unsigned int num_pdef_extensions;
+extern ext_t *extensions;
+extern unsigned int num_extensions;
#endif /* EXT_H */
diff --git a/tools/cert_create/include/key.h b/tools/cert_create/include/key.h
index d96d983..128e7f7 100644
--- a/tools/cert_create/include/key.h
+++ b/tools/cert_create/include/key.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -73,11 +73,20 @@
/* Macro to register the keys used in the CoT */
#define REGISTER_KEYS(_keys) \
- key_t *keys = &_keys[0]; \
- const unsigned int num_keys = sizeof(_keys)/sizeof(_keys[0])
+ key_t *def_keys = &_keys[0]; \
+ const unsigned int num_def_keys = sizeof(_keys)/sizeof(_keys[0])
+
+/* Macro to register the platform defined keys used in the CoT */
+#define PLAT_REGISTER_KEYS(_pdef_keys) \
+ key_t *pdef_keys = &_pdef_keys[0]; \
+ const unsigned int num_pdef_keys = sizeof(_pdef_keys)/sizeof(_pdef_keys[0])
/* Exported variables */
-extern key_t *keys;
-extern const unsigned int num_keys;
+extern key_t *def_keys;
+extern const unsigned int num_def_keys;
+extern key_t *pdef_keys;
+extern const unsigned int num_pdef_keys;
+extern key_t *keys;
+extern unsigned int num_keys;
#endif /* KEY_H */
diff --git a/tools/cert_create/src/cert.c b/tools/cert_create/src/cert.c
index 153f555..4b35d73 100644
--- a/tools/cert_create/src/cert.c
+++ b/tools/cert_create/src/cert.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,6 +24,9 @@
#define SERIAL_RAND_BITS 64
#define RSA_SALT_LEN 32
+cert_t *certs;
+unsigned int num_certs;
+
int rand_serial(BIGNUM *b, ASN1_INTEGER *ai)
{
BIGNUM *btmp;
@@ -220,6 +223,28 @@
cert_t *cert;
unsigned int i;
+ certs = malloc((num_def_certs * sizeof(def_certs[0]))
+#ifdef PDEF_CERTS
+ + (num_pdef_certs * sizeof(pdef_certs[0]))
+#endif
+ );
+ if (certs == NULL) {
+ ERROR("%s:%d Failed to allocate memory.\n", __func__, __LINE__);
+ return 1;
+ }
+
+ memcpy(&certs[0], &def_certs[0],
+ (num_def_certs * sizeof(def_certs[0])));
+
+#ifdef PDEF_CERTS
+ memcpy(&certs[num_def_certs], &pdef_certs[0],
+ (num_pdef_certs * sizeof(pdef_certs[0])));
+
+ num_certs = num_def_certs + num_pdef_certs;
+#else
+ num_certs = num_def_certs;
+#endif
+
for (i = 0; i < num_certs; i++) {
cert = &certs[i];
cmd_opt.long_opt.name = cert->opt;
diff --git a/tools/cert_create/src/ext.c b/tools/cert_create/src/ext.c
index 65dd3e5..2882123 100644
--- a/tools/cert_create/src/ext.c
+++ b/tools/cert_create/src/ext.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,8 +13,12 @@
#include <openssl/x509v3.h>
#include "cmd_opt.h"
+#include "debug.h"
#include "ext.h"
+ext_t *extensions;
+unsigned int num_extensions;
+
DECLARE_ASN1_ITEM(ASN1_INTEGER)
DECLARE_ASN1_ITEM(X509_ALGOR)
DECLARE_ASN1_ITEM(ASN1_OCTET_STRING)
@@ -51,6 +55,26 @@
int nid, ret;
unsigned int i;
+ extensions = malloc((num_def_extensions * sizeof(def_extensions[0]))
+#ifdef PDEF_EXTS
+ + (num_pdef_extensions * sizeof(pdef_extensions[0]))
+#endif
+ );
+ if (extensions == NULL) {
+ ERROR("%s:%d Failed to allocate memory.\n", __func__, __LINE__);
+ return 1;
+ }
+
+ memcpy(&extensions[0], &def_extensions[0],
+ (num_def_extensions * sizeof(def_extensions[0])));
+#ifdef PDEF_EXTS
+ memcpy(&extensions[num_def_extensions], &pdef_extensions[0],
+ (num_pdef_extensions * sizeof(pdef_extensions[0])));
+ num_extensions = num_def_extensions + num_pdef_extensions;
+#else
+ num_extensions = num_def_extensions;
+#endif
+
for (i = 0; i < num_extensions; i++) {
ext = &extensions[i];
/* Register command line option */
diff --git a/tools/cert_create/src/key.c b/tools/cert_create/src/key.c
index fcc9d53..6435975 100644
--- a/tools/cert_create/src/key.c
+++ b/tools/cert_create/src/key.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,6 +21,9 @@
#define MAX_FILENAME_LEN 1024
+key_t *keys;
+unsigned int num_keys;
+
/*
* Create a new key container
*/
@@ -182,6 +185,28 @@
key_t *key;
unsigned int i;
+ keys = malloc((num_def_keys * sizeof(def_keys[0]))
+#ifdef PDEF_KEYS
+ + (num_pdef_keys * sizeof(pdef_keys[0]))
+#endif
+ );
+
+ if (keys == NULL) {
+ ERROR("%s:%d Failed to allocate memory.\n", __func__, __LINE__);
+ return 1;
+ }
+
+ memcpy(&keys[0], &def_keys[0], (num_def_keys * sizeof(def_keys[0])));
+#ifdef PDEF_KEYS
+ memcpy(&keys[num_def_keys], &pdef_keys[0],
+ (num_pdef_keys * sizeof(pdef_keys[0])));
+
+ num_keys = num_def_keys + num_pdef_keys;
+#else
+ num_keys = num_def_keys;
+#endif
+ ;
+
for (i = 0; i < num_keys; i++) {
key = &keys[i];
if (key->opt != NULL) {
diff --git a/tools/fiptool/Makefile b/tools/fiptool/Makefile
index df8ab5c..11d2e7b 100644
--- a/tools/fiptool/Makefile
+++ b/tools/fiptool/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -32,6 +32,16 @@
HOSTCC ?= gcc
+ifneq (${PLAT},)
+TF_PLATFORM_ROOT := ../../plat/
+include ${MAKE_HELPERS_DIRECTORY}plat_helpers.mk
+PLAT_FIPTOOL_HELPER_MK := ${PLAT_DIR}/plat_fiptool.mk
+endif
+
+ifneq (,$(wildcard ${PLAT_FIPTOOL_HELPER_MK}))
+include ${PLAT_FIPTOOL_HELPER_MK}
+endif
+
.PHONY: all clean distclean
all: ${PROJECT}
@@ -43,7 +53,7 @@
@echo "Built $@ successfully"
@${ECHO_BLANK_LINE}
-%.o: %.c %.h Makefile
+%.o: %.c Makefile
@echo " HOSTCC $<"
${Q}${HOSTCC} -c ${CPPFLAGS} ${HOSTCCFLAGS} ${INCLUDE_PATHS} $< -o $@
diff --git a/tools/fiptool/fiptool.c b/tools/fiptool/fiptool.c
index 8c5b04a..d92c31d 100644
--- a/tools/fiptool/fiptool.c
+++ b/tools/fiptool/fiptool.c
@@ -215,6 +215,18 @@
toc_entry->cmdline_name);
add_image_desc(desc);
}
+#ifdef PLAT_DEF_FIP_UUID
+ for (toc_entry = plat_def_toc_entries;
+ toc_entry->cmdline_name != NULL;
+ toc_entry++) {
+ image_desc_t *desc;
+
+ desc = new_image_desc(&toc_entry->uuid,
+ toc_entry->name,
+ toc_entry->cmdline_name);
+ add_image_desc(desc);
+ }
+#endif
}
static image_desc_t *lookup_image_desc_from_uuid(const uuid_t *uuid)
@@ -753,6 +765,12 @@
for (; toc_entry->cmdline_name != NULL; toc_entry++)
printf(" --%-16s FILENAME\t%s\n", toc_entry->cmdline_name,
toc_entry->name);
+#ifdef PLAT_DEF_FIP_UUID
+ toc_entry = plat_def_toc_entries;
+ for (; toc_entry->cmdline_name != NULL; toc_entry++)
+ printf(" --%-16s FILENAME\t%s\n", toc_entry->cmdline_name,
+ toc_entry->name);
+#endif
exit(exit_status);
}
@@ -867,6 +885,12 @@
for (; toc_entry->cmdline_name != NULL; toc_entry++)
printf(" --%-16s FILENAME\t%s\n", toc_entry->cmdline_name,
toc_entry->name);
+#ifdef PLAT_DEF_FIP_UUID
+ toc_entry = plat_def_toc_entries;
+ for (; toc_entry->cmdline_name != NULL; toc_entry++)
+ printf(" --%-16s FILENAME\t%s\n", toc_entry->cmdline_name,
+ toc_entry->name);
+#endif
exit(exit_status);
}
@@ -1001,6 +1025,12 @@
for (; toc_entry->cmdline_name != NULL; toc_entry++)
printf(" --%-16s FILENAME\t%s\n", toc_entry->cmdline_name,
toc_entry->name);
+#ifdef PLAT_DEF_FIP_UUID
+ toc_entry = plat_def_toc_entries;
+ for (; toc_entry->cmdline_name != NULL; toc_entry++)
+ printf(" --%-16s FILENAME\t%s\n", toc_entry->cmdline_name,
+ toc_entry->name);
+#endif
printf("\n");
printf("If no options are provided, all images will be unpacked.\n");
exit(exit_status);
@@ -1126,6 +1156,12 @@
for (; toc_entry->cmdline_name != NULL; toc_entry++)
printf(" --%-16s\t%s\n", toc_entry->cmdline_name,
toc_entry->name);
+#ifdef PLAT_DEF_FIP_UUID
+ toc_entry = plat_def_toc_entries;
+ for (; toc_entry->cmdline_name != NULL; toc_entry++)
+ printf(" --%-16s\t%s\n", toc_entry->cmdline_name,
+ toc_entry->name);
+#endif
exit(exit_status);
}
diff --git a/tools/fiptool/tbbr_config.h b/tools/fiptool/tbbr_config.h
index 1fc6cad..b926ff0 100644
--- a/tools/fiptool/tbbr_config.h
+++ b/tools/fiptool/tbbr_config.h
@@ -21,4 +21,8 @@
extern toc_entry_t toc_entries[];
+#ifdef PLAT_DEF_FIP_UUID
+extern toc_entry_t plat_def_toc_entries[];
+#endif
+
#endif /* TBBR_CONFIG_H */
diff --git a/tools/nxp/cert_create_helper/cert_create_tbbr.mk b/tools/nxp/cert_create_helper/cert_create_tbbr.mk
new file mode 100644
index 0000000..e3b2e91
--- /dev/null
+++ b/tools/nxp/cert_create_helper/cert_create_tbbr.mk
@@ -0,0 +1,31 @@
+#
+# Copyright 2021 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Compile time defines used by NXP platforms
+
+PLAT_DEF_OID := yes
+
+ifeq (${PLAT_DEF_OID},yes)
+
+$(eval $(call add_define, PLAT_DEF_OID))
+$(eval $(call add_define, PDEF_KEYS))
+$(eval $(call add_define, PDEF_CERTS))
+$(eval $(call add_define, PDEF_EXTS))
+
+
+INC_DIR += -I../../plat/nxp/common/fip_handler/common/
+
+PDEF_CERT_TOOL_PATH := ../nxp/cert_create_helper
+PLAT_INCLUDE += -I${PDEF_CERT_TOOL_PATH}/include
+
+PLAT_OBJECTS += ${PDEF_CERT_TOOL_PATH}/src/pdef_tbb_cert.o \
+ ${PDEF_CERT_TOOL_PATH}/src/pdef_tbb_ext.o \
+ ${PDEF_CERT_TOOL_PATH}/src/pdef_tbb_key.o
+
+$(shell rm ${PLAT_OBJECTS})
+
+OBJECTS += ${PLAT_OBJECTS}
+endif
diff --git a/tools/nxp/cert_create_helper/include/pdef_tbb_cert.h b/tools/nxp/cert_create_helper/include/pdef_tbb_cert.h
new file mode 100644
index 0000000..f185619
--- /dev/null
+++ b/tools/nxp/cert_create_helper/include/pdef_tbb_cert.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PDEF_TBB_CERT_H
+#define PDEF_TBB_CERT_H
+
+#include <tbbr/tbb_cert.h>
+
+/*
+ * Enumerate the certificates that are used to establish the chain of trust
+ */
+enum {
+ DDR_FW_KEY_CERT = FWU_CERT + 1,
+ DDR_UDIMM_FW_CONTENT_CERT,
+ DDR_RDIMM_FW_CONTENT_CERT
+};
+
+#endif /* PDEF_TBB_CERT_H */
diff --git a/tools/nxp/cert_create_helper/include/pdef_tbb_ext.h b/tools/nxp/cert_create_helper/include/pdef_tbb_ext.h
new file mode 100644
index 0000000..5fb349c
--- /dev/null
+++ b/tools/nxp/cert_create_helper/include/pdef_tbb_ext.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PDEF_TBB_EXT_H
+#define PDEF_TBB_EXT_H
+
+#include <tbbr/tbb_ext.h>
+
+/* Plat Defined TBBR extensions */
+enum {
+ DDR_FW_CONTENT_CERT_PK_EXT = FWU_HASH_EXT + 1,
+ DDR_IMEM_UDIMM_1D_HASH_EXT,
+ DDR_IMEM_UDIMM_2D_HASH_EXT,
+ DDR_DMEM_UDIMM_1D_HASH_EXT,
+ DDR_DMEM_UDIMM_2D_HASH_EXT,
+ DDR_IMEM_RDIMM_1D_HASH_EXT,
+ DDR_IMEM_RDIMM_2D_HASH_EXT,
+ DDR_DMEM_RDIMM_1D_HASH_EXT,
+ DDR_DMEM_RDIMM_2D_HASH_EXT
+};
+
+#endif /* PDEF_TBB_EXT_H */
diff --git a/tools/nxp/cert_create_helper/include/pdef_tbb_key.h b/tools/nxp/cert_create_helper/include/pdef_tbb_key.h
new file mode 100644
index 0000000..b26b651
--- /dev/null
+++ b/tools/nxp/cert_create_helper/include/pdef_tbb_key.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PDEF_TBB_KEY_H
+#define PDEF_TBB_KEY_H
+
+#include <tbbr/tbb_key.h>
+
+/*
+ * Enumerate the pltform defined keys that are used to establish the chain of trust
+ */
+enum {
+ DDR_FW_CONTENT_KEY = NON_TRUSTED_FW_CONTENT_CERT_KEY + 1,
+};
+#endif /* PDEF_TBB_KEY_H */
diff --git a/tools/nxp/cert_create_helper/src/pdef_tbb_cert.c b/tools/nxp/cert_create_helper/src/pdef_tbb_cert.c
new file mode 100644
index 0000000..40bd928
--- /dev/null
+++ b/tools/nxp/cert_create_helper/src/pdef_tbb_cert.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <pdef_tbb_cert.h>
+#include <pdef_tbb_ext.h>
+#include <pdef_tbb_key.h>
+
+static cert_t pdef_tbb_certs[] = {
+ [DDR_FW_KEY_CERT - DDR_FW_KEY_CERT] = {
+ .id = DDR_FW_KEY_CERT,
+ .opt = "ddr-fw-key-cert",
+ .help_msg = "DDR Firmware Key Certificate (output file)",
+ .fn = NULL,
+ .cn = "DDR Firmware Key Certificate",
+ .key = TRUSTED_WORLD_KEY,
+ .issuer = DDR_FW_KEY_CERT,
+ .ext = {
+ TRUSTED_FW_NVCOUNTER_EXT,
+ DDR_FW_CONTENT_CERT_PK_EXT,
+ },
+ .num_ext = 2
+ },
+ [DDR_UDIMM_FW_CONTENT_CERT - DDR_FW_KEY_CERT] = {
+ .id = DDR_UDIMM_FW_CONTENT_CERT,
+ .opt = "ddr-udimm-fw-cert",
+ .help_msg = "DDR UDIMM Firmware Content Certificate (output file)",
+ .fn = NULL,
+ .cn = "DDR UDIMM Firmware Content Certificate",
+ .key = DDR_FW_CONTENT_KEY,
+ .issuer = DDR_UDIMM_FW_CONTENT_CERT,
+ .ext = {
+ TRUSTED_FW_NVCOUNTER_EXT,
+ DDR_IMEM_UDIMM_1D_HASH_EXT,
+ DDR_IMEM_UDIMM_2D_HASH_EXT,
+ DDR_DMEM_UDIMM_1D_HASH_EXT,
+ DDR_DMEM_UDIMM_2D_HASH_EXT,
+ },
+ .num_ext = 5
+ },
+ [DDR_RDIMM_FW_CONTENT_CERT - DDR_FW_KEY_CERT] = {
+ .id = DDR_RDIMM_FW_CONTENT_CERT,
+ .opt = "ddr-rdimm-fw-cert",
+ .help_msg = "DDR RDIMM Firmware Content Certificate (output file)",
+ .fn = NULL,
+ .cn = "DDR RDIMM Firmware Content Certificate",
+ .key = DDR_FW_CONTENT_KEY,
+ .issuer = DDR_RDIMM_FW_CONTENT_CERT,
+ .ext = {
+ TRUSTED_FW_NVCOUNTER_EXT,
+ DDR_IMEM_RDIMM_1D_HASH_EXT,
+ DDR_IMEM_RDIMM_2D_HASH_EXT,
+ DDR_DMEM_RDIMM_1D_HASH_EXT,
+ DDR_DMEM_RDIMM_2D_HASH_EXT,
+ },
+ .num_ext = 5
+ }
+};
+
+PLAT_REGISTER_COT(pdef_tbb_certs);
diff --git a/tools/nxp/cert_create_helper/src/pdef_tbb_ext.c b/tools/nxp/cert_create_helper/src/pdef_tbb_ext.c
new file mode 100644
index 0000000..f6da6dd
--- /dev/null
+++ b/tools/nxp/cert_create_helper/src/pdef_tbb_ext.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <openssl/err.h>
+#include <openssl/x509v3.h>
+
+#if USE_TBBR_DEFS
+#include <tbbr_oid.h>
+#else
+#include <platform_oid.h>
+#endif
+
+#include "ext.h"
+#include "tbbr/tbb_ext.h"
+#include "tbbr/tbb_key.h"
+
+#include <pdef_tbb_ext.h>
+#include <pdef_tbb_key.h>
+
+static ext_t pdef_tbb_ext[] = {
+ [DDR_FW_CONTENT_CERT_PK_EXT - DDR_FW_CONTENT_CERT_PK_EXT] = {
+ .oid = DDR_FW_CONTENT_CERT_PK_OID,
+ .sn = "DDR FirmwareContentCertPK",
+ .ln = "DDR Firmware content certificate public key",
+ .asn1_type = V_ASN1_OCTET_STRING,
+ .type = EXT_TYPE_PKEY,
+ .attr.key = DDR_FW_CONTENT_KEY
+ },
+ [DDR_IMEM_UDIMM_1D_HASH_EXT - DDR_FW_CONTENT_CERT_PK_EXT] = {
+ .oid = DDR_IMEM_UDIMM_1D_HASH_OID,
+ .opt = "ddr-immem-udimm-1d",
+ .help_msg = "DDR Firmware IMEM UDIMM 1D image file",
+ .sn = "DDR UDIMM IMEM 1D FirmwareHash",
+ .ln = "DDR UDIMM IMEM 1D Firmware hash (SHA256)",
+ .asn1_type = V_ASN1_OCTET_STRING,
+ .type = EXT_TYPE_HASH
+ },
+ [DDR_IMEM_UDIMM_2D_HASH_EXT - DDR_FW_CONTENT_CERT_PK_EXT] = {
+ .oid = DDR_IMEM_UDIMM_2D_HASH_OID,
+ .opt = "ddr-immem-udimm-2d",
+ .help_msg = "DDR Firmware IMEM UDIMM 2D image file",
+ .sn = "DDR UDIMM IMEM 2D FirmwareHash",
+ .ln = "DDR UDIMM IMEM 2D Firmware hash (SHA256)",
+ .asn1_type = V_ASN1_OCTET_STRING,
+ .type = EXT_TYPE_HASH
+ },
+ [DDR_DMEM_UDIMM_1D_HASH_EXT - DDR_FW_CONTENT_CERT_PK_EXT] = {
+ .oid = DDR_DMEM_UDIMM_1D_HASH_OID,
+ .opt = "ddr-dmmem-udimm-1d",
+ .help_msg = "DDR Firmware DMEM UDIMM 1D image file",
+ .sn = "DDR UDIMM DMEM 1D FirmwareHash",
+ .ln = "DDR UDIMM DMEM 1D Firmware hash (SHA256)",
+ .asn1_type = V_ASN1_OCTET_STRING,
+ .type = EXT_TYPE_HASH
+ },
+ [DDR_DMEM_UDIMM_2D_HASH_EXT - DDR_FW_CONTENT_CERT_PK_EXT] = {
+ .oid = DDR_DMEM_UDIMM_2D_HASH_OID,
+ .opt = "ddr-dmmem-udimm-2d",
+ .help_msg = "DDR Firmware DMEM UDIMM 2D image file",
+ .sn = "DDR UDIMM DMEM 2D FirmwareHash",
+ .ln = "DDR UDIMM DMEM 2D Firmware hash (SHA256)",
+ .asn1_type = V_ASN1_OCTET_STRING,
+ .type = EXT_TYPE_HASH
+ },
+ [DDR_IMEM_RDIMM_1D_HASH_EXT - DDR_FW_CONTENT_CERT_PK_EXT] = {
+ .oid = DDR_IMEM_RDIMM_1D_HASH_OID,
+ .opt = "ddr-immem-rdimm-1d",
+ .help_msg = "DDR Firmware IMEM RDIMM 1D image file",
+ .sn = "DDR RDIMM IMEM 1D FirmwareHash",
+ .ln = "DDR RDIMM IMEM 1D Firmware hash (SHA256)",
+ .asn1_type = V_ASN1_OCTET_STRING,
+ .type = EXT_TYPE_HASH
+ },
+ [DDR_IMEM_RDIMM_2D_HASH_EXT - DDR_FW_CONTENT_CERT_PK_EXT] = {
+ .oid = DDR_IMEM_RDIMM_2D_HASH_OID,
+ .opt = "ddr-immem-rdimm-2d",
+ .help_msg = "DDR Firmware IMEM RDIMM 2D image file",
+ .sn = "DDR RDIMM IMEM 2D FirmwareHash",
+ .ln = "DDR RDIMM IMEM 2D Firmware hash (SHA256)",
+ .asn1_type = V_ASN1_OCTET_STRING,
+ .type = EXT_TYPE_HASH
+ },
+ [DDR_DMEM_RDIMM_1D_HASH_EXT - DDR_FW_CONTENT_CERT_PK_EXT] = {
+ .oid = DDR_DMEM_RDIMM_1D_HASH_OID,
+ .opt = "ddr-dmmem-rdimm-1d",
+ .help_msg = "DDR Firmware DMEM RDIMM 1D image file",
+ .sn = "DDR RDIMM DMEM 1D FirmwareHash",
+ .ln = "DDR RDIMM DMEM 1D Firmware hash (SHA256)",
+ .asn1_type = V_ASN1_OCTET_STRING,
+ .type = EXT_TYPE_HASH
+ },
+ [DDR_DMEM_RDIMM_2D_HASH_EXT - DDR_FW_CONTENT_CERT_PK_EXT] = {
+ .oid = DDR_DMEM_RDIMM_2D_HASH_OID,
+ .opt = "ddr-dmmem-rdimm-2d",
+ .help_msg = "DDR Firmware DMEM RDIMM 2D image file",
+ .sn = "DDR RDIMM DMEM 2D FirmwareHash",
+ .ln = "DDR RDIMM DMEM 2D Firmware hash (SHA256)",
+ .asn1_type = V_ASN1_OCTET_STRING,
+ .type = EXT_TYPE_HASH
+ }
+};
+
+PLAT_REGISTER_EXTENSIONS(pdef_tbb_ext);
diff --git a/tools/nxp/cert_create_helper/src/pdef_tbb_key.c b/tools/nxp/cert_create_helper/src/pdef_tbb_key.c
new file mode 100644
index 0000000..cf2ebda
--- /dev/null
+++ b/tools/nxp/cert_create_helper/src/pdef_tbb_key.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <pdef_tbb_key.h>
+
+static key_t pdef_tbb_keys[] = {
+ [DDR_FW_CONTENT_KEY - DDR_FW_CONTENT_KEY] = {
+ .id = DDR_FW_CONTENT_KEY,
+ .opt = "ddr-fw-key",
+ .help_msg = "DDR Firmware Content Certificate key (input/output file)",
+ .desc = "DDR Firmware Content Certificate key"
+ }
+};
+
+PLAT_REGISTER_KEYS(pdef_tbb_keys);
diff --git a/tools/nxp/create_pbl/Makefile b/tools/nxp/create_pbl/Makefile
new file mode 100644
index 0000000..f971a74
--- /dev/null
+++ b/tools/nxp/create_pbl/Makefile
@@ -0,0 +1,61 @@
+#
+# Copyright 2018-2020 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+MAKE_HELPERS_DIRECTORY := ../../../make_helpers/
+include ${MAKE_HELPERS_DIRECTORY}build_macros.mk
+include ${MAKE_HELPERS_DIRECTORY}build_env.mk
+
+PROJECT_1 := create_pbl${BIN_EXT}
+OBJECTS_1 := create_pbl.o
+PROJECT_2 := byte_swap${BIN_EXT}
+OBJECTS_2 := byte_swap.o
+V ?= 0
+
+override CPPFLAGS += -D_GNU_SOURCE -D_XOPEN_SOURCE=700
+CFLAGS := -Wall -Werror -pedantic -std=c99
+ifeq (${DEBUG},1)
+ CFLAGS += -g -O0 -DDEBUG
+else
+ CFLAGS += -O2
+endif
+LDLIBS :=
+
+ifeq (${V},0)
+ Q := @
+else
+ Q :=
+endif
+
+INCLUDE_PATHS :=
+
+HOSTCC ?= gcc
+CC = gcc
+
+.PHONY: all clean distclean
+
+all: create_pbl byte_swap
+
+${PROJECT_1}: ${OBJECTS_1} Makefile
+ @echo " LD $@"
+ ${Q}${HOSTCC} ${OBJECTS_1} -o $@ ${LDLIBS}
+ @${ECHO_BLANK_LINE}
+ @echo "Built $@ successfully"
+ @${ECHO_BLANK_LINE}
+
+${PROJECT_2}: ${OBJECTS_2} Makefile
+ @echo " LD $@"
+ ${Q}${HOSTCC} ${OBJECTS_2} -o $@ ${LDLIBS}
+ @${ECHO_BLANK_LINE}
+ @echo "Built $@ successfully"
+ @${ECHO_BLANK_LINE}
+
+%.o: %.c %.h Makefile
+ @echo " CC $<"
+ ${Q}${HOSTCC} -c ${CPPFLAGS} ${CFLAGS} ${INCLUDE_PATHS} $< -o $@
+
+clean:
+ $(call SHELL_DELETE_ALL, ${PROJECT_1} ${OBJECTS_1})
+ $(call SHELL_DELETE_ALL, ${PROJECT_2} ${OBJECTS_2})
diff --git a/tools/nxp/create_pbl/README b/tools/nxp/create_pbl/README
new file mode 100644
index 0000000..3b6f854
--- /dev/null
+++ b/tools/nxp/create_pbl/README
@@ -0,0 +1,65 @@
+Description:
+------------
+Tool 'create_pbl' is a standalone tool to create the PBL images.
+ where,
+ On the basis of Chassis,
+ RCW image is placed first followed by the,
+ PBI commands to copy the,
+ Input BL2 image stored on the,
+ Specified boot source (QSPI or SD or NOR) to the,
+ Specified destination address.
+
+
+Usage in standalone way:
+-----------------------
+
+./create_pbl [options] (mentioned below):
+
+ -r <RCW file-name> - name of RCW binary file.
+ -i <BL2 Bin file-name> - file to be added to rcw file.
+ -c <SoC Number> - SoC numeric identifier, may be one of
+ 1012,1023,1026.1028,
+ 1043,1046,1088,2080,
+ 2088,2160
+ -b <boot source id> - Boot source id string, may be one of
+ "qspi", "nor", "nand", "sd", "emmc"
+ -d <Address> - Destination address where BL2
+ image is to be copied
+ -o <output filename> - Name of PBL image generated
+ as an output of the tool.
+ -e <Address> - [Optional] Entry Point Address
+ of the BL2.bin
+ -f <Address> - BL2 image offset
+ on Boot Source for block copy.
+ command for chassis >=3.)
+ (Must for Ch3, Ignored for Ch2)
+ -h Help.
+ -s Secure boot.
+
+ -s secure boot
+ -c SoC Number (see description above)
+ -b Boot source.
+ -r RCW binary file.
+ -i Input file that is to be added to rcw file.
+ -o Name of output file
+ -f Source Offset (Block Copy)
+ -d Destination address to which file has to be copied
+ -h Help.
+
+Example:
+ ./create_pbl -r <RCW file> -i <bl2.bin> -c <chassis_no> -b <boot_source = sd/qspi/nor> -d <Destination_Addr> -o <pbl_image_name>
+
+
+
+Usage at compilation time:
+--------------------------------
+
+ make <compilation command......> pbl RCW=<Path_to_RCW_File>/<rcw_file_name.bin>
+
+Example: QSPI Boot For LS1046ARDB-
+
+ make PLAT=ls1046rdb all fip BOOT_MODE=qspi SPD=opteed BL32=tee.bin BL33=u-boot-ls1046.bin pbl RCW=/home/pankaj/flexbuild/packages/firmware/dash-rcw/ls1046ardb/RR_FFSSPPPN_1133_5506/rcw_1600_qspiboot.bin
+
+Example: QSPI Boot For LX2160ARDB-
+
+ make PLAT=lx2160ardb all fip BOOT_MODE=flexspi_nor SPD=opteed BL32=tee_lx2.bin BL33=u-boot_lx2160.bin pbl RCW=plat/nxp/soc-lx2160/lx2160ardb/rcw_1900_600_1600_19_5_2.bin
diff --git a/tools/nxp/create_pbl/byte_swap.c b/tools/nxp/create_pbl/byte_swap.c
new file mode 100644
index 0000000..1d0bfce
--- /dev/null
+++ b/tools/nxp/create_pbl/byte_swap.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <getopt.h>
+#include <unistd.h>
+
+#define NUM_MEM_BLOCK 1
+#define FOUR_BYTE_ALIGN 4
+#define EIGHT_BYTE_ALIGN 8
+#define SIZE_TWO_PBL_CMD 24
+
+#define SUCCESS 0
+#define FAILURE -1
+#define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24)| \
+ (((word) & 0x00ff0000) >> 8) | \
+ (((word) & 0x0000ff00) << 8) | \
+ (((word) & 0x000000ff) << 24))
+
+
+/*
+ * Returns:
+ * SUCCESS, on successful byte swapping.
+ * FAILURE, on failure.
+ */
+int do_byteswap(FILE *fp)
+{
+ int bytes = 0;
+ uint32_t upper_byte;
+ uint32_t lower_byte;
+ uint32_t pad = 0U;
+ /* Carries number of Padding bytes to be appended to
+ * make file size 8 byte aligned.
+ */
+ int append_bytes;
+ int ret = FAILURE;
+
+ fseek(fp, 0L, SEEK_END);
+ bytes = ftell(fp);
+
+ append_bytes = EIGHT_BYTE_ALIGN - (bytes % EIGHT_BYTE_ALIGN);
+ if (append_bytes != 0) {
+ if (fwrite(&pad, append_bytes, NUM_MEM_BLOCK, fp)
+ != NUM_MEM_BLOCK) {
+ printf("%s: Error in appending padding bytes.\n",
+ __func__);
+ goto byteswap_err;
+ }
+ bytes += append_bytes;
+ }
+
+ rewind(fp);
+ while (bytes > 0) {
+ if ((fread(&upper_byte, sizeof(upper_byte), NUM_MEM_BLOCK, fp)
+ != NUM_MEM_BLOCK) && (feof(fp) == 0)) {
+ printf("%s: Error reading upper bytes.\n", __func__);
+ goto byteswap_err;
+ }
+ if ((fread(&lower_byte, sizeof(lower_byte), NUM_MEM_BLOCK, fp)
+ != NUM_MEM_BLOCK) && (feof(fp) == 0)) {
+ printf("%s: Error reading lower bytes.\n", __func__);
+ goto byteswap_err;
+ }
+ fseek(fp, -8L, SEEK_CUR);
+ upper_byte = BYTE_SWAP_32(upper_byte);
+ lower_byte = BYTE_SWAP_32(lower_byte);
+ if (fwrite(&lower_byte, sizeof(lower_byte), NUM_MEM_BLOCK, fp)
+ != NUM_MEM_BLOCK) {
+ printf("%s: Error writing lower bytes.\n", __func__);
+ goto byteswap_err;
+ }
+ if (fwrite(&upper_byte, sizeof(upper_byte), NUM_MEM_BLOCK, fp)
+ != NUM_MEM_BLOCK) {
+ printf("%s: Error writing upper bytes.\n", __func__);
+ goto byteswap_err;
+ }
+ bytes -= EIGHT_BYTE_ALIGN;
+ }
+ ret = SUCCESS;
+
+byteswap_err:
+ return ret;
+}
+
+int main(int argc, char **argv)
+{
+ FILE *fp = NULL;
+ int ret = 0;
+
+ if (argc > 2) {
+ printf("Usage format is byteswap <filename>");
+ return -1;
+ }
+
+ fp = fopen(argv[1], "rb+");
+ if (fp == NULL) {
+ printf("%s: Error opening the input file: %s\n",
+ __func__, argv[1]);
+ return -1;
+ }
+
+ ret = do_byteswap(fp);
+ fclose(fp);
+ return ret;
+}
diff --git a/tools/nxp/create_pbl/create_pbl.c b/tools/nxp/create_pbl/create_pbl.c
new file mode 100644
index 0000000..244b0fb
--- /dev/null
+++ b/tools/nxp/create_pbl/create_pbl.c
@@ -0,0 +1,996 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <getopt.h>
+#include <unistd.h>
+
+#define NUM_MEM_BLOCK 1
+#define FOUR_BYTE_ALIGN 4
+#define EIGHT_BYTE_ALIGN 8
+#define SIZE_TWO_PBL_CMD 24
+
+/* Define for add_boot_ptr_cmd() */
+#define BOOTPTR_ADDR 0x09570604
+#define CSF_ADDR_SB 0x09ee0200
+/* CCSR write command to address 0x1e00400 i.e BOOTLOCPTR */
+#define BOOTPTR_ADDR_CH3 0x31e00400
+/* Load CSF header command */
+#define CSF_ADDR_SB_CH3 0x80220000
+
+#define MAND_ARG_MASK 0xFFF3
+#define ARG_INIT_MASK 0xFF00
+#define RCW_FILE_NAME_ARG_MASK 0x0080
+#define IN_FILE_NAME_ARG_MASK 0x0040
+#define CHASSIS_ARG_MASK 0x0020
+#define BOOT_SRC_ARG_MASK 0x0010
+#define ENTRY_POINT_ADDR_ARG_MASK 0x0008
+#define BL2_BIN_STRG_LOC_BOOT_SRC_ARG_MASK 0x0004
+#define BL2_BIN_CPY_DEST_ADDR_ARG_MASK 0x0002
+#define OP_FILE_NAME_ARG_MASK 0x0001
+
+/* Define for add_cpy_cmd() */
+#define OFFSET_MASK 0x00ffffff
+#define WRITE_CMD_BASE 0x81000000
+#define MAX_PBI_DATA_LEN_BYTE 64
+
+/* 140 Bytes = Preamble + LOAD RCW command + RCW (128 bytes) + Checksum */
+#define CHS3_CRC_PAYLOAD_START_OFFSET 140
+
+#define PBI_CRC_POLYNOMIAL 0x04c11db7
+
+typedef enum {
+ CHASSIS_UNKNOWN,
+ CHASSIS_2,
+ CHASSIS_3,
+ CHASSIS_3_2,
+ CHASSIS_MAX /* must be last item in list */
+} chassis_t;
+
+typedef enum {
+ UNKNOWN_BOOT = 0,
+ IFC_NOR_BOOT,
+ IFC_NAND_BOOT,
+ QSPI_BOOT,
+ SD_BOOT,
+ EMMC_BOOT,
+ FLXSPI_NOR_BOOT,
+ FLXSPI_NAND_BOOT,
+ FLXSPI_NAND4K_BOOT,
+ MAX_BOOT /* must be last item in list */
+} boot_src_t;
+
+/* Base Addresses where PBL image is copied depending on the boot source.
+ * Boot address map varies as per Chassis architecture.
+ */
+#define BASE_ADDR_UNDEFINED 0xFFFFFFFF
+#define BASE_ADDR_QSPI 0x20000000
+#define BASE_ADDR_SD 0x00001000
+#define BASE_ADDR_IFC_NOR 0x30000000
+#define BASE_ADDR_EMMC 0x00001000
+#define BASE_ADDR_FLX_NOR 0x20000000
+#define BASE_ADDR_NAND 0x20000000
+
+uint32_t base_addr_ch3[MAX_BOOT] = {
+ BASE_ADDR_UNDEFINED,
+ BASE_ADDR_IFC_NOR,
+ BASE_ADDR_UNDEFINED, /*IFC NAND */
+ BASE_ADDR_QSPI,
+ BASE_ADDR_SD,
+ BASE_ADDR_EMMC,
+ BASE_ADDR_UNDEFINED, /*FLXSPI NOR */
+ BASE_ADDR_UNDEFINED, /*FLXSPI NAND 2K */
+ BASE_ADDR_UNDEFINED /*FLXSPI NAND 4K */
+};
+
+uint32_t base_addr_ch32[MAX_BOOT] = {
+ BASE_ADDR_UNDEFINED,
+ BASE_ADDR_UNDEFINED, /* IFC NOR */
+ BASE_ADDR_UNDEFINED, /* IFC NAND */
+ BASE_ADDR_UNDEFINED, /* QSPI */
+ BASE_ADDR_SD,
+ BASE_ADDR_EMMC,
+ BASE_ADDR_FLX_NOR,
+ BASE_ADDR_UNDEFINED, /*FLXSPI NAND 2K */
+ BASE_ADDR_UNDEFINED /*FLXSPI NAND 4K */
+};
+
+/* for Chassis 3 */
+uint32_t blk_cpy_hdr_map_ch3[] = {
+
+ 0, /* Unknown Boot Source */
+ 0x80000020, /* NOR_BOOT */
+ 0x0, /* NAND_BOOT */
+ 0x80000062, /* QSPI_BOOT */
+ 0x80000040, /* SD_BOOT */
+ 0x80000041, /* EMMC_BOOT */
+ 0x0, /* FLEXSPI NOR_BOOT */
+ 0x0, /* FLEX SPI NAND2K BOOT */
+ 0x0, /* CHASIS3_2_NAND4K_BOOT */
+};
+
+uint32_t blk_cpy_hdr_map_ch32[] = {
+ 0, /* Unknown Boot Source */
+ 0x0, /* NOR_BOOT */
+ 0x0, /* NAND_BOOT */
+ 0x0, /* QSPI_BOOT */
+ 0x80000008, /* SD_BOOT */
+ 0x80000009, /* EMMC_BOOT */
+ 0x8000000F, /* FLEXSPI NOR_BOOT */
+ 0x8000000C, /* FLEX SPI NAND2K BOOT */
+ 0x8000000D, /* CHASIS3_2_NAND4K_BOOT */
+};
+
+char *boot_src_string[] = {
+ "UNKNOWN_BOOT",
+ "IFC_NOR_BOOT",
+ "IFC_NAND_BOOT",
+ "QSPI_BOOT",
+ "SD_BOOT",
+ "EMMC_BOOT",
+ "FLXSPI_NOR_BOOT",
+ "FLXSPI_NAND_BOOT",
+ "FLXSPI_NAND4K_BOOT",
+};
+
+enum stop_command {
+ STOP_COMMAND = 0,
+ CRC_STOP_COMMAND
+};
+
+/* Structure will get populated in the main function
+ * as part of parsing the command line arguments.
+ * All member parameters are mandatory except:
+ * -ep
+ * -src_addr
+ */
+struct pbl_image {
+ char *rcw_nm; /* Input RCW File */
+ char *sec_imgnm; /* Input BL2 binary */
+ char *imagefile; /* Generated output file */
+ boot_src_t boot_src; /* Boot Source - QSPI, SD, NOR, NAND etc */
+ uint32_t src_addr; /* Source Address */
+ uint32_t addr; /* Load address */
+ uint32_t ep; /* Entry point <opt> default is load address */
+ chassis_t chassis; /* Chassis type */
+} pblimg;
+
+#define SUCCESS 0
+#define FAILURE -1
+#define CRC_STOP_CMD_ARM 0x08610040
+#define CRC_STOP_CMD_ARM_CH3 0x808f0000
+#define STOP_CMD_ARM_CH3 0x80ff0000
+#define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24)| \
+ (((word) & 0x00ff0000) >> 8) | \
+ (((word) & 0x0000ff00) << 8) | \
+ (((word) & 0x000000ff) << 24))
+
+#define PBI_LEN_MASK 0xFFF00000
+#define PBI_LEN_SHIFT 20
+#define NUM_RCW_WORD 35
+#define PBI_LEN_ADD 6
+
+#define MAX_CRC_ENTRIES 256
+
+/* SoC numeric identifier */
+#define SOC_LS1012 1012
+#define SOC_LS1023 1023
+#define SOC_LS1026 1026
+#define SOC_LS1028 1028
+#define SOC_LS1043 1043
+#define SOC_LS1046 1046
+#define SOC_LS1088 1088
+#define SOC_LS2080 2080
+#define SOC_LS2088 2088
+#define SOC_LX2160 2160
+
+static uint32_t pbl_size;
+bool sb_flag;
+
+/***************************************************************************
+ * Description : CRC32 Lookup Table
+ ***************************************************************************/
+static uint32_t crc32_lookup[] = {
+ 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
+ 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
+ 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
+ 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
+ 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
+ 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
+ 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
+ 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
+ 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
+ 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
+ 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
+ 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
+ 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
+ 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
+ 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
+ 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
+ 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
+ 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
+ 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
+ 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
+ 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
+ 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
+ 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
+ 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
+ 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
+ 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
+ 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
+ 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
+ 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
+ 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
+ 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
+ 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
+ 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
+ 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
+ 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
+ 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
+ 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
+ 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
+ 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
+ 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
+ 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
+ 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
+ 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
+ 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
+ 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
+ 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
+ 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04,
+ 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
+ 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
+ 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
+ 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
+ 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
+ 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
+ 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
+ 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
+ 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
+ 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
+ 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
+ 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
+ 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
+ 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
+ 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
+ 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
+ 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
+ };
+
+
+static void print_usage(void)
+{
+ printf("\nCorrect Usage of Tool is:\n");
+ printf("\n ./create_pbl [options] (mentioned below):\n\n");
+ printf("\t-r <RCW file-name> - name of RCW binary file.\n");
+ printf("\t-i <BL2 Bin file-name> - file to be added to rcw file.\n");
+ printf("\t-c <Number> - Chassis Architecture (=2 or =3\n");
+ printf("\t or =4 for 3.2).\n");
+ printf("\t-b <qspi/nor/nand/sd> - Boot source.\n");
+ printf("\t-d <Address> - Destination address where BL2\n");
+ printf("\t image is to be copied\n");
+ printf("\t-o <output filename> - Name of PBL image generated\n");
+ printf("\t as an output of the tool.\n");
+ printf("\t-f <Address> - BL2 image Src Offset\n");
+ printf("\t on Boot Source for block copy.\n");
+ printf("\t command for chassis >=3.)\n");
+ printf("\t-e <Address> - [Optional] Entry Point Address\n");
+ printf("\t of the BL2.bin\n");
+ printf("\t-s Secure Boot.\n");
+ printf("\t-h Help.\n");
+ printf("\n\n");
+ exit(0);
+
+}
+
+/***************************************************************************
+ * Function : crypto_calculate_checksum()
+ * Arguments : data - Pointer to FILE
+ * num - Number of 32 bit words for checksum
+ * Return : Checksum Value
+ * Description : Calculate Checksum over the data
+ ***************************************************************************/
+uint32_t crypto_calculate_checksum(FILE *fp_rcw_pbi_op, uint32_t num)
+{
+ uint32_t i;
+ uint64_t sum = 0;
+ uint32_t word;
+
+ fseek(fp_rcw_pbi_op, 0L, SEEK_SET);
+ for (i = 0; i < num ; i++) {
+ if ((fread(&word, sizeof(word), NUM_MEM_BLOCK, fp_rcw_pbi_op))
+ < NUM_MEM_BLOCK) {
+ printf("%s: Error reading word.\n", __func__);
+ return FAILURE;
+ }
+ sum = sum + word;
+ sum = sum & 0xFFFFFFFF;
+ }
+ return (uint32_t)sum;
+}
+
+/***************************************************************************
+ * Function : add_pbi_stop_cmd
+ * Arguments : fp_rcw_pbi_op - output rcw_pbi file pointer
+ * Return : SUCCESS or FAILURE
+ * Description : This function insert pbi stop command.
+ ***************************************************************************/
+int add_pbi_stop_cmd(FILE *fp_rcw_pbi_op, enum stop_command flag)
+{
+ int ret = FAILURE;
+ int32_t pbi_stop_cmd;
+ uint32_t pbi_crc = 0xffffffff, i, j, c;
+ uint32_t crc_table[MAX_CRC_ENTRIES];
+ uint8_t data;
+
+ switch (pblimg.chassis) {
+ case CHASSIS_2:
+ pbi_stop_cmd = BYTE_SWAP_32(CRC_STOP_CMD_ARM);
+ break;
+ case CHASSIS_3:
+ case CHASSIS_3_2:
+ /* Based on flag add the corresponsding cmd
+ * -- stop cmd or stop with CRC cmd
+ */
+ if (flag == CRC_STOP_COMMAND) {
+ pbi_stop_cmd = CRC_STOP_CMD_ARM_CH3;
+ } else {
+ pbi_stop_cmd = STOP_CMD_ARM_CH3;
+ }
+ break;
+ case CHASSIS_UNKNOWN:
+ case CHASSIS_MAX:
+ default:
+ printf("Internal Error: Invalid Chassis val = %d.\n",
+ pblimg.chassis);
+ goto pbi_stop_err;
+ }
+
+ if (fwrite(&pbi_stop_cmd, sizeof(pbi_stop_cmd), NUM_MEM_BLOCK,
+ fp_rcw_pbi_op) != NUM_MEM_BLOCK) {
+ printf("%s: Error in Writing PBI STOP CMD\n", __func__);
+ goto pbi_stop_err;
+ }
+
+ if (flag == CRC_STOP_COMMAND) {
+ for (i = 0; i < MAX_CRC_ENTRIES; i++) {
+ c = i << 24;
+ for (j = 0; j < 8; j++) {
+ c = (c & 0x80000000) ?
+ PBI_CRC_POLYNOMIAL ^ (c << 1) : c << 1;
+ }
+
+ crc_table[i] = c;
+ }
+ }
+
+ switch (pblimg.chassis) {
+ case CHASSIS_2:
+ /* Chassis 2: CRC is calculated on RCW + PBL cmd.*/
+ fseek(fp_rcw_pbi_op, 0L, SEEK_SET);
+ break;
+ case CHASSIS_3:
+ case CHASSIS_3_2:
+ /* Chassis 3: CRC is calculated on PBL cmd only. */
+ fseek(fp_rcw_pbi_op, CHS3_CRC_PAYLOAD_START_OFFSET, SEEK_SET);
+ break;
+ case CHASSIS_UNKNOWN:
+ case CHASSIS_MAX:
+ printf("%s: Unknown Chassis.\n", __func__);
+ goto pbi_stop_err;
+ }
+
+ while ((fread(&data, sizeof(data), NUM_MEM_BLOCK, fp_rcw_pbi_op))
+ == NUM_MEM_BLOCK) {
+ if (flag == CRC_STOP_COMMAND) {
+ if (pblimg.chassis == CHASSIS_2) {
+ pbi_crc = crc_table
+ [((pbi_crc >> 24) ^ (data)) & 0xff] ^
+ (pbi_crc << 8);
+ } else {
+ pbi_crc = (pbi_crc >> 8) ^
+ crc32_lookup[((pbi_crc) ^
+ (data)) & 0xff];
+ }
+ }
+ }
+
+ switch (pblimg.chassis) {
+ case CHASSIS_2:
+ pbi_crc = BYTE_SWAP_32(pbi_crc);
+ break;
+ case CHASSIS_3:
+ case CHASSIS_3_2:
+ if (flag == CRC_STOP_COMMAND) {
+ pbi_crc = pbi_crc ^ 0xFFFFFFFF;
+ } else {
+ pbi_crc = 0x00000000;
+ }
+ break;
+ case CHASSIS_UNKNOWN:
+ case CHASSIS_MAX:
+ printf("%s: Unknown Chassis.\n", __func__);
+ goto pbi_stop_err;
+ }
+
+ if (fwrite(&pbi_crc, sizeof(pbi_crc), NUM_MEM_BLOCK, fp_rcw_pbi_op)
+ != NUM_MEM_BLOCK) {
+ printf("%s: Error in Writing PBI PBI CRC\n", __func__);
+ goto pbi_stop_err;
+ }
+ ret = SUCCESS;
+
+pbi_stop_err:
+ return ret;
+}
+
+/*
+ * Returns:
+ * File size in bytes, on Success.
+ * FAILURE, on failure.
+ */
+int get_filesize(const char *c)
+{
+ FILE *fp;
+ int ret = FAILURE;
+
+ fp = fopen(c, "rb");
+ if (fp == NULL) {
+ fprintf(stderr, "%s: Error in opening the file: %s\n",
+ __func__, c);
+ goto filesize_err;
+ }
+
+ fseek(fp, 0L, SEEK_END);
+ ret = ftell(fp);
+ fclose(fp);
+
+filesize_err:
+ return ret;
+}
+
+/***************************************************************************
+ * Function : get_bootptr
+ * Arguments : fp_rcw_pbi_op - Pointer to output file
+ * Return : SUCCESS or FAILURE
+ * Description : Add bootptr pbi command to output file
+ ***************************************************************************/
+int add_boot_ptr_cmd(FILE *fp_rcw_pbi_op)
+{
+ uint32_t bootptr_addr;
+ int ret = FAILURE;
+
+ switch (pblimg.chassis) {
+ case CHASSIS_2:
+ if (sb_flag == true)
+ bootptr_addr = BYTE_SWAP_32(CSF_ADDR_SB);
+ else
+ bootptr_addr = BYTE_SWAP_32(BOOTPTR_ADDR);
+ pblimg.ep = BYTE_SWAP_32(pblimg.ep);
+ break;
+ case CHASSIS_3:
+ case CHASSIS_3_2:
+ if (sb_flag == true)
+ bootptr_addr = CSF_ADDR_SB_CH3;
+ else
+ bootptr_addr = BOOTPTR_ADDR_CH3;
+ break;
+ case CHASSIS_UNKNOWN:
+ case CHASSIS_MAX:
+ default:
+ printf("Internal Error: Invalid Chassis val = %d.\n",
+ pblimg.chassis);
+ goto bootptr_err;
+ }
+
+ if (fwrite(&bootptr_addr, sizeof(bootptr_addr), NUM_MEM_BLOCK,
+ fp_rcw_pbi_op) != NUM_MEM_BLOCK) {
+ printf("%s: Error in Writing PBI Words:[%d].\n",
+ __func__, ret);
+ goto bootptr_err;
+ }
+
+ if (pblimg.ep != 0) {
+ if (fwrite(&pblimg.ep, sizeof(pblimg.ep), NUM_MEM_BLOCK,
+ fp_rcw_pbi_op) != NUM_MEM_BLOCK) {
+ printf("%s: Error in Writing PBI Words\n", __func__);
+ goto bootptr_err;
+ }
+ }
+
+ printf("\nBoot Location Pointer= %x\n", BYTE_SWAP_32(pblimg.ep));
+ ret = SUCCESS;
+
+bootptr_err:
+ return ret;
+}
+
+/***************************************************************************
+ * Function : add_blk_cpy_cmd
+ * Arguments : pbi_word - pointer to pbi commands
+ * args - Command line args flag.
+ * Return : SUCCESS or FAILURE
+ * Description : Add pbi commands for block copy cmd in pbi_words
+ ***************************************************************************/
+int add_blk_cpy_cmd(FILE *fp_rcw_pbi_op, uint16_t args)
+{
+ uint32_t blk_cpy_hdr;
+ uint32_t file_size, new_file_size;
+ uint32_t align = 4;
+ int ret = FAILURE;
+ int num_pad_bytes = 0;
+
+ if ((args & BL2_BIN_STRG_LOC_BOOT_SRC_ARG_MASK) == 0) {
+ printf("ERROR: Offset not specified for Block Copy Cmd.\n");
+ printf("\tSee Usage and use -f option\n");
+ goto blk_copy_err;
+ }
+
+ switch (pblimg.chassis) {
+ case CHASSIS_3:
+ /* Block copy command */
+ blk_cpy_hdr = blk_cpy_hdr_map_ch3[pblimg.boot_src];
+ pblimg.src_addr += base_addr_ch3[pblimg.boot_src];
+ break;
+ case CHASSIS_3_2:
+ /* Block copy command */
+ blk_cpy_hdr = blk_cpy_hdr_map_ch32[pblimg.boot_src];
+ pblimg.src_addr += base_addr_ch32[pblimg.boot_src];
+ break;
+ default:
+ printf("%s: Error invalid chassis type for this command.\n",
+ __func__);
+ goto blk_copy_err;
+ }
+
+ file_size = get_filesize(pblimg.sec_imgnm);
+ if (file_size > 0) {
+ new_file_size = (file_size + (file_size % align));
+
+ /* Add Block copy command */
+ if (fwrite(&blk_cpy_hdr, sizeof(blk_cpy_hdr), NUM_MEM_BLOCK,
+ fp_rcw_pbi_op) != NUM_MEM_BLOCK) {
+ printf("%s: Error writing blk_cpy_hdr to the file.\n",
+ __func__);
+ goto blk_copy_err;
+ }
+
+ if ((args & BL2_BIN_STRG_LOC_BOOT_SRC_ARG_MASK) == 0)
+ num_pad_bytes = pblimg.src_addr % 4;
+
+ /* Add Src address word */
+ if (fwrite(&pblimg.src_addr + num_pad_bytes,
+ sizeof(pblimg.src_addr), NUM_MEM_BLOCK,
+ fp_rcw_pbi_op) != NUM_MEM_BLOCK) {
+ printf("%s: Error writing BLK SRC Addr to the file.\n",
+ __func__);
+ goto blk_copy_err;
+ }
+
+ /* Add Dest address word */
+ if (fwrite(&pblimg.addr, sizeof(pblimg.addr),
+ NUM_MEM_BLOCK, fp_rcw_pbi_op) != NUM_MEM_BLOCK) {
+ printf("%s: Error writing DST Addr to the file.\n",
+ __func__);
+ goto blk_copy_err;
+ }
+
+ /* Add size */
+ if (fwrite(&new_file_size, sizeof(new_file_size),
+ NUM_MEM_BLOCK, fp_rcw_pbi_op) != NUM_MEM_BLOCK) {
+ printf("%s: Error writing size to the file.\n",
+ __func__);
+ goto blk_copy_err;
+ }
+ }
+
+ ret = SUCCESS;
+
+blk_copy_err:
+ return ret;
+}
+
+/***************************************************************************
+ * Function : add_cpy_cmd
+ * Arguments : pbi_word - pointer to pbi commands
+ * Return : SUCCESS or FAILURE
+ * Description : Append pbi commands for copying BL2 image to the
+ * load address stored in pbl_image.addr
+ ***************************************************************************/
+int add_cpy_cmd(FILE *fp_rcw_pbi_op)
+{
+ uint32_t ALTCBAR_ADDRESS = BYTE_SWAP_32(0x09570158);
+ uint32_t WAIT_CMD_WRITE_ADDRESS = BYTE_SWAP_32(0x096100c0);
+ uint32_t WAIT_CMD = BYTE_SWAP_32(0x000FFFFF);
+ int file_size;
+ uint32_t pbi_cmd, altcbar;
+ uint8_t pbi_data[MAX_PBI_DATA_LEN_BYTE];
+ uint32_t dst_offset;
+ FILE *fp_img = NULL;
+ int ret = FAILURE;
+
+ altcbar = pblimg.addr;
+ dst_offset = pblimg.addr;
+ fp_img = fopen(pblimg.sec_imgnm, "rb");
+ if (fp_img == NULL) {
+ printf("%s: Error in opening the file: %s\n", __func__,
+ pblimg.sec_imgnm);
+ goto add_cpy_err;
+ }
+ file_size = get_filesize(pblimg.sec_imgnm);
+ altcbar = 0xfff00000 & altcbar;
+ altcbar = BYTE_SWAP_32(altcbar >> 16);
+ if (fwrite(&ALTCBAR_ADDRESS, sizeof(ALTCBAR_ADDRESS), NUM_MEM_BLOCK,
+ fp_rcw_pbi_op) != NUM_MEM_BLOCK) {
+ printf("%s: Error in writing address of ALTCFG CMD.\n",
+ __func__);
+ goto add_cpy_err;
+ }
+ if (fwrite(&altcbar, sizeof(altcbar), NUM_MEM_BLOCK, fp_rcw_pbi_op)
+ != NUM_MEM_BLOCK) {
+ printf("%s: Error in writing ALTCFG CMD.\n", __func__);
+ goto add_cpy_err;
+ }
+ if (fwrite(&WAIT_CMD_WRITE_ADDRESS, sizeof(WAIT_CMD_WRITE_ADDRESS),
+ NUM_MEM_BLOCK, fp_rcw_pbi_op) != NUM_MEM_BLOCK) {
+ printf("%s: Error in writing address of WAIT_CMD.\n",
+ __func__);
+ goto add_cpy_err;
+ }
+ if (fwrite(&WAIT_CMD, sizeof(WAIT_CMD), NUM_MEM_BLOCK, fp_rcw_pbi_op)
+ != NUM_MEM_BLOCK) {
+ printf("%s: Error in writing WAIT_CMD.\n", __func__);
+ goto add_cpy_err;
+ }
+ do {
+ memset(pbi_data, 0, MAX_PBI_DATA_LEN_BYTE);
+
+ ret = fread(&pbi_data, MAX_PBI_DATA_LEN_BYTE,
+ NUM_MEM_BLOCK, fp_img);
+ if ((ret != NUM_MEM_BLOCK) && (!feof(fp_img))) {
+ printf("%s: Error writing ALTCFG Word: [%d].\n",
+ __func__, ret);
+ goto add_cpy_err;
+ }
+
+ dst_offset &= OFFSET_MASK;
+ pbi_cmd = WRITE_CMD_BASE | dst_offset;
+ pbi_cmd = BYTE_SWAP_32(pbi_cmd);
+ if (fwrite(&pbi_cmd, sizeof(pbi_cmd), NUM_MEM_BLOCK,
+ fp_rcw_pbi_op) != NUM_MEM_BLOCK) {
+ printf("%s: Error writing ALTCFG Word write cmd.\n",
+ __func__);
+ goto add_cpy_err;
+ }
+ if (fwrite(&pbi_data, MAX_PBI_DATA_LEN_BYTE, NUM_MEM_BLOCK,
+ fp_rcw_pbi_op) != NUM_MEM_BLOCK) {
+ printf("%s: Error writing ALTCFG_Word.\n", __func__);
+ goto add_cpy_err;
+ }
+ dst_offset += MAX_PBI_DATA_LEN_BYTE;
+ file_size -= MAX_PBI_DATA_LEN_BYTE;
+ } while (!feof(fp_img));
+
+ ret = SUCCESS;
+
+add_cpy_err:
+ if (fp_img != NULL) {
+ fclose(fp_img);
+ }
+ return ret;
+}
+
+int main(int argc, char **argv)
+{
+ FILE *file = NULL;
+ char *ptr;
+ int opt;
+ int tmp;
+ uint16_t args = ARG_INIT_MASK;
+ FILE *fp_rcw_pbi_ip = NULL, *fp_rcw_pbi_op = NULL;
+ uint32_t word, word_1;
+ int ret = FAILURE;
+ bool bootptr_flag = false;
+ enum stop_command flag_stop_cmd = CRC_STOP_COMMAND;
+
+ /* Initializing the global structure to zero. */
+ memset(&pblimg, 0x0, sizeof(struct pbl_image));
+
+ while ((opt = getopt(argc, argv,
+ ":b:f:r:i:e:d:c:o:h:s")) != -1) {
+ switch (opt) {
+ case 'd':
+ pblimg.addr = strtoull(optarg, &ptr, 16);
+ if (*ptr != 0) {
+ fprintf(stderr, "CMD Error: invalid load or destination address %s\n", optarg);
+ goto exit_main;
+ }
+ args |= BL2_BIN_CPY_DEST_ADDR_ARG_MASK;
+ break;
+ case 'r':
+ pblimg.rcw_nm = optarg;
+ file = fopen(pblimg.rcw_nm, "r");
+ if (file == NULL) {
+ printf("CMD Error: Opening the RCW File.\n");
+ goto exit_main;
+ } else {
+ args |= RCW_FILE_NAME_ARG_MASK;
+ fclose(file);
+ }
+ break;
+ case 'e':
+ bootptr_flag = true;
+ pblimg.ep = strtoull(optarg, &ptr, 16);
+ if (*ptr != 0) {
+ fprintf(stderr,
+ "CMD Error: Invalid entry point %s\n", optarg);
+ goto exit_main;
+ }
+ break;
+ case 'h':
+ print_usage();
+ break;
+ case 'i':
+ pblimg.sec_imgnm = optarg;
+ file = fopen(pblimg.sec_imgnm, "r");
+ if (file == NULL) {
+ printf("CMD Error: Opening Input file.\n");
+ goto exit_main;
+ } else {
+ args |= IN_FILE_NAME_ARG_MASK;
+ fclose(file);
+ }
+ break;
+ case 'c':
+ tmp = atoi(optarg);
+ switch (tmp) {
+ case SOC_LS1012:
+ case SOC_LS1023:
+ case SOC_LS1026:
+ case SOC_LS1043:
+ case SOC_LS1046:
+ pblimg.chassis = CHASSIS_2;
+ break;
+ case SOC_LS1088:
+ case SOC_LS2080:
+ case SOC_LS2088:
+ pblimg.chassis = CHASSIS_3;
+ break;
+ case SOC_LS1028:
+ case SOC_LX2160:
+ pblimg.chassis = CHASSIS_3_2;
+ break;
+ default:
+ printf("CMD Error: Invalid SoC Val = %d.\n", tmp);
+ goto exit_main;
+ }
+
+ args |= CHASSIS_ARG_MASK;
+ break;
+ case 'o':
+ pblimg.imagefile = optarg;
+ args |= OP_FILE_NAME_ARG_MASK;
+ break;
+ case 's':
+ sb_flag = true;
+ break;
+ case 'b':
+ if (strcmp(optarg, "qspi") == 0) {
+ pblimg.boot_src = QSPI_BOOT;
+ } else if (strcmp(optarg, "nor") == 0) {
+ pblimg.boot_src = IFC_NOR_BOOT;
+ } else if (strcmp(optarg, "nand") == 0) {
+ pblimg.boot_src = IFC_NAND_BOOT;
+ } else if (strcmp(optarg, "sd") == 0) {
+ pblimg.boot_src = SD_BOOT;
+ } else if (strcmp(optarg, "emmc") == 0) {
+ pblimg.boot_src = EMMC_BOOT;
+ } else if (strcmp(optarg, "flexspi_nor") == 0) {
+ pblimg.boot_src = FLXSPI_NOR_BOOT;
+ } else if (strcmp(optarg, "flexspi_nand") == 0) {
+ pblimg.boot_src = FLXSPI_NAND_BOOT;
+ } else if (strcmp(optarg, "flexspi_nand2k") == 0) {
+ pblimg.boot_src = FLXSPI_NAND4K_BOOT;
+ } else {
+ printf("CMD Error: Invalid boot source.\n");
+ goto exit_main;
+ }
+ args |= BOOT_SRC_ARG_MASK;
+ break;
+ case 'f':
+ pblimg.src_addr = strtoull(optarg, &ptr, 16);
+ if (*ptr != 0) {
+ fprintf(stderr,
+ "CMD Error: Invalid src offset %s\n", optarg);
+ goto exit_main;
+ }
+ args |= BL2_BIN_STRG_LOC_BOOT_SRC_ARG_MASK;
+ break;
+ default:
+ /* issue a warning and skip the unknown arg */
+ printf("Cmd Warning: Invalid Arg = %c.\n", opt);
+ }
+ }
+
+ if ((args & MAND_ARG_MASK) != MAND_ARG_MASK) {
+ print_usage();
+ }
+
+ fp_rcw_pbi_ip = fopen(pblimg.rcw_nm, "rb");
+ if (fp_rcw_pbi_ip == NULL) {
+ printf("%s: Error in opening the rcw file: %s\n",
+ __func__, pblimg.rcw_nm);
+ goto exit_main;
+ }
+
+ fp_rcw_pbi_op = fopen(pblimg.imagefile, "wb+");
+ if (fp_rcw_pbi_op == NULL) {
+ printf("%s: Error opening the input file: %s\n",
+ __func__, pblimg.imagefile);
+ goto exit_main;
+ }
+
+ printf("\nInput Boot Source: %s\n", boot_src_string[pblimg.boot_src]);
+ printf("Input RCW File: %s\n", pblimg.rcw_nm);
+ printf("Input BL2 Binary File: %s\n", pblimg.sec_imgnm);
+ printf("Input load address for BL2 Binary File: 0x%x\n", pblimg.addr);
+
+ printf("Chassis Type: %d\n", pblimg.chassis);
+ switch (pblimg.chassis) {
+ case CHASSIS_2:
+ if (fread(&word, sizeof(word), NUM_MEM_BLOCK, fp_rcw_pbi_ip)
+ != NUM_MEM_BLOCK) {
+ printf("%s: Error in reading word from the rcw file.\n",
+ __func__);
+ goto exit_main;
+ }
+ while (BYTE_SWAP_32(word) != 0x08610040) {
+ if (BYTE_SWAP_32(word) == 0x09550000
+ || BYTE_SWAP_32(word) == 0x000f400c) {
+ break;
+ }
+ if (fwrite(&word, sizeof(word), NUM_MEM_BLOCK,
+ fp_rcw_pbi_op) != NUM_MEM_BLOCK) {
+ printf("%s: [CH2] Error in Writing PBI Words\n",
+ __func__);
+ goto exit_main;
+ }
+ if (fread(&word, sizeof(word), NUM_MEM_BLOCK,
+ fp_rcw_pbi_ip) != NUM_MEM_BLOCK) {
+ printf("%s: [CH2] Error in Reading PBI Words\n",
+ __func__);
+ goto exit_main;
+ }
+ }
+
+ if (bootptr_flag == true) {
+ /* Add command to set boot_loc ptr */
+ ret = add_boot_ptr_cmd(fp_rcw_pbi_op);
+ if (ret != SUCCESS) {
+ goto exit_main;
+ }
+ }
+
+ /* Write acs write commands to output file */
+ ret = add_cpy_cmd(fp_rcw_pbi_op);
+ if (ret != SUCCESS) {
+ goto exit_main;
+ }
+
+ /* Add stop command after adding pbi commands
+ * For Chasis 2.0 platforms it is always CRC &
+ * Stop command
+ */
+ flag_stop_cmd = CRC_STOP_COMMAND;
+ ret = add_pbi_stop_cmd(fp_rcw_pbi_op, flag_stop_cmd);
+ if (ret != SUCCESS) {
+ goto exit_main;
+ }
+
+ break;
+
+ case CHASSIS_3:
+ case CHASSIS_3_2:
+ if (fread(&word, sizeof(word), NUM_MEM_BLOCK, fp_rcw_pbi_ip)
+ != NUM_MEM_BLOCK) {
+ printf("%s: Error reading PBI Cmd.\n", __func__);
+ goto exit_main;
+ }
+ while (word != 0x808f0000 && word != 0x80ff0000) {
+ pbl_size++;
+ /* 11th words in RCW has PBL length. Update it
+ * with new length. 2 comamnds get added
+ * Block copy + CCSR Write/CSF header write
+ */
+ if (pbl_size == 11) {
+ word_1 = (word & PBI_LEN_MASK)
+ + (PBI_LEN_ADD << 20);
+ word = word & ~PBI_LEN_MASK;
+ word = word | word_1;
+ }
+ /* Update the CRC command */
+ /* Check load command..
+ * add a check if command is Stop with CRC
+ * or stop without checksum
+ */
+ if (pbl_size == 35) {
+ word = crypto_calculate_checksum(fp_rcw_pbi_op,
+ NUM_RCW_WORD - 1);
+ if (word == FAILURE) {
+ goto exit_main;
+ }
+ }
+ if (fwrite(&word, sizeof(word), NUM_MEM_BLOCK,
+ fp_rcw_pbi_op) != NUM_MEM_BLOCK) {
+ printf("%s: [CH3] Error in Writing PBI Words\n",
+ __func__);
+ goto exit_main;
+ }
+ if (fread(&word, sizeof(word), NUM_MEM_BLOCK,
+ fp_rcw_pbi_ip) != NUM_MEM_BLOCK) {
+ printf("%s: [CH3] Error in Reading PBI Words\n",
+ __func__);
+ goto exit_main;
+ }
+
+ if (word == CRC_STOP_CMD_ARM_CH3) {
+ flag_stop_cmd = CRC_STOP_COMMAND;
+ } else if (word == STOP_CMD_ARM_CH3) {
+ flag_stop_cmd = STOP_COMMAND;
+ }
+ }
+ if (bootptr_flag == true) {
+ /* Add command to set boot_loc ptr */
+ ret = add_boot_ptr_cmd(fp_rcw_pbi_op);
+ if (ret != SUCCESS) {
+ printf("%s: add_boot_ptr_cmd return failure.\n",
+ __func__);
+ goto exit_main;
+ }
+ }
+
+ /* Write acs write commands to output file */
+ ret = add_blk_cpy_cmd(fp_rcw_pbi_op, args);
+ if (ret != SUCCESS) {
+ printf("%s: Function add_blk_cpy_cmd return failure.\n",
+ __func__);
+ goto exit_main;
+ }
+
+ /* Add stop command after adding pbi commands */
+ ret = add_pbi_stop_cmd(fp_rcw_pbi_op, flag_stop_cmd);
+ if (ret != SUCCESS) {
+ goto exit_main;
+ }
+
+ break;
+
+ default:
+ printf("%s: Unknown chassis type.\n",
+ __func__);
+ }
+
+ if (ret == SUCCESS) {
+ printf("Output file successfully created with name: %s\n\n",
+ pblimg.imagefile);
+ }
+
+exit_main:
+ if (fp_rcw_pbi_op != NULL) {
+ fclose(fp_rcw_pbi_op);
+ }
+ if (fp_rcw_pbi_ip != NULL) {
+ fclose(fp_rcw_pbi_ip);
+ }
+
+ return ret;
+}
diff --git a/tools/nxp/create_pbl/create_pbl.mk b/tools/nxp/create_pbl/create_pbl.mk
new file mode 100644
index 0000000..b68882e
--- /dev/null
+++ b/tools/nxp/create_pbl/create_pbl.mk
@@ -0,0 +1,52 @@
+#
+# Copyright 2018-2020 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+
+CREATE_PBL ?= ${CREATE_PBL_TOOL_PATH}/create_pbl${BIN_EXT}
+BYTE_SWAP ?= ${CREATE_PBL_PLAT_TOOL_PATH}/byte_swap${BIN_EXT}
+
+HOST_GCC := gcc
+
+#SWAP is required for Chassis 2 platforms - LS102, ls1043 and ls1046 for QSPI
+ifeq (${SOC},ls1046a)
+SOC_NUM := 1046a
+SWAP = 1
+CH = 2
+else ifeq (${SOC},ls1043a)
+SOC_NUM := 1043a
+SWAP = 1
+CH = 2
+else ifeq (${SOC},ls1012a)
+SOC_NUM := 1012a
+SWAP = 1
+CH = 2
+else ifeq (${SOC},ls1088a)
+SOC_NUM := 1088a
+CH = 3
+else ifeq (${SOC},ls2088a)
+SOC_NUM := 2088a
+CH = 3
+else ifeq (${SOC},lx2160a)
+SOC_NUM := 2160a
+CH = 3
+else ifeq (${SOC},ls1028a)
+SOC_NUM := 1028a
+CH = 3
+else
+$(error "Check SOC Not defined in create_pbl.mk.")
+endif
+
+ifeq (${CH},2)
+
+include ${CREATE_PBL_TOOL_PATH}/pbl_ch2.mk
+
+endif #CH2
+
+ifeq (${CH},3)
+
+include ${CREATE_PBL_TOOL_PATH}/pbl_ch3.mk
+
+endif #CH3
diff --git a/tools/nxp/create_pbl/pbl_ch2.mk b/tools/nxp/create_pbl/pbl_ch2.mk
new file mode 100644
index 0000000..e6f1d8b
--- /dev/null
+++ b/tools/nxp/create_pbl/pbl_ch2.mk
@@ -0,0 +1,60 @@
+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+
+CREATE_PBL ?= ${CREATE_PBL_TOOL_PATH}/create_pbl${BIN_EXT}
+BYTE_SWAP ?= ${CREATE_PBL_TOOL_PATH}/byte_swap${BIN_EXT}
+
+HOST_GCC := gcc
+
+.PHONY: pbl
+pbl: ${BUILD_PLAT}/bl2.bin
+ifeq ($(SECURE_BOOT),yes)
+pbl: ${BUILD_PLAT}/bl2.bin
+ifeq ($(RCW),"")
+ ${Q}echo "Platform ${PLAT} requires rcw file. Please set RCW to point to the right RCW file for boot mode ${BOOT_MODE}"
+else
+ # Generate header for bl2.bin
+ $(Q)$(CST_DIR)/create_hdr_isbc --in ${BUILD_PLAT}/bl2.bin --out ${BUILD_PLAT}/hdr_bl2 ${BL2_INPUT_FILE}
+ # Compile create_pbl tool
+ ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" --no-print-directory -C ${CREATE_PBL_TOOL_PATH};\
+ # Add bl2.bin to RCW
+ ${CREATE_PBL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE}\
+ -o ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl ;\
+ # Add header to RCW
+ ${CREATE_PBL} -r ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl -i ${BUILD_PLAT}/hdr_bl2 -b ${BOOT_MODE} -c ${SOC_NUM} \
+ -d ${BL2_HDR_LOC} -e ${BL2_HDR_LOC} -o ${BUILD_PLAT}/bl2_${BOOT_MODE}_sec.pbl -s;\
+ rm ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl
+# Swapping of RCW is required for QSPi Chassis 2 devices
+ifeq (${BOOT_MODE}, qspi)
+ifeq ($(SWAP),1)
+ ${Q}echo "Byteswapping RCW for QSPI"
+ ${BYTE_SWAP} ${BUILD_PLAT}/bl2_${BOOT_MODE}_sec.pbl;
+endif # SWAP
+endif # BOOT_MODE
+ cd ${CREATE_PBL_TOOL_PATH}; ${MAKE} clean ; cd -;
+endif
+else # NON SECURE_BOOT
+ifeq ($(RCW),"")
+ ${Q}echo "Platform ${PLAT} requires rcw file. Please set RCW to point to the right RCW file for boot mode ${BOOT_MODE}"
+else
+ # -a option appends the image for Chassis 3 devices in case of non secure boot
+ ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" --no-print-directory -C ${CREATE_PBL_TOOL_PATH};
+ ${CREATE_PBL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE} \
+ -o ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl ;
+# Swapping of RCW is required for QSPi Chassis 2 devices
+ifeq (${BOOT_MODE}, qspi)
+ifeq ($(SWAP),1)
+ ${Q}echo "Byteswapping RCW for QSPI"
+ ${BYTE_SWAP} ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl;
+endif # SWAP
+endif # BOOT_MODE
+ cd ${CREATE_PBL_TOOL_PATH}; ${MAKE} clean ; cd -;
+endif
+endif # SECURE_BOOT
+
+
+
diff --git a/tools/nxp/create_pbl/pbl_ch3.mk b/tools/nxp/create_pbl/pbl_ch3.mk
new file mode 100644
index 0000000..e9dbfb0
--- /dev/null
+++ b/tools/nxp/create_pbl/pbl_ch3.mk
@@ -0,0 +1,71 @@
+#
+# Copyright 2018-2020 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#
+SHELL=/bin/bash
+
+CREATE_PBL ?= ${CREATE_PBL_TOOL_PATH}/create_pbl${BIN_EXT}
+BYTE_SWAP ?= ${CREATE_PBL_TOOL_PATH}/byte_swap${BIN_EXT}
+
+HOST_GCC := gcc
+
+BL2_SRC_OFFSET ?= 0x9000
+BL2_HDR_SRC_OFFSET ?= 0x5000
+bl2_hdr_loc=$(shell echo $$(( $(BL2_HDR_SRC_OFFSET) / 1024 )))
+bl2_loc=$(shell echo $$(( $(BL2_SRC_OFFSET) / 1024 )))
+
+.PHONY: pbl
+pbl: ${BUILD_PLAT}/bl2.bin
+ifeq ($(SECURE_BOOT),yes)
+pbl: ${BUILD_PLAT}/bl2.bin
+ifeq ($(RCW),"")
+ ${Q}echo "Platform ${PLAT} requires rcw file. Please set RCW to point to the right RCW file for boot mode ${BOOT_MODE}"
+else
+ # Generate header for bl2.bin
+ $(Q)$(CST_DIR)/create_hdr_isbc --in ${BUILD_PLAT}/bl2.bin --out ${BUILD_PLAT}/hdr_bl2 ${BL2_INPUT_FILE}
+
+ # Compile create_pbl tool
+ ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" --no-print-directory -C ${CREATE_PBL_TOOL_PATH};\
+
+ # Add Block Copy command for bl2.bin to RCW
+ ${CREATE_PBL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE}\
+ -o ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl -f ${BL2_SRC_OFFSET};\
+
+ # Add Block Copy command and Load CSF header command to RCW
+ ${CREATE_PBL} -r ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl -i ${BUILD_PLAT}/hdr_bl2 -b ${BOOT_MODE} -c ${SOC_NUM} \
+ -d ${BL2_HDR_LOC} -e ${BL2_HDR_LOC} -s -f ${BL2_HDR_SRC_OFFSET} \
+ -o ${BUILD_PLAT}/rcw_sec.pbl
+
+ # Sign and add "Load Security Header command to PBI commands
+ $(Q)$(CST_DIR)/create_hdr_pbi --out ${BUILD_PLAT}/bl2_${BOOT_MODE}_sec.pbl --in ${BUILD_PLAT}/rcw_sec.pbl ${PBI_INPUT_FILE}
+
+ # Append the bl2_hdr to the RCW image
+ @echo "${bl2_hdr_loc}"
+ dd if=${BUILD_PLAT}/hdr_bl2 of=${BUILD_PLAT}/bl2_${BOOT_MODE}_sec.pbl bs=1K seek=${bl2_hdr_loc}
+
+ # Append the bl2.bin to the RCW image
+ @echo "${bl2_loc}"
+ dd if=${BUILD_PLAT}/bl2.bin of=${BUILD_PLAT}/bl2_${BOOT_MODE}_sec.pbl bs=1K seek=${bl2_loc}
+
+ rm ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl
+ cd ${CREATE_PBL_TOOL_PATH}; ${MAKE} clean ; cd -;
+endif
+else #SECURE_BOOT
+ifeq ($(RCW),"")
+ ${Q}echo "Platform ${PLAT} requires rcw file. Please set RCW to point to the right RCW file for boot mode ${BOOT_MODE}"
+else
+ ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" --no-print-directory -C ${CREATE_PBL_TOOL_PATH};
+
+ # Add Block Copy command and populate boot loc ptrfor bl2.bin to RCW
+ ${CREATE_PBL} -r ${RCW} -i ${BUILD_PLAT}/bl2.bin -b ${BOOT_MODE} -c ${SOC_NUM} -d ${BL2_BASE} -e ${BL2_BASE} \
+ -o ${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl -f ${BL2_SRC_OFFSET};
+
+ # Append the bl2.bin to the RCW image
+ @echo "bl2_loc is ${bl2_offset}"
+ dd if=${BUILD_PLAT}/bl2.bin of=${BUILD_PLAT}/bl2_${BOOT_MODE}.pbl bs=1K seek=${bl2_loc}
+
+ cd ${CREATE_PBL_TOOL_PATH}; ${MAKE} clean ; cd -;
+endif
+endif # SECURE_BOOT
diff --git a/tools/nxp/plat_fiptool/plat_def_uuid_config.c b/tools/nxp/plat_fiptool/plat_def_uuid_config.c
new file mode 100644
index 0000000..fdb4b93
--- /dev/null
+++ b/tools/nxp/plat_fiptool/plat_def_uuid_config.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stddef.h>
+
+#include <firmware_image_package.h>
+
+#include "tbbr_config.h"
+
+toc_entry_t plat_def_toc_entries[] = {
+ /* DDR PHY firmwares */
+ {
+ .name = "DDR UDIMM PHY IMEM 1d FW",
+ .uuid = UUID_DDR_IMEM_UDIMM_1D,
+ .cmdline_name = "ddr-immem-udimm-1d"
+ },
+ {
+ .name = "DDR UDIMM PHY IMEM 2d FW",
+ .uuid = UUID_DDR_IMEM_UDIMM_2D,
+ .cmdline_name = "ddr-immem-udimm-2d"
+ },
+ {
+ .name = "DDR UDIMM PHY DMEM 1d FW",
+ .uuid = UUID_DDR_DMEM_UDIMM_1D,
+ .cmdline_name = "ddr-dmmem-udimm-1d"
+ },
+ {
+ .name = "DDR UDIMM PHY DMEM 2d FW",
+ .uuid = UUID_DDR_DMEM_UDIMM_2D,
+ .cmdline_name = "ddr-dmmem-udimm-2d"
+ },
+ {
+ .name = "DDR RDIMM PHY IMEM 1d FW",
+ .uuid = UUID_DDR_IMEM_RDIMM_1D,
+ .cmdline_name = "ddr-immem-rdimm-1d"
+ },
+ {
+ .name = "DDR RDIMM PHY IMEM 2d FW",
+ .uuid = UUID_DDR_IMEM_RDIMM_2D,
+ .cmdline_name = "ddr-immem-rdimm-2d"
+ },
+ {
+ .name = "DDR RDIMM PHY DMEM 1d FW",
+ .uuid = UUID_DDR_DMEM_RDIMM_1D,
+ .cmdline_name = "ddr-dmmem-rdimm-1d"
+ },
+ {
+ .name = "DDR RDIMM PHY DMEM 2d FW",
+ .uuid = UUID_DDR_DMEM_RDIMM_2D,
+ .cmdline_name = "ddr-dmmem-rdimm-2d"
+ },
+ {
+ .name = "FUSE PROV FW",
+ .uuid = UUID_FUSE_PROV,
+ .cmdline_name = "fuse-prov"
+ },
+ {
+ .name = "FUSE UPGRADE FW",
+ .uuid = UUID_FUSE_UP,
+ .cmdline_name = "fuse-upgrade"
+ },
+
+ /* Key Certificates */
+ {
+ .name = "DDR Firmware key certificate",
+ .uuid = UUID_DDR_FW_KEY_CERT,
+ .cmdline_name = "ddr-fw-key-cert"
+ },
+
+ /* Content certificates */
+ {
+ .name = "DDR UDIMM Firmware content certificate",
+ .uuid = UUID_DDR_UDIMM_FW_CONTENT_CERT,
+ .cmdline_name = "ddr-udimm-fw-cert"
+ },
+ {
+ .name = "DDR RDIMM Firmware content certificate",
+ .uuid = UUID_DDR_RDIMM_FW_CONTENT_CERT,
+ .cmdline_name = "ddr-rdimm-fw-cert"
+ },
+
+ {
+ .name = NULL,
+ .uuid = { {0} },
+ .cmdline_name = NULL,
+ }
+};
diff --git a/tools/nxp/plat_fiptool/plat_fiptool.mk b/tools/nxp/plat_fiptool/plat_fiptool.mk
new file mode 100644
index 0000000..ca2962a
--- /dev/null
+++ b/tools/nxp/plat_fiptool/plat_fiptool.mk
@@ -0,0 +1,33 @@
+#
+# Copyright (c) 2021, NXP. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Name of the platform defined source file name,
+# which contains platform defined UUID entries populated
+# in the plat_def_toc_entries[].
+PLAT_DEF_UUID_CONFIG_FILE_NAME := plat_def_uuid_config
+
+PLAT_DEF_UUID_CONFIG_FILE_PATH := ../nxp/plat_fiptool
+
+PLAT_DEF_OID := yes
+PLAT_DEF_UUID := yes
+PLAT_DEF_UUID_OID_CONFIG_PATH := ../../plat/nxp/common/fip_handler/common
+
+
+INCLUDE_PATHS += -I${PLAT_DEF_UUID_OID_CONFIG_PATH} \
+ -I./
+# Clean the stale object file.
+$(shell rm ${PLAT_DEF_UUID_CONFIG_FILE_PATH}/${PLAT_DEF_UUID_CONFIG_FILE_NAME}.o)
+
+ifeq (${PLAT_DEF_OID},yes)
+HOSTCCFLAGS += -DPLAT_DEF_OID
+endif
+
+ifeq (${PLAT_DEF_UUID},yes)
+HOSTCCFLAGS += -DPLAT_DEF_FIP_UUID
+PLAT_OBJECTS += ${PLAT_DEF_UUID_CONFIG_FILE_PATH}/${PLAT_DEF_UUID_CONFIG_FILE_NAME}.o
+endif
+
+OBJECTS += ${PLAT_OBJECTS}
diff --git a/tools/stm32image/stm32image.c b/tools/stm32image/stm32image.c
index 41024e2..fb1dee0 100644
--- a/tools/stm32image/stm32image.c
+++ b/tools/stm32image/stm32image.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2021, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -45,8 +45,6 @@
uint8_t binary_type;
};
-static struct stm32_header stm32image_header;
-
static void stm32image_default_header(struct stm32_header *ptr)
{
if (!ptr) {
@@ -54,10 +52,9 @@
}
ptr->magic_number = HEADER_MAGIC;
- ptr->header_version[VER_MAJOR] = HEADER_VERSION_V1;
ptr->option_flags = HEADER_DEFAULT_OPTION;
- ptr->ecdsa_algorithm = 1;
- ptr->version_number = 0;
+ ptr->ecdsa_algorithm = __cpu_to_le32(1);
+ ptr->version_number = __cpu_to_le32(0);
ptr->binary_type = TF_BINARY_TYPE;
}
@@ -105,27 +102,33 @@
}
static void stm32image_set_header(void *ptr, struct stat *sbuf, int ifd,
- uint32_t loadaddr, uint32_t ep, uint32_t ver)
+ uint32_t loadaddr, uint32_t ep, uint32_t ver,
+ uint32_t major, uint32_t minor)
{
struct stm32_header *stm32hdr = (struct stm32_header *)ptr;
stm32image_default_header(stm32hdr);
+ stm32hdr->header_version[VER_MAJOR] = major;
+ stm32hdr->header_version[VER_MINOR] = minor;
stm32hdr->load_address = __cpu_to_le32(loadaddr);
stm32hdr->image_entry_point = __cpu_to_le32(ep);
stm32hdr->image_length = __cpu_to_le32((uint32_t)sbuf->st_size -
sizeof(struct stm32_header));
- stm32hdr->image_checksum = stm32image_checksum(ptr, sbuf->st_size);
+ stm32hdr->image_checksum =
+ __cpu_to_le32(stm32image_checksum(ptr, sbuf->st_size));
stm32hdr->version_number = __cpu_to_le32(ver);
}
static int stm32image_create_header_file(char *srcname, char *destname,
uint32_t loadaddr, uint32_t entry,
- uint32_t version)
+ uint32_t version, uint32_t major,
+ uint32_t minor)
{
int src_fd, dest_fd;
struct stat sbuf;
unsigned char *ptr;
+ struct stm32_header stm32image_header;
dest_fd = open(destname, O_RDWR | O_CREAT | O_TRUNC | O_APPEND, 0666);
if (dest_fd == -1) {
@@ -177,11 +180,12 @@
dest_fd, 0);
if (ptr == MAP_FAILED) {
- fprintf(stderr, "Can't read %s\n", srcname);
+ fprintf(stderr, "Can't write %s\n", destname);
return -1;
}
- stm32image_set_header(ptr, &sbuf, dest_fd, loadaddr, entry, version);
+ stm32image_set_header(ptr, &sbuf, dest_fd, loadaddr, entry, version,
+ major, minor);
stm32image_print_header(ptr);
@@ -193,9 +197,11 @@
int main(int argc, char *argv[])
{
int opt, loadaddr = -1, entry = -1, err = 0, version = 0;
+ int major = HEADER_VERSION_V1;
+ int minor = 0;
char *dest = NULL, *src = NULL;
- while ((opt = getopt(argc, argv, ":s:d:l:e:v:")) != -1) {
+ while ((opt = getopt(argc, argv, ":s:d:l:e:v:m:n:")) != -1) {
switch (opt) {
case 's':
src = optarg;
@@ -204,17 +210,23 @@
dest = optarg;
break;
case 'l':
- loadaddr = strtol(optarg, NULL, 16);
+ loadaddr = strtol(optarg, NULL, 0);
break;
case 'e':
- entry = strtol(optarg, NULL, 16);
+ entry = strtol(optarg, NULL, 0);
break;
case 'v':
- version = strtol(optarg, NULL, 10);
+ version = strtol(optarg, NULL, 0);
+ break;
+ case 'm':
+ major = strtol(optarg, NULL, 0);
+ break;
+ case 'n':
+ minor = strtol(optarg, NULL, 0);
break;
default:
fprintf(stderr,
- "Usage : %s [-s srcfile] [-d destfile] [-l loadaddr] [-e entry_point]\n",
+ "Usage : %s [-s srcfile] [-d destfile] [-l loadaddr] [-e entry_point] [-m major] [-n minor]\n",
argv[0]);
return -1;
}
@@ -241,7 +253,7 @@
}
err = stm32image_create_header_file(src, dest, loadaddr,
- entry, version);
+ entry, version, major, minor);
return err;
}
